1987_ALS_AS_Logic_Databook 1987 ALS AS Logic Databook

User Manual: 1987_ALS_AS_Logic_Databook

Open the PDF directly: View PDF PDF.
Page Count: 666

Download1987_ALS_AS_Logic_Databook 1987 ALS AS Logic Databook
Open PDF In BrowserView PDF
~

National
Semiconductor
Corporation

400005

ALS/ AS Logic
DATABOOK

, ,

, "",

Introduction to Bipolar Logic
Advanced Low Power Schottky
Advanced Schottky
Physical Dimensions!Appendices
iii

II
g
II
II

TRADEMARKS
Following is the most current list of National Semiconductor Corporation's trademarks and registered trademarks.
Abuseable™
AnadigTM
ANS-R-TRANTM
APPSTM
Auto-Chem Deflasher™
BI-FETTM
BI-FET IITM
BI-L1NETM
BIPLANTM
BLCTM
BLXTM
Brite-Lite™
BTLTM
CheckTrackTM
CIMTM
CIMBUSTM
Cloc~ChekTM

r

'#

COMBOTM
COMBO ITM
COMBO IITM
COPSTM microcontrollers
Datacheckerl!l
DENSPAKTM
DIBTM
Digitalkerl!l
DISCERNTM
DISTILLTM
DNRI!l
DPVMTM
ELSTARTM

E-Z-UNKTM
5-Star Service™
GENIXTM
GNXTM
HEX 3000TM
HPCTM
ICMTM
INFOCHEXTM
Integral ISETM
IntelisplayTM
iSETM
ISE/OSTM
ISE/08TM
ISE/1STM
ISE32TM
KeyScan™
LMCMOSTM
M2CMOSTM
Macrobus™
Macrocomponent™

Naked-8™
National~

NAX 800TM
Nitride PIUS™
Nitride Plus Oxide™
NMLTM
NOBUSTM
NSC800TM
NSX-1STM
NS-XC-1STM
NURAMTM
OXISSTM
P2CMOSTM
Perfect WatchTM
Pharm~ChekTM

PLANTM
Polycraft™
POSitalker™
Power & Control™
QUAD3000TM
QUIKLOOKTM
RATTM
RTX1STM
SABRTM

Mea~ChekTM

Microbus™ data bus
MICRO-DACTM
p.talker™
Microtalker™
MICROWIRETM
MICROWIRE/PLUSTM
MOLETM
MSTTM

Scrip~ChekTM

SCXTM
SERIES/800TM
Series 3000™
Series 32000~

Shelf,....ChekTM
SPIRETM
STARTM
StarlinkTM
STARPLEXTM
STARPLEX IITM
SuperChipTM
SuperScriptTM
SYS32TM
TapePak™
TDSTM
TeleGate™
The National Anthem@
Tim~ChekTM

TINATM
TLCTM
Trapezoidal™
TRI-CODETM
TRI-POLYTM
TRI-SAFETM
TRI-STATEI!l
TURBOTRANSCEIVERTM
VIPTM
VR32TM
XMOSTM
XPUTM
Z STARTM
883B/RETSTM
883S/RETSTM

LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions
for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

National Semiconductor Corporation 2900 Semiconductor Drive, P.O. Box 58090, Santa Clara, California 95052-8090 (408) 721-5000
TWX (910) 339-9240
National does not assume any responsibility for use of any circuiby described, no circuit patent licenses are implied, and National reserves the right, at any time
without notice.

to change said circuitry or specifications.

iv

Table of Contents
Section 1 Introduction to Bipolar Logic
Guide to Bipolar Logic Families Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IC Device Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-363 Designing with TTL. .. .. . .. .... .. . . ... . .... .. ...... . .. .. .. .... .. .. . . ... .
AN-372 Designer's Encyclopedia of Bipolar One-Shots. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-476 Guide to ALS and AS .. .. ...... .. .. .. .. .. . ..... . .. .. .. ... .. .. .. .. .. .... .
Functional Index/Selection Guide. ......... .. .. .. . ...... .. .. .. ... .... .. .... .... .
Glossary of Terms. .... .. . .. ..... .... .. ..... .. .. . .. .... ... .. .. .. .... .. .... .... .
Test Waveforms. ..............................................................

1-3
1-8
1-16
1-19
1-35
1-44
1-63
1-68

Section 2 Advanced Low Power Schottky
Buffers/Drivers
DM54174ALS28A Quad 2-lnput NOR Buffers.... .. .. ....... .. .. ... .. .... ..... ... .
DM54174ALS33A Quad 2-lnput NOR Buffers with Open-COllector Outputs. .. ........ .
DM54174ALS37A Quad 2-lnput NAND Buffers....................................
DM54174ALS38A Quad 2-lnput NAND Buffers with Open-Collector Outputs ..........
DM54174ALS40A Dual4-lnput NAND Buffers. ... .. .. .. .. .. .. . .. .. .. .... .. ... .... .
DM54174ALS240A Octal TRI-STATE Inverting Buffers/Line Drivers/Line Receivers...
DM54174ALS241A Octal TRI-STATE Buffers/Line Drivers/Line Receivers...........
DM54174ALS244A Octal TRI-STATE Bus Driver..................................
DM54174ALS465A Octal TRI-STATE Buffers/Bus Drivers ........... :... .... .. .....
DM54174ALS466A Octal TRI-STATE Inverting Buffers/Bus Drivers. .. .... .... .. .....
DM54174ALS467A Octal TRI-STATE Buffers/Bus Drivers..........................
DM54174ALS468A Octal TRI-STATE Inverting Buffers/Bus Drivers..................
DM54174ALS540 Octal Inverting Buffers and Line Drivers with TRI-STATE Outputs....
DM5417 4ALS541 Octal Buffers and Line Drivers with TRI-STATE Outputs . . . . . . . . . . ..
DM54174ALS804A Hex 2-lnput NAND Driver. .. . .. .. .. .. ... .. .. . .. .. ...... ... ....
DM54174ALS805A Hex 2-lnput NOR Driver.. ... . .. .... .. ... .... . .. ...... .. .......
DM54174ALS808A Hex 2-lnput AND Driver.. ... . .. .. .. ..... .. .. . .. .... .... .......
DM54174ALS832A Hex 2-lnput OR Drivers.. . .. . .. .. .. ... .. .. .. . .. .. .. .. .. .......
DM54174ALS1000A Quad 2-lnput NAND Buffer. . .. . ...... .. . .... .. .... .... .......
DM54174ALS1002A Quad 2-lnput Positive NOR Buffer.. . .. .. . .... .. .... ...........
DM5417 4ALS 1003A Quad 2-lnput NAN D Buffer with Open-Collector Outputs .... . . . ..
DM54174ALS1004 Hex Inverting Drivers.........................................
DM54174ALS1005 Hex Inverting Drivers with Open-Collector Outputs..... ...... .....
DM54174ALS1008A Quad 2-lnput AND Buffers.. .. . .. .. ... .. . .. .. .. .. .. .. ........
DM54/74ALS1010A Triple 3-lnput NAND Buffers. .. . .. .... . .. . .. .. ...... .. ........
DM54174ALS1011A Triple 3-lnput AND Buffers.. ... ... .. .. ... .. ... .. ......... ....
DM54174ALS1020A Dual4-lnput NAND Buffers.. ... ... .. .. . .. ... .. .. .... .. .......
DM54174ALS1032A Quad 2-lnput OR Buffers.....................................
DM54174ALS1034 Hex Non-Inverting Buffers.... . .. . .. .. .. . .... . .. .... .... .......
DM54174ALS1035 Hex Non-Inverting Buffers with Open-Collector Outputs.... .. .....
DM54174ALS1240 Octal TRI-STATE Inverting Bus Drivers/Receivers.. .. . . .. ........
DM54174ALS1241A Octal TRI-STATE Bus Drivers/Receivers......................
DM54174ALS1244A Octal TRI-STATE Bus Drivers................................
DM54174ALS2541 Octal Buffers and MOS Line Drivers with TRI-STATE Outputs.. ....
Comparators
DM5417 4ALS518 Octal 8-Bit Identity Comparator with Open-Collector Outputs . . . . . . . .
DM5417 4ALS519 Octal 8-Bit Identity Comparator with Open-Collector Outputs. . . . . . . .
DM5417 4ALS520 Octal 8-Bit Identity Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM5417 4ALS521 Octal 8-Bit Identity Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM5417 4ALS522 Octal 8-Bit Identity Comparator with Open-Collector Outputs. . . . . . ..
DM54174ALS689 8-Bit Comparator.... . .... ... . .. . .. . .. .. . ... .. ... ... . .. .... ....
v

2-42
2-48
2-50
2-52
2-54
2-129
2-129
2-137
2-176
2-176
2-176
2-176
2-192
2-195
2-250
2-252
2-254
2-261
2-279
2-281
2-283
2-285
2-287
2-289
2-291
2-293
2-295
2-297
2-299
2-301
2-303
2-303
2-311
2-320
2-180
2-180
2-180
2-180
2-180
2-247

Table of Contents (Continued)
Counters
DM5417 4ALS160B Synchronous 4-Bit Decade Counter with Asynchronous Clear. . . . . .
DM5417 4ALS161 B Synchronous 4-Bit Binary Counter with Asynchronous Clear . . . . . . .
DM54174ALS162B Synchronous 4-Bit Decade Counter with Asynchronous Clear. . . . . .
DM54174ALS163B Synchronous 4-Bit Binary Counter with Asynchronous Clear .... '.' .
DM54174ALS168B Synchronous 4-Bit Up/Down Decade Counter. . . . . . . . . . . . . .. . . . .
DM54/74ALS169B Synchronous 4-Bit Up/Down Binary Counter. ... .. ..... ... . .. ...
DM54/74ALS190 Synchronous 4-Bit Up/Down Decade Counter. ... ....... ... ... ...
DM54174ALS191 Synchronous 4-Bit Up/Down Binary Counter. . . . . . . . . . . . . . . . . . . . ..
DM5417 4ALS 192 Synchronous 4-Bit Up/ Down Decade Counter with Clear and Dual
Clock ..............................'. .. ... .. ... .. .. .. . .. . . .. .... ... ... ......
DM5417 4ALS193 Synchronous 4-Bit Up/Down Binary Counter with Clear and Dual
Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54174ALS390 Dual4-Bit Decade Counters....................................
DM54174ALS590 8-Bit Binary Counter with Output Registers. . . . . . . . . . . . . . . . . . . . . . ..
Decoders/Encoders
DM54174ALS131 3 to 8 Line Decoder/Demultiplexer with Address Register... ..... ..
DM54174ALS137 3 to 8 Line Decoder/Demultiplexer with Address Latches. ... .. ... ..
DM54174ALS138 3 to 8 Line Decoder/Demultiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flip-Flops
DM54174ALS74A Dual D Positive-Edge-Triggered Flip-Flops with Preset and Clear. ...
DM54174ALS109A Dual Positive-Edge-Triggered J-K Flip-Flops with
Preset and Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/7 4ALS 174 Hex D Flip-Flops with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54174ALS175 Quad D Flip-Flops with Clear and Complementary Outputs. ... .. .. ..
DM54174ALS273 Octal D-Type Edge-Triggered Flip-Flops with Clear................
DM54174ALS374 Octal TRI-STATE D-Type Edge-Triggered Flip-Flops... ... ... ......
DM54174ALS534 Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs...
DM54174ALS564A Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs..
DM54174ALS57 4A Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs .. '
DM54174ALS576A Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs..
DM54174ALS874B Dual4-Bit D-Type Edged-Triggered Flip-Flops with TRI-STATE
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54174ALS876A Dual4-Bit D-Type Edged-Triggered Flip-Flops with TRI-STATE
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gates/Inverters
DM54174ALSOOA Quad 2-lnput NAND Gates.. . .. .. . .. . . ... .. ........ ......... ...
DM54174ALS01 Quad 2-lnput NAND Gates with Open-Collector Outputs. ... ... ... .. .
DM54/74ALS02 Quad 2-lnput NOR Gates. ... .. ... ... .. . .... .. .... ..... .... .. .. . .
DM54174ALS03B Quad 2-lnput NAND Gates with Open-Collector Outputs. ..... ... ..
DM54174ALS04B Hex Inverters. ........ . ... .. ... ... .. . .. .. .. . .. . .. .• .. . .. .. .. . .
DM5417 4ALS05A Hex Inverters with Open-Collector Outputs .......................
DM5417 4ALS08 Quad 2-lnput AND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54174ALS09 Quad 2-lnput AND Gates with Open-Collector Outputs ..............
DM54174ALS10A Triple 3-lnput NAND Gates.. ... .. . .. . . ... ... ......... ..........
DM54174ALS11A Triple 3-lnput AND Gates. . .. ... ... .. . .. .. .. . .. ... . ... ... ... .. .
DM54174ALS12A Triple 3-lnput NAND Gates with Open-Collector Outputs. . . . . . . . . . .
DM54174ALS13 Dual4-lnput NAND Gates with Schmitt Trigger Inputs. . . . . . . . . . . . . . .
DM54174ALS14 Hex Inverters with Schmitt Trigger Inputs. .. . .. .. .... .. .. ... .. ... ..
DM54/74ALS15A Triple 3-lnput AND Gates with Open-Collector Outputs. .. ........ ..
DM54174ALS20A Dual4-lnput NAND Gates......................................
vi

2-89
2-89
2-89
2-89
2-106
2-106
2-115
2-115
2-122
2-122
2-172
2-222
2-64
2-73
2-76
2-56
2-61
2-111
2-111
2-154
2-168
2-188
2-202
2-210
2-214
2-267
2-271
'2-5
2-7
2-9
2-11
2-13
2-15
2-17
2-19
2-21
2-23
2-25
2-27
2-29
2-32
2-34

Table of Contents (Continued)
DM54174ALS21A Dual4-lnput AND Gates..... .. ..... .. .... .... .. .... .......... .
DM54174ALS22B Dual4-lnput NAND Gates with Open-Collector Outputs. . . . . . . . . .. .
DM54174ALS27 Triple 3-lnput NOR Gates ....................... " .............. .
DM54174ALS30A 8-lnput NAND Gate.. . .. ..... .. .. ..... .. .. .. ........... .. .....
DM54174ALS32 Quad 2-lnput OR Gates. .. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .. .
DM54174ALS86 Quad 2-lnput Exclusive-OR Gates. ... .... .. .. ... .... .. ...... .....
DM54174ALS132 Quad 2-lnput NAND Gates with Schmitt Trigger Inputs...... .. .....
DM54174ALS133 13-lnput NAND Gate... ... ......... .... .. .... ............. .....
DM54174ALS136 Quad 2-lnputs Exclusive-OR Gates with Open-Collector Outputs ....
DM54174ALS810 Quad 2-lnput Exclusive-NOR Gates....... .. .............. ... ....
DM54174ALS811 Quad 2-lnput Exclusive-NOR Gates with Open-Collector Outputs....

2-36
2-38
2-40
2-44
2-46
2-59
2-67
2-69
2-71
2-256
2-259

Latches
DM54174ALS373 Octal D-Type TRI-STATE Transparent Latches ................. '"
DM5417 4ALS533 Octal D-Type Transparent Latches with TRI-STATE Outputs. . . . . . . .
DM54174ALS563A Octal D-Type Transparent Latches with TRI-STATE Outputs.... ...
DM54174ALS573B Octal D-Type Transparent Latches with TRI-STATE Outputs. . . . .. .
DM5417 4ALS580A Octal D-Type Transparent Latches with TRI-STATE Outputs. . . . . ..
DM54174ALS873B Dual4-Bit D-Type Transparent Latches with TRI-STATE Outputs.. .
DM54174ALS880A Dual4-Bit D-Type Transparent Latches with TRI-STATE Outputs. . .

2-164
2-184
2-198
2-206
2-218
2-263
2-275

Multiplexers/Demultiplexers
DM54174ALS151 1 of 8 Line Data Selector/Multiplexer..... .. ...... . ..... .. ... ....
DM54174ALS153 Dual 1 of 4 Line Data Selectors/Multiplexer....... .. .. ..... .. .....
DM54174ALS157 Quad 1 of 2 Line Data Selectors/Multiplexers........... . .. ... ....
DM5417 4ALS158 Quad 1 of 2 Line Data Selectors/Multiplexers. . . . . . . . . . . . . . . . . . . . .
DM54174ALS251 TRI-STATE 1 of 8 Line Data Selector/Multiplexer........ . .. .. . ....
DM54174ALS253 TRI-STATE Dual 1 of 4 Line Data Selectors/Multiplexers . . . . . . . . . ..
DM54174ALS257 Quad TRI-STATE 1 of 2 Line Data Selectors/Multiplexers ....... '"
DM54174ALS258 Quad TRI-STATE 1 of 2 Line Inverting Data Selectors/Multiplexers..
DM54174ALS352 Dual 1 of 4 Line Inverting Data Selectors/Multiplexers. . . . . . . . . . . . ..
DM54174ALS353 TRI-STATE Dual 1 of 4 Line Data Selectors/Multiplexers . . . . . . . . . . .

2-79
2-83
2-86
2-86
2-143
2-147
2-150
2-150
2-158
2-161

Registers
DM54174ALS165 8-Bit Parallel In/Serial Out Shift Register ... . . . . . . . . . . . . . . . . . . . . . .
DM54174ALS166 8-Bit Parallel Load Shift Registers. .. .. ........ .... .. ... .. .. .....

2-97
2-102

Transceivers
DM54174ALS242B Quad TRI-STATE Inverting Bus Transceivers........... .. .......
DM54174ALS243A Quad TRI-STATE Bus Transceivers............................
DM54174ALS245A Octal TRI-STATE Bus Transceivers.. ...... .. .. .... ... .. .......
DM54174ALS620A Octal TRI-STATE Bus Transceiver... .............. ... .. .......
DM54174ALS640A Inverting Octal Bus Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54174ALS645A Octal TRI-STATE Bus Transceivers.. ... .. .... ........ .. .......
DM54174ALS646 Octal TRI-STATE Bus Transceivers and Registers.... .... ... ......
DM54/74ALS648 Octal TRI-STATE Inverting Bus Transceivers............ ... ......
DM54174ALS652 Octal TRI-STATE Bus Transceivers and Registers........ .........
DM54174ALS1242 Quad TRI-STATE Inverting Bus Drivers .........................
DM54174ALS1243A Quad TRI-STATE Bus Drivers................................
DM54174ALS1245A TRI-STATE Bus Transceivers................................
DM54174ALS1645A Octal TRI-STATE Bus Transceivers. . . . . . . . . . . . . . . . . . . . . .. .. . .
DM54174ALS2645 Octal TRI-STATE Transceivers ........... :....................
DM54174ALS5245 Octal TRI-STATE Transceivers ....... " .... ...... .... ....... ..
DM54174ALS5620 Octal TRI-STATE Transceivers .............................. "

2-133
2-133
2-140
2-226
2-229
2-232
2-235
2-239
2-243
2-307
2-307
2-314
2-317
2-323
2-326
2-329

vii

Table of Contents (Continued)
Section 3 Advanced Schottky
Arithmetic Functions
DM74AS181B Arithmetic Logic Unit/Function Generators..........................
DM74AS182 Look-Ahead Carry Generators .................................. : . . . .
DM74AS280 9-Bit Parity Generator/Checker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74AS282 Look Ahead Carry Generator with Selectable Carry Inputs. . . . . . . . . . . . . . .
DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port. . . . . . . . . ..
DM74AS881 B 4-Bit Arithmetic Logic Unit/Function Generator. . . . . . . . . . . . . . . . . . . . . . .

3-60
3-69
3-93
3-97
3-102
3-193

Buffers/Drivers
DM74AS230 Octal TRI-STATE Bus Drivers/Receivers
True and Inverting Outputs ............................... , .. .. .. .. . ........ .. .
DM74AS231 Octal TRI-STATE Inverting Bus Drivers/Receivers. ... ... ... .. ..... ....
DM74AS240 Octal TRI-STATE Inverting Buffers/Line Drivers/Line Receivers........ .
DM74AS241 Octal TRI-STATE Buffers/Line Drivers/Line Receivers. .. .. . .......... .
DM74AS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers.... .. .... ..... ..
DM74AS804B Hex 2-lnput NAND Driver...... .. ..... ....... ... .. .. .. .. ...........
DM74AS805B Hex2-lnputNOR Driver...........................................
DM74AS808B Hex 2-lnput AND Driver ......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74AS832B Hex 2-lnput OR Driver ............................................
DM74AS1000A Quad 2-lnput NAND Drivers.... ............ . .... ... ... . ..........
DM74AS1004A Hex Inverting Drivers........ .. ... .. ... .. .. . .... ... ... . ..........
DM74AS1008A Quad 2-lnput AND Drivers... .... ... ....... ... .. .... ... .. .........
DM74AS1032A Quad 2-lnput OR Drivers....... .... .... ..... . .. .. .. .. ............
DM74AS1034A Hex Non-Inverting Drivers...... . ....... .. ... ... .. .. .. . . ..........
DM74AS1036A Quad 2-lnput NOR Drivers........................................
DM74AS1804 Hex 2-lnput NAND Drivers...... .. ... ..... ..... ... ... . .. .. ..... ....
DM74AS1805 Hex2-lnput NOR Drivers..........................................
DM74AS1808 Hex 2-lnput AND Drivers......... ... ..... .. ... ... ... . .. .. .. ... ....
DM74AS1832 Hex 2-lnput OR Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-73
3:73
3-16
3-76
3-76
3-159
3-161
3-163
3-170
3-205
3-207
3-209
3-211
3-213
3-215
3-217
3-219
3-221
3-223

Counters
DM74AS 160 Synchronous 4-Bit Decade Counter with Asynchronous Clear ...........
DM74AS161 Synchronous 4-Bit Binary Counter with Asynchronous Clear. . . . . . . . . . . . .
DM74AS 162 Synchronous 4-Bit Decade Counter with Synchronous Clear. . . . . . . . . . . . .
DM74AS163 Synchronous 4-Bit Binary Counter with Synchronous Clear.. . . ..... .. .. .
DM74AS168A Synchronous 4-Bit Up/Down Decade Counter.. . .. .. .. ... ..... ... .. .
DM74AS169A Synchronous 4-Bit Up/Down Binary Counter. . . . . . . . . . . . . . . . . . . . . . . . .
DM74AS264 Look Ahead Carry Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-42
3-42
3-42
3-42
3-49
3-49
3-88

Flip-Flops
DM74AS74 Dual D Positive-Edge-Triggered Flip-Flops with Preset and Clear. . . . . . . . . .
DM74AS109 Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear. . . . . . .
DM74AS174 Hex D Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74AS175A Quad D Flip-Flops with Clear. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .
DM74AS37 4 Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs. . . . . . . .
DM74AS534 Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs. . . . . . ..
DM74AS57 4 Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs. . . . . . . .
DM74AS575 Octal 0-Type Edge-Triggered Flip-Flops with Synchronous Clear. . . . . . . . .
DM74AS576 Octal D-Type Edge-Triggered Flip-Flops with Inverted Outputs. . . . . . . . . . .
DM74AS577 Octal D-Type Edge-Triggered Flip-Flops
with Inverted Outputs and Synchronous Preset. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . ..
DM7 4AS87 4 Dual 4-Bit D-Type Edge-Triggered Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . ..
viii

3-28
3-33
3-54
3-57
3-110
3-117
3-124
3-127
3-130
3-133
3-176

Table of Contents (Continued)
DM74AS876 Dual4-Bit D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs ... .
DM74AS878 Dual4-Bit D-Type Edge-Triggered Flip-Flops with Synchronous Clear .... .
DM74AS879 Dual4-Bit D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs and
Synchronous Clear ......................................................... .

3-180
3-183
3-186

Gates/Inverters
DM74ASOO Quad 2-lnput NAND Gates .......................................... .
DM74AS02 Quad 2-lnput NOR Gates ........................................... .
DM74AS04 Hex Inverters ...................................................... .
DM74AS08 Quad 2-lnput AND Gates ........................................... .
DM74AS10 Triple 3-lnput NAND Gates .......................................... .
DM74AS11 Triple 3-lnput AND Gates ........................................... .
DM74AS20 Dual4-lnput NAND Gates ........................................... .
DM74AS21 Dual4-lnput AND Gates ............................................ .
DM74AS27 Triple 3-lnput NOR Gates ........................................... .
DM74AS30 8-lnput NAND Gates ............................................... .
DM74AS32 Quad 2-lnput OR Gates ............................................. .
DM74AS34 Hex Non-Inverter .................................................. .
DM74AS86 Quad 2-lnput Exclusive-OR Gates ................................... .
DM74AS136 Quad 2-lnput Exclusive-OR Gates with Open-Collector Outputs ......... .
DM74AS810 Quad 2-lnput Exclusive NOR Gates ................................. .
DM74AS811 Quad 2-lnput Exclusive NOR Gates with Open Collector Outputs ........ .

3-4
3-6
3-8
3-10
3-12
3-14
3-16
3-18
3-20
3-22
3-24
3-26
3-31
3-36
3-165
3-168

Latches
DM74AS373 Octal D-Type Transparent Latches with TRI-STATE Outputs ........... .
DM74AS533 Octal D-Type Transparent Latches with TRI-STATE Outputs ........... .
DM74AS573 Octal D-Type Transparent Latches with TRI-STATE Outputs ........... .
DM74AS580 Octal D-Type Transparent Latches with TRI-STATE Outputs ........... .
DM74AS873 Dual4-Bit D-Type Transparent Latches with TRI-STATE Outputs ....... .
DM74AS880 Dual 4-Bit 0-Type Transparent Latches with TRI-STATE Outputs ....... .

3-107
3-114
3-120
3-136
3-172
3-189

Multiplexers/Demultiplexers
DM74AS15 7 Quad 1 of 2 Line Data Selectors/Multiplexers ........................ .
DM74AS158 Quad 1 of 2 Line Inverting Data Selectors/Multiplexers ................ .
DM74AS257 Quad TRI-STATE 1 of 2 Line Data Selectors/Multiplexers .............. .
DM74AS258 Quad TRI-STATE 1 of 2 Line Inverting Data Selectors/Multiplexers ..... .

3-38
3-38
3-84
3-84

Transceivers
DM74AS242 Octal TRI-STATE Inverting Bus Transceivers ......................... .
DM74AS243 Octal TRI-STATE Bus Transceivers ................................. .
DM74AS245 Octal TRI-STATE Bus Transceivers ................................. .
DM74AS620 Octal TRI-STATE Inverting Bus Transceiver .......................... .
DM74AS640 Octal TRI-STATE Bus Transceivers ................................. .
DM74AS645 Octal TRI-STATE Bus Transceivers ................................. .
DM74AS646 Octal TRI-STATE Bus Transceivers/Registers ........................ .
DM74AS648 Octal TRI-STATE Inverting Bus Transceivers/Registers ............... .
DM74AS651 Octal TRI-STATE Inverting Bus Transceivers/Registers ............... .
DM74AS652 Octal TRI-STATE Bus Transceivers/Registers ........................ .
DM74AS2620 Octal Bus Transceivers/MOS Drivers .............................. .
DM74AS2645 Octal TRI-STATE Bus Transceivers/MOS Drivers .................... .

3-76
3-76
3-82
3-139
3-142
3-145
3-148
3-148
3-153
3-153
3-225
3-228

Section 4

Physical DimensionslAppendices

Physical Dimensions .......................................................... .
Data Bookshelf
Sales and Distribution Offices
ix

4-3

Alpha-Numeric Index
AN-363 Designing with TIL ...... ; ............................................ : ............ 1-16
AN-372 Designer's Encyclopedia of Bipolar One-Shots ........................................ 1-19
AN-476 Guide to ALS and AS ............................................................... 1-35
DM54174ALSOOA Quad 2-lnput NAND Gates .................................................. 2-5
DM54174ALS01 Quad 2-lnput NAND Gates with Open-Collector Outputs ......................... 2-7
DM54174ALS02 Quad 2-lnput NOR Gates .................................................... 2-9
DM5417 4ALS03B Quad 2-lnput NAND Gates with Open-Collector Outputs ....................... 2-11
DM54174ALS04B Hex Inverters ............................................................ 2-13
DM54174ALS05A Hex Inverters with Open-Collector Outputs ................................... 2-15
DM54174ALS08 Quad 2-lnput AND Gates .............................. ; .................... 2-17
DM54174ALS09 Quad 2-lnput AND Gates with Open-Collector Outputs .......................... 2-19
DM54174ALS10A Triple 3-lnput NAND Gates ................................................ 2-21
DM54174ALS11A Triple 3-lnput AND Gates .................................................. 2-23
DM54174ALS12A Triple 3-lnput NAND Gates with Open-Collector Outputs ....................... 2-25
DM54174ALS13 Dual4-lnput NAND Gates with Schmitt Trigger Inputs ........................... 2-27
DM54174ALS14 Hex Inverters with Schmitt Trigger Inputs ...................................... 2-29
DM54174ALS15A Triple 3-lnput AND Gates with Open-Collector Outputs ........................ 2-32
DM54174ALS20A Dual4-lnput NAND Gates ................................................. 2-34
DM5417 4ALS21 A Dual 4-lnput AND Gates ................................................... 2-36
DM54174ALS22B Dual4-lnput NAND Gates with Open-Collector Outputs ........................ 2-38
DM54174ALS27 Triple 3-lnput NOR Gates ................................................... 2-40
DM54174ALS28A Quad 2-lnput NOR Buffers ................................................. 2-42
DM54174ALS30A 8-lnput NAND Gate ....................................................... 2-44
DM54174ALS32 Quad 2-lnput OR Gates ..................................................... 2-46
DM54174ALS33A Quad 2-lnput NOR Buffers with Open-Collector Outputs ....................... 2-48
DM54/74ALS37 A Quad 2-lnput NAND Buffers ................................................ 2-50
DM54174ALS38A Quad 2-lnput NAND Buffers with Open-Collector Outputs ...................... 2-52
DM54174ALS40A Dual4-lnput NAND Buffers ................................................ 2-54
DM54174ALS74A Dual D Positive-Edge-Triggered Flip-Flops with Preset and Clear ............ : ... 2-56
DM54174ALS86 Quad 2-lnput Exclusive-OR Gates ............................................ 2-59
DM54174ALS109A Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear ............ 2-61
DM54174ALS131 3 to 8 Line Decoder Demultiplexer with Address Register .....................• 2-64
DM54174ALS132 Quad 2-lnput NAND Gates with Schmitt Trigger Inputs ......................... 2-67
DM54174ALS133 13-lnput NAND Gate ...................................................... 2-69
DM54174ALS136 Quad 2-lnputs Exclusive-OR Gates with Open-Collector Outputs ................ 2-71
DM54174ALS137 3 to 8 line Line Decoder/Demultiplexer with Address Latches ................... 2-73
DM54174ALS1383 to 8 Line Decoder/Demultiplexer .......................................... 2-76
DM54174ALS1511 of 8 Line Data Selector/Multiplexer ........................................ 2-79
DM54174ALS153 Dual 1 of 4 Line Data Selectors/Multiplexers ................................. 2-83
DM54174ALS157 Quad 1 of 2 Line Data Selectors/Multiplexers ...................•............. 2-86
DM54174ALS158 Quad 1 of 2 Line Inverting Data Selectors/Multiplexers ........................ 2-86
DM54174ALS160B Synchronous 4-Bit Decade Counter with Asynchronous Clear ................. 2-89
DM5417 4ALS 161 B Synchronous 4-Bit Binary Counter with Asynchronous Clear ................... 2-89
DM5417 4ALS 162B Synchronous 4-Bit Decade Counter with Synchronous Clear .................. 2-89
DM5417 4ALS 163B Synchronous 4-Bit Binary Counter with Synchronous Clear .................... 2-89
DM54174ALS165 8-Bit Parallel In/Serial Out Shift Register ..................................... 2-97
DM54174ALS166 8-Bit Parallel Load Shift Registers .......................................... 2-102
DM54174ALS168B Synchronous 4-Bit Up/Down Decade Counter .............................. 2-106
DM54174ALS169B Synchronous 4-Bit Up/Down Binary Counter ............................... 2-106
DM54174ALS174 Hex D Flip-Flops with Clear ............................................... 2-111
DM5417 4ALS175 Quad D Flip-Flops with Clear and Complementary Outputs .................... 2-111

x

Alpha-Numeric Index (Continued)
DM54174ALS190 Synchronous 4-Bit Up/Down Decade Counter ............................... 2-115
DM5417 4ALS191 Synchronous 4-Bit Up/Down Binary Counter ................................ 2-115
DM54174ALS192 Synchronous 4-Bit Up/Down Decade Counter with Clear and Dual Clock ........ 2-122
DM5417 4ALS193 Synchronous 4-Bit Up/Down Binary Counter with Clear and Dual Clock ......... 2-122
DM54174ALS240A Octal TRI-STATE Inverting Buffers/Line Drivers/Line Receivers .............. 2-129
DM54174ALS241A Octal TRI-STATE Buffers/Line Drivers/Line Receivers ...................... 2-129
DM5417 4ALS242B Quad TRI-STATE Inverting Bus Transceivers .............................. 2-133
DM5417 4ALS243A Quad TRI-STATE Bus Transceivers ....................................... 2-133
DM54174ALS244A Octal TRI-STATE Bus Driver ............................................. 2-137
DM54174ALS245A Octal TRI-STATE Bus Transceivers ....................................... 2-140
DM54/74ALS251 TRI-STATE 1 of 8 Line Data Selector/Multiplexer ............ " ....... " ..... 2-143
DM5417 4ALS253 TRI-STATE Dual 1 of 4 Line Data Selectors/Multiplexers ..................... 2-147
DM54/74ALS257 Quad TRI-STATE 2 to 1 Line Data Selectors/Multiplexers ..................... 2-150
DM54174ALS258 Quad TRI-STATE 2 to 1 Line Inverting Data Selectors/Multiplexers ............ 2-150
DM5417 4ALS273 Octal 0-Type-Edge-Triggered Flip-Flops with Clear ........................... 2-154
DM5417 4ALS352 Dual 1 of 4 Line Inverting Data Selectors/Multiplexers ........................ 2-158
DM54174ALS353 TRI-STATE Dual 1 of 4 Line Data Selectors/Multiplexers ..................... 2-161
DM5417 4ALS373 Octal 0-Type TRI-STATE Transparent Latches .............................. 2-164
DM54174ALS374 Octal TRI-STATE D-Type-Edge-Triggered Flip-Flops ......................... 2-168
DM5417 4ALS390 Dual 4-Bit Decade Counters ............................................... 2-172
DM54174ALS465A Octal TRI-STATE Buffers/Bus Drivers .................................... 2-176
DM54174ALS466A Octal TRI-STATE Inverting Buffers/Bus Drivers ............................ 2-176
DM54174ALS467A Octal TRI-STATE Buffers/Bus Drivers .................................... 2-176
DM54174ALS468A Octal TRI-STATE Inverting Buffers/Bus Drivers ............................ 2-176
DM5417 4ALS518 Octal 8-Bit Identity Comparator with Open-Collector Outputs .................. 2-180
DM54174ALS519 Octal8-Bit Identity Comparator with Open-Collector Outputs .................. 2-180
DM54174ALS520 Octal8-Bit Identity Comparator ............................................ 2-180
DM5417 4ALS521 Octal 8-Bitldentity Comparator ............................................ 2-180
DM54174ALS522 Octal 8-Bit Identity Comparator with Open-Collector Outputs .................. 2-180
DM54174ALS533 Octal D-Type Transparent Latches with TRI-STATE Outputs .................. 2-184
OM 5417 4ALS534 Octal 0-Type-Edge-Triggered Flip-Flops with TRI-STATE Outputs .............. 2-188
DM541?4AI,.S540 Octal Inverting Buffers and Line Drivers with TRI-STATE Outputs .............. 2-192
DM54174ALS541 Octal Buffers and Line Drivers with TRI-STATE Outputs ...................... 2-195
DM54174ALS563A Octal 0-Type Transparent Latches with TRI-STATE Outputs ................. 2-198
DM54174ALS564A Octal D-Type-Edge-Triggered Flip-Flops with TRI-STATE Outputs ............ 2-202
DM54174ALS573B Octal D-Type Transparent Latches with TRI-STATE Outputs ................. 2-206
DM5417 4ALS57 4A Octal 0-Type-Edge-Triggered Flip-Flops with TRI-STATE Outputs ............ 2-210
DM54174ALS576A Octal D-Type-Edge-Triggered Flip-Flops with TRI-STATE Outputs ............ 2-214
DM5417 4ALS580A Octal 0-Type Transparent Latches with TRI-STATE Outputs ................. 2-218
DM5417 4ALS590 8-Bit Binary Counter with Output Registers .................................. 2-222
DM54174ALS620A Octal TRI-STATE Bus Transceivers ....................................... 2-226
DM54174ALS640A Inverting Octal Bus Transceivers ......................................... 2-229
DM54174ALS645A Octal TRI-STATE Bus Transceivers ....................................... 2-232
DM54174ALS646 Octal TRI-STATE Bus Transceivers and Registers ........................... 2-235
DM54/74ALS648 Octal TRI-STATE Inverting Bus Transceivers ................................ 2-239
DM54174ALS652 Octal TRI-STATE Bus Transceivers and Registers ........................... 2-243
DM54174ALS689 8-Bit Comparator .................................... " .................. 2-247
DM54174ALS804A Hex 2-lnput NAND Driver ................................................ 2~250
DM5417 4ALS805A Hex 2-lnput NOR Driver ................................................. 2-252
DM5417 4ALS808A Hex 2-1 nput AN 0 Driver ................................................. 2-254
DM54174ALS810 Quad 2-lnput Exclusive-NOR Gates ........................................ 2-256

xi

Alpha-Numeric Index (Continued)
DM54174ALS811 Quad 2-lnput Exclusive-NOR Gates with Open Collector Outputs .............. 2-259
DM5417 4ALS832A Hex 2-lnput OR Line Drivers ............................................. 2-261
DM54174ALS873B Dual4-Bit D-Type Transparent Latches with TRI-STATE Outputs ............. 2-263
DM5417 4ALS874B Dual 4-Bit D-Type-Edge-Triggered Flip-Flops with TRI-STATE Outputs ........ 2-267
DM54174ALS876A Dual4-Bit D-Type-Edge-Triggered Flip-Flops with TRI-STATE Outputs ........ 2-271
DM54174ALS880A Dual4-Bit D-Type Transparent Latches with TRI-STATE Outputs ............. 2-275
DM54174ALS1000A Quad 2-lnput NAND Buffer ............................................. 2-279
DM54174ALS1002A Quad 2-lnput NOR Buffer .............................................. 2-281
DM54/74ALS1 003A Quad 2-lnput NAND Buffer with Open-Collector Outputs .................... 2-283
DM54174ALS1004 Hex Inverting Drivers .................................................... 2-285
DM54174ALS1005 Hex Inverting Drivers with Open-Collector Outputs .......................... 2-287
DM54174ALS1008A Quad 2-lnput AND Buffers .............................................. 2-289
DM54174ALS1 01 OA Triple 3-lnput NAND Buffers ............................................. 2-291
DM54174ALS1011A Triple 3-lnput AND Buffers .............................................. 2-293
DM54174ALS1020A Dual4-lnput NAND Buffers ............................................. 2-295
DM54/74ALS1032A Quad 2-lnput OR Buffers ............. ~ ................................. 2-297
DM54174ALS1034 Hex Non-Inverting Buffers ............................................... 2-299
DM54174ALS1 035 Hex Non-Inverting Buffers with Open-Collector Outputs ...................... 2-301
DM54174ALS1240 Octal TRI-STATE Inverting Bus Drivers/Receivers .......................... 2-303
DM54174ALS1241A Octal TRI-STATE Bus Drivers/Receivers ................................. 2-303
DM54174ALS1242 Quad TRI-STATE Inverting Bus Drivers .................................... 2-307
DM54174ALS1243A Quad TRI~STATE Bus Drivers ........................................... 2-307
DM54174ALS1244A Octal TRI-STATE Bus Drivers ........................................... 2-311
DM54174ALS1245A TRI-STATE Bus Transceivers ........................................... 2-314
DM5417 4ALS 1645A Octal TRI-STATE Bus Transceivers ...................................... 2-317
DM54174ALS2541 Octal Buffers and MOS Line Drivers with TRI-STATE Outputs ................ 2-320
DM5417 4ALS2645 Octal TRI-STATE Transceivers ........................................... 2-323
DM54174ALS5245 Octal TRI-STATE Transceivers .............................•............. 2-326
DM54174ALS5620 Octal TRI-STATE Transceivers ........................................... 2-329
DM54174ASOO Quad 2-lnput NAND Gates .................................................... 3-4
DM54174AS02 Quad 2-lnput NOR Gates ..................................................... 3-6
DM54174AS04 Hex Inverters ................................................................ 3-8
DM5417 4AS08 Quad 2-lnput AND Gates ..................................................... 3-10
DM54174AS10 Triple 3-lnput NAND Gates ................................................... 3-12
DM5417 4AS11 Triple 3-lnput AND Gates .................................................... 3-14
DM54174AS20 Dual4-lnput NAND Gates ............... , .................................... 3-16
DM54174AS21 Dual4-lnput AND Gates ..................................................... 3-18
DM54174AS27 Triple 3-lnput NOR Gates .................................................... 3-20
DM54174AS30 8-lnput NAND Gates ........................................................ 3-22
DM54174AS32 Quad 2-lnput OR Gates ...................................................... 3-24
DM54174AS34 Hex Non-Inverter ........................................................... 3-26
DM54174AS74 Dual D Positive-Edge-Triggered Flip-Flops with Preset and Clear .................. 3-28
DM54174AS86 Quad 2-lnput Exclusive-OR Gates ............................................. 3-31
DM54174AS109 Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear ............... 3-33
DM54/74AS136 Quad 2-lnput Exclusive-OR Gates with Open-Collector Outputs .................. 3-36
DM54174AS157 Quad 1 of 2 Line Data Selectors/Multiplexers .................................. 3-38
DM54174AS158 Quad 1 of 2 Line Inverting Data Selectors/Multiplexers ......................... 3-38
DM5417 4AS 160 Synchronous 4-Bit Decade Counter with Asynchronous Clear .................... 3-42
DM54174AS161 Synchronous 4-Bit Binary Counter with Asynchronous Clear ..................... 3-42
DM5417 4AS162 Synchronous 4-Bit Decade Counter with Synchronous Clear ............... ~ ....• 3-42
DM54174AS163 Synchronous 4-Bit Binary Counter with Synchronous Clear ...................... 3-42

xii

Alpha-Numeric Index (Continued)
DM54174AS168A Synchronous 4-Bit Up/Down Decade Counter ................................ 3-49
DM54174AS169A Synchronous 4-Bit Up/Down Binary Counter ................................. 3-49
DM5417 4AS 174 Hex D Flip-Flops with Clear .................................................. 3-54
DM54/74AS175A Quad D Flip-Flops with Clear ............................................... 3-57
DM5417 4AS181 B Arithmetic Logic Unit/Function Generators ................................... 3-60
DM54174AS182 Look-Ahead Carry Generators ............................................... 3-69
DM54174AS230 Octal TRI-STATE Bus Drivers/Receivers with True and Inverting Outputs ......... 3-73
DM54/74AS231 Octal TRI-STATE Inverting Bus Drivers/Receivers ............................. 3-73
DM54174AS240 Octal TRI-STATE Inverting Buffers/Line Drivers/Line Receivers ................. 3-76
DM54174AS241 Octal TRI-STATE Buffers/Line Drivers/Line Receivers ......................... 3-76
DM54/74AS242 Octal TRI-STATE Inverting Bus Transceivers .................................. 3-76
DM54174AS243 Octal TRI-STATE Bus Transceivers .......................................... 3-76
DM54174AS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers ......................... 3-76
DM54174AS245 Octal TRI-STATE Bus Transceivers .......................................... 3-82
DM54/74AS257 Quad TRI-STATE 1 of 2 Line Data Selectors/Multiplexers ....................... 3-84
DM5417 4AS258 Quad TRI-STATE 1 of 2 Line Inverting Data Selectors/Multiplexers ............... 3-84
DM54174AS264 Look Ahead Carry Generator ................................................ 3-88
DM54174AS280 9-Bit Parity Generator/Checker .............................................. 3-93
DM5417 4AS282 Look Ahead Carry Generator with Selectable Carry Inputs ....................... 3-97
DM5417 4AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port .................. 3-102
DM5417 4AS373 Octal D-Type Transparent Latches with TRI-STATE Outputs .................... 3-107
DM5417 4AS374 Octal D-Type-Edge-Triggered Flip-Flops with TRI-STATE Outputs ............... 3-110
DM5417 4AS533 Octal D-Type Transparent Latches with TRI-STATE Outputs .................... 3-114
DM54174AS534 Octal D-Type-Edge-Triggered Flip-Flops with TRI-STATE Outputs ............... 3-117
DM54174AS573 Octal D-Type Transparent Latches with TRI-STATE Outputs .................... 3-120
DM54174AS574 Octal D-Type-Edge-Triggered Flip-Flops with TRI-STATE Outputs ............... 3-124
DM5417 4AS575 Octal D-Type-Edge-Triggered Flip-Flops with Synchronous Clear ................ 3-127
DM5417 4AS576 Octal D-Type-Edge-Triggered Flip-Flops with Inverted Outputs .................. 3-130
DM54174AS577 Octal D-Type-Edge-Triggered Flip-Flops with Inverted
Outputs and Synchronous Preset ........................................................ 3-133
DM5417 4AS580 Octal D-Type Transparent Latches with TRI-STATE Outputs .................... 3-136
DM54174AS620 Octal TRI-STATE Inverting Bus Transceiver .................................. 3-139
DM54174AS640 TRI-STATE Octal Bus Transceivers ......................................... 3-142
DM54174AS645 TRI-STATE Octal Bus Transceivers ......................................... 3-145
DM5417 4AS646 Octal TRI-STATE Bus Transceivers/Registers ................................ 3-148
DM54174AS648 Octal TRI-STATE Inverting Bus Transceivers/Registers ....................... 3-148
DM54174AS651 Octal TRI-STATE Inverting Bus Transceivers/Registers ....................... 3-153
DM54174AS652 Octal TRI-STATE Bus Transceivers/Registers ................................ 3-153
DM54174AS804B Hex 2-lnput NAND Driver ................................................. 3-159
DM54174AS805B Hex 2-lnput NOR Driver .................................................. 3-161
DM5417 4AS808B Hex 2-lnput AND Driver .................................................. 3-163
DM54174AS810 Quad 2-lnput Exclusive NOR Gates ......................................... 3-165
DM54174AS811 Quad 2-lnput Exclusive NOR Gates with Open Collector Outputs ................ 3-168
DM54174AS832B Hex 2-lnput OR Line Driver ............................................... 3-170
DM54174AS873 Dual 4-Bit D-Type Transparent Latches with TRI-STATE Outputs ................ 3-172
DM54174AS874 Dual4-Bit D-Type-Edge-Triggered Flip-Flops ................................. 3-176
DM54174AS876 Dual 4-Bit D-Type-Edge-Triggered Flip-Flops ................................. 3-180
DM54174AS878 Dual4-Bit D-Type-Edge-Triggered Flip-Flops with Synchronous Clear ............ 3-183
DM54174AS879 Dual 4-Bit D-Type-Edge-Triggered Flip-Flops with TRI-STATE
Outputs and Synchronous Clear ......................................................... 3-186
DM5417 4AS880 Dual 4-Bit D-Type Transparent Latches with TRI-STATE Outputs ........•....... 3-189

xIII

Alpha-Numeric Index (Continued)
DM5417 4AS881 B 4-Bit Arithmetic Logic Unit/Function Generator .................•............ 3-193
DM54174AS1000A Quad 2-lnput NAND Drivers ........................•...•................ 3-205
DM54174AS1004A Hex Inverting Drivers ...............•.................................... 3-207
DM54174AS1008A Quad 2-lnput AND Drivers .........•....•................................ 3-209
DM5417 4AS1 032A Quad 2-lnput OR Drivers ..........................•..................... 3-211
DM54174AS1034A Hex Non-Inverting Drivers ............................................... 3-213
DM54174AS1036A Quad 2-lnput NOR Drivers ..............................•................ 3-215
DM54/74AS1804 Hex 2-lnput NAND Drivers •.............•...............•................. 3-217
DM54174AS1805 Hex 2-lnput NOR Drivers .........................•....................... 3-219
DM5417 4AS1808 Hex 2-lnput AND Drivers .................................................. 3-221
DM54174AS1832 Hex 2-lnput OA Drivers ........................•....•....•...•............ 3-223
DM54174AS2620 Octal Bus Transceivers/MOS Drivers ................•.•..•................ 3-225
DM5417 4AS2645 Octal TAl-STATE Bus Transceivers/MOS Drivers ............................ 3-228

xiv

Section 1
Introduction to
Bipolar Logic

II

Section 1 Contents
Guide to Bipolar logic Families. . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . .. . . . . . . .. . . . .. . . . . . . . . .
Ie Device Testing ..................................................................
Application Notes
AN-363 Designing with TTL ...'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-372 De~igner's Encyclopedia of BjPolar One-Shots. . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . .
AN-476 GUide to AlS and AS ........... .. .......... ................. ..... .... .....
Functionallndex/Selection Guide ....................................................
Glossary of Terms....... ..... ............. ..................... ... ............... ..
Test Waveforms. ...................................................................

1-2

1-3
1-8
1-16
1-19
1-35
1-44
1-63
1-68

Guide to Bi~olar Logic
Device Families

Since the introduction of the first saturating logic bipolar integrated circuit family (DM54/DM74), there have been many
developments in the process and manufacturing technologies as well as circuit design techniques which have produced new generations (families) of bipolar logic devices.
Each generation had advantages and disadvantage~ qver
the previous generations. Today National provides six bipolar logic families.
TTL
Low Power
Low Power Schottky
Advanced Low Power Schottky
Schottky
Advanced Schottky

LOW POWER SCHOTTKY (DM54LS/DM74LS)
The low power Schottky family features a combined fivefold
reduction in current and power when compared to the TTL
family. Gold doping commonly used in the TTL devices reduces switching times at the expense of current gain. The
LS process overcomes this limitation by using a surface barrier diode (Schottky diode) in the baker clamp configuration
between the base and collector junction of the transistor. In
this way, the transistor is never fully saturated and recovers
quickly when base drive is interrupted. USing shallower diffusion and soft-saturating Schottky diode clamped transistors,
higher current gains and faster turn-on times are obtained.
The LS circuits do not use the multi-emitter inputs. They use
diode-transistor inputs which are faster and give increased
input breakdown voltage; the input threshold is - 0.1 V lower than TTL.. Another commonly used input is the vertical
substrate PNP transistor. In addition to fast switching, it exhibits very high impedance at both the high and low input
states, and the transistor's current gain (/3) significantly reduces input loading and provides better output performance. The output structure is also modified with a Darlington
transistor pair to increase speed and improve drive capability. An active pull-down transistor (03) is incorporated to
yield a symmetrical transfer characteristic (squaring network). This family achieves circuit performance exceeding
the standard TTL family at fractions of its power consumption. The typical device power dissipation is 2 mW per gate
and typical propagation delay is 10 ns while driving a 15 pF I
2 kO load.

(DM54/DM74)
(DM54L1DM74L)
(DM54LS/DM74LS)
(DM54ALS/DM74ALS)
(DM54S/DM74S)
(DM54AS/DM74AS)

TTL LOGIC (DM54/DM74)
TTL logic was the first saturating logic integrate~circuit family introduced, thus setting the standard for all the future
families. It offers a combination of speed, power consumption, output source and sink capabilities suitable for most
applications. This family offers the greatest variety of logic
functions. The basic gate (see Fiiure 1) features a multipleemitter input configuration for fast switching speeds, active
pull-up output to provide a low driving source impedance
which also improves noise margin and device speed. Typical device power dissipation Is 10 mW per gate and the
typical propagation delay is 10 ns when driving a 15
pF/4000 load.
LOW POWER (DM54L/DM74L)
The low power family has essentially the same circuit configuration as the TTL devices. The resistor values, however,
are increased by nearly tenfold, which results in tremendous
reduction of power dissipation to less than V10 of the TTL
family. Because of this reduction of power, the device speed
is sacrificed. The propagation delays are increased threefold. These devices have a typical power dissipation of 1
mW per gate and typical propagation delay of 33 ns, making
this family ideal for applications where power consumption
and heat dissipation are the critical parameters.

SCHOTTKY (DM54S/DM74S)
This family features the high switching speed of unsaturated
bipolar emitter-coupled logiC, but consumes more power
than standard TTL devices. To achieve this high speed, the
Schottky barrier diode is incorporated as a clamp to divert
the excess base current and to prevent the transistor from
reaching deep saturation. The Schottky gate input and inter-

Vee

Vee

OUTPUT

TLlF/5534-2

TL/F/5534-1

FIGURE 2. DM54LOO/DM74LOO

FIGURE 1. DM5400/DM7400

1-3

nal circuitry resemble the standard TTL gate except the resistor values are about one-half the TTL value. The output
section has a Darlington transistor pair for pull-up and an
active pull-down squaring network. This family has power
dissipation of 20 rWN per gate and propagation delays three
times as fast as TTL devices with the average time of 3 ns
while driving 15 pF/2800 load.

clamped by Schottky diodes to prevent them from swinging
excessively below ground level. A buried N+ guard ring
around all input and output structures prevents croSstalk.
The ALS family has a typical power dissipation of 1 mW per
gate and typical propagation delay time of 4 ns into a 50
pF/2 kO load.

ADVANCED LOW POWER SCHOTTKY
(DM54ALS/DM74ALS)

This family of devices is designed to meet the needs of the
system deSigners who require the ultimate in speed. Utilizing Schottky barrier diode clamped transistors with Shallower diffusions and advanced oxide-isolation fabrication techniques, the AS family achieves the fastest propagation delay that bipolar technology can offer. The AS family has
virtually the same circuit configuration as the ALS lamily. It
has PNP transistor or diode inputs with electrostatic protection base-emitter shorted transistors. The output totem-pole
consists of a Darlington pair transistor pull-up and an active
pull-down squaring network. The inputs and outputs are
Schottky clamped to attenuate critical transmission line reflections. In addition, the circuit contains the "Miller Killer"
network at the output section to improve output rise time
and reduce power consumption during switching at high
repetition rates. The AS family yields typical power dissipation of 7 mW per gate and propagation delay time of 1.5 ns
when driving a 50 pF/2 kO load.

ADVANCED SCHOTTKY (DM54AS/DM74AS)

The advanced low power Schottky family is one of the most
advanced TTL families. It delivers twice the data handling
efficiency and still provides up to 50% reduction in power
consumption compared to the LS family. This is possible
because of a new fabrication process where components
are isolated by a selectively grown thick-oxide rather than
the P-N junction used in conventional processes. This refined process, coupled with improved circuit design techniques, yields smaller component geometries, shallower diffusions, and lower junction capacitances. This enables the
devices to have increased tr in excess of 5 GHz and improved switching speeds by a factor of two, while offering
much lower operating currents.
In addition to the pin-to-pin compatibility of the ALS family, a
large number of MSI and LSI functions are introduced in the
high density 24-pin 300 mil DIP. These devices offer the
deSigners greater cost effectiveness with the advantages of
reduced component count, reduced circuit board real-estate, increased functional capabilities per device and improved speed-power perfomanee.

SELECTING A FAMILY

Two factors shoud be considered when choosing a logic
family for application, speed and power consumption. New
logic families were created to improve the speed or lower
the power consumption of the previous families. The following tables rate each family.

The basic ALS gate schematic is quite similar to the LS
gate. It consists of either the PNP transistor or the diode
inputs, Darlington transistor pair pull-up and active pulldown (squaring network) at the output. Since the shallower
Iliffusions and thinner oxides will cause ALS devices to be
more susceptible to damage from electro-static discharge,
additional protection via a base-emitter shorted transistor is
included at the input for rapid discharge of high voltage static electriCity. Furthermore, the inputs and outputs are

Speed
Fastest

J.

Vee

Slowest

Power Consumption
AS
S
ALS
LS
TTL
L

Low

J.
High

L
ALS
LS
AS
TTL
S

vee
18k

7k
2.8kll

90011

6011

OUll'UT

INPIIT B ~~...t41--'

OUTPUT

TLlF/5534-4

1.5k

FIGURE 4. DM54S00/DM74S00

TL/F/5534-3

FIGURE 3. DM54LSOO/DM74LSOO

1-4

r--------------------------------------------------------------------.~

c

Vee

40k

12k

i
s-

25

ID

-6'

o
~

b

CO

C:;'
Ie

~

C:;'
CD

INPUT A - - t - - t

~

+--1.-+-.....- OUTPUT

~

ii'
(II

INPUT 8 - - t - - t

TLiF/5534-5

FIGURE 5, DM54ALSOO/DM74ALSOO
Vee

10k

2k

50k

26

~I--t-----

TRI-STATE ISOURCE: Output is set in the low state and then
TRI-STATE mode. VOZH = 2.7V is then applied. The current drawn into the device is then measured.

TRI-STATEIII> ISINK and ISOURCE are measured with the output control input tied to the appropriate threshold value
(usually VIL = O.8V) and with VCC(max)' This is to insure that

IOZHVSVOZH
(TRI-5TATE ISOURCE),
IOZLVSVOZL
(yRI-STATE'SINK)
Typical LS Device Curve

VCLAMP vs ICLAMP

o Typical LS Device Curve

J"

If

1
]

12
16
20
-1.6

ICLAMP

VCLAMP

-18mA

-1.5V

20

10Z

10

IOZL - 20,.A O.4V
IOZH 20 ,.A 2.7V

IOlH

10

J

~
-10

I

VOZ

lOll

-20
-1.2

-0.8

o

-0.4
TL/F/6731-19

TL/F/6731-26

rrVCC=MIN
liN

0.5 1.0 1.5 2.0 2.5 3.0 3.5
VOl (VI

VCLAMP (VI

:::t....Jc>-

VcC=MAX

TLIF/6731-21

VCC=MIN

J
Rl

INPUT

hl

OUTPUT CONTROL

TL/F/6731-22

TL/F/6731-23

1·13

II

CDr-----------------------------------------------------------------------------,
C

]

8

~

S:!

HIGH LEVEL OUTPUT CURRENT (OPEN-COLLECTOR
DEVICES ONLy)

AC SWITCHING CHARACTERISTICS

The AC switching characteristics are generally measured in
units of time (commonly in nanoseconds), and define how
long it takes for the signal to propagate from the input to the
output The definitions used in determining the pass/fail
status of each limit are not the same for AC as they are for
DC. The distinction lies in the fact that for DC operation
there exists one characteristic V-I curve on which the device
must operate. Devices are good if they operate on the correct side of the limit, and bad if they operate on the wrong
side of the limit. When dealing with certain AC parameters
(fMAX' tsET-UP, tHOLD, tRELEASE, tpw), the device can, and
usually does, operate on both sides of the databook limit.
The limit really implies a boundary that all devices are guaranteed to exceed. Depending upon the parameter, the device will either operate at all values above and some below
the limit, or it will operate at all values below and some
above the limit. In each case, the device is only guaranteed
to operate for all values on one side of the limit. Although
the device will also operate beyond the limit, it is not guaranteed to. Furthermore, device operation beyond the limit is
not considered a failure. For instance, take the fMAX parameter with a min limit of 25 MHz. All devices are guaranteed
to operate at all frequencies below 25 MHz and will operate
in excess of 25 MHz, although this is not guaranteed. Now,
take the example of tsET-UP with a minimum limit of 25 ns.
All of the devices are guaranteed to operate with a set-up
time of 25 ns and longer, and will operate with set-up times
below 25 ns, although this is not guaranteed either. Be
aware that both of these specifications are listed in the minimum column in the databook, but the interpretation of what
is failing differs significantly.

ICEX is tested with the output in the high state. VCC is set to
5.0V and the specified voltage (5.5V for LS) is applied to the
output. The inputs are at the threshold values (O.BV and
2.0V, depending upon the logic to put output in the high
state) and the resulting ICEX leakage current is measured.

ICEXVSVOUT

(Open-Collector Device)
250 Typical LS Device Curve
200

ICEX

VOUT

250 I'A 5.5V

150

l1110
j

-

50

-50

o

3

4

8

7

Your IV)
TL/F/6731-24

Propagation delays (called prop delays and denoted by the
symbols tpHL and tpLH) are specified as maximum limits,
and guarantee the maximum time one must wait to insure
that the correct data has appeared at the device's output.
Each propagation delay is specified from one input to one
output only.

TUF/6731-25

Vee MAX

I

Input set-up and hold times (including tRELEASE) specify
how long one input must be stable at a particular logic level
prior to an action occurring at another input. For example,
take the DM54/74LS74 positive-edge-triggered D flip-flop.
The "set-up 1" specification defines how long a logiC "1"
must be present and stable at the DATA input prior to the
positive edge of the CLOCK to insure that the device will
recognize that data as a "1". There also exists a "hold 1"
specification which specifies how long a logic "1" must be
held after the active edge of CLOCK for the device to recognize that logic "1". Both the set-up and hold times must
always be met or the device will not necessarily bring in the
proper data. Set-up times are generally positive, while hold

YIN LOW {

TLlF/6731-26

1-14

times may be either positive or negative, usually negative.
The meaning of a negative hold time is that the data may be
removed from the input prior to the active edge of CLOCK,
and the CLOCK will still bring in the desired data. Set-up
and hold times are specified as minimum values, since this
defines the minimum time data must be stable prior to any
change at the CLOCK input. Removing the data sooner than
the minimum time may cause improper action on the part of
the device.

be able to operate at frequencies up to 25 MHz. For the
DM54174LS74 with an fMAX of 25 MHz, all of the devices
are guaranteed to operate at all clock frequencies, up to
and including 25 MHz. Although no devices are guaranteed
to operate above fMAX (only below it), most devices will
operate beyond the maximum specification. The minimum
limit does not state that the device will not operate below
fMAX or that any devices that do are bad, but rather that all
the devices will operate up to the limit.

tRELEASE is specified on devices where there is an input
that must be set inactive prior to the active edge of CLOCK.
Such inputs are usually overriding inputs like CLEAR and
PRESET. With CLEAR active, it will prevent the device from
switching on the CLOCK Signal. tRELEASE is defined as the
time it takes for the CLEAR input to "release" the device for
clocking action, and is specified as a minimum. This represents the maximum delay required between CLEAR going
inactive and the active edge of CLOCK to insure proper
device operation.
All devices that have a CLOCK input also have a specification that defines the maximum speed that the CLOCK can
be driven, called fMAX. This specification is defined as a
minimum specification and states that all of the devices will

Table IV shows the direction of the tighter testing for the
more common AC parameters. All prop dealys (those AC
parameters that have the symbols tpLH or tpHU have simple
min/max limits. The device is guaranteed to operate within
the bounds of the min/max limits, and any operation outside
these limits denotes a device failure. tSET-UP, tHOLD. fMAX.
and tRELEASE parameters have limits that denote guaranteed operation boundaries (i.e., the device is guaranteed to
operate up to the boundary) but no guarantee is made concerning the device operation (or lack of it) beyond the
boundary.
For detailed information on the AC waveforms, please see
the test waveforms in this section.

TABLE IV. Looser/Tighter AC Test Limits Example: DM74LS74
Test

fmax(min)
tPLH(max)
tPHL(max)
iw(min)
tW(min)
tSET·UP(min)
tSET.UP(min)
tHOLD(min)

From

Looser

Nominal

Tighter

Units

CLR, PRE, CLK
CLR, PRE, CLK
CLOCK HIGH
PRE,CLRLOW
DATA HIGH
DATA LOW
All DATA

24
26
31
21
26
21
21
1

25
25
30
20
25
20
20
0

26
24
29
19
24
19
19
-1

MHz
ns
ns
ns
ns
ns
ns
ns

1-15

~ r---------------------------------------------------------------------------~

~ Designing with TTL

National Semiconductor Corp.
Application Note 363
WaltSirovy

OIl(

54174 series TTL has been used for more than a decade
with excellent results, and. continues to be a standard
choice for design engineers because of the wide performance range and system optimization possible from the different families available. 54174 logic comes in 7 different
speed/power families (standard TTL, LS, S, ALS, AS, and L)
that allow a design engineer to select device performance
. to suit his needs. Understanding the differences and the
general limitations of all these families will go a long way
toward insuring that a system will operate as intended with
the minimum of corrections and redesigning.

these elements together, thus eliminating the integrity of the
circuil. This mayor may not result in actual damage to the
device depending upon the magnitude of the violating signal
and the specifics of the device being violated. This holds
true for both junction and oxide isolated logic. Oxide isolated logic may provide more margin before failing (thereby
"working" in some marginal designs), but it is nevertheless
subject to the same kind of limitations as junction isolated
logic.

FAM.ILY COMPATIBILITY: Intermixing Logic Types in
One Design
Family interchangeability is a beneficial characteristic of the
different TTL families and provides the designer with the
ability to customize specific areas of his design in order to
accomplish the task of achieving both high performance
and the lowest power consumption possible. However, interchangeability is not simply a matter of replacing, say, an
SOO for an LSOO to improve the speed and replac;ing an
LSOO for an SOO for power savings. One must also look at
the DC and AC characteristics to insure that the replacement device will be compatible with the existing circuit. The
DC problems include input loading and compatible output
drive capabilities. The AC problems include insuring that the
new device speeds will be acceptable to the rest of the
system. The different logic families also generate different
amounts of noise and have different noise immunity. Finally,
measure points for the AC parameters of the different families, although very similar, do vary some, and this will require
attention.

Bipolar logic uses the ground rail as the signal reference.
Consequently, any modulation on the ground line will be
directly added to the signal voltage. The logic "0" input
noise margin is guaranteed as the difference between the
VOL and VIL specification, and the logical "1" input noise
margin is guaranteed as the difference between the VOH
and VIH specification. This noise margin is intended to be
protection against a reasonable amount of noise present.
Insufficient grounding techniques can cause significant IR
and IL drops on the ground line between two ICs and result
in a "floating" ground line. This is due to the large currents
that are present on ground and Vee during high speed
switching and means that the two devices are not using the
same reference pOint. Any voltage drop in the ground line is
added to the signal and ends up consuming some of the
noise margin. Eventually, the mismatch caused by the floating ground will exceed the total noise margin and causeerroneous data to propagate through the system. The solutions to this problem are many and varied, but ali of them
revolve around improving the system grounding and include
such ideas as providing separate signal and power grounds.

IMPROPER GROUNDING: Noise Immunity,
Floating Grounds

SUPPLY RAILS: Why Not to Exceed the Specs
Ali bipolar logic (both junction and oxide isolated) is made
up of selectively located regions of differently doped materials that form transistors, resistors, and diodes. Because of
this, certain overall requirements are necessary to insure
that the IC will be able to perform its task without interference from its environment. The first characteristic of bipolar
devices is that the two power rails (Vee and ground) represent the two voltage extremes that should be used in any
system. Certain exceptions exist, primarily inputs and opencollector outputs that are pulled up to higher voltages than
Vee. However, while it is occasionally permissible to exceed
the Vee specification, it is never permissible to drive any
input or output more than 0.5V below the ground reference.
This limitation is due to the method used to electrically isolate the many circuit elements that are present on a 6ipolar
IC. Oxide isolated devices use an oxide layer surrounding
the various transistor and resistor tanks to provide an insulating barrier, while the original junction isolated devices use
reverse biased PN junctions to provide that barrier. In both
cases, the circuit is built on a P-type substrate that uses
reverse biased PN junctions to separate the different circuit
elements. The ground pin is electrically connected to the
substrate and must be the most negative voltage on the
device. When an input or output pin is taken below ground,
the normally reverse biased isolation regions between the
elements become forward biased and electrically connect

Vee NOISE AND DECOUPLING: Providing Clean Power
The Vee power rail is also susceptible to both IR and IL
voltage drops. The problems that arise from the Vee line are
not the same as the problems that arise from the ground
line. Since the VOH level tracks the Vee almost exactly, any
voltage loss on the Vee line is directly transferred to the
VOH level. However, the noise margin for the logic high
state is typically 700 mV for commercial and 500 mV for
military product, versus 400 mV and 300 mV for commercial
and military product, respectively, for the logic low level. The
main consequences of a drooping Vee line now become
IOLIiOH drive capability, and the AC performance in critical
applications. Although bipolar devices are only guaranteed
to operate over a given Vee range (5V ± 10%), these devices typically function to Vee values as low as 4V. Be
aware that if the device does indeed function down to 4V,
the AC and DC characteristics will be compromised, some
quite severely.
DeSigning in a good power distribution system will insure
that all the devices in the circuit will perform the same, regardless of their physical location. Properly decoupling the
Vee against both high and low frequency noise will help
eliminate any problems with individual device operation.
High frequency noise (100 MHz and above) comes primarily
from two sources, while low frequency noise (less than
25 MHz) results from primarily one source.

1-16

SOURCES OF HIGH FREQUENCY NOISE
ON THE Vee LINE
1) High frequency noise results from the device rapidly
switching logic levels. The bulk of the switching current from
a low to high transitions shows up in lee current surges,
while the bulk of the switching current from a high to low
transition shows up in ground current surges.

to protect the input against Vee voltage surges and to protect the system against the possibility of the input shorting
directly to ground. A single 1k resistor can handle up to 10
inputs.
TERMINATIONS: Why Terminate a Transmission Line?
Whenever signals change voltage levels, a wavefront is created that propagates according to the characteristics of the
transmission line being used. If the overall length of the signal path is short compared with the Signal's wavelength
(1/frequency), then none of the complications of transmission lines are present. However, if the length of the signal
path is long in comparison, then the wavefront will be significantly affected by the geometry and composition of that
transmission line.
Fortunately, when dealing with a single board layout, the
distances are usually short enough that one need not worry
about the difficulties of terminating or impedance matching
the line. However, if one is driving between boards or over
long distances, he must be aware of the characteristics involved. When dealing with transmission lines it is necessary
to know the impedance of the line. Every time the signal
wavefront encounters a discontinuity (a point where the impedance Changes, whether from a branch, junction or because of a change of environment), the opportunity for reflections and standing waves is present. These waves can
easily cause the loss of the Signal's integrity, having the
ability to build voltages that are large enough to destroy an
IC. Proper line termination will insure that the signal propagates down the line and is totally absorbed at the receiving
end, thus preventing these waves from occurring.
Listed below is a guideline to the types of transmission lines
to use when sending signals over various distances.
0" to 12" Single wire conductor OK. Use pOint-to-point routing and avoid parallel routing if possible. Ground
plane recommended, but not mandatory. Space
conductors as far apart as possible to reduce line
to line capacitance.

2) Noise is transmitted through the changing magnetic fields
that result from the changing electric fields in a switching
line and are picked up on adjacent signal paths.
Note that the frequency causing the noise is not the signal's
frequency, but the frequency of the signal's slew rate. For
instance, in an SOO that is switching OV to 3V at 1 MHz, the
slew rate of the output is typically about 1 nslV, which is a
frequency of around 160 MHz. The faster the slew rate, the
higher the frequency, until one has an ideal square wave
with infinite frequency. It is this frequency component that
gives rise to the strong magnetic fields associated with
switching bipolar devices.
SOURCES OF LOW FREQUENCY NOISE
ON THE Vee LINE
1) Low frequency noise results from the change in the lee
current demand as devices change state. For instance,
gates, flip-flops, and registers will draw different lee currents, depending upon the state of the outputs.
The most commonly used method for countering these
noise problems is to decouple the Vee line. With this approach, capacitors are used to stabilize the Vee line and
filter out the unwanted frequency components. A small value capacitor (i.e., 0.1 /LF) is used near the device to insure
that the transient currents arising from device switching and
magnetic coupling are minimized. A large value capacitor
(i.e., 50 /LF to 100 /LF) is used on the board in general to
accommodate the continually changing lee requirements of
the total Vee bus line. The following table shows a rough
"rule of thumb" approach to determining how many capacitors to use for a given number if ICs. Be aware that the table
is not a hard and fast rule, and that you must always evaluate your particular application to insure that there is sufficient Vee decoupling. When using these guidelines, be sure
that the devices are located near each other and near the
capaCitor. If the capacitor is too far away, IR and IL drops
will diminish the capacitor's effect. All capacitors (especially
the 0.01 /LFs) must be high frequency RF capacitors. Disk
ceramics are acceptable for this application. Keep in mind
that, in synchronous systems, since a majority of the devices will be switching at once, alter your power distribution
system accordingly.
Device Family
AS, S, ALS, LS, H
TTL,L

Number

12" to 6' Dense ground plane required with wire routed as
closely as possible. Twisted-pair lines or coaxial
cable mandatory for clock lines and recommended for all sensitive control lines.
Over 6'

Use fully terminated transmission lines. Avoid the
use of radially distributed lines and avoid sharp
bends in the line. Be aware that transmission
lines have complex impedances and are not simply resistive in nature.

BUS DRIVERS: On Board vs Off Board
Many of the TRI-STATEiI!> buffers and flip-flops are intended
to connect directly to the system bus and must be able to
drive heavily capacitive loads. Keeping this in mind, all of
National's LS TRI-STATE devices have "triple-sink" capability; that is, the IOL and IOH drive currents have been tripled. However, these devices are intended to drive single
board buses. Driving off the board with these devices can
easily lead to serious problems.

of CapaCitors

1 Cap per 1 device
1 Cap per 2 devices

TYING ALL UNUSED INPUTS TO A SOLID LOGIC LEVEL
Unused inputs on TTL devices float at threshold, anywhere
from 1.1V to 1.5V, depending upon the device and its family.
While this usually simulates a "high", many application
problems can be traced to open inputs. Inputs floating at
threshold are very susceptible to induced noise (transmitted
from other lines) and can easily switch the state of the device. A good design rule is to tie unused inputs to a solid
logic level. Inputs are usually tied to Vee through a 1 kO to
5 kO resistor, since tying them to ground means supplying
the IlL current instead of the IIH current. IlL is several orders
of magnitude greater than IIH. The resistor is recommended

When using standard logic bus drivers on a single board, be
aware that many of the octal and bus oriented devices have
PNP inputs to reduce DC loading. PNP inputs on 54S/74S
devices tend to be more capacitive than the corresponding
diode or emitter inputs, and as such, compromise the AC
loading of the bus. Careful attention must be given to both
DC and AC loading when driving heavily loaded buses. PNP

1-17

•

inputs on LSI ASI ALS operate at significantly lower currents
and do not significantly increase capacitive load.

designed to approximate the input structure, while using no
switches for the TRI-STAT~ parameters. Please see waveforms in this section. In the final analysis of these loads, it
must be kept in mind that they represent a standard that can
be used to determine the quality of an IC. No load will be
able to pr6dict exactly how a device will perform in a circuit
or the speeds that a device cim ~chieve in a good test jig
with the spec load, as compared to ~he speeds that a device
will produce in an application.

It is strongly recommended that any time a bus line leaves a
board, interface bus drivers tJe used. These devices (see
National's 1986 Interface/Databook) are specifically designed to impedance match different kinds of transmission
lines and have the necessarY current drive to handle the
job. Using an ordinary logic device will usually yield poor
results. If one must drive a transmission line with a logic
device, there are some guidelines that should be followed to
'
minimize the problems that can result.
1) Take care to properly terminate the bus. Be aware that
every time a signal passes through a different impedance,
an interface is created and that any impedance mismatch
"
will result in reflections.

OPEN·COLLECTOR DEVICES: What They Are,
How to Uee Them
Open-collector devices are totem pole outputs where the
upper output (usually Darlington tranSistor) is left out of
the circuit. As such, these devices have no active logic high
drive and cannot be used to drive a line high. The advantage to open-collector devices is that a number of outputs
can be directly tied together. If one were to tie two complete
totem pole outputs together, then at some time one output
would be qriving high .while the other output was driving low:
The result is that one device will be dumping excessive current directly into the other device. The resulting power dissipation in both, dEwices can easily degrade the lifetime of the
device. Since open-collector devices only have active drive
in one state, if two connected devices drive to oppOSite
states, the low state will always predominate and there will
be no degradation to either device. Open-collector specifications are obvious by the lack of a VOH specification. The
only VOH/IOH specification is the leakage limits, and these
are specifie~ at VOH = 5.5'if.
When dealing with open-collector devices, it must be noted
that each o'utput requires a resistive pull-up, usually tied to
Vcc. (By using high voltage outputs, one can tie the resistor
pull-up to' a voltage higher than Vcc.) Designers often try to
get away with tying the output to an input and relying on the
IlL current to pull up the output. This unwise, as it is just like
leaving inputs floating: the input is very susceptible to noise
and can easily" give false signals. Shown below are two
equations that can be used to determine the minimax range
of the pull-up resistor.
.

a

2) Never drive off the board with a bistable element like a
flip-flop or a latch. This is because those devices are very
susceptible to reflected waves changing their state. By buff- ering the output of the latch with another device, the reflected wave can affect the output of the buffer, but not the
latcll. "This means that when the wave finally dies out, the
latch will still have the proper data and the buffer will "snap
back" to the proper o u t p u t . '
~)"Be sure to carry an adequate ground plan with the signals
and to shield the bus. Carrying a good ground plan (use
multiple ground lines spaced around the connector if possible) will reduce the problem of floating ground, and the
shielding will help protect the signal lines for induced noise.
USing twisted-pair transmission lines for critical signals
helps to eliminate the capacitive coupling that can degrade
signals," or even cause false signals.

4) It is best to buffer any clock or control lines lhat dElpend

upon fast, clean switching. Buffering at both the sending
and receiving end will go a long way toward insuring that the
clock can aqcomplish its goals.
5) Use the devices with Schmitt inputs to add to the noise

margin of the receiving device. This will help increase the
noise rejection of the system. Decouple each receiver separately, connectinq. the capacitor directly between ground
and Vcc. Make sure that the device ground is tied directly to
the bus gro~nd.
6) If using open-collector devices to drive the bus, add a
pull-up .resistor on the input to the receiving device if the IOL
current' of the driving device can handle it. A resistance in
the 3000 range will significantly improve the signlij's rise
time.

RMAX =' (VCC(MIN) - VOH)
(N1 • IOH + N2· IIH)
RMIN = (VCC(MIN) - VoLl
(lOL - N2 • IILl
where: N1 == the number of open-collector devices tied
together,
N2 = the number of inputs being driven on the line.

AC LOADING: What Do AC Loads Look Like, and Why?
The standard AC load for all of the logic families, except
ALS and AS, is built around a diode chain to ground and a
pull-up resistor to Vcc with added capacitance. This load is
designed to.. look like the standard logic circuit input structure, and to simulate the appearance of switching in an actual application. For ALS and AS, the load is built around a
resistor to' ground and added capacitance. This is primarily
for the requirements of high speed device testing. There
also exists·a set of standardized military AC loads that were

If the mliximum resistance is exceeded, then it is possible
for the total leakage currents from all of the inputs and outputs to pull the VOH level below the spec value. Likewise, if
the RMIN value is exceeded, then the driving device may not
be able to pull down the signal line to a solid VOL. Either of
these two cases can easily result in false logic levels being
propagated through the system.

1·18

~

National Semiconductor Corp.
Application Note 372
Kern Wong

Designer's Encyclopedia of
Bipolar One-Shots
INTRODUCTION
National Semiconductor manufacturers a broad variety of
industrial bipolar monostable multivibrators (one-shots) in
TTL and LS-TTL technologies to meet the stringent needs
of systems designers for applications in the areas of pulse
generation, pulse shaping, time delay, demodulation, and
edge detection of waveforms. Features of the various device types include single and dual monostable parts, retriggerable and non-retriggerable devices, direct clearing input,
and DC or pulse-triggered inputs. Furthermore, to provide
the designer with complete flexibility in controlling the pulse
width, some devices also have Schmitt trigger input, and/or
contain internal timing components for added deSign convenience.

eters, or more frequently by poor circuit layout, improper
bypassing, and improper triggering signal.
In the following sections all bipolar one-shots manufactured
by National Semiconductor are presented with features tables and design charts for comparisons. Operating rules are
outlined for devices in general and for specific device types.
Notes on unique differences per device and on special operating considerations are detailed. Finally, truth tables and
connection diagrams are included for reference.
DEFINITION
A one-shot integrated circuit is a device that, when triggered, produces an output pulse width that is independent
of the input pulse width, and can be programmed by an
external Resistor-Capacitor network. The output pulse width
will be a function of the RC time constant. There are various
one-shots manufactured by National Semiconductor that
have diverse features, although, all one-shots have the basic property of prodUCing a programmable output pulse
width. All National one-shots have True and Complementary
outputs, and both positive and negative edge-triggered inputs.

DESCRIPTION
One-shots are versatile devices in digital circuit design.
They are actually quite easy to use and are best suited for
applications to generate or to modify short timings ranging
from several tens of nanoseconds to a few microseconds.
However, difficulties are constantly being experienced by
design and test engineers, and basically fall into the categories of either pulse width problems or triggering difficulties.
The purpose of this note is to present an overall view of
what one-shots are, how they work, and how to use them
properly. It is intended to give the reader comprehensive
information which will serve as a designer's guide to bipolar
one-shots.
Nearly all malfunctions and failures on one-shots are
caused by misuse or misunderstanding of their fundamental
operating rules, characteristic deSign equations, param-

OPERATING RULES
In all cases, Rand C represented by the timing equations
are the external resistor and capaCitor, called REXT and
CEXT, respectively, in the data book. All the foregoing timing
,equations use C in pF, R in Kfi, and yield tw in nanoseconds. For those one-shots that are not retriggerable, there
is a duty cycle specification associated with them that

TTL AND LS-TTL ONE-8HOT FEATURES
#Per
IC
Package

Retrigger

Reset

DM54121
DM74121

One
One

No
No

No
No

DM54LS122
DM74LS122

One
One

Yes
Yes

Yes
Yes

DM54123
DM74123

Two
Two

Yes
Yes

DM54LS123
DM74LS123

Two
Two

DM54LS221
DM74LS221
DM8601
DM9601

Device
Number

Capacitor
Min Max
In/-tF

Resistor
Min
Max
inKfi

Timing Equation"
for
CEXT> 1000 pF

1.4
1.4

30
40

tw = KRCe(1 + 0.7/R)
K = 0.55

None
None

5
5

180
260

tw = KRC
K = 0.45

Yes
Yes

None
None

5
5

25
50

tw = KRCe(1 + 0.7/R)
K = 0.34

Yes
Yes

Yes
Yes

None
None

5
5

180
260

tw =

Two
Two

No
No

Yes
Yes

1.4
1.4

70
100

tw = KRC
K = 0.7

One
One

Yes
Yes

No
No

5
5

25
50

tw = KRCe(1 + 0.7/R)
K = 0.32

0
0

1000
1000

0
0

1000
1000
None
None

KRC
K = 0.45

tw = KRCe(1 + 1/R)
DM8602
Two
Yes
None
5
25
Yes
K = 0.31
DM9602
Two
Yes
Yes
None
5
50
'The above timing equations hold for all combinations of REXr and CEXT for all cases of CEXT > 1000 pF within specified limits on the REXT and CEXT'

1-19

II

It is never a good practice to leave any unused inputs of a
logic integrated circuit "floating". This is particularly true for
one-shots. Floating uncommitted inputs or attempts to establish a logic HIGH level in this manner will result in malfunction of some devices.

defines the maximum trigger frequency as a function of the
external resistor, REXT.
In a" cases, an external (or internal) timing resistor (REXT)
connects from Vee or another voltage source to the "REXT/
CEXT" pin, and an external timing capacitor (CEXT) connects between the "REXT/CEXT'" and "CEXT" pins are required for proper operation. There are no other elements
needed to program the output pulse width, though the value
of the timing capacitor may vary from 0.0 to any necessary
value.

Operating one-shots with values of the REXT outside the
recommended limits is at the risk of the user. For some
devices it will lead to complete inoperation, while for other
devices it may result in either output pulse widths different
from those values predicted by design charts or equations,
or with modes of operation and performance quite different
from known standard characterizations.

When connecting the REXT and CEXT timing elements, care
must be taken to put these components absolutely as close
to the device pins as pOSSible, electrically and physically.
Any distance between the timing components and the device wi" cause time-out errors in the resulting pulse width,
because the series impedance (both resistive and inductive)
wi" result in a voltage difference between the capaCitor and
the one-shot. Since the one-shot is designed to discharge
the capacitor to a specific fixed voltage, the series voltage
wi" "fool" the one-shot into releasing the capacitor before
the capacitor is fully discharged. This wi" result in a pulse
width that appears much·shorter than the programmed value. We have encountered users who have been frustrated
by pulse width problems and had difficulty to perform correlations with commercial test equipment. The nature of such
problems are usually related to the improper layout of the
OUT adapter boards. (See Figure 6 for a PC layout of an AC
test adapter board.) It has been demonstrated that lead
length greater than 3 cm from the timing component to the
device pins can cause pulse width problems on some devices.

To obtain variable pulse width by remote trimmiing, the following circuit is recommended (Figure 2). "RREMOTE"
should be placed as close to the one-shot as possible.

REXT
"REXT/CEXT" o-~~--W~-.,

-LCEXT
RREMOTE :

r-I
Vee

"CEXT"J

TL/FI750B-2

FIGURE 2

Vee and ground wiring should conform to good high frequency standards and practices so that switching transients
on the Vee and ground return leads do not cause interaction between one-shots. A 0.001. /l-F to 0.1 /l-F bypass capacitor (disk or monolithic type) from the Vee pin to ground
is necessary on each device. Furthermore, the bypass capacitor shoud be located so as to provide as short an electrical path as possible between the Vee and ground pins. In
severe cases of supply-line noise, decoupling in the form of
a local power supply voltage regulator is necessary.

For precise timing, precision resistors with good temperature coefficient should be used. Similarly, the timing capacitor must have low leakage, good dielectric absorption characteristics, and a low temperature coefficient for stability.
Please consult manufacturers to obtain the proper type of
component for the application.

For retriggerable devices the retrigger pulse width is calculated as follows for positive-edge triggering:

For sma" time constants, high-grade mica glass, polystyrene, polypropylene, or polycarbonate capacitor may be
used. For large time constants, use a solid tantalum or special aluminum capaCitor.

VTRIGGER

In general, if a sma" timing capacitor is used that has leakage approaching 100 nA or if the stray capacitance from
either terminal to ground is greater than 50 pF, then the
timing equations or design curves which predict the pulse
width would not represent the programmed pulse width
which the device generates.

--.J
TLlF1750B-3
tRET ~

tw

FIGURE 3
+ IpLH ~ Ke (REXT)(eEXTl + IpHL

(See tables for exact expressions for K and tw; K is unity on
most HCMOS devices.)

When an electrolytiC capaCitor is used for CEXT, a switching
diode is often suggested for standard TTL one-shots to prevent high inverse leakage current (Figure 1). In general, this
switching diode is not required for LS-TTL devices; it is also
not recommended with retriggerable applications.

SPECIAL CONSIDERATIONS AND NOTES:
The 9601 is the single version of the dual 9602 one-shot.
With the exception of an internal timing resistor, RINT, the
'LS 122 has performance characteristics virtually identical to
the 'LS123. The design and characteristic curves for equivalent devices are not depicted individually, as they can be
referenced from their parent device.
National's TTL-'123 dual retriggerable one-shot features a
unique logic realization not implemented by other manufacturers. The "CLEAR" input does not trigger the device, a
design tailored for applications where it is desired only to
terminate or to reduce the timing pulse width.

TLlFI750B-1

FIGURE 1

1-20

r--------------------------------------------------------------------,~

The 'LS221 trigger on "CLEAR": This mode of trigger requires first the "8-lnput" be set from a Low-to-High level
while the "CLEAR" input is maintained at logic Low level.
Then, with the "8" Input at logic High level, the "CLEAR"
input, whose positive transition from LOW-to-HIGH will trigger an output pulse ("A input" is LOW).

The 'LS221, even though it has pin-outs identical to the
'LS123, is not functionally identical. It should be remembered that the 'LS221 is a non-retriggerable one-shot, while
the 'LS123 is a retriggerable one. For the 'LS123 device, it
is sometimes recommended to externally ground its "CEXT"
pin for improved system performance. The "CEXT" pin on
the 'LS221, however, is not an internal connection to the·
device ground. Hence, grounding this pin on the 'LS221 device will render the device inoperative.

CLR

Furthermore, if a polarized timing capacitor is used on the
'LS221, the positive side of the capacitor should be connected to the "CEXT" pin. For the 'LS123 part, it is the contrary, the negative terminal of the capacitor should be connected to the "CEXT" pin of the device (Figure 4).

~

.....
N

1 ...____..1

----------~II--

Iw----l~I----TL/FI7S08-S

FIGURES

Vee

"CeXT"~

Z

~

RX

AC Test Adapter Board
The compact PC layout below is a universal one-shot test
adapter board. 8y wiring different jumpers, it can be configured to accept all one-shots made by National Semiconductor. The configuration shown below is dedicated for the '123
device. It has been used successfully for functional and
pulse width testing on all the '123 families of one-shots on
the Teradyne AC test system.

-

Cx

"REXT/CEXT"

"REXT I CEXT"

(,LS221)

(,LS123)
TLlFI7S08-4

FIGURE 4

1

BOTTOM VIEW

TOP VIEW
TL/FI7508-6

-I-

TLlFI7508-7

FIGURE 6a. AC Test Adapter

FIGURE 6b. AC Test Adapter

II

1·21

Vee

r-

R2

I
b

,

11C3=0

~

16

Cl

14

Q

O·S

0

CLR

TLfFI7508-8

FIGURE 7a. Timing Components and 1/0 connections to D.U.T.

Typical Output Pulse Width vs Timing Components
Timing equations listed in the features
tables hold all combinations of REXT
and CEXT for all cases of CEXT >
1000 pF. For cases where the CEXT <
1000 pF, use graphs shown below.

• DM74121

10·

~J~--~.~.
• R';50

,

=R-~'"

~~

..Io"t"

I-.a....
10 '---"-L..J..I..LJ.U"---"-L..J..I..LJ.W
10
100
1000

10
10

105

DM74LS123

Ig1iDM74LS221
TA=25·C

[Ii:• ....

.......

;:;R.
10

L..-.J....Jw...L..LJ.J.J.I..-.J.....JL..L.L.J..WJ

10

100
CEXT (pF)

1000

vee-5.~.

.....

---t
10

R-l~

~ ~\i:50K
.......

lill

10

1000

100
CEXT (pF)

CEXT (pF)

100
Cm (pF)

10

1000

R-5I(

=== _R-UKIII
10

100

1000

CEXT (pF)

TUFI7508-9

1-22

.--------------------------------------------------------------------..
z

Typical Output Pulse Width Variation vs Ambient Temperature
DM74121

The graphs shown below demonstrate
the typical shift in the device output
pulse widths as a function of temperature. It should be noted that these
graphs represent the temperature shift
of the device after being corrected for
any temperature shift in the timing
components. Any shift in these components will result in a corresponding
shift in the pulse width. as well as any
shift due to the device itself.

10

RElIT-51(
Cm - 1000 pF
Vcc-5.OV

.....

i'-~

........

10

z
~

t- r-

10
RElIT = 10K
CElIT=l000 pF
Vee=5.0V

!
u
~
~

:Ie

~

-5

...... ......

1- i---"'''''

"

!
~

$

-5

-10
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE ('CI

RElIT-10K
Cm=1000 pF
Vee=5.0V

"

"- ........

u

-5

- 10 L-.L-...L.....L.....L---L---'~
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE ('CI

"

DM74123

DM74LS123

~

'- ........

-10
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE ('CI

10

U

RElIT-10K
Cm-l000pF
Vcc-5.OV -

-5

Rm=1OK
Cm=lll11O pF
VCC K 5.0V

z~
C

f'

u
~
~

-10
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE ('CI

74LS221

i'

....

-5

10

~

DM9602

r-...

i'-.

-10
-60 -30 0 30 60 90 120 150
AMBIENT TEMPERATURE ('CI
TLIF/1508-10

Typical Output Pulse Width Variation vs Supply Voltage
The following graphs show the dependence of the pulse width on Vee.
As with any IC applications. the device
should be properly bypassed so that
large transient switching currents can
be easily supplied by the bypass capaCitor. CapaCitor values of 0.001 /l-F
to 0.10 /l-F are generally used for the
Vee bypass capacitor.

10

DM9602
11m- 10K

10

DM74121

.I

IIm=5K
Cm -1000 pF
TA-25°C

Cm-l0GO pF

roo T.=25'C

--

",..,

-5

-

I
~

$

-5

-10

-10
4

4.5

4

5.5

DM74123

10

Vee (VI

DM74LS123

CEXT-lll11O pF
lA-25°C

.....-

I- T.=25'C

-

-5

10

~:;::~~ PF 1

ROT=1OK

-10

-10
4

4.5

5.5

Vee (VI

DM74LS221
REXT=5K
CEXT-looo pF

II

TA=-25°C

--

r-5

5.5

4.5

Vee (VI

10

...-

ic

..

~

$

-5

-10
4

4.5

5.5

Vee (VI

4

4.5

5.5
Vee (VI
TLIF/1508-11

1-23

~

~
CLK

FF

TLlFI7508-22

FIGURE 8. NOise Discriminator
1-27

,... ,---------------------------------------------------------------------------------,
~

___U

i

---"--

__________~rl~_____
Tl/F17508-23

FIGURE 8. Noise Discriminator (Continued)
FREQUENCY DISCRIMINATOR (Figure 9)
The circuit shown in Figure 9 can be used as a frequency·
to-voltage converter. For a pulse train of varying frequency
applied to the input, the one-shot will produce a pulse con-

stant width for each triggering transition on its input. The
output pulse train is integrated by Rl and Cl to yield a waveform whose amplitude is proportional to the input frequency.
(Retriggerable device required.)

Vee

n . _________

VIN

al-""",..,....

o·s

VIN

VOUT

VOUT

--'
/

L:::

TUFI7508-25

TUFI7508-24

FIGURE 9. Frequency Discriminator
ENVELOPE DETECTOR (Figures tOB and tOb)

An envelope detector can be made by using the one-shot's

absence (see Figure 10a). The same circuit can also be
employed for a specific frequency input as a Schmitt trigger
to obviate input trigger problems associated with hysteresis
and slow varying, noisy wllveforms (see Figure 10b). (Retriggerable device required.)

retrigger mode. The time constant of the device is selected
to be slightly longer than the period of each cycle within the
input pulse burst. Two distinct DC levels are present at the
output for the duration of the input pulse burst and for its

Vee
VINJ\A

Rx

aJ1SL

ex

TL/FI7508-27

FIGURE 10b. Schmitt Trigger
VIN

o·s

TUFI7508-26

VIN

VOUT

u

ru

FIGURE 10a. Envelope Detector (Retriggerable Device Required)
1-28

TL/FI7508-28

r-----------------------------------------------------------------,~

PULSE GENERATOR (Figure 11)
Two one-shots can be connected together to form a pulse
generator capable of variable frequency and independent
duty cycle control. The RXI and CXl of 0-81 determine

the frequency developed at output 01. RX2 and CX2 of
0-82 determine the output pulse width at 02. (Retriggerable device required.)

Z
~

.....

I\)

Vcc

TL/FI7508-29

u

u

L

DUTY CYCLE

~

RX2 CX2
RX1 CX1

FREQ~ _ _
I_
KRX1 CX1
TL/FI7508-30

FIGURE 11. Pulse Generator (Retriggerable Device Required)
Note: K is the multiplication factor dependent of the device. Arrow indicates edge·trigger mode.

DELAYED PULSE GENERATOR WITH OVERRIDE TO
TERMINATE OUTPUT PULSE (Figure 12)
An input pulse of a particular width can be delayed with the
circuit shown in Figure 12. Preselected values of RXI and
CXl determine the delay time via 0-81, while preselected

values of RX2 and CX2 determine the output pulse width
through 0-82. The override input can additionally serve to
modify the output pulse width.

Vee

R"

C"

V,.
0·S2
CLR

ii,
ii,
Q,

CLEAR~__

.""_

n
____________r-l____
TL/F/7508-32

I

OVERRIDE
TLlF/7508-31

FIGURE 12. Delayed Pulse Generator with Override to Terminate Output Pulse

1-29

III

MISSING PULSE DETECTOR (Figure 13)
By setting the time constent of 0-S1 through RX1 and CX1
to be the least one full period of the incoming pulse period,
the one-shot will be continuously retriggered as long as no
missing pulse occurs. Hence, 0 1 remains LOW until a pulse

is missing in the incoming pulse train, which then triggers

0-S2 and produces an indicating pulse at Q2. (Retriggerable device required.)

Vee

RX'

VIN

t

Rn

ex,

eX!

t

0,
D-S1

0,

02
":"

.--- ..
I
I

VIN

TL/F/75D8-33

I
I

I

__________________ ____________
~n~

TLlF/75D8-34

FIGURE 13. Missing Pulse Detector (Retriggerable Device Required)
PULSE WIDTH DETECTOR (Figure 14)
The circuit of Figure 14 produces an output pulse at VOUT if
the pulse width at VIN is wider than the predetermined pulse
width set by Rx and Cx.
Vee

Rx

ex
0,

Q,L----'-,

VOUT

Vx

o·s

TLlFI7508-35

FIGURE 14. Pulae Width Detector

1-30

'--_. .n___

u

Vx

VOUT

TL/FI7508-36

FIGURE 14. Pulse Width Detector (Continued)
BAND PASS FILTER (FIgure 15)
The band pass of the circuit is determined by the time constants of the two low-pass filters represented by 0-S1 and
0-S2. With the output at 02 delayed by C, the D-flip flop

(D-FF) clocks HIGH only when the cutoff frequency of 0-S2
has been exceeded. The output at 03 is gated with the delayed input pulse train at 04 to produce the desired output.
(Retriggerable device required.)

Vee

0,

0,
O·Sl

Y,N

ii,

T

C

elK

0.

D.

VOUT

IJ.FF

IJ.FF

0·82

ii,

0,

0.

ii,

CLK
CLR

-=-

. TLlFI7506-37

II
nn_ _ _ _ _ __
______......'n ununUU'

VOUT

TLlFI7508-38

FIGURE 16. Band Pass Filter (Retriggerable Device Required)

1-31

CN

~
.,

Z

......f:>cI-4~L..:..J>e-l-l~:>-. + SEP elK
03
FF

TL/FI7508-40

FIGURE 16. FM Data Separator (Continued)

PHASE-LOCKED LOOP YCO (Figure 17)
The circuit shown in F/{Jure 17 represents the VCO in the
data separation part of a rotational memory storage system
which generates the bit rate synchronous clocks for write
data timing and for establishing the read data windows.

phase-error summing node. When the one-shot times out, if
this occurs after the 2F clock has reset the phase detector
FF to a lOW output, a positive pulse will be seen at the
summing node until both the one-shot and the FF are reset.
Any positive pulse will be reflected by a negative change in
the op-amp output, which is integrated and reduces the positive control voltage at the veo input in direct proportion to
the duration of the phase-error pulse. A negative phase-error pulse occurs when the phase detector FF remains set
longer than the one-shot.
Negative phase-error pulse causes the integrated control
voltage to swing positive in direct proportion to the duration
of the phase-error pulse. It is recommended that a clamping
circuit be connected to the output of the op-amp to prevent
the VCO control voltage from going negative or more positive than necessary. A back-to-back diode pair connected
between the op-amp and the VCO is highly recommended,
for it will present a high impedance to the veo input during
locked mode. This way, stable and smooth operation of the
PlO circuit .is assured.

The op-amp that performs the phase-lock control operates
by having its inverting input be driven by two sources that
normally buck one another. One source is the one-shot, the
other source is the phase detector flip-flop. When set, the
one-shot, through an inverter, supplies a HIGH-level voltage
to the summing node of the op-amp and the phase detector
FF, also through an inverter, supplies a canceling lOW-level input.
It is only when the two sources are out of phase with each
other, that is one HIGH and the other lOW, that a positiveor negative-going phase error will be applied to the op-amp
to effect a change in the VCO frequency. Figure 17 illustrates the process of phase-error detection and correction
when synchronizing to a data bit pattern. The rising edge of
each pulse at DATA+PlO clocks the one-shot lOW and
the phase detector FF HIGH. Since both outputs are still
bucking each other, no change will be observed at the

1-33

II

N

I?Z

r-------------------------------------------------------------------------,
2F Bit Rate Synchronous Read/Write Clock
Vee

III(

READ
READ DATA

~-,._

ENABLE
lOCAL OSCillATOR

Rm

Vee
DATA+PlD

~r-----------------~_tD3
D·S

2F

ClK

TLlFI7508-41

BIT CEll
MRZ DATA

I

MFM DATA

O·S(o.)

veo (2F)

~ERROR

nl-----~--.....,LnJr-----

- -....

TL/F/75OB-42

FIGURE 17. Phase-Locked Loop Voltage Controlled Oscillator
A FINAL NOTE

ACKNOWLEDGEMENT

It is hoped that this brief note will clarify many pertinent and
subtle points on the use and testing of one-shots. We invite
your comments to this application note and solicit your constructive criticism to help us improve our service to you.

The author wishes to thank Stephen Wong, Bill Llewellyn,
Walt Sirovy, Dennis Worden, Stephen Yuen, Weber Lau,
Chris Henry and Michelle Fong for their help and guidance.

1-34

National Semiconductor Corp.
Application Note 476
WaltSirovy

Guide to ALS and AS
INTRODUCTION
Since the introduction of the first bipolar Transistor-Transistor Logic (TTL) family (DM54174), system designers have
wanted more speed, less power consumption, or a combination of the two attributes. These requirements have
spawned other logic families such as the DM54174L (low
power), DM54174LS (low power Schottky), DM54174S
(Schottky), etc., in order to give the system deSigners some
choice.
The most common way of comparing logic families is by
using their speed-power products. Figure 1 displays a
graphical representation of the logic families now available.
The addition of the Advanced logic families broadens the
spectrum of speed/power characteristics. This will allow the
sys~em designer to optimize his system's speed/power
product by using performance budgeting. Performance budgeting is the intermixing of logic families to achieve the best
speed/power product for a design. This is possible since
bipolar logic families are designed to be fully compatible
with each other. When the designer uses.performance budgeting he is trading power consumption for-speed. The designer identifies the_ speed critical paths and uses the fastest products to optimize the system's speed. For all other
non-critical speed paths, the logic family with the best
speed/power product should be used to optimize his system's power consumption. Since no other family offers the
speed capability of AS and the low power of ALS, these
families are the best choice when performance budgeting.
20

es

18
16

14
12
10

8
6

eAS

"
2

eALS

eLS

eL

~~~~~~~~p

1 2 3 "

5 6 7 8 9 10 33

SPEED (ns)
TL/F/9158-1

FIGURE 1_ Speed Power Product Comparison
Each of the logic families is a compromise between speed
and power consumption. Since the speed/power product is
approximately a constant, a decrease in the power consumption must be traded off in a slowing down of the device
and vice versa. The power consumption of a device is the
easiest to control. By simply increasing the resistive values
in the circuit the power consumption can be decreased.
The device speed can be handled in a similar manner. The
speed of a device is limited by the charge stored in the
transistors of the circuits. The time to remove this charge is
proportional to the capacitance of the transistor and the current s\lpplied. In the early speed improvements, the current
aspect of this relationship was involved. A simple decrease
in the resistive values in the circuits was done. This did help
the speed but it greatly increased the power consumption.
The advent of the Schottky transistor helped increase the

device speed. The Schottky transistor adds a Schottky
clamp diode between the base and collector of the transistor. The Schottky clamp diode has a lower forward voltage
(about 0.4V) than the base-collector junction diode (about
0.5V): When the transistor is turned on the base current
drives the transistor toward saturation and the collector voltage drops. This causes the Schottky clamp diode to conduct and divert some of the base current from the base-collector junction of the transistor. This clamp diode prevents
the transistor from going into deep saturation. This allows
the transistor to recover quickly by decreasing the transistor
storage time. The Schottky logic families (DM54174S,
DM54174LS) used the Schottky transistor and low values of
resistors to achieve their high speeds.
Now NSC has introduced the Advanced Low Power
Schottky (ALS) and the Advanced Schottky (AS) logic families. These families use a reduced transistor size, advanced
process technology, and innovative design techniques to
achieve the improved device speeds. This article will discuss various aspects of the Advanced logic families including deSign goals, application goals, circuit design enhancements, family features, and some helpful application tips.

ADVANCED LOGIC FAMILIES DESIGN GOALS
For the Advanced logic families our main design goal was to
reduce the power consumption while improving the speed
of the parts. We also set the requirement that the Advanced
logic parts be pin for pin compatible with existing logic families to allow ease of system upgrading and interfacing with
existing products.
The design goals for ALS family were to produce a complete logic family which would achieve one half the propagation delays of OM54/74LS at one half the power dissipation
of DM54174LS and improve the capability of the outputs to
drive 50 to 1000 lines.
For the AS family the design goal was to produce a complete logic family which would achieve one half the propagation delays of DM54174S at one third the power dissipation
of DM54/74S.
We set some goals for both Advanced logic families that
were more application related because of our experience
with other logic families. These goals were to improve the
input characteristics and line driving capability, reduce internally generated supply current spikes, eliminate parasitic
failure modes and decoding glitches, and provide better
electro-static discharge protection.

AN OVERVIEW OF THE ADVANCED LOGIC FAMILIES
The Advanced logic families (ALS & AS) have included most
of the functions now present in the DM54174LS and
OM54/74S families. Some additions have been made to the
Advanced families over the OM54174LS and S families in
order to make the families more complete. Both of the Advanced families have added a better (more complete) selection of octal bus transceivers, transparent latches and 0type flip-flops. A series of logic gate drivers (800 series)
have been added to the ALS family. These devices have
increased logic high and low current capabilities which allow
the driving of high capacitive lines. These drivers have also
been added to the AS family but have been deSignated the
1000 series. The ALS family has also added a series of gate

1-35

Another of the design enhancements is the use of a PNP
transistor in the input circuitry. The use of the PNP transistor
reduces the typical IlL of these circuits (-10 p.A for ALS
and -50 p.Afor AS). When using a PNP transistor the
equation for IlL becomes:

buffers (1000 series) which increase the fanout of these
devices by increasing the logic low and high driving capabilities (but not as much as the 800 series).
The datasheets for the Advanced Logic devices have been
improved in order to more accurately reflect application requirements'lind to reduce the need for special testing. The
supply voltage range for the commercial products has been
defined as 10% (4.5V to 5.5V) instead of 5% as all other
bipolar logic have done in the past. The high level output
iloltage specification has been changed to Vcc-2 to allow
easier interfacing with CMOS parts which have Vee sensitive thresholds and to better reflect the actual operation of
the parts. The output drive current (10) is measured at a
forcing voltage of 2.25V instead of OV used by other logic
families. This demonstrates that the Advanced logic families
have sourcing capability through the threshold level of the
next gate. The low level input current (Ill) specification has
been reduced from -400 p.A used for DM54/74LS to -100
p.A for ALS. This indicates that ALS devices' IlL current is
less of a dominant factor in the limiting of device fanout.
Current sinking capability (Iou for the AS family of
TRI-STATE devices has been substantially increased (20 to
48 mAl over the DM54/74S family to allow the connection
of these parts to a heavily loaded bus. The dynamic characteristics (propagation delays, etc.) have been specified over
the supply voltage and temperature range. Also the output
load used to test the dynamic characteristics has been simplified to allow easier construction of hardware for automatic test equipment and still reflect in-circuit operation. These
items should give the designer a higher confidence level of
the product used in his systems. Table 1 shows a comparison between ALSI AS and LS/S product. Appendix A includes generic datasheets for ALS and AS family of products.
TABLE 1. Family Comparison
Typical
Delay
(ns)

Typical
Power
(mW)

IOL
Max
(mA)

IlL
Max
(mA)

LSSTD

8

2

8

-0.4

Logic
Family

LSTS

8

6

24

-0.4

HC

8

-

4

-0.001

ALSSTD

4

1.3

8

-0.1

ALS BUFFER

4

3

24

-0.1

54S

3

20

20

-2.0

AS

1.5

7.6

20

-0.5

2

8

48

-0.5

AS BUFFER
Vee

=

5V,

Ct. =

IlL = Vee - VBE(OI) - VI
R(hFE(OI) + 1)

>.
I

4

~

~

...g
:::>

I!:
:::>

2

0

rt
Q.2 Q.4 Q.6

0.8 1.0 1.2 1.4 1.6

VI - INPUT VOLTAGE - V
TL/F/9158-2

FIGURE 2. VIN VB VOUT
Past logic families which used diodes or NPN transistors at
the inputs had higher IlL since they lacked the gain (hF8 of
the PNP transistor. The PNP transistor of the Advanced
families effectively eliminates the IlL current from being a
dominant limiting factor in device fanout. The fanout constraints are now primarily associated with AC loading.
The input clamping and electrostatic discharge protection
methods have also been improved. Past circuits have used
diodes to do the negative voltage clamping action. The Advanced logic circuits use a Schottky transistor with the base
and the emitter shorted to ground. The forward resistance
of the base-collector is less than the diodes used in previous logic families. This lower resistance allows higher currents to be absorbed. This has improved the electrostatic
discharge resistance from less than 1000V to 4000V. This
gives the Advanced logic families a non-sensitive rating for
the MIL-M-38510 people.
The lower output characteristic has been improved by the
addition of the transistor (09) for the AS parts and the diode
(D3) for the ALS. These elements provide additional base
drive for the lower output transistor (05) when the output
transitions from a high to low state. Thus the transistor pair
03 and 05 acts as a darlington pair. The AS parts use a
transistor instead of the diode because of the higher drive
requirements. Figure 3 shows the Advance families output

1

...i3

15 pF

180

I

CIRCUIT DESIGN ENHANCEMENTS
One of the design enhancements of the Advanced logic
families is the improvement of the input threshold voltage.
Figures 4 (ALS schematic) and 5 (AS schematiC) are used
for reference for the following discussion. The input threshold is determined by the following equation.

'"
'":::>
<..>

140

~

100

:::>

60

...
...
11.

:::>
0

20

Vthreshold = VBE(02) + VBE(03) + VBE(04) - VBE(OI)
The typical VBE of these transistors is 0.7V. Therefore the
typical threshold voltage is 1.4V. This optimizes the threshold point between the high and low level input voltages. This
provides maximum noise immunity. Figure 2 demonstrates
the threshold enhancement.

-'
Q

2

3

Vo - OUTPUT VOLTAGE(V)
TUF/9158-3

FIGURE 3. Low Logic Level VOUT VB lOUT
1-36

The AS circuits incorporate additional circuitry to reduce
current supply spikes. During a low to high transition a sup·
ply current spike can be produced because the lower output
transistor (aS) remains temporarily on. This can increase
the power consumed by the circuit especially at high fre·
quencies. The lower output transistor remains on because
of charge being coupled by this transistor's base-collector
capacitance. The circuitry used to eliminate this problem is
the addition of a transistor (09), two diodes (08 & 011), and
two resistors (R9 & R10). This circuit has been named the
Miller killer. The diode (08) is used as a capacitor to couple
charge into the base of the transistor, 09, during a low to
high transition of the output. Thus 09 turns on providing a
means of turning off the lower output transistor (aS). This
circuitry is not required for most ALS devices due to the
lower frequency of operation and smaller output structures.
APPLICATION RELATED DESIGN IMPROVEMENTS
A major consideration in the layout of the Advanced logic
families was their response to negative transients. The Advanced logic families have high transition rates which can
generate large reflections ( - 2.5 volts) when terminated into
a high impedance. A method of limiting reflections is to use
a clamp diode. All the Advanced logic devices include
Schottky clamp diodes on both the inputs and outputs.
These clamp diodes may have to handle peak currents of
30 to 60 rnA. At these currents substrate junctions will be·
come forward biased.

Tl/F/9158-5

FIGURE 4. ALSOO Schematic
r-----~~~--------~--_.--ovre

Rl

R2

R3

Figure 6 shows a cross sectional view of the area of an
Advanced logiC device where a negative transient may be a
problem. A negative transient on an input or output tank (the
structure in the center) will forward bias the substrate to N
epi junction. This will form a parasitic NPN transistor between adjacent structures. If the adjacent structure is an
input or output the only impact will be an increase in the
leakage current. Since most of the devices have an active
totem pole output design a logic state change does not hap·
pen. If the adjacent structure is a collector of an internal
transistor the increase in the leakage current may cause a
logic state change from a high logic state to a low logic
state. This state change in a combinational logiC part can
propagate to the output and cause a glitch which can affect
the system performance. If the adjacent transistor is part of
a flip-flop a change in the logic state can happen. This can
cause a sequential error in the system.

R4

INTERNAl
TRANSISTER
COLLECTOR
nEpl

TlIF/9158-4

FIGURE 5. ASOO Schematic
characteristic compared to the old Schottky families. Note
that the current sink capability of the AS family takes off at
1.5V while the OM54174S family remains flat. The ALS
graph shows a similar characteristic but the break point is
1.8V.

n+

The Advanced logic families include the output shaping cir·
cuit used in most modern bipolar logic families. This circuit
consisting of transistor 04, resistor R7 and resistor R8
helps to turn off the low output transistor
during the low
to high output transition. The diode 07 is used to help turn
off the upper output transistor (07).

OXIOE
ISOLATION

p+

NEGATIVE CURRENT
TRANSIENT (INPUT
OR OUTPUT)
n Epl

n+

OXIDE
ISOlATION

p+

as

ADJACENT
INPUT OR
OUTPUT
nEpl

n+

TlIF/9158-6

FIGURE 6. Parasitic Failures Modes

1-37

..

Ie
INTERNAL
TRANSISTER
COLLECTOR
nEpl

I

Z

CC

NEGATIVE CURRENT
TRANSIENT (INPUT
OR OUTPUT)
OXIDE
ISOLATION

nEpl

OXIDE
ISOLATION

n+

ADJACENT
INPUT OR
OUTPUT
nEpl

n+

TLlF19158-7

FIGURE 7. Solution to Parasitic Failures Modes
Figure 7 demonstrates the method we use to minimize this
problem. A grounded N + guard ring around all input and
output transistors is included. The guard ring increases the
spacing between the two structures thus reducing the effiCiency of the parasitic transistor. The grounded guard ring
also acts as an energy well which collects the majority of
the electrons injected by the parasitic transistor. An example of the amount of protection achieved can be demonstrated by looking at the ALS74. Without the guard ring this
device will change state with only -5 mA input current. With
a guard ring the device can withstand in excess of -35 mA
input current with no change in logic state and only a few
tenths of a volt degradation of the high state logic level.

SELECT

TLlF19158-9

FIGURE 9. New Method of Decoding
PROCESS DESCRIPTION
A major factor which allowed us to meet our design goals is
the Advanced Schottky process. The Advanced Schottky
process uses oxide isolation and ion implantation. This allows the physical size of the transistors to be reduced.

Another problem associated with older logic families is decoding glitches. The old method of decoding is demonstrated in Figure 8. A decoding glitch occurs when the A and B
inputs are at a high logic level and the select input transitions from a low to high logic level. The propagation delay
from a high to a low logic level is faster for the inverting gate
than the propagation delay from a low to high logiC level is
for the non-inverting gate. This causes both the SEL and the
SEL' lines to be at a low logic level for a short time. If both
these lines are at a low logic level at the same time the Y
output will transition to a low logic level even if the A and B
inputs are at a high logic level. With the circuit used for the
Advanced logiC families (Figure 9) the SEL' line cannot go
to a low logic level until the SEL line goes to a high logic
level since the SELECT and SEL lines are logically connected with a NAND gate.

SELECT

Y

Figure 10 shows the size comparison between a junction
isolated and oxide isolated transistors. The oxide isolated
transistor is more than half the size of the junction isolated
transistor. This reduction in size provides higher packing
density and, most important, smaller active junction areas
(2.5,... emitter width). The oxide isolated structure has much
smaller capacitance due to the reduced geometries thus
improving the speed/power performance (5 GHz FTJ.
Figure 11 shows a cross sectional view comparison between the junction and oxide isolation processes. In the oxide isolated process the emitter of the transistor contacts
the oxide isolation directly (walled emitter). This greatly reduces the side wall capacitance since the capacitance is
inversely proportional to the dielectric constant and dielectric constant between silicon/oxide is much smaller than the
dielectric constant between two sections of silicon.

Y

Ion implantation is a technique of introducing impurities by
bombarding the host material with a beam of ions. This
technique is superior to the deposition method used in previous processes because it is easier to control the amount
of impurities introduced into the silicon. The deposition
method relies on control of diffusion time, diffusion temperature, gasflow rate and surface cleaniness. Ion implantation
relies on the control of only current and voltage of the machine.
Figure 12 is a lengthwise cross sectional view of the oxide
isolated transistor. From this figure it can be seen that the
limiting factor of the size of the transistor is the metal interconnects and the spacing between the metal.

TLIF19158-8

FIGURE 8. Old Method of Decoding

1-38

,--------------------------------------------------------------------,

~

z

•

oIiIo

~

SCHOTTKY

2

t

2

4.60 MIL DEVICE AREA 2.03 MIL
2
2
BASE 0.67 MIL BASE AREA 0.24 MIL
2
2
0.16 MIL EMITTER AREA 0.03 MIL

t
EMITTER

t
COLLECTOR

JUNCTION ISOLATED

OXIDE ISOLATED

t
TL/F 19158-10

FIGURE 10. Top View of Junction and Oxide Isolated Transistors

METAL

'\-----+--

EMITIER

1--------1-- BASE

1--------1-- EPI
OXIDE ISOLATION

p+ CHANNEL STOP

TL/F/9158-11

FIGURE 11. Cross Sectional View of Oxide Isolated Transistor

BASE
METAL

I

I

I

I

I

I

lp+

~

N+

P
N EPITAXIAL LAYER

B

I

I
N+

OXIDE
ISOLATION

COLLECTOR
METAL

EMITIER
METAL

N+

N+

OXIDE
ISOLATION

II

~
TL/F/9158-12

FIGURE 12. Cross Sectional View of Oxide Isolated Transistor

1-39

q)

"'=I'
"""
Z•

c(

r------------------------------------------------------------------------------------------,
NOISE CONSIDERATIONS

LINE REFLECTIONS
Line reflection is another source of noise. Line reflection is
caused by a difference in the impedance of the transmission
line and the resistance of the line load. Each transmission
line has a characteristic impedance which is the initial resistance seen by a signal entering" the line.
Lets consider a simple circuit which includes a voltage
source, a switch, a transmission line and a resistive load.
The characteristic impedance of the transmission line is Z
and the resistive load is R. The resistive load, R, can be
referred to as the terminating resistance. When the switch is
closed the initial current flowing into the line will be I = VIZ.
A current step of magnitude I and voltage step of V flows
down the transmission line. The current required by the load
at the end of the transmission line is VIR. If the characteristics impedance of the transmission line does not equal the
load resistance a partial reflection of the signal will occur.

When a digital system is being designed, the designer works
with a perfect mathematical system. Once the designer
starts to layout his design he enters the real world where
everything is not perfect. There are pitfalls in the laying out
circuits that will make a perfectly good logic circuit work
incorrectly and unpredictably. One of the major considerations in the layout of a circuit is noise. Noise is extraneous
currents and voltages introduced into or produced by the
circuit. When slower circuits are used consideration of noise
is not as important as it is for fast circuits such as the Advanced Logic families. This is true because the slower circuits take longer to respond to noise and characteristically
noise is pulses of short duration. The Advanced Logic families have addressed noise produced by the device itself, as
mentioned previously, so it will not be addressed here.
Noise can be introduced by several methods: external to the
system, cross talk between lines, power supply spikes and
line reflections. Each of these problems will be examined
and solutions presented.

One can define a reflection coefficient (Rho) as the reflected voltage amplitude divided by the incident voltage amplitude. It can be mathematically shown that the Rho = [R Zl I [R + Zl. If R equals 0 (short circuit) the Rho equals -1.
If R equals infinity (open circuit) the Rho equals 1. If R = Z
the Rho equals 0 which indicates that there will be no reflection. The magnitude of the voltage at the load resistance is
initially V(1 + Rho). If a reflection initially occurs, further
reflections will occur until I = VIR. Possible waveforms are
shown in Figure 13.

NOISE MARGIN
Each logic family has a certain amount of noise margin.
Noise margin is the voltage amplitude of an extraneous signal that can be added to the input level of a logic circuit
before change in the output logic voltage level could occur.
Worst case noise margin is defined as the difference between the minimum high voltage [VOH (2.5Vll minus the
maximum input high voltage [VIH (2V)l or the maximum inPllt low voltage [VIL (0.8Vll minus the maximum output low
voltage [VOL (0.5V)l whichever is smaller. For the ALS and
AS families these numbers turn out to be 0.5 and 0.3 volts
respectively.
POWER SUPPLY SPIKES
Power supply spikes can be introduced to the system externally or generated internally. As gates switch from one logic
state to another, their current drain on the supply will
change. The more gates that switch at the same time the
greater the current drain on the supply will be. The speed of
the changes is also a factor as will be demonstrated. These
current changes produce voltage variations because of supply line resistance and inductance.

R(2

R)2
TLlF/915B-13

FIGURE 13. Waveforms for Improperly
Terminated Transmission Lines
It can be shown that the duration of each reflection is equal
to twice the time it takes for the signal to propagate down
the transmission line. Generally, gates do not respond to a
signal that is shorter than the propagation delay of device
itself. A good rule of thumb to use to determine if a transmission line requires termination is if the time required for the
Signal to propagate down the transmission line is greater
than one quarter of the propagation delay of the device the
line should be terminated.

In most designs the supply lead inductance is the dominant
factor. For a current change di in time dt with a lead inductance of L, the resulting noise voltage is defined as V =
L[di/dtl. For a octal ALS buffer the current change can be
10 mA, the transition time can be 3 ns, and for a 15 cm line
on a printed circuit board the inductance can be 0.1 ,..,H.
This will give a noise pulse of 333 mV. With several circuits
switching at the same time this could produce a problem.
The solution to the problem is to include several decoupling
capacitors evenly distributed around the board. Ceramic
disc capaCitors of 0.01 ,..,F are otten used. If a 0.01 ,..,F capaCitor is used in the above example the noise pulse would
be greatly reduced. For a capacitor C and a current change
di in the time dt the voltage change is represented by V =
[(di) (dt)l/C. This gives a noise pulse of 3 mV. Usually one
capacitor for every five ICs is sufficient. If more high power
ICs (buffers and line drivers) are used a one to one ratio of
capacitor to ICs might be required. Since the transition time
of AS devices is so fast, each IC shoulCl have a bypass
capacitor. These capacitors are inexpensive and will greatly
increase the reliability of your design.

Lets calculated the maximum line length for some Advanced Logic family devices. Lets assume that the signal
travels down the line at the speed of light (3 X 10 to the
eight m/s). The maximum line length is the speed of light
times cine quarter the propagation delay of the device. The
propagation delay of an ALS gate is about 4 ns. This would
give a safe maximum length of the line of 0.3m (about 1 tt).
The propagation delay of an AS gate is about 2 ns. This
would give a safe maximum length of the line of 0.15m
(about 0.5 tt).

I' nother method of termination of a transmission line is a
series termination. It can be shown that the initial step received at an open circuit termination is twice the input step.

1-40

If we have a series resistor at the transmitter that is equal to
the characteristic impedance of the line the reflection would
be absorbed by the series resistance. This method requires
a high impedance receiver but uses less power than the
previous method.

N = # of wired-OR outputs
R . - VCC(max) - VOL
(min) IOL - M x IlL
R
- VCC(min) - VOH
(max)- NxlOH + MxllH

CROSSTALK
Cross talk is the coupling of a signal from one line to an
adjacent line. It is caused by the mutual inductance and
capacitance between Signal lines. Long parallel lines are the
most susceptible to this problem. To minimize the effects of
cross talk, proper shielding, grounding and decoupling
should be done. On lines which may be particularly sensitive
to cross talk, the distance between these lines should be
increased.

M = # of inputs being driven
IlL = LOW lavel input current
IIH = HIGH level input current
VOL = output LOW voltage (O.5V)
VOH = output HIGH voltage (2.5)
IOL = LOW level fanout current
IOH = ICEX = output HIGH current
Example: Two ALS03 gate outputs driving three LS gates.

Use flat cable with alternate signal/ground wires, coaxial
cable, signal lines (PCB track) above ground plane with the
minimum distance between lines equal to the distance between ground plane and signal plane, or twisted pairs to
minimize cross talk.

R . =
5.25V - O.5V
= 6980
(min)
8mA - 3xO.4mA
R
=
4.75V - 2.5V
= 16 kO
(max)
2xO.1 mA + 3xO.02mA

Unused Inputs
Unused inputs which are left open circuited can be a source
of noise. An open circuited input settles at the threshold
voltage of that node. It can act as an antenna and accept a
signal. To avoid this problem any unused input should be
tied to a potential that will not cause a logic error. For example, unused inputs of AND gates, NAND gates, and active
low presets and clears of flip-flops should be tied to a high
potential. Unused inputs of NOR gates should be tied to
ground. Unused inputs that are tied to a high potential can
be connected directly to the supply voltage as long as the
5.5V maximum is not exceeded. A better method is to connect unused inputs to a high potential through a resistor
(1 kO or greater) to the supply voltage. This will give some
protection in case this input is shorted to ground. Several
inputs can be connected to this resistor.

The R range for the pull-up is between 698 and 16 kO. The
lower resistor values will provide faster speeds while the
higher resistances give lower power dissipation.

SUMMARY
•
•
•
•

Pin compatible with other 5V bipolar families
Faster propagation delays
Lower power consumption
Better selection of octal bus transceivers, transparent
latches, and D-type flip-flops

• Addition of series of line drivers
• Addition of series of buffers
• Dynamic characteristics specified over supply voltage
and temperature range
• Improved input threshold voltage
• Improved ESD protection
• Better pin-to-pin isolation

Open-Collector Outputs
All open collector outputs, whether used alone or in a wiredOR configuration, requires an external pull-up resistor. The
resistor value is dependent upon the fanout of the OR tie
and the number of devices in the OR tie. R(min) is determined so that if only one output is LOW the maximum allowable OR tie fanout is not surpassed. The R(max) value is
calculated with all the OR tied outputs HIGH to sustain the
necessary VOH.

• Elimination of decoding glitches

II

1-41

~

z

APPENDIX

III(

Recommended Operating Conditions Advanced Low Power Schottky
Symbol

Standard
Output

Parameter

Buffer
Output

Bus Driver
Output

Max

Min

Max

Min

Max

5.5

4.5

5.5

4.5

5.5

V

0.8

V

Vee

Supply Voltage

54/74ALS

4.5

VIH

High Level Input Voltage

54174ALS

2

Vil

Low Level Output Voltage

54174ALS

0.8

10H

High Level Output Current

2

2
0.8

V

54ALS

-0.4

-1

-12

74ALS

-0.4

-2.6

-15

VOH(l)

High Level Output Voltage

54/74ALS

5.5

5.5

5.5

10l

Low Level Output Current
(Note 2)

54174ALS

4

12

12

74ALS

8

24

24

74ALS -1
TA
TA

Operating Free-Air Temperature
Temperature

Units

Min

mA
V

mA

48

54ALS

-55

125

-55

125

-55

125

74ALS

0

70

0

70

0

70

·C

Note 1: For open-collector outputs.
Note 2: The extended limits (-1) apply only

nVee is maintained between 4.75 and 5.25V. These parts are offered as a commercial version only.

Electrical Characteristics Advanced Low Power Schottky
Symbol

Parameter

Standard Output

Conditions

Min
VIK

Input Clamp
Voltage

Vee = 4.5V
11=-18mA

VOH

High Level
Output Voltage

Vee = 4.5V
10H = Max

Typ(1) Max

Buffer Output
Min

Typ(1) Max

2.4

, Vee- 2

10H

High Level
Output Current

Vee = 4.5V
VOH = 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V 54174ALS
10l = Max 74ALS

Input Current at
Maximum Input
Voltage

Vee = 5.5V
VI = 7V

IIH

High Level Input
Current

Vee = 5.5V
VI = 2.7V

III

Low Level Input
Current

Vee = 5.5V
VI = 0.4V

10

Output Drive
Current

Vee = 5.5V
Vo = 2.25V

10ZH

Off·State Output Vee = 5.5V
Current, High Level Vo = 2.7V
Voltage Applied

II

IOZl

lee

3.2

-1.5
2

3.2

2.4

3.2

0.1

0.1

V

V

0.1

0.25

0.4

0.25

0.4

0.25

0.4

0.35

0.5

0.35

0.5

0.35

0.5

mA
V

0.1

0.1

0.1

mA

20

20

20

p.A

-0.05 -0.1

-0.02 -0.1
-112

-30

Units

Typ(1) Max

Vee- 2

Vee- 2

-30

-112

-0.05 -0.1
-30

mA

-112 mA

20

p.A

0.1

0.1

mA

-20

-20

p.A

20

Off·State Output Vee = 5.5V 1/0 Ports
Current, Low Level Vo = 0.4V
Non 1/0
Voltage Applied
Supply Current

Min

-1.5

-1.5

Vee = 4.5V
10H = -3mA
Vee = 4.5V to 5.5V
10H = -0.4mA

Bus Driver Output

mA

Vee = 5.5V

1-42

Recommended Operating Conditions Advanced Schottky
Symbol

Buffer
Output

Standard
Output

Parameter

Bus Driver

Output

Min

Max

Min

Max

Min

Max

5.5

4.5

5.5

4.5

5.5

Vee

Supply Voltage

54174AS

4.5

VIH

High Level Input Voltage

54174AS

2

Vil

Low Level Output Voltage

54174AS

0.8

0.8

0.8

10H

High Level Output Current

54AS

-2

-12

-40

74AS

-2

-15

-48

2

V

High Level Output Voltage

54/74AS

5.5

5.5

5.5

10l

Low Level Output Current

54174AS

20

32

40

74AS

20

48

48

Operating Free-Air Temperature

Note

V

2

VOH(1)

TA

Units

54AS

-55

125

-55

125

-55

125

74AS

0

70

0

70

0

70

V
mA
V

mA
·C

1: For open-collector parts.

Electrical Characteristics Advanced Schottky
Symbol

Parameter

Conditions

Standard Output
Typ(1) Max

Min
VIK

Input Clamp
Voltage

Vee = 4.5V
II = -18mA

VOH

High Level
Output Voltage

Vee = 4.5V
10H = Max

VOL

Low Level Output
Voltage

II

Input Current at
Maximum Input
Voltage

3.2

0.35

0.5

0.35

0.5

0.5

V

0.1

mA

20

/LA

Low Level Input
Current

Vee = 5.5V
VI = O.4V

-0.5

-0.5

10

Output Drive
Current

Vee = 5.5V
Vo = 2.25V

10ZH

Off-State Output Vee = 5.5V
Current, High Level Vo = 2.7V
Voltage Applied

=

mA

0.1

III

-30

0.35

0.1

0.1

20

Vee

V

3.2

0.1

0.1

20

Supply Current

-1.2

Vee- 2

Vee- 2

Vee = 5.5V
VI = 2.7V

lee

Units

Typ(1) Max

V
Vee- 2

High Level Input
Current

Off-State Output Vee = 5.5V
Current, Low Level Vo = 0.4V
Voltage Applied

Min

2

IIH

10Zl

Bus Driver Output

-1.2
2.4

= 4.5V
= 5.5V
Vee = 4.5V
10l = Max
Vee = 5.5V
VI = 7V

High Level Output Vee
Current
VOH

Typ(1) Max

-1.2

Vee = 4.5V to 5.5V
10H = -2mA
10H

Buffer Output
Min

-112

-30

-112

50

-0.5 mA
-30

-112 mA

50

/LA

I/O Ports

-0.5

-0.5 mA

Non I/O

-50

-50

/LA
mA

5.5V

1-43

II

~

Functional Index/Selection Guide

'Several methods are used to represent typical values. For propagation delay typical values, the average of the typical values of the two delays are used.
[tPHl!TYPl ; IplH!TYPlj
For power dissipation, the average of the typical values of current for all states the outputs can achieve is used (ICCl. ICCH' Iccz.) This current value is mulliplied by
nominal supply voltage (5V), and In some cases divided by the number of galas, bRs, etc. All other typical values are singular typicals.

Adders
Description

5ingle 4-Bit
Full Adders

Device Type

54174L5283
541745283

54174L583A

Typ' Carry
Time (ns)
12
8.5
12

Package
Availability

Typ' Power
Diss.lBit
(mW)

Typ' Add
Time (ns)

24
110
24

15
11
15

Mil

Com

J
J
J

N,M
N
N,WM

Page

t
t
t

Arithmetic Logic Units, Carry Look-Ahead Generators

Description

Device Type

4-BitALu/
Function
Generators

54/74A5181B

Carry
Look-Ahead
Generator

Typ'
Carry
Time
(ns)

Typ'
Add
Time
(ns)

Typ'
Power
Diss.
Total
(mW)

Mil

Com

5
7
12.5
10
5

5
14
18
12
5

370
600
455
525
370

J
J
J
J
J

N
N
N
N
N

3-60

N/A
N/A
N/A
N/A

115
345
140
130

J
J
J
J

N
N
N
N

3-69

541745181
54174181
541745381
5417 4A5881 B

5
9
6
·6

54174A5182
541745182

54/74A5264
54174A5282

Package
Availability

Page

t
t
t
3-193

t
3-88
3-97

Buffers/Clock Drivers with Totem-Pole Outputs

Description

Dual4-lnput
NAND Buffers

LowLevel
Output
Current
(mA)

HighLevel
Output
Current
(mA)

Typ'
Prop.
Delay
Time
(n8)

Typ'
Power
Diss.
/Gate
(mW)

-1
-2.6
-3
-1
-2.6

4
4
4
4
4

3.5
3.5
44
3.6
3.6

J

54AL51020A
74AL51020A

12
24
60
12
24

54AL537A
74ALS37A
54L537
74L537
54/7437
54AL51000A
74AL51000A
54A51000A
74A51000A

12
24
12
24
48
12
24
40
48

-1
-2.6
-1.2
-1.2
-1.2
-1
-2.6
-40
-48

5
5
10
10
10.5
5
5
2
2

5
5
4.3
4.3
27
3.5
3.5
8.5
8.5

J

Device Type

54ALS40A
74ALS40A
54174540

Quad 2-lnput
NAND Buffers

t Please see the LS/S/TTL logic Oatabook for this datasheel.
1-44

Package
Availability
Mil

J
J

Com
N,M
N

J
J

2-54
2-54

t

N,M

2-295
2-295

N,M

2-50
2-50

t

J
J
J

Page

N,M
N
N,M
N
N

t

t
2-279
2-279
3-205
3-205

Buffers/Clock Drivers with Totem-Pole Outputs (Continued)
HighLevel
Output
Current
(mA)

Typ·
Prop.
Delay
Time
(ns)

Typ·
Power
Diss.
/Gate
(mW)

Description

Device Type

LowLevel
Output
Current
(mA)

Quad 2-lnput
NOR Buffers

54ALS28A
74ALS28A
54ALS1002A
721ALS1002A
54AS1036A
74AS1036A

12
24
12
24
40
48

-1
-2.6
-1
-2.6
-40
-48

3.7
3.7
3.7
3.7
2
2

4.5
4.5
4.5
4.5
9.7
9.7

54ALS1032A
74ALS1032A
54AS1032A
74AS1032A

12
24
40
48

-1
-2.6
-40
-48

5.5
5.5
2.5
2.5

5.7
5.7
14
14

54ALS1008A
74ALS1008A
54AS1008A
74AS1008A

12
24
40
48

-1
-2.6
-40
-48

5.6
5.6
2.5
2.5

4.7
4.7
12
12

J

Triple
3-lnput NAND

54ALS1010A
74ALS1010A

12
24

-1
-2.6

4
4

3.6
3.6

J

Triple
3-lnputAND

54ALS1011A
74ALS1011A

12
24

-1
-2.6

6.4
6.4

4.75
4.75

J

Hex Buffers

54ALS1034
74ALS1034
54AS1034A
74AS1034A

12
24
40
48

-12
-15
-40
-48

4.5
4.5
2.5
2.5

4.6
4.6
11.9
11.9

J

54ALS1004
74ALS1004
54AS1004A
74AS1004A

12
24
40
48

-12
-15
-40
-48

2.6
2.6
1.7
1.7

3.3
3.3
8.5
8.5

J

LowLevel
Output
Current
(mA)

Typ·
Prop_
Delay
Time
(ns)

Typ*
Power
Diss.
/Gate
(mW)

12
24
12
24
48
4
8
16
12
24

14.5
14.5
15
15
12.5
16
16
13.5
14.5
14.5

3.5
3.5
4.3
4.3
24.4
2
2
10
3.5
3.5

Quad 2-lnput
OR

Quad 2-lnput
AND

Hex Inverter
Buffers

Package
Availability
Mil

Page

Com

J
N,M

J
N,M

J
N

J
N,M

J
N

2-42
2-42
2-281
2-281
3-215
3-215
2-297
2-297
3-211
3-211

N

2-289
2-289
3-209
3-209

N,M

2-291
2-291

N,M

2-293
2-293

N,M

J

N,M

J
N

2·299
2-299
3-213
3-213

N

2-285
2-285
3-207
3-207

Package
Availability

Page

N,M

J

Buffers/Clock Drivers with Open-Collector Outputs

Description

Device Type

HighLevel
Output
Voltage
V

Quad 2-lnput
NAND Buffers

54ALS38A
74ALS38A
54LS38
74LS38
5417438
54LS26
74LS26
54/7426
54ALS1003A
74ALS1003A

5.5
5.5
5.5
5.5
5.5
15
15
15
5.5
5.5

t Please see the LS/S/TTL Logic Datebook for this datasheet.

1-45

Mil

Com

J
N,M

N,M
N

t
t
t
t
t
t

N,M

2-283
2-283

J
J
J
J
J

2-52
2-52

N,M
N,M

II

Q)

"C
·s

Buffers/Clock Drivers with Open-Collector Outputs (Continued)

~

c

o

i

~
c

o

LowLevel
Output
Current
(mA)

Prop.
Delay
Time
(nl)

Typ·
Power
01...
IGate
(mW)

Package
Availability

Description

Device Type

Quad 2-lnput
NOR Buffers

54ALS33A
74ALS33A

5.5
5.5

12
24

13.5
13.5

4.5
4.5

J

Hex Buffers/
Drivers

5407
7407
5417
7417
54ALS1035
74ALS1035

30
30
15
15
5.5
5.5

30
40
30
40
12
24

13
13
13
13
12.5
12.5

21
21
21
21
4.6
4.6

J

5406
7406
5416
7416
54ALS1005
74ALS1005

30
30
15
15
5.5
5.5

30
40
30
40
12
24

12.5
12.5
12.5
12.5
12.5
12.5

26
26
26
26
3.3
3.3

J

Max
Source
Current
(mA)

Max
Sink
Current
(mA)

Typ·
Prop.
Delay
Time
(ns)

Power
Dlss.
IGate
(mW)

~

.E
'ii

Typo

HlghLevel
Output
Voltage
(V)

=fic

:::J
U.

Hex Inverter
Buffers/
Drivers

Mil

Page

Com
N,M
N,M

J
N

J
N,M
N,M

J
N

J
N,M

2-48
2-48

t
t
t
t
2-301
2-302

t
t
t
t
2-287
2-287

Buffer Gates with TRI-STATE~ Totem-Pale Outputs
Typ.
Package
Availability

Description

Device Type

Quad Buffers

54LS125A
74LS125A
54125
74125
54LS126A
74LS126A

-1
-2.6
-2
-5.2
-1
-2.6

12
24
16
16
12
24

10
10
11
11
10
10

14.4
14.4
40
40
14.4
14.4

J

54LS365A
74LS365A
54365
74365
54LS367A
74LS367A
54367
74367

-1
-2.6
-2
-5.2
-1
-2.6
-2
-5.2

12
24
32
32
12
24
32
32

10
10
10.5
10.5
10
10
12
12

10.8
10.8
51.6
51.6
10.8
10.8
51.6
51.6

J

54LS366A
74LS366A
54LS368A
74LS368A
54368
74368
70L98
80L98

-1
-2.6
-1
-2.6
-2
-5.2
-1
-1

12
24
12
24
32
32
2
3.6

10
10
10
10
10.5
10.5
30
30

10.8
10.8
10.8
10.8
51.6
51.6
3
3

J

Hex Buffers

Hex Inverter
Buffers

t Please see the LS/S/TIL Logic Oatabook for this datasheet

1-46

Mil

Page

Com

1"
N,M

J
N

J
N,M
N,M

J
N

J
N,M

J
N
N,M

J
N,M

J
N

J
N

t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t

Buffer Gates with TRI-STATEIIl> Totem-Pole Outputs (Continued)
Typ.

Max
Sink
Current
(rnA)

Typ·
Prop.
Delay
Time
(ns)

Power
Dlss.
IGate
(mW)

Description

Device Type

Max
Source
Current
(rnA)

Octal Buffers

54ALS465A
74ALS465A
54LS465
74LS465
54ALS467A
74ALS467A
54LS467
74LS467
54ALS2541
74ALS2541
54ALS541
74ALS541

-12
-15
-2.6
-5.2
-12
-15
-2.6
-5.2
-12
-15
-12
-15

12
24
12
24
12
24
12
24
12
24
12
24

6.6
6.6
14.5
14.5
6.6
6.6
14.5
14.5
6
6
6
6

8.6
8.6
10
10
9.1
9.1
10
10
10.8
10.8
10.8
10.8

J

54ALS466A
74ALS466A
54LS466
74LS466
54ALS468A
74ALS468A
54LS468
74LS468
54ALS540
74ALS540
54ALS5620
74ALS5620

-12
-15
-2.6
-5.2
-12
-15
-2.6
-5.2
-12
-15
-12
-15

12
24
12
24
12
24
12
24
12
24
12
24

4.8
4.8
9.5
9.5
4.7
4.7
9.5
9.5
6.6
6.6
6.6
6.6

7.5
7.5
8
8
7.5
7.5
8
8
10.8
10.8
18.3
18.3

J

54ALS242B
74ALS242B
54AS242
74AS242

-12
-15
-12
-15

12
24
48
64

5.6
5.6
3.5
3.5

16.3
16.3
33.8
33.8

J

54ALS243A
74ALS243A
54AS243
74AS243
54LS243
74LS243

-12
-15
-12
-15
-15
-15

12
24
48
64
12
24

6
6
4
4
12
12

23.3
23.3
45.8
45.8
34.5
34.5

J

54AS231
74AS231
54ALS240A
74ALS240A
54AS240
74AS240
54LS240
74LS240
54S240
74S240
54S940
74S940
54ALS1240A
74ALS1240A

-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15

40
48
12
24
48
64
12
24
48
64
48
64
8
16

3.5
3.5
2.6
2.6
3.5
3.5
10
10
5
5
5
5
9
9

18.5
18.5
6.5
6.5
19.2
19.2
14.2
14.2
56.3
56.3
56.3
56.3
5.9
5.9

J

Octal Inverter
Buffers

Quad Inverter
Transceivers

Quad
Transceivers

Octal Inverter
Bus Buffers/
Drivers

t

Please see the LS/S/TTL Logic Databook for this datasheet.

,

1-47

Package
Availability
Mil

Page

Com
N,M

2-176
2-176

N,M

t
t

N,M

2-176
2-176

N,M

t

J
J

t

J
J

N,M

2-320
2-320
2-195
2-195

N,M

2-176
2-176

N,M

t

N,M

2-176
2-176

N,M

J

t

J
J
J

t
N,M

J
N,M

J
N,M
N,M

J
N
N,M

J
N

t
2-192
2-192
2-329
2-329
2-133
2-133
3-76
3-76
2-133
2-133
3-76
3-76

t

J
N,M
N

J
N,wM

J
N

t
3-73
3-73
2-129
2-129
3-76
3-76

t

J
N,WM

t
t

N,WM

t

J
J

t
N

J
N,WM

t
2-303
2-303

II

Buffer Gates with TRI-5TATE@ Totem-Pole Outputs (Continued)
Max
Sink
Current
(mA)

Typ·
Prop.
Delay
Time
(ns)

Typ·
Power
Diss.
IGate
(mW)

Description

Device Type

Max
Source
Current
(mA)

Octal Bus
Buffersl
Drivers

54ALS241A
74ALS241A
54AS241
74AS241
54LS241
74LS241
54S241
74S241
54ALS244A
74ALS244A
54AS244
74AS244
54LS244
74LS244
54S244
74S244
54S941
741)941
54ALS1241A
74ALS1241A
54ALS1244A
74ALS1244A

-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15

12
24
48
64
12
24
48
64
12
24
48
64
12
24
48
64
48
64
12
24
12
24

4.3
4.3
4
4
10
10
5
5
4.3
4.3
4
4
10
10
5
5
5
5
9
9
9
9

8.6
8.6
24.6
24.6
14.2
14.2
67.2
67.2
8.5
8.5
24.1
24.1
24.6
24.6
67.2
67.2
67.2
67.2
5.9
5.9
5.9
5.9

54ALS245A
74ALS245A
54AS245
74AS245
54LS245
74LS245
54ALS645A
74ALS645A
54AS645
74AS645
54LS645
74LS645
54ALS1243A
74ALS1243A
54ALS1245A
74ALS1245A
54ALS1645A
74ALS1645A

-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15
-12
-15

12
24
32
48
12
24
12
24
48
64
12
24
8
16
8
16
8
16

9
9
5.5
5.5
8
8
5
5
5.5
5.5
8
8
7
7
9
9
7.5
7.5

21.7
21.7
49.1
49.1
36.3
36.3
21.7
21.1
49.2
49.2
36
36
19
19
14
14
14.4
14.4

Octal
Transceivers

t

Please see the LS/S/TTL Logic Oatabook for this datasheel.

1-48

Package
Availability
Mil

Com

J
N,WM

J
N

J
N,WM

J
N

J
N,wM

J
N

J
N,WM

J
N

J
N,WM

J
N,WM

J
N,WM

J
N,WM

J
N

J
N,wM

J
N,WM

J
N

J
N,wM

J
J
J
J

Page

N,WM
N,WM
N,WM
N,WM

2-129
2-129
3-76
3-76

t
t
t
t
2-137
2-137
3-76
3-76

t
t
t
t
t
t
2-303
2-303
2-311
2-311
2-140
2-140
3-82
3-82

t
t
2-232
2-232
3-145
3-145

t
t
2-307
2-307
2-314
2-314
2-317
2-317

Buffer Gates with TRI-STATEiII> Totem-Pole Outputs (Continued)
Max
Source
Current
(mA)

Max
Sink
Current
(mA)

Typ'
Prop.
Delay
Time
(ns)

Typ'
Power
Dlss.
IGate
(mW)

54ALS620A
74ALS620A
54AS620
74AS620
54ALS640A
74ALS640A
54AS640
74AS640
54ALS1242
74ALS1242

-12
-15
-12
-15
-12
-15
-12
-15
-12
-15

12
24
48
64
12
24
48
64
12
24

8
8
5.5
5.5
5
5
4
4
5
5

14.6
14.6
32.7
32.7
15.4
15.4
32.9
32.9
10.9
10.9

J

Octal Transceivers with
True and
Inverting
Outputs

54AS230
74AS230

-12
-15

48
64

3.5
3.5

20.8
20.8

J

Octal Transceivers with
Register
Storage

54AS646
74AS646
54AS652
74AS652

-12
-15
-12
-15

32
48
32
48

5
5
5
5

93.8
93.8
93.8
93.8

J

Octal Inverter
Transceivers
with Register
Storage

54AS648
74AS648
54AS651
74AS651

-12
-15
-12
-15

32
48
32
48

6
6
6
6

81.3
81.3
81.3
81.3

J

N

3·148
3-148
3-153
3-153

Octal Inverting
Tranceiversl
MOSDrivers

54/74AS2620

-2

1

4.5

38.3

J

N

3-225

Octal Bus
Transceivers/
MOSDrivers

54/74ALS2645A
54174AS2645

TBD
-2

TBD
1

TBD
5.5

TBD
47

J
J

N,WM
N

2-323
3-228

Description

Octal Inverter
Transceivers

Device Type

Package
Availability
Mil

Page

Com

N,WM

2-226
2-226
3-139
3·139
2-229
2-229
3-142
3·142
2-307
2-307

N

3-73
3-73

N,WM

J
N

J
N,WM

J
N

J

N

J
N
N

J

3-148
3-148
3-153
3-153

Code Converters

Description

t

Device Type

Typ' Prop.
Delay Time
(ns)

Typ' Power
Diss. Total
(mW)

Package
Availability
Mil

Com

Page

6-BH Binary to 6-Bit
BCD Converters

54174185A
8899

25
31

280
350

J

N
N

t
t

6-BH BCD to 6-Bit Binary
or 4-Line to 4-Line BCD
9's/BCD 1O's Converters

54174184
8898

25
31

280
350

J

N
N

t
t

II

Please see the LS/S/TTL Logic Databook for this datasheet.

1-49

cg
"CI

·s

Comparators

CI

c

o

:gcg

Description

~

"CI

.5
fti

c

o

:g
C

:=I

U.

Device Type

Typ·
Prop.
Delay
Time
(ns)

Typ.
Power
Diss.
Total
(mW)

Mil

Com

52
275

J
J

N,M
N

t
t
t

Package
Availability

Page

4-Bit Magnitude
Comparator

54174LS85

5417485

20
21

6-Bit Magnitude
Comparators

71/8131
71/8136
71/8160

20
20
21

250
250
205

J
J
J

N
N
N

8-Bit Identity
Comparator

54/74ALS520
54/74ALS521

13.5
13.5

60
60

J
J

N,M
N,M

2·180
2·180

8-Bit Identity
Comparator with
Open-Collector
Outputs

54174ALS518
54174ALS519
54174ALS522

18.2
18
19
11

55
55
45
60

J
J
J
J

N,M
N,M
N,M
N,M

2·180
2-180
2·180
2·247

10·Bit Magnitude
Comparators

71/8130

21

240

J

N

~174ALS689

t
t

t

Counters, Asynchronous (Ripple Clock)/Negative-Edge-Triggered

Clear

(MHz)

Parallel
Load

Typ·
Power
Diss.
Total
(mW)

Mil

Com

54174LS93
5417493A
54174L93
54174LS293

32
32
6
32

None
None
None
None

High
High
High
High

39
160
20
45

J
J
J
J

N,M
N
N
N,M

t
t
t

Decade

54174LS90
5417490A
54/74LS290

32
32
32

Set-to·9
Set-to-9
None

High
High
High

40
160
45

J
J
J

N,M
N
N,M

t
t
t

Dual4-Bit Decade

54174LS390

25

None

High

75

J

N,M

t

Dual4-Bit Binary

54/74LS393

25

None

High

75

J

N,M

t

Description

4-Bit Binary

t

Device Type

Count
Freq.

Please see the LS/S/TIL Logic Databook for this datasheel

I

1-50

Package
Availability

Page

t

Counters, Synchronous/Posltlve-Edge-Triggered

Parallel
Load

Clear

Typ·
Power
Diss.
Total
(mW)

Mil

Com

Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync
Sync

Async-L
Async·L
Async-L
Async-L
Async-L
Sync-L
Sync-L
Sync-L
Sync-L
Sync-L
Sync-L
Async-L

60
200
93
475
305
60
200
93
475
93
375
305

J
J
J
J
J
J
J
J
J
J
J
J

N,M
N
N,M
N
N
N,M
N
N,M
N
N
N
N

2-89
3-42

Sync
Sync
Async
Async
Async
Async
Async
Async
Async
Async

None
None
None
None
None
None
Async-H
Async-H
Async-H
Async-H

75
230
100
60
90
325
60
85
325
40

J
J
J
J
J
J
J
J
J
J

N,M
N
N,M
N,M
N,M
N
N,M
N,M
N
N

2-106
3-49

Sync
Sync
Sync
Sync
Sync
Sync

Async-L
Async-L
Sync-L
Sync-L
Sync-L
Async-L

60
200
60
200
305
305

J
J
J
J
J
J

N,M
N
N,M
N
N
N

2-89
3-42
2-89
3-42

Sync
Sync
Async
Async
Async
Async

None
None
None
None
Async-H
Async-H

75
230
110
100
60
40

J
J
J
J
J
J

N,M
N
N,M
N,M
N,M
N

2-106
3-49
2-115

Count
Description

Device Type

Freq.
(MHz)

4-Bit Binary

4-Bit Binary
Up-Down

Decade

Decade
Up/Down

54/74ALS161 B
54174AS161
54174LS161A
54/74S161
54174161A
54174ALS163B
54174AS163
54/74LS163A
54174S163
54174163A
75/8556
93/8316

5417 4ALS169B
54174AS169
54174LS169A
54/74ALS191
54174LS191
54174191
54174ALS193
54174LS193
54174193
75/85L63
54174ALS160B
54174AS160
54/74ALS162B
54174AS162
54174162A
93/8310
54174ALS168B
54/74AS168A
54174ALS190
54/74LS190
54174ALS192
75/85L60

25
25
40
25
25
25
40
25
25
25
25
25
25
20
20
25
25
20
6
25
25
25
25
25
20
20
20
6

Package
Availability

Page

t
t
t
2-89
3-42

t
t
t
t
t
t
2-115

t
t
2-122

t
t
t

t
t

t
2-122

t

t Please see the LS/S/TTL Logic Datsbook for this datssheet.

II

1-51

Data Selectors/Multiplexers

Description

Quad2to 1
Line

Quad2to 1
Line
(Inverting)

Dual4to 1
Line

Dual4to 1
Line (Inverting)
8to 1 Line

Type
of
Output

Data
Inver.
Output

54174ALS157
54/74AS157
54/74LS157
54174S157
54174157
54/74ALS257
54/74AS257
54/74LS257B
54/74S257
93/8322
71/8123

Standard
Standard
Standard
Standard
Standard
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
Standard
TRI-STATE

54174ALS158
54/74AS158
54174LS158
54174S158
54174ALS258
54/73AS258
54/74LS258B
54/74S258

Typ. Prop. Delay
Time (ns)

Typ.

Data
to
Out

From
Enable

Power
Dlss.
Total
(mW)

Mil

Com

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

4.3
3.5
9
5
9
4.2
3.5
12
5
9
9.5

6.3
5.5
14
8
14
6
4
12
41
14
N/A

39
95
49
250
150
33
83
50
320
150
200

J
J
J
J
J
J
J
J
J
J
J

N,M
N
N,M
N
N
N,M
N
N,M
N
N
N

Standard
Standard
Standard
Standard
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE

4.2
2.5
7
4
4.2
3
12
4

N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A

6.1
4
12
7
6
4.5
12
14

11.5
78
24
195
29.2
58.5
35
280

J
J
J
J
J
J
J
J

N,M
N
N,M
N
N,M
N
N,M
N

2-86
3-38

54/74ALS153
54174LS153
54174S153
54174153
5417 4ALS253
54174LS253
54174S253
93/8309

Standard
Standard
Standard
Standard
TRI-STATE
TRI-STATE
TRI-STATE
Standard

N/A
N/A
N/A
N/A
N/A
N/A
N/A
12

16.5
14
6
10.5
8
15
6
20

14.5
22
9.5
20
4.5
25
12
20

37.5
31
225
170
35
38
275
135

J
J
J
J
J
J
J
J

N,M
N,M
N
N
N,M
N,M
N
N

2-83

54/74ALS352
54174LS352
54174ALS353

Standard
Standard
TRI-STATE

6
15
6

4.5
18
4.5

32.5
31
37.5

J
J
J

N,M
N,M
N,M

2-158

N/A
N/A

54174ALS151
54/74S151
54174151A
54174ALS251
54/74LS251
54/74S251
93/8312

Standard
Standard
Standard
TAl-STATE
TRI-STATE
TRI-STATE
Standard

9.3
4.5
8
9.4
17
4.5
9

7.8
8
16
7.6
21
8
16

11
9
22
7
21
14
17

37.5
225
145
47
35
275
135

J
J
J
J
J
J
J

N,M
N
N
N,M
N,M
N
N

11

N/A

18

200

J

N

Device Type

16 to 1 Line
54174150
Standard
t Please see the LS/SITTL Logic Databook for this datasheet

~

'-

1-52

Package
Availability

Page

2-86
3-38

t
t
t
2-150
3-84

t
t
t
t
t
t
2-150
3-84

t
t
t
t
t
2-147

t
t
t
t
2-161
2-79

t
t
2-143

t
t
t
t

Decoders/Demultiplexers

Type
of
Output

Typ.
Select
Time
(ns)

Typ.
E'nable
Time
(ns)

Typ·
Power
Diss.
Total
(mW)

Mil

Com

Totem
Totem
Totem
Totem
Open·Coliector

22
7.5
18
21
33

19
6
15
16
26

34
300
30
250
31

J
J
J
J
J

N,M
N
N,M
N
N,M

t
t
t
t
t

8.5
22
8

9
21
7

25
31
225

J
J
J

N,M
N,M
N

2·76

541748138

Totem
Totem
Totem

3 to 8 Line Decoder
with Address Register

54/74AL8131

Totem

8.5

10

25

J

N,M

2-64

3 to 8 Line Decoder
with Address Latch

54174AL8137

Totem

11

10

25

J

N,M

2·73

54174L842

Totem
Totem
Totem

17
17
20

N/A
N/A
N/A

35
140
125

J
J
J

N,M
N
N

t
t
t

54174154
93/8311

Totem
Totem
Totem

23
19.5
19.5

19
17.5
17.5

45
170
170

J
J
J

N,WM
N
N

t
t
t

93/8301

Totem

19.5

N/A

125

J

N

t

Description

Device Type

54/74L8139
54/748139
54/74L8155
54/74155

Dual 2 to 4 Line

54174L8156
3 to 8 Line

54174AL8138
54174L8138

4 to 10 Line
BCD to
Decimal

54/7442
93/8301

4t016Une

54174L8154

1 of 10 Decoder

Package
Availability

Page

t
t

Decoder/Drivers, Display

Description

Device Type

Output
Sink
Current
(mA)

State
Output
Voltage
(V)

Typ'
Power
Dlss.
Total
(mW)

Blanking

Mil

Com

30
15

320
320

Ripple
Ripple

J
J

N
N

t
t

Invalid
Invalid
Invalid
Invalid

J
J
J
J

N
N
N
N

t
t
t
t

None

J

N

t

Off·

BCD to
7·Segment
DecoderlDrivers

54/7446A

40

5417447A

40

BCD to
Decimal
Decoderl
Driver

54/7442
54/7445
54/74141
54174145

16
80
7
80

5.5
30
15

140
215
80
215

Nixie Driver

54/7441 A

7

70

105

60

Package
Availability

Page

Flip-flops, Gated

DevleeType

54174L72

Clear

Preset

Typ·
fMAX
(MHz)

Yes

Yes

20

Data
Setup
Time
(na)

Data
Hold
Time
(ns)

Typ·
Power
Diss.
/FF(mW)

0

0

3.8

t Please see the LS/SITTL Logic Oatabook for this datasMel

1·63

Package
Availability
Mil

Com

J

N

Page

t

II

Flip-Flops, Single and Dual J-K Edge Triggered
Typ'
Device Type

Clear

Preset

'MAX

(MHz)

54174LS73A
54174LS107A
54174ALS109A
54174AS109
54174LS109A

54174109
54174LS112A

541748112
54174S113
90/8024

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

No

Data
Hold
Time
(ns)

Typ'
Power
Diss.
IFF(mW)

Mil

Com

25
20
15
3
25
10
20
6
6
15

5
0
0
1
0
6
0
0
0
10

10
10
6
28.8
10
45
10
75
75
45

J
J
J
J
J
J
J
J
J
J

N,M
N,M
N,M
N
N,M
N
N,M
N
N
N

45
45
50
125
33
33
45
125
125
40

No
No

Yes

Data
Setup
Time
(ns)

Package
Availability

Page

t
t
2-61
3·33

t
t
t
t
t
t

Fllp·Flops, Dual 0 Edge Triggered with Preset and Clear
Typ'
Device Type

'MAX

(MHz)

54174ALS74A
54174AS74
54174LS74A

54174874
5417474
54174L74

30
125
33
110
25
6

Data
Setup
Time
(ns)

Data
Hold
Time
(ns)

Typ.
Power
Diss.
IFF(mW)

Mil

Com

15
2
20
3
20
50

0
1
0
2
5
15

6
26.3
10
75
43
4

J
J
J
J
J
J

N,M
N
N,M
N
N,M
N

Package
Availability

Page

2·56
3·28

t
t
t
t

Flip-Flop, Octal 0 Edge Triggered with TRI·STATE Outputs
Typ.
Device Type

'MAX

(MHz)

54174ALS374
54174AS374
54174LS374

54174S374
54174ALS534
54174AS534
54/74ALS564A
54174ALS574A
54174AS574
54174AS575
54174ALS576A
54174AS576
54174AS577
54174ALS874B
54174AS874
54174ALS876A
54174AS876
54174AS878
54174AS879

50
200
50
100
50
200
50
50
200
160
50
160
160
50
160
50
160
160
160

Data
Setup
Time
(ns)

Data
Hold
Time
(ns)

Typ'
Power
DisL
IFF(mW)

Mil

Com

10
3
20
5
10
3
15
15
3
3
15
3
3
15
2.5
15
2.5
3
3

4
3
0
2
0
2
4
4
3
3
4
3
3
4
1
4
1
3
3

10.8
50.3
15.9
60.9
10.4
50.3
8.5
8.5
50.4
53
8.5
52.5
50.4
10.8
62.5
10.8
58
62.5
59

J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J

N,WM
N
N,WM
N
N,WM
N
N,WM
N,WM
N
N
N,WM
N
N
N,WM
N
N,WM
N
N
N

t Please see the LS/S/TTL logic Oatabook for this datasheel.

1·54

Package
Availability

Page

2·168
3·110
/

t
t
2·188
3·117
2·202
2·210
3·124
3-127
2·214
3·130
3-133
2-267
3·176
2·271
3-180
3-183
3·186

Flip-FlOps, Single and Dual, Pulse Triggered
Typ.
Device Type

5417473
54174L73
54/7476
54/74107

Clear

Preset

fMAX
(MHz)

No
No
Yes
No

Yes
Yes
Yes
Yes

35
11
20
20

Typ.

Data
Setup
Time
(ns)

Data
Hold
Time
(na)

Power
Dlss.
IFF(mW)

0
0
0
0

0
0
0
0

50.0
3.8
50.0
50.0

Package
Availability
Mil

Com

J
J
J
J

N
N
N
N

Page

t
t
t
t

Gatea, AND with Totem-Pole Outputa

Description

Device Type

Typ.
Prop.
Delay
Time (na)

Mil

Com

Dual4-lnput

54174ALS21A
54/74AS21
54/74LS21

9
3.3
7.8

2.2
12.5
4.5

J
J
J

N,M
N
N,M

2-36
3-18

Triple 3-lnput

54174ALS11A
54174AS11
54/74LS11
54174811

9
3.3
7.8
4.8

2.1
12.9
4.3
31

J
J
J
J

N,M
N
N,M
N

2-23
3-14

54174ALS08
54174AS08
54174LS08
54174508
54/7408

6.5
3.3
7.8
4.8
15

2.2
12.9
4.3
31
19

J
J
J
J
J

N,M
N
N,M
N
N

2-17
3-10

Typ·
Power
Din.
IGate(mW)

Quad 2-lnput

Typ·
Power
Din.
IGate(mW)

Package
Availability

Page

t
t
t
t
t
t

Gatea, AND with Open-Collector Outputs

Description

Device Type

Typ.
Prop.
Delay
Time (na)

Mil

Com

Triple 3-lnput

54174AL815A

17

1.5

J

N,M

2-32

Quad 2-lnput

54174ALS09
54174LS09
54/74509
5417409

17

2.2
4.3
31
19.4

J
J
J
J

N,M
N,M
N
N

2-19

19
6.5
18.5

Package
Availability

Page

t
t
t

.

Gatea, AND-OR-INVERT with Totem-Pole Outputa

Description

Device Type

Typ.

Typ·
Prop.
Delay
Time (na)

Power
01...
IGate(mW)

Package
Availability
Mil

Com

Page

t

Dual2-Wide
2-lnput

54/74L851
54/74S51

7.5
3.5

2.75
28

J
J

N,M
N

t

4-Wide 4-2-3-2
Input

54174S64

3.5

29

J

N

t

t Please see the LS/S/TTL logic Datebook for this datasheet.

-

1-55

II

Gates, NAND and Inverters with Open-Collector Outputs

Power
Diss.
IGate(mW)

Description

Device Type

Dual4-lnput
NAND Gates

54174ALS22B

19

Triple 3-lnput
NAND Gates

54174ALS12A
54174LS12

Quad 2-lnput
NAND Gates

Hex Inverters

Typo

Typ'
Prop.
Delay
Time (ns)

Package
Availability

Page

Mil

Com

1.3

J

N,M

2-38

18
21

1.3
2

J
J

N,M
N,M

2-25

54174ALS01
5417401
54/74ALS03B
54174LS03
54/74S03
5417403

17
32
17
22
7
10

1.3
10
1.3
2
17.5
22

J
J
J
J
J
J

N,M
N
N,M
N,M
N
N

2-7

54174ALS05A
54174LS05
54174S05
5417405

18
21
7
22

1.5
2
17.5
10

J
J
J
J

N,M
N,M
N,M
N

2-15

t
t
2-11

t
t
t
t
t
t

Gates, NAND and Inverters with Totem-Pole Outputs
,

Description

Device Type

Mil

Com

Dual 4-lnput
NAND Gates

5417 4ALS20A
54174AS20
54174LS20
54174S2O
5417420
54174L20

6.5
2
8
4.5
10
33

1.3
8.7
2
19
10
1

J
J
J
J
J
J

N,M
N
N,M
N
N
N

2-34
3-16

54/74ALS10A
54174AS10
54174LS10
54174S10
54/7410
54174L10

7
2
8
4.5
10
33

1.3
14
2
19
10
1

J
J
J
J
J
J

N,M
N
N,M
N
N
N

2-21
3-12

5417 4ALSOOA
54174ASOO
54/74LSOO
54174S00
5417400
54174LOO
9002C

3.5
2
8
4.5
10
33
10

1.25
8
2
19
10
1
11

J
J
J
J
J
J
J

N,M
N
N,M
N,M
N
N
N

2-5
3-4

Triple 3-lnput
NAND Gates

Quad 2-lnput
NAND Gates

t

Typo
Power
Diss_
IGate(mW)

Typ'
Prop.
Delay
Time (ns)

Please see the LS/S/TTL logic Databook for this datasheet.

1-56

Package
Availability

Page

t
t

t
t

t

t
t
t
t
t
t
t
t

Gates, NAND and Inverters with Totem-Pole Outputs (Continued)

Description

Hex Inverters

Device Type

Typ.
Prop.
Delay
Tlme(ns)

Typ.
Power
Dlss.
IGate(mW)

Mil

Com

3.5
2
8
4.5
10
33
8

1.5
7.1
2
19
10
1
10

J
J
J
J
J
J
J

N,M
N
N,M
N,M
N,M
N
N,M

2-13
3·8

6.5
2
10
4.5
10

1.9
9.8
2.4
19
10

J
J
J
J
J

N,M
N
N,M
N
N

2·44
3-22

2
19

J
J

N,M
N,M

2-69

12

J

N

3-26

54174AlS04B
54174AS04
54174lS04

54174S04
5417404
54/74104
54/74AlS14
8-lnput NAND
Gates

54/74AlS30A
54174AS30

54/74lS30
54/74S30
5417420
13·lnput NAND
Gate

54/74AlS133

54174S133

7
6

Hex Non-Inverter

54/74AS34

4.5

Package
Availability

Page

t
t
t
t
2-29

t
t

t
t

Gates, Exclusive NOR, OR with Open-Collector Outputs

Description

Device Type

Quad 2-lnput
Exclusive NOR Gates

54/74AlS811
54174AS811

Quad 2-lnput
Exclusive OR Gates

54/74AlS136

Typ.
Prop.
Delay
Tlme(ns)

Typ.
Power
Diss.
IGate(mW)

Package
AvallabllHy

9.1

54/74AS136

Page

Mil

Com

J
J

N,M
N

2-259
3-168

J
J

N,M
N

2-71
3-36

Gates, Exclusive NOR with Totem-Pole Outputs

Description

Device Type

Typ·
Prop.
Delay
Time (ns)

Typ·
Power
Diss.
IGate(mW)

Mil

Com

Quad 2-lnput
Exclusive NOR Gates

54174AlS810
54174AS810

N/A
N/A

N/A
N/A

J
J

N,M
N

Package
Availability

Page

2-256
3-165

Gates, NOR with Totem-Pole Outputs

Description

Device Type

Triple 3-lnput
NOR Gates

54174AlS27
54174AS27
54174lS27

Typ·
Prop.
Delay
Time (ns)

Typ·
Power
Diss.
IGate(mW)

Mil

Com

5.5
2
10
8.5

2.5
12.2
4.5
22

J
J
J
oJ

N,M
N
N,M
N

2-40
3-20

5
2
10
5
10
33

1.9
10.1
2.75
29
14
1.5

J
J
J
J
J
J

N,M
N
N,M
N
N
N

2-9
3-6

5417427
Quad 2-lnput
NOR Gates

54174AlS02
54174AS02
54174lS02

54174S02
54/7402
54/74102
t Please see the LS/S/TTL Logic Databook for this datasheel

1-57

Package
Availability

Page

t
t
t
t
t

t

II

Gates, OR with Totem-Pole Outputs

Description

Device Type

auad 2·lnput
OR Gates

54174ALS32
54174AS32
54174LS32
54/74S32

Typ'
Prop.
.~_ Delay
Tlme(ns)

5417432
auad 2-lnput
Exclusive
OR Gates

54174ALS86
54/74AS86
54174LS86
54/74586

5417486

Typ'
Power
0188.
IGate(mW)

Package
Availability

Page

Mil

Com

5.5
3.5
10
5
12

2.8
14.9
5
35
24

J
J
J
J
J

N,M
N
N,M
N
N

2-46
3-24

7

3.75
7.5
62.5
41

N,M
N
N,M
N
N

2-59
3-31

10
9
14

J
J
J
J
J

t

t
t
t
t
t

Latches

Description

Device Type

No.
of
Bits

Clear

Outputs

Typ.'
Prop.
Delay
Time
(ns)

Typ'
Power
Dlss.
Total
(mW)

Mil

Com

Low
Low
Low

a
a
a

17
21
21

110
150
280

J
J
J

N,WM
N
N

a,a
a,a

11
15

32
160

J
J

N,M
N

Package
Availability

Page

DG (Clocked)
Latches

54174LS75

5417475

4
4

None
None

S,R Latches

54174LS279

4

None

a

12

19

J

N,M

t
t
t
t
t
t

Dual4-Bit
Latches

54174ALS880A
54174A5880

4
4

None
None

a
a

9
6

88.3
391.5

J
J

N,M
N

2-275
3-189

Octal Latch

54174ALS273

8

Low

a

12

50

J

N,M

2-154

TRI-STATE
Octal
Latches

54/74ALS373
54174AS373
54/74LS373

None
None
None
None
None
None

a
a
a
a
a
a

10
6
17
12
9
4.5

70
300
120
525
68.3
293

J
J
J
J
J
J

N,WM
N
N,wM
N,WM
N,WM
N

2-164
3-107

54174ALS573B
54174AS573

8
8
8
8
8
8

54174ALS533
54174AS533
54174ALS563A
54/74ALS580A
54/74AS580

8
8
8
8
8

None
None
None
None
,None

a
a
a
a
a

10
5
13
9
4.5

75.8
328
68.3
68.3
330

J
J
J
J
J

N,WM
N
N,WM
N,WM
N

2-184
3-114
2-198
2-218
3-136

Dual4-Bit
54174AL5873B
4
Low
TRI-STATE
54174AS873
4
Low
Latches
t Please see the LS/S/TTL logiC Datebook for this datasheet.

a
a

10
4.5

68.3
330

J
J

N,WM
N

2-236
3-172

Addressable
Latches

54174LS259

54174259
93/8334

54174S373

TRI-STATE
Inverting
Octal
Latches

8 ",
8
8

1-58

t
t
2-206
3-120

UneDrlvers

Description

Device Type

LowLevel
Output
Current
(rnA)

HlghLevel
Output
Current
(rnA)

Typ·
Prop.
Delay
Time
(n8)

Typ·
Power
Diss.
IGate
(mW)

Package
Availability
Mil

Com

Dual4-lnput NAND

54174S140

60

-40

4

43.8

J

N

Hex2·lnput
NAND

54ALS804A
74ALS804A
54AS804B
74AS804B
54AS1804
74AS1804

12
24
40
48
40
48

-1
-2.6
-40
-48
-40
-48

2.7
2.7
2
2
2
2

3.3
3.3
7.7
7.7
7.7
7.7

J

54ALS805A
74ALS805A
54AS805B
74AS805B
54AS1805
74AS1805

12
24
40
48
40
48

-12
-15
-40

4.1
4.1
9.6
9.6
9.6
9.6

J

-40
-48

3
3
1.6
1.6
1.6
1.6

54ALS808A
74ALS808A
54AS808B
74AS808B
54AS1808
74AS1808

12
24
40
48
40
48

-12
-15
-40
-48
-40
-48

4.3
4.3
3
3
3
3

4.6
4.6
10.6
10.6
10.6
10.6

J

54ALS832A
74ALS832A
54AS832B
74AS832B
54AS1832
74AS1832

12
24
40
48
40
48

-12
-15
-40
-48
-40
-48

4
4
2.5
2.5
2.5
2.5

5.6
5.6
12.9
12.9
12.9
12.9

J

Hex2-lnput
NOR

Hex2-lnput
AND

Hex2-lnput
OR

-48

Page

t
2-250
2-250
3-159
3-159
3-217
3-217

N,M

J
N

J
N

2-252
2-252
3-161
3-161
3-219
3-219

N,M

J
N

J
N

2-254
2-254
3-163
3-163
3-221
3-221

N,M

J
N

J
N

2-261
2-261
3-170
3-170
3·223
3-223

N,M

J
N

J
N

Multipliers
Description
4-Bit by 4-Bit Parallel
Binary Multipliers

t

Package Availability

Device
Type

Mil

Com

78/8875A
78/8875B

J
J

N
N

Page

t
t

Please see the LS/S/TIL Logic Datebook for this datesheet.

II

1-59

One Shots, Retrlggerable

No.of
Inputs

Dlr.
Clear

Output
Pulse
Renge(n.)

Typ'
Total
Power
01...
(mW)

Package
Availability

Description

Device Type

Poe

Neg

Mil

Com

Single

54174LS122
96/8601

2
2

2
2

Ves
Ves

45 ns-inf.
50ns-inf.

30
90

J
J

N,M
N

Dual

54174LS123

1
1
1

1
1
1

Ves
Ves
Ves

90 ns-inf.
45ns-inf.
72 ns-inf.

60
230
195

J
J
J

N,M
N
N

Dlr.
Clear

Output
Pulse
Range(n.)

Typ'
Totsl
Power
Di...
(mW)

54174123
96/8602

Page

t
t
t
t
t

One Shots with Schmitt-Trigger Inputs

Description

No.of
Inputs

Device Type

Poe

Nag

Package
Availability
Mil

Com
N

Single

54174121

1

2

Ves

40ns-28s

90

J

Dual

54LS221
74LS221

1
1

1
1

Ves

20 ns-49s
20ns-49s

65
23

J

Page

t
t
t

N,M

Parity Generators/Checkers

Description

Device Type

Typo

Typ'
Prop.
Delay
Tlme(n.)

Power
01•••
Total(mW)

Package
Availability

Page

Mil

Com

8-Bit Odd/Even Parity
Generators/Checkers

54174180

35

170

J

N

9-Bit Odd/Even Parity
Generators/Checkers

54174S280
54174AS280

13
7.3

335
135

J
J

N,M
N

3-93

9-Bit Parity
Generator/Checker
with Bus Driver
Parity 110 Port

54174AS286

9.3

160

J

N

3-102

t
t

Priority Encoders

DescrIption

Cascadable Octal
Priority Encoders

Device Type

Typ'
Prop.
Delay
Tlme(n.)

Typ'
Power
01...
Total (mW)

12
12

190
190

54174148
93/8318

Package
Availability
Mil

Com

J
J

N
N

Page

t
t

Register File.

DescrIption

Devlc8Type

Typ'
Addre..
Time
(ns)

4 Words of 4 Bits
with TRI-STATE Outputs

54174LS670

24

Typ'
Read
Enable
Time
(ns)

Data
Input
Rate
(MHz)

TypO
Power
01...
Total
(mW)

Mil

Com

19

20

135

J

N,M

t Please see the LS/smL logic Databook for this datasheet.

1-60

Package
Availability

Page

t

Registers, Other

Description

Device Type

Typ·
Clock

Freq.

Asyn.
Clear

(MHz)

Typ'
Power
Dlss.
Total(mW)

Package
Availability

Page

Mil

Com

85
250

J
J

N.M
N

t
t

Low
Low
Low
Low
Low

47.5
395
55
300
150

J
J
J
J
J

N,M
N
N,M
N
N

2·111
3·57

15

None

30

J

N

54/74ALS174
54174AS174
54/74LS174
54174S174
54/74174

60
160
40
90
40

Low
Low
Low
Low
Low

50
395
80
450
225

J
J
J
J
J

N,M
N
N,M
N
N

8-Bit Universal
Shift/Storage
Registers

54174S299

60

Low

700

J

N

Octal D-Type
Registers

54174ALS374
54174AS374
54174LS374
541745374
54174ALS534
54174AS534
54174ALS574A
54174AS574
54174AS575
54174ALS576A
54174AS576
54174AS577
54/74ALS874B
54174AS874
54174ALS876A
54174AS876
54174AS878
54174AS879

50
200
50
100
50
200
40
160
160
50
160
160
50
160
50
160
160
160

None
None
None
None
None
None
None
None
None
None
None
None
Low
Low
None
None
Low
Low

86
402
128
487
83
328
68
403
383
68
420
420
87
500
87
500
500
500

J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J

N,WM
N
N,WM
N,WM
N,WM
N
N.WM
N
N
N,WM
N
N
N,WM
N
N,WM
N
N
N

8-Bit Dual Rank
Shift Register

54174LS952
54174LS962

36
36

None
None

305
305

J
J

N.M
N,M

t
t

Successive
Approximation
Registers

2502C
2503C
2504C

21
21
21

None
None
None

325
300
450

J
J
J

N
N
N

t
t
t

Octal Bus
Transceivers
And8-Bit
Storage Register

54174ALS646
54174ALS648
5417 4ALS652

40
40
40

None
None
None

255
260
255

J
J
J

N,WM
N,WM
N,WM

Quad Bus
Buffer Registers

54174LS173A
54174173

40
30

High
High

QuadD·Type
Registers

54174ALS175
54/74AS175A
54174LS175
54174S175
54174175

60
160
40
90
40

Quad Multi·
plexers with Storage

54174L98

HexD-Type
Registers

.,

t

Please see the LS/S/TTL Logic Datebook for this datesheet.

1-61

t
t
t
t
2-111
3-54

t
t
t
t

2-168
3-110

t
t
2-188
3-117
2-210
3-124
3-127
2-214
3-130
3-133
2-267
3-176
2-271
3-180
3-183
3-186

2-235
2-239
2-243

II

Registers, Shift

Parallel-In
Parallel-Out
(Bidirectional)
Parallel-In
ParallelOut

Package
Availability

S-R

SoL

Load

Hold

Mil

Com

25
90
36

D
D
D

Low
Low
Low

x
x
x

x
x
x

x
x
x

x
x
x

75
450
195

J
J
J

N.M
N
N

4
4
4
4
4

36
14
39
90
39

D
D

x
x
x
x
x

x
x

x
x
x
x
x

x
x

J-R
J-R
J-R

None
None
Low
Low
Low

x

195
24
70
375
356

J
J
J
J
J

N
N
N.M
N
N

54/74ALS166

8
8
8
8
8
8

14
30
60
35
35
60

D
D
D
D
D
D

None
None
None
Low
Low
Low

x
x
x
x
x
x

x
x
x
x
x
x

x
x
x
x
x
x

30
125
80
110
360
80

J
J
J
J
J
J

N
N.WM
N.WM
N.WM
N
N.WM

54174LS184

8

36

Low

x

80

J

N.M

t

54/74184

8

36

Gated
D
Gated
D

Low

x

175

J

N

t

54174LS194A

54/74S194
54/74194
54/7495
54174L95
54174LS195A

76/86L90
54/74LS165
54174ALS165

54/74LS168
54174166
Serial·ln
ParallelOut

Typ.

4
4
4

DeviceType

541748195
93/8300
Parallel-In
Serial·Out

Typ.

Power
Dlaa.
Total
(mW)

Description

No.
of
Bits

Shift

Freq.
(MHz)

Ser.
Data
Input

Modea

Asyn.
Clear

Page

t
t

t
t
t
t
t
t
t
t
2·97

t
t
2·102

Schmltt-Trlggera with Totem-Pole Outputs
Typ.
Description

t

Device Type

Dual4·lnput
NAND Schmitt
Triggers

54174ALS13

Quad 2-lnput
NAND Schmitt
Triggers

54174LS132

Hex Schmitt
Trigger
Inverters

54174LS14

54174132

Typ.·
Hyatereala
(V)

Prop.
Delay
Time (na)

15
15

54174ALS132

54/7414

15
15

54/74ALS14

Pi..... see the LS/S/TTL Logic Oatabook for this datasheel

1-62

Package
Availability

Page

Mil

Com

0.8

J

N.M

2-27

0.8
0.8
0.8

J
J
J

N.M
N
N.M

t
t

0.8
0.8
0.8

J
J
J

N.M
N
N.M

2-67

t
t
2-29

Glossary of Terms

DC Operating Conditions and Characteristics
GENERAL DEFINITIONS

OUTPUT CURRENT PARAMETERS

I: Current is the flow of electric charge from one potential to
another through a conductor. The unit of measure is the
Ampere, or Amp, abbreviated A. One Amp is equal to the
current flowing through one ohm of resistance when one
volt is applied across that resistance. Common units found
in the semiconductor industry are the milliampere, abbreviated mA, equal to 0.001A and the microampere, abbreviated /LA, equal to 0.000001 A. Negative current is defined as
current flowing out of a device terminal and positive current
is defined as current flowing into a device terminal.

ICEX Output Leakage Current: The current flowing into an
open collector output when input conditions have been applied that, according to the product specification, will cause
the output to be in the logic high state. This test checks the
reverse breakdown of the output transistor.

V: Voltage, or the electromotive force which causes current
to flow through a conductor. One Ampere of current flowing
through one ohm of resistance develops a potential difference of one volt across that resistance. The unit of measure
is the Volt, abbreviated V, and a common unit is the millivolt,
abbreviated mV, equal to O.OO1V.

ed to drive devices other than logic circuits, such as displays. Any
leakage current applied to a display may cuase the display to be
activated.

Io(off) Off-8tate Output Current: The current flowing into
an output with input conditions applied that, according to the
product specification, will cause the output switching element to be in the off state.
NOTE: This parameter is usually spec~ied for open ccllector outputs intend-

IOH High Level Output Current: The current flowing out of
an output with input conditions applied that, according to the
product specification, will establish a logiC high level at the
output. This test guarantees the current sourcing (drive) capability of the output and the fan-out specified for the family.

INPUT CURRENT PARAMETERS
II Maximum High Level Input Current: Current flowing into
an input when that input has the maximum voltage specified
for the family applied to it. This test is used to guarantee the
minimum reverse breakdown voltage of the input structure.

IOl Low Level Output Current: The current flowing into an
output with input conditions applied that, according to the
product specification, will establish a logic low level at the
output. This test guarantees the current sinking capability of
the output and the fan-out specified for the family.

IIH High Level Input Current: The current flowing into an
input when that input has a high level voltage equal to the
minimum high level output voltage specified for the family.
This test is used to check the emitter-to-emitter leakage and
the inverse transistor action of a multi-emitter transistor input, the input leakage of a diode, PNP transistor, or CoB
short type of input, and to guarantee the fan-in specified for
the family.
11K Input Clamp Current: The current flowing out of an input when that input is pulled below ground. This test is used
to guarantee the integrity of the input clamp diode. The input
clamp diode is used to limit the voltage swings on the input
by clamping the negative excursions to a level equal to one
diode drop below ground. This serves to reduce ringing on
an incoming signal. Pulling the input below ground for an
extended length of time can cause parasitic transistor action
to occur between adjacent tanks on the die which can
cause erroneous data to occur on the outputs of the device.
To prevent this, voltages on the inputs during operation
(other than high speed ringing) should be limited to no mora
than 0.5V below ground at all times.
III Low Level Input Current: The current flowing out of an
input when a low level voltage equal to the maximum low
level output voltage specified for the family is applied to the
input. This test is used to check the input pullup resistor on
an MET or a diode input and to guarantee the specified fanin of the family.

los Output Short-Circuit Current: The current out of an
output when that output is shorted to ground, or another
specified potential, with input conditions applied that, according to the product specification, will establish a logic
high level at the output.
IOZ High-Impedance State Output Current: These tests
guarantee that the device will not excessively load a bus
line when the device output is put into the TRI-STATE~
mode.
IOZH (or ISINK): The current flowing into an output with input
conditions applied to the output control pin such that the
output is in the high impedance state and input conditions
applied to the other inputs that, according to the product
specification, will establish a logic low level at the output.
IOZl(or ISOURCE): The current flowing out of an output with
input conditions applied to the output control pin such that
the output is in the high impedance state and input condi. tions applied to the other inputs that, according to the product specification, will establish a logic high level at the output.
SUPPLY CURRENT PARAMETERS
ICCH Supply Current (outputs In the high state): The current flOwing into the Vee terminal of a device with input
conditions applied that, according to the product specification, will establish a logic high level at the output(s).

IT+ Current at Positive-Going Threshold Point: The current flowing out of a transition-operated (Schmitt trigger) input when a voltage equal to the positive going threshold
voltage is applied to the input.

ICCl Supply Current (outputs In the low state): The current flowing into the Vee terminal of a device with input
conditions applied that, according to the product specification, will establish a logic low level at the output(s).

IT- Current at Negatlve-Golng Threshold Point: The
current flowing out of a transition-operated (Schmitt trigger)
input when a voltage equal to the negative going threshold
voltage is applied to the input.

1-63

•

~ r-------------------------------------------------------------------------------~

E

{!!.

'0

i

.2
CJ

DC Operating Conditions and Characteristics (Continued)
Iccz Supply Current (outputs In the hlgh-lmpeclance
state): The current flowing into the Vee terminal of a device
with input conditions applied that, according to tha product
specification, will establish a high impedance state at the
output.
INPUT VOLTAGE PARAMETERS
BVIN Input Breakdown Voltage: The maximum voltage
that the device is guaranteed to be able to withstand without
exceeding the maximum 'input current specification.

VT+ Posltlve-Golng Threshold Voltage: The voltage level at a transition-operated (Schmitt trigger) input that causas
operation of tha logic element according to specification as
the input voltage risas from a level below the negative-going
. threshold voltage, VT- •
VT- Negatlve-Golng Threshold Voltage: The voltage level at a transition-operated (Schmitt trigger) input that causas
operation of the logic element according to specification as
the input voltage falls from a level above the positive-going
threshold voltage, VT+.

VF Input Forward Voltage: The voltage applied to the input
of a device that causes the input structure to become forward biased; usually equal to the maximum output low voltage specified for the family.

OUTPUT VOLTAGE PARAMETERS
VOH High Level O~ut Voltage: The voltage at an output
terminal with input conditions applied that, according to the
product SJlecification, will establish a high level at the output.

VIH High Level Input Voltage: The minimum positive volt-,·
age level that can be applied to an input terminal of a device
and be recognized as a logic high level.
VIK Input Clamp Voltage: The input clamp voltage specification checks the quality of the input diode whose purpose
is to damp out ringing. This is not intended t9 be an operating condition and if this voltage is allowed to persist for any
length of time, parasitic transistor action will olfUr between
adjacent geometry tanks and circuit performance will be degraded, in some cases to the point of failure.

VOL Low Level Output Voltage: The voltage at an output
terminal with input conditions applied that, according to the
product specification, will establish a low level at the output.
Vo(off) Off-state OutPUt Voltage: The voltage at an output terminal with input conditions applied that, according to
the product specification, will cause the output switching element to be in the off state.
NOTE: ThIs characteristic Is usually specified only for outputs without internal

VIL Low Level Input Voltage: The maximum positive voltage level that can be applied to an input terminal of a device
and be recognized as a logic low level.

pul~up

elements Intended for driving devices other than logic

circuits.

Vo(on) On-8tate Output Voltage: The voltage at an output
terminal with· input conditions applied that, according to the
product specification, will cause the output switching element to be in the on state.
'

VR Input Reverse Voltage: The voltage applied to an input
of a device that causes the input structure to become reverse biased; usually equal to the minimum high level output
voltage specified for the family.

NOTE: ThIs characterlatlc is usually spaclfied only for outputs without Internal pull-up elements intended for driving devices other than logic

ctrcuits.

1-64

AC Operating Conditions and Characteristics
tPHZ Output Disable Time from a High logic Level: The
propagation delay time between the specified voltage reference points on the input and output waveforms with a TRISTATE output changing from the defined high state to the
high impedance (off) state.
tpLZ Output Disable Time from a Low Logic Level: The
propagation delay time between the specified voltage reference points on the input and output waveforms with a TRISTATE output changing from the defined low state to the
high impedance (off) state.

INPUT PARAMETERS
fMAX Maximum Clock Frequency: The highest rate at
which the clock input of a bistable circuit can be driven
through its required sequence while maintaining stable transitions of logic levels at the output with input conditions established that should cause changes of output logic level in
accordance with the specification. Unless otherwise specified, this test is performed with no restrictions on input rise
and fall times or duty cycle.
NOTE: A minimum value Is specified that is the highest frequency at which
all devices are guarantaed to function correctly.

twOUT Output Pulse Width: The time interval between
specified voltage reference points on the leading and trailing edges of an output waveform.

tH Hold Time: The interval during which a signal must be
maintained at a given data input after an active transition at
another given input.

NOTE: This is usually only specified for monostable elements.

NOTE: A minimum value is specified that is the smallest time interval above
which all devicas are guarantaed to function ccrrectiy.

tpLH Propagation Time, Low to High: The time between
the specified voltage reference points on the input and output waveforms with the output changing from a low logic
level to a high logiC level.

tw Pulse Width: The time interval between specified voltage reference points on the leading and trailing edges of a
pulse waveform.

tpHL Propagation Delay, High to Low: The time between
the specified voltage reference points on the input and output waveforms with the output changing from a high logic
level to a low logic level.

NOTE: A minimum value is specified that is the smallest time Interval at
which correct operation of the logic element is guerentaed.

tREe Recovery Time: The time interval needed to switch a
memory-type device from a write mode to a read mode and
to obtain valid data signals at the output.

trLH, tr Transition Time, or Rise Time: The time interval
between a specified low-level voltage and a specified highlevel voltage on a waveform that is changing from a defined
low level to a defined high level. Common defined levels are
from 10% of the signal amplitude to 90% of the signal amplitude, or from 0.6V to 2.6V.

NOTE: A minimum value is specified that is the smallest time interval at
which correct operation of the device is guaranteed.

tREL Release Time: The time interval between one control
input going inactive and another input going active after
which the inactive input no longer has any influence on the
device operation.

trHLo It Transition Time, or Fall Time: The time interval
between a specified high-level voltage and a specified lowlevel voltage on a waveform that is changing from a defined
high level to a defined low level. Common defined levels are
from 90% of the signal amplitude to 10% of the signal amplitude, or from 2.6V to 0.6V.

NOTE: A minimum value is specirNOd that is the smallest tima inteJ'Vai at
which correct operation of the logic element is guarantaed.

Is

Set-Up Time: The time interval during which a stable
signal must be maintained at a specified input terminal before an active transition at another specified input terminal.
NOTE: A minimum value is specified that is the smallest time interval at
which correct operation of the logic element is guaranteed.

EXPLANATION OF DEVICE FUNCTIONS
Circuit Complexity
SSI: Small Scale Integration; the lowest level of complexity
in integrated circuits.
MSI: Medium Scale Integration; small subsystems integrated into a single microcircuit.

tR Rise Time: The time interval between a specified lowlevel voltage and a specified high-level voltage on a waveform that is changing from a defined low level to a defined
high level. Common defined levels are from 10% of the signal amplitude to 90% of the Signal amplitude.

LSI: Large Scale Integratiori;'large subsystems or small systems integrated into a single microcircuit.

tF Fall Time: The time interval between a specified high-level voltage and a specified low-level voltage on a waveform
that is changing from a defined high level to a defined low
level. Common defined levels are from 90% of the signal
amplitude to 10% of the signal amplitude.
OUTPUT PARAMETERS

FUNCTIONAL DESCRIPTIONS
Buffer: A logic gate with high output drive capability, or fanout. Buffers are used where a single circuit must drive a
large number of loads.

tpZH Output Enable Time to a High Logic Level: The
propagation delay time between the specified voltage reference points on the input and output waveforms with a TRISTATE output changing from a high impedance (off) state to
the defined high state.

Comparator: A logic circuit that will compare two separate
input signals and produce an output based on that comparison. A Simple comparator is the Exclusive-NOR gate, which
produces a high level output only when its two inputs are
identical.

tpZL Output Enable Time to a Low Logic Level: The propagation delay time between the specified voltage reference
points on the input and output waveforms with a TRI-STATE
output changing from a high impedance (off) state to the
defined low state.

Counter: A logic circuit that counts the number of input
pulses it receives. Counters can be used for frequency division, counting, and sequencing digital operations. Common
counter configurations are Binary, where the device counts
from 0 to 15 and Decade, where the device counts from 0
to 9.

1-65

•

AC Operating Conditions and Characteristics (Continued)
Data Selector/Multiplexer: A logic circuit that will select
one of several input signals and feed that signal onto a common bus line. It can be thought of as a multipole, multiposition switch with each switch pole representing one output
and each switch position representing one input.

TRI·STATE: A registered trademark for a circuit configuration in which the device can bEi switched 'off' during which
time the output presents a very high impedance to the bus it
is connected to. This allows multiple outputs to be connected to a bus line while only one output drives the line, the
other outputs being switched into their high impedance
states.

Decoder/Demultiplexer: A logic circuit that is the complement of the Data SelectorIMultiplexer; that is, this circuit
takes an input signal and feeds it to anyone of several
output lines depending on the information placed on its
steering, or control, inputs.

EXPLANATION OF FUNCTION TABLES
The following symbols are used in the function tables found
in NSC data sheets:
= high logic level (steady state)
H

Driver: Same as Buffer, above.
Fllp·Flop: A logic circuit that is used to store information. A
flip-flop is called "bistable" since it has two stable states.

L

t

Gate: The basic building block of all logic circuits; an element whose output is a Boolean function of its inputs. The
basic functions are the AND, OR, and NOT. By combining
these functions, NAND, NOR, and Exclusive-OR and Exclusive-NOR gates are built.

= low logic level (steady state)
= transition from low to high logic level

,1.

= transition from high to low logic level

x

= irrelevant (any level, including tranSitions)

= off (high impedance) state of a TRI-STATE output
Z
a ... h = the level of steady state inputs at inputs A
through H respectively

Latch: A bistable element that latches, or holds, data which
is present at its input at the time the Enable input goes to its
inactive state. When the Enable input is active, the data,
present at the input, is passed directly to the output, similar
to the operation of a gate.

Qo

= the level of Q before the indicated steady state

00

= complement of Qo or level of Q before the indi-

input conditions were established
cated steady state input conditons were established
Qn
= level of Q before the most recent active transition
indicated by t or ,1.
..rt. = one high level pulse
lS
= one low level pulse
toggle = each output changes to the complement of its
previous level on each active transition indicated
bytor,1.
If, in the input columns, a row contains only the symbols H,
L, and/or X, this means the indicated output is valid whenever the input configuration is achieved regardless of the
sequence in which it is achieved. The output persists so
long as the input configuration is maintained.

One-Shot: Monostable multivibrator; a flip-flop that only has
one stable state. When triggered by an input transient, it
flips to its unstable state for a time period determined by an
external R-C network connected to its timing inputs, and
then returns to its stable state.
Shift Register: A series of flip-flops in which the data Signal
is shifted out of one flip-flop and into the succeeding flip-flop
during an active transition on the clock input.
Transceiver: A logic circuit that can transmit data onto a
bus line and receive data off of the bus line using the same
terminal as an input and output. The direction of signal flow
is determined by logic levels present at a Direction Control
input.
OTHER TERMS

If, in the input columns, a row contains H, L, andlor X together with t andlor ,1., this means the output is valid
whenever the input configuration is llchieved but the transition(s) must occur following the achievement of the steady
state levels. If the output is shown as a level (H, L, Qo, or
00), it persists so long as the steady state input levels and
the levels that terminate indicated transitions are maintained. Unless otherwise indicated, input transitions in the
opposite direction to thoSe shown have no effect on the
output. If the output is shown as a pulse, ..rt. or lS, the
pulse follows the indicated input transition and persists for
an interval dependent on the circuit.
Among the most complex function tables in this book are
those of the shift registers. These embody most of the symbols used in any of the function tables, plus more. As an
example, Figure 1 is the function table for a 4-bit bidirectional universal shift register, similar to the DM54LS194.
The first line of the table represents "asynchronous" clearing of the register and indicates that if CLEAR is low, all four
outputs will be reset low regardless of the states of the other inputs. In the succeeding lines, CLEAR is inactive (high)
and consequently has no effect.

Asynchronous: A mode of operation that does not require
any specific timing relationship between different control inputs.
Open Collector: Output confrguration that has no internal
pullup. This configuration enables outputs that are connected together (wired-OR) to assume oPPOsite states without
incurring damage.
Schmitt Trigger: An input configuration that has a different
threshold point depending on whether the input signal is
rising or falling. This is especially useful in electrically noisy
environments.
Synchronous: A mode of operation where specific timing
requirements must be met between control inputs before an
indicated action can occur.
Totem Pole: An output configuration that contains an internal pull up structure, usually a transistor pullup allowing higher output drive capability than is available with open collector outputs.

1-66

AC Operating Conditions and Characteristics (Continued)
The second line indicates that so long as the CLOCK input
remains low (while CLEAR is high), no other input has any
effect and the outputs maintain the IEll/eis they assumed
before the steady-state combination of CLEAR high and
CLOCK low was established. Since on all the other lines of
the table only the rising edge of the CLOCK is shown to be
active, the second line implicitly shows that no further
change in the outputs will occur while the CLOCK remains
high or on the high-to-Iow transition of the CLOCK.

tively, and the data previously at OD has been shifted out of
the register. This entry of data and shifting takes place on
the low-ta-high level transition of CLOCK when S1 is low
and SO is high and as shown, the levels at the PARALLEL
inputs, A through D, have no effect.

The third line of the table represents "synchronous" parallel
loading of the register and indicates that if S1 and SO are
both high, then regardless of the levels at the SERIAL inputs, the data present at A will transfer to OA, the data
present at S will transfer to OS, and so forth, following a
low-to-high transition on CLOCK.

The sixth and seventh lines represent the "synchronous"
loading of high and low level data respectively, from the
SHIFT LEFT SERIAL input and the shifting one bit to the left
of previously entered data; data previously at OD is now at
OC, data previously at QC and OS is now at OS and OA
respectively, and the data previously at OA has been shifted
out of the register. This entry of serial data and shifting to
the left takes place on the low-to-high level transition of
CLOCK when S1 is high and SO is low and as seen, the
levels at the PARALLEL inputs, A through D, have no effect.

The fourth and fifth lines represent the "synchronous" loading of high and low level data, respectively, from the,SHIFT
RIGHT SERIAL input and the shifting one bit to the right of
previously entered data; data previously at OA is now at OS,
data previously at OS and OC is now at OC and OD respec-

The last line indicates that so long as both MODE inputs are
low, no other input has any effect and, as in the second line,
the outputs maintain the levels they assumed before the
steady state combination of CLEAR high and both MODE
inputs low was established.

Inpula

Mode
Clear

L
H
H
H
H
H
H
H

Clock

Parallel

Left

Right

A

B

C

0

QA

QB

Qc

X
X
X
X
X

X
X
X

X
X

X
X

X
X

X
X

L

L

L

L

a

b

c

d

OBO
b

OCO
c

ODO
d

H
L

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

OAO
a
H
L

OAn
OAn
OCn
OCn
OBO

OBn
OBn
ODn
ODn
Oco

OCn
OCn
H
L

S1

SO

X
X

X
X

X

H
L
L
H
H
L

H
H
H
L
L
L

t
t
t
t
t

H
L

X

X

L

Outputs

Serial

X
X
X

FIGURE 1. Function Table

1-67

OBn
OBn
OAO

QD

ODO

DM54/74, 5451745 Test Waveforms
Parameter Measurement Information

Load Circuit for BI-State
Totem-Pole Outputa

RL

Ct
. (See Note A)

t~

UNDER TEST.

RL

TEST

51

POINT

f:-..

l

Vee

POINT

. r

FROM OUTPUT

(See Note B)

UNDER TEST

TEST

vee

TEST Vee

POINT

FROM OUTPUT

Load Circuit for TRI-sTATEe Outputa

Load Clrc;ult for
Open-Collector Outputs

FROM OUTPUT -

Note A)

UNDER TEST

....- - H. . . (See Note B)

TLIX/0005-2

TLlX/0005-1

TL/X/0005-3
Note A: CL Includes probe and jig cape.cItance.

Note B: All dtodas are 1N916 or 1N3064.

Input Wavetonn
54174 tr s: 7 ns; tf s: 7 ns
545/745 tr s: 2.5 ns, tf s: 2.5 ns
Generator: ZOUT :::: 500.
PRR s: 1 MHz

-----

3V
OV

TLlX/0005-4

volta(je Wavetonns
Setup and Hold Times

Voltage Wavetonns
Pulse Widths
3V

L

T_

HIGH-LEVEL
PULSE

4~:-------OY

INPUT - - - -......

~Iaetup...t-"'~-t

DATA
INPuT

-rl - - - - 3 Y

~
I

I

1.S Y

1.S Y

LOW-LEYEL

OY

PULSE
TL/X/0005-6

TLlX/0005-5

1-68

DM54/74, 5481748 Test Waveforms (Continued)
Parameter Measurement Information (Continued)

Voltage Waveforms Propagation Delay Times
INPUT

1

I

:

I

I-IfIHL ----l

L.-IIILH -+I
IN-PHASE
OUTPUT

ov

i y.sv:

~J..---VOH

I

I

VOL

:-1fIHL -f

:- \put -f

I

I

I

I 1.5V

~~s_v______~~:::

OUT-oF-PHASE

OUTPUT
(S-NoteE)

TUX/0OO5-7

Voltage Waveforms Enable and Disable Times, TRI-sTATE Outputs

=VELX
ENAIIUNG)

SV

I

'

:-tm.---J
I
____
~"'

WAVEFORM 1
(S-NoteC)

I
I

S1 CI.OSED
S20PEN

~3V
:-II>LZ-tI
I
Y---t.. '"

---L4-:~----------.DV
"'4.SV

I

I
:

1.SV

I

SUND
52 CLOSED

1.5V

----!j---".- - - 'T ---. VOL
IIIHZ
o.s V0.5 V

I

r-

I---tpZH---l

£

-!

I L - t - -___ VOH

WAVEFORM 2
(S-NoteC)

S10PEN
52CLOSED

I 1.5V
______ oV

,.-

_ 1.5 V

~~

TUX/0005-8

N_ C: Wavefonn 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output
with Internal conditions such that the output is high except when disabled by the output control.
Note D: In the examples above, the phase relationships between Inpuls and outputs have been chosen arbitrarily.

Note E: When measuring propagation delay times of TRI-STATE outputs, switches 81 and S2 are closed.

1-69
"~~"""'----

•

r-------------------------------------------------------------------------------------~

Ji
I-

DM54L/74L, 54LS/74LS Test Waveforms
Parameter Measurement Information

Load Circuit for BloState
Totem-Pole Outputs

RL

FROM OUTPUT

FROM OUTPUT ~~H""
UNDER TEST

(Se;';1; ii)l

UNDER TEST

I

(See Note A) -::-

TEST
POINT

VCC

TEST Vee
POINT

ClI

TRloSTATE Outputs

Load Circuit for OpenCollector Outputs

C1*
(See Note C)I

t~

r
Rl

TEST
POINT

••

FROM OUTPUT -~--H
UNDER TEST

f;t-eeNoteA)

-¥

........ClI
)~

(

TL/X/Ooo5-10

TL/X/0005-9

TLiX/Ooo5-11

Note A: CL includes probe and Jig capacitance.
Nola a: All dlodaa are 1N916 0' 1N3054.
Note C: Cl (30 pF) Is used 10, testing Series

54lf74l devices only.

Input Waveform
54LSI74LS: t,

3V

s: 6 ns, If s: 6 ns
s: 60 ns, t, s: 60 ns
s: 25 ns, If s: 25 ns

54L174L gates and inverters: I,

OV

54L174L flip-flops and MSI: t,
Generalor: ZOUT :::: 500

PRR

TL/X/OOO5-12

3V'

~1.3V

HIGH-lEVEL
PULSE

----~~r---------OV.
i-tntup-t-lhoIcI-t

-r----

3V
DATA~:
1.3 V
1.3 V

INPUT

1 MHz

Voltage Waveforma
Pulse Widths

Voltage Waveforms
Setup and Hold Times
IIPUT
TIllING

s:

lOW-lEVEL
PULSE

OV,

TL/X/0005-14

TL/X/0OO5-13

1-70

DM54L/74L, 54LS/74LS Test Waveforms (Continued)
Parameter Measurement Information (Continued)

Voltage Waveforms Propagation Delay Times

I

I '-----oV

I-II'HL-+I

~--+--~-t--

_IE

I
I

OUTPUT

l-IJILH -l

~~3_V

OUT-Of-PHASE
OUTPUT
,See_F)

VOH

VOL

I

l- 1M.-I

-

___

-J~:::
TUX/OOOS-IS

Voltage Waveforms Enable and Disable Times, TRI-STATE Outputs

=VEL

~)

WAVEFORM 1

,See_D)

~3V

~UV

~~.---------------------- ----4~::~-------- ---ov
I
~lJILz-t

l-tpZL--j

~+-_---"'4.sv

,
I

SI CLOSED

I 13 V

'S2OPEN
I

,

(See_D)

SIOPEN
S2CLOSED

I

I

I

I

-

I

i

~tpZH---l

WAVEFORM 2

I

!Ir

'"

I.SV

0.5 V 0.5 V

_____________-..:l. _t -

UV
_____ '" OV

t..

---.----VOL

,---

r-'PHz-l

£'

SI AND
S2CLOSED

----

,.SI AND
S2CLOSED

VOH

",'.SV

TL/X/0005-16

Note D: Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output
with internal conditions such that the output is high except when disabled by the output control.
Note E: In the examples above, the phaSe rel8t1onshlps batween inputs and outputs have been chosen arbHrarily.
Note F: When maasuring propagation delay times of TRI-8TATE outputs, swHches 51 and 52 are closed.

1-71

• r---------------------------------------------------------------------------------,

J.

Test Waveforms DM54ALS/74ALS, 54AS/74AS
Load Circuit for Bi-state Totem-Pole Outputs

Load Circuit for Open-Collector Outputa

Vee

~

FROM OUTPUT

UNDER TEST

f NT
TpO'
RL

lEST

.I

CL

TL/X/OOOS-17

TUX/OOO5-33

Voltage Waveforms Propagation Delay nmes

~-~~~---------

INPUT

3.5V

~O.3V

-./I''''

-IpLH-I_-t--Ip. .

HLJ-----

IN PHASE
OUTPUT

VOH

1.3V

-trtIL-\

Val

-IPLH-\

.

F
. ._ _ _

O~&r; - - -......~'",.3V____ ~~

VOL
TUXlOOO5-18

Voltage Waveforms Setup and Hold nmes

,--------3j

p:~ME1::~llll~.

I.3V
-------,- - REFERENCE
INPUT

I

-

-

-

-

-

-

0.3

----------------3.5

NE~l\~:f:l~~~roN ~11.3V
_
1

18ETUPI _ _
'"--IH-OL-0-1-_-'---0.3

r---------"'- - - VoH
1.3V

INPUT

1-

IIlTUPO - - IHOLOO

I.3V
Tl/X/OO05~ 19

Voltage Waveforms Pulse Widths
HI6H·LEVEl
PULSE

~
11.3V
1.3V I

---3.5V

-tw-

I-Iw-I

LOW.LEVEl~.3V
1.3V
PULSE

O.3V

3.5V

----0.3V
TUX/0005-22

_

All Input pulses are supplied by generatorS having Ihe following chareclBrisllcs: frequency - 1 MHz, louT = 500, Ir =

1-72

tr = 2 ns.

Test Waveforms DM54ALS/74ALS, 54AS/74AS (Continued)
Load Circuit for
TRI-ITATE Outputs

Voltage Waveforms
Setup and Hold Times

1vI

p~\~MEf::~ll:I~N

r-------3~

S1

I.3V

-------,,- -

1
INPUT
-------.- -

-

-

-

-

-

--8.3

-

-

-

-

-

-

II

REFERENCE

WITH RESPECT TO
NEGATIVE TRANSITION

1

Isnup 1 -

IiUOIl

-3.5

II.3V
_'--I-HO-LO-l-_-I--- O.3

CL

R2

50pF

&G01l

- - -VoH
1.3V

INPUT

1-

IlnuPO - - IHDLDD

TL/X/OOO5-20

1.3V

TL/X/OOO5-19

Voltsge Waveforms
Propagation Delay Times

Voltage Waveforms
Pulse Widths

~
11.3V
t.3V 1

---3.5V

HI8H·LEVEL
PULSE

-IW-

0.3V

•
'I
~

3.5V

IW

LOW·LEVEl
PULSE

Vel

1.311

1.311

----0.3V

-IPHL-I
tnH-1
O~~~f ---""""'~....~_V_ _ _F
..~~_".. VGI.

TL/X/OOO5-22

TL/X/0005-21

vOltage Waveforms
Enable and Disable Times, TRI-ITATE Outputs
Parameter

S1 Switch Position

TplH
TpHl
TpHZ
TpZH
TpLZ
TpZl

OPEN
OPEN
OPEN
OPEN
CLOSED
CLOSED

LOW-lEVfL

ENAILIN.

f.

~13V

3.5

,.-__",\ i---13V

I"

-0.3V

~::tt.~~L ~11.3V
OUTPUT
CONnOL

Ipn

IpZN

~

~.3V

_Ix. ~1.311
.

-I

1-

----8.3V

1...

IPlZ

r

1......--=·3.5V
O.3V
t(__

-

-T-VII.

-II-=I~ l. _VOH
--L o.3v

1.311

'OV
TLlX/OO05-23

NOTE: Allinpul pulses are supplied by generators having the following characIeriatIcs frequency - 1 MHz, lour = SOO, t, =

1·73

It= 2 nL

Group 4 Test Waveforms. DM~4ALS/74ALS, 54AS/74AS
54ALS74, 109,112, 113, 114, 131, 137,160, 161,162, 163, 168,169, 174,175,273
54AS74, 109, 112, 113, 114, 160, 161, 162,163, 168,169,174,175,273
Load Circuit for Bi-state Totem-Pole Outputa

Voltage Waveforms Setup and Hold nmea

k.a

WITH REIPECT TO

3.&

_P_O_81T_IVE_TRA_N_81_TI_O._,.,~ ::.V _ _ _ _ _ _ _ G.3

I

REFEIlENCE
IIPUT

--------~---------l5

'N,.av

IE~~\~:~~~I~O.

1-

TL/X/OOO5-27

---L-_-_-:

IIETUP I -I-'--'H-OL-O-I

1.3V

INPUT

1-

'lETUP 0 -

-

'HOLD D

I.3V

TLlX/OOOS-2B

Voltage Waveforms
Pulse Widths

Voltage Waveforms
Propagation Delay nmea

~
II.3V
1.3V 1
-'wQ.3V
---3.5V

HIGH·LEVEL
PULSE

LOW.LEVEL

PULSE

'W
'I
~
I.3V

1.3V

IBPUT

35V

IN PIIOE
OUTPUT

.

~.3V

~~-••••-

-~1 ~-+_"'. .LJ-_..

-'m

TLlXlOOO5-29

:

VGH

1.3V

-I

----Q.3V

•••

Df.?~ ----~...

-m-I

.3V
___

'VOL

~F_
. ~~.__ VOL

-

TLlX/OOO5-30

NOTE: All input pulses are supplied by generalOrs having the following characteristics: frequency = 1 MHz, ZOUT = 5On, Ir = " = 2 ns.

1-74

Group 5 Test Waveforms DM54ALS/74ALS, 54AS174AS
~LS01,03,05,09,12,15,2~33,38,518,519,522,689,1003,1005,1035

Load Circuit for
Open-Collector Outputs
cc

~

Rl (See Nat. BI

FROM
OUTPUT
UNOER TEST

r

TEST POINT
50pF

TLIX/OOO5-SI

NOTES:

A. CL includes probe and Jig capacitance
B. RL = 2 kO for standard outputs
RL

= 6670 for buffered Ou1puts

Voltage Waveforms
Propagation Oelay Time.
INPUT

~~~~----------

-./i ,..,

3.5V

~ D.3V

-~1

-lI'Hl-I______
VON

II PIIASt

1.3V

OUTPUT

VOL

~IPHl-1
OUT
OF PIIAJE
OUTPUT

~JV

-IpLH-1

EVOl
TLIX/OOO5-32

Note: All Input pulses are supplied by generators having the following characteristics: frequency

= 1 MHz, Zour = 500, I, = If = 2 ns.

II

1-75

Section 2

Advanced Low Power
Schottky

Section 2 Contents
DM54174ALSOOA Quad 2-lnput NAND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-5
DM54174ALS01 Quad 2-lnput NAND Gates with Open-Collector Outputs. .. . .. . .. .. . . .. . ..
2-7
DM54174ALS02 Quad 2-lnput NOR Gates .... , . .. . .. .. . .. . .. .. . .. .. ... . .. .. . .. . . .. .. . .
2-9
DM54174ALS03B Quad 2-lnput NAND Gates with Open-Collector Outputs ...•............ ·2-11
DM54174ALS04B Hex Inverters...................................................... 2-13
DM54174ALS05A Hex Inverters with Open-Collector Outputs ............................ 2-15
DM54174ALS08 Quad 2-lnput AND Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
DM54174ALS09 Quad 2-1 nput AND Gates with Open-Collector Outputs ................... 2-19
DM54174ALS10A Triple 3-lnput NAND Gates.......................................... 2-21
DM54174ALS11A Triple 3-lnput AND Gates........................................... 2-23
DM54174ALS12A Triple 3-lnput NAND Gates with Open-Collector Outputs................ 2-25
DM5417 4ALS13 Dual4-lnput NAND Gates with Schmitt Trigger Inputs .. . . . . . . . . . . . . . . . . . . 2-27
DM5417 4ALS14 Hex Inverters with Schmitt Trigger Inputs .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
DM54174ALS15A Triple 3-lnput AND Gates with Open-Collector Outputs.. .. . .. .. . ... ... . . 2-32
DM54174ALS20A Dual4-lnput NAND Gates................................ ........... 2-34
DM54174ALS21 A Dual 4-lnput AND Gates ............................................ 2-36
DM54174ALS22B Dual4-lnput NAND Gates with Open-Collector Outputs.. . .. . .. . . . . .. .. . 2-38
DM54174ALS27 Triple 3-lnput NOR Gates............................................ 2-40
DM54174ALS28A Quad 2-lnput NOR Buffers. . . . . . . . .. . .. . . .. .. .. . .. .. .. .. . . . . ... .. . .. 2-42
DM54174ALS30A 8-lnput NAND Gate.................... ............................ 2-44
DM54174ALS32 Quad 2-lnput OR Gates. . . . .. . .. . ... .. ... . . .. .. . .. ... ... .. . .. . . .. . .. .2-46
DM5417 4ALS33A Quad 2-lnput NOR Buffers with Open-Collector Outputs. . . . . . . . . . . . . . . . . 2-48
DM5417 4ALS37 A Quad 2-lnput NAND Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
DM54174ALS38A Quad 2-lnput NAND Buffers with Open-Collector Outputs ............... 2-52
DM54174ALS40A Dual4-lnput NAND Buffers.......................................... 2-54
DM54174ALS74A:Dual D Positive-Edge-Triggered Flip-Flops with Preset and Clear......... 2-56
DM54174ALS86 Quad 2-lnput Exclusive-OR Gates..................................... 2-59
DM54174ALS109A Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear.. . . . . 2-61
DM54174ALS 131 3 to 8 Line Decoder/Demultiplexer with Address Register ............... 2-64
DM54174ALS132 Quad 2-lnput NAND Gates with Schmitt Trigger Inputs. .. .. .. . .. . . .. .. . . 2-67
DM54174ALS13313-lnput NAND Gate................................................ 2-69
DM54174ALS136 Quad 2-lnputs Exclusive-OR Gates with Open-Collector Outputs ......... 2-71
DM54174ALS137 3 to 8 Line Decoder/Demultiplexer with Address Latches................ 2-73
DM54174ALS138 3 to 8 Line Decoder/Demultiplexer................................... 2-76
DM54174ALS1511 of8LineDataSelector/Multiplexer ...•..................•.......... 2-79
DM54174ALS153 Dual 1 of 4 Line Data Selectors/Multiplexer............................ 2-83
DM54174ALS157 Quad 1 of 2 Line Data Selectors/Multiplexers.......................... 2-86
DM54174ALS158 Quad 1 of 2 Line Data Selectors/Multiplexers.......................... 2-86
DM54174ALS160B Synchronous 4-Bit Decade Counter with Asynchronous Clear. . . . . . . . . . . 2-89
DM54174ALS 161 B Synchronous 4-Bit Binary Counter with Asynchronous Clear . . . . . . . . . . . . 2-89
DM54174ALS 162B Synchronous 4-Bit Decade Counter with Asynchronous Clear. . . . . . . . . . . 2-89
DM54174ALS163B Synchronous 4-Bit Binary Counter with Asynchronous Clear. . . . . . . . . . . . 2-89
DM54174ALS 165 8-Bit Parallel In/Serial Out Shift Register .............................. 2-97
DM54174ALS166 8-Bit Parallel Load Shift Registers..... ................•.............. 2-102
DM5417 4ALS168B Synchronous 4-Bit Up/Down Decade Counter . . . . . . . . . . . . . . . . . . . . . . .. 2-106

2-2

Section 2 Contents (Continued)
DM54174ALS169B Synchronous 4-Bit Up/Down Binary Counter.........................
DM54174ALS 174 Hex D Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . .. • . . . . . . . . . . • . .. .. . ..
DM54174ALS 175 Quad D Flip-Flops with Clear and Complementary Outputs. . . . . . . . . . . . . ..
DM54174ALS190 Synchronous 4-Bit Up/Down Decade Counter..... ........... .........
DM5417 4ALS191 Synchronous 4-Bit Up/Down Binary Counter. . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54174ALS192 Synchronous 4-Bit Up/Down Decade Counter with Clear and Dual Clock..
DM5417 4ALS193 Synchronous 4-Bit Up/Down Binary Counter with Clear and Dual Clock ...
DM54174ALS240A Octal TRI-STATE Inverting Buffers/Line Drivers/Line Receivers........
DM54174ALS241A Octal TRI-STATE Buffers/Line Drivers/Line Receivers. ...............
DM54174ALS242B Quad TRI-STATE Inverting Bus Transceivers.........................
DM54174ALS243A Quad TRI-STATE Bus Transceivers....... ........... ...............
DM54174ALS244A Octal TRI-STATE Bus Driver. ......................................
DM54174ALS245A Octal TRI-STATE Bus Transceivers..... ......•......... .. ..........
DM54174ALS251 TRI-STATE 1 of 8 Line Data Selector/Multiplexer... .... ......... .......
DM54174ALS253 TRI-STATE Dual 1 of 4 Line Data Selectors/Multiplexers................
DM54174ALS257 Quad TRI-STATE 1 of 2 Line Data Selectors/Multiplexers ..... . . . . . . . . ..
DM54174ALS258 Quad TRI-STATE 1 of 2 Line Inverting Data Selectors/Multiplexers.......
DM54174ALS273 Octal D-Type Edge-Triggered Flip-Flops with Clear.....................
DM54174ALS352 Dual 1 of 4 Line Inverting Data Selectors/Multiplexers. . . . . .. . . . . . . . . . . ..
DM54174ALS353 TRI-STATE Dual 1 of 4 Line Data Selectors/Multiplexers. . . . . . . . . . . . . . ..
DM54174ALS373 Octal D-Type TRI-STATE Transparent Latches.........................
DM54174ALS374 Octal TRI-STATE D-Type Edge-Triggered Flip-Flops........ ............
DM54174ALS390 Dual 4-Bit Decade Counters ... . . . . .. . . . . . . . . . . . . . . . . . .. . . . . .. . . .. . ..
DM54174ALS465A Octal TRI-STATE Buffers/Bus Drivers.......... ......... .........•..
DM54174ALS466A Octal TRI-STATE Inverting Buffers/Bus Drivers.......................
DM54174ALS467A Octal TRI-STATE Buffers/Bus Drivers...............................
DM54174ALS468A Octal TRI-STATE Inverting Buffers/Bus Drivers.......................
DM54174ALS518 Octal 8-Bit Identity Comparator with Open-Collector Outputs . . . . . . . . . . . ..
DM54174ALS519 Octal 8-Bit Identity Comparator with Open-Collector Outputs. . . . . . . . . . . •.
DM5417 4ALS520 Octal 8-Bit Identity Comparator ......................................
DM5417 4ALS521 Octal 8-Bit Identity Comparator ......................................
DM5417 4ALS522 Octal 8-Bit Identity Comparator with Open-Collector Outputs. . . . . . . . . . . ..
DM5417 4ALS533 Octal D-Type Transparent Latches with TRI-STATE Outputs. . . . . . . . . . . ..
DM5417 4ALS534 Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs ........
DM5417 4ALS540 Octal Inverting Buffers and Line Drivers with TRI-STATE Outputs. . . . . . . ..
DM5417 4ALS541 Octal Buffers and Line Drivers with TRI-STATE Outputs . . . . . . . . . . . . . . . ..
DM5417 4ALS563A Octal D-Type Transparent Latches with TRI-STATE Outputs. . . . . . . . . . .•
DM54174ALS564A Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs. .. . . ..
DM54174ALS573B Octal D-Type Transparent Latches with TRI-STATE Outputs. . . . . . . . . . •.
DM54174ALS574A Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs.......
DM54174ALS576A Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs.......
DM54174ALS580A Octal D-Type Transparent Latches with TRI-STATE Outputs.. . . . . . . . ••.
DM5417 4ALS590 8-Bit Binary Counter with Output Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54174ALS620A Octal TRI-STATE Bus Transceiver. ..... .........................•.•
DM54174ALS640A Inverting Octal Bus Transceivers. .. ..... ....................•.•.•...
DM54174ALS645A Octal TRI-STATE Bus Transceivers......... ....•....... .. ..........
DM54174ALS646 Octal TRI-STATE Bus Transceivers and Registers............ ..........
DM54174ALS648 Octal TRI-STATE Inverting Bus Transceivers................. .........
DM54174ALS652 Octal TRI-STATE Bus Transceivers and Registers... .... ............•..
DM54174ALS689 8-Bit Comparator ........ , . . . . . . . . . . . . . . . .. . . . . . . . • . . . . . . . . . . .. . . . ..

2-3
-~

--~

~----

2-106
2-111
2-111
2-115
2-115
2-122
2-122
2-129
2-129
2-133
2-133
2-137
2-140
2-143
2-147
2-150
2-150
2-154
2-158
2-161
2-164
2-168
2-172
2-176
2-176
2-176
2-176
2-180
2-180
2-180
2-180
2-180
2-184
2-188
2-192
2-195
2-198
2-202
2-206
2-210
2-214
2-218
2-222
2-226
2-229
2-232
2-235
2-239
2-243
2-247

fI

Section 2 Contents (Continued)
DM54174ALS804A Hex 2-lnput NAND Driver ••••......••.••..•..•.......••........••.•
DM54174ALS805A Hex 2-lnput NOR Driver. . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM54174ALS808A Hex 2-lnput AND Driver. • • • . • . . . . . . • • • . • • . . . • . . • . . . . . • • . . . . . . . . • . .•
DM54174ALS810 Quad 2-lnput Exclusive-NOR Gates ............•.....................
DM54174ALS811 Quad 2-lnput Exclusive-NOR Gates with Open-Collector Outputs.. . . . .. ..
DM54174ALS832A Hex 2-lnput OR Drivers. .... . . .. .. .. . .. . . . . . . . • . . . . ... .. . . . . . • . . . ..
DM54174ALS873B Dual4-Bit D-Type Transparent Latches with TRI-STATE Outputs........
DM54174ALS874B Dual4-Bit D-Type Edged-Triggered Flip-Flops with TRI-STATE Outputs..
DM54174ALS876A Dual4-Bit D-Type Edged-Triggered Flip-Flops with TRI-STATE Outputs..
DM54174ALS880A Dual4-Bit D-Type Transparent Latches with TRI-STATE Outputs. • . . . • ..
DM54174ALS1 OOOA Quad 2-lnput NAND Buffer. • . . • • . . . . • • . • . • . • • . . . . . . . . • . . . . . . . . . . ..
DM5417 4ALS 1002A Quad 2-lnput Positive NOR Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM5417 4ALS1 003A Quad 2-lnput NAND Buffer with Open-Collector Outputs .......••.•...
DM54174ALS1004 Hex Inverting Drivers ...............................................
DM54174ALS1005 Hex Inverting Drivers with Open-Collector Outputs.................. ...
DM54174ALS1 008A Quad 2-lnput AND Buffers ........................................
DM54174ALS1 01 OA Triple 3-lnput NAND Buffers. • . .. • .. . . . .. .. • .. . . . . .. . .. . . .. . . . . . . ..
DM54174ALS1011A Triple 3-lnput AND Buffers. . . . .. . •. . . . .. .. .•• .. . . .. . .. . . .. . . . . . . ..
DM54174ALS1020A Dual4-lnput NAND Buffers................................... ...••
DM54174ALS1 032A Quad 2-lnput OR Buffers •.....•..................................
DM54174ALS1034 Hex Non-Inverting Buffers..........................................
DM54174ALS1035 Hex Non-Inverting Buffers with Open-Collector Outputs................
DM54174ALS1240 Octal TRI-STATE Inverting Bus Drivers/Receivers.....................
DM54174ALS1241A Octal TRI-STATE Bus Drivers/Receivers...........................
DM54174ALS1242 Quad TRI-STATE Inverting Bus Drivers. . •. .. .. • . . .. . . . .. . . ... • . . . . ..
DM54174ALS1243A Quad TRI-STATE Bus Drivers .....••.••.•.•• , .. • . .. . .. . . ... . . . . . ••
DM54174ALS1244A Octal TRI-STATE Bus Drivers................. ....................
DM54174ALS1245A TRI-STATE Bus Transceivers .....................................
DM54174ALS1645A Octal TRI-STATE Bus Transceivers ...•••.....•....•..... , . . . . •. • .•
DM54174ALS2541 Octal Buffers and MOS Line Drivers with TRI-STATE Outputs . . . . . . . . . ..
DM54174ALS2645 Octal TRI-STATE Transceivers .....................................
DM54174ALS5245 Octal TRI-STATE Transceivers.. .. .. . .. . .. . . . . . . .. . .. . . . .. . . . . . . . ..
DM54174ALS5620 Octal TRI-STATE Transceivers.. .. .. . • . • • . • . . . . . .. . .. . . . . . . . . • .. . .•

2-250
2-252
2-254
2-256
2-259
2-261
2-263
2-267
2-271
2-275
2-279
2-281
2-283
2-285
2-287
2-289
2-291
2-293
2-295
2-297
2-299
2-301
2-303
2-303
2-307
2-307
2-311
2-314
2-317
2-320
2-323
2-326
2-329

i

;

~ Semiconductor
National

Corporation

DM54ALSOOA/DM74ALSOOA
Quad 2-lnput NAND Gates

C

iI:::
......

• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

General Description
This device contains four independent gates, each of which
performs the logic NAND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vc;c range

t
r.:

~
_

Connection Diagram
Dual·ln·L1ne Package

vee

...

1A

1.

4A

4Y

3B

3A

3Y

1Y

2A

2B

2Y

GND

2
TL/F/8270-1

Order Number DM54ALSOOAJ, DM74ALSOOAM or DM74ALSOOAN
See NS Package Number J14A, M14A or N14A

Function Table
Y=AB

Output

Inputs

H
L

A

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

= High Logic Level
= Low logic Level

PI
2-5

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those valuBS
beyond which the safety qf the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guarantBBd at the abso/uta maximum ratings.
The "Recommended Opeiating Conditions" table will define
the condi,fiP,ns for actual device operation.

If MIlitary/Aerospace specified. devices are required,.
contact the National Semiconductor Sales OffIce/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Operating Free Air Temperature Range
DM54ALS
-55·C to + 125·C
DM74ALS
O·Cto +70"C
Storage Temperature Range

-65·C to + 150"C

Recommended Operating Conditions
Symbol

DM54ALSOOA

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IOH

High Level Output Current

DM74ALSOOA

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

IOL

Low Level qutput Current

TA

Free Air Operating Temperature

Units

Min

2

V

0.7

0.8

V

.::-0.4

-0.4

mA

8

mA

70

·c

4
-55

0

125

Electrical Characteristics
over recommended operating free air temperature range. All ty~1 values are measured at Vee

= 5V, T A = 25"C.

Symbol

Typ

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Min

Conditions

= 4.5V,11 = -18 mA
10H = -0.4mA
Vee = 4.5Vto5.5V
54174ALS
Vee = 4.5V
10L = 4mA

Vee

74ALS
10L = 8mA
II

Input Current at Max
Input Voltage

Vee

V

Units
V

Vee -2

,

V
0.25

0.4

V

0.35

0.5

V

0.1

rnA

= 5.5V, VIH = 7V

= 5.5V, VIH = 2.7V
= 5.5V, VIL = O.4V
Vo = 2.25V
Vee = 5.5V
Outputs High
Vee = 5.5V

Max
-1.5

IIH

High Level Input Current

Vee

20

/LA

IlL

Low Level Input Current

Vee

-0.1

rnA

10

Output Drive Current

-112

rnA

lee

Supply Current

0.43

0.85

rnA

1.62

3

rnA

Outputs Low

-30

-

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Del~y Time
High to Low Level Output

DM54ALSOOA

Conditions
Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

Note 1: See Section 1 for test waveform. and output load.

2-6

DM74ALSOOA

Units

M!n

Max

Min

Max

3

16

3

11

ns

2

13

2

8

ns

~ Semiconductor
National

Corporation

DM54ALS01/DM74ALS01 Quad 2-lnput
NAND Gates with Open-Collector Outputs
General Description

Features

This device contains four independent gates, each of which
performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

Pull-Up Resistor Equations
R

Vee (Min) - VOH
MAX = Nl (IOH) + N2 (I,H)

R
MIN =
Where:

Vee (Max) - VOL
IOL - N3 (I,U

Nl (IOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (I,H) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (I,U = total maximum input low current for aU
inputs tied to pull-up resistor

Connection Diagram
Dual-In-Une Package

vee

4Y

48

4A

3Y

3B

3A

8

7
1Y

1A

1B

2Y

2A

2B

GND
TLlF/6174-1

Order Number DM54ALS01J, DM74ALS01M Dr DM74ALS01N
See NS Package Number J14A, M14A or N14A

Function Table
y= AB
Inputs

Output

A

B

Y

L
L

L
L

H
H
H

H

L

H
H

H

H = High Logic Level
L

= Low Logic Level

2-7

fII

...

!
.....

~

ic

Absolute Maximum Ratings
Note: The "AbsoIufB MBXimum RstingS" are those values
beyond which the safety of the deviciecsnnot be guarsnteed. The device should not be operated st thes9limits. The
psrstTIBtric values defined in the "Electricsl ChsrscfBristics"
tsbIB are not gUllfBnfBed st the sbsolufB maximum ratings.
The "R9COfTIfTIBfIded ()pBnJting Conditions" tsbIB will define
the conditions for sctual device operation.

If MilitarylAerospace ap8cH'lecI devices are required,

contact the National Semiconductor Sales OffIce/
Distributors for availability and speclftcatlons.
Supply Voltage

7V

Input Voltage

7V
7V

High Level Output Voltage

Operating Free Air Temperature Range
-55"C to + 125·C
DM54ALS
DM74ALS
O"C to + 70"C
Storage Temperature Range

-65"C to

+ 150"C

Recommended Operating Conditions
Symbol

DM54ALS01

Parameter

DM74ALS01

Unlta

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.6

VOH

High Level Output Voltage

5.5

5.5

V

IOL

Low Level Output Current

4

8

mA

TA

Free Air Operating Temperature

70

·c

V

2

2

-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, T A = 25"C.
Symbol

Parameter

Conditions

Min

Typ

Max

Unlta

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

-1.5

V

IOH

High Level Output Current

Vee = 4.5V, VOH = 5.5V

100

IJoA

VOL

Low Level Output
Voltage

Vee = 4.5V

54174ALS
IOL =4mA

0.25

0.4

V

74ALS
IOL = 8mA

0.35

0.5

V

0.1

mA

II

Input Current @ Max.
Input Voltage

Vee = 5.5V, VIH = 7V

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

IJoA

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.1

mA

lee

Supply Current

Vee = 5.5V

Outputs High

0.43

0.85

mA

Outputs Low

1.62

3

mA

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

tpLH

Propagation Delay TIme
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS01

COnditions
Vee = 4.5V to 5.5V
RL = 2kO
CL=50pF

N.... 1: See Section 1 for test waveforms and output load.

2·8

DM74ALS01

Unlta

Min

Max

Min

Max

23

66

23

54

ns

8

39

4

28

ns

C

_

iii:

National
Semiconductor
Corporation

t

tg
~

DM54ALS02/DM74ALS02
Quad 2-lnput NOR Gates

C
!Ill:

.....
~

• Advanced oxide-isolated. ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

General Description
This device contains four independent gates. each of which
performs the logic NOR function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

~
I\)

Connection Diagram
Dual·ln-Llne Package

vee

Y4

B4

A4

Y3

B3

A3
8

Y1

0\1

81

Y2

A2

82

GIl)

TLlF/6175-1

Order Number DM54ALS02J, DM74ALS02M or DM74ALS02N
See NS Package Number J14A, M14A or N14A

Function Table
Y=A+B
Inputs

Output

A

B

Y

l
l
H
H

l
H
l
H

H
l
l
l

H - High logic Level

L

= Low Logic Level

fI
2-9

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the· device cannot be guarant99d. The device should not be operated at thesalimits. The
parametric values defifl9dln the "Electrical Characteristics"
table are not guaranteed at the absolute maximum retings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace sPecHled devices are required,
contact the National Semiconductor SeIM Office/
Distributors for availability and speclflcetlons.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
-55"Cto +125"C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·C to + 15O"C

Recommended Operating Conditions
Symbol

DM74ALS02

DM54ALS02

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

10L

Low Level Output Current

TA

Free Air Operating Temperature

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2
0.7

0.8

V

-0.4

-0.4

mA

8

mA

70

·c

4
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

= 5V, TA = 25·C.

Symbol

Typ

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Min

Conditions

= 4.5V,11 = -16 mA
10H = -0.4mA
Vee = 4.5V to 5.5V
54174ALS
Vee = 4.5V
10L = 4mA

Vee

Input Current @ Max.
Input Voltage

Vee

Units
V
V

0.25

0.4

V

0.35

0.5

V

0.1

mA

= 5.5V, VIH = 7V

= 5.5V, VIH = 2.7V
= 5.5V, VIL = O.4V
Vee = 5.5V
Vo = 2.25V
Outputs High
Vee = 5.5V

Max
-1.5

Vee - 2

74.ALS
10L = 8mA
II

V
V

2

IIH

High Level Input Current

Vee

20

/LA

IlL

Low Level Input Current

Vee

-0.1

mA

10

Output Drive Current

-112

mA

Icc

Supply Current

0.85

2.2

mA

2.16

4

mA

-30

Outputs Low

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS02

Conditions
Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Nota 1: See Section 1 lor test waveforms and output load.

2-10

DM74ALS02

Un"s

Min

Max

Min

Max

1

18

3

12

ns

1

11

3

10

ns

_

National
Semiconductor
CorporaHon

DM54ALS03B/DM74ALS03B Quad 2-lnput
NAND Gates with Open Collector Outputs
General Description

Features

This device contains four independent gates, each of which
performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

Pull-Up Resistor Equations
R

Vee (Min) - VOH
MAX = N1 (IOH) + N2 (lIH)

R
MIN =
Where:

Vee (Max) - VOL
IOL - N3 (IIU

N1 (IOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (IIU = total maximum input low current for all
inputs tied to pull-up resistor

Connection Diagram
Dual-In-Llne Package
Vee

B4

Y4

A4

B3

A3

Y3

8

A1

81

Y1

A2

82

Y2
TL/F/6176-1

Order Number DM54ALS03BJ, DM74ALS03BM or DM74ALS03BN
See NS Package Number J14A, M14A or N14A

Function Table
y= AB
Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H

~

High logic Level

L

~

Low Logic Level

2-11

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cennot 'be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

High Level Output Voltage

7V

Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70·C
Storage Temperature Range

- 65·C t6 + 150·C

Recommended Operating Conditions
Symbol

DM54ALS03B

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS03B

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2

Vil

Low Level Input Voltage

0.7

0.8

VOH

High Level Output Voltage

5.5

5.5

V

IOl

Low Level Output Current

4

8

mA

TA

Free Air Operating Temperature

70

·C

-55

125

0

V

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

Min

Typ

Max

Units

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18 mA

-1.5

IOH

High Level Output Current

Vee = 4.5V, VOH = 5.5V

100

p.A

VOL

Low Level Output
Voltage

Vee = 4.5V

V

54174ALS
IOl =4mA

0.25

0.4

V

74ALS
IOl=8mA

0.35

0.5

V

0.1

mA

II

Input Current @ Max.
Input Voltage

Vee = 5.5V, VIH = 7V

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

p.A

III

Low Level Input Current

Vee = 5.5V, Vil = 0.4V

-0.1

mA

lee

Supply Current

Vee = 5.5V

Outputs High

0.43

0.85

mA

Outputs Low

1.62

3

mA

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHl

Propagation Delay Time
High to Low Level Output

DM54ALS03B

Conditions
Vee = 4.5V to 5.5V
Rl = 2k!l
Cl = 50pF

Nole 1: See Section 1 for lest waveforms and outpulload.

2-12

DM74ALS03B

Units

Min

Max

Min

Max

20

59

20

50

ns

3

23

3

13

ns

IJ

Natlonal

Semiconductor
Corporation

DM54ALS04B/DM74ALS04B Hex Inverters
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TIL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

General Description
This device contains six independent gates, each of which
performs the logic INVERT function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual·ln·Une Package
Vee

1~4

1
A1

All

Y8

13

AS

12

2

11

3

Y1

A2

4
Y2

Y5
10

5
A3

A4

Y4
I

8
Y3

I

8

17
GHDi
TL/F/6177-1

Order Number DM54ALS04BJ, DM74ALS04BM or DM74ALS04BN
See NS Package Number J14A, M14A or N14A

Function Table
Y=A
Input

Output

A

Y

L
H

H
L

H = High Logic Level
L = Low Logic Level

2-13

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Dlstrlbutora for availability and specifications.
Supply Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The '''Recommended Operating Conditions" table will define
the conditions for actual device operation.

Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·0 to + 125·C
DM74ALS
O"Cto +70·C
Storage Temperature Range
-65·C to + 150"C

Recommended Operating Conditions
Symbol

DM54ALS04B

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

DM74ALS04B

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

10L

Low Level Output Current

TA

Free Air Operating Temperature

Units

Min

V
V

2
0.7

0.8

V

-0.4

-0.4

mA

8

mA

70

·C

4
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

=

VIK

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

10H = -O.4mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V

Typ

Max

Units

-1.2

V
V

Vee - 2

54/74ALS
10L = 4mA

0.25

0.4

V

74ALS
10L = 8mA

0.35

0.5

V

0.1

mA

II

Input Current @ Max.
Input Voltage

Vee = 5.5V, VIH = 7V

=

Min

4.5V,11 = -18 mA

IIH

High Level Input Current

Vee

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

10

Output Drive Current

Vee = 5.5V

Vo = 2.25V

lee

Supply Current

Vee = 5.5V

Outputs High

0.65

Outputs Low

2.4

5.5V, VIH = 2.7V
-30

20

/LA

-0.1

mA

-112

mA

1.1

mA

4.2

rnA

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol
tpLH

Parameter
Propagation Delay Time
Low to High Level Output

DM54ALS04B

Conditions
Vee = 4.5V to 5.5V
RL = 5000.
CL = 50pF

Propagation Delay Time
High to Low Level Output
Note 1: See Section 1 for test waveforms and output load.

tpHL

2·14

DM74ALS04B

Units

Min

Max

Min

Max

3

14

3

11

ns

2

12

2

8

ns

.------------------------------------------------------------------, 0
iii:

_

National

t

Semiconductor
CorporaHon

fi
~o

DM54ALS05A/DM74ALS05A Hex Inverters
with Open Collector Outputs

iii:

.....

General Description

Features

This device contains six independent gates, each of which
performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced OXide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

Pull-Up Resistor Equations
R
Vee (Min) - VOH
MAX = N1 (IOH) + N2 (ItH)
R
Vee (Max) - VOL
MtN = IOl - N3 (III)
Where:

N1 (IOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (ItH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (III) = total maximum input low current for all
inputs tied to pull-up resistor

Connection Diagram
Dual-in-Line Package

Vee

A6

Y6

A5

Y5

A4

Y4

14

13

12

11

10

1

2

3

4

567

A1

Y1

A2

Y2

A3

9

Y3

8

GND
TL/F/6178-1

Order Number DMS4ALSOSAJ, DM74ALSOSAM or DM74ALSOSAN
See NS Package Number J14A, M14A or N14A

Function Table
Y=A
Input

Output

A

Y

L

H

H

L

H

~

High Logic Level

L

~

low Logic Level

2-15

~~

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

H Military/Aerospace specified devices are required,
contact the NaDonal Semiconductor Sal.. Offlcel
Dlatrlbutora for availability and apeclflcaUons.
Supply Voltage
7V
Input Voltage
7V
High Level Output Voltage '
7V
Operating Free Air Temperature Range
-55"Cto + 125·C
DM54ALS
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·Cto +15O"C

Recommended Operating Conditions
Symbol

DM54ALS05A

Parameter

DM74ALS05A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4,5

5

5.5

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

VOH

High Level Output Voltage

5.5

5.5

V

IOL

Low Level Output Current

4

8

mA

TA

Free Air Operating Temperature

70

·c

2

2

-55

125

V
V

0

V

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V. TA = 25·C.
Symbol

Parameter

Max

Units

-1.5

V

100

p.A

Conditions

Min

VIK
IOH

High Level Output Current

Vee = 4.5V. VOH = 5,5V

VOL

Low Level Output
Voltage

Vee = 4,5V

II

Input Current @ Max
Input Voltage

Typ

Vee = 4.5V.11 = -18 mA

Input Clamp Voltage

54174ALS
IOL =4 rnA

0.25

0.4

V

74ALS
IOL=8mA

0.35

0.5

V

0.1

mA

Vee = 5.5V. VIH = 7V

IIH

High Level Input Current

Vee = 5.5V. VIH = 2.7V

20

p.A

IlL

Low Level Input Current

Vee = 5.5V. VIL = 0.4V

-0.1

rnA

ICC

Supply Current

Vee = 5.5V

Outputs High

0.65

1.1

rnA

Outputs Low

2.4

4,2

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

~L

Propagation Delay Time
High to Low Level Output

DM54ALS05A

Conditions
Vcc = 4.5V to 5.5V
RL = 2kO
CL=50pF

Note 1: See Section 1 for test waveforms and output lOad,

2·16

DM74ALS05A

Units

Min

Max

Min

Max

23

84

23

54

ns

4

24

4

14

ns

_

National
Semiconductor
Corporation

DM54ALS08/DM74ALS08
Quad 2-lnput AND Gates
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

General Description
This device contains four independent gates, each of which
performs the logic AND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package

vee

B4

A4

Y4

B3

A3

Y3

8

A1

B1

Y1

A2

B2

Y2

GND
TUF/6271-1

Order Number DM54ALSOSJ, DM74ALS08M or DM74ALS08N
See NS Package Number J14A, M14A or N14A

Function Table
y= AB
Inputs

Output

A

B

Y

L
L

L
H

H
H

L

L
L
L

H

H

H

= High logiC Level

L

= Low Logic Level

PI
2-17

Absolute Maximum Ratings
If MIlitary/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and speclflcationL
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55"C to + 125°C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65°C to + 15O"C

Note: The "Absolute Maximum Ratings" are those values
beyond which the ssfety of the device cannot be guarant88d. The device should not be operated at these limits. The
parametric values defined in the "Electricsl Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actusl device operation.

Recommended Operating Conditions
Symbol

DM74ALS08

DM54ALS08

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H
10L
TA

Free Air Operating Temperature

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

V
V

0.7

0.8

V

High Level Output Current

-0.4

-0.4

mA

Low Level Output Current

4

8

mA

70

°C

-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VOH

High Level Output
Voltage

10H = -0.4mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V

Min

Typ

Max

Units

-1.5

V
V

Vee- 2

54174ALS
IOL = 4mA

0.25

0.4

V

74ALS
IOL=8mA

0.35

0.5

V

0.1

mA

II

Input Current @ Max.
Input Voltage

Vee = 5.5V, VIH = 7V

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

pA

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.1

mA

10

Output Drive Current

Vee = 5.5V

Vo = 2.25V

-112

mA

lee

Supply Current

Vee = 5.5V

Outputs High

1.3

2.4

mA

Outputs Low

2.2

4

mA

-30

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol
tpLH
~L

Parameter
Propagation Delay Time
Low to High Level Output

DM54ALS08

Conditions
Vee = 4.5Vt05.5V
RL = 5000
CL=50pF

Propagation Delay Time
High to Low Level Output
Note 1: See Section 1 for teat waveforms and output load.

2-18

DM74ALS08

Units

Min

Max

Min

Max

4

18

4

14

ns

3

15

3

10

ns

National

~ Semiconductor
Corporation

DM54ALS09/DM74ALS09 Quad 2-lnput AND Gates
with Open Collector Outputs
General Description

Features

This device contains four independent gates. each of which
performs the logic AND function. The open-collector outputs require external pull-up resistors for proper logical operation.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated. ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

Pull-Up Resistor Equations
R
Vee (Min) - VOH
MAX = N1 (IOH) + N2 (IIH)
R
Vee (Max) - VOL
MIN =
IOL - N3 (Ill)
Where:

N1 (lOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (Ill) = total maximum input low current for all
inputs tied to pull-up resistor

Connection Diagram
Dual-In-Llne Package
U

A4

Y4

12

A1

11

3
Y1

B1

B3

Y3

10

8

7

A2

Y2

B2

GND
TLlF/6179-1

Order Number DM54ALS09J, DM74ALS09M or DM74ALS09N
See NS Package Number J14A, M14A or N14A

Function Table

Y=AB
Inputs

Output

A

B

Y

L
L

L

H

H
H

L

L
L
L

H

H

H = High logic Level
L - Lew logic Leval

2-19

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those vsluB8
beyond which the safety of the device cannot be gusran·
teed. The device should not be operated at thBSB limits. The

If Mllltary/Aeroapace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specfflcaUons.
Supply Voltage
7V
Input Voltage
7V

parametric values defined In the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Opsrsting Conditions" table will define
the conditions for actusl device operation.

High Level Output Voltage
7V
Operating Free Air Temperature Range
DM54ALS
-55°C to + 125°C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65°C to +15O"C

Recommended Operating Conditions
Symbol

DM74ALS09

DM54ALS09

Paremeter

Unlta

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

O.B

V

VOH

High Level Output Voltage

5.5

5.5

V

IOL

Low Level Output Current

4

B

mA

TA

Free Air Operating Temperature

70

°C

2

V

2

-55

0

125

V

Electrl.cal Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25°C.
Symbol

Max

Unlta

VIK

Input Clamp Voltage

Parameter

Vee = 4.5V, II = -1BmA

Min

-1.5

V

IOH

High Level Output Current

Vee = 4.5V, VOH = 5.5V

100

IlA

VOL

Low Level Output
Voltage

Vee = 4.5V

Conditions

Typ

54174ALS
IOL =4mA

0.25

0.4

V

74ALS
IOL = BmA

0.35

0.5

V

0.1

mA

II

Input Current @ Max
Input Voltage

Vee = 5.5V, VIH = 7V

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

/-LA

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.1

rnA

lee

Supply Current

Vee = 5.5V

Outputs High

1.3

2.4

mA

Outputs Low

2.2

4

mA

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS09

Conditions
Vee = 4.5Vt05.5V
RL = 2kO
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

2-20

DM74ALS09

Unlta

Min

Max

Min

Max

20

69

23

54

ns

5

23

5

15

ns

i

National

~ Semiconductor

t

Corporation

In
....

~

DM54ALS1 OA/DM7 4ALS1 OA
Triple 3-lnput NAND Gates
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TIL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

General Description
This device contains three Independent gates, each of
which perfonns the logic NAND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

I
In
....

ii:

Connection Diagram
Dual·ln·Une Package
Vee

C1

Y1

2
A1

81

C3

B3

A3

B2

C2

Y2

Y3

3
A2

TUF/6180-1

Order Number DM54ALS10AJ, DM74ALS10AM or DM74ALS10AN
See NS Package Number J14A, M14A or N14A

Function Table
Y=~

Output

Inputs

H

A

B

C

y

X
X
L
H

X
L
X
H

L
X
X
H

H
H
H
L

= High LogIc Level

L - Low Logic Level
X = Either Low or HIgh LogIc Level

fI
2-21

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings'~ anHhose values
beyond which the safety qf the device cannet be guarant88d. The device should not be operated at thesa limits. The
parametric valU8S defifl8d in the "Electrical Cheracterlstics"
table lire not guaranf88d at ~ absolute maximum ratings.
"Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54ALS
DM74ALS
O"Cto +70"C
-65·C to + 150·C
Storage Temperature Range

The

Recommended Operating Conditions
Symbol
Vee

Supply Voltage

VIH

High Lavellnput Voltage

VIL

Low Lavellnput Voltage

10H

High Level Output Current

DM74ALS10A

DM54ALS10A

Parameter

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

10L

Low Lavel Output Current

TA

Free Air Operating Temperature

0.7

0.8

V

-0.4

-0.4

mA

8

mA

70

·c

4
-55

125

0

Electrical Characteristics

=

Symbol

Typ

. Conditions

Parameter

=

=

VIK

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

10H = -0.4mA
Vee = 4.5Vto5.5V

VOL

Low Level Output
Voltage

Vee

II

Input Current @ Max
Input Voltage

Vee

IIH

High Level Input Current

Vee

IlL

Low Level Input Current
Output Drive Current

lee

Supply Current

=

=

=
Vee =
Vee =
Vee =

4.5V,11

4.5V

Min

5V, TA

=

-18 mA

25·C.

Max

Units

-1.5

V
V

Vee - 2

54/74ALS
10L = 4mA

0.25

0.4

V

74ALS
10L = 8mA

0.35

0.5

V

0.1

mA

5.5V, VIH = 7V

= 2.7V
5.5V, VIL = O.4V
5.5V
Vo = 2.25V
5.5V, VIH

5.5V

V
V

2

over recommended operating free air temperature range. All typical values are measured at Vee

10

Units

Min

-30

20

",A

-0.1

mA

-112

mA

Outputs High

0.32

0.6

mA

Outputs Low

1.2

2.2

rnA

Switching Characteristics over recommended operating free air temperature range (Note 1).
Symbol
tpLH

Parameter
Propagation Delay Time
Low to High Lavel Output

DM54ALS10A

Conditions
Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

Propagation Delay Time
High to Low Level Output
Note 1: See Section 1 for test waveforms and output load.

tpHL

2-22

DM74ALS10A

Units

Min

Max

Min

Max

2

16

2

11

ns

2

12

2

10

ns

•

National
SemIconductor

Corporation

DM54ALS11A/DM74ALS11A
Triple 3-lnput AND Gates

I'
• Advanced oxide-isolated. ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TIL counterpart
• 'improved AC performance over Schottky and low power Schottky counterparts

General Description
',This device contains three independent gates. each of
which performs the logic AND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Line Package

vee

C1

At

81

2

Y1

C3

B3

3
A2

82

C2

Y3

Y2
TLlF/6181-1

Order Number DM54ALS11AJ, DM74ALS11AM or DM74ALS11AN
See NS Package Number J14A, M14A or N14A

Function Table
y= ABC
Inputs

B

C

Y

X
X

X

L

L

L

?<
H

X
X

L
L
L

H

H

H
H

e

Output

A

High logic Level

L = Low Logic Level
X = Either Low or High LcgIc Level

2-23

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are. those values
beyond which the safety of .t~. r/evice cannot beguaranteed. The device should not be op6rated at these iimits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The ''Recommended Operating Conditfons"table will define
the qonditJons for actual device operatfon.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales OffIce/
DIstributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55°C to + 125°C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65°C to + 150"C

Recommended Operating Conditions
Symbol

DM74ALS11A

DM54ALS11A

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

10L

Low Level Output Current

TA

Free Air Operating Temperature

Unlta

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

0.7

0.8

V

-0.4

-0.4

mA

8

rnA

70

°C

2

2

V

4
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

=

Symbol

Typ

Parameter

Conditions

=

VIK

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

10H = -0.4 rnA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee

=

4.5V,11

=

4.5V

Min

-18 rnA

0.35

0.5

V

0.1

rnA

=

5.5V, VIH

=

2.7V

= 5.5V, VIL = 0.4V

IlL
10

Output Drive Current

Vee

=

lee

Supply Current

Vee

= 5.5V

5.5V

V

74ALS
10L = 8mA

Vee

Low Level Input Current

V

V

Vee

High Level Input Current

-1.5

0.4

7V

IIH

Units

0.25

=

Vee

25°C.

Max

54/74ALS
10L = 4mA

5.5V, VIH

Input Current @ Max
Input Voltage

=

Vee - 2

=

II

5V, TA

Vo

=

2.25V

-30

20

p.A

-0.1

rnA

-112

rnA

Outputs High

1

1.8

rnA

Outputs Low

1.6

3

rnA

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Paremeter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS11A

Condltlona
Vee = 4.5Vto5.5V
RL = 500n
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

DM74ALS11A

Units

Min

Max

Min

Max

2

17

2

13

ns

2

14

2

10

ns
\

2-24

IJ

National
Semiconductor
Corporatton

DM54ALS 12A/DM74ALS 12A Triple 3-lnput
NAND Gates with Open Collector Outputs
General Description

Features

This device contains three independent gates, each of
which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL

process

Pull-Up Resistor Equations
R

Vee (Min) - VOH
MAX = N, (IQH) + N2 (I'H)

R
MIN =
Where:

• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

Vee (Max) - VOL
IOL - Ns (Ill)

N, (IOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (I'H) = total maximum input high current for all
inputs tied to pull-up resistor
NS (Ill'> = total maximum input low current for all
Inputs tied to pull-up resistor

Connection Diagram
Dual-In-Une Package
Vee

f14

C1

V1

13

1

2

41

81

C3

112

83

11

3

4

A2

82

A3

10

19

V3

8

Ie 17

5
C2

Y2

OND
TLiF 16182-1

Order Number DM54ALS12AJ, DM74ALS12AM or DM74ALS12AN
See NS Package Number J14A, M14A or N14A

Function Table
V = ABC
Inputs

Output

A

B

C

V

X
X

X

L

L

X

L

X

H

H

X
H

H
H
H

H - High logic Level
L
X

= Low logic Level
= Either Low or High Logic Level
2-25

L

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and speclficetlons.
Supply Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the df!vice cannot be guarenteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics" .
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for acttial device operation.

Input Voltage
7V
High Level Output Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O·Cto +70·C
Storage Temperature Range

-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS12A

Parameter

DM74ALS12A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

VOH

High Level Output Voltage

5.5

5.5

V

IOL

Low Level Output Current

4

8

mA

TA

Free Air Operating Temperature

70

·C

2

2

-55

125

V

0

-,

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

Min

Typ

Max

Units

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

-1.5

V

IOH

High Level Output Current

Vee = 4.5V, VOH = 5.5V

100

p.A

VOL

Low Level Output
Voltage

Vee = 4.5V

54174ALS
IOL =4mA

0.25

0.4

V

74ALS
IOL = 8mA

0.35

0.5

V

0.1

mA

20

p.A

-0.1

mA

II

Input Current @ Max
Input Voltage

Vee = 5.5V, VIH = 7V

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

IlL

Low Level Input Current

Vee = 5.5V, VIL = O.4V

lee

Supply Current

Vee = 5.5V

Outputs High

0.32

0.6

mA

Outputs Low

1.2

2.2

mA

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol
tpLH

Parameter
Propagation Delay Time
Low to High Level Output

DM54ALS12A

Conditions
Vee = 4.5V to 5.5V
RL = 2 kO
CL = 50pF

Propagation Delay Time
High to Low Level Output
Note 1: See Section 1 for test waveforms and output load.

tpHL

2-26

DM74ALS12A

Units

Min

Max

Min

Max

23

59

23

54

ns

5

26

5

18

ns

_

National

Semiconductor
Corporation

DM54ALS13/DM74ALS13 Dual 4-lnput
NAND Gates with Schmitt Trigger Inputs
General Description
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with Schottky
and Low Power Schottky TTL counterparts
• Improved AC performance over low power Schottky
counterpart

This device contains two independent gates, each of which
performs the logic NAND function. Each input has hysteresis which increases the noise immunity and transforms a
slowly changing input signal to a fast changing, jitter-free
output.

Features
• Switching specification at 50 pF

Connection Diagram
vee

C2

02

114

NC

82

111

12

13

V2

A2

9

10

8

~
~>j
2

AI

4

Jc3

81

5

Cl

01

Is
VI

17
GNO

Order Number DM54ALS13J, DM74ALS13M or DM74ALS13N
See NS Package Number J14A, M14A or N14A

Function Table
v=

ABeD

Inputs

Output
V

A

B

C

X
X
X

X
X

X

L

L

L

L

X

X
X

X
X
X

H
H
H
H

H

H

H

H

L

= High Logic Level
L = Low Logic Level
X = El1her Low or High logic Level
H

2-27

D

TL/F/B772-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for avallabillty and specifications.
Supply Voltage
7V
Input Voltage
7V
Storage Temperature Range
- 65°C to + 150"C

Note: The "Absolute Maximum Ratings"are t/Jose values
beyond which the safety of ,the' device I;!lnno( be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Operating Free Air Temperature Range
DM54ALS
- 55°C to + 125°C
DM74ALS
O"Cto +70°C

Recommended Operating Conditions
Symbol
Vee

Supply Voltage

VT+

Positive-Going Input
Threshold Voltage

VTHYS

DM54ALS13

Parameter

Negative-Going Input
Threshold Voltage
Input Hysteresis

=
Vee =
Vee =
Vee =
Vee =
Vee =
Vee

DM74ALS13

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5

5.5

5.5

4.5

Min to Max

1.4

2

1.4

2

5V

1.55

1.85

1.55

1.85

Min to Max

0.75

1.2

0.75

1.2

5V

0.85

1.1

0.85

1.1

Min to Max

0.5

0.5

5V

0.6

0.6

V
V

V

V

10H

High Level Output Current

-0.4

-0.4

mA

10L

Low Level Output Current

4

8

mA

TA

Operating Free Air Temperature Range

70

~c

-55

125

0

Electrical Characteristics over recommended free air temperature range (unless otherwise noted)
Symbol

Parameter

Vie

Input Clamp Voltage

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

Test Conditions

=
Vee =
Vee =

Vee

Min,11

=

=

4.5V to 5.5V, 10H
Min

Max

Units

-1.5

V
V

Vee- 2

Max

54174ALS
10L = 4mA

0.25

0.4

74ALS
10l = 8mA

0.35

0.5

IT+

Input Current at Positive-Going
Threshold Voltage

Vee

=

5V, VI

=

VT+

IT-

Input Current at Negative-Going
Threshold Voltage

Vee

=

5V, VI

=

VT-

=
=
Vee =
Vee =
Vee =
Vee =

Typ

Min

-18mA

V

= 7V
= 2.7V
Max, VI = 0.4V
Max, Vo = 2.25V

20

p.A

-100

p.A
p.A

II

Input Current at Maximum Input Voltage

Vee

Max, VI

100

IIH

High Level Input Current

Vee

Max, VI

20

p.A

IlL

Low Level Input Current

-100

p.A

10

Output Drive Current

leeH

Supply Current with Outputs High

leel

Supply Current with Outputs Low

-112

mA

Max

-30

4

mA

Max

4

mA

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

tplH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Conditions (Note 1)
Vee = 4.5V to 5.5V
RL = 5000., CL = 50 pF

Nole 1: See Section 1 for test waveforms and output load.

2-28

DM54ALS13

DM74ALS13

Min

Max

Min

Max

2

13

2

12

2

13

2

12

Units

ns

_

National

Semiconductor
CorporaHon

DM54ALS14/DM74ALS14 Hex Inverters
with Schmitt Trigger Inputs
General Description

Features

This device contains six independent gates. each of which
performs the logic INVERT function. Each input has hysteresis which increases the noise immunity and transforms a
slowly changing input signal to a fast changing. jitter-free
output.

• Switching specification at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated. ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with Schottky
and Low Power Schottky TTL counterparts
• Improved AC performance over low power Schottky
counterpart

Connection Diagram
vee

AS

Y.S

AS

A1

Y1

A2

Y2

Y5

A4

Y4

TLlF/8773-1

Order Number DM54ALS14J, DM74ALS14M or DM74ALS14N
see NS Package Number J14A, M14A or N14A

Function Table
Y=A
Input

H

L

A

Output
Y

L
H

H
L

= High Logic Level
= Low Lcglc Level

2-29
---_.-

-

_._-----_.

Absolute Maximum Ratings
NOTE: The "Absolute MBXimum Rstings" SrB those valuss .

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales OffIce/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

beyond which the safety of the devicB cannot be gusrsnt88d. The devicB should not be operstBd st these limits. The
pBrBmBtric valUBS definBd in the "E/ectricsl ChsrsctBfistics"
table SrB.not gusrant88d st the sbsoIuts msximum ratings.
The "R8COfTImBnded Opsrsting Conditions" tabl8 will define
the conditions for sctusl devicB operstion.

Storage Temperature Range
-65°C to + 150"C
Operating Free Air Temperature Range
DM54ALS
- 55°C to + 125°C
DM74ALS
O"Cto +70"C

Recommended Operating Conditions
Symbol
Vee

Supply Voltage

VT+

Positive-Going Input
Threshold Voltage

VT-

HYS

DM54ALS14

Parameter

Negative-Going Input
Threshold Voltage
Input Hysteresis

=
Vee =
Vee =
Vee =
Vee =
Vee =
Vee

DM74ALS14

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5

5.5

5.5

4.5

Min to Max

1.4

2

1.4

2

5V

1.55

1.85

1.55

1.85

Min to Max

0.75

1.2

0.75

1.2

5V

0.85

1.1

0.85

1.1

V
V

V

Minto Max

0.5

0.5

5V

0.6

0.6

V

10H

High Level Output Current

-0.4

-0.4

mA

10L

Low Level Output Current

4

8

mA

TA

Operating Free Air Temperature Range

70

°C

-55

125

0

Electrical Characteristics over recommended free air temperature range (unless otherwise noted)
Symbol

Paremeter

Test Conditions

Vie

Input Clamp Voltage

Vee

VOH

High Level Output Voltage

Vee

VOL

Low Level Output Voltage

Vee

=
=
=

Min,ll

=

4.5V to 5.5V, 10H
Min

0.35

0.5

V

20

p.A

-100

p.A

100

p.A

20

p.A

=

VT+

IT-

Input Current at NegativeGoing Threshold Voltage

Vee

=

5V, VI

=

VT-

II

Input Current at Maximum
Input Voltage

Vee

=

Max, VI

IIH

High Level Input Current

Vcc

=
Vcc =
Vee =
Vee =

Max, VI

ICCH

Supply Current with
Outputs High

leel

Supply Current with
Outputs Low

Vcc

=

7V

= 2.7V
Max, VI = 0.4V
Max, Vo = 2.25V
Max
Max

2-30

V

74ALS
10l = 8mA
5V, VI

Low Level Input Current

V

Vcc- 2

V

=

Output Drive Current

Max

Unlta

0.4

Vcc

=

=

Max
-1.5

0.25

Input Current at PositiveGoing Threshold Voltage

10

Typ

54/74ALS
10L = 4mA

IT+

III

Min

-18 mA

-30

-100

p.A

-112

mA

12

mA

12

mA

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Conditions (Note 1)
Vee = 4.5V to 5.5V
RL = 500n, CL = 50 pF

Note 1: See Section 1 for test waveforms and output load.

---

2·31

DM54ALS14

DM74ALS14
Units

Min

Max

Min

Max

2

13

2

12

ns

2

11

2

10

ns

IJ

NatiOnal
Semiconductor
CorporaHon

DM54ALS15A/DM74ALS15A Triple 3-lnput
AND Gates with Open Collector Outputs .
General Description

Features

This device contains three independent gates, each of
Which performs the logic AND function. The open-collector
outputs require external pull-up resistors for proper logical
operation.

• Switching specifications guaranteed over full temperature and Vee range
• Advanced Oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

Pull-Up Resistor Equations
R

Vee (Min) - VOH
MAX = N1 (IOH) + N2 (lIH)

R
MIN =
Where:

Vee (Max) - VOL
IOL - Ns (lILl

N1 (IOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
Ns (lILl = total maximum input low current for all
inputs tied to pull-up resistor

Connection Diagram
Dual-In-Une Package
vee

C1

114

Y1

13

CS

112

B3

A3

11

10

4

5

19

Y3

8

L

p
1

2

A1

81

3
A2

82

~
\e \7
Y2

C2

GND

TL/F/6183-1
Order Number DM54ALS15AJ, DM74ALS15AM or DM74ALS15AN
See NS Package Number J14A, M14A or N14A

Function Table
Y=ABC
Inputs

B

C

Y

X
X

X

L

L

X

X
X

H

H

L
L
L
H

L
H
H

Output

A

= High logic Level

L = Low logic Level
X = Ei1her Low or High Logic Level

2-32

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "£Iectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operatiOn.

High Level Output Voltage
7V
Operating Free Air Temperature Range
-55·C to + 125·C
DM54ALS
DM74ALS
O·Cto +70·C
- 65·C to + 150·C
Storage Temperature Range

Recommended Operating Conditions
Symbol

DM54ALS15A

Parameter

DM74ALS15A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

VOH

High Level Output Voltage

5.5

5.5

V

IOL

Low Level Output Current

4

8

mA

70

·C

TA

2

Free Air Operating Temperature

2

-55

125

V
V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Min

Conditions

Typ

Max

Units

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

-1.5

V

IOH

High Level Output Current

Vee = 4.5\!, VOH = 5.5V

100

/LA

VOL

Low Level Output
Voltage

Vee = 4.5V

II

Input Current @ Max
Input Voltage

54/74ALS
IOL =4mA

0.25

0.4

V

74ALS
IOL = 8mA

0.35

0.5

V

0.1

mA

Vee = 5.5V, VIH = 7V

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

/LA

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.1

mA

lee

Supply Current

Vee = 5.5V

Outputs High

1.0

1.8

mA

Outputs Low

1.66

3

mA

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS15A

Conditions
Vee = 4.5V to 5.5V
RL = 2kn
CL=50pF

Note 1: See Section 1 for test wavefonn.. and output load.

2-33

DM74ALS15A

Units

Min

Max

Min

Max

20

59

20

45

ns

6

25

6

20

ns

fI

rJ

Naoonal
Semiconductor
CorporaHon

DM54ALS20A/DM74ALS20A
Dual4-lnput NAND Gates
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

General Description
This device contains two independent gates, each of which
performs the logic NAND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package
D2

C2

13

NC

12

111

2

A1

B2
10

19

Y2
B

15 1& 17

4
C1

B1

A2

D1

Y1

GIlD
TLlF/6184-1

Order Number DM54ALS20AJ, DM74ALS20AM or DM74ALS20AN
See NS Package Number J14A, M14A or N14A

Function Table
y = ABeD
Inputs

Output

A

B

C

D

Y

X
X
X

X
X

X

L

L

L

L

X
H

X
X
H

X
X
X
H

H
H
H
H

H

= High Logic Lavel
L = Low Logic Level
X = Ei1her Low or High Logic Level

H

2-34

L

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications,
Supply Voltage
7V
Input Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Operating Free Air Temperature Range
DM54ALS
- 55'C to + 125'C
DM74ALS
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C

Recommended Operating Conditions
Symbol
Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

DM74ALS20A

DM54ALS20A

Parameter

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

0.7

0.8

V

-0.4

-0.4

mA

8

mA

70

'C

2

10L

Low Level Output Current

TA

Free Air Operating Temperature

Units

Min

2

V

4
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. Aillypical values are measured at Vee

=

Symbol

Typ

Parameter

Conditions

=

=

VIK

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

10H = -O.4mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee

=

4.5V, II

4.5V

Min

-18 mA

IlL
10

Output Drive Current

lee

Supply Current

5.5V, VIL
5.5V
5.5V

V

74ALS
10L = 8mA

0.35

0.5

V

0.1

mA

= 2.7V
= O.4V
Vo = 2.25V

Vee

Low Level Input Current

V

V

5.5V, VIH

High Level Input Current

-1.5

0.4

=
Vee =
Vee =
Vee =

IIH

Units

0.25

=

Vee

25'C.

Max

54174ALS
10L = 4mA

5.5V, VIH

Input Current @ Max
Input Voltage

=

Vee- 2

=

II

5V, TA

7V

-30

20

".A

-0.1

mA

-112

mA

Outputs High

0.22

0.4

mA

Outputs Low

0.81

1.5

mA

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS20A

Conditions
Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

2-35

DM74ALS20A

Units

Min

Max

Min

Max

1

18

3

11

ns

1

15

3

10

ns

•

_

National
Semiconductor
Corporation

DM54ALS21A/DM74ALS21A
Dual 4-lnput AND Gates
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

General Description
This device contains two independent gates, each of which
performs the logic AND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Une Package
VCC

02

114

A1

C2
12

2

13
NC

B1

B2

NC

13

111

10

4

5
01

C1

A2

Ie

18

Y1

Y2
8

1

7
GNO
TLlF/6185-1

Order Number DM54ALS21AJ, DM74ALS21AM or DM74ALS21AN
See NS Package Number J14A, M14A or N14A

Function Table
Y = ABCD
(

Inputs

H

Output

A

B

C

D

Y

X
X
X

X
X

X

L

L

L

L
H

X

X
X

X
X
X

H

H

H

L
L
L
L
H

= High logiC Level

L = Lew logic Level
X

= Either Low or High Logic Level

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the Nstlonal Semiconductor sales OffIce/
Distributors for availability and specifications.
Supply Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarenteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Oparating Conditions" table will define
the conditions for actual device operation.

Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-55·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS21A

Parameter

Va:;

Supply Voltage

VIH

High Level Input Voltage

DM74ALS21A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

V
V

VIL

Low Level Input Voltage

0.8

0.8

V

10H

High Level Output Current

-0.4

-0.4

mA

10L

Low Level Output Current

4

8

mA

TA

Free Air Operating Temperature

70

·C

-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA =. 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Va:; = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

IOH = -0.4mA
Va:; = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Va:; = 4.5V

Min

Typ

Max

Units

-1.5

V

Va:; - 2

V

54/74ALS
10L = 4mA

0.25

0.4

V

74ALS
IOL = 8mA

0.35

0.5

V

0.1

mA

II

InputCurrent,@ Max
Input Voltage

Va:; = 5.5V, VIH = 7V

IIH

High Level Input Current

Va:; = 5.5V, VIH = 2.7V

20

,..A

IlL

Low Level Input Current

Va:; = 5.5V, VIL = 0.4V

-0.1

mA

10

Output Drive Current

Vee = 5.5V

Vo = 2.25V

-112

mA

Ia:;

Supply Current

Va:; = 5.5V

Outputs High

0.85

1.4

mA

Outputs Low

1.4

2.3

mA

-

-30

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

DM54ALS21A

Conditions

tpLH

Propagation Delay TIme
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Va:; = 4.5V to 5.5V
RL = 500.0.
CL = 50pF

Max

Min

Max

4

18

4

15

ns

2

12

2

10

ns

2-37
_.

-

Units

Min

Note 1: See Section 1 for test waveforms and output load.

-----

DM74ALS21A

----

fII

ID

~
~

II

~
::E
Q

I
2!i

National
Semiconductor
Corporation

DM54ALS22B/DM74ALS22B Dual 4-lnput NAND Gates
with o.pen Collector Outputs
.
General Description

Features

This device contains two independent gates, each of which
performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation.

• Switching specifications at 50 pF.
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL

process

Pull-Up Resistor Equations

• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

R

Vee (Min) - VOH
MAX = N1 (IOH) + N2 (IIH)

R
MIN =
Where:

Vee (Max) - VOL
IOL - N3 (IlL>

N1 (IOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (lIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (IlL> = total maximum input low current for all
inputs tied to pull-up resistor

Connection Diagram
Dual-In-Llne Package
V!=C

D2

114

C2

13

NC

12

B2

111

A2

Y2

I'

10

8

h
2

13

.1

A1

6

4

NC

C1

D1

18
Y1

17
Gil)
TlIF/6188-1

Order Number DM54ALS22BJ, DM74ALS22BM or DM74ALS22BN
Se. NS Package Number J14A, M14A or N14A

.,
).~

,

Function Table
y

= ABeD

Inputa

Output
D

Y

X

L

L

X
X

X
X
X

H
H
H
H

H

H

L

A

B

C

X
X
X

X
X
L

L

X

H

H

H = High logic Level
L = Low Logic Level
X = Either Low or High Logic Level

2·38

Absolute Maximum Ratings
If Mllltary/Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

High Level Output Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS22B

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VOH

High Level Output Voltage

DM74ALS22B

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

IOL

Low Level Output Current

TA

Free Air Operating Temperature

Units

Min

2

V

0.7

0.8

V

5.5

5.5

V

8

rnA

70

·c

4
-55

V

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V. TA = 25·C.
Symbol

Parameter

Conditions

Min

Typ

Max

Units

Vee = 4.5V.11 = -18 mA

-1.5

V

IOH

High Level Output Current

Vee = 4.5V. VOH = 5.5V

100

",A

VOL

Low Level Output
Voltage

Vee = 4.5V

VIK

Input Clamp Voltage

54/74ALS
IOL =4mA

0.25

0.4

V

74ALS
IOL=8mA

0.35

0.5

V

0.1

rnA

20

",A

II

Input Current @ Max
Input Voltage

Vee = 5.5V. VIH = 7V

IIH

High Level Input Current

Vee = 5.5V. VIH = 2.7V

IlL

Low Level Input Current

Vee = 5.5V. VIL = 0.4V

lee

Supply Current

Vee = 5.5V

-0.1

mA

Outputs High

0.22

0.4

mA

Outputs Low

0.80

1.5

mA

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol
tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Note 1: See Section 1 for _

DM54ALS22B

Conditions

Parameter

Vee = 4.5V to 5.5V
RL = 2kO
CL = 50pF

wavefonns and outpulload.

2·39

DM74ALS22B

Units

Min

Max

Min

Max

23

65

23

45

ns

4

32

4

18

ns

fII

_

National

Semiconductor

Corporation

DM54ALS27/DM74ALS27
Triple 3-lnput NOR Gates
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TIL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

General Description
This device contains three independent gates, each of
which performs the logic NOR function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package
Vcc

C1

Y1

C3

B3

A3

C2

Y2

va

11

3
A1

81

4

A2

82

TUF/6187-1

Order Number DM54ALS27J, DM74ALS27M or DM74ALS27N
See NS Package Number J14A, M14A or N14A

Function Table
Y=A+B+C
Output

Inputs

H

A

B

C

Y

H
X
X
L

X·
H
X

X
X

L
L
L
H

H
L

L

= High Logic Level

L = Low Logic Level
X

= Either Low or High Logic Level

2-40

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Seles Office/
Distributors for availability and specifications.
Supply Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Cheracteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O·Cto +70"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS27

Parameter

Vec

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

DM74ALS27

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

10L

Low Level Output Current

TA

Free Air Operating Temperature

Unlta

Min

V
V

2
0.7

0.8

V

-0.4

-0.4

mA

4

8

mA

125

70

·c

-55

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Min

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VaH

High Level Output
Voltage

10H = -0.4mA
Vee = 4.5Vto5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V

II

Input Current @ Max
-Input Voltage

Typ

Max

Units

-1.5

V
V

Vee - 2

54174ALS
10L = 4mA

0.25

0.4

V

74ALS
IOL=8mA

0.35

0.5

V

0.1

mA

Vee = 5.5V, VIH = 7V

.- .. ~:.-

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

p.A

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.1

mA

10

Output Drive Current

Vee = 5.5V

Va = 2.25V

-112

mA

Icc

Supply Current

Vee = 5.5V

Outputs High

0.97

1.8

mA

Outputs Low

2

4

-30

mA

\

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

DM54ALS27

Conditions

Min
tpLH

Propagation Delay TimeLow to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to5.5V
RL = 500n
CL = 50pF

--

Note 1: See Secllon 1 for test waveforms and output load.

2·41

DM74ALS27

Units

Max

Min

Max

-21

26

4

15

ns

1

11

3

9

ns

Ij Corporation
Semiconductor
National

DM54ALS28A/DM74ALS28A
Quadruple 2-lnput NOR Buffers
• Advanced, oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with LS TTL
counterpart
• Improved AC performance over LS28
• Improved line receiving characteristics

General Description
This device contains four independent gates, each of which
performs the logic NOR function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package
14

V2

81

Al

V3
10

B3

A3

A2

B2

GNO
TL/F/6188-1

Order Number DM54ALS28AJ,
DM74ALS28AM or DM74ALS28AN
See NS Package Number J14A, M14A or N 14A

Function Table
Y=A+B
Inputs

H
L

Output

A

B

Y

L
L
H
H

L
H
L
H

H
L
L
L

= High Logic Level
= Low Logic Level

2-42

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
perametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Input Voltage

7V
Operating Free Air Temperature Range
DM54ALS28A
- 55·C to + 125·C
DM74ALS28A
O"Cto +70"C
Storage Temperature Range

-65·Cto

+ 150"C

Recommended Operating Conditions
Symbol

DM54ALS28A

Parameter

DM74ALS28A

Unlta

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-1

-2.6

mA

24

mA

70

·C

2

10L

Low Level Output Current

TA

Free Air Operating Temperature

2

V

12
-55

125

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vcc

Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

Conditions

= 4.5V, II =
Vee = 4.5V
VIL = VILMax

Low Level Output
Voltage

=

25·C.

Max

Units

-1.5

V

2.4

3.2

V

74ALS
10H = -2.6mA

2.4

3.3

V
V

Vee -2

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

II

Input Current at Max
Input Voltage

Vee

=

5.5V, VIH

=

IIH

High Level Input Current

Vee

III

Vee

= 2.7V
= O.4V

10

Output Drive Current

Vee

ICCH

Supply Current with
Outputs High

Vee

=
=
=
=

5.5V, VIH

Low Level Input Current

5.5V, VI

=

OV

leel

Supply Current with
Outputs Low

Vcc

=

5.5V, VI

=

4.5V

7V

5.5V

=

54ALS
10H = -1 mA

54/74ALS

-400 p.A

Vee = 4.5V
VIH = 2V

5.5V, Vil

5V, T A
Typ

-18 mA

Vee

10H
VOL

=

Min

Vo

=

20

p.A

-0.1

mA

-112

mA

1.7

2.8

mA

4.8

9

mA

-30

2.25V

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tplH

Propagation Delay Time
Low to High Level Output

tpHl

Propagation Delay Time
High to Low Level Output

DM54ALS28A

Conditions
Vee = 4.5Vto 5.5V
Rl = 500n
Cl = 50pF

Note 1: See Section 1 for test waveforms and output load.

2-43

DM74ALS28A

Units

Min

Max

Min

Max

1

6

2

8

ns

1

10

2

7

ns

PI

_

National
Semiconductor
CorporaHon

DM54ALS30A/DM74ALS30A
a-Input NAND Gate
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TIL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

General Description
This device contains a single gate, which performs the logic
NAND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Une Package
H

G

12

NC

11

Ne

110

19

y
8

Tl/F/6169-1

Order Number DM54ALS30AJ, DM74ALS30AM lor DM74ALS30AN
See NS Package Number J14A, M14A or N14A

Function Table
Y =ABCDEFGH
Inputs
Athru H

Output
Y

All Inputs H
One or More
Input L
H

L
H

= High Logic Level

L = Low logic Level

2-44

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Cheracteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70·C
Storage Temperature Range
-65·C to + 150"C

Recommended Operating Conditions
Symbol

DM54ALS30A

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

DM74ALS30A

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

10L

Low Level Output Current

TA

Free Air Operating Temperature

Units

Min

0.7

0.8

V

-0.4

-0.4

mA

8

mA

70

·c

4
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

=

Symbol

Typ

Parameter

Conditions

=

=

VIK

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

10H = -0.4mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee

=

4.5V,11

4.5V

Min

=

25·C.

Max

Units

-1.5

V
V

Vee- 2

54174ALS
10L = 4mA

0.25

0.4

V

74ALS
10L = 8mA

0.35

0.5

V

0.1

mA

Input Current at Max
Input Voltage

Vee

=

5.5V, VIH

=

IIH

High Level Input Current

Vee

IlL

Vee

5.5V, VIL

10

Output Drive Current

= 2.7V
= O.4V
Vo = 2.25V

Icc

Supply Current

=
=
Vee =
Vee =

5.5V, VIH

Low Level Input Current

5.5V

5V, T A

-18 mA

II

5.5V

V
V

2

7V

-30

20

/LA

-0.1

mA

-112

mA

Outputs High

0.22

0.36

mA

Outputs Low

0.54

0.90

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol
tpLH

Parameter
Propagation Delay Time
Low to High Level Output

DM54ALS30A

Conditions
Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

Propagation Delay Time
High to Low Level Output
Note 1: See Section 1 for test waveforms and output load.

tpHL

2-45

DM74ALS30A

Units

Min

Max

Min

Max

3

15

3

10

ns

3

15

3

12

ns

~ Semiconductor
National

CorporaHon

DM54ALS32/DM74ALS32
Quad 2-lnput OR Gates
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

General Description
This device contains four independent gates, each of which
performs the logic OR function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Line Package
vee

B4

A4

A1

B1

Y1

Y4

A2

B3

B2

Y2

GND
TL/F/6190-1

Order Number DM54ALS32J, DM74ALS32M or DM74ALS32N
See NS Package Number J14A, M14A or N14A

Function Table
Y=A+B
Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

L
H
H
H

H - High Logic Level
L - Low Logic Level

2-46

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
DIstributors for availability and specifications.
Supply Voltage
7V

Note: The "Absolute Maximum RaUngs" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum raUngs.
The "Recommended Operating Conditions" table will define
the conditions for actual device operaUon.

Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O·Cto +700C
-65·C to + 150·C
Storage Temperature Range

Recommended Operating Conditions
Symbol

DM54ALS32

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H
10L
TA

Free Air Operating Temperature

DM74ALS32

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2
0.7

0.8

V

High Level Output Current

-0.4

-0.4

mA

Low Level Output Current

4

8

mA

70

·c

-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V.11 = -18 mA

VOH

High Level Output
Voltage

10H = -0.4mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V

Min

Typ

Max

Units

-1.5

V
V

Vee - 2

54174ALS
10L = 4mA

0.25

0.4

V

74ALS
10L = 8mA

0.35

0.5

V

0.1

mA

II

Input Current @ Max.
Input Voltage

Vee = 5.5V. VIH = 7V

IIH

High Level Input Current

Vee = 5.5V. VIH = 2.7V

20

/J-A

IlL

Low Level Input Current

Vee = 5.5V. VIL = O.4V

-0.1

mA

10

Output Drive Current

Vee = 5.5V

Vo = 2.25V

-112

mA

lee

Supply Current

Vee = 5.5V

Outputs High

1.9

4

mA

Outputs Low

2.6

4.9

mA

-30

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Conditions
Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

Nota 1: See Section 1 for test waveforms and output load.

2-47

DM54ALS32

DM74ALS32

Units

Min

Max

Min

Max

3

18

3

14

ns

3

16

3

12

ns

IJ

NatiOnal
Semiconductor
Corporation

DM54ALS33A/DM74ALS33A Quadruple 2-lnput
NOR Buffers with Open-Collector Outputs
General Description

Features

This device contains four independent gates. each of which
performs the logic NOR function. The open-collector outputs require external pull-up resistors for proper logical operation.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated. ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with LS TIL
counterpart
• Improved AC performance over LS33
• Improved line receiving characteristics

Pull-Up Resistor Equations
R
MAX
R
MIN =
Where:

Vee (Min) - VOH
+ N2 (IIH)

= N1 (IOH)

Vee (Max) - VOL
IOL - N3 (11Ll

N1 (lOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (lIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (lILl = total maximum input low current for all
inputs tied to pull-up resistor

Connection Diagram
Dual-In-Line Package
14

lY

lB

lA

2Y

2A

28

SNU

TUFf6191-1

Order Number DM54ALS33AJ, DM74ALS33AM or DM74ALS33AN
See NS Package Number J14A, M14A or N14A

Function Table
Y=A+B
Inputs

H

Output

A

B

Y

L
L

L

H

H
H

L

H
H
H

H

L

= High logic Level

L = Low Logic Level

2-48

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
perametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
High Level Output Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55DC to + 125DC
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65DCto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS33A

Parameter

Vee

Supply Voltage

V,H

High Level Input Voltage

DM74ALS33A

Unlta

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2

V,l

Low Level Input Voltage

0.7

0.8

V

VOH

High Level Output Voltage

5.5

5.5

V

24

rnA

70

DC

IOl

Low Level Output Current

TA

Free Air Operating Temperature

12
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

=

Symbol

Typ

Parameter

Conditions

Min

= 4.5V, I, = -18 mA
= 4.5V, VOH = 5.5V
54174ALS
Vee = 4.5V,
V,H = 2V
IOl = 12mA

5V, TA

=

25DC.

Max

Units

V,K

Input Clamp Voltage

Vee

-1.5

V

IOH

High Level Output Current

Vee

100

IIA

VOL

Low Level Output
Voltage

0.25

0.4

V

0.35

0.5

V

0.1

mA

74ALS
IOl = 24mA
I,

Input Current @ Max.
Input Voltage

Vee

=

5.5V, V,H
5.5V, V,H

/J-A

-0.1

mA

5.5V, V,

= 2.7V
= 0.4V
= OV

20

5.5V, V,l

1.7

2.8

mA

5.5V, V,

=

4.8

9

rnA

I'H

High Level Input Current

Vee

I,l

Low Level Input Current

Vee

leeH

Supply Current with
Outputs High

Vee

=
=
=

leel

Supply Current with
Outputs Low

Vee

=

=

7V

4.5V

,

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tplH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

_

DM54ALS33A

Conditions
Vee = 4.5V to 5.5V,
Rl = 680.0.,
CL = 50pF

1: See Section 1 for test waveforms and output load.

2·49

DM74ALS33A

Units

Min

Max

Min

Max

10

59

10

33

ns

2

18

2

12

ns

fI

_

National
Semiconductor
Corporation

DM54ALS37 A/DM7 4ALS37A
Quadruple 2-lnput NAND Buffers
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with LS TTL
counterpart
• Improved AC performance over LS37
• Improved line receiving characteristics

General Description
This device contains four independent gates, each of which
performs the logic NAND function.

Features
• Switching specifications at 50 pF
• Switching speCifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package
Vee

84

A4

Y4

83

A3

A1

81

Y1

A2

82

Y2

GND
TLlF/6192-1

Order Number DM54ALS37AJ, DM74ALS37AM or DM74ALS37AN
See NS Package Number J14A, M14A or N14A

Function Table
y= AB
Inputs

Output

A

B

Y

L
L

L

H

H
H

L

H
H
H

H

L

H

~

High Logic Level

L

~

Low logic Level

2-50

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Operating Free Air Temperature Range
DM54ALS
- 55"C to + 125DC
DM74ALS
O"Cto +70"C
Storage Temperature Range
- 65DC to + 15O"C

Recommended Operating Conditions
Symbol

DM54ALS37A

Parameter

DM74ALS37A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-1

-2.6

mA

10L

Low Level Output Current

12

24

mA

TA

Free Air Operating Temperature

70

DC

2

V

2

-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

Conditions

= 4.5V,II =
Vee = 4.5V
VIL = Max

VOL

=

-400 p,A

74ALS
10H = -2.6mA

2.4

3.3

V

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

5.5V, VIH

=

5.5V, VIH

= 2.7V
= 0.4V

5.5V, VI

=

OV

5.5V, VI

=

4.5V

Vee

10

Output Drive Current

Vee

leeH

Supply Current with
Outputs High

Vee

=
=
=
=

leeL

Supply Current with
Outputs Low

Vee

=

5.5V, VIL

V

Vee- 2

54174ALS
10L = 12mA

=

Vee

7V

5.5V

V
V

Vee

Low Level Input Current

Units

-1.5
3.2

Input Current @ Max.
Input Voltage
High Level Input Current

25DC.
Max

2.4

II
IIH

=

54ALS
10H = -1 mA

54174ALS

Vee = 4.5V
VIH = 2V

IlL

5V, TA
Typ

-18 rnA

Vee

10H
Low Level Output
Voltage

=

Min

Vo

=

20

p.A

-0.1

mA

-112

mA

0.86

1.6

mA

4.0

7.8

mA

-30

2.25V

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol
tpLH

Parameter
Propagation Delay Time
Low to High Level Output

DM54ALS37A

Conditions
Vee = 4.5Vto 5.5V
RL = 5000
CL = 50pF

Propagation Delay Time
High to Low Level Output
Note 1: See Section 1 fOr taat waveforms and output loed.

tpHL

2-51

DM74ALS37A

Units

Min

Max

Min

Max

2

17

2

8

ns

2

10

2

7

ns

fI

~. .
~

II

.....

~

g
~

:&
Q

National
Semiconductor
Corporation

DM54ALS38A/DM74ALS38A Quadruple 2-lnput
NAND Buffers with Open-Collector Outputs
General Description

Features

This device contains four independent gates. each of which
performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical 0peration.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxlde-isolated. ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with LS TTL
counterpart
• Improved AC performance over LS38
• Improved line receiving characteristics

Pull-Up Resistor Equations
R
MAX

Vee (Min) - VOH

= N1 (lOH) + N2 (lIH)

R
Vee (Max) - VOL
MIN = IOL - N3 (Ill)
Where:

N1 (IOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (IlL,) = total maximum input low current for all
inputs tied to pull-up resistor

Connection Diagram
Dual-In-Llne Package

A1

B4

A4

Y4

B3

81

Y1

A2

82

Y2
TUF/6193-1

Order Number DM54ALS38AJ, DM74ALS38AM or DM74ALS38AN
See NS Package Number J14A, M14A or N14A

Function Table
y=D
Output

Inputs

H

A

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

= High Logic Level

L - Low logic Level

2-52

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales OffIce/
DIstributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

High Level Output Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS38A

Parameter

DM74ALS38A

Unlta

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

V

Vcc

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.7

0.8

VOH

High Level Output Voltage

5.5

5.5

V

IOl

Low Level Output Current

12

24

mA

TA

Free Air Operating Temperature

70

·C

2

2

-55

125

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vcc

=

Symbol

Typ

Parameter

VIK

Input Clamp Voltage

IOH

High Level Output Current

VOL

Low Level Output
Voltage

Conditions

=
Vee =
Vee =
Vcc

4.5V.11

=

4.5V. VOH

5V. TA

=

25·C.

Max

Units

-18 rnA

-1.5

V

=

100

/-LA

4.5V
VIH = 2V

5.5V

54174ALS
IOl = 12 rnA

0.25

0.4

V

74ALS
IOl = 24 rnA

0.35

0.5

V

0.1

rnA

II

Input Current at Max
Input Voltage

Vcc

=

5.5V. VIH
5.5V. VIH

,.,.A

-0.1

rnA

5.5V. VI

= 2.7V
= 0.4V
= OV

20

5.5V. Vil

0.86

1.6

rnA

5.5V. VI

=

4.0

7.8

rnA

IIH

High Level Input Current

Vcc

III

Low Level Input Current

Vcc

ICCH

Supply Current with
Outputs High

Vcc

=
=
=

ICCl

Supply Current with
Outputs Low

Vee

=

=

Min

7V

4.5V

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHl

Propagation Delay Time
High to Low Level Output

DM54ALS38A

Conditions
Vcc = 4.5Vto 5.5V
Rl = 6800
Cl = 50pF

Note 1: See Section 1 lor test waveforms and output load.

2-53

DM74ALS38A

Units

Min

Max

Min

Max

10

59

10

33

ns

2

18

2

12

ns

_

National

Semiconductor

Corporation

DM54ALS40A/DM74ALS40A
Dual4-lnput NAND Buffers
• Advanced oxide-isolated. ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with LS TTL
counterpart
• Improved AC performance over LS40
• Improved line receiving characteristics

General Description
This device contains two independent gates. each of which
performs the logic NAND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package

vee

T~4

02

2
A1

81

Me

C2

13

12

B2

10

111

13

41&

Me

C1

01

A2

III

Ie
Y1

Y2

8

17
GNO

TUF/S194-1

Order Number DM54ALS40AJ, DM74ALS40AM or DM74ALS40AN
See NS Package Number J14A, M14A or N14A

Function Table
y = ABCD
Inputs

Output

A

B

C

D

Y

X
X
X

X
X

X

L

L

L

L

X

X
X

X
X
X

H
H
H
H

H

H

H

H

L

= High Logic Level
L = Low logic Level
X = EHher Low or High Logic Level

H

2-54

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those. values
beyond which the safety of the device cannot be guarenteed. The device should not be operated at these limits. The
perametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sal.. Office/
DIstributors for availability and specifications.

Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DMS4ALS
-SS'C to + 12S'C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-6S'Cto +15O"C

Recommended Operating Conditions
Symbol

DM54ALS40A

Parameter

DM74ALS40A

Unlta

Min

Nom

Max

Min

Nom

Max

4.S

S

S.S

4.S

S

S.S

V

0.6

V

Vcc

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

10H

High Level Output Current

-1

-2.6

mA

10L

Low Level Output Current

12

. 24

rnA

TA

Free Air Operating Temperature

70

'C

2

2

-SS

12S

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vcc
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

Conditions

= 4.SV, II = -18 mA
S4ALS
Vee = 4.SV
10H = -1 mA
VIL = VILMax

II

Input Current @ Max.
Input Voltage

Typ

Vcc

IOH
Low Level Output
Voltage

= SV, TA = 2S·C.

Min

74ALS
10H = -2.6mA
VOL

V

= -400!IA

S4174ALS

Vcc = 4.SV
VIH = 2V

Vee

Max

Unite

-1.S

V

2.4

3.2

V

2.4

3.3

V
V

Vcc - 2

S4/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

O.S

V

0.1

mA

= S.SV, VIH = 7V

= S.SV, VIH = 2.7V
= S.SV, VIL = O.4V
Vo = 2.2SV
Vcc = S.SV
Vcc = S.SV, VI = OV

IIH

High Level Input Current

Vee

20

p.A

IlL

Low Level Input Current

Vcc

-0.1

mA

10

Output Drive Current

-112

mA

ICCH

Supply Current with
Outputs High

0.43

0.8

mA

ICCL

Supply Current with
Outputs Low

2.4

3.9

mA

Vcc

-30

= S.SV, VI = 4.SV

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

tpLH

Propagation Delay TIme
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS40A

Conditions

Vcc = 4.SV to S.SV
RL = soon
CL = SOpF

Note 1: See Section 1 for test waveforms and output load.

2·S5

DM74ALS40A

Unlta

Min

Max

Min

Max

2

10

2

8

ns

2

10

2

7

ns

_

National
Semiconductor
Corporation

DM54ALS74A/DM74ALS74A Dual D PositiveEdge-Triggered Flip-Flops with Preset and Clear
General Description

Features

The 'ALS74A contains two independent positive edge-triggered flip-flops. Each flip-flop has individual D, clock, clear
and preset inputs, and also complementary Q and 0 outputs.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with Schottky
and LS TTL counterpart
• Improved AC performance over LS74 at approximately
half the power

Information at input D is transferred to the Q output on the
positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly
related to the transition time of the positive going pulse.
When the clock input is at either the high or low level, the D
input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.

Connection Diagram
Dual-In-llne Package
Vee

CLR2

CLR 1

D1

D2

CLK2

PR2

02

02

CLK 1 PR 1

01

01

GND

7
TUF/6109-1

Order Number DM54ALS74AJ, DM74ALS74AM or DM74ALS74AN
See NS Package Number J14A, M14A or N14A

Function Table
Inputs

Outputs

PR

ClR

ClK

D

Q

L

H

L

L

L

L
L

H
HO

H
H
H

H
H
H

X
X
X
H

H

H

X
X
X

t
t

L

X

L

HO
H
L
Qo

Q

L

H

00

L = Low State, H = High State, X = Don't Care

t

= Positive Edge Transition

00 = Previous Condition of Q
• = This condition is nonstable; H will not persist when

preset and clear
Inputs return to thoir Inactive (high) level. The output levels In this condition
are not guaranteed to meet the VOH specification.

2-56

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
- 65"C to + 150·C

Recommended Operating Conditions
Symbol

DM54ALS74A

Parameter

Vee

Supply Voltage

V,H

High Level Input Voltage

V,l

Low Level Input Voltage

DM74ALS74A

Units

Min

Nom

Max

Min

Nom"

Max

4.5

5

5.5

4.5

5

5.5

V

0.7

0.8

V
rnA

2

2

V

10H

High Level Output Current

-0.4

-0.4

10l

Low Level Output Current

4

8

rnA

fClK

Clock Frequency

34

MHz

tw(ClK)

Width of Clock Pulse

tw

Pulse Width
Preset & Clear

tau

Data Setup Time

0

30

0

High

17.5

14.5

ns

Low

17.5

14.5

ns

15

14.5

ns

Data

16t

15t

PREorCLR
Inactive

10t

10t

Low

lti

Data Hold Time

2t

TA

Free Air Operating Temperature

-55

ns
ns

ot
125

0

70

·C

The (t) arrow indicates the positive edge of the Clock is used for reference.

Electrical Characteristics
over recommended operating free air temperature range. Ail typical values are measured at Vce
Symbol

Parameter

V,K

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Conditions

Min

= 4.5V,I, = -18 rnA
10H = -400,..A
Vee = 4.5Vto 5.5V
54/74ALS
Vee = 4.5V
V,H = 2V
10l = 4mA

= 5V, TA = 25·C.
Typ

Vee

Max

Units

-1.5

V
V

Vcc- 2

74ALS
10l = 8mA

0.25

0.4

V

0.35

0.5

V

Input Current @
Max Input Voltage

Vec = 5.5V,
V,H = 7V

Clock, D

0.1

Preset, Clear

0.2

High Level
Input Current

Vee = 5.5V,
V,H = 2.7V

Clock, D

20

Preset, Clear

40

Low Level
Input Current

Vee = 5.5V,
V,l = O.4V

Clock, D

-0.2

Preset, Clear

-0.4

10

Output Drive Current

Vee

lee

Supply Current

Vee

I,

I'H
I,l

= 5.5V, Vo = 2.25V
= 5.5V (Note 1)

Note 1: Icc I. measured with D, ClK and PRESET grounded, than with D, ClK and CLEAR grounded.

2-57

-30
2.4

rnA

,..A

rnA

-112

rnA

4

rnA

Switching Characteristics
over recommended operating free air temperature range (Note 1).

Parameter

Conditions

From

DM54ALS74A

To

Min
fMAX
tpLH

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

DM74ALS74A

Max

Min

30
Preset
or Clear

tpHL
tpLH

OorO

Clock

OorO

tPHL

34
18

3

13

5

17

5

15

ns

5

23

5

16

ns

5

20

5

18

ns

Logic Diagram

CLEAR

1

~
I

UK

0

~ I

E

2-58

I

MHz

3

Note 1: See Section 1 for test waveforms and output load.

PIOET

Units

Max

Q

Q

TLlF/6109-2

ns

_

National

PRELIMINARY

Semiconductor
Corporation

DM54ALS86/DM74ALS86
Quad 2-lnput Exclusive-OR Gates
• Advanced oxide-isolated. ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

General Description
This device contains four independent gates. each of which
performs the logic exclusive-OR function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package
vee

84

A4

Y4

81

Y1

A2

A3

Y2

82

Y3

TUF/6195-1

Order Number DM54ALS86J, DM74ALS86M or DM74ALS86N
See NS Package Number J14A, M14A or N14A

Function Table
Y=AeB=AB+AB
Inputs

Output

Y

A

B

L
L

L

L

H

H
H

L

H
H

H

L

H - High Logic Level
L - Low Logic Level

This document contains Information on a product under development. NSC reserves the right to change or discontinue this product without notice.

2-59

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS86

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

DM74ALS86

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

0.7

0.8

V

2

2

V

10H

High Level Output Current

-0.4

-0.4

mA

10L

Low Level Output Current

4

8

mA

TA

Free Air Operating Temperature

70

·C

-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VOH

High Level Output
Voltage

10H = -O.4mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V

Typ

Min

Max

Unita

-1.5

V

Vee- 2

V

54174ALS
10L = 4mA

0.25

0.4

V

74ALS
IOL=8mA

0.35

0.5

V

0.1

mA

II

Input Current @ Max.
Input Voltage

Vee = 5.5V, VIH = 7V

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

/LA

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.1

mA

10

Output Drive Current

Vee = 5.5V

-112

mA

lee

Supply Current

Vee = 5.5V, All Inputs at 4.5V

5.9

mA

-30

Vo = 2.25V

3.9

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

(Note 2)

AorBtoY
Other Input Low

AorBtoY
Other Input High

Propagation Delay Time
High to Low Level Output
Nota 1: See Section 1 for test waveform. and output load.

tpHL

Nota 2: Vee

= 4.5V to 5.5V, RL =

5000, CL

=

50 pF.

2·60

DM54ALSS.6

DM74ALS86

Unlta

Min

Max

Min

Max

3

22

3

17

ns

2

14

2

12

ns

3

22

3

17

ns

2

12

2

10

ns

_

National
Semiconductor
Corporation

DM54ALS109A/DM74ALS109A Dual J-K PositiveEdge-Triggered Flip-Flops with Preset and Clear
General Description

Features

The DM54ALS109A is a dual edge-triggered flip-flop. Each
flip-flop has individual J, K. clock, clear and preset inputs,
and also complementary Q and 0 outputs.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and LS TTL counterpart
• Improved AC performance over LS109 at approximately
half the power

Information at input J or K is transferred to the Q output on
the positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse.
When the clock input is at either the high or low level, the J,
K input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
The J-K design allows operation as a D flip-flop by tying the
J and K inputs together.

Connection Diagram
Dual-In-Line Package
vcc
116

ClR 2
115

J2

K2

14

12

L

I

PR
y

a
O~

'--K
ClR
y

an

I
2
ClR 1

.13
Kl

Jl

9

PR

~ClK

_ ClR _
r--K
01->ClK

02

10

111

!

r----;:~:::;_I11jJ

J

Q2

ClK 2 PR2

113

14
ClK 1

6

15
PR 1

01

7
01

.18
GNO
TL/F/6196-1

Order Number DM54ALS109AJ, DM74ALS109AM or DM74ALS109AN
See NS Package Number J16A, M16A or N16A

Function Table
PR
L
H
L
H
H
H
H
H

CLR

H
L
L
H
H
H
H
H

L ~ low State, H

t

Outputs

Inputs
CK

X
X
X

t
t
t
t
L
~

Q

J

K

Q

X
X
X
L
H
L
H
X

X
X
X
L
L
H
H
X

H
L
L
H
H·
H·
L
H
TOGGLE
Qo
00
H
L
QO
00

High State, X ~ Don't Care

~ Positive Edge Transition,

00

~ Previous Condition of Q

'This condition is nonstable; it will not persist when present and clear Inputs
return to their inactive (high) level. The output levels in this condition are not

guaranteed to meet the VOH specification.

2-61

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the devic8 cannot be guaranteed. The devic8 should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guarantged at the absolute maximum ratings.
The. "Recommended Operating Conditions" table will define
the conditions for actual devic8 operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55°C to + 125°C
DM74ALS
OOCto +700C
Storage Temperature Range
-65°C to + 1500C

Recommended Operating Conditions
Symbol

DM54ALS109A

Parameter

VCC

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

DM74ALS109A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

V
V

0.7

0.8

V

10H

High Level Output Current

-0.4

-0.4

mA

10l

Low Level Output Current

4

8

mA

fClK

Clock Frequency

34

MHz

tw(ClK)

Pulse Width

tw

Pulse Width

Preset and Clear

tsu

Data Setup Time

tH

30

0

0

Clock High

16.5

14.5

Clock Low

16.5

14.5

ns

15

15

ns

JorK

15t

15t

PREorCLR
inactive

10t

10t

Data Hold Time

ot

ns

ns
ns

ot

-55
Free Air Operating Temperature
TA
The (t) arrow indicates the positive edge of the Clock is used for reference.

125

0

70

°C

Electrical Characteristics
over recommended operating free-air temperature range. All typical values are measured at Vce = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 rnA

VOH

High Level Output
Voltage

10H = -400,.A
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V
VIH = 2V

II

IIH

III

10
lee
Note 1: Icc is

Min

Typ

Max

Units

-1.5

V
V

Vee- 2

54174ALS
10l = 4mA

0.25

0.4

V

74ALS
IOl=8mA

0.35

0.5

V

Input Current at Max
Input Voltage

Vcc = 5.5V,
VIH = 7V

Clock,J, K

0.1

Preset, Clear

0.2

High Level
Input Current

Vee = 5.5V,
VIH = 2.7V

Clock,J, K

20

Preset, Clear

40

Low Level
Input Current

Vee = 5.5V,
Vil = 0.4V

Clock,J, K

-0.2

Preset, Clear

-0.4

Output Drive Current

Vee = 5.5V, Vo = 2.25V

-30

Supply Current
Vee = 5.5V (Note 1)
measured with J. R, ClK and PRESET grounded, then with J, R. ClK and CLEAR grounded.
2-62

2.4

mA

,.A
mA

-112

mA

4

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

From

To

DM54ALS109A
Min

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Vee = 4.5V to 5.5V
RL = 5000.
CL=50pF

DM74ALS109A

Max

Min

30
Preset
or Clear

OorO

Propagation Delay Time
High to Low Level Output

Preset
or Clear

OorO

tpLH

Propagation Delay Time
Low to High Level Output

Clock

OorO

tpHL

Propagation Delay Time
High to Low Level Output

Clock

OorO

34

MHz

3

17

3

13

ns

5

17

5

15

ns

5

21

5

16

ns

5

20

5

18

ns

Nole 1: See Section 1 for test waveforms and output load.

Logic Diagram
PRESET

CLEAR
ClK

J

R
r --.,

0

I

~
FJ

a

~

K

TLlF/6196-2

2-63

Units

Max

~
CO)
~

~

~

r--------------------------------------------------------------------------------,

~ Semiconductor
National

Corporation

:E

e

DM54ALS131/DM74ALS131
3
to 8 Line DecoderIDemultiplexer
~
cc
• with Address Register
~

CO)
~

10

i!i

General Description

Features

The AlS131 is a three-line to eight-line decoder/demultiplexer with registers on the three address inputs. When the
clock transitions from low to high, the address present at
the select inputs (A, B, and C) is stored in the latches. The
output enable controls, G1 and G2, control the state of the
outputs independently of the select or clock inputs. All of
the outputs are high unless G1 is high and G2 is low. The
AlS131 is ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented
systems.

• Combines decoder and 3-bit address register
• Incorporates 2 enable inputs to simplify cascading
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process

Connection Diagram

Function Table

Dual-In-Llne Package
I

Vee
161

YO
15

VI

14

13

VI

I1A
1

V
:

2

C

3

SELfCT

V2

"

V3
12

V4
11

V3

V5

V6

10

9

C

CLK

ClK G1 G2 C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7

V4

4
CLOCK

S2

G1

5

6

112

G1

~

V1

1

BI

V1
OUTPUT

GNO

X
X

X
L

H
X

X X X H
X X X H

H
H

H
H

H
H

H
H

H
H

H
H

H
H

t
t
t
t
t
t
t
t

H
H
H
H

L
L
L
L

L
l
L
L

L
L
H
H

L L
H H
L H
H H

H
l
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H
H
H

L
L
L
L
L
L

H
H
H
H
X
X

L
L
H
H
X
X

L
H
L
H
X
X

L
H

ENABLE
TLlF/6200-1

Order Number DM54ALS131J,
DM74AlS131M or DM74ALS131N
See NS Package Number J16A, M16A or N16A

Outputs
Select

V5+_
V6

A
'-----.r------B

V2

Inputs

,

H H H H L H H H
H H H H H L H H
H H H H H H L H
H H H H H H H L
Output corresponding to stored
address, l; all others, H.

H = High Logic Level. L = Low Logic Level, X = Don't Care

t

2-64

= TransUion from Low to High Level

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54ALS
DM74ALS
O"Cto +70"C
- 65·C to + 150·C
Storage Temperature Range

Recommended Operating Conditions
Symbol

DM54ALS131

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

DM74ALS131

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

0.8
-0.4

mA

8

mA

50

MHz

10H

High Level Output Current
Low Level Output Current

4

Clock Frequency
Width of Enabling Pulse, (High or Low)

0

tsu

Setup Time

I
I

A,B,C

tH

Hold Time

TA

Free Air Operating Temperature

A,B,C

V

0.7

10L
feLOCK

V
V

2

-0.4

tweLK

Units

Min

40

0

12.5

10

ns

1st

10t

ns

ot

ns

ot

-55

125

70

0

·c

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output Voltage

VOL

Low Level Output
Voltage

Conditions

Min

= 4.5V, II = -18 mA
IOH = -0.4 mA, Vee = 4.5V to 5.5V
54174ALS
Vee = 4.5V
10L = 4mA

=

5V, TA
Typ

Vee

Input Current @ Max.
Input Voltage

Vee

=

5.5V, VIH

=

IIH

High Level Input Current

Vee

5.5V, VIH

IlL

Low Level Input Current

Vee

= 2.7V
= 0.4V

10

Output Drive Current

Vee

lee

Supply Current

Vee

=
=
=
=

5.5V, VIL
5.5V

Vo

=

2.25V

Max

Units

-1.5

V
V

0.25

0.4

V

0.35

0.5

V

0.1

mA

7V

-30
5

5.5V

25·C.

Vee- 2

74ALS
10L = 8mA
II

=

20

/LA

-0.1

mA

-112

mA

11

mA

tI
2-65

Switching Characteristics over recommended operating free air temperature range (Note 1).
Symbol

Parameter

From (Input)
to (Output)

Conditions

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

DM54ALS131
Min

Max

40

Vee = 4.5Vto 5.5V
RL = 5000
CL = 50pF

G2
toY

DM74ALS131
Min

Units

Max
MHz

50

5

18

5

15

ns

tpHL

Propagation Delay Time
High to Low Level Output

G2
toY

5

18

5

15

ns

tpLH

Propagation Delay Time
Low to High Level Output

G1
toY

7

24

7

20

ns

tpHL

Propagation Delay Time
High to Low Level Output

G1
toY

6

20

6

17

ns

tpLH

Propagation Delay Time
Low to High Level Output

Clock
toY

8

28

8

25

ns

tpHL

Propagation Delay Time
High to Low Level Output

Clock
toY

7

24

7

20

ns

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram
--'

A

-

I

0

;---CI

-

.l

Q-

rf

..........

> CLK
VI-

15 YO

~

14 YI

'--

13 Y2
SELECT
INPUTS

>-f

r---

B2

Q

0

~

>

-

-;:t-

CLK

12 13

DATA

OUTPUTS

'---

C3

CLOCK

-

0

...I
~

.

Q

> CLK

...I

II Y4

10

Y5

~

-

r-r

.!.-.{:>o--

9 Y6

7 Y7
ENABLE f 2 5
INPUTS
GI~

~

~

TUF/6200-2

2-66

II

ien

National
Semiconductor
Corporation

~

DM54ALS132/DM74ALS132 Quad 2-lnput NAND Gates
with Schmitt Trigger Inputs
Features

This device contains four independent gates. each of which
performs the logic NAND function. Each input has hysteresis which increases the noise immunity and transforms a
slowly changing input signal to a fast changing. jitter-free
output.

• Swltching specification at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated. ion-implanted Schottky TIL
process
• Functionally and pin-for-pin compatible with Schottky
and Low Power Schottky TIL counterparts
• Improved AC performance over low power Schottky
counterpart

Connection Diagram
14

B4

M

Y4

B3

A3

7

4

AI

BI

Y3

10

13

Yl

A2.

82

Order Number DM54ALS132J,
DM74ALS132M or DM74ALS132N
See NS Package Number J14A, M14A or N14A

Function Table
y= AB
Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H = High Logic Level

L - Low logic Level

2-67

i

t

..

Iii

General Description

vee

..~

Iii

GND

TL/F/8771-1

~

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voliage

7V

-65·C to + 15O"C

Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device can not be guaranteed. The device should not be operated at these limits. The
perametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O·Cto +700C

Recommended Operating Conditions
Symbol

DM54ALS132

Parameter

DM74ALS132

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5

5.5

Vee

Supply Voltage

5.5

4.5

VT+

Positive-Going Input
Threshold Voltage

Vcc = Min to Max

1.4

2

1.4

2

Vee = 5V

1.55

1.85

1.55

1.85

Negative-Going Input
Threshold Voltage

Vcc = Min to Max

0.75

1.2

0.75

1.2

Vee = 5V

0.85

1.1

0.85

1.1

Input Hysteresis

Vcc = Min to Max

0.5

0.5

Vee = 5V

0.6

0.6

VTHYS

V
V

V
V

10H

High Level Output Current

-0.4

-0.4

mA

10L

Low Level Output Current

4

8

mA

TA

Operating Free Air Temperature Range

70

·C

-55

125

0

Electrical Characteristics over recommended free air temperature range
Symbol

Parameter

Test Conditions

VIC

Input Clamp Voltage

Vcc = Min,ll = -18 mA

VOH

High Level Output Voltage

Vee = 4.5V to 5.5V, 10H = Max

VOL

Low Level Output Voltage

Vcc = Min

IT+

Input Current at Positive-Going
Threshold Voltage

Vcc = 5V, VI = VT+

IT-

Input Current at Negative-Going
Threshold Voltage

Vcc = 5V, VI = VT-

II

Input Current at Maximum Input Voltage

IIH

High Level Input Current

III
10

Typ

Min

Max

Units

-1.5

V
V

Vee- 2

DM54174
10l = 4mA

0.25

DM74
IOL=8mA

0.35

0.4
V
0.5
20

p.A

-100

p.A

Vcc = Max, VI = 7V

100

p.A

Vee = Max, VI = 2.7V

20

p.A

Low Level Input Current

Vee = Max, VI = 0.4V

-100

p.A

Output Drive Current

Vee = Max, Vo = 2.25V

-112

mA

ICCH

Supply Current with Outputs High

Vee = Max.

8

mA

ICCl

Supply Current with Outputs Low

Vee = Max

8

mA

-30

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

tplH

Propagation Delay Time
Low to High Level Output

tpHl

Propagation Delay Time
High to Low Level Output

Conditions (Note 1)
Vcc = 4.5V to 5.5V
RL = 5000, CL = 50 pF

Nate 1: See Section 1 for test waveforms and output load.

2-68

DM54ALS132

DM74ALS132

Min

Max

Min

Max

2

13

2

12

2

12

2

11

Units

ns

_

CI
iii:

National
Semiconductor

UI

:=
Ii)

Corporation

....

Co)
Co)

.....

DM54ALS133/DM74ALS133
13-lnput NAND Gate

CI
iii:
......

• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

General Description
This device contains a single gate, which performs the logic
NAND function.

Features

:=

Ii)
....

~

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Une Package
vcc

M

118

1

L

14

2

3

ABC

H

J

K

15

13

12

4
D

11

5
E

8
F

110

Y
9

17 18
G

GND
TL/F/6201-1

Order Number DM54ALS133J, DM74ALS133M or DM74ALS133N
See NS Package Number J16A, M16A or N16A

Function Table
Y = ABCDEFGHIJKLM
Inputs

Output

AthruM

Y

AlllnputsH
One or More
Input L

L

H

~

High Logic Level

L

~

Low Logic Level

H

fII
2-69

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,

Note: The "Absolute Maximum Ratings" are those values
beyond which the ssfBty of the device cannot be guarentBSd. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" teble will define
the conditions for actusl device operation.
.

contact the National Semiconductor Sales Office/
Distributors for ava!labillty snd specifications.
Supply Voltage
7V
Input Voltage
7V
OpEirating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"C to + 70"C
Storage Temperature Range
-65·Cto + 150"C

Recomm~nded
Symbol

Operating Conditions
DM54ALS133

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

DM74ALS133

Units

Min

Nom

Max

Min

Nom.

Max

4.5

5

5.5

4.5

5

5.5

2

2
0.7

0.8

V

-0.4

mA

8

mA

70

·c

IOH

High Level Output Current

-0.4

IOL

Low Level Output Current

4

TA

Free Air Operating Temperature

-55

125

0

Electrical Characteristics
over recommended operating free air tempereture range. All typical values are measured at Vee

= 5V. TA = 25·C.

Symbol

Typ

Parameter

Conditions

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

IOH = -0.4mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V

II

Input Current @ Max
Input Voltage

Vee

IIH

High Level Input Current

Vee

IlL

Low Level Input Current

16

Output Drive Current

lee

Supply Current

Min

= 4.5V.11 = -18mA

VIK

V
V

Max

Unlta

-1.5

V
V

Vee - 2

54174ALS
IOL=4rnA

0.25

0.4

V

74ALS
IOL=8mA

0.35

0.5

V

0.1

mA

20

p.A

-0.1

mA

-112

mA

= 5.5V. VIH = 7V

= 5.5V. VIH = 2.7V
Vee = 5.5V. VIL = 0.4V
Vee = 5.5V
Vo = 2.25V
Outputs High
Vee = 5.5V

-30

Outputs Low

0.24

0.34

mA

0.56

0.8

rnA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Psrameter

DM54ALS133
..', Max

Conditions

Min
tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Lev!!1 Output

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Nota 1: See Section 1 for test waveforms and output load.

2·70

DM74ALS133
Min

Max

Units

1

16

3

11

ns

5

47

5

25

ns

•

National

PRELIMINARY

Semiconductor
Corporation

DM54ALS136/DM74ALS 136 Quad 2-lnput
Exclusive-OR Gates with Open-Collector Outputs
General Description

Features

This device contains four independent gates, each of which
performs the logic excluslve-OR function. The open-co"ector outputs require external pull-up resistors for proper logical operation.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functiona"y and pin for pin compatible with LS TTL
counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

Pull-Up Resistor Equations
R
Vee (Min) - VOH
MAX = N1 (IOH) + N2 (lIH)
R
Vee (Max) - VOL
MIN =
IOl - N3 (lILl
Where:

N1 (IOH) = total maximum output high current for
a" outputs tied to pull-up resistor
N2 (IIW = total maximum input high current for a"
inputs tied to pull-up resistor
Na (lILl = total maximum input low current for a"
inputs tied to pull-up resistor

Connection Diagram
Dual-In-Llne Package
vcc

B4

A4

A1

B1

Y1

Y4

83

7
B2

Y2

GND

TL/F/9161-1

Order Number DM54ALS136J, DM74ALS136M or DM74ALS136N
See NS Package Number J14A, M14A or N14A

Function Table
Y=AEIlB

Inputs

H
L

Output

A

B

Y

L
L
H
H

L
H
L
H

L
H
H
L

= High Logic Laval
= Low logic Laval

2·71
- - - - - - ------

------~--

Absolute Maximum Ratings
Note: The "Absolute MiJximum Ratings" are thosB values
beyond which the safety of the devics cannot be guaranteed. The devics should not be operated at these limits. The
parametric values defined in the "Electrical Charecteristics"
teb/e are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual devics operation.

It Mllltary/Aer08pace specltled devices are required,
contact the National Semiconductor Sales Offlcel
Dlatrlbutora tor availability and speclflcatlons.
Supply Voltage

7V

Input Voltage

7V

High Level Output Voltage

7V

Operating Free Air Temperature Range
DM54ALS
-55"Cto + 125"C
DM74ALS
O"Cto +70"C
Storage Temperature Range

-65·C to + 15O"C

Recommended Operating Conditions
Symbol

DM74ALS136

DM54ALS136

Parameter

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.6

V

VOH

High Level Output Voltage

5.5

5.5

V

6

mA

70

·C

2

IOL

Low Level Output Current

TA

Free Air Operating Temperature

V

2

4
-55

125

0

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions

=

=

VI

Input Clamp Voltage

Vee

ICEX

High Level Output
Current

Vee = Min, Vo
VIL = Max, VIH

VOL

Low Level Output
Voltage

Min,ll

Min

Typ
(Note 1)

Input Current at Max
Input Voltage

=

Max, VI

=

=
=
Vee =

= 2.7V
= O.4V

Vcc

IIH

High Level Input Current

Vee

Max, VI

IlL

Low Level Input Current

Vee

Max, VI

lee

Supply Current

Units

-1.5

V

100

p.A

0.25

0.4

V

0.35

0.5

V

0.1

mA

-16 mA

= 5.5V
= Min
Vee = Min, VOL = Max,
VIL = Max, VIH = Min

54174ALS
IOL

=

4mA

74ALS
IOL = 6mA
II

Max

7V

Max, (Note 1)

3.9

20

p.A

-0.1

mA

5.9

mA

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS136

Conditions
Vee = 4.5V to 5.5V
RL = 2kO
CL = 50pF
Other Input Low
Vee = 4.5V to 5.5V
RL = 2kO
CL = 50pF
Other Input High

Note 1: All typlcals are at Vee = 5V, TA = 25'C.
Note 2: lee Is measured with all inputs at 4.5V and the outputs open.

2·72

DM74ALS136

Units

Min

Max

Min

Max

20

55

20

50

ns

3

16

3

15

ns

20

55

20

50

ns

3

15

3

12

ns

.------------------------------------------------------------------,ciii:
National

_

...~

Semiconductor

Corporation

~
C

DM54ALS137/DM74ALS137 3 to 8 Line
DecoderIDemultiplexer with Address Latches
General Description

Features

The ALS137 is a three line to eight line decoder/demultiplexer with latches on the three address inputs. When the
latch-enable input (CIC) is low. the ALS137 acts as a decoder/demultiplexer. When CIC goes from low to high. the address present at the select inputs (A. B. and C) is stored in
the latches. Further address changes are ignored as long as
CIC remains high. The output enable controls. G1 and~.
control the state of the outputs independently of the select
or latch-enable inputs. All of the outputs are high unless G1
Is high and ~ is low. The ALS137 is ideally suited for implementing glitch-free decoders in strobed (stored-address)
applications in bUS-Oriented systems.

•
•
•
•

Connection Diagram

Function Table

~A~

Va:

.I.r

YO

15

VI

14

Y2
13

YI
IZ

Y4
\I

Inputa
Enable

~

m:::

VI

Y5

.....

~
Ii)

Combines decoder and 3-blt address latch
Incorporates 3 enable inputs to simplify cascading
Low power dissipation .................... 28 mW typ
Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated. ion-implanted Schottky TIL
process

Dual·ln·Llne Package
DATA OUTPUTS
r - - -______
__________

iii:

10

Outputs
Select

G1 G2 C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7

XXHXXXHHHHHHHH
XL XXXXHHHHHHHH
L H LLLLLHHHHHHH
LHLLLHHLHHHHHH
LHLLHLHHLHHHHH
L H LLHHHHHLHHHH

5
A
8
C
~
SElECT

II.

I'z

81

Y7
OUTPUT

LHLHLLHHHHLHHH
LHLHLHHHHHHLHH
LHLHHLHHHHHHLH
L H LHHHHHHHHHH L

:!o

H H

EIlABLE

L

Tl/F/6202-1

Order Number DM54ALS137J, DM74ALS137M or
DM74ALS137N
See NS Package Number J18A, M18A or N16A

L

2·73

=

Low State, H

X X X Output corresponding to stored
address. L; all others. H

= High State, X = Don't Care

...~

Absolute Maximum Ratings
Note: The "Absolute Maximum Rstlngs" sre those values
beyond which the ssfety of the device cannot be gusrsnteed. The device should not be operated st these limits. The
psrsmetric values defined In the "Electricsl Cherscteristlcs"
tsbl9 sre not guarsnteed st the sbsoluts maximum rstlngs.
The "Recommended Operating Conditions" tsble will define
the conditions for sctusl device operation.

If Military/Aerospace 8peclfled devices are required,
contact the National Semiconductor Sale8 Office/
Dlstributora for availability and 8pecHicationa.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperatur~ Range
DM54ALS
- 55·C to + 125"C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS137

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

DM74ALS137

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

0.7

0.8

V

-0.4

-0.4

rnA

8

mA

2

2

V

10L

Low Level Output Current

tw

Width of Enabling Pulse

G[Low

15

10

ns

tsu
lH

Setup Time

A,B,C

15t

10t

ns

Hold Time

A,B,C

5t

5t

ns

0

·C

4

-55
Free Air Operating Temperature
TA
The arrow ( t) indicates the positive edge of the G[ Input pules Is used for reference.

125

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output Voltage

VOL

Low Level Output
Voltage

Conditions

= 4.5V,11 = -18 mA
10H = -0.4mA
Vee = 4.5Vt05.5V
54174ALS
Vee = 4.5V
10L = 4mA

Min

IIH

IlL

= 5V, TA = 25·C.
Typ

Vee

Max

Units

-1.5

V
V

Vee- 2

74ALS
10L = 8mA
II

70

0.25

0.4

V

0.35

0.5

V

Input Current @
Max. Input Voltage

Vee = 5.5V
VIH = 7V

Enable

0.1

A,B,C

0.1

High Levell nput Current

Vee = 5.5V
VIH = 2.7V

Enable

20

A,B,C

20

Enable

-0.1

A,B,C

-0.1

Low Level Input Current

Vee = 5.5V
VIL = 0.4V

10

Output Drive Current

Vee

lee

Supply Current

Vee

= 5.5V, Vo = 2.25V
= 5.5V

2-74

-30
5

rnA
p.A

mA

-112

mA

11

mA

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

Conditions

From (Input)
To (Output)

DM74ALS137

Units

Max

Min

Max

A,B,C
toy

5

25

5

20

ns

A,B,C
toY

6

25

6

20

ns

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

~
toY

4

15

4

12

ns

tpHL

Propagation Delay Time
High to Low Level Output

~
toY

5

18

5

15

ns

tpLH

Propagation Delay Time
Low to High Level Output

G1
toY

5

21

5

17

ns

tpHL

Propagation Delay Time
High to Low Level Output

G1
toY

5

19

5

15

ns

tpLH

Propagation Delay Time
Low to High Level Output

toY

7

27

7

22

ns

Propagation Delay Time
High to Low Level Output

toY

7

25

7

20

ns

tpHL

Vee - 4.5Vt05.5V
RL = 500n
CL = 50pF

DM54ALS137
Min

rn:
rn:

Nota 1: See Section 1 lor test waveforms and output load.

Logic Diagram
"1.-

,..,

-

A~~

~

-;:l
-.....-.

15 YG

~~

14 Yl

J

13 Y2

-

H-J- --

SELECT
INPUTS

Bl..~

Qg.

~

~

~

>OUo:::TS

J

C.!...~

ENABLE
INPUTS

10 Y5

~

~

]"}..!.Y8

H"
i.....-

12 5
81 8

-

11 Y4

H

:E
-

iLL.....cf>-

12 Y3

r-...

W

fI

7 Y7

H

.....

TL/F/6202-2

2·75

_

National

Semiconductor
CorPOration

DM54ALS138/DM74ALS 138
3 to 8 Line DecoderIDemultiplexer
General Description
These Schottky-clamped circuits are designed to be used in
high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In
high-performance memory systems these decoders can be
used to minimize the effects of system decoding. When
used with high-speed memories, the delay times of these
decoders are usually less than the typical access time of the
memory. This means that the effective system delay introduced by the decoder is negligible.
The ALS138 decodes one-of-eight lines, based upon the
conditions at the three binary select inputs and the three
enable inputs. Two active-low and one active-high enable
inputs reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented with no
external inverters, and 32-line decoder requires only one
inverter. An enable input can be used as a data input for
demultiplexing applications.

This decoder/demultiplexer features fully buffered inputs,
presenting only one normalized load to its driving circuit. All
inputs are clamped with high-performance Schottky diodes
to suppress line-ringing and simplify system design.

Features
• Designed specifically for high speed:
Memory decoders
Data transmission systems
• 3- to 8-line decoder incorporates 3 enable inputs to
simplify cascading and/or data reception
• Low power dissipation .•. 23 mW typ
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TIL
process

Connection Diagram
Dual-In-Line Package
DATA OUTPUTS

r------------A~----------~,
yz
YO
Y1
Y3
Y4
Y5
Y6
15

ABC

14

12

13

a2A

82B

11

61

10

Y7

~~OUTPUT

SELECT

ENABLE
TLlF/6111-1

Order Number DM54ALS138J, DM74ALS138M or DM74ALS138N
See NS Package Number J18A, M16A or N18A

2·76

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications..
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55°C to + 125°C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65°C to + 150"C

Recommended Operating Conditions
Symbol

DM74ALS138

DM54ALS138

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

10L

Low Level Output Current

TA

Free Air Operating Temperature

Units

Min

V
V

2
0.7

0.8

V

-0.4

-0.4

mA

8

mA

70

°C

4
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

=

Symbol

Typ

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Min

Conditions

= 4.5V, II = -18 mA
10H = -0.4mA
Vee = 4.5V to 5.5V
54/74ALS
Vee = 4.5V
10L = 4mA
Vee

II

Input Current @ Max.
Input Voltage

Vee

=

5.5V, VIH

=

IIH

High Level Input Current

=
Vee =
Vee =
Vee =

5.5V, VIH

= 2.7V
= 0.4V
Vo = 2.25V

IlL

Low Level Input Current
Output Drive Current

lee

Supply Current

Vee

5.5V, VIL
5.5V

=

25°C.

Max

Units

-1.5

V
V

Vee- 2

74ALS
10L = 8mA

10

5V, TA

0.25

0.4

V

0.35

0.5

V

0.1

mA

7V

-30
5

5.5V

20

p.A

-0.1

mA

-112

mA

10

mA

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

Conditions

DM54ALS138

DM74ALS138

Min

Max

Min

Max

A,B,C
toY

2

28

6

22

ns

A,B,C
toY

6

22

6

18

ns

From (Input)
To (Output)

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Units

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

Enable
toY

2

22

4

17

ns

tpHL

Propagation Delay Time
High to Low Level Output

Enable
toY

4

21

5

17

ns

Note 1: See Section 1 for test wavefonns and output load.

2-77

fI

Function Table
Enable
Inputs

Select
Inputs

G1

~2·

X

H

L
H
H
H
H
H
H
H
H

X

X X X
X X X

L
L
L
L
L
L
L
L

L
L
L
L
H
H
H
H

'1l2

C

Outputs

B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

H
H
L
H
H
H
H
H
H
H

H
H
H
L
H
H
H
H
H
H

H
H
H
H
L
H
H
H
H
H

H
H
H
H
H
L
H
H
H
H

H
H
H
H
H
H
L
H
H
H

H
H
H
H
H
H
H
L
H
H

H
H
H
H
H
H
H
H
L
H

H
H
H
H
H
H
H
H
H
L

= 112A + 112B

Logic Diagram

~~n{i:J:~--~==![=>--~~::::=t=F::~
ii28..:5'--__--'

DATA
OUTPUTS

A I

SELECT
INPUTS

• 2

C 3
TLlF/6111-2

2·78

C

I:

National

_

CI'I

~....

Semiconductor
Corporation

........c
CI'I

DM54ALS151/DM74ALS151 1 of 8 Line
Data Selector/Multiplexer

I:

......

~

General Description

Features

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a
unique three-bit binary code at the Select inputs. Two complementary outputs provide both inverting and non-inverting
buffer operation. A Strobe input is provided which, when at
the high level, disables all data inputs and forces the Y output to the low state and the W output to the high state. The
Select input buffers incorporate internal overlap features to
ensure that select input changes do not cause invalid output
transients.

• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Switching performance is guaranteed over full temperature and Vee supply range
• Pin and functional compatible with LS family counterpart
• Improved output transient handling capability

Connection Diagram

Function Table

Dual-In-Une Package

03

D2

Select

~VCC

2

INPm

al

3

B

A

S

15 D4

X

X

X

H

L
L

L

14 U5

L
L
L
L

H

H
H

H

L
L

H

H
H

H

L
L
L
L
L
L
L
L

am
III

OUTPUTY

OUTPUTW

4

5

I

8TIIOI£S 1

13 116

...
.... t=

......

INPUTS

H
H
H
H

12 01

i~
A
....
i~
S

....

Strobe

C
DATA

H

II SHECTA

L
L
L

....

Outputs

Inputs

;--

I

Iii
....
CI'I

y

W

L
DO
01
02
03
04
05
06
07

DO
01
02
03
04
05
06
07

H

= High Level. L = Low Level. X = Don't Care
= the level of the respective 0 input

00 thru 07

10 SELECTS

~I'\..
SIU...!

~

....

9 SELECTC

TL/F/6203-1

Order Number DM54ALS151J, DM74ALS151M
or DM74ALS151N
See NS Package Number J16A, M16A or N16A

PI
2-79

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the NaUonal Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarant88d. The device should not be operated at th8SelimifB. The
parametric values defined in the "Electrical Characteristics"
tabl8 are not guaranteed at the absolute maximum ratings.
The "Recommended Oparating Conditions" table will define
the conditions for actual device operation.

Operating Free Air Temperature Range
DM54ALS
-55"Cto + 125"C
DM74ALS
O"C to + 70"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS151

Parsmeter

DM74ALS151

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0:7

0.8

V

IOH

High Level Output Current

-1

-2.6

mA

10L

Low Level Output Current

12

24

mA

TA

Free Air Operating Temperature

70

·c

2

2

-55

125

V

0

Electrical Characteristics
over recommended operating free-air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

CondlUons

=

Min

= 4.5V.IIN = -18 mA
Vee = 4.5V. 10H = Max
10H = -400 p.A. Vee = 4.5Vto 5.5V
54174ALS
Vee = 4.5V
10L = 12mA

5V. TA

=

Typ

Vee

2.4

25·C.
Max

Units

-1.5

V

3.2

V
V

Vee- 2

74ALS
10L = 12mA

0.25

0.4

V

0.35

0.5

V

0.1

mA

II

Input Current at
Max Input Voltage

Vee

=

5.5V. VIN

=

7V

IIH

High Level Input Current

Vee

20

p.A

Vee

=
=

2.7V

Low Level Input Current

0.4V

-0.1

mA

10

Output Drive Current

Vee

-112

mA

lee

Supply Current

=
=
=
=

5.5V. VIN

IlL

Vee
5.5V
All Inputs = 4.5V

12

mA

5.5V. VIN

5.5V. VOUT

=

2.25V

-30
7.5

2-80

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Conditions
Vee = 4.5V to 5.5V
CL = 50pF
RL = 500n

From

To

DM54ALS151

DM74ALS151

Min

Max

Min

Max

Units

I
....
....
....CI
CII

Select

y

4

21

4

18

ns

Select

y

8

35

8

24

ns

Propagation Delay Time
Low to High Level Output

Select

W

5

36

7

24

ns

tpHL

Propagation Delay Time
High to Low Level Output

Select

W

7

26

7

23

ns

tpLH

Propagation Delay Time
Low to High Level Output

Data

Y

3

14

3

10

ns

tpHL

Propagation Delay Time
High to Low Level Output

Data

Y

5

21

5

15

ns

tpLH

Propagation Delay Time
Low to High Level Output

Data

W

3

23

3

15

ns

tpHL

Propagation Delay Time
High to Low Level Output

Data

W

4

20

4

15

ns

tpLH

Propagation Delay Time
Low to High Level Output

Strobe

y

4

21

4

18

ns

tpHL

Propagation Delay Time
High to Low Level Output

Strobe

Y

4

25

4

19

ns

tpLH

Propagation Delay Time
Low to High Level Output

Strobe

W

5

27

5

19

ns

tpHL

Propagation Delay Time
High to Low Level Output

Strobe

W

5

26

5

23

ns

iI:

~

....
CII
....

Note 1: See Section 1 for test waveforms and output losd.

fI
2-81

9- , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

."
9-

~

Logic Diagram
STRDI!

::Ii

Q
.....

00

7

4

9-

."

J

9-

~

~
I 3

::Ii
Q

~

22

)-~
3 I

~ ~

DATA

INPUTS

~
4 1&

rr:r

fo-

TY

OUTPU TW

& 14

)-~

.13

fo7 12

II

i

1

J

a[>-L

'--

i
DATA

SELECT

IBINARY.

8 I

1

8

C

1

c
TlIF/620S-2

2·82

,-------------------------------------------------------------------, C
iI::

~ Semiconductor
NatiOnal

~....

Corporatton

~

DM54ALS 153/DM74ALS 153 Dual 1 of 4 Line
Data SelectorIMultiplexer

i

General Description

Features

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-four data sources as a result of a unique
two-bit binary code at the Select inputs. Each of the two
Data Selector/Multiplexer circuits have their own separate
Data and Strobe inputs and a non-inverting output buffer.
The Select inputs A and B are common to both sections.
The Strobe inputs, when at the high level, disable their associated data inputs and force the corresponding output to
the low state. The Select input buffers incorporate internal
overlap features to ensure that select input changes do not
cause invalid output transients.

• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Switching performance is guaranteed over full temperature and Vee supply range
• Pin and functional compatible with LS family counterpart
• Improved output transient handling capability

Connection Diagram

Function Table

Dual-In-Une Package
ITIIIIIlBI I

Select
Inputa

...

..

...

IILICT ., ...2,+-.-0tfi+--,

.....

...

....--+-.

,..,

...

15 1TRDlEaz

1411LECTA

IC2~rlATA

iil--...............fi

lel...l r -

Alt---+-~

i i l - -......-..fj
ICI1-'t-OUTpunl 7

T

...

.....

Output

B

A

CO

C1

C2

C3

G

y

X

X

L
L

L

X
X
X
X
X

X
X
X
X
X
X
X

H

L
L
L
L

X
X
X

L
L

H
H
L
L

H
H

H
X
X
X
X
X
X

L

H
X
X
X
X

Select inputs A and B are common
H

Strobe

X

H
H
H
H

.'t-~-+-+-I

llPUII

Datalnputa

L

H
X
X

L

H

L
L
L
L
L
L
L
L

~....g:

H
L

H
L

H
L

H

to both sections.

= High Level. L = Low Level, X = Don'l Care

1--j!L2CI1

1...

I OUTrunl

TL/F/6204-1

Order Number DM54ALS153J, DM74ALS153M or
DM74ALS153N
See NS Package Number J16A, M16A or N16A

PI
2-83

Absolute Maximum Ratings
Note: The "Absolute Msxlmum Ratings" are those values
beyond which the safety of the device cannot be gusrenI86d. The device should not be operated at these limits. The
parametric values defined in the "EI9ctricaI Characteristics"
table are not guaranlBBd at the absolute msxImum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual d9vice operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sal.. Office/
Distributors for availability and specHIcatlona.

Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
-55°C to + 125°C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65"Cto + 150"C

Recommended Operating Conditions
Symbol

DM74ALS153

DM54ALS153

Parameter

Unite

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

IOH

High Level Output Current

-1

-2.6

mA

10L

Low Level Output Currant

12

24

mA

TA

Free Air Operating Temperature

70

°C

2

2

-55

125

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

= 4.5V.IIN = -18mA
Vee = 4.5V.IOH = Max
10H = -400 /loA. Vee = 4.5V to 5.5V
Vee = 4.5V

= 5V. TA = 25°C.
Min

CondItions

Typ

Vee

II

Input Current at
Max Input Voltage

Vee

2.4

Unite

V

3.2

V

Vee -2

V

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

= 5.5V. VIN = 7V

= 5.5V. VIN = 2.7V
= 5.5V. VIN = 0.4V
Vee = 5.5V. VOUT = 2.25V
Vee = 5.5V
All Inputs = 4.5V

Max

-1.5

IIH

High Level Input Current

Vee

20

II-A

IlL

Low Level Input Current

Vee

-0.1

mA

10

Output Drive Current

-112

mA

lee

Supply Current

14

mA

2-64

-30
7.5

Switching Characteristics
over recommended operating free air temperature range (Note 1).
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay TIme
High to Low Level Output

tpLH

Vee = 4.5V to 5.5V
CL = 50pF
RL = 5000

From

To

DM54ALS153

DM74ALS153

Min

Max

Min

Max

Units

Select

Y

5

29

5

21

ns

Select

y

5

27

5

21

ns

Propagation Delay Time
Low to High Level Output

Data

Y

3

15

3

10

ns

tpHL

Propagation Delay Time
High to Low Level Output

Data

Y

2

18

4

15

ns

tpLH

Propagation Delay TIme
Low to High Level Output

Strobe

y

5

27

5

18

ns

Strobe

y

3

22

5

18

ns

Propagation Delay Time
High to Low Level Output
Note 1: See Section 1 for test waveforms and ou1put load.

tpHL

Logic Diagram
I

STROlE II
ICO

ICI

.

_...

6

.... f----4

~.,.

5

DATA 1
lC2

lC3

}--

7 OUTPUT
YI

4

}--

3

.....

r

JV ~l

·""r ,,f' TI I
2CO

10

~

2Cl

)---,

11

DATA 2

9
2C2

2C3
STROBE G2

12

..... t----I
13
15

-r

OUTPUT
12

fI

_...
.....

TLIF/6204-2

2-85

_

National

PRELIMINARY

Semiconductor
Corporation

DM54ALS/DM74ALS157,158 Quad 1 of 2 Line
Data Selectors/Multiplexers
• Advanced oxide-Isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power SChottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts
• Expand any data input point
• Multiplex dual data buses
• General four functions of two variables (one variable is
common)

General Description
These data selectors/multiplexers contain inverters and
drivers to supply full on-chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word
is selected from one of two sources and is routed to the four
outputs. The ALS157 presents true data whereas the
ALS158 presents inverted data to minimize propagation delay time.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Une Package

vee

-- -INPUTS OUTPUT INPUTS

OUTPUT

4Y

3Y

STROBE 4A

"J 18

15

G

48

14

3A

12

13

38

4A

48

4Y

3A

38

1B

1Y

2A

2B

2Y

-S

9

3Y~

1A

2

SELECT

10

11

3

4

5

8

-- -1A

1B

INPUTS

1Y

2A

7
2Y

2B

OUTPUT INPUTS

IB
GND

OUTPUT
TLIF/8205-1

Order Number DM54ALS157J, DM54ALS158J,
DM74ALS157M, N, or DM74ALS158M, N
See NS Package Number J16A, M16A or N16A

Function Table
Inputs

OutputY

Strobe

Select

A

B

ALS157

ALS158

H

X
L
L
H
H

X
L
H
X
X

X
X
X
L
H

L
L

H
H

L
L
L
L

H

L

L

H

H

L

H - High Level, L - Low Level, X - Don'1 care

This document contains infonnalion on a product under development. NSC """""es the right to change or discontinue this product without notice.

2-86

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are thosB values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

II Mllltary/Aeroapace specified devices are required,
contact the National Semiconductor Sales OffIcel
Dl8trlbutors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
-55"Cto + 125"C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65°C to +15O"C

Recommended Operating Conditions
Symbol

DM54ALS157,158

Parameter

Vee

Supply Voltage

V,H

High Level Input Voltage

V,L

Low Level Input Voltage

10H

High Level Output Current

DM74ALS157,158

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

10L

Low Level Output Current

TA

Free Air Operating Temperature

Unite

Min

0.7

0.8

V

-0.4

-0.4

mA

8

mA

70

'C

4
-55

V
V

2

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25°C.

Symbol

Parameter

Conditions

V,K

Input Clamp Voltage

Vee = 4.5V,I, = -18mA

VOH

High Level Output Voltage

10H = -0.4 mA, Vee = 4.5V to 5.5V

VOL

Low Level Output Voltage

Vee = 4.5V

I,

Input Current @
Max Input Voltage

Vee

= 5.5V, V,H =

Min

Typ

Max
-1.5

Units
V
V

Vce- 2

54174ALS,
10L = 4mA

0.25

0.4

V

74ALS,
IOL=8mA

0.35

0.5

V

0.1

mA

7V

I'H

High Level Input Current

Vee = 5.5V, V,H = 2.7V

20

p.A

I,L

Low Level Input Current

Vee = 5.5V, V,L = 0.4V

-0.1

mA

10

Output Drive Current

Vee

-112

mA

lee

Supply Current

Vee = 5.5V

54174ALS157

6

11

mA

All Inputs = 4.5V

54174ALS158

5

10

mA

= 5.5V

Va = 2.25V

2·87

-30

Switching Characteristics
over recommended operating free air temperature range (Note 1).

Symbol
tpLH

tpHL

tpLH

Propagation Delay Time
Low to High Level Output

r--

157

Propagation Delay Time
High to Low Level Output

r--

Propagation Delay Time
Low to High Level Output

r--

DatatoY

158

157

DM54Ai.S157,158
CondItIons

=

Vc;c
4.5V
to5.5V
CL = 50pF
RL = 500n

158

157

StrobetoY

158

Propagation Delay Time
157
t--High to Low Level Output
158

tpHL

Propagation Delay Time
157
t--Low to High Level Output
158

tpLH

Propagation Delay Time
High to Low Level Output

tpHL
_

From (Input)
To (Output)

Parameter

SelecttoY

~
158

DM74ALS157,158

Min

Max

Min

Max

4

17

4

14

4

18

4

15

2

15

2

12

2

12

2

8

7

25

7

20

5

22

5

18

4

18

4

13

5

22

5

18

7

28

7

24

5

22

5

18

4

16

4

13

5

22

5

18

Units

ns

ns

ns
ns

ns

ns

1: See Section 1 for test waveforms and output load.

Logic Diagrams
Aj 2

8J

~~,

3

~ 5

ll

ill

10

~

.. 14

i4

13

SElECT I
ITI08E 15

8J

~,

IIr •

aa

Aj

......

~,

2

-~,

3

It

5

IIr

•

aa

II

ill

10

~

~,

~

~.

~

~..

.. 14

~..

B4 13
SELfCT

......

J .....
.......
.....

I

ITROBE 15

-

TL/F/6205-2

r ....... .

_....

-.....
TL/F/6205-3

2-88

IJ

National
Semiconductor
Corporation

DM54ALS/DM74ALS160B, 161B, 162B, 163B

Synchronous Four-Bit Counters
General Description
These synchronous presettable counters feature an internal
carry look ahead for application in high speed counting designs. The ALS160B and ALS162B are four-bit decade
counters, while the ALS161B and ALS163B are four-bit binary counters. The ALS160B and ALS161B clear asynchronously, while the ALS162B and ALS163B clear synchronously. The carry output is decoded to prevent spikes during
normal counting mode of operation. Synchronous operation
is provided by having aU flip-flops clocked simultaneously so
that outputs change coincident with each other when so
instructed by count enable inputs and internal gating. This
mode of operation eliminates the output counting spikes
which are normally associated with asynchronous (ripple
clock) counters. A buffered clock input triggers the four flipflops on the rising (positive-going) edge of the clock input
waveform.
These counters are fully programmable, that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with set up data after the
next clock pulse regardless of the levels of enable input.
Low to high transitions at the load input are perfectly acceptable regardless of the logic levels on the clock or enable inputs.
The ALS160B and ALS161 B clear function is asynchronous.
A low level at the clear input sets all four of the flip-flop
outputs low regardless of the levels of clock, load or enable
inputs. These two counters are provided with a clear on
power-up feature. The ALS162B and ALS163B clear function is synchronous; and a low level at the clear input sets
all four of the flip-flop outputs low after the next clock pulse,
regardless of the levels of enable inputs. This synchronous
clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished
with one external NAND gate. The gate output is connected
to the clear input to synchronously clear the counter to all
low outputs. Low to high transitions at the clear input of the
ALS162B and ALS163B are also permissible regardless of
the levels of logic on the clock, enable or load inputs.

The ALS160B through ALS163B feature a fully independent
clock circuit. changes made to control inputs (enable P or T,
or load) that will modify the operating mode will have no
effect until clocking occurs. The function of the counter
(whether enabled, disabled, loading or counting) will be dictated solely by the conditions meeting the stable set-up and
hold times.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts
• Synchronously programmable
• Internal look ahead for fast counting
• Carry output for n-bit cascading
• Synchronous counting
• Load control line
• ESD inputs

Connection Diagram

The carry look ahead circuitry provides for cascading counters for n bit synchronous application without additional gating. Instrumental in accomplishing this function are two
count enable inputs (P and
and a ripple carry output. Both
count enable inputs must be high to count. The T input is
fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high level output pulse
with a duration approximately equal to the high level portion
of QA output. This high level overflow ripple carry pulse can
be used to enable successive cascaded stages. High to low
level transitions at the enable P or T inputs of the ALS160B
through ALS163B may occur regardless of the logic level on
the clock.

n

2-89

Dual-In-Llne Package
OUTPUTS

RIPPLE

CARRY - - - - - - - ENABLE
Vee OUTPUT QA Os Qc 00 T LOAD

10

9

LOAD
CK·

ENABLE

A

B

C

P
8

2
CLEAR CLOCK A

D

B

C

D ENABLEGND
P

DATA INPUTS
TLlF/6206-1

Order Number DM54ALS160BJ, 161BJ, 162BJ,
163BJ, DM74ALS160BM, 161BM, 162BM, 163BM
or DM74ALS160BN, 161BN, 162BN, 163BN
See NS Package Number J16A, M16A or N16A

Absolute Maximum Ratings
If MUltarylAeroapace specified devlcea are required,
contact the National Semiconductor Sal.. 0ffIce1
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54LS
-SS·Cto + 12SOC
DM74LS
O"Cto +70"C
-6S·Cto +1SO"C
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device csnnotbe gusran-

teed. The device should not be operated at these limits. The
parametric values defined in the "Electricsl Characteristics"
table are not gusrsnfBed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will deNne
the conditions for actusl device operation.

Recommended Operating Conditions
Symbol

DM54ALS
160B,161B,162B,163B

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IOH

High Level Output Current

IOL

Low Level Output Current

feLK

Clock Frequency

tseTuP

Setup Time

Data; A, 8, C, 0

I ALS1608/1618
L

Clear (Only for
low
1628 and 1638) High

I

tw

Hold Time

Clear Inactive

Min

Nom

Max

5.5

4.5

5

5.5

2
0.8

V

-0.4

mA

22

0
1St

ns

1St

ns

20t

1St

ns

20t

1St

ns

20t

1St

ns

10t

10t

ns

Data; A. 8, C, D

ot

-3

ot

-3

load
Clear (Only for 1628 and 1638

ClK High or low
AlS1608/1618 ClR Low

4

ns

ot

-3

ns

ot

-3

ns

ot

-4

ot

-4

ns

ot

-7

ot

-7

ns

0

-4

0

-4

ns

20

12.5

ns

20

15

ns

20

15

-55

Operating Free Air Temperature

Note 1: The symbol ( t) Indicates that the rising edge of the clock Is used as a reference.

2-90

mA
MHz

2st

EnP, EnT

Width of Clock
or Clear Pulse

8

40

20t

10

Clear

V
V

0.7

4

Hold 0 (Only for
1608 and 161 B)

Unlll

-0.4

10

Width of Load Pulse
TA

Max

5

4

IAlS1628/1638

tHOLD

Nom

4.5
2

load

Setup 1 (Only for
1608 and 1618)

Min

0

EnP, EnT

DM74ALS
16OB, 161B, 162B, 163B

125

0

ns
70

·C

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Conditions

Typ

Min

= 4.5V, II = -18 mA
10H = -0.4mA
Vee = 4.5V to 5.5V
54174ALS
Vee = 4.5V
IOL = 4mA

= 5V, TA = 25·C.

Vee

Input Current at Max
Input Voltage

Vee

Units
V
V

Vec - 2

74ALS
IOL = 8mA
II

Max
-1.5

0.25

0.4

V

0.35

0.5

V

0.1

mA

= 5.5V, VIH = 7V

= 5.5V, VIH = 2.7V
= 5.5V, VIL = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V

IIH

High Level Input Current

Vee

20

p.A

IlL

Low Level Input Current

Vee

-0.2

mA

10

Output Drive Current

-112

mA

Icc

Supply Current

21

mA

-30
12

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

From

To

DM54ALS

DM74ALS

160B,161B

160B,161B

Min
fMAl(

Max. Clock Freq.

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Vee = 4.5V
to5.5V
RL = 500n
CL = 50pF

Max

Min
40

22

Units

Max
MHz

Clock

Ripple
Carry

5

34

5

20

ns

Clock

Ripple
Carry

5

27

5

20

ns

Propagation Delay Time
Low to High Level Output

Clock

AnyQ

4

19

4

15

ns

tpHL

Propagation Delay Time
High to Low Level Output

Clock

AnyQ

6

25

6

20

ns

tpLH

Propagation Delay Time
Low to High Level Output

EnT

Ripple
Carry

3

18

3

13

ns

tpHL

Propagation Delay Time
High to Low Level Output

EnT

Ripple
Carry

3

17

3

13

ns

tpHL

Propagation Delay Time
High to Low Level Output

Clear

AnyQ

8

27

8

24

ns

Clear

Ripple
Carry

11

32

11

23

ns

Note 1: See Section 1 for test waveforms and outpulload.

2·91

'ALS1628, 'ALS1638 Switching Characteristics
over recommended operating free air temperature range (Note 1)

Symbol

Parameter

Conditions

From

To

DM54ALS

DM74ALS

1628,1638

1628,1638

Min
fMAX

Max. Clock Freq.

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Vee = 4.5V
to5.5V
RL = 5000
CL = 50pF
TA = Min
toMax

Max

Min

40

35

Units

Max
MHz

Clock

Ripple
Carry

5

25

5

20

ns

Clock

Ripple
Carry

5

25

5

20

ns

Propagation Delay Time
Low to High Level Output

Clock

AnyQ

4

18

4

15

ns

tpHL

Propagation Delay Time
High to Low Level Output

Clock

AnyQ

6

25

6

20

ns

tpLH

Propagation Delay Time
Low to High Level Output

EnT

Ripple
Carry

3

16

3

13

ns

tpHL

Propagation Delay Time
High to Low Level Output

EnT

Ripple
Carry

3

16

3

13

ns

Note 1: See SecUon 1 for test waveforms and output load.

2-92

til
DM54ALS160B/DM54ALS161 B/DM54ALS162B/DM54ALS163B/DM74ALS160B/DM74ALS161 B/DM74ALS162B/DM74ALS163B
'CD1'

~..

:-~

A

T

""-----'1

aolc=ao

---c

a

~<

-

--Cl

)

;

~

1

L 6 - -T
----.
010

~<

-

.~))

GI

1

l~)

G(J

~ <1--------.

D

-r

~

010-

d< -- - r---c d

~~

a

u::~

+])

:~

DID

d

CD

~=

cu

8

1

1
4 ----.

(' ()

Ir

UJ(1

'

!
J

rn

E

l!
Q
ca

Q
u

"6»

.9

:!:

:I

. rf
:!:

:I

. ..
~

~

-

I

" ~ J ."_ ·
:!:

:I

c

~

~

~

:I

~

lEI

CO)

~

Logic Diagrams (Continued)

~

ALS161B

~

::, ~-8v-."J :. ">~14';"'OA

:&

I
~

~

:&

1

-

DATA A-3L------+-~__1=t::t:=======:C-)

~

I-_i

...

Q

.....
lEI
,..

,..

CD

~
r-..
==
:&

Q
.....

lEI

~
,..

~
r-..
==
:&

Q
.....

lEI
CO)

,..

CD

~
an
==
:&

I

1

Q

.....
lEI

N
CD

,..

01-

~
an
==
:&

-

Q

iD
,..
CD
,..
~

~

L------------------"1~IIPPLE
~CARR'

Nljl~D_J_--------------------------------------------------~
TLIFI6206-3

:&

Q
.....
lEI

o

CD
,..

~
an
==
:&
Q

2·94

II

DM54ALS160B/DM54ALS161 B/DM54ALS162B/DM54ALS163B/DM74ALS160B/DM74ALS161 B/DM74ALS162B/DM74ALS163B
~

.II

l!I

:}

,

ILhr

GI

:>

~
~
II)

..

T--r

.9

-

~

c
c

=

....
~oJ:C;::=====--~a2"-ll

',I..!...'

.....

"

t

U'

In
....

=
~
!II:
en

~....

Z

5!

54ALSI8I

411TDlCMlE

~

UP/DMCOUITEII

....

i

DATAC

..!...-------fta*~t=====:::t:J

DATAD.!..--!:===:±~Ff:~t======~~
. ,...;'--,,"",--

PI
Tl/F/6207-2

2-109

Logic Diagrams (Continued)
DM54ALS/DM74ALS169B
U~~I~~~-[~------------------

______________________~__~

14

OA

PTAA~------------II;4::::~::::::::::~C:)

~~K~~~--------~+i-----r------------------------------~

13
_SIII1I
4 liT 111m

01

UP/11BW1I COUNTER

--------------1f++---+-I-_________-r--...

PTAI..:4

12

ilATAe .;.-----------t~=:t:1::t:======C)
II

OD
IN~----~~

PTAg~-----t-------t:~~~=====~c:P

16

TL/F/8207-3

2·110

r-------------------------------------------------------------------,c

iii:

~ Semiconductor
National

E

CorporaHon

...

Ii)

~

DM54ALS174/DM54ALS175/DM74ALS174/DM74ALS175
Hex/Quad 0 Flip-Flops with Clear

i

General Description

Features

Ii)

These positive-edge-triggered flip-flops utilize TTL circuitry
to implement O-type flip-flop logic. Both have an asynchronous clear input, and the quad (175) version features complementary outputs from each flip-flop.

• Advanced oxide-isolated ion-implanted Schottky TTL
process
• Pin and functional compatible with LS family counterpart
• Typical clock frequency maximum 80 MHz
• Switching performance guaranteed over full temperature and Vee supply range
• 54ALS174 contains six flip-flops with separate 0 inputs
and outputs
• 54ALS175 contains four flip-flops with separate 0 inputs and both and outputs

~

Information at the 0 inputs meeting the setup time requirements is transferred to the outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the high or low level, the 0 input signal has no effect
at the output.

a

is

a

a

a

Connection Diagrams

Function Table

Dual-In-Llne PaCkage
VCC

06

D8

OS

OS

04

Inputs
04

CLOCK

Outputs

Cleer

Clock

D

Q

Q*

L
H
H
H

X

X

t
t

H
L

L
H
L

L

X

ao

H
L
H
00

E

...

i

...~
~

i.....

~
Ii)

...01

= High Level (steady state)
L = Low Level (steady state)
X = Don't Care
t = Transition from Low to High Level
00 = the level of Q before the indicated steadyH

state input conditions were astebllshed
CLEAR

O.

O.

02

02

03

03

GNO

TL/F/6'12-1

'applies to 54ALS175174ALS175 only

Order Number DM54ALS174J or DM74ALS174M, N
See NS Package Number J16A, M16A or N16A
Dual-in-Une Package

Order Number DM54ALS175J
or DM74ALS175M, N
See NS Package Number J16A,
M18Aor N16A

fI
TL/F/6112-2

2-111

~bsolute

Maximum Ratings

If Military/Aerospace apeclfled devlcea are required,

Note: The "Absolute Maximum Ratings" ST9 those values
beyond which the safety of the device cannot be guarsnteed. The device should not be operated at these limits. The
perametric values defined in the "Electricsl Cheracteristics ..
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actusl device operation.

contact the National Semiconductor Sales Office/
DIstributors for availability and apecHlcatlona.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS174,175

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IOH

DM74ALS174,175

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

V
V

0.7

0.8

V

High Level Output Current

-0.4

-0.4

mA

10L

Low Level Output Current

4

8

mA

tw

Pulse Width

tsETUP

Setup Time (Note 1)

Clock
High or Low

12.5

10

Clear Low

15

10

Data Input

15t

10t

Clear
Inactive State

8t

6t

tHOLD

Data Hold Time (Note 1)

'eLOCK

Clock Frequency

TA

Free Air Operating Temperature
-55
t Indicates that the rising edge of the clock Is used ss reference.

ot

ns

ns
ns

ot

0

40

0

50

MHz

125

0

70

·C

Note 1: The symbol

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25"C.

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,IIN = -18 mA

VOH

High Level Output
Voltage

10H = -400 p.A
Vee = 4.5Vto5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V

Min

Vee -2

Typ

Max

Units

-1.5

V

Vee -1.6

DM54/74
IOL=4mA

0.25

DM74
10L = 8mA

0.35

V
0.4

~

V
0.5

II

Input Current at
Max Input Voltage

Vee = 5.5V, VIN = 7V

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

p.A

IlL

Low Level Input Current

Vee = 5.5V, VIN = 0.4V

-0.1

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

-112

mA

lee

Supply Current

Vee = 5.5V
Clock = 4.5V
Clear = GND
Input = GND

o

ALS174
ALS175

2-112

0.1

-30
11

19

8

.14

mA

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

DM54ALS174,175

Conditions

Min
fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
low to High level
Output From Clear (175 Only)

tpHL

tpLH

tpHL

RL = 500n
CL = 50pF
Vee = 4.5V to 5.5V

Max

40

DM74ALS174,175
Min

Units

Max
MHz

50

5

20

5

18

ns

Propagation Delay Time
High to low level
Output From Clear

8

30

8

23

ns

Propagation Delay Time
low to High level
Output From Clock

3

20

3

15

ns

Propagation Delay Time
High to low level
Output From Clock

5

24

5

17

ns

Nota 1: See Section 1 lor test waveforms and outpu1loed.

PI
2-113

Logic Diagrams
54ALS174174ALS174
01

3

54ALS175174ALS175

or-2-o Ql

0

01

01
CLOCK

CLOCK

01

CLEAR

Y
02

4

02

or-J-o 02

0

02
CLOCK

CLOCK

02

CLEAR Q

CLEAR

J
03
03

6

Or2-0

0

12

Q3

0

10

Q3

CLOCK
11

CLOCK

03

CLEAR

CLEAR

Y
04

11

04

O~ 04

0

CLOCK

CLOCK

CLOCK
CLEAR

r

06
CLOCK

14
9

ot-ll-o 06

0

,...,

CLOCK
CLEAR

CLEAR

1

-v
"'"

04

CLOCK

14

04

TL/F/6112-4

or2-0 05

0

15

CLEAR

Y
13

0

CLEAR "0

CLEAR

05

13

j
TL/F/6112-3

2·114

_

National

PRELIMINARY

Semiconductor
Corporation

DM54ALS190/DM74ALS190/DM54ALS191/DM74ALS191
Synchronous 4-Bit Up/Down Decade and Binary Counter
General Description
The 'AlS190 and 'AlS191 are synChronous, reversible up/
down counters. The 'ALS190 is a 4-bit decade counter and
the' AlS191 is a 4-bit binary counter. Synchronous counting
operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each
other when so instructed by the steering logiC. This mode of
operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.
The outputs of the four flip-flops are triggered on a low-tohigh level transition of the clock input if the enable input (G)
is low. A high at G inhibits counting. The direction of the
count is determined by the level of the down/up (D/U) input.
When % is low, the counter counts up and when D/U is
high, it counts down.
These counters feature a fully independent clock circuit.
Changes at the control inputs (G and D/U) that will modify
the operating mode have no effect on the contents of the
counter until clocking occurs. The function of the counter
will be dictated solely by the condition meeting the stable
set-up and hold times.
These counters are fully programmable; that is, the outputs
may each be preset to either level by placing a low on the
load input and entering the desired data at the data inputs.
The output will change to agree with the data inputs independently of the level of the clock input. This feature allows
the counters to be used as modulo-N dividers by simply
modifying the count length with the preset inputs.
The ClK, D/U, and lOAD inputs are buffered to lower the
drive reqUirement, which significantly reduces the loading
on, or current required by, clock drivers, etc., for long parallel words.

Two outputs have been made available to perform the cascading function; ripple clock and maximum/minimum count.
The latter output produces a high-level output pulse with a
duration approximately equal to one complete cycle of the
clock while the count is zero (all outputs low) counting down
or maximum (9 or 15) counting up. The ripple clock output
produces a low-level output pulse under those same conditions but only while the clock input is low. The counters can
be easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts
• Single down/up count control line
• look-ahead circuitry enhances speed of cascaded
counters
• Fully synchronous in count modes
• Asynchronously presettable with load control

Connection Diagram
Dual-In-Llne Package

---N'UTS

DATA

Vcr:

A

OUTPUTS

MAXI

RIPPLE

C\.OCKCLOCK _

N'UTS

LOAD

DATA

C

115114 113 11.111 110

/18

DATA

D

9

I I l I ! I
A

'"
CK

IIIPI'LE MAXI LOAD

C\.OCK

C

IIIN

r-B

aa
I
1

QA

I

DATA

B

G

DN/UP

Y I

Dc

00

I

I

I' 13 14 15 Ie 17 18

aa

--INPUT

Order Number DM54ALS190J, DM54ALS191J,
DM74ALS190M, DM74ALS191M,
DM74ALS190N or DM74ALS191N
See NS Package Number J16A, M16A or N16A

D

QA ENABLE

OUTPUTS

G

DOWNI
UP

N'UTS

--

Dc

00

GND

OUTPUTS

Tl/F/6208-1

ThIs document contains Information on a device under davalopment. National SemIconductor Corporation reserves the right t. change or discontinue thl.
product without nolios.

2-115

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

Note: The "Absolute Msximum Ratings" are those values
beyond which the ssfety of the device cannot be gusrsn·
teed. The device should not be operated at these limits. The
psrsmetric values defined in the "Electricsl Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actusl device operation.

Operating Free Air Temperature Range
DM54AlS
- 55'C to + 125'C
DM74AlS
O"Cto +70"C
Storage Temperature Range
-65'Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS190, 191

Parameter

Vee

Supply Voltage

VIH

High level Input Voltage

VIL

low level Input Voltage

DM74ALS190, 191

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

0.7

0.8

V
mA

2

V

2

10H

High level Output Current

-0.4

-0.4

10L

low level Output Current

4

8

mA

feLOCK

Clock Frequency

'AlS190

0

25

MHz

0

30

MHz

tw

Pulse Duration

ClK High or low

'AlS191

tsu

tH

Setup Time

Hold Time

I
I

20

0

25

'AlS190

25

20

'AlS191

20

16.5

ns

lOAD low

25

20

ns

Data before lOAD t

25

20

ns

G before ClK t

45

20

ns

0/0 before CLK t

45

20

ns

lOAD Inactive before ClK t

20

20

ns

ns

Data after lOAD t

5

5

ns

GafterClKt

0

0

ns

DIU after ClK t
TA

0

0
-55

Operating Free Air Temperature

0
125

ns
70

0

'C

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
DM74ALS190, 191
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

Max
-1.5

Units

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18 mA

VOH

High level Output
Voltage

Vee = 4.5V to 5.5V
10H = -0.4mA

VOL

low level Output
Voltage

Vee = 4.5V

54174AlS
10L = 4mA

0.25

0.4

V

Vee = 4.5V

74AlS
10L = 8mA

0.35

0.5

V

0.1

rnA

II

Input Current at Max
Input Voltage

Vee = 5.5V, VI = 7V

IIH

High level Input Current

Vee = 5.5V, VI = 2.7V

IlL

low level Input
Current

Vee = 5.5V,
VI = 0.4V

10

Output Drive
Current

Vee = 5.5V,
Vo = 2.25V (Note 2)

Vee- 2

V
V

20

p.A

GorClK

-0.2

mA

All Others

-0.1

rnA

-112

mA

-30

Supply Current
Vee = 5.5V, All Inputs at OV
12
22
lee
Note 1: All typical values are at Vee = SV, TA = 2S'C.
Note 2: The output conditions have been chosen to produce a current that closely approximates one half of the true short circuR output current, lOS.
2·116

mA

Switching Characteristics (Note 1)
Symbol

fMAX

Parameter

From (Input)
to (Output)

Maximum Clock Frequency

Conditione

Min
Vee - 4.5Vto 5.5Vl'ALS190

tpLH

Propagation Delay Time
Low to High Level Output

LOAD to
Any 0

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

DM54ALS190,191

CL
RL
TA

=
=
=

50 pF
500n
Minto Max

I'ALS191

Max

DM74ALS190,191
Min

Unite

Max

20

25

MHz

25

30

MHz

7

37

8

30

ns

LOAD to
Any 0

8

34

8

30

ns

Propagation Delay Time
Low to High Level Output

A,B,C,Dto
Any 0

4

25

4

21

ns

tpHL

Propagation Delay Time
High to Low Level Output

A, B, C, Dto
Any 0

4

25

4

21

ns

'PLH

Propagation Delay Time
Low to High Level Output

CLKto

5

24

5

20

ns

tPHL

Propagation Delay Time
High to Low Level Output

CLKto

5

24

5

20

ns

tpLH

Propagation Delay Time
Low to High Level Output

CLKto
Any 0

3

26

3

18

ns

tpHL

Propagation Delay Time
High to Low Level Output

CLKto
Any 0

3

22

3

18

ns

tpLH

Propagation Delay Time
Low to High Level Output

CLKto
Max/Min

8

37

8

31

ns

tpHL

Propagation Delay Time
High to Low Level Output

CLKto
Max/Min

8

34

8

31

ns

tpLH

Propagation Delay Time
Low to High Level Output

D/Uto

12

45

15

37

ns

Propagation Delay Time
High to Low Level Output

D/Uto

10

36

10

28

ns

tpLH

Propagation Delay Time
Low to High Level Output

D/Uto
Max/Min

8

35

8

25

ns

tpHL

Propagation Delay Time
High to Low Level Output

D/Uto
MaxiMin

8

30

8

25

ns

tpLH

Propagation Delay Time
Low to High Level Output

F!OO

4

21

4

18

ns

Propagation Delay Time
High to Low Level Output

RCO

4

23

4

18

ns

tpHL

tpHL

RCO

F!OO

RCO
RCO

Gto
Gto

Note 1: See SectIon 1 lor test waveionns and output load.

fI
2-117

Logic Diagrams
ALS190
11~1 MAX/MIN

-~t~~~4=[)I----~tr+-------~s ~Q

rm~

....

~-

7

11

~

Cl

>--+--110

.:...h

~~~r-------------~~~----<~~----~----'~
1
"'I
r-~:t:4::t:l:t:t::::[:Jo-----H-+--------+-4-- I~I

~

..;.11;..1

mm=JD-=--=J)J[L.::>-m===t-~tL-.-... ~ '" --0

r-!..utti:t:::o4"":n)r=>---tt!:t::i~s~>-+--Il0
;;;;;,

~~~~---~-------H~fI
I

L4~~~_JC>~---H~-------+4~~
I

~~~~----+-------4~~
I
TLiF/82D8-2

Pin numbers shown are for J and N packages.

2-118

Logic Diagrams (Continued)
ALS191

>--1___

,.;,11.;;.21

--r-

-

MAXIMIN

1131 RU

D/U~O--141

C~ ~ o--~~~~~~-------~~~~--------,

....

mD~

~~ll_5tIJt~~:t4=~~~:t::~I=--:>>-----rt1r-1--------t~~~O
"""O~Cl

....:===~!lL~~t-11D

~

I

........

.:....~
J

........

I

=

.:;ll;.;.:Oli-1tt:t:t:t::t:t:1tt::::[):>-----H+---------+-oI~
161
S
~Oc
..~

......+-+-H--L.J)r-~...
1·L)-r>-+4'""___,-~..J<:t---......o

Cl

' : : :
---.JL?--=3:J--1H1D
+-++tt-+±+tt-b::[",,:J"~D3)[r::>-ttt:t::i=s~

=-

~tttt~~~~~------H.:....~
I

TL/F/8208-3

Pin numbers shown are for J and N packages.

2-119

Timing Diagrams
'ALS190 TypIcal Load, Count, and Inhibit Sequences

A

...

DATA
INPUTS

o
ClOCK

DIU

--

OUTPUTS

MAXIMIN -

-..,

Reo _ - - I

I

9

2

2

I----COUNT UP----.I!-INHIBIT-

~

LOAD

I-----...:....~
Tl/F/6208-4

2-120

Timing Diagrams (Continued)
'ALS191 Typical Load, Count, and Inhibit Sequences

A

L.

rDATA
INPUTS

L.
L.
eLK

DIU

o.

- --.

OUTPUTS

oc_~

oo_~

MAXIMIN -

lmI
-

--.

~113

14

15

2

2

i-----CDUNT uP-----.II-INHIBIT-

15

14

13

I-----COUNT DOWN------i

~

LOAD
TUF/620B-5

2·121

~ Semiconductor
Natlonal

PRELIMINARY

Corporation

DM54ALS192/DM74ALS192/DM54ALS193/DM74ALS193
Synchronous Four-Bit Up/Down Counters
(Dual Clock with Clear)
General Description
The 'ALS192 and 'ALS193 are synchronous, reversible up/
down counters. The 'ALS192 is a 4-blt decade counter and
the 'ALS193 is a 4-bit binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each
other when so instructed by the steering logic. This mode of
operation 'eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.
The outputs of the four flip-flops are triggered by a low-tohigh level transition of either count (clock) input (up or
down). The direction of counting is determined by which
count input is pulsed while the other count input is high.
All four counters are fully programmable; that is, each output may be preset to either level by plaCing a low on the
load input and entering the desired data at the data inputs.
. The output will change to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying
the count length with the preset inputs.
A clear input has been provided that forces all outputs to
the low level when a high level is applied. The clear function
Is Independent of the count and the load inputs. The clock,
count, and load inputs are buffered to lower the drive requirements. This significantly reduces the loading on clock
drivers, etc., for long parallel words.

These counters were designed to be cascaded without the
need for external circuitry. The borrow output (BO) produces
a low-level pulse while the count is zero (all outputs low)
and the count-down input is low. Similarly, the carry output
(CO) produces a low-level pulse while the count is maximum
(9 or 15) and the count-up input is low. The counters can
then be easily cascaded by feeding the borrow and carry
outputs to the count-down and count-up inputs, respectively, of the succeeding counter.

Features
• SWitching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Functionally and pin-for-pin compatible with Schottky
and low power Schottky TIL counterparts
• Improved AC performance over Schottky and low power Schottky counterparts
• Look ahead circuitry enhances cascaded counters
• Fully synchronous in count mode
• Parallel asynchronous load for modulo-N count lengths
• Asynchronous clear

Connection Diagram
Dual-In-Une Package

-----IN'U1'S

Vee

0U11'UTS

.uTa

DATA
BORROW
DATA DATA
A CLEAR
CARRY LOAD
C
D

I.&i.s 1.4 I.. 1.2 -111 1.0
I I 1 I 1 I

g

I I I J I I
• J2 13 14 15 J& P Ie

--DATA

CIa

OA

DOWN

UP

8

.ur

OUlPUTS

INPUTS

-Qc

Do

GND

0U11'UTS

TL/F/B209-1

Order Number DM54ALS192J, 193J, DM74ALS192M, 193M or DM74ALS192N, 193N
See NS Package Number J16A, M16A or N16A

This document contains information on a device under development. National Semiconductor Corporation reserves the right to change or discontinue this
product without notice.

2-122

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
perametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Operating Free Air Temperature Range
DM54ALS
- 55'C to + 125'C
DM74ALS
Oto +70"C
Storage Temperature Range
-65'Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS192,193

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

IOH

High Level Output Current

IOl

Low Level Output Current

fClK

Clock Frequency 'ALS192

tw

Pulse Duration

Setup Time

Typ

Max

4.5

5

5.5

4.5

5

5.5

2

Units
V
V

0.7

0.8

V

-0.4

-0.4

mA

0

20
25

8

mA

0

25

MHz

0

30

MHz

'ALS193

0
10

10

ns

LOAD Low

25

20

ns

'ALS192

25

20

ns

'ALS193

30

16.5

ns

25

20

ns

20

20

ns

20

20

ns

17

17

ns

15

15

ns

5

5

ns

0

0

ns

Data before LOAD

t
t

or DOWN

t

t

or DOWN

t

t
DOWN High before UP t
Data after LOAD t
UP High after DOWN t
DOWN High after UP t
UP High before DOWN

TA

Min

CLRHigh

LOAD Inactive before UP

Hold Time

Max

4

CLR Inactive before UP

tH

Typ

2

UP or DOWN High or Low
tsu

DM74ALS192,193

Min

0
-55

Operating Free Air Temperature

0
125

ns
70

0

'C

Electrical Characteristics over recommended operating free air temperature range
DM74ALS192,193
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

Units
Max
-1.5

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18mA

VOH

High Level Output

Vee = 4.5V to 5.5V
IOH = -0.4mA

VOL

Low Level Output
Voltage

Vee = 4.5V

54/74ALS
IOl = 4mA

0.25

0.4

V

Vee = 4.5V

74ALS
IOl = 8mA

0.35

0.5

V

0.1

mA

V

Vec - 2

II

Input Current at
Max Input Voltage

Vee = 5.5V, VI = 7V

IIH

High Level Input Current

Vee = 5.5V, VI = 2.7V

III

Low Level Input Current

Vee = 5.5V, VI = 0.4V

2-123

I
I

V

20

IJ-A

UP,DOWN

-0.2

mA

All Others

-0.1

mA

Electrical Characteristics over recommended operating free air temperature range (Continued)
DM74ALS192, 193
Symbol

10

Parameter
Output Drive Current

Conditions
Vee

Min

= 5.5V, Vo = 2.25V (Note 2)

Typ
(Note 1)

-30

Units
Max
-112

Supply Current
Vee = 5.5V (Note 3)
12
22
Note 1: All typical values are at Vcc = 5V, TA = 2S'C.
Note 2: The output conditions have been chosen to produce a current that closely approximates one half of the true short circuH output curren~ lOS.
Note 3: Icc Is measured with the clear and load inputs grounded, and all other inputs at 4.SV.

lee

mA
mA

Switching Characteristics (Note 4)
Symbol
fMAX

Parameter
'ALS192
'ALS193

Conditions

From
To
(Input) (Output)

Vee = 4.5V to 5.5V
CL = 50pF
RL = 500n
Up
TA = Minto Max

CO

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Up

CO

tpLH

Propagation Delay Time
Low to High Level Output

Down

80

tpHL

Propagation Delay Time
High to Low Level Output

Down

,80

tpLH

Propagation Delay Time
Low to High Level Output

Up or
Down

AnyQ

tpHL

Propagation Delay Time
High to Low Level Output

Up or
Down

AnyQ

tpLH

Propagation Delay Time
Low to High Level Output

IOA5

AnyQ

tpHL

Propagation Delay Time
High to Low Level Output

LOAD

AnyQ

CLR

AnyQ

Propagation Delay Time
High to Low Level Output
Note 4: See Section 1 for teat waveforms and output loed.

tpHL

2·124

DM54ALS192,193
Min

Max

DM74ALS192, 193
Min

Units

Max

20

25

MHz

25

30

MHz

3

20

4

16

ns

3

21

5

18

ns

4

20

4

16

ns

5

22

5

18

ns

4

27

4

19

ns

4

23

4

17

ns

8

38

8

30

ns

8

37

8

28

ns

5

20

5

17

ns

Logic Diagrams
'ALS192

-

(12)

co

I

~"'---­
CLR~~

(13)

B

mo~

~

4-

I

UP_(5~)-----;~;-~~+;r-~__~:::::::::::::[--:)O-

)t

________-,

OOWN+.(4~)----~r+~ri-r~~-+--~~
A

~

115

~~~E$~~==t:~~~::::--"r----------------r~~
~Q
~ Cl
1~~4-~~~::~

+

____~I::::~::r=--~--------_rtr~~10
I ':"'1
.A.

-

. .··,r

T

-(I-)lr---~~E$~~~~~-:>>----------rt----------------t~~ ~Q
~-~~
J_
~L
._
>--+--110

_(9_)

lJ

J

s
itt1~$~$~~:[:>>----------rt----------------t~-

m1t=J[-}-"::jLD--+--':::[~:)h

"'74::ff~:fE3D

1r
-

J

::n
--

~QD
(7)

10

--

L----4-~~~~==cr-~--.--4.:...~
~.

J
TL/F/6209-2

Pin numbers shown are for J and N packages.

2-125

Logic Diagrams (Continued)
'ALS193
112) Cli

~"--­
CLR---vv
-

113)

e

mlI~
UP IS)

~~(4~)------~~~~~~~~-;---tbD=;-

A(15)y

I

:

..t:*=l~$~~$;::={--=)<>-----------t-ir------------1t:~~
S

~

---Q
13)

.....cI>Cl

!-U-W-l-U--==-___~I::I::t:::r=)_----+r_f-__oI1D
_
I-=---o-

I
..

~~~~~------------_+~----_<~p_---~l------~
~-

I

~~r+~~+-----~--~-----1~--r~--1~1:~1~----+-~R ~
~~~-----+------~~---- Cl

:=~~>--~ID

l

TlIF/6209-3

Pin numbers shown are for J and N packages.

2-126

Timing Diagrams
'ALS192 Typical Clear, Load and Count Sequences

C~----.r-l~

____________________________________________________________________

DATA
INPUTS

UP

DOWN

Qa

OUTPUTS

110

III
SEQUENCE
ILWSTIIATED

----CLEAR

I------COUNT U P - - - - - I

I-----COUNTDOWN-----I

~

PRESET

TUF/6209-4

Note A:. Clear overrides load. data. and count inputs.
Note B: When counting uP. count-down input must be high; when counting down. count·up input must be high.

2·127

Timing Diagrams (Continued)
'ALS193 Typical Clear, Load and Count Sequences

CLR----.r-l~----------------------------------------------------------------

DATA
INPUTS

UP

DOWII

IIA

D,
OUTPUTS

Dc

DD

I:U

l1li
SEDUENCE
ILLUSTRATED

13

--- --CLEAR

14
15
I-----COUNTUP-----!

13
15
14
I-----COUNT DOWN-----I

PRESET

TLlFI6209-5

Note A: Claar overrides load, data, and count inputs.
Note B: When counting up, count-down Input must be high; when counting down, count-up input must be high.

2-128

_

National

Semiconductor
Corporation

DM54ALS240A/DM74ALS240A/DM54ALS241 AI
DM74ALS241A Octal TRI-STATE® Bus Drivers
General Description

Features

These octal TRI-STATE bus drivers are designed to provide
the designer with flexibility in implementing a bus interface
with memory, microprocessor, or communication systems.
The output TRI-STATE gating control is organized into two
separate groups of four buffers. The ALS240A control inputs symmetrically enable the respective outputs when set
logic low, while the ALS241A has complementary enable
gating. The TRI-STATE circuitry contains a feature that
maintains the buffer outputs in TRI-STATE (high impedance
state) during power supply ramp-up or ramp-down. This
eliminates bus glitching problems that arise during power-up
and power-down.

• Advanced low power oxide-isolated ion-implanted
Schottky TIL process
• Functional and pin compatible with the DM54174LS
counterpart
• Improved switching performance with less power dissipation compared with the DM54174LS counterpart
• Switching response specified into 500n and 50 pF load
• Switching response specifications guaranteed over full
temperature and Vee supply range
• PNP input design reduces input loading
• Low level drive current:
54ALS = 12 mA, 74ALS = 24 mA

Connection Diagram

Function Tables

Dual-In-Llne Package
Vee 2G

tYt

2M tYa 2A3

tY3

'ALS240A

2AI tY4 2At

Input

Output

G

A

Y

L
L

L

H

H

H

X

L
Z

'ALS241A
10

1A 1

ZY.

1A1

IVa 1A3

2V!

Input

1M 2Y1 GND
TL/F/6210-1

2G

Top View

H
H

Order Number DM54ALS240AJ,
DM74ALS240AWM or DM74ALS240AN
See NS Package Number J20A, M20B or N20A

L
H

Dual-In-Line Package

~

'ALS241A
Input

Output

Y

1G

L

L

H
X

H

L
L

Z

H

2A

Output
1A

Y

L

L

H
X

H

Z

High Level Logic State

L ~ Lew Level Logic Slata
X ~ Don't Care (Either Low or High
Level logic State)

Vee IG

Z ~ High Impedance (Oft) State

lA I

2Y4

lAI

IY3

lA3

In

1M IYl ClND
TL/F/621 0-2

Top View
Order Number DM54ALS241AJ,
DM74ALS241AWM or DM7~ALS241AN
See NS Package Number J20A, M20B or N20A

2·129

fI

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the ssfety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric vs/ues defined in the "ElBctrical ChsrsctBristics"
tsb/B are not gusrantBBd at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales OffIce/
Distributors for availability and specifications.
Supply Voltage, Vee
Input Voltage

7V

7V
Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
DM54ALS
- 55'C to + 125'C
DM74ALS
O'Cto +70'C
Storage Temperature Range
-65'C to + 150'C

Recommended Operating Conditions
Symbol

DM54ALS240A, 241A

Parameter

DM74ALS240A,241A

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.7

0.8

V

2

2

V

10H

High Level Output Current

-12

-15

mA

10l

Low Level Output Current

12

24

mA

TA

Operating Free Air Temperature

70

'C

-55

0

125

Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise specified)
Symbol

Parameter

DM54ALS240A, 241A

Conditions

Min
VIK

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

Vee
Vee

=
=
=

4.5V,11

=

Typ

Typ

V
V
V

2

2

V

-3mA

Low Level Output
Voltage

Vee = 4.5V
10l = 54ALS (Max)

II

Input Current at Max
Input Voltage

Vee

IIH

High Level Input
Current

Vee

=

5.5V, VI

III

Low Level Input
Current

Vee

=

5.5V, Vil

=

0.4V

10

Output Drive
Current

Vee

=

5.5V, Vo

=

2.25V

10ZH

High Level TRI-STATE Vee
Output Current

=

5.5V, Vo

=

2.7V

10Zl

Low Level TRI-STATE
Output Current

Vee

=

5.5V, Vo

=

O.4V

Icc

Supply Current

Vee = 5.5V, ALS240B
Outputs High

4

10

Outputs Low

13

Outputs TRI-STATE

14

Vee = 5.5V,ALS241B
Outputs High

9

Outputs Low
Outputs TRI-STATE

= 74ALS (Max)
= 5.5V, VI = 7V

0.25

0.4

0.25

0.4

V

-

-

0.35

0.5

V

0.1

0.1

rnA

20

20

p.A

-0.1

-0.1

rnA

-112 • -30

-112

mA

20

20

p.A

-20

-20

p.A

4

10

rnA

23

13

23

rnA

25

14

25

mA

17

9

15

mA

15

28

15

26

mA

17

32

17

30

rnA

2.7V

-30

2-130

-1.5

2.4

4.5V

Max

Units

Max

2.4

-0.4mA Vee - 2

=

Min
Vee- 2

4.5V to 5.5V 10H

VOL

10l

DM74ALS240A,241A

-1.5

-18 mA

=
10H =
10H =

Max

'ALS240A Switching Characteristics over recommended operating free air temperature range
Symbol
tpLH

Parameter
Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tPZH

Output Enable Time
to High Level Output

Conditions
Vee = 4.SV to 5.5V,
CL = 50pF,
R1 =
R2 = 5000.,
TA = Minto Max

soon,

From
(Input)

To
(Output)

A

Y

G
tPZL

Output Enable Time
to Low Level Output

tpHZ

Output Disable Time
from High Level Output

tpLZ

G

Output Disable Time
from Low Level Output

DM54ALS240A

DM74ALS240A
Units

Min

Max

Min

Max

2

22

2

' 9

ns

2

11

2

9

ns

4

34

S

13

ns

5

26

S

18

ns

1

1S

2

10

ns

3

24

3

12

ns

y

y

'ALS241 A Switching Characteristics over recommended operating free air temperature range
Symbol
tpLH

Parameter
Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tPZH

Output Enable Time
to High Level Output

tPZL

Output Enable Time
to High Level Output

tpHZ

Output Disable Time
to High Level Output

Conditions
Vee = 4.SV to 5.SV,
CL = 50pF,
R1 =
R2 = 5000.,
TA = Minto Max

soon,

From
(Input)

To
(Output)

A

Y

1~

1G
tpLZ

Output Disable Time
to Low Level Output

tPZH

Output Enable Time
to High Level Output

tPZL

Output Enable Time
to Low Level Output

tpHZ

Output Disable Time
from High Level Output

2G

2G
tpLZ

Output Disable Time
from Low Level Output

2-131

DM54ALS241A

DM74ALS241A
Units

Min

Max

Min

Max

3

31

3

11

ns

1

14

3

10

ns

5

33

7

21

ns

7

27

7

21

ns

2

13

2

10

ns

2

32

3

15

ns

7

38

7

21

ns

7

30

7

21

ns

2

17

2

10

ns

3

35

3

15

ns

y

y

y

y

DM54/74ALS240A

lAl

1""!~O_+-_1_8 lYl

lA2

I

"'~O_-+-_1_6

lY2

".0---t_1_4

lY3

_ _ _12_
tA4

1Y4

9 2Yl

2Al

7 2Y2

5 2Y3

3 2Y4

2A4

TLIF/6210-3

DM54174ALS241A

Iii
lAl

18 lYl

lA2

16 lY2

lA3

14 lY3

lA4

12 lY4

~---t~-g

..

2Yl

~~_..,..._7 2Y2

5
>---tr--

2Y3

~_ _ _ _
3

2Y4
TLIF/621 0-4

2·132

•

National
Semiconductor
Corporation

DM54ALS242B/DM74ALS242BI
DM54ALS243A/DM74ALS243A
Quad TRI-STATE® Bidirectional Bus Drivers
General Description

Features

These octal TRI-STATE. bus drivers are designed to provide the designer with flexibility in implementing a bus interface with memory, microprocessor, or communication systems. The ALS242B has inverting buffers, while the
ALS243A has non-inverting buffers. The direction enable
gating is configured with separate control over either buffer
direction and the two control buffers are complementary.
Connecting these control inputs to one common line implements single line direction control, while individual control
can put both buffar directions into TRI-STATE simultaneously (disabled state) or put both buffer directions into the
active state (data latch state). The TRI-STATE circuitry contains a feature that maintains the buffer outputs in TRISTATE (high impedance state) during power supply rampup or ramp-down. This eliminates bus glitching problems
that arise during power-up and power-down.

• Advanced low power oxide-isolated ion-implanted
Schottky TIL process
• Functional and pin compatible with the DM54174LS
counterpart
• Improved switching performance with less power dissipation compared with the DM54174LS counterpart
• Switching response specified into 500n and 50 pF load
• Switching response specifICations guaranteed over full
temperature and Vee supply range
• PNP input design reduces input loading
• Low level drive current:
54ALS = 12 mA, 74ALS = 24 rnA

Connection Diagram
Dual-In-Una Package
DAB- 1

U

14 ~Vcc

NC- 2

13 ~G8A

Al- 3

12 ~NC

A2- 4

11

~Bl

A3- 5

10

~B2

M- 6

9~B3

GND- 7

B ~B4
TLfFf6211-1

Top View
Order Number DM54ALS242BJ, DM54ALS243AJ,
DM74ALS242BM, DM74ALS242BN, DM74ALS243AM, DM74ALS243AN
See NS Packaga Number J14A, M14A or N14A

Function Table
Inputa

'ALS242B

'ALS243A

AtoB

AtoB

GAB

GBA

L

L

H

H

'8toA

BtoA

H

L

Isolation

Isolation

L

H

LatchAandB
(A = '8)

LatchAandB
(A = B)

2-133

fI

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
perametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devlclI8 are required,
contact the National Semiconductor Sales Office/
DIstributors for availability and specifications.

7V

Supply Voltage, Vee
Input Voltage
Dedicated Inputs
1/0 Ports

7V
5.5V

Operating Free Air Temperature Range
DM54ALS
- 55DC to + 125DC
DM74ALS
010 +70"C
Storage Temperature Range
-65DC to + 150"C

Recommended Operating Conditions
Symbol
Vee

DM54ALS242B, 243A

Parsmeter
. Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

10L

Low Level Output Current

TA

Operating Free-Air Temperature

DM74ALS242B, 243A

Unita

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

0.7

0.8

V

. -12

-15

mA

24

mA

70

DC

2

V

2

12
-55

125

0

Electrical Charac~erlstlcs over recommended operating free-air temperature (unless otherwise specified)
Symbol

Parameter

DM54ALS242B,243A

Conditions

Min
VIK

Input Clamp Voltage

VOH

High Lev~! Output

= 4.5V, II = -18mA
Vee = 4.5V to 5.5V 10H =
Vee = 4.5V
10H =

Typ

=

-0.4mA
-3mA
Max

V
V
V

2

2

V

Input Current at Max Vee = 5.5V, VI = 7V
Input Voltage
(5.5V for 1/0 Ports)

IIH

High Level Input
Current

Vee

=

5.5V, VI

IlL

Low Level Input .
Current.

Vee

=

5.5V, VIL

=

0.4V (Note 1)

10

Output Drive
Current

Vee

=

5.5V, Vo

=

2.25V

lee

Supply Current

Vee = 5.5V, ALS242B
Active Outputs High

Hi

Active Outputs Low

14

Outputs TRI-STATE

12

Vee = 5.5V, ALS243A
Active Outputs High

15

Active Outputs Low
Outputs TRI-STATE

74ALS (Max)

0.25

0.4

0.25

0.4

V

-

-

0.35

0.5

V

0.1

0.1

rnA

20

20

poA

-0.1

-0.1

mA

-112

mA

10

16

mA

26

14

21

mA

24

12

19

mA

30

15

25

mA

20

35

20

30

rnA

21

37

21

32

mA

2.7V (Note 1)

-30

-112

IIH and IlL include the TRI·STATE output currenta (loZH and IOZU.
2·194

-1.2

2.4

II

N_ 1: For the 1/0 'porta, the parameters

Units

Max

Vee - 2

VOL

=

Typ

2.4

Vee = 4.5V
10L = 54ALS (Max)

=

Min

Vee -2

Low Level Output
Voltage

10L

DM74ALS242B,243A

-1.2

Vee

10H

Max

20

-30

'ALS242B Switching Characteristics over recommended operating free-air temperature range (Note 1)
Symbol
tpLH

Parameter
Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpZH

Output Enable Time
to High Level Output

tpZL

Output Enable Time
to Low Level Output

tpHZ

Output Disable Time
to High Level Output

tpLZ

Output Disable Time
to Low Level Output

tPZH

Output Enable Time
to High Level Output

tPZL

Output Enable Time
to Low Level Output

tpHZ

Output Disable Time
from High Level Output

tpLZ

Conditions
Vee = 4.5V to 5.5V,
CL = 5OpF,
R1 = 5000,
R2 = 5000,
TA = Min to Max

From
(Input)

To
(Output)

AorB

BorA

GAB

GAB

GBA

GBA

54ALS242B

74ALS242B

Min

Max

Min

Max

2

15

2

11

ns

2

14

2

10

ns

4

22

4

18

ns

7

25

7

21

ns

2

16

2

14

ns

2

18

2

12

ns

4

22

4

18

ns

7

25

7

21

ns

2

16

2

14

ns

2

18

2

12

ns

Units

B

B

A

A

Output Disable Time
from Low Level Output

'ALS243A Switching Characteristics over recommended operating free-air temperature range (Note 1)
Symbol
tpLH

Parameter
Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpZH

Output Enable Time
to High Level Output

tPZL

Output Enable Time
to Low Level Output

tpHZ

Output Disable Time
to High Level Output

tpLZ

Output Disable Time
to Low Level Output

tpZH

Output Enable Time
to High Level Output

tPZL

Conditions
Vee = 4.5Vto5.5V,
CL = 50pF,
R1 = 5000,
R2 = 5000,
TA = Minto Max

From
(Input)

To
(Output)

AorB

BorA

GAB

GAB

GBA

tpLZ

GBA

Output Disable Time
from Low Level Output

Note 1: See Section 1 for test waveforms and output loads.

2·135

Min

Max

4

15

4

11

ns

4

15

4

11

ns

7

25

7

20

ns

7

25

7

20

ns

2

16

2

14

ns

3

27

3

22

ns

7

25

7

20

ns

7

25

7

20

ns

2

16

2

14

ns

3

27

3

22

ns

Units

B

A

Output Enable Time
Output Disable Time
from High Level Output

74ALS243A

Max

B

to Low Level Output
tpHZ

54ALS243A

Min

A

tI

..
..
•..
c:c

CI)

('II

Logle Diagrams

!i
c:c

DM54174ALS242B

.....
::::E
Q

Al

CI)

('II

!i

~::&
....lEIQ

..

A2

10 B2

A3

9 B3

('II
('II

!i
~
.....
::::E

....Q
lEI

..

A4

6

8 B4

('II
('II

TL/F/6211-2

!i
~
&I)

::::E
Q

DM54174ALS243A
lAB
Al

~-------t-t--~~--,-t----------9 B3

A4

..!...---~-D-:--1"T---- B4
TL/F/6211-3

2-136

.------------------------------------------------------------------.c
_

iii:

NaHonal
Semiconductor

I

CorporaHon

~C

DM54ALS244A/DM74ALS244A
Octal TRI-STATE® Bus Driver

iii:

t

General Description

Features

This octal TRI-STATE bus driver is designed to provide the
designer with flexibility in implementing a bus interface with
memory, microprocessor, or communication systems. The
output TRI-STATE gating control is organized into two separate groups of four buffers, and both control inputs enable
the respective outputs when set logic low. The TRI-STATE
circuitry contains a feature that maintains the buffer outputs
in TRI-STATE (high impedance state) during power supply
ramp-up or ramp-down. This eliminates bus glitching problems that arise during power-up and power-down.

• Advanced low power oxide-isolated ion-implanted
Schottky TIL process
• Functional and pin compatible with the DM54/74LS
counterpart
• Improved switching performance with less power dissipation compared with the DM54174LS counterpart
• Switching response specified into 5000 and 50 pF load
• SWitching response specifications guaranteed over full
temperature and Vee supply range
• PNP input design reduces input loading
• Low level drive current:
54ALS = 12 mA, 74ALS = 24 mA

Connection Diagram
Dual-In-Une Package
vee 2G

10

1A 1

1Y1

2A4

1Y2

2A3

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1 GND
TUF/6212-1

Top View
Order Number DM54ALS244AJ, DM74ALS244AWM or DM74ALS244AN
See NS Package Number J20A, M20B or N20A

Function Table
Input

G
L
L

H

Output
A

Y

L

L

H
X

H

Z

H - High Level Logic State
L = Low Level Logic State
X = Don'l Care (EHher Low or High Level logic Statal

z = High Impedance (Off) State

2-137

~
~

Absolute Maximum Ratings
Note: The "Absolute Msximum Ratings" are those valU8S
beyond which the safety of the device cannot be guarsnt88d. The device should not be operated at thesellm/ts. The
parametric values defined In the "El8ctrical Charscf8ristics"
table are not guarantaed af the absolute msximum ratings.
The "R8COfTImended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vee
7V
Input Voltage
7V
Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
Oto +700C
Storage Temperature Range
-65·Cto + 1500C

Recommended Operating Conditions
Symbol

DM54ALS244A

Parameter

DM74ALS244A

Unlta

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.7

0.8
-15

mA

24

mA

70

·c

2

V

2

10H

High Level Output Current

-12

10l

Low Level Output Current

12

TA

Operating Free-Air Temperature

-55

125

V

0

V

Electrical Characteristics over recommended operating free air temperature (unless otherwise specified)
Symbol

Parameter

DM54ALS244A

Conditions

Min
VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

= 4.5V,11 = -18 mA
Vee = 4.5Vto5.5V 10H = -0.4mA
Vee = 4.5V
10H = -3mA
10H = Max
Vee = 4.5V
10l = 54ALS (Max)
10l = 74ALS (Max)
Vee = 5.5V, VI = 7V

Typ

Max

DM74ALS244A
Min

Typ

-1.5

-1.5

Vee

Units

Max
V

Vee- 2

Vee- 2

V

2.4

2.4

V

2

2

V

VOL

Low Level Output
Voltage

II

Input Current at Max
Input Voltage

IIH

High Level Input
Current

Vee

= 5.5V, VI = 2.7V

IlL

Low Level Input
Current

Vee

= 5.5V, Vil = 0.4V

10

Output Drive
Current

Vee

= 5.5V, Vo = 2.25V

10ZH

High Level TRI·STATE Vee
Output Current

= 5.5V, Vo = 2.7V

10Zl

Low Level TRI·STATE
Output Current

Vee

= 5.5V, Vo = 0.4V

lee

Supply Current

Vee = 5.5V
Outputs High

9

15

9

15

mA

Outputs Low

15

24

15

24

mA

Outputs TRI·STATE

17

27

17

27

mA

0.25

0.4

0.25

0.4

V

-

-

0.35

0.5

V

0.1

0.1

rnA

20

20

JAoA

-0.1

-0.1

mA

-112

mA

20

20

JAoA

-20

-20

JAoA

-30

2·138

-112

-30

Switching Characteristics over recommended operating free-air temperature range (Note 1)
Symbol

Parameter

From
(Input)

To
(Output)

tpLH

Propagation Delay Time
Low to High Level Output

A

y

tpHL

Propagation Delay Time
High to Low Level Output

A

Y

tpZH

Output Enable Time
to High Level Output

G

y

tPZL

OUtput Enable Time
to Low Level Output

G

Y

tpHZ

Output Disable Time
from High Level Output

G

y

tpLZ

Output Disable Time
from Low Level Output

G

y

54ALS244A

Conditions
Vee = 4.5Vto5.5V,
CL = 50pF,
R1 = 500n,
R2 = 500n,
TA = Min to Max

Min

Max

1

18

3

10

ns

3

13

3

10

ns

1

29

7

20

ns

1

27

7

20

ns

2

12

2

10

ns

1

21

3

13

ns

Logic Diagram
DM54174ALS244B

lG~
18 lYl

lA2.y>::

16 lY2

lA3.y>::

14 lY3

lA4

211

8

12 lY4

2!....0[>----

2Al~
2A2~

9 2Yl

7

2Y2

2A3~

5 2Y3

2A4 17

3 2Y4
TLlF/6212-2

2-139

Units

Max

Note 1: See Section 1 for test wavefonns and output load.

lAl.y>::

74ALS244A

Min

Ij Corporation
Semiconductor
Nattonal

DM54ALS245A/DM74ALS245A
Octal TRI-STATE® Bus Transceivers
General Description

Features

This advanced low power Schottky device contains 8 pairs
of TRI-STATE logic elements configured as octal bus transceivers. These circuits are designed for use in memory, microprocessor systems and in asynchronous bidirectional
data buses. Two way communication between buses is controlled by the (DIR) input. Data transmits either from the A
bus to the B bus or from the B bus to the A bus. Both the
driver and receiver outputs can be disabled via the (~) enable input which causes outputs to enter the high impedance mode so that the buses are effectively isolated.

• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Non-inverting logic output
• Glitch free bus during power up and down
• TRI-STATE outputs independently controlled on A and
B buses
• Low output impedance to drive terminated transmission
lines to 1330
• Switching response specified into 5000/50 pF
• Specified to interface with CMOS at VOH = Vee - 2V
• PNP inputs to reduce input loading
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Une Package

D

~

120

i 19

~

u

~

u

~

H

§

i18 I17 III T15 I14 "1"13

~

~

~

~

~

I~

~

~

~

T12
~

H

Tll

~

I~ I~

i'
~

'r
1

~

rrrrrrrr
12

~

13

14

15

16

iii i

17

i

IS

~

19

i

•

110

Order Number DM54ALS245AJ or DM74ALS245AWM, N
See NS Package Number J20A, M20B or N20A

Function Table
Control
Inputs

Operation

G

DIR

L
L
H

L
H

B Data to A Bus
A Data to B Bus
Hi-Z

X

H = High Logic Level
L = Low logic Level
X = Either High or Low Logic Level

2-140

TUF/6213-1

Absolute Maximum Ratings
If Mllltary/Aerospace specified devices are required,
contaet the National Semiconductor Sales Offlcel
Dlstriltut.... for availability and speclflcatlons_
Supply Voltage

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarenteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Charecteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V

Inpul Voltage
Control Inputs
110 Ports

7V
5.5V

Operating Free Air Temperature Range
DM54ALS
- 55'C to + 125'C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65'Cto + 150"C

ReHlRmended Operating Conditions
Symbol

DM54ALS245A

Parameter

DM74ALS245A

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

IOH

High Level Output Current

-12

-15

mA

IOL

Low Level Output Current

12

24

mA

TA

Operating Free Air
Temperature

70

'C

2

V

2

-55

125

V

0

Electrical Characteristics
over reeommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25'C.
SymbGI

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,IIN = -18 rnA

VOH

High Level Output Voltage

Vee = 4.5V,IOH = -3 mA

Min

IOH = -0.4 mA, Vee = 4.5V to 5.5V

II

Low Level Output Voltage

Vee = 4.5V

Inpul Current at Max
Inpul Voltage

Vee = 5.5V

Max
-1.5

Vee = 4.5V, IOH = Max

VOL

Typ

Units

V

2.4

3.2

V

2

2.3

V
V

Vee- 2

54174ALS
IOL = 12mA

0.25

0.4

V

74ALS
IOL = 24mA

0.35

0.5

V

VIN = 7V
VIN = 5.5V

I Control Inputs
I A or B Ports

0.1

mA

0.1

IIH

High Level Input Current

Vee = 5.5V, VIN = 2.7V

20

p.A

IlL

Low Level Input Current

Vee = 5.5V, VIN = 0.4V

-0.1

mA

10

Output Drive Current

Vee = 5.5V, VOUT = 2.25V

lee

54ALS254A Supply Current

Vee = 5.5V

lee

74ALS254A Supply Current

Vee = 5.5V

-112

mA

Oulputs High

-30
30

48

mA

Outputs Low

38

60

mA

TRI-STATE

38

63

mA

Outputs High

30

45

mA

Outputs Low

36

55

mA

TRI-STATE

38

58

mA

2-141

Switching Characteristics over recommended operating free air temperature range (Notes 1 and 2)
Symbol

Parameter

tpLH

Propagation Delay Time
High-to-Low Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

tPZL

Output Enable Time
to Low Level

tpZH

Output Enable Time
to High Level

tpLZ

Output Disable Time
from Low Level

tpHZ

Output Disable Time
from High Level

Circuit
Configuration

DM54ALS245A

DM74ALS245A

Min

Max

Min

Max

1

19

3

10

ns

1

14

3

10

ns

2

29

5

20

ns

2

30

5

20

ns

2

30

4

15

ns

2

14

2

10

ns

IN~OUT

.~

Note 1: See Section 1 for test waveforms end output load.
Note 2: Switching chenscteristic conditions are Vee = 4.5V to 5.5V. RL

AORB
OUT

= 5oon. CL = 50 pF.

2-142

Units

,----------------------------------------------------------------.0
_

iI:

National

E

Semiconductor
Corporation

i....
ell

....o

DM54ALS251/DM74ALS251 TRI-STATE®
1 of 8 Line Data SelectorIMultiplexer

iI:

......

General Description

Features

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a
unique three-bit binary code at the Select inputs. Two complementary outputs provide both inverting and non-inverting
buffer operation. An Output Control input is provided which,
when at the high level, places both outputs in the high impedance Off state. In order to prevent bus access conflicts,
output disable times are shorter than output enable times.
The Select input buffers incorporate internal overlap features to ensure that select Input changes do not cause invalid output transients.

• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Switching performance is guaranteed over full temperature and Vee supply range
• Pin and functional compatible with LS family counterpart
• Improved output transient handling capability
• Output
control
circuitry
incorporates
power-up
TRI-STATE feature

Connection Diagram

Function Table
Inputs

Dual-ln-L1ne Package

Outputs

C

Select
B

Strobe

A

S

y

X

X

X

Z

Z

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

H
L
L
L
L
L
L
L
L

DO

DO
01

= High Level, L = Low Level, X = Don't Care
Z = High Impedance (Off)
DO thru 07 = The Level of the Respective 0 Input
H

2-143

01
02
03

W

i52

05

03
04
05

De

De

07

07

D4

§....

Absolute Maximum Ratings
Note: The "Absolute Msximum Ratings" are thoss. values
beyond which the safety of the device cannot beguarenteed. The device should not be operated at thes81im;~. The
parametric values defined in the "E/ectricsl Chara~tics"
table are not guaranteed at the absolute msximum f"{ftings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office!
Dletributors for availability and specifications.

Supply Voltage, Vee
7V
Input Voltage
7V
Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
DM54ALS251
- 55°C to + 125°C
DM74ALS251
O"Cto +70"C
Storage Temperature Range
- 65°C to + 15O"C

Recommended Operating Conditions
Symbol

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS251

DM54ALS251

Parameter

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V
V

2

2

.>

Vil

Low Level Input Voltage

0.7

0.6

V

IOH

High Level Output Current

-1

-2.6

rnA

24

rnA

IOl

Low Level Output Current

TA

Free Air Operating Temperature

12
-55

125

0

70

°C
~."""".,,

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

= 5V. TA = 25°C.

Min

Conditions

= 4.5V,IIN = -18 mA
Vee = 4.5V. IOH = Max
10H = 400 p,A. Vee = 4.5V to 5.5V
54174ALS
Vee = 4.5V
IOl = 12mA

Typ

Vee

2.4

Mq

Unlta

-1.5

V

3.2

V
V

Vee- 2

74ALS
IOl = 24mA

0.25

0.4

V

0.35

0.5

V

0.1

rnA

= 5.5V. VIH = 7V

II

Input Current at
Max Input Voltage

Vee

IIH

High Level Input Current

Vee

5.5V. VIH

20

p,A

III

Low Level Input Current

Vee

5.5V. VIN

-0.1

mA

10

Output Drive Current

-112

rnA

10ZH

Off-State Output
Current. High Bias

20

p,A

10ZL

Off-State Output
Current. Low Bias

Vee

= 5.5V. VOUT = 0.4V

-20

p,A

lee

Supply Current

Vee

= 5.5V. Inputs = GND
= 4.5V. Vee = 5.5V

=
=
Vee =
Vee =

= 2.7V
= 0.4V
5.5V. VOUT = 2.25V
5.5V. VOUT = 2.7V

Inputs

2-144

-30

Enabled

7

10

Disabled

9.4

14

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

From

tpLH

Propagation Delay Time
Low to High Level Output

Select

tpHL

Propagation Delay Time
High to Low Level Output

Select

tpLH

Propagation Delay Time
Low to High Level Output

Select

tpHL

Propagation Delay Time
High to Low Level Output

Select

tpLH

Propagation Delay Time
Low to High Level Output

Data

tpHL

Propagation Delay Time
High to Low Level Output

Data

tpLH

Propagation Delay Time
Low to High Level Output

Data

tpHL

Propagation Delay Time
High to Low Level Output

Data

tpZH

Output Enable Time
to High Level

Output
Control

tPZL

Output Enable Time
to Low Level

Output
Control

tpZH

Output Enable Time
to High Level

Output
Control

tpZL

Output Enable Time
to Low Level

Output
Control

tpHZ

Output Disable Time
from High Level

Output
Control

tpLZ

Output Disable Time
from Low Level

Output
Control

tpHZ

Output Disable Time
from High Level

Output
Control

Output Disable Time
from Low Level

Output
Control

tpLZ

To

y

Conditions
Vee = 4.5V
t05.5V
CL = 50pF
RL = 5000

DM54ALS251

DM74ALS251

Min

Max

Min

Max

1

21

5

18

ns

8

34

8

24

ns

5

38

8

24

ns

7

26

7

23

ns

2

15

2

10

ns

3

23

3

15

ns

3

25

3

15

ns

3

20

3

15

ns

3

21

3

15

ns

3

19

3

15

ns

3

21

3

15

ns

3

19

3

15

ns

2

12

2

10

ns

1

18

1

10

ns

2

12

2

10

ns

1

18

1

10

ns

Units

W

y

W

y

W

y

W

Note 1: See Section 1 for test wave!onns and output load.

2·145

!
...
.....
i

I...

_

;
;
~
....

r-----------------------------------------------------------------------~

Logic Diagram
OUTPUT 7_....
COlT Rlil~
DO 4

=-=r-

~

--

01 3

---f
02 2

~
03 1

r----r

DATA
INPUTS

04 15

r1
05

~
r;:l

rt~

TV

OUTPUTW

14

)--

.--

-f
DB 13

.....r07

12

i

A~

"

DATA
SELECT
IIINARYI

I~
"

I

1 ,....

..........

-r

A

B

1 .......
,.....

I

C

l..£~

I

.....

C
TL/F/8214-2

2·148

.-------------------------------------------------------------------,c
Nal1onal

~ Semiconductor

PRELIMINARY

Corporation

DM54ALS253/DM74ALS253 TRI-STATE® Dual 1 of 4 Line
Data SelectorIMultiplexer
General Description

Features

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-four data sources as a result of a unique
two-bit binary code at the Select Inputs. Each of the two
Data Selector/Multiplexer circuits have their own separate
Data and Output Control inputs and a non-inverting TRISTATE output buffer. The Output Control inputs. when at
the high level. place the corresponding output in the high
impedance Off state. In order to prevent bus access conflicts. output disable times are shorter than output enable
times. The Select input buffers incorporate internal overlap
features to ensure that select input changes do not cause
invalid output transients.

• Advanced oxide-isolated. ion-implanted Schottky TIL
process
• Switching performance is guaranteed over full temperature and Vee supply range
• Pin and functional compatible with LS family counterpart
• Improved output transient handling capability
• Output control circuitry incorporates power-up TRISTATE feature

Connection Diagram

Function Table
Select
Inputs

Dual-In-Une Package

""WIl
II

I

SELlCTB I

....

. . 11-

...

...

NI

....

.--

lca-'I--

'lao
....

r-

'--

II:!.J ..... t-

r-

14 IELlCTI

i

lel..J l-

't---+......--11

I

11:0.11OUTPUTYI I

1-1-

1

....

'"

tll-lCl

IIPUTI

A

CO

C1

C2

C3

G

y

X

X

X
L

X
X
X
X
X

X
X
X
X
X
X
X

Z

L
L

X
X
X

H

L
L
L
L

H
H
L
L

H
H

H
X
X
X
X
X
X

L

H
X
X
X
X

L

H
X
X

H = High Level. L = Low Level, X

1-1- ~lCD

1.J....

Output

L

H

L
L
L
L
L
L
L
L

L

H
L

H
L

H
L

H

Address Inputs A and B are common to both sections

DATI

iit--.....---1i

Output
Control

B

H
H
H
H

l!La

•'t-....,H+--1·

DATI

"'UTI

......

II

Data Inputs

I auTM yz

TLlF/6215-1

Order Number DM54ALS253J, DM74ALS253M or
DM74ALS253N
See NS Package Number J16A, M16A or N16A

2-147

= Don'l Care, Z = High Impedance

iii:

t

~i

;

i

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vee
7V
Input Voltage
7V
Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
DM54ALS
- 55°C to + 125°C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65"Cto + 150"C

parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

DM74ALS253

DM54ALS253

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

Unlta

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2

Vil

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-1

-2.6

mA

24

mA

70

°C

10l

Low Level Output Current

TA

Free Air Operating Temperature

12
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

II

Input Current at
Max Input Voltage

Condltlona

= 4.5V,IIN = -18 mA
Vee = 4.5V, 10H = Max
10H = 400 /LA, Vee = 4.5V to 5.5V
Vee = 4.5V

= 5V, TA = 25°C.

Min

Typ

Vee

2.4

3.2

High Level Input Current
Low Level Input Current

10

Output Drive Current

10ZH

Off-State Output
Current, High Bias

10Zl

Off-State Output
Current, Low Bias

Vee

= 5.5V, VOUT = 0.4V

lee

Supply Current

Vee

= 5.5V

V
V
V

Vee- 2
0.25

0.4

V

74ALS
10l = 24mA

0.35

0.5

V

0.1

mA

= 5.5V, VIN = 2.7V
= 5.5V, VIN = 0.4V
Vee = 5.5V, VOUT = 2.25V
Vee = 5.5V, VOUT = 2.7V

IIH

Units

54174ALS
10l = 12mA

= 5.5V, VIN = 7V

III

Max
-1.5

Vee

Vee

20

/LA

Vee

-0.1

mA

-112

mA

20

!LA

-20

/LA

-30

Output High

2-148

6.5

12

Output Low

6.5

12

Output Disabled

7.5

14

mA

Switching Characteristics
over recommended operating free air temperature range (Note 1). All typical values are measured at Vee

Symbol

From (Input)
To (Output)

Parameter

Conditions

=

5V, TA

=

25°C.

DM54ALS253

DM74ALS253

Min

Max

Min

Max

5

30

5

21

ns

5

27

5

21

ns

2

15

2

10

ns

3

18

3

14

ns

Vee = 4.5V to 5.5V
CL = 50pF
RL = 5000

Units

tpLH

Propagation Delay Time
Low to High Level Output

SelecttoY

tpHL

Propagation Delay Time
High to Low Level Output

Select to Y

tpLH

Propagation Delay Time
Low to High Level Output

DatatoY

tpHL

Propagation Delay Time
High to Low Level Output

DatatoY

tpZH

Output Enable Time
to High Level Output

Output Control
toY

3

20

3

14

ns

tpZL

Output Enable Time
to Low Level Output

Output Control
toY

2

19

4

16

ns

tpHZ

Output Disable Time
from High Level Output

Output Control
toY

2

12

2

10

ns

tpLZ

Output Disable Time
from Low Level Output

toy

2

18

2

14

ns

Output Control

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram
I
OUTPUT
COIITilOl WI

..J":l
...

=I ) - -

ICO 6

ICI 5

,.... .... :::::J

ICt 4

1--1

DATA I <

YI

}--

IC3 3

SELECT

~OOT~T

C'

A 14

.....

...

1 ..........

........

.........

I

2CD 1O

fl.)-

2CI "
DATU

t::I

te3 13
OUTPUT
CO.TROl

15
6t

~OIITPUT

E:[)--I

tCt 12

--I-

n

}--

.......

,...
TL/F/6215-2

2·149

_

National
Semiconductor

Corporation

DM54ALS/DM74ALS257, 258 TRI-STATE®
Quad 1-of-2-Line Data Selectors/Multiplexers
General Description

Features

These data selectors/multiplexers contain inverters and
drivers to supply full on-chip data selection to the four TRISTATE outputs that can interface directly with data lines of
bus-organized systems. A 4-bit word selected from one of
two sources is routed to the four outputs. The ALS257 presents true data whereas the ALS258 presents inverted data
to minimize propagation delay time.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TIL counterpart
• Improved AC performance over Schottky and low powerSchottkycoumerparts
• TRI-STATE buffer-type outputs drive bus lines directly
• Expand any data input point
• Multiplex dual data buses
• General four functions of two variables (one variable is
common)
• Source programmable counters

This TRI-STATE output feature means that n-bit (paralleled)
data selectors with up to 258 sources can be implemented
for data buses. It also permits the use of standard TIL registers for data retention throughout the system.

Connection Diagram
Dual-In-Una Package
OUTPUT IM'UTS OUTPUT INPUTS OUTPUT
vccCONTROL4i'"'4i

l~e

115 114 113

4Y
112

3A3is
111

1,0

3Y

II

! I I l I I
Ii

4A

48

4Y

3A

38

s

3Y
1A

1B

1Y

2A

I I T I
1
12
SELECT 1A

13
1B

14
1Y

15
2A

2B

2Y

I Y
Ie 17 Is
2B

2Y

"iNiiiirS OUTPUT INPI:iii' OUTPUT

GND
TL/F/6227-1

Order Number DM54ALS257J, DM54ALS258J,
DM74ALS257M, DM74ALS258M, DM74ALS257N, DM74ALS258N
See NS Package Number J16A, M16A or N16A

Function Table
Inputs

OulputY

Output
Control

Select

A

B

ALS257

ASL258

H

X

X

L
L
L
L

L
L

L

Z
L

H

H

X
X
X

H

L

H
H

X
X

L

L

H

H

H

L

H = High Level, L = Low Level, X = Don't care
Z = High Impedance (off)

2-150

Z

Absolute Maximum Ratings
Note: TfIB "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be gusranteed. The device should not be operated at tfIBsa limits. The

If Mllitary/Aerospace specified devices are required,
contact the National Semiconductor Seles OffIcel
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

parametric values defined in tfIB "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will dtlfine
the conditions for actusl dtlvice operation.

Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
DM54ALS
- 55DC to + 125DC
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65"Cto +15O"C

Recommended Operating Conditions
Symbol

DM54ALS257, 258

Parameter

DM74ALS257,258

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

2

2

V

10H

High Level Output Current

-1

-2.6

rnA

10L

Low Level Output Current

12

24

TA

Free Air Operating Temperature

rnA
DC

-55

125

0

70

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

Conditions

= 4.5V,II =
Vee = 4.5V
VIL = Max
Vee

10H
VOL

= -0.4mA

74ALS
10H = -2.6mA

2.4

3.3

V

54/74ALS

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

Vee

20

Vee

-0.1

/J- A
mA

-112

mA

20

IJ.A

-20

IJ.A

= 5.5V, VIH = 7V

IlL

Low Level Input Current

10

Output Drive Current

10ZH

Off·State Output
Current, High Level
Voltage Applied

= 5.5V, VIH = 2.7V
= 5.5V, VIL = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V. VIH = 2V
Vo = 2.7V

leez

Off·State Output
Current, Low Level
Voltage Applied

Vee = 5.5V, VIH
Vo = 0.4V

Supply
Current

Vee = 5.5V
Outputs Open

Supply
Current
Supply
Current

V

Vee- 2

54174ALS
10L = 12mA

High Level Input Current

leeL

V
V

IIH

ALS258

Units

3.2

Vee

ALS257

Max
-1.5

2.4

Input Current at Max
Input Voltage

ICCH

Typ

54ALS
10H = -1 rnA

II

10ZL

= 5V, TA = 25DC.

-18rnA

Vee = 4.5V
VIH = 2V

Low Level Output
Voltage

Min

-30

= 2V
Outputs High
Outputs Low

ALS257
ALS258
ALS257

Outputs Disabled

ALS258

2·151

3

6

mA

2.5

4

mA

8

12

mA

7

11

mA

9

14

mA

8

13

mA

'ALS257 Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Conditions
Vee = 4.5V to 5.5V
CL = 50pF
RL = 5000

From

To

Data

Any
Y

Data

Any

y

Propagation Delay Time
Low to High Level Output

Select

tpHL

Propagation Delay Time
High to Low Level Output

Select

tZH

Output Enable Time
to High Level

Output
Control

Any

tZL

Output Enable Time
to Low Level

Output
Control

Any

lHz

Output Disable Time
from High Level

Output
Control

Any

tLZ

Output Disable Time
from Low Level

Output
Control

Any

tpLH

Any

y
Any

y
y
y
y
y

DM54ALS257

DM74ALS257

Min

Max

Min

Max

2

12

2

10

ns

2

14

2

12

ns

4

21

4

18

ns

5

25

5

22

ns

4

20

4

16

ns

5

22

5

18

ns

2

12

2

10

ns

3

35

3

15

ns

Units

'ALS258 Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Conditions
Vee = 4.5V to 5.5V
CL = 50pF
RL = 5000

From

To

Data

Any
Y

Data

Any

y
Any

tpLH

Propagation Delay Time
Low to High Level Output

Select

tpHL

Propagation Delay Time
High to Low Level Output

Select

tZH

Output Enable Time
to High Level

Output
Control

Any

tZL

Output Enable Time
to Low Level

Output
Control

Any

tHZ

Output Disable Time
from High Level

Output
Control

Any

tLZ

Output Disable Time
from Low Level

Output
Control

Any

y
Any

y

Note 1: See Section 1 for test waveforms and output losd.

2-152

y
y
y
y

DM54ALS258

DM74ALS258

Min

Max

Min

Max

1

12

2

8

ns

2

9

2

7

ns

3

28

3

20

ns

8

25

5

25

ns

5

20

5

18

ns

5

21

5

18

ns

2

12

2

10

ns

3

37

3

18

ns

Units

Logic Diagrams
54174ALS257

TLlF/6227-2

54174ALS258

TUF/6227-3

2-153

IJ

Nalional
Semiconductor

Corporation

DM54ALS273/DM74ALS273
Octal 0-Type Edge-Triggered Flip-Flops with Clear
General Description

Features

These monolithic, positive-edge-triggered flip-flops utilize
TTL circuitry to implement Ootype flip-flop logic with a direct
clear input.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Buffer-type outputs and improved AC offer significant
advantage over 'LS273.
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with 'LS273.

Information at the D inputs meeting the setup requirements
is transferred to the Q outputs on the positive-going edge of
the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of
the positive-going pulse. When the clock input is at either
the high or low level, the D input signal has no effect at the
output.

Connection Diagram
Dual-tn-Une Package

1
CLEAR
TUFI6216-1

Oreler Number DM54ALS273J, DM74ALS273WM or DM74ALS273N
See NS Package Number J20A, M20B or N20A

2-154

Absolute Maximum Ratings
If MilltarylAeroepace specified devices are reqUired,
contact the NatIonal Semiconductor Sel.. OffIcel
DIstributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
-55"C to + 125"C
DM74ALS
O"C to + 70"C
Storage Temperature Range
-65·Cto + 150"C

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

DM54ALS273

Parameter

DM74ALS273

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

IOH

High Level Output Current

-1

-2.6

mA

IOL

Low Level Output Current

12

24

mA

fOLK

Clock Frequency

35

MHz

tw(OLK)

Width of Clock Pulse

tw

Width of Clear Pulse

tsu

Data Setup Time

2

2

0

30

V

0

High

16.5

14

ns

Low

18.5

14

ns

Low

10

10

ns

10t

10t

1St

15t

Clear Inactive
tH

Data Hold Time

ot

TA

Free Air Operating Temperature

-55

ns
ns

ot
125

0

70

·C

The (t) arrow indica1es \he positive edge of the Clock is used for reference.

Electrical Characteristics

over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25"C.
Symbol

Pararnster

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V
VIL = VILMax

VOL

Low Level Output
Voltage

Min

Typ

Max

Units

-1.5

V

54ALS
IOH = -1 mA

2.4

3.2

V

74ALS
IOH = -2.6mA

2.4

3.3

V

IOH = -400 p.A

54174ALS

Vee = 4.5V
VIH = 2V

54174ALS
10L = 12mA

Vee- 2

V
0.25

0.4

V

74ALS
IOL = 24mA

0.35

0.5

V

0.1

mA

II

Input Current @ Max.
Input Voltage

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

p.A

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.2

mA

10

Output Drive Current

Vee = 5.5V

Vo = 2.25V

-112

mA

lee

Supply Current

Vee == 5.5V
Outputs Open

Outputs High

11

20

mA

Outputs Low

19

29

mA

Vee = 5.5V, VIH = 7V

2-155

-30

Switching Characteristics over recommended operating free air tel1)peraturerangl! (Note 1).
Symbol

Parameter

Conditions

From'

'To

o'PA'S.ALS:m
Min'

fMAX

Maximum Clock Frequency

tpHL

Propagation Delay Time
High to Low Level Output

tpLH
tpHL

Vee = 4.5Vto 5.5V
RL = 500n
CL =50pF

30

"Min

Units

Milx

35

MHz

Any 0

4

24

4

18

ns

Propagation Delay Time
Low to High Level Output

Clock

Any 0

2

20

2

12

ns

Propagation Delay Time
High to Low Level Output

Clock

Any 0

"3-

1,7

3

15

ns

waveforms and ou1pu\ load.

Function Table (Each Flip-Flop)
Inputs

t

.. ,DM74ALS273

Clear

Note 1: See SectIon 1 for _

L=

",·Max

Clear

Clock

0

L
H
H
H

X

t
t

X
H
L
X

L

Output
Q
L
H
L

00

Low State, H = High State, X = Don't Care
= Positive Edge Transition, 00 = Previous Condition of Q

2-156

c
Logic Diagram

==

UI

~

3

10

Ii)
N

.....
W
.....
C
.....
==

2 10

20

...

4

~

5

Ii)

20

N

.....
W

7

30

6 30

40

I
9

liD

40

13
12 60

6D 14
15 60

70 17
18 70

8D II
19 BQ
CLOCK 11
CLEAR 1
TLIFI6216-2

2-157

PRELIMINARY

National

_

.

Semiconductor

Corporation

DM54ALS352/DM74ALS352 Dual 1 of 4 Line
Data SelectorIMultlplexer
General Description

Features

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-four data sources as a result of a unique
two-bit binary code at the Select inputs. Each of the two
Data Selector/Multiplexer circuits have their own separate
Data and Strobe inputs and an inverting output buffer. The
Strobe inputs, when at the high level, disable their associated data inputs and force the corresponding output to the
high state. The Select input buffers incorporate internal
overlap features to ensure that select input changes do not
cause invalid output transients.

• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Switching performance is guaranteed over full temperature and Vee supply range
• Pin and functional compatible with the LS family coun-

terpart
• Improved output transient handling capability

Connection Diagram
Dual-In-L1ne Package

.

DATA INPUTS

STROBE B
DATA INPUTS

10 SELECT

TlIF/6218-1

Order Number DM54ALS352J, DM74ALS352M, or DM74ALS352N
Sea NS Package Number J16A, M16A or N16A

Function Table
SaIact

Datalnputa

Inputa

Strobe

Output

B

A

co

C1

C2

C3

G

y

X

X
L
L

X
X
X
L
H
X
X
X
X

X
X
X
X
X

X
X
X
X
X
X
X

H

L
L
L
L

X
L
H
X
X
X
X
X
X

H
H

H
H
H
H

H
H
L
L
H
H

L

H
X
X

L

H

Select Inputs A and B are common to both sections
H = High Laval, L = Low Level, X - Don'! Care

2-158

L
L

L
L
L
L
L
L

L

H
L
H
L
H
L

Absolute Maximum Ratings
It Military/Aerospace specified devices are required,
contact the National Semiconductor Salee Office/
Distributors for availability and specifications.

Note: The "Absolute Msximum Ratings" are those values
beyond which the safety of the device cannot be guarenteed. The device should not be operated at thesalimits. The
paremetric values defined in the "Electrical Characteristics ..
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
-55"Cto + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150·C

Recommended Operating Conditions
Symbol

DM74ALS352

DM54ALS352

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V

2

V

VIL

Low Level Input Voltage

0.7

0.8

V

IOH

High Level Output Current

-1

-2.6

mA

24

mA

70

·c

IOL

Low Level Output Current

TA

Free Air Operating Temperature

12
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parametar

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Conditions

= 4.5V,IIN = -18 mA
Vee = 4.5V, IOH = Max
IOH = -400 /-LA, Vee = 4.5V to 5.5V
,.
Vee = 4.5V

= 5V, TA = 25"C.

Min

Typ

Vee

II

Input Current at
Max Input Voltage

Vee

2.4

Max

Units

-1.5

V

3.2

V
V

Vee- 2
54/74ALS
IOL = 12mA

0.25

0.4

V

74ALS
IOL = 24mA

0.35

0.5

V

0.1

mA

= 5.5V, VIN = 7V

= 5.5V, VIN = 2.7V
= 5.5V, VIN = 0.4V
Vee = 5.5V, VOUT = 2.25V
Vee = 5.5V (Note 1)

IIH

High Level Input Current

Vee

20

p.A

IlL

Low Level Input Current

Vee

-0.1

mA

10

Output Drive Current

-112

mA

lee

Supply Current

10

mA

Note 1: Icc Is measured with data and salect inpuls at 4.5V. Ginputs grounded and outputs open.

2·159

-30
6.5

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

From (Input)
To (Output)

Parameter

Conditions

DM54ALS352

DM74ALS352

UnIW

Min

lin

Min

MIIx

5

32

5

24

n8

5

24

5

21

n8

tpLH

Propagation Delay Time
Low to High Level Output

Select
toY

tpHL

Propagation Delay Time
High to Low Level Output

Select
toY

tpLH

Propagation Delay Time
Low to High Level Output

Data
toY

3

24

3

18

ns

tpHL

Propagation Delay Time
High to Low Level Output

Data
toY

2

15

2

13

ns

tpLH

Propagation Delay Time
Low to High Level Output

Strobe
toY

4

28

4

18

ns

tpHL

Propagation Delay Time
High to Low Level Output

Strobe
toY

4

24

4

20

ns

Vee = 4.5Vto5.5V
CL=50pF
RL = 5000

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram
I

STROlE 81

8

rICO

......
-.....

---t

)--

lCI 5

...I.

,

DATA I

7 OUTPUT
Y1

lC2 4

J-

lC3 3

SELECT

.........

{"

A 14

1

Jooo.

....

I

......
....
-

......
...

2CO 10

)-2&1 11
--""

DATA 2

,

2&2 12

2&3 13
"STROlE 02 15

9 OUTPUT
Y2

..... ~

........

}-

-

TLlF/8218-2

2·160

_

National

Semiconductor
Corporation

DM54ALS353/DM74ALS353 TRI-STATE® Dual
1 of 4 Line Data SelectorIMultiplexer
General Description

Features

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-four data sources as a result of a unique
two-bit binary code at the Select inputs. Each of the two
Data Selector/Multiplexer circuits have their own separate
Data and Output Control inputs and an inverting TRI-STATE
output buffer. The Output Control inputs, when at the high
level, place the corresponding output in the high impedance
Off state. In order to prevent bus access conflicts, output
disable times are shorter than output enable times. The Select input buffers incorporate internal overlap features to ensure that select input changes do not cause invalid output
transients.

• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Switching performance is guaranteed over full temperature and Vee supply range
• Pin and functional compatible with LS family counterpart
• Improved output transient handling capability
• Output control circuitry incorporates power-up TRISTATE feature

Connection Diagram
Dual·ln·Llne Package

TUF/6219-1

Order Number DM54ALS353J or DM74ALS353M, N
See NS Package Number J16A, M16A or N16A

Function Table
Select
Inputs

Data Inputs

Output
Control

Output

y

B

A

CO

C1

C2

C3

G

X

X

X
L

X
X
X
X
X

X
X
X
X
X
X
X

Z

L
L

X
X
X

'H

L
L
L
L

L
L
L
L
L
L
L
L

H

H
H
H
H

H
H
L
L

H
H

H
X
X
X
X
X
X

L

H
X
X
X
X

L

H
X
X

L

H

Address Inputs A and B are common to bolh sections
H = High Level, L = Low Level, X = Oon'l Care
Z = High Impedance Slats

2·161

L

H
L

H
L

H
L

Absolute Maximum Ratings
Note: The "Absolute MsxJmum Ratings" Sf9 those va/UBS
beyond which the SIlfety of the devlcs cannot be gusran-

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

teed. The devlcs should not be operated at these limits. The
psrsmetric values defined in the "EIIJctricsI ChsrsctBristJcs"
table ara not gusrsnteBd at the absoIutB msxImum ratings.
The ''Recoml1lBflded Operating Conditions" table will define
the conditions for actusl devIcs operation.

Supply Voltage
7V
Input Voltage
7V
Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS353

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS353

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2

Vil

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-1

-2.6

mA

10l

Low Level Output Current

12

24

mA

TA

Free Air Operating Temperature

70

·c

-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

ConditiOns

= 4.5V,IIN = -18 mA
Vee = 4.5V, 10H = Max
IOH = -400 "A, Vee = 4.5V to 5.5V
54ALSI74ALS
Vee = 4.5V
10l = 12mA

Min

= 5V, TA = 25·C.
Typ

Vee

2.4

Input Current at
Max Input Voltage

Vee

V

3.2

V
V

0.25

0.4

V

0.35

0.5

V

0.1

mA

= 5.5V, VIN = 7V

= 5.5V, VIN = 2.7V
= 5.5V, VIN = 0.4V
Vee = 5.5V, VOUT = 2.25V
Vee = 5.5V, VOUT = 2.7V

Units

Vee- 2

74ALS
10l = 24mA
II

Max
-1.5

IIH

High Level Input Current

Vee

20

p.A

III

Low Level Input Current

Vee

-0.1

mA

10

Output Drive Current

-112

mA

10ZH

Off-State Output
Current, High Bias

20

"A

IOZH

Off-State Output
Current, Low Bias

Vee

= 5.5V, VOUT = 0.4V

-20

p.A

lee

Supply Current

Vee

= 5.5V

-30

All Inputs at 4.5V

8

13

All Inputs at GND

7

12

2-162

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol
tplH

Parameter

From

Propagation Delay Time
Low to High Level Output

tpHl

Propagation Delay Time
High to Low Level Output

tplH

Propagation Delay Time
Low to High Level Output

tpHl

Output Enable Time
to High Level Output

tZl

Output Enable Time
to Low Level Output

tHZ

Output Disable Time
from High Level Output

Conditions

= 4.5V to 5.5V
= 50pF
= 500n

Vee
Cl
Rl

Select

DM54ALS353

DM74ALS353

Min

Max

Min

Max

5

32

5

24

ns

5

24

5

21

ns

4

24

4

18

ns

3

15

3

13

ns

3

18

3

13

ns

3

20

2

16

ns

2

12

2

10

ns

2

22

2

14

ns

y

Output
Control

Output Disable Time
from Low Level Output
Note 1: See Section 1 for test wavefonns and output load.

tLZ

Logic Diagram
I
IJUTPUT
CONTROl. 01

.......
....
H

ICO 6

)-::::I

ICI 6

7 OUTPUT
VI

DATA I
~

IC! 4

)--

le3 3

...

to..
SEUCT

{"

A 14

...

1 ....

"...

-"

Joo,

l

"...

2CO 10

~FLJ-

2C1 1\

-~

DATU

9 OUTPUT
Y2

2Cl 12

2C3 13
OUTPUT
CONTROL

15
G2

Units

Data

Propagation Delay Time
High to Low Level Output

tZH

To

.......

...

TLlF/6219-2

2-163

~

.....

!i
~
.....

::::&
C

~

~

r----------------------------------------------------------------------------,

ri1I

National
Semiconductor
Corporation

DM54ALS373/DM74ALS373 Octal
D-Type TRI-STATE® Transparent Latches

~ General Description

an
:::IE
C

These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, 1/0 ports, bidirectional
bus drivers, and working registers.
The eight latches of the ALS373 are transparent Ootype
latches. While the enable (G) is high the Q outputs will follow the data (0) inputs. When the enable is taken low the
output will be latched at the level of the data that was set
up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance

state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with LS TTL
counterpart
• Improved AC performance over LS373 at approximately
half the power
• TRI-STATE buffer-type outputs drive bus lines directly

Connection Diagram
Dual-In-Line Package

Vcc

eo

aD

7D

70

60

aD

5D

sa

OUTPUT

10

1D

2D

20

3Q

3D

4D

4Q

ENABLE

CONTROl.

G

GND
TLiF/8220-1

Order Number DM54ALS373J, DM74ALS373WM or DM74ALS373N
See NS Package Number J20A, M20B or N20A

2-164

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Input Voltage
Voltage Applied to Disabled Output

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranfBBd. TfIB device should not be operated at tflBselimits. The
parametric values defined in tfIB "ElBctrical Characteristics"
table are not guarantBsd at the absolute maximum ratings.
The "RscommendBd Operating Conditions" table will define
tfIB conditions for actual device operation.

7V
7V
5.5V

Operating Free Air Temperature Range
DM54ALS
- 55'C to + 125'C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65'Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS373

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS373

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

V
V

Vil

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-1

-2.6

mA

24

mA

10l

Low Level Output Current

tw
tsu

Width of Enable Pulse, High or Low

tH

12
10

10

ns

Data Setup TIme

10,J..

10,J..

ns

Data Hold Time

7,J..

H

Free Air Operating Temperature
-55
TA
The ( J.) arraw indicates the negative edge of the enable is ueed for referenca.

125

ns

0

70

'C

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25'C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,II = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V
Vil = VllMax

VOL

Low Level Output
Voltage

Min

Typ

Max

Units

-1.5

V

54ALS
10H = -1 mA

2.4

3.2

V

74ALS
10H = -2.6mA

2.4

3.3

V

Vee = 4.5V to 5.5V
10H = -400",A

54/74ALS

Vee = 4.5V
VIH = 2V

54174ALS
10l = 12mA

0.25

0.4

V

74ALS
10l = 24mA

0.35

0.5

V

0.1

mA

V

Vee - 2

II

Input Current at Max
Input Voltage

Vee = 5.5V, VIH = 7V

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

p.A

III

Low Level Input Current

Vee = 5.5V, Vil = 0.4V

-0.1

mA

10

Output Drive Current

Vee = 5.5V

-112

mA

10ZH

Off-State Output Current
High Level Voltage Applied

Vee = 5.5V, VIH = 2V
Vo = 2.7V

20

",A

10Zl

Off-State Output Current
Low Level Voltage Applied

Vee = 5.5V, VIH = 2V
Vo = 0.4V

-20

",A

Icc

Supply Current

54174ALS
Vo = 2.25V

Vee = 5.5V
Outputs Open

2-165

-30

Outputs High

9

16

mA

Outputs Low

16

25

mA

Outputs Disabled

17

27

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
., lIarameter

Symbol

CondHions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH
tpHL

Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

From

To

Data

AnyQ

Data

AnyQ

Propagation Delay Time
Low to High Level Output

Enable

AnyQ

Propagation Delay Time
High to Low Level Output

Enable

AnyQ

Output Enable Time

Output
Control

AnyQ

to High Level Output
tPZL

Output Enable Time
to Low Level Output

Output
Control

AnyQ

tpHZ

Output Disable Time
from High Level Output

Output
Control

AnyQ

tpLZ

Output Disable Time
from Low Level Output

Output
Control

AnyQ

tpZH

Note 1: See Saction 1 lor test waveforms and output load.

Function Table
Output
Control

Enable

L
L
L
H

H
H
L
X

L = lO!" State, H =

G

High State,

D
H
L
X
X

Output
Q

H
L
Qo

Z

X = Don't Care

Z = High Impedance State

Qg - Previous Condition 01 Q

2·166

DM54ALS373

DM74ALS373

Min

Max

Min

Max

2

17

2

12

nil

1

19

4

16

ns

6

29

6

22

ns

1

27

7

23

ns

3

33

6

18

ns

3

24

5

20

ns

2

24

2

10

ns

2

16

2

12

ns

Units

..
c

iii:

Logic Diagram

U'I

~

OUTPUT CONTROL

10

&;
W
.....
W

.....
C

3

iii:

.....

!

t

10

I!i.....
W

!O 4
5

30

!O

7
6 30

40 8

9 4Q

50 13
I! 5Q

60 14
15 60

78 17
16

70

80 18
19

BQ

ENABLE G 11
Tl/F/8220-2

fI
2·167

.. r----------------------------------------------------------------------------,

IJ
~

§

NaHonal
Semiconductor
CorporaHon

:::E
Q

~

DM54ALS374/DM74ALS374 Octal TRI-STATE®

!l D-Type-Edge-Triggered Flip-Flops

~

21

General Description
These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, 110 ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the ALS374 are edge-triggered D-type
flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D
inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vcc range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with LS TTL
counterpart
• Improved AC performance over LS374 at approximately
half the power
• TRI-STATE buffer-type outputs drive bus lines directly

Connection Diagram
Dual-In-Llne Package

Vee

8Q

8D

7D

70

OUTPUT
CONTROL

10

1D

2D

20

6Q

6D

5D

50

CLOCK

30

3D

4D

4Q

GND
TLlF/6113-1

Order Number DM54ALS374J, DM74ALS374WM or DM74ALS374N
See NS Package Number J20A, M20B or N20A

2-168

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sal.. Office/
DIstributors for availability and apecHlcatlons.
Supply Voltage
7V
Input Voltage
7V
Voltage Applied ta Disabled Output
5.5V
Operating Free Air Temperature Range
DM54ALS
-55·Cta + 125"C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·Cta + 150"C

Note: The "Absolute Maximum Ratings" ara those values
beyond which the safety of the device cannot be guarant99d. The device should not be operated at theS9limits. The

perametric values defined in the "Electrical Ch9racteristics"
table ara not guaranteed at the absolute maximum ratings.
The "R9COIT1mend9d Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

DM54ALS374

Parameter

DM74ALS374

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V
V

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.7

0.8

10H

High Level Output Current

-1

-2.6

mA

10l

Low Level Output Current

12

24

mA

35

MHz

·fCLOCK

tw

2

Clock Frequency
Width of Clock Pulse

0

I
I

V

2

30

0

High

16.5

14

ns

Low

16.5

14

ns
ns

tau

Data Setup Time

10t

10t

IH

Data Hold Time

TA

Free Air Operating Temperature

4t
-55

ot
0

125

ns
70

·C

The ( t) anow indicates the positive edge of the Clock is used for reference.

Electrical Characteristics
over recommended opereting free air temperature renge. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Condltlona

= 4.5V,11 = -18 mA
Vee = 4.5V
10H = Max
54/74ALS
10H = -400 JIoA
Vee = 4.5V to 5.5V
54/74ALS
Vee = 4.5V
10l = 12mA
VIH = 2V

= 5V, TA = 25"C.

Min

Typ

2.4

3.2

Vee

Input Current @ Max.
Input Voltage

Vee

V

V
0.25

0.4

V

0.35

0.5

V

0.1

mA

= 5.5V, VIH = 7V

= 5.5V, VIH = 2.7V
= 5.5V, Vil = 0.4V
54174ALS
Vee = 5.5V
Vo = 2.25V
Vee = 5.5V, VIH = 2V
Vo = 2.7V
Vee = 5.5V, VIH = 2V

Units
V

Vee- 2

74ALS
10l = 24mA
II

Max
-1.5

IIH

High Level Input Current

Vee

20

JIoA

III

Low Level Input Current

Vee

-0.2

mA

10

Output Drive Current

-112

mA

10ZH

Off·State Output Current,
High Level Voltage Applied

20

JIoA

10Zl

Off-State Output Current,
Low Level Voltage Applied

-20

/loA

19

mA

lee

Supply Current

-30

Vo = 0.4V
Vee = 5.5V
Outputs Open

Outputs High

2·169

11

Outputs Low

19

28

mA

Outputs Disabled

20

31

mA

fI

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditione

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Vee = 4.5Vto5.5V
RL = 500n
CL = 50pF

From

To

AnyQ

Propagation Delay Time
High to Low Level Output

Clock

AnyQ

tPZH

Output Enable Time
to High Level Output

Output
Control

AnyQ

tPZL

Output Enable Time
to Low Level Output

Output
Control

AnyQ

tpHZ

Output Disable Time
from High Level Output

Output
Control

AnyQ

tpLZ

Output Disable Time
from Low Level Output

Output
Control

AnyQ

Note 1: See Section 1 for test waveforms and output load.

Function Table

L
L
L
H

Clock

D

t
t

H
L

DM74ALS374

Min

Min

Max

30
Clock

Output
Control

DM54ALS374

Output

Q
H
L

X
00
Z
X
L = Low State, H = High State, X = Don't Care
t = PositIve Edge Transition
L

X

Z - High 1"1)8danca State

00 = PrevIous Condition of Q

2-170

Units

Max

35

MHz

3

21

3

12

ns

5

19

5

16

ns

5

27

5

17

ns

6

23

7

18

ns

2

12

2

10

ns

3

33

3

18

ns

Logic Diagram
~_1~____~~____- ,

CONTROL

10

3
2

2D

4
5

30

40

50

60

70

80

CLOCK

10

20

7

'0

6

'0

9

'0

12

ij

15

'0

16

'0

19

30

8

40

13

50

14

60

17

70

18

11

BO
TL/F/6113-2

2-171

_Nal1onal

PRELIMINARY

Semiconductor
Corporation

DM54ALS390/DM74ALS390 Dual 4-Bit Decade Counters
General Description

Features

Each of these monolithic counters contains eight masterslave flip-flops and additional gating to implement two independent four bit counters in a single package.
To use their maximum count length, the B input is connected to the QA output. The Input count pulses are applied to
Input A and the outputs are as described in the appropriate
truth table. A symmetrical divide-by-ten count can be obtained by connecting the QD output to the A input and applying the input count to the B input.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated;- ion-Implanted Schottky TIL
process
• Individual clocks for A and B flip-flops provide dual divide-by-2 and divide-by-5 counters
• Direct clear for each 4-bit counter

Connection Diagram

Function Tables
BCD Count Sequence
(See Note 2)

a.KA1 1

J
QA1 J

ClR1

a.K 1B J

~vcc
~a.KA2

Count

liCLR2
l!QA2

QBl j

l!a.K82

QC1:!

110B2

QD12

.ll!.QC2

eND:!

.!...OD2
TVF/9168-1

Order Number DM54ALS39OJ, DM74ALS390M or
DM74ALS390N
See NS Package Number J16A, M16A or N16A

Output
OD

QC

OB

0

L

L

L

OA

L

1

L

L

L

H

2

L

L

H

L

3

L

L

H

H

4

L

H

L

L

5

L

H

L

H

6
7

L

H

H

L

L

H

H

H

8

H

L

L

L

9

H

L

L

H

BI-Qulnary (5-2)
(See Note 3)
Output

Count

"

QA

OD

OC

0

L

L

L

OB

L

1

L

L

L

H

2

L

L

H

L

3

L

L

H

H

4

L

H

L

L

5

H

L

L

L

6

H

L

L

H

7

H

L

H

L

8

H

L

H

H

9

H

H

L

L

Note 2: Output QA Is connected to Input B for BCD count
Note 3: Output QD Is connected to Input A for bi.qulnsry count
H = High logic Level, L - Low Logic Level

This document contslns InformaUon on a product undar development NSC .....rvea tho

2·172

~ght

to change or discontinue this product without noUce.

Absolute Maximum Rating
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
DIstrIbutors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O·Cto +70"C
- 65·C to + 150"C
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be gusranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

DM54ALS390

Parameter

Vcc

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

--

DM74ALS390

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V

2

V

0.7

0.8

V

IOH

High Level Output Current

-0.4

-0.4

mA

IOL

Low Level Output Current

4

8

mA

fCOUNT

Count Frequency

tw

Pulse Width

A Input

0

0

B Input

0

0

MHz

A Input High
A Input Low

ns

B Input High
Clear High

tau

Clear Inactive-State Setup Time

TA

Free Air Operating Temperature

ns
-55

125

·c

70

0

Electrical Characteristics over recommended free air temperature range
Symbol

Parameter

Test Conditions

Vie

Input Clamp Voltage

VOH

High Level Output Voltage

VOL

Low Level Output
Voltage

= Min,ll = -18 mA
Vee = 4.5V to 5.5V, 10H = -0.4 mA
54/74ALS
Vee = Min
IOL = 4mA

Min

IIH

IlL

Input Current at Max, VI
Input Voltage

High Level Input
Current

Low Level Input
Curtent

= 7V

Vee

Vee

Vee

= Max, VI = 7V

= Max, VI = 2.7V

= Max, VI = 0.4V

10

Output Drive Current
(B Bus Ports Only)

Vee

= Max, Vo = 2.25V

ICC

Supply Current

Vee

= Max (Note 1)
2-173

Max

Units

-1.5

V

Vee- 2

V
0.25

0.4

0.35

0.5

V

74ALS
10L = 8mA
II

Typ

Vee

Clear

100

Input A

200

Input B

300

Clear

IJA

20

Input A

40

Input B

60

Clear

-100

Input A

-200

InputB

-300
-30

-112

/LA

/LA

mA
mA

fI

Switching Characteristics over recommended operating free air temperature range
Symbol
f max

Parameter
Maximum Clock Frequency

tpLH

Propagation Delay TIme
Low to High Level Output

tpHL

From (Input)
To (Output)

Conditione

Vee = 4.6 to 6.6V,
RL = 600,0
CL = 50pF
TA = Minto Max
(Note 2)

:

,'.

DM54ALS380

DM74ALS380

Min

Min

Max

Max

AtoQA

'c

i

Unite
,
MHz

BtoQB
AtoQA

ns

Propagation Delay Time
High to Low Level Output

AtoQA

ns

tpLH

Propagation Delay Time
Low to High Level Output

AtoQC

ns

tpHL

Propagation Delay TIme
High to Low Level Output

AtoQC

ns

tpLH

Propagation Delay TIme
Low to High Level Output

BtoQB

ns

tpHL

Propagation Delay TIme
High to Low Level Output

BtoQB

ns

tpLH

Propagation Delay Time
Low to High Level Output

BtoQC

ns

tpHL

Propagatio,:, Delay Time
High to Low Level Output

BtoQC

ns

tpLH

Propagation Delay Time
Low to High Level Output

BtoQD

ns

tpHL

Propagation Delay Time
High to Low Level Output

BtoQD

ns

tpHL

Propagation Delay Time
High to Low Level Output

Clear to
AnyQ

ns

Note 1: Icc is measured with all outputs open, both clear inputs grounded following momentsry connection to 4.5V and all other Inputs grounded.
Note 2: See Section 1 lor test wavalorms and output load.

\

2·174

i

Logic Diagram
INPUT A - - - - - - - - - - - - - - - - c J D T

I

OUTPUT QA

I

OUTPUT Q8
INPUT 8 - - - + - - - - - - -.......

OUTPUT QC

OUTPUT QD

CLEAR
TLlF/9169-2

2·175

NatiOnal

~ Semiconductor
Corporation

DM54/DM7 4ALS465A/466A/467A/468A
Octal TRI-STATE® Bidirectional Bus Drivers
General Description

Features

These octal TRI-STATE bus drivers are designed to provide
the designer with flexibility in implementing a bus interface
with memory, microprocessor, or communication systems.
The output TRI-STATE gating control is organized into two
separate groups of four buffers on the ALS467 A and
ALS468A, and one common gating control for all eight buffers on the ALS465A and ALS468A. All control inputs are
active low enabling. The buffers on the ALS465A and
ALS467 A are non-inverting and the buffers on the ALS466A
and ALS468A are inverting. The TRI-STATE circuitry contains a feature that maintains the buffer outputs in
TRI-STATE (high impedance state) during power supply
ramp-up or ramp-down. This eliminates bus glitching problems that arise during power-up and power-down.

• Advanced low power oxide-isolated ion-implanted
Schottky TTL process
• Functional and pin compatible with the DM54174LS
counterpart and the DM71 /81 LS95, 98, 97, 98
• Improved Switching performance with less power dissipation compared with the DM54174LS counterpart
• Switching response specified into 5000 and 50 pF load
• Switching response specifications guaranteed over full
temperature and Vee supply range
• PNP input design reduces input loading

Connection Diagrams
Dual-In-Une Package

Dual-In-Llne Package

i!1

Vee

11

Vee

Al

if2

lAl

21

Yl

AS

lYl

2M

At

YB

lA2

2Y4

Y2

16

A7

lY2

2A3

A3

15

Y7

lA3

2Y3

Y3

14

A6

lY3

2A2

M

13

Y6

1M

2Y2

Y4

12

A5

lY4

2Al

11

Y5

GND

2Yl

GND

10

TL/F/6221-1

TLlF/6221-2

Top View

Top View

Order Number DM54ALS465AJ, DM54ALS466AJ,
DM74ALS465AWM, DM74ALS466AWM,
DM74ALS465AN or DM74ALS466AN
See NS Package Number J20A, M20B or N20A

Order Number DM54ALS467AJ, DM54ALS468AJ,
DM74ALS467AWM, DM74ALS468AWM,
DM74ALS467AN or DM74ALS468AN
See NS Package NumberJ20A, M20B or N20A

2-176

Absolute Maximum Ratings
If Mllltary/Aeroepace specified devices are required,
contact the National Semiconductor Sel.. OffIcel
Distributors for availability and specifications.
Supply Voltage, Vee
Input Voltage
Output Voltage (Disabled)

Note: The "Absolute Maximum Ratings" ara those values
beyond which the safety of the device cannot be guarant99d. The device should not be operated at these limits. The
parametric values defined in the "Electrical Cheracteristics"
tablfl ara not guaranteed at the absolute maximum ratings.
The ''R9COfTIrnended Operating Conditions" tablfl will define
the conditions for actual device operation.

7V
7V
5.5V

Operating Free Air Temperature Range
DM54ALS
-55"Cto + 125'C
DM74ALS
O'Cto +70'C
Storage Temperature Range
-55'Cto + 150'C

Recommended Operating Conditions
Symbol

DM54ALS465A
DM54ALS468A
DM54ALS487A
DM54ALS468A

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS485A
DM74ALS488A
DM74ALS487A
DM74ALS488A

Unlta

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2

Vil

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-12

-15

mA

10l

Low Level Output Current

12

24

mA

70

'C

TA

Operating Free Air Temperature

'125

-55

0

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise specified)

Symbol

Parameter

DM54ALS485A
DM54ALS486A
DM54ALS487A
DM54ALS486A

Conditions

Min
VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

= 4.5V, II = -18 mA
Vee = 4.5Vto5.5V 10H = -0.4mA
10H = -SmA
Vee = 4.5V
IOH = Max
Vee = 4.5V
10l = 54ALS (Max)
10l = 74ALS (Max)
Vee = 5.5V, VI = 7V

Typ

VOL

II

Input Current at Max
Input Voltage

IIH

High Level Input
Current

Vee

= 5.5V, VI = 2.7V

III

Low Level Input
Current

Vee

= 5.5V, Vil = 0.4V

10

Output Drive
Current

Vee

= 5.5V, Vo = 2.25V

10ZH

High Level TRI-STATE Vee
Output Current

= 5.5V, Vo = 2.7V

10Zl

Low Level TRI-STATE
Output Current

= 5.5V, Vo = 0.4V

Vee

Typ

Unlta

Max
-1.5

V

Vee- 2

Vee- 2

V

2.4

2.4

V

2

2

V

0.25

-

-30

2-177

Min

-1.5

Vee

Low Level Output
Voltage

Max

DM74ALS465A
DM74ALS468A
DM74ALS467A
DM74ALS468A

0.4

0.25

0.4

V

-

0.S5

0.5

V

0.1

0.1

mA

20

20

,...A

-0.1

-0.1

mA

-112

rnA

20

20

p.A

-20

-20

,...A

-112

-30

PI

Electrical Characteristics

(Continued)
over recommended operating free air temperature range (unless otherwise specified)

Symbol

Parameter

DM54ALS465A
DM54ALS466A
DM54ALS467A
DM54ALS468A

Conditions

Typ

Max

21
33
38

11
19
23

16
28
33

7
16
19

15
29
32

7
16
19

10
24
27

Vee = 5.5V, ALS467A
Outputs High
Outputs Low
Outputs TRI-STATE

11
19
23

21
33
38

11
19
23

16
28
33

Vee = 5.5V, ALS468A
Outputs High
Outputs Low
Outputs TRI-STATE

7
16
19

15
29
32

7
16
19

10
24
27

Typ

Max

Vee = 5.5V, ALS465A
Outputs High
Outputs Low
Outputs TRI-STATE

11
19
23

Vee = 5.5V, ALS466A
Outputs High
Outputs Low
Outputs TRI-STATE

Min
lee

Supply Current

DM74ALS465A
DM74ALS466A
DM74ALS467A
DM74ALS468A
Min

Units

mA

mA

mA

mA

,ALS465A and' ALS467 A Switching Characteristics
over recommended operating free air temperature range (Note 1)

Parameter

tpLH
tpHL
tpZH
tpZL

Conditions

Vee = 4.5V to 5.5V,
CL = 50pF,
R1 = 5000,
R2 = 5000,
TA = Minto Max

tpHZ

From
(Input)

A

G
G

To
(Output)

Y

AnyY

AnyY

tpLZ

DM54ALS465A
DM54ALS467A

DM74ALS465A
DM74ALS467A

Min

Max

Min

Max

2

16

2

13

ns

4

15

4

12

ns

4

27

4

23

ns

5

30

5

25

ns

Units

2

12

2

10

ns

3

21

3

18

ns

,ALS466A and'ALS468A Switching Characteristics
over recommended operating free air temperature range (Note 1)

Parameter

tpLH
tpHL
tPZH
tpZL
tpHZ

Conditions
Vee = 4.5V to 5.5V,
CL = 50pF,
R1 = 5000,
R2 = 5000,
TA = Min to Max

From
(Input)

A

G
~

To
(Output)

Y

AnyY

AnyY

tpLZ
Nott 1: See SectIon 1 for teat waveform. and OUtpulloada.

2-178

DM54ALS466A
DM54ALS468A

DM74ALS466A
DM74ALS468A

Min

Max

Min

Max

3

14

3

12

ns

2

11

2

9

ns

4

21

4

16

ns

7

25

7

23

ns

2

12

2

10

ns

2

20

2

17

ns

Units

c

II:

Logic Diagrams

en

....C
~

ALS465A

ALS466A

II:

......

(3)

(3)

t
r;;

Yl

Y1

(5) Y2

(5) Y2

(7) Y3

(7) Y3

~

G»

....~
;
....
~

G»
~

G»

....~

(9)

(9) Y4

~

Y4

G»

~

(11) Y5

(11) Y5

(13) y&

(13) Y6

(15) Y7

(15)

(17) Y8

(17)

Y7

Y8

TL/F/6221-4

TLlF/6221-3

ALS468A

ALS467A

(3)

(3) lYl

1Yl

(5)

(5) 1Y2

W2

(7)

(7) lY3

lY3

(9) lY4

(9) lY4

(11)

(11) !VI

2Yl

(13) 2Y2

(13)

(15) !V3

(15)

!V2

2Y3

PI

(17) 2Y4

(17) 2Y4

TLlF/8221-5
TLlF/6221-8

2·179

...~

;...

Nal1onal

~ Semiconductor
Corporation

c;; DM54/74ALS518/519/520/521/522
1ft

8-Bit Comparators

CiCi

:;; General Description
!) These comparators perform an "equal to" comparison of
~
.....
.;z

~

two eight-bit words with provision for expansion or external
enabling. The matching of the two 8-bit input plus a logic
LOW on the ~ input produces the output A = B on the
ALS518 and 519 and the output A = B on the ALS520, 521
and 522. The ALS520 and 521 have totem pole outputs,
while the ALS518, 519 and 522 have open collector outputs
for wire AND cascading. Additionally, the ALS518, 520 and
522 are provided with B input pull up termination resistors
for analog or switch data.

Connection Diagrams

Features
• Switching specifications .t 50 pF
• Switching specifications guaranteed over full temperature.nd Vee range
• Advanced oxide-isolated, lon-implanted Schottky TIL
process
• Functionally and pin for pin compatible with LS family
counterpart
• Improved output transient hanciling capability

Function Tables

ALS518,519

Du....ln-Una P.ck.ge

1 7 816 ~ 8.5 ~5 ~ ~4

Inputa

VfA;a 8

20 19 18 17 16 15 14 13 12 11

L
L
H

D
1 2

E'N

3

4

5

6

~ ~ 11 J1~

7

8

H

9 10

~ 8f

'f 8t ~4

H

D
E'N

~

5

6

X

= High logic Level; L =

Low LcgIc Level;

Inputa

20 19 18 17 16 15 14 13 12 11

4

H
L
L

x = Oon·t Care

ALS520, 521, 522

Du.I-ln-Une Package

1 2 3

A=B

2

TLlF/6114-1

816

Data
A=B
A¢B

J 13 J3~D

Order Number DM54ALS518J, DM54ALS519J,
DM74ALS518WM, DM74ALS519WM,
DM74ALS518N or DM74ALS519N
See NS P.ckage Number J20A, M20B or N20A

Vf~ 81 Al

Output

7

8

9 10

Jo ~1 J1 12 ~2 13 ~3 G~D
TUF/6114-2

Order Number DM54ALS52OJ, DM54ALS521J,
DM54ALS522J, DM74ALS520WM, DM74ALS521WM,
DM74ALS522WM, DM74ALS520N,
DM74ALS521N or DM74ALS522N
See NS Package Number J20A, M20B or N20A

2-180

Output

EN

D.ta

L
L
H

A=B
A¢B

X

L
H
H

= High Logic Level; L = Low Logic Level; X = Oon't Care

Absolute Maximum Ratings
If Military/Aerospace speclfled devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55°C to + 125°C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65°C to + 150"C

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

DM54ALS
518,519,520,521,522

Parameter

DM74ALS
518,519,520,521,522

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

VOH

High Level Output Voltage
(ALS518. 519, 522)

5.5

5.5

V

10H

High Level Output Current
(ALS520, 521)

-1

-2.6

mA

24

rnA

70

°C

2

10L

Low Level Output Current

TA

Free Air Operating Temperature

V

2

12
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

10H

High Level Output
Current

VOL

Low Level Output
Voltage

Conditions

= 4.5V, II = -18 mA
Vee = 4.5V to 5.5V
ALS520, 521
10H = -400 p.A
Vee = 4.5V
10H = Max
ALS518,
Vee = 5.5V
519,522
VOH = 5.5V
54174ALS
Vee = 4.5V
10L = 12mA

Max High Input
Current

Vee

=

5.5V

High Level Input
Current

Vee = 5.5V,
VIH = 2.7V

Low Level Input
Current

Vee = 5.5V,
VIL = 0.4V

10

Output Drive
Current

Vee

lee

Supply Current

Vee = 5.5V
(Note 1)

IlL

Typ

=

5.5V

=

=

25°C.

Max

Units

-1.5

V
V

Vee -2
2.4

3.2

V
0.1

mA

0.25

0.4

V

0.35

0.5

V

0.1

mA

VIH = 5.5V
B InputALS518,520, 522
VIH

IIH

5V, TA

Vee

74ALS
10L = 24mA
II

=

Min

7V, All Others

All Others

20

poA

BlnputALS518,520,522

-200

B InputALS518, 520,522

-0.6

mA

All Others

-0.1

mA

-112

mA

Vo = 2.25V
ALS520, 521

-30

ALS518, 519, 522

11

17

mA

ALS520,521

12

19

mA

Note 1: Icc is measured with G grounded, A and B Inputs a\ 4.5V and outputs open.

2-181

fI

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH
tpHL

From
Input

Conditions

To
Output

DM74ALS
518, 519

DM54ALS
518,519

Min

Max

Min

Max

Units

AorB
Data

A=B

15

37

15

33

ns

AorB
Data

A=B

3

18

3

15

ns

Propagation Delay Time
Low to High Level Output

EN

A=B

15

37

15

33

ns

Propagation Delay Time
High to Low Level Output

EN

A=B

3

18

3

15

ns

Vee = 4.5V to 5.5V
CL=50pF
RL = 6670

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH
tpHL

From
Input

Conditions

To
Output

DM54ALS
520,521

DM74ALS
520,521

Min

Max

Min

Max

Units

AorB
Data

A=B

3

19

30

12

ns

AorB
Data

A=B

3

25

50

20

ns

Propagation Delay Time
Low to High Level Output

EN

A=B

2

18

2

12

ns

Propagation Delay Time
High to Low Level Output

EN

A="B

5

23

5

22

ns

Vee = 4.5Vt05.5V
CL = 50pF
RL = 5000

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH
tpHL

From
Input

Conditions

To
Output

DM74ALS
522

DM54ALS
522

Min

Max

Min

Max

Units

AorB
Data

A=B

10

30

10

25

ns

AorB
Data

A=B

5

25

5

23

ns

Propagation Delay Time
Low to High Level Output

EN

A=B

8

30

8

25

ns

Propagation Delay Time
High to Low Level Output

EN

A=B

8

30

8

23

ns

Vee = 4.5V to 5.5V
CL = 50pF
RL = 6670

Note 1: Sea Section 1 for test waveforms and output load.

2-182

~------------------------------------------------------~i

Logic Diagrams

ALS518/519

~

Ii....
~
....
~

I....
....

CII

~

A=B

TUF/6114-3

ALS520/5211522

EN

~--{>~------------~
2-183

TLlF/6114-4

_

National

Semiconductor
Corporation

DM54ALS533/DM74ALS533
Octal 0-Type Transparent Latches
with TRI-STATE® Outputs
General Description
These 8-bit registers feature totem-pole TAl-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, 110 ports, bidirectional
bus drivers, and working registers.
The eight inverting latches of the ALS533 are transparent
outputs
D-type latches. While the enable (G) is high the
will follow the complement of the data (D) inputs. When the
enable is taken low the output will be latched at the complement of the level of the data that was set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic

a

levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• Switching speCifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TAI-STATE buffer-type outputs drive bus lines directly

Connection Diagram
Dual-in-Line Package
ENABLE
G
11

OUTPUT
CONTROL
TL/F/6222-1

Order Number DM54ALS533J, DM74ALS533WM or DM74ALS533N
See NS Package Number J20A, M20B or N20A

2-184

Absolute Maximum Ratings
If MHltarylAerospace specified devlcell are required,
contact the National Semiconductor Sel.. Offlcel
Dlatrlbutora for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
DM54ALS
-5S-C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-6S-Cto +15O"C

Note: The "Absolute Maximum Ratings" are those values
bByond which the saf8ty of the device cannot bB guarant99d. The device should not be operated at these limits. The
peramefric valU9S defined in the "Electrical Cheract9ristics"
tabl9 are not guaranteed at the absolute maximum ratings.
The "R9COfTImended Operating Conditions" table WIll define
the conditions for actusl device operation.

Recommended Operating Conditions
Symbol

DM74ALS533

DM54ALS533

Parametar

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V
V

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.7

0.8

2

V

2

10H

High Level Output Current

-1

-2.6

mA

10l

Low Level Output Current

12

24

mA

tw

Width of Enable Pulse, High or Low

15

15

ns

tsu
IH

Data Setup TIme

15,J..

15,J..

ns

Data Hold TIme

7,J..

7,J..

-55
Free Air Operating Temperature
The ( ./.) arrow Indicates the negative edge of the enable is ueed for reference.

125

TA

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Paremetar

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

Conditions

= 4.5V,11 = -18 mA
Vee = 4.5V
Vil = VllMax
Vee

VOL

Low Level Output
Voltage

II

Input Current II Max.
Input Voltage

= 5V, TA = 25·C.

Min

Typ

Vee

= 4.5V to 5.5V

Vee = 4.5V
VIH = 2V

Vee

54ALS
10H = -1 mA
74ALS
10H = -2.6mA
54174ALS
10H = -400 p.A

ns
·C

70

0

Max

Units

-1.5

V

2.4

3.2

V

2.4

3.3

V
V

Vee- 2

54174ALS
10l = 12mA
74ALS
10l = 24 rnA

0.25

0.4

V

0.35

0.5

V

0.1

mA

20
-0.1

/loA
mA

-112

mA

= 5.5V, VIH = 7V

IIH

High Level Input Current

III

Low Level Input Current

10

Output Drive Current

= 5.5V, VIH = 2.7V
= 5.5V, Vil = 0.4V
Vee = 5.5V

IOZH

Off-state Output Current
High Level Voltage Applied

Vee = 5.5V, VIH
Vo = 2.7V

= 2V

20

p.A

10Zl

Off-State Output Current
Low Level Voltage Applied

Vee = 5.5V, VIH
Va = 0.4V

= 2V

-20

p.A

lee

Supply Current

Vee = 5.5V
Outputs Open

Vee

Vee

54174ALS
Va = 2.25V

Outputs High

10

17

rnA

Outputs Low

17

26

mA

18.5

28

rnA

Outputs Disabled

2-185

-30

Switching Characteristics over recommended operating free air temperature range (Note 1).
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

COndItlona
Vee = 4.SVto S.SV
RL = SOOO
CL=50pF

From

To

Data

Anytl

Data

Anytl

Propagation Delay Time
Low to High Level Output

Enable

Anytl

tPHL

Propagation Delay Time
High to Low Level Output

Enable

Anytl

tpZH

Output Enable Time
to High Level Output

Output

Anytl

Control

tpZL

Output Enable Time
to Low Level Output

Output
Control

Anytl

tpHZ

Output Disable Time
from High Level Output

Output
Control

Anytl

tpLZ

Output Disable Time
from Low Level Output

Output

Anytl

Control

Note 1: See Section 1 lor test wavefonna and output load.

Function Table
output

Enable

Control

G

L
L
L
H

H
H
L

L ~ Low State, H ~

X

D

Output

a

H
L

L
H

X
X

llo
Z

High State, X - Don't Care

Z - High Impedance State

Co =

PnwIoua CondItIon 01 a

2·186

DM54ALS534

DM74ALS534

MIn

lID

Min

Max

4

24

4

19

ns

4

14

4

13

ns

5

28

5

23

ns

4

21

4

18

ns

4

19

4

17

ns

4

20

4

18

ns

2

12

2

10

ns

3

22

3

16

ns

Units

r-------------------------------------------------------~c

!:

;

Logic Diagram
OUTPUT CO.TROl

Hiw
~

10

c

!:

3

;

Ii)
UI

5

20

5D 13

12

50

8D 14

15

60

1D 11

16

10

8D 18

II

ao

20

4

38

1

~

48 8

liABLE

Gi..;I~I--_C>o_.....
Tl/F/6222-2

2-187

I!J

National

Semiconductor
Corporation

DM54ALS534/DM74ALS534 Octal D-Type
Edge-Triggered Flip-Flops with TRI-STATE® Outputs
General Description
These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, 1/0 ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the ALS534 are edge-triggered inverting O·type flip-flops. On the positive transition of the clock,
the Q outputs will be set to the complement of the logic
states that were set up at the 0 inputs.

A buffered output control input cen be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-5TATE buffer-type outputs drive bus lines directly

Connection Diagram
Dual-In-Une Package
CLOCK
II

TLIFI6223-1

Order Number DM54ALS534J, DM74ALS534WM or DM74ALS534N
See NS Package Number J20A, M20B or N20A

2-188

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be opersted at these limits. The
parametric values defined in the "£/ectricsl Characteristics"
tsbIe are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operstion.

If MIUtary/Aeroepace specHled devices are required,
contact the National Semiconductor Sal.. 0ffIce1
Dlalrlbutora for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Voltage Applied to Disabled Output

5.5V

Operating Free Air Temperatura Range
DM54ALS
-55"Cto + 125°C
DM74ALS
O"C to + 70"C
Storage Temperature Range

-65°C to

+ 150"C

Recommended Operating Conditions
Symbol

DM54ALS534

Parameter

DM74ALS534

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V
mA

2

2

V

10H

High Level Output Current

-1

-2.6

10L

Low Level Output Current

12

24

mA

fCLOCK

Clock Frequency

35

MHz

tw

Width of Clock Pulse

0

I
I

30

0

High

16.5

14

ns

Low

16.5

14

ns

tsu
1H

Data Setup Time

10t

10t

ns

Data Hold Time

ot

ot

TA

Free Air Operating Temperature

-55

125

ns

0

70

·C

The ( t) arrow Indicates IIIe pooItive edge oIlIIe Clock is used for reference.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Min

Conditions

= 4.5V, II = -18 mA
Vee = 4.5V
Vil = VILMax
Vee = 4.5V to 5.5V
10H = -400 p.A
Vee = 4.5V
VIH = 2V

= 5V, TA = 25°C.
Typ

Vee

II

Input Current at Max
Input Voltage

Vee

= 5.5V, VIH = 7V

IIH

High Level Input Current

Vee

IlL

Low Level Input Current

Vee

= 5.5V, VIH = 2.7V
= 5.5V, Vil = 0.4V

10

Output Drive Current

Vee

= 5.5V

IOH

= Max

54174ALS

2.4

Units
V
V

3.2

Vee -2

V

54174ALS
10L = 12mA

0.25

0.4

V

74ALS
IOl = 24mA

0.35

0.5

V

0.1

mA

20
-0.2

All Others

Vo

= 2.25V

/loA
mA

-0.1

CLK,OC

2-189

Max
-1.5

-30

-112

mA

"
Electrical Characteristics (Continued)
over recommended operating free air temperature range. All typical values are measured at Vee

Symbol

Pararfteter

IOZH

Off-State Output Current
High Level Voltage Applied

Vee = 5.5V, VIH
Vo =2.7V

= 2V

IOZl

Off-State Output Current
Low Level Voltage Applied

Vee = 5.5V, VIH
Vo = O.4V

= 2V

lee

Supply Current

Vee = 5.5V
Outputs Open

= ,5V, TA = 25"C.

""in

Conditions

Typ

...

un~

Max

20

p.A
",l"

-20

,/J-A
mA

Outputs High

11

19

Outputs Low

, 19

28

mA

20

31

m~

Outputs Disabled

Switching Characteristics over recommended oper~ting free air temperature range (Note 1)
Symbol

Parameter

Conditions

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

tpHl

Vee = 4.5V to 5.5V
Rl = 500n
Cl = 50pF

From

To

Any 0

Propagation Delay Time
High to Low Level Output

Clock

AnyO

tpZH

Output Enable Time
to High Level Output

Output
Control

Any 0

tpZl

Output Enable Time
to Low Level Output

Output
Control

Any 0

tPHZ

Output Disable Time
from High Level Output

Output
Control

Any 0

tpLZ

Output Disable Time
from Low Level Output

Output
Control

Any 0

Note 1: See SectIon 1 foi- lest waveforms and output load.

Function Table

L
L
L
H

Clock

D

t
t

H
L
X
X

L
X

Output

Q
L
H

00
Z

L - Low State, H - High Stale. X - Don·1 Care
t - Positive Edge Transition
Z = High Impedance Stale

llo -

PrevIcius Condition of

DM74ALS534

Min

Min

Max

30
Clock

Output
Control

DM54ALS534

a

2-190

Units

Max
MHz

35

3

15

3

12

ns

5

18

5

16

ns

5

19

5

17

ns

7

20

7

18

ns

2

12

2

10

ns

2

16

2

14

ns

r-------------------------------------------------------------'ca=
Logic Diagram

E

OUTrUT CONTIOl "':"--Cl>---,

Ii
~
c
a=

18 3

t

i

2. 4

u--------t-~

CD •

50 13

eO

10 14

15

78 11

16 70

nil

II

eO

ClOCK .1;.;.1_ _""""1DC.....
TL/F/6223-2

PI
2·191

_

National

PRELIMINARY

Semiconductor
Corporation

DM54ALS540/DM74ALS540 Octal Inverting
Buffers and Line Drivers with TRI-STATE® Outputs
General Description

Features

These octal buffers and line drivers are designed to have
the performance of the 'ALS240 series and, at the same
time, offer a pinout with inputs and outputs on oPPOsite
sides of the package. This arrangement greatly enhances
printed circuit board layout. The TRI-STATE control gate is
a 2-input NOR such that if either ~1 or ~2 is high, all eight
outputs are in the high impedance state.

• Advanced oxide-isolated, Ion-lmplanted Schottky TTL
procesa
• Switching performance is guaranteed over full temperature and Vee supply range
• Data flow-thru pinout (All inputs on opposite side from
outputs)
• P-N-P inputs reduce DC loading

Connection Diagram
n

~

18

N

~

1716

15

~

14

~

13

n

~

12

11

1

Gl

TLlF/9170-1

Order Number DM54ALS54OJ, DM74ALS540WM or DM74ALS54ON
See NS Package Number J20A, M20B or N20A

Function Table
Output

Inputs

01

02

A

y

H

X

X

Hi-Z

X

H

X

Hi-Z

L

L

L

H

L

L

H

L

= High logic Level, L = Low logic Level
X = Don't Care (EIther High or Low logic LeveQ
H

H~Z =

High Impedance (011) Slate

ThiS document contains information on a product under development NSC reserves the right 10 change or discontinue this product without notice.

2-192

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales OHlce/
Distributors for availability and specifications.

Supply Voltage
7V
Input Voltage
7V
Voltage Applied to a
Disabled TRI-STATE Output
5.5V
Operating Free·Air Temperature Range
DM54ALS
- 55"C to + 125·C
DM74ALS
O·Cto +70"C
Storage Temperature Range
- 65·C to + 150"C

Recommended Operating Conditions
Symbol

DM54ALS540

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS540

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2

VIL

Low Level Input Voltage

0.7

0.8

V

IOH

High Level Output Current

-12

-15

mA

24

mA

70

·C

IOL

Low Level Output Current

TA

Free Air Operating Temperature

12
-55

125

0

Electrical Characteristics over recommended free air temperature range
Symbol

Parameter

Test Conditions

VIK

Input Clamp Voltage

Vee = Min,ll = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V to 5.5V

IOH = -0.4mA

Vee = Max

IOH = -3mA
IOH = Max

VOL

Low Level Output
Voltage

Vee = Min

II

Input Current @ Max
Input Voltage

Vee = Max, VI = 7V

IIH

High Level Input Current

IlL
IOZH
10ZL

Low Level TRI·STATE
Output Current

Vee = Max, Vo = 0.4V

10

Output Drive Current

Vee = Max, Vo = 2.25V

lee

Supply Current

Vee = Max

Min

Typ

Max

Units

-1.5

V

Vee- 2
2.4

3.2

V

2

54/74ALS
IOL = 12 mA

0.25

0.4

74ALS
IOL = 24mA

0.35

0.5

mA

100

p.A

Vee = Max, VI = 2.7V

20

p.A

Low Level Input Current

Vee = Max, VI = O.4V

-100

p.A

High Level TRI·STATE
Output Current

Vee = Max, Vo = 2.7V

20

p.A

-20

p.A

-112

mA

2·193

-30
Outputs High

5

10

Outputs Low

13

22

Outputs Disabled

11

19

mA

Switching Characteristics over recommended free air operating temperature range
Symbol
tpLH

Parameter
Propagation Delay Time
Low to High Level Output

Conditions

= 4.5V to 5.5V.
= R2 = 500n.
CL = 50pF
Vee

From (Input)
To (Output)

DM54ALS540

DM74ALS540

Min

Max

Min

Max

2

14

2

12

ns

AorB
toY

2

11

2

9

ns

AorB

toy

R1

Units

tpHL

Propagation Delay Time
High to Low Level Output

tpZH

Output Enable Time
to High Level Output

GtoY

5

18

5

15

ns

tPZL

Output Enable Time
to Low Level Output

GtoY

8

24

8

20

ns

tpHZ

Output Disable TIme
from High Level Output

GtoY

1

12

1

10

ns

tpLZ

Output DisableTime
from Low Level Output

GtoY

2

14

2

12

ns

(Note 1)

Note 1: See Section 1 for outpulload and test waveforms.

2-194

PRELIMINARY

DM54ALS541/DM74ALS541
Octal Buffers and Line Drivers with TRI-STATE® Outputs
General Description

Features

These octal buffers and line drivers are designed to have
the performance of the 'ALS240 series and, at the same
time, offer a pinout with inputs and outputs on opposite
sides of the package. This arrangement greatly enhances
circuit board layout. The TRI-8TATE control gate is a 2-input
NOR such that if either G1 or G2 Is high, all eight outputs
are in the high impedance state.

• Advanced oxide-isolated ion-implanted Schottky TIL

process
• Switching performance is guaranteed over full tempera-

IiE

~...

"ca::
.....

~...

ture and Vee supply range

• Date flow-thru pinout (all inputs on opposite side from
outputs)
• P-N-P Inputs reduce DC loading

Connection Diagram
n

~

18

~

17

~

18

~

15

~

14

~

13

~

12

11

1

01

TL/F/9171-1

Order Number DM54ALS541J, DM74ALS451WM or DM74ALS541N
See NS PIIc:IaIge Number J2OA, M208 or NZOA

Function Table
-Input

ell

Output

ela

A

y

H

X

X

HI-Z

X

H

X

HI-Z

L

L

L

L

L

L

H

H

H - HIgh logic Level, L - Low LogIc Level
X - Don't
(ent. Low or HIgh I.ogIc Level)
HI-Z - HIgh Impedance (011) lllal8

en

PI
This document contains Informallan on • producI under development. NSC _

2-195

!he right to change or discontinue Ihia product wIIhoUi notice.

Abs.olute Maximum Ratings
Note: The "Absolute MtJXimiJm Rsf/rlgs" sriI those·values
beyond which the ssfety o(the device csnnpfbe'gusrsnteed. The device should not be operated st these limits. The
psramstrlc vsJuss defined In the "Electrlcsl Chsracteristics"
tsbIB si'e1J(Jf.~nlBed st theSbsolute InBxJmum"tIngs.
The ''IIf1COfi7msndBd OpBrsting CdndItiOns" tSbie will define
the conditions for sctusl device operstfon.

If MilitarY/Aerospace specified devices are required.
contact the National Semiconductor Sel.. Offlce/
Distributors for availability and epeclflcaUons.
Supply Voltage
7V
Input Voltage: Control Inputs
Voltage Applied to a Disabled
TRI-STATE Output

7V

5.5V
Operating Free-Air Temperature Range
DM54ALS
-55·Cto + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65"C to + 15O"C

Recommended Operating Conditions
Symbol

DM54ALS541

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS541

Unlta

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2

Vil

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current .

-12

-15

mA

24

mA

70

·C

10l

Low Level Output Current

TA

Free Air Operating Temperature

12
-55

125

0

.'

Electrical Characteristics over recommended free air temperature range
Symbol

Parameter

VIC

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Teat Condltlona

= Min,ll = -18mA
Vee = 4.5V to 5.5V
10H = -0.4mA
10H = -3mA·
Vee = Max
10H = Max
54/74ALS
Vee = Min
10l = 12mA

Min

Typ

Vee

2.4

Vee

IIH

High Level Input Current

III

Low Level Input Current

10ZH

High Level TRI-STATE
Output Current

= Max, VI = 2.7V (Note 1)
= Max, VI = 0.4V (Note 1)
Vee = Max, Vo = 2.7V

10Zl

Low Level TRI-STATE
Output Current

Vee

= Max, Vo = 0.4V

10

Output Drive Current

Vee

= Max, Vo = 2.25V

Icc

Supply Current

Vee

= Max

V

3.2

V

2
0.25

0.4
mA

0.35

= Max, VI = 7V

Input Current at Max
Input Voltage

Unite

Vee- 2

74ALS
10l = 24mA
II

Max
-1.5

0.5
100

!IA

Vee

20

!IA

Vee

-100

"A

20

!IA

-20

!IA

-112

mA

Outputs High
Outputs Low
Outputs Disabled

2·196

-30
6

14

15

25

13.5

22

mA

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

Conditions

From (Input)
To (Output)

DM54ALS541

DM74ALS541

Min

Max

Min

Max

AorB
toY

4

17

4

14

ns

AorB
toY

2

12

2

10

ns

5

18

5

15

ns

8

24

8

20

ns

1

12

1

10

ns

2

14

2

12

ns

tpLH

Propagation Delay TIme
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tPZH

Output Enable Time
to High Level Output

GtoY

tPZL

Output Enable Time
to Low Level Output

GtoY

tpHZ

Output Disable Time
from High Level Output

GtoY

tpLZ

Output DisableTime
from Low Level Output

GtoY

Vee = 4.5Vto 5.5V,
R1 = R2 = 500n,
CL = 50pF
(Note 1)

Unlta

Note 1: See Section 1 for test waveforms and output load.

PI
2-197

National
Semiconductor

_

Corporation

DM54ALS563A/DM74ALS563A Octal D-Type
Transparent Latches with TRI-STATE® Outputs
General Description
These 8-bit registers feature totem-pole TAl-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and incressed high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for Implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight inverting latches of the ALS563A are transparent
O-type latches. While the enable (G) is high the Q outputs
will follow the data (D) inputs. When the enable is taken low
the output will be latched at the complement of the level of
the data that was set up.

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• TAI-STATE buffer-type outputs drive bus lines directly

Connection Diagram
Dual-In-Une Package
~

20
II

-

i

17

eO

II

1&

14

ii

I

GUTM

\0

411

BD

iN.m
II

.
TUF/9162-1

Output
Control

Enable

L
L
L
H

H
H
L

G

X

D

Output

Q

H
L

L
H

X
X

00
Z

L - Low State. H - High State, X - Don't Care
Z

7D

Order Number DM54ALS563AJ, DM74ALS563AWM or DM74ALS563AN
See NS Package Number J20A, M20B or N20A

Function Table

= High Impedance State

00 -

i
12

13

PrevIous Condhlon of c:!

2-198

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Voltage Applied to Disabled Output

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the devic9 cannot b9 guarant99d. The device should not be op9f8ted at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" tabl9 will define
the conditions for actual device operation.

7V
5.5V

Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O·Cto +70·C
Storage Temperature Range
-65·C to + 150·C

Recommended Operating Conditions
Symbol

DM54ALS563A

Parameter

DM74ALS563A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V
V

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.7

0.8

10H

High Level Output Current

-1

-2.6

mA

12

24

mA

2

2

V

10l

Low Level Output Current

tw

Width of Enable Pulse, High or Low

15

15

ns

tsu

Data Setup Time

10,j.

10,j.

ns

tH

Data Hold Time

10,j.

TA

Free Air Operating Temperature

-55

The (

10,j.
125

ns

0

·C

70

J..) arrow indicates the negative edge of the enable is used for reference.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V
Vil = VllMax

VOL

Low Level Output
Voltage

Min
10H = Max

2.4

Typ

Max

Units

-1.5

V
V

3.2

Vee = 4.5V to 5.5V

10H = -400/LA

Vee = 4.5V
VIH = 2V

54174ALS
10l= 12mA

0.25

0.4

V

74ALS
10l = 24mA

0.35

0.5

V

0.1

mA

II

Input Current @ Max.
Input Voltage

Vee = 5.5V, VIH

=

7V

=

2.7V

IIH

High Level Input Current

Vee = 5.5V, VIH

III

Low Level Input Current

Vee = 5.5V, Vil = 0.4V

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

10ZH

Off-State Output Current
High Level Voltage Applied

Vee = 5.5V, VIH
Vo = 2.7V

=

2V

10Zl

Off-State Output Current
Low Level Voltage Applied

Vee = 5.5V, VIH
Vo = 0.4V

=

2V

lee

Supply Current

Vee = 5.5V
Outputs Open

2-199

V

Vee - 2

-30

20

/LA

-0.1

mA

-112

mA

20

/LA

-20

/LA

Outputs High

10

17

mA

Outputs Low

16

26

mA

Outputs Disabled

17

29

mA

fI

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Conditions
Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

From

To

Data

AnyQ

Data

Any 0

Propagation Delay Time
Low to High Level Output

Enable

AnyQ

tpHL

Propagation Delay Time
High to Low Level Output

Enable

AnyO

tpZH

Output Enable Time
to High Level Output

Output
Control

AnyQ

tpZL

Output Enable Time
to Low Level Output

Output
Control

Any 0

tpHZ

Output Disable Time
from High Level Output

Output
Control

Any a

tpLZ

Output Disable Time
from Low Level Output

Output
Control

Anya

Note 1: See Section 1 for test waveforms and output load.

2-200

DM54ALS563A

DM74ALS563A

Units

Min

Max

Min

Max

3

21

3

18

ns

3

15

3

14

ns

8

29

8

22

ns

8

22

8

21

ns

4

21

4

18

ns

4

21

4

18

ns

2

12

2

10

ns

3

18

3

15

ns

.
C

I:

Logic Diagram

CII

IIiiTPilT

~

1

CO.nOl ":"'--~II>--.....,

Iii
CII
G)

10

~

I:
19

20

~

16

40

6

50

7
14

70

30

5

15

60

20

4

CK

50

~

3

17

40

.....

10

Iii
8:
11

3D

.

10

2

60

8
13

70

80~9~________~~

12 80
ENAlLE G ...;1;,.:.1------i.>c........
TL/F/9162-2

2·201

_

National

Semiconductor
Corporatton

DM54ALS564A/DM74ALS564A Octal 0-Type
Edge-Triggered Flip-Flops with TRI-STATE® Outputs
General Description
These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, 110 ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the ALS564A are edge-triggered inverting Ootype flip-flops. On the positive transition of the
clock, the 0 outputs will be set to the complement of the
logic states that were set up at the 0 inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic

levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly

Connection Diagram
Dual-In-Une Package

70

80

CLOCK

11

1
OUTPUT
CONTROL

2
10

3
20

4
30

6
50

5
40

7
60

8
70

9
80

GNO
TUF/6225-1

Order Number DM54ALS564AJ, DM74ALS564AWM or DM74ALS564AN
See NS Package Number J20A, M20B or N20A

Function Table
Output
Control
L
L
L
H

Clock

D

t
t

H
L
X
X

L
X

Output

Q
L
H

00
Z

L - Low State, H - High State, X - Don't Care
t - Positive Edge Transition
Z - High Impedance State

l:io = Previous Condition of l:!

2-202

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Note: The ''Absolute Maximum Ratings" are those values
beyond which the safely of the device cannot be guaran·
t88d. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guarantaad at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V
7V
5.5V

Input Voltage
Voltage Applied to Disabled Output

Operating Free Air Temperature Range
DM54ALS
-55·Cto +125·C
DM74ALS
O"Cto +70·C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM74ALS564A

DM54ALS564A

Parameter

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-1

-2.6

mA

10L

Low Level Output Current

feLoeK

Clock Frequency

tw

Width of Clock Pulse

tsu

2

12
0

I
I

V

2

25

0

24

mA

30

MHz

High

16.5

14

Low

16.5

14

ns

15t

15t

ns

Data Setup Time

tH

Data Hold Time

4t

TA

Free Air Operating Temperature

-55

ns

ns

ot
125

70

0

·C

The (t) arrow indicates the pOSitive edge of the Clock is used for reference.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Conditions

Parameter

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V
VIL = VILMax

VOL

Low Level Output
Voltage

Min
10H = Max

2.4

Typ

Max

Units

-1.2

V

3.2

V

Vee = 4.5V to 5.5V

10H = -400/LA

Vee = 4.5V
VIH = 2V

54/74ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

II

Input Current @ Max
Input Voltage

Vee = 5.5V, VIH = 7V

V

Vee - 2

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

/LA

IlL

Low Level Input Current

Vee = 5.5V, VIL = O.4V

-0.2

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

-112

mA

10ZH

Off·State Output Current
High Level Voltage Applied

Vee = 5.5V, VIH = 2V
Vo = 2.7V

20

/LA

10ZL

Off·State Output Current
Low Level Voltage Applied

Vee = 5.5V, VIH = 2V
Vo = 0.4V

-20

/LA

lee

Supply Current

Vee = 5.5V
Outputs Open

mA

2·203

-30

Outputs High

10

18

Outputs Low

15

24

mA

Outputs Disabled

16

30

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

p4ameter

Conditions

From

To

DM64ALS564A
Min

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

tPHL

Vee = 4.5V to 5.5V
RL = 5000
CL=50pF

Any 0

Propagation Delay Time
High to Low Level Output

Clock

Any 0

Output Enable Time

Output
Control

Any 0

to High Level Output
tpZL

Output Enable Time
to Low Level Output

Output
Control

Any 0

tpHZ

Output Disable Time
from High Level Output

Output
Control

Any 0

tpLZ

Output Disable Time
from Low Level Output

Output
Control

Any 0

Note 1: See SectIon 1 far test waveforms and output load.

~-

"

2·204

DM74ALS564A
Min

Units

Max

30

25
Clock

tpZH

Max

MHz

4

15

4

14

ns

4'

15

4

14

ns

4

21

4

18

ns

4

21

4

18

ns

2

12

2

10

ns

3

17

3

15

ns

2-205

_

National

Semiconductor
Corporation

DM54ALS573B/DM74ALS573B Octal 0-Type Transparent
Latches with TRI-STATE® Outputs
General Description
These S-bit registers feature totem-pole TRI-STATE outputs
designed speCifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, lID ports, bidirectional
bus drivers, and working registers.
The eight latches of the ALS5738 are transparent Ootype
latches. While the enable (G) is high the 0 outputs will follow the data (0) inputs. When the enable is taken low the
output will be latched at the level of the data that was set
up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance

state the outputs neither load nor drive the bus lines Significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally equivalent with LS373
• Improved AC performance over LS373 at approximately
half the power
• TRI-STATE buffer-type outputs drive bus lines directly

Connection Diagram
Dual-In-Llne Package

1
OUTPUT

lQ

2Q

3Q

10

20

3D

CONTROL

4D

50

6Q

7Q

80

50

60

7D

80

ENABLE

TL/F/6226-1

Order Number DM54ALS573BJ, DM74ALS573BWM or DM74ALS573BN
See NS Package Number J20A, M20B or N20A

Function Table

L

Output
Control

Enable

L
L
L

H
H

H
L

L

L

00

H

X

X
X

G

D

Output
Q

H

Z

= Low State, H = High State, X = Don't Care

Z = High Impedance State

aD = Previous Condition of a

2-206

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V

Input Voltage

7V

Voltage Applied to Disabled Output

S.SV

Operating Free Air Temperature Range
DM54ALS
- SSDC to + 12SDC
O"Cto +70"C
DM74ALS
Storage Temperature Range
- 6SDC to + 15O"C

Recommended Operating Conditions
Symbol

DM54ALS573B

Parameter

DM74ALS573B

Units

Min

Nom

Max

Min

Nom

Max

4.S

5

5.5

4.5

5

5.5

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-1

-2.6

mA

24

mA

10L

Low Level Output Current

tw
tsu

Width of Enable Pulse. High

2

2

V
V

12
10

10

ns

Data Setup Time

10J..

10 J..

ns

tH

Data Hold Time

7J..

7J..

TA

Free Air Operating Temperature

-S5

125

70

0

ns
DC

The ( .j.) arrow indicates the negative edge of the enable is used for reference.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Conditions

= 4.SV.11 = -18 mA
Vee = 4.5V
VIL = VILMax
Vee = 4.5V to 5.SV
Vee = 4.SV
VIH = 2V

= 5V. TA = 25DC.

Min

Typ

Vee

10H

= Max

10H

=

-400/LA

2.4

Max

Units

-1.2

V

3.2

V
V

Vee - 2

54174ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

= 5.5V. VIH = 7V

II

Input Current @ Max
Input Voltage

Vee

IIH

High Level Input Current

IlL

Low Level Input Current

10

Output Drive Current

10ZH

Off·State Output Current
High Level Voltage Applied

10ZL

Off·State Output Current
Low Level Voltage Applied

lee

Supply Current

= 5.SV. VIH = 2.7V
= S.5V. VIL = 0.4V
Vee = 5.5V. Vo = 2.25V
Vee = 5.5V. VIH = 2V
Vo = 2.7V
Vee = S.5V. VIH = 2V
Vo = 0.4V
Vee = S.5V

Outputs High

Outputs Open

Outputs Low

Vee

20

/LA

Vee

-0.1

mA

-112

mA

20

/LA

-20

/LA

10

17

mA

15

24

mA

15.5

27

mA

-30

Outputs Disabled

2·207

fI

Switching Characteristics over recommended operating free air temperature range (Note 1).
Symbol

Parameter

Conditions
Vee = 4.5Vto 5.5V
RL = 500n
CL = 50pF

From

To

Data

AnyQ

Data

AnyQ

Propagation Delay Time
Low to High Level Output

Enable

AnyQ

tpHL

Propagation Delay Time
High to Low Level Output

Enable

AnyQ

tpZH

Output Enable Time
to High Level Output

Output
Control

AnyQ

tpZL

Output Enable Time
to Low Level Output

Output
Control

AnyQ

tpHZ

Output Disable Time
from High Level Output

Output
Control

AnyQ

tpLZ

Output Disable Time
from Low Level Output

Output
Control

AnyQ

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Note 1: See Section 1 for test waveforms and output load.

2-208

DM54ALS573B

DM74ALS573B

Min

Max

Min

Max

2

15

2

14

ns

2

15

2

14

ns

8

25

8

20

ns

8

20

8

19

ns

4

21

4

18

ns

4

21

4

18

ns

2

12

2

10

ns

2

18

2

15

ns

Units

Logic Diagram
bUtPUt tblfROl

10-=------.....,
19 10

20

-=-----t-,
18

30

20

....;..-----r-.....,
,,'

17

~-I---<1I.>---- 30

40~----,-.....,

16 40

50....;..----,-.....,
15 50

60

-----r-.
14

60

13

70

12

80

70...;;...----.-,

80

...:....-----jr-,

II
ENABLE G-----IVO,,-TL/F/8226-2

fI
2-209

National

_

Semiconductor
Corporation

DM54ALS574A/DM74ALS574A Octal D-Type
Edge-Triggered Flip-Flops with TRI-STATE® Outputs
General Description
These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the ALS574A are edge-triggered
D-type flip-flops. On the positive transition of the clock, the
outputs will be set to the logic states that were set up at
the D inputs.

a

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally equivalent with LS374
• Improved AC performance over LS374 at approximately
half the power
• TRI-STATE buffer-type outputs drive bus lines directly

Connection Diagram
Dual-In-Llne Package
10

20

50

4Q

30

60

70

80

CLOCK
11

1
OUTPUT

2
10

3
20

4
30

5
4D

CONTROL

6
50

7
60

8
70

9
80

GNO
TUF/6110-1

Order Number DM54ALS574AJ, DM74ALS574AWM or DM74ALS574AN
See NS Package Number J20A, M20B or N20A

Function Table
Output
Control
L
L
L
H
L

Output

Clock

0

t
t

H
L

H
L

L

X
X

00
Z

X

Q

= Low Stata, H = High State, X = Don't Care

t

= PosHlve Edge Transition
Z - High Impedance State
00 - Previous CondHlon Of Q

2-210

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70·C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS574A

Parameter

DM74ALS574A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-1

-2.6

mA

10L

Low Level Output Current

feLOCK

Clock Frequency

tw

Width of Clock Pulse

tsu

2

2

I
I

V

12
0

28

V

0

24

mA

35

MHz

High

16.5

14

Low

16.5

14

ns

15t

15t

ns

Data Setup Time

tH

Data Hold TIme

4t

TA

Free Air Operating Temperature

-55

ns

ns

ot
125

70

0

·C

The ( t) arrow indicates the positive edge of the Clock is used for reference.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Conditions

= 4.5V,11 = -18 mA
Vee = 4.5V
10H = Max
VIL = VILMax
Vee = 4.5V to 5.5V
10H = -400/LA
54174ALS
Vee = 4.5V
10L = 12mA
VIH = 2V

Min

=

=

II

Input Current at Max
Input Voltage

Vee

= 5.5V, VIH = 2.7V
= 5.5V, VIL = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V, VIH = 2V
Vo = 2.7V
Vee = 5.5V, VIH = 2V
Vo = 0.4V
Outputs High
Vee = 5.5V

IIH

High Level Input Current
Low Level Input Current

10

Output Drive Current

10ZH

Off-State Output Current
High Level Voltage Applied

10ZL

Off-State Output Current
Low Level Voltage Applied

lee

Supply Current

5V, TA
Typ

Vee

2.4

5.5V, VIH

=

25·C.
Max

Units

-1.2

V

3.2

V
V

Vee - 2

74ALS
10L = 24mA

IlL

=

0.25

0.4

V

0.35

0.5

V

0.1

mA

7V

Vee

20

/LA

Vee

-0.2

mA

-112

mA

20

/LA

-20

/LA

11

18

mA

Outputs Low

17

27

mA

Outputs Disabled

17

28

mA

Outputs Open

2-211

-30

fI

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay TIme
Low to High Level Output

tPHL
tpZH

Conditions
V(X;. = 4.5V to 5.5V
RL = 500n
CL = 50pF

From

To

DM74ALS574A

Min

Min

Max

28
Clock

AnyQ

Propagation Delay Time
High to Low Level Output

Clock

AnyQ

Output Enable Time
to High Level Output

Output
Control

AnyQ

Output Enable TIme

Output
Control

AnyQ

to Low Level Output
tpHZ

Output Disable TIme
from High Level Output

Output
Control

AnyQ

tpLZ

Output Disable Time
from Low Level Output

Output
Control

AnyQ

tpZL

DM54ALS574A

Note 1: See SectIon 1 for test waveforms and output load.

2-212

Units

Max
MHz

35

4

22

4

14

ns

4

17

4

14

ns

4

21

4

18

ns

26

4

18

ns

2

16

2

10

ns

2

25

2

12

ns

4
J/.

c

~

Logic Diagram
OUTPUT
CONTROL

10

en
~
J>

1

r-

rn

en
......
~
J>
C

....

2

CK

ZO

19

3

~

J>

0"

"0

30

16

40

6

Ci

60

17

5

CK

50

ZO

4

CK

40

~

J>

rrn
en
......
18

3D

~
......
10

ij

15

Q

14 60

Q

13 70

ij

lZ

50

7

Ci

70

8

Ci

80

9

Ci

80

CLOCK 11
TL/F/6110-2

PI
2-213

It

National

Semiconductor
Corporation

DM54ALS576A/DM74ALS576A Octal 0-Type
Edge-Triggered Flip-Flops with TRI-STATE® Outputs
General Description
These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, 1/0 ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the ALS576A are edge-triggered inverting Ootype flip-flops. On the positive transition of the
clock, the 0 outputs will be set to the complement of the
logic states that were set up at the 0 inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic

levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced OXide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly

Connection Diagram
Dual-In-Line Package

50

60

50

60

BO

CLOCK

BO

GNO

1
OUTPUT

20

10

CONTROL

40

30

70

TL/F/6228-1

Order Number DM54ALS576AJ, DM74ALS576AWM or DM74ALS576AN
See NS Package Number J20A, M20B or N20A

Function Table
Output
Control
L
L
L
H

Output

Clock

D

t
t

H

L

L

H

L

X
X

00

X

Q

Z

L = Low State, H = High State, X = Don't Care

t = Positive Edge Transition
Z = High Impedance State

c:io =

Previous Condition of c:i

2-214

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Voltage Applied to Disabled Output

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be gusran·
t66d. The device should not be operated at th6Selimits. The
parametric values defined in the "Electrical Characteristics"
table are not guarant66d at the absolute maximum ratings.
The "Recommend6d Operating Conditions" table will define
the conditions for actual device operation.

5.5V

Operating Free Air Temperature Range
DM54ALS
- 55'C to + 125'C
DM74ALS
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C

Recommended Operating Conditions
Symbol

DM54ALS576A

Parameter

DM74ALS576A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.7

0.8

V
mA

2

2

V

IOH

High Level Output Current

-1

-2.6

IOl

Low Level Output Current

12

24

mA

feloeK

Clock Frequency

30

MHz

tw

Width of Clock Pulse

tsu

0

I
I

25

0

High

20

16.5

Low

20

16.5

ns

15t

15t

ns

Data Setup Time

tH

Data Hold Time

4t

TA

Free Air Operating Temperature

-55

ns

ns

ot
125

0

70

'C

The (t) arrow indicates the positive edge of the Clock is used for reference.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Conditions

= 4.5V, II = -18 mA
Vce = 4.5V
IOH = Max
Vil = VllMax
Vee = 4.5V to 5.5V
IOH = -400/J-A
54174ALS
Vee = 4.5V
IOl = 12mA
VIH = 2V

Min

=

5V. TA

Typ

Vee

2.4

=

25'C.

Max

Units

-1.2

V
V

3.2

V

Vee - 2
0.25

0.4

V

0.35

0.5

V

0.1

mA

Vee

20

Vee

-0.2

/J- A
mA

-112

mA

20

IJ-A

-20

/J-A

74ALS
IOl = 24mA

=

=

II

Input Current @ Max
Input Voltage

Vee

IIH

High Level Input Current

III

Low Level Input Current

10

Output Drive Current

IOZH

Off·State Output Current
High Level Voltage Applied

10Zl

Off·State Output Current
Low Level Voltage Applied

lee

Supply Current

= 5.5V, VIH = 2.7V
= 5.5V, Vil = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V, VIH = 2V
Vo = 2.7V
Vee = 5.5V, VIH = 2V
Vo = O.4V
Outputs High
Vee = 5.5V

5.5V. VIH

7V

Outputs Open

2·215

-30

10

18

mA

Outputs Low

15

24

mA

Outputs Disabled

16

30

mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
Symbol

Parameter

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Conditions
Vee = 4.5V to 5.5V
RL = 5000.
CL = 50pF

From

To

DM54ALS576A

DM74ALS576A

Min

Min

Max

25
Clock

Any a

Propagation Delay Time
High to Low Level Output

Clock

AnyQ

tpZH

Output Enable Time
to High Level Output

Output
Control

Anya

tpZL

Output Enable Time
to Low Level Output

Output
Control

Anya

tpHZ

Output Disable Time
from High Level Output

Output
Control

Anya

tpLZ

Output Disable Time
from Low Level Output

Output
Control

AnyQ

Note 1: See Section 1 for test waveforms and output load.

2-216

Units

Max

30

MHz

4

15

4

14

ns

4

15

4

14

ns

4

21

4

18

ns

4

21

4

18

ns

2

12

2

10

ns

3

17

3

15

ns

c

a:
en

Logic Diagram

~

DliTflII

:I>

1

~
en
.....

CORUOt

10

~
.....
C
a:
.....

2
19 Ii

~

:I>
21

30

CD

50

60

70

rU)

3

en
.....

18

~

17

3i

16

40

15

50

I'

60

~

•
5

6

7

I
13 7i

80 9
12

&i

CLOCK II
TL/F/6228-2

2-217

National

~ Semiconductor
CorporaHon

DM54ALS580A/DM74ALS580A Octal 0-Type
Transparent Latches with TRI-STATE® Outputs
General Description
These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, 110 ports, bidirectional
bus drivers, and working registers.
The eight inverting latches of the ALS580A are transparent
Ootype latches. While the enable (G) is high the Q outputs
will follow the complement of the data (0) inputs. When the
enable is taken low the output will be latched at the complement of the level of the data that was set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic

levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• Switching specifications at 50 pF
• SWitching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly

Connection Diagram
Dual-In-Una Package

50

60

50

60

80

ENABLE

80

GNO

1

OUTPUT
CONTROL

20

10

40

3D

70

TlIF/6229-'

Order Number DM54ALS580AJ, DM74ALS580AWM or DM74ALS580AN
See NS Package Number J20A, M20B or N20A

Function Table
Output
Control

Enable

L
L
L
H

H
H
L

G

X

L = Low State. H = High Stele, X
Z = High Impedance State

00 =

Previous Condition of 0

2-218

D

Output
~

H
L

L
H

X
X

Co
Z

= Don't care

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specHications.
Supply Voltage
Input Voltage

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V
7V

Voltage Applied to Disabled Output

5.5V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS580A

Parameter

DM74ALS580A

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Units

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-1

-2.6

mA

24

mA

2

2

10l

Low Level Output Current

tw
tsu

Width of Enable Pulse, High or Low

tH

V

12
15

15

ns

Data Setup Time

10i

10i

ns

Data Hold Time

10i

Free Air Operating Temperature
TA
The (,j.) arrow Indicates the negative edge 01 the enable Is used for reference.

125

0

Electrical Characteristics
Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Conditions

= 4.5V,11 = -18 mA
Vee = 4.5V
Vil = VllMax
Vee = 4.5V to 5.5V
Vee = 4.5V
VIH = 2V

ns

10i

-55

over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

V

=

Min

70

5V, TA

=

Typ

Vee

II

Input Current @ Max
Input Voltage

Vee

=

5.5V, VIH

=

10H

=

Max

10H

=

-400 ",A

2.4

·C

25·C.
Max

Units

-1.2

V

3.2

V

Vee- 2

V

54/74ALS
10l = 12mA

0.25

0.4

V

74ALS
IOl = 24mA

0.35

0.5

V

0.1

mA

7V

= 5.5V, VIH = 2.7V
= 5.5V, Vil = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V, VIH = 2V
Vo = 2.7V
Vee = 5.5V, VIH = 2V
Vo = 0.4V
Vee = 5.5V

Outputs High

10

17

mA

Outputs Open

Outputs Low

16

26

mA

Outputs Disabled

17

29

mA

IIH

High Level Input Current

Vee

20

",A

III

Low Level Input Current

Vee

-0.1

mA

10

Output Drive Current

-112

mA

10ZH

Off·State Output Current
High Level Voltage Applied

20

",A

10Zl

Off·State Output Current
Low Level Voltage Applied

-20

",A

Icc

Supply Current

2-219

-30

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

From

To

Data

Any 0

Data

Any a

Propagation Delay Time
low to High level Output

Enable

Anya

tpHL

Propagation Delay Time
High to low level Output

Enable

Any 0

tpZH

Output Enable Time
to High level Output

Output
Control

Any 0

tpZL

Output Enable Time
to low level Output

Output
Control

Any a

tpHZ

Output Disable Time
from High level Output

Output
Control

Any a

tpLZ

Output Disable Time
from low level Output

Output
Control

Any a

tpLH

Propagation Delay Time
low to High level Output

tpHL

Propagation Delay Time
High to low level Output

tpLH

Vee = 4.SV to S.SV
RL = soon
CL = 50pF

Note 1: See Section 1 for lest waveforms and output load.

2-220

DM54ALS580A

DM74ALS580A

Min

Max

Min

Max

3

21

3

18

ns

3

15

3

14

ns

8

29

8

22

ns

8

22

8

21

ns

4

21

4

18

ns

4

21

4

18

ns

2

12

2

10

ns

3

18

3

15

ns

Units

Logic Diagram
~

_1~____~>-

____

~

CONTROL

10

ZO

3D

Z

19

1lI

18

2li

....:1..:....7

3li

3

4

1-+__OC>-_ _

2-221

_

National

PRELIMINARY

Semiconductor
Corporation

DM54ALS590/DM74ALS590

8-Bit Binary Counter with
Output Registers
General Description
These devices each contain an 8-bit binary counter that
feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and the storage register. The binary counter
features a direct clear input (CCLR) and a count enable input (CCKEN). For cascading, a ripple carry output (ROO) is
provided. Expansion is easily accomplished for two stages
by connecting RCO of the first stage to CCKEN of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to CCK of the
following stage.

Both the counter and register clocks are positive edge triggered. If the user wishes to connect both clocks together,
the counter state will always be one count ahead of the
register. Internal circuitry prevents clocking from the clock
enable.

Features
• Advanced oxide-isolated ion-implanted Schottky TTL
process
• Switching performance is guaranteed over full temperature and Vee supply range

Connection Diagram
QB- 1

'-'

16 -VCC

QC- 2

15 -QA

QO- 3

14

QE- 4

13 -RCK

QF- 5

12 -CCKEN

-Ii

QG- 6

ll-CCK

QH- 7

10 -CCLR

GNO- 8

9 r-RCO
TL/F/9167-1

Order Number DM54ALS59OJ or DM74ALS590M, N
See NS Package Number J16A, M16A or N16A

This document contains Information on a product under developmenl NSC reserves the right to change or discontinue this product without notice.

2-222

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications_
Supply Voltage

7V

Input Voltage

7V

Voltage Applied to Disabled Output

5.5V

Operating Free-Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O·Cto +70"C
Storage Temperature Range

-65·C to + 15O"C

Recommended Operating Conditions
Symbol

DM54ALS590

Paremeter

DM74ALS590

Unlta

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

0.8

V

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

IOH

High Level Output
Current

~

-1

-1

a

-1

-2.6

Low Level Output
Current

~

8

16

a

12

24

IOl

2

V

2
0.7

mA

mA

feeK

Counter Clock Frequency

0

0

MHz

fReK

Register Clock Frequency

0

0

MHz

tw(CCK)

Width of Counter Clock Pulse

ns

tw(CCLR)

Width of Counter Clear Pulse

ns

tw(RCK)

Width of Register Clock Pulse

ns

tsu

Setup Time

CCKEN Low before CCK P
CCLR Inactive before CCK P

ns

CCK before RCK P (Note 1)
~ Low afterCCK P

tH

Hold Time

TA

Free Air Operating Temperature

ns
-55

125

0

70

·C

Note 1: This setup time ensures the register will see stable data from the counter outputs. The clocks may be tied together in which case the register state will be
one clock pulse behind the counter.

Electrical Characteristics over recommended free air temperature range
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

IOZH

IOZl

Low Level Output
Voltage

Test Conditions

=
Vee =
Vee =
Vee =
Vee

Min. II

=

4.5 to 5.5V. IOH
Min. IOH
Min

Min

Typ

-18 mA

=

=

-0.4 mA

Max

Max

Units

-1.5

V

Vee - 2
2.4

V
3.2

54174ALS
IOl = 12mA

0.25

0.4

74ALS
IOl = 24mA

0.35

0.5

V

Off-State Output Current
With High Level Voltage
Applied

Vee = Min. Vil = Max.
VIH = Min. Vo = 2.7V

20

/loA

Off-State Output Current
With Low Level Voltage
Applied

Vee = Min. Vil = Max.
VIH = Min. Vo = 0.4V

-20

p.A

2-223

PI

Electrical Characteristics over recommended free air temperature range (Continued)
Symbol

Parameter

Test Conditions

II

Input Current at Max
Input Voltage

Vee

Typ

Min

= Max, VI = 7V

= Max, VI = 2.7V
= Max, VI = 0.4V
Vee = Max, Vo = 2.25V
Outputs High
Vee = Max

Max

Units

100

/J- A

IIH

High Level Input Current

Vee

20

IlL

Low Level Input Current

Vee

-100

IJ.A
IJ.A

10

Output Drive Current

-112

mA

lee

Supply Current

-30
33

Outputs Low

46

Outputs Disabled

44

mA

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

Conditions
Vee = 4.5 to 5.5V,
RL = 4800,
Rl = R2 = 5000,
TA = Min to Max

From (Input)
To (Output)

DM54ALS590

DM74ALS590

Min

Min

Max

Units

Max

CCKto~

MHz

CCKtoRCO

ns

CCKtoROO

ns

oro:i
to~

ns

tpLH

Propagation Delay Time
Low to High Level Output

RCKtoQ

ns

tpHL

Propagation Delay Time
High to Low Level Output

RCKtoQ

ns

tpLH

Propagation Delay Time
Low to High Level Output

GtoQ

ns

tpHL

Propagation Delay Time
High to Low Level Output

GtoQ

ns

tpZH

Output Enable Time
to High Level Output

GtoQ

ns

tpZL

Output Enable Time
to Low Level Output

GtoQ

ns
"

tpHZ

Output Disable Time
from High Level Output

GtoQ

ns

tpLZ

Output DisableTime
from Low Level Output

GtoQ

ns

Nole 1: See Section 1 for test waveforms and output load.

.'

2-224

c

iii:

Logic Diagram

U1
~

:J>
r-

G

en
U1
CD

RCK

.....

<:)

C

iii:

.....

CCKEN

~

RCO

:J>
r-

en
U1

CCK

CD
<:)

QA
CCLR

QB

TL/F/9167-2

2·225

_

National

PRELIMINARY

Semiconductor
Corporation

DM54ALS620A/DM74ALS620A
Octal TRI-STATE® Bus Transceiver
General Description

Features

This advanced low power Schottky device contains 8 pairs
of TRI-STATE logic elements configured as an octal bus
transceiver. It is designed for use in memory, microprocessor systems and in asynchronous bidirectional data buses.
Data transmission from the A bus to the B bus or from the B
bus to the A bus is selectively controlled by (GBA and GAB)
the enable inputs. These inputs are also used to disable the
devices so that the buses are effectively isolated.
The dual-enable configuration gives the ALS620A the capability to store data by simultaneous enabling of GBA and
GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and
all other data sources to the two sets of bus lines are at high
impedance, both sets of bus lines will remain at their last
logiC states.

• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE outputs on A and B buses
• Local bus-latch capability
• Switching specifications into 5000/50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Low output impedance to drive terminated transmission
lines to t330

Connection Diagram
Dual-In-Line Package

I

~

~

GAB

lA

a

m

B

q

~

9

n

9

2A

3A

4A

5A

BA

7A

BA

GND

TUF/6230-1

Order Number DM54ALS620AJ, DM74ALS620AN or DM74ALS620AWM
See NS Package Number J20A, M20B or N20A

Function Table
Enable Inputs

Operation

GBA

GAB

L
H
H
L

L
H
L
H

H = High Logic Level, L
HI-Z = High Impedance

B Data to A Bus

A Data to B Bus
Hi-Z

B Data to A Bus
A Data to B Bus

= Low Logic Level

This document centsins infonmation on a product under development. NSC reserves the right to change or discontinue this product without notice.

2-226

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guarantaed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device oparation.

If Mllitary/Aeroapace specified devices are required,
contact the National Semiconductor Seles Offlcel
Distributors for availability and specifications..
Supply Voltage
7V
Input Voltage
Enable Inputs
7V
1/0 Ports
5.5V
Operating Free Air Temperature Range
DM54ALS
- 55'C to + 125'C
DM74ALS
O"Cto +70"C
Storage Temperature Range
- 65'C to + 150"C

Recommended Operating Conditions
Symbol

DM74ALS620A

DM54ALS620A

Parameter

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

V

2

2

10H

High Level Output Current

-12

-15

mA

10L

Low Level Output Current

12

24

mA

TA

Free Air Operating Temperature

70

'C

-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

DM54ALS620A

Conditions

Min
VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

II

Input Current at
Max Input Voltage

IIH

High Level
Input Current

= 45V, liN = -18 mA
Vee = 4.5V, 10H = -3mA
Vee = 4.5V, 10H = Max
10H = -0.4 mA,
VOL = 4.5V to 5.5V
Vee = 4.5V
10L = 12mA
10L = 24mA
Vee = 5.5V, VIN = 7V
(VIN = 5.5V for A or B Ports)
Vee = 5.5V,
VIN = 2.7V

Typ

=

5V, TA

=

Max

Min

Typ

2.4

3.2

2.4

2

2

Vee -2

Vee - 2
0.25

Units

Max
-1.5

-1.5

Vee

25'C.

DM74ALS620A

3.2

V
V
V
V

0.25

0.4

V

0.35

0.5

V

0.1

0.1

mA

20

20

/LA

-0.1

-0.1

mA

-112

mA

0.4

(Note 1)
Low Level Input
Current

Vee = 5.5V,
VIN = 0.4V
(Note 1)

10

Output Drive Current

Vee

lee

Supply Current

Vee

IlL

=
=

5.5V, VOUT
5.5V

=

2.25V

-112

-30

-30

Output High

24

39

24

34

mA

Output Low

25

49

31

44

mA

TRI-STATE

27

52

33

47

mA

Note 1: For 1/0 ports, the parameters IIH and IlL Include the oIf-state current (lOZH, lozLI.

2-227

Switching Characteristics over recommended operating free air temperature range. (Notes 1 and 2)
Symbol

Circuit
Configuration

Parameter

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tPZL

Output Enable Time to Low Level Output

tpZH

Output Enable Time to High Level Output

tpLZ

Output Disable Time from Low Level Output

tpHZ

Output Disable Time from High Level Output

tPZL

Output Enable Time to Low Level Output

tPZH

Output Enable Time to High Level Output

tpLZ

Output Disable Time from Low Level Output

tpHZ

Output Disable Time from High Level Output

DM74ALS620A

Units

Min

Max

Min

Max

2

12

2

10

ns

2

12

2

10

ns

2

12

2

10

ns

B

2

12

2

10

ns

'~

5

31

5

25

ns

3

23

3

17

ns

3

22

3

18

ns

2

14

2

12

ns

~
A
B

~A

aBA

OUT

A

'~

GAB

OUT

B

Note 1: See Section 1 for test waveforms and output load.

Note 2: Switching characteristic conditions are Vee

DM54ALS620A

= 4.5V to 5.5V, Rl

= R2

= soon, CL = 50 pF.

2·228

5

31

5

25

ns

3

23

3

18

ns

3

22

3

18

ns

2

14

2

12

ns

National

~ Semiconductor
CorporaHon

DM54ALS640A/DM74ALS640A
Inverting Octal Bus Transceivers
General Description

Features

These inverting octal bus transceivers are designed for
asynchronous two-way communication between data busses. These devices transmit data from the A bus to the B
bus or from the B bus to the A bus depending upon the level
at the direction control (DIR) input. The enable input (G) can
be used to disable the device so the busses are effectively
isolated.

• Advanced Oxide-isolated lon-implanted Schottky TTL
process
• Switching performance is guaranteed over full temperature and Vee supply range
• SWitching performance specified at 50 pF
• PNP input design reduces input loading

Connection and Logic Diagrams
vee G

Bl

B2

B3

B4

B5

B6

B7

88

I:~ :" :" :" :" :" :" :" :" :'1
1
2
3
4
5
6
7
8
9
10
DIR AI A2 A3 A4 A5 A6 A7 A8 GND

TL/F/B640-1

Order Number DM54ALS640AJ, DM74ALS640AWM or DM74ALS640AN
See NS Package Number J20A, M20B or N20A

G-------.

DIR

~8

TL/F 18640-2

Function Table
Control
Inputs
G

L

Operation
DIR

L

L

B Data to A Bus

L

H

A Data to B Bus

H

x

Isolation

= Low Logic Level

H ~ High Logic Level
X

~

Etlher Low or High Logic Level

2-229

PI

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage; Control Inputs
1/0 ports

Note 1: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V
5.5V

Operating Free Air Temperature Range
DM54ALS
- 55°C to + 125°C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65°C to + 150"C

Recommended Operating Conditions
Symbol

DM54ALS640A

Paremeter

DM74ALS640A

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

2

V

2

10H

High Level Output Current

-12

-15

mA

10L

Low Level Output Current

12

24

mA

TA

Operating Free Air Temperature Range

70

°C

-55

125

0

Electrical Characteristics Over Recommended Free Air Temperature Range
Symbol

Parameter

Test Conditions

DM74ALS640A

Min

Min

Typ Max

Input Clamp Voltage

High Level Output Voltage Vee = 4.5 to 5.5V 10H = -0.4mA

Vee = Min, 11= -18 mA

Vee = Max

Vee- 2

IOH=-3mA
10H = Max

Low Level Output Voltage Vee = Min

2.4

3.2

-1.5

2.4

2

Input Current at
Maximum Input Voltage

Vee = Max.

V

3.2

V

2
0.25

10L = 12 mA

Units

Max

Vee - 2

0.4

10L = 24mA
II

Typ

-1.5

Vie
VOH

VOL

DM54ALS640A

0.25

0.4

0.35

0.5

1/0 Ports, VI = 5.5V

100

100

Control Inputs, VI = 7V

100

100

V
".A

IIH

High Level Input Current

Vee = Max, VI = 2.7V (Note 2)

20

20

IlL

Low Level Input Current

Vee = Max, VI = 0.4V (Note 2)

-100

-100

".A

10

Output Drive Current

Vee = Max, Vo = 2.25V

-112

mA

lee

Supply Current

Vee = Max

-30

-112

-30

Outputs High

19

35

Outputs Low

27

45

27

40

28

48

28

43

Outputs Disabled
Note 2: For 1/0 ports, IIH and IlL parameters Include the TRI-STATE output current (IOZL and IOZH).

2-230

19

".A

30
mA

Switching Characteristics Over Recommended Operating Free Air Temperature Range
Symbol

Parameter

From
To
(Input) (Output)

Conditions

Vee = 4.5 to 5.5V,
CL = 50pF,
R1 = R2 = 500n
(Note 1)

DM54ALS640A

DM74ALS640A

Units

Min

Max

Min

Max

2

14

2

11

ns

2

13

2

10

ns

tpLH

Propagation Delay Time Low to
High Level Output

AorB

BorA

tpHL

Propagation Delay Time High to
Low Level Output

AorB

BorA

tPZH

Output Enable Time to High Level Output

G

AorB

5

25

5

21

ns

tPZL

Output Enable Time to Low Level Output

G

AorB

8

27

8

24

ns

tpHZ

Output Disable Time from
High Level Output

G

AorB

2

12

2

10

ns

tpLZ

Output Disable Time from
Low Level Output

G

AorB

3

20

3

15

ns

Note 1: See Section 1 for test waveforms and output load.

•

2·231

II

National

SemIconductor

Corporation

DM54ALS645A/DM74ALS645A Octal Bus Transceivers
General Description

Features

These octal bus transceivers are designed for asynchronous two-way communication between data busses. These
devices transmit data from the A bus to the B bus or from
the B bus to the A bus depending upon the level at the
direction control (DIR) input. The enable input (G) can be
used to disable the device so the busses are effectively
isolated.

• Advanced Oxide-isolated lon-implanted Schottky TTL
process
• SWitching performance is guaranteed over full temperature and Vee supply range
• SWitching performance specified at 50 pF
• PNP input design reduces input loading

Connection and Logic Diagrams
~

~

~

~

H

~

~

"

~

~

I

:m :" :" :17 :" :" :" :" :" :'1

1
2
3
4
5
6
7
8
9
10
DIR AI A2 A3 A4 AS A6 A7 A8 GND

TLIF/9304-1

Order Number DM54ALS645AJ, DM74ALS645AWM or DM74ALS645AN
See NS Package Number J20A, M20B or N20A
'ALS645A

il----"'I

TO SEVEN OTHER TRANSCEIVERS

Function Table
Control
Inputs
G

Operation
DIR

L

L

B Data to A Bus

L

H

A Data to B Bus

H

x

Isolation

Low = Low Logic Level
High = High Logic Level
X = Either Low or High Logic Level

2-232

TLIF/9304-2

Absolute Maximum Ratings (Note)
Note: The "Absolute Meximum Ratings" are those values
beyond which the safety of the device cannot be guarenteed. The device should not be operated at these Omits. The
parametric values defined in the "Electrical Characteristics"
table ara not guaranteed at the absolute meximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and speclffcatlon..
Supply Voltage
7V
Input Voltage; Control Inputs
7V
110 ports
5.5V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O·Cto +70"C
Storage Temperature Range
-65·C to + 150"C

Recommended Operating Conditions
Symbol

DM54ALS645A

Parameter

DM74ALS645A

Unlta

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-12

-15

rnA

24

mA

70

·c

2

10L

Low Level Output Current

TA

Operating Free Air Temperature Range

2

V

12
-55

125

0

Electrical Characteristics Over Recommended Free Air Temperature Range
Symbol

Parsmeter

Test Conditions

DM74ALS645A
Min

Typ Max

Input Clamp Voltage

VOH

High Level Output Voltage Vee = 4.5 to 5.5V 10H = -0.4mA
Vee = Max

2.4

Low Level Output Voltage Vee = Min

3.2

2.4

2

10H = Max

0.4

10L = 24mA
II

IIH

3.2

V

0.25

0.4

0.35

0.5

1/0 Ports, VI = 5.5V

100

100

Control Inputs, VI = 7V

100

100

20

20

Input Current at
Maximum Input Voltage

Vee = Max

High Levell nput Current

Vee = Max, VI = 2.7V (Note 2)

IlL

Low Level Input Current

Vee = Max, VI = 0.4V (Note 2)

10

Output Drive Current

Vee = Max, Vo = 2.25V

lee

Supply Current

Vee = Max

-100
-30

-112

-30

p.A

pA
rnA

30

48

30

45

36

60

36

55

Outputs Disabled

38

63

38

58

2·233

pA

-100

Outputs High

-

V

-112

Outputs Low
Note 2: For 1/0 ports, IIH and IlL parameters include \he TRI·STATE'" output current (loZL and 10ZH).

V

2
0.25

10L = 12mA

-1.5
Vee- 2

Vee - 2

IOH=-3mA

Units

Typ Max

-1.5

Vee = Min, 11= -18 mA

Vie

VOL

DM54ALS645A
Min

mA

Switching Characteristics Over Recommended Operating Free Air Temperature Range
Symbol

Parameter

From
(Input)

To
(Output)

tpLH

Propagation Delay Time
Low to High Level Output

AorB

BorA

tPHL

Propagation Delay Time
High to Low Level Output

AorB

BorA

tpZH

Output Enable Time to
High Level Output

G

AorB

tpZL

Output Enable Time to
Low Level Output

G

AorB

tpHZ

Output Disable Time from
High Level Output

G

AorB

tpLZ

Output Disable Time from
Low Level Output

G

AorB

Conditions
Vee = 4.5 to 5.5V,
CL = 50pF,
R1 = R2 = 500n
(Note 1)

Note 1: See SectIon 1 for Test Waveforms and Output Load.

2·234

DM54ALS645A

DM74ALS845A

Units

Min

Max

Min

Max

1

15

3

10

ns

1

13

3

10

ns

2

30

5

20

ns

2

29

5

20

ns

2

14

2

10

ns

2

30

4

15

ns

r------------------------------------------------------------------.c
_

~
PRELIMINARY en

National
Semiconductor
Corporation

:=

DM54ALS646/DM74ALS646 Octal TRI-STATE® Bus
Transceivers and Registers
General Description
This device incorporates an octal bus transceiver and an
octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus.

break" configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between store and real-time data.

This bus transceiver features totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and
increased high-logic level drive provides this device with the
capability of being connected directly to and driving the bus
lines in a bus-organized system without the need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, 110 ports, bidirectional
bus drivers, and working registers.

The enable G and direction control pins provide four modes
of operation: real-time data transfer from bus A to B, realtime data transfer from bus B to A, real-time bus A andlor B
data transfer to internal storage, or internally stored data
transfer to bus A or B.

The registers in the ALS646 are edge-triggered D-type flipflops. On the positive transition of the clock (CAB or CBA),
the input bus data is stored into the appropriate register.
The CAB input controls the transfer of data into the A register and the CBA input controls the B register.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A low
input level selects real-time data, and a high level selects
stored data. The select controls have a "make before

I
c

II:

~

Ii&

When the enable G pin is low, the direction pin selects
which bus receives data. When the enable G pin is high,
both buses become disabled yet their input function is still
enabled.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• TRI-STATE buffer outputs drive bus lines directly
• Multiplexed real-time and stored data
• Independent registers for A and B buses

Connection Diagram
CAB- 1
SAB- 2

24 I-Vcc
23 I-CBA

DIR- 3

22 r-SBA

Al- 4

21 r-G

A2- 5

20 r-Bl

A3- 6

19 r-B2

A4- 7

181-B3

A5- 8

17 I- B4

A6- 9

161-B5

A7- 10
A8- 11

141-B7

GND- 12

131-B8

15 r-B6

TUF/9172-1

Order Number DM54ALS646J or DM74ALS646WM, N
See NS Number Package J24A, M24B or N24A

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

2-235

fI

Absolute Maximum Ratings
Note: The "Absolute MBXimum Ratings" are thos9 values
beyond which the safety of the device cannot be guarantB6d. The device should not be operated at thes8limits. The

If Military/Aeroapace specified davlcel are required,
contact the National Semiconductor Sel.. OffIce/
Dlatrlbutora for availability and apeclflClltlona.
Supply Voltage
7V
Input Voltage
Control Inputs
7V
1/0 Ports
5.5V
Operating Free-Air Temperature Range
DM54ALS
-55"C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-85"Cto +15O"C

paremetric valuss defined in the "Electrical Characteristics"
table are not guarenteed at the absolute maximum ratings.
The "R8COfTImended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

DM54ALS648

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS646

Unlta

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2

Vil

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-12

-15

mA

10l

Low Level Output Current

fClK

Clock Frequency

12

tw

Pulse Duration, Clocks Low or High

14.5

12.5

ns

tau
IH

Data Setup Time, A before CAB or B before CBA

15t

10t

ns

0

Data Hold Time, A after CAB or B after CBA

35

ot

Free Air Operating Temperature
t - WIth reference to the low to high transition of the respective clock.

TA

0

24

mA

40

MHz

ns

ot

-55

125

0

70

·C

Max

Unlta

-1.2

V

Electrical Characteristics over recommended free air temperature range
Symbol

Parameter

Min

Teat Conditione

VIC

Input Clamp Voltage

VOH

High Level Output
Voltage

= Min,ll = -18 mA
Vee = 4.5V to 5.5V
10H = -0.4mA
Vee = Min
10H = -3mA
IOH = Max

Low Level Output

Vee

VOL

Voltage

= Min

= Max

Input Current at Maximum
Input Voltage

Vee

IIH

High Level Input Current

Vee

III

Low Level Input
Current

Vee = Max,
VI = 0.4V, (Note 1)

10

Output Drive Current

Vee

lee

Supply Current

II

Typ

Vee

Vee- 2
2.4

3.2

2

54174ALS
10l = 12mA

0.25

74ALS
10l = 24mA

0.35

1/0 Ports, VI

V

0.4
V

= 5.5V
= 7V

0.5
100

Control Inputs, VI

= Max, VI = 2.7V (Note 1)

20

Control Inputs

-200

1/0 Ports

-200

= Max, Vo = 2.25V
Outputs High
Vee = Max

-30

-112
47
55

88

Outputs Disabled

55

88

2·238

p.A
p.A
mA

78

Outputs Low
Note 1: For 110 ports the TRI-STATE output currents (l0ZH and lozu are Included In the IIH and IlL parameters.

p.A

100

mA

Switching Characterlstlea over recommended operating free air temperature range
Symbol

Parameter

DM54ALS646

DM74ALS646

Min

Max

Min

Max

CBAorCAB
toAorB

10

35

10

30

ns

CBAorCAB
toAorB

5

20

5

17

ns

AorBto
BorA

5

22

5

20

ns

3

15

3

12

ns

CondIIIonI

From (Input)
To (Output)

Vee = 4.5V to 5.5V,
CL - 5OpF,
R1 ". R2

Units

tpLH

Propagation Delay TIme
Low to High Level Output

tpHL

Propagation Delay TIme
High to Low Level Output

tpLH

Propagation Delay TIme
Low to High Level Output

tpHL

Propagation Delay TIme
High to Low Level Output

AorBto
BorA

tpLH

Propagation Delay TIme
Low to High Level Output
(with A or B Low) (Note 2)

SBAorSAB
toAorB

15

40

15

35

ns

Propagation Delay TIme
High to Low Level Output
(with A or B Low) (Note 2)

SBA or SAB
toAorB

5

23

5

20

ns

Propagation Delay TIme
Low to High Level Output
(with A or B High) (Note 2)

SBA or SAB
toAorB

8

30

8

25

ns

Propagation Delay TIme
High to Low Level Output
(with A or B High) (Note 2)

SBA or SAB
toAorB

5

24

5

20

ns

3

20

3

17

ns

5

22

5

20

ns

1

12

1

10

ns

2

20

2

16

ns

tPHL

tpLH

tpHL

= SOOO,

TA'" Minto Max
(Note 1)

~to

Output Enable TIme
to High Level Output

AorB

Output Enable TIme
to Low Level Output

AorB

Output Disable Time
from High Level Output

AorB

Output Disable TIme
from Low Level Output

AorB

tPZH

Output Enable TIme
to High Level Output

DIRto
AorB

10

38

10

30

ns

tpZL

Output Enable TIme
to Low Level Output

DIRto
AorB

5

30

5

25

ns

tpHZ

Output Disable TIme
from High Level Output

DIRto
AorB

1

12

1

10

ns

tpLZ

Output Disable TIme
from Low Level Output

DIRto
AorB

2

21

2

16

ns

tPZH
tPZL
tpHZ
tpLZ

~to
~to
~to

Nota 1: See Section 1 for test waveforms and output lOad.

Note 2: TheBe parameters 818 I1I888IK8d with \he InIemaI output 81818 of Ih8 storage register oppoa/I8 to that of Ih8 bus input

2-237

Function Table
Inputs

G

Data I/O (Note 1)

DIR

CAB

CBA

SAB

X

X

t

X

X

X

X

X

X

H

X

t

t
t

X

H

X

H/L

H/L

X

L

L

X

X

X

L

L

X

H/L

X

L

H

X

X

L

L

H

H/L

X

H

SBA

Operation or FunCtion

A1 thru A8

B1 thru B8

X

Input

Not Specified

Store A, B Unspecified

X

Not Specified

Input

Store B, A Unspecified

X

Input

. Input

Store A and B Data

X

Input

Input

Isolation, Hold Storage

L

Output

Input

Real-Time B Data to a Bus

H

Output

Input

Stored B Data to a Bus

X

Input

Output

Real-Time A Data to B Bus

X

Input

Output

Stored A Data to B Bus

Note 1: The data output functions may be enabled or disabled by various signals at the G and DlR inputs. Data input functions are always anabled, I.a., data at
the bus pins will be stored on every low-to-high transition on the clock inputs.
H = High Logic Level, L
excluding transitions, t

= Low Logic Level, X = Don't Care (Either Low or High Logic Levels including transitions), H/L = EHhar Low or High Logic Level
= Positive going edge of pulse.
.

Logic Diagram

:!P
----"'\

DIR

--/

CBA

SBA

CA~~

SAB

I

C>-

:acg

AI

10

~
.

-

i>ort>-

--

1

lD

0
F

CLK1< 1- ....

--

8

'----

Bl

~~
,

TO SEVEN OTHER CHANNELS

2-238

C
H
A
N
N
E
L
S
TL/F/9172-2

.----------------------------------------------------------------.0

!!:
PRELIMINARY en

~ Semiconductor
National

t

CorporaHon

Ii

DM54ALS648/DM74ALS648 Octal TRI-STATE® Inverting
Bus Transceivers
General Description
This device incorporates an octal bus transceiver and an
octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus.
This bus transceiver features totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and
increased high-logic level drive provides this device with the
capability of being connected directly to and driving the bus
lines in a bus-organized system without the need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers. and working registers.
The registers in the ALS648 are edge-triggered D-type flipflops. On the positive transition of the clock (CAB or CBA).
the Input bus data is stored into the appropriate register.
The CAB input controls the transfer of data into the A register and the CBA input controls the B register.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A low
input level selects real-time data. and a high level selects
stored data. The select controls have a "make before
break" configuration to eliminate a glitch which would nor-

mally occur in a typical multiplexer during the transition between stored and real-time data.
The enable G and direction control pins provide four modes
of operation: real-time data transfer from bus A to B, realtime data transfer from bus B to A, real-time bus A and/or B
data transfer to internal storage, or internally stored data
transfer to bus A or B.
When the enable G pin is low, the direction pin selects
which bus receives data. When the enable G pin is high,
both buses became disabled yet their input function is still
enabled.

~
o

i:

t
Ii
'"

CD

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer outputs drive bus lines directly
• Multiplexed real-time and stored data
• Independent registers for A and B buses

Connection Diagram
-Vee

CAB- 1

24

SAB- 2

23 -eBA

DIR- 3

22 -SBA

Al- 4

21 -G

A2- 5

20 -Bl

A3- 6

19 -B2

A4- 7

18 rB3

A5- 8

17 -B4

A6- 9
A7- 10

16 r-B5

AB- 11

14r-B7

GND- 12

13 r- B8

15 r- B6

TL/F/9173-1

Order Number DM54ALS648J or DM74ALS648WM, N
See NS Package Number J24A, M24B or N24A

PI
This document contains information on a product undar development. NSC reserves the right

2-239

to change or discontinue this product without notice.

Absolute Maximum Ratings
Note: The '~ Maximum Ratings" are those values
btIyond which tits ssfety of tits device cannot be guarsntHd. The device should not be operated at these limits. The
{JSf8IMIrIt: values cIefinfJd In tits "EIBctrfcaI CharscterisUcs"
fIIbIs are not (JUBf8f/tfIMJ at tits absolute maximum ratings.
The ''RtICOIrIfr/(II/c Opsrating Conditions" fIIbIs will define
tits conditions for actual device operation.

If Military/Aerospace specified devlcee are required,
contact the National Semiconductor Sal.. OffIce/
DIstributors for availability and .peclflcatlonL
Supply Voltage
7V
Input Voltage
Control Inputs
7V
110 Ports
5.5V
Operating Free-Air Temperature Range
DM54ALS
-55·Cto + 125"C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65"C to + 15O"C

Recommended Operating Conditions
Symbol

Dlll4ALSe48

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS648

Unite

Min

Nom

M_

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V
V

2

2

Vil

Low Level Input Vollage

0.7

0.8

V

10H

High Level Output Current

-12

-15

mA

10l

Low Level Output Current

fClOCK

Clock Frequency

tw
tsu

Pulse Duration, Clocks Low or High

14.5

12.5

ns

Data Setup Time, A before CAB or
BbeforeCBA

15t

10t

ns

tH

Data Hold Time, A after CAB or
BafterCBA

ot

ot

ns

Free Air Operating Temperature Range

-55

TA

t

12
0

35

125

0

24

mA

40

MHz

70

0

·C

= With reference to the low to high transition of the respactive clock.

Electrical Characteristics over recommended free air temperature range
Symbol

Teat CondItIona

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

= Min, II = -18mA
Vee = 4.5Vto5.5V
1oH'"
Vee = Min

Low Level Output
Voltage

Vee = Min

Input Current at
Maximum Input Voltage

Vee

IIH

High Level Input Current

Vee

III

Low Level Input
Current

Vee = Max,
VI = 0.4V (Note 1)

10

Output Drive Current

Vee

lee

Supply Current

II

Typ

2.4

= Max

2

Unite
V

3.2

V

54174AlS IOL "" 12 mA

0.25

0.4

IOL =- 24mA

0.35

0.5

74AlS

= Max

Max
-1.2

Vee- 2

-0.4mA

IOH'" -3mA
IOH

VOL

Min

Vee

I/O Ports, VI ... 5.SV
Control Inputs, VI

100

= 7V

20

Control Inputs

-200

1/0P0rt8

-200

Outputs Low
Outputs Diaabled
Note 1: For I/O ports the TAl-STATE output currants (IOZH and lozu are Included In the IIH and ~L ~

2-240

p,A

100

= Max, VI'" 2.7V (Note 1)

= Max, Vo ... 2.25V
Outputs High
Vee = Max

V

-30

-112
47

p,A
p,A
mA

76

57

88

57

88

mA

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

Conditions

From (Input)
To (Output)

DM54ALS648

DM74ALS648

Min

Max

Min

Max

CBAorCAB
toAorB

8

39

8

33

ns

CBAorCAB
toAorB

5

23

5

20

ns

AorBto
BorA

3

20

3

17

ns

2

12

2

10

ns

Units

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

AorBto
BorA

tpLH

Propagation Delay Time
Low to High Level Output
(with A or B Low)(Note 2)

SBAor SAB
toAorB

5

44

5

39

ns

Propagation Delay Time
High to Low Level Output
(with A or B Low)(Note 2)

SBAor SAB
toAorB

4

26

4

22

ns

Propagation Delay Time
Low to High Level Output
(with A or B High)(Note 2)

SBAor SAB
toAorB

6

30

6

25

ns

Propagation Delay Time
High to Low Level Output
(with A or B High)(Note 2)

SBAorSAB
toAorB

6

25

6

21

ns

4

25

4

22

ns

4

25

4

22

ns

1

12

1

10

ns

2

21

2

15

ns

tpHL

tpLH

tpHL

Vee = 4.5V to 5.5V,
CL = 50pF,
R1 = R2 = SOOO,
TA = Minto Max
(Note 1)

~to

Output Enable Time
to High Level Output

AorB

Output Enable Time
to Low Level Output

AorB

Output Disable Time
from High Level Output

AorB

Output Disable Time
from Low Level Output

AorB

tpZH

Output Enable Time
to High Level Output

DIRto
AorB

4

35

4

27

ns

tPZL

Output Enable Time
to Low Level Output

DIRto
AorB

3

25

3

19

ns

tpHZ

Output Disable Time
from High Level Output

DIRto
AorB

1

17

1

14

ns

2

15

ns

tpZH
tpZL
tpHZ
tpLZ

~to
~to
~to

Output Disable Time
DIRto
2
22
from Low Level Output
AorB
Note 1: See SectIon 1 for test waveforms and output load.
Note 2: These parameters are measured with the internal output state of the storage register opposite to thet of the bus input

tpLZ

II
2-241

Function Table
Inputs

Oats I/O (Note 3)

Ci

DIR

CAB

CBA

SAB

SBA

X

X

t

X

X

X

X

X

H

X

t

t
t

X

H

X

H/L

H/L

L

L

X

X

L

L

X

H/L

L

H

X

L

H

H/L

Operation or Function

A1 thru A8

B1 thru B8

X

Input

Not Specified

Store A, B Unspecified

X

Not Specified

Input

Store B, A Unspecified

X

X

Input

Input

Store A and B Data

X

X

Input

Input

Isolation, Hold Storage

X

L

Output

Input

Real-Time B Data to A Bus

X

H

Output

Input

Stored B Data to A Bus

X

L

X

Input

Output

Real·Time A Data to B Bus

X

H

X

Input

Output

Stored A Data to B Bus

Note 3: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data at
the bus pins will be stored on every low-\O-high transHlon on the clock inputs.

H - High Logic Level, L - Low logic Level, X - Don't Care (Either Low or High Logic Levels including transitions), H/L - EHher Low or High Logic Level
excluding transitions, t - Positive-going edge of pulse.

Logic Diagram

G-:t::j}-

~Rr:v

CBA

-l<\>-

SBA

CA~~
SAD

-t>ot-t:?-

r-GAB
CBA

~~
SAB

I

.-- I 1>-I

~

-

--.J- ,...,... f---o

Al-

-

.-

rEJ
~

-

\

I-

0
F

CLK1<

8

0...-

~

TO SEVEN OTHER CHANNELS

2-246

1
1D

B1

,

C
H
A
N
N
E
L
S
TL/F/9174-2

_

National
semiconductor

Corporation

DM54ALS689/DM74ALS689 8-Bit Comparator
General Description

Features

This comparator performs an "equal to" comparison of two
eight-bit words with provision for expansion or external enabling. The matching of the two 8-bit inputs plus a logic
LOW on the EN input produces the output A = B. The
ALS689 has an open collector output for wire AND cascading.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with LS family
TIL counterpart
• Improved output transient handling capability

Connection Diagram
Dual·ln·Una Package

Vee

w

17

Ai

la

Aa

Ie

Ae

1 I I 1 I I I I
211

19

II

17

18

1&

14

13

A4

12

I

11

•
e
a
1III AuI I I I I I I I I
I

2

3

4

80

AI

II

A2

7

8

I

82

A3

13

10

-

TL/F/6238-1

Order Number DM54ALS689J, DM74ALS689WM or DM74ALS689N
See NS Package Number J20A, M20B or N20A

Function Table
Inputs

H

Output

EN

Data

L
L

A=B
A=l:.B

L
H

H

X

H

= High Level, L = Low Level, X = Don't Care

2-247

Absolute Maximum Ratings
Note: ThfI "Absolute Msximum Rstings" sre those values
/»yond which tht1 ssfety of tht1 device cannot be gusrsnteed. ThfI device should not be op6I7Jted st th9S9limits. ThfI
psrsmetric vsIuss defined in tht1 "E/ectricsl Chsrscteristics"
fIIbkI IUS no/guaranteed st the absolute msximum ratings.
ThfI "RBCOmITIefIded Opersting Conditions" tsblfJ will define
tht1 conditions for actus! device op6I7Jtion.

If Military/Aerospace specified devices .... required,
contact the National Semiconductor Sales OffIce/
Distributors tor availability and apecltlcatlons.
Supply Voltage
7V
Input Voltage

7V
7V

Off State Output Voltage

Operating Free Air Temperature Range
DM54ALS
-55·Cto + 125"C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65"Cto +15O"C

Recommended Operating Conditions
Symbol

DM54ALS88t

Parameter

DM74ALS689

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

VOH

High Level Output Voltage

5.5

5.5

V

IOL

Low Level Output Current

12

24

mA

TA

Free Air Operating Temperature

70

·c

2

2

-55

125

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

= 5V. TA = 25·C.

Symbol

Typ

Parameter

VIK

Irlput Clamp Voltage

IOH

High Level Output Gurrent

VOL

Low Level Output
Voltage

II

Max High Input Current

IIH

High Level Input Current

IlL

Low Level Input Current

lee

Supply Current

Min

Condlllona
I

Vee = 4.5V.11 = -18 mA
:1 Vee

= 5.5V. VOH = 5.5V

Vee = 4.5V

V

0.1

mA
V

74ALS
IOL = 24mA

0.35

0.5

V

0.1

mA

5.5V (Note 1)

2-248

-1.5

0.4

= 5.5V. VIH = 7V
\ Vee = 5.5V. VIH = 2.7V
Vee = 5.5V. VIL = 0.4V
-=

Units

0.25

Vee

Vee

Max

V

54174ALS
IOL
12mA

=

Note 1: Icc is measured with EN grounded. A and B inputs at 4.5V.

V

12

20

/LA

-0.1

mA

19

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

DM54ALS689

DM74ALS689

Min

Max

Min

Max

A=B

10

30

10

25

ns

AorB
Data

A=B

5

25

5

23

ns

From
(Input)

To
(Output)

AorB
Data

Units

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

EN

A=B

8

30

8

25

ns

tpHL

Propagation Delay Time
High to Low Level Output

EN

A=B

8

30

8

25

ns

Vee = 4.5V to 5.5V
CL = 50pF
RL = 6670

Note 1: See Section 1 for test wavefonns and oUlptJlIoad.

Logic Diagram
At!

lie
Al

8,

Az
82

Aa

Sa
~

.
As

Brio

At!

lie
A7
87

EJi

2

3

4
5
8

7
8

9
11

12
13

14
15
18

17

18
1

~
~
~
~
~

---•
19

A=B

r---

~D
~D

ro-

~
".....

TL/F/6238-2

'Output Is open collector

2-249

rii

National
Semiconductor
Corporation

DM54ALS804A/DM74ALS804A Hex 2-lnput NAND Drivers
General Description

Features

These devices contain six independent 2-input drivers, each
of which performs the logic NAND function.

_ Switching specifications at 50 pF
_ Switching specifications guaranteed over full temperature and Vee range
_ Advanced oXide-isolated, ion-implanted Schottky TIL
process
_ Functionally and pin for pin compatible with Schottky
and low power Schottky TIL counterpart
_ Improved AC performance over Schottky and low power Schottky counterparts

Connection Diagram
Dual-In-Une Package

vee

IA

68

6A

BY

58

5A

5Y

48

4A

18

IV

2A

28

2Y

3A

38

3V

4Y

TL/F/6239-'

Order Number DM54ALS804AJ, DM74ALS804AWM or DM74ALS804AN
See NS Package Number J20A, M208 or N20A

Function Table
Y =A8
Inputs

Output

A

8

Y

L
L

L

H

H
H

L

H
H
H

H

L

H = High LogIc Level
L = Low Logic Level

2-250

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Operating Free Air Temperature Range
DM54ALS
- 55'C to + 125'C
DM74ALS
O'Cto +70'C
Storage Temperature Range

-65'Cto + 150'C

Recommended Operating Conditions
Symbol

DM54ALS804A

Parameter

DM74ALS804A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V
V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

10H

High Level Output Current

-12

-15

mA

10L

Low Level Output Current

12

24

mA

70

'c

2

2

-55

Free Air Operating Temperature
TA
"Applies for the DM74ALSB04·1 option only.

V

0

125

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25'C.
Symbol

Parameter

Conditions

Input Clamp Voltage

Vee = 4.5V.11 = -18 mA

VOH

High Level Output
Voltage

10H = -0.4 mA, Vee = 4.5V to 5.5V
10H = -3 mAo Vee = 4.5V
10H = Max. Vee = 4.5V

VOL

Low Level Output
Voltage

II

Input Current at Max
Input Voltage

Vee = 4.5V

Typ

Min

VIK

Max

Units

-1.2

V

Vee -2

V

2.4

V

2

V

54174ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

Vee = 5.5V. VIH = 7V

IIH

High Level Input Current

Vee = 5.5V. VIH = 2.7V

20

p.A

IlL

Low Level Input Current

Vee = 5.5V. VIL = 0.4V

-0.1

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

lee

Supply Current

Vee = 5.5V

-30

VI = OV, Outputs High
VI = 4.5V. Outputs Low

-112

mA

0.9

2.5

mA

7

12

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS804A

Conditions
Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

2-251

DM74ALS804A

Units

Min

Max

Min

Max

2

9

2

7

ns

2

9

2

8

ns

_

National
Semiconductor
Corporation

DM54ALS805A/DM74ALS805A Hex 2-lnput NOR Drivers
General Description

Features

These devices contain six independent 2-input drivers, each
of which performs the logic NOR function.

- Switching specifications at 50 pF
_ Switching specifications guaranteed over full temperature and Vee range
_ Advanced oxide-isolated, ion-implanted Schottky TTL
process
_ Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
_ Improved AC performance over Schottky and low power Schottky counterparts

Connection Diagram
Dual-In-Llne Package

vee

68

6A

6Y

58

5A

IA

18

IY

2A

28

2Y

5Y

48

4A

4Y

TlIF/6240-1

Order Number DM54ALS805AJ, DM74ALS805AWM or DM74ALS805AN
See NS Package Number J20A, M20B or NZOA

Function Table
Y=A+1i
Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

H
L
L
L

H = High logic Level
L = Low Logic Level

2·252

Absolute Maximum Ratings
Note: The "Abso/uffJ Maximum Ratings" are those values
beyond which the safety of the device cannot be {/UlUBnteed. The device should not be operated at thesellm/ts. The
parametric values defined In the "Electrical CharacffJristics"
table are not guaranteed at the absolute maximum ratings.
The "R9COI1Imended Operating Conditions" table will define
the conditions for actusl device operation.

If Military/Aerospace specHlecI devices are required,
contact the National Semiconductor Sales Office/
DIstributors for availability and specifications.
Supply Voltage
Input Voltage

7V
7V

Operating Free Air Temperature Range
DM54ALS
-55°C to + 125°C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-85"Cto +15O"C

Recommended Operating Conditions
Symbol

DM54ALS8OSA

itarameter

DM74ALS8OSA

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V
V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

10H

High Level Output Current

-12

-15

mA

10L

Low Level Output Current

12

24

mA

70

·C

2

Free Air Operating Temperature
TA
•Applies for the OM74ALS805-1 option only.

2

-55

125

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical vaiues ara measured at Vee = 5V, TA = 25"C.
Symbol

Parameter

Conditions

Input Clamp Voltage

Vee = 4.5V,11 = -18 rnA

VOH

High Level Output.
Voltage

10H';" -0.4mA. Vee = 4.5Vto5.5V

Low Level Output
Voltage

Vcr;:= 4.5V

IOH = -3 rnA, Vee = 4.5V
10H = Max, Vee = 4.5V

VOL

Typ

Min

VIK

Max

Units

-1.2

V

Vcc- 2

V

2.4

V

2

V

54174ALS
10L= 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

II

Input Current at Max
Input Voltage

Vee = 5.5V, VIH = 7V

IIH

High Level Input Current

Vee = 5.5V. VIH = 2.7V

20

pA

IlL

Low Level Input Current

Vee = 5.5V. VIL = O.4V

-0.1

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

lee

Supply Current

Vee = 5.5V

-112

mA

VI = OV, Outputs High

2

4

mA

VI = 4.5V, Outputs Low

8

14

mA

-30

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS8OSA

Conditions
Vee = 4.5Vto 5.5V
RL = 5000
CL=50pF

Note 1: See Section 1 for test waveforms and output load.

2-253

DM74ALS805A

Units

Min

Max

Min

Max

2

9

2

7

ns

2

9

2

8

ns

DM54ALS808A/DM74ALS808A Hex 2-lnput AND Drivers
General Description

Features

These devices contain six independent 2-input drivers. each
of which performs the logic AND fu~n.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated. ion-implanted Schottky TTL

process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

Connection Diagram
DuIII-ln-Une Package

TLlF/8241-1

Order Number DM54ALS808AJ, DM74ALS808AWM or DM74A~AN
See NS Package Number J20A, M20B or N20A

Function Table
Y=AB
Inpula

Output

A

B

Y

L
L

L

H

H
H

L

L
L
L

H

H

H - High logic Level

L - Low logic Level

2-254

Absolute Maximum Ratings
If Mllitary/Aeroepace epecIfIed devices ere required,
contact the National Semiconductor Sale. 0ffIce1
DIstrIbutors for availability and specification..
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
-55·Cto + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-85"Cto +15O"C

Note: The "AbsolutB Msxlmum Ratings" are thosB values
beyond which thB ssfety of the device cannot be gUBrBntBBd. The device should not be operated at thBse limits. The

parametric values defined in the "Electrical ChsrsctBrist/cs"
table are not guaranteed at thB absolutB msxlmum ratings.
The "Recommended Operating Conditions" table will define
thB conditions for actual device operation.

Recommended Operating Conditions
Symbol

DM54ALS808A

Parameter

DM74ALS808A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Vee

Supply Voltage

ViH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

IOH

High Level Output Current

-12

-15

mA

24

mA

70

·C

2

IOL

Low Level Output Current

TA

Free Air Operating Temperature

2

V

12
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range••AII typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

ConcIltlona

= 5V, TA = 25·C.
Typ

Min

= 4.5V,11 = -18 mA
IOH = 0.4 mA, Vee = 4.5 to 5.5V
IOH = -3 mA, Vee = 4.5V
IOH = Max, Vee = 4.5V
54174ALS
Vee = 4.5V
IOL = 12mA
Vee

Vee

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

IlL

Low Level Input Current

Vee

= 5.5V, VIL = 0.4V

10

Output Drive Current

Vee = 5.5V. Vo = 2.25V

lee

Supply Current

Vee

= 5.5V

Units
V
V

2.4

V

2

V
0.25

0.4

V

0.35

0.5

V

0.1

mA

= 5.5V, VIH = 7V

Input Current at Max
Input Voltage

Max
-1.2

Vee -2

74ALS
IOL = 24mA
II

V

-30

20

/loA

-0.1

mA

-112

mA

Outputs High

4.5

7

mA

Outputs Low

8

18

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol
tpLH

Parameter
Propagation Delay Time
Low to High Level Output

DM54ALS808A

Condltlonl
Vee = 4.5V to 5.5V
RL = 500n
CL=50pF

Propagetion Delay Tune
High to Low Level Output
Note 1: See Section 1 for test waveforms and output load.

tpHL

2·255

DM74ALS808A

Units

Min

Max

Min

Max

2

11

2

9

ns

1

10

1

8

ns

o

r---------------------------------------------------------------------,

i:s ~Natlonal
Semiconductor
~

. Corporation

::E
Q

c:;
.... DM54ALS810/DM74ALS810

!I
~

!

Quad 2-lnput Exclusive-NOR Gates
• Advanced oxide-isolated. ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with Schottky
and lOw' power Schottky TIL counterpart
.
• Improved AC performance over Schottky and low power Schottky counterparts

General Description
This device contains four independent gates. each of which
performs the logiC exclusive-NOR function.

Features
• Switching specifications at 50 pF
• Switching specifications ·guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Une Package
Vee

B4

A4

81

Y1

Y4

83

A3

82

Y2

Y3

TUF/6714-1

Order Number DM54ALS81OJ,.DM74ALS810M or DM74ALS810N
See NS Package Number J14A, M14A or N14A

Function Table
Y=A61B
Output

Inputs

H

A

B

Y

L
L
H
H

L
H
L
H

H
L
L
H

= High logic Level

L - Low logic Level

2-256

Absolute Maximum Ratings
If Military/Aerospace lIPeclfled devices are required,
contact the National Semiconductor Sales OffIce/
DIstrIbutors for availability and specifications.
Supply Vollage
7V
Input Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarant88d. The device should not be opereted at thesellm/ts. The
parametric values defined in the "Electrical Characteristics"
table are not guarantBBd at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Operating Free Air Temperature Range
DM54ALS
- 55"C to + 125"C
DM74ALS
O"Cto +70"C
Storage Temperature Range
- 65"C to + 150"C

Recommended Operating Conditions
Symbol

DM54ALS810

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output Current

DM74ALS810

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

10L

Low Level Output Current

TA

Free Air Operating Temperature

Units

Min

2

V

0.7

0.8

V

-0.4

-0.4

mA

8

mA

70

"C

4
-55

V

125

0

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted).
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

Max

Units

-1.5

V

VI

Input Clamp Voltage

Vee = Min,ll = -18 mA

VOH

High Level Output
Voltage

Vee = Min
10H = Max
VIL = Max
VIH = Min

DM54

Vee = Min
VIL = Max
VIH = Min

54/74ALS
IOL=4mA

0.25

0.4

V

74ALS
IOL=8mA

0.35

0.5

V

0.1

mA

VOL

Low Level Output
Voltage

DM74

II

Input Current at Max
Input Voltage

Vee = Max, VI = 7V

Vee - 2

3.4

V

Vee - 2

3.4

V

IIH

High Level Input Current

Vee = Max, VI = 2.7V

20

p,A

IlL

Low Level Input Current

Vee = Max, VI = 0.4V

-0.1

mA

10

Output Drive Current

Vee = Max, Vo = 2.25V

-112

mA

lee

Supply Current

Vee = Max (Note 2)

7.5

rnA

Note ,: All typicals are at Voo

-30

= 5V, TA = 25"C.

Note 2: 100 Is measured with all outputs open, one Input of each gate at 4.5V. and the other Inputs grounded.

2·257

5

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS810

Conditions
Other Input Low
Vee = 4.5V to 5.5V
RL = 5000.
CL = 50pF
Other Input High
Vee = 4.5V to 5.5V
RL = 5000.
CL = 50pF

2-258

DM74ALS810

Units

Min

Max

Min

Max

5

23

5

20

ns

3

17

3

14

ns

5

21

5

18

ns

3

17

3

14

ns

r------------------------------------------------------------------, 0
_

~

National

en

:t

Semiconductor
Corporation

~...

DM54ALS811/DM74ALS811 Quad 2-lnput Exclusive-NOR
Gates with Open-Collector Outputs
General Description

Features

This device contains four independent gates, each of which
performs the logic exclusive-NOR function. The open-collector outputs require external pull-up resistors for proper
logical operation.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

Pull-Up Resistor Equations
R

Vee (Min) - VOH
MAX = N1 (IOH) + N2 (IIH)

R
MIN =
Where:

.......o
~
......

:t
~...

...

Vee (Max) - VOL
IOL - N3 (lILl

N1 (IOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (lILl = total maximum input low current for all
inputs tied to pull-up resistor

Connection Diagram
Dual·ln·Llne Package
Vec

B4

A4

Y4

83

A1

81

Y1

A2

82

Y3

Y2

GND

TUF16715-1

Order Number DM54ALS811J or DM74ALS811M, N
See NS Package Number J14A, M14A or N14A

Function Table
Y=AEDB
Inputs
A
L
L

H
H

Output

B

y

L

H

H

L
L
H

L
H

H - High logic Lavel

L = Low Logic Level

2-259

fI

,...
,...

!I

Absolute Maximum Ratings

~

It Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Q

Supply Voltage

7V

Input Voltage

7V

::&

......
,...
,...

!I
~

:::IE
Q

Note: The "Absolute Maximum Rstings" sre thos8 values
beyond which the ssfety of the devlc6. cannot be gusrsnteed. The dev1c6 should not be operated st these limits. The
psrsmetrlc vslues defined in the "EI9ctrIcsI Chsrscterlstics"
tsble sre not gusrsnteed st the sbsolute maximum rstings.
The "R6COfTImended Operating Conditions" table will define
the conditions for sctusl dev1c6 operation.

Operating Free Air Temperature Range
DM54ALS
- 55°C to + 125°C
DM74ALS
O"Cto +70"C
Storage Temperature Range
- 65°C to + 150"C

Recommended Operating Conditions
Symbol

DM74ALS811

DM54ALS811

Parameter

Unlta

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

VOH

High Level Output Voltage

5.5

5.5

V

IOL

Low Level Output Current

8

mA

TA

Free Air Operating Temperature

70

°C

2

4
-55

125

V
V

2

0

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

Max

Unlta

VI

Input Clamp Voltage

Vee = Min, 11= -18 rnA

-1.5

V

ICEX

High Level Output Current

Vee = Min, Vo = 5.5V
VIL = Max, VIH = Min

100

/Jo A

VOL

Low Level Output
Voltage

Vee = Min
VIL = Max
VIH = Min

54/74ALS
IOL = 4mA

0.25

0.4

V

74ALS
IOL = 8mA

0.35

0.5

V

0.1

rnA

II

Input Current at Max
Input Voltage

Vee = Max, VIH = 7V

IIH

High Level Input Current

Vee = Max, VIH = 2.7V

IlL

Low Level Input Current

Vee = Max, VI = 0.4V

lee

Supply Current

Vee = Max (Note 2)

5

20

/JoA

-0.1

mA

7.5

mA

typicals are at Vee = 5V. TA = 25'C.
Note 2: lee is measured with all outputs open, one input of each gate aI4.5V. and the other Inputs grounded.
Note 1: All

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS811

Conditions
Other Input Low
Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF
Other Input High
Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

2-260

DM74ALS811

Units

Min

Max

Min

Max

25

60

25

55

ns

5

30

5

28

ns

20

55

20

50

ns

5

28

5

23

ns

r------------------------------------------------------------------,c
•

iii:
en

National
Semiconductor
Corporation

~

~

DM54ALS832A/DM74ALS832A Hex 2-lnput OR Drivers

~

~
.....

c

~

General Description

Features

These devices contain six Independent drivers, each of
which performs the logic OR function.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vc;c range
• Advanced oxide-isolated, ion-implanted Schottky TTL

~
~

w
~

process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

Connection Diagram

..

Du....n-Une Package

IA

•

4B

IA

41

.1
TL/F/6242-1

Order Number DM54ALS832AJ or DM74ALS832AWM, N
See NS Package Number J20A, M20B or N20A

Function Table
Y=A+B

Inputa

Output

A

B

Y

L
L
H
H

L
H
L
H

L
H
H
H

H - High LogiC Level

L = Low LogiC Level

EI
2·261

Absolute Maximum Ratings
If Mllltary/Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and speclflcatlons_
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55"C to + 125·C
DM74ALS
OOCto +700C
Storage Temperature Range
-65·Cto + 1500C

Note: The "Absolute Meximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute meximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

DM54ALS832A

Parameter

DM74ALS832A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

IOH

High Level Output Current

-12

-15

mA

24

mA

70

·c

2

IOL

Low Level Output Current

TA

Free Air Operating Temperature

2

V

12
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Conditions

= 5V, TA = 25·C.
Typ

Min

= 4.5V,11 = -18 mA
IOH = -0.4 mA, Vee = 4.5V to 5.5V
10H = -3 mA, Vee = 4.5V
10H = Max, Vee = 4.5V
54/74ALS
Vee = 4.5V
10L = 12mA

Vee

Input Current @ Max
Input Voltage

Vee

Units
V
V

2.4

V

2

V
0.25

0.4

V

0.35

0.5

V

0.1

mA

= 5.5V, VIH = 7V

= 5.5V, VIH = 2.7V
= 5.5V, VIL = 0.4V
Vee = 5.5V, Va = 2.25V
VI = 4.5V, Outputs High
Vee = 5.5V
VI = OV, Outputs Low

Max
-1.2

Vee -2

74ALS
IOL = 24mA
II

V

IIH

High Level Input Current

Vee

20

p.A

IlL

Low Level Input Current

Vee

-0.1

mA

10

Output Drive Current

lee

Supply Current

-30

-112

mA

6

9

mA

9.5

16

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS832A

Conditions
Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

2-262

DM74ALS832A

Units

Min

Max

Min

Max

2

11

2

9

ns

1

10

1

8

ns

National

~ Semiconductor
CorporaHon

DM54ALS873B/DM74ALS873B Dual4-Bit D-Type
Transparent Latches with TRI-STATE® Outputs
General Description
These dual 4-bit registers feature totem-pole TRI-STATE
outputs designed specifically for driving highly-capacitive or
relatively low-impedance toads. The high-impedance state
and increased high-logic-level drive provide these registers
with the capability of being connected directly to and driving
the bus lines in a bus-organized system without need for
interface or pull-up components. They are particularly attractive for implementing buffer registers, lID ports, bidirectional bus drivers, and working registers.
The eight latches of the ALS873B are transparent Ootype
latches. While the enable (G) is high the outputs will follow the data (0) inputs. When the enable is taken low the
output will be latched at the level of the data that was set
up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic

a

levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• SWitching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced OXide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly
• Space saving 300 mil wide package

Connection Diagram
Dual-In-Llne Package
ENABLE
lG

lQl

lQ2

lQ3

lQo4

22

21

20

19

3

4

5

6

102

103

104

101

2Ql
18

7
201

2Q2

17

8
202

2Q4

2Q3

16

9
203

ENABLE
2G

2CLR

15

10
204
TL/F/6243-1

Order Number DM54ALS873BJ, DM74ALS873BWM or DM74ALS873BNT
See NS Package Number J24A, M24B or N24C

fI
2-263

Absolute Ma;clmum Ratings
If ~llItary/Aerospace specified devices are required,
contact the National Semiconductor Seles Offlcel
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Voltage Applied to Disabled Output

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

5.5V

Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range

-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS873B

Parameter

DM74ALS873B

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-1

-2.6

rnA

10L

Low Level Output Current

12

24

rnA

tw

Pulse Width

I
I

2

2

V

Enable High

10

10

ns

Clear Low

15

15

ns
ns

tsu

Data Setup Time

10,J..

10,J..

tH

Data Hold Time

7,J..

7,J..

TA

Operating Free Air Temperature

-55

125

ns

0

70

·C

The (,j.) arrow Indicates the negative edge of \he enable is used for reference.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 rnA

VOH

High Level Output
Voltage

Vee = 4.5V
VIL = VILMax
10H = Max

VOL

Low Level Output
Voltage

Min

2.4

Typ

Max

Units

-1.2

V

3.2

V

10H = -400 /loA
Vee = 4.5Vt05.5V

54174ALS

Vee = 4.5V
VIH = 2V

54174ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24 rnA

0.35

0.5

V

0.1

rnA

V

Vee - 2

II

Input Current @ Max.
Input Voltage

Vee = 5.5V, VIH = 7V

Illi

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

p.A

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.1

rnA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

-112

rnA

10ZH

Off-State Output Current
High Level Voltage Applied

Vee = 5.5V, VIH = 2V
Vo = 2.7V

20

p.A

10ZL

Off-State Output Current
Low Level Voltage Applied

Vee = 5.5V, VIH = 2V
Vo = 0.4V

-20

p.A

lee

Supply Current

Vee = 5.5V
Outputs Open

rnA
rnA
rnA

2-264

-30

Outputs High

11

21

Outputs Low

16

29

Outputs Disabled

20

31

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

From

To

Data

AnyQ

Data

AnyQ

Propagation Delay Time
Low to High Level Output

Enable

AnyQ

tpHL

Propagation Delay Time
High to Low Level Output

Enable

AnyQ

tPZH

Output Enable Time
to High Level Output

Output
Control

AnyQ

tPZL

Output Enable Time
to Low Level Output

Output
Control

AnyQ

tpHZ

Output Disable Time
from High Level Output

Output
Control

AnyQ

tpLZ

Output Disable Time
from Low Level Output

Output
Control

AnyQ

tpHL

Propagation Delay Time
High to Low Level Output

Clear

AnyQ

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

Function Table
Inputs
CLR

0

EN

OC

X

X
X

X
X

H
L

H
H
L

H
L
L
L
L

L
H
H
H

X

Output
Q

Z
L
H
L
Qo

= Low State, H = High State, X = Don't care
Z = High Impedance State
00 = Previous Condition of 0
L

2·265

DM54ALS873B

DM74ALS873B

Min

Max

Min

Max

2

17

2

14

ns

2

15

2

14

ns

8

29

8

22

ns

8

26

8

21

ns

4

22

4

18

ns

4

23

4

18

ns

2

12

2

10

ns

2

21

2

15

ns

6

24

6

20

ns

Units

Logic Diagram
I ENABlE-=23__I>o-_'"I
IOUTPUT_~2~c>_ _~_ _ _ _~

CONTROL
I CLEAR

101~---+-+--1

102

4

103

5

104

6

201

7

202

8

19

104

17

202

9_ _ _+-+---4
203....::.
16 203

204 10
15

204

2~~1~1~1>_ _~_ _ _ _~

CONTROL
2 E.ABLE~I:;.4~I~o--"
Tl/F/6243-2

2·266

National

_

Semiconductor
Corporation

DM54ALS874B/DM74ALS874B Dual 4-Bit D-Type
Edge-Triggered Flip-Flops with TRI-STATE® Outputs
General Description
These dual 4-bit registers feature totem-pole TRI-STATE
outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these registers
with the capability of being connected directly to and driving
the bus lines in a bus-organized system without need for
interface or pull-up components. They are particularly attractive for implementing buffer registers, 110 ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the ALS874B are edge-triggered
Ootype flip-flops. On the positive transition of the clock, the
outputs will be set to the logic states that were set up at
the 0 inputs.

o

A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced OXide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly
• Space saving 300 mil wide package
• Asynchronous clear

Connection Diagram
Dual-In-L1ne Package

..

Va:

ICu<
23

101

"

1112

II

1113
IG

IOf

!VI

19

18

I

ICUi

liE

101

102

113

104

1111

IQ2

11

2113

!Vf

18

1&

I

10

2113

11M

II:IJ(

"

"IiiC

Ki'i
13

12
lID

TL/F/6244-1

Order Number DM54ALS8748J, DM74ALS874BWM or DM74ALS874BNT
See NS Package Number J24A, M24B or N24C

fI
2-267

Absolute Maximum Ratings

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarenteed. The device should not be operated at theSe limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" teb/e will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales OffIce/
Distributors for availability and specifications.

Supply Voltage
7V
Input Voltage
7V
Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
-65·Cto + 150"C
Storage Temperature Range

Recommended Operating Conditions
Symbol

DM54ALS874B

Parameter

DM74ALS874B

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Vee

Supply Voltage

VIH
VIL

High Level Input Voltage
Low Level Input Voltage

10H

High Level Output Current

0.7
-1

0.8
-2.6

10L

Low Level Output Current

12

24

rnA

fCLK

Clock Frequency

30

MHz

twCLK

Width of Clock Pulse

2

2

0

25

0

V
V
V

rnA

High

20

16.5

Low

20

16.5

ns
ns

tWCLR
tsu

Width of Clear Pulse

10

10

ns

Data Setup Time

15t

15t

ns

tH

Data Hold Time
Clear Inactive
Free Air Operating Temperature

ot
10

ns

tsu

4t
10
-55

TA

Low

125

0

70

ns
·C

The ( t) arrow indicates the positive edge of the Clock is used for reference.

Electrical Characteristics
over recommended operating free. air temperature range. All typical values are measured at Vee
Symbol

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

II
IIH
IlL
10
i .-.'

Parameter

= 4.5V.11 = -18 mA
Vee = 4.5V
VIL = VILMax
Vee = 4.5V to 5.5V
Vee = 4.5V
VIH = 2V
Vee

Low Level Input Current

Vee
VCC

Output Drive Current
Off-State Output Current
High Level Voltage Applied

10ZL

Off-State Output Current
Low Level Voltage Applied

lee

Supply Current

= 5V, TA = 25·C.

Min

Typ

Vee

Input Current @Max
Input Voltage
High Level Input Current

10ZH
,r',

Conditions

10H

= Max

10H = -400 p.A
54174ALS
10L = 12 rnA
74ALS
10L = 24mA

2.4

Outputs Low
Outputs Disabled

2·268

V
V

0.25

0.4

V

0.35

0.5

V

0.1

rnA

20
-0.2

,...A
mA

-112

rnA

20

,...A

-20

,...A

21

-30

Outputs High

V

Vec- 2

Vee

Outputs Open

Units

3.2

= 5.5V. VIH = 7V

= 5.5V. VIH = 2.7V
= 5.5V. VIL = 0.4V
= 5.5V. Vo = 2.25V
Vee = 5.5V. VIH = 2V
Vo = 2.7V
Vee = 5.5V. VIH = 2V
Vo = 0.4V
Vee = 5.5V

Max

-1.2

14
19

30

rnA
mA

20

32

mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
Symbol

'MAX

Parameter

Conditions

Maximum Clock Frequency

Vee = 4.5V to 5.5V
RL = 500n
CL=50pF

From

To

tpLH
tpHL

Propagation Delay Time
High to Low Level Output

Clock

AnyQ

tPZH

Output Enable TIme
to High Level Output

Output
Control

AnyQ

tpZL

Output Enable Time
to Low Level Output

Output
Control

AnyQ

tpHZ

Output Disable Time
from High Level Output

Output
Control

AnyQ

tpLZ

Output Disable Time
from Low Level Output

Output
Control

AnyQ

Clear

AnyQ

Propagation Delay TIme
High to Low Level Output
Note 1: See Section 1 for last waveforms and output load.

DM74ALS874B

Min

Min

Max

25

Propagation Delay TIme
Low to High Level Output

tPHL

DM54ALS874B

Clock

AnyQ

Units

Max

30

MHz

4

15

4

14

ns

4

15

4

14

ns

4

21

4

18

ns

4

21

4

18

ns

2

12

2

10

ns

3

15

3

12

ns

5

20

5

17

ns

Function Table
Inputs

Output

CLR

D

CLK

OC

Q

X

X
X

X
X

Z

H
L

t
t

X

L

H
L
L
L
L

L
H
H
H

L
H
L

Co

L = Low State. H = High State. X = Don'l Cere
t - PositIve Edge Transition

Z = High Impedance S_

ao - .Previous Condition of Q

•
2-269

;

Logic Diagram

c

1 CLOCK

!.....

lOuTPuT
CONTROL

it

!

;!

23

,.

2

1CLR

101

3

102

4

103

5

104 ...:.6---t-r--t
1--.or.~;""I04

201...;.,7- - - - - - t

202 ...-8-_.......,t--t--1

1---t--t--1
2D3...-

204 10

20UTPUT_~I1~[>_ _~_ _ _ _~

CONTROL
2 CLOCK...;.;14--1D<~_'"
TLIF16244-2

2·270

NaHonal
Semiconductor
CorporaHon

_

DM54ALS876A/DM74ALS876A Dual4-Bit D-Type
Edge-Triggered Flip-Flops with TRI-STATE@ Outputs
General Description
These inverting dual 4-bit registers feature totem-pole TRISTATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide
these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system
without need for interface or pull-up components. They are
particularly attractive for implementing buffer registers, 1/0
ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the ALS876A are edge-triggered inverting Ootype flip-flops. On the positive transition of the
clock, the Q outputs will be set to the complement of the
logic states that were set up at the 0 inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance

state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly
• Space saving 300 mil wide package
• Asynchronous preset

Connection Diagram
Dual-In-Line Package
Vee

24

lCLK

101

22

3
101

102
21

"

102

103

2CLK

104

20

19

5

6

103

104

2PRE
13

7
201

8

9

202

203

10

204
TL/F/8245-1

Order Number DM54ALS876AJ, DM74ALS876AWM or DM74ALS876ANT
See NS Package Number J24A, M24B or N24C

fI
2-271

Absolute Maximum Ratings
Note: The "Absolute M8ximum Rstings" iue those values

If Military/Aerospace apecIfIed .devlces ara required,
contact the National Semiconductor Sal.. OffIce/
Distributors for availability and specHlcationa.
Supply Voltage
7V
Input Voltage
7V
Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
DM54ALS
-55"Cto + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·C to + 15O"C

beyond which the ssfilty of the devfcs cannot be gusrsntHd. The devfcs should not be opsrstBd st theSB limits. The

psrsmetrlc vslues defined in the "E/ectricsl Chsrscteristics"
tsbIe Bf8"irot gusrsntBBd st the sbsoIute maximum ratings.
The "RecomrnsndBd Opersting Conditions" table will define
the conditions for sctusl devfcs opsrstion.

Recommended Operating Conditions
Symbol
Vcc
VIH
VIL
10H
10L
fCLK
twCLK

1wPRE

tsu
1H
tsu
TA

,

Parameter

DM54ALS876A
Min
4.5
2

Supply Vollage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency
Width of Clock Pulse
High
Width of Preset Pulse
Data Setup Time

Nom
5

Max
5.5

0.8
-2.8

12
25

24
30

10

0
16.5
16.5
10

15t

15t

4t
10t
-55

ot
10t
0

Low
Low

20

Free Air Operating Temperature

DM74ALS876A
Nom
Max
5.5
5

0.7
-1
0
20

Dala Hold Time
Preset Inactive

Min
4.5
2

125

70

Units
V
V
V

RiA
mA
MHz
ns
ns
ns
ns
ns
ns
·C

The ( t) arrow indicates the positive edge of the CloCk Is used for reIarenCe.

Electrical Characteristics
over recommended operating free air temperature range. All typiCal values are measured at Vee = 5V. TA
Symbol
VIK
VOH

Parameter
Input Clamp Voltage
High Level Output
Voltage

VOL

Low Level Output
Voltage

II
IIH
IlL
10
10ZH
10ZL
lee

Input Current @ Max.
Input Voltage
High Level Input Current
Low Level Input Current
Output Drive Current
Off·State Output Current
High Level Voltage Applied
Off-State Output Current
Low Level Voltage Applied
Supply Current

Conditions
Vee = 4.5V. II = -18 mA
Vee = 4.5V
VIL = VILMax
Vee = 4.5V to 5.5V
Vee = 4.5V
VIH = 2V

Vee

IOH

= Max

10H = -400 p.A
54174ALS
10L = 12mA
74ALS
10L = 24mA

Min

Typ

2.4

3.2

= 5.5V. VIH = 2.7V
= 5.5V. VIL = 0.4V
= 5.5V. Vo = 2.25V
Vee = 5.5V. VIH = 2V
Vo = 2.7V
Vee = 5.5V. VIH = 2V
Vo = 0.4V
Vee = 5.5V
Outputs Open

2·272

Units
V
V
V

0.25

0.4

V

0.35

0.5

V

0.1

mA

20
-0.2
-112

mA

20

p.A

-l!O

p.A

21
29
31

mA
mA

-30

Outputs High
Outputs Low
Outputs Disabled

Max
-1.5

Vee- 2

= 5.5V. VIH = 7V

Vee
Vee
Vee

=. 25"C.

14
18
20

p.A
mA

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditione

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Vee = 4.5Vt05.5V
RL = 500n
CL = 50pF

From

To

DM54ALS876A

DM74ALS876A

Min

Min

Max

30

25
Clock

AnyQ

Propagation Delay Time
High to Low Level Output

Clock

AnyO

tpZH

Output Enable TIme
to High Level Output

Output
Control

Any 0

tPZL

Output Enable Time
to Low Level Output

Output
Control

Any 0

tpHZ

Output Disable Time
from High Level Output

Output
Control

Any 0

tpLZ

Output Disable TIme
from Low Level Output

Output
Control

Any 0

tpHL

Propagation Delay Time
High to Low Level Output

Preset

AnyQ

Units

Max
MHz

4

15

4

14

ns

4

15

4

14

ns

4

21

4

18

ns

4

21

4

18

ns

2

12

2

10

ns

3

15

3

13

ns

6

22

6

19

ns

Note 1: See Section 1 for test wavefonns and output load.

Function Table
Inputs

output

PRE

D

eLK

oc

Q

x

x

L
H
H
H

X
H
L
X

X
X

H
L
L
L
L

Z
L
L
H

t
t
L

00

L = Low Stale, H = High State, X = Don't Care

,t =

Positive Edge Transition
Z = High Impedance Stale

00 =

Previous Condition 01 t\

PI
2·273

I
~
.....
:::Ii
Q

I
~

logic Diagram
I CLOCK ...;;23:-'1>1>-_.,
IOUTPUT~2~1>_ _~______~

CONTROL
I

PRE -_~---.
101

3

102

4

103

5

:::Ii
Q

104

...::..------I--+_~

201....:..7-_ _ _ _ _~

202 ...::.B_ _ _I--+_~

203

9

204 ~---I--+_~

20UTPUT~II-aI.>_ _+_----~
CONTROL
2 CLOCK ...:;:14~1>1>-_'"
TUF/6245-2

2-274

_

National

Semiconductor
Corporation

DM54ALS880A/DM74ALS880A
Dual 4-Bit D-Type Transparent Latches
with TRI-STATE® Outputs
General Description
These dual 4-bit registers feature totem-pole TRI-STATE
outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these registers
with the capability of being connected directly to and driving
the bus lines in a bus-organized system without need for
Interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight inverting latches of the ALS880A are transparent
O-type latches. While the enable (G) is high the c:i outputs
will follow the complement of the data (0) inputs. When the
enable is taken low the output will be latched at the complement of the level of the data that was set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic

levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are off.

Features
• SWitching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines direcUy
• Space saving 300 mil wide package

Connection Diagram
Dual-In-Llne Package

ENABLE
lG

ENABLE
2G

2PRE
13

3
101

"

102

5
103

6
10.4

7

8

9

201

202

203

10

20.4

20C

GNO
TL/F/6248-1

Order Number DM54ALS880AJ, DM74ALS880AWM or DM74ALS880ANT
See NS Package Number J24A, M24B or N24C

fI
2-275

'Absolute Maximum Ratings
If Mllltary/Aeroapace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications_
Supply Voltage

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V

Input Voltage

7V

Voltage Applied to Disabled Output

5.5V

Operating Free Air Temperature Range
DM54ALS
- 55°C to + 125°C
DM74ALS
O"Cto +70"C
Storage Temperature Range
- 65°C to + 150"C

Recommended Operating Conditions
Symbol

DM54ALS880A

Parameter

DM74ALS880A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.7

0.8

V

2

2

V

10H

High Level Output Current

-1

-2.6

mA

10l

Low Level Output Current

12

24

mA

tw

Pulse Width

I
I

Enable High

15

15

ns

Preset Low

15

15

ns
ns

tsu

Data Setup Time

10,J,

10,J,

tH

Data Hold Time

10,J,

10,J,

-55
Free Air Operating Temperature
TA
The ( .J,) arrow Indicates the negative edge of the enable is used for reference.

125

ns

0

70

°C

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

= 4.5V,11 = -18 mA
Vee = 4.5V
Vil = VILMax
Vee = 4.5V to 5.5V
Vee = 4.5V
VIH = 2V

=

Min

Conditions

5V, TA
Typ

Vee

II

Input Current @ Max
Input Voltage

IIH

High Level Input Current

Vee

IlL

Low Level Input Current

. Vee

10

Output Drive Current

10ZH

Off-State Output Current
High Level Voltage Applied

10Zl

Off-State Output Current
Low Level Voltage Applied

lee

Supply Current

Vee

=

5.5V, VIH

=

IOH

=

Max

IOH

=

-400 poA

2.4

25°C.
Max

Units

-1.2

V

3.2

V
V

Vee - 2

54174ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

7V

= 5.5V, VIH = 2.7V
= 5.5V, VIL = O.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V, VIH = 2V
Vo = 2.7V
Vee = 5.5V, VIH = 2V
Vo = 0.4V
Vee = 5.5V

Outputs High

Outputs Open

Qutputs Low
Outputs Disabled

20

2-276

=

20

poA

-0.2

mA

-112

mA

20

poA

-20

poA

14

21

mA

19

29

mA

31

mA

-30

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

.

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Conditions

From

Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

To

Data

AnyQ

Data

AnyQ

Propagation Delay Time
Low to High Level Output

Enable

Any 0

tpHL

Propagation Delay Time
High to Low Level Output

Enable

Any 0

tPZH

Output Enable Time
to High Level Output

Output
Control

AnyQ

tPZL

Output Enable Time
to Low Level Output

Output
Control

Any 0

tpHZ

Output Disable Time
from High Level Output

Output
Control

AnyQ

tpLZ

Output Disable Time
from Low Level Output

Output
Control

AnyQ.

tpHL

Propagation Delay Time
High to Low Level Output

Preset

AnyQ

DM54ALS880A

DM74ALS880A

Min

Max

Min

Max

3

23

3

20

ns

3

15

3

14

ns

8

31

8

24

ns

8

22

8

21

ns

4

21

5

18

ns

4

21

5

18

ns

2

12

2

10

ns

3

21

3

17

ns

6

24

6

21

ns

Units

Note 1: See Section 1 for test waveforms and output load.

Function Table
Inputs

Output

PRE

0

EN

OC

X

X
X

X
X

H
L

H
H
L

H
L
L
L
L

L
H
H
H

X

L = Low Slate, H = High Slate, X
Z = High Impedance Slate

~

Z
L
L
H

00

= Don't Care

00 = Previous Condition of 0

fI
2·277

;

!1
,...
==

::&
C

......

Logic Diagram
1 ENABLE 23
1 0iiiPuT 2
CONTROL

;co

!J

101

==

In

22

::&

101

C

102

4

21 102

lD3

5
20

103

104 8

201

7

lB 201

202 B
17 2'02

203

9
18 203

204 10
2P'ii"EsEi" 13

2 OUTPUT
CONTROL
2 ENABLE

15 204

1

14
TUF/6248-2

2-278

_

National

Semiconductor
Corporation

DM54ALS1000A/DM74ALS1000A
Quadruple 2-lnput NAND Buffers
General Description

Features

These devices contain four independent 2-input buffer/ drivers, each of which performs the logic NAND function. The
'ALS1000A is a buffer/driver version of the 'ALSOOA.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Improved line receiving characteristics

Connection Diagram
Dual·ln·Une Package
Vee

48

4A

4Y

38

3A

3Y

8

1A

1B

1Y

2A

2B

2Y

GNO

Order Number DM54ALS1000AJ,
DM74ALS1000AM or DM74ALS1000AN
See NS Package Number J14A, M14A or N14A

Function Table
Y=AB
Inputs

H

Output

A

B

Y

L
L

L

H

H
H

L

H
H
H

H

L

= High Logic Level

L = Low Logic Level

2-279

TL/F/6249-1

Absolute Maximum Ratings
If Military/Aerospace specified devices 'are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55°C to + 125°C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65°C to + 150"C

'._-

Note: The "Absolute Maximum Ratings" are those val1J6S
beyond which the safety of the device cannot be guarantf)(!)(}. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

DM54ALS1000A

Parameter

DM74ALS1000A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Vcc

Supply Voltage

VIH

High Lev9J Input Voltage

Vil

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-1

-2.6

mA

24

rnA

70

°C

2

10l

Low Level Output Current

TA

Free Air Operating Temperature

V

2

V

12
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vcc = 5V, TA = 25°C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VOH

High Level Output
Voltage

Vcc = 4.5V
Vil = VllMax

VOL

Low Level Output
Voltage

Min

10H = Max

Typ

2.4

IIA

Max

Units

-1.5

V
V

3.2

V

Vcc = 4.5V to 5.5V

10H = -400

Vcc = 4.5V
VIH = 2V

54174ALS
IOl = 12 rnA

0.25

0.4

V

74ALS
IOl = 24mA

0.35

0.5

V

0.1

mA

Vee -2

II

Input Current at Max
Input Voltage

Vcc = 5.5V, VIH = 7V

IIH

High Level Input Current

Vcc = 5.5V, VIH = 2.7V

20

IIA

III

Low Level Input Current

Vcc = 5.5V, Vil = 0.4V

-0.1

mA

10

Output Drive Current

Vcc = 5.5V, Vo = 2.25V

-112

mA

ICCH

Supply Current with
Outputs High

Vcc = 5.5V, VI = OV

0.86

1.6

mA

ICCl

Supply Current with
Outputs Low

Vcc = 5.5V, VI = 4.5V

4.8

7.8

rnA

-30

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Conditions
Vcc = 4.5V to 5.5V
RL = 500n
CL = 50pF

Note 1: See Section 1 for lest waveforms and output load.

2-280

DM54ALS1000A

DM74ALS1000A

Min

Max

Min

Max

2

10

2

8

ns

2

10

2

7

ns

Units

NatiOnal

~ Semiconductor
Corporation

DM54ALS 1002A/DM7 4ALS 1002A
Quadruple 2-lnput Positive-NOR Buffers
General Description

Features

This device contains four independent 2-input buffers, each
of which performs the logic NOR function. The 'ALS1002A
is a buffer verision of the' ALS02.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Improved line receiving characteristics

Connection Diagram
Dual-In-Llne Package

,vee

Y4

B4

A4

Y3

B3

A3

8

I

Y1

A1

B1

Y2

A2

B2

GND

Order Number DM54ALS1002AJ,
DM74ALS1002AM or DM74ALS1002AN
See NS Package Number J14A, M14A or N14A

Function Table
Y=A+B
Inputs
A

B

Y

L
L

L

H

H

L
L
L

H
H

H
L

Output

L

H
= High Logic Level
= Low Logic Level

2-281

TL/F/6250-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
- 65·C to + 150·C

Recommended Operating Conditions
Symbol

DM54ALS1002A

Parameter

DM74ALS1002A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

V

Vcc

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.7

0.8

10H

High Level Output Current

-1

-2.6

mA

IOL

Low Level Output Current

12

24

mA

TA

Free Air Operating Temperature

70

·C

2

2

-55

125

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vcc = 5V. TA = 25·C.
Symbol

Parameter

Min

Conditions

VIK

Input Clamp Voltage

Vcc = 4.5V.11 = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V
VIL = VILMax

VOL

Low Level Output
Voltage

Typ

2.4

10H = Max

Max

Units

-1.5

V

3.2

V

Vee = 4.5V to 5.5V

10H = -400 ""A

Vcc = 4.5V
VIH = 2V

54174ALS
10L = 12mA

Vcc -2

V
0.25

0.4

V

74ALS
10l = 24mA

0.35

0.5

V

0.1

mA

II

Input Current @ Max
Input Voltage

Vcc = 5.5V. VIH = 7V

IIH

High Level Input Current

Vee = 5.5V. VIH = 2.7V

20

III

Low Level Input Current

Vcc = 5.5V. VIL = 0.4V

-0.1

""A
mA

10

Output Drive Current

Vee = 5.5V. Vo = 2.25V

-112

mA

ICCH

Supply Current with
Outputs High

Vee = 5.5V. VI = OV

1.7

2.8

mA

ICCl

Supply Current with
Outputs Low

Vee = 5.5V. VI = 4.5V

5.6

9

rnA

-30

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHl

Propagation Delay Time
High to Low Level Output

Conditions
Vcc = 4.5V to 5.5V
RL = 5000
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

2-282

DM54ALS1002A

DM74ALS1002A

Min

Max

Min

Max

2

10

2

8

ns

2

10

3

7

ns

Units

_

National
Semiconductor

CorporaHon

DM54ALS1003A/DM74ALS1003A Quadruple 2-lnput
NAND Buffers with Open-Collector Outputs
General Description

Features

This device contains four independent 2-input buffers, each
of which performs the logic NAND function. The outputs
require an external pull-up resistor for proper logical operation. The 'ALS1003A is a buffer version of the 'ALS03A.

• Switching speCifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with LS TTL
counterpart
• Improved line receiving characteristics

Pull-Up Resistor Equations
R
Vee (Min) - VOH
MAX = N1 (IOH) + N2 (lIH)

R
MIN =
Where:

Vee (Max) - VOL
IOL - Na (lILl

N1 (IOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
Na (Ill) = total maximum input low current for all
inputs tied to pull-up resistor

Connection Diagram
Dual-In-Line Package
Vee

B4

B3

M

A3

V3

8

A1

B1

V1

A2

V2

B2

TLlF/6251-1

Order Number DM54ALS1003AJ, DM74ALS1003AM or DM74ALS1003AN
See NS Package Number J14A, M14A or N 14A

Function Table
Y =AB
Inputs

H

Output

A

B

Y

L
L

L

H

H
H

L

H
H
H

H

L

= High Logic Level

L = Low logic Level

2-283

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the devies cannot ~ guaranteed. The devies should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table ara not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual devies Operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Off State (High Level)
Output Voltage

, 7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
OOCto +700C
Storage Temperature Range

-65·Cto + 1500C

Recommended Operating Conditions
Symbol

DM54ALS1003A

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS1003A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

2

V
V

VIL

Low Level Input Voltage

0.7

0.8

VOH

High Level Output Voltage

5.5

5.5

V

IOL

Low Level Output Current

12

24

mA

TA

Free Air Operating Temperature

70

·C

-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

= 5V, TA = 25·C.

Symbol

Typ

Parameter

VIK

Input Clamp Voltage

IOH

High Level Output Current

VOL

Low Level Output
Voltage

Min

Conditions

= 4.5V,11 = -18 mA
= 4.5V, VOH = 5.5V
54174ALS
Vee = 4.5V
VIH = 2V
IOL = 12mA

Max

V

Units

Vee

-1.5

V

Vee

100

pA

0.25

0.4

V

0.35

0.5

V

0.1

mA

74ALS
IOL = 24mA

= 5.5V, VIH = 7V

II

Input Current at Max
Input Voltage

Vee

IIH

High Level Input Current

Vcc

20

pA

IlL

Low Level Input Current

Vcc

-0.1

mA

ICCH

Supply Current with
Outputs High

0.86

1.6

mA

ICCL

Supply Current with
Outputs Low

4.8

7.8

mA

= 5.5V, VIH = 2.7V
= 5.5V, VIL = 0.4V
Vcc = 5.5V. VI = OV
Vcc

= 5.5V, VI = 4.5V

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Conditions
Vcc = 4.5V to 5.5V
RL = 6670
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

2-284

DM54ALS1003A

DM74ALS1003A

Min

Max

Min

Max

10

40

10

33

ns

2

18

2

12

ns

Units

r------------------------------------------------------------------.o
_

s:::

National

CII

:t

Semiconductor
Corporation

~
.....

DM54ALS1004/DM74ALS1004 Hex Inverting Drivers
Features

These devices contain six independent drivers, each of
which performs the logic inverter/complement function. The
'ALS1004 is a driver version of the 'ALS04A.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

Connection Diagram
Dual-In-Une Package

:I

C

14

1

At;

lli

12

~J
-"
....

1

~8

131

I

:i

I ,. . I
&J
IJ

~D

I",.... I
"

I"'" I

3J

2J
VI

9~

v5
101

~

4J2

Aa

...

I ...,.... I
3

Order Number DM54ALS1004J or DM74ALS1004M, N
See NS Package Number J14A, M14A or N14A

Function Table
Y=A
Input

Output

A

Y

L
H

H
L

H ~ High Logic Level
L

~

Low Logic Level

2-285

:eo
a:

General Description

Aa

g

TLlF/6252-1

~

Ii)

.....
2

C)

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors tor availability and specifications.
Supply Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the devic8 cannot be guaranteed. The devic8 should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
taple are not guaranteed at the absolute maximum ratings.
The ··Recommended Operating Conditions" table will define
the conditions for actual devic8 operation.

7V

Input Voltage

Operating Free Air Temperature Range
DM54ALS
-55·eto + 125·C
DM74ALS
O"Cto +70·C
Storage Temperature Range

-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS1004

Parameter

DM74ALS1004

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

V

2

2

10H

High Level Output Current

-12

-15

mA

10L

Low Level Output Current

12

24

mA

TA

Free Air Operating Temperature

70

·c

-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.

Symbol

Parameter

Conditions

Min

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VOH

High Level Output
Voltage

10H = -0.4 mA, Vee = 4.5V to 5.5V

Low Level Output
Voltage

Vee = 4.5V

Input Current at Max
Input Voltage

Vee = 5.5V, VIH = 7V

Units
V

2

10H = Max, Vee = 4.5V

II

Max
-1.5

Vee -2
V

2.4

10H = -3 mA, Vee = 4.5V
VOL

Typ

54174ALS
10L = 12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

/LA

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.1

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

Icc

Supply Current

Vee = 5.5V

-112

mA

Outputs High

-30
0.84

3

mA

Outputs Low

7

12

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS1004

Conditions
Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

2-286

DM74ALS1004

Units

Min

Max

Min

Max

1

9

1

7

ns

1

8

1

6

ns

,-------------------------------------------------------------------, c

~

NatiOnal

~ Semiconductor

U1

:=

Corporation

~
....

DM54ALS1005/DM74ALS1005 Hex Inverting Drivers
with Open Collector Outputs
General Description

Features

These devices contain six independent drivers, each of
which performs the logic INVERTIComplement function.
The outputs require external pull-up resistors for proper logical operation. The 'ALS 1005 is a driver version of the
'ALS05A.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

Pull-Up Resistor Equations
R

Vee (Min) - VOH
MAX = N1 (IOH) + N2 (IIH)

R
MIN =
Where:

Vee (Max) - VOL
IOL - N3 (I"J

N1 (IOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (IIH) = total maximum input high current for all
inputs tied to pull-up resistor
N3 (I"J = total maximum input low current for all
inputs tied to pull-up resistor

Connection Diagram
Dual-In-Une Package

vee:

YB
12f

As

14i'

13f

~

1
......

1 ...

IJ

AJ

1

"

Ys

At;

"i
...

-joo,.

"

3J.At

2),

j

J

I"...
"

1 ...

1 "

1

~Y2

Y4

loi

~I
As

Ji

1

1

3

BJ

~lD
TLlF/6253-1

Order Number DM54ALS1005J or DM74ALS1005M, N
See NS Package Number J14A, M14A or N14A

Function Table
Y=A

L
H

Input

Output

A

Y

H

L

L

H

= Low Logic Level
= High logic Leve'

2-287

g

U1
.....

C

~
.....

:=
~
....

o
o

U1

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the devies cannot be guaranteed. The devies should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual devies operation.

If Military/Aerospace specHled devices are required,
contact the ,,!atlonal Semiconductor Sales Office/
Distributors for availability and speclflcetlons_

Supply Voltage
7V
Input Voltage
7V
Off-State Output Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55"C to + 125"C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65"Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS1005

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS1005

Units

",in

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2

Vil

Low Level Input Voltage

0.7

0.8

VOH

High Level Output Voltage

5.5

5.5

V

IOl

Low Level Output CUrrent

12

24

mA

TA

Free Air Operating Temperature

70

"C

-55

125

0

V

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

= 5V, TA = 25"C.

Symbol

Typ

Parameter

Conditions

Min

= 4.5V,II = -18 mA
= 4.5V. VOH = 5.5V
54174ALS
Vee = 4.5V
IOl = 12mA

Max

Units

VIK

Input Clamp Voltage

Vee

-1.5

V

IOH

High Level Output Current

Vee

100

IJoA

VOL

Low Level Output
Voltage

0.25

0.4

V

0.35

0.5

V

0.1

mA

74ALS
IOl = 24mA
II

Input Current at Max
Input Voltage

Vcc

= 5.5V, VIH = 7V

= 5.5V. VIH = 2.7V
= 5.5V, VIL = 0.4V
Outputs High
Vee = 5.5V

IIH

High Level Input Current

Vee

20

IJoA

III

Low Level Input Current

Vee

-0.1

mA

Icc

Supply Current

0.9

3

mA

7

12

mA

Outputs Low

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

DM54ALS1005

Conditions

Vee = 4.5V to 5.5V
RL = 6670
CL = 50pF

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Note

1: See Section 1 lor lest waveform. and outpulload.

2-288

DM74ALS1005

Units

Min

Max

Min

Max

5

35

5

30

ns

2

12

2

10

ns

Nalional

~ Semiconductor
Corporation

DM54ALS 1008A/DM74ALS 1008A
Quadruple 2-lnput AND Buffers
General Description

Features

These devices contain four independent 2-input buffers,
each of which performs the logic AND function. The
'ALS1008A is a buffer version of the 'ALS08.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Improved line receiving characteristics

Connection Diagram
Dual-In-Llne Package
Vee

B4

A4

Y4

83

A3

Y3

8

A1

81

Y1
TLlF/6254-1

Order Number DM54ALS1008AJ,
DM74ALS1008AM or DM74ALS1008AN
See NS Package Number J14A, M14A or N14A

Function Table
Y = AB
Inputs

L
H

Output

A

B

Y

L
L
H
H

L
H
L
H

L
L
L
H

= Low Logic Level
= High Logic Lavel

2·289

Absolute Maximum Ratings
Note: The "Absolute Maximum RaUngs"aretf/ose values
beyond which the safety of the deviCe cannot b9 guaranteed The device should not be operated at th6se limits. The
perametric values defined in the "Electrical CheracterisUcs"
table are not guaranteed at the absolute maximum raUngs.
The "Recommended OperaUng CondiUons" table will define
the condiUons for actual device operaUon.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors tor availability and specifications.
Supply Voltage
7V
Input Voltage

7V

Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range

-65·Cto + 150·C

Recommended Operating Conditions
Symbol

DM74ALS1008A

DM54ALS1008A

Parameter

Unlta

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-1

-2.6

mA

24

mA

70

·c

10L

Low Level Output Current

TA

Free Air Operating Temperature

V
V

2

2

12
-55

0

125

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vcc

Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Conditions

=

= 4.5V,11 = -18 mA
Vee = 4.5V
10H = Max
VIH = 2V
Vcc = 4.5V to 5.5V
10H = -400,.A
54174ALS
Vcc = 4.5V
VIH = 2V
10L = 12mA

5V, TA

Typ

Min

Vcc

2.4

=

5.5V, VIH

=
=
Vee =
Vcc =

Input Current @ Max
Input Voltage

Vee

=

25·C.

Max

Units

-1.5

V
V

3.2

Vcc- 2

V

74ALS
10L = 24·mA
II

=

0.25

0.4

V

0.35

0.5

V

0.1

mA

7V

= 2.7V
= O.4V
5.5V, Vo = 2.25V
5.5V, VI = OV

IIH

High Level Input Current

Vee

5.5V, VIH

20

IJ.A

IlL

Low Level Input Current

Vcc

5.5V, VIL

-0.1

mA

10

Output Drive Current

-112

mA

ICCH

Supply Current
with Outputs High

1.8

3

mA

ICCL

Supply Current
with Outputs Low

5.7

9.3

mA

Vcc

=

5.5V, VI

=

-30

4.5V

Switching Characteristics
over recommended operating free air temperature range (Note 1).

Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Conditions
Vee = 4.5V to 5.5V
RL = 500n
CL = 50 pF

Note 1: See Section 1 for test waveforms and output load.

2-290

DM54ALS1008A

DM74ALS1008A

Min

Max

Min

Max

2

11

2

9

ns

3

11

3

9

ns

Units

r-------------------------------------------------------------------,c
_

i:

NaHonal
Semiconductor
CorporaHon

U'I

:t
Ii)

DM54ALS 101 OA/DM74ALS1 01 OA
Triple 3-lnput NAND Buffers

....
....
~c

General Description

Features

:t

These devices contain three independent buffers, each of
which performs the logic NAND function. The 'ALS1010A is
a buffer version of the 'ALS10A.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Improved line receiving characteristics

o

i:
......

Ii)

....o
....
~

Connection Diagram
Dual-In-Line Package

vcc

C1

Y1

C3

83

A3

Y3

A1

81

A2

82

C2

Y2

GND
TLlF/6255-1

Order Number DM54ALS1010AJ,
DM74ALS1010AM or DM74ALS1010AN
See NS Package Number J 14A, M14A or N 14A

Function Table
Y = ABC
Inputs

Output

A

B

C

Y

L

X

X
X
H

L

X
X

X
H

L

H
H
H

H

L

L ~ Low Logic Level
H

~

High Logic Level

X ~ EHher Lew or High Legic Level

EI
2-291

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Seles Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
- 55·C to + 125·C
DM54ALS
DM74ALS
O"Cto +70·C
-65·Cto + 150"C
Storage Temperature Range

Note: The "Absolute Maximum Ratings" af,8 those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Opetating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

DM74ALS1010A

DM54ALS1010A

Parameter

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

IOH

High Level Output Current

-1

-2.6

mA

IOL

Low Level Output Current

12

24

mA

TA

Free Air Operating Temperature

70

·C

2

2

-55

125

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Conditions

=

5V, TA

Min

= 4.5V, 'I = -18 mA
Vcc = 4.5V
10H = Max
VIL = VILMax
10H = -400",A
Vee = 4.5V to 5.5V
54174ALS
Vee = 4.5V
10L = 12mA
VIH = 2V

=

25·C.

Typ

Vee

2.4

Units
V
V

3.2

V

Vee - 2

74ALS
10L = 24mA

0.25

0.4

V

0.35

0.5

V

0.1

mA

=

5.5V, VIH

Vcc

=
=
Vee =
Vcc =
Vcc =

5.5V, VIH

20

",A

Vee

5.5V, VIL

-0.1

mA

'I

Input Current at Max
Input Voltage

Vee

IIH

High Level Input Current

IlL

Low Level Input Current

10

Output Drive Current

ICCH

Supply Current with Outputs High

ICCL

Supply Current with Outputs Low

=

Max
-1.5

7V

= 2.7V
= 0.4V
5.5V, Vo = 2.25V
5.5V, VI = OV

-30

5.5V, VI "" 4.5V

-112

mA

0.65

1.2

mA

3.6

5.8

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS1010A

Conditions
Vee = 4.5V to 5.5V
RL = 5000.
CL = 50pF

Note t: See Section 1 for test waveforms and output load.

2·292

DM74ALS1010A

Units

Min

Max

Min

Max

2

12

2

8

ns

2

12

2

8

ns

r------------------------------------------------------------------.o

s:::

~ Semiconductor
Nattonal

~

CorporaHon

Ii)

....
o
....
....

DM54ALS1011A/DM74ALS1011A
Triple 3-lnput AND Buffers

~

General Description

Features

:t

These devices contain three independent buffers, each of
which performs the logic AND function. The 'ALS1011A is a
buffer version of the' ALS11 A.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Improved line receiving characteristics

o

iii:

.....

Connection Diagram
Dual-In-Llne Package
Vee

C1

Y1

2
A1

B1

C3

B3

A3

C2

Y2

3
A2

GND
TUF/6256-1

Order Number DM54ALS1011AJ,
DM74ALS1011AM or DM74ALS1011AN
See NS Package Number J14A, M14A or N14A

Function Table
y= ABC
Inputs

Output

A

B

C

Y

L

X

X
X
H

L

X
X

X
H

L

L
L
L

H

H

= Low Logic Level
H = High Logic Level
X = Either Low or High Logic Level
L

2-293

Ii)

....o
........

~

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those valu8S
beyond which the ssfety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electricsl Characteristics"
tsbIe are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National semiconductor Sales Office/
Distributors for availability and speclflcatlona.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Condlti()ns
Symbol

DM54ALS1011A

Parametar

DM74ALS1011A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

V

2

2

10H

High Level Output Current

-1

-2.6

mA

10L

Low Level Output Current

12

24

mA

TA

Free Air Operating Temperature

70

·c

-55

125

0

,

Electrical Characteristics

over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Parameter

Symbol

Conditions

Min

Typ

Max

Units

-1.5

V

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V
VIH = 2V

10H = Max

Vee = 4.5V to 5.5V

10H = -400~

VOL

Low Level Output
Voltage

Vee = 4.5V
VIH = 2V

54174ALS
10L = 12 rnA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

2.4

V

3.2

Vee- 2

V

II

Input Current at Max
Input Voltage

Vee = 5.5V, VIH = 7V

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

JJ-A

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.1

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

-112

rnA

ICCH

Supply Current with Outputs High

Vee = 5.5V, VI = OV

1.4

2.3

mA

ICCl

Supply Current with Outputs Low

Vcc = 5.5V, VI = 4.5V

4.3

7

mA

-30

'.

Switching Characteristics

>

over recommended bperating free air temperature range (Note 1).

,
Symbol
tpLH

Paremeter

..

Propagation Delay Time
Low to High Level Output

Conditions
Vee = 4.5Vto5.5V
Rl = 500n
CL=50pF

Propagation Delay Time
High to Low Level Output
Note 1: Sea Section 1 for test waveforms and output load.

tpHL

2-294

DM54ALS1011A

DM74ALS1011A

Min

Max

Min

Max

2

12

2

10

ns

3

11

3

9

ns

Units

.------------------------------------------------------------------.0
_

iii:

National

UI

:;
Ii)
....
~
.....

Semiconductor
Corporation

Q

DM54ALS1020A/DM74ALS 1020A
Dual 4-lnput NAND Buffers

o

!i!:

~

General Description

Features

These devices contain two independent 4-input buffers,
each of which performs the logic NAND function. The
'ALS1020A is a buffer version of the 'ALS20A.

• Switching specifications at 50 pF
• Switching speCifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TIL
procass
• Improved line receiving characteristics

Connection Diagram
Dual-In-Llne Package
VCC

02

114

2

1

AI

C2

13

Bl

NC

12

B2

111

13

4
Cl

NC

A2

10

5
01

19

V2

8

16 17
VI

GNO
TL/F/B257-1

Order Number DM54ALS1020AJ,
DM74ALS1020AM or DM74ALS1020AN
See NS Package Number J14A, M14A or N14A

Function Table
y

= ABCD

Inputs

Output

A

B

C

D

Y

L

X

X
X
X

L

X
X

X
X

X
X
X

X

H

H

H

H
H
H
H
L

L

= Low Logic Level
= High Logic Level
X = Either Low or High Logic Level
L

H

2-295

L
H

Ii)

....
~
Q

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Ottlce/
Distributors for availability and speclflcatlona.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·Cto +15O"C

Note: The "Absoluts Msximum Ratings" ara thoss values
beyond which the safety of the devics cannot be guarant88d. The devics should not be operated at thsselimits. The
parametric values defined in th8 "Elsctrical Charactsristics"
table ara not guarantssd at the absoluts msximum ratings.
The "Rscommended Operating Conditions" table will define
th8 conditions for actual devics operation.

Recommended Operating Conditions
Symbol

DM74ALS1020A

DM54ALS1020A

Parameter

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

2

2

V

10H

High Level Output Current

-1

-2.6

rnA

10L

Low Level Output Current

12

24

rnA

TA

Free Air Operating Temperature

70

·C

-55

125

0

Electrical Characteristics

= 5V, TA = 25·C.

over recommended operating free air temperature range. All typical values are measured at Vcc
Symbol

Conditions

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Min

= 4.5V,11 = -18mA
Vee = 4.5V
IOH = Max
VIL = VILMax
Vcc = 4.5V to 5.5V
10H = -400/LA
54/74ALS
Vee = 4.5V
10L = 12mA
VIH = 2V

Typ

Vee

2.4

Input Current at Max
Input Voltage

Vee

V
V
V

Vee- 2
0.25

0.4

V

0.35

0.5

V

0.1

rnA

= 5.5V, VIH = 7V

= 5.5V, VIH = 2.7V
= 5.5V, VIL = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V, VI = OV
Vee = 5.5V, VI = 4.5V

Units

3.2

74ALS
10L = 24 rnA
II

Max
-1.5

IIH

High Level Input Current

Vee

20

IlL

Low Level Input Current

Vee

-0.1

/LA
rnA

10

Output Drive Current

ICCH

Supply Current with Outputs High

ICCL

Supply Current with Outputs Low

-30

-112

rnA

0.5

0.8

rnA

2.4

3.9

rnA

Switching Characteristics over rscommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay TIme
High to Low Level Output

Conditions
Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

2-296

DM54ALS1020A

DM74ALS1020A

Min

Max

Min

Max

2

10

2

8

ns

2

10

2

7

ns

Units

•

National
Semiconductor
Corporation

DM54ALS1 032A/DM7 4ALS 1032A
Quadruple 2-lnput OR Buffers
General Description

Features

These devices contain four independent buffers, each of
which performs the logic OR function. The 'ALS1032A is a
buffer version of the 'ALS32.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Improved line receiving characteristics

Connection Diagram
Dual-In-Llne Package

7
A1

B1

Y1

A2

B2

Y2

GND
TL/F/6258-1

Order Number DM54ALS1032AJ,
DM74ALS1032AM or DM74ALS1032AN
See NS Package Number J14A, M14A or N14A

Function Table
Y=A+B
Inputs
A

B

L
H

X

X

H

L

Output
Y
L
H
H

L

~

Low Logic Level

H
X

~
~

High logiC Level
EHher Low or High Logic Level

fI
2·297

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales OffIce/
Distributors for availability and specifications.
Supply Voltage
7V

parametric values defined in the "Electrical Characteristics"
table are not guBrantaed at the absolute maximum ratings.
The "RecomlTlflfldBd Operating Conditions" table will define
, the conditions for actual device operation.

Input Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"C to + 70"C
Storage Temperature Range
-65·CIo + 150"C

Recommended Operating Conditions
Symbol

DM54ALS1032A

Parameter

DM74ALS1032A

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-1

-2.6

mA

10L

Low Level Output Current

12

24

mA

TA

Free Air Operating Temperature

70

·C

2

V

2

-55

125

0

Electrical Characteristics

= 5V, TA = 25·C.

over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Typ

Min

Conditions

= 4.5V, II = -18 mA
Vee = 4.5V
10H = Max
VIH = 2V
Vee = 4.5V to 5.5V
10H = -400 p.A
54/74ALS
Vee = 4.5V
VIH = 0.8V
10L = 12mA
Vee

2.4

Input Current at Max
Input Voltage

Vee

Units
V
V

3.2

Vee -2

V

74ALS
10L = 24mA
II

Max
-1.5

0.25

0.4

V

0.35

0.5

V

0.1

mA

= 5.5V, VIH = 7V

= 5.5V, VIH = 2.7V
= 5.5V, VIL = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V, VI = 4.5V

IIH

High Level Input Current

Vee

20

/loA

IlL

Low Level Input Current

Vee

-0.1

rnA

10

Output Drive Current

-112

rnA

ICCH

Supply Current
with Outputs High

2.5

5

mA

leeL

Supply Current
with Outputs Low

6.6

10.6

rnA

Vee

-30

= 5.5V. VI = OV

Switching Characteristics over recornmended operating free air temperature range (Note 1)
Symbol

Paremeter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS1032A

Conditions
Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Nota 1: See Section 1 for test waveforms and output load.

2-298

DM74ALS1032A

Units

Min

Max

Min

Max

2

12

2

9

ns

3

15

3

12

ns

r-------------------------------------------------------------------, C

rJ

!i:

National
Semiconductor
CorporaHon

UI

:t

...

~

DM54ALS 1034/DM7 4ALS 1034 Hex Non-Inverting Drivers
General Description

Features

These devices contain six independent drivers, each of
which performs the logic identity function.

_ Switching specifications at 50 pF
_ Switching specifications guaranteed over full temperature and Vee range
_ Advanced oxide-isolated, ion-implanted Schottky TTL
process
_ Functionally and pin for pin compatible with Schottky
and Low Power Schottky TTL counterpart
_ Improved AC performance over Schottky and low power Schottky counterparts

~

i.....
:t

...

~

~

Connection Diagram
Dual-In-Una Package

At!

'rf

...

IIi

1

2J,

3

Az

~~

g~

V

'0

........

.....

I ... I

I ... I

'J~.

As

Va

,i

5}_
Aa

:i

I........ I

I
BJ3

:10
TUF/6259-1

Order Number DM54ALS1034J or DM74ALS1034M, N
See NS Package Number J14A, M14A or N14A

Function Table
Y=A

L
H

Input

Output

A
H
L

V
H
L

= Low Logic Level
= High Logic Level

fI
2-299

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual d~vice operation.

Input Voltage
: 7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O"Cto +70"C
Storage Temperature Range
- 65·C to + 150·C

Recommended Operating Conditions
Symbol

DM54ALS1034

Parameter

DM74ALS1034

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-12

-15

mA

24

mA

70

·C

2

10L

Low Level Output Current

TA

Free Air Operating Temperature

2

V

12
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Min

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VOH

High Level Output
Voltage

10H = -0.4 mA, Vee = 4.5V to 5.5V

Low Level Output
Voltage

II

Input Current @ Max
Input Voltage

Vee = 5.5V, VI = 7V

Units
V
V

2

10H = Max, Vee = 4.5V

Vee = 4.5V

Max
-1.2

Vee - 2

V

2.4

10H = -3 mA, Vee = 4.5V
VOL

Typ

54174ALS
IOL=12mA

0.25

0.4

V

74ALS
10L = 24mA

0.35

0.5

V

0.1

mA

IIH

High Level Input Current

Vee = 5.5V, VI = 2.7V

20

p.A

IlL

Low Level Input Current

Vee = 5.5V, VI = 0.4V

-0.1

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

Icc

Supply Current

Vee = 5.5V

-112

mA

Outputs High

-30
3

6

mA

Outputs Low

8

14

mA

Switching Characteristics over recommended operating free air temperature range (Note 1).
Symbol
tpLH

Parameter
Propagation Delay Time
Low to High Level Output

DM54ALS1034

Conditions
Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Propagation Delay Time
High to Low Level Output
Nota 1: See Section 1 for teBt waveform. and output load.

tpHL

2·300

DM74ALS1034

Units

Min

Max

Min

Max

1

11

1

8

ns

1

13

1

8

ns

FJ

i

National

t.n
....

Semiconductor
Corporation

DM54ALS 1035/DM74ALS 1035 Hex Non-Inverting Drivers
with Open Collector Outputs
General Description

Features

These devices contain six independe!lt drivers, each of
which performs the logic identity function. The outputs require an external pull-up resistor for proper logical operation.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperatura and Vee range
• Advanced oXide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

~C

ill:
....,

.n~
....

B

UI

Connection Diagram
Dual-In-Une Package

:,c

14

....
.....

1.1

I

gr

l

10

.....
J'oo..

I~
31At

2).

.'i

I ....... I

.....

.....

.....

I~
..

At;

IIf

1111&

13

~

4

5

2

~

1

&J3

~!o
TUF/6260-1

Order Number DM54ALS1035J or DM74ALS1035M, N
See NS Package Number J14A, M14A or N14A

Function Table
Y=A

L

Input

Output

A

Y

L

L

H

H

= Low Logic Level

H = High Logic Level

PI
2-301

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
1V
Input Voltage
1V

Note: The "Absolute MBJdmum Ratings" are those values
beyond which the safety of the device cannot be. guarenteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute mBJdmum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Off·State Output Voltage
7V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM14ALS
O"Cto +10"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS1035

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS1035

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2

VIL

Low Level Input Voltage

0.7

0.8

V

VOH

High Level Output Voltage

5.5

5.5

V

24

mA

10

·c

IOL

Low Level Output Current

TA

Free Air Operating Temperature

12
-55

125

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee

=

4.5V.11

IOH

High Level Output Current

Vee

4.5V. VOH

VOL

Low Level Output
Voltage

Vee

=
=

=

Min

5V. TA

=

25·C.

Max

Units

-18 mA

-1.5

V

=

100

/loA

4.5V

5.5V

54174ALS
IOL = 12mA

0.25

0.4

V

14ALS
IOL = 24mA

0.35

0.5

V

0.1

mA

II

Input Current @ Max
Input Voltage

Vee

=

5.5V. VIH

=

IIH

High Level Input Current

Vee

Low Level Input Current

Vee

= 2.7V
= O.4V

lee

Supply Current

Vee

=
=
=

5.5V. VIH

IlL

5.5V. VIL

=

Typ

5.5V

1V

20

/loA

-0.1

mA

Outputs High

3

6

mA

Outputs Low

8

14

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM54ALS1035

Conditions
Vee = 4.5V to 5.5V
RL = 6800
CL = 50pF

Note 1: See Section 1 for lesl waveforms and oulpulload.

2·302

DM14ALS1035

Units

Min

Max

Min

Max

5

35

5

30

ns

2

14

2

12

ns

National
Semiconductor
Corporation

_

PRELIMINARY

DM54ALS1240/DM74ALS 12401
DM54ALS1241A/DM74ALS1241A
Octal TRI-STATE® Bus Drivers
General Description

Features

These octal TRI-STATE bus drivers are designed to provide
the designer with flexibility in implementing a bus interface
with memory, microprocessor, or communication systems,
and are low power dissipation versions of the 'ALS240 and
'ALS241. The output TRI-STATE gating control is organized
into two separate groups of four buffers. The' ALS1240 control inputs symmetrically enable the respective outputs
when set logic 10111', while the 'ALS1241A has complementary enable gating. The TRI-STATE circuitry contains a feature
that maintains the buffer outputs in TRI-STATE (high impedance state) during power supply ramp-up or ramp-down.
This eliminates bus glitching problems that arise during
power-up and power-down.

• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Switching response specified into 500n and 50 pF load
• Switching response specifications guaranteed over full
temperature and Vee supply range
• PNP input design reduces input loading
• Low power dissipation version of the DM54174ALS240,
241
• Low level drive current: 54ALS = 8 mA, 74ALS = 16 mA

Connection Diagrams
Dual-In-Llne Package

u

1(1-1

Dual-In-Llne Package

20 !-Vcc

U

111-1

1A1- 2

20 -Vee

1A1- 2

19 -2G

2Y4- 3

18 i-1Y1

2Y4- 3

18 -1Y1

1A2- 4

17i-2A4

1A2- 4

17 -2A4

2Y3- 5

16i-1Y2

2Y3- 5

16-1Y2

1A3- 6

15 -2A3

lA3- 6

15 -2A3

2Y2- 7

14 -1Y3

2Y2- 7

14,-1Y3

1A4- 8

13 -2A2

1A4- 8

13 -2A2

2Y1-9

12 -lY4

2Y1-9

12!-lY4

GND- 10

11-2A1

GND- 10

TLlF/6261-1

11 r-2A1

TL/F/6261-2

Top View

Top View

Order Number DM54ALS1240J,
DM74ALS1240WM or DM74ALS1240N
See NS Package Number J20A, M20B or N20A

Order Number DM54ALS1241AJ,
DM74ALS1241AWM or DM74ALS1241AN
See NS Package Number J20A, M20B or N20A

Function Tables
'ALS1240
Input
G

H

'ALS1241A
Input

Output
A

y

2G

'ALS1241A
Input

Output

y

2A

1G

Output
1A

Y

L

L

H

H

L

L

L

L

L

L

H

L

H

H

H

L

H

H

Z

L

H
X
= High Level Logic Slale

L

= Low Level Logic Slale

X

X
Z
X
Z
H
= Don'l Care (Eilher Low or High Level Logic Slate) Z = High Impedance (Off) Slate

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

2-303

fI

Absolute Maximum Ratings
Note: The "Absolute Msximum Ratings" alTJ thoss values
beyond which the safety of the device cannot be guarantS6d. The device should not be operated at thesfillmilB. The
parBmfltric values defined in the "EI9ctricaI Characteristics"
tabl9 BITJ not guarant99d at the absolute msximum ratings.
The "R9COfTImfindfld Operating Conditions" tabl9 will deRnfi
the conditions for actual device operation.

If Military/Aerospace sp8cHled devices are required,
contact the National Semiconductor Seles OffIce/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125"C
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS1240
DM54ALS1241A

Paremeter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS1240
DM74ALS1241A

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

2

2

V
V

Vil

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-12

-15

mA

16

mA

70

·C

10l

Low Level Output Current

TA

Operating Free Air Temperature

8
-55

125

0

Electrical Characteristics
over recommended operating free alr temperature range (unless otherwise specified)
Symbol

Parameter

VIK

Input ClampVoltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Conditions

= 4.5V,11 = -18 rnA
Vee = 4.5V to 5.5V
10H = -0.4mA
Vee = 4.5V
10H = -3mA
10H = Max
54174ALS
Vee = 4.5V
10l = 12mA

Min

Typ

Vee

Max

Units

-1.2

V

Vee- 2

V

2.4

V

2

V

74ALS
10l = 24mA

0.25

0.4

V

0.35

0.5

V

0.1

mA

= 5.5V, VI = 7V

II

Input Current at Max
Input Voltage

Vee

IIH

High Level Input Current

Vee

20

p.A

III

Low Level Input Current

Vee

-0.1

mA

10

Output Drive Current

-112

rnA

10ZH

High Level TRI-STATE
Output Current

20

p.A

10Zl

Low Level TRI-STATE
Output Current

Vee

-20

p.A

lee

Supply Current

Vee = 5.5V, ALS1240
Outputs High

5

8

mA

Outputs Low

8

14

rnA

Outputs TRI-STATE

8

13

mA

Vee = 5.5V, ALS1241
Outputs High

7

Outputs Low

10

rnA

Outputs TRI-STATE

11

mA

= 5.5V, VI = 2.7V
= 5.5V, Vil = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V, Vo = 2.7V

-30

= 5.5V, Vo = 0.4V

2-304

mA

'ALS 1240 Switching Characteristics
over recommended operating free air temperature range (see Section 1 for Test Waveforms and Output Load)

Symbol

Parameter

From
(Input)

Vee = 4.5V to 5.5V, CL = 50 pF,
R1 = 500n, R2 = 500n,
TA = Min to Max

To
(Output)

DM54ALS1240

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tPZH

Output Enable Time
to High Level Output

tPZL

Output Enable Time
to Low Level Output

tpHZ

Output Disable Time
from High Level Output

tpLZ

A

G

G

Units

DM74ALS1240

Min

Max

Min

Max

2

16

2

13

ns

2

16

2

13

ns

4

23

4

20

ns

6

28

6

22

ns

2

12

2

10

ns

3

18

3

13

ns

y

y

y

Output Disable Time
from Low Level Output

'ALS1241A Switching Characteristics
over recommended operating free-air temperature range (see Section 1 for Test Waveforms and Output Load)

Symbol

tpLH

Parameter

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tPZH

Output Enable Time
to High Level Output

tPZL

Output Enable Time
to Low Level Output

tpHZ

Output Disable Time
from High Level Output

tpLZ

From
(Input)

Vee = 4.5V to 5.5V, CL = 50 pF,
R1 = 500n, R2 = 500n,
TA = Min to Max

To
(Output)

Units

DM54ALS1241A

DM74ALS1241A

Min

Min

Max

Max
ns

A

y
ns
ns

GorG

y
ns
ns

GorG

y

Output Disable Time
from Low Level Output

ns

PI
2-305

c .----------------------------------------------------------------,

-~

i

Logic Diagrams
DM54174ALS1240

DM54174ALS1241A

.....

::&

•-Q

~

i

::&

18 1Y1

18 1Y1

16 1Y2

16 1Y2

14

1Y3

14 1Y3

12 1Y4

12 1Y4

:>0--+"";;"2Y1

>_+...;..9 2Y1

Q

.....

~
~

~

Q

!-

>_-+__
7 2Y2

_1.>0--+_7;.. 2Y2

i

>_-+__
5 2Y3

::&
Q

> ___

.;..3

2Y4
TL/F/6261-4

TUF/6261-3

2-306

_

National
Semiconductor
Corporation

PRELIMINARY

DM54ALS1242/DM74ALS12421
DM54ALS 1243A/DM74ALS1243A

Quad Bidirectional Bus Drivers
General Description

Features

These octal TRI-STATEiII> bus drivers are designed to provide the designer with flexibility in implementing a bus interface with memory, microprocessor, or communication systems, and are low power dissipation versions of the
'ALS242 and 'ALS243. The 'ALS1242 has inverting buffers,
while the 'ALS1243A has non-inverting buffers. The direction enable gating is configured with separate control over
either buffer direction and the two control buffers are complementary. Connecting these control inputs to one common line implements single line direction control, while individual control can put both buffer directions into TRI-STATE
Simultaneously (disabled state) or put both buffer directions
into the active state (data latch state). The TRI-STATE circuitry contains a feature that maintains the buffer outputs in
TRI-STATE (high impedance state) during power supply
ramp-up or ramp-down. This eliminates bus glitching problems that arise during power-up and power-down.

• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Switching response specified into soon and 50 pF load
• Switching response specifications guaranteed over full
temperature and Vee supply range
• PNP input design reduces input loading
• Low power diSSipation version of the DM54/74ALS242,
243
• Low level drive current: 54ALS = 8 mA, 74ALS = 16 mA

Connection Diagram
Dual-In-Une Package

U

IIAI- 1

14 rYcc

NC- 2

13 r-GBA

Al- 3

12 rNC

A2- 4

11 rB1

A3-

s

10 r-B2

M-

6

9r-B3

GND- 7

Br-B4
TL/F/6262-1

Top View
Order Number DM54ALS1242J, DM54ALS1243AJ, DM74ALS1242M,
DM74ALS1243AM, DM74ALS1242N or DM74ALS1243AN
See NS Package Number J14A, M14A or N14A

Function Table
Inputs
GAB

ALS1242A

ALS1243A

GBA

L

L

AtoB

AtoB

H

H

BtoA

BtoA

H

L

Isolation

Isolation

L

H

LatchAandB
(A=B)

LatchAandB
(A= B)

This document contains Information on a product under developmenl NSC reserves the right to change or discontinue this product wKhout nctlce.

2-307

fI

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vee
7V
Input Voltage
Dedicated Inputs
7V
1/0 Ports
5.5V
Operating Free Air Temperature Range
DM54ALS
- 55·C to + 125·C
DM74ALS
O·Cto +700C
Storage Temperature Range
- 65·C to + 1500C

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table ara not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

DM54ALS1242
DM54ALS1243A

Parameter

DM74ALS1242
DM74ALS1243A

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

2

V

2

IOH

High Level Output Current

-12

-15

rnA

IOL

Low Level Output Current

8

16

rnA

TA

Operating Free-Air Temperature

70

·c

-55

125

0

Electrical Characteristics over recommended operating free-air temperature (unless otherwise specified)
Symbol

VIK
VOH

VOL

II
IIH

Parameter

Conditions

DM54ALS1242
DM54ALS1243A

DM74ALS1242
DM74ALS1243A

Min

Min

Typ

Max

Typ

Units

Max

-1.2
-1.2
= 4.5V, II = -18 mA
= 4.5Vt05.5V IOH = -0.4mA
Vee- 2
Vee - 2
2.4
2.4
Vee = 4.5V
10H = -3mA
2
2
10H = Max
Low Level Output
0.4
Vee = 4.5V
10L = 54ALS (Mal<)
0.25
0.4
0.25
Voltage
0.35
0.5
10L = 74ALS (Max)
- Input Current at Max Vee = 5.5V. VI = 7V
0.1
0.1
Input Voltage
(VI = 5.5V for A or B Ports)
High Level Input
Vee = 5.5V, VI = 2.7V
Input Clamp Voltage Vee

V

High Level Output
Voltage

V

Vee

Current

V
V
V
V
rnA

20

20

/LA

-0.1

-0.1

rnA

-112

rnA

IlL

Low Level Input
Current

Vee

= 5.5V. VIL = 0.4V

10

Output Drive
Current

Vee

= 5.5V. Vo = 2.25V

lee

Supply Current

Vee = 5.5V, ALS1242
Active Outputs High

8

14

8

12

mA

Active Outputs Low

10

17

10

15

rnA

Outputs TRI-STATE

9

16

9

14

rnA

"':112

-30

-30

Vee = 5.5V,ALS1243
Active Outputs High

9

9

mA

Active Outputs Low

10

10

mA

Outputs TRI-STATE

11

11

rnA

2-308

'ALS1242 Switching Characteristics
over recommended operating free·air temperature range (see Section 1 for Test Waveforms and Output Load)
Vee
Symbol

Parameter

= 4.5V to 5.5V, CL = SO pF,
= 6000, R2 = SODa,
TA = Minto Max

R1

From (Input)
To (Output)

54ALS1242

Units

74ALS1242

Min

Max

Min

Max

tpLH

Propagation Delay Time
Low to High Level Output

AorB
toBorA

2

14

2

12

ns

tPHL

Propagation Delay Time
High to Low Level Output

AorB
toBorA

2

12

2

10

ns

tpZH

Output Enable Time
to High Level Output

~AB
toB

4

20

4

17

ns

tPZL

Output Enable Time
to Low Level Output

GAB
toB

5

23

5

21

ns

tpHZ

Output Disable Time
from High Level Output

GAB
toB

2

12

2

10

ns

tpLZ

Output Disable Time
from Low Level Output

GAB
toB

2

12

2

10

ns

tpZH

Output Enable Time
to High Level Output

GBA
toA

5

23

5

20

ns

tPZL

Output Enable Time
to Low Level Output

GBA
toA

6

25

6

23

ns

tpHZ

Output Disable Time
from High Level Output

GBA
toA

2

12

2

10

ns

tpLZ

Output Disable Time
from Low Level Output

GBA
toA

2

15

2

12

ns

'ALS1243A Switching Characteristics
over recommended operating free-air temperature range (see Section 1 for Test Waveforms and Output Load)
Vee
Symbol

Parameter

= 4.5V to 5.5V, CL = 50 pF,
= 5000, R2 = SODa,
TA = Min to Max

R1

From (Input)
To (Output)

54ALS1243A
Min

Max

Units

74ALS1243A
Min

Max

tpLH

Propagation Delay Time
Low to High Level Output

AorB
toBorA

ns

tpHL

Propagation Delay Time
High to Low Level Output

AorB
toBorA

ns

tPZH

Output Enable Time
to High Level Output

GAB
toB

ns

tpZL

Output Enable Time
to Low Level Output

~AB
toB

ns

tpHZ

Output Disable TIme
from High Level Output

~AB
toB

ns

tpLZ

Output Disable Time
from Low Level Output

GAB
toB

ns

tpZH

Output Enable Time
to High Level Output

GBA
toA

ns

tpZL

Output Enable Time
to Low Level Output

GBA
toA

ns

tpHZ

Output Disable Time
from High Level Output

GBA
toA

ns

tpLZ

Output Disable Time
from Low Level Output

GBA
toA

ns
2·309

fI

-....-f-----,;.;;.

A3

.,;..---+........... >-......+----...;;. B3

A4 - - - - -..........

>--++----.;.. B4
TLlF/6262-3

2·310

.-----~-----------------------------------------------------------.c

_

,

National

E

semiconductor
Corporatton

Ii)

....

~c

DMS4ALS1 ~44A/DM74ALS1244A
Octal TRI-STATE® Bus Driver

iii:

t

General Description

Features

This octal TRI-STATE bus driver is designed to provide the
designer with flexibility in implementing a bus inter:fll,ce with
memory. microprocessor. or communication systems. and is
a low pOwer diSSipation version of the' ALS244. The output
TRI-STATE gating control is organized into two separate
groups of four buffers. and both control inputs enable the
respective outputs when set logic low. The T,RI-STATE circuitry contains a feature that maintains the buffer outputs in
TRI-STATE (high impedance state) during power supply
ramp-up or ramp-down. This eliminates bus glitching problems that arise during power-up and power-down.

• Advanced oxide-isolated. ion-implanted Schottky TTL
process
• Switching response specified into 5000 and 50 pF load
• Switching response specifications guaranteed over full
temperature and Vee supply range
• PNP input design reduces input loading
• Low power dissipation version of the DM54/
74ALS244A
• Low level drive current: 54ALS=8 mAo 74ALS=16 rnA

Connection Diagram

Logic Diagram

Dual-In-Une Package

8 lVl
> _ - t _'-..

~_-t_'_6 lV2
14

~--t--1Y3

> __....;1.;.2 1Y4

>_--t_;,.9 2Vl
TlIF/6263-1

Top View
Order Number DM54ALS1244AJ, DM74ALS1244AWM or
DM74ALS1244AN
See NS Package Number J20A, M20B or N20A

Function Table
Enable
Input
1G or 2G

Data
Buffer
Outputs

L

Active
TRI-STATE

H

> _ - t _ . -7. 2Y2

>--t--2Y3

> ____
3 2V4
TlIF/6263-2

2-311

..:=....

Ii)
N

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarantB8d. The device should not be operated at th8Sslimits. The
parametric valuss defined in the "Electrical Characteristics"
table are not guaranf88c/ at the absolute maximum ratings.
The "Recommended Operating Conditions" tabl8 will defins
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and speclfleetloM.
Supply Voltage, Vee
Input Voltage
Voltage Applied to Disabled Output

7V
7V
5.5V

Operating Free Air Temperature Range
DM54AlS
- 55·C to + 125·C
DM74AlS
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

DM74ALS1244A

DM54ALS1244A

Parameter

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High level Input Voltage

Vil

low level Input Voltage

0.7

0.8

V

10H

High level Output Current

-12

-15

mA

10l

low level Output Cumint

8

16

mA

TA

Operating Free·Air Temperature

70

·c

2

2

-55

V

0

125

Electrical Characteristics over recommended operating free·air temperature (unless otherwise specified)
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High level Output
Voltage

Conditions

= 4.5V,11 = -18 mA
Vee = 4.5Vt05.5V 10H = -0.4mA
Vee = 4.5V
10H = -3mA
10H = Max
Vee = 4.5V
10l = 54AlS (Max)
10L = 74AlS (Max)
Vee = 5.5V, VI = 7V
(VI = 5.5V for A or B Ports)
Vee = 5.5V, VI = 2.7V

DM54ALS1244A

DM74ALS1244A

Min

Min

Typ

Max

Typ

-1.5

Vee

-1.5

V

Vee- 2

Vee -2

V

2.4

2.4

V

2

2

V

VOL

low level Output
Voltage

II

Input Current at Max
Input Voltage

IIH

High level Input
Current

III

low level Input
Current

Vee

= 5.5V, Vil = O.4V

10

Output Drive
Current

Vee

= 5.5V, Vo = 2.25V

10ZH

High level TRI·STATE Vee
Output Current

= 5.5V, Vo = 2.7V

10Zl

low leveITRI-STATE
Output Current

Vee

= 5.5V, Vo = 0.4V

lee

Supply Current

Vee = 5.5V
Outputs High

6

15

6

Outputs low

10

20

Outputs TRI·STATE

11

25

0.25

0.4

0.25

0.4

V

-

-

0.35

0.5

V

0.1

0.1

rnA

20

20

p.A

-0.1

-0.1

mA

-112

mA

20

20

p.A

-20

-20

p.A

11

mA

10

17

mA

11

20

mA

-30

2·312

Units

Max

-112

-30

Switching Characteristics over recommended operating free-air temperature range
Vee
Symbol

Parameter

From
(Input)

=
R1

To
(Output)

4_5V to 5_5V, CL = 50 pF,
= 500n, R2 = 500n,
TA = Min to Max

54ALS1244A

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tPZH

Output Enable Time
to High Level Output

tpZL

Output Enable Time
to Low Level Output

tpHZ

Output Disable Time
from High Level Output

tpLZ

A

G

G

Units

74ALS1244A

Min

Max

Min

Max

3

21

3

14

ns

3

16

3

14

ns

6

28

6

22

ns

6

26

6

22

ns

2

15

2

10

ns

3

25

3

13

ns

y

y

y

Output Disable Time
from Low Level Output

2-313

Natlonal

. Semiconductor
~
Corporation

DM54ALS1245A/DM74ALS1245A
TRI-STATE@ Bus Transceivers
General Description

Features

This advanced low power Schottky device contains 8 pairs
of TRI-STATE logic elements configured as octal bus transceivers. This circuit is designed for use in memory, microprocessor systems and in asynchronous bidirectional data
buses. Two way communication between buses is controlled by the (DIR) input. Data either transmits from the A
bus to the B bus or from the B bus to the A bus. Both the
driver. and receiver outputs can be disabled via the (G) enable input which causes outputs to enter the high impedance mode, so that the buses are effectively isolated. The
TRI-STATE circuitry also contains a protection feature that
prevents the buffer from glitching the bus during power-up
or power-down.

• Low power version of ALS245A
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Low output impedance to drive terminated transmission
lines to 1330
• Switching response specified into 5000/50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Une Package
~

jiG

i
j'9

~

~
u "
~
M
1,8 T17
T,.
1,5 1,4
1,3

~ ~

~

~

~

~

~

~
"
112

1"

~

~
I'

110
GND
TL/F/8438-1

Order Number DM54ALS1245AJ, DM74ALS1245AWM or DM74ALS1245AN
See NS Package Number J20A, M20B or N.20A

Function Table
Controllnputa

L

I

Operation

G

DIR

L
L
H

H
X

L

B Data to A Bus
A Data to B Bus
Hi-Z

= Low Logie Level, H = High Logic Level

X = Either Low or High Logic Level
HI-Z

= High Impedance (off) State

I.

2-314

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National semiconductor Sales Office/
Distributors for availability and speclflcetlons_
Supply Voltage, Vee
Input Voltage
Control Inputs
I/O Ports

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V

7V
5.5V

Operating Free Air Temperature Range
DM54AlS
-55'Cto + 125'C
DM74AlS
O"Cto +70"C
Storage Temperature Range
-65"Cto + 150"C

Recommended Operating Conditions
Symbol

DM74ALS1245A

DM54ALS1245A

Parsmeter

Units

Min

Typ

Max

Min

Typ

Max

4.5

5

5.5

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High level Input Voltage

VIL

low level Input Voltage

0.7

O.B

V

10H

High level Output Current

-12

-15

mA

16

mA

70

·c

2

10L

low level Output Current

TA

Operating Free Air Temperature Range

2

B
-55

0

125

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High level
Output Voltage

VOL

low level
Output Voltage

DM54ALS1245A

Conditions

= 4.5V, liN = -18 mA
= 4.5V, 10H = -3 mA
Vee = 4.5V,IOH = Max
10H = -0.4mA,
VOL = 4.5V to 5.5V
Vee = 4.5V
10L = BmA
10L = 16mA
Vee = 5.5V, VIN = 7V
MN = 5.5V for A or B Ports)
Vee = 5.5V, VIN = 2.7V
Vee

II
IIH

High level
Input Current

IlL

low level
Input Current

10

Output Drive Current Vee

lee

Supply Current

Vee

Vee

DM74ALS1245A

Units

Typ

3.2

2.4

3.2

V

2.3

2

2.3

V

Typ

2.4
2

Max
-1.5

Max
-1.5

Vee -2

Vee - 2
0.25

= 5.5V, VIN = 0.4V
= 5.5V, Vo = 2.25V
= 5.5V

= 5V, TA = 25·C.
Min

Min
Vee

Input Current at
Max Input Voltage

V

-30

V

V
0.25

0.4

V

0.35

0.5

V

0.1

0.1

mA

20

20

p.A

-0.1

-0.1

mA

-112

mA

0.4

-112

-30

Outputs High

21

33

21

30

mA

Outputs low

23

36

23

33

mA

TRI-STATE

25

40

25

36

mA

2-315

Switching Characteristics over recommended operating free air temperature" range (Notes 1 and 2)
Symbol

Circuit
Configuration

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tPZL

Output Enable Time
to Low Level Output

tPZH

Output Enable Time
to High Level Output

tpLZ

Output Disable Time
from Low Level Output

tpHZ

Output Disable Time
from High Level Output

IN~our

"~

DM54ALS1245A

DM74ALS1245A

Min

Max

Min

Max

2

19

2

13

ns

2

15

2

13

ns

8

29

8

25

ns

8

30

8

25

ns

3

30

3

18

ns

2

14

2

12

ns

A OR B

our

Note 1: See Section 1 for test waveforms and output load.
Note 2: Switching characteristic condHions are Vee

Units

= 4.5V to 5.5V, RL = 500n, CL = 50 pF.

I

2-316

ri1I

National
Semiconductor
Corporation

PRELIMINARY

DM54ALS1645A/DM74ALS1645A
Octal TRI-STATE® Bus Transceivers
General Description

Features

This device contains eight pairs of TRI-STATE logic elements configured as octal bus transceivers. This device is
designed for use in memory, microprocessor systems and in
asynchronous bidirectional data buses. Two way communication between buses is controlled by the direction (DIR)
input. Data either transmits from the A bus to the B bus or
from the B bus to the A bus. Both the driver and receiver
outputs can be disabled by the enable (G) input which causes outputs to enter the high impedance mode, so that the
buses are effectively isolated.

• Low power version of the ALS645A
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• PNP input design reduces input loading
• Low output impedance to drive terminated transmission
lines to 1330
• Switching specifications guaranteed over the full temperature and Vee range

Connection Diagram

TL/F/9164-1

Order Number DM54ALS1645AJ, DM74ALS1645AWM or DM74ALS1645AN
See NS Package Number J20A, M20A or N20A

Function Table
Control
Inputs

Operation

G

DIR

L

L

B Data to A Bus

L

H

A Data to B Bus

H

X

Hi-Z

= Low Logic Level
H = High Logic Level
X = Don~ Care (Either Low or High Logic Level)
HI-Z = High Impedance
L

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

2-317

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot ~, guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Mllitary/Aeroapace apecHied devices are required,
contact the National Semiconductor sales Office/
Dlstributora for availability and apeclflcaUona.
Supply Voltage
7V
Input Voltage
Control Inputs
110 Ports

7V
5.5V

Operating Free-Air Temperature Range
DM54ALS
-55·Cto + 125"C
DM74ALS
O"C to + 70"C
Storage Temperature Range
-65·Cto + 150"C
I

Recommended Operating Conditions
Symbol

DM74ALS1645A

DM54ALS1645A

Parameter
Min

Nom

4.5

5

Max
-5.5

Units

Min

Nom

Max

4.5

5

5.5

V

VCC

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.7

0.8

V

10H

High Level Outpu1 Current

-12

-15

mA

10L

Low Level Output Current

8

16

mA

TA

Free Air Operating Temperature

70

·C

2

V

2

-55

125

0

Electrical Characteristics over recommended free air temperature range
Symbol

Parameter

Test Condltlona

Input Clamp Voltage

Vee = Min, 11= -18mA

VOH

High Level Output
Voltage

Vee = 4.5V to 5.5V 10H = -0.4mA
10H = -3mA
10H = Max

VOL

II

Low Level Output
Voltage

Vee = Min

Input Current at Max
Input Voltage

Vee = Max

DM74ALS1645A

Min

Min

Typ Max

Vee- 2
2.4

-1.5

3.2

2.4

=

=

V

0.25

0.4

0.25

0.4

0.35

0.5

110 Ports, VI = 5.5V

100

100

Control Inputs, VI = 7V

100

100

IIH

High Levellnpu1 Current Vee

Low Level Input Current Vee = Max, VI = 0.4V (Note 1)

10

Output Drive Current

ICC

Supply Current

Max, VI

3.2

2

10L = 16mA

IlL

2.7V (Note 1)

Vee = Max, Vo = 2.25V

2·318

25

V

poA

20

20

-100

-100

poA

-112

mA

36

mA

-112

-30

Vee = Max
Note 1: For 1/0 ports. the parameters IIH and IlL include the off·state currents. (l0ZH. loztJ

V

Vee - 2

2

10L = 8mA

Unlta

Typ Max

-1.5

VIC

Vee = Min

DM54ALS1645A

40

-30
25

poA

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

Conditions

DM54ALS1645A

DM74ALS1645A

Units

Min

Max

Min

Max

AorBto
BorA

2

15

2

13

ns

AorBto
BorA

2

15

2

13

ns

8

28

8

25

ns

8

28

8

25

ns

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tPZH

Output Enable Time
to High Level Output

Gto
AorB

tPZL

Output Enable Time
to Low Level Output

AorB

Output Disable Time
from High Level Output

Gto
AorB

2

14

2

12

ns

Gto
AorB

3

22

3

18

ns

tpHZ

Vee = 4.5Vt05.5V,
Rl = 5000,
R2 = 5000,
CL=50pF

From (Input)
To (Output)

Output Disable Time
from Low Level Output
Note 1: See Section 1 lor 19s1 waveforms and ou1pu1load.

tpLZ

~to

2-319

.. ,--------------------------------------------------------------------------------,
~

~
~

_

.

National

.

PRELIMINARY

Semiconductor
. Corporation

"'"

..
:::::E

o DM54ALS2541/DM74ALS2541
.....
Octal Buffers and MOS Line Drivers with
~ TRI-STATE® Outputs
~

~

In

~

General Description

Features

These octal buffers and line drivers are deSigned to have
the performance of the •ALS240 series and. at the same
time. offer a pinout with inputs and outputs on opposite
sides of the package. This arrangement of input! outputs
enhances printed circuit board layout. These drivers are designed to drive the capacitive inputs of MOS devices. The
outputs have 250 resistors in series. thus external components are not required. The TRI-STATE control gate is a 2input NOR such that if either <31 or <32 is high. all eight
outputs are in the high impedance state.

• Advanced oxide-isolated ion-implanted Schottky TTL
process
• Switching performance is guaranteed over full temperature and Vee supply range
• Data Flow-Thru Pinout (All inputs on opposite side from
outputs)
• P-N-P Inputs reduce DC loading
• Outputs have 250 series resistors thus no external resistors are required

Connection Diagram
Y1

Y2

18

Y3

17

Y5

Y4

15

16

Y6
14

Y7

13

Y8

12

11

1

G1

TL/F/9165-1

Order Number DM54ALS2541J or DM74ALS2541WM, N
See NS Package Number J20A, M20B or N20A

Function Table
Input

Output

G1

G2

A

Y

H

X

X

H
L
L

X
X

Hi-Z
Hi-Z
L
H

L
L

L
H

H

~

High Logic Level, L

X

~

Don't Care (Either high or low logic level)

H~Z ~

~

Low logic Level

High Impedance (Off) State

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without notice.

2-320

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Voltage Applied to a
Disabled TRI·STATE Output
5.5V
Operating Free-Air Temperature Range
DM54ALS
- 55'C to + 125'C
DM74ALS
O"Cto +70'C
Storage Temperature Range
-65'Cto + 150"C

Recommended Operating Conditions
Symbol

DM54ALS2541

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

10H

DM74ALS2541

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2
0.7

0.8

V

High Level Output Current

-0.4

-0.4

mA

10l

Low Level Output Current

12

12

mA

TA

Operating Free Air
Temperature Range

70

'C

-55

125

0

Electrical Characteristics over recommended free air temperature range
Symbol

Parameter

Test Conditions

VIK

Input Clamp Voltage

Vee = Min,ll = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V to 5.5V,
10H = -0.4mA

VOL

Low Level Output
Voltage

Vee = Min

10ZH

High Level TRI-STATE
Output Current

Vee = Max, Vo = 2.7V

10Zl

Low Level TRI-STATE
Output Current

Vee = Max, Vo = 0.4V

10H

High Level Output
Current

Vee = Min, Vo = 2V

10l

Low Level Output
Current

Vee = Min, Vo = 2V

II

Input Current @
Maximum Input Voltage

Vee = Max, VI = 7V

IIH

High Level Input
Current

Vee = Max, VI = 2.7V

III

Low Level Input
Current

Vee = Max, VI = 0.4V

10

Output Drive Current

Vee = Max, Vo = 2.25V

Icc

Supply Current

Vee = Max

Min

Typ

Max

Units

-1.2

V

Vee -2
mA
IOl=1mA

0.15

0.5

10l = 12mA

0.35

0.8
20

/LA

-20

/LA

-15

mA

30

mA

-15

100

/LA

20

/LA

-100

/LA

-70

mA

Outputs High

6

14

Outputs Low

15

25

13.5

22

Outputs Disabled

2·321

mA

fI

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

Conditions

From (Input)
To (Output)

DM74ALS2541

DM54ALS2541

Units

Min

Max

Min

Max

AtoY

2

17

2

15

ns

AtoY

2

14

2

12

ns

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tPZH

Output Enable Time
to High Level Output

"GtoY

5

18

5

15

ns

tPZL

Output Enable Time
to Low Level Output

"GtoY

8

24

8

20

ns

tpHZ

Output Disable Time
from High Level Output

"GtoY

1

12

1

10

ns

tpLZ

Output Disable Time
from Low Level Output

"GtoY

2

14

2

12

ns

Vee = 4.5V to 5.5V,
R1 = R2 = 5000
(Note 1)
CL = 50pF

Note 1: See Section 1 for output load and test waveforms.

\

2-322

_

National

PRELIMINARY

Semiconductor
Corporation

DM54ALS2645A/DM74ALS2645A
Octal TRI-STATE® Transceivers
General Description

Features

This octal bus transceiver is designed for asynchronous two
way communication between data buses. Data is transmitted either from the A bus to the B bus or from the B bus to
the A bus depending on the logic level of the direction control (DIA) input. The device can be disabled via the enable
input (G) which causes outputs to enter the high impedance
mode so the buses are effectively isolated.

• Advanced oxide-isolated, ion implanted Schottky TTL
process
• Switching specification guaranteed over the full temperature and Vee range
• PNP inputs to reduce input loading
• I/O ports have 250 series resistors so no external resistors are required

Connection Diagram

TL/F/9166-1

Order Number DM54ALS2645AJ, DM74ALS2645AWM or DM74ALS2645AN
See NS Package Number J20A, M20B or N20A

Function Table
Control
Inputs

L

Operation

G

DIA

L
L
H

L
H

X

B Data to A Bus
A Data to B Bus
High Impedance

= Low Logic Level. H = High Logic Level

X = Don't Cere (Either Low or High Logic Level)

fI
This document contains information on a product under development NSC reserves the right to change or discontinue this product without notice.

2-323

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Control Inputs
1/0 Ports

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V
5.5V

Storage Temperature Range

- 65'C to

+ 150'C

ESD rating is to be determined.

Recommended Operating Conditions
Symbol

DM54ALS2645A

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

DM74ALS2645A

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

VIL

Low Level Input Voltage

TA

Free Air Operating Temperature Range

Units

Min

0.7
-55

V
V

2
125

0

0.8

V

70

'C

Electrical Characteristics over recommended free air temperature range
Symbol

Parameter

Test Conditions

DM54ALS2645A
Min

Typ

Max

Input Clamp Voltage

VOH

High Level Output Voltage Vee = 4.5V to 5.5V, 10H = -2 mA

VOL

Low Level Output
Voltage

Vee = Min

Input Current at Maximum
Input Voltage

Vee = Max 1/0 Ports, VI = 5.5V

High Level Input Current
(Note 1)

Vee = Max Control Inputs
VI = 2.7V
1/0 Ports

Low Level Input Current
(Note 1)

Vee = Max Control Inputs
VI = O.4V
1/0 Ports

10

Output Drive Current

Vee = Max, Vo = 2.25V

Icc

Supply Current

Vee = Max Outputs High

58

95

Outputs Low

95
73

IIH

IlL

Typ

-1.2

VIK

II

DM74ALS2645A
Min

Vee = Min, 11= -18 mA
Vee- 2

-1.2

0.15

0.4

0.15

0.4

10L = 12mA

0.35

0.7

0.35

0.7

-50

Outputs Disabled
Note 1: For 1/0 ports, IIH and III parameters include the TRI-STATE output currents (loZl and 10ZH).

2·324

100

100

100

100

20

20

70

70

-500

-500

-750

-750

-150

V
V

Vee - 2

IOL=1mA

Control Inputs, VI = 7V

Units

Max

-50

-150
58

95

155

95

155

119

73

119

V

/Jo A

/Jo A

/Jo A
mA

mA

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

Conditions

From (Input)
To (Output)

DM54ALS2645A

DM74ALS2645A

Units

Min

Max

Min

Max

AorBto
BorA

1

12

1

10

ns

AorBto
BorA

1

11

1

9.5

ns

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay TIme
High to Low Level Output

tpZH

Output Enable TIme
to High Level Output

Gto
AorB

1

13

1

11.5

ns

tPZL

Output Enable Time
to Low Level Output

Gto
AorB

1

13

1

10.5

ns

tpHZ

Output Disable Time
from High Level Output

Gto
AorB

1

9

1

8

ns

tpLZ

Output DisableTime
from Low Level Output

Gto
AorB

1

13

1

12

ns

Vee = 4.5V to 5.5V
R1 = R2 = 500n,
CL = 50pF
(Note 1)

Note 1: See Section 1 for lest waveforms and output load.

2·325

..

U) r---------------------------------------------------------------------------~

C"III

Semiconductor
~ ~ Corporation
~
National

PRELIMINARY

~ DM54ALS5245/DM74AI-S5245
~
Octal TRI-STATE® Transceivers

..
~

cc General Description

:s
~

Features

This octal bus transceiver is designed for asynchronous
two-way communication between data buses. The inputs include hystersis which provides improved noise rejection.
Data is transmitted either from the A bus to the B bus or
from the B bus to the A bus depending on the logic level of
the direction control (OIR) input. The device can be disabled
via the enable input (~) which causes the outputs. to enter
the high impedance mode so the buses are effectively isolated.

• Advanced oxide-isolated, ion implanted Schottky TIL
process
• Switching specification guaranteed over the full temperature and Vee range
• PNP inputs to reduce input loading
• Input Hystersis to improve noise margin

Connection Diagram

TUF/9175-1

Order Number DM54ALS5245J, DM74ALS5245WM or DM74ALS5245N
See NS Packllge Number J20A, M20B or N20A
.

Function Table
Control
Inp!,lta

G

L

Operation

DIR

L

L

B Data to A Bus

L

H

A Data to B Bus

H

X

High Impedance

= Low Logic Level. H = High Logic Level

X = Don't Care (E!lher Low or High Logic Level)

This document contains information on a product under development. NSC reserves the right to change or discontinue this product without no1lce.

2-326

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales OffIce/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Control Inputs
1/0 Ports

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operatiOn.

7V
5.5V

Operating Free-Air Temperature Range
DM54ALS
- 55°C to + 125°C
DM74ALS
O"Cto +70"C
Storage Temperature Range
- 65°C to + 150"C

Recommended Operating Conditions
Symbol

DM54ALS5245

Parameter

Vcc

Supply Voltage

VIH

High Level Input Voltage

DM74ALS5245

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

2

V
V

2

VIL

Low Level Input Voltage

0.7

0.8

V

10H

High Level Output Current

-12

-15

mA

10L

Low Level Output Current

12

24

mA

TA

Free Air Operating Temperature
Range

70

°C

-55

125

0

Electrical Characteristics over recommended free air temperature range
Symbol
VIC

Input Clamp Voltage

Hystersis (VT+ - VT-) Vee = Min

VOH

High Level Output
Voltage

Low Level Output
Voltage

Typ

0.2

0.4

Vee = Min

Max

DM74ALS5245

Vee - 2

10H = 3mA

2.4

10H = Max

2

Typ

Max

0.2

0.4

V

3.2

V

-1.5

V

Vee - 2
2.4

3.2

2
0.25

10L = 12mA

Units

Min

-1.5

Vcc = 4.5V to 5.5V 10H = -0.4mA
Vcc = Min

0.4

10L = 24mA

Input Current at
Vee = Max
Maximum Input Voltage

II

Min
Vee = Min, 11= -18mA

HyS

VOL

DM54ALS5245

Test Conditions

Parameter

0.25

0.4

0.35

0.5

1/0 Ports, VI = 5.5V

100

100

Control Inputs, VI = 7V

100

100

V

/LA

High Level Input Current Vee = Max, VI = 2.7V (Note 1)

20

20

IlL

Low Level Input Current Vcc = Max, VI = 0.4V (Note 1)

-100

-100

/LA

10

Output Drive Current

Vcc = Max, Vo = 2.25V

-112

mA

Icc

Supply Current

Vcc = Max

IIH

-30

-112

-30

Outputs High

30

48

30

45

Outputs Low

36

60

36

55

Outputs Disabled

38

63

38

58

Not. 1: For 1/0 ports. IIH and IlL parameters include the TAl-STATE output currents (loZL and 10ZH).

2·327

/LA

mA

fI
)

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

Condmons
Vee = 4.5V to 5.5V,
R1 = R2 .., SOOO,
CL=50pF
(Note 1)

From (Input)
To (Output)

DM54ALS5245

DM74ALS5245

Min

Max

Min

Max

AorBto
BorA

3

15

3

10

ns

AorBto
BorA

3

13

3

10

ns

Units

trui

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpZH

Output Enable Time
to High Level Output

"G"to
AorB

5

25

5

20

ns

tpZL

Output Enable Time
to Low Level Output

"G"to
AorB

5

25

5

20

ns

tpHZ

Output Disable Time
from High Level Output

"G"to
AorB

2

12

2

10

ns

tpLZ

Output DisableTirne
from Low Level Output

"G"to
AorB

4

18

4

15

ns

Nota 1: See Section 1 for test waveforms and output load.

2·328

.-------------------------------------------------------------------,0
_

National
Semiconductor
CorporaHon

PRELIMINARY

a:

E

i

~
.....
o
a:
.....

DM54ALS5620/DM74ALS5620
Octal TRI-STATE® Transceivers

:=

General Description

Features

This octal bus transceiver is designed to have the performance of the' ALS620 device with the addition of hystersis on
the inputs. The input hystersis provides improved noise margin. Data is transmitted either from the A bus to the B bus or
the B bus to the A bus depending on the logic level of the
directon control input (OIR). The device can be disabled via
the enable input (G) which causes the outputs to enter the
high impedance mode so the busses are effectively isolated.

• Advanced oxide-isolated, ion implanted Schottky TTL
process
• Switching specification guaranteed over the full temperature and Vee range
• PNP inputs to reduce input loading
• Hystersis on the inputs to improve noise rejection

i

~

Connection Diagram
DIR- 1

20rVCC

Al- 2

19Hi

A2- 3

18rBI
17 -B2

A3- 4
A4- 5

16 -B3

AS- 6

15-B4

A6- 7

14 -B5

A7- 8

13-B6

A8- 9

12-B7

GND- 10

"-B8
TUF/9166-1

Order Number DM54ALS5620J or DM74ALS5620WM, N
See NS Package Number J20A, M20B or N20A

Function Table
Control
Inputs
GBA

Operation

GAB

L

X

B Data to A Bus

X

H

A Data to B Bus

H

L

High Impedance

L = Low Logic Level. H = High logic Level
X = Don't Care (Either Low or High Logie Level)

fI
This document contains Information on a product under development NSC reserves the right to change or discontinue this product without noUce.

2-329

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Control Inputs
I/O Ports

parametric values defined in the "Electrical Characteristics"
table ara not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device oparation.

7V
5.5V

Operating Free Air Temperature Range
DM54ALS
- 55DC to + 125DC
DM74ALS
O"Cto +70"C
Storage Temperature Range
-65DC to + 150"C

Recommended Operating Conditions
Symbol
Vee

Supply Voltage

DM74ALS5620

DM54ALS5620

Parameter

Units

Min

Nom

Max

Min

Nom

Max

4.5

5

5.5

4.5

5

5.5

V

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.8

0.8

V

IOH

High Level Output Current

-12

-15

mA

IOl

Low Level Output Current

12

24

mA

TA

Operating Free Air
Temperature Range

70

DC

2

V

2

-55

125

0

Electrical Characteristics over recommended free air temperature range
Symbol

Parameter

DM54ALS5620

Test Conditions

Min
VIC

Input Clamp Voltage

Vcc

HYS

Input Hystersis
(VT+ - VT-)

Vee

VOH

High Level Output
Voltage

Vee

Val

II

=
=

=
Vcc =

Low Level Output
Voltage

Vee

Input Current @ Max
Input Voltage

Vcc

=
=

=
=
Vcc =
Vee =

Min, II

=

= -0.4mA
10H = -3mA
IOH = Max
10l = 12mA
10l = 24mA
I/O Ports, VI = 5.5V
Control Inputs, VI = 7V

4.5V to 5.5V IOH

Min

Max

DM54ALS5620
Min

= 2.7V (Note 1)
= 0.4V (Note 1)
Max, Vo = 2.25V

-1.5

0.2

0.2

Vee -2

Vee -2

2.4

3.2

2.4

2

Units

Typ Max

-1.5

-18 mA

Min

Min

Typ Max

V
V

3.2

V

2
0.25

0.4

0.25

0.4

0.35

0.5

100

100

100

100

V

/J- A

IIH

High Level Input Current Vee

Max, VI

20

20

III

Low Level Input Current Vee

Max, VI

-100

-100

IJ.A

10

Output Drive Current

-112

mA

Icc

Supply Current

Note

1: For 1/0 ports. IIH and

Max

-30

-112

-30

Outputs High

24

39

24

34

Outputs Low

25

49

31

44

27

52

33

47

Outputs Disabled
IlL parameters Include the TRI-STATE output currents (IOZL and lozHl.

2·330

/J-A

mA

Switching Characteristics over recommended operating free air temperature range
Symbol

Parameter

Conditions
Vee = 4.5V to 5.5V,
R1 = R2 = 5000,
CL = 50pF
(Note 1)

From (Input)
To (Output)

DM54ALS5620

DM74ALS5620

Units

Min

Max

Min

Max

AorBto
BorA

2

12

2

10

ns

AorBto
BorA

2

12

2

10

ns

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tPZH

Output Enable Time
to High Level Output

ClBAor GBA
toAorB

3

23

3

17

ns

tPZL

Output Enable Time
to Low Level Output

ClBAor GBA
toAorB

5

31

4

25

ns

tpHZ

Output Disable Time
from High Level Output

ClBAor GBA
toAorB

2

14

3

12

ns

tpLZ

Output DisableTime
from Low Level Output

ClBAorGBA
toAor B

3

22

4

18

ns

Note 1: See Section

1 for test waveforms and output load.

PI
2·331

Section 3
Advanced Schottky

II

Section 3 Contents
DM74ASOO Quad 2-lnput NAND Gates ..................................... , ..........
DM74AS02 Quad 2-lnput NOR Gates... ... ..... .. ... .... .. ................ ... .. ......
DM74AS04 Hex Inverters ................. ;-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74AS08 Quad 2-lnput AND Gates. .. ........ ........... ...... ........ .............
DM74AS10 Triple 3-lnput NAND Gates... ... .. ........ .. .............. ... .... .. .. ... ..
DM74AS11 Triple 3-lnput AND Gates.. ..... ..... ....... .......... ....... . ..... ..... ..
DM74AS20 Dual4-lnput NAND Gates.................................................
DM74AS21 DuaI4-lnputANDGates...... .......... ............ .......... ............
DM74AS27 Triple 3-lnput NOR Gates.... ... ............ .. .. .......... ... ...... .. ... ..
DM74AS30 8-lnput NAND Gates.....................................................
DM74AS32 Quad 2-lnput OR Gates ..................................................
DM74AS34 Hex Non-Inverter......... .......... ... .... .... .... .. ... .... . ... .. ... ....
DM74AS74 Dual 0 Positive-Edge-Triggered Flip-Flops with Preset and Clear...............
DM74AS86 Quad 2-lnput Exclusive-OR Gates ...................................... , ..
OM 74AS 109 Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear. ..... ......
DM74AS136 Quad 2-lnput Exclusive-OR Gates with Open-Collector Outputs.... ... ....... .
DM74AS157 Quad 1 of 2 Line Data Selectors/Multiplexers........... .. .. . ... ... .. ......
DM74AS158 Quad 1 of 2 Line Inverting Data Selectors/Multiplexers ................... , . .
DM74AS160 Synchronous 4-Bit Decade Counter with Asynchronous Clear ................
DM74AS161 Synchronous 4-Bit Binary Counter with Asynchronous Clear.... ......... .....
DM74AS162 Synchronous 4-Bit Decade Counter with Synchronous Clear .................
DM74AS163 Synchronous 4-Bit Binary Counter with Synchronous Clear...................
DM74AS168A Synchronous 4-Bit Up/Down Decade Counter ........ , ................ ,. .
DM74AS169A Synchronous 4-Bit Up/Down Binary Counter....... ... .. .... . .... .. .. .....
DM74AS 174 Hex 0 Flip-Flops with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM7 4AS175A Quad 0 Flip-Flops with Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74AS181B Arithmetic Logic Unit/Function Generators...............................
DM74AS182 Look-Ahead Carry Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74AS230 Octal TRI-STATE Bus Drivers/Receivers with
True and Inverting Outputs..... ......... .. ... ... ................. .. .... ... .. .. ... .
DM74AS231 Octal TRI-STATE Inverting Bus Drivers/Receivers..................... ... ..
DM74AS240 Octal TRI-STATE Inverting Buffers/Line Drivers/Line Receivers. ... ... .. .....
DM74AS241 Octal TRI-STATE Buffers/Line Drivers/Line Receivers.... ..... .... ..... .. ..
DM74AS242 Octal TRI-STATE Inverting Bus Transceivers.... .. .. ..... ..... .... ..... .. ..
DM74AS243 Octal TRI-STATE Bus Transceivers.......................................
DM74AS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers.. .. ..... .... ..... .. ..
DM74AS245 Octal TRI-STATE Bus Transceivers.. ... ................. .... .. ...... .....
DM74AS257 Quad TRI-STATE 1 of 2 Line Data Selectors/Multiplexers.. ..... .... ..... .. ..
DM74AS258 Quad TRI-STATE 1 of 2 Line Inverting Data Selectors/Multiplexers ........ , ..
DM74AS264 Look Ahead Carry Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM74AS280 9-Bit Parity Generator/Checker. ..... . .. . .. .. .. .. .. .......... .. ... ....... .
DM74AS282 Look Ahead Carry Generator with Selectable Carry Inputs ...................
DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port. . ...... ... .. ..
DM74AS373 Octal 0-Type Transparent Latches with TRI-STATE Outputs ............. :...
DM74AS374 Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs. . ... ........
DM74AS533 Octal D-Type Transparent Latches with TRI-STATE Outputs... . ........... ..

3-2

3-4
3-6
3-8
3-10
3-12
3-14
3-16
3-18
3-20
3-22
3-24
3-26
3-28
3-31
3-33
3-36
3-38
3-38
3-42
3-42
3-42
3-42
3-49
3-49
3-54
3-57
3-60
3-69
3-73
3-73
3-76
3-76
3-76
3-76
3-76
3-82
3-84
3-84
3-88
3-93
3-97
3-102
3-107
3-110
3-114

Section 3 Contents (Continued)
DM74AS534 Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs. . . . . . . . . . . ..
DM74AS573 Octal D-Type Transparent Latches with TRI-STATE Outputs .................
DM74AS57 4 Octal D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs. . . . . . . . . . . ..
DM74AS575 Octal D-Type Edge-Triggered Flip-Flops with Synchronous Clear .............
DM74AS576 Octal D-Type Edge-Triggered Flip-Flops with Inverted Outputs. . . . . . . . . . . . . . ..
DM74AS577 Octal D-Type Edge-Triggered Flip-Flops
with Inverted Outputs and Synchronous Preset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74AS580 Octal D-Type Transparent Latches with TRI-STATE Outputs. .. .. .. ...... .. ..
DM74AS620 Octal TRI-STATE Inverting Bus Transceiver... .. ... ... .. ... ...... ...... ....
DM74AS640 TRI-STATE Octal Bus Transceivers .......................................
DM74AS645 TRI-STATE Octal Bus Transceivers .......................................
DM74AS646 OctaITRI-STATE Bus Transceivers/Registers .............................
DM74AS648 Octal TRI-STATE Inverting Bus Transceivers/Registers... .. ...... ...... ....
DM74AS651 Octal TRI-STATE Inverting Bus Transceivers/Registers .....................
DM74AS652 Octal TRI-STATE Bus Transceivers/Registers .............................
DM74AS804B Hex 2-lnput NAND Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74AS805B Hex 2-lnput NOR Driver. ...... .. ......... .. ... ... ... .. .. ... ... .. .. .. . ..
DM74AS808B Hex 2-lnput AND Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74AS810 Quad 2-lnput Exclusive NOR Gates .......................................
DM74AS811 Quad 2-lnput Exclusive NOR Gates with Open Collector Outputs .............
DM74AS832B Hex 2-lnput OR Driver .................................................
DM74AS873 Dual 4-Bit D-Type Transparent Latches with TRI-STATE Outputs .............
DM74AS874 Dual4-Bit D-Type Edge-Triggered Flip-Flops.. ... .... .. ... .. .. .. ........ ...
DM74AS876 Dual4-Bit D-Type Edge-Triggered Flip-Flops with TRI-STATE Outputs. . . . . . . ..
DM74AS878 Dual 4-Bit D-Type Edge-Triggered Flip-Flops with Synchronous Clear. . . . . . . . ..
DM74AS879 Dual4-Bit D-Type Edge-Triggered
Flip-Flops with TRI-STATE Outputs and Synchronous Clear. . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74AS880 Dual 4-Bit D-Type Transparent Latches with TRI-STATE Outputs .............
DM74AS881 B 4-Bit Arithmetic Logic Unit/Function Generator. . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74AS1000A Quad 2-lnput NAND Drivers ...........................................
DM74AS1004A Hex Inverting Drivers. .. .... .... ....... .. ... .... .. ... .. .... .. ...... . ..
DM74AS1008A Quad 2-lnput AND Drivers. .. .. .. ...... . ... .. .... .. ... .. .. .. .. .. .. ... ..
DM74AS1032A Quad 2-lnput OR Drivers.... .......... . .. ... ... . .. ... .. .. .. .. .. .... . ..
DM74AS1034A Hex Non-Inverting Drivers .............................................
DM74AS1 036A Quad 2-lnput NOR Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM74AS1804 Hex 2-lnput NAND Drivers ..............................................
DM74AS1805 Hex 2-lnput NOR Drivers ...............................................
DM74AS1808 Hex 2-lnput AND Drivers. ...... ...... .. . ... .. . ... .. . .. ..... .......... ..
DM74AS1832 Hex 2-lnput OR Drivers... ....... ........ .. . .. . ... .. . .. .. .... ...... ... ..
DM74AS2620 Octal Bus Transceivers/MOS Drivers..... .. ... .... .. . .. ............... ..
DM74AS2645 Octal TRI-STATE Bus Transceivers/MOS Drivers .........................

3-3

3-117
3-120
3-124
3-127
3-130
3-133
3-136
3-139
3-142
3-145
3-148
3-148
3-153
3-153
3-159
3-161
3-163
3-165
3-168
3-170
3-172
3-176
3-180
3-183
3-186
3-189
3-193
3-205
3-207
3-209
3-211
3-213
3-215
3-217
3-219
3-221
3-223
3-225
3-228

_

National

. Semiconductor
Corporation

DM74ASOO Quad 2-lnput NAND Gates
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TIL counterpart
• Improved AC performance over Schottky, low power
Schottky, and advanded low power Schottky counter-

General Description
This device contains four independent gates, each of which
performs the logic NAND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

parts

Connection Diagram
Dual·ln-Une Package
Vee

4B

4A

4Y

38

3A

3Y

8

1A

18

1Y

2A

2B

2Y

GND
Tl/F/6105-1

Order Number DM74ASOOM or DM74ASOON
See NS Package Number M14A or N14A

Function Table
V=AB
Inputs

H

L

Output

A

B

V

L
L

L

H

H
H

L

H
H
H

H

L

= High Logic Level
= Low logic Level

3-4

Absolute Maximum Ratings
If MIlitary/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V

Input Voltage

7V

Operating Free Air Temperature Range
Storage Temperature Range

O"C to +70"C
-65'Cto + 150"C

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

V,H

High Level Input Voltage

Min

Nom

Max

4.5

5

5.5

Units
V

2

V

V,L

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-2

mA

10L

Low Level Output Current

20

mA

TA

Free Air Operating Temperature

70

'C

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25'C.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

-1.2

V

V,K

Input Clamp Voltage

Vee = 4.5V, I, = -18 mA

VOH

High Level Output
Voltage

10H = -2mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V. 10L = 20 mA

I,

Input Current at Max
Input Voltage

Vee = 5.5V, V,H = 7V

I'H

High Level Input Current

Vee = 5.5V, V,H = 2.7V

20

p.A

I,L

Low Level Input Current

Vee = 5.5V, V,L = 0.4V

-0.5

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

-112

mA

lee

Supply Current

Vee = 5.5V

V

Vee - 2

I
I

0.35

-30

0.5

V

0.1

mA

Outputs High

2.2

3.2

mA

Outputs Low

10.8

17.4

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Symbol

Note 1: See Section 1 for test waveforms and output load.

3-5

Min

Max

Units

1

4.5

ns

1

4

ns

_

National
Semiconductor
CorporaHon

DM74AS02 Quad 2-lnput NOR Gates
General Description
• Advanced oxide:isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TTL counterpart
• Improved AC performance over Schottky, low power
Schottky and advanced low power Schottky counterparts

This device contains four independent gates, each of which
performs the logic NOR function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package
Vee

Y4

B4

A4

Y3

B3

A3

a

/

7

Yl

AI

Y2

A2

B2

GND

Order Number DM74AS02M, N
See NS Package Number M14A or N14A

Function Table
V= AB
Inputs

H
L

Output

A

B

V

L
L
H
H

L
H
L
H

H
L
L
L

= High Logic Level
= Low Logic Level

3-6

TL/F/6272-1

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absoluta maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Seles Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Operating Free Air Temperature Range
Storage Temperature Range

OOCto +700C
-65·C to + 1500C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

VIL

Low Level Input Voltage

0.8

V

Vee

Supply Voltage

VIH

High Level Input Voltage

2

V

10H

High Level Output Current

-2

mA

10L

Low Level Output Current

20

rnA

TA

Free Air Operating Temperature

70

·c

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

Conditions

= 4.5V,11 = -18 rnA
10H = -2mA,
Vee = 4.5V to 5.5V
Vee = 4.5V, 10L = 20 rnA

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

II

Input Current at Max
Input Voltage

Vee

IIH

High Level Input Current

Vee

IlL

Low Level Input Current

10

Output Drive Current

lee

Supply Current

Min

=

5V, T A
Typ

Vee

=

5.5V, VIH

=
Vee =
Vee =
Vee =

5.5V, VIH

=

5.5V

I

I

25·C.
Max

Units

-1.2

V
V

Vee - 2
0.35

7V

= 2.7V
5.5V, VIL = 0.4V
5.5V, Vo = 2.25V

=

-30

0.5

V

0.1

rnA

20

p.A

-0.5

mA

-112

rnA

Outputs High

3.7

5.9

rnA

Outputs Low

12.5

20.1

rnA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Parameter

Conditions

tpLH

Symbol

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

Note 1: See SeCtion 1 for test waveforms and output load.

3-7

Min

Max

Units

1

4.5

ns

1

4.5

ns

NatiOnal

~ Semiconductor
Corporation

DM74AS04 Hex Inverters
General Description
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

This device contains six independent gates, each of which
performs the logic INVERT function.

Features
• Switching specifications al 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package

VCf

114

1
A1

Y8

A8

13

12

2
Y1

3
A2

A5
11

4
Y2

Y5

Y4

A4

10

5
A3

9

8
Y3

8

17
GND
TL/F/8273-1

Order Number DM74AS04M, N
See NS Package Number M14A or N14A

Function Table

Y=A
Input

Output

A

Y

L
H

H
L

H - High Logic Level
L - Low Logic Level

3-8

Absolute Maximum Ratings
Note: The "AbsolutB Maximum Ratings" arB those values
beyond which the safety of the device cannot be gusrantfIBd. The device should not be operatsd at theselimifs. The
parametric values defined in the "Electricsl Chsrscteristics"
tsbI8 srs not gusranf88d at the absolutB maximum ratings.
The "R8COfTImended Operating Conditions" table will define
the conditions for actusl device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales OffIce/
Dlstributore for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range

7V

+ 70"C
-65'C to + 15O"C
O"C to

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

4.5

5

5.5

Units

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.8

V

V
V

2

10H

High Level Output Current

-2

rnA

10l

Low Level Output Current

20

mA

TA

Free Air Operating Temperature

70

'C

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V. TA = 25·C.
Symbol

Paremeter

Condltlona

Min

Typ

Max

Units

-1.2

V

VIK

Input Clamp Voltage

Vee = 4.5V.11 = -18 mA

VOH

High Level Output
Voltage

10H = -2rnA
Vee = 4.5Vto5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V
10l = 20mA

II

Input Current @ Max
Input Voltage

Vee = 5.5V. VIH = 7V

IIH

High Level Input Current

Vee = 5.5V. VIH = 2.7V

20

/Jo A

III

Low Level Input Current

Vee = 5.5V. Vil = 0.4V

-0.5

mA

10

Output Drive Current

Vee = 5.5V. Vo = 2.25V

-112

mA

lee

Supply Current

Vee = 5.5V

V

VCC- 2
0.35

I
I

-30

0.5

V

0.1

mA

Outputs High

3

4.8

mA

Outputs Low

14

26.3

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHl

Propagation Delay Time
High to Low Level Output

Vee = 4.5Vt05.5V
Rl = 500n
Cl=50pF

Note 1: See Section 1 for test waveforms and output load.

3-9

Min

Max

Units

1

5

ns

1

4

ns

~r-----------------------------------------------------~

~":::E

c

•

National
Semiconductor
Corporation

DM74AS08 Quad 2-lnput AND Gate
General Description
This device contains four independent gates, each of which
performs the logic AND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TIL counterpart
• Improved AC performance over Schottky, low power
Schottky and advanced low power Schottky counterparts

Connection Diagram
Dual-In-Llne Package

A1

a1

Y1
TL/F/6106-1

Order Number DM74AS08M or DM74AS08N
See NS Package Number M14A or N14A

Function Table
Y =AB
Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

L
L
L
H

H = High Logic Level
L

= Low Logic Level

3-10

Absolute Maximum Ratings
If Military/Aerospace specified ~eYlces are required,
contact the National Semiconductor Sales Office/
Distributors for ayallability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those valU8S
beyond which the safety of the device cannot be guaran·
t88d. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table Will define
the conditions for actual device operation.

O"Cto +70"C
-65·Cto +1sQoC

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

IOH

High Level Output Current

-2

mA

20

mA

70

·c

2

IOL

Low Level Output Current

TA

Free Air Operating Temperature

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.

Symbol

Parameter

Min

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18mA

VOH

High Level Output
Voltage

IOH=-;-2mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee

=

4.5V, IOL = 20 mA

II

Input Current at Max
Input Voltage

Vee

=

5.5V, VIH

=

IIH

High Level Input Current

Vee

Low Level Input Current

Vee

=
=

5.5V, VIH

IlL

= 2.7V
= 0.4V

5.5V, VIL

Units

-1.2

V
V

0.35

7V

I

0.1

mA

20

p.A

-0.5

mA

-112

mA

9.3

mA

Outputs Low

14.9

24

mA

lee

I

V

5.8

Vee = 5.5V, Vo = 2.25V
Vee

-30

0.5

Outputs High

Output Drive Current
Supply Cu;"ent

5.5V

Max

Vee- 2

10

=

Typ

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

3·11

Min

Max

Units

1

5.5

ns

1

5.5

ns

~r-------------------------------------------------------~
.-

NatiOnal.
~r-- ~ Semiconductor

i!'i

Corporation

DM74AS10 Triple 3-lnput NAND Gates
• Advanced oxide-isolated. ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky.
low power· Schottky. and advanced low power Schottky
TTL counterpart
• Improved AC performance over Schottky. low power
Schottky. and advanced low power Schottky counterparts

General Description
This device contains three independent gates. each of
which performs the logic NAND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package

vcc

C1

A1

81

A2

C3

B3

82

C2

Y3

Y2
TLlF/6274-1

Order Number DM74AS10N
See NS Package Number N14A*

Function Table
Y=ABC
Inputs

Output

A

B

C

Y

X
X

X

L

L

L

X
H

X
X

H
H
H

H

L

H
H = High Logic Level
L = Low Logic Level
X

I~

=

EHher Low or High Logic Level

.

f"··
'Contact your locel NSC representative about surface mount (M) package availabilHy.

3-12

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air
Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "£/ectrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

O'Cto +70'C
-65'C to + 150'C

Storage Temperature Range

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-2

mA

10L

Low Level Output Current

20

mA

TA

Free Air Operating Temperature

70

'C

2

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

Conditions

=

VIK

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

10H = -2mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V, 10L

II

Input Current @ Max
Input Voltage

Vee = 5.5V, VIH = 7V

5V, TA
Typ

4.5V, II = -18 mA

=

20 mA

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

Low Level Input Current

Vee

10

Output Drive Current

Vee

Icc

Supply Current

Vee

5.5V

=

25'C.
Max

Units

-1.2

V
V

0.35

5.5V, VIL = O.4V
5.5V, Vo

=

Vee - 2

IlL

=
=
=

Min

=

2.25V

I
I

-30

0.5

V

0.1

mA

20

/LA

-0.5

mA

-112

mA

Outputs High

1.5

2.4

mA

Outputs Low

8.1

13

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol
tpLH

Parameter

Conditions

Propagation Delay Time
Low to High Level Output

Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

Propagation Delay Time
High to Low Level Output
Note 1: See Section 1 for test waveforms and output load.
tpHL

3·13

Min

Max

Units

1

4.5

ns

1

4.5

ns

~ ~~uctor

-~--~----------------------------------I

:Ii
Q

~ CorporaHon

DM74AS11 Triple 3-lnput AND Gates
• Advanced oXide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TTL counterpart
• Improved AC performance over Schottky, low power
Schottky, and advanced low power Schottky counter-

General Description
This device contains three independent gates each of which
performs the logic AND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

parts

Connection Diagram
Dual-In-Une Package
Vee

et

2

t

At

yt

8t

e3

3
A2

B3

4
82
TLlF/6275-1

Order Number DM74AS11N
See NS Package Number N14A'

Function Table
Y=ABC
Inputs

Output

A

B

C

Y

X
X
L
H

X
L
X
H

L
X
X
H

L
L
L
H

H = High Logic Level
L = Low Logic Level
X = Either Low or High Logic Level

'Contact your IoceI NBC representative about surface mount (M) package availability.

3-14

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Operating Free Air
Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

O"Cto +70"C

Storage Temperature Range

-65·Cto + 150"C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-2

mA

10L

Low Level Output Current

20

mA

TA

Free Air Operating Temperature

70

·c

2

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

Symbol

Parameter

Conditions

=

4.5V,11

=

Min

VIK

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

10H = -2mA
Vee = 4.5Vto 5.5V

VOL

Low Level Output
Voltage

Vee

=

4.5V, 10L

=

20 mA

II

Input Current @ Max
Input Voltage

Vee

=

5.5V, VIH

=

7V

=
=
Vee =
Vee =

= 2.7V
= 0.4V
= 2.25V

IIH

High Level Input Current

Vee

5.5V, VIH

IlL

Low Level Input Current

Vee

5.5V, VIL

10

Output Drive Current

lee

Supply Current

5.5V, Vo
5.5V

=

5V, T A

Typ

-18 mA

=

25·C.

Max

Units

-1.2

V
V

Vee - 2

I

I

0.35

-30

0.5

V

0.1

mA

20

/LA

-0.5

mA

-112

mA

Outputs High

4.3

7

mA

Outputs Low

11.2

18

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tPHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

3-15

Min

Max

Units

1

6

ns

1

5.5

ns

NaHonal

, Semiconductor
~
COrporaHon

DM74AS20 Dual 4-lnput NAND Gates
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TTL counterpart
• Improved AC performance over Schottky, low power
Schottky, and advanced low power Schottky counterparts

General Description
This device contains two independent gates, each of which
performs the logic NAND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package
VCC

114

D2

1

A1

C2

13

2
81

HC

12

82

111

/3

10

4

HC

C1

5
D1

A2

19

1&
Y1

Y2
B

17
GHD
TLiF16276-1

Order Number DM74AS20N
See NS Package Number N14A'

Function Table
Y = ABeD
Inputs

H

Output

A

B

C

D

Y

X
X
X
L
H

X
X
L
X
H

X
L
X
X
H

L
X
X
X
H

H
H
H
H
L

= High Logic Level

L = Low Logic Level
X = Either Low or High Logic Level

I
'Contect your local NSC representative about surface mount (M) package availability.

3-16

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Operating Free Air
Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

O"Cto +70"C

Storage Temperature Range

-65'C to + 150"C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-2

mA

20

mA

70

·c

10L

Low Level Output Current

TA

Free Air Operating Temperature

2

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V. T A = 25'C.
Symbol

Parameter

Min

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V.11 = -18 mA

VOH

High Level Output
Voltage

10H = -2mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V. 10L = 20 rnA

II

Input Current @ Max
Input Voltage

Vee = 5.5V. VIH = 7V

Typ

Max

Units

-1.2

V
V

Vee- 2
0.35

0.5

V

0.1

mA

IIH

High Level Input Current

Vee = 5.5V. VIH = 2.7V

20

/LA

IlL

Low Level Input Current

Vee = 5.5V. VIL = O.4V

-0.5

mA

10

Output Drive Current

Vee = 5.5V. Vo = 2.25V

lee

Supply Current

Vee = 5.5V

I

I

-112

mA

Outputs High

-30
1.1

1.6

mA

Outputs Low

6

8.7

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

3·17

Min

Max

Units

1

5

ns

1

4.5

ns

...N r--------------------------------------------------------------------------------,

;.....

:::E
C

National

~ SemiconductOr
.

Corporation

DlVi74AS21 Dual4-lnput AND Gates
General Description
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TTL counterpart
• Improved AC performance over Schottky, low power
Schottky and advanced low power Schottky counterparts

This device contains two independent 4-input gates, each of
which performs the logic AND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
vCC

, 114

Dual-In-Llne Package
02
C2
A2
NC
B2
13
12
10
/11
9

Y2

1

8

~
1
AI

2
Bl

4

13
NC

Cl

5

01

~
)1

6

Gl~

Order Number DM74AS21N
See NS Package Number N14A·

Function Table
Inputs

Output

A

B

C

D

Y

H
L
X
X
X

H
X
L
X
X

H
X
X
L
X

H
X
X
X
L

H
L
L
L
L

H

~

High Logic Level

L

~

Low Logic Level

X

~

Either

Lew or High Logic Level

'Contact your local NSC representative about surface mount (M) psckage availability.

3-18

TL/F/6277-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Operating Free Air Temperature Range
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

+ 70'C
+ 150"C

O"C to
-65'Cto

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

2

V

10H

High Level Output Current

-2

mA

10L

Low Level Output Current

20

rnA

TA

Free Air Operating Temperature

70

'C

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, T A = 25'C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,II = -18 rnA

VOH

High LevElIOutl?ut
Voltage

10H = -2 rnA,
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V, 10L = 20 rnA

II

Input Current @ Max
Input Voltage

Vee = 5.5V, VIH = 7V

Min

Typ

Max

Units

-1.2

V
V

Vee - 2
0.35

0.5

V

0.1

rnA

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

p,A

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.5

rnA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

lee

Supply Current

Vee = 5.5V

I

I

-112

rnA

Outputs High

-30
2.9

4.6

rnA

Outputs Low

7.4

12

rnA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Note

1: See Section 1 for test waveforms and output load.

3·19

Min

Max

Units

1

6

ns

1

6

ns

~r---------------------------------------------------------~

~

~

::::e

c

_

National
. Semiconductor
CorporaHon

DM74AS27 Triple 3-lnput NOR Gates
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TIL counterpart
• Improved AC performance over Schottky, low power
Schottky, and advanced low power Schottky counterparts

General Description
This device contains three independent 3-input gates, each
of which performs the logic NOR function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package
VCC

Y1

C1

C3

12

B3

A3

Y3

C2

Y2

GND

11

3

4
82

Order Number DM74AS27N
See NS Package Number N14A·

Function Table
Y=A+B+C
Inputs
A
L
H

X
X

Output

B

C

Y

L

L

X
H

X
X

X

H

H
L
L
L

H = High Logic Level
L
X

= Low Logic Level
= Either Low or High Logic Level

'Contact your local NSC representative about surface mount (M) psckage aVailability.

3-20

TUF/6278-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Operating Free Air
Temperature Range

Note: The ''Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

O'Cto +70'C

Storage Temperature Range

- 65'C to + 150'C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

4.5

5

5.5

Units

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

IOH

High Level Output Current

-2

mA

IOL

Low Level Output Current

20

mA

TA

Free Air Operating Temperature

70

'C

V
V

2

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

Conditions

=

=

Min

=

5V, T A
Typ

=

25'C.
Max

Units

-1.2

V

VIK

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

IOH = -2mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee

=

4.5V, 10L

=

20 mA

II

Input Current at Max
Input Voltage

Vee

=

5.5V, VIH

=

7V

IIH

High Level Input Current

Vee

=

5.5V, VIH

=

2.7V

20

/LA

IlL

Low Level Input Current

Vee

5.5V, VIL

-0.5

mA

Output Drive Current

Vee

=
=

O.4V

10

=
=

-112

mA

lee

Supply Current

Vee

=

5.5V

4.5V, II

5.5V, Vo

-18 mA

V

Vee - 2

2.25V

I

I

0.35

-30

0.5

V

0.1

mA

Outputs High

4

6.4

mA

Outputs Low

10.6

17.1

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

Min

Max

Units

1

5.5

ns

1

4.5

ns

Note 1: See Section 1 for test waveforms and output load.

II
3-21

~ Semiconductor
NatiOnal

Corporation

DM74AS30 8 Input NAND Gate
• Advanced oxide-isolated. ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with Schottky.
low power Schottky. and advanced low power Schottky
TIL counterpart
• Improved AC performance over Schottky. low power
Schottky. and advanced low power Schottky counterparts

General Description
This device contains a single gate which performs the logic
NAND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package
H

He

G

12

11

NC

110

y

19

8

)0-

2
A

B

C

~Ie
5

4

3

D

F

E

Order Number DM74AS30N
See NS Package Number N14Ao

Function Table
Y = ABCDEFGH
Inputs

Output

Athru H

Y

AllinputsH
One or More
Inputs L

L
H

H ~ High Logic Level
L

~

Low Logic Level

'Contact your local NSC representative about surface mount (M) packaga availability.

3-22

17
GND

TL/F/6279-1

Absolute Maximum Ratings

Note~ The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical CharacfBrlstics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air
Temperature Range
O"Cto +70"C
Storage Temperature Range
-65'Cto + 150"C

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

Min

Nom

Max

Units

4.5

5

5.5

V

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-2

mA

10l

Low Level Output Current

20

mA

TA

Free Air Operating Temperature

70

'C

2

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25'C.
Symbol

Parameter

Conditions

Min

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

IOH=-2mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V, 10l = 20 mA

II

Input Current at Max
Input Voltage

Vee = 5.5V, VIH = 7V

Typ

Max

Units

-1.2

V

Vee- 2

V
0.35

0.5

V

0.1

mA

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

p.A

III

Low Level Input Current

Vee = 5.5V, Vil = 0.4V

-0.5

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

-112

mA

Icc

Supply Current

Vee = 5.5V

I
I

-30

Outputs High

1

1.5

mA

Outputs Low

3.4

4.9

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tplH

Propagation Delay Time
Low to High Level Output

tpHl

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
Rl = 500n
Cl = 50pF

Note 1: See Section 1 for

test waveforms and output load.

3-23

Min

Max

Units

1

5

ns

1

4.5

ns

N.-----------------~----------------------------------------I

~

:IE
Q

NaHonal

~ Semiconductor
CorporaHon

DM74AS32 Quad 2-lnput OR Gates
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TTL counterpart
• Improved AC performance over Schottky, low power
Schottky and advanced low power Schottky counterparts

General Description
This device contains four independent gates, each of which
performs the logic AND function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package
vee

B4

A4

Y4

Y3

B3

7
A1

B1

A2

Y1

B2

Y2

GND
TL/F /6280-1

Order Number DM74AS32M or DM74AS32N
See NS Package Number M14A or N14A

Function Table
Y=A+B
Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

L
H
H
H

H

~

High Logic Level

L

~

Lew Legic Level

3-24

Absolute Maximum Ratings
If MIlitary/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air
Temperature Range
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V
O'Cto +70"C
-65'C to + 150'C

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

Min

Nom

Max

4.5

5

5.5

Units
V

2

V

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-2

rnA

20

rnA

70

'C

10L

Low Level Output Current

TA

Free Air Operating Temperature

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25'C.
Symbol

Parameter

Conditions

Min

Typ

Max

Units

-1.2

V

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18 rnA

VOH

High Level Output
Voltage

Vee = 4.5V to 5.5V
10H = -2mA

VOL

Low Level Output
Voltage

Vee = 4.5V, 10L = 20 mA

II

Input Current at Max
Input Voltage

Vee = 5.5V, VIH = 7V

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

/LA

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.5

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

Icc

Supply Current

Vee = 5.5V

V

Vee- 2

I
I

0.35

-30

0.5

V

0.1

rnA

-112

mA

Outputs High

7.3

12

mA

Outputs Low

16.5

26.6

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

Note 1: See Section 1 for lest waveforms and output load.

3·25

Min

Max

Units

1

5.8

ns

1

5.8

ns

_

National
Semiconductor

CorporaHpn

DM74AS34 Hex Non-Inverter
~eneral

Description

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated. ion-implanted Schottky TIL
process

these devices contain six independent gates. each of which
performs the logic identity function.

Connection Diagram
Dual-In-Llne Package

ya

Aa

y~c

114

13

--t>1

Y5

11

3

Y1

II

a

1>4

A2

Y4

A4

10

--t>2

A1

AS

12

Y2

a

5
A3

Y3

17
GND
TLlF/6281-1

Order Number DM74AS34N
Package Number N14A·
See

llis

Function Table

Y=A

H

~

L

~

Input

Output

A
H

Y
H

L

L

High Logic Level
Low Lcglc Level

'Ccntact your loeel NSC representative about surface mount (M) package availability.

3·26

Absolute Maximum Ratings
Note: The ''Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V
O·Cto +70·C

Operating Free Air Temperature Range
Storage Temperature Range

- 65·C to + 150"C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

IOH

High Level Output Current

-2

mA

10L

Low Level Output Current

20

mA

TA

Free Air Operating Temperature

70

·C

V

2

0

Electrical Characteristics
over recommended operating free air temperature ran~e. All typical values are measured at Vee = 5V, T A = 25·C.
Symbol

Conditions

Parameter

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V to 5.5V
IOH = -2mA

VOL

Low Level Output
Voltage

Vee = 4.5V,
10L = 20mA

II

Input Current @ Max
Input Voltage

Vee = 5.5V, VIH = 7V

Min

Typ

Max

Units

-1.2

V
V

Vee- 2
0.35

0.5

V

0.1

mA

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

/LA

IlL

Low Level Input Current

Vee = 5.5V, VIL = O.4V

-0.5

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

lee

Supply Current

Vee = 5.5V

-112

mA

7.4

12

mA

21.3

34.6

mA

-30

I Outputs High
I Outputs Low

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 5000.
CL = 50pF

Min

Max

Units

1

5.5

ns

1

6

ns

Note 1: See Section 1 for test waveforms and output load.

&I
3-27

~._.
:Ii
Q

II

National

Semiconductor

Corporation

DM74AS7 4 Dual D Positive-Edge-Triggered
Flip-Flops with Preset and Clear
General Description

Features

The AS74 is a dual edge-triggered flip-flops. Each flip-flop
has individual 0, clock, clear and preset Inputs, and also
complementary 0 and ~ outputs.
Information at input 0 is transferred to the 0 output on the
positive gOing edge of the clock pulse. Clock triggering 0ccurs at a voltage level of the clock pulse and is not directly
related to the transition time of the positive going pulse.
When the clock input Is at either the high or low level, the 0
Input signal has no effect.
Asynchronous praset and clear inputs will set or clear 0
output respectively upon the application of low level signal.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with Schottky
and LS TTL counterpart
.
• Improved AC performance over 974 at approximately
half the power

Connection Diagram
Dual-In-llne Package
Vee

CLR2

CLRI

Dl

D2

CLK2

PR2

Q2

Q2

CLK 1 PR 1

Ql

01

GND

7
TUF/8282-1

Order Number DM74AS74M, N
See NS Package Number M14A or N14A

Function Table
Inputs

L

Outputs

PR

CLR

ClK

D

Q

a

L
H
L
H
H
H

H
L
L
H
H
H

X
X
X

X
X
X
H
L
X

H
L
H*
H
L

L
H
H*
L
H

00

00

t
t
L

= Low State, H = High State, X =

Don~

Care

t = PooI1Iva Edge TransI1Ion
00 = Previous Condition of Q
• = This condition Is nonstable; R will not persist wilen preset end cI_
Inputs retum to Ihelr inactive (high) level. The outpullevels in this condition
are not guaranteed to meet the VOH specification.

3-28

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V

Input Voltage

7V

Operating Free Air Temperature Range

O"Cto +70"C
-65·Cto + 150"C

Storage Temperature Range

Recommended Operating Conditions
Symbol

Parameter

Vcc

Supply Voltage

VIH

High Level Input Voltage

Min

Nom

Max

Unite

4.5

5

5.5

V
V

2

Vil

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-2

mA

10l

Low Level Output Current

fClK

Clock Frequency

tW(ClK)

Width of Clock Pulse

0

I
I

20

mA

105

MHz

High

4

Low

5.5

ns
ns

4

ns

tw

Pulse Width Preset & Clear Low

tsu
tsu

Data Setup Time

4.5f

ns

PRE or CLR Setup-Time

2t

ns

tH

Data Hold Time

ot

Free Air Operating Temperature
TA
The ( t) arrow indicates the positive edge of the Clock is used for reference.

ns

0

·C

70

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

= 4.5V, II = -18 mA
Vee = 4.5V to 5.5V,
10H = -2mA

VOL

Low Level Output
Voltage

VCC = 4.5V, VIH
10l = 20mA

II

Input Current @ Max
Input Voltage

Vee

IIH

High Level Input Current

Vee = 5.5V,
VIH = 2.7V

III

Low Level Input Current

Vee = 5.5V,
Vil = 0.4V

Clock,D

10

Output Drive Current

VCC

Icc

Supply Current

VCC

Min

=

5V, TA
Typ

Vee

=

=
=

5.5V, VIH

5.5V, Vo

=

Max,

=

7V

Max

Units

-1.2

V
V

0.5

V

0.1

mA

Clock,D

20

fJ-A

Preset, Clear

40

fJ-A

-0.5

mA

-1.8

mA

2.25V

0.35

-30
10.5

5.5V

25·C.

Vee- 2

Preset, Clear

=

=

-112

mA

16

mA

II
3-29

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

Vee = 4.SV to S.SV
RL = soon
CL = 50pF

tpHL
tpLH
tpHL

From

To

Min

Preset
or Clear

Oor

Propagation Delay Time
High to Low Level Output

Preset
or Clear

Oor

Propagation Delay Time
Low to High Level Output

Clock

Oor

Propagation Delay Time
High to Low Level Output

Clock

0
0
0
Oor

0

ns

3.S

10.S

ns

3.S

8

ns

4.S

9

ns

1

CLEAR

I

0

~

~

3·30

MHz
7.S

Logic Diagram

ClOCK

Units

3

Note 1: See Section 1 for test waveforms and output load.

PRESET

Max

10S

TUF/6262-2

_

National

Semiconductor
Corporation

DM74AS86 Quad 2-lnput Exclusive-OR Gates
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TTL counterpart
• Improved AC performance over Schottky, low power
Schottky, and advanced low power Schottky counterparts

General Description
This device contains four independent gates, each of which
performs the logic exclusive-OR function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Une Package
vee

B4

A4

Y4

A1

B1

Y1

A2

B3

7
Y2

Order Number DM74AS86N
See NS Package Number N14A·

Function Table
Y=AEDB=AB+AB
Inputs

H

Outputs

A

B

L
L

L

L

H

H
H

L

H
H

H

L

= High Logic Level

L = Low Logic Level

'Contact your local NSC representative about surface mount (M) package availability.

3-31

GND

TL/F/6283-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Operating Free Air
Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The devica should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

O·Cto +700C

Storage Temperature Range

- 65·C to + 1500C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Unita

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-2

mA

10L

Low Level Output Current

20

mA

TA

Free Air Operating Temperature

70

·C

2

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V. T A = 25·C.
Symbol

Parameter

Min

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V.11 = -18 mA

VOH

High Level Output
Voltage

10H = -2mA
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V. 10L = 20 mA

II

Input Current @ Max
Input Voltage

Vee = 5.5V. VIH = 7V

Typ

Max

Units

-1.2

V

Vee- 2

V
0.35

0.5

V

0.1

mA

IIH

High Level Input Current

Vee = 5.5V. VIH = 2.7V

20

/LA

IlL

Low Level Input Current

Vee = 5.5V. VIL = 0.4V

-0.5

mA

10

Output Drive Current

Vee = 5.5V. Vo = 2.25V

lec

Supply Current

Vee = 5.5V

I
I

-30

-112

mA

Outputs High

12

16.5

mA

Outputs Low

24

38

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol
tpLH

tpHL

tpLH

tpHL

Parameter

Conditions

Min

Max

Units

Propagation Delay Time
Low to High Level Output
(Other Input Low)

Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

2

6.5

ns

Propagation Delay Time
High to Low Level Output
(Other Input Low)

2

6.5

ns

Propagation Delay Time
Low to High Level Output
(Other Input High)

1

6

ns

Propagation Delay Time
High to Low Level Output
(Other Input High)

1

6

ns

Note 1: See Section 1 lor test waveforms and output load.

3·32

National
Semiconductor
Corporation

_

DM74AS 109 Dual J-K Positive-Edge-Triggered
Flip-Flops with Preset and Clear
General Description

Features

The DM54AS109 is a dual edge-triggered flip-flop. Each flipflop has individual J, R, clock, clear and preset inputs, and
also complementary 0 and 0 outputs.
Information at inputs J and K meeting the setup time requirements are transferred to the 0 output on the positive
going edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse and is not directly related to
the transition time of the positive going pulse. When the
clock input is at either the high or low level, the J, K input
signal has no effect.
Asynchronous preset and clear inputs will set or reset 0
output respectively upon the application of low level signal.
The J-K design allows operation as a 0 flip-flop by tying the
J and K inputs together.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and LS TTL counterpart
• Improved AC performance over S109 at approximately
half the power

Connection Diagram

Function Table

Dual-In-Une Package
Vee

116

CLRZ

JZ

KZ

14

\15

\13

1Z

OZ

10

111

9

~

L

I

oz

CLKZ PRZ

PR

0"

J
_ CLR_
0
K

r--

.....

~CLK

J PR

on

---

i>CLK
K

CLR

0 ~

Q

I
CLR 1

Z
J1

CLR

L
H
L
H
H
H
H
H

H
L
L
H
H
H
H
H

Inputs
CK

X
X
X

t
t
t
t
L

Outputs

c:i

J

K

Q

X
X
X
L
H
L
H
X

X
X
X
L
L
H
H
X

H
L
L
H
HO
H*
L
H
TOGGLE

00

00

H

L

00

00

= Low State, H = High Stete, X = Don't Cere
t = Positive Edge Transition, 00 = Previous Condition of Q

L

Q

1

PR

15

14
it3
CLK 1 PR 1

7

6
01

01

18
GND

'This condition is nonstable; it will not persist when preset and clear inputs
retum to their inactive (high) level. The output levels in this condHion are not
guaranteed to meet tha VOH specification.

TL/F/6284-1

Order Number DM74AS109N
See NS Package Number N16A°

'Coniect your local NSC representetive about surface mount (M) package availabiHly.

3-33

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150"C

Note: The ''Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these Omits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

Parameter

Vcc

Supply Voltage

VIH

High Level Input Voltage

Min

Nom

Max

4.5

5

5.5

Units

V
V

2

Vil

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-2

mA

10l

Low Level Output Current

fClK

Clock Frequency

tWClK

Pulse Width

tw
tsu

0

mA
MHz

Clock High

4

ns

Clock Low

5.5

ns

4

ns

Pulse Width

Preset & Clear

Data Setup Time

JorK

5.5t

PREorCLR
Inactive
tH

20
105

Data Hold Time

ns
2t
ns

ot

Free Air Operating Temperature
TA
The ( t) indicates the positive edge of the Clock Is used for reference.

0

·C

70

Electrical Characteristics
over recommended operating free-air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

Min

Typ

Max

Units

-1.2

V

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

10H = -2mA
VCC = 4.5V to 5.5V

VOL

Low Level Output
Voltage

VCC = 4.5V, VIH = 2V
10l = 20mA

II

Input Current at Max
Input Voltage

VCC = 5.5V, VIH = 7V

IIH

High Level Input
Current

Vee = 5.5V,
VIH = 2.7V

Clock,J, K

20

Preset, Clear

40

Low Level Input
Current

VCC = 5.5V,
Vil = O.4V

Clock,J, K

-0.5

Preset, Clear

-1.8

Output Drive Current

Vo = 2.25V, Vee = 5.5V

III

10

Supply Current
Vee = 5.5V (Note 1)
Icc
Note 1: Icc Is meesured with J, K, ClK and PR grounded, then with J, K, ClK and ClR grounded.

3-34

V

VCC- 2
0.35

-30
11.5

0.5

V

0.1

mA
IJoA
mA

-112

mA

17

mA

c

i:

Symbol

Parameter

Conditions
Vee = 4.5V to 5.5V
RL = 5000.
CL = 50pF

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

tPHL

From

To

Min

Max

105

Units
MHz

Preset
or Clear

cora

3

8

ns

Propagation Delay Time
High to Low Level Output

Preset
or Clear

cora

3.5

10.5

ns

tpLH

Propagation Delay Time
Low to High Level Output

Clock

cora

3.5

9

ns

tpHL

Propagation Delay Time
High to Low Level Output

Clock

cora

4.5

9

ns

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram
PRESET

rr=L>)c)----- 0
CLEAR

elK

I

~I

'--------1

] )0-

K---I~~'----11
TUF/62B4-2

3-35

...
.....

Switching Characteristics over recommended operating free air temperature range (Note 1)

l>

CJ)

.....
Q
CD

II

National

Semiconductor
Corporation

DM74AS136 Quad 2-lnput
Exclusive-OR Gates with Open-Collector Outputs
General Description

Features

This device contains four independent gates, each of which
performs the logic exclusive-OR function. The open-collector outputs require external pull-up resistors for proper logical operation.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vcc range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TTL counterparts
• Improved AC performance over Schottky, low power
Schottky, and advanced low power Schottky counterparts
• Open collector outputs for wired AND cascading
• PNP input design reduces input loading

Pull-Up Resistor Equations
RMAX=
R
Where:

_V.=cc""--,-(M...,.i..:n)c..-:-:-V-,,,-OH'-':.
N1 (lOH) + N2 (lIH)

Vee (Max) - VOL
MIN = .. IOL - N3 (IIU

N1 (IOH) = total maximum output high current for
all outputs tied to pull-up resistor
N2 (lIH) = total maximum input high current for all
inputs tied to pull-up resistor

N3 (lIU = total maximum input low current for all
inputs tied to pull-up resistor

Connection Diagram
Dual-In-L1ne Package

A1

81

Y1

A2

82

Y2

Order Number DM74AS136N
See NS Package Number N14A*

Function Table
Y=AE&B
Output

Inputs

H
L

A

B

Y

L
L
H
H

L
H
L
H

L
H
H
L

= High Logic Level
= Low Logic Level

'Contact your local NSC representative about surface mount (M) package availability.

3-36

GND

TUF/6718-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V
7V

Output Voltage (off-state)
Operating Free Air Temperature Range
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

O"Cto +70"C
-65'C to + 150'C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

VOH

High Level Output Voltage

5.5

V

IOL

Low Level Output Current

20

mA

TA

Free Air Operating Temperature

70

'C

2

V

0

V

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)

Symbol

Parameter

Conditions

Typ
(Note 1)

Min

Max

Units

VI

Input Clamp Voltage

Vee = Min, 11= -18 mA

-1.2

V

leEX

High Level Output
Current

Vee = Min, Vo = 5.5V
VIL = Max, VIH = Min

100

p.A

VOL

Low Level Output
Voltage

Vee = Min, IOL = Max
VIH = Min, VIL = Max

0.5

V

II

Input Current at Max
Input Voltage

Vee = Max, VI = 7V

0.1

mA

IIH

High Level Input Current

Vee = Max, VI = 2.7V

20

p.A

IlL

Low Level Input Current

Vee = Max, VI = 0.5V

-0.5

mA

lee

Supply Current

Vee = Max

0.35

Outputs High

13

18

Outputs Low

28

41

mA

Switching Characteristics
over recommended operating free air temperature range (Note 1)

Symbol

Parameter

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

DM74AS136

Conditions
Other Input Low
Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF
Other Input Low
Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Note 1: See Section 1 for lest waveforms and output load.

3-37

Units

Min

Max

5

45

ns

1

8

ns

5

45

ns

1

9

ns

co

II)
..-

.---------------------------------------------------------------------------~

~:::E

~ Semiconductor

j:::

..-

DM74AS157/DM74AS158
Quad 1 of 2 Line Data Selectors/Multiplexers

:::E

General Description

NatiOnal

Corporation

C

II)

~,....
C

• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TTL counterpart
• Improved AC performance over Schottky, low power
Schottky, and advanced low power Schottky counter-

These data selectors/multiplexers contain inverters and
drivers to supply full on-Chip data selection to the four output gates. A separate strobe input is provided. A 4-bit word
is selected from one of two sources and is routed to the four
outputs. The AS157 presents true data whereas the AS158
presents inverted data to minimize propagation delay time.

Features

parts

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

• Expand any data input point
• Multiplex dual data buses
• General four functions of two variables (one variable is
common)
• Source programmable counters

Connection Diagram
Dual·ln·Llne Package

--- --INPUTS

vee

STROBE 4A

·116

15

G

OUTPUT ItAJTS
4Y

4B

14

13

12

11

4B

4Y

3A

38

18

1Y

2A

2B

2Y

SELECT

2

3

-1A

1B

INPUTS

4

5

6

--

1Y

2A

2B

9

OUTPUT INPUTS

7 /8
2Y

Function Table
Inputs

OutputY

Strobe

Select

A

B

AS157

AS158

H
L
L
L
L

X
L
L
H
H

X
L
H
X
X

X
X
X
L
H

L
L
H
L
H

H
H
L
H
L

= High Level, L = Low Level, X = Don't Care

'Contact your local NSC representative about surface mount (M) package aVailability.

3·38

GND

OUTPUT

Order Number DM74AS157N
or DM74AS158N
See NS Package Number N16A*

H

3Y

3Y -

1A

1

10

4A

-S

OUTPUT

3B

3A

TUF/6290-1

Absolute Maximum Ratings
If Military/Aerospace specified devlcee are required,
contact the National Semiconductor Seles Office/
Distributors for availability and speclflceUona.
Supply VoHage
7V
Input Voltage
7V
Operating Free Air Temperature Range
OOCto +700C
Storage Temperature Range
-65'Cto +l500C

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

DM74AS157, 158

Parameter

Nom

Max

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

IOH

High Level Output Current

-2

mA

IOL

Low Level Output Current

20

mA

TA

Free Air Operating Temperature

70

'C

V

2

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Paremeter

Conditions

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

Vee

= 4.5V, 10L = 20 mA

II

Input Current at Max
Input Voltage

Vee

= 5.5V, VIH = 7V

High Level Input Current

Vee

IlL

Low Level Input Current

10

Output Drive Current

lee

Supply Current

= 5V, TA = 25'C.

Min

= 4.5V,11 = -18 mA
Vee = 4.5V to 5.5V, 10H = - 2 mA

VIK

IIH

Units

Min

Typ

Vee

= 5.5V, VIH = 2.7V

Vee = 5.5V,
VIL = 0.4V

I 'ASl58

3-39

V
V

0.35

0.5

Select

0.2

All Others

0.1

Select

40

All Others

20

V
mA
p.A

-1

Select

= 5.5V, Vo = 2.25V
Vee = 5.5V
I 'AS157

Units

Vee- 2

-0.5

All Others

Vee

Max
-1.2

-30

mA

-112

mA

17.5

28

mA

15.6

22.5

mA

'AS 157 Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

From
(Input)

Conditions
Vee = 4.SV to S.SV,
CL = SOpF,
RL = SOOO

To
(Output)

Data

Y

Data

Y

Propagation Delay Time,
Low to High Level Output

Strobe

Y

tpHL

Propagation Delay Time,
High to Low Level Output

Strobe

Y

tpLH

Propagation Delay Time,
Low to High Level Output

Select

y

tpHL

Propagation Delay Time,
High to Low Level Output

Select

Y

DM74AS157

Units

Min

Max

1

6

ns

1

S.S

ns

2

10.S

ns

2

7.S

ns

2

11

ns

2

10

ns

'AS 158 Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

From
(Input)

Conditions
Vee = 4.SV to S.SV,
CL = SOpF,
RL = SOOO

To
(Output)

.Data

Y

Data

Y

Propagation Delay Time,
Low to High Level Output

Strobe

Y

tpHL

Propagation Delay Time,
High to Low Level Output

Strobe

Y

tpLH

Propagation Delay Time,
Low to High Level Output

Select

y

tpHL

Propagation Delay Time,
High to Low Level Output

Select

Y

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Note 1: See Section 1 for test waveforms and output load.

3-40

DM74AS158

Units

Min

Max

1

S

ns

1

4.S

ns

2

6.S

ns

2

10

ns

2

9.S

ns

2

10.S

ns

~------------------------------------~i

Logic Diagrams

-~

AS157

~

i

-~

., 3

~~5-----t====+=+=rJ

~

~ II

,,10
~ 14

~ 13

STIDIE .!:15:.-_ _ _-q
TlIF/1I29O-2

AS158
AI 2

., 3

~ 11

IIa

10

~ 14

~ 13

SELEtT-1....,__~

'TI08E~I::.5_----q,r
TUF/6290-3

3-41

•

National

~ Semiconductor
Corporation

DM74AS160, 161, 162, 163

Synchronous Four-Bit Counters
General Description

Features

These synchronous presettable counters feature an internal
carry look ahead for application in high speed counting designs. The AS160 and AS162 are four-bit decade counters,
while the AS161 and AS163 are four-bit binary counters.
The AS160 and AS161 clear asynchronously, while the
AS162 and AS163 clear synchronously. The carry output is
decoded to prevent spikes during normal counting mode of
operation. Synchronous operation is provided by having all
flip-flops clocked simultaneously so that outputs change coincident with each other when so instructed by count enable
inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered
clock input triggers the four flip-flops on the rising (positivegoing) edge of the clock input waveform.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts
• Synchronously programmable
• Internal look ahead for fast counting
• Carry output for n-bit cascading
• Synchronous counting
• Load control line
• ESO inputs

These counters are fully programmable, that is, the outputs
may each be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the
counter and causes the outputs to agree with set up data
after the next clock pulse regardless of the levels of enable
input. Low to high transitions at the load input are perfectly
acceptable regardless of the logic levels on the clock or
enable inputs. (Continued)

Connection Diagram
Dual-In-Llne Package
RIPPLE
CARRY
vCC OUTPUT OA

OUTPUTS
OB

Oc

00

ENABLE
T
LOAD

10

RIPPLE OA
CARRY
OUTPUT
CLEAR
CK

Oa

9

Oc
LOAD
ENABLE

A

B

C

D

P

CLEAR CLOCK A

B

C

D ENABLEGNO

2

8
P
DATA INPUTS
TUFI6291-1

Order Number DM74AS160N, DM74AS161N,
DM74AS162N or DM74AS163N
See NS Package Number N16A*

'Contact your local NSC representative about surface mount (M) package availability.

3-42

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications_
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

O·Cto +700C

Storage Temperature Range

- 65·C to + 1500C

Recommended Operating Conditions
Symbol

DM74AS160 thru 183

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

Units

Min

Nom

Max

4.5

5

5.5

2

V
V

Vil

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-2

mA

10l

Low Level Output Current

fClK

Clock Frequency

tsu

!setup, Set-Up Time

0

tH

8

ns

En P, EnT

8

ns

Load

8

ns

I

Low

12

I

High

9

Clear

thold, Hold Time

Hold 0
(Only for 160 & 161)

mA
MHz

Data;A,B,C,D

Clear (Only for
162 & 163)
Set-up 1
(Only for 160 & 161)

20
75

ns

8

ns
ns

Data; A, B, C, 0

0

En P, EnT

0

ns

Load

0

ns

Clear·
(Only for 162 & 163)

0

ns

0

ns

Clear

tWClK

Width of Clock Pulse

twClR

Width of Clear Pulse, (,AS160, 'AS161 Low)

6.7

ns

8

ns

Electrical Characteristics over recommended operating free air temperature range
All typical values are measured at Vee
Symbol

=

5V, TA

=

25·C

Parameter

Conditions

= 4.5V, II =
= -2mA,

VIK

Input Clamp Voltage

VCC

VOH

High Level Output
Voltage

10H
VCC

VOL

Low Level Output
Voltage

Vee = 4.5V,
10l = 20mA

II

Input Current @ Max
Input Voltage

VCC = 5.5V,
VIH = 7V

IIH

III

High Level Input Current

Low Level Input Current

>=

Output Drive Current

Vee

Supply Current

Vee

=
=

5.5V, Vo

Load

0.3
0.2

Others

0.1

Load

60

ENT

40

Others

20

Units

V·

V

mA

/loA

-0.5

ENT

-1

Others

0.5

= 2.25V

-30
35

3-43

0.5

ENT

Load

5.5V

M.ax
-1.2

V
0.35

Vee = 5.5V,
Vil = O.4V

Icc

Typ

Vee - 2

4.5 to 5.5V

VCC = 5.5V,
VIH = 2.7V

10

Min

-18 mA

mA

-112

mA

53

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol.

Parameter

Conditions

From

To

DM74AS160 thru 163
Min

fMAX

Max. Clock Freq.

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Vee = 4.5V
t05.5V
RL = 5000
CL = 50pF

Ripple
Garry

Propagation Delay Time
Low to High Level Output
with Load High

Clock

Propagation Delay Time
Low to High Level Output
with Load Low

Clock

tpLH

Propagation Delay Time
Low to High Level Output

Clock

AnyQ

tpHL

Propagation Delay Time
High to Low Level Output

Clock

AnyQ

tpLH

Propagation Delay Time
Low to High Level Output

EnT

tpHL

Propagation Delay Time
High to Low Level Output

tpHL

tpLH

tpHL

MHz

75
Clock

Units

Max

2

12.5

ns

Ripple
Carry

1

8

ns

Ripple
Carry

3

16.5

ns

1

7

ns

2

13

ns

Ripple
Carry

1.5

9

ns

EnT

Ripple
Garry

1

8.5

ns

Propagation Delay Time
High to Low Level Output

Clear
(AS160,
AS161)

AnyQ
2

13

ns

Propagation Delay Time
High to Low Level Output

Clear
(AS160,
AS161)

Ripple
Garry

2

12.5

n8

Note 1: See Section 1 for test waveforms and output load.

General Description

(Continued)

n

The AS160 and AS161 clear function is asynchronous. A
low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load or enable
inputs. These two counters are provided with a clear on
power-up feature. The AS162 and AS163 clear function is
synchronous; and a low level at the clear input sets all four
of the flip-flop outputs low after the next clock pulse, regardless of the levels of enable inputs. This synchronous clear
allows the count length 10 be modified easily, as decoding
the maximum count desired can be accomplished with one
external NAND gate. The gate output is connected to the
clear input to synchronously clear the counter to all low outputs. Low to high transitions at the clear input of the AS162
and AS 163 are also permissible regardless of the levels of
logic on the clock, enable or load inputs.
The carry look ahead cirCUitry provides for cascading counters for n bit synchronous application without additional gating. Instrumental in accomplishing this function are two

count-enable inputs (P and
and a ripple carry output.
Both count-enable inputs must be high to count. The T input
is fed forward to enable the ripple carry output. The ripple
carry output thus enabled will produce a high level output
pulse with a duration approximately equal to the high level
portion of QA output. This high level overflow ripple carry
pulse can be used to enable successive cascaded stages.
High to low level transitions at the enable P or T inputs of
the AS160 through AS163, may occur regardless of the Iogic level on the clock.
The AS160 through SA163 feature a fully independent clock
circuit. Changes made to control inputs (enable P or T, or
load) that will modify the operating mode will have no effect
until clocking occurs. The function of the counter (whether
enabled, disabled, loading or counting) will be dictated soleIy by the conditions meeting the stable set-up and hold
times.

3-44

r-----------------------------------------------------------------------.o
!!:
Logic Diagrams
....
AS160
....~
G)

~

o

[~J
r----------o-!Lo

-

......
v

r--f".

LOA 0

I

C;:

4

1

OATAC

ij~O

CLR

...--

CLOCK

ex

~" I

-

CLEAR

or-

1

...--

DATA B

1

CLR

'.

-~

I

~
-

~

to--

6

~
--

1

CLR

or0

I

ex

-

1

-~
Dc
o ....

I

~" J
CLR

CLK
~

Ot-

01- ~ 00
L-

~

RIPPLE
CARRY

1 10

TUF/629,-3

I
3-46

c

!!I:
......

Logic Diagrams (Continued)

Ao

l;;
.....

AS162

OAtAA

~~~

3

~~J
=f
-1~~J,

0)

0
.....

c

i:

......

OA

.....
0)
.....
.....
C

i:

......
Ao
~

U)

-~ Os

DATAS

CLOCK

OATAC
CLUR

LOAD

4

2

......

.~

5
1

....

~

-

-,

1

,

'-

0)
Co)

12

~.-

Oc

00

L-olr'-

>"

10

RIPPLE
CARRY

TL/F/6291-4

3·47

N
.....
C
a:::
......
Ao

H~J
. l~..-t>-"~"J

OAIAD

.....
0)

l;;
.....

-)0-

9

Ao
~

U)

CO)

..""
CD
.....

tn

cr:

Logic Diagrams (Continued)
AS163

:i

c
.....
C"'I
CD
.....
(J)

14 OA

==
:i
""

c
....
.....

DATA A 3

..""
CD
.....

(J)

cr:

:i
C

.....
«:I
CD
.....

CLK

Q

DATA B 4

tn

==
""

:i
C

CLOCK

2
CLK

DATA C

CLEAR

LOAD

ENP

TUF/6291-5

3-48

.------------------------------------------------------------------.0
_

!!:

National

i....

Semiconductor
Corporation

G)

;

DM74AS168A, 169A
Synchronous Four Bit Up/Down Counters

o

!!:

General Description
These synchronous presettable counters feature an internal
carry look ahead for cascading in high speed counting applications. The AS168 is a four-bit decade up/down counter
and the AS169 is a four-bit binary up/down counter. The
carry output is decoded to prevent spikes during normal
mode of counting operation. Synchronous operation is provided so that outputs change coincident with each other
when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output counting
spikes which are normally associated with asynchronous
(ripple clock) counters. A buffered clock input triggers the
four flip-flops on the rising (positive going) edge of clock
input waveform.

the QA output when counting down. This low level overflow
carry pulse can be used to enable successively cascaded
stages. Transitions at the enable P or f inputs are allowed
regardless of the level of the clock input.

These counters are fully programmable; that is, the outputs
may each be preset either high or low. The load input circuitry allows loading with carry-enable output of cascaded
counters. As loading is synchronous, setting up a low level
at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.

• Switching Specifications at 50 pF
• Switching Specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts
• Synchronously programmable
• Internal look ahead for fast counting
• Carry output for n-bit cascading
• Synchronous counting
• Load control line
• ESO inputs

The carry look-ahead circuitry permits cascading counters
for n-bit synchronous applications without additional gating.
Both count enable inputs (is and 'f) must be low to count.
The direction of the count is determined by the level of the
up/down input. When the input is high, the counter counts
up; when low, it counts down. Input T is fed forward to enable the carry outputs. The carry output thus enabled will
produce a low level output pulse with a duration approximately equal to the high portion of the QA output when
counting up, and approximately equal to the low portion of

-...
~....

G)

~

The control functions for these counters are fully synchronous. Changes at control inputs (enable P, enable f, load,
up/down) which modify the operating mode have no effect
until clocking occurs. The function of the counter (whether
enabled, disabled, loading or counting) will be dictated solely by the conditions meeting the stable setup and hold
times.

Features

Connection Diagram
Dual-In-Llne Package
RIPPLE
CARRY
Vee OUTPUT QA

1

16

J1S

114

OUTPUTS
ENABLE

Os

Qc

1 J12
13

111

~

LOAD

1 10

9

~

RIPPLE QA
CARRY

Os

Oc

00

LOAD

UP/DOWN
CK
A

2

elK

E~E

T

OUTPUT

u/o

'f

00

ENABLE

B

3

4

ji

D

C

5

ABC

6
D

~----~----

7

Ie

ENABLE GND

ji

DATA INPUTS

Tl/F/6292-1

Order Number DM74AS168AN or DM74AS169AN
See NS Package Number N16A*
'Contact your local NSC representative about surface mount (M) package availability.

3-49

III

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "RecommemierJ Operating Conditions" table will define
the conditions for actual device operation.

7V

Input Voltage

7V

Operating Free Air Temperature Range
Storage Temperature Range

O"Cto +70"C
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vec

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-2

mA

10L

Low Level Output Current

fCLK

Clock Frequency

tsu

1setup, Set-up Time

tH

V

2

0

thold, Hold Time

20

mA

75

MHz

Data; A, S, C, 0

8

ns

EnP, EnT

8

ns

Load

8

ns

UfO

11

ns

Data; A, S, C, 0

0

ns

EnP, EnT

0

ns

Load

0

ns

UfO

0

ns

tWCLK

Width of Clock Pulse

6.7

tA

Free Air Operating Temperature

ns

0

·C

70

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

Symbol

Parameter

Conditions

=

Min

=

5V, T A

Typ

25·C

Max

Units

-1.2

V

VIK

Input Clamp Voltage

Vee = 4.5V, II

VOH

High Level Output
Voltage

10H = -2mA,
Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V,
10L = 20mA

II

Input Current @ Max
Input Voltage

Vee = 5.5V,
VIH = 7V

High Level Input Current

Vee = 5.5V,
VIH = 2.7V

[OAD,ENT,UfD

40

Others

20

VCC = 5.5V,
VIL = 0.4V

CLK, DATA, tNP
mAD, Ef\iT, UfO

IIH

IlL

Low Level Input Current

-18 mA

=

V

Vee- 2
0.35
LOAD, ENT, UfO

0.2

Others

0.1

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

Ice

Supply Current

Vee = 5.5V

-0.5

V
mA

/loA

rnA

-1
-30
46

3-50

0.5

-112

mA

63

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

fMAX

Max. Clock Freq.

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Conditions

From

Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

To

Min

Max

75

Units
MHz

Clock

Ripple
Carry

3

16.5

ns

Propagation Delay Time
High to Low Level Output

Clock

Ripple
Carry

2

13

ns

tpLH

Propagation Delay Time
Low to High Level Output

Clock

AnyQ

1

7

ns

tpHL

Propagation Delay Time
High to Low Level Output

Clock

AnyQ

2

13

ns

tpLH

Propagation Delay Time
Low to High Level Output

EnT

Ripple
Carry

1.5

9

ns

tpHL

Propagation Delay Time
High to Low Level Output

EnT

Ripple
Carry

1.5

9

ns

tpLH

Propagation Delay Time
Low to High Level Output

ufo
(Note 2)

Ripple
Carry

2

12

ns

Propagation Delay Time
High to Low Level Output

UfD
(Note 2)

Ripple
Carry

2

13

ns

tpHL

Note 1: See Section 1 for test waveforms and output load.
Note 2: Propagation delay time from up/down to ripple carry must be measured with the counter at enher a minimum or a maximum count. As the logic level of the
up/down input is changed, the ripple cany output will follow. If the count is minimum (0), the ripple carry output transition will be in phase. If the count is maximum
(9 for ASI68A or 15 for ASI69A), the ripple eeny output will be out of phase.

3·51

c(

en
~

Logic Diagrams

~
..,.

....

:Ii
Cl

i.....

DM74AS168A

u'~~~~~--------------------------------------~-----h

~
..,.

....

:Ii
Cl

DATA A

CLOCK

..::...------I~t==t=======[)
-'-----{:---f+t---t------------------;

....,..

4 BITOECAD£
UPfDQWN COUNTER

OA1A8

-'-------11~~=t1++=====L)

11

0'

OATAC

...!..-------4-1-+=I=1++:I==~:::..---,.....,

00

"" -"---..,.-t:>---.l+t-H++-II--LJ
DATA 0

..:'----jI:::C;;;:::::;:=t++~~+======:::[:~

'"'----=::j

TLlF/6292-2

3-52

.-------------------------------------------------------------'c
iii:

Logic Diagrams (Continued)

......

...~

DM74AS169A
UII

.... 1 ......

I

~

I

~I~J.-.
L

OATU

CLOCK

...l

3

2

~J-

-4-

4

190-..
L

....

,
ENP

DAUD

OA

...en~
~

..
.

~

.....

v

~

,........

~

6

J',

13

'V'Oa

~r-

~190-~~

5

9

14

F

~-

~

LOAD

Joo.

....

Lf=.

DAlAt

C

iii:
......

..

MAS 169
4 BIT BINARY
UP DOWN CDUNHA

omB

~

....

l~~r

.f)o....!!
F

oc

"

00

2::
EMf

10

........

-

15
RCO

J::

-I---..

I
TL/F/6292-3

3·53

~

r----------------------------------------------------------------------------,

~ rJ

r-.

:IE

NatiOnal

Semiconductor
Corporation

Q

,

DM74AS174 Hex 0 Flip-Flops with Clear
General Description

Features

These positive-edge-triggered flip-flops utilize TTL circuitry
to implement Ootype flip-flop logic. This device has an asynchronous clear input.

• Advanced oxide-isolated. ion-implanted Schottky TTL
process
• Pin and functional compatible with LS and Schottky
family counterpart
• Switching performance guaranteed over full temperature and Vee supply range

Information at the 0 inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either a high or low level. the 0 input signal has no effect at
the output.

Connection Diagram
VCC

Q6

D6

05

05

Function Table
D4

04

CLOCK

Output

Inpuls

CLEAR

Clock

D

Q

L

X

H
H
H

t
t

X
H

H

L

01

01

02

02

03

03

L

L

X

Qo

H - High logic State
L - Low logic
X = Either Low or High logic State
00 = The level of Q before the indlceted
steady-etate Input conditIonS were
established.
t = Transition from Low logic
Level to High Logic Level

s_

ClEAR

L

GND
TlIF/8655-1

Order Number DM74AS174N
See NS Package Number N16A'

'Contact your local NSC representative about surface mount (M) package avallebillty.

3-54

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors tor availability and specltlcatlons.
Supply Voltage
Input Voltage

Note: The "Absolute Msximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at th9selimits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute msximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V
7V

Operating Free Air Temperature Range
Storage Temperature Range

OOCto +700C
- 65·C to + 1500C

Recommended Operating Conditions
Symbol

Min

Nom

Max

Units

4.5

5

5.5

V

VIL

Low Level Input Voltage

0.8

V
mA

Paremeter

Vee

Supply Voltage

VIH

High Level Input Voltage

2

V

10H

High Level Output Current

-2

10L

Low Level Output Current

20

mA

feLOCK

Clock Frequency

100

MHz

tw

Pulse Width

0

I
J

Setup Time

lsetup

Clock High

4

Clock Low

6

CLEAR

5

Data

4

CLEAR Inactive

6

tHOLD

Data Input Hold Time

1

TA

Operating Free Air Temperature Range

0

ns

ns
ns

·c

70

Electrical Characteristics over recommended operating free air temperature range
Symbol

Parsmeter

Conditions

VIK

Input Clamp Voltage

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

II

Input Current at Maximum Input Voltage

IIH

High Level Input Current

IlL

Low Level Input Current

10

Output Drive Current
Supply Current

Icc
Note 2:

= 4.5V,11 = -18 mA
10H = Max, Vee = 4.5 to 5.5V
Vee = 4.5V, 10L = Max, VIH =
Vee = 5.5V, VI = 7V
Vee = 5.5V, VI = 2.7V
Vee = 5.5V, VI = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V (Note 2)

Min

Typ

Vee

Max

Units

-1.2

V

0.5

V

100

pA

20

pA

V

Vee- 2
0.35

2V

-30

-500

pA

-112

mA

45

mA

30

Icc is measured wHh 0 inputs and CUi grounded and eLK at 4.5V.

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Paremeter

From
(Input)

To
(Output)

fMAX

Maximum Clock Frequency

tpHL

Propagation Delay Time
High to Low Level Output

CLEAR

Q

tpLH

Propagation Delay Time
Low to High Level Output

Clock

tpHL

Propagation Delay Time
High to Low Level Output

Clock

Nota 1: See

Conditions

Min

Vee = 4.5V to 5.5V,
CL = 50pF,
TA = Min to Max,
RL = 500n

100

Max

Units
MHz

5

14

ns

Q

3.5

8

ns

Q

4.5

10

ns

Section 1 for test waveforms and output load.

3-55

II

Logic Diagram

01

2

3

01

CLOCK
CLEAR

~
02

5

4

02

CLOCK
CLEAR

~
03

7

6

03

CLOCK
CLEAR

~
04

10

11

04

CLOCK
CLEAR

~
05

12

13

05

CLOCK
CLEAR

~
06

CLOCK

14

15

9

06

CLOCK
CLEAR

CLEAR

1

~

"-

TL/F/8655-2

3·66

_

National

Semiconductor
Corporation

DM74AS175A Quad 0 Flip-Flops with Clear
General Description

Features

These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. This device has an asynchronous clear input.
Information at the 0 inputs meeting the setup time requirements is transferred to the 0 outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either a high or low level, the 0 input signal has no effect at
the output.

• Advanced Oxide-Isolated lon-Implanted Schottky TTL
process
• Pin and Functional compatible with LS and Schottky
family counterpart
• Switching performance guaranteed over full temperature and Vee supply range

Connection Diagram
D4
13

ClR

CLK

03
12

03

o

CLOCK

ClR

CLK

ClK

4
01

5
02

TUF/8856-1

Order Number DM74AS175AN
See NS Package Number N16A*

Function Table
Inputs

Outputs

CLEAR

Clock

D

Q

Q

L

X

L

H

H
H
H

t
t

X
H
L
X

H

= High logic State

l

=

L

H

L

L

H

00

00

low Logic State

00 =

The level 01 Q before the indicated steady-state input cond~ions were
established.

t = Transition from low Logic level to High Logic level

'Contact your local NSC representative about surface mount (M) package availability.

3-57

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot. be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guarant99d at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Operating Free Air Temp. Range

O"Cto +70"C

Storage Temperature Range

-65·C to + 150·C

Recommended 0p,erating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

IOH

High Level Output Current

-2

mA

2

IOL

Low Level Output Current

'CLOCK

Clock Frequency

tw

Pulse Width

Setup Time

!setup

V

0
Clock High

I
I

20

mA

100

MHz

4

Clock Low

5

Clear

5

Data

3

CLEAR Inactive

6

tHOLD

Data Input Hold Time

1

TA

Operating Free Air Temperature Range

0

ns

ns
ns

·c

70

Electrical Characteristics (over recommended operating free air temperature range)
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output Voltage

Conditions

Min

= 4.5V, II = -18 mA
IOH = Max, Vee = 4.5V to 5.5V
Vee = 4.5V, 10L = Max, VIH = 2V
Vee = 5.5V, VI = 7V
Vee = 5.5V, VI = 2.7V
Vee = 5.5V, VI = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V (Note t)

Typ

Vee

VOL

Low Level Output Voltage

II

Input Current at Maximum Input Voltage

IIH

High Level Input Current

IlL

Low Level Input Current

10

Output Drive Current

lee

Supply Current

.~".

Max

Units

-1.2

V
V

Vee - 2
0.35

-30
22.5

0.5

V

100

/LA

20

/LA

-500

/LA

-112

mA

34

mA

Note 1: Icc is measured with D inputs and CLEAR grounded, and clock at 4.5V.

Switchill$J Characteristics over recommended operating free air temperature range (Note 2)
.{
Symbol

..
..

Parameter

From
(Input)

To
(Output)

Conditions

Vee = 4.5V to 5.5V,
CL = 50pF,
RL = 500n,
TA = Minto Max

Min

Max

Units

\

fMAX

Maximum Clock Frequency

100

tpLH

Propagation Delay Time Low to High Level Output

CLEAij

Q

tpHL

Propagation Delay Time High to Low Level Output

CLEAR

Q

tpLH

Propagation Delay Time Low to High Level Output

Clock

QorQ

Propagation belay Time High to Low Level Output
tpHL
Note 2: See Section 1 for test waveforms and output load.

Clock

QorO
l

a-58

MHz

4

9

ns

4.5

13

ns

4

7.5

ns

4

10

ns

C
ii:

.....
,a::o.

Logic Diagram
01

4

2

~
....
.....
~

01

CLOCK
CLEAR

02

5

7

CLOCK
CLEAR

03

3

12

6

10

CLOCK
CLEAR

11

15

04

CLOCK

01

02
02

03
03

04

CLOCK
CLEAR

14

04

CLEAR
TUF/8656-2

&I
3·59

_National

Semiconductor

Corporation

DM74AS 181 B Arithmetic Logic
Unit/Function Generators
General Description

Features

These arithmetic logic units (ALU)/function generatore perform 16 binary arithmetic operations on two 4-bit words, as
shown in Tables I and II. These operations are selected by
the four function-select lines (SO, Sl, S2, 53) and include
addition, subtraction, decrement, and straight transfer.
When performing arithmetic manipulations, the internal carries must be enabled by applying a low-level voltage to the
mode control input (M). A full carry look-ahead scheme is
available in these devices for fast, simultaneous carry generalion by means of two cascade-outputs (P and G) for the
four bits in the package. When used in conjunction with the
DM74AS 182 full carry look-ahead circuits, high-speed arilhmelic operations can be performed. The typical addition
times shown in Table III illustrate how little time is required
for addition of longer words, when full carry look-ahead is
employed. The method of cascading AS182 circuits with
these ALU's to provide m\.llti-Ievel full carry look-ahead is
illustrated under typical applications data for the
DM74AS182.
(Continued)

• Arithmetic operating modes:
Addition
Subtraction
Shift operand A one position
Magnitude comparison
Plus twelve other arithmetic operations

Connection Diagram

Pin Designations

• Logie function modes:
EXCLUSIVE-OR
Comparator
AND, NAND, OR, NOR
Plus ten other logic operations
• Full look-ahead for high-speed operations on long
words
• Switching specifications guaranteed over full temperature and Vee range
• Switching specifications at 5000/50 pF
• Advanced oxide-isolated, ion-implanted Schottky TIL
process

Dual-In-Une Package
INPUTS

OUTPUTS

" ~ G Cn+4

i

vcc A1 B1
124

23

A2
22

A3 B3

B2
21

20

19

18

17

16

15 14

13

Pc

1
\

2
AO

3
53

4
52

5

.

51

INPUTS

6

7

so Cn

8
M

9
FO

',

PlnNos.

Function

19,21,23,2

Word A Inputs

B3, B2, B1, BO

18,20,22,1

Word B Inputs

S3, S2, Sl, SO

3,4,5,6

Function-Select
Inputs

Cn

7

Inv. Carry Input

M

8

Mode Control
Input

F3,F2,F1,FO

13,11,10,9

Function Outputs

A=B

14

Comparator Output

j5

15

Carry Propagate
Output

Cn+4

16

Inv. Carry Output

C3

17

Carry Generate
Output

Vee

24

Supply Voltage

GND

12

Ground

\

P A=B F3

roC

BO

Designation
A3, A2, Al, AO

10
F1

11 112
F2 GND
i

OUTPUTS
TUF/6295-1

Order Number DM74AS181BN, NT
See NS Package Number N24A or N24C

3-60

CI

~
.....

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Off-State Output Voltage (A = B only)
7V
Operating Free Air Temperature Range
O'Cto +70'C
Storage Temperature Range
- 65'C to + 150'C

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

~
.....
CO
.....

m

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

10H

High Level Output
Current

10L

Min

Nom

Max

Units

4.5

5

5.5

V

0.8

V

V

2
All Outputs Except
A = BandG

-2

G

-3

Low Level Output

All Outputs Except G

20

Current

G

48

VOH

High Level Output Voltage,
(A = BOnly)

TA

Free Air Operating Temperature

mA

0

mA

5.5

V

70

'C

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25'C.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

-1.2

V

VIK

Input Clamp Voltage

Vee = 4.5V,II = -18 rnA

VOH

High Level Output
Voltage

IOH=-2mA

Any Output
Except A = B

= -3mA
Vee = 4.5V,
VOH = 5.5V

G

Vee = 4.5V,
10L = 20mA

Any Output
ExceptG

0.3

0.5

G

0.4

0.5

10H

10H

High Level Output
Current (A = B)

VOL

Low Level Output
Voltage

10L
II

IIH

IlL

Input Current @ Max
Input Voltage

High Level Input
Current

Low Level Input
Current

= 48mA

Vee = Max,
VIH = 7V

Vee = Max,
VIH = 2.7V

Vee = Max,
VI = 0.5V

Vee - 2
2.4

V
3.4
100

V

Mode

0.1

AnyAorB

0.3

S

0.4

Carry

0.6

Mode Input

20

AnyS Input

80

Any A or B Input

60

Carry Input

120

Mode Input

-0.5

AnyS Input

-2

AnyAorB
Input

-1.5

Output Drive Current

Vee = 5.5V

lee

Supply Current

Vee = 5.5V

Vo = 2.25V

-30
70

3-61

mA

/LA

mA

-2.5

Carry Input
10

/LA

-112

rnA

104

rnA

II

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH.

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay TIme,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL
tpLH

Propagation Delay Time,
High-to-Low Level Output
Propagation Delay Time,
Low-to-High Level Output

tPHL

Propagation Delay TIme,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay TIme,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-ta-Low Level Output

Conditions
(Note 2)

From
(Input)

(Output)

Cn

Cn+4

M = OV,
SO = S3 = 4.5V
S1 = S2 = OV
(SUM mode}

Any A
orB

M= OV,
SO=S3=OV
S1 = S2 = 4.5V

Any A
orB

To

Cn

M= OV,
SO = S3 = 4.5V
S1 = S2 = OV
(SUM mode}

Any A
orB

M = OV,
SO = S3 = OV
S1 = S2 = 4.5V
(DIFFmode)

Any A
orB

M=OV,
SO = S3 = 4.5V
S1 = S2 = OV
(SUM mode}

Any A
orB

M = OV,
SO=S3=OV
S1 = S2 = 4.5V

Any A
orB

M = OV,
SO=S3=OV.
S1 = 82 = 4.5V
(DIFFmode)
M = 4.5V
(logic mode)

Aj or BI

Ai or BI

Aj or Bj

M = OV,
80=83=OV
81 = 82 = 4.5V
(l>iFF mode)

Any A
orB

Note 1: See Section 1 for test wavefonna and outpulloed.
Note 2: Vee = 4.5V to 5.5V. CL = 50 pF (15 pF for A = B). RL = 5000 (2800 for A

3-62

= B).

2

9

2

9

2

12

2

12

2

16

2

16

3

9

3

9

2

7

2

7

2

9

2

9

2

8

2

8

2

10

2

10

2

8

2

8

2

10

2

10

2

11

2

11

4

21

4

21

ns

ns

AnyF

ns

G

ns

G

ns

ns

P

ns

P

FI

Fj

Fj

Units

ns

Cn+4

(~mode)

M= OV,
SO = S3 = 4.5V
S1 = S2 = OV
(SUM mode}

Max

Cn +4

(~mode)

M =OV
(SOMor
DIFFmode)

Min

ns

ns

ns

A=B

ns

C
i:

Dynamic Parameter Measurement Information

.....

logic Mode Test Table
Function Inputs: S1 = S2 = M = 4.5V, SO = S3 = OV

Parameter

tpLH

Input
Under
Test

Other Input
Same Bit

Other Data Inputs

tpLH

Apply
4.5V

Apply
GND

Aj

BI

None

None

Remaining
A and B, Cn

Fj

Out·ol-Phase

Bj

Ai

None

None

Remaining
A and B, Cn

Fj

Out-ol-Phase

Output
Under
Test

Output
Waveform

SUM Mode Test Table
Function Inputs: SO = S3 = 4.5V, S1 = S2

tpLH

Input
Under
Test

Other Input
Same Bit

Other Data Inputs

Apply
GND

Apply
4.5V

Apply
GND

Aj

Bj

None

Remaining
AandB

Cn

Fj

In-Phase

Bj

Aj

None

Remaining
AandB

Cn

Fj

In-Phase

Aj

Bj

None

None

Remaining
A and B, Cn

P

In-Phase

Bj

Aj

None

None

Remaining
AandB,C n

P

In-Phase

Aj

None

Bj

Remaining
B

Remaining
A,Cn

G

In-Phase

Bj

None

Aj

Remaining
B

Remaining
A,Cn

G

In-Phase

Cn

None

None

All
A

All
B

AnyF
orC n +4

In-Phase

Ai

None

Bj

Remaining
B

Remaining
A,C n

Cn +4

Out-ol-Phase

Bj

None

Aj

Remaining
B

Remaining
A,C n

Cn +4

Out-ol-Phase

tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL

= M = OV

Apply
4.5V

tpHL
tpLH

Output
Waveform

Apply
GND

tpHL

Parameter

Output
Under
Test

Apply
4.5V

tpHL

~....
....
m

C»

II
3-63

Dynamic Parameter Measurement Information (Continued)
DIFF Mode Test Table
Function Inputs: S1 = S2 = 4.SV, SO = S3 = M = OV

Parameter

Input
Under
Test

Other Input
Same Bit
Apply

4.SV
tpLH

Apply
GND

4.SV

Remaining
B,Cn

Fj

In-Phase

None

Bj

Bj

A;

None

Remaining
A

Remaining
B,Cn

Fj

Out-of-Phase

Aj

None

Bj

None

Remaining
AandB, Cn

P

In-Phase

Bj

Aj

None

None

Remaining
AandB, Cn

P

Out-of-Phase

Aj

Bj

None

None

Remaining
AandB,Cn

G

In-Phase

Bj

None

AI

None

Remaining
A and B,C n

G

Out-of-Phase

AI

None

Bj

Remaining
A

Remaining
B,Cn

A=B

In-Phase

Bj

Aj

None

Remaining
A

Remaining
B,Cn

A=B

Out-of-Phase

Cn

None

None

All
AandB

None

Cn +4
or any F

In-Phase

Aj

Bj

None

None

Remaining
A,B,Cn

Cn +4

Out-of-Phase

Bj

None

AI

None

Remaining
A,B,C n

Cn +4

In-Phase

tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH

Output
Waveform

Apply
GND

A;

tpHL
tpLH

Apply

Output
Under
Test

Remaining
A

tpHL
tpLH

Other Data Inputs

tpHL

3-64

General Description (Continued)
(2) (1)

,, ,,

(23)(22) (21) (20) (19) (18)

I I II

AO 80
(7)_P-< c"

A1 B1

A2 B2

AS181 B or 5181
(8)- I--

•FO F1
(t (1~)
(3)1(4)
YO XO

(1~

F2

F3

(J1) (1'3)

A=B -(14)

Cn+4

Y X

(I)

1/17 (15)

TT'r)(r
Y1 X1

A3 B3

Y2 X2

TT

Y3 X3
X 1--/7)

AS182

c"
c,,+x

c,,+y

(X)

(X)
FIGURE

Y 1--(10)
c,,+.

1

Jl

TUF/6295-2

TABLE I
Active High Data

selection

S3

S2

S1

SO

M=H
logic
Functions

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

F=A
F=A+B
F=AB
F=O
F=AB
F=S
F=AEBB
F= AS
F=A+B
F=AEBB
F=B
F=AB
F= 1
F=A+8
F=A+B
F=A

M = L; Arithmetic Operations

Cn = H (no carry)

Cn = L (with carry)

F=A
F=A+B
F=A+S
F = Minus (2's Compl)
F = APlusAB
F = (A + B) Plus AS
F = A Minus B Minus 1
F = AS Minus 1
F = A PlusAB
F = A Plus B
F = (A + B) PlusAB
F = ABMinus 1
F = APlusAo
F = (A + B) Plus A
F = (A + S) Plus A
F = A Minus 1

F=APlusl
F=(A+B)Plusl
F=(A+S)Plus1
F = Zero
F = A PlusAB Plus 1
F = (A + B) Plus AS Plus 1
F = A Minus B
F= AS
F = A Plus AB Plus 1
F=APlusBPlus1
F = (A + 8) PlusAB Plus 1
F= AB
F=APlusAPlus1
F = (A + B) Plus A Plus 1
F = (A + '1:1) Plus A Plus 1
F=A

1

'Each bn is shifted to the next more significant position.

Cfn

Output
Cn +4

Active-High Data
(FIgure 1)

H
H
L
L

H
L
H
L

As:B
A>B
A-(7)

AS182

Cn

G 0-(10)
Cn+ x
(1t

Cn+ v

Cn+z

),)

(!)

TL/F/6295-3

FIGURE 2
TABLEU
Active Low Data

Selection

63

62

61

60

M=H
Logic
Functions

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

F=A
F= AB
F=A+B
F=1
F=A+B
F=S
F=AeB
F=A+S
F= AB
F=AeB
F=B
F=A+B
F=O
F= AS
F= AB
F=A

M = L; Arithmetic Operations
Cn = L (no carry)

Cn = H (with carry)

F = A Minus 1
F = ABMinus 1
F = ABMinus 1
F = Minus 1 (2's Compl)
F = A Plus (A + S)
F= ABPlus(A + B)
F = A Minus B Minus 1
F=A+S
F = A Plus (A + B)
F = A Plus B
F = AS Plus (A + B)
F=A+B
F=APlusA*
F = AB Plus A
F = AS Plus A
F=A

F=A
F= AB
F= AS
F = Zero
F = A Plus (A + S) Plus 1
F = AB Plus (A + S) Plus 1
F = AMinusB
F=(A+S)Plus1
F = A Plus (A + B) Plus 1
F=APlusBPlus1
F = AS Plus (A + B) Plus 1
F=(A+B)Plus1
F = A Plus A Plus 1
F = AB Plus A Plus 1
F =AS Plus A Plus 1
F=APlus1

'Each bR is shifted to the next more significant position.

Pin Number

I

2

I

1

Input
Cn

Output
Cn +4

Active-Low Data
(Flgurtl2)

H
H
L
L

H
L
H
L

A~B

AB
A:s:B

I 23 I 22 I 21 I 20 I 19 I 111 I

9

Active-Low Data (Table II) 1 AO 1 BO 1 A1 1 B1 1 A2 1 S2 1 A3 1 B3 1 FO

~-66

10

I 11 I 13 I

7

I

16

I 15

1 17

F1 1 F2 1 F3 1 Cn 1 Cn+4 1- P 1

~

General Description (Continued)
If high speed is not important, a ripple-carry input (Cn) and a
ripple-carry output (Cn+4) are available. However, the ripple-carry delay has also been minimized so that arithmetic
manipulations for small word lengths can be performed
without external circuitry.
.

relative magnitude information. Again, the ALU should be
placed in the subtract mode by placing the function select
inputs 53, 52, 51, SO at L, H, H, L, respectively.
These circuits have been designed to not only incorporate
all of the designer's requirements for arithmetic operations,
but also to provide 16 possible functions of two Boolean
variables without the use of external circuitry. These logic
functions are selected by use of the four function-select inputs (SO, 51, 52, 53) with the mode-control input (M) at a
high level to disable the intern!!1 carry. The 16 logic functions are detailed in Tables I and II and include exclusiveOR, NAND, AND, NOR, and OR functions.

These circuits will accommodate active-high or active-low
data, if the pin designations are interpreted as shown below.
Subtraction is accomplished by 1's complement addition,
where the 1's complement of the subtrahend is generated
internally. The resultant output is A-B-1, which requires
an end-around or forced carry to provide A-B.
The A5181B can also be utilized as a comparator. The A =
B output is internally decoded from the function outputs (FO,
F1, F2, F3) so that when two words of equal magnitude are
applied at the A and B inputs, it will assume a high level to
indicate equality (A = B). The ALU should be in the subtract
mode with Cn = H when performing this comparison. The
A = B output is open-collector so that it can be wire-AND
connected to give a comparison for more than four bits. The
carry output (Cn +4) can also be used to supply

ALU SIGNAL DESIGNATIONS
The TTL 5181 and A5181B can be used with the signal
designations of either Figure 1 or Figure 2.
The logic functions and arithmetic operations obtained with
Signal designations as in Figure 1 are given in Table I; those
obtained with the signal designations of Figure 2 are given
in Table II.

TABLE III
Number
of
Bits

Typical Addition
Times Using
AS181B & AS882

Arlthmetlcl
Logic Units

Package Count
Look Ahead
Carry Generators

Carry Method
Between
ALU's

1 t04
5t08
9to 16
17to64

5ns
10 ns
14 ns
101 ns

1
2
30r4
5to 16

0
0
1
2to 5

None
Ripple
Full Look-Ahead
Full Look-Ahead

3-67

CD
~

....
:l....

Logic Diagram

::Ii!

151
III

CD

.....

Q

I"

S3 (4)

!:
.so

Goo_
(17)

'3

118)

.3

(15) C.+4

(15)

....

1131

.3

"9)

i.
(20)

,iI(231
----i-++t---t

~~~~I::>-t1r--------11~~L-L--~.,
"0t

io-4~~~~~--+-t
I"

, , -....--,::::., '0
io~..~,------~--i
Vcr;

M~'8~'-~~-------------------~

c.----------------------_________________

GND

= PIN 24
= PIN 12

--J

'71

TUF/6295-4

3-68

•

NaHonal

Semiconductor
CorporaHon

DM74AS 182 Look-Ahead Carry Generators
General Description
These circuits are high-speed, look-ahead carry generators,
capable of anticipating a carry across four binary adders or
groups of adders. They are cascadable to perform full lookahead across n-bit adders. Carry, generate-carry, and propagate-carry functions are provided as shown in the pin designation table.
When used in conjunction with the AS181B arithmetic logic
unit, these generators provide high-speed carry look-ahead
capability for any word length. Each AS182 generates the
look-ahead (antiCipated carry) across a group of four ALUs
and, in addition, other carry look-ahead circuits may be employed to anticipate carry across sections of four lookahead packages up to n-bits. The method of cascading circuits to perform multi-level look-ahead is illustrated under
typical application data.

compatible with the look-ahead generator. Positive logic
equations for the AS182 are:
Cn+x
Cn + y
Cn + z
G

= GO+PO Cn
= Gl +Pl GO+Pl PO Cn
= G2+ P2 Gl + P2 PI GO+ P2 PI PO Cn
= G3+P3.G2+P3.P2.Gl+P3.P2.Pl.GO

15 = P3 P2 PI PO

Features

Carry input and output of the ALUs are in their true form,
and the carry propagate (P) and carry generate (G) are in
negated form; therefore, the carry functions (inputs, outputs,
generate, and propagate) of the look-ahead generators are
implemented in the compatible forms for direct connection
to the ALU. Reinterpretations of carry functions, as explained on the 181 data sheet are also applicable to and

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Offers carry functions in a compatible form for direct
connection to the ALU
• Cascadable to perform look-ahead across n-bit adders
• PNP inputs reduce input loading
• Improved AC performance over Schottky at reduced
power consumption

Connection Diagram

Pin Designations
DeSignation

Dual·ln·Llne Package
INPUTS

,
vcc

P2

116

15

G2

,
Cn

14

13

OUTPUTS

,

c n+x c n+y
12

11

,

10

,

9

f-

1

2
PI

3

Go

4

Po

5
03

7

8

P3

Function

GO, Gl, G2, G3

3,1,14,5

Active Low
Carry Generate Inputs

PO, PI, 152, 153

4,2,15,6

Active Low
Carry Propagate Inputs

Cn

13

Carry Input

Cn+x,Cn+ y,
Cn+ z

12,11,9

Carry Outputs

G

10

Active Low
Carry Generate Output

15

7

Active Low
Carry Propagate Output

Vee

16

Supply Voltage

GND

8

Ground

Cn+z

G

-<

Gl

Pin Nos.

'ji

18
GND

, OUTPUT
INPUTS

TLlF/6296-1

Order Number DM74AS182N
See NS Package Number NI6A·

II
'Contact your local NSC representative about surface mount (M) package availability.

3·69

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarant88d. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

5.5V
O"Cto +70"C
- 65·C to + 150"C

Recommended Operating Conditions
Symbol

Parameter

Min

Typ

Max

Units

4.5

5

5.5

V

VIL

Low Level Input Voltage

O.S

V

Vee

Supply Voltage

VIH

High Level Input Voltage

2

V

10H

High Level Output Current

-2

mA

10L

Low Level Output Current

20

mA

TA

Free Air Operating Temperature Range

70

·C

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

II

Input Current at Max
Input Voltage

IIH

IlL

High Level
Input Current

Low Level
Input Current

Conditions

= 4.5V,11 = -1S mA
10H = -2mA
Vee = 4.5V, 10L = 20 mA
Vee = 5.5V, VIH = 7V

=

Min

5V, TA
Typ

Vee

=

=

Max, VI

Max, VI

=

=

2.7V

0.4V

0.35

Vee

Supply Current

Vee

=
=

5.5V, Vo

=

P3

200
300

PO, P1, G3

400

GO,G2

700

G1

SOO

Cn

60

P3

40,

P2

60

PO, P1, G3

SO

GOorG2

140

G1

160

Cn

-1.5

P3

-1

P2

-1.5

3-70

V

".A

".A

mA

-3.5
-4
-112

Outputs High (1)

16

25

Outputs Low (2)

23

36

Note 1: ICCH Is measured with all outputs open, Inputs P3 and G3 at4.5V, and all other Inputs grounded.
Note 2: ICCl Is measured with all outputs open, inputs GO, GI, and G2 at 4.5V, and all other inputs grounded.

V

-2

-30

2.25V

5.5V

0.5

Cn, P2

G1
Output Drive Current

Units

V

GOorG2

Icc

Max

Vee- 2

PO, P1,G3

10

25·C.

-1.2

Vee

Vee

=

mA
mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

From
(Input)

To
(Output)

Conditions

GO,G1,
G2,G3,
Po, P1,
P2,orPa

c,,+x,
Cn+ y,
orc,,+z

Vee = 4.5V to 5.5V,
CL = 50pF,
RL = 5000

G

P

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

GO,G1,
G2,G3,
P1, P2,
orP3

tpLH

Propagation Delay Time,
Low to High Level Output

PO, P1,
P2,orPa

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

c"

Propagation Delay Time,
High to Low Level Output
Note 1: See Section 1 for test waveforms and output load.

tpHL

Min

Max

2SoC,SV
Max

Units

3

10.5

9.5

ns

2

6

6

ns

3

12

11

ns

2

8

7.5

ns

2

7.5

7

ns

2

6

5.5

ns

3

10

9

ns

3

9.5

9

ns

Cn+ x,
Cn+ y,
orc,,+z

Function Tables
Output

Inputs

GS

G2

G1

GO

PS

P2

P1

G

PSlp21p11PO

L
X
X
X

X
L
X
X

X
X
L
X

X
X
X
L

X
L
L
L

X
X
L
L

X
X
X
L

L
L
L
L

Inputs

All Other Combinations

I

L

I

L

Output

I

L

P
L

L

All Other Combinations

H

H
Inputs

Inputs

OUtput

G2

G1

GO

P2

P1

PO

Cn

Cn+ z

L
X
X
X

X
L
X
X

X
X
L
X

X
L
L
L

X
X
L
L

X
X
X
L

X
X
X
H

H
H
H
H

All Other Combinations

Po

Cn

Cn+ x

L
X

X
L

X
H

H
H

All Other Combinations

L

Inputs

L

H = High level. L = Low level, X = Irrelevant
Arry Inputs not shown in a given table are irrelevant with respect to

Output

Go

that

output.

Output

G1

GO

P1

PO

Cn

Cn + y

L
X
X

X
L
X

X
L
L

X
X
L

X
X
H

H
H
H

All Other Combinations

S·71

L

CN

CIO

~.....

Logic Diagram

::IE

(7)

P

Q

P2 (15)

G2---+-r--~~~-r~-I
(14)

PI (2)

Gl-(~I-)+------r~--~--~

Po

(4)

GO (3)
Cn (13)

Vee

~

PIN 16

GND

~

PIN 8
TLlF/6296-2

Typical Application
64-Bit ALU, Full-carry Look-Ahead In Three Levels
'ASI82, AS881

A and B Inpuls and F oulputs of ASI 81 B are nol shown.

TLlF/6296-3

3·72

.-------------------------------------------------------------------,0
a=

National

_

i

Semiconductor
Corporation

DM74AS230/DM74AS231
TRI-STATE® Bus Drivers/Receivers

i.....

General Description

Features

This family of Advanced Schottky TRI·STATE Bus circuits
are designed to provide either bidirectional or unidirectional
buffer interface in Memory, Microprocessor, and Communication Systems. The output characteristics of the circuits
have low impedance sufficient to drive terminated transmission lines down to 133 ohms. The input characteristics of
the circuits likewise have a high impedance so it will not
significantly load the transmission line. The package con·
tains eight TRI·STATE buffers organized with four buffers
having a common TRI·STATE enable gate. The AS230 is
organized as 4 bit buffers inverting and 4 bit buffers non
inverting. The AS231 is organized as two 4 bit wide inverting
buffers with separate complementary output control buffers.

• Advanced oxide·isolated, ion·implanted Schottky TTL
process
• Improved switching performance over low power
Schottky counterpart
• Functional and pin compatible with low power Schottky
counterpart
• Switching response specified into 500n and 50 pF
• Low level drive current 74AS = 48 mA
• Specified to interface with CMOS al VOH = Vee - 2V

Connection Diagrams
Dual-In-Une Package

Dual-In-Une Package

vce 20

lOlA 1

2Y4

lA2

2Y3

lA3

2Y2

lA4

lY4 2Al

Vee 2G

2Yl GNU

10

lAl

2Y4

lA2

2Y3

lA3

lY3

2A2

lY4

2Y2

lA4

2Yl GND

TlIF/6297-1

2A 1

TlIF/6297-2

Order Number DM74AS230N
See NS Package Number N20A'

Order Number DM74AS231N
See NS Package Number N20A'

Function Tables
'AS230
Inputs

H~
L~
X~
Z~

'AS231
Outputs

G

A

1Y

L
L
H

L
H
X

Inputs

2Y

1G

H

L

L

H

L
L

Z

Z

H

1A

'AS231
Output
1Y

L

H

H
X

L
Z

High Logic Level
Low Logic Level
Either Low or High Logic Level
High Impedance (off)

'Contact your local NSC representative about surface mount (M) package availability.

3-73

Inputs
2G

H
H
L

2A

Output
2Y

L

H

H
X

L
Z

~

....

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
O·Cto +70"C
Storage Temperature Range
-65·C to + 150"C

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guara"..
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

DM74AS 230, 231

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

Min

Nom

Max

4.5

5

5.5

Units

V

2

V

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-15

mA

-64

mA

70

·c

10L

Low Level Output Current

TA

Free Air Operating Temperature

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Conditions

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

II

Input Current at Max
Input Voltage

IIH
IlL

= 4.5V,IIN = -18 mA
10H = Max, Vee = 4.5V
10H = -2mA, Vee = 4.5Vto5.5V
Vee = 4.5V, 10L = Max

Typ

Vee

Vee

= 5.5V, VIN = 7V

High Level Input Current

Vee

= 5.5V, VIN = 2.7V

Low Level Input Current

Vee = 5.5V
VIN = 0.4V
Vee

= 5.5V, Vo = 2.7V

10Zl

Low Level TRI-STATE
Output Current

Vee

= 5.5V, Vo = O.4V
= 5.5V, VOUT = 2.25V
Outputs High
= 5.5V

10

Output Drive Current

Vee

Icc

74AS230
Supply Current

Vee

74AS231
Supply Current

Vee

= 5.5V

Units

V
V

Vee- 2

V
0.35

0.55

V

0.1

mA

20

p.A

-0.5

-50

50

p.A

-50

p.A

-150

mA

16

25

Outputs Low

55

87

TRI-STATE

29

46

Outputs High

12

18

Outputs Low

52

82

TRI-STATE

25

39

3-74

mA

-1

AS230 2A Inputs

High Level TRI-STATE
Output Current

Max

-1.2
2.4

Others

10ZH

lee

Min

= 5V, TA = 25·C.

mA

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

tpLH

Parameter

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

tpLH

Propagation Delay Time
Low-to-High Level Output

From
(Input)

1A

2A

To
(Output)

1Y

Conditions

Vee = 4.5V to 5.5V
RL = soon
CL = 50pF

DM74AS230
Min

Max

2.5

6.5

2

5.7

2.5

6.2

2

6.2

ns

2Y

ns

tpHL

Propagation Delay Time
High-to-Low Level Output

tPZH

Output Enable to High Level

2

6.4

tpZL

Output Enable to Low-Level

2

8.5

tpHZ

Output Disable from i'Ugh Level

2

5

tpLZ

Output Disable from Low Level

2

9.5

tPZH

Output Enable to High Level

2

9

tpZL

Output Enable to Low Level

2

7.5

tpHZ

Output Disable from High Level

2

6

tpLZ

Output Disable from Low Level

2

9

1G

2G

Units

1Y

2Y

ns

ns

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

tpLH

Parameter

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

From
(Input)

A

To
(Output)

Y

Conditions

Vee = 4.5V to 5.5V
RL = soon
CL = 50pF

DM74AS231
Min

Max

2

6.5

2

5.7

.-

ns
I

tPZH

Output Enable to High Level

2

6.4

tPZL

Output Enable to Low Level

2

8.5

tpHZ

Output Disable from High Level

2

5
9.5

G

Y

IpLZ

Output Disable from Low Level

2

tpZH

Output Enable to High Level

3

6

tPZL

Output Enable to Low Level

3

9

tpHZ

Output Disable from High Level

3

6

tpLZ

Output Disable from Low Level

3

7

G

Y

Note 1: See Section 1 for test waveforms and output load.

3-75

Units

ns

ns

~

~

~....
c
==
.....

,----------------------------------------------------------------------------,
National
Semiconductor
Corporation

_

~

DM74AS240, 241, 242, 243, 244
TRI-STATE® Bus Drivers/Receivers

::E

General Description

Features

~

This family of Advance Schottky TRI-STATE Bus circuits are
designed to provide either bidirectional or unidirectional
buffer interface in Memory, Microprocessor, and Communication Systems. The output characteristics of the circuits
have low impedance sufficient to drive terminated transmission lines down to 133 ohms. The input characteristics of
the circuits likewise have a high impedance so it will not
significantly load the transmission line. The package contairis eight TRI-STATE buffers organized with four buffers
having a common TRI-STATE enable gate. The AS240, 241
and 244 are eight wide in a 20 pin package, and may be
used as a 4 wide bidirectional or eight wide unidirectional.
The AS242 and 243 are organized four wide bidirectional in
a 14 pin package. The buffer selection includes inverting
and non-inverting, with enable or disable TRI-STATE control.

• Advanced oXide-isolated, ion-implanted Schottky TIL
process
• Improved switching performance with less power dissipation compared with Schottky counterpart
• Functional and pin compatible with 54/74LS and
Schottky counterpart
• Switching response specified into 500 ohm and 50 pF
• Specified to interface with CMOS at VOH = Vee - 2V

~....
C

~

~....

::E
C

......
.,...
~

~....

:::IE

C
.....

~

~....
::E

Connection Diagrams

C

Dual-In-Llne Package

lG

Dual-In-Line Package

20

1Yl

2A4

lY2

2A3

1Y3

2A2

lY4 2Al

lA 1

2Y4

lA2

2Y3

lA3

2Y2

lA4

2Yl GNO

vcc 2G

lG

lAl

lY 1

2A4

lY2

2A3

1Y3

2A2

1Y4

2A 1

2Y4

lA2

2Y3

lA3

2Y2

lA4

2Yl GND
TL/F/629B-2

TLlF/6298-1

Order Number DM74AS241N
See NS Package Number N20A·

Order Number DM74AS240N
See NS Package Number N20A·

'Contact your local NSC representative about surface mount (M) package availability.

3-76

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vee
7V
Input Voltage
7V
Voltage Applied to Disabled Output
5.5V
Operating Free Air Temperature Range
O·C to + 70·C
Storage Temperature Range
- 65·C to + 1500C

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V
mA

V

2

IOH

High Level Output Current

-15

IOL

Low Level Output Current

64

mA

TA

Free Air Operating Temperature

70

·C

o

Connection Diagrams (Continued)
Dual·ln·Line Package

Dual·ln·Llne Package
Vee

GSA

Ne

18

28

38

4B

vee

GBA

Ne

lB

2B

3B

4B

GAB

Ne

lA

2A

3A

4A

GND

GAB

Ne

lA

2A

3A

4A

GND

TLlF/6298-4

TL/F/6298-3

Order Number DM74AS243N
See NS Package Number N14A *

Order Number DM74AS242N
See NS Package Number N14A*
Dual·ln·Line Package
vee 2G

lYl

2A4

lY2 2A3

lY3

2A2

lG

2Y4

lA2

2Y3

2Y2

lA4 2Yl GND

lAl

IA3

lY4 2Al

TLlF/6298-5

Order Number DM74AS244WM, N
See NS Package Number M20B or N20A
'Contact your local NSC representative about surface mount (M) package availability.

3-77

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25°C.

Symbol

Parameter

Conditions

Min

VIK

Input Clamp Voltage

Vee = 4.5V, liN = -18 mA

VOH

High Level Output
VoHage

Vee = 4.5V, 10H = -3 mA

2.4

Vee = 4.5V,IOH = Max

2.4

10H = -2mA, Vee = 4.5Vto5.5V
VOL

Low Level Output
Voltage

Vee = 4.5V,IOl = Max

II

Input Current at Max
Input Voltage

Vee = 5.5V

VIN = 7V

IlL

High Level Input Current

Low Level Input Current

Vee = 5.5V, VIN = 2.7V

Vee = 5.5V, VIN = 0.4V

IOZH

High Level TRI-STATE
Output Current

Vee = 5.5V, V= 2.7V

IOZl

Low Level TRI-STATE
Output Current

Vee = 5.5V, V = 0.4V

V

AS242,243
(A or B)

70

Others

20

AS240, 241
(G,m,242,
243 (Control
Inputs),
244(6)

-500

AS241 (A),
243 (A or B),
244 (A)

-1000

Icc

Icc

54174AS243
Supply Current

Vee = 5.5V

54174AS244
Supply Current

Vee = 5.5V

/-LA

-500
-50

/-LA

-1000
-150
17

Outputs Low

51

75

-50

TRI-STATE

24

38

Outputs High

22

35

Outputs Low

61

90

TRI-STATE

35

56

A Port Outputs High

18

28

A Port Outputs Low

38

60

TRI-STATE

25

39

A Port Outputs High

28

44

A Port Outputs Low

47

74
56

TRI-STATE

35

Outputs High

22

34

Outputs Low

60

90

TRI-STATE

34

54

3-78

p.A

p.A

11

lee

Vee = 5.5V

p.A

Outputs High

Vee = 5.5V

54174AS242
Supply Current

100

-115

54/74AS240

lee

V

For AS242,
243 (A or B)

AS243
Vee = 5.5V, VOUT = 2.25V

Vee = 5.5V

0.55

Others

AS242

Output Drive Current

54174AS241
Supply Current

V

50

10

lee

Units

Vee- 2

AS240,241,
244

Supply Current

Max
-1.2

3.2

0.35

VIN = 5.5V
IIH

Typ

mA
mA

mA

mA

mA

mA

'AS240 Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions
Vee = 4.5V to 5.5V
R, = R2 = 500n
CL = 50pF

From
(Input)

To
(Output)

Min

Max

Units

A

Y

2

6.5

ns

A

y

2

5.7

ns
ns

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

tPZL

Output Enable to Low Level

G

y

2

9

tPZH

Output Enable to High Level

G

Y

2

6.4

ns

tpLZ

Output Disable from Low Level

G

Y

2

9.5

ns

tpHZ

Output Disable from High Level

G

y

2

5

ns

'AS241 Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions
Vee = 4.5V to 5.5V
R, = R2 = 500n
CL = 50pF

From
(Input)

To
(Output)

Min

Max

Units

A

Y

2

6.2

ns

A

y

2

6.2

ns

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

tPZL

Output Enable to Low Level

1G

Y

2

7.5

ns

tPZH

Output Enable to High Level

1G

Y

2

9

ns

1G

Y

2

9

ns

tpLZ

Output Disable from Low Level

tpHZ

Output Disable from High Level

1G

Y

2

6

ns

tPZL

Output Enable to Low Level

2G

Y

3

8.5

ns

tPZH

Output Enable to High Level

2G

Y

3

10.5

ns

tpLZ

Output Disable from Low Level

2G

Y

3

12

ns

tpHZ

Output Disable from High Level

2G

Y

3

7

ns

'AS242 Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

tPZL

Output Enable to Low Level

Conditions
Vee = 4.5V to 5.5V
R, = R2 = 500n
CL = 50pF

From
(Input)

To
(Output)

Min

Max

Units

AorB

BorA

2

6.5

ns

AorB

BorA

2

5.7

ns

GBA

A

3

8

ns

6

ns
ns

tPZH

Output Enable to High Level

GBA

A

3

tpLZ

Output Disable from Low Level

GBA

A

3

10.5

tpHZ

Output Disable from High Level

GBA

A

3

6

ns

tPZL

Output Enable to Low Level

GAB

B

2

7.5

ns

tPZH

Output Enable to High Level

GAB

B

2

5.5

ns

tpLZ

Output Disable from Low Level

GAB

B

2

9.5

ns

tpHZ

Output Disable from High Level

GAB

B

2

6.5

ns

3-79

'AS243 Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

<

From
(Input)

To
(Output)

Min

Max

Units

AorB

BorA

3

7.5

ns

AorB

BorA

3

6.5

ns

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

tpZL

Output Enable to Low Level

GAB

B

2

7.5

ns

tpZH

Output Enable to High Level

GAB

B

2

9

ns

tpLZ

Output Disable from Low Level

GAB

B

2

9

ns

tpHZ

Output Disable from High Level

GAB

B

2

6.5

ns

tpZL

Output Enable to Low Level

GBA

A

3

8.5

ns

tpZH

Output Enable to High Level

GBA

A

3

10.5

ns

tpLZ

Output Disable from Low Level

GBA

A

3

11

ns

tpHZ

Output Disable from High Level

GBA

A

3

7

ns

Vee = 4.5V to 5.5V
R1 = R2 = 500n
CL = 50pF

'AS244 Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

From
(Input)

To
(Output)

Min

Max

Units

A

Y

2

6.2

ns

A

y

2

6.2

ns

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

tPZL

Output Enable to Low Level

G

y

2

7.5

ns

tPZH

Output Enable to High Level

G

y

2

9

ns

2

9

ns

2

6

ns

Vee = 4.5V to 5.5V
R1 = R2 = 500n
CL = 50pF

tpLZ

Output Disable from Low Level

G

y

tpHZ

Output Disable from High Level

G

y

Note 1: See Section 1 for test waveforms and output load.

3-80

Function Tables
AS240
Inputa

AS241
Output

Inputa

Outputs

~

A

Y

2G

16

1A

2A

1Y

L
L
H

L
H
X

H
L
Z

X
X
X
H
H
L

L
L
H
X
X
X

L
H
X
X
X
X

X
X
X
L
H
X

L
H
Z

AS244

L
H

Z

AS242, AS243

Output

Inputs

2Y

INPUTS

G

A

Y

~AB

GBA

L
L
H

L
H
X

L
H

L
H
H
L

L
H
L
H

Z

L = Low logic Level
H = High logic Level
X = Either Low or High logic Level
Z - High Impedance

3-81

'AS242

'AS243

AtoB
BtoA
Isolation
LatchAandB
(A=B)

AtoB
BtoA
Isolation
Latch A and B
(A= B)

~

~

C'II

Si

~. National

Semiconductor
Corporation

c

DM74AS245 Octal TRI-STATE® Bus Transceivers
General Description

Features

This advanced Schottky device contains 8 pairs of TRISTATE logic elements configured as octal bus transceivers.
These circuits are deSigned for use in memory, micropr6cessor systems and In asynchronous bidirectional data buses. Two way communication between buses is controlled by
the (DIR) input. Data transmits either from the A bus to the
B bus or from the B bus to the A bus. Both the driver and
receiver outputs can be disabled via the (G) enable input
which causes outputs to enter the high impedance mode so
that the buses are effectively isolated.

• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• Non-inverting logic output
• TRI-STATE outputs independently controlled on A and
B buses
• Low output impedance to drive terminated transmission
lines to 1330
• Switching response specified into 5000./50 pF
• Specified to interface with CMOS at VOH = Vee - 2V
• PNP inputs reduce input loading
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Line Package

Vee

ii

18

28

38

48

58

68

78

88

ho 119 hB 117 h6 115 114 113 112111
,.J rl rl rl rl ~ ~ rl rpJ

r

Y
1
OIR

I~

I~

I~

I~

I~

I~

I~

I~~

~

'7

'7

'7

7

'7

'7

..,

Ir r r r rl- L I
J2
J3 3A14 4A15 5A16 6AF 7A18 8A19 GNDpO
1A
2A
TL/F/6299-1

Order Number DM74AS245N
See NS Package Number N20A·

Function Table
Control
Inputs

Operation

G

DIR

L
L
H

L
H

B Data to A Bus
A Data to B Bus
Hi-Z

X

'Contact your local NSC representative about surface mount (M) package availability.

3-82

Absolute Maximum Ratings

\

It Military/Aerospace specified devices are required,

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaraq;.
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vee

7V

Input Voltage
Control Inputs
1/0 Ports

7V
5.5V

Operating Free Air Temperature Range
Storage Temperature Range

O"Ct070"C
- 65DC to + 150DC

Recommended Operating Conditions
Symbol

Parameter

Min

Typ

Max

Units

4.5

5

5.5

V

Low Level Input Voltage

0.8

V

Vee

Supply Voltage

V,H

High Level Input Voltage

V,L

2

V

10H

High Level Output Current

-15

mA

10L

Low Level Output Current

48

TA

Free Air Operating Temperature

mA
DC

70

0

Electrical Characteristics over recommended operating free air temperature range
Symbol

Parameter

V,K

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output Voltage

I,

Input Current at Max
Input Voltage

I'H

High Level Input Current

I,L

Low Level Input Current

Conditions

Min

= 4.5V,I'N = -18 mA
Vee = 4.5V, 10H = -3 mA
Vee = 4.5V,IOH = -15 mA
10H = - 2 mA, Vee = 4.5V to 5.5V
Vee = 4.5V, 10L = Max
Vee = 5.5V, Y,N = 7V,
(V,N = 5.5V for A or B Ports)
Control Inputs
Vee = 5.5V,
Y,N = 2.7V
Aor B Ports

Typ

Vee

Vee = 5.5V,
Y,N = 0.4V

10

Output Drive Current

Vee

Icc

Supply Current

Vee

=
=

3.2

2

2.3

V

V

0.35

0.55

V

0.1

mA

20

p.A

70
-0.5

mA

-0.75

A or B Ports

=

Units

Vee - 2

Control Inputs

5.5V, VOUT
5.5V

2.4

Max
-1.2

-50

2.25V

-150

Output High

62

mA

97

Output Low

95

149

TRI-STATE

79

123

mA

Switching Characteristics over re~ommended operating free air temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time
High-to-Low Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

tPZL

Output Enable Time to Low Level

tpZH

Output Enable Time to High Level

tpLZ

Output Disable Time from Low Level

tpHZ

Output Disable Time from High Level

Conditions
Vee = 4.5V to 5.5V,
R1 = R2 = 500n,
CL = 50pF

Note 1: See Section 1 for test waveforms and output load:

3-83

From

To

Min

Max

Units

AorB

BorA

2

7.5

ns

AorB

BorA

2

7

ns

G
G
G
G

AorB

2

8.5

ns

AorB

2

9

ns

AorB

2

9.5

ns

AorS

2

5.5

ns

•

National
Semiconductor
Corporation

DM74AS257/DM74AS258
TRI-STATE®
Quad
1 of 2 Line
.
.
.
Data Selectors/Multiplexers
General Description
• Advanced oxide-lsolated. ion-implanted' Schottky TTL

These data selectorsl multiplexers contain inverters and
drivers to supply full on-chip data selection to the four
TAI-STATE outputs that can interface directly with data
lines of bus-organized systems. A 4-bit word selected from
one of two sources is routed to the four outputs. The AS257
presents true data whereas the AS258 presents inverted
data to minimize propagation delay time.

process
• Functionally and pin for pin compatible with Schottky.
low power Schottky. and advanced low power Schottky
TTL counterpart
• Improved AC performance over Schottky. low power
Schottky. and advanced low power Schottky counterparts
• TRI-STATE buffer-type output drive bus lines directly
• Expand any data input point
• Multiplex dual data buses
• General four functions of two variables (one variable is
common)

This TAl-STATE output feature means that n-bit (paralleled)
data selectors with up to 300 sources can be implemented
for data buses. It also permits the use of standard TTL registers for data retention throughout the system.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

• Source programmable counters

Connection Diagram
Dual-In-Une Package

OUTPUT INPUTS OUTPUT INPUTS OUTPUT
3Y
vCCCONTROL4i'""48
4Y'

3A'38

l~e

115

114

113

h2

ho

111

II

l I I I I I
G

4A

48

4Y

3A

38

1A

1.

1Y

2A

2B

2Y

S

3Y

I I I I I I
SELECT 1A

1.

1Y

15
2A

Ie 17 1a

2B

2Y

""'iiiUTS OUTPUT ~ OUTPUT

GND
TLlFI8107-1

Order Number DM74AS257N or DM74AS258N
See NS Package Number N16A*

Function Table
Inputs

OUtputY

Output
Control

Select

A

B

AS257

AS258

H

X

X

L
L

L

X
X
X

Z

L
L
L
L

Z
H

H

L

L

L

H

H

H

L

H
H

H
X
X

= High Level, L = Low Level, X = Don't Care
Z = High Impedance (011)

H

'Contact your local NSC representative about surface mount (M) package availability.

3-84

L

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vee
Input Voltage

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
paremetric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operatiOn.

7V
7V

Voltage Applied to Disabled Output
Operating Free Air Temperature Range
Storage Temperature Range

5.5V
O·Cto +700C
-65·C to + 150·C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-15

mA

48

mA

70

·c

2

10l

Low Level Output Current

TA

Free Air Operating Temperature

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

Conditions

=

=

Min

VIK

Input Clamp
Voltage

Vee

VOH

High Level Output
Voltage

Vee

2.4

10H

Vee- 2

4.5V,11

Low Level Output
Voltage

II

Input Current @
Max Input Voltage

Vee

High Level Input
Current

Vee

Low Level Input
Current

Vee

10

Output Drive
Current

Vee

10lH

Off-State Output
Current, High
Level Voltage
Applied

Vee = 5.5V
Vo = 2.7V

Off-State Output
Current, Low Level
Voltage Applied

Vee = 5.5V
Vo = 0.4V

IIH

III

lOll

leeH
leel

leel

Supply
Current

AS257

Supply
Current

AS257

Supply
Current

=
=
=

5.5V, VIH

5.5V, VIH

5.5V, Vil

=
=
=

7V

Typ

2.7V

O.4V

5.5V, Vo

=

V
V
V

0.35

0.5

A,B,G

20

Select

40
-1

Select

V
mA

p.A

mA

-0.5
-30

Outputs Disabled

3·85

-1.2

0.1

Outputs Low

AS257

Units

0.2

Outputs High

AS258

Max

A,B,G

2.25V

Vee = 5.5V
Outputs Open

25·C.

3.2

Ail Others

=

=

Select

AS258

AS258

5V, TA

-18 mA

= 4.5V, 10H = Max
= - 2 mA, Vee = 4.5V to 5.5V
Vee = 4.5V, 10l = Max

VOL

=

-112

mA

-50

p.A

-50

p.A

12.9

19.7

mA

8.8

13.5

mA

19

30.6

rnA

15.8

24.6

mA

19.7

31.9

mA

15.5

25.2

mA

,AS257 Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol
tpLH

Parameter

From

To

Conditions

Propagation Delay TIme,
Low to High Level Output

Data

Any

Vee = 4.5Vt05.5V,
CL = 50pF,
RL = 5000

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time, '
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tPZH

Output Enable Time to
High Level

tPZL

Output Enable TIme to
Low Level

tpHZ

Output Disable Time,
from High Level

tpLZ

y

Select

Any

y

Output
Control

Output
Control

Any

y

Any

Y

Output Disable Time,
from Low Level

Min

Max

Units

1

5.5

ns

1

6

ns

2

11

ns

2

10

ns

2

7.5

ns

2

9.5

ns

1.5

6.5

ns

2

7

ns

'AS258 Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol
tpLH

Parameter

From

To

Conditions

Propagation Delay Time,
Low to High Level Output

Data

Any

Vee = 4.5V to 5.5V,
CL = 50pF,
RL = 5000

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tPZH

Output Enable Time to
High Level

tpZL

Output Enable Time to
Low Level

tpHZ

Output Disable Time,
from High Level

tpLZ

Y

Select

Any

Y

Output
Control

Output
Control

Any

y

Any

Y

Output Disable Time,
from Low Level

Nota 1: See Section 1 for test waveforms and outpulload.

3-86

Min

Max

Units

1

5

ns

1

4

ns

2

9.5

ns

2

10

ns

2

8

ns

2

10

ns

1.5

6

ns

2

6.5

ns

Logic Diagrams
74AS257
OUTPUT 15
COIITROL

AJ

8J

Ar
If
Aa
iI3

"
84
HLECT

II

10

14

13

TlIF/61 07-2

74AS258
OUTPUT _1:.::5--cID_---------,
CONTROL
AI~-------_r~

81....::.---+----,""'\

Tl/F/6107-3

3-87

II

~

~

~

:&

,----------------------------------------------------------------------------,

~ Semiconductor
NatiOnal

Corporation

c

DM74AS264 Look-Ahead Carry Generator
General Description

Features

This circuit is a high speed, look-ahead carry generator capable of anticipating a carry across four counters. It is cascadable to perform look-ahead across N-bit counters. Carry,
generator-carry and propagate-carry output functions are
provided as shown in the connection diagram.

• Advanced oxide-isolated, ion implanted Schottky TTL
process
• Switching specification at 50 pF
• Switching specifications guaranteed over full temperature range and Vee range
• PNP inputs reduce input loading

This circuit can accommodate counters which have either
low level carry pulse or high level carry pulse outputs, and
can provide high speed carry look-ahead capability for any
word length. Each AS264 generates the look-ahead (anticipated carry) across a group of four counters, and in addition, other carry look-ahead circuits may be employed to
anticipate a carry across sections of four look-ahead packages up to N bits. This method of cascading circuits to
perform multi-level look-ahead is illustrated under Typical
Applications.

Connection Diagram
Dual-In-Llne Package
61-1

u

16 r-- Vee

Pl- 2

15 r-- P2

60- 3

14

PO-4

13 r-- Cn

INPUTS

r

62

63- 5

12 r--cn+l}
11 r-- Cn+y

P3-ti
POUTPUT -

OUTPUTS

lOr6

7

6NO- 8

9 r Co+z
TL/F/6302-1

Top View
Order Number DM74AS264N
See NS Package Number N16A*

'Contact your local

Nse representative about surface mount (M) package availability.

3-88

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device can not be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

contact the National Semiconductor Sales Office/
Distributors for availability and lPeciflcations_
Supply Voltage, Vcc
Input Voltage
Operating Free Air Temperature
Storage Temperature Range

7V
7V
O'Ct070'C
-65'C to + 150'C

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

Min

Typ

Max

4.5

5

5.5

Units
V

2

V

Vil

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-2

mA

10l

Low Level Output Current

20

mA

TA

Operating Free-Air Temperature

70

'C

0

Electrical Characteristics over recommended operating free-air temperature range (unless otherwise specified)
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

II

Input Current
@Maxlnput
Voltage

IIH

III

10

High Level
Input Current

Low Level
Input Current

Output Drive Current

ICCH

Supply Current with Outputs High

leel

Supply Current with Outputs Low

Conditions

Min

= 4.5V, II = -18mA
Vcc = 4.5V to 5.5V, 10H = - 2 mA
Vcc = 4.5V, 10l = 20 mA
Cn
Vcc = 5.5V, VI = 7V

Typ
(Note 1)

Vee

Vcc

= 5.5V, VI = 2.7V

= 5.5V, VI = 0.4V

= 5.5V, Vo = 2.25V
Vee = 5.5V
Vee = 5.5V
Vcc

Note 1: All Iyplcals are at Vee = 5V and T... = 25"C.

3-89

Units

-1.2

V
V

Vee - 2
0.3

0.5

V

500

GO,G2

Vee

Max

700

G1

800

G3, PO, P1

400

P2

300

P3

200

Cn

100

GO,G2

140

G1

160

G3, PO, P1

80

P2

60

P3

40

Cn

-2.5

GO,G2

-3.5

G1

-4

G3, PO, P1

-2

P3

-1

P2

-1.5
-30

IJ-A

IJ-A

mA

-112

mA

26

38

mA

28

43

mA

II

Switching Characteristics over recommended supply and temperature range (Note 1)
Symbol

Parameter

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

,.

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-ta-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-LoW Level Output

From
(Input)

To
(Output)

PorG

Cn + x,
Cn + y,
orC n + z

PorG

Conditions

Min

Max

25°C
5VMax

Units

2

8

7.5

ns

2

7

7

ns

3

9.5

9

ns

3

8.5

8

ns

2

7.5

7

ns

2

6.5

6

ns

3

9

8.5

ns

2

8

7.5

ns

CL = 50pF
RL = 5000
Vee = 4.5V
to5.5V

G

P

P

Cn

Cn + x,
Cn + y,
orCn + z

NOIe 1: See Sectlllt{ 1 for test waveforms and output load.

Function Tables
Logic Equations for the' AS264 are:
Active High carry
Counters
(Cn = H)

Active Low Carry
Counters
(Cn = L)

Cn + x = GO
Cn + y = GO • G1 _
Cn + = GO.  outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, 110 ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the AS575 are edge-triggered D-type
flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D
inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package, while all the
outputs are on the other side.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly
• Synchronous clear
• Bus structured pinout

Connection Diagram
Dual-In-Llne Package
NC

1
CLR

2
OUTPUT
CONTROL

1Q

2Q

3
10

4
20

5Q

3Q

5
30

6
40

7

50

6Q

8
60

7Q

9
70

8Q

10
80

CLOCK

NC

11
NC
TL/F/6315-1

Order Number DM74AS575N
See NS Package Number N20A'

'Contact your local NSC representative about surface mount (M) package availability.

3-127

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V

Input Voltage

7V

Voltage Applied to Disabled Output

5.5V

Operating Free Air Temperature Range

O·Cto +70·C

Storage Temperature Range

- 65·C to + 150·C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Low Level Input Voltage

0.8

V

IOH

High Level Output Current

-15

rnA

IOL

Low Level Output Current

48

rnA

feLK

Clock Frequency

80

MHz

tw

Width of Clock Pulse

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

tsu

tH

TA

2

V

0

Data Setup Time

Data Hold Time

High

4

Low

6

DATA

4t

CLR High or Low

6t

DATA

2t

CLR

ot

Free Air Operating Temperature

ns

ns

ns

0

·C

70

The ( t) arrow indicates the posHive edge of the elock is used for reference.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18 rnA

VOH

High Level Output
Voltage

Vee = 4.5V, VIL = Max,
IOH = Max

2.4

Vee = 4.5Vto 5.5V, IOH = -2 rnA
VOL

Low Level Output
Voltage

Vee = 4.5V, VIH = 2V,
IOL = Max

II

Input Current
@ Max Input Voltage

Vee = 5.5V, VIH = 7V

Min

Typ

Max

Units

-1.2

V

3.3

V

Vee - 2
0.35

0.5

V

0.1

rnA

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

p.A

IlL

Low Level Input Current

Vee = 5.5V, VIL = O.4V

-0.5

rnA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

-112

rnA

10ZH

Off-State Output Current,
High Level Voltage
Applied

Vee = 5.5V, VIH = 2V,
Va = 2.7V

50

p.A

Off-State Output Current,
Low Level Voltage
Applied

Vee = 5.5V, VIH = 2V,
Vo = 0.4V

-50

p.A

Supply Current

Vee = 5.5V
Outputs Open

IOZL

lee

3·128

-30

Outputs High

78

126

Outputs Low

88

142

Outputs Disabled

88

142

rnA

0

a=
....

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

Vee = 4.SV to S.SV
RL = soon
CL = SOpF

tpHL

From

To

Min

Max

80
Clock

Any 0

Propagation Delay Time
High to Low Level Output

Clock

Any 0

tPZH

Output Enable Time
to High Level Output

Output
Control

Any 0

tpZL

Output Enable Time
to Low Level Output

Output
Control

Any 0

tpHZ

Output Disable Time
from High Level Output

Output
Control

Any 0

tpLZ

Output Disable Time
from Low Level Output

Output
Control

Any 0

Units
MHz

3

8

ns

4

9.S

ns

2

6

ns

3

10

ns

2

6

ns

2

6

ns

~
....

UI
UI

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

Function Table
Output
Control
L
L
L
L
H

CLR

Clock

D

L
H
H
H

t
t
t

H
L

X

X

L

Output
Q

X

X
X

L
H
L

00
Z

L = Low State, H = High State, X = Don't Care
t = Positive Edge Transition
Z = High Impedance State
00 = Previous CondHion of 0
NC = No Internal Connection

II

TL/F/6315-2

3-129

U)

~

::IE

r----------------------------------------------------------------------------,
NatiOnal

~ Semiconductor
Corporation

Q

DM74AS576 Octal D-Type Edge-Triggered
Flip-Flops with Inverted Outputs
General Description
These a-bit registers feature totem-pole TRI-STATE® outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, 1/0 ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the AS576 are edge-triggered inverting D-type flip-flops. On the positive transition of the clock,
the Q outputs will be set to the complement of the logic
states that were set up at the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package while the
outputs are on the other side.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly
• Bus structured pinout

Connection Diagram
Dual-In-Line Package

Vee

OUTPUT
CONTROL

10

20

3D

40

50

60

40

50

60

80

CLOCK

70
TL/F/6316-1

Order Number DM74AS576N
See NS Package Number N20A*

'Contact your local NSC representative about surface mount (M) package availability.

3-130

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Voltage Applied to Disabled Output

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

5.5V
O·Cto +70·C

Operating Free Air Temperature Range
Storage Temperature Range

- 65·C to + 150"C

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

Min

Nom

Max

4.5

5

5.5

Units
V
V

2

Vil

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-15

mA

10l

Low Level Output Current

felOeK

Clock Frequency

tw

Width of Enable Pulse

0

I
I

High

4

Low

6

tsu

Data Setup Time

4j

tH

Data Hold Time

2j

TA

Free Air Operating Temperature

48

rnA

80

MHz
ns
ns
ns

0

·C

70

The ( t) arrow indicates the pos~ive edge of the clock is used for reference.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

Symbol

Parameter

Conditions

=

=

VIK

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

Vee = 4.5V, Vil
10H = Max
10H

=

4.5V, II

Min

=

5V, TA

Typ

-18 rnA

=

Vil Max,

2.4

=

25·C.

Max

Units

-1.2

V

3.3
V

-2 rnA, Vee

=

Low Level Output
Voltage

Vee = 4.5V, VIH
10l = Max

II

Input Current @ Max.
Input Voltage

Vee

=

IIH

High Level Input Current

Vee

=

5.5V, VIH

=

2.7V

20

p.A

III

Low Level Input Current

Vee

5.5V, Vil

-0.5

rnA

Output Drive Current

Vee

=
=

0.4V

10

=
=

2.25V

-112

rnA

10ZH

Off-State Output Current,
High Level Voltage
Applied

Vee = 5.5V, VIH
Vo = 2.7V

=

2V
50

p.A

Off-State Output Current,
Low Level Voltage
Applied

Vee = 5.5V, VIH
Vo = 0.4V

=

-50

p.A

Supply Current

Vee = 5.5V
Outputs Open

10Zl

lee

5.5V, Vo

2V

=

7V

Vee - 2

VOL

5.5V, VIH

=

4.5V to 5.5V

0.35

-30

0.5

V

0.1

rnA

2V

3-131

Outputs High

77

125

Outputs Low

84

135

Outputs Disabled

84

135

rnA

Symbol

Parameter

Conditions

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

tpHL

From

To

Min

Max

80
Clock

Any 0

Propagation Delay Time
High to Low Level Output

Clock

AnyO

tPZH

Output Enable Time
to High Level Output

Output
Control

AnyO

tPZL

Output Enable Time
to Low Level Output

Output
Control

Any 0

tpHZ

Output Disable Time
from High Level Output

Output
Control

AnyO

tpLZ

Output Disable Time
from Low Level Output

Output
Control

Any 0

MHz

3

8

ns

4

9

ns

2

6

ns

3

10

ns

2

6

ns

2

6

ns

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

Function Table
Output
Control

OUTPUT......;.._ _oQI

CONTROL

L
L
L
H

lD 2

L

20 3

t
Z

~

Low State. H

40 _5;;""_ _1--1

50_6;""'_-+-1

7

60---+--t

-+--1

70....;;.,8_ _

8D 9

TL/F/6316-2

3-132

0

t
t

H
L
X
X

High State. X

~ Positive Edge Transition
~

High Impedance State

'00 =
30_4.;....._ _1-...

Clock

L
X
~

Previous Condition of Q

. Units

~

Output

Don't Care

Q
L
H

00
Z

C

_

....iii:
~
........c.n

National

Semiconductor
Corporation

DM74AS577 Octal 0-Type Edge-Triggered Flip-Flops
with Inverted Outputs and Synchronous Preset
General Description
These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, 1/0 ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the AS577 are edge-triggered inverting D-type flip-flops. On the positive transition of the clock,
the Q outputs will be set to the complement of the logic
states that were set up at the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.
When the CLR is held on during a positive transition of the
clock the Q outputs of the flip-flops with go high.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package, while all the
outputs are on the other side.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly
• Synchronous preset
• Bus structured pinout

Connection Diagram
Dual·ln·Line Package
IIC

jij
22

2ij
21

3ij
20

50

4ij
19

18

10
16

iO
15

CLOCK

"

KC

13

TL/F/6317-1

Order Number DM74AS577N
See NS Package Number N24A'

'Contact your local NSC representalive about surface mount (M) package availability.

3-133

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Voltage Applied to Disabled Output

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V
5.5V

Operating Free Air Temperature Range
Storage Temperature Range

O'Cto +70'C
-65'Cto + 150'C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Low Level Input Voltage

0.8

V
mA

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

V

2

10H

High Level Output Current

-15

10l

Low Level Output Current

48

mA

felK

Clock Frequency

80

MHz

twelK

Width of Clock Pulse

tsu
tH
TA

0

Data Setup Time
Data Hold Time

High

4

ns

Low

a

ns

Data

4t

ns

CLR

at

ns

Data

2t

ns

CLR

ot

Free Air Operating Temperature

ns

0

70

'C

The ( t) arrow indicates the pOSitive edge of the Clock Is used for reference.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

II

Input Current at Max
Input Voltage

Conditions

= 4.5V,II = -18 mA
Vee = 4.5V, Vil = Max,
10H = Max
10H = -2 mA, Vee = 4.5V to 5.5V
Vee = 4.5V, VIH = 2V,
10l = Max
Vee = 5.5V, VIH = 7V

Min

=

5V, TA
Typ

Vee

= 5.5V, VIH = 2.7V
= 5.5V, Vil = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V, VIH = 2V,
Vo = 2.7V

2.4

=

25'C.
Max

Units

-1.2

V

3.3

V

Vee -2
0.35

0.5

V

0.1

mA

IIH

High Level Input Current

Vee

20

III

Low Level Input Current

Vee

-0.5

mA

10

Output Drive Current

-112

mA

10ZH

Off-State Output Current,
High Level Voltage
Applied

50

p.A

-50

p.A

10Zl

Icc

Off-State Output Current,
Low Level Voltage
Applied

Vee = 5.5V, VIH
Vo = O.4V

Supply Current

Vee = 5.5V
Outputs Open

=

-30

p.A

2V,

3-134

Outputs High

78

126

Outputs Low

76

123

Outputs Disabled

88

142

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay TIme
Low to High Level Output

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

tpHL

From

To

Max

Min

MHz

80
Clock

Any 0

Propagation Delay Time
High to Low Level Output

Clock

Any 0

tPZH

Output Enable Time
to High Level Output

Output
Control

AnyQ

tPZL

Output Enable Time
to Low Level Output

Output
Control

Any

tpHZ

Output Disable Time
from High Level Output

Output
Control

AnyQ

tpLZ

Output Disable Time
from Low Level Output

Output
Control

Any 0

a

3

8

ns

4

9.5

ns

2

6

ns

3

10

ns

2

6

ns

2

6

ns

Note 1: See Section 1 lor lest waveforms and outpulload.

Logic Diagram
mPlIT 2

Function Table
--"....

CQITROL

Output
Control

mm..!...q:>o10...!.-

~~

Q

20.....L-

ro--

.........I--

r--0

f-c~CR
0

'--

3'....!..-

r---

•
=0- I-~mi

Q

'----

r---

4D....!.-

~ I-r-~mi
0

Q

'----

5D...l......-

r---

•
~ I-~mi

Q

'----

-,.

-,..

n

n
n

-,.

10

21

it

28

Jt

19

Ii

n
po- -.
n

" iO

,....

17 ..

8D~

....,..

_

---I.

Q

,...

15

Ii

,...

15

Ii

~"fi

-

Q

j

CLR

Clock

0

L
H
H
H

t
t
t

X

X

X

L

Output

H
L

X
X

= Low Stale, H = High State, X = Don'l Care
t = Positive Edge Transition
Z = High Impedance Stale
00 = Pravlous Condition 01 Q
L

Q

_"fi

CLDCK 14

Z2

-

~ I-•
_"fi
7• ..L
6• .....L-

n
n

L
L
L
L
H

TUF/8317-2

3-135

Units

Q
H
L
H

00
Z

_

National

Semiconductor
Corporation

DM74AS580 Octal D-Type Transparent Latches
with TRI-STATE® Outputs
General Description
These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, 1/0 ports, bidirectional
bus drivers, and working registers.
The eight inverting latches of the AS580 are transparent
D-type latches, meaning that while the enable (G) is high
the Q outputs will follow the complement of the data (D)
inputs. When the enable is taken low the output will be
latched at the complement of the level of the data that was
set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance

state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are off.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package while all the
outputs are on the other side.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly
• Bus structured pinout

Connection Diagram
Dual-In-Llne Package

OUTPUT
CONTROL

10

20

3D

40

50

60

70

50

60

70

80

ENABLE

GNO
TLlF/6318-1

Order Number DM74AS580N
See NS Package Number N20A'

'Contact your local NSC representative about surface mount (M) package availability.

3-136

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Voltage Applied to Disabled Output
Operating Free Air Temperature Range
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

5.5V
O·Cto +70·C
-65·C to + 150"C

Recommended Operating Conditions
Symbol

Min

Nom

Max

Units

4.5

5

5.5

V

Low Level Input Voltage

0.8

V

High Level Output Current

-15

mA

48

mA

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil
10H

V

2

10l

Low Level Output Current

tw

Width of Enable Pulse, High or Low

2

ns

tsu

Data Setup Time

2

ns

tH

Data Hold Time

3

ns

0

·C

TA

Free Air Operating Temperature

70

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

Conditions

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

Vee = 4.5V, Vil
10H = Max

Val

Low Level Output
Voltage

Vee = 4.5V, VIH
10l = Max

II

Input Current @ Max
Input Voltage

Vee

= 5.5V, VIH = 7V

IIH

High Level Input Current

Vee

III

Low Level Input Current

Vee

= 5.5V, VIH = 2.7V
= 5.5V, Vil = O.4V

10

Output Drive Current

Vee

= 5.5V, Va = 2.25V

10ZH

Off-State Output Current,
High Level Voltage
Applied

Vee = 5.5V, VIH
Va = 2.7V

= 2V,

Off-State Output Current,
Low Level Voltage
Applied

Vee = 5.5V, VIH
Va = 0.4V

= 2V,

Supply Current

Vee = 5.5V
Outputs Open

10Zl

lee

Typ

= 4.5V, II = -18 mA

VIK

10H

Min

= 5V, TA = 25·C.

= Vil Max,

= -2 mA, Vee = 4.5V to 5.5V

2.4

Units
V

3.3

V

Vee - 2

= 2V,

3-137

Max
-1.2

0.35

-30

0.5

V

0.1

mA

20

p.A

-0.5

mA

-112

mA

50

p.A

-50

p.A

Outputs High

62

100

Outputs Low

65

106

Outputs Disabled

71

115

mA

C)

co

In

~
:::iii
"'C"

r-------------------------------------------------------------------------------------~

Switching Characteristics
over recommended operating free air temperature range (Note 1). All typical values are measured at Vee = 5V, TA = 25°C.

Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

tpLH

From

To

Data

Any 0

Data

Any 0

Propagation Delay Time
Low to High Level Output

Enable

Any 0

tpHL

Propagation Delay Time
High to Low Level Output

Enable

Any 0

tPZH

Output Enable Time
to High Level Output

Output
Control

AnyO

tPZL

Output Enable Time
to Low Level Output

Output
Control

AnyO

tpHZ

Output Disable Time
from High Level Output

Output
Control

Any 0

tpLZ

Output Disable Time
from Low Level Output

Output
Control

AnyO

Min

Max

Units

3

7.5

ns

3

7

ns

5

9

ns

4

8

ns

2

6.5

ns

4

9.5

ns

2

6.5

ns

2

7

ns

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

Function Table

OUTPUT
CONTROL"';'---OI

10 2

20_;3;...._ _.......

Output
Control

Enable

L
L
L
H

H
H
L

G

X

30...;,,4_ _-+--1

50

60

70

80

Output

5

4Q

6
50

7

8

9

TLlF/6318-2

3·138

Q

H
L

L
H

X
X

00

L = Low State, H = High State, X = Don't Care
Z = High Impedance State

00 = Previous Condition 01 "0

40

0

Z

~ Semiconductor
NatiOnal

Corporation

DM74AS620 Octal Bus Transceiver
General Description
This octal bus transceiver is designed for asynchronous
two-way communication between data buses. The control
function implementation allows for maximum flexibility in
timing.
This device allows data transmission from the A bus to the
B bus or from the B bus to the A bus, depending upon the
logic levels at the enable inputs (GBA and GAB).
The enable inputs can be used to disable the device so that
the buses are effectively isolated.
The dual-enable configuration gives the octal bus transceivers the capability of storing data by simultaneous enabling
of GBA and GAB. Each output reinforces its input in this

Connection Diagram

transceiver configuration. Thus, when both control inputs
are enabled and all other data sources to the two sets of
bus lines are at high impedance, both sets of bus lines (16
in all) will remain at their last states.

Features
• Local bus-latch capability
• Choice of true or inverting logic
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Logic Diagram
GBA----OI

Dual-In-Line Package
GAB

20

Vee

Al

19

iiBA

AZ

18

Bl

A3

17

B2

A4

16

83

A5

15

84

A6

14

B5

A7

13

86

GAB

A l - -....t-...

TO OTHER SEVEN
TRANSCEIVERS
TL/F/6319-2

Function Table
Enable Inputs
Operation
GBA

AS

GNO

10

12

B7

11

B8

. .-Bl

~~-t

TL/F 16319-1

Top View
Order Number DM74AS620N
See NS Package Number N20A'

·Contact your local NSC representative about surface mount (M) package availability.

3-139

GAB

L

L

B Data to A Bus

H

H

Ii. Data to B Bus

H

L

Isolation

L

H

B Data to A Bus,
Ii. Data to B Bus

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage (110 ports)

5.5V

Input Voltage (all other inputs)

7V

Operating Free Air Temperature Range
Storage Temperature Range

O"Cto +70'C
-55'Cto + 150"C

Recommended Operating Conditions
Symbol

Parameter

Min

Typ

Max

4.5

5

5.5

Units

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

10H

High Level Output Current

-15

mA

10L

Low Level Output Current

54

mA

TA

Free Air Operating Temperature

70

'C

V

2

V

0

V

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VOH

Output High Voltage

Vee = 4.5Vto5.5V,IOH = -2 mA
Vee = 4.5V, 10H = -3 mA
Vee = 4.5V,IOH = Max

VOL

Output Low Voltage

Vee = 4.5V, 10L = Max

II

Input Current at Max
Input Voltage

Vee = 5.5V
VI = 7V

Control Inputs

Vee = 5.5V
VI = 5.5V

A or B Ports

High Level
Input Current

Vee = 5.5V
VI = 2.7V

Low Level
Input Current

Vee = 5.5V
VI = O.4V

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V (Note 2)

lee

Supply Current

Vee = 5.5V

IIH

IlL

Nole 1: All typical values are at Vee

Min

Typ
(Note 1)

Max

Units

-1.2

V

Vee - 2
2.4

3.2

V

2
0.35

0.55
0.1

mA
0.1

Control Inputs

20

A or B Ports (Note 3)

70

Control Inputs

-0.5

A or B Ports (Note 3)

-0.75
-50

-150

Outputs High

35

57

Outputs Low

74

122

Outputs Disabled

48

77

= 5V, TA = 25'C.

Note 2: The output condijions have been chosen 10 produce a current that closely apprOximates one half of the true short circuit output current, los.
Nole 3: For I/O ports, the parameters IIH and IlL include the off-state output current.

'-.'

\

'.

'.

3-140

V

/LA

mA
mA

mA

AS620 Switching Characteristics over recommended free air temperature range (Note 1)
From (Input)
To (Output)

Min

Max

Units

AtoB

1

7

ns

AloB

2

6

ns

Propagation Delay Time
Low to High Level Output

BtoA

1

7

ns

tpHL

Propagation Delay Time
High to Low Level Output

BtoA

2

6

ns

tPZH

Output Enable Time
to High Level Output

GBAtoA

2

8

ns

tpZL

Output Enable Time
to Low Level Output

GBAtoA

2

9

ns

tpHZ

Output Disable Time
from High Level Output

GBAtoA

1

6

ns

tpLZ

Output Disable Time
from Low Level Output

GBAtoA

2

12

ns

tPZH

Output Enable Time
to High Level Output

GABtoB

2

8

ns

tPZL

Output Enable Time
to Low Level Output

GAB to B

2

9

ns

tpHZ

Output Disable Time
from High Level Output

GABtoB

1

6

ns

tpLZ

Output DisableTime
from Low Level Output

GABtoB

2

13

ns

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
CL = 50pF
R1 = 500n
R2 = 500n
TA = Min to Max

tpLH

Symbol

Note 1: See Section 1 for test waveforms and output load.

3-141

rit
5i
~

~

==

National
Semiconductor
CorporaHon

Q

DM74AS640 TRI-STATE® Octal Bus Transceiver
General Description

FeatOres

This advanced Schottky device contains 8 pairs of TRISTATE logic elements configured as octal bus transceiver.
This circuit is designed for use in memory, microprocessor
systems and in asynchronous bidirectional data buses. This
device transmits data from the A bus to the B bus, or vice
versa, depending upon the logic level of the direction control input (DIR). The enable input (G) can be used to disable
the devices, effecting isolation of buses A and B.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TTL counterpart
• Improved AC performance over Schottky, low power
Schottky, and advanced low power Schottky counterparts
• TRI-STATE outputs independently controlled on A and
B buses
• Low output Impedance drive to drive terminated transmission lines to 1330.
• Specified to interface with CMOS at VOH = Vee - 2V

The TRI-STATE circuitry also contains a protection feature
that prevents these transceivers from glitching the bus during power-up or power-down.

Connection Diagram

Function Table

Dual-In-Llne Package

_

ENABLE

U

~

~

~

M

~

Control Inputs
~

G

"

~

Operation

DIR

L

L

B Data to A Bus

L

H

A Data to B Bus

H

X

Isolation

Logic Diagram
R-----,
DIR....f---...I

+- Bl

Al....f~-I'~)--....,.....
~

M

~

~

M

M

M

~

M

~

TUF/6708-1

Top View

TO SEVEN OTHER TRANSCEIVERS

TL/F/8708-2

Order Number DM74AS640N
See NS Package Number N20A·

'Contact your local NSC representative about surface mount (M) package availability.

3-142

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales OffIce/
Distributors for availability and speclflcatlons_
Supply Voltage
7V
Input Voltage
Control Inputs
7V
110 Ports
5.5V
O"Cto +70"C
Operating Free Air Temperature Range
Storage Temperature Range
- 65'C to + 150'C

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

Parameter

Min

Typ

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low level Input Voltage

0.8

V

10H

High Level Output Current

-15

mA

64

mA

70

'c

V

2

10l

Low Level Output Current

TA

Free Air Operating Temperature

0

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol

Parameter

VI

Input Clamp Voltage

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

II

Input Current at Max
Input Voltage

IIH

High Level Input Current

III

Low Level Input Current

Conditions

= Min, II = -18 mA
= 4.5V to 5.5V, 10H = -2 mA
Vee = 4.5V, 10H = -3 mA
Vee = 4.5V, 10H = Max
Vee = Min, 10l = Max
Vcc = Max, VI = 7V,
(VI = 5.5V for A or B Ports)
Control Inputs
Vcc = Max
VI = 2.7V (Note 2)
A or B Ports

Min

Typ
(Note 1)

-1.2

Vcc
Vee

Vee = Max,
VI = 0.4V (Note 2)

=
=

=

Max

Units
V
V

Vcc - 2
2.4

V

2.4

V
0.35

0.55

V

0.1

mA

20

p.A

70
-0.5

Control Inputs

mA

-0.75

A or B Ports

-150

mA

37

58

mA

Supply Current with Outputs Low

78

123

mA

Supply Current with Outputs
in TRI-STATE

51

80

mA

10

Output Drive Current

Vee

ICCH

Supply Current with Outputs High

Vee

ICCl
leez

Note 1: All typicals are at Vee

Max, Vo

2.25V

Max

= 5.0V, TA = 25'C.

Note 2: For I/O ports, the parameters IIH and III include the off-state output current, IOZH and IOZl.

3-143

-50

Switching Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol

Parameter

From
(Input)

To
(Output)

tpLH

Propagation Delay Time
Low to High Level Output

AorB

BorA

tpHL

Propagation Delay Time
High to Low Level Output

AorB

tpzH

Output Enable Time to
High Level Output

G

AorB

tPZL

Output Enable Time to
Low Level Output

G

AorB

tpHZ

Output Disable Time from
High Level Output

G

AorB

tpLZ

Output Disable Time from
Low Level Output

G

AorB

BorA

3·144

CL

Vee = Min to Max,
= 50pF,R1 = R2 = soon

Units

Min

Max

2

7

ns

2

6

ns

2

8

ns

2

10

ns

2

8

ns

2

13

ns

.------------------------------------------------------------------,0
i:
.....
National
_
Semiconductor
~
Corporation
en

""'

UI

DM74AS645 TRI-STATE® Octal Bus Transceiver
General Description

Features

This advanced Schottky device contains 8 pairs of TRISTATE logic elements configured as an octal bus transceiver. This circuit is deSigned for use in memory, microprocessor systems and in asynchronous bidirectional data buses.
This device transmits data from the A bus to the B bus, or
vice versa, depending upon the logic level of the direction
control input (DIR). The enable input (G) can be used to
disable the devices, effecting isolation of buses A and B.
The TRI-STATE circuitry also contains a protection feature
that prevents these transceivers from glitching the bus during power-up or power-down.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky,
low power Schottky, and advanced low power Schottky
TTL counterpart
• Improved AC performance over Schottky, low power
Schottky, and advanced low power Schottky counterparts
• TRI-STATE outputs independently controlled on A and
B buses
• Low output impedance drive to drive terminated transmission lines to 1330
• Specified to interface with CMOS at VOH = Vee - 2V

Connection Diagram

Function Table

Dual-In-Line Package

_

ENABLE
~

~

~

~

~

~

Control
Inputs
~

M

~

G

Operation

DIR

L

L

B Data to A Bus

L

H

A Data to B Bus

H

X

Isolation

Logic Diagram
DM74AS645

D1R-I---......
~

M

M

~

AA

~

~

U

M

~D

TL/F/9311-1

Top View

Al

Order Number DM74AS645N
See NS Package Number N20A*

Bl

TO SEVEN OTHER TRANSCEIVERS
TL/F/9311-2

I
·Contact your local NSC representative about surface mount (M) package availability.

3-145

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications_
Supply Voltage
7V
Input Voltage
Control Inputs
7V
I/O Ports
5.5V
Operating Free Air Temperature Range
O·Cto +70"C
Storage Temperature Range
- 65·C to + 150·C

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

Parameter

Min

Typ

Max

Units

4.5

5

5.5

V

Vcc

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-15

mA

64

mA

70

·C

10l

Low Level Output Current

TA

Free Air Operating Temperature

2

V

0

DM74AS645 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol

Parameter

Conditions

VI

Input Clamp Voltage

Vee = Min, 11= -18 mA

VOH

High Level Output Voltage

Vcc = 4.5V to 5.5V, 10H = - 2 mA

Min

Typ
(Note 1)

Max

Units

-1.2

V

Vcc- 2

V

Vee = 4.5V, 10H = -3 mA

2.4

V

Vcc = 4.5V, 10H = Max

2.4

V

VOL

Low Level Output Voltage

Vcc = Min, 10l = Max

II

Input Current at Max
Input Voltage

Vee = Max, VI = 7V,
(VI = 5.5V for A or B Ports)

IIH

High Level Input Current

Vcc = Max
VI = 2.7V (Note 2)

Control Inputs

20

Aor B Ports

70

Vcc = Max,
VI = O.4V (Note 2)

Control Inputs

Low Level Input Current

III

Output Drive Current

Vcc = Max, Vo = 2.25V

ICCH

Supply Current with Outputs High

Vcc = Max

ICCl
Icc

Note

0.55

V

0.1

mA

-0.5

A or B Ports

10

Note 1:

0.35

/LA
mA

-0.75
-50

-150

mA

62

97

mA

Supply Current with Outputs Low

95

149

mA

Supply Current with Outputs
in TRI-STATE

79

123

mA

All typicals are at Vee

- S.OV, TA - 2S'C.

2: For 1/0 ports. the parameters IIH and IlL include the off-state output current. 10ZH and 10ZL'

3-146

Switching Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol

Parameter

From
(Input)

To
(Output)

tpLH

Propagation Delay Time
Low to High Level Output

AorB

BorA

tpHL

Propagation Delay Time
High to Low Level Output

AorB

BorA

tpZH

Output Enable Time to
High Level Output

G

AorB

tPZL

Output Enable Time to
Low Level Output

G

AorB

tpHZ

Output Disable Time from
High Level Output

G

AorB

tpLZ

Output Disable Time from
Low Level Output

G

AorB

3·147

CL

Vee = Min to Max,
Rz = 500n

= 50pF,R1 =

Units

Min

Max

2

9.5

ns

2

9

ns

2

11

ns

2

10

ns

2

7

ns

2

12

ns

00
00:1'

i

.....
c...... .
::::!!!

CD
00:1'

~.....

::i
C

r----------------------------------------------------------------------------,
NatiOnal

~ Semiconductor
Corporation

DM7 4AS646/DM7 4AS648 Octal
Bus Transceivers and Registers
General Description
These devices incorporate an octal bus transceiver and an
octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus.
These bus transceivers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance third
state and increased high-logic-level drive provide these devices with the capability of being connected directly to and
driving the bus lines in a bus-organized system without need
for interface or pull-up components. They are particularly
attractive for implementing buffer registers, 110 ports, bidirectional bus drivers, and working registers.
The registers in the AS646, 648 are edge-triggered D-type
flip-flops. On the positive transition of the clock (CAB or
CBA), the input bus data is stored.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A low
input level selects real-time data, and a high level selects
stored data. The select controls have a "make before
break" configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data.

The enable G and direction control pins provide four modes
of operation; real-time data transfer from bus A to B, realtime data transfer from bus B to A, real-time bus A and lor B
data transfer to internal storage, or internal store data transfer to bus A or B.
When the enable G pin is low, the direction pin selects
which bus receives data. When the enable G pin is high,
both buses become disabled yet their input function is still
enabled.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with LS TTL
counterpart
• TRI-STATE® buffer-type outputs drive bus lines directly

Connection Diagram
Dual-In-Line Package
B3

17

18

21

I

B4

B5

B8

B6

15

16

13

I

I
B TRANSCEIVERS

CONTROL ~-----i
LOGIC

- - - -

I

I

I

A1

A2

A3

I

-~ - - - I

I

1
SAB

DIR

I

112

3

CAB

I

- -

GND
TLlF/6324-1

Order Number DM74AS646NT or DM74AS648NT
See NS Package Number N24C·

*Contact your local NSC representative about surface mount (M) package availability.

3-148

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Control Inputs
7V
I/O Ports
5.5V
O·Cto +70·C
Operating Free Air Temperature Range
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

-65·C to + 1500C

Recommended Operating Conditions
Symbol

DM74AS646,648

Parameter

Units

Min

Nom

Max

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V
mA

2

V

10H

High Level Output Current

-15

10L

Low Level Output Current

48

mA

feLK

Clock Frequency

90

MHz

tw

Width of Clock Pulse

0

I

High

5

ns

I

Low

6

ns
ns

tsu

Data Setup Time

6t

tH

Data Hold Time

ot

TA

Free Air Operating Temperature

ns
·C

70

0

The (t) arrow indicates the positive edge of the Clock is used for reference.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vcc
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

II

Input Current @ Max
Input Voltage

IIH

High Level Input Current

Conditions

= 4.5V,11 = -18 mA
Vee = 4.5V
10H = Max
VIL = Max
10H = -3mA
VIH = Min
Vee = 4.5V to 5.5V, IOH = -2 mA
Vee = 4.5V, VIL = Min
VIH = 2V, 10L = Max
Control Inputs
Vee = 5.5V
VI = 7V
A or B Ports
VI = 5.5V
Control Inputs
Vee = 5.5V, VIH = 2.7V

Low Level Input Current

Typ

Vce

(Note 1)
IlL

= 5V, TA = 25·C.

Min

10

Output Drive Current

Vee

lee

Supply Current

Vee

= O.4V

2.4

'AS646

'AS648

0.35

0.5
0.1

V
mA

0.1
20

",A

70
-0.5

mA

-0.75
-30

-112
120

195

Outputs Low

130

211

Outputs Disabled

130

211

Outputs High

110

185

Outputs Low

120

195

Outputs Disabled

120

195

Note 1: For 1/0 ports, the parameters IIH and IlL include the off·state current, IOZH and IOZL.

3·149

V

Vee - 2

Control Inputs

Outputs High

V

3.2

A or B Ports

= 5.5V, Vo = 2.25V
= 5.5V

Units

2

A or B Ports

Vee = 5.5V, VIL
(Note 1)

Max
-1.2

rnA

mA

'AS646 Switching Characteristics over recommended operating free air temperature range (Note 1).
Symbol

Parameter

fMAX

Maximum Clock
Frequency

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tPZH

Output Enable Time
to High Level Output

tpZL

Output Enable Time
to Low Level Output

From
(Input)

Conditions

To
(Output)

DM74AS646
Min

Vee = 4.5V to 5.5V,
Rl = R2 = 5000
CL = 50 pF (Note 1)

MHz

90

CBAor
CAB

AorB

SBAor SAB
(Note 2)

Enable

G

Units

Max

2

8.5

ns

2

9

ns

2

9

ns

1

7

ns

2

11

ns

2

9

ns

2

9

ns

3

14

ns

2

9

ns

AorB

BorA

AorB

AorB

tpHZ

Output Disable Time
from High Level Output

tpLZ

Output Disable Time
from Low Level Output

2

9

ns

tPZH

Output Enable Time
to High Level Output

3

16

ns

tpzL

Output Enable Time
to Low Level Output

3

18

ns

DIR

AorB

tpHZ

Output Disable Time
from High Level Output

2

10

ns

tpLZ

Output Disable Time
from Low Level Output

2

10

ns

Note 1: See Section 1 for te.t waveforms and output load.
Note 2: These parameters are measured with the internal output state of the storage register opposite to that of the bus Input.

3-150

I

AS648 Switching Characteristics over recommended operating free air temperature range (Note 1)

Symbol

Parameter

From
(Input)

Conditions

fMAX

Maximum Clock
Frequency

tPLH

Propagation Delay Time
Low to High Level Output

tPHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

To
(Output)

Vee = 4.5V to 5.5V,
R1 = R2 = 500n
CL = 50 pF (Note 1)

DM74AS648
Min

90

CABorCBA

Units

Max

MHz

2

8.5

ns

2

9

ns

2

8

ns

1

7

ns

2

11

ns

AorB

AorB

BorA

SBA or SAB (Note 2)

AorB

tpHL

Propagation Delay Time
High to Low Level Output

2

9

ns

tpZH

Output Enable Time
to High Level Output

2

9

ns

tpZL

Output Enable Time
to Low Level Output

3

15

ns

2

9

ns

Enable

AorB

G

tpHZ

Output Disable Time
from High Level Output

tpLZ

Output Disable Time
from Low Level Output

2

9

ns

tPZH

Output Enable Time
to High Level Output

3

16

ns

tpZL

Output Enable Time
to Low Level Output

3

18

ns

2

10

ns

10

ns

Bus

DIR

Output Disable Time
from High Level Output

tPHZ

Output Disable Time
2
from Low Level Output
Note 1: See Section 1 for test waveforms and output load.
Note 2: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
tpLZ

Function Table
Inputs
G DIR

CAB

CBA

A1 thruA8

B1 thru B8

Input

Input

Real Time B Data to A Bus Real B Data to A Bus
Stored B Data to A Bus
Stored B Data to A Bus

t

L
L

X
X

X
HorL

X
X

L
H

Output

Input

H
H

X
HorL

X
X

L
H

X
X

Input

Output

L
L

'AS648

Isolation, Hold Storage
Store A and B Data

t

H

'AS646

X
X

X
X

X
X

HorL HorL

Operation or Function

Data I/O'
SAB SBA

Isolation, Hold Storage
Store A and B Data

Real Time A Data to B Bus Real Time A Data to B Bus
Stored A Data B Bus
Stored A Data to B Bus

X
Input
Unspecified' Store A, B Unspecified"
Store A, B Unspecified'
X
X
X X
t
Input
Store B, A Unspecified'
Store B, A Unspecified'
X
X
Unspecified'
X X
X
t
H-high level; L-Iow level; X-Irrelevent; i -Iow·ta-high level transition
'The date output functions may be enabled or disabled by various Signals at the G and DIR inputs. Date input functions are always enabled. i.e .. date at the
bus pins will be stored on every low·to-hlgh transition on the clock inputs.

3·151

..
~
..
..
co
CD

Block Diagram (positive logic)

.....

'AS646

::E
Q

.....
CD
CD

~

.....

G
Dill

CBA
58A

(21)

(3)
(23)
(22)

:::&
Q

CAB
SAB

(1)
(2)

-

-.
I

I

I
1(20)

...+-+-...,.........-

A1_+~-+-i

B1

I

I

L ________ _

-

I
-~

~------------_,vr--------------~
TD 7 OTHER CHANNELS

TUF/6324-2

'AS648
G
DIR
CSA
SSA

CAS

(21)

(3)
(23)
(22)

(1)
(2)

SAS

I
1(20)

...+-+-""':"'1......_

A1 - .....-+-+_

B1

L ________ _

~--------------~v
TO 7 OTHER CHANNELS

TL/F/6324-5

3·162

_

C
iii:

....

National

i....

Semiconductor
Corporation

UI

.....

DM7 4AS651/DM7 4AS652 Octal
Bus Transceiver and Register

C

....iii:

i

General Description

UI
N

These devices incorporate an octal transceiver and an octal
D-type register configured to enable transmission of data
from bus to bus or internal register to bus.
These bus transceivers feature totem-pole TRI-STATE!!>
outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these devices
with the capability of being connected directly to and driving
the bus lines in a bus-organized system without need for
interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The registers in the AS651, 652 are edge-triggered D-type
flip-flops. On the positive transition of the clock (CAB or
CBA), the input data is stored.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A low
input level selects real-time data and a high level selects
stored data. The select controls have a "make before

break" configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data.
The Enable (GAB and GBA) control pins provide four
modes of operation; real-time data transfer from bus A to B,
real-time data transfer from bus B to A, real-time bus A and/
or B data transfer to internal storage, or internal stored data
transfer to bus A and/or B.

Features
• Switching speCifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE!!> buffer-type outputs drive bus lines directly

Connection Diagram
Dual-In-Line Package
VCC

24\

SBA

CBA

23

GBA

22

"'7

21

Bl

B2

B3

20 1

19 1

lal

I

I

I

*
CAB

SAB

B6

B7

lsi

141

I

I

B8

13

8 TRANSCEIVERS

~

2

BS

16

I

CONTROL
LOGIC

11

B4

17

'I
13
GAB

------

f-

I

I

I

14

Is

1

AI

A2

-~ - - - - - -

I
6

A3

17
A4

-r--

I

la
AS

19
A6

110
A7

111
Aa

112
GND
TL/F/6325-1

Order Number DM74AS651NT
See NS Package Number N24C'

'Contact your local NSC representative about surface mount (M) package availability.

3-153

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors tor availability and specifications.
Supply Voltage
7V
Input Voltage
Control Inputs
7V
I/O Ports
5.5V
Operating Free Air Temperature Range
O·Cto +70·C
- 65·C to + 150·C
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-15

mA

10l

Low Level Output Current

48

mA

felK

Clock Frequency

90

MHz

twelK

Width of Enable Pulse

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

V

2

0

I

I

High

5

Low

6

tsu

Data Setup Time

6

tH

Data Hold Time

0

TA

Operating free Air Temperature

0

ns
ns
ns
·C

70

The ( t) arrow indicates the positive edge of the Clock is used for reference.

ElectricallCharacteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, T A = 25·C.

Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V

10H = Max

Vee = 4.5V to 5.5V
VOL

Low Level Output
Voltage

Vee = 4.5V, 10l = Max

II

Input Current at
Max Input Voltage

Vee = 5.5V

High Level Input Current

Vee = 5.5V, VIH = 2.7V

IIH
III

Low Level Input Current

Min

Typ

Max

Units

-1.2

V

2

10H = -3mA

2.4

10H = -2mA

Vee - 2

3.2

0.35

V

0.5

VI = 7V

Control Inputs

0.1

VI = 5.5V

A or B Ports

0.1

Vee = 5.5V, Vil = O.4V

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

Icc

Supply Current

Vee = 5.5V
'AS651

'AS652

3·154

Control Inputs

20

A or B Ports

70

Control Inputs

-0.5

A or B Ports

-0.75
-30

-112

Outputs
High

110

185

Outputs
Low

120

195

Outputs
Disabled

130

195

Outputs
Low

120

195

Outputs
High

130

211

Outputs
Disabled

130

211

V
mA
/LA
mA
mA

mA

'AS651 Switching Characteristics over recommended operating free air temperature range (Note 1)
Parameter

Conditions

fMAX

Symbol

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

Vee = 4.5V to 5.5V
R1 = R2 = 500n
CL = 50pF

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tPZH

Output Enable Time
to High Level Output

tPZL

Output Enable Time
to Low Level Output

From

To

Min

Max

CBAorCAB

AorB

SBAorSAB
(Note 2)

EnabieGBA

Units
MHz

90
2

8.5

ns

2

9

ns

2

8

ns

1

7

ns

2

11

ns

2

9

ns

2

10

ns

3

16

ns

AorB

BorA

AorB

A

tpHZ

Output Disable Time
from High Level Output

2

9

ns

tpLZ

Output Disable Time
from Low Level Output

2

9

ns

tPZH

Output Disable Time
to High Level Output

3

11

ns

tpZL

Output Disable Time
to Low Level Output

3

16

ns

Enable GAB

B

tpHZ

Output Disable Time
from High Level Output

2

10

ns

tpLZ

Output Disable Time
from Low Level Output

2

11

ns

Note

1: See Section 1 for test waveforms and output load.

Note 2: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.

3·155

'AS652 Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

Vee = 4.5V to 5.5V
At = A2 = 500n
CL=50pF

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

From

To

Min

Max

90

CBAorCAB

AorB

SBAorSAB

Units
MHz

2

8.5

ns

2

9

ns

2

9

ns

1

7

ns

2

11

ns

AorB

BorA

AorB

tpHL

Propagation Delay Time
High to Low Level Output

2

9

ns

tPZH

Output Enable Time
to High Level Output

2

10

ns

tpZL

Output Enable Time
to Low Level Output

3

16

ns

Enable-eiBA

A

tpHZ

Output Disable Time
from High Level Output

2

9

ns

tpLZ

Output Disable Time
from Low Level Output

2

9

ns

tPZH

Output Disable Time
to High Level Output

3

11

ns

tPZL

Output Disable Time
to Low Level Output

3

16

ns

Enable GAB

B

tpHZ

Output Disable Time
from High Level Output

2

10

ns

tpLZ

Output Disable Time
from Low Level Output

2

11

ns

Nole 1: See Section 1 for test waveforms and oulpot load.
Note 2: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.

3-156

Schematics of Inputs and Outputs
Equivalent of All Other Inputs

Typical of AII'AS651, 'AS652 Outputs
-

......-vcc

OUTPUT

TL/F/6325-5
TL/F/6325-4

Block Diagram
'AS651

SBA

(2)

(4)
Al - - ..........1-+..

(20)
H-+~H--Bl

....-+---<:0 ClK
Q

1----1f+H-I

TO 7 OTHER CHANNELS
TUF/6325-2

3·157
----_. -- -

-

-- - - - - - - - - - -

Block Diagram

(Continued)
'AS652

-~

GBA

-

GAB~--

CAB

SBA

.--

V-

(23)
CBA
SBA (22)

......

J!l[>o-

I

-Vo-

(2)

-Vo-

-~ ------------_. '. -~-------------.
or
1

8 CHANNELS

r0o-

D

~
-

(4)
Al

ClK

Q
'--(20)
B1

D

,

ClK

Q

-

.-

---------------

--

~
------------_. -

,

TO 7 OTHER CHANNELS
TL/F/6325-3

Function Table
INPUTS
GAB

GBA

L
L

H
H

L
L

CAB

CBA

HorL HorL

DATAI/O'
A1THRUA8

B1THRUB8

OPERATION OR FUNCTION

'AS651

SAS

SBA

X
X

Input

Input

Isolation
Store A and B Data

'AS652

Isolation
Store A and B Data

t

t

X
X

L
L

X
X

X
HorL

X
X

L
H

Output

Input

Real Time B Data to A Bus Real Time B Data to A Bus
Stored B Data to A Bus
Stored B Data to A Bus

H
H

H
H

X
H orL

X
X

L
H

X
X

Input

Output

Real Time A Data to B Bus Real Time A Data to B Bus
Stored A Data to B Bus
Stored A Data B Bus

H

L

HorL HorL

H

H

Output

Output

Stored A Data to B Bus
& Stored B Data to A Bus

X
H

H
H

X
X(1)

X
X

Input
Input

t
t

HorL

t
t
t

Unspecified' Store A, Hold B
Output
Store A in both registers

Stored A Data to B Bus
& Stored B Data to A Bus
Store A, Hold B
Store A in both registers

L
X
HorL
X
X
Unspecified'
Input
Hold A, Store B
Hold A, Store B
X(1)
Output
Input
Store B in both registers
Store B in both registers
L
L
X
Note 1: ~ the select control Is low, the clocks osn occur SimultaneouSly. If the select control I. high, the clocks muat be staggered In order to load both registers.

t

H-hlgh level L-Iow level X-irrelevant

t

-Iow-to-high transition

'The data output functions may be enabled or disabled by various signals at the GAB end CIBA Inputs. Data Input functions are always enabled, I.e., data at the bus
pins will be stored on every low-to-hlgh transition on the clock inputs.

3-158

_

National

Semiconductor
Corporation

DM74AS804B Hex 2-lnput NAND Drivers
General Description

Features

These devices contain six independent drivers, each of
which performs the logic NAND function. Each driver has
increased output drive capability to allow the driving of high
capacitive loads.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with advanced
low power Schottky TTL counterpart

Connection Diagram
Dual-In-Line Package

vee

6B

6A

BY

5B

5A

5Y

4B

4A

lA

lB

lY

2A

2B

2Y

3A

3B

3Y

Order Number DM74AS804BN
See NS Package Number N20A'

Function Table
y= AB
Inputs

H
L

Output

A

B

V

L
L

L

H

H
H

L

H
H
H

H

L

= High Logic Level
= Low Logic Level

'Contact your local NSC represen1etive about surface mount (M) package availability.

3-159

4Y

TL/F/6326-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V
O"Cto +70"C
-65'Cto + 150"C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-48

mA

10L

Low Level Output Current

48

mA

TA

Free Air Operating Temperature

70

'C

2

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

Conditions

10H

= 4.5V,II = -18 mA
= -2 mA, Vee = 4.5Vto 5.5V
= -3 mA, Vee = 4.5V

10H

=

VIK

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

10H

VOL

Low Level Output
Voltage

Vee = 4.5V, 10L
VIH = 2V

II

Input Current @
Max Input Voltage

Vee

=

IIH

High Level Input Current

Vee

IlL

Low Level Input Current

Vee

=
=

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

lee

Supply Current

Vee = 5.5V

=
=

4.5V

5.5V, VIH

=

7V

5.5V, VIH

=

2.7V

Max, Vee

Min

=

5V, TA
Typ

=

25'C.
Max

Units

-1.2

V

Vee - 2
2.4

V

2

Max

0.35

5.5V, VIL = O.4V
-50

0.5

V

0.1

mA

20

".A

-0.5

mA

-135

-200

mA

Outputs High

3.5

5

mA

Outputs Low

16

27

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

3-160

Min

Max

Units

1

4

ns

1

4

ns

IJ

National

Semiconductor
CorporaHon

DM74AS805B Hex 2-lnput NOR Drivers
General Description

Features

These devices contain six independent drivers, each of
which performs the logic NOR function. Each driver has increased output drive capability to allow the driving of high
capacitive loads.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oXide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with advanced
low power Schottky TTL counterpart

Connection Diagram
Dual-In-Une Package

vee

68

6A

6Y

58

5A

5V

48

4A

IA

18

IV

2A

28

2V

3A

38

3V

4V

TLlF/6327-1

Order Number DM74AS805BWM or DM74AS805BN
See NS Package Number M20B or N20A

Function Table
Y=A+B
Inputs

H

L

Output

A

B

Y

L
L
H
H

L
H
L
H

H
L
L
L

= High logic Level
= Low Logic Level

II
3-161

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
O"Cto +70"C
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

-65·C to + 150·C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

4.5

5

5.5

Units

Vee

Supply Voltage

VIH

High Level Input Voltage

V

Vil

Low Level Input Voltage

0.8

V

V

2

10H

High Level Output Current

-48

mA

10l

Low Level Output Current

48

mA

TA

Free Air Operating Temperature

70

·C

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

10H = -2 mA, Vee = 4.5V to 5.5V
10H = -3 mA, Vee = 4.5V
10H = Max, Vee = 4.5V

Min

Typ

Max

Units

-1.2

V

Vee - 2
2.4

V

2

VOL

Low Level Output
Voltage

Vee = 4.5V, 10l = Max

II

Input Current @
Max Input Voltage

Vee = 5.5V, VIH = 7V

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

IJA

III

Low Level Input Current

Vee = 5.5V, Vil = O.4V

-0.5

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

Icc

Supply Current

Vee = 5.5V

0.35

-50

0.5

V

0.1

mA

-135

-200

mA

Outputs High

6.5

10

mA

Outputs Low

18

32

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tplH

Propagation Delay Time
Low to High Level Output

tpHl

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
Rl = 5000.
Cl = 50pF

Note 1: See Section 1 for test waveforms and output load.

3·162

Min

Max

Units

1

4.3

ns

1

4.3

ns

,----------------------------------------------------------------------, c
_

i:
......

National

~

Semiconductor
Corporation

co

:;
OJ

DM74AS808B Hex 2-lnput AND Driver
General Description

Features

This device contains six independent drivers, each of which
performs the logic AND function. Each driver has increased
output drive capability to allow the driving of high capacitive
loads.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with advanced
low power Schottky TTL counterpart

Connection Diagram
Dual-In-Llne Package

vee

68

58

6A

5A

5V

48

4A

2V

3A

38

3Y

16

IA

18

2A

IV

28

Order Number DM74AS808BWM or DM74AS808BN
See NS Package Number M20B or N20A

Function Table
y= AB

Inputs

Output

A

B

V

L
L
H
H

L
H
L
H

L
L
L
H

H

~

High Logic Level

L

~

Low Logic Level

3-163

TLlF/632B-l

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales OffIce/
Distributors for availability and specifications..
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device canfl()t be guarant99d. The device should fl()t be operated at thesalimits. The
parametric values defined in the "Electrical Characteristics"
table are fl()t guaranteed st the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

O"Cto +70"C
-65"Cto + 150"C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-48

mA

10L

Low Level Output Current

48

mA

TA

Free Air Operating Temperature

70

·C

2

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

II

Input Current @
Max Input Voltage

IIH

High LevE!I'lnput Current

IlL

Low Level Input Current

10

Output Drive Current

lee

Supply Current

Conditions

= 4.5V, II = -18 mA
10H = - 2 mA, Vee = 4.5V to 5.5V
10H = -3 mA, Vee = 4.5V
10H = Max, Vee = 4.5V
Vee = 4.5V, 10L = Max

Min

= 5V, TA = 25·C.
Typ

Vee

Vee

Units
V

Vee -2
2.4

V

2
0.35

= 5.5V, VIH = 7V

= 5.5V, VIH = 2.7V
= 5.5V, VIL = 0.4V
Vee = 5.5V, Vo = 2.25V
Outputs High
Vee = 5.5V

Max
-1.2

0.5

V

0.1

mA

Vee

20

pA.

Vee

-0.5

mA

-200

mA

8

13

mA

20

33

mA

-50

Outputs Low

-135

Switching Characteristics over recommended operating free air temperature range (Note 1)
Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Symbol

Note 1: See SecUon 1 for _

waveformS and output load.

3-164

Min

Max

Units

1

6

ns

1

6

ns

.------------------------------------------------------------------.c
_

iii:
.....

NaHonal
Semiconductor
CorporaHon

E
...
CI

DM74AS810 Quad 2-lnput Exclusive-NOR Gate
• Advanced oxide-isolated. ion-implanted Schottky TIL
process
• Functionally and pin for pin compatible with advanced
low power Schottky TTL counterpart
• Improved AC performance over advanced low power
Schottky counterparts
• PNP input design reduces input loading

General Description
This device contains four independent gates each of which
performs the logic exclusive-NOR function.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Line Package
vec

B4

A1

81

V1

A2

82

V2

TUF/6724-1

Order Number DM74AS810N
See NS Package Number N14A·

Function Table
Y=AEIlB
Inputs

H

Output

A

B

Y

L
L
H
H

L
H
L
H

H
L
L
H

= High Logic Level. L = Low Logic Level

I
·Contact your local NSC representative about surface mount (M) package availability.

3-165

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Operating Free Air Temperature Range
Storage Temperature Range

O'Cto +70'C
-65'C to + 150'C

Recommended Operating Conditions
Symbol

/

Parameter

Min

Nom

Max

Units

4.75

5

5.25

V

Vcc

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.8

V

V

2

10H

High Level Output Current

-2

mA

10l

Low Level Output Current

20

mA

TA

Free Air Operating Temperature

70

'C

0

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Conditions

=

=

VI

Input Clamp Voltage

Vcc

VOH

High Level Output
Voltage

Vcc = 4.5V to 5.5V
10H = Max

VOL

Low Level Output
Voltage

Vee = Min, 10l = Max
VIH = Min, Vil = Max

II

Input Current @ Max
Input Voltage

Vee

Min, II

=

Max, VI

=
=
Vcc =
Vee =

Min

Typ
(Note 1)

-18 mA

=

Vee - 2V

Units

-1.2

V

3.4
0.35

5.5V

= 2.7V
= 0.5V
Max, Vo = 2.25V

Max

V
0.5

V

0.1

mA

IIH

High Level Input Current

Vcc

Max, VI

20

p.A

III

Low Level Input Current

Vcc

Max, VI

-0.5

mA

10

Output Drive Current

-112

mA

ICCH

Supply Current with
Outputs High

18

26

mA

Icel

Supply Current with
Outputs Low

25

36

mA

-30

Max
(Note 3)

Vee = Max
(Note 2)

,

Nola 1: All typical. are at Vcc ~ 5V. TA ~ 25'C.
Nola 2: ICCl is measured with all outputs open, one input of each gala at 4.5V, and the other inputs grounded.
Note 3: ICCH is measured with all outputs open and all Inputs at 4.5V.

3·166

Switching Characteristics over recommended operating free air temperature range (Note t)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Other Input Low
Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Note 1: See Section 1 for

Other Input High
Vee =4.5V to 5.5V
RL = 500n
CL=50pF

Min

Max

Units

1

6.5

ns

1

6.5

ns

2

7

ns

2

7

ns

test waveforms and output load.

EI
3-167

~ r-------------------------------------------------------------------------------~
~

~ _NatiOnal
::f
Semiconductor
Si!
Corporation

c

DM74AS811 Quad 2-lnput Exclusive-NOR Gates
with Open-Collector Outputs
General Description

Features

This device contains four independent gates. each of which
performs the logic exclusive-NOR function. The open-collector outputs require external pull-up resistors for proper
logical operation.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated. ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with advanced
low power Schottky TTL counterpart
• Improved AC performance over advanced low power
Schottky counterparts
• Open collector outputs for wired AND cascading
• PNP input design reduces input loading

Pull-Up Resistor Equations

RMIN =

Vee (Max)

-

VOL

IOL - Ns (lIU
Where: N1 (IOHI = total maximum output high current for all
outputs tied to pull-up resistor
N2 (IIHI = total maximum input high current for all
inputs tied to pull-up resistor
Ns (lIU = total maximum input low current for all inputs tied to pull-up resistor

Connection Diagram

Dual·ln·Line Package

vee

A1

B1

A4

Y4

Y1

A2

Y2

B2

Order Number DM74ALS811N
See NS Package Number N14A·

Function Table
Y=AeB
Inputs

H
L

Output

A

B

Y

L

L

H

L

L

H

H

L

L

H

H

H

= High Lagle Level
= Low Logie Level

·Contact your local NSC representative about surface mount (M) package availability.

3-168

TL/F/6725-1

c

a:::::
.....

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaran·
teed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Oparating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Off State Output Voltage

7V

Operating Free Air Temperature Range

O"Cto +70"C
-65·C to + 150·C

Storage Temperature Range

Recommended Operating Conditions
Symbol

Parameter

Vcc

Supply Voltage

VIH

High Level Input Voltage

Min

Nom

Max

Units

4.5

5

5.5

V
V

2

VIL

Low Level Input Voltage

0.8

VOH

High Level Output Voltage

5.5

V

IOL

Low Level Output Current

20

mA

TA

Free Air Operating Temperature

70

·C

0

V

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol

Parameter

Conditions

Typ
(Note 1)

Min

Max

Units

VIK

Input Clamp Voltage

Vcc = Min,ll = -18 mA

-1.2

V

ICEX

High Level Output Current
Current

Vee = Min, Vo = 5.5V
VIL = Max, VIH = Min

100

/J- A

VOL

Low Level Output
Voltage

Vee = Min,lOL = Max
VIH = Min, VIL = Max

0.5

V

II

Input Current @ Max
Input Voltage

Vee = Max, VI = 7V

0.1

mA

IIH

High Level Input Current

Vcc = Max, VI = 2.7V

20

/J- A

ICCH

Supply Current with
Outputs High

Vee = Max
(Note 3)

19.6

28

mA

ICCL

Supply Current with
Outputs Low

Vee = Max
(Note 2)

25

36

mA

0.35

Note 1: All typical. are at Vee = sv. TA = 2S'C.
Note 2: ICCl is measured with all outputs open, one input of each at 4.SV. and the other inputs grounded.
Note 3: ICCH is measured with all outputs open and all inputs at 4.SV.

Switching Characteristics over recommended operating free air temperature range (Note 4)
Parameter

Conditions

tpLH

Symbol

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Other Input Low
Vee = 4.5V to 5.5V
RL = 5000.
CL = 50pF

tpLH

Propagation Delay TIme
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Other Input High
Vee = 4.5V to 5.5V
RL = 5000.
CL = 50pF

Note 4: See Section 1 for test waveforms and output load.

3·169

Min

Max

Units

5

45

ns

1

8.5

ns

5

45

ns

2

9

ns

E
....
....

_

National

Semiconductor
Corporation

DM74AS832B Hex 2-lnput OR Drivers
General Description

Features

These devices contain six independent drivers, each of
which performs the logic OR function. Each driver has increased output drive capability to allow the driving of high
capacitive loads.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin for pin compatible with Schottky
and low power Schottky TTL counterpart
• Improved AC performance over Schottky and low power Schottky counterparts

Connection Diagram
Dual-In-Llne Package

vee

6B

6A

IA

IB

IV

5B

5A

5Y

4B

4A

3A

3B

3Y

Order Number DM74AS832BWM or DM74AS832BN
See NS Package Number M20B or N20A

Function Table
Y=A+B
Inputs

H

Output

A

B

Y

L
L
H
H

L
H
L
H

L
H
H
H

= High Logic Level

L = Low Legic Level

3-170

4Y

TUF/6329-1

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

O·Cto +70·C
-65·Cto + 150·C

Storage Temperature Range

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Low Level Input Voltage

0.8

V

High Level Output Current

-48

rnA

48

rnA

70

·C

Vee

Supply Voltage

V,H

High Level Input Voltage

V,L
10H

V

2

10L

Low Level Output Current

TA

Free Air Operating Temperature

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

Symbol

Parameter

Conditions

=

=

V,K

Input Clamp Voltage

Vee

VOH

High Level Output
Voltage

= - 2 rnA, Vee = 4.5V to 5.5V
= -3 rnA, Vee = 4.5V
10H = Max, Vee = 4.5V
Vee = 4.5V, 10L = Max

4.5V, I,

Min

Vee - 2

10H

2.4

Low Level Output
Voltage

I,

Input Current at Max
Input Voltage

Vee

=

5.5V, V,H

I'H

High Level Input Current

Vee

5.5V, V,H

I,L

Low Level Input Current

Vee

10

Output Drive Current

Vee

Icc

Supply Current

Vee

=
=
=
=

=

=

25·C.

Max

Units

-1.2

V

V

2
0.35

7V

= 2.7V
5.5V, V,L = O.4V
5.5V, Vo = 2.25V
5.5V

5V, TA

Typ

-18 rnA

10H

VOL

=

-50

0.5

V

0.1

rnA

20

/LA

-0.5

rnA
rnA

-135

-200

Outputs High

11

17

rnA

Outputs Low

22

36

rnA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

Symbol

Min

Max

Units

1

6.3

ns

1

6.3

ns

Note 1: See Section 1 for test waveforms and output load.

3-171
" " - -

-----------

~

'"

~
:::&i
C

r----------------------------------------------------------------------------,

~ Semiconductor
Natlonal

Corporation

DM74AS873 Dual 4-Bit D-Type
Transparent Latches with TRI-STATE® Outputs
General Description
These dual 4-bit registers feature totem-pole TRI-STATE
outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these registers
with the capability of being connected directly to and driving
the bus lines in a bus-organized system without need for
interface or pull-up components. They are particularly attractive for implementing buffer registers, 1/0 ports, bidirectional bus drivers, and working registers.
The eight latches of the AS873 are transparent Ootype
latches meaning that while the enable (G) is high the Q
outputs will follow the data (0) inputs. When the enable is
taken low the output will be latched at the level of the data
that was set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are off.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package while all
outputs are on the other side.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
.• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly
• Space Saving 300 Mil Wide Package
• Bus structured pinout

Connection Diagram
Dual-In-Llne Package
ENABLE
lG

lQl

lQ2

lQ3

lQ4

2Q2

2Q3

2Q4

ENABLE
2G

2CLR
13

4
102

5
103

6
104

7
201

8
202

2D3

10
204
TL/F/6330-1

Order Number DM74AS873NT
See NS Package Number N24C

3-172

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications_
Supply Voltage
Input Voltage

Note: The ''Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V
7V

Voltage Applied to Disabled Output

5.5V

Operating Free Air Temperature Range

O·Cto +70·C

Storage Temperature Range

-65·C to + 150·C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Low Level Input Voltage

0.8

V

Vee

Supply Voltage

V,H

High Level Input Voltage

V,L

2

V

10H

High Level Output Current

-15

mA

10L

Low Level Output Current

48

mA

tw

Pulse Width

I
I

Enable High

5.5

Clear Low

3.5

tsu

Data Setup Time

2,J,

tH

Data Hold Time

3,J,

Free Air Operating Temperature
TA
The (J,) arrow indicates the negative edge of the enable is used for reference.

ns
ns
ns

0

·C

70

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

Min

Typ

Max

Units

-1.2

V

V,K

Input Clamp Voltage

Vee = 4.5V, I, = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V, V,L = Max
10H = Max

VOL

Low Level Output
Voltage

Vee = 4.5V, V,H = 2V
10L = Max

I,

Input Current at Max
Input Voltage

Vee = 5.5V, V,H = 7V

I'H
I,L

High Level Input Current

Vee = 5.5V, V,H = 2.7V

20

",A

Low Level Input Current

Vee = 5.5V, V,L = 0.4V

-0.5

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

-112

mA

10ZH

Off-State Output Current,
High Level Voltage Applied

Vee = 5.5V, V,H = 2V
Vo = 2.7V

50

",A

10ZL

Off-State Output Current,
Low Level Voltage Applied

Vee = 5.5V, V,H = 2V
Vo = O.4V

-50

",A

Icc

Supply Current

Vee = 5.5V
Outputs Open

10H = - 2 mA, Vee = 4.5V to 5.5V

2.4

V

3.3

V

Vee -2
0.35

-30

0.5

V

0.1

mA

Outputs High

68

110

mA

Outputs Low

67

109

mA

Outputs Disabled

80

129

mA

3-173

Switching Characteristics
over recommended operating free air temperature range (Note 1). All typical values are measured at Vee

Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

tpLH

=

5V, TA

=

25°C.

From

To

Min

Max

Unlta

Data

AnyQ

3

6.5

ns

Data

AnyQ

3

6

ns

Propagation Delay Time
Low to High Level Output

Enable

AnyQ

6

11.5

ns

tpHL

Propagation Delay Time
High to Low Level Output

Enable

AnyQ

4

7.5

ns

tPZH

Output Enable Time
to High Level Output

Output
Control

AnyQ

2

6.5

ns

tPZL

Output Enable Time
to Low Level Output

Output
Control

AnyQ

4

9.5

ns

tpHZ

Output Disable Time
from High Level Output

Output
Control

AnyQ

2

6.5

ns

tpLZ

Output Disable Time
from Low Level Output

Output
Control

AnyQ

2

7.5

ns

tpHL

Propagation Delay Time
High to Low Level Output

Clear

AnyQ

3

8.5

ns

Note 1: See Section 1 for lest waveforms and output load.

Function Table
Inputa
CLR

D

EN

OC

x

x

L
H
H
H

X

X
X

H
L
L
L
L

H
L

X

H
H
L

L = Low Stele, H = High Stete, X = Don't Care
Z = High Impedance Stete
= Previous Condition of Q

00

3·174

Output
Q

Z
L
H
L
Qo

.------------------------------------------------------------------.0
i:

Logic Diagram

"

~~

23_t.,;>_ _.,
I ENA8LE __

I~_~~>-----t----------,
CONTROL
ICLUR-'-- ............

101

3

102

4

103

5

104

&

------1

1
201 ......

m

B

203

9

204 10

-+________~

20LITPtrr_~1I~()~__
CONTROL
2 EUBLE-'-'-' ""........-

....
TLlF/6330-2

3·175

~ Semiconductor
National

Corporation

DM7 4AS87 4 Dual 4-Bit D-Type
Edge-Triggered Flip-Flops
General Description
These dual 4-bit inverting registers feature totem-pole TRISTATE® outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide
these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system
without need for interface or pull-up components. They are
particularly attractive for implementing buffer registers, 1/0
ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the AS874 are edge-triggered D-type
flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D
inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package, while all
outputs are on the other side.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TIL
process
• TRI-STATE buffer-type outputs drive bus lines directly
• Space saving 300 mil wide package
• Bus structured pinout

Connection Diagram
Dual-In-Line Package
1CLK

1Q1

1Q4

2Q1

2Q2

2Q3

2Q4

2CLR
13

3
101

4
102

5
103

7
201

104

8
202

9
203

10
204

GNO
TUF/6331-1

Order Number DM74AS874NT
See NS Package Number N24C·

f
'Contact your local NSC reprasentative about surface mount (M) package availability.

3-176

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and speclflcatlons_
Supply Voltage

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V

Input Voltage

7V

Voltage Applied to Disabled Output

5.5V

Operating Free Air Temperature Range
Storage Temperature Range

O·Cto +70'C
- 65·C to + 150'C

Recommended Operating Conditions
Symbol

Parameter

Vcc

Supply Voltage

VIH

High Level Input Voltage

Min

Nom

Max

4.5

5

5.5

Units
V
V

2

VIL

Low Level Input Voltage

0.8

V

IOH

High Level Output Current

-15

mA

IOL

Low Level Output Current

fCLK

Clock Frequency

twCLK

Width of Clock Pulse

0
High

3

Low

6

48

mA

80

MHz
ns

tWCLR

Width of Clear Pulse

Low

2

ns

Isu

Setup Time

Data

4t

ns

Clear Inactive

5t

tH

Data Hold Time

TA

Free Air Operating Temperature

The ( t)

ns

1t

·C

70

0

arrow Indicates the positive edge of the Clock is used for reference.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V, VIL = VIL Max,
IOH = Max
IOH = -2 mA, Vee = 4.5V to 5.5V

VOL

Low Level Output
Voltage

Vee = 4.5V, VIH = 2V,
IOL = Max

II

Input Current at Max
Input Voltage

Vee = 5.5V, VIH = 7V

Min

2.4

Typ

Max

Units

-1.2

V

3.3

V

Vec - 2
0.35

0.5

V

0.1

mA

IIH

High Level Input Current

Vec = 5.5V, VIH = 2.7V

20

/LA

IlL

Low Level Input Current

Vee = 5.5V, VIL = 0.4V

-0.5

mA

10

Output Drive Current

Vcc = 5.5V, Vo = 2.25V

-112

mA

10ZH

Off-State Output Current,
High Level Voltage
Applied

Vce = 5.5V, VIH = 2V,
Vo = 2.7V,

50

/LA

Off-State Output Current,
Low Level Voltage
Applied

Vcc = 5.5V, VIH = 2V,
Vo = O.4V

-50

/LA

Supply Current

Vee = 5.5V
Outputs Open

10ZL

lee

3-177

-30

Outputs High

82

133

Outputs Low

92

149

Outputs Disabled

100

160

mA

I

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions
Vee' = 4.5V to 5.5V
RL = 500.0.
CL = 50pF

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

From

To

AnyQ

Propagation Delay Time
High to Low Level Output

Clock

AnyQ

tPZH

Output Enable Time
to High Level Output

Output
Control

AnyQ

tpZL

Output Enable Time
to Low Level Outpu1

Output
Control

AnyQ

tpHZ

Output Disable Time
from High Level Output

Output
Control

AnyQ

tpLZ

Output Disable Time
from Low Level Output

Output
Control

AnyQ

Clear

AnyQ

Propagation Delay Time
High to Low Level Output
Note 1: See Section 1 for test waveforms and output load.

tpHL

Function Table
Inputs

Output

CLR

0

CLK

OC

Q

X

X
X

X
X

H
L

t
t

X

L

H
L
L
L
L

Z
L
H
L
QO

= Low Stete, H = High State, X = Don't Care
t = Positive Edge Transition
Z = High Impedance State
Qo = Previous Ccndltlon of Q
L

3-178

Max

80
Clock

L
H
H
H

Min

Units
MHz

3

8.5

ns

4

10.5

ns

2

7

ns

3

10.5

ns

2

6

ns

2

7.5

ns

4

11.5

ns

Logic Diagram
1 CLOCK ...;2:.:,3-----11>0-_-,
liiUrPUr
CONTROL

2

101 -=.--~I-+-~

102

103

....;,4--.....,t-+---t

5

---+-+---4

104 ....::,6

104

--------4

201 ....;,.7

---+-+---4

202 ....;,.8

203 -=.9_ _--11-+---1

204 10

2 OUTPUT
CONTROL

11

2 CLOCK....:.;:14--11>0-_...J
TUF/6331-2

3·179

~

~....

:E

r----------------------------------------------------------------------------,

~ Semiconductor
National

.

CorporaHon

Q

DM74AS876 Dual 4-Bit D-Type Edge-Triggered
Flip-Flops with TRI-STATE® Outputs
General Description
These inverting dual 4-bit registers feature totem-pole TRISTATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide
these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system
without need for interface or pull-up components. They are
particularly attractive for implementing buffer registers, lID
ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the AS876 are edge-triggered inverting D-type flip-flops. On the positive transition of the clock,
the Q outputs will be set to the complement of the logic
states that were set up at the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package, while all
outputs are on the other side.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced OXide-isolated, ion-implanted Schottky TIL
process
• TRI-STATE buffer-type outputs drive bus lines directly
• Space saving 300 mil wide package
• Bus structured pinout

Connection Diagram
Dual-In-Llne Package
lCLK

102

103

104

201

202

203

204

2CLK

2PRE
13

3
101

4
102

5
103

7
201

104

8
202

9
203

10
204

GNO
TliF/6332-1

Order Number DM74AS876NT
See NS Package Number N24C'

'Contact your local NSC representative about surface mount (M) package availability.

3-180

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V
7V

Input Voltage
Voltage Applied to Disabled Output

5.5V

Operating Free Air Temperature Range
Storage Temperature Range

O'Cto +70'C
-65'C to + 150'C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-15

mA

10L

Low Level Output Current

48

mA

feLK

Clock Frequency

80

MHz

tW(eLK)

Width of Clock Pulse

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

V

2

0
High

3

Low

6

ns

tW(PR~

Width of Preset Pulse

Low

2

ns

tsu

Data

Data

4f

ns

Preset Inactive

5f

tH

1t

Data Hold Time

Free Air Operating Temperature
TA
The (i) arrow indicates the positive edge of the Clock is used for reference.

ns

0

·C

70

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

II

Input Current at Max
Input Voltage

IIH

High Level Input Current

IlL

Low Level Input Current

10

Output Drive Current

10ZH

Off-State Output Current,
High Level Voltage
Applied

10ZL

Icc

Conditions

= 4.5V, II = -18 mA
Vee = 4.5V, VIL = VIL Max,
10H = Max
10H = -2 mA, Vee = 4.5V to 5.5V
Vee = 4.5V, VIH = 2V,
10L = Max
Vee = 5.5V, VIH = 7V

Min

=

5V, T A
Typ

Vee

= 5.5V, VIH = 2.7V
= 5.5V, VIL = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V, VIH = 2V,
Vo = 2.7V,

2.4

=

25'C.
Max

Units

-1.2

V

3.3
V

Vee - 2
0.35

0.5

V

0.1

mA

Vee

20

/LA

Vee

-0.5

mA

-112

mA

50

/LA

-50

/LA

OIl-State Output Current,
Low Level Voltage
Applied

Vee = 5.5V, VIH
Vo = 0.4V

Supply Current

Vee = 5.5V
Outputs Open

=

-30

2V,

3·181

Outputs High

88

142

Outputs Low

94

150

Outputs Disabled

100

160

mA

CD
.....

~

c:c

•.....

:E
Q

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

tpHL

From

To

Min

Max

80

a

Clock

Any

Propagation Delay Time
High to Low Level Output

Clock

Any 0

tPZH

Output Enable Time
to High Level Output

Output
Control

Any 0

tPZL

Output Enable Time
to Low Level Output

Output
Control

Any

tpHZ

Output Disable Time
from High Level Output

Output
Control

AnyO

tpLZ

Output Disable Time
from Low Level Output

Output
Control

Any 0

tpHL

Propagation Delay Time
High to Low Level Output

Preset

Any 0

a

MHz

3

8.5

ns

4

10.5

ns

2

7

ns

3

10.5

ns

2

6

ns

2

6

ns

4

10

ns

Note 1: See Section 1 for lesl waveforms and output load.

Logic Diagram

Function Table
Inputs

1 OUTPUT 2
CONTROL

I

PRE 1

+-+-101

3_ _ _
101..::

Output

PRE

D

eLK

oc

Q

x

x

L
H
H
H

X

X
X

H
L

t
t

Z
L
L
H

X

L

H
L
L
L
L

L = Low Stele. H = High Stele. X =

102...;4_ _ _+-+-I

t = Positive Edge Transition
Z

= High Impedenoe Stele

c:io = Previous CondHion of Q

+-+-1

103 ..::5_ _ _

+-+-fi)1

1~..::6_ _ _

CONTROL

TLlF/6332-2

3·182

Units

Don~

00
Care

.-------------------------------------------------------------------,0

III

!i:

National
Semiconductor
Corporation

I

DM74AS878 Dual 4-Bit D-Type
Edge-Triggered Flip-Flops with Synchronous Clear
General Description
These dual 4-bit registers feature totem-pole TRI-STATE'"
outputs designed specifically for driving highly-capacitive or
relatively low-impedance loads. The high-impedance state
and increased high-logic-level drive provide these registers
with the capability of being connected directly to and driving
the bus lines in a bus-organized system without need for
interface or pull-up components. They are particularly attractive for implementing buffer registers, 110 ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the AS878 are edge-triggered D-type
flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D
inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package while all
outputs are on the other side.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly
• Synchronous clear
• Bus structured pinout

Connection Diagram
Oual-In-Line Package

101

102

103

104

201

202

203

102

103

104

201

202

203

204

2CLK

2CLR

TL/F/6333-1

Order Number DM74AS878N
See NS Package Number N20A'

'Contact your local NSC representative about surface mount (M) package availability.

3-183

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V

Input Voltage

7V

Voltage Applied to Disabled Output

5.5V

Operating Free Air Temperature Range

O·Cto +70"C
- 65·C to + 150·C

Storage Temperature Range

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-15

mA

10L

Low Level Output Current

feLK

Clock Frequency

tWeLK

Width of Enable Pulse

tsu

tH

2

V

48

mA

80

MHz

0

Data Setup Time

Data Hold Time

High

4

Low

6

Data

4t

CLR

6t

Data

2t

CLR

ot

Free Air Operating Temperature
TA
The (t) arrow indicates the positive edge of the Clock is used for reference.

ns

ns

ns
70

0

ns

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

Symbol

Parameter

Conditions

= 4.5V, II = -18 mA
Vee = 4.5V, VIL = VIL Max,
10H = Max
10H = -2 mA, Vee = 4.5Vto 5.5V
Vee = 4.5V, VIH = 2V,
10L = Max
Vee = 5.5V, VIH = 7V

Min

=

5V, T A

Typ

=

25·C.

Max

Units

-1.2

V

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

II

Input Current @
Max Input Voltage

IIH

High Level Input Current

Vee

20

/J- A

IlL

Low Level Input Current

Vee

-0.5

mA

10

Output Drive Current

-112

mA

10ZH

Off-State Output Current,
High Level Voltage
Applied

50

/J- A

-50

/J- A

10ZL

lee

Vee

= 5.5V, VIH = 2.7V
= 5.5V, VIL = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V, VIH = 2V,
Vo = 2.7V

Off-State Output Current,
Low Level Voltage
Applied

Vee = 5.5V, VIH
Vo = 0.4V

Supply Current

Vee = 5.5V
Outputs Open

=

2.4

V

3.3

V

Vee- 2
0.35

-30

0.5

V

0.1

mA

2V,

3·184

Outputs High

82

132

Outputs Low

96

155

Outputs Disabled

100

160

mA

0

!!:
......

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

From

DM74AS878

To

Min
fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

AnyQ

Propagation Delay Time
High to Low Level Output

Clock

AnyQ

tpZH

Output Enable Time
to High Level Output

Output
Control

AnyQ

tPZL

Output Enable Time
to Low Level Output

Output
Control

AnyQ

tpHZ

Output Disable Time
from High Level Output

Output
Control

AnyQ

Output
Control

AnyQ

Output Disable Time
from Low Level Output
Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

Max

3

8.5

ns

4

10.5

ns

2

7

ns

3

10.5

ns

2

6

ns

2

6

ns

Function Table
Inputs

I OUTPUT 2
CONTROL

Output

ClR

0

ClK

OC

Q

X

X
X

X

H
L
L
L
L

Z
L
H
L
Qo

L
H
H
H

H
L

t
t
t

X

L

= Low State, H = High State, X = Don't Care
t = Pos"lve Edge Trans"ion
Z = High Impedance State
L

00 = Previous Condition of 0

203

2 OUTPUT II
CONTROL

TLlF/6333-2

3-185
----------

t

0

co
......
co

MHz

80
Clock

tpLZ

Units

NatiOnal

~ Semiconductor
Corporation

DM74AS879 Dual 4-Bit D-Type
Edge-Triggered Flip-Flops with
TRI-STATE® Outputs and Synchronous Clear
General Description
These inverting dual 4-bit registers feature totem-pole TRISTATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide
these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system
without need for interface or pull-up components. They are
particularly attractive for implementing buffer registers, 1/0
ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the AS879 are edge-triggered inverting Ootype flip-flops. On the positive transition of the clock,
the Q outputs will be set to the complement of the logic
states that were set up at the 0 inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package while all
outputs are on the other side.

Features
• SWitching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vcc range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly
• Synchronous preset
• Bus structured pinout

Connection Diagram
Dual-In-Line Package
204

2CLK

2CLR

103
TL/F/6334-1

Order Number DM74AS879N
See NS Package Number N20A*

'Contact your local NSC representative about surface mount (M) package availability.

3-166

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V

Input Voltage

7V

Voltage Applied to Disabled Output

5.5V

Operating Free Air Temperature Range
Storage Temperature Range

O"Cto +70"C
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

Parameter

Vcc

Supply Voltage

VIH

High Level Input Voltage

Min

Nom

Max

4.5

5

5.5

Units
V

2

V

Vil

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-15

rnA

10l

Low Level Output Current

fClK

Clock Frequency

tWClK

Width of Clock Pulse

tsu
tH

TA

0

Data Setup Time

Data Hold Time

High

4

Low

6

Data

4t

CLR

6t

Data

2t

CLR

ot

Free Air Operating Temperature

48

rnA

80

MHz
ns

ns

ns

0

·C

70

The (t) arrow indicates the positive edge of the clock is used for reterence.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee

Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

Conditions

= 4.5V, II = -18 rnA
VCC = 4.5V, Vil = Max,
10H = Max
10H = - 2 rnA, Vee = 4.5V to 5.5V
Vee = 4.5V, VIH = 2V,
10l = Max
Vee = 5.5V, VIH = 7V

Min

=

5V, T A

Typ

Vee

2.4

=

25·C.

Max

Units

-1.2

V

3.3

V

Vee - 2

VOL

Low Level Output
Voltage

II

Input Current @
Max Input Voltage

IIH

High Level Input Current

Vec

20

p.A

Vee

-0.5

rnA

-112

rnA

50

p.A

-50

p.A

III

Low Level Input Current

10

Output Drive Current

10ZH

Off-State Output Current,
High Level Voltage
Applied

IOZl

ICC

= 5.5V, VIH = 2.7V
= 5.5V, Vil = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V, VIH = 2V,
Vo = 2.7V

Off-State Output Current,
Low Level Voltage
Applied

Vee = 5.5V, VIH
Vo = 0.4V

Supply Current

Vee = 5.5V
Outputs Open

=

0.35

-30

0.5

V

0.1

rnA

2V,

3-187

142

Outputs High

88

Outputs Low

94

150

Outputs Disabled

100

160

rnA

Symbol

Parameter

' Conditions

fMAX

Maximum Clock Frequency

tpLH

Propagation Delay Time
Low to High Level Output

Vee = 4.5Vto 5.5V
RL = 500n
CL = 50pF

tpHL

From

To

Min

Max

80
Clock

Any 0

Propagation Delay Time
High to Low Level Output

Clock

Any 0

tPZH

Output Enable Time
to High Level Output

Output
Control

Any 0

tpZL

Output Enable Time
to Low Level Output

Output
Control

AnyO

tpHZ

Output Disable Time
from High Level Output

Output
Control

AnyO

tpLZ

Output Disable Time
from Low Level Output

Output
Control

Any 0

MHz

3

8.5

ns

4

10.5

ns

2

7

ns

3

10.5

ns

2

6

ns

2

6

ns

Note 1: See Section 1 for test waveforms and output load.

Logic Diagram

Function Table
Inputs

L

t
Z

CLR

0

X
L
H
H
H

CONTROL

TLlF/6334-2

3-188

OC

X

X

X

t
t
t

H
L
L
L
L

X
L
= Low Slale, H = High Slale, X = Don'l Care
= Positive Edge TransHion

= High Impedance Stale

00 =

2 OUTPUT 11

Output

Clock

H
L

Previous Condition of Q

Units

Q
Z
H
L
H

00

_

National
Semiconductor
Corporation

DM74AS880 Dual 4-Bit D-Type
Transparent Latches with TRI-STATE® Outputs
General Description
These dual 4-bit inverting registers feature totem-pole TRISTATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide
these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system
without need for interface or pull-up components. They are
particularly attractive for implementing buffer registers, lID
ports, bidirectional bus drivers, and working registers.
The eight inverting latches of the ASaaO are transparent 0type latches meaning that while the enable (G) is high the Q
outputs will follow the complement of the data (D) inputs.
When the enable is taken low the output will be latched at
the complement of the level of the data that was set up.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are off.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package while all
outputs are on the other side.

Features
• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• TRI-STATE buffer-type outputs drive bus lines directly
• Space saving 300 mil wide package
• Bus structured pinout

Connection Diagram
Dual·ln·Une Package
ENABLE
lG

101

ENABLE
2G

102

2PRE
13

3
101

4
102

5
103

7

6
104

201

8
202

9
203

10
204

GNO
TL/F/6335-1

Order Number DM74AS880NT
See NS Package Number N24C·

'Contact your local NSC representative about surfaoa mount (M) package availability.

3·189

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be gUBTBnteed. The device should not be operated at these limits. The
ptlI'Bmetric values defined in the "Electrical Characteristics"
table sre not guaranteed st the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V
5.5V

Voltage Applied to Disabled Output
Operating Free Air Temperature Range
Storage Temperature Range

O"C to +70"C
-65"Cto + 150"C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-15

mA

48

mA

10L

Low Level Output Current

tw

Pulse Width

tsu

Data Setup Time

tH

Data Hold TIme

1,J..

TA

Free Air Operating Temperature

I
I

V

2

Enable
Preset Low

2.5

ns

4

ns

2,J..

ns
ns
·C

70

0

The ( J.) arrow indicates the negative edge of the enable is used for r8!erence.

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

VOL

Low Level Output
Voltage

II

Input Current @ Max
Input Voltage

Conditions

= 4.5V,11 = -18 rnA
Vee = 4.5V, VIL = VIL Max,
10H = Max
10H = - 2 rnA, Vee = 4.5V to 5.5V
Vee = 4.5V, VIH = 2V,
10L = Max
Vee = 5.5V, VIH = 7V

Min

=

5V, T A
Typ

Vee

= 5.5V, VIH = 2.7V
= 5.5V, VIL = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V, VIH = 2V,
Vo = 2.7V

2.4

=

25·C.
Max

Units

-1.2

V

3.3
V

Vee - 2
0.35

0.5

V

0.1

rnA

IIH

High Level Input Current

Vee

20

poA

IlL

Low Level Input Current

Vee

-0.5

rnA

10

Output Drive Current

-112

rnA

10ZH

Off-State Output Current,
High Level Voltage
Applied

50

poA

-50

poA

10Zl

lee

Off-State Output Current,
Low Level Voltage
Applied

Vee = 5.5V. VIH
Vo = 0.4V

Supply Current

Vee = 5.5V
Outputs Open

=

-30

2V,

3-190

Outputs High

73

118

Outputs Low

76

122

Outputs Disabled

86

137

rnA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay TIme
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 5000
CL = 50pF

tpLH

From

To

Data

Any 0

Data

Any 0

Propagation Delay Time
Low to High Level Output

Enable

Any 0

tpHL

Propagation Delay Time
High to Low Level Output

Enable

Any 0

tPZH

Output Enable Time
to High Level Output

Output
Control

AnyO

tpZL

Output Enable Time
to Low Level Output

Output
Control

Any 0

tpHz

Output Disable Time
from High Level Output

Output
Control

Any 0

tpLZ

Output Disable Time
from Low Level Output

Output
Control

Any 0

Preset

AnyO

Propagation Delay Time
High to Low Level Output
Note 1: See Section 1 for test wavefonns and output loed.

tpHL

Min

Max

Units

4

9.5

ns

4

8.5

ns

6

11.5

ns

4

8

ns

2

7.5

ns

4

10

ns

2

6.5

ns

2

8

ns

4

10

ns

Function Table
Inputs

PRE

0

EN

OC

X
L
H
H
H

X
X
H
L
X

X
X
H
H
L

H
L
L
L
L

Output
Q

Z
L
L
H

00

L ~ Low State. H ~ High State, X ~ Don't Gare

Z ~ High Impedance State

00 ~ Previous Condition of a

II
3·191

3·192

_National
Semiconductor
Corporation

DM7 4AS881 B 4-Bit Arithmetic Logic
Unit/Function Generator
General Description

Features

The DM74AS881 8 is an arithmetic logic unit (ALU)/function
generator that has a complexity of 77 equivalent gates, respectively, on a monolithic chip. These circuits perform 16
binary arithmetic operations on two 4-bit words, as shown in
Tables I and II. These operations are selected by the four
function-select lines (SO, S1, S2, S3) and include addition,
subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries must
be enabled by applying a low level voltage to the mode
control input (M). A full carry look-ahead scheme is made
available in these devices for fast, simultaneous carry generation by means of two cascade outputs (pins 15 and 17)
for the four bits in the package. When used in conjunction
with the DM74AS882 full carry look-ahead circuits, high
speed arithmetiC operations can be performed. The typical
addition times shown previously illustrate the little additional
time required for addition of longer words when full carry
look-ahead is employed. The method of cascading 'AS882
circuits with these ALUs to provide multi-level full carry lookahead is illustrated under "signal designations."

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Functionally and pin-for-pin compatible with Schottky
TTL counterpart
• Improved AC performance over Schottky counterpart
• Arithmetic operating modes:
Addition
Subtraction
Shift operand A one pOSition
Magnitude comparison
Plus twelve other arithmetic operations
• Logic function modes:
Exclusive-OR
Comparator
AND, NAND, OR, NOR
Plus ten other logic operations
• Full look-ahead for high speed operations on long
words

If high speed is not of importance, a ripple-carry input (Cn)
and a ripple-carry output (Cn +4) are available. However, the
ripple-carry delay has also been minimized so that arithmetic manipulations for small word-lengths can be performed
without external circuitry.

Connection Diagram

Pin Designations

Dual·ln·Une Package
Vee

I

r24

Al

INPUTS
A2 82

81
23

22

21

.

OUTPUTS
83

A3
2G

19

\I

18

G Cn+4 P A=8 F3'
17

16

15

r:

13

14

Designation

Pin Number

Function

A3, A2, A1, AO

19,21,23,2

Word A Inputs

83,82,81,80

18,20,22,1

Word 8 Inputs

S3, S2, S1, SO

3,4,5,6

Function-Select
Inputs

Cn

7

Inv. Carry Input

M

8

Mode Control
Input

10F3,F2,F1,FO

1

,80

2
AD

3

S3

4
S2

5

SI

6
SO

7

C,

8

9

M"FO

10
Fl

I

GNO

Comparator Output

P

15

Carry Propagate
Output

Cn +4

16

Inv. Carry Output

G

17

Carry Generate
Output

Vee

24

Supply Voltage

GND

12

Ground

TL/F/6336-1

Top VIew
Order Number DM74AS881BNT
See NS Package Number N24C o

'Contact your local NSC representative about surface mount (M) package availability.

3-193

Function Outputs

14

11 .1.12
F2

OUTPUTS

I"Pins

13,11,10,9

A= 8 '

I

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air
Temperature Range
Storage Temperature Range

Note: The "Absolute Maximum Ratings-" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical CharacteriStics"
table are not guaranteed at the absolute maximum ratings. _
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

O"Cto +70·C
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VOH

High Level Output Voltage
A = B Output Only

IOH

High Level Output Current

10L
TA

Low Level Output Current

Min

Typ

Max

Units

4.5

5

5.5

V

2

V
V

5.5
All Outputs Except
A = BandG

-2

G

-3

All Outputs Except G

20

G

46

Operating Free Air Temperature

0

mA
mA
·C

70

Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol

Parameter

Min

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V to 5.5V
10H = -2mA

Any Output
ExceptA = B

Vee = 4.5V, 10H = -3 mA

G

Typ
(Note 1)

Max

Units

-1.2

V

Vee -2
2.4

V
3.4

IOH

High Level Output Current

Vee = 4.5V. VOH = 5.5V

A=B

VOL

Low Level Output
Voltage

Vee = 4.5V, 10L = 20 mA

Anyou*ut
Except

0.3

0.5

Vee = 4.5V, IOL = 48 mA

G

0.4

0.5

Input Current @ Max
Input Voltage

II

IIH

IlL

10

High Level Input
Current

Low Level Input
Current

Output Drive Current

Vee = 5.5V, VI = 7V

Vee = 5.5V, VI = 2.7V

Vee = 5.5V, VI = O.4V

Vee = 5.5V, Vo = 2.25V

0.1

!v1lnput

0.1

Any A or B Input

0.3

AnyS Input

0.4

Carry Input

0.6

M Input

20

Any A or B Input

60

AnyS Input

80

Carry Input

120

M Input

-0.5

Any A or B Input

-1.5

AnySlnput

-2

Carry Input

-3

All Outputs
Except A = B
andG
G

-30

-112

3·194

V

mA

/LA

mA

mA

-165
70

Vee = 5.5V
Supply Current
Note 1: AlllypicaJ values are at Vee = 5V, TA = 25"C.

lee

mA

104

mA

Switching Characteristics
Symbol

tpLH

Parameter

Conditions

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

Cn
M
OV
80 = 83 = 4.5V
81 = 82 = OV
(8UMMode)

Any A
orB

OV
M
80=S3=OV
81 = 82 = 4.5V
(DIFFMode)

Any A
orB

M
OV
(SUM or
DIFFMode)

Any A
orB

M
OV
80=83=OV
81 = 82 = 4.5V
(DIFFMode)

Any A
orB

OV
M
80 = S3 = 4.5V
81 = 82 = OV
(8UMMode)

Any A
orB

M
OV
80=S3=OV
81 = 82 = 4.5V
(DIFFMode)

Any A
orB

M
OV
SO = 83 = 4.5V
81 = 82 = OV
(8UMMode)

A; or Bj

Aj or Bj

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

4.5V
M
(Logic Mode)

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

Cn

OV
M
80 = 83 = 4.5V
81 = 82 = OV
(8UM Mode)

M
OV
80=83=OV
81 = 82 = 4.5V
(DIFFMode)

tpHL

From
(Input)

M
OV
80=S3=OV
81 = 82 = 4.5V
(DIFFMode)

AjorBj

Any A
orB

3-195

To
(Output)

CL = 50pF(15pFforA = B)
RL = 5000 (2800 for A = B)
Min

Max

2

9

2

9

2

12

2

12

2

16

2

16

3

9

3

9

2

7

2

7

2

9

2

9

2

8

2

8

2

10

2

10

2

8

2

8

2

10

2

10

2

11

2

11

4

21

4

21

Cn +4

Units

ns

Cn +4

ns

Cn +4

ns

AnyF

ns

G

ns

G

ns

P

ns

P

ns

Fj

ns

Fj

ns

Fj

ns

A=B

ns

II

Switching Characteristics (Continued)
Symbol

tpLH

Parameter

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

Propagation Delay Time,
High-to-Low Level Output

tpLH

Propagation Delay Time,
Low-to-High Level Output

tpHL

From
(Input)

CondlUons

Cn=M=SO=
83 = 4.5V,
81 = 82 = OV,
Equality (Aj = BI
orAj""BJ

Propagation Delay Time,
High-to-Low Level Output

Any A
orB

P

Cn = M = 83 = 4.5V,
81 = 82 = OV,
Equality (A; = Bj
orAl"" Bj)

Any A
orB

Cn+4

Cn = m = 82 = 4.5V,
80 = 81 = 83 = OV,
(Aj=B;=Hor
Aj or Bj = L)

Any A
orB

Cn = M = 82 = 4.5V,
SO = 51 = 53 = OV,
(A;=Bj=Hor
Aj or Bj = L)

Any A
orB

Number
Typical Addition Times
of
Using AS881 and AS882
Bits
1 t04
5t08
9to 16
17 to 64

To
(Output)

5
10
14
19

CL = 50pF(15pFforA = B)
RL = 5000 (2800 for A = B)
Min

Max

2

15

2

15

2

18

2

18

2

15

2

15

2

19

2

19

Units

ns

ns

P

ns

ns

Cn+4

Arlthmetlcl
Logic Units

Package Count
Look-Ahead
carry Generatora

carry Method
Between
ALUs

1
2
30r4
5to 16

0
0
1
2t05

None
Ripple
Full Look-Ahead
Full Look-Ahead

Functional Description
The DM74A8881 B will accommodate active-high or active-low data if the pin designations are interpreted as follows:
Pin Number

2

1

23

22

21

20

19

18

9

10

11

13

7

16

15

17

Active-Low Data (Table I)

AO

BO

A1

B1

A2

B2

A3

B3

FO

F1

F2

'F3

Cn

Cn+4

P

'G

Active-High Data (Table II)

AO

BO

A1

B1

A2

B2

A3

B3

FO

F1

F2

F3

Cn Cn+4

X

y

Subtraction is accomplished by 1's complement addition
where the 1's complement of the subtrahend is generated
internally. The resultant output is A - B-1, which requires
an end-around or forced carry to provide A-B.
The DM74AS881B can also be utilized as a comparator.
The A = B output is internally decoded from the function
outputs (FO, F1, F2, F3) so that when two words of equal
magnitude are applied at the A and B inputs, it will assume a
high level to indicate equality (A = B). The ALU must be in
the subtract mode with Cn = H when performing this cornparison. The A = B output is open-collector so that it can
be wire-AND connected to give a comparison for more than
four bits. The carry output (Cn + 4 ) can also be used to supply relative magnitude information. Again, the ALU must be
placed in the subtract mode by placing the· function-select
inputs 53, 52, 81, SO at L, H, H, L, respectively.

Input
Cn

Output
Cn+4

Active-low Data
(FIgure 1)

AcUve-Hlgh Data
(Figure 2)

H
H
L
L

H
L
H
L

A.,B
AB

A~B

A~B

A>B
Autput

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

tpLH

Propagation Delay Time
Low-to-High'Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

propagation Delay Time
High-to-Low Level Output

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

Input
Under
Te8t

Other Input
Same Bit

Other Data Inputs

Apply
4.5V

Apply
GND

Apply
4.5V

Apply
GND

Ai

SI

None

Remaining
AandS.Cn

None

P

Out-of-Phase

SI

~

None

Remaining
AandS. Cn

None

P

Out-of-Phase

Ai

None

SI

Remaining
AandS. Cn

None

P

In-Phase

Si

None

Ai

Remaining
AandS.Cn

None

P

In-Phase

Ai

SI

None

Remaining
AandS.Cn

None

Cn+4

In-Phase

3-202

Parameter Measurement Information (Continued)
Input Bits Equal/Not Equal Test Table (Continued)
Function Inputs: 50 = 53 = M = 4.!;iV, 51 = 52 = OV

Symbol

Input
Under
Test

Parameter

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-te-Low Level Output

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

Other Input
Same Bit

Other Data Inputs

Output
Under
Test

Output
Waveform

Apply
4.5V

Apply
GND

Apply
4.5V

Apply
GND

Si

Ai

None

Remaining
AandS, Cn

None

Cn+4

In-Phase

A;

None

Si

Remaining
AandS, Cn

None

Cn+4

Out-aI-Phase

Si

None

Ai

Remaining
AandS, Cn

None

Cn+4

Out-aI-Phase

Output
Under
Test

Output
Waveform

Input!Palrs High/Not High Test Table
Function Inputs: S2 = M = 4.5V, SO = S1 = S3 = OV

Symbol

Parameter

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-te-Low Level Output

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

tpLH

Propagation Delay Time
Low-te-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

tpLH

Propagation Delay Time
Low-to-High Level Output

tpHL

Propagation Delay Time
High-to-Low Level Output

Input
Under
Test

Other Input
Same Bit

Other Data Inputs

Apply
4.5V

Apply
GND

Apply
4.5V

Apply
GND

A;

Si

None

Remaining
A,C n

Remaining
S

p

In-Phase

Si

Ai

None

Remaining
s'Cn

Remaining
A

p

In-Phase

Ai

Si

None

Remaining
A,Cn

Remaining
S

Cn+4

Out-ol-Phase

Si

A;

None

Remaining
S,Cn

Remaining
A

Cn+4

Out-aI-Phase

3-203

Logic Diagram (Positive Logic)
74AS881B

...
so

"

3

.

so •

>-____.::.11 Cl+4

I. ,

"r.

)...j~---.:.'""

c,~---------------------------------~

3·204

TLlF/6336-4

_

National
Semiconductor
Corporation

DM74AS1000A Quadruple 2-lnput NAND Drivers
General Description

Features

These devices contain four independent 2-input drivers,
each of which performs the logic NAND function. The
'AS1000A is a driver version of the 'ASOO. Each driver has
increased output drive capability to allow the driving of high
capacitive loads.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Improved line receiving characteristics

Connection Diagram
Dual-In-Llne Package
vee

48

4A

4V

38

3A

3Y

8

2
1A

1B

1V

2A

2B

2Y

GND
TLiF16337-1

Order Number DM74AS1000AN
See NS Package Number N14A·

Function Table
y= AB
Inputs

Output

A

B

Y

L
L
H
H

L
H
L
H

H
H
H
L

H

~

High Logic Level

L

~

Low Logic Level

'Contact your local NSC representative about surface mount (M) package availability.

3-205

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" af6 those values
b6yond which th6 safety of the devic6 cannot b6 guarant66d The devic6 should not b6 op6rat6d at th6selimits. The
parametric values defin6d in th6 "EI6Ctrical Characteristics"
table af6 not guarant66d at the absolute maximum ratings.
The "R6COmmended Operating Conditions" table will define
th6 conditions for actual devic6 op6ration.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
O"Cto +70"C
Storage Temperature Range
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

5

5.5

V

Vcc

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-48

mA

10L

Low Level Output Current

48

mA

TA

Free Air Operating Temperature

70

·c

4.5

V

2

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vcc
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

= 4.5V, II =
Vcc = 4.5V
VIL = Max

VOL

Low Level Output
Voltage

Vcc = 4.5V, VIH
10L = Max

II

Input Current @
Max Input Voltage

Vcc

Vcc

10H

Min

= 5V, TA = 25·C.
Typ

-18 mA

= -3mA
10H = Max

llOH

I

= -2mA, Vee = 4.5Vto5.5V
= 2V

2.4

Units

1.2

V

3.2
V

2
Vcc -2
0.35

= 5.5V, VIH = 7V

= 5.5V. VIH = 2.7V
= 5.5V, VIL = 0.4V
Vcc = 5.5V, Vo = 2.25V
Outputs High, Vee = 5.5V, VI = OV
Outputs Low, Vcc = 5.5V, VI = 4.5V

Max

0.5

V

0.1

mA

IIH

High Level Input Current

Vcc

20

IJ.A

IlL

Low Level Input Current

Vcc

-0.5

mA

10

Output Drive Current

-135

-200

mA

ICCH

Supply Current

2.3

3.5

mA

ICCl

Supply Current

11.5

19

mA

-50

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

tpLH

Parameter

Conditions

Propagation Delay Time
Low to High Level Output

Vcc = 4.5V to 5.5V
RL = 5000
CL = 50pF

Propagation Delay Time
High to Low Level Output
Note 1: See Section 1 for test waveforms and output load.
tpHL

3-206

Min

Max

Units

1

4

ns

1

4

ns

,-------------------------------------------------------------------, C

_

!:

......

National

i.....

Semiconductor
Corporation

8

:=

DM74AS1004A Hex Inverting Drivers
General Description

Features

These devices contain six independent 2-input drivers, each
of which performs the logic invert/complement function.
The 'AS1004A is a driver version of the 'AS04. Each driver
has increased output drive capability to allow the driving of
high capacitive loads.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process

Connection Diagram
Dual-In-Llne Package
Vec

1~4

AI

1
A1

YI

13

12

2
Y1

3
A2

AS

YS

11

4
Y2

A4

10

S
A3

Y4
II

8

I

17

Y3

GND
TL/F/6338-1

Order Number DM74AS1004AN
See NS Package Number N14A·

Function Table
A=Y
Input

Output

A

Y

L
H

H
L

H = High Logic Level
L

= Low Logic Level

'Contact your local NBC representative about surface mount (M) package availability.

3-207

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V
O·Cto +70·C
-65·C to + 150"C

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

Min

Nom

Max

4.5

5

5.5

Units
V
V

2

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-48

mA

10L

Low Level Output Current

48

mA

TA

Free Air Operating Temperature

70

·c

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

VIK

Input Clamp Voltage

VOH

High Level Output
Voltage

Conditions

= 4.5V,11 = -18 mA
10H = -2 mA, Vee = 4.5Vto 5.5V
10H = -3 mA, Vee = 4.5V
10H = Max, Vee = 4.5V
Vee = 4.5V, 10L = Max

Low Level Output
Voltage

II

Input Current @
Max Input Voltage

Vee

IIH

High Level Input Current

= 5.5V, VIH = 2.7V
= 5.5V, VIL = O.4V
Vee = 5.5V, Vo = 2.25V
Outputs High
Vee = 5.5V

IlL
10

Output Drive Current

lee

Supply Current

Typ

Vee

VOL

Low Level Input Current

Min

= 5V, TA = 25·C.
Max

Units

-1.2

V

Vee - 2
2.4

3.2

V

2
0.35

= 5.5V, VIH = 7V

0.5

V

0.1

mA

Vee

20

".A

Vee

-0.5

mA

-50

Outputs Low

-135

-200

mA

3.2

5

mA

16

27

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 500.0
CL = 50pF

Nole 1: See Section 1 for test waveforms and oulpulload.

3·208

Min

Max

Units

1

4

ns

1

4

ns

_

National

Semiconductor
Corporatton

DM74AS1008A Quadruple 2-lnput AND Driver
General Description

Features

This device contains four independent 2-input drivers, each
of which performs the logic AND function. The 'AS1008A is
a driver version of the 'AS08. Each driver has increased
output drive to allow the driving of high capacitive loads.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Improved line receiving characteristics

Connection Diagram
Dual-In-Llne Package

AI

14

A4

BI

YI

Y4

13

A3

Y3

•

TL/F/6339-1

Order Number DM74AS1008AN
See NS Package Number N14A'

Function Table
Y = AB
Inputl

Output

A

B

Y

L
L

L

H

H
H

L

L
L
L

H

H

= Low LogIc Level
H = High Logic Level
L

'Contact you, local NSC representative about surface mount (M) package availability.

3-209

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range

Note: The "Absolute Maximum Ratings" arB those values
beyond which the safety of the device cannot be guarant86d. The device should not be operated at these limits. The
paralTl6tric values defined in the "Electrical Characteristics"
table arB not guaranteed at the absolute maximum ratings.
The "RecomlTl6nded Operating Conditions" table will define
the conditions for actual device operation.

7V
O·Cto +70"C
- 65·C to + 15O"C

Recommended Operating Conditions
Symbol

.,

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Vcc

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-48

mA

48

mA

70

·c

10L

Low Level Output Current

TA

Free Air Operating Temperature

2

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V
VIH = 2V

IOH=-3mA
10H = Max

10H = -2mA, Vee = 4.5Vto5.5V

Min

2.4

Typ

Max

Units

-1.2

V
V

3.2

2

V

Vee- 2

V

VOL

Low Level Output
Voltage

Vee = 4.5V, VIL = 0.8V
10L = Max

II

Input Current at Max
Input Voltage

VCC = 5.5V, VIH = 7V

IIH

High Level Input Current

VCC = 5.5V, VIH = 2.7V

20

fJ-A

IlL

Low Level Input Current

Vcc = 5.5V, VIL = 0.4V

-0.5

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

-135

-200

mA

ICCH

Supply Current with
Outputs High

Vee = 5.5V, VI = 4.5V

5.6

9.5

mA

ICCL

Supply Current with
OutputsL.ow

VCC = 5.5V, VI = OV

13.5

22

rnA

0.35

-50

0.5

V

0.1

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

VCC = 4.5V to 5.5V
RL = 5000
CL = 50pF

Note 1: See Section 1 for test waveforms and output load.

3·210

Min

Max

Units

1

6

ns

1

6

ns

_

National

Semiconductor
Corporation

DM74AS1032A Quadruple 2-lnput OR Driver
General Description

Features

This device contains four independent 2-input drivers, each
of which performs the logic OR function. The 'AS1032A is a
driver version of the' AS32A. Each driver has increased output drive capability to allow the driving of high capacitive
loads.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced OXide-isolated, ion-implanted Schottky TTL
process
• Improved line receiving characteristics

Connection Diagram
Dual-in-Line Package

vee

B4

A4

A1

B1

Y1

Y4

B3

A3

Y3

B2

Y2

GND

7
A2

TLiF/6340-1

Order Number DM74AS1032AN
See NS Package Number N14A·

Function Table
Y=A+B
Inputs
A

B

Output
Y

L

L

L

H

X

X

H

H
H

L = Low Logie Level
H

= High Logic Level

X = EHher Low or High Logic Level

'Contact your local NSC representative about surface mount (M) peckege availability.

3·211

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
Storage Temperature Range

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

O"Cto +70"C
-65·Cto + 150"C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Low Level Input Voltage

0.8

V

Vcc

Supply Voltage

VIH

High Level Input Voltage

Vil

2

V

10H

High Level Output Current

-48

mA

10l

Low Level Output Current

48

mA

TA

Free Air Operating Temperature

70

·C

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, TA = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V, II = -18 mA

VOH

High Level Output
Voltage

Vee = 4.5V
VIH = 2V

IOH=-3mA

IOH=-2mA

Vee = 4.5V to 5.5V

Min
2.4

Low Level Output
Voltage

Vee = 4.5V, VIH = 0.8V
10l = Max

II

Input Current @ Max
Input Voltage

Vee = 5.5V, VIH = 7V

Max

Units

1.2

V

3.2

V

2

V

Vee - 2

V

10H = Max

VOL

Typ

0.35

0.5

V

0.1

mA

IIH

High Level Input Current

Vce = 5.5V, VIH = 2.7V

20

/loA

III

Low Level Input Current

Vcc = 5.5V, Vil = 0.4V

-0.5

mA

10

Output Drive Current

VCC = 5.5V, Vo = 2.25V

-135

-200

rnA

ICCH

Supply Current

Outputs High, Vee = 5.5V, VI = 4.5V

7.7

11.5

mA

ICCl

Supply Current

Outputs Low, Vee = 5.5V, VI = OV

14.7

24

mA

-50

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHl

Propagation Delay Time
High to Low Level Output

Vec = 4.5V to 5.5V
Rl = 5000
Cl = 50pF

Nota 1: See Section 1 for test waveforms and output load.

3-212

Min

Max

Units

1

6.3

ns

1

6.3

ns

.-------------------------------------------------------------------,0
_

a:::::

National

~.....

Semiconductor
Corporation

Q

W

:t

DM74AS 1034A Hex Non-Inverting Drivers
General Description

Features

These devices contain six independent drivers, each of
which performs the logic indentity function. The 'AS1034A is
a driver version of the 'AS34. Each driver has increased
output drive capability to allow the driving of high capacitive
loads.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process

Connection Diagram

:i

14

Dual·ln·Llne Package
C

Y6

Afi
13f

A5

Y5

11

12

4>-

10

Y4

8

4>-

-t>-

rt>-

~

9

-t>rl>-

3

5
A3

~

TL/F/6341-1

Order Number DM74AS1034AN
See NS Package Number N14A*

Function Table
A=Y
Input

Output

A

Y

L

L

H

H

L = Low Logie Level
H

=

High Logic Level

II
'Contact your local NSC represen1ative about surface mount (M) package availability.

3·213

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V

Input Voltage

7V

Operating Free Air Temperature Range

O·Cto +700C

Storage Temperature Range

- 65·C to + 1500C

Recommended Operating Conditions
Symbol

Parameter

Min

Nom

Max

Units

4.5

5

5.5

V

Low Level Input Voltage

0.8

V

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

2

V

10H

High Level Output Current

-48

mA

10L

Low Level Output Current

48

mA

TA

Free Air Operating Temperature

70

·c

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V, T A = 25·C.
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VOH

High Level Output
Voltage

10H = -2 mA, Vee = 4.5Vto 5.5V

Min

2.4

Vee = 4.5V
10L = Max

II

Input Current @
Max Input Voltage

Vee = 5.5V, VIH = 7V

Units
V
V

3.2

V

2

10H = Max, Vee = 4.5V
Low Level Output
Voltage

Max
-1.2

Vee -2

10H = -3 mA, Vee = 4.5V

VOL

Typ

0.35

0.5

V

0.1

mA

IIH

High Level Input Current

Vee = 5.5V, VIH = 2.7V

20

/LA

IlL

Low Level Input Current

Vee = 5.5V, VIL = O.4V

-0.5

mA

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

lee

Supply Current

Vee = 5.5V

-50

I Outputs High
I Outputs Low

-135

-200

mA

9

15

mA

21

35

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

Note ,: See Section 1 for test waveforms and output load.

3-214

Min

Max

Units

1

6

ns

1

6

ns

r-------------------------------------------------------------------.c
_

i:

National
Semiconductor
CorporaHon

~

~....

o

;

DM74AS1036A Quad 2-lnput NOR Drivers
General Description

Features

These devices contain four independent drivers, each of
which performs the logic NOR function. Each driver has increased output drive capability, allowing the driving of high
capacitive loads.

• Switching specifications at 50 pF
• Switching specification guaranteed over full temperature
and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process

Connection Diagram
Dual-In-Line Package

vee

84

A4

Y4

83

A3

Y3

11

3
A1

81

Y1

TL/F/6342-1

Order Number DM74AS1036AN

See NS Package Number N14A·

Function Table
Y=A+B
Inputs

Output

A

B

Y

L

X

L
H

H

X

H
L
L

= High Level
L = Low Level
X = Don't Care
H

'Contact your local NSC representative about surface mount (M) package availability.

3-215

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage

7V

Input Voltage

7V

Operating Free Air Temperature

O"Cto +70'C

Storage Temperature Range

- 65'C to + 150'C

Recommended Operating Conditions
Symbol

Min

Nom

Max

Units

4.5

5

5.5

V

VIL

Low Level Input Voltage

0.8

V

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

V

2

10H

High Level Output Current

-48

mA

10L

Low Level Output Current

48

mA

TA

Operating Free Air Temperature Range

70

'C

0

Electrical Characteristics over recommended operating free air temperature range
Symbol

Parameter

Conditions

Typ
(Note 2)

Min

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VOH

High Level Output Voltage

10H = -2 mA, Vee = 4.5Vto 5.5V

Max

Units

-1.2

V

Vee- 2

10H = -3 mA, Vee = 4.5V

2.4

V

3.2

2

10H = Max, Vee = 4.5V
VOL

Low Level Output Voltage

Vee = 4.5V, 10L = Max, VIH = 2V

0.35

0.5

V

II

Input Current at Maximum Input Voltage

Vee = 5.5V, VI = 7V

100

p.A

IIH

High Level Input Current

Vee = 5.5V, VI = 2.7V

20

p.A

IlL

Low Level Input Current

Vee = 5.5V, VI = 0.4V

-500

p.A

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

-135

-200

mA

leeH

Supply Current with Outputs High

Vee = 5.5V

4.7

7

mA

leeL

Supply Current with Outputs Low

Vee = 5.5V

15.3

23

mA

-50

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Conditions
(Note 1)

Parameter

tpLH

Propagation Delay Time, Low to High Level Output

tpHL

Propagation Delay Time, High to Low Level Output

Note 1: See
Note 2:

Section 1 for test waveforms and output load.
Typical values are measured at Vee ~ SV and TA

~

2S'C.

3·216

Vee = 4.5V to 5.5V
RL = 500n
CL = 50pF

Min

Max

Units

1

4.3

ns

1

4.3

ns

.-------------------------------------------------------------'0
_

.

s:

National

i.....

Semiconductor
Corporation

co
Q

.".

DM74AS1804 Hex 2-lnput NAND Drivers
General Description

Features

These devices contain six independent 2-lnput drivers each
of which performs the logic NAND function. The' AS1804 is
equivalent to the 'AS804B but the supply voltage and
ground pins are centered in the package. This positioning of
the supply voltage and ground pins reduce the lead inductance of these pins. This reduction of lead inductance will
minimize noise generated onto either the supply voltage or
ground bus which is significant in high current switching applications.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Centered Vee and GND configuration provides minimum lead inductance for high current switching applications
• High capacitive drive capability

Connection Diagram
SA

5Y

48

4A

4Y

GND

3Y

38

3A

2Y

58

6Y

6A

68

Vee

lA

18

lY

2A

28
TL/F/B619-1

Order Number DM74AS1804N
See NS Package Number N20A

Function Table
y = A.a
INPUTS

OUTPUT

A

a

y

L
L

L
H

H
H

L

H
H
H

H

L

3-217

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device can not be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature
O"Cto +70"C
Storage Temperature Range

-65·C to + 150"C

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

Min

Nom

Max

Units

4.5

5

5.5

V

2

V

Vil

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-48

mA

48

mA

70

·C

10l

Low Level Output Current

TA

Operating Free Air Temperature Range

0

Electrical Characteristics over recommended operating free air temperature range
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee = 4.5V,11 = -18 mA

VOH

High Level Output Voltage

10H = -2 mA, Vee = 4.5V to 5.5V

Typ

Min

Max

Units

-1.2

V

Vee- 2

10H = -3 mA, Vee = 4.5V
10H = Max, Vee = 4.5V

2.4

3.2

V

2

VOL

Low Level Output Voltage

Vcc = 4.5V, 10l = Max, VIH = 2V

0.5

V

II

Input Current at Maximum Input Voltage

Vcc = 5.5V, VI = 7V

100

IJA

IIH

High Level Input Current

Vcc = 5.5V, VI = 2.7V

20

IJ.A

IlL

Low Level Input Current

Vcc = 5.5V, VI = OAV

-500

IJ.A

10

Output Drive Current

Vee = 5.5V, Vo = 2.25V

-135

-200

mA

leeH.

Supply Current with Outputs High

Vee = 5.5V

3.5

5

mA

ICCl

Supply Current with Outputs Low

Vee = 5.5V

16

27

mA

-50

Switching Characteristics over recommended operating free air temperature range (Note 1)
Parameter

'·Condltlons (Note 1)

Min

Max

Units

tplH

Propagation Delay Time Low to High Level Output

4

ns

Propagation Delay Time High to Low Level Outp",t

Vcc = 4.5V to 5.5V
Rl = 500n
Cl = 50pF

1

tpHl

1

4

ns

Symbol

Note 1: See

Section 1 for test waveforms and output load.

3·218

,-------------------------------------------------------------------, c
a::
......
National
_

~...

Semiconductor
Corporation

m

DM74AS1805 Hex 2-lnput NOR Drivers
General Description

Features

These devices contain six independent 2-lnput drivers each
of which performs the logic NOR function. The 'AS1805 is
equivalent to the 'AS805B but the supply voltage and
ground pins are centered in the package. This positioning of
the supply voltage and ground pins reduce the lead inductance of these pins. This reduction of lead inductance will
minimize noise generated onto either the supply voltage or
ground bus which is significant in high current switching applications.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-Isolated, lon-Implanted Schottky TTL
process
• Centered Vee and GND configuration provides minimum lead inductance for high current switching applications
• High capacitive drive capability

Connection Diagram

58

6Y

SA

68

Vee

1A

18

1Y

2A
TLlF/8618-1

Order Number DM74AS1805N
See NS Package Number N20A

Function Table
Y=A+B
INPUTS

OUTPUT

A

B

Y

L
L
H
H

L
H
L
H

H
L
L
L

3-219

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" BI'8 tfIOse values

If Military/Aerospace specified devices are required,
contact the National Semiconductor Seles OffIce/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature
O"Cto 70"C
Storage Temperature Range
-65·Cto + 150"C

beyond which the ssfety of the device csnnot be g/J81'Bnteed. The device should not be operated at these limits. The

parametric values defined in the "Electrical Characteristics"
table ara not guaranteed at the abSolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

. Min

Paremeter

Nom

Max

Units

5

5.5

V

Vcc

Supply Voltage

4.5

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-48

mA

10L

Low Level Output Current

48

mA

TA

Operating Free Air Temperature Range

70

·c

V

2

0

Electrical Characteristics over recommended operating free air temperature range
Symbol

Conditions

Paremeter

VIK

Input Clamp Voltage

VOH

High Level Output Voltage

= 4.5V.11 = -18 mA
10H = - 2 mAo Vcc = 4.5V to 5.5V
10H = -3 mAo Vcc = 4.5V
10H = Max. Vcc = 4.5V
Vcc = 4.5V. 10L = Max. VIH = 2V
Vcc = 5.5V. VI = 7V
Vee = 5.5V. VI = 2.7V
Vcc = 5.5V. VI = 0.4V
Vcc = 5.5V. Vo = 2.25V
Vcc = 5.5V
Vcc = 5.5V

Typ

Min

Vcc

VOL

Low Level Output Voltage

II

Input Currant at Maximum Input Voltage

IIH

High Level Input Current

IlL

Low Level Input Current

10

Output Drive Current

ICCH

Supply Current with Outputs High

ICCL

Supply Current with Outputs Low

Max

Units

-1.2

V

VCC-2
3.2

2.4

V

2

-50

0.5

V

100

fJoA

20

fJoA

-500

,...A

-135

-200

mA

6.5

10

mA

20

32

mA
\.-

Switching Characteristics over recommended operating free air temperature range (Note 1)
Parameter

Conditions (Note 1)

Min

Max

Units

TpLH

Propagation Delay Time Low to High Level Output

4.3

ns

Propagation Delay Time High to Low Level Output

Vcc = 4.5V to 5.5V
RL = 5000
CL = 50pF

1

TpHL

1

4.3

ns

Symbol

Note 1: See Section 1 for test waveforms and ou1pUt load.

3-220.

.-------------------------------------------------------------------,c
i:
.....
National
_

~....

Semiconductor
Corporation

E

DM74AS1808 Hex 2-lnput AND Drivers
General Description

Features

These devices contain six independent 2-lnput drivers each
of which performs the logiC AND function. The 'ASIBOB is
equivalent to the' ASBOB but the supply voltage and ground
pins are centered in the package. This positioning of the
supply voltage and ground pins reduce the lead inductance
of these pins. This reduction of lead inductance will minimize noise generated onto either the supply voltage or
ground bus which is significant in high current switching applications.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Centered Vee and GND configuration provides minimum lead inductance for high current switching
applications
• High capacitive drive capability

Connection Diagram
5Y

6Y

49

4A

6A

69

Vee

lA

3Y

39

3A

2Y

19

lY

2A

29
TL/F/8620-1

Order Number DM74AS1808N
See NS Package Number N20A

Function Table
Y = A.B
OUTPUT

INPUTS

A

B

Y

L
L

L
H

H
H

L

L
L
L

H

H

3-221

Absolute Maximum Ratings
Note: The "Absolute Maximum Rstings" Bf9 those values
beyond which the ssfBty of the devic6 csn not be gusranteed. The devic6 should not be operated st th6SB limits. The
pBfBfTlBtric values defined in the "EIectricBI Chsracteristics"
tIIbIB SrB not guaranteed st the sbsolute maximum ratings.
The ''Rf1COITIfT16f1dB Operating CondItIons" tBblB will define
the conditions for sctusl devic6 operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sal.. OffIce/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature
Storage Temperature Range

7V
O"Cto +70"C
- 65·C to + 150"C

Recommended Operating Conditions
Symbol

Paramater

Min

Nom

Max

Unit

5

5.5

V

V

Vee

Supply Voltage

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.8

10H

High Level Output Current

-48

mA

10l

Low Level Output Current

48

mA

TA

Operating Free Air Temperature Range

70

·c

4.5

V

2

0

Electrical Characteristics over recommended operating free air temperature range
Symbol

Conditions

Parameter

= 4.5V,11 = -18mA
= -2 mA, Vee = 4.5 to 5.5V
10H = -3 mA, Vee = 4.5V
10H = Max, Vee = 4.5V
Vee = 4.5V, 10l = Max, VIH = 2V
Vee = 5.5V, VI = 7V
Vee = 5.5V, VI = 2.7V
Vee = 5.5V, VI = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V
Vee = 5.5V

VIK

Input Clamp Voltage

Vee

VOH

High Level Output Voltage

10H

.
VOL

Low Level Output Voltage

II

Input Current at Maximum Input Voltage

IIH

High Levell nput Current

III

Low Level Input Current

10

Output Drive Current

ICCH

Supply Current with Outputs High

ICCl

Supply Current with Outputs Low

Min

Typ

Max

Unit

-1.2

V

Vee- 2
2.4

3.2

V

2

-50

0.5

V

100

/LA

20

/LA

-500

p.A

-200

rnA

8

13

mA

20

33

mA

-135

Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol

Parameter

Conditions (Note 1)

Min

Max

Unit

tplH

Propagation Delay Time Low to High Level Output

6

ns

Propagation Delay Time High to Low Level Output

Vee = 4.5V to 5.5V
Rl = 500n
CL = 50pF

1

tpHl

1

6

ns

.

Note 1: See Section 1 for test waveforms and output load.

3·222

r-------------------------------------------------------------~----,o

_

iii:

.....

National
Semiconductor
Corporation

i....

C»
Co)

N

DM74AS1832 Hex 2-lnput OR Drivers
General Description

Features

These devices contain six independent 2-lnput drivers each
of which performs the logic OR function. The 'AS1832 is
equivalent to the 'AS8328 but the supply voltage and
ground pins are centered in the package. This positioning of
the supply voltage and ground pins reduce the lead inductance of these pins. This reduction of lead inductance will
minimize noise generated onto either the supply voltage or
ground bus which is significant in high current switching applications.

• Switching specifications at 50 pF
• Switching specifications guaranteed over full temperature and Vee range
• Advanced oxide-isolated, ion-implanted Schottky TTL
process
• Centered Vee and GND configuration provides minimum lead inductance for high current switching
applications
• High capacitive drive capability

Connection Diagram
5A

5Y

58

6Y

48

4A

6A

68

Vee

lA

18

38

3A

2Y

lY

2A

28
TL/F/8621-1

Order Number DM74AS1832N
See NS Package Number N20A

Function Table
Y = A+B
INPUTS

OUTPUT

A

B

Y

L
L

L

L

H

H
H

H

H
H
H

L

3-223

Absolute Maximum Ratings
Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
Operating Free Air Temperature

7V
O"C to + 70"C
-65·C to + 150"C

Storage Temperature Range

Recommended Operating Conditions
Symbol

\

Parameter

Vcc

Supply Voltage

Min

"om

4.5

5

Max

Unit

5.5

V
V

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

0.8

V

10H

High Level Output Current

-48

mA

10L

Low Level Output Current

48

mA

TA

Operating Free Air Temperature Range

70

·c

2

0

Electrical Characteristics over recommended operating free air temperature range
Symbol

Parameter

Conditions

VIK

Input Clamp Voltage

Vee

VOH

High Level Output Voltage

10H
10H

..
VOL

= 4.5V, II = -18mA
= -2mA, Vee = 4.5Vt05.5V
= -3 mA, Vcc = 4.5V

= Max, Vec = 4.5V
Vcc = 4.5V, 10l = Max, VIH =
Vcc = 5.5V, VI = 7V
Vcc = 5.5V, VI = 2.7V
Vee = 5.5V, VI = 0.4V
Vee = 5.5V, Vo = 2.25V
Vee = 5.5V
Vee = 5.5V

II

Input Current at Maximum Input Voltage

IIH

High Level Input Current

III

Low Level Input Current

10

Output Drive Current

ICCH

Supply Current with Outputs High

ICCl

Supply Current with Outputs Low

Max

Unit

-1.2

V

Vce- 2
2.4

3.2

V

2

10H

Low Level Output Voltage

Typ

Min

2V

-50

-135

0.5

V

100

p.A

20

p.A

-500

p.A

-200

mA

11

17

mA

22

36

mA

Switching Characteristics over recommended operating free air temperature range (Note 1)
Parameter

Conditions (Note 1)

Min

Max

Unit

tplH

Symbol

Propagation Delay Time Low to High Level Output

1

6.3

ns

tpHl

Propagation Delay Time High to Low Level Output

Vee = 4.5V to 5.5V
Rl = 500n
Cl = 50pF

1

6.3

ns

Note 1: See Section 1 for test waveforms and output load.

,

3·224

_

National
Semiconductor
Corporation

PRELIMINARY

DM74AS2620 Octal Bus Transceivers/MOS Drivers
General Description
These octal bus transceivers are designed to drive the capacitive input characteristics of MaS devices and allow
asynchronous two-way communication between data buses. The control function implementation allows for maximum
flexibility in timing.
These devices allow data transmission from the A bus to
the B bus or from the B bus to the A bus, depending upon
the logic levels at the enable inputs (GBA and GAB).
The enable inputs can be used to disable the device so that
the buses are effectively isolated.
The dual enable configuration gives the' AS2620 the capability to store data by simultaneous enabling of the GBA and
GAB. Each output reinforces its input in this transceiver con-

figuration. Thus, when both control inputs are enabled and
all other data sources to the two sets of bus lines are at high
impedance, both sets of bus lines (16 in all) will remain at
their last states. The 8-bit codes appearing on the two sets
of buses will be complementary.

Feature$
• Bidirectional octal bus transceivers for driving MaS devices
• 1/0 ports have 250. series resistors so no external resistors are required
• Local bus-latch capability

Logic Diagram

Connection Diagram
Dual-In-Line Package

GBA---_OI
GAB

20

Vee

A1

19

iiBA

A2

18

B1

A3

17

B2

A4

16

B3

A5

15

14

AS

14

B5

A7

13

B6

AI

12

17

11

BB

GAB

...-B1

A 1 - -.............. ~~-+

TO OTHER SEVEN
TRANSCEIVERS
TL/F/6729-2

GND

10

Function Table
Enable Inputs
GBA

TL/F/6729-1

Operation

GAB

L

L

B Data to A Bus

H

H

Ii. Data to B Bus

Top View

H

L

Isolation

Order Number DM74AS2620N
see NS Package Number N20A'

L

H

B Data to A Bus,
Ii. Data to B Bus

II
'Contact your local NSC representative about surface mount (M) package availability.
This document contains Information on a product under development. NSC reserves the right to change or discontinue this product without notice.

3-225
---_._-------

Absolute Maximum Ratings
If Mllitary/A!lrospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
I/O Ports
5.5V
Other Ports
7V
Operating Free Air Temperature Range
O"Cto +70"C
Storage Temperature Range
- 65·C to + 150"C

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guarant88d. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics'~
table are not guaranteed at the absolute maximum ratings:
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

TA

Free Air Operating Temperature

Min

Nom

Max

Units

4.5

5

5.5

V

0.8

V

70

·c

2

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee = 5V. TA = 25·C.
Symbol

Parameter

Conditions

Min

Typ
(Note 1)

Max

Units

-1.2

V

VIK

Input Clamp Voltage

Vee = 4.5V.11 = -18 mA

VOH

High Level Output Voltage

Vee = 4.5Vto 5.5V.IOH = -2 mA

VOL

Low Level Output Voltage

Vee = 4.5V. 10L = 1 mA

0.15

0.4

Vee = 4.5V. 10L = 12 mA

0.35

0.7

V

Control Inputs

0.1

mA
mA

V

Vee -2

V

II

Input Current @
Max Input Voltage

Vee = 5.5V. VI = 7V
Vee = 5.5V. VI = 5.5V

AorB Ports

0.1

IIH

High Level Input Current
(Note 3)

Vee = 5.5V. VI = 2.7V

Control Inputs

20

IJA

A or B Ports

70

",A

IlL

Low Level Input Current
(Note 3)

Vee = 5.5V. VIL = 0.4V

-0.5

mA

-0.75

mA

10

Output Current (Note 2)

Vee = 5.5V. Vo = 2.25V

-50

-150

mA

10H

High Level Output Current

Vee = 4.5V. Vo = 2V

-35

mA

10L

Low Level Output Current

Vee = 4.5V. Vo = 2V

35

mA

lee

Supply Current

Vee = 5.5V

Control Inputs
A or B Ports

Outputs High

62

100

rnA

Outputs Low

74

121

mA

Outputs Disabled
48
77
Note 1: All typical values are at Vrx; = 5V. TA = 25"C.
Note 2: The output conditions have been chosen to produce a currant that closely approximates one haH of the true short circu~ output curren~ los.
Note 3: For 110 ports, the parameters IIH and IlL inciude the off·state output current.

mA

3-226

Switching Characteristics over recommended operating free air temperature range (Note 1)
From
(Input)

To
(Output)

A

B

A

B

B

A

B

A

Output Enable TIme
to High Level Output

GBA

A

tpZL

Output Enable Time
to Low Level Output

~BA

A

tpHZ

Output Disable Time
from High Level Output

~BA

A

tpLZ

Output Disable Time
from Low Level Output

GBA

A

tPZH

Output Enable Time
to High Level Output

GAB

B

tpZL

Output Enable Time
to Low Level Output

GAB

B

tpHZ

Output Disable Time
from High Level Output

GAB

B

tpLZ

Output Disable Time
from Low Level Output

GAB

B

Symbol

Parameter

Conditions

tpLH

Propagation Delay Time
Low to High Level Output

tpHL

Propagation Delay Time
High to Low Level Output

tpLH

Propagation Delay Time
Low to High Level Output

Vee = 4.5V to 5.5V
CL = 50pF
R1 = 500n
R2 = 500n
TA = Minto Max

tpHL

Propagation Delay TIme
High to Low Level Output

tPZH

Note 1: See Section 1 for test waveionns and output load.

3-227
-~------'---

.. _ - - -

-

-

Min

Max

Units

1

8

ns

1

6.5

ns

1

8

ns

1

6.5

ns

1

10

ns

1

11

ns

1

6

ns

1

12

ns

1

8

ns

1

8

ns

1

11

ns

1

11

ns

National

~ Semiconductor
CorporaHon

DM74AS2645 TRI-STATE®
Bus Transceivers/MOS Drivers
General Description

Features

This device contains 8 pairs of logic elements configured as
octal bus transceivers. They are deSigned to drive the capacitive input characteristics of MOS devices and allow
asynchronous bidirectional communications between data
buses. Data transmission from the A bus to the B bus or
from the B bus to the A bus are selectively controlled by
, (OIR and G) the direction and enable inputs. This enable
input is also used to disable the device so that the buses are
effectively isolated.

• Bidirectional octal bus transceivers for driving MOS devices
• 1/0 ports have 250 series reSistors so no external resistors are required
• Advanced oxide isolated, ion-implanted Schottky TTL
process
• Switching response specified into 5000/50 pF load
• Switching specifications guaranteed over full temperature and Vee range

Connection Diagram
Dual-In-Llne Package

G

Vee

lB

28

3B

4B

5B

6B

7B

BB

120 h9 h. 117 116 115 J14 J13 J12 111
~ ~ ~ ~ ~ ~ ~ ~ ~
I'

r r r r r r r r

DIRl

1~2 ~3

J4

4~5 ~6

!7

7~8

J:

G~~O
TUF/6343-1

Order Number DM74AS2645N
See NSPackage Number N20A·

Function Table
Control
Inputs

Operation
DIR

L

L

B Data to A Bus

L

H

A Data to B Bus

H

x

Hi-Z

L

~

H

= High Logic Level

Low Logic Level

Hi-Z

~

X

EHher Low or High logic Level

~

High Impedance State

'Contact your local NSC representative about surface mount (M) package availability.

3-228

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and speclflcatlons_

Note: The "Absolute Maximum Ratings" are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the "Electrical Characteristics"
table are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define
the conditions for actual device operation.

7V

Supply Voltage, Vee
Input Voltage
Control Inputs
I/O Ports

7V
5.5V

Operating Free Air Temperature Range
Storage Temperature Range

O"Ct070"C
-65'C to

+ 150"C

Recommended Operating Conditions
Symbol

Parameter

Vee

Supply Voltage

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

TA

Operating Free Air Temperature

Min

Typ

Max

Units

4.5

5

5.5

V

0.8

V

70

'C

2

V

0

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at Vee
Symbol

Parameter

Conditions

Vee

=
=

4.5Vt05.5V,IOH

Vee

=

4.5V

Input Current at
Max Input Voltage

Vee
(VIN

=
=

5.5V, VIN = 7V
5.5V for A or B Ports)

High Level
Input Current

Vee = 5.5V,
VIN = 2.7V

Low Level
Input Current

Vee = 5.5V,
VIN = 0.4V

10

Output Drive Current

Vee

lee

Supply Current

Vee

VIK

Input Clamp Voltage

Vee

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

II
IIH

IlL

=
=

4.5V, II

=

=

5V, TA

=

25'C.

Typ

Min

-18 mA

=

-2mA

=
10L =
10L

5.5V, VOUT

=

Units

-1.2

V
V

Vcc- 2

-1 mA

0.25

0.4

V

12mA

0.35

0.7

V

0.1

mA

Control Inputs

20

AorB Ports

70

Control Inputs

-0.5

AorB Ports

-0.75
-50

p.A

mA

-150

mA

Outputs High

58

95

mA

Outputs Low

95

155

mA

TRI-STATE

73

119

mA

2.25V

5.5V

Max

Switching Characteristics over recommended operating free air temperature range (Notes 1 and 2)
Symbol

Parameter

From
(Input)

To
(Output)

Min

Max

Units

tpLH

Propagation Delay Time
Low to High Level Output

AorB

BorA

1

10

ns

tpHL

Propagation Delay Time
High to Low Level Output

AorB

BorA

1

9.5

ns

tPZL

Output Enable Time to Low Level

~

AorB

1

11.5

ns

tPZH

Output Enable Time to High Level

~

AorB

1

10.5

ns

tpLZ

Output Disable Time from Low Level

G

AorB

1

8

ns

G

AorB

1

12

ns

Output Disable Time from High Level
tpHZ
Note 1: See Section 1 for lest waveforms and outpulload.
Note 2: Switching characteristic conditions are Vee = 4.5V to 5.5V. RL =

5000, CL

3-229

=

50 pF.

Section 4
Physical Dimensionsl
Appendices

Section 4 Contents
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Bookshelf
Sales and Distribution Offices

4-2

4-3

_

Nanonal
Semiconductor
Corporation

All dimensions are in inches (millimeters)
0.185
1-----119.939)-------1

MAX

0.025
(0.635)

t

0.220-0.310
(5.588-1.814)

RAD

~"T:T'T':T"r.'1""'1":'T"'1":'T"'T";'r"""""~
0.290-0.320

I (1.366-8.128)
!:!!!.MJ~ ii-I

0.060 ±O.OOS

(4.512)

L

0.018±o.o03
(OA51±0.016)

-H-

0.100 ±Q.OIO
(2.540 ±0.254)

0.125-0.200
(3.115-5.080)
0.150
(3.81)
MIN

J14A (REV 0)

NS Package J14A

0.025
(0.635)
RAO

0.005 - 0.020
(0.127 - 0.508)
RAOTYP

-.--=!-

0.290-0.320

I

~f!!\J(7'3~_8'128)
0.180

(~~x~21

95"±5"

0.310 - 0.410
(7.874-10.41)

0.005

0.200
(5.080)
MAX

__

---l

~ ~~~~~~~~~t;~.:=~~ +_~~
0.008-0.012

~(0'203-0'~~~

J

(2.~:
BDTH
ENDS
J16A(REVK)

NS Package J16A

4-3

II

wr-----------------------------------------------------~------~

C

o
"iii
cCI)
E

0.985
1 " + - - - - - (25.019)
MAX

------+-

is

1j
"~

.c

a.

'.180
(4.572)
MAX

GLASS SEAlANT

0.200
(5.DlO)

MAX

,

0.125 - 0.200
(3.175 - 5.080)

O.ODl - 0.012
(0.203-0.305)
0.018±o.D03 _II~
(0.457 ± 0.076)

I I

0.100±0.010
(2.540±0.254)
J20A (REV Mj

NS Package J20A

1.290

I

0.600

(32.766)-------------~~~

MAX

0.025
(0.635)
, RAD

(15.2~)

fMAX

iGLASS
0.514-0.526

0.030-0.055
(0.762-1.397)
RADTYP
0.590-0.620 ~

~ (14.986-16.748)

~
_
1

II

~

95 '5
+0.025
0.685 -0.060 _
+0.635)
(
17.~ -1.524

,I
---,

0.005
(0.127)

MIN
0.008-0.012
(0.203 0.305)
0.098

J

(2.489)
MAX

NS Package J24A

4-4

0.125-0.200
(3.175-5.080)

0.150
(3.810)

MIN

MIN

rI~ B,,~ .",,0.336-0.344

_ j _14

13

12

11

10

9

8

0.228 -0.244

'T~I~

=T2nrr::rr::::r;;::;;;::nJ

:;:1

0.020
(0.508)

_

0.150-0.158
(3.810-4.013)

r

_

0.017
(0.432)

-

1r__X_ 45_·","""

TYP

0.024-0.031 0.053-0.069
(0.610-0.787) (1.346-1.753)
• •

~~~~DS

LJr;:tJ~~ll +
f.::!l..! r
[-======
t

J

0.007 -0.010
40.178-0.254)

tl806Ebi:ib]

!~J

I

0.020-0.050
(0.508 -1.270)

0.004
(0.102)

TYP

1_

AFTER,. FINISH

J[2...

I

(1.270)

0.004-0.010
(0.102 -0.254)

-

(0.356-0.483)

TYP

TYP

TYP AlL LEADS

ALL LEAD TIPS

M14A,AEV F)

NS Package M14A

.
.
r4
16

0.385-0.394
(9.779-10.008)
15

14

13

12

11

10

i

r·

0.228 -0.244
(5.791

198
)

~E;::;:::;:;::;::;:::;::;:::;:;::;::;:::;:~

LEAD NO.1
10ENT

0.150-0.158 (3.810-4.013)

=1 1_
I

~cb
0.007 tOl0

~~~~u:~=J

0.017
(0.432)
x45.

r
+
I
0.004
(0.102)

j

0·-8·
TYP
ALL LEADS

tQ".

+

L-=:!.'050

+t

0.024-0.031
(0.610-0.787)

-

0.053 -0.069
(1.346-1.753)

+

t

(0.508-1.270)
TYP ALL LEADS

0.004-0.010
(0.102-0.254)

~ AFTER LEf FINISH

_I

I_~
(1.270)
TYP

_11_

001L.019
(0.356-0.483)
TYP
Ml&AIFlE.1=

ALL LEAD TIPS

NS Package M16A

4-5

(I)

c

o

..

'iii

i

0.488 -0.112
{12.518-13·1I061

E

is

~

.i-

Do

-£
iD.4iii
r

{~::=~::I

.!:!!!!=.!:!.!!

0.017

.45'

{2.312 -2.1421

-----&i

•

.-"

I--±

t -·~~==7=....!.f~f
0.004/

.!!:!!!!.::!!:!
{0.229-0·3301
TVP ALL LEADS

{0.1021
ALLLEAO TIPS

t

0·... •
1YP ALL LEADS

t

0.037-0.044
{0.940-1.1181

~0.1I04-0.012

t

J

_.--~

(0.7112-1.2701
TYP ALL LEADS

~

_I L

L~

OJ-0.Ol1
(0.356-0.4831
TVP

{1.2701
1YP

NS Package M20B

0.596-0.612
115.14-15.54)
20 19 18 17

t--i::~=:::I­
.!J!!=.Yl!.

.!2!!._1 ~
10.4321

0.037 - O.INC

.!:!!!.=!.!!!.

10.940 - 1.1181

12.362 - 2.1421

t

.45'

10.229-0.3301

TYPALL LEADS

~+=[..-J.J:J.!==~~'~L~l.,

t

t

0° _8° TYP ALL LEADS

i J

0.004

iDTo2i

~

[:Jo~

t

{0.71I2-1.2701
1YP AlL LEADS

15

14

13

B

18

11

12

fii10titiritiri
J I_~
J
(1.270)

All lEAD TIPS

NS Package M24B

4-6

"I

1&

0.004-0.012

{0.,02r- 3GBI

Q-0.Ol1
{0.35&-0.4831
TVP

0.090

(2.116)

1E

0.743 - 0.770
(18.87 - 19.56)

0.092 (2 PlS)
(2.337) ~1. 13
2PLS

12

"

--.

Ill-+

C\

PIN NO.1 IDENT ~
-,..;

0.280
(7.112)

~

0.250 ±0.005
(6.350 ±0.127)

_~

.1

(0.229-0.381 )

fJ

0.075 ±0.015
(1.906 >0.381)

I.

OPTIONS 2.3

0.145 - 0.200
(3.683 - 5.080)

900 ±4°

ILL
--l

+1.01&)
\8.265 -0.381

~~

0.100.0.010

0.018 ±0.003
(0.457 '0.076)
0.125 - 0.140

(2.540 ±O.2&4)

(3.175 - 3.556)
N14AlAEV 0)

NS Package N14A

0.092
(2.337)

DIANDM
(2X)

0.280

0.065

95°.6°

0.009-0.015

tJ

I_"
_
~ tc

i2t+
yp

0.018 ±0.003
0.125-0.140
(0.457'0.07&) (3.175-3.556)

0.326 -0:015

0.020

(oM~~8)

( 8265 +1.016)
.
-8.381

N16A(REVEJ

NS Package N16A

4-7

RAD

1

(1.651)

95"t6°

0.032 ± 0.005
(0.813 ±0.127)

_ P I N NO.lIDENT

0.130 '0.005
(3.302 >0.127)

OPTION 1

+0.040
0.325 -0.815

1

""'ffi=';F."i"'i'Ti"'ffi=i7T9.'i==m=d-.i.

MIN

I.

e

10

1.013-1.040
(25.73-26.42)

0.092 X0.030
(2.337 X 0.762)
MAXDP

=:1

~======~~~17~~16~~1~5~1;4~1~3~I~Z~~II~

0.032±o.o05~0
19

-r

(0.813±0.127)
RAD

0.260 ±0.005
(6.604 ±0.127)

PIN NO.1 IDENT

PIN NO.lIDENT~

~rnT.mm~~~mm~~

I

DPTlONZ

0.065
(1.651)

~hI"++,,on~~~~"

f

0.009-0.01JJ
(0.229-0.381)

I.

I-

TYP

+0040
0.325 -0:015

0.000.0.005
(1.524.0.127)

0.01"0.003
(0.457>0.076)

0.020
(0.508)
MIN

~ 1_

'8255 +1.018
~ .
-D.381
N20AIRevG)

NS Package N20A

f-------I~:~=~:~:I-------I·I
13

0.1182
(1.676)
RAO
PIN NO.lIDENT

C±>

C±>

i1

I 0.640 ±0.006

~~~~Tn=F.~~~=F.~F.F~FT.~~~rYl
,

::Jl±o.'211

DOTTED OUTLINES
REFLECT ALTERNATE
MOLDED BODY CONFIGURATION

~

~

, t

TYP
0.016
0.018±0 03 0.126-0.140 10.3811
0.100 ±0.0101110.467 ±0.878) 13.175-3.5661 MIN
12.640 ±0.2141

_11_

N24A(AEVEI

NS Package N24A

4·8

1.243-1.270
(31.57 -32.26)

I
~~~MAX!!!:6!:!:f:!:::~~_t

0.092
(2.337)
(2 PLS)
PIN NO.1
IDENT

0.260±0.005
16.604±0.127)

I
OPTION 2

0.062
(1.575)
RAO

0.040
0.130+0.005
13.302±0.127)

f
0.009-0.015
(0.229-0.381)
+0040
0.325 -0:015

la 255 +1.016)

(.

0.020
(O.508) 0.145-0.200
MIN 13.683-5.080)

0.065
(1.651)
0.280
(7.112)MIN

-1-_-==---1

-r-_

0.075±0.015
(1.905±0.3Bl)

I

I--

-0.381

NS Package N24C

4·9

N24C(REVFj

NOTES

~ Semiconductor
NatiOnal

Corporation

Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
Please contact your local National sales office for possible complimentary copies. A listing of sales offices follows this
bookshelf.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 23-200
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
For a recorded update of this listing plus ordering information for these books from National's Literature Distribution operation,
please call (408) 749-7378.

DATA CONVERSION/ACQUISITION DATABOOK-1984
Selection Guides • Active Filters. Amplifiers. Analog Switches. Analog-to-Digital Converters
Analog-to-Digital Display (DVM) • Digital-to-Analog Converters. Sample and Hold. Sensors/Transducers
Successive Approximation Registers/Comparators. Voltage References

HYBRID PRODUCTS DATABOOK-1982
Operational Amplifiers. Buffers • Instrumentation Amplifiers. Sample & Hold Amplifiers. Comparators
Non-Linear Functions. Precision Voltage Regulators and References. Analog Switches
MOS Clock Drivers. Digital Drivers. A-D Converters. D-A Converters. Fiber-Optic Products
Active Filters & Telecommunication Products. Precision Networks. 883/RETS

INTERFACE DATABOOK-1986
Transmission Line Drivers/Receivers • Bus Transceivers. Peripheral/Power Drivers. Display Controllers/Drivers
Memory Support • Microprocessor Support. level Translators/Buffers. Frequency Synthesis

INTERFACE/BIPOLAR LSI/BIPOLAR MEMORY/PROGRAMMABLE LOGIC
DATABOOK-1983
Transmission Line Drivers/Receivers. Bus Transceivers. Peripheral/Power Drivers
level Translators/Buffers. Display Controllers/Drivers. Memory Support. Dynamic Memory Support
Microprocessor Support. Data Communications Support. Disk Support. Frequency Synthesis
Interface Appendices. Bipolar PROMs. Bipolar and ECl RAMs. 2900 Family/Bipolar Microprocessor
Programmable logic

INTUITIVE IC CMOS EVOLUTION-1984
Thomas M. Frederiksen's new book targets some of the most Significant transitions in semiconductor technology since the
change from germanium to silicon. Intuitive IC CMOS Evolution highlights the transition in the reduction in defect densities and
the development of new circuit topologies. The author's latest book is a vital aid to engineers, and industry observers who need
to stay abreast of the semiconductor industry.

INTUITIVE IC OP AMPS-1984
Thomas M. Frederiksen's new book, IntuitivelC Op Amps, explores the many uses and applications of different IC op amps.
Frederiksen's detailed book differs from others in the way he focuses on the intuitive groundwork in the basic functioning
concepts of the op amp. Mr. Frederiksen's latest book is a vital aid to engineers, deSigners, and industry observers who need to
stay abreast of the computer industry.

LINEAR APPLICATIONS HANDBOOK-1986
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed SUbject Index.

LINEAR SUPPLEMENT DATABOOK-1984
Amplifiers. Comparators. Voltage Regulators. Voltage References. Converters. Analog Switches
Sample and Hold • Sensors. Filters. Building Blocks. Motor Controllers. Consumer Circuits
Telecommunications Circuits. Speech. Special Analog Functions

LOGIC DATABOOK VOLUME 1-1984
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. LSIIVLSI

LS/S/TTL DATABOOK-1987
Introduction to Bipolar LQgic • Low Power Schottky. Schottky. TIL • Low Power

MASS STORAGE HANDBOOK-1986
Disk Interface Design Guide and User Manual. Winchester Disk Support. Winchester Disk Data Controller
Floppy Disk Support. Drive Interface Support Circuits

MEMORY SUPPORT HANDBOOK-1986
Dynamic Memory Control. Error Checking and Correction. Microprocessor Interface and Applications
Memory Drivers and Support

THE NSC800 MICROPROCESSOR FAMILY DATABOOK-1985
CPU • Peripherals. Evaluation Board. Logic Devices. MA2000 Macrocomponent Family

NON-VOLATILE MEMORY DATABOOK-1987
CMOS EPROMs • EEPROMs • Bipolar PROMs

SERIES 32000 DATABOOK-1986
Introduction. CPU-Central Processing Unit. Slave Processors. Peripherals. Data Communications and LAN's
Disk Control and Interface • DRAM Interface. Development Tools. Software Support. Application Notes

RANDOM ACCESS MEMORY DATABOOK-1987
Static RAMs • TIL RAMs • TIL FIFOs • ECL RAMs

RELIABILITY HANDBOOK-1986
Reliability and the Die • Internal Construction. Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process. Reliability and the Hybrid Device. VLSIIVHSIC Devices
Radiation Environment. Electrostatic Discharge • Discrete Device • Standardization
Quality Assurance and Reliability Engineering. Reliability and Documentation. Commercial Grade Device
European Reliability Programs. Reliability and the Cost of Semiconductor Ownership
ReliabilityTesting at National Semiconductor. The Total Militaryl Aerospace Standardization Program
883B/RETSTM Products. MILSIRETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products
Radiation Hardened Technology. Wafer Fabrication • Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms. Key Government Agencies. ANI Numbers and Acronyms
Bibliography. MIL-M-38510 and DESC Drawing Cross Listing

THE SWITCHED-CAPACITOR FILTER HANDBOOK-1985
Introduction to Filters. National's Switched-Capacitor Filters. DeSigning with Switched-Capacitor Filters
Application Circuits • Filter Design Program. Nomographs and Tables

TRANSISTOR DATABOOK-1982
NPN Transistors. PNP Transistors. Junction Field Effect Transistors. Selection Guides. Pro Electron Series
Consumer Series. NAINBINR Series. Process Characteristics Double-Diffused Epitaxial Transistors
Process Characteristics Power Transistors. Process Characteristics JFETs. JFET Applications Notes

VOLTAGE REGULATOR HANDBOOK-1982
Product Selection Procedures. Heat Flow & Thermal Resistance. Selection of Commercial Heat Sink
Custom Heat Sink Design. Applications Circuits and Descriptive Information. Power Supply DeSign
Data Sheets

48-SERIES MICROPROCESSOR HANDBOOK-1980
The 48-Series Microcomputers. The 48-Series Single-Chip System. The 48-Series Instruction Set
Expanding the 48-Series Microcomputers. Applications for the 48-Series • Development Support
Analog 110 Components. Communications Components. Digital 110 Components. Memory Components
Peripheral Control Components

NATIONAL SEMICONDUCTOR CORPORATION
AUTHORIZED DISTRIBUTORS
ALABAMA
Huntsville
Arrow
(205) 837-6955
Hamilton!Avnet
(205) 837-7210
Klerullf
(205) 883-6070

Pioneer
(205) 637-9300
ARIZONA
Phoenix
Kierullf
(602) 437-0750
Tempe
Anthem Electronics
(602) 966-8600
Arrow
(602) 968-4600
Bell Industries
(602) 966-7800
Hamihon!Avnet
(602) 231-5100
CALIFORNIA
Chetsworih
Anthem Electronics
(818) 700-1000
Arrow
(818) 701-7500
Hamilton Electro Sales
(818) 700-0440
Kierullf
(818) 407-2500
Costa Mesa
Avnet Electronics
(714) 754-6050
Hamilton Electro sales
(714) 641-4159
Cypress
Kierullf
(714) 220-6300
Garden Grove
Bell Industries
(714) 895-7801
Haminon Electro Sales
(213) 217-6751
Gardena
Bell Industries
(213) 515-1800
Irvine
Anthem Electronics
(714) 768-4444
Los Angeles
Klerullf
(213) 725-0325
Ontario
Hamilton!Avnet
(714) 989-4602
sacramento
Hamilton!Avnet
(916) 925-2218
(916) 922-8800
San Diego
Anthem Electronics
(619) 453-9005
Arrow
(819) 565-4800
Hamilton! Avnet
(619) 571-7510
Kierullf
(619) 278-2112

San Jose
Anthem Electronics
(408) 295-4200
Kierullf
(406) 947-3400
Sunnyvale
Arrow
(408) 745-6600
Bell Industries
(408) 734-8570
Hamilton!Avnet
(408) 743-3355
Thousand Oaks
Bell Industries
(805) 499-6821
Tustin
Arrow
(714) 838-5422
Klerullf
(714) 731-5711
COLORADO

Aurora
Arrow (303) 695-1111
Englewood
Anthem Electronics
(303) 790-4500
Hamilton! Avnet
(303) 799-9998
Kierullf
(303) 790-4444
Wheatridge
Bell Industries
(303) 424-1985
CONNECTICUT
Danbury
Hamilton! Avnet
(203) 797-2800

Meridian
Llonex Inc_
(203) 237-2282
Norwalk
Pioneer Northeast
(203) 853-1515
Wallinglord
Arrow
(203) 265-7741
Kierullf
(203) 265-1115
FLORIDA
Altamonte Springs
Pioneer
(305) 834-9090
Kierullf
(305) 662-6923
Deerfield Beach
Arrow
(305) 429-8200
Bell Industries
(813) 541-4434

Pioneer
(305) 428-8877
Fort Lauderdale
Hamilton!Avnet
(305) 971-2900
Kierullf
(305) 486-4004

Largo
Bell Industries
(813) 541-4434
Palm Bay

Arrow
(305) 725-1480

51. Petersburg
Hamilton!Avnet
(813) 576-3930
Winter Park
Hamilton!Avnet
(305) 628-3888
GEORGIA
Norcross
Arrow
(404) 449-8252
Bell Industries
(404) 662-0923
Hamilton!Avnet
(404) 447-7500

Pioneer
(404)448-1711
Klerullf
(404) 447-5252
ILLINOIS
Bensenville
Hamilton! Avnet
(312) 860-7780
Elk Grove Village
Bell Industries
(312) 640-1910

Pioneer
(312) 437-9680
Itasca
Kierullf
(312) 250-0500
Schaumberg
Arrow
(312) 397-3440
Urbana
Bell Industries
(217) 328-1077
INDIANA
Carmel
Hamilton!Avnet
(810) 260-3966
Indianapolis
Advent
(317) 872-4910
Arrow
(317) 243-9353
Bell Industries
(317) 634-8202
Pioneer
(317) 949-7300
IOWA
Cedar Rapids
Advent Electronics
(319) 363-0221
Arrow
(319) 395-7230
Bell Industries
(319) 395-0730
Hamiltonl Avnet
(319) 362-4757
KANSAS
Lenexa
Arrow
(913) 541-9542
Overiand Park
Hamilton! Avnet
(913) 888-8900
MARYLAND
Columbia
Arrow
(301) 995-0003

Uonex
(301) 984-0040

Gaithersburg

Pioneer
(301) 921-0660

Kierulff
(301) 940-1155
MASSACHUSETTS
Billerica
Kierullf
(617)667-8331
Columbia
HamiltonlAvnet
(301) 995-3500
Lexington
Pioneer Northeast
(617)861-9200
Norwood
Gerber Electronics
(617) 769-8000
Peabody
Haminon!Avnet
(617) 531-7430
Wilmington

Lionex
(617)657-5170
Woburn
Arrow
(617) 933-8130
MICHIGAN
Ann Arbor
Arrow
(313) 971-8220
Grand Rapids
Arrow
(616) 243-0912
Hamiltonl Avnet
(616) 243-8805
R-M Michigan
(616) 531-9300
Livonia
Hamilton!Avnet
(313) 522-4700

Pioneer
(313) 525-1800
MINNESOTA
Edina
Arrow
(612)830-1800
Kierullf
(612)941-7500
Minnetonka

HamiltonlAvnet
(612) 932-0800

Pioneer
(612) 935-5444
MISSOURI
Earth City
Hammon! Avnet
(314) 344-1200
Klerullf
(314) 997-4956
St Louis
Arrow
(314) 567-6888
Kierullf
(314) 997-4956
NEW HAMPSHIRE

Manchester
Arrow
(603) 668-6988
Bell Industries
(617) 273-4450
Hamilton! Avnet
(603) 624-9400

NATIONAL SEMICONDUCTOR CORPORATION
AUTHORIZED DISTRIBUTORS (Continued)
NEW JERSEY
CherTY Hill
Hamilton!Avnet
(609) 424·0100
Fairfield
Arrow
(201) 575·5300
Hamlllon!Avnet
(201) 575·3390
Kierulff
(201) 575·6750
Lionex
(201) 227·7960

Nu Horizons Electronics
(201) 882·8300
Marlton
Arrow
(609) 596·8000
Mt. Laurel
Kierulff
(809) 235·1444
Pine Brook
Pioneer Northeast
(201) 575·3510
NEW MEXICO
Albuquerque
Alliance Electronics
(505) 292·3360
Arrow
(505) 243·4566
Bell Industries
(505) 292·2700
Hamilton! Avnet
(505) 765·1500
NEW YORK
Amityville
Nu Horizons
(516) 226·6000
Brookhaven
Arrow
(516) 924·0700
Buffalo
Summit Distributors
(716) 887·2800
Fairport"
Pioneer
(716) 381·7070
Hauppauge
Arrow
(516) 231·1000
Hamilton!Avnet
(516)434-7413
Lionex
(516) 273·1680
Melville
Arrow
(516)391·1300
Rochester
Arrow
(716) 427-0300
Hamilton!Avnet
(716) 475·9130
Summit Electronics
(716) 334·8110
Syracuse
Hamilton!Avnet
(315)437·2841
Vestal
Pioneer
(807)748·8211
Westbury
Hemllton! Avnet
(516) 997-6868
Woodbury
Pioneer
(516) 921·8700

NORTH CAROUNA
Charlotte
Pioneer
(704) 527·8188
Raleigh
Arrow
(919) 876-3132
Hamilton!Avnet
(919) 878-0810
Kierulff
(919) 872-8410
Salem
Arrow
(919) 725-8711
OHIO
Beachwood
Kierulff
(216) 831·5222
Centerville
Arrow
(513) 435·5563
Cleveland
Hamilton! Avnet
(216) 831·3500
Pioneer
(216) 587·3600
Columbus
Arrow
(614) 885-8362
Dayton
Bell Industries
(513) 435-8880
(513) 434-8231
Hamilton!Avnet
(513) 439-6700
Pioneer
(513) 236-9900
Kierulff
(513) 439-0045
Highland Heights
CAM!OHIO
(216) 461-4700
Salon
Arrow
(216) 248·3990
Westerville
Hamilton! Avnet
(614) 882·7004
OKLAHOMA
Tulsa
Arrow
(918) 665-7700
Kierulff
(918) 252·7537
Quality Components
(918) 664-8812
Radio Inc.
(918) 587·9123
OREGON
Beaverton
Almac Electronics
(503) 629·8090
Anthem Electronics
(503) 843·1114
Lake Oswego
Bell Industries
(503)241-4115
Hamilton!Avnet
(503) 635-7850
Portland
Kierulff
(503) 641·9150
Tigard
Arrow
(503) 684-1690

PENNSYLVANIA
Horsham
Llonex
(215) 443·5150
Pioneer
(215) 674-4000
Monroeville
Arrow
(412) 856-7000
Pittsburgh
CAMRPC
(412) 782-3770
Hemilton!Avnet
(412)281-4150
Pioneer
(412) 782·2300
TEN~EE

NbliVilie
Bell Industries
(615) 367-4400
TEXAS
Addison
Quality Components
(214) 733·4300
Austin
Arrow
(512) 835-4180
Hemilton!Avnet
(512)837·8911
Kierulff
(512) 835-2090
Pioneer
(512) 835-4000
Quality Components
(512) 835·0220
Carrollton
Arrow
(214) 380-6484
Dallas
Kierulff
(214) 343·2400
Pioneer
(214) 386·7300
Houston
Arrow
(713) 530-4700
Kierulff
(713) 530-7030
Pioneer
(713) 988·5555
Irving
Hamilton!Avnet
(214) 550·7755
Stafford
Hamilton!Avnet
(713) 240·7733
Sugarland
Quality Components
(713) 491·2255

UTAH .

Lake

Selt
City
Anthem Electronics
(801) 973-8555
Arrow
(801) 972·0404
Bell Industries
(801) 972·6969
Hemillon! Avnet
(801) 972-4300
Kierulff
(801) 973-6913

WASHINGTON
Bellevue
Almanac Electronics
(208) 843·9992
Arrow
(206) 843-4800
Hamilton!Avnet
(206) 453·5844
Redmond
Anthem Electronics
(206) 881-0850
WISCONSIN
Brookfield
Arrow
(414) 792-0150
Milwaukee
Taylor Electric Co.
(414) 241-4321
New Berlin
Hamiltonl Avnet
(414) 784-4516
Waukesha
Bell Industries
(414) 547-8879
Klerulff
(414) 784-8160
CANADA
Weatern province.
Calgary
Hainilton!Avnet
(403) 230-3586
Zentronics
(403) 272·1021
Edmoirton
Zentronics
(403) 488·9306
Richmorid
Zentronics
(604) 694·1957
Winnipeg
Zentronles
(204) 775-8661
Eastam Provinces
Brampton
Zentronics
(416) 451·9600

Doval
Samad
(514) 636-4614
Markhem
Semad
(416) 475-8500
Mi"~ga
Hemllton!Avnet
(416) 677·7432
Nepean
Hamilton!Avnet
(613) 226·1700
Zentronics
(613) 226-8840
St Laurent
Hemilton!Avnet
(514) 331-8443
Zentronics
(514) 735-5361
Wnlowdale
Electrosonlc
(416) 494·1666

~

National
Semiconductor
Corporation
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2017:06:19 12:09:40-08:00
Modify Date                     : 2017:06:19 12:46:45-07:00
Metadata Date                   : 2017:06:19 12:46:45-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:183a09c9-ba87-014f-a518-bd0867f924f9
Instance ID                     : uuid:30441eed-1b03-b747-8438-c5a0166dcb30
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 666
EXIF Metadata provided by EXIF.tools

Navigation menu