1987_Fairchild_FACT_Logic_Data_Book 1987 Fairchild FACT Logic Data Book

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I=AIRCHILO

l~\(~T

Fairchild Advanced
CMOS Technology
Logic Data Book

© 1987 Fairchild Semiconductor Corporation,
Digital and Analog Unit
333 Western Avenue, South Portland, Maine 04106
207-775-8700 • TWX 710-221-1980

Introduction

F=AIRCHILD

Section

This data book presents advanced information on
Fairchild's very high-speed, low-power CMOS logic
family, fabricated with Fairchild's state-of-the-art
CMOS process.

1 Literature Classification, Product
Index and Selection Guide

Tabulation of device numbers to assist in locating
appropriate technical data.

Section

FACT (Fairchild Advanced CMOS Technology)
utilizes Fairchild's 1.3 /-1m Iso planar silicon gate
CMOS process to attain speeds similar to that of
Advanced Low Power Schottky while retaining the
advantages of CMOS logic, namely, ultra low power
and high noise immunity. As an added benefit,
FACT offers the system designer superior line
driving characteristics and excellent ESD and latchup immunity.

2 FACT Descriptions and Family
Characteristics

Basic information on FACT performance including
technologies.

Section

3 Ratings, Specifications and
Waveforms

Section

4 Design Considerations

Information to assist both TTL and CMOS
designers to get the most out of Fairchild's FACT
family.

The FACT family consists of devices in two
categories:
1. AC, standard logic functions with CMOS
compatible inputs and TTL and MOS
compatible outputs;
2. ACT, standard logic functions with TTL
compatible inputs and TTL and MOS
compatible outputs.

Section

5 Data Sheets

Section

6 Package Outlines and Ordering
Information

Section

7 CMOS Gate Array Family FGC
Series

Section

8 CMOS Gate Array Computer
Aided Design Tools

Section

9 CMOS Gate Array Packaging

Section 10 Field Sales Offices and
Distributor Locations

iii

I=AIRCHILD

Table of Contents

Section 1

Section 6

Literature Classification, Product
Index and Selection Guide

Literature Classification
Product Index
Selection Guide
G~es

Registers
Flip-Flops
Latches
Counters
Buffers/Line Drivers
FIFOs
Decoders/Demulti plexers
Arithmetic Functions
Shift Registers
Multiplexers
Comparators
Transceivers/Registered Transceivers

1-2
1-3
1-7
1q
1-7
1-8
1-9
1-9
1-10
1-10
1-10
1-10
1-11
1-11
1-11
1-12

Ordering Information
Package Outlines
Plastic Dual In-Line
Ceramic Dual In-Line
Side Brazed Dual In-Line
Small Outline Integrated Circuit
Plastic Chip Carrier
Ceramic Leadless Chip Carrier
Ceramic Flatpak

Section 7
Section 8
Section 9

Section 2

FACT Descriptions and Family
Characteristics

Family Characteristics
Logic Family Characteristics
Circuit Characteristics

Section 3
Section 4

Ratings, Specifications and
Waveforms

3-3

Design Considerations
4-3
4-5
4-7
4-7
4-9
4-10

Section 5

5-3

Data Sheets

4-13
4-14
4-16

v

6-3
6-4
6-4
6-7
6-11
6-12
6-15
6-18
6-19

FGC Series Advanced
2-Micron Gate Array Family

7-3

FAIRCAD™ Semicustom
Design System

8-3

CMOS Arrays Packaging
Guide

9-3

Section 10 Field Sales Offices and
Distributor Locations

2-3
2-8
2-10

Interfacing
Line Driving
CMOS Bus Loading
Crosstalk
Ground Bounce
Decoupling Requirements
TTL-Compatible CMOS Designs Require
Delta ICC Consideration
Testing Advanced CMOS Devices with
I/O Pins
Testing Disable Times of 3-State Outputs
in a Transmission Line Environment

Package Outlines and Ordering
Information

10-3

Product Index and Selection Guide

FAcr Descriptions and Family Characteristics

Ratings, Specifications and Waveforms

Design Considerations

IData Sheets
Package Outlines and Ordering Information

FGC Series Advanced 2·Micron CMOS Gate Array

FAIRCAD™ Semicustom Design System

ICMOS Arrays Packaging Guide
Field Sales Offices and Distributor Locations

Literature Classification

Preliminary: This product is in sampling or preproduction stage. This document contains advanced information and specifications that are subject to change without notice. Fairchild reserves the right to make
changes at any time in order to improve design and provide the best product possible.

1-2

I=AIRCHILC

Product Index and
Selection Guide

Product Index
'ACXX Devices -

CMOS Input Levels

Device No.

Description

54AC/74ACOO
54AC/74AC02
54AC/74AC04
54AC/74AC08

Quad 2-lnput NAND Gate
Quad 2-lnput NOR Gate
Hex Inverter
Quad 2-lnput AND Gate

5-3
5-5
5-7
5-9

54AC/74AC10
54AC/74AC11
54AC/74AC14
54AC/74AC20

Triple 3-lnput NAND Gate
Triple 3-lnput AND Gate
Hex Inverter Schmitt Trigger
Dual 4-lnput NAND Gate

5-11
5-13
5-15
5-18

54AC/74AC32
54AC/74AC74
54AC/74AC86
54AC/7 4AC1 09

Quad 2-lnput OR Gate
Dual 0 Flip-Flop
Quad 2-lnput Exclusive-OR Gate
Dual Ji< Positive Edge-Triggered Flip-Flop

5-20
5-22
5-27
5-29

54AC/74AC138
54AC/74AC139
54AC/74AC151
54AC/74AC153

1-of-8 Decoder/Demultiplexer
Dual 1-of-4 Decoder/Demultiplexer
8-lnput Multiplexer
Dual 4-lnput Multiplexer

5-34
5-39
5-43
5-47

54AC/74AC157
54AC/74AC158
54AC/74AC160
54AC/74AC161

Quad 2-lnput Multiplexer
Quad 2-lnput Multiplexer
BCD Decade Counter, Asynchronous Reset
4-Bit Binary Counter, Asynchronous Reset

5-51
5-55
5-59
5-66

54AC/74AC162
54AC/74AC163
54AC/74AC168
54AC/74AC169

BCD
4-Bit
4-Bit
4-Bit

5-59
5-66
5-77
5-77

54AC/74AC174
54AC/74AC175
54AC/74AC190
54AC/74AC191

Hex 0 Flip-Flop with Master Reset
Quad 0 Flip-Flop with Master Reset
Up/Down Decade Counter
UplDown Binary Counter

5-85
5-89
5-94
5-94

54AC/74AC192
54AC/74AC193
54AC/74AC240
54AC/74AC241

Up/Down Decade Counter
UplDown Binary Counter
Octal Buffer/Line Driver
Octal Buffer/Line Driver

5-102
5-102
5-109
5-112

54AC/74AC244
54AC/74AC245
54AC/74AC251
54AC/74AC253

Octal Buffer/Line Driver
Octal Bidirectional Transceiver
8-lnput Multiplexer
Dual 4-lnput Multiplexer

5-115
5-118
5-121
5-125

Page No.

Decade Counter, Synchronous Reset
Binary Counter, Synchronous Reset
Bidirectional Binary Counter
Bidirectional Binary Counter

1-3

•

,I

II

Device No.

Description

Page No.

54AC/74AC257
54AC/74AC258
54AC/74AC273
54AC/74AC299

Quad
Quad
Octal
Octal

2·lnput Multiplexer
2-lnput Multiplexer
D Flip-Flop
Shift/Storage Register

5·129
5-133
5-137
5-142

54AC/74AC323
54AC/74AC352
54AC/74AC353
54AC/74AC373

Octal Shift/Storage Register
Dual 4·lnput Multiplexer
Dual 4·lnput Multiplexer
Octal D Latch

5·149
5·156
5·161
5·165

54AC/74AC37 4

54AC/74AC377
54AC/74AC378
54AC/74AC379

Octal D Flip-Flop
Octal D Flip·Flop with Clock Enable
Parallel D Register with Enable
Quad D Flip·Flop with Enable

5·170
5·175
5·180
5·185

54AC/74AC398
54AC/74AC399
54AC/74AC520
54AC/74AC521

Quad 2·Port Register
Quad 2·Port Register
8-Bit Identity Comparator with Pull·Up Resistors
8-Bit Identity Comparator

5·190
5·190
5-223
5·223

54AC/74AC533
54AC/74AC534
54AC/74AC540
54AC/74AC541

Octal
Octal
Octal
Octal

5·228
5·233
5-238
5·238

54AC/74AC563
54AC/74AC564
54AC/74AC568
54AC/74AC569

Octal D Latch
Octal D Flip-Flop
4-Bit Bidirectional Decade Counter
4-Bit Bidirectional Binary Counter

5·241
5·246
5·251
5·251

54AC/74AC573
54AC/74AC574
54AC/74AC640
54AC/74AC643

Octal
Octal
Octal
Octal

5-260
5·265
5-270
5·273

54AC/74AC646
54AC/74AC648
54AC/74AC705
54AC/74AC708

Octal Bus Transceiver and Register
Octal Bus Transceiver and Register
DSP ALU
64 x 9 FIFO Memory

5·276
5-280
5-284
5-296

54AC/74AC723
54AC/74AC725
54AC/74AC818
54AC/74AC821

64 x 9 FIFO
512 x 9 FIFO
Diagnostic and Pipeline Register
10·Bit D Flip·Flop

5·314
5-330
5-346
5·354

54AC/74AC822
54AC/74AC823
54AC/74AC824
54AC/74AC825

10·Bit D Flip·Flop
9-Bit D Flip·Flop
9-Bit D Flip·Flop
8·Bit D Flip·Flop

5·354
5-359
5·359
5-366

Transparent Latch
D Flip·Flop
Buffer/Line Driver
Buffer/Line Driver

D Latch
D Flip·Flop
Transceiver
Transceiver

1·4

Page No.

Device No.

Description

54AC/74AC826
54AC/74AC841
54AC/74AC842
54AC/74AC843

8·Bit D Flip·Flop
10·Bit Transparent Latch
10·Bit Transparent Latch
9·Bit Transparent Latch

5·366
5·373
5·373
5·378

54AC/74AC844
54AC/74AC845
54AC/74AC846
54AC/74AC1010

9·Bit Transparent Latch
8·Bit Transparent Latch
8·Bit Transparent Latch
16 x 16 Multiplier/Accumulator

5·378
5·385
5·385
5·392

54AC/74AC1016
54AC/74AC1017

16 x 16 Parallel Multiplier
16 x 16 Parallel Multiplier with Common Clock

5·402
5-413

'ACTXX Devices -

TTL Input Levels

54ACT/74ACTOO
54ACT/74ACT04
54ACT/74ACT08
54ACT/74ACT14

Quad 2·lnput NAND Gate
Hex Inverter
Quad 2-lnput AND Gate
Hex Inverter Schmitt Trigger

5·3
5-7
5·9
5-15

54ACT/74ACT32
54ACT/74ACT74
54ACT/74ACT109
54ACT/74ACT138

Quad 2-lnput OR Gate
Dual D Flip·Flop
Dual JK Positive Edge·Triggered Flip·Flop
1·of·8 Decoder/Demultiplexer

5·20
5·22
5·29
5·34

54ACT/74ACT139
54ACT/74ACT151
54ACT/74ACT153
54ACT/74ACT157

Dual 1·of·4 DecoderlDemultiplexer
8-lnput Multiplexer
Dual 4-lnput Multiplexer
Quad 2·lnput Multiplexer

5·39
5·43
5·47
5·51

54ACT/74ACT158
54ACT/74ACT160
54ACT/74ACT161
54ACT/74ACT162

Quad 2·lnput Multiplexer
BCD Decade Counter, Asynchronous Reset
4-Bit Binary Counter, Asynchronous Reset
BCD Decade Counter, Synchronous Reset

5-55
5-59
5-66
5-59

54ACT/74ACT163
54ACT/74ACT174
54ACT/74ACT175
54ACT/74ACT240

4-Bit Binary Counter, Synchronous Reset
Hex D Flip·Flop with Master Reset
Quad D Flip·Flop
Octal Buffer/Line Driver

5·66
5-85
5-89
5-109

54ACT/74ACT241
54ACT/74ACT244
54ACT/74ACT245
54ACT/74ACT251

Octal Buffer/Line Driver
Octal Buffer/Line Driver
Octal Bidirectional Transceiver
8-lnput Multiplexer

5-112
5-115
5-118
5-121

54ACT/74ACT253
54ACT/74ACT257
54ACT/74ACT258
54ACT/74ACT273

Dual 4-Bit Multiplexer
Quad 2-lnput Multiplexer
Quad 2-lnput Multiplexer
Octal D Flip·Flop

5·125
5-129
5-133
5-137

1-5

•

Device No.

Description

54ACT/74ACT299
54ACT/74ACT323
54ACT/74ACT352
54ACT/74ACT353

Octal Shift/Storage Register
Octal Shift/Storage Register
Dual 4-lnput Multiplexer
Dual 4-lnput Multiplexer

5-142
5-149
5-156
5-161

54ACT/74ACT373
54ACT/74ACT374
54ACT/75ACT377
54ACT/74ACT378

Octal D Latch
Octal D Flip-Flop
Octal D Flip-Flop with Clock Enable
Parallel D Register with Enable

5-165
5-170
5-175
5-180

54ACT/74ACT379
54ACT/74ACT398
54ACT/74ACT399
54ACT/74ACT488

Quad D Flip-Flop with Enable
Quad 2-Port Register
Quad 2-Port Register
General Purpose Interface Bus (GPIB) Circuit

5-185
5-190
5-190
5-195

54ACT/74ACT520
54ACT/74ACT521
54ACT/74ACT533
54ACT/74ACT534

8-Bit Identity Comparator with Pull-Up Resistors
8-Bit Transparent Comparator
Octal Transparent Latch
Octal D Flip-Flop

5-223
5-223
5-228
5-233

54ACT/74ACT540
54ACT/74ACT541
54ACT/74ACT563
54ACT/74ACT564

Octal
Octal
Octal
Octal

Buffer/Line Driver
Buffer/Line Driver
D Latch
D Flip-Flop

5-238
5-238
5-241
5-246

54ACT/74ACT573
54ACT/74ACT640
54ACT/74ACT643

Octal
Octal
Octal
Octal

D Latch
D Flip-Flop
Transceiver
Transceiver

5-260
5-265
5-270
5-273

54ACT/74ACT705
54ACT/74ACT708
54ACTl74ACT723
54ACT/74ACT725

DSP ALU
64 x 9 FIFO Memory
64 x 9 FIFO
512 x 9 FIFO

5-284
5-296
5-314
5-330

54ACT/74ACT818
54ACT/74ACT821
54ACT/74ACT822
54ACT/74ACT823

Diagnostic and Pipeline Register
10-Bit D Flip-Flop
10-Bit D Flip-Flop
9-Bit D Flip-Flop

5-346
5-354
5-354
5-359

54ACT/74ACT824
54ACT/74ACT825
54ACT/74ACT826
54ACTl74ACT841

9-Bit D Flip-Flop
8-Bit D Flip-Flop
8-Bit D Flip-Flop
10-Bit Transparent Latch

5-359
5-366
5-366
5-373

54ACT/74ACT842
54ACT/74ACT843
54ACT/74ACT844
54ACT/74ACT845

10-Bit Transparent Latch
9-Bit Transparent Latch
9-Bit Transparent Latch
8-Bit Transparent Latch

5-373
5-378
5-378
5-385

54ACT/74ACT846
54ACT/74ACT1010
54ACT/74ACT1016
54ACTl74ACT1017

8-Bit Transparent Latch
16 x 16 Multiplier/Accumulator
16 x 16 Parallel Multiplier
16 x 16 Parallel Multiplier with Common Clock

5-385
5-392
5-402
5-413

54ACT/74ACT57 4

Page No.

1-6

Selection Guide
Gates
Device

Page
No.

NAND
Quad 2·lnput
Quad 2-lnput
Triple 3-lnput
Dual 4-lnput

54AC/74ACOO
54ACT/74ACTOO
54AC/74AC10
54AC/74AC20

5·3
5-3
5-11
5-18

AND
Quad 2-lnput
Quad 2-lnput
Triple 3-lnput

54AC/74AC08
54ACT/74ACT08
54AC/74AC11

5-9
5-9
5-13

OR/NOR/Exclusive-OR
Quad 2-lnput OR
Quad 2-lnput OR
Quad 2-lnput NOR
Quad 2-lnput Exclusive-OR

54AC/74AC32
54ACT/74ACT32
54AC/74AC02
54AC/74AC86

5-20
5-20
5-5
5-27

Invert
Hex Inverter
Hex Inverter
Hex Schmitt Trigger Inverter
Hex Schmitt Trigger Inverter

54AC/74AC04
54ACT/74ACT04
54AC/74AC14
54ACT/74ACT14

5-7
5-7
5-15
5-15

Function

Registers
Function

Quad 2-Port Register
Quad 2-Port Register
Quad 2-Port Register
Quad 2-Port Register
Diagnostic and Pipeline Register
Diagnostic and Pipeline Register

Device

Clock
Inputs

Page
No.

54AC/74AC398
54ACT/74ACT398
54AC/74AC399
54ACT/74ACT399
54AC/74AC818
54ACT/74ACT818

1(.f)
1(I)
1(.f)
1(.f)
2
2

5-190
5-190
5·190
5-190
5-346
5-346

•

Flip·Flops
Function
Dual D
Dual D
Dual JK
Dual JK
Quad D
Quad D
Quad D
Quad D
Hex D
Hex D
Hex D
Hex D
Octal D
Octal D
Octal D
Octal D
Octal D
Octal D
Octal D
Octal D
Octal D
Octal D
Octal D
Octal D
Octal D
Octal D
Octal D
Octal D
9-Bit D
9-Bit D
9-Bit D
9-Bit D
10-Bit D
10-Bit D
10-Bit D
10-Bit D

Device
54AC/74AC74
54ACT/74ACT74
54AC/7 4AC1 09
54ACT/74ACT109
54AC/74AC175
54ACT/74ACT175
54AC/74AC379
54ACT/74ACT379
54AC/74AC174
54ACT/74ACT174
54AC/74AC378
54ACT/74ACT378
54AC/74AC273
54ACT/74ACT273
54AC/74AC374
54ACT/74ACT37 4
54AC/74AC377
54ACT/74ACT377
54AC/74AC534
54ACT/74ACT534
54AC/74AC564
54ACT/74ACT564
54AC/74AC574
54ACT/74ACT574
54AC/74AC825
54ACT/74ACT825
54AC/74AC826
54ACT/74ACT826
54AC/74AC823
54ACT/74ACT823
54AC/74AC824
54ACT/74ACT824
54AC/74AC821
54ACT/74ACT821
54AC/74AC822
54ACT/74ACT822

1-8

3·State
Outputs

Master
Reset

No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

Page
No.
5·22
5-22
5-29
5-29
5-89
5-89
5-185
5-185
5-85
5-85
5-180
5-180
5-137
5-137
5-170
5-170
5-175
5-175
5-233
5-233
5-246
5-246
5-265
5-265
5-366
5-366
5-366
5-366
5-359
5-359
5-359
5-359
5-354
5-354
5-354
5-354

Latches
Function

Octal
Octal
Octal D
Octal D
Octal D
Octal D
Octal Transparent
Octal Transparent
Octal Transparent
Octal Transparent
Octal Transparent
Octal Transparent
9·Bit Transparent
9-Bit Transparent
9-Bit Transparent
9-Bit Transparent
10-Bit Transparent
10·Bit Transparent
10·Bit Transparent
10·Bit Transparent

Device

a·State
Outputs

Broadside
Pinout

Page
No.

54AC/74AC373
54ACT/74ACT373
54AC/74AC563
54ACT/74ACT563
54AC/74AC573
54ACT/74ACT573
54AC/74AC533
54ACT/74ACT533
54AC/74AC845
54ACT/74ACT845
54AC/74AC846
54ACT/74ACT846
54AC/74AC843
54ACT/74ACT843
54AC/74AC844
54ACT/74ACT844
54AC/74AC841
54ACT/74ACT841
54AC/74AC842
54ACT/74ACT842

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

No
No

5·165
5·165
5·241
5·241
5·260
5·260
5·228
5·228
5·385
5·385
5·385
5·385
5·378
5·378
5·378
5·378
5·373
5·373
5-373
5·373

Yes
Yes
Yes
Yes

No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

Counters
Function

BCD
BCD
BCD
BCD
4·Bit
4-Bit
4·Bit
4-Bit
4·Bit
4-Bit
4·Bit
4·Bit
4-Bit
4·Bit
4-Bit
4·Bit

Decade
Decade
Decade
Decade
Decade
Decade
Decade
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary

Device

54AC/74AC160
54ACT/74ACT160
54AC/74AC162
54ACTl74ACT162
54AC/74AC190
54AC/74AC192
54AC/74AC568
54AC/74AC161
54ACT/74ACT161
54AC/74AC163
54ACT/74ACT163
54AC/74AC168
54AC/74AC169
54AC/74AC191
54AC/74AC193
54AC/74AC569

Parallel
Entry

S
S
S
S
A
A

S
S
S
S
S
S
S
A
A

S

S = Synch ronous
A = Asynchronous

1·9

Reset

UfO

A
A

No
No
No
No

S
S

-

A
S/A
A
A

S
S

-

A
S/A

Yes
Yes
Yes

No
No
No
No

a·State
Outputs

Page
No.

No
No
No
No
No
No

5-59
5-59
5-59
5-59
5-94
5-102
5-251
5-66
5·66
5·66
5-66
5-77
5·77
5-94
5-102
5·251

Yes

Yes
Yes
Yes
Yes

No
No
No
No
No
No
No
No

No

Yes

II

Buffers/Line Drivers
Function
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal
L= LOW

Enable
Inputs
(Level)

Invertingl
Non·lnverting

Broadside
Pinout

Page
No.

2(L)
2(L)
1(H) & 1(L)
1(H) & 1(L)
2(L)
2(L)
2(L)
2(L)
1(H) & 1(L)
1(H) & 1(L)

I
I
N
N
N
N
I
I
N
N

No
No
No
No
No
No
Yes
Yes
Yes
Yes

5·109
5·109
5·112
5·112
5·115
5·115
5·238
5·238
5·238
5·238

Device
54AC/74AC240
54ACT/74ACT240
54AC/74AC241
54ACT/74ACT241
54AC/74AC244
54ACT/74ACT244
54AC/74AC540
54ACT/74ACT540
54AC/74AC541
54ACT/74ACT541
H = HIGH

FIFOs
Function
64 x 9 FIFO Memory
64 x 9 FIFO Memory
64 x 9 FIFO
64 x 9 FIFO
512 x 9 FIFO
512 x 9 FIFO

Device
54AC/74AC708
54ACT/74ACT708
54AC/74AC723
54ACT/74ACT723
54AC/74AC725
54ACT/74ACT725

Input

Output

3·State
Outputs

Page
No.

Parallel
Parallel
Parallel
Parallel
Parallel
Parallel

Parallel
Parallel
Parallel
Parallel
Parallel
Parallel

Yes
Yes
Yes
Yes
Yes
Yes

5·296
5·296
5·314
5·314
5-330
5-330

Decoders/Demultiplexers
Function
1-01-8
1-01-8
Dual 1-01-4
Dual 1'01-4

Device

LOW
Enable

Active·
HIGH
Enable

Active·
LOW
Outputs

Active·
Address
Inputs

Page
No.

2
2
1&1
1&1

1
1
No
No

8
8
4&4
4&4

3
3
2&2
2&2

5-34
5·34
5·39
5-39

54AC/74AC138
54ACT/74ACT138

54AC/74AC139
54ACT/74ACT139

Arithmetic Functions
Function

Device

Features

16 x 16 Multiplier/Accumulator
16 x 16 Multiplier/Accumulator
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
16 x 16 Multiplier
Arithmetic Logic Unit 10r DSP

54AC/7 4AC1 01 0

Arithmetic Logic Unit 10r DSP

54ACT/74ACT705

54ACTJ74ACT1010
54AC/74AC1016
54ACT/74ACT1016
54AC/7 4AC1 017
54ACT/7 4ACT1 017
54AC/74AC705

1-10

2s Complement & Unsigned Arithmetic
2s Complement & Unsigned Arithmetic
2s Complement & Unsigned Arithmetic
2s Complement & Unsigned Arithmetic
Common Clock
Common Clock
16·8it ALU and 8 x 8 Parallel Multiplierl
Accumulator
16-8it ALU and 8 x 8 Parallel Multiplierl
Accumulator

Page
No.
5-392
5-392
5-402
5·402
5-413
5-413
5-284
5-284

Shift Registers
Function
Octal
Octal
Octal
Octal

No. of
Bits

Device
54AC/74AC299
54ACT/74ACT299
54AC/74AC323
54ACT/74ACT323

Shift/Storage
Shift/Storage
Shift/Storage
Shift/Storage

A =Asynchronous

8
8
8
8

Reset
A

A
S
S

Serial
Inputs

3·State
Outputs

Page
No.

2
2
2
2

Yes
Yes
Yes
Yes

5·142
5·142
5·149
5·149

S =Synchronous

Multiplexers
Function

Device

8·lnput
8·lnput
8·lnput
8·lnput
Dual 4·lnput
Dual 4·lnput
Dual 4·lnput
Dual 4·lnput
Dual 4·lnput
Dual 4·lnput
Dual 4·lnput
Dual 4·lnput
Quad 2·lnput
Quad 2·lnput
Quad 2·lnput
Quad 2·lnput
Quad 2·lnput
Quad 2·lnput
Quad 2·lnput
Quad 2·lnput

54AC/74AC151
54ACT/74ACT151
54AC/74AC251
54ACTJ74ACT251
54AC/74AC153
54ACT/74ACT153
54AC/74AC253
54ACT/74ACT253
54AC/74AC352
54ACT/74ACT352
54AC/74AC353
54ACT/74ACT353
54AC/74AC157
54ACT/74ACT157
54AC/74AC158
54ACT/74ACT158
54AC/74AC257
54ACTJ74ACT257
54AC/74AC258
54ACT/74ACT258

Enable
Inputs
(Level)

True
Output

Complement
Output

Page
No.

1(L)
1(L)
1(L)
1(L)
2(L)
2(L)
2(L)
2(L)
2(L)
2(L)
2(L)
2(L)
1(L)
1(L)
1(L)
1(L)
1(L)
1(L)
1(L)
1(L)

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Yes
Yes
No
No
Yes
Yes
No
No

Yes
Yes
Yes
Yes
No
No
No
No
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
No
Yes
Yes

5·43
5·43
5·121
5·121
5-47
5-47
5·125
5·125
5·156
5·156
5·161
5·161
5·51
5·51
5·55
5·55
5·129
5·129
5·133
5·133

Comparators
Function
Octal
Octal
Octal
Octal

Identity
Identity
Identity
Identity

Device
Comparator
Comparator
Comparator
Comparator

54AC/74AC520
54ACT/74ACT520
54AC/74AC521
54ACT/74ACT521

1-11

Features

Page No.

Expandable
Expandable
Expandable
Expandable

5·223
5·223
5·223
5·223

•

Transceivers/Registered Transceivers
Function

Octal
Octal
Octal
Octal
Octal
Octal
Octal
Octal

Bidirectional Transceiver
Bidirectional Transceiver
Bus Transceiver & Register
Bus Transceiver & Register
Bidirectional Transceiver
Bidirectional Transceiver
Bidirectional Transceiver
Bidirectional Transceiver

Device

54AC/74AC245
54ACT/74ACT245
54AC/74AC646
54AC/74AC648
54AC/74AC640
54ACT/74ACT640
54AC/74AC643
54ACT/74ACT643

1·12

Registered

Enable
Inputs
(Level)

3·State
Output

Page
No.

No
No
Yes
Yes
No
No
No
No

1(L)
1(L)
1(L) & 1(H)
1(L) & 1(H)
1(L)
1(L)
1(L)
1(L)

Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

5·118
5·118
5·276
5·280
5·270
5·270
5·273
5·273

FGC Series-Sub 2J.1. Silicon Gate CMOS
Typical
Buffer DeIBY.'

Gate
Equiv.

Levels

Typical
Internal
Gate Delay
(ns)

FGC0500

540

TTUCMOS

1.1

2.1

FGC1200

1188

TTUCMOS

1.1

FGC2400

2625

TTUCMOS

FGC4000

3960

FGC6000

FGC8000

Product

1/0

Input
(ns)

Output
(ns)

Power

Max

(W)

1/0

2.3

·

40

20, 24, 28, 40 PDI P
20, 24, 28, 40 CDIP
44 PLCC
44 CLCC

2.0

3.8

·

73

1.1

2.0

3.8

·

24, 28, 40, 48 PDIP
24,28,40,48 CDIP
44,68 PLCC
44, 68, 84 CLCC
68,84 PPGA
68,84 CPGA

105

TTUCMOS

1.1

2.0

3.8

·

24,28,40,48,64 PDIP
24,28,40,48,64 CDIP
44, 68, 84 PLCC
44, 68, 84 CLCC
68,84,120 PPGA
68, 84, 120 CPGA

133

6000

TTUCMOS

1.1

2.0

3.8

·

40,48 PDIP
40,48 CDIP
-44, 68, 84 PLCC
44, 68, 84 CLCC
68,84, 120, 144 PPGA
68,84,120,144 CPGA
132 CFPAK

158

68,84 PLCC
68,84 CLCC
84,120, 144 PPGA
84,120,144,180 CPGA
132 CFPAK

7896

TTUCMOS

1.1

2.0

3.8

·

181

84 PLCC
84 CLCC
144 PPGA
144, 180, 209 CPGA

Packaging'

'FGC series input buffer delays for CMOS input with fanout = 2 and statistical wirelength. FGC series output buffer delay for
CL=15pF.
'PDIP = Plastic Dual In-Line, CDIP = Ceramic Dual In·Line Side Brazed, PLCC = Plastic Leaded Chip Carrier (J·Bend Leads),
CLCC = Ceramic Leaded Chip Carrier (J-Bend Leads), CPGA = Ceramic Pin Grid Array, PPGA = Plastic Pin Grid Array,
CFPAK = Ceramic Flatpak. Consult local sales office for package availability.
*Power dissipation for CMOS arrays is design/array dependent with worst case ranging from 0.25·1.0 W.

1·13

•

Product Index and Selection Guide

FACT Descriptions and Family Characteristics

Ratings, Specifications and Waveforms

Design Considerations

Data Sheets

Package Outlines and Ordering Information

FGC Series Advanced 2-Micron CMOS Gate Array

I FAIRCAD™ Semicustom Design System
ICMOS Arrays Packaging Guide
Field Sales Offices and Distributor Locations

FACT Descriptions and
Family Characteristics

F=AIACHILD

Fairchild Advanced CMOS Technology FACT - Logic

• Improved ESD Protection Network
• High Current Latch-Up Immunity

Interfacing

Fairchild Digital introduced FACT (Fairchild
Advanced CMOS Technology) logic, a family of highspeed advanced CMOS circuits, in 1985.

FACT devices have a wide operating voltage range •
(Vcc = 2 to 6 VDC) and sufficient current drive to
interface with most other logic families available
today.

FACT logic offers a unique combination of high
speed, low power dissipation, high noise immunity,
wide fanout capability, extended power supply
range and high reliability.

Device designators are as follows:
'AC - This is a high-speed CMOS device with
CMOS input switching levels and buffered CMOS
outputs that can drive ± 24 mA of 10H and 10L
current. Industry standard 'AC nomenclature and
pinouts are used.

This data book describes the product line with
device specifications as well as material discussing
design considerations and comparing the FACT
family to predecessor technologies.

'ACT - This is a high-speed CMOS device with a
TTL-to-CMOS input buffer stage. These device
inputs are designed to interface with TTL outputs
operating with a Vcc = 5 V ± 0.5 V with VOH =
2.4 V and VOL = 0.4 V, but are functional over the
entire FACT operating voltage range of 2.0 to 5.5
VDC. These devices have buffered outputs that
will drive CMOS or TTL devices with no
additional interface circuitry. 'ACT devices have
the same output structures as 'AC devices.

The 1.3-micron silicon gate CMOS process utilized
in this family has been proven in the field of high
performance gate arrays, Fairchild's 32-Bit
Microprocessor, CLIPPER, and FACT. It has been
further enhanced to meet and exceed the JEDEC
standards for 74ACXX logic.
For direct replacement of LS, ALS and other TTL
devices, the 'ACT circuits with TTL-type input
thresholds are included in the FACT family. These
include the more popular bus drivers/transceivers as
well as many other 54ACT/74ACTXXX devices.

Low Power CMOS Operation
If there is one single characteristic that justifies the
existence of CMOS, it is low power dissipation. In
the quiescent state, FACT draws three orders of
magnitude less power than the equivalent LS or
ALS TTL device. This enhances system reliability;
because costly regulated high current power
supplies, heat sinks and fans are eliminated, FACT
logic devices are ideal for portable systems such as
laptop computers and backpack communications
systems. Operating power is also very low for FACT
logic. Power consumption of various technologies
with a clock frequency of 1 MHz is shown below.

Characteristics
• Full Logic Product Line
• Industry Standard Functions and Pinouts for SSI,
MSI and LSI
• Meets or Exceeds JEDEC Standards for 74ACXX
Family
• TTL Inputs on Selected Circuits
• High Performance Outputs
Common Output Structure for Standard and
Buffer Drivers
Output Sink/Source Current of 24 mA
Transmission Line Driving 50 ohm
(Commercial)/75 ohm (Military)
Guaranteed
• Operation from 2 - 6 Volts Guaranteed
• Temperature Range -40°C to +85°C
(Commercial), -55°C to + 125°C (Military)

FACT = 0.1 mW/Gate
ALS = 1.2 mW/Gate
LS
= 2.0 mW/Gate
HC = 0.1 mW/Gate

2-3

Multiple Output Switching

Figure 2·1: Icc vs Vcc

Propagation delay is affected by the number of
outputs switching simultaneously. Typically, devices
with more than one output will follow the rule: for
each output switching, derate the databook
specification by 250 ps. This effect typically is not
significant on an octal device unless more than four
outputs are switching simultaneously. This derating
is valid for the entire temperature range and
5.0 V ± 10% Vcc .

500
CL = 50 pF @ 1 MHz

400

<'
..:;
()

.2

300

Noise Immunity
The noise immunity ofa logic family is also an
important equipment cost factor in terms of
decoupling components, power supply dynamic
resistance and regulation as well as layout rules for
PC boards and signal cables.

200
100

= Fixture Capacitance

CL

@

1 MHz

0
0

2

The comparisons shown describe the difference
between the input threshold of a device and the
output voltage, I VIL - VOL II I VIH - VOH I at
4.5 V Vcc.

6

4
Vcc (Volts)

FACT
ALS
LS
HC

Figure 2-1 illustrates the effects of Icc versus power
supply voltage (Vcc) for two load capacitance
values: 50 pF and stray capacitance. The clock
frequency was 1 MHz for the measurements.

= 1.25/1.25 V
= 0.410.7 V

= 0.3/0.7 V @ 4.75 V Vcc
= 0.8/1.25 V

Output Characteristics
All FACT outputs are buffered to ensure consistent
output voltage and current specifications across
the family. Both 'AC and 'ACT device types have the
same output structures. Two clamp diodes are
internally connected to the output pin to suppress
voltage overshoot and undershoot in noisy system
applications which can result from impedance
mismatching. The balanced output design allows
for controlled edge rates and equal rise and fall
times.

AC Performance
In comparison to LS, ALS and HC families, FACT
devices have faster internal gate delays as well as
the basic gate delays. Additionally, as the level of
integration increases, FACT logic leads the way to
very high·speed systems.
The example below describes typical values for a
74XX138, 3-to-8 line decoder.
FACT
ALS
LS
HC

=

6.0 ns @ CL
CL
CL
CL

= 12.0 ns @
= 22.0 ns @
= 17.5 ns @

= 50 pF

All devices (,AC or 'ACT) are guaranteed to source
and sink 24 rnA. Commercial devices, 74AC/ACTXXX,
are capable of driving 50 ohm transmission lines,
while military grade devices, 54AC/ACTXXX, can
drive 75 ohm transmission lines.

= 50 pF
= 15 pF
= 50 pF

AC performance specifications are guaranteed at
5.0 V ± 0.5 V and 3.3 V ± 0.3 V. For worst case
design at 2.0 V Vcc on all device types, the formula
below can be used to determine AC performance.
AC performance at 2.0 V Vcc
specification at 3.3 V.

= 1.9

IOL/loH Characteristics
FACT
ALS
LS
HC

x AC

2-4

= 241-24 rnA
= 24/-15 rnA
= 81-0.4 rnA @

= 4/-4 rnA

4.75 V Vcc

Dynamic Output Drive

Begin analysis at the VOL (quiescent) point. This is
the intersection of the VOlJlOL curve for the output
and the VINIiIN curve for the input. For CMOS inputs
and outputs, this pOint will be approximately
100 mY. Then draw a 50 ohm load line from this
intersection to the VOH/loH curve as shown by Line
1. This intersection is the voltage that the incident
wave will have. Here it occurs at approximately
3.95 V. Then draw a line with a slope of -50 ohms
from this first intersection pOint to the VIN/IIN curve
as shown by Line 2. This second intersection will
be the first reflection back from the input gate.
Continue this process of drawing the load lines
from each intersection to the next. Lines
terminating on the VOHlioH curve should have
positive slopes while lines terminating on the
VIN/IIN curve should have negative slopes.

Traditionally, in order to predict what incident wave
voltages would occur in a system, the designer was
required to do an output analysis using a Bergeron
diagram. Not only is this a long and time
consuming operation, but the designer needed to
depend upon the accuracy and reliability of the
manufacturer-supplied 'typical' output IIV curve.
Additionally, there was no way to guarantee that any
supplied device would meet these 'typical'
performance values across the operating voltage
and temperature limits. Fortunately for the system
designers, Fairchild has taken the necessary steps
to guarantee incident wave switching on
transmission lines with impedances as low as 50
ohms for the commercial temperature range and 75
ohms for the military temperature range.
Figure 2-2 shows a Bergeron diagram for switching
both HIGH-to-LOW and LOW-to-HIGH. On the right
side of the graph (lout> 0), are the VOH and IIH
curves for FACT logic while on the left side
(lout < 0), are the curves for VOL and IlL. Although
we will only discuss here the LOW-to-HIGH
transition, the information presented may be
applied to a HIGH-to-LOW transition.

Each intersection point predicts the voltage of each
reflected wave on the transmission line. Intersection
pOints on the VOHlioH curve will be waves travelling
from the driver to the receiver while intersection
points on the VIN/IIN curve will be waves travelling
from the receiver to the driver.
Figures 2-3a and 2-3b show the resultant
waveforms. Each division on the time scale
represents the propagation delay of the
transmission line.

Figure 2·2: Gate Driving 50 Ohm Line
Reflection Diagram

Figure 2·3a: Resultant Waveforms Driving
50 Ohm Line - Theoretical

VIN/IIN

I----...
I

. . . \ Uoe 2

~/\/

I

"",Slope l=50\i

----

\
\/, '\,,:

~

-1----t====F-:x.-~---=t_---+'-=
~=--1

-2-+---~---+----~--~
-0.2

-0.1

o

01

0.2

Current (A)

- - - RECEIVER

- _.- _._.- DRIVER

-1

-1

Time (1 Propagation Delay/Div)

2-5

•

Figure 2·3b: Resultant Waveforms Driving
50 Ohm Line - Actual

Figure 2·3a: Resultant Waveforms Driving
50 Ohm Line - Actual
VZR 0

- - - RECEIVER

->_.-.-.- DRIVER
VZR 0

-1

_ _ RECEIVER
-.-.-.-.- DRIVER

-1

Time (ns)

Time (ns)

Figure 2·3b: Resultant Waveforms Driving
50 Ohm Line - Theoretical

-

While this exercise can be done for FACT, it is no
longer necessary. FACT is guaranteed to drive an
incident wave of enough voltage to switch another
FACT input.

_ _ RECEIVER

_._._._.- DRIVER

We can calculate what current is required by looking
at the Bergeron diagram. The quiescent voltage on
the line will be within 100 mV of either rail. We know
what voltage is required to guarantee a valid voltage
at the receiver. This is either 70% or 30% of Vce.
The formula for calculating the current and voltage
required is I (VOQ - VI)/ZO I at VI. For VOQ = 100 mV,
VIH = 3.85 V, Vee = 5.5 V and Zo = 50 ohms, the
required 10H at 3.85 V is 75 rnA. For the HIGH-toLOW transition, VOQ = 5.4 V, VIL = 1.35 V and Zo =
50 ohms, 10L is 75 rnA at 1.65 V. FACT's I/O
specifications include these limits. For
transmission lines with impedances greater than 50
ohms, the current requirements are less and
switching is still guaranteed.

-1

Time (1 Propagation Delay/Div)

2·6

Figure 2·6: Input Characteristics VIN/IIN

It is important to note that the typical 24 rnA drive
specification is not adequate to guarantee incident
wave switching. The only way to guarantee this is to
guarantee the current required to switch a
transmission line from the output quiescent point to
the valid VIN level.

Vcc = 5.0 V, TA =25°C
VIN/IIN

7
6
5
~ 4
Q) 3
Cl
~ 2

The following performance charts are provided in
order to aid the designer in determining dynamic
output current drive of FACT devices with various
power supply voltages.

0

>
Figure 2·4: Output Characteristics VOH/loH,
'ACOO

0
-1
-2
-0.2

-0.1
o
Current (rnA)

0.1

VCC=5.5V

>4

~V~~
Vee =4.54

ell

Choice of Voltage Specifications

~-....... ~

Q) 3
Cl
....

~

..........

2

"0

>,

'"

To obtain better performance and higher density,
semiconductor technologies are reducing the
vertical and horizontal dimensions of integrated
device structures. Due to a number of electrical
limitations in the manufacture of VLSI devices and
the need for low voltage operation in memory cards,
it was decided by the JEDEC committee to
establish interface standards for devices operating
at 3.3 V ± 0.3 V. To this end, Fairchild Digital
guarantees all of its devices operational at 3.3 V ±
0.3 V. Note also that AC and DC specifications are
guaranteed between 3.0 and 5.5 V. Operation of
FACT logic is also guaranteed from 2.0 to 6.0 V on
Vcc.

"\ \" \

\ \ \

-1

-2
-50

-100

-150

-200 rnA

Current (rnA)

Figure 2·5: Output Characteristics VoLlloL,
'ACOO

Operating Voltage Ranges
FACT
ALS
LS
HC

Vee 5.5V

Vee s.ov
VCC=4.5V

4

\

3

\

150

Q)
Cl

2~
o

~ 1::--....'-..

1

200 rnA

~

G

100

50

>

-2

Current (rnA)

2·7

=
=
=
=

2.0
5.0
5.0
2.0

to
V
V
to

6.0 V
± 10%

± 5%
6.0 V

•

0.2

Figure 2·7: Internal Gate Delays

FACT Replaces LS, ALS, HCMOS

10

Fairchild's Advanced CMOS family is specifically
designed to outperform the LS, ALS and HCMOS
families. Figure 2-7 shows the relative position of
various logic families in speed/power performance.
FACT exhibits 1 ns internal propagation delays while
consuming 1 p,W of power.

SPEED VS. POWER

gs
~

Q)
Cl

-HC

The Logic Family Comparisons table below
summarizes the key performance specifications for
various competitive technology logic families.

~6

<1l
(!J

"iii
c::

~4

-ALS

c::

2

-FAST
_FAST
LSI

- FACT
0.001

3.0

1.0

0.3

10.0

Power Per Gate (mW)
(Not to scale)

Figure 2·8: Logic Family Comparisons
General Characteristics (All Max Ratings)
Characteristics
Operating Voltage
Range
Operating
Temperature Range
Input Voltage (limits)

Output Voltage
(limits)
Input Current

Output Current
at Vo (limit)
DC Noise Margin
LOW/HIGH

Symbol

LS

ALS

HCMOS

VCCfEEfDD

5±5%

5±10%

2.0 to 6.0

FACT
'AC

'ACT

2.0 to 6.0

2.0 to 6.0

TA 74 Series
o to + 70
o to +70 -40 to +85 -40 to +85 -40 to +85
TA 54 Series -55 to +125 -55 to +125 -55 to +125 -55 to +125 -55 to +125

Unit
V

°C

VIH (min)

2.0

2.0

3.15

3.15

2.0

V

VIL (max)

0.8

0.8

0.9

1.35

0.8

V

VOH (min)

2.7

2.7

VOL (max)

0.5

0.5

0.1

0.1

0.1

V

hH

20

20

+ 1.0

+ 1.0

+ 1.0

p,A

IlL

-400

-200

-1.0

-1.0

-1.0

p,A

10H

-0.4

-0.4

-4.0@Vcc-O.B

-24@Vcc-O.B

-24@Vcc-O.B

mA

10L

8.0

8.0

4.0 @0.4 V

24 @0.4V

24 @ 0.4 V

mA

1.25/1.25

0.7/2.4

V

DCM

0.3/0.7

0.4/0.7

Vcc-0.1

0.8/1.25

Note: All DC parameters are specified over the commercial temperature range.

2-B

Vcc-0.1

Vcc-0.1

V

Figure 2·8: Logic Family Comparisons, cont'd.
Speed/Power Characteristics (All Typical Ratings)
Symbol

LS

ALS

HCMOS

FACT

Unit

Quiescent Supply Current/Gate

IG

0.4

0.2

0.0005

0.0005

rnA

Power/Gate (Quiescent)

PG

2.0

1.2

0.0025

0.0025

rnW

Propagation Delay

tp

7.0

5.0

8.0

5.0

ns

Speed Power Product

-

14

6.0

0.02

0.01

pJ

Clock Frequency D/FF

fmax

33

50

50

160

MHz

ALS

HCMOS

FACT

Unit

Characteristics

Propagation Delay (Commercial Temperature Range)
Product

74XXOO

tPLH/tPHL

tPLH/tPHL

74XX74

(Clock to Q)
tPLH/tPHL

74XX163

(Clock to Q)

=

=
=

LS

Typ

10.0

5.0

8.0

5.0

ns

Max

15.0

11.0

23.0

8.5

ns

Typ

25.0

12.0

23.0

8.0

ns

Max

40.0

18.0

44.0

10.5

ns

Typ

18.0

10.0

20.0

5.0

ns

Max

27.0

17.0

52.0

10.0

ns

Conditions: (LS) Vee 5.0 V, CL 15 pF, 25°C;
(ALS/HC/FACT) Vee 5.0 V ± 10%, CL
-40 to + 85°C for HC/FACT.

=50 pF, Typ values at 25°C, Max values at 0 to 70°C for ALS,

2·9

•

Circuit Characteristics
Cpo values for CMOS devices are calculated by
measuring the power consumption of a device at
two different frequencies. Cpo is calculated in the
following manner:
1. The power supply voltage is set to Vcc =
5.5VDC.
2. Signal inputs are set up so that as many
outputs as possible are switching, giving a
worst·case situation per JEDEC Cpo
conditions (see Section 3).
3. The power supply current is measured and
recorded at input frequencies of 200 kHz and
1 MHz.
4. The power dissipation capacitance is
calculated by solving the two simultaneous
equations
P1 = (Cpo • Vcc' • f1) + (Icc • Vcc)
P2 = (Cpo • Vcc' • f2) + (Icc • Vcc)
giving
Cpo =(P1-P2)/Vcc'(h-f2)
or
Cpo = (11-12)/vcc(h-f2)
where
11 = supply current at h =200 kHz.
12 = supply current at f2 = 1 MHz.

Power Dissipation
One advantage to using CMOS logic is its extremely
low power consumption. During quiescent
conditions, FACT will consume several orders of
magnitude less current than its bipolar
counterparts. But DC power consumption is not the
whole picture. Any circuit will have AC power
consumption, whether it is built with CMOS or
bipolar technologies.

Power consumption of a circuit can be calculated
using the formula:
PD = [(CL + Cpo) - Vcc - Vs -f] + [10 - Vcc]
where
PD = power dissipation
CL = load capacitance
Cpo = device power capacitance
Vcc = power supply
Vs
= output voltage swing
f
= frequency of operation
= quiescent current
10

Power consumption for FACT is dependent on the
supply voltage, frequency of operation, internal
capacitance and load. Vs will be Vcc and 10 can be
considered negligible for CMOS. Therefore, the
simplified formula for CMOS is:
PD = (CL + Cpo) Vcc' f

On FACT device data sheets, Cpo is a typical value
and is given either for the package or for the
individual device (i.e., gates, flip-flops, etc.) within
the package.

Figure 2·9: Power Demonstration Circuit Schematic
Vcc

INPUT

'04 LOAD DEVICES

2-10

This graph shows two advantages of FACT circuits
(power and speed). FACT logic delivers increased
performance in addition to offering the power
savings of CMOS.

The circuit shown in Figure 2-9 was used to
compare the power consumption of FACT versus
ALS devices.
Two identical circuits were built on the same board
and driven from the same input. In the circuit, the
input signal was driven into four D-type flip-flops
which act as divide-by-2 frequency dividers. The
outputs from the flip-flops were connected to the
inputs of a '138 decoder. This generated eight nonoverlapping clock pulses on the outputs of the '138,
which were then connected to an '04 inverter. The
input frequency was then varied and the power
consumption was measured. Figure 2-10 illustrates
the results of these measurements.

Refer to Section 3 for test philosophies regarding
power dissipation.

Specification Derivation
At first glance, the specifications for FACT logic
might appear to be widely spread, possibly
indicating wide design margins are required.
However, several effects are reflected in each
specification.
Figures 2-11a through 2-11e illustrate how the data
from the characterization of actual devices is
transformed into the specifications that appear on
the data sheet. This data is taken from the 'AC245.

Figure 2-10: FACT vs. ALS Circuit Power
400,-,--------------------,

Figure 2-11a shows the data taken (from one part) on
a typical, single path, tPHL from An to Bn, over
temperature at 5.0 V; there is negligible variation in
the value of tPHL. The next graph, Figure 2-11b,
depicts data taken on the same device; this set of
curves represents the data on all paths A to Band B
to A. The data on this plot indicates only a small
variation for tPHL.

350
300

~

.s

250

~

200

Q;

~

FACT

150
100

~

AlS Circuit

\ ALS
\
I

Stopped
Functioning

The graphs in Figures 2-11a and 2-11b include data at
5.0 V; Figure 2-11c shows the variation of delay times
over the standard 5.0 ± 0.5 V voltage range. Note
there is only a ± 6% variation in delay time due to
voltage effects.

,______ ---------------

50
0
0

20

40

60

80

100

Frequency (MHz)

Below 40 MHz, the FACT circuit dissipates much
less power than the ALS version. It is interesting to
note that when the frequency went to zero, the FACT
circuit's power consumption also went to zero; the
ALS circuit continued to dissipate almost 100 mW.
Another advantage of FACT is its capabilities above
40 MHz. At this frequency, the first 74ALS74 D-type
flip-flop ceased to operate. Once this occurred, the
entire circuit stopped working and the power
consumption fell to its quiescent value. The FACT
device, however, continued functioning beyond the
limit of the frequency generator, which was
100 MHz.

Now refer to Figure 2-11d which illustrates the
process effects on delay time. This graph indicates
that the process effects contribute to the spread in
specifications more than any other factor in that the
effects of the theoretical process spread can
increase or decrease specification times by 30%.
Because this 30% spread represents considerably
more than ± 3 standard deviations, this guarantees
an increase in the manufacturability and the quality
level of FACT product. To further ensure parts within
specification will pass on testers at the limits of
calibration, tester guardbands are incorporated.
With voltage and process effects added (Figure
2-11e), the full range of the specification can be
seen. For reference, the data sheet values are shown
on the graph.

2·11

•

Figure 2·11c: Voltage Effects on Delay Times

This linear behavior with temperature and voltage
is typical of CMOS. Although the graphs are drawn
for a specific device, other part types have very
similar graphical representations. Therefore, for
performance-critical applications, where not all
variables need to be taken into account at once,
the user can narrow the specifications. For example, all parts in a critically timed subcircuit are
together on a board, so it may be assumed the
devices are at the same supply and temperature.

1.1
1.08
1.06
1.04
1.02
1

0.98
0.96

Figure 2-11a: tPHL, An to Bn, Single Path

0.94
8

Vcc=5.0 V

0.92

7

+-------+---------1

0.9

5.5

6

5.0
Volts

4.5

5
4
3

2Figure 2·11d: FACT Process Effects on Delay
Times

o+--+--+--+--+-~--~~--~~

-60 -40 -20

0

20

40

60

80 100 120

1.4

Temperature (0C)

1.3

Figure 2·11b: tPHL, A to B, All Paths

1.2
1.1

8

Vcc=5.0 V

7
6

0.9

5

0.8

4

Maximum

0.7

3

2

0.6

Typical

Min

Minimum

Typ
Process Window

0+-~--+--4--4__4--~~--~~

-60 -40 -20

0

20

40

60

80 100 120

Temperature (0C)

2-12

Max

Capacitive Loading Effects

Figure 2·11e: tPHL, A to B, with Voltage
and Process Variation

en
.s

8

7
~ 6
Q)
Cl
5
c
.2 4

Commercial

Maximum

....

Military
Room temp

I:'""

Voltage (V)

~

3

a.

2

a.

- Commercial
Minimum
0+-~--~~--~--~~--+--+--1

Parameter

ttl

e

In addition to temperature and power supply effects,
capacitive loading effects for loads greater than
50 pF should be taken into account for propagation
delays of FACT devices. Minimum delay numbers
may be determined from the table below. Propagation delays are measured to the 50% point of the
output waveform.

1

·55 ·35

Units

Typical

Military

·15

5

25

45

65

85 105 125

3.0

4.5

5.5

trise

31

22

19

ps/pF

tfall

18

13

12.5

ps/pF

Temperature (0C)

•

TA=25°C
The two graphs following, Figures 2-12 and 2-13,
describe propagation delays on FACT devices as affected by variations in power supply voltage (Vce)
and lumped load capacitance (CL). Figures 2-14 and
2-15 show the effects of lumped load capacitance on
rise and fall times for FACT devices.

The same reasoning can be applied to setup and
hold times. Consider the 'AC74. The setup time is
3.0 ns while the hold time is 0 ns. Theoretically, if
these numbers were violated, the device would
malfunction; however, in actuality, the device probably will not malfunction. Looking at the typical
setup and hold times gives a better understanding
of the device operation.

Figure 2·12: Propagation Delay vs. Vee CACOO)
Delay (ns)
32

CL = 1000pF, IpLH

30

At 25°C and 5.0 V, the setup time is 1.5 ns while the
hold time is -1.5 ns. They are the same; a positive
setup time means the control signal to be valid
before the clock edge, a positive hold time indicates
the control signal will be held valid after the clock
edge for the specified time, and a negative hold
time means the control signal can transition before
the clock edge. FACT devices were designed to be
as immune to metastability as possible. This is
reflected in the typical specifications. The true
'critical' time where the input is actually sampled is
extremely short: less than 50 ps.

'--h

28

I
I

26
24

CL = 1000pF, IpHl

22

20

.......
.-.~

--

-::---t-

t:-c--

CL=470pF, tPLH

18

-II

16

14 ~470pF, IPHl12

10

---

.......
r--- ...........

1---

r---

=

220pF, tpHL

I"--

- --

-

i- __ -""---.
--r----- - f-"::::"~ C------_

=-; = 220i)F,TpL;:-:::::-::r-Cl

r-----

- -1----

_.

Cl = 50pF, tpLH

CL - 50pF, t~Hl

-~

-

-:::---

- - f--

'-

-

'-

.-

I
By applying the same reasoning as we did to the
propagation delays to the setup and hold times, it
becomes obvious that the spread from setup to hold
time (3 ns worst-case) really covers devices across
the entire processltemperature/voltage spread. The
real difference between the setup and hold times for
any single device, at a specified temperature and
voltage, is negligible.

3.0

3.5

4.0

4.5
Vee (Volts)

2-13

5.0

5,5

6.0

Figure 2·15:

Figure 2·13: Propagation Delay vs. CL (,ACOO)
Delay (ns)

Jri"L

22

20

!
18

,
16

i

tpLH

v"::'jq/Y ,
tpHL

~

~

!

~:F:::

10

#. 

36.8%+-1--+--+--

----4.

• Transient Dose/Latchup
Methods 1020, 1021 per MIL-STD-883
Minimum transient upset threshold
specification
Minimum latchup threshold specification
Device burnout specification
Gamma rays

10%

----"'E~
TIME

Radiation Tolerance
Semiconductors subjected to radiation
environments undergo degradation in operating life
as their exposure to radiation increases. As
technology advances, so does the demand for
radiation·tolerant devices. Fairchild is meeting this
challenge by developing the FACT family into a
comprehensive radiation tolerant product for
present and future rad-hard needs. Such
applications include:
• Space
Satellites
Space Stations

• Neutron
Test not required for CMOS product
• Single Event Upset
To be announced in the future
Alpha Particle Radiation

Summary of Testing
To demonstrate and verify FACT's performance in
radiation environments, we have tested several of
our standard device types to total dose, transient
dose and latch-up parameters. Standard
manufacturing techniques were used in the
production of all circuits. Devices of the same type
were manufactured from the same wafer.

• Airborne and Military
Fighters/Bombers
Missile Systems
Ground Based Systems
Navigation & Communications

Test results, although limited to a small one-time
sampling of the FACT product line, offer an
indication of how various radiation environments
affect specific standard FACT product. In most
instances the standard FACT devices that were
exposed to varying levels of total dose radiation
showed reduced power consumption over
functionally similar FAST and Schottky device types
in non-radiation environments. Figure 2-19 shows a
typical comparison of a FACT device's (54AC241)
power consumption at various dose rates compared
with functionally similar FAST (54F241) and Schottky
(54S241) as tested in a non-radiation environment.

• Commercial
Power Stations
Medical
Food and Bacterial Control
Radiation tolerant semiconductors increase the
useful life of the product in which it is incorporated.
Additionally, radiation tolerant devices reduce
shielding requirements and improve stabilization of
parametric, performance, resulting in cost
reductions for shielding and weight, reduce power
consumption and size.

2-16

Figure 2·19: Total Dose Response (54AC241)
200
190
180
170
160
150
140
130
;f: 120
~
co 110
en 100
0
S2 90
80
70
60
50
40
30
2
10
0

Transient dose testing evaluated how these devices
would respond to quick bursts of radiation energies.
Results were varied due to biasing and input
conditions. Devices were generally free of transient
upset and/or latch·up up to the range of 3x10· to
4.4x10· rads(Si)/second.

x 7KRAD/SEC
o 3.3 KRAD/SEC

o

0.6 KRAD/SEC
'S241 NO EXPOSURE
+ 'F241 NO EXPOSURE

L>

All devices were also taken to 5x10'· rads(Si)/
second to determine if burnout would occur. There
was no burnout at this level.

~----~----~----6----6

FACT is Radiation Tolerant
FACT logic employs the use of thin gate oxides,
oxidation cycles, and annealing steps that enhance
the tolerance of the standard FACT product line.
We are conducting additional testing and are
evaluating further design enhancements for
increased radiation tolerance levels of our FACT
devices. Our current goal is a radiation tolerant
FACT product line which exceeds the U.S.
Government's VHSIC Phase II radiation
requirements. At that time, Fairchild radiation tested
products will be guaranteed at various total dose
tolerance levels ranging between 50 Krads(Si) and
1 Mrad(Si).

+----+----+----+----+

50

100

500

1000

For total dose testing, all devices were subjected up
to a 1 Mrad(Si) limit. There were no functional
failures. Yet, based on the testing, parametric
changes did occur.

2-17

•

Product Index and Selection Guide

FACT Descriptions and Family Characteristics

Ratings, Specifications and Waveforms

I Design Considerations

r

Data Sheets

Package Outlines and Ordering Information

FGC Series Advanced 2-Micron CMOS Gate Array

I FAIRCAD™ Semicustom Design System
CMOS Arrays Packaging Guide

Field Sales Offices and Distributor Locations

Ratings, Specifications
and Waveforms

F=AIRCHILC

Specifying FACT Devices
Traditionally, when a semiconductor manufacturer
completed a new device for introduction,
specifications were based on the characterization
of just a few parts. While these specifications were
appealing to the designer, they were often too tight
and, over time, the IC manufacturers had difficulty
producing devices to the original specs. This
forced the manufacturer to relax circuit
specifications to reflect the actual performance of
the device.

test setup for each type of device. This allows a
device to be exercised in a consistent manner for
the purpose of specification comparison. All device
measurements are made with Vce = 5.0 V at 25°C,
with 3-state outputs both enabled and disabled.

As a result, designers were required to review
system designs to ensure the system would remain
reliable with the new specifications. Fairchild
realized and understood, the problems associated
with characterizing devices too aggressively.
To provide more realistic and manufacturable
specs, Fairchild devised a systematic and thorough
process to generate specifications. Devices are
selected from multiple wafer lots to ensure process
variations are taken into account. In addition, the
process parameters are measured and compared to
the known process limits. With more than two
years of experience manufacturing FACT logic,
Fairchild can accurately predict how these wafer
lots compare with the best and worse case lots
that can possibly be expected.
This method of characterizing parts more
accurately represents the product across time,
voltage, temperature and process rather than
portraying the fastest possible device. FACT
circuits are therefore guaranteed to be
manufacturable over time without the need to
respecify timing.
These specification guidelines allow designers to
design systems more efficiently since the devices
used will behave as documented. Unspecified
guard bands no longer need to be added by the
designer to ensure system reliability.

Power Dissipation -

Gates:

Switch one input. Bias the
remaining inputs such that the
output switches.

Latches:

Switch the Enable and D inputs
such that the latch toggles.

Flip-Flops:

Switch the clock pin while
changing D (or bias J and K)
such that the output(s) change
each clock cycle. For parts with
a common clock, exercise only
one flip-flop.

Decoders:

Switch one address pin which
changes two outputs.

Multiplexers:

Switch one address pin with
the corresponding data inputs
at opposite logic levels so that
the output switches.

Counters:

Switch the clock pin with other
inputs biased such that the
device counts.

Shift Registers:

Switch the clock pin with other
inputs biased such that the
device counts.

Transceivers:

Switch one data input. For
bidirectional devices enable
only one direction.

Parity Generator:

Switch one input.

Priority Encoders:

Switch the lowest priority input.

Test Philosophy

In an effort to reduce confusion about measuring
CPD, a JEDEC standard test procedure (7A
Appendix E) has been adopted which specifies the

Load Capacitance: Each output which is switching
should be loaded with the
standard 50 pF. The equivalent

3-3

If the device is tested at a high enough frequency,
the static supply current can be Ignored. Thus at
1 MHz, the following formula can be used to
calculate Cpo:
Cpo = lee/(Vee) (1 x 10") - Equivalent Load
Capacitance

Ratings and Specifications
Figure 3·1: Absolute Maximum Ratings!
Parameter

LimIts

Units

-0.5 to 7.0

V

VI=-0.5
VI=Vee+0.5

-20
20
-0.5 to Vee + 0.5

rnA
rnA
V

Vo=-0.5
Vo=Vee+0.5

Vo

-20
20
-0.5 to Vee + 0.5

rnA
rnA
V

10

±50

rnA

Icc or IGNO

±50

rnA

TSTG

-65 to 150

°C

Symbol

Supply Voltage

Conditions

Vee

DC Input Diode Current
or
DC Input Voltage

11K

DC Output Diode Current
or
DC Output Voltage

10K

VI

DC Output Source or Sink Current
DC Vcc or Ground Current Per Output Pin
Storage Temperature

'Absolute maximum ratings are those values beyond which damage to the device may occur. Obviously the databook
specifications should be met, without exception, to ensure that the system design is reliable over its power supply,
temperature, output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook
specifications.

Figure 3·2: Recommended Operating Conditions
Limits

Units

Vee

2.0 to 6.0

V

Input Voltage

VI

V

Output Voltage

Vo

o to Vee
o to Vee

Parameter

Symbol

Supply Voltage
(unless otherwise specified)

Operating Temperature
Junction Temperature

CondItions

V

74AC/ACT
54AC/ACT

TA

-40 to +85
-55 to + 125

°C
°C

CDIP
PDIP

TJ

175
140

°C

Input Rise and Fall Time' (typical)
(except Schmitt inputs)
'AC devices
VIN from 30% to 70% of Vee

tr, tl

Vee@ 3.0 V
Vee @ 4.5 V
Vee @ 5.5 V

150
40
25

nsN
nsN
nsN

Input Rise and Fall Time' (typical)
(except Schmitt inputs)
'ACT devices
VIN from 0.8 to 2.0 V, Vmeas
from 0.8 to 2.0 V

tr, tl

Vee @ 4.5 V
Vee@ 5.5 V

10
8

nsN
nsN

'See Individual data sheets for those devices which differ from the typical Input rise and fall times noted here.

3-4

DC Characteristics for 'AC Family Devices
74AC
Symbol

Parameter

54AC

Conditions

Vee
(V)

VouT=0.1 V
or Vee-0.1 V

3.0
4.5
5.5
3.0
4.5
5.5

1.5
2.25
2.75
1.5
2.25
2.75

2.1
3.15
3.85
0.9
1.35
1.65

2.1
3.15
3.85
0.9
1.35
1.65

2.1
3.15
3.85

V

0.9
1.35
1.65

V

3.0
4.5
5.5

2.99
4.49
5.49

2.9
4.4
5.4

2.9
4.4
5.4

2.9
4.4
5.4

V

2.56
3.86
4.86

2.4
3.7
4.7

2.46
3.76
4.76

V

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

3.0
4.5
5.5

0.32
0.32
0.32

0.4
0.4
0.4

0.37
0.37
0.37

V

5.5

±0.1

± 1.0

±1.0

p.A

VI (OE) = VIL, VIH
VI = Vee, VGND 5.5
Vo=Vee, GND

±0.5

± 10.0

±5.0

p.A

TA=25°C
Typ

VIH

VIL

Minimum
High Level
Input Voltage
Maximum
Low Level
Input Voltage

VouT=0.1 V
or Vee-0.1 V

louT = -50 p.A
VOH

Minimum
High Level
Output Voltage ·VIN = VIL or VIH
-12 mA
10H
-24 mA
-24 mA
lOUT = 50 p.A

VOL

Maximum
Low Level
Output Voltage ·VIN = VIL or VIH
12 mA
10L
24 mA
24 mA

liN

Maximum
Input Leakage
Current

IOZ

Maximum
3·State
Current

IOLD
10HD

tMinimum
Dynamic
Output Current

74AC

VI = Vee, GND

3.0
4.5
5.5
3.0
4.5
5.5

0.002
0.001
0.001

TA=
TA=
-55° to +125°C -40° to +85°C
Guaranteed Limits

Units

VOLD=1.1 V

5.5

57

86

mA

VOHD = 3.85 V

5.5

-50

-75

mA

• All outputs loaded; thresholds on Input associated with output under test.
tMaximum test duration 20 ms, one output loaded at a time.

3·5

•

DC Characteristics for 'ACT Family Devices
74ACT
Symbol

Parameter

Conditions

Vcc
(V)

54ACT

TA=25°C
Typ

74ACT

TA=
TA=
-55° to + 125°C -40° to + 85°C
Guaranteed Limits

Units

VIH

Minimum
High Level
Input Voltage

VouT=0.1 V
or Vee-0.1 V

4.5
5.5

1.5
1.5

2.0
2.0

2.0
2.0

2.0
2.0

V

VIL

Maximum
Low Level
Input Voltage

VouT=0.1 V
or Vee-0.1 V

4.5
5.5

1.5
1.5

0.8
0.8

0.8
0.8

0.8
0.8

V

lOUT = -50 p.A

4.5
5.5

4.49
5.49

4.4
5.4

4.4
5.4

4.4
5.4

V

4.5
5.5

0.0001

3.86
4.86

3.70
4.70

3.76
4.76

V

4.5
5.5

0.001
0.001

0.1
0.1

0.1
0.1

0.1
0.1

V

4.5
5.5

0.32
0.32

0.40
0.40

0.37
0.37

V

VOH

Minimum
High Level

*VIN = VIL or VIH
IOH
-24 mA
-24 mA
lOUT = 50 p.A

VOL

liN

Maximum
*VIN = VIL or VIH
Low Level
24 mA
Output Voltage IOL
24 mA
Maximum
Input

VI = Vee, GND

5.5

±0.1

± 1.0

± 1.0

p.A

loz

Maximum
3-State
Current

VI=VIL, VIH
Vo = Vee, GND

5.5

±0.5

± 10.0

±5.0

p.A

leeT

Maximum
leellnput

VI = Vee-2.1 V

5.5

1.6

1.5

mA

VOLD=1.1 V

5.5

57

86

mA

VOHD = 3.85 V

5.5

-50

-75

mA

IOLD
IOHD

tMinimum
Dynamic
Output Current

0.6

• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 2.0 ms, one output loaded at a time.

Figure 3-3: AC Loading Circuit
-OPEN

TEST LOAD

2xVcc

tr=3.0 ns
tf=3.0 ns
500 Scope

3·6

tPZH
tPHZ
tPZL
tPLZ

AC Loading and Waveforms
Loading Circuit

Figure 3-3 shows the AC loading circuit used in
characterizing and specifying propagation delays of
all FACT devices (,AC and 'ACT) unless otherwise
specified in the data sheet of a specific device.

The 500 ohm resistor to ground can be a high
frequency passive probe for a sampling
oscilloscope, which costs much less than the
equivalent high impedance probe. Alternately, the
500 ohm resistor to ground can simply be a 450
ohm resistor feeding into a 50 ohm coaxial cable
leading to a sampling scope input connector, with
the internal 50 ohm termination of the scope
completing the path to ground. This is the
preferred scheme for correlation. (See Figure 3-3.)
With this scheme there should be a matching
cable from the device input pin to the other input
of the sampling scope; this also serves as a 50
ohm termination for the pulse generator that
supplies the input signal.

The use of this load, which is equivalent to the
FAST (Fairchild Advanced Schottky TTL) test jig,
differs somewhat from previous (HCMOS) practice,
provides more meaningful information and
minimizes problems of instrumentation and
customer correlation. In the past, + 25°C
propagation delays for TTL devices were specified
with a load of 15 pF to ground; this required great
care in building test jigs to minimize stray
capacitance and implied the use of high
impedance, high frequency scope probes. FAST
circuits changed to 50 pF of capacitance allowing
more leeway in stray capacitance and also loading
the device during rising or falling output
transitions. This more closely resembles the inloading to be expected in average applications and
thus gives the designer more useful delay figures.
We have incorporated this scheme into the FACT
product line. The net effect of the change in AC
load is to increase the average observed
propagation delay by about 1 ns.

Shown in figure 3-3 is a second 500 ohm resistor
from the device output to a switch. For most
measurements this switch is open; it is closed for
measuring one set of the EnablelDisable
parameters (LOW-to-OFF and OFF-to-LOW) of a
3-state output. With the switch closed, the pair of
500 ohm resistors and the 2 x Vee supply voltage
establish a quiescent HIGH level.

Figure 3·4a: Test Input Signal Levels
'ACxx Devices
Vcc
Vcc-O.1V

70% Vcc

30% Vce
0.1 V
OV
AC Test
Input Levels

DC LOW
Input Range

LOW Level
Noise
Immunity

3·7

DC HIGH
Input Range

HIGH Level
Noise
Immunity

Transition
Region

II

Figure 3·4b: Test Input Signal Levels
'ACTxx Devices
Vcc
Vcc-O.1V

3.0 V
2.0 V

0.8 V

0.1 V
OV
AC Test
Input Levels

DC LOW
Input Range

LOW Level
Noise
Immunity

Test Conditions

DC HIGH
Input Range

HIGH Level
Noise
Immunity

Transition
Region

tests should not induce a switch condition on the
appropriate outputs of the FACT device.

Figures 3·4a and 3·4b describe the input signal
voltage levels to be used when testing FACT
circuits. The AC test conditions follow industry
convention requiring VIN to range from 0 V for a
logic LOW to 3.0 V for a logic HIGH for 'ACT
devices and 0 V to Vcc for 'AC devices. The DC
parameters are normally tested with VIN at
guaranteed input levels, that is VIH to VIL (see data
tables for details). Care must be taken to
adequately decouple these high performance parts
and to protect the test signals from electrical noise.
In an electrically noisy environment, (e.g., a tester
and handler not specifically designed for high
speed work), DC input levels may need to be
adjusted to increase the noise margin to allow for
the extra noise in the tester which would not be
seen in a system.

Good high frequency wiring practices should be
used in constructing test jigs. Leads on the load
capaCitor should be as short as possible to
minimize ripples on the output waveform
transitions and to minimize undershoot. Generous
ground metal (preferably a ground plane) should be
used for the same reasons. A Vcc bypass capacitor
should be provided at the test socket, also with
minimum lead lengths.

Rise and Fall Times
Input signals should have rise and fall times of
3.0 ns and signal swing of 0 V to 3.0 V Vcc for 'ACT
devices or 0 V to Vcc for 'AC devices. Rise and fall
times less than or equal to 1 ns should be used for
testing fmax or pulse widths.

Noise immunity testing is performed by raising VIN
to the nominal supply voltage of 5.0 V then
dropping to a level corresponding to VIH
characteristics, and then raising again to the 5.0 V
level. Noise tests can also be performed on the VIL
characteristics by raising VIN from 0 V to VIL, then
returning to 0 V. Both VIH and VIL noise immunity

CMOS devices, including 4000 Series CMOS, HC,
HCT and FACT families, tend to oscillate when the
input rise and fall times become lengthy. As a
direct result of its increased performance, FACT
devices can be more sensitive to slow input rise
and fall times than other lower performance
technologies.

3·8

It is important to understand why this oscillation
occurs. Consider the outputs, where the problem is
initiated. Usually, CMOS outputs drive capacitive
loads with low DC leakage. When the output
changes from a HIGH level to a LOW level, or from
a LOW level to a HIGH level, this capacitance has
to be charged or discharged. With the present high
performance technologies, this charging or
discharging takes place in a very short time,
typically 2·3 ns. The requirement to charge or
discharge the capacitive loads quickly creates a
condition where the instantaneous current change
through the output structure is quite high. A
voltage is generated across the Vee or ground
leads inside the package due to the inductance of
these leads. The internal ground of the chip will
change in reference to the outside world because
of this induced voltage.

so that it re-crosses the input level. If the gain of
the device is sufficient and the input rise or fall
time is slow enough, then the device may go into
oscillation. As device propagation delays become
shorter, the inputs will have less time to rise or fall
through the threshold region. As device gains
increase, the outputs will swing more, creating
more induced voltage. Instantaneous current
change will be greater as outputs become quicker,
generating more induced voltage.

Consider the input. If the internal ground changes,
the input voltage level appears to change to the
DUT. If the input rise time is slow enough, its level
might still be in the device threshold region, or
very close to it, when the output switches. If the
internally-induced voltage is large enough, it is
possible to shift the threshold region enough

Package-related causes of output oscillation are
not entirely to blame for problems with input rise
and fall time measurements. All testers have Vec
and ground leads with a finite inductance. This
inductance needs to be added to the inductance in
the package to determine the overall voltage which
will be induced when the outputs change. As the
reference for the input Signals moves further away
from the pin under test, the test will be more
susceptible to problems caused by the inductance
of the leads and stray noise. Any noise on the
input signal will also cause problems. With FACT
logic having gains as high as 100, it merely takes a
50 mV change in the input to generate a full 5 V
swing on the output.

Figure 3-5: Waveform for Inverting and
Non-Inverting Functions

Figure 3-6: Propagation Delay, Pulse Width
and trec Waveforms

CONTROL
IN

CLOCK

OUTPUT

'Vmi=50% Vcc for 'AC devices; 1.5 V for 'ACT devices
Vmo = 50% for 'ACI'ACT devices

3-9

Vm

I

Figure 3·7: 3·State Output High Enable
and Disable Times

r:fJi'--_J

Propagation Delays, fmax, Set and Hold Times
A 1.0 MHz square wave is recommended for most
propagation delay tests. The repetition rate must
necessarily be increased for testing fmax. A 50%
duty cycle should always be used when testing
fmax. Two pulse generators are usually required for
testing such parameters as setup time, hold time,
recovery time, etc.

Vmo

Enable and Disable Times
Figures 3·7 and 3·8 show that the disable times are
measured at the point where the output voltage
has risen or fallen by 10% from the voltage rail
level (i.e., ground for tpLZ or Vcc for tPHZ). This
change enhances the repeatability of
measurements, reduces test times, and gives the
system designer more realistic delay times to use
in calculating minimum cycle times. Since the high
impedance state rising or falling waveform is RC·
controlled, the first 10% of change is more linear
and is less susceptible to external influences.
More importantly, perhaps from the system
designer's point of view, a change in voltage of
10% is adequate to ensure that a device output
has turned OFF. Measuring to a larger change in
voltage merely exaggerates the apparent Disable
time and thus penalizes system performance since
the designer must use the Enable and Disable
times to devise worst case timing signals to
ensure that the output of one device is disabled
before that of another device is enabled.

Figure 3·8: 3·State Output Low Enable
and Disable Times

OUTPUT
CONTROL

Vmi

IPZL
DATA
OUT

Vmo

, __I}....._ _ _.2~== 10% Vee
"

---Gnd

Figure 3·9: Setup Time, Hold Time
and Recovery Time

DATA
IN

~
-------,

~

Is

Electrostatic Discharge
Precautions should be taken to prevent damage to
devices by electrostatic discharge. Static charge
tends to accumulate on insulated surfaces such as
synthetic fabrics or carpeting, plastic sheets, trays,
foam, tubes or bags, and on ungrounded electrical
tools or appliances. The problem is much worse in
a dry atmosphere. In general, it is recommended
that individuals take the precaution of touching a
known ground before handling devices. To
effectively avoid electrostatic damage to FACT
devices, it is recommended that individuals wear a
grounded wrist strap when handling devices. More
often, handling equipment, which is not properly
grounded, causes damage to parts. Ensure that all
plastic parts of the tester, which are near the
device, are conductive and connected to ground.

t~mi

I

Ih

----------------~

CONTROL
~/ Vmi
INPUT ____~----------~/\'--------

MR =fjlS_trec-:-

OR
CLEAR

Vmi

'Vmi=50% Vcc for 'AC devices; 1.5 V for 'ACT devices
Vmo = 50% Vcc for' ACt' ACT devices

3-10

Product Index and Selection Guide

FACT Descriptions and Family Characteristics

Ratings, Specifications and Waveforms

Design Considerations

Data Sheets

Package Outlines and Ordering Information

FGC Series Advanced 2-Micron CMOS Gate Array

FAIRCAD™ Semicustom Design System

CMOS Arrays Packaging Guide

Field Sales Offices and Distributor Locations

Design Considerations

I=AIRCHILD

Today's system designer is faced with the problem
of keeping ahead when addressing system
performance and reliability. Fairchild's Advanced
CMOS helps designers achieve these goals.

• Board Layout - Prudent board layout will ensure
that most noise effects are minimized.
• Power Supplies and Decoupling - Maximize
ground and Vee traces to keep Vee/ground
impedance as low as possible; full groundlVce
planes are best. Decouple any device driving a
transmission line; otherwise add one capacitor
for every package.

FACT (Fairchild Advanced CMOS Technology) logic
was designed to alleviate many of the drawbacks
that are common to current technology logic
circuits. FACT logic combines the low static power
consumption and the high noise margins of CMOS
with a high fan-out, low input loading and a 50 ohm
transmission line drive capability (comparable to
Fairchild's FAST bipolar technology family) to offer
a complete family of 1.3-micron SSI, MSI and LSI
devices.

Interfacing
FACT devices have outputs which combine
balanced CMOS outputs with high current line
driving capability. Each standard output is
guaranteed to source or sink 24 mA of current at
worst case conditions. This allows FACT circuits to
drive more loads than standard advanced Schottky
parts; FACT can directly drive ALS, AS, LS, HC and
HCT devices.

Performance features such as advanced Schottky
speeds at CMOS power levels, advanced Schottky
drive, excellent noise, ESD and latch-up immunity
are characteristics that designers of state-of-the-art
systems require. FACT logic answers all of these
concerns in one family of products. To fully utilize
the advantages provided by FACT, the system
designer should have an understanding of the
flexibility as well as the trade-offs of CMOS design.
The following section discusses common design
concerns relative to the performance and
requirements of FACT.

Figure 4-1: Interfacing FACT to NMOS, CMOS
and TTL

There are five items of interest which need to be
evaluated when implementing FACT devices in new
designs:
• Interfacing - interboard and technology
interfaces, battery backup and power down or live
insert/extract systems require some special
thought.
• Transmission Line Driving - FACT has line
driving capabilities superior to all CMOS families
and most TTL families.
• Noise effects - As edge rates increase, the
probability of crosstalk and ground bounce
problems increases. The enhanced noise
immunity and high threshold levels improve
FACT's resistance to crosstalk problems.

FACT devices can be directly driven by both NMOS
and CMOS families, as shown in Figure 4-1,
operating at the same rail potential without special
considerations. This is possible due to the low
input loading of FACT product, guaranteed to be
less than 1 p.A per input.
Some older technologies, including all existing TTL
families, will not be able to drive FACT circuits
directly; this is due to inadequate high level
capability, which is guaranteed to 2.4 V. There are
two simple approaches to the TTL-to-FACT interface
problem. A TIL-to-CMOS converter can be

4-3

4

Figure 4·4a: Resistive FACT·to·ECl Translation

constructed employing a resistor pull-up to Vcc of
approximately 4.7k ohms, which is depicted in
Figure 4-2. The correct HIGH level is seen by the
CMOS device while not loading down the TIL
driver.

Figure 4-2:

VIH

+5V

560{J

Pull·Up on TTL Outputs

TTL

510{J
470{J

-5.2V

Figure 4·4b: Single·Ended ECl·to·'AC Circuit

Unfortunately, there will be designs where
including a pull-up resistor will not be acceptable.
In these cases, such as a terminated TTL bus,
Fairchild has designed devices which offer
thresholds that are TIL-compatible (Figure 4-3).
These interfaces tend to be slightly slower than
their CMOS-level counterparts due to an extra
buffer stage required for level conversion.

50V

T1,T2 . 2 N2369
01,02 - HP5082 - 2811

Figure 4·3: TTL Interfacing to 'ACT
Vee

-5.2V

Figure 4·4c: Differential Output ECl·to·'AC
Circuit

ECl devices cannot directly drive FACT devices.
Interfacing FACT-to-ECl can be accomplished by
using TIl-to-ECl translators and 10125 ECl-to-TIl
translators in addition to following the same rules
on the TIL outputs to CMOS inputs (I.e., a resistor
pull-up to Vcc of approximately 4.7k ohms). The
translation can also be accomplished by a resistive
network. A three-resistor interface between FACT
and ECl logic is illustrated in Figure 4-4a. Figures
4-4b and 4-4c show the translation from ECl-toFACT, which is somewhat more complicated. These
two examples offer some possible interfaces
between ECl and FACT logic.

5.0V

D1

D3

620

620

T1 - 2N2369
01,02· HP5082· 2811
03 - IN414 OR IN 4148

~-----------'~- -5.2V

4-4

properties may be exhibited in an example where
devices have edge rates of 3 ns and lines of
8 inches or greater, assuming propagation delays of
1.7 nsfft for an unloaded printed circuit trace.

It should be understood that for FACT, as with
other CMOS technologies, input levels that are
between specified input values will cause both
transistors in the CMOS structure to be
conducting. This will cause a low resistive path
from the supply rail to ground, increasing the
power consumption by several orders of magnitude.
It is important that CMOS inputs are always driven
as close as possible to the rail.

Of the many properties of transmission lines, two
are of major interest to the system designer: Zoe,
the effective equivalent impedance of the line, and
tpde, the effective propagation delay down the line.
It should be noted that the intrinsic values of line
impedance and propagation delay, Zo and tpd, are
geometry-dependent. Once the intrinsic values are
known, the effects of gate loading can be
calculated. The loaded values for Zoe and tpde can
be calculated with:
Zo

Figure 4·5: Crystal Oscillator Circuit
Implemented with FACT 'ACOO

Zoe =
tpde =

-J1+CtfCI
tpd

-J 1+ CtfCI

where CI = intrinsic line capacitance and Ct
additional capacitance due to gate loading.

The formulas indicate that the loading of lines
decreases the effective impedance of the line and
increases the propagation delay. Lines that have a
propagation delay greater than one third the rise
time of the signal driver should be evaluated for
transmission line effects. When performing
transmission line analysis on a bus, only the
longest, most heavily loaded and the shortest, least
loaded lines need to be analyzed. All lines in a bus
should be terminated equally; if one line requires
termination, all lines in the bus should be
terminated. This will ensure similar signals on all
of the lines.

r-----,[J~----~

I

=

I

Line Driving
With the available high-speed logic families,
designers can reach new heights in system
performance. Yet, these faster devices require a
closer look at transmission line effects.

There are several termination schemes which may
be used. Included are series, parallel, AC parallel
and Thevenin terminations. AC parallel and series
terminations are the most useful for low power
applications since they do not consume any DC
power. Parallel and Thevenin terminations
experience high DC power consumption.

Although all circuit conductors have transmission
line properties, these characteristics become
significant when the edge rates of the drivers are
equal to or less than three times the propagation
delay of the line. Significant transmission line

4-5

•

Termination Schemes

The amplitude will be one-half the voltage swing if
Rs (the series resistor) plus the output impedance
(Zs) of the driver is equal to the line impedance.
The second step of the waveform is the reflection
from the end of the line and will have an amplitude
equal to that of the first step. All devices on the
line will receive a valid level only after the wave
has propagated down the line and returned to the
driver. Therefore, all inputs will see the full voltage
swing within two times the delay of the line.

Figure 4·6: Termination Schemes

a: No Termination

Parallel Termination
Parallel terminations are not generally recommended for CMOS circuits due to their power consumption, which can exceed the power consumption of
the logic itself. The power consumption of parallel
terminations is a function of the resistor value and
the duty cycle of the signal. In addition, parallel
termination tends to bias the output levels of the
driver towards either Vcc or ground. While this
feature is not desirable for driving CMOS inputs, it
can be useful for driving TTL inputs.

b: Series Termination

c: Parallel Termination

AC Parallel Termination
AC parallel terminations work well for applications
where the delays caused by series terminations are
unacceptable. The effects of AC parallel terminations are similar to the effects of standard parallel
terminations. The major difference is that the
capacitor blocks any DC current path and helps to
reduce power consumption.

I
T

d: AC Parallel Termination

Thevenin Termination
Thevenin terminations are also not generally
recommended due to their power consumption.
Like parallel termination, a DC path to ground is
created by the terminating resistors. The power
consumption of a Thevenin termination, though,
will generally not be a function of the signal duty
cycle. Thevenin terminations are more applicable
for driving CMOS inputs because they do not bias
the output levels as paralleled terminations do. It
should be noted that lines with Thevenin terminations should not be left floating since this will
cause the input levels to float between Vcc or
ground, increasing power consumption.

e: Thevenin Termination
Series Terminations
Series terminations are most useful in high-speed
applications where most of the loads are at the far
end of the line. Loads that are between the driver
and the end of the line will receive a two-step
waveform. The first wave will be the incident wave.
The amplitude is dependent upon the output impedance of the driver, the value of the series
resistor and the impedance of the line according to
the formula
Vw Vcc-Zoe/(Zoe + Rs + Zs)

FACT circuits have been designed to drive 50 ohm
transmission lines over the full commercial
temperature range and 75 ohm transmission lines
over the military temperature range. This is
guaranteed by the FACT family's specified dynamic

=

4-6

Figure 4·8: Noise Effects

drive capability of 86 mA sink and 75 mA source
current. This ensures incident wave switching on
50 ohm transmission lines and is consistent with
the 3 ns rated edge transition time.
FACT devices also feature balanced output totem
pole structures to allow equal source and sink
current capability. This gives rise to balanced edge
rates and equal rise and fall times. Balanced drive
capability and transition times eliminate both the
need to calculate two different delay times for each
signal path and the requirement to correct signal
polarity for the shortest delay time.

INPUT

Figure 4·7: Input Threshold

However, even the most advanced technology
cannot alone eliminate noise problems. Good
circuit board layout techniques are essential to take
full advantage of the superior performance of FACT
circuits.

Input Thresholds

~

~*:::I!!~O~UTPUT

Noise Effects
FACT offers the best noise immunity of any
competing technology available today. With input
thresholds specified at 30% and 70% of Vec and
outputs that drive to within 100 mV of the rails,
FACT devices offer noise margins approaching 30%
of Vec. At 5 V Vee, FACT's specified input and
output levels give almost 1.5 V of noise margin for
both ground- and Vee-born noise. With realistic
input thresholds closer to 50% of Vce, the actual
margins approach 2.5 V.

FACT product inputs have been created to take full
advantage of high output levels to deliver the
maximum noise immunity to the system designer.
VIH and VIL are specified at 70% and 30% of Vcc
respectively. The corresponding output levels, VOH
and VOL, are specified to be within 0.1 V of the
rails, of which the output is sourcing or sinking 20
jJ.A or less. These noise margins are outlined in
Figure 4·7.

70%....L.

122S1-----1~

~50%

,30%

Well-designed circuit boards also help eliminate
manufacturing and testing problems.
Another recommended practice is to segment the
board into a high-speed area, a medium-speed area
and a low-speed area. The circuit areas with high
current requirements (Le., buffer circuits and highspeed logic) should be as close to the power
supplies as possible; low-speed circuit areas can be
furthest away.

CMOS Bus Loading
CMOS logic devices have clamp diodes from all
inputs and outputs to Vce and ground. While these
diodes increase system reliability by damping out
undershoot and overshoot noise, they can cause
problems if power is lost.

Decoupling capacitors should be adjacent to all
buffer chips; they should be distributed throughout
the logic: one capacitor per chip. Transmission lines
need to be terminated to keep reflections minimal.
To minimize crosstalk, long signal lines should not
be close together.

Figure 4-8 exemplifies the situation when power is
removed. Any input driven above the Vee pin will
forward-bias the clamp diode. Current can then flow
into the device, and out Vee or any output that is
HIGH. Depending upon the system, this current, liN,
can be quite high, and may not allow the bus
voltage to reach a valid HIGH state. One possible
solution to eliminate this problem is to place a
series resistor in the line.

Crosstalk
The problem of crosstalk and how to deal with it is
becoming more important as system performance
and board densities increase. Crosstalk is the
capacitive coupling of signals from one line to

4-7

•

Reverse crosstalk, Figure 4·9b, is caused by the
mutual inductance and capacitance between the
lines which is a transformer action. Reverse
crosstalk increases linearly with distance up to a
critical length. This critical length is the distance
that the signal can travel during its rise or fall time.

another. The amplitude of the noise generated on
the inactive line is directly related to the edge rates
of the signal on the active line, the proximity of the
two lines and the distance that the two lines are
adjacent.
Crosstalk has two basic causes. Forward crosstalk,
Figure 4·9a, is caused by the wavefront propagating
down the printed circuit trace at two different
velocities. This difference in velocities is due to the
difference in the dielectric constants of air (er=1.0)
and epoxy glass (er=4.7). As the wave propagates
down the trace, this difference in velocities will
cause one edge to reach the end before the other.
This delay is the cause of forward crosstalk; it
increases with longer trace length, so consequently
the magnitude of forward crosstalk will increase
with distance.

Although crosstalk cannot be totally eliminated,
there are some design techniques that can reduce
system problems resulting from crosstalk. FACT's
industry·leading noise margins make systems
immune to crosstalk·related problems easier to
design. FACT's AC noise margins, shown in
Figures 4·10a and 4·10b, exemplify the outstanding
immunity to everyday noise which can effect
system reliability.

Figure 4·9b: Reverse Crosstalk on PCB Traces

Figure 4·9a: Forward Crosstalk on PCB Traces

"._._./.-..

r·--·_·/·I

i

I

I

/
_i

~ ~~

I

i \ {

; I I
,. I,
I,

,.

I

I

~

"

\I
___ "'"' .............. _- __... l
~

I;
I.
-'I
i

.,i.......

-1

I

,
.,

,J

i
i

J

i

\

\,
i
\

' . . . . ------__. . -,\ i.

I

"\i

I

\

1'---

;
;

\

0.0 v _.j

;
,1--- ""',

.--.

0",,""",.-,0_._,

0.0

Time (ns) (5.0 ns/div)

i

i

\...,-

v.--=,...·.L_·-

Time (ns) (5.0 nsldiv)

Vertical Scale Horizontal Scale
Key
_._._. Active Driver
50 nslDlv
1.0 VlDiv
••.••.••• Reverse Crosstalk
0.2 VIOl v
5.0 nslDiv
- - Active Receiver
1.0 VlDlv
5.0 nslDiv
This figure shows traces taken on a test fixture designed to
exaggerate the amplitude of crosstalk pulses.

Key
Vertical Scale Horizontal Scale
_._._. Active Driver
1.0 VlDlv
50 nS/Dlv
••••- Forward Crosstalk
0.2 VlDiv
5.0 ns/Div
- - Active Receiver
1.0 VlDlv
5.0 nslDiv
This figure shows traces taken on a test fixture designed to
exaggerate the amplitude of crosstalk pulses.

4-8

Ground Bounce

Figure 4·10a: High Noise Margin

Ground bounce occurs as a result of the intrinsic
characteristics of the leadframes and bondwires of
the packages used to house CMOS devices. As
edge rates and drive capability increase in advanced
logic families, the effects of these intrinsic
electrical characteristics become more pronounced.
Figure 4-12a shows a simple circuit model for a
device in a leadframe driving a standard test load.
The inductor L1 represents the parasitic inductance
in the ground lead of the package; inductor L2
represents the parasitic inductance in the power
lead of the package; inductor L3 represents the
parasitic inductance in the output lead of the
package; the resistor R1 represents the output
impedance of the device output, and the capacitor
and resistor CL and RL represent the standard test
load on the output of the device.

Pulse Width (nS)

Figure 4·10b: Low Noise Margin

Figure 4·12a: Output Model

Pulse Width (nS)

With over 2.0 V of noise margins, the FACT family
offers beUer noise rejection than any other
comparable technology.

L3

In any design, the distance that lines run adjacent
to each other should be kept as short as possible.
The best situation is when the lines are
perpendicular to each other. For those situations
where lines must run parallel, the effects of
crosstalk can be minimized by line termination.
Terminating a line in its characteristic impedance
reduces the amplitude of an initial crosstalk pulse
by 50%. Terminating the line will also reduce the
amount of ringing. Crosstalk problems can also be
reduced by moving lines further apart or by
inserting ground lines or planes between them.

CL

Figure 4·12b: Output Voltage

Figure 4·12c: Output Current

Figure 4·11: Effects of Termination on
Crosstalk
Signal on Active Line

Passive une--.
Zo

v,

~

Noise Amplitude at A

f

Vn=;OUPled Si 9 nal

Versus R

V

-----In,----

R~Zo

Figure 4·12d: Inductor Voltage
100%.: No R
67%: R = 2Z0
60%: R=1.5Zo
50%. R = Zo

4-9

RL

a

Observing either one of the following rules is
sufficient to avoid running into any of the problems
associated with ground bounce:
First, use caution when driving asynchronous TILlevel inputs from CMOS octal outputs, or
Second, use caution when running control lines
(set, reset, load, clock, chip select) which are
glitch-sensitive through the same devices that
drive data or address lines.

The three waveforms shown in Figures 4-12b, c and
d, depict how ground bounce is generated. The first
waveform shows the voltage (V) across the load as
it is switched from a logic HIGH to a logic LDW.
The output slew rate is dependent upon the
characteristics of the output transistor, the
inductors L1 and L3, and Cl, the load capacitance.
The second waveform shows the current that is
generated as the capacitor discharges [I =Cl·dV/dtj.
The third waveform shows the voltage that is
induced across the inductance in the ground lead
due to the changing currents [Vgb = -L·(dl/dt)].

When it is not possible to avoid the above
conditions, there are simple precautions available
which can minimize ground bounce noise. These
are:

There are many factors which affect the amplitude
of the ground bounce. Included are:

• Locate these outputs as close to the ground pin
as possible.

• Number of outputs switching simultaneously:
more outputs results in more ground bounce.

• Use the lowest Vec possible or separate the
power supplies.

• Type of output load: capacitive loads generate two
to three times more ground bounce than typical
system traces. Increasing the capacitive load to
approximately 60-70 pF increases ground bounce.
Beyond 70 pF, ground bounce drops off due to the
filtering effect of the load. Moving the load away
from the output reduces the ground bounce.

• Use board design practices which reduce any
additive noise sources, such as crosstalk,
reflections, etc.

Design Rules
The set of design rules listed below are
recommended to ensure reliable system operation
by providing the optimum power supply connection
to the devices. Most designers will recognize these
guidelines as those they have employed with
advanced bipolar logic families.

• Location of the output pin: outputs closer to the
ground pin exhibit less ground bounce than those
further away.
• Voltage: lowering Vcc reduces ground bounce.

• Use multi-layer boards with Vec and ground
planes, with the device power pins soldered
directly to the planes to insure the lowest power
line impedances possible.

• Test fixtures: standard test fixtures generate 30 to
50% more ground bounce than a typical system
since they use capacitive loads which both
increase the AC load and form LCR tank circuits
that oscillate.

• Use decoupling capacitors for every device,
usually 0.10 JLF should be adequate. These
capacitors should be located as close to the
ground pin as possible.

Ground bounce produces several symptoms:
• Altered device states. FACT logic does not exhibit
this symptom.

• Do not use sockets or wirewrap boards whenever
possible.

• Propagation delay degradation. FACT devices are
characterized not to degrade more than 250 ps per
additional output switching.

• Do not connect capacitors from the outputs
directly to ground.

Decoupling Requirements

• Undershoot on active outputs. The worst-case
undershoot will be approximately equal to the
worst-case quiet output noise.

Fairchild Advanced CMOS, as with other highperformance, high-drive logic families, has special
decoupling and printed circuit board layout
requirements. Adhering to these requirements will
ensure the maximum advantages are gained with
FACT products.

• Quiet output noise. FACT logic's worst-case quiet
output noise has been measured to be approximately 500-1100 mV in actual system applications.

4·10

Figure 4·13: Power Distribution Impedances

vcc-.....3~~~-=
1116

a) SOll Vee
Impedance

vcc~

Impedance

c) 6811 Vee
Impedance

God
032

Epoxy Glass
e) 211 Vee
Impedance

d) 10011 Vee
Impedance

Local high frequency decoupling is required to
supply power to the chip when it is transitioning
from a LOW to a HIGH value. This power is
necessary to charge the load capacitance or drive a
line impedance. Figure 4-13 displays various Vcc
and ground layout schemes along with associated
impedances.

impedance and will cause a droop in the Vce at the
part. This limits the available voltage swing at the •
local node, unless some form of decoupling is
used. This drooping of rails will cause the rise and
fall times to become elongated. Consider the
example described in Figure 4-14 to calculate the
amount of decoupling necessary. This circuit
utilizes an 'AC240 driving a 100 ohm bus from a
point somewhere in the middle.

For most power distribution networks, the typical
impedance is between 50 and 100 ohms. This
impedance appears in series with the load

Figure 4·14: Octal Buffer Driving a 100 Ohm Bus

Buffer Output Sees Net 500 Load.
500 Load Line on 10H - VOH Characteristic
Shows Low·to·High Step of Approx. 4.8V

Data Bus--.

VOUT

I'"

O.W
Ground

I
I

----I

Plane

I
I

1018

10H

I
I

1-4n8

I
I

"r·~

Worst-Case Octal Drain

4-11

=8

x 94 rnA

= 0.75 Amp.

In this example, if the Vcc droop is to be kept below
0.1 V and the edge rate equals 4 ns, a 0.030 I-'f
capacitor is needed.

Being in the middle of the bus, the driver will see
two 100 ohm loads in parallel, or an effective
impedance of 50 ohms. To switch the line from rail
to rail, a drive of 94 mA is needed; more than
750 mA will be required if all eight lines switch at
once. This instantaneous current requirement will
generate a voltage across the impedance of the
power lines, causing the actual Vcc at the chip to
droop. This droop limits the voltage swing available
to the driver. The net effect of the voltage droop will
lengthen device rise and fall times and slow system
operation. A local decoupling capacitor is required
to act as a low impedance supply for the driver chip
during high current conditions. It will maintain the
voltage within acceptable limits and keep rise and
fall times to a minimum. The necessary values for
decoupling capacitors can be calculated with the
formula given in Figure 4-15.

It is good practice to distribute decoupling
capacitors evenly through the logic, placing one
capacitor for every package.

Capacitor Types
Oecoupling capacitors need to be of the high K
ceramic type with low equivalent series resistance
(ESR), consisting primarily of series inductance and
series resistance. Capacitors using 5ZU dielectric
have suitable properties and make a good choice
for decoupling capacitors; they offer minimum cost
and effective performance.

Figure 4·15: Formula for Calculating Decoupling Capacitors

Vee Bus ~
Zee
Vee _ _
_,...._ _,...._ _,....---,

ICBI~
T
T r
.Y

...L
T

Bypass-=-Capaeilors-=-

Q" CV

1=0.7SA

I" Cb.V/b.1
C" 1b.t/b.V

-=-

b.1

0

4 x 10.9

Specify Vee Droop" 0.1 V max.

C=

0.750

x 4 x 10-9
0.1

=30)( 10

-9

=0.030!,F

Select CB '" 0.047!'F

Place one decoupling capacitor adjacent to each package
driving any transmission line and distribute others
evenly thoughout the logic. One capacitor per three
packages.

4·12

TTL·Compatible CMOS Designs Require Delta Icc Consideration
Figure 4·17: Icc versus Input Voltage for
'ACT Devices

The FACT product line is comprised of two types of
advanced CMOS circuits: 'AC and 'ACT devices. 'ACT
indicates an advanced CMOS device with TTL-type
input thresholds for direct replacement of LS and
ALS circuits. As this 'ACT series is used to replace
TTL, the Delta Icer specification must be
considered; this spec may be confusing and
misleading to the engineer unfamiliar with CMOS.

1.000

It is important to understand the concept of Delta
Icer and how to use it within a design. First,
consider where Delta Icer initiates. Most CMOS
input structures are of the totem pole type with an
n-channel transistor in a series with a p-channel
transistor as illustrated below.

>

'C

<
"E

-"0

§
ci

Figure 4·16: CMOS Input Structure

/

Vee
INPUT PAD

0.0000
0.0000

I

" '- '-...

./
O.5000V/div

V,N

P CHANNEL

a

......

............

---

5.000

TO

r---------~INTERNAL

LOGIC
The Delta Icc specification is the increase in Icc.
For each input at Vcc-2.1 V, the Delta Icc value
should be added to the quiescent supply current to
arrive at the circuit's worst-case static Icc value.
These two transistors can be modeled as variable
resistors with resistances varying according to the
input voltage. The resistance of an ON transistor is
approximately 50 ohms while the resistance of an
OFF transistor is generally greater than 5 Mohm.
When the input to this structure is at either ground
or Vcc, one transistor will be ON and one will be
OFF. The total series resistance of this pair will be
the combination of the two individual resistances,
greater than 5 Mohm. The leakage current will then
be less than 1 pA. When the input is between
ground and Vcc, the resistance of the ON transistor
will increase while the resistance of the OFF
transistor will decrease. The net resistance will
drop due to the much larger value of the OFF
resistance. The total series resistance can be as
low as 600 ohms. This reduction in series
resistance of the input structure will cause a
corresponding increase in Icc as current flows
through the input structure. The following graph
depicts typical Icc variance with input voltage for
an 'ACT device.

Fortunately, there are several factors which tend to
reduce the increase in Icc per input. Most TTL
devices will be able to drive FACT inputs well
beyond the TTL output specification due to FACT's
low input loading in a typical system. FAST logic
outputs can drive 'ACT-type inputs down to 200 mV
and up to 3.5 V. Additionally, the typical Icc increase
per input will be less than the specified limit. As
shown in the graph above, the Icc increase at
Vcc-2.1 V is less than 200 J.'A in the typical system.
Experiments have shown that the Icc of an 'ACT240
series device typically increases only 200 J.'A when
all of the inputs are connected to a FAST device
instead of ground or Vcc.
It is important when designing with FACT, as with
any TTL-compatible CMOS technology, that the
Delta Icc specification be considered. Designers
should be aware of the spec's significance and that
the data book specification is a worst-case value;
most systems will see values that are much less.

4-13

Testing Advanced CMOS Devices with 110 Pins
There are more and more CMOS families becoming
available which can replace TTL circuits. Although
testing these new CMOS units with programs and
fixtures which were developed for bipolar devices
will yield acceptable results most of the time, there
are some cases where this approach will cause the
test engineer problems.

conducts. Most Icc testing is done with all of the
inputs tied to either Vcc or ground. If the inputs are
allowed to float, they will typically float to the
middle of the transition region, and the input
structure will conduct an order of magnitude more
current than the actual Icc of the device under test
which is being measured by the tester.

Such is the case with parts that have a bidirectional
pin, exemplified by the '245 Octal Transceiver. If the
proper testing methods are not followed, these
types of parts may not pass those tests for Icc and
input leakage currents, even when there is no fault
with the devices.

Figure 4-18: Icc versus liN
10.00

CMOS circuits, unlike their bipolar counterparts,
have static Icc specification orders of magnitude
less than standard load currents. Most CMOS Icc
specifications are usually less than 100 p.A. When
conducting an Icc test, greater care must be taken
so that other currents will not mask the actual Icc
of the device. These currents are usually sourced
from the inputs and outputs.

1

Since the static Icc requirements of CMOS devices
are so low, output load currents must be prevented
from masking the current load of the device during
an Icc test. Even a standard 500 ohm load resistor
will sink 10 rnA at 5 V, which is more than twice the
Icc level being tested. Thus, most manufacturers
will specify that all outputs must be unloaded
during Icc tests.

0.00
0.00

V V

~

f:::::: r-.

VIN (V)

5.00

When testing the Icc of a CMOS '245, problems can
arise depending upon how the test is conducted.
Note the structure of the '245's 1/0 pins illustrated
below.

Figure 4-19: '245 I/O Structure
Another area of concern is identified when
considering the inputs of the device. When the
input is in the transition region, Icc can be several
orders of magnitude greater than the specification.
When the input voltage is in the transition region,
both the n-channel and the p-channel transistors in
the input totem-pole structure will be slightly ON,
and a conduction is created from Vcc to ground.
This conduction path leads to the increased Icc
current seen in the Icc vs. VIN curve. When the input
is at either rail, the input structure no longer

DRIVE ENABLE

4-14

Each 1/0 pin is connected to both an input device
and an output device. The pin can be viewed as
having three states: input, output and output
disabled. However, only two states actually exist.

device will also float, and an excessive amount of
current will flow from Vcc to ground. A simple rule
to follow is to treat any output which is disabled as
an input. This will help insure the integrity of an Icc
test.

The pin is either an input or an output. When
testing the Icc of the device, the pins selected as
outputs by the T/R signal must either be enabled
and left open or be disabled and tied to either rail.
If the output device is disabled and allowed to float,
the input

Another area which might precipitate problems is
the measurement of the leakages on 1/0 pins. The
1/0 pin internal structure is depicted below.
The pin is internally connected to both an input
device and an output device; the limit for a leakage
test must be the combined liN specification of the
input and the loz specification of the output. For
FACT devices, liN is specified at ± 1 pA while loz is
specified at ± 5 pA Combining these gives a limit
of ±6 p,A for 1/0 pins. Usually, 1/0 pins will show
leakages that are less than the loz specification of
the output alone.

Figure 4·20: 1/0 Pin Internal Structure

Testing CMOS circuits is no more difficult than
testing their bipolar counterparts. However, there
are some areas of concern that will be new to many
test engineers beginning to work with CMOS.
Becoming familiar with and understanding these
areas of concern prior to creating a test philosophy
will avert many problems that might otherwise arise
later.

liN:

loz

t

INPUT

~-------------.

CLAMP DIODES
OUTPUT

4·15

•

Testing Disable Times of 3·State Outputs in a
Transmission Line Environment
high degree of correlation can be achieved.
However, when devices with high output slew rates
are tested, different results are observed that make
correlating tester results with bench results more
difficult. This difference is due to the transmission
line properties of the test equipment. Most disable
tests are preceded by establishing a current flow
through the output structure. Typically, these
currents will be between 5 rnA and 20 rnA. The
device is then disabled, and a comparator detects
when the output has risen to the 10% or 90% level.

Traditionally, the disable time of a 3-state buffer has
been measured from the 50% point on the disable
input, to the 10% or 90% point on the output. On a
bench test site, the output waveform is generated
by a load capacitor and a pull-up/pull-down resistor.
This circuit gives an RC charge/discharge curve as
shown below.

Figure 4·21: Typical Bench 3-State Waveform

10

11

Consider the situation where the connection
between the device under test (OUT) and the
comparator is a transmission line. Visualize the
device output as a switch; the effect is easier to
see. There is current flowing through the line, and
then the switch is opened. At the device end, the
reflection coefficient changes from 0 to 1. This
generates a current edge flowing back down the
line equal to the current flowing in the line prior to
the opening of the switch. This current wave will
propagate down the line where it will encounter the
high impedance tester load. This will cause the
wave to be reflected back down the line toward the
OUT. The current wave will continue to reflect in the
transmission line until it reaches the voltage
applied to the tester load. At this point, the current
source impedance decreases and it will dissipate
the current. A typical waveshape on a modern ATE
is depicted in Figure 4-23.

12

Time (ns)

ATE test sites generally are unable to duplicate the
bench test structure. ATE test loads differ because
they are usually programmable and are situated
away from the actual device. A commonly used test
load is a Wheatstone bridge. The following figure
illustrates the Wheatstone bridge test structure
when used on the MGT 2000 test-system to
duplicate the bench load.

Figure 4·22: MCT Wheatstone Bridge Test
Load

Figure 4·23: Typical ATE 3-State Waveform
OE

.

~4

,;'3

OUT

'0

>2

J
1

The voltage source provides a pull-up/pull-down
voltage while the current sources provide 10H and
10L. When devices with slow output slew rates are
tested with the ATE load, the resultant waveforms
closely approximate the bench waveform, and a

4-16

2

3

4

5

6

9
7
8
Time (ns)

10

11

12

would be required before the comparator would
detect the level. It is this added delay time caused
by the transmission line environment of the ATE
that may cause parts to fail customers' incoming
tests, even though the device meets specifications.
The figure below graphically shows this stepout.

Transmission line theory states the voltage level of
this current wave is equal to the current in the line
times the impedance of the line. With typical
currents as low as 5 mA and impedances of 50 to
60 ohms, this voltage step can be as minimal as
250 mV. If the comparator was programmed to the
10% point, it would be looking for a step of 550 mV
at 5.5 V Vce. Three reflections of the current pulse

Point A represents the typical 50% measurement
point on tester driven waveforms. Point B
represents the point at which the delay time would
be measured on a bench test fixture. Point C
represents where the delay time could be measured
on ATE fixtures. The delay time measured on the
ATE fixture can vary from the bench measured delay
time to some greater value, depending upon the
voltage level that the tester is set. If the voltage
level of the tester is close to voltage levels of the
plateaus, the results may become non·repeatable.

Figure 4·24: Measurement Stepout

B

II

C

Time (ns)

4·17

Product Index and Selection Guide

FACT Descriptions and Family Characteristics

Ratings, Specifications and Waveforms

Design Considerations

Data Sheets

Package Outlines and Ordering Information

FGC Series Advanced 2-Micron CMOS Gate Array

FAIRCAD™ Semicustom Design System

CMOS Arrays Packaging Guide

Field Sales Offices and Distributor Locations

ACOO • ACTOO
54AC/74ACOO • 54ACT/74ACTOO
Quad 2-lnput NAND Gate
Connection Diagrams
• Outputs Source/Sink 24 rnA
• 'ACTOO has TTL·Compatible Inputs

GND~

rn

rn
rn

ITIl

[j]

Ii]

~vcc

~

~

Ordering Code: See Section 6
NC

NC

~~~@]I!!l
Ne
Ne

Pin Assignment
for LCC

Pin Assignment
for DIP, Flatpak and SOIC

DC Characteristics (unless otherwise specified)
Parameter

Symbol

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

4.0

ICCT

Maximum Additional
Icc/Input (,ACTOO)

1.6

74AC/ACT

80

Units

Conditions

/J- A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

4.0

/J- A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

40

AC Characteristics

Symbol

Parameter

Vce·
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= - 55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay

3.3
5.0

1.0
1.0

7.0
6.0

9.5
8.0

1.0
1.0

11.0
8.5

1.0
1.0

10.0
8.5

ns

3·5

tPHL

Propagation Delay

3.3
5.0

1.0
1.0

5.5
4.5

8.0
6.5

1.0
1.0

9.0
7.0

1.0
1.0

8.5
7.0

ns

3·5

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.
5·3

•

ACOO • ACTOO
AC Characteristics

Symbol

Parameter

Vcc·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay

5.0

1.0

5.5

9.0

1.0

9.5

1.0

9.5

ns

3-5

tPHL

Propagation Delay

5.0

1.0

4.0

7.0

1.0

8.0

1.0

8.0

ns

3-5

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request· Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

CPD

Power Dissipation
Capacitance

30.0

pF

Vcc=5.5 V

5-4

AC02
54AC/74AC02
Quad 2-lnput NOR Gate
Connection Diagrams

• Outputs Source/Sink 24 mA

Ordering Code: See Section 6
[!]
GND~

III
III

IBl

[j]

~

~ Vee

~

~

NC

NC

Pin Assignment
for LCC

Pin Assignment
for DIP, Flatpak and SOIC

DC Characteristics (unless otherwise specified)
Symbol

54AC

Parameter

Units

74AC

Conditions

Icc

Maximum Quiescent
Supply Current

80

40

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

4.0

4.0

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

AC Characteristics

Symbol

Parameter

Vcc*
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig';
No.

tPLH

Propagation Delay

3.3
5.0

1.0
1.0

5.0
4.0

7.5
6.0

1.0
1.0

9.0
7.0

1.0
1.0

8.0
6.5

ns

3-5

tPHL

Propagation Delay

3.3
5.0

1.0
1.0

5.0
4.5

7.5
6.5

1.0
1.0

9.0
7.5

1.0
1.0

8.0
7.0

ns

3-5

'Voltage Range 3.3 Is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.
5-5

•

AC02
Capacitance
Symbol

54174AC

Parameter

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

30.0

pF

Vcc=5.5 V

5-6

AC04 • ACT04
54AC/74AC04 • 54ACT/74ACT04
Hex Inverter
Connection Diagrams
• Outputs Source/Sink 24 mA
• 'ACT04 has nL·Compatlble Inputs

He

He

[!][lJ[!][!][!J

Ordering Code: See Section 6
[!]

[!]

GHD~

[!]

He

ITIl

(jJ He

~

~Vcc

~

~
§]~~I!!l~

He

He

Pin Assignment
for DIP, Flatpak and SOIC

Pin Assignment
for LCC

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

74AC/ACT

Units

Conditions

Icc

Maximum Quiescent
Supply Current

80

40

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

4.0

4.0

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

ICCT

Maximum Additional
Icc/Input (,ACT04)

1.6

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

AC Characteristics

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay

3.3
5.0

1.0
1.0

4.5
4.0

9.0
7.0

1.0
1.0

11.0
8.5

1.0
1.0

10.0
7.5

ns

3·5

tPHL

Propagation Delay

3.3
5.0

1.0
1.0

4.5
3.5

8.5
6.5

1.0
1.0

10.0
7.5

1.0
1.0

9.5
7.0

ns

3-5

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 Is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
Information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·7

•

AC04 • ACT04
AC Characteristics
54ACT

74ACT

8y

Units

Fig.

No.

Propagation Delay

5.0

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54174AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

30.0

pF

Vcc=5.5 V

5·8

AC08 • AeT08
54AC/74AC08 • 54ACT/74ACT08
Quad 2-lnput AND Gate
Connection Diagrams

• Outputs Source/Sink 24 mA
• 'ACTOS has TTL·Compatible Inputs

He

He

[!]1Il11J[5J~

Ordering Code: See Section 6

rn

[]J
GND~

[2]

[TIl

[i]

Ii]]

~ Vee

§

[iID

NC

NC

1Hl[i]~[i]~
Ne
Ne

Pin Assignment
for LCC

Pin Assignment
for DIP, Flatpak and SOIC

DC Characteristics (unless otherwise specified)
Symbol

Parameter

74AC/ACT

54AC/ACT

Units

Conditions

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

4.0

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

1.6

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA=Worst Case

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

4.0

ICCT

Maximum Additional
Icc/Input (,ACT08)

40

80

AC Characteristics

Symbol

Parameter

Vcc·
(V)

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay

3.3
5.0

1.0
1.0

7.5
5.5

9.5
7.5

1.0
1.0

12.0
9.0

1.0
1.0

10.0
8.5

ns

3·5

tPHL

Propagation Delay

3.3
5.0

1.0
1.0

7.0
5.5

8.5
7.0

1.0
1.0

11.5
8.5

1.0
1.0

9.0
7.5

ns

3·5

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·9

ACOS • ACTOS
AC Characteristics
54ACT

74ACT
Units

tPLH

Propagation Delay

tPHL

Propagation Delay

5.0

6.7

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

20.0

pF

Vcc=5.5 V

5·10

AC10
54AC/74AC10
Triple 3-lnput NAND Gate
Connection Diagrams

• Outputs Source/Sink 24 mA

Ordering Code: See Section 6
[II

[3J

GND~

[3J

ITIl

[i]

[g]

~ Vee

~--~~

[lID

NC

NC

NC

NC

Pin Assignment
for LCC

Pin Assignment
for DIP, Flatpak and SOIC

DC Characteristics (unless otherwise specified)
Symbol

Parameter

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

54AC

74AC

Units

80

40

p.A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

p.A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

4.0

4.0

Conditions

AC Characteristics

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay

3.3
5.0

1.0
1.0

6.0
4.5

9.5
7.0

1.0
1.0

11.0
8.5

1.0
1.0

10.5
8.0

ns

3·5

tPHL

Propagation Delay

3.3
5.0

1.0
1.0

5.5
4.0

8.5
6.0

1.0
1.0

10.0
7.0

1.0
1.0

10.0
6.5

ns

3·5

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·11

•

AC10
Capacitance
Symbol

54174AC

Parameter

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

CPD

Power Dissipation
Capacitance

25.0

pF

Vcc=5.5 V

5·12

AC11
54AC/74AC11
Triple 3-lnput AND Gate
Connection Diagrams

• Outputs Source/Sink 24 mA
NC

NC

w[7]w[E[4J

Ordering Code: See Section 6

m
GND
NC

[oJ

li:oJ

[Ill

[11] [

[ [i]

NC

12jJ

--"I,,-,..-.I.~..I.-y

Vee

[19]

~[i5]B][i7]B]
NC

NC

Pin Assignment
for LCC

Pin Assignment
for DIP, Flatpak and SOIC

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC

Icc

Maximum Quiescent
Supply Current

80

Icc

Maximum Quiescent
Supply Current

4.0

Units

74AC

40

4.0

Conditions

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

/LA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

AC Characteristics

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay

3.3
5.0

1.0
1.0

5.5
4.0

9.5
8.0

1.0
1.0

11.0
8.5

1.0
1.0

10.0
8.5

ns

3·5

tPHL

Propagation Delay

3.3
5.0

1.0
1.0

5.5
4.0

8.5
7.0

1.0
1.0

10.5
8.0

1.0
1.0

9.5
7.5

ns

3·5

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information· please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-13

•

AC11
Capacitance
Symbol

54174AC

Parameter

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

20.0

pF

Vcc=5.5 V

5·14

AC14 • ACT14
54AC/74AC14 • 54ACT/74ACT14
Hex Inverter Schmitt Trigger
Description

Connection Diagrams

The 'ACI'ACT14 contains six logic inverters which
accept standard CMOS input signals (TTL levels for
'ACT14) and provide standard CMOS output levels.
They are capable of transforming slowly changing
input signals into sharply defined, jitter-free output
signals. In addition, they have a greater noise
margin than conventional inverters.

Vee

The 'ACI'ACT14 has hysteresis between the
positive-going and negative-going input thresholds
(typically 1.0 V) which is determined internally by
transistor ratios and is essentially insensitive to
temperature and supply voltage variations.

Gnd

• Outputs Source/Sink 24 mA
• 'ACT14 has TTL-Compatible Inputs

Pin Assignment
for DIP, Flatpak and SOIC

Ordering Code: See Section 6
Ne

Ne

[!]11J[!][!][!]

Function Table
Input

A

0

L
H

H
L

rn
rn

[!]

Output

GND~
Ne

[j]

[j] Ne

Jg

~vcc

[j]]

[jID
§][i][i]IIil~
Ne

Ne

Pin Assignment
for LCC

5-15

•

AC14 • ACT14
DC Characteristics (unless otherwise specified)
Symbol

Parameter

Vee
(V)

54AC

54ACT

74AC

74ACT

Units

Conditions

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

4.0

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = 25°C

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

2.2
3.2
3.9

2.0

V

TA = Worst Case

0.8

0.5
0.9
1.1

0.8

V

TA = Worst Case

1.2
1.4
1.6

1.2

1.2
1.4
1.6

1.2

V

TA = Worst Case

0.3
0.4
0.5

0.4

0.3
0.4
0.5

0.4

V

TA = Worst Case

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

lecT

Maximum Additional
Icc/Input (,ACT14)

Vt+

Maximum Positive
Threshold

3.0
4.5
5.5

2.2
3.2
3.9

2.0

Vt-

Minimum Negative
Threshold

3.0
4.5
5.5

0.5
0.9
1.1

Vh(max)

Maximum Hysteresis

3.0
4.5
5.5

Vh(min)

Minimum Hysteresis

3.0
4.5
5.5

80

40

80

4.0

4.0

40

4.0

1.6

AC Characteristics

Symbol

Parameter

Vee·
(V)

tPLH

Propagation Delay

3.3
5.0

tPHL

Propagation Delay

3.3
5.0

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Units

Fig.
No.

Min

Typ

Max

Min

Max

Min

Max

1.0
1.0

9.5
7.0

13.5
10.0

1.0
1.0

16.0
12.0

1.0
1.0

15.0
11.0

ns

3·5

1.0
1.0

7.5
6.0

11.5
8.5

1.0
1.0

14.0
10.0

1.0
1.0

13.0
9.5

ns

3·5

·Voltage Range 3.3 Is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V±0.5 V
MIlitary parameters given herein are for general references only. For current military specifications and subgroup testing
Information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·16

AC14 • ACT14
AC Characteristics
54ACT

74ACT
Units

Sym

Fig.

No.

Propagation Delay

5.0

8.6

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative .

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

25.0

pF

Vcc=5.5 V

5-17

•

AC20
54AC/74AC20
Dual 4-lnput NAND Gate
Connection Diagrams

• Outputs Source/Sink 24 mA
NC

NC

NC

[IJ1Il[IJw0

Ordering Code: See Section 6

rn

I1J

GND~

o

NC

[1iJ

[1J NC

11?l
Ii]

Ii]

~ Vee

~[i5][i6][i!][i6]
NC

NC

NC

Pin Assignment
for LCC

Pin Assignment
for DIP, Flatpak and SOIC

DC Characteristics (unless otherwise specified)
Symbol

Parameter

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

54AC

74AC

80

40

4.0

Conditions

Units

4.0

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

AC Characteristics

Symbol

Parameter

Vee·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay

3.3
5.0

1.0
1.0

6.0
5.0

8.5
7.0

1.0
1.0

11.0
8.5

1.0
1.0

10.0
8.0

ns

3·5

tPHL

Propagation Delay

3.3
5.0

1.0
1.0

5.0
4.0

7.0
6.0

1.0
1.0

10.0
7.0

1.0
1.0

9.0
7.0

ns

3·5

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·18

AC20
Capacitance
Symbol

54174AC

Parameter

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

40.0

pF

Vcc=5.5 V

•

5·19

AC32 • ACT32
54AC/74AC32 • 54ACT/74ACT32
Quad 2-lnput OR Gate
Connection Diagrams
• Outputs Source/Sink 24 mA
• 'ACT32 has TTL·Compatlble Inputs

Ordering Code: See Section 6

GND
NC

[!]

rn

[j]J

rn

ffiI

[j]

[g]

~ Vee

[j]J

liE

NC

~~~5?l[1i]
Ne

NC

Pin Assignment
for LCC

Pin Assignment
for DIP, Flatpak and SOIC

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

74AC/ACT

Units

Conditions

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

4.0

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

80

40

Icc

Maximum Quiescent
Supply Current

4.0

ICCT

Maximum Additional
Iccllnput (,ACT32)

1.6

AC Characteristics

Symbol

Parameter

Vcc·
(V)

tPLH

Propagation Delay

3.3
5.0

tPHL

Propagation Delay

3.3
5.0

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Units

Fig.
No.

Min

Typ

Max

Min

Max

Min

Max

1.0
1.0

7.0
5.5

9.0
7.5

1.0
1.0

12.0
9.0

1.0
1.0

10.0
8.5

ns

3·5

1.0
1.0

7.0
5.0

8.5
7.0

1.0
1.0

11.5
8.5

1.0
1.0

9.0
7.5

ns

3·5

·Voltage Range 3.3 Is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.
5-20

AC32 • ACT32
AC Characteristics
74ACT

54ACT

74ACT
Units

Fig.
No.

tPLH

tPHL

Propagation Delay

5.0

6.6

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

20.0

pF

Vcc=5.5 V

5·21

•

AC74 • ACT74
54AC/74AC74 • 54ACT/74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
Connection Diagrams

Description
The 'ACI'ACT74 is a dual D-type flip-flop with
Asynchronous Clear and Set inputs and
complementary (Q, 0) outputs. Information at the
input is transferred to the outputs on the positive
edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not
directly related to the transition time of the
positive-going pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input
is locked out and information present will not be
transferred to the outputs until the next rising
edge of the Clock Pulse input.

Pin Assignment
for DIP, Flatpak and SOIC

Asynchronous Inputs:
LOW input to "So (Set) sets Q to HIGH level
LOW input to Co (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on Co and "So makes both
Q and 0 HIGH

Q1

Ne Sol NC cp,

[!][!][!]J]][!J

o,m

• Outputs Source/Sink 24 mA
• 'ACT74 has TTL-Compatible Inputs

mCo,

ffiI

III NC

02~

~vcc

Q2~

[jIDCD2

NC

Ordering Code: See Section 6

mO,

_L--_

GNO~

§I[j]~[jZ]1@
SD2 NC CP:! NC 02

Logic Symbol

Pin Assignment
for LCC
SOf
Of
Of

S02
O2
O2

cP f

cP 2

CO f

Y

Of

Truth Table (Each Half)
Inputs

C0 202

y

Pin Names
01, D2
CP1, CP2
COl, C02
"SOl, "S02
Ql,

'01,

Q2, '02

Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs

Outputs

"So

CO

CP

D

Q

0

L
H
L
H
H
H

H
L
L
H
H
H

X
X
X

X
X
X
H
L
X

H
L
H
H
L
Qo

L
H
H
L
H

.r
.r
L

00

H = HIGH Voltage Level
L LOW Voltage Level
X = Immaterial
I
LOW·to·HIGH Clock Transition
Qo(O'o) = Previous 0(0) before
LOW-to-HIGH Transition of Clock

=
=

5·22

AC74 • ACT74
Logic Diagram
SD - - - - - - - - - - - - - - - - _ . - 1 :>oO--__t :>><>_----,

D

Q

cp-----+------------~~~

CD-----------------+-I>~--__t:>><>_----~

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

•

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

4.0

ICCT

Maximum Additional
Iccllnput (,ACT74)

1.6

74AC/ACT

5-23

Conditions

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

4.0

p.A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

mA

VIN = Vcc - 2.1 V
Vcc=5.5 V,
TA=Worst Case

40

80

Units

AC74 • ACT74
AC Characteristics

Symbol

Parameter

Vee·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL= 50 pF

Min

Min

Min

Typ

Max

Max

95
95

Units

Fig.
No.

MHz

3·3

Max

fmax

Maximum Clock
Frequency

3.3
5.0

100
140

125
160

95
125

tPLH

Propagation Delay
GOn or SOn to an or On

3.3
5.0

1.0
1.0

8.0
6.0

12.0
9.0

1.0
1.0

14.5
10.5

1.0
1.0

13.0
10.0

ns

3·6

tPHL

Propagation Delay
GOn or SOn to an or On

3.3
5.0

1.0
1.0

10.5
8.0

12.0
9.5

1.0
1.0

20.0
14.5

1.0
1.0

13.5
10.5

ns

3·6

tPLH

Propagation Delay
CPn to an or On

3.3
5.0

1.0
1.0

8.0
6.0

13.5
10.0

1.0
1.0

17.5
11.0

1.0
1.0

16.0
10.5

ns

3·6

tPHL

Propagation Delay
CPn to an or On

3.3
5.0

1.0
1.0

8.0
6.0

14.0
10.0

1.0
1.0

16.0
11.5

1.0
1.0

14.5
10.5

ns

3-6

Units

Fig.
No.

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements

Symbol

Parameter

Vee·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

ts

Set-up Time,
HIGH or LOW
Dn to CPn

3.3
5.0

1.5
1.0

4.0
3.0

5.0
3.5

4.5
3.0

ns

3-9

th

Hold Time, HIGH or LOW
Dn to CPn

3.3
5.0

-2.0
-1.5

0
0

0.5
0.5

0
0

ns

3-9

tw

CPn or COn or SOn
Pulse Width

3.3
5.0

3.0
2.5

5.5
4.5

8.0
5.5

7.0
5.0

ns

3-6

tree

Recovery Time
GOn or SOn to CP

3.3
5.0

-2.5
-2.0

0
0

0.5
0.5

0
0

ns

3-9

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-24

AC74. ACT74
AC Characteristics

Symbol

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

fmax

Maximum Clock
Frequency

5.0

145

210

tPLH

Propagation Delay
"COn or SOn to Qn or an

5.0

1.0

5.5

9.5

1.0

11.5

1.0

tPHL

Propagation Delay
"COn or 50n to Qn or On

5.0

1.0

6.0

10.0

1.0

12.5

tPLH

Propagation Delay
CPn to Qn or an

5.0

1.0

7.5

11.0

1.0

tPHL

Propagation Delay
CPn to Qn or On

5.0

1.0

6.0

10.0

1.0

Units

Fig.
No.

Max
MHz

3-3

10.5

ns

3·6

1.0

11.5

ns

3-6

14.0

1.0

13.0

ns

3-6

12.0

1.0

11.5

ns

3-6

95

125

•

'Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements

Symbol

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Set-up Time,
HIGH or LOW
On to CPn

5.0

1.0

3.0

4.0

3.5

ns

3-9

th

Hold Time, HIGH or LOW
On to CPn

5.0

-0.5

1.0

1.0

1.0

ns

3-9

tw

CPn or "COn or SOn
Pulse Width

5.0

3.0

5.0

6.5

6.0

ns

3-6

tree

Recovery Time
"COn or 50n to CP

5.0

-2.5

0

0

0

ns

3-9

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·25

AC74 • ACT74
Capacitance
Symbol

Parameter

54174AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

35.0

pF

Vcc=5.5 V

5·26

AC86
54AC/74AC86
Quad 2-lnput Exclusive-OR Gate
Connection Diagrams
• Outputs Source/Sink 24 rnA

rn
rn

rn
GND~

Ordering Code: See Section 6

NC

!TIl

IT]

[j.2J

~ Vee

§

IiID

NC

~[1]~[i7]~
NC

NC

Pin Assignment
for LCC

Pin Assignment
for DIP, Flatpak and SOIC

DC Characteristics over Operating Temperature Range (unless otherwise specified)
Symbol

Parameter

54AC

74AC

Units

Conditions

Icc

Maximum Quiescent
Supply Current

80

40

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

4.0

4.0

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

AC Characteristics
74AC

54AC

74AC

TA= -55°C
to + 125°C
91,.,=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Units

Fig.
No.

tPHL
tPLH

Propagation Delay
Inputs to Outputs

3.3
5.0

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·27

•

AC86
Capacitance
Symbol

Parameter

CIN

Input Capacitance

Cpo

Power Dissipation
Capacitance

54174AC/ACT

Units

Conditions

pF

Vcc=5.5 V

pF

Vcc=5.5 V

Typ
4.5

5·28

AC109 • ACT109
54AC/74AC109 • 54ACT/74ACT109
Dual JK Positive Edge-Triggered Flip-Flop
Description
The 'ACI'ACT109 consists of two high-speed
completely independent transition clocked JK flipflops. The clocking operation is independent of
rise and fall times of the clock waveform. The JK
design allows operation as a D flip-flop (refer to
'ACI'ACT74 data sheet) by connecting the J and K
inputs together.

Connection Diagrams

Asynchronous Inputs:
LOW input to So (Set) sets
to HIGH level
LOW input to CD (Clear) sets a to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and So makes both
and 0 HIGH

a

a

Pin Assignment
for DIP, Flatpak and SOIC

• Outputs Source/Sink 24 mA
• 'ACT109 has TTL-Compatible Inputs

0,

SOl

NC cp, Kl

~12J~mw

Ordering Code: See Section 6

(i,m
Logic Symbol
J So Q

J

cp

cp

So Q

[I] J,

GND

[iQ]

[II CD'

NC

Ii]

[j]

NC

Q2 [2]

[gQ]

Vee

Q2

~

[jill CD2

[i][i][i][jlJ[i]
S02 CP2 NC

Inputs

L
H
L
H
H
H
H
H

J2

Pin Assignment
for LCC

Truth Table

So

K2

Outputs

CD

CP

J

K

a

H
L
L
H
H
H
H
H

X
X
X
S
S
S
S

X
X
X

X
X
X

L
H
L
H

L
L
H
H

L

X

X

H
L
L
H
H
H
L
H
Toggle
0000
H
L
0000

0-

Pin Names

J1, J2,

K1, K2

CP1, CP2
C01, C02
S01, S02
01, 02, 01, 02

=

H HIGH Voltage Level
L =LOW Voltage Level
I= LOW·to-HIGH Transition
X =Immaterial
00(0'0) = Previous 00(00) before
LOW-to-HIGH Transition of Clock

5-29

Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs

•

AC109 • ACT109
Logic Diagram (one half shown)

Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

4.0

ICCT

Maximum Additional
Iccllnput (,ACT109)

1.6

74AC/ACT

5-30

Conditions

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

4.0

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = 25°C

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

40

80

Units

AC109 • ACT109
AC Characteristics

Symbol

Parameter

Vcc*
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

90
95

Units

Fig.
No.

MHz

3·3

Max

100
125

fmax

Maximum Clock
Frequency

3.3
5.0

125
150

150
175

tPLH

Propagation Delay
CPn to On or <:in

3.3
5.0

1.0
1.0

8.0
6.0

13.5
10.0

1.0
1.0

17.5
11.0

1.0
1.0

16.0
10.5

ns

3·6

tPHL

Propagation Delay
CPn to On or <:in

3.3
5.0

1.0
1.0

8.0
6.0

14.0
10.0

1.0
1.0

16.0
11.5

1.0
1.0

14.5
10.5

ns

3·6

tPLH

Propagation Delay
COn or SOn to On or <:in

3.3
5.0

1.0
1.0

8.0
6.0

12.0
9.0

1.0
1.0

14.5
10.5

1.0
1.0

13.0
10.0

ns

3·6

tPHL

Propagation Delay
COn or SOn to On or <:in

3.3
5.0

1.0
1.0

10.0
7.5

12.0
9.5

1.0
1.0

20.0
14.5

1.0
1.0

13.5
10.5

ns

3·6

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

•

AC Operating Requirements

Symbol

Parameter

Vcc*
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA=-40oC
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Set·up Time,
HIGH or LOW
In or Kn to CPn

3.3
5.0

3.5
2.0

6.5
4.5

8.0
5.5

7.5
5.0

ns

3·9

th

Hold Time, HIGH or LOW
In or Kn to CPn

3.3
5.0

-1.5
-0.5

0
0.5

1.0
1.0

0
0.5

ns

3·9

tw

Pulse Width
CPn or GOn or SOn

3.3
5.0

2.0
2.0

4.0
3.5

8.0
5.5

4.5
3.5

ns

3·6

tree

Recovery Time
COn or SOn to CP

3.3
5.0

-2.5
-1.5

0
0

0
0

0
0

ns

3·9

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing in·
formation please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·31

AC109 • ACT109
AC Characteristics

Symbol

Parameter

Vcc·
(V)

74ACT

54ACT

74ACT

TA=+25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Units

Fig.
No.

MHz

3·3

Max

fmax

Maximum Clock
Frequency

5.0

145

210

tPLH

Propagation Delay
CPn to an or an

5.0

1.0

7.0

11.0

1.0

14.0

1.0

13.0

ns

3·6

tPHL

Propagation Delay
CPn to an or an

5.0

1.0

6.0

10.0

1.0

12.0

1.0

11.5

ns

3·6

tPLH

Propagation Delay
COn or SOn to an or an

5.0

1.0

5.5

9.5

1.0

11.5

1.0

10.5

ns

3·6

tPHL

Propagation Delay
COn or SOn to an or an

5.0

1.0

6.0

10.0

1.0

12.5

1.0

11.5

ns

3·6

Units

Fig.
No.

95

125

'Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements

Symbol

Parameter

Vcc·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

ts

Set·up Time,
HIGH or LOW
In or Kn to CPn

5.0

0.5

2.0

2.5

2.5

ns

3·9

th

Hold Time, HIGH or LOW
In or Kn to CPn

5.0

0

2.0

2.0

2.0

ns

3·9

tw

Pulse Width
CPn or COn or SOn

5.0

3.0

5.0

6.5

6.0

ns

3·6

tree

Recovery Time
COn or SOn to CP

5.0

-2.5

0

0

0

ns

3·9

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·32

AC109 • ACT109
Capacitance
Symbol

Parameter

54"4AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

35.0

pF

Vcc=5.5 V

•

5-33

AC138 • ACT138
54AC/74AC138 • 54ACT/74ACT138
1-of-8 Decoder/Demultiplexer
Description

Connection Diagrams

The 'ACI'ACT138 is a high-speed 1-of-8
decoder/demultiplexer. This device is ideally suited
for high-speed bipolar memory chip select address
decoding. The multiple input enables allow parallel
expansion to a 1-of-24 decoder using just three
'ACI'ACT138 devices or a 1-of-32 decoder using
four 'ACI'ACT138 devices and one inverter.
•
•
•
•
•

Demultlplexing Capability
Multiple Input Enable for Easy Expansion
Active LOW Mutually Exclusive Outputs
Outputs Source/Sink 24 rnA
'ACT138 has TIL·Compatible Inputs

Ordering Code: See Section 6

Pin Assignment
for DIP, Flatpak and SOIC

Logic Symbol
E3

E2

Ne

E1

A2

[!]0[!][]][!]

07 [!J

[]J

GND~

[II

Ao

ffi)

[j]

NC

NC

o.ij]]

~ Vee

05~

~Oo

~~~Il!ll!!l
04 03 NC 02 0,

Pin Assignment
for LCC

Pin Names
Ao - A2
Address Inputs
E1-~

E3

00 - 07

Enable Inputs
Enable Input
Outputs

5·34

A,

AC138 • ACT138
Functional Description

enabled function allows easy parallel expansion of
the device to a 1-of-32 (5 lines to 32 lines) decoder
with just four 'ACI'ACT138 devices and one inverter
(See Figure a). The 'ACI'ACT138 can be used as an
8-output demultiplexer by using one of the active
LOW Enable inputs as the data input and the other
Enable inputs as strobes. The Enable inputs which
are not used must be permanently tied to their
appropriate active-HIGH or active-LOW state.

The 'ACI'ACT138 high-speed 1-of-8
decoder/demultiplexer accepts three binary
weighted inputs (AD, A1, A2) and, when enabled,
provides eight mutually exclusive active-LOW
outputs (00 - 07). The 'ACI'ACT138 features three
Enable inputs, two active-LOW (E1, ~2) and one
active-HIGH (E3). All outputs will be HIGH unless
"E1 and ~2 are LOW and E3 is HIGH. This multiple

Truth Table
Inputs

E1

Outputs

~2

E3

AD

A1

A2

00

01

02

03

04

05

06

07

X
X
X

X
X
X

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H

X

X
X

H

X
X

X

L

X
X
X

L
L
L
L

L
L
L
L

H
H
H
H

L
H
L
H

L
L
H
H

L
L
L
L

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

H
H
H
H

L
H
L
H

L
L
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

=

H HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-35

•

AC138 • ACT138
Figure a: Expansion to 1-0'-32 Decoding
Ao~~------------------~----

______________.-________________--,

A'--r-~----------------~~----------------+_.-----------------~
A2--r-r-~--------------t-t-~--------------t-t-~--------------t-+-,

'04
A3----------~~------------------~~----------------~--------+_+_+_~~~
A4-----------;~------------------~r_----------------~~------+_+_+_----_+,

00 ---................. --.. ---.... -.................... -----........................... -.... --.... -........................ --.......... -------.................... ---... -------------.. ----------.. --........ ----

031

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Icc/Input (,ACT138)

1.6

160

5·36

74AC/ACT

Units

Conditions

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = 25°C

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

80

AC138 • ACT138
AC Characteristics

Symbol

Parameter

Vee·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
An to On

3.3
5.0

1.0
1.0

8.5
6.5

13.0
9.5

1.0
1.0

16.0
12.0

1.0
1.0

15.0
10.5

ns

3·6

tPHL

Propagation Delay
An to On

3.3
5.0

1.0
1.0

8.0
6.0

12.5
9.0

1.0
1.0

15.0
11.5

1.0
1.0

14.0
10.5

ns

3·6

tPLH

E1

Propagation Delay
or 'E2 to On

3.3
5.0

1.0
1.0

11.0
8.0

15.0
11.0

1.0
1.0

16.5
13.0

1.0
1.0

16.0
12.0

ns

3·6

tPHL

'E1

Propagation Delay
or E2 to On

3.3
5.0

1.0
1.0

9.5
7.0

13.5
9.5

1.0
1.0

15.5
12.0

1.0
1.0

15.0
10.5

ns

3-6

tPLH

Propagation Delay
E3 to On

3.3
5.0

1.0
1.0

11.0
8.0

15.5
11.0

1.0
1.0

17.0
13.5

1.0
1.0

16.5
12.5

ns

3-6

tPHL

Propagation Delay
E3 to On

3.3
5.0

1.0
1.0

8.5
6.0

13.0
8.0

1.0
1.0

15.0
11.0

1.0
1.0

14.0
9.5

ns

3·6

•

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 Is 5.0 V ± 0.5 V

AC Characteristics

Parameter

Symbol

Vee·
(V)

74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
An to On

5.0

1.0

7.0

10.5

1.0

12.5

1.0

11.5

ns

3·6

tPHL

Propagation Delay
An to On

5.0

1.0

6.5

10.5

1.0

12.5

1.0

11.5

ns

3·6

Propagation Delay
or E2 to On

5.0

1.0

8.0

11.5

1.0

13.5

1.0

12.5

ns

3·6

Propagation Delay
or 'E2 to On

5.0

1.0

7.5

11.5

1.0

12.5

1.0

12.5

ns

3·6

tPLH

Propagation Delay
E3toOn

5.0

1.0

8.0

12.0

1.0

14.0

1.0

13.0

ns

3·6

tPHL

Propagation Delay
E3 to On

5.0

1.0

6.5

10.5

1.0

12.0

1.0

11.5

ns

3·6

tPLH

E1

tPHL

'E1

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
Information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-37

AC138 • ACT138
Capacitance
Symbol

Parameter

54174AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

60.0

pF

Vcc=5.5 V

5·38

AC139 • ACT139
54AC/74AC139 • 54ACT/74ACT139
Dual 1-of-4 Decoder/Demultiplexer
Description

Connection Diagrams

The 'ACI'ACT139 is a high-speed, dual 1-of-4
decoder/demultiplexer. The device has two
independent decoders, each accepting two inputs
and providing four mutually-exclusive active-LOW
outputs. Each decoder has an active-LOW Enable
input which can be used as a data input for a
4-output demultiplexer. Each half of the
'ACI'ACT139 can be used as a function generator
providing all four minterms of two variables.
•
•
•
•
•

Multifunction Capability
Two Completely Independent 1-of-4 Decoders
Active LOW Mutually Exclusive Outputs
Outputs Source/Sink 24 mA
'ACT139 has TTL-Compatible Inputs
Pin Assignment
for DIP, Flatpak and SOIC

Ordering Code: See Section 6

02a 01a

Ne

Goa Ala

[!][l][!]~m

Logic Symbol

mAo.

03, [!]

[]]e.

GND~
NC

DECODER a

DECODER b

ITIl

[i]

~Vcc

02b~

~Et,

~[i]][i]][jrJ[i]]
'01b Oob

Ne

Alb Aob

Pin Assignment
for LCC

Pin Names
Ao, A1

E
'0'0-03

Address Inputs
Enable Inputs
Outputs

5-39

NC

030 [g

•

AC139 • ACT139
Logic Diagram
Ea

AOa

A'a

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

Figure a: Gate Functions (each half)

Functional Description
The 'ACI'ACT139 is a high-speed dual 1-of-4
decoder/demultiplexer. The device has two
independent decoders, each of which accepts two
binary weighted inputs (Ao - Al) and provides four
mutually exclusive active-LOW outputs (00 - (3).
Each decoder has an active-LOW enable (E). When
E is HIGH all outputs are forced HIGH. The enable
can be used as the data input for a 4-output
demultiplexer application. Each half of the
'ACI'ACT139 generates all four minterms of two
variables. These four minterms are useful in some
applications, replacing multiple gate functions as
shown in Figure a, and thereby reducing the
number of packages required in a logic network.

Truth Table
Inputs

Outputs

E

Ao

Al

00

01

02

03

H
L
L
L
L

X

X

L
H
L
H

L
L
H
H

H
L
H
H
H

H
H
L
H
H

H
H
H
L
H

H
H
H
H
L

H = HIGH Voltage Level
L =LOW Voltage Level
X = Immaterial
5-40

AC139 • ACT139
DC Characteristics (unless otherwise specified)
Parameter

Symbol

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

lecT

Maximum Additional
Icc/Input (,ACT139)

1.6

74AC/ACT

160

Conditions

Units

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

p.A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

rnA

VIN = Vcc - 2.1 V
Vcc=5.5 V,
TA = Worst Case

80

AC Characteristics

Symbol

Parameter

Vcc*
(V)

74AC

54AC

74AC

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Units

Fig.
No.

Min

Typ

Max

Min

Max

Min

Max

tPLH

Propagation Delay
An to On

3.3
5.0

1.0
1.0

8.0
6.5

11.5
8.5

1.0
1.0

14.5
11.0

1.0
1.0

13.0
9.5

ns

3·6

tPHL

Propagation Delay
An to On

3.3
5.0

1.0
1.0

7.0
5.5

10.0
7.5

1.0
1.0

12.5
10.0

1.0
1.0

11.0
8.5

ns

3·6

tPLH

Propagation Delay
En to On

3.3
5.0

1.0
1.0

9.5
7.0

12.0
8.5

1.0
1.0

14.5
11.0

1.0
1.0

13.0
10.0

ns

3·6

tPHL

Propagation Delay
En to On

3.3
5.0

1.0
1.0

8.0
6.0

10.0
7.5

1.0
1.0

12.5
10.0

1.0
1.0

11.0
8.5

ns

3·6

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·41

•

AC139 • ACT139
AC Characteristics

Symbol

tPLH
tPHL
tPLH
tPHL

Parameter

Propagation Delay

An to On
Propagation Delay

An to On
Propagation Delay

En to On
Propagation Delay

En to On

Vcc·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Units

Fig.
No.

Min

Typ

Max

Min

Max

Min

Max

5.0

1.0

6.0

8.5

1.0

12.0

1.0

9.5

ns

3·6

5.0

1.0

6.0

9.5

1.0

11.0

1.0

10.5

ns

3·6

5.0

1.0

7.0

10.0

1.0

12.5

1.0

11.0

ns

3·6

5.0

1.0

7.0

9.5

1.0

12.0

1.0

10.5

ns

3-6

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

40.0

pF

Vcc=5.5 V

5·42

AC151 • ACT151
54AC/74AC151 • 54ACT/74ACT151
1-of-8 Decoder/Demultiplexer
Description

Connection Diagrams

The 'ACI'ACT151 is a high-speed 8-input digital
multiplexer. It provides, in one package, the ability
to select one line of data from up to eight sources.
The 'ACI'ACT151 can be used as a universal
function generator to generate any logic function
of four variables. Both true and complementary
outputs are provided.
• Outputs Source/Sink 24 rnA
• 'ACT151 has TTL-Compatible Inputs

Ordering Code: See Section 6
Logic Symbol

Pin Assignment
for DIP, Flatpak and SOIC
ZZNCIOh

I1lIIl~ru@]

rn I,

Ern
GND~

[2J

[i]

OJ NC

S,

Ii]

~ Vee

s, Ii]

~I'

fi4l!15l~Ii1l~
SohNCI6b

Pin Assignment
for LeC

Truth Table
Inputs

Outputs

E

S2

S1

So

Z

Z

H
L
L
L
L
L
L
L
L

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
L
H
L
H
L
H

H
To
T1

L
10
11
12
13
14
15
16
17

T2

T3
T4
T5
T6

T7

Pin Names
10 - 17
So - S2

E
Z

Z

H = HIGH Voltage Level
L LOW Voltage Level
X Immaterial

=
=

5-43

13

NC

Data Inputs
Select Inputs
Enable Input
Data Output
Inverted Data Output

•

AC151 • ACT151
Functional Description
The 'ACI'ACT151 provides the ability, in one
package, to select from eight sources of data or
control information. By proper manipulation of the
inputs, the 'ACI'ACT151 can provide any logic
function of four variables and its complement.

The 'ACI'ACT151 is a logic implementation of a
single pole, 8-position switch with the switch
position controlled by the state of three Select
inputs, So, Sl, S2. Both true and complementary
outputs are provided. The Enable input (E) is active
LOW. When it is not activated, the complementary
output is HIGH and the true output is LOW
regardless of all other inputs. The logic function
provided at the output is:

z =i:-(10-50-51-52 + 11-So-51-52 +
12-50-S1-52 + 13-S0-S1-52 +
14-50-51-S2 + 15-So-51-S2 +
16-50-S1-S2 + 17-S0-S1-S2)

Logic Diagram
10

14

13

11

15

s2------~I~o---~--_clJ~----+_----_+------~----_;------4_~----r_~--~~----r_,

S,------~~---.--~~----~~----~----_+~----~~--_4~----4_~--~~----_h

so------~~--~----~~~----+H----_4~----~r_--_;~~--~+_----~t_--_HH_----+h

E------~>_--------------~~--_H+H~~tH~--H+Hr--~~--_H+H~~tH~--H+h

z

z

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5·44

AC151 • ACT151
DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

74AC/ACT

Units

Conditions

160

80

p.A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

8.0

p.A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

ICCT

Maximum Additional
Icc/Input (,ACT151)

1.6

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA=Worst Case

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

AC Characteristics

Parameter

Symbol

Vcc·
(V)

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
Sn to Z or Z

3.3
5.0

1.0
1.0

11.5
8.5

18.0
13.0

1.0
1.0

22.0
15.5

1.0
1.0

20.0
15.0

ns

3-6

tPHL

Propagation Delay
Sn to Z or Z

3.3
5.0

1.0
1.0

12.0
8.5

18.0
13.0

1.0
1.0

22.0
15.5

1.0
1.0

20.0
15.0

ns

3-6

tPLH

E to

Propagation Delay
Z or Z

3.3
5.0

1.0
1.0

8.0
6.0

13.0
10.0

1.0
1.0

15.5
12.0

1.0
1.0

14.0
11.0

ns

3-6

tPHL

E to

Propagation Delay
Z or Z

3.3
5.0

1.0
1.0

8.5
6.5

13.0
10.0

1.0
1.0

15.5
12.0

1.0
1.0

14.0
11.0

ns

3-6

tPLH

Propagation Delay
In to Z or Z

3.3
5.0

1.0
1.0

9.5
7.0

14.0
10.5

1.0
1.0

16.0
12.0

1.0
1.0

15.5
11.0

ns

3-5

tPHL

Propagation Delay
In to Z or Z

3.3
5.0

1.0
1.0

9.5
7.0

15.0
11.0

1.0
1.0

18.0
13.0

1.0
1.0

16.0
12.0

ns

3-5

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-45

AC151 • ACT151
AC Characteristics

Symbol

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
Sn to Z

5.0

1.0

12.5

15.5

1.0

17.0

ns

3-6

tPHL

Propagation Delay
Sn to Z

5.0

1.0

12.5

15.5

1.0

16.5

ns

3-6

tPLH

Propagation Delay
Sn to Z

5.0

1.0

12.5

15.0

1.0

16.5

ns

3-6

tPHL

Propagation Delay
Sn to Z

5.0

1.0

12.5

16.5

1.0

18.5

ns

3-6

5.0

1.0

10.0

9.5

1.0

10.0

ns

3-6

tPLH

Propagation Delay

1: to Z

tPHL

Propagation Delay
Eto Z

5.0

1.0

10.5

9.0

1.0

10.0

ns

3-6

tPLH

Propagation Delay
Eto Z

5.0

1.0

10.0

8.5

1.0

9.5

ns

3-6

tPHL

Propagation Delay
Eto Z

5.0

1.0

10.5

10.0

1.0

10.5

ns

3-6

tPLH

Propagation Delay
In to Z

5.0

1.0

11.0

11.5

1.0

12.5

ns

3-6

tPHL

Propagation Delay
In to Z

5.0

1.0

11.0

12.0

1.0

13.5

ns

3-6

tPLH

Propagation Delay
In to Z

5.0

1.0

11.0

12.0

1.0

13.0

ns

3-6

tPHL

Propagation Delay
In to Z

5.0

1.0

11.0

12.5

1.0

14.0

ns

3-6

·Voltage Range 5.0 Is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
Information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54174AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

70.0

pF

Vcc=5.5 V

5-46

AC153 • ACT153
54AC/74AC153 • 54ACT/74ACT153
Dual 4-lnput Multiplexer
Description

Connection Diagrams

The 'ACI'ACT153 is a high-speed dual 4-input
multiplexer with common select inputs and
individual enable inputs for each section. It can
select two lines of data from four sources. The two
buffered outputs present data in the true (noninverted) form. In addition to multiplexer operation,
the 'ACI'ACT153 can act as a function generator
and generate any two functions of three variables.

• Outputs Source/Sink 24 mA
• 'ACT153 has TTL-Compatible Inputs

Ordering Code: See Section 6
Pin Assignment
for DIP, Flatpak and SOIC
loa

11a

NC

12a

l3a

[!Jl1lw[§J@l

Logic Symbol

rn s,

:zorn
GND

[j]]

mE,.

NC

[j]

IT]

~ Vee

IOb§

IiID Eb

So

§]~[i§][i][i§]
I1b 12b NC I3b So

Pin Assignment
for LCC

Pin Names
loa - 13a
lab - 13b
50,51

Ea
Eb
Za
Zb

Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Enable Input
Side B Enable Input
Side A Output
Side B Output

5-47

NC

Zb~

•

AC153 • ACT153
Functional Description

Truth Table

The 'ACI'ACT153 is a dual 4-input multiplexer. It
can select two bits of data from up to four sources
under the control of the common Select inputs (So,
Sl)_ The two 4-input multiplexer circuits have
individual active-LOW Enables (Ea, Eb) which can
be used to strobe the outputs independently. When
the Enables (Ea, Eb) are HIGH, the corresponding
outputs (Za, Zb) are forced LOW. The 'ACI'ACT153
is the logic implementation of a 2-pole, 4-position
switch, where the position of the switch is
determined by the logic levels supplied to the two
Select inputs. The logic equations for the outputs
are shown below.

Select
Inputs

Za =Ea-(loa-Sl-S0 + 11a-Sl-S0 + 12a-Sl-S0 + 13a-Sl-S0)
Zb =Eb-(lob-Sl-S0 + 11 b-Sl-S0 + 12b-Sl-S0 + 13b-Sl-S0)

Inputs (a or b)

Output

So

Sl

E

10

11

12

13

Z

X
L
L
H

X
L
L
L

H
L
L
L

X
L
H
X

X
X
X
L

X
X
X
X

X
X
X
X

L
L
H
L

H
L
L
H
H

L
H
H
H
H

L
L
L
L
L

X
X
X
X
X

H
X
X
X
X

X
L
H
X
X

X
X
X
L
H

H
L
H
L
H

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

Logic Diagram
fa lOa

So

10 b

z.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-48

AC153 • ACT153
DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Iccllnput (,ACT153)

1.6

74AC/ACT

160

Units

Conditions

p,A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

p,A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

80

•

AC Characteristics

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
Sn to Zn

3.3
5.0

1.0
1.0

9.5
6.5

15.0
11.0

1.0
1.0

19.5
14.0

1.0
1.0

17.5
12.5

ns

3-6

tPHL

Propagation Delay
Sn to Zn

3.3
5.0

1.0
1.0

8.5
6.5

14.5
11.0

1.0
1.0

18.0
13.5

1.0
1.0

16.5
12.0

ns

3-6

tPLH

Propagation Delay
En to Zn

3.3
5.0

1.0
1.0

8.0
5.5

13.5
9.5

1.0
1.0

16.5
12.5

1.0
1.0

16.0
11.0

ns

3-6

tPHL

Propagation Delay
En to Zn

3.3
5.0

1.0
1.0

7.0
5.0

11.0
8.0

1.0
1.0

14.0
10.0

1.0
1.0

12.5
9.0

ns

3-6

tPLH

Propagation Delay
In to Zn

3.3
5.0

1.0
1.0

7.5
5.5

12.5
9.0

1.0
1.0

16.0
11.5

1.0
1.0

14.5
10.5

ns

3-5

tPHL

Propagation Delay
In to Zn

3.3
5.0

1.0
1.0

7.0
5.0

11.5
8.5

1.0
1.0

14.5
10.5

1.0
1.0

13.0
10.0

ns

3-5

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·49

AC153 • ACT153
AC Characteristics

Symbol

Parameter

Vcc·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
Sn to Zn

5.0

1.0

7.0

11.5

1.0

15.0

1.0

13.5

ns

3·6

tPHL

Propagation Delay
Sn to Zn

5.0

1.0

7.0

11.5

1.0

14.5

1.0

13.5

ns

3·6

tPLH

Propagation Delay
En to Zn

5.0

1.0

6.5

10.5

1.0

13.5

1.0

12.5

ns

3·6

tPHL

Propagation Delay
En to Zn

5.0

1.0

6.0

9.5

1.0

11.5

1.0

11.0

ns

3·6

tPLH

Propagation Delay
In to Zn

5.0

1.0

5.5

9.5

1.0

12.5

1.0

11.0

ns

3·5

tPHL

Propagation Delay
In to Zn

5.0

1.0

5.5

9.5

1.0

12.0

1.0

11.0

ns

3·5

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

CPD

Power Dissipation
Capacitance

65.0

pF

Vcc= 5.5 V

5·50

AC157 • ACT157
54AC/74AC157 • 54ACT/74ACT157
Quad 2-lnput Multiplexer
Connection Diagrams

Description
The 'ACI'ACT157 is a high-speed quad 2-input
multiplexer. Four bits of data from two sources can
be selected using the common Select and Enable
inputs. The four outputs present the selected data
in the true (noninverted) form. The 'ACI'ACT157 can
also be used as a function generator.
• Outputs Source/Sink 24 mA
• 'ACT157 has TTL-Compatible Inputs

Ordering Code: See Section 6

•

Pin Assignment
for DIP, Flatpak and SOIC

Logic Symbol

hb lOb NC Za I1d
[!]0[!]1]J~

s

mlo,
rns

z.[!]
GND~
NC

ffil

[j]

~ Vee

11d~

~E

~~[j]IEI[j]
IOd Zc Ne 11c Ioe

Pin Assignment
for LCC

Pin Names
lOa - IOd

l1a - I1d

1:
S
Za-Zd

Source 0 Data Inputs
Source 1 Data Inputs
Enable Input
Select Input
Outputs

5-51

NC

z,(g]

AC157. ACT157
Functional Description
The 'ACI'ACT157 is a quad 2-input multiplexer. It
selects four bits of data from two sources under
the control of a common Select input (5). The
Enable input (E) is active-LOW. When I: is HIGH, all
of the outputs (Z) are forced LOW regardless of all
other inputs. The 'ACI'ACT157 is the logic
implementation of a 4-pole, 2-position switch where
the position of the switch Is determined by the
logic levels supplied to the Select input. The logic
equations for the outputs are shown below:

generate any four of the sixteen different functions
of two variables with one variable common. This is
useful for implementing gating functions.

Truth Table
Inputs

Za= l:e(l1a eS + 10aeS)
Zb= 'E e (11b e S+ 10b-S)
Zc = 'E e (11c e S + laceS)
Zd = l:e(l1d eS + lOdeS)

Outputs

E

S

10

11

Z

H
L
L
L
L

X

X
X
X

X

L
H

X
X

L
L
H
L
H

H
H
L
L

L
H

H = HIGH Voltage Level
L= LOW Voltage Level
X = Immaterial

A common use of the 'ACI'ACT157 is the moving
of data from two groups of registers to four
common output busses. The particular register
from which the data comes is determined by the
state of the Select input. A less obvious use is as
a function generator. The 'ACfACT157 can

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-52

AC157 • ACT157
DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Iccllnput (,ACT157)

1.6

74AC/ACT

160

Units

Conditions

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

80

•

AC Characteristics

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
S to Zn

3.3
5.0

1.0
1.0

7.0
5.5

11.5
9.0

1.0
1.0

14.5
11.0

1.0
1.0

13.0
10.0

ns

3·6

tPHL

Propagation Delay
S to Zn

3.3
5.0

1.0
1.0

6.5
5.0

11.0
8.5

1.0
1.0

13.5
10.5

1.0
1.0

12.0
9.5

ns

3·6

Propagation Delay

3.3
5.0

1.0
1.0

7.0
5.5

11.5
9.0

1.0
1.0

14.0
10.5

1.0
1.0

13.0
10.0

ns

3·6

tPLH

E to Zn

tPHL

E to Zn

3.3
5.0

1.0
1.0

6.5
5.5

11.0
9.0

1.0
1.0

13.0
10.5

1.0
1.0

12.0
9.5

ns

3·6

tPLH

Propagation Delay
In to Zn

3.3
5.0

1.0
1.0

5.0
4.0

8.5
6.5

1.0
1.0

10.0
7.5

1.0
1.0

9.0
7.0

ns

3·5

tPHL

Propagation Delay
In to Zn

3.3
5.0

1.0
1.0

5.0
4.0

8.0
6.5

1.0
1.0

10.0
7.5

1.0
1.0

9.0
7.0

ns

3·5

Propagation Delay

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 Is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing In·
formation please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·53

AC157 • ACT157
AC Characteristics

Parameter

Symbol

Vcc·
(V)

74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
S to Zn

5.0

1.0

5.5

9.0

1.0

13.0

1.0

10.0

ns

3·6

tPHL

Propagation Delay
S to Zn

5.0

1.0

5.5

9.5

1.0

12.5

1.0

10.5

ns

3·6

5.0

1.0

6.0

10.0

1.0

13.0

1.0

11.5

ns

3·6

5.0

1.0

5.0

8.5

1.0

12.5

1.0

9.0

ns

3·6

Propagation Delay

tPLH

E to Zn

tPHL

'E to Zn

Propagation Delay

tPLH

Propagation Delay
In to Zn

5.0

1.0

4.0

7.0

1.0

10.0

1.0

8.5

ns

3·5

tPHL

Propagation Delay
In to Zn

5.0

1.0

4.5

7.5

1.0

10.0

1.0

8.5

ns

3·5

'Voltage Range 5.0 Is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
Information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54174AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

50.0

pF

Vcc=5.5 V

5-54

AC158 • ACT158
54AC/74AC158 • 54ACT/74ACT158
Quad 2-lnput Multiplexer
Connection Diagrams

Description
The 'ACI'ACT158 is a high-speed quad 2-input
multiplexer. It selects four bits of data from two
sources using the common Select and Enable
inputs. The four buffered outputs present the
selected data in the inverted form. The
'ACI'ACT158 can also be used as a function
generator.
• Outputs Source/Sink 24 mA
• 'ACT158 has TTL-Compatible Inputs

Ordering Code: See Section 6
Pin Assignment
for DIP, Flatpak and SOIC

Logic Symbol

hb lOb Ne Za ha
[!][l][!]m[1J

s

Zb [!]

m

GND~

[!Is

NC

ha - hd

'E
S

Za - Zd

ITIl

[j]NC

Zd~

~ Vee

11d~

~E

1HI~1HI11i11H1

Pin Names
lOa - 10d

10.

ICd

Source 0 Data Inputs
Source 1 Data Inputs
Enable Input
Select Input
Inverted Outputs

ZC

NC

11c

loc

Pin Assignment
for LCC

5-55

•

AC158 • ACT158
Functional Description
The 'ACI'ACT158 quad 2-input multiplexer selects
four bits of data from two sources under the
control of a common Select input (S) and presents
the data in inverted form at the four outputs. The
Enable input (e) is active-LOW. When "E is HIGH, all
of the outputs (Z) are forced HIGH regardless of all
other inputs. The 'ACI'ACT158 is the logic
implementation of a 4-pole, 2-position switch where
the position of the switch is determined by the
logic levels supplied to the Select input.

generate four functions of two variables with one
variable common. This is useful for implementing
gating functions.

Truth Table
Inputs

A common use of the 'ACI'ACT158 is the moving
of data from two groups of registers to four
common output busses. The particular register
from which the data comes is determined by the
state of the Select input. A less obvious use is as
a function generator. The 'ACI'ACT158 can

Output

"E

S

10

11

Z

H
L
L
L
L

X
L
L
H
H

X
L
H
X
X

X
X
X
L
H

H
H
L
H
L

H = HIGH Voltage Level
L LOW Voltage Level
X = Immaterial

=

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.
5-56

AC158 • ACT158
DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

74AC/ACT

Units

Conditions

Icc

Maximum Quiescent
Supply Current

160

80

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

8.0

8.0

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = 25°C

ICCT

Maximum Additional
Icc/Input (,ACT158)

1.6

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V
TA = Worst Case

AC Characteristics

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
S to Zn

3.3
5.0

1.0
1.0

7.0
5.5

11.5
9.0

1.0
1.0

13.5
10.5

1.0
1.0

12.5
9.5

ns

3·6

tPHL

Propagation Delay
S to Zn

3.3
5.0

1.0
1.0

7.0
5.5

11.5
9.0

1.0
1.0

14.0
10.5

1.0
1.0

12.5
10.0

ns

3-6

Propagation Delay

3.3
5.0

1.0
1.0

7.5
6.0

12.0
9.5

1.0
1.0

14.5
11.0

1.0
1.0

13.0
10.5

ns

3-6

tPLH

'E to Zn

tPHL

'E to Zn

3.3
5.0

1.0
1.0

7.0
5.5

11.0
8.5

1.0
1.0

13.0
10.0

1.0
1.0

12.0
9.5

ns

3-6

tPLH

Propagation Delay
In to Zn

3.3
5.0

1.0
1.0

5.5
4.0

9.0
7.0

1.0
1.0

10.5
8.5

1.0
1.0

10.0
7.5

ns

3·5

tPHL

Propagation Delay
In to Zn

3.3
5.0

1.0
1.0

5.0
4.0

8.0
6.5

1.0
1.0

9.5
7.5

1.0
1.0

8.5
6.5

ns

3·5

Propagation Delay

·Voltage Range 3.3 Is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
Information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·57

•

AC158 • ACT158
AC Characteristics

Parameter

Symbol

Vcc*
(V)

74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
S to Zn

5.0

1.0

6.0

9.5

1.0

12.0

1.0

11.0

ns

3-6

tPHL

Propagation Delay
S to Zn

5.0

1.0

5.5

9.0

1.0

11.0

1.0

10.0

ns

3-6

5.0

1.0

5.5

9.5

1.0

11.0

1.0

10.5

ns

3·6

5.0

1.0

5.5

9.5

1.0

11.5

1.0

10.5

ns

3·6

Propagation Delay

tPLH

"E to In

tPHL

"E to In

Propagation Delay

tPLH

Propagation Delay
In to Zn

5.0

1.0

4.5

8.0

1.0

9.5

1.0

8.5

ns

3-6

tPHL

Propagation Delay
In to Zn

5.0

1.0

4.0

6.5

1.0

8.0

1.0

7.5

ns

3-6

·Voltage Range 5.0 is 5.0 V ± 0.5 V
MIlitary parameters given herein are for general references only. For current military specifications and subgroup testing
Information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54"4AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

45.0

pF

Vcc=5.5 V

5·58

AC160 • ACT160 • AC162 • ACT162
54AC/74AC160 • 54ACT/74ACT160
54AC/74AC162 • 54ACT/74ACT162
Synchronous Presettable BCD Decade Counter
Description

Connection Diagrams

The 'ACI'ACT160 and 'ACI'ACT162 are high-speed
synchronous decade counters operating in the
BCD (8421) sequence. They are synchronously
presettable for application in programmable
dividers and have two types of Count Enable
inputs plus a Terminal Count output for versatility
in forming synchronous multistage counters. The
'ACI'ACT160 has an asynchronous Master Reset
input that overrides all other inputs and forces the
outputs LOW. The 'ACI'ACT162 has a Synchronous
Reset input that overrides counting and parallel
loading and allows all outputs to be
simultaneously reset on the rising edge of the
clock.

•
•
•
•
•

Pin Assignment
for DIP, Flatpak and SOIC

Synchronous Counting and Loading
High-Speed Synchronous Expansion
Typical Count Rate of 120 MHz
Outputs Source/Sink 24 mA
'ACT160 and 'ACT162 have TTL-Compatible Inputs

p]

p,

NC

p,

Po

mITl[K]mw
CEP

Ordering Code: See Section 6

@]

[!]

NC

[i]

[i]

NC

~ Vee

i'E[gj

Logic Symbol

CP

[II 'R

GNO ~

~ TC

CET ~

[14]~~[i1J~
0,

CET

TC

02

NC

0,

00

Pin Assignment
for LeC

CP

• MR for '160
• 'S'R" for '162

• MR for '160
• SA" for '162

Pin Names
CEP
CET
CP
'fJR" (,160)
SA (,162)
Po - P3
PE

00 - 03
TC

Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Asynchronous Master Reset Input
Synchronous Reset Input
Parallel Data Inputs
Parallel Enable Input
Flip-Flop Outputs
Terminal Count Output
5-59

•

AC160 • ACT160 • AC162 • ACT162
Functional Description
The 'ACI'ACT160 and 'ACI'ACT162 count modul0-10
in the BCD (8421) sequence. From state 9 (HLLH)
they increment to state 0 (LLLL). The clock inputs
of all flip-flops are driven in parallel through a
clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the '160) occur as a
result of, and synchronous with, the LOW-to-HIGH
transition of the CP input signal. The circuits have
four fundamental modes of operation, in order of
precedence: asynchronous reset (,160),
synchronous reset (,162), parallel load, count-up
and hold. Five control inputs-Master Reset (JiifFf,
'160), Synchronous Reset (SR, '162), Parallel Enable
(PE), Count Enable Parallel (CEP) and Count Enable
Trickle (CET)-determine. the mode of operation, as
shown in the Mode Select Table. A LOW signal on
"f.ifFi overrides all other inputs and asynchronously
forces all outputs LOW. A LOW signal on "SA
overrides counting and parallel loading and allows
all outputs to go LOW on the next rising edge of
CPo A LOW signal on PE overrides counting and
allows information on the Parallel Data (Pn) inputs
to be loaded Into the flip-flops on the next rising
edge of CPo With "J5E and M"Fi ('160) or "SA (,162)
HIGH, CEP and CET permit counting when both
are HIGH. Conversely, a LOW signal on either CEP
or CET inhibits counting.

The 'ACI'ACT160 and 'ACI'ACT162 use D-type edgetriggered flip-flops and changing the "SA, PE, CEP
and CET inputs when the CP is in either state does
not cause errors, provided that the recommended
setup and hold times, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET
is HIGH and counter is in state 9. To implement
synchronous multistage counters, the TC outputs
can be used with the CEP and CET inputs In two
different ways. Please refer to the 'AC568 data
sheet. The TC output Is subject to decoding spikes
due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous
reset for flip-flops, counters or registers. In the
'ACI'ACT160 and 'ACI'ACT162 decade counters, the
TC output is fully decoded and can only be HIGH
in state 9. If a decade counter is preset to an
illegal state, or assumes an illegal state when
power is applied, it will return to the normal
sequence within two counts, as shown in the State
Diagram.

=

Logic Equations: Count Enable CEP-CET-PE
TC = QO-Ql-Q2-Q3-CET

State Diagram
Mode Select Table
Action on the Rising

""SA PE CET CEP Clock Edge (.f)
L
H
H
H

H

X
L
H
H
H

X
X
H
L
X

X
X
H
X
L

Reset (Clear)
Load (Pn-Qn)
Count (Increment)
No Change (Hold)
No Change (Hold)

• For '162 only
H HIGH Voltage Level
L LOW Voltage Level
X = Immaterial

=
=

5-60

AC160 • ACT160 • AC162 • ACT162
Logic Diagram
P,

Po

CEP
CET

"~~
r~-'

[
I "62
I ONLY
1I
I
I

...

CP

~~

CP

II
lao

rI'

I
D
LCO

D
QQ

CP

----..J

I

L ___

~. 160

I

-

!,.,1TI~
1
I~I

~

,~

r-----r--

h

,...

Qo

i
I
II

:

~
r - r--

L..-...c

I

m
r--

DETAIL A

TC

r-

DETAIL A

DETAIL A

........

'-c

_ _ ~E!.A~~

•

i

SJi •162
00

Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate
propagation delays,

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Icc/Input (,ACT160/162)

1.6

160

5·61

74AC/ACT

Units

Conditions

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=WOrst Case

8.0

pA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = 25°C

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

80

AC160 • ACT160 • AC162 • ACT162
AC Characteristics

Symbol

Parameter

Vee·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

3.3

87

5.0

118

Max

Max

Units

Fig.

No.

Max

MHz

3·3

ns

3·6

tPHL

ns

3·6

tPLH

ns

3-6

ns

3·6

ns

3·6

ns

3·6

fmax

7.5
5.5

tPLH

tPHL

Propagation Delay
CP to Qn (15E Input LOW)

tPLH

Propagation Delay
CP to TC

3.3

tPHL

Propagation Delay
CP to TC

3.3
5.0

tPLH

Propagation Delay
CET to TC

3.3
5.0

7.5
5.5

3·6

tPHL

Propagation Delay
CET to TC

3.3
5.0

8.5
6.0

3-6

tPLH

Propagation Delay
MR to Qn ('AC160)

3.3

8.5
6.0

ns

3-6

tPHL

Propagation Delay
MR to Qn (,AC160)

3.3

8.5
6.0

ns

3·6

5.0

5.0
5.0

·Voltage Range 3.3 is 3.0 V ±0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein ani for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-62

..

~--~---

~~~~

AC160 • ACT160 • AC162 • ACT162
AC Operating Requirements
74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ns

3·9

th

ns

3·9

ts

ns

3·9

th

ns

3·9

ns

3·9

Symbol

Parameter

Vcc*
(V)

5.5
4.0

ts

ts

Setup Time,
HIGH or LOW
CEP or CET to CP

3.3
5.0

th

Hold Time, HIGH or LOW
CEP or CET to CP

3.3
5.0

-4.5
-3.0

3·9

tw

Clock Pulse Width (Load)
HIGH or LOW

3.3
5.0

3.0
2.0

3·6

tw

Clock Pulse Width
(Count)
HIGH or LOW

3.3
5.0

3.0
2.0

3·6

tw

MR Pulse Width, LOW
(,AC160)

3.3
5.0

4.5
3.0

ns

3-6

tree

Recovery Time
MR to CP (,AC160)

3.3
5.0

0
0

ns

3·9

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 Is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-63

•

AC160 • ACT160 • AC162 • ACT162
AC Characteristics

Vee·

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Units

Fig.
No.

118

MHz

3-3

5.5

ns

3-6

tPHL

ns

3-6

tPLH

ns

3-6

ns

3-6

Symbol

Parameter

74ACT

(V)

Min
5.0

fmax
tPLH

Typ

Max

Max

Max

tPHL

Propagation Delay
CP to an (PE" Input LOW)

tPLH

Propagation Delay
CP to TC

5.0

ns

3-6

tPHL

Propagation Delay
CP to TC

5.0

ns

3-6

tPLH

Propagation Delay
CET to TC

5.0

5.5

3-6

tPHL

Propagation Delay
CET to TC

5.0

6.0

3-6

Propagation Delay
(,ACT160)

5.0

6.0

ns

3-6

Propagation Delay
(,ACT160)

5.0

6.0

ns

3-6

tPLH

M"Fi" to an

tPHL

M"Fi" to an

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
Information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-64

AC160 • ACT160 • AC162 • ACT162
AC Operating Requirements

Symbol

Parameter

Vee·
(V)

/ '....
ts
"
th

ts

~~

74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

5.0

4.0

ns

3·9

~~,

-5.0

ns

3·9

ns

3·9

ns

3·9

ns

3-9

ns

3-9

n

HOld~J¥l~
I
...

Pn to

Setup Time,'J ~
HIGH or LOW
l'E or SA to CP (,AC 3~

V/

I!O /7/

';')

th

'J5E or SA to CP (,ACT162) ~{

ts

Setup Time,
HIGH OR LOW
'J5E or MR to CP (' ACT160

5.0

th

Hold Time, HIGH or LOW
PE or JiifFi to CP (' ACT160

5.0

-5.5

ts

Setup Time,
HIGH or LOW
CEP or CET to CP

5.0

2.5

th

Hold Time, HIGH or LOW
CEP or CET to CP

5.0

-3.0

~ Vns

3-9

tw

Clock Pulse Width (Load)
HIGH or LOW

5.0

2.0

ns

3-6

tw

Clock Pulse Width
(Count) HIGH or LOW

5.0

2.0

ns

3-6

tw

MR Pulse Width, LOW
(,ACT160)

5.0

3.0

ns

3-6

5.0

0

ns

3-9

tree

Hold Time, HIGH or LOW

Recovery Time

MR to CP (' ACT160)

iff) t1; /)
~(

4.0

'1/~ ~1
~I/?

G~

/".,

7/ ~

J!i)1

!)

t~

I> 3-9

·Voltage Range 5.0 Is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
Information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54n4AC/ACT

Units

Conditions

pF

Vcc=5.5 V

pF

Vcc=5.5 V

Typ
CIN

Input Capacitance

Cpo

Power Dissipation
Capacitance

4.5

5-65

•

AC161 • ACT161 • AC163 • ACT163
54AC/74AC161 • 54ACT/74ACT161
54AC/74AC163 • 54ACT/74ACT163
Synchronous Presettable Binary Counter
Connection Diagrams

Description
The 'ACI'ACT161 and 'ACI'ACT163 are high-speed
synchronous modul0-16 binary counters. They are
synchronously presettable for application in
programmable dividers and have two types of
Count Enable inputs plus a Terminal Count output
for versatility in forming synchronous multistage
counters. The 'ACI'ACT161 has an asynchronous
Master Reset input that overrides all other inputs
and forces the outputs LOW. The 'ACI'ACT163 has
a Synchronous Reset input that overrides counting
and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the
clock.
•
•
•
•
•

Synchronous Counting and Loading
High-Speed Synchronous Expansion
Typical Count Rate of 125 MHz
Outputs Source/Sink 24 mA
'ACT161 and 'ACT163 have TTL-Compatible Inputs

Pin Assignment
for DIP, Flatpak and SOIC

Po

Ordering Code: See Section 6
CEP

Ne

Pl

Po

[!J

[!]

NC

ITII

[j]

~ Vee

[j1]

~ TC

§][j§~5Il~

CP

03

02

Ne

0,

Do

Pin Assignment
for LCC

• J;m for '161
'163

• S"R" for

• MR for

'161
• ~ for '163

Pin Names
CEP
CET
CP
JXR" (,161)
SF{ (,163)
Po - P3

PE
Qo - Q3
TC

NC

PE~
CET

TC

CP

ill -il

GND~

Logic Symbol

CET

P2

[!][I][!][]J~

Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Asynchronous Master Reset Input
Synchronous Reset Input
Parallel Data Inputs
Parallel Enable Input
Flip-Flop Outputs
Terminal Count Output
5-66

AC161 • ACT161 • AC163 • ACT163
Functional Description
The 'ACI'ACT161 and 'ACI'ACT163 count in
modul0-16 binary sequence. From state 15 (HHHH)
they increment to state 0 (LLLL). The clock inputs
of all flip-flops are driven in parallel through a
clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the '161) occur as a
result of, and synchronous with, the LOW-to-HIGH
transition of the CP input signal. The circuits have
four fundamental modes of operation, in order of
precedence: asynchronpus reset (,161),
synchronous reset (,163), parallel load, count-up
and hold. Five control inputs-Master Reset (MR,
'161), Synchronous Reset ('S'Fi, '163), Parallel Enable
(PE), Count Enable Parallel (CEP) and Count Enable
Trickle (CET)-determine the mode of operation, as
shown in the Mode Select Table. A LOW signal on
MR overrides all other inputs and asynchronously
forces all outputs LOW. A LOW signal on SA
overrides counting and parallel loading and allows
all outputs to go LOW on the next rising edge of
CPo A LOW signal on PE overrides counting and
allows information on the Parallel Data (Pn) inputs
to be loaded into the flip-flops on the next rising
edge of CPo With l5E and MR (,161) or 'S'Fi ('163)

HIGH, CEP and CET permit counting when both
are HIGH. Conversely, a LOW signal on either CEP
or CET inhibits counting.
The 'ACI'ACT161 and 'ACI'ACT163 use Ootype edgetriggered flip-flops and changing the §i, ~, CEP
and CET inputs when the CP is in either state does
not cause errors, provided that the recommended
setup and hold times, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET
is HIGH and counter is in state 15. To implement
synchronous multistage counters, the TC outputs
can be used with the CEP and CET inputs in two
different ways. Please refer to the 'AC568 data
sheet. The TC output is subject to decoding spikes
due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous
reset for flip-flops, counters or registers.

=

Logic Equations: Count Enable CEP-CET-PE
TC = QO-Q1-Q2-Q3-CET

Mode Select Table

State Diagram
Action on the Rising

"SA J5E CET CEP Clock Edge (I)
L

X

X

H
H
H
H

L
H
H
H

X
H
L
X

X
X
H
X
L

Reset (Clear)
Load (Pn-Qn)
Count (Increment)
No Change (Hold)
No Change (Hold)

"For '163 only
H = HIGH Voltage Level
L =LOW Voltage Level
X = Immaterial

5-67

•

AC161 • ACT161 • AC163 • ACT163
Block Diagram
P,

Po

CEP
CET

l~C
rI
I
I
I

'--f--

'163

I~Y

CP

...

CP

r

r--~1
i'6':
ONLYI

1

(

1-1
c.
11+,0
L
o
11
1
a
: 06

'----<

J

1
1L ____

161
163

~

~

-,

0
a

t----ao

........LJ'

I
-

r---

~

TC

rI

r--DETAIL A

DETAIL A

OETAll A

_ _ _ DETAIL
____
A .J

..
0,

00

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays,

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Icc/Input (,ACT161/163)

1.6

160

5·68

74AC/ACT

Units

Conditions

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = 25°C

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

80

AC161 • ACT161 • AC163 • ACT163
AC Characteristics

Symbol

Parameter

Vee·
(V)

74AC161

54AC161

74AC161

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Min

Typ
87
118

fmax

tPLH

Max

Max

Units

Fig.
No.

MHz

3·3

ns

3·6

Max

tPHL

Propagation Delay
CP to Qn ('J5E Input
HIGH or LOW)

ns

3-6

tPLH

Propagation Delay
CP to TC

ns

3·6

tPHL

Propagation Delay
CP to TC

3.3
5.0

11.0
8.0

ns

3-6

tPLH

Propagation Delay
CET to TC

3.3
5.0

7.5
5.5

3·6

tPHL

Propagation Delay
CET to TC

3.3
5.0

8.5
6.0

3-6

Propagation Delay

lim to Qn

3.3
5.0

8.5
6.0

3-6

Propagation Delay
MR to TC

3.3
5.0

11.0
8.0

tPLH
tPHL

ns

3-6

·Voltage Range 3.3 is 3.0 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-69

•

AC161 • ACT161 • AC163 • ACT163
AC Operating Requirements

Symbol

Parameter

Vcc*
(V)

ts

jjijme,
rLOW
to
A.

th

~(j)0rLOW

ts

th

"set"p(rfinW!~
Pn to C

A

)

f'.....

HIGH or L
SR to CP

74AC161

54AC161

74AC161

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

3.3
5.0

5.5
4.0

ns

3·9

3.3
5.0

-7.0
-5.0

ns

3·9

ns

3·9

ns

3·9

ns

3·9

ns

3·9

WVA5

5.5
4.0

~

'"

Hold Time, HIGH 0'NJi)~
SA to CP
r--.. 0

~V

ts

Setup Time,
HIGH or LOW
PE to CP

th

Hold Time, HIGH or LOW
PE to CP

3.3
5.0

-7.5
-5.5

ts

Setup Time,
HIGH or LOW
CEP or CET to CP

3.3
5.0

3.5
2.5

th

Hold Time, HIGH or LOW
CEP or CET to CP

3.3
5.0

-4.5
-3.0

tw

Clock Pulse Width (Load)
HIGH or LOW

3.3
5.0

3.0
2.0

tw

Clock Pulse Width
(Count)
HIGH or LOW

3.3
5.0

tw

MR Pulse Width, LOW

tree

Recovery Time

MR to CP

3-:;
5.0

D

/'...

~vl,

v~

~

u~ ¥
~ns

/

'"

3·9

3·9

ns

3·6

3.0
2.0

ns

3-6

3.3
5.0

4.5
3.0

ns

3-6

3.3
5.0

0
0

ns

3·9

·Voltage Range 3.3 Is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
MIlitary parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·70

AC161 • ACT161 • AC163 • ACT163
AC Characteristics

Symbol

Parameter

Vcc·
(V)

74ACT161

54ACT161

74ACT161

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

MHz

3·3

Typ

5.0

115

125

Propagation Delay
CP to an (PE Input
HIGH or LOW)

5.0

1.0

5.5

9.5

1.0

10.5

ns

3·6

Propagation Delay
CP to an (PE Input
HIGH or LOW)

5.0

1.0

6.0

10.5

1.0

11.5

ns

3·6

tPLH

Propagation Delay
CP to TC

5.0

1.0

7.0

11.0

1.0

12.5

ns

3·6

tPHL

Propagation Delay
CP to TC

5.0

1.0

8.0

12.5

1.0

13.5

ns

3·6

tPLH

Propagation Delay
CET to TC

5.0

1.0

5.5

8.5

1.0

10.0

ns

3·6

tPHL

Propagation Delay
CET to TC

5.0

1.0

6.0

9.5

1.0

10.5

ns

3-6

tPHL

Propagation Delay
MR to an

5.0

1.0

6.0

10.0

1.0

11.0

ns

3-6

tPHL

Propagation Delay
MR to TC

5.0

1.0

8.0

13.5

1.0

14.5

ns

3-6

fmax

tPLH

tPHL

Max

Fig.
No.

Min
Maximum Count
Frequency

Max

Units

Max

100

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-71

•

AC161 • ACT161 • AC163 • ACT163
AC Operating Requirements

Symbol

Parameter

Vcc·
(V)

74ACT161

54ACT161

74ACT161

TA= +25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Setup Time,
HIGH or LOW
Pn to CP

5.0

4.0

9.5

11.5

ns

3·9

th

Hold Time, HIGH or LOW
Pn to CP

5.0

-5.0

0

0

ns

3·9

ts

Setup Time,
HIGH or LOW
MR to CP

5.0

4.0

8.5

9.5

ns

3·9

th

Hold Time, HIGH or LOW
MR to CP

5.0

-5.5

-0.5

-0.5

ns

3·9

ts

Setup Time
HIGH or LOW
PE to CP

5.0

4.0

8.5

9.5

ns

3·9

th

Hold Time, HIGH or LOW
PE to CP

5.0

-5.5

-0.5

-0.5

ns

3·9

ts

Setup Time,
HIGH or LOW
CEP or CET to CP

5.0

2.5

5.5

6.5

ns

3·9

th

Hold Time, HIGH or LOW
CEP or CET to CP

5.0

-3.0

0

0

ns

3·9

tw

Clock Pulse Width (Load)
HIGH or LOW

5.0

2.0

3.0

3.5

ns

3·6

tw

Clock Pulse Width
(Count) HIGH or LOW

5.0

2.0

3.0

3.5

ns

3·6

tw

MR Pulse Width, LOW

5.0

3.0

3.0

7.5

ns

3·6

tree

Recovery Time
MR to CP

5.0

0

0

0.5

ns

3·6

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

45.0

pF

Vcc=5.5 V

5·72

AC161 • ACT161 • AC163 • ACT163
AC Characteristics

Symbol

Parameter

Vee·
(V)

74AC163

54AC163

74AC163

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Units

Fig.
No.

MHz

3·3

Max

60

fmax

Maximum Count
Frequericy

3.3
5.0

70
110

87
118

tPLH

Propagation Delay
CP to an (PE Input
HIGH or LOW)

3.3
5.0

1.0
1.0

7.5
5.5

12.5
9.0

1.0
1.0

13.5
9.5

ns

3-6

tPHL

Propagation Delay
CP to an (PE Input
HIGH or LOW)

3.3
5.0

1.0
1.0

8.5
6.0

12.0
9.5

1.0
1.0

13.0
10.0

ns

3-6

tPLH

Propagation Delay
CP to TC

3.3
5.0

1.0
1.0

9.5
7.0

15.0
10.5

1.0
1.0

16.5
11.5

ns

3·6

tPHL

Propagation Delay
CP to TC

3.3
5.0

1.0
1.0

11.0
8.0

14.0
11.0

1.0
1.0

15.5
11.5

ns

3-6

tPLH

Propagation Delay
CET to TC

3.3
5.0

1.0
1.0

7.5
5.5

9.5
6.5

1.0
1.0

11.0
7.5

ns

3·6

tPHL

Propagation Delay
CET to TC

3.3
5.0

1.0
1.0

8.5
6.0

11.0
8.5

1.0
1.0

12.5
9.5

ns

3-6

95

'Voltage Range 3.3 is 3.0 V:t 0.3 V
Voltage Range 5.0 Is 5.0 V:t 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·73

•

AC161 • ACT161 • AC163 • ACT163
AC Operating Requirements

Symbol

Parameter

Vee·
(V)

74AC163

54AC163

74AC163

TA= + 25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Setup Time,
HIGH or LOW
Pn to CP

3.3
5.0

5.5
4.0

13.5
8.5

16.0
10.5

ns

3-9

th

Hold Time, HIGH or LOW
Pn to CP

3.3
5.0

-7.0
-5.0

-1.0
0

-0.5
0

ns

3-9

ts

Setup Time,
HIGH or LOW
SR to CP

3.3
5.0

5.5
4.0

14.0
9.5

16.5
11.0

ns

3-9

th

Hold Time, HIGH or LOW
SR to CP

3.3
5.0

-7.5
-5.5

-1.0
-0.5

-0.5
0

ns

3-9

ts

Setup Time,
HIGH or LOW
PE to CP

3.3
5.0

5.5
4.0

11.5
7.5

14.0
8.5

ns

3-9

th

Hold Time, HIGH or LOW
PE to CP

3.3
5.0

-7.5
-5.0

-1.0
-0.5

-0.5
0

ns

3-9

ts

Setup Time,
HIGH or LOW
CEP or CET to CP

3.3
5.0

3.5
2.5

6.0
4.5

7.0
5.0

ns

3-9

th

Hold Time, HIGH or LOW
CEP or CET to CP

3.3
5.0

-4.5
-3.0

0
0

0
0.5

ns

3-9

tw

Clock Pulse Width (Load)
HIGH or LOW

3.3
5.0

3.0
2.0

3.5
2.5

4.0
3.0

ns

3-6

tw

Clock Pulse Width
(Count)
HIGH or LOW

3.3
5.0

3.0
2.0

4.0
3.0

4.5
3.5

ns

3-6

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-74

AC161 • ACT161 • AC163 • ACT163
AC Characteristics

Symbol

Parameter

Vcc·
(V)

74ACT163

54ACT163

74ACT163

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Maximum Count
Frequency

5.0

120

128

Propagation Delay
CP to an (PE Input
HIGH or LOW)

5.0

1.0

5.5

10.0

1.0

Propagation Delay
CP to an (PI: Input
HIGH or LOW)

5.0

1.0

6.0

11.0

tPLH

Propagation Delay
CP to TC

5.0

1.0

7.0

tPHL

Propagation Delay
CP to TC

5.0

1.0

tPLH

Propagation Delay
CET to TC

5.0

tPHL

Propagation Delay
CET to TC

5.0

fmax

tPLH

tPHL

Units

Fig.
No.

Max

105

MHz

3·3

11.0

ns

3·6

1.0

12.0

ns

3·6

11.5

1.0

13.5

ns

3·6

8.0

13.5

1.0

15.0

ns

3·6

1.0

5.5

9.0

1.0

10.5

ns

3·6

1.0

6.0

10.0

1.0

11.0

ns

3·6

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing informa·
tion please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·75

•

AC161 • ACT161 • AC163 • ACT163
AC Operating Requirements

Symbol

Parameter

Vee·
(V)

74ACT163

54ACT163

74ACT163

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Setup Time,
HIGH or LOW
Pn to CP

5.0

4.0

10.0

12.0

ns

3·9

th

Hold Time, HIGH or LOW
Pn to CP

5.0

-5.0

0.5

0.5

ns

3·9

ts

Setup Time,
HIGH or LOW
SA to CP

5.0

4.0

10.0

11.5

ns

3·9

Hold Time, HIGH or LOW
CP

5.0

-5.5

-0.5

-0.5

ns

3·9

ts

Setup Time
HIGH or LOW
PE to CP

5.0

4.0

8.5

10.5

ns

3·9

th

Hold Time, HIGH or LOW
PE to CP

5.0

-5.5

-0.5

0

ns

3·9

ts

Setup Time,
HIGH or LOW
CEP or CET to CP

5.0

2.5

5.5

6.5

ns

3·9

th

Hold Time, HIGH or LOW
CEP or CET to CP

5.0

-3.0

0

0.5

ns

3·9

tw

Clock Pulse Width
HIGH or LOW

5.0

2.0

3.5

3.5

ns

3·6

tw

Clock Pulse Width
(Count) HIGH or LOW

5.0

2.0

3.5

3.5

ns

3·6

th

SA to

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

45.0

pF

Vcc=5.5 V

5·76

AC168 • AC169
54AC/74AC168 • 54AC/74AC169
4-Stage Synchronous Bidirectional Counters
Description

Connection Diagrams

The 'AC168 and 'AC169 are fully synchronous
4-stage up/down counters. The 'AC168 is a BCD
decade counter; the 'AC169 is a modul0-16 binary
counter. Both feature a preset capability for
programmable operation, carry lookahead for easy
cascading and a uil:) input to control the direction
of counting. All state changes, whether in counting
or parallel loading, are initiated by the LOW-toHIGH transition of the Clock.
•
•
•
•

Synchronous Counting and Loading
Built-In Lookahead Carry Capability
Presetlable for Programmable Operation
Outputs Source/Sink 24 mA
Pin Assignment
for DIP, Flatpak and SOIC

Ordering Code: See Section 6

P3

P2

Ne

Pl

Po

[!]ml!l[]]~

Logic Symbol
CEP

rn

[!]

NC

CEP
CEl
CP

II]

ITII

~vcc

CET ~

[j!]fC

lC
1HI1!§~11Il~
Q3

Pin Names
CP
Po - P3

'J5E
Uil:)

Qo - Q3

'fC

Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Parallel Data Inputs
Parallel Enable Input
Up-Down Count Control Input
Flip-Flop Outputs
Terminal Count Output

5-77

NC

i'E~

Q2

Ne 01

00

Pin Assignment
for LCC

CEP
CET

CP

ill UfO

GND ~

•

AC168 • AC169
Logic Diagrams

'AC168

,-

l]
~
(j[ ~
1
itT
0-

,,--1
1
1

--

----~

1
1

I
1.1. ....

1
1
1

1

1

i=

t-t-

Uti)
UP

..

~ 4-,
I--'

'I'

CP

I~

~I
1'
1
,1
,

:~

......

r--;

T

,AAFi

1
1
1

I .....
-"

I(j

A

r

~

T

1

CP

P3

~

~

-

CET

p.

P,

Po

PE->.

CEP"

CP :

1
1

,
1

I

.,
~,

LD

HJ.

TC

~

Ir=1

-.,..

T

I--

BT

r-

BF
UP
DN
DETAIL A
ENF

-

tr

I-DETAIL A

-

CP

0==

I-DETAIL A

r-

Q

~i

'"I

,

___ 9_J

L _______

~~

~~

~

0,

00

~~

O.

03

Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

'AC169
-

~
CEP~

-w

'r--- -

CET

T

1
1
1
1

~

-

~I

1

CP

..

,...

:J
~

t-t-

:~
I~

L __

1
1
1

ml

ZI
",
~ =b
1
1

'T

CP :

1
1

I

"I

~,

I

-~

LD

i~r
BTl--

I--

BFt--

I--

UP
DN
DETAIL A
ENF

r=

DETAIL A

-

CP

0==

c===3

t---I 1.

TC

~

rr=I

ll::

T

1

UP

1
1
1 CP
1
1
1
1
1

~AF,

P3

r

AT'

1

1
1
1
1
1
1
1
1
1
1

p.

P,

Po

PE ->.

t---

I--DETAIL A

W

I---

Q

;::1

·1

---t - -o- - 1
I

~7

00

~7

~7

0,

02

~7

03

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5·78

AC168 • AC169
State Diagrams

Functional Description
The 'AC168 and 'AC169 use edge-triggered J-K-type
flip-flops and have no constraints on changing the
control or data input signals in either state of the
Clock. The only requirement is that the various
inputs attain the desired state at least a setup time
before the rising edge of the clock and remain
valid for the recommended hold time thereafter.
The parallel load operation takes precedence over
the other operations, as indicated in the Mode
Select Table. When PE is LOW, the data on the
PO-P3 inputs enters the flip-flops on the next rising
edge of the Clock. In order for counting to occur,
both CEP and CET must be LOW and PE must be
HIGH; the UfO input then determines the direction
of counting. The Terminal Count (i'e) output is
normally HIGH and goes LOW, provided that CET
is LOW, when a counter reaches zero in the Count
Down mode or reaches 9 (15 for the 'AC169) in the
Count Up mode. The TC output state is not a
function of the Count Enable Parallel (CEP) input
level. The TC output of the 'AC168 decade counter
can also be LOW in the illegal states 11, 13 and 15,
which can occur when power is turned on or via
parallel loading. If an illegal state occurs, the
'AC169 will return to the legitimate sequence
within two counts. Since the TC signal is derived
by decoding the flip-flop states, there exists the
possibility of decoding spikes on TC. For this
reason the use of TC as a clock signal is not
recommended (see logic equations below).

'AC168

- - - Count Down
CountUp

'AC169

1) Count Enable =CEPeCETePE
2) Up: (,AC168): TC =Qoe01.Q2 e03 e(Up)eCET
(' AC169): fC' = QoeQ1 eQ2 eQ3 e(Up)eCET
3) Down (both): TC =Ooe01 e02 e03 e(Down)eCET

- - - Count Down
Count Up
-

Mode Select Table
Action on Rising
Clock Edge

L
H
H
H
H

X

X

L
L
H

L
L
X

X

H

X
H
L
X
X

Load (Pn to Qn)
Count Up (Increment)
Count Down (Decrement)
No Change (Hold)
No Change (Hold)

H =HIGH Voltage Level
L =LOW Voltage Level
X =Immaterial

5-79

•

AC168 • AC169
DC Characteristics (unless otherwise specified)
54AC

Parameter

Symbol

Units

74AC

Conditions

Icc

Maximum Quiescent
Supply Current

160

80

p,A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

8.0

8.0

p,A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

AC Characteristics

Parameter

Vce·
(V)

74AC168

54AC168

74AC168

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Units

Fig.
No.

Max

fmax

118
154

MHz

3·3

tPLH

9.5
7.0

ns

3·6

tPHL

Propagation Delay
CP to Qn
(Pi: HIGH or LOW)

ns

3·6

tPLH

Propagation Delay
CP to fC

ns

3·6

tPHL

Propagation Delay
CP to fC

3.3
5.0

ns

3·6

Propagation Delay

3.3
5.0

11.0
8.0

3·6

GET to fC

3.3
5.0

9.5
7.0

3·6

Propagation Delay
UfO to TC

3.3
5.0

10.5
7.5

ns

3·6

Propagation Delay

3.3
5.0

9.0
6.5

ns

3·6

tPLH
tPHL
tPLH
tPHL

~tofC

Propagation Delay

UfO to fC

'Voltage Range 3.3 Is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·80

AC168 • AC169
AC Operating Requirements

Symbol

Parameter

Vcc·
(V)

Z

Se~p

ts
i

th

ts

Time,
~ cqr LOW

'(,

i\

.( jtOi(U:·
f4'Pn to C,

iG~r LOW
.?~.'. ~j . / ......

th

"l

54AC168

74AC168

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum
ns

3·9

3.3
5.0

1.5
0.5

ns

3·9

ns

3·9

ns

3·9

ns

3·9

ns

3·9

[~",ns

3·9

Il ;/

Hold Time, HIGH 0(b0V/ /3.3
CEP to C P ' " ,~.Q,

7.5
4.5
:".

/4:~~
/fi·
f

l. Vl

3.3
5.0

th

Hold Time, HIGH or LOW
CET to CP

3.3
5.0

6.0
4.0

ts

Setup Time,
HIGH or LOW
PE to CP

3.3
5.0

3.5
2.0

th

Hold Time, HIGH or LOW
PE to CP

3.3
5.0

3.5
1.5

Setup Time,
HIGH or LOW
ufO to CP

3.3
5.0

ufo to CP

Hold Time, HIGH or LOW

CP Pulse Width,
HIGH or LOW

ts

th
tw

Fig.
No.

3.0
1.5

Setup Time,
HIGH or LOW
CET to CP

ts

Units

3.3
5.0

r·) ;k3,
s.tuplrftn~
HIGH or L
/~~~;
/5,6
CEP to CP

74AC168

I

i~~~

« !
.O(

/')

tl/.,~ ~1'1

"'/<>~:

v,~

~./

3·9

12.5
9.0

ns

3·9

3.3
5.0

7.0
4.0

ns

3·9

3.3
5.0

2.0
2.0

ns

3·6

I

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·81

•

AC168 • AC169
AC Characteristics

Symbol

Parameter

Vcc*
(V)

74AC169

54AC169

74AC169

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Fig.
No.

MHz

3-3

Max

fmax

Maximum Clock
Frequency

3.3
5.0

75
100

118
154

tPLH

Propagation Delay
CP to an
(PE HIGH or LOW)

3.3
5.0

1.0
1.0

9.5
7.0

13.0
10.0

1.0
1.0

16.0
12.0

1.0
1.0

14.5
11.0

ns

3-6

tPHL

Propagation Delay
CP to an
(PE HIGH or LOW)

3.3
5.0

1.0
1.0

10.5
7.5

14.5
11.0

1.0
1.0

17.5
13.0

1.0
1.0

16.0
12.0

ns

3-6

tPLH

Propagation Delay
CP to 'fC

3.3
5.0

1.0
1.0

13.5
9.5

18.0
13.0

1.0
1.0

22.5
16.0

1.0
1.0

22.0
14.0

ns

3-6

tPHL

Propagation Delay
CP to TC

3.3
5.0

1.0
1.0

13.5
9.5

18.0
13.0

1.0
1.0

23.0
16.0

1.0
1.0

20.5
14.5

ns

3-6

tPLH

Propagation Delay
CET to TC

3.3
5.0

1.0
1.0

11.0
8.0

15.0
10.5

1.0
1.0

18.5
13.0

1.0
1.0

16.5
12.0

ns

3-6

tPHL

Propagation Delay
CET to 'fC

3.3
5.0

1.0
1.0

9.5
7.0

12.5
9.0

1.0
1.0

16.0
11.5

1.0
1.0

14.5
10.0

ns

3-6

uio to 'fC

Propagation Delay

3.3
5.0

1.0
1.0

11.0
8.0

15.0
10.5

1.0
1.0

19.0
13.5

1.0
1.0

17.0
12.0

ns

3-6

Propagation Delay
to TC

3.3
5.0

1.0
1.0

10.0
7.0

13.5
9.5

1.0
1.0

17.0
12.0

1.0
1.0

15.5
10.5

ns

3-6

tPLH
tPHL

uio

55
75

Units

65
90

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-82

AC168 • AC169
AC Operating Requirements

Symbol

Parameter

Vcc·
(V)

74AC169

54AC169

74AC169

TA=+25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA=-40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Setup Time,
HIGH or LOW
Pn to CP

3.3
5.0

3.0
1.5

4.5
2.5

6.0
3.0

5.0
2.5

ns

3·9

th

Hold Time, HIGH or LOW
Pn to CP

3.3
5.0

1.5
0.5

0.5
1.5

0.5
1.5

0.5
1.5

ns

3·9

ts

Setup Time,
HIGH or LOW
GEP to CP

3.3
5.0

7.5
4.5

10.5
7.0

14.0
9.0

12.5
8.0

ns

3·9

th

Hold Time, HIGH or LOW
GEP to CP

3.3
5.0

4.5
2.0

0
0.5

0.5
1.0

0
1.0

ns

3·9

ts

Setup Time,
HIGH or LOW
GET to CP

3.3
5.0

7.0
4.0

10.0
6.5

13.5
9.0

12.0
8.0

ns

3-9

th

Hold Time, HIGH or LOW
GET to CP

3.3
5.0

6.0
4.0

0
0.5

0.5
1.0

0
1.0

ns

3-9

ts

Setup Time,
HIGH or LOW
PE to CP

3.3
5.0

3.5
2.0

5.5
3.5

7.0
4.5

6.5
4.0

ns

3-9

th

Hold Time, HIGH or LOW
PE to CP

3.3
5.0

3.5
1.5

0
0.5

0
0.5

0
0.5

ns

3-9

ts

Setup Time,
HIGH or LOW
Uio to CP

3.3
5.0

7.0
4.5

10.0
6.5

13.0
8.5

11.5
7.5

ns

3-9

ufo to CP

3.3
5.0

7.0
4.0

0
0.5

0
0.5

0
0.5

ns

3-9

CP Pulse Width,
HIGH or LOW

3.3
5.0

2.0
2.0

3.0
3.0

5.0
5.0

4.0
3.0

ns

3-6

th
tw

Hold Time, HIGH or LOW

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-83

•

AC168 • AC169
Capacitance
Symbol

Parameter

CIN

Input Capacitance

Cpo

Power Dissipation
Capacitance

54174AC

Units

Conditions

4.5

pF

Vcc=5.5 V

60.0

pF

Vcc=5.5 V

Typ

5·84

AC174 • ACT174
54AC/74AC174 • 54ACT/74ACT174
Hex D Flip-Flop With Master Reset
Connection Diagrams

Description
The 'ACI'ACT174 is a high-speed hex D flip-flop.
The device is used primarily as a 6-bit edgetriggered storage register. The information on the
D inputs is transferred to storage during the LOWto-HIGH clock transition. The device has a Master
Reset to simultaneously clear all flip-flops.
• Outputs Source/Sink 24 mA
• 'ACT174 has TTL-Compatible Inputs

Ordering Code: See Section 6

Pin Assignment
for DIP, Flatpak and SOIC

Logic Symbol

D2

01

Ne

01

Do

[!][!][!][!][!]

a, [!]

cp

[!lao

I1lMii

GND~
NC

MR

ffil

[j]

~vcc

a3~

IW as
~1j]~1!!l1Thl
03 Q4 He 04 Os

Pin Assignment
for LeC

Pin Names

Do - D5
CP

M1=i
Qo - Q5

Data Inputs
Clock Pulse Input
Master Reset Input
Outputs

5-85

NC

CP~

•

AC174 • ACT174
Functional Description

Truth Table

The 'ACI'ACT174 consists of six edge-triggered 0
flip-flops with individual 0 inputs and Q outputs.
The Clock (CP) and Master Reset ("M"R) are common
to all flip-flops. Each 0 input's state is transferred
to the corresponding flip-flop's output following
the LOW-to-HIGH Clock (CP) transition. A LOW
input to the Master Reset (MR) will force all
outputs LOW independent of Clock or Oata inputs.
The 'ACI'ACT174 is useful for applications where
the true output only is required and the Clock and
Master Reset are common to all storage elements.

Inputs

Output

MR

CP

0

Q

L
H
H
H

X
I
I
L

X
H
L
X

L
H
L
Q

H = HIGH Voltage Level
L= LOW Voltage Level
X = Immaterial
I= LOW-to-HIGH Transition of Clock

Logic Diagram
MR

CP

0,

05

Do

a,

05

00

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

74AC/ACT

Units

Conditions

Icc

Maximum Quiescent
Supply Current

160

80

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

8.0

8.0

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = 25°C

ICCT

Maximum Additional
Iccllnput (,ACT174)

1.6

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V
TA = Worst Case

5-86

AC174 • ACT174
AC Characteristics

Symbol

Parameter

Vcc*
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Units

Fig.
No.

MHz

3·3

Max

fmax

Maximum Clock
Frequency

3.3
5.0

90
100

100
125

tPLH

Propagation Delay
CP to an

3.3
5.0

1.0
1.0

9.0
6.0

11.5
8.5

1.0
1.0

14.0
10.5

1.0
1.0

12.5
9.5

ns

3·6

tPHL

Propagation Delay
CP to an

3.3
5.0

1.0
1.0

8.5
6.0

11.0
8.0

1.0
1.0

13.0
10.0

1.0
1.0

12.0
9.0

ns

3-6

tPHL

Propagation, Delay
MR to an

3.3
5.0

1.0
1.0

9.0
7.0

11.5
9.0

1.0
1.0

13.5
11.0

1.0
1.0

12.5
10.5

ns

3-6

65
90

70
100

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

•

AC Operating Requirements

Symbol

Parameter

Vcc*
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Set-up Time,
HIGH or LOW
Dn to CP

3.3
5.0

2.5
2.0

6.5
5.0

7.5
5.5

7.0
5.5

ns

3-9

th

Hold Time, HIGH or LOW
Dn to CP

3.3
5.0

1.0
0.5

3.0
3.0

3.0
3.0

3.0
3.0

ns

3-9

tw

MR Pulse Width, LOW

3.3
5.0

1.0
1.0

5.5
5.0

7.0
5.0

7.0
5.0

ns

3-6

tw

CP Pulse Width

3.3
5.0

1.0
1.0

5.5
5.0

7.0
5.0

7.0
5.0

ns

3-6

tree

Recovery Time
MR to CP

3.3
5.0

0
0

2.5
2.0

3.0
2.0

2.5
2.0

ns

3-6

'Voltage Range 3.3 Is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
MIlitary parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-87

AC174 • ACT174
AC Characteristics

Parameter

Symbol

Vcc·
(V)

74ACT

54ACT

74ACT

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Units

Fig.
No.

MHz

3·3

Max

fmax

Maximum Clock
Frequency

5.0

165

200

tPLH

Propagation Delay
CP to On

5.0

1.0

7.0

10.5

1.0

11.5

1.0

11.5

ns

3·6

tPHL

Propagation Delay
CP to On

5.0

1.0

7.0

10.5

1.0

11.0

1.0

11.5

ns

3·6

tPHL

Propagation Delay
MR to On

5.0

1.0

6.5

9.5

1.0

12.0

1.0

11.0

ns

3-6

Units

Fig.
No.

140

95

'Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements

Symbol

Parameter

Vcc·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum

ts

Set-up Time,
HIGH or LOW
Dn to CP

5.0

0.5

1.5

1.5

1.5

ns

3-9

th

Hold Time, HIGH or LOW
Dn to CP

5.0

1.0

2.0

2.0

2.0

ns

3-9

tw

MR Pulse Width, LOW

5.0

1.5

3.0

5.0

3.5

ns

3-6

tw

CP Pulse Width
HIGH or LOW

5.0

1.5

3.0

5.0

3.5

ns

3-6

tree

Recovery Time
MR to CP

5.0

-1.0

0.5

0.5

0.5

ns

3-6

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

54/74ACT

Parameter

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

85.0

pF

Vcc=5.5 V

5-88

AC175 • ACT175
54AC/74AC175 • 54ACT/74ACT175
Quad D Flip-Flop
Connection Diagrams

Description
The 'ACI'ACT175 is a high-speed quad D flip-flop.
The device is useful for general flip-flop
requirements where clock and clear inputs are
common. The information on the D inputs is stored
during the LOW-to-HIGH clock transition. Both true
and complemented outputs of each flip-flop are
provided. A Master Reset input resets all flip-flops,
independent of the Clock or D inputs, when LOW.
•
•
•
•
•
•

Edge-Triggered D-Type Inputs
Buffered Positive Edge-Triggered Clock
Asynchronous Common Reset
True and Complement Output
Outputs Source/Sink 24 mA
'ACT175 has TTL-Compatible Inputs

Pin Assignment
for DIP, Flatpak and SOIC

Ordering Code: See Section 6

0,

0,

NC

Do

Q()

[IJ[IJ[!][!][!]

Logic Symbol

cp

Do

0,

Q,

I1J

rn

GNO

[OJ

[I]MA

NC

Ii]

[jJ Ne

CP

Ii]

@

Q,

[i]

~Q,

~[iS][16][i7][iS]
02

02

NC

03

03

Pin Assignment
for LCC

Pin Names
Do - D3
CP
MR
00 - 03
03 - 03

Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs

5-89

Q"

Vee

•

AC175 • ACT175
Functional Description

Truth Table

The 'ACI'ACT175 consists of four edge-triggered D
flip-flops with individual D inputs and a and Q
outputs. The Clock and Master Reset are common.
The four flip-flops will store the state of their
individual D inputs on the LOW-to-HIGH clock (CP)
transition, causing individual a and Q outputs to
follow. A LOW input on the Master Reset (MR) will
force all a outputs LOW and Q outputs HIGH
independent of Clock or Data inputs. The
'ACI'ACT175 is useful for general logic applications
where a common Master Reset and Clock are
acceptable.

Inputs

Outputs

@tn, MR=H

@tn+1

Dn

an

an

L
H

L
H

H
L

H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit Time before Clock Pulse
tn+1 = Bit Time after Clock Pulse

Logic Diagram
Do

~ 7

c

'--

~

0

CP

co

a

-

0

0-

1

-

0

'----0 CP

a

~

0

P-

CD

1

'--

0

0

---0 CP 0
CD

1

~

p-

'--

L-o

0

0

CP 0
CD

0-

I
00 00

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-90

AC175 • ACT175
DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Icc/lnput (,ACT175)

1.6

74AC/ACT

160

Units

Conditions

p,A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

80

AC Characteristics
74AC

54AC

74AC

TA= +25°C
Cl=50 pF

TA=-55°C
to + 125°C
Cl=50 pF

TA=-40°C
to + 85°C
Cl=50 pF

Min

Min

Max
fmax
tPHl

Propagation Delay
CP to Qn or On

tPlH

Propagation Delay
CP to Qn or On

3.3
5.0

tPHl

Propagation Delay
MR to Qn

3.3
5.0

7.5
5.5

tPlH

Propagation Delay
MR to On

3.3
5.0

8.5
6.0

Max

Units

Fig.
No.

MHz

3·3

ns

3·6

Max

3-6
,;'It

,3:6
,d
f

I

nS~'/

3·6

·Voltage Range 3.3 is 3.0 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·91

•

AC175 • ACT175
AC Operating Requirements

Vee·
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Units

Fig.
No.

ns

3·9

ns

3·9

Guaranteed Minimum
ts
On to CP
th
tw

CP Pulse Width
HIGH or LOW

3.3
5.0

tw

MR Pulse Width, LOW

3.3
5.0

5.5
4.0

tree

Recovery Time
MR to CP

3.3
5.0

0
0

3·6
%";?

r 3.6

3·9

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Characteristics

Symbol

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Units

Fig.
No.

MHz

3·3

Max

fmax

Maximum Clock
Frequency

5.0

175

160

tPLH

Propagation Delay
CP to an or an

5.0

1.0

6.0

10.0

1.0

11.5

1.0

11.0

ns

3·6

tPHL

Propagation Delay
CP to an or an

5.0

1.0

7.0

11.0

1.0

13.0

1.0

12.0

ns

3·6

tPLH

Propagation Delay
MR to an

5.0

1.0

6.0

9.5

1.0

11.5

1.0

10.5

ns

3·6

tPHL

Propagation Delay
MR to an

5.0

1.0

5.5

9.5

1.0

11.0

1.0

10.5

ns

3·6

145

95

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·92

AC175 • ACT175
AC Operating Requirements

Symbol

Vcc*
(V)

54ACT

74ACT

TA= +25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

Setup Time
Dn to CP

5.0

3.0
3.0

2.0
2.5

2.5
3.0

2.0
2.5

ns

3-9

th

Hold Time, HIGH or LOW
Dn to CP

5.0

0

1.0

1.0

1.0

ns

3-9

tw

CP Pulse Width
HIGH or LOW

5.0

4.0

3.0

5.0

3.5

ns

3-6

t8

(H)
(L)

Parameter

74ACT

tw

MR Pulse Width, LOW

5.0

4.0

3.5

5.0

4.0

ns

3-6

tree

Recovery Time, MR to CP

5.0

0

0

0.5

0

ns

3-9

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

CPD

Power Dissipation
Capacitance

45.0

pF

Vcc=5.5 V

5-93

•

AC190 • AC191
54AC/74AC190 • 54AC/74AC191
Up/Down Counters with Preset and Ripple Clock
Connection Diagrams

Description
The 'AC190 is a reversible BCD (8421) decade
counter. The 'AC191 is a reversible modulo 16
binary counter. Both feature synchronous counting
and asynchronous presetting. The preset feature
allows the 'AC190 and 'AC191 to be used in
programmable dividers. The Count Enable input,
the Terminal Count output and the Ripple Clock
output make possible a variety of methods of
implementing multistage counters. In the counting
modes, state changes are initiated by the rising
edge of the clock.
•
•
•
•
•

High·speed-120 MHz Typical Count Frequency
Synchronous Counting
Asynchronous Parallel Load
Cascadable
Outputs Source/Sink 24 mA

Pin Assignment
for DIP, Flatpak and SOIC
0, UfO NC CE 00

[!]12l[!][!][iJ

Ordering Code: See Section 6
03[]]

mO,

GND~

[IjP,
[i] NC

NCITIl

Logic Symbol

P3[j]]

~Vcc

P,[i]

~po

~~[i6][17][i6]
PL Po p,

UfO

l'[

p, P3
RC

Pin Assignment
for LCC

CE
CP

TC NC RC CP

TC

Pin Names
Count Enable Input
CP
Clock Pulse Input
Po - P3
Parallel Data Inputs
J5[
Asynchronous Parallel Load Input
Ufo
Up/Down Count Control Input
00 - 03
Flip-Flop Outputs
RC
Ripple Clock Output
TC
Terminal Count Output

CE

5·94

AC190 • AC191
Mode Select Table

Functional Description
The 'AC190l'AC191 are synchronous up/down
counters. The 'AC190 is a BCD decade counter
while the 'AC191 is organized as a 4-bit binary
counter. Both contain four edge·triggered flip-flops
with internal gating and steering logic to provide
individual preset, count·up and count-down
operations.

Inputs

Mode

PL CE UID CP
H
H
L
H

Each circuit has an asynchronous parallel load
capability permitting the counter to be preset to
any desired number. When the Parallel Load (PL)
input is LOW, information present on the Parallel
Load inputs (Po - P3) is loaded into the counter and
appears on the Q outputs. This operation overrides
the counting functions, as indicated in the Mode
Select Table.

L
L
X
H

L
H
X
X

I
I
X
X

Count Up
Count Down
Preset (Asyn.)
No Change (Hold)

RC Truth Table
Inputs

A HIGH signal on the CE input inhibits counting.
When
is LOW, internal state changes are
initiated synchronously by the LOW-to·HIGH
transition of the clock input. The direction of
counting is determined by the iJlD input signal, as
indicated in the Mode Select Table. CE and iJlD
can be changed with the clock in either state,
provided only that the recommended setup and
hold times are observed.

cr

Outputs

CE

TC·

CP

RC

L
H
X

H
X
L

"l..r

"l..r

X
X

H
H

*TC IS generated Internally
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
I= LOW·to·HIGH Transition

Two types of outputs are provided as overflow/
underflow indicators. The terminal count (TC)
output is normally LOW. It goes HIGH when the
circuits reach zero in the count down mode or
9 CAC190) or 15 (,AC191) in the count up mode.
The TC output will then remain HIGH until a state
change occurs, whether by counting or presetting
or until UID is changed. The TC output should not
be used as a clock signal because it is subject to
decoding spikes.

State Diagram

The TC signal is also used internally to enable the
Ripple Clock (RC) output. The RC output is
normally HIGH. When CE is LOW and TC is HIGH,
RC output will go LOW when the clock next goes
LOW and will stay LOW until the clock goes HIGH
again. This feature simplifies the design of
multistage counters, as indicated in Figures a and
b. In Figure a, each RC output is used as the clock
input for the next higher stage. This configuration
is particularly advantageous when the clock source
has a limited drive capability, since it drives only
the first stage. To prevent counting in all stages it
is only necessary to inhibit the first stage, since a
HIGH signal on CE inhibits the RC output pulse, as
indicated in the RC Truth Table. A disadvantage of

COUNT UP
..
COUNT DOWN ._-_

5·95

•

AC190 • AC191
this configuration, in some applications, is the
timing skew between state changes in the first and
last stages. This represents the cumulative delay
of the clock as it ripples through the preceding
stages.

goes HIGH. There is no such restriction on the
HIGH state duration of the clock, since the RC
output of any device goes HIGH shortly after its
CP input goes HIGH.
The configuration shown in Figure c avoids ripple
delays and their associated restrictions. The CE
input for a given stage is formed by combining the
TC signals from all the preceding stages. Note that
in order to inhibit counting an enable signal must
be included in each carry gate. The simple inhibit
scheme of Figures a and b doesn't apply, because
the TC output of a given stage is not affected by
its own CEo

A method of causing state changes to occur
simultaneously in all stages is shown in Figure b.
All clock inputs are driven in parallel and the RC
outputs propagate the carry/borrow signals in
ripple fashion. In this configuration the LOW state
duration of the clock must be long enough to allow
the negative-going edge of the carry/borrow signal
to ripple through to the last stage before the clock

Figure a: N·Stage Counter Using Ripple Clock

O~R~~;~~~ -~--------r--------~----RC 0-- - -

CLOCK

----t::._..J

Figure b: Synchronous N·Stage Counter Using Ripple Carry/Borrow

O~~~~~~_~

_ _ _ _ _ _ _~_ _ _ _ _ _ _~_ _ _ ____

DID

U/o
ENABlE~CE

'----ojCE

CP

CP

RC 0-- - -

CLOCK-~--------~-------------+---------

Figure c: Synchronous N·Stage Counter With Parallel Gated Carry/Borrow
DIRECTION
CONTROL

ENABLE

-

r

"-t>o--o

~O--OCE

CE
CP

r

I . - UfO

UfO

TC'---

CP

CLOCK

5-96

~

U/O

~Do--<>cE
TC-

rcp

TC~

AC190 • AC191
Logic Diagram
CP

U/O

CE

Po

~ ~

-

~

~7

reJ ~

f--

I

-

.....

'7

V

~

)

er

LI +
J CLOCK K
PRESET
CLEAR

Q

0

b

~I'

'I~

PRESET
J CLOCK K
CLEAR

0

Q

V
LI'

~
b I

TC

)

J CLOCK K+_
PRESET
CLEAR

0

Q

LRC

-

1 I)

~C

I

l I

.....

II

~.~

h~ e
LI" ,L '.IJ
PAESET

CLEAR

Q

'17

'\7

00

0,

a

L-

L-

t

'V

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

DC Characteristics (unless otherwise specified)
Symbol

Parameter

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

54AC

160

8.0

5-97

74AC

80

8.0

Units

Conditions

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

p,A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

•

AC190 • AC191
AC Characteristics

Symbol

Parameter

Vee·
(V)

74AC190

54AC190

74AC190

TA= +25°C
CL=50 pF

TA= - 55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Fig.
No.

Max

3.3
5.0

88
120

MHz

3·3

3.3
5.0

9.5
7.0

ns

3·6

tPHL

10.5
7.5

ns

3·6

tPLH

15.0
11.0

ns

3·6

tPHL

ns

3·6

tPLH

ns

3·6

ns

3·6

ns

3·6

fmax

Maximum Count
Frequency

Units

tPLH

tPHL

Propagation Delay
CP to RC

tPLH

cr to RC

tPHL

Propagation Delay

3.3
5.0

Propagation Delay

CE to RC

3.3
5.0

8.5
6.0

3·6

tPLH

Propagation Delay
UfD to RC

3.3
5.0

11.0
8.0

3·6

tPHL

Propagation Delay
OlDtoRC

3.3
5.0

10.5
7.5

3·6

tPLH

Propagation Delay
OlD to TC

3.3
5.0

9.5
7.0

ns

3·6

tPHL

Propagation Delay
UfD to TC

3.3
5.0

9.5
7.0

ns

3·6

tPLH

Propagation Delay
Pn to an

3.3
5.0

10.5
7.5

ns

3·6

tPHL

Propagation Delay
Pn to an

3.3
5.0

9.5
7.0

ns

3·6

Propagation Delay
P[ to an

3.3
5.0

11.5
8.5

ns

3·6

Propagation Delay
PL to an

3.3
5.0

11.5
8.5

ns

3·6

tPLH
tPHL

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·98

AC190 • AC191
AC Operating Requirements

Symbol

Parameter

Vcc·
(V)

74AC190

54AC190

74AC190

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum

4.5
3.0

ts

Units

Fig.
No.

ns

3-9

th

Hold Time,
Pn to PL

ns

3-9

ts

Setup Time, LOW
CE to CP

ns

3-9

th

Hold Time, LOW
CE to CP

ns

3-9

ts

Setup Time,
HIGH or LOW
DID to CP

3.3
5.0

ns

3-9

th

Hold Time, HIGH or LOW
DID to CP

3.3
5.0

-1.5
-1.0

3-9

tw

PL Pulse Width, LOW

3.3
5.0

5.5
6.0

3-6

tw

CP Pulse Width, LOW

3.3
5.0

5.5
6.0

3-6

tree

Recovery Time
PL to CP

3.3
5.0

4.5
3.0

ns

3-9

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-99

•

AC190 • AC191
AC Characteristics

Parameter

Symbol

Vcc·
(V)

74AC191

54AC191

74AC191

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

60
80

Units

Fig.
No.

MHz

3·3

Max

fmax

Maximum Count
Frequency

3.3
5.0

70
90

105
133

65
85

tPLH

Propagation Delay
CP to an

3.3
5.0

3.0
2.0

8.5
6.0

15.0
11.0

1.0
1.0

17.5
13.0

1.0
1.0

16.0
12.0

ns

3-6

tPHL

Propagation Delay
CP to an

3.3
5.0

3.0
2.0

8.5
6.0

14.5
10.5

1.0
1.0

17.5
12.5

1.0
1.0

16.0
11.5

ns

3-6

tPLH

Propagation Delay
CP to TC

3.3
5.0

4.0
3.0

10.5
7.5

18.0
12.0

1.0
1.0

22.0
15.5

1.0
1.0

20.0
14.0

ns

3-6

tPHL

Propagation Delay
CP to TC

3.3
5.0

4.5
3.0

10.5
7.5

17.5
12.5

1.0
1.0

20.5
15.0

1.0
1.0

19.0
13.5

ns

3-6

tPLH

Propagation Delay
CP to R'C"

3.3
5.0

3.0
2.5

7.5
5.5

12.0
9.5

1.0
1.0

14.5
11.0

1.0
1.0

13.5
10.5

ns

3-6

tPHL

Propagation Delay
CP to R'C"

3.3
5.0

2.5
2.0

7.0
5.0

11.5
8.5

1.0
1.0

14.0
10.0

1.0
1.0

12.5
9.5

ns

3-6

Propagation Delay

3.3
5.0

2.5
1.5

7.0
5.0

12.0
8.5

1.0
1.0

15.0
10.5

1.0
1.0

13.5
9.5

ns

3-6

3.3
5.0

2.5
1.5

6.5
5.0

11.0
8.0

1.0
1.0

14.0
10.0

1.0
1.0

12.5
9.0

ns

3-6

3.3
5.0

2.5
1.5

6.5
5.0

12.5
9.0

1.0
1.0

16.0
11.5

1.0
1.0

14.5
10.0

ns

3-6

tPLH

CE to R'C"

tPHL

CE to R'C"

tPLH

iJlD to R'C"

tPHL

iJlD to RC

3.3
5.0

2.5
1.5

7.0
5.0

12.0
8.5

1.0
1.0

15.5
11.0

1.0
1.0

13.5
10.0

ns

3-6

Propagation Delay
UfD to TC

3.3
5.0

2.5
2.0

7.0
5.0

11.5
8.5

1.0
1.0

14.5
10.5

1.0
1.0

13.5
9.5

ns

3-6

UID

Propagation Delay
to TC

3.3
5.0

2.5
1.5

6.5
5.0

11.0
8.5

1.0
1.0

13.5
10.5

1.0
1.0

12.5
9.5

ns

3-6

tPLH

Propagation Delay
Pn to an

3.3
5.0

3.0
2.0

8.0
5.5

13.5
9.5

1.0
1.0

17.0
11.5

1.0
1.0

15.5
10.5

ns

3-6

tPHL

Propagation Delay
Pn to an

3.3
5.0

3.0
2.0

7.5
5.5

13.0
9.5

1.0
1.0

16.5
11.5

1.0
1.0

14.5
10.5

ns

3-6

tPLH

Propagation Delay
PL to an

3.3
5.0

3.5
2.0

9.5
5.5

14.5
9.5

1.0
1.0

19.0
11.5

1.0
1.0

17.5
10.5

ns

3-6

tPHL

Propagation Delay
PL to an

3.3
5.0

3.0
2.0

8.0
6.0

13.5
10.0

1.0
1.0

16.5
12.0

1.0
1.0

15.5
11.0

ns

3-6

tPLH
tPHL

Propagation Delay
Propagation Delay
Propagation Delay

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 Is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
Information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.
5-100

AC190 • AC191
AC Operating Requirements

Parameter

Symbol

Vcc·
(V)

74AC191

54AC191

74AC191

TA= +25°C
CL=50 pF

TA= - 55°C
to + 125°C
CL=50 pF

TA=-40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Setup Time,
HIGH or LOW
Pn to PL

3.3
5.0

1.0
0.5

3.0
2.0

3.5
3.0

3.0
2.5

ns

3-9

th

Hold Time, HIGH or LOW
Pn to PL

3.3
5.0

-1.5
-0.5

0.5
1.0

1.0
1.0

1.0
1.0

ns

3-9

Setup Time, LOW

3.3
5.0

3.0
1.5

6.0
4.0

7.5
5.0

7.0
4.5

ns

3-9

(;E to CP

3.3
5.0

-4.0
-2.5

-0.5
0

-0.5
0

-0.5
0

ns

3-9

Setup Time, HIGH or
LOW, DID to CP

3.3
5.0

4.0
2.5

8.0
5.5

10.5
7.0

9.0
6.5

ns

3-9

th

Hold Time, HIGH or LOW
DID to CP

3.3
5.0

-5.0
-3.0

0
0.5

0
0.5

0
0.5

ns

3-9

tw

PL Pulse Width, LOW

3.3
5.0

2.0
1.0

3.5
1.0

4.5
1.0

4.0
1.0

ns

3-6

tw

CP Pulse Width, LOW

3.3
5.0

2.0
2.0

3.5
3.0

4.5
4.0

4.0
4.0

ns

3-6

tree

Recovery Time
PL to CP

3.3
5.0

-0.5
-1.0

0
0

0
0

0
0

ns

3-9

ts
th

ts

(;E to CP

Hold Time, LOW

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

54/74AC

Parameter

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

75.0

pF

Vcc=5.5 V

5·101

•

AC192 • AC193
54AC/74AC192 • 54AC/74AC193
Up/Down Counters with Separate Up/Down Clocks
Description

Connection Diagrams

The 'AC192 is an up/down BCD decade (8421)
counter. The 'AC193 is an up/down modulo·16
binary counter. Separate Count Up and Count
Down Clocks are used, and in either counting
mode the outputs change state synchronously with
the LOW·to·HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count
Down outputs are provided that are used as the
clocks for a subsequent stage without extra logic,
thus simplifying multistage counter designs.
Individual preset inputs allow the circuit to be used
as a programmable counter. Both the Parallel Load
(PL) and the Master Reset (MR) inputs
asynchronously override the clocks.
•
•
•
•

Pin Assignment
for DIP, Flatpak and SOIC

High·Speed-120 MHz Typical Count Frequency
Synchronous Counting
Asynchronous Parallel Load and Master Reset
Outputs Source/Sink 24 mA

Q2 CPu NC CPo 00

wwww0

Ordering Code: See Section 6

Q3!]]

[IJQ1

GND[j]]

[IjP1

NCITIl

Logic Symbol

ITlNC

P3[g]

~vcc

P2lill

[iIDPo

[4]~~[jl][8]
P[ Teu

CPo

Po - P3
00 - 03
TCo
TCu

MR

Pin Assignment
for LCC

TCo

Pin Names
CPu
CPo
MR
PL

NC TeD

Count Up Clock Input
Count Down Clock Input
Asynchronous Master Reset Input
Asynchronous Parallel Load Input
Parallel Data Inputs
Flip-flop Outputs
Terminal Count Down (Borrow) Output
Terminal Count Up (Carry) Output

5-102

AC192 • AC193
Logic Diagram

'AC192
TCu

Teo

(CARRY) (BORROW)

~

~tJ
--r
=r--r-

P3

...

..Jo,

03

rtoJ

~
-- if
a

J

CP

•

...

..Jo"

~

p-

J

~
r->.~

.
~

CPu

..Jo"

f

r

tooJ

CP
~

Ti

=r--r-

Po

a

J

CP

'J

J-

.?-

+J

00

.~

MR

CPo

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.
5-103

AC192 • AC193
Logic Diagram

'AC193
TC u
(CARRY)

TC o
(BORROW)

~

t"T

XJ.-t-J
T
CP

=r->-

°a

...

v

~J
a

J
»{
CP

K

...

a

-v

i-

r--r-

~J
a

J
~
T
CP

r--r-

P,

L~

~~

--

"""}-

Po

......

a,

~J
a

J

CP

K Co

...

a

v

~
,~

QXQ
CPu

,~

MR

CPo

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.
5-104

AC192 • AC193
Functional Description
The 'AC1921'AC193 are asynchronously presettable
counters. The 'AC192 is a decade counter while the
'AC193 is organized for 4·bit binary operation. They
both contain four edge·triggered flip·flops, with
internal gating and steering logic to provide master
reset, individual preset, count up and count down
operations.

input will disable the preset gates, override both
clock inputs, and latch each Q output in the LOW
state. If one of the clock inputs is LOW during and
after a reset or load operation, the next LOW-toHIGH transition of that clock will be interpreted as
a legitimate signal and will be counted.

Function Table
A LOW-to-HIGH transition on the CP input to each
flip-flop causes the output to change state.
Synchronous switching, as opposed to ripple
counting, is achieved by driving the steering gates
of all stages from a common Count Up line and a
common Count Down line, thereby causing all
state changes to be initiated simultaneously. A
LOW-to-HIGH transition on the Count Up input will
advance the count by one; a similar transition on
the Count Down input will decrease the count by
one. While counting with one clock input, the other
should be held HIGH, as indicated in the Function
Table. Otherwise, the circuit will either count by
twos or not at all, depending on the state of the
first flip-flop, which cannot toggle as long as either
clock input is LOW.

MR

PL

CPu

CPo

H
L
L
L
L

X

X
X

X
X

H
I
H

H
H
I

L
H
H
H

H = HIGH Voltage Level
L= LOW Voltage Level

Mode

Reset (Asyn.)
Preset (Asyn.)
No Change
Count Up
Count Down
X = Immaterial
I= LOW-to-HIGH Transition

State Diagrams
'AC192

The Terminal Count Up (TCu) and Terminal Count
Down (feD) outputs are normally HIGH. When the
circuit has reached the maximum count state; 9
(,AC192) or 15 (,AC193), the reset HIGH-to-LOW
transition of the Count Up Clock will cause 'fCu to
go LOW. TCu will stay LOW until CPu goes HIGH
again, thus effectively repeating the Count Up
Clock, but delayed by two gate delays. Similarly,
the TCo output will go LOW when the circuit is in
the zero state and the Count Down Clock goes
LOW. Since the TC outputs repeat the clock
waveforms, they can be used as the clock input
Signals to the next higher order circuit in a
multistage counter.

COUNT UP
---.. COUNT DOWN

'AC193

TCu =Qoe01 e02 eQ3 eCPu (' AC192)
'fCu = QoeQ1 eQ2 eQ3 eCPu (' AC193)
TCu =Ooe01 e02 e03 eCPO
Both the 'AC192 and the 'AC193 have an
asynchronous parallel load capability permitting
the counter to be preset. When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW,
information present on the Parallel Data input
(Po - P3) is loaded into the counter and appears on
the outputs regardless of the conditions of the
clock inputs. A HIGH signal on the Master Reset

-COUNT UP
·---COUNT DOWN

5·105

AC192 • AC193
DC Characteristics (unless otherwise specified)
Symbol

54AC

Parameter

74AC

Units

Conditions

Icc

Maximum Quiescent
Supply Current

160

80

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

8.0

8.0

p,A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

AC Characteristics

Symbol

Vec·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL= 50 pF

Min

Min

Units

Fig.
No.

MHz

3·3

tPLH

ns

3·6

tPHL

ns

3·6

ns

3-6

Min

Typ
88
120

fmax

Max

Max

Max

tPLH

Propagation Delay
CPu or CPD to Qn

tPHL

Propagation Delay
CPu or CPD to Qn

3.3
5.0

ns

3-6

tPLH

Propagation Delay
Pn to Qn

3.3
5.0

ns

3-6

tPHL

Propagation Delay
Pn to Qn

3.3
5.0

9.5
7.0

3-6

tPLH

Propagation Delay
PLtoQn

3.3
5.0

12.5
9.0

3-6

tPHL

Propagation Delay
PL to Qn

3.3
5.0

11.0
8.0

ns

3-6

tPHL

Propagation Delay
MR to Qn

3.3
5.0

12.5
9.0

ns

3-6

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 Is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-106

AC192 • AC193
AC Characteristics, continued

/
symb?i

l l~)

,/"l'"

'",

tPLH
tPHL

cP~~m.'e,
i /'\/~~:~:::::I
t "::
,r"',::::/
('

Vcc·
(V)

J

",?'

74AC

54AC

74AC

TA= + 25°C
CL=50pF

TA= - 55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Typ

Min

1'"

prd~gatihry D/¢I,)',::::,;,/ /3.3
M R to TCO'

t.,"' ..

Propagation Delay
MR to TCo

';(1

/5.0

i

3.3
l? JCZ
.5:.1) V'/i~,/ir 1i1.~i
!~. t9"?/~
/

"iL·1;~I/

Propagation Delay
PL to TCu or TI)o

3.3
5.0

9.5
7.0

tPLH

Propagation Delay
Pn to TCu or TCo

3.3
5.0

11.5
8.5

tPHL

Propagation Delay
Pn to TCu or TCo

3.3
5.0

11.5
8.5

l'/l /

/"'~

'I,

No.

ns

3·6

ns

3·6

ns

3·6

,

i//\\ \ . ,./:.'

"'*',

Fig.

Max

·~.O

3.3
5.0

tPHL

Max

12.5
j

Propagation Delay
PL to TCu or TCo

tPLH

Max

Units

("

if

:c

'i,(i.:::. i)

/"""

f/.:~:·~)" ~ ~9
\ I

I'·

L/

lJ f~;;>

3·6

!po,

.?

V

3·6

·'··f

ns

3·6

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·107

•

AC192 • AC193
AC Operating Requirements

Vcc·
(V)

Symbol

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

4.5
3.0

Units

Fig.

No.

ns

3·9

th

ns

3·9

tw

ns

3·6

ns

3·6

ns

3·6

ts

tw

CPu or CPo Pulse Width,
LOW

tw

CPu or CPo Pulse Width,
LOW (Change of
Direction)

3.3
5.0

tw

MR Pulse Width, HIGH

3.3
5.0

7.0
5.0

3·6

tree

Recovery Time
PL to CPu or CPo

3.3
5.0

4.5
3.0

3·9

tree

Recovery Time
MR to CPu or CPo

3.3
5.0

8.5
6.0

ns

3·9

'Voltage Range 3.3 Is 3.3 V ± 0.3 V
Voltage Range 5.0 Is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

54174AC

Parameter

Units

Conditions

pF

Vcc=5.5 V

pF

Vcc=5.5 V

Typ
CIN

Input Capacitance

Cpo

Power Dissipation
Capacitance

4.5

5·108

AC240 • ACT240
54AC/74AC240 • 54ACT/74ACT240
Octal Buffer/Line Driver With 3-State Outputs
Connection Diagrams

Description
The 'ACI'ACT240 is an octal buffer and line driver
designed to be employed as a memory address
driver, clock driver and bus oriented transmitter or
receiver which provides improved PC board
density .
• 3·State Outputs Drive Bus Lines or Buffer
Memory Address Registers
• Outputs Source/Sink 24 mA
• 'ACT240 has TTL·Compatible Inputs

Ordering Code: See Section 6
Truth Tables
Outputs

Inputs
OEl

0

(Pins 12, 14, 16, 18)

L
L
H

L
H

H
L
Z

X

Inputs

Pin Assignment
for DIP, Flatpak and SOIC

Outputs

OE2

0

(Pins 3, 5, 7, 9)

L
L
H

L
H

H
L
Z

X

GND

IIQ]

rn

ITIl

IT] Ofl

~

~v"

6ID 0E2

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
z= High Impedance

Pin ASSignment
for LCC

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Iccllnput (,ACT240)

1.6

160

5·109

74AC/ACT

Units

Conditions

/LA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=Worst Case

8.0

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

mA

VIN = Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

80

•

AC240 • ACT240
AC Characteristics

Symbol

Parameter

Vee*
(V)

74AC

54AC

74AC

TA=+25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Units

Fig.
No.

Min

Typ

Max

Min

Max

Min

Max

tPLH

Propagation Delay
Data to Output

3.3
5.0

1.0
1.0

6.0
4.5

8.0
6.5

1.0
1.0

11.0
8.5

1.0
1.0

9.0
7.0

ns

3-5

tPHL

Propagation Delay
Data to Output

3.3
5.0

1.0
1.0

5.5
4.5

8.0
6.0

1.0
1.0

10.5
8.0

1.0
1.0

8.5
6.5

ns

3·5

tPZH

Output Enable Time

3.3
5.0

1.0
1.0

6.0
5.0

10.5
7.0

1.0
1.0

11.5
9.0

1.0
1.0

11.0
8.0

ns

3-7

tPZL

Output Enable Time

3.3
5.0

1.0
1.0

7.0
5.5

10.0
8.0

1.0
1.0

13.0
10.5

1.0
1.0

11.0
8.5

ns

3·8

tPHZ

Output Disable Time

3.3
5.0

1.0
1.0

7.0
6.5

10.0
9.0

1.0
1.0

12.5
10.5

1.0
1.0

10.5
9.5

ns

3-7

tpLZ

Output Disable Time

3.3
5.0

1.0
1.0

7.5
6.5

10.5
9.0

1.0
1.0

13.5
11.0

1.0
1.0

11.5
9.5

ns

3-8

Units

Fig.
No.

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Characteristics

Symbol

Parameter

Vee*
(V)

74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

5.0

1.0

6.0

8.5

1.0

9.5

1.0

9.5

ns

3-5

Propagation Delay
Data to Output

5.0

1.0

5.5

7.5

1.0

9.0

1.0

8.5

ns

3-5

tPZH

Output Enable Time

5.0

1.0

7.0

8.5

1.0

10.0

1.0

9.5

ns

3-7

tPZL

Output Enable Time

5.0

1.0

7.0

9.5

1.0

11.5

1.0

10.5

ns

3-8

tPHZ

Output Disable Time

5.0

1.0

8.0

9.5

1.0

11.0

1.0

10.5

ns

3-7

tpLZ

Output Disable Time

5.0

1.0

6.5

10.0

1.0

11.5

1.0

10.5

ns

3-8

tPLH

Propagation Delay
Data to Output

tPHL

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-110

AC240 • ACT240
Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

45.0

pF

Vcc=5.5 V

•

5·111

AC241 • ACT241
54AC/74AC241 • 54ACT/74ACT241
Octal Buffer/Line Driver With 3-State Outputs
Description

Connection Diagrams

The 'ACI'ACT241 is an octal buffer and line driver
designed to be employed as a memory address
driver, clock driver and bus-oriented transmitter or
receiver which provides improved PC board
density .
• 3·State Outputs Drive Bus Lines or Buffer
Memory Address Registers
• Outputs Source/Sink 24 mA
• 'ACT241 has TTL·Compatible Inputs

Ordering Code: See Section 6
Truth Tables
Inputs

Outputs

OE1

0

(Pins 12, 14, 16, 18)

L

L

L

H

L
H

H

X

Z

0

(Pins 3, 5, 7, 9)

Inputs

OE2

H
H
L

Pin Assignment
for DIP, Flatpak and SOIC

Outputs

L
H
X

[II

GNOI'Q]

L

Ii]

OJ DE,

B]]

~ Vee

[i]

~ OE2

H
Z

H =HIGH Voltage Level
L =LOW Voltage Level
X =Immaterial
Z= High Impedance

Pin Assignment
for LCC

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

lecT

Maximum Additional
lecllnput ('ACT241)

1.6

160

5-112

74AC/ACT

Units

Conditions

/LA

VIN=Vce or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

/LA

VIN=Vee or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

rnA

VIN = Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

80

AC241 • ACT241
AC Characteristics

Symbol

Parameter

Vee·
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
Data to Output

3.3
5.0

1.0
1.0

6.0
5.0

9.0
7.0

1.0
1.0

12.0
9.5

1.0
1.0

10.0
7.5

ns

3-5

tPHL

Propagation Delay
Data to Output

3.3
5.0

1.0
1.0

6.0
4.5

9.0
7.0

1.0
1.0

11.0
9.0

1.0
1.0

10.5
7.5

ns

3-5

tPZH

Output Enable Time

3.3
5.0

1.0
1.0

6.5
5.5

12.5
9.0

1.0
1.0

13.0
10.0

1.0
1.0

13.0
9.5

ns

3-7

tPZL

Output Enable Time

3.3
5.0

1.0
1.0

7.0
5.5

12.0
9.0

1.0
1.0

13.0
10.0

1.0
1.0

13.0
9.5

ns

3-8

tPHZ

Output Disable Time

3.3
5.0

1.0
1.0

8.0
6.5

12.0
10.0

1.0
1.0

13.0
11.5

1.0
1.0

12.5
10.5

ns

3-7

tpLZ

Output Disable Time

3.3
5.0

1.0
1.0

7.0
6.0

12.5
10.0

1.0
1.0

13.0
11.5

1.0
1.0

13.5
10.5

ns

3-8

Units

Fig.
No.

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Characteristics

Symbol

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

5.0

1.0

6.5

9.0

1.0

10.0

1.0

10.0

ns

3-5

Propagation Delay
Data to Output

5.0

1.0

7.0

9.0

1.0

10.0

1.0

10.0

ns

3-5

tPZH

Output Enable Time

5.0

1.0

6.0

9.0

1.0

11.5

1.0

10.0

ns

3-7

tPZL

Output Enable Time

5.0

1.0

7.0

10.0

1.0

12.5

1.0

11.0

ns

3-8

tPHZ

Output Disable Time

5.0

1.0

8.0

10.5

1.0

12.5

1.0

11.5

ns

3-7

tpLZ

Output Disable Time

5.0

1.0

7.0

10.5

1.0

12.5

1.0

11.5

ns

3-8

tPLH

Propagation Delay
Data to Output

tPHL

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·113

•

AC241 • ACT241
Capacitance
54/74AC/ACT
Symbol

Parameter

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

45.0

pF

Vcc=5.5 V

5·114

AC244 • ACT244
54AC/74AC244 • 54ACT/74ACT244
Octal Buffer/Line Driver With 3-State Outputs
Description

Connection Diagrams

The 'ACI'ACT244 is an octal buffer and line driver
designed to be employed as a memory address
driver, clock driver and bus-oriented
transmitter/receiver which provides improved PC
board density.
• 3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
• Outputs Source/Sink 24 mA
• 'ACT244 has TTL-Compatible Inputs

Truth Tables
Inputs

Outputs

OE1

0

(Pins 12, 14, 16, 18)

L

L

L

H

H

X

L
H
Z

Pin Assignment
for DIP, Flatpak and SOIC

~[ZJ~[]J[i]

Outputs

Inputs
OE2

0

(Pins 3, 5, 7, 9)

L
L
H

L
H

L
H
Z

X

GND

rn

w

[!Q]

[2J

[ii]

IT] 6£1

Ii]

~vcc

Ii]

I1ID 0E2

H = HIGH Voltage Level
L = LOW Voltage Level
x= Immaterial
Z= High Impedance

~[i][i][iiJ[i]

Pin Assignment
for LCC

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Icc/Input (,ACT244)

1.6

160

5-115

74AC/ACT

Units

Conditions

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

p,A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

rnA

VIN = Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

80

•

AC244 • ACT244
AC Characteristics

Symbol

Parameter

Vee·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Units

Fig.
No.

Min

Typ

Max

Min

Max

Min

Max

3.3
5.0

1.0
1.0

6.5
5.0

9.0
7.0

1.0
1.0

12.5
9.5

1.0
1.0

10.0
7.5

ns

3·5

Propagation Delay
Data to Output

3.3
5.0

1.0
1.0

6.5
5.0

9.0
7.0

1.0
1.0

12.0
9.0

1.0
1.0

10.0
7.5

ns

3·5

tPZH

Output Enable Time

3.3
5.0

1.0
1.0

6.0
5.0

10.5
7.0

1.0
1.0

11.5
9.0

1.0
1.0

11.0
8.0

ns

3·7

tPZL

Output Enable Time

3.3
5.0

1.0
1.0

7.5
5.5

10.0
8.0

1.0
1.0

13.0
10.5

1.0
1.0

11.0
8.5

ns

3·8

tPHZ

Output Disable Time

3.3
5.0

1.0
1.0

7.0
6.5

10.0
9.0

1.0
1.0

12.5
10.5

1.0
1.0

10.5
9.5

ns

3·7

tpLZ

Output Disable Time

3.3
5.0

1.0
1.0

7.5
6.5

10.5
9.0

1.0
1.0

13.0
11.0

1.0
1.0

11.5
9.5

ns

3·8

Units

Fig.
No.

tPLH

Propagation Delay
Data to Output

tPHL

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Characteristics

Symbol

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

tPLH

Propagation Delay
Data to Output

5.0

1.0

6.5

9.0

1.0

10.0

1.0

10.0

ns

3·5

tPHL

Propagation Delay
Data to Output

5.0

1.0

7.0

9.0

1.0

10.0

1.0

10.0

ns

3·5

tPZH

Output Enable Time

5.0

1.0

6.0

8.5

1.0

9.5

1.0

9.5

ns

3·7

tPZL

Output Enable Time

5.0

1.0

7.0

9.5

1.0

11.0

1.0

10.5

ns

3·8

ns

3·7

ns

3·8

tPHZ

Output Disable Time

5.0

1.0

7.0

9.5

1.0

11.0

1.0

10.5

tpLZ

Output Disable Time

5.0

1.0

7.5

10.0

1.0

11.5

1.0

10.5

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·116

AC244 • ACT244
Capacitance
Symbol

54/74AC/ACT
Parameter

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

CPD

Power Dissipation
Capacitance

45.0

pF

Vcc=5.5 V

•

!
I

I
5-117

I

AC245 • ACT245
54AC/74AC245 • 54ACT/74ACT245
Octal Bidirectional Transceiver With 3-State Inputs/Outputs

Description

Connection Diagrams

The 'ACI'ACT245 contains eight non-inverting
bidirectional buffers with 3-state outputs and is
intended for bus-oriented applications. Current
sinking capability is 24 mA at both the A and B
ports. The Transmit/Receive (TfR) input determines
the direction of data flow through the bidirectional
transceiver. Transmit (active-HIGH) enables data
from A ports to B ports; Receive (active-LOW)
enables data from B ports to A ports. The Output
Enable input, when HIGH, disables both A and B
ports by placing them in a High Z condition.
•
•
•
•

Noninverting Buffers
Bidirectional Data Path
A and B Outputs Source/Sink 24 mA
'ACT245 has TTL-Compatible Inputs

Pin Assignment
for DIP, Flatpak and SOIC

Ordering Code: See Section 6

A6

Pin Names
OE

Output Enable Input
Transmit/Receive Input
Side A 3-State Inputs or
3-State Outputs
Side B 3-State Inputs or
3-State Outputs

TfR
Ao - A7
Bo - B7

A,

A3

A2

III 0 III III

As

A4

[I]

1 ____ [3JA'

III

GND

[i]]

B,

!TIl

B6

[j]]

rn Ao

~li~Lt OJ

~OE

B5~

IBJ~~@]~
B4

Truth Table
OE

Outputs

T/R

L

L

L

H

H

X

83

82

81

eo

Pin Assignment
for LCC

Inputs

Bus B Data to Bus A
Bus A Data to Bus B
High Z State

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

5-118

Tlil

~vcc

AC245 • ACT245
DC Characteristics (unless otherwise specified)
Parameter

Symbol

74AC/ACT

54AC/ACT

Conditions

Units

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

p.A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA= 25°C

1.6

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

74AC

54AC

74AC

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Iccllnput (,ACT245)

160

80

AC Characteristics

Symbol

Parameter

Vcc·
(V)

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
An to Sn or Sn to An

3.3
5.0

1.0
1.0

5.0
3.5

8.5
6.5

1.0
1.0

11.5
8.5

1.0
1.0

9.0
7.0

ns

3·5

tPHL

Propagation Delay
An to Sn or Sn to An

3.3
5.0

1.0
1.0

5.0
3.5

8.5
6.0

1.0
1.0

10.0
7.5

1.0
1.0

9.0
7.0

ns

3·5

tPZH

Output Enable Time

3.3
5.0

1.0
1.0

7.0
5.0

11.5
8.5

1.0
1.0

13.5
10.0

1.0
1.0

12.5
9.0

ns

3·7

tPZL

Output Enable Time

3.3
5.0

1.0
1.0

7.5
5.5

12.0
9.0

1.0
1.0

14.5
10.5

1.0
1.0

13.5
9.5

ns

3·8

tPHZ

Output Disable Time

3.3
5.0

1.0
1.0

6.5
5.5

12.0
9.0

1.0
1.0

13.5
10.5

1.0
1.0

12.5
10.0

ns

3·7

tpLZ

Output Disable Time

3.3
5.0

1.0
1.0

7.0
5.5

11.5
9.0

1.0
1.0

14.0
10.5

1.0
1.0

13.0
10.0

ns

3·8

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-119

•

AC245 • ACT245
AC Characteristics

Parameter

Symbol

Vcc·
(V)

74ACT

54ACT

74ACT

TA=+25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
An to Bn or Bn to An

5.0

1.0

4.0

7.5

1.0

9.0

1.0

8.0

ns

3-5

tPHL

Propagation Delay
An to Bn or Bn to An

5.0

1.0

4.0

8.0

1.0

10.0

1.0

9.0

ns

3-5

tPZH

Output Enable Time

5.0

1.0

5.0

10.0

1.0

12.0

1.0

11.0

ns

3·7

tPZL

Output Enable Time

5.0

1.0

5.5

10.0

1.0

13.0

1.0

12.0

ns

3-8

tPHZ

Output Disable Time

5.0

1.0

5.5

10.0

1.0

12.0

1.0

11.0

ns

3-7

Output Disable Time

5.0

1.0

5.0

10.0

1.0

12.0

1.0

11.0

ns

3-8

tpLZ

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ

CIN

input Capacitance

4.5

pF

Vcc=5.5 V

CliO

Input/Output
Capacitance

15.0

pF

Vcc=5.5 V

CPD

Power Dissipation
Capacitance

45.0

pF

Vcc=5.5 V

5-120

AC251 • ACT251
54AC/74AC251 • 54ACT/74ACT251
8-lnput Multiplexer With 3-State Outputs
Description

Connection Diagrams

The 'ACI'ACT251 is a high-speed 8-input digital
multiplexer. It provides, in one package, the ability
to select one bit of data from up to eight sources.
It can be used as universal function generator to
generate any logic function of four variables. Both
true and complementary outputs are provided.
•
•
•
•
•

Multifunctional Capability
On-Chip Select Logic Decoding
Inverting and Noninverting 3-State Outputs
Outputs Source/Sink 24 mA
'ACT251 has TTL-Compatible Inputs

Ordering Code: See Section 6

Pin Assignment
for DIP, Flatpak and SOIC

Logic Symbol
Z

Z

NC

10

11

[!][l]wwlil

OEm
OE 10

h

z

12

13

14

15

[3]

I,

GND

Ii]]

11113

NC

[j]

[iJ

S,

[j]

@Q]

Vee

s,

!!ill

[i]]

I,

16· 17

•

NC

z
~~[i]][i][i]]
So

17

NC

16

15

Pin Assignment
for LCC

Pin Names
So - S2
OE
10 - 17

Z

Z

Select Inputs
3-State Output Enable Input
Multiplexer Inputs
3-State Multiplexer Output
Complementary 3-State Multiplexer
Output

5-121

I

AC251 • ACT251
Functional Description
maximum ratings. The Output Enable signals
should be designed to ensure there is no overlap
in the active-LOW portion of the enable voltages.

This device is a logical implementation of a singlepole, 8-position switch with the switch position
controlled by the state of three Select inputs, So,
Sl, S2. Both true and complementary outputs are
provided. The Output Enable input (OE) is active
LOW. When it is activated, the logic function
provided at the output is:

Truth Table
Outputs

Inputs

Z = DE -(lo-So-81-S2 + 11-So-81-82 +
12-S0-S1-S2 + 13-S0-S1-82 +
14-So-81-S2 + 15-S0-S1-S2 +
16-S0-S1-S2 + 17-S0-S1-S2)
When the Output Enable is HIGH, both outputs are
in the high impedance (High Z) state. This feature
allows multiplexer expansion by tying the outputs
of up to 128 devices together. When the outputs of
the 3-state devices are tied together, all but one
device must be in the high impedance state to
avoid high currents that would exceed the

DE

S2

Sl

So

H
L
L
L
L
L
L
L
L

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
L
H
L
H
L
H

Z

Z

Z

Z

10
11
12

10
11
12
13
14
15
16
17

13
14
15
16

h

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

Logic Diagram

S2~o-~~~~I~~----+-----~~-----+------~------~~--~~~---+~----~~
S1~o-~~~~1 >------~----_4+_----_H~----4+._----~----_4~~--~H_----_h

OE

z

Z

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-122

AC251 • ACT251
DC Characteristics (unless otherwise specified)
Symbol

Parameter

74AC/ACT

54AC/ACT

Conditions

Units

/lA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

/lA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = 25°C

1.6

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

74AC

54AC

74AC

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Iccllnput (,ACT251)

160

80

AC Characteristics

Symbol

Parameter

Vce·
(V)

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
Sn to Z or Z

3.3
5.0

1.0
1.0

11.5
8.5

17.5
12.5

1.0
1.0

21.0
15.5

1.0
1.0

19.0
13.5

ns

3·6

tPHL

Propagation Delay
Sn to Z or Z

3.3
5.0

1.0
1.0

11.0
8.0

17.5
12.5

1.0
1.0

21.0
15.5

1.0
1.0

19.0
13.5

ns

3-6

tPLH

Propagation Delay
In to Z or Z

3.3
5.0

1.0
1.0

10.0
7.0

14.0
10.0

1.0
1.0

17.0
12.0

1.0
1.0

15.5
11.0

ns

3-5

tPHL

Propagation Delay
In to Z or Z

3.3
5.0

1.0
1.0

9.0
6.5

14.0
10.0

1.0
1.0

16.5
12.0

1.0
1.0

15.5
11.0

ns

3-5

Output Enable Time

DE to Z orZ

3.3
5.0

1.0
1.0

7.5
5.5

11.0
8.0

1.0
1.0

13.0
10.0

1.0
1.0

12.0
9.0

ns

3-7

Output Enable Time
OE to Z or Z

3.3
5.0

1.0
1.0

7.5
5.5

11.0
B.O

1.0
1.0

13.0
10.0

1.0
1.0

12.0
9.0

ns

3-8

Output Disable Time

3.3
5.0

3.5
2.5

8.5
7.0

11.5
9.5

3.5
2.5

14.0
11.0

3.5
2.5

13.0
10.0

ns

3-7

3.3
5.0

4.0
3.0

7.0
5.5

11.0
8.0

4.0
3.0

13.0
10.0

4.0
3.0

12.0
8.5

ns

3-8

tPZH
tPZL
tPHZ
tpLZ

DE to Z or Z
Output Disable Time

DE to Z or Z

'Voltage Range 3.3 is 3.3 V ±0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-123

•

AC251 • ACT251
AC Characteristics

Parameter

Symbol

Vcc·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
Sn to Z or Z

5.0

1.0

7.0

13.5

1.0

16.5

1.0

13.0

ns

3·6

tPHL

Propagation Delay
Sn to Z or Z

5.0

1.0

7.5

13.0

1.0

16.0

1.0

14.5

ns

3·6

tPLH

Propagation Delay
In to Z or Z

5.0

1.0

5.5

10.0

1.0

13.0

1.0

10.5

ns

3·5

tPHL

Propagation Delay
In to Z or Z

5.0

1.0

6.5

10.5

1.0

13.0

1.0

12.0

ns

3·5

5.0

1.0

5.0

9.0

1.0

11.0

1.0

9.0

ns

3·7

5.0

1.0

4.5

9.0

1.0

11.0

1.0

8.5

ns

3·8

5.0

1.0

6.0

10.5

1.0

12.0

1.0

10.0

ns

3·7

5.0

1.0

4.5

9.0

1.0

11.0

1.0

8.5

ns

3·8

Output Enable Time

tPZH

OE to Z or Z

tPZL

OE to Z or Z

tPHZ

OE to Z or Z

tpLZ

OE to Z or Z

Output Enable Time
Output Disable Time
Output Disable Time

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

70.0

pF

Vcc=5.5 V

5·124

AC253 • ACT253
54AC/74AC253 • 54ACT/74ACT253
Dual 4-lnput Multiplexer With 3-State Outputs
Connection Diagrams

Description
The 'ACI'ACT253 is a dual 4-input multiplexer with
3-state outputs. It can select two bits of data from
four sources using common select inputs. The
outputs may be individually switched to a high
impedance state with a HIGH on the respective
Output Enable (DE) inputs, allowing the outputs to
interface directly with bus oriented systems.
•
•
•
•

Multifunction Capability
Noninverting 3·State Outputs
Outputs Source/Sink 24 mA
'ACT253 has TTL-Compatible Inputs

Ordering Code: See Section 6

Pin Assignment
for DIP, Flatpak and SOIC
loa

11a

NC

12a

133

IIJlIlwww

Logic Symbol

•

[II s,

z.[9J
GND ~

mOE,

NC

[j]

IT]

Zb

[j]]

~ Vee

lOb

§

IjID OEb

NC

~~[j]lm[i]
11b

12b

NC

13b

So

Pin Assignment
for LCC

Pin Names
loa - 13a
lOb -13b

SO, S1

DEa
DEb
Za, Zb

Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Output Enable Input
Side B Output Enable Input
3-State Outputs

5-125

I

AC253 • ACT253
Functional Description

Za =OEa-(loa-S1-So + l1a-S1-S0 +
12a-S1-S0 + 13a-S1-S0)

The 'ACI'ACT253 contains two identical 4-input
multiplexers with 3-state outputs. They select two
bits from four sources selected by common Select
inputs (So, 51). The 4-input multiplexers have
individual Output Enable (OEa, ~b) inputs which,
when HIGH, force the outputs to a high impedance
(High Z) state. This device is the logic
implementation of a 2-pole, 4-position switch,
where the position of the switch is determined by
the logic levels supplied to the two select inputs.
The logic equations for the outputs are shown:

Zb =OEb-(lob-S1-S0 + 11 b-S1-S0 +
12b-S1-So + 13b-S1-S0)
If the outputs of 3-state devices are tied together,
all but one device must be in the high impedance
state to avoid high currents that would exceed the
maximum ratings. Designers should ensure that
Output Enable signals to 3-state devices whose
outputs are tied together are designed so that
there is no overlap.

Truth Table
Select
Inputs

Data Inputs

Output
Enable

Outputs

So

51

10

11

12

13

OE

Z

X

X

X

L
L
H
H
L
L
H
H

L
L
L
L
H
H
H
H

L
H

X
X
X

X
X
X
X
X
L
H

X
X
X
X
X
X
X

X
X

L
H

H
L
L
L
L
L
L
L
L

Z
L
H
L
H
L
H
L
H

X
X
X
X
X
X

L
H

X
X
X
X

H =HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

Address inputs So and S, are common to both sections.

Logic Diagram
OEb

6

lab

So

s,

IDa

~ ~

Za

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-126

AC253 • ACT253
DC Characteristics (unless otherwise specified)
Symbol

54AC/ACT

Parameter

74AC/ACT

Units

Conditions

Icc

Maximum Quiescent
Supply Current

160

80

p.A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

8.0

8.0

p.A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = 25°C

ICCT

Maximum Additional
Iccllnput (,ACT253)

1.6

1.5

rnA

VIN = Vcc - 2.1 V
Vcc=5.5 V,
TA = Worst Case

AC Characteristics

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Units

Fig.
No.

Min

Typ

Max

Min

Max

Min

Max

tPLH

Propagation Delay
Sn to Zn

3.3
5.0

1.0
1.0

8.5
6.5

15.5
11.0

1.0
1.0

19.5
13.5

1.0
1.0

17.5
12.5

ns

3-6

tPHL

Propagation Delay
Sn to Zn

3.3
5.0

1.0
1.0

9.5
7.0

16.0
11.5

1.0
1.0

20.0
15.0

1.0
1.0

18.0
13.0

ns

3-6

tPLH

Propagation Delay
In to Zn

3.3
5.0

1.0
1.0

7.0
5.5

14.5
10.0

1.0
1.0

19.0
13.0

1.0
1.0

17.0
11.5

ns

3·5

tPHL

Propagation Delay
In to Zn

3.3
5.0

1.0
1.0

7.5
5.5

13.0
9.5

1.0
1.0

16.0
12.0

1.0
1.0

15.0
11.0

ns

3·5

tPZH

Output Enable Time

3.3
5.0

1.0
1.0

4.5
3.5

8.0
6.0

1.0
1.0

9.5
7.0

1.0
1.0

8.5
6.5

ns

3-7

tPZL

Output Enable Time

3.3
5.0

1.0
1.0

5.0
3.5

8.0
6.0

1.0
1.0

10.0
7.5

1.0
1.0

9.0
7.0

ns

3-8

tPHZ

Output Disable Time

3.3
5.0

1.0
1.0

5.5
5.0

9.5
8.0

1.0
1.0

11.0
9.5

1.0
1.0

10.0
8.5

ns

3·7

tpLZ

Output Disable Time

3.3
5.0

1.0
1.0

5.0
4.0

8.0
7.0

1.0
1.0

9.5
8.0

1.0
1.0

9.0
7.5

ns

3-8

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-127

•

AC253 • ACT253
AC Characteristics

Symbol

Parameter

Vcc·
(V)

74ACT

54ACT

74ACT

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
Sn to Zn

5.0

1.0

7.0

11.5

1.0

14.5

1.0

13.0

ns

3·6

tPHL

Propagation Delay
Sn to Zn

5.0

1.0

7.5

13.0

1.0

16.0

1.0

14.5

ns

3-6

tPLH

Propagation Delay
In to Zn

5.0

1.0

5.5

10.0

1.0

12.0

1.0

11.0

ns

3-5

tPHL

Propagation Delay
In to Zn

5.0

1.0

6.5

11.0

1.0

13.5

1.0

12.5

ns

3-5

tPZH

Output Enable Time

5.0

1.0

4.5

7.5

1.0

9.5

1.0

8.5

ns

3-7

tPZL

Output Enable Time

5.0

1.0

5.0

8.0

1.0

9.5

1.0

9.0

ns

3-8

tPHZ

Output Disable Time

5.0

1.0

6.0

9.5

1.0

11.0

1.0

10.0

ns

3-7

tpLZ

Output Disable Time

5.0

1.0

4.5

7.5

1.0

9.0

1.0

8.5

ns

3-8

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

50.0

pF

Vcc=5.5 V

5-128

AC257 • ACT257
54AC/74AC257 • 54ACT/74ACT257
Quad 2-lnput Multiplexer With 3-State Outputs
Description

Connection Diagrams

The 'ACI'ACT257 is a quad 2-input multiplexer with
3-state outputs. Four bits of data from two sources
can be selected using a Common Data Select
input. The four outputs present the selected data
in true (noninverted) form. The outputs may be
switched to a high impedance state by placing a
logic HIGH on the common Output Enable (DE)
input, allowing the outputs to interface directly
with bus-oriented systems.
•
•
•
•

Multiplexer Expansion by Tying Outputs Together
Noninverting 3-State Outputs
Outputs Source/Sink 24 mA
'ACT257 has TTL-Compatible Inputs
Pin Assignment
for DIP, Flatpak and SOIC

Ordering Code: See Section 6
Logic Symbol

I1b

lOb

NC

Za

11a

iIl[l]iIl[§J0
Zb

s

[II

[!]

NC

[ill

ITl NC

Zd

[j]

~ Vee

I"

[j]

~OE

[4][j]~Im~
IOd

S

DE
lOa - 10d
l1a - 11d

Za - Zd

Zc

NC

11c

IDe

Pin Assignment
for LeC

Pin Names
Common Data Select Input
3-State Output Enable Input
Data Inputs from Source 0
Data Inputs from Source 1
3-State Multiplexer Outputs

5-129

100

[Ijs

GND ~

•

AC257 • ACT257
Functional Description
The 'ACI'ACT257 is a quad 2-input multiplexer with
3-state outputs. It selects four bits of data from
two sources under control of a Common Data
Select input. When the Select input is LOW, the lox
inputs are selected and when Select is HIGH, the
I1x inputs are selected. The data on the selected
inputs appears at the outputs in true (non inverted)
form. The device is the logic implementation of a
4-pole, 2-position switch where the position of the
switch is determined by the logic levels supplied
to the Select input. The logic equations for the
outputs are shown below:

the outputs are tied together, all but one device
must be in the high impedance state to avoid high
currents that would exceed the maximum ratings.
Designers should ensure the Output Enable signals
to 3-state devices whose outputs are tied together
are designed so there is no overlap.

Truth Table

Za == OE-(11a-S + 10a-S)
Zb == OE-(11b-S + 10b-S)
Zc == 0E-(11C-S + 10c-S)
Zd == OE-( 11d-S + 10d-S)
When the Output Enable input (OE) is HIGH, the
outputs are forced to a high impedance state. If

Output
Enable

Select
Input

Data
Inputs

OE

S

10

11

Z

H
L
L
L
L

X

X
X
X

X

H
H
L
L

L
H

X
X

Z
L
H
L
H

L
H

Outputs

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z= High Impedance

logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-130

AC257 • ACT257
DC Characteristics (unless otherwise specified)
Symbol

54AC/ACT

Parameter

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Iccllnput (,ACT257)

1.6

74AC/ACT

160

Units

Conditions

/LA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

/LA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

rnA

VIN = Vcc - 2.1 V
Vcc=5.5 V,
TA = Worst Case

80

AC Characteristics

Symbol

Vcc'
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Min

Typ
5.0
4.0

tPLH
tPHL
tPLH

Propagation Delay
S to Zn

tPHL

Propagation Delay
S to Zn

3.3
5.0

tpzH

Output Enable Time

3.3
5.0

6.5
5.0

tPZL

Output Enable Time

3.3
5.0

5.5
5.0

tPHZ

Output Disable Time

3.3
5.0

5.5
5.0

tpLZ

Output Disable Time

3.3
5.0

5.5
5.0

Max

Max

Units

Fig.
No.

ns

3·5

ns

3-5

ns

3-6

ns

3-6

ns

3-7

Max

j'

•

i

n'S

3·8

·Voltage Range 3.3 is 3.0 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
Information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·131

I

AC257 • ACT257
AC Characteristics

Symbol

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Units

Fig.
No.

Min

Typ

Max

Min

Max

Min

Max

5.0

1.0

5.0

7.0

1.0

8.0

1.0

7.5

ns

3·6

Propagation Delay
In to Zn

5.0

1.0

6.0

7.5

1.0

9.5

1.0

8.5

ns

3·6

tPLH

Propagation Delay
S to Zn

5.0

1.0

7.0

9.5

1.0

11.5

1\.0

10.5

ns

3·6

tPHL

Propagation Delay
S to Zn

5.0

1.0

7.0

10.5

1.0

12.5

1.0

11.5

ns

3·6

tPZH

Output Enable Time

5.0

1.0

6.0

8.0

1.0

9.5

1.0

9.0

ns

3·7

tPZL

Output Enable Time

5.0

1.0

6.0

8.0

1.0

9.5

1.0

9.0

ns

3·8

tPHZ

Output Disable Time

5.0

1.0

6.5

9.0

1.0

10.5

1.0

10.0

ns

3·7

tpLZ

Output Disable Time

5.0

1.0

6.0

7.5

1.0

9.0

1.0

8.5

ns

3·8

tPLH

Propagation Delay
In to Zn

tPHL

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vec=5.5 V

Cpo

Power Dissipation
Capacitance

50.0

pF

Vcc=5.5 V

5·132

AC258 • ACT258
54AC/74AC258 • 54ACT/74ACT258
Quad 2-lnput Multiplexer With 3-State Outputs
Connection Diagrams

Description
The 'ACI'ACT258 is a quad 2-input multiplexer with
3-state outputs. Four bits of data from two sources
can be selected using a common data select input.
The four outputs present the selected data in the
complement (inverted) form. The outputs may be
switched to a high impedance state with a HIGH
on the common Output Enable (DE) input, allowing
the outputs to interface directly with bus-oriented
sytems.

•
•
•
•

Multiplexer Expansion by Tying Outputs Together
Inverting 3-State Outputs
Outputs Source/Sink 24 rnA
'ACT258 has TTL-Compatible Inputs
Pin Assignment
for DIP, Flatpak and SOIC

Ordering Code: See Section 6
Logic Symbol

11b

lob

NC

Za

ha

w[lJ[]]Wm
[lJ

Zb []]

s

•

10,

GND

[1Q]

[2Js

NC

[j]

ITl NC

Zd

I!?l

~ Vee

[i]j5E

1,,1i]]
~[i]][i]]I!Zl[i]]
IOd

ZC

NC

he

loc

Pin Assignment
for LCC

Pin Names
S

oe:
lOa - IOd
l1a - I1d
Za - Zd

Common Data Select Input
3-State Output Enable Input
Data Inputs from Source 0
Data Inputs from Source 1
3-State Inverting Data Outputs

5-133

I

AC258 • ACT258
Functional Description
maximum ratings. Designers should ensure that
Output Enable signals to 3-state devices whose
outputs are tied together are designed so there is
no overlap.

The 'ACI'ACT258 is a quad 2-input multiplexer with
3-state outputs. It selects four bits of data from
two sources under control of a common Select
input (S). When the Select input is LOW, the lox
inputs are selected and when Select is HIGH, the
11x inputs are selected. The data on the selected
inputs appears at the outputs in inverted form. The
'ACI'ACT258 is the logic implementation of a
4-pole, 2-position switch where the position of the
switch is determined by the logic levels supplied
to the Select input. The logic equations for the
outputs are shown below:

Truth Table

Za =Q'Eo(l1a oS + 10aoS)
Zb =OEo(l1b OS + 10bOS)
Zc = Q'Eo(l1c o S + locoS)
Zd = Q'EO(l1d OS + 10dOS)

Output
Enable

Select
Input

Data
Inputs

OE

S

10

11

Z

H
L
L
L
L

X
H
H
L
L

X
X
X
L
H

X
L
H
X
X

H
L
H
L

Outputs

Z

H = HIGH Voltage Level
L =LOW Voltage Level
X= Immaterial
Z =High Impedance

When the Output Enable input (OE) is HIGH, the
outputs are forced to a high impedance state. If
the outputs of the 3-state devices are tied together,
all but one device must be in the high impedance
state to avoid high currents that would exceed the

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-134

AC258 • ACT258
DC Characteristics (unless otherwise specified)
Symbol

Parameter

74AC/ACT

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Icc/lnput (,ACT258)

1.6

160

Conditions

Units

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

mA

VIN=Vcc-2.1 V,
Vcc=5.5 V,
TA = Worst Case

80

AC Characteristics

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
In to Zn

3.3
5.0

1.0
1.0

6.0
4.5

9.5
7.5

1.0
1.0

12.0
9.5

1.0
1.0

11.0
8.5

ns

3·5

tPHL

Propagation Delay
In to Zn

3.3
5.0

1.0
1.0

5.0
4.0

8.5
6.5

1.0
1.0

10.5
7.5

1.0
1.0

9.5
7.0

ns

3·5

tPLH

Propagation Delay
S to Zn

3.3
5.0

1.0
1.0

7.5
6.0

12.0
9.5

1.0
1.0

15.0
12.0

1.0
1.0

14.0
10.5

ns

3·6

tPHL

Propagation Delay
S to Zn

3.3
5.0

1.0
1.0

7.5
5.5

11.5
9.0

1.0
1.0

14.0
10.5

1.0
1.0

13.0
10.0

ns

3·6

tPZH

Output Enable Time

3.3
5.0

1.0
1.0

6.0
4.5

9.5
7.5

1.0
1.0

11.5
9.0

1.0
1.0

10.5
8.5

ns

3·7

tPZL

Output Enable Time

3.3
5.0

1.0
1.0

5.5
5.5

9.0
7.0

1.0
1.0

10.5
8.5

1.0
1.0

10.0
8.0

ns

3·8

tPHZ

Output Disable Time

3.3
5.0

1.0
1.0

5.5
5.5

10.0
8.5

1.0
1.0

11.5
9.5

1.0
1.0

11.5
9.0

ns

3·7

tpLZ

Output Disable Time

3.3
5.0

1.0
1.0

5.5
5.0

9.0
7.0

1.0
1.0

10.5
8.5

1.0
1.0

10.0
8.0

ns

3·8

•

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

i

I
5·135

II

AC258 • ACT258
AC Characteristics

Symbol

Parameter

Vcc·
(V)

74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA=-40°C
to +85°C
CL=50 pF

Min

Min

Max

Fig.
No.

Min

Typ

Max

5.0

1.0

6.5

8.5

1.0

9.5

ns

3-5

Propagation Delay
In to Zn

5.0

1.0

5.5

7.5

1.0

8.0

ns

3·5

tPLH

Propagation Delay
S to Zn

5.0

1.0

7.5

10.5

1.0

11.5

ns

3-6

tPHL

Propagation Delay
S to Zn

5.0

1.0

7.0

9.5

1.0

11.0

ns

3-6

tPZH

Output Enable Time

5.0

1.0

6.5

8.5

1.0

9.5

ns

3-7

tPZL

Output Enable Time

5.0

1.0

6.5

8.5

1.0

9.5

ns

3-8

tPHZ

Output Disable Time

5.0

1.0

7.0

9.0

1.0

10.0

ns

3-7

tpLZ

Output Disable Time

5.0

1.0

6.0

8.0

1.0

9.0

ns

3-8

tPLH

Propagation Delay
In to Zn

tPHL

Max

Units

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

CPD

Power Dissipation
Capacitance

55.0

pF

Vcc=5.5 V

5-136

AC273 • ACT273
54AC/74AC273 • 54ACT/74ACT273
Octal D Flip-Flop
Description

Connection Diagrams

The 'ACI'ACT273 has eight edge-triggered D-type
flip-flops with individual D inputs and Q outputs.
The common buffered Clock (CP) and Master Reset
(MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of
each D input, one setup time before the LOW-toHIGH clock transition, is transferred to the
corresponding flip-flop's Q output.
All outputs will be forced LOW independently of
Clock or Data inputs by a LOW voltage level on the
MR input. The device is useful for applications
where the true output only is required and the
Clock and Master Reset are common to all storage
elements.

•
•
•
•
•
•
•
•
•

Pin Assignment
for DIP, Flatpak and SOIC

Ideal Buffer for MOS Microprocessor or Memory
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Buffered, Asynchronous Master Reset
See '377 for Clock Enable Version
See '373 for Transparent Latch Version
See '374 for 3-State Version
Outputs Source/Sink 24 mA
'ACT273 has TTL-Compatible Inputs

03

02

Q2

01

•

01

[!][l][!][]][iJ

rn Do

03 []]

Ordering Code: See Section 6

GND

[jQJ

[I]

CP

[i]

[j]iiffi

0,

[g]

~ Vee

00

~07

0, ~

~[j][i]]@][j]

Logic Symbol

05

as

06

06

07

Pin Assignment
for Lee
CP
MR

Pin Names
Do - D7
MR
CP
Qo - Q7

Data Inputs
Master Reset
Clock Pulse Input
Data Outputs

I,
5-137

I

AC273 • ACT273
Logic Diagram
Do

06

05

cp--~:~~~------~+-------~~------~------~~------~~------~~------,

00

05

06

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

Mode Select· Function Table
Inputs
Operating Mode

Outputs

MR

CP

On

Qn

Reset (Clear)

L

X

X

L

Load '1'

H

1"

H

H

Load '0'

H

1"

L

L

H = HIGH Voltage Level
L= LOW Voltage Level
X = Immaterial
S= LOW-to-HIGH Clock Transition

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Icc/Input (,ACT273)

1.6

160

5-138

74AC/ACT

Units

Conditions

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

p.A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

80

AC273 • ACT273
AC Characteristics

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Max

Max

Units

Fig.
No.

MHz

3·3

Max

Min

Typ

fmax

Maximum Clock
Frequency

3.3
5.0

90
140

125
175

tPLH

Propagation Delay
Clock to Output

3.3
5.0

1.0
1.0

7.0
5.5

12.5
9.0

1.0
1.0

19.0
11.0

1.0
1.0

14.0
10.0

ns

3-6

tPHL

Propagation Delay
Clock to Output

3.3
5.0

1.0
1.0

7.0
5.0

13.0
10.0

1.0
1.0

16.0
11.5

1.0
1.0

14.5
11.0

n5

3-6

tPHL

Propagation Delay
MR to Output

3.3
5.0

1.0
1.0

7.0
5.0

13.0
10.0

1.0
1.0

16.0
11.5

1.0
1.0

14.0
10.5

ns

3-6

75
95

75
125

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

•

AC Operating Requirements

Symbol

Parameter

Vcc·
(V)

ts

Setup Time, HIGH or
LOW, Data to CP

3.3
5.0

th

Hold Time, HIGH or LOW
Data to CP

tw

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

3.5
2.5

5.5
4.0

6.5
5.0

6.0
4.5

ns

3-9

3.3
5.0

-2.0
-1.0

0
1.0

0
1.0

0
1.0

ns

3-9

Clock Pulse Width
HIGH or LOW

3.3
5.0

3.5
2.5

5.5
4.0

6.5
5.0

6.0
4.5

ns

3-6

tw

MR Pulse Width
HIGH or LOW

3.3
5.0

2.0
1.5

5.5
4.0

6.5
5.0

6.0
4.5

ns

3-6

tree

Recovery Time
MR to CP

3.3
5.0

1.5
1.0

3.5
2.0

4.5
3.0

4.5
3.0

ns

3-9

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-139

I
I

AC273 • ACT273
AC Characteristics
74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA=-40°C
to + 85°C
CL=50 pF

Min

Min

Units

Fig.
No.

MHz

3-3

ns

3-6

Units

Fig.
No.

ts

ns

3·9

th

ns

3-9

Sym

Max

Max

fmax

tPLH

Propagation Delay
Clock to Output

tPHL

Propagation Delay
Clock to Output

5.0

tPHL

Propagation Delay
MR to Output

5.0

7.0

'Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements
74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Guaranteed Minimum

tw

Clock Pulse Width
HIGH or LOW

5.0

tw

MR Pulse Width,
HIGH or LOW

5.0

2.5

~-6

tree

Recovery Time
MR to CP

5.0

-1.0

3-6

3-6

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-140

AC273 • ACT273
Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

50.0

pF

Vcc=5.5 V

•

5-141

AC299 • ACT299
54AC/74AC299 • 54ACT/74ACT299
8-lnput Universal Shift/Storage Register With Common Parallel I/O Pins
Connection Diagrams

Description
The 'ACI'ACT299 is an 8-bit universal shift/storage
register with 3-state outputs. Four modes of
operation are possible: hold (store), shift left, shift
right and load data. The parallel load inputs and
flip-flop outputs are multiplexed to reduce the total
number of package pins. Additional outputs are
provided for flip-flops Qo, Q7 to allow easy serial
cascading. A separate active LOW Master Reset is
used to reset the register.
• Common Parallel I/O for Reduced Pin Count
• Additional Serial Inputs and Outputs for
Expansion
• Four Operating Modes: Shift Left, Shift Right,
Load and Store
• 3-State Outputs for Bus-Oriented Applications
• Outputs Source/Sink 24 mA
• 'ACT299 has TTL-Compatible Inputs

Pin Assignment
for DIP, Flatpak and SOIC

Ordering Code: See Section 6

00 1/00 1/02

will III
Logic Symbol

1104

1/06

ffim

MRIIi

[3]0102

mOE.

GNO[i]j

oso[i]
So

CP[g]

s.

IIO.~

ITlso
~vcc
~Sl

cp
~~[6]IiIl[6]
1103 1/05 1/07 07 OS7

Pin Assignment
for LCC
Pin Names
CP
DSo
DS7
So, S1
QR

0E1, 0E2
1/00 - 1/07
Qo, Q7

Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset
3-State Output Enable Inputs
Parallel Data Inputs or
3-State Parallel Outputs
Serial Outputs

5-142

AC299 • ACT299
Logic Diagram
OS7

H--t>-'- 1107

H-H>'-+'- 1106

H-H>'-+'- 1105

•
1100

oSo

cp

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-143

I

AC299 • ACT299
A HIGH signal on either OEl or 0E2 disables the
3-state buffers and puts the I/O pins in the high
impedance state. In this condition the shift, hold,
load and reset operations can still occur. The
3-state buffers are also disabled by HIGH signals
on both So and Sl in preparation for a parallel load
operation.

Functional Description
The 'AC/'ACT299 contains eight edge-triggered 0type flip-flops and the interstage logic necessary to
perform synchronous shift left, shift right, parallel
load and hold operations. The type of operation is
determined by So and Sl, as shown in the Truth
Table. All flip-flop outputs are brought out through
3-state buffers to separate 110 pins that also serve
as data inputs in the parallel load mode. 00 and 07
are also brought out on other pins for expansion in
serial shifting of longer words.

Truth Table
Inputs

A LOW signal on MR overrides the Select and CP
inputs and resets the flip·flops. All other state
changes are initiated by the rising edge of the
clock. Inputs can change when the clock is in
either state provided only that the recommended
setup and hold times, relative to the rising edge of
CP, are observed.

MR

Sl

So

CP

L

X

X

X

H
H

H
L

H
H

.r
.r

H

H

L

.r

H

L

L

X

Response

Asynchronous Reset;
00 - 07= LOW
Parallel Load; liOn-On
Shift Right; OSO-OO,
00-01, etc.
Shift Left; OS7-07,
07-06, etc.
Hold

H = HIGH Voltage Level
L LOW Voltage Level
X Immaterial
I= LOW·to·HIGH Transition

=
=

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Ouiescent
Supply Current

Icc

Maximum Ouiescent
Supply Current

8.0

Iccl

Maximum Additional
Icc/Input ('ACT299)

1.6

160

5·144

74AC/ACT

Units

Conditions

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = 25°C

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V
TA = Worst Case

80

AC299 • ACT299
AC Characteristics

Vee·
(V)

Symbol

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Min

Typ
55
130

Max

Max

Units

Fig.
No.

Max
MHz

3·3

tPLH

ns

3·6

tPHL

ns

3·6

fmax

tPLH

Propagation Delay
CP to lIOn

ns

3-6

tPHL

Propagation Delay
CP to lIOn

ns

3·6

tPLH

Propagation Delay
MR to lIOn

3.3
5.0

ns

3·6

tPHL

Propagation Delay
MR to lIOn

3.3
5.0

31.0
13.0

3·6

tPZH

Output Enable Time
OE to lIOn

3.3
5.0

24.0
10.0

3-7

tPZL

DE: to

Output Enable Time
lIOn

3.3
5.0

24.0
10.0

ns

3-8

tPHZ

DE: to

Output Disable Time
lIOn

3.3
5.0

25.0
13.0

ns

3·7

Output Disable Time
lIOn

3.3
5.0

24.0
12.0

ns

3·8

tpLZ

DE: to

•

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·145

I

AC299 • ACT299
AC Operating Requirements
74AC

54AC

74AC

TA::;:: + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

ns

3·9

th

ns

3·9

ns

3·9

Vee*
(V)

ts

Setup Time,
HIGH or LOW
liOn, OSo or OS7 to CP

th

Hold Time, HIGH or LOW
liOn, OSo or OS7 to CP

3.3
5.0

0
0

3·9

tw

CP Pulse Width,
HIGH or LOW

3.3
5.0

9.0
4.0

3-6

tw

MR Pulse Width, LOW

3.3
5.0

7.0
4.0

3·6

tree

Recovery Time,
MR to CP

3.3
5.0

0
0

ns

3·9

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·146

AC299 • ACT299
AC Characteristics

Symbol

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Units

Fig.
No.

Max

fmax

125

MHz

3-3

tPLH

11.0

ns

3-6

ns

3-6

tPHL
tPLH

Propagation Delay
CP to lIOn

ns

3-6

tPHL

Propagation Delay
CP to lIOn

ns

3-6

tPLH

Propagation Delay
MR to 00 or 07

5.0

ns

3-6

tPHL

Propagation Delay
MR to 00 or 07

5_0

13.0

3-6

5.0

10.0

3-7

5.0

10.0

ns

3-8

5.0

12.0

ns

3-7

5.0

11.0

ns

3-8

tPZH
tPZL
tPHZ
tpLZ

Output Enable Time

OE to lIOn
Output Enable Time
OE to lIOn
Output Disable Time

OE to lIOn
Output Disable Time

OE to lIOn

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-147

•

AC299 • ACT299
AC Operating Requirements

Vcc·
(V)

74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

ns

3·9

th

ns

3-9

ns

3-9

ns

3-9

ts

Setup Time,
HIGH or LOW
liOn, DSo or DS7 to CP

th

Hold Time, HIGH or LOW
liOn, DSo or DS7 to CP

5.0

0

tw

CP Pulse Width
HIGH or LOW

5.0

4.0

3-6

tw

MR Pulse Width, LOW

5.0

4.0

3-6

tree

Recovery Time,
MR to CP

5.0

0

3-9

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

pF

Vcc=5.5 V

pF

Vcc=5.5 V

Typ
CIN

Input Capacitance

Cpo

Power Dissipation
Capacitance

4.5

5-148

AC323 • ACT323
54AC/74AC323 • 54ACT/74ACT323
8-Bit Universal Shift/Storage Register
With Synchronous Reset and Common 110 Pins
Description

Connection Diagrams

The 'ACt'ACT323 is an a-bit universal shift/storage
register with 3-state outputs. Its function is similar
to the 'ACt' ACT299 with the exception of
Synchronous Reset. Parallel load inputs and flipflop outputs are multiplexed to minimize pin count.
Separate serial inputs and outputs are provided for
00 and 07 to allow easy cascading. Four operation
modes are possible: hold (store), shift left, shift
right and parallel load.
• Common Parallel I/O for Reduced Pin Count
• Additional Serial Inputs and Outputs for
Expansion
• Four Operating Modes: Shift Left, Shift Right,
Load and Store
• 3·State Outputs for Bus·Oriented Applications
• Outputs SourcelSink 24mA
• 'ACT323 has TTL·Compatible Inputs

Pin Assignment
for DIP, Flatpak and SOIC

Ordering Code: See Section 6
00 1100 1/02 1/04 1/06

~[i]~w[±]

Logic Symbol

mOl"

SAW
050

OS,

GND~

So

rnOE'1

DsoiTIl

5,

[j]So

cp[i2]

~vcc

CP
1/01 'i]

[!9]S1
[i4J[i][!9]I!D~
1/03 1/05 1/07 Q7

os?

Pin Assignment
for LCC

Pin Names
CP
DSo
DS7

So, Sl
SR

0E1, 0E2
1/00 - 1/07
00,07

Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Synchronous Reset Input
3-State Output Enable Inputs
Multiplexed Parallel Data Inputs or
3-State Parallel Data Outputs
Serial Outputs

5-149

AC323 • ACT323
Logic Diagram
DS7

Il

.---

~~

ur

cp

o

0

I107

L

'--

~

~~

"~~
it

cp

o

-"

0

I10 6

L

'----

.--cp

o

0

I105

L

'--

~

~~

cp

o

0

I

L

~

,---

c=~

cp

o

0
'----

ilh

I~~

'L

==nJ

I

cp

~

'L

110 2

~

~~

o 0
'----

'L

.---

ill:

~~
,. . ., r;:::::Ur- i
I

cp

cp

o

0

'L

'--

1/0 0

\

r.:-I

DSo

-SR

OE1

CP

00

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-150

AC323 • ACT323
Functional Description
The 'ACI'ACT323 contains eight edge-triggered
Ootype flip-flops and the interstage logic necessary
to perform synchronous reset, shift left, shift right,
parallel load and hold operations. The type of
operation is determined by So and 51 as shown in
the Mode Select Table. All flip-flop outputs are
brought out through 3-state buffers to separate
1/0 pins that also serve as data inputs in the
parallel load mode. Qo and Q7 are also brought out
on other pins for expansion in serial shifting of
longer words.

rising edge of CPo All other state changes are also
initiated by the LOW-to-HIGH CP transition. Inputs
can change when the clock is in either state
provided only that the recommended setup and
hold times, relative to the rising edge of CP, are
observed.
A HIGH signal on either OEl or 0E2 disables the
3-state buffers and puts the 1/0 pins in the high
impedance state. In this condition the shift, load,
hold and reset operations can still occur. The
3-state buffers are also disabled by HIGH signals
on both So and 51 in preparation for a parallel load
operation.

A LOW signal on SR overrides the Select inputs
and allows the flip-flops to be reset by the next

Mode Select Table
Inputs
Response
SR

51

So

CP

L
H
H
H
H

X

X

H
L
H
L

H
H
L
L

.r
.r
.r
.r
X

•

Synchronous Reset; QO-Q7= LOW
Parallel Load; I/0n-Qn
Shift Right; OSo-Qo, QO-Ql, etc .
Shift Left; OS7-Q7, Q7-QS, etc .
Hold

=
=

H HIGH Voltage Level
L LOW Voltage Level
X= Immaterial
I= LOW-to-HIGH Clock Transition

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

IccT

Maximum Additional
Iccllnput (,ACT323)

1.6

160

5-151

74AC/ACT

Units

Conditions

J1.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

J1.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V
TA = Worst Case

80

AC323 • ACT323
AC Characteristics

Vee*

Symbol

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Units

Fig.
No.

MHz

3·3

tPLH

ns

3·6

tPHL

ns

3-6

ns

3-6

ns

3-6

(V)

Min

Typ
55
130

fmax

Max

Max

Max

tPLH

Propagation Delay
CP to liOn

tPHL

Propagation Delay
CP to liOn

3.3
5.0

tPZH

Output Enable Time

3.3
5.0

24.0
10.0

3-7

tPZL

Output Enable Time

3.3
5.0

24.0
10.0

3-8

tPHZ

Output Disable Time

3.3
5.0

25.0
13.0

3-7

tpLZ

Output Disable Time

3.3
5.0

24.0
12.0

ns

3-8

·Voltage Range 3.3 is 3.0 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-152

AC323 • ACT323
AC Operating Requirements

Vee·
(V)

Symbol

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Units

Fig.
No.

ts

ns

3·9

th

ns

3·9

ns

3·9

ns

3·9

Typ

Guaranteed Minimum

ts

Setup Time,
HIGH or LOW
liOn, OSo, OS7 to CP

th

Hold Time, HIGH or LOW
liOn, OSo, OS7 to CP

3.3
5.0

ts

Setup Time,
HIGH or LOW
SR to CP

3.3
5.0

4.0
2.0

3-9

th

Hold Time, HIGH or LOW
SR to CP

3.3
5.0

0
0

3-9

tw

CP Pulse Width
HIGH or LOW

3.3
5.0

9.0
4.0

ns

3-6

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-153

•

AC323 • ACT323
AC Characteristics

Symbol

Vee*
(V)

74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ
125

1max

tPLH

Max

Max

Units

Fig.

No.

Max
MHz

3·3

ns

3·6

tPHL

Propagation Delay
CP to 00 or 07

ns

3·6

tPLH

Propagation Delay
CP to liOn

ns

3·6

tPHL

Propagation Delay
CP to liOn

5.0

ns

3·6

tPZH

Output Enable Time

5.0

10.0

3·7

tPZL

Output Enable Time

5.0

10.0

3·8

tPHZ

Output Disable Time

5.0

12.0

3·7

tpLZ

Output Disable Time

5.0

11.0

3·8

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·154

AC323 • ACT323
AC Operating Requirements

Vcc·
(V)

Symbol

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ns

3·9

T

ts

SetuP!:r;rme',)
HIGH or LQItv,i
So or Sl to CID

th

Hold Time, HIGH Orl0¥'
1(5.0
So or Sl to C p o " 'i", ~","

ns

3·9

ts

Setup Time,
HIGH or LOW
liOn, DSo, DS7 to CP

ns

3·9

th

Hold Time, HIGH or LOW
liOn, DSo, DS7 to CP

5.0

ns

3·9

ts

Setup Time,
HIGH or LOW
SR to CP

5.0

2.0

3·9

th

Hold Time, HIGH or LOW
SR to CP

5.0

0

3·9

tw

CP Pulse Width
HIGH or LOW

5.0

4.0

J

5.0

"

ns

3·6

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

pF

Vcc=5.5 V

pF

Vcc=5.5 V

Typ
CIN

Input Capacitance

CPD

Power Dissipation
Capacitance

4.5

5·155

•

AC352 • ACT352
54AC/74AC352 • 54ACT/74ACT352
Dual 4-lnput Multiplexer
Description

Connection Diagrams

The 'ACI'ACT352 is a very high-speed dual 4-input
multiplexer with common Select inputs and
individual Enable inputs for each section. It can
select two bits of data from four sources. The two
buffered outputs present data in the inverted
(complementary) form. The 'ACI'ACT352 is the
functional equivalent of the 'ACI'ACT153 except
with inverted outputs.
•
•
•
•

Inverted Version of the 'AC/'ACT153
Separate Enables for Each Multiplexer
Outputs Source/Sink 24 rnA
'ACT352 has TTL-Compatible Inputs
Pin Assignment
for DIP, Flatpak and SOIC

Ordering Code: See Section 6

lOa

l1a

NC

12a

13a

1!l0[I][I][!]

Logie Symbol

z,[I]

[IjSl

GNO[iQj

[2jE,

NC[i]

[j]NC

2,[i]j

~Vcc

10,Ii]]

~Eb

[j]~~[i1J~
11b

S1

Za

lOb - 13b

SO, Sl

Ea
Eb
Za, Zb

So

Pin Assignment
for LCe

Pin Names
lOa - 13a

12b NC I3b

Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Enable Input
Side B Enable Input
Multiplexer Outputs

5-156

AC352 • ACT352
Functional Description
The 'ACI'ACT352 is a dual 4-input multiplexer. It
selects two bits of data from up to four sources
under the control of the common Select inputs
(So, S1). The two 4-input multiplexer circuits have
individual active LOW Enables (Ea, Eb) which can
be used to strobe the outputs independently. When
the Enables (Ea, Eb) are HIGH, the corresponding
output:; (la, lb) are forced HIGH.

The 'ACI'ACT352 can be used to move data from a
group of registers to a common output bus. The
particular register from which the data came would
be determined by the state of the Select inputs. A
less obvious application is as a function generator.
The 'AC/ACT352 can generate two functions of
three variables. This is useful for implementing
highly irregular random logic.

The logic equations for the outputs are shown
below:
la =Ea-(loa-S1-S0 + 11a-S1-S0 +
12a-S1-S0 + 13a-S1-S0)

lb = Eb-(lOb-S1-S0 + 11b-S1-So +
12b-S1-S0 + 13b-S1-So)

•
Truth Table
Inputs (a or b)

Select Inputs

Outputs

So

S1

E

10

11

12

13

l

X

X

X

L
L
H
H
L
L
H
H

L
L
L
L
H
H
H
H

H
L
L
L
L
L
L
L
L

X
X
X

X
X
X
X
X

X
X
X

H
H
L
H
L
H
L
H
L

L
H
X

X
X
X
X
X

L
H

X
X
X
X

X

X
X

L
H

X

X
X

L
H

H = HIGH Voltage Level
L LOW Voltage Level
X = Immaterial

=

5-157

AC352 • ACT352
Logic Diagram
Ea lOa

ha

12a

13a

So

So

hb

lOb

12b

Za
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54ACIACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Iccllnput (,ACT352)

1.6

160

5·158

74ACIACT

Units

Conditions

J.tA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

J.tA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V
TA=Worst Case

80

AC352 • ACT352
AC Characteristics

Parameter

Vee·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Units

No.

Max

ns

3·6

ns

3-6

Propagation Delay

3·6

En to Zn
Propagation Delay

En to Zn
Propagation Delay

In to Zn
Propagation Delay

In to Zn

Fig.

3.3
5.0
3.3
5.0

8.5
6.0

3.3
5.0

8.5
6.0

ns

3-5

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-159

•

AC352 • ACT352
AC Characteristics
74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA=-40°C
to +85°C
CL=50 pF

Min

Min

Typ

Max

Max

Units

Fig.
No.

ns

3-6

Max

tPLH
tPHL

Propagation Delay
Sn to Zn

ns

3-6

tPLH

Propagation Delay
"En to Zn

ns

3-6

tPHL

Propagation Delay
"En to Zn

5.0

5.5

3-6

tPLH

Propagation Delay
In to Zn

5.0

6.5

,/3-5

tPHL

Propagation Delay
In to Zn

5.0

6.5

3-5

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

pF

Vcc=5.5 V

pF

Vcc= 5.5 V

Typ

CIN

Input CapaCitance

Cpo

Power Dissipation
Capacitance

4.5

5-160

AC353 • ACT353
54AC/74AC353 • 54ACT/74ACT353
Dual 4-lnput Multiplexer With 3-State Outputs
Connection Diagrams

Description
The 'ACI'ACT353 is a dual 4-input multiplexer with
3-state outputs. It can select two bits of data from
four sources using common Select inputs. The
outputs may be individually switched to a high
impedance state with a HIGH on the respective
Output Enable (OE) inputs, allowing the outputs to
interface directly with bus-oriented systems.
•
•
•
•
•

Inverted Version of the 'AC/'ACT253
Multifunction Capability
Separate Enables for Each Multiplexer
Outputs Source/Sink 24 rnA
'ACT353 has TTL-Compatible Inputs
Pin Assignment
for DIP, Flatpak and SOIC

Ordering Code: See Section 6

lOa

11a

NC 12a

13a

lli][l]m[]][I]

Logic Symbol

ms,

z, []]

[]JOE,

GNO[iQj
loa

t 1a

12a 13a lOb 11 b 12b IJb OEb

NCITIl

IT] NC

Zb~

@Q]Vee

Ii]]

~OEb

lOb

[i3J[i5][i5][il][i5]
I1b

12b

NC

13b

So

Pin Assignment
for LCC and PCC

Pin Names
lOa - 13a
lOb - 13b

SO, S1

OEa
OEb

Za, Zb

Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Output Enable Input
Side B Output Enable Input
3-State Outputs

5-161

•

AC353 • ACT353
Functional Description

If the outputs of 3-state devices are tied together,
all but one device must be in the high impedance
state to avoid high currents that would exceed the
maximum ratings. Designers should ensure that
Output Enable signals to 3-state devices whose
outputs are tied together are designed so that
there is no overlap.

The 'ACI'ACT353 contains two identical 4-input
multiplexers with 3-state outputs. They select two
bits from four sources selected by common Select
inputs (So, S1). The 4-input multiplexers have
individual Output Enable (OEa, OEb) inputs which,
when HIGH, force the outputs to a high impedance
(High Z) state. The logic equations for the outputs
are shown below:
Za = OEa-(loa-S1-So + l1a-S1-S0 +
12a-S1-S0 + 13a-S1-S0)
Zb =OEb-(lob-S1-So + 11b-S1-So +
12b-S1-S0 + 13b-S1-S0)

Truth Table
Select
Inputs

Data Inputs

Output
Enable

Outputs

So

S1

10

11

12

13

OE

Z

X
L
L
H
H
L
L
H
H

X
L
L
L
L
H
H
H
H

X
L
H
X
X
X
X
X
X

X
X
X
L
H
X
X
X
X

X
X
X
X
X
L
H
X
X

X
X
X
X
X
X
X
L
H

H
L
L
L
L
L
L
L
L

Z
H
L
H
L
H
L
H
L

H = HIGH Voltage Level
L= LOW Voltage Level
X = Immaterial
Z = High Impedance

Address inputs 80 and 81 are common to both sections.

logic Diagram
lab

s,

So

10,

~ ~

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-162

AC353 • ACT353
DC Characteristics (unless otherwise specified)
Symbol

Parameter

74AC/ACT

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

B.O

IccT

Maximum Additional
Iccllnput (,ACT353)

1.6

Conditions

p,A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

B.O

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA=Worst Case

BO

160

Units

AC Characteristics

Vcc·
(V)

Symbol

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to +B5°C
CL=50 pF

Min

Min

Min

Typ
9.0
6.5

tPLH
tPHL

Max

Max

Units

Fig.
No.

ns

3-6

ns

3-6

Max

tPLH

Propagation Delay
In to Zn

ns

3·5

tPHL

Propagation Delay
In to Zn

ns

3-5

tPZH

Output Enable
Time

3.3
5.0

ns

3·7

tPZL

Output Enable
Time

3.3
5.0

6.0
4.5

3-B

tPHZ

Output Disable
Time

3.3
5.0

7.0
5.5

3·7

tpLZ

Output Disable
Time

3.3
5.0

5.5
4.0

3·B

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·163

•

AC353 • ACT353
AC Characteristics

Symbo

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Units

Fig.
No.

tPLH

ns

3·6

tPHL

ns

3·6

ns

3·5

ns

3·5

Min

Typ

Max

Max

Max

tPLH

Propagation Delay
In to Zn

tPHL

Propagation Delay
In to Zn

5.0

tPZH

Output Enable Time

5.0

4.5

3·7

tPZL

Output Enable Time

5.0

5.0

3·8

tPHZ

Output Disable Time

5.0

6.0

3·7

tpLZ

Output Disable Time

5.0

4.5

3·8

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

pF

Vcc=5.5 V

pF

Vcc=5.5 V

Typ
CIN

Input Capacitance

Cpo

Power Dissipation
Capacitance

4.5

5·164

AC373 • ACT373
54AC/74AC373 • 54ACT/74ACT373
Octal Transparent Latch With 3-State Outputs
Description
The 'ACI'ACT373 consists of eight latches with
3-state outputs for bus organized system
applications. The flip-flops appear transparent to
the data when Latch Enable (LE) is HIGH. When LE
is LOW, the data that meets the setup time is
latched. Data appears on the bus when the Output
Enable (01:) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
•
•
•
•

Connection Diagrams

Eight Latches In a Single Package
3-State Outputs for Bus Interfacing
Outputs Source/Sink 24 mA
'ACT373 has TTL-Compatible Inputs

•

Ordering Code: See Section 6
Pin Assignment
for DIP, Flatpak and SOIC

Logic Symbol

D3

LE

D2

02

[!]1Il

[!]

0,

0,

mw

OE
03

[!]

[3J Do

GND ~

lE

Truth Table
Inputs

Outputs

OE

LE

Dn

On

H
L
L
L

X
H
H
L

X
L
H
X

Z
L
H
00

[2J

o,~

@I

D, ~

~O'
~[i5J ~ @]~
Ds

Os

0,

06

D,

Pin Assignment
for LCC
Pin Names
Do - 07
Data Inputs
LE
Latch Enable Input
OE
Output Enable Input
00 - 07
3-State Latch Outputs

H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
00 = Previous 00 before
LOW-to-HIGH Transition of Clock

5-165

00

mOE

1m

Vee

AC373 • ACT373
Functional Description
The 'ACI'ACT373 contains eight D-type latches with
3-state standard outputs. When the Latch Enable
(LE) input is HIGH, data on the Dn inputs enters
the latches. In this condition the latches are
transparent, i.e., a latch output will change state
each time its D input changes. When LE is LOW,
the latches store the information that was present

on the D inputs a setup time preceding the HIGHto-LOW transition of LE. The 3-state standard
outputs are controlled by the Output Enable (OE)
input. When OE is LOW, the standard outputs are
in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode
but this does not interfere with entering new data
into the latches.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

74AC/ACT

Units

Conditions

160

80

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

8.0

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

ICCT

Maximum Additional
Icc/lnput (,ACT373)

1.6

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

5·166

AC373 • ACT373
AC Characteristics

Symbol

Parameter

Vee*
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
Dn to On

3.3
5.0

1.0
1.0

10.0
7.0

13.5
9.5

1.0
1.0

16.5
11.5

1.0
1.0

15.0
10.5

ns

3·5

tPHL

Propagation Delay
Dn to On

3.3
5.0

1.0
1.0

9.5
7.0

13.0
9.5

1.0
1.0

16.0
11.5

1.0
1.0

14.5
10.5

ns

3-5

tPLH

Propagation Delay
LE to On

3.3
5.0

1.0
1.0

10.0
7.5

13.5
9.5

1.0
1.0

16.5
12.0

1.0
1.0

15.0
10.5

ns

3-6

tPHL

Propagation Delay
LE to On

3.3
5.0

1.0
1.0

9.5
7.0

12.5
9.5

1.0
1.0

15.0
11.0

1.0
1.0

14.0
10.5

ns

3-6

tPZH

Output Enable Time

3.3
5.0

1.0
1.0

9.0
7.0

11.5
8.5

1.0
1.0

14.0
10.5

1.0
1.0

13.0
9.5

ns

3-7

tPZL

Output Enable Time

3.3
5.0

1.0
1.0

8.5
6.5

11.5
8.5

1.0
1.0

13.5
10.0

1.0
1.0

13.0
9.5

ns

3-8

tPHZ

Output Disable Time

3.3
5.0

1.0
1.0

10.0
8.0

12.5
11.0

1.0
1.0

16.0
13.5

1.. 0
1.0

14.5
12.5

ns

3-7

tpLZ

Output Disable Time

3.3
5.0

1.0
1.0

8.0
6.5

11.5
8.5

1.0
1.0

13.0
10.5

1.0
1.0

12.5
10.0

ns

3-8

Units

Fig.
No.

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements

Symbol

Parameter

Vee*
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

ts

Setup Time,
HIGH or LOW
Dn to LE

3.3
5.0

3.5
2.0

5.5
4.0

6.5
5.0

6.0
4.5

ns

3-9

th

Hold Time, HIGH or LOW
Dn to LE

3.3
5.0

-3.0
-1.5

0
0

1.0
1.0

0
0

ns

3-9

tw

LE Pulse Width, HIGH

3.3
5.0

4.0
2.0

5.5
4.0

6.5
5.0

6.0
4.5

ns

3-6

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-167

•

AC373 • ACT373
AC Characteristics

Symbol

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
Dn to On

5.0

1.0

8.5

10.0

1.0

12.5

1.0

11.5

ns

3-5

tPHL

Propagation Delay
Dn to On

5.0

1.0

8.0

10.0

1.0

12.5

1.0

11.5

ns

3-5

tPLH

Propagation Delay
LE to On

5.0

1.0

8.5

11.0

1.0

12.5

1.0

11.5

ns

3-6

tPHL

Propagation Delay
LE to On

5.0

1.0

8.0

10.0

1.0

11.5

1.0

11.5

ns

3-6

tPZH

Output Enable Time

5.0

1.0

8.0

9.5

1.0

11.5

1.0

10.5

ns

3-7
3-8

tPZL

Output Enable Time

5.0

1.0

7.5

9.0

1.0

11.0

1.0

10.5

ns

tPHZ

Output Disable Time

5.0

1.0

9.0

11.0

1.0

14.0

1.0

12.5

ns

3-7

tpLZ

Output Disable Time

5.0

1.0

7.5

8.5

1.0

11.0

1.0

10.0

ns

3-8

Units

Fig.
No.

·Voltage Range 5.0 Is 5.0 V ± 0.5 V

AC Operating Requirements

Symbol

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

ts

Setup Time,
HIGH or LOW
Dn to LE

5.0

3.0

7.0

8.5

8.0

ns

3-9

th

Hold Time, HIGH or LOW
Dn to LE

5.0

0

0

1.0

1.0

ns

3-9

tw

LE Pulse Width, HIGH

5.0

2.0

7.0

8.5

8.0

ns

3-6

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
Information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·168

AC373 • ACT373

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

40.0

pF

Vcc=5.5 V

•

5·169

AC374 • ACT374
54AC/74AC374 • 54ACT/74ACT374
Octal O-Type Flip-Flop With 3-State Outputs
Description

Connection Diagrams

The 'ACI'ACT374 is a high-speed, low-power octal
Ootype flip-flop featuring separate Ootype inputs for
each flip-flop and 3-state outputs for bus-oriented
applications. A buffered Clock (CP) and Output
Enable ('0'1:) are common to all flip-flops.
Buffered Positive Edge-Triggered Clock
3-State Outputs for Bus-Oriented Applications
Outputs Source/Sink 24 mA
See '273 for Reset Version
See '377 for Clock Enable Version
See '373 for Transparent Latch Version
See '574 for Broadside Pinout Version
See '564 for Broadside Pinout Version with
Inverted Outputs
• 'ACT374 has TTL-Compatible Inputs

•
•
•
•
•
•
•
•

Pin Assignment
for DIP, Flatpak and SOIC

Ordering Code: See Section 6

03

Logic Symbol

02

02

01

0,

I!Jllll!lrnm
[!J

[!]Da

GNO~

[2J00

IIi]

[]JOE

03

Cp

CP
OE

O,~

~vcc

O'~

~O'

~~~@]~
05

05

06

Os

07

Pin Assignment
for LCC

Pin Names

Do - 07
CP

OE
00 - 07

Data Inputs
Clock Pulse Input
3·State Output Enable Input
3·State Outputs

5-170

AC374 • ACT374
Truth Table

Functional Description
The 'ACI'ACT374 consists of eight edge-triggered
flip-flops with individual Ootype inputs and 3-state
true outputs. The buffered clock and buffered
Output Enable are common to all flip-flops. The
eight flip-flops will store the state of their
individual 0 inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the
contents of the eight flip-flops are available at the
outputs. When the OE is HIGH, the outputs go to
the high impedance state. Operation of the OE
input does not affect the state of the flip-flops.

Inputs

Outputs

On

CP

OE

On

H
L

I
I
X

L
L
H

H
L

X

Z

=HIGH Voltage Level
=LOW Voltage Level

H
L
X=
Z=
j'

Immaterial
High Impedance
LOW·to·HIGH Transition

=

Logic Diagram
0,

Do

0,

0,

CP~I~>---~~~----~-+------~1------'--~----~-+------~1------'--~----,

•

OE

0,

00

0,

Os

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Icc/Input (,ACT374)

1.6

160

5·171

74AC/ACT

Units

Conditions

/LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

/LA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

80

AC374 • ACT374
AC Characteristics

Symbol

Parameter

Vee·
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Units

Fig.
No.

MHz

3·3

Max

fmax

Maximum Clock
Frequency

3.3
5.0

60
100

110
155

tPLH

Propagation Delay
CP to On

3.3
5.0

1.0
1.0

11.0
8.0

13.5
9.5

1.0
1.0

16.5
12.0

1.0
1.0

15.5
10.5

ns

3-6

tPHL

Propagation Delay
CP to On

3.3
5.0

1.0
1.0

10.0
7.0

12.5
9.0

1.0
1.0

15.0
11.0

1.0
1.0

14.0
10.0

ns

3-6

tPZH

Output Enable Time

3.3
5.0

1.0
1.0

9.5
7.0

11.5
8.5

1.0
1.0

14.0
10.5

1.0
1.0

13.0
9.5

ns

3-7

tPZL

Output Enable Time

3.3
5.0

1.0
1.0

9.0
6.5

11.5
8.5

1.0
1.0

14.0
10.5

1.0
1.0

13.0
9.5

ns

3-8

tPHZ

Output Disable Time

3.3
5.0

1.0
1.0

10.5
8.0

12.5
11.0

1.0
1.0

16.0
12.5

1.0
1.0

14.5
12.5

ns

3-7

tpLZ

Output Disable Time

3.3
5.0

1.0
1.0

8.0
6.5

11.5
8.5

1.0
1.0

13.0
10.5

1.0
1.0

12.5
10.0

ns

3-8

Units

Fig.
No.

60
95

60
100

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements

Symbol

Parameter

Vee·
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

ts

Setup Time,
HIGH or LOW
On to CP

3.3
5.0

2.0
1.0

5.5
4.0

6.5
5.0

6.0
4.5

ns

3-9

th

Hold Time, HIGH or LOW
On to CP

3.3
5.0

-1.0
-4.0

1.0
1.5

1.0
1.5

1.0
1.5

ns

3·9

tw

CP Pulse Width,
HIGH or LOW

3.3
5.0

4.0
2.5

5.5
4.0

6.5
5.0

6.0
4.5

ns

3-6

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-172

AC374 • ACT374
AC Characteristics

Symbol

Parameter

Vcc*
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Units

Fig.
No.

MHz

3·3

Max

fmax

Maximum Clock
Frequency

5.0

100

160

tPLH

Propagation Delay
CP to On

5.0

1.0

8.5

10.0

1.0

12.5

1.0

11.5

ns

3·6

tPHL

Propagation Delay
CP to On

5.0

1.0

8.0

9.5

1.0

12.0

1.0

11.0

ns

3·6

tPZH

Output Enable Time

5.0

1.0

8.0

9.5

1.0

11.5

1.0

10.5

ns

3·7

tPZL

Output Enable Time

5.0

1.0

8.0

9.0

1.0

11.5

1.0

10.5

ns

3·8

tPHZ

Output Disable Time

5.0

1.0

8.5

11.5

1.0

13.0

1.0

12.5

ns

3·7

tpLZ

Output Disable Time

5.0

1.0

7.0

8.5

1.0

11.0

1.0

10.0

ns

3·8

70

90

•

'Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements

Symbol

Parameter

Vcc*
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Setup Time,
HIGH or LOW
On to CP

5.0

1.0

7.0

5.5

5.5

ns

3·9

th

Hold Time, HIGH or LOW
On to CP

5.0

0

1.5

1.5

1.5

ns

3·9

tw

CP Pulse Width,
HIGH or LOW

5.0

2.0

7.0

5.0

5.0

ns

3·6

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·173

AC374 • ACT374

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

80.0

pF

Vcc=5.5 V

5-174

AC377 • ACT377
54AC/74AC377 • 54ACT/74ACT377
Octal D Flip-Flop With Clock Enable
Description
The 'AC/'ACT377 has eight edge-triggered, Ootype
flip-flops with individual 0 inputs and 0 outputs.
The common buffered Clock (CP) input loads all
flip-flops simultaneously, when the Clock Enable
(eE) is LOW.

Connection Diagrams

The register is fully edge-triggered. The state of
each 0 input, one setup time before the LOW-toHIGH clock transition, is transferred to the
corresponding flip-flop's 0 output. The 'Ci: input
must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable
operation.
• Ideal for Addressable Register Applications
• Clock Enable for Address and Data
Synchronization Applications
• Eight Edge-Triggered 0 Fllp·Flops
• Buffered Common Clock
• Outputs Source/Sink 24 mA
• See '273 for Master Reset Version
• See '373 for Transparent Latch Version
• See '374 for 3-State Version
• 'ACT377 has TTL-Compatible Inputs

•

Pin Assignment
for DIP, Flatpak and SOIC
03

02

02

01

01

[!]011l[!]0

Ordering Code: See Section 6

[II Do

03

[II

GND

!!Q]

[2J

CP

[j]

[iJOE

04

[g

~ Vee

!'ill 07

04 ~

Logic Symbol
~~[6]Im[6]
05

Os

06

06

07

Pin Assignment
for LCC

CP
OE

Pin Names
Data Inputs
Do - 07
Clock Enable (Active LOW)
'Ci:
Data Outputs
00 - 07
Clock Pulse Input
CP

5-175

00

AC377 • ACT377
Mode Select·Function Table
Inputs
Operating Mode

Outputs

CP

CE

On

an

Load '1'

I

L

H

H

Load '0'

I

L

L

L

Hold (Do Nothing)

I
X

H
H

X
X

No Change
No Change

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
I = LOW-to-H IG H Clock Transition

Logic Diagram

Do

03

05

06

CP
00

03

05

06

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-176

AC377 • ACT377
DC Characteristics (unless otherwise specified)
Symbol

54AC/ACT

Parameter

74AC/ACT

Units

Conditions

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

1.6

1.5

rnA

VIN = Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

Iccl

Maximum Additional
Icc/Input ('ACT377)

160

80

•

AC Characteristics

Symbol

Parameter

Vcc·
(V)

Min

Typ

Max

Max

75
95

Units

Fig.
No.

MHz

3·3

Max

fmax

Maximum Clock
Frequency

3.3
5.0

90
140

125
175

75
125

tPLH

Propagation Delay
CP to Qn

3.3
5.0

1.0
1.0

8.0
6.0

13.0
9.0

1.0
1.0

14.0
10.0

1.0
1.0

14.0
10.0

ns

3·6

tPHL

Propagation Delay
CP to Qn

3.3
5.0

1.0
1.0

8.5
6.5

13.0
10.0

1.0
1.0

15.0
11.0

1.0
1.0

14.5
11.0

ns

3·6

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·177

AC377 • ACT377
AC Operating Requirements

Symbol

Parameter

Vee·
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Setup Time,
HIGH or LOW
On to CP

3.3
5.0

3.5
2.5

5.5
4.0

7.5
6.0

6.0
4.5

ns

3·9

th

Hold Time, HIGH or LOW
On to CP

3.3
5.0

-2.0
-1.0

0
1.0

0
1.0

0
1.0

ns

3·9

ts

Setup Time,
HIGH or LOW
CE to CP

3.3
5.0

4.0
2.5

6.0
4.0

9.5
6.0

7.5
4.5

ns

3·9

th

CE to CP

Hold Time, HIGH or LOW

3.3
5.0

-3.5
-2.0

0
1.0

0
1.0

0
1.0

ns

3·9

tw

Clock Pulse Width
HIGH or LOW

3.3
5.0

3.5
2.5

5.5
4.0

6.5
5.0

6.0
4.5

ns

3·6

Units

Fig.
No.

MHz

3·3

'Voltage Range 3.3 is 3.0 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Characteristics

Symbol

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

5.0

140

175

Propagation Delay
CP to On

5.0

1.0

6.5

9.0

1.0

11.0

1.0

10.0

ns

3·6

Propagation Delay
CP to On

5.0

1.0

7.0

10.0

1.0

12.0

1.0

11.0

ns

3·6

fmax

Maximum Clock
Frequency

tPLH
tPHL

Max

Max

85

Max

125

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·178

AC377 • ACT377
AC Operating Requirements

Symbol

Parameter

Vcc·
(V)

74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Setup Time,
HIGH or LOW
On to CP

5.0

2.5

4.5

7.0

5.5

ns

3·9

th

Hold Time, HIGH or LOW
On to CP

5.0

-1.0

1.0

1.0

1.0

ns

3-9

ts

Setup Time,
HIGH or LOW
CE to CP

5.0

2.5

4.5

7.0

5.5

ns

3-9

5.0

-1.0

1.0

1.0

1.0

ns

3-9

5.0

2.0

4.0

5.5

4.5

ns

3-6

th
tw

Hold Time, HIGH or LOW

CE to CP
Clock Pulse Width
HIGH or LOW

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

90.0

pF

Vcc=5.5 V

5-179

•

AC378 • ACT378
54AC/74AC378 • 54ACT/74ACT378
Parallel 0 Register With Enable
Connection Diagrams

Description
The 'ACI'ACT378 is a 6-bit register with a buffered
common Enable. This device is similar to the
'ACI'ACT174, but with common Enable rather than
common Master Reset.
•
•
•
•
•

6·Bit High·Speed Parallel Register
Positive Edge·Triggered D·Type Inputs
Fully Buffered Common Clock and Enable Inputs
Outputs Source/Sink 24 mA
'ACT378 has TTL-Compatible Inputs

Ordering Code: See Section 6
Pin Assignment
for DIP, Flatpak and SOIC

Logic Symbol
0,

Q1

NC

01

Do

lIlWlIlrn@]
cp

a,

rn

rn ao

GNO

!lID

mE

Ne

ITIJ

[j]

ep

jg]

~ Vee
~as

a3~

§]~~ij!]~
03

Pin Names

E
Do - D5
CP
00 - 05

Enable Input
Data Inputs
Clock Pulse Input
Outputs

04

Ne

04

05

Pin Assignment
for LCC

5-180

Ne

AC378 • ACT378
Functional Description

Truth Table

The 'AC/'ACT378 consists of six edge-triggered Dtype flip-flops with individual D inputs and
Q outputs. The Clock (CP) and Enable (E) inputs
are common to all flip-flops.

Inputs

When the E input is LOW, new data is entered into
the register on the LOW-to-HIGH transition of the
CP input. When the E input is HIGH, the register
will retain the present data independent of the
CP input.

Outputs

E

CP

On

Qn

H
L
L

.f
.f
.f

X
H
L

No Change
H
L

H = HIGH Voltage Level
L = LOW Voltage level
X = Immaterial
S= LOW-to-HIGH Transition

Logic Diagram
0,
CP

-"

CP

CP

0

0

r---E

-E

a

CP

0

r-E

CP

a

a

CP

0

r--E

0

r-E

CP

0

r-E

a

a

a

a,
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

74AC/ACT

160

80

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Iccllnput ('ACT378)

1.6

5-181

Units

Conditions

!LA

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

!LA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

•

AC378 • ACT378
AC Characteristics
74AC

54AC

74AC

TA= -40°C
to + 85°C
CL=50 pF

fmax

Units

Fig.
No.

Units

Fig.
No.

ns

3·9

Frequency

tPLH

Propagation Delay
CP to On

tPHL

Propagation Delay
CP to On

7.5
5.5

3.3
5.0

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements

Parameter

Vce·
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Guaranteed Minimum

ts

th

Hold Time, HIGH or LOW'
On to CP

ts

Setup Time,
HIGH or LOW
E to CP

3.3
5.0

E to

Hold Time, HIGH or LOW
CP

3.3
5.0

0
0

ns

3·9

CP Pulse Width,
HIGH or LOW

3.3
5.0

8.5
6.0

ns

3·6

th
tw

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·182

AC378 • ACT378
AC Characteristics
74ACT

54ACT

74ACT

TA= - 55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Units

Fig.

No.

Max
fmax

Frequency

tPLH

Propagation Delay
CP to an

5.0

tPHL

Propagation Delay
CP to an

5.0

5.5

·Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements

Symbol

Parameter

Vcc·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= - 40°C
to + 85°C
CL=50 pF

Typ

Units

Fig.

No.

Guaranteed Minimum

ts

ns

3·9

th

ns

3·9

ns

3·6

ts

Setup Time,
HIGH or LOW
E to CP

5.0

-1.0

th

Hold Time,
HIGH or LOW
E to CP

5.0

0

tw

CP Pulse Width,
HIGH or LOW

5.0

6.0

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·183

•

AC378 • ACT378
Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

pF

Vcc=5.5 V

pF

Vcc=5.5 V

Typ

CIN

Input Capacitance

CPD

Power Dissipation
Capacitance

4.5

5-184

AC379 • ACT379
54AC/74AC379 • 54ACT/74ACT379
Quad Parallel Register With Enable
Description

Connection Diagrams

The 'ACI'ACT379 is a 4-bit register with a buffered
common Enable. This device is similar to the
'ACI'ACT175 but features the common Enable
rather than common Master Reset.

•
•
•
•
•
•

Edge-Triggered D-Type Inputs
Buffered Positive Edge-Triggered Clock
Buffered Common Enable Input
True and Complement Outputs
Outputs Source/Sink 24 rnA
'ACT379 has TTL-Compatible Inputs

Ordering Code: See Section 6
Pin Assignment
for DIP, Flatpak and SOIC

Logic Symbol

0,

0,

O2

01

NC

Do

00

w[JJww[1J

03

cp

a, [[]

rnao
[2Je

GRD [@]

NC [i]

Do - D3
CP
00 - 03
00 - 03

~vcc

a2~

[i]]
1Bl~6:§][j][i]
cb 02 NC 03 cb

Pin Names

E

[j]NC

CP[gJ

Enable Input
Data Inputs
Clock Pulse Input
Flip-Flop Outputs
Complement Outputs

Pin Assignment
for LCC and PCC

5-185

•

AC379 • ACT379
Functional Description
independent of the CP input. When the E is LOW,
new data is entered into the register on the LOWto-HIGH transition of the CP input.

The 'ACI'ACT379 consists of four edge-triggered
D-type flip-flops with individual D inputs and Q and
Q outputs. The Clock (CP) and Enable (E) inputs
are common to all flip-flops. When the E input is
HIGH, the register will retain the present data

Truth Table
Inputs

Outputs

E

CP

Dn

Qn Qn

H
L
L

j"

X
H
L

NC
H
L

j"
j"

H =HIGH Voltage Level
L = LOW Voltage Level
X =Immaterial
I= LOW-to-HIGH Transition
NC =No Change

NC
L
H

Logic Diagram
0

CP

6
CP

6
0

r-- E

0

1

0

-

!

6

CP

CP

0

-

E
0

0

E

0

;--

0

(

0

CP

0

0

0

E

(

E

0

0,

1

PLease note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Iccllnput ('ACT379)

1.6

160

5-186

74AC/ACT

Units

Conditions

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=Worst Case

8.0

p,A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

80

AC379 • ACT379
AC Characteristics
74AC

1r

J

~

Sym~of···.

54AC

74AC

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF
Min

Units

Fig.
No.

MHz

3·3

Max

fmax

Propagation Delay
CP to Qn, On
Propagation Delay
CP to Qn, On

3.3
5.0

8.5
6.0

3-6

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

r-__

_A_C__O_p_eTra_t_in_g__R_e_q_u_ir_em
__e_n_ts____
Symbq1

i-

Parameter

- r__________

Vee·
(V)

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Units

Fig.
No.

ns

3-9

ns

3-9

ns

3-6

Guaranteed Minimum

Typ
ts

~----------r---------~----~----.

74AC

Set}JI1~~~J j
HI~.biI
or 'J-Qw'r
,,,1
,0

Dn to cpJ"i

I

""'"~

'or"l0vli ·'3.~

th

Hold Time, HIGH
Dn to CP

ts

Setup Time,
HIGH or LOW
Eto CP

3.3
5.0

th

Hold Time, HIGH or LOW
E to CP

3.3
5.0

3.0
2.0

tw

CP Pulse Width,
HIGH or LOW

3.3
5.0

5.5
4.0

"~ltb

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-187

AC379 • ACT379
AC Characteristics
74ACT

54ACT

74ACT

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Units

Fig.

No.

Max
fmax

Propagation Delay
CP to Qn, an

5.0

Propagation Delay
CP to Qn, an

5.0

6.0

'Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Units

Fig.

No.

Guaranteed Minimum

ts

ns

3-9

ns

3-6

th

ts

th
tw

Setup Time,
HIGH or LOW
E: to CP
Hold Time, HIGH or LOW

E: to CP
CP Pulse Width,
HIGH or LOW

5.0

3.0

5.0

2.0

5.0

4.0

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·188

AC379 • ACT379
Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

pF

Vcc=5.5 V

pF

Vcc=5.5 V

Typ

CIN

Input Capacitance

CPD

Power Dissipation
Capacitance

4.5

•

5-189

AC398 • ACT398 • AC399 • ACT399
54AC/74AC398 • 54ACT/74ACT398
54AC/74AC399 • 54ACT/74ACT399
Quad 2-Port Register
Connection Diagrams

Description
The 'ACt'ACT398 and 'ACt'ACT399 are the logical
equivalents of a quad 2-input multiplexer feeding
into four edge-triggered flip-flops. A common
Select input determines which of the two 4-bit
words is accepted. The selected data enters the
flip-flop on the rising edge of the clock. The
'ACt'ACT399 is the 16-pin version of the
'ACt'ACT398, with only the Q outputs of the flipflops available.

AV) is 1.1 ,.s for the first byte sent after a LOW to HIGH transition of ATN and 500 ns for subsequent
bites.
2. For dual address Talker/Listener modes the Talk and Listen addresses can be different.
5-202

ACT488

Table 2
~Os

0107

0106

X
X
X
X
X

H
H
L
L
L

L
L
H
H
L

0105
A5

0104
A4

0103
A3

0102
A2

0101
Al

L

L

L

L

L

A5

A4

A3

A2

Al

L

L

L

L

L

85

84

83

82

81

Primary Listen Address
Unlisten
Primary Talk Address
Untalk
Secondary Address

Addressing Modes
Where extended addressing or different Talk and
Listen addresses are required, the address codes
must be externally multiplexed, using ASEL (Figure
3). In the extended address modes, ASEL is LOW
for the primary address and HIGH for the
secondary address (Figure 11). In the dual address
modes, ASEL is HIGH for the Listen address and
LOW for the Talk address.

address if, and only if, it has received its primary
address. If a device is addressed to Talk and
receives its Listen address it will un-address as a
Talker and go to Listener addressed state, and
vice versa. A Talker Addressed device will unaddress if it receives a non-matching talk address.
The 'ACT488 indicates its address status on the
TAD, LAD and D/S/E outputs (Table 3).

In single address mode the 'ACT488 will go into the
addressed state on receipt of the primary address.
In extended address mode it will go to the
addressed state on receipt of its secondary

Table 3: Status Codes
TAD

LAD

D/S/E

H

H
L
H
H
L

L
L
L
H
H

H

L
L
H

5·203

State
Off Line
Addressed to Listen (LADS)
Addressed to Talk (TAOS)
Serial Poll Mode (SPM)
Receiving END Message
(LACS)

5

ACT488
Figure 3: Address Multiplexer
---1-........-

Vee

MR

I
PRIMARY
ADDRESS

1--1

CP

I

XTAL

E

A1

A2
~r-~~~

____

~'ACT157~

__________________________~

'ACT488

A3

A4

S

As

~oo

- - - - - - - - - -l

ASEL
Mo M1

I
I

I
I

I
I
I

I
L

M2 M3

- I
I
I
--.l

L ___________ ..J

-=-

MODE SELECT

-=- L __ ..J
SECONDARY
ADDRESS

Status Response
In Serial Poll Active State (SPAS) the instrument is
requested to return a status byte, via the usual
handshake, to the Controller. Seven bits are defined
by the instrument. Bit 7 denotes the Request
Service Status (RQS) and is provided by the
'ACT488 on the RQS output. If the instrument
provides no status, other than RQS, then the RQS
output can drive the bus directly (Figure 4). If the

instrument provides status information this can be
multiplexed to the bus using D/S/E (Figure 5). After
the bus handshake, the instrument can send a
second status byte by making STRDY LOW then
HIGH again, which starts the handshake. The
sequence can be repeated to send additional bytes,
as long as ATN remains HIGH (Figure 16).

5-204

ACT488
Figure 4: Status Bit Driven Direct by RQS
DATA
HANDSHAKE

TXRDV
TXST

+r

STATUS
HANDSHAKE

u- L

DATA
REGISTER

t-8

STROY

'ACT488

~

STST
......;:E
DO.

DID, 0106 0105 DID. 0103 DID,

DATA
DRIVER

0101 Ras D/S/E ORB

I

y

-

~

•

Figure 5: Status Byte Multiplexing
Status
&
Byte

Data

'ACT488

Byte
Transfer
&

Data

Interface

110

To
Management
Bus

Data Bus

GPIB
Management Bus

5-205

ACT488
Clock Input

relevant DIO line will be enabled or disabled within
200 ns of an lOY transition.

The CP and XTAL inputs allow the 'ACT488 either
to accept external clock pulses or to generate its
own clock (Figure 6).

Since the internal logic of the 'ACT488 is
synchronous with the CP input, while in general all
inputs are asychronous, the precise timing of all
responses to external Signals is subject to a
maximum uncertainty equal to one clock period.
This is illustrated in the following timing diagrams,
where some delays are defined as tcp + tx (i.e.,
clock period + propagation delay).

a. An external clock can drive CP. The XTAL pin
may used as an inverted buffered version of
the external clock, but has limited drive
capability.
b. The CP and XTAL pins will form a stable
crystal oscillator by connecting a 10 MHz
crystal and an RC network to provide positive
feedback. XTAL may be used to clock external
circuits provided it is buffered.

Listen Address Sequence (Figure 7)
a. Controller takes ATN line LOW followed by
b. putting the Listen address on the GPIB.
c. Within (tcp + tPHL) the 'ACT488 takes NRFD
and NDAC LOW,

Figure 6: Clock Timing Component
Connections

d. and a tcp later takes NRFD HIGH, indicating
that the 'ACT488 is ready for data.

8.

e. After a delay TCDAV(L) (determined by the
Controller logic), the Controller takes DAV
LOW.

CP-f>-r-~

XTAL~

f. Within (tcp + tPHL) the 'ACT488 takes NRFD
LOW and
g. three clock periods later NDAC goes HIGH,
indicating that the 'ACT488 has accepted the
data,

b.

h. followed by LAD indicating listen addressed
status.
30 pF

i. After a Controller dependent delay, TCDAV(H),
the DAV line goes HIGH and
j. within (tcp + tPHL) the 'ACT488 takes Nl5AC
LOW.

Timing Sequences
k. A tcp later the 'ACT488 allows 1iJ'RFl) to go
HIGH. NRFD stays HIGH until the Controller
takes ATN HIGH, unless a further command
is sent over the GPIB when a similar
handshake sequence takes place.

A 10 MHz clock frequency is recommended to give
the correct Source Handshake delays. The 'ACT488
can be clocked at a slower rate if the GPIB is not
running at its maximum data rate of 1M byte. The
lowest clock frequency allowable is dependent on
the GPIB speed.

I.

ATN goes HIGH followed by

m. NRFD going LOW within (tcp + tPHL). This
occurs if the instrument is not ready to
receive data (RXRDY LOW). If RXRDY is HIGH,
NRFD will stay HIGH allowing a data transfer
to take place.

Regardless of clock frequency, the 'ACT488 will
respond to ATN within 200 ns by disabling NRFD,
"fii""IJAC and DAV while forcing "[)"R"B" HIGH to disable
the data drivers. In Parallel Poll sequences the

5·206

ACT488
Figure 7: Timing Diagram for Listen Address Sequence

)( tcp

+ tPHl .... j

Note: ATN, IDa bus and DAV driven by controller;

NRF!5, NDAC driven by'ACT488.

Data Transfer from Bus to Listener (Figure 8)'
Assuming the instrument logic responds to RXST
within one clock period (Figure 8a).

g. After a delay TTDAV(H) determined by the
Talker, the DAV line goes HIGH.
h. Within (tcp + tPHL) NDAC goes LOW

a. The instrument signals it is ready to receive a
byte by taking RXRDY HIGH (keeping RXRDY
LOW constitutes an "NRFD hold").

i. followed by NRFD going HIGH one clock
later.

b. Provided the 'ACT488 is in the Listen
Addressed State (LADS), NRFD is taken HIGH
within (tcp + tPHL).

This assumes that the instrument logic is slow and
requires more than one clock period to process a
data byte (Figure 8b).

c. When the current Talker sees the NRFD line
HIGH it takes DAV LOW after a setting delay
TTDAV(L).

The timing sequence is identical to Figure 8a until
RXST goes HIGH.
a. After RXST goes HIGH the instrument delays
tPRX (> 1 clock cycle) before taking RXRDY
LOW.

d. The 'ACT488 takes RXST HIGH within (tcp
+ tPLH) to inform the instrument that the GPIB
data is valid and takes m:rFD LOW.

b. RXST will remain HIGH and NDAC will remain
LOW during this period, causing the bus data
to be maintained valid.

e. Assuming the instrument responds by pulsing
RXRDY LOW within one clock period (tPRX <
tcp) then RXST will remain HIGH only for one
clock.

c. RXST goes LOW, and NDAC goes HIGH
within (tcp + tPHLj of RXRDY.

f. At the same time as RXST returns LOW,
NDAC is taken HIGH to inform the Talker that
data has been accepted.
'In applications where the bus data can be latched by the
RXST rising edge and handshaking is not necessary,
RXRDY can be driven by RXST via an inverter.

5·207

•

ACT488
Figure 8: Timing Diagram, Data Transfer
from Bus to Listener

d. After a delay TTDAV(H) the Talker takes DAV
HIGH.

a.
e. Within (tcp

~

Bus Data Valid

tPw-.j

+

tPHL) NDAC goes LOW.

f. Assuming the instrument is not ready (Le., is
holding RXRDY LOW) the 'ACT488 holds
NRFD LOW preventing another data transfer
from starting.

1_

g. Within (tcp + tPLH) of RXRDY going HIGH,
NRFD goes HIGH and the next data transfer
cycle can start.

RXST

Data Transfer from Talker to GPIB (Figure 9)'
a. ATN goes HIGH after completion of a Talk
address sequence; TAD (not shown) is already
LOW.
b. Within (tcp + tPHL) ORB goes LOW to enable
the bus drivers.

L

c. At a time determined by the instrument logic,
TXRDY goes HIGH.
d. If NRFD is already HIGH, the 'ACT488 drives
DAV LOW after delay T1 (11 x tcp + tPHL in
high or 20 x tcp + tPHL in low speed). If NRFD
is LOW, DAV will stay HIGH until NRFD goes
HIGH (assuming T1 has expired). The DAV
LOW period corresponds to the Source
Transfer State (STRS).

b.
Bus Data Valid

~

e. The Listener(s) responds by eventually taking
NDAC HIGH.

RXRDY

f. Within (tcp + tPLH) 'ACT488 takes DAV HIGH
and TXST HIGH to inform the instrument that
the data has been accepted and a new byte
can be presented.

RXST

g. The instrument takes TXRDY LOW and holds
it there until it has provided a new byte, h or
h'. The minimum time TXRDY must be LOW is
tPWL.

tcp + tPlH-'

h. If TXRDY pulses LOW within tcp of TXST,
TXST(H) will be a minimum of tcp wide.
Otherwise TXST goes LOW within (tcp + tPHL)
of TXRDY, f. After the first byte is sent, T1
drops from 11 x tcp to 5 x tcp in high-speed
mode.

'In order to get the source handshake delays specified in
IEEE Std 488-1978, tcp must be 100 ns (fcLocK = 10 MHz).

5-208

ACT488
i. If TXRDY is HIGH before NRFD, DAV goes
low within T2 of NRFD going HIGH (5 x tcp in
high speed or 20 x tcp in low speed).

If the Talk sequence is interrupted by ATN while
the instrument is generating a new byte (between f
and h), DRB will go HIGH within 200 ns and the
DAV line will be relinquished. DRB will return LOW
and the sequence will continue within (tcp + tPHL)
of ATN going HIGH. If the 'ACT488 is in high
speed mode the first data byte sent will have a
delay T1 = 11 x tcP.

If TXRDY does not go HIGH until h' (after NRFD
goes HIGH) DAV goes LOW T3 later, i' (T3 = 6 x
tcp in HIGH and 21 x tcp in low speed).

Figure 9: Timing Diagram Data Transfer from Talker to Bus

____)I(

~~oa_"_S"_b"_________

OlilaStable

\'-____1

-'1

_""_,°____

o
TXRDY

•

TXST

'''-I~

Notes

NR'Fl>, iiiDAC are driven by the current listener(s); f5AV is driven by 'ACT488.
= 11 x tcp + tPHL in high speed, 20 x tcp + tPHL in low speed
T2 = 5 x tcp + tPHL in high speed, 20 x tcp + tPHL in low speed
T3 = 6 x tcp + tPHL in high speed, 21 x tcp + tPHL in low speed
T1

Figure 10: Talk Address Sequence
010 BUS

x'.f.tIJt!:IX
...........

'tgttlj.xttJ..~_____
va_lid_Ta_lk_Ad_dre_ss_ _ _---I..j£Xm~X.X'
. . .t.J. .X
.'.tA.....'t....A@
.........

ATN

........ tcpl~

NRFD

DAV

-

-

--.

_ I c p + IPHL

Icp
+ IpHL

I:

-\

-Ilcp~ I
IPHL -

.~

Icp+lpLH - - .

j
Icp +
- - . IPHL

. - - 4 x ICP_I
+ IPLH

f

NDAC

--.

_IPLH

\

~4 x Icp + IPLH-+:I

-\:

TAD

ORB
_ 4 x Icp + IPLH_I

D/S/E (if and only if Ihe 'ACT488 is in SPMS, i.e., an SPE has been reCeiVed)!

5·209

--.

..-Icp + IpHL

ACT488
Figure 11: Timing Diagram for Secondary Address Sequence
VALID SECONDARY ADDRESS

010 BUS

ATN

NRFD

DAV

NDAC

ASEL
A1-A5
(mu. output)

econ ary
Address

Icp +
tPLH
(if address received was a talk address)

Figure 12: Timing Diagram for 'ACT488 Receiving Bus Commands

DIOBUS

~~____________________________B_Us__c_o_m_m_a_n_d______________--J~

r_---------k+----~---..J2 x Icp
+ IPLH

-+

tcp
tPHL

IPLH (if nol LADS)

Icp

Internal Stale Change (e.g., PUCS-PACS, LOCS-LWLS)

Note: Internal state changes do not necessarily change any 'ACT488 outputs.

5-210

+

IPHL--

r--

ACT488
Figure 13: Timing Diagram for Device Clear and Device Trigger Commands
010 BUS

ATN

-,

GET, DCl or SOC Command
_ _ Icp

+ IPHL

- --

Icp

DAV

--,

,

2 x Icp

,

j

~

___ Icp

+ IPHL

.. ..

~

+ IPHL

Figure 14: Timing Diagram for Remote/Local Logic
(Starting in LOCAL State)

xoox

-

Valid Listen Address or LLO Command

@

Note: If LLO has been sent, RTL will not cause R/L to change.

5-211

,

_Icp

~

I

\

DiO BUS

1\

IPLH (if nol lADS)_

f-

J

. - 4 x Icp_
+ IPLH

2 x Icp

, ---

+ IPLH

I

~

NDAC

I--

J

Icp

L.J

+ IPHL (lADS only)_

+ IPHL

/

,,---

2 x Icp

•

ACT488
Figure 15: Timing Diagram for Remote/Local Logic
(Starting in REMOTE State)

m

010 BUS

~

GTL Command

____________

~(L~O~W~)

_____________

ATN

RlL

.-Icp

+

IPHL

L;~,~-,_
R/L

f

____________________--J

Serial Poll Sequence (Figure 16)
a. The Controller has sent the Unlisten (UNL) and
Serial Poll Enable (SPE) commands, generally
in response to a LOW signal on SRO, and
places a Talk address on the GPIB. The
'ACT488 is sending the Service Request (SRO)
message, which was caused by the instrument
logic making RSV LOW.

g. NDAC is allowed to float passive HIGH,
indicating that the command data byte has
been received.
h. The Controller takes DAV HIGH.
i. NDAC is pulled LOW, showing that the
'ACT488 is ready for a new handshake cycle.

b. The 'ACT488 allows NRFD to float passive
HIGH to initiate normal handshake routine.

j. The Controller allows the bus to float.

c. The Controller forces DAV LOW. Since ATN is
also LOW, the 'ACT488 receives the GPIB
information as the message My Talk Address
(MTA).

k. The Controller releases ATN. Because the
'ACT488 is in the Serial Poll Mode, it now
enters the Serial Poll Active State (SPAS),
which prevails until the Controller makes ATN
LOW again.

d. NRFJ) is active, acknowledging that the device
is receiving a data byte.

I. DRB goes active LOW, allowing the instrument
to place its status byte on the bus. DRB goes
LOW at time (tcp + tPHL) after ATN goes
HIGH.

e. The 'ACT488 enters the Talker Addressed
State at time (4 x tcp + tPLH) after DAV was
forced LOW.

m. When the 'ACT488 enters SPAS, SRO goes
HIGH at time tPLH after ATN goes HIGH.

f. D/S/E goes HIGH at time (4 x tcp + tPLH) after
DAV was forced LOW. This indicates that the
'ACT488 is in the Serial Poll Mode.

5·212

ACT488
n. The instrument indicates that a status byte is
ready by taking STRDY HIGH. This may occur
earlier than shown, without affecting any of
the foregoing.

HIGH to indicate valid data and to start the
handshake.
y. At the completion of the Serial Poll of this
instrument, the Controller assumes control of
the bus by forcing ATN LOW.

o. DRB enables the 3-state output RQS when in
SPAS. RQS goes LOW at time (tcp + tPZL)
after ATN is released.

z. DRB goes HIGH at time tPLH after ATN goes
LOW. This places the bus drivers of this
instrument in the high-impedance (3-state
output) or oft (open-drain outputs) state.

p. The Controller has taken NRFD HIGH,
acknowledging that it is ready for the status
byte.

aa. Since DRB is no longer valid, the RQS output
reverts to its high-impedance state.

q. The 'ACT488 takes DAV LOW after the time
interval T1, which starts either at the rising
edge of STRDY or the falling edge of ORB,
whichever occurs later. The DAV LOW period
corresponds to the Source Transfer State
(STRS).

bb. NRFD goes HIGH, indicating that devices are
ready to receive a command from the bus.
cc. The Controller forces DAV LOW to show that
it has placed a control byte on the bus.

r. The Controller takes NRFD LOW.
dd. NRFD goes LOW to acknowledge DAV.
s. The instrument may release RSV at any time
after the 'ACT488 enters SPAS.

ee. NDAC goes HIGH when devices all
acknowledge acceptance of the command
byte.

t. The Controller takes DNAC HIGH,
acknowledging that it has received the status
byte.

ft. The 'ACT488 has received the Other Talk
Address (OTA) command and reverts to its
unaddressed state. TAD goes HIGH at time
(4 x tcp + tPLH) after DAV went LOW.

u. The 'ACT488 releases DAV at time (tcp + tPLH)
after NDAC ~oes HIGH.
v. STST goes HIGH at time (tcp + tPLH) after
NDAC goes HIGH. This tells the instrument
that the status byte has been accepted. The
instrument takes STRDY LOW to indicate that
the data is no longer valid and to allow STST
to go LOW again one tcp after STRDY goes
LOW.

gg. DAV is set HIGH by the Controller.
hh. Because the 'ACT488 has been unaddressed it
is no longer in the Serial Poll Active State
(SPAS). The DlS/E output goes LOW at time
(4 x tcp + tPHL) after DAV went HIGH. The
'ACT488 is still in the Serial Poll Mode State
(SPMS), however, and will return to SPAS
(D/S/E HIGH, STST and STRDY valid) if
subsequently addressed to talk. The 'ACT488
enters the Serial Poll Idle State (SPIS) when
the Controller either issues the Serial Poll
Disable (SPD) command or makes iFC LOW.

w. The controller takes NDAC LOW once more
after DAV goes HIGH.
x. The data on the bus is no longer valid. If the
ATN line remains HIGH, the instrument can
provide another status byte by making STRDY

5-213

•

ACT488
Figure 16: Timing Diagram for Serial Poll Sequence

OIOi

SPE Received

XC~

jlX

MTA Received

Status Byte Sent (0107

I

\

~
~C0\\

~

~
8\

1\

D/S/E

top + r"Ht..

\
j

~

STST

STRDY

I.... F-

I \
I~/
~ {ttPlH

,,' "" '/1~

r-Jr""'-+\i
tcH)rSV

5-214

+

x

1f)1 /

•

tpLH

4 x

\

/

~~tcp +

\

1

@\

\

\

•

,@, ~4 top tPlH

\
~z~

I

-

~4, i \
ee)1 Li
\

l-

+ tPHL-+t

@/

@l

tPlH-

II

q)\
tcp

\/

G:

ef( -(w

~\
tPHL
-1--I

~J

'@n@

@

C£I

4 x tcp + tPLH

OTA Received

T\

01

[

4 x tcp +

C~X

= RaS)

~{

tPHl

l..-tPLZ

tep

+

tPHL

ACT488
Parallel Poll Sequence (Figure 17)
a. The Controller sends the instrument's listen
address,

h. The 'ACT488 enables data bit 0101 after a
delay tPHL from the time EDT goes active LOW.
DTOj remains valid while lOY is active. Note
that this is an asynchronous message sent
and is not governed by the handshake
protocol.

b. then the Controller issues the Parallel Poll
Configure command: this enables the 'ACT488
to receive a subsequent PPE command.

i. 1ST may be altered not less than time th 1ST
after lOY is active. Because 1ST is latched by
lOY it will not affect the status byte sent
during the lOY routine.

c. The Contoller issues the Parallel Poll Enable
command. Bits 01 - 03 of the command byte
determine which data output (mOl) will be
valid when the lOY command is sent. Bit 04 of
the command is compared with 1ST
(Instrument Status) during the lOY command.

j. lOY is false and the 'ACT488 stops sending a

status byte. Outputs 0101 - 0107, DOs again
float passive HIGH.

d. The Controller issues the Unlisten command.
The 'ACT488 will now not respond to further
PPE commands, allowing the Controller to
configure other instruments.

k. The status bit DTOj floats passive HIGH at a
time not greater than tPLH after lOY goes
FALSE.

e. The Instrument Status bit (1ST) is set by the
instrument before an IOENTIFY command is
received. 1ST must be in a stable state when
lOY is received so the setup and hold times
must be observed (ts 1ST and th 1ST).

I. The Controller can now place information on
the data bus.

m. Once the 'ACT488 has been configured via
•
steps a-c, the Controller can examine 1ST at
any time by issuing the lOY command. To
change the 01 - 04 assignment of a particular
'ACT488, the Controller must address it to
listen, issue the PPC command, then the
Parallel Poll Disable (PPO) command (which
clears the 01 - 04 latches), then the PPE
command with the revised 01 - 04 assignment.
The 01 - 04 assignment will also be cleared by
the universal Parallel Poll Unconfigure (PPU)
command or by MR, but not by TFC. PPU, MR
or the MLA/PPC/PPO sequence puts the
'ACT488 in the Parallel Poll Idle State (PPIS)
and it will not respond to lOY until it is
subsequently reconfigured.

f. During the lOY command the Controller
releases the data lines 0101 - 0107, ~Os. The
assigned data line 0101 will be taken active
LOW by the 'ACT488 if 1ST compares with bit
04 of the PPE command.
g. The lOY Message is received (lOY = EDT •
ATN). At this time the Instrument Status bit
1ST is latched in the 'ACT488, and the output
data 0101 is true if 1ST compares with bit 04 of
the PPE command. OIOj is LOW if 04 was
LOW and 1ST was HIGH, or if 04 was HIGH
and 1ST was LOW.

5·215

ACT488
Figure 17: Timing Diagram for Parallel Poll Sequence
H

H

EOi
H
0101

01°1

~t.tuS)
Bit

H

L
H

1ST

H

LAii

Figure 18: IFe Timing Diagram

- - - --- -

~tCP+tPLH

IplH

tPHl

DIS/E

tcp + tPlH

t<:p

TXST/STST

+

tPHl

I+-

1"--

tPLH

I

tPlH

RXST

-

tPHl

I--

Absolute Maximum Ratings
(above which the useful life may be impaired)
-65°C to + 150°C
Storage Temperature
Temperature (Ambient) Under Bias -55°C to + 125°C
Vee Pin Potential to Ground Pin
-0.5 V to + 7.0 V
*Input Voltage (DC)
Bus Pins 0.5 to 12 V; Others 0 to Vee + 0.5 V
*Input Current (DC)
±20 rnA
Voltage Applied to Outputs (Output
HIGH)
-0.5 V to + 5.5 V
Output Current (DC) (Output LOW) Bus Pins + 64 rnA; Others + 24 rnA
*Either input voltage limit or input current limit is sufficient to protect the inputs.
5-216

ACT488
DC Characteristics (unless otherwise specified)
Symbol

Parameter

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

54ACT

74ACT

ICCT

VIH

VIL

Input LOW Voltage
All Inputs
(except CiS)

VT+-VT-

Hysteresis Voltage

VCD

Input Clamp Diode Voltage
Output HIGH Voltage
RQS, DAV

0101 - 0107, DOs,
VOH

SRQ,NRFD,'N'iJA'C
R/L, DISIE, RXST, TXST,
STST, CCR, TRIG, ORB,
ASEL,XTAL, LAD, TAD

Units

Conditions

/LA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

/LA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

V

Recognized as a
HIGH Signal
Over
Recommended
Vcc Range
Recognized as a
LOW Signal
Over
Recommended

Typ=O.4

Inputs

2.4

V

2.6

V

Open Collector
Bus Pins
IOH = 0 rnA

2.5

V

IOH = -0.4 rnA

0.5

V

IOL = 48 rnA

0.4
0.5

V
V

IOL = 4.0 rnA
IOL = 8.0 rnA

Output LOW Voltage

Di01 - Di07, DOs, SRQ,
VOL

RQS,NRFD,NDAC, DAV
All Other Outputs

IIH

Input HIGH Current

/LA

VIN=2.7 V

ilL

Input LOW Current

rnA

VIN =0.4 V

IpoFs

Leakage into GPIB Pins
in Powered-off State

/LA

VIN = 2.5 V

5-217

•

ACT488
DC Characteristics (cont'd)
Symbol

Parameter

54ACT

Units

74ACT

Conditions

IOZH

3-State Output OFF
Current HIGH

/LA

VOUT = 2.4 V

IOZl

3-State Output OFF
Current LOW

/LA

VOUT = 0.4 V

AC Characteristics

Symbol

Parameter

Vee·

74ACT

54ACT

74ACT

TA=+25°C
Cl=50 pF

TA= -55°C
to + 125°C
Cl=50 pF

TA= -40°C
to +85°C
Cl=50 pF

Min

Min

Units

Fig_
No_

5.0

MHz

3-3

5.0

ns

3-6

ns

3-6

ns

3-6

ns

3-6

ns

3-6

(V)

Min
fmax

Typ

Propagation Delay

CP to NDAC
Propagation Delay

CP to NDAC
Propagation Delay
ATN to NDAC
Propagation Delay

CP to DAV
Propagation Delay

CJ5 to DAV

tPZH

Max

Max

Max

5.0

3-6

5.0

3-6

5.0

3-6

Output Disable Time
ATN to DAV

5.0

ns

3-8

Output Disable Time
ATN to DAV

5.0

ns

3-7

5.0

ns

3-7

5.0

ns

3-8

Output Enable Time

CP to DAV
Output Disable Time

CP to DAV
·Voltage Range 5.0 is 5.0 V ± 0.5 V

Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-218

ACT488
AC Characteristics (cont'd)

Symbol

Vee·

Parameter

(V)

74ACT

54ACT

74ACT

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Units

Fig.
No.

Max

tPHZ

Output Disable Time
CP to DAV

5.0

ns

3-7

tPLH

Propagation Delay
IFC to LAD or TAD

5.0

ns

3-6

F:'ropagation Delay
;Tf!"OtQ
D/S/E
'''~''

5.0

ns

3-6

5.0

ns

3-6

ns

3-6

ns

3-6

ns

3·6

ns

3·6

tPHL
{i

tPLH
tPHL
tPLH
tPHL

/

'1"

IlIop1ghtj6·Il',Qelay

fcp::i0'~A9·dr·,rAD

t,

propa~Cj,fioJi:1{rtt' (.::".': }50
i/~'~}
CP to.IlAD ?r/ .' .
Propagatioll"bEt(a,•.. 00,/ / /
5.0
Mo . M3 to LAD or"

ol

Propagation Delay
Mo· M3 to LAD or TAD

0.,

';'"0:7

Propagation Delay
CP to RXST, TXST or
STST

5.0

tPHL

Propagation Delay
CP to RXST, TXST or
STST

5.0

tPLH

Propagation Delay
CP to DRB

5.0

tPHL

Propagation Delay
CP to DRB

tPLH
tPLH

tPLH

tPHL

ilttt;:;;7l
"(,/1//1:

1

r'o,

?\ iV/'/

to/ <~~o~~:

I!"'""o~

foj

....

i'll!{?l/ n/f')·

3-6

I)

l~'>o

3-6

5.0

ns

3·6

Propagation Delay
ATN to DRB

5.0

ns

3-6

Propagation Delay
CP to TRIG or CLR

5.0

ns

3-6

5.0

ns

3-6

Propagation Delay

CP to TRIG or CLR

tPLH

Propagation Delay
DAV to ASEL

5.0

ns

3-6

tPHL

Propagation Delay
DAV to ASEL

5.0

ns

3-6

tPHL

Propagation Delay
MR to RXST, TXST, STST
or D/S/E

5.0

ns

3-6

tPLH

Propagation Delay
MR to LAD, TAD or AIL

5.0

ns

3-6

'Voltage Range 5.0 is 5.0 V ± 0.5 V

5·219

•

ACT488
AC Characteristics (cont'd)

Vee·
(V)

Parameter

Symbol

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Units

Fig.
No.

5.0

ns

3-6

5.0

ns

3-6

5.0

ns

3-6

5.0

ns

3-6

ns

3-6

ns

3-6

ns

3-6

Min
Propagation Delay
MR to NRFD, NDAC,
~, 0101 - D107, OOa or
SRQ

tPLH

Propagation Delay
f~to XTAL

tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL

I
IJ

~gation Delay

~

~

~

CP

Propagati

CP to R/L

Propag~ion Delay"
RTL to R/L

/ [1.0

l/

Propagation Delay
REN to R/L
Propagation Delay

CP to ])/S/E
Propagation Delay

CP to ])/S/E

Propagation Delay
RSV to SRQ

5.0

tPZL
tPZH

Propagation Delay
Output Enable Time

CP to RQS
Output Enable Time

CJ5 to RQS

Max

)

'~ ii

ns

5.0

tPHL

Al"'f\l to SAO

V

5.0

5.0

Max

%

5.0

Propagation Delay
RSV to SRQ

Max

1"

~

tPLH

tPLH

Typ

s

3-6
3-6

iy

/

/

~

3-6

ns

3-6

5.0

ns

3-6

5.0

ns

3-6

5.0

ns

3-6

tpLZ

Output Disable Time
ATN to RQS

5.0

ns

3-8

tPHZ

Output Disable Time
ATN to RQS

5.0

ns

3-7

5.0

ns

3-6

5.0

ns

3-6

tPLH
tPHL

Propagation Delay

EOf to DI01 - 0107, DOa
Propagation Delay
EOI to 0101 - D107, DOa

'Voltage Range 5.0 is 5.0 V ± 0.5 V

5-220

ACT488
AC Characteristics (cont'd)

Vcc·
(V)

Parameter

Symbol

/ I~:~~~~\
tPLH,(l
tPHL

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Units

Fig.
No.

5.0

ns

3·6

t~.O

ns

3·6

ns

3-6

ns

3-6

ns

3·6

Min

'~Pf()~I;:iJ'~el ay

mll'§lE)~
prOeqgatl~~15

EOi t1> Dtfll'
,

~",<:?

d

~,

"~

I

De~t::) /'

Typ

Max

Max

Max

I

//!~

tPLH

Propagation
MR to DR

tPLH

Propagation Delay
TSCto TAD

" "'lli~
5:0

tPLH

Propagation Delay
TSCto LAD

5.0

tPLH

Propagation Delay
MR to RQS

5.0

tpLZ

Propagation Delay
Mode to NRFD

5.0

tpLZ

Propagation Delay
Mode to NDAC

5.0

~/ns

3·8

tPZH

Propagation Delay
Mode to DAV

5.0

ns

3·7

tPHZ

Propagation Delay
Mode to DAV

5.0

ns

3-7

Units

Fig.
No_

ns

3-9

I:

5.0

/",,~:>//

:;//7 /:1

V(/

d,

l//, /\\/~/ ,/':: Ii
\"./,;~>:,:::,~J

,/i(::::)~)

~~ lj~)

r)

ns

r":
t

3·6

;i

~;,~ ~> 3-8

'Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements
74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

ts

th

Hold Time,
HIGH or LOW
1ST to EOi

5.0

ts

Setup Time, LOW
RSVto ATN

5.0

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.
5-221

•

ACT488
AC Operating Requirements (eont'd)

Parameter

Symbol

Vee·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Units

Fig.
No.

Guaranteed Minimum

th

Hold Time, LOW
RSV to ATN

5.0

ns

3·9

ts

Setup Time, LOW
ATN to CP

5.0

ns

3·9

5.0

ns

3·9

5.0

ns

3·6

ns

3·6

ns

3-6

ns

3-6

ns

3-9

~:ime,LOW

th

lOP

(H:/j

tw
tw (L)
tw
tw
tw

~"1:!u.u

'~

PU:I~~d

RXR ,T
STRDY
"

Ir.0
II

II "

L ,5.0 II/A
RTL Pulse Width, LOW
1/ //1 J
MR Pulse Width,

~.~

ts (H)
ts (L)

Setup Time
Di01 - DI07 to CP

5.0

th (H)
th (L)

Hold Time
DIOo - Di07 to CP

5.0

ts

Setup Time, HIGH or
LOW, DAV to CP

5.0

th

Hold Time, HIGH or
LOW, DAV to CP

5.0

ts (H)
ts (L)

Setup Time
RXRDY, TXRDY,STRDY

5.0

ts (H)
ts (L)

Setup Time
NRFD to CP

ts (H)

lJ~

r,

~~
j

l

=<
"

~

~~ W
ns

3-9

r-~-9

V

3-9

ns

3-9

5.0

ns

3-9

Setup Time
NDAC to CP

5.0

ns

3·9

ts (H)
ts (L)

Setup Time
Address to CP

5.0

ns

3-9

tw (L)

TFC Pulse Width, LOW

5.0

ns

3-6

'Voltage Range 5.0 is 5.0 V ± 0.5 V

5-222

AC520 • ACT520 • AC521 • ACT521
54AC/74AC520 • 54ACT/74ACT520
54AC/74AC521 • 54ACT/74ACT521
8-Bit Identity Comparator
Description
The 'ACI'ACT520/521 are expandable 8·bit
comparators. They compare two words of up to
eight bits each and provide a LOW output when
the two words match bit for bit. The expansion
input IA=B also serves as an active LOW enable
input. The '521 features a pull·up resistor on each
input.
•
•
•
•
•
•

Compares Two 8·Blt Words In 6.5 ns Typ
Expandable to Any Word Length
20·Pln Package
Outputs Source/Sink 24 mA
'521 has Input Pull·Up Resistors
'ACT520 and 'ACT521 have TTL·Compatible Inputs

Ordering Code: See Section 6

Logic Symbol

A3

82

Az

B1

At

1!llll01!lw

Pin Names
Ao· A7
80·87

IA=B
OA=B

B31!l

rnBo

GNDI)]]

[IjAo

A,[i1j

[IJ IA=B

B4[j]]

~vcc

A5§

~OA=B

~~~[il][8]

Word A Inputs
Word 8 Inputs
Expansion or Enable Input
Identity Output

85

A6

B6

A7

B7

Pin Assignment
for LCC

5·223

AC520 • ACT520 • AC521 • ACT521
Truth Table
Inputs

Outputs

TA=B

A, S

OA=B

L
L
H
H

A=S"
A¢S
A=S"
A¢S

L
H
H
H

=
=

H HIGH Voltage Level
L LOW Voltage level

"Ao= So, A1 = Sl, A2= S2, etc.

Logic Diagram (' ACI' ACT520)

Ao

[>0

)

[>0

)

[>0

)

[>0

)

Bo---f>o
A1
B1---f>o
A2
B2---f>o
A3
B3---f>o
A4

)

[>0

)

[>0

)

[>0

)

B4---f>o
As
Bs----{:>O
A6
B6---f>o
A7
B7----{:>0

OA=B

[>0

TA = B

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5·224

AC520 • ACT520 • AC521 • ACT521
Logic Diagram CACrACT521)

Vcc
AO~~~----~~r-__~
Bo~~~~~------------~

A 1 .......--+--------1 ~~----_\
B1~~~ ~~----------~

A2 ~--r_----_I >0------_\
B2~~~ ~~------------~
A3~~~-----I ~(>-----~

B3
A4 ~--t-----_I >0------_\

B4 .....~~ ~~-------------#

•

A5~--~----_I~~----~

B5~~~ ~~~------------~
A6~~~----_I ~(r-----\

B6
A7 ~--f------~
B7 .....--'-4~
fA = B ........---------01

>-------------------------------1

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Icc/Input (,ACT520/521)

1.6

160

5-225

74AC/ACT

Units

Conditions

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = 25°C

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

80

AC520 • ACT520 • AC521 • ACT521
AC Characteristics
Ir".

!

Symblill

'r
C

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Max

Min

Units

Fig.
No.

ns

3-6

Max

Propagation Delay

3-6

An or Bn to OA=B
Propagation Delay
IA=B to OA=B

3.3
5.0

Propagation Delay
IA=B to OA=B

3.3
5.0

9.5
7.0

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Characteristics
74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Max

Propagation Delay

Min

Units

Fig.
No.

ns

3-6

Max

3·6

An or Bn to OA=B
Propagation Delay
IA=B to OA=B

5.0

Propagation Delay
IA=B to OA=B

5.0

,:3'-6

7.0

3-6

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-226

AC520 • ACT520 • AC521 • ACT521
Capacitance
Symbol

Parameter

54174AC/ACT

Units

Conditions

pF

Vcc=5.5 V

pF

Vcc=5.5 V

Typ
CIN

Input Capacitance

Cpo

Power Dissipation
Capacitance

4.5

Applications
Ripple Expansion

•
Parallel Expansion

ENABLE
LOW

5·227

AC533 • ACT533
54AC/74AC533 • 54ACT/74ACT533
Octal Transparent Latch With 3-State Outputs
Description
The 'ACI'ACT533 consists of eight latches with
3-state outputs for bus organized system
applications. The flip-flops appear transparent to
the data when Latch Enable (LE) is HIGH. When LE
is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output
Enable (DE) is LOW. When DE is HIGH the bus
output is in the high impedance state. The
'ACI'ACT533 is the same as the 'ACI'ACT373,
except that the outputs are inverted on the
'ACI'ACT533. For functional description please
refer to the 'ACI'ACT373 data sheet.
•
•
•
•
•

Connection Diagrams

Eight Latches in a Single Package
3·State Outputs for Bus Interfacing
Outputs Source/Sink 24 mA
'ACT533 has TTL·Compatible Inputs
Inverted Output VerSion of 'ACT373

Pin Assignment
for DIP, Flatpak and SOIC

03 02 '02 01 01
~0wl1lw

Ordering Code: See Section 6

Logic Symbol

03[!]

moo

GRO[iQ]

moo

LE[j]

[iJOE

04[1]

~vcc

04[il]

§lo?
§J[i]]~[jB~
05

05 06

06

07

Pin Assignment
for LCC

Pin Names
Do - 07
Data Inputs
LE
Latch Enable Input
DE
Output Enable Input
(50 - 07
Complementary 3-State Outputs

5-228

AC533 • ACT533
Logic Diagram

00

as

0,

Os

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

•
DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

74AC/ACT

Units

Conditions

Icc

Maximum Quiescent
Supply Current

160

80

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

8.0

8.0

p,A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

ICCT

Maximum Additional
Icc/Input ('ACT533)

1.6

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

5·229

AC533 • ACT533
AC Characteristics
74AC

Vee·

TA=+25°C
CL=50 pF

54AC

74AC

TA= -55°C
to + 125°C
CL=50 pF

TA=-40oC
to + 85°C
CL=50 pF

Min

Min

Units

Fig.
No.

ns

3·5

tPHL

ns

3·5

tPLH

ns

3·6

ns

3·6

(V)

Min

Typ

Max

Max

Max

8.0
5.0

tPLH

tPHL

Propagation Delay
LE to On

tPZH

Output Enable Time

3.3
5.0

ns

3·7

tPZL

Output Enable Time

3.3
5.0

ns

3·8

tPHZ

Output Disable Time

3.3
5.0

7.0
5.0

3·7

tpLZ

Output Disable Time

3.3
5.0

5.0
3.5

3·8

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements
74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

t8

Units

Fig.
No.

3-9

th

Hold Time, HIGH or LOW
On to LE

tw

LE Pulse Width, HIGH

3.3
5.0

3.0
2.5

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.
5-230

AC533

• ACT533

AC Characteristics

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA= + 25°C
CL= 50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Units

Fig.
No.

ns

3·5

tPHL

ns

3·5

tPLH

ns

3·6

ns

3·6

Min

Typ

tPLH

Max

Max

Max

7.0

tPHL

Propagation Delay
LE to On

5.0

tPZH

Output Enable Time

5.0

6.0

tPZL

Output Enable Time

5.0

5.5

tPHZ

Output Disable Time

5.0

7.5

tpLZ

Output Disable Time

5.0

5.0

3·7

3·7
ns

3·8

Units

Fig.
No.

Dn to LE

ns

3-9

th

Hold Time, HIGH or LOW
Dn to LE

ns

3·9

tw

LE Pulse Width, HIGH

'Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements
74ACT

54ACT

74ACT

TA=+25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Guaranteed Minimum

ts

5.0

3-6

2.0

II

'Voltage Range 5.0 is 5.0 V ± 0.5 V

J

(J

Military parameters given herein are for general references only. For current military specifications
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or accoun

5·231

•

AC533 • ACT533
Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

pF

Vcc=5.5 V

pF

Vcc= 5.5 V

Typ

CIN

Input Capacitance

Cpo

Power Dissipation
Capacitance

4.5

5-232

AC534 • ACT534
54AC/74AC534 • 54ACT/74ACT534
Octal D-Type Flip-Flop With 3-State Outputs
Description

Connection Diagrams

The 'ACI'ACT534 is a high-speed, low-power octal
Ootype flip-flop featuring separate Ootype inputs for
each flip-flop and 3-state outputs for bus-oriented
applications_ A buffered Clock (CP) and Output
Enable (OE) are common to all flip-flops_ The
'ACI'ACT534 is the same as the 'ACI'ACT374
except that the outputs are inverted.
•
•
•
•
•
•

Edge-Triggered D-Type Inputs
Buffered Positive Edge-Triggered Clock
3-State Outputs for Bus-Oriented Applications
Outputs Source/Sink 24 mA
'ACT534 has TTL-Compatible Inputs
Inverted Output Version of 'ACI'ACT374

Ordering Code: See Section 6

Pin Assignment
for DIP, Flatpak and SOIC

Logic Symbol

03

02

Cl2 01

01

~w~[]]11l

Do 0, 02 03 04 05 06 07

cp
OE

Cl3 []]

moo

GNO[i]]

[2]00

CP!Iil

ITlOE

04[12]

@VCC

04§

[iill07

~[i5][i5]@][i]
05

05

06

06

07

Pin Assignment
for LCC

Pin Names
Do - 07
CP
OE

00-07

Data Inputs
Clock Pulse Input
3-State Output Enable Input
Complementary 3-State Outputs

5-233

•

AC534 • ACT534
Functional Description
Clock (CP) transition. With the Output Enable (OE)
LOW, the contents of the eight flip-flops are
available at the outputs. When the OE is HIGH, the
outputs go to the high impedance state. Operation
of the OE input does not affect the state of the
flip-flops.

The 'ACI'ACT534 consists of eight edge-triggered
flip-flops with individual D-type inputs and 3-state
complementary outputs. The buffered clock and
buffered Output Enable are common to all flipflops. The eight flip-flops will store the state of
their individual D inputs that meet the setup and
hold times requirements on the LOW-to-HIGH

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

ICCT

Maximum Additional
Iccllnput (,ACT534)

1.6

160

5-234

74AC/ACT

Units

Conditions

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

8.0

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

8.0

AC534 • ACT534
AC Characteristics

Vee·
(V)

Symbol

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Fig.
No.

MHz

3-3

ns

3-6

ns

3-6

ns

3·7

ns

3-8

Max

125
150

fmax

Units

tPLH
tPHL

Propagation Delay
CP to On

tPZH

Output Enable Time

3.3
5.0

tPZL

Output Enable Time

3.3
5.0

8.5
6.0

tPHZ

Output Disable Time

3.3
5.0

9.0
7.0

3·7

tpLZ

Output Disable Time

3.3
5.0

7.5
6.0

3-8

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

It;~'''j,~~,

AC

OP~'~~9::lR)qoi~ments

Symbol

74AC

54AC

74AC

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Units

Fig.
No.

ns

3-9

ns

3-9

ns

3·6

Guaranteed Minimum
ts

Setup Time,
HIGH or LOW
Dn to CP

th

Hold Time, HIGH or LOW
Dn to CP

3.3
5.0

tw

CP Pulse Width,
HIGH or LOW

3.3
5.0

3.5
2.5

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specificatio
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or acco nt r

5·235

•

AC534 • ACT534
AC Characteristics
74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Typ

Max

Max

tPLH
tPHL
tPZH

Output Enable Time

5.0

5.5

tPZL

Output Enable Time

5.0

5.5

tPHZ

Output Disable Time

5.0

7.0

tpLZ

Output Disable Time

5.0

5.0

Fig.
No.

MHz

3·3

ns

3·6

Max

fmax

Propagation Delay
CP to On

Units

5.0
7

ns

3·8

Units

Fig.
No.

'Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements
74ACT
Sym

54ACT

74ACT

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

ts
On to CP

th

Hold Time, HIGH or LOW
On to CP

5.0

tw

CP Pulse Width,
HIGH or LOW

5.0

2.5

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-236

AC534 • ACT534

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

pF

Vcc=5.5 V

pF

Vcc=5.5 V

Typ

CIN

Input Capacitance

Cpo

Power Dissipation
Capacitance

4.5

5·237

AC540 • ACT540 • AC541 • ACT541
54AC/74AC540 • 54ACT/74ACT540
54AC/74AC541 • 54ACT/74ACT541
Octal Buffer/Line Driver With 3-State Outputs
Description
The 'ACI'ACT540 and 'ACI'ACT541 are octal
bufferlline drivers designed to be employed as
memory and address drivers, clock drivers and bus
oriented transmitter/receivers. The 'ACI'ACT541 is a
noninverting option of the 'ACI'ACT540.
These devices are similar in function to the
'ACI'ACT240 and 'ACI'ACT244 while providing flow·
through architecture (inputs on opposite side from
outputs). This pinout arrangement makes these
devices especially useful as output ports for
microprocessors, allowing ease of layout and
greater PC board density.

Connection Diagrams
vee

rn
GNO

[iQ]

ITIl

• 3·State Outputs
• Inputs and Outputs Opposite Side of Package,
Allowing Easier Interface to Microprocessors
• Output Source/Sink 24 mA
• 'ACI'ACT540 Provides Inverted Outputs
• 'ACI'ACT541 Provides Noninverted Outputs
• 'ACT540 and 'ACT541 have TTL·Compatible Inputs

'ACI'ACT540

vee
OE2

Ordering Code: See Section 6

W
GNO i1<>l1

Truth Table

ITIl

Outputs

Inputs

JOo

OJ OE

cp[i1]

Logic Symbol

(h~

~vcc

06[i1]

[iIDoo
~[i:sJ~[j]~
Os 04 03 Cb 01

Do 0, 02 03 04 05 06 07

Pin Assignment
for LCC

CP
OE

Pin Names
Do - 07
CP

DE:
00· (57

Data Inputs
Clock Pulse Input
3-State Output Enable Input
3-State Outputs

5-246

AC564 • ACT564
Functional Description
The 'AC/'ACT564 consists of eight edge-triggered
flip-flops with individual D-type inputs and 3-state
complementary outputs_ The buffered clock and
buffered Output Enable are common to all flipflops. The eight flip-flops will store the state of
their individual 0 inputs that meet the setup and
hold times requirements on the LOW-to-HIGH

Clock (CP) transition. With the Output Enable (OE)
LOW, the contents of the eight flip-flops are
available at the outputs. When OE is HIGH, the
outputs go to the high impedance state. Operation
of the OE input does not affect the state of the
flip-flops.

Function Table
Inputs

-

Internal

Outputs
Function

OE

CP

0

Q

0

H
H
H
H
L
L
L
L

H
H
I
I
I
I
H
H

L
H
L
H
L
H
L
H

NC
NC
H
L
H
L
NC
NC

Z
Z
Z
Z

H
L
NC
NC

Hold
Hold
Load
Load
Data Available
Data Available
No Change in Data
No Change in Data

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z= High Impedance
= LOW-to-HIGH Transition
NC = No Change

r

Logic Diagram
05

DO

06

CP

~~>-~~---+-+---~~~--~-+---~-r--~~T----*~---~

00

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-247

•

AC564 • ACT564
DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

74AC/ACT

Units

Conditions

160

80

p,A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

8.0

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

Iccl

Maximum Additional
Iccllnput (,ACT564)

1.6

1.5

mA

VIN = Vcc - 2.1 V
Vcc=5.5 V,
TA = Worst Case

AC Characteristics

Vcc·
(V)

Symbol

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA=-40°C
to +85°C
CL=50 pF

Min

Min

Units

Fig.
No.

fmax

MHz

3·3

tPLH

ns

3·6

I

L(

Min

Typ

Max

Max

Max

tPHL

Propagation Delay
CP to On

ns

3·6

tPZH

Output Enable Time

ns

3·7

tPZL

Output Enable Time

3.3
5.0

tPHZ

Output Disable Time

3.3
5.0

9.5
7.0

3·7

tpLZ

Output Disable Time

3.3
5.0

7.5
5.5

3·8

3·8

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·248

AC564 • ACT564
AC Operating Requirements
74AC

54AC

74AC

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Units

ts

Fig.
No.

3·9
Dn to CP

th

Hold Time, HIGH or LOW
Dn to CP

3.3
5.0

tw

CP Pulse Width,
HIGH or LOW

3.3
5.0

3.5
2.5

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

•

AC Characteristics

Symbol

Parameter

Vcc·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Units

Fig.
No.

MHz

3·3

Max

fmax

Maximum Clock
Frequency

5.0

85

90

tPLH

Propagation Delay
CP to On

5.0

1.0

6.5

10.5

1.0

12.5

1.0

11.5

ns

3·6

tPHL

Propagation Delay
CP to On

5.0

1.0

6.0

9.5

1.0

11.5

1.0

10.5

ns

3·6

tPZH

Output Enable Time

5.0

1.0

5.5

9.0

1.0

10.5

1.0

9.5

ns

3·7

tPZL

Output Enable Time

5.0

1.0

5.5

8.5

1.0

10.5

1.0

9.5

ns

3·8

tPHZ

Output Disable Time

5.0

1.0

7.0

10.5

1.0

12.5

1.0

11.5

ns

3·7

tpLZ

Output Disable Time

5.0

1.0

5.0

8.0

1.0

9.0

1.0

8.5

ns

3·8

65

75

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·249

AC564 • ACT564
AC Operating Requirements

Symbol

Parameter

Vcc·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Setup Time,
HIGH or LOW
On to CP

5.0

1.0

2.5

3.0

3.0

ns

3·9

th

Hold Time, HIGH or LOW
On to CP

5.0

-0.5

1.0

1.0

1.0

ns

3·9

tw

LE Pulse Width,
HIGH or LOW

5.0

2.5

3.0

5.0

3.5

ns

3·6

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

50.0

pF

Vcc=5.5 V

5·250

AC568 • AC569
54AC/74AC568 • 54AC/74AC569
4-Bit Bidirectional Counters With 3-State Outputs
Description

Connection Diagrams

The 'AC568 and 'AC569 are fully synchronous,
bidirectional counters with 3-state outputs. The
'AC568 is a BCD decade counter; the 'AC569 is a
modulo 16 binary counter. They feature preset
capability for programmable operation, carry
lookahead for easy cascading, and a ufo input to
control the direction of counting. For maximum
flexibility there are both synchronous and master
asynchronous reset inputs as well as both Clocked
Carry (CC) and Terminal Count (Fe) outputs. All
state changes except Master Reset are initiated by
the rising edge of the clock. A HIGH signal on the
Output Enable (OE) input forces the output buffers
into the high-impedance state but does not prevent
counting, resetting or parallel loading.
•
•
•
•
•
•

Synchronous Counting and Loading
Lookahead Carry Capability for Easy Cascading
Preset Capability for Programmable Operation
3·State Outputs for Bus Organized Systems
Outputs Source/Sink 24 mA
Synchronous and Asynchronous Resets

Pin Assignment
for DIP, Flatpak and SOIC

MR CEP P3

Pl

SRW

Logic Symbol

CEP
CET
CP

P2

wll][§J[§J@]

Ordering Code: See Section 6

[}] Po

[2Jcp

GNDIi:Ql

CC
TC

i'E1TIJ

[i] UfO

CET [g]

~vcc

C31i]]

~fC

[14]~~[jl]~
01 00 OE CC

02

Pin Assignment
for LCC and PCC

Pin Names
Po - P3
Parallel Data Inputs
CEP

CET
CP
PE

ufo

OE
MR
SR

Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Parallel Enable Input
Up/Down Count Control Input

00 - 03

TC
CC

5-251

Output Enable Input
Master Reset Input
Synchronous Reset Input
3-State Parallel Data Outputs
Terminal Count Output
Clocked Carry Output

AC568 • AC569
Logic Diagram (,AC568)

Po

PE

------+++--------~

I

I

I ~
I

A
CP

~+

I
1
L..4-_---+

I

~ !

l

....

00

0,

0,

0,

Please note that this diagram Is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-252

AC568 • ACT569
logic Diagram (,AC569)
P,

r

-t-T

~I~

W

1--,

r+

LD

P,

i ()? !~ - '-++--++++-H----+--+++++-+-++_____.~ L.....
I~ ~:;:

:

I I

I"
:1

UfO

--I

-I>-

I

_.....

-.....

CP

C IQ

UP
ON

Til

I

.....
.....

L Ilr

~S_R ~

ENFII-

I

II

I~ ll~

'I

'I

=- =-

LDTBT

I
I
I

UP

-

BF

D.,"ETAILA

-0.
ENF
Co l'i SA

_

-

DETAILA

~...--....

~

DETAILA

1--_ _--1

Lr--..-.....

I

CP

! I: }, 1+ ~;~
-t>

!

l

I

.. 1.0

00

0,

0,

0,

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5·253

•

AC568 • AC569
State Diagrams
'AC568

'AC569

- - ..... COUNT DOWN
_COUNT UP

Logic Equations:

-

Count Enable
= CEP
Up ('AC568): TC = 00 •
(,AC569): TC = 00 •
Down (Both): TC = 00 •

-COUNTUP

• CET • PE

- __ COUNT DOWN

01 • 02 • 03 • (Up) • CET
01 • 02 • 03 • (Up) • CET
01 • 02 • 03 • (Down) • CET

Functional Description
The 'AC568 counts modul0-10 in the BCD (8421)
sequence. From state 9 (HLLH) it will increment to
o (LLLL) in the Up mode; in Down mode it will
decrement from 0 to 9. The 'AC569 counts in the
modul0-16 binary sequence. From state 15 it will
increment to state 0 in the Up mode; in the Down
mode it will decrement from 0 to 15. The clock
inputs of all flip-flops are driven in parallel through
a clock buffer. All state changes (except due to
Master Reset) occur synchronously with the LOWto-HIGH transition of the Clock Pulse (CP) input
signal.

to be loaded into the flip-flops on the next rising
edge of CPo With MR, SR and PE HIGH, CEP and
CET permit counting when both are LOW.
Conversely, a HIGH signal on either CEP or CET
inhibits counting.
The 'AC568 and 'AC569 use edge-triggered flipflops and changing the SR, PE, CEP, CET or U/O
inputs when the CP is in either state does not
cause errors, provided that the recommended
setup and hold times, with respect to the rising
edge of CP, are observed.

The circuits have five fundamental modes of
operation, in order of precedence: asynchronous
reset, synchronous reset, parallel load, count and
hold. Five control inputs-Master Reset (MR),
Synchronous Reset (SR), Parallel Enable (PE),
Count Enable Parallel (CEP) and Count Enable
Trickle (CET)-plus the Up/Down (UfO) input
determine the mode of operation, as shown in the
Mode Select Table. A LOW signal on MR overrides
all other inputs and asynchronously forces the flipflop 0 outputs LOW. A LOW signal on SR
overrides counting and parallel loading and allows
the 0 outputs to go LOW on the next rising edge
of CPo A LOW signal on PE overrides counting and
allows information on the Parallel Data (Pn) inputs

Two types of outputs are provided as
overflow/underflow indicators. The Terminal Count
(TC) output is normally HIGH and goes LOW
providing CET is LOW, when the counter reaches
zero in the Down mode, or reaches maximum (9 for
the 'AC568, 15 for the 'AC569) in the Up mode. TC
will then remain LOW until a state change occurs,
whether by counting or presetting, or until U/O or
CET is changed. To implement synchronous
multistage counters, the connections between the
TC output and the CEP and CET inputs can provide
either slow or fast carry propagation. Figure a
shows the connections for simple ripple carry, in
which the clock period must be longer than the CP
to TC delay of the first stage, plus the cumulative

5-254

AC568 • AC569
CET to fC delays of the intermediate stages, plus
the CEi to CP setup time of the last stage. This
total delay plus setup time sets the upper limit on
clock frequency. For faster clock rates, the carry
lookahead connections shown in Figure bare
recommended. In this scheme the ripple delay
through the intermediate stages commences with
the same clock that causes the first stage to tick
over from max to min in the Up mode, or min to
max in the Down mode, to start its final cycle.
Since this final cycle takes 10 ('AC568) or 16
('AC569) clocks to complete, there is plenty of time
for the ripple to progress through the intermediate
stages. The critical timing that limits the clock
period is the CP to fC delay of the first stage plus
the CEP to CP setup time of the last stage. The TC

output is subject to decoding spikes due to
internal race conditions and is therefore not
recommended for use as a clock or asynchronous
reset for flip·flops, registers or counters. For such
applications, the Clocked Carry (CC) output is
provided. The C'C output is normally HIGH. When
'SA and PE are HIGH, and CEP, eET and TC are
LOW, the C'C output will go LOW when the clock
next goes LOW and will stay LOW until the clock
goes HIGH again, as shown in the C'C Truth Table.
When the Output Enable (DE) is LOW, the parallel
data outputs 00 - 03 are active and follow the flipflop Q outputs. A HIGH signal on OE forces 00·03
to the high-Z state but does not prevent counting,
loading or resetting.

Mode Select Table

CC Truth Table

Inputs
MR SA PE CEP CEi

X

L
H
H

L
H

H
H
H
H

H
H
H
H

X
X
L
H
H
H
H

ufo

PE

CEP

CET

fC*

CP

CC

L

X

X
X

L

X
X

X
X
X

X
X
X
X

X
X
X
X
X

H
H
H
H
H

X
X
X

X
X
X

Asynchronous Reset
Synchronous Reset
Parallel Load

H

X

X

H
L
L

X
X

Hold
Hold
Count Up
Count Down

H
L

X
X

H

H

H

L

L

H
L

X

V

= 'i'C is generated internally
H = HIGH Voltage Level
*

L = LOW Voltage Level
X = Immaterial

Multistage Counter with Ripple Carry

,o""j~:'
cp

Figure b:

H

X

X
X
X

X

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

Figure a:

Output

SR

X
X
X

L
L

Inputs

Operating
Mode

~

"H'" "Hm "He<' "H.

'_E_T_--,

.. TO ALL STAGES

Multistage Counter with Lookahead Carry

cP_>---.

5-255

V

•

AC568 • AC569
DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC

74AC

Units

Conditions

Icc

Maximum Quiescent
Supply Current

160

80

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

8.0

8.0

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

AC Characteristics

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Units

Fig.
No.

fmax

87
117

MHz

3·3

tPLH

10.0
7.5

ns

3-6

ns

3-6

ns

3-6

ns

3-6

Min

tPHL

Typ

Propagation Del~,
CP to On (PE HIGH or

Max

Max

Max

LOW)

tPLH

Propagation Delay
CP to fC

tPHL

Propagation Delay
CP to TC

3.3
5.0

Propagation Delay

'OEf to fC

3.3
5.0

10.5
7.5

tPHL

Propagation Delay
CET to fC

3.3
5.0

10.0
7.0

tPLH

Propagation Delay
UfO' to iC ('568)

3.3
5.0

10.5
7.5

ns

3-6

tPHL

Propagation Delay
UfO' to fC ('568)

3.3
5.0

9.0
6.5

ns

3-6

tPLH

~-6
,/'

3-6

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-256

AC568

• AC569

AC Characteristics (cont'd)

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Min
3.3
5.0

Typ

Max

Max

Units

Fig.
No.

Max

10.5
7.5

ns

3-6

9.0
6.5

ns

3-6

tPLH

ns

3-6

tPHL

ns

3-6

tPLH

tPLH

Propagation Delay
CEP or CET to CC

ns

3·6

tPHL

Propagation Delay
CEP or CET to CC

ns

3-6

tPHL

Propagation Delay
MR to On

3.3
5.0

12.5
9.0

3-6

tPZH

Output Enable Time
OE to On

3.3
5.0

7.5
5.5

3-7

tPZL

Output Enable Time
OE to On

3.3
5.0

7.5
5.5

3-8

tPHZ

Output Disable Time
OE to On

3.3
5.0

9.5
7.0

ns

3-7

Output Disable Time
On

3.3
5.0

11.0
8.0

ns

3-8

tPZL

OE to

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-257

•

AC568 • AC569
AC Operating Requirements

Symbol

Parameter

Vee·
(V)

ts

Setup Time,
HIGH or LOW
Pn to CP

3_3

5.0
3.3

th

5.0
3.3

ts

5.0

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum

Setup Time,
HIGH or LOW
PE to CP

th

Hold Time,
HIGH or LOW
PE to CP

ts

Setup Time,
HIGH or LOW
uio to CP ('568)

3-9

o
o

ns

3-9

8.0
12.5

ns

3-9

ns

3-9

ns

3-9

ns

3-9

ts

Setup Time,
HIGH or LOW
UfO to CP ('569)

th

Hold Time,
HIGH or LOW
UiO to CP

ts

Setup Time,
HIGH or LOW
SR to CP

th

Hold Time,
HIGH or LOW
SR to CP

3.3

5.0
3.3

5.0
3.3

5.0
3.3

5.0
3.3

5.0

No_

ns

5.0
3.3

Fig_

8.0
6.0

th

ts

Units

12.5
9.0

3-9

12.5
9.0

3-9

o
o

ns

3-9

4.0
3.0

ns

3-9

-1.5
-1.0

ns

3-9

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-258

AC568 • AC569
AC Operating Requirements (cont'd)
74AC
if"' '""-\~~, %"""""~\

sym~qr )

54AC

74AC

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Units

Fig.

No.

tw
tw

MR Pulse Width, LOW

tree

MR Recovery Time

3.3

4.0

5.0

3.0

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative .

•

Capacitance
Symbol

54/74AC

Parameter

Units

Conditions

pF

Vcc=5.5 V

pF

Vcc=5.5 V

Typ

CIN

Input Capacitance

CPD

Power Dissipation
Capacitance

4.5

5·259

AC573 • ACT573
54AC/74AC573 • 54ACT/74ACT573
Octal D-Type Latch With 3-State Outputs
Description
The 'ACI'ACT573 is a high-speed octal latch with
buffered common Latch Enable (LE) and buffered
common Output Enable (DE) inputs_

Connection Diagrams

The 'ACI'ACT573 is functionally identical to the
'ACI'ACT373 but has inputs and outputs on
opposite sides_
• Inputs and Outputs on Opposite Sides of
Package Allowing Easy Interface with
Microprocessors
• Useful as Input or Output Port for
Microprocessors
• Functionally Identical to 'ACt' ACT373
• 3-State Outputs for Bus Interfacing
• Outputs Source/Sink 24 mA
• 'ACT573 has TTL-Compatible Inputs

Pin Assignment
for DIP, Flatpak and SOIC

Ordering Code: See Section 6
06 05 04 03 02
[!][lJ[!]~[IJ

Logic Symbol

D?[]]

rn 0,

GND

[1Q]

rn Do

LE

[j]

[Doe
~Vcc

07§
06

LE
OE

[!9]00

Ii]

§][i][i]IiZ][i]
05

04

03

02

01

Pin Assignment
for LCC

Pin Names
Do - 07
Data Inputs
LE
Latch Enable Input
OE
3-State Output Enable Input
00 - 07
3-State Latch Outputs

5-260

AC573 • ACT573

Functional Description

Truth Table

The 'ACI'ACT573 contains eight Ootype latches with
3-state output buffers. When the Latch Enable (LE)
input is HIGH, data on the On inputs enters the
latches. In this condition the latches are
transparent, i.e., a latch output will change state
each time its 0 input changes. When LE is LOW
the latches store the information that was present
on the 0 inputs a setup time preceding the HIGHto-LOW transition of LE. The 3-state buffers are
controlled by the Output Enable (DE) input. When
OE is LOW, the buffers are enabled. When OE is
HIGH the buffers are in the high impedance mode
but this does not interfere with entering new data
into the latches.

Inputs

Outputs

OE

LE

0

On

L
L
L
H

H
H
L

H
L

H
H

X
X

00

X

Z

H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X= Immaterial
00 = Previous 00 before LOW·to·HIGH
Transition of Clock

•

Logic Diagram

LE--~·~--~---+----~--4---~--~~--~---+--~~--+---~---4----+---~--~

00

05

06

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-261

AC573 • ACT573
DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

74AC/ACT

Units

Conditions

160

80

p.A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=Worst Case

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

8.0

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

ICCT

Maximum Additional
Icc/Input (,ACT573)

1.6

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

AC Characteristics

Vcc*
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

9.0
6.0

tPLH
tPHL

Max

Max

Units

Fig.
No.

ns

3·5

ns

3·5

Max

tPLH

Propagation Delay
LE to On

ns

3·6

tPHL

Propagation Delay
LE to On

ns

3·6

tPZH

Output Enable Time

3.3
5.0

ns

3·7

tPZL

Output Enable Time

3.3
5.0

7.5
5.5

3·8

tPHZ

Output Disable Time

3.3
5.0

8.5
6.5

3·7

tpLZ

Output Disable Time

3.3
5.0

6.5
5.0

ns

3·8

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·262

AC573 • ACT573
AC Operating Requirements
74AC

54AC

74AC

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Units

Fig.
No.

ts
Dn to LE
th

Hold Time, HIGH or LOW
Dn to LE

3.3
5.0

o
o

tw

LE Pulse Width, HIGH

3.3
5.0

4.0
2.5

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Characteristics

Symbol

Parameter

Vee·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
Dn to On

5.0

1.0

6.0

10.5

1.0

13.5

1.0

12.0

ns

3-5

tPHL

Propagation Delay
Dn to On

5.0

1.0

6.0

10.5

1.0

13.5

1.0

12.0

ns

3-5

tPLH

Propagation Delay
LE to On

5.0

1.0

6.0

10.5

1.0

13.0

1.0

12.0

ns

3-6

tPHL

Propagation Delay
LE to On

5.0

1.0

5.5

9.5

1.0

12.0

1.0

10.5

ns

3-6

tPZH

Output Enable Time

5.0

1.0

5.5

10.0

1.0

11.5

1.0

11.0

ns

3-7

tPZL

Output Enable Time

5.0

1.0

5.5

9.5

1.0

11.0

1.0

10.5

ns

3-8

tPHZ

Output Disable Time

5.0

1.0

6.5

11.0

1.0

13.5

1.0

12.5

ns

3-7

tpLZ

Output Disable Time

5.0

1.0

5.0

8.5

1.0

10.5

1.0

9.5

ns

3-8

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-263

•

AC573 • ACT573
AC Operating Requirements

Symbol

Parameter

Vcc·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CI-=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Setup Time,
HIGH or LOW
On to LE

5.0

1.5

3.0

3.5

3.5

ns

3-9

th

Hold Time, HIGH or LOW
On to LE

5.0

-1.5

0

0.5

0

ns

3-9

tw

LE Pulse Width, HIGH

5.0

2.0

3.5

5.0

4.0

ns

3-6

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

Typ
CIN

Input Capacitance

5.0

pF

Vcc= 5.5 V

CPD

Power Dissipation
Capacitance

25.0

pF

Vcc=5.5 V

5-264

AC574 • ACT574
54AC/74AC574 • 54ACT/74ACT574
Octal D-Type Flip-Flop With 3-State Outputs
Connection Diagrams

Description
The 'ACI'ACT574 is a high-speed, low power octal
flip-flop with a buffered common Clock (CP) and a
buffered common Output Enable (OE)_ The
information presented to the D inputs is stored in
the flip-flops on the LOW-to-HIGH Clock (CP)
transition.
The 'ACI'ACT574 is functionally identical to the
'ACI'ACT374 except for the pinouts.
• Inputs and Outputs on Opposite Sides of
Package Allowing Easy Interface with
Microprocessors
• Useful as Input or Output Port for
Microprocessors
• Functionally Identical to 'ACI'ACT374
• 3-State Outputs for Bus-Oriented Applications
• Outputs Source/Sink 24 mA
• 'ACT574 has TTL-Compatible Inputs

•

Pin Assignment
for DIP, Flatpak and SOIC

06

Os

04

03

02

[I][I][I][]]@]

Ordering Code: See Section 6

Logic Symbol

0,

[9J

[I]

0,

GNO

[i]]

[IJ

DO

Cp

Ii]

WOE

o,~

~ Vee

06~

§]
~~~!1Zl~

CP
OE

05

04

03

02

01

Pin Assignment
for LCC

Pin Names
Data Inputs
Do - D7
Clock Pulse Input
CP
3-State Output Enable Input
OE
3-State Outputs
00 - 07

5-265

00

AC574 • ACT574
functional Description
The 'ACI'ACT574 consists of eight edge-triggered
flip-flops with individual D-type inputs and 3-state
true outputs. The buffered clock and buffered
Output Enable are common to all flip-flops. The
eight flip-flops will store the state of their
individual D inputs that meet the setup and hold

time requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the
contents of the eight flip-flops are available at the
outputs. When OE is HIGH, the outputs go to the
high impedance state. Operation of the DE input
does not affect the state of the flip-flops.

Function Table
Inputs

Internal

Outputs

DE CP D

Q

On

NC
NC
L
H
L
H
NC
NC

Z
Z
Z
Z

H
H
H
H
L
L
L
L

H
H
I
I
I
I
H
H

L
H
L
H
L
H
L
H

L
H
NC
NC

Function

Hold
Hold
Load
Load
Data Available
Data Available
No Change in Data
No Change in Data

H = HIGH Voltage Level
L =LOW Voltage Level
X =Immaterial
Z =High Impedance
I
= LOW-to-HIGH Clock Transition
NC = No Change

Logic Diagram

Do

06

05

~--~~~r-----~-+------~+-----~-+------~+------+-+------~+-----~

00

03

05

06

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-266

AC574 • ACT 574
DC Characteristics
Symbol

Parameter

74AC/ACT

54AC/ACT

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

S.O

ICCT

Maximum Additional
Icc/Input (,ACT574)

1.6

160

Units

Conditions

pA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=Worst Case

S.O

pA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

1.5

mA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

SO

AC Characteristics

Symbol

Jl /~'
"J
fmax

lPar!lmeter
J" ,
''\-:~

Vee·
(V)

§

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +S5°C
CL=50 pF

Min

Min

Min

"T;:'~JI

Typ

Ma><:lfn u mlGAocl
L if f
Frequency'! ':

tPLH

Max

Max

Units

Fig.
No.

MHz

3-3

ns

3-6

ns

3-6

ns

3·7

Max

tPHL

Propagation Delay
CP to On

tPZH

Output Enable Time

3.3
5.0

tPZL

Output Enable Time

3.3
5.0

6.0
4.0

,),3·S

tPHZ

Output Disable Time

3.3
5.0

7.0
5.0

3·7

tpLZ

Output Disable Time

3.3
5.0

5.0
3.5

ns

3-S

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·267

•

AC574 • ACT574
AC Operating Requirements
74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

ts

Units

Fig.
No.

ns

3·9

Dn to CP
th

Hold Time, HIGH or LOW
Dn to CP

3.3
5.0

tw

CP Pulse Width
HIGH or LOW

3.3
5.0

4.0
2.5

3·6

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Characteristics

Symbol

Parameter

Vcc·
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

Typ

Max

Max

Units

Fig.
No.

ns

3-3

Max

fmax

Maximum Clock
Frequency

5.0

100

110

tPLH

Propagation Delay
CP to On

5.0

1.0

7.0

11.0

1.0

13.0

1.0

12.0

ns

3·6

tPHL

Propagation Delay
CP to On

5.0

1.0

6.5

10.0

1.0

12.5

1.0

11.0

ns

3-6

70

85

tPZH

Output Enable Time

5.0

1.0

6.4

9.5

1.0

11.0

1.0

10.0

ns

3·7

tPZL

Output Enable Time

5.0

1.0

6.0

9.0

1.0

11.5

1.0

10.0

ns

3-8

tPHZ

Output Disable Time

5.0

1.0

7.0

10.5

1.0

12.5

1.0

11.5

ns

3·7

tpLZ

Output Disable Time

5.0

1.0

5.5

8.5

1.0

10.0

1.0

9.0

ns

3·8

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·268

AC574 • ACT574
AC Operating Requirements

Symbol

Parameter

Vcc*
(V)

74ACT

54ACT

74ACT

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Typ

Guaranteed Minimum

Units

Fig.
No.

ts

Set·up Time,
HIGH or LOW
Dn to CP

5.0

1.5

2.5

3.0

2.5

ns

3·9

th

Hold Time, HIGH or LOW
Dn to CP

5.0

-0.5

1.0

1.0

1.0

ns

3-9

tw

CP Pulse Width
HIGH or LOW

5.0

2.5

3.0

5.0

4.0

ns

3-6

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative .

Capacitance
Symbol

Parameter

54174AC/ACT

Units

Conditions

Typ

CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

40.0

pF

Vcc=5.5 V

5-269

•

AC640 -ACT640
54AC/74AC640 - 54ACT/74ACT640
Octal Bidirectional Transceiver With 3-State Outputs
Description

Connection Diagrams

The 'ACI'ACT640 octal bus transceiver is designed
for asynchronous two-way communication between
data buses. The device transmits data from bus A
to bus B when TiA" = HIGH, or from bus 8 to bus
A when T/R = LOW. The enable input can be used
to disable the device so the buses are effectively
isolated.
• Bidirectional Data Path
• A and B Outputs Sink 24 mA/Source -24 mA
• 'ACT640 has TTL-Compatible Inputs

Ordering Code: See Section 6
Pin Assignment
for DIP, Flatpak and SOIC

Pin Names
Side A Inputs or 3-State Outputs
Output Enable Input
Transmit/Receive Input
Side 8 Inputs or 3-State Outputs

Ao - A7
OE
T/R

Bo - 87

A6

As

A4

Truth Table
OE

T/R

Applied
Inputs

H
L
L
L
L

X
H
H
L
L

X
H
L
H
L

X
to
to
to
to

A
A
8
8

8
8
A
A

GND

[jQJ

B,

[Ii]

X
L
H
L
H

~W~~~lt

Ao

[j]

T/A

[j]

~OE

84

83

82

81

80

Pin Assignment
for LCC

5-270

[II

~VCG

§]1I§l[i][17J[i]

H =HIGH Voltage Level
L = LOW Voltage Level
x= Immaterial

rn A,

B6 [2]
B5

Output

A2

I ~----

M~

Valid
Direction
I/P-O/P

A3

~1Il~~m

AC640 • ACT640
DC Characteristics (unless otherwise specified)
Symbol

Parameter

74AC/ACT

54AC/ACT

Units

Conditions

Icc

Maximum Quiescent
Supply Current

160

80

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

8.0

8.0

p.A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

ICCT

Maximum Additional
Iccllnput (,ACT640)

1.6

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

AC Characteristics
74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Max

Max

Units

Fig.
No.

ns

3-5

ns

3-5

Max

3·7

tPZH

Output Enable Time

tPZL

Output Enable Time

3.3
5.0

7.5
5.5

Output Disable Time

3.3
5.0

7.0
6.0

Output Disable Time

3.3
5.0

7.5
6.0

ns

3·8

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·271

•

AC640 • ACT640
AC Characteristics
74ACT

54ACT

74ACT

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Max

Propagation Delay
An to Bn or Bn to An

tPZH

Output Enable Time

5.0

tPZL

Output Enable Time

5.0

tPHZ

Output Disable Time

5.0

tpLZ

Output Disable Time

5.0

Fig.
No.

ns

3-5

ns

3-5

ns

3-8

Max

tPLH
tPHL

Units

6.0

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

4.5

pF

Vcc=5.5 V

15.0

pF

Vcc=5.5 V

pF

Vcc=5.5 V

Typ

CIN

Input Capacitance

ClIO

Input/Output
Capacitance

CPD

Power Dissipation
Capacitance

5-272

AC643 • ACT643
54AC/74AC643 • 54ACT/74ACT643
Octal Bidirectional Transceiver With 3-State Outputs
Description

Connection Diagrams

The 'ACI'ACT643 octal bus transceiver is designed
for asynchronous two-way communication between
data buses. The device transmits data from bus A
to bus B when Tiff = HIGH, or from bus B to bus
A when Tiff = LOW. The enable input can be used
to disable the device so the buses are effectively
isolated.
•
•
•
•

Noninverting Buffers
Bidirectional Data Path
A and B Outputs Sink 24 mA/Source -24 mA
'ACT643 has TTL·Compatible Inputs

Ordering Code: See Section 6
Pin Assignment
for DIP, Flatpak and SOIC

Pin Names
Side A Inputs or 3-State Outputs
Output Enable Input
TransmitlReceive Input
Side B Inputs or 3-State Outputs

Ao - A7

DE
Tiff
Bo - B7

A6

Truth Table
OE

T/R

Applied
Inputs

H
L
L
L
L

X
H
H
L
L

X
H
L
H
L

Valid
Direction
I/P-O/P
X
A to
A to
B to
B to

B
B
A
A

A5

A4

A3

A2

1]][l][§J[]][I]

Output

MI]]

rn A1

GND

I!]]

III Ao

6,

ITIl

[j]

@lvee

[i]]

[i]]OE

65

~[i][i]@][i]

X
L
H
H
L

B4

63

B2

B1

Bo

Pin Assignment
for LCC

H = HIGH Voltage Level
L LOW Voltage Level
X Immaterial

=
=

5-273

T/R

66~

•

AC643 • ACT643
DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC/ACT

74AC/ACT

Units

Conditions

160

80

p,A

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

Icc

Maximum Quiescent
Supply Current

Icc

Maximum Quiescent
Supply Current

8.0

8.0

p,A

VIN=VCC or
Ground,
Vcc=5.5 V,
TA=25°C

ICCT

Maximum Additional
Iccllnput (,ACT643)

1.6

1.5

rnA

VIN=Vcc-2.1 V
Vcc=5.5 V,
TA = Worst Case

AC Characteristics

Vee·
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Units

Fig.
No.

tPLH

ns

3-5

tPHL

ns

3-5

ns

3-7

Typ

Max

Min

Max

Min

Max

tPZH

Output Enable Time

tPZL

Output Enable Time

3.3
5.0

tPHZ

Output Disable Time

3.3
5.0

7.0
6.0

/ 3-7

tpLZ

Output Disable Time

3.3
5.0

7.5
6.0

3-8

3-8
,:7-1'

·Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·274

AC643 • ACT643
AC Characteristics
74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Typ

Max

Max

Propagation Delay
An to Bn or Bn to An

tPZH

Output Enable Time

5.0

tPZL

Output Enable Time

5.0

6.0

tPHZ

Output Disable Time

5.0

6.5

tpLZ

Output Disable Time

5.0

6.0

Fig.
No.

ns

3-5

ns

3-5

Max

tPLH
tPHL

Units

3-7

3·7
ns

3·8

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

Parameter

54/74AC/ACT

Units

Conditions

4.5

pF

Vcc=5.5 V

15.0

pF

Vcc=5.5 V

pF

Vcc=5.5 V

Typ
CIN

Input Capacitance

CliO

InputlOutput
Capacitance

Cpo

Power Dissipation
Capacitance

5·275

•

AC646
54AC/74AC646
Octal Transceiver/Register With 3-State Outputs
Connection Diagrams

Description
The 'AC646 consists of registered bus transceiver
circuits, with outputs, D-type flip-flops and control
circuitry providing multiplexed transmission of data
directly from the input bus or from the internal
storage registers. Data on the A or B bus will be
loaded into the respective registers on the LOW-toHIGH transition of the appropriate clock pin (CAB
or CBA). The four fundamental data handling
functions available are illustrated in the following
figures.
Real Time Transfer
A-Bus to B-Bus

Real Time Transfer
B-Bus to A-Bus

A-Bus

A-Bus

Vcc
CAB
SBA

G
Bo
B1

B2

.....I---------i.~ .....I---------I.~

B3

~(~ll~ (~rt~j

B4

B-Bus

....

I----------I.~

Figure 1

Storage
from Bus to Register

.

A-Bus

~t
~EG I

.

Figure 3

Bs

A7

B6

Gnd

B7

I----~--------I.~

Figure 2

Pin Assignment
for DIP, Flatpak and SOIC

Transfer
from Register to Bus

.
.

A-Bus

REU I..t t
• .. .

I

REG

B-Bus

•
•
•
•
•
•

•
•

B-Bus

.....

A6

B-Bus
Figure 4

•

As

A4

As

NC

A2

A1

Ao

1TIl[ill~~rn~rn

•••I
REG

•
•

A.[j]

[I] DIR

A7~

III SAB
111 CAB
III NC

GND~

NC~

Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data Transfers
Choice of True and Inverting Data Paths
3-State Outputs
300 mil Slim Dual In-Line Package
Outputs Source/Sink 24 mA

B7~

~vcc

B.im

I21lCBA

B5[j]]

~SBA

~~~~I?]]~~
84
83
82 NC 81
80
G

Pin Assignment
for LCC

Ordering Code: See Section 6
Logic Symbol

Pin Names
Ao - A7

CAB
SAB

Bo - B7

DIR

CAB,CBA
SAB, SSA
DIR, IT

5-276

Data Register Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Inputs

AC646
Function Table
Data 1/0·

Inputs

Operation or Function

IT

DIR

CAB

CBA

SAB

SBA

Ao - A7

Bo - B7

H
H

X
X

H or L

H or L

.r

.r

X
X

X
X

Input

Input

Isolation
Store A and B Data

L
L

L
L

X
X

X
X

X
X

L
H

Output

Input

Real Time B Data to A Bus
Stored B Data to A Bus

L
L

H
H

X
H or L

X
X

L
H

X
X

Input

Output

Real Time A Data to B Bus
Stored A Data to B Bus

-The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are
always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
I= LOW-to-HIGH Transition

Logic Diagram
G--~or

DIR

---O~-L.J

CBA------------~--------~--~~>O-----_+~

SBA
CAB
SAB

----:----+-----D"""f>
---'--+-+----1:>0,<>1:>-,

-++.+--/-------Do
Co 10---+-1--+

Ao

--I-t-l--+
I
I

I
I

HH--t'-.... Bo

Do

t-I_+--
---L....J

CBA-------~-------~~>-------~

SBA ----,-----+------1
CAB -------..,---,
SAB ------+-~--_i

Do
ColO---+-~

---I++-H
I

HH-t'--+-Bo

Ao ....

I

I
I

Do

H-+--oICo

I

I
I
L

~------------~'-/~-----------~
TO 7 OTHER CHANNELS
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

5-281

•

AC648
DC Characteristics (unless otherwise specified)
Symbol

Parameter

54AC

74AC

Icc

Maximum Quiescent
Supply Current

160

80

Icc

Maximum Quiescent
Supply Current

8.0

8.0

Conditions

Units

itA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA = Worst Case

itA

VIN =Vcc or
Ground,
Vcc=5.5 V,
TA=25°C

AC Characteristics

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA= + 25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH

Propagation Delay
Clock to Bus

3.3
5.0

1.0
1.0

10.0
7.0

15.5
11.0

1.0
1.0

18.5
13.0

1.0
1.0

17.0
12.0

ns

3-6

tPHL

Propagation Delay
Clock to Bus

3.3
5.0

1.0
1.0

8.5
6.0

13.5
10.5

1.0
1.0

16.5
13.0

1.0
1.0

14.5
11.5

ns

3-6

tPLH

Propagation Delay
Bus to Bus

3.3
5.0

1.0
1.0

6.0
4.0

10.0
7.0

1.0
1.0

12.0
8.5

1.0
1.0

11.0
7.5

ns

3-5

tPHL

Propagation Delay
Bus to Bus

3.3
5.0

1.0
1.0

5.5
3.5

9.0
7.5

1.0
1.0

11.0
9.0

1.0
1.0

10.0
8.0

ns

3-5

tPLH

Propagation Delay
SBA or SAB to An or Bn
(with An or Bn HIGH or
LOW)

3.3
5.0

1.0
1.0

7.5
5.5

12.5
9.0

1.0
1.0

15.0
11.0

1.0
1.0

14.0
10.0

ns

3·6

tPHL

Propagation Delay
SBA or SAB to An or Bn
(with An or Bn HIGH or
LOW)

3.3
5.0

1.0
1.0

7.5
5.5

12.5
9.5

1.0
1.0

15.5
11.5

1.0
1.0

14.0
10.5

ns

3-6

3.3
5.0

1.0
1.0

6.5
5.0

11.0
8.0

1.0
1.0

12.5
9.5

1.0
1.0

11.5
9.0

ns

3-7

3.3
5.0

1.0
1.0

7.0
5.0

11.0
8.0

1.0
1.0

13.5
9.5

1.0
1.0

12.5
9.0

ns

3-8

3.3
5.0

1.0
1.0

7.5
6.0

12.0
10.0

1.0
1.0

13.5
12.0

1.0
1.0

13.0
11.0

ns

3-7

3.3
5.0

1.0
1.0

7.0
5.5

11.5
9.0

1.0
1.0

13.5
10.5

1.0
1.0

12.5
10.0

ns

3-8

tPZH
tPZL
tPHZ
tpLZ

Enable Time

G to An or Bn
Enable Time

G to An or Bn
Disable Time

G to An or Bn
Disable Time

G to An or Bn

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing in·
formation please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-282

AC648
AC Characteristics, cont'd

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPZH

Enable Time
DIR to An or Bn

3.3
5.0

1.0
1.0

6.0
4.5

12.5
9.5

1.0
1.0

15.5
11.5

1.0
1.0

14.0
10.5

ns

3·7

tPZL

Enable Time
DIR to An or Bn

3.3
5.0

1.0
1.0

6.5
4.5

13.0
9.0

1.0
1.0

15.0
10.0

1.0
1.0

14.5
10.5

ns

3·8

tPHZ

Disable Time
DIR to An or Bn

3.3
5.0

1.0
1.0

7.0
5.5

11.5
9.0

1.0
1.0

15.0
10.5

1.0
1.0

13.5
10.0

ns

3·7

tpLZ

Disable Time
DIR to An or Bn

3.3
5.0

1.0
1.0

7.0
5.0

13.5
9.5

1.0
1.0

15.5
11.5

1.0
1.0

15.0
10.0

ns

3·8

Units

Fig.
No.

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements

Symbol

Parameter

Vcc·
(V)

74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Typ

Guaranteed Minimum

ts

Setup Time, HIGH or
LOW, Bus to Clock

3.3
5.0

2.0
1.5

3.0
2.0

4.0
2.5

3.5
2.0

ns

3·9

tn

Hold Time, HIGH or
LOW, Bus to Clock

3.3
5.0

-1.5
-0.5

0
1.0

0
1.0

0
1.0

ns

3·9

tw

Clock Pulse Width
HIGH or LOW

3.3
5.0

2.0
2.0

3.5
3.0

4.5
3.5

4.0
3.0

ns

3·6

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing in·
formation please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

Capacitance
Symbol

54/74AC

Parameter

Units

Conditions

Typ
CIN

Input Capacitance

4.5

pF

Vcc=5.5 V

Cpo

Power Dissipation
Capacitance

65.0

pF

Vcc=5.5 V

CliO

Input/Output
Capacitance

15.0

pF

Vcc=5.5 V

5·283

•

AC705 • ACT705
54AC/74AC705 • 54ACT/74ACT705
Arithmetic Logic Unit for Digital Signal Processing Applications
Description

Connection Diagrams

The 'ACI'ACT705 is a high-speed arithmetic
processing integrated circuit which is packaged in
an 84-pin lead less chip carrier. It features separate
input busses that provide data and instruction
codes to a high-speed single-cycle 16-bit ALU and
an 8-bit by 8-bit parallel multiplier/accumulator.

~~~&~~&~~~~~£~~~~~~~~

~~~~u.u~~~n~wggngg"u~

AE 33
ACOUT 34

6E

The ALU is a 16-bit parallel design which supports
sixteen arithmetic and logic functions, as well as
carry-in/out and borrow-in/out. The multiplier/
accumulator, which offers a full 16-bit product,
provides for unsigned, signed, mixed mode and
imaginary number multiplication. Product
accumulation with sum and difference arithmetic is
available in each multiplier operating mode.

11 MCOUT
10 MAC2

35

9 MAC1

RMUX 36
ALUCIN 37

8 MACo
7 TCB

ALU338
ALU239

6 TCA

ALU1 40

4 MIRCLK
3 ACLK

5 AIRCLK

ALUo 41

AAAMUX 42

2 MCLK
1 DCLK

MUXD143
MUXDo 44

84 MUXAl
83 MUXAo

0745
D.46

82 A7

Os 47

~

D.48
0349
0250
0151

~

00"

MUXC153

The 16-bit results of the ALU and
multiplier/accumulator are multiplexed to a single
set of 3-state output buffers. The two ALU and
multiplier/accumulator carry-out bits, as well as the
4-bit status field indicating ALU and
multiplier/accumulator error conditions make up
the remaining six bits of the entire 22-bit output.

•
•
•

•

•

•
•

80 As
79 A4

78 A3
77 A2

76 A1

~

75 AO

Pin Assignment
for PCC

L
•
•
•
•

81 A6

84-Pin PCC, CPGA
Outputs Source/Sink 8 mA
'ACT70S has TTL-Compatible Inputs
High Throughput Achieved with High Degree of
Parallelism in the Architecture
Pipelined Stages
High-Speed 16-Bit ALU and an 8 x 8 Complex
Multiplier
31.0 ns (Typical at 2SoC, S_O V) Cycle 16-Bit Full
ALU Performs Sixteen Boolean and Arithmetic
Functions with Carry·ln and Carry·Out
SO.O ns (Typical at 2SoC, S.O V) Cycle 8 x 8
Parallel Multiplier Supports Unsigned, Signed,
Complex or Mixed Mode Multiplications,
Produces 16·Bit Result with Carry·Out
Separate Data and Instruction Busses Allow
Instruction Fetches in Parallel with Execution Single Cycle Operation
Accepts 8· or 16·Bit Data and Delivers a 16·Bit
Output
Data Register Bank Configured to Accept a
Combination of 8· or 16·Bit Data

K
J
H
G

F
E

0
C

B
A

•••••••••••
•••••••••••
••
••
• •• ••
••
•••
• ••
•••
•••
•••
•••
•• ••• ••
•••
••
•••••••••••
•••••••••••
1 2 3 4 5 6 7 8 9 10 11
Pin Assignment
for CPGA

• Separate Clocks for ALU Instruction, Multiplier
Instruction, Data, ALU Accumulator and Multiplier
Accumulator Registers
• Clustered Clock Pins for Ease of Board Design
• 16·Bit ALUlAccumulator with Feedback to ALU
Input
• Status of Accumulator Inputs is Monitored:
Conditions Monitored Include Twos Complement
Overflow, Underflow or Equal·to·Zero
5-284

AC705 • ACT705
Applications

Pin Names

• Voice· Band Signal Processjng
• Discrete Fourier Transform Applications:
FIR Filters
IIR Filters
• Fast Fourier Transform Applications:
Spectrum Analysis
Speech Recognition

A7 - Ao
B7 - Bo
C7 - Co
07 - Do
DCLK
AIRCLK
MIRCLK

Data Inputs
Data Inputs
Data Inputs
Data Inputs
Data Register Clock
ALU Instruction Register Clock
Multiplier Instruction Register
Clock
ACLK
ALU Accumulator Register Clock
MCLK
Multiplier Accumulator Clock
TCA,TCB
Multiplier Opcode Input
ALU3 - ALUo
ALU Opcode Input
MAC2 - MACo
Multiplier Opcode Input
MUXAl - MUXDo Data Configuration Field Inputs
Multiplier Accumulator Path
AAAMUX
Enable Input
ALUCIN
ALU Carry-ln/Borrow-Out Input
Multiplexing Input
RMUX
Output Enable Input
OE
Result Output
R15 - Ro
MCOUT, ACOUT Carry-Out Outputs
MZ, ME, AZ, AE Error Status Flag O~tPuts

Ordering Code: See Section 6
Logic Symbol

DCLK
AIRCLK
MIRCLK
ACLK
MCLK
TCA
TCB
DE _

Block Diagram
DATA INPUTS (A, B, C, D)
32

DATA
CONFIGURATION
FIELD

INTERNAL BUS J

8

~MUX--------------------4---~-------+~
ALUCIN

MIRCLK

,.

c:~~=J-_t---------------ACLK
,.

MCLK-------------------L,-~~-,J

RMUX--------------------+---------~

OE--------------------+-----------~
AlD==AlU INSTRUCTION DECODE

MZ.ME,MCOUT

R15 . 0

5-285

AZ,AE,ACOUT

MID=MULTIPLIER INSTRUCTION DECODE

•

AC705 • ACT705
Functional Description
On-Chip Registers

3. Accumulator
15

1. Data

o
RAO

7

0
I+--A7.0

RA

1

7
1

Rs

0
I+--B7-0

Rc

0
I+--C7-0

RD

0
1+--07.0

7
1

7
1

Multiplier Accumulator

Status

RAI

I+-- ALUCIN, ALU3·0

0
RMI

16

...
I_----'-R.;;..;A..:;..O_ _ _......I - - . AZ, AE, ACOUT

0

4
1

o
RMO

4. Flags and Carry-Out
18

2. Instruction
4
1

ALU Accumulator

15

18

I+-- MAC2-0, TCB, TCA

16

1 _----'--R.:.:..;;M:.::,O_ _ _......I
...

- - . MZ, ME, MCOUT

Signal Descriptions
Data Inputs
ALUCIN, A7 - Ao, B7 - Bo, C7 - Co, 07 - Do: Data inputs.
Input Clocks
DCLK, AIRCLK, MIRCLK: Input data is loaded on the rising edge of these clocks.
Outputs
R15 - Ro: Result
MCOUT: Multiplier/Accumulator Carry-Out
ACOUT: ALU Carry-Out
MZ, ME, AZ, AE: Error Status Flags
Output Clocks
ACLK, MCLK: Output data is loaded into the output register on the rising edge of this clock.
Other Signals
ALU3 - ALUo: ALU Instruction Input
MAC2 - MACo, TCA, TCB: Multiplier Instruction Input
MUXAo, A1, Bo, B1, Co, C1, Do, 01: Multiplexer Select Signals for Input Data

Control Signals
Clock Signals
Dedicated signals for controlling the five sets of positive edge-triggered on-chip registers.
DCLK: Data Registers (RA, Rs, Rc, RD)
.
AIRCLK: ALU Instruction Register (RAI)
MIRCLK: Multiplier Instruction Register (RMI)
ACLK: ALU Accumulator Register (RAO)
MCLK: Multiplier/Accumulator Register (RMO)
5-286

AC705 • ACT705
Control Signals, cont'd
ALUCIN
Clocked ALU Carry-In/Borrow-Out Signal.
1 - Carry-In to ALU
o - Borrow from ALU
MUXA1, MUXAo ___ MUXDo (Data Configuration Field, see Table A)
Level signals for configuring the ALU and multiplier operands in 256 possible ways with the contents of RA,
RB, Rc, RD.
MUXA1, MUXAo: Control the state of internal bus J7 - Jo
MUXB1, MUXBo: Control the state of internal bus K7 - Ko
MUXC1, MUXCo: Control the state of internal bus L7 - Lo
MUXD1, MUXDo: Control the state of internal bus M7 - Mo
AAAMUX
Level signal for enabling/disabling the 16-bit multiplier/accumulator path to the ALU.
o - Path enabled. ALU takes operand from RMO.
1 - Path disabled. ALU takes operand from internal buses J7 - Jo and K7 - Ko.
ALU3 - ALUo
Clocked ALU opcode. See Table B.

•

MAC2 - MACo, TCB, TCA
Clocked multiplier opcode. See Table C.
RMUX
Level signal for multiplexing the contents of RMO and RAO.
o - Output RM015 - RMOO
1 - Output RA015 - RAOO
OE
Active LOW Enable signal for making available the 16-bit result, R15 - Ro.

Instruction Format

,.

11 10 9

.5

~L".",,_,
MULTIPLIER OPCODE (Clocked)
5: MAC2
4: MAC1
3: MACo

2: Tee
1: TCA

' - - - - - - - - A L U OPCODE (Clocked)
9: ALU3
8: ALU2

7: ALU,
6: ALUo

L - - - - - - - - - - A A A M U X (Level)

L....._ _ _ _ _ _ _ _ _ DATA CONFIGURATION FIELD (Level)
18:
17:
16:
15:
14:
13:
12:
11:

5-287

MUXA1
MUXAO
MUXB1
MUXBO
MUXC1
MUXCO
MUXD1
MUXDO

AC705 • ACT705
Table A: Data Input Configuration
Data Configuration Field
MUXAI MUXAo

0
0

0

1
1

0

MUXBl MUXBo

Internal Buses

MUXCI MUXCo

MUXDI MUXDo

J7 - Jo

RA7
RB7
RC7
R07

1
1

0
0

0

1
1

0

-

RA7
RB7
RC7
R07

1

0

1
1

0

-

RAO
RBO
Rco
Roo
RA7
RB7
RC7
RD7

1
1

0
0

0

1
1

0

M7 - Mo

RAO
RBO
Rco
Roo

1

0
0

L7 - Lo

K7 - Ko

-

RAO
RBO
Rco
Roo
RA7
RB7
RC7
R07

1
1

-

RAO
RBO
Rco
RDO

Table B: Arithmetic and Logic Operations
Signal
MACo

TCB

TCA

X
X

X
X

X
X

X
X

X

X

X

X

X

1

X

X

X

X

X

0

0

X

X

X

X

X

1

0

1

X

X

X

X

X

0

1

1

0

X

X

X

X

X

0

0

1

1

1

X

X

X

X

X

X
0

1
1

0
0

0
0

0
1

X
X

X
X

X
X

X
X

X
X

0

1

0

1

0

X

X

X

X

X

0

1

0

1

1

X

X

X

X

X

AAAMUX

ALU3

ALU2

ALU1

ALUo

MAC2 MAC1

X
0

0
0

0
0

0
0

0
1

X
X

0

0

0

1

0

0

0

0

1

0

0

1

0

0

0

5-288

Function
Clear ALU Output
(Ls - Lo II Ms - Mo) minus
RM016 - RMOO
RM016 - RMOO minus
(Ls - Lo II Ms - Mo)
RM016 - RMOO plus
(Ls - Lo II Ms - Mo)
RM016 - RMOO XOR
(Ls - Lo II Ms - Mo)
RM016 - RMOO OR
(Ls - Lo II Ms - Mo)
RM016 - RMOO AND
(Ls - Lo II Ms - Mo)
RM016 - RMOO plus
{O}16-0
Preset ALU Output
RA016 - RAOO minus
RM016 - RMOO
RM016 - RMOO minus
RA016 - RAOO
RM016 - RMOO plus
RA016 - RAOO

AC705 • ACT705
Table B: Arithmetic and Logic Operations, cont'd
Signal
AAAMUX

ALU3

ALU2

ALU1

ALUo

MAC2

MAC1

MACo

TCB

BCA

0

1

1

0

0

X

X

X

X

X

0

1

1

0

1

X

X

X

X

X

0

1

1

1

0

X

X

X

X

X

0

1

1

1

1

X

X

X

X

X

1

0

0

0

1

X

X

X

X

X

1

0

0

1

0

X

X

X

X

X

1

0

0

1

1

X

X

X

X

X

1

0

1

0

0

X

X

X

X

X

1

0

1

0

1

X

X

X

X

X

1

0

1

1

0

X

X

X

X

X

1

0

1

1

1

X

X

X

X

X

1

1

0

0

1

X

X

X

X

X

1

1

0

1

0

X

X

X

X

X

1

1

0

1

1

X

X

X

X

X

1

1

1

0

0

X

X

X

X

X

1

1

1

0

1

X

X

X

X

X

1

1

1

1

0

X

X

X

X

X

1

1

1

1

1

X

X

X

X

X

Note: Combination of ALU and multiplier opcodes allowed.

5-289

Function

RM016 - RMOO XOR
RA016 - RAOO
RM016 - RMOO OR
RA016 - RAOO
RM016 - RMOO AND
RA016 - RAOO
RM016 - RMOO XOR
(0)16-0
(La - Lo II Ma - Mo) minus
(Ja - Jo II Ka - Ko)
(Ja - Jo II Ka - Ko) minus
(La - Lo II Ma - Mo)
(Ja - Jo II Ka - Ko) plus
(La - Lo II Ma - Mo)
(Ja - Jo II Ka - Kci ) XOR
(La - Lo II Ma - Mo)
(Ja - Jo II Ka - Ko) OR
(La - Lo II Ma - Mo)
(Ja - Jo II Ka -Ko) AND
(La - Lo II Ma - Mo)
(Ja - Jo II Ka - Ko) plus
(0)16-0
RA016 - RAOO minus
(Ja - Jo II Ka - Ko)
(Ja - Jo II Ka - Ko) minus
RA016 - RAOO
(Ja - Jo II Ka - Ko) plus
RA016 - RAOO
(Ja - Jo II Ka - Ko) XOR
RA016 - RAOO
(Ja - Jo II Ka - Ko) OR
RA016 - RAOO
(Ja - Jo II Ka - Ko) AND
RA016 - RAOO
(Ja - Jo II Ka - Ko) XOR
(0)16-0

•

AC705 • ACT705
Table C: Multiplication Operations
Signal
Function

AAAMUX

ALU3

ALU2

ALU1

ALUo

MAC2

MAC1

MACo

TCB

TCA

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

0
0
0
0

0
0
0
0

0
0
0
0

0
0

0

1
1

0
1

(Js - Jo x Ks . Ko)
(J's . J'o X Ks . Ko)
(Js . Jo x K's . K'o)
(J's . J'o x K's· K'o)

X

X

X

X

X

0

0

1

0

0

(Js . Jo x Ks . Ko) plus

X

X

X

X

X

0

0

1

0

1

(J's . J'o x Ks· Ko) plus

X

X

X

X

X

0

0

1

1

0

(Js . Jo x K's . K'o) plus

X

X

X

X

X

0

0

1

1

1

(J's . J'o x K's· K'o)
plus RMO'16 . RMO'O

X

X

X

X

X

0

1

0

X

X

Clear

X
X

X
X

X
X

X
X

X
X

0
0

1
1

1
1

0
0

0

X

X

X

X

X

0

1

1

1

0

X

X

X

X

X

0

1

1

1

1

Undefined
(J's - J'o X Ks . Ko)
minus RMO'16 • RMO'O)
(Js - Jo x K's . K'o)
minus RMO'16 . RMO'O
(J's· J'o x K's· K'o)
minus RMO'16 • RMO'O

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

1
1
1
1

0
0
0
0

0
0
0
0

0
0

0

1
1

0

X
X

X
X

X
X

X
X

X
X

1
1

0
0

1
1

0
0

0

X

X

X

X

X

1

0

1

1

0

X

X

X

X

X

1

0

1

1

1

X

X

X

X

X

1

1

0

X

X

Preset

X
X

X
X

X
X

X
X

X
X

1
1

1
1

1
1

0
0

0

X

X

X

X

X

1

1

1

1

0

X

X

X

X

X

1

1

1

1

1

Undefined
(-J's· J'o x Ks· Ko)
minus RMO'16 • RMO'O
(-Js . Jo x K's . K'o)
minus RMO'16 • RMO'O
(-J's· J'o x K's· K'o)
minus RMO'16 • RMO'O

1

RMO'16 . RMO'O
RMO'16 . RMO'O)
RMO'16 • RMO'O

Notes: Combination of ALU and multiplier opcodes allowed.
, stands for twos complement representation of a number.

5·290

1

1
1
1

1

RM016 • RMOO

Undefined
(-J's· J'o x Ks· Ko)
(-Js . Jo x K's . K'o)
(-J's . J'o X K's . K'o)
Undefined
(-J'8 . J'o X Ks . Ko)
plus RMO'16 • RMO'O
(-Js . Jo x K's . K'o)
plus RMO'16 . RMO'O
(-J's· J'o x K's . K'o)
plus RMO'16 . RMO'O
RM016 • RMOO

AC705 • ACT705
DC Characteristics over Operating Temperature Range (unless otherwise specified)
74AC/ACT
Symbol

25°C

Parameter

54AC/ACT

74AC/ACT
Units

Conditions

Guaranteed Limit

Typ
liN

Maximum Input Current

0.1

10.0

1.0

p.A

Vcc=Max
VIN=VCC

loz

Maximum 3-State Current

0.5

10.0

5.0

p.A

High Z, Vcc = Max
VOUT = 0 to Vcc

ICCQ

Supply Current, Quiescent

50.0

2.0

10.0

10.0

rnA

VCC = Max, VIN =0 V

4.49

4.4

4.4

4.4

V

VIN = VIL or VIH
IOUT=20 p.A,
Vcc=4.5 V

5.49

5.4

5.4

5.4

V

VIN = VIL or VIH
lOUT = 20 p.A,
Vcc=5.5 V

3.86

3.70

3.76

V

IOH= -8 rnA,
Vcc=4.5 V

4.86

4.70

4.76

V

10H= -8 rnA,
Vcc=5.5 V

0.001

0.1

0.1

0.1

V

VIN = VIL or VIH
IOUT=20 p.A,
Vcc=4.5 V

0.001

0.1

0.1

0.1

V

VIN = VIL or VIH
lOUT = 20 p.A,
Vcc=5.5 V

0.32

0.4

0.37

V

IOL=8 rnA, Vcc=4.5 V

0.32

0.4

0.37

V

IOL=8 rnA, Vcc=5.5 V

VOH

VOL

Minimum HIGH Level Output

Maximum HIGH Level Output

10LD

Minimum Dynamic Output
Current

32

32

rnA

Vcc=5.5 V
VOLD=2.2 V

IOHD

Minimum Dynamic Output
Current

-32

-32

rnA

Vcc=5.5 V
VOHD=3.3 V

Note 1: Test Load 50 pF, 500 ohm to Ground

5-291

•

AC705

• ACT705

AC Characteristics

Vee·
(V)

Symbol

74AC

54AC

74AC

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Min

tA

Typ

31.0

tL

Max

Max

Units

Fig.
No.

Max

ns
ns

tM

Multiply Time

ns

2

to

Output Delay

ns

1,2

tENA

3·State Output
Enable Delay

3.3
5.0

ns

1,2

tOIS

3·State Output
Disable Delay

3.3
5.0

8.5

1,2

ts

Input Register
Setup Time

3.3
5.0

3.0

1,2

th

Input Register
Hold Time

3.3
5.0

0

1,2

tw

Cloek Pulse Width

3.3
5.0

5.0

ns

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·292

1,2

AC705

• ACT705

AC Characteristics

Vcc'
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Min
tA

Typ
31.0

tL

Max

Max

Units

Fig.

No.

Max
ns
ns

tM

Multiply Time

ns

2

tD

Output Delay

ns

1,2

tENA

3-State Output
Enable Delay

ns

1,2

tDIS

3-State Output
Disable Delay

5.0

ns

1,2

ts

Input Register
Setup Time

5.0

3.0

1,2

th

Input Register
Hold Time

5.0

0

1,2

tw

Clock Pulse Width

5.0

5.0

ns

'Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-293

1,2

•

AC705 • ACT705
Waveforms
Figure 2: Multiplication

Figure 1: Arithmetic Logic Operation
A7- 0
C7-0
87- 0
07·

AWCIN

A7·0
87·0
C7·0
07" 0
ALUCIN

m~=~mmmm.ml

MAC2·0

CONFIGURfT~6~
FIELD
AAAMUX

TeB
TeA

1.,------...1"'''''''''

..."."....

""'F""r'-----'TIIl<""'''

DeLK
MIRCLK

DCLK
AIRCLK

AeL.

RMUX

DE

m=

,......,.
m
--

-

v-----

---'

r\

MCLK

-+--+-+---'1

i ••e$emmr-----

RMUX

-r--r--t------r----__I

R15.0 _ _ _

U~

R15·0

I--=- -=-

to
tA or tL

1

Ih=O

th=O

5-294

lENA

•

I--"""---

AC705 • ACT705
CPGA Pinout
Signal to Pinout

Pinout to Signal
Pinout

Signal

Pinout

Signal

Signal

Ai
A2
A3

MCOUT
MAC1
MACo
TCA
ACLK
MCLK
MUXAo
A5
A3
A2
MUXB1
Ro
MZ
MAC2
TCB
MIRCLK
A6
A7
A4
A1
Ao
B7
R1
ME
NO
CONNECTION
AIRCLK
OCLK
MUXA1
MUXBo
B6
R3
R2
B5
B4
R6
R5
R4
B3
B2
B1
R10
R7

F3
F9
F10
F11
G1
G2
G3
G9
G10
G11
Hi
H2
H10
H11
J1
J2
J5
J6
J7
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
Li0
L11

GN02
VCC1
C2
Bo
Rs
R9
VCC2
GN01
C1
Co
R11
R12
C4
C3
R13
R15
ALU2
MUX01
MUXOo
C7
C5
R14
AE
ACOUT
ALUCIN
ALU1
AAAMUX
06
03
Do
MUXCo
C6
AZ
OE
RMUX
ALU3
ALUo
05
07
04
02
01
MUXC1

MZ
B2
ME
C2
B1
Ro
R1
C1
R2
02
R3
01
R4
E3
R5
E2
E1
R6
R7
F2
GN02
F3
VCC2
G3
G1
Rs
R9
G2
F1
RlO
R11
Hi
R12
H2
R13
J1
R14
K1
R15
J2
AZ
L1
AE
K2
ACOUT K3
OE
L2
RMUX L3
ALUCIN K4
ALU3
L4
ALU2
J5
ALU1
K5
ALUo
L5
AAAMUX K6
MUX01 J6
MUXOo J7
07
L7
K7
06
05
L6
04
L8
03
K8
02
L9
01
L10
Do
K9
MUXC1 L11

A4

A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C1
C2
C3
C5
C6
C7
C10
C11
01
02
010
011
E1
E2
E3
E9
Ei0
E11
F1
F2

5-295

Pinout

Signal

Pinout

MUXCo
C7
C6
C5
C4
C3
C2
C1
Co
GN01
VCC1
Bo
B1
B2
B3
B4
B5
B6
B7
MUXBo
MUXB1
Ao
A1
A2
A3
A4
A5
A6
A7
MUXAo
MUXA1
OCLK
MCLK
ACLK
MIRCLK
AIRCLK
TCA
TCB
MACo
MAC1
MAC2
MCOUT

K10
J10
K11
J11
H10
H11
F10
G10
G11
G9
F9
F11
E11
E10
E9
011
010
C11
B11
C10
A11
B10
B9
A10
A9
B8
A8
B6
B7
A7
C7
C6
A6
A5
B5
C5
A4

B4
A3
A2
B3
Ai

II

AC708 • ACT708
54AC/74AC708 • 54ACT/74ACT708
64 x 9 First-In, First-Out Memory
Connection Diagrams

Description
The 'ACI'ACT708 is an expandable first-in, first-out
memory organized as 64 words by 9 bits. An 85
MHz shift-in and 60 MHz shift-out data rate make it
ideal for high-speed applications. It uses a dual
port RAM architecture with pointer logic to achieve
the high speed with almost negligible fall-through
time.
Separate Shift-In (SI) and Shift-Out (SO) clocks
control the use of synchronous or asynchronous
write or read. Other controls include a Master
Reset (MR) and Output Enable (OE) for initializing
the internal registers and allowing the data outputs
to be 3-stated. Input Ready (IR) and Output Ready
(OR) signal when the FIFO is ready for 1/0
operations. The status flags HF and FULL indicate
when the FIFO is full, empty or half full.

Pin Assignment
for DIP and Flatpak

The FIFO can be expanded to increase the depth
by cascading or to provide different word lengths
by tying off unused data inputs.

06

• 64-Words by 9-Bit Dual Port RAM Organization.
• 85 MHz Shift-In, 60 MHz Shift-Out Data Rate with
Flags, Typical 'ACT708
• Expandable in Word Depth and Width Dimensions
• 'ACT708 has TTL-Compatible Inputs
• Asychronous or Synchronous Operation
• Asynchronous Master Reset
• Outputs Source/Sink 8 mA
• 3-State Outputs
• Full ESD Protection
• Output and Input Pins Directly in Line for Easy
Board Layout
• TRW 1030 Work-Alike Operation Available

Ds

04

03

02

01

Do

1Dl~~~I.?J~~
~~

OO~

D,1i]

W'R

GND

I!4J

[]] HF

DE

B]

[i] FULL

08

B]

~vcc

lli~

~D

llil!4J

~w

1!4J[2O]~~~~[2O]
Q,;
06 Q3 02 0, 00 OR

Pin Assignment
for LCC and PCC

Applications
•
•
•
•
•

High-Speed Disk or Tape Controllers
A/D Output Buffers
High-Speed Graphics Pixel Buffer
Video Time Base Correction
Digital Filtering

Ordering Code: See Section 6

5-296

AC708 • ACT708
Logic Symbol

Pin Names

IR

MR

Data Inputs
Master Reset
Output Enable Input
Shift-In
Shift-Out
Input Ready
Output Ready
Half Full Flag
Full Flag
Data Outputs

Do - 08
MR
OE
SI
SO
IR
OR
HF

OR

Sl

FULL

SO

00 - 08
OE

Block Diagram
DO 008
.... 1--9

J
SI

I

SO MR

INPUT REGISTER

.... 1--9

j

:--...I

r--

0

a:

..

IR

l-

CONTROL
LOGIC

Z
0

f---

a:

r---

0

OR

w

I-

-

64 x 9

DUAL PORT
RAM ARRAY

Z

(5
Q.

-

9

·1 OUTPUT REGISTER

FLAG LOGIC

.... 1--9
HF

FULL
OE

\

/13oSTATE
BUFFER
..... 1--9

07 08
0

5-297

•

AC708 • ACT708
Functional Description
Inputs
Data Inputs (Do - Os)
Data inputs for 9-bit wide data are TTL-compatible
(,ACT708). Word width can be reduced by tying
unused inputs to ground and leaving the
corresponding outputs open.

Outputs
Data Outputs (00 - Os)
Data outputs are enabled when OE is LOW and in
the 3-state condition when OE is HIGH.
Input Ready (IR)
IR HIGH indicates data can be shifted-in. When SI
goes HIGH, IR goes LOW, indicating input stage is
busy. IR stays LOW when the FIFO is full and goes
HIGH after the falling edge of the first shift-out.

Reset (MR)
Reset is accomplished by pulsing the MR input
LOW. During normal operation MR is HIGH. A reset
is required after power up to guarantee correct
operation. On reset, the data outputs go LOW, IR
goes HIGH, OR goes LOW, HF and FULL go LOW.
During reset, both internal read and write pointers
are set to the first location in the array.

Output Ready (OR)
OR HIGH indicates data can be shifted-out from
the FIFO. When SO goes HIGH, OR goes LOW,
indicating output stage is busy. OR is LOW when
the FIFO is reset or empty and goes HIGH after
the falling edge of the first shift-in.

Shift-In (SI)
Data is written into the FIFO by pulsing SI HIGH.
When Shift-In goes HIGH, the data is loaded into
an internal data latch. Data setup and hold times
need to be adhered to with respect to the falling
edge of SI. The write cycle is complete after the
falling edge of SI. The shift-in is independent of
any ongoing shift-out operation. After the first
word has been written into the FIFO, the falling
edge of SI makes HF go HIGH, indicating a nonempty FIFO. The first data word appears at the
output after the falling edge of SI. After half the
memory is filled, the next rising edge of SI makes
FULL go HIGH indicating a half-full FIFO. When
the FIFO is full, any further shift-ins are disabled.

Half-Full (HF)
This status flag along with the FULL status flag
indicates the degree of fullness of the FIFO. On
reset, HF is LOW; it rises on the falling edge of
the first SI. The rising edge of the SI pulse that
fills up the FIFO makes HF go LOW. Going from
the empty to the full state with SO LOW, the
falling edge of the first SI causes HF to go HIGH,
the rising edge of the 33rd SI causes FULL to go
HIGH, and the rising edge of the 64th SI causes
HF to go LOW.
When the FIFO is full, HF is LOW and the falling
edge of the first shift-out causes HF to go HIGH
indicating a "non-full" FIFO.

When the FIFO is empty and OE is LOW, the falling
edge of the first SI will cause the first data word
just shifted-in to appear at the output, even though
SO may be LOW.

Full Flag (FULL)
This status flag along with the HF status flag
indicates the degree of fullness of the FIFO. On
reset, FULL is LOW. When half the memory is
filled, on the rising edge of the next SI, the FULL
flag goes HIGH. It remains set until the difference
between the write pointer and the read pointer is
less than or equal to one-half of the total memory
of the device. The FULL flag then goes LOW on
the rising edge of the next SO.

Shift-Out (SO)
Data is read from the FIFO by the Shift-Out signal
provided the FIFO is not empty. SO going HIGH
causes OR to go LOW indicating that output stage
is busy. On the falling edge of SO, new data
reaches the output after propagation delay tD. If
the last data has been shifted-out of the memory,
OR continues to remain LOW, and the last word
shifted-out remains on the output pins.

Status Flags Truth Table

Output Enable (OE)
OE LOW enables the 3-state output buffers. When
OE is HIGH, the outputs are in a 3-state mode.

5-298

HF

FULL

0
0

0
1
0

Status Flag Conditions
Empty
Full
<32 Locations Filled
~32 Locations Filled

AC708 • ACT708
Reset Truth Table
Inputs
MR

SI

SO

IR

OR

HF

1

x

X

X

X

X

X

X

o

3. Input Ready (IR) goes LOW propagation delay tlR
after SI goes HIGH: input stage is busy.

Outputs

o

FULL 00 - Os

X

o

o

4. Shift-In is set LOW; IR goes HIGH indicating the
FIFO is ready for additional data. Data just
shifted-in arrives at output propagation delay
t005 after SI falls. OR goes HIGH propagation
delay tlOR after SI goes LOW, indicating the FIFO
has valid data on its outputs. HF goes HIGH
propagation delay tiE after SI falls, indicating the
FIFO is no longer empty.

x

o

Modes of Operation
Mode 1: Shift In Sequence for FIFO Empty to Full
Sequence of Operation
1. Input Ready is initially HIGH; HF and FULL flags
are LOW. The FIFO is empty and prepared for
valid data. OR is LOW indicating that the FIFO is
not yet ready to output data.

5. The process is repeated through the 64th data
word. On the rising edge of the 33rd SI, FULL
flag goes HIGH propagation delay tlHF after SI,
indicating a half-full FIFO. HF goes LOW
propagation delay tlF after the rising edge of the
64th pulse indicating that the FIFO is full. Any
further shift-ins are disabled.

2. Shift-In is set HIGH, and data is loaded into the
FIFO. Data has to be settled ts before the falling
edge of SI and held th after.

•

Figure 1: Modes of Operation
Mode 1
1st PULSE

SI
IR

-~}-

DO - 08

+_---------

------I)j~(

FULL
___ tlE--

r---------------~)~(------~--------I
HF

--- ,tlOR

Ir-----------------~I~(------+---------~/~(~----------

OR

00 - 08

----------+-~r---------------~).~(------+---------~i~(+---------1st DATA WORD

__________~-J ~--------------_{/I~-----r--------~£~(+----------

Note: SO and OE are LOW; 1iifR is HIGH.

5-299

AC708 • ACT708
Mode 2: Master Reset
4. IR rises (if not HIGH already) to indicate ready
to write state recovery time tMRIRH after the
falling edge of MR. Both HF and FULL will go
LOW indicating an empty FIFO, occurring
recovery times tMRE and tMRO respectively after
the falling edge of MR. OR falls recovery time
tMRORL after MR falls. Data at outputs goes LOW
recover time tMRONL after MR goes LOW.

Sequence of Operation
1. In put and Output Ready, H F and FU LL can be in
any state before the reset sequence with Master
Reset (MR) HIGH.
2. Master Reset goes LOW and clears the FIFO,
setting up all essential internal states. Master
Reset must be LOW pulse width tMRW before
rising again.

5. Shift·ln goes HIGH a minimum of recovery time
tMRSIH after MR goes HIGH.

3. Master Reset rises.

Figure 2: Modes of Operation
Mode 2
tMRW

,

..

-tMRSIH

I

'tMRIRH

,

\'

IR

.

,

tMRORL

OR

J~

SO

,

tMRE

HF

''--)

FULL

.

tMRO

\
J\

00·8

..

tMRONL

I

51

J

5·300

AC708 • ACT708
Mode 3: With FIFO Full, Shift·ln is Held HIGH in Anticipation of an Empty Location
Sequence of Operation
1. The FIFO is initially full and Shift-In goes HIGH.
OR is initially HIGH. Shift-Out is LOW. IR is
LOW.

HIGH tOF after SO falls, indicating that the FIFO
is no longer full.
4. IR returns LOW pulse width tiP after rising and
shifting fresh data in. Also, HF returns LOW
pulse width t3F after rising, indicating the FIFO
is once more full.

2. Shift-Out is pulsed HIGH, Shift-Out pulse
propagates and the first data word is latched on
the rising edge of SO. OR falls on this edge. On
the falling edge of SO, the second data word
appears after propagation delay to. New data is
written into the FIFO after SO goes LOW.

5. Shift-In is brought LOW to complete the shift-in
process and maintain normal operation.

3. Input Ready goes HIGH fall-through time tFT
after the falling edge of SO. Also, HF goes

Figure 3: Modes of Operation
Mode 3

•

SO

51
tFT-ptIP-1
IR
OR

HF

00·08

----------------~.
\--_--1
FULL

FULL

______________~x~________~x~____

00 - 08 _____________
1s_t_W
__
0_R_O__________

Note:

MR and

~------------

FULL are HIGH; OE is LOW.

5-301

-J)(~________2_n_d_W_0__R_O___________

AC708 • ACT708
Mode 4: Shift·Out Sequence, FIFO Full to Empty
Sequence of Operation
1. FIFO is initially full and OR is HIGH, indicating
valid data is at the output. IR is Law.

4. Repeat process through the 64th SO pulse.
FULL flag goes LOW propagation delay tOHF after
the rising edge of 33rd SO, indicating that the
FIFO is less than half full. On the falling edge of
the 64th SO, HF goes LOW propagation delay tOE
after SO, indicating the FIFO is empty. The SO
pulse may rise and fall again with an attempt to
unload an empty FIFO. This results in no change
in the data on the outputs as the 64th word
stays latched.

2. SO goes HIGH, resulting in OR going LOW
propagation delay tOR after SO rises. OR LOW
indicates output stage is busy.
3. SO goes LOW, new data reaches output
propagation delay tD after SO falls; OR goes
HIGH propagation delay tOR after SO falls and
HF rises propagation delay tOF after SO falls. IR
rises fall-through time tFT after SO falls.

Figure 4: Modes of Operation
Mode 4
33rd PULSE

~

64th PULSE

so
OR

IR--+--+J

00 - 08
FULL--~---~----~f-----~

~

t::_O_F____

~~----------4_------~~----------------_k

HF---+----_+_'

Note: 81 and

OE are LOW; MR is HIGH; Do - 08 are immaterial.

5-302

AC708 • ACT708
Mode 5: With FIFO Empty, Shift·Out is Held HIGH in Anticipation of Data
Sequence of Operation
1. FIFO is initially empty; Shift·Out goes HIGH.

4. Data arrives at output propagation delay tOD5
after the falling edge of Shift·ln.

2. Shift·ln pulse loads data into the FIFO and IR
falls. HF rises propagation delay tXl after the
falling edge of SI.

5. OR goes LOW pulse width top after rising and
HF goes LOW pulse width tX3 after rising,
indicating that the FIFO is empty once more.

3. OR rises fall·through time tFTO after the falling
edge of Shift-In, indicating that new data is
ready to be output.

6. Shift-Out goes LOW, necessary to complete the
Shift-Out process.

Figure 5: Modes of Operation
Mode 5

1\

SI

SO

•

ti~top-j

OR
IR
tOD5

~

DO - 08

" NEW DATA
J\.

/

00·08

HF

"-

NEW DATA

1\

J

EMPTY

~tx1-

EMPTY

i"- tx3-

Note: FULL is LOW; MR is HIGH; OE is LOW; tOOF= tFTO - t005. Data output transition-valid data arrives at output stage
tOOF after OR is HIGH.

5-303

AC708 • ACT708
Mode 6: Shift·ln Operation in High·Speed Burst Mode
Sequence of Operation
1. Shift·ln goes HIGH, loading data into the FIFO.
IR is ignored.

3. Shift-In rises again for the second load pulse
width tLOW after the falling edge.
The burst-in rate is determined by SI HIGH and
LOW. Data is shifted-in, ignoring the IR flag. Any SI
after the FIFO is filled up will be ignored.

2. Shift-in goes LOW pulse width tHIGH time later,
loading is complete.

Figure 6: Modes of Operation
Mode 6

(~---')>------cc
Note: MR is HIGH; tHIGH >tSIH; tLOW>tSIL; tHIGH

+ tLOW;;:; 1/1BI.

Mode 7: Shift·Out Operation in High Speed Burst Mode
Sequence of Operation
1. Shift-Out is LOW; valid data is available on
output with OR ignored.

3. Shift-Out falls; new data is loaded onto output.

The Burst-out rate is determined by minimum SO
HIGH and LOW. The OR flag is ignored.

2. Shift-Out rises; data out is latched.

Figure 7: Modes of Operation
Mode 7

SO

00·08

1st DATA WORD

2nd DATA WORD

to

Note: OE is LOW; MR is HIGH; tHIGH>tSOH; tLOW>tSOL; tHIGH + tLow;;:;1/IBO.

5-304

AC708 • ACT708
FIFO Expansion
Word Width Expansion
Word width can be increased by connecting the
corresponding input control signals of multiple
devices. Flags can be monitored on anyone device
(Figure 8), or composite flag signals can be
achieved by ANDing the corresponding flags.

IR(n)-SO(n-1); IR(n-1)-SO(n-2) ... IR(2)-SO(1). The
OR signal from each FIFO is connected to its
succeeding SI signal: i.e., OR(1)-SI(2); OR(2)-SI(3)
... OR(n-1)-SI(n). Handshaking signals are shown
in Figure 10.
FIF01 operates in Mode 5 during Shift-In until
FIF02 is filled. FIF02 operates in Mode 3 during
Shift-Out until FIF01 is empty. Data from FIF01 is
written into FIF02 after a word is read from FIF02.
To achieve this, the OE pin is grounded for FIF01.
In general, for n FIFOs, all OE pins except the nth
FIFO's OE pin are enabled. 3-state control of the
outputs can be achieved by controlling the nth
FIFO's OE pin.

Depth Expansion
Depth Expansion can be achieved by connecting as
shown in Figure 9. No external circuitry is required
for handshaking, which is achieved by the internal
FIFO signals IR and OR.
When n FIFOs are cascaded to attain a 64n-word
FIFO, the SI signal is connected to the first FIFO
and the SO Signal to the nth FIFO. The IR and OR
signals are monitored from the first and last FIFOs
respectively. The IR signal from each FIFO is
connected to its preceding SO signal:

Figure 8: Word Width Expansion -

•

64 x 18 FIFO

FULL 1

t

IR 1

FULL

9

DIN (0-8)

9

00·8

00·8

FIF01 IR
so 64 x 9 OR
HF
r - - Sl
OE

r< MR

MR
51
SO -------<

9,

,

COMPOSITE
IR
OR 1 ---r-\
COMPOSITE
OR2~
OR

DOUT (0-8)
IR1
OR1
HF1

0-

HF 1 =D--COMPOSITE
HF 2
HF
FULL 1 ~ COMPOSITE
FULL2~
FULL

---OE
OE

'-< MR
'--

DIN (9-17 )

---r-'\

IR2~

IR
Sl
so FIF02 OR
64 x 9 HF
00·8

00·8

0-

9

IR2
OR2
HF2
DOUT(9-17)

FULL

~

FULL 2
Note: Monitor flags from anyone FIFO, or AND the corresponding flags to obtain a composite signal.

5-305

AC708 • ACT708
Figure 9: Depth Expansion Mode -

128 x 9 FIFO
MR

FULLl

FULL2

HFl

HF2

IR

so

IR

SO

51

OR

51

OR

00

Do

01

D1

Do
01

,....

00
N

02

0

02

02

0

D.
D_

ii:

o.

ii:

U.

U.

01
02

o.

O-

D.
D_

D.

O.

D.

O.

D.

O.
0,

D.
D,

O.
0,

O.

D.

0,

D.

O_

O.
OE

OE

Figure 10: Handshaking for Depth Expansion Mode-128 x 9 FIFO

MR

lJ

51
SO
IR

00·08
00·08
HFl
HF2
FULLl
FULL2
IR2 ; 501

OR1 =

512
FIF02 FULL

FIFOl FULL

FIFOl EMPTY

FIF02 EMPTY

Note: The numbers for SI and SO indicate the pulse numbers. The numbers for data in and data out indicate data words:
1 is first data word, 2 is second data word, etc.

5-306

AC708 • ACT708
DC Characteristics over Operating Temperature Range (unless otherwise specified)

Symbol

Parameter

74AC/ACT
25°C
Typ

54AC/ACT

74AC/ACT
Units

Conditions

Guaranteed Limit

liN

Maximum Input Current

0.1

10.0

1.0

p.A

Vcc = Max
VIN=VCC

loz

Maximum 3-State Current

0.5

10.0

5.0

p.A

High Z, Vcc = Max
VOUT = 0 to Vcc

ICCQ

Supply Current, Quiescent

50.0

2.0

10.0

10.0

mA

Vcc=Max, VIN=O V

ICCD

Supply Current, 20 MHz
Loaded

325

150

150

mA

Vcc = Max, f = 20 MHz
Test Load: See Note 1

VOH

VOL

4.49

4.4

4.4

4.4

V

VIN = VIL or VIH
lOUT = 20 p.A,
Vcc=4.5 V

5.49

5.4

5.4

5.4

V

VIN = VIL or VIH
lOUT = 20 p.A,
Vcc=5.5 V

3.86

3.70

3.76

V

10H= -8 mA,
Vcc=4.5 V

4.86

4.70

4.76

V

10H= -8 mA,
Vcc=5.5 V

0.001

0.1

0.1

0.1

V

VIN = VIL or VIH
lOUT = 20 p.A,
Vcc=4.5 V

0.001

0.1

0.1

0.1

V

VIN = VIL or VIH
lOUT = 20 p.A,
Vcc=5.5 V

0.32

0.4

0.37

V

IOL=8 mA, Vcc=4.5 V

0.32

0.4

0.37

V

IOL=8 mA, Vcc=5.5 V

Minimum HIGH Level Output

Maximum HIGH Level Output

IOLD

Minimum Dynamic Output
Current

32

32

mA

Vcc=5.5 V
VOLD=2.2 V

IOHD

Minimum Dynamic Output
Current

-32

-32

mA

Vcc=5.5 V
VOHD=3.3 V

Note 1: Test Load 50 pF, 500 ohm to Ground

5-307

•

AC708 • ACT708
AC Characteristics

Symbol

Vcc·
(V)

Parameter

74AC

54AC

74AC

TA=+25°C
CL=50 pF

TA=-55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Min

Min
tPLH, tPHl
tPLH

Typ

Max

Max

Units

Fig.
No.

Max

pro~,ay, to,

3.3
5.0

8.5
5.5

ns

1

~~

3.3
5.0

13.0
9.5

ns

1

3.3

13.0
9.5

ns

1

~~ ~

12.5
9.0

ns

1

/),3:0

ns

1

ns

2

ns

2

ns

2

ns

2

SI to

tlHF

SI 0 >H

tPHL

Propagati
SI to Full

tPLH

Propagation De1iY~
SI to Not Empty

tPLH

Propagation Delay, tIOR'"
SI to OR

tPLH

Recovery Time, tMRIRH
MR to IR

tPHL

Recovery Time, tMRORL
MR to OR

3.3
5.0

tPHL

Recovery Time, tMRO
MR to Full Flag

3.3
5.0

9.5
7.0

tPHL

Recovery Time, tMRE
MR to HF Flag

3.3
5.0

20.0
15.0

tPHL

Recovery Time, tMRONL
MR to On, LOW

3.3
5.0

11.0
8.0

tw

IR Pulse Width, tiP

3.3
5.0

38.0
28.0

tw

H F Pulse Width, t3F

3.3
5.0

40.0
30.0

tPHL, tPLH

Propagation Delay, tD
SO to Data Out

3.3
5.0

tPHL

Propagation Delay, tOHF
SO to 

16.0
11.5

/1,23.0

/1J~~,

}:«1~X/~;)

V/1~fo~>;;
'1<3t
1/I/~'i
7.5
/ I/;?
55

<)::>

tpLZ

Output Disable
OE to On

3.3
5,0

6.0
4.5

tPZH

Output Enable
OE to On

3.3
5,0

9.0
6.5

tPHZ

Output Disable
OE to On

3.3
5.0

9,0
6,S

fSI

Maximum SI
Clock Frequency

3.3
5,0

60
85

fso

Maximum SO
Clock Frequency

3.3
5.0

fBO

Maximum
Clock Frequency
SO Burst Mode

fBI

Maximum
Burst-In Clock

~I

"f"

I':,

(<<~~~:::;:< 1/ '//'"

ljl l,(:',~~,,;:';) l

((i /} f!:::;;~>
<"/

3-7

MHz

1

50
60

MHz

4

3.3
5.0

55
65

MHz

7

3.3
5.0

60
85

MHz

6

'Voltage Range 3,3 is 3,3 V ± 0.3 V
Voltage Range 5,0 is 5.0 V ± 0,5 V
Military parameters given herein are for general references only, For current military specifications and subgroup testing information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5-309

•

AC708

• ACT708

AC Operating Requirements
74AC

54AC

74AC

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL= 50 pF

TA= -40°C
to +85°C
CL=50 pF

Units

Fig.
No.

tw

ns

1,6

tw

ns

1, 6

Vcc·
(V)

Guaranteed Minimum

Typ

ts

Setup Time, HIGH or
LOW, On to SI

th

Hold Time, HIGH or
LOW, On to SI

3.3
5.0

tw

MR Pulse Width, tMRW

3.3
5.0

17.0
13.0

2

tree

MR

Recovery Time, tMRSIH
to SI

3.3
5.0

7.0
4.0

2

tw

SO Pulse Width, tSOH
HIGH

3.3
5.0

4.5
2.0

4, 7

tw

SO Pulse Width, tSOL
LOW

3.3
5.0

12.5
9.0

ns
ns

ns

4, 7

'Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·310

AC708 • ACT708
AC Characteristics

Symbol

Parameter

Vcc*
(V)

74ACT

54ACT

74ACT

TA= +25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to + 85°C
CL=50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

Fig.
No.

tPLH, tPHL

Propagation Delay, tlR
SI to IR

5.0

1.0

6.5

11.0

1.0

14.0

1.0

12.0

ns

1

tPLH

Propagation Delay, tlHF
SI to >HF

5.0

1.0

10.5

17.0

1.0

21.5

1.0

19.5

ns

1

tPHL

Propagation Delay, tlF
SI to Full Condition

5.0

1.0

10.5

16.5

1.0

21.5

1.0

19.5

ns

1

tPLH

Propagation Delay, tiE
SI to Not Empty

5.0

1.0

10.0

15.5

1.0

19.5

1.0

17.5

ns

1

tPLH

Propagation Delay, tlOR
SI to OR

5.0

1.0

10.5

16.5

1.0

21.5

1.0

19.0

ns

1

tPLH

Recovery Time, tMRIRH
MR to IR

5.0

13.5

8.5

17.5

15.5

ns

2

tPHL

Recovery Time, tMRORL
MR to OR

5.0

25.5

16.5

32.5

29.0

ns

2

tPHL

Recovery Time, tMRO
MR to Full Flag

5.0

14.0

9.0

17.5

16.0

ns

2

tPHL

Recovery Time, tMRE
MR to HF Flag

5.0

27.5

17.5

34.0

30.5

ns

2

tPHL

Recovery Time, tMRONL
MR to On, LOW

5.0

15.0

9.0

18.5

17.0

ns

2

tw

IR Pulse Width, tiP

5.0

43.0

28.0

58.5

51.5

ns

3

tw

HF Pulse Width, t3F

5.0

46.5

30.0

64.5

56.0

ns

3

5.0

1.0

18.5

29.5

1.0

38.0

1.0

34.5

ns

4

Propagation Delay, to
tPHL, tPLH
SO to Data Out
tPHL

Propagation Delay, tOHF
SO to --~c

Note: MR is HIGH; tHIGH>tSIH; tLOW>tSIL; tHIGH + tLOW> 1/fBI.

Mode 7: Shift-Out Operation in High-Speed Burst Mode
Sequence of Operations
1. Shift·Out is LOW; valid data is available on
output with OR ignored.

3. Shift-Out falls pulse width time tHIGH after rise
Shift-Out is complete; new data is loaded onto
output.

2. Shift-Out rises; data out is latched.
The burst-out rate is determined by SO HIGH and
LOW. The OR flag is ignored.

Figure 7: Modes of Operation
Mode 7
tLOW _1-----"1/""8"'0'-----1

50

00·08

1s1 DATA WORD

2nd DATA WORD

tD

Note:

OE is

LOW; MR is HIGH; tHIGH > tSOH; tLOW>tSOL; tHIGH +tLow>1/fBo,

5·322

AC723 • ACT723
FIFO Expansion
Word Width Expansion
Word width can be increased by connecting the
corresponding input control signals of multiple
devices. Flags can be monitored on anyone device
(Figure 8), or composite flag signals can be
achieved by ANDing the corresponding flags.

respectively. The IR signal from each FIFO is
connected to its preceding 50 signal:
IR(n)-50(n-1); IR(n-1)-50(n-2) ... IR(2)-50(1). The
OR signal from each FIFO is connected to its
succeeding 51 signal: i.e., OR(1)-51(2); OR(2)-51(3)
. .. OR(n-1)-51(n). Handshaking signals are shown
in Figure 10.

Depth Expansion
Depth expansion can be achieved by connecting as
shown in Figure 9. No external circuitry is required
for handshaking, which is achieved by the internal
FIFO signals IR and OR.

FIFO 1 operates in Mode 5 during 51 until FIF02 is
filled. FIF02 operates in Mode 3 during 50 until
FIF01 is empty. Data from FIF01 is written into
FIF02 after a word is read from FIF02. To achieve
this, the OE pin is grounded for FIF01. In general,
for n FIFOs, a" DE pins but the nth FIFO's OE pin
are enabled. 3-state control of the outputs can then
be achieved by controlling the nth FIFO's DE pin.

When n FIFOs are cascaded to attain a 64n word
FIFO, the 51 signal is connected to the first FIFO
and the 50 signal to the nth FIFO. The IR and OR
signals are monitored from the first and last FIFOs

Figure 8: Word Width Expansion -

DIN (O-S)

1

9

64 x 18 FIFO

9

Do·s

Oo·s
FIF01 IR
so 64 x 9 OR

•

DOUT (O-S)
IR1
OR1

r - - - Sl

-&:,9 IlIIA
II /'"
5:6 ( 1/ II/ ~/< .~!

tw

Reset Pulse Width

5.0

l.J

tREC

Reset Recovery Time

5.0

tRTC

Retransmit Cycle Time

5.0

Jns

tw

Retransmit Pulse Width

5.0

ns

tREC

Retransmit Recovery
Time

5.0

ns

'If

("I

I V/

Fig.
No.

ns
ns

L/"l

/< /1 I

<[0,)'1,
i',."

/7<~'~~7

t::::,

ns
~s

1s /

r'JJ

n~/'

·Voltage Range 5.0 is 5.0 V ± 0.5 V
Military parameters given herein are for general references only. For current military specifications and subgroup testing
information please request Fairchild's Table I data sheet from your Fairchild sales engineer or account representative.

5·338

AC725 • ACT725
Figure 1

ANALOG TO
DIGITAL
CONVERTER

ANALOG
DATA

a: Typical Application -

DIGITAL
DATA

Signal Processing System

SLAVE PROCESSOR

SLAVE PROCESSOR

SLAVE PROCESSOR

•

SLAVE PROCESSOR

b: Typical Application -

High-Speed Multiprocessing System

Figure 2: Reset

IRS

Lf

--'

Vi

EF-----=i~
_ _ IEFL

= tRS + tRSR
Wand R = VIH during RESET

Notes: tRSC

5-339

________
I-IRSR

AC725 • ACT725

Figure 3: Asynchronous Write and Read Operation

Qo· Q a - - - - - - I

w-f~';1 ,~; ~
~

twe

---JI

Do· Da

-----iK

DATA·IN VALID

~

(rD-p;-JA-.I-N-VA-L-ID""'\)>----

Figure 4: Full Flag from Last Write to First Read

LAST WRITE

FIRST READ

R---~----------------+-~
W

----1--'1
tRFF

FF----l--~

5-340

ADDITIONAL
READS

FIRST WRITE

AC725 • ACT725
Figure 5: Empty Flag from Last Read to First Write
ADDITIONAL
WRITES

FIRST WRITE

LAST READ

FIRST
READ

W

QO·Q8

Figure 6: Retransmit

•

tRT

,) l

-\
R,W

tRTR
Notes: tRTC = tRT + tRTR
EF/HF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be
valid at tRTC.

Figure 7: Empty Flag Timing

Note: tRPE = tRPW

5·341

AC725 • ACT725
Figure 8: Full Flag Timing

Note: tWPF

=twpw

Figure 9: Half·Full Flag Timing

,

w

\.

.

-'

-

•

i--

tWHF

Half·Full or Less

tRHF

~

7~

- M o r e than Half·Full

-1 __

Half·Full or Le ss

Operating Modes
Width Expansion Mode
Word width may be easily increased by connecting
the corresponding input control signals of multiple
devices. Status flags, EF, ff and HF, can be
detected from anyone device. Any word width can
be obtained with additional 'ACI'ACT725s.

Single Device Mode
A single 'ACI'ACT725 device may be utilized for
applications requiring 512 words or less. The
'ACI'ACT725 is in a single device configuration
when Expansion In (xl) is grounded. In this mode,
HF flag is valid.

Figure 10: Block Diagram of Single 512 x 9 FIFO

.

Vi

r
h.

h.
DATA IN

(D)

(Q)

DATA OUT

r

r

XiI
5-342

AC725 • ACT725
Operating Modes, cont'd

Depth Expansion (Daisy Chain) Mode

Figure 11: Block Diagram of 512 x 18 x 18
FIFO Memory Used in Width
Expansion Mode

The 'ACI'ACT725 can easily be adapted to
applications when the requirements are for greater
than 512 words. Any depth can be obtained with
additional 'ACI'ACT725 devices. The 'ACI'ACT725
operates in the Depth Expansion mode when:

DATA
IN (D)

W-----~I

i'i'_-------1

iiS--------I

~====REi'

I-

1. FL of the first device is grounded.
2. FL pins of all other devices are HIGH.
3. XO of each device is tied to XI of the next
device.
4. External logic is needed to generate a
composite FF and EF. This requires ORing all
EFs and all FFs, I.e., all must be set to generate
the correct composite FF or EF.
5. The RT function and HF are not available in the
Depth Expansion mode.

•

Notes: Flag detection is accomplished by monitoring FF,
EF and FiF on any device used in the width
expansion configuration. Output signals should not
be connected together.

Figure 12: Block Diagram of a 1536 x 9 FIFO Memory (Depth Expansion)

~~--,---+------R

Do·D8 ------,{--,---r--,

I-+--.--t-t-----

RS--------~~

5·343

Vee

AC725 • ACT725
Operating Modes, cont'd
Compound Expansion Mode
The two expansion techniques described
previously can be combined in a straightforward
manner to achieve large FIFO arrays.

read and write operations) can be achieved by
pairing '725s as shown in Figure 14. Care must be
taken to assure that the appropriate flag is
monitored by each system (FF is monitored on the
device where W is used; 'EF is monitored on the
device where 'F{ is used). Both Depth Expansion
and Width Expansion may be used in the
Bidirectional Mode.

Bidirectional Mode
Applications which require data buffering between
two systems (where each system is capable of

Figure 13: Compound FIFO Expansion

Q.·Q17

Co· Q8

···

Q (n·8)· Qn

Q(n-8)' an

Q•• Q8

if

·• ····

Vi
RS

018-0n e

09· On

Do· On

Notes: For depth expansion block, see Depth Expansion and Figure 12.
For flag detection, see Width Expansion and Figure 11.

Figure 14: Bidirectional FIFO Mode

WA

iii
ffii

FFA

~

Hl'i

FIFO
QBo·a

DAD·8

-y

.

A

~

SYSTEM B

SYSTEM A

r

~

IADBO·8

QAO·8

iii:

FIFO

~

Ws

HFA

ffi

FFB

5-344

AC725 • ACT725
Data Flow-Through Modes
Two types of flow-through modes are permitted
with the '725: read flow-through and write
flow-through.

immediately upon writing one word of data into the
completely empty FIFO.
In the write flow-through mode (Figure 16), the
FIFO permits writing a single word of data
immediately after reading one word of data from a
completely full FIFO.

For the read flow-through mode (Figure 15), the
FIFO permits reading a single word of data

Figure 15: Read Data Flow-Through Mode

Do· Os

W

--!---"'
tRPE

R .....-+__________________+-______+-________- J
EF __-+__________________+-____- J

Qo· Qs

---t------------------~~mm~~~~~~~~

Figure 16: Write Data Flow-Through Mode

~
-tWPF-

w
_tRFF

I

_ _ tWFF

,

1\

Do· Os
~

tA

-

------+-

5·345

V--

1-

DATA IN
VALID

-

tS---j

l-tH

•

AC818 • ACT818
54AC/74AC818 • 54ACT/74ACT818
8-Bit Diagnostic Register
Description

Connection Diagrams

The 'ACI'ACT818 is a high-speed, general-purpose
pipeline register with an on-board diagnostic
register for performing serial diagnostics and/or
writable control store loading.
The D-to-Y path provides an 8-bit parallel data path
pipeline register for normal system operation. The
diagnostic register can load parallel data to or from
the pipeline register and can output data through
the D input port (as in WCS loading).
The 8-bit diagnostic register has multiplexer inputs
that select parallel inputs from the V-port or
adjacent bits in the diagnostic register to operate
as a right-shift-only register. This register can then
participate in a serial loop throughout the system
where normal data, address, status and control
registers are replaced with 'ACI'ACT818 diagnostic
pipeline registers. The loop can be used to scan in
a complete test routine starting point (Data,
Address, etc.). Then after a specified number of
machine cycles it scans out the results to be
inspected for the expected results. WCS loading
can be accomplished using the same technique.
An instruction word can be serially shifted into the
shadow register and written into the WCS RAM by
enabling the D output.

Pin Assignment
for DIP, Flatpak and SOIC

06

04

NC 03

02

01

07~

[!joo

SOI~

[!jOClK

GNO~

• On-Line and Off-Line System Diagnostics
• Swaps the Contents of Diagnostic Register and
Output Register
• Diagnostic Register and Diagnostic Testing
• Cascadable for Wide Control Words as Used in
Microprogramming
• Edge-Triggered 0 Registers
• Outputs Source/Sink 24 mA
• 'ACT818 has TTL-Compatible Inputs
• 'ACT818 Is Functionally- and Pin-Compatible to
AMD 29818 and MMI 74S818

[[JOEY

~~

m~

PClK~

~Vcc

~~

~~~

~~

~~

~~®l~~~~
Ys

Ys

Y4

Ne

V3

Y2

Y,

Pin Assignment
for LCC and PCC

Logic Symbol

Applications
•
•
•
•
•
•
•
•

05

Ijj]~[[][[]m[!][!]

Register for Microprogram Control Store
Status Register
Data Register
Instruction Register
Interrupt Mask Register
Pipeline Register
General Purpose Register
Parallel·SertaIlSerial·Paraliel Converter

OEY

PClK

5-346

AC818 • ACT818
Pin Names

Do - 07
SOl
DCLK
MODE
PCLK
OEY
SDO
Yo - Y7

Ordering Code: See Section 6
Data Inputs
Serial Data Input
Diagnostics Clock
Control Input
Pipeline Register Clock
Output Enable Input
Serial Data Output
Data Outputs

Diagnostic Register
ft

~

Y7

(

r----- -----------l-------1
SOI-::-- - - r - - + - - - - - - j - - - - - +

+---+---.j

I
I
I

I
I

MO 0 E

-----t-:

L..--,---'

I
I
I
I
I

I

I
I

-

OCLK

I
I
I

i

i

i i

I
I
I

i i

----------So

S1

-----))------

Block Diagram

_________________ J

S7

07· Do

SOI----,------I
DCLK---r--4--I

8·BIT
DIAGNOSTIC
REGISTER

~~---~-SOO

MODE-~-----~

PCLK--------~~

8·BIT
OUTPUT
REGISTER

OE-----------~

Y7· Yo

5-347

•

AC818 • ACT818
Functional Description
Oata transfers into the diagnostic register occur on
the LOW-to-HIGH transition of DCLK. Mode and
SDI determine what data source will be loaded.
The pipeline register is loaded on the LOW-toHIGH transition of PCLK. Mode selects whether
the data source is the data input or the diagnostic

register output. Because of the independence of
the clock inputs, data can be shifted in the
diagnostic register via DCLK and loaded into the
pipeline register from the data input via PCLK
simultaneously, as long as no setup or hold times
are violated. This simultaneous operation is legal.

Function Table
Inputs
SDI

Outputs

Operation

MODE DCLK PCLK

SOO

Diagnostic Reg.

Pipeline Reg.

X

L

I

X

S7

SkSI-1,
SO);

5.5
4.0

ns

3-9

ns

3-9

ns

3-9

ns

3-9

ts

setup Parameter
\

)
;( ;:::--,
"--"
fmax

tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tpLZ

Vee*
(V)

~

,

'''''',) / / 0
"
Propagation Delay
CP to On

~

Output Enable Time
OEto On
Output Enable Time

DE to On
Output Disable Time
c:>E to On
Output Disable Time

DE to On

TA=+25°C
CL=50 pF

TA= -55°C
to + 125°C
CL=50 pF

TA= -40°C
to +85°C
CL=50 pF

Min

Min

Typ

Max

Max

Units

Fig.
No.

MHz

3·3

ns

3·6

ns

3·6

ns

3·6

ns

3·7

ns

3·8

Max

110

f"""

prOpagation·'b.ti~ ··v

Propagation Delay

74ACT

5.0

CP to On

CLR to On

54ACT

Min

"

Maxi;'~
~~~:
Frequ~ney J /,

74ACT

5.0

/i I'.8.0

1;2
;
tOC"all.-

!

~1

IP7

[Q7

rP6

[Q6

"-'---::>--0

I

V

em

IPS

-+P7

~

IQS

i PL8DC~ f- " [Q4

< ~4

,

I

uo;

I

I!<.~

-"'

[ocell rP3

~

-

j;IS
[:>---:J

IJ>2

IBC81 0'1

I I

[ocell

P8

'C' '; r-------...2

P3

Q4/1-

l.--""""

~~

-

~--...-------'""'~

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TC

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Figure 8-3: Sample Circuit Network Analysis Summary

NETWORK "ALYSIS IIURUMY
PWER ,U""ARY TAIoLI

"""au.

a, ••

"_ ••• u.

Noa,n.l

IttU,'
On-Cha.p

Itt CA.
Otf-C'"p

I •• CA.

0.001

0.040

0.010

0.08

0.:'29

1.55

0.040

0.339

I.U

vee·

0.00
'4.70
·1 ....0

PDIW.

ItLCAJ
On-Ctlap

IttC')

Off-e", ..

0.001

0.040

' •• '"

POUU

Itte.,
On-C'up

0.013

0.11

0.41'

2.18

IttcAI
tla','·Ctup

"rl.era

ell •••• :

Total.:

0.001

VEE·
VTT •

0.040

0.001

vee·
VEl·
'ITT·

IJ.~...

...s . .

0.432

0.00
-5.20
-2.00

vee·
VEE •

VTT

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CELL UTILIZATION .URNARY

........ _---_ ..

NURIER USED

CELL TYPE

NURIER AVAILABLE

.. _- ..... _-_ ....... -.......

PIRCERT USED

172.
35
70

'.55_
14.2••
24.2._

1105
5
17

INTERRAL
INPUT
1/0

.. ...... --- .......

UROR
.. --_ ................ -- .... -_.............................
-_ TYPE
.... -- --_ . -- IRROR
............ DISCRIPTION
_...... --_ .............. -_ .............................. _................................................................... .

RET/CORPONENTIPIN NAIIE
CTR/BUFO

OJ

·E

REGULAR LCS INPUTS AND TRANSLATED INPUTS CANNOT U

eTR/BUF,

7

-E

WIRED-OR RACROS RUST HAVE IIIUTICAL "ACRo POWER.

CTR/8UF22

•

·E

CTR/8UF23

10

"

CTR/81jF30
CTR/BUrll

10

CTR/BUFl2

"

eTR'HUF33

"ACRO MA"E

CELL TYPE

2NA04

INTERNAL
INTUNAL
INTUNAL
INTERNAL
INTERNAL
JNlEtI'MAL

AN~02

aUF02
DFP02
lNVOI
IN\'11
"X021

W

IHTEN"AL

,.ORO':

INTERNAL

NOROl
ORO:

INTERNAL

NACRO OUTPUT NOT CONNECTED.
-E

1

...

3 ...
9
10.

•.
~

4
7

INTERNAL

4

.uio10~

INTERNAL

l

1/(;

~

~

ONLY INTERNAL CELL NACNOS CAN HAVE OUTPUT DOTTING.

NURIER USED

XNOROl1

~

.

1('1

:"

: ".:,-,. ;

:";'1,1

:i'\I;;'S

INP~'

:i:tv:·:·

•

"ACRO OUTPUT NOT CONNECTED.

ON~04

!

~IN

"ACRO OUTPUT NOT CONNECTEII.

OUTPUT PIN IS' NOT CONNECTED.

INTERNAL
1 NTEN,UL

: . '......' ~
lu..-I.·:&
.!b"1.
'l'",'"

ILLEGAL OPEN INPUT

CoNNICTEII SIMULTANEOUSLY.

:N?~I

'''?'.'

8-5

•

the existence of injected faults. Then, after
placement and routing are complete, corrected
delay times can be computed using actual wiring
distances. To speed the computer-intensive task of
fault simulation, access to Fairchild's Cray 1-8
Supercomputer (located In Milpitas, California) is
provided. Now, controllability analysis is run by
FAIRCAD at your facility to generate a potentially
detectable and undetectable faults listing. Test
vectors are produced for automatic test equipment
(ATE) with programs that create and edit packagepin files and supply input/output pin information.

Circuit Design Rule Checking
FAIRCAD's circuit analyzer checks the design to
find problems early in the design cycle. This
program extracts a netlist from a capture design
and checks it for design rule violations, calculates
power dissipation and summarizes the usage of
logic macros. The design rule checker also
analyzes netlists produced using FAIRCAD's
Netlist Input Mode. See Figure 8-3 for a sample
!'letlist summary. Errors found in your design must
be corrected before design continuation. Circuit
analysis checks fan-out, determines bias types
required for each macro (ECl only), and
automatically places additional power pads where
required. Illegal macro interconnections such as
the following are also checked:
•
•
•
•
•
•

LoglclTiming Simulation
FAIRCAD's logic and timing simulators are used
for accurately gauging the functionally and
performance of the design early in the design
cycle. Using FAIRCAD, nodes can be set to
specific values; simulated and compared results
may be with the expected results. FAIRCAD's easyto-learn Fortran-like control language provides the
ability to inspect and set internal nodes, do
conditional branching, looping, and simulate such
conditions as circuit stability. Simulation on
FAIRCAD can be hierarchical; any block. (or an
entire circuit) in the hierarchy can be simulated,
saving time and facilitating circuit debugging.

Illegal open pins
Wired ORion-chip bussing violations
Unblasable connections
Incompatible circuits
Excessive fanout
Net naming conflicts

Simulation
•
•
•
•
•

Hierarchical
Accurate Default Delays Automatically Calculated
Access to Internal Nodes
Hex/Octal Input to Circuits
Flexible Simulation Programming

Both logic and timing Simulation check for
violations such as minimum pulse width, setup
time, hold and release time. The FAIRCAD timing
program allows simulation of one timestep, one
clock cycle, or multiple timesteps at a time, and
inspection of internal nodes and 1I0s
simultaneously. Prior to placement and routing,
default metal lengths and default wire delays are
used; after placement and routing, actual metal
delays are used.

Simulation is used after the design has been
entered into FAIRCAD and a netlist generated
without any logic design violations. logic, timing,
and hierarchical simulation, as well as test
program generation, are available on FAIRCAD.
With hierarchical simulation you can simulate any
block of a design as if it were an Independent
design: this hierarchical approach facilitates
efficient design partitioning while maintaining
consistency and improving the integration of the
overall circuit. See Figure 8-4 for a sample
FAIRCAD timing simulation output.

Fault Simulation
Fault simulation informs the user if, by inspecting
the design's output pins, manufacturing defects
modeled as "stuck-at" faults can be detected. To
ensure test vectors screen potential manufacturing
defects (short, open, pin hole, etc.), Fairchild
provides access to a Cray 1-S Supercomputer and
a powerful fault simulation program. In FAIRCAD,
fault simulation is divided into two stepscontrollability and observability. Controllability,
invoked by a single command in the test sequence,

First, using typical, automatically calculated
propagation delays for all components, logic
simulation is performed on FAIRCAD to check the
accuracy of the logic. Initially, fault simulation is
run to determine whether the input test patternsprovided by the designer-successfully diagnose

8-6

FAIRCAD's powerful placement program allows
random, manual, or automatic placement of
components. FAIRCAD provides the ability to
interactively place II0s andlor critical path
components in minutes. Automatic placement
programs (automatic parameters, placement and
improvement) are available to help achieve the
optimum placement of your design. Placement, like
all other interactive FAIRCAD programs, is menu·
driven with extensive "help" features that list all
possible user options. Many important display
features such as cell and component outlines are
also provided .

determines the percent of internal nodes being
toggled by the vectors provided. In short, this
analysis shows how effective the test vectors are
in controlling the faults. Observability, which is
accomplished using the parallel fault simulator on
the Cray 1-S Supercomputer, propagates the faults
to primary outputs; this determines if the faults are
detectable.

Placement
•
•
•
•

Automatic/Interactive
Automatic Improvement
Prohibits Design Rule Violations
Congestion Parameter Settings

Figure 8-4: FAIRCAD Timing Waveforms
-. - :.-:

......

". - -~

.:;-

..... ~::;

]5

:]3

D2
01

G!0
LOAD
PESET

•

CLOCK
P7
P6
P5
P4
P3
P2
Pl
PEl
9ElEll

12El61

15661

8·7

18661

21661

246El1

3El

Single-keystroke commands allow you to change
the color of various levels, make a hard copy of
what is currently visible on the terminal screen,
graph congestion values, or show placement
obstructions. The congestion graph feature,
illustrated in Figure 8-5, helps you minimize
interconnect length and congestion by
automatically graphing vertical and horizontal
placements. Cell "overlaps" are averted with a
program that automatically informs you if a
selected component placement overlaps others
previously placed.

Before placement, a FAIRCAD program compiles
and merges the netlist (generated by the circuit
design rule checker) and chip databases into a
format suitable for both placement and routing. An
output listing is then produced that contains the
following:
•
•
•
•
•
•

Circuit Netlist Description
Overall Circuit Summary
Detailed Summary of Component Macro Types
Detailed Summary of Components
Detailed Summary of Nets
Component-Net Cross Reference List

To aid in the organizing of the placement, an
extensive display menu is available for viewing
selected component outlines, labels, cells, etc.

Figure 8-5: FAIRCAD Placement with Congestion Graph Feature

8-8

Routing
•
•
•
•

Automatically invoked each time you exit the
routing editor, the DRC warns of any design rule
violation. Table 8-1 lists FAIRCAD routing features.
Figure 8-6 shows a typical routing display.

Automatic/Interactive
Automatic Improvement
Prohibits Design Rule Violations
Congestion Parameter Settings

Table 8·1: Routing Programs and Functions
Like placement, FAIRCAD's routing program has
both manual and automatic features and is
completely interactive. Critical nets may be prerouted and the automatic router invoked to finish
routing the design. Manual routing, completely
menu-driven, is available for specifying critical
paths and editing disconnects. FAIRCAD's program
for viewing the design reads information from the
design file and allows viewing of unconnected
nets; "airlines"-diagonal lines-are drawn
between unconnected pins. As an additional
safeguard against errors, FAIRCAD employs the
automatic Design Rule Checker (DRC).

Program

Functions

Route Chip
Automatically

automatically routes
component interconnections

View the Chip

allows you to view various
aspects of your design at any
time after design file
generation

Manual Routing

allows you to pre-route critical
nets and edit routing

Figure 8·6: FAIRCAD Routing Display

L.J

0

L.J

LJ

III

2~0RI02

1
LJ

2B
LJ

II

•

[]-

0

L.J

El

El

I Lr

u

=L.J

L.J

(j

0
0-

w

0LJ

D

26.1SX scale, at <-0_073,-0.0&46:>·'

8·9

-EJ

-

•

Engineering Support

FAIRCAD, databases and accompanying files
require approximately 50 Megabytes of storage
space. In addition to space required for FAIRCAD
and its files, approximately 50 Megabytes of
storage space is also required for the chosen array.

Fairchild applications engineers, the experts of
gate array design, are available for assistance
during the work week and, by arrangement, can
complete some or all of FAIRCAD's design tasks
for you.

MicroVAX "
Instruction

FAIRCAD is available for use on the DEC
MicroVAX II. All FAIRCAD design tasks, including
simulation, placement and routing, can be
accomplished using the MicroVAX at your facility.
Access to the Cray 1-S Supercomputer for fault
simulation is available when designing with the
MicroVAX II. Two MicroVAX II configurations are
supported for FAIRCAD-the workstation and
minicomputer configurations. The workstation
configuration, which supports 1-2 users, requires
the following:

Because you may only have a workable concept of
what you want your circuit to do, Fairchild places a
premium on instruction. Courses are taught by
knowledgeable applications engineers at
FAIRTECH design centers, and by special
arrangement can be taught at your facility.
Classrooms equipped with color graphics
terminals-one per student-and video projection
systems provide the perfect place to explore gate
array design.
A first-time customer will take both the hardware
design course (1-2 days) for his chosen gate array
family and the FAIRCAD training course (5 days).
Since FAIRCAD is technology independent, the
FAIRCAD seminar need not be repeated to
accomplish a design using a different Fairchild
gate array family. Instruction on FAIRCAD system
installation and administration is also available. A
complete listing of class dates and times is
available at Fairchild Design Centers and sales
offices. Training credits are provided with NRE
charges for each design option.

• BA123 MicroVAX II cabinet (World Box)
• Three 71 Megabyte disk drives (two for single
user)
• RQDX3 disk controller
• 1-2 Tektronix graphics terminals (4107, 4109, 4113,
4115,4125)
.1-2 VT220 (VT100-compatible) terminals (one for
each graphics terminal)
• TK50 tape drive
• MicroVMS operating system
The minicomputer configuration, supporting 1-8
users, includes the following:

FAIReAD Hardware Requirements
To run FAIRCAD at your facility you must have the
DEC VMS operating system and FAIRCADcompatible hardware. The following lists operating
system and hardware requirements:

H9642 MicroVAX II cabinet
5 Megabytes (min) memory
RA81 456 Megabyte fixed disk
1-4 Tektronix graphics terminals (4107, 4109, 4113,
4115, 4125)
• 1-4 VT220 (VT100-compatible) terminals (one for
each graphics terminal)
• TK50 tape drive
• MicroVMS operating system
•
•
•
•

• VMS Operating System V4_2
• MicroVAX II, VAX 111750, 111780, 111785,8600,
8650
• Tektronix Graphics Terminals 4113, 4115, 4107,
4109,4125
• VT100-Compatible Terminals (one for each
graphics terminal)
• 9-Track Tape Drive

8-10

Product Index and Selection Guide

FACT Descriptions and Family Characteristics

Ratings, Specifications and Waveforms

Design Considerations

Data Sheets

Package Outlines and Ordering Information

FGC Series Advanced 2-Micron CMOS Gate Array

FAIRCAD™ Semicustom Design System

CMOS Arrays Packaging Guide

Field Sales Offices and Distributor Locations

I=AIRCHILD

CMOS Arrays
Packaging Guide

Introduction

Quad Packages

This guide describes the packaging options
available for FGC Series CMOS gate arrays. A wide
selection of lead counts and package styles,
including dual in-line, leaded chip carriers, pin grid
arrays and ceramic flatpaks, is offered. Table 9-1
lists the package styles and lead counts available
and planned for each array in the FGC Series.

Plastic and ceramic leaded chip carriers (J-bend)
with lead counts from 44 to 84 are available for the
entire FGC Series of arrays. Refer to Table 9-1 for
specific product applicability.

Pin Grid Arrays
Plastic and ceramic pin grid arrays with lead
counts from 68 to 209 are available for all FGC
Series arrays except the FGC0500. Refer to Table
9-1 for specific product applicability.

The following paragraphs summarize the data
presented in the table.

Dual In-Line Packages
Plastic and ceramic dual in-line packages with lead
counts from 20 to 64 are available for FGC Series
arrays with fewer than 4000 equivalent gates. Refer
to Table 9-1 for product applicability.

•
9-3

Table 9·1: FGC Series Package Selection Guide
FGC

FGC

FGC

FGC

FGC

FGC

Lead Count

Style

0500

1200

2400

4000

6000

8000

20
20

PDIP
CDIP

A
P

24
24

PDIP
CDIP

A
A

A
A

A
A

28
28

PDIP
CDiP

P
A

P
A

A
A

40
40

PDIP
DCIP

A
A

A
A

A
A

P
P

44
44

PLCC
CLCC

A
P

A
A

A
A

A
P

48
48

PDIP
CDiP

A
A

A
A

A
A

64
64

PDIP
CDIP

68
68
68
68

PLCC
CLCC
PPGA
CPGA

P
A
A
A

A
P
A
A

A
P
P
A

A
A

84
84
84
84

PLCC
CLCC
PPGA
CPGA

P
A
A

P
A
A
A

A
A
P
A

A
A
P
P

120
120

PPGA
CPGA

A
A

A
A

P
A

132

CFPAK

P

P

144
144

PPGA
CPGA

P
A

A
A

A
A

180

CPGA

A

A

209

CPGA

A
A

P
P

A

PDIP = Plastic Dual In-Line Package
CDIP = Ceramic Dual In-Line Side Brazed Package
PLCC = Plastic Leaded Chip Carrier (J-Bend Leads)
CLCC = Ceramic Leaded Chip Carrier (J-Bend Leads)
PPGA = Plastic Pin Grid Array
CPGA = Ceramic Pin Grid Array
CFPAK = Ceramic Flatpak

9-4

A=Avaiiable
P= Planned

Product Index and Selection Guide

FACT Descriptions and Family Characteristics

Ratings, Specifications and Waveforms

Design Considerations

Data Sheets

Package Outlines and Ordering Information

FGC Series Advanced 2-Micron CMOS Gate Array

FAIRCAD™ Semicustom Design System

I CMOS Arrays Packaging Guide
Field Sales Offices and Distributor Locations

Fairchild
Semiconductor
Alabama
555 Sparkman Drive, Suite 1030
Huntsville, Alabama 35805
Tel: 205-837-8960
Arizona
9201 North 25th Avenue, Suite 215
Phoenix, Arizona 85021
Tel: 602-943-2100
California
Auburn Office (Temporary)
3620 Sugarview Road
Meadow Vista, California 95722
Tel: 916-823-6664
·Costa Mesa Office
3505 Cadillac Avenue, Suite 0-104
Costa Mesa, California 92626
Tel: 714-241-5900
·Cupertino Office
10400 Ridgeview Court
Cupertino, California 95014
Tel: 408-864-6200
Encino Office
15760 Ventura Blvd., Suite 1027
Encino, California 91436
Tel: 818-990-9800
San Diego Office
4355 Ruffin Road, Suite 100
San Diego, California 92123
Tel: 619-560-1332
Colorado
Colorado Springs Office
102 South Tejon Street, Suite 1100
Colorado Springs, Colorado 80903
Tel: 303-578-3319
Denver Office
10200 East Girard
Bldg. B., Suite 222
Denver, Colorado 80231
Tel: 303-695-4927
Connecticut
2440 Whitney Avenue
Hamden, Connecticut 06518
Tel: 203-288-1560

United States
and Canada

Sales
Offices
Florida
Deerfield Beach Office
450 Fairway Drive, Suite 107
Deerfield Beach, Florida 33441
Tel: 305-421-3000
·Orlando Office
Maitland Colonnades
2301 Lucien Way, Suite 260
Maitland, Florida 32751
Tel: 305-875-0500
St. Petersburg Office
9800 4th Street North, Suite 206
St. Petersburg, Florida 33702
Tel: 813-577-1380
"Georgia
3080 Northwoods Circle, Suite 130
Norcross, Georgia 30071
Tel: 404-441-2740
Illinois
500 Park Blvd., Suite 575
Itasca, Illinois 60143
Tel: 312-773-3133
Indiana
11711 North Meridan Street
Suite 200
Carmel, Indiana 46032
Tel: 317-843-5686/5687
Iowa
373 Collins Road NE, Suite 200
Cedar Rapids, Iowa 52402
Tel: 319-395-0090
Kansas
8600 West 110th Street, Suite 206
Overland Park, Kansas 66210
Tel: 913-451-8374
Maryland
10270 Old Columbia Road
Suite R
Columbia, Maryland 21046
Tel: 301-381-2500
Massachusetts
*1432 Main Street
Waltham, Massachusetts 02154
Tel: 617-890-4000

• Fairtech Center located in this office
10-3

Michigan
21999 Farmington Road
Farmington Hills, Michigan 48024
Tel: 313-478-7400
Minnesota
·3600 West 80th Street, Suite 590
Bloomington, Minnesota 55431
Tel: 612-835-3322
New Jersey
783 Riverview Drive North
Totowa, New Jersey 07512
Tel: 201-256-9006
New Mexico
2900 Louisiana NE, Suite D
Albuquerque, New Mexico 87110
Tel: 505·884-5601
New York
Endicott Office
421 East Main Street
Endicott, New York 13760
Tel: 607-757-0200
Fairport Office
830 Cross Keys Office Park
Fairport, New York 14450
Tel: 716·223-7700
Hauppauge Office
300 Wheeler Road
Hauppauge, New York 11788
Tel: 516-348-0900
Poughkeepsie Office
66 Middlebush Road, Suite U-306
Wappingers Falls, New York 12590
Tel: 914-298-0680
North Carolina
5954-A Six Forks Road
Raleigh, North Carolina 27609
Tel: 919-848-2420
Ohio
Cleveland Office
6133 Rockside Road, Suite 304
Cleveland, Ohio 44131
Tel: 216-447-9700

II
I

Fairchild
Semiconductor
Ohio

United States
and Canada

Sales
Offices
* Dallas Office

Dayton Office
7250 Poe Avenue, Suite 260
Dayton, Ohio 45414
Tel: 513-890-5878

1702 North Collins Blvd.
Suite 101
Richardson, Texas 75080
Tel: 214-234-3811

Oregon
6600 SW 92nd Avenue, Suite 27
Portland, Oregon 97223
Tel: 503-244-6020

Houston Office
9896 Bissonnet-2, Suite 470
Houston, Texas 77036
Tel: 713-771-3547

Pennsylvania
Willow Wood Office Center
Suite 110
3901 Commerce Avenue
Willow Grove, Pennsylvania 19090
Tel: 215-657-2711

Utah
5282 South 320 West, Suite D120
Murray, Utah 84107
Tel: 801-266-0773

Texas

Austin Office
8310 Capital of Texas Hwy. N
Suite 160
Austin, Texas 78731
Tel: 512-346-3990

Washington

11911 NE First Street, Suite 310
Bellevue, Washington 98005
Tel: 206-455-3190

*Fairtech Center located in this office

10-4

Canada
Toronto Regional Office
7 Director Court
Building C, Unit 102
Woodbridge, Ontario L4L 4S5
Tel: 416-746-7120

Montreal Office
3675 Sources Blvd., Suite 109
Dollard des Ormeaux
Quebec, H9B 2K4
Tel: 614-683-0883
Ottawa Office
148 Colonnade Road South,
Unit 13
Nepean, Ontario K2E 7J5
Tel: 613-226-8270

Fairchild
Sem icond uctor
Austria and Eastern Europe

Fairchild Electronics GmbH
Assmayergasse 60
A-1120 Wien
Austria
Tel: (0222) 85-86-82

Sales
Offices

International

Fairchild Semiconductor GmbH
Zweigniederlassung Neufahrn
Hans-Braunstrasse 50
0-8056 Neufahrn
Tel: (08165) 61-80

Korea

Fairchild Semiconductor
10th Floor, Life Bldg.
61 Yuido-Oong, Youngdongpo-Ku
Seoul 150
Tel: 783-3795

Holland
Brazil

Fairchild Semiconductores Ltda.
Caixa Postal 30407
Rua Alagoas, 663
01242 Sao Paulo, Brazil
Tel: 66-9092

Fairchild Semiconductor B.v.
Ruysdaelbaan 35
NL-5613 OX-Eindhoven
The Netherlands
Tel: (040) 44-69-09

Scandinavia

Fairchild Semiconductor AB
Bergsunds Strand 39
S-117 38 Stockholm
Sweden
Tel: (08) 84-01-70

Hong Kong

Fairchild Semiconductor Ltd.
Rua Oswaldo Cruz, 505
Caixa Postal 948
13100 Campinas SP Brazil
Tel: 55-192-46655
55-192-416434

Fairchild Semiconductor Products
12th Floor, Austin Tower
22-26A Austin Avenue,
Tsimshatsui
Kowloon, Hong Kong
Tel: 3-723-5256

France

Fairchild Semiconductor (HK) Ltd.
5/F-6/F, San Miguel Bldg.
9-11, Shing Wan Road
Tai Wai, Shatin
NT Hong Kong
Tel: 852-0-6055311

Fairchild Semiconductor GmbH
Baumackerstr. 46
CH-8050 Zurich
Tel: (01) 311-42-30

Italy

Taiwan

Fairchild Semiconductori S.p.A.
Viale Corsica 7
20133 Milano
Tel: (02) 749-12-71

Fairchild Semiconductor Ltd.
Hsietsu Bldg., Room 502
47 Chung Shan North Road
Sec. 3 Taipei, Taiwan
Tel: 573205 thru 573207

Fairchild Europe Semiconductor
Headquarters
12 Place Oes Etats-Unis
B.P. 655
92542 Montrouge Cedex
Tel: (1) 47-46-61-61
Germany

Fairchild Semiconductor GmbH
Gebauede 458, Zimmer 2194
0-6000 Frankfurt/Main 75
Tel: (069) 690-56-13

Singapore

Fairchild Singapore Pty. Ltd.
74 Bukit Timah Road
#03-01/02
Boon Siew Bldg.
Singapore 0922
Tel: (65) 258-1944
Switzerland

Japan

Fairchild Semiconductor GmbH
Oeltzenstrasse 14
0-3000 Hannover
Tel: (0511) 178-44
Fairchild Semiconductor GmbH
Poststrasse 37
0-7250 Leonberg
Tel: (07152) 410-26

Fairchild Semiconductor
Pola Shibuya Bldg, 7th Floor
1-15-21, Shibuya-Ku
Tokyo 150
Tel: (02) 4008351
Fairchild Japan Corporation
Yotsubashi Chuo Bldg.
1-4-26, Shinmachi
Nishi-Ku, Osaka 550
Tel: 06-541-6138/9

10·5

United Kingdom

Fairchild Semiconductor Ltd.
230 High Street
Potters Bar
Hertsfordshire EN6 5BU
England
Tel: (0707) 51111

II

Fairchild
Sem icond uctor

Authorized
Distributors

Hamilton/Avnet Electronics
4940 Research Drive NW
Huntsville, Alabama 35805
Tel: 205-837-7210

Avnet Electronics
350 McCormick Avenue
Costa Mesa, California 92626
Tel: 714-754-6111 (Orange County)
213-558-2345 (Los Angeles)

Schweber Electronics
4910 Corporate Drive, Suite J
Huntsville, Alabama 35805
Tel: 205-895-0480

Hamilton/Avnet Electronics
3170 Pullman Avenue
Costa Mesa, California 92626
Tel: 714-641-1850

Arizona

Hamilton Electro Sales
10950 West Washington Blvd.
Culver City, California 90230
Tel: 213-558-2000

Alabama

Hamilton/Avnet Electronics
505 South Madison Drive
Tempe, Arizona 85281
Tel: 602-231-5100
Schweber Electronics
11049 North 23rd Drive, Suite 100
Phoenix, Arizona 85029
Tel: 602-997-4874
Wyle Distribution Group
17855 North Black Canyon Hwy.
Phoenix, Arizona 85023
Tel: 602-866-2888
California
Arrow Electronics
19748 Dearborn Street
Chatsworth, California 91311
Tel: 818-701-7500

Arrow Electronics
9511 Ridgehaven Court
Viewriego, California 92123
Tel: 619-565-4800
Arrow Electronics
521 Weddell Avenue
Sunnyvale, California 94066
Tel: 406-745-6600
Arrow Electronics
2961 Dow Avenue
Tustin, California 92680
Tel: 714-838-5422

Hamilton/Avnet Electronics
4103 North Gate Blvd.
Sacramento, California 95834
Tel: 916-920-3150
Hamilton/Avnet Electronics
454!) View ridge Avenue
San Diego, California 92123
Tel: 619-571-7527
Hamilton Electro Sales
1361-B West 190th Street
Gardena, California 90248
Tel: 213-217-6700
Hamilton Electro Sales
9650 Desoto Avenue
Chatsworth, California 91311
Tel: 818-700-6500
Hamilton Electro Sales
3002 East G Street
Ontario, California 91764
Tel: 714-989-4602

United States
and Canada
Schweber Electronics
17822 Gillette Avenue
Irvine, California 92714
Tel: 714-863-0200
Schweber Electronics
21139 Victory Blvd.
Canoga Park, California 91303
Tel: 818-999-4702
Schweber Electronics
90 East Tasman Drive
San Jose, California 95134
Tel: 408-946-7171
'Sertech Laboratories
3170 Pullman Drive
Costa Mesa, California 92626
Tel: 714-754-0666
Wyle Distribution Group
7382 Lampson Street
Garden Grove, California 92641
Tel: 800-222-9953
Wyle Distribution Group
26677 Agoura Road
Calabassas, California 91302
Tel: 818-880-9001
Wyle Distribution Group
124 Maryland Street
EI Segundo, California 90245
Tel: 213-322-8100
Wyle Distribution Group
17872 Cowan Avenue
Irvine, California 92714
Tel: 714-863-9953

Hamilton/Avnet Electronics
1175 Bordeaux Drive
Sunnyvale, California 94066
Tel: 408-743-3355

Wyle Distribution Group
Military Product Division
18910 Teller Avenue
Irving, California 92715
Tel: 714-851-9953

Schweber Electronics
1225 West 190th Street, Suite 360
Gardena, California 90248
Tel: 213-327-8409

Wyle Distribution Group
11151 Sun Center Drive
Rancho Cordova, California 95670
Tel: 916-638-5282

'This distributor carries Fairchild die products only.
10-6

Fairchild
Semiconductor
California
Wyle Distribution Group
9525 Chesapeake Drive
San Diego, California 92123
Tel: 619-565-9171

Authorized
Distributors
Wyle Distribution Group
451 East 124th Avenue
Thornton, Colorado 80241
Tel: 303-457-9953

United States
and Canada
Schweber Electronics
317 South North Lake Blvd.
Suite 1024
Altamonte Springs, Florida 32701
Tel: 305-331-7555

Wyle Distribution Group
3000 Bowers Avenue
Santa Clara, California 95051
Tel: 408-727-2500

Connecticut
Arrow Electronics
12 Beaumont Road
Wallingford, Connecticut 06492
Tel: 203-265-7741

Zeus Components, Inc.
5236 Colodny Drive
Agoura Hills, California 91301
Tel: 818-889-3838

Hamilton/Avnet Electronics
Commerce Drive, Commerce Park
Danbury, Connecticut 06810
Tel: 203-797-2800

Zeus Components, Inc.
1580 Old Oakland Road
Suite C 205
San Jose, California 95131
Tel: 408-998-5121

Schweber Electronics
Finance Drive
Commerce Industrial Park
Danbury, Connecticut 06810
Tel: 203-792-3500

Zeus Components, Inc.
22700 Savi Ranch Pkwy.
Yorba Linda, California 92686
Tel: 714-921-9000

Florida
Arrow Electronics
350 Fairway Drive
Deerfield Beach, Florida 33441
Tel: 305-429-8200

Hamiiton/Avnet Electronics
5825-D Peachtree Corners East
Norcross, Georgia 30092
Tel: 404-447-7500

Arrow Electronics
1530 Bottlebrush Drive NE
Palm Bay, Florida 32905
Tel: 305-725-1480

Schweber Electronics
2979 Pacific Drive, Suite E
Norcross, Georgia 30092
Tel: 404-449-9170

Colorado
Arrow Electronics
1390 South Potomac Street
Suite 136
Aurora, Colorado 80012
Tel: 303-696-1111
Hamilton/Avnet Electronics
710 Wooton Road
Colorado Springs, Colorado 80913
Tel: 303-637-0055
Hamilton/Avnet Electronics
8765 East Orchard Rd., Suite 706
Englewood, Colorado 80111
Tel: 303-740-1000
Schweber Electronics
8955 East Nichols Avenue
Englewood, Colorado 80112
Tel: 303-799-0258

*Chip Supply
7725 North Orange Blossom Trail
Orlando, Florida 32610
Tel: 305-298-7100
Hamilton/Avnet Electronics
6801 NW 15th Way
Ft. Lauderdale, Florida 33309
Tel: 305-971-2900
Hamilton/Avnet Electronics
3197 Tech Drive, North
St. Petersburg, Florida 33702
Tel: 813-576-3930
Hamilton/Avnet Electronics
6947 University Blvd.
Winter Park, Florida 32792
Tel: 305-628-3888

*This distributor carries Fairchild die products only.

10-7

Schweber Electronics
3665 Park Central Blvd. North
Building 6
Pompano Beach, Florida 33064
Tel: 305-977-7511
Zeus Components, Inc.
1750 West Broadway, Suite 114
Oviedo, Florida 32765
Tel: 305-365-3000
Georgia
Arrow Electronics
3155 Northwoods Pkwy., Suite A
Norcross, Georgia 30071
Tel: 404-449-8252

Illinois
Arrow Electronics
2000 Algonquin Road
Schaumburg, Illinois 60195
Tel: 312-397-3440
Hamilton/Avnet Electronics
1130 Thorndale Avenue
Bensenville, Illinois 60106
Tel: 312-860-7780
Schweber Electronics
904 Cambridge Road
Elk Grove Village, Illinois 60007
Tel: 312-364-3750

II

Fairchild
Semiconductor
Indiana
Arrow Electronics
2495 Directors Row, Suite H
Indianapolis, Indiana 46241
Tel: 317-243-9353
Hamilton/Avnet Electronics
485 Gradle Drive
Carmel, Indiana 46032
Tel: 317-844-9333
Iowa
Arrow Electronics
1930 St. Andrews NE
Cedar Rapids, Iowa 52402
Tel: 319-395-7230
Hamilton/Avnet Electronics
915 33rd Avenue SW
Cedar Rapids, Iowa 52404
Tel: 319-302-4757
Schweber Electronics
5270 North Park Place NE
Cedar Rapids, Iowa 52402
Tel: 319-373-1417
Kansas
Hamilton/Avnet Electronics
9219 Quivira Road
Overland Park, Kansas 66215
Tel: 913-888-8900
Schweber Electronics
10300 West 103rd Street
Suite 103
Overland Park, Kansas 66214
Tel: 913-492-2921
Kentucky
Hamilton/Avnet Electronics
1061-D Newtown Pike
Lexington, Kentucky 40511
Tel: 609-259-1475
Maryland
Arrow Electronics
8300 Guilford Road
Suite H, Rivers Center
Columbia, Maryland 21046
Tel: 301-995-0003

Authorized
Distributors

United States
and Canada

Hamilton/Avnet Electronics
6822 Oak Hall Lane
Columbia, Maryland 21045
Tel: 301-995-3500

Arrow Electronics
3510 Roger B. Chaffee SE
Grand Rapids, Michigan 49508
Tel: 616-243-0912

Schweber Electronics
9330 Gaither Road
Gaithersburg, Maryland 20877
Tel: 301-840-5900

Hami Iton/Avnet Electronics
2215 29th Street SE, Space A5
Grand Rapids, Michigan 49508
Tel: 616-243-8805

Zeus Components, Inc.
8930 Rt. 108
Columbia, Maryland 21045
Tel: 301-997-1118

Hamilton/Avnet Electronics
32487 Schoolcraft
Livonia, Michigan 48150
Tel: 313-522-4700

Massachusetts
Arrow Electronics
One Arrow Drive
Woburn Massachusetts 01801
Tel: 617-933-8130

Schweber Electronics
12060 Hubbard Avenue
Livonia, Michigan 48150
Tel: 313-525-8100

Gerber Electronics
128 Carnegie Row
Norwood, Massachusetts 02062
Tel: 617-329-2400

Minnesota
Arrow Electronics
5230 West 73rd Street
Edina, Minnesota 55435
Tel: 612-830-1800

Hamilton/Avnet Electronics
10-D Centennial Drive
Peabody, Massachusetts 01960
Tel: 617-531-7430

Hamilton/Avnet Electronics
10300 Bren Road East
Minnetonka, Minnesota 55343
Tel: 612-932-0600

Schweber Electronics
25 Wiggins Avenue
Bedford, Massachusetts 01730
Tel: 617-275-5100

Schweber Electronics
7424 West 78th Street
Edina, Minnesota 55435
Tel: 612-941-5280

'Sertech Laboratories
10-B Centennial Drive
Peabody, Massachusetts 01960
Tel: 617-531-8673

Missouri
Arrow Electronics
2360 Schuetz Road
st. Louis, Missouri 63146
Tel: 314-567-6888

Zeus Components, Inc.
429 Marrett Road
Lexington, Massachusetts 02173
Tel: 617-863-8800
Michigan
Arrow Electronics
755 Phoenix Drive
Ann Arbor, Michigan 48104
Tel: 313-971-8220

'This distributor carries Fairchild die products only.
10-8

Hamilton/Avnet Electronics
13743 Shoreline Court East
Earth City, Missouri 63045
Tel: 314-344-1200
Schweber Electronics
502 Earth City Expressway
Earth City, Missouri 63045
Tel: 314-739-0526

Fairchild
Semiconductor
New Hampshire
Arrow Electronics
1 Perimeter Road
Manchester, NH 03103
Tel: 603-668-6968

Hamilton/Avnet Electronics
444 East Industrial Drive
Manchester, NH 03104
Tel: 603-624-9400
Schweber Electronics
Bedford Farms Building 2
Kilton and South River Roads
Manchester, N H 03102
Tel: 603-625-2250
New Jersey
Arrow Electronics
6000 Lincoln Drive East
Marlton, New Jersey 08053
Tel: 609-596-8000

Arrow Electronics
2 Industrial Road
Fairfield, New Jersey 07006
Tel: 201-575-5300
Hamilton/Avnet Electronics
10 Industrial Road
Fairfield, New Jersey 07006
Tel: 201-575-3390
Hamilton/Avnet Electronics
1 Keystone Avenue
Cherry Hill, New Jersey 08003
Tel: 609-424-0100
Schweber Electronics
18 Madison Road
Fairfield, New Jersey 07006
Tel: 201-227-7880
New Mexico
Arrow Electronics
2460 Alamo Avenue SE
Albuquerque, New Mexico 87106
Tel: 505-243-4566

Authorized
Distributors

United States
and Canada

Hamiiton/Avnet Electronics
2524 Baylor Drive SE
Albuquerque, New Mexico 87106
Tel: 505-765-1500

Summit Distributors, Inc.
916 Main Street
Buffalo, New York 14202
Tel: 716-887-2800

New York
Arrow Electronics
25 Hub Drive
Melville, New York 11747
Tel: 516-694-6800

Zeus Components, Inc.
100 Midland Avenue
Port Chester, New York 10573
Tel: 914-937-7400

Arrow Electronics
20 Oser Avenue
Hauppauge, New York 11787
Tel: 516-231-1000
Arrow Electronics
3375 Brighton-Henrietta Town
Line Road
Rochester, New York 14623
Tel: 716-275-0300
Hamiiton/Avnet Electronics
933 Motor Pkwy.
Hauppauge, New York 11788
Tel: 516-231-9800
Hamilton/Avnet Electronics
333 Metro Park
Rochester, New York 14623
Tel: 716-475-9130
Hamilton/Avnet Export
1065 Country Road, Suite 211A
Westbury, New York 11590
Hamilton/Avnet Electronics
103 Twin Oaks Drive
Syracuse, New York 13207
Tel: 315-437-2642
Schweber Electronics
Jericho Turnpike
Westbury, New York 11590
Tel: 516-334-7474
Schweber Electronics
3 Town Line Circle
Rochester, New York 14623
Tel: 716-424-2222

10-9

Zeus Components, Inc.
2110 Smithtown Avenue
Ronkonkoma, New York 11779
Tel: 516-737-4500
North Carolina
Arrow Electronics
5240 Greens Dairy Road
Raleigh, North Carolina 27604
Tel: 919-876-3132

Hamilton/Avnet
3510 Spring Forest Road
Raleigh, North Carolina 27604
Tel: 919·878-0819
Schweber Electronics
5285 North Blvd.
Raleigh, North Carolina 27604
Tel: 919-876-0000
Ohio
Arrow Electronics
7620 McEwen Road
Centerville, Ohio 45459
Tel: 513-435-5563

Arrow Electronics
6238 Cochran Road
Solon, Ohio 44139
Tel: 216-248-3990
Hamilton/Avnet Electronics
954 Senate Drive
Dayton, Ohio 45459
Tel: 513-433-0610
Hamilton/Avnet Electronics
4588 Emery Industrial Parkway
Warrensville Heights, Ohio 44128
Tel: 216-831-3500

III

Fairchild
Semiconductor
Ohio
Hamilton/Avnet Electronics

Authorized
Distributors

777 Brooksedge Blvd.
Westerville, Ohio 43081
Tel: 614-882-7004

Pennsylvania
Arrow Electronics
650 Seco Road
Monroeville, Pennsylvania 15146
Tel: 412-856-7000

Schweber Electronics
23880 Commerce Park
Beachwood, Ohio 44122
Tel: 216-464-2970

Schweber Electronics
2800 Liberty Avenue, Bldg. E
Pittsburgh, Pennsylvania 15222
Tel: 412-281-4150

Schweber Electronics
7865 Paragon Road
Dayton, Ohio 45459
Tel: 513-439-1800

Schweber Electronics
900 Business Center Drive
Horsham, Pennsylvania 19044
Tel: 215-441-0600

Oklahoma

Arrow Electronics
4719 South Memorial
Tulsa, Oklahoma 74145
Tel: 918-665-7700

Texas
Arrow Electronics
2227 West Braker Lane
Austin, Texas 78758
Tel: 215-835-4180

Hamilton/Avnet Electronics
12121 East 51st, Suite 102A
Tulsa, Oklahoma 74146
Tel: 918-252-7297

Arrow Electronics
3220 Commander Drive
Carrollton, Texas 75006
Tel: 214-380-6464

Schweber Electronics
4815 South Sheridan Road
Tulsa, Oklahoma 74145
Tel: 918-622-8000

Arrow Electronics
10899 Kinghurst, Suite 100
Houston, Texas 77099
Tel: 713-530-4700

Oregon
Arrow Electronics
10260 SW Nimbus, Suite M3
Tigard, Oregon 97223
Tel: 503-684-1690

Hamilton/Avnet Electronics
4850 West Braker Lane
Austin, Texas 78758
Tel: 512-837-8911

Hamilton/Avnet Electronics
6024 SW Jean Road
Building C, Suite 10
Lake Oswego, Oregon 97034
Tel: 503-635-8157
Wyle Distribution
5250 NE Elam Young Parkway
Suite 600
Hillsboro, Oregon 97124
Tel: 503-640-6000

Hamilton/Avnet Electronics
4850 Wright Road, Suite 190
Stafford, Texas 77477
Tel: 713-240-7733
Hamiiton/Avnet Electronics
2111 West Walnut Hill Lane
Irving, Texas 75062
Tel: 214-659-4111

United States
and Canada
Schweber Electronics
4202 Beltway Drive
Dallas, Texas 75234
Tel: 214-661-5010
Schweber Electronics
10625 Richmond, Suite 100
Houston, Texas 77042
Tel: 713-784-3600
Wyle Distribution Group
2120 West Braker Lane, Suite F
Austin, Texas 78758
Tel: 512-834-9957
Wyle Distribution Group
11001 South Wilcrest, Suite 105
Houston, Texas 77099
Tel: 713-879-9953
Wyle Distribution Group
1810 North Greenville Avenue
Richardson, Texas 75081
Tel: 214-235-9953
Zeus Components, Inc.
1800 North Glenville Road
Richardson, Texas 75081
Tel: 214-783-7010
Utah
Arrow Electronics
1515 West 2200 South
Salt Lake City, Utah 84119
Tel: 801-972-0404

Hamilton/Avnet Electronics
1585 West 2100 South
Salt Lake City, Utah 84119
Tel: 801-972-2800
Wyle Distribution Group
1959 South 4130 West, Unit B
Salt Lake City, Utah 84104
Tel: 801-974-9953
Virginia

Schweber Electronics
6300 La Calma Drive, Suite 240
Austin, Texas 78752
Tel: 512-458-8253

10-10

Arrow Electronics
8002 Discovery Drive
Richmond, Virginia 23285
Tel: 804-282-0413

Fairchild
Semiconductor

Authorized
Distributors

United States
and Canada

Washington

Canada

Arrow Electronics
14320 NE 21st Street
Bellevue, Washington 98005
Tel: 206-643·4800

Future Electronics
3220 5th Avenue NE
Calgary, Alberta T2A 5N1
Tel: 403-235·5325

Hamilton/Avnet Canada Ltd.
2550 Boundary Road, Suite 115
Burnaby,
British Columbia V5M 3C3
Tel: 604-437·6667

Ham'ilton/Avnet Electronics
14212 NE 21st Street
Bellevue, Washington 98005
Tel: 206·453-5844

Future Electronics
82 St. Regis Crescent North
Downsview, Ontario M3J 1Z3
Tel: 416-638·4771

Hamilton/Avnet Canada Ltd.
6845 Rexwood Road, Units 3-4-5
Mississauga, Ontario L4V 1R2
Tel: 416·677·7432

Wyle Distribution Group
1750 132nd Avenue NE
Bellevue, Washington 98005
Tel: 206-453-8300

Future Electronics
Baxter Center
1050 Baxter Road
Ottawa, Ontario K2C 3P2
Tel: 613·820·8313

Hamilton/Avnet Canada Ltd.
190 Colonnade Road
Nepean, Ontario K2E 7J5
Tel: 613·226·1700

Wisconsin

Arrow Electronics
200 North Patrick Blvd.
Brookfield, Wisconsin 53005
Tel: 414-792-0150
Hamilton/Avnet Electronics
2975 South Moorland Road
New Berlin, Wisconsin 53151
Tel: 414·784·4510
Schweber Electronics
150 Sunnyslope Road, Suite 120
Brookfield, Wisconsin 53005
Tel: 414·784·9020

Future Electronics
237 Hymus Blvd.
Pointe Claire (Montreal),
Quebec H9R 5C7
Tel: 514-694·7710
Future Electronics
1695 Boundary Road
Vancouver,
British Columbia V5K 4X7
Tel: 604-438·5545
Future Electronics
5312 Calgary Trail
Edmonton, Alberta P6H 4J8
Tel: 403·438·2858
Hamilton/Avnet Canada Ltd.
2816 21st Street NE
Calgary, Alberta T2E 6Z2
Tel: 403·250-9380

Hamiiton/Avnet Canada Ltd.
2795 Halpern Road
st. Laurent, Quebec H4S 1P8
Tel: 514·335-1000
Semad Electronics Ltd.
9045 Cote de Liesse, Suite 101
Dorval, Quebec H9P 2M9
Tel: 514·636·4614
Semad Electronics Ltd.
864 Lady Ellen Place
Ottawa, Ontario K1Z 5M2
Tel: 613·722·6571
Semad Electronics, Ltd.
85 Spy Court
Markham, Ontario L3R 4Z4
Tel: 416·475·8500

•
10·11

Notes

Notes

DC Characteristics for 'AC Family Devices
74AC
Symbol

Parameter

Conditions

Vee
(V)

54AC

TA=25°C
Typ

VIH

VIL

VOH

Minimum
High Level
Input Voltage
Maximum
Low Level
Input Voltage

VouT=0.1 V
or Vee-0.1 V

3.0
4.5
5.5

1.5
2.25
2.75

2.1
3.15
3.85

VouT=0.1 V
or Vee-0.1 V

3.0
4.5
5.5

1.5
2.25
2.75

lOUT = -50 p.A

3.0
4.5
5.5

2.99
4.49
5.49

0.9
1.35
1.65

2.1
3.15
3.85
0.9
1.35
1.65

2.9
4.4
5.4

2.9
4.4
5.4

2.9
4.4
5.4

V

2.56
3.86
4.86

2.4
3.7
4.7

2.46
3.76
4.76

V

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

V

3.0
4.5
5.5

0.32
0.32
0.32

0.4
0.4
0.4

0.37
0.37
0.37

V

5.5

±0.1

± 1.0

±1.0

p.A

VI (OE) = VIL, VIH
VI = Vee, VGND
5.5
Vo = Vee, GND

±0.5

± 10.0

±5.0

p.A

Minimum
High Level
Output Voltage ·VIN = VIL or VIH
-12 mA
10H
-24 mA
-24 mA

Maximum
Low Level
Output Voltage ·VIN = VIL or VIH
12 mA
10L
24 mA
24 mA

liN

Maximum
Input Leakage
Current

10Z

Maximum
3·5tate
Current

10LO
10HD

tMinimum
Dynamic
Output Current

Units

2.1
3.15
3.85
0.9
1.35
1.65

IOUT=50 p.A
VOL

74AC

TA=
TA=
-55° to +125°C -40° to +85°C
Guaranteed Limits

VI = Vee, GND

3.0
4.5
5.5
3.0
4.5
5.5

0.002
0.001
0.001

V

V

VOLO= 1.1 V

5.5

57

86

mA

VOHD=3.85 V

5.5

-50

-75

mA

• All outputs loaded; thresholds on input associated with output under test.
tMaximum test duration 20 ms, one output loaded at a time.

DC Characteristics for 'ACT Family Devices

Symbol

Parameter

Conditions

Vee
(V)

74ACT

54ACT

TA=25°C

-55° to + 125°C

Typ

74ACT

TA=
-40° to + 85°C
Guaranteed Limits
TA=

Units

VIH

Minimum
High Level
Input Voltage

VouT=O.l V
or Vcc-O.l V

4.5
5.5

1.5
1.5

2.0
2.0

2.0
2.0

2.0
2.0

V

VIL

Maximum
Low Level
Input Voltage

VouT=O.l V
or Vcc-0.1 V

4.5
5.5

1.5
1.5

0.8
0.8

0.8
0.8

0.8
0.8

V

lOUT = -50 p,A

4.5
5.5

4.49
5.49

4.4
5.4

4.4
5.4

4.4
5.4

V

4.5
5.5

0.0001

3.86
4.86

3.70
4.70

3.76
4.76

V

4.5
5.5

0.001
0.001

0.1
0.1

0.1
0.1

0.1
0.1

V

4.5
5.5

0.32
0.32

0.40
0.40

0.37
0.37

V

VOH

VOL

liN

Minimum
High Level

*VIN = VIL or VIH
IOH
-24 rnA
-24 rnA

lOUT = 50 p,A
Maximum
*VIN = VIL or VIH
Low Level
24 rnA
Output Voltage IOL
24 rnA
Maximum
Input

VI=VCC, GND

5.5

±0.1

± 1.0

± 1.0

p,A

loz

Maximum
3-State
Current

VI=VIL, VIH
Vo=Vcc, GND

5.5

±0.5

± 10.0

±5.0

p,A

ICCT

Maximum
Iccllnput

VI = Vcc-2.l V

5.5

1.6

1.5

rnA

VOLD = 1.1 V

5.5

57

86

rnA

VOHD=3.85 V

5.5

-50

-75

rnA

IOLD
IOHD

tMinimum
Dynamic
Output Current

0.6

• All outputs loaded; thresholds on input associated with output under test.
tMaxlmum test duration 2.0 ms, one output loaded at a time.



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