1987_Fairchild_Linear_Data_Book 1987 Fairchild Linear Data Book
User Manual: 1987_Fairchild_Linear_Data_Book
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F=AIRCHILD
A Schlumberger Company
1987
Linear Division
FAIRCHILD
Linear Data Book
A Schlumberger Company
1987 MAR 02
1987
Linear Division
Linear Division
313 Fairchild Drive. Mountain V_. CA 94043
(415) 962·4011 TWX MVLD
Introduction
The Linear Data Book includes the standard linear product
line plus our new Winchester Disk Drive circuits and
CLASIC™ standard cells. For ease of reference linear
products are organized by sections. For example, Operational Amplifiers, Voltage Regulators and Special Functions,
which includes Digital Signal Processing products such as
the pA212 Single Chip Modem.
Technical information and basic product specifications,
presented in data sheet form, include maximum ratings,
electrical characteristics, performance curves, and packaging information. For many products, typical applications and
test circuits are also included.
Package codes, included on each data sheet, indicate the
specific package(s) offered for the product. Detailed packaging information, listed by package code, is included in a
separate section. This section includes the new Surface
Mount Devices (SMD), such as the Small Outline integrated Circuit (SOIC) packages.
A section on Aerospace and Defense precedes the Hi-Rei
data sheets, which are organized in the same order as
Standard ReI. These data sheets indicate the conformance
to MIL-STD-883 and reference identical commercial data
sheets for more complete information.
Section 1 has an alpha-numeric product listing of all
Fairchild device numbers in the book. An explanation of
the part numbering system appears in the "Ordering Information" portion of Section 1. In addition, there is an industry cross reference keying Fairchild Linear Products to
direct replacement and function equivalents offered by major linear products manufacturers.
Other sections include information on Thermal Considerations and Quality. As added assistance, addresses and
phone numbers of worldwide Field Sales Offices and Authorized Distributors have been listed.
Information on any commercial or Hi-Rei linear product
may be obtained from a local sales office or by
contacting:
Fairchild Linear Products
Marketing Department MS 4-370
313 Fairchild Drive
Mt. View, CA. 94039
The specifications included in this data book are as current and correct as could reasonably be determined at
time of printing. Any errors noted by users, whether involving content or omissions can be directed to Linear Marketing at the above address.
iii
Table of Contents
Section 1
Alpha Numeric Index ......................... .1-3
Industry Cross Reference Guide ........ 1-11
Ordering Information ........................ 1·17
Section 7
Operational Amplifiers
MA101A, MA201A, MA301A ....................................7-3
MA101, MA201 .................................................. 7-11
Section 2
MA108/A, MA208/A, MA30B/A .............................. 7-14
Thermal Considerations ......................2-3
MA124, MA224, MA324, MA2902 ............................ 7-22
Section 3
MA1458, MA1558 ............................................... 7-27
Testing, Quality and Reliability ............ .3-3
MA 148, MA248, MA34B ........................................ 7-33
MA3303, MA3403, MA3503 ................................... 7-40
Section 4
CLASIC™ ......................................... .4-3
MA4136 ........................................................... 7-50
MA709 ............................................................ 7-58
Section 5
Disk Drives
MA714 ............................................................ 7-67
pA24H80 ...........................................................5-3
MA715 ............................................................ 7-80
MA2460, MA2461 .................................................5-5
MA725 ............................................................ 7-88
pA2470 ........................................................... 5-13
MA741 .......................................................... 7-100
pA248X, MA248XR Series ................................... 5-23
MA747 .......................................................... 7-109
MA2480 ........................................................... 5-33
MA748 .......................................................... 7-118
pA2490 ........................................................... 5-36
MA759, MA77000 ............................................. 7-128
MA2580 ........................................................... 5-51
MA771 .......................................................... 7-140
MA772 .......................................................... 7-148
Section 6
Voltage Regulators
MA774 .......................................................... 7-155
MA105, MA305, MA305A, MA376 .............................6-3
MA776 .......................................................... 7-162
MA117, MA217, MA317 ........................................ 6-10
MA798 .......................................................... 7-172
MA138, MA238, MA338 ........................................ 6-16
MA 150, MA250, MA350 ........................................ 6-23
Section 8
MA 1524A, MA2524A, MA3524A ............................. 6-36
Comparators
MA111, MA311 ....................................................8-3
MA431A .......................................................... 6-42
MA139, MA239, MA339, MA2901, MA3302 ................ 8-11
MA494 ............................................................ 6-48
MA6685 ........................................................... 8-21
MA723 ............................................................ 6-55
MA6687 ...................................................•....... 8-30
MA78G, MA79G ................................................. 6-63
MA685 ............................................................ 8-32
MA78LOO Series ................................................ 6-72
MA687, MA687A ................................................ 8-42
MA78MG, MA79MG ............................................ 6-81
MA710 ............................................................ 8-44
MA78MOO Series ............................................... 6-91
MA711 ............................................................ 8-51
MA78S40 ....................................................... 6-103
MA760 ............................................................ 8-56
MA7800 Series ................................................ 6-111
MA79MOO Series ............................................. 6-126
Section 9
MA7900 Series ................................................ 6-135
Interface
MA1488 ..................................•..........................9-3
MA1489, MA1489A ...............................................9-7
MA26LS31 ....................................................... 9-11
v
Table of Contents
Section 9
Interface (Cont.)
pA556 ................................ :; ........................ 11·28
pA592 .......................................................... 11·34
1AA26LS32 ....................................................... 9·14
pA3486 ........................................................... 9·17
pA733 .......................................................... 11·39
pA3467 ...............•............•.•..............·.............. 9·21
pA7392 ......................................................... 11-45
pA55107A, pA75107A, pA75107B, pA75108B ......... 9·25
FSP100 ......................................................... 11·51
pA55110A, pA75110A ........................................ 9-34
F2224, F2212 ................................................. 11·63
pA75150 ................................................... ;·..... 9·40
F30S54, F30S57 ............................................. 11-64
pA75154 .................................. ; .......•.............. 9-45
F30S64, F30S67 ............................................. 11·76
pA75450/60170 Series .........•.................•....•...... 9·52
F3054, F3057 ................................................. 11·89
pA75491, pA75492 ....................................... , .... 9·68
pAV22 ......................................................... 11·102
pA9614 ........................................................... 9·72
1AA212A, pA212AT .................... '...................... 11·103
pA9615 ........................................................... 9·79
pA212K ..................•.................................... 11·115
pA96172, pA96174 ............................................ 9-87
pA96173, pA96175 ............................................ 9·92
Section 12
Aerospece and Defense .................. 12·3
Section 13
HI-Rei Voltage Regulators
pA96176 ......................................................... 9·97
pA96177, pA96178 .......................................... 9·105
pA9636A ....................................................... 9·113
pA10SQB ........................................................ 13·3
pA9637A ....................................................... 9·118
pA109QB ........................................................ 13·7
pA9638 ......................................................... 9·122
pA117HQB .................................................... 13·11
pA9639A ....................................................... 9·126
pA117KQB .................................................... 13·15
pA9640 (1AA26S10) .......................................... 9·130
pA138QB ...................................................... 13-19
pA9643 ......................................................... 9·135
pA 150QB ...................................................... 13·20
pA9645 (pA3245) ............................................ 9·139
pA431QB ...................................................... 13·21
pA9665, pA9666, pA9667, pA9668 ..................... 9·143
pA494QB ...................................................... 13-22
pA9679 ......................................................... 9·149
,iA723QB ...................................................... 13-23
pA78M05QB .................................................. 13-27
Section 10
Data Acquisition
pA78M06QB .................................................. 13-31
DAC08 ............................................................ 10·3
pA78M08QB .................................................. 13·35
DAC1408/1508 Series ...................................... 10·12
pA78M12QB .................................................. 13-39
pA565........................................................... 10-17
,iA78M1SQB .................................................. 13-43
pA571 .......................................................... 10·25
pA78M24QB .................................................. 13·47
pA9650 ......................................................... 10·34
pA78S400B ................................................... 13·51
pA7805QB ..................................................... 13·55
SectIon 11
Special Functions
pA7812QB ..................................................... 13·59
1AA2240 .................................... , ...................... 11·3
pA7815QB ..................................................... 13·63
pA3046, pA3086 ............................................. 11·13
pA79M05QB .................................................. 13·67
pA3680 ......................................................... 11·19
pA79M08QB .................................................. 13·71
pA555 .......................................................... 11·22
pA79M12QB .................................................. 13·75
vi
Table of Contents
Section 13
Section 15
Hi-Rei Voltage Regulators (Cont.)
Hi-Rei Comparators
j.tA79M150B .................................................. 13-79
1/A1110B ........................................................ 15-3
j.tA79050B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-83
1/A1390B ........................................................ 15-7
j.tA79120B ..................................................... 13-87
1/A21110B ..................................................... 15-11
j.tA79150B ..................................................... 13-91
1/A7100B ...................................................... 15-15
j.tA 1524AOB ................................................... 13-95
1/A7110B ...................................................... 15-19
I/A7600B
Section 14
...................................................... 15-23
Hi-Rei Operational Amplifiers
Section 16
j.tA101AOB ...................................................... 14-3
Hi-Rei Interface
j.tA1010B ........................................................ 14-7
1/A55107AOB ................................................... 16-3
j.tA108AOB .................................................... 14-11
1/A55110AOB ................................................... 16-7
j.tA1080B ...................................................... 14-15
1/A55452BOB ................................................. 16-11
j.tA1100B ...................................................... 14-19
1/A96140B ....................................................• 16-15
j.tA1240B ...................................................... 14-23
1/A96150B ..................................................... 16-19
j.tA 1480B ...................................................... 14-27
1/A9616HOB ..................................................• 16-23
j.tA15580B ..................................................... 14-31
1/A96220B .................................•................... 16-27
j.tA2101AOB ................................................... 14-35
1/A96240B ...........•........................................• 16-31
j.tA21 01 OB ..................................................... 14-39
1/A96250B ..........................................•.......... 16-35
j.tA2108AOB ................................................... 14-43
j.tA96270B ..................................................... 16-39
j.tA21080B ..................................................... 14-47
1/A9636AOB ................................................... 16-43
j.tA41360B . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14-51
1/A9637AOB ................................................... 16-47
j.tA7020B ...................................................... 14-55
1/A96380B .•................................................... 16-51
1/A709AOB .................................................... 14-59
1/A9639AOB ................................................... 16-55
1/A7090B ..............................•....................... 14-63
1/A96670B .•..............•.................................... 16-59
1/A7140B ...................................................... 14-67
1/A26LS310B ................................................. 16-63
1/A7150B ....................................•................. 14-71
1/A26LS320B ................................................. 16-64
1/A725AOB .................................................... 14-75
1/A7250B ....................................•................. 14-79
Section 17
1/A741AOB .................................................... 14-83
Hi-Rei Data Acquisition
1/A571S0B ...................................................... 17-3
1/A7410B ...................................................... 14-87
1/A747AOB .................................................... 14-91
Section 18
Hi-Rei Special Functions
1/A7470B ...................................................... 14-95
1/A30450B ....................................................... 18-3
1/A7590B ...................................................... 14-99
1/A5550B ........................................................ 18-7
1/A771BOB .................................................... 14-103
1/A7330B ...................................................... 18-11
j.tA772BOB ................................................... 14-107
1/A774BOB ................................................... 14-111
Section 19
Package Outlines ........................... 19-3
Section 20
Sales Offices and Distributors .......... 20-3
1/A7760B ..•.................................................. 14-115
vii
Alpha Numeric Index
FAIRCHILD
A Schlumberger Company
Device
Description
Page
Device
Description
Page
flA24H80FC
flA24H80RC
!lA24H80SC
!lA24H80TC
!lA26LS31DC
flA26LS31 DMQB
flA26LS31 LMQB
IlA26LS31PC
IlA26LS32DC
IlA26LS32DMQB
!lA26LS32LMQB
IlA26LS32PC
!lA78GU1C
IlA78L05ASC
IlA78L05AWC
!lA78L05AWV
IlA78L09AWC
IlA78L09AWV
IlA78L 12AWC
/lA78L 12AWV
/lA78L15AWC
/lA78L 15AWV
J.LA 78L62A WC
J.LA78L62AWV
/lA78L82AWC
J.LA78L82AWV
J.LA78M05HC
,uA78M05HM
/lA78M05HMQB
J.LA 78M05LMQB
,uA78M05UC
J.LA78M06HC
!lA78M06HM
IlA78M06HMQB
!lA78M06UC
!lA78M08HC
!lA78M08HM
!lA78M08HMQB
flA78M08UC
flA78M12HC
flA78M12HM
flA78M12HMQB
!lA78M12LMQB
!lA78M12UC
!lA78M15HC
IlA78M15HM
IlA78M15HMQB
IlA78M15LMQB
IlA78M15UC
IlA78M24HC
IlA78M24HM
!lA78M24HMQB
/lA78M24UC
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Interface
Hi-Rei Interface
Hi-Rei Interface
Interface
Interface
Hi-Rei Interface
Hi-Rei Interface
Interface
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
5-3
5-3
5-3
5-3
9-11
16-63
16-63
9-11
9-14
16-64
16-64
9-14
6-63
6-72
6-72
6-72
6-72
6-72
6-72
6-72
6-72
6-72
6-72
6-72
6-72
6-72
6-91
6-91
13-27
13-27
6-91
6-91
6-91
13-31
6-91
6-91
6-91
13-35
6-91
6-91
6-91
13-39
13-39
6-91
6-91
6-91
13-43
13-43
6-91
6-91
6-91
13-47
6-91
flA78MGU1C
flA78S40DC
flA78S40DM
flA78S40DMQB
flA78S40PC
flA78S40PV
flA79GU1C
IlA79M05AHC
IlA79M05AUC
IlA79M05HM
IlA79M05HMQB
IlA79M05LMQB
!lA79M08AHC
IlA79M08AUC
IlA79M08HM
IlA79M08HMQB
IlA79M12AHC
IlA79M12AUC
IlA79M12HM
IlA79M12HMQB
IlA79M12LMQB
IlA79M15AHC
!lA79M15AUC
IlA79M15HM
IlA79M15HMQB
IlA79M15LMQB
IlA79MGU1C
IlA101ADMQB
IlA 101AFMQB
IlA101AHM
IlA101AHMQB
IlA101DMQB
IlA101FMQB
IlA101HM
IlA101HMQB
IlA105HM
IlA105HMQB
IlA 108ADMQB
IlA 108AFMQB
IlA108AHM
IlA 108AHMQB
!lA108DMQB
!lA108FMQB
IlA108HM
IlA108HMQB
!lA109HMQB
J.LA 109KMQB
!lA110HMQB
!lA111DMQB
IlA111FMQB
IlA111HM
!lA111HMQB
!lA111RMQB
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Voltage Regulators
Hi-Rei Voltage Regulators
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Voltage Regulators
Hi-Rei Voltage Regulators
Hi-Rei Operational Amplifiers
Hi-Rei Comparators
Hi-Rei Comparators
Comparators
Hi-Rei Comparators
Hi-Rei Comparators
6-81
6-103
6-103
13-51
6-103
6-103
6-63
6-126
6-126
6-126
13-67
13-67
6-126
6-126
6-126
13-71
6-126
6-126
6-126
13-75
13-75
6-126
6-126
6-126
13-79
13-79
6-81
14-3
14-3
7-3
14-3
14-7
14-7
7-11
14-7
6-3
13-3
14-11
14-11
7-14
14-11
14-15
14-15
7-14
14-15
13-7
13-7
14-19
15-3
15-3
8-3
15-3
15-3
1-3
Alpha Numeric Index
Device
Description
Page
Device
Description
Page
/lA117HMQB
/lA117KM
/lA117KMQB
/lA124DM
/lA124DMQB
/lA124FMQB
/lA124LMQB
/lA138KM
/lA138KMQB
/lA139DM
1.lA139DMQB
I.lA 139FMQB
I.lA 139LMQB
/lA148DM
/lA148DMQB
/lA150KM
/lA150KMQB
1.lA201AHV
1.lA201HC
1.lA201TC
1.lA208AHV
/lA208HV
1.lA212ADC
/lA212ADV
1.lA212APC
1.lA212ATDC
1.lA212ATDV
/lA212ATPC
/lA212ATQC
/lA217KV
/lA217UV
/lA224DV
/lA224PV
/lA238KV
1.lA239DV
1.lA239PV
1.lA239SV
1.lA248DV
1.lA248PV
1.lA250KV
1.lA301AHC
1.lA301ASC
1.lA301ATC
1.lA305AHC
1.lA305HC
/lA308AHC
/lA308ASC
1.lA308ATC
1.lA308HC
1.lA308SC
1.lA308TC
1.lA311HC
1.lA311SC
Hi-Rei Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Voltage Regulators
Hi-Rei Voltage Regulators
Comparators
Hi-Rei Comparators
Hi-Rei Comparators
Hi-Rei Comparators
Operational Amplifiers
Hi-Rei Operational Amplifiers
Voltage Regulators
Hi-Rei Voltage Regulators
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Special Functions
Special Functions
Special Functions
Special Functions
Special Functions
Special Functions
Special Functions
Voltage Regulators
Voltage Regulators
Operational Amplifiers
Operational Amplifiers
Voltage Regulators
Comparators
Comparators
Comparators
Operational Amplifiers
Operational Amplifiers
Voltage Regulators
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Voltage Regulators
Voltage Regulators
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Comparators
Comparators
13-11
6-10
13-15
7-22
14-23
14-23
14-23
6-16
13-19
8-11
15-7
15-7
15-7
7-33
14-27
6-23
13-20
7-3
7-11
7-11
7-14
7-14
11-103
11-103
11-103
11-103
11-103
11-103
11-103
6-10
6-10
7-22
7-22
6-16
8-11
8-11
8-11
7-33
7-33
6-23
7-3
7-3
7-3
6-3
6-3
7-14
7-14
7-14
7-14
7-14
7-14
8-3
8-3
/lA311TC
/lA317KC
/lA317UC
/lA324DC
/lA324PC
/lA324SC
/lA338KC
/lA338UC
/lA339DC
1.lA339PC
1.lA339SC
/lA348DC
1.lA348PC
1.lA350KC
1.lA350UC
1.lA376TC
1.lA431ASC
/lA431AWC
/lA431AWV
/lA431LMQB
/lA431RMQB
/lA494DC
/lA494DMQB
/lA494LMQB
/lA494PC
1.lA494PV
1.lA555HMQB
1.lA555RMQB
1.lA555SC
1.lA555TC
1.lA556PC
1.lA565JJC
1.lA565KJC
/lA565SJM
/lA565TJM
1.lA571JJC
/lA571KJC
/lA571SDMQB
/lA571SJM
/lA592DC
/lA592DM
1.lA592PC
1.lA592SC
1.lA592TC
/lA685DM
/lA685DV
/lA685HM
/lA685HV
1.lA685PV
1.lA685SV
1.lA687ADM
1.lA687ADV
/lA687APV
Comparators
Voltage Regulators
Voltage Regulators
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Voltage Regulators
Voltage Regulators
Comparators
Comparators
Comparators
Operational Amplifiers
Operational Amplifiers
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Special Functions
Hi-Rei Special Functions
Special Functions
Special Functions
Special Functions
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Hi-Rei Data Acquisition
Data Acquisition
Special Functions
Special Functions
Special Functions
Special Functions
Special Functions
Comparators
Comparators
Comparators
Comparators
Comparators
Comparators
Comparators
Comparators
Comparators
8-3
6-10
6-10
7-22
7-22
7-22
6-16
6-16
8-11
8-11
8-11
7-33
7-33
6-23
6-23
6-3
6-42
6-42
6-42
13-21
13-21
6-48
13-22
13-22
6-48
6-48
18-7
18-7
11-22
11-22
11-28
10-17
10-17
10-17
10-17
10-25
10-25
17-3
10-25
11-34
11-34
11-34
11-34
11-34
8-32
8-32
8-32
8-32
8-32
8-32
8-42
8-42
8-42
1-4
Alpha Numeric Index
Device
Description
Page
Device
Description
Page
jlA687DM
jlA687DV
jlA687PV
jlA702DMQB
MA702FMQB
jlA702HMQB
MA709ADMQB
MA709AFMQB
MA709AHM
MA709AHMQB
jlA709DMQB
jlA709FMQB
jlA709HC
jlA709HM
jlA709HMQB
jlA709PC
jlA709SC
jlA709TC
jlA710DC
jlA710DM
jlA710DMQB
jlA710FMQB
jlA710HC
jlA710HM
jlA710HMQB
jlA710PC
jlA711DC
jlA711DM
jlA711DMQB
jlA711FMQB
jlA711HC
jlA711HM
jlA711HMQB
jlA711PC
jlA714AHM
jlA714EHC
jlA714HC
jlA714HM
jlA714HMQB
MA714LHC
jlA714LSC
jlA714LTC
jlA714SC
jlA714TC
jlA715HC
jlA715HM
jlA715DM
jlA715DC
jlA715HMQB
jlA723DC
jlA723DM
jlA723DMQB
jlA723HC
Comparators
Comparators
Comparators
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Comparators
Comparators
Hi-Rei Comparators
Hi-Rei Comparators
Comparators
Comparators
Hi-Rei Comparators
Comparators
Comparators
Comparators
Hi-Rei Comparators
Hi-Rei Comparators
Comparators
Comparators
Hi-Rei Operational Amplifiers
Comparators
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
8-42
8-42
8-42
14-55
14-55
14-55
14-59
14-59
7-58
14-59
14-63
14-63
7-58
7-58
14-63
7-58
7-58
7-58
8-44
8-44
15-15
15-15
8-44
8-44
15-15
8-44
8-51
8-51
15-19
15-19
8-51
8-51
15-19
8-51
7-67
7-67
7-67
7-67
14-67
7-67
7-67
7-67
7-67
7-67
7-80
7-80
7-80
7-80
14-71
6-55
6-55
13-23
6-55
jlA723HM
jlA723HMQB
jlA723LMQB
jlA723PC
MA723SC
jlA725AHM
jlA725AHMQB
jlA725EHC
jlA725HC
MA725HM
jlA725HMQB
jlA725TC
MA733DC
jlA733DM
MA733DMQB
jlA733FMQB
jlA733HC
jlA733HM
MA733HMQB
MA733PC
jlA733SC
jlA741ADMQB
jlA741AFMQB
jlA741AHM
jlA741AHMQB
Voltage Regulators
Hi-Rei Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Special Functions
Special Functions
Hi-Rei Special Functions
Hi-Rei Special Functions
Special Functions
Special Functions
Hi-Rei Special Functions
Special Functions
Special Functions
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational. Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
6-55
13-23
13-23
6-55
6-55
7-88
14-75
7-88
7-88
7-88
14-79
7-88
11-39
11-39
18-11
18-11
11-39
11-39
18-11
11-39
11-39
14-83
14-83
7-100
14-83
7-100
14-83
14-87
7-100
7-100
7-100
14-87
7-100
7-100
14-87
7-100
7-100
14-87
7-100
7-100
7-109
14-91
14-91
7-109
14-91
7-109
7-109
14-95
7-109
7-109
14-95
7-109
7-109
jlA741 ARM
jlA741ARMQB
jlA741DMQB
jlA741EHC
jlA741ERC
jlA741 ETC
jlA741FMQB
jlA741HC
jlA741HM
jlA741HMQB
jlA741RC
jlA741RM
jlA741RMQB
jlA741SC
jlA741TC
jlA747ADM
jlA747ADMQB
jlA747AFMQB
jlA747AHM
jlA747AHMQB
jlA747DC
jlA747DM
MA747DMQB
jlA747EDC
jlA747EHC
jlA747FMQB
MA747HC
MA747HM
1-5
---------.~
Alpha Numeric Index
Device
Description
Page
Device
Description
Page
pA747HMQB
pA747PC
pA747SC
pA748HC
pA748HM
pA748RC
pA748SC
pA748TC
pA759HC
pA759HM
pA759HMQB
pA759U1C
pA760DC
pA760DM
pA760DMQB
pA760HC
pA760HM
pA760HMQB
pA760RC
pA760RM
pA771ARC
pA771ARM
pA771ASC
pA771ATC
pA771BHMQB
pA771BRC
pA771BRM
pA771BRMQB
pA771BSC
pA771BTC
pA771LRC
pA771LSC
pA771LTC
pA771RC
pA771SC
pA771TC
pA772ARC
pA772ARM
pA772ASC
pA772ATC
pA772BHMQB
pA772BRC
pA772BRM
pA772BRMQB
pA772BSC
pA772BTC
pA772LRC
pA772LSC
pA772LTC
pA772RC
pA772SC
pA772TC
pA774BDC
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Comparators
Comparators
Hi-Rei .Comparators
Comparators
Comparators
Hi-Rei Comparators
Comparators
Comparators
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational AmplifierS
Operational Amplifiers
Operational Amplifiers
14-95
7-109
7-109
7-118
7-118
7-118
7-118
7-118
7-128
7-128
14-99
7-128
8-56
8-56
15-23
8-56
8-56
15-23
8-56
8-56
7-140
7-140
7-140
7-140
14-103
7-140
7-140
14-103
7-140
7-140
7-140
7-140
7-140
7-140
7-140
7-140
7-148
7-148
7-148
7-148
14-107
7-148
7-148
14-107
7-148
7-148
7-148
7-148
7-148
7-148
7-148
7-148
7-155
pA774BDM
pA774BDMQB
pA774BPC
pA774DC
pA774DM
pA774LDC
pA774LPC
pA774PC
pA774SC
pA776HC
pA776HM
pA776HMQB
pA776TC
pA798SC
pA798TC
pA1458CHC
pA1458CRC
pA1458CTC
pA1458HC
pA1458RC
pA1458SC
pA1458TC
pA1488DC
pA1488PC
pA1488SC
pA1489ADC
pA1489APC
pA1489DC
pA1489PC
pA1489SC
pA1524ADM
pA 1524ADMQB
pA1558HM
pA1558HMQB
pA1558RM
pA1558RMQB
pA2101ADMQB
pA2101DMQB
pA2108ADMQB
pA2108DMQB
pA2111DMQB
F2212DC
F2212PC
F2212QC
F2224DC
F2224PC
F2224QC
pA2240DC
pA2240PC
pA2460DC
pA2460QC
pA2461DC
pA2461QC
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Voltage Regulators
Hi-Rei Voltage Regulators
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Operational Amplifiers
Hi-Rei Comparators
Special Functions
Special Functions
Special Functions
Special Functions
Special Functions
Special Functions
Special Functions
Special Functions
Disk Drives
Disk Drives
Disk Drives
Disk Drives
7-155
14-111
7-155
7-155
7-155
7-155
7-155
7-155
7-155
7-162
7-162
14-115
7-162
7-172
7-172
7-27
7-27
7-27
7-27
7-27
7-27
7-27
9-3
9-3
9-3
9-7
9-7
9-7
9-7
9-7
6-36
13-95
7-27
14-31
7-27
14-31
14-35
14-39
14-43
14-47
15-11
11-63
11-63
11-63
11-63
11-63
11-63
11-3
11-3
5-5
5-5
5-5
5-5
1-6
•
Alpha Numeric Index
Device
Description
Page
Device
Description
Page
IlA2470DC
IlA2480FC
/lA2480TC
/lA2482DC
IlA2482RDC
/lA2484DC
/lA2484FC
/lA2484GC
/lA2484RDC
/lA2484RFC
/lA2484RGC
/lA2485DC
/lA2485FC
/lA2485GC
/lA2485RDC
/lA2485RFC
/lA2485RGC
/lA2486DC
/lA2486QC
/lA2486RDC
/lA2486RQC
/lA2488GC
/lA2488QC
/lA2488RGC
/lA2488RQC
/lA2490DC
/lA249OQC
/lA2524ADV
/lA2524APV
/lA2580DC
/lA2580FC
!lA2580SC
/lA2901DV
/lA2901PV
/lA2902PV
/lA3045DMQB
/lA3046PC
/lA3046SC
/lA3086DV
/lA3086PV
/lA3086SV
/lA3302DV
/lA3302PV
/lA3302SV
/lA3303DV
/lA3303PV
/lA3403DC
/lA3403PC
/lA3403SC
IlA3486DC
/lA3486PC
/lA3487DC
/lA3487PC
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Disk Drives
Voltage Regulators
Voltage Regulators
Disk Drives
Disk Drives
Disk Drives
Comparators
Comparators
Operational Amplifiers
Hi-Rei Special Functions
Special Functions
Special Functions
Special Functions
Special Functions
Special Functions
Comparators
Comparators
Comparators
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Interface
Interface
Interface
Interface
5-13
5-33
5-33
5-24
5-24
5-24
5-24
5-23
5-24
5-24
5-23
5-24
5-25
5-25
5-24
5-25
5-25
5-25
5-25
5-25
5-25
5-26
5-26
5-26
5-26
5-36
5-37
6-36
6-36
5-51
5-51
5-51
8-11
8-11
7-22
18-3
11-13
11-13
11-13
11-13
11-13
8-11
8-11
8-11
7-40
7-40
7-40
7-40
7-40
9-17
9-17
9-21
9-21
/lA3503DM
/lA3524ADC
/lA3524APC
/lA3680DV
/lA3680PV
/lA3680SV
/lA4136DC
/lA4136DMQB
/lA4136PC
/lA4136SC
/lA6685DM
/lA6685DV
/lA6685HM
/lA6685HV
/lA6685PV
/lA6685SV
/lA6687DM
/lA6687DV
/lA6687PV
/lA7392DV
/lA7392PV
/lA7805KC
/lA7805KM
/lA7805KMQB
/lA7805UC2
/lA7805UC
/lA7806KC
/lA7806KM
/lA7806UC
/lA7808KC
/lA7808KM
/lA7808UC
/lA7812KC
/lA7812KM
/lA7812KMQB
/lA7812UC2
/lA7812UC
/lA7815KC
/lA7815KM
/lA7815KMQB
/lA7815UC
/lA7818KC
/lA7818KM
/lA7818UC
/lA7824KC
/lA7824KM
/lA7824UC
/lA7885UC
/lA7905KC
/lA7905KM
/lA7905KMQB
/lA7905UC
/lA7908KC
Operational Amplifiers
Voltage Regulators
Voltage Regulators
Special Functions
Special Functions
Special Functions
Operational Amplifiers
Hi-Rei Operational Amplifiers
Operational Amplifiers
Operational Amplifiers
Comparators
Comparators
Comparators
Comparators
Comparators
Comparators
Comparators
Comparators
Comparators
Special Functions
Special Functions
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Voltage Regulators
Hi-Rei Voltage Regulators
Voltage Regulators
Voltage Regulators
7-40
6-36
6-36
11-19
11-19
11-19
7-50
14-51
7-50
7-50
8-21
8-21
8-21
8-21
8-21
8-21
8-30
8-30
8-30
11-45
11-45
6-111
6-111
13-55
6-111
6-111
6-111
6-111
6-111
6-111
6-111
6-111
6-111
6-111
13-59
6-111
6-111
6-111
6-111
13-63
6-111
6-111
6-111
6-111
6-111
6-111
6-111
6-111
6-135
6-135
13-83
6-135
6-135
1-7
Alpha Numeric Index
Device
Description
pA7908KM
Voltage Regulators
pA7908UC
Voltage Regulators
IlA7912KC
Voltage Regulators
pA7912KM
Voltage Regulators
pA7912KMQB
Hi-Rei Voltage Regulators
pA7912UC
Voltage Regulators
pA7915KC
Voltage Regulators
pA7915KM
Voltage Regulators
pA7915KMQB
Hi-Rei Voltage Regulators
pA7915UC
Voltage Regulators
pA9614DC
Interface
pA9614DM
Interface
pA9614DMQB
Hi-Rei Interface
pA9614FMQB
Hi-Rei .Interface
1lA9614LMQB
Hi-Rei Interface
pA9614PC
Interface
pA9615DC
Interface
pA9615DM
Interface
pA9615DMQB
Hi-Rei Interface
pA9615FMQB
Hi-Rei Interface
pA9615LMQB
Hi-Rei Interface
pA9615PC
Interface
pA9616HDMQB Hi-Rei Interface
pA9616HLMQB Hi-Rei Interface
pA9622DMQB
Hi-Rei Interface
pA9622FMQB
Hi-Rei Interface
pA9622LMQB
Hi-Rei Interface
pA9624DMQB
Hi-Rei Interface
pA9624FMQB
Hi-Rei .Interface
pA9625DMQB
Hi-Rei Interface
pA9625FMQB
Hi-Rei Interface
pA9627DMQB
Hi-Rei Interface
pA9636ARC
Interface
pA9636ARM
Interface
pA9636ARMQB Hi-Rei Interface
pA9636ATC
Interface
pA9637ARC
Interface
pA9637ARM
Interface
IlA9637ARMQB Hi-Rei Interface
pA9637ASC
Interface
pA9637ATC
Interface
pA9638RC
Interface
pA9638RM
Interface
pA9638RMQB
Hi-Rei Interface
pA9638SC
Interface
pA9638TC
Interface
pA9639ARMQB Hi-Rei Interface
pA9639ATC
Interface
1lA9640DC(26S10) Interface
1lA9640DM(26S10) Interface
IlA9640PC(26S10) Interface
1lA9643TC
Interface
pA9645DC(3245) Interface
Page
Device
Description
Page
6-135
6-135
6-135
6-135
13-87
6'135
6-135
6-135
13-91
6-135
9-72
9-72
16-15
16-15
16-15
9-72
9-79
9-79
16-19
16-19
16-19
9-79
16-23
16-23
16-27
16-27
16-27
16-31
16-31
16-35
16-35
16-39
9-113
9-113
16-43
9-113
9-118
9-118
16-47
9-118
9-118
9-122
9-122
16-51
9-122
9-122
16-55
9-126
9-130
9-130
9-130
9-135
9-139
pA9645PC(3245)
pA9665DC
pA9665PC
pA9666DC
pA9666DM
pA9666PC
pA9667DC
pA9667DM
pA9667DMQB
1lA9667PC
IlA9668DC
1lA9668DM
pA9668PC
1lA9679TC
IlA55107ADM
pA55107ADMQB
1lA55110ADM
1lA55110ADMQB
1lA55452BRMQB
pA75107ADC
pA75107APC
1lA75107ASC
pA75107BDC
pA75107BPC
pA75107BSC
pA75108BPC
pA75108BSC
1lA75110ADC
pA75110APC
1lA75110ASC
pA751SOPC
pA75150RC
pA75150SC
pA75150TC
pA75154DC
pA75154PC
pA75450DC
pA75450PC
1lA75451RC
pA7S451SC
pA75451TC
1lA75452SC
pA75452TC
pA75453RC
pA75453SC
pA75453TC
pA75461TC
pA75462TC
pA75471TC
pA75472TC
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Hi-Rei Interface
Interface
Interface
Interface
Interface
Interface
Interface
Hi-Rei Interface
Interface
Hi-Rei Interface
Hi-Rei Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Operational Amplifiers
9-139
9-143
9-143
9-143
9-143
9-143
9-143
9-143
16-59
9-143
9-143
9-143
9-143
9-149
9-25
16-3
9-34
16-7
16-11
9-25
9-25
9-25
9-25
9-25
9-25
9-25
9-25
9-34
9-34
9-34
9-40
9-40
9-40
9-40
9-45
9-45
9-53
9-53
9-56
9-56
9-56
9-59
9-59
9-62
9-62
9-62
9-56
9-59
9-56
9-59
9-68
9-68
7-128
pA75491PC
1lA75492PC
1lA77000U1C
1-8
•
Alpha Numeric Index
Device
Description
Page
Device
Description
/lA96172DC
/lA96172PC
/lA96173DC
/lA96173PC
/lA96174DC
/lA96174PC
/lA96175DC
/lA96175PC
/lA96176RC
/lA96176TC
/lA96177RC
/lA96177TC
/lA96178RC
/lA96178TC
/lA96501DC
/lA96502DC
/lA96503DC
/lAV22DC
/lAV22PC
/lAV22QC
DAC08CDC
DAC08CPC
DAC08DM
DAC08EDC
DAC08EPC
DAC1408ADC
DAC1408APC
DAC1408BDC
DAC1408BPC
DAC1408CDC
DAC1408CPC
DAC1508DM
F30S54DC
F30S57DC
F30S64DC
F30S67DC
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Interface
Data Acquisition
Data Acquisition
Data Acquisition
Special Functions
Special Functions
Special Functions
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Data Acquisition
Special Functions
Special Functions
Special Functions
Special Functions
9-87
9-87
9-92
9-92
9-87
9-87
9-92
9-92
9-97
9-97
9-105
9-105
9-105
9-105
10-34
10-34
10-34
11-102
11-102
11-102
10-3
10-3
10-3
10-3
10-3
10-12
10-12
10-12
10-12
10-12
10-12
10-12
11-64
11-64
11-76
11-76
F3054DC
F3057DC
FSP100DC
FSP100LC
10101
10102
10103
10104
10108
10201
10304
10403
10404
10701
10702
10703
10704
10706
10707
10708
10802
10901
11001
11004
11005
11201
11301
11302
11305
11501
11502
11503
11505
11506
11507
11-89
Special Functions
Special Functions
11-89
Special Functions
11-51
Special Functions
11-51
JAN Hi-Rei Operational Amplifiers14-83
JAN Hi-Rei Operational Amplifiers14-91
JAN Hi-Rei Operational Amplifiers14-3
JAN Hi-Rei Operational Amplifiers 14-11
JAN Hi-Rei Operational Amplifiers14-31
JAN Hi-Rei Voltage Regulators 13-23
JAN Hi-Rei Comparators
15-3
JAN Hi-Rei Interface
16-15
JAN Hi-Rei Interface
16-19
JAN Hi-Rei Voltage Regulators 13-7
JAN Hi-Rei Voltage Regulators 13-27
JAN Hi-Rei Voltage Regulators 13-39
JAN Hi-Rei Voltage Regulators 13-43
JAN Hi-Rei Voltage Regulators 13-55
JAN Hi-Rei Voltage Regulators 13-59
JAN Hi-Rei Voltage Regulators 13-63
JAN Hi-Rei Special Functions
18-3
JAN Hi-Rei Special Functions
18-7
JAN Hi-Rei Operational Amplifiers14-27
JAN Hi-Rei Operational Amplifiers14-51
JAN Hi-Rei Operational Amplifiers14-23
JAN Hi-Rei Comparators
15-7
JAN Hi-Rei Comparators
15-15
JAN Hi-Rei Comparators
15-19
JAN Hi-Rei Comparators
15-11
JAN Hi-Rei Voltage Regulators 13-67
JAN Hi-Rei Voltage Regulators 13-75
JAN Hi-Rei Voltage Regulators 13-79
JAN Hi-Rei Voltage Regulators 13-83
JAN Hi-Rei Voltage Regulators 13-87
JAN Hi-Rei Voltage Regulators 13-91
1-9
Page
Industry
Cross Reference Guide
F=AIRCHILO
A Schlumberger Company
Part
Number
Fairchild
Equivalent
AMD
715DC
715HC
715DM
715HM
723DC
723DM
723HC
723HM
723PC
725HC
725HM
733DC
733DM
733HC
733HM
741FM
741HC
741HM
741AFM
741AHM
741EHC
747DC
747DM
747HC
747HM
747PC
747ADM
747AHM
747EDC
747EHC
748HC
74BHM
AM1408L6
AM1408L7
AM1408LB
AM1508L8
AM26LS31DM
AM26LS31PC
AM26LS31DC
AM26LS32DC
AM26LS32PC
AM6685DL
AM6685DM
AM66B5HL
AM6685HM
AM6685LL
AM6687DL
AM6687DM
pA715DC
pA715HC
pA715DM
pA715HM
pA723DC
pA723DM
pA723HC
IlA723HM
pA723PC
pA725HC
pA725HM
IlA733DC
pA733DM
pA733HC
IlA733HM
pA741FM
pA741HC
pA741HM
pA741AFM
pA741AHM
pA741EHC
pA747DC
pA747DM
pA747HC
pA747HM
pA747PC
pA747ADM
pA747AHM
IlA747EDC
pA747EHC
pA74BHC
IlA74BHM
DAC1408ADC
DAC1408BDC
DAC140BCDC
DAC1508DM
pA26LS31DM
pA26LS31PC
pA26LS31DC
pA26LS32DC
pA26LS32PC
pA6685DV
IlA66B5DM
pA6685HV
pA6685HM
pA66B5SV
pA6687DV
pA6687DM
Part
Number
Fairchild
Equivalent
AMD (Cont.)
AM6B5DL
AM6B5DM
AM6B5HL
AM6B5HM
AM6B5LL
AM6B7DL
AM6B7DL
AM6B7DM
DAC-08CQ
DAC-OBEQ
LM101H
LM101AH
LM105H
LM108AH
LMlllH
LM124D
LM139D
LM201H
LM201AH
LM20BAH
LM224D
LM301AH
MC14BBL
MC14B9L
SN75107BJ
SN75107BN
SN75110J
SN75110N
SN75450BJ
SN75450BN
pA6B5DV
pA6B5DM
pA6B5HV
pA6B5HM
pA6B5SV
pA6B7DM
pA6B7DV
pA6B7DM
DACOBCDC
DAC08EDC
pAl01HM
pAl01AHM
pAl05HM
IlAl0BAHM
pAlllHM
pA124DM
pA139DM
pA201HC
pA201AHV
pA20BAHV
pA224DV
pA301AHC
pA14BBSC
pA14B9SC
pA75107BDC
pA75107BPC
IlA75110DC
pA75110PC
IlA75450BDC
pA75450BPC
INTERSIL
ICL10BLNTY
ICL741CHSPA
ICL741 MHSTY
LM101AH
LM105H
LM10BH
LM10BAH
LMlllH
LM124J
LM301AH
LM301AN
LM305H
LM308H
LM308AH
LM30BAN
NE555N
pAl0BHM
IlA741TC
pA741HM
pAl01AHM
pAl05HM
pAl0BHM
pAl08AHM
pAlllHM
pA124DM
pA301AHC
pA301ATC
pA305HC
pA30BHC
pA30BAHC
IlA30BATC
pA555TC
*Note
Not exact package replacement
1-11
Part
Number
INTERSIL (Cont.)
NE556N
pA723DC
pA723DM
pA723HC
pA723HM
pA723PC
pA733HC
pA733HM
pA741FM
pA741HC
pA741HM
pA741TC
pA74BHC
pA74BHM
pA74BTC
. MOTOROLA
AM26LS31DC
AM26LS31PC
AM26LS32DC
AM26LS32PC
DACOBEP
DACOBPC
LM101AH
LM105HM
LM108H
LM10BAH
LMlllH
LMlllJ-B
LMl17K
LM124J
LM139J
LM201AH
LM20BAH
LM217K
LM224J
LM239J
LM301AH
LM301AN
LM30BAH
LM30BAN
LM311H
LM311J-8
LM311N
LM317K
LM317T
LM324J
LM339J
Fairchild
Equivalent
pA556PC
pA723DC
pA723DM
pA723HC
pA723HM
pA723PC
pA733HC
pA733HM
pA741FM
pA741HC
pA741HM
pA741TC
pA748HC
pA74BHM
pA748TC
pA26LS31DC
IlA26LS31PC
pA26LS32DC
pA26LS32PC
DAC08EPC
DAC08CPC
pAl01AHM
pAl05HM
pAl08HM
pAl08AHM
IlAll1HM
pAl11RM
pA117KM
pA124DM
pA139DM
pA201AHV
pA208AHM
IlA217UV
pA224DV
IlA239DC
pA301AHC
IlA301ATC
pA308AHC
pA308ATC
IlA311HC
pA311RC
IlA311TC
pA317KC
pA317UC
IlA324DC
IlA339DC
•
Industry
Cross Reference Guide
Part
Number
Fairchild
Equivalent
MOTOROLA (Cont.)
LM348J
MA348 DC
LM348N
MA348PC
LM350K
MA350KC
LM350T
MA350UC
LM710CH
MA710HC
LM711CH
MA711HC
LM723CH
MA723HC
LM723CJ
MA723DC
LM741CH
MA741HC
LM741CN
MA741TC
LM2901N
MA2901PC
MC1408L7
DAC1408EDC
MC1408L8
DAC1408ADC
DAC1408CPC
MC1408P6
MC1408P7
DAC1408BPC
MC1408P8
DAC1408APC
MC1411P
MA9665PC
MC1412P
MA9666PC
MC1413P
MA9667PC
MC1416P
MA9668PC
p.A555TC
MC1455P1
MC1458CG
p.A1458CHC
MC1458CP1
MA1458CTC
MC1458CU
p.A1458CRC
MC1458G
MA1458HC
MC1458P1
MA1458TC
MC1458U
MA1458RC
MC1488L
MA1488DC
MC1488P
MA1488PC
MC1489L
MA1489DC
MC1489P
MA1489PC
MC1489AL
p.A1489ADC
MC1489AP
MA1489APC
DAC1508DM
MC1508L8
MC1558G
MA1558HM
MC1558U
MA1558RM
MC1709AG
MA709AHM
MC1709CP1
MA709TC
MC1709CP2
MA709PC
MC1709G
p.A709HM
MC1710CG
p.A710HC
MC1710CL
MA710DC
MC1710CP
MA710PC
MC1710G
MA710HM
MC1710L
MA710DM
MC1711CG
MA711HC
MC1711CL
MA711DC
MC1711CP
p.A711PC
Part
Number
Fairchild
Equivalent
MOTOROLA (Cont.)
MC1711G
MC1711 L
MC1723CG
MC1723CL
MC1723CP
MC1723G
MC1723L
MC1733G
MC1733L
MC1733CG
MC1733CL
MC1741CG
MC1741CP1
MC1741CU
MC1741G
MC1747CG
MC1747CL
MC1747CP2
MC1747G
MC1747L
MC1748CG
MC1748CP1
MC1748G
MC1776CG
MC1776CP1
MC1776G
MC3303P
MC3386P
MC3403L
MC3403P
MC3440AP
MC3443P
MC3456P
MC3458P1
MC3486CL
MC3486CN
MC3487CL
MC3487CN
MC3488AP
MC3558U
MC55107L
MC685B
MC75107L
MC75107P
MC75108CL
MC75108CP
MC75491P
MC75492P
p.A711HM
p.A711DM
MA723HC
MA723DC
p.A723PC
MA723HM
MA723DM
MA733HM
MA733DM
MA733HC
p.A733DC
p.A741HC
p.A741TC
p.A741RC
MA741HM
MA747HC
MA747DC
MA747PC
MA747HM
p.A747DM
MA748HC
p.A748TC
p.A748HM
MA776HC
MA776TC
p.A776HM
MA3303PV
MA3086PC
p.A3403DC
MA3403PC
p.A9640PC
MA9640PC
p.A556PC
MA798TC
p.A3486DC
p.A3486PC
MA3487DC
MA3487PC
p.A9636AT
p.A798TC
MA55107ADM
MA685HM
MA75107ADC
p.A75107APC
MA75108ADC
MA75108BPC
MA75491PC
p.A75492PC
·Note
Not exact package replacement
1-12
Part
Number
Fairchild
Equivalent
MOTOROLA (Cont.)
MC7805K
MC7805CK
MC7805CT
MC7812K
MC7812CK
MC7812CT
MC7815K
MC7815CK
MC7815CT
MC7818K
MC7818CK
MC7818CT
MC7824K
MC7824CK
MC7824CT
MC78L05ACP
MC78L12ACP
MC78L15ACP
MC78M05CG
MC78M05CT
MC78M06CG
MC78M06CT
MC78M08CG
MC78M08CT
MC78M12CG
MC78M12CT
MC78M15CT
MC78M24CT
MC7905CK
MC7905CT
MC7908CK
MC7908CT
MC7912CK
MC7912CT
MC7915CK
MC7915CT
NE592N
SE592F
SN75451BP
SN75452BP
SN75453BP
TL431CLP
TL494CJ
TL494CN
MA710HC
MA711HC
MA723DC
p.A723HC
MA7805KM
MA7805KC
MA7805UC
MA7812KM
MA7812KC
MA7812UC
MA7815KM
p.A7815KC
MA7815UC
p.A7818KM
p.A7818KC
p.A7818UC
p.A7824KM
MA7824KC
MA7824UC
MA78L05AWC
MA78L12AWC
MA78L15AWC
p.A78M05HC
p.A78M05UC
MA78M06HC
MA78M06UC
MA78M08HC
MA78M08UC
p.A78M12HC
p.A78M12UC
MA78M15UC
MA78M24UC
MA7905KC
MA7905UC
MA7908KC
p.A7908UC
p.A7912KC
MA7912UC
MA7915KC
p.A7915UC
MA592PC
MA592DM
p.A75451BTC
MA75452BTC
MA75453BTC
MA4131AWC
p.A494DC
p.A494PC
p.A710HC
p.A711 HC
MA723DC
MA723HC
Industry
Cross Reference Guide
Part
Number
Fairchild
Equivalent
MOTOROLA (Con!.)
IlA723PC
IlA723PC
IlA741HC
IlA741 HC
IlA741TC
1lA741TC
NATIONAL
COP431I
C0494M
DS1488J
DS1488N
DS1489AJ
DS1489AN
DS1489J
DS1489N
DS26LS31C
DS26LS31M
DS26LS32C
DS26LS32M
DS3486J
DS3486N
DS75107J
DS75107N
DS75108J
DS75108N
DS75150J-8
DS75150N
DS75154J
DS75154N
DS75450J
DS75450N
DS75491N
LF351A
LF351B
LF351
LF351 N
LF353A
LF353B
LF353
LF353N
LF374B
LF374
LM101AH
LM105H
LM108AH
LM108H
LM110H/883
LM111H
LM117H/883
LM124J
1lA431AWC
1lA494DC
IlA1488DC
IlA1488PC
IlA1489ADC
IlA1489APC
IlA1489DC
IlA1489PC
IlA26LS31 PC
IlA26LS31DC
IlA26LS32PC
IlA26LS32DC
IlA3486DC
IlA3486PC
IlA751 07 ADC
IlA75107APC
IlA75108ADC
IlA751 08APC
IlA75150SC
1lA75150PC
IlA75154DC
IlA75154PC
IlA75450DC
IlA75450PC
IlA75491PC
IlA771 A
IlA771B
IlA771
IlA771TC
IlA772A
IlA772B
IlA772
IlA772TC
IlA774B
IlA774
IlA101AHM
IlA105HM
1lA108AHM
IlA108HM
IlA110HMOB
IlA111HM
IlA117HMOB
IlA124DM
Fairchild
Equivalent
Part
Number
NATIONAL (Con!.)
LM139J
LM140K-5.0
LM140K-12
LM140K-15
LM201AH
LM208H
LM208AH
LM21 01 AD/883
1lA2108AD/833
1lA2108D/883
LH2111 D/883
LM224J
LM239J
LM301AH
LM301AN
LM305H
LM305AH
LM308AN
LM311J-8
LM311N
LM317K
LM317T
LM324J
LM324N
LM339J
LM339N
LM340K-5.0
LM340T-5.0
LM340K-6.0
LM340K-8.0
LM340K-12
LM340T-12
LM340K-15
LM340T-15
LM340K-18
LM340K-24
LM348J
LM348N
LM350K
LM3501
LM555CN
LM556CN
LM592JD
LM592D
LM709H
LM709CH
LM709CN
LM709CN-8
1lA139DM
1lA7805KM
IlA7812KM
1lA7815KM
IlA201AHM
IlA208HM
IlA208AHM
IlA21 01 ADMOB
IlA2108ADMOB
IlA2108DMOB
1lA2111 DMOB
IlA224DV
IlA239DC
IlA301AHC
IlA301ATC
1lA305HC
1lA305AHC
1lA308ATC
1lA311RC
1lA311TC
IlA317KC
1lA317UC
IlA324DC
IlA324PC
1lA339DC
1lA339PC
1lA7805KC
1lA7805UC
1lA7806KC
1lA7808KC
IlA7812KC
IlA7812UC
IlA7815KC
IlA7815UC
IlA7818KC
IlA7824KC
IlA348DC
1lA348PC
IlA350KC
IlA350UC
1lA555TC
1lA556PC
IlA592DM
IlA592D
IlA709HM
IlA709HC
IlA709PC
JlA709TC
*Note
Not exact package replacement
1-13
Part
Number
NATIONAL (Con!.)
LM710H
LM710CH
LM710CN
LM711H
LM711CH
LM711CN
LM723H
LM723J
LM723CH
LM723CJ
LM723CN
LM725H
LM725CH
LM725CN
LM733H
LM733CH
LM733CN
LM741H
LM741AH
LM741CH
LM741CJ
LM741CN
LM747H
LM747J
LM747AH
LM747AJ
LM747CH
LM747CJ
LM747CN
LM747EH
LM747EJ
LM748H
LM748CJ
LM748CH
LM748CN
LM760CH
LM1458H
LM1458J
LM1458N
LM1558H
LM1558J
LM2901N
LM2901J
LM3086N
LM3302J
LM3302N
LM7805CK
LM7805CT
Fairchild
Equivalent
1lA710HM
1lA710HC
1lA710PC
1lA711 HM
IlA711 HC
IlA711PC
IlA723HM
IlA723DM
IlA723HC
IlA723DC
1lA723PC
1l725HM
IlA725HC
IlA725TC
1lA733HM
1lA733HC
1lA733 PC
1lA741 HM
1lA741AHM
1lA741 HC
1lA741RC
IlA741TC
IlA747HM
IlA747DM
1lA747AHM
IlA747ADM
IlA747HC
1lA747DC
1lA747PC
IlA747EHC
1lA747EDC
1lA748HM
1lA748RC
1lA748HC
1lA748TC
1lA760HC
JlA1458HC
IlA1458RC
1lA1458TC
1lA1558HM
1lA1558RM
1lA2901PC
1lA2901DC
1lA3086PC
1lA3302DC
JlA3302PC
IlA7805KC
1lA7805UC
Industry
Cross Reference Guide
Part
Number
Fairchild
Equivalent
NATIONAL (Cont.)
LM7812CK
LM7812CT
LM7815CK
LM7815CT
LM78L05ACZ
LM78L12ACZ
LM78L15ACZ
LM78M05CP
LM78M12CP
LM78M15CP
LM7905CK
LM7905CT
LM7912CK
LM7912CT
LM7915CK
LM7915CT
LM7905CH
LM7912CH
LM7915CH
MC1508-8
/lA7812KC
/lA7812UC
/lA7815KC
/lA7815UC
/lA78L05AWC
/lA78L 12AWC
/lA 78L15AWC
J.LA78M05UC
/lA78M12UC
/lA78M15UC
/lA7905KC
J.LA7905UC
/lA7912KC
/lA7912UC
J.LA7915KC
J.LA7915UC
J.LA79M05AHC
J.LA79M12AHC
J.LA79M15AHC
DAC1508DM
PMI
DAC-08C
DAC-08E
DAC1408A-6
DAC1408A-7
DAC1408A-8
DAC1508A-8
OP-07J
OP-07CJ
OP-07EJ
PM108J
PM108AJ
PM139AY
PM139Y
PM208J
PM208AJ
PM339Y
PM339AY
PM725J
PM725CJ
PM725CP
PM741J
PM741CJ
PM741CZ
PM1458J
PM1458Z
PM1558J
DAC08CDC
DAC08EDC
DAC1408CPC
DAC1408BPC
DAC1408APC
DAC1508DM
J.LA714HM
J.LA714HC
J.LA714EHC
J.LA108HM
J.LA108AHM
J.LA139ADM
J.LA139DM
J.LA208HV
/lA208AHV
J.LA339DC
/lA339ADC
/lA725HM
/lA725HC
/lA725TC
/lA741HM
/lA741HC
/lA741RC
J.LA1458HC
/lA1458RC
/lA1558HM
Part
Number
Fairchild
Equivalent
Part
Number
Fairchild
Equivalent
SIGNETICS (Con!.)
PMI (Con!.)
PM1558Z
PM4136Y
PM4136CY
J.LA1558RM
/lA4136PC
/lA4136DC
SIGNETICS
LM101AH
LM111H
LM124F
LM139AF
LM201AN
LM224N
LM224F
LM301AN
LM324N
LM324F
LM339N
LM339F
LM2901F
LM2901N
MC1458FE
MC1458H
MC1458N
MC1488N
MC1488F
MC1489N
MC1489F
MC1489AN
MC1489AF
MC1558H
MC1558FE
MC3302N
MC3302F
MC3403CF
MC3403CN
NE5501
NE555D
NE555N
NE555N
NE556N
NE571F
NE592D
NE592F
SE592F
NE592N
NE592N8
SE555FE
ULN2001N
ULN2003F
/lA101AHM
/lA111HM
/lA124DM
/lA139ADM
/lA201AHM
/lA224PV
/lA224DV
/lA301ATC
J.LA324PC
/lA324DC
/lA339PC
J.LA339DC
J.LA2901DC
J.LA2901PC
/lA1458RC
/lA1458HC
/lA1458TC
/lA1488PC
/lA1488DC
/lA1489PC
/lA1489DC
/lA1489APC
/lA1489ADC
/lA1558HM
/lA1558RM
/lA3302PC
/lA3302DC
/lA3403DC
/lA3403PC
/lA9665PC
J.LA555SC
J.LA555TC
J.LA555PC
/lA556PC
/lA571JJC
/lA592SC
/lA592DC
/lA592DM
J.LA592PC
J.LA592TC
J.LA555RM
/lA9665PC
/lA9667DC
·Note
Not exact package replacement
1-14
ULN2003N
ULN2004F
ULN2004N
/lA723F
/lA723H
/lA723CD
/lA723CF
/lA723CH
/lA723CN
/lA733F
/lA733H
/lA733CF
/lA733CH
/lA733CN
/lA741 FE
/lA741CFE
/lA741CN
J.LA747F
J.LA747CF
J.LA747CN
J.LA9667 PC
J.LA9668 DC
/lA9668PC
J.LA723DM
J.LA723HM
J.LA723SC
J.LA723DC
J.LA723HC
/lA723PC
/lA733DM
/lA733HM
/lA733DC
J.LA733HC
J.LA733PC
J.LA741RM
J.LA741RC
J.LA741TC
J.LA747DM
J.LA747DC
J.LA747 PC
SILICON
GENERAL
SG101A
SG105T
SG111T
SG117K
SG124J
SG217P
SG224J
SG224N
SG301AM
SG301AT
SG305T
SG305AT
SG311M
SG311T
SG317K
SG317P
SG324J
SG324N
SG555M
SG556N
SG710J
SG710T
SG710CN
SG710CT
SG711J
/lA101AHM
J.LA105HM
/lA111 HM
/lA117KM
/lA124DM
/lA217UV
/lA224DV
/lA224PV
J.LA301ATC
J.LA301AHC
J.LA305HC
/lA305AHC
/lA311TC
/lA311 HC
/lA317KC
J.LA317UC
J.LA324DC
/lA324PC
/lA555TC
/lA556PC
J.LA710DM
J.LA71 OHM
J.LA710PC
/lA710HC
/lA711DM
•
Industry
Cross Reference Guide
Part
Number
Fairchild
Equivalent
SILICON
GENERAL (Cont.)
SG711T
SG711CJ
SG711CN
SG711CT
SG723CJ
SG723CT
SG723J
SG723T
SG723CN
SG733J
SG733T
SG733CJ
SG733CN
SG733CT
SG741F
SG741T
SG741CM
SG747J
SG747T
SG747CJ
SG747CN
SG747CT
SG748T
SG748CM
SG748CT
SG1488J
SG1489AJ
SG1558T
SG2001J
SG2002J
SG2003J
SG3086J
SG3086N
SG3302J
SG3302N
SG75450BJ
SE75450BN
SG7805K
SG7805CK
SG7805CP
SG7808K
SG7808CK
SG7808CP
SG7812K
SG7812CK
SG7812CP
SG7815K
Part
Number
Fairchild
Equivalent
SILICON
GENERAL (Cont.)
J.lA711HM
J.lA711DC
J.lA711PC
J.lA711HC
J.lA723DC
J.lA723HC
J.lA723DM
J.lA723HM
J.lA723PC
J.lA733DM
J.lA733HM
J.LA733DC
J.lA733PC
J.lA733HC
J.LA741FM
J.LA741HM
J.lA741TC
J.LA747DM
J.LA747HM
J.lA747DC
J.LA747 PC
J.LA747HC
J.LA748HM
J.lA748TC
J.LA748HC
J.lA1488DC
J.lA1489ADC
J.lA1558HM
J.lA9665PC
J.lA9666DC
J.LA9667DC
J.lA3086DC
J.lA3086PC
J.LA3302DC
J.lA3302PC
J.LA75450BDC
J.LA75450BPC
J.lA7805KM
J.lA7805KC
J.lA7805UC
J.lA7808KM
J.lA7808KC
J.lA7808UC
J.lA7812KM
J.lA7812KC
J.lA7812UC
J.lA7815KM
SG7815CK
SG7815CP
SG7818K
SG7818CK
SG7818CP
SG7824K
SG7824CK
SG7824CP
SG7905K
SG7905CK
SG7905CP
SG7908K
SG7908CK
SG7908CP
SG7912K
SG7912CK
SG7912CP
SG7915K
SG7915CK
SG7915CP
SG75450BCN
SG75451BCM
SG75451BCY
SG75452BCM
SG75453BCM
SG75453BCY
SG75461CM
SG75462CM
SILICON SYSTEMS
J.LA2482RDC
J.lA2484RDC
J.lA2486RDC
TEXAS
INSTRUMENTS
AM26S10CJ
AM26S10CN
TC101AJ
LM105L
LM124J
LM139J
LM148J
TC201AJG
LM348J
LM348N
LM376P
J.lA9640DC
J.lA9640PC
J.lA101AHM
J.lA105HM
J.lA124DM
J.lA139DM
J.lA148DM
J.lA201AHV
J.lA348DC
J.lA348PC
J.lA376TC
"Note
Not exact package replacement
1-15
Fairchild
Equivalent
TEXAS
INSTRUMENTS (Cont.)
J.LA7815KC
J.lA7815UC
J.lA7818KM
J.lA7818KC
J.LA7818UC
J.lA7824KM
J.lA7824KC
J.LA7824UC
J.lA7905KM
J.LA7905KC
J.LA7905UC
J.LA7908KM
J.lA7908KC
J.lA7908UC
J.lA7912KM
J.lA7912KC
J.lA7912UC
J.lA7915KM
J.lA7915KC
J.lA7915UC
J.LA75450BPC
J.lA75451BTC
J.lA75451BRC
J.LA75452BTC
J.lA75453BTC
J.lA75453BRC
J.lA75461TC
J.lA75462TC
SS1117-2
SS1117-4
SS1117-6
Part
Number
MC1558JG
NE555P
NE556N
RC4136D
RC4136J
RC4136N
SA555D
SA555P
SE556N
SN55107AJ
SN55110AJ
SN75107AJ
SN75107AN
SN75107BJ
SN75107BN
SN75108BN
SN75110AJ
SN75110AN
SN75114J
SN75114N
SN75115J
SN75115N
SN75150N
SN75150P
SN75154J
SN75154N
SN75188J
SN75188N
SN75189J
SN75189N
SN75189AJ
SN75189AN
SN75450BN
SN75451BJG
SN75451BP
SN75452BP
SN75453BJG
SN75453BP
SN75461P
SN75462P
SN75471P
SN75472P
SN75491N
SN75492N
TLC555MJG
TLC555CD
TLC555CP
J.lA1558RM
J.lA555TC
J.lA556PC
J.lA4136SC
J.lA4136DC
J.LA4136PC
J.LA555SC
J.lA555TC
J.LA556PC
J.lA55107ADM
J.lA55110ADM
J.lA75107ADC
J.lA75107APC
J.lA75107BDC
J.lA75107BPC
J.lA75108BPC
J.lA75110ADC
J.lA75110APC
J.lA9614DC
J.lA9614PC
J.lA9615DC
J.lA9615PC
J.LA75150PC
J.lA75150TC
J.lA75154DC
J.lA75154PC
J.lA1488DC
J.lA1488PC
J.lA1489DC
J.LA1489PC
J.lA1489ADC
J.lA1489APC
J.LA75450BPC
J.LA75451 BRC
J.lA75451BTC
J.lA75452BTC
J.lA75453BRC
J.lA75453BTC
J.lA75461TC
J.lA75462TC
J.lA75471TC
J.lA75472TC
J.LA75491PC
J.lA75492PC
J.lA555RM
J.LA555SC
J.lA555TC
Industry
Cross Reference Guide
Part
Number
Fairchild
Equivalent
Part
Number
Fairchild
Equivalent
Part
Number
Fairchild
Equivalent
TEXAS
INSTRUMENTS (Cont.)
TEXAS
INSTRUMENTS (Cont.)
TEXAS
INSTRUMENTS (Cont.)
TL071ACO
TL071ACP
TL071 BCD
TL071BCP
TL071CD
TL071CP
TL071MJGB
TL072ACD
TL072ACP
TL072BCD
TL072BCP
TL072CD
TL072CP
TL072MJGB
TL074ACN
TL074CN
TL074MJB
TL081ACJG
TL081ACP
TL081 BCJG
TL081BCP
TL081CJG
TL081CP
TL431CLP
TL494CN
TL494CJ
TL494MJ
ULN2001AN
ULN2002AJ
ULN2002AN
ULN2003AJ
ULN2003AN
ULN2004AJ
ULN2004AN
/1A709MJ
/1A709MU
/1A709AMJ
/1A709AMU
/1A709CP
I1A710CJ
I1A710CN
/1A710MJ
/1A711CJ
/1A711CN
/1A711 MJ
/1A711MV
/1A723CJ
/1A723CN
/1A723MJ
/1A733CJ
I1A733CN
/1A733MJ
/1A741CJG
I1A741CD
I1A741CP
/1A741MJ
/1A741MJG
/1A741MU
/1A747C
/1A747CN
/1A747MJ
I1A748CP
I1A2240CJ
/1A2240CN
/1A7805CKC
/1A7808CKC
/1A7812CKC
/1A7815CKC
/1A7818CKC
/1A7824CKC
/1A7885CKC
/1A78L05CLP
I1A78L12CLP
I1A 78L15CLP
/1A78M05CKC
/1A 78M06CKC
/1A78M08CKC
/1A78M12CKC
/1A78M15CKC
/1A78M24CKC
/1A7905CKC
I1A7908CKC
/1A7912CKC
/1A7915CKC
/1A79M05CKC
/1A79M08CKC
/1A79M12CKC
/1A 79M 15CKC
I1A9637AC
9614CJ
9614CN
9615CJ
9615CN
/1A771 BSC
/1A771 BTC
/1A771ASC
/1A771ATC
/1A771SC
/1A771TC
/1A771 BRMOB
/1A772BSC
I1A772BTC
I1A772ASC
/1A772ATC
/1A772SC
/1A772TC
/1A772BRMOB
/1A774BPC
/1A774PC
/1A774BDMOB
/1A771 BRC
I1A771BTC
I1A771 ARC
/1A771ATC
/1A77LRC
I1A77LTC
11A431AWC
/1A494PC
/1A494DC
/1A494DM
/1A9665PC
/1A9666DC
/1A9666PC
/1A9667DC
/1A9667PC
/1A9668DC
/1A9668PC
/1A709DM
/1A709FM
I1A709ADM
/1A709AFM
/1A709TC
/1A710DC
/1A710PC
/1A710DM
I1A711 PC
I1A711PC
/1A711DM
/1A711 FM
I1A723DC
/1A723PC
/1A723DM
/1A733DC
I1A733PC
/1A733DM
/1A741RC
/1A741SC
/1A741TC
/1A741DM
/1A741RM
/1A741FM
/1A747DC
/1A747PC
/1A747DM
/1A748TC
*Note
Not exact package replacement
1-16
/1A2240DC
/1A2240PC
I1A7805UC
I1A7808UC
/1A7812UC
/1A7815UC
/1A7818UC
/1A7824UC
I1A7885UC
/1A78L05AWC
/1A78L12AWC
/1A78L15AWC
I1A78M05UC
I1A78M06UC
/1A78M08UC
/1A78M12UC
/1A78M15UC
/1A78M24UC
/1A7905UC
/1A7908UC
/1A7912UC
/1A7915UC
/1A79M05AUC
/1A79M08AUC
/1A79M12AUC
/1A79M15AUC
/1A9637RC
I1A9614DC
/1A9614PC
/1A9615DC
/1A9615PC
Ordering Information
F=AIRCHILO
A Schlumberger Company
Standard ReI. and Hi-ReI. Ordering Code
Device Identification
Three basic units of information are contained in the ordering code.
J.LA741
T
C
All Fairchild standard
catalog linear circuits
will be marked as
shown in the following
example.
Device Type
PackageType
Temperature Range
Device Type
~A7100C
of Data Code
JAN Part Ordering Code*
This group of alpha numeric characters defines the device
including functional and electrical characteristics, alpha suffixes are added to further delineate electrical options.
l
J
M 385101
101 01 B G
c
JAN Designator
Cannot be marketed with "J"
unless qualified on Part I
or Part II of the QPL
General +--_ _ _ _ _ _--'
Procurement Spec
Refers to Detail Spec +--_ _ _ _--'
101 Op Amps
102 Voltage Regulators
103 Comparators
104 Interface
106 Voltage Followers
107 Positive Fixed Voltage Regulators
108 Transistor Arrays
109 Timers
110 Quad Op Amps
112 Voltage Comparator
113 D to A Converter
115 Negative Fixed Voltage Regulators
117 Positive Adjustable Voltage Regulators
118 Negative Adjustable Voltage Regulators
119 Low Power, Low Noise, Bi-Fet Op Amps
Defines Device Type +--_ _ _ _ _ _ _-'
Package Type
One alpha suffix represents the basic package style.
D = Dual In-Line (Hermetic, Ceramic)
F = Flatpak (Hermetic)
G = Flatpak (Brazed)
H = Metal package
J = Dual In-Line (Side Brazed)
K = Metal Power Package (TO-3)
L = LCC Leadless Ceramic Chip Carrier
P = Dual In-Line (Molded)
= PLCC Plastic Leaded Chip Carrier
R = 8 Lead Dual In-Line (Hermetic, Ceramic)
S = SOIC Small Outline Integrated Circuits
T = 8 Lead Dual In-Line (Molded)
U = Power Package (Molded, TO-220)
W = Molded Package (TO-92 Outline)
o
Different outlines exist within each package style to accommodate various die sizes and number of leads. Specific dimensions for each package can be found in the
Package Outline section of this catalog, listed by online
code. These specific codes are referenced on each data
sheet.
Processing Level +--_ _ _ _ _ _ _ _ _ _---'
S
B
Temperature Range
Package Type +--_ _ _ _ _ _ _ _ _ _ _ _ _--'
A 14-lead 1/4 x 1/4 Flatpak
B 14-lead 114 x Flatpak
C 14-lead 114 x 3/4 Dip
D 14-lead 1/4 x 3/8 Flatpak
E 16-lead 114 x 718 Dip
F 16-lead 1/4 x 3/8 Flatpak
G 8-lead Can
H la-lead 114 x 114 Flatpak
I la-lead Can
J 24-lead 1/2 x 1 1/4 Dip
K 24-lead 3/8 x 5/8 Flatpak
L 24-lead 3/8 x 112 Flatpak
X 3-lead TO-5 Can
Y 2-lead TO-3 Can
Z 24-lead 114 x 3/8 Flatpak
Z 20 Terminal LCC
Lead Finish +--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
A Hot Solder Dip
B Tin Plate
C Gold Plate
X Any Finish Above
One alpha suffix represents one of the following three basic temperature grades in common use. Exact values and
conditions are specified on the device data sheets.
C = Commercial
O°C to + 70°C
M = Extended
-55°C to + 125°C
v = Industrial
-25°C to +85°C
-40°C to +85°C
aB/883 Processing
A two alpha suffix of OB indicates conformance to Class
"B" process requirements of MIL-STD-883 to Fairchild MIL
temperature range data sheet electricals.
Examples
J.LA 741 FM This number code indicates a J.LA741 Operational Amplifier in a flatpak with military temperature rating capability.
J.LA725EHC This number code indicates a J.LA725 Instrumentation Operational Amplifier, electrical option E, in a
metal package with a commercial temperature rating capability.
• See Section 12 Aerospace & Defense
1-17
Thermal Considerations
FAIRCHILD
A Schlumberger Company
Thermal Management
{}JA = {}JC
An effective and safe performance of various IC or transistor packages is attained by proper heat removal and maintenance of their junction temperatures below the specified
maximum values. In order to achieve efficient thermal
management, the user must rely upon important parameters, provided by the manufacturer (junction-to-ambient and
junction-to-case thermal resistances and maximum operating junction temperature).
+ {}CS + {}SA
TJ-TC
Tc-Ts
Ts-TA
Po
Po
Po
=---+---+--TJ - TA
= - - (OC/W)
Po
Where
Po
= Power dissipation
Measurements
Thermal resistance is considered as the temperature gradient between two reference pOints in the package or the
total system, per unit of power dissipation through the device encapsulated in the package, under steady state conditions. It is expressed as {}xy, in degrees centigrade per
Watt (OC/W) - where X and Yare the two reference
pOints.
Substrate or isolation diode method is used to determine
the device junction temperature, TJ. The other reference
temperatures are measured using thermocouples attached
to required points. There are standard procedures available
for {}JA and {}JC measurements, details of which could be
referred from MIL-STD-883 Method 1012, SEMI-STD Document #1341 and 1342.
Equations
A simple thermal circuit for a semiconductor device in
equilibrium is shown in Figure 1. The reference pOints in
this case are
J - Device junction
C - Package case
S-Heat sink
A-Ambient
The package thermal characterization is best performed
using 'Test Chips'. The chip specification conforms to
SEMI-STD NO. G 32-86. These chips consist of transistors
or resistor strips (as the heat source) covering 85 percent
of the active device area. Temperature sensing diodes and
associated metallization runs are electrically isolated from
the heat source. Such a test chip is considered a basic
cell. Heat dissipating through a large size chip could be
simulated by using an array of such basic cells. The device, and thus the package, is heated while being powered. The diode forward voltage (VF) is simultaneously
monitored using an independent low current source. TJ is
determined from a VF vs TJ calibration curve. This very
reliable thermal resistance data could be correlated with
the die size (= heat dissipating area).
Figure 1 Simplified Thermal Circuit
...-_ _ _
-_
: : : - - - - . TJ JUNCTION TEMPERATURE
POWER (PI
9JC JUNCTION·TO·CASE
THERMAL RESISTANCE
TC CASE TEMPERATURE
HEAT
SOURCE
lies
CASE·TO·SINK
THERMAL RESISTANCE
TS SINK TEMPERATURE
The thermal resistance measurement of specific device
plus package combination differs from the above described
test chip method. In this case, a substrate diode is selected for determining TJ. Special electrical equipment is required for pulsing power in the forward direction of the
device under test while measuring voltage drop across the
substrate diode in between the pulses. This measurement
technique has its shortcomings, since it is more prone to
experimental errors.
BsA SINK·TO·AMBIENT
THERMAL RESISTANCE
' - - - - - -_ _..... TA AMBIENT TEMPERATURE
The power dissipation, which is analogous to current flow
in electrical terms, is caused by a heat source similar to a
voltage source. Temperature is analogous to voltage potential and thermal resistance to ohmic resistance. The
junction-to-ambient thermal resistance, {}JA, is then expressed as a sum of thermal resistances in series, as
shown:
In order to maintain the junction temperature below a specific level, at times it is necessary to use an external heat
sink. The following is devoted to selection of proper heat
sinks, with special relevance to voltage regulators.
2-3
Thermal Considerations
TJ Max- TA
8JA(tol) = 8JC + 8c s + 8SA =
Thermal Considerations Using Voltage Regulators
as an Example
-=...:.="-.....:..;
Po
Case-to-sink and sink-to-ambient thermal resistance information on commercially available heat sinks is normally
provided by the heat sink manufacturer. A summary of
some commercially available heat sinks is shown in Table
1. However, if a chassis or other conventional surface is
used as a heat sink, Figure 2 can be used as a guide to
estimate the required surface area.
Heat Sink Requirements
When is a heat sink necessary, and what type of a heat
sink should one use? The answers to these questions depend on reliability and cost requirements. Heat sinking is
necessary to keep the operating junction temperature (TJ)
of the regulator below the specified maximum value. Since
semiconductor reliability improves as operating junction
temperature is lowered, a reliability/cost compromise is
usually made in the device design.
How to Choose a Heat Sink - Example
Determine the heat sink required for a regulator which has
the following system requirements:
Thermal characteristics of voltage regulator chips and
packages determine that some form of heat sinking is
mandatory whenever the power disSipation exceeds the
following.
Operating
Maximum
Maximum
Maximum
0.67 W for the TO-39 package
0.69 W for the TO-92 package
1.56 W for the Mini Batwing and Power Watt (similar to
TO-202) packages
1.8 W for the TO-220 package
2.8 W for the TO-3 package
ambient temperature range: O°C to 60°C
junction temperature: 125°C
output current: 800 mA
input to output differential: 10 V
The TO-220 package is sufficient (lower cost, better thermal resistance).
8JC = 5°C/W maximum (from data sheet)
TJ-TA
8JA(tol) = 8JC + 8cs + 8SA = ---p[)"
125-60
8cs + 8sA = - - - - 5 = 3.13°C/W
0.8 x 10
at 25°C ambient or lower power levels at ambients above
25°C.
To choose or design a heat sink, the designer must determine the following regulator parameters.
Assuming 8cs = 0.13°C/W then 8SA = 3°C/W
Figure 2 Heat Sink Material Selection Guide
Po Max - Maximum· power dissipation: (VI - Va) 10 + VI IQ
TA - Ambient temperature the regulator will encounter during operation.
TJ Max - Maximum operating junction temperature, specified by the manufacturer.
8Jc, 8JA - Junction-to-case and junction-to-ambient thermal
resistance values, also specified by the regulator manufacturer.
8c s -'- Case-to-heat sink thermal resistance which, for large
packages, can range from about 0.2°C/W to about
1°C/W depending on the quality of the contact between the package and the heat sink.
8SA - Heat sink-to-ambient thermal resistance, specified by
heat sink manufacturer.
, SURFACE AREA
{BOTH SIDES OF THE HEAT SINK}
SQUARE INCHES
11II111II~lIIiII~lilllillIllII'llIIpl~ 1/i/llllllillIlIIlIllllllllIlllIlIllIlIlllIIl.~" "11111111111
3
4
:
3/32"
7
6
8
8JA
5
44
3
3 2
2.;·5
2
5
4
5
3
4
2 1.5
2.5
3
1
1
2
I
I
7
5
6
4
6
3
4
2.6
3.5
2
2.5 2
3
lilIlIIlIiIUlllllilhlllllllilllllljllllllllll!lllljI!/i1iil
1lIlIllIlIllIlIliiii/ililliillliiii 1I II I I I I I I 1 I I I II
77
3/32"
~...;.;;"---'-'
65
III Ii 1111111111/1111111111111111111 III I I I I I I I II I ill
7
THICKNESS
405060 80
1IIIIIIIIiI""IIIIII"IiIIl"lliilllllll!II!1 I I:
3/32"
PD Max =
6
6
7
3/'S"
TJMax-TA
76
7
3/32"
Maximum permissible dissipation without a heat sink is determined by
202530
1"11/1 111 1"11111111'1111111111111111"111111"1111"11111 I !
THICKNESS
3/'."
15
luuhliiluuhlillilUlilill!lilll! III II IIi! II I I I I I I I ! I Ii I
3;16"
THICKNESS
8 10
/1111/1111/1111111111111111111111111111111111/111111111111111111 I I I 1I II
3/16"
THICKNESS
6 6
66
55
4
4
;.5
32 . 5 2.6 2 2
!ililil "I Ii II 1111 III I II I III II! II II!I I 1111 I II I II ill
COPPER;
HORIZONTALLY.
MOUNTED
COPPER,
VERTICALLY MOUNTED
ALUMINUM.
HORIZONTAllYMOUNTED
ALUMINUM,
VERTICAllY MOUNTED
THERMAL RESISTANCE IN °CjW
If the device dissipation Po exceeds this figure, a heat
sink is necessary. The total required thermal resistance
may then be calculated.
To determine either area required or thermal resistance of a given area,
draw a vertical line between the lop (or area) line down
interest_
2-4
10
the malerial of
Thermal Considerations
This thermal resistance value can be achieved by using
either 22 square inches of 3/16 inch thick vertically
mounted aluminum (Figure 2) or a commercial heat sink
(Table 1).
In some applications, especially with negative regulators, it
is desirable to electrically insulate the regulator case from
the heat sink. Hardware kits for this purpose are commer·
cially available for such packages as the TO·3 and TO·
220. They generally consist of a 0.003 to 0.005 inch thick
piece of mica or bonded fiberglass to electrically isolate
the two surfaces, yet provide a thermal path between
them. As expected, the thermal resistance will increase
but, as in the direct metal·to·metal jOint, some improve·
ment can be realized by using thermal lubricant on each
side of the mica.
Tips for Better Regulator Heat Sinking
Avoid placing heat·dissipating components such as power
resistors next to regulators.
When using low dissipation packages such as TO·5,
TO·39, and TQ.92, keep lead lengths to a minimum and
use the largest possible area of the printed board traces
or mounting hardware to provide a heat dissipation path
for the regulator.
If the regulator is mounted on a heat sink with fins, the
most efficient heat transfer takes place when the fin is in
a vertical plane, as this type of mounting forces the heat
transfer from fin to air in a combination of radiation and
convection.
When using larger packages, be sure the heat sink sur·
face is flat and free from ridges or high spots. Check the
regulator package for burrs or peened·over corners. Re·
gardless of the smoothness and flatness of the package
and heat sink contact, air pockets between them are un·
avoidable unless a lubricant is used. Therefore, for good
thermal conduction, use a thin layer of thermal lubricant
such as Dow Corning DC·340, General Electric 662 or
Thermacote by Thermalloy.
If it is necessary to bend any of the regulator leads, han·
die them carefully to avoid straining the package. Further·
more, lead bending should be restricted since repeated
bending will fatigue and eventually break the leads.
Table 1 Heat Sink Selection Guide
This list is only representative. No attempt has been made to provide a complete list of all heat sink manufacturers. All
values are typical as given by manufacturer or as determined from characteristic curves supplied by manufacturer.
DBA Approx. ("C/W)
To-3 Packages
0.4 (9" length)
0.4 - 0.5 (6" length)
0.56-3.0
0.6 (7.5" length)
0.7-1.2 (5-5.5"
length)
1.0 - 5.4 (3" length)
1.9
2.1
2.3-4.7
4.2
4.5
4.8-7.5
5-6
5-10
Manufacturer3 and Type
DSA Approx. (OC/W)
5.6
5.9 -10
6
6.4
6.5-7.5
8
8.1
8.8
9.5
9.5-10.5
9.8 -13.9
10
11
Thermalloy (Extruded)
6590 Series
Thermalloy (Extruded)
6660, 6560 Series
Wakefield 400 Series
Thermalloy (Extruded)
6470 Series
Thermalloy (Extruded) 6423,
6443, 6441, 6450 Series
Thermalloy (Extruded)
6427, 6500, 6123, 6401,
6403, 6421, 6463, 6176,
6129, 6141, 6169, 6135,
6442 Series
IERC E2 Series (Extruded)
IERC E1, E3 Series (Extruded)
Wakefield 600 Series
IERC HP3 Series
Staver V3·5·2
Thermalloy 6001 Series
IERC HP3 Series
Thermalloy 6013 Series
Manufacturer3 and Type
Staver V3·3·2
Wakefield 680 Series
Wakefield 390 Series
Staver V3·7·224
IERC UP Series
Staver V1·5
Staver V3·5
Staver V3·7·96
Staver V3·3
IERC LA Series
Wakefield 630 Series
Staver V1·3
Thermalloy 6103, 6117 Series
TO·220 Packages (See Note 1)
4.2
IERC HP3 Series
5- 6
IERC HP1 Series
6.4
Staver V3· 7·225
6.5 - 7.5
IERC VP Series
7.1
Thermalloy 6070 Series
8.1
Staver V3·5
8.8
Staver V3· 7·96
9.5
Staver V3·3
2·5
Thermal Considerations
Table 1 Heat Sink Selection Guide (Cont.)
BSA Approx. ("C/W)
Manufacturer3 and Type
10
12.5 -14.2
13
15
15.1-17.2
16
18
19
20
20
25
Thermalloy 6032, 6034 Series
Staver V4·3·192
Staver V5·1
Thermalloy 6030 Series
Staver V4-3-128
Thermalloy 6072, 6106 Series
Thermalloy 6038, 6107 Series
IERC PB Series
Staver V6-2
Thermalloy 6025 Series
IERC PA Series
TO·92 Packages
30
46
50
57
65-5
72
85
Staver F2-7
Staver F5-7A, F5-8-1
IERC RUR Series
Staver F5-7D
IERC RU Series
Staver F1-7
Thermalloy 2224 Series
TO-S and
12
12 - 16
15
22
22
24
25
26-30
27-83
28
T~39
BSA Approx. (OC/W)
34
35
39
41
42
42-65
46
50
50-55
53
55
56
58
60
68
72
Manufacturer3 and Type
Thermalloy 2228 Series
IERC Clip Mount Thermal Link
Thermalloy 2215 Series
Thermalloy 2205 Series
Staver F5-5A
Wakefield 296 Series
Staver F6-5, F6-5L
Thermalloy 2225 Series
IERC Fan Tops
Thermalloy 2211 Series
Thermalloy 2210 Series
Thermalloy 1129 Series
Thermalloy 2230, 2235 Series
Thermalloy 2226 Series
Staver F1-5
Thermalloy 1115 Series
Power Watt (similar to TO-202)
Packages (See Note 2)
12.5 -14.2
Staver V4-3-192
13
Thermalloy 6063 Series
Staver V5-1
13
15.1-17.2
Staver V4-3-128
19
Thermalloy 6106 Series
Staver V6-2
20
24
Thermalloy 6047 Series
25
Thermalloy 6107 Series
37
IERC PA1-7CB with PVC-1B
Clip
40-42
Staver F7-3
Staver F7-2
40-43
42
IERC PA2-7CB with PVC-1B
Clip
42-44
Staver F7-1
Packages
Thermalloy 1101, 1103 Series
Wakefield 260-5 Series
Staver V3A-5
Thermalloy
1116,1121, 1123 Series
Thermalloy
1130,1131, 1132 Series
Staver F5-5C
Thermalloy 2227 Series
IERC Thermal Links
Wakefield 200 Series
Staver F5-5B
Notes
1. Most TQ-3 heat sinks can also be used with TO-220 packages with
appropriate hole patterns.
2. Most TO-220 heat sinks can be used with the Power Watt package.
3. IERC: 135 W. Magnolia Blvd., Burbank, CA 91502
. Staver Co., Inc.: 41-51 N. Saxon Ave., Bay Shore, N.Y. 11706
Thermalloy Inc.: 2021 W. Valley View Lane, Dallas, TX 75234
Wakefield Engineering, Inc.: Audubon Rd., Wakefield, MA 01880
2-6
Testing, Quality and
Reliability
FAIRCHILD
A Schlumberger Company
c. Periodic sample testing at temperature extremes is done
by Quality Assurance on outgoing material to ensure
compliance.
Testing
For proper interpretation and understanding of published
data sheet parameters, one must understand the philosophy used by Fairchild in testing its linear products.
Quality and Reliability
It is the policy of Fairchild Semiconductor Corporation that
every employee be committed to pursuing excellence by
producing zero defect products and services in conformance with customer requirements. Prevention, detection,
and control methodologies are applied throughout the manufacturing and administrative processes to strive for zero
defects and continual quality improvement.
All Fairchild products are tested during various phases of
the manufacturing process to ensure the shipment to the
customer of a reliable product that meets or exceeds the
guaranteed specifications. Fairchild tests its finished products, at room ambient, with automated equipment that operates at relatively high speeds. It is not unusual to
perform more than a hundred tests on a simple product;
each test normally takes a few milliseconds and testing of
one device is normally completed in a matter of a few
hundred milliseconds. Parameter variations due to internal
heating of the device are minimized during factory testing.
During normal operation of the device, the effects of the
internal heating on the device performance must be kept
in mind by the user as well as the person performing incoming testing in the laboratory. Internal power dissipation
and thermal resistance numbers supplied in each data
sheet will be helpful in determining temperature rise due
to internal heating.
Specific programs for quality improvement include, but are
not limited to, the following:
• Quality training. A formal nationally-recognized
program Involving all engineering and management
personnel. Operators are formally trained and
certified for all production operations.
• Statistical Process Control (SPC). A formal program
of characterization and control limit setting.
• Electrostatic Damage (ESD) control and
measurement. A program to contain the effects of
ambient static and to reduce device sensitivity.
• Design control. A program to assure adequate rules
and Implementation, process control, and
demonstrated conformance of processes, materials,
and products.
• Measurement. In-process and outgoing attributes.
Reconciliation of internal versus customer results.
• Reliability hazard prevention. In-process monitors for
the prevention of hazards such as moisture,
pinholes, step coverage, contamination, and
passivation integrity.
• Reliability monitor. OutgOing reliability as measured
by operating life In dry and moisture environments
and other stress tests.
Except for Aerospace and Defense products or customers
that specifically request it, normally no temperature testing
is done on production devices. How does Fairchild then
guarantee the parameters it specifies over the temperature
extremes? We do this by thorough characterization of the
product. Prior to release to production of a new product,
or a product modification, a representative sample from
three production runs is tested in temperature chambers
over the operating temperature range of the device. This
characterization testing, normally done on automated testers, is supplemented by bench testing and covers all of
the "guaranteed", "typical", as well as parameters not
normally specified on the product data sheet. The results
of this characterization are thoroughly analyzed and from
them, the "minimum", "typical" and "maximum" data
sheet values are determined. In addition, room temperature
guardbands are established and yield enhancements are
identified. The characterization is an on-going process and
normally the correlation between room temperature and
operating temperature extremes are very good. Product integrity and compliance to data sheet parameters are
checked periodically by Quality Asssurance by sample testing outgoing material at temperature extremes.
For continual product improvement the Linear division
maintains failure analysis capability, return material system,
and specification review to provide customer assistance
and to focus factory actions for response to fitness for
use issues. The failure analysis laboratory contains fundamental tools for optical and electrical definitions, for decapsulation, for specimen preparation, for SEM, EDAX, and
electrical microprobe. Expert diagnosiS is provided by internal personnel and augmented with outside consultation.
In summary then:
a. Production testing is done at high speeds and normally
at room temperature only.
b. Compliance to temperature specifications is accomplished through on-going characterization and room temperature guardbands.
Reliability is product performance in time, stress, and environment. The science of reliability is to define those attributes and controls necessary to assure and improve time/
stress/environment performance. Finished product reliability
is measured periodically to assure conformance with life
3-3
Testing, Quality and Reliability
requirements, and data is available quarterly for operating
life and moisture life attributes.
wafer is processed with automated die preparation that includes saw and pick and place.
Quality is performance now, conformance to specification,
and fitness for use. Basic elements of the linear division
quality system are controlled documents and in-process inspections. Outgoing quality is measured for all lots to assure conformance to specification, and data is available
monthly for electrical, visual, and mechanical attributes.
The die (or chip) itself is assembled with automated die
attach and wire bond, molded, and finished with automated handling at trim, form, test, and lead scan operations.
In-process controls assure die attach, wire bond, molding,
trim, and form. Emphasis on automation has reduced variability and enhances our ability to control quality and reliability.
Commercial Product Flow
Wafer fab must begin with controlled raw materials such
as silicon, gasses, and chemicals. Post alloy sample probes
and other monitors assure built-in quality. Automated electrical testing is performed at wafer level. The fabricated
Finished product is inspected on a lot basis for electrical,
visual, and mechanical parameters. Records are maintained
for all inspections,and deviations from conformance are
reviewed monthly for trend analysis and corrective improvements. Accept number for all inspections is zero.
3-4
,
~
~
"'
't"
"
"
,
"
~
"
~
r"
~
''''
"
"
M
&::
~" 15
":"
'" ~~
"'
"
","
~
16
=
,
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'
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17
CLASIC™
F=AIRCHILD
A Schlumberger Company
Selecting a Design Entry Level
Standard Cell Design with Fairchild CLASIC
Approach
Introduction
The Fairchild CLASIC (Customizable Linear Applications
Specific Integrated Circuits) approach brings to the systems designer a level of sophistication that will enable
VlSI solutions requiring analog and mixed analog/digital
functions to be integrated cost effectively. The CLASIC
approach offers:
• Bipolar and CMOS Technologies
• Standard Cell and Array Methodologies
• Customer CAD Tools That Allow Design and
Simulation with Higher Level Building Blocks
By offering a cell library of pre-designed commonly identified function blocks such as op amps, comparators,
DAC's, VCO, Pll, gates, flip flops, counters, etc., and
CAD tools to combine them, the CLASIC system considerably reduces the time and the risks associated with VlSI
designs. The designers task is somewhat more complicated, but similar to designing a printed circuit board using
standard IC's. Most importantly, however, with the CLASIC
approach the customer can select the level of design participation desired. At the lowest level the customer can
simply provide a functional description of the desired design and a CLASIC applications engineer will translate this
into a standard cell schematic. As the user gains experience and confidence with the CLASIC approach, any level
of design up through layout can be accomplished with the
appropriate CAD tools at the users location if desired. The
user has a choice of options best suited to his needs and
experience.
• Peak Detectors
• PLL
• Programmable Current Sources
• VCO's
• Wave Generators
• Zero Crossing (Detectors)
.555 Timer
The Cell Library
There are presently over 150 cells in the CLASIC library
covering a broad range of linear and digital function with
additional cells being added on a continual basis. The following is a partial list of the type of cells available:
-
Digital
• Gates
• Flip Flops
• One Shots
.• Edge Detectors
• MUX's
• Counters
• Registers
• Decoders
• Delay Cells
• Drivers
• Translators (ECL/TTL)
Linear
• Amplifiers
Op Amps, General Purpose
Op Amps, Low Offset
Op Amps, Programmable
Norton Amp
AGC Amp
Video Amp
Control Amp
ECL Output
• Comparators
TTL Output
General Purpose
• Data Converters A/D
D/A
• Line Drivers/Receivers 422
485
The linear performance offered by Bipolar CLASIC cells is
based on NPN fl of 2.5 GHz and PNP fl of 40 MHz. The
logic cells are based on high performance ECl offering
gate delays of 1.5 ns at fanout of 3 and 0 flip flop toggle
frequencies better than 100 MHz.
4-3
CLASIC™
The CMOS cell library is presently based on a: 3 micron
double poly process providing offset voltages of less than
5 mV, unity gain BW· of 2 MHz, gate delays of 5 ns at
fan out of 3 and D flip flop toggle frequencies at better
than 50 MHz. A new generation of cells is presently in
design for a 2 micron CMOS double poly process which
will provide gate delays of 1.5 ns and D flip flop toggle
frequencies better than 200 MHz.
A CLASIC software package for VAX mainframe systems
will also be offered. If desired, customers can also work
through Fairtech centers which are a worldwide design
center network.
In any case, the starting point for the customer is to describe the required system function in terms of the
CLASIC cells. Where a requirement is not met with an
existing cell, either the customer can create a new cell by
using the macro level components such as transistors, resistors and capacitors which are available and described in
the library or the special requirements can be described to
Fairchild's CLASIC applications engineers who can deSign
the cell for incorporation into the IC design. New cells are
being continually added to the library to serve the vast
majority of the customers needs.
CLASIC CAD
An important feature of the CLASIC system is to provide
comprehensive CAE packages for PC's, workstations and
mainframes. USing these software tools the customer can
perform all of the design steps from schematic capture to
circuit simulation and verification in their own laboratory.
Figure 1 Data Separator/Encoder Block Diagram - A CLASIC Example
--
PRE-COMPENSATION
Vee
At FOUND
GND
2"
2'
RZ
WRITE
READ WRITE
GATE GATE
DATA
ADDRESS
MARK
ENABLE
_-+---1
t--+---r-::~:-l
READ/REF ...
CLOCK
WRITE
~--;-- MISSING
CLOCK
NRZ DATA
L-_+-_______-+__ WRITE
L----~-------_;--WRITECLOCK
·~-------------r--------1---GATE
RZ READ
DATA
REFERENCE
OSCILLATOR
(IF)
--t-l-..r-::~:--'
--t........L.::.:::...J
DELAY
RESISTOR
DELAY
CAPACITOR
ADDRESS
MARK
FOUND
FAST SLOW
--CHARGE PUMP
+
FILTER
vco
CAPACITOR
EO"'''''''
4-4
CLASIC™
CLASIC CAD I (PC Based)
•
•
•
•
•
•
Step 3:
Fairchild Cell Libraries
Schematic Capture
Simulation Software
Net List Post Processor
Test Generation
Documentation
- Installation Manual
- Design Applications Manual
- Simulation Manual
Step 4:
Step 5:
Step 6:
Step 7:
CLASIC CAD II (Workstation Based)
For those customers who own or plan to purchase one of
the popular workstations, CLASIC cell libraries with simulation models will be offered.
Run simulation on schematic from Step 2.
Redesign and/or reselect cells as appropriate
to achieve desired performance. If breadboarding is desired for critical areas, kit parts
of various standard cells are available in
packaged form. This permits breadboarding to
be accomplished with relative ease and accuracy.
Auto route and place run on desired CAD
tool.
Layout verification run on desired CAD tool.
Mask generation.
Wafer Fabrication.
CLASIC CAD III (VAX based)
The CAD system used internally by the CLASIC groups
which includes complete capability from cell schematic
through layout verification, can be made available for
those customers desiring this level of performance.
Design Example:
Task: To design a disk drive data separator/encoder
decoder on a single chip. Original design required 25 IC packages plus numerous discretes.
Approach: Use CLASIC Standard Cell Methodology.
Step 1: Translate system level functional diagram into
standard cell schematic. Create new cells if
required. See Figure 1. Search cell library for
required functions.
Step 2: Perform Schematic Capture on desired CAD
tool. Net list generation
Step 8:
Step 9:
Assemble/Test (Fast turnaround prototype assembly; 1 day service).
Evaluate prototypes.
Fairchild can perform all the steps outlined 1 through 9,
however with entry level CAD tools steps 1 through 3 can
be achieved by the customer with minimal training and investment resulting in rapid payback and improved communications and efficiency.
4-5
CLASIC™
Available Packages:
set from attachment
No. of PhIs
8
14
16
20
24
28
32
40
44
68
132
Plastic Dip
SOIC
•
•
•
••
•
•
•
•
•
Side Brazed
&
Ceramic Dip
•
•
•
•
•
•
•
•
4-6
PLCC
•
•
•
•
LCC
•
•
•
•
•
•
•
Flat Pak
•
•
•
•
•
•
<
<
,
18
J,lA24H80
Winchester Disk
Servo Preamplifier
F=AIRCHILO
A Schlumberger Company
Linear Division Disk Drives
Description
Connection Diagram
8-Lead DIP and 50-8 Package
(Top View)
The !lA24H80 provides termination, gain, and impedance
buffering for the servo read head in Winchester disk
drives. It is a differential input, differential output design
with fixed gain of approximately 100. The bandwidth is
guaranteed greater than 30 MHz.
The internal design of the !lA24H80 is optimized for low
input noise voltage to allow its use in low input signal
level applications. It is offered in 8-lead DIP, 10-lead flatpak, or SO-8 package suitable for surface mounting.
•
•
•
•
Low Input Noise Voltage
Wide Power Supply Range (8.0 V To 13 V)
Internal Damping Resistors (1.3 kil)
Direct Replacement For SSI 101A, With Improved
Performance
Device Code
!lA24H80RC
!lA24H80SC
!lA24H80TC
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP and Flatpak
Molded DIP and SO-8
Operating Temperature Range
Lead Temperature
Ceramic DIP and Flatpak
(soldering, 60 s)
Molded DIP and SO-8
(soldering, 10 s)
Internal Power Dissipation 1, 2
8L-Ceramic DIP
8L-Molded DIP
SO-8
10L-Flatpak
Supply Voltage
Output Voltage
Differential Input Voltage
-65'C to +175'C
-65'C to + 150'C
O'C to 70'C
+IN
NC
-IN
v+
NC
-OUT
v-
+ OUT
Package Code
6T
KC
9T
Package Description
Ceramic DIP
Molded Surface Mount
Molded DIP
Connection Diagram
10-Lead Flatpak
(Top View)
300'C
•
.-------,10
•
+IN
265'C
1.30 W
0.93 W
0.81 W
0.79 W
15 V
15 V
± 1.0 V
NC
v+
-IN
NC
-OUT
v-
+ OUT
NC
NC
Order Information
Device Code
Notes
1. TJ Max = 150·C for the Molded DIP and 50-8, and 175·C for the
Ceramic DIP and Flatpak.
2. Ratings apply to ambient temperature at 25·C. Above this temperature,
derate the BL-Ceramic DIP at B.7 mWrC, the BL-Molded DIP at
7.5 mWrC, the SO-B at 6.5 mWrC. and the Flatpak at 5.3 mWrC.
!lA24H80FC
Package Code
3F
Package Description
Flatpak
Description of Lead Functions
Name
5-3
Description of Functions
V+
Positive Differential Supply with respect
to V-
V-
Negative Differential Supply with respect
to V+
+IN
Positive Differential Input
-IN
Negative Differential Input
+OUT
Positive Differential Output
-OUT
Negative Differential Output
NC
No connection
MA24H80
Electrical Characteristics TA = 25°C, Vee = 8.0 V to 13.2 V, unless otherwise specified.
Symbol
Condition
Characteristic
Gain (differential)4
G
BW
Bandwidth (3.0 dB)2
n,
n,
Rp= 130
Vee = 12 V
TA = O·C to 70·C
70
VI = 0.5 mVp _ p
30
65
1040
1300
RI
Input Resistance
Input Capacitance
VI
Input Dynamic Range (differential)
Rp = 130
n,
Is
Supply Current
Vee = 12 V
Output Offset (differential)
Rp = 130
Vn
Equivalent Input Noise2, 3
Rs=O
PSRR
Power Supply Rejection Ratio 1
Rs = 0
AG/AV
Gain Sensitivity (Supply)
Rp = 130
AG/AT
Gain Sensitivity (Temp)
Rp= 130
CMR
Common Mode Rejection 1 (Input)
f= 5.0 MHz
n,
n,
Notes
1. Tested at DC, guaranteed at frequency
2. Guaranteed, but not tested in production
3. Equivalent input noise (additional specification):
MAX
UNIT
4
1.0
jJ.V
100
Max
CONDITION
BW-15MHz2
BW=15MHz2
nV/v'Hz
Typical Applications
v+
SERVO
HEAD
ROC!
v-
ROC!
-=
Note.
1. Leads shown for B-Iead DIP.
2. Roq is equivalent load resistance.
3. Rp. RL' Roq
RL +ROq
4. G - 0.77 Rp
Where Rp = value from Note 3 (aboVe) in ohms.
5-4
n,
Vee = 12 V
130
MHz
1560
f = 5.0 MHz
n,
n,
mVp _ p
n
1.5
BW=4.0 MHz
55
25
rnA
200
mV
2.0
jlV
70
dB
±0.5
AVec = ± 10%
TA=25·C to 70·C
-0.1
60
n
pF
3.0
20
Rs = 0
Unit
120
3.0
AVo
3
0.85
Typ
80
CI
TYP
Min
Vcc= 12 V
Rp= 130
75
%/V
%rC
dB
JIA2460 • JIA2461
FAIRCHILD
Servo Control Chips
A Schlumberger Company
Linear Division Disk Drives
Description
Connection Diagram
28-Lead DIP (Top View)
The 1lA2460 and !.lA2461 provide the analog signal processing required between a drive resident microprocessor
and the servo power amplifier for Winchester disk closed
loop head positioning. The !.lA2460 and 1lA2461 receive
quadrature position signals from the servo channel; and
from these, derive actual head seek velocity as well as
position-mode off-track error. In the seek mode, the Digital
to Analog Converter (DAC) is used to command velocity,
while actual velocity is obtained by differentiating the quadrature position signals provided at V1 for external processing. The velocity signal (V2), obtained by integrating the
motor current, is also available for extra damping, if desired. Further, the DAC may be used for detenting the
head off-track for any purpose such as thermal compensation or soft-error retrys.
..
DO
v+
27
D.
DIRECTION INIOUT
D2
CLOCK IN
D3
D4
os
DO
VELOCITV2
VELOCITY 1
D7
LATCH ENABLE
POSITION OUT
SEEK/FOLLOW
ANALOGSW
TR'
ANALOGSW
17
TR.
•
•
•
•
•
•
•
•
Microprocessor Compatible Interface
Quadrature DI-Blt Compatible
On Board DAC
Velocity V1 Derived From Position Signal
Velocity V2 Derived From Motor Current
Quarter-Track-Crosslng Signal Outputs
Minimal External Components
Compatible With 1lA2470 Demodulator
I
QUAD
POSmON SIGNALS
'5
ANALOG COMMON
GND
Order Information
Device Code
1lA2460DC
1lA2461DC
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
PLCC
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 5)
PLCC (soldering, 10 s)
Internal Power Dissipation 1, 2
28L-Ceramic DIP
28L-PLCC
Supply Voltage
Analog Common Voltage
All inputs
QIN
16 N IN
TAO
Package Description
Package Code
FM
FM
Ceramic DIP
Ceramic DIP
Connection Diagram
28-Lead PLCC (Top View)
-65°C to + 175°C
-65°C to + 150°C
O°C to 70°C
~. ~
.. '" II8
II S Ci 8 >+ ",Ii'
iSiS
aoo°c
265°C
D4
2.50 W.
1.a9 W.
15 V Max
8.0 V Max
V supply Max
•
0
3
••
.. .
IT
DACOUT
DO
MOTOR CUR-
DO
MOTOR CUR +
117
VELOCITY 2
LATCH ENABLE
VELOCITY 1
SEEKIFOLLOW
POSmONOUT
Notes
1. TJ Max = 150·C for the PLCC, and 175·C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 25·C. Above this temperature,
derate the 28L·Ceramic DIP at 16.7 mWI"C, and the 28L·PLCC at
11.2 mWI"C.
TAO
ANALOGSW
••
'3
~ ~
•• ••
pz;;
Q (for j.lA2460)
TTL signal whose frequency is 2 times N (or Q) (for j.lA2461).
12
Track 21 (TR1)
TTL signal indicating N > Q (for j.lA2460)
TTL signal whose frequency is 4 times N (or Q) (for j.lA2461).
13
Track 20 (TRO)
TTL Signal whose frequency is 8 times N (or Q).
18
Analog Switch
19
Analog Switch
Motor current sense input to motor current integrator.
Outputs
Analog switch to be used externally for changing from seek to follow.
20
Position Output
Analog Signal representing sensed off track amplitude
21
Velocity 1
Analog output representing velocity processed from position Signals Nand Q.
22
Velocity 2
Analog output representing the integral of motor current.
25
DAC Output
Used to command velocity and position.
5·6
Figure 1 Head Actuator Control System
SYSTEM CLOCK
TO DATA SEPERATOR
JJ.A2470
SERVO
HEAD
POSmON
DEMODULATOR
DRIVE
INTERFACE
1LA2460
CONTROL
CIRCUIT
MOTOR CURRENT
SENSE RESISTOR
Figure 2 Block Diagram
N
QUADRATURE
POSlnON
SIGNALS
DACOUT
Q
POSITION
OUT
CLOCK IN
ANALOG
SWITCH
N -N
+
SEEK/FOLLOW
-
} MOTOR
CURRENT
SENSE
IN
VELOCITY 2
V+
N
ANLGCOM
VELOCITY 1
Q
GND
5-7
MA2460 • MA2461
Functional Description
The input signals Nand Q are quadrature quasi triangular
waveforms with amplitudes of ± 2.5 V nominal referenced
to Analog Common. The periods of the input signals are
subdivided by internal comparators and logic and sent to
the Track Crossing outputs To, T1, and T2. The relationship of these outputs to the inputs Nand Q is shown in
Figure 3a (for pA2460) and Figure 3b (for pA2461).
Figure 2 shows a block diagram of the j.tA2460/ j.tA2461
Servo Controller.
Power Supply And Reference Requirements
The j.tA2460/ j.tA2461 is designed to operate from a single
supply of 10 V to 12 V. Also required is a reference voltage of 5.0 V called Analog Common which serves two
functions; all analog signals will be referenced to this voltage and in addition the internal DAC will use it to set full
scale.
Note that different servo patterns may yield different numbers of track centerlines for each period of the quadrature
signal pair. The relationship of To, T1, and T2 to Nand Q
is independent of track centerlines, leaving the correct interpretations to the microcontroller.
A clock signal must be provided as a reference for the
internal switched capacitor position differentiator and motor
current integrator. The clock signal should be a sine or
square wave between Analog Common and ground at a
maximum frequency of 4.0 MHz.
DAC
The DAC is an 8-bit, buffered input, voltage output digital
to analog converter. The output voltage with an input code
of all zeros is equal to Analog Common. Full scale is
equal to Analog Common ± 2.35 V. The polarity depends
on the Direction In Signal; Direction In High will result in a
positive DAC output.
All digital inputs and outputs are TTL compatible levels
referenced to ground.
Input Signals And Track Crossing Outputs
The input format selected for position feedback is consistent with a large class of sensors that generate two cyclical output signals displaced in space phase by 90 degrees
(quadrature signal pairs). These sensors include resolvers,
inducto-syns, optical encoders, and most importantly, servo
demodulators designed for rigid disk head position sensing.
Figure 3a
The DAC enable line when high will cause the DAC's input buffer to become transparent, i.e. input data will affect
the output voltage immediately. When DAC enable is
brought low the data present on the input lines will be
latched and any further changes to the input data will not
change the output voltage. The DAC functions in both
Seek and Follow Mode. During Seek Mode the DAC outFigure 3b
Track Crossing Outputs (for /lA2460)
RADIAL
t<-!-+-+-7f-H-+*+-H--'I.:----"""7I-
~-+~~~-+~~~~----~_ HEAD
POSITION
TO
TO
Tl
Tl
T2
T2
TO
Track Crossing Outputs (for /lA2461)
0101010101010101
TO
0101010101010101
Tlllllll00000000ll
T1
0011001100110011
T21100000000111111
T2
0000111100001111
5-8
RADIAL
HEAD
POSITION
J,LA2460 •
~A2461
direction indicated by DIRECTION IN/OUT. Figure 4 shows
typical seek operation.
put is used as a velocity reference. In Follow Mode the
DAC output can be summed into the position reference
signal to offset the heads from track center.
Position Output
When the 1lA2460/1lA2461 is set to Seek Mode the signal
from Position Output lead is shown in Figure 5. This signal
is made by switching the position inputs, (N and 0)
through an inverter if required, (N" and 0) to the output
using the track crossing signals. It can be used, if desired,
to interpolate between DAC steps by attenuating it and
summing it with the DAC output.
Analog Switch
An uncommitted single pole single throw analog switch
with an ON resistance of approximately 100 .n is provided.
This switch is ON during Follow Mode.
Mode Select
The two major intended operating modes for the !lA2460
are controlled by the microcontroller via the SEEK/FOLLOW input. Mode Select input high enables Seek Mode,
low enables Track Follow Mode.
Track Follow Mode is entered when the heads are near
the end of a seek, usually within one half to one track
away from the target track centerline. The final setting to
the track center is done by the position loop.
SEEK, when asserted by the microcontroller along with
DIRECTION and a non-zero VELOCITY value as inputs,
causes the actuator system to accelerate in the requested
direction. During the ensuing motion, the actuator system
will come under velocity feedback control. The velocity
feedback signal is created by differentiation of the quadrature position signals and, additionally, by integration of motor current.
When the device is switched to Follow Mode, the position
input signal (N, N, 0 or 0) that is currently selected to
the output is latched and the Position Out Signal follows
the selected position input signal until the device is
switched back to Seek Mode. This implies that the switch
to Follow Mode must not be made until the signal that
will be the correct Position error signal for the target track
is present at the output. If track centers are defined as
the zero crossings of both Nand 0 this means that the
switch to Follow Mode must be made less than one-half
track away from the target track. (This is with respect to a
convention of 4 track per encoder cycle, so switching
must be done within 90° of the period of N or 0).
FOLLOW, the negation of SEEK, changes the feedback
loop to a track-following or position mode. Position servos
are typically second order systems and without loop compensation are potentially unstable. External components
are used, along with the 1lA2460, to achieve stable track
following performance. Velocity information (V1) is made
available as an output in this mode as an aid in stabilizing
certain loops. If non-zero data is supplied to the velocity
latches in this mode, it will result in a track offset in the
Figure 5 Position Output During Seek Mode
Figure 4 Typical Seek
DACOUT
NAND Q INPUTS
VELDCITY
VI
COIL
CURRENT
ACCELERATE
CONSTANT
VELOCITY
SEEK
POsmON OUTPUT
DECELERATE
TRACK FOLLOW
5-9
MA2460 • MA2461
Velocity Outputs
There are two analog signal outputs representing velocity.
The first (V1) is derived by differentiating the position input
signals. The entire differentiator is on-chip, using switched
capacitor techniques and requires no external components.
grees and negative. if Q is leading N. This block functions
during both Seek and Follow modes.
The second velocity output is obtained by integrating a
voltage proportional to the current in the motor using the
following function:
The transfer function of the differentiator is:
dv/dt (out)=V (+lin--lin)x2x10-4 f (clock) Hz.
Vo = dv/dt (input) x 14.3/f (clock) Hz
The motor current integrator output is clamped to Analog
Common during Follow Mode and is released at the initiation of a seek.
As an example; a 10kHz triangular signal pair into Nand
Q of 6.0 V peak-to-peak amplitude (dv/dt = 120 kv/sec)
would result in a velocity voltage output of 1.716 volts
referenced to Analog Common with. a clock of 1.0 MHz.
The polarity will be ·positive if N is leading Q by 90 de-
Figure 6 shows a typical application set up for the Servo
Control chip.
Figure 6 Typical Application Setup
DACOUT
r-
PORT 1
8-SlTS
L-
PORT 2
L
ERROR
SIGNAL
IlA2460
MICROCONTROLLER
I
SWITCH
MATRIX
VEL 1
VEL 2
DACIN
POSOUT
3-Brrs
TRKOUT
DACEN
SWl
siF
SW2
DIR
POSlnoN
DEMODULATOR
CURRENT SENSE
SERVO IN
VOICE COIL
MOTOR
5-10
MA2460 • MA2461
1JA2460, 1JA2461
Electrical Characteristics TA = O°C to 70°C, Vee = 12 V, fclk = 2.0 MHz, Analog Common = 5.0 V, unless
otherwise specified.
Symbol
Digital I/O
Characteristic
Condition
Input Voltage HIGH
DAC
Typ
Output Voltage HIGH
IOH=40 pA
Input Load Current
VI = 0 V to Vee
Input Comparator
Reference Level
2.5
Input Impedance
15
20
Linearity1
-1
V
+1
LSB
kil
bits
Monotonicity Guaranteed
7.25
7.35
7.45
Direction In Low
2.55
2.65
2.75
Zero Scale Voltage
V
5.0
±10
Settling Time2 • 4
To
Y2
LSB All bits ON or OFF
Input Voltage Range
1.0
15
On Resistance
VCM=O V to 12 V
Off Leakage3
Output Voltage Swing
RL = 15K Follow Mode
Voltage Gain
RL = 15K
~
V1
9.0
20
100
200
il
2.0
100
nA
9.0
V
0.9
1.1
1.0
-
±20
mV
9.0
V
±20
mV
+15
5-11
V
kil
1.0
Output Offset Voltage
Output Voltage Swing
mV
[J.s
Input Impedance
Output Offset Voltage
rnA
Direction In High
Output Offset Voltage
Velocity Outputs
0.2
3.0
8.0
Differential Nonlinearity
Position Output
V
2.4
2.0
Full Scale Output Voltage
Analog Switch
Unit
0.8
0.45
IOL =2.5 rnA
Resolution
Position Inputs
Max
2.0
Output Voltage LOW
Clock Input
Min
Input Voltage LOW
IlA2460 • 1lA2461
1lA2460, 1lA2461 (Cont.)
Electrical Characteristics TA
= O°C to 70°C, Vee
otherwise specified.
Symbol
= 12
V, fClk = 2.0 MHz, Analog Common
Characteristic
Condition
Positive Supply
Vcc= 13.2 V
Iss
Negative Supply
Vcc = 13.2 V
lAC
Analog Common I
V1 - Differentiator
Linearity
fclk
V2 - Integrator
Linearity
fclk
Icc
Min
= 5.0
V, unless
Typ
Max
Unit
10
15
mA
-15
-10
-2.0
0
mA
+2.0
mA
= 1.0 MHz to 4.0 MHz;
fN/Q ..; 10kHz
0.25
%
= 1.0 MHz to 4.0 MHz
1.0
%
Notes
1. DAC Unearity is a function of the Clock frequency; Unearity at 1.0 MHz
is typically ± b LSB.
2. DAC Settling TIme is approx 5.0 /lS, plus a delay of maximum
32 x Clock period i.e., 5 + 32 /lS at Clock = 1.0 MHz Minimum could be
5.0 /lS.
3. Equivalent to 50 Mn.
4. Guaranteed, 'but not tested in production.
5-12
~A2470
FAIRCHILD
A Schlumberger Company
Winchester Disk
Position Demodulator
Preliminary
Linear Division Disk Drives
Description
Connection Diagram
28-Lead DIP
(Top View)
The 1lA2470 is a monolithic analog/digital integrated circuit
which decodes a quadrature di-bit pattern from the dedicated servo surface of a disk file into head position, track
data and timing components. The 1lA2470 accepts this signal after it has been amplified by a 1lA2480 type of
preamp and processes the various components for input
to a 1lA2460 type servo controller. These three circuits
and their external components form a disk servo control
system for closed loop applications.
TAKCLK
Vcc,
PRE·SCALER USB
PRE-SCALER LSB
SYNCTlUING
VCO TUNING VOLTAGE
• Quadrature Position Signals
• Programmable Charge And Discharge In Peak
Detectors
• Sync Lock By PLL With Lock Detection Output
• NRZ Track Data And Clock Output
• Band Gap 5.0 V Reference Provided
• AGC Amplifier With 36 dB Range
• Servo Frame Rates To 400 kHz
• Compatible With j.lA2480 Servo Preamp And j.lA2460
Servo Control Chip
• Standard 5.0 V And 12 V Power Supplies
VCOCAP1
VCOCAP2
STORAGE CAP 1
STORAGE CAP 2
CLKOUT
ANALOG REF
CHRG PUMP CUR
CHRG MAGNITUDE
COMPOUT
PLLLOCKED
CHRGCUR
GND
DlSCHRGCUR
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, SO s)
Internal Power Dissipation 1, 2
28L-Ceramic DIP
Supply Voltage, VCC1
Supply Voltage, VCC2
-S5°C to + 175°C
O°C to +70°C
Order Information
Device Code
300°C
1lA2470DC
2.50 W
S.O V
15 V
Not..
1. TJ Max = 175°C.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate at 16.7 mWI"C.
5-13
Package Code
FM
Package Description
Ceramic DIP
JlA2470
Block Diagram
CHARGE
PUMP
CURRENT
BALANCE
BYPASS
AGC
COMP,'
- tCOMPOSITE IN 2 - tCOMPOSITE IN 1
Vee,
VCC2
GROUND
-
-
AGC
MP2
C1
COMPOSITE
OUT
SYNC
nMlNG
,
I
I1
AGC
AMPLIFIER
COMP
CHARGE
MAGjlTUOE
SIG
J
SYNC
SYNC
SEPARATOR
ANALOG
REF
-
CHARGE
PUMP
PUMP
DOWN
1
rr-
0
t-
SYNC
PLLLOCK
DETECTOR
U.
W
'"
VCO
WINOOW
LOCKEO
I
!
DATA
DEMODULATOR
I
TR!CK TRicK
CLOCK DATA
VCOCAPI
VCOCAP2
VCOTUNING
VOLTAGE
0
WINDOWS
~
-
t-t-t-- -
'0"
DATA
-H
>
o
w z
VI >
w VI
'"
5V
REGULATOR
0
>
AGC
i--
~
CAr 1
UP
PHASE
DETECTOR
0-
PLLLOCKED
STORAGE
CAP 2
STORAGE
I
WINDOWS
POSITION
DEMODULATOR
CLOCK OUT
..J
0
I
DIVIDER
DECODER
DIV
CLK
PRE-SCALER
I
Jp jp
OUT OUT
DISCHARGE CHARGE
CURRENT CURRENT
5-14
PRE-SCAJR
LSB
P!E-SCALER
MSB
J.LA2470
Description Of Lead Functions
Lead
I
Name
Function
Input Signals
Pre-scaler LSB
Pre-scaler MSB
Programs the Pre-scaler for VCO frequency relative to the frame rate. Divide ratios
of 32, 64, 96, and 128 are available. Inputs are TTL levels.
5
VCO Tuning Voltage
Voltage input sets the VCO Current.
11
Charge Pump Current
Voltage input sets the current level into the Loop Filter.
2
3
14
Ground
18
VCC2
12 V supply input.
25
26
Composite IN 1
Composite IN 2
Composite signal inputs.
28
VCC1
5.0 V supply input.
1
Track Clock OUT
Clock output derived from the Sync signal. Used as reference for Track Data; TTL.
10
Clock OUT
VCO output; TTL.
13
PLL Locked
Logic high when PLL is locked; TTL.
17
Composite OUT
AGC Amplifier output.
19
Analog Reference
5.0 V reference output. Used as reference for Nand Q outputs.
20
QP OUT
Quadrature position output.
Outputs
21
NP OUT
Normal position output.
27
Track Data
NRZ data from missing Sync pulses; TTL.
External Components
4
Sync Timing
Oneshot timing RC network. Sets length of window used in Sync Separator.
6-7
VCO Capacitor
VCO Timing Capacitor. Sets VCO center frequency.
8-9
Storage capacitor
PLL Loop Filter.
12
Charge Magnitude
Oneshot timing RC network. Sets length of current pulse out of the Phase
Detector.
15
Peak Detector
Discharge Current
Resistor to Ground. Sets the internal peak detector discharge current.
16
Peak Detector
Charge Current
Resistor to Ground. Sets the internal peak detector charge current.
21
Balance Bypass
Bypass capacitor for the offset cancelling circuit in the AGC Amplifier. Sets the
low frequency roll off of the Amplifier.
23
AGC 1
Loop Filter capacitor for AGC Amplifier.
24
AGC 2
Bypass Capacitor for AGC Amplifier.
5-15
MA2470
Theory Of Operation
pulse in the stream. Sync separator timing is shown in
Figure 3.
The purpose of the /lA2470 is to demodulate both analog
and digital information from the composite servo .signal as
shown in figure 1. This signal contains the digital signals
Data and Sync and the analog quadrature di-bit signals N,
N, Q, and Q.
TRACK DATA DEMODULATOR The track data encoding
flip-flop changes state whenever there is a data pulse
present producing NRZ data for the user.
Data The track data is presented as NRZ with a companion clock signal for latch control. The track data is decoded· from the first pulse in each servo cell. This data
permits identification of index position, guardband etc. The
codes and schemes are entirely at the user's option as
no decoding is done on-chip.
Sync The sync pulse is the one
is always present in every frame
pulse is used to synchronize the
the rest of the information in the
PHASE LOCK LOOP When a disk sync pulse is sensed
by the Sync Separator, the PLL compares the phase of
disk sync with the phase of a reference sync pulse
generated by the window decoder. Refer to Figure 4 and
5. Every other sync pulse from the Sync Separator causes
the window decoder counter to preset. This forces the
decoder into phase alignment with the disk sync. Starting
from a known condition allows a phase comparison to be
made on the next frame by comparing the trailing edges
of the reference sync with the disk sync pulses and
outputing a correction signal to the charge pump to
increase or decrease the veo frequency to correct the
phase error. On the next frame the cycle is repeated.
pulse in the frame which
on every track. This
PLL and makes decoding
frame possible.
Quadrature Position Signals The four position pulses are
analog signals whose amplitude encodes the position of
the disk file heads with respect to the data track centers.
Nand Q are in a quadrature relationship, i.e. when Nand
N are equal in magnitude the difference between Q and Q
is at maximum and vice versa. Equal magnitudes of Nand
N represent odd tracks and Q and Q the even tracks.
LOCK DETECTOR When the frequency and phase of the
veo are correct, the trailing edge of the sync pulse will
coincide with the trailing edge of count 4 from the
counter/decoder. The decoder generates a window from
the end of count 3 to the end of count 5, so that the
sync edge will ideally fall in the middle. Whenever the
sync falls inside the window four consecutive times, lock
is detected and the lock Signal goes true. In order for the
lock signal to be reset the sync pulse must be outside the
window for four consecutive frames.
AGC Amplifier The 1lA2470 AGe Amplifier is a fully differential design with a typical bandwidth of 20 MHz and active offset cancelling. The composite signal input level
must be between 30 mV and 300 mV to be within the
Amplifier's active AGe range. The offset cancelling circuit
requires an external filter capacitor which provides control
of the low frequency response. An external capacitor is
used to control the AGe bandwidth. The AGe Amplifier
output amplitude is typically 3.5 Vp-p and is available at
an output lead on the device for monitoring.
POSITION DEMODULATOR Figure 6 shows the position
signals as a function of servo head position. The Position
Demodulator consists of four digitally enabled peak
detectors, two summing amplifiers and a precision band
gap reference. Each of the four peak detectors is enabled
by the window decoder during one of the position pulses
as shown in Figure 7. The N pOSition output is derived by
taking the difference between the first two peak detector
outputs. The Q output is similarly obtained from the
second pair. The outputs are referenced to the 5 V
reference which is available as an output to be used as
an analog baseline. The charging and discharging slew
rates in the peak detectors are programmable by external
resistors. The charging slew rate is associated with
acquisition of the peak and the discharge slew rate
controls the droop rate between peaks.
Sync Separator The Sync Separator shown in Figure 2
operates on the composite signal as it appears at the output of the AGe Amplifier. The hystereSiS comparator has
thresholds of +0.7 V and 0 V and produces pulses whose
trailing edges are at the zero crossings of the composite
signal. The trailing edges of these pulses trigger the oneshot. The output of the oneshot is AND-gated with the
pulse stream from the hysteresis comparator to produce
the sync pulse. The pulse length from the oneshot should
only be long enough to enclose the sync bit as the next
5-16
J,.LA2470
Figure 1 Composite Servo Signal
Figure 2 Sync Separator
TRACK
CLOCK
MONOSHOT
COMPOSITE SIGNAL
FROMAGC
HYSTERSIS
COMPARATOR
NRZ
TRACK
AMPLIFIER
DATA
SYNC TO
PHASE
DETECTOR
~:~ ~II~~O~~ =Jl...~_____________---J
SYNC WINDOW
..:1I=-_____________--'
Figure 3 Sync Separator Timing
DATA
SYNC
POSITION
COMPOSITE
SIGNAL
CO~~!~~~~~ ~ ;-----u-,L._
.._ _
MONOSHOT - - - - (
!
___Ir---
Ur--------------------------
SYNCTO-----,
PHASE
DETECTOR
5-17
J.LA2470
Figure 4 Phase Lock Loop Block Diagram
Figure 5
veo
Fast/Slow Timing Diagram
PRESET
PRESET
COMPARE
SYNC
PRESET
REF SYNC
PUMP UP
PUMPOOWN
veo SLOW
PRESET
~~
COMPARE
PRESET
~
U
PRESET
REF SYNC
PUMP UP
PUMP DOWN
veOFAST
5-18
fJ.A2470
Figure 6 Magnetized Pattern of Quadrature Oi-Bit Servo Signal and Read Signal
SERVO HEAD
GAP POSITION
r-DATA PULSE
-SYNC PULSE
,-NPULSE
I I
fNPULSE
Q PULSE
j
N NS SN NS S
N NS S
N NS S
r'rQPULSE
N NS SN NS S
A
N NS SN NS S
N NS S
N NS S
I
N NS SN NS S
V
V 1/
A
V
JlJJ
N NS SN NS S
N NS S
N NS S
I
N NS SN NS S
VV
N NS SN NS S
111\
V\I
N NS SN NS S
N NS S
N NS S
I
I
I
Position Pulse
N
N
COMPOSITE
SERVO
SIGNAL
I
I
I
I
Iii
--Ir-l. .-li___+-______
WINDOW 1 _ _ _ _ _ _ _
WINDOW 2
--______________
iI
A A
V V
N NS SN NS S
MAGNETIC PATTERN
Figure 7
A
VV
A
V
/I /1
I
N NS SN NS S
N NS S
N NS S
1\
VV
1\/1
VI/
A A 1\
\I v v \I
/1/\
AA
I
,L-________
,----,
~,
5-19
READ SIGNAL
VV
/I 1\/1
V VI/
-----I
J,LA2470
Figure 8 PLL Synchronizing Event
WINDOW
DECODER
SYNC
WINDOW
WINDOW 1
WINDOW 2
WINDOW 3
L
WINDOW 4
SYNCP
SYNC
SEPARATOR
n
~
:-'-,
-AJ\;
Jl
Y
DATA
AGC
AMPLIFIER
I
:
r--,
r--,
~
~
,, ,,
,. .... "'1
'
I
fI
,
~
Y
Y
PLL SYNCHRONIZING EVENT
Mayor may not be present. Width varies.
May be present at any amplitude (from zero to sync pulse amplitude)
I'A2470 TIMING DIAGRAM when Loop is locked.
MA2470
Electrical Characteristics TA = 25°C, VCC2 = 12 V, VCC1 = 5.0 V, unless otherwise specified.
Characteristic
Condition
Units
AGC Amplifier
Max Voltage Gain
Input Freq = 1.0 MHz
46
AGC Range
Input Freq = 1.0 MHz
40
dB
15
MHz
Frequency Response
Input Voltage Range
30
Output Voltage
dB
300
mV
5.0
Vp_p
5.0
Vp_p
Nand Q Outputs
Output Voltage
RL
=
20K
Output Impedance
Output Offset Voltage
100
n
20
mV
Voltage Reference
Output Voltage
V
Output Current
mA
5-20
/-LA2470
J.LA2470 (Cont.)
Electrical Characteristics TA = 25°C, VCC2 = 12 V, VCC1 = 5.0 V, unless otherwise specified.
Characteristic
Condition
VCO
Max Frequency
Cvco = 20 pF
Tuning Range
Digital Outputs
(R pull-up = 2.0K to Vee>
VOL
0.4
V
Rise Time
O.B to 2.4 V
20
ns
Fall Time
2.4 to O.B V
5.0
ns
Vcc 1
140
mA
VCC2
12
mA
Supply Current
Program Voltage vs
Charge Pump Current
Capicator Value vs
Sync Pulse Demodulator And
Charge Pump Oneshot Pulse
Length
Control Voltage vs
VCO Frequency
Q.4
V
/
V
V
50
/
V
>
I
..
!
0
!;!
150
OUTPUT CURRENT -
200
mA
250
-Q.4
~
0.8
b
:z:
40
V
U)
w
Z
0
1.0
1.2
NORMALIZEO VCO FREQUENCY - MHz
5-21
/
60
~
V
1/
1/
0.&
'/
I
g
V
-0.2
X
VR=12K
80
II:
/
~
...~
:>
...
"-
/
..,
/
100
V
0.2
w
/
100
'/
/
1.4
/
20
/
o
o
/'
R = 24K
./
"
200
;'
V
400
&00
PULSE LENGTH - ns
800
1000
IlA2470
Test Circuit (Note 2)
•
(NOTE 1)
TRK ClK
TRK DATA
PRE-SCl lSB
COMP IN 2
-=-------I SYNC TIMING
COMPIN 1
VCO TUN VOL
AG COMP2
VCO CAP 1
AGCOMP1
5.0 v -...........-'\IIAr.....
.u A2470
C2
0.5
Jl
~F
510
VCO CAP 2
n
O.~"~F-~~AOA°r-~---~~~---i
(NOTE 1)
UV
VCC1
PRE-SCl MSB
N OUT
STOR CAP 1
SAL SYPS
STOR CAP 2
QOUT
ClK OUT
VREF OUT
f---IN
q
NOUT
1.0"F~
QOUT
VREFOUT
5.1 kO
~OV-~~--t------------__i
750n
CHG PMP CUR
VCC2
CHG PMPMAG
COMPOUT
24kO
(NOTE 1)
Pll lOCKED
CHRG CUR
GND
DISCH CUR
12 V
~
-=-
COMP
OUT
20kO
2OOkO
Notes
1. Open coilector digital outputs
2. C1 - 33 pF
C2 -100 pF
C3=15 pF
Values are for a frame frequency of 150 kHz.
Scale linearly for other frame notes.
5-22
-=-
IlA248X • IlA248XR Series
Winchester Disk
Read/Write Preamplifiers
FAIRCHILD
A Schlumberger Company
Linear Division Disk Drives
Description
Connection Diagram
24·Lead Flatpak
(Top View)
The J.LA248X/ J.LA248XR Series High Performance Read/
Write Preamplifiers are intended for use in Winchester disk
drives which employ center tapped ferrite or manganesezinc read/write heads. The circuit can interface with up to
eight read/write heads which makes it ideal for multi-platter disk drive designs. Designed to reside in the Head/
Disk Assembly (HDA) of Winchester disk drives, the Read/
Write Preamplifiers provide termination, gain, and output
buffering for the disk heads as well as switched write current. Certain write fault conditions are detected and reported to protect recording integrity. The parts are available
with internal damping resistor (J.LA248XR) and without internal damping resistor. (J.LA248X)
•
•
•
•
•
•
•
•
•
Wide Bandwidth, High Gain, Low Noise
Up To Eight Read/Write Channels
Internal Write Fault Condition Detection
5.0 V & 12 V Power Supply Voltages
Independent Read & Write Data Lines
TTL Control And Data Logic Levels
Externally Programmable Write Current
Available With Internal Damping Resistor
Compatible With 551 117 Family
cs
HSO
GNO
HS1
HOX
WDI
HOY
VDD1
H1X
v DD2
H1Y
veT
H2X
H3X
H2Y
H3Y
Aiw
Ne
we
Ne
ROX
WUS
ROY
vee
Order Information
Device Code
Package Code
FR
FR
J.LA2484GC
J.LA2484RGC
Package Description
Brazed Flatpak
Brazed Flatpak
Input Voltages
Absolute Maximum Ratings
Head Select (HSO, HS1, HS2)
Write Current (WC) Voltage in
read and idle modes. (Write
mode must be current limited
to -70 mAl
Chip Select (CS)
Read/Write (R/W)
Storage Temperature Range
-65°C to + 175°C
Ceramic
-65°C to + 150°C
Plastic
Operating Junction Temperature Range 25°C to 135°C
Lead Temperature
Ceramic (soldering, 60 s)
300°C
265°C
Plastic (soldering, 10 s)
Internal Power Dissipation,l, 2
28L-Ceramic DIP
2.50 W
24L-Ceramic DIP
1.95 W
18L-Ceramic DIP
1.58 W
32L-Brazed Flatpak
1.88 W
24L-Brazed Flatpak
0.97 W
24L-Ceramic Flatpak
0.90 W
44L-PLCC
1.92 W
1.39 W
28L-PLCC
Supply Voltage, VCCI
6.0 V
15 V
Supply Voltage, VCC2
Write Current (IWC)
70 mA
Part Selection
Device Code
J.LA2482X
J.LA2484X
J.LA2485X
J.LA2486X
J.LA2488X
Notes
1. TJ Max - 150°C for the Plastic, and 175°C for the Ceramic.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 28L~Ceramic DIP at 16.7 mW/oC the 24L~Ceramic DIP at
13 mW/oC, the 18L·Ceramic DIP at 10.5 mwrc, the 32L·Brazed
Flatpak at 12.5 mwrc, the 24L·Brazed Flatpack at 6.5 mwrc, the
24L Ceramic Flatpak at 6.0 mW/oC, the 44L·PLCC at 15.3 mW/oC, and
the 28L·PLCC at 11.2 mW/oC.
5-23
Channels
2
4
5
6
8
-0.4 V to VCCI +0.3 V
-0.3 V to VCCI +0.3 V
-0.4 V to VCCI +0.3 V
-0.4 V to VCCI +0.3 V
J.LA248X • J.LA248XR Series
Connection Diagram
24-Lead DIP
(Top View)
Connection Diagram
18-Lead DIP
(Top View)
24
cs
GND
18
HSO
cs
HSI
GND
WDI
HC
VDD1
V"""
HOX
HSO
HIX
vco,
vco•
HOX
HOY
VCT
H1Y
VCT
R/W
HIX
H1Y
HOY
H2X
H3X
WC
H2Y
H3Y
RDX
RDY
R/W
WC
RDX
wus
RDY
Vee
Order Information
Device Code
j.iA2482DC
j.iA2482RDC
Order Information
Device Code
j.iA2484DC
j.iA2484RDC
Vcc
NC
Package Code
7L
7L
Package Description
FU
FU
24
cs
HSO
GND
HSI
HOX
HSO
GND
HSI
HOY
WDI
HOX
WDI
HIX
VCC2
HOY
VDD1
HIX
V...
H1Y
VCT
H2X
H3X
H2Y
H3Y
R/Vi
HC
WC
NC
RDX
WUS
RDY
Vcc
Package Description
Ceramic DIP
Ceramic DIP
Connection Diagram
24-Lead DIP
(Top View)
Ceramic DIP
Ceramic DIP
Connection Diagram
24-Lead Cerpak
(Top View)
Ci
Package Code
H1Y
VCT
H2X
H4X
H2Y
H4Y
RiW
H3X
WC
H3Y
RDX
wus
ADY
Veef
Order Information
Device Code
j.iA2484FC
j.iA2484RFC
Package Code
FN
FN
Package Description
Ceramic Flatpak
Ceramic Flatpak
Order Information
Device Code
j.iA2485DC
j.iA2485RDC
5-24
Package Code
7L
7L
Package Description
Ceramic DIP
Ceramic DIP
MA248X • MA248XR Series
Connection Diagram
24-Lead Cerpak
(Top View)
Connection Diagram
28-Lead DIP
(Top View)
cs
HSO
GNO
HSI
HOX
HS2
28
HOY
WOI
HIX
VDD1
H1Y
VCT
HOX
H2X
H4X
HOY
H2Y
H4Y
Riw
H3X
GNO
HIX
WC
H3Y
H1Y
ROX
wus
H2X
ROY
Vee
Order Information
Device Code Package Code
Package Description
MA2485FC
MA2485RFC
Ceramic Flatpak
Ceramic Flatpak
FN
FN
HSI
HSO
H5Y
H2Y
H4X
R/Vi
H4Y
WC
H3X
NC
H3Y
ROX
WUS
ROY
Vee
Connection Diagram
28-Lead PLCC (Top View)
3
HOY
2
1
28
27
26
Order Information
Device Code Package Code
Package Description
MA2486DC
MA2486RDC
Ceramic DIP
Ceramic DIP
FM
FM
VDQ1
Connection Diagram
24-Lead Flatpak
(Top View)
HIX
V....
H1Y
VCT
H2X
H5X
H2V
H5Y
CS
HSO
R/;;;;
H4X
GNO
HSI
WC
H4Y
HOX
HS2
HOY
WOI
HIX
VDD1
H1Y
VCT
12
13
14
"
)(
>
Q
Z
Q
a:
II:
15
u
:Ii
16
17
18
)(
::>
~
2 2
Order Information
Device Code Package Code
/lA2486QC
KH
MA2486RQC
KH
Package Description
Plastic Leaded Chip
Carrier
Plastic Leaded Chip
Carrier
H2X
H4X
H2Y
H4Y
R/W
H3X
wc
H3Y
ROX
WUS
ROY
Vee
Order Information
Device Code Package Code
MA2485GC
/lA2485RGC
5-25
FR
FR
Package Description
Brazed Flatpak
Brazed Flatpak
MA248X • MA248XR Series
Functional Description
Connection Diagram
44·Lead PLCC (Top View)
Ne
7
S
5
4
3
2
1
44
43
42
In the Write mode, the /lA248X//lA248XR Series accepts
TTL compatible write data pulses on the WDI lead. On
the falling edge of each write data pulse, a current transition is made in the selected head. Head selection is accomplished via TTL input signals: HSO, HS1, HS2 (see
Table 2). Internal circuitry senses the following conditions:
V DD1
41
VD02
VCT
HOX
HOY
11
35
H6Y
~X
•
H~
H1Y
13
HSY
H2X
H4X
H2Y
H7X
1.
2.
3.
4.
5.
H6X
Absence of data transitions.
Open circuit head connection.
Absence of write current.
Short circuit head connection.
Idle or read mode.
H4Y
Any or all of the above conditions would result in a high
level on the write unsafe (WUS) output signal.
16
H7Y
2!l
H3Y
During read operations, the /lA284X amplifies the differential voltages appearing across the selected R/W head lead
and applies the amplified signal differentially to data lines
RDX and ROY.
Order Information
Device Code
Package Code
/lA2488QC
KI
/lA2488RQC
KI
Package Description
Plastic Leaded Chip
Carrier
Plastic Leaded Chip
Carrier
Connection Diagram
32·Lead Flatpak
(Top View)
HSI
32
HS2
HSO
31
WOI
cs
30
GND
29
VD01
VDD2
HOX
28
VCT
HOY
27
H6X
HIX
26
H6Y
H1Y
25
H5X
H2X
24
H5Y
H2Y
10
23
H4X
H7X
11
22
H4Y
H7Y
12
21
H3X
R/W
13
20
H3Y
WC
14
19
WUS
ROX
15
1.
NC
ROY
16
17
Vee
Order Information
Device Code
Package Code
/lA2488GC
/lA2488RGC
FS
FS
Package Description
Brazed Flatpak
Brazed Flatpak
5-26
J.lA248X • J.lA248XR Series
Description of Lead Functions
Lead
Name
Description of Functions
CS
Chip Select
Chip Select High disables the read/write function of the device and
forces idle mode. (TTL)
R/W
Read/Write Select
A Logic High places the devices in read mode and a Logic Low forces
write mode. Refer to Table 1. (TTL)
HOX, Y
through H7X, Y
Read/Write Head
Connections
The J.LA2488 has eight pairs of read/write connections. The X and Y
phases are made consistent with the read output, RDX and RDY,
phases. (Differential)
RDX, Y
Read Data Outputs
The chip has one pair of read data outputs which is multiplexed to the
appropriate head connections. (Differential)
HSO through HS2
Head Select Inputs
The eight read/write heads are addressed with the head select inputs.
Refer to Table 2. (TTL)
WC
Write Current Input
This lead sets the current level for the write mode. An external resistor is
connected from this lead to ground, and write current is determined by
the value of this resistor divided into the write current constant K, which
is typically 140 V.
WDI
Write Data Input
The write data input toggles the write current between the X and Y
selected head connections. Write current is switched on the negative
edge of WDI. The initial direction for write current is the X side of the
switch and is set upon entering read or idle mode. (TTL)
VDD2
Resistor Center Tap
In some versions (determined by lead availability) of the J.LA248X series,
a resistor may be connected between RCT and VDD1 to reduce internal
power dissipation. If this resistor is not used, RCT must be connected
externally to VDD1.
VCT
Center Tap Voltage
The center tap output provides bias voltage for the head inputs in read
and write mode. It should be connected to the center tap of the read/
write heads.
WUS
Write Unsafe
A high logic level at the write unsafe output indicates a fault condition
during write. Write unsafe will also be high during read and idle mode.
(Open collector)
5-27
tlA248X • tlA248XR Series
Table 2 Head Select Inputs
Table 1 Read/Write Select
Operating Modes
Head Selection
Chip Select CS
Read/Write R/W
Mode
HSO
HS1
HS2
Head Selected 1
1
X
Idle
Read
Write
0
1
0
1
0
1
0
1
0
0
1
0
0
0
0
1
1
0
1
2
3
4
5
o
o
1
o
1
0
0
6
7
Note
1. If selected head is beyond the capacity of the /lA248X model, the open input
condition on the selected input will be reported as an unsafe level at the WUS
oulput.
Block Diagram (Typical, J.LA248X)
VCT
>--
H C~P h
SELECT
WDI
WRITE
SELECT
I
R/W
READ EN
RDX
I
ROY
POST READ
AMPUFIER
HSO
HSI
HS2
WUS
I
HEAD
SELECT
I
I
WRITE EN
I
I
UNSAFE
CIRCUIT
DETECTOR
1J
HOX
I
I
~
HEAD 0
DIFFERENTIAL
READ
AMPLIFIERS
AND
WRITE
CURRENT
SWITCHES
I
HEAD 1
H1V
H2X
HEAD 2
H2Y
H3X
HEAD3
H3Y
(5 CHANNELS)
I
CURRENT
DRIVER
t-
HOY
HIX
H4X
HEAD4
H4Y
I
1
WC
5-28
MA248X • MA248XR Series
Absolute Maximum Ratings All voltages referenced to GND
Symbol
Characteristic
Value
Unit
-0.3 to + 14
V
VOO2
-0.3 to + 14
V
Vee
-0.3 to +6.0
V
VOOl
DC Supply Voltage
Vin
Digital Input Voltage Range
-0.3 to Vee +0.3
V
VH
Head Port Voltage Range
-0.3 to VOD +0.3
V
Vwus
WUS Port Voltage Range
-0.3 to + 14
V
Iw
Write Current
10
Output Current
RDX, RDY
60
rnA
-10
mA
VCT
-60
WUS
+12
Recommended Operating Conditions
Value
Unit
12 ± 10%
V
VOO2
6.5 to VOOl
V
Vee
5.0 ± 10%
V
5.0 to 15
/lH
500 to 2000
Symbol
VOOl
Characteristic
DC Supply Voltage
Lh
Head Inductance
RD
Damping Resistor (External)
RCT
RCT Resistor
90 ± 5.0% (1'2 watt)
n
n
Iw
Write Current
25 to 50
rnA
10
RDX, RDY Output Current
o to
IlA
5-29
100
J.LA248X • J.LA248XR Series
DC Characteristics 25°C ';;;TJ';;; 125°C Voo 1 = 12 V, Vee = 5.0 V, unless otherwise specified.
Symbol
Icc
IDD
Pc
VIL
VIH
Characteristic
Supply Current
Supply Current
Power Consumption
Digital
Inputs:
Read/Idle Mode
25
Write Mode
30
Idle Mode
25
Read Mode
50
Write Mode
30+lw
= 125°C
TJ
Idle Mode
400
Read Mode
600
Write Mode,
Iw=50 rnA,
RCT=90 n
850
Write Mode,
Iw=50 rnA,
RCT=O n
1050
-0.3
0.8
Input Voltage HIGH
2.0
Vee + 0.3
IIH
rnA
mW
V
V
VIL - 0.8 V
Input Current HIGH
VIH =2.0 V
100
/lA
IOL =8.0 rnA
0.5
V
VOH =5.0 V
100
/lA
WUS Output
Center Tap Voltage
-0.4
rnA
Input Current LOW
IOH
VCT
Unit
Max
Input Voltage LOW
IlL
VOL
Min
Condition
rnA
Read Mode
4.0 (typ)
V
Write Mode
6.0 (typ)
V
Write Characteristics VOOl = 12 V, Vee = 5.0, Iw = 45 rnA, Lh = 10 J.lH, f(Oata) = 5.0 MHz, CL (ROX,
ROY) .;;; 20 pF, Ro EXT = 750 n or Ro INT, unless otherwise specified.
Characteristic
Condition
Write Current Range
Min
Max
Unit
rnA
10
50
Write Current Constant "K"
133
147
Differential Head Voltage Swing
5.7
V
V (pk)
Unselected Diff. Head Current
2.0
rnA (pk)
Differential Output Capacitance
15
pF
Differential Output· Resistance
WDI Transition Frequency
Without Internal Resistors
10K
With Internal Resistors
538
WUS= LOW
Iwe to Head Current Gain
5-30
n
1.0K
400 (typ)
kHz
18 (typ)
rnA/rnA
MA248X • MA248XR Series
Read Characteristics VDD1 = 12 V, Vee = 5.0 V, Lh = 10 MH, f (Data) = 5.0 MHz, CL (RDX, RDY)
(Vin is referenced to VeT)' RD EXT = 750
Characteristic
n
<
20 pF,
or RD INT, unless otherwise specified.
Min
Max
Unit
80
120
VIV
-2.0
+2.0
mV
Condition
Differential Voltage Gain
Yin = 1.0 mVp. p at 300 kHz
RL (RDX), RL (ROY) = 1.0 kQ
Dynamic Range
Input Voltage, VI, Where Gain Falls by 10%.
Yin = VI + 0.5 mVp_p at 300 kHz
Bandwidth (-3db)
I Zs 1<5.0 Q, Yin = 1.0 mVp _ p
30
MHz
Input Noise Voltage
BW = 15 MHz, Lh = 0, Rh = 0
2.1
nV/YHZ
Differential Input Capacitance
f = 5.0 MHz
23
pF
Differential Input Resistance
f = 5.0 MHz
I Without Internal Resistors
I With Internal Resistors
Q
2K
440
850
Input Bias Current
45
IJA
Common Mode Rejection Ratio
VCM=VCT+100 mVp _ p at 5.0 MHz
50
Power Supply Rejection Ratio
100 mVp _ p at 5.0 MHz on V001, V002, or VCC
45
db
Channel Separation
Unselected Channels: Yin = 100 mVp _ p at
5.0 MHz and Selected Channel: Yin = 0 mVp _ p
45
db
Output Offset Voltage
-480
+480
5.0
7.0
V
35
Q
1070
Q
Common Mode Output Voltage
Single Ended Output Resistance
db
f = 5.0 MHz
Internal Damping Resistor
560
mV
Switching Characteristics VDD1 = 12 V, Vee = 5.0 V, TJ = 25°C, Iw = 45 rnA, Lh = 10 MH, f (Data)
RD EXT = 750
Symbol
n
= 5.0
MHz,
or RD INT, unless otherwise specified.
Characteristic
Condition
Min
Max
Unit
IJS
R/W to Write
Delay to 90% of Write Current
1.0
R/W to Read
Delay to 90% of 100 mV 10 MHz Read Signal
Envelope or to 90% Decay of Write Current
1.0
CS to Select
Delay to 90% of Write Current or to 90% of
100 mV 10 MHz Read Signal Envelope
1.0
CS to Unselect
Delay to 90% Decay of Write Current
1.0
HSO
HS1
HS2
to any Head
Delay to 90% of 100 mV to 10 MHz Read
Signal Envelope
1.0
IJS
WUS
Safe to Unsafe - TD1
Iw= 50 mA
8.0
IJS
Unsafe to Safe - TD2
Iw=20 mA
1.0
Prop. Delay - TD3, TD4
Lh = 0 IJH, Rh = 0 Q
From 50% Points
25
Asymmetry
WDI has 50% Duty Cycle and
1 ns Rise/Fall Time
Rise/Fall Time
10% - 90% Points
R/W
CS
Head
Current
1.6
5-31
2
20
IJs
nS
•
J.LA248X • J.LA248XR Series
Figure
Head Current Timing
DIFFERENnAL
HEAD CURRENT
figure 2a
Unsafe to Safe Timing
' -_ _ _ DATA
VWD
Vwus - - - - - - -
=
'-------
LOAD CAPACITANCE 20 pF
PULL UP RESISTOR = 1.0 kQ
Figure 2b Safe to Unsafe Timing
HEAD OVERSHOOT
VOLTAGE
(VH1o VH2)
1---'.'=1
2.0V
--LO-A-OCA-PAC-ITANCE =20pF
PULL UP RESISTOR
=1.ok2
5-32
MA2480
FAIRCHIL.D
Winchester Disk
Servo Preamplifier
A Schlumberger Company
Linear Division Disk Drives
Description
Connection Diagram
8-Lead DIP
(Top View)
The fJA2480 provides termination, gain, and impedance
buffering for the servo read head in Winchester disk
drives. It is a differential input, differential output design
with fixed gain of approximately 100. The bandwidth is
guaranteed greater than 10 MHz.
The internal design of the f.lA2480 is optimized for low
input noise voltage to allow its use in low input signal
level applications. It is offered in 8-lead DI P (plastic) or
10-lead flatpak.
•
•
•
•
Low Input Noise Voltage
Wide Power Supply Range (8.0 V To 13 V)
Internal Damping Resistors (1.0 kil)
Functionally Compatible with SSI 101
Ne
-IN
v+
Ne
-OUT
v-
+OUT
Order Information
Absolute Maximum Ratings
Storage Temperature Range
Flatpak
Molded DIP
Operating Temperature Range
Lead Temperature
Flatpak (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1, 2
8L-Molded DIP
10L-Flatpak
Supply Voltage
Output Voltage
Differential Input Voltage
+IN
Device Code
fJA2480TG
-65°C to + 175°G
-65°C to + 150 0 G
OOG to 70°C
Package Code
9T
Package Description
Molded DIP
Connection Diagram
10-Lead Flatpak
(Top View)
0.93 W
0.79 W
15 V
15 V
± 1.0 V
•
+IN
Ne
v+
-IN
Notes
1. TJ Max -150"C for the Molded DIP, and 175"C for the Flatpak.
2. Ratings apply to ambient temperature at 25"C. Above this temperature,
derate the 10L·Flatpak at 5.3 mWrC, and the 8L-Molded DIP at
7.5 mWrC.
Ne
-OUT
v-
+ OUT
Ne
Ne
Order Information
Device Code
f.lA2480FC
5-33
Package Code
3F
Package Description
Flatpak
J1A2480
Equivalent Circuit
v+
+OUT
-OUT
a9
a24
R6
240Q
a6
R1
9kQ
R2
4.3kQ
a2S
R7
+IN
R4
500
-IN
R8
Q
-4-----+----'
R14
250Q
~----+-----~------~----------~------------~--------+-~------+--vEQOO710F
5-34
J,LA2480
Electrical Characteristics TA = 25°C, (V+)-(V-) =8.0 V to 13.2 V, unless otherwise specified.
Symbol
G
Characteristic
Condition
Gain (differential)
Min
Rp= 130 n, Vce= 12 V
92
Rp=130 n, Vee=12 V,
80
Typ
115
Max
Unit
138
150
TA = O·C to 70·C
VI = 2.0 mVp _ p
BW
Bandwidth (3.0 dB)
RI
Input Resistance
CI
Input Capacitance
VI
Input Dynamic Range (differential)
Rp = 130 n, Vee = 12 V
Is
Supply Current
Vee = 12 V
10
30
800
1000
MHz
1200
n
pF
3.0
mVp _ p
3.0
30
40
mA
600
mV
t:No
Output Offset (differential)
Rs=On,Rp=130n
Vn
Equivalent Input Noise
BW = 4.0 MHz, Rs = 0 n
PSRR
Power Supply Rejection Ratio
Rs = 0 n, f < 5.0 MHz
t::.GIt::.V
Gain Sensitivity (Supply)
t::. Vcc=±10%, Rp=130 n
± 1.3
%IV
t::.GIt::.T
Gain Sensitivity (Temp)
TA = 25·C to 70·C, Rp = 130 n
-0.2
%fOC
CMR
Common Mode Rejection (Input)
f< 5.0 MHz
Typical Applications
v...
SERVO
HEAD
R..
R..
V-
Notes
1. Leads shown for 8·lead DIP.
2. Req is equivalent load resistance.
3. Rp- RL • Req
RL'" Reo
4. G=.88 Rp
Where Rp = value from Note 3 (above) In ohms.
5-35
1.5
50
55
65
70
10
/lV
dB
dB
JIA2490
F=AIRCHILD
MFM/2,7 Data Separatorl
Encoder-Decoder
A Schlumberger Company
Linear Division Disk Drives
Description
Connection Diagram
28-Lead DIP
(Top View)
The 1lA2490 Data Separator/Encoder-Decoder chip provides a convenient, high performance means of converting
MFM or 2,7 encoded data derived from magnetic media to
an NRZ digital bit stream. Also included is an MFM or 2,7
encoder which converts NRZ data to MFM or 2,7 encoded
. serial formal suitable for recording on magnetic media. The
1lA2490 provides both MFM and 2,7 modes of operation
selectable with a select pen.
NRZ WRITE DATA
ADDRESS MARK ENABLE
WRrTECLOCK
WRITE GATE
28
WRITE MISSING CLOCK
RZ WRITE DATA
25
PRE-COMPENSAllON 2'
NRZ READ DATA
The Data Separator chip provides the complete oscillator
synchronization and data decode function required on controllers in the ST506 format, and disk drives in the ESDI
format. The chip also allows selectable precompensation
for those drives that may require it.
M
GATE (NOTE 1)
ADDRESS MARK FOUND
23
FILTER +
(NOTE 1)
FlLTER(NOTE 11
22
8
Yee
DELAY CAPACITOR
(NOTE 1)
AI FOUND
•
•
•
•
•
Data Rates To 25 Mbps
ESDI And ST506 Compatible Signal Definitions
Can Be Used In Drive. Or ControJler
Selectable MFM Or 2,7 Encoding/Decoding
Internal Generation/Detection Of MFM And 2,7
Address Marks
• Internal Write Precompensatlon With Externally
Programmed Value
yeo CAP1 (NOTE 1)
yeo CAP2 (NOTE 11
GROUND
20
1.
CHARGE PUMP SLOW (NOTE 11
CHARGE PUMP FAST (NOTE 11
18
NC
DELAY RESISTOR (NOTE 1)
READ REF CLOCK
RZ READ DATA
READ GATE
REFERENCE OSCILLATOR
MFM (2,7) SELECT
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
PLCC
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
PLCC (soldering, 10 s)
Internal Power Dissipation1, 2
28L-Ceramic DIP
44L-PLCC
Supply Voltage
TTL Inputs
Output Voltage
Note
1. Passive compensation node.
-65·C to + 175·C
-65·C to + 150·C
O·C to +70·C
Order Information
Device Code
1lA2490DC
300·C
265·C
2.50 W
1.92 W
6.0 V
6.0 V
6.0 V
NolM
1. TJ Max -150·C for the PLCC, and 175·C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 25·C. Above this temperature,
derate the Ceramic DIP at 16.7 mWrC, and the PLCC at 15.3 mWI·C.
5-36
Package Code
FM
Package Description
Ceramic DIP
MA2490
Connection Diagram
44-Lead PLCC
(Top View)
NC
7
•
5
4
:I
a
1
44
43
42
41
VCOCAP'
VCOCAP'
NC
FILTER + ,
FlLTER- ,
NC
VCCD
11
VCCA
1:1
GNDA
VCCD
13
GND.
DELAY CAPACITOR
A1FOUND
,.
CHARGE PUMP SLOW'
CHARGE PUMP FAST'
NC
NC
GND.
NC
"
NC
axt1710F
Note
1. Passive compensation node.
Order Information
Device Code
j.lA2490QC
Package Code
KI
Package DescrlpUon
Plastic Leaded Chip
Carrier
5-37
MA2490
Description of Lead Functions
Name
Description of Functions
Input Leads - All inputs are TTL
Address Mark Enable
This lead has two functions depending on the state of the WRITE GATE input lead.
If ADDRESS MARK ENABLE is enabled (LOW) and WRITE GATE IS DISABLED
(HIGH), then the 1lA2490 will go into an address mark search mode. The address
mark is the DC erased gap. If ADDRESS MARK ENABLE is enabled (LOW) and
WRITE GATE is enabled (LOW), then the 1lA2490 will not allow the RZ WRITE
DATA output to change state. This allows the writing of DC erased gaps (address
marks).
Write Gate
When enabled (LOW) this lead will allow the 1lA2490 to output encoded RZ data on
the Write Data lead. Its function is tabulated as shown:
Address Mark Enable
Write Gate
Resultant Function
Enabled
Enabled
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Write DC Erased Gap
Search for DC Erased Gap
Write RZ Data
Disabled
(LOW)
(LOW)
(HIGH)
(HIGH)
(LOW)
(HIGH)
(LOW)
(HIGH)
RZ Read Data
This lead receives the encoded RZ data pulses from the Read Channel in the disk
drive. This input is what the phase lock loop (PLL) locks up to when decoding read
data, and is also what will restart the internal VCO clock after READ GATE switches
from HIGH to LOW.
Read Gate
When enabled (LOW) this lead will allow the 1lA2490 to lock up to and read RZ
data from the disk. When this lead changes states, the internal VCO clock is turned
off. When this lead changes from HIGH to LOW (enabled), the first RZ READ DATA
INPUT will restart the internal VCO clock. When this lead changes from LOW to
HIGH (disabled), the first REFERENCE OSCILLATOR input pulse will restart the
internal VCO clock.
MFM/2,7 Select
This lead allows the user to select the desired code. A TTL low selects MFM and a
TTL high selects the 2,7 code.
Reference Oscillator
This is the reference clock input that the 1lA2490 phase lock loop syncs to when in
the write mode and the idle state. This input also restarts the VCO clock after
READ GATE switches from LOW to HIGH. The frequency of the reference oscillator
should be the same as the data rate. During write, the WRITE CLOCK input must
be phase locked to the signal on this lead.
Precompensation 2°
When this lead is enabled (HIGH) and PRECOMPENSATION 21 lead is disabled
(LOW), the precompensation value will be 5% of the 2f clock period.
Precompensation 21
When this lead is enabled (HIGH) and PRECOMPENSATION 2° lead is disabled
(LOW), the precompensation value will be 10% of the 2f clock period. If both
PRECOMPENSATION 2° and PRECOMPENSATION 21 leads are enabled (HIGH), the
precompensation value will result in a 15% correction of 2f clock period.
Write Missing Clock
This lead receives the signal (active low) from the controller to drop the clock pulse
out of bit 6 in the MFM "A 1" pattern. This lead should be enabled (LOW) only
when the "A1" pattern is present at the NRZ WRITE DATA input.
Write Clock
This lead receives the clock from the controller which clocks the NRZ WRITE DATA
(lead 28) input.
5-38
J.lA2490
Description of Lead Functions (Cont.)
Name
Description of Functions
Input Leads - All inputs are TTL (Cont.)
NRZ Write Data
This lead receives NRZ data from the controller along with WRITE CLOCK, for
encoding and subsequent writing on the disk. Data is valid at the rising edge of
WRITE CLOCK. This input assumes "Os" are a TTL low level.
Output Leads - All outputs are TTL
RZ Write Data
This lead is the RZ write data output to be written on the disk. This output is active
low. It is clocked out with the PLL oscillator (which is locked to the REFERENCE
OSCILLATOR).
NRZ Read Data
This lead is the NRZ decoded data output to the controller. This output assumes
"Os" are a TTL low level. NRZ Read Data is valid at the rising edge of Read/
Reference Clock.
Address Mark Found
A negative pulse output on this lead will indicate the presence of a DC erased gap.
If the 1lA2490 is able to count 16 clock intervals without a flux change being sensed
from the disk, then a "zero" will be clocked out at the first rising edge of a flux
change and will last for one clock period. The address mark Signal will occur at the
beginning of the sync field since that is usually where the first flux change occurs
after the DC gap.
"A1" Found
A negative pulse at this lead indicates that a missing clock has been found in the
MFM code. This pulse lasts for one VCO clock period and is associated with the
missing clock that was written in the "A1" pattern.
Read/Reference Clock
This lead will output the reference oscillator when READ GATE is disabled (HIGH),
or the internal J.LA2490 clock when READ GATE is enabled (LOW) and 16
consecutive zeros have been decoded (in sync field). This allows the phase lock
loop to lock up to the incoming RZ READ DATA before switching the READ/
REFERENCE CLOCK output from the REFERENCE OSCILLATOR INPUT to the
internal PLL's oscillator.
External Connection Leads
Filter
+
Filter -
This lead is the output of the charge pump and one of the differential inputs to the
veo. A negative pulse here will increase the veo frequency.
This lead is the output of the charge pump and the other (differential) input to the
VCO. A negative pulse here will decrease the VCO frequency.
This lead is the + 5.0 V supply -
DIP only.
Vee
VeeA
This lead is the
VCCD
This lead is the + 5.0 V supply for digital circuitry - PLCC only.
Delay Capacitor
The external capacitor that sets the delay time of the RZ READ DATA to one half
of a clock (VCO) period is attached here. Varying the capacitor value will vary the
centering of the incoming data in its phase-error window. The other side of the
capacitor should be tied to the + 5.0 V supply.
Delay Resistor
An external resistor tied from this lead to GROUND will set the delay time (in
conjunction with the capacitor on lead 9) of the internal delay network. A variable
resistor can be used to accurately adjust the centering of the phase margin window.
+ 5.0 V supply for analog circuitry - PLCC only.
5-39
•
J.LA2490
Description of Lead Functions (Cont.)
Name
Description of Functions
External Connection Leads (Cont.)
Charge Pump Fast
An external resistor from this lead to ground will determine the current that is added
to the CHARGE PUMP SLOW current that will be used by the charge pump to drive
the filter. This current is switched in, only during the sync fields, to decrease the
sync-up time of the phase lock loop. It is turned off when 16 consecutive zeros
have been decoded in the sync field, indicating a proper phase lock to data.
Charge Pump Slow
An external resistor from this lead to ground sets the operating current in the
Charge Pump for normal data reading. This current is always ON. The CHARGE
PUMP FAST and CHARGE PUMP SLOW current values are selected in conjunction
with the FILTER + and FILTER - component values to insure proper stability of the
phase lock loop during its operation.
Ground
This lead is the GROUND return for the chip - DIP only.
.Ground A
This lead is the GROUND return for the analog circuit on the chip - PLCC only.
Ground D
This lead is the GROUND return for the digital circuit on the chip - PLCC only.
VCO Cap 1
One side of the VCO frequency-setting capacitor connects to this lead. A negative
sloping transition on this lead corresponds to an "up" level of the VCO clock. The
other side of the capacitor connects to lead 23.
VCO Cap 2
One side of the VCO frequency-setting capacitor connects to this lead. A negative
sloping transition on this lead corresponds to an "up" level of the VCO clock. The
other side of the capacitor connects to VCO CAP 1 lead. This lead can be
connected to GATE lead if an in-phase start up is desired during the sync-up mode.
Gate
This lead can be tied to the adjacent veo CAP 2 lead for an in-phase start up of
the VCo. The internal CLOCK GENERATOR (see block description) will always turn
off the internal VCO clock when the READ GATE changes state. The VCO will
continue to free-run unless this lead is connected to VCO CAP 2 lead. The in-phase
start up can be used in those situations where a servo clock is available for
accurate frequency prediction of the anticipated incoming RZ READ DATA stream.
5-40
MA2490
Detailed Block Description
phase error between the occurrence of an incoming pulse
(from the SWITCH block) and the phase lock loop's oscillator (VCO). One output will control charge-up current to
the filter and the other output will control the discharge
current to the filter.
The following description gives a brief outline of the
blocks contained in the block diagram of the j.lA2490 Data
Separator. See Figure 1.
SWITCH - Connects either incoming read data (from the
disk drive read electronics) or a reference oscillator to the
phase lock loop for synchronizing the phase lock loop's
oscillator (VCO). When not reading data the SWITCH
block connects the reference oscillator to the PLO's input.
SINGLE SHOT DELAY - Provides a delay to allow the
phase detector to set up for a phase comparison between
incoming pulses and the phase lock loop's oscillator. The
timing of this delay should be one half the VCO's clock
period (quarter of the data rate) to assure a properly centered pulse in the Phase Lock Window. This delay circuit
has absolutely no effect on the Data Window and the
Data pulse phase relationships. The rising edges of the
Delayed Data pulse and the VCO clock pulse are inherently in phase at the phase detector input, no matter how
much the delay circuit is delaying the data. Since the Data
Window is set by inverting the VCO clock waveform, the
PHASE DETECTOR - Has two modes of operation - harmonic for read mode and non-harmonic for write and idle
mode. In the harmonic mode, the phase detector is enabled by the rising edge .of the incoming pulse. In the
non-harmonic mode, the phase detector is constantly enabled. The phase detector generates pulses to control the
CHARGE PUMP. The pulse width will correspond to the
Figure 1 Block Diagram
---
PRE-COMPENSATION
Vee
A. FOUNO
GND
20
2'
RZ
READ WRITE
GATE GATE
WRITE
DATA
AOORESS
MARK
ENABLE
--+---1
NRZ~~~ --+--Il-=~::~t---------+t-=~~:J
f--~-~r-::'::-l
READ/REF ....
CLOCK
WRITE
i+---j-- MISSING
CLOCK
NRZ
'--+--------t-- WRITE DATA
'----+---------j-- WRITE CLOCK
L-------------~r_-------i_-GATE
RZ READ
DATA
REFERENCE
OSCILLATOR
_-+_~~-:~=---,
--t. . . . . L.::::::..J
(IF)
DELAY
RESISTOR
DELAY
CAPACITOR
ADDRESS
MARK
FOUND
FAST SLOW
-.-
CHARGE PUMP
5-41
+
FILTER
VCO
CAP.
VCO
CAPz
MA2490
Delayed Data input will always be centered in the Data
Window.
enable all internal clocks. This provides the capability for
an in-phase start up for PLL. See Figure 2.
CHARGE PUMP - Provides either a charging or discharging current, as directed by the phase comparator, to the
externally connected loop filter. The value of the current is
internally switched between CHARGE PUMP FAST (a high
current) and CHARGE PUMP SLOW (a low current). The
higher current is used in the "sync-up" mode during the
reading of sync-fields, and the lower current is used during
reading data or ID fields.
CONTROL LOGIC - Decodes the input control lines from
the controller to provide internal control Signals to the
j.tA2490. It indicates to the rest of the chip when reading
or writing is being requested, and whether the MFM or 2,7
code is being used. During WRITE, it also presets the encoders to an encoded zero pattern.
READ/WRITE CONTROL - This block controls the switching of the 1lA2490 between READ and WRITE modes of
operation.
VCO - The Voltage Controlled Oscillator generates a continuous stream of clock pulses at a frequency rate that is
determined by the input voltage provided from the chargepump/filter combination, and an externally connected capacitor. The VCO output is. continually being phase
compared .to the pulse stream selected by the SWITCH
block. The input controlling voltage to the VCO is caused
to vary in such a way as to maintain phase lock with the
input pulses.
MFM & 2,7 ENCODER - This block is controlled by the
MFM/2,7 select lead. The MFM/2,7 select input will cause
incoming WRITE DATA IN to be encoded into either MFM
format or 2,7 format before it is clocked out as NRZ
WRITE DATA.
16 BIT REGISTER - The incoming data stream for both
read and write functions is shifted into this register for
processing purposes. During sync-up time this register is
used to count the number of incoming zeros to insure
proper synchronization to the RZ READ DATA. During
WRITE this register is used to enable precompensation
time-shifts at the appropriate time in the write data stream.
DC erased gaps in the RZ READ DATA stream are also
detected by using this shift register.
CLOCK GENERATOR - Provides the output of the VCO
to the rest of the Chip. The output of the CLOCK GENERATOR switches off at a change of state of the READ
GATE input, and turns back on at the first occurrence of
the RZ READ DATA (if READ GATE is enabled), or the
REFERENCE OSCILLATOR (if READ GATE is disabled).
The GATE lead can be tied to the VCO CAP lead to start
the VCO in-phase with incoming RZ DATA or REFERENCE OSCILLATOR.
ADDRESS MARK DECODE - During read mode, when address mark enable is active this block finds DC erased
gaps in the incoming bit-stream that are at least 16 bits
wide. A signal is sent to the controller to indicate a gap
has been found (ADDRESS MARK FOUND).
ZERO PHASE START UP - This block turns off all internal clocks whenever the READ GATE input changes state,
and also toggles the GATE lead. This lead can be tied to
one of the VCO capaCitor leads to turn off the VCO at
the same time. The first incoming bit that is to be fed into
the phase lock oscillator (RZ READ DATA for READ
GATE enabled, the REFERENCE OSCILLATOR for READ
GATE disabled) will disable the gate function and allow
the VCO to start in-phase with the incoming data, and. will
MISSING CLOCK DECODER (MFM) -Immediately following the sync-field in an MFM encoded bit stream there is
a pattern written that is not allowed in the MFM encode
process. The byte written is generally "A1," and the
CLOCK transition that should have occurred on the sixth
bit is not written. On read-back this missing CLOCK bit is
Figure 2 In-Phase Start up Timing for GATE Output Tied to Lead 23 (VCO CAP)
READGA11:
(INPUT)
________
READ DATAl
REF CLOCK
~
(INPUT)
~x~
__________________________
__________________
~n~~~
GATE
(OUTPUT)
INTERNAL CLOCK
5-42
}lA2490
detected by the Missing Clock Decoder and a pulse is
generated. This pulse is used for timing alignment in the
controller.
signals and levels. When utilized within the drive, the interface becomes compatible with ESDI (Enhanced Small Disk
Interface) the proposed industry standard for higher capacity drive.
PHASE UP - This block lines up the ~2490's clock with
the WRITE CLOCK input to assure proper phasing to
clock out the WRITE DATA. The WRITE CLOCK input
must be synchronized with the REFERENCE OSCILLATOR.
Operation of the ~2490 is dependent on the format in
which the sectors of the disk are written. The principal
requirement is the provision of an adequately long synchronization field prior to valid data. For the ~490, this
field must contain an all "zeros" (NRZ) data pattern for a
minimum of 32 data bit intervals (NRZ) between assertion
of READ GATE and the beginning of valid data (including
address marks). Such a format as is suggested in the
ST506 interface specifications is suitable. With the exception of the provision for leading "address marks," the format suggested in ESDI interface documents is also
suitable.
MFM & 2,7 DECODER - Translates the encoded RZ
READ DATA into decoded NRZ DATA OUT before sending it on to the controller. The CONTROL LOGIC block
will determine if the MFM decode or 2,7 decode algorithm
is to be used.
MISSING CLOCK GENERATOR (MFM) -In MFM
this block allows the CLOCK transition in the 6th
the ID byte" A1" to be stripped out before being
as write data to the disk. This block is controlled
controller.
mode,
bit of
sent out
by the
Read
When not writing, the internal PLL remains phase and frequency locked to the REFERENCE OSCILLATOR input until the READ GATE input is asserted by the controller.
When ADDRESS MARK enable is asserted without asserting READ GATE or WRITE GATE, the ~2490 looks for
the DC erased gap which should be at least 16 bits long.
After detecting 16 bits of DC erased gap, a pulse appears
at ADDRESS MARK FOUND lead at the first flux transition
on the READ DATA lead. This pulse disappears with the
arrival of the second pulse on the READ DATA lead. It is
assumed, that this flux transition is the first bit of the encoded zero sync-field. ADDRESS MARK ENABLE should
be disabled at this point and READ GATE should be asserted. ADDRESS MARK ENABLE and READ GATE
should not be asserted at the same time.
DIGITAL PRECOMP - Four values of precompensation delays can be selected through two digital inputs. The precompensation written is dependent on the bit position in
the write data stream. Its purpose is to cause a bit to be
written early or late to offset the effects of bit-crowding
(peak shifting) of closely spaced flux transitions on the
disk. The four values of precompensation allowed are selectable between 0%, 5%, 10% and 15% of the VCO
clock period.
ANALOG PRE-COMP - Works with the Digital Precomp
block to actually inject the early or late write-time for a
given WRITE DATA transition.
Functional Description
As discussed before, assertion of READ GATE is presumed to occur during the PLO sync portion of the track
format. At the assertion of READ GATE, the PLL changes
to phase lock mode. It enters a "fast acquisition" mode
The ~2490 can reside in either the disk controller or the
drive itself. When it resides in the controller, the interface
signals are compatible with the industry standard ST506
Figure 3 READ/REF Clock Output Timing During Read Sync-up at the Time 16 Zeros Have Been
Decoded in the Preamble Sync Field.
R~GA~
-,~
___________________________________________________
REFOSC
(INPUT)
(INTERNAL IF CLOCK)
READ/REFCLOCK
(OUTPUT)
5-43
J,LA2490
and attempts to lock on to the incoming MFM (or 2,7) RZ
READ DATA pulses using pattern sensitive phase discrimination and fast loop dynamics. The j.lA2490 makes the
important assumption that the pattern written in this field
represents encoded zero data bits.
WRITE CLOCK following the assertion of WRITE GATE.
Prior to clocking out the first encoded data bit, an encoded zero pattern (preset internally) is clocked out for an
integral number of WRITE CLOCK intervals (aSSOCiated
with internal processing, 7 clock periods for MFM and 9
clock periods for 2,7). See Figure 4.
When lock is achieved and 16 successive zero data bits
have been decoded, the internal PLL switches to "slow
track" mode in preparation for encountering the unique address mark byte. NRZ READ DATA OUT lead (which was
high until now) switches to the decoded output pattern
and READ/REFERENCE CLOCK output is switched from
the READ/REFERENCE CLOCK to the PLL's clock. See
Figure 3.
The alignment of encoded RZ WRITE DATA pulses with
respect to the internal VCO clock is modified by the
j.lA2490 according to precompensation rilles shown in Table 1a. The amount of precompensation is one of four
values (including zero) set by the state of the two PRECOMPENSATION SELECT inputs. The actual precompensation value is given in Table 1b as a percent of the
oscillator period. The percentages are ± 0%, ± 5%, ± 10%,
and ± 15% of the 2f clock.
For MFM, the address mark is fixed internally as "A1"
(HEX) or 10100001 where the clock pulse associated with
bit 6 is not present. "A1" FOUND, a pulse from the
j.lA2490 to the controller, is asserted at the rise of the
VCO CLOCK associated with bit 6 of the address mark
byte and is reset at the fall of the VCO CLOCK.
For MFM, unique address mark bytes may be written by
supplying an NRZ data stream representing "A1" (HEX)
and asserting the WRITE MISSING CLOCK line at the fall
of WRITE CLOCK for bit 1. See Figure 5. WRITE MISSING CLOCK must be negated at the fall of WRITE
CLOCK for bit 8 of the "A 1" byte. This suppresses the
normal "clock" transition for bit cell 6. The assertion or
deassertion of WRITE MISSING CLOCK line does not
have to be synchronous with the WRITE CLOCK. The level of WRITE MISSING CLOCK SIGNAL does not have any
effect on the operation of j.lA2490 in 2,7 mode.
NRZ DATA OUT and CLOCK are supplied continuously
thereafter by the j.lA2490 until negation of the READ
GATE signal by the controller. At that point the PLL is
resynchronized with the REFERENCE OSCILLATOR and
the reference clock is presented at the READ/REFERENCE output.
Writing proceeds continuously until negation of WRITE
GATE. Only the transitions (or lack thereof) associated
with the WRITE DATA bit valid at the last rise of WRITE
CLOCK will be written. Note that because of the aforementioned internal processing delays the writing of the last
flux transitions will occur seven clock intervals for MFM (or
nine clock intervals for 2,7) after the negation of WRITE
GATE. Null bits appended to the controller write data
stream allow for the finite turn-off time of write current.
Write
Write operations are begun at the assertion of WRITE
GATE by the controller. The PLL remains phase and frequency locked to the REFERENCE OSCILLATOR input all
the time during the WRITE MODE. WRITE CLOCK must
be synchronized to the READ/REFERENCE CLOCK and
the jitter should be less than ± Y4 of a period for reliable
data transfer. The internal clock will be realigned to the
write clock to assure reliable data transfer. WRITE DATA
is sampled for processing on the first rising edge of
Figure 4 Write Data Transfer Timing
WRITE CLOCK
WRITE DATA
(INPUT)
WRITE GATE
(INPUT)
I~--------------~------------I+f..--INTERNALLY PRESET ENCODED ZERO PATTERN
ENCODED WRITE DATA
HZ WRITE DATA
(MFM OUTPUT)
5-44
MA2490
Figure 5 Missing Clock Generation
BIT POSITION
6
o
"AlII DATA
WRITE MISSING CLOCK
-,
I~.
________________
r
~
ENCODED PATTERN
ENCODED PATTERN
WITH DROPPED CLOCK
CDCDCDCDCDCDCDCD
C = CLOCK TIME POSITION
D - DATA TIME POSmON
Recommended Operating Conditions
Symbol
Condition
Characteristic
Vcc
Supply Voltage
Min
Typ
Max
Unit
4.75
5.0
5.25
V
Vcc = 5.0 V
Icc
Supply Current
200
TA
Ambient Temperature
fOATA
Input Data Rate
TREF
Reference Oscillator Clock Period
40
WREF
Width of Reference Oscillator Clock
10
TWFO
Width of Encoded RZ Data Pulse
0
25
mA
70
C
25
Mbps
ns
ns
Y2T
ref
TRZO
Pulse Width of RZ Read Data
10
5-45
ns
JLA2490
Electrical Characteristics TA = 25°C, Vee = 5.0 V, unless otherwise specified.
DC Characteristics
Symbol
Characteristic
Condition
Min
Typ
Vee - 2.0
Vee - 1.6
VOH
Output Voltage HIGH
Vee = Min, IOH = Max
VOL
Output Voltage LOW
Vee = Min, IOL = Max
IIH
Input Current HIGH
VIH
V
80
IlL
Input Current LOW
VIL = 0.4 V
195
IOH
Output Current HIGH
IOL
Output Current LOW
VIH
Input Voltage HIGH
VIL
Input Voltage LOW
= 2.7
Max
Unit
0.5
V
V
!1A
!1A
!1A
-800
10
JJA
V
2.0
0.8
V
AC Characteristics
Condition
Min
Max
Unit
TLock R
Positive input
transitions after Read
Gate· goes LOW
Gate not connected to VCO
capacitor
32
TBD
Ref
Clock
Period
TLock w
Positive input after
Read Gate goes HIGH
until PLL locks to
reference oscillator
Gate not connected to VCO
capacitor
16
TBD
Ref
Clock
Period
Decode MFM
Number of clock cycles
required until output
RZin NRZ out
MFM
1
Ref
Clock
Period
Decode 2,7
Number of clock cycles
required until output
(2,7)
5
Ref
Clock
Period
Encode MFM
Number of clock cycles
accompanying input
data to encoded write
data NRZin RZout
MFM
7
Ref
Clock
Period
Encode 2,7
Number of clock cycles
accompanying input
data to encoded
write data
(2,7)
9
Ref
Clock
Period
KI
Charge Pump and
Filter Gain
n = number of VCO
cycles between
Data Bits,
MFM: 1";;n";;3
2,7: 2";;n";;7
Symbol
Characteristic
Typ
Slow
5
21TnGjR eps
Fast
5
21TnC,Reps
VControl
II
Rep!
±400
Differential Voltage
Swing of Charge Pump
5-46
Amps!
radian
mV
MA2490
Electrical Characteristics (Cont.) T A = 25°C, Vee = 5.0 V, unless otherwise specified.
AC Characteristics
Symbol
Characteristic
Condition
Min
Typ
Measured from filter output
Unit
Max
Kyco
VCO Gain Constant
fMAX YCO
Maximum VCO
Frequency
fyeo
VCO Center Frequency
Tolerance
±30
fTEMPCO
VCO Center Frequency
Temperature Coefficient
-5
Radians/
sec-volt
0.5 "-'Vco
70
MHz
%
%/oC
External Component Selection
Symbol
Characteristic
Min
Capacitor1
Typ
Max
Unit
kn
kn
Cyeo
VCO Frequency Set
Rcps
Charge Pump Slow Resistor
0.7
5.0
50
RCPF
Charge Pump Fast Resistor
0.7
5.0
50
Css
Delay Capacitor2
Rss
Delay Current Setting Resistor2
Notes
1. cvco -1/(2K) (fveo)
2. Delay TIme = Tveo/2
5.0
pF
10
0.1
Components
pF
kn
1.5
= (O.673)RssC..
Table 1a Precompensation Patterns
2,7 Precompensatlon Patterns
Past
MFM Precompensation Patterns
Present
Future
Past
Present
Future
+3
+2
+1
Write Bit
-1
-2
-3
+2
+1
Write Bit
-1
-2
0
1
1
0
0
0
0
0
0
0
0
0
ON TIME
ON TIME
EARLY
LATE
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
ON TIME
ON TIME
EARLY
LATE
0
0
0
0
0
1
0
1
1
0
1
5-47
1lA2490
path as possible to the chip supply or ground. The chip
itself should be we" decoupled with the decoupling capacitors placed close to the chip. A" leads on the timing and
filter components should be kept as short as possible.
Table 1b PrecompensaUon Values
Precomp. MSB
Value LSB
BIt Interval Shift %
Of 2f Clock
0
0
1
1
0
1
0
1
±O%
±5%
±10%
±15%
A good ground plane should be used in the vicinity of the
Data Separator Chip. Digital signals should be kept away
from the vicinity of the Chip. Wire wrap configurations
should be avoided for best performance. A" filter capacitors and single shot delay capacitors should be connected
to the Vee lead.
Table 2 2,7 Code Pattern
Data
A
B
0
0
1
1
1
1
1
1
0
1
0
0
1
1
C
Code
D
8
7
6
5
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
1
0
1
0
0
4
VCO CapacItor
3
2
&0
40
0
0
0
0
0
0
0
1
0
VCO
Freq
MHz
25
20
15
10
5
50
40
30
20
10
CYCO
VCO cap
12
18
25
39
85
pF
pF
pF
pF
pF
-
\
0
0
Ca.
Delay
Cap
R..
Delay
Res
10
12
16
24
49
1.5
1.5
1.5
1.5
1.5
pF
pF
pF
pF
pF
1
CVCD - 2000 Ivco
1\
0
0
I\"
I'
r---.
10
Table 3 Tabulated Values for VCO and SIngle Shot
Data
Rate
Mbps
\
\
20
40
-
~
100
80
&0
veo CAPACITOR-pF
kn
kn
kn
kn
kn
Delay Circuit Values
&0
40
Recommended Charge Pump and Filter Component
Values for 10 Mbps OperatIon.
Cj - 0.47 /IF
RI == 220 n
Rep! = 5.1 kn
Cp = 0.0047 /IF
Reps = 5.1 kn
~
II
I
30
~
zUI
:::I
..51
a:
Layout PreoauUons
A careful layout is required when attaching the critical timing components to the Data Separator. Connect the VCO
capacitor and the Single Shot capacitor as close to the
chip as possible. This will help cut down on the amount
of noise picked up from other switching components nearby on the board that will affect the timing. The filter com~
ponents should also be placed as close to the chip as
the layout wi" allow, with the returns making as short a
20
0
g
\
\
C
1
~~ .......
10
o
o
_
ss - (1.34811vco Ass
'1\ \
\
\
1\
\ \ ~.
I\. ~""""-O~~
~"4!'''''' r-....
r-
10
20
30
Css-pF
5-48
--
40
so
JlA2490
Figure 6
ST506
~---------------------INDEX------------------------~
t--------------------DRIVE SELECTED
ENCDDED WRITE DATA
ENCDDED READ DATA
-------------------+1
1J.A2490
NRZ WRITE DATA
DATA
NRZ WRITE CLOCK
SEPARATOR
ADDRESS MARK ENABLE
AND
ENCODER I+------READ GATE ------I
WRITE GATE-----i
PRE·COMP.ENSATION VALUE
PRE·CDMPENSATION VALUE
DRIVE
CONTROLLER
~-----INDEX-----~
CR0431DF
5-49
MA2490
Figure 7
ESDI
\-----------DRIVESELECTED----------+I
~-----------------------INDEX----------------------~
NRZ WRITE DATA
ENCDDED WRITE DATA
ENCDDED READ DATA
PRE-COMPENSATION VALUE
PRE-COMPENSATION VALUE
ADDRESS MARK ENABLE
ADDRESS MARK FOUND
CONTROLLER
READ GATE
WRITE GATE
WRITE FAULT
DRIVE
1+------- STEP --------------I
DIRECTION
TRACK ZERO
~------INDEX
--------+I
DRIVE SELECT 2
Typical Hook-up Diagram
Vee
Vee
-=-
Rss
L
Reps
-=-
~
eveo
1:'f f '1p
V
Repf
REFERENCE
OSCILLATOR
READ REFERENCE
CLOCK
READ GATE
RZREADDATA
NRZ READ DATA
RZ WRITE DATA
WRITE CLOCK
NRZ WRITE DATA
A1 FOUND
WRITE GATE
WRITE
MISSING CLOCK
ADDRESS MARK
ENABLE
ADDRESS MARK
FOUND
GND
Vee
MFM(2,7)
SELECT
PRE-COMPENSATION
VALUE
5-50
J.LA2580
Winchester Disk
Servo Preamplifier
FAIRCHIL.D
A Schlumberger Company
Preliminary
Linear Division Disk Drives
Description
Connection Diagram
8-Lead DIP and 50-8 Package
(Top View)
The !lA2580 provides termination, gain, and impedance
buffering for the thin film servo read head in Winchester
disk drives. It is a differential output design with fixed gain
of approximately 250. The bandwidth is guaranteed greater
than 30 MHz.
The internal design of the /.lA2580 is optimized for low
input noise voltage to allow its use in low input signal
level applications. It is offered in 8-lead ceramic DIP,
10-lead Flatpak, and an SO-8 package suitable for surface
mounting.
• Low Input Noise Voltage, Typ 0.5 nV/YHz
• Wide Power Supply Range (8_0 V to 13 V)
• Internal Damping Resistors (1.0 kQ)
NC
-IN
V+
NC
-OUT
v-
+ OUT
Order Information
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP and Flatpak
SO-8
Operating Temperature Range
Lead Temperature
Ceramic DIP and Flatpak
(soldering, 60 s)
SO-8 (soldering, 10 s)
Internal Power Dissipation 1, 2
8L-Ceramic DIP
10L-Flatpak
SO-8
Supply Voltage
Output Voltage
Differential Input Voltage
+IN
Device Code
-65°C to + 175°C
-65°C to + 150°C
O°C to 70°C
Package Code
Package Description
6T
KC
Ceramic DIP
Molded Surface Mount
!lA2580DC
!lA2580SC
Connection Diagram
10-Lead Flatpak
(Top View)
•
+IN
1.30 W
0.79 W
0.81 W
15 V
15 V
± 1.0 V
NC
- IN
V+
NC
-OUT
V-
+ OUT
NC
NC
Notes
1. TJ Max = 150·C for the 50-8. and 175·C for the Ceramic DIP and
Flatpak.
2. Ratings apply to ambient temperature at 25·C. Above this temperature,
derate the 8L-Ceramic DIP at 8.7 mW rc, the 10L-Flatpak at
5.3 mWrC, and the SO-8 at 6.5 mWrC.
Order Information
Device Code
/.lA2580FC
Package Code
3F
Package Description
Flatpak
Description Of Lead Functions
Name
Description of Functions
+IN
-IN
NC
Positive Differential Input
Negative Differential Input
V-
Negative Differential Supply with respect to Vcc.
Positive Differential Output
Negative Differential Output
Positive Differential Supply with respect to Vcc
No Connection
+OUT
-OUT
V+
NC
5-51
MA2580
1lA2580
Electrical Characteristics TA=25 C, (V+)-(V-) =8.0 to 13.2 V, unless otherwise specified.
Symbol
Condition
Characteristic
n,
Min
Max
Unit
Rp=100
BW
Bandwidth (3 dB)
VI = 0.5 mVp.p
RI
Input Resistance
300
n
CI
Input CapaCitance
35
pF
n,
(V+)-(V-) = 12 V
Typ
Gain (differential)
G
250
30
VI
Input Dynamic Range (Differential)
Rp=100
Is
Supply Current
(V+)-(V-) = 12 V
tiNo
Output Offset (Differential)
Rs = 0, Rp = 100
Vn
PSRR
(V+)-(V-) = 12 V
28
n
600
Equivalent Input Noise
BW=4.0 MHz
Power Supply Rejection Ratio
Rs = 0, f = 5.0 MHz
50
IlGIV
Gain Sensitivity (Supply)
11 (V+)-(V-) ±10%, Rp=100
IlG/T
Gain Sensitivity (Temp)
TA = 25°C to 70°C, Rp = 100
CMR
Common Mode Rejection (Input)
f = 5.0 MHz
Typical Application (Notes 1-4)
V+
SERVO
HEAD
REO
V-
65
Reo
0'"''''''
Notes
1. Leads shown for B-leed DIP.
2. Rea is equivalent loed resist""(l8.
RL • Rea
3. R p - - RL + Rea
4. G-2.5 Rp
Where Rp - value from Note 3 (above) in ohms.
5-52
MHz
1.0
mV pop
40
mA
600
mV
nV/YHz
0.6
65
n
0.90
0.5
n
0.16
60
70
dB
%IV
°fi,I"C
dB
""
,
',"
'
"
"
"
'"
18
MA 105 • MA30S
MA30SA • MA376
Voltage Regulators
FAIRCHILD
A Schlumberger Company
Linear Division Voltage Regulators
Description
Connection Diagram
a-Lead Metal Package
(Top View)
The pA 105/305/305A/376 are monolithic positive voltage
regulators constructed using the Fairchild Planar Epitaxial
process. Applications for these devices include both linear
and switching regulator circuits with output voltages greattlr
than 4.5 V. These devices will not oscillate when confronted with varying resistive and reactive loads and will start
reliably regardless of the load within the ratings of the circuit. They also feature fast response to both load and line
transients. Used independently, the pA105/305 will supply
12 mA, the pA305A, 45 mA and pA376, 25 mAo The
pA 105 is specified for the extended temperature range of
-55°C to + 125°C. The pA305/376/305A are specified for
O°C to +70°C operation. The pA105/305/305A are in an
8-lead TO-5 package and the pA376 is available in the
space and cost saving DIP.
REG
OUT
BOOSTER
FEEDBACK
OUT
COMMON
Lead 4 connected to case.
• Low Standby Current Drain
• Adjustable Output Voltage From 4.5 To 40 V
• High Output Currents Exceeding 10 A With External
Components
• Load Regulation Better Than 0.1%, Full Load With
Current-Limiting
• DC Line Regulation Guaranteed At 0.03%/V
• Ripple Rejection Of 0.01%/V
• Available In Extended Temperature Range
Order Information
Device Code
pA105HM
pA305HC
pA305AHC
Package Code
5W
5W
5W
Package Description
Metal
Metal
Metal
Connection Diagram
a-Lead DIP
(Top View)
Absolute Maximum Ratings
Storage Temperature Range
Metal Can
Molded DIP
Operating Temperature Range
Extended (pA 105)
Commercial (pA205,
pA305A, pA376)
Lead Temperature
Metal Can (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1,2
8L-Metal Can
8L-Molded DIP
Input Voltage
pA 105, pA305A
pA305, pA376
Input/Output Voltage Differential
-65°C to + 175°C
-65°C to + 150°C
CURRENT
LIMIT
REG OUT
BOOSTER
COMP
SHUTOOWN
OUT
-55°C to +125°C
UNREGIN
COMMON
1.00 W
0.93 W
FEEDBACK
REF BYPASS
Order Information
Device Code
pA376TC
50 V
40 V
40V
Notes
1. TJ Max = 1.50°C for the Molded DIP, and 175°C for the Metal Can.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 8L·Metal Can at 6.7 mWrC, and the 8L·Molded DIP at 7.5
mWrC.
6-3
Package Code
9T
Package Description
Molded DIP
p.A 105 • p.A30S
p.A30SA • p.A376
Equivalent Circuit
.------_t_-------......- -......-
UNREGULATED IN
R10
600Q
BOOSTER OUT
+-w.........l - - - CURRENT LIMIT
~---
REGULATED OUT
+-__,._---- ~~~~nON
::I--+-t---4-- FEEDBACK
.......- - t - - - + - - - + - - - - REFERENCE BYPASS
.......~-~-~-------+--~------COM~
EQOO620F
~105
Electrical Characteristics TA = 25°C unless otherwise speeified 1
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
VIR
Input Voltage Range
8.5
50
V
VOR
Output Voltage Range
4.5
40
V
VI-VO
Input/Output Voltage Differential
VR LINE
Line Regulation
VR LOAD
Load Regulation2
3.0
30
VI-VO < 5.0 V
0.025
0.06
VI-VO> 5.0 V
0.015
0.03
TA = 25°C
0.02
0.05
TA = 125°C
0.03
0.1
TA=-55°C
0.03
0.1
0.003
0.02
0.3
1.0
1.7
1.81
O 0.1 f.LF
0.002
TA=25°C,
6-4
225
300
V
%/V
%
%/V
%
V
%
375
mV
IlA 105 • IlA305
IlA305A • IlA376
/JA 105 (Cont.)
Electrical Characteristics TA
Symbol
=
25°C unless otherwise specified 1
Characteristic
Condition
ISCD
Standby Current Drain
VI = 50 V
S
Long Term Stability of FBSV
TJ=125°C
Min
ITA = 25°C For End Point
Measurement
Typ
Max
Unit
0.8
2.0
mA
0.1
1.0
%/1000
hrs
Typ
Max
/JA305A
Electrical Characteristics T A = 25°C unless otherwise specified 1
Symbol
Characteristic
Condition
Min
Unit
VIR
Input Voltage Range
8.5
50
V
VOR
Output Voltage Range
4.5
40
V
VI-VO
Input/Output Voltage Differential
VR LINE
Line Regulation
VR LOAD
Load Regulation
3.0
30
VI-Vo<5.0 V
0.025
0.06
VI - Vo > 5.0 V
0.Q15
0.03
O 0.1 IlF
TA = 25°C,
0.4
0.02
0.005
10Hz < f < 10kHz I CREF = 0
n,
0.03
0.003
V
%/V
225
ITA = 25°C For End Point
Measurements
300
375
mV
0.8
2.0
mA
0.1
1.0
%/1000
hrs
/JA305
Electrical Characteristics TA = 25°C unless otherwise specified 1
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
VIR
Input Voltage Range
8.5
40
V
VOR
Output Voltage Range
4.5
30
V
VI-VO
Input/Output Voltage Differential
3.0
30
VR LINE
Line Regulation
VI-Vo<5.0 V
0.025
0.06
VI-VO > 5.0 V
0.015
0.03
V
%/V
/JA 105 • /JA305
/JA305A • /JA376
JlA305 (Cont.)
Electrical Characteristics TA = 25°C unless otherwise specified 1
Symbol
VR LOAD
Characteristic
Condition
Load Regulation 2
O~
IL ~ 12 mA
Min
Rsc = 10
Rsc = 15
Rsc = 10
tNI/!:No
Ripple Rejection
CREF = 10 !.IF, f = 120 Hz
Ts
Temperature Stability" of FBSV
O°C ~ T A ~
FBSV
Feedback Sense Voltage
No
Noise
Typ
Max
Unit
T A = 25°C
0.02
0.05
%
T A = 70°C
0.03
0.1
T A = O°C
0.03
0.1
0.003
0.02
0.3
1.0
1.7
1.81
+ 70°C
1.63
I
10Hz ~ f ~ 10kHz CREF = 0
ICREF
n,
VCLS
Current Limit Sense VoltageS
ISCD
Standby Current Drain
VI =40 V
S
Long Term Stability of FBSV
TJ = 125°C
JlA376
Electrical Characteristics O°C
Symbol
n,
n,
n,
~
Rsc = 10
Vo=O V
> 0.1
0.005
%
V
%
0.002
!.IF
225
T A = 25°C
%/V
ITA = 25°C For End Point
Measurements
300
375
mV
0.8
2.0
mA
0.1
1.0
%/1000
hrs
TA .;;; 70°C
Characteristic
Condition
Min
Typ
Max
Unit
VIR
Input Voltage Range
9.0
40
V
5.0
37
V
VOR
Output Voltage Range
VI-VO
Input/Output Voltage Differential
VR LINE
Line Regulation
VR LOAD
Load Regulation
3.0
O°C
~TA ~
0~IL~25
0.03
70°C
mA
Rsc=O
Ripple Rejection
VCLS
Current Limit Sense Voltage
ISCD
Standby Current Drain
VREF
Reference Voltage
V
%/V
0.1
Rsc = 0
Rsc= 0
!:J.VI/!:No
30
TA = 25°C
n,
n,
n,
TA = 25°C
0.2
TA = 70°C
0.5
TA = O°C
0.5
f = 120 Hz, TA = 25°C
0.1
%/V
2.5
mA
1.80
V
360
VIN = 30 V, TA = 25°C
1.60
1.72
%
mV
Notes
1. These specifications apply for input and output voltages within the
ranges given, and for a divider impedance seen by the feedback
terminal of 2.0 kn, unless otherwise specified. The load and line
regulation specifications are for constant junction temperature.
Temperature drift effects must be taken into account separately when
the unit is operating under conditions of high dissipation.
2. The output currents given, as well as the load regulation, can be
increased by the addition of external transistors. The improvement factor
will be roughly equal to the composite current gain of the added
transistors.
3. With no external pass transistor.
4. Temperature stability is defined as the percentage change in output
voltage for a thermal variation from room temperature to either
temperature extreme,
6-6
IlA 105 • IlA305
IlA305A • IlA376
Typical Performance Curves
1
~
~
~
'.0
....~,.:::... ...... T1 = ,Joc
0.0'
-~ •••.•....••.••....••
•••••••
~-f---r--+·-···-··~·~.~..-.. ~T~
0.02
~
~-f---r--+----4---+..-"..•..,j.---+---I
........
TA:::: -55°C
5
........
5o O.031--+--+--+--l--+--+----~-i
-RSr
Short Circuit Current vs
Temperature
Current-Limiting Characteristics
Load Regulation
~ll ~
0.6
I:;
I:;
0
w 0.4
>
~w
iw
t!'~ : ~
ru
,---
O,
Rs~ =
0.04 0~-.l-.....J,-....I..-...1'O,-..L-,.LS-..L----l
20
00
'r
a;
a;
:>
-
~}--
.........
...0a;
30
0
en
'0
..
40
r....
t--....
. . . . r--. W"f...""" .........
Rr=I20~ r--. ~ r--....
20
-75 -50 -25
OUTPUT CURRENT-mA
LOAD CURRENT-mA
Rsc = 10 Q
f' t--.,!'sc = 'S"
:J:
Q
20
....
t::
:>
u
a;
!
!
'0
.........
30
u
i l - 'fi- II :
~t- ~+, -
0.2
a;
..
I
::
0
..
.
E
"~
>
'--;f- -
1\
>
I
w 0.8
25
50
75
100 125 150
TEMPERATURE-oC
PC09060F
I
~ -0.021---+-"1"',"":"+''-"-,"'"'!'~::t-~~I--±=--I
~
'\ \.
\ ' •••••TA--SSOC
,,
~
.~.
g -O.06I--+--+--+H--+---Hr---+----i:--1
~
"~
!i:J
...z
1 t--+:--!
a:
a;
-0.081---t-t-1-+c+--I-tiTA= 126°C \
'r--...
..........
.........
2.2
o
2.0
25
50
75
100 125 150
~
~
1'-..
0.0 2
r---....:
\
,
Standby Current Drain vs
Input Voltage
~
g;
~o.oo 2
I- CREF = 10 /-t F
1
f;3!o
1jHZI
0.00
100
'.2,---,---r-....,-...,...-,.---.--,----,
'0
125
1 ,.,\-.....j--+-+---l---+--+-kod
~
I
EF
-
"~
~o.ooS
75
..
0.05
w 0.0
/"
""";;;::::
20
'0
5
~
OUTPUT VOLTAGE-V
=
~
V
TEMPERATURE-OC
2.4
Yo 10V
TA=25°C_
~
....V
so
......
,
-'.
YoI= 4.SY-
25
........
illa;
Supply Voltage Rejection vs
Input/Output Voltage Differential
o.
8
6
~
.......
TEMPERATURE-oC
Minimum Input Voltage vs
Temperature
50-25
I"--. I'....
u
-75 -50 -25
- 75
.......
:>
0.2
V
\
~ 2.8
I
w
~ 2.6
w 0.3
LOAD CURRENT-mA
./
3.0
0.5
w
en
zw 0.4
en
~=wc,
RlIl1';'=2~kQ
Rl=l.11 Yo
I I
lo~5.0mA-
>
\
~
>
I
w
0
....
III -0.04 ~T-A.j.=-,..-+o-c-'.\cT.--+----4t---+-",,"+--l
~
3.2
0.6
J
ROr 'j"-
"Y':-..
if.
Optimum Divider Resistance
Values
Current Limit Sense Voltage vs
Temperature
Load Regulation
20
=0 p.F
1l~
TA
.......
L--1__-b~.~'+.__~~t-=~25~O~C~~~__~
0.9
.
= -ssoc ......................... .
'.0 I
I .·6
INPUT/OUTPUT VOLTAGE OIFFeRENTlAL-V
6-7
W
J..-f-t
i{'" ••.•.••.••..
TA = 125"C
............................
.......
O··,l:O-.L-20L-L--30
L..L--'
..L..L-.J
..
INPUT VOlTAGE-V
•
IlA 105 • IlA305
IlA305A • IlA376
Typical Performance Curves (Cont.)
Regulator Dropout Voltage
Minimum Output Voltage vs
Temperature
Transient Response
~'-"-'--'I--'R-SC-=~'0-Q'
4.5
>
I
w
....
.~... ••••
...... ......r . ·
IL = 2omA=+-_f--l
······~
·~
••• ~L=10mA
-=.. P',,*""'""I
•••• ..... ··J,o:r·;:•••
IL =5.0mA
!l"g
..
/
4.0
3.5
V
,/
!;
....
:>
0
....v
3.0
••••••••
""'::75=---±50=--""2'=5-+--:!25=-"'50!::---:O75"-"'100~""'!'25
2.5
-75
-so
TEMPERATURE-oC
0
~
1~.Y....
=r4
1-_-f-_-+_OUT6~~:~~~AGE
-401--+--+--1--+--+---1
w
"
~
g
I
/'
-
25
-25
50
75
100
~
~
1.00
1-+--t.....I-+-+-+"'I"t..--k--+-l
\
fA
.
~
ffi
g....
0.751-+---+-t-+----I-+--*~,-j""':.+----1
TA = 25"C--:-
~O
TA = ere
0.50 f-+----I-+-+----I-+--I+-+--i-<-+--l
ID
3~ 0.251-+----1-+-+----1-+-*+-:-++---1
"'
§
10
30
0
> 1.70
0
j$ 1.65
1.60
I....
i
15
25
20
30
/'
1/
V
10
l
Minimum Input Voltage vs
Temperature
I.
IO:1i6 5.0mA-
Vo
7.3
'"
15
'"f-"
~
J..-
~ 5.0Iv_
40
20
25
.............
0.300
::J
-
10.250
o
CJ
6.9
g
6.8
~
6.7
'"
6.6
j$
I
Iis:
,/
V
0
_ _ CL.= O/-tF
!l"
0
........ CL=l.o'~F
w
...... V
400
I
>
!;
l!:
LOAD
If......r .
:>
0
25
50
70
AMBIENT TEMPERATURE-"C
-400
6.4
25
50
70
AMBIENT TEMPERATURE_oC
6 .. 8
av, = 5.0 vVo = 10V
DEVIATION
I
w -40
6.5
0.200
~
'O~~~~T VOL~AGE_
0
/'
35
Rsc = 10 Q
1\
LINE
z
7.0
fo-
30
I
>
E
7.1
!
-
Vo=5.0V
Transient Response
7.2
......
~-
INPUT YOLTAGE-V
OUTPUT CURRENT-rnA
Current Limit Sense Voltage vs
Temperature
.1
Vo = 10 V
1.75
z
LOAD CURRENT-rnA
_......
1.95
1.80
II:
1.50
20
_LI25"~
1.90
1.55
l""- I'---
~~o ~~
Standby Current Drain vs
Input Voltage
E
= 70"c-1-1
~
au 0.350
= 10 Q
:
-400~0-~-~'~0-~--2=0~-~~3~0
125
1.95
g
::~
INPUT VOLTAGE
Current Limiting Characteristics
'i
j$
Rsc
I--+'~-O..-A...-~.t--+-...-..-...+.~O =J'.~.~ ....
2.00
~ OAOO
CL = 0 f.l-F
••••••. CL = 1.0 J.tF
400
TEMPERATURE-OC
Load Regulation
>
Vo •••:=.
-';"~"F;;;;;f~-t'l
_
~
Typical Performance Curves for IlA376
10
~
LINE
I
/
/
1--+--+--II---tIlV, = 5.0V-
:e
0
I
I
Rsc = 10 Q
= 20mA
INL = 1.0mA
Vo = 10V
'FL
l\...... ......... 1.. ......
INPUT. VOLTAGE
I
I
10
20
TIME-p.s
30
MA 105 • MA305
MA305A • MA376
Typical Performance Curves for J.IA376 (Cont.)
Regulator Dropout Voltage
3.0
'2.3 r--r-,r--r--r-r-...,---,--,--r-.
v'o ,; .0J
12.21--+-I-I+--+-1--t- Rsc = 10 Q-
'2.• 1--+-I-I-l--+-1-+-+-+-+-l
IL=20mA
>
~
~
12.01-+-1-+\\-+-1-+-+-+--+-l
11.9I---F=i""'''I-..1O.r-=-+-r-....-II-+--+-+--l
~ l1.81---t.=I:::-:+-+-I-~""'::-+--+-i
i
.....
1··-;;...::····....
11.7
11.6 -
IL"" lOrnA
I .= 5.0 mA
11.5
Supply Voltages Rejection vs
Input/Output Voltage Differential
Optimum Divider Resistance
R.I= J.11 lvoikQJ--
2.8
R2=~
ell
2.7
~
2. 6
z
2.5
is
.........
2.9
I
•.••••••••
".
11.4 1--+-1-+-+-+-+--+-+--+-1
~
'"
g
2.3
'\
•
5
>0.015
~
'0
15
\
"\
r-...
l- t-
iil 0.010
20
25
30
OUTPUT VOLTAGE-V
TEMPERATURE-OC
TA
Ct!Ef : ~2:FHZ_
t
'{.
r---t--
2.0
11.3 L--'--'--'-2-5-'--'----:SO'--'--7=-'=0-.L-....I
~0.025
\
2.2
2.
1°1':1 L
, , ~.'
Vo= 1.72 x (R2+ 1)-
vo' =.~ v '
= 25°C -
f30
:!O,020
m 2.4
a:
'
1
-'-
35
'0
.5
20
25
30
INPUTfOUTPUT VOLTAGE DIFFERENTIAL
PC12040F
Typical Applications
Basic Positive Regulator With Current-Limiting
RSC
R.
V'---"""1>---(:)
R2
lOS <:c
V~Esr;E
mA
6-9
J.lA 117 • J.lA217 • J.lA317
3-Terminal Positive
Adjustable Regulators
FAIRCHILD
A Schlumberger Company
Linear Division Voltage Regulators
Connection Diagram
TO-3 Package
(Top View)
Description
The !iA 117/ !iA217 / !iA317 are adjustable 3-terminal positive
voltage regulators capable of supplying in excess of 1.5 A
over an output voltage range of 1.2 V to 37 V. They are
exceptionally easy to use and require only two external
resistors to set the output voltage. Further, they employ
internal current-limiting, thermal shutdown and safe-area
compensation, making them essentially blowout proof.
(C~~:~2
IN
o
The IJ.A 117 series serves a wide variety of applications including local, on-card regulation. They also make an especially simple adjustable switching regulator, and a
programmable output regulator; or by connecting a fixed
resistor between the adjustment and output, the !iA 117 series can be used as a precision current regulator.
0
10
ADJ
Order Information
Device Code
• Output Current In Excess Of 1.5 A In TO-3 And
TO-220 Packages
• Output Adjustable Between 1.2 V And 37 V
• Internal Thermal Overload Protection
• Internal Short Circuit Current-Limiting Constant
Temperature
• Output Transistor Safe-Area Compensation
• Floating Operation For High Voltage Applications
• Standard 3-Terminal Transistor Packages
• Available In Extended Temperature Range
Package Code
!iA117KM
!iA217KV
!iA317KC
HJ
HJ
HJ
Package Description
Metal
Metal
Metal
Connection Diagram
TO-220 Package
(Top View)
Absolute Maximum Ratings
Storage Temperature Range
TO-3 Metal Can
TO-220 Package
Operating Junction Temperature Range
Extended (!iA117)
Industrial (!iA217)
Commercial (!iA317)
Lead Temperature
TO-3 Metal Can (soldering, 60 s)
TO-220 Package (soldering, 10 s)
Power Dissipation
Input/Output Voltage Differential
-65°C to +175°C
-65°C to + 150°C
Lead 3 connected to case.
-55°C to +150°C
-40°C to + 150°C
O°C to + 150°C
Order Information
Device Code
!iA217UV
!iA317UC
300°C
265°C
Internally Limited
40 V
6-10
Package Code
GH
GH
Package Description
Molded Power Pack
Molded Power Pack
Equivalent Circuit
V,
310 Q
310Q
230Q
120Q
5.6 kQ
6.3 V
125kQ
12AkQ
5.0 pF
135Q
5102
200Q
13 kQ
6.8 kQ
6.3 V
6.3 V
30 pF
105Q
3.6kQ S.8kQ
~
190Q
S.lkQ
110Q
12.5 kQ
4Q
0.1 Q
Vo
ADJUST
J,LA 117 • J,LA217 • J,LA317
Electrical Characteristics TJ = -55°C to + 150°C for the J..I.A 117, -40°C to + 125°C for the J..I.A217, and O°C to
+125°C for the J..LA317; VI-Vo=5.0 V; 10=0.5 A; IMax=1.5 A; PMax=20 W;
unless otherwise specified.
~117/217
Symbol
VR LINE
VR LOAD
Condition 1
Characteristic
Line Regulation 1,5
Load Regulation 1
Min
Typ
Max
TA = 25°C; 3.0 V5.0 V
0.1
0.3
0.1
0.5
%Vo
10 mA< 10< IMax
Vo<5.0 V
20
50
20
70
mV
Vo>5.0 V
0.3
1.0
0.3
1.5
%Vo
50
100
50
100
!.LA
0.2
5.0
0.2
5.0
!.LA
1.25
1.30
1.25
1.30
V
Adjustment Lead
Current
Llladi
Adjustment Lead
Current Change
2.5 V25 V.
6-12
O/OVo
10
mA
A
%Vo
dB
80
0.3
1.0
%/1000
hrs
J,tA117· J,tA217· J,tA317
Typical Performance Curves
Load Regulation
0.4
VI
VO
0.2
Adjustment Lead Current
Current Limit
10
= 15V
= 10V
1 .1.
;I!
~
IL=O.5A
~
IL=I.SA-
() -0.2
r- r-r-..
W
~ -0.4
.........
g
...
~ -0."
/
,
TJ = 25"C
~
.........
1
I
IiW
a:
a:
u
"0
.- ,~:-..
'"
i~
TJ
f- TJ, 15
-0.8
-1.0
-75
o 0
50
25
0
25
50
75
o
100 125 150
10
2.5
!;~
.. z
......
2.0
.. 0
ZW
-to
~
>
i'--.
~
l"1.5
i=
L
i'--.
0
25
~
~~ 1.240
1.0 A
- <'
IL
.::::
=500mA
~
P>-
r---. r-...
i 200 lmA I""-- I'....
50
75
.
W
..
40
~
20
o
0
25
50
75
100
3.0
"...
2.5
W
z
2.0
W
1.5
"
1.0
R
~
80
~
a:
...
60
=
1
I
15
20
25
OUTPUT VOLTAGE-V
r--
T(= 150"C
-
30
35
0.01
,/
If::: r:::::. v
1"-
TJ = 25"C
10
20
30
40
Ripple Rejection vs
Frequency
100
Cadi
.
80
/
III
~
~
Cacti
I
= 10JLF
z
0
i3W
~THbJ~l!,
TJ
.
~
-.....
............
-WiTHOUT~
40
1'\
\
['\,.\
1.0
10
IL
VI
Vo
TJ
= 500 mA
= 15V
= 10V
= 25°C
\"'-
"'-
20
OUTPUT CURRENT-A
6-13
//"
= 10 JLF
0:
=
=
= 25°7111
0.1
60
OJ
a:
40
o
;;: ~
INPUT/OUTPUT
VOLTAGE DIFFERENTIAL-V
VI = 15V
_~O
10V
20
f
120 Hz
IL
500 mA
f == 120 Hz
TJ == 25"C
= -55°C / /
/ ~
~ ".
I\,
o 11
o
125 150
100
u
0:
10
TJ
120
W
..J
VO =5.0V
o
4.0
0.5
iz
WITHOUT Cadj
75 100 125 150
35
a:
a:
u
5
III
"-
50
4.5
W
U
UI
80
OJ
a:
~
~z
I"- ........
Ripple Rejection vs
Output Current
......
25
E
130
60
0
JUNCTION TEMPERATURE_oC
"
1.220
-75 -50 -25
Cadi! 10p..J-
I
z
§
-75 -50 -25
JUNCTION TEMPERATURE_oC
Ripple Rejection vs
Output Voltage
III
/
40
35
40
.
..........
JUNCTION TEMPERATURE-oC
100
45
5.0
1,.230
100 125 150
V
V
V
. Minimum Operating Current
ffi
.........
iomj
IL
1.0
-75 -50 -25
,'.250
.....- V
IL=1.5A
:---- ,""-'L =
t- c:::- ~
... w
0
W
= 100 mV
-......
50
UI
1.260
AVO
~!l;
,- -
30
_f-- l-
55
Z
Temperature Stability
3.0
"a:
OW
20
60
INPUT/OUTPUT
VOLTAGE OIFFERENTIAL-V
Dropout Voltage
.!.
~
W
..J
-......
JUNCTION TEMPERATURE-"C
>
= _55°C
.~
7~
l-
..
...
.....
a.
65
10
'-.
100
1K
10K
100K
FREQUENCY -Hz
1M
10M
J.LA 117 • J.LA217 • J.LA317
Typical Performance Curves (Cont.)
Output Impedance
Load Transient Response
Line Transient Response
10 I
.0
~~~:~g~
f--- IL =
1.5
CL :: 0 p.F; WITHOUT Cadj
500 rnA
r--- TJ = 2S-C
I
0
/
I
V
/
5
0
~
L
I L
I
./
=
Cadi = 10 p~-::
-----100
\
Ct.=
1K
I
I
10K
lOOK
~~
1. 0
!:;~
O. 5
>~
'" '"'"
~(,)
0
10
o
/
-2.0
-3.0
30
40
.5
ft-~
1\
"
II
CL
/
1\1
= 0 ~F; WITHOUT Cadi
V, = 15V
Vo :: 10 V I-'NL = 50mA
TJ = 25"C
1
il
0
I \
I-
I-1\, 'L I--
\
10
30
40
Basic Circuit Operation
The JlA 117 is a 3-terminal floating regulator. In operation,
the JlA 117 develops and maintains a nominal 1.25 V reference (VREF) between its output and adjustment terminals.
This reference voltage is converted to a programming current (Iprog) by R1 (see Figure 1), and this constant current
flows through R2 to ground. The regulated output voltage
is given by:
Typ
OJC
Max
OJC
Typ
OJA
Max
OJA
°C/W
°C/W
°C/W
°C/W
2.3
3.5
35
5.0
40
Vo
=
VREF ( 1 +
:~ ) + ladj
R2
(2)
Since the current from the adjustment terminal (ladj) represents an error term in equation 2, the JlA 117 was deSigned to control ladj to less than 0 V and keep it
constant. To do this, all quiescent operating current is returned to the output terminal. This imposes the requirement for a minimum load current. If the load current is
less than this minimum, the output voltage will rise.
Since the JLA 117 is a floating regulator, it is only the voltage differential across the circuit which is important to performance, and operation at high voltages with respect to
ground is possible.
Co
1.0#
R2
CI is required if regulator is located an appreciable distance from power
supply filter.
Vo = 1.25 V ( 1 +
~~ -1 .0
"c
I
20
Vo
AD.lUST
I
0
n
CL - 1.0 p.F; Cadi - 10 JLF
TIME-J.C.s
Standard Application
~F
~Q
... 1;(
1.0
.5
Typical Applications
0.1
">
~~
..
.0
1M
TO-220 (JlA317)
C,
10~F
Q
Design Considerations
To calculate the maximum junction temperature or heat
sink required, the following thermal resistance values
should be used:
TO-3
c...1 =
1,'- - -
FREQUENCY-Hz
Package
1.0~F;
-1.o - r-- Vo = 10V
IL =50mA
2S C
~> -1.5 - 1-- TJ
/
/
"-
(\
5
WITHOUT Cadi
10· 3
10
w
:~ ) + ladj
R2
(1 )
Since ladj is controlled to less than 100 pA, the error associated with this
term is negligible in most applications.
6-14
J1A 117 • J1A217 • J1A317
Figure
Basic Circuit Configuration
t
VI
Although the J1.A 117 is stable with no output capacitance,
like any feedback circuit, certain values of external capacitance can cause excessive ringing. An output capacitance
(Co) in the form of a 1.0 J1.F tantalum or 25 J1.F aluminum
electrolytic capacitor on the output swamps this effect and
insures stability.
Vo
+
R1
VREF
~
\
IlpROO
________~t
Vo
Protection Diodes
When external capacitors are used with any IC regulator it
is sometimes necessary to add protection diodes to prevent the capacitors from discharging through low current
points into the regulator.
--+ladJ
VRel
= 1.25
R2
V Typical
Figure 2 shows the J1.A 117 with the recommended protection diodes for output voltages in excess of 25 V or high
capacitance values (Co> 25 J1.F, Cadi> 10 J1.F). Diode D1
prevents Co from discharging through the IC during an input short circuit. Diode D2 protects against capacitor Cadi
discharging through the IC during an output short circuit.
The combination of diodes D1 and D2 prevents Cadi from
discharging through the IC during an input short circuit.
Load Regulation
The J1.A 117 is capable of providing extremely good load
regulation, but a few precautions are needed to obtain
maximum performance. For best performance, the programming resistor (R1) should be connected as close to
the regulator as possible to minimize line drops which effectively appear in series with the reference, thereby degrading regulation. The ground end of R2 can be returned
near the load ground to provide remote ground sensing
and improve load regulation.
Figure 2 Voltage Regulator with Protection Diodes
01
1N4002
External Capacitors
A 0.1 J1.F disc or 1.0 J1.F tantalum input bypass capacitor
(CI) is recommended to reduce the sensitivity to input line
impedance.
Vo
R1
D2
1N4002
+
The adjustment terminal may be bypassed to ground to
improve ripple rejection. This capacitor (Cadi) prevents ripple from being amplified as the output voltage is increased. A 10 J1.F capacitor should improve ripple rejection
about 15 dB at 120 Hz in a 10 V application.
ADJUST
R2
6-15
Co
t----------<>------1
Cadj
IlA 138 • IlA238 • IlA338
5-Amp Positive
Adjustable Regulators
FAIRCHILD
A Schlumberger Company
Linear Division Voltage Regulators
Description
Connection Diagram
TO-3 Package
(Top View)
The J,LA 1381 J,LA2381 J.LA338 are adjustable 3-terminal positive
voltage regulators capable of supplying in excess of 5.0 A
over a 1.2 V to 32 V output range. They are exceptionally
easy to use and require only two resistors to set the output voltage.
IN
(C~Q2
A unique feature of the J.LA 138 family is time dependent
current-limiting. The current limit circuity allows peak currents of up to 12 A to be drawn from the regulator for
short periods of time. This allows the J.LA 138 family to be
used with heavy transient loads and speeds start up under
full-load conditions. Under sustained loading conditions, the
current limit decreases to a safe value protecting the regulator. Also included on the chip are thermal overload protection and safe-area protection for the power transistor.
Overload protection remains functional even if the adjustment lead is accidentally disconnected.
o
ADJ
Order Information
Device Code
Package Code
J.LA 138KM
J.LA238KV
J,LA338KC
The J.LA 1381 J.LA2381 J,LA338 are packaged in standard TO-3
transistor packages. The J.LA338 is also available in standard TO-220 transistor packages.
•
•
•
•
•
•
•
•
•
•
•
0
1
FT
FT
FT
Package Description
Metal
Metal
Metal
Connection Diagram
TO-220 Package
(Top View)
Guaranteed 7.0 A Peak Output Current
Guaranteed 5.0 A Output Current
Output Adjustable Between 1.2 V and 32 V
Load Regulation Typically 0.1 %
Line Regulation Typically 0.005%/V
Internal Thermal Overload Protection
Internal Short Circuit Current-Limiting
Output Transistor Safe-Area Compensation
Floating Operation for High Voltage Applications
Standard TO-3 and TO-220 Transistor Packages
Available in Extended Temperature Range
Lead 3 connected to case.
Order Information
Absolute Maximum Ratings
Device Code
Storage Temperature Range
TO-3 Metal Can
TO-220 Package
Operating Junction Temperature Range
Extended (J.LA138)
Industrial (J,LA238)
Commercial (J.LA338)
Lead Temperature
TO-3 Metal Can (soldering, 60 s)
TO-220 Package (soldering, 10 s)
Power Dissipation
Input/Output Voltage Differential
J.LA338UC
-65°C to + 175°C
-65°C to 150°C
-55°C to +150°C
-40°C to + 150°C
O°C to + 150°C
300°C
265°C
Internally Limited
35 V
6-16
Package Code
GH
Package Description
Molded Power Pack
Equivalent Circuit
r---~~------~------~------~--------~--~----------------------------------~------------~----~---~
R26
0.03
L--1---~L-------L---~--L---L---l---l---l---l-__L-------t------J-----J__-------------=======~==~===~
L--------------------------------------------ADJ
~
-..)
~
......
Co)
CO
•
~
N
Co)
CO
•
~
Co)
Co)
CO
•
IlA 138 • IlA238 • IlA338
Electrical Characteristics Unless otherwise specified, these specifications apply: -55°C';;;; TJ';;;; + 150°C for the
~A138, -25°C';;;;TJ';;;;+150°C for ~A238 and 0°C';;;;TJ';;;;+125°C for the M338,
VI- Vo = 5.0 V and 10 = 2.5 A. Although power dissipation is internally limited, these
specifications are applicable for power dissipation up to 50 W, for TO-3; 25 W for
TO-220
J.lA138/J.lA238
Symbol
Characteristic
Conditions
VREF
Reference Voltage 3
3.0 V<'VI-Vo<'35 V,
10 mA<.lo<.5.0 A,
P <.50 W, TA = 25°C
VR LINE
Line Regulation 1
TA = 25°C,
3.0 V<'VI-Vo<.35 V
VR LOAD
Load Regulation 1
J.lA338
Min
Typ
Max
Min
Typ
Max
Units
1.19
1.24
1.29
1.19
1.24
1.29
V
0.005
0.Q1
0.005
0.03
%/V
%IV
0.02
0.04
0.02
0.06
TA = 25°C,
10 mA<.lo<.5.0 A
Vo<.5.0 V
5.0
15
5.0
25
mV
Vo~5.0
0.1
0.3
0.1
0.5
%Vo
10 mA <'10 <.5.0 A
Vo<.5.0 V
20
30
20
50
mV
~5.0
0.3
0.6
0.3
1.0
%Vo
0.002
0.01
0.002
0.02
%/W
3.0 V<'VI-Vo<'35 V
Vo
VRTH
Thermal Regulation
Pulse = 20 ms
VDO
Dropout Voltage4
IL <.5.0 A, VI
TA = 25°C
ladi
Adjustment Lead
Current
dladi
Adjustment Lead
Current Change
Ts
~
7.0 V
V
V
3.0
3.0
V
45
100
45
100
J.lA
10 mA<'IL<'5.0 A
3.0 V<'VI-Vo<'35 V
0.2
5.0
0.2
5.0
!LA
Temperature
Stability
TMin <.TJ <.TMax
1.0
IL Min
Minimum Load
Current
VI-Vo=35 V
3.5
IL
Current Limit
VI-Vo<'10 V
5.0
8.0
5.0
0.5 ms Peak
7.0
12
7.0
VI-Vo=30 V
No
Noise
TA = 25°C
10 Hz<'f<'10 kHz
dVI/dVO
Ripple Rejection
Vo = 10 V,
f = 120 Hz
Long Term Stability2
S
I Without Cadi
I Cadi = 10 J.lF
T A = 25°C for Endpoint
Measurements
5.0
3.5
10
8.0
mA
A
12
1.0
1.0
0.003
0.003
%Vo
60
%Vo
60
60
%
1.0
75
0.3
60
1.0
75
0.3
dB
1.0
%/1000
hrs
Notes
1. Regulation is measured at constant junction temperature. Changes in
output voltage due to heating effects are taken into account sepatately
3. Selected devices with tightened tolerance reference voltage available.
4. Minimum VI- Vo at aoe ~ TJ ~ + 125°C is 3.0 V and at
-55·C ';;;TJ';;; + 150·C is 3.2 V.
by thermal regulation.
2. Since Long Term Stability cannot be measured on each device before
shipment, this specification is an engineering estimate of average
stability from lot to lot.
6-18
JlA 138 • JlA238 • JlA338
Typical Performance Curves
Line Transient Response
Load Transient Response
I
O.6
CL:;:;; D~F, C.dJ
= Op.F
/CL = 1.0 p.F, Cadi
0
= 10 J.l.F
VI
-0.2
""
II
0.0
~
10
VI = 15V
Vo
10V
INI..
100 mA
=
=
TJ
6.0
4.0
~
~
30
20
2.0
0
V
-
-6.0
-'§
o
2.
~ -0.2 ~-+-+--I-+-l---+-+--I--j
~0-0.3 1---+-+--+-+-1---1--+--+--;
i\
\
I
10
-0.4 '----'---'--'--'--'--'---'----'---'
-75 -so -25
25 50 75 100 125 150
30
20
TEMPERATURE-oC
-
~
10'
V,
Vo
IL
T,
3.0
~
r- f-.-
Ii
I-2.0
~
0
1!;
1.0
Output Impedance
!:No= 100mV
1 3.0
~ffi
-
Dropout Voltage
0
r .....
-
~-+-t--+-t--+-+--+-+---
~
~~ -0.1 IL-.f.~f~~*;:::::f::::t:::::3;::.:::r-l
TlME-p,S
Thermal Regulation
0
= 25~C
Ii
I-
TIME-J.LS
0
~ ~1
"1\..
J.
-4.0
I
I
0
2.0
~~
!:iii
".- V l
I
I!: iti- 20 I-- tfiCL= 1.0~F,C." = 10~F_ 8°
.
I
I
VO:;:;; lOY
-0.4 ....-IL = 50 mA
TJ :;:;; 250C
0
.5
">
~I
I
r---r-r---r-r--r-,--r-,-,
0.2
CL=OJ.l.F.Cadj=DJ,tFn
w
.4
2
Load Regulation
4.0
15V
10V
2.0 A
25°C
I-
~ tr- r~~
r- r-
c.., = O"F
1
I"""-
./
1/
1.0
-75
40
-so
-25
0
25
50
75
100
II
10-3
125 150
10
100
TEMPERATURE-"C
Adjustment Current
ffi
:I
55
V
50
II)
:::0
35
-75
V
,/
~
I
/
-so
lOOK
Minimum Operating Current
25
..-
50
75
100
125
150
1.23
-75
/
~
,/
L.o
1 :if
~ \: .... ...
"F
/
I--I--T, =
125"C
TJ :;:;; 2S0C,.-"
•.••
~
~
a:: 1.24
TEMPERATURE-DC
..z. 1#'
~ao
VV
i
I
-25
,/'
126
~> 1.25
/
45
40
....-, /
/
l-
d
c
I
10K
1.27
I
II:
II:
:::0
0
1K
FREQUENCY-Hz
Temperature Stability
60
!Zw
c..,-l0~F
VI = lOY
Vo = 5.0 V
0
"1
'/
IL=5.0A
-25
25
75
TEMPERATURE-OC
6-19
125
1.0
.... T'I- 55
o
o
10
20
30
INPUT/OUTPUT DlFFERENTlAL-V
40
IlA 138 • IlA238 • IlA338
Typical Performance Curves (Cent.)
Current Limit
12
Current Limit
r-IOli
.r'ta. "" 1.0A
~~
10
INL-S.OA
8.0
c
I
= 3.0 A
8.0
III
IEIII
::> 6.0
::> 6.0
'NL
a:
a:
a:
a:
"
I
\
::> 4.0
0
2.0
V, -10V
Vo = S.OV
TJ
=
25°C
1.0
10
o
100
IiIII
iil
a:
..
~
,
§
10
~
15
~
--
c.., "" 1D/J-F
~
VlaVO = 5.0 V
IL=2.0A
f
120 Hz
Tad)
2S"C
0.1
.,...
I
0
z
g
iil
a:
~
W
~
20
~
OUTPUT VOLTAGE-V
20
~
=20V
1
L
II
1.0
1
10
100
TlME-ms
Ripple Rejection
80
80
Cad)
80
Codl
.,...
= 10PP
1
= OPP
....
V
60
I
z
0:::
~
l-
r...
:1
Cadi
i"-
~
1
= 10"F
\..
0
r'\
40
Cad)
a:
40
= O"F,
~
~
20
=
=
M
v,-VO
V,-VQ
o
"
~
~
o
-"
2.0
~
~
Ripple Rejection
40
o
'" ~~iV:
~,-VT r -
f-
"'-
20
4.0
I
TJtI2S"~
........
~
U
6.0
"
!;
100
,
80
"
'"-
III
i::>
,\
~"
8.0
'NL -0 A
INPUT/OUTPUT DtFFERENTlAL-V
Ripple Rejection
80
~
....--INL = 1.0 A
I
o
nME-ms
100
C
INL = ioOA
\
I-
0.1
I
0
"\ ~Yt
,
-
10
~'
~-INL= 3.0,A
I-
o
z
.........
,
= 25°C
~-INL=OA
::>
2.0
.,...
TJ
"..
4.0
12
PEAK CURRENT LIMIT
DC CURRENT LIMIT
~~~
~
j
~
-
~~~
10
c
Current Limit
12
o
V,
Vo
f
TJ
lSV
10V
120 Hz
2S"C
20
\..
v,
Vo
IL
TJ
1.0
0.1
OUTPUT CURRENT-A
6-20
10
'\
lSV
10V
2.0 A
25°C
100
1K
FREQUENCY-Hz
10 K
lOOK
IlA 138 • IlA238 • IlA338
formance, and operation at high voltages with respect to
ground is possible.
Design Considerations
To calculate the maximum junction temperature or heat
sink required, the following thermal resistance values
should be used:
Typ
eJC
°C/W
Package
Max
eJC
°C/W
Typ
eJA
°C/W
Max
eJA
°C/W
TO-3
1.0
35
TO-220
3.5
40
Po Max =
TJ Max- TA
eJC + eCA
Load Regulation
The !LA 138 is capable of providing excellent load regulation, but a few precautions are needed to obtain maximum
performance. For best performance, the programming resistor (R1) should be connected as close to the regulator as •
possible to minimize line drops which effectively appear in
•
series with the reference, thereby degrading regulation.
The ground end of R2 can be returned near the load
ground to provide remote ground sensing and improve
load regulation.
TJ Max TA
or ---:--eJA
Figure 1 Basic Circuit Configuration
eCA = ecs + eSA (Without heat sink)
Solving for TJ:
TJ=TA+PO (eJC+ eCA) or
= TA + POeJA (Without heat sink)
V,
(+R1
Vo
--o;;;;-~VREF
r
L::-__
'-+t"PROG Vo
Where:
TJ
TA
Po
eJA
eJc
eCA
eCS
eSA
= Junction Temperature
= Ambient Temperature
= Power
R2
1
Dissipation
= Junction-to-Ambient Thermal Resistance
= Junction-to-Case
Thermal Resistance
= Case-to-Ambient Thermal Resistance
= Case-to-Heat Sink Thermal Resistance
= Heat Sink-to-Ambient Thermal Resistance
Figure 2 Voltage Regulator with Protection Diodes
Typical Applications
Basic Circuit Operation
The I1A 138 is a 3-terminal floating regulator. In operation,
the !LA 138 develops and maintains a nominal 1.25 V reference (VREF) between its output and adjustment terminals.
This reference voltage is converted to a programming current (lprog) by R1 (see Figure 1), and this constant current
flows through R2 to ground. The regulated output voltage
is given by:
Vo = VREF( 1 +
:~) + ladiR2
+
Co
(1)
External Capacitors
A 0.1 !LF disc or 1.0 !LF tantalum input bypass capacitor
(CI) is recommended to reduce the sensitivity to input line
impedance.
Since the current from the adjustment terminal (Iadj) represents an error term in equation 1, the I1A 138 was designed to minimize ladi and make it constant with line and
load changes. To do this, all quiescent operating current is
returned to the output terminal. This imposes the requirement for a minimum load current. If the load current is
less than this minimum, the output voltage will rise.
The adjustment terminal may be bypassed to ground to
improve ripple rejection. This capacitor (Cadi) prevents ripple from being amplified as the output voltage is increased. A 10 !LF capacitor should improve ripple rejection
by 15 dB at 120 Hz in a 10 V application.
Since the I1A 138 is a floating regulator, it is only the voltage differential across the circuit which is important to per-
6-21
IlA 138 • IlA238 • IlA338
Figure 2 shows the J.LA 138 with the recommended protection diodes for output voltages in excess of 25 V or high
capaCitance values (Co> 25 J.lF, Cadi> 10 J.lF).
Although the J.lA 138 is stable with no output capacitance,
like any feedback circuit, certain values of external capacitance can cause excessive ringing. An output capacitance
(Co) in the form of a 1.0 J.lF tantalum or 25 J.lF aluminum
electrolytic capacitor on the output swamps this effect and
insures stability.
Diode D1 prevents Co from discharging through the IC
during an input short circuit Diode D2 protects against capaCitor Cadi discharging through the IC during an output
short circuit. The combination of diodes D1 and D2 prevents Cadi from discharging through the IC during an input
short circuit.
Protection Diodes
When external capaCitors are used with any IC regulator it
is sometimes necessary to add protection diodes to prevent the capacitors from discharging through low current
points into the regulator.
Figure 3a
Figure 3b
Adjustable Regulator with Improved Ripple
Rejection
High Stability 10 V Regulator
15~ --,.--1
Rl
V,
2.0kQ
5%
01
lN4002
(NOTE 2)
C3
+ Cl
1.0~F
10 ~F
R2
1.5 kQ
1%
LM329B
+
(NOTE 1)
R3
2S7Q
1%
Figure 4 Adjustable Current Regulator
Figure 5 Simple 12 V Battery Charger
Rl
t--'\O."'24"'Q_...._ _ _
~A _ 5.0 A
R Q
...._ _ _ _. , 0.1
v,
(NOTE 4)
Rl
120Q
-=-12 V
R2
2.4 kQ
R3
120 Q
V-5.0 V TO -10 V
Notes
1. Solid tantalum.
2. Discharges Cl if output is shorted to ground.
3. Rl ~ 240 12 for LM138 and LM238.
(R2)
4. As - sets output impedance of charger Zo = Rs 1 + Use of Rs allows low charging rates with fully
Rl
charged battery.
5. The 1000 IlF is recommended to filter out input transients.
6-22
1
-=
J.lA 150 • J.lA250 • J.lA350
3-Amp Positive
Adjustable Regulators
FAIRCHILO
A Schlumberger Company
Linear Division Voltage Regulators
Description
Connection Diagram
TO-3 Package
(Top View)
The !lA 150/ MA250lJ,LA350 are adjustable 3-terminal positive
voltage regulators capable of supplying in excess of 3.0 A
over a 1.2 V to 33 V output range. They are exceptionally
easy to use and require only two external resistors to set
the output voltage.
(C~S~T~2
IN
A unique feature of the MA 150 family is time dependent
current-limiting. The current limit circuitry allows peak currents of up to 6.0 A to be drawn from the regulator for
short periods of time. This allows the !lA 150 family to be
used with heavy transient loads and speeds start up under
full load conditions. Under sustained loading conditions, the
current limit decreases to a safe value protecting the regulator. Also included on the chip are thermal overload protection and safe-area protection for the power transistor.
Overload protection remains functional even if the adjustment lead is accidentally disconnected.
o
ADJ
Order Information
Device Code
FT
FT
FT
Package Description
Metal
Metal
Metal
Connection Diagram
TO-220 Package
(Top View)
Guaranteed 3.0 A Output Current
Output Adjustable Between 1_2 V and 33 V
Load Regulation Typically 0.1 %
Line Regulation Typically 0.005%/V
Internal Thermal Overload Protection
Internal Short Circuit Current-Limiting
Output Transistor Safe-Area Compensation
Floating Operation for High Voltage Applications
Standard TO-3 and TO-220 Transistor Packages
Available in Extended Temperature Range
Lead 3 connected to case
Order Information
Absolute Maximum Ratings
Storage Temperature Range
TO-3 Metal Can
TO-220 Package
Operating Junction Temperature Range
Extended (MA 150)
Industrial (MA250)
Commercial (MA350)
Lead Temperature
TO-3 Metal Can (soldering, 60 s)
TO-220 Package (soldering, 10 s)
Power Dissipation
Input/Output Voltage Differential
Package Code
MA150KM
MA250KV
MA350KC
The MA 150/MA250/ !lA350 are packaged in standard TO-3
transistor packages. The MA350 is also available in standard TO-220 transistor packages.
•
•
•
•
•
•
•
•
•
•
0
10
Device Code
MA350UC
-65°C to + 175°C
-65°C to + 150°C
-55°C to + 150°C
-25°C to + 150°C
O°C to + 150°C
300°C
265°C
Internally Limited
35 V
6-23
Package Code
GH
Package Description
Molded Power Pack
Equivalent Circuit
.---~-----r----~------~----~--~----------~--------------r----------'---r---~
llImiLLf:UJ~~~==----~==-=-=:~
R9
RIO
R12
180
4.1 k
72
RI3
5.lk
RI4
12 k
R26
0.03
<»
'"
.j>.
$.
......
c.n
c
•
$.
N
c.n
C
•
$.
Co)
c.n
c
IlA 150 • IlA250 • IlA350
J..IA150/J..lA250
Electrical Characteristics Unless otherwise specified, these specifications apply -55°e;:;;;;; T J ;:;;;;; + 1500 e for the
J..IA 150, -25°e;:;;;;; TJ ;:;;;;; + 150 0 e for the J..IA250, and ooe;:;;;;; TJ;:;;;;; + 1500 e for the
J..IA350, VI- Va = 5.0 V and 10 = 1.5 A. Although power dissipation is internally
limited, these specifications are applicable for power dissipation up to 30 W, for
TO-3; 25 W for TO-220.
Symbol
Characteristic
Min
Conditions
Max
Units
1.30
V
TA = 25°C
3.0 V
u
~
---
-1.0
-7S
0
-2S
2S
75
TEMPERATURE-OC
6-27
12S
10
20
TlME-p.s
30
40
IlA 150 • IlA250 • IlA350
Typical Performance Curves (Cont.)
Adjustment Current
Dropout Voltage
Temperature Stability
65
1.26
60
C
.--
E
~w
II:
II:
"u....
z
55
50
w
45
d
40
i!
gs
'"
",
!
.......
1.25
"~
> 1.24
/'
V
/
V
V
V
V
I
a:
"
1.23
1.0
r.-+-+-+---+-t--r-I---t--l
35
1.22
30
-75
-25
75
25
-75
125
-25
25
75
125
-75
-25
25
75
TEMPERATURE-OC
TEMPERATURE-"C
TEMPERATURE-OC
Ripple Rejection
100
80
...
-
.I J
~C.dJ=10p.F
CD
J
~
'-....
80
u
w
Cadj
iil
II:
.
w
-
= OJ.lF
40
it
iE
Vl~VO
f
o
= 5.0 V
= 500 mA
= 120 Ml
20 r--1L
!'J=2r
o
~
10
15
~
~
M
~
OUTPUT VOLTAGE-V
Design Considerations
Solving for TJ:
TJ = TA + po(eJC + eCA) or
= T A + poeJA (Without heat sink)
To calculate the maximum junction temperature or heat
sink required, the following thermal resistance values
should be used:
Package
Typ
Max
eJC
°C/W
eJC
°C/W
TO-3
TO-220
Po Max =
3.0
TJ Max- TA
eJC
eCA = ecs
+ eCA
or
Typ
eJA
Max
eJA
°C/W
°C/W
Where:
TJ
TA
Po
= Junction Temperature
= Ambient Temperature
= Power Dissipation
1.5
35
eJC
e JA
= Junction-to-Ambient
4.0
40
eCA
eCS
eSA
=
=
=
=
TJ Max TA
-=-=~--'-'
eJA
+ eSA (Without heat sink)
6-28
Thermal Resistance
Junction-to-Case Thermal Resistance
Case-to-Ambient Thermal Resistance
Case-to-Heat Sink Thermal Resistance
Heat Sink-to-Ambient Thermal Resistance
125
p-A 150 • p-A250 • p-A350
Typical Applications
In operation, the !lA150 develops a nominal 1.25 V reference voltage, VREF, between the output and adjustment
terminal. The reference voltage is impressed across program resistor R1 and, since the voltage is constant, a
constant current 11 then flows through the output set resistor R2, giving an output voltage of (Figure 1)
Vo
= VREF
(
1+
:~) + ladjR2
Figure 1 Basic Circuit Configuration
V,
r
(1)
Vo= V.Edl + ~) I.dl R2
Since the 50 !lA current from the adjustment terminal represents an error term, the /JA 150 was designed to minimize ladj and make it very constant with line and load
changes. To do this, all quiescent operating current is returned to the output establishing a minimum load current
requirement. If there is insufficient load on the output, the
output will rise.
r
Although the /JA 150 is stable with no output capacitors,
like any feedback circuit, certain values of external capacitance can cause excessive ringing. This occurs with values
between 500 pF and 5000 pF. A 1.0 /JF solid tantalum (or
25 /JF aluminum electrolytic) on the output swamps this
effect and insures stability.
External Capacitors
An input bypass capacitor is recommended. A 0.1 /JF disc
or 1.0 /JF solid tantalum on the input is suitable input bypassing for almost all applications. The device is more
sensitive to the absence of input bypassing when adjustment or output capacitors are used, but the above values
will eliminate the possibility of problems.
Load Regulation
The /JA 150 is capable of providing extremely good load
regulation but a few precautions are needed to obtain
maximum performance. The current set resistor connected
between the adjustment terminal and the output terminal
should be tied directly to the output of
(usually 240
the regulator rather than near the load. This eliminates
line' drops from appearing effectively in series with the reference and degrading regulation. For example, a 15 V regulator with 0.05
resistance between the regulator and
load will have a load regulation due to line resistance of
0.05 n x 1L. If the set resistor is connected near the load
the effective line resistance will be 0.05
(1 + R2/R1) or
in this case, 11.5 times worse.
n)
The adjustment terminal can be bypassed to ground on
the !lA150 to improve ripple rejection. This bypass capacitor prevents ripple from being amplified as the output voltage is increased. With a 10 /JF bypass capacitor 88 dB
ripple rejection is obtainable at any output level. Increases
over 10 /JF do not appreciably improve the ripple rejection
at frequencies above 120 Hz. If the bypass capacitor is
used, it is sometimes necessary to include protection diodes to prevent the capacitor from discharging through internal low current paths and damaging the device.
n
n
Figure 2 shows the effect of resistance between the reguset resistor.
lator and 240
n
In general, the best type of capacitor to use is solid tantalum. Solid tantalum capacitors have low impedance even
at high frequencies. Depending upon capacitor construction, it takes about 25 /JF in aluminum electrolytic to equal
1.0 /Jf: solid tantalum at high frequencies. Ceramic capacitors are also good at high frequencies, but some types
have a large decrease in capacitance at frequencies
around 0.5 MHz. For this reason, 0.01 /JF disc may seem
to work better than a 0.1 /JF disc as a bypass.
With the TO-3 package, it is easy to minimize the resistance from the case to the set resistor, by using two separate leads to the case. The ground of R2 can be
returned near the ground of the load to provide remote
ground sensing and improve load regulation.
6-29
IlA 150 • IlA250 • IlA350
Figure 2
Protection Diodes
When external capacitors are used with any IC regulator it
is sometimes necessary to add protection diodes to prevent the capacitors from discharging through low current
points into the regulator. Most 10 fJ.F capacitors have low
enough internal series resistance to deliver 20 A spikes
when shorted. Although the surge is short, there is
enough energy to damage parts of the IC.
Voltage Regulator with Line Resistance in
Output Lead
V,
R2
When an output capacitor is connected to a regulator and
the input is shorted, the output capacitor will discharge
into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage of
the regulator, and the rate of decrease of VI. In the
fJ.A 150, this discharge path is through a large junction that
is able to sustain 25 A surge with no problem. This is not
true of other types of positive regulators. For output capacitors of 25 fJ.F or less, there is no need to use diodes.
Figure 3
Voltage Regulator with Protection Diodes
01
lN4002
The bypass capacitor on the adjustment terminal can discharge through a low current junction. Discharge occurs
when either the input or output is shorted. Internal to the
JJ.A 150 is a 50 n resistor which limits the peak discharge
current. No protection is needed for output voltages of
25 V or less and 10 fJ.F capacitance. Figure 3 shows a
JJ.A 150 with protection diodes included for use with outputs
greater than 25 V and high values of output capacitance.
I-_......-+-_-Vo
V,
Cl
Vo = 1.25 V ( 1 +
R2
iii) I.dj R2
01 PROTECTS AGAINST Cl
02 PROTECTS AGAINST C2
Typical Applications
Temperature Controller
Light Controller
~~------------'--Vo
Rl
1.2 kQ
HEATER
R2
80Q
6-30
JJ.A 150 • JJ.A250 • JJ.A350
Typical Applications (Cant.)
Precision Power Regulator with Low Temperature
Coefficient
Slow Turn-On 15 V Regulator
V,
V,
Adjustable Regulator with
Improved Ripple Rejection
High Stability 10 V Regulator
15~-.....- - i
V, -
R1
2.0kQ
5.0%
.....- - i
R1
240Q
01
1N4003
+
R2
1.5 kQ
1.0%
(NOTE 3)
C3
1.0"F
(NOTE 2)
R3
2.67 Q
1.0%
Notes
1. Adjust for 3.75 V across RI
2. Solid Tantalum
3. Discharge CI if output is shorted to ground
6-31
JlA 150 • JlA250 • JlA350
Typical Applications (Cont.)
5 V Logic Regulator with
Electronic Shutdown (Note 2)
Digitally Selected Outputs
v,
t----~Vo
V, 7.0 V - 35 V
C2
0.1
~F
1.0 kl>
r-+--'VItv- TTL
o to 30 V Regulator
AC Voltage Regulator
V, _ _ _- - I
I - -.......- - V o
35V
1201>
v.....
r\.
R2
6 V.....
3A
rv
12
2.0kl>
'V
4002
1.2V
120\1
R3
6802
-10V
Notes
1. Sets maximum Vo
2. Min output '" 1.2 V
6-32
4882
IlA 150 • IlA250 • IlA350
Typical Applications (Cont.)
5.0 A Constant Voltage/Constant Current Regulator
R3
R2
250kQ
36V
0.2
5W
Rl
33
t-1----------t-----------r------1--+~r__~~~-30V
+
C3
10~F
I
"::" (NOTE 1)
R6
240Q
R5
330kQ
-6.0 V TO -15 V
R7
220
RB
B.OkQ
VOLTAGE
ADJUST ";"
12 V Battery Charger
T012V
BATTERY
Noles
1. Solid tantalum
2. Lights in constant current mode
6-33
IlA 150 • IlA250 • IlA350
Typical Applications (Cont.)
Adjustable Current Regulator
1.2 V - 20 V Regulator with
Minimum Program Current
3.0 A Current Regulator
Rl
1-...0.,,3,..2_---
~TO 3.0 A
1--,....-~1)
v,----I
v,
R2
20kQ
R3
120Q
CR03440F
v-5.0 V TO -18 V
Precision Current Limiter
Tracking Pre-Regulator
,-+ ~ ~~"-M-'
Vo
II,
R3
120Q
R4
1.0 kQ
CR03460F
Noles
1. Minimum load current 4.0 mA
2. 0.4';;Rl';;120 n
6-34
OUT
ADJUST
p.A 150 • p.A250 • p.A350
Typical Applications (Cont.)
Adjusting Multiple On-Card Regulators with Single Control (Note 1)
Simple 12 V Battery Charger
RS
Vo
0.211
Vo
110
(NOTE 3)
(NOTE 2)
(NOTE 2)
IN4802
+
R2
2Akll
Adjustable 10 A Regulator
Current Limited 6.0 V Charger
V,
,
CR03501F
110
9.OV",aov
+
1000"F
1.1 kll
(NOTE 4)
10011
4.5VTO 25 V
1.011
(NOTES)
5.0kll
5.0kll
Notes
1. All outputs within ± 100 mV
2. Minimum load -10 mA
(
A2 )
3. As - sels output impedance of charger Zo = As 1 +Use of As allows low charging rates with fully
AI
charged battery.
4. 1000 IJ.F is recommended to filter out any input transients.
5. Sets peak current (2 A to 0.3 f!)
6-35
p.A 1524A • p.A2524A • p.A3524A
Advanced
Pulse Width Modulators
FAIRCHILD
A Schlumberger Company
Linear Division Voltage Regulators
Description
Connection Diagram
16-Lead DIP
(Top View)
The p.A 1524A family of regulating PWM ICs have been designed to retain the same highly versatile architecture of
the industry standard UC1524 (SG1524) while offering substantial improvements to many of its limitations. The
p.A1524A family is lead compatible with "non-A" models
and in most existing applications can be directly interchanged with no effect on power supply performance. Using the p.A1524A family, however, frees the designer from
many concerns which typically had required additional circuitry to solve.
16
ERROR AMP -IN
+SVVREF
ERROR AMP +IN
+VIN
OSC/SVNC
The p.A1524A family includes a precise 5.0 V reference
trimmed to ± 1% accuracy, eliminating the need for potentiometer adjustments; an error amplifier with an input range
which includes 5.0 V, eliminating the need for a reference
divider; a current sense amplifier useful in either the
ground or power supply output lines; and a pair of 60 V,
200 mA uncommitted transistor switches which greatly enhance output versatility.
CUR LIM AMP +IN
COLLECTOR B
CUR LIM AMP -IN
COLLECTOR A
R,.
EMITTER A
Cor
SHUTDOWN
GND
An additional feature of the p.A 1524A family is an undervoltage lockout circuit which disables all the internal circuitry except the reference, until the input voltage has
risen to the turn-on threshold. This holds standby current
low until turn-on, greatly simplifying the design of low power, off-line supplies. The turn-on circuit has approximately
300 mV of hysteresis for jitter-free activation.
EMlTTERB
COMPENSATION
c001390F
Order Information
Device Code
p.A1524ADM
p.A2524ADV
p.A2524APV
p.A3524APC
p.A3524ADC
Other product enhancements within the p.A1524A family
design include a PWM latch which insures freedom from
multiple pulsing within a period, even in noisy environments; logic to eliminate double pulsing on a single output;
and a 300 ns external shutdown capability. The oscillator
circuit of the p.A 1524A family is usable beyond 500 kHz
and is now easier to synchronize with an external clock
pulse.
•
•
•
•
•
•
•
•
The p.A 1524A is packaged, in a hermetic 16-lead DIP and
rated for operation from -55·C to + 125·C. The p.A2524A
and p.A3524A are available in either ceramic or plastic
packages and are rated for operation from -25·C to
+ 85·C and O·C to 70·C respectively.
•
•
•
•
•
6-36
Package Code
78
78
98
98
78
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
Molded DIP
Ceramic DIP
Fully Interchangeable With Standard 1524 Families
PreCision Reference Internally Trimmed To ± 1%
High Performance Current Limit Function
Under Voltage Lockout With Hysteristic Turn-On
Start-Up Supply Current Less Than 4.0 mA
Output Current To 200 mA
60 V Output Capability
Wide Common Mode Input Range For Both Error
And Current Limit Amplifiers
PWM Latch Ensures Single Pulse Per Period
Double Pulse Suppression Logic
300 ns Shutdown Through PWM Latch
Guaranteed Frequency Accuracy
Available In Extended Temperature Range
p.A 1524A • p.A2524A • p.A3524A
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Extended (IIA1524A)
Industrial (1IA2524A)
Commercial (1IA3524A)
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1,2
16L-Ceramic DIP
16L-Molded DIP
Supply Voltage
Collector Supply Voltage
Output Current (Each Output)
Reference Output Current
Oscillator Charging Current
-65·C to +175·C
-65·C to + 150·C
-55·C to +125·C
-25·C to +85·C
O·C to +70·C
300·C
265·C
Notes
1. TJ Max - IS0·C for the Molded DIP, and 17S·C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 2S·C. Above this temperature,
derate the 16L-Ceramic DIP at 10 mwrc, and the 16L-Molded DIP at
8.3 mwrc.
Equivalent Circuit
1--------- YRE.
VIN-------~----------~
osc------,
POWER TO
INTERNAL
CIRCUITRY
COMP------~
-IN
1.0K2
+IN
~~~~~-----------------~~WN
10K2
f""
-IN
Power Dissipation at TA = +2S·C ........................................... 1000 mW
Derate above + SO·C ....................................................... 10 mW
Power Dissipation at Tc = + 2S·C ........................................... 2000 mW
Derate for Case Temperature above + 2S·C .......................... 16 mW
rc
rc
6-37
GNO
1.50 W
1.04 W
40 V
60 V
200 rnA
50 rnA
5.0 rnA
IJA 1524A • 1lA2524A • 1lA3524A
1lA1524, 1lA2524A, 1lA3524A
Electrical Characteristics T A = -55°C to
O°C to
+ 125°C
+ 70°C
for the iJA.1524A, -25°C to + 85°C for the iJA.2524A, and
for the iJA.3524A, VI = Vc = 20 V, unless otherwise specified.
j.lA3524A
j.lA 1524A/j.lA2524A
Symbol
Characteristic
Conditions
I
I
Max
Min
40
8.0
7.5
8.5
5.5
V
2.5
V to 40 V
6.0
Min
Typ
I Typ
I
Max
Unit
Turn-on Characteristics
Vo
Input Voltage
Operating Range after
Turn-on
Turn-on Threshold
8.0
5.5
Turn-on Current
VI
Operating Current
VI
= 6.0
= 8.0
Turn-on Hysteresis1
40
V
7.5
8.5
V
4.0
2.5
4.0
mA
10
6.0
10
mA
0.3
0.3
V
Reference Section
= 25°C
= 10 V to
IL = 0 mA to
Vo
Output Voltage
TJ
VR LINE
Line Regulation
VI
4.90
V
5.0
5.05
5.0
5.10
10
20
10
30
mV
5.0
50
5.0
50
mV
Temperature
Stability1
Over Operating Range
20
50
20
50
mV
los
Output Short Circuit
Current
VREF = 0 V, TJ
= 25°C
80
100
80
100
mA
No
Noise 1
10 Hz';;;f';;;10 kHz,
TJ = 25°C
VR LOAD
Load Regulation
4.95
40 V
Long Term Stability1
Oscillator Section RT = 2700 n,
Initial Accuracy
TJ
= 125°C,
Cr = 0.01 mF,
TJ = 25°C
20 mA
40
1000 Hrs
20
50
43
45
/lVrms
20
50
mV
43
47
kHz
unless otherwise specified
41
Temperature
Stability1
Over Operating
Temperature Range
Minimum Frequency
TJ = 25°C, RT
CT = 0.1 mF
= 150
kn,
Maximum Frequency
TJ = 25°C, RT
CT = 470 pF
= 2.0
kn.
Output Amplitude 1
TJ
Output Pulse Width 1
TJ
= 25°C
= 25°C
TJ
= 25°C
39
2.0
Ramp Peak
Ramp Valley
40
2.0
140
500
%
120
500
Hz
kHz
3.5
3.5
V
0.5
0.5
/lS
3.3
3.5
3.7
3.3
3.5
3.7
V
0.6
0.75
0.9
0.6
0.75
0.9
V
Error Amplifier Section VCM = 2.5 V. unless otherwise specified.
VIO(EA)
Input Offset Voltage
0.5
5.0
2.0
10
mV
liB
Input Bias Current
1.0
5.0
1.0
10
110
Input Offset Current
.05
1.0
0.5
1.0
/.LA
/.LA
6-38
MA 1524A • MA2524A • MA3524A
JlA1524, JlA2524A, JlA3524A (Cont.)
Electrical Characteristics TA = -55°C to + 125°C for the JlA 1524A, -25°C to + 85°C for the JlA2524A, and
O°C to +70°C for the JlA3524A, VI
= Vc = 20
V, unless otherwise specified.
IlA 1524A1IlA2524A
Symbol
Characteristic
Conditions
Min
Typ
Max
!lA3524A
Min
Typ
Max
Unit
CMR
Common Mode
Rejection
VCM=1.S V to S.S V
60
7S
60
7S
dB
PSRR
Power Supply
Rejection Ratio
VI = 10 V to 40 V
SO
60
SO
60
dB
Output Swing
Minimum Total Range
O.S
Open Loop Voltage
Gain
!lVo = 1.0 V to 4.0 V,
RL ;;'10 MQ
72
80
60
80
dB
Gain Bandwidth 1
TJ=2Soc, Av=O dB
1.0
3.0
1.0
3.0
MHz
DC
Transconductance 1, 2
TJ = 2SoC,
30 kQ < RL < 1.0 MQ
1.6
mho
S.O
O.S
1.6
S.O
V
Current Limit Amplifier Lead S = 0 V, unless otherwise specified.
VIO
Input Offset Voltage
TJ = 2SoC, E/A Set for
maximum output
190
VIO
Input Offset Voltage
Over Operating
Temperature Range
180
lis
Input Bias Current
CMR
Common Mode
Rejection
VLead 5 = -0.2 V
to +S.S V
SO
60
SO
60
dB
PSRR
Power Supply
Rejection Ratio
VI = 10 V to 40 V
SO
60
SO
60
dB
Output Swing
Minimum Total Range
O.S
Open Loop Voltage
Gain
Vo= 1.0 V to 4.0 V,
RL ;;'10 MQ
70
Delay Time 1
Lead 4 to Lead 9,
!l VI = 300 mV
200
-1.0
210
180
220
170
-10
S.O
80
200
-1.0
O.S
70
300
220
mV
230
mV
-10
!lA
S.O
V
80
dB
300
ns
80
V
Output Section (Each Output)
!lA
VCE
Collector Emitter
Voltage
Ic = 100
60
80
SO
ICE
Collector Leakage
Current
VCE = SO V
0.1
20
0.1
20
!lA
VCE Sat
Saturation Voltage
Ic= 20 mA
0.2
0.4
0.2
0.4
V
Ic=100 mA
1.0
1.S
1.0
1.S
Ic= 200 mA
2.0
2.7
2.0
2.S
VE
Emitter Output
Voltage
IE = SO mA
t,
Rise Time 1
TJ = 2SoC, R = 2.0 kQ
tf
Fall Time 1
TJ = 2SoC, R = 2.0 kQ
17
6-39
18
17
18
V
1S0
1S0
ns
SO
SO
ns
JJ.A 1524A • JJ.A2524A • JJ.A3524A
J.LA 1524, J.LA2524A, IlA3524A (Cont.)
Electrical Characteristics TA = -55°C to + 125°C for the p.A 1524A, -25°C to + 85°C for the IlA2524A, and
O°C to + 70°C for the IlA3524A, VI = Vc = 20 V, unless otherwise specified.
~A3524A
MA1524A/~A2524A
Symbol
Characteristic
Conditions
Min
Typ
Max
Min
Max
Unit
TJ = 25°C,
Lead 9 to Output
350
350
ns
Shutdown Delay1
TJ = 25°C,
Lead 10 to Output
300
300
ns
Shutdown Threshold
TJ = 25°C, Rc = 2.0 k.l1
0.6
0.7
1.0
0.6
Notes
1" These parameters are guaranteed by design but not 100% tested in
production.
2. DC transconductance (gM) relates to DC open loop voltage gain
according to the following equation: Av = 9M RL where RL is the
resistance from lead 9 to ground. The minimum 9M specification is used
to calculate minimum Av when the error amplifier output is loaded.
Open Loop Test Circuit (Note 1, 2)
+Vc
2.0 kQ
lW
COLLECTOR A
f - f - -......-
COLLECTOR B
f-......- - - B O
,u.A1524A
SYNC
EMITTER A
ERROR AMP
CURRENT LIMIT
EMITTER B
2.0 kQ
RT
0.1
Typ
Comparator Delay 1
10kQ
0.1
CT
EIACONTROl
10kQ
2.0 kQ
'----t--... ~1.0 kQ
Cl CONTROL
Notes
1. The !lA1524A should be able to be tested in any 1524 test circuit with
two possible exceptions.
a. The higher gain bandwidth of the current limit amplifier in the
pA 1524A may cause oscillations in an uncompensated 1524 test
circuit.
b. The effect of the shutdown, lead 10, cannot be seen at the
compensation terminal, lead 9; but must be observed at the outputs.
2. The circuit will allow all pA 1524A functions to be evaluated.
6-40
Ao
0.7
1.0
V
J1A 1524A • J1A2524A • J1A3524A
Typical Performance Curves
Supply Current vs
Voltage
Error Amplifier Voltage Gain vs
Frequency
10
1
.
E
~
a:
a:
--
I
T~ -
III
55·1:_
2S·C
TJ
1,
!zw
14
"
:;
Ul
W
o
/
o I
o
Y
10
0
TJ ,'2S·C
1
60
40
0-
0
0
-i
I
z
W
0-
0
CIO
1
40
30
20
20
RL
1.0M2
RL
300 kQ
RL
100 kQ
RL
30 kQ
= 20 V
= 2S·C r-
V,
TJ
1"\
1'-
>
1
NOTE: OUTPUTS OFF, RT =
~
w
"~
?
a
a
"
_
80
"I
z
Pulse Width Modulator
Transfer Function
1'1'-
J I
SUPPLY VOLTAGE-V
f
~~--~~-t--~~--+-~
30
I-----t----t.
!2.
w
"
LEAD 9 TO GROUND. VALUES
~
f-BELOW 30 kQ WILL BEGIN TO ~
LIMIT THE MAXIMUM DUTY CYCLE.
100
I
!Ii!
r- R~ IS I~PEbANCE FROM
50
.
1K
10 K
100 K
K:
20 f---+--+--:~+--~f---j
1,0
f---t-J'-7"',
1M
PWM INPUT VOLTAGE (LEAD 9)-V
FREQUENCY-Hz
Oscillator Frequency vs
Timing Components
Output Dead Times vs
Timing Capacitor Value
Output Saturation Voltage
10
V,
TJ
.......
20V
2S·C
5.0
c''> I, 1
c~'"
0
~
I
''>
''>
o 101),
''>
C~
''>
~~
.......
w
::E
>=
.
0
w
0
t-
::>
...::>
0-
'00",
10
1
20
>
...::>I
...::>
0.5
INPUT AHEAD 4
>
...::>I
0-
~
20
50
100
Shutdown Delay From PWM
Comparator - Lead 9
,. ,.,Ir"
:1/.1",
I. 1 .!..I
10
I
TIMING CAPACITOR-nF
>
15
...::>
10
J
TlErhb
0.2
VIN == 20 V, TJ == 25°C
0.1
LEAD 2
TO LEAD 16
LEAD 5 GROUNDED
J, = ~o vi
RL
TJ
::>
0-
OUTPUT COLLECTOR CURRENT-mA
Turn-Off Delay From
Shutdown - Lead 10
1
20
I
t-
0
I',
0
=
OSC OUTPUT
NOTE: DEAD TIME
PULSE WIDTH PLUS
1 ,OUTPUT DELAY
1
100
~48~ ~ '/. '/
/50%
0-
~
0.1
50
OUTPIUT ~T LEAD 9
VERDRIVE:
5%
~
a:
..... 1-'
0.2 -
Current Limit Amplifier Delay
'"'I'
"i!
Q
1.0
TIMING RESlSTOR-kQ
-
>
I
w
2.0
0
1 1
100
V,-20V
RT = 2700
TJ == 25"C
= 2.0 kQ= 2S·C _
-I 1 1
OUTPUT AT
LEAD 12 OR 131
>
...::>I
...::>
0-
VI
...I
::>
4
3
2
INPUT AT
LEAD ,9
...::>
I
0-
0-
~
>
f- NOTE: MINIMUM INPUT PULSE WIDTH TO LATCH IS 200 ns
~
OUTPUT AT
LEAD 12 OR 13
t-t-i
J
DELAY TIME-~s
6-41
1
1
1
I I I
INPUT AT 1
LEAD 10 1
1
1
1
1
_ NOTE: MINIMUM INPUT PULSE WIDTH _
T~ LATCH IS 200 ns
1
DELAY TlME-,u.s
1
20V
TJ == 25°C
r-- I--H
0,5
1
=
RL == 2.0 kQ
10
0
1.0
>
1
20
15
DELAYTIME-""
tlA431A
Adjustable Precision Zener
Shunt Regulator
FAIRCHILD
A Schlumberger Company
Linear Division Voltage Regulators
Connection Diagram
TO-92 Package
(Top View)
Description
The J.IA431 A is a 3-terminal adjustable shunt regulator with
guaranteed temperature stability over the entire temperature range of operation. The output voltage may be set at
any level greater than 2.5 V (VREF) up to 36 V merely by
selecting two external resistors that act as a voltage divided network. Due to the sharp turn-on characteristics this
device is an excellent replacement for many zener diode
applications.
• Average Temperature Coefficient 50 ppmrC
• Temperature Compensated For Operation Over The
Full Temperature Range
• Programmable Output Voltage
• Fast Turn-On Response
• Low Output Noise
ANODE
Order Information
Device Code
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Industrial (J.IA431AV)
Commercial (J.IA431AC)
Lead Temperature
TO-92 Package/SO-8
(soldering, 1Q s)
Internal Power Dissipation 1,2
TO-92 Package
SO-8 Package
Cathode Voltage
Continuous Cathode Current
Reference Voltage
Reference Input Current
Operating Conditions
Cathode Voltage
Cathode Current
Package Code
J.IA431AWC
p.A431AWV
EI
EI
Package Description
Molded
Molded
-65°C to + 15QoC
Connection Diagram
SO-8 Package
(Top View)
-40°C to +85°C
QOC to +70°C
265°C
0.78 W
0.81 W
37 V
-10 mA to
+150 mA
-0.5 V
10 mA
Min
Max
37 V
VREF
1.0 mA 100 mA
Order Information
Notes
1. TJMax=150°C.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the TO·92 at 6.2 mW rc, and the 50-8 at 6.5 mW rc.
Device Code
J.IA431ASC
6-42
Package Code
KC
Package Description
Molded Surface Mount
J.lA431 A
Equivalent Circuit
r-________________________________~--~~--~--_4~-~~~HODE
•
R3
2.SkO
RS
Rl
3.30
6400
~
____________~~----------~~------------~--~~-~~~E
DC Test Circuits
Figure 1 Test Circuit For Vz = VREF
Figure 2 Test Circuit For Vz
IN -"'VIIv--t-- Vz
Rl
""'"' liz
--t
R2
Figure 3 Test Circuit For Off-State Current
Note
Vz
= VREF
(1 + Rl/R2) + IREF· Rl
6-43
> VREF
J1A431A
J.lA431 A
Electrical Characteristics TA = 25°C unless otherwise specified.
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
2.440
2.495
2.550
V
8.0
17
Vz from VREF to 10 V
-1.4
-2.7
Vz from 10 V to 36 V
-1.0
-2.0
2.0
4.0
/JA
Rl = 10 kil, R2 = 00,
11=10 mA,
TA = Full Range, Fig. 2
0.4
1.2
iJ.A
Minimum Cathode Current
for Regulation
Vz = VREF, Fig. 1
0.4
1.0
mA
IZ(OFF)
Off-State Current
Vz = 36 V, VREF = 0 V, Fig. 3
0.3
1.0
iJ.A
rz
Dynamic Output
Impedance 2
Vz = VREF,
Frequency = 0 Hz, Fig. 1
.75
il
VREF
Reference Voltage
Vz = VREF, II = 10 mA, Fig. 1
VDEV
Deviation of Reference
Input Voltage Over
Temperature 1
Vz = VREF, II = 10 mA,
TA = full range, Fig. 1
dVREF
Ratio of the Change in
Reference Voltage to the
Change in Cathode
Voltage
Iz = 10 mA,
Fig. 2
IREF
Reference Input Current
Rl = 10 kil, R2 =
II = 10 mA, Fig. 2
oc IREF
Deviation of Reference
Input Current over
Temperature
IZ(MIN)
dVz
00,
Notes
mV
mVIV
ex: VREF can be positive or negative depending on whether the slope is
positive or negative.
1. Deviation of reference input voltage, VDEV. is defined as the maximum
variation of the reference input voltage over the full temperature range.
Example: VOEV
= 8.0
mY. VREF
8.0 mV ]10
[
= 2495
mY, T2 - T,
= 70"C,
slope is positive
6
2495 mV
ox VREF =
'7O'C
=
+ 46 ppml"C
2. The dynamic output impedance, rz, is defined as:
AVz
rz=Alz
T.
When the device is programmed with two external resistors, R1 and R2,
(see Figure 2), the dynamic output impedance of the overall circuit, rz,
is defined as:
TEMPERATURE
The average temperature coefficient of the reference input voltage,
is defined as:
VOEV
]10
[
± VREF (at 25"C)
0:
VREF,
rz = AV z '" [rz 1 +
Alz
6
T2 T,
Where:
T2 - T, = full temperature change.
6-44
~
]
R2
MA431A
Typical Performance Curves
Input Current vs Vz
Thermal Information
Input Current vs Vz
1000
TA "" 25°C
Vz =
I
VREF
500
/
/
IzMlN
I
I
100
o
V
o
/
i'..
500
1 100 1----+--+-+--+--11---;
~
~
i
"""
I
5O~--t---~---t--~----t-~
;
100
1.0
70
25
3.0
2.0
CATHODE YOLTAGE-V
85
125
CATHODE VOLTAGE-V
TEMPERATURE-OC
PC01361F
Dynamic Impedance vs
Frequency
15
TA = ZSOC
liz = """"
'~"
U
10
~
l
~
z
~
5.0
/
I
I
J
~
l.okll
SOil
tlz=10mA
./
o
1.OK
10K
1.0M
lOOK
10 M
FREQUENCY-Hz
Stability Boundary Conditions
100
90
~
I
80
70
!i
w
60
:>
so
II:
II:
u
w
Q
0
~
u
A
B
C
D
VKA = 5VATIK =:I 10mA
VItA = 10 V AT IK = 10 rnA
VKA = 15 V ATI. = 10 mA
1
(NOTE 1)
A
20
10 pF
STABLE
1\
,I 1/
STABLE
30
o
B
C
40
10
Note
1. The areas under the curves represent ccnditions that may cause the
device to oscillate. For curves B, C, and D, R2 and V+ were adjusted
to establish the initial VKA and I. ccndltlons with CL = O. V+ and CL
were then adjusted to determine the ranges of stability.
1
VKA· VREF
Ih I
TA - 25°C
100 pF
~
r; / / r-2.....: \\
1
1000 pF
0.01 "F
0.1 "F
1 "F
10 "F
LOAD CAPACITANCE
6-45
IlA431A
Typical Characteristics
Test Circuit for Curves B, C, And D Below
Test Circuit For Curve A Below
Rl
+I. 150
=
10kQ
+
+
Cl
Cl
Q
v+
VREF
R2
Typical Applications
Single Supply Comparator With
Temperature Compensated
Threshold
Shunt Regulator
v+
v+--~~-,--------~------~----Vo
Rl
VREF +----+-=i~
R2
I
I
+----OUT
1
T
I
IN -"""'----i-'iil~
I
I
lint
~
2.5 V --~-----<~-----GND
Output Control of a Three
Terminal Fixed Regulator
Series Regulator
v+--~~-----------------------,
v+-----..,
30Q
IN
~A7805
OUTt----_---Vo
Rl
R2
Vo
= VREF (1
+~)
VOMlN=VREF+SV
6-46
MA431A
Typical Applications (Cont.)
Higher Current Shunt Regulator
Yv--<,....--.....
V+ - .....
--""""1~-
Crow Bar
Vo
V+
~-~--~--~-----Vo
R1
R1
R2
R2
Over Voltage/Under Voltage
Protection Circuit
Voltage Monitor
V+ - .....- - - - - -.....-w\o---.....----,
V+---1~----t---1~---'
R1B
R1B
R1A
R1A
R2B
R2A
R2B
R2A
LOW UMIT "" VREF
(1 + ~)+
VBE
R2B
I,
HIGH UMIT "" VREF ~
VREF ( 1 +
R1B)
R2B
HIGH UMIT ~ VREF ( 1 +
R1A)
R2A
LOW UMIT
Fi1A)
+ RiA
It:
LED ON WHEN
~~~
r I - .-/
-4.0
o
~
-20
- 12V
=5.0V_
= 40mA
= 25"C
Q~
a" ~~ "-
"8~.~~
.0"1 i""::
t--..
> 0.6
w
~
w
,.
UI
I::
0
:J
-'
!zW
~
0.7
0:
0:
0.5
--
CUIII/£IVT
20
so
~
0.4
~
~
'0.3
15
25
35
-so
45
::; -O.11-+....,I-+-t-+--t-t-+....,---i
40
-20
o
100
-0·:':5-:.0-'----:5.':-0--'-,-:'5~-'---:2:':5-.L--:3':-5--'-45:'.
140
INPUT/OUTPUT VOLTAGE OIFFERENTlAl-V
Output Impedance vs
Frequency
Line Transient Response
0.2
6.0
.0
4.0
f-Vo
f-v,
INPUT VOLTAGE
I
0.1
-t--0.1
-
-
...I
v, = 12 V
= 5.0 V
I---TA = 25"C
= 1.0 mA TO IL = 50 mA
5.0
15
25
CL
!
I;
-2.0 >
..
I;
= 1.0 ~F
,/
I!::::> 0.'
~
v, = 12V
f----vo = 5.0 V
1.0mA
'
L == 25°C
I--TA
c."
50mA
w
0
'-'
25·C
'L
1.0
~
OQ
.i!!
"~
~U~OLTAGE r - f-
l"-
Rsc=OQ
'L
~
z
>
I
w
-0.2 I---Vo
-0.3
-5.0
01
/
5.0 V
12V
Roc
_TA
2.0
I
r-.....
o
C!
-
W
Z
JUNcnON TEMPERATURE-DC
Load Regulation vs
Input/Output Voltage Differential
~
~
0:
=1.0mA
Rsc=OQ
5.0
~
IL
0
TIME-~s
~
= 5.0 V
1--+....,f-+--+-+--+-t-+-t--;
!B0:
i"
lisc~,o" t-~ I---
0.•
~
i'-.. r--
:::>
-30
Vo
I-+-+-t-+-+-Hlisc = Oil TAo = 2S"C
0.21-+""'I-+-t-+--t-,AV = 3.0V -
ot~
>
~
1'--
Line Regulation vs
Input/Output Voltage Differential
0
4.0
Rsc=OQ
35
0.01
100
-6.0
-4.0
-5.0
45
5.0
15
25
35
45
10 K
1K
100K
1 M
FREQUENCY-Hz
INPUT/OUTPUT VOLTAGE DlFFERENTIAL-V
Typical Performance Curves for fJ.A723
Maximum Load Current vs
Input/Output Voltage Differential
200
~Jl
Jw l RTH::::< 15O"C/W
PSTANDBV
1SO
= 60 rnA
(NO HEAT SINK)
r120
.
~
g
80
40
o
TA
~
10
~r-"""'~·C
...... ?4=!.
t---
-
'~ :::...
.......
... -0.15
~
I
~
:l
!BII:
Q
g
40
INPUT/OUTPUT VOLTAGE OIFFERENTIAL-V
50
o
20
60
OUTPUT CURRENT-mA
6-59
so
= ~ ...~ l - I-- r-
~
r~~·C
r--..~~'7;->
-0.15
-0.25
100
I
I
~·C
t- v,Vo = 5.0 V
= 12V
l40
7,
I'
-0.1
-0.2
Vo = 5.0 V
=12 V
Rsc=OQ
t"" ~
-0.05
I--V,
-0.2
30
~
g
"- ...... r-.....
20
I
I
IIIII!!~
7~ = '~.C
-0.1
= 125"C
"'4..
o
"
-0.05
S
I\, TA = 2SoC
\
~ I;::::-
~
\
:::>
0
0
0.05
-
\
0:
0:
Load Regulation Characteristics
With Current-Limiting
0.05
1
i
Load Regulation Characteristics
Without Current-Limiting
o
Rsc=10Q
5.0
10
15
20
OUTPUT CURRENT-mA
25
30
1lA723
Typical Performance Curves for 1lA723
Load Regulation Characteristics
With Current-Limiting
0.1
....... ~
i
f-
-~\
..\ -';,
•
~
~n t-~
-Q.4
o
20
0.0
=
Ico
S
~
\
~... -0.3
1.0
"'\
"'\
~
~
,,~
~
;-0.2
5.Q
~ o.a
~~
~ -0.1
1.2
Vo
VREF, _
I'L =OmA
viJov I-V, = 12V
Rsc =-102
Standby Current Drain vs
Input Voltage
Current-Limiting Characteristics
~
Q.6
~
t- -
.. r-~
,;'1-- I-• I-- I--
II r-II
~'-~
o
o
20
I
81~
"n
t- Vo=5.0V~R!: ~~~
Q.2
100
80
80
40
OUTPUT CURRENT- mA
3.0
I--
ell-- I--
u
m
/
= -SSoC
TA'" 25°C
~c
'"
1.0
o
o
100
80
:..--
./ ,.....
~
I
80
40
2.0
Q
'"
TA
./'
:::>
w Q.4
!.
..~
..
10
20
30
40
50
INPUT VOLTAGE-Y
OUTPUT CURRENT-mA
Typical Performance Curves for 1lA723C
Maximum Load Current vs
Input/Output Voltage Differential
Load Regulation Characteristics
Without Current-Limiting
Current-Limiting Characteristics
1.2
h 1-
'TJuL.', ....
Ant= 1WC/W
~::~E-
180
t:r
(NOHEATSIfjK)
\ 1\
-
~
...........
r-..;;
1\
.\
\i\.
TA=7O"'C
o
10
X~
20
30
TA,
.....
liZ'
o.c
T.~2S·c- _
8
r-...~
.......
,;'
,;'
,;'r- I-
" I-- t" " de~ tl
t-
" "
r--.. T.-25·C
IT
o
---
f - vo=5.QV
-
'-- v, = 12V
V, = 12Y
-0.2
40
50
f-t sc
o
I1
Yo
0
20
o
40
80
100
80
-lAse
o
= 5.0 V
i 10 12
20
40
80
100
80
OUTPUT CURRENT-mA
OUTPUT CURRENT-mA
INPUT/OUTPUT VOLTAGE DlFFERENTIAL-V
POQII570F
Maximum Load Current vs
Input/Output Voltage Differential
~J.l)I28"b rAnt - I1t"C/W
180
PSTANDBY
n
= 60 mW
DlPPilCKAGE
Load Regulation Characteristics With
Current-Limiting
5.Q
o. 1
V,
.... ~
\
........
I'
...........
\
40
\ " ~~...,.
r>]"'{...
f- ·i~c
o
o
10
20
30
1
I I
I I
T.
~
I"40
IM'UT/OUTPUT VOLTAGE DlFFERENTIAL-V
-0.2
50
o
o.J -
~
2S·C f;::
~~
I
~~ t"<;
I I
I I
10
20
OUTPUT CURRENT-rnA
6-60
'L=OmA-
= 12V
R"F -1'Oll -
l-
30
l v.~
Vo
Vo=5.0~_
r-
(NOHEAT_)
Standby Current Drain vs
Input Voltage
i~
0.0
!i
2.0
.,~
TA
=25°C
~ ;;..:
~V
A=~
TA = 70·C
-
f-
1.0
o
o
10
20
30
INPUT YOlTAGE-V
40
50
IlA723
Typical Applications
Figure 1 Basic Low Voltage Regulator
(Vo = 2.0 V to 7.0 V)
Figure 2 Basic High Voltage Regulator
(Vo = 7.0 V to 37 V)
V,
V,
V+
V+
Vc
Vc
VAEF
OUT
OUT
VAEF
Rsc
R3
J.'A723
CL I-~--,\N"v""__ ~~~ULATED
R1
CSI-----4
CR.F
r
R3
C1
100 pF
C1
100pF
R2
Typical Performance
Regulated Output Voltage
Line Regulation (AV 1= 3.0 V)
Load Regulation (AIL = 50 mAl
R1
1NV
NJ.
R2
Typical Performance
Regulated Output Voltage
Line Regulation (AVI = 3.0 V)
Load Regulation (AIL = 50 mAl
+5.0 V
0.5 mV
1.5 mV
+15 V
1.5 mV
4.5 mV
R, R2
A3 = - - for minimum temperature drift.
R, + R2
R,R2
R3 = R1 + R2 for minimum temperature drift.
R3 may be eliminated for minimum component count.
Figure 3 Negative Voltage Regulator (Note 1)
V,
Figure 4 Positive Voltage Regulator (External NPN
Pass Transistor)
V,
,...---f---I
RS
2.0kQ
VR.F
Vz
JiA723
Q1
2N4898
CL
Rsc
R4
3.0 kQ
R3
3.0kQ
1----j.--1r
CS
R1
V-
REGULATED
OUT
C1
100pF
R1
+-........
L-_ _....._--j_ _ _ _ _ _ _
REGULATED
R2
OUT
Typical Performance
Regulated Output Voltage
Line Regulation (AV1 = 3.0 V)
Load Regulation (AIL = 100 mAl
Typical Performance
Regulated Output voltage
Line Regulation (AVI = 3.0 V)
Load Regulation (AIL = 1.0 A)
-15 V
1 mV
2 mV
Note
1. For metal can applications where Vz is required, an external 6.2 V
Zener diode should be connected in series with Va.
6-61
+15 V
1.5 mV
15 mV
JlA723
Typical Applications (Cont.)
Figure 5
Positive Voltage Regulator (External PNP
Pass Transistor)
Figure 6
Foldback Current-Limiting
V,
V,
v+
R3
60Q
V+
Vc
Rse
30 Q
OUT
VREF
Q1
2N4898
Ve
REGULATED
OUT
R3
2.7kQ
VREF
OUT
,.A723
Rt
CL
R4
5.6 kQ
IJ.A723
R1
CL
Rse
CS
R2
INV 1--4----4-.... ~~~ULATED
N.I.
R2
-=-
Typical Performance
Regulated Output Voltage
Line Regulation (~VI = 3.0 V)
Load Regulation (~IL = 10 mAl
Short Circuit Current
-=-
Typical Performance
Regulated Output Voltage
Line Regulation (.::~.vl = 3.0 V)
Load Regulation (~IL = 1.0 A)
Figure 7
+5.0 V
0.5 mV
5.0 mV
Figure 8
Remote Shutdown Regulator with CurrentLimiting (Note 1)
Output Voltage Adjust
Rt
V,
Pt
V+
_
Vc
Rse
VREF
OUT
""+-"",- ~~~ULATED
~""""1-WIr-.....
R2
"A723
R1
CL
CS
NJ.
R2
INV
1:--'V'.tv-Q1'l._"",,~
R'
CCSL
LDGICIN
2.0 kQ
-=-
-=-
Typical Performance
Regulated Output Voltage
Line Regulation (~VI = 3.0 V)
Load Regulation (~IL = 50 mAl
+5.0 V
0.5 mV
1.5 mV
Note
1. Current limit transistor may be used for shutdown if current limiting is
not required. Add diode if vo> to v.
6·62
~ON'INVERTING
+5.0 V
0.5 mV
1.0 mV
20 mA
JiA78G • JiA79G
4-Terminal Adjustable
Voltage Regulators
FAIRCHILD
A Schlumberger Company
Linear Division Voltage Regulators
Description
Connection Diagram
4-Lead TO-202 Package
(Top View)
The /lA78G and /lA79G are 4-terminal adjustable voltage
regulators. They are designed to deliver continuous load
currents of up to 1.0 A with a maximum input voltage of
+40 V for the positive regulator /lA78G and -40 V for the
negative regulator /lA79G. Output current capability can be
increased to greater than 1.0 A through use of one or
more external transistors. The output voltage range of the
/lA78G positive voltage regulator is +5 V to +30 V and
the output voltage range of the negative /lA79G is -30 V
to -2.2 V. For systems requiring both a positive and negative, the /lA78G and /1A79G are excellent for use as a
dual tracking regulator with appropriate external circuitry.
These 4-terminal voltage regulators are constructed using
the Fairchild Planar process.
•
•
•
•
•
•
IN
2
1==:
Heat sink tabs connected to common through device substrate.
Order Information
Device Code
Package Code
/1A78GU1C
Package Description
8Z
Power Watt
Connection Diagram
4-Lead TO-202 Package
(Top View)
~r-
0
O°C to 150°C
265°C
Internally Limited
IN
3
IN
OUT
:;:=;=
CO NT
2
-
COMM
1
Heat sink tabs connected to input through device substrate. Not
recommended for direct electrical connection.
+40 V
-40 V
Order Information
Control Lead Voltage
/lA78G
/lA79G
COMM
COMM
Absolute Maximum Ratings
/lA78G
/1A79G
OUT
3-
0
Output Current In Excess Of 1 A
/lA78G Positive Output +5 To +30 V
/lA79G Negative Output -30 To -2.2 V
Internal Thermal Overload Protection
Internal Short Circuit Protection
Output Transistor Safe-Area Protection
Storage Temperature Range
Operating Junction
Temperature Range
Lead Temperature (soldering, 10 s)
Power Dissipation
Input Voltage
CO NT
-~
o V-10 V
(Vo-20 V)
•. 5
;!:
-....
...
200
-25
0
25
50
Load Transient Response
~
110=
I
~
!:
III
-!.."..:.!1ItA
~
-
2
.
1
• w!Z
i
LOAD CURRENT
I
~
o
f-
- I-
OUTPUT VOLTAGE
DEVIATION
,/
100 125 150 175
JUNCTION TEMPERATURE _ °C
-1
• ••
3.
20
TIME-.l'1
4.
6
a...
-
I'
-1
-2
"
15
os
20
30
OUTPUT VOLTAGE - V
100
Q
~
.
,
•
's~~
Ripple Rejection vs Frequency
1 I
1 1
".V
iii
"T"--
~"'" -
75
85
1000
800
.~o = ~%OF Vo
-75 - 50
~ 1>
w
80
600
VI=1OV
t- ?ROPOUT CONDITIONS
•
"-
~
>
SOo
lo.~
1.•
::>
0.
- - -~ t:- r-.
-.
10 ~
,
7•
OUTPUT CURRENT - rnA
r-.
I"--.
\
75
I
;;;
3.
r-.... r-....
50 75 100 125 150 175
0.
25
--- --_IO~
25
80
-7.5
J.lA780
~
0
Ripple Rejection vs
Output Voltage
2.5
...
-25
JUNCTION TEMPERATURE _ °C
8
Dropout Voltage vs
Junction Temperature vs Frequency
!'-..",
Vo=5.0Y
10 = SOOmA
-so
i""l"'-. ......
Vo=5.0V
INPUT VOLTAGE - V
>
I
Vi = 10Y
•
V
20
"-
1.•
35
Differential Control Voltage vs
Output Current
lit
8
~
l!:Z
INPUT VOLTAGE - V
10 = SOOmA
Vo = 5.0 V
6
15
V
w
...
~
1\
::> 1.5
...u0
0.5
12
~
g
2..
u
Differential Control Voltage vs
Input Voltage
~I ,.
..
!Zw
0
~
'~ ~
,.
I
_
t~
0.5
•
~
~
~ t
'!'
/
•
~,
'-': ~
'{i
2.5
--- -
~-..
I 2.
3..
5V
IL = 20mA
TJ = WC
-
. •
~
Control Current vs
Junction Temperature
50
80
'II
••
-.
I
z
0
tw
80
..
~
40
OJ
!'i
2.
VI
= 8VT018V
Yo = 5.0Y
•••
'0 = 500 rnA
TJ =25"C
'00
1.0K
10K
.OOK
FREQUENCY - Hz
PCl1860F
6-67
J-lA78G • J.LA79G
Typical Performance Curves for J.!A79G
Line Transient Response
for MA78G
..
>
e
Peak Output Current vs
Input/Output Differential Voltage
I
20
3.0
15
2.5
z
0
..iZ
C
3()
C
10
10
5
!;
...zI
7
.
~
DEVIATION
!:j
...
...=>
..
• i
!
10 = 500 mA
Vo = s.ov
-20
o
10
12
I
II:
' ".
,~
~
...
6?K'"
~
~
TIME-~I
15
Y
•.5
/
I" I'-- !'.l"
0.5
o
...zI
~,,""
rll
0
-,.
.e
,
1.•
-
-10
0
~
2.0
a:
a: 1.5
=>
...~
OUTPUT VOLTAGE
>
..
Vo=5.0Y
TJ=WC
10
zo
"~
...=>
1.5
INPUT VOLTAGE
I
!i
Quiescent Current vs
Input Voltage
•o
30
10
15
20
25
30
3S
40
INPUT VOLTAGE - V
PC11690F
Control Current vs
Junction Temperature
Differential Control Voltage vs
Input Voltage
r--. r-.. .........
1••
>
e
0.9
.
I -2.0
0.8
1\
1.
I 0.7
...
"~
~
Z 0.8
w
a:
=> 0.5
...z
0
....
\
II:
Differential Control Voltage vs
Output Current
10
=500 mA
=25°C
100
1.0K
FREQUENCY- Hz
10K
100K
fJA 78G • fJA 79G
Typical Performance Curves for /-lA79G (Cent.)
Load Transient Response
>
>
I
E
II
z
o
~
~
"~
1
0
~
...zI
"w
"~
-5
..
VI =10 v
VO,=5'jV
0
30
40
-10
>
I
~
j!!
r- r-
1\
0
-5.0
g
...
~
!!;
V
0
10 = 500 mA
r-vl' =
JOV
20
OUTPUT VOLTAGEDEVIATION
A
g
...::>
...::>
-1
10
\
w
w
-15
1\
:;
"
g
-, o
J
z
0
co
co
::>
u
-
-
INPUT VOLTAGE
I
.
I~PU1 VO~TAGf \
OUT~UT
~OLJAGE
DEVIATION
j!!
g
~
S
Line Transient Response
20
50
I
40
60
80
100
TIME -/-IS
TIME -#-18
Test Circuits
Design Considerations
J.LA78G Test Circuit
The /lA78G and /lA79G Adjustable Voltage Regulators
have an output voltage which varies from VCONT to typically
OUT
VI
IN
Rl
CONTROL
COMM
I~
0.33 "F
COMM
R1 + R2
VI -2.0 V by Vo = VCONT - - R2
Vo
pA78G
r--
The nominal reference in the /lA78G is 5.0 V and /lA79G
is -2.23 V. If we allow 1.0 mA to flow in the control
string to eliminate bias current effects, we can make
R2 = 5.0 kn in the IJA78G. Then, the output voltage is;
Vo = (R1 + R2) V, where R1 and R2 are in kns.
0.1
R2
10
..L
CR05650F
VO=
Example:
(RI:2R2) VOONT
VOONT
Nominal = 5.0 V
By proper wiring of the feedback resistors, load regulation
of the device can be improved significantly.
/-lA79G Test Circuit 2
OUT
IN
- VI
"A79G
CONTROL
COMM
2.0 "F
1~
-Vo
-
Both /lA78G and /lA79G regulators have thermal overload
protection from excessive power, internal short circuit protection which limits each circuit's maximum current, and
output transistor safe-area protection for reducing the output current as the voltage across each pass transistor is
increased.
Rl
I .•
R2
10
COMM
..L
Vo = (
If R2 = 5.0 kn and R1 = 10 kn then
Vo = 15 V nominal, for the /lA78G
R2 = 2.2 kn and R1 = 12.8 kn then
Vo = -15.2 nominal, for the /lA79G
RI:2 R2) VeoNT
Nominal = -2.23 V
Recommended R2 current "" 1.0 rnA
:. R2 = 5.0 k.l1 (1lA78G)
R2 = 2.2 k.l1 (1lA79G)
VOONT
6-69
•
fJ.A78G • fJ.A79G
Typical Applications For p.A78G (Note 1)
Although the internal power dissipation is limited, the junction temperature must be kept below the maximum specified temperature in order to meet data sheet specifications. To calculate the maximum junction temperature or
heat sink required, the following thermal resistance values
should be used:
Max
Typ
Max
Typ
°C/W
°C/W
°C/W
Bypassing of the input and output (0.33 pF and 0.1 pF,
respectively) is necessary.
Basic Positive Regulator
iJA78G
OUT
°C/W
5.0 A) (Note 2)
V,- 2.0
0.125 IN. LEAD LENGTH
FROM PC BOARD.
__-:-:WITH 72"'C/W.1'EAT SINK
~
I\.
I
0.4 IN. LEAD LENGTH
FROM PC BOARD.
0.02
r
0.01
25
50
75
'R
rEr
100
II:
f=
r-
125
::>
~
150
j:;
::>
o.
8.0
~1nJ.-
-
'0_ 7OtnA.
r- I-r- r- ~40mA
rI-1.5
r--....I.
'0== 1.0 mA
i-=
"'""
1.0
l. I,5.0.!.V
r-Yo::
J
-1 25
6.0
~AJL05I_
I 1
>
::>
0
AMBIENT TEMPERATURE-"C
Note
Other
~
w
.....
~Ib.
~ 0.05
w
j
......
IS
0.125 IN. LEAD LENGTH
FROM PC BOARD.
FREE AIR
r- f--
Dropout Characteristics
2.5
I
5.0
~
Dropout Voltage vs
Junction Temperature
10=1.0mA-~
I
w
"~
0
>
~
5
~~
4.0
~
"-' 10 = 100 mA
2.0
lo=40mA
0.5
1!:
DROPOUTS CONDmON$
o
o
A~o = ;""0%1 Of'
25
yo
50
I
I
75
100
JUNCTION TEMPERATURE-"C
IlA 78LOO Series devices have similar curves.
6-77
125
2.0
4.0
6.0
INPUT VOLTAGE-V
8.0
10
JlA78LOO Series
Typical Performance Curves (Cont.)
Quiescent Current vs
Input Voltage
4.2
7.0
i-~O= 500 V
Il =40mA
6.0 i-TJ =:we
4.0
E
I--- l- f-"
>-
zw
()
!fl
3.0
'--.....",-
r--... -.....
::>
()
!Zw
3.4
a~
3.2
2.8
15
10
20
25
30
1'0
o
i 40 r
25
20
~~L~5
INPUT VOLTAGE
10
200
o i:!
>
OUTPUT VOLTAGE
DEVIATION
g
.....
i
I I I I VI I
::>
>-
6-100
-200
>
I
~
i!i
Q
w 100
r
o
2.0
I I
4.0
I
I 11-
6.0
8,0
100
125
o
10
.......
8.0VT018V
5.0 V
100mA
25°C
100
1.0 K
10K
100K
FREQUENCY-Hz
>
3.0
Ii
2.0
~
1.0
~
~
i!i
~~78Js
1
LOAD CURRENT
g
200
100
r-r-
_ OUTPUT VOLTAGE
DEVIATION
r
~
0-1.0
10 - 100 rnA (RESISTIVE LOAD)
r- IVOj 5
TJ
75
50
4.0
1
300
0
"~
I-Y'Vo
1-'0
-
Load Transient Response
Line Transient Response
400
20
AMBIENT TEMPERATURE_oC
INPUT VOLTAGE-V
Ii
ill
\
3.0 ,--Vo= 5.0 V
-
40
'\.
VI = 10V
1
5.0
I
z
.......
()
I
'E
60
a: 3.6
a:
6
2.0
80
!Z
w
l-
4.0
3.8
I
--
5.0
a:
a:
()
J7~~
J78LL
-..... ........
C
E
::>
100
}'A78L05 _
c
~
w
Ripple Rejection vs
Frequency
Quiescent Current vs
Temperature
--
10
i-V' = 10V
Yo = 5.0 V
-2.0
12
o
10
20
l1ME-I'S
30
40
50
80
TIME-.us
Design Considerations
The MA 78L series regulators have thermal overload protection from excessive power, internal short-circuit protection
which limits each circuit's maximum current, and output
transistor safe-area protection for reducing the output current as the voltage across each pass transistor is increased.
Package
TO-92
160
160
Thermal Considerations
The TO-92 molded package manufactured by Fairchild is
capable of unusually high power dissipation due to the
lead frame design. However, its thermal capabilities are
generally overlooked because of a lack of understanding
of the thermal paths from the semiconductor junction to
ambient temperature. While thermal resistance is normally
specified for the device mounted 1 cm above an infinite
heat sink, very little has been mentioned of the options
available to improve on the conservatively rated thermal
capability.
Although the internal power dissipation is limited, the junction temperature must be kept below the maximum specified temperature (125°C) in order to meet data sheet
specifications. To calculate the maximum junction temperature or heat sink required, the following thermal resistance
values should be used:
6-78
JJ.A 78LOO Series
An expl~lfiation of the thermal paths of the TO-92 will allow the designer to determine the thermal stress he is
applying in any given application.
ed case. The heat sink effectively replaces the eCA
(Figure 2) and the new thermal resistance, e' JA, equals
145°C/W (assuming 0.125 inch lead length).
The TO-92 Package
The TO-92 package thermal paths are complex. In addition
to the path through the molding compound to ambient
temperature, there is another path through the leads, in
parallel with the case path, to ambient temperature, as
shown in Figure 1.
The net change of 15°C/W increases the allowable power
diSSipation to 0.86 W with a minimal inserted cost. A still
further decrease in JA could be achieved by using a heat
sink rated at 46°C/W, such as the Staver FS-7A. Also, if •
the case sinking does not provide an adequate reduction
•
in total eJA, the other external thermal resistance, eLA,
may be reduced by shortening the lead length from package base to mounting medium. However, one point must
be kept in mind. The lead thermal path includes a thermal
resistance, eSA, from the leads at the mounting point to
ambient, that is, the mounting medium. eLA is then equal
to e LS + eSA. The new model is shown in Figure 2.
e
The total thermal resistance in this model is then:
(1 )
Where:
eJc = thermal resistance of the case between the
regulator die and a point on the case directly
above the die location.
= thermal resistance between the case and air at
ambient temperature.
= thermal resistance from regulator die through
the input lead to a point 1/16 inch below the
regulator case.
= total thermal resistance of the input/output
ground leads to ambient temperature.
= junction to ambient thermal resistance.
In the case of a socket, eSA could be as high as
270°C/W, thus causing a net increase in (JJA and a consequent decrease in the maximum dissipation capability.
Shortening the lead length may return the net (JJA to the
original value, but lead sinking would not be accomplished.
In those cases where the regulator is inserted into a copper clad printed circuit board, it is advantageous to have a
maximum area of copper at the entry points of the leads.
While it would be desirable to rigorously define the effect
of PC board copper, the real world variables are too great
to allow anything more than a few general observations.
Figure 1 TO-92 Thermal Equivalent Circuit
TJ
The best analogy for PC board copper is to compare it
with parallel resistors. Beyond some pOint, additional resistors are not significantly effective; beyond some point, additional copper area is not effective.
t
Pe(WATTS)
Figure 2 TO-92 Thermal Equivalent Circuit
(Lead at Other Than Ambient Temperature)
HCA
TA
'-----*---1:111-----1
Methods of Heat Sinking
With two external thermal resistances in each leg of a
parallel network available to the circuit designer as variables, he can choose the method of heat sinking most
applicable to his particular situation. To demonstrate, consider the effect of placing a small 72°C/W flag type heat
sink, such as the Staver F1-7D-2, on the /lA78LXX mold-
tPE(WATTS)
TA
L...---~o-----fllll----"""
6-79
JLA78LOO Series
High Dissipation Applications
As an example, consider a 15 V regulator with a supply
voltage of 30 ± 5.0 V, required to supply a maximum load
current of 30 mAo IQ is 4.3 mA, and minimum load current
is to be 10 mAo
R1 =
25-15-28
-="240.n
30 + 4.3
34.3
(6)
VI = 35 - (30 + 4.3) 0.24 = 35 - 8.2 = 26.8 V
R1
240 Q
V,-"",,_ _
---
PD Max = (26.8 -15) 30 + 26.8 (4.3)
= 354 + 115
= 470 mW, which permit operation up to 70 0 e
in most applications.
Vo
~
C1
C2
0.33 "F
0.1 J.LF
It
10 _ 30 mA
RL
Line regulation of this circuit is typically 110 mV for an
input range of 25 - 35 V at a constant load current;
i.e. 11 mV IV.
CROO181F
Load regulation = constant VI load regulation
(7)
(typically 10 mV, 10 - 30 mA III
+ (11 mVIV) x 0.24 x 20 mA
(typically 53 mV)
= 63 mV for a load current change of
20 mA at a constant VI of 30 V.
When it is necessary to operate a !lA78LOO regulator with
a large input! output differential voltage, the addition of series resistor R1 will extend the output current range of the
device by sharing the total power dissipation between R1
and the regulator.
VI Min-VO-2.0 V
R1 = ....:..::.:.:::.:..---'=---IL Max + IQ
(3)
Typical Applications
where:
IN---r'-l
C1
0.33 fJ.F
IQ is the regulator quiescent current.
(NOTE 2)
~_---OUT
C2
0.1 J.LF
' - - - - - -..... (NOTE 2)
Regulator power dissipation at maximum input voltage and
maximum load current is now
(4)
Notes
1. To specify an output voltage. substitute voltage value for "00".
2. Bypass capacitors are recommended for optimum stability and transient
where:
response and should be located as close as possible to the regulator.
The presence of R1 will affect load regulation according to
the equation:
Load regulation (at constant VI)
= load regulation (at constant VI)
+ line regulation (mV per V)
x (RI) x (.:lILl.
(5)
6-80
JlA78MG • JlA79MG
FAIRCHILD
4-Terminal Adjustable
Voltage Regulators
A Schlumberger Company
Linear Division Voltage Regulators
Connection Diagram
1lA78MG Power Watt
(Top View)
Description
The 1lA78MG and 1lA79MG are 4-terminal adjustable voltage regulators. They are designed to deliver continuous
load currents of up to SOO mA with a maximum input voltage of +40 V for the positive regulator 1lA78MG and
-40 V for the negative regulator 1lA79MG. Output current
capability can be increased to greater than 10 A through
use of one or more external transistors. The output voltage range of the 1lA78MG positive voltage regulator is s.o
V to 30 V and the output voltage range of the negative
1lA79MG is -30 to -2.2 V. For systems requiring both a
positive and negative, the 1lA78MG and 1lA79MG are excellent for use as a dual tracking regulator. These 4-terminal voltage regulators are constructed using the Fairchild
Planar process.
CONT
o
4t:::::;:;:==
OUT
COUM
Heat sink tabs connected to input through device substrate. Not
recommended for direct electrical connection.
Order Information
•
•
•
•
•
•
Output Current In Excess Of 0.5 A
1lA78MG Positive Output Voltage +5.0 To +30 V
1lA79MG Negative Output Voltage -30 V To -2.2 V
Internal Thermal Overload Protection
Internal Short Circuit Current Protection
Output Transistor Safe-Area Protection
Device Code
1lA78MGU1C
Package Code
8Z
Connection Diagram
pA79MG Power Watt
(Top View)
Absolute Maximum Ratings
Storage Temperature Range
Operating Junction Temperature
Range
Lead Temperature (soldering, 10 s)
Internal Power Dissipation
Input Voltage
1lA78MGC
1lA79MGC
Control Lead Voltage
1lA78MGC
1lA79MGC
Package Description
Molded Power Pack
IN
-6S0C to + 1S0°C
0
O°C to 1S0°C
26SoC
Internally Limited
OUT
CONT
COUU
IN
CDOO1fJ1F
+40 V
-40 V
Heat sink tabs connected to input through device substrate. Not
recommended for direct electricel connection.
o V<.V+ <'Vo
Vcr <'-V<'O V
Order Information
Device Code
1lA79MGU1C
6-81
Package Code
8Z
Package Description
Molded Power Pack
~A78MG
Equivalent Circuit
r----.--------------~------------~~------~~--~------~----IN
R11
O.6kO
R5
~~~--------+_--~~--------4-------4-----0UT
3.3kO
~------~-------------------------------CONTROL
R6
2.7 kO
01
R1
1 kO
R7
500 0
~--~~--~--~~--~~--~------~~--~--~~-------------------COMMON
~79MG
Equivalent Circuit (Note 1)
r---1-----------~~------~--------_1------------~--------------------_1--------~~----------COMMON
R2
Uk
l-------------------~--------_+-----------CONTROL
R23
4k
OUT
R22
0.1 k
R13
0.2 k
~--~--~------~--~--~--~--------------_4--_4--_4
Note
1. Resistor values in
n
unless otherwise noted.
6-82
________________4_--------4_----IN
J.LA78MG • J.LA79MG
J.lA78MGC
Electrical Characteristics O°C <: TA <: 125°C for J.lA78MGC, VI = 10 V, 10 = 350 rnA, CI = 0.33 J.lF, Co = 0.1 J.lF,
Test Circuit 1, unless otherwise specified.
Symbol
Condition 1,3
Characteristic
Min
Typ
Max
Unit
VIR
Input Voltage Range
TJ = 25°C
7.5
40
V
VOR
Output Voltage Range
VI =Vo + 5.0 V
5.0
30
V
Vo
Output Voltage Tolerance
Vo+3.0 V- ..........
V
!i1M
'=".c
2
00
3.0
I
.-
a:
5
Control Current vs
Temperature
Quiescent Current vs
Input Voltage
PQI1501F
Differential Control Voltage vs
Output Current
Differential Control Voltage vs
Input Voltage
••
~
10 = SOD rnA
VO=i.DY
'0
I
/
I
I
/
,/
TJ "12I"C
o.
10
15
/
•
r-.... ..........
I
-a.•
i!I!I
-5.0
e•
1-'·'·
10
..........
-1.
..........
21
-20.0
200
20
1;, ..
'~
\
\
...
400
I\.
TJ-25"C
100
1000
5
• 0
~ t- r-
5
~
Ripple Rejection vs
Frequency
21
75
~
1Of-1+IH-+-++tI-+-++++-++lI+F>.d
a:
~f-I+IH-+-++tI-+-++++-++lH+-1
~
~ko~
I"'- f::: l"'t- ~
50
20
21
30
VI
Yo
= 10 V
= 5.GY
3
LOAO CURRENT
I
i
II:
1
l- I--
OUTPUT VOLTAGE
DEVIATION
l/
20
:~ ==1:': yTO 18 V
I\..
1
10"" 500 mA
DROPOUT CONDITIONS
!JoVo= 5'fo OF Yo
•
15
Load Transient Response
!Il 101-1-:::!::±t;J::::+-f-j.~:I-++tt-+t1*-f
'0"" 500 InA.
IO~ri ....
o
,.
OUTPUT YOLTAOe - Y
mA
•
ot-""'" r-rt.....
r- l"'- I"'I"'-
'\
10
OUTPUT CUARENT -
Dropout Voltage vs
Junction Temperature
~
lo-200.mA
..........
-17.5
20
!-....
I
~::::
INPUT VOLTAGE - V
......
85
VI =10V
Vo=5.0V
I
/
Ripple Rejection vs
Output Voltage
TJ'" 25"C
100
125
JUNCTION TEMPERATURE _·C
150
·,0
-2
100
10 k
1k
FREQUENCY -
100 Ie,
PC01551F
6-85
o
••
20
~
30
TIME -
Hz
50
10
pi
PC01581F
MA78MG • MA79MG
Typical Performance Curves For 1lA78MG (Cant.)
Line Transient Response
>
E
I
.
I
I
I
I
INPUT VOLTAGE
30
zo
I
!
I
z
1
>
0
~ zo
...~
10
"
~
>
."
0"
- - I-
OUTPUT VOLTAGE
DEVIATION
I
+-r ,
~
i!!
II-
...I
1
-'o=50~ml
-10
-zo
-rOj"!",
o
10
12
10
TIME -~.
P001571F
Typical Performance Curves For 1lA79MG
Peak Output Current vs
Input/Output Differential Voltage
Quiescent Current vs
Input Voltage
BOO
-1.5
700
c
BOO
10"" -2.0 A
~
......
I
I-
0:
u
300
"
S
0 '00
ill
'§
1\
\
fA -o.s
15
20
25
"
30
-.0
~
I
I
r-.. ........ ........
-
B
J
-8.0
'\
O.4
10
- 15
20
-25
-30
-35
-40
3
~
....... ~
r--- .....
VI =10V
Vo = -5.0 V
o
o
..... ~
' I =f"JnAJ
25
50
75
100
125
Ripple Rejection vs
Output Voltage
80
VI =10Y
Yo =LOY
.,,/
3.0
1. /
,/
'
1.V
~c,
~;.-'"
V
70
.....
aD
0
~o~
' ' ' '...
1""" ......
50
..........
0
-10
-1.
-5.0
lOUT
=-.
A
YOUT "'-5.0Y
-10
0
-15
INPUT VOLTAGE - V
-25
150
JUNCTION TEMPERATURE- °C
Differential Control Voltage vs
Output Current
II
"
~
I :...
4.0
'" " ""-
~o
I O.5 ....
ffi0:
I'
INPUT VOLTAGE-V
~
I"""'"~'C
·4.0
0.8
~
1
INPUT/OUTPUT DIFFERENTIAL - V
Differential Control Voltage vs
Input Voltage
/
I
~
\
V
./V
ffi
OOC
I
o
/lYo"" 5% OF Jo
0.4
10001-n,-"-n,-"-n,-,,,,.,....,
'~500IhA
I-
1. 0
Ripple Rejection vs
Frequency
Load Transient Response
40
50
TIME-IAI
:+H-+-++t+-+-++It-l
10 ' 200 mA
TJ '2S·C ,
10
100
Ik
10 k
100 k
FREQUENCY - Hz
PC01661F
Typical Performance Curve For J.tA78MG and J.lA79MG
Worst Case Power Dissipation vs
Ambient Temperature
Line Transient Response
.
100
50
~
INPUT VOLTAGE
I
z
!
'"
~
§!
I
>
I
0
-5
\
vo"sr
!
LIMITS FOR C GRADE-
......
I~FINiTE ~EA~ SIN~
10
!!o 3.0
2.0
a: 1.0
!
"
10 =200 mA
z0
30
20
;: 5.0 ;;;;;; ~
~~
"'< 2QoC/W "lis ~ 700
4.0
.
." ;a
..
!j
DEVIAnON
I
. ..
-10~
OUTPUT VOLTAGE
..
~
o
;;0
i\
,...
-s
,
-15
0
0.5
0.'
0.3
0.2
-
~
y-....j.
k- ~ r--
r- 1-0 "d",L i ' ..... 1'... 1\
-~"o\"
~
I""-
8JC "" 12°CJW
80
TIME-IJS
100
0.1
25
50
75
100
125
150
AMBIENT TEMPERATURE _ °C
Design Considerations
Example:
The !LA78MG and !LA79MG variable voltage regulators
have an output voltage which varies from VCONT to
typically
VI -2.0 V by Vo = VCONT
\\
I\.~
PO(MAX} = 7.5 W
(R1 + R2)
R2
If R2 = 5.0 kQ and R1 = 10 kQ then
Vo = 15 V nominal, for the !LA78MG;
R2 = 2.2 kQ and R1 = 12.8 kQ then
Vo = -15.2 V nominal, for the !LA79MG.
By proper wiring of the feedback resistors, load regulation
of the devices can be improved significantly.
The nominal reference in the !LA78MG is 5.0 V and
IlA79MG is -2.23 V. If we allow 1.0 mA to flow in the
control string to eliminate bias current effects, we can
make R2 = 5 kQ in the !LA78MG. The output voltage is
then: Vo = (R1 + R2) Volts, where R1 and R2 are in kQs.
Both !LA78MG and j.tA79MG regulators have thermal overload protection from excessive power, internal short circuit
protection which limits each circuit's maximum current, and
output transistor safe-area protection for reducing the
6-87
1lA78MG ellA79MG
Basic Positive Regulator
output current as the voltage across each pass transistor
is increased.
OUT
Although the internal power dissipation is limited, the junction temperature must be kept below the maximum specified temperature in order to meet data sheet
specifications. To calculate the maximum junction temperature or heat sink required, the following thermal resistance
values should be used:
>V,o-_-~
0.33
~F
+Vo
IN,.A78MG
R1
CONTROL
COMMON
0.1
~F
R2
-::CROO191F
Typical
IJJC
Package
8.0
Power Watt
Typical
IJJA
12.0
70
Vo - VCONT (
75
R1 + R2)
"""Fi2
Positive 5.0 V to 30 V Adjustable Regulator
TJ Max- TA
POMax- B
B or
JC+ CA
OUT
TJ Max- TA
B
0.33
(Without a heat sink)
+Vo
~A78MG
+VI
IN
CONTROL
COMMON
~F
0.1 p.F
Skll
JA
IJCA = Bcs + BSA
Solving for TJ:
TJ = TA + Po(IJJc + BcAl or
TA + POIJJA (Without heat sink)
Where
= Junction Temperature
TJ
= Ambient Temperature
TA
= Power Dissipation
Po
IJJC = Junction-to-case thermal resistance
IJCA = Case-to-ambient thermal resistance
IJcs = Case-to-heat sink thermal resistance
IJsA = Heat sink-to-ambient thermal resistance
BJA = Junction-to-ambient thermal resistance
Positive 5.0 V to 30 V Adjustable Regulator 10> 1.5 A
Q11>1.SA_
...---""
R1
2N6124
OUT I-(0",1",)_ _
VR Max(Jl + 1)
-10
Max
If load is not ground raferenced, connect reverse biased diodes from
outputs to ground.
Output Waveform
.,
Typical Applications for MA79MG (Note 1)
~
Bypass capacitors are recommended for stable operation
of the 1lA79MG over the input voltage and output current
ranges. Output bypass capacitors will improve the transient
response of the regulator.
,,/:::"1
The bypass capacitors, (2.0 j.lF on the input, 1.0 j.lF on
the output) should be ceramic or solid tantalum which
have good high frequency characteristics. If aluminum electrolytics are used, their values should be 10 j.lF or larger.
The bypass capacitors should be mounted with the shortest leads, and if possible, directly across the regulator terminals.
OV----------
Nole
1. All resistor values in ohms.
6-89
MA78MG • MA79MG
Typical Applications for #lA79MG (Note 1) (Cont.)
Negative High Current Voltage Regulator External
Series Pass
Negative High Current Short Circuit Protected
Regulator
Rac
Q1
-Vo
Rl
In
=--.,.-+-f
-VI-~M+____
H~--+-""'--Vo
lo~
R2
Rl
1.0 IJ.F
#lA78MG Test Circuit 1
Rl =
iJVBE(OI)
V,
IN
.A7IMG
Basic Negative Regulator
-VI
2.0.F
OUT
.A7IMO
IN
CONTROL
COMMON
Rl
CONTROL
O.I.F
0.33 .F
-Vo
R2
Rl
1.0.F
R2
Rl
+ R2)
Vo= ( ~
R1
Vo
OUT
IR Max({l) -10 Max
VCONT
VCONT Nominally = 5 V
+ R2)
VO--VCONT ( ~
#lA79MG Test Circuit 2
-30 V to -2.2 V Adjustable Regulator
--
1-1~_-t--Vo
IN
-VI
CONTROL
COMM
It
R1
+ R2)
VCONT
VCONT Nominally = -2.23 V
Recommended R2 current'" 1 rnA
:.R2 = 5 kn (pA78MG)
R2 - 2.2 kn (pA79MG)
6-90
-
*1
R2
10
1Vo= ( ~
Rl
.A78MG
F
Nate
1. All resistor values in ohms.
-Vo
OUT
JlA78MOO Series
3-Terminal Positive
Voltage Regulators
F=AIRCHILD
A Schlumberger Company
Linear Division Voltage Regulators
Description
The pA78MOO series of 3-terminal medium current positive
voltage regulators is constructed using the Fairchild Planar
Epitaxial process. These regulators employ internal currentlimiting, thermal shutdown and safe-area compensation
making them essentially indestructible. If adequate heat
sinking is provided, they can deliver in excess of 0.5 A
output current. They are intended as fixed voltage regulators in a wide range of applications including local (oncard) regulation for elimination of noise and distribution
problems associated with single-point regulation. In addition
to use as fixed voltage regulators, these devices can be
used with external components to obtain adjustable output
voltages and currents.
Connection Diagram
TO-39 Package
(Top View)
•
•
•
•
•
•
•
Order Information
Device Code Package Code
pA78M05HM
FC
pA78M06HM
FC
pA78M08HM
FC
pA78M12HM
FC
pA78M15HM
FC
pA78M24HM
FC
pA78M05HC
FC
pA78M06HC
FC
pA78M08HC
FC
pA78M12HC
FC
pA78M15HC
FC
pA78M24HC
FC
COMMON
OUT
Lead 3 connected to case.
Output Current In Excess Of 0.5 A
No External Components
Internal Thermal Overload Protection
Internal Short Circuit Current-Limiting
Output Transistor Safe-Area Compensation
Available In JEDEC TO-220 And TO-39 Packages
Output Voltages Of 5 V. 6 V. 8 V. 12 V. 15 V. And
24 V
• Available In Extended Temperature Range
Absolute Maximum Ratings
Storage Temperature Range
TO-39 Metal Can
TO-220 Package
Operating Junction Temperature Range
Extended (pA78MOOM)
Commercial (pA78MOOC)
Lead Temperature
TO-39 Metal Can (soldering, 60 s)
TO-220 Package (soldering, 60 s)
Power Dissipation
Input Voltage
5.0 V to 15 V
24 V
-65'C to + 175'C
-65'C to + 150'C
-55'C to + 150'C
O'C to +150'C
Package Description
Metal
Metal
Metal
Metal
Metal
Metal
Metal
Metal
Metal
Metal
Metal
Metal
Connection Diagram
TO-220 Package
(Top View)
300'C
265'C
Internally Limited
35 V
40 V
"""""'F
Lead 3 connected to case.
Order Information
Device Code Package Code
pA78M05UC
GH
pA78M06UC
GH
pA78M08UC
GH
pA78M12UC
GH
pA78M15UC
GH
pA78M24UC
GH
6-91
Package Description
Molded Power Pack
Molded Power Pack
Molded Power Pack
Molded Power Pack
Molded Power Pack
Molded Power Pack
MA78MOO Series
Equivalent Circuit
IN
Q12
Rn
0.6 Q
R5
3.3kQ
OUT
A6
2.7 kQ
D1
R7
500Q
'--_~
___
~
_ _ _-+_ _ _
1lA78M05
Electrical Characteristics -55°C:;;;; TA:;;;; 125°C, VI
otherwise specified.
VR
LINE
VR LOAD
Output Voltage
TJ = 25°C
Line Regulation
TJ = 25°C
Load Regulation
TJ = 25°C
~
_ _ _ COMMON
V, 10 = 350 rnA, CI = 0.33 /IF, Co
Min
= 0.1
/IF, unless
Typ
Max
5.0
5.2
V
7.0 V"';;;; V, ..,;;;; 25 V,
10 = 200 rnA
3.0
50
rnV
8.0 V"';;;;V,"';;;;20 V,
10= 200 rnA
1.0
25
5.0 rnA"';;;; 10"';;;;500 rnA
20
50
5.0 rnA"';;;; 10"';;;;200 rnA
10
25
4.8
Vo
Output Voltage
8.0 V "';;;;V,"';;;;20 V,
5.0 rnA"';;;; 10 ..,;;;; 350 rnA
10
Quiescent Current
TJ = 25°C
Ala
Quiescent
Current Change
I with
I with
___
Condition 1
Characteristic
Symbol
Vo
= 10
~_-6--_~
4.7
4.5
V
7.0
rnA
rnA
8.0 V"';;;; VI ..,;;;; 25 V, 10 = 200 rnA
0.8
load
5.0 rnA"';;;; 10 ..,;;;; 350 rnA
0.5
Noise
T A = 25°C, 10Hz"';;;; f
..,;;;; 100 kHz
AV,/AVo
Ripple Rejection
f = 2400 Hz, 10 = 125 rnA, TJ = 25°C
Voo
Dropout Voltage
TA = 25°C
8.0
62
6-92
40
80
2.0
rnV
5.3
line
No
Unit
MVNo
dB
2.5
V
J,LA78MOO Series
~78M05 (Cont.)
Electrical Characteristics -55°C";; T A ";; 125°C, VI
otherwise specified.
Symbol
= 10
V, 10 = 350 rnA, CI = 0.33 p.F, Co = 0.1 IJ.F, unless
Condition 1
Characteristic
los
Output Short Circuit Current
TJ = 25°C, VI = 35 V
Ipk
Peak Output Current
TJ = 25°C
!:No/ AT
Average Temperature
Coefficient of Output Voltage
10= 5.0 rnA
~78M05C
Electrical Characteristics O°C";; TA ..;; 125°C, VI
otherwise specified.
Symbol
= 10
Output Voltage
TJ = 25°C
VR LINE
Line Regulation
TJ = 25°C
Load Regulation
Vo
Output Voltage
0.5
TJ = 25°C
Typ
Max
Unit
300
600
rnA
0.7
1.4
A
0.4
rnvrc/
Vo
I -55°C ";TA"; +25°C
I + 25°C ";TA"; + 125°C
V, 10 = 350 rnA, CI
= 0.33
Condltlon 1
Characteristic
Vo
VR LOAD
Min
0.3
IJ.F, Co = 0.1 IJ.F, unless
Min
Typ
Max
5.0
5.2
V
7.0 V";VI";25 V,
10=200 rnA
3.0
100
mV
8.0 V..; VI ..; 20 V,
10=200 rnA
1.0
50
5.0 rnA"; 10 ..; 500 rnA
20
100
5.0 rnA"; 10 ..; 200 rnA
10
50
4.8
7.0 V..; VI ..; 20 V,
5.0 rnA"; 10 ..; 350 rnA
4.75
TJ = 25°C
mV
5.25
V
8.0
rnA
0.8
rnA
la
Quiescent Current
Ala
Quiescent
Current Change
No
Noise
TA=25°C, 10 Hz";f";100 kHz
AVI/AVo
Ripple Rejection
f = 2400 Hz, 10 = 125 rnA, TJ = 25°C
VDO
Dropout Voltage
TA = 25°C
2.0
V
los
Output Short Circuit Current
TJ = 25°C, VI = 35 V
300
rnA
Ipk
Peak Output Current
TJ = 25°C
700
rnA
AVo/AT
Average Temperature
Coefficient of Output Voltage
10=5.0 rnA
1.0
rnvrc
I with line
I with load
4.5
Unit
8.0 V"; VI ..; 25 V, 10 = 200 rnA
5.0 rnA"; 10 ..; 350 rnA
6·93
0.5
62
40
p.V
80
dB
~78MOO
J.LA78M06
Electrical Characteristics -55°C.s;; TA .s;; 125°C, VI
otherwise specified.
Symbol
= 11
V,
10
= 350
Series
rnA, CI
= 0.33
Condition 1
Typ
Max
6.0
6.25
8.0 V ";;V,";;25 V,
10=200 mA
5.0
60
9.0 V..;; V, ..;; 20 V,
10=200 mA
1.5
30
5.0 mA";;lo";;500 mA
20
60
Characteristic
Vo
Output Voltage
TJ = 25°C
VR L'NE
Line Regulation
TJ = 25°C
IlF, Co = 0.1 IlF, unless
Min
,5.75
VR LOAD
Load Regulation
TJ = 25°C
Vo
Output Voltage
9.0 V";;V,";;21 V,
5.0 mA";;lo";;350 mA
IQ
Quiescent Current
~IQ
Quiescent
Current Change
5.0 mA";;lo";;200 mA
4.5
mV
30
6.3
V
7.0
mA
0.8
mA
5.0 mA";;lo";;350 mA
0.5
No
Noise
TA=25°C, 10 Hz";;f";;100 kHz
Ripple Rejection
f = 2400 Hz, 10 = 125 mA, TJ = 25°C
Voo
Dropout Voltage
TA=25°C
los
Output Short Circuit Current
TJ = 25°C, V,=35 V
IPk
Peak Output Current
TJ = 25°C
~Vo/~T
Average Temperature
Coefficient of Output Voltage
10=5.0 mA
J.LA78M06C
Electrical Characteristics O°C.s;; TA .s;; 125°C, VI
otherwise specified.
= 11
8.0
Vo
Output Voltage
TJ = 25°C
VR UNE
Line Regulation
TJ = 25°C
59
0.5
V,
10
= 350
rnA, CI
= 0.33
40
IlVlVo
80
dB
2.0
2.5
V
300
600
mA
0.7
1.4
A
0.4
mVrCI
0.3
Vo
I -55°C ";;TA";; + 25°C
I +25°C ";;TA";; + 125°C
Condltlon 1
Characteristic
IlF, Co = 0.1 IlF unless
Min
5.75
Typ
Max
Unit
6.0
6.25
V
8.0 V";;V,";;25 V,
10=200 mA
5.0
100
mV
9.0 V ";;V,";;20 V.
10=200 mA
1.5
50
5.0 mA";;lo";;500 mA
20
120
VR LOAD
Load Regulation
TJ = 25°C
Vo
Output Voltage
8.0 V..;; V, ..;; 21 V.
5.0 mA";;lo";;350 mA
IQ
Quiescent Current
~IQ
Quiescent
Current Change
5.0 mA";;lo";;200 mA
10
5.7
4.5
mV
60
6.3
V
8.0
mA
9.0 V ";;V,";;25 V. 10 = 200 mA
0.8
mA
5.0 mA";;lo";;350 mA
0.5
TJ = 25°C
I with line
I with load
V
mV
9.0 V..;; V, ..;; 25 V, 10 = 200 mA
TJ = 25°C
I with line
I with load
~V,/~Vo
Symbol
10
5.7
, .. Unit
6-94
MA78MOO Series
/-IA78M06C (Cont.)
Electrical Characteristics O°C ~ T A ~ 125°C, VI
= 11
V, 10 = 350 rnA, CI
= 0.33
/-IF, Co
= 0.1
/-IF unless
otherwise specified.
Symbol
Condition 1
Characteristic
No
Noise
TA = 25°C, 10Hz ~ f
~
Min
Typ
100 kHz
Unit
MV
80
dB
!lVI/!lVO
Ripple Rejection
f = 2400 Hz, 10 = 125 rnA, TJ = 25°C
VDO
Dropout Voltage
TA = 25°C
2.0
V
los
Output Short Circuit Current
TJ = 25°C, VI = 35 V
270
rnA
IPk
Peak Output Current
TJ = 25°C
700
mA
!lVo/!lT
Average Temperature
Coefficient of Output Voltage
10= 5.0 mA
0.5
mV/oC
/JA78M08
Electrical Characteristics -55°C ~ T A ~ 125°C, VI
= 14
V, 10 = 350 rnA, CI
59
Max
45
= 0.33
/-IF, Co
= 0.1
/-IF, unless
otherwise specified.
Symbol
Vo
VR
LINE
VR LOAD
Condition 1
Characteristic
Output Voltage
TJ = 25°C
Line Regulation
TJ = 25°C
Load Regulation
TJ = 25°C
Min
Typ
Max
8.0
8.3
V
10.5 V~VI~25 V,
10= 200 mA
6.0
60
mV
11 V~VI~20 V,
10=200 mA
2.0
30
7.7
5.0
mA~lo~500
mA
25
80
5.0
mA~lo~200
mA
10
40
Vo
Output Voltage
11.5 V~VI~23 V,
5.0 mA~lo~350 mA
la
Quiescent Current
TJ = 25°C
!lla
Quiescent
Current Change
No
Noise
TA = 25°C, 10Hz ~ f
!lVI/!lVO
Ripple Rejection
f = 2400 Hz, 10 = 125 mA, TJ = 25°C
VDO
Dropout Voltage
TA = 25°C
los
Output Short Circuit Current
TJ = 25°C, VI = 35 V
Ipk
Peak Output Current
TJ = 25°C
!lVo/!lT
Average Temperature
Coefficient of Output Voltage
10= 5.0 mA
I with line
I with load
11.5
5.0
7.6
4.6
V~VI~25
V, 10=200 mA
mA~lo~350
100 kHz
8.0
56
0.5
I -55°C ~ TA ~ +25°C
I +25°C ~TA ~ +125°C
6-95
mV
8.4
V
7.0
mA
0.8
mA
0.5
mA
~
Unit
40
80
MVNo
dB
2.0
2.5
V
300
600
mA
0.7
1.4
A
0.4
mV/oC
0.3
MA78MOO Series
MA78M08C
Electrical Characteristics 0°C
12V
-UmA
.......
~'2.04
.......
".0
0.1
26
50
i
,
.
"
S
......
.......
ia!
11 ...
-so
-25
0
25
50
75 100 125 150 175
-
1.0
I-- r-~J
~
i
II:
II:
-so
4.8
e-
4.7
~
.......
I, 1~~~~
i
~
L I l~
0.'
~
20
26
30
INPUT/OUTPUT VOLTAGE OIFFERENTIAL-V
U
150
10
15
-25 0
TJ =125OCI
~ ='oomA--.
_____
25
10
r-
=
~"'" f_1o;-:!mA
o
75 100 125 150 175
4.3
I!V
~
~
II
o
2.0
0
4.1
4.G
8.0
6.0
10
100 r-T-rr......,r-T"TT1r--rr-TTTTr-T-r"TTT-'
8Om:l~~
i:H-+tH-++HH-++t+-+-++++--l
i
"
M 4,'
5
= 100 mA
I !/
INPUT VOLTAGE-V
J.nl
I
e:r
Ripple Rejection vs
Frequency
Vil
I
Vo = 5.0 V
Io = 200 rnA
II
V~
"""
~ ~ r---,o
/
2.0
50
4.5
~
"'"
10 "20"",:::::-
i--
Jni
_~o.l5.oJ
4.6
G 4A
!i:w
20
V,
= a.ov TO 18 '-V+++t+-+-HtH
r
L
H'-t-Ht-+-t-H+-l
I 111 "F I 1Ii
Vo=5.0V
_\'0T :: 200
mA
25
4.0
o~~~~~~-L~-L-LLU~
10
15
20
25
30
35
INPUT VOLTAGE-V
-75 -50 -25
0
25
50
75 100 125 150 175
AMBIENT TEMPERATURE-"C
I-IA78MOO
Series devices have similar curves,
6-101
10
100
1.0 K
10 K
100 K
FREQUENCY-Hz
PC120SOF
Note
Other
fi.:~
':,,,~,
Dropout Characteristics
a.o
r-..:
f-~~~~~~~S
o ...1.1 1 i
75
~~-
1/
3.0
5.0
"'f::::.
~
~
'\
Quiescent Current vs
Temperature
::OCmA
".....
..til-
,. ...... ~
,,~""c
JUNClION TEMPERATURE-OC
Quiescent Current vs
Input Voltage
5.0
0,6
...... r--;: ~
~"'" -
-
0.5
JUNClION TEMPERATURE-OC
r+.Jo .IUIV
iG
.............
J ....
~-
I"'-- ......
.::::: ~
0
~
75
r-
15
11.88
11.80
125
100
-- --
• .0
II:
~11.96
0.8
10.4
'.5
w 1.5
0 '1 .92
75
~
- r- r- \ \
•
1.0
PC01841F
II:
"
r\1\
.
AMBIENT TEMPERATURE-"C
~i78l.
=
-10
~~
Dropout Voltage vs
Junction Temperature
-v! = ~.v'
Yo
12.12
..... ~
f\.\.~-
8JC -S.OIJC/W
"" .... ~7.5w··1
150
Output Voltage vs
Junction Temperature
12.1'
~""'9Ir~
CI.2
AMBIENT TEMPERATURE-"C
12.20
.
~
S
-10 -TJ"UOC
o
I:
"
10
10
0.0
20
>
J.
~
~1.0
~
ij
~
!i
S
I
-20
o
r--
OUTPUT VOLTAGE
DEYlA110N
0
1.0
l"-
V
0-1.0
j
2.0
'.0
e.o
4.0
-2.0
10
12
o
10
20
Design Considerations
The 1lA78MOO fixed voltage regulator series has thermaloverload protection from excessive power, internal short
circuit protection which limits the circuit's maximum current,
and output transistor safe-area compensation for reducing
the output short circuit current as the voltage across the
pass transistor is increased.
Although the. internal power dissipation is limited, the junction temperature must be kept below the maximum specified temperature (150·C for 1lA78MOO; 125·C for
1lA78MOOC) in order to meet data sheet specifications. To
calculate the maximum junction temperature or heat sink
required, the following thermal resistance values should be
used:
Max
(lJC
Typ
Package
Typ
(lJC
(lJA
Max
(lJA
TO-39
TO-220
18
3.0
25
5.0
120
60
140
40
TJ Max-TA
Po MAX = "
"
or
vJC + "CA
TJMax-TA
="
.JJA
30
40
50
80
TlME-~
TlME-II-_
(lCA
.J..ri,.,L
I
I
LOAD CURRENT
5
10 -6ODmA,
5.0 V
-vo
c--y.Vo=S.DV
=10V
Where:
TJ
= Junction Temperature
= Ambient Temperature
TA
= Power Dissipation
Po
(lJC = Junction to case thermal resistance
(lCA = Case-to-ambient thermal resistance
(lcs = Case-to-heat sink to resistance
(lSA = Heat sink-to-ambient thermal resistance
(lJA = Junction-to-ambient thermal resistance
Typical Applications
Fixed Output Regulator
IN -Wlr-t--t
0.33 p.F
(NOTE 2)
1"-_--- OUT
+
0.1 p.F
(NOTE 2)
Notes
1. To specify an output voltage, substitute voltage value for "XX".
2. Bypass capaCitors are recommended for optimum stability and transient
response and should be located as close as possible to the regulator.
(Without a heat Sink)
= (lcs + (lSA
Solving for TJ:
TJ = TA + Po«(lJC + (lCA) or
= TA + Po (lJA (Without a heat sink)
6-102
J,lA78S40
Universal Switching
Regulator Subsystem
FAIRCHILD
A Schlumberger Company
Linear Division Voltage Regulators
Description
Connection Diagram
16-Lead DIP
(Top View)
The MA78S40 is a monolithic regulator subsystem consisting of all the active building blocks necessary for switching
regulator systems. The device consists of a temperature
compensated voltage reference, a duty-cycle controllable
oscillator with an active current limit circuit, an error amplifier, high current, high voltage output switch, a power diode and an uncommitted operational amplifier. The device
can drive external NPN or PNP transistors when currents
in excess of 1.5 A or voltages in excess of 40 V are
required. The device can be used for step-down, step-up
or inverting switching regulators as well as for series pass
regulators. It features wide supply voltage range, low
standby power dissipation, high efficiency and low drift. It
is useful for any stand-alone, low part count switching system and works extremely well in battery operated systems.
16
DIODE
CATHODE
SWITCH
COLLECTOR
DIODE
ANODE
DRIVER
COLLECTOR
SWITCH
EMmER
v,
OPAMPOUT
OPAMP
SUPPLY
• Step-Up, Step-Down or Inverting Switching
Regulators
• Output Adjustable From 1.25 V to 40 V
• Peak Currents To 1.5 A Without External Transistors
• Operation From 2.5 V to 40 V Input
• Low Standby Current Drain
• 80 dB Line And Load Regulation
• High Gain, High Current, Independent OP AMP
• Pulse Width Modulation With No Double Pulsing
TIMING CAPACITOR
OPAMP +IN
GND
OPAMP -IN
COMPARATOR -IN
REFERENCE
VOLTAGE
COMPARATOR +IN
CD01400F
Order Information
Device Code
Package Code
MA78S40DM
MA78S40PV
MA78S40DC
MA78S40PC
Package Description
78
98
78
98
Ceramic DIP
Molded DIP
Ceramic DIP
Molded DIP
Block Diagram
COMPARATOR COMPARATOR
+IN -IN
nMING
GROUND CAPACITOR
r--
Ipk
SENSE
V,N
_1__ __1 ___ _
DRIVER
COLLECTOR
SWITCH
COLLECTOR
--,
I
I
I
I
I
I
I
I
I
I
I
I
1...--_--.
I
I
I~";;;';;;;~
L __
REFERENCE OP AMP
VOLTAGE
-IN
OP AMP
+IN
•
IpK SENSE
OP AMP
SUPPLY
OP AMP
OUT
6-103
--Fi-J
SWITCH
EMITTER
DIODE
ANODE
DIODE
CATHODE
MA78S40
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Extended (J,LA 78S40M)
Industrial (J,LA78S40V)
Commercial (J,LA78S40C)
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1,2
16L-Ceramic DIP
16L-Molded DIP
Input Voltage from V+ to VInput Voltage from V+ Op Amp to V-
-65°C to + 175°C
-65°C to + 150°C
-55°C to + 125°C
-40°C to + 125°C
O°C to +70°C
300°C
265°C
1.50 W
1.04 W
40 V
40 V
Common Mode Input Range
(Error Amplifier and Op Amp)
Differential Input Voltage 3
Output Short Circuit Duration
(Op Amp)
Current from VREF
Voltage from Switch
Collectors to GND
Voltage from Switch
Emitters to GND
Voltage from Switch
Collectors to Emitter
Voltage from Power Diode to GND
Reverse Power Diode Voltage
Current through Power Switch
Current through Power Diode
-0.3 to V+
±30 V
Indefinite
10 mA
40 V
40 V
40 V
40 V
40 V
1.5 A
1.5 A
Notes
1. T J Max
= 150·C for the Molded DIP, and 175·C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 25·C. Above this temperature,
derate the 16l-Ceramic DIP at 10 mWrC, and the 16l-Molded DIP at
8.3 mWrC.
3. For supply voltages less than 30 V. the absolute maximum voltage is
equal to the supply voltage.
Functional Description
The ,uA78S40 is a variable frequency, variable duty cycle
device. The initial switching frequency is set by the timing
capacitor. 1 The initial duty cycle is 6:1. This switching frequency and duty cycle can be modified by two mechanisms - the current limit circuitry (Ipk sense) and the
comparator.
The comparator modifies the OFF time. When the output
voltage is correct, the comparator output is in the HIGH
state and has no effect on the circuit operation. If the
output voltage is too high then the comparator output
goes LOW. In the LOW state the comparator inhibits the
turn-on of the output stage switching transistors. As long
as the comparator is LOW the system is in OFF time. As
the output current rises the OFF time decreases. As the
output current nears its maximum the OFF time approaches its minimum value. The comparator can inhibit
several ON cycles, one ON cycle or any portion of an ON
cycle. Once the ON cycle has begun the comparator cannot inhibit until the beginning of the next ON cycle.
The current limit modifies the ON time. The current limit is
activated when a 300 mV potential appears between lead
13 (Vcel and lead 14 (lPk)' This potential is intended to
result when designed for peak current flows through Rsc.
When the peak current is reached the current limit is
turned on. The current limit circuitry provides for a quick
end to ON time and the immediate start of OFF time.
Generally the oscillator is free running but the current limit
action tends to reset the timing cycle.
Increasing load results in more current limited ON time
and less OFF time. The switching frequency increases with
load current.
VFD is the forward voltage drop across
diode. It is listed on the data sheet as
1.5 V maximum. If an external diode is
forward voltage drop must be used for
the internal power
1.25 V typical,
used, then its own
VFD.
VSAT is the voltage across the switch element (output
transistors 01 and 02) when the switch is closed or ON.
This is listed on the data sheet as output saturation voltage.
Output saturation voltage 1 - defined as the switching element voltage for 02 and 01 in the Darlington configuration with collectors tied together. This applies to Figure 1,
the step down mode.
Output saturation voltage 2 - switching element voltage for
01 only when used as a transistor switch. This applies to
Figure 2, the step up mode.
For the inverting mode, Figure 3, the saturation voltage of
the external transistor should be used for VSAT.
Note
1. Oscillator frequency is set by a single external capacitor and may be
varied over a range of 100 Hz to 100 kHz.
6-104
MA78S40
J.tA78S40
Electrical Characteristics TA = Operating temperature range, VI
specified.
Symbol
Characteristic
= 5.0
V, VOp Amp
= 5.0
V, unless otherwise
Condition
Unit
General Characteristics
IcC
Icc
Supply Current
(Op Amp Disconnected)
VI = 5.0 V
1.8
3.5
mA
VI =40 V
2.3
5.0
mA
Supply Current
(Op Amp Connected)
VI = 5.0 V
4.0
mA
VI = 40 V
5.5
mA
Reference Section
VREF
Reference Voltage 1
IREF = 1.0 mA
VR LINE
Reference Voltage Line
Regulation
VI = 3.0 V to VI = 40 V, IREF = 1.0 mA,
TA = 25°C
VR LOAD Reference Voltage Load
Regulation
Extend -55°C < TA < +125°C,
Comm 0 < TA < + 70°C,
Indus -40°C < TA < + 85°C
1.180
IREF=1.0 mA to IREF=10 mA, TA=25°C
1.245
1.310
V
0.04
0.2
mV/v
0.2
0.5
mV/mA
Oscillator Section
ICHG
Charging Current
VI = 5.0 V, TA = 25°C
20
50
p.A
ICHG
Charging Current
VI=40 V, TA=25°C
20
70
p.A
IDISCHG
Discharge Current
VI = 5.0 V, TA = 25°C
150
250
p.A
IDISCHG
Discharge Current
VI = 40 V, TA = 25°C
150
350
f.l.A
Vosc
Oscillator Voltage Swing
VI = 5.0 V, TA = 25°C
ton/toff
Ratio of Chargel
Discharge Time
0.5
V
6.0
f.l.s/f.l.s
Current Limit Section
VCLS
Current Limit Sense Voltage
mV
Output Switch Section
VSAT 1
Output Saturation Voltage 1
Isw = 1.0 A, Figure 1
1.1
1.3
V
VSAT 2
hFE
Output Saturation Voltage 2
Isw = 1.0 A, Figure 2
0.45
0.7
V
Output Transistor Current Gain
Ic=1.0 A, VCE=5.0 V, TA = 25°C
70
IL
Output Leakage Current
Vo=40 V, TA=25°C
10
nA
Power Diode
IDR
Forward Voltage Drop
ID = 1.0 A
V
Diode Leakage Current
VD = 40 V, TA = 25°C
nA
Comparator
VIO
Input Offset Voltage
VCM = VREF
1.5
15
mV
liB
Input Bias Current
VCM = VREF
35
200
nA
110
Input Offset Current
VCM = VREF
5.0
75
nA
6-105
t-tA78S40
j.lA78S40 (Cont.)
Electrical Characteristics TA = Operating temperature range, VI
specified.
Symbol
Characteristic
= 5.0
V, VOp Amp
Condition
= 5.0
V, unless otherwise
Min
Typ
0
VCM
Common Mode Voltage Range
TA
= 25°C
PSRR
Power Supply Rejection Ratio
VI = 3.0 V to 40 V, TA = 25°C
70
Max
Unit
V1-2
V
96
dB
Output Operational Amplifier
VIO
Input Offset Voltage
VCM= 2.5 V
4.0
15
mV
nA
liB
Input Bias Current
VCM = 2.5 V
30
200
110
Input Offset Current
VCM= 2.5 V
5.0
75
Avs+
Voltage Gain +
RL = 2.0 kn to GND; Vo = 1.0 V to 2.5 V,
TA = 25°C
25
250
V/mV
Avs-
Voltage Gain-
RL = 2.0 kn to V+ (Op Amp)
Vo = 1.0 V to 2.5 V, T A = 25°C
25
250
V/mV
VCM
Common Mode Voltage Range
TA = 25°C
CMR
Common Mode Rejection
VCM = 0 V to 3.0 V, TA = 25°C
76
100
dB
PSRR
Power Supply Rejection Ratio
V+ Op Amp = 3.0 to 40 V, TA = 25°C
76
100
dB
10+
Output Source Current
TA = 25°C
75
150
mA
10-
Output Sink Current
TA = 25°C
10
35
mA
SR
Slew Rate
TA = 25°C
0.6
VIIlS
VOL
Output Voltage LOW
IL = -5.0 mA, T A = 25°C
VOH
Output Voltage HIGH
IL = 50 mA, T A = 25°C
0
Note
1. Selected devices with tightened tolerance reference voltage available.
6-106
Vcc-2
1.0
V+OP
Amp
-3.0 V
nA
V
V
V
MA78S40
Design Formulas
CHARACTERISTIC
STEP-DOWN
STEP-UP
INVERTING
-ton
VO+VD
Vo +VD-VI
IVol+VD
toff
VI-VSAT-VO
VI- VSAT
VI-VSAT
(ton + toff) Max
-
1
-
CT
4 X 10- 5 ton
4 X 10- 5 ton
Ipk
2 10 Max
ton + toff
210M
1
JJ.s
fMin
fMin
0 _ _-
ax
4 X 10- 5 ton
210 Max
ton + toff
0 ___
toff
JJ.F
A
toff
LMin
(VI-VSAT-VO)
I
ton Max
pk
(VI-VSAT)
- 1 - - ton Max
pk
(VI-VSAT)
- 1 - - ton Max
pk
JJ.H
Rse
0.33/lpk
0.33/lpk
0.33/lpk
n
Ipk (ton + toff)
10
""--
8 Vripple
Vripple
Note
VSAT ~
~
-
fMin
Co
Vo
1
UNIT
Saturation voltage of the switching element
Forward voltage of the flyback diode
6-107
10
0
ton
""--
VriPple
0
ton
JJ.F
JIA78S40
Figure
Figure 2
Typical Step-Down Operational Performance
(TA = 25°C)
Rsc
V,
25V
=
L
Rsc
V,
10V
0.33 Q
Typical Step-Up Operational Performance
(TA 25°C)
3OOI'H
0.332
""'
Cy
0.01 JJ.F
~
--,
V,N
IBlAS- - - -
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
t----["
Ql
I
I
I
I
I
I
I
I
I""
Cy
OSCILLATOR
I
I
J
~1,214
I
I
~
I
I
\
10= 100 mA
8.0 V < VI < 18 V
5.0 mA
i
8
........
~
r--..
r-V'
I
1 1 1
i
0
25
50
75
8.0
100 125 150 175
100
75
125
1
6.0
4.0
~
4.0
g
• .0
o
1.0
I
o
~
m
.."
I'
2.0
4.0
r':
DA
6.0
INPUT VOLTAGE-V
-
8.0
15
2.0
:-- r-
20
~
I""-' r::::: ~
1.5
L I
0.4
j
~~
1.6
2.0
2.4
-r- ~"'A.
~
"'A.
r- ~~
-75
-so
-2S
0
2S
so
7S 100 125 lSO 175
JUNcnON TEMPERATURE-oC
4.6
JnJs
VI = 10V
-Vo=5.DV
10 = 500mA
JAJ.-
--
f-
"""
J78.&~-
Quiescent Current vs
Junction Temperature
~O ~ s.~ V 1
-~J :~.~
V
30
f- DROPOUT CONDmONS
!J.Vo = 5.0% OF Vo
o
1.2
25
r- I- ~~A.
;:-
~
l! 0.5
~
0.8
~
~ l-
I07~~
........
S 1.0
0
I-
f- f-
V
II
i
I ../..
10
........
>
/
-
~O=100mA~~ '" I~ Joo JA -
I
2.0
5.0
f-
Dropout Voltage vs
Junction Temperature
II
= lOY
Yo = S.OY
-TJ = 25°C
""'c
I" '.so;
"
l'...
INPUT/OUTPUT DlFFERENTlAL-Y
1
_y,
"
I Ie
I
ZI
o
o
5.0
t
~
t
o
w
-LJ", i'/"h
/
I'
2.5
'.0
I
~
~
n
1.0
OUTPUT CURRENT-A
JAJ.-
-TJ =25'C
1.5
150
Quiescent Current vs
Input Voltage
~o 25.D~
.....
~
,,~ ~
""<'$:"....... :::--, ""-
0
I"
= 150"C
JnJs
~
...........
=19V
Vo
-so -25
."
5a.
I
't*"~~
0.5
5
....... ~
'1 .9
o
',\
"!'§
.......
Dropout Characteristics
..
5
(.)
=65' C/W
50
JUNCnON TEMPERATURE-"C
g
........
"
i" ',\
>
12.0
-75
"!'§
......
)
},If--.
2.0
w
II!
II!
5.0
1
~
~
Hs:::: 7$oC/..,
~TS
r--:!."IC
1
~
6.0
,l781k-
= 12V
11.8f-1o =.DrnA
>
'.'c:-",
Current·Limiting Characteristics
".2
I!i
'''.~ s ..,.......
•
~~nJs
1
1
AMBIENT TEMPERATURE-DC
Output Voltage vs
Junction Temperature
~ 1~
2.5
= 5.0"C/W
AMBIENT TEMPERATURE_DC
,
3.0
= 0 C/W
r-
W 1.0
'\'
........
--
r--
20
II!
D.' r-- .Je =5.0' C/W
0.2 r-- .JA = 65' C/W
TJ MAX = 150"C "I
0.1
25
UMIT FOR "A78OOC -
50
40
30
= OC/W
10 i--
-
100
f--
40
30
Peak Output Current vs
Input/Output Voltage Differential
Worst Case Power Dissipation vs
Ambient Temperature (TO·220)
l10
3."
5.0
10
15
20
25
INPUT VOLTAGE-V
6-122
30
35
• .6
-75 -50 -25
0
25
50
75 100 125 150 175
JUNcnON TEMPERATURE_oC
IlA7800 Series
Typical Performance Curves (Cont.)
Ripple Rejection vs
Frequency
Line Transient Response
100
40
,1J.1.k
F
80
!
60
0
"
u
w
OJ
a:
r4
~
10
g
a:
r,YI
20
Yo
r-~
z::::
I
1-10 rTJ =25'C I
==c
10 • ... mA
mA
10
ryo
-20
100
1.0K
10K
100 K
o
=S.oy
2.0
4.0
~
=5.0 y
10
JnJ.
I
r.-:-'I "'10Y
~
I
g
o
L
1.0
r- -r- OU~~:~AGE
~
I\..
I
Ct..
= S.GY
250C
=OjA-f
II<
1111
1
~
10 = 20mA
I
~
V
I
,19,=500mA
0-1.0
-2.0
1.
10
J~
V,I ~ 1~~1I
Yo
TA
1.0
S
,"
'.0
LOAD CURRENT
~ '.0
8.0
Output Impedance vs
Frequency
Load Transient Response
4.0
6.0
nME-JA-S
FREQUENCY-Hz
Yo
i
DEVlAT10N
0
o
1010
20
30
40
50
60
TIUE-f.4.
•10
100
'K
10K
FREQUENCY-Hz
Note
The other p.A7800 series devices have similar curves.
DC Parameter Test Circuit
0.1 JLF
Vo
6-123
~
~
'.0 g
OUTPUT VOLTAGE
8.0 V TO 18 V
=5.0 V
"
10
~
40
20
"~ni..
I
INPUT VOLTAGE
lOOK
.11
tlA7800 Series
Design Considerations
Typical Applications
The !1A7800 fixed voltage regulator series has thermal
overload protection from excessive power dissipation, internal short circuit protection which limits the regulator's maximum current, and output transistor safe-area compensation
for reducing the output current as the voltage across the
pass transistor is increased.
Although the internal power dissipation is limited, the junction temperature must be kept below the maximum specified temperature (150°C for Jl.A7800, 125°C for Jl.A7800C)
in order to meet data sheet specifications. To calculate
the maximum junction temperature or heat sink required,
the following thermal resistance values should be used:
Package
Typ IiJC
°C/W
Max IiJC
°C/W
Typ IiJA
°C/W
Max IiJA
°C/W
TO-3
3.5
5.5
35
40
TO-220
3.0
5.0
40
60
Fixed Output Regulator
v,----_-I
I-_---vo
0.33 p.F
Notes
1. To specify an output voltage, substitute voltage value for "'XX."'
2. Bypass capacitors are recommended for optimum stability and transient
response. and should be located as close as possible to the regulator.
High Input Voltage Circuits
I-O-.....---vo
'--__+-__-+
0.1 p.F
(NOTE 2)
TJMax-TA
Po Max =" +" . or
"JC "CA
v, _ _-""\
TJ MaxTA
= - - , , - (Without heat sink)
"JA
~"",,--vo
0.1 ;.tF
IiCA = lics + liSA
Solving for TJ:
TJ=TA+Po(IiJc+licAl or
= TA + POIiJA (Without heat sink)
Where:
TJ
TA
Po
IiJC
IiCA
lics
liSA
IiJA
High Current Voltage Regulator
= Junction Temperature
= Ambient Temperature
= Power Dissipation
= Junction-to-case thermal resistance
= Case-to-ambient thermal resistance
= Case-to-heat sink to thermal resistance
= Heat sink-to-ambient thermal resistance
= Junction-to-ambient thermal resistance
v,-_----=>·
13(01)
~
10
Max
IREG Max
R1 = ~ =
IREG
6-124
13(01)VSE(Q1)
(13 + 1) -10 Max
IREG Max
I1A 7800 Series
Dual Supply Operational Amplifier Supply
(±15 V@1.0 A)
·20I~ ---1r--t
J.=4r---....------~~~ v
1----,.--1
GND--.~~-~~~-~~~-~_.-----GND
lN4001 DR
EQUIVALENT
I---+---....-----~:ir v
High Output Current, Short Circuit Protected
Roc
I N -.....---.-""'~.....""'
Q2
2N6124
I--+_.-DUT
Rl
0.1 "F
3.02
0.8
Rsc=ISC
R1 =
iNBE(Q1)
IREG Max (~+ 1) -10 Max
Positive and Negative Regulator
6·125
JlA 79MOO Series
3-Terminal Negative
Voltage Regulators
FAIRCHIL.D
A Schlumberger Company
Linear Division Voltage Regulators
Description
The }.LA79MOO series of 3-Terminal Medium Current Negative Voltage Regulators are constructed using the Fairchild
Planar Epitaxial process. These regulators employ internal
current-limiting, thermal shutdown, and safe-area compensation making them essentially indestructible. If adequate
heat sinking is provided, they can deliver up to 0.5 A output current. They are intended as fixed voltage regulators
in a wide range of applications including local (on-card)
regulation for elimination of noise and distribution problems
associated with single-point regulation. In addition to use
as fixed voltage regulators, these devices can be used
with external components to obtain adjustable output voltages and currents.
Connection Diagram
TO-39 Package
(Top View)
•
•
•
•
•
•
Order Information
Device Code Package Code
MA79M05HM
FC
MA79M08HM
FC
MA79M12HM
FC
MA79M15HM
FC
MA79M05AHC
FC
MA79M08AHC
FC
MA79M12AHC
FC
MA79M15AHC
FC
Output Current In Excess Of 0.5 A
Internal Thermal Overload Protection
Internal Short Circuit Current-Limiting
Output Transistor Safe-Area Compensation
Available In JEDEC TO-220 And TO-39 Packages
Output Voltages Of -5 V, -8 V, -12 V, and -15 V
Absolute Maximum Ratings
Storage Temperature Range
TO-39 Metal Can
TO-220 Package
Operating Junction Temperature Range
Extended (MA79MOOM)
Commercial (MA79MOOAC)
Lead Temperature
TO-39 Metal Can (soldering, 60 s)
TO-220 Package (soldering, 60 s)
Power Dissipation
Input Voltage
-5.0 V to -15 V
-65°C to + 175°C
-65°C to + 150°C
-55°C to + 150°C
O°C to + 150°C
IN
OUT
Lead 3 connected to case.
Package Description
Metal
Metal
Metal
Metal
Metal
Metal
Metal
Metal
Connection Diagram
TO-220 Package
(Top View)
300°C
265°C
Internally Limited
::;('"
rOUT
~I :~Ii
-35 V
\..
\..COMMON
IN
Lead 3 connected to case.
Order Information
Device Code
Package Code
MA79M05AUC
GH
MA79M08AUC
GH
MA79M12AUC
GH
MA79M15AUC
GH
6-126
Package Description
Molded Power Pack
Molded Power Pack
Molded Power Pack
Molded Power Pack
I1A79MOO Series
Equivalent Circuit
r-----~----------~------~--~------------~------------~--------._--~-COMMON
R25
4.5 k
TO 6.3 k
R20
17.2 k
6.4k
4.0k
R24
1.7 k
TO 18 k
.....-w~---_J
-12 V end-24 V
R5
OPTIONS
420
•
R23
I
I
I
I
.---+--f-------....l
OUT
Ql
R22
0.1
R30
200
R6
800
R13
0.2
IN
IlA79M05H
Electrical Characteristics -55°C';;; TA';;; 125°C, V, = -10 V, 10 = 350 rnA, C, = 2.0 IlF, Co = 1.0 IlF, unless
otherwise specified. 1,2
Symbol
Output Voltage
Vo
VR
LINE
VR LOAD
TJ = 25°C
Load Regulation
Output Voltage
10
Quiescent Current
L\lo
Quiescent Current
Change
Noise
Min
Typ
Max
-5.2
-5.0
-4.8
l-25 V';;'V,';;'-7.0 V
7.0
50
1-18 V';;'VI';;'-8.0 V
TJ = 25°C
Line Regulation
Vo
No
Condition 3
Characteristic
3.0
30
TJ = 25°C, 5.0 rnA';;' 10';;' 500 rnA
75
100
TJ = 25°C, 5.0 rnA';;' 10';;' 350 rnA
50
-25 V';;'VI';;'-7.0 V,
5.0 rnA';;' 10';;'350 rnA, PD';;'4.0 W
TJ = 25°C
I with line
I with load
-5.25
-4.75
V
rnV
rnV
V
2.0
rnA
-25 V.;;, VI';;'-8.0 V
0.4
rnA
5.0 rnA';;' 10';;'350 rnA
0.4
TA = 25°C, 10 Hz';;'t';;'100 kHz
6-127
1.0
Unit
25
80
MVNo
J.lA 79MOO Series
1lA79M05H (Cont.)
Electrical Characteristics -55°C';;; TA .;;; 125°C, VI
otherwise specified. 1,2
Symbol
= -10
V, 10 = 350 rnA, CI
= 2.0
Condition 3
Characteristic
Min
Ripple Rejection
f = 2400 Hz, 10 = 125 mA, TJ = 25°C
Voo
Dropout Voltage
TJ = 25°C
los
Output Short Circuit Current
TJ = 25°C, VI = -35 V
Ipk
Peak Output Current
VI-Vo=10 V, TJ=25°C
f1Vo/f1T
Average Temperature Coefficient
of Output Voltage
10 = 5.0 mA, O°C < TA < 125°C
f1VI/t:No
1lA79M05AC
Electrical Characteristics -O°C';;; TA .;;; 125°C, VI
otherwise specified. 1,2
Symbol
= -10
V, 10 = 350 rnA, CI
= 2.0
Max
J.!F, Co
0.65
= 1.0
2.3
A
1.4
A
0.3
my/oCt
Vo
J.!F, unless
Typ
Max
-5.0
-4.8
1-25 V 0.20
I
w
Co
"
....
"a
.
"j'MAX =7.• W
Output Voltage vs
Junction Temperature
g
700
··C/I\<
. . . . . . . ~If~.l
AMBIENT TEMPERATURE-"C
"~
' " HEAT
SINK
~
I
2.0
0.2
~-'---'-...JL......I.....L...J._L.-'---'-....J
0.1
0.15
~""C/
is
a:
w 0.5
;t
w 0 .•
~
Co
~
"'j..;::
800
"INFINITE
. . . -ko"sJ,
5.0
4.0
;t 3.0
Peak Output Current vs
Input/Output Voltage Differential
10 K
100 K
NOMINAL OUTPUT VOlTAGE-V
MA 79MOO Series
Typical Performance Curves (Cont.)
Line Transient Response
Output Impedance vs
Frequency
Load Transient Response
2.0
3.0
101
INPUT VOLTAGE
-15
1\
L
>
~
,
>
r
0
OUTP1
DEVIAnoN
V
g
,
>
~
I-~I
o
80
Co
= 25p.F
il~MINMTI
§-1.0
-2.
40
60
TlME-p..
= 1.01LF
SOUD TANTAWM
ou~uJ
VOL~AGE- t DEVIATION
"~
i!!
I
5.o r~O =200mA
Vo = 5.0 V
20
Co
1.0
w
-5.0 ~
\i
LOAD CURRENT
~
~
\
1.0
2.0
Iii
-10 ~
vJLTAGE- l - I--
10 - 100 MA
Vo= -5.0 V
TJ = 25°C
= lOY
Vf =f Ov ,
30
40
50
10- 10
Design Considerations
The safe-area protection network may cause the device to
latch-up if the output is shorted and the regulator is operating with high input voltages. This mode of operation will
not damage the device. However, power (input voltage or
the load) must be interrupted momentarily for the device
to recover from the latched condition.
Although the internal power dissipation is limited, the junction temperature must be kept below the maximum specified temperature (150°C for /lA79MOO, 125°C for
/lA79MOOC and /lA7900MAC) in order to meet data sheet
specifications. To calculate the maximum junction temperature or heat sink required, the following thermal resistance
values should be used:
Package
TO-39
18.0
25
120
140
TO-220
3.0
5.0
60
40
TJ Max- TA
POMAX = 8 + 8
or
JC
CA
100
1.0K 10K lOOK 1.0M 10M 100M
FREQUENCY-Hz
TlME-,us
The /l79MOO fixed voltage regulator series have thermaloverload protection from excessive power, internal shortcircuit protection which limits the circuit's maximum current,
and output transistor safe-area compensation for reducing
the output current as the voltage across the pass transistor is increased.
111111111
2
20
10
100
Solving for TJ:
TJ=TA+PO (8Jc+8cA) or
= TA + P0 8JA (Without a heat sink)
Where:
TJ
TA
Po
8JC
8CA
8cs
8sA
8JA
= Junction Temperature
= Ambient Temperature
= Power Dissipation
= Junction-to-case thermal resistance
= Case-to-ambient thermal resistance
= Case-to-heat sink thermal resistance
= Heat sink-to-ambient thermal resistance
= Junction-to-ambient thermal resistance
Typical Applications
Bypass capacitors are necessary for stable operation of
the/lA79MOO series of regulators over the input voltage
and output current ranges. Output bypass capacitors will
improve the transient response of the regulator.
The bypass capacitors, (2.0 /IF on the input, 1.0 /IF on
the output) should be ceramic or solid tantalum which
have good high frequency characteristics. If aluminum electrolytics are used, their values should be 10 /IF or larger.
The bypass capacitors should be mounted with the shortest leads, and if possible, directly across the regulator terminals.
Fixed Output Regulator Test Circuit
(1 )
V,--_9_---i
2.0"F
TJ Max - TA (Without a heat sink)
8JA
8CA = 8cs + 8SA
6-134
I---+--Vo
1.0p.F
IlA7900 Series
3-Terminal Negative
Voltage Regulators
F=AIRCHILD
A Schlumberger Company
Linear Division Voltage Regulators
Description
The jJ.A7900 series of monolithic 3-terminal negative regulators is manufactured using the Fairchild Planar Epitaxial
process. These negative regulators are intended as complements to the popular jJ.A7800 series of positive voltage
regulators, and they are available in voltage options from
-5.0 V to -15 V. The jJ.A7900 series employ internal current-limiting, thermal shutdown, and safe-area compensation, making them virtually indestructible.
•
•
•
•
•
•
Connection Diagram
To-3 Package
(Top View)
Output Current In Excess Of 1.0 A
Internal Thermal Overload Protection
Internal Short Circuit Current-Limiting
Output Transistor Safe-Area Compensation
Available In JEDEC TO-220 And TO-3 Packages
Output Voltages of -5 V, -8 V, -12 V, and -15 V
Order Information
-55'C to + 150'C
O'C to +150'C
Device Code
jJ.A7905KM
jJ.A7908KM
jJ.A7912KM
jJ.A7915KM
jJ.A7905KC
jJ.A7908KC
jJ.A7912KC
jJ.A7915KC
300'C
265'C
Internally Limited
Connection Diagram
TO-220 Package
(Top View)
Absolute Maximum Ratings
Storage Temperature Range
TO-3 Metal Can
TO-220 Package
Operating Junction Temperature Range
Extended (jJ.A7900M)
Commercial (jJ.A7900C)
Lead Temperature
TO-3 Metal (soldering, 60 s)
TO-220 Package (soldering, 10 s)
Power Dissipation
Input Voltage
-5 V to -15 V
-65'C to + 175'C
-65'C to + 150'C
Package Code
HJ
HJ
HJ
HJ
HJ
HJ
HJ
HJ
Package Description
Metal
Metal
Metal
Metal
Metal
Metal
Metal
Metal
rOUT
-35 V
~I :I~;
~~IN
Note
1. The convention for Negative Regulators is the Algebraic value. thus -15
is less then -10 V.
"
\.....IN
' - - COMMON
Lead 3 connected to case.
Order Information
Device Code
jJ.A7905UC
jJ.A7908UC
jJ.A7912UC
jJ.A7915UC
6-135
Package Code
GH
GH
GH
GH
Package Description
Molded Power Pack
Molded Power Pack
Molded Power Pack
Molded Power Pack
J.lA7900 Series
Equivalent Circuit
r-----~--------------~~--------_1~_1------------------._----------------._----------._----._-COMMON
R2
1.4kQ
R25
R23
4.0kQ
4.5 kQ
T06.3kQ
I
I
R24
1.7 kQ
I
R4
2.2 kQ
TO 18kQ
1_12 V AND
I -15V
I OPTIONS
.-J/ ~I--I---~._
OUT
R5
420Q
01
020
Rlg
5.3 kQ
C3
3 pF
R16
4.7kQ
R14
2.3kQ
R17
3.0kQ
R21
17 kQ
R30
200Q
R22
O.04Q
R13
O.05Q
IN
6·136
J.LA 7900 Series
1-!A7905
< <
Electrical Characteristics -55°C TA 125°C, VI = -10 V, 10 = 500 rnA, CI = 2.0 j.lF, Co = 1.0 j.lF, unless
otherwise specified.
Symbol
Vo
VR
LINE
VR LOAD
Conditlon 1
Characteristic
Output Voltage
TJ
Line Regulation
TJ
Load Regulation
TJ
= 25°C
= 25°C
= 25°C
Min
3.0
50
-2.0 V';;;VI';;;-12 V
1.0
25
15
100
5.0
25
5.0 rnA';;; 10 .;;; 1.5 A
Vo
Output Voltage
10
Quiescent Current
ala
Quiescent Current
Change
No
Noise
TA = 25°C, 10Hz';;; 1.;;; 100 kHz
aVI/aVo
Ripple Rejection
1 = 2400 Hz, 10 = 350 rnA, TJ
VDO
Dropout Voltage
10 = 1.0 A, TJ
Ipk
Peak Output Current
TJ
aVo/aT
Average Temperature Coefficient 01
Output Voltage
los
Output Short Circuit Current
j.lA7905C
-8.0 V';;;VI';;;-20 V
5.0 rnA';;; 10 .;;; 1.0 A
p';;;15 W
-4.70
= 25°C
IWith load
1.0
5.0 rnA';;; 10 .;;; 1.0 A
= 25°C
10 = 5.0 rnA,
mV
V
2.0
rnA
1.3
rnA
0.5
= 25°C
25
80
pVIVo
54
60
1.1
2.3
1.3
2.1
3.3
A
0.3
mVioClVo
1.2
A
= 25°C
-55°C';;; TA';;; 125°C
VI = -35 V, TJ
V
mV
-5.30
-8.0 V';;;VI';;;-25 V
Iwith line
Unit
Max
-7.0 V ';;;VI';;;-25 V
250 rnA';;; 10 .;;; 750 rnA
TJ
Typ
-4.8 -5.0 -5.2
= 25°C
dB
V
< <
Electrical Characteristics O°C TA 125°C, VI = -10 V, 10 = 500 rnA, CI = 2.0 j.lF, Co = 1.0 j.lF, unless
otherwise specified.
Symbol
Vo
VR
LINE
VR LOAD
Condltion 1
Characteristic
Output Voltage
TJ
Line Regulation
TJ
= 25°C
= 25°C
Min
Typ
Max
-4.8
-5.0
-5.2
V
-7.0 V';;;VI';;;-25 V
3.0
100
mV
-8.0 V';;; VI';;;-12 V
1.0
50
15
100
5.0
50
TJ = 25°C 5.0 rnA';;; 10';;; 1.5 A
Load Regulation
250 rnA';;; 10';;;750 rnA
Vo
-7.0 V';;;VI';;;-20 V,
5.0 rnA';;; 10';;; 1.0 A,
p';;; 15 W
Output Voltage
= 25°C
-4.75
-5.25
Unit
mV
V
10
Quiescent Current
TJ
2.0
rnA
ala
Quiescent Current
Change
IWith line
-7.0 V';;;VI';;;-25 V
1.3
rnA
IWith load
5.0 mA';;;lo';;;1.0 A
0.5
No
Noise
TA
= 25°C,
1.0
10 Hz';;;I';;;100 kHz
6-137
125
IlV
J.lA 7900 Series
1lA7905C (Cont.)
Electrical Characteristics O°C
~ T A ~ 125°C, VI
otherwise specified.
Symbol
= -10
V, 10 = 500 rnA, C I = 2.0 IlF, Co= 1.0 IlF, unless
Condition 1
Characteristic
!lVlI tNo
Ripple Rejection
VDO
Dropout Voltage
IPk
Peak Output Current
!:Nol LlT
Average Temperature
Coefficient of Output Voltage
10 = 5.0 mA, OOG";; TA";; 125°C
IlA7908
Electrical Characteristics
Min
Typ
54
Max
Unit
60
dB
10=1.0 A, TJ = 25°C
1.1
V
TJ = 25°C
2.1
A
0.4
mV/oC
f = 2400 Hz, 10 = 350 mA, TJ = 25°C
-55°C~TA~125°C, VI=-14 V, 10=500
rnA, CI=2.0 IlF, Co=1.0 IlF, unless
otherwise specified.
Symbol
Condition 1
Characteristic
Min
Typ
Max
-7.7
-8.0
-8.3
6.0
80
Vo
Output Voltage
TJ = 25°C
VA
Line Regulation
TJ = 25°C -10.5 V";;VI";;-25 V
-11 V";; VI ..;; -17 V
2.0
40
Load Regulation
TJ = 25°C 5.0 mA";; 10";; 1.5 A
12
100
4.0
40
LINE
VA LOAD
250 mA";;lo";;750 mA
Vo
Output Voltage
-11.5 V";;VI";;-23 V,
5.0 mA";; 10";; 1.0 A,
p";;15 W
la
Quiescent Current
Llla
Quiescent Current
Change
-7.6
TJ = 25°C
Unit
V
mV
mV
-8.4
1.0
V
2.0
mA
[with line
-11.5 V";;VI";;-25 V
1.0
mA
[with load
5.0 mA";; 10 ..;; 1.0 A
0.5
No
Noise
TA=25°C, 10 Hz";;f";;100 kHz
LlVI/LlVo
Ripple Rejection
f = 2400 Hz, VI = -13 V
10 = 350 mA, TJ = 25°C
VDO
Dropout Voltage
10=1.0 A, TJ
IPk
Peak Output Current
TJ
LlVoILlT
Average Temperature
Coefficient of Output Voltage
los
Output Short Circuit Current
= 25°C
= 25°C
10 = 5.0 mA, -55°C";; TA";; 125°C
VI
25
80
pVlVo
54
60
1.1
2.3
1.3
2.1
3.3
A
0.3
mV/oClVo
1.2
A
= -35 V, TJ = 25°C
dB
V
1lA7908C
Electrical Characteristics O°C ~ T A ~ 125°C, VI = -14 V, 10 = 500 rnA, C I = 2.0 IlF, Co = 1.0 IlF, unless
otherwise specified.
Symbol
Vo
Condition 1
Characteristic
Output Voltage
TJ = 25°C
6-138
Min
Typ
Max
Unit
-7.7
-8.0
-8.3
V
#-LA 7900 Series
1lA7908C (Cont.)
Electrical Characteristics O°C';;;; TA .;;;; 125°C, V, = -14 V, 10 = 500 mA, C, = 2.0 IlF, Co = 1.0 IlF, unless
otherwise specified.
Symbol
VR
LINE
VR LOAD
Condltlon 1
Characteristic
Line Regulation
TJ = 25°C
Load Regulation
TJ = 25°C
Min
Typ
Max
Unit
160
rnV
-10.5 V":V,":-25 V
6.0
-11 V":V,":-17 V
2.0
80
5.0 rnA": 10 ..: 1.5 A
12
160
250 rnA": 10 ..: 750 rnA
4.0
80
Vo
Output Voltage
-10.5 V":V,":-23 V,
5.0 rnA": 10": 1.0 A,
p": 15 W
10
Quiescent Current
TJ = 25°C
dlo
Quiescent Current
Change
-7.6
-8.4
1.0
rnV
V
2.0
rnA
rnA
Iwith line
-10.5 V..: V,":-25 V
1.0
Iwith load
5.0 rnA": 10": 1.0 A
0.5
200
/lV
60
dB
1.1
V
No
Noise
TA = 25°C, 10 Hz":f": 100 kHz
dV,/dVo
Ripple Rejection
f = 2400 Hz, V, = -13 V,
10 = 350 rnA, TJ = 25°C
VDO
Dropout Voltage
10 = 1.0 A, TJ = 25°C
Ipk
Peak Output Current
TJ = 25°C
2.1
A
dVo/dT
Average Ternperature
Coefficient of Output Voltage
10 = 5.0 rnA, O°C": TA ..: 125°C
0.6
rnV/oC
54
1lA7912
Electrical Characteristics -55°C';;;;TA';;;;125°C, V,=-19 V, 10=500 mA, C,=2.0 IlF, Co=1.0 IlF, unless
otherwise specified.
Symbol
Condltlon 1
Characteristic
Output Voltage
TJ = 25°C
VR
Line Regulation
TJ = 25°C -14.5 V":V,":-30 V
Load Regulation
TJ = 25°C 5.0 rnA": 10": 1.5 rnA
LINE
Min
10
-16 V ":V,":-22 V
VR LOAD
Typ
Max
-11.5 -12.0 -12.5
Vo
250 rnA": 10 ..: 750 rnA
Vo
Output Voltage
-15.5 V ":V,":-27 V,
5.0 rnA": 10 ..: 1.0 A,
p": 15 W
10
Quiescent Current
TJ = 25°C
dlO
Quiescent Current
Change
120
3.0
60
12
120
4.0
60
-11.4
-12.6
1.5
1.0
5.0 rnA": 10 ..: 1.0 A
0.5
Noise
TA=25°C, 10 Hz":f":100 kHz
f=2400 Hz, V,=-17 V,
10 = 350 rnA, TJ = 25°C
6-139
25
54
60
V
rnA
-15 V ":V,":-30 V
Ripple Rejection
rnV
rnA
IWith load
No
V
rnV
3.0
Iwith line
dV,/dVo
Unit
80
/lVlVo
dB
MA7900 Series
~7912 (Cont.)
Electrical Characteristics -55°C';;;; T A';;;; 125°C, V,
otherwise specified.
Symbol
Voo
= -19
V, 10 = 500 rnA, C, = 2.0 fJF, Co = 1.0 fJF, unless
Condition 1
Characteristic
Dropout Voltage
10 -1.0 A, TJ
'Pk
Peak Output Current
TJ = 25°C
t.Volt.T
Average Temperature
Coefficient of Output Voltage
10 = 5.0 rnA, -55°C";; TA";; 150°C
los
Output Short Circuit Current
VI
= -35
Min
= 25°C
1.3
V, TJ
Typ
Max
1.1
2.3
Unit
V
2.1
3.3
A
0.3 mVrClVo
= 25°C
A
1.2
~7912C
Electrical Characteristics 0°C';;;;TA';;;;125°C, V,=-19 V, 10=500 rnA, C,=2.0 fJF, Co=1.0 fJF, unless
otherwise specified.
Symbol
Condition 1
Characteristic
Vo
Output Voltage
VR LINE
Line Regulation
= 25°C
TJ = 25°C
VR LOAD
Load Regulation
TJ
= 25°C
Min
Typ
Max
-11.5 -12.0 -12.5
TJ
-14.5 V";;VI";;-30 V
10
-16 V";;VI";;-22 V
3.0
120
5.0 rnA";;
12
240
4.0
120
'0 . ; 1.5 A
250 rnA";; '0";;750 rnA
Vo
Output Voltage
-14.5 V";;VI";;-27 V,
5.0 rnA";; '0 ..;; 1.0 A,
p";;15 W
10
Quiescent Current
TJ
t.lo
Quiescent Current
Change
-11.4
240
-12.6
= 25°C
1.5
1.0
5.0 rnA";; '0 ..;; 1.0 A
0.5
t.Vl/t.Vo
Ripple Rejection
f = 2400 Hz, VI = -17 V,
10 = 350 rnA, TJ = 25°C
Voo
Dropout Voltage
10 = 1.0 A, TJ
Ipk
Peak Output Current
TJ
t.Volt.T
Average Temperature
Coefficient of Output Voltage
10 = 5.0 rnA, O°C";; TA";; 125°C
V
rnA
-14.5 V";;VI";;-30 V
TA=25°C, 10 Hz";;f";;100 kHz
mV
rnA
lwith line
Noise
V
mV
3.0
lwith load
No
Unit
300
p.V
60
dB
1.1
V
54
= 25°C
= 25°C
2.1
A
0.8
mVrC
Note8
1. All characteristics except noise voltage and ripple rejection ratio are measured using pulse techniques (tw .;; 10 ms, duty cycle .;; 5%). Output voltage changes due to
changes in internal temperature must be taken into account separately.
~7915
Electrical Characteristics -55°C';;;; TA .;;;; 125°C, V, = -23 V, 10 = 500 rnA, C, = 2.0 fJF, Co = 1.0 fJF, unless
otherwise specified.
Symbol
Vo
Condltion 1
Characteristic
Output Voltage
TJ
= 25°C
6-140
Min
Typ
Max
Unit
-14.4
-15.0
-15.6
V
J.1A 7900 Series
!lA7915 (Cont.)
Electrical Characteristics -55°C ~ T A ~ 125°C, VI
= -23
V, 10
= 500
mA, CI
= 2.0
IJ.F, Co
= 1.0
IJ.F, unless
otherwise specified.
Symbol
VR
LINE
Condition 1
Characteristic
Line Regulation
TJ = 25°C
Min
Typ
11
150
3.0
75
5.0 mA
150
Dropout Voltage vs
Junction Temperature
> 0.20
!;
!;
I~m """"-
I
0
PC09390F
PC09400F
"~
~~~,~~
0.5
9JC
50
l-
~""'t-~ l""I...... ~ 1""-"
'n
r--- '\ l\
AMBIENT TEMPERATURE-"C
AMBIENT TEMPERATURE-GC
r-...
I
I...... ~tr-..
L '-::--. t
0.
.00
Peak Output Current vs
Input/Output Voltage Differential
f-
= 5.0C/W
o.2 r-- 'JA = "'C/W
1
PDMAX = 15Wf
75
50
-0_-
.0
II:
I-- 8JC - 5.S"CJW
I--- 8JA = 45·C/W
Po MAX = 15Wr
25
1 UMIT FOR ~A79OOC
50
40
30
20 INFINITE HEAT SINK
i 3:8
3.0 I:;;:
1---"0 "eA.r SINK
2.0
II:
Worst Case Power Dissipation vs
Ambient Temperature (TO-220)
...
__
......
r
cw~
/O~7.0A
~
c-
~
~~
'0",
...... ~~"
'o",~ ...... ........
"'-4
DROPOUT CONDInONsL
",5%IFVi
- 75 -50 -25
0
25
50
V~= -"5 V
L
,../
IE '.0
l'J
f3
ii
~
'.5
I'
Vo = -5.0 V
0.5
t"...
75 100 125 150 175
JUNCTION TEMPERATURE_oC
6-142
~
2.0
0
o
~
w
~
~
~
INPUT VOLTAGE-V
30
~
40
1lA7900 Series
Typical Performance Curves (Cont.)
Quiescent Current vs
Temperature
'00
VO~5.0IV_
Vo=
r-;.;
-'2 V AND ~,s
r---
..........
'00
I II
v,1
10 = 500mA
~
Ripple Rejection vs
Output Voltages
Ripple Rejection vs
Frequency
r-UL\UJUL
i'I~li
~
t- f0-
1111
r-
Vo
"-Hd~:t.t.!'lS:
= -5.0 V AND -8.0 Y
-
ii ·.
'
,,
.......
-lVa
80
"
= 5.0 V AND -8.0 V - r-.
AY, =10Vp _ p
200mA
-76 -150 -2S 0
TJ
o
2S 150 75 '00 '26'SO '76
r
~
10
>
0
~
~
I
I
IN VOLTAGE
4.0
20
,.
> a.o
~
~
I
OUT VOLTAGE
DeVIATION
10
10K
'OOK
I!i
2.0
'.0
I
OUT VOLTAGE
"
.
E
~
w
a:
a:
w
a:
a:
-'.00
DEVIAnON
~
18
20
22
24
10 = 100mA
Yo= -5.0 V
'0'
~
0
1.0
~
16
TJ'" 25"C
LOAD CURRENT
2.0
14
Output Impedance vs
Frequency
I I I I
I I I I
V, = 'OV
Vo=5.0V
12
NOMINAL OUTPuT VOLTAGE-V
~
10'
Co'" 1.o,."F
SOUOTANTALUll
G
Q
V
-2.0
Co = 25#'F
ALUIIINUIl
9 110"1
0-1.0
=500mA
Vo=5.DV
-ao
4.0 8.0 8.0 10
Load Transient Response
Ii
0-1 0
1.oK
FREQUENCY-Hz
Line Transient Response
.
= 200mA
o
100
AMBIENT TEMPERATURE-"C
= '20 Hz
r'o
10
=250C
10
r.1.
20 I-TJ = 25"C
AV, =10Vp _ p
1-10 =
11.3
-
-3.0
02.04.01.08.01012
nllE-~
-2.G
o
10
20
30
40
50
10-2
60
10
100
1.oK 10K 100K 1.0M 10M
FREQUENCY-Hz
nME-""
Design Considerations
The !!A7900 fixed voltage regulator series has thermal
overload protection from excessive power dissipation, internal short circuit protection which limits the circuit's maximum current, and output transistor safe-area compensation
for reducing the output current as the voltage across the
pass transistor is increased.
Typ
8JC
Max
8JC
Typ
8JA
Max
8JA
·C/W
·C/W
·C/W
·C/W
TO-3
3.5
5.5
40
35
TO-220
3.0
5.0
60
40
Package
TJ MaxTA
or - - 8JC + 8CA
8JA
8CA = 8cs + 8SA (Without heat sink)
Although the internal power dissipation is limited, the junction temperature must be kept below the maximum specified temperature (150·C for !!A7900, 125·C for !!A7900C)
in order to meet data sheet specifications. To calculate
the maximum junction temperature or heat sink required,
the following thermal resistance values should be used:
Po Max =
TJ Max-TA
Solving for TJ:
TJ = TA + Po (8JC + 8cAl or
= TA + P08JA (Without heat sink)
6-143
100M
p.A7900 Series
Where:
= Junction Temperature
TJ
TA = Ambient Temperature
= Power Dissipation
Po
8JA = Junction-to-Ambient Thermal Resistance
8JC = Junction-to-Case Thermal Resistance
8CA = Case-to-Ambient Thermal Resistance
8cs = Case-to-Heat Sink Thermal Resistance
8sA = Heat Sink-ta-Ambient Thermal Resistance
Output Current HIGH, Foldback Current-Limited
V,__.--.,....w......--+"\.
~------.--Vo
l.o"F
CF".",,.
Typical Applications
Bypass capacitors are necessary for stable operation of
the p.A7900 series of regulators over the input voltage and
output current ranges. Output bypass capacitors will improve the transient response of the regulator.
The bypass capacitors, (2.0 IlF on the input, 1.0 IlF on
the output) should be ceramic or solid tantalum which
have good high frequency characteristics. If aluminum electrolytics are used, their values should be 10 !IF or larger.
The bypass capaCitors should be mounted with the shortest leads, and if possible, directly across the regulator terminals.
Fixed Output Regulator
v, -__.-"--1
Output Current HIGH, Short Circuit Protected
r=~~---~-Vo
RSC
= VSE(Q2)
los
Operational Amplifier Supply (± 15 V at 1.0 A)
t-:--.,.------1P"------- ~~~ V
~~--Vo
1.0,..F
GND----.,....+---~~~----~__.--~~------GND
lN40010R
EQUIVALENT
CA03711lF
t=-----+------<~--- ~~ V
High Current Voltage Regulator
V,--t--"\.
~~'-------__'--Vo
6-144
IlA 101A ellA201A ellA301A
General Purpose
Operational Amplifiers
I=AIRCHILO
A Schlumberger Company
Linear Division Operational Amplifiers
Description
Connection Diagram
8-Lead Metal Package
(Top View)
The j.lA101A, j.LA201A, and j.lA301A are general purpose
monolithic operational amplifiers constructed using the
Fairchild Planar Epitaxial process. These integrated circuits
are intended for applications requiring low input offset voltage or low input offset current. The accuracy of long interval integrators, timers, and sample-and-hold circuits is
improved due to the low drift and low bias currents of the
j.lA 101 A, j.LA201 A, or j.LA301 A. Frequency response may be
matched to the individual circuit need with one external
capacitor. The absence of latch up coupled with internal
short circuit protection make the j.lA 101 A, j.LA201 A and
j.LA301 A virtually foolproof.
FREQ
COMP
v•
•
•
•
e
Low Offset Current And Voltage
Low Offset Current Drift
Low Bias Current
Short Circuit Protected
Low Power Consumption
Lead 4 connected to case.
Order Information
Device Code
j.lA101AHM
j.LA201 AHV
j.LA301 AHC
Absolute Maximum Ratings
Storage Temperature Range
Metal Can
Molded DIP and 50-8
Operating Temperature Range
Extended (j.lA101AM)
Industrial (j.lA201 AV)
Commercial (j.LA301AC)
Lead Temperature
Metal Can (soldering, 60 s)
Molded DIP and 50-8
(soldering, 10 s)
Internal Power Dissipation 1, 2
8L-Metal Can
8L-Molded DIP
50-8
Supply Voltage
j.LA 101 A, j.LA201 A
j.lA301A
Differential Input Voltage
Input Voltage3
Output Short Circuit Duration4
-65°C to + 175°C
-65°C to + 150°C
Package Code
5W
5W
5W
Package Description
Metal
Metal
Metal
Connection Diagram
8-Lead DIP and SO-8 Package
(Top View)
-55°C to + 125°C
-25°C to +85°C
O°C to +70°C
FREQ
300°C
- OFFSET NULL/
FREQCOMP
265°C
-IN
v+
+IN
OUT
1.00 W
0.93 W
0.81 W
COMP
+ OFFSET
NULL
v-
±22 V
± 18 V
±30 V
± 15 V
Indefinite
Order Information
Device Code
j.LA301ASC
j.lA301ATC
Notes
1. TJ Max = 150·C for the Molded DIP and SO·8, and 175·C for the Metal
Can.
2. Ratings apply to ambient temperature at 25·C. Above this temperature,
derate the 8L·Metal Can at 6.7 mWrC. the 8L-Molded DIP at
7.5 mwrc and the SO-8 at 6.5 mW/·C.
3. For supply voltage less than ± 15 V. the absolute maximum input
voltage is equal to the supply voltage.
4. Short circuit may be ground or either supply. pA 101 A and pA201 A
ratings apply to + 125°C case temperature or + 75°C ambient
temperature. pA301A ratings apply for case temperatures to 70·C.
7-3
Package Code
KC
9T
Package Description
Molded Surface Mount
Molded DIP
JlA 101A· JlA201A· JlA301A
Equivalent Circuit
-OFFSET
NULL!
FREQ COMP
FREQ
COMP
r---------~------~--r_--;_------~--------------~----v+
R11
25 fl
'----f--......-OUT
~--~~~~~--~~------------~------
__________-4__~__~_____~
R4
2SOfl
+ OFFSET NULL
7-4
J-lA 101A· J-lA201A· J-lA301A
J.lA101A, J.lA201A and J.lA301A
Electrical Characteristics T A = 25°C, ± 5.0 V « Vee « ± 20 V for the J.LA 101 A and J.LA201 A,
±5.0 V«Vcc«±15 V for the J.LA301A, unless otherwise specified.
J.lA 101A, J.lA201A
Symbol
Characteristic
Condition
Min
Typ
Max
J.lA301A
Min
Typ
Max
Unit
VIO
Input Offset Voltage
0.7
2.0
2.0
7.5
mV
110
Input Offset Current
1.5
10
3.0
50
nA
liS
Input Bias Current
30
75
70
250
nA
ZI
Input Impedance
Icc
Supply Current
Rs <50 k.l1
1.5
0.5
4.0
1.8
Vcc=±20 V
Large Signal Voltage Gain
Vcc=±15 V,
Vo =±10 V, RL>2.0 k.l1
50
M.I1
rnA
1.8
VCC=±15V
Avs
2.0
3.0
160
25
3.0
V/mV
160
The following specifications apply over the range of -55°C2.0 k.l1
25
VOP
Output Voltage Swing
VCC=±15V IRL=10k.l1
±12
±14
±12
±14
I RL = 2.0 k.l1
±10
±13
±10
±13
Vcc=±20 V
10
30
±12
Vcc=±15V
7-5
96
70
96
15
dB
V/mV
V
MA 101A • MA201A • MA301A
Typical Performance Curves
Input Voltage Range vs
Supply Voltage (1lA101A and 201A)
zo
Output Swing vs
Supply Voltage (1lA101A and 201A)
20
-55·C:Si TA:S 125°C
8
21-t--
8/
V
~~v/
+.\~
;t>'f';'
O·C
S
Voltage Gain vs
Supply Voltage (1lA301A)
100
8
......
V
./
~t."""
, ~.
/1
5
1/
5
.......
:;...
~
_\Io'j'l!'
78
0
1.
70
••
10
SUPPLYYOLTAGE- ±V
SUPPLVVOLTAQE- ;t;Y
180
I
'20
~-+--~ ~~~-+~~~1'5Q
I
80
~
80
r--+---r--t-~~~~+-~80 ~
g
r-+--r~~~~~~'5
~
i
1\
GAIN
20
0
f-
r\
Vcc=±15V
TA : 25°C
C1-30pF
C2 "" 300 pF
-20
1
FREQUENCY - Hz
TA = 25°C
I\..
•
i'\.PH~E
r"\ N-
40
i5
~
'\ ~ 1\ 1/
Vcc=±15V
f-- r.....
225
I
~
10
100
1.0K
10K
7-6
/
~~
GAIIN>-
~
~
100K1.0M 10M
FREQUENCY - Hz
.5
Open Loop Frequency Response
(1lA101A, 201A, and 301A)
TWO POLE
PHASE
~
SUPPLYVOLTAGE- ::tV
'20
,'00
-
.0
5
Open Loop Frequency Response
(1lA101A, 201A, and 301A)
Open Loop Frequency Response
(1lA101A, 201A, and 301A)
~,~010
-
oIo~>-Il
~010"'~~
./
~
10
......
~010"'~
~ 1/ V
0
............
o
O·C::s lAS 70·e
lAS; 70·e
...... ~
......
20
15
10
SUPPLYVOLTAOE- ±V
94
..,-
~
5
Output Swing vs
Supply Voltage (1lA301A)
zo
~ 18
~ 12
70
20
SUPPLYVOLTAGE- ::tV
w
V
./
g
15
O·C:5 TA:5 70°C
~
"'~'*'
~'<;;-
III
78
10
Input Voltage Range vs
Supply Voltage (1lA301A)
zo
88
;:'!82
0
zo
15
SUPPLYVOLTAOE- ,±y
!E
I
~
5~
10
94
z
I---
V~);··#
0
~
."
./
5
·v ""
g~
-SSoc S TA:$ 125°C
-66°C:5 TA:5 125°e
--
V
Voltage Gain vs Supply Voltage
(1lA101A and 201A)
0
FEE~ FOR~ARD
-20
10
100
loOK
10K
"
lOOK 1.0M
FREQUENCY - Hz
180
..t::
.35
Q
90
~
~
I
·si
10M 100M
MA101A· MA201A· MA301A
Typical Performance Curves for 1lA101A, 1lA201A, and 1lA301A (Cent.)
Large Signal Frequency Response
Large Signal Frequency Response
TA
12
I
"~
>
8
~
1\
C, • 30 F\
o
1.0K
it
III
i'. . . . .
100 K
1.0 M
> 12
I
"itz
~
TWO POLE
---
o
FREQUENCY -
FEED FORWARD
......
100 K,
10K
FREQUENCY - Hz
1\
8
S
1\
10M
1\
~
III
I
SINGLE POLE
...... 110K
8
TA ::: 25"C
\
\
\
I
\
S
o
12
!i
C1=3OpF
C2 = 300 pF
1\
+I
\C1 =3pF
!
veJ =I~I,~ Iv
TA :::; 25°C
= 25°C
\
+1
18
VCC=:t1SV
vcl.I±ljJv
>
Large Signal Frequency Response
18
18
1.0 M
o
r-_
10M
1.0 M
100 K
Hz
FREQUENCY -
Hz
PC04391F
Voltage Follower Pulse Response
Voltage Follower Pulse Response
Voltage Follower Pulse Response
0
10
10
OUTPUT
r-
>
I
!i
~w
i\
2
N /
"; -2
I
~ -4
I
\
j--
-6
!I
-
>
I
!w
OUTPUT
,..--
!\
1\
0
IIINPUT
~
~ -4
I
-8
-8
-10
-10
o ro
~
30
~
TIME
M
H
ro
=
1
I
...6
!i1.5
w
FEED FORWARD
~
~
~
~
~
~
--- --
TA =
30
~
T~'-$~
~
:---
iil
0.5
-
......,..yA = 25°C
TA
-
'\
~
5
-- 1\
vee ='
'"
20
15
SUPPLY VOLTAGE -
7-7
±15V
~
>'
>'
tl
(;
cl
10
~
>'
~-
~- rei
"
= 125"C
80
15
SUPPLYVOLTAGE- ±V
ro
H
Current Limiting
;:-.......:
V
~
V _
TIME- #oil
Jssoc
~
10
~
15
r;r: 25"C
5
o ro
~
#oil
Voltage Gain vs Supply Voltage
1---"""1
~~C:::; =2io~5
-8
120
~ 1.0
o
10
TIME -
2.5
2.0
r
-10
-.us
Supply Voltage Current vs
Supply Voltage
I
Vcc=±15V
TA 25"C
C1 =3OpF
- ..,
o
I
TWOPOLE
300
j=l
~
INPUT
OUTPUT
I
I
SINGLE POLE
-8
- - IT- t
H
I \
~ -2
I
\
-
~
IA.
I
0
- r- I-
r
INPUT
±V
o
o
15
20
10
OUTPUT CURRENT - mA
cl
25
30
p.A101A· p.A201A· p.A301A
Typical Performance Curves for
Input Current vs Temperature
and ~201A)
~101A, ~201A,
(~301A
50
00
BlM' r-.
80
l"- t--....
t-- r
to--
B1AS
r- r-
'"
20
...
•
.
0
.......
8
r-....
OFFSET
.~
l - I-.
TA·25·C
r-r-
OFFSET
2
25
0
25
50
75
100
•10
10-'
0
-to
"
....
8
1
0
-75
•
........
!?>2
Input Noise Voltage vs Frequency
80
10
3
(Cent.)
Input Current vs Temperature
only)
(~101A
0
~301A
and
20
125
80
40
80
TEMPERATURE - ·C
1.oK
100
100K
10K
FREQUENCY - Hz
TEMPERATURE. _ °C
PCQ4481F
Input Noise Current vs Frequency
(~101A and ~201A)
Input Noise Current vs Frequency
(~301A)
Common Mode Rejection vs
Frequency
120
10-24
Rs.lldl
TA =25°C
~
"
1'\
I"
[\
t-100
10k
1.Ok
100k
10-26
10
FREQUENCY -
-~
I'"
,
0
Avs
,
/
2
10
100
1.0 K
10 K
FREQUENCY -
100 K 1.0 M
Hz
10M
Avs - 1000
/'
'-./
10-3
=1
/
I'--'"
10
100
,,/
/
SINGLE POLE
COMPENSATION
~~ ~~Jt
IOi+ 5mA
1.0 K
10 K
FREQUENCY -
7-8
Hz
100
1.0 K
-
I
100 K
1.0 M
r
VCMS±1V
10 K
FREQUENCY - Hz
Hz
Closed Loop Output Impedance
vs Frequency
Supply Rejection vs Frequency
100
100K
10K
1.OK
100
FREQUENCY - Hz
20
10
"
~±10V
100 K
1.0 M
pA101A· pA201A· pA301A
Compensation Circuits (Note 2)
Typical Applications (Note 2)
Single Pole Compensation
Fast Voltage Follower
R2
Vo
V,
Power Bandwidth: 15 kHz
Slew Rate: 1 VI P.s
Inverting Amplifier With Balancing Circuit
Rl
R2
IN--~~~----~V-----~
Two Pole Compensation
R2
>::...........---OUT
Rl
R4
5.1 Mn
-V,--~V-""":..j
>""-'.....--
R3
Vo
Cl
30 pF
Voltage Comparator For Driving Or DTL Integrated
Circuits
R,C
s
c,>----
IN
R, + R2
Cs
~
OUT
30 pF
C2~10
C,
Feed Forward Compensation
C2
Notes
1. May be zero or equal to parallel combination of Rl and R2 for
minimum offset.
2. All lead numbers shown refer to 8-lead metal package.
R2
Rl
V,---'V'.",....-----t
Vo
R3
C,
150 pF
7-9
p.A 101A· p.A201A· p.A301A
Typical Applications (Cont.) (Note 2)
Low Frequency Square Wave Generator
Practical Differentiator
Rl
C2
lMe
R2
,-__+ ___
(Note 1)
~~~
IMPEDANCE
Cl
>'-'-JVW.,...."'-t-- g~MPED
D1,6.2V
D2,6.2V
Circuit For Operating Without A Negative Supply
R1
R2
1
1
I
v,
----,------,r
'...!'-----4-R3
Notes
I. Adjust C, for frequency
2. All lead numbers shown refer to 8-lead metal package
7-10
fh
~ 21TRI CI
fc
< fh < funity
1
- 21TR2C2
gain
}.LA 101 • }.LA20 1
General Purpose
Operational Amplifiers
FAIRCHILD
A Schlumberger Company
Linear Division Operational Amplifiers
Description
Connection Diagram
8-Lead Metal Package
(Top View)
The IlA101 and IlA201 are general purpose monolithic operational amplifiers constructed using the Fairchild Planar
Epitaxial process. They are intended for a wide range of
analog applications where tailoring of frequency characteristics is desirable. The IlA101 and IlA201 compensate
easily with a single external component. High common
mode voltage range and absence of latch up make the
IlA 101 and IlA201 ideal for use as voltage followers. The
high gain and wide range of operating voltages provide
superior performance in integrator, summing amplifier, and
general feedback applications. The IlA 101 and 1lA201 are
short circuit protected and have the same lead configuration as the popular 1lA741 , IlA748 and IlA709.
FREQ
COMP
v-
• Short Circuit Protection
• Offset Voltage Null Capability
• Large Common Mode And Differential Voltage
Ranges
• Low Power Consumption
• No Latch Up
Lead 4 connected to case.
Order Information
Device Code
Absolute Maximum Ratings
Storage Temperature Range
Metal Can
Molded DIP
Operating Temperature Range I
Extended (IlA 101 M)
Commercial (IlA201 C)
Lead Temperature
Metal Can (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 2, 3
8L-Metal Can
8L-Molded DIP
Supply Voltage
Differential Input Voltage
Input Voltage4
5W
5W
Package Description
Metal
Metal
Connection Diagram
8-Lead DIP
(Top View)
-65°C to + 175°C
-65°C to + 150°C
-55°C to + 125°C
O°C to +70°C
FREQ
COMP
- OFFSET NULL!
FREQCOMP
v+
-IN
300°C
265°C
1.00
0.93
±22
±30
± 15
Package Code
1lA101HM
1lA201HC
OUT
+IN
W
W
V
+ OFFSET
v-
NULL
V
V
Order Information
Device Code
Notes
I. Short circuit may be to ground or either supply. The IlA 101 ratings
apply to + 125·C case temperature or + 75·C ambient temperature. The
1lA201 ratings apply to case temperatures up to + 70·C.
2. TJ Max ~ 150·C for the Molded OIP, and 175·C for the Metal Can.
3. Ratings apply to ambient temperature at 25·C. Above this temperature,
derate the BL·Metal Can at 6.7 mW rc, and the BL-Molded DIP at
7.5 mWrC.
4. For supply voltages less than ± 15 V, the absolute maximum input
voltage is equal to the supply voltage.
1lA201TC
7-11
Package Code
9T
Package Description
Molded DIP
Equivalent Circuit
-OFFSET
NULL!
FREQ COMP
FREQ
COMP
r----------1--------.--+----+-------~--------------~------v+
-IN
--+---------Ir-------I..'
+ IN
--+------1:'
Rl1
25
n
~__1f_--OUT
R8
1kn
L-~~~---+--__~~----__----~----------------~--~--~---vR4
250 n
+ OFFSET NULL
7-12
IlA101 ellA201
MA101 and MA201
Electrical Characteristics TA = 25°C, ±5.0 V2.0
50
kn
The following specifications apply over the range of -55°C < TA <
160
20
3.0
V/mV
150
+ 125°C for /.IA 101, and O°C < TA < + 70°C for /.IA201.
kn
n
kn
VIO
Input Offset Voltage
Rs<50
!:Nlo/AT
Input Offset Voltage
Temperature Sensitivity
Rs<50
110
Input Offset Current
TA=TA Min
10
200
50
400
TA=TAMax
100
500
150
750
AIIO/ AT
Input Offset Current
Temperature Sensitivity
liB
Input Bias Current
Rs<50
6.0
10
3.0
10.0
25°C < T A < T A Max
0.01
0.1
0.01
0.3
TA Min 2.0 kn
VoP
Output Voltage Swing
Vee=±15 V
kn
70
90
±12
kn
70
I RL =10 kn
I RL = 2.0 kn
7-13
25
nA
nA/oC
/.IA
mA
65
90
dB
90
dB
±12
90
mV
/.IV/oC
6.0
6.0
Supply Current
nA
kn
400
3.0
Vee=±15V
Avs
Typ
70
V
15
V/mV
±12
±14
±12
±14
±10
±13
±10
±13
V
/lA 1081A • /lA2081 A • /lA3081 A
Super Beta
Operational Amplifiers
FAIRCHILD
A Schlumberger Company
Linear Division Operational Amplifiers
Description
Connection Diagram
8-Lead Metal Package
(Top View)
The p.A 108 Super Beta Operational Amplifier series is constructed using the Fairchild Planar Epitaxial process. High
input impedance, low noise, low input offsets, and low
temperature drifts are made possible through use of super
beta processing, making the device suitable for applications requiring high accuracy and low drift performance.
The pA 108 series is specially selected for extremely low
offset voltage and drift, and high common mode rejection,
giving superior performance in applications where offset
nulling is undesirable. Increased slew rate without performance compromise is available through use of feed forward compensation techniques, maximizing performance in
high speed sample-and-hold circuits and precision high
speed summing amplifiers. The wide supply range and excellent supply voltage rejection assure maximum flexibility
in voltage follower, summing, and general feedback applications.
•
•
•
•
•
FREQ
COMP2
vLead 4 connected to case.
Order Information
Device Code
/JA108HM
pA108AHM
pA208HV
pA208AHV
pA308HC
pA308AHC
Guaranteed Low Input Offset Characteristics
High Input Impedance
Low Offset Current
Low Bias Current
Operation Over Wide Supply Range
Absolute Maximum Ratings
Storage Temperature Range
Metal Can
Molded DIP and SO-8
Operating Temperature Range
Extended (pA 108AM, pA 108M)
Industrial (pA208AV, pA108V)
Commercial (pA308AC, pA308C)
Lead Temperature
Metal Can (soldering, 60 s)
Molded DIP and SO-8
(soldering, 10 s)
Internal Power Dissipation 1. 2
8L-Metal Can
8L-Molded DIP
SO-8
Supply Voltage
pA 1081 A, pA2081 A
pA308/A
Differential Input Current 3
Input Voltage4
Output Short Circuit DurationS
-65°C to + 175°C
-65°C to + 150°C
Package Code
5W
5W
5W
5W
5W
5W
Package Description
Metal
Metal
Metal
Metal
Metal
Metal
Connection Diagram
8-Lead DIP and SO-8 Package
(Top View)
-55°C to +125°C
-25°C to + 85°C
O°C to +70°C
8
FREQ
CQMPI
300°C
265°C
1.00 W
0.93 W
0.81 W
±20 V
±18 V
±10 mA
±15 V
Indefinite
FREQ
CQMP2
-IN
v+
+IN
OUT
v-
NC
Order Information
Device Code
pA308SC
/JA308TC
pA308ASG
pA308ATG
Notes
1. TJ Max -150'C for the Molded DIP and SO-B, and 175'C for the Metal
Can.
2. Ratings apply to ambient temperature at 25°C. Above this temperature.
derate the BL-Metal Can at 6.7 mWI'C. the BL-Molded DIP at
7.5 mWI'C. and the SO-B at 6.5 mWI'C.
3. The inputs are shunted with back-to-back diodes for overvoltage
protection. Therefore, excessive current will flow if a differential input
voltage in excess of 1.0 V is applied between the inputs unless
adequate limiting resistance is used.
Package Code
KG
9T
KG
9T
4. For supply voltages less than
voltage is equal to the supply
5. Short circuit may be to either
operation up to the maximum
7-14
Package Description
Molded Surface Mount
Molded DIP
Molded Surface Mount
Molded DIP
± 15 V. the absolute maximum input
voltage.
supply or ground. Rating applies to
operating temperature range.
p.A 108! A • p.A208!A • p.A308! A
Equivalent Circuit
FREQ
FREO
COMP 1
COMP'
r-----------.-----i---~--~------~--~--~--------------------~----------y+
RS
20 Idl
R4
201dl
R6
101dl
R7
10 kG
r -.....-'lM---1rOUT
019
-IN
020
R13
201dl
TIN
Rl
o kG
RIO
3200
RIS
6Q kG
R17
5000
RIS
1 kn
y-
7-15
J.1A 1OSI A • J.1A20S1 A • J.1A30S1 A
pA108/A and pA208/A
Electrical Characteristics ± 5.0 V
< Vee < ± 20
V. TA = 25°C. unless otherwise specified.
IlAl08A
!lA208A
Symbol
Characteristic
Condition
Min
IlA108
IlA208
Typ
Max
Typ
Max
Unit
VIO
Input Offset Voltage
0.3
0.5
0.7
2.0
mV
110
Input Offset Current
0.05
0.2
0.05
0.2
nA
0.8
2.0
0.8
2.0
liS
Input Bias Current
ZI
Input Impedance
lee
Supply Current
Vee=±20 V
Avs
Large Signal Voltage
Gain
Vee=±15 V.
Vo=±10 V. RL>10 n
30
70
.03
80
Via
Input Offset Voltage
eNlo/AT
Input Offset Voltage
Temperature Sensitivity
110
Input Offset Current
Alia/AT
Input Offset Current
Temperature Sensitivity
liS
Input Bias Current
lee
Supply Current
CMR
Common Mode
Rejection
30
0.6
300
The following specifications apply over the range of -55°C < TA < + 125°C for the
for the pA208/ A. unless otherwise specified.
Min
0.3
50
!lA108/ A.
Vee = ±20 V. TA = 125°C
5.0
3.0
96
0.8
3.0
0.4
110
Vee=±15V
Power Supply Rejection
Ratio
Vee = ±5.0 V to ±20 V
96
Avs
Large Signal Voltage
Gain
Vee=±15 V.
Vo=±10 V. RL>10 n
40
VoP
Output Voltage Swing
Vee = ± 15 V. RL = 10 kn
< Vee < ± 15
±13
0.5
0.15
85
± 13.5
Input Voltage Range
PSRR
pA308/A
Electrical Characteristics T A = 25°C. ± 5.0 V
2.5
0.15
80
mV
15
IlV/oC
0.4
nA
2.5
pAloC
3.0
nA
0.4
mA
100
dB
96
dB
V
±13
VlmV
±14
V
V. unless otherwise specified.
Min
Condition
3.0
25
±14
mA
V/mV
±13.5
110
!lA308A
Characteristic
0.6
and -25°C < TA < + 85°C
0.4
0.5
nA
Mn
300
1.0
1.0
VIR
Symbol
70
IlA308
Typ
Max
Min
Typ
Max
Unit
Via
Input Offset Voltage
0.3
0.5
2.0
7.5
mV
110
Input Offset Current
0.2
1.0
0.2
1.0
nA
liS
Input Bias Current
1.5
7.0
1.5
7.0
ZI
Input Impedance
10
7-16
40
10
40
nA
Mn
/lA 1081 A • /lA2081 A • /lA3081 A
J.lA308! A (Cont.)
Electrical Characteristics T A = 25°C, ± 5.0 V < Vee
< ± 15
V, unless otherwise specified.
j.LA308
J.lA308A
Symbol
Characteristic
Condition
Min
Icc
Supply Current
Vee=±15V
Avs
Large Signal Voltage
Gain
Vee = ± 15 V,
Vo=±10 V, RL;;;'10
Typ
Max
0.3
0.8
80
n
300
Min
25
Typ
Max
0.3
0.8
300
Unit
mA
V/mV
The following specifications apply over the range of O°C';; TA .;; + 70°C
VIO
Input Offset Voltage
t:Nlo/toT
Input Offset Voltage
Temperature Sensitivity
110
Input Offset Current
tollo/ toT
Input Offset Current
Temperature Sensitivity
liS
Input Bias Current
CMR
Common Mode
Rejection
VIR
Input Voltage Range
Vee=±15V
PSRR
Power Supply Rejection
Ratio
Vee=±5.0 V to ±18 V
96
Avs
Large Signal Voltage
Gain
Vee=±15V,
Vo=±10 V, RL;;;'lO
60
VOP
Output Voltage Swing
Vee=±15 V,
0.73
1.0
5.0
6.0
1.5
2.0
10
2.0
10
96
110
80
mV
30
j.LV/oC
1.5
nA
10
pA/oC
10
nA
100
± 13.5
± 13.5
kn
RL=10 kn
10
110
80
V
96
15
±13
±13
±14
dB
dB
V/mV
±14
V
Typical Performance Curves for J.lA108 Series
Input Noise Voltage vs Frequency
Open Loop Frequency Response
120
1000
~
100"'"
400
~
:.;
Z
i
w 100
'"
0
z
po
~
i!<
~
Rs-l.0M
I
I
Rs
lOOK
l-
80
-
~ 60
Mi' 80
c, _ 30pF-
--,""
~
~~ol
'q;
IIJ
Cs
;.o~"
"-
40
I,
10
10
:
II
100
1.0K
FREQUENCY - Hz
20
~
o
0
PHASE ___
GAIN _ _
i
10K
g
= 100pF
...
.0",
Q,
Rs ;:;; 0
,
fi!'-I
'J-
o
40
1~r---;----r----r---;----'
I C'=13PF~
.......
~
g
Supply Rejection vs Frequency
c,
;...,
-'/
"'"" " \
'"
135 ~
~
90
4S
1
10
100
1.0 K
=
30pF~ ~.
10 K 100 K 1.0 M 10 M
FREQUENCY - Hz
7-17
~
~
-20
lOOK
I
~
-~oo~~'~~-K--~'O~K--'~OO~K---'.~O~M--'~OM
fREQUENCY - Hz
JlA 1081 A • JlA2081 A • JlA3081 A
Typical Performance Curves for J.l.A 108 Series (Cant.)
Closed Loop Output Impedance vs
Frequency
103
/
102
"I
w
~
/
100
~
10-
l000,Cf
I
Vee
TA
30pF
10- 2
1.0 K
10 K
6
>
I
~
= :t
=
Ct
::>
I
1\
~
w
= 3pF
0
15 v-
Cf=
25°C
II
o
1.0 K
g -4
10 K
!j
1/
1\
-c-'
6
~
Hz
J
/ OUTPUT
/
I
!
-2
3OP~
INPUT I
i\
0
~
\
f-
100 K 1.0 M 10M
FREQUENCY -
\
---1--
>-
"z
.5
1
100
= 25°C
TA
"z
'i· mj
...J
lD
\
12
I
'Av .1,C,. 30pF
/
,
10
I III
Vcc=±15V
~
=
=
\,'"
V I)
Av
!
,...
~
I
~ "; ~
10,
~
~
",
Voltage Follower Pulse
Response
Large Signal Frequency
Response
Ycc=±15V
TA
-8
t-
-1 0
- 20 0
1.0 M
100 K
:=
25°C
_~' .~30
20
40
60
TIME -
FREQUENCY - Hz
j
80 100 120 140 160 180
~s
Typical Performance Curves for J.l.A108/A, and J.l.A208/A (Unless otherwise specified)
Input Currents vs Temperature
!Z
~
I
w
......b-,
,0
~oa..v,
r'-!~AS ~208
.5
0.25
r-::>
~
.
!
~
~
iz
0.20
0.1 5
~
0.1 0 ........
~
v
10
1.0
~
0
-55 -35
-15
5
25
45
65
85
III
1~~J.A
105 125
111
100 K
Voltage Gain vs
Supply Voltage (pA 108)
I
110
z
"."
w
!:; 100
0
>
,...L"""
-....-
1.0 M
10M
~125'C
15
20
o
o
10M
100M
Supply Current vs
Supply Voltage (f.lA 108)
\
\
= 125°C
500
1.
I 400
f-
I T
15a:
TIA • j5'C
"
TAi-r II
iil
~300
7-18
~
100
II
OUTPUT CURRENT -
/
~200 V
5
90
1.0 M
INPUTAESISTANCE-Q
c
10
0
100 K
100M
n
2f/20rAII ~5'Ct TAl s 18f;C
600
TA
SUPPLYVOLTAGE- ±Y
lO8Jl08A: - 55°C::s TA:S 125°C
I
Vcc=±1SV
0
c
~~
,.
......
.........
\
V
5
~
-\08I:zoa
10
TA:S 125°C
2i8J2~1:u5'cl TAtlIf
~
~5OC
"t::"t·
ffi
t:
5
c. = 0
f = 100Hz
III
~
a:
Output Swing vs
Output Current (IlA 108)
120
=
<
7
V.
V
/
INPUT RESISTANCE -
TEMPERATURE - 'C
TA
",.
1081108A: - 55°C
g O.1
-..!..,0&A/10& OFFSET 20&Al208
'"
r-,081208
o
8
~
1.oK
:; 100
..
~
I
Maximum Drift Error
Maximum Offset Error
2.0
--
--
0
10
± rnA
.fA. "" I_ 55°C
Tl
=25'C
TA
1~'C
=
15
SUPPLY VOLTAGE- ±V
20
IlA 1081A • p.A2081A • p.A3081A
Typical Performance Curves for IlA3081 A (Unless otherwise specified)
Input Current vs Temperature
> 1000
E
3
2r-1
T;
I
-
~
i
BIAS
"'r--
>
.........
,..l!EF~
0.1 6
Ii
i!E
100
V
/
10 -MAXIMUM
10
30
20
40
60
TEMPERATURE -
80
10
80
120
110
z
>
,/
100
UlM
10M
100M
INPUT RESISTANCE - 0
Supply Current vs Supply Voltage
Output Swing vs Output Current
16
>
7
~.~26°:"~.C
10
I
TA = 70°C
V
V
T!T= ~oc
-r
V
I
400
vcc l- ±\sv
....... .......
1"'=SO·~
--
I II
INPUT RESISTANCE - 0
C, =0
f = 100Hz
...
:c
1.0
100 K
·C
Voltage Gain vs Supply Voltage
~
i-'
-~YPICAL
"wi
0
"w
V
/
r--
0.1 0
I
=IJJc_
w
0
........
Maximum Drift Error (!lA308)
Maximum Offset Error (!lA308)
4
~
350
~
\
.." ~
'"
...... ~
-
T.
_!.c.1
TA=ioc
T.
7O°C
/'
t-= toc
60
90
20
16
10
5
SUPPLY VOLTAGE - ±
v
o
o
o
6
OUTPUT CURRENT -
Standard Compensation Circuits
R2
R2
Rl
Rl
-IN -""''''"""........
-IN-OM"......H
OUT
R3
+IN -""''''"""--I
R3
+IN
c, (NOTE 1)
Note
1. CF ;;>30 (
1 +1
~
)
7-19
-w\,---I
10
15
SUPPLY VOLTAGE-
± mA
OUT
20
"v
J.l.A 1081A • J.l.A2081 A • J.l.A3081 A
Feed Forward Compensation
Higher Slew Rate and
Wider Bandwidth
Guarding
Extra care must be taken in the assembly of printed circuit boards to take full advantage of the low input currents of the p.A 108 amplifier. Boards must be thoroughly
cleaned with TCE or alcohol and blown dry with compressed air. After cleaning, the boards should be coated
with epoxy or silicone rubber to prevent contamination.
Even with properly cleaned and coated boards, leakage
currents may cause trouble at 125°C, particularly since the
input leads are adjacent to leads that are at supply potentials. This leakage can be significantly reduced by using
guarding to lower the voltage difference between the inputs and adjacent metal runs. Input guarding of the 8-lead
TO-99 package is accomplished by using a 10-lead circle,
with the leads of the device formed so that the holes
adjacent to the inputs are empty when it is inserted in the
board. The guard, which is a conductive ring surrounding
the inputs, is connected to a low impedance point that is
at approximately the same voltage as the inputs. Leakage
currents from high voltage leads are then absorbed by the
guard.
The lead configuration of the dual-in-line package is designed to facilitate guarding, since the leads adjacent to
the inputs are not used (this is different from the standard
1-/A741 and p.A101A lead configuration).
Standard Feed Forward
C2
RI
5pF
10 Idl
IN .....W\'"""""~--It~-....,
OUT
Open Loop Frequency Response
..
z
..3
120
I
~
"
~
-.....
"'
100
80
"-
40
9
20
0
z
r0
"- '\
-
80
.
I
,
I
FEE~ FOR~ARD CO},PENSATION /
I
."
'\
,
STANDARD'
r-COMPENSATION
"
'\V
I
10
100
-{HASE
)."'"
\..
""
I
I
-20
I 80
\..GAlN
"' I'\..
1""-..'0
1.0 K 10 K 100 K 1.0 M 10 M
FREQUENCY - Hz
Feed Forward Compensation for Decoupling Load Capacitance
R2
Rs> 101cO
lOOIdl
IN~~~-1~--~~-~~---~
10pFI-Ij
>'......
......-OUT
~~_
Note
'------4-----+
CL
75 pF
to O.OI.F
CR01201F
7-20
p.A 1081 A • p.A2081 A • p.A3081 A
Inverting Amplifier
Rl
Board Layout for Input Guarding
With Metal Package
R2
IN--~~1-------~~--------'
COMPENSATION
OUT
R - R,IIR 2 (muol be low impedance)
Follower
BOTTOM VIEW
CA01240F
OUT
IN
----*r---I
Non-Inverting Amplifier
R2
OUT
Nole
1. Use to compensate for large source resistances.
7-21
JiA 124 • JiA224 • JiA324 • JiA2902
Quad
Operational Amplifiers
FAIRCHILD
A Schlumberger Company
Linear Division Operational Amplifiers
Description
Connection Diagram
14-Lead DIP and 50-14 Package
(Top View)
The /1A 124 series of quad operational amplifiers consists
of four independent high gain, internally frequency compensated operational amplifiers designed to operate from a
single power supply or dual power supplies over a wide
range of voltages. The common mode input range includes
the negative supply, thereby eliminating the necessity for
external biasing components in many applications. The output voltage range also includes the negative power supply
voltage. They are constructed using the Fairchild Planar
Epitaxial process.
OUT A
-IN A
-IN D
+IN A
+IN 0
y+
• Input Common Mode Voltage Range Includes Ground
Or Negative Supply
• Output Voltage Can Swing To Ground Or Negative
Supply
• Four Internally Compensated Operational Amplifiers
In A Single Package
• Wide Power Supply Range; Single Supply Of 3.0 V
to 30 V, Dual Supply of ± 1.5 V to ± 16 V
• Power Drain Suitable For Battery Operation
y- OR GND
+IN B
+IN C
-IN B
-IN C
OUT C
OUT B
Order Information
Device Code
/1A124DM
/1A224DV
/1A224PV
/1A324DC
/1A324PC
/1A324SC
/1A2902PV
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
-65°C to + 175°C
Molded DIP and SO-14
-65°C to +150°C
Operating Temperature Range
Extended (/1A 124M)
-55°C to +125°C
Automotive (/1A2902V)
-40°C to +85°C
Industrial (/1A224V)
-25°C to + 85°C
Commercial (/1A324C)
O°C to +70°C
Lead Temperature
Ceramic DIP (soldering, 60 s)
300°C
Molded DIP and SO-14
(soldering, 10 s)
265°C
Internal Power Dissipation 1, 2
14L-Ceramic DIP
1.36 W
14L-Molded DIP
1.04 W
SO-14
0.93 W
Supply Voltage Between V + and V- 32 V
Differential Input Voltage 3
32 V
Input Voltage3
-0.3 V
(V-) to V+
Notes
1. TJ Max ~ 150·C for the Molded DIP and 80-14, and 175·C for the
Ceramic DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature
derate the 14L-Ceramic DIP at 9.1 mWrC, the 14L-Molded DIP at
8.3 mWrC, and the 80-14 at 7.5 mWrC.
3. The input common mode voltage or either input signal voltage should
not be allowed to go negative by more than 0.3 V. The upper end of
the common mode voltage range is Vee -1.5 V, but either or both
inputs can go to + 32 V without damage (+ 26 V for iJA2902).
4. Short circuits from the output to Vee can cause excessive heating and
eventual destruction. Destructive disSipation can result from simultaneous
shorts on all amplifiers.
7-22
Package Code
6A
6A
9A
6A
9A
KD
9A
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
Ceramic DIP
Molded DIP
Molded Surface Mount
Molded DIP
IlA 124 • IlA224 • IlA324 • IlA2902
Equivalent Circuit (1/4 of Circuit)
-IN
+IN
OUT
v+
BIAS COMMON TO
ALL FOUR CHANNELS
,.-- - ------ - - ------ ------
v- orGND
EQ00790F
p.A 124, p.A224 and p.A324
Electrical Characteristics T A = 25°C, V +
= 5.0
V, V -
= GND,
unless otherwise specified.
J.LA 124/A224
Symbol
Characteristic
Via
Input Offset Voltage
110
Input Offset Current
liB
Input Bias Current
Condition
Min
V + = 5.0 V to 30 V
VCM=O V to (V-)-1.5 V,
Vo",,1.4 V, Rs~50 n
CMR
Common Mode Rejection
Rs~10
kn
70
VIR
Input Voltage Range
V+ =30 V
0
PSRR
Power Supply Rejection
Ratio
los
Output Short Circuit
Current1
10+
Output Source Current
VID = 1.0 V, V + = 15 V
20
10-
Output Sink Current
VID = -1.0 V, V +
VID
= 15 V
= -1.0 V, Vo = 200 mV
V + = 15 V, RL;;' 2.0 kn
50
Avs
Large Signal Voltage
Gain
CS
Channel Separation
65
Typ
Max
Typ
Max
Unit
2.0
5.0
2.0
7.0
mV
3.0
30
5.0
50
nA
45
150
45
250
85
7-23
Min
65
28.5
100
40
1.0 kHz ~ f ~ 20 kHz,
(Input Referenced )
J-IA324
70
28.5
0
65
60
100
40
nA
dB
V
dB
60
mA
40
20
40
mA
10
20
10
20
mA
12
50
12
50
p.A
100
25
100
V/mV
-120
dB
-120
JJ.A 124 • JJ.A224 • JJ.A324 • JJ.A2902
J,LA 124, J,LA224 and J,LA324 (Cont.)
Electrical Characteristics TA = 25°C, V + = 5.0 V, V - = GND, unless otherwise specified.
iJA 1241 A224
Symbol
Characteristic
Condition
Min
I
Typ
I
iJA324
I
Min
Max
Typ
I
Max
Unit
The following specifications apply over the range of -55°C";;;TA";;;+125°C for the J..lA124; -25°C";;;TA";;;+85°C for the
iJA224; and the O°C";;; TA ,,;;; + 70°C for the J..LA324.
Via
Input Offset Voltage
LlVlolLlT
Input Offset Voltage
Temperature Sensitivity
110
Input Offset Current
LlllolLlT
Input Offset Current
Temperature Sensitivity
10
liB
Input Bias Current
40
Icc
Supply Current
V + = 5.0 V to 30 V,
VCM = 0 V to V - = 2.0 V,
Vo :::C1.4 V, Rs";;;50 il
7.0
9.0
7.0
7.0
100
Va = 0 V, RL =
00
V + = 30 V, Va = 0 V,
RL = 00
J..lVrC
150
10
nA
pArC
500
nA
0.7
1.2
mA
1.5
3.0
300
50
0.7
1.2
1.5
3.0
28
mV
VIR
Input Voltage Range
V+ =30 V
10+
Output Source Current
Via =
+ 1.0 V, V + = 15 V
10
20
10
20
mA
10-
Output Sink Current
Vlo=-1.0 V, V+ =15 V
5.0
8.0
5.0
8.0
mA
Avs
Large Signal Voltage
Gain
V + = 15 V, RL ;<>2.0 kil
25
VOH
Output Voltage HIGH
V + = 30 V, RL = 10 kil
27
V + = 30 V, RL = 2.0 kil
26
VOL
Output Voltage LOW
V+ =5.0 V, RL=10 kil
0
28
0
15
28
V
V/mV
27
28
V
26
5.0
20
5.0
20
mV
J.LA2902
Electrical Characteristics TA = 25°C, V + = 5.0 V, V - = GND, unless otherwise specified.
Symbol
Characteristic
Via
Input Offset Voltage
110
Input Offset Current
Condition
Min
V + = 5.0 V to 26 V,
VCM = 0 V to (V-) -1.5 V,
Vo::::'1.4 V, Rs";;;50 il
liB
Input Bias Current
CMR
Common Mode Rejection
Rs";;; 10 kil
50
VIR
Input Voltage Range
Vcc= 26 V
0
PSRR
Power Supply Rejection Ratio
los
Output Short Circuit Current 1
50
Typ
Max
Unit
2.0
7.0
mV
5.0
50
nA
45
250
70
24.5
100
40
7·24
nA
dB
V
dB
60
mA
JlA 124 • JlA224 • JlA324 • JlA2902
J1A2902 (Cont.)
Electrical Characteristics T A = 25°C, V + = 5.0 V, V - = GND, unless otherwise specified.
Symbol
10+
Characteristic
Output Source Current
Condition
Min
VID = + 1.0 V, V + = 15 V
20
Typ
Max
Unit
40
rnA
= 15
10-
Output Sink Current
VID=-1.0 V, V+
V
10
20
rnA
Avs
Large Signal Voltage Gain
V+ =15 V, RL;;;'2.0 kn
15
100
V/mV
CS
Channel Separation
1.0 kHz < f < 20 kHz,
Input Referenced
-120
dB
The following specifications apply over the operating temperature range of -40°C < TA < + 85°C
V + = 5.0 V to 26 V,
VCM = 0 V to V - = 2.0 V,
Vo""-1.4 V, Rs<50 n
VIO
Input Offset Voltage
10
LlVlol LlT
Input Offset Voltage
Temperature Sensitivity
7.0
110
Input Offset Current
45
Lliiol LlT
Input Offset Current
Temperature Sensitivity
mV
p.V/oC
200
nA
pA/oC
10
liB
Input Bias Current
Icc
Supply Current
Vo = 0 V, RL =
VIR
Input Voltage Range
V+ =26 V
10+
Output Source Current
V ID = + 1.0 V, V + = 15 V
10
20
rnA
10-
Output Sink Current
V ID
V, V + = 15 V
5.0
8.0
rnA
Avs
Large Signal Voltage Gain
V+ = 15 V, RL;;;' 2.0 kn
15
100
V/mV
VOH
Output Voltage HIGH
= 2.0 kn
= 10 kn
RL = 10 kn
22
V+
Output Voltage LOW
= -1.0
V, Vo = 0 V, RL
= 26
V, RL
V+ = 5.0 V,
= 00
50
500
nA
0.7
1.2
rnA
1.5
3.0
rnA
24
V
0
V + = 26 V, RL
V+
VOL
= 26
00
Notes
1. Short circuits from the output to Vee can cause excessive heating and
eventual destruction. Destructive dissipation can result from simultaneous
shorts on all amplifiers.
7-25
23
V
24
5.0
100
mV
p.A 124 • p.A224 • p.A324 • p.A2902
Typical Performance Curves
Open Loop Frequency Response
120
."
vc~='i~v
100
-fo...
I
~
80
co
"'~
...~
TA
..... ......
80
.......
t......
~
§
...iii0
= 25°C
.......
20
.......
t......
-20
10
1.0
UK
100
10K
100M
100K
FREQUENCY - Hz
Output Characteristics Current
Sourcing
,.
I
,.+
1111 I 1111 I
I.
f-
I
,.
~
,....9-
..
I
..
~
i
~
:::I
I
Tiifr
OUTPUT SOURCE CURRENT -
20
10
S
0
0
5.0
I'.r-
-5.0
10
0.1
0.01
0.1
V
1111 I
1
0.001
:::I
aoe
Rl.=10kO
15
~
!:i
>
........
TA ""'
I
0
INDEPENDENT OF V+
Vcc=±16V
1\
IS
10+
~
Output Voltage vs Frequency
30
UII
:.~~
e
I
Output Characteristics Current
Sinking
1.0 K
100
mA
Output Swing vs
Supply Voltage
OUTPUT SINK CURRENT -
Input Bias Current vs
Temperature
~
100K
1.0M
Input Bias Current vs
Supply Voltage
400
T. = 211'C_
10K
FREQUENCY - Hz
mA
V.!,=I±
1~V
180
/
1-,...
/
V
"
r-
/
oo '2.0
4.0 6.0 1.0 10
12
SUPPLY VOLTAGE
14 16
-±v
18
20
0
0
-75 -55 -35 -IS 5.0 3
45 65
TEMPERATURE
7-26
_oc
85 105 13
o
2.0 4.0 S.O 8.0 10 12
14
SUPPLY VOLTAGE - ±V
'6
18
20
IlA 1458 • IlA 1558
I=AIRCHIL.O
Dual Internally Compensated
Operational Amplifiers
A Schlumberger Company
Linear Division Operational Amplifiers
Description
Connection Diagram
8-Lead Metal Package
(Top View)
The J.lA 1458, J.lA 1558 are a monolithic pair of internally
frequency compensated high performance amplifiers constructed using the Fairchild Planar Epitaxial process. They
are intended for a wide range of analog applications
where board space or weight are important. High common
mode voltage range and absence of latch up make the
J.lA 1458, J.LA 1558 ideal for use as voltage followers. The
high gain and wide range of operating voltage provide superior performance in integrator, summing amplifier and
general feedback applications.
The J.lA 1458, J.lA 1558 are short circuit protected and require no external components for frequency compensation.
The internal 6.0 db/octave roll off ensures stability in
closed loop applications. For single amplifier performance,
see the J.LA 741 data sheet.
The Fairchild J.lA1458, J.lA1558 slew rate has been improved to 0.8/ J.lS typical.
v+
vLead 4 connected to case.
Order Information
Device Code
Package Code
J.lA1458HC
J.lA1458CHC
J.lA1558HM
• No Frequency Compensation Required
• Short Circuit Protection
• Large Common Mode And Differential Voltage
Ranges
• Low Power Consumption
• No Latch Up
• Mini-Dip Package
5W
5W
5W
Package Description
Metal
Metal
Metal
Connection Diagram
8-Lead DIP and 50-8 Package
(Top View)
Absolute Maximum Ratings
Storage Temperature Range
Metal Can and Ceramic DIP
Molded DIP and SO-8
Operating Temperature Range
Extended (J.LA 1558M)
Commercial (J.lA 1458C)
Lead Temperature
Metal Can and Ceramic DIP
(soldering, 60 s)
Molded DIP and SO-8
(soldering, 10 s)
Internal Power Dissipation I, 2
8L-Metal Can
8L-Ceramic DIP
BL-Molded DIP
SO-8
Supply Voltage
J.LA1558
J.LA1458
Differential Input Voltage
Common Mode Input Swing 3
Output Short Circuit Duration 4
v+
-65°C to + 175°C
-65°C to + 150°C
OUTS
-INB
-55°C to + 125°C
O°C to +70°C
+INB
300°C
Order Information
265°C
1.00
1.30
0.93
0.81
Device Code
J.lA1458RC
J.lA1458SC
J.LA1458TC
J.lA1458CRC
J.LA1458CTC
J.lA1558RM
W
W
W
W
±22 V
± 18 V
±30 V
±15 V
Indefinite
Package Code
6T
KC
9T
6T
9T
6T
Package Description
Ceramic DIP
Molded Surface Mount
Molded DIP
Ceramic DIP
Molded DIP
Ceramic DIP
B.7 mWrC, the BL·Molded DIP at 7.5 mWrC, and the SO·B at
6.5 mWrC.
3. For supply voltages less than ± tS V, the absolute maximum input
voltage is equal to the supply voltage.
4. Short circuit may be to ground or either supply. Rating applies to
Notes
1. TJ Max = IS0·C for the Molded DIP and SO·B, and 17S·C for the Metal
Can and Ceramic DIP.
2. Ratings apply to ambient temperature at 2S·C. Above this temperature,
derate the BL·Metal Can at 6.7 mW rc, the BL-Ceramic DIP at
+ 125°C case temperature or 70°C ambient temperature.
7-27
p.A 1458 • p.A 1558
Equivalent Circuit (112 of Circuit)
;-~--------~------~---------1----~-------------------'--V+
OUT
+IN
-IN
----+---+-----1f-....I
Rl
1 kO
R3
5OkO
RZ
lkO
L-____~--_4----~------~----~
____
Rll
5OkO
L_--~~~~_____+--~L_~~V-
7-28
I1A 1458 • I1A 1558
~A1458 and ~A1458C
Electrical Characteristics TA = 25°C, Vee = ± 15 V, unless otherwise specified.
!.LA1458C
!.LA1458
Symbol
Characteristic
VIO
Input Offset Voltage
110
Input Offset Current
liB
Input Bias Current
21
Input Impedance
Icc
Supply Current
Pc
Power Consumption
CMR
Common Mode Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Condition
Min
Rs<10 kil
0.3
Vo=O V
Typ
Max
Typ
Max
Unit
2.0
6.0
2.0
10
mV
0.03
0.2
0.03
0.3
!.LA
0.2
0.5
0.2
0.7
!.LA
1.0
2.3
5.6
2.3
8.0
mA
70
170
70
240
mW
70
90
60
90
±13
± 11
±13
30
los
Output Short Circuit Current
Large Signal Voltage Gain
Vo=±10 V, RL;;;'2.0 kD
VOP
Output Voltage Swing
RL=10kil
fc
Unity Gain Crossover
Frequency
SR
Slew Rate
150
dB
V
30
20
!.LVIV
20
mA
20
100
20
100
V/mV
±12
±14
± 11
±14
V
1.1
1.1
MHz
0.8
0.8
V/!.Ls
Av = 1.0
The following specifications apply for O°C < TA <
MD
1.0
±12
Rs<10 kil
Avs
Min
+ 70°C
VIO
Input Offset Voltage
Rs<10 kD
7.5
tlVloltlT
Input Offset Voltage
Temperature Sensitivity
Rs= 50 il
110
Input Offset Current
0.3
0.4
!.LA
liB
Input Bias Current
0.8
1.0
!.LA
12
15
Avs
Large Signal Voltage Gain
Vo=±10 V, RL;;;'2.0 kil
VOP
Output Voltage Swing
RL = 2.0 kD
7-29
±13
!.LVloC
15
15
15
±10
±9.0
mV
V/mV
±13
V
JIA 1458 • JIA 1558
/lA1558
Electrical Characteristics T A = 25°C, Vee = ± 15 V, unless otherwise specified.
J.LA 1558
Symbol
VIO
Characteristic
Input Offset Voltage
110
Input Offset Current
liB
Input Bias Current
ZI
Input Impedance
Icc
Supply Current
Pc
Power Consumption
CMR
Common Mode Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
los
Output Short Circuit Current
Condition
Min
Rs": 10 kn
0.3
Vo=O V
Avs
Large Signal Voltage Gain
Vo=±10 V, RL>2.0 kn
Output Voltage Swing
RL = 10 kn
fc
Unity Gain Crossover Frequency
SR
Slew Rate
Max
Unit
1.0
5.0
0.03
0.2
IlA
0.2
0.5
!lA
mV
Mn
1.0
2.3
5.0
mA
70
150
mW
70
90
±12
±13
30
Rs":10 kn
VOP
Typ
dB
V
150
IlVN
20
mA
50
200
VlmV
±12
±14
V
1.1
MHz
0.8
V/IlS
Av = 1.0
The following specifications apply for -55°C": TA": + 125°C
6.0
VIO
Input Offset Voltage
Rs":10 kn
tJ.VloltJ.T
Input Offset Voltage Temperature
Sensitivity
Rs=50 n
110
Input Offset Current
0.5
liB
Input Bias Current
1.5
Avs
Large Signal Voltage Gain
Vo=±10 V, RL>2.0 kn
VOP
Output Voltage Swing
RL =2.0 kn
7-30
!lA
!lA
V/mV
25
±10
mV
IlV/oC
15
±13
V
JlA 1458 • JlA 1558
Typical Performance Curves TA = 25°C, Vee
Voltage Gain vs
Supply Voltage
115
z
C
110
"w
"~ 100
..
95
g
90
o
.ffi
28
./'
-
V
.;-
24
I
w
20
"~
,/'"
0
>
..
I-
=>
12
I-
=> 8.0
85
80
3.0
6.0
9.0
12
18
15
.,
o
10
m
100
70
50
C
"w
!i
~
60
!j
..
g
..
0
>
zw
;t
40
2
20
I'"
..
i'..
0
-20
10
40
30
z
20
1.0
I
E
"-
100
1.0K
Ii:
iii
z
100 K
Hz
LOAD RESISTANCE -
1.4
r-
Yo
0
1.'
~
./
~
/'
10
E
I
w 0.8
0
z
7.0
a: 5.0
4.0
~
0 3.0
"'- \
..
1.0
2.0
0.6
l-
=>
l-
=>
0.4
0
0.2
2.0
Hz
1.0
.
//
0
..
n
Output Noise vs
Source Resistance
0
10K lOOK 1.0M 10M
FREQUENCY -
r--.
10 K
1.0 K
Power Consumption vs
Supply Voltage
100
80
100
FREQUENCY -
120
I
I II I II I II
tv
Open Loop Frequency
Response
..
RL = 2 k
r-VOLTAGE FOLLOWER
±15 V SUPPLIES
THO < 5%
4.0
SUPPLY VOLTAGE-
Z
1\
18
0
o
Output Voltage Swing vs
Load Resistance
32
105
g
V, unless otherwise specified
Power Bandwidth (Large Signal
Swing vs Frequency)
120
tI
= ± 15
6.0
10
18
14
22
SOURCE RESISTANCE -
SUPPLY VOlTAGE-± V
Typical Applications
Quadrature Oscillator
High Impedance, High Gain Inverting Amplifier
Y+
.2
190 kU
1%
f = 21r
7-31
J
1
C2 R2 C3 R3 (R1 C1
C1
= R2
C2)
:r:~~~
pF
n
J1A 1458 • J1A 1558
Typical Applications (Cont.)
CompressorIExpander Amplifiers
Dl
R
RZ
10 kO
D3
R
+15 V
R
COMPRESSOR
R4
EXPANDER
10 kO
>'':l:''"___~_DO_UT_ _ _ -..:(IN>-4_..,;;;,yy_....,_
......-lF"
R
D4
Notes
Maximum compression expansion ratio - R,/R (10 kn> R >0)
Diodes 01 through 04 are matched F06666 or equivalent
Analog Multiplier
+15 V
AMPLIFIER
CURRENT SOURCE
lN9638
R2
20 kll
1%
Rl
20 kll
1%
Eo
E"
RS
-15
v
5 kn
1%
R4
R3
15 kll
1%
20 kll
1%
-=EXPANDER
COMPRESSOR
-=
-15 V
ZERO ADJUST
+15 V
Note
1. Matched to 0.1%
Eo - 100 EI1 X E'2
7-32
EXPANDER
OUT
J.1.A 148 • J.1.A248 • J.1.A348
FAIRCHILD
Quad
Operational Amplifiers
A Schlumberger Company
Linear Division Operational Amplifiers
Description
Connection Diagram
14·Lead DIP
(Top View)
The JJA 148 series is a true quad JJA741. It consists of
four independent, high gain, internally frequency compensated, low power operational amplifiers which have been
designed to provide functional characteristics identical to
those of the familiar JJA741 operational amplifier. In addition, the total supply current for all four amplifiers is comparable to the supply current of a single JJA741 type
operational amplifier.
Other features include input offset currents and input bias
currents which are much less than those of a standard
JJA 741. Also, excellent isolation between amplifiers has
been achieved by independently biasing each amplifier and
using layout techniques which minimize thermal coupling.
OUT A
-IN A
-IN D
+IN A
y+
•
•
•
•
•
•
•
•
JJA741 Op Amp Operating Characteristics
Low Supply Current Drain
Class AB Output Stage - No Crossover Distortion
Lead Compatible With The JJA324 & JJA3403
Low Input Offset Voltage -1.0 mV Typically
Low Input Offset Current - 4.0 nA Typically
Low Input Bias Current - 30 nA Typically
Gain Bandwidth Product For JJA148 (Unity Galn)1.0 MHz Typically
• High Degree Of Isolation Between Ampllflers120 dB Typically
• Overload Protection For Inputs And Outputs
y-
+IN B
+IN C
-IN B
-IN C
OUT B
OUT C
Order Information
Device Code
JJA148DM
JJA248DV
JJA248PV
JJA348DC
JJA348PC
Package Code
6A
6A
9A
6A
9A
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
Ceramic DIP
Molded DIP
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Extended (JJA 148M)
Industrial (JJA248V)
Commercial (JJA348C)
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1,2
14L-Molded DIP
14L-Ceramic DIP
Supply Voltage
JJA148
JJA248, JJA348
Differential Input Voltage
JJA148
JJA248, IlA348
Input Voltage
JJA148
JJA248, JJA348
Output Short Circuit Duration 3
-65°C to + 175°C
-65°C to +150°C
-55°C to + 125°C
-25°C to +85°C
O°C to +70°C
300°C
265°C
1.04 W
1.36 W
±22 V
±18 V
Notes
1. TJ Max = 150'C for the Molded DIP, and 175'C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 25'C. Above this temperature,
derate the 14-Lead Molded DIP at 8.3 mWI'C, and the 14-Lead
Ceramic DIP at 9.1 mWI'C.
3. Any of the amplHier outputs can be shorted to ground indefinitely;
however, more than one should not be simultaneously shorted as the
maximum junction temperature will be exceeded.
±44 V
±36 V
±22 V
±18 V
Indefinite
7-33
JlA 148 • JlA248 • JlA348
Equivalent Circuit (1/4 of Circuit)
~------------------.-----------~~~-------------.--v+
R6
-IN
+IN
18
n
OUT
R7
V+
22n
+-----+-1: Q7
R3
SOKn
~--~~~--~
__
R4
3.4K
n
~------~--+----------4--~----~--~--~~V-
D
= CIIOSSUNDER
EOO0061F
7-34
IlA 148 • IlA248 • IlA348
pA148
Electrical Characteristics TA = 25°C, Vee = ± 15 V, unless otherwise specified.
DC Characteristics
Symbol
Characteristic
Via
Input Offset Voltage
110
Input Offset Current
liB
Input Bias Current
ZI
Input Impedance
Condition
Min
Typ
Max
0.8
Unit
5.0
mV
4
25
nA
30
100
1.0
Rs<10 kn
2.5
nA
Mn
3.6
rnA
Icc
Supply Current (Total)
2.4
los
Output Short Circuit Current
25
rnA
160
V/mV
Avs
Large Signal Voltage Gain
Vo=±10 V, RL;;;'2.0 kn
CS
Channel Separation
1.0 Hz
Phase Margin
SR
Slew Rate
Av
=
7-35
IlA 148 • IlA248 • J.LA348
!.LA248
Electrical Characteristics T A = 25°C. Vee
= ± 15
V. unless otherwise specified.
DC Characteristics
Symbol
Characteristic
Via
Input Offset Voltage
110
Input Offset Current
lis
Input Bias Current
ZI
Input Impedance
Condition
Min
Typ
Max
1.0
Rs';;; 10 kU
0.8
Unit
6.0
mV
4
50
nA
30
200
2.5
nA
MU
Icc
Supply Current (Total)
2.4
los
Output Short Circuit Current
25
mA
Avs
Large Signal Voltage Gain
Vo=±10 V. RL;;;'2.0 kU
160
V/mV
CS
Channel Separation
1.0 Hz';;; f .;;; 20 kHz
(Input Referred)
25
4.5
-120
mA
dB
The following specifications apply over the range of -25°C';;; TA .;;; + 65°C.
Via
Input Offset Voltage
110
Input Offset Current
Rs';;;10 kU
7.5
mV
125
nA
500
lis
Input Bias Current
CMR
Common Mode Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection
Ratio
Rs';;; 10 kU
77
Avs
Large Signal Voltage Gain
Va = ± 10 V. RL ;;;'2.0 kU
15
VoP
Output Voltage Swing
RL = 10 kU
±12
±13
RL = 2.0 kU
±10
±12
70
Rs';;; 10 kU
90
±12
nA
dB
V
96
dB
V/mV
V
AC Characteristics
BW
Bandwidth
1.0
MHz
rt>
Phase Margin
Av= 1.0
60
degrees
SR
Slew Rate
Av = 1.0
0.5
V/J.IS
7-36
J.1A 148 • J.1A248 • J.1A348
J.lA348
Electrical Characteristics TA
=
25°C, Vee
=
± 15 V, unless otherwise specified.
DC Characterisitcs
Symbol
Characteristic
Via
Input Offset Voltage
110
Input Offset Current
118
Input Bias Current
ZI
Input Impedance
Condition
Rs~
Min
10 kil
Typ
Max
1.0
0.8
Unit
6.0
mV
4
50
nA
30
200
2.5
nA
Mil
Icc
Supply Current (Total)
2.4
los
Output Short Circuit Current
25
mA
Avs
Large Signal Voltage Gain
Vo=±10 V, RL;;'2.0 kil
160
V/mV
CS
Channel Separation
1.0 Hz~f~20 kHz
(Input Referred)
-120
dB
25
4.5
mA
The following specifications apply over the range of O°C ~ TA ~ + 70°C.
Via
Input Offset Voltage
110
Input Offset Current
Rs~10 kil
lis
Input Bias Current
CMR
Common Mode Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection
Ratio
Rs~
Avs
Large Signal Voltage Gain
Vo=±10 V, RL;;'2.0 kil
VoP
Output Voltage Swing
RL = 10 kil
±12
±13
RL = 2.0 kil
±10
±12
7.5
mV
100
nA
400
Rs~
10 kil
70
90
±12
10 kil
77
nA
dB
V
96
15
dB
V/mV
V
AC Characteristics
BW
Bandwidth
rt>
Phase Margin
SR
Slew Rate
1.0
MHz
Av = 1.0
60
degrees
Av = 1.0
0.5
V/J1-s
7-37
•
p.A 148 • p.A248 • p.A348
Typical Performance Curves
Positive Common Mode Input
Voltage Limit vs Supply Voltage
20
-55 0
..
....
:>
J~ 1 J
TA
01
~t::
15
/
z!!
0..1
:lw
:10
oc
U!:i
wo
~>
10
/
!::
..
on
0
5
5
/
/
~120
~
;;
z
\
80
60
10
~
MEAN NOISE VOLTAGE
o
10
100
FREQUENCY -
1.0
i
0.6
1.0K
II
II
0
>
I
"'i>v,
;;
~
0.2 :I
/
81
-15
:I!::
+25O.C~
z:l
0:::;
I~
~5
tLL
w
z
-5
-5
-20
V
>
I
w
Ii
a
vJ=±!v
RL=2k
/
Av=·'
TA=25°C -
\
\
I
... .,.
10
/
\
?'
>
v,
10
100
10
0
0
0
-1 00
10
10
160
120
TIME
I
0
\
~io--
80
-15
Vo
10
[\
!:i '!io--
40
-10
Inverting Large Signal
Pulse Response
~
TIME -~.
/7
NEGATIVE SUPPLY VOLTS -
Av = 1
RL ~ 2 K
~
"..:: ~5°lc
0
0
10K
~
hV
-10
5>
TA "" 25°C
/
+125O~ ~
i!!
w>
Hz
~
<-
.......
:>
Vo
10
1\
\
h
......
:I 8;'!
0.4 Z
Large Signal Pulse Response
Ycc=±15V
TA = 25"e
Av = 1
I
I
I
I
20
V
Small Signal Pulse Response
Vo
1
0.8 ~
MEAN NOISE CURRENT
20
15
100
1.2
a:
~ 40
:I
-20
1.6
1 .4 ~
I
III 100
~~
POSITIVE SUPPL Y VOLTS -
0
'±;~ U
vee' =
TA "" 25"C
~140
1/
z
;;;>
160
;~
+125 o
Negative Common Mode Input
Voltage Limit vs Supply Voltage
Input Noise Voltage and Noise
Current vs Frequency
v,
o
200
20
40
60
-~.
80 100 120 140 160 180 200
TIME -
p8
PC/),2981F
Supply Current vs
Power Supply Voltage
Input Bias Current vs
Ambient Temperature
Output Voltage Swing vs
Supply Voltage
80
50
1
70
>
I
~
I
~
80
!
:i
50
ID
30
80
25
0
/
: ,.....
C,........-
""""-:L..--' ?
-55"
~ ~ ~ ~C
f-""
o
o
10
15
SUPPLY VOLTAGE - ±V
--
a~
~
~ ~ Vcc.,.±20V cc=±15Vr--~
.....
R~.(.
Vcc=±10V
-. r--.
--,:::~~._
20 vee ±5r
_
~f=::=i
40
l
10
20
0
-55 -35
15
25
45
65
TEMPERATURE _ "C
7-38
85
105 125
TA "" 25°C
40
i
30
~
20
..
0
1
V
~
~
*
V
V
V
V
V
0
10
15
SUPPLY VOLTAGE
20
-±V
25
IlA 148 • IlA248 • 1lA348
Typical Performance Curves (Cont.)
Output Voltage vs
Source Current
Output Voltage vs
Sink Current
-15
15
>
I
VCC=±15V
I
~
0
~ ~ ..........·c
25'~
\\ss.c
1\
~
5
'"
125"C
o
VCC=~'SV
'\
e
I
~
i'\,r\
10
!;
Output Impedance vs
Frequency
o
10
I
+~OC\
20
"
OUTPUT SOURCE CURRENT -
os
Q
I
i
~
I
125"e
o
o
30
10
mAo
11
20
OUTPUT SINK CURRENT -
21
30
mA
FREQUENCY -
Hz
FC03030F
CMR vs Frequency
Gain and Phase vs Frequency
110
80
r-...
70
3
30
i
'"
r-...
"-
10
100 K 1.0 K
10 K
FREQUENCY -
I
-5
3
-10
"
-15
-20
"
-25
i\..
-10
10
10
r-...
i\..
Iso
15
Vcc"'±1SV
TA ... 25"C
t--
"
'8
20
I
i\..
"''''''''F
Gain Bandwidth vs
Temperature
100 K
Hz
1.0 M 10 M
-30
-35
0.1
100
Vcc=±15V
90
TA = 25"C
80
Llll
~
IIIII
"
PHASE
IBw
II
so Ii!
~
60
~
\
10kO
40
r'\.GAIN
f1>l:
30
20
2.0k~\
.
Vcc=±15V
70
:l
f
10
10
0.5
FREQUENCY -
'w"I
MHz
z
~
~~45~-_~U~~'~25=-~U7-~5S~5S=-~105=-~~
TEMPERATURE - "C
"""""
7-39
I
10
"\
.
0:
PC03010F
MA3303 • MA3403 • MA3503
Quad
F=AIRCHILD
A Schlumberger Company
Operational Amplifiers
Linear Division Operational Amplifiers
Description
Connection Diagram
14-Lead DIP and S~14 Package
(Top View)
The pASSOS, pAS40S, and pAS50S are monolithic quad
operational amplifiers consisting of four independent high
gain, internally frequency compensated, operational amplifiers designed to operate from a single power supply or
dual power supplies over a wide range of voltages. The
common mode input range includes the negative supply,
thereby eliminating the necessity for external biasing components in many applications. They are constructed using
the Fairchild Planar Epitaxial process.
OUT A
-IN A
+IN 0
+IN A
v+
• Input Common Mode Voltage Range Includes Ground
Or Negative Supply
• Output Voltage Can Swing To Ground Or Negative
Supply
• Four Internally Compensated Operational Amplifiers
In A Single Package
• Wide Power Supply Range Single Supply Of 3.0 V
To 36 V Dual Supply Of ± 1.5 To ± 18 V
• Class AB Output Stage For Minimal Crossover
Distortion
• Short Circuit Protected Outputs
• High Open Loop Gain 200K Typically
• pA741 Operational Amplifier Type Performance
v·
+IN B
-IN C
-IN B
OUT C
OUT B
Order Information
Device Code
pASSOSDV
pASSOSPV
pAS40SDC
pA340SPC
pAS40SSC
pAS50SDM
Absolute Maximum Ratings
5torage Temperature Range
-65·C to + 175·C
Ceramic DIP
-65·C to + 150·C
Molded DIP and 50-14
Operating Temperature Range
-55·C to + 125·C
Extended (pAS50SM)
-40·C to + 85·C
Industrial (pASSOSV)
O·C to +70·C
Commercial (pAS40SC)
Lead Temperature
SOO·C
Ceramic DIP (soldering, 60 s)
Molded DIP and 50-14
265·C
(soldering, 10 s)
Internal Power Disisipation l , 2
1.S6 W
14L-Ceramic DIP
14L-Molded DIP
1.04 W
50-14
0.9S W
Supply Voltage Between V + and V- S6 V
±SO V
Differential Input Voltage3
Input Voltage (V _1)3
-O.S V (V-) to V+
Notes
I. TJ Max = 150·C for the Molded DIP and 80-14, and 175·C for the
Ceramic DIP.
2. Ratings apply' to ambient temperature at 25·C. Above this temperature,
derate the 14L·Ceramic DIP at 9.1 mW/·C, the 14L·Molded DIP at
B.3 mWrC, and the 80·14 at 7.5 mWrC.
3. For supply voltage less than 30 V between V + and V -, the absolute
maximum input voltage is equal to the supply voltage.
7-40
Package Code
Package Description
6A
9A
6A
9A
KD
6A
Ceramic DIP
Molded DIP
Ceramic DIP
Molded DIP
Molded Surface Mount
Ceramic DIP
~3303 • J.LA3403 • ~3503
Equivalent Circuit (1/4 of Circuit)
OUT
~------------~----------'-----~~------'------+-1------~--V+
+IN
-1------------++------.
-IN
7-41
MA3303 • MA3403 • MA3503
MA3303 and MA3403
Electrical Characteristics TA = 25°C, Vee = ± 15 V, unless otherwise specified.
~3403
~3303
Symbol
Characteristic
Condition
Min
Typ
Max
Typ
Min
Max
Unit
VIO
Input Offset Voltage
2.0
8.0
2.0
8.0
mV
110
Input Offset Current
30
75
30
50
nA
118
Input Bias Current
200
500
200
500
nA
ZI
Input Impedance
Icc
Supply Current
Vo = 0 V, RL =
CMR
Common Mode Rejection
Rs";10 kn
VIR
Input Voltage Range
PSRR
Power Supply Rejection
Ratio
los
Output Short Circuit Current
(Per Amplifier) 1
Avs
Large Signal Voltage Gain
Vo=±10 V,
RL >2.0 kn
VOP
Output Voltage Swing
TR
Transient
Response
0.3
1.0
2.8
00
0.3
7.0
MS1
1.0
2.8
7.0
mA
70
90
70
90
dB
+12
to
V-
+12.5
to
V-
+13
to
V-
+13.5
to
V-
V
30
150
p.VIV
±10
±30
±45
mA
200
20
200
12.5
±12
+13.5
12
±10
±13
30
150
±10
±30
±45
20
RL = 10 kS1
±12
RL =2.0 kS1
±10
V/mV
V
Rise timet Vo=50 mY,
Fall time
Av = 1.0, RL = 10 kS1
0.3
0.3
p.s
Overshoot Vo=50 mY,
Av = 1.0, RL = 10 kS1
5.0
5.0
%
BW
Bandwidth
Vo=50 mY,
Av = 1.0, RL = 10 kS1
1.0
1.0
MHz
SR
Slew Rate
VI=-10 V to +10 V,
Av = 1.0
0.6
0.6
V/IJ.S
The following speCifications apply for -40·C"; TA ..; + 85·C for the p.A3303, and O·C"; TA ..; + 70·C for the p.A3403.
VIO
Input Offset Voltage
10
110
10
10
I1VlolfH Input Offset Voltage
Temperature Sensitivity
Input Offset Current
250
11110/I1T Input Offset Current
Temperature Sensitivity
200
50
50
118
Input Bias Current
Avs
Large Signal Voltage Gain
Vo=±10 V,
RL>2.0 kS1
15
1000
15
VOP
Output Voltage Swing
RL =2.0 kS1
±10
±10
7-42
mV
p'vrc
10
nA
pArC
800
nA
VlmV
V
/-LA3303 • /-LA3403 • /-LA3503
IlA3303 and 1lA3403 (Cont.)
Electrical Characteristics T A = 25°C, V + = 5.0 V, V - = Gnd, unless otherwise specified.
/lA3303
Symbol
VIO
Characteristic
Typ
Max
Typ
Min
B.O
Input Offset Voltage
110
Input Offset Current
lis
Input Bias Current
Icc
Supply Current
PSRR
Power Supply Rejection
Ratio
Avs
Large Signal Voltage Gain
VoP
Output Voltage SWing 2
2.5
RL > 2.0 kg
20
RL = 10 kg
~30
V,
Unit
B.O
mV
nA
75
30
50
500
200
500
nA
7.0
2.5
7.0
rnA
150
/lVN
20
200
3.3
3.3
(V+)
-2.0
(V+)
-2.0
1.0 Hz ~ f ~ 20 kHz
(Input Referenced)
Channel Separation
Max
2.0
150
5.0 V~V+
RL = 10 kg
CS
Min
Condition
/lA3403
200
V/rnV
V
-120
-120
dB
IlA3503
Electrical Characteristics TA = 25°C, Vee = ± 15 V, unless otherwise specified.
!lA3S03
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
Via
Input Offset Voltage
2.0
5.0
mV
110
Input Offset Current
30
50
nA
liS
Input Bias Current
200
500
ZI
Input Impedance
0.3
Icc
Supply Current
Va = 0, RL =
CMR
Common Mode Rejection
Rs~lO
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
los
2.B
00
kg
Output Short Circuit Current
(Per Amplifier) 1
rnA
90
dB
+13
to
V-
+13.5
to
V-
V
30
150
/lVN
±10
±30
±45
rnA
Avs
Large Signal Voltage Gain
Vo=±10 V, RL>2.0 kg
50
200
Output Voltage Swing
RL = 10 kg
±12
± 13.5
RL = 2.0 kg
±10
±13
Transient
Response
4.0
70
VOP
TR
nA
Mg
1.0
V/mV
V
IRise time
Va = 50 mY, Av = 1.0, RL = 10 kg
0.3
JOvershoot
Vo=50 mY, Av=1.0, RL=10 kg
5.0
%
/lS
BW
Bandwidth
Va = 50 mY, Av = 1.0, RL = 10 kg
1.0
MHz
SR
Slew Rate
VI=-10 V to +10 V, Av=1.0
0.6
V//ls
7-43
1lA3303 • 1lA3403 • J,LA3503
A" +
1lA3503
Electrical Characteristics -55°C" T
125°C, Vee = ± 15 V, unless otherwise specified.
/lA3503
Symbol
Characteristic
VIO
Input Offset Voltage
!lVIO!!IT
Input Offset Voltage
Temperature Sensitivity
110
Input Offset Current
!lllo! !IT
Input Offset Current
Temperature Sensitivity
Condition
Min
Typ
Max
6.0
200
Input Bias Current
Avs
Vo=±10 V, RL~2.0 kfl
VOP
Output Voltage Swing
RL=2.0 kfl
nA
pArC
50
Large Signal Voltage Gain
mV
IlVloC
10
liB
Unit
1200
25
nA
V!mV
±10
V
The following specifications apply for T A = 25°C, V + = + 5.0 V, V- = GND.
VIO
Input Offset Voltage
2.0
5.0
mV
110
Input Offset Current
30
50
nA
liB
Input Bias Current
200
500
nA
Icc
Supply Current
PSRR
Power Supply Rejection
Ratio
2.5
Avs
Large Signal Voltage Gain
RL~2.0 kfl
20
VOP
Output Voltage SWing2
RL=10 kfl
3.3
5.0 V<"V+ <"30 V, RL=10 kfl
CS
Channel Separation
1.0 Hz <" f <" 20 kHz (Input Referenced)
Notes
1. Not to exceed maximum package power dissipation.
2. Output will swing to ground.
7-44
200
4.0
mA
150
IlVIV
V!mV
V
(V+)
-2.0
-120
dB
J,LA3303 • J,LA3403 • J,LA3503
Typical Performance Curves
Open Loop Frequency Response
:c
"..
"~
80
>
40
Output Voltage vs Frequency
VCC"" ±1S V
TA
1100
I
z
Sine Wave Response
30
120
Av = 100
"" 25°C
~ III 1/\ 1\ If\ [
~
d
80
..
g
...
0
.I
IV V hl IV \J
i!:
0
~
20
z
III
0
r. r.
.::
.~
g
~~
1
\
5
10
5.0
-......
o
Hz
r-
-5 .0
T.OK
SO
= 25°C
"" 10 kU
TA
AL
20
I
NOTE: CI... AS output ltage produce.
dl,tortlonl... line wave
- 20 1!-'.o,u.LI..:l'O,...uw..,I-!;:IIO,..u.ll,:-:.o~K:f-'JIL'~O:-:K!-"-"'IOO±-!K;'l':,:-:!.O M
FREQUENCY -
r.
r..
r.;
lee 1= Wv
.
~./DIV
10 K
1.0 M
100 K
FREQUENCY -
Hz
PC02591F
Output Swing vs
Supply Voltage
Input Bias Current vs
Temperature
40
t='2.·L
Input Bias Current vs
Supply Voltage
180
4110
Vel
=
~'5 J-
~
~
..
.". 20
I
.is
30
./
z
...
..
r-
'/
0
>
:>
/'
10
.
~
...
..
!; 160
!
/
:>
"
u
'-.
"~
'10
::i:>
a:
/
0
,I
oQ
2.0 4.0 8.0 8.0 1Q
12
SUPPLY VOLTAGE -
14
tv
16
18 20
150
o
-75 -55 -35 -15 5.0 25
45
TEMPERATURE _
7-45
65
0
C
85 105 125
o
2.0 4.0 6.0 8.0 10
12
14
16
SUPPLY VOLTAGE-:!:Y
18
20
J,LA3303 • J,LA3403 • J,LA3503
Typical Applications
Wein Bridge Oscillator
50 kll
r-----~~-----t--vo
Multiple Feedback Bandpass Filter
10 kll
-t
VREF ....- " " '............
VREF =
c
+V+
R
fo = center frequency
fo
BW ~ Bandwidth
R in kU
C in I'F
~
1
- - for fo ~ 1 kHz
21TRC
R~16 kn
C ~ 0.Q1 I'F
Comparator With Hysteresis
Q~~<10
BW
C1
R2
Q
~C2~~
R1
3
VAEF-""',...............
v,---------f'
R1 ~ R2 ~ 1J
R3 = 9Q2_1
Use scaling factors in these expressions.
HYSTERESIS
VOHEifL
I
VOL
Vo
Vo
VIL
IVIH
I
VAEF
If source impedance is high or varies, filter may be preceded with
voltage follower buffer to stabilize filter parameters.
Design example:
given: Q ~ 5, fo ~ 1 kHz
Let R1 - R2 ~ 10 kn
then R3 ~ 9(5)2 - 10
R3~215
5
C~-~
3
kn
1.6 nF
7-46
J..lA3303 • J..lA3403 • J..lA3503
Typical Applications (Cant.)
High Impedance Differential Amplifier
AC Coupled Inverting Amplifier
R6
RI
100 kn
Vl
Rl
C, 10 kn
'f
R3
Co
R4
+
Cl
11
10 kn
R2
l001cQ
V+
10.uFJ,
1\ 1\""
o
\J
RS
2Vp_p
T
V2
R7
Rt
AY~Fi1
Ay
~
10 (as shown)
Your ~ C(1 + a + b)(V2 - V1)
R2
R6
R5
R7
- '" R1
~
R2~
Voltage Reference
tor
best CMRR
V+
R4
R5
R6 ( 1 +
2R1
-)
R5
R3
Gain~-
R2
10kO
~C(1
+a+b)
Rl
10kO
AC Coupled Non-Inverting Amplifier
AFOO380F
V - -R1
-- (
0- R1 + R2
=2 as shown )
V+
Ground Referencing A
Differential Input Signal
Rl
1MO
va
R2
Ay~ 1 +Fi1
Ay
~
+
VR
11 (as shown)
R2
1Mn
R4
1Mn
+VCM
R3
1M!}
7-47
MA3303 • MA3403 • MA3503
Typical Applications (Cont.)
Voltage Controlled Oscillator
RI
100 kll
n...r
+Vco - ......"..""'......- - - - -.....-4
(NOTE 1)
51 kll
OUT 1
R2
50 kll
/'.A
OUT 2
Function Generator
VAEF
=
i
TRIANGLE WAVE
OUT
Vee
R2
300kll
,---'\IIoI\t--......-SQUARE WAVE
OUT
R3
75kU
VAEF
c
RI
IOOkll
Rf
(NOTE 2)
L---'--VREF
Pulse Generator
Vo
+
SL..rL
Note
1. Wide Control Voltage Range:
OV';;'Vco';;'2 (V+-1.5 V)
R1 + R2
R2R1
2. f = - - - if R3=--4CRIR1
R2 + R1
7-48
J,LA3303 • MA3403 • MA3503
Typical Applications (Cent.)
Bi-Quad Filter
A
R
C
C1
V,
R2
--jf-1.........Nv-.......-I
VREF
R1
RZ
C1
f--NOTCH OUT
VREF
BW
Q-10
where
TBP - Center Frequency Gain
TN - Bandpass Notch Gain
Rl-QR
Rl
R2-TBP
R3 -TNR2
Cl-l0 C
Example:
10 -1000 Hz
BW-l00 Hz
T BP - l
TN-l
R-160 kS1
Rl =1.6 MS1
R2-1.6 MS1
R3-1.6 MS1
C -0.001 p.F
7-49
J.lA4136
Quad
Operational Amplifier
I=AIRCHILD
A Schlumberger Company
Linear Products Operational Amplifiers
Description
Connection Diagram
14-Lead DIP and 80-14 Package
(Top View)
The j.lA4136 Monolithic Quad Operational Amplifier consists
of four independent high gain, internally frequency compensated operational amplifiers. The specifically designed
low noise input transistors allow the j.lA4136 to be used in
low noise signal proceSSing applications such as audio
preamplifiers and signal conditioners. It is constructed using the Fairchild Planar Epitaxial process. The simplified
output stage completely eliminates .crossover distortion under any load conditions, has large source and sink capacity, and is short circuit protected. A novel current source
stabilizes output parameters over a wide power supply
voltage range.
-INA
+INA
Unity Gain Bandwidth - 3.0 MHz Typically
Continuous Short Circuit Protection
No Frequency Compensation Required
No Latch Up
Large Common Mode and Differential Voltage
Ranges
• pA741 Operational Amplifier Type Performance
• Parameter Tracking Over Temperature Range
• Gain and Phase Match Between Amplifiers
•
•
•
•
•
OUT A
OUT 0
OUTB
y+
+INB
OUTC
-IN B
+INC
y-
-INC
Order Information
Device Code
j.lA4136DC
j.lA4136PC
j.lA4136SC
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP and SO-14
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP and SO-14
(soldering, 10 s)
Internal Power Disisipation 1, 2
14L-Ceramic DIP
14L-Molded DIP
SO-14
Supply Voltage
Differential Input Voltage3
Input Voltage 1
Output Short Circuit Duration4
-IN 0
-65°C to + 175°C
-65°C to + 150°C
O°C to +70°C
300°C
265°C
1.36 W
1.04 W
0.93 W
±18 V
±30 V
±15 V
Indefinite
Notes
1. TJ Max = 150·C for the Molded DIP and SO-14, and 175·C for the
Ceramic DIP.
2. Rating apply to ambient temperature at 25·C. Above this temperature,
derate tha 14L·Ceramic DIP at 9.1 mWrC, the 14L·Molded DIP at B.3
mWrC, and tha SO-14 at 7.5 mWrC.
3. For supply voltage less than ± 15 V, tha absolute maximum input
voltage is equal to the supply voltage.
4. Short circuit may be to ground, one amplifier only.
7-50
Package Code
6A
9A
KD
Package Description
Ceramic DIP
Molded DIP
Molded Surface Mount
J.lA4136
Equivalent Circuit (1 /4 of Circuit)
v.--------_4~----------~--_4~--------------~------~--__,
R1
B.7 k
05:.----------~--_f~~--------------~r__1--~
+----.----~r 011
R6
50
RB
100
+--~~-+_--+----OUT
-IN
+IN
R7
50
----t------+---'
014
R9
6.B k
R5
50 k
v-----~--
__
~--_+------~
__--------______
_+----4_------~
Nole
1. All resistor values are in ohms.
7-51
____~----J
J.lA4136
IlA4136
Electrical Characteristics TA = 25°C, Vee
Symbol
= ± 15
V, unless otherwise specified.
Condition
Characteristic
Min
Max
Unit
0.5
6.0
mV
nA
Typ
VIO
Input Offset Voltage
110
Input Offset Current
5.0
200
lis
Input Bias Current
40
500
ZI
Input Impedance
Pc
CMR
Common Mode Rejection
VIR
PSRR
Rs<10 kU
0.3
210
Power Consumption
Rs< 10 kU
70
±12
Input Voltage Range
340
mW
dB
90
±14
V
150
Power Supply Rejection Ratio
Rs< 10 kU
Avs
Large Signal Voltage Gain
RL;;.o2.0 kU, Vo=±10 V
20
300
V/mV
VOP
Output Voltage Swing
RL = 10 kU
±12
±14
V
RL =2.0 kU
±10
±13
TR
BW
Transient
Response
I Rise time
I Overshoot
Bandwidth
30
nA
MU
5.0
VI = 20 mY, RL = 2.0 kU,
CL = 100 pF, Av = 1.0
0.13
Av = 1.0
pV!V
/.LS
5.0
%
3.0
MHz
1.0
V//.LS
dB
SR
Slew Rate
RL = 2.0 kU, Av = 1.0
CS
Channel Separation
f = 10 kHz, Rs = 1.0 kU,
Open Loop
105
f = 10kHz, Rs = 1.0 kU
Av= 100
105
The following specifications apply over the range of - 55°C < TA < + 125°C for /.LA4136; O°C < TA < + 70°C for 1.LA4136C
VIO
Input Offset Voltage
7.5
mV
110
Input Offset Current
300
nA
lIB
Input Bias Current
800
nA
Pc
Power Consumption
TA=TAMax
180
300
mW
400
Large Signal Voltage Gain
TA = TA Min
RL;;.o2.0 kU, Vo=±10 V
240
Avs
VOP
Output Voltage Swing
Rs<10 kU
RL =2.0 kU
Vcc=±15 V
7-52
15
±10
V/mV
V
fJ.A4136
Typical Performance Curves
Input Bias Current vs
Temperature
100
Vee
~
Input Offset Current vs
Temperature
25
1 J
±1S
J
=[ :t15
Vee
':l
80
Common Mode Range vs
Supply Voltage
>
I
w
20
"~
15
"~
...z
..13~
60
'"
"'
40
iii
...
~
!
--
..
w
w
::>
()
I--
t;;
10
~
0
...
......
~
20
~
o
0
10
20
30
40
50
TEMPERATURE _
60
70
40
Z
20
§
~
()
40
50
60
70
SUPPLY VOLTAGE -
°C
-20
1.OK
I 220
g
..,.
W
o
100
E
z
~
~
~ 400
!:i
""","
10
~
I
Z
"r\.
1
Vee
240
j 600
"-
10K
FREQUENCY -
~
±15
J
- r-
r--
()
180
~
~
~
160
0
10
20
30
40
50
60
70
10
TEMPERATURE _ °C
>
26 Vee
TA
I
4
>
I
"~
2
2
"z
~
2
!;
18
~...
::>
~
6
1
o
14
~
12
"
~
"
25°C
/
0
8
0.1
30
40
50
0
60
70
C
Output Voltage Swing vs
Frequency
0
Vee:: :t15 V
= 25°C
= 2 kH
6 TA
R,
2
4
0
~
o
=:
-
.,.
J±1~.1
20
TEMPERATURE _
Output Voltage Swing vs
Load Resistance
28
;tV
..
200
lOOK 1.0M 10M
o
200
'"0z
-!!k...""2kn
§
Hz
Typical Output Voltage vs
Supply Voltage
SUPPLY VOLT AGE -
::>
1-
g
"f:V
Power Consumption vs
Temperature
1"5 V
Vee =
'r\.
g
30
,.'o"
Open Loop Voltage Gain vs
Temperature
r--
80
60
20
w
o
o
'oz"
800
~
~
10
TEMPERATURE _
120
~
-- --
°c
Open Loop Voltage Gain vs
Frequency
.. 100
o
~
0
II
6
2
II
\
8
'\
4
J
0
1.0
LOAD RESISTANCE -
7-53
10
kH
......
100
1.0K
10K
FREQUENCY -
100K
Hz
1.0M
p.A4136
Typical Performance Curves (Cont.)
Quiescent Current vs
Supply Voltage
Voltage Follower Large Signal
Pulse Response
Transient Response
8
0
,
Vee == :t15 V
8 TA = 25°C
10
TA ='2S"C
I
6
~
0
I
>
.
t-
E
Z
W
""""
0:
::>
I
~
"ffi
"ffl
::>
o
..,
•
1
I
8
0
12
SUPPLY VOLTAGE -
15
-4
-0.25
18
r~O% RISE
Vcc=±lSV
TA == 25° C
RL == 2 kH
CL =:: 100 pF
TIME
0.25
0.50
TIME -
:tV
Input Noise Voltage vs Frequency
0
0.75
1.0
-. -
-4
10
1.25
I 100
z
i
0:
::>
I'-
"
w 1.0
'"oz
Distortion vs
Frequency (Vo
=
0
;::
R,
0.5
Av
f
Rs
'"
==
::;:
=
'z"I
2 k
40 dB
1 kHz
1 kn
0
;::
Q
"i,.
..
0
l:
0
t-
'"0
0.'
I
0.3
ot-
0.2
0.1
",.i
...
..
0
~
~
100 K
0 .•
....-
)
O!=;t:;t:::t:t::t:t:~u
o 1,0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10
OUTPUT VOLTAGE-V
:I:
=1 Vrms)
Vee '" 230 V
RIAA COMPENSATION
0.5
0.4
0.3
0.2
\
~
t0
t-
O. 1
./
o
10
100
80
60
.li
40
"
0
loOK
FREQUENCY -
7-54
10 K
Hz
10
100
I.OK
FREQUENCY -
Hz
0:
0:
0
t-
!!!
10 K
o.7
0.7r-.,--.--,-.--r-,-y-..,..,.-"
Vee =- :t15 V
0 .•
1.0K
FREQUENCY -
Distortion vs Output Voltage
(f 1 kHz)
...... r-,
25°C
0
100
Hz
--
:I:
till jOldi
10
40
w
Vee -' _r15 V
~ 25°C
Rs -;;; 100 k
1.0
'z"I
~
TA
0.1
FREQUENCY -
'"
J.m..lvLIJL,L
=
TA
o
..ffi
30
~s
Channel Separation
140
10
___
20
TIME -
I~
I
L
-8
120
i
if
~s
Input Noise Current vs Frequency
i1~HH~~-+~-+~~~++H-+-~+;
,,,
,, 1\
,,
\
,,
,
-1 0
100
~
-
1/
2
!;
o
r-
2
2
~
I
4
~
~g
I
2
~--
,, i/
,,
4
w
90%
lOOK
10 K
Hz
100 K
JlA4136
Typical Applications (Note 1)
400 Hz Lowpass Butterworth Active Filter
10k
620Q
20 k
820 Cl
IN~~-;I~~~~~'-------------~~----------------~------------~~--------,---OUT
0.33pF
1k
1k
-I
I.
I
I
MI38
_____
0.33pF
1.62 k
1k
1k
O.33pF
Differential Input Instrumentation Amplifier With
High Common Mode Rejection
I
I
+
OUT
R3
10k
1%
A
R4
45k
1%
R6
10 k
0.1%
(NOTE 2)
V
~.!!!f,+~)
R2\
R3
Notes
1. All resistor values are in ohms
2. Matching determines CMRR
RI
R7
~
R4
R2=R5
R6= R7
100 k
0.1%
(NOTE 2)
7-55
13.2k
IlA4 136
Typical Applications (Cont.) (Note 1)
Analog Multiplier/Divider
. - - - -.....-0-16 V
10k
10k
El E2
Eo= - -
10k
E,
10k
10 k
10k
10k
10 k
kHz Bandpass Active Filter
v+
120 k
v+
r-.IVI~-t--t-Vo
390k
39k
0.01 pF
820n
620k
J.
10PF
100 k
lOOk
v+
Note
1. All resistor values are in ohms
7-56
tJA4136
Typical Applications (Cont.) (Note 1)
Full-Wave Rectifier And Averaging Filter
20 k
20 k
2.6 k
r -____________JV1%~--------------r_~1A%A-~~~,__~T
4.71'F
~c~~~+~~~~
______~~____-,
4.71'F
CAL
4.7"F
10k
1%
6.1 k
10k
Notch Filter Using The !1A4136 As A Gyrator
Multiple Aperture Window Discriminator
R2
V,
30k
V.
IN
Q,
V3 < VI < V4
Q,==]~--------~
R4
v,-If---i
Notch Frequency vs Capacitor
10k
V'------i
:I!
'1k
liZ
I"'
w
a
I'.
w
II:
:.....
a:: 100
r-..
~
w
(J
10
0.0001
0.001
0.01
0.1
Note
1. All resistor values are in ohms
1.0
CAPACITOR - "F
7-57
11A709
High Performance
Operational Amplifier
FAIRCHIL.D
A Schlumberger Company
Linear Division Operational Amplifiers
Description
Connection Diagram
8-Lead Metal Package
(Top View)
The p.A709 is a monolithic high gain operational amplifier
constructed using the Fairchild Planar Epitaxial process. It
features low offset, high input impedance, large input common mode range, high output swing under load, and low
power consumption. The device displays exceptional temperature stability and will operate over a wide range of
supply voltages with little performance degradation. The
amplifier is intended for use in DC servo systems, high
impedance analog computers, low level instrumentation applications, and for the generation of special linear and
nonlinear transfer functions.
IN FREQ COMP 2
-IN
OUT
v-
Connection Diagram
8-Lead DIP and 50-8 Package
(Top View)
Lead 4 connected to case
Order Information
IN FREQ
COMP1
IN FREQ
COMP2
-IN
y+
+IN
OUT
y-
Device Code
p.A709AHM
p.A709HM
p.A709HG
~A709TG
p.A709SG
Package Code
9T
KG
Package Description
Metal
Metal
Metal
Connection Diagram
14-Lead DIP
(Top View)
OUTFREQ
COMP
NC
Order Information
Device Code
Package Code
5W
5W
5W
Package Description
Molded DIP
Molded Surface Mount
NC
NC
NC
12
IN FREQ
COMP1
IN FREQ
COMP2
-IN
v+
+IN
OUT
vNC
OUT FREQ
COMP
NC
CD00741F
Order Information
Device Code
p.A709PG
7-58
Package Code
9A
Package Description
Molded DIP
fJ.A709
Internal Power Dissipation I, 2
8L-Metal Can
8L-Molded DIP
SO-8
14L-Molded DIP
Supply Voltage
Differential Input Voltage
Input Voltage
Output Short Circuit Duration
Absolute Maximum Ratings
Storage Temperature Range
Metal Can
Molded DIP and SO-8
Operating Temperature Range
Extended (/lA709AM, /lA709M)
Commercial (/lA709C)
Lead Temperature
Metal Can (soldering, 60 s)
Molded DIP and SO-8
(soldering, 1Os)
-65°C to + 175°C
-65°C to + 150°C
-55°C to + 125°C
O°C to +70°C
300°C
265°C
Notes
1. TJ Max ~ IS0·C for the Molded DIP and SO-8, and 17S·C for the Metal
Can.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 8L-Metal Can at 6.7 mWrC, the 8L-Molded DIP at
7.5 mWrC, the SO-8 at 6.5 mWrC, and the 14L-Molded DIP at
8.3 mWrC.
Equivalent Circuit
IN FREO
COMPI
IN FREO
COMP2
~--------.----4-------------+--------~--~--------~----~--V+
R7
1 kfl
06
05
R15
30 kll
OUT
R8
3.6 kll
R9
10kll
OUT FREO
COMP
-IN
RIO
18 kfl
-IN
Q1
013
Rl1
Rl3
2,4 lUI
7511
~-----------4--------------~---+--V-
7-59
1.00 W
0.93 W
0.81 W
1.04 W
± 18 V
±5.0 V
± 10 V
5.0 s
pA709
~709A and MA709
Electrical Characteristics T A = 25°C, ± 9.0 V
« Vee « ± 15
V, unless otherwise specified.
/lA709A
Symbol
Characteristic
Condition
Min
kn
Typ
/lA709
Max
Min
Max
Unit
0.6
2.0
Typ
1.0
5.0
mV
10
50
50
200
nA
100
200
200
500
VIO
Input Offset Voltage
110
Input Offset Current
118
Input Bias Current
ZI
Input Impedance
Icc
Supply Current
VCC=±15V
2.5
3.6
2.7
5.5
mA
Pc
Power Consumption
Vcc=±15 V
75
10S
SO
165
mW
TR
Transient Response
Vcc=±15 V
VI =20 mV
RL =2.0 kn
C1 = 5.0 nF
Av = 1.0
0.3
1.5
0.3
1.0
/lS
Overshoot R2 = 50 n
CL<100 pF
R1 = 1.5 kn
C2 = 200 pF
Av = 1.0
10
30
10
30
%
..
Rs<10
350
Rise time
700
150
nA
kn
400
The follOWing specifications apply over the range of -55°C to + 125°C for the !1A709A and !1A709 .
VIO
Input Offset Voltage
AVIO/AT
Input Offset Voltage
Temperature Sensitivity
110
Input Offset Current
AIIO/AT
Input Offset Current
Temperature Sensitivity
kn
Rs= 50 n
Rs<10 kn
1.S
10
3.0
4.8
25
6.0
TA = +125°C
3.5
50
20
200
TA = -55°C
40
250
100
500
TA = +25°C to
+125°C
0.08
0.5
TA = +25°C to
-55°C
0.45
2.S
TA = -55°C
300
600
2.1
3.0
4.5
3.0
Rs<10
6.0
mV
/lV/DC
nA
nArC
116
Input Bias Current
AIlS/AT
Input Bias Current Temperature
Sensitivity
TA = +125°C
TA = -55°C
2.7
ZI
Input Impedance
TA =-55°C
S5
170
40
100
kn
CMR
Common Mode Rejection
Rs<10
SO
110
70
90
db
VIR
Input Voltage Range
VCC=±15V
±8.0
±10
±S.O
±10
PSRR
Power Supply Rejection Ratio
Rs<10
Avs
Large Signal Voltage Gain
VCC=±15V
RL ;;;'2.0 kn
Vo=±10V
25
VOP
Output Voltage Swing
Vcc=±15 V
RL = 10 kn
±12
VCC=±15V
RL = 2.0 kn
±10
kn
kn
40
7-60
500
1500
nA
nA/oC
100
V
50
150
/lV/v
25
45
70
V/mV
±14
±12
±14
±13
±10
±13
70
V
IlA709
J,lA709A and J,lA709 (Cont.)
Electrical Characteristics T A = 25°C, ± 9.0 V
~ Vee ~ ± 15 V, unless otherwise specified.
J.lA709
/lA709A
Symbol
Icc
Min
Typ
Max
TA = ± 125°C
2.1
3.0
TA = -55°C
2.7
4.5
Characteristic
Condition
Supply Current
Min
Typ
Max
Unit
mA
J,lA709C
Electrical Characteristics T A = 25°C, Vee = ± 15 V, unless otherwise specified.
J.lA709C
Symbol
Characteristic
VIO
Input Offset Voltage
110
Condition
Rs";;;10
Min
kn
Typ
Max
Unit
2.0
7.5
mV
Input Offset Current
100
500
nA
lis
Input Bias Current
300
1500
ZI
Input Impedance
Icc
Supply Current
Vcc=±15V
2.7
6.66
mA
Pc
Power Consumption
Vcc=±15V
80
200
mW
CMR
Common Mode Rejection
Rs";;;10
VIR
Input Voltage Range
VCC=±15V
PSRR
Power Supply Rejection Ratio
Rs";;; 10
TR
Transient Response
50
kn
65
90
±8.0
±10
kn
50
nA
kn
250
dB
V
200
J.lVIV
Rise time
Vcc=±15V
VI =20 mV
RL = 2.0 kn
C1 = 5.0 nF
Av = 1.0
0.3
J.IS
Overshoot
R2 = 50 n
CL = 100 pF
R1 = 1.5 kn
C2 = 200 pF
Av = 1.0
10
%
The following specifications apply over the range of O°C to + 70°C.
kn
VIO
Input Offset Voltage
Rs";;; 10
10.0
mV
110
Input Offset Current
TA = O°C
750
nA
lis
Input Bias Current
TA = O°C
2000
ZI
Input Impedance
TA = O°C
Avs
Large Signal Voltage Gain
VCC=±15V
VOP
Output Voltage Swing
nA
35
80
kn
15
45
V/mV
Vcc=±15 V
RL = 10 kn
±12
±14
V
Vcc=±15 V
RL = 2.0 kn
±10
±13
V
RL~2.0
kn
Vo=±10V
7-61
pA709
Typical Performance Curves for p.A709A
Voltage Gain vs
Supply Voltage
Output Voltage Swing vs
Supply Voltage
7.
>
E
>:
RL2:2kH
I
-55°e:::; TA s +125°C
60
.
"
~
w
"~
40
0
30
zw
2.
..
9
..
g
0
1/
i-""
I
I.
,
...'"~-
fo-I-
1. 9
I
11
~
I
12
11
~
,
,
1iM
,/
14
13
VCC~±15VI
10
T, -
I
I
rfJ
-ss·c ......' ~
>
I 5 .•
w
9--
~o:~
1!
~
E
I
TA - 2SCl C
~
"w
I
02 OA 0.6 0.8
~
9
10
13
12
11
14
•
15
.. "
30
z
w
c
20
.......
"
:---.
-
r-....
I
26
"~
24
...
".....
,."c
~
Vc~"19V
I
10
-60
28
>
~Y
r-- ~~:t72'"
20
20
---
I
60
100
TEMPERATURE _
TA
/'
/
22
/
20
~
18
..~
14
., ,.
/
/
12
10
0.1
140
60
(Ie
I-
--
11
40
I
!:
-J.e1s T~ s l'25!e
10
70
..g
9
..
0
I
c
o
>
I
I
TA -125°C
,
-
5.0
12
~
~
.:t~t'-
!J
-15
-1.0 -0,8 -0.6 -0.4 -0.2
~
~
Voltage Gain vs Temperature
~
-10
10
...,11,...11 ,:;
_r-
SUPPLY VOLTAGE -
g
0
~
.;
15
I
~
...
5" -5.0
15
±V
,~
I
I
RL~lOknl
_
~,.~
I- - - ~I'~~''''\
>:-
Voltage Transfer Characteristics
15
~I'c
20
~
o
I
SUPPLY VOLTAGE -
I
I
I 25
,/
'YI I
:,...I I
I
>
L
l~~
I
30
V
I
I I
I I .J
Input Common Mode Voltage
Range vs Supply Voltage
~
9
10
11
12
13
SUPPLY VOLTAGE -
7-62
14
~V
15
\
1""'-
10
o
80
i\
20
-60
-20
20
......
60
TEMPERATURE _
100
(I
C
140
IlA709
Typical Performance Curves for pA709A (Cont.)
Common Mode Rejection Ratio vs
Temperature
11
'II
•
~
I
~
~
108
-
.....
r--..
1/
Vee ""±15V
3.0
2.0
i
....... ~
I
~
Z
V
/'
1.0
~
I
./
~
w '06
i
~
z
8 '0
•
-60
.0
-20
60
,
O.
-60
'.0
'00
!
V
•
,..
,.. -
....
t....
r-OVERLooT
:.L ..........
'.0
-
0
w 0 .•
5
w 0.'
a:
0.'
90
..
0
A
;::
70
50
()
a:
~
0
..
RISETIMf
I
O.S
1.0
1.5
2.0
•
./
./V'
30
V'
r--
TIME- ....s
~
,.
11
c
'00
'40
~
10
w
~
~
1.0
I
I--"
'0
0
!ca:
o('t~G~
V
./
'0 9
2.5
V-
,/
:I
:l
U)
Z
0
~
60
_vLLUsv
-TA-2S°C
,/
I
20
'00
V
r-TF'SOC -
~
-20
Slew Rate vs Closed Loop
Gain Using Recommended
Compensation Networks
TA == 25"C
z
I
I
f-
-50
TEMPERATURE _
110
vcc~I±,sv
I
:l
'40
'00
"C
Power Consumption vs
Supply Voltage
'-
0.8
60
TEMPERATURE -
Transient Response
50
40
.0
-20
TEMPERATURE _ °C
I"'--
50
8
0,3
o.
104
"
70
:I
m
o.5
a:
8:I
r- .........
80
z
~
~
~
90
5.0
RS~1o~n
Q 110
!ca:
Power Consumption vs
Temperature
Input Resistance vs
Temperature
,.
'3
,,
o.
's
'0
±v
SUPPLY VOLTAGE -
'00
'000
CLOSED LOOP VOLTAGE GAIN
PC05010F
Power Consumption vs
Supply Voltage (!lA709 and j.lA709C)
110
Voltage Transfer Characteristics
(!lA709 and j.lA709C)
s
LV
TA'" 25°C
,/
it
E
90
f
70
,/
:I
::>
vV'
U)
z
0
50
()
a:
w
..~
0
~"'V
I
z
1--"1-""
30
./
./
./
,/
I s.0
~
g
0
~
~
"'"
I
~
TA -125"C
fJ--II
'I
TA - 25"C
TA- -5S",?~1
>
"'~
~~\G~
V
I I
RL ==10kfl
,.
- r/I
I I
Vcc=±,svl
Input Bias Current vs
Temperature (!lA709 and !lA709C)
!Z
'I.
10
9
'0
11
,.
'3
SUPPLY VOLTAGE - =.V
,.
-'5
'5
"
-1.0 -0.8 0.6 -0.4 -0.2
~
o.6
~
o.
i
O.
a
I
0
Vee"'::t15 V
'\ o.8
J
II
-5. 0
0
•
""
O
0
0.2 0.4 0.6 0,8
INPUT VOLTAGE -
7-63
mY
1.0
~
•
60
-
t-
.0
20
60
TEMPERATURE - "C
'00
'40
MA709
Typical Performance Curves for p.A709 and p.A709C (Cont.)
Input Offset Current vs
Temperature
Input Resistance vs
Temperature
200
1.0
z
u
~
'"~
" "-
80
II:
.......
40
o
-20
-60
.i
r--.
20
60
-
100
~
0.2
"
L
o
-20
-60
140
20
>
J
"iz
=
J
/'
24
....'"
S
..'"" ,.
...
:>
>
/'
26
~
/
22
I
1/
20
0
~
18
w
""'"
~
I
"~
/
12
0.2
0.•
15
I-
10
~,
~
""", r:::-
--
~
9
10
117s
-r-
w 0.6
~
91-
o.7
O.5
125
10
11
12
13
SUPPLY VOLTAGE - :!.V
14
15
I
I
f-
0.4
II:
13
12
11
14
~
~
I
0.5
9
r-±L JveJ
$
±1~ V
~
......
w
IIEsPo
3
fj.- r- r-..
~
1.2
~
~
\.OO~6
0.8
II:
J-"
""
~t-~
~..¥
A
.- ~C~
'S~o
~tE I (00
"'8
'1"'0", l -
T' 'Ot",
17 _
0.4
o
11
12
13
7-64
14
15
~
~o,,?- I -
1.6
SUPPLY VOLTAGE - ::tV
2.5
Frequency Characteristics vs
Temperature
::~,,"OIH\OT"
10
2.0
1.5
1.0
TIME-J,ls
±V
sJIHR"TE
~ 'CiosiO
I
I
Vee ='±15V
e-TA= 25"C-
-
~ISE TIMjE
15
2.0
1
150
9
~
1
l-
c
I
0
TA "" 25°C
-r--
140
100
0
~
l!;
I
25c C
J
60
L .........
0.8
0.2
1.3
~200
20
OVERlHOOT
1.0
~:>
Frequency Characteristics vs
Supply Voltage
~225
-
5.0
1.5
TA=
~
f- - f-
I',-~\.~
~I'~~Z~(\
SUPPLY VOLTAGE -
250
.
i
20
kO
Input Bias Current vs
Supply Voltage
~
1.2
as
10
LOAD RESISTANCE -
-20
Transient Response
I
O°C:5 TA '$ +70°1
o
10
0.1
40
TEMPERATURE _
...
14
-
1.4
30
25°C
r-- l- I -
60
20
-60
140
Output Voltage Swing vs
Supply Voltage
Veej±\5~
TA
100
60
-l- i--
80
TEMPERATURE _ °C
Output Voltage Swing vs
Load Resistance
28
;8
i.
,/
TEMPERATURE _ °C
30
ii:
....... V
0.4
=;t15V
100
J
~
/
I!
ti
..i
/
J
w
u 0.6
120
~
L
i
zW
~
Vee
Vee'" ±12 V
0.8
J
II:
II:
120
VCC=±1SV
~ 160
..
:>
Power Consumption vs
Temperature
-80
-20
20
60
TEMPERATURE _ °C
100
140
MA709
Typical Performance Curves for fJA709 and fJA709C (Cont.)
Voltage Gain vs
Supply Voltage (j.LA709C)
15
aoc:s: TA $:
E
,1,
-t-70°C
R,
;;;
I
e
10
~¢~ ~
"
~"
w
:,.-- f"""
0
>
Q.
i--"
VV
~
~
50
"~
I~
>
0
9
9
~
0
z
W
Q.
0
11
""
I
:ri
w
";!g
V
40
12
13
14
15
"
~
:,.-- ......
",\..,,,,\l~
-,
- i - t9
6. 0
10
11
12
~~
--
i--'"
2.0
8
13
SUPPLY VOLTAGE -
SUPPLY VOLTAGE - ±V
4.0
Z
o
~
...- ......
8.0
w
V
30
20
o:c ~ TAI$ +~o'~
10
~
a:
"'7
10
10
,/
~
0
0
9
I
.I~~;:.-
"w
:,.--
V
1 _I 1
I
Q.
o
~ 2 kll
-55°C $ TA:::; +125°C
60
Input Common Mode Voltage
Range vs Supply Voltage
12
70
RLI~2Ikn I
>
z
Voltage Gain vs
Supply Voltage (j.LA709)
14
0
15
10
-r.V
11
12
13
14
15
SUPPLY VOLTAGE - :!:.V
PCQ5121F
Frequency Compensation Curves For All Types
Open Loop Frequency
Response For Various Values
Of Compensation
Frequency Response For
Various Closed Loop Gains
z
~
~
Output Voltage Swing vs
Frequency For Various
Values Of Compensation
>
I
28H..I+H-+..I+H~:+++
z
"~
24
~
20
Q.
I;;
o
~
9
6
'7
8.0
~
4.0
~
~
o
16
12
Q.
z
o
i!!
Co
~.OLK""'.!.J..JC-...J'-1....l..1..L""'--'-.J...J..'-'-W.ll...,...10 M
FREOUENCY - Hz
FREQUENCY - Hz
7-65
FREQUENCY - Hz
IJ.A709
Test Circuits
Transient Response Circuit
Frequency Compensation Circuit
10kO
R2(Nole 1)
CROla6(lF
Protection Circuits
Output Short Circuit Protection
Input Breakdown Protection
Rl
Rl
200n
D1
R2
CROl380F
CR01390F
Latch Up Protection
R2
Supply Over Voltage Protection
v+
Dl
Rl
EO
CRQl400F
Note
1. Use R2 = 50 n when the amplifier is
operated with capacitive loading.
7·66
J.lA714
Precision
Operational Amplifier
FAIRCHILD
A Schlumberger Company
Linear Division Operational Amplifiers
Description
Connection Diagram
8-Lead Metal Package
(Top View)
The IlA714 is a monolithic instrumentation operational amplifier constructed using the Fairchild Planar Epitaxial process. It is intended for precise, low level signal amplification applications where low noise, low drift and accurate
closed loop gain are required. The offset null capability,
low power consumption, very high voltage gain as well as
wide power supply voltage range provide superior performance for a wide range of instrumentation applications.
-OFFSET
NULL
-IN
•
•
•
•
•
•
•
•
•
Low Offset Voltage - 75 IlV
Low Offset Voltage Drift-l.0 Ilvrc Typically
Low Bias Current - ± 2.6 nA
Low Input Noise Current - 0.12 pAl VHi
at 1.0 kHz Typically
High Open Loop Gain - 500 K Typically
Low Input Offset Current - 2.8 nA
High Common Mode Rejection - 110 dB
Wide Power Supply Range - ± 3.0 To ± 22 V
Plug-In Replacement For Op-07
vLead 4 connected to case.
Order Information
Device Code
Package Code
/lA714HM
/lA714HC
tJA714EHC
/lA714LHC
Absolute Maximum Ratings
Storage Temperature Range
Metal Can
Molded DIP and SO-8
Operating Temperature Range
Extended (/lA714M)
Commercial
(IlA714C, /lA714EC, IlA714LC)
Lead Temperature
Metal Can (soldering, 60 s)
Molded DIP and SO-8
(soldering, 10 s)
Internal Power Dissapation l , 2
8L-Metal Can
8L-Molded DIP
SO-8
Supply Voltage
IlA714, IlA714C, /lA714E
IlA714L
Differential Input Voltage
Input Voltage 3
IlA714, IlA714C, /lA714E
IlA714L
>--':'VOUT
-65°C to +175°C
-65°C to + 150°C
5W
5W
5W
5W
Package Description
Metal
Metal
Metal
Metal
Connection Diagram
8·Lead DIP and SO-8 Package
(Top View)
-55°C to +125°C
O°C to +70°C
-OF1'SET
300°C
NULL
V+
265°C
OUT
1.00 W
0.93 W
0.81 W
NC
±22 V
± 18 V
±30 V
Order Information
Device Code
/lA714SG
/lA714TC
IlA714LSC
/lA714LTG
±22 V
± 18 V
Notes
I. TJ Max ~ 150°C for the Molded DIP and 50·8, and 175°C for the Metal
Can.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the BL·Metal Can at 6.7 mWrC, the 8L-Molded DIP at
7.5 mW/oC, and the 50-8 at 6.5 mWrC.
3. For supply voltage less than ± 22 V, the absolute maximum input
voltage is equal to the supply voltage.
7-67
Package Code
KC
9T
KG
9T
Package Description
Molded
Molded
Molded
Molded
Surface Mount
DIP
Surface Mount
DIP
JIA714
Equivalent Circuit
r-------_,--------~----t_--_,------~~------~----_t----_t----t_--~v+
+
OF:~~~
__ -OF:~~~ __
R2A (NOTE 1)
RIA
030t...,~.....,--+_+------+----_;----i::'-
029
C2
J,......019
'7
~
034,..r
016
C3
R9
C4
f"-f-OUT
R23
R24
R17
R18
RS
R19
R25
RIS
~~--~--~----------~~--~--~~----~v-
Note
1. R2A and R2B are electronically adjusted on chip at the factory for
minimum offset voltage
7-68
MA714
J..LA714
Electrical Characteristics TA = 25°C, Vee = ± 15 V
Characteristic
Symbol
Condition
Min
Typ
Via
Input Offset Voltage
Rs=50 n,
VCM = 0 V
30
S
Long Term Input Offset
Voltage Stability
Rs= 50 n,
VCM =0 V
0.2
Input Offset Voltage Adjustment Range
Ro= 20 kn
110
Input Offset Current
VCM =0 V
VCM =0 V
Via
adj
lis
Input Bias Current
ZI
Input Impedance
Pc
Power Consumption
1.0
3.0
60
4.0
6.0
Power Supply Rejection Ratio
Vce=±3.0 V to
±18V, Rs=50n
Ays
Large Signal Voltage Gain
nA
nA
Mn
Vce = ±3.0 V,
Vo=O V
Input Voltage Range
mW
110
126
± 13.0
±14.0
V
100
110
dB
RL;;'2.0 kn,
Vo=±10 V
200
500
V/mV
RL ;;'500 n,
Vo=±0.5 V
Vce=±3.0 V
150
500
RL = 10 kn
± 12.5
± 13.0
RL =2.0 kn
± 12.0
± 12.8
RL=1.0 kn
± 10.5
± 12.0
VCM=±13 V,
Rs= 50 n
BW
Bandwidth
Ay= 1.0
SR
Slew Rate
en
in
2.8
120
PSRR
/J.V
mV
0.4
75
VIR
Unit
/J.V/mo
Vo=O V
Common Mode Rejection
Output Voltage Swing
75
±4.0
20
CMR
VoP
Max
dB
V
0.6
MHz
RL = 2.0 kn,
Ay = 1.0
0.17
V//J.s
Input Noise Voltage
0.1 Hz to 1.0 kHz
0.35
0.6
/J.Vp-p
Input Noise Voltage Density
fo = 10 Hz
10.3
18.0
nV/YHZ
fo = 100 Hz
10.0
13.0
fo = 1000 Hz
9.6
11.0
Input Noise Current
0.1 Hz to 1.0 kHz
Input Noise Current Density
fo = 10 Hz
0.32
0.80
fo = 100 Hz
0.14
0.23
fo = 1000 Hz
0.12
0.17
7-69
14
pA p-p
pA/YHZ
JlA714
J.IA714 (Cont.)
Electrical Characteristics TA = 25°C, Vee = ± 15 V
Symbol
Characteristic
Condition
Unit
The foilowing specifications apply for Vec = ± 15 V, -55°C";; TA ,,;; + 125°C
VIO
Input Offset Voltage
AVlo/AT
Input Offset Voltage
Temperature Sensitivity1
Rs= 50 n,
VCM =0 V
60
200
Jl.V
Without
External Trim
Rs=50 n,
VCM=O V
0.3
1.3
Jl.V/oC
With
External Trim
Ro= 20 kn,
Rs=50 n
0.3
1.3
110
Input Offset Current
VCM=O V
1.2
5.6
nA
Allo/AT
Input Offset
Current Temperature Sensitivity1
VCM=O V
8.0
50
pAloC
liB
Input Bias Current
VCM =0 V
2.0
6.0
nA
AIIB/AT
Input Bias
Current Temperature Sensitivity1
VCM=O V
13
50
pArC
CMR
Common Mode Rejection
VCM=±13 V,
Rs=50 n
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Vcc = ±3.0 V to
±18 V, Rs=50 n
Avs
Large Signal Voltage Gain
VOP
Output Voltage Swing
J.IA714E
Electrical Characteristics TA
Symbol
= 25°C,
Vee
= ± 15
106
123
dB
± 13.0
± 13.5
V
94
106
dB
RL#2.0 kn,
Vo=±10V
150
400
VlmV
RL = 2.0 kn
±12.0
±12.6
Min
Typ
V
V
Characteristic
Condition
Max
Input Offset Voltage
Rs=50 n,
VCM =0 V
30
S
Long Term Input Offset
Voltage Stability
Rs=50 n,
VCM =0 V
0.3
Input Offset Voltage Adjustment Range
Ro=20 kn
110
Input Offset Current
VCM =0 V
0.5
3.8
nA
liB
Input Bias Current
VCM =0 V
1.2
4.0
nA
ZI
Input Impedance
Pc
Power Consumption
VIO
adj
CMR
Common Mode Rejection
75
Unit
VIO
Jl.V/mo
±4.0
15
mV
50
Mn
Vo=O V
75
120
Vcc=±3.0 V,
Vo=O V
4.0
6.0
VCM = ±13 V,
Rs= 50 n
7-70
106
123
Jl.V
mW
dB
J.lA714
f..LA714E (Cont.)
Electrical Characteristics TA = 25°C, Vee = ± 15 V
Symbol
Characteristic
Condition
Min
Typ
± 13.0
± 14.0
V
94
107
dB
RL;;;'2.0 kn,
Vo=±10 V
200
500
V/mV
RL ;;;'500 51,
Vo=±0.5 V
Vcc=±3.0 V
150
500
RL=10 kn
± 12.5
± 13.0
RL = 2.0 kn
± 12.0
± 12.8
RL =1.0kn
± 10.5
± 12.0
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Vcc = ±3.0 V to
± 18 V, Rs = 50 51
Avs
Large Signal Voltage Gain
VOP
Output Voltage Swing
Max
Unit
V
BW
Bandwidth
Av = 1.0
0.6
MHz
SR
Slew Rate
RL =2.0 kn,
Av = 1.0
0.17
V/p.s
en
Input Noise Voltage 1
0.1 Hz to 1.0 kHz
0.35
0.6
p.V p-p
Input Noise Voltage Density 1
fo=10 Hz
10.3
18.0
nV/YHz
fo=100 Hz
10.0
13.0
fo = 1000 Hz
9.6
11.0
in
Input Noise Current 1
0.1 Hz to 1.0 kHz
Input Noise Current Density 1
14
30
pA p-p
fo=10 Hz
0.32
0.80
pA/YHz
fo=100 Hz
0.14
0.23
fo = 1000 Hz
0.12
0.17
The following specifications apply for Vcc = ± 15 V, O°C
VIO
Input Offset Voltage
t:Nloll:.T
Input Offset Voltage
Temperature Sensitivity 1
~ TA ~
70·C
45
Rs = 50 51, VCM = 0
V
130
Without
External Trim
Rs=50 51,
VCM = 0 V
0.3
1.3
With
External Trim
Ro=20 kn,
Rs= 5051
0.3
1.3
p.V
p'vrc
110
Input Offset Current
VCM =0 V
0.9
5.3
nA
1:.1 101 I:.T
Input Offset
Current Temperature Sensitivity1
VCM =0 V
8.0
35
pA/oe
118
Input Bias Current
VCM =0 V
1.5
5.5
nA
1:.1 18 II:.T
Input Bias
Current Temperature Sensitivity1
VCM =0 V
13
35
pA/·e
CMR
Common Mode Rejection
VCM=±13 V,
Rs = 5051
7-71
103
123
dB
MA714
MA714E (Cont.)
Electrical Characteristics TA = 25°C, Vee = ± 15 V
Symbol
Characteristic
Condition
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Vcc = ±3.0 V to
± 18 V, Rs = 50 n
Avs
Large Signal Voltage Gain
RL;;;'2.0 kn,
Vo=±10V
VOP
Output Voltage Swing
RL = 2.0 kn
Min
Typ
± 13.0
± 13.5
V
90
104
dB
180
450
V/mV
± 12.0
± 12.6
Min
Typ
Max
Unit
V
MA714C
Electrical Characteristics TA = 25°C, Vee = 15 V
Symbol
Characteristic
Condition
Max
Unit
VIO
Input Offset Voltage
Rs = 50 n,
VCM =0 V
60
150
/lV
S
Long Term Input Offset
Voltage Stability
Rs = 50 n,
VCM = 0 V
0.4
2.0
/lV/mo
VIO adi
Input Offset Voltage Adjustment Range
Ro= 20 kn
110
Input Offset Current
VCM = 0 V
118
Input Bias Current
VCM = 0 V
ZI
Input Impedance
Pc
Power Consumption
8.0
6.0
1.8
7.0
33
150
Vcc= ±3.0 V,
Vo= 0 V
4.0
8.0
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Vcc=±3.0 V to
±18 V, Rs=50 n
Avs
Large Signal Voltage Gain
nA
nA
Mn
80
Common Mode Rejection
Output Voltage Swing
mV
0.8
Vo=O V
CMR
VOP
±4.0
mW
100
120
± 13.0
± 14.0
V
90
104
dB
RL;;;'2.0 kn,
Vo=±10 V
120
400
V/mV
RL;;;'500 n,
Vo=±0.5 V
Vcc=±3.0 V
100
400
RL = 10 kn
± 12.0
± 13.0
RL = 2.0 kn
± 11.5
± 12.8
VCM=±13 V,
Rs=50n
RL = 1.0 kn
BW
Bandwidth
Av = 1.0
SR
Slew Rate
RL = 2.0 kn,
Av = 1.0
7-72
dB
V
± 12.0
0.6
MHz
0.17
V//ls
J.LA714
I-lA714C (Cont.)
Electrical Characteristics TA
Symbol
en
in
= 25°C,
Vee
= 15
V
Characteristic
Condition
Min
Typ
Max
Unit
Input Noise Voltage 1
0.1 Hz to 1.0 kHz
0.38
0.65
pVp-p
Input Noise Voltage Density1
fo=10 Hz
10.5
20.0
nV/YHZ
fo=100 Hz
10.2
13.5
fo = 1000 Hz
9.8
11.5
Input Noise Current1
0.1 Hz to 1.0 kHz
0.15
35
,Np-p
Input Noise Current Density1
fo=10 Hz
0.35
0.90
pAlYHZ
fo=100 Hz
0.15
0.27
fo = 1000 Hz
0.13
0.18
Rs= 50 n,
VCM =0 V
85
250
fJ.V
Without
External Trim
Rs=50 n,
VCM =0 V
0.5
1.8
fJ.V/oC
With
External Trim
Ro= 20 kn,
Rs=50 n
0.4
1.6
The following specifications apply for Vcc = ± 15 V, O°C';;; TA < 70°C
VIO
Input Offset Voltage
I).Vloll).T
Input Offset Voltage
Temperature Sensitivity1
110
Input Offset Current
VCM =0 V
1.6
8.0
nA
1).1 101 I).T
Input Offset
Current Temperature Sensitivity 1
VCM =0 V
12
50
pArC
liS
Input Bias Current
VCM = 0 V
2.2
9.0
nA
I).lls//).T
Input Bias
Current Temperature Sensitivity1
VCM=O V
18
50
pAloC
CMR
Common Mode Rejection
VCM = ±13 V,
Rs=50 n
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Vcc = ± 3.0 V to
±18 V, Rs=50 n
Avs
Large Signal Voltage Gain
RL ;;. 2.0 kn,
Vo=±10V
VOP
Output Voltage Swing
RL = 2.0 kn
7-73
97
120
± 13.0
± 13.5
V
86
100
dB
100
400
V/mV
± 11.0
± 12.6
dB
V
JjA714
1lA714L
Electrical Characteristics TA
Symbol
= 25°C.
Vee
= ± 15
V
Characteristic
Condition
Min
Typ
Max
Unit
VIO
Input Offset Voltage
Rs=50 il.
VCM =0 V
100
250
MV
S
Long Term Input Offset
Voltage Stability
Rs= 50 il.
VCM =0 V
0.5
3.0
pV/mo
±4.0
mV
Input Offset Voltage Adjustment Range
Ro=20 kil
110
Input Offset Current
VCM =0 V
5.0
20
nA
lis
Input Bias Current
VCM = 0 V
6.0
30
nA
ZI
Input Impedance
Pc
Power Consumption
mW
VIO
adj
CMR
Common Mode Rejection
8.0
33
100
180
VCC = ±3.0 V.
Vo=O V
5.0
12
VCM=±13 V.
Rs=50 il
100
120
± 13.0
± 14.0
V
90
104
dB
V/mV
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Vcc = ± 3.0 V to
±18V.Rs=50il
Avs
Large Signal Voltage Gain
RL>2.0 kil.
Vo = ±10 V
100
300
RL>500 il.
Vo=±0.5 V
Vcc= ±3.0 V
50
150
RL = 10 kil
± 12.0
± 13.0
RL = 2.0 kil
± 11.0
± 12.8
VOP
Output Voltage Swing
RL = 1.0 kil
dB
V
± 12.0
0.6
MHz
0.17
V/MS
0.5
MV p-p
fo = 10 Hz
10.5
nV/v'Hz
fo = 100 Hz
10.2
fo = 1000 Hz
9.8
BW
Bandwidth
Av = 1.0
SR
Slew Rate
RL = 2.0 kil.
Av = 1.0
en
Input Noise Voltage 1
0.1 Hz to 1.0 kHz
Input Noise Voltage Density1
in
Mil
Vo=O V
Input Noise Current 1
0.1 Hz to 1.0 kHz
0.15
pA p-p
Input Noise Current Density 1
fo = 10 Hz
0.35
pAlv'Hz
fo = 100 Hz
0.15
fo = 1000 Hz
0.13
7-74
J.lA714
~A714L (Cont.)
Electrical Characteristics O°C ~ T A ~ + 70°C, Vee = ± 15 V
Symbol
Characteristic
VIO
Input Offset Voltage
AVIO/AT
Input Offset Voltage
Temperature Sensitivity 1
Condition
Min
Typ
Rs=n, VCM=O V
Without
External Trim
Rs=50 n,
VCM =0 V
1.0
With
External Trim
Ro= 20 kn,
Rs= 50 n
1.3
Max
Unit
400
/lV
3.0
/lV/oC
110
Input Offset Current
VCM =0 V
8.0
40
nA
AIIO/AT
Input Offset
Current Temperature Sensitivity1
VCM =0 V
20
100
pArC
liB
Input Bias Current
VCM = 0 V
15
60
nA
AIIB/AT
Input Bias
Current Temperature Sensitivity1
VCM=O V
35
150
pArC
CMR
Common Mode Rejection
VCM=±13V,
Rs=50 n
94
120
dB
VIR
Input Voltage Range
± 13.0
±13.5
V
PSRR
Power Supply Rejection Ratio
VCC = ±3.0 V to
± 18 V, Rs = 50 n
83
100
dB
Avs
Large Signal Voltage Gain
RL~2.0 kn,
Vo=±10 V
80
400
V/mV
VOP
Output Voltage Swing
RL =2.0 kn
± 10.0
±12.6
Note
1. Parameter is not 100% tested; 90% of the units meet this specification.
7-75
V
t.£A714
Typical Performance Curves
Untrimmed Offset Voltage vs
Temperature
>
90
'"
I
>
w
70
>
60
/
0
..Iii
it
50
II.
40
0
w
=>
:;l
30
I!!=>
20
>
...
0
..
i
NULLING POT: 20 kG
I
I
""!:;
k'
f.../
"'- "'-...
0
16
VIO TRIMMED TO < 5.0 /LV
I
W
V~A714C
Ycc- ±15V
R = 1000
""!:;
30
'"
/
90
JLA714~ ~A714
.....
..
0
l.P V
0
w
:3
10
w
!:i
.....5
10
"
100
50
" JotA,714
/
- ,uA714C
~
w
12
'~714E
~ 20
;!
-50
Offset Voltage Stability vs
Time
Trimmed Offset Voltage vs
Temperature
II cy
/
...
"...
~
I!
g
'1 '(I'
-8
1
100
2
3
4
5
6
7
8
9 10 11 12
TIME - MONTHS
Warm-Up Drift
25
800
~
I
w
25
~
20
~
I
z
C
-
600
~
~
~~t:&'TINE
-16
50
Offset Voltage Change Due to
Thermal Shock
p.A714
g
.
S
z
...-h ~t~&"l.~NE
-4
-12
1000
"w
~~t~&'TINE
P't:': ~~t~&"l.~NE-
:c
:t
t::
TEMPERATURE - DC
Voltage Gain vs Temperature
O.2j1.V/mo
I/TRENDLINE
I
W
~
1\ yID @, /(J)
~~\ I;, ~
50
TEMPERATURE - DC
'S
:-
~~:rimL~NE
.
>
...-r--
400
i.
I
-50
"
50
100
20
~
15
j1.A714C""
1
"71 4E,
If
!I;
15
...=>
..
10
10
i:
i:
Y
:r
0
-20
0
":c~
DEVICE IMMERSED
IN700COILBATH
20
40
60
60
100
"
TIME - SECONDS
TEMPERATURE - "C
?
u:. ;....-
w
":I!
0
w
Iii
w
z
200
TA'" 26°e
"~
!:i
i:
i:
Vee :'.,,5V
~
"'-
..-.A714
TIME AFTER POWER SUPPLY TURN-ON - MINUTES
PC05620F
Maximum Error vs
Source Resistance
Maximum Error vs
Source Resistance
> 1.0
1.0
'S
=
=
..
I
0.8
(j)
i:
g
Q
w
a: 0.6
a:
w
w
a:
a: 0.4
0
a:
a:
w
=> 0.2
..
'~"
"'"
~
1
V/l
"""~
1.0
I.
Vee: !,5V
-55°C ... TA
~ o.8
if
o
0.1
" ~A714E
• ~A714
• ,uA714C
=e
E
Vee
:15V
TA 25°C
...=>
Maximum Error vs
Source Resistance
100
MATCHED OR UNMATCHED SOURCE RESISTANCE - k!l
::s;
125°C
i:
g
fiJ
0.6
II:
a:
$a: 0.4
l!ia:
a:
w
p.A714
:E 0.2
i
;
o
0.1
1.0
i
-V
I.
/
/
Vee
g
Q
/
l/
V/
----
0.6
o
0.4
~
0.2
ffi
100
i
J.lA714C
,u.A714E
o
0.1
I
I
0.8
w
a:
a:
$
= :t15V
O"C.;;; TA';;; 7€rC
1.0
a:
a:
MATCHED OR UNMATCHED SOURCE RESISTANCE - kfl
7·76
1.2
I
1.0
-
10
100
MATCHED OR UNMATCHED SOURCE RESISTANCE - kO
J.lA714
Typical Performance Curves (Cont.)
Input Bias Current vs
Temperature
Input Bias Current vs
Differential Input Voltage
~
= :t:115V
Vee
30
illII:
20
I
a:
:>
<.>
V01FF ,,;;: 1.0 V
lis""' 3.0 nA (jj.A714)
"" 7.0 nA (;.LA714C)
r-
10
I
'"
III
~
I-
:>
~ -10
V
/
-20
~
V
-10
~
50
20
-20
TEMPERATURE _ "C
,
:::E
~
>
r-10
W
is
z
I
Rs = 0
I-
:>
:
!!!
10
a
'"~
i.O
11 0
--,
100
0.11
0.1
,.
oe
'i
!
1.0
"w
"~
TA
10
100
FREQUENCY - Hz
i\~
r'\~
10
800
> 400
o.
,
g
illo.
I
",
-r--
/'
200
1K
r- ..........
I
~
,u.A714
r'\.
III
,
100K
Open Loop Frequency Response
120
600
10K
t.OK
100
FREQUENCY - Hz
80
"
w
51
......,
!:i
0
~~;5:~5V
r'\.
40
>
o.
0
g
"-
_
'\.
~
zw
o.
\
0
0
~
1.0
i
,
90
60
1.0
100
=25"C
0
~
0
50
0.1
10
~A~'4
-
z
:;;
~
0
Q
1'\
70
, III
i
0
0
o.
III
'i:
!g 100
~
U~I= ~,~J
TA = 25 C
"ilrn
110
,,
1000
"r--r\
90
I:
*-r
BANOWIDTH - kHz
#L A714C
100
50
80
~
~AU~lJ
,,/
iJ.A714E
TEMPERATURE - "C
f-++r.,--+-ri+t7',+--+-H+-I
f=
1000
~~
-so
30
Voltage Gain vs Supply Voltage
JHJ4
~
CMR vs Frequency
'/
z
PSRR vs Frequency
a:
a:
20
120
w
FREQUENCY - Hz
U)
:>
./
II
II
100
120
'\
o.
!!! 0.5
!I
+-r:t:::l
TArTl1
1.0
1.0
",
1.0
I-
~A714
I!
J,tA714
Vee - +15V
o.
III
10
,/
1\
~A714
t;;
~
0
Vee = :t:15V
TA = 25°C
0
U)
"
!!!
Ia:
w
>
!!!
<.>
130
100
."
-10
Input Wideband Noise vs
Bandwidth (0.1 Hz to
Frequency Indicated)
RS! llRS 2 L2~ j~1::
THERMAL
NOISE OF SO~fF
~ISTORS INCLUOjD
~
EXCLUDE9
~'i;
w
~
!!!
a: 1.5
:>
DIFFERENTIAL INPUT VOLTAGE
Input NOise Voltage vs
Frequency
1000
vJ = ~lsv
2.0
30
--30
-30
100
!Zw
II:
III
l-
Z
50
§
!!
10
-a,
U)
<.>
/
/
~ -20
2.5
,
I-
z
w
a:
L'/
o.
!!!
"A71~ ~~
r- -
/
..
E
/
!!
,~
30
= ±15V
Vee
TA = 25"C
I-
"'-.,
Input Offset Current vs
Temperature
I
10K
o
o
-40
::,:5
T10
:!;15
SUPPLY VOLTAGE - V
7-77
:!;20
0.1
1.0
10
100
1.0K 10K 100K 1.0M 10M
FREQUENCY - Hz
J.lA714
Typical Performance Curves (Cont.)
Frequency Response For
Various Closed Loop Gains
'",
100
~
80
;;;
I
Z
:c
80
~
40
""'
!i!
&
9
fil
28
Vee
TA
= .z15V
=:we
p.A714
>
...'"'"
e
,.
"..'"'"
I
t-
"~"'
~~
gu
100
1.0K
10K
lOOK
1.0M
Vee = ±15V
TA = 25°C
>
I
I
1\
"
o
10M
V
I
30
...
2.
Iil
5
li:o
ill
0
o
20
40
TOTAL SUPPLY YOLTAGE, V+ to y- - v
II
II
Vee = ::t15V
TA=25"C
,\
~~
......... ~
60
20
I--
•
®
r-- ""'1"
i( i i i
cDv, (LEAD3)::>: -10 mY, Yo = +15 V
LE D3) +10 V' Vi =
5V
®V
-i
TIME FROM OUTPUT BEING SHORTED - MINUTES
7-78
0.1
1.0
LOAD RESISTOR TO GROUND - kO
p.A714
u
liE
u
/
10
-
1
L
1.0
1000
35
=:we
>=
Ie
100
Short Circuit Current vs Time
~
..
I8
..;:
NEGATIVE SWING
o
10
1
FREQUENCY - kHz
r-p.A714
100
VI= :t10mV
TA = 25"C
0
1000
E
III
pbs,LJ JJ.Jl
~~:t15~
10
I
12
.."......
Power Consumption vs
Supply Voltage
•
,.
-
I
FREQUENCY - Hz
rTA
20
:JI
~714
!i!
"\
10
24
-
20
-\.
20
Output Voltage vs
Load Resistance
Maximum Undistorted Output
vs Frequency
10
IlA714
Test Circuits
Offset Voltage Test Circuit
Optional Offset Nulling Circuit
200k!!
Ro
20kll
>-Ol-..--V+
Vo
VIO=
OUT
4~
v-
Low Frequency Noise Test Circuit
+15V
2.5M!!
Vo
Input Referred Noise ~ 25,000
7-79
MA715
High Speed
Operational Amplifier
FAIRCHILD
A Schlumberger Company
Linear Division Operational Amplifiers
Description
Connection Diagram
10-Lead Metal Package
(Top View)
The ~A715 is a high speed, high gain, monolithic operational amplifier constructed using the Fairchild Planar Epitrudal process. It is intended for use in a wide range of
applications where fast signal acquisition or wide bandwidth is required. The ~A715 features fast settling time,
high slew rate, low offsets, and high output swing for
large signal applications. In addition, the device displays
excellent temperature stability and will operate over a wide
range of supply voltages. The ~A715 is ideally suited for
use in AID and 01 A converters, active filters, deflection
amplifiers, video amplifiers, phase-locked loops, multiplexed
analog gates, precision comparators, sample-and-holds,
and general feedback applications requiring DC wide bandwidth operation.
COMP1A
vlead 5 connected to case.
• High Slew Rate -100 V/~
(Inverting, Av = 1) Typically
• Fast Settling Time - 800 ns Typically
• Wide Bandwidth - 65 MHz Typically
• Wide Operating Supply Range
• Wide Input Voltage Ranges
Order Information
Device Code
5X
5X
~A715HC
-65°C to +175°C
-55°C to +125°C
O°C to +70°C
300°C
1.07
1.36
± 18
± 15
± 15
Package Description
Metal
Metal
Connection Diagram
14-Lead DIP
(Top View)
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Extended (~A715M)
Commercial (jJA715C)
Lead Temperature
Metal Can and Ceramic DIP
(soldering, 60 s)
Internal Power Dissipation 1, 2
10L-Metal Can
14L-Ceramic DIP
Supply Voltage
Differential Input Voltage
Input Voltage3
Package Code
~A715HM
COMP1A
COMP 2B
COMP lB
y+
CASCOOE
COMP 2A
W
-IN
OUT
+IN
y-
NC
NC
NC
NC
W
V
V
V
Notes
1. TJ Max = 175°C.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 10l-Metal Can at 7.1 mWrC, and the 14l-Ceramic OIP at
9.1 mWrC.
3. For supply voltages less than ± 15 V, the absolute maximum input
voltage is equal to the supply voltage.
Order Information
Device Code
jJA715DM
jJA715DC
7-80
Package Code
6A
6A
Package Description
Ceramic DIP
Ceramic DIP
J.LA715
Equivalent Circuit
r---------~-------.----------._----------~----~~----~----~~----~--v+
R24
10 kO
lkll
R7
COMP1A
400n
R20
50 II
COMP1B
15pF
OUT
R2
R1
R27
400n
-IN
son
+IN
4000
R22
3OO11
R23
3 kit
R25
750
-+____+-____________________-+____-+____-+____
L-__
7-81
~--v-
j.lA715 and !lA715C
Electrical Characteristics TA = 25°C, Vee = ± 15 V, unless otherwise specified.
MA715
Symbol
Characteristic
VIO
Input Offset Voltage
110
Input Offset Current
Condition
Min
Rs';; 10 kil
Typ
MA715C
Max
Unit
2.0
Max
5.0
Min
Typ
2.0
7.5
mV
70
250
70
250
nA
400
750
400
1500
liS
Input Bias Current
ZI
Input Impedance
1.0
1.0
Mil
Ro
Output Resistance
75
75
il
nA
Icc
Supply Current
5.5
7.0
5.5
10
mA
Pc
Power Consumption
165
210
165
300
mW
VIR
Input Voltage Range
Avs
Large Signal Voltage Gain
RL ;;. 2.0 kil,
Vo=±10V
V
Settling Time
Vo
TR
Transient
Response
SR
IRise time
IOvershoot
Slew Rate
= ± 5.0
±10
±12
±10
±12
15
30
10
30
V
V/mV
V, Av = 1.0
800
VI = 400 mV, Av = 1.0
30
60
30
75
25
40
25
50
Av= 100
800
70
70
38
Av= 10
Av = 1.0 (non-inverting)
15
Av = 1.0 (inverting)
ns
ns
%
V/p.s
38
18
10
100
18
100
The following specifications apply over the range of -55°C';; TA';; + 125°C for the p.A715, and O°C';; TA .;; + 70°C for the
p.A715C.
VIO
Input Offset Voltage
Rs';; 10 kil
7.5
10
mV
110
Input Offset Current
TA=TAMax
250
250
nA
TA=TAMin
800
750
TA=TAMax
750
1500
TA=TAMin
4.0
7.5
lis
Input Bias Current
CMR
Common Mode Rejection
Rs';; 10 kil
74
PSRR
Power Supply Rejection
Ratio
Rs';; 10 kil
Avs
Large Signal Voltage Gain
RL ;;. 2.0 kil,
Vo=±10V
10
VOP
Output Voltage Swing
RL = 2.0 kil
±10
45
Note
1. TA - 2S·C only.
7-82
74 1
92
92 1
45 1
300
8
±13
±10
nA
db
400 1
p.VIV
V/mV
±13
V
J.lA715
Typical Performance Curves for IlA715 and IlA715C
Voltage Gain vs
Temperature (MA7l5)
Supply Voltage Rejection Ratio
vs Temperature (MA7l5)
50
'E
:-
v~c
="'5~
RL =2kO ' -
40
I
z
C
w 30
" 1"~
..g
..
g
-
ti
140
0
120
-r- t-...
~
'"w
;;J
20
"~
g
10
0
.
I\.
~
80
40
:>
20
Ii
'"
'"
"-
60
I-
15
v~c = .,5V_
-
RL
= 10kO
-.
"
:--...
w
"-
10
il
!!l
.......
r-.
'"
,.
40
-40
20
100
~
g:
25
v~c
=1 "'5~
Rs :S10kO'-
,,.
1
0 160
'z"
0
zw
200
~
Slew Rate vs
Temperature (I.lA7l5)
-40
120
TEMPERATURE _ cC
,.
40
-40
120
,.
40
TEMPERATURE _
TeMPERATURE _ °C
c
120
C
PC04610F
Common Mode Rejection Ratio
vs Temperature (pA7l5)
11 0
Voltage Gain vs
Temperature (pA7l5C)
v:x,
=''''5~
Rs~10kO'-
'Il
I
Q 100
Ii
RL=2kO
90
~
8
g
70
0
"
w
r--..
/
..g
..
g
-
30
40
40
80
TEMPERATURE _
cC
20
30
40
50
110
=
Vee
~15V
RL = 10kH
vdc= "j5V
18
I
Rs S10kO
25
20
w
ul
-
2100
~
r--
15
10
-
'z"
~
;;J
l!:'"
90
-
r-
,.
~
z
o
~
70
8
o
60
0102030405060
TEMPERATURE _
cc
70
............
.......... r-..,
~
40
~
20
010203040
TEMPERATURE _
7-83
50
cc
o
o
10
20
30
-40
TEMPERATURE _
Ii
'~"
70
60
Common Mode Rejection Ratio
vs Temperature (pA7l5C)
35
30
10
TEMPERATURE _ °C
Slew Rate vs
Temperature (pA7l5C)
I'..
60
;;J
~
00
120
~
g
10
0
60
ti
'"z
'"
20
0
zw
~~=1:k~V-
I
o ,.
"~
j
8
Ii
100
~
-
40
~
r-.
I-"'"
8'"
..
'E
:-
VC~ = .'~V
I
'"
~
50
Supply Voltage Rejection Ratio
vs Temperature (MA715C)
60
70
50
"c
60
70
I1A715
Typical Performance Curves for j.iA715 and j.iA715C
Frequency Response For Open
Loop Gains (Note 1)
120
Frequency Response for
Closed Loop Gains
80
=
~
100
:c
Z
80
~
60
"w
g
..
S
..
ill
:;::::
"
40
"I
'w"
~-
"";"-r-,
'"
~
.."
§
40
['\1'\
20
:c
IIII
r-..
10K
I
!'"
...
..."
..
"0
"
~
0
to;
~"
z
w
1.0M
lOOK
z
0
;:
60
Iia:
r\
It
II
GAIN 1
II
20
I
15
"~
0
.....
40
GAIN 100
\
w
-'
1\
~ -240
0.01
to
0.1
\
-400
0.001
10
0.01
"
1.0
20
10
50
MHz
6.0
VCC"" ±15 V
TA "" 2S"C
5.0
>
I
4.0
w
I
'~"
1\
\
I
II
1.0
Large Signal Pulse Response
for Gain 10
\
I
0.1
FREQUENCY -
Vee = ±15 V
TA = 25°C
'I\.
3.0
2.0
0
z
0
:>!
:>!
0
m -80
-320
I-
:>
0
:>!
=
=
Vee
:t15V
TA 25"C
NOCOMP
'\
-160
GAIN 10
0
>
100M
10
> 4.0
I
w
;oJ
10M
Hz
S
~
I I
5.0
"
1.0M
r...
6.0
VC~I~ :t15V
TA 25"C
""; lCOMP
lOOK
10K
Open Loop Phase vs
Frequency
Unity Gain Large Signal Pulse
Response
M
a:
w
1.0K
FREQUENCY -
RL = 10kn1: =25"C
kHz
=
80
o
SOM
FREQUENCV - MHz
Common Mode Rejection Ratio
vs Frequency
0
10M
Hz
Vcc- .:t15V
25
0.001
100
20
0
o
~
I
\
40
0
30
FREQUENCY -
.
S
.
.\
0
Output Swing vs Frequency for
Closed Loop Gains
>
"
80
>
FREQUENCY -
Hz
Supply Voltage Rejection Ratio
vs Frequency
"w
<
'"
!:;
IIII
IIII
-20
1.0K
-~.o':-:'KWJ."'--::1O~K..J.J.'-::100::-:K,.u-'-:'1.~OM:,:-,-.u...='0::-M';->-~50·M
80
I
GAI~\
w
Vdc;
±15V
TA=25"C
NOCOMP
Z
IIII
9
"
1'\['\
FREQUENCY -
G~,'~\oci
['\
G~'~ \0
>
Q
w
.."
IIII
0
r\
20
0
=250C
TA
GAIN 1000
60
~
'14
~I
'k~o~
0
Z
OJ
100
tc~~ l,dv'
1111
Vee
:t15V
TA'" 25°C
Voltage Gain vs Frequency
I
I
3.0
g
~
o
2.0
\
to
\
0
0
-1.0
0.01
0.1
1.0
FREQUENCY -
10
kHz
100
500
o
400
800
TIME -
1200
AS
Note
1. See "Non-Inverting Compensation Components Value Table" for Closed Loop Gain values.
7-84
1500
-t0
200
400
600
800 1000 1200 1400 1600
TIME-ns
MA715
Typical Performance Curves for j.LA715 and j.LA715C (Cont.)
Large Signal Pulse Response
for Gain 100
6.0
24
100
Vee = :t15V
RL = 10kG TA = 25°C
Vee'" :r15 V
TA:=: 25"C
5.0
>
I
I
4.0
80
~
w
"~
3.0
>
::>
2.0
I
..
0
.
/
80
~
w
w
~
Ii:
0
...
...::>
Slew Rate vs
Supply Voltage
Slew Rate vs
Closed Loop Voltage Gain
'"
~
1.0
-1.0
\
o
200
400
600
800
/'
40
o
2.0
TA
Il
o J. it
o
~ RISoj TIME
50
150
-4.0
It..
y
-6.0
200
250
300
350
-400
-400
400
TIME-ns
Voltage Follower (Note 1)
22
v
~~N==2::mv -
\
\\
1
'O%
100
18
VC~= "'~V
~ -2.0
~
14
Small Signal Pulse Response
Inverting Unity Gain
~
o
10
SUPPLY VOLTAGE -
= 250C
I
~
200
100
6
f-~=I"'5IV
>
IV
I'
,/
o
o
100
Inverting Unity Gain Large
Signal Pulse Response
v~ = "'~V
90%"~
12
~
10
1
VIN = 400niV TA = 25c C
II \
V
/
CLOSED LOOP VOLTAGE GAIN
Voltage Follower Transient
Response
500
16
~
~
/
20
1000 1200 1400 1600
700
I-- T,I=..l·c
RL = 10kG
I-- NOCOMP
",..
TIME- ns
600
20
800
1200
I\IJ
IV
1600
180
Voltage Offset Null Circuit (Note 1)
480
320
TIME-ns
TIME-ns
High Slew Rate Circuit (Note 1)
y+
5kH
V+
FD100
50kH
OUT
+
5
7
~lr.onF
-15 V
2.5kfl
y-
Note
1. Lead numbers apply to metal package.
7-85
JiA715
Non-Inverting Compensation Components Values
Frequency Compensation Circuit
C1
Closed
Loop
Gain
C1
1000
C2
C3
10 pF
100
50 pF
250 pF
10 (Note)
100 pF
500 pF
1000 pF
1
500 pF
2000 pF
1000 pF
Note
For gain 10, compensation may be simplified by removing C2, C3 and adding a
200 pF capacitor (C4) between lead 7 and 10.
Note
lead numbers apply to metal package.
Suggested Values of Compensation Capacitors vs
Closed Loop Voltage Gain
Vee
%1000
C3
= ±15V
C2
\
I
w
(J
Z
i$
13
if
~ 100
".
c>. .... ....c,
.....
I-
c.
CLOSED LOOP VOlTAGE GAIN
Layout Instructions
Large source resistances may also give rise to the same
problem and this may be decreased by the addition of a
capaCitance across the feedback resistance. A value of
around 50 pF for unity gain configuration and around
3,0 pF for gain 10 should be adequate.
Latch Up - This may occur when the amplifier is used as
a voltage follower. The inclusion of a diode between leads
6 and 2 with the cathode toward lead 2 is the recommended preventive measure.
Layout - The layout should be such that stray capacitance
is minimal.
Supplies - The supplies should be adequately bypassed.
Use of 0.1 fJ.F high quality ceramic capacitors is recommended.
Ringing - Excessive ringing (long acquisition time) may occur with large capacitive loads. This may be reduced by
isolating the capacitive load with a resistance of 100 n.
7-86
JlA715
Typical Applications
Wide Bank Video Amplifier
Drive Capability With 75 .n Coax Cable
,.
+20 V
VIDEO OUTPUT
TO 75 !l COAX
7Sfl
""'\
fl
-10
I
o dB =
z
~
"
\
255 mVpfI:- pice
5~
pk- pitt
-20
7500
10k!!
\
-30
75 !l
r--Sikii-'
NOISE OUT'" 2 mV RMS
'. pk _ ~k SIG/R~S NOISE, " 42 dB
..... ....
-40
0.'
FREQUENCY -
100
10
1.0
MHz
I
I""
1
L _____ --l
EQUIVALENT CIRCUIT
FOR IMAGE ORTHICON
51 kH
-20V
High Speed Integrator
SOpF
20
10 kO
10 kO
15
I
10
./NPUT /
>
I
~o~
\
1\
-s
-10
I
\
/
~
\
/
5.0 k!l
.L
IN
OUT
°r !,
p
s
-20
•
1.0
2.0
s.onF
+15 V
\
2.5k!l
3.0
4.0
soon
5.0
-15 V
TIME-J.(s
Note
All lead numbers shown refer to metal package.
7-87
IlA725
Instrumentation
Operational Amplifier
F=AIRCHILD
A Schlumberger Company
Linear Division Operational Amplifiers
Connection Diagram
8-Lead Metal Package
(Top View)
Description
The p.A725 is a monolithic instrumentation operational amplifier constructed using the Fairchild Planar Epitaxial process. It is intended for precise, low level signal
amplification applications where low noise, low drift, and
accurate closed loop gain are required. The offset null capability, low power consumption, very high voltage gain as
well as wide power supply voltage range provide superior
performance for a wide range of instrumentation applications. The p.A725 is lead compatible with the popular
p.A741 operational amplifier.
-OFFSET
NULL
• Low Input Noise Current- 0.15 pAlYHz
At 1.0 kHz Typically
• High Open Loop Gain - 3,000,000 Typically
• Low Input Offset Current - 2.0 nA typically
• Low Input Voltage Drift - 0.6 p.V
typically
• High Common Mode Rejectlon-120 dB
• High Input Voltage Range-±14 V Typically
• Wide Power SUpply Range - ± 3.0, V To ± 22 V
• Offset Null Capability
v-
rc
Order Information
Device Code
p.A725HM
p.A725HC
p.A725AHM
p.A725EHC
Absolute Maximum Ratings
Storage Temperature Range
Metal Can
Molded DIP
Operating Temperature Range
Extended (p.A725AM, p.A725M)
Commercial (p.A725EC, p.A725C)
Lead Temperature
Metal Can (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1, 2
8L-Metal Can
8L-Molded DIP
Supply Voltage
Differential Input Voltage
Input Voltage3
Voltage Between Offset Null and V+
, COO",."
Lead 4 connected 10 case.
-65·C to + 175·C
-65·C to + 150·C
Package Code
5W
5W
5W
5W
Package Description
Metal
Metal
Metal
Metal
Connection Diagram
8-Lead DIP
(Top View)
-55·C to + 125·C
O·C to +70·C
300·C
265·C
+OFFSET 1
NULL
1.00 W
0.93 W
±22 V
±5.0 V
±22 V
±0.5 V
-OFFSET
NULL
-IN
V+
+IN
OUT
v-
FREQ
caMP
Order Information
Notes
1. TJ Max -150°C for the Molded DIP, and 175°C for the Metal Can.
2. Ratings apply 10 ambient temperature at 25°C. Above this temperature.
derate the 8L-Metal Can at 6.7 mWrC. and the BL-Molded DIP at
7.5 mWrC.
3. For supply voltsges less than ± 22 V, the absolute maximum input
voltage is equal 10 the supply voltsge.
Device Code
p.A725TC
7-88
Package Code
9T
Package Description
Molded DIP
Equivalent Circuit
tI
R2A
+ OFFSET
I
10kn
+
-'W'v-
NULL
"
R2B
10 kll
t
R3
RlO
29 k!l
300 !l
t
V+
-OFFSET
NULL
100 k!!
R1A
EXTERNAL
42 kll
R16
25 n
+IN
-£
01
OUT
-.J
cD
co
-IN
--+--------'
R19
4.5 k!l
016
>
R6
RS
5.1 k!l <> 2.4 kll
R18
R12
R13
5.1 kn
1 kn
150 II
R14
300 !~
~--------------~----~----~--~-------+---+---4----------~--~----4-------~--v-
fJ.A725
JJ.A725A/E and J.lA725
Electrical Characteristics TA = 25°C, Vee = ± 15 V, unless otherwise specified.
pA.725A1E
Symbol
Characteristic
Vlo
Input Offset Voltage
(Without external trim)
110
Input Offset Current
lis
Input Bias Current
ZI
Input Impedance
Pc
Power Consumption
Condition
Typ
Min
Rs<10 kn
pA.725A1pA.725
80
Max
Unit
0.5
0.5
1.0
mV
5.0
2.0
20
nA
42
100
1.5
120
80
nA
Mn
120
mW
6.0
120
130
± 13.5
±14
Common Mode
Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection
Ratio
Rs< 10 kn
Avs
Large Signal Voltage
Gain
RL;;o.2.0 kn,
Vo=±10V
1000
VOP
Output Voltage Swing
RL = 10 kn
RL = 2.0 kn
in
Rs<10 kn
Typ
150
CMR
Input Noise Current
Min
75
Vcc=±3.0 V
en
Max
1.5
pA.725E
Input Noise Voltage
pA.725
2.0
110
120
± 13.5
±14
5.0
2.0
dB
V
10
INIV
1000
3000
V/mV
± 12.5
±12
±13.5
V
±10
±10
± 13.5
3000
fo = 10 Hz
15
15
15
fo = 100 Hz
9.0
12
9.0
fo = 1.0 kHz
8.0
12
8.0
fo = 10 Hz
1.0
1.2
1.0
fo = 100 Hz
0.3
0.6
0.3
fo = 1.0 kHz
0.15
0.25
0.15
The following specifications apply over the range of O°C < TA <
and pA.725.
Input Offset Voltage
(Without external trim)
Rs < 10 kn
0.75
.£lVlo/.£lT
Input Offset Voltage
Temperature Sensitivity
(Without external trim)
Rs = 50 n
2.0
.£lVlo/.£lT
Input Offset Voltage
Temperature Sensitivity
(With external trim)
Rs=50 n
0.6
110
Input Offset Current
TA=TAMax
5.0
7-90
pAlYHz
+ 70°C for /JA 725E, - 55°C < TA < + 125°C for /JA 725A
VIO
TA=TAMin
V
nV/YHz
2.0
2.0
1.5
mV
5.0
/JV/ o C
0.6
/Jvre
4.0
1.2
20
18
7.5
40
nA
IlA725
Jl.A725A/E and Jl.A725 (Cont.)
Electrical Characteristics Vee=±15 V.
and Jl.A725.
O°C~TA~+70°C for Jl.A725E. -55°C~TA~+125°C for
IlA725A/E
Symbol
Characteristic
Condition
Min
Typ
Jl.A725A
IlA725
Max
Typ
Min
Max
Unit
pA/oC
dllO/dT
Input Offset Current
Temperature Sensitivity
118
Input Bias Current
CMR
Common Mode
Rejection
Rs~lO kil
PSRR
Power Supply Rejection
Ratio
Rs~lO
Avs
Large Signal Voltage
Gain
RL;;;'2.0 kil.
TA=TAMax
1000
1000
V/mV
RL;;;'2.0 kil.
TA = TA Min
500
250
V/mV
RL = 2.0 kil
±10
±10
V
35
TA=TAMax
Output Voltage Swing
35
70
20
100
80
200
180
TA = TA Min
VOP
90
110
kil
nA
nA
100
dB
20
8.0
IlVN
Jl.A725C
Electrical Characteristics T A = 25°C. Vee = ± 15 V. unless otherwise specified.
Symbol
Characteristic
VIO
Input Offset Voltage
(Without external trim)
110
Input Offset Current
118
Input Bias Current
en
Input Noise Voltage
Condition
Input Noise Current
Typ
0.5
to = 10 Hz
to=
in
Min
Rs~ 10 kil
mV
2.0
35
nA
42
125
9.0
to = 1.0 kHz
8.0
to = 10 Hz
1.0
to = 100 Hz
0.3
to = 1.0 kHz
0.15
Input Impedance
VIR
Input Voltage Range
Avs
Large Signal Voltage Gain
RL ;;"2.0 kil.
Vo=±10V
CMR
Common Mode Rejection
Rs~10
kil
PSRR
Power Supply Rejection Ratio
Rs~lO
kil
VOP
Output Voltage Swing
RL = 10 kil
±12
± 13.5
RL = 2.0 kil
±10
± 13.5
pAlYHz
1.5
Mil
± 13.5
±14
V
250
3000
V/mV
94
120
2.0
80
7-91
nA
nV/YHz
15
100 Hz
Power Consumption
Unit
2.5
ZI
Pc
Max
dB
35
IlVN
V
150
mW
p.A725
/lA725C (Cont.)
Electrical Characteristics QOC';;; T A .;;; + 7QoC, Vee = ± 15 V, unless otherwise specified.
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
VIO
Input Offset Voltage
(Without external trim)
Rs';;;10
kn
t:.Vlol t:.T
Input Offset Voltage Temperature
Sensitivity (Without external trim)
Rs=50
n
2.0
pV 1°C
t:.Vlolt:.T
Input Offset Voltage Temperature
Sensitivity (With external trim)
Rs= 50
n
0.6
pV/oC
110
Input Offset Current
TA=TAMax
1.2
35
TA=TA Min
4.0
50
t:.IIOI t:.T
Input Offset Current Temperature
Sensitivity
liB
Input Bias Current
3.5
TA=TAMax
125
TA = TA Min
250
Avs
Large Signal Voltage Gain
RL>2.0
Common Mode Rejection
Rs';;; 10
PSRR
Power Supply Rejection Ratio
Rs';;; 10
VoP
Output Voltage Swing
RL = 2.0
7-92
kn
kn
kn
kn
nA
V/mV
125
±10
nA
pArC
10
CMR
mV
115
dB
20
/lVIV
V
pA725
Typical Performance Curves
Voltage Gain vs Temperature For
Supply Voltages For p.A725/A
140
.......l-I-'"
ID
z
~
"'"
~
.
g
~z
~
..
:::. 100
Vee - :15V
I
Vee = :t10Y
--r-
I 120
Untrimmed Input Offset Voltage
vs Temperature For p.A725/A
1.0
.1 'LII"
"c<;""'?
...
Change In Trimmed Input Offset
Voltage vs Temperature For p.A725/A
Vee
I
±5V
AL
O!:
~
2 ItO
100
o
i-
:
~~~ :,,~s.~ 25 J
50
-
0
V
..
! -so
!
co
..
... V
~
0.8
~
0.4
~!
20
100
80
140
20
-20
-60
100
60
...... 1"'"
0.2
o
140
-60
-20
Voltage Gain vs Temperature for
Supply Voltages For p.A725C/E
20
140
100
60
TEMPEAATURE _ ·C
TEMPERATURE - ·C
TEMPERATURE _ °C
V
i--""
........ ........
o
U
-20
........
g
!-100
80
-80
Vee= :t15V
0.8
I
./
I--'"
~
80
'r!
0
Trimmed Input Offset Voltage vs
Temperature For p.A725C/E
Untrimmed Input Offset Voltage
vs Temperature For p.A725C/E
140
1.0
Vee = :t2DY
i
Vee
I
..~
~
..g
9
..
= :t15V
±10V_
Vee
z 120
Vee - :t:15V
f--
-
Yos:s S"Vat2S°C
-- -
Vee - :t5V
o~ r-
100
0
z
AL:it: 2kO
80
o
20
10
30
40
50
60
10
70
·c
TEMPERATURE -
20
30
40
50
TEMPERATURE -
60
70
Vee
= :t15V
0.8
I
'"
~
~
.
!;
!
80
0
'r!
--
0.8
f0- r-OA
f-- ~
0..2
0
10
20
·c
30
40
50
60
70
TEMPERATURE - °C
"""70'
Input Offset Current vs
Temperature For p.A725/A
Input Bias Current vs
Temperature For p.A725/A
Input Offset Current vs
Temperature For p.A725C/E
100
8
~
7
vJ, = ±15V
\
\
r\
3[""'--.
l"-
2
I"-20
20
100
·c
140
0
10
"
-
...........
1
60
TEMPERATURE _
&.
1\..'" ~
4
1
o
~
5
\
-60
,
Vee = .:t1SV
5
20
30
~
Vee =
20
:t10~~ ~
Vee
40
50
60
70
TEMPERATURE - ·C
0
-80
-20
20
= :t5V
.......
100
60
TEMPERATURE "",.9OF
7-93
Vee= :t20V
~vcc=:t15V
·c
140
MA725
Typical Performance Curves for all Types (Cont.)
Input Bias Current vs
Temperature !1A725C/E
Power Supply Rejection
Ratio vs Temperature
Common Mode Rejection
Ratio vs Temperature
."
100
10
Vee
= :1:15V
VCC=::t15V
6 120~-=r=p.,..-t-I-+-+-I=r-j
~z
9 1001-+--+-1-+-+-+-1-+-+-1
~
~ ~20V
:----+:-:3
~
cc
r-r t
=
0
~
Vee = :t15V
~
o
801-+-+-+-+--1--!--+-1-+-I
:&
OV
z
~
Vcc= ±5V
~
80~~-+-+--+~-~-+-~~-;
8
10
30
20
50
40
80
o
70
-60
TEMPERATURE _ "'C
vccl = l'5J
."
.
0:
0
0
:&
1 I
1 1
.
80
20
80
,00
140
"
AVCL! 10000
iffi
1
AVCL - 1000
0.01
z
0
:&
:&
0
TA = 25"'C
~
;;J
1
VC~ = .sv
1.0
I
z
;:: 100
1
t.
.. o.
~
g
.
9
z
l
-20
~
120
0
Vcc== :t10V
RL O!! 2k!l
140.--.,..---..,---,---r--,---,
TA = 25°C
0:
I
I
.."
I
1 1
o
60
40
!"
Q
15
10
5
TEMPERATURE _oc
20
AVCL
= 100
0.001
1,0
10
100
1.0 K
10 K
100 K
1.0 M
SOURCE RESISTANCE- 11
SUPPLY VOLTAGE - :tV
Stabilization Time of Input
Offset Voltage From
Power Turn-On
Input Offset Voltage Drift vs
Time
Common Mode Input Voltage
Range vs Supply Voltage
100
60
DC Closed Loop Voltage Gain
Error vs Source Resistance
Common Mode Rejection Ratio
vs Supply Voltage
= ::t20V
20
TEMPERATURE _ °C
TEMPERATURE _ °C
Output Voltage Swing vs
Temperature
Vee
20
i--
50
TA! 25°C
,/
V
:0;.
.."s
/
8
....
...."
.
."
0
.,......
>
/V
i!!
i!!
:I:
15
SUPPL V VOLTAGE -
20
:tv
"
~
PREVIOUS VIO :::; 1 p,V
-
g
30
tij
20
!2...
o
!;
..
20
10
1\
i!!
.
i!!
10 ~ r-
Z
10
Vee == ± 15 V
TA == 25"C
.. 30
we
VIO~20p.YATt=O
0
,/
./
0
I
YCC=±1SV
TA =
40
~E
"~
"
0
i"10N
:I:
/'
200
400
600
TlME-HRS
7-94
800
1000
TIME FROM POWER APPLICATION - MIN
MA725
Typical Performance Curves for all Types (Cont.)
Change In Input Offset Voltage
Due to Thermal Shock vs Time
Input Noise Current vs
Frequency
Input Noise Voltage vs
Frequency
.
lit"
10'" r-rrrr-'-TTTr-r-rTTT-r-r"TT"
Vee
N
:I:
,
>
1 10'"
g
;!;
;!;
w
a:
a: 1....
I,
i3w
10-n
W
."..
!II
!II
fi lOw
0
Z
11
w 10.
a:
a:
"'0"
'z"
0
"
'" -10
1_
Z
tAPPLY
10""
80
20
TIME FROM HEAT APPLICATION -
100
'"
10'"
'"
10
100
lOOK
10 K
1.0 K
Narrow Band Spot Noise Figure
Contours
!
g
10
.."
/'
10Hz
~
i
1.0
1
I-
~
!II
0
z
I--
Il'I"znir
o. 1
100
1.0 K
100
~
~
10
10
± 15 vt=~=fI\VCL = 1
Vee
TA = 25°C
=f1
EXTE~~~;EC~~L~~:EMIOE
~o
'"6z
1/
1()2
>
PEAK-To-PEAK
~
10
5
1
10
1.0 K
10 K
FReQUENCY - Hz
100 K
~t'l,
'~~~
~ f$:~
10
,,<>~
,<>
~
5
1111
1/
100
V
!zw
IIX
&1
1.0 M
/
POWER SUPPLY
RIPPLE VOLTAGE
a:
5
10mV
V
IJ J
10 2
8:
~
&1
I I I
~
IV
100mV
~
-
/
1
1
/
FREQUENCY - Hz
7-95
/
'-
~
~<--,
Y~
/IA
"r.y
100
10
1\
o
100
1.0 K
10 K
SOURCE RESISTANCE - 0
FREQ COMPENSATIONrr-Vcc = ± 15 v--j-ti Avec = 1
f-I--- T A = 25"C
W
;!;
!Ew
,
w
10V
w
10'
1()4
Equivalent Input Ripple Voltage
Due to Power Supply Ripple vs
Frequency
I II'FREQ COMPENSATION
g
10'
FREQUENCY - Hz
=
1
w
"
I
I III
10'
I)
Equivalent Input Noise Voltage
Due to External Common Mode
Noise vs Frequency
10'
'5
TA = 25°C
f = 1kHz
1\
.......
~~'?rtH ....111
10
100 K
10 K
SOURCE RESISTANCE -
Hz
vJl LI
\
\
""u:w
,/
10Hz-10kHz
'"5z
100 K
10 K
1.0 K
1
w
100kHz
I
100
10
a:
w
e'"
10
12
25°C
a:
w
10"'
,.
Q
~
10"'
Noise Figure vs Source
Resistance
100
.5
!'..
.
FREQUENCY -
{ = vW.J.v
=
1
.......
FREQUENCY - Hz
S
Broadband Noise for Various
Bandwidths
TA
.
i5
w
0
-20
"lilz'"
'"
:I:
:t:15V
25'C
ffi
w
"!:;'"
TA
1.0K
-I"""'"
100 K
flA725
Typical Performance Curves for all Types (Cont.)
Power Consumption vs
Temperature
160
........
140
~
I
z
2
l;:
100
~
80
i-
"
8
0
~
40
-- -
Open Loop Frequency Response
For Values of Compensation
a:
-- -
00
±20V
..".
~
.gg
z
~-
J10J-
20
-20
R1 == 10kn C1
80
I III
60
"
;!
40
..
~
§
c
~
20
R1 = 470 C1
-Rl '= 27rl
R2
-:=
r-
= .01p.F
= .05,F
I
JJ, = .JS,F
10'
I III
I III
I I II
"\.
1
o
1
10
H~
10'
10'
1
10'
CLOSED LOOP VOLTAGE GAIN
Output Voltage Swing vs
Frequency
Slew Rate vs Closed Loop Gain
Vee == ±15V
TA == 25°C
R2 = ail? C2 == .02J.1F
-20
100
10
FREQUENCY -
I
I
I
=="Vcc= ±1SV
10
..........
..........
~I
"
w
"'
270 n C2 :::; .0015/iF
f-Rl l= ,~
0
J,
I-R~
0:
"c
= .001 jtF
1 I
I III
"
-
100
R2_
100
SOpF
I T
R1 == 4700 C1
~
-=
'Ii
1 .OK~
Z
~
Frequency Response for Various
Closed Loop Gains
!1j
I
10K
/
.,.
1.0K
140
100
60
TEMPERATURE _
~'
",-C2
"
f3~
z
rT
-
C>
~
o
Vee - ±5V
0
-60
.'"
10
!g
I
vcd=
0
lOOK
100.
Rl =
':::'::"6 =
120
Values for Suggested
Compensation Networks vs
Various Closed Loop Voltage
Gains
:
~
"' "'
r-..... ......
o. 1
'V
10
10
10'
10
FREQUENCY -
FREQUENCY - Hz
Compensation Component Values
Cl
(J.lF)
V
I
0.0
10'
Rl
1.0
,/
800
> .....-..,....-vo
E
I
90%
w
I
;400
g
~
150 pF
~O.,/-1F
I'
Vee
10·
!;
o
= ::r1SV
TA=2S0C -
V
RL
= 2 kU
C,= l~rAT =1100
RljETljE
-400
TIME-I-'s
Typical Applications
Precision Amplifier AVCL = 1000
SOMn
500kn
500kn
10kn
90kn
~~----EO
Characteristics
Av= 1000=60 dB
DC Gain Error = 0.05%
Bandwidth = 1 kHz for -0.05% error
Diff. Input Res. = 1 Mfl
Typical amplifying capability
e n =10 MV on VCM=I.0 V
Caution: Minimize Stray Capacitance
Active Filter -
Band Pass With 60 dB Gain
Active Filter Frequency Response
C,
100
Av= (AV' DC)(2+¥C')(
R3
1
)
R3 + Rs + i27rloC3
80
I
t!
I
z
~
fI\
Rx=Ry
w
g
I
60
~
Eo
I
11
&..fo=
40
211'RxC)I..;c;iCx
Q =
1
1/2 ..;c;iCx
VI\
II
20
'{DC GAIN
R)l+R y +R4
Av. DC = 1 + --R-S-to X 10-2
fo X 10-1
10
Tl=2S0 C
foX10
NORMALIZED FREQUENCY
Lead numbers are shown for metal package only.
7-97
fo X 102
J.LA725
Typical Applications (Cont.)
Photodiode Amplifier (Note 2)
R4
C1
100 !l (NOTE 1)
~_N......-l0,000
t-""7.;:-::;-"""M.--~....,r--"""",,,f.kl~l-l,ooo
:;'~~E
T I~SELECT
~U
R3
10
10
lOOkU
(NOTE 1)
(NOTE 1) CALIBRATE
':"
R14
100 n
(NOTE 1)
-15 V
DC GAINS ~ 10,000; 1,000; 100; AND 10
BANDWIDTH ~ DETERMINED BY VALUE OF Cl
AF00541F
Thermocouple Amplifier (Note 2)
± 100 V Common Mode Range Differential Amplifier
(Note 2)
Cl
SOOpF
Rl
SOkn
R2
R3
5 kll
511 kO
(NDTE 1)
R4
>'-1-W'w-.....- OUT
REFERENCE
THERMOCOUPLE
R4
5 kH
IN
2000
C2
lOOpF
-::R7
R3
511 kH
(NOTE 1)
RBI :
pF
510n
SDk!!
I; = II 'or be.' CMR
+
>~...,...--OUT
Rl = R4
-::-
R2=R5
Gain
39!!
= RI + ( : ' )
5 kll
DC GAIN = 1000
BANDWIDTH =DC TO 540 Hz
EQUIVALENT INPUT NOISE = 0.24 pVrms
-::-
Notes
1. Indicates ± 1% metal film resistors recommended for temperature
stability.
2. Lead numbers are shown for metal package only.
7-98
IlA725
Typical Applications (Cont.)
Instrumentation Amplifier With High Common Mode Rejection (Note 1)
R2
10 kU
39
n
Rl
47 kil
AS
100
k!)
OUT
IN
270
R3
10 kfl
n
R5
10 kll
39
n
R7
lOOk£!
-=
R1
R3
R6
R4
- =-
for best CMRR
R3=R4
R1 =R6=10 R3
R6
Gain=R7
Note
1. Lead numbers are shown for metal package only.
7-99
MA741
FAIRCHILD
Operational Amplifier
A Schlumberger Company
Linear Division Operational Amplifiers
Description
The !LA741 is a high performance monolithic operational
amplifier constructed using the Fairchild Planar Epitaxial
process. It is intended for a wide range of analog applications. High common mode voltage range and absence of
latch up tendencies make the !LA741 ideal for use as a
voltage follower. The high gain and wide range of operating voltage provide superior performance in integrator,
summing amplifier, and general feedback applications.
Connection Diagram
8-Lead Metal Package
(Top View)
NC
>-~OOUT
-IN
•
•
•
•
No Frequency Compensation Required
Short Circuit Protection
Offset Voltage Null Capability
Large Common Mode And Differential Voltage
Ranges
• Low Power Consumption
• No Latch Up
vLead 4 connected to case.
Order Information
Absolute Maximum Ratings
Device Code
Storage Temperature Range
Metal Can and Ceramic DIP
Molded DIP and SO-8
Operating Temperature Range
Extended (!LA741 AM, !LA741M)
Commercial (!LA741EC, !LA741C)
Lead Temperature
Metal Can and Ceramic DIP
(soldering, 60 s)
Molded DIP and SO-8
(soldering, 10 s)
Internal Power Dissipation 1, 2
8L-Metal Can
8L-Molded DIP
8L-Ceramic DIP
SO-8
Supply Voltage
!LA741 A, !LA741 , !LA741E
!LA741C
Differential Input Voltage
Input Voltage 3
Output Short Circuit Duration 4
!LA741HM
!LA741 HC
!LA741AHM
!LA741EHC
-65°C to + 175°C
-65°C to + 150°C
-55°C to + 125°C
O°C to +70°C
mwrc.
Package Description
Metal
Metal
Metal
Metal
300°C
265°C
1.00
0.93
1.30
0.81
+OFF$ET
NULL
NC
-IN
v+
+IN
OUT
W
W
W
W
v-
±22 V
± 18 V
±30 V
± 15 V
Indefinite
-OFFSET
NULL
Order Information
Device Code
!LA741RM
!LA741RC
!LA741SC
!LA741TC
!LA741 ARM
!LA741 ERC
!LA741 ETC
Can and Ceramic DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the BL-Metal Can at 6.7
the BL-Molded DIP at
7.5 mW/oC. the BL-Ceramic DIP at B.7
and the SO-B at
mwrc.
5W
5W
5W
5W
Connection Diagram
8-Lead DIP and 50-8 Package
(Top View)
Notes
1. T J M., = 150°C for the Molded DIP and SO-B. and 175°C for the Metal
6.5
Package Code
mwrc.
3. For supply voltages less than ± 15 V. the absolute maximum input
voltage is equal to the supply voltage.
4. Short circuit may be to ground or either supply. Rating applies to 12S C
case temperature or 75°C ambient temperature.
D
7-100
Package Code
6T
6T
KC
9T
6T
6T
9T
Package Description
Ceramic DIP
Ceramic DIP
Molded Surface Mount
Molded DIP
Ceramic DIP
Ceramic DIP
Molded DIP
J.LA741
Equivalent Circuit
-IN
~~--------~----.---------~------------.---~-----------------------t--V+
•
is2
4/
•
~
2
o
15
20
/v
c
w
"
/'
/
10
"~
SUPPLY VOLTAGE -
- 55 C:s TA:OS: 125°C
12
r!
/
20
>;-
85
4
II:
I-
V
95
3. f- RL".kO
- 550(: 5" TA:S 12SCC
3.
..
/'
,.
/
'
.."''""
/'
" /'
":;..'" V
:0
~
i
>
I
36 t-- RL1"'kO
DOC:s TA:S 7O"C
I
/
70
,.
40
105
!B
Input Common Mode Voltage
Range vs Supply Voltage
for IJA741C/E
Output Voltage Swing vs
Supply Voltage for !lA741C/E
Voltage Gain vs
Supply Voltage for !lA741C/E
\.
10
100
1.0K 10K
FREQUENCY -
lOOK 1.0M 10M
Hz
J,LA741
Typical Performance Curves (Cont.)
Frequency Characteristics vs
Supply Voltage for MA741C/E
Voltage Follower Large Signal
Pulse Response for MA741C/E
Voltage Offset Null Circuit
for MA741C/E
y-8~~-+~--+--r-+--r-~-+-4
SUPPLY VOLTAGE -
±V
Power Consumption vs
Supply Voltage
106
TA =
;.
60
U
40
'"
;.
..
!
20
.
§ 10
V
~
V"
o
5
3
~102
//
II:
0
~""0
/
/
26
I
"z~
22
~
20
l-
I.
":I
16
::>
0
'l-
0
':"
"~
I--
.,..
0.5
1.0
Vee
+15
TA - 2S C
Q
V=
I
W
"
~ 10-15
o
>
w
610- 16
Z
w
a:
«
5 10-1
7
U>
~
::E
10~18
10
100
lOOK
10K
1.OK
FREQUENCY -
Hz
Hz
!' 100
.
::>
10- 23
,/
10
10.100 kHz
~
.......
,/
ffia:
,
10-10 kHz
~
~ 10- 2
It. k~' ....V
w
a:
w
.o
~
::>
10-2 5
z
....
Z
:I
«
o
I-
10-26
10
100
I-
10K
1.0K
FREQUENCY -
100K
O. 1
100
lOOK
10K
1.OK
Hz
SOURCE RESISTANCE -
fl
Input Impedance vs
Temperature for IlA741/A
Input Bias Current vs
Temperature for IlA741/A
100
200
Short Circuit Current vs
Temperature for IlA741/A
35
V~e =1±15~
Vee = :t15V
«
50
1
i
150
ilia:
a
e
-
30
I
I-
~
~
100
U>
«
iii
50
0
i'-
-60
r-20
....
-20
i
100
60
TEMPERATURE -
"C
-,.0
I
10.0
V
5.0
".-
25
::>
'"
.........
'"
u
l-
S
u
a:
20
.........
r-..
U
I-
a:
..
---
0
:r
1.0
-60
I'
Z
il!a:
V
3.0
30
I-
....-
~
a:
~
vt=
I-
w
;!;
Q
~
I
.!
U>
"
~OO~~u-~I.O~K~~~IO~K~~~I=OO~K~~-'~"OM
,
o
Vee - :1:15
TA - 2S C
Broadband Noise for Various
Bandwidths
I 10-2 2
o
16~~H-~~HK~~-H+-~~H+~
FREQUENCY -
IZ
W
(I)
~
kD
10- 2
~
a
2.~~H-~4-~~~-H+-~~Ht~
10
5.0
2.0
Input Noise Current vs
Frequency
a:
a:
5
~ 4~rtH--r-rrH~~HH~~~~-H+-~
I"LOAD RESISTANCE -
.
10-1
~ ·~rtH--r-rrH~~rH~i-i-Ht-1
0.2
10-13
.
s:
l:
-
6 12~~H-~~HK~~~+-~~H+~
10
• /
TA=25°C
~ 2o~~H-~~~~I4H\-H+-~4-Ht~
o
\
/
12
_=ro~
32
~ 2.~~H-~~~~~-H+-~~Ht~
I
I.
H+++-++++t-+-H ~~e ~ ±I,~J -
z
l.I'
0.1
:t
,or-rrn-~~n;-,-,-n~;-"OT-'
> 36
I
CI
2.
Input Noise Voltage vs
Frequency
Output Voltage Swing vs
Frequency
-20
20
60
TEMPERATURE _
7-107
100
0
c
,.0
......
15
10
-60
-20
20
60
TEMPERATURE _ "C
100
"0
•
J.1.A741
Typical Performance Curves (Cont.)
Input Offset Current vs
Temperature for /lA7411A
Frequency Characteristics vs
Temperature for /lA741/A
Power Consumption vS
Temperature for /lA741/A
14
J,5V
vcc'=
~ 12
1.4
I
120
Vee
~
Vee
o
~
~
W
0:
~
8
\
"....
~
6
'-...
o
....
~
;;
z
o'"
r- r-
o
-60
-20
20
.J ~
~r-
:t:15V
80
~~
,
:3
,,~ f'
r-- r--.... A;;J...!
I
~ P' c~
;;
r--- ......
r- r-
.......
"ffi60
-
~
-
1.\\""
~ 1.0
~
;-
a:
0.8
SLEW RATE
Oo.~
8"."",.,~
I I"""
I
40
0.6
100
60
TEMPERATURE -
w
r-
z
z
=
1.2
1'00
.... 10
I
= :t20V
E
I
-20
140
20
Input Bias Current vs
Temperature for /lA741C/E
100
60
TEMPERATURE _
°C
140
10
20
60
100
TEMPERATURE _
<>
-
I-- Vee = ::t: 15V
Vee
7.0
= ±15V
~ 80
c:
....
ffi
0:
Ii
60
0:
::>
"'"
iii
"
....
40
;;
20
..
- - r--
::>
o
o
20
30
40
50
I--
60
z
o
10
~80
..
40
50
60
o
70
""'"-
= :t:20V
r-- I---
:3
"- ........
$
l""'-
~
"> 1.00
~
I".
........
50
0
C
60
70
~
a:
0.95
60
70
/'
/
,/
-
"
::::--
~
V
SLEW RATE
0..~"
~
~01
~;'l-c
":-c.-:-
20
18
0
50
"c
Vc~ = "'~V
..........
w
26
H24
60
40
40
1.05
Ii:
30
30
Frequency Characteristics vs
Temperature for /lA741C/E
1.10
~ 22
20
20
TEMPERATURE -
i§ i'-u
TEMPERATURE _
10
I 28
70
10
o
°C
Short Circuit Current vs
Temperature for /lA741C/E
"a:w
~
30
30
lE
::>
'"~
20
~
-....
---
"'-
1
TEMPERATURE -
100
= ::!::15V
~ 2.0
70
Power Consumption vs
Temperature for /lA741C/E
Vee
"-
5
1.0
10
Vee
3.0
TEMPERATURE _ °C
~ 90
I
r-....
f-"
lE
I 5.0
140
c
Input Offset Current vs
Temperature for /lA741C/E
Input Impedance vs
Temperature for /lA741C/E
100
-20
~O
°C
0.90
10
20
30
40
TEMPERATURE -
7-108
50
"C
60
70
o
10
20
30
40
TEMPERATURE _
50
"c
~
60
70
JlA747
Dual
Operational Amplifier
FAIRCHILD
A Schlumberger Company
Linear Division Operational Amplifiers
Description
The IlA747 contains a pair of high performance monolithic
operational amplifiers constructed using the Fairchild Planar
Epitaxial process. They are intended for a wide range of
analog applications where board space or weight are important. High common mode voltage range and absence
of latch up make the JJ.A747 ideal for use as a voltage
follower. The high gain and wide range of operating voltage provide superior performance in integrator, summing
amplifier, and general feedback applications. The IlA747 is
short circuit protected and requires no external components for frequency compensation. The internal 6 dB/octave roll-off insures stability in closed loop applications.
For single amplifier performance, see J-IA741 data sheet.
Connection Diagram
10-Lead Metal Package
(Top View)
NC
vLead 5 connected to case.
•
•
•
•
No Frequency Compensation Required
Short Circuit Protection
Offset Voltage Null Capability
Large Common Mode And Differential Voltage
Ranges
• Low Power Consumption
• No Latch Up
Absolute Maximum Ratings
Storage Temperature Range
Metal Can and Ceramic DIP
Molded DIP and SO-14
Operating Temperature Range
Extended (IlA747AM, JJ.A747M)
Commercial (IlA747EC, IlA747C)
Lead Temperature
Metal Can and Ceramic DIP
(soldering, 60 s)
Molded DIP and SO-14
(soldering, 10 s)
Internal Power Dissipation 1, 2
10L-Metal Can
14L-Ceramic DIP
14L-Molded DIP
SO-14
Supply Voltage
IlA747A, IlA747
IlA747E, IlA747C
Differential Input Voltage
Input Voltage3
Voltage Between Offset Null and VOutput Short Circuit Duration 4
Order Information
Device Code
Package Code
Package Description
IlA747HM
JJ.A747HC
IlA747AHM
IlA747EHC
Metal
Metal
Metal
Metal
5X
5X
5X
5X
Connection Diagram
14-Lead DIP and 50-14 Package
(Top View)
-65°C to + 175°C
-65°C to + 150°C
-55°C to + 125°C
O°C to +70°C
-IN A
V+ A
+IN A
300°C
-OFfSET
265°C
1.07
1.36
1.04
0.93
OUT A
NULL A
NC
y-
-OFFSET
W
W
W
W
OUT B
NULL B
V+ B
+IN B
+OFFSET
-IN B
±22 V
± 18 V
±30 V
± 15 V
±0.5 V
Indefinite
NULL B
Order Information
Package Code
Device Code
JJ.A747DM
JJ.A747 DC
IlA747PC
JJ.A747SC
IlA747ADM
JJ.A747EDC
Notes
1. TJ Max-150"C for the Molded DIP and 50-14, and 175"C for the Metal
Can Ceramic DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 10l-Metal Can at 7.1 mW/oC, the 14l-Ceramic DIP at
9.1 mWrC, the 14l-Molded DIP at 8.3 mWrC, and the 50-14 at
7.5 mWrC.
3. For supply voltages less than ± 15 V, the absolute maximum input
voltage is equal to the supply voltage.
6A
6A
9A
KD
6A
6A
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
Molded Surface Mount
Ceramic DIP
Ceramic DIP
4. Short circuit may be to ground or either supply. Rating applies to 125°C
case temperature or 75°C ambient temperature.
7-109
JlA747
Equivalent Circuit (112 of circuit)
-IN
~~-------i-----1~--------~----------~---'----------------------~--V+
R6
+IN
27
n
OUT
R7
22
+QFFSET
NULL
-OFFSET
NULL
v + A is internally connected to V + B.
7-110
n
p.A747
~A747 and ~747C
Electrical Characteristics TA = 25°C, Vcc = ± 15 V, unless otherwise specified.
jlA747C
IlA747
Symbol
Input Offset Voltage
V,o
V,o
Characteristic
adj
Condition
Min
Rs';;10 kn
Typ
Max
1.0
5.0
Min
±15
Input Offset Voltage
Adjustment Range
Typ
Max
1.0
6.0
±15
Input Offset Current
20
200
20
200
I'B
Input Bias Current
80
500
60
500
Z,
Input Impedance
Icc
Supply Current
Pc
Power Consumption
PSRR
Power Supply Rejection
Ratio
Vcc~±5.0
los
Output Short Circuit Current
Large Signal Voltage Gain
RL;o.2.0 kn, Vo~±10 V
TR
Transient
Response
V, ~ 50 mY, RL ~ 2.0 kn,
CL ~ 100 pF, Av ~ 1.0
BW
I Overshoot
SR
Slew Rate
Channel Separation
2.0
RL ~ 2.0 kn, Av ~ 1.0
nA
nA
Mn
3.4
5.6
3.9
5.6
rnA
100
170
100
170
mW
30
150
30
150
IlVN
25
50
Bandwidth
CS
0.3
V to ±16 V
Avs
IRise time
2.0
mV
mV
1'0
0.3
Unit
25
rnA
200
V/mV
0.3
0.3
I1S
5.0
5.0
%
1.0
1.0
MHz
0.5
0.5
V/IlS
120
120
dB
200
25
The following specifications apply over the range of -55·C';;TA';;+125·C for jlA747, 0·C';;TA';;70·C for jlA747C
V,o
Input Offset Voltage
Rs';;10 kn
1'0
Input Offset Current
O·C';;TA ';;70·C
1.0
TA~+125·C
TA
I'B
Input Bias Current
~
-55·C
~
+125·C
TA ~ -55·C
Supply Current
~
+125·C
TA ~ -55·C
Power Consumption
200
85
500
0.03
0.5
0.3
1.5
3.0
5.0
4.0
6.6
90
150
120
200
O·C ';;TA';; 70·C
TA~+125·C
TA~-55·C
1.0
7.5
mV
7.0
300
nA
30
800
4.0
6.6
rnA
120
200
mW
CMR
Common Mode Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection
Ratio
Avs
Large Signal Voltage Gain
RL;o.2.0 kn, Vo~±10 V
VOP
Output Voltage Swing
RL
~
10 kn
±12
±14
±12
±14
RL
~
2.0 kn
±10
±13
±10
±13
Rs';;10 kn
70
90
70
90
±12
±13
±12
±13
30
Vcc~±5.0
7-111
dB
V
150
I1VN
V to ±16 V
30
25
nA
jlA
O·C ';;TA';; 70·C
TA
Pc
7.0
O·C ';;TA';; 70·C
TA
Icc
6.0
15
150
V/mV
V
IlA747
~A747A and ~747E
Electrical Characteristics TA = 25°C, ± 5.0 V < Vcc < ± 20 V, unless otherwise specified.
Symbol
VIO
VIO
adj
Characteristic
Condition
Input Offset Voltage
Rs";;;50 Q
Input Offset Voltage Adjustment
Range
Vee=±20 V
Min
Typ
Max
Unit
0.8
3.0
mV
10
mV
110
Input Offset Current
3.0
118
Input Bias Current
30
ZI
Input Impedance
Vee=±20V
1.0
Power Consumption
Vee = ±20 V
Common Mode Rejection
Vee=±20 V, VI=±15 V, Rs=50 Q
PSRR
Power Supply Rejection Ratio
Vee = + 10 V, -20 V to Vee = +20 V, -10 V,
Rs=50 Q
los
Output Short Circuit Current
AyS
Large Signal Voltage Gain
TR
Transient Response
BW
Bandwidth
SR
Slew Rate
I Rise time
I Overshoot
80
mW
50
INN
mA
dB
pA747A
10
25
40
I1A747E
10
25
35
Vee=±20 V, RL>2.0 kQ, Vo=±15 V
50
0.25
0.8
6.0
20
VI =50 mV, RL = 2.0 kQ, CL = 100 pF
Ay = 1.0
VI=±10 V, Ay=1
nA
300
95
15
nA
MQ
6.0
160
Pc
CMR
30
80
V/mV
/1S
%
0.437
1.5
MHz
0.3
0.7
VI/1s
The following specifications apply over the range of -55°C";;; TA";;; + 125°C for pA747A, O°C";;; TA ,,;;; + 70°C for pA747E.
VIO
Input Offset Voltage
LlVlol LlT
Input Offset Voltage Temperature
Sensitivity
110
Input Offset Current
118
Input Bias Current
LlIIOI LlT
Input Offset Current Temperature
Sensitivity
pA747E
/1A747A
ZI
Input Impedance
Vee = ± 20 V
Pc
Power Consumption
Vee = ±20 V
Output Short Circuit Current
Avs
Large Signal Voltage Gain
VOP
Output Voltage Swing
Channel Separation
/1VI'C
70
nA
nA
TA = 25°C to 70°C
0.2
nAloC
TA = O°C to 25°C
0.5
TA = 25°C to 125°C
0.2
TA = -55°C to + 25°C
0.5
MQ
0.5
pA747A
I -55°C
I + 125°C
330
330
Vee=±20 V, RL>2.0 kQ, Vo=±15 V
Vee=±20 V
Vee=±20 V
7-112
mW
270
10
Vee=±5 V, RL>2.0 kQ, Vo=±2.0 V
CS
mV
15
210
pA747E
los
4.0
I RL=10 kQ
I RL =2.0 kQ
32
40
mA
V/mV
10
±16
V
±15
100
dB
I1A747
Typical Performance Curves for J.lA747A and J.lA747
Input Bias Current vs
Temperature
100
200
~
rJz
'"
100
i
U>
'"
iii
I'-..
I-
;!;
30
50
-
"
~
r- r- I-
o
-50
I-
20
-20
-
5.0
~
I-
u
~
I:
o
ili
"-
" I" ,
20
15
10
.0
20
"-
25
I-
",
-60
60
100
-60
140
-20
20
1.'
Vee
Vee = ±20V
l-
"~5V
I
~I~
it
10
ffi
a:
o
t:
a:
"u
~
~
'\
.."
I-
-
......... ........
80
U>
8
........
;!;
IS
..
60
~
r- r-
">~
...>
........
1.0
~a:
r-
",..9
,,~ 9i
....
w
i'"'--
z
"'-
~
1.'
I .......
0.8
~
:;-
~J}
SLEW RATE
........ ,,~""
'7
1
c~
OOI>~
44
"'l>~~
I
40
o
-60
-20
20
60
-50
140
100
-20
Input Bias Current vs
Temperature For /1A747C/E
80
I--- Vee = ,,'5V
...
ffi
"
U>
60
'"
40
;!;
20
-
iii
.."
I-
-
'--- i--
o
010203040
TEMPERATURE -
506070
"c
,.c:I
5.0
i~
3. 0
!;
;i;
-
7.0
,.....
I-"'"'
0.6
-60
f~"
I
-20
20
60
140
100
TEMPERATURE _ "C
"C
-
10
Vee:;:: ;t15V
a:
a:
u
140
100
60
Input Impedance vs
Temperature For /1A747C/E
100
~
20
TEMPERATURE _
TEMPERATURE _ °C
140
"C
Frequency Characteristics vs
Temperature
120
E
I 100
Z
100
50
TEMPERATURE _
°C
Power Consumption vs
Temperature
vlc =1"'5~
12
~I--
"
U
TEMPERATURE _
Input Offset Current vs
Temperature
!!i
./
3.0
TEMPERATURE _ "C
14
V
~
V
1.0
140
100
60
10
30
!Z
::!
I
a:
.."
~
I
i
...a:z
U
35
V~c= ~'5~
50
Vee '" ±15V
150
I-
"
Short Circuit Current vs
Temperature
Input Impedance vs
Temperature
Input Offset Current vs
Temperature For /1A747C/E
...Vee"" ±15V
.............
r-....
---
:--
2.0
1
1.0
o
10
20
30
40
SO
TEMPERATURE _ "C
7-113
60
70
o
o
10
20
30
40
TEMPERATURE -
SO
"C
60
70
pA747
Typical Performance Curves (Cont.)
Power Consumption vs
Temperature For pA.747C/E
Short Circuit Current vs
Temperature For /JA747C/E
30
100
~
.......
z
,.
~
~
~
o
80
70
~
a:
20
30
40
50
60
0
10
20
30
40
50
80
70
40
TEMPERATURE _ °C
/
C
160
/
Ii:
/'
:>
80
0
a:
~
o
70
0.951--t--t--t----1f-~
TEMPERATURE -
./
40
L
=e
'~"
V
104
~
/
10
15
102
10
,
1.0
20
-45
'" '"
10
100
1.0K
w
'" '"
10K
FREQUENCY -
Input Offset Current vs
Supply Voltage
tOOK
TA
0
\
a:
a:
:>
...0w
3.0
100
1.0K
10K
-
r-
..
."
Vee
'Ii
1JZ
~
I-
0
10
15
SUPPLY VOLTAGE -
20
tV
c:
I
w 400
. .z
.... ..
... .
. "
0
l-
I-
~
300
w
a:
1
lOOK
10K
100
= ±1SV
= 25°C
500
0
0
C,
;!;
1.0
I
w
z
i!O
~ 2.0
1.0M 10M
600
TA
10
i"
lOOK
Hz
Output Resistance vs
Frequency
100
1.0M
I-
5
10
FREQUENCY -
Hz
c:
V
-180
1.0
f - ZI
4.0
W
r"-13 5
~
IZ
\
-90
:z:
Input Impedance and Input
Capacitance vs Frequency
l25 C
= 25°C
TA
..
1.0M 10M
10M
5.0
~
vc~= :t1~V
1\
TA = 25°C
0
±v
SUPPLY VOLTAGE -
I'"
'j$"
g
8. .
~
10-
5
vcJ=%I!v_
r---.,
W 103
,,/
o
105
"c
Open Loop Phase Response
vs Frequency
106
l25
I
0
20
Open Loop Frequency Response
Q 120
..
..
r--... .........
.........
"c
z
z
22
18
10
TA
0
i'-- r-...
0
0
:t
200
..,.
24
S
Power Consumption vs
Supply Voltage
e
0
l-
0
TEMPERATURE -
~
26
...a:
o
1.05 k:----1f----1f----1f--+
............
...a:z
a:
:>
60
50
28
I
-- -
r--r--r--r---,,---,---,,--,.
1.10
I-
r--
a:
~
.e
= ±20V
Vee
90
I
o
Frequency Characteristics vs
Temperature For pA.747C/E
0
II
~ 200
:>
I-
;!;
0
100
0.1
t.OK
100 K
10K
FREQUENCY -
7-114
Hz
100M
100
1.0 K
10K
FREQUENCY -
100 K
Hz
1.0M
IlA747
Typical Performance Curves (Cont.)
Output Voltage Swing vs
Load Resistance
28
>
I
26
"
24
Z
...~:>
...:>
22
~
16
..
..
...6
.
0
t:"
Vee ~ ,,\sJ
_r-r-
TA = 2S°C
Input Noise Voltage Density vs
Frequency
Output Voltage Swing vs
Frequency
..-
40
>
I
f"
RL
10-1 3
~lJL
Vee'.
3S
Vee _ :t15
= 10kO
TA=25"C
N
w
20
"
~10-15
1\
I
o
>
\
I
W
~10-16
g
14
I
12
Z
~'O-17
'"
w
10
8
0.1
/
0.2
0.5
1.0
2.0
5.0
LOAD RESISTANCE -
kO
Vee
::t:15
TA=WC
110-22
V=
,
!&
5\0:
:lI
is
Z 10-24
~
"
~
'" •
...
10 kHz
10 I
llH~
~Ul
.,.,. V-
..
=
TA=OSOC ' -
\.
70
\.
..
50
\.
40
~
~
30
~
20
i\.
\.
8'" o
10
O.1
100
1.0 K
Hz
lOOK
10 K
SOURCE RESISTANCE -
1.0
10
n
100
1.0K
10K
lOOK 1.0M 10M
FREQUENCY -
Voltage Follower Large Signal
Pulse Response For /JA747/C
Transient Response For p.A747/C
Hz
Frequency Characteristics vs
Supply Voltage For p.A7471C
1.4
28
Vee
=- z15 V
TA
TAo == 2S"C
24
= 25°C
AL = 2 kO
CL
20
,.
10
g
lOOK
10K
1.0 K
100
FREQUENCV -
...I
~
~
oz
10-2
,.
-
m
Z
>E
..
1/
0:
°10-25
10
!c
"'"
10 _ 100 kHz
100K
V~ ±l~V
90
Q 80
10
o
~
100
100
~- e
;:) 10-23
10K
Hz
Common Mode Rejection Ratio
vs and Frequency p.A747/C
I
0:
0:
1.0K
100
FREQUENCY -
~
i
10
Hz
Broadband Noise for Various
Bandwidths
I
10-18
l.oM
lOOK
10K
1.0K
FREQUENCY -
10-21
!
......
0
100
10
Input Noise Current Density vs
Frequency
o
v~
;10-14
V
18
TA=~
%
_
~
= 100 pF
1.'
..
J
/
"~
J
0
....... -.
INPUT
>
:>
11
:>
0
10%
I - - ~erMe
0.5
w
OUTPUT
w
:>
~
~
\
\
... 1--
~N"E
_!.
I'~~~
"'\O~"
s\.~'"
6~"O
>=
........ ..l..
-4
~"""le"7
w
> 1.0
-
S
w
~\.OO'
0:
I--
0.8
G"
--~
-8
1.0
TIME
-I'_
1.5
2.0
'.5
-10
-10
0
10
20
30 40
50
TIME -
j.I.'
7-115
60
70
80
90
O. 6
5
10
2D
15
SUPPLY VOLTAGE -
±V
IlA747
Test Circuits
Voltage Offset Null Circuit
Transient Response Test Circuit
>-~"""'~--Vo
RL
t
V-
Typical Applications
Quadrature Oscillator
C2
820 pF
1%
Tracking Positive and Negative
Voltage References
C3
820 pF
1%
SINE
OUT
01
R4
12 kO
02
f-15V
R2
190kll
1%
-15 V
, ~ --:2:-~-J"'C"'2';'R"'2"'C""3R"'3~ (R1Cl ~ R2C2)
1
NEGATIVE
REGULATED
OUT
-12 V
1L!5 5 mA
SOURCE
OR SINK
R3
180 kll
Rl
'90 kll
1%
v-
Cl
820 pF
1%
Rl
10 kll
AI +A2
Positive Output
= VOl x~
Negative Output
7-116
= - Positive
Output x
A6
AS
iJA747
Analog Multiplier
.,.-15 V
CURRENT SOURCE
R2
20 kU
AMPLIFIER
1~.
1% (NOTE 2)
R14
25.8 kO
R12
12 kO
1%
(NOTE 2)
+15 V
..,..15 V
Eo
-15 V
R3
20 kll
1%
R5
5 kO
1%
25.8 k!l
1"10
--I,
R4
15 kll
1%
-15 V
R15
E, 2
(NOTE 2)
R7
150 kll
R10
150 kll
ZERO ADJUST
-15 V
+15 V
Compressor/Expander Amplifiers (Note 1)
D1 (NDTE 3)
R
R2
10 kH
~
D2
R5
R
1 kH
D3
CDMPRESSOR
IN
EXPANDER
IN
-=
COMPRESSOR
f\7
EXPANDER
OUT
R
fu-
R6
1 kll
-=
EXPANDER
Notes
1. Maximum Compression Expansion Ratio = RIR (10 kn > R ;;. 0)
2. Matched 10 0.1% Eo = 100 Ell X E'2
3. Diodes D1 through D4 are matched FD666 or Equivalent
7-117
J.lA748
Operational Amplifier
F=AIRCHILO
A Schlumberger Company
Linear Division Operational Amplifiers
Description
The p.A748 is a high performance monolithic operational
amplifier constructed using the Fairchild Planar Epitaxial
process. It is intended for a wide range of analog applications where tailoring of frequency characteristics is desirable. High common mode voltage range and absence of
latch up make the p.A748 ideal for use as a voltage follower. The high gain and wide range of operating voltages
provide superior performance in integrator, summing amplifier, and general feedback applications. The p.A748 is
short circuit protected and has the same lead configuration
as the popular p.A741 operational amplifier. Unity gain frequency compensation is achieved by means of a single
30 pF capacitor.
Connection Diagram
8-Lead Metal Package
(Top View)
FREQ
COMP
vLead 4 connected to case.
• Short Circuit Protection
• Offset Voltage Null Capability
• Large Common Mode And Differential Voltage
Ranges
• Low Power Consumption
• No Latch Up
Absolute Maximum Ratings
Storage Temperature Range
Metal Can and Ceramic DIP
Molded DIP and SO-8
Operating Temperature Range
Extended (p.A748M)
Commercial (p.A748C)
Lead Temperature
Metal Can and Ceramic DIP
(soldering, 60 s)
Molded DIP and SO-8
(soldering, 10 s)
Internal Power Dissipation I, 2
8L-Metal Can
8L-Molded DIP
8L-Ceramic DIP
SO-8
Supply Voltage
Differential Input Voltage
Input Voltage 3
Output Short Circuit Duration 4
-65°C to + 175°C
-65°C to + 150°C
Order Information
Device Code Package Code
Package Description
p.A748HM
p.A748HC
Metal
Metal
5W
5W
Connection Diagram
8-Lead DIP and 50-8 Package
(Top View)
-55°C to + 125°C
O°C to +70°C
- OFFSET NULLI
FREQCOMP
FREQ
COMP
-IN
v+
+IN
OUT
+ OFFSET
v-
1.00 W
0.93 W
1.30 W
0.81 W
±22 V
±30 V
± 15 V
Indefinite
NULL
Order Information
Device Code Package Code
Package Description
p.A748RC
p.A748SC
pA748TC
Ceramic DIP
Molded Surface Mount
Molded DIP
Notes
I. TJ Max = 150"C for the Molded DIP and SO·8, and 175"C for the Metal
Can and Ceramic DIP
2. Ratings apply to ambient temperature at 25'C. Above this temperature,
derate the 8L-Metal Can at 6.7 mWI"C, the 8L-Molded DIP at
7.5 mWI"C, the 8L-Ceramic DIP at 8.7 mWI"C, and the SO-8 at
6.5 mWrC.
3. For supply voltages less than ± 15 V, the absolute maximum input
voltage is equal to the supply voltage.
4. Short circuit may be to ground or either supply. Rating applies to 125"C
case temperature or + 75°C ambient temperature.
7-118
6T
KC
9T
fJ.A748
Equivalent Circuit
- IN
- OFFSET NULL IFREQ COMP
FREQ COMP
vt
+IN
R6
27H
OUT
+ OFFSET NULL
V+
R1
1kn
7-119
f.1A748
J-IA748
Electrical Characteristics TA
Symbol
= 25°C,
Vee
= ± 15
V, Ce
= 30
Characteristic
Via
Input Offset Voltage
Via adj
Input Offset Voltage Adjustment
Range
pF, unless otherwise specified.
Condition
Min
Rs';; 10 kn
Typ
Max
1.0
5.0
±15
Unit
mV
mV
110
Input Offset Current
20
200
lis
Input Bias Current
80
500
ZI
Input Impedance
Icc
Supply Current
1.9
2.8
rnA
Pc
Power Consumption
60
85
mW
0.3
los
Output Short Circuit Current
Avs
Large Signal Voltage Gain
TR
Transient Response
SR
Slew Rate
I Rise time
IOvershoot
RL ;;;'2.0 kn, Vo=±10 V
50
VI = 20 mY, Cc = 30 pF,
RL = 2.0 kn, CL = 100 pF, Av = 1.0
RL = 2.0 kn, Av
= 1.0
RL = 2.0 ·kn, Cc = 3.5 pF, Av = 10
2.0
nA
nA
Mn
25
rnA
150
V/mV
0.3
iJ.s
5.0
%
0.5
V/J-Is
5.5
The following specifications apply for -55°C';; TA';; 125°C
Via
Input Offset Voltage
Rs';; 10 kn
1.0
6.0
mV
110
Input Offset Current
TA=TAMax
10
200
nA
TA = TA Min
50
500
lis
Input Bias Current
TA=TA Max
0.03
0.5
TA=TAMin
0.3
1.5
Icc
Pc
Supply Current
Power Consumption
TA=TAMax
1.5
2.5
TA=TA Min
2.0
3.3
TA=TAMax
45
75
TA=TA Min
60
100
CMR
Common Mode Rejection
Rs';; 10 kn
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Rs';; 10 kn
Avs
Large Signal Voltage Gain
RL;;;'2.0 kn, Vo=±10 V
VOP
Output Swing
RL=10 kn
±12
±14
RL = 2.0 kn
±10
±13
7-120
70
90
±12
±13
30
25
iJ.A
rnA
mW
dB
V
150
iJ.VN
V/mV
V
fJA748
IlA748C
Electrical Characteristics TA
Symbol
= 25°C,
Vee
= ± 15
V, Ce
= 30
Characteristic
VIO
Input Offset Voltage
110
Input Offset Current
pF, unless otherwise specified.
Condition
Min
Rs< 10 kn
Typ
Max
Unit
2.0
6.0
mV
20
200
nA
80
500
liB
Input Bias Current
ZI
Input Impedance
Icc
Supply Current
1.9
2.8
mA
Pc
Power Consumption
60
85
mW
los
Output Short Circuit Current
25
mA
0.3
Avs
Large Signal Voltage Gain
TR
Transient Response
SR
I Rise time
IOvershoot
Slew Rate
2.0
nA
Mn
150
V/mV
VI = 20 mY, Cc = 30 pF,
RL = 2.0 kn, CL = 100 pF, Av = 1.0
0.3
/J.s
5.0
%
RL = 2.0 kn, Av = 1.0
0.5
V//J.s
RL;;'2.0 kn, Vo=±10 V
20
The following specifications apply for O°C < TA < 70°C
VIO
Input Offset Voltage
Rs<10 kn
110
Input Offset Current
TA=TAMax
300
nA
TA = TA Min
800
/J. A
mA
IcC
Supply Current
Pc
Power Consumption
2.0
7.5
TA=TAMax
1.5
2.5
TA = TA Min
2.0
3.3
TA =TA Max
45
75
TA = TA Min
60
100
CMR
Common Mode Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Rs<10 kn
Avs
Large Signal Voltage Gain
RL;;'2.0 kn, Vo=±10 V
VOP
Output Voltage Swing
RL=10 kn
±12
±14
RL = 2.0 kn
±10
±13
Rs < 10 kn
7-121
mV
mW
70
90
dB
±12
±13
V
30
15
150
/J.VIV
V/mV
V
f.1A748
Typical Performance Curves for p.A748
Input Bias Current vs
Temperature
Short Circuit Current vs
Temperature
Input Impedance vs
Temperature
300
Vee
10.0
~ ±1~V
35
vcd ~±~v
/ 'V
5.0
\
1i
....
200
iii
1\
Z
w
a:
a:
"
III
.."
....
~
....
i'-- r--.
~
o
-so
1.0
20
i
t--..
--
so
20
100
TEMPERATURE _
<>
a:
a:
0.5
Vcc '=±15V
'" .....
" "-
25
"0t::
"()0a:
'/
~
100
!
140
c
Power Consumption vs
Temperature
50
40r---.---~--.----r---r---'
-20
c
0
I
80
Vee = ±15 V
VJc~±1'V
r-RL-="
1i
I
....z
~
e
30
ffi
w
a:
a:
"t;
0
~
".
a
II:
20
~
~-
....
~
10
0
•
,.
10
r-
20
-20
a:
i3
t-
...........
so
20
50
~
40
30
-so
140
100
<>
Z
0
0
-20
c
--
~
so
20
TEMPERATURE _
100
<>
30
40
50
TEMPERATURE _ °C
70
IVee =IX1. V
1
5.0
I-
I
V
- Ii :
60
1.0
140
c
Short Circuit Current vs
Temperature for IlA748C
7.0
w
a:
a:
"
"li
t::
20
...... r-........
26
...........
24
"'-
()
I-
a:
/'"
10
28
0
/'"
/'
o
30
Z
/V
V
20
r-
32
2.0
40
10
......
Vee - ±15 V
r-- I--
o
1- r-
a:
w
Input Impedance vs
Temperature for 1lA748C
iI
80
o
"
10
ffia: 120 t-...
80
In
10
Vee -:!:15V
i~
~
:Ii
TEMPERATURE _
200
"
0
-
I ......
SUPPLY VOLTAGE - -z.V
Input Bias Current vs
Temperature for IlA748C
~
z
30
o
-so
20
70
I
22
0
l:
In
30
40
TEMPERATURE _
7-122
50
<>
C
60
70
20
18
o
10
20
30
'"
40
TEMPERATURE _
..........
50
<>
C
~
60
70
f..LA748
Typical Performance Curves for I-IA748 and I-IA748C (Cont.)
Input Offset Current vs Supply
Voltage for J,lA748C
Input Offset Current vs
Temperature for J,lA748C
Power Consumption vs
Temperature for J,lA748C
so
50
Vee"" ±.15 V
...z 301---'/--+--+--+--+-""
w
a;
a;
:>
0
i...
:>
ffi
a;
a;
:>
0
20
~
...l!;:>
0
..
~
I
..
10
3:
3:
15
~
--
20
20
o
I
~
I'..."
105
w
0
;/
100
95
..
V
"..
:>
V
/
.."'"
...
'"
.."
w
20
16
so
60
0
0
40
~
~
V
16
./'
./
20
o
>
+1
I
w
/
V
/'
~
!
~
~
!
./
5
10
15
SUPPLY VOLTAGE -
20
:tv
50
0
60
70
c
TA =125oC
'a;~"
12
~
10
/"""
/'
/
'/
/
w
0
0
/
/
:E
z
0
1/
:E
:E
0
0
10
o
20
15
20
15
10
5
±v
SUPPLY VOLTAGE -
±v
Frequency Characteristics vs
Supply Voltage
1.4
TA= 25°C
±15V
25°C
Vee
TA
24
/
V
1.2
w
!O
20
w
> 1.0
1
~
16
I
2
J
0.2
J
s\.I'-'"
~s£
,,~I'-
b=
-r--
..\Q~"
~",Q
~.oo~"·
0:
8
0.1
N4.V
S1EN}-
...
:>
o
..
40
14
g""
V
Output Voltage Swing vs Load
Resistance
/
30
I!
/
5
I
20
Input Common Mode Voltage
Range vs Supply Voltage
28
E
w
24
>
100
10
TEMPERATURE _
./
SUPPLY VOLTAGE -
TA = 25°C
RL=oo
a;
30 o
70
£
o
120
iilz
60
./
±V
Power Consumption vs Supply
Voltage
:E
50
c
0
w
12
....
40
32
.;
SUPPLY VOLTAGE -
I
z
30
40
16
:>
0
80
Q
20
~
85
~
10
r--
50
w
-RL=2kU
>
I
-- -
60 b
a;
..
~
TA= 25°C
RL = 2 ktl
~ 110
g
0
0
40
C
§z
iilz
r-
Output Voltage Swing vs
Supply Voltage
TA-25 C
~
f
:E
TEMPERATURE _
115
!;l
!:i
z
10
~y
Voltage Gain vs
Supply Voltage
70
I
30
o
10
SUPPLY VOLTAGE -
=.
Vee L±15V
RL
40
0.8
osl'-Q
0.6
0.5
1.0
2.0
LOAD RESISTANCE -
7-123
5.0
kO
10
10
15
SUPPLY VOLTAGE -
20
±V
J.1A748
Typical Performance Curves for I1A748 and !1A748C (Cont.)
Frequency Characteristics vs
Temperature for J.lA748
1.'
-
w
'3
~
w
>
1.10
~cc ~ ±1J v
1.2
!:i
Lv
0.8
~
I'--.. r--... ~ JLEWIRAiE
II
~ P' c~
1.0
iil
a:
Vee = ±15 V
~('~
'i>\-t;;,~
0.6
-60
(Oo..~
60
100
TEMPERATURE _
0
3
~
~ 1.00
~
I
--¥I
~
...~"
" ......
:::::-
~
~
~ol
10
20
30
40
50
TEMPERATURE _
C
0
60
70
c
FREQUENCY -
10-22
V
10-100 kHz
10-23
~
W 10-24
10-1 kHz.........
~
Veel~ ±15 ~
TA
•••••••••• "
Rs
i
10
loOK
100
FREQUENCY -
lOOK
10K
RL=2kfl
Cc=30pF
".
~
••••••• 1 " -
..... \
~~~--+-~---r~t.-~.--i
-30
\
--60
'\
RL=2kn
Cc=3pF
...•..•...
m
a: -90
m
c
RL = 2 kO
Cc""30pF
~ -120
TA
~
Rs
=500
25°C
>
I
-
~.
J"
I!I-I
~~ : ~ok~
.
II
"...
"
'\
0
24
l!
~
FREOUENCY -
Hz
60
9z
40
0
~
..
w
.....
o
106
80
>;-
·180
lOS
100
Z
6
-210
104
.""
~
.g
I
\cc ~ 30 PF\
'"~
103
,.---,.--,--,-..,.--,-..,.--,
ID
\CC:=3pF
,.
Hz
Open loop Frequency Response
for RL;;' 10 kil
1~
32
107
1.0 K
10 K
100 K
FREQUENCY -
7-124
\
'--....L_..L...-...l_...L._..L...-'_-'
10
102
103
104
105
106
107
FREQUENCY -
II vL'±U~
c.
~
102
n
z
"
~
-150
10
100 K
Output Voltage Swing vs
Frequency
i\
1
10 K
40
v~ ~±lJv
"\
.....
-~
1.0 K
SOURCE RESISTANCE -
Hz
Open Loop Phase Response vs
Frequency
.~
1
100
25°C_
=SOl
40r--r-~r--I~8~'~~~_+---1
Go
§
I
,.,..",
~
~ 80r--r--4b,-,~,~.~,,-+-~-+---1
~
V
10--25
~
i
~
100
~ wr--I-~~~~.~~~'-~-'R'~.2"kn~
~
":;'"
Cc=3pF
10-10 kHz
Z
::&
""=-
120 ...---'r--'~--'~-'~-'~..,.~-'
_Y~C-+15Y
-TA ->soC
i
Hz
Open loop frequency Response
for RL = 2 kil
Broadband Noise for Various
Bandwidths
a
'"~
'"
~,. 10-171-f.+1+-++H+-+-++t+--+-+-+++-I
1ft(
0.9 0
100
l-rtff""f...t:Ii+t-t-t+tt-t--Htt-i
10-161-f.+1+-++H+-+-++t+-+-+-+++-I
"o
~+'1<0
140
+15 V
10-1S
w
~
>soc
~ 10-141--++++-++H4-1-1-+1-+--+--+-H+-I
g
I
~0J.
1O-13...-,....,.,.,---r-r-rrr-,-,...,.,..,..-..,.-..,.-rrr-,
I
w
S~EWRATE
/'
7"
0:
10-21
Vee
TA
"'~
...........
0.95
Input Noise Current vs
frequency
~
~~
f<-""
1.05
10"''f~''
I I
-20
Input Noise Voltage vs
Frequency
Frequency Characteristics vs
Temperature for JJA748C
.....
100M
Hz
10 M
FREQUENCY -
Hz
MA748
Typical Performance Curves for JlA748 and JlA748C (Cont.)
Frequency Response for Various
Closed Loop Gains
120
!/lI
Vee I; ±IS
Compensation Capacitance vs
Closed Loop Voltage Gain
so
t
~~<>k71-
TA
RL
100
Input Impedance and Input
Capacitance vs Frequency
'&
Z
~
w
10
S!
g
0
9
0
III
I
Cc=1pF
~ 60
..
'&
2,
80
--~
Cc =]2 pF
40
ce;3~ ~
20
90
cc",1 3OPF
100
1.0K
10K
FREQUENCY -
C,
11: 100 K I-t-+H-++t+t-t-t-+tt--t-+i-t+-t 1.0
!;
"'
-20
10
"r!z
1\
~PFj ~\.
Cc;
~
K
I
w
"z~
~
."
!ion
2.0
z
0
z
FREQUENCY -
At. =2kU
\
\
"
NO OVERSHOOT
(CL:51OO pF)
"-
"-"'
L
~
1.0
~
.......",
0.5
010
20
30
40
Transient Response Test Circuit
~
506070
CLOSED LOOP VOLTAGE GAIN -
Hz
+15 V
TA = 25"C
2()O/o OVERSHOOT
~
"
Vee
\.
(el::; 20 pF)
1.0M
100 K
Hz
10
5.0
:I!
0
10M
Voltage Follower Transient
Response (Gain of 1)
~
...
0
!
0.1
lOOK 1.0M
w
20
dB
Voltage Follower Large Signal
Pulse Response
10
28
Vee::: ±15 V
TA ; 2S"C
24
20
90%
~
I
...
K
16
~~4-----~------Vo
12
I
;.
i'
w
~
>
...
....
:>
11
-
>
I
"0~
I
'o5
1/221'
RL
V,
Vee::c ±15 v
eL =
:>
-6
RL ::: 2 k!l
R,ser ME - r -
-2
0
TA =25°C
100 pF
V
"-
r
OU~PUk~
,I
INPUT/
=r-- cr !",
"
Cc=30pF
['y
:I
;,
<10
..
3
-10
0.5
1.0
1.5
2.5
2.0
TIME -
TIME -).JS
Output Resistance vs Frequency
Common Mode Rejection Ratio vs
Frequency
600
100
Vee
=
±15 v
!/l
TA =25"C
0
I
~
z
0
w 400
0
~
I
90
z
;::
80
\.
70
\.
60
id so
300
a:
.......
/
:> 200
:>
;;J
a:
l!l0
\
40
:I!
30
0
20
0
0
10
\.
z
0
100
''""
0
100
1.0 K
10 K
FREOUENCY - Hz
100 K
l.oM
.1
Vee =±15VTA =25"C
CL =30pF_
~
I
500
~
-
RL =2kO
C'SiPi-
10
100
1.0 K
10 K
100 K 1.0M 10 M
FREQUENCY _ Hz
7-125
~s
\
~
JlA748
Test Circuits
Feed Forward Compensation
Large Signal Feed Forward
Transient Response
10
10 kll
r-~CC~±I~V
RL
;10
7.5
=10pF
r-~L "'25°C
TA
r
10 kll
>--<....._p--Vo
\
3.0 kll
-2.5
150 pF
o
2
RESPONSE TIME -,.s
Voltage Offset Null Circuit
Suggested
y+
10 Mil
Alternate
y-
5.1 Mil
25 kll
7-126
J.lA748
Typical Applications
Pulse Width Modulator
Rl
R2
~~'V _-'l00'MkO,..-......_ _ _ _ _ _...
l00WkO~
+15 V -15 V
,---+--Vo
R3
C1
0.47
~F
10 kO
J.
R'
100 k!l
01
6.2V
RS
100 !l
02
6.2 V
Practical Dlfferentiator
Circuit for Operating the j.tA748 Without a Negative
Supply
C2
Rl
R2
R2
+15 v -15 V
+ZOV
V,
>8'--_-VO
R3
1
Ie = 211' R2 C1
1
Ih
=
211' Rl Cl
fc
< fh < funity
211' R2 C2
gain
7-127
p.A759 • p.A77000
FAIRCHILD
Power
Operational Amplifiers
A Schlumberger Company
Linear Division Operational Amplifiers
Description
The pA759 and pA77000 are high performance monolithic
operational amplifiers constructed using the Fairchild Planar
Epitaxial process. The pA759 provides 325 mA and the
pA 77000 provides 250 mA output current and feature
small signal characteristics better than the fJA741. The
amplifiers are designed to operate from a single or dual
power supply with the input common mode range including
the negative supply. The high gain and high output power
provide superior performance whenever an operational amplifier is needed. The pA759 and pA77000 employ internal
current limiting, thermal shutdown, and safe-area compensation making them essentially indestructible. These amplifiers are intended for a wide range of applications
including voltage regulators, audio amplifiers, servo amplifiers, and power drivers.
• Output Current
p.A759 - 325 mA Minimum
p.A77000 - 250 mA Minimum
• Internal Short Circuit Current Limiting
• Internal Thermal Overload Protection
• Internal Output Transistors Safe-Area Protection
• Input Common Mode Voltage Range Includes Ground
Or Negative Supply
Connection Diagram
8-Lead Metal Package
(Top View)
NC
vLead 4 connected to case.
Order Information
Device Code
fJA759HM
fJA759HC
Package Code
5W
5W
Package Description
Metal
Metal
Connection Diagram
TO-202 Package
(Top View)
Absolute Maximum Ratings
Storage Temperature Range
Metal Can
Power Watt
Operating Junction Temperature Range
Extended (pA759M)
Commercial (pA759C, pA77000C)
Lead Temperature
Metal Can (soldering, 60 s)
Power Watt (soldering, 10 s)
Internal Power Dissipation 1
Supply Voltage
Differential Input Voltage
Input Voltage2
-65°C to + 175°C
-65°C to + 150°C
-55 to + 150°C
O°C to + 125°C
Order Information
Device Code
fJA759U1C
fJA77000U1C
Internally Limited
±18 V
30 V
± 15 V
Notes
1. Although the internal power dissipation is limited. the junction
temperature must be kept below the maximum specified temperature in
order to meet data sheet specifications. To calculate the maximum
junction temperature or heat sink required, use the thermal resistance
values which follow the Electrical Characteristics Table.
2. For a supply voltage less than 30 V between V+ and V-. the absolute
maximum input voltage is equal to the supply voltage.
7-128
Package Code
8Z
8Z
Package Description
Power Watt
Power Watt
p.A759 • p.A77000
Equivalent Circuit
-IN
+IN--~--~-----+-----4---4--------~
-OFFSET
NULL
+ OFFSET
NULL
Note
All resistor values in ohms.
--------------_-.=,"".;;.-;'---------------...---7-129
J.LA759 • J.LA77000
p.A759
Electrical Characteristics TJ = 25°C. Vee = ± 15 V. unless otherwise specified.
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
VIO
Input Offset Voltage
1.0
3.0
mV
110
Input Offset Current
5.0
30
nA
liB
Input Bias Current
50
150
nA
Rs<:10 kil
ZI
Input Impedance
Icc
Supply Current
0.25
VIR
Input Voltage Range
los
Output Short Circuit Current
IVcc-vo1=30 V
10 PEAK
Peak Output Current
3.0 V<:lvcc-vo1<:10 V
1.5
12
+13
to V-
Avs
Large Signal Voltage Gain
TR
Transient Response
I Rise time
I Overshoot
RL>50 il. Vo=±10 V
±325
50
RL = 50 il. Av = 1.0
Mil
18
mA
+13
to V-
V
±200
mA
±500
mA
200
V/mV
300
ns
5.0
%
SR
Slew Rate
RL = 50 il. Av = 1.0
0.6
Vlp.s
BW
Bandwidth
Av= 1.0
1.0
MHz
The foliowing specifications apply for -55°C <: TJ <: + 150°C
VIO
Input Offset Voltage
110
Input Offset Current
Rs<:10 kil
4.5
mV
60
nA
liB
Input Bias Current
CMR
Common Mode Rejection
Rs<:10 kil
80
100
dB
PSRR
Power Supply Rejection Ratio
Rs<:10 kil
80
100
dB
25
200
V/mV
±10
± 12.5
300
Avs
Large Signal Voltage Gain
RL>50 il. Vo=±10 V
VOP
Output Voltage Swing
RL =50 il
7-130
nA
V
fJ.A759 • fJ.A77000
IlA759C
Electrical Characteristics TJ = 25°C, Vee = ± 15 V, unless otherwise specified.
Symbol
Characteristic
VIO
Input Offset Voltage
110
Condition
Min
Typ
Max
Unit
1.0
6.0
mV
Input Offset Current
5.0
50
nA
lis
Input Bias Current
50
250
ZI
Input Impedance
Icc
Supply Current
VIR
Input Voltage Range
Rs";; 10 kn
1.5
+13
to V-
+13
to V-
V
±200
mA
12
los
Output Short Circuit Current
IVcc-vo1=30 V
10 PEAK
Peak Output Current
3.0 v,,;;lvcc-vok10 V
Avs
Large Signal Voltage Gain
RL > 50 n, Vo = ± 10 V
TR
Transient Response
I
I
Rise time
nA
0.25
Mn
18
mA
±325
±500
25
200
V/mV
300
ns
RL = 50 n, Av = 1.0
Overshoot
mA
10
%
SR
Slew Rate
RL = 50 n, Av = 1.0
0.5
V//ls
BW
Bandwidth
Av = 1.0
1.0
MHz
The following specifications apply for 0°";; TJ";; + 125°C
VIO
Input Offset Voltage
110
Input Offset Current
lis
Input Bias Current
CMR
Common Mode Rejection
Rs";;10 kn
7.5
mV
100
nA
400
Rs";; 10 kn
70
100
nA
dB
PSRR
Power Supply Rejection Ratio
Rs";;10 kn
80
100
dB
Avs
Large Signal Voltage Gain
RL>50 n, Vo=±10 V
25
200
V/mV
VOP
Output Voltage Swing
RL = 50 n
±10
± 12.5
7-131
V
IlA759 • IlA77000
1JA77000
Electrical Characteristics TJ = 25°C, Vee =
Symbol
± 15
V, unless otherwise specified.
Characteristic
VIO
Input Offset Voltage
110
Input Offset Current
lis
Input Bias Current
ZI
Input Impedance
Condition
Min
Rs';;;l0 kn
Icc
Supply Current
VIR
Input Voltage Range
los
Output Short Circuit Current
IVcc-v01=30 V
Typ
mV
5.0
50
nA
50
250
1.5
+13
to V-
+13
to V-
V
±200
mA
18
mA
±400
200
V/mV
= 1.0
300
ns
10
%
= 1.0
0.5
VI/1s
1.0
MHz
3.0 V.;;;lvce-vol.;;;lO V
Large Signal Voltage Gain
RL;;'50 n, Vo=±10 V
TR
Transient Response
SR
Slew Rate
RL
BW
Bandwidth
Av = 1.0
n, Av
Mn
25
Peak Output Current
= 50
nA
0.25
±250
10 PEAK
Avs
RL = 50 n, Av
Unit
8.0
12
I Rise time
I Overshoot
Max
1.0
mA
The following specifications apply for 0·';;; TJ .;;; + 125°C
VIO
Input Offset Voltage
Rs';;;10 kn
10
mV
110
lis
Input Offset Current
100
nA
Input Bias Current
400
CMR
Common Mode Rejection
Rs';;; 10 kn
70
100
nA
dB
PSRR
Power Supply Rejection. Ratio
Rs';;;l0 kn
80
100
dB
Avs
Large Signal Voltage Gain
RL;;'50 n, Vo=±10 V
25
200
V/mV
VOP
Output Voltage Swing
RL = 50 n
±10
± 12.5
7-132
V
tJ.A759 • tJ.A7700a
Package
Typ
Max
Typ
Max
Mounting Hints
IiJC
°C/W
IiJC
°C/W
IiJA
°C/W
IiJA
°C/W
Metal Can Package (/lA759HChIA759HM)
The /lA75[) in the S·Lead TO·99 metal can package must
be used with a heat sink. With ± 15 V power supplies, the
!lA759 can dissipate up to 540 mW in its quiescent (no
load) state. This w0U1d result in a 100°C rise in ohip temperature to 125°C (assuming a 25°C ambient temperature).
In order to avoid this problem, it is advisable to use either
a slip on or stud mount heat sink with this package. If a
stud mount heat sink is used, it may be necessary to use
insulating washers between the stud and the chassis because the case of the !lA759 is internally connected to
the negative power supply terminal.
Power Watt (U1)
S.O
12
75
SO
Metal Can (H)
30
40
120
150
TJMax-TA
POMax= Ii
or
JC + IiCA
=
TJMax-TA
(Without a heat sink)
IiJA
IiCA = lics + liSA
Power Watt Package (!lA7""1C//lA77000U1C)
The !lA759U1C and !lA77000U1C are designed to be attached by the tab to a heat sink. This heat sink can be
either one of the many heat sinks which are commercially
available, a piece of metal such as the equipment chassis,
or a suitable amount of copper foil as on a double sided
PC board. The important thing to remember is that the
negative power supply connection to the op amp must be
made through the tab. Furthermore, adequate heat sinking
must be provided to keep the chip temperature below
125 C under worst case load and ambient temperature
conditions.
Solving TJ:
TJ = TA + PD(IiJC + IiCA) or
= TA + POIiJA (Without a heat sink)
Where:
TJ
=
TA =
PD
=
IiJA =
IiJC =
IiCA =
lics =
liSA =
Junction Temperature
Ambient Temperature
Power Dissipation
Junction to ambient thermal resistance
Junction to case thermal resistance
Case to ambient thermal resistance
Case to heat sink thermal resistance
Heat sink to ambient thermal resistance
Q
Typical Performance Curves
Frequency Response For Various
Closed Loop Gains
100
.....
~
C
90
80
70
"w
80
.g
40
"~
0
>
....
.,0w
- ,
"
100
90
'll
"\
~
I\.
50
"w
"~
\
"'
30
..
..
10
g
u
"'
-10
101
102
103
104
r-
'\
80 ."'-.
70
80
I
I
"\.
"\. \
50
./'
\
40
105
FREQUENCY·Hz
\.
,
1\
106
>
30
§
20
z
w
10
0
0
Output Voltage vs Frequency
/~AIN
I\.
0
.\
20
100
Open Loop vs
Frequency Response
\
"\.
'"
-10
107
100
101
1()2
103
104
80
105
60
40
20
>'t.
25
i!lc
!:i0
20
E
"
...>
50
10
-40
"I'
10'
107
103
104
FREQUENCY·Hz
FREQUENCY-Hz
$
7-133
~
-20
\.
106
AL = SOO
TA = 25°C
30
140
100
\,
v~cl ~\!v
160
PHA.k- 120
"'-
3'
180
105
10'
p.A759 • p.A77000
Typical Performance Curves (Cont.)
Output Voltage vs
Load Resistance
II
30
>'t.
Vee = :t15V
~~- is'C
25
IIIc
~
>
....
i....
"0
20
15
/I
II,
i
//\
Vi
TJ;,lsor
V
I I
10
/
II
-2
-4
Vee = :t15V
10
1000
20
40
~O
30
30
40
50
20
I
10
I
25"f
-6
100
'E
\
I
=
RL SOO
TAl;
/
RISE TIME 0.22
Il.
km
0.2
60
0.4
0.6
0.8
1.0
1.2
1.4
TlME-",_
TIME-""
LOAD RESISTANCE-O
AL .. SOO
~~~~-
90%
1\
I \
INPUT ....
I
50
~
OUTPUT
Vee - :t15V
r,
80
~
/
,,-:
\,
10
Voltage Follower Transient
Response
Voltage Follower Large Signal
Pulse Response
f'CO,251OF
Total Harmonic Distortion vs
Power Output
Total Harmonic Distortion vs
Frequency
10
10
Vee = :15V
RL = SOO
~
Vee = :18V (320)
2O""_p
~
I I
I
Vee III :t12V(160,80)
f= 1kHz,
1.0
1.0
0.1
I
f-
If-
.0
:;!
....
Av
III:
20dB
-1~1= J..I
"
I
II
1
I I
RL
80
-
160
.01
.001
.01 .02
103
,
/
320
e
III I I
Vc6 ~ ~j5V
TA-WC
I
Av= 1
0.1
103
I
~....
yj
Input Noise Voltage vs
Frequency
.05 0.1 0.2
0.5 1.0
2
5
100
10
10'
POWER OUTPUT·W
FREQUENCY-Hz
FREQUENCY-Hz
"""'''''''
Noise Current vs Frequency
,
Vee
III:
±15V
TA-we
~
ILl
~
700
c
E
i
800
800
10
..... 100
!iw
I
r-.....
800
PowItr supply-single 36 V
Temperature TJ = 2SOC
,
500
B
!:: 400
c
..........
,
r--.....
..........
........
..........
u
I'-..
I'i
300
.
200
~:I:
500
5
400
....
300
0
200
a:
a:
:>
u
,
..........
~
:>
"c
~
--
V
E
:>
10-
Peak Output Current vs
Output Voltage
Short Circuit Current vs
Junction Temperature
./
/'
V
100
100
•,
102
103
FREQUENCY·Hz
-so
so
100
JUNCnoN TEMPERATURE - °C
7-134
lSO
12
18
24
OUTPUT VOLTAGE.V
30
36
J1A759· J1A77000
Offset Null Circuit
Paralleling p.A759 Power Op Amps
V, --'VIIV-_-f
0.50
Vo
0.50
Audio Applications
Low Cost Phono Amplifier
C2
10pF
R3
25k
,~~~t}~
1-=
CARTRIDGE
.1
":'"
-=
-=
Headphone Amplifier
v,
25k
1,.F
180pF
22k
10k
2.2k
Note
1. All resistor values in ohms.
7·135
Speaker
Impedance
(ohms)
Output
Power
(watts)
Min
Supply
(volts)
(volts)
4
8
16
32
.18
.36
.72
1.44
9
12
15
25
2.4
4.8
9.6
19.2
Vop.p
JiA759 • JiA77000
Bi-Directional Intercom System Using
the /lA759 Power Op Amp
+12 V
2k
+
10~
+12V
160
-12V
TONE
CONTROL
(OP1'lONAL)
Features
Circuit Simplicity
1 Watt of Audio Output
Duplex operation with only one two-wire cable as
interconnect.
Note
1. All resistor values in ohms.
7-136
IlA759 • IlA77000
High Slew Rate Power OP Ampl Audio Amp
AG Servo Amplifier - Bridge Type
C
5k
50k
v, ----;iil-""I\i-.,.----w..-,
+28 V
300
10pF
10 k
+28 V
t - - - - Vo
5.1 k
V,-'VV'....-........
-"""I'¥-..,...--I
PO(MAX) (8 0) - 18 W
5.1 k
2 PHASE
SERVOMOTOR
-13V
~0.47"F
10k
Features
High Slew Rate 9 V/IlS
High 3 dB Power Bandwidth 85 kHz
18 Watts Output Power Into an 8
Load.
Low Distortion-.2%, 10 VRMS, 1 kHz Into 8
n
Features
Gain of 10
Use of 1lA759 Means Simple Inexpensive Circuit
n
Design Consideration
Av>10
Design Considerations
325 mA Max Output Current
Servo Applications
DC Servo Amplifiers
5k
50 k
V,
1
Features
Circuit Simplicity
One Chip Means Excellent Reliability
Design Considerations
10<325 mA
Note
1. All resistor values in ohms.
7-137
IlA759 • IlA77000
Regulator Applications
Adjustable Dual Tracking Regulator
+y,--------------,
+7Y to +35 Y
+Yo
1 "F
5.6 k
1%
GND
2k
2"F
1 "F
-V,
IN
!'A79MG
-7Yto-35V
5.6 k
1%
25k
OUT
-Yo
Features
Wide Output Voltage Range (± 2.2 to ± 30 V)
Excellent Load Regulation AVo < ± 5 mV for
Alo = ±0.2 A
Excellent Line Regulation AVo < ±2 mV for AVI = 10 V
Note
1. All resistor values in ohms.
7·138
p.A759 • p.A77000
Regulator Applications (Cont.)
10 Amp -12 Volt Regulator
15-2~IV_"""'_ _" " " ' - - - - - - - '
R1
12
Q1
2N2907
Q2
_125
o
I"F
r-I
R2
1~9300
I
I
I
-=2k
I
--.J
Q4
2N2612
R4
0.03 !l
12k
Vo- 12V
RS
Uk
R6
3k
Features
Excellent Load and Line Regulation
Excellent Temperature Coefficient-Depends
Largely on Tempco of the Reference Zener
Note
1. All resistor values in ohms.
7-139
p,A771
Operational Amplifier
F=AIRCHIa...D
A Schlumberger Company
Linear Division Operational Amplifiers
Description
This monolithic JFET Input Operational Amplifier incorporates well matched ion implanted JFETs on the same chip
with standard bipolar transistors. The key features of this
op amp are low input bias current in the sub nanoamp
range plus high slew rate (13 V / p.s typically) and wide
bandwidth (3.0 MHz typically).
•
•
•
•
Connection Diagram
8-Lead DIP and SO-8 Package
(Top View)
+OFFSET
NULL
-IN
Low Input Bias Current - 200 pA
Low Input Offset Current - 100 pA
High Slew Rate - 13 V I p.s Typically
Wide Bandwidth - 3.0 MHz Typically
Absolute
Maximum
+IN
v-
Ratings
Storage Temperature. Range
Ceramic DIP
Molded DIP and SO-8
Operating Temperature Range
Extended (pA771 AM, pA771BM)
Commercial (pA771C, pAn1AC,
pA771BC, pA77tLC)
Lead Temperature
Ceramic DIP (soldering, 60 8)
Molded DIP and S0-8
(soldering, lOs)
Internal Power Di8sipation 1,2
8l,..CeramiC DIP
8L-Molded DIP
SO-8
Supply VeI1age
Differential Inrt Voltage
Input Voltage
Output.ShortCircuit Duration
OUT
-OFFSET
NULL
CDOO761F
-65·C to + 175·C
-65·C to + 150°C
~55·C
to + 125°C
O·C to +70·C
300°C
265°C
1.30 W
0.93 W
0.81 W
±18 V
30 V
±16 V
Indefinite
Order Information
Device Code
MA771RC
MA771SC
pA771TC
pA771ARM
pA771ARC
pA771ASC
pA771ATC
pA771BRM
pA771BRC
pA771BSC
pA771BTC
MA771LRC
pA771LSC
pA771 LTC
Notft
1. TJ _=150"C lor the MOldlld OIPai"ld so.e, and 17SoC for the
CeiarI1ie OIP.
2 . Rltlingsapplyto .ambl$t11:1!1tnperalure4t25°C•. AbOve this temperature,
detatethe 8L·Qeramic 011> at fn rrNVN;,. the SL-Moided DIP at
7.5.mwrC~andtheSO-8 at6.5mWrC.
3. unless0th9/Wise speCified theab.soIut& maximum negative input voltage
1$ equal to tht\ negative powersupptyvOltage:.
, we
7-140
Package Code
6T
KC
9T
6T
6T
KC
9T
6T
6T
KC
9T
6T
KC
9T
Package Description
Ceramic DIP
Molded Surface Mount
Molded DIP
Ceramic DIP
Ceramic DIP
Molded Surface Mount
Molded DIP
Ceramic DIP
Ceramic DIP
Molded Surface Mount
Molded DIP
Ceramic DIP
Molded Surface Mount
Molded DIP
IlA771
Equivalent Circuit
r---------------~----------~~~--------~----------------------.-----~----~v+
J6
R5
OUT
Q24
R8
R18
~-4____~--t_~--~~~~--~~--~------~~--------------~-----+--~v- OFFSET NULL
+ OFFSET NULL
7-141
IlA771
MA771 and MA771L
Electrical Characteristics T A = 25°C, Vee = ± 15 V, unless otherwise specified.
DC Characteristics
p.A771
Symbol
Characteristic
Condition
Via
Input Offset Voltage
110
Input Offset Current1
VCM=O V, TJ=25°C
liB
Input Bias Current1
VCM = 0 V, TJ = 25°C
21
Input Impedance
Icc
Supply Current
los
Output Short Circuit
Current
Avs
Large Signal Voltage
Gain
Min
Typ
VCM = 0 V, Rs = 50 n
50
p.A771L
Max
Unit
10.0
15.0
mV
100
100
pA
200
pA
Max
Min
200
Typ
50
1012
1012
2.8
2.8
25
Va = ± 10 V, RL > 2.0 kn
50
100
n
50
mA
25
mA
100
V/mV
The following specifications apply for O°C';;;; TA .;;;; + 70°C, Vcc = ± 15 V
Via
Input Offset Voltage
VCM = 0 V, Rs = 50 n
/lVlo//lT
Input Offset Voltage
Temperature Sensitivity
Rs=50n
110
Input Offset Current1
VCM =0 V
4.0
4.0
liB
Input Bias Current1
VCM =0 V
8.0
8.0
nA
3.0
3.0
mA
20
13
10
10
mV
/lVrC
nA
Icc
Supply Current
CMR
Common Mode Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection
Ratio
Vcc=±10 V to ±18 V,
Rs=50n
70
70
dB
Avs
Large Signal Voltage
Gain
Vo=±10 V, RL>2.0 kn
25
25
V/mV
VoP
Output Voltage Swing
RL = 10 kn
±12
±12
RL = 2.0 kn
±10
±10
VCM = ± 11 V, Rs = 50 n
70
± 11
7-142
70
+15
-12
± 11
dB
+15
-12
V
V
f.lA771
MA771A and MA771B
Electrical Characteristics TA = 25 DC, Vee = ± 15 V, unless otherwise specified.
DC Characteristics
IlA771 A
Symbol
Characteristic
Condition
Via
Input Offset Voltage
VCM = 0 V, Rs = 50
110
Input Offset Current 1
VCM = 0 V, TJ = 25°C
Current 1
lis
Input Bias
ZI
Input Impedance
Icc
Supply Current
los
Output Short Circuit
Current
Avs
Large Signal Voltage
Gain
Min
Typ
n
50
VCM = 0 V, TJ = 25°C
IlA771B
Max
Max
Unit
2.0
Min
5.0
mV
50
50
pA
100
pA
2.8
mA
100
Typ
50
2.8
25
Vo=±10 V, RL;;'2.0
kn
50
n
10 12
1012
100
50
25
mA
100
V/mV
The following specifications apply for 0°C2.0 kn
50
50
V/mV
VOP
Output Voltage Swing
RL = 10 kn
±12
±12
RL = 2.0 kn
±10
±10
50
100
50
1012
1012
2.S
± 11
The following specifications apply for -55°C
< TA < + 125°C,
± 11
+15
-12
n
+15
-12
V
V
VCC = ± 15 V
VIO
Input Offset Voltage
VCM = 0 V, Rs = 50 n
~Vlo/~T
Input Offset Voltage
Temperature Sensitivity
Rs=50 n
S.O
110
Input Offset Current 1
VCM =0 V
20
20
nA
liS
Input Bias Current1
VCM = 0 V
50
50
nA
3.4
rnA
5.0
10
mV
JlVo IC
10
Icc
Supply Current
CMR
Common Mode Rejection
VCM=±11 V, Rs=50 n
SO
SO
dB
PSRR
Power Supply Rejection
Ratio
Vcc=±10 V to ±1S V,
Rs = 50 n
SO
SO
dB
Avs
Large Signal Voltage
Gain
Vo = ± 10 V, RL>2.0 kn
25
25
V/mV
VOP
Output Voltage Swing
RL = 10 kn
±12
±12
RL = 2.0 kn
±10
±10
3.4
7·144
V
p.A771
J.LA771 (Cant.)
Electrical Characteristics TA
= 25°C,
= ± 15
Vee
V, unless otherwise specified.
AC Characteristics
All Grades
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
BW
Bandwidth
(Figure 2) Av = -10
3.0
SR
MHz
Slew Rate
(Figure 1)
13
V//ls
en
Input Noise Voltage
Rs = 100 [2, f = 1000 Hz
16
nV/YHz
in
Input Noise Current
f = 1000 Hz
0.01
pA/YHz
Note
operation the junction temperature rises above the ambient temperature
as a result of internal power dissipation, Po· T J =TA + 8JA PO where 8JA
is the thermal resistance from junction to ambient. Use of a heat sink is
recommended if input bias current is to be kept to a minimum.
1. The input bias currents are junction leakage currents which
approximately double for every 1aoc increase in the junction
temperature, TJ. Due to limited production test time, the input bias
currents measured are correlated to junction temperature. In normal
Typical Performance Curves
Output Voltage Swing vs
Load Resistance
140
0
Vee I", :l:15V
TA = 25°C
~ 25
/
II
>
C>
z
20
~
15
V
"I 100 h
o
.
>
0
~
'"
~
o
~
g
S
z
&
./
5
O.S
0.1
5.0
1.0
OUTPUT LOAD·
10
32
12
::I
f\
100 K
1.0M
"'
'"
~180 ~
'-,
"\
10
100
"'" 2.
..
5
'"
4
~
3
V
'"C>
<
2
~
1
z
10M
•
-75
/
.
....~" ,
.
>
7
i7
0
o
o
20
15
10
Hz
SUPPLY VOLTAGE •
±v
Slew Rate vs Temperature
7
III
v
z
!j;
::I
1.0K 10K 100K 1.0M 10M 100M
~
'"a:C>
~135 ~
11:
20
8a:
<
0
FREQUENCY - Hz
"'
~
.
~
10 K
~'"'1-"
',"
...g
,.
1.0 K
\'"Q
::l
25
20
o
"-9.
·90
Gain Bandwidth Product vs
Temperature
!;!
RL = 1OkO
TA = 25°C
~ 24
::I
"'
FREQUENCY
v~J lUv
28
....'"
60
n
Maximum Undistorted Output vs
Frequency
z
!j;
PHASE
"-
·20
1.0
0
C>
"'~
80
0.
>
·45
.. 4.
/
~
!;
. 3.
III
I
!:;
>
40
120
C>
'"~
Output Voltage Swing vs
Supply Voltage
Open Loop Frequency Response
v.!c = ~'5V
20
..... 1'-..
"-
r-.........
.........
.........
~50
~25
"'" r---..
t--.... I
25
r- t--
SO
TEMPERATURE -"C
7-145
75
100
10
125
5
-75
-so
-25
25
"'" f""-.... ....
50
TEMPERATURE-OC
75
100
125
p.A771
Typical Performance Curves (Cont.)
Input Bias Current vs
Case Temperature
Small Signal Pulse Response
70
Vee
>
E
"~
0
>
30
20
0
10
(\
90%/ T
V I
40
....
i....
100M
TA = 25"C
50
,;,
=
±15V
RL= 20
CL = 100pF
60
L
::>
10% /
r--
r5
a:
50
~
m 100
i
~
100
125
150
175
",V
-
15
E
>
w
g
~~
~#
o~
:&
z
~~
&Ci
5
o
o
10
15
SUPPl y VOLTAGE - ±V
20
~ 4.0
a:
§
o
o
'!;!
It
5
/
0
50
75
100
125
o
!i
sz
.........
3.0
-
r-
~ 2.0
::>
"'1.•
-so
-25
25
50
TEMPERATURE·OC
7-146
75
o
-1
TIME AFTER POWER SUPPLY TURN-ON _ MINUTES
1 5.•
100
:&
:&
o
V / '"
0
..'"
150
u"/ /
z
0 10
:&
:&
0
'!;!
~
V
0
:&
25
v,!, = ;,5V
w
w
0
V
,/
/'
Supply Current vs Temperature
20
>
w
/'
/
CASE TEMPERATURE - °C
Maximum Common Mode Input
Voltage vs Supply Voltage
C
V
V
TIME Mn.
""~
1 '50
'"
10K
a:
,I
75
G
ij 1.0K
RISEn'ME = 60 os
vc~ = .},5V
TAo = 25 e
/
....
1.0
25
200
Vc~ = .,',5V
l100K
j/
-10
-25
Bias Current Warm up Change
100
125
JlA771
Test Circuit
Input Offset Voltage Null Circuit
v-
Typical Applications
Figure 1 Unity Gain Amplifier
Figure 2 Gain-of-10 Inverting Amplifier
lOkI!
1 kl!
V,-W..------1
V,
RL
2 kll
RL
2kU
O'I01t31F
7-147
iJ.A772
Dual
Operational Amplifier
FAIRCHIL.D
A Schlumberger Company
Linear Division Operational Amplifiers
Description
This monolithic JFET Input operational amplifier incorporates well matched ion implanted JFETs on the same chip
with standard bipolar transistors. The key features of this
op amp are low input bias current in the sub nanoamp
range plus high slew rate (13 V/ IlS typically) and wide
bandwidth (3.0 MHz typically).
•
•
•
•
Connection Diagram
8-Lead DIP and SO-8 Package
(Top View)
v+
aUTB
Low Input Bias Current - 200 pA
Low Input Offset Current - 100 pA
High Slew Rate-13 V/jJ.S Typically
Wide Bandwidth - 3.0 MHz Typically
+INA
-INB
+INS
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP and SO-8
Operating Temperature Range
Extended (IlA772AM, p.A772BM)
Commercial (p.A772C, p.A772AC,
p.A772BC, p.A772LC)
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP and SO-8
(soldering, 10 s)
Internal Power Dissipation 1. 2
8L-Ceramic DIP
8L-Molded DIP
SO-8
Supply Voltage
Differential Input Voltage
Input VoltageS
Output Short Circuit Duration
-65°C to + 175°C
-65°C to + 150°C
- 55°C to + 125°C
O°C to +70°C
300°C
265°C
1.30 W
0.93 W
0.81 W
±18 V
30 V
±16 V
Indefinite
Order Information
Device Code
p.A772RC
p.A772SC
p.A772TC
p.A772ARM
p.A772ARC
p.A772ASC
p.A772ATC
p.A772BRM
p.A772BRC
p.A772BSC
p.A772BTC
IlA772LRC
IlA772LSC
IlA772LTC
Notes
1. TJ Max = IS0·C for the Molded DIP and SO·B. and 17S·C for the
Ceramic DIP.
2. Ratings apply to ambient temperature at 2S·C. Above this temperature,
derate the Bl-Ceramic DIP at B.7 mWrC, the Bl-Molded DIP at
7.5 mWrC, and the SO-B at 6.5 mWrC.
S. Unless otherwise specified the absolute maximum negative input voltage
is equal to the negative power supply voltage.
7-148
Package Code
6T
KC
9T
6T
6T
KC
9T
6T
6T
KC
9T
6T
KC
9T
Package Description
Ceramic DIP
Molded Surface Mount
Molded DIP
Ceramic DIP
Ceramic DIP
Molded Surface Mount
Molded DIP
Ceramic DIP
Ceramic DIP
Molded Surface Mount
Molded DIP
Ceramic DIP
Molded Surface Mount
Molded DIP
IlA772
Equivalent Circuit (112 of Circuit)
r---------------~----------~~._--------~----------------------._----~----~v+
Rl
R2
r-~~~-----------r-Q3
J6
RS
R16
L-~~--~~--~--~--~------~~--_4--------+_--------------_+------~--4_v-
7-149
IlA772
~772 and MA772L
Electrical Characteristics T A = 25°C, Vee = ± 15 V, unless otherwise specified.
DC Characteristics
iJ.A772L
J.LA772
Symbol
Characteristic
Condition
Min
Typ
Max
Min
Typ
Max
Unit
VIO
Input Offset Voltage
VCM = 0 V, Rs = 50 Q
10.0
15.0
mV
110
Input Offset Current1
VCM = 0 V, TJ = 25°C
100
100
pA
lis
Input Bias Current1
VCM=O V, TJ=25°C
200
pA
2.8
mA
ZI
Input Impedance
Icc
Supply Current
(Per Amplifier)
los
Output Short Circuit
Current
Avs
Large Signal Voltage
Gain
50
200
50
10 12
10 12
2.8
25
Vo=±10 V, RL~2.0 kQ
50
100
50
Q
25
mA
100
V/mV
The following specifications apply for Vcc = ± 15 V, O°C ~ TA ~ + 70°C
VIO
Input Offset Voltage
VCM = 0 V, Rs= 50 Q
13
20
!;,.VloI!;,.T
Input Offset Voltage
Temperature Sensitivity
Rs=50 Q
110
Input Offset Current1
VCM = 0 V
4.0
VCM =0 V
8.0
8.0
nA
3.0
3.0
mA
10
mV
iJ.V/oC
10
4.0
nA
lis
Input Bias Current 1
Icc
Supply Current
(Per Amplifier)
CMR
Common Mode
Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection
Ratio
Vcc=±10 V to ±18 V,
Rs=50 Q
70
70
dB
Avs
Large Signal Voltage
Gain
Vo = ± 10 V, RL~2.0 kQ
25
25
V/mV
VOP
Output Voltage Swing
RL = 10 kQ
±12
±12
RL = 2.0 kQ
±10
±10
VCM = ± 11 V, Rs = 50 Q
70
± 11
7-150
70
+15
-12
± 11
dB
+15
-12
V
V
pA772
MA772A and MA772B
Electrical Characteristics TA = 25°C, Vee = ± 15 V, unless otherwise specified.
DC Characteristics
JiA772B
JiA772A
Symbol
Via
Characteristic
Condition
Input Offset Voltage
VCM = 0 V, Rs = 50
Current 1
110
Input Offset
liB
Input Bias Current 1
ZI
Input Impedance
Icc
Supply Current
(Per Amplifier)
los
Output Short Circuit
Current
Avs
Large Signal Voltage
Gain
Min
Typ
kn
Max
Min
Typ
2.0
50
VCM = 0 V, TJ = 25°C
50
VCM = 0 V, TJ = 25°C
50
100
2.8
50
mV
50
pA
100
pA
n
2.8
25
kn
Unit
5.0
10 12
1012
Vo=±10 V, RL;;'2.0
Max
100
50
mA
25
mA
100
V/mV
The following specifications apply for O°C < TA < + 70°C, Vcc = ± 15 V
n
Via
Input Offset Voltage
VCM = 0 V, Rs = 50
iJ.VloliJ.T
Input Offset Voltage
Temperature Sensitivity
Rs= 50
110
Input Offset Current1
VCM =0 V
2.0
2.0
nA
liB
Input Bias Current1
VCM =0 V
4.0
4.0
nA
Icc
Supply Current
(Per Amplifier)
3.0
3.0
mA
CMR
Common Mode
Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection
Ratio
Rs=50
± 18 V
Avs
Large Signal Voltage
Gain
Vo=±10V, RL;;' 2.0
VoP
Output Voltage Swing
RL = 10
Rs=50
4.0
n
n,
VCM=±11 V
80
± 11
RL = 2.0
n,
7.0
10
Vcc=±10 V to
kn
kn
kn
7-151
dB
80
+15
-12
± 11
mV
JiV/oC
10
+15
-12
V
80
80
dB
25
25
V/mV
±12
±12
±10
±10
V
J.lA772
J.LA712AM and J.LA712BM
Electrical Characteristics TA = 25°C, Vee = ± 15 V, unless otherwise specified.
DC Characteristics
JlA772BM
J..LA772AM
Symbol
Characteristic
Condition
VIO
Input Offset Voltage
VCM = 0 V, Rs = 50 .11
110
Input Offset Current 1
VCM = 0 V, TJ = 25°C
liS
Input Bias Current1
VCM = 0 V, TJ = 25°C
ZI
Input Impedance
Icc
Supply Current
(Per Amplifier)
VIR
Input Voltage Range
Min
Typ
Max
Min
Typ
2.0
50
50
100
Unit
5.0
mV
50
pA
50
100
pA
2.8
rnA
.11
10 12
1012
2.8
± 11 V, Rs = 50 .11
Max
+11
+15
+11
+15
-11
-12
-11
-12
V
80
80
dB
Vcc=±10 V to ±18 V,
Rs = 50 .11
80
80
dB
large Signal Voltage
Gain
Vo=±10 V, RL;;;' 2.0 k.l1
50
50
V/mV
Output Voltage Swing
RL = 10 k.l1
±12
±12
RL = 2.0 k.l1
±10
±10
CMR
Common Mode
Rejection
VCM =
PSRR
Power Supply Rejection
Ratio
Avs
VOP
V
The following specifications apply for Vcc = ± 15 V, -55°C <; TA <; 125°C
Via
Input Offset Voltage
VCM = 0 V, Rs <; 50 .11
LiVia/LiT
Input Offset Voltage
Temperature Sensitivity
Rs = 50 .11
110
Input Offset Current 1
VCM = 0 V
20
20
liS
Input Bias Current 1
VCM= 0 V
50
50
nA
Icc
Supply Current
(Per Amplifier)
3.4
3.4
rnA
CMR
Common Mode
Rejection
VCM = ± 11 V, Rs = 50 .11
80
80
dB
PSRR
Power Supply Rejection
Ratio
Vcc=±10 V to ±18 V,
Rs = 50 .11
80
80
dB
Avs
large Signal Voltage
Gain
Vo=±10 V, RL;;;' 2.0 k.l1
25
25
V/mV
VOP
Output Voltage Swing
RL = 10 k.l1
±12
±12
RL = 2.0 k.l1
±10
±10
5.0
8.0
7-152
mV
JlVo/C
10
10
nA
V
MA772
Electrical Characteristics (Cont.) Vee = ± 15 V, TA = 25°C
AC Characteristics
All Grades
Symbol
Characteristic
Typ
Min
Condition
Max
Unit
3.0
BW
Bandwidth
(Figure 2) Av
-10
SR
Slew Rate
(Figure 1)
13
V/l1s
en
Input Noise Voltage
Rs = 100 .11, f = 1000 Hz
16
nV/YHz
in
Input Noise Current
f = 1000 Hz
0.01
pA/YHz
=
MHz
Note
1. The input bias currents are junction leakage currents which
approximately double for every 1DOC increase in the junction
temperature, TJ. Due to limited production test time, the input bias
currents measured are correlated to junction temperature. In normal
operation the junction temperature rises above the ambient temperature
as a result of internal power dissipation, Po. TJ = TA + 8JAPO where 8JA
is the thermal resistance from junction to ambient. Use of a heat sink is
recommended if input bias current is to be kept to a minimum.
Typical Performance Curves
Output Voltage Swing vs
Load Resistance
30
Vee l=
..
TA
:
~'5~
=25°C
z
I
20
~
-
,r
25
Cl
Output Voltage Swing vs
Supply Voltage
.
~
/
120
III
I 100
30
z
~
w
10
~g
~
~
....
./
5.0
1.0
OUTPUT LOAD·
RL
TA
i,
=1QkO
=25"C
....
g
g
16
e~
"
12
1.0M
~
10M
,
~'"1-"
w
-180 ~
~
20
IE
'r-...
1.0
10
100
"
1.0K 10K 100K 1.0M 10M 100M
FREQUENCY - Hz
Slew Rate vs Temperature
.
5
v~ = ~'5V
20
"'-.
4
.........
3
r-.....
1
o
-75
-50
-25
25
50
TEMPERATURE- QC
7-153
75
100
"
..........
........
------
!z
[\
100 K
40
"'0.
7
~
z
FREQUENCY - Hz
..
,
"'
~
25
~ 24
10 K
20
15
10
Gain Bandwidth Product vs
Temperature
>
1.0K
" ...
SUPPLY VOLTAGE -:tV
~ 20
o
60
*
10
v~J lUv
28
PHASE
-20
n
Maximum Undistorted Output vs
Frequency
32
g
z
,I'
0
0.5
0.1
;!
§
L/
10
::>
o
w
·45
~
Cl
/
o
~
80
~
V
20
....
/
::>
o
~
/
Cl
15
;
i
....
'"
~
....
::>
o
140
~
w
Cl
Open Loop Frequency Response
40
..........
. . . 1"---
10
125
~
5
75
·50
25
25
50
TEMPERATURE- °C
75
100
125
IlA772
Typical Performance Curves (Cont.)
Input Bias Current vs
Case Temperature
Small Signal Pulse Response
Vee
0
..
0
S
30
...>
=
:t:15V
RL=2fl
CL = 100pF
TA = 25°C
0
"~
1.0M
f\
/
~ 20
10
f-
/
~100
'.0
0
/'
V
!;
.. '0
!
J
V
/"/'
~ I--'"
o
-1 0
-25
25
50
75
TIME
100
125
150
= 25°C
1 150
/
10K
G1.0K
,I
VC~ = %1'5 V
TA
...
ffi
II:
II:
RISETJME == SOns
10~/V'
vo:, = "I'5V
t100K
r--
90%1 T
V I
!;
o
Bias Current Warm up Change
200
0
175
25
50
75
100
125
-1
CASE TEMPERATURE _ (Ie
~".
3
4
7
TIME AFTER POWER SUPPLY TURN-ON _ MINUTES
PC02911F
Maximum Common Mode Input
Voltage vs Supply Voltage
."
.~
.
.
15
v"/
ff-'"
:
150
>
/
0
~~
fP
'"
''o""
...
~ 10
V /
5
5
/
in
~
o
o
~
Z
"'!§II: 3.0
100
~,.
()
15.0
0
'"
'"
u
...'"
<\~+.-
.qoq.
~= ~'5V
~
V
o
o
~
Supply Current vs Temperature
20
4.0
u
.
.g
0
~ 2.0
>
:>
;:
...........
(I)
-
---I--..
1.0
z
10
15
20
SUPPLY VOLTAGE - ±V
0
-so
-25
25
50
75
100
125
TEMPERATURE -"C
Typical Applications
Figure 2 Gain-of-10 Inverting Amplifier
Figure 1 Unity Gain Amplifier
'Ok!!
, k!!
V,--¥./Ir......_-I
V,
Cl
Al
100 pF
2 kH
Al
2k!!
7-154
JlA774
Quad
FAIRCHILD
A Schlumberger Company
Operational Amplifier
Linear Division Operational Amplifiers
Description
Connection Diagram
4-Lead DIP and 50-14 Package
(Top View)
This monolithic JFET Input Operational Amplifier incorporates well matched ion implanted JFET on the same chip
with standard bipolar transistors. The key features of this
op amp are low input bias current in the sub nanoamp
range plus high slew rate (13 V I IlS typically) and wide
bandwidth (3.0 MHz typically).
•
•
•
•
OUT A
Low Input Bias Current - 200 pA
Low Input Offset Current -100 pA
High Slew Rate-13 VIIlS Typically
Wide Bandwidth - 3.0 MHz Typically
-IN A
-IN 0
+IN A
+IN 0
v-
v+
+IN B
+IN C
-IN B
-IN C
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP and SO-14
Operating Temperature Range
Extended (J1A774M, IlA774BM)
Commercial (J1A774C, IlA774BC,
IlA774LC)
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP and SO-14
(soldering 10 s)
Internal Power Dissipation 1, 2
14L-Ceramic DIP
14L-Molded DIP
SO-14
Supply Voltage
Differential Input Voltage
Input Voltage 3
Output Short Circuit Duration
-65°C to + 175°C
-65°C to + 150°C
OUT C
Order Information
Device Code
IlA774DM
I.lA774DC
IlA774PC
IlA774SC
IlA774BDM
IlA774BDC
IlA774BPC
IlA774LDC
IlA774LPC
1.36 W
1.04 W
0.93 W
± 18 V
30 V
± 16 V
Indefinite
NOles
1. TJ Max ~ 150·C for the Molded DIP and 50-14, and 175·C for the
Ceramic DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 14L-Ceramic DIP at 9.1
the 14L-Molded DIP at
8.3
and the 50-14 at 7.5 mwrc.
3. Unless otherwise specified the absolute maximum negative input voltage
is equal to the negative power supply voltage.
mwrc,
mwrc,
7-155
Package Code
7A
7A
9A
KD
7A
7A
9A
7A
9A
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
Molded Surface Mount
Ceramic DIP
Ceramic DIP
Molded DIP
Ceramic DIP
Molded DIP
p.A774
Equivalent Circuit (1/4 of Circuit)
r---------------~----------~~._--------~----------------------~----~----~v+
Rl
R2
r-~~~-----------r-Q3
J6
RS
R16
~~~--~~--_4--~~__~----~~+_--_+--------~----------------+_------+_
7-156
__
~v-
J.l.A774
J1A774, J1A774L
Electrical Characteristics TA = 25°C, Vee = ± 15 V, unless otherwise specified.
DC Characteristics
MA774L
J.LA774
Symbol
Characteristic
Condition
Input Offset Voltage
VCM = 0 V, Rs=50
110
Input Offset Current 1
VCM = 0 V, TJ = 25°C
VCM = 0 V, TJ = 25°C
liB
ZI
Input Impedance
Icc
Supply Current
(Per Amplifier)
los
Output Short Circuit
Current
Avs
Large Signal Voltage
Gain
Typ
n
VIO
Input Bias Current 1
Min
50
Max
Unit
10.0
15.0
mV
100
100
pA
200
pA
2.8
mA
Max
Min
200
Typ
50
1012
2.8
25
Vo=±10 V, RL=2.0
kn
50
n
10 12
100
50
25
mA
100
V/mV
The following specifications apply for O°C < TA < + 70°C, Vcc = ± 15 V
VIO
Input Offset Voltage
VCM = 0 V, Rs = 50
!::Nlol LlT
Input Offset Voltage
Temperature Sensitivity
Rs = 50
110
Input Offset Current1
VCM =0 V
Current 1
n
13
n
20
10
liB
Input Bias
Icc
Supply Current
(Per Amplifier)
CMR
Common Mode
Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection
Ratio
Vcc=±10 V to ±18 V, Rs=50
Avs
Large Signal Voltage
Gain
Vo=±10 V, RL>2.0
VOP
Output Voltage Swing
RL = 10
VCM =0 V
VCM = ± 11 V, Rs = 50
n
70
± 11
kn
kn
RL = 2.0 kn
7-157
n
4.0
nA
8.0
8.0
nA
3.0
3.0
mA
70
+15
-12
MV/oC
10
4.0
mV
± 11
dB
+15
-12
V
70
70
dB
25
25
V/mV
±12
±12
±10
±10
V
p.A774
JJ.A774A, JJ.A774B
Electrical Characteristics TA = 25°C, Vee = ± 15 V, unless otherwise specified.
DC Characteristics
IJA774A
Symbol
Characteristic
Condition
V,o
Input Offset Voltage
VCM = 0 V, Rs = 50
kn
1'0
Input Offset Current1
VCM = 0 V, TJ = 25°C
I'B
Input Bias Current 1
VCM=O V, TJ=25°C
Z,
Input Impedance
Icc
Supply Current
(Per Amplifier)
los
Output Short Circuit
Current
Avs
Large Signal Voltage
Gain
Min
Typ
IJA774B
Max
Min
Typ
2.0
50
50
100
50
1012
25
The following specifications apply for Vcc
= ± 15
V, O°C < TA
kn
50
mV
50
pA
100
pA
2.8
mA
n
50
25
mA
100
V/mV
< + 70°C
4.0
Input Offset Voltage
VCM = 0 V, Rs = 50
LlV,ol LlT
Input Offset Voltage
Temperature Sensitivity
Rs =50
1'0
Input Offset Current 1
VCM = 0 V
I'B
Input Bias Current1
VCM=O V
Icc
Supply Current
(Per Amplifier)
CMR
Common Mode
Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection
Ratio
Vcc=±10 V to ±18 V, Rs=50
Avs
Large Signal Voltage
Gain
Vo=±10 V, RL~2.0
VoP
Output Voltage Swing
RL = 10
n
7.0
10
n
80
kn
kn
kn
7-158
n
2.0
nA
4.0
4.0
nA
3.0
3.0
mA
80
+15
-12
mV
IJV/oC
10
2.0
± 11
RL = 2.0
100
n
V,o
VCM=±11 V, Rs=50
Unit
5.0
10 12
2.8
Vo=±10 V, RL~2.0
Max
± 11
dB
+15
-12
V
80
80
dB
25
25
V/mV
±12
±12
V
±10
±10
IlA774
/JA774AM, /JA774BM
Electrical Characteristics T A = 25°C, Vee
= ± 15
V, unless otherwise specified.
DC Characteristics
iJ.A774AM
Symbol
Characteristic
Condition
Min
Typ
iJ.A774BM
Max
Min
Max
Unit
VIO
Input Offset Voltage
VCM = 0 V, Rs = 50 Q
2.0
5.0
mV
110
Input Offset Current1
VCM = 0 V, TJ = 25°C
50
50
pA
lis
Input Bias Current 1
VCM = 0 V, TJ = 25°C
100
pA
ZI
Input Impedance
Icc
Supply Current
(Per Amplifier)
2.8
mA
VIR
Input Voltage Range
CMR
Common Mode
Rejection
VCM = ± 11 V, Rs = 50 Q
80
80
dB
PSRR
Power Supply Rejection
Ratio
Vcc = ± 10 V to ± 18 V, Rs = 50 Q
80
80
dB
Avs
Large Signal Voltage
Gain
Vo=±10V, RL > 2.0 kQ
50
50
V/mV
VOP
Output Voltage Swing
RL = 10 kQ
±12
±12
RL =2.0 kQ
±10
±10
50
100
Typ
50
1012
1012
2.8
± 11
± 11
+15
-12
Q
+15
-12
V
V
The following specifications apply for -55°C';;; TA';;; + 125°C, VCC = ± 15 V
Input Offset Voltage
VCM=O V, Rs';;;50 Q
Input Offset Voltage
Temperature Sensitivity
Rs =50 Q
110
Input Offset Current 1
VCM =0 V
lis
Input Bias Current 1
VCM = 0 V
Icc
Supply Current
(Per Amplifier)
3.4
CMR
Common Mode
Rejection
VCM=±11 V, Rs=50 Q
80
80
dB
PSRR
Power Supply Rejection
Ratio
Vcc=±10 V to ±18 V, Rs=50 Q
80
80
dB
Avs
Large Signal Voltage
Gain
Vo=±10 V, RL>2.0 kQ
25
25
VlmV
VOP
Output Voltage Swing
RL = 10 kQ
±12
±12
RL = 2.0 kQ
±10
±10
VIO
aVlo/aT
5.0
8.0
mV
iJ.vo/C
20
20
nA
50
50
nA
3.4
mA
10
7-159
10
V
IlA774
Electrical Characteristics (Cont.) TA = 25°C, Vee = ± 15 V
AC Characteristics
All Grades
Symbol
Characteristic
Condition
BW
Bandwidth
(Figure 2) Av = -10
SR
Slew Rate
(Figure 1)
en
Input Noise Voltage
Rs = 100
in
Input Noise Current
f= 1000 Hz
n,
Min
Typ
Unit
Max
3.0
MHz
13
V//ls
16
nV/YHz
0.01
pA/YHz
f = 1000 Hz
Note
operation the junction temperature rises above the ambient temperature
as a result of internal power dissipation, Po. TJ = TA + 8JAPo where (JJA
is the thermal resistance from junction to ambient. Use of a heat sink is
recommended if input bias current is to be kept to a minimum.
1. The input bias currents are junction leakage currents which
approximately double for every 1COC increase in the junction
temperature, TJ. Due to limited production test time, the input bias
currents measured are correlated to junction temperature. In normal
Typical Performance Curves
Output Voltage Swing vs
Load Resistance
30
Vee l=
TA
A
I.. 25
>
"i
Z
'"
140
;'5~
= 25°C
120
/'
II
20
~
/
I 100
~
>
..
h
~
15
!j
50
..
40
g
10
~
!/
;)
I-
~
/
;)
0
PHASE
'\
0.5
0.1
~'-",
5.0
1.0
-20
1.0
10
I
I-
g
8
• 20
i
z
I
~ 12
I-
;)
o
"'z
1\
~
o
lOOk
FREQUENCY - Hz
il:
I-
/
K
10
I-
V
;)
\
100
V
g
o
1.0K 10K 100K 1.0M 10M 100M
0
5
1.0M
V~c = ~'5V
10M
"-~
I"-
~
3
--
.........
2
r-- :---.
.......
i'-..
....... --....--.
10
1
0
-75
·50
·25
25
50
TEMPERATURE·OC
7-160
20
Slew Rate vs Temperature
20
..........
15
10
SUPPLY VOLTAGE· ±V
6
::c 4
16
I-
10k
;
0.
i
AL == 10kO
TA=WC
~ 24
1.0k
~ 20
-180 ~
"10
/
25
>
'"
"
Gain Bandwidth Product vs
Temperature
V~c J lUv
28
~
FREQUENCY - Hz
Maximum Undistorted Output vs
Frequency
32
"'
~
20
V
"z
1-"
OUTPUT LOAD - 0
"i
"'
""-9,
o
o
.
I..
> 30
-45
~
0.
l-
I-
40
80
~
0.
""
S
Output Voltage Swing vs
Supply Voltage
Open Loop Frequency
Response
75
100
125
-
5
75
50
25
25
50
TEMPERATURE·OC
75
100
125
p.A774
Typical Performance Curves (Cont.)
Input Bias Current vs
Case Temperature
Small Signal Pulse Response
70
CL
TA
~ 50
= 100pF
=25"C
~
S
>
30
"
20
10
~
h
/
0-
o
1.0M
0-
e::
~
60na
I
i.
5
!
100
10
1.0
-10
-25
25
50
75
100
125
150
-75
175
/
...
"
.S
15
.d/
10'"
z
,p4'
10
:IE
:IE
."
15~
g
/
:IE
z
~~f(,
100
:IE
:IE
~t;
0
>
>=
~
~~
~
:IE
0
..
V
0
o
".>
V /
5
;;
.
5
/
0
o
o
/~
-
/
V
-so
-25
25
50
75
100
o
125
-1
~
lilz
10
4
TIME AFTER POWER SUPPLY TURN-ON -
Supply Current vs Temperature
20
0
/
CASE TEMPERATURE - DC
0-
>
/'
V
TIME -ns
Maximum Common Mode Input
Voltage vs Supply Voltage
= we
1 150
/V
51.0K
RISETIME
10'1//
/
~ 10K
a:
a:
V I
YC~ = ,."5Y
TA
1100 K
........
90%f ~
.. 40
200
yo:, = ,.',5Y
Vee = :t15V
RL = 20
60
Bias Current Warm Up Change
20
15
SUPPL y VOLTAGE - ±V
0
,J, = ,.'15Y
t 5.0
~
4.0
::l
.........
!Po
..""
~
-
t-
2. 0
'"I. 0
·50
-25
25
so
75
100
125
TEMPERATURE - "C
Typical Applications
Figure 1 Unity Gain Amplifier
Figure 2 Gain·of·10 Inverting Amplifier
10kH
CL
'00 pF
AL
AL
2 kll
2kn
-::-
7-161
6
MINUTES
J.lA776
FAIRCHILD
Multi-Purpose Programmable
Operational Amplifier
A Schlumberger Company
Linear Division Operational Amplifiers
Description
The pA776 Programmable Operational Amplifier is constructed using the Fairchild Planar Epitaxial process. High
input impedance, low supply currents, and low input noise
over a wide range of operating supply voltages coupled
with programmable electrical characteristics result in an extremely versatile amplifier for use in high accuracy, low
power consumption analog applications. Input noise voltage
and current, power consumption, and input current can be
optimized by a single resistor or current source that sets
the chip quiescent current for nano watt power consumption or for characteristics similar to the pA741. Internal frequency compensation, absence of latch up, high slew rate
and short circuit current protection assure ease of use in
long time integrators, active filters, and sample and hold
circuits.
•
•
•
•
•
•
•
•
•
•
Micropower Consumption
± 1.2 V To ± 18 V Operation
No Frequency Compensation Required
Low Input Bias Currents
Wide Programming Range
High Slew Rate
Low Noise
Short Circuit Protection
Offset Null Capability
No Latch Up
Connection Diagram
8-Lead Metal Package
(Top View)
ISET
-IN
vlead 4 connected to case.
Order Information
Device Code
pA776HM
J.!A776HC
Package Code
5W
5W
Package Description
Metal
Metal
Connection Diagram
8-Lead DIP
(Top View)
-OFFSET
NULL
Absolute Maximum Ratings
Storage Temperature Range
Metal Can
Molded DIP
Operating Temperature Range
Extended (pA776M)
Commercial (pA776C)
Lead Temperature
Metal Can (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation " 2
8L-Metal Can
8L-Molded DIP
Supply Voltage
Differential Input Voltage
Input Voltage 3
Voltage Between Offset Null and VOutput Short Circuit Duration 4
ISET (Maximum Current at ISET)
VSET (Maximum Voltage to
Ground at ISET)
>-"':';0 OUT
-65°C to + 175°C
-65°C to +150°C
-IN
v+
+IN
OUT
v-
-55°C to +125°C
O°C to +70°C
ISET
+OFFSET
NULL
Order Information
Device Code
1.00 W
0.93 W
± 18 V
±30 V
± 15 V
±0.5 V
Indefinite
pA776TC
Package Code
9T
Package Description
Molded DIP
500 pA
(V+ -2.0 V)
5.0 kQ
VOP
180
12
3.0
200
MQ
5.0
0.75
Vo=±10 V, RL>75 kQ
mV
18
VI = 20 mV, RL = 5.0 kQ,
CL = 100 pF, Av= 1.0
1.6
0.35
0
10
%
RL = 5.0 kQ, Av = 1.0
0.1
0.8
V/J.ls
J.ls
The following specifications apply -55°C < TA < + 125°C
VIO
Input Offset Voltage
Rs< 10 kQ
6.0
6.0
mV
110
Input Offset Current
TA = +125°C
5.0
15
nA
lis
Input Bias Current
20
120
Icc
Supply Current
30
200
J.IA
0.9
6.0
mW
TA=-55°C
10
40
TA = +125°C
7.5
50
TA =-55°C
Pc
Power Consumption
CMR
Common Mode Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Rs< 10 kQ
Avs
Large Signal Voltage Gain
Vo=±10 V, RL >75 kQ
100
75
VOP
Output Voltage Swing
RL = 75 kQ
±10
±10
Rs< 10 kQ
70
70
90
±10
7-164
dB
90
±10
25
150
nA
V
25
150
J.lV/v
V/mV
V
J1A776
IlA776
Electrical Characteristics T A = 25°C, Vee
= ± 3.0
V, unless otherwise specified.
ISET = 1.51lA
Symbol
Characteristic
Condition
Min
Typ
Max
2.0
5.0
ISET = 15J.LA
Min
Typ
Max
Unit
2.0
5.0
mV
Via
Input Offset Voltage
Via adi
Input Offset Voltage Adjustment
Range
9.0
110
Input Offset Current
0.7
3.0
2.0
15
nA
lis
Input Bias Current
2.0
7.5
15
50
nA
ZI
Input Impedance
50
Icc
Supply Current
13
20
130
160
Pc
Power Consumption
78
120
780
960
los
Output Short Circuit Current
Avs
Large Signal Voltage Gain
Rs < 10 kS1
18
5.0
3.0
Vo=±1.0 V, RL:;;'75 kS1
50
SR
Transient Response
I Rise time
I Overshoot
Slew Rate
RL = 5.0 kS1, Av = 1.0
J.LA
IlW
mA
5.0
V/mV
50
VI = 20 mV, RL = 5.0 kS1,
CL=100 pF, Av=1.0
MS1
200
Vo=±1.0 V, RL:;;'5.0 kS1
TR
mV
200
3.0
0.6
0
5
0.03
0.35
IlS
%
VIIlS
The following specifications apply -55°C < TA < + 125°C
Via
Input Offset Voltage
Rs< 10 kS1
6.0
110
Input Offset Current
TA = +125°C
TA = -55°C
liS
Input Bias Current
Icc
Supply Current
TA = +125°C
TA =-55°C
Pc
Power Consumption
CMR
Common Mode Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Rs<10 kS1
Avs
Large Signal Voltage Gain
Va = ± 1.0 V, RL:;;'75 kS1
Rs<10 kS1
70
Output Voltage Swing
mV
5.0
15
nA
10
40
nA
7.5
50
nA
20
120
25
180
150
1080
86
70
± 1.0
86
25
150
V
25
25
RL = 5.0 kS1
7-165
150
IlVN
V/mV
25
±2.0 ±2.4
RL = 75 kS1
J.LA
IlW
dB
± 1.0
Va = ± 1.0 V, RL:;;'5.0 kS1
VoP
6.0
V
± 1.9
±2.1
IlA776
!lA77SC
Electrical Characteristics TA = 25°C, Vee
= ± 15
V, unless otherwise specified.
ISET = 1.5/lA
Symbol
Characteristic
Condition
Min
Typ
Max
2.0
6.0
ISET = 15/lA
Min
Typ
Max
Unit
2.0
6.0
mV
VIO
Input Offset Voltage
VIO
Input Offset Voltage Adjustment
Range
9.0
110
Input Offset Current
0.7
6.0
2.0
25
nA
lis
Input Bias Current
2.0
10
15
50
nA
30
160
adj
Rs< 10 kn
ZI
Input Impedance
50
Icc
Supply Current
20
Pc
Power Consumption
los
Output Short Circuit Current
Avs
Large Signal Voltage Gain
18
5.0
0.9
3.0
Vo = ± 10 V, RL>75 kU
50
Output Voltage Swing
RL = 75 kU
±12
SR
Transient Response
I Rise time
I Overshoot
Slew Rate
/1A
5.7
mW
12
mA
V/mV
50
400
±10
±13
±14
V
RL = 5.0 kn
TR
Mn
190
400
Vo= ± 10 V, RL>5.0 kU
VOP
mV
VI = 20 mV, RL > 5.0 kU,
CL=100 pF, Av=1.0
1.6
0.35
0
10
%
RL = 5.0 kn, Av = 1.0
0.1
0.8
VI/1s
/1S
The following specifications apply O°C < TA < + 70°C
VIO
Input Offset Voltage
Rs<10 kU
7.5
7.5
mV
110
Input Offset Current
TA = 70°C
6.0
25
nA
TA = O°C
10
40
lis
Input Bias Current
TA = 70°C
10
50
TA = O°C
20
100
35
200
/1A
1.05
6.0
mW
Icc
Supply Current
Pc
Power Consumption
CMR
Common Mode Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Rs<1O kU
Avs
Large Signal Voltage Gain
Vo=±10 V, RL >75 kU
VOP
Output Voltage Swing
RL = 75 kU
Rs<10 kU
70
90
70
±10
7-166
dB
90
±10
25
200
V
25
50
50
±10
±10
nA
200
/1VIV
V/mV
V
IlA776
!lA77SC
Electrical Characteristics TA = 25°C, Vee = ± 3.0 V, unless otherwise specified.
ISET = 1.51lA
Symbol
Characteristic
Input Offset Voltage
Via
Condition
Min
Rs < 10 kn
Typ
Max
2.0
6.0
Input Offset Voltage Adjustment
Range
9.0
110
Input Offset Current
0.7
6.0
10
Via
adj
ISET = 151lA
Min
Typ
Max
Unit
2.0
6.0
mV
18
mV
2.0
25
15
50
nA
liB
Input Bias Current
2.0
ZI
Input Impedance
50
Icc
Supply Current
13
20
130
170
IlA
Pc
Power Consumption
78
120
780
1020
IlW
los
Output Short Circuit Current
3.0
Avs
Large Signal Voltage Gain
Va = ± 1.0 V, RL # 75 kn
25
5.0
5.0
SR
Transient Response
I Rise time
LOvershoot
200
Slew Rate
25
VI = 20 mV, RL # 5.0 kn,
CL = 100 pF, Av = 1.0
RL = 5.0 kn, Av = 1.0
mA
VlmV
Va = ± 1.0 V, RL # 5.0 kn
TR
nA
Mn
200
3.0
0.6
0
5
0.03
0.35
IlS
%
VIlIS
The following specifications apply O°C < T A < + 70°C
Via
Input Offset Voltage
Rs< 10 kn
7.5
7.5
mV
110
Input Offset Current
TA = 70°C
6.0
25
nA
TA = O°C
10
40
liB
Input Bias Current
TA = 70°C
10
50
TA = O°C
20
100
Icc
Supply Current
Pc
Power Consumption
CMR
Common Mode Rejection
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Rs< 10 kn
Avs
Large Signal Voltage Gain
Vo=±1.0 V, RL#75 kn
VoP
Output Voltage Swing
Rs< 10 kn
70
25
180
IlA
150
1080
IlW
86
70
± 1.0
RL = 5.0 kn
7-167
200
dB
V
25
25
Vo =±1.0 V, RL # 5.0 kn
RL = 75 kn
86
±1.0
25
nA
200
IlVN
VlmV
25
±2.0 ±2.4
V
±2.0 ±2.1
pA776
Typical Performance Curves for J,1A776 and J,1A776C
Input Bias Current vs
Set Current
100
Input Bias Current vs
Temperature
Input Offset Current vs
Temperature
30
f-~1 ~12s.~ I III ,
'±3.0'V
$
t- ±3.0 V =:; Vee s; ±1, v
'.!
1/
0
IZ
W
V
'"
"'"
:/
,.
1
iii
"'- ........
'" ISET"'" 15 p.A
12
".!5
/
V
O. 1
0.1
0.01
"'-
I-
1SET CURRENT -
o
-60
100
10
-
'\
C- -
~cc ~ ±1~ v
20
o
100
60
TEMPERATURE _
c
~seT=15pA
rr- JJs~- c- f-
i-
~ '-
-20
$
"'i-
........
'
/J.A
'+3.0'V
\
\.
\
u
/
~CC l ±1~ v
24
-60
140
-20
20
60
100
140
TEMPERATURE _ "C
C
PC03981F
Change in Input Offset Voltage
vs Set Current
0
Change in Input Offset Voltage
vs Temperature (Unnulled)
~l
=~'c' '"
±3.0 V S Vee:5; ±1S v
300
~
200
~
100
t;
r"-
..!;
!5
!
~
-300
W
"~
w
"
-500
'"
"".
10-15
0
.
1/
z
10- 16
W
::E
(.) -300
o
100
10
-20
-60
10- 14
.;2(15ET'- "A)±:::
±3.~ v ~cc
J-
~,
1.5'
I
$' ±1.
$
W
TA "'" 25"C
10- 15
g
.
o
e~2(ISE! I
- 1S ,llA)
W
"-
z
.
~ 10- 16
!'..
"~
~
::E
r---..
"10-1 7
10
I I I
In2(lsET
=.
i
10-2S~
FREQUENCY -
10K
Hz
10-17
0.01
140
r= ..
o
w
SET CURRENT -
...l'!,
iii
100
,
10-26
'"
I-
~
ffi
10-27
'"
"'"o
::E
::E
"
w
z
ilZ
w
W
."
10-27
100 K
~::E
."
10
r\.
W
U
.
10-28
10-29
~
f-Htt-+++t+!;.o :5~;CC < :t18 V
~f
W
::E
100
jJ.A
Optimum Source Resistor for
Minimum Noise vs Set Current
'"~ '"
r--
10
0.1
Input Noise Current vs
Set Current
'"
"'" U"'"
~
1.0K
100
U
15 I-IA}
in2(ISET - 1.5 ,uA)
100
60
20
TEMPERATURE _ "C
Input Noise Voltage and Current
vs Frequency
"~
10-14
:I:
SET CURRENT - /loA
~
+18 V
>
w
/'
V
<:::
0
V
-100
±3.0 v < Vee
t
1 kHz
10-13 r-~~1-~+t~r =1Hz
w
/'
~ -20 0 /
~
,
".~
V
0
TA
25"C
10-"~~Bj~[[=~
~>
ISET = 15 IlA
w
0
0
vL =1±ls~_
I 400
I,
!;1
500
~
Input Noise Voltage vs
Set Current
f
- 1 Hz
- 1 kHz
0.01
0.1
10
SET CURRENT -
7-168
jJ.A
~
o
, ,
10-30
"-
1
100
"O. 1
0.01
0.1
SET CURRENT -
10
/loA
100
JlA776
Typical Performance Curves for !lA776 and !lA776C (Cont.)
Output Voltage Swing vs
Load Resistance
30
'z"
TA
25°C
~
24
~
V
..
":I '2
.
"~
I-
:J
18
'YII,·Y
/
0
I
I
g
-
~
I-
:J
o
I I
100 K
1 M
,.
500
'"
'~"
400
z
;;:
w
..gg
..ffi
300
200
0
100
:v
o
= 15 IlA
RL.=5::~
-
.,.... V
,......
.....
io
~
z
I'
'"
±9
±6
±12
::,:15
±18
...- ~SET
RL=75k!l
0
0
0
-60
-20
20
60
1,000
140
'00
800
-/
g
.
g
ffi..
600
~
400
200
-60
-20
150
~
o-r-
;:
RL=75kfl
"a:z
\
~
"--
a:
a:
:J
u
...
>~
90
~
'"
60
100
140
10
0
0.1
:: ;;.0
:5;~cc
+18 V
w
~
/
1
ISET = 1.5;.;A
Vee
0
Vee
0
-20
20
-+:15~
±3.0
o
>
t;
V
~
TEMPERATURE _
LL
"C
/
200
I
/
~
w
'"z
0.Q1
V
40 0
~
::-
140
J50C l'2~OC I
~
vl'tsgle 1.0 il l<:
:J:
U
0.1
10
SET CURRENT -
7-169
IJ.A
100
-
Vee"" ±15 V
InitialOffsel
0
"
v
100
- ----
o
O. 1
60
100
ilA
Thermal Response Of Input
Offset Voltage To Step Change
Of Case Temperature
~ 80 0
<
10
SET CURRENT -
1000
V
-60
20
~
:r
0
:J
~a:
'"a:
1-3.0 V-
Ve
$ 18 V
30
'" 600
-
±3.0 v ~ Vee
I-+-H+--+-H_T,'A = 25°C
>-
:J
12
ffi
100
JlA
0
;:
u
Standby Supply Current vs
Set Current
. . ,5 v
Vee
40
TEMPERATURE _ °C
1 J.-I.
ISET = 15 J.lA
~~
20
TEMPERATURE _ °C
Supply Current vs Temperature
SET CURRENT -
Power Supply Rejection Ratio vs
Set Current
"'-;:ET~15"A'
RL=stn I
"-
w
-
10
ISET -
0
I 1,200
= 1.5 JJ.A- ~
1.0K
0.1
V
VCC=:t15V
z
;;:
'"
~'"
10K
;;:
,.
,
/'
o
E
rlSET
Vee - ±3.0 v
:::E: 100 K
I-
> 1.400
-
V/ . /
..
Voltage Gain vs Temperature
Vcc=±3.0V
I
E
#
8
Vee - ±15
oa:
ISET = 1.5 J.lA
RL = 5 k!l
r;r
1.0M
:J
~V
/,
~
I
I
t;
V
SUPPLY VOLTAGE -
Voltage Gain vs Temperature
600
4-
12
n
LOAD RESISTANCE -
>
6
I-
I I
I I
10 K
1.0 K
20
"'~"
Vee ..co ;±:3.0 V
1.5 MA < ISET < 15 iJA
-
o
~.~~J.L7~ ~!~SET ~ 15 >LAy'
w
I
:J:
~
AL = 5 kfl
4
'~z"
-
A
J
_III
6
I-
>
I
=
C:::T~I ~~oc I
N
ISET ="5 /lA
8
Vee = j:15 V
I-
:J
TA=2S"C
Vee = ±15 V
ISET
15 p.A
K-
10 M
2
-"- ...d-t1"f
~
Gain Bandwidth Product vs
Set Current
Output Voltage Swing vs
Supply Voltage
-20
20
40
60
TIME FROM HEAT APPLICATION -
80
s
pA776
Typical Performance Curves for pA776 and pA776C (Cont.)
Stabilization Time Of Input Offset
Voltage From Power On
Input Offset Voltage Drift vs Time
::. 100
~
I
w
i--'"
-10
V
1/
g
>
-20
~
..
-30
tu
Vee'"" :t15
TA
-40
=:
Initial
v
w
"
..
I-
::>
16
I-
::>
0
/
I
I
I--
800
600
1000
"
I
.>
1.0M
Vee = ±3
"
vV'
0:
I:!
II 1
lOOK
"
I I liET to V~
-II if" ti GjD
0.5
1.0
1.5
2.0
2.5
Vs
1.5 I1A
± 1.5 V
Mn
3.6 Mn
7.5 Mn
20 Mn
1.7
10K
0.1
10
seT CURRENT -
100
p.A
ISET Equations
(V + )-0.7 - (V -)
ISET
15
IlA
kn
360 kn
750 kn
2.0 Mn
170
0.01
Y
Vee
ISET = -'---'----'--'RSET
where:
RSET is connected to V(V + )-0.7
ISET = -'---'--RSET
where:
RSET is connected to ground.
Note
The iJA776 may be operated with RSET
connected to ground or V-
7-170
0.00 1
0.01
/
±3.a v
V
V
1/
10
0.1
seT CURRENT -
Hr.
Vcc- +15 V
l-
I
Quiescent Current Setting Resistor
(ISET to V-)
± 15 V
"
0:
~
w
TIME -Ill
±6.0 V
400
'00
0
I-
.
I
10 M
±15
ISET= 15 IJ.A
RL = 5 kfl
CL '" 100 pF
~8
±3.0 V
I
.0
Set Current vs Set Resistor
v
Vee =
o. 1
~
TIME -
1
-0.5
w
:
/
+15 Y
;0
Min
v----
40
3'
V-
100 M
48
"!:;<
40
o
56
E
II
U ov
Voltage Follower Transient
Response (Unity Gain)
Vee
TREND IlIN~
i!!
i!!
0l'set IV01jge 11.0 IV
1
1
60
23456789
~
>
80
~
~
/
::>
i!!
TA 'j125 C
O
o
J
t;
~
~
>
10
~ee" ±18 V
w
"
V
Slew Rate vs Set Current
IJ.A
100
JlA776
Biasing Circuits
Voltage Offset Null Circuit
Resistor Biasing
v-
Va
RSET
v-
-::-
FET Current Source Biasing
RSET Connected to Ground
v+
Va
RSET
v-
v-
Transient Response Test Circuit
RSET Connected to V-
"Recommended for supply voltages less than ± 6 V.
Transistor Current Source Biasing
. A - - - Va
v-
7-171
IlA798
Dual
Operational Amplifier
FAIRCHIL.D
A Schlumberger Company
Linear Division Operational Amplifiers
Description
Connection Diagram
8-Lead DIP and 50-8 Package
(Top View)
The pA798 consists of a monolithic pair of independent,
high gain, internally frequency compensated operational
amplifiers designed to operate from a single power supply
or dual power supplies over a wide range of voltages. The
common mode input range includes the negative supply,
thereby eliminating the necessity for external biasing components in many applications. The output voltage range
also includes the negative power supply voltage. The
J.l.A798 is constructed using the Fairchild Planar Epitaxial
process.
• Input Common Mode Voltage Range Includes Ground
Or Negative Supply
• Output Voltage Can Swing Near Ground Or Negative
Supply
• Internally Compensated
• Wide Power Supply Range Single Supply Of 3.0 V
To 36 V Dual Supply of ± 1.5 V To ± 18 V
• Class AB Output Stage For Minimal Crossover
Distortion
• Short Circuit Protected Output
• High Open Loop Gain - 200 k Typ
• Exceeds J.l.A1458 Type Performance
• Operation Specified At ± 15 V And +5.0 V Power
Supplies
• High Output Current Sink Capability
0.8 mA At Vo 400 mV Typ
v+
-IN A
+IN A
-IN B
v-
+IN B
Order Information
Device Code
pA798SC
J.l.A798TC
=
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(soldering, 10 s)
Internal Power Dissipation 1. 2
8L-Molded DIP
SO-8
Supply Voltage Between V+ and VDifferential Input Voltage
Input Voltage 3
Output Short Circuit Duration 4
OUT B
-65°C to + 150°C
O°C to +70°C
0.93 W
0.81 W
36 V
±30 V
-0.3 V (V-) to V+
Indefinite
Noles
1. TJ Max = 150°C.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the Molded DIP at 7.5 mW/'C. and the SO-8 at 6.5 mW/'C.
3. For supply voltage less than 30 V between V+ and V -, the absolute
maximum input voltage is equal to the supply voltage.
4. Indefinite on shorts to ground or V - supply. Shorts to v+ supply may
result in power dissipation exceeding the absolute maximum rating.
7-172
Package Code
Package Description
KC
9T
Molded Surface Mount
Molded DIP
JJ-A798
Equivalent Circuit (112 of circuit shown)
v+----------------------~----------------------~r_------~--------~--------_,
C1
5 pF
-IN
v---~-+----+_----~----+_--r_----+-4-----------+-----+---+-----+---+-~
'IN
Note
1. All resistor values in ohm.
7-173
J1A798
IlA798
Electrical Characteristics TA = 25°C, Vee = ± 15 V, unless otherwise specified.
Symbol
Characteristic
V,o
Input Offset Voltage
1'0
Input Offset Current
Condition
Min
Typ
2.0
I'B
Input Bias Current
Z,
Input Impedance
Ro
Output Resistance
Icc
Supply Current
Vo = 0, RL =
CMR
Common Mode Rejection
Rs<:10 kil
VIR
Input Voltage Range
PSRR
Power Supply Rejection Ratio
Positive
los
Output Short Circuit Current1 •2
Vo=-15 V, V,o=1.0 V
(Per Amplifier)
Vo=Gnd, V,o=-1.0 V
Avs
Large Signal Voltage Gain
Vo=±10 V, RL=2.0 kil
VoP
Output Voltage Swing
RL = 10 kil
RL = 2.0 kil
TR
Transient Response
0.3
Max
mV
10
50
nA
50
250
1.0
2.0
nA
Mil
800
00
Unit
6.0
il
4.0
mA
70
90
dB
+13
to V-
+13.5
to V-
V
Negative
30
150
/JVIV
30
150
30
45
10
70
85
20
200
V/mV
±13
±14
V
±12
± 13.5
10
mA
Rise Time
Vo=50 mV,
Av = 1.0, RL = 10 kil
0.3
Fall Time
Vo= 50 mV,
Av = 1.0, RL = 10 kil
0.3
Overshoot
Vo=50 mV
Av=1.0, RL=10 kil
20
%
/Js
BW
Bandwidth
Vo = 50 mV, Av = 1.0,
RL = 10 kil
1.0
MHz
SR
Slew Rate
V, = -10 V to + 10 V,
Av = 1.0
0.6
V//Js
CS
Channel Separation
f = 1.0 kHz to 20 kHz
(Input Referenced)
-120
dB
The following specifications apply for O°C <: TA <: + 70°C
V'O
Input Offset Voltage
AV,ol AT
Input Offset Voltage Temperature
Sensitivity
1'0
Input Offset Current
AI,ol AT
Input Offset Current Temperature
Sensitivity
I'B
Input Bias Current
7.5
10
/JVfOC
200
nA
pAloC
50
400
7-174
mV
nA
IlA798
/lA798 (Cont.)
Electrical Characteristics TA
Symbol
= 25°C,
Vee
= ± 15
V, unless otherwise specified.
Characteristic
Min
Condition
Avs
Large Signal Voltage Gain
RL=2.0 kn, Vo=±10 V
VOP
Output Voltage Swing
RL = 2.0 kn
Typ
Max
15
Unit
V/mV
±10
V
The following specifications apply for TA = 25°C, V + = 5.0 V, V-=GND
Via
Input Offset Voltage
2.0
7.5
mV
110
Input Offset Current
10
50
nA
liB
Input Bias Current
80
250
Avs
Large Signal Voltage Gain
PSRR
Power Supply Rejection Ratio
VOP
Output Voltage SWing 3
RL ;;;"2.0 kn
Output Sink Current
Icc
Supply Current
200
RL = 10 kn
4.0
~30
Vo= 200 mV,
V ID = 1.0 V
V
1. Not to exceed maximum package power dissipation.
2. Indefinite on shorts to ground or v- supply. Shorts to v+ supply may
result in power dissipation exceeding the absolute maximum rating.
3. Output will swing to ground.
7-175
pVIV
Vp . p
(V+)
-1.5
0.35
mA
2.0
Notes
nA
V/mV
150
5.0 V~V+
RL = 10 kn
10-
20
4.0
mA
IlA798
Typical Performance Curves
Sinewave Response
Output Voltage vs Frequency
AVI
'\
fA
"
=
'2°rTTrr,-;nrT-n~rT~,-rm~~~
t--
~100f-+~~tH~~ff-rt~-t-Mtrt~~
I
vLUJ
251-++-t-t--t-H+f'OkO
,i,.
RL =
TA
25°C
Ifl f'
Open Loop Frequency Response
30r--rTTr--r~-rrr-;--,,-n--'
=
Vee'" :t1SY
TA
~ 8°f-+~-t-tH~~ff-rt~-t-Htf-t~~
"
w
~
IV IV V IV \
60
~ 40rt~~~rt-HTI-rt~~Htr+~~
t;
9
r-
h
..........
Ir-
* o~~~++ffiH1#rrmrrH~
-2~.'=o.ll"-:',o,-J-t.LL",!,OO,.wlL,.':-O:-!-K"'""=,-:fO"'KllJ.,':O':-O:fK.ill,~.O M
-5.0 L-...J....J...J-l-....J.._"--''-'-'--:-':-''''''''...J....u..-:-,
1.0 K
10 K
100 K
FREQUENCY -
Output Swing vs Supply Voltage
40
1.0M
FREQUENCY -
Hz
Input Bias Current vs Temperature
'00
I
TA -
20~~~~rt-HTI-rt~-t-Ht~~~
z
h
50 ,us/DIY
1
25~C
Vee
~
Hz
Input Bias Current vs
Supply Voltage
80
I
= ±15V
~
> 30
I
w
I 15
...
"
Z
... 50
rr:
il!a:
z
w
Z
<
rr:
'"G 50
w 20
"
0
...>
.."...
= 25°C
<
!;;
V
'0
r-,...
iii
~
a
....
~
iii 40
~
~ 25
1/
"0
r-
~
V
~
/
o
o
!
o
2.0 4.0 6.0
8.0 10
12
SUPPLY VOLTAGE -
14
16
±V
18
20
0
-75 -55 -35 -15 5.0
25
45
65
TEMPERATURE _ °C
7-176
85 105 125
o
2.0 4.0 6.0 8.0
10
12
14
SUPPLY VOLTAGE -
16
±V
18
20
/J.A798
Typical Applications
Multiple Feedback Bandpass Filter
Wein Bridge Oscillator
&OK
r------JVY~------t--Yo
10 k
YREf
+
VREF
1_-10 J.lF
1
C
VREF O;::iV+
t.
to = center frequency
t.
R
C
BW = Bandwidth
A in kil
C in "F
fo
1
fo = - - for fo
0--<10
BW
21TAC
o
Cl-C2-3
= 1.0 kHz
A=16 kil
C= 0,01 "F
High Impedance Differential Amplifier
Al - A2 = 1]
R3 = 902-1 Use scaling factors in these expressions.
R'
V1
If source impedance is high or varies, filter may be preceded
with voltage follower buffer to stabilize filter parameters.
" ' -....--Yo
Design example:
given: 0 - 5, fo = 1.0 kHz
Let Al =A2-10 kil
then A3 - 9(5)2 -10
A3-215 kil
R3
5
C=:;=1.6 "F
R4
Comparator With Hysteresis
RS
R2
YOH
HYSTERESIS
~y.,,0t:ffi
I
R1
VREF ---'lM__..........
-----
V,-----..f
va
R7
Vo
VOL
V!L
I
AF00691F
VIH
VO=C (1 +a+b)(V2-Vl)
Afooe81F
-
VAEF
A2
A5
A6
'" -
A7
for best CMAA
Al - A4
A2= AS
A6
Gain
Al
H - Al + A2 (VOH VOL)
Al + A2
A2Al
4CA,Al
A2 + Rl
2Al
-Ai (1 +Fi3) =C (1 +8 +b)
Note
1. All resistor values in ohms.
f - - - - if A 3 - - - -
7-177
I1A798
Typical Applications (Cont.)
Pulse Generator
Vo
R3
100 k
RS
100 k
+0
n II
....J L..J L-
Function Generator
VREF
1
=-
2
TRIANGLE WAVE
OUT
v+
R2
r-_ _...J3VOOVVk_ _....,~_~~~ARE WAVE
R3
VAEF
75 k
R1
100 k
c
Rt
' - - -....-VREF
AF00661F
Note
1. All resistor values are in ohms.
7-178
J.lA 111 • J.lA311
Voltage Comparators
FAIRCHILD
A Schlumberger Company
Linear Division Comparators
Connection Diagram
8-Lead Metal Package
(Top View)
Description
The MA 111 and MA311 are monolithic, low input current
voltage comparators, each constructed using the Fairchild
Planar Epitaxial process. The MA 111 series operates from
the single 5.0 V integrated circuit logic supply to the standard ± 15 V operational amplifier supplies. The MA 111 series is intended for a wide range of applications including
driving lamps or relays and switching voltages up to 50 V
at currents as high as 50 mA. The output stage is compatible with RTL, DTL, TTL and MOS logic. The input
stage current can be raised to increase input slew rate.
V+
• Low Input Bias Current 100 nA Max (MA111), 250 nA
Max (MA311)
• Low Input Offset Current 10 nA Max (MA 111), 50 nA
Max (MA311)
• Differential Input Voltage ± 30 V
• Power Supply Voltage Single 5.0 V Supply To ± 15 V
• Offset Voltage Null Capability
• Strobe Capability
V-
Lead 4 connected to case
Order Information
Device Code
Package Code
5W
5W
MA111HM
!J.A311 HC
Absolute Maximum Ratings 1
Storage Temperature Range
Metal Can
Molded DIP and SO-8
Operating Temperature Range
Extended (MA 111 M)
Commercial (MA311 C)
Lead Temperature
Metal Can (soldering, 60 s)
Molded DIP and SO-8
(soldering, 10 s)
Internal Power Dissipation 2, 3
8L-Metal Can
8L-Molded DIP
SO-8
Voltage between V+ and VOutput to V(MA111)
(MA311)
Ground to VDifferential Input Voltage
Input Voltage
Output Short Circuit Duration
BALANCE!
STROBE
+IN
Package Description
Metal
Metal
Connection Diagram
8-Lead DIP and SO-8 Package
(Top View)
-65°C to + 175°C
-65°C to + 150°C
-55°C to + 125°C
O°C to 70°C
GND
300°C
+IN
265°C
BALANCEI
-IN
STROBE
1.00 W
0.93 W
0.81 W
36 V
50 V
40 V
30 V
±30 V
± 15 V
10 s
Order Information
Device Code
!J.A311TC
MA311SC
Notes
1. This rating applies for ± 15 V supplies. The positive input voltage limit is
30 V above the negative supply. The negative input voltage limit is
equal to the negative supply voltage or 30 V below the positive supply,
whichever is less.
2. TJ Ma, ~ 150°C for the Molded DIP and SO-B, and 175°C for the Metal
Can.
3. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the BL-Metal Can at 6.7 mwrc, the BL-Molded DIP at
7.5 mW/oC, and the SO-B at 6.5 mW/oC.
8-3
Package Code
9T
KC
Package Description
Molded DIP
Molded Surface Mount
•
Equivalent Circuit
BALANCE
BALANCE! STROBE
r---~---.~~--r---+---~----~------~---'-----------------'-----W
+IN
>-+--_OUT
-IN ---1--1((
RU
130Q
Q15
R12
600Q
R13
4Q
'-----t---------GND
v-
pA111
Electrical Characteristics TA = 25°C, Vee
Symbol
Characteristic
= ± 15
V, unless otherwise specified. 1
Condition
Min
Typ
Max
Unit
VIO
Input Offset Voltage 2
0.7
3.0
mV
110
Input Offset Current2
4.0
10
nA
liB
Input Bias Current
60
100
nA
Rs';;;50 kn
Avs
Large Signal Voltage Gain
200
tpD
Response Time3
200
VSAT
Saturation Voltage
10(ST)
Strobe On Current
ICEX
Output Leakage Current
VI .;;; -5.0 mV, 10L = 50 mA
0.75
V/mV
ns
1.5
mA
3.0
VI;;' 5.0 mV, Vo = 35 V
0.2
V
10
nA
4.0
mV
20
nA
150
nA
The following specifications apply for -55°C';;; TA';;; + 125°C.
VIO
Input Offset Voltage 2
110
Input Offset Current2
liB
Input Bias Current
VIR
Input Voltage Range
VSAT
Saturation Voltage
Rs';;;50 kn
±14
V+ ;;'4.5 V, V- = 0 V,
VI .;;; -6.0 mV, 10L';;; 8.0 mA
8-4
0.23
V
0.4
V
lolA 111 (Cont.)
Electrical Characteristics -55·C"; TA"; + 125·C. Vee = ± 15 V. unless otherwise specified. 1
Symbol
Typ
Max
0.1
0.5
p.A
TA = 25·C
5.1
6.0
rnA
= 25·C
4.1
5.0
rnA
Typ
Max
Unit
2.0
7.5
rnV
nA
Characteristic
Min
Condition
ICEX
Output Leakage Current
VI ;;"5.0 rnV. Vo
1+
Positive Supply Current
1-
Negative Supply Current
TA
= 35
V
Unit
1oIA311
Electrical Characteristics TA = 25·C. Vee = ± 15 V. unless otherwise specified. 1
Symbol
VIO
Condition
Characteristic
Input Offset Voltage2
Rs";;;;50 k!l
Min
110
Input Offset Current2
6.0
50
liB
Input Bias Current
100
250
200
Avs
Large Signal Voltage Gain
tpo
Response Tirne3
VSAT
Saturation Voltage
lo(sn
Strobe On Current
ICEX
Output Leakage Current
ns
200
VI";;;;-10 rnV. 10 = 50 rnA
0.75
1.5
0.2
V
rnA
3.0
VI;;"10 rnV. Vo=35 V
nA
V/rnV
50
nA
10
rnV
70
nA
300
nA
The following specifications apply for O·C";;;; TA .,;;;; + 70·C.
VIO
Input Offset Voltage2
110
Input Offset Current2
liB
Input Bias Current
VIR
Input Voltage Range
VSAT
Saturation Voltage
V+ ;;.. 4.5 V. V- = 2.25 V.
VI";;;;-10 rnV. 10L ";;;;8.0 rnA
1+
Positive Supply Current
1-
Negative Supply Current
Rs";;;;50 k!l
±14
V
0.23
0.4
V
TA = 25°C
5.1
7.5
rnA
TA = 25°C
4.1
5.0
rnA
Notes
1. The offset voltage, offset current and bias current specifications apply
for any supply voltage from a single 5.0 V supply to ± 15 V supplies.
2. The offset voltages and offset currents given are the maximum values
required to drive the output within a volt of either supply with a 1.0 mA
load. Thus, these parameters define an error band and take into
account the worst case effects of voltage gain and input impedance.
3. The response time spec~ied is for a 100 mV input step with 5.0 mV
overdrive.
8-5
Typical Performance Curves for p.A 111
Input Bias Current vs
Temperature
Input Offset Current vs
Temperature
...
30
Vc~. t1~V-
25
45
o
-55 -35
105 125
85
-15
-
"-
NORMAL
25
45
V+
>
I
85
85
Ifilil voi+ti
105 125
.,
~
..g'"
'"
i
50
..
I
s-
o
-16
12
-12
-8
-4
DIFFERENTIAL INPUT VOLTAGE - V
18
o.a
....
L
. ..-: ;y
r-T." -we
1>' /"
//
....
.L
0.1
..
o
2S
65
85
oc
30
40
I
eoc:o
J
I\.
'\
-0.'
'-
I--
0.'
1.0
DIFFERENTIAL INPUT VOLTAGE -
mY
Leakage Current vs
Temperature
10-7
Vee = t15 v
Vee = ±15v:;;r=
;..'
i
::::::",
'
OUTPUT CURRENT - rnA
-1.0
105 125
= 30V
~'\
FOLLOWER
OUTPUT
R~.
4S
10
.
-r-... r-
0
-55 -35 -15
---
.~
;
25
45
6S
Note
1. Leads 5, 6 and 8 are shorted.
8-6
85 105 125
.........
10-8
/'
V, = 15V
./
~ 10-10
10-11
5
TEMPERATURE - OC
Vo,'OV/'
10-8
!Z
POSlTI":':'PPLY -
~
I ~::I;;;:~ I'"""'
r-- r-- NEGATIVE
SUPPLYr-- r-- r- I (tTHr- I-- I--
~ f"<;T•• :we
10
EMITTER
10
7~
i'--
..-
o
-55 -35 -15
Vee
TA = 250C
I
I
II
I\.
~20
o
V-
""'"
A;..'
-
--
!;
'-- .....
f
I
~
g30
~
Supply Current vs
Temperature
+•. ~",
v, = sov ht..
~
:!. ..
-1
I
RL= 1 kQ
w'40
-1.0
TEMPERATURE -
Saturation Voltage vs
Output Current
'-NObMAL1Oun!uT
>
D.2
•
0
Output Voltage vs
Differential Input Voltage
~FE~~ED_f.?
0.'
it
1M
INPUT RESISTANCE -
::;
r0-
100 K
"K
etC
S PPLY VD :rAG
o.,
,./
1.0
Common Mode Limits vs
Temperature
I TA,=WC
JccUl'~
r
RAISED (NOTE 1)
........ ......
TEMPERATURE -
Input Bias Current vs
Differential Input Voltage
110
.........
-
oc
TEMPERATURE -
150
"-
......
65
":'
10
"
NORMAL
-15
c',
~
".......
-55 -35
oo~
vee' • 'l~V
~,
RAISED (NOTE 1)
o
Offset Voltage vs
Input Resistance
i--"':
25
45
.
85
TEMPERATURE - OC
105
125
#lA 111 • #lA311
Typical Performance Curves for 1lA311
Input Bias Current vs
Temperature
20
500
RAISEiI
(NOTE 1
I
~300
r- t--
i
~
i
i
i200
r-
r- r-
-
V
iITrrtlsl'rn
01020
30
40
TEMPERATURE -
5060
100K
70
oc
T = 25"C
80
Vee·30V
TA = 250C
REFERRED TO
YVO~ AGES
50
-0.
i
i
i
~
o
-16
-12 -8
-4
•
12
DIFFERENTIAL INPUT VOLTAGE - V
16
:!,::...
... ~
f--
EMITTER
FOLLOWER
OUTPUT
A
II
II
\.
'\.
RL=8DDO:
I
0.2
v
I
-
::;
u
T
I
(
.. -1
0
T
NORMAL OUTPUT
AL" 1 kO
V1 = 40V
>
I -1 .0
...
n
Output Voltage vs
Differential Input Voltage
8UPP
•
10M
1M
INPUT RESISTANCE -
v+
Jcc l• ~15~_
/
TYPICAL
Common Mode Limits vs
Temperature
Input Bias Current vs
Differential Input Voltage
MIAXIMUM
NORMAL
o
010203040506070
TEMPERATURE - "C
200
~
TA= 250C
10
D
225
ve!,= .Jv(NOTE 1)
o
NORMAL
100
r--....
~
I
~
i
r-....
v":'=.Jv-
t-- t--
~400
Offset Voltage vs
Input Resistance
Input Offset Current vs
Temperature
T
-
10
20
30
40
TEMPERATURE -
-1.0
ere
\.
T
T
o
70
50
1
-0.5
"
1.0
DIFFERENTIAL INPUT VOLTAGE - mV
PC'''••' '
Supply Current vs
Temperature
Saturation Voltage vs
Output Current
o.a
T. .
a\~:-
0.7
~
./
Leakage Current vs
Temperature
0
FOumrr
V
rr-
/'
./
1/
-
I
10
~~W J. - f---
OUTPUT
~M!-
NEGATIVE SUPPl.YIOUTTHlj-
20
30
OUTPUT CURRENT - ....
40
= 40V
..... ,;"
I
10-1
INPUT VI
50
o
f---
Note
1. Leads 5. 6 and 8 are shorted.
8-7
&0
70
15 Y
~
10-11
01020
30
40
50
TEMPERATURE - "C
:I
•
0.1
D
Vo
c
./
V
FYcc' mv
Vcc ."15V
8
~
25
35
4S
15
TEMPERATURE - 'C
15
75
Typical Applications
Offset Null Circuit
Strobe Circuit
Zero Crossing Detector
Driving MOS Logic (Note 3)
Increasing Input Stage
Current (Note 1)
r-1......--V+
TTL
STROBE
V+=5.0V
1.01cll
7
TOMOS
R3 LOGIC
10 k
OFFSET BALANCING
STROBING ":::
"""""'"
CR02210F
Adjustable Low Voltage
Reference Supply
Negative Peak Detector
+lSV
Vo
Digital Transmission Isolator (Note 3)
v+ =s.ov
I
v+=5.0Y
(:= ~ ~)
FCD820
RS
5k
21 8
31""1~
Positive Peak Detector
R3
3.,-1
+15 V
100
Rl
FROM
TTL
GATE
Notes
1) Increases typical common mode slew rete from 7.0 VI /IS to 1B VI /IS.
2) Solid Tantalum.
3) All resistor values in ohms.
8-8
R2
SDk
o.01~::
RS
1k
R4
lk
• 4
TTL
OUT
MA 111 • MA311
Typical Applications (Cont.)
Relay Driver with Strobe
Y,
Strobing of Both Input
And Output Stages (Note 1)
FROM D/A NETWORK
TTL
STROBE
Rl
1 kO
TTL STROBE
Switching Power Amplifier
Precision Photodiode Comparator
IN
Rl
Rl
10 kO
'--""'--""'''---'''''--'-+5.0
Y
3.9kO
~FPT100
R3
1 kO
R2
lOOk{)
OUT
3
R3
TTL
OUT
100
Cl
0.1 JJ.F
Notes
1. Typical input current is 50 pA with inputs strobed off.
2. Absorbs inductive kickback of relay and protects Ie from severe voltage
transients on VI line.
3. R2 sets the comparison level. At comparison, the photodiode has less
than 5.0 mV across it, decreasing leakages by an order of magnitude.
8-9
to
'---+-==.....-v-
Switching Power Amplifier
V+
Q2.~
1112
2N61~
112
6200
OUT
I
6200
1
R11
6200
I
I
300 k!l
RS
RS
5'00
39kO
1
h
R13
3OOkO
R9
39kO
R14
5100
R8
15 kO
~--~------------~-----t--------~~----~~-----------------------t---4--~A---IN
J,.Cl
To.22,J1
R7
~~------------~----~-----4~------~---------------------------------4------~A---REFERENCE
15 kO
8-10
p.A 139 • p.A239 • p.A339
p.A290 1 • p.A3302
F=AIRCHILO
A Schlumberger Company
Quad Comparators
Linear Division Comparators
Description
Connection Diagram
14-Lead DIP and 50-14 Package
(Top View)
The pA 139 series consists of four independent precision
voltage comparators designed specifically to operate from
a single power supply. Operation from split power supplies
is also possible and the low power supply current drain is
independent of the supply voltage range. Darlington connected PNP input stages allow the input common mode
voltage to include ground.
,.
OUTB
OUTC
OUT A
OUT 0
• Single Supply Operation + 2.0 V To + 36 V
• Dual Supply Operation ± 1.0 V To ± 18 V
• Allow Comparison Of Voltages Near
Ground Potential
• Low Current Drain 800 /lA Typ
• Compatible With All Forms Of Logic
• Low Input Bias Current 25 nA Typ
• Low Input Offset Current ± 5.0 nA Typ
• Low Offset Voltage ± 2.0 mV
V+
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP and SO-14
Operating Temperature Range
Extended (pA 139M)
Automotive (pA2901V, pA3302V)
Industrial (pA239V)
Commercial (pA339C)
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP and SO-14
(soldering, 10 s)
Internal Power Dissipation 1. 2
14L-Ceramic DIP
14L-Molded DIP
SO-14
Supply Voltage
pA 139 Series/ pA2901
pA3302
Differential Input Voltage
pA 139 Series/ pA2901
pA3302
Output Short Circuit to GND 3
Input Current (VI < -0.3 V)4
-65°C to + 175°C
-65°C to + 150°C
V-orGNO
-INA
+IND
+INA
-IN 0
-IN B
+INC
+INB
-INC
Order Information
Device Code
pA139DM
pA239DV
pA239PV
pA239SV
pA339DC
pA339PC
pA339SC
pA2901DV
pA2901PV
pA3302DV
pA3302PV
pA3302SV
-55°C to +125°C
-40°C to +85°C
-25°C to +85°C
O°C to 70°C
300°C
265°C
1.36 W
1.04 W
0.93 W
Package Code
6A
6A
9A
KD
6A
9A
KD
6A
9A
6A
9A
KD
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
Molded Surface Mount
Ceramic DIP
Molded DIP
Molded Surface Mount
Ceramic DIP
Molded DIP
Ceramic DIP
Molded DIP
Molded Surface Mount
36Vor±18V
28 V or ±14 V
36 V
28 V
Indefinite
50 mA
Notes
1. TJ Max ~ 150'C for the Molded DIP and SO·14. and 175'C for the
Ceramic DIP.
2. Ratings apply to ambient temperature at 25'C. Above this temperature,
derate the 14L-Ceramic DIP at 9.1 mWI'C, the 14L·Molded DIP at
8.3 mW I'C, and the SO-14 at 7.5 mW I'C.
3. Short circuits from the output to V+ can cause excessive heating and
eventual destruction. The maximum output current is approximately
20 mA independent of the magnitude of v+.
4. This input current will exist only when the voltage at any of the input
leads is driven negative. It is due to the collector base junction of the
input PNP transistors becoming forward biased and thereby acting as
input diode clamps. In addition to diode action, there is also lateral NPN
parasitic transistor action on the Ie chip. This transistor action can
cause the output voltages of the comparators to go to the v+ voltage
level or to ground for a large overdrive, for the time duration that an
input is driven negative. This is not destructive and normal output states
will re-establish when the input voltage, which is negative, again returns
to a value greater than -0.3 V.
8-11
MA 139 • MA239 • MA339
MA2901 • MA3302
Equivalent Circuit
V+
+IN----1C
- I N - - - - - - - / - - - - - - 1 -_ _ _---I
.----OUT
y- or GNO
IlA 139, 1.lA239, 1.lA339
Electrical Characteristics TA
= 25°C,
V+
= 5.0
V, unless otherwise specified.
!lA139
Symbol
Characteristic
Condition
VIO
Input Offset Voltage 5
liB
Input Bias Current 1
11+ or 11- with Output
in Linear Range
(11+) - (11-)
Min
Typ
!lA239, J,lA339
Max
Min
Typ
Max
Unit
±2.0
±5.0
±2.0
±5.0
mV
25
100
25
250
nA
±50
nA
(V+)-1.5
V
110
Input Offset Current
VIR
Input Common Mode
Voltage Range2
±5.0
Icc
Supply Current
RL = 00 on all
Comparators
0.8
Avs
Large Signal Voltage
Gain
RL;;;'15 kn,
V+ =15 V (To
Support Large Vo
Swing)
200
200
V/mV
tpD1
Large Signal
Response Time
VI = TTL Logic Swing,
VREF = 1.4 V,
VRL = 5.0 V,
RL = 5.1 kn
300
300
ns
tpD2
Response Time 3
VRL = 5.0 V,
RL = 5.1 kn
1.3
1.3
J,lS
8-12
±25
(V+)-1.5
0
2.0
±5.0
0
0.8
2.0
mA
p.A 139 • MA239 • p.A339
MA2901 • p.A3302
J.(A139, MA239, J.(A339 (Cont.)
Electrical Characteristics TA = 25°C, V+ = 5.0 V, unless otherwise specified.
pA139
Symbol
Characteristic
Condition
IOL
Output Sink Current
VI- ;;;'1.0 V,
VI+ = 0 V,
Vo< 1.5 V
VSAT
Saturation Voltage
VI- ;;;'1.0 V,
VI+ = 0 V,
iOL <4.0 rnA
ICEX
Output Leakage
Current
VI+ ;;;'1.0 V,
VI- =0 V,
Vo=30 V
Min
6.0
Typ
IlA239, pA339
Max
16
250
Min
6.0
400
Typ
250
200
Unit
Max
16
rnA
400
rnV
200
nA
The following specifications apply for -55°C < TA < + 125°C for the IlA 139, -25°C < TA < + 85°C for the 1lA239 and
O°C < TA < + 70°C for the 1lA339.
VIO
Input Offset VoltageS
110
Input Offset Current
(II+)-(Ij-)
118
Input Bias Current
11+ or 11- with Output
in Linear Range
0
9.0
9.0
rnV
± 100
±150
nA
300
400
nA
VIR
Input Voltage Range
VSAT
Saturation Voltage
VI- ;;;'1.0 V,
VI+ =0 V,
10L <4.0 rnA
700
700
rnV
ICEX
Output Leakage
Current
VI+ ;;;'1.0 V,
VI- =0 V,
Vo=30 V
1.0
1.0
IlA
VIO
Differential Input
Voltage4
Keep all VI's;;;' 0 V
(or V-, if used)
36
36
V
8-13
(V+)-2.0
0
(V+)-2.0
V
JlA 139 • JlA239 • JlA339
JlA2901 • JlA3302
J,!A2901, J,!A3302
Electrical Characteristics TA = 25°C, V+ = 5.0 V, unless otherwise specified.
1lA2901
Symbol
Characteristic
Condition
VIO
Input Offset Voltage5
118
Input Bias Current1
11+ or 11- with Output
in Linear Range
110
Input Offset Current
(11+)-(11-)
VIR
Input Common Mode
Voltage Range2
Icc
Supply Current
Avs
Large Signal Voltage
Gain
Min
Typ
RL = co, V+ = 30 V
RL~15 kn,
25
Max
Min
Typ
Max
Unit
±2.0
±7.0
±3.0
±2.0
mV
25
250
25
500
nA
±S.O
±50
±S.O
± 100
nA
(V+)-1.5
V
0
RL = co on all
Comparators
1lA3302
(V+)-1.5
0.8
2.0
1.0
2.5
100
0
0.8
2.0
2.0
mA
30
V/mV
300
300
ns
1.3
1.3
j.lS
16
mA
V+ = 15 V (To
Support Large Vo
Swing)
tpD1
Large Signal
Response Time
VI = TTL Logic Swing,
VREF = 1.4 V,
VRL = 5.0 V,
RL = 5.1 kn
tpD2
Response Time3
VRL = 5.0 V,
RL = 5.1 kn
10L
Output Sink Current
VI- ~1.0 V,
VI+ =0 V,
Vo~1.5 V
VSAT
Saturation Voltage
VI- ~1.0 V,
VI+ =0 V,
10L ~4.0 mA
400
ICEX
Output Leakage
Current
VI+ ~1.0 V,
VI- =0 V,
Vo= 30 V
200
6.0
8-14
16
2.0
250
SOO
mV
200
nA
IlA 139 - IlA239 - IlA339
IlA2901 -IlA3302
1lA2901, 1lA3302 (Cont.)
Electrical Characteristics -40°C';;;; T A';;;; + 85°C, V+ = 5.0 V, unless otherwise specified.
1lA2901
Symbol
Characteristic
Condition
Via
Input Offset VoltageS
110
Input Offset Current
(II+)-(Id
liB
Input Bias Current
11+ or 11- with Output
in Linear Range
Min
Typ
9.0
VIR
Input Voltage Range
VSAT
Saturation Voltage
VI- ;;;;'1.0 V,
VI+ =0 V,
10L <4.0 rnA
ICEX
Output Leakage
Current
VID
Differential Input
Voltage4
1lA3302
Min
Max
15
Typ
Max
Unit
40
mV
50
200
300
nA
200
500
1000
nA
(V+)-2.0
0
0
(V+)-2.0
V
700
700
mV
VI+ ;;;;'1.0 V,
VI- =0 V,
Vo= 30 V
1.0
1.0
p.A
Keep all VI's;;;;' 0 V
(or V-, if used)
V+
V+
V
400
Notes
1. The direction of the input current is out of the IC due to the PNP input
stage. This current is essentially constant, independent of the state of
the output so no loading change exists on the reference or input lines.
2. The input common mode voltage or either input signal voltage should
not be allowed to go negative by more than 0.3 V. The upper end of
the common mode voltage range is (V+) - 1.5 V, but either or both
inputs can go to + 30 V without damage.
3. The response time specified is for a 100 mV input step with 5.0 mV
overdrive. For larger overdrive signals 300 ns can be obtained, see
typical periormance curves segment.
4. Positive excursions of input voltage may exceed the power supply level.
As long as the other voltage remains within the common mode range,
comparator will provide a proper output state. The low input voltage
state must not be less than -0.3 V or 0.3 V below the magnitude of
the negative power supply, if used.
5. At output switch pOint, Vo= 1.4 V, Rs = 0 fl with V+ from 5.0 V; and
over the full input common mode range 0 V to V+ -1.5 V.
6. For input signals that exceed Vee. only the overdriven comparator is
affected. With a 5.0 V supply, VI should be limited to 25 V maximum
and a limiting resistor should be used on all inputs that might exceed
the positive supply.
8-15
pA 139 • pA239 • MA339
MA2901 • MA3302
Typical Performance Curves for 1lA139, 1lA239, 11339
Supply Current
1.0
",
0.8
I
..
o.a
/"
a:
a:
::>
u
~
o.
o.
--I--
1
Ii
Input Bias Current
f'
TA = -wc
i
o
i
80
~
_T~=
~
~
-
20
I
RLa ..
o
10
Z
0
~
l
""
20
10
I-
::>
rrTAo *12&OC
S
-
0.001
40
30
SUPPLY VOLTAGE - V
SUPPLY VOLTAGE - V
,
0
5.0 mY ,.. INPUT OVERDRIVE
2Om~
100mV
.0
"
'~'~Vo
.
\
0
_
-
...
"
Response Time for Various Input
Overdrives - Positive Transition
;
6.0
g
~
!;
o
n
'" ""
4.G
3.0
2.0
5mV
l20mv
II
I
I
.0
J 1
0
1.0
TIME -"s
1.5
I
1
+5.0 V
""
TYi
I
2.0
o.s
-
...
~
v. -
1-
r- r-Yi - 0.5
I
INPUT OVERDRIVE,.. 100 mY
IV s.o
I!
Vo
I I
1.0
TlME-"s
8-16
1.5
~~
/~ '/
:%
0.G1
"TA = 25'C
,/
0.1
1.0
10
OUTPUT SINK CURRENT - mA
PCOe9OOF
Response Time for Various Input
Overdrives - Negative Transition
~~
0.G1
0
'"
~
0. ~A=-55OC
0.1
3
"-
~Tr1i
o
o
40
30
20
TA=12SOC~
~
I-
-"t=11'c-
1.0
~
-SS'C
~40 _T~"J
;;.J:.j
I
G.2
.."
c
1"_
Tt=~
,.
>
I
RI(eY) .. 10· Q
l
,V
0.'
10
VI(JMI' Jv
...J.
1
TA" o-i:-
---
Output Saturation Voltage
80
2.0
....
100
J.lA 139 • J.lA239 • J.lA339
J.lA290 1 • J.lA3302
Typical Performance Curves for 1lA2901, IlA3302
Supply Current
RL =
k--"
GO
1.2
E
Iiw
......T.
=-4C)OC
TA
1.0
/"
.. ......'"
..
~ 0.8
I
.......
....... ~
......
0.8
~ ~oocl
TA =
8.0 r--r--.--r---rs.o-m-Y....=-ITNPUT---r-ove-rRD-R"TIVE---r
w
s.o
3.0
II
2Om~
1-:-:-+--tt--tl-+-+Y'~+5.0Y
5.1 kfl-
Yo _
2.0
0
100 mY
.0
~
!:i
4.0
3.G
g
§
-
~ ~~+-4-~~~I-:-:-+-1--r-+-1
~!:i
~r
~
~ -100 1-+--+-+-+-+-+-+ TAr
!
~
u
TlME-,uS
u
i
U
2.0
.0
'E
~
s.o
I
g
!;
~
0
n
r
"- ~
ISmY
120 mY
I I
IJ J
I
II
I +5.0 V
V, -
+
-SO-100
_
~'~
~
rTie -
Vo-
-
-
I I I
I
0.5
1.0
TIME -p.S
8-17
1.5
~
V
~
/
a
0.01
r
0.1
~ K:"
~
'TA=OOC
riC
1.0
10
OUTPUT SINK CURRENT - mA
I
6.o INPUT OVERDRIVE .. 100 mY
i
0~+-4-~~~1-:-:-~~-r-+~
I
~
40
30
20
"·C, f\... ~V
/
0.01
::>
Response Time for Various Input
Overdrives - Positive Transition
i
I
.....
!;
0
SUPPLY YOLTAGE - Y
~
4 .0
r-
..~
~~
T.=85"C
TA.
0.1
0.001
10
V
Response Time for Various Input
Overdrives - Negative Transition
!;
!;
o
o
40
30
SUPPLY VOLTAGE -
g
I
i
85
20
~
-
---T T-
-
z
0
ooc
Td:.:
Tj=85 -
r--
1..-:
1.0
g
....-t ...~-
......
V 10
'E
>
"~
::>
.
=-4O"e
w
...........
'"'"::>
u
"~
10
80
"...
c
I
Output Saturation Voltage
Input Bias Current
2.0
?"
100
MA 139 • MA239 • MA339
MA2901 • MA3302
Application Information
Typical Applications (V+
The pA 139 series are high gain, wide bandwidth devices
which, like most comparators, can easily oscillate if the
output lead is inadvertently allowed to capacitively couple
to the inputs via stray capacitance. This shows up only
during the output voltage transition intervals as the comparator changes states. Power supply bypassing is not required to solve this problem. Standard PC board layout is
helpful as it reduces stray input! output coupling. Reducing
the input resistors to < 10 kn reduces the feedback signal
levels and finally, adding even a small amount (1.0 V to
10 mY) of positive feedback (hysteresis) causes such a
rapid transition that oscillations due to stray feedback are
not possible. Simply socketing the Ie and attaching resistors to the leads will cause input! output oscillations during
the small transition intervals unless hysteresis is used. If
the input signal is a pulse waveform, with relatively fast
rise and fall times, hysteresis is not required.
=15 V)
AND Gate
V+
39kQ
3.0kQ
A
B
C
V:::r
"::"
"0·"1"
OR Gate
V+
All leads of any unused comparators should be grounded.
The bias network of the pA 139 series establishes a drain
current which is independent of the magnitude of the power supply voltage over the range of 2.0 V to 30 V.
3.0kQ
200kQ
A
It is usually unnecessary to use a bypass capacitor across
the power supply line.
B
C
V;=r
The differential input voltage may be larger than V+ without damaging the device. Protection should be provided to
prevent the input voltages from going more negative than
-0.3 V (at 25°C). An input clamp diode can be used as
shown in the applications segment of this data sheet.
"::"
"0·"1"'
f=A-B·C
Monostable Multivibrator
The output of the pA 139 series is the uncommitted collector of grounded emitter NPN output transistor. Many collectors can be tied together to provide wired OR output
function. An output pull-up resistor can be connected to
any available power supply within the permitted supply
voltage range. There is no restriction on this voltage due
to the magnitude of the voltage which is applied to the
V+ terminal of the pA139 package. The output can also
be used as a simple SP/ST switch to ground (when a pull
up resistor is not used). The amount of current which the
output device can sink is limited by the drive available
(which is independent of V+) and the ~ of this device.
When the maximum current limit is reached (approximately
16 rnA), the output transistor will come out of saturation
and the output voltage will rise very rapidly. The output
saturation voltage is limited by the approximately 60 n
saturation resistance of the output transistor. The low offset voltage of the output transistor (1.0 mY) allows the
output to clamp essentially to ground level for small load
currents.
ol
to -It-..,---.-........-t
l00pF
;:J""E o
PW
---V+
1mB _
_
to It
lN914
Vo
o.o01F
1.0MQ
8-18
p.A 139 • p.A239 • MA339
MA2901 • MA3302
Typical Applications (V+
= 15
V) (Cont.)
Monostable Multivlbrator with Input Lock Out
Bistable Multivibrator
V.
V·
100kO
15kO
51kO
v:::n..
S
.Ii:.15 V
R
v::::n..
1OOkO
.'"
100kO
0
--IE
<4 V
1,..
0
-::-
Vo
1OOkO
Vo
240kO
62 kO
-=CA"",F
Squarewave Oscillator
Time Delay Generator
V·
V.
4.3kO
1OOkO
10kO
15 kO
200
3.0 kO
10kO
V;::r
'. ..
51 kO
INPUT GATING
SIGNAL
1OkO
Ve,
3.0 kO
1OOkO
10MO
10kO
V;:n..
_
to
"'+VI-+
V;:r
V.
10 12
aOkO
51 kO
v+
•
----------.,.-~-
10 kO
V.
v;:r
~ct V2
I
"
-.12
..
v,
Vo
100kO
V.·-..:.Wlr-..........---'\/V'._--I
V.,
10 "
f4
51kO
~_
8-19
CR02370F
IlA 139 • IlA239 • IlA339
IlA2901 • IlA3302
Typical Applications (V+
=15 V) (Cont.)
Large Fan-In AND Gate (Note 1)
Pulse Generator
V+
V+
Dl
lN914
R1 (NOTE 4)
l.oUO
R2
100 leO
V::r
VO(NOTE 3)
"0· "I"
l.oUO
(NOTE 2)
Wired-OR Outputs
V+
Vo
Notes
1) All resistor values in ohms.
2) All diodes 1N914.
3) Vo=A-e-c-o
4) For large ratios 01 Rl/R2. 01 can be omitted.
8-20
15 kO
/lASS8S
Ultra Fast
Single Latched Comparator
FAIRCHIL.D
A Schlumberger Company
Linear Division Comparators
Connection Diagram
10-Lead Metal Package
(Top View)
Description
The !lA6685 is an ultra fast single voltage comparator
manufactured with an advanced high speed bipolar process that makes possible very short propagation delays
(2.7 ns) with excellent matching characteristics. The comparator has differential analog inputs and complementary
logic outputs compatible with most forms of ECL. The output current capability is adequate for driving terminated
50 n transmission lines. The low input offsets and short
delays make this comparator especially suitable for high
speed precision analog to digital processing.
GND1
+IN
-IN O:~t-:,..~---:;-4:J Q OUT
The !lA6685 is lead compatible with the AM6685 and
functionally compatible with AD9685 and SP9685.
•
•
•
•
•
•
~~----::OQOUT
v-
2.7 ns Typical Propagation Delay
Complementary ECl Outputs
50 n line Driving Capability
Built-In Latch
Typical Output Skew 0.2 ns
Propagation Delay Constant With Overdrive
Order Information
Device Code
!lA6685HM
!lA6685HV
Package Code
5X
5X
Package Description
Metal
Metal
Connection Diagram
16-Lead DIP
(Top View)
Connection Diagram
50-14 Package
(Top View)
16
GND1
14
GND2
Q OUT
NC
v+
NC
+IN
NC
-IN
NC
OUT
GND2
Q
GNDI
NC
v+
v-
+IN
LATCH ENABLE
NC
NC
-IN
NC
NC
Q OUT
LATCH ENABLE
Q OUT
NC
NC
v-
NC
CD00961F
Order Information
Device Code
!lA6685SV
Package Code
Package Description
KD
Molded Surface Mount
Order Information
Device Code
!lA6685DM
!lA6685DV
!lA6685PV
8-21
Package Code
68
68
98
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
J.LA6685
Absolute Maximum Ratings
Storage Temperature Range
Metal Can and Ceramic DIP
Molded DIP and SO-14
Operating Temperature Range
Extended (!lA6685M)
Industrial (!lA6685V)
Lead Temperature
Metal Can and Ceramic DIP
(soldering, 60 s)
Molded DIP and SO-14
(soldering, 10 s)
Internal Power Dissipation 1, 2
10L-Metal Can
16L-Ceramic DIP
16L-Molded DIP
SO-14
Positive Supply Voltage
Negative Supply Voltage
Input Voltage
Differential Input Voltage
Output Current
Minimum Operating Voltage (V+ to V - )
-65°C to + 175°C
-65°C to + 150°C
-55°C to + 125°C
-30°C to + 85°C
300°C
1.07 W
1.50 W
1.04 W
0.93
+7.0 V
-7.0 V
!4.0 V
!6.0 V
30 mA
9.7 V
265°C
Notes
1. TJ Max = 150·C for the Molded DIP and 80·14, and 175·C for the Metal
Can and Ceramic DIP.
2. Ratings apply to ambient temperature at 25·C. Above this temperature,
derate the 10l-Metal Can at 7.1 mWrC, the 16l-Ceramic DIP at
10 mWrC, the 16l-Molded DIP at 6.3 mWrC, and the 80-14 at
7.5 mWrC.
Equivalent Circuit
V+--~--~--------~----------T---~~--~--------~--~--'
~------~~--~--+---~r-~r-r----+--~----+-T---~----~----------GND2
-IN
GN01
Q
V-------~
____
~--------~----~----------_4
______________ ______________
~
~
EQOO360F
8-22
MA6685
1lA6685V, 1lA6685M
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, unless
otherwise specified.
DC Characteristics
/lA6685M
"A6685V
Symbol
V,O
Condltlon 1
Characteristic
Input Offset Voltage
Rs < 100
Rs<100
n,
n
n
Min
T A = 25°C
-3.0
Typ
Max
0.3
-3.5
Min
+3.0
-2.0
+3.5
-3.0
Typ
0.3
Max
+2.0
"vrc
Average Temperature
Coefficient of Input
Offset Voltage
Rs<100
1'0
Input Offset Current2
25°C < TA < TA Max
-1.0
0.2
+1.0
-1.0
0.2
+1.0
TA=TA Min
-1.3
0.3
+1.3
-1.6
0.3
+1.6
liB
Input Bias Current
VCM
Common Mode Voltage Range
CMR
Common Mode Rejection
4.0
25°C
I-
t-t-t-t-t-t--t--t--H
Yr= -S.2V
°O~~~l00~~200f--L~~~~-~L-~~SOO
0.2
'PD
-"-~-~
TIME-ns
5
~
%
e
~
;
1"- ......
-4.0
-4.S
~
~m
-4.6
TEMPERATURE-"C
-4.8
-5.0
-5.2
-5.4
-5.6 -5.8
NEGATIVE SUPPLY VOLTAGE-V
PC06550F
Positive Common Mode Limit vs
Positive Supply Voltage
-0.6
4.5
-0.7
>
I -0.9
§ -1.0
............
!:l
~
~
~ ......
-
5.6
5.8
6.0
6.2
6.4
POsmVE SUPPLY VOLTAGE-V
6.8
~ -1.0
!:l
~
5Q. -1.6
~ -1.7
VOL
-1.5
-1.9
-1.9
-M-~-15
5
~
~
~
TEMPERATURE-oC
8-24
H
~
VOH
1-0.8
-1.8
-2.0
2.S
I
-0.8
>
-1.6
lS
-1.7
r-'""
5.4
..... ~
-0.6
-0.7
~
J
v'!--
-0.8
...... r-'""
Output Levels vs
Negative Supply Voltage
Output Levels vs Temperature
m
-r-..
-;:'r-..
r-_
-2.0
-4.6 -4.8
-S.O
-5.2
-5.4
-5.6
NEGATIVE SUPPLY VOLTAGE-V
-5.&
MA668S
Typical Performance Curves (Cont.) TA = 25°C, V+ = 6.0 V, V - = -5.2 V, Vr = -2.0 V, RL = 50 n, and
switching characteristics are for Vin = 100 mV, VOD = 10 mV, unless
otherwise specified.
Output Levels vs DC Loading
Supply Currents vs Temperature
-0.6
/2002
'\ J
-0.8
.1
r r- -!";...
>
~ -0.9
II
!i -1.0
~
g
1/502
-
..L
/
I
,2002
-1.6
J
5i!: -1.7
1/ 502
LOAD~
FOR
/
VOL
/
-1.9
o
12
16
20
~
~
II:
II:
.8
e
25
~
20
28
e;.
25
I
1-
::>
"
....
::>
ffi
e;.
10
I
6.0
6.2
6.4
.......
............
o
1.
12
!Zw
10
!Zw
10
~
~
1Mm
§
.."~
::>
l.I
..
::>
a;
o
-3
1\1
1/\
...
V"
-4
/1--'
'\
-2
-1
COMMON MODe VOLTAGE-V
o
-150
~v
-100
J
V
1\
"r-....
- 50
50
100
DIFFERENTIAL INPUT VOLTAGE-mY
8-25
-4.6
-4.8
-5.0
-5.2
-5.4
-5.6
NEGATIVE SUPPLY VOLTAGE-V
NON-INVERTING IN
1',
II:
II:
::>
.
~
5
INVERTING IN
12
II:
II:
-5.8
.....
,....
..
14
1.
a;
.."
16
I
-5.6
10
~
Input Current vs
Differential Input Voltage
16
-5.4
12
~
r- r- r-
TEMPERATURE-oC
I.
-5.2
a;
POSITIVE SUPPLY VOLTAGE-V
Input Bias Current vs
Common Mode Voltage
-5.0
::>
-~-~-~
6.8
---
_~f-
II:
II:
o
5.8
,~
,....~
....
Input Bias Current vs
Negative Supply Voltage
!Zw
.......
.... ~ ....
NEGATIVE SUPPLY VOLTAGE-V
12
a;
5.6
10
-4.6 -4.8
~m
M
16
~
15
"..:!
'~"
~
I.
.."~
..
,~
10
5.4
I
~
15
16
::>
~
.... ~ I--"
20
I.
II:
II:
20
~
5
Input Bias Current vs Temperature
!Z
w
II:
II:
::>
TEMPERATURE-"C
30
I
II:
II:
::>
15
-~-~-~
32
1-
!Zw
10
24
25
I
~
l - I---
Supply Currents vs
Positive Supply Voltage
E
E
."
..
1+
LOAD CURRENT-mA
e
-
I
~
Yr= -2.0V
'~ i--
-1.8
-2.0
30
30
\
-0.7
!;
Supply Currents vs
Negative Supply Voltage
150
-5.8
•
MA6685
Typical Applications (TA = 25°C)
High Speed Window Detector
+VREF
--T----I
IN
"-
OUT
50Q
+VREF
r
~
OJT
2oJmVl~iv.
/f
[\
-VREF
"-VREF
--T-----of
50Q
IN~mvt'v.
V
50Q
10ns/div.
-2.0V
High Speed Sampling
IN
LATCH
ENABLE
~
~Q--~--~--- OUT
IN
50Q
OUT
LATCH ENABLE
(Sample Rate = 100 MHz)
IJ [1 (
IJ IJ J
-2.0V
V\,
"\
\
if
-
/
\
(
\
\
5ns/div.
8-26
J .... IJ
(
5OOmV/dlv.
100mVldlv.
SOOmV/div.
MA6685
Measurement Of Propagation Delay
+6.0V
V+
~D
'LL
INPUT
FROM PULSE
GENERATOR
50Q
COAX CABLE
~
O.1iJ.F
HIGH SPEED
SCOPE PROBES
GND
tt::51.2".
(10%-90%)
5.0kQ
V'-----.M---t---<>I
50Q
50Q
50Q
-2.0V
-5.2V
Propagation delays tpo + (0 output) and tpo - (Q output)
are measured with input signal conditions of a 100 mV
step with an overdrive of 10 mV (the overdrive is the voltage in excess of that needed to bring the output to the
center of its dynamic range). Offset is compensated for by
adjusting VI until outputs are in the linear region while the
Pulse Generator is disconnected. VI is then increased in
the positive direction so inverting input changes by 10 mV,
i.e. the overdrive condition. Propagation delays are then
measured with actual input pulse condition of + 110 mV to
o V swing, with a tpo + or tpo - reading taken between
the + 10 mV level of the input pulse and the 50% point
of the outputs.
over the devices. If the IlA6685 is operated without air
flow, the change in electrical characteristics due to the increased die temperature must be taken into account.
Interconnection Techniques
All high speed Eel circuits require that special precautions
be taken for optimum system performance. The 1lA6685 is
particularly critical because it features very high gain
(60 dB) at very high frequencies (100 MHz). A ground
plane must be provided for a good, low inductance,
ground current return path. The impedance at the inputs
should be as low as possible and lead lengths as short
as practical. It is preferable to solder the device directly to
the printed circuit board instead of using a socket. Open
wiring on the outputs should be limited to less than one
inch, since severe ringing occurs beyond this length. For
longer lengths, the printed circuit interconnections become
microstrip transmission lines when backed up by a ground
plane, with a characteristic impedance of 50 to 150 n.
Reflections will occur unless the line is terminated in its
characteristic impedance. The termination resistors normally
go to -2.0 V, but a Thevenin equivalent to V- can be
used at some increase in power. Best results are usually
obtained with the terminating resistor at the end of the
driven line. The lower impedance lines are more suitable
for driving capacitive loads. The supply voltages should be
decoupled with RF capaCitors connected to the ground
plane as close to the device supply leads as possible.
Thermal Considerations
To achieve the high speed of the IlA6685, a certain
amount of power must be dissipated as heat. This increases the temperature of the die relative to the ambient
temperature. In order to be compatible with Eel III and
Eel 10,000, which normally use air flow as a means of
package cooling, the 1lA6685 characteristics are specified
when the device has an air flow across the package of
500 linear feet per minute or greater. Thus, even though
different Eel circuits on a printed circuit board may have
different power dissipations, all will have the same input
and output levels, etc. provided each sees the same air
flow and air temperature. This eases deSign, since the
only change in characteristics between devices is due to
the increase in ambient temperature of the air passing
8-27
J1A6685
Timing Diagram
Key To Timing Diagram
WAVEFORM
INPUTS
OUTPUTS
LATCH
ENABLE
MUST BE
STEADY
OIFFERENTIAL
INPUT
VOLTAGE
Q
MAY CHANGE
FROM HTOL
OUT
Q OUT
-- -----~~1----------~~:)'= 5~/.
WILLSE
STEADY
WIUBe
CHANGING
FROM HTOL
MAY CHANGE
FROM L TOH
WILL BE
DON'TeARE;
ANY CHANGE
PERMITTED
CHANGING;
STATE
UNKNOWN
CHANGING
FROM l TOH
Note
The set up and hold times are a measure of the time required for an input
signal to propagate through the first stage of the comparator to reach the
latching circuitry. Input signal changes occurring before ts will be detected
and held; those occurring after th will not be detected. Changes between ts
and th mayor may not be detected.
Definition Of Terms
VIO
Input Offset Voltage - That voltage which must
be applied between the two input terminals through
two equal resistances to obtain zero voltage
between the two outputs.
.lVlo/.lT Average Temperature Coefficient Of Input Offset
Voltage - The ratio of the change in input offset
voltage over the operating temperature range to the
temperature range.
Input Offset Current - The difference between
the currents into the two input terminals when there
is zero voltage between the two outputs.
Input Bias Current currents.
VOH
Output Voltage HIGH - The logic HIGH output
voltage with an external pull-down resistor returned
to a negative supply.
VOL
Output Voltage LOW The logic LOW output
voltage with an external pull-down resistor returned
to a negative supply.
1+
Positive Supply Current - The current required
from the positive supply to operate the comparator.
1-
Negative Supply Current - The current required
from the negative supply to operate the comparator.
Power Consumption - The power dissipated by
the comparator with both outputs terminated in 50 n
to -2.0 V.
The average of the two input
Switching Terms (see Timing Diagram)
Input Resistance - The resistance looking into
either input terminal with the other grounded.
tpD+
Input To Output HIGH Delay - The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50% point of
an output LOW to HIGH transition.
tPD-
Input To Output LOW Delay - The propagation
delay measured from the time the input Signal
crosses the input offset voltage to the 50% point of
an output HIGH to LOW transition.
tpD+(E)
Latch Enable To Output HIGH Delay The
propagation delay measured from the 50% point of
the Latch Enable Signal LOW to HIGH transition to
the 50% point of an output LOW to HIGH transition.
Input Capacitance - The capacitance looking into
either input terminal with the other grounded.
VCM
Common Mode Voltage Range - The range of
voltages on the input terminals for which the offset
and propagation delay specifications apply.
CMR
Common Mode Rejection - The ratio of the input
voltage range to the peak-to-peak change in input
offset voltage over this range.
PSRR
Power Supply Rejection Ratio - The ratio of the
change in input offset voltage to the change in power
supply voltages producing it.
8-28
MA6685
tpO-(E)
Latch Enable To Output LOW Delay The
propagation delay measured from the 50% point of
the Latch Enable signal HIGH to LOW transition to
the 50% point of an output HIGH to LOW transition.
ts
Minimum Set up Time The minimum time
before the negative transition of the Latch Enable
signal that an input signal change must be present in
order to be acquired and held at the outputs.
tpw(E)
Minimum Latch Enable Pulse Width The
minimum time that the Latch Enable signal must be
HIGH in order to acquire and hold an input signal
change.
Other Symbols
TA
Output load terminating
voltage
Rs Input source resistance RL Output load resistance
Yin Input pulse amplitude
Vee Supply voltages
V+ Positive supply voltage Voo Input overdrive
Frequency
V- Negative supply voltage f
Minimum Hold Time - The minimum time after
the negative transition of the Latch Enable signal
that the input signal must remain unchanged in order
to be acquired and held at the outputs.
8-29
Ambient temperature
VT
•
J,LA6687
Ultra Fast
Voltage Comparators
FAIRCHILD
A Schlumberger Company
Linear Division Comparators
Description
Connection Diagram
16-Lead DIP
(Top View)
The /lA6687 is an ultra fast dual voltage comparator manufactured with an advanced high speed bipolar process
that makes possible very short propagation delays (2.7 ns)
with excellent matching characteristics. These comparators
have differential analog inputs and complementary logic
outputs compatible with most forms of ECl. The output
current capability is adequate for driving terminated 50
transmission lines. The low input offsets and short delays
make these comparators especially suitable for high speed
precision analog-to-digital processing.
16
n
Separate latch functions are provided to allow each comparator to be independently used in a sample and hold
mode. The latch function inputs are designed to be driven
from the complementary outputs of a standard ECl gate.
If latch enable is HIGH and latch enable is LOW, the
comparator functions normally. When latch enable is driven
lOW and latch enable is driven HIGH, the comparator
outputs are locked in their existing logical states. Should
the latch function not be used, latch enable must be connected to ground.
Q OUT B
Q OUT
A
Q OUT
GND A
GNDB
B
LATCH ENABLE A
LATCH ENABLE B
LATCH ENABLE A
LATCH ENABLE B
v-
The /lA6687 is lead compatible with the AM6687 and with
the AD9687 and SP9687.
v+
-IN A
-IN B
+INA
+ IN B
Order Information
Device Code
j.lA6687DM
j.lA6687DV
/lA6687PV
• 2.7 ns Typical Propagation Delay At 10 mV
Overdrive
• Complementary ECl Outputs
• 50 n line Driving Capability
• 1.0 ns Latch Set up Time
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Extended (/lA6687M)
Industrial (/lA6687V)
lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation I, 2
16l-Ceramic DIP
16l-Molded DIP
Positive Supply Voltage
Negative Supply Voltage
Input Voltage
Differential Input Voltage
Output Current
Q OUT A
-65°C to + 175°C
-65°C to + 150°C
-55°C to + 125°C
-30°C to + 85°C
1.50 W
1.04 W
+7.0 V
-7.0 V
!4.0 V
!6.0 V
30 mA
Notes
1. TJ Max = IS0·C for the Molded DIP and 17S·C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 2S·C. Above this temperature,
derate the 16L·Ceramic DIP at 10 mWrC, and the 16L-Molded DIP at
8.3 mWrC.
8-30
Package Code
68
68
98
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
JlA6687
Electrical Characteristics Over the recommended operating temperature and supply voltage ranges, unless
otherwise specified.
DC Characteristics
JlA6687V
Symbol
Condition 1
Characteristic
Input Offset Voltage
VIO
110
Input Offset Current2
Input Bias Current
lis
VCM
Input Common Mode Range
CMR
Common Mode Rejection
Max.
Min.
Max.
-2.0
+2.0
-3.0
+3.0
-3.0
+3.0
-10
+10
-10
+10
JlV;oC
25°C
1-0.2
;-
...g~-1.0
-1.2
-1.4
-1.6
-4.6
-4.8
-5.0
-5.2
-5.4
2
-4
-5.6 -5.8
NEGATIVE SUPPLY VOLTAGE-V
-1
.1
r- POSrrWEOOMMoNMODEUMrr
~
3.$
I--
I
-4.0
5
~
%
"~1~~
TEMPERATURE-oC
2
4
6
~
\
\
t--... J
8
wnw
~
-so
~
60
......
u
~
-40
-70
~
Positive Common Mode Limit vs
Positive Supply Voltage
I
:E
:::i
1'-- .......
4.0
w
c
0
:E
1'-- ......
§
-$-~-~
o
!\
t:
~ -3.5
NEGATIVE COMMON MODE UMrr
I
1I
5
;-..-
I
4.$
-3.0
g
-3.$
\
\
GOUT
-: ~
>
w
i
10 :;
TlME-ns
-2.5
.J.
i"
-2
Negative Common Mode Limit vs
Negative Supply Voltage
4.0
~
-3
-\
COMMON MODE VOLTAGE-V
Common Mode Limits vs
Temperature
t
-1~
i"..
I
~
~-O.8
2~L-L-L-L-~L-~~~~~
10
i"..
/
I\.. ./
./
~ -0.6
'-
i"..
1/
z
0
:E
:E
1"-......
...... r--.,
-4.0
I
0
""" .....
3.$
..... "'"
.....
..........
"w
E 3.0
.....
I!!CL
-4.5
-4.6
-4.8
-5.0
-5.2
-5.4
-5.6 -S.B
NEGATIVE SUPPlY VOLTAGE-V
8-36
2.$
5.4
5.6
5.8
6.0
6.2
6.4
POSmVE SUPPLY VOLTAGE-V
6.8
U
Typical Performance Curves (Cant.) TA = 25°C, V+ = 6.0 V, V- = -5.2 V, Vr = -2.0 V, RL = 50 n, and
switching characteristics are for Yin = 100 mY, VOD = 5.0 mY, unless
otherwise specified.
Output Levels vs
Negative Supply Voltage
Output Levels vs Temperature
-0.6
-0.7
-
I-
.I ,.....
vo.!!.--
-0.8
>
I -0.9
_I-"""
w
~ -1.0
-0.6
-0.7
-0.7
-0.8
-0.8
I -0.9
~ -1.0
g
!;; -1.6
-1.6
g
I!:
5 -1.7
VOL
-1.7
-1.8
-1.8
-1.9
-1.9
-2.0
-2.0
-"-~-15
5
~
~
~
~
~
m
r-_ r-
-4.8
I
20
::>
...
::>
15
..
~
12
!Zw
10
a;
a;
.......
-4.B
r- t-
0;
o
-M-~-~
-5.0
-5.2
-5.4
-5.6
5
~
~
-
M M
TEMPERATURE-OC
32
Il
-5.8
5.'
5.6
~
0;
6.0
6.2
6.'
6.8
16
1
I
!Zw
-
-
..
!;;
5.8
POSITIVE SUPPLY VOLTAGE-V
,.
u
o
1~m
28
Input Bias Current vs
Common Mode Voltage
::>
r--..
24
I
Input Bias Current vs
Negative Supply Voltage
,.
10
20
10
-4.6
16
12
16
-- -
Supply Currents vs
Positive Supply Voltage
1-1-
1-- I-r--
15
,.
......
12
NEGAnVE SUPPLY VOLTAGE-V
Input Bias Current vs Temperature
::>
o
.... 1--" ....
,~
I-'"'
TEMPERATURE- OC
a;
a;
I
LOAD CURRENT -mA
10
10
Vr=-2.0V
VOL
...... f--' ....
::;
1+
u
-5.8
-
~g~D~
J
25
u
u
~
-S.6
/S02
30
!Zw
a;
a;
::;
""I
-5.4
Supply Currents vs
Negative Supply Voltage
""EI
25
ffi
!Zw
-5.2
r-!~r:- .i.
,/
...... ~
-1.9
30
I
i
-5.0
,L
-1.8
t-r--
-2.0
-4.6
30
::>
""""f-,.....
o
-
,2002 /S02
-1.6
-1.7
NEGATiVe SUPPLY VOLTAGE-V
Supply Currents vs Temperature
a;
a;
..5
!;;
VOL
1
TEMPERATURE- "C
~
r
II
:i -1.0
!:i
g
1
[2002
'J
w
!:i
g
1\
>
I -0.9
VOH
>
!:i
~
Output Levels vs DC Loading
-0.6
-4.6
a;
a;
12
10
::>
0
~
/,
-ssoc
I
w
"~
2.0
~
1.0
..S!
...-:
rl-)
IJ/
III
:g
0
-aD
-1.0
r---..
Z
TA = 25°C
>
I
1500
S!
3.0
"w
"~
1500
V
"X
./
./
V
1000 V
/'
V
~
,,-I.r
~rV ,,- _-~$>"
.... / -
,V
V
500
1300
-50
5.0
2000
S!
\
1400
1.0
z
C
\
w
"~
...1S\'"
;;;
\.
~
,V
2500
"' '\
I 1600
I
r-T.I =25'~
v- = -S.OY
~
TA = lZSOC
3000
V.I"2~
1700
~I (~
-1.0
-5.0
Voltage Gain vs
Supply Voltages
-20
20
60
100
140
12
11
10
13
14
POSITIVE SUPPLY VOLTAGE - V
TEMPERATURE _ °C
INPUT VOLTAGE - mY
"""."
Input Bias Current vs
Temperature
Input Offset Current vs
Temperature
50
2.0
v. ~ 12~
Y+ '.
V-=-6.0V
1
II!
i
V+ = 12V
v- = -7.0V
-5.0 V S VCM $: +5.0Y
'--
I-
I
I
30
§
"~
12~
v- = -6.GY
'\
1
40
I
!i
Common Mode Rejection Ratio vs
Temperature
"
20
i'\
~
.........
10
r--. .......
o
i
r- r-
o
o
-50
-20
20
r- .......
\
() 1.0
50
100
140
-50
-20
.......
""
20
i'
~
.........
Power Consumption vs
Temperature
100
60
TEMPERATURE -
TEMPERATURE - OC
100
r-.....
i'.
94
140
3.5
4.0
= -6.DV
3.0
I.....
................
./
50
....e~+J.!l!..~m.L
-::::: ~~""'A£
i'-
.........
20
100
140
oc
Output Voltage Levels vs
Temperature
J.=
\2V~_
v-
v- = -6.0Y
-20
TEMPERATURE -
Output Sink Current vs
Temperature
v. ~ 12~
-50
oc
~+=\2V'
v- = -6.0 V -
SHOlO
.......
~~
i'.
0
NEGATIVE OUTPUT LEVEL
75
-10
-20
20
50
100
TEMPERATURE _ °C
-1.0
1.0
140
-50
-20
20
50
TEMPERATURE _ °C
8-48
100
140
-50
I
-20
20
50
TEMPERATURE _ °C
100
140
MA710
Typical Performance Curves for 11A710 (Cont.)
Response Time for
Response Time for
Various Input Overdrives
Various Input Overdrives
>
4.0
I
3.0
W
~
2.0
~
.Jm~
I I
,II
10mY
V1
/~ i'-~.o ~v
,~
.0
~
>
I
3.0
!:j
2.0
~
'\r-..~
\
1.0
~
°r -
1
5
-1 .0
i
~
I
/IV
0
Common Mode Pulse Response
4.0
r\
o -IOiV
lot
"
WI
g~
~5.0mV
:I ..
~g
i'
I
W
100
!:i
~
so
!;i
~> or- r-
20
40
60
80
Y+= 12V
V- = -B.OV
TA = 2SOC
0
0
0
0
100
20
120
40
60
80
100
40
>
I
=OO,? ......
T.~JC, ~ /
r-- '.0
0
.>
.
....
W
";!
I
....
::>
0
'I
3.0
5.0
20
30
40
0
50
60
30
o
o
~
~
b-.
1.0
20
30
40
SO
TEMPERATURE - OC
60
"
~
!
70
14
V+:c 12V
v- .. -7.0Y
-5.0VSVCM:55.DV
98
-
I-
-
r-- I--
Ul
W
'" t"'--.
o
10
13
'""'""-
0:
o
l - t----.
102
I
~
~
'""'""- r-
f-
I.
11
Vi
0:
~
0:
o
t;
~~
0100
::>
0
-~ ~
~~
Common Mode Rejection Ratio vs
Temperature
I
::>
I-
POSITIVE SUPPLY VOLTAGE _ V
-6.DY
ffi
0:
~
V
10
70
vL,.J_
v- =
-6.0 V
1
10
~ ./' /
,/
400
10
..
v+=I.v
40
~
i!
~ 1200
TEMPERATURE _ °C
v-:;:;
"....
V~
..
1600
600
o
-I
JP .--
-I-
~
........
Input Offset Current vs
Temperature
50
en
20 t--..
iii
2000
~
..........
mY
Input Bias Current vs
Temperature
!
.........
1400
1200
1.0
,..,- ~ !--
z
1300
INPUT VOLTAGE -
1
I
....z
r--.....
~:= ~~.~v-
-1.0
-3.0
T~= 25~
'400
~I
~
A
-1.0
-5.D
2800
........
ISO
Voltage Gain vs
Supply Voltages
y- = -6.0V
'""'""-
1500
~
J
1.0
::>
I
z
TA'" 70"C
1//
l"-
,'0
80
V.'. 12V 1. _
-
~
..fI '-....
W
"~
1600
-
TIME-n.
1700
TA
Vo
~
120
Typical Performance Curves for JJA710C
Voltage Gain vs
Ambient Temperature
Voltage Transfer Characteristic
4.0
J.lA710
-
TIME-nl
TIME -nl
3.0
SOCl
r- 'VCM
o- r
0
I
50Cl
r-- r-
e-
Tj=ri
!
V- -6.0 V
A =25"C-
.0
-1.~r- 20mV
vLI,• V
v- =-6.0 V
0
~
i
2.0
I
'l!
W
0:
0:
J+== j.v ~_
!> 3-0
2.0 mY
iz
.....
010203040506070
TEMPERATURE -
8-49
oc
0
:I
:I
0
0
96
..
9.
0
10
20
30
40
so
TEMPERATURE _ °C
80
70
J,LA71 0
Typical Performance Curves for j.LA710C (Cont.)
Power Consumption vs
Temperature
Output Voltage Levels vs
Temperature
Output Sink Current vs
Temperature
4.0
'00
V!=.2J
-6.0 V-
V.'=.2V',_
v-:: -B.OY
v-=
~
I
~
~
90
8
85
I
-
3.0
~_
2.,
a
'"~
o
10
20
30
40
50
60
-
>
I
..
"~
~
~
4.0
,I
3.0
2Jm~
2.0
10mV
.0
0
o _..0
/~
1/11 V '"
......
v-"'"
~
100
~
50
~
i
·rr
0
10
1=("J
20
40
60
TIME
-ft.
80
100
1-1-
120
2•0
> •.0
7-
V-:: -6.0Y
0
a
1-1-1-
LOGJ~ THR~SHOLJ VOLTAGE- -
1.0
NEGATIVE OUTPUT LEVEL
..
> 4 •0
I
~ 3.0
I
2.0
0
'.5
20
30
so
40
60
I ..
O~i"r
- Of-- 20mV
1,\ i'
K
1\
~V
~r\
-..0
70
100
g
50
i
0
8-50
80
70
L
0
i'
-
500
- - 2.0 - -
500
0-
TA = 250C
60
60
Y-=-S.oV
VA=25°C._
S.OmV
V- =-B.OV -
TIME -n8
50
J.= kv ,_
0
>
=> ..
I!:~
.. ,
40
40
2.0mV
V+ = 12V
20
30
Common Mode Pulse Response
I
!:i
20
TEMPERATURE - OC
~
i
10
°C
Response Time for
Various Input Overdrives
2.0~V f--+-
y-:: -6.GV
POSIT',E ourUT LjVEL
>
~
5
TEMPERATURE -
vL 1'2 V 1-1-
I
~
......
V!=.2J,,_
o
70
,/
i/ll
po..,
-
I
,
~
I-- I---
~
TEMPERATURE _ °C
Response Time for
Various Input Overdrives
I
>
2.0
O~
80
75
'I
,
95
3.0
100
120
5!:i
g
.......
"A~
Vo
-
I-
VCM
,
•.0
0
40
80
TIME-ns
.20
.60
IlA711
Dual High Speed
Differential Comparator
FAIRCHILD
A Schlumberger Company
Linear Division Comparators
Description
Connection Diagram
10-Lead Metal Package
(Top View)
The I1A711 is a dual high speed differential comparator
featuring high accuracy, fast response times, large input
voltage range, low power consumption and compatibility
with practically all integrated logic forms. When used as a
sense amplifier, the threshold voltage can be adjusted
over a wide range, almost independent of the integrated
circuit characteristics. Independent strobing of each comparator channel is provided, and pulse stretching on the
output is easily accomplished. Other applications of the
dual comparator include a window discriminator in pulse
height detectors and a double ended limit detector for automatic Go/No-Go test equipment. The I1A711, which is
similar to the pA710 differential comparator, is constructed
using the Fairchild Planar Epitaxial process.
•
•
•
•
V+
V-
Lead 5 connected to case
Fast Response Time - 40 ns Typical
5.0 mV Maximum Offset Voltage
10 I1A Maximum Offset Current
Independent Comparator Strobing
Order Information
Device Code
pA711HM
pA711HC
Absolute Maximum Ratings
Storage Temperature Range
Metal Can and Ceramic DIP
Molded DIP
Operating Temperature Range
Extended (pA 711 M)
Commercial (pA711C)
Lead Temperature
Metal Can and Ceramic DIP
(soldering, SO s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1, 2
10L-Metal Can
14L-Ceramic DIP
14L-Molded DIP
Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
Strobe Voltage
Package Code
5X
5X
Package Description
Metal
Metal
Connection Diagram
14-Lead DIP
(Top View)
-S5°C to + 175°C
-S5°C to + 150°C
14
-55°C to +125°C
O°C to 70°C
NC
1.07 W
1.3S W
1.04 W
+14 V
-7.0 V
50 mA
±5.0 V
±7.0 V
o V to +S.O V
NC
-INA
STROBE A
+INA
GND
v+
v+IN B
OUT
-INB
STROBE B
NC
NC
c001061F
Notes
I. TJ Max -ISO·C for the Molded DIP, and 17S·C for the Metal Can and
Ceramic DIP.
2. Ratings apply to ambient temperature at 2S·C. Above this temperature,
derate the IOl·Metal Can at 7.1 mW·C, the 14l·Ceramic DIP at
9.1 mW·C, and the 14l·Molded DIP at 8.3 mW·C.
Order Information
Device Code
I1A711DM
pA711DC
I1A711 PC
8-51
Package Code
SA
SA
9A
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
I1A711
Equivalent Circuit
STROBE A
STROBE B
.---_4r_--------------~----~----~----~----~------------_4r_--~---v+
R4
4.3 kG
04
6.2 V
R1S
4.3kO
R14
4.3 kQ
06
018
R2
R12
9100
9100
R13
910n
R1
910 n
02
6.2 V
-INA
-IN B
GNO
+INA
+INB
R7
S.DS kO
R9
1200
R8
2400
R10
1200
L-----------------~~--------------------~------
_______V-
J.lA711
Electrical Characteristics T A = 25°C, V+ = 12 V, V- = -6.0 V, unless otherwise specified.
Symbol
VIO
Characteristic
Input Offset Voltage
Condition
Vo=1.4 V, Rs<200
Vo=1.4 V, Rs<200
110
Input Offset Current
lis
Input Bias Current
Avs
Large Signal Voltage Gain
tpD
Response
Time 1
tSTRL
Strobe Release Time
VIR
Input Voltage Range
n,
n
Min
VCM=O V
Vo=1.4 V
750
V- =-7.0 V
Typ
Max
Unit
1.0
3.5
mV
1.0
5.0
0.5
10.0
IJ.A
25
75
p.A
1500
VIV
40
ns
12
ns
± 5.0
V
±5.0
VIDR
Differential Input Voltage Range
Ro
Output Resistance
VOH
Output Voltage HIGH
VI ;;'10 mV
VOH
Loaded Output Voltage HIGH
VI ;;'10 mY, 10H = 5.0 mA
2.5
3.5
VOL
Output Voltage LOW
VI ;;'10 mV
-1.0
-0.5
VO(ST)
Strobed Output Level
VST<0.3 V
-1.0
V
n
200
8-52
4.5
5.0
V
V
0
V
0
V
JiA711
J.l.A711 (Cont.)
Electrical Characteristics T A = 25°C, V+ = 12 V, V- = -6.0 V, unless otherwise specified.
Symbol
Characteristic
Min
Condition
Typ
Max
Unit
10L
Output Sink Current
VI;;;' 10 mY, Vo;;;'O V
10(ST)
Strobe Current
VST = 100 mV
1.2
1+
Positive Supply Current
Vo = GND, Inverting Input = 5.0 mV
8.6
mA
1-
Negative Supply Current
Vo = GND, Inverting Input = 5.0 mV
3.9
mA
Pc
Power Consumption
The following specifications apply for -55°C
0.5
0.8
130
~
VIO
Input Offset Voltage2
110
Input Offset Current
liB
Input Bias Current
AVIO/ AT
Temperature Coefficient of Input
Offset Voltage
Avs
Large Signal Voltage Gain
mA
2.5
mA
200
mW
4.5
mV
6.0
mV
20
pA
TA ~ + 125°C
Rs ~ 200
Rs~200
n,
n
VCM = 0 V
150
!lA
!lV/DC
5.0
500
VIV
J.l.A711C
Electrical Characteristics T A = 25°C, V+ = 12 V, V- = -6.0 V, unless otherwise specified.
Symbol
VIO
Condition 1
Characteristic
Input Offset Voltage
Vo = +1.4 V, Rs~200
Vo=+1.4 V, Rs~200
110
Input Offset Current
liB
Input Bias Current
Avs
Large Signal Voltage Gain
tpD
Response Time 1
n,
n
Min
VCM=O V
Vo=+1.4 V
700
Typ
Max
Unit
1.0
5.0
mV
1.0
7.5
mV
0.5
15
!lA
25
100
1500
40
ns
12
ns
tSTRL
Strobe Release Time
VIR
Input Voltage Range
VIDR
Differential Input Voltage Range
Ro
Output Resistance
VOH
Output Voltage HIGH
VI;;;'lO mV
VOH
Loaded Output Voltage HIGH
VI ;;;'10 mY, 10H = 5.0 mA
2.5
3.5
VOL
Output Voltage LOW
VI;;;'lO mV
-1.0
-0.5
VO(ST)
Strobed Output Level
VST~0.3
-1.0
10L
Output Sink Current
VI;;;' 10 mY, Vo;;;'GND
10(ST)
Strobe Current
VST = 100 mV
1.2
1+
Positive Supply Current
Vo = GND, Inverting Input = 10 mV
8.6
V- =-7.0 V
±5.0
V
±5.0
V
n
200
V
8-53
4.5
0.5
!lA
VIV
5.0
V
0
V
0
V
V
0.8
mA
2.5
mA
mA
IlA711
p.A711C (Cont.)
Electrical Characteristics TA = 25°C, V+
Symbol
= 12
V, V-
= -6.0
Characteristic
1-
Negative Supply Current
Pc
Power Consumption
V, unless otherwise specified.
Min
Condition'
Typ
Max
Unit
230
mW
6.0
mV
10
mV
25
pA
3.9
Vo=GNO, Inverting Input = 10 mV
130
mA
The following specifications apply for O·C < TA < 70·C
Input Offset Voltage2
VIO
Rs<200
Rs <200
110
Input Offset Current
liB
Input Bias Current
fl.Vlo/fl.T
Temperature Coefficient of Input
Offset Voltage
Avs
Large Signal Voltage Gain
n,
n
VCM=O V
150
pA
/J.vrc
5.0
500
VIV
Notes
1. The response time specified is for a 100 mV step input with 5.0 mV
overdrive.
2. The input offset voltage is specified for a logic threshold as follows:
JJA711: 1.8 V at -55·C, 1.4 Vat + 25·C, 1.0 V at + 125·C
jJA711C: 1.5 V at O·C, 1.4 V at 25·C, 1.2 V at 70·C
Typical Performance Curves
Voltage Transfer
Characteristic p.A 711
5.0
4.0
>
I
OJ
"~
...~
:>
3.0
V+= 12Y
V- -&.OV
=
Voltage Transfer
Characteristic p.A711C
5.0
I
I
~
1 11
TA
lB.
=12S"C ....
>
I
r1L
III1
/I,
2.0
4.0
'II
TA = _55°C
I
.......T. = 25°C
Ii
~ 1.0
-3.0
-1.0
3.0
TA
1.0
3.0
5.0
INPUT VOLTAGE - mY
= ooc
II.
'fI1
i"A 'I...
IH~
2.0
VI
~
TA
-
>
~
~
...
~
i 7~C
TA = 250C
-3.0
-1.0
8-54
1. 0
0
J_ J,
yjV
'.
1~m~ jll il
II
'I
..< 5.~~V
?
KJ.omv
-1.0
I
1.0
INPUT VOLTAGE - mV
PCQ7200F
4. 0
3. 0
~
OJ
"~
g
-1.0
-5.0
5. 0
g 2-o
.4
II
1.0
0
VI
-1.0
-5.0
"~
~
...
:>
5
HI
:>
0
OJ
I
J
.L L
I-V.=12V
V-=-&.ov
Response Time for
Various Input Overdrives
3.0
5.0
~
i!<
V+
100
= 12V
V- = -6.0V
TA = 25°C
50
0
I
20
40
60
80
TIME -ns
100
120
p.A711
Typical Performance Curves (Cont.)
Voltage Gain vs
Temperature
1700
>
""
~
I
2800
"'\
1600
1500
i...
TAl.
J+.12V v-, -6.0V
2400
V
>
~ 2000
" "'\
I
~
...
~ 1400
"~
1,\
!:l
~
~
1"'\
1300
1600
1200
I\.
-20
20
800
100
140
V
1>0"
/p
V
-
y-·-6.0Y
TA
T
= 25Ge
CL
...'i
4.0
"~
0
_ _ 5.1kO
2.0
>
...
:::l
~
0
-,
_6.0y-f-f-
l~ c~1
fI
f- f-
....
......
~'::.~
t'--..
!;
~
"
40-
./
/
-2.0
10
"C
.....
~Yo
6.0
.....
,,'~~
".V~
..- V
400
60
TEMPERATURE -
/
alc
I-I,.....- V
;I.
Z
"'\
1200
-60
Output Pulse Stretching
With Capacitive Loading
Voltage Gain vs
Supply Voltages
13
12
11
100
14
300
200
TIME -ns
POSITIVE SUPPLY VOLTAGE - V
400
500
PC07240F
Common Mode Pulse Response
~
!> a 0
I II 1
::I" 1.0 f-
r
00
of-'
.f-
>
!; I 2. 0 -
.
~
0
'$.40
$I
~
E,
~
I
1 I
i
~
I
120
80
40
'\
'\
30
()
Vo
I I I I
J
y+ ~ 12~
y-. -6.0 V
\
TA'25"C
500
!;~ 1.0
0g
50
= 12V
v-. -6.0V
,
... I 2.0
g~
z!:l
V+
Strobe Release Time for
Various Input Overdrives
Input Bias Current vs
Temperature
160
........
10
-60
-
-20
20
60
100
140
~
V+ 12ly
y-. -6.0 V
I
z
o
f
~
130
l- I-
r... I'-...
I-"
()
I
120
-60
-20
20
60
~
100
1.0
0
2.0
~
1.0
140
TEMPERATURE - "C
8-55
§
i-""
/
vi. \2VI
y-. -6.0V
TA= 250C
I
5.omv....,
!;
Power Consumption vs
Temperature
~
a0
>
I
g
PC01210F
~
g
~
TEMPERATURE - "C
140
~
;! 2. 0
!
......
o
TIME -ns
"-
20
>
I
-1.0
-.
'i ~
2.omV
&V
10
OmV
1.omyL f-
20
TIME
30
-ns
40
50
p.A760
FAIRCHILD
High Speed
Differential Comparator
A Schlumberger Company
Linear Division Comparators
Description
Connection Diagram
8-Lead Metal Package
(Top View)
The pA7S0 is a differential voltage comparator offering
considerable speed improvement over the pA710 family
and operates from symmetric supplies of ± 4.5 V to
± S.5 V. The pA7S0 can be used in high speed analog-todigital conversion systems and as a zero crossing detector
in disc file and tape amplifiers. The pA7S0 output features
balanced rise and fall times for minimum skew and close
matching between the complementary outputs. The outputs
are TTL compatible with a minimum sink capability of two
gate loads.
•
•
•
•
•
V+
Guaranteed High Speed - 25 ns Max
Guaranteed Delay Matching On Both Outputs
Complementary TTL Compatible Outputs
High Sensitivity
Standard Supply Voltages
V-
Lead 4 connected to case
Order Information
Device Code
pA7S0HM
pA7S0HC
Connection Diagram
14-Lead DIP
(Top View)
Ne
Ne
Ne
Ne
V+
Ne
V+
IN2
OUT 1
IN2
OUT 1
INI
OUT 2
INI
OUT 2
v-
ONO
Ne
Ne
V-
Order Information
Device Code
pA7S0RM
pA7S0RC
Order Information
Package Code
SA
SA
OND
COO'09OF
CD01080f
Device Code
pA7S0DM
pA7S0DC
Package Description
Metal
Metal
Connection Diagram
8-Lead DIP
(Top View)
14
Ne
Package Code
5W
5W
Package Description
Ceramic DIP
Ceramic DIP
8-5S
Package Code
ST
ST
Package Description
Ceramic DIP
Ceramic DIP
IlA760
Absolute Maximum Ratings
Storage Temperature Range
Metal Can and Ceramic DIP
Molded DIP
Operating Temperature Range
Extended (MA760M)
Commercial (!1A760C)
Lead Temperature
Metal Can and Ceramic DIP
(soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation l , 2
8L-Metal Can
14L-Ceramic DIP
8L-Ceramic DIP
Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Differential Input Voltage
Input Voltage
-65°C to + 175°C
-65°C to + 150°C
-55°C to + 125°C
O°C to 70°C
1.00 W
1.36 W
1.30 W
+8.0 V
-8.0 V
10 mA
±5.0 V
V+ >VI >V-
300°C
265°C
Notes
I. TJ Max - 175°C.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the SL-Metal Can at 6.7 mW'oC, the 14L-Ceramic DIP at
9.1 mwrc, and the SL-Ceramic DIP at S.7 mW'oC.
Equivalent Circuit
.-~----~------~----~--------------------~
R2
Rl
--~
RIS
SkO
1k0
1 kO
__
__
---------4~--~~----------~--V+
R16
6200
Rll
1050 0
OUT 1
~
INI
IN 2
__--------+-----+-~--------~----~--GND
----1----1
1-_________________ OUT 2
R3
R5
R7
350 0
3500
3500
Rl'
3500
L-----~------+_----~~----~----~~----~------------------------------------vEQ00420F
8-57
J.lA760
IlA760
Electrical Characteristics Vee = ± 4.5 V to ± 6.5 V, T A = -55°C to + 125°C, T A = 25°C for typical figures,
unless otherwise specified.
Symbol
Condition
Characteristic
Rs~200
Min
n
Ty~
Max
Unit
VIO
Input Offset Voltage
1.0
6.0
mV
110
Input Offset Current
0.5
7.5
pA
liB
Input Bias Current
8.0
60
pA
Ro
Output Resistance (either output)
Vo= VOH
tpo
Response Time
TA = 25°C1
30
ns
18
TA=25°C2
25
16
(Note 3)
~tpo
n
100
ns
Response Time Difference
between Outputs 1
(tpo of +VI1)-(tpO of -VI2)
TA = 25°C
(tpo of + V12) - (tpo of - V11)
TA = 25°C
5.0
(tpo of + VII) - (tpo of + V12)
TA = 25°C
7.5
5.0
7.5
(tpo of -VI1) - (tpo of -VI2)
TA = 25°C
RI
Input Resistance
f = 1.0 MHz
12
CI
Input Capacitance
f = 1.0 MHz
8.0
pF
3.0
pV/oC
2.0
nArC
n,
~Vlo/~T
Average Temperature Coefficient of
Input Offset Voltage
Rs = 50
~llo/~T
Average Temperature Coefficient of
Input Offset Current
TA = 25°C to 125°C
VIR
Input Voltage Range
Vee=±6.5 V
VIOR
Differential Input Voltage Range
VOH
Output Voltage HIGH (either
output)
TA = -55°C to + 125°C
7.0
TA = + 25°C to -55°C
o mA ~ 10H ~ 5.0
±4.0
mA
kn
±4.5
V
±5,0
V
2.4
3.2
V
2.4
3.0
Vee = +5.0 V
10H = 80 pA, Vee = ± 4.5 V
0.25
0.4
V
Vee = ±6.5 V
18
32
mA
Vee=±6.5 V
9.0
16
mA
VOL
Output Voltage LOW (either
output)
10L =3.2 mA
1+
Positive Supply Current
1-
Negative Supply Current
Notes
1. Response time measured from the 50% point of a 30 mVp-p 10 MHz
sinusoidal input to the 50% point of the output.
2. Response time measured from the 50% point of a 2.0 V POp 10 MHz
sinusoidal input to the 50% point of the output.
3. Response time measured from the start of a 100 mV input step with
5.0 mV overdrive to the time when the output crosses the logic
threshold.
8-58
J.1A760
/JA760C
Electrical Characteristics Vee = ± 4.5 V to ± 6.5 V, TA = O°C to 70°C, TA = 25°C for typical figures, unless
otherwise specified.
Symbol
Characteristic
Condition
Min
n
Typ
Max
Unit
VIO
Input Offset Voltage
1.0
6.0
mV
110
Input Offset Current
0.5
7.5
MA
8.0
60
MA
30
ns
Rs<200
118
Input Bias Current
Ro
Output Resistance (either output)
VO=VOH
tpD
Response Time
TA = 25°C '
TA = 25°C2
18
(Note 3)
16
dtpD
n
100
25
ns
Response Time Difference
between Outputs 1
(tpD of +Vll) - (tpD of -VI2)
TA = 25°C
5.0
(tpD of +VI2)-(tpD of -VII)
TA = 25°C
5.0
(tpD of + VII) - (tPD of + V12)
TA = 25°C
10
10
(tpD of -VII) - (tPD of -VI2)
TA = 25°C
RI
Input Resistance
f= 1.0 MHz
12
kn
CI
Input Capacitance
f= 1.0 MHz
8.0
pF
dVIO/dT
Average Temperature Coefficient of
Input Offset Voltage
Rs = 50
3.0
MV/oC
diIO/dT
Average Temperature Coefficient of
Input Offset Current
TA = 25°C to 70°C
5.0
nA/oC
VIR
Input Voltage Range
Vce = ±6.5 V
VIDR
Differential Input Voltage Range
VOH
Output Voltage HIGH (either
output)
n,
TA = O°C to 70°C
10
TA = 25°C to O°C
±4.0
±4.5
V
±5.0
V
V
o mA
I
>
I
Vee- t5Y
w
TA = 25°e -
";!
~
2OmV..,
2
I•
,.mV-'!
1
~
g
50
~
i
~
2
~~=~o~V
3
Vcc=tSV
10 MHz SINE WAYE INPUTS
TAo = 25°C
_
~ V2jV
20mV
!
~5mv
1
I
w
,.mV" ~
•"..
~
I
100
~
o
~
~
40
4
~
~ -5mV
~ 2mV
Response Time vs
Input Voltage
e
10
15
20
25
30
35
i
Ipd-
!w
~
-- '''- --
.,z
2
I
~ 100
~
•
1
30
13II:
I
I
20
I
I
50
•
I.
10
TIME-M
15
20
25
30
35
1
12
INPUT VOLTAGE - mVp•p
TIME - ns
Response Time vs
Input Voltage
I.
2
Voltage Transfer Characteristic
Voltage Transfer Characteristic
30
Vee = tSV
Ycc=t5V
10 MHz SINE WAVE INPUTS
TAo = 25°e
~
I
f"'...
20
...-
I"'---.
w
:IE
.,..
'
Z
0
W
I--+-I--+_/-,:!-/I-
. r-
;::
.,w
:
>
I
w
vJ =tiD v
"~
g
-
~
10
5o
II:
1
/I!
•
10
20
50
100 200
500 1000 2000
INPUT VOLTAGE -
Voltage Gain vs
Supply Voltage
~~2==~=_~,==~~---L--L--L--J
INPUT VOLTAGE - mY
mV
Voltage Gain vs
Temperature
Input Bias Current vs
Temperature
12
8000
TA = 25°C
4000
8000
~
7000
~
-
,,/
I 8000
~5000
~4000
3000
2000
/'
Vee
vcc=t5V
.........
1
"I'...
V ...
!
i:!>
I
VJ
~2~==~_I~~'~Z'..~!~-L--~-L~
INPUT VOLTAGE - mVp•p
iii
I/P
"....-
...zI
,
........
W
'"'"
~
".,~
r'\.
= t6.5 V
I'...
II:
"'
...
"!I:
/
L
t4.S
I. I,
2000
ts.o
u.s
t6.0
SUPPLY VOLTAGE - V
t6.S
....
-2.
20
50
TEMPERATURE _ °C
8-60
100
14.
•
-50
-2.
2.
50
TEMPERATURE _ °C
100
14.
pA760
Typical Performance Curves (Cont.)
Input Offset Current vs
Temperature
'.0
.,
e~
\
0.8
30
Vee = tI.sv
,
w
:>
!
!w
'\
:>
u
"
0.0
'''-
-r-
I
II>
W
a:
'0
V~H @'IO ='5.0 ~A
-
,
I
~
L,.....- li-"" 1-1-""
r- :-- r'''-
II>
0.2
Vee = t5Y
>
20
z
2 '5
.......
-
25
2
w
a: 0.0
a:
...
:~ ~±::::~=~,!Hz
~
z
Iii
~
0
Output Voltage Levels vs
Temperature
Response Time vs
Temperature
~/CTI1"£
Votr"'Oe
~
VOL @ ISINK
-20
20
60
'00
TEMPERATURE - OC
25
w
:E
w
!!
a:
20
80
'00
-eo
'40
20
I
l-
I
25
,
15
'0
~
'0
,
5
10
CAPACITIVE LOAD -
50
'00
200
pi'
I
20
!
I
,
o
I
'00
'40
oc
Vee
10
Y
8-61
'2
10
~
!!iu
i..
:>
~
50
CAPACITIVE LOAD - pF
Common Mode Range vs
Supply Voltage
,
Iiw
e
100 200
= t6.SV
=25"C _
L,.....-f-"-TA
.0
a:
-
PC;07420F
SUPPLY VOLTAGE -
= 3.2 mA
80
18
Vee = t5Vi
= 250C
2
20
Input Bias Current vs
Differential Input Voltage
TA
'5
o
-20
TEMPERATURE -
30
= t5V
TA = 250C
Vee
;::
-20
Fall Time vs
Capacitive Load
30
,
-eo
TEMPERATURE - "c
Rise Time vs
Capacitive Load
2
o
5
140
.,.,.- -r,;;;
!/
,/
<
I'."
" "- .......
I,..
20
40
r80
--80
DIFFERENnAL INPUT VOLTAGE - mY
'00
p.A760
Typical Applications (Note 1)
Line Receiver With High Common Mode Range
R.
.....---.,
Fast Positive Peak Detector
IN -.iV'~-""IIr---~:.j ~"'--'---- OUT
Rl
PI
FD888
IN -""">IV-------.,..,L~--- OUT
RS
JL
-Ifso ...
Common mode range
= ±4)( ~
Differential input sensitivity
V
= 5 x ~ mV
p, must be adjusted for optimum common mode rejection.
For As = 200 0
Common "mode range = t16 V
Sensitivity 20 mV
Level Detector with Hysteresis
=
100kn
High Speed 3·Bit AID Converter
j
IN
Msa
Q.7SV
Zero Crossing Detector (Note 2)
R3
Icon
V+
FD888
IN
5.0k
1.2SV
-_--I . . .;.,..--I)I-.....
-~f_....._+.:.j ~......- - - OUT
R4
loon
~.::...-.....-OUT
1.7SV
so
RS
loon
2.25 V
Total delay = 30 ns
= 300 Hz to 3.0 MHz
Minimum input voltage = 20 mVp-p
R6
Input frequency
loon
""""OF
Not. .
2.75 V
1. Lead numbers shown are for Metal Package only.
2. All resistor values in ohms.
loon
R7
3.25 V
son
R8
350n
+5.0 V
Input voltage range = 3.5 V
Typical conversion speed = 30 ns
CFlO2..aoF
8-62
MA1488
FAIRCHILO
RS-232C
Quad Line Driver
A Schlumberger Company
Linear Division Interface Products
Description
Connection Diagram
14-Lead DIP and 50-14 Package
(Top View)
The /JA 1488 is an EIA RS-232C specified quad line driver.
This device is used to interface data terminals with data
communications equipment. The /JA 1488 is a lead-for -lead
replacement of the MC1488.
v•
•
•
•
Current Limited Output - ± 10 rnA Typical
Power-Off Source Impedance 300
Minimum
Simple Slew Rate Control With External CapaCitor
Flexible Operating Supply Range
n
IN 01
OUT A
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP and SO-14
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP and SO-14
(soldering, 10 s)
Internal Power Dissipation " 2
14L-Ceramic DIP
14L-Molded DIP
SO-14
Supply Voltage
Input Voltage Range
Output Signal Voltage
v+
IN A
IN 02
IN81
OUTO
INB2
INC'
OUTB
-65°C to + 175°C
-65°C to + 150°C
O°C to +70°C
INC2
GND
OUTC
Order Information
Device Code
Package Code
Package Description
6A
9A
KD
Ceramic DIP
Molded DIP
Molded Surface Mount
/JA1488DC
/JA1488PC
/JA1488SC
1.36 W
1.04 W
0.93 W
± 15 V
-15V to +7.0V
± 15 V
Note
1. TJ Max ~ 175°C for the Ceramic DIP, and 150°C for the Molded DIP and
50-14.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 14L-Ceramic DIP at 9.1 mW 1°C, the 14L-Molded DIP at
8.3 mwrc, and the 50·14 at 7.5 mW/oC.
Equivalent Circuit (1/4 of Circuit)
v+----~----------~----~----.
05
R5
300n
+---_+--.-'VV',,--OUT
07
09
GNO~
R8
v---------~~
__ ________
~
9-3
70 !l
~~
JJ.A1488
~A1488
Electrical Characteristics
DC Characteristics Vee = ± 9.0 V ± 1 %, TA = O°C to 70°C, unless otherwise specified.
Symbol
Characteristic
Condition
Figure
IlL
Input Current LOW
VIL = 0 V
1
IIH
Input Current HIGH
VIH = 5.0 V
1
VOH
Output Voltage HIGH
VIL = 0.8 V, RL = 3.0 kn
Vee = ±9.0 V
2
Min
1.0
6.0
7.0
9.0
10.5
-6.0
-7.0
VIL = 0.8 V, RL = 3.0 kn
Vee=±13.2 V
VOL
Output Voltage LOW
VIH = 1.9 V, RL = 3.0 kn
Vee = ±9.0 V
2
VIH = 1.9 V, RL = 3.0 kn
Vee=±13.2 V
Typ
Max
Unit
1.6
mA
10
p.A
V
V
-9.0 -10.5
los+
Positive Output Short Circuit Current 1
VIL = 0.8 V
3
-6.0
-10
-12
mA
los-
Negative Output Short Circuit Current 1
VIH = 1.9 V
3
+6.0
+10
+12
mA
Ro
Output Resistance
Vee = 0 V, Va = ± 2.0 V
4
300
1+
Positive Supply Current
RL = 00
VIH = 1.9 V, V+ = 9.0 V
5
VIL = 0.8 V, V+ = 9.0 V
1-
Negative Supply Current
n
mA
15
20
4.5
6.0
VIH=1.9 V, V+ =12 V
19
25
VIL =0.8 V, V+ = 12 V
5.5
7.0
VIH=1.9 V, V+ =15 V
34
VIL = 0.8 V, V+ = 15 V
12
RL = 00
VIH = 1.9 V, V - = -9.0 V
5
-13
VIL = 0.8 V, V - = -9.0 V
VIH = 1.9 V, V - = -12 V
Pe
Power Consumption
-18
-17
mA
-15
p.A
-23
mA
VIL=0.8 V, V- =-12 V
-15
p.A
VIH=1.9 V, V- =-15 V
-34
mA
VIL = 0.8 V, V - = -15 V
-2.5
mA
Vee=±9.0 V
333
mW
Vee=±12 V
576
AC Characteristics Vee = ± 9.0 V ± 1 %, T A = 25°C
Symbol
tpLH
Characteristic
Propagation Delay Time
Condition
RL = 3.0 kn, CL = 15 pF
Figure
6
tpHL
t,
Fall Time
t,
Rise Time
RL = 3.0 kn, CL = 15 pF
Note
1. Maximum package power dissipation may be exceeded if all outputs are shorted simultaneously.
9-4
6
Min
Typ
Max
Unit
220
350
ns
70
175
ns
70
75
ns
55
100
ns
IlA1488
Typical Performance Curves
Transfer Characteristics vs
Supply Voltage
12
>
I
6.0
w
~"
~
vcci
Output Voltage and Current Limiting
Characteristics
20
I
12 v
rr- Vee +9V
r- VCr"16V
+
~
I
....
~
12
I\- t-\
4.0
!z
~
~\
---
\ 1\~ \.o"o.J::'.~}-
:J
>
r-- r---..
1\
a:
a:
0
....
(,)
't~
:J
1=:J
0
-6.0
-12
~
I
I
I
I
0.8
0.4
-4.0
o~
3 kH
o
1.9
-12
I
-20
1.2
1.•
2.0
,.
'l.
"
v
Vcc=±9V
-aD
-:-
r--
,.
1\
i\
100
\
w
a:
;0
~
II.
'"
10
4.0
v'--Dyvo1\1\
I
V-
-25
75
TEMPERATURE _
<>
c
125
1.0
1.0
10
CL
100
CAPACITANCE -
9-5
1\
1000
pF
~
~
~
6.0 1--+-+--V++-~-+-f9-.0-V+-+--I---l
v,'·~V _ ~_
o.~
V-=-9.oV
~-aor---f-+-+--I--+--f--I--1
!5
e:
:J
o
TEMPERATURE _
t(
8.0
0
-75
\
~
8 .•
I
!i
II.
iil
0.8
12
I
w
>
-=
los
Output Slew Rate vs
Load Capacitance
1000
0
"\..
OUTPUT VOLTAGE - V
Supply Voltage vs Maximum
Operating Temperature
"~
\
V
v,
INPUT VOLTAGE-V
>
Short Circuit Output Current vs
Temperature
10,000
0
c
I1A1488
DC Test Circuits
Figure 1 Input Current
Figure 4 Output Resistance (Power-off)
+ 9 V -9 V
14
10
12
13
10
III
t
it
1
I'H
+5V
Figure 5 Supply Currents
V+
Figure 2 Output Voltage
v+
y-
1.9 V
~
1.9 V
14
lVIH
v,Hb
3 kll
12
12
~
O.BV
O.BV
V-
Figure 6 AC Test Circuit and Voltage Waveforms
Figure 3 Output Short Circuit Current
+9V
V, -O-}-3.'-'-r,----vo
r
-9V
14
'SPF
-=-
-=-
~
~ ~~
12
CL
RL
+3.0V+l'SV
v,
11
~
tPHL
--.
O.BV
V o - - -....
-
~-----OV
' -_ _ _r - - - I ,
tr and tf are measured 10% to 90%
9-6
p.A 1489 • p.A 1489A
RS-232C
Quad Line Receivers
FAIRCHILO
A Schlumberger Company
Linear Division Interface Products
Description
Connection Diagram
14-Lead DIP and 50-14 Package
(Top View)
The /lA 1489 and the /lA 1489A are EIA RS-232C specified
quad line receivers. These devices are used to interface
data terminals with data communications equipment. The
/lA 1489 and /lA 1489A are lead-for-Iead replacements of
the MC1489 and MC1489A respectively.
•
•
•
•
INA
RESPONSE
CONTROL A
Input Resistance 3.0 kS1 To 7.0 kS1
Input Signal Range ± 30 V
Input Threshold HystereSiS Built-In
Response Control
a) Logic Threshold Shifting
b) Input Noise Filtering
RESPONSE
CONTROL D
OUT A
IN B
RESPONSE
CONTROL B
RESPONSE
CONTROL C
OUTS
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP and 80-14
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP and SO-14
(soldering, 10 s)
Internal Power Dissipation 1. 2
14L-Ceramic DIP
14L-Molded DIP
SO-14
Supply Voltage
Input Voltage Range
Output Load Current
IND
12
GND
OUTC
-65°C to + 175°C
-65°C to + 150°C
O°C to +70°C
Order Information
300°C
Device Code
Package Code
Package Description
6A
9A
KD
6A
9A
Ceramic DIP
Molded DIP
Molded Surface Mount
Ceramic DIP
Molded DIP
J.LA1489DC
/lA1489PC
/lA 1489SC
/lA 1489ADC
/lA1489APC
265°C
1.36 W
1.04 W
0.93 W
10 V
±30 V
20 mA
Note
1. TJ Ma, ~ 175·C for the Ceramic DIP. and 150·C for the Molded DIP and
50·14.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 14L-Ceramic DIP at 9.1 mW/·C. the 14L-Molded DIP at
8.3
and the 50-14 at 7.5
mwrc.
mwrc.
Equivalent Circuit (1/4 of circuit)
, - - - _ -....-vcc
9 kll
5 kll
1.6 kll
OUT
3.55 kll
L--~~---~~~~-~--GND
9-7
•
IlA 1489 • IlA 1489A
~1489, ~1489A
Electrical Characteristics
DC Characteristics Vee = 5.0 V ± 1.0%, response control lead is open, TA = O·C to 70·C, unless otherwise specified.
Symbol
Characteristic
IIH
Input Current HIGH
IlL
Input Current LOW
Condition
VIH = 25 V
Figure
3.6
1
-3.6
VIL = -25 V
VOH
Input Turn-on Threshold
Voltage
TA = 25·C,
VOL <0.45 V
j.LA1489
Input Turn-off Threshold
Voltage
TA = 25·C,
VOH ;;;'2.5 V,
10H =-0.5 mA
j.tA1489
Output Voltage HIGH
Max
Unit
8.3
mA
-8.3
mA
-0.43
VIL = -3.0 V
VTH-
Typ
0.43
VIH = 3.0 V
VTH+
Min
1
2
j.tA1489A
2
j.LA1489A
VIH = 0.75 V, 10H = -0.5 mA
1.0
1.75
1.5
1.95
0.75
1.25
0.75
0.8
1.25
2.6
4.0
5.0
2
0.2
0.45
3
3.0
2
V
2.25
V
V
Input Open Circuit, 10H = -0.5 mA
VOL
Output Voltage LOW
los
Output Short Circuit Current
lee
Supply Current
VIH = 5.0 V
4
20
26
mA
Pe
Power Consumption
VIH = 5.0 V
4
100
130
mW
VIL = 3.0 V, 10L = 10 mA
V
mA
AC Characteristics Vee = 5.0 V ± 1.0%, TA = 25·C
Symbol
tpLH
Condition
Characteristic
Propagation Delay Time
tpHL
t,
Rise Time
t/
Fall Time
kn
RL = 390 n
RL = 3.9 kn
RL =390 n
RL = 3.9
9-8
Figure
Min
Typ
5
25
5
10
Max
Unit
85
ns
25
50
ns
120
175
ns
20
ns
Typical Performance Curves
6.0
V
I
Ii
2.0
w
/'
a;
a;
::I
.."
I-
V
/'
-2.0
/'
!!O
"~
g
1.6
90
1.2
-
-5.0
3.0
~
0
15
5.0
..
I-
::I
::I
0
2.0
1.0
r-
-1.0
-3.0
_~T
VJlI1
:!l
a;
-60
~A1489
,.,41489
",A1489A
I-
~
i!!
I
I
o
r---- V,lH f.I
:t
I
OA
V,HL
1.0
:t
o
120
.0
°c
o
4.0
8.0
SUPPLY VOLTAGE -
-=- VTH
8.0
RT = 5.0 kn
YTH=5.0Y
3.0
6.0
RT = 11 kO
VTH",,-5.0Y
[/RT""
•
5.0
>
I
4.0
w
"~
3.0
0
>
I-
::I
2.0
YIH~--
~
::I
0
1.0
.A1
V,LHI
=11 kO
INPUT VOLTAGE - V
--'"
-
-1.0
-3.0
~
...
6.0
3.0
INPUT VOLTAGE -
V
Test Circuits
Figure
Input Current
Figure 2 Output Voltage and Input Threshold Voltage
+ 5.0 V
V,
12
V
/.LA 1489A Input Threshold
Voltage Adjustment
1....
'-/r-III
13k:'
VTi =5.i V
i""C"Y I 1 I
RT =
~HL
TEMPERATURE _
RT
V,HL
~
0
I-
90
;-
25
Y
~V'i'"
w
>
0
>
.uA 1489A
lr" I I I
RT - 5.0 kn
VTH = 5.0 V
"~
w
"~
a;
!!O
/.lA1489 Input Threshold
Voltage Adjustment
4.0
I
-I"'-
lI-
INPUT VOLTAGE - V
>
I
>
/J.Al489 V'LH
..
Y
-15
5.0
V'HL pA1489A
1'.....'''',4B9.q ~"
::I
V,
6.0
6.0
I I I
:t 0.8
,/
-10
-25
I
w
2.D
.,:tw
./
::I
>
2.0
-
2.4
10
C
E
Input Threshold Voltage vs
Supply Voltage
Input Threshold Voltage vs
Temperature
Input Current vs Input Voltage
VIHL
I
14
V,LH
V,HlO
OPEN 0
V,LH + 5.0 V
- 5.0 V
14
10
12
10
L...----'.:,:3t._..,.,,_J"
12
13
9-9
11
JlA 1489 • JlA 1489A
Test Circuits (Cent.)
Figure 4 Supply Current
Figure 3 Output Short Circuit Current
Vee
Vee
ICC
14
14
--lOS
10
10
12
12
13
11
13
11
Figure 5 AC Test Circuit and Voltage Waveforms
T
5.0 V
~:OV
1\0%
~I '--~--tP-LH-(NOTE
»---4----~~------Vo
V,
Figure 6 Response Control Node
R (NOTE 5)
RESPONSE NODE
Vo
V,
1/4 J,lA1489A
Notes
1. All diodes FDSOO or equivalent.
2. CT ~ 15 pF ~ total parasitic capacitance,
which includes probe and jig capacitance.
3, tr and tf measured 10% to 90%.
4. Capacitor is for noise filtering.
5. Resistor is for threshold shifting.
9-10
3)
JJ.A26LS31
Quad High Speed
Differential Line Driver
F=AIRCHILO
A Schlumberger Company
Linear Division Interface Products
Description
Connection Diagram
16-Lead DIP
(Top View)
The I.lA26LS31 is a quad differential line driver designed
for digital data transmission over balanced lines. The
1.lA26LS31 meets all the requirements of EIA Standard
RS-422 and Federal Standard 1020. It is designed to provide unipolar differential drive to twisted-pair or parallel-wire
transmission lines.
The circuit provides an enable and disable function common to all four drivers. The 1.lA26LS31 features three-state
outputs and logical OR-ed complementary enable inputs.
The inputs are all LS compatible and are all one unit
load.
OUTAi
INO
OUTA2
OUTD1
ENABLE
OUT02
OUTB2
ENABLE
OUTBi
OUTC2
INB
OUTC1
The I.lA26LS31 offers optimum performance when used
with the 1.lA26LS32 Quad Differential Line Receiver.
•
•
•
•
•
•
•
•
•
•
Output Skew - 2_0 ns Typical
Input To Output Delay - 12 ns
Operation From Single + 5_0 V Supply
16-Lead Ceramic And Molded DIP Package
Outputs Won't Load Line When Vcc = 0 V
Four Line Drivers In One Package For Maximum
Package Density
Output Short Circuit Protection
Complementary Outputs
Meets The Requirements Of EIA Standard RS-422
High Output Drive Capability For 100
Terminated
Transmission Lines
GND
INC
Order Information
n
Device Code
Package Code
I.lA26LS31DC
I.lA26LS31PC
78
98
Package Description
Ceramic DIP
Molded DIP
Function Table (Each Driver)
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1,2
16L-Ceramic DIP
16L-Molded DIP
Supply Voltage3
Input Voltage
Output Voltage
+s.ov
INA
Outputs
-65°C to + 175°C
-65°C to + 150°C
O°C to +70°C
Input
Enable
y
Z
H
L
H
H
L
H
L
L
H
Z
Z
X
H = High level
l= low level
X = Immaterial
Z = High Impedance (off)
1.50 W
1.04 W
7.0 V
7.0 V
5.5 V
Logic Symbol
Notes
1. TJ Max = 150'C for the Molded DIP, and 175'C for the Ceramic DIP.
2. Ratings apply to ambient temperatures at 25'C. Above this temperature,
derate the 16l-Ceramic DIP at 10 mWI'C, and the 16l-Molded DIP at
8.3 mWI'C.
3. All voltages are with respect to network ground terminals.
GND
Vee
D2
D1
C2
C1
B2
OUTPUTS
9-11
81
A2
Ai
J,lA26LS31
J.lA26LS31
Electrical Characteristics
Symbol
ooe < TA < 70 oe,
4.75 V < Vee < 5.25 V, unless otherwise specificied.
Characteristic
Condition
Typl
2.5
3.2
Max
Unit
V
Output Voltage HIGH
Vee = Min, IOH =-20 rnA
VOL
Output Voltage LOW
Vee = Min, 10L = 20 rnA
V,H
Input Voltage HIGH
Vee = Min
V,L
Input Voltage LOW
Vee = Max
I,L
Input Current LOW
Vee = Max, V, = 0.4 V
I'H
Input Current HIGH
Vee = Max, V, = 2.7 V
0.5
20
IlA
I'R
Input Reverse Current
Vee = Max, V, = 7.0 V
0.001
0.1
rnA
loz
Off State (High Impedance)
Output Current
Vee = Max
IVo=2.5 V
0.5
20
I1A
IVo=0.5 V
0.5
-20
V'c
Input Clamp Voltage
Vee = Min, I, = -18 rnA
los
Output Short Circuit
Vee = Max
0.32
0.5
0.8
-0.20
-30
V
V
2.0
-0.36
V
rnA
-0.8
-1.5
V
-60
-150
rnA
Icc
Supply Current
Vee = Max, All Outputs Disabled
60
80
rnA
IplH
Input 10 Output
Vee = 5.0 V, TA = 25°C,
Load = Note 2
12
20
ns
tpHL
Input 10 Output
Vee = 5.0 V, TA = 25°C,
Load = Note 2
12
20
ns
SKEW
Output to Output
Vee = 5.0 V, TA = 25°C,
Load = Note 2
2.0
6.0
ns
tLZ
Enable to Output
Vee = 5.0 V, TA = 25°C,
CL = 10 pF
23
35
ns
tHZ
Enable to Output
Vee = 5.0 V, TA = 25°C,
CL = 10 pF
17
30
ns
tZl
Enable to Output
Vee = 5.0 V, TA = 25°C,
Load = Note 2
35
45
ns
tZH
Enable to Output
Vee = 5.0 V, TA = 25°C,
Load = Note 2
30
40
ns
Noles
1.
2.
Min
VOH
All typical values are Vee = 5.0 V, TA = 25"e
eL = 30 pF, V, = 1.3 V to Vo = 1.3 V, VPULSE
load Test Circuit for Three-State Outputs)
= 0 V to +3.0 V (See Ae
9-12
MA26LS31
AC Load Test Circuit for Three-State Outputs
TEST
POINT
FROM OUTPUT
UNDER TEST
Propagation Delay (Notes 1 and 3)
Vee
INPUT
TRANSmON
___-r~--r---~7'St,~
t~n I
Rt
750
OUT
Enable and Disable Times (Notes 2 and 3)
Enable
Disable
3V
ENABLE
INPUT
•
OV
OUTPUT
NORMALLY
LOW
~t.5V
OUTPUT
NORMALLY
HIGH
~t.5V
Notes
1. Diagram shown for Enable Low. Switches S1 and S2 open.
2. S1 and S2 of Load Circuit are closed except where shown.
3. Pulse Generator for all Pulses: Rate < 1.0 MHz, 20 = 50 n,
tr ~6.0 ns, tf <6.0 ns.
4. CL includes probe and jig capacitance.
Typical Application
DATA
IN
RT
SHIELD OR COMMON GROUND RETURN
9-13
DATA
OUT
J,LA26LS32
Quad Differential
Line Receiver
FAIRCHILO
A Schlumberger Company
Linear Division Interface Products
Description
Connection Diagram
16-Lead DIP (Top View)
The !lA26LS32 is a quad differential line receiver designed
to meet the requirements of EIA Standards RS-422 and
RS-423, and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission.
1
The device features an input sensitivity of 200 mV over
the input range of ± 7.0 V. The MA26LS32 provides an
enable function common to all four receivers and threestate outputs with 8.0 mA sink capability. Also, a fail-safe
input/ output relationship keeps the outputs high when the
inputs are open.
-INA
Vec
+INA
-INB
OUTA
+INB
OUTC
The !lA26LS32 offers optimum performance when used
with the !lA26LS31 Quad Differential Line Driver.
• Input Voltage Range Of ± 7.0 V (Differential Or
Common Mode) ± 0.2 V Sensitivity Over The Input
Voltage Range
• Meets All The Requirements Of EIA Standards
RS-422 And RS-423
• Input Impedance (15K Typical)
• 30 mV Input Hysteresis
• Operation From Single + 5.0 V Supply
• Fail-Safe Input/Output Relationship. Output Always
High When Inputs Are Open.
• Three-State Drive, With Choice Of Complementary
Output Enables, For Receiving Directly Onto A Data
Bus.
• Propagation Delay 17 ns Typical
• Advanced Low Power Schottky processing
• 100% Reliability Assurance Screening To
MIL-STD-883 Requirements.
8.3
mwrc.
mwrc,
OUTO
-INC
+IND
GNO
-INO
Device Code
Package Code
!lA26LS32DC
MA26LS32PC
7B
9B
Package Description
Ceramic DIP
Molded DIP
Function Table (Each Receiver)
Differential Inputs
E
V
VID;;;.oO.2 V
H
X
H
H
< 0.2
V
X
X
L
H
X
X
L
H
X
X
L
L
L
H
Z
L
H ~ High Level
L ~ Low Level
300°C
265°C
Outputs
E
VID<-0.2 V
-6SOC to + 175°C
-6SoC to + 150°C
O°C to +70°C
Enables
A-B
-0.2 V < VID
x
?
?
= Immaterial
X ~ High Impedance (off)
? = Indeterminate
Logic Symbol
1.S0 W
1.04 W
7.0 V
±25 V
±25 V
7.0 V
SO mA
INPUTS
ENiiLE
ENABLE
" D2
01
C2
C1
82
81
A2
41
~,c1c1c1rY
Notes
1. TJ Max~ 150"C for the Molded DIP, and 175"C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 16L·Ceramic DIP at 10
+INC
Order Information
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 5)
Internal Power Dissipation 1, 2
16L-Ceramic DIP
16L-Molded DIP
Supply Voltage 3
Common Mode Voltage Range
Differential Input Voltage
Enable Voltage
Output Sink Current
OUTB
ENABLE
GND
and the 16L·Molded DIP at
3. All voltages are with respect to network ground terminal.
9-14
Vee
OUTPUT
OUTPUT
o
C
OUTPUT
8
OUTPUT
A
J-lA26 LS32
IlA26 LS32
Electrical Characteristics
Symbol
ooe
«
TA
«
70 oe, 4.75 V
«
Characteristic
«
Vee
5.25 V, unless otherwise specified.
Conditions
Min
Typ
Max
Units
-0.2
±0.06
+0.2
V
VTH
Differential Input Voltage
-7.0 V0.2 V
H
H
H
?
-0.2 V
< VIO < 0.2
Vlo<-0.2 V
H
L
X
L
Z
H = High Level
L = Low Level
? = Indeterminate
X = Immaterial
Z = High Impedance (off)
Noles
1. TJ Max ~ 150°C for the Molded DIP, and 175°C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 16L-Ceramic OIP at 10 mwrc. and the 16L-Malded DIP at
8.3 mwrc.
3. All voltages are with respect to network ground terminal.
9-17
V
J,lA3486
Block Diagram
DIFFERENTIAL
INPUTS
THREE-STATE
CONTROL
INPUT
OllTPUT
Y
Recommended Operating Conditions
Symbol
Value
Unit
Vee
Supply Voltage
Characteristic
4_75 to 5.25
V
VeM
Input Common Mode Voltage Range
-7.0 to +7.0
V
VIO
Input Differential Voltage Range
6.0
V
TA
Operating Temperature
o to
+70
°C
1-lA3486
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, unless
otherwise specified.
Symbol
Characteristic
Condition
VIH
Input Voltage HIGH
VIL
Input Voltage LOW
Three-State Control
VTH(O)
Differential Input Threshold Voltage 5
-7.0 V~Vle~7.0 V,
VIH =2.0 V
Min
Three-State Control
10 =-0.4 mA,
VOH;;;'2.7 V
10=8.0 mA,
VOL ~0.5 V
liS
Input Bias Current
HIGH 4
VOH
Output Voltage
VOL
Output Voltage LOW
Vee=O V or 5.25 V,
Other inputs at 0 V
Max
V
0.8
V
0.2
V
-3.25
VI =-3.0 V
-1.50
VI = +3.0 V
+1.50
VI = +10 V
+3.25
10 = 8.0 mA,
VIO= 0.4 V
Unit
-0.2
VI =-10 V
-7.0 V~VeM~7.0 V, 10 =-0.4 mA,
VIH =2.0 V
VIO = 0.4 V
9-18
Typ1
2.0
2.7
mA
V
0.5
I1A3486
j.lA3486 (Cont.)
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, unless
otherwise specified.
Symbol
loz
Characteristic
Output Third State Leakage Current
Condition
Min
Typt
Max
VI(D) = + 3.0 V, VIL = 0.8 V,
Vo = 0.5 V
-40
V'(D) = -3.0 V, VIL = 0.8 V,
Vo=2.7 V
40
los
Output Short Circuit Current3
V'(D) = 3.0 V, VIH= 2.0 V,
Vo=O V
I,L
Input Current LOW
Three-State Control VIL = 0.5 V
I'H
Input Current HIGH
-15
Unit
J,lA
-100
mA
-100
I1A
I1A
Three-State Control VIH = 2.7 V
Three-State Control V,H = 5.25 V
20
100
-1.5
VIC
Input Clamp Diode Voltage
(Three-State Control)
Three-State Control Ilc=-10mA
Icc
Supply Current
VIL = 0 V
V
85
mA
Typt
Max
Unit
Switching Characteristics Vcc = 5.0 V, TA = 25°C
Symbol
Characteristic
Propagation Delay Time
Differential
Condition
Min
Inputs to Outputs
tpHL(D)
Output HIGH to LOW
16
35
ns
tpLH(D)
Output LOW to HIGH
16
30
ns
tpLZ
Control to Output
Output LOW to Third State
24
35
ns
tpHZ
Output HIGH to Third State
16
35
ns
tpZH
Output Third State to HIGH
16
30
ns
tPZL
Output Third State to LOW
16
30
ns
Propagation Delay Time
Notes
1. All currents into device leads are shown as positive, out of device leads
are negative. All voltages referenced to ground unless otherwise noted.
2. Typical values are TA ~ 25°C, Vcc ~ 5.0 V. and V'c ~ 0 V.
3. Only one output at a time should be shorted.
4. Refer to EtA RS-422/3 for exact conditions. Input balance and VOH/VOL
levels are tested Simultaneously for worst case.
5. Differential input threshold voltage and guaranteed output levels are
tested simultaneously for worst case.
9-19
J,lA3486
Parameter Measurement Information
Figure 1 Propagation Delay Differential Input to Output
TO SCOPE
(INPUT)
TOSCOPE
(OUTPUT)
INPUT~.SV
1.SV
3.0V
ov
tPLH(~~H
tpLH(:F_ €)
PULSE
GENERATOR
(Note 1)
I
+1.5V
OUTPUT
CL =15 PF
1.3V
1.3V
VOL
-------------------OV
(N..,2)
+2.0V
Figure 2 Propagation Delay Three-State Control Input to Output
TO SCOPE
(INPUT)
3-STATE
CONTROL
TO SCOPE
(OUTPUT)
PULSE
GENERATOR
(NolO 1)
SW1
2.OkO
o--+S.OV
DIFFERENTIAL
INPUTS
CL=1SpF
(N..,2)
I
5.0kO
3.0V
3.0V
IN
_____J_-,-___
' - - - - - - ' - - - - - OV
OV
SW1CLOSED
~
SW2 CLOSED
--~1.3V
OUT
O.SV
VOL
OV
~
HSW2CLOSED
~
'PZH
IN
1.SV
'PZL
3.0V
1.SV
- - - - - OV
SW10PEN
CLOSED
ZLSW2 OPEN
VOH
OUT
3.0V
IN~'SV
--tipS~~
1.SV
OUT
1.SV
---OV
/
--'
\.SV
~5.0V-V.E
VOL
- - - - - - - - - - - - - - - - - - - OV
Notes
1. The input pulse is supplied by a generator having the following
characteristics: PRR = 1.0 MHz, 50% duty cycle, tTLH = tTHL = 6.0 ns
(10% to 90%), Zo = 50 n.
2. CL includes probe and jig cpacitance.
3. All diodes are IN916 or equivalent.
9-20
MA3487
FAIRCHILD
RS-422 Quad Line Driver
With Three-State Outputs
A Schlumberger Company
linear Division Interface Products
Connection Diagram
16-Lead DIP
(Top View)
Description
Fairchild's RS-422 Quad line Driver features four independent driver chains which comply with EIA Standards for
the electrical characteristics of balanced voltages digital interface circuits. The outputs are three-state structures
which are forced to a high impedance state when the appropriate output control lead reaches a logic zero condition. All input leads are PNP buffered to minimize input
loading for either logic one or logic zero inputs. In addition, internal circuitry assures a high impedance output
state during the transition between power-up and powerdown.
•
•
•
•
•
•
•
•
A/B
CONTROL
C/O
CONTROL
Four Independent Driver Chains
Three-State Outputs
PNP High Impedance Inputs
Fast Propagation Time
TTL Compatible
Single 5.0 V Supply Voltage
Output Rise And Falls Times Less Than 20 ns
Lead Compatible And Interchangeable With MC3487
And DS3487
COOO451F
Order Information
Device Code
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1,2
16L-Ceramic DIP
16L-Plastic DIP
Supply Voltage 3
Input Voltage
Package Code
!lA3487DC
IlA3487PC
78
98
Package Description
Ceramic DIP
Molded DIP
-65°C to +175°C
-65°C to + 150°C
O°C to +70°C
Function Table (Each Driver)
300°C
265°C
Outputs
1.50 W
1.04 W
8.0 V
5.5 V
Input
Enable
y
Z
H
L
X
H
H
L
H
L
L
H
Z
Z
H = High Level
L= Low Level
X = Immaterial
Z = High Impedance (off)
Notes
1. TJ Max = 150"C for the Molded DIP. and 175"C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 25"C. Above this temperature,
derate the 16L·Ceramic DIP at 10 mWrC, and the 16L·Molded DIP at
8.3 mWrC.
3. All voltages are with respect to network ground terminal.
9-21
tlA3487
Block Diagram
NON·INVERTING
INPlIT
OllTPUTS
INVERTING
/.lA3487
Electrical Characteristics 4.75 V .;;; Vee';;; 5.25 V, TA = DoC to 70°C, unless otherwise specified.
Symbol
V,L
Characteristic
Condition
Min
Input Voltage LOW
Typ1
Max
Unit
0.8
V
J.IA
J.IA
V,H
Input Voltage HIGH
I'L
Input Current LOW
V,L = 0.5 V
-400
I'H
Input Current HIGH
V,H = 2.7 V
+50
V,H = 5.5 V
+ 100
V,C
Input Clamp Voltage
1,=-18mA
-1.5
V
VOL
Output Voltage LOW
10L =48 mA
0.5
V
VOH
Output Voltage HIGH
10H =-20 mA
2.5
los
Output Short Circuit Current3
V,H = 2.0 V
-40
loz
Output Leakage Current Hi·Z State
10L(off)
V
V
-140
mA
V,L = 0.5 V, V,L (z) = 0.8 V
+100
J1.A
V,H = 2.7 V, C'L (z) = 0.8 V
+100
Output Leakage Current
VOH=6.0 V, Vee=O V
+ 100
Power Off
VOL = -0.25 V, Vee = 0 V
-100
Vos·Vos
Output Offset
Voltage Difference 2
Voo
Output Differential Voltage 2
tNoo
Output Differential
Voltage Change
leex
Supply Current4
Icc
2.0
±OA
2.0
Control Leads Gnd
Control Leads 2.0 V
9·22
J.IA
V
V
±OA
V
105
mA
85
mA
MA3487
IlA3487 (Cont.)
Electrical Characteristics
Switching Characteristics Vee
= 5.0
V, TA
= 25°C
Max
Unit
Propagation Delay Times
High to Low Input
20
ns
Low to High Input
20
ns
Output Transition
Times - Differential
High to Low Input
20
ns
Low to High Input
20
ns
Propagation Delay
Control to Output
RL
Symbol
Characteristic
tpHL
Condition
tpLH
tTHL
tTLH
Typ
CL = 50 pF
25
ns
RL = 200, CL = 50 pF
25
ns
tpZH(E)
RL = 00, CL = 50 pF
30
ns
tpZL(E)
RL
30
ns
tpHZ(E)
tpLZ(E)
= 200,
Min
= 200,
CL
= 50
pF
Notes
1. Typical values are TA~25'e, Vcc~5.0 V
2. See EIA Specification RS-422 for exact test conditions
3. Only one output may be shorted at a time
4. Circuit in three-state condition
Parameter Measurement Information
Figure 1 Three-State Enable Test Circuit and Waveforms
TO SCOPE 3.0V or GND
IN
INPUT
TO SCOPE
OUT
OPEN FOR
INVERTING
OUTPUT
tPZH(E)
TEST ONLY
2000
NON-INVERTING
OUTPUT
CONTROL
~~~~ATOR
...n..
o---.I'>N-- +5Y
r
CL =5O PF
(Note 2)
-=-1.OkO
500
OPEN FOR
tpZl.(E)
(Note I)
TEST ONLY
CR00961F
~'5V
CONTROL
INPUT
'PHZ(E)
OUT
OUT
~v
-~
aov
3.0V
CONTROL
INPUT
1,.5V
OY
tPZl.(E)-
VOH
IpZH(E)~1.5V
OUT
VOL
OV
OV
VOH
'\ 1.5V
OUT
¢.
I
I-
~
:!:
L!J 1
-4.0 f--+-I7'7*,~"77'*,~"---+---l
INPUT -
9-27
H
Lor H H
w
The input protection diodes are useful in certain party-line
systems which may have multiple V + power supplies and,
in which case, may be operated with some of the V +
supplies turned off. In such a system, if a supply is turned
off and allowed to go to ground, the equivalent input circuit connected to that supply would be as follows:
Indeterminate
L
-------+---------'
>
H
L
Recommended Combinations of
Input Voltage for Line Receivers
+IN
Output
Lor H Lor H H
< VIO < 25
B Version
-IN
S
G
A-B
Vlo;;;'25 mV
B-TO-GROUND VOLTAGE - V
L
•
~A55107A· ~A75107A
~A75107B· ~A75108B
pA55107A, pA75107A, pA75107B
Electrical Characteristics Over recommended operatin~ temperature range with V+ = Max and V- = Max,
unless otherwise specified. 1,
DC Characteristics
Symbol
Characteristic
Min
Condition
IIH
Input Current HIGH
VOIFF = 0.5 V, VCM = -3.0 V to +3.0 V
IlL
Input Current LOW
VOIFF = -2.0 V, VCM = -3.0 V to +3.0 V
IIH(G)
Gate Input Current HIGH
Typ
30
Max
Unit
75
IlA
-10
/lA
V(G) =2.4 V
40
IlA
V(G) = V+
1.0
mA
-1.6
mA
IIL(G)
Gate Input Current LOW
V(G) = 0.4 V
IIH(ST)
Strobe Input Current HIGH
V(ST) = 2.4 V
80
/lA
V(ST) =V+
2.0
mA
-3.2
mA
IIL(ST)
Strobe Input Current LOW
VOH
Output Voltage HIGH
10H = -400 /lA,
VCM = -3.0 V to +3.0 V
Vcc= Min
VOL
Output Voltage LOW
10L = 16 mA,
VCM = -3.0 V to +3.0 V
Vcc= Min
los
Output Short Circuit Current2
Vo=O V
1+
Positive Supply Current
Vo = VOH, 10H = 0 V, TA = 25°C
18
1-
Negative Supply Current
Vo = VOH, 10H = 0 V, TA = 25°C
-8.4
V(ST) = 0.4 V
2.4
V
0.4
V
-70
mA
30
mA
-15
mA
Typ
Max
Unit
17
25
ns
tpHL(O)
17
25
ns
tpLH(S)
10
15
ns
tpHL(S)
10
15
ns
AC Characteristics Vcc = ± 5.0 V, RL = 390
Symbol
tpLH(O)
n,
-18
CL = 50 pF, TA = 25°C. (See Test Circuit)
Characteristic
Condition
Min
Propagation Delay Time
J..IA75108B
DC Characteristics
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
IIH
Input Current HIGH
VOIFF = 0.5 V, VCM = -3.0 V to + 3.0 V
IlL
Input Current LOW
VOIFF = -2.0 V, VCM = -3.0 V to +3.0 V
IIH(G)
Gate Input Current HIGH
V(G) = 2.4 V
IIL(G)
Gate Input Current LOW
V(G) = 0.4 V
IIH(ST)
Strobe Input Current HIGH
V(ST) = 2.4 V
80
/lA
V(ST) = V+
2.0
mA
30
75
-10
40
V(G)=V+
9-28
/lA
/lA
/lA
1.0
mA
-1.6
mA
MA55107A· MA75107A
MA75107B· MA75108B
J..IA75108B (Cont.)
Electrical Characteristics Over recommended operatin~ temperature range with V+
unless otherwise specified. 1 ,
Symbol
Characteristic
Condition
= Max
and VTyp
Min
= Max,
Max
Unit
-3.2
mA
IIL(ST)
Strobe Input Current LOW
V(ST) = 0.4 V
VOL
Output Voltage LOW
IOL = 16 mA,
VeM =-3.0 V to +3.0 V
Vee = Min
0.4
V
IOH
Output Current HIGH
Vo=V+
Vce = Min
250
pA
1+
Positive Supply Current
VO=VOH' IOH = 0 V, TA = 25°C
18
30
mA
1-
Negative Supply Current
VO=VOH' IOH = 0 V, TA = 25°C
-8.4
-15
mA
AC Characteristics Vce = ± 5.0 V, RL = 390
Symbol
n,
CL = 15 pF, TA = 25°C. (See Test Circuit)
Characteristic
Min
Condition
Typ
tpLH(D)
Max
19
Propagation Delay Time
Unit
25
ns
tpHL(D)
19
25
ns
tpLH(S)
13
20
ns
tpHL(S)
13
20
ns
Notes
I. For ,.,A551 07A guaranteed supply voltage range is ± 4.5 V to ± 5.5 V
and operating temperature range is -55°C
I 4.0
~
g~
100
~7l1089
5.0
}lA7J,08B I
JNVER~ING
-
_I INiuTS
~
I
x
I
"
;:
~A55107A/B
I'A75107A/B
I-
a:
I I
"
~
o
- 40
",A75107A/B
~ ",A75108B+1
20
10
10
20
30
40
--- --!
~
~
1
~:~~:~:~B"I
0
I
20
~
IT
:.-15
..
.."
~
...........
25°C
DIFFERENTIAL INPUT VOLTAGE - mY
a:
a:
::>
40
o
30
20
Z
W
ii
N - 10
TA
..
I
l-
VcC"'-'-S.ov
1.0
I
I
~
I-
()
I
I
o
Vcc=..!:5.0V
25
80
~
3.0
2.0
30
YcC"'::5.0V
10N.I~VER~ING
~'NPu7
I-
~
High Logic Level
Supply Current vs
Ambient Temperature
Input Current HIGH
Into 1A or 2A vs
Ambient Temperature
Output Voltage vs
Differential Input Voltage
0
~
~
TEMPERATURE - °C
9-29
n
00
_
I
10
I
'i
75
100
5.0
o
75
-50
25
0
25
SO
TEMPERATURE _ °C
125
J.LA55107A· MA75107A
MA75107B· MA75108B
Typical Performance Curves (Cont.)
ILA55107A, !LA75107A/B Propagation
Delay Time (Differential Inputs) vs
Ambient Temperature
120
40
Vee
Vee =:t 5.0 v
~
w
l-
1(
iif
a
z
0
15
..
10
0
~A75107A/B
20 -.tPl.H(O)
!i
"if
100
30
25
RJ390L
~
~
I~ , / '
80
~
...-t
tPHL(DI
RLLJn
~
40
if
0
If
o
~
0
25
~
~
~
m
75
CL=50pF
30
~
if
0
If
I
J II---
25
50
75
,/'
"'~75108~.A
tPLH(S)
15
_p> k::
10 r--~~\..\S)
~
_
20
z
0
I
!i
15
..
10
"if
T
5.0
o
~
V
0
~"'(S)
II:
~
0
25
~
~
-
tpHllS)
5.0
,uA75107A/B
H
-~
100
125
m m
75
50
-25
25
----200mV
+IN~~
OUT
~
-4--tp
--+---+---5j""",1
,.........
I
I
Voltage Waveforms
STROBE OR
STROBE
COMMON
~ I>-
50
TEMPERATURE _ "C
_ _ _-OV
2--1
aov
VOL
9-30
!i
15
0
10
I
I-R!E:=:::::,
e3J"~
... ~A7S108B""1
I
~
l'
RL
Rl-- 1950 !!
25
50
TEMPERATURE -
o
TEMPERATURE _ "C
20
I
75
100
,
3900 11
5.0
25
~
,/
20
iif
a
z
I
If
30
w
30
25
I
Vee""..!: 5.0 V
CL ~ 15 pF
0
:IE
1=
25
z
0
./
HI-'"'
VCC=±5.0V
RL=390B
CL=15pF
35
:I
a
1(
40
VCC"'±S.ov
Rl=3900
35
~
~
!LA55107A, ILA75107A/B Propagation
Delay Time (Strobe Inputs) vs
Ambient Temperature
40
w
w
TEMPERATURE _ "C
!LA75108B Propagation
Delay Time (Strobe Inputs) vs
Ambient Temperature
w
V
f--
25
TEMPERATURE - <>C
1=
35
- -il
--
TI
50
40
~J5108l-l
20 r-RL l J n
5.0
~
II
60
Z
0
II:
~
= ± 5.0 V
CL=15pF
35 -RL=390U
CL=50pF
w
ILA75108B Propagation
Delay Time HIGH-to-LOW level vs
Ambient Temperature
!LA75108B Propagation Delay
Time LOW-to-HIGH Level vs
Ambient Temperature
125
75
"C
100
125
MA55107A· MA75107A
MA75107B • MA75108B
AC Test Circuit
OUTPUT
MA55107A
DIFFERENTIAL
INPUT
~A75107A/B
(NOTE 4)
390 II
-1
STROBE
COMMON STROBE B
$TROBEA
OUTPUT
751088
son
STROBE
INPUT
(NOTE 2)
-: (NOTE 3)
-:
V+=+5.0V
Notes
1. The pulse generators have the following characteristics:
t, ~ t, ~ 10 ± 5.0 ns, tPl ~ 500 ns, PRR ~ 1.0 MHz, tp2 ~ 1.0 p.s,
PRR ~ 500 kHz, Zo ~ 50 n.
2. Strobe input pulse is applied to Strobe A when inputs AI - A2 are being
tested; to common Strobe when inputs Al-A2 or Bl- 92 are being
tested; and to Strobe 9 when inputs Bl - B2 are being tested.
3. CL includes probe and jig capacitance.
4. All diodes are 1N916.
Basic Balanced-Line Transmission System
p
+
("ASSn5110A)
DATA
INPUT
INA1
(,.A55n5107A)
TWISTED-PAIR OR EQUIVALENT
TRANSMISSION LINE
Zo = 2 RT
'NA2
INHIBIT
INHA
INH COMMON
r
CL
STROBE
A
·1
9-31
RECEIVER
STROBE
COMMON
•
MA55107A· MA75107A
MA75107B· MA75108B
Data-Bus or Party-Line System
RT
DATA
INPUT
+
p
!
!
TWIsteD-PAIR LINE
P
STROBE
COMMON
RT
DRIVER 1
+
!
AT
AT
DRIVER 3
DRIVER 2
INAl
INA2
INHIBIT
INHA
INH
COMMON
Application
The J.tA55107A, J.tA75107A dual line circuits are designed
specifically for use in high speed data transmission systems that utilize balanced, terminated transmission lines
such as twisted-pair lines. The system operates in the balanced mode, so that noise induced on one line is also
induced on the other. The noise appears common mode
at the receiver input terminals where it is rejected. The
ground connection between the line driver and receiver is
not part of the signal circuit so that system performance
is not affected by circulating ground currents.
as 25 mV (or less). For normal line resistances, data may
be recovered from lines of several thousand feet in length.
Line termination resistors (RT) are required only at the extreme ends of the line. For short lines, termination resistors at the receiver only may prove adequate. The signal
amplitude will then be approximately:
VOIFF "'" 10(on) • RT
The strobe feature of the receivers and the inhibit feature
of the drivers allow the J.tA55107A, J.tA75107A dual line
circuits to be used in data-bus or party-line systems. In
these applications, several drivers and receivers may share
a common transmission line. An enabled driver transmits
data to all enabled receivers on the line while other drivers and receivers are disabled. Data is thus time multiplexed on the transmission line. The J.tA551 07 A, J.tA 75107 A
device specifications allow widely varying thermal and electrical environments at the various driver and receiver locations. The data-bus system offers maximum performance
at minimum cost.
The unique driver output circuit allows terminated transmission lines to be driven at normal line impedances. High
speed system operation is ensured since line reflections
are virtually eliminated when terminated lines are used.
Cross-talk is minimized by low signal amplitudes and low
line impedances.
The typical data delay in a system is approximately
(30 + 1.3L) ns, where L is the distance in feet separating
the driver and receiver. This delay includes one gate delay
in both the driver and receiver.
Data is impressed on the balanced-line system by unbalancing the line voltages with the driver output current. The
driven line is selected by appropriate driver input logic levels. The voltage difference is approximately:
V0 1FF "'" 112
10(on) • RT
(2)
The J.tA55107A, J.tA75107A dual line circuits may also be
used in unbalanced or single line systems. Although these
systems do not offer the same performance as balanced
systems for long lines, they are adequate for very short
lines where environment noise is not severe.
The receiver threshold level is established by applying a
DC reference voltage to one receiver input terminal. The
signal from the transmission line is applied to the remaining input. The reference voltage should be optimized so
(1)
High series line resistance will cause degradation of the
signal. The receivers, however, will detect signals as low
9-32
J,LA55107A· J,LA75107A
J,LA75107B • J,LA75108B
tionately. Input sensitivity, input Impedance and delay times
will be adversely affected.
that signal swing is symmetrical about it for maximum
noise margin. The reference voltage should be in the
range of -3.0 V to +3.0 V. It can be provided by a voltage supply or by a voltage divider from an available supply voltage.
The p.A75108B line receivers feature an open-collector-output circuit that can be connected in the DOT-OR logic
configuration with other p.A75108B outputs. This allows a
level of logic to be implemented without additional logic
delay.
Unbalanced or Single-Line Systems
INPUT~
VRE'-Y-
Increasing Common Mode Input Voltage Range of
Receiver
~OUTPUT
STROBES
R1
R2
Precautions in the Use of J..IA55107A, J..IA75107A
and J..IA75108B Dual Line Receivers
The following precaution should be observed when using
or testing j.LA551 07 A, p.A 75107A line circuits.
R2
R1
When only one receiver in a package is being used, at
least one of the differential inputs of the unused receiver
should be terminated at some voltage between -3.0 V
and + 3.0 V, preferably at ground. Failure to do so will
cause improper operation of the unit being used because
of common bias circuitry for the current sources of the
two receivers.
Cfl01900F
p.A75108B Wired-OR Output Connections
The p.A55107A, j.LA75107A and j.LA75108B line receivers
feature a common mode input voltage range of ± 3.0 V.
This satisfies the requirements for all but the noisiest system applications. For these severe noise environments, the
common mode range can be extended by the use of external input attenuators. Common mode input voltages can
in this way be reduced to ± 3.0 V at the receiver input
terminals. Differential data signals will be reduced propor-
~r=::::3JO-P~-OUTPUT
9-33
J,LA55110A • J,LA75110A
Dual Line Drivers
FAIRCHILD
A Schlumberger Company
Linear Division Interface Products
Description
Connection Diagram
14-Lead DIP and 50-14 Package
(Top View)
The J.lA55110AlJJA75110A have improved output current
regulation with supply voltage and temperature variations.
The higher current outputs allow data to be transmitted
over longer lines. These drivers offer optimum performance
when used with the J.lA55107A, JJA75107A, JJA75107B, and
J.lA75108B line receivers.
INA1
INA2
INHA
These drivers feature independent channels with common
voltage supply and ground terminals. The significant difference between the two drivers is in the output current
specification. The driver circuits feature a constant output
current that is switched to either of two output terminals
by the appropriate logic levels at the input terminals. The
output current can be switched off (inhibited) by LOW logic levels on the inhibit inputs.
INH9
IN 91
IN B2
GND
Order Information
The inhibit feature is provided so the circuits can be used
in party line or data bus applications. A strobe or inhibitor,
common to both drivers, is included for increased driver
logic versatility. The output current in the inhibited mode,
10(0If), is specified so that minimum line loading is induced
when the driver is used in a party line system with other
drivers. The output impedance of the driver in the inhibited
mode is very high; the output impedance of output transistor is biased to cutoff.
Inputs
Outputs
C
D
Al/Bl
A2/B2
X
X
L
X
OFF
OFF
X
X
X
L
Ol-F
OFF
L
X
H
H
ON
OFF
X
L
H
H
ON
OFF
H
H
H
H
OFF
ON
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
Molded Surface Mount
-65°C to + 175°C
-65°C to + 150°C
-55°C to +125°C
O°C to +70°C
300°C
265°C
1.36 W
1.04 W
0.93 W
±7.0 V
5.5 V
-5.0 V to 12 V
Noles
1. TJ Max - 175°C for the Ceramic DIP, and 150°C for the Molded DIP and
80-14.
Inhibitor
B
6A
6A
9A
KD
Storage Temperature Range
Ceramic DIP
Molded DIP and SO-14
Operating Temperature Range
Extended (JJA55110A)
Commercial (JJA75110A)
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP and SO-14
(soldering, 10 s)
Internal Power Dissipation 1, 2
14L-Ceramic DIP
14L-Molded DIP
SO-14
Supply Voltage 3
Input Voltage (any input)
Output Voltage (any output)
Function Table
A
Package Code
JJA55110ADM
JJA75110ADC
JJA75110APC
JJA75110ASC
Absolute Maximum Ratings
• No Output Transients On Power-Up Or Down
• Improved Stability Over Supply Voltage And
Temperature Ranges
• Constant Current, High Impedance Outputs
• High Speed 15 ns
• Standard Supply Voltages
• Inhibitor Available For Driver Selection
• High Common Mode Output Voltage Range
(-3.0 V to 10 V)
• TTL Input Compatibility
• Extended Temperature Range
Logic
Device Code
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 14L-Ceramic DIP at 9.1 mwrc, the 14L-Molded DIP at 8.3
mWI'C, and the 80-14 at 7.5 mWrC.
3. Voltage values are with respect to network ground terminal.
H - HIGH, L - LOW, X - Don't Care
9-34
Equivalent Circuit
Rl.
R2
6OOl!
Rl
2.2 k!l
,...-.03
O.
850"
I
-
I
"
INA2
2~ 08
OUTAl
850"
01
IN AI
V
550"
OS
3.5 kn
~Q4
......
~
01
~~ ZI
• t' Z2
o;-.t
02
OUTA2
Vas
......
O~
Vas
702
~ ~D9
R7
4 kn
~03
os
4kO
y-
GN0
y,
R9
1.2 kfl
08
2 kO
n~
J.
011
1.3kn
~
i~
010
n
R21
2.5 k!l
01S
r
Val.
011........
tI
2kU
013
,~
Q114
' " Z4
v---
01."
l
7 os
lY'
-
INH
8Ol!
70S
r
.".
COMMON
y,
4-
V
to Z3
~..
R10
1 kH
01.
3700
R10S
Rl09
2 kn
1.2 kll
n~
•
4Rl11
1.3kU
......
01'
018
017
01S
1 kO
5 kO
1 kU
. 1-'"
~~ ZI03
V 0109
r
019
011
All0 r / " 0
1 kn
R113
2 kll
~~ ZS
r-
...... 011S
70104
011
R112
3700 !I
'"'
)
011r-
~
'(,;
07
01S
RIS
12 k!l
Y-
.".
r-y,
~
0101
2.2kU
R114
0105
800"
sson
3.5 kU
Rl03
0104
850"
8500
I:
)
IN 81
......
0101
I
-
0102
0103........
OUTS1
~~ Z101
it' ZI02
V
......0106 010~
r.. 0102
INS.
70103
~ 013
~
01.
OUTB2
......0105
V 0104
,.--
0101
[
R107
0106
4 k!l
4 k!l
Y- _ > - - .".
o
= CROSSUNDER
9-35
I
8O!l
MA55110A· MA75110A
Recommended Operating Conditions 1
J.LA75110A
J.LA55110A
Symbol
Characteristic
V+
Positive Supply Voltage
V-
Negative Supply Voltage
VeM+
Positive Common Mode Voltage
VeM-
Negative Common Mode Voltage
TA
Operating Temperature
Min
Typ
Max
Typ
Min
Max
Unit
V
4.5
5.0
5.5
4.75
5.0
5.25
-4.5
-5.0
-5.5
-4.75
-5.0
-5.25
V
10
0
10
V
-3.0
0
125
0
0
0
-55
25
25
-3.0
V
70
°C
MA55110A, MA75110A
Electrical Characteristics Over recommended operating temperature range, unless otherwise specified.
DC Characteristics
Symbol
Condition 2
Characteristic
Min
Typ3
Max
Unit
V
VIH
Input Voltage HIGH
2.0
VIL
Input Voltage LOW
VIC
Input Clamp Voltage
Vce = Min, II = -12 mA
10(on)
On-State
Output Current
Vce = Max, Vo = 10 V
10(011)
Off-State Output Current
Vee = Min, Vo=10 V
100
J.LA
II
Input Current
At Maximum
Input Voltage
A,BorC
Inputs
Vee = Max, VI = 5.5 V
1.0
mA
IIH
Input Current HIGH
A,BorC
Input
IlL
Input Current LOW
A, B or C
Inputs
I+(on)
Positive Supply Current
With Driver Enabled
I-(on)
Negative Supply Current
With Driver Enabled
1+(011)
Positive Supply Current
With Driver Inhibited
I-(off)
Negative Supply Current
With Driver Inhibited
0.8
Vee = Min, Vo = -3.0 V
6.5
-0.9
-1.5
12
15
V
V
mA
12
2.0
D Input
Vee = Max, VI = 2.4 V
40
Vee = Max, VI = 0.4 V
-3.0
J.LA
80
D Input
mA
-6.0
D Input
Vee = Max,
A & B Inputs at 0.4 V,
C & D Inputs at 2.0 V
Vee = Max,
A, B, C, & D Inputs
at 0.4 V
9-36
23
35
mA
-34
-50
mA
21
mA
-17
mA
J..LA55110A· J..LA75110A
~55110A, IlA75110A (Cont.)
Electrical Characteristics
AC Characteristics Vcc
= ± 5.0
Symbol
tpLH
V, T A
= 25°C
Characteristic
Condition
Propagation Delay Time, LOW to HIGH
tpHL
Propagation Delay Time, HIGH to LOW
tpLH
Propagation Delay Time, LOW to HIGH
tpHL
Propagation Delay Time, HIGH to LOW
CL = 40 pF,
RL = 50 n
See Test
Circuit
Notes
1. When using only one channel of the line drivers, the other channel
should be inhibited and/or its outputs grounded.
2. For conditions shown as Min or Max, use appropriate value specified
under recommended operating conditions.
3. All typical values are Vee ~ ± 5.0 V, TA ~ 25"C
AC Test Circuit
;:-.....,.-......-OUTPUT 2
'---t-.....,.-OUTPUT 1
o
___'*___
I,.L
l-=-
RL
50n
TO OTHER CHANNEL -JI
Notes
1. The pulse generators have the following characteristics:
tr ~ tf ~ 10 ±5.0 ns, twl ~ 500 ns, PRR ~ 1.0 MHz,
tW2 ~ 1.0 ,"S, PRR ~ 500 kHz, Zo ~ 50 n.
2. CL includes probe and jig capacitance.
3. For simplicity, only one channel and the inhibitor connections are shown.
9-37
From
(Input)
To
(Output)
A or B
1 or 2
Cor D
1 or 2
Min
Typ
Max
Unit
9.0
15
ns
9.0
15
ns
16
25
ns
13
25
ns
pA55110A • pA75110A
AC Waveforms
'-___--JI\'"--~~~~~~~~::
LOGIC
INPUT
10R2
1..----lw2----I~1
3V
INHIBITOR
INPUT
OR
INHIBITOR
COMMON
50%
'--------------'.4---- 0V
OUT
2
,.~Ifi_------
__------------__--------OFF
OUT
1
'"-__~J.~--------------------ON
Typical Applications
Simplex Operation
p
DATA
IN
•+
DATA OUT
INHIBIT
RO/2
SHIELD OR COMMON GROUND RETURN
9-38
MA55110A • MA75110A
Typical Applications (Cont.)
Half-Duplex Operation
PORT
ENABLES
'--L-"'-PORT
ENABLES
OATA
IN
OATA
IN
SHIELD OR
COMMON GROUNO
RETURN
OATA
OUT
DATA
OUT
Notes
1. All drivers are jtA75110A or jtA55110A. Receivers are jtA75107A or
jtA75108B. Twisted-pair or coaxial transmission line should be used for
minimum noise and cross talk.
2. When only one driver in a package is being used, the outputs of the
other driver should either be grounded or inhibited to reduce power
dissipation.
9-39
•
MA75150
RS-232C
I=AIRCHILD
A Schlumberger Company
Dual Line Driver
Linear Division Interface Products
Description
Connection Diagram
14-Lead DIP
(Top View)
The pA75150 is a monolithic dual line driver designed to
satisfy the requirements of the standard interface between
data terminal equipment and data communication equipment as defined by EIA Standard RS-232C. A rate of 20K
bps can be transmitted with a full 2500 pF load. Other
applications are in data transmission systems using relatively short single lines, in level translators, and for driving
MOS devices. The logic input is compatible with most TTL
and DTL families. Operation is from + 12 V and -12 V
power supplies.
NC
STROBE
INA
INB
GND
• Withstands Sustained Output Short Circuit To Any
Low Impedance Voltage Between -25 V And + 25 V
• 2.0 IJS Max Transition Time Through The + 3.0 V To
-3.0 V Transition Region Under Full 2500 pF Load
• Inputs Compatible With Most TTL And DTL Families
• Common Strobe Input
• Inverting Output
• Slew Rate Can Be Controlled With An External
Capacitor At The Output
• Standard Supply Voltages ± 12 V
NC
NC
CDOO88OF
Order Information
Device Code
pA75150PC
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP and S0-8
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP and SO-8
(soldering, 10 s)
Internal Power Dissipation 1, 2
14L-Molded DIP
8L-Ceramic DIP
8L-Molded DIP
SO-8
Supply Voltage
Input Voltage3
Applied Output Voltage3
Package Code
9A
Package Description
Molded DIP
Connection Diagram
8-Lead DIP and SO-8 Package
(Top View)
-65·C to +175·C
-65·C to +150·C
O·C to +70·C
300·C
v+
STROBE
IN A L
265·C
1.04 W
1.30 W
0.93 W
0.81 W
±15 V
15 V
±25 V
r-r,--"
OUT A
INB
OUTB
GND
v-
Order Information
Device Code
pA75150RC
pA75150TC
pA75150SC
Notes
1. TJ Max = 175·C for the Ceramic DIP, and 150·C for the Molded DIP and
80·14.
2. Ratings apply to ambient temperature at 25·C. Above this temperature,
derate the 14L-Ceramic DIP at 9.1 mWrC, the 14L·Molded DIP at 8.3
mWrC, and the SO-14 at 7.5 mWrC.
3. Voltage values are with respect to network ground.
9-40
Package Code
6T
9T
KC
Package Description
Ceramic DIP
Molded DIP
Molded Surface Mount
MA75150
Equivalent Circuit (1/2 of Circuit)
y+------------1_-----------.------~----1_------------__,
R2
15kn
R1
111U1
01
IN
----------tCt--+
~OBE--------~C~~
07
09
OUT
011
GNO------------~--~--~
012
013
014
Note
Component values shown are nominal.
y------------------------------------+--------~----~~
Recommended Operating Conditions
Symbol
Characteristics
V+
Positive Supply Voltage
V-
Negative Supply Voltage
VI
Input Voltage
Vo
Applied Output Voltage
TA
Operating Temperature
Typ
Min
Unit
10.8
12
13.2
-10.8
-12
-13.2
V
5.5
V
0
0
9-41
Max
25
V
±15
V
70
·C
MA75150
J.lA75150
Electrical Characteristics TA = 0 to 70°C, unless otherwise specified. 1
DC Characteristics
Symbol
VIH
Characteristic
Condition
Input Voltage HIGH
Figure
1
VIL
Input Voltage LOW
VOH
Output Voltage HIGH
V+ =10.8 V, V- =-13.2 V,
VIL = 0.8 V, RL = 3.0 kil to 7.0 kil
2
VOL
Output Voltage LOW
Vee = ± 10.8 V, VIH = 2.0 V,
RL = 3.0 kil to 7.0 kil
1
IIH
Input Current HIGH
Vee = ± 13.2 V,
VI = 2.4 V
IlL
los
Input Current LOW
Output Short
Circuit Current
Min
5.0
Data Input
Vee = ± 13.2 V,
VI = 0.4
Strobe Input
Vee=±13.2V
Vo= 25 V
3
3
I-H
Negative Supply
Current HIGH
I+L
Positive Supply
Current LOW
I-L
Negative Supply
Current LOW
V
V
-5.0
V
J.l.A
1.0
10
2.0
20
-1.0
-1.6
-2.0
-3.2
2.0
4
mA
mA
-3.0
Vo=-25 V
15
Va = 0 V, VI = 3.0 V
Positive Supply
Current HIGH
8.0
-8.0
Strobe Input
Unit
V
2
Data Input
Max
0.8
-15
Vo = 0 V, VI = 0 V
I+H
Typ2
2.0
Vee = ± 13.2 V,
VI = 3.0 V, RL = 3.0 kil,
TA = 25°C
5
Vee=±13.2 V
VI = 3.0 V, RL = 3.0 kil,
TA = 25°C
5
10
22
mA
-1.0
-10
mA
8.0
17
mA
-9.0
-20
mA
AC Characteristics Vee = ± 12 V, TA = 25°C.
Symbol
Figure
Min
Typ2
Max
Unit
CL = 2500 pF,
RL = 3.0 kil to 7.0 kil
6
0.2
1.4
2.0
J.l.S
0.2
1.5
2.0
J.l.S
CL = 15 pF, RL = 7.0 kil
6
40
ns
20
ns
CL = 15 pF, RL = 7.0 kil
6
60
ns
45
ns
Condition
Characteristic
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
tTLH
Transition Time, Output LOW to HIGH
tTHL
Transition Time, Output HIGH to LOW
tpLH
Propagation Delay Time,
Output LOW to HIGH
tpHL
Propagation Delay Time,
Output HIGH to LOW
Notes
1. The algebraic convention where the most positive (least negative) limit is
designated as maximum is used in this data sheet for logic levels only,
e.g., when -5.0 V is the maximum, the typical value is a more negative
voltage.
2. All typical values are at Vee - ± 12 V. TA - 25"e.
9-42
MA75150
Typical Performance Curves
Typical Output Current vs
Applied Output Voltage
20
15
~
I
I-
z
'"::I
"::I....
10
5.0
II:
II:
V, =
-5.0
0
-10
--
::/::. ,
-
·15
20
-25
-
2.lv
I
,
·20 -15 -10 -5.0
-
I-
,-
I--
......
::I
_~cJJv
TA=25'C {
-Rl-7kH
I
I
..... RL ;=:3kH_
l.J
•
VIIO.4~
0
5.0
10
15
20
25
APPLIED OUTPUT VOLTAGE - V
Test Circuits
Figure 2 VIL. VOH (Note 1)
Figure 1 VIH. VOL
Figure 4 los
Figure 3 IIH. IlL
v+
~
IIH
v, -
.-
v-
l---l,
ffD-e+
r
NOTE
2
III
II
I
I
L
I
J
--l--
OPEN
Notes
1. Each input is tested separately.
2. When testing I,H. the other input is at 3.0 V; when testing I,L. the other
input is open.
3. los is tested for both input conditions at each of the specified output
conditions.
9-43
MA75150
Figure 6 Switching Characteristics
Figure 5 I+H' LH, I+L' LL (Note 1)
v+
I+H. I+L
~I
v-
It
3.0 V
"~
L_-r-_J
r
~~~:[==)o--t>--+-~---'---OUT
Okll
CA017QOF
Noles
1. Arrows indicate actual direction of current flow. Current into a terminal is
a positive value.
2. The pulse generator has the following characteristics: duty cycle -< 50%,
Zo~50
V+
I-H. I-L
n.
3. CL includes probe and jig capacitance.
Voltage Waveforms
I
I
~~10ns
....c:"l90:::.::-Y.----':;:90::::.'~.=!iL
::: -
t- - - - - - - -
3.0
V
I
I
IN
I
_"",.,;1:,:;O',;:;V'J):
:
~.:.11l'::;~:::..._ _ _ _ _ ov
:..---50 1 - ' $ - - -.....1: I
I.-tPHL~
'..... tPLH-.1
I
I
I
-----------~I
I
I
OUT
~3.0V
I
-3.0V
I
I
r;"";:"'-'"---"';;;;;"';';"F-+---
VOL
tTLHI~
9-44
MA75154
RS-232C
FAIRCHILD
A Schlumberger Company
Quad Line Receiver
Linear Division Interface Products
Description
Connection Diagram
16-Lead DIP
(Top View)
The /.IA75154 is a monolithic quad line receiver designed
to satisfy the requirements of the standard interface between data terminal equipment and data communication
equipment as defined by EIA Standard RS-232C. Other applications are for relatively short, single line, point-to-point
data transmission and for level translators. Operation is
normally from a single 5.0 V supply; however, a built-in
option allows operation from a 12 V supply without the
use of additional components. The output is compatible
with most TTL and DTL circuits when either supply voltage
is used.
~r
VCC2
Veel
CONTROLS
14
A
In normal operation, the threshold control terminals are
connected to the VCC1 terminal, lead 15, even if power is
being supplied via the alternate VCC2 terminal, lead 16.
This provides a wide hysteresis loop which is the difference between the positive-going and negative-going threshold voltages. In this mode of operation, if the input voltage
goes to zero, the output voltage will remain LOW or HIGH
as determined by the previous input.
THRESHOLD
CONTROL D
INA
OUT A
IN B
OUT B
INC
OUT C
IN D
CUT 0
GND
R1
Order Information
Device Code
For fail-safe operation, the threshold control terminals are
open. This reduces the hysteresis loop by causing the negative-going threshold voltage to be above zero. The positive-going threshold voltage remains above zero as it is
unaffected by the disposition of the threshold terminals. In
the fail-safe mode, if the input voltage goes to zero or an
open circuit condition, the output will go HIGH regardless
of the previous input condition.
1.IA75154DC
1.IA75154PC
Package Code
68
98
Package Description
Ceramic DIP
Molded DIP
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1, 2
16L-Ceramic DIP
16L-Molded DIP
Supply Voltage (Lead 15)3
Alternate Supply Voltage (Lead 16)3
Input Voltage 3
• Input Resistance - 3.0 kn To 7.0 kn Over Full
RS-232C Voltage Range
• Input Threshold Adjustable To Meet Fail-Safe
Requirements Without Using External Components
• Built-In Hysteresis For Increased Noise Immunity
• Inverting Output Compatible With DTL Or TTL
• Output With Active Pull-Up For Symmetrical
Switching Speeds
• Standard Supply Voltages - 5.0 V Or 12 V
-65°C to + 175°C
-65°C to + 150°C
O°C to +70°C
300°C
265°C
1.50 W
1.04 W
7.0 V
14 V
±25 V
Notes
1. T J Max~ 175·C for the Ceramic DIP, and 150·C for the Molded DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 16L-Ceramic DIP at 10 mwrc, and the 16L·Molded DIP at
8.3 mWrC.
3. Voltage values are with respect to network ground terminal.
9-45
MA75154
,---,
Equivalent Circuit (Note 1)
---------1
COMMON TO 4 CIRCUITS
Vee2 -+---"""1~---'
(NOTE 2)
1 OF 4 RECEIVERS
I
5 kn
I
3.2kH
1.6 kn
1.6 kU
200!l
1.4 k!l
I
I
V C C 1 - + - - -.....
I
I
I
OUT
I
4.2
.....____+-+~
k~l
R1-+-~~
I
GNO-~------~
1 kU
I
I
L _________ ~
Notes
1. Component values shown are normal.
2. When using Vee" Vee2 may be left open or shorted to Vee,. When
using Vee2, Vee, must be left open or connected to the threshold
control leads.
Recommended Operating Conditions
Symbol
Characteristic
Typ
Min
Max
Unit
VCCl
Supply Voltage
4.5
5
5.5
V
VCC2
Supply Voltage
10.8
12
13.2
V
±15
V
VI
Input Voltage
N
Normalized Fan Out from
Each Output
TA
Operating Temperature
10
0
9-46
25
70
°C
MA75154
JlA75154
Electrical Characteristics TA
=
0 to 70 0 e unless otherwise specified. 3
DC Characteristics
Symbol
Characteristic
Condition
Figure
VIH
Input Voltage HIGH
1
VIL
Input Voltage LOW
1
VTH+
Positive-Going
Threshold Voltage
Normal Operation
1
Negative-Going
Threshold Voltage
(VTH+) (VTH-)
Hysteresis
VOH
Output Voltage HIGH
10H =-400 /J.A
1
VOL
Output Voltage LOW
10l = 16 mA
1
RI
Input Resistance
f,VI = -25 V to -14 V
2
Normal Operation
1
Fail-Safe Operation
Normal Operation
Max
Unit
-3.0
V
V
3.0
Fail-Safe Operation
VTH-
Typ2
Min
1
V
0.8
2.2
3.0
0.8
2.2
3.0
-3.0
-1.1
0
0.8
1.4
3.0
0.8
3.3
6.0
0
0.8
2.2
Fail-Safe Operation
2.4
3.5
V
V
V
0.23
0.4
V
3.0
5.0
7.0
kn
f,VI = -14 V to -3.0 V
3.0
5.0
7.0
f,VI = -3.0 V to +3.0 V
3.0
6.0
f,VI = 3.0 V to 14 V
3.0
5.0
7.0
7.0
f,VI = 14 V to 25 V
3.0
5.0
11=0 mA
3
0
0.2
2.0
V
los
Output Short Circuit CurrentI
VCCI = 5.5 V, VI = -5 V
4
-10
-20
-40
mA
ICCI
Supply Current from VCCI
VCCI = 5.5 V, T A = 25°C
5
20
35
mA
ICC2
Supply Current from VCC2
VCC2 = 13.2 V,
TA = 25°C
23
40
mA
Max
Unit
VI (open)
Input Open Circuit Voltage
AC Characteristics VCCI = 5.0 V, TA = 25°C
Symbol
Characteristic
tpLH
Propagation Delay Time, LOW-to-HIGH
tpHL
Condition
CL = 50 pF, RL = 390
Figure
n
Min
Typ
22
ns
Propagation Delay Time, HIGH-to-LOW
20
ns
tTLH
Transition Time, LOW-to-HIGH
9.0
ns
tTHL
Transition Time, HIGH-to-LOW
6.0
ns
Notes
I. Not more than one output should be shorted at a time.
2. All typical values are at V, ~ 5.0 V, TA ~ 25°C.
3. The algebraic convention where the most positive (least negative) limit is
designated as maximum is used in this data sheet for logic and
threshold levels only, e.g., when -3.0 V is the maximum, the minimum
limit is a more negative voltage.
9-47
6
IlA75154
Typical Characteristics
Output Voltage vs Input Voltage (Note 1)
4.0
-"
Vee,
=5.0 V
TA= 25°C
> 3.0
I
~
NORMAL
OPERATION
~
~
I
2.0
/!
r-
FAIL-SAFE
OPERATION
VrH-
VTH-
u
"
f..
VTH+
"
1.0
/I
',',
/!
o
-2S
"
- 4.0
- 3.0
-2.0
-1.0
0
1.0
2.0
3.0
4.0
INPUT VOLTAGE-V
Note
1. For normal operation, the threshold controls are connected to
fail-safe operation, the threshold controls are open.
Vcc,.
For
DC Test Circuits
s.svo
013.2 V
Note
1. Arrows indicate actual direction of current flow. Current into a terminal is
a positive value.
9-48
"
2S
J,LA75154
DC Test Circuits (Cont.)
Test Table
Test
In
T
VOH
Open
Open
IOH
4.5 V
VOH
Open
Open
IOH
Open
10.8 V
VTH+ Min.
VTH- Min (fail-safe)
VOH
0.8 V
Open
IOH
5.5 V
Open
VOH
0.8 V
Open
IOH
Open
13.2 V
VTH- Min (normal)
VOH
Note 1
Lead 15
IOH
5.5 V and TH
Open
VOH
Note 1
Lead 15
IOH
TH
13.2 V
VIL Max.
VTH- Min (normal)
VOH
-3.0 V
Lead 15
IOH
5.5 V and TH
Open
VOH
-3.0 V
Lead 15
IOH
TH
13.2 V
VIH Min. VTH+ Max.
VTH- Max (fail-safe)
VOL
3.0 V
Open
IOL
4.5 V
Open
VOL
3.0 V
Open
IOL
Open
10.8 V
Open
Measure
Open circuit input
(fail-safe)
VIH Min.
VTH+ Max (normal)
VTH- Max (normal)
Out
VCC1
VCC2
Open
VOL
3.0 V
Lead 15
IOL
4.5 V and TH
VOL
3.0 V
Lead 15
IOL
TH
10.8 V
VOL
Note 2
Lead 15
IOL
5.5 V and TH
Open
VOL
Note 2
Lead 15
IOL
TH
13.2 V
Notes
1. Momentarily apply -5.0 V. then 0.8 V.
2. Momentarily apply 5.0 V. then ground.
Figure 2
Test Table
RI
Op::~vo (::PEN
.L
-=
I,
0
I: -
0
15
~IIN
V,
16
Vee, VCC2 -
TH
OPEN
---.1
"I
OUT
I
I OPEN
I
L __ - T --. _J
GND
9-49
VCC2
Open
Open
GND
Open
Open
Open
Open
Open
1
-=
VCC1
5.0 V
Lead 15
TH and 5.0 V
Open
GND
GND
Open
Open
Open
12 V
Open
Open
GND
Lead 15
TH
12 V
Lead 15
TH
GND
Lead 15
TH
Open
IlA75154
DC Test Circuits (Cont.)
Figure 4
los (Note 1)
OPEN
Figure 3
V1(open)
5'5V:J0_10--0 3,2
1
5.5 V
OPEN
OPEN
Veel
VCC2
R1
_k.-16_~
I
v
OUT/
-5.0 V
/
15
16
- - Vq:1 VCC2 - -
Rl
~IOS
I
GND
OUT/
+ 1
1
-.-l
/
L __ -T- __ J
OPEN
><>---=-='-+-I
VI(OPEN)L
---T---
~
J
-OPEN
Figure 5
Icc (Note 2)
5'5V)C:~E-IICC~13'2V
GND
t
OPEN
Test Table
TH
VCC1
rTi
I ::
VCC2
Open
5.5 V
Open
Lead 15
5.5 V
Open
Open
Open
13.2 V
Lead 15
TH
13.2 V
5.0 V
-
t
Vee1 VCC2
OPEN
-~II
R1
.><:>-_-""ou~T-r-1-OPEN
Notes
1. Each output is tested separately.
2. All four line receivers are tested simultaneously. Arrows indicate actual
direction of current flow. Current into a terminal is a positive value,
9-50
MA75154
AC Test Circuit
5.0 V
IN
OPEN
j--TH
PULSE
GENERATOR
(NOTE 1)
_
OPEN
15_~_~_
VCC1
VCC2
OUT
R1
liN
'I
RL
=
390 11
oUTI
I
I
L----T----J
I
CL == 50 pF
(NOTE 2)
GND
•
Voltage Waveforms
Notes
1. The pulse generator has the following characteristics:
tw ~ 200 ns, duty cycle';; 20%, Zo ~ 50 n.
2. C L includes probe and jig capacitance.
3. All diodes are 1N3064.
9-51
J.lA75450/60/70 Series
F=AIRCHILO
Dual Peripheral Drivers
A Schlumberger Company
Linear Division Interface Products
Description
The JJA75400 series offers flexibility in designing high
speed logic buffers, power drivers, lamp drivers, line drivers, MOS drivers, clock drivers, and memory drivers.
The JJA75400 series of devices are dual high speed general purpose interface drivers that convert TTL and DTL
logic levels to high current drive capability. The JJA75450
features two TTL NAND gates and two uncommitted transistors. The JJA 75451, JJA 75452, and JJA 75453 feature two
standard series 74 TTL gates in AND, NAND and OR
configurations respectively, driving the base of two high
voltage, high current, uncommitted collector output transistors.
•
•
•
•
•
No Latch·Up Up To 55 V
High Output Current Capability
TTL Or DTL Input Compatibility
Input Clamp Diodes
5.0 V Supply Voltage
Absolute Maximum Ratings
JJA75451
JJA75452
JJA75453
JJA75450
Storage Temperature Range 1
Ceramic DIP
JJA75461
JJA75462
JJA75471
JJA75472
-65°C to +175°C
-65°C to + 175°C
-65°C to + 150°C
-65°C to + 150°C
Operating Temperature Range
O°C to +70°C
O°C to +70°C
Lead Temperature
Ceramic DIP (soldering, 60 s)
300°C
300°C
265°C
265°C
Molded DIP and SO-8
Molded DIP and SO-8 (soldering, 10 s)
Internal Power Dissipation 2 , 3
14L-Ceramic DIP
1.36 W
14L-Molded DIP
1.04 W
8L-Ceramic DIP
1.30 W
8L-Molded DIP
0.93 W
SO-8
0.81 W
Supply Voltage 4
7.0 V
Input Voltage4
5.5 V
5.5 V
Inter-emitter Voltage5
5.5 V
5.5 V
Vcc to Substrate Voltage 9
35 V
Collector to Substrate Voltage 9
35 V
Collector to Base Voltage
35 V
Collector to Emitter Voltage6
30 V
Emitter to Base Voltage
Output Voltage4 and 7
5.0 V
Continuous Collector Current8
300 mA
7.0 V
Table 2
300 mA
Continuous Output Current8
Notes
1. 1lA75452 is Molded DIP and 50-8 only.
2. TJ Max -175·C for the Ceramic DIP, and 150·C for the Molded DIP.
3. Ratings apply to ambient temperature at 25·C. Above this temperature,
derate the 14L-Ceramic DIP at 9.1 mW/·C, the 14L-Molded DIP at 8.3
mWrC, the 8L-Ceramic DIP at 8.7 mWrC, and the 8L-Molded DIP at
5. This is the voltage between two emitters of a mulitiple emitter input
transistor.
6. This value applies when the base-emitter resistance (RBE) is equal to or
less than 500 n.
7. This is the maximum Yoltage which should be applied to any output
when it is in the off state.
S. Both halves of these dual circuits may conduct rated current
simultaneously.
9. For the !lA75450 only, the substrate (Lead 8), must always be at the
most negative device voltage for proper operation.
7.5 mWrC.
4. Voltage values are with respect to network ground terminal unless
otherwise specified.
9-52
IlA75450/60/70 Series
Test Table 1 Operating Temperature Range and Supply Voltage Range
Symbol
Characteristic
TA
Operating Temperature
Vee
Supply Voltage
!1A75000 Series
O°C to 70°C
+4.75 V to +5.25 V
Test Table 2
VOH
Vs
!1A75471
!1A75472
!1A7545X
!1A75461
J1A75462
Maximum Output
30 V
35 V
80
Maximum, Latch-up
20
V
30 V
55
Symbol
Characteristic
V
V
Equivalent Circuit
J.tA75450
Dual Positive AND Peripheral Drivers
..---;---T"-......- - - - v c c
Connection Diagram
14-Lead DIP
(Top View)
1.6k
4k
130
1E
GATE
INA
1B
1C
1B
SUB
G
1C
4k
1E
1.6 k
130
GNO
2C
OUT
Logic Function
B
Positive Logic: Z = XY (gate only)
Z = XY (gate and transistor)
IN
-+--i--+
2B
2E
Order Information
Device Code
J.tA75450DC
J.tA75450PC
Package Code
6A
9A
~~-~--~-~~--------GNO
Package Description
Ceramic DIP
Molded DIP
All resistor values in ohms
9-53
J.lA75450/60/70 Series
IlA75450
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, (use Test
Table 1), unless otherwise indicated.
DC Characteristics
TTL Gates
Symbol
Characteristic
Test
Figure
Condition
Min
Typl
Max
Unit
V
VIH
Input Voltage HIGH
1
VIL
Input Voltage LOW
2
0.8
V
VIC
Input Clamp Diode Voltage
Vcc = Min, II = -12 mA
3
-1.5
V
VOH
Output Voltage HIGH
Vcc = Min, Vil = 0.8 V,
10H = -400 /lA
2
VOL
Output Voltage LOW
Vcc = Min, VIH = 2.0 V,
10L = 16 mA
1
II
Input Current at
Maximum Input
Voltage
Input A
Vcc = Max, VI = 5.5 V
4
Input Current HIGH
Input A
IIH
2.0
2.4
3.3
0.22
Input G
Vcc = Max, VI = 2.4 V
4
0.4
V
1.0
mA
2.0
mA
40
!lA
80
Input G
Input A
V
Vcc = Max, VI = 0.4 V
-1.6
3
IlL
Input Current LOW
los
Input G
Output Short Circuit Current2
Vcc = Max
5
ICCH
Supply Current HIGH
Vcc = Max, VI = 0 V
6
ICCl
Supply Current LOW
Vcc = Max, VI = 5.0 V
mA
-3.2
-18
-55
mA
2.0
4.0
mA
6.0
11
Output Transistors (Note 4)
Symbol
Characteristic
Condition
Min
V
5.0
V
V(BR)CER
Collector to Base
Breakdown Voltage
Ic = 100 /lA, RBE = 500
V(BR)EBO
Emitter to Base
Breakdown Voltage
IE=100 /lA, Ic=O!lA
hFE
Static Forward Current
Transfer Rati0 3
VCE = 3.0 V, Ic = 100 mA, TA = 25°C
25
VCE = 3.0 V, Ic = 300 mA, T A = 25°C
30
VCE = 3.0 V, Ic = 100 mA
20
VCE = 3.0 V, Ic = 300 mA
25
VSE(sat)
VCE(sat)
Collector to Emitter Saturation
Voltage 3
18 = 10 mA, Ic = 100 mA
0.85
1.0
IB = 30 mA, Ic = 300 mA
1.05
1.2
IB=10 mA, Ic=100 mA
0.25
0.4
IB = 30 mA, Ic = 300 mA
0.5
0.7
9-54
Unit
30
Ic=100 /lA, IE=O /lA
Base to Emitter Voltage3
Max
V
Collector to Base
Breakdown Voltage
.n
Typl
35
V(BR)CBO
V
V
IlA75450/60/70 Series
fJA75450 (Cont.)
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, (use Test
Table 1), unless otherwise indicated.
AC Characteristics Vcc = 5.0 V, TA = 25°C
TTL Gates
Symbol
Characteristic
tPLH
Propagation Delay Time,
LOW to HIGH
tpHL
Propagation Delay Time,
HIGH to LOW
Condition
CL = 15 pF, RL = 400
n
Test
Figure
J.lA75450B
Min
12
Typ
Max
Unit
12
22
ns
8.0
15
ns
Typ
Max
Unit
8.0
15
ns
12
20
Output Transistors
Symbol
Condition 3
Characteristic
Test
Figure
Min
td
Delay Time
tr
Rise Time
ts
Storage Time
7.0
15
ns
tf
Fall Time
6.0
15
ns
Typ
Max
Unit
20
30
ns
20
30
ns
ns
Ic = 200 mA, VSE(off) = -1.0 V,
IS(I) = 20 mA, IS(2) = -40 mA,
CL=15 pF, RL=50
13
n
ns
--"--,"
Gates and Transistors Combined
Symbol
Condition
Characteristic
Ic= 200 mA,
CL=15 pF,
RL = 50 n
Test
Figure
Min
tpLH
Propagation Delay Time, LOW to HIGH
tpHL
Propagation Delay Time, HIGH to LOW
tTLH
Transition Time, LOW to HIGH
7.0
12
tTHL
Transition Time, HIGH to LOW
9.0
15
VOH
HIGH Level Output Voltage After
Switching
VI =20 V,
Ic"'300 mA,
RSE = 500 n
Notes
1. All typical values are at Vee ~ 5.0 v. TA ~ 25°C.
2. Not more than one output should be shorted at a time.
3. These parameters must be measured using the pulse techniques.
tw = 300 J.lS, duty cycle < 2%.
4. Voltage and current values shown are nominal; exact values vary slightly
with transistor parameter.
9-55
14
15
VI-6.5
ns
mV
•
J-lA75450/60/70 Series
Truth Table
~75451, ~75461, ~75471
Dual Positive AND Peripheral Drivers
Output
Inputs
Connection Diagram
8-Lead DIP and 50-8 Package
(Top View)
IN A1 LJ-----,
Vee
INA2
IN B2
OUT A
INB1
GND
n-+----'
Device Code
OUT B
Package Code
Package Description
6T
KC
9T
9T
9T
Ceramic DIP
Molded Surface Mount
Molded DIP
Molded DIP
Molded DIP
Equivalent Circuit (1/2 of Circuit)
,---_-_-----vcc
4k
1.6k
130
OUTPUT
INPUTS
L
L
L
H
H
H
L
L
L
L
H
H
H = HIGH Level, L
Order Information
1lA75451RC
1lA75451SC
MA75451TC
MA75461TC
1lA75471TC
X
y
{_+-_..
t--~--~~---+-*--~--GND
Notes
Component values shown are nominal.
All resistor values in ohms.
9-56
= LOW
Level
Z
(on
(on
(on
(off
state)
state)
state)
state)
MA75450/60/70 Series
IlA75451
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, (use Test
Table 1), unless otherwise indicated.
DC Characteristics
Symbol
Characteristic
Condition
Test
Figure
!1A75451
Min
Typ1
Max
2.0
Unit
VIH
Input Voltage HIGH
7
VIL
Input Voltage LOW
7
0.8
V
VCD
Input Clamp
Diode Voltage
Vcc= Min,
11=-12mA
8
-1.5
V
10H
Output Current HIGH 2
Vcc= Min,
VIH = 2.0 V
7
100
p.A
VOL
Output Voltage LOW
Vcc= Min,
VIL = 0.8 V,
10L = 100 mA
7
0.25
0.4
V
0.5
0.7
Vcc= Min,
VIL = 0.8 V,
10L = 300 mA
V
II
Input Current at Maximum
Input Voltage
Vcc = Max,
VI = 5.5 V
9
1.0
mA
IIH
Input Current HIGH
Vcc= Max,
VI = 2.4 V
9
40
p.A
IlL
Input Current LOW
Vcc= Max,
VI = 0.4 V
8
-1.0
-1.6
mA
ICCH
Supply Current HIGH
Vcc = Max,
VI = 5.0 V
10
7.0
11
mA
ICCL
Supply Current LOW
Vcc= Max,
VI=O V
52
65
mA
Typ
Max
18
25
ns
25
25
ns
ns
AC Characteristics Vcc = 5.0 V, TA = 25°C
Symbol
Characteristic
tpLH
Propagation Delay Time, LOW
to HIGH
tpHL
Propagation Delay Time, HIGH
to LOW
Condition
10"'200 mA,
CL = 15 pF,
RL = 50
Test
Figure
Min
14
n
tTLH
Transition Time, LOW to HIGH
5.0
8.0
tTHL
Transition Time, HIGH to LOW
7.0
12
VOH
HIGH Level Output Voltage After
Switching 3
10"'300 mA
9-57
15
VI-6.5
Unit
ns
mV
•
jlA75450/S0/70 Series
1lA75461, 1lA75471
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, (use Test
Table 1), unless otherwise indicated.
DC Characteristics
~75461
Test
Figure
Min
VIH
Input Voltage HIGH
7
2.0
VIL
Input Voltage LOW
7
VIC
Input Clamp
Diode Voltage
Vce= Min,
11=-12mA
8
10H
Output Current HIGH 2
Vee = Min,
VIH = 2.0 V
7
VOL
Output Voltage LOW
Vee = Min,
VIL = 0.8 V,
10L = 100 mA
7
Symbol
Characteristic
Condition
Typl
IlA75471
Max
Typl
Min
-1.2
Unit
V
0.8
-1.5
-1.2
100
Vee = Min,
VIL = 0.8 V,
10L = 300 mA
Max
2.0
0.8
V
-1.5
V
100
IlA
V
0.16
0.4
0.16
0.4
0.35
0.7
0.35
0.7
II
Input Current at Maximum
Input Voltage
Vee = Max,
VI = 5.5 V
9
1.0
1.0
mA
IIH
Input Current HIGH
Vee = Max,
VI = 2.4 V
9
40
40
IlA
IlL
Input Current LOW
Vee = Max,
VI = 0.4 V
8
ICCH
Supply Current HIGH
Vce= Max,
VI = 5.0 V
10
ICCL
Supply Current LOW
Vcc= Max,
VI=O V
-1.0
-1.6
-1.0
-1.6
mA
8.0
11
8.0
11
mA
61
76
61
76
mA
AC Characteristics Vcc = 5.0 V, TA = 25°C
Symbol
Characteristic
Condition
Test
Figure
~75471
IlA75461
Min
Typ
Max
Typ
Max
Unit
35
55
35
55
ns
25
40
25
40
ns
ns
Min
tpLH
Propagation Delay Time, LOW
to HIGH
tpHL
Propagation Delay Time, HIGH
to LOW
tTLH
Transition Time, LOW to HIGH
8
20
8.0
20
tTHL
Transition Time, HIGH to LOW
10
20
10
20
VOH
HIGH Level Output Voltage
After Switching 3
10""200 mA,
CL=15pF,
RL = 50 n
10""300 mA
Notes
1. All typical values are at Vee = 5.0 V, TA = 25°C.
2. VOH = 30 V for pA75451 , 35 V for I'A75461, 80 V for pA75471.
3. V, = 20 V for pA75451, 30 V for I'A75461, 55 V for I'A75471.
9-58
14
15
V!-10
VI-18
ns
mV
JIA75450/60/70 Series
Truth Table
f.lA75452, f.lA75462, f.lA75472
Dual Positive NAND Peripheral Driver
Inputs
Connection Diagram
8-Lead DIP and 80-8 Package
(Top View)
Output
2
L
L
H
H
INAI
L
H
L
H
H - HIGH Level. L - LOW Level
INA2
OUT A
GND
Order Information
Device Code
Package Code
J.lA75452SC
J.lA75452TC
J.LA75462TC
J.lA75472TC
Package Description
Molded
Molded
Molded
Molded
KC
9T
9T
9T
Surface Mount
DIP
DIP
DIP
Equivalent Circuit (112 of Circuit)
r--_.-----.--......- - -vcc
4kn
1.6kn
1.6 kn
130n
UTPUT
INPUTS[_+-~
Notes
Component values shown are nominal.
All resistor values in ohms.
9-59
H
H
H
L
(off
(off
(off
(on
state)
state)
state)
state)
~A75450/60/70
Series
pA75452
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, (use Test
Table 1), unless otherwise indicated.
DC Characteristics
J,LA75452B
Test
Figure
Min
VIH
Input Voltage HIGH
7
2.0
Vil
Input Voltage LOW
7
0.8
V
VIC
Input Clamp
Diode Voltage
Vcc= Min,
11=-12 rnA
8
-1.5
V
10H
Output Current HIGH 2
Vcc= Min,
Vil = 0.8 V
7
100
JlA
VOL
Output Voltage LOW
Vcc = Min,
VIH = 2.0 V,
10l = 100 rnA
7
0.25
0.4
V
0.5
0.7
Symbol
Characteristic
Condition
Vcc= Min,
VIH = 2.0 V,
10l = 300 rnA
Typ1
Max
Unit
V
II
Input Current at Maximum
Input Voltage
Vcc= Max,
VI = 5.5 V
9
1.0
rnA
IIH
Input Current HIGH
Vcc= Max,
VI = 2.4 V
9
40
JJ.A
III
Input Current LOW
Vcc= Max,
VI = 0.4 V
8
-1.0
-1.6
rnA
ICCH
Supply Current HIGH
Vcc= Max,
VI =0 V
10
11
14
rnA
ICCl
Supply Current LOW
Vcc= Max,
VI = 5.0 V
56
71
rnA
Typ
Max
25
35
ns
22
35
ns
ns
J.LA75452
AC Characteristics Vcc = 5.0 V, TA = 25°C
Symbol
Characteristic
Condition
Test
Figure
Min
tplH
Propagation Delay Time, LOW
to HIGH
tpHl
Propagation Delay Time, HIGH
to LOW
tTlH
Transition Time, LOW to HIGH
5.0
8.0
tTHl
Transition Time, HIGH to LOW
7.0
12
VOH
HIGH Level Output Voltage After
Switching 3
10"'200 rnA,
Cl=15pF,
Rl = 50 .n
10"'300 rnA
9-60
14
15
VI-6.5
Unit
ns
mV
MA75450/60/70 Series
iJ.A75462! iJ.A75472
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, (use Test
Table 1), unless otherwise indicated.
DC Characteristics
Symbol
Characteristic
Condition
IlA75462
Test
Figure
Min
2.0
VIH
Input Voltage HIGH
7
VIL
Input Voltage LOW
7
VCD
Input Clamp
Diode Voltage
Vcc= Min,
11=-12 mA
8
10H
Output Current HIGH 2
Vcc= Min,
VIL = 0.8 V
7
VOL
Output Voltage LOW
Vcc= Min,
V1H =2.0 V,
10L = 100 mA
7
Typ1
IlA75472
Max
Typ1
Min
Unit
V
0.8
-1.2
-1.5
-1.2
100
Vcc= Min,
VIH =2.0 V,
10L = 300 mA
Max
2.0
0.8
V
-1.5
V
100
!-LA
V
0.16
0.4
0.16
0.4
0.35
0.7
0.35
0.7
..
-----
,.
II
Input Current at Maximum
Input Voltage
Vcc= Max,
VI =5.5 V
9
1.0
1.0
mA
IIH
Input Current HIGH
Vcc= Max,
VI = 2.4 V
9
40
40
IlA
IlL
Input Current LOW
Vcc= Max,
VI = 0.4 V
8
-1.0
-1.6
-1.0
-1.6
mA
ICCH
Supply Current HIGH
Vcc= Max,
VI=O V
10
13
17
13
17
mA
ICCL
Supply Current LOW
Vcc= Max,
VI = 5.0 V
65
76
65
76
mA
Typ
Max
Unit
65
ns
AC Characteristics Vcc = 5.0 V, T A = 25°C
Symbol
Characteristic
Condition
Test
Figure
!lA75472
!lA75462
Min
Typ
Max
Min
50
65
45
40
50
30
50
ns
Transition Time, LOW to HIGH
12
25
13
25
ns
Transition Time, HIGH to LOW
15
20
10
20
tpLH
Propagation Delay Time, LOW
to HIGH
tpHL
Propagation Delay Time, HIGH
to LOW
tTLH
tTHL
VOH
HIGH Level Output Voltage
After Switching 3
10""200 mA,
CL=15pF,
RL = 50
14
.n
10""300 mA
Notes
1. All typical values are at Vee = 5.0 V, TA = 25"C.
2. VOH = 30 V for ",,75452, 35 V for ",,75462, 80 V for ",,75472.
3. Vs = 20 V for ",,75452, 30 V for ",,75462 and 55 V for ",,75472.
9-61
15
VI-10
VI-18
ns
mV
IlA75450/S0/70 Series
Truth Table
J.lA75453
Dual Positive OR Peripheral Drivers
Inputs
Connection Diagram
8·Lead DIP and 50·8 Package
(Top View)
INA1
Vee
IN A2
IN 92
OUT A
IN 81
GND
2
L
L
H
H
H
~
OUT B
Device Code
Package Code
Package Description
6T
KG
9T
Ceramic DIP
Molded Surface Mount
Molded DIP
Equivalent Circuit (112 of Circuit)
r-------~--------~-----.--------""""VCC
1k
500
~----~----~--------------__~-4----~'GND
Notes
Component values shown are nominal.
All resistor values in ohms.
9-62
L
H
L
H
HIGH Level, L ~ LOW Level
Order Information
pA75453RG
pA75453SG
pA75453TG
Output
L
H
H
H
(on
(off
(off
(off
state)
state)
state)
state)
JlA75450/60/70 Series
MA75453
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, (use Test
Table 1), unless otherwise indicated.
DC Characteristics
Symbol
Characteristic
Condition
Test
Figure
Min
2.0
Typl
Max
Unit
VIH
Input Voltage HIGH
7
VIL
Input Voltage LOW
7
0.8
V
V
VIC
Input Clamp Diode Voltage
Vcc = Min, II = -12 mA
8
-1.5
V
10H
Output Current HIGH
Vcc = Min, VOH = 30 V,
VIH = 2.0 V
7
100
MA
VOL
Output Voltage LOW
Vcc = Min, VIL = 0.8 V,
10L = 100 mA
7
0.25
0.4
V
0.5
0.7
Vcc = Min, VIL = 0.8 V,
IOL = 300 mA
II
Input Current at Maximum Input
Voltage
Vcc = Max, VI = 5.5 V
9
1.0
IIH
Input Current HIGH
Vcc = Max, VI = 2.4 V
9
IlL
Input Current LOW
Vcc = Max, VI = 0.4 V
8
-1.0
ICCH
Supply Current HIGH
Vcc = Max, VI = 5.0 V
11
ICCL
Supply Current LOW
Vcc = Max, VI = 0 V
mA
40
IlA
-1.6
mA
8.0
11
mA
54
68
mA
Typ
Max
Unit
18
25
ns
16
25
ns
ns
AC Characteristics Vcc = 5.0 V, TA = 25°C
Symbol
Characteristic
Condition
Test
Figure
MA75453
Min
tpLH
Propagation Delay Time, LOW to
HIGH
tpHL
Propagation Delay Time, HIGH to
LOW
tTLH
Transition Time, LOW to HIGH
5.0
8.0
tTHL
Transition Time, HIGH to LOW
7.0
12
VOH
HIGH Level Output Voltage After
Switching
10""200 mA,
CL = 15 pF,
RL = 50
14
n
VI = 20 V,
10""300 mA
Notes
1. All typical values are at Vee - 5.0 V, TA - 25°C.
9-63
15
VI -6.5
ns
mV
•
JIA75450/60/70 Series
Characteristics Measurement Information
DC Test Circuits (Note 1)
Figure 1 VIH. VOL (Note 2)
Figure 4
Vee
Vee
10L
V,H
I.. IIH (Note 3)
VI-----f --,
--'=~[)~-T"""::·==-'
OPEN
t
I
t
Figure 5
CR00370F
los (Note 5)
Vee
Figure 2 Vil. VOH (Note 3)
Vee
~
V,L
VOH
1t
-=
Figure 6
ICCH. ICCl (Note 6)
V'-"""'1--r""\.
OPEN
Figure 3 VIC. III (Notes 3 and 4)
4.5 V
---====
..,!Lj
VI _ _ _ _
'lfT
! 1
Vee
--"1.._'
OPEN
Figure 7 VIH. Vil. 10H. VOL (Note 3)
CROO390F
V,H
VOL
Notes
1. Arrows indicate actual direction of current flow. Current into a terminal is
a positive value.
2. Both inputs are tested simultaneously.
3. Each input is tested separately.
4. When testing V'c, input not under test is open.
5. Eaeh gate is tested separately.
6. Both gates are tested simultaneously.
1
9-64
-=
t
MA75450/60/70 Series
Characteristics Measurement Information (Cont.)
Figure 9
110 IIH (Note 1)
Vee
DC Test Circuits (Note 5)
ii, hH
Test Table 2
V,
Input
Under
Test
Other
Input
Apply
Measure
f.lA754X1
VIH
VIL
VIH
Vee
VOH
IOL
IOH
VOL
f.lA754X2
VIH
VIL
VIH
Vee
IOL
VOH
VOL
IOH
/JA754X3
VIH
VIL
GND
VIL
VOH
IOL
IOH
VOL
Circuit
Figure 8
-A,B
Output
B,A
Figure 10
(Note 4)
CIRCUIT y
UNDER
TEST
OPEN
ICCH' ICCl for AND, NAND Circuits
VIC, III (Note 1)
Vec
OPEN
ICCH • •ICCL
Vee
4.5V----....,
r
V,--t--+--r-,
CIRCUIT Y
UNDER
B,A
OPEN
TEST
I ___
L
Figure 11
Notes
1. Each input is tested separately.
2. When lesting I'L J.lA75400, Ihe inpul not under test is grounded. For all
other circuits it is at 4.5 V.
3. When testing VIC. input not under test is open.
4. Both gates are tested simultaneously.
5. Arrows indicate actual direction of current flow. Current into a terminal is
a position value.
II
ICCH' ICCl for OR, NOR Circuits (Note 4)
VI----+~I""'_
I
L ___
9·65
1
I
I
I
J
J1A75450/S0/70 Series
Characteristics Measurement Information (Cont.)
Switching Characteristics
Figure 12
Propagation Delay Times, Each Gate
()lA75450 Only)
INPUT
OUTPUT
5V
90%
I
rl
10%
1/
r
......---O.5~s
IPLH_
1. The pulse generator has the following characteristics:
PAR -1.0 MHz, Zo '" 50 n.
2. CL includes probe and jig capacitance.
3. All diodes are FD777.
90%
3V
1.5 V
~O%1 - - - - - 0 V
--
I_IPHL
v
~.:
OUTPUT _ _ _ _.J
Notes
r"10ns
Figure 13 Switching Times, Each Transistor
(IlA75450 Only)
-1 V
INPUT
10 V
1 kn
+--.....--1-0UTPUT
O.1pF
62
INPUT
son
n
d«
-----.90~~~,~+-------3V
Rl.=500
CL = 15 pF
(Note 2)
OUTPUT-_~=
Notes
1. The pulse generator has the following characteristics:
duty cycle .;; 1%, Zo '" 50 n.
2. CL includes probe and jig capacitance.
9-66
~i'~",~_o_%_______
~-i-
0 V
~_________ ~
I /~10~~~'----
MA75450/60/70 Series
Characteristics Measurement Information (Cant.)
Switching Characteristics
Figure 14 Switching Times of Complete Drivers
INPUT
2.4 V
-I
'OV
INPUT
r-~5 ns
lJtt:~10ns
~1:VI
3V
1.5 V
_10_"'_______.,;,10;. '4;.;."'-I+________
,A75451
p.A75450
p.A75453
0V
---
INPUT
1:: :90:: -'"__0_.5_"
so: 1:lf-~1-0n_s
--3
1.5V
~10~"'~
V
______ OV
0.4 V
Notes
tPLHltc'" VOH
OUTPUT---~~
1. The pulse generator has the following characteristics:
PRR = 1.0 MHz, Zo '" 50 n.
2. When testing IlA75450, connect output Y to transistor base with a
500 n resistor to ground.
3. CL includes probe and jig capacitance.
....._______ 50'" I---VOL
..,;,10~"';;",(
trLH-j
I-
WFOO100F
Figure 15 Latch-up Test of Complete Drivers
Vee = 2OVto 55V
(T.ble 2)
I
rS5n.
V
1
-2r{%
INPUT
'.5
~:~::~
JlA75453
' - -........-..-'OUTPUT
r::,on.
3V
1.5v
'0%
1
.;.:'O%;;;..._ _ _ _ _ _ _ _ _ _.....;;~_r.:_+.
-------0 v
1 - - - - - - -40 ....
' ~_ _ _ _ _~.~I
INPUT:jt.-';,.,t: "":,. .5_n·______...,~=_f_s'_on_.--3V
p.A7S452
10
CL=15pF
(Note 3)
0.4 V
l1t
OUTPUT
Notes
1. The pulse generator has the following characteristics:
PRR = 12.5 kHz, Zo '" 50 n.
2. When testing !lA75450, connect output Y to transistor base with a
500 n resistor from there to ground, and ground the substrate terminal.
3. CL includes probe and jig capacitance.
9-67
1.5 V
~~'·..
"~...;,;;.O%;::..,_ _ _ _'OV
J-lA75491 • J.LA75492
FAIRCHILD
MOS To LED Segment
And Digit Drivers
A Schlumberger Company
Linear Division Interface Products
Description
Connection Diagram
14-Lead DIP
(Top View)
The JJA75491 LED Quad Segment Digit Driver interfaces
MOS signals to common cathode LED displays. High output current capability makes the device ideal for use in
time multiplex systems using the segment address or digit
scan method of driving LEDs to minimize the number of
drivers required.
The JJA75492 Hex LED/Lamp Driver converts MOS signals
to high output currents for LED display digit select or lamp
select. The high output current capability makes this device ideal for use in time multiplex systems using the segment address or digit scan method of driving LEDs to
minimize the number of drivers required.
IE
4E
lC
4C
Yss
GND
1lA75491
• 50 mA Source Or Sink Capability
• Low Input Currents For MOS Compatibility
• Low Standby Power
• Four High Gain Darlington Circuits
2C
3C
2E
3E
IN 3
1lA75492
• 250 mA Sink Capability
• MOS Compatible Inputs
• Low Standby Power
• Six High Gain Darlington Circuits
Order Information
Device Code
Package Code
JJA75491 PC
9A
Package Description
Molded DIP
Connection Diagram
14-Lead DIP
(Top View)
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1,2
Supply Voltage
Input Voltage3
Collector (Output) Voltage 4
Collector (Output) to Input Voltage
Emitter to Ground Voltage
(VI;;;' 5.0 V) JJA75491
Emitter to Input Voltage JJA75491
Continuous Collector Current
JJA75491
JJA75492
Collector Output Current
(all collectors) JJA75492
IN4
INI
-65°C to +150°C
O°C to +70°C
265°C
1.04 W
10 V
-5.0 V to Vss
10 V
10 V
lC
2C
IN2
10 V
5.0 V
GND
50 mA
250 mA
IN3
3C
600 mA
4C
Notes
1. T.J Ma)l' = 150°C.
2. Ratings apply to ambient temperature at 2S'C. Above this temperature,
derate at 8.3 mW/'C.
3. The input is the only device terminal which may be negative with
respect to ground.
4. Voltage values are with respect to network ground terminal unless
Order Information
Device Code
JJA75492PC
otherwise noted.
9-68
Package Code
9A
Package Description
Molded DIP
J.LA75491 • J.LA75492
Equivalent Circuit (1/3 of /lA75492)
Equivalent Circuit (1/2 of /lA75491)
COLLECTOR
IN
-t:
OUT
COLLECTOR
4kn
4kO
IN-_r-'No
___
4.4kO
4.4 kH
IN--P-'Nor-t-I:..
6 kn
7 kU
7 kH
7kn
6 kn
EMITTER
430
430 !l
7kO
n
Vss--4O------+--....
vss-->-----f---f-.....---.,KI--I
GND
OUT
IN
GND
EMITTER
Truth Tables
/lA75492
/lA75491
OUTPUTS
INPUTS
OUTPUTS 1C-6C
L
H
H
L
INPUTS
1E-4E
L
1C-4C
L
H
H
/lA75491
Electrical Characteristics Vss = 10 V, TA =
H
H = HIGH Level, L = LOW Level
L
ooe
to 70 oe, unless otherwise specified.
DC Characteristics
Symbol
VCEL
ICH
Typ
Max
VI = 8.5 V through 1.0 kn,
10L = 50 mA, VE = 5.0 V,
TA = 25°C
Condition
0.9
1.2
V
VI = 8.5 V through 1.0 kn,
10L = 50 mA, VE = 5.0 V
0.9
1.5
V
p.A
Characteristic
LOW Level Collector
to Emitter Voltage
Collector Current HIGH
Min
VCH=10V
VE = 0 V,
VI = 0.7 V
100
VCH = 10 V
VE = 0 V,
II = 40 p.A
100
10L = 20 mA
II
Input Current at Maximum
Input Voltage
VI = 10 V
IER
Reverse Biased
Emitter Current
Ic = 0 V, VI = 0 V, VE = 5.0 V
Iss
Supply Current
9-69
2.0
Unit
3.3
mA
100
p.A
1.0
mA
J,LA75491 • J,LA75492
JlA75491 (Cont.)
Electrical Characteristics
AC Characteristics Vss = 7.5 V, TA = 25°C
Symbol
tpHL
Characteristic
Propagation Delay Time
tpLH
Min
Condition
RL = 200 .11, VIH = 4.5 V
CL = 15 pF, VE = 0 V
Typ
Max
Unit
20
ns
100
ns
J.tA75492
Electrical Characteristics Vss = 10 V, TA = O°C to 70°C, unless otherwise specified.
DC Characteristics
Symbol
VOL
IOH
Characteristic
Output Voltage LOW
Output Current HIGH
II
Input Current at Maximum
Input Voltage
Iss
Supply Current
Typ
Max
VI = 6.5 V through 1.0 kn,
IOL = 250 mA, TA = 25°C
Condition
Min
0.9
1.2
VI = 6.5 V through 1.0 kn,
IOL = 250 mA
0.9
1.5
VOH=10V
11=40 pA
200
VOH=10 V
VI = 0.5 V
200
VI= 10 V
IOL = 20 mA
2.0
Unit
V
JJ.A
3.3
mA
1.0
mA
Max
Unit
AC Characteristics Vss = 7.5 V, TA = 25°C
Symbol
tpHL
Characteristic
Propagation Delay Time
tpLH
Condition
RL = 39 .11, VI = 7.5 V
CL = 15 pF
Test Circuit and Waveforms
7.5 V
PULSE
GENERATOR
(NOTE 1)
1 kH
I--'V"""'-i
>C>--'-_-Vo
Notes
1. The pulse generator has the following characteristics:
PRR - 100 kHz. tw - 1.0 jlS, Zo - 50 n.
2. CL includes probe and jig capacitance.
9-70
Min
Typ
30
ns
300
ns
IlA75491 -IlA75492
Typical Applications
Interfacing Between MOS Calculator Circuit and
LED Multi-Digit Display
This example of time multiplexing the individual digits in a
visible display minimizes display circuitry. Up to twelve dig,
I
I
I
its of a 7-segment display plus decimal point may be displayed using only three J.lA75491 and two J.lA75492
drivers.
'v,
_ _ .1. _ _ _ ,
1.
I
I
~--~-------------------------------,
v,
I
I
RL
I
I
I
[2DF4---
1.
I
I
I
I
I
I
RL
Vss
-,
-------
I
1
I
I
I .A75491
I
QUAD
SEGMENT
I DRIVER
I (3 PACKAGES)
I
I
I
I
I
I
..J
I
I
~A~~
_____ _
"::" GND
II
II
v~
LI
II
I I
I- 0I
I- 0I
I- 0
I
_______ _
I
II
II
~
I
_I
e
I I
II
I_ .I
I
I
-0
--,
J..
I
I
I
011
I,u.A75492
I HEX DIGIT
I
I
I
I
_______ .......J
"::" GND
9-71
?2R~~~~AGES)
IlA9614
Dual Differential
Line Driver
FAIRCHIL.D
A Schlumberger Company
Linear Division Interface Products
Description
Connection Diagram
16-Lead DIP
(Top View)
The pA9614 is a TTL compatible dual differential line driver. It is designed to drive transmission lines either differentially or single ended, back matched or terminated. The
outputs are similar to TIL, with the active pull-up and the
pull-down split and brought out to adjacent leads. This allows multiplex operation (wired-OR) at the driving site in
either the single ended mode via the uncommitted collector, or in the differential mode by use of the active pullups on one side and the uncommitted collectors on the
other (See Applications). The active pull-up is short circuit
protected and offers a low output impedance to allow
back matching. The two pairs of outputs are complementary, providing NAND and AND functions of the inputs and
adding greater flexibility. The input and output levels are
TTL compatible with clamp diodes provided at both input
and output to handle line transients.
ACTive
ACTive
Max
OUTA2
OUTBI
OUTB2
IN Al
ACTIve
PULL-UP 92
INA2
INB3
INA3
INB2
GNO
IN 81
Order Information
Device Code
Package Code
68
68
98
pA9614DM
pA9614DC
pA9614PC
Absolute Maximum Ratings
Note
1. TJ
PUli-UPBl
PULL·UPA2
Single 5.0 V Supply
TTL Compatible Inputs
Output Short Circuit Protection
Input Clamp Diodes
Output Clamp Diodes For Termination Of Line
Transients
• Complementary Outputs For NANDI AND Operation
• Uncommitted Collector Outputs For Wired-OR
Application
• Extended Temperature Range
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
Truth Table
-65°C to + 175°C
-65°C to + 150°C
INPUTS
-55°C to + 125°C
O°C to +70°C
1.50
1.04
-0.7
-0.5
OUT Al
ACTIVE
•
•
•
•
•
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Extended (pA9614M)
Commercial (pA9614C)
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1.2
16L-Ceramic DIP
16L-Molded DIP
Vcc Lead Potential to Ground Lead
Input Voltage
Voltage Supplied to Outputs
(Open Collectors)
Vcc
PULL-UP Al
W
W
V to +7.0 V
V to +5.5 V
-0.5 V to +12 V
-175°C for the Ceramic DIP. and 150°C for the Molded DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 16L·Ceramic DIP at 10 mwrc. and 16L·Molded DIP at
8.3 mwrc.
9-72
OUTPUTS
3
2
1
1
2
L
L
L
H
L
L
L
H
H
L
L
H
L
H
L
L
H
H
H
L
H
L
L
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
H
JlA9614
Equivalent Circuit (112 of circuit)
r-~r-_1r-_1~-----t------~--~--~------t---------_1r-_1~---------t----t-----Vcc
R19
540
Q25
01
+-----i:.Q24
C4
03
R22
4k
ACTIVE
PULL-UP 2-----...--...-----1
R23
10
OUT 2 - - - -......--.
ACTIVE
C3
'-------4~---+----PULL-UP 1
. - - -......--OUT1
R1
R16
4k
1.6k
04
R21
1k
INPUTS
U----------+-------.------'
} b~HER
.;I---==-,7--...~_1~------------------------. DRIVER
GND
Note
All resistor values in ohms.
9-73
J.LA9614
MA9614
Electrical Characteristics Vee = 5.0 V±10%, TA=-55°C to +125°C, unless otherwise specified.
-55°C
Symbol
Characteristic
Condition
Min
+25°C
Max
Min
Typ
Min
400
Max
Unit
400
mV
Output Voltage LOW
10L =40 mA
Vcc = 4.5 V
VOH1
Output Voltage HIGH
10H =-10 mA,
Vec = 4.5 V
2.4
2.4
3.2
2.4
V
IOH = -20 mA,
Vcc=4.5 V
2.0
2.0
2.6
2.0
V
-40
-90
-120
10
100
200
IJ.A
-1.10
-1.60
-1.60
mA
35
60
100
IJ.A
1.3
0.8
0.8
V
los
Output Short Circuit
Current
Vo=O V
Vcc = 5.5 V
ICEX
Output Leakage Current
VCEX = 12.0 V
Vcc = 5.5 V
IlL
Input Current LOW
VI = 0.4 V
Vec = 5.5 V
IIH
Input Current HIGH
VI = 4.5 V
Vec = 5.5 V
VIL
Input Voltage LOW
Vec = 5.5 V
VIH
Input Voltage HIGH
200
Max
VOL
VOH2
400
+ 125°C
-1.60
0.8
2.0
Vcc=4.5 V
2.0
1.5
mA
2.0
-0.8
-1.5
V
V
Voc
Clamp Output
Voltage LOW
lac =-40 mA
Vcc = 5.5 V
Icc
Supply Current
Inputs = 0 V
Vcc = 5.5 V
34
50
mA
IMax
Supply Current
Inputs = 0 V
VMax = 7.0 V
46
65
mA
tpLH
Turn-Off Time
14
20
ns
tpHL
Turn-On Time
CL = 30 pF
Vcc = 5.0 V
(See AC Circuit)
VM = 1.5 V
18
20
ns
VIC
Input Clamp
Diode Voltage
-1.0
-1.5
V
Vcc = 4.5 V
Ilc=-12 mA
9-74
J.lA9614
J1A9614C
Electrical Characteristics Vee = 5.0 V ± 5%, TA =
ooe
to 70
oe,
unless otherwise specified.
25°C
O°C
Symbol
Characteristic
Condition
Min
Max
Min
200
70°C
Max
Min
450
Max
450
Unit
VOL
Output Voltage LOW
10L = 40 mA
Vcc = 4.75 V
VOH1
Output Voltage HIGH
10H =-10 mA,
Vce = 4.75 V
2.4
2.4
3.2
2.4
V
10H = -40 mA,
Vcc = 4.75 V
2.0
2.0
2.6
2.0
V
-40
-90
-120
10
100
200
J.lA
-1.10 -1.60
-1.60
mA
100
JJ.A
0.8
V
VOH2
450
Typ
mV
los
Output Short Circuit
Current
Vo=O V
Vcc = 5.25 V
ICEX
Output Leakage Current
VCEX = 5.25 V
Vcc = 5.25 V
IlL
Input Current LOW
VI = 0.45 V
Vcc = 5.25 V
IIH
Input Current HIGH
VI = 4.5 V
Vcc = 5.25 V
VIL
Input Voltage LOW
Vcc = 5.25 V
VIH
Input Voltage HIGH
Vec = 4.75 V
Voc
Clamp Output
Voltage LOW
loc =-40 mA
Vee = 5.25 V
-0.8
-1.5
Icc
Supply Current
Inputs = 0 V
Vec = 5.25 V
33
50
mA
IMax
Supply Current
Inputs = 0 V
VMax = 7.0 V
46
70
mA
tpLH
Turn-Off Time
14
30
ns
tpHL
Turn-On Time
CL = 30 pF
Vcc = 5.0 V
(See AC Circuit)
VM=1.5 V
18
30
ns
VIC
Input Clamp
Diode Voltage
-1.0
-1.5
V
-1.60
0.8
2.0
Vee = 4.75 V
Ilc=-12 mA
9-75
2.0
35
60
1.3
0.8
1.5
mA
2.0
V
V
MA9614
Typical Performance Curves
Active Pull-Down Output Current
LOW vs Output Voltage LOW
100
.
~
~
60
~
20
~
~
ij'
"
0.1
3.5
t%/'
3.0
!
~
~
40
Logic Levels vs
Ambient Temperature
~
VCC"" 5.5 V
Vee-S.oy
a
o
l~
0
I
i
TA-25"C
Active Pull-Up Output Current
HIGH vs Output Voltage HIGH
2.5
-
VC~=5'0V
-
f-
VdH=NbLd..D
g"
~ 2.0
Vcc-4.SV
"-
~ 1.S
!;
01.0
0.2
0.3
0.4
0.5
0.6
0.7
-100 !--'---;',.;:"O-'--::'::--"--:3"'.0,--'----,J4.0
0.5
VOL
o
I
-80
20
OUTPUT VOLTAGE LOW-V
so
140
Supply Current vs
Operating Frequency
Supply Current vs
Temperature
80
I
20
AMBIENT TEMPERATURE- C C
OUTPUT VOLTAGE HIGH- V
Supply Current vs
Supply Voltage
0
at IOL 40mA
40
NO LOAD
TA""25"C
vcJ=5.!V
//
0
I
vcc=toy_
CL=30pF
OUTPUTS OPEN
80
~ 35
I
II
~~
~
0
o
ft,;::f-'
1.0
0
20
so
140
o
5.0
10
3.0
-
Vcc-S.5V
Vee = 5.0 V
Vcc-- 4.5 V
2.0
1.01---1--+-"--+--+-+--1
o
100
AMBIENT TEMPERATURE- "C
4.0
>
T -55"C
~
Z
0
efi
li'
0
TA
>
S
2.0
5.0r--r--,--.,--Y--,r--r--,
5.0
30
1.0
Transfer Characteristics vs
Supply Voltage
T -125"C
!
I
0.5
FREQUENCY-MHz
Transfer Characteristics vs
Temperature
40
0.2
0.5
1.0
1.5
2.0
2.5
INPUT VOLTAGE-V
9-76
3.0
3.5
°0~~0.~S"1~.0~!'~.S'-~2~.o'-~2~.S-~3.~0-~3.5
INPUT VOLTAGE-V
MA9614
AC Test Circuit and Waveforms
Vee
Vee
I
I
I
H'PLH
_%_(_A)__
IPHL
-J~rM------------~
Input Pulse
Frequency ~ 500 kHz
Amplitude ~ 3.0 ±0.1 V
Pulse Width ~ 110 ± 10 ns
tr =tf<5.0 ns
Typical Applications
Differential Mode Expansion Multiplex Operation
1-1-..--------TWISTEO.PAIR
p
10
I
LlNE---------.j~
SHIELD DR COMMON GROUND CONNECTION
11
Only one driver is enabled at one time
Expand by tying NAND active pull-down outputs together and by tying AND
active pull~up outputs together. The drivers can be inhibited by taking one
input to ground.
9-77
100"
4 3
MA9614
Typical Applications (Cont.)
Simplex -
Differential Operation
5:~VCC"'16~ I·____T_W_'S_~...,~_~_P_AI_R_I
t
i
1
42
1I2.A9614
DATA
INPUTS
__
£
SHIELD OR COMMON GROUND
CONNECTION
P
See pA9615 data sheet for operation of pA9615
Typical Reflection Diagram
200
1M
2
vJc s.Jv
TA=25"C
A:o~ S~A.Je du}pu~ DLvl~E
120
CHARACTERISTICS
i-"
/
f
/
HIGH STATE OUTPUT DEVICE
iiiTEt'y',S
-200
-
I I I
I
-2
_I - -
_ _ _ _I t > r . ; v c c
T
3
10
OUTPUT VOLTAGE-V
See pA9621 data sheet for usage of reflection diagram
9-78
2
1I~9615r.=oC OATA
7
1
OUTPUT
6
£
4
3
see 9615 DATA SHEET FOR OPERATION OF 9615
iL A9615
Dual Differential
Line Receiver
FAIRCHILD
A Schlumberger Company
Linear Division Interface Products
Description
Connection Diagram
16-Lead DIP
(Top View)
The MA9615 is a dual differential line receiver designed to
receive differential digital data from transmission lines and
operate over the extended and industrial temperature
ranges using a single 5.0 V supply. It can receive differential data in the presence of high level (± 15 V) common
mode voltages and deliver undisturbed TTL logic to the
output.
OUT A
ACTIVE 2
PULL-UP A 3
STROBE A
RESPA
The response time can be controlled by use of an external capacitor. A strobe and a 130 Q terminating resistor
are provided at the inputs. The output has an uncommitted collector with an active pull-up available on an adjacent lead to allow either wired-OR or active pull-up TTL
output configuration.
+INA
RA
-INA
GNO
• TTL Compatible Output
• High Common Mode Voltage Range
• Choice Of An Uncommitted Collector Or Active
Pull-Up
• Strobe
• Extended Temperature Range
• Single 5_0 V Supply Voltages
• Frequency Response Control
• 130 Q Terminating Resistor
Order Information
Device Code
MA9615DM
MA9615DC
MA9615PC
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Extended (MA9615M)
Commercial (MA9615C)
Lead Temperature
Ceramic DIP (soldering. 60 s)
Molded DIP (soldering. 10 s)
Internal Power Dissipation 1,2
16L-Ceramic DIP
16L-Molded DIP
Vcc Lead Potential to Ground Lead
Input Voltage Referred to Ground
Voltage Applied to Outputs for High
Output State without Active Pull-up
Voltage Applied to Strobe
-65°C to + 175°C
-65°C to + 150°C
-55°C to + 125°C
O°C to +70°C
1.50
1.04
-0.5
±20
-INB
W
W
V to +7.0 V
V
-0.5 V to +13.2 V
-0.5 V to +5.5 V
Note
1. TJ M., ~ 175°C for the Ceramic DIP, and 150°C for the Molded DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 16L·Ceramic DIP at 10 mW
and the 16L·Molded DIP at
8.3 mW/oC.
rc,
9-79
Package Code
68
68
98
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
tLA9615
Equivalent Circuit (1/2 of Circuit)
Vee
RESP
STROBE
R1B
R4
R11
R5
1.64 kO
1.skU
1.64kH
R22
2.0 k!l
1.8kn
R19
R24
80 n
013
900n
R
Rl
13011
R2
R3
8.36 k!~
8.36 ktl
ACTIVE
PULL·UP
+IN
r--------,
I Vee
I
I
I
I
I
I
-IN
R7
7.0k!!
R6
7.0kH
R1S
2.5 kH
Rl'
2.5 kO
R27
3.0 k!l
R16
R17
soon
500!!
L,
Q15
RB
3000
Rl0
132 il
R9
lOOn
GND
R25
100 !l
R29
10 k!!
OUT
R20
2.5 ktl
R28
100 III
I _______
L
02
R26
90!!
I
I
..JI
- - - = COMMON TO BOTH CHANNELS
9·80
TO
OTHER
RECEIVER
R21
1.0 kn
-=
-=
MA9615
MA9615
Electrical Characteristics Vee = 5.0 V ± 10%, TA = -55°C to
+ 125°C, unless otherwise specified.
T = -55°C
Symbol
Characteristic
Condition 1
VOL
Output Voltage LOW
Vee = 4.5 V,
Va = (Note 2),
10L = 15.0 rnA,
VOIFF = 0.5 V
VOH
Output Voltage HIGH
Vee = 4.5 V,
Va = (Note 2),
10H = -5.0 rnA,
VOIFF = -0.5 V
leEx
Output Leakage
Current
Vee = 4.5 V,
VeEx = 12 V,
VOIFF = Vee
los
Output Short Circuit
Current
Vee = 5.5 V,
Vos=O V2 ,
VOIFF = -0.5 V
II
Input Current
Vee = 5.5 V,
VI = 0.4 V,
Other input = 5.5 V
II(ST)
Strobe Input Current
Vee=5.5 V,
VI = 0.4 V,
VOIFF = 0.5 V
II(R.C)
Response Control
Input Current
Vee = 5.5 V,
VI(R.e) = 0.4 V,
VOIFF = 0.5 V
VeM
Common Mode
Voltage
Vee = 5.0 V,
VOIFF = 1.0 V
IR(ST)
Strobe Input
Leakage Current
Vee = 4.5 V,
VR = 4.5 V,
VOIFF = -0.5 V
RI
Input Resistance
Vee = 5.0 V,
VI(R) = 1.0 V,
+ Input = GND
VTH
Differential Input
Threshold Voltage 3
Vee = 5.0 V
VeM =0 V
Min
Max
T= 25°C
Min
0.40
2.2
Typ
0.18
2.4
T = +125°C
Max
Min
0.40
3.2
-0.9
-15
Vee = 5.0 V ± 10%,
-15 V
2.0
0
1.0
~
-1--~0V'
~:!:~
~
~ 3.0
II
t:
<
~
o
I!::>
-0.2
-20
-10
-
>
I
w
"~
>
...:>
•
I!::>
S:
0
Vee
I
V'~-
-
3.0
>'
r-
;:;-
>' >',
"~
OJ
OJ
~-
j$
3.0
I!::>
o
o
0.2
~
2.0
Vee 1o 5.5
o
-=-
4.0
v
Vee
5.0
Vee
4.5 V
2.0
3.0
~
I
"eI
...Z
!L
I
2.0
/
a:
a:
.....
-4.0
VOIFF "" 2.0 V
\1
vcc;ov
5.0
0
5.0
15
COMMON MODE VOLTAGE - V
9-84
V
I'
;:;
15
/
:>
0
VDIFF .,.., - 2.0 V
:> -2.0
25
4.0
Vee 5.0 V
UNTESTED INPUT ~ 0 V
TA = 25°C
w
o
4.0
'I
1.0
TA = 25<>C
1.0
3.0
~
Input Current vs Input Voltage
o
STROBE INPUT VOLTAGE - V
c
STROBE INPUT VOLTAGE - V
6.0
ve~ - 5!5 V
8J
2.0
OA
I!::>
" " "
1.0
0.2
3.0
~ 2.0
>' ;;' >'
" " "
~
<>
0
o
g
1\
2.0
140
100
1.0
--
w
"
l"\
1.0
60
20
Vee - 5.0
Vee0 4.5V
0
...:>>
8J
" " "
2.0
4.0
0
0
TA ° 1250c
5.0
>
I 4.0
w
4.0
>
I
3.0
20
0.5 V
6.0
I Vee
'.
5.0
~ 5.0 V
r-...
i--
4.5 V
15 rnA
IOl
VOfFF
Strobe Input/Output Transfer
Characteristics vs Vee
Output Voltage vs
Common Mode Voltage
5.0
-
(vee
1-
INPUT VOLTAGE - V
6.0
...:>>
....:>
I
5.0
-0.4
0.2
Strobe Input/Output Transfer
Characteristic vs Ambient
Temperature
0
-50
o
0.1
VOL
AMBIENT TEMPERATURE -
~
INPUT VOLTAGE - V
"~
-40
-30
6.0
0
- 0.1
1.0
0
60
1.0
o
1.5
0.5 -
o
o
1.0
>
I
w 4.0
2.0
~
g
5
Vee l 5.0
o ~,
II
2.5
f
w
=
VOIFF '" 0.5 V
OUTPUT CURRENT HIGH - rnA
~~
0
-
a
-fI4.5 V
-~ HVOH
IOH 5.0 rnA
~
!:;
Input/Output Transfer
Characteristics vs Temperature
TA""25"C
I.....
I
r- I-- ~e~s.sv
"fw r--..
"~
20
V'~-
I
2.0
3.0
>
7.0
>
_
~
I I I v~e
-.,
~ 4.0
~ o
I
:z:
mA
Input/Output Transfer
Characteristics vs Vee
6.0
>
I'-...
4.0
3.0
Vee - 5.5 V
I
TA = 2S"C
TA _125°C
o
Output Voltage HIGH vs
Ambient Temperature
Output Voltage HIGH vs
Output Current HIGH
25
-6.0
-25
/
/
-15
-5.0
0
5.0
INPUT VOLTAGE - V
15
25
MA9615
Typical Performance Curves for IlA9615 and IlA9615C (Cont.)
70
WITL AcJVE PU~L-UP I
...
15
'"'"
u
:>
\
40
-INPUTS"" 0
.~
~
10
o
o
V
1.0
V
v
I
Z
V
70
60
60
50
so
Vee"" S.OV
Vj=-3VT03V
..~
40
':>"
u 30
~SS-oV
/
o. 20
:>
..e
.....'"
\<. .V
30
70
TA "" 25°C
60 r-CONNECTEO TO ACTIV.
PULL-oOiN\ ONLY
I
E 50
+
INPUTS = Vee
I
.
Switching Time vs
Ambient Temperature
Supply Current vs
Ambient Temperature
Supply Current vs Supply Voltage
Vee
~
o.
o.
il
- INjUTS .., Vee
+
20
S.sy- -
INPU~
Jee
rpur =o,v
0
";:
--
~
-
......
30
20
1
Cl=30~
40
Z
-
IPL~
RL=3.9kn
V
I---V V
..-
.L -
V
tpHL
RL=390n-
[L 0130
p]
-
10
10
WITH REilsTORI PULL-r p
o
2.0
3.0
4.0
5.0
SUPPLY VOLTAGE -
6.0
-60
7.0
-20
0
20
60
-20
140
100
TEMPERATURE _ cC
V
0
20
60
100
TEMPERATURE _ °C
Switching Time Test Circuit and Waveforms (Note 1)
Figure 1
~+3.0V
Vee
~~
V,
)0----<....--1-.....- Vo
v,
~-UV
.:~\r f:~~;;
RL
~
_ _ _ _~'.5V
STROBE
Note
1. Use V, or
Vi.
ground other input.
Figure 2
+INA=t>---o-INA
OUT A
-
Notes
1. For tpHL measurement RL = 390 n
2. For tpHL measurement RL ~ 3.9 kn
3. For input pulse: Width ~ 100 ns ± 10 ns,
t r• tf =
5.0 ns
PRR ~ 500 kHz
4. CL = 30 pF including probe and jig capacitance
5. Response control open, maximum scocket capacitance = 5.0 pF
<
VERTICAL"" 2.0 VlOIV. HORIZONTAL = 50 ns/DlV.
Photograph of a !lA9615 switching differential data in the presence of
high common mode noise.
9-85
140
J1A9615
Typical Applications
Figure 3 Standard Usage
DRIVER SYSTEM
RECEIVER SYSTEM
LINE
....:;..=~....I=:::j:==<'l==:::j:~....
....
Figure 4
H
_"A_9_61_5_...
Frequency Response Control
Frequency Response as a
Function of Capacitance
-t>---t-o-
10M
~~~~J
CONTROL PIN
TTL LOGIC
vc~H.hv
TA = 25°C
100M
CR
N
:r
I 100K
>-
"zw
::>
0
Notes
w
CR > 0.01 p.F may cause slowing of rise and fall times of the output.
Due to the mechanism of induction of differential noise, the
use of the response control is not normally needed.
10 K
0:
"-
to
K
100
0.001
.....
0.01
0.1
CAPACITANCE -
9-86
1.0
MF
10
MA96172· MA96174
FAIRCHILO
Quad Differential
Line Drivers
A Schlumberger Company
Linear Division Interface Products
Connection Diagram
16-Lead DIP
(Top View)
Description
The pA96172 and pA96174 are high speed quad differential line drivers designed to meet EIA Standard RS-485.
The devices have three-state outputs and are optimized
for balanced multipoint data bus transmission at rates up
to 10 Mbps. The drivers have wide positive and negative
common mode range for multipoint applications in noisy
environments. Positive and negative current-limiting is provided which protects the drivers from line fault conditions
over a + 12 V to -7.0 V common mode range. A thermal
shutdown feature is also provided and occurs at junction
temperature of approximately 160°C. The pA96172 features an active high and active low Enable, common to all
four drivers. The pA96174 features separate active high
Enables for each driver pair. Compatible RS;485 receivers,
transceivers, and repeaters are also offered by Fairchild
and are designed to provide optimum bus performance.
The respective device types are pA96173/96175,
pA96176, and pA96177 /96178.
IIA96172
•
•
•
•
•
•
Meets EIA Standard RS-485 And RS-422A
Monotonic Differential Output Switching
Transmission Rate To 10 Mbs
Three-State Outputs
Designed For Multipoint Bus Transmission
Common Mode Output Voltage Range: -7.0 V To
+12 V
• Operates From Single + 5.0 V Supply
• Thermal Shutdown Protection
• pA96172196174 Are Lead And Function Compatible
with the SN75172175174 or the AM26LS31/MC3487
respectively
•
I'A96174
Function Table (Each Driver) J.LA96172
Input
A
H
L
H
L
X
Enables
Outputs
E
E
y
Z
H
H
X
X
L
X
X
L
L
H
H
L
H
L
L
H
L
H
Z
Z
Order Information
Device Code
pA96172DC
pA96172PC
pA96174DC
pA96174PC
Function Table (Each Driver) J.LA96174
Outputs
Input
Enable
Y
Z
H
L
X
H
H
L
H
L
Z
L
H
Z
H - High Level
L = Low Level
X = Immaterial
Z - High Impedance (off)
9-87
Package Code
78
98
78
98
Package Description
Ceramic DIP
Molded DIP
Ceramic DIP
Molded DIP
~96172· ~96174
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation l , 2
16L-Ceramic DIP
16L-Molded DIP
Supply Voltage3
Enable Input Voltage
-65·C to + 175·C
-65·C to +150·C
O·C to +70·C
300·C
265·C
1.50 W
1.04 W
7.0 V
5.5 V
Note.
1. TJ Max = 150'C for the Molded DIP, and 17S'C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 2S'C. Above this temperature,
derate the 16L·Ceramic DIP at 10 mW/'C, and the 16L·Molded DIP at
8.3 mWI'C,
3. All voltages are with respect to network ground terminal.
Recommended Operating Conditions
Symbol
Min
Characteristic
4.75
Supply Voltage
Vcc
Typ
5.0
-7.01
Max
Unit
5.25
V
+ 12.0
V
Voc
Common Mode Output Voltage
IOH
Output Current HIGH
-60
mA
IOL
Output Current LOW
60
mA
TA
Operating Temperature
70
·C
0
25
Note
1. The algebraic convention, where tha less positive (more negative) limit is
deSignated minimum, is used in this data sheet for common moda input
voltage and threshold voltage levels only.
1lA96172, 1lA96174
Electrical Characteristics Over recommended temperature and supply voltage ranges, unless otherwise
specified.
Symbol
Condition
Characteristic
Min
Typl
2.0
Input Voltage HIGH
Input Voltage LOW
VOH
Output Voltage HIGH
IOH=-20mA
3.1
VOL
Output Voltage LOW
IOL =20mA
0.8
VIC
Input Clamp Voltage
11=-18 mA
IVODll
Differential Output Voltage
10=0 mA
IVOD21
Differential Output Voltage
RL = 54 n, Fig. 1a
RL = 100 n, Fig. 1b
Change in Magnitude of Differential
Output Voltage 2
0.8
RL = 54 nor 100 n, Fig. 1b
9-88
V
V
V
-1.5
6.0
1.5
2.0
Unit
V
VIH
VIL
.lIVODI
Max
V
V
V
2.0
2.3
V
±0.2
V
MA96172· MA96174
~96172, ~96174
(Cont.)
Electrical Characteristics Over recommended temperature and supply voltage ranges, unless otherwise
specified.
Symbol
Characteristic
Condition
Voc
Common Mode Output Voltage3
AIVocl
Change in Magnitude of Common Mode
Output Voltage2
10
Output Current with Power off
Vcc=O V, Vo=-7.0 V to 12 V
loz
High Impedance State Output Current
Vo=-7.0 V to 12 V
IIH
Input Current HIGH
Min
Typl
Max
Unit
3.0
V
±0.2
V
± 100
pA
±200
pA
VI = 2.7 V
20
pA
±50
IlL
Input Current LOW
VI =0.5 V
-100
pA
los
Short Circuit Output Current
Vo=-7.0V
-250
mA
Vo=O V
-150
Icc
Vo=Vcc
150
Vo= 12 V
250
Supply Current (all drivers)
I Outputs Enabled
I Outputs Disabled
No load
50
70
50
60
mA
Switching Characteristics Vee = 5.0 V, TA = 25°C
Symbol
Characteristic
too
Differential Output Delay Time
Condition
Typ
Max
Unit
15
25
ns
15
25
ns
12
20
ns
12
20
ns
Fig. 4
30
45
ns
Fig. 5
30
45
ns
Fig. 4
25
35
ns
Fig. 5
30
45
ns
RL = 60
n,
Fig. 2
RL = 27
n,
Fig. 3
tTO
Differential Output Transition Time
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time, High-to-Low
Level Output
tPZH
Output Enable Time to High Level
RL = 110
tPZL
Output Enable Time to Low Level
RL = 110
tpHZ
Output Disable Time from High Level
RL = 110
tpLZ
Output Disable Time from Low Level
RL = 110
Notes
1. All typical values are Vee = 5.0 V and TA = 25°C.
2. '" IVool and "'IVael are the changes in magnitude of Voo and Voe
respectively, that occur when the input is changed from a high level to
a low level.
3. In EIA Standard RS-422A and RS·485, Vae, which is the average of the
two output voltages with respect to ground, is called output offset
voltages, Vas.
9-89
n,
n,
n,
n,
Min
J,tA96172· J,tA96174
Parameter Measurement Information
Figure 1a Differential Output Voltage with Varying
Common Mode Voltage
Figure 1b Differential and Common Mode Output
Voltage
3750
_~~+f~···
-=-
(NoIe31
CROOe21F
Figure 2 Differential Output Delay and Transition Times
Figure 3 Propagation Delay Times
,-------~-----3V
2.3Y
IN
r----------l
I
I
GENERATOR
~11
500
OV
RL-270
~>tI~~~1:
OUT
I:
y
OUT
1
_
IL________ I
IY
-=-
e::.::
z
OUT
~
1J>i.H
2.3V
VOL
YOH
2.3V
--YOL
Figure 4 tPZH and tpHZ
, -______,--------3V
IN
,-__
GENERATOR
+-~--L-
VOH
OUT
~11
VOFF:::OV
CR0C871F
9-90
MA96172· MA96174
Parameter Measurement Information (Cant.)
Figure 5
tPZL
and
tpLZ
5V
r---------l
11&.-11011
'I,I
......>-:1~~:>----,.J:'-'our
OVor 3V -+----1
"Ji '~:
.-.~-:-'V
r-------~-_r~!-~~
5V
I
Il __________ JI
GENERATOR
SOil
(N.... 1)
our
2.3V
tVOI.
-=
O.5V
3V
(Note 4)
Notes
I. The input pulse is supplied by a generator having the following
characteristics: PRR = 1.0 MHz, duty cycle = 50%, t,"; 5.0 ns,
t, ..; 5.0 ns, Zo - 50 fl.
2. CL includes probe and jig capacitance.
3. !lA96172 with active high and active low Enables is shown here.
!lA96174 has active high Enable only.
4. To test the aclive low Enable E of !lA96172, ground E and apply an
inverted waveform to E. !lA96174 has active high Enable only.
Typical Application
1/41/A18172
~~--~--~----~-----------------------~----~~----~,
~~~;--+~--+---------------------+-~~-;~--~
1/4pA861n
1/411A98175
UP TO 32
ORIVER/RECEIVER
PAIRS
AFOO13OF
Note
The line length should be terminated at both ends in its characteristic
impedance.
Stub lengths off the main line should be kept as short as possible.
9-91
J.lA96173 • J.lA96175
Quad Differential
Line Receivers
FAIRCHILD
A Schlumberger Company
Linear Division Interface Products
Description
Connection Diagram
16-Lead DIP
(Top View)
The 1lA96173 and 1lA96175 are high speed quad differential line receivers designed to meet EIA Standard RS-485.
The devices have three-state outputs and are optimized
for balanced multipoint data bus transmission at rates up
to 10 Mbps. The receivers feature high input impedance,
input hysteresis for increased noise immunity, and input
sensitivity of 200 mV over a common mode input voltage
range of -12 V to +12 V. The receivers are therefore
suitable for multipoint applications in noisy environments.
The 1lA96173 features an active high and active low Enable, common to all four receivers. The 1lA96175 features
separate active high Enables for each receiver pair. Compatible RS-485 drivers, transceivers, and repeaters are also
offered by Fairchild and are designed to provide optimum
bus performance. The respective device types are
1lA96172/96174, 1lA96176 and 1lA96177/96178.
•
•
•
•
•
•
•
•
•
•
"A98173
Meets EIA Stsndard RS-485, RS-422A, RS-423A
Designed For Multipoint Bus Applications
Three-State Outputs
Common Mode Input Voltage Range: -12 V To
+12 V
Operates From Single + 5.0 V Supply
Input Sensitivity Of ± 200 mV Over Common Mode
Range
Input Hysteresis Of 50 mV Typical
High Input Impedance
Fall-Safe Input/Output Features Drive Output HIGH
When Input Is Open
1lA96173/96175 Are Lead And Function Compatible
With SN75173175175 Or The AM26LS32/MC3486
Respectively.
I'A98175
Function Table (Each Receiver) 1oIA96173
Differential Inputs
A-B
Enables
Outputs
E
E
V
H
X
X
L
H
H
-0.2 V < VIO < 0.2 V
H
X
X
L
?
?
Vlo<-0.2 V
H
X
X
L
L
L
X
L
H
Z
VIO
> 0.2
V
Order Information
Device Code
Package Code
1lA96173DC
1lA96173PC
1lA96175DC
1lA96175PC
78
98
78
98
Package Description
Ceramic DIP
Molded DIP
Ceramic DIP
Molded DIP
Function Table (Each Receiver) 1oIA96175
H = High Level
L- Low Level
? - Indeterminate
X - Immaterial
Z = High Impedance (off)
9-92
Differential Inputs
A-B
Enable
Output
y
Vlo;;;'0.2 V
H
H
-0.2 V < VIC < 0.2 V
H
?
Vlo";;-0.2 V
H
L
X
L
Z
MA96173· MA96175
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1,2
16L-Ceramic DIP
16L-Molded DIP
Supply Voltage3
Input Voltage, A or B Inputs
Differential Input Voltage
Enable Input Voltage
Low Level Output Current
-65°C to + 175°C
-65°C to + 150°C
O°C to +70°C
300°C
265°C
1.50 W
1.04 W
7.0 V
±25 V
±25 V
7.0 V
50 mA
•
Notes
2.
TJ Me> ~ 150·C for the Molded DIP, and 17S·C for the Ceramic DIP.
Ratings apply to ambient temperature at 2S·C. Above this temperature,
derate the 16l-Ceramic DIP at 10 mWrC, and the 16l-Molded DIP at
3.
All voltages are with respect to network ground terminal.
1.
8.3 mWrC.
Recommended Operating Conditions
Max
Unit
5.25
V
Common Mode Input Voltage
_12 1
+12
V
Differential Input Voltage2
-12
+12
V
-400
p.A
16
mA
70
°C
Symbol
Min
Characteristic
Supply Voltage
4.75
VCM
VID
Vcc
10H
Output Current HIGH
10l
Output Current LOW
TA
Operating Temperature
0
Typ
5.0
25
Notes
1. The algebraic convention, where the less positive (more negative) limit is
designated minimum, is used in this data sheet for common mode input
voltage and threshold voltage levels only.
2. Differential input! output bus voltage is measured at the noninverting
terminal A with respect to the inverting terminal B.
J,lA96173, J,lA96175
Electrical Characteristics Over recommended temperature, common mode input voltage, and supply voltage
ranges, unless otherwise specified.
Symbol
Characteristic
Condition
VTH
Differential-Input
High Threshold Voltage
Vo = 2.7 V, 10 = -0.4 mA
VTL
Differential-Input
Low Threshold Voltage
Vo = 0.5 V, 10 = 16 mA
VT+ -VT_
Hysteresis3
VCM =0 V
VIH
Enable Input Voltage HIGH
Min
Max
0.2
_0.2 2
Unit
V
V
50
2.0
9-93
Typl
mV
V
MA96173· MA96175
J,lA96173, J,lA96175 (Cont.)
Electrical Characteristics Over recommended temperature, common mode input voltage, and supply voltage
ranges, unless otherwise specified.
Symbol
Characteristic
Condition
VIL
Enable Input Voltage LOW
VIC
Enable Input Clamp Voltage
VOH
Output Voltage HIGH
VIO= 200 mY, 10H = -400 IlA
VOL
Output Voltage LOW
Vlo=-200 mV
Min
Typl
11=-18mA
Max
Unit
0.8
V
-1.5
V
2.7
V
IIOL = 8.0 mA
0.45
V
110L = 16 mA
0.50
loz
High-Impedance State Output
Vo = 0.4 V to 2.4 V
II
Line Input Current4
Other Input = 0 V
I
I
VI = 12 V
±20
IlA
1.0
mA
-0.8
VI = -7.0 V
IIH
Enable Input Current HIGH
VIH = 2.7 V
20
IlL
Enable Input Current LOW
VIL = 0.4 V
-100
AI
Input Aesistance
los
Short Circuit Output Current
Icc
Supply Current
!1A
k.l1
12
-15
IlA
-85
mA
75
mA
Typ
Max
Unit
15
25
ns
15
25
ns
22
ns
Outputs Disabled
Switching Characteristics Vcc = 5.0 V, T A = 25°C
Symbol
Characteristic
Condition
VIO = -2.5 V to 2.5 V,
CL = 15 pF, Fig. 1
Min
tpLH
Propagation Delay Time,
Low to High Level Output
tpHL
Propagation Delay Time,
High to Low Level Output
tpZH
Output Enable Time to High Level
CL = 15 pF, Fig. 2
15
tPZL
Output Enable Time to Low Level
CL = 15 pF, Fig. 3
15
22
ns
tpHZ
Output Disable Time from High Level
CL = 5.0 pF, Fig. 2
14
30
ns
tpLZ
Output Disable Time from Low Level
CL = 5.0 pF, Fig. 3
24
40
ns
Notes
1. All Typical values are at Vee - 5.0 V, TA - 25°C.
2. The algebraic convention, where the less positive (more negative) limit is
designated minimum, is used in this data sheet for common mode input
voltage and threshold voltage levels only.
3. Hysteresis is the difference between the positive-going input threshold
voltage, VT+. and the negative·going input threshold voltage. V-r-.
4. Refer to EIA standard RS·485 for exact conditions.
9-94
J.LA96173· J.LA96175
Parameter Measurement Information
Figure 1 tpLH. tpHL (Note 3)
>--:----,-- OUT
IN
:1" }s;-
U'
-2.5V
L
~
----VOH
OUT
1.3V
1.3V
VOL
CA00891F
Figure 2 tpHZ. tPZH (Note 3)
CR00901F
Figure 3 tPZL. tpLZ (Note 3)
Vee
Notes
1. The inpul pulse is supplied by a generalor having Ihe following
characterislics: PRR - 1.0 MHz, 50% duty cycle, t,..;;; 6.0 ns, If';;; 6.0 ns,
Zo=50n.
2. CL includes probe and jig capacilance.
3. pA96173 wilh active high and aclive low Enables is shown here.
pA96175 has active high Enable only.
4. All diodes are 1N916 or equivalent.
5. To lesl the active low Enable E of pA96173, ground E and apply an
inverted inpul waveform to E. pA96175 has active high Enable only.
9-95
MA96173· MA96175
Typical Application
114..-74
114..-72
~----r-~--~---------------------T---~~r---~
~~-r+-~~~r--------------------+--r-+~~--~
114jJA96175
114pA81173
UP TO 32
DRIVERlRECEIVER
PAIRS
Note
The line length should be terminated at both ends in its characteristic impedance.
Stub lengths off the main line should be kept as short as possible.
9-96
J.lA96176
FAIRCHIL.D
Differential Bus Transceiver
A Schlumberger Company
Linear Division Interface Products
Description
Connection Diagram
8-Lead DIP
(Top View)
The J.lA96176 Differential Bus Transceiver is a monolithic
integrated circuit designed for bidirectional data communication on balanced multipoint bus transmission lines. The
transceiver meets EIA Standard RS-485 as well as
RS-422A.
7 B} IN/OUT
The J.lA96176 combines a three-state differential line driver
and a differential input line receiver, both of which operate
from a single 5.0 V power supply. The driver and receiver
have an active Enable that can be externally connected to
function as a direction control. The driver differential outputs and the receiver differential inputs are internally connected to form differential input/output (I/O) bus ports that
are designed to offer minimum loading to the bus whenever the driver is disabled or when Vee = 0 V. These ports
feature wide positive and negative common mode voltage
ranges making the device suitable for multipoint applications in noisy environments.
6
Package Code
Package Description
6T
9T
Ceramic DIP
Molded DIP
Function Table (Driver)
Differential
Inputs
The J.lA96176 can be used in transmission line applications
employing the J.LA96172 and the J.LA96174 quad differential
line drivers and the J.LA96173 and J.lA96175 quad differential line receivers.
•
•
•
•
•
•
•
•
BUS PORT
Order Information
Device Code
J.LA96176RC
J.LA96176TC
The driver is designed to handle loads up to 60 mA of
sink or source current. The driver features positive and
negative current-limiting a.nd thermal shutdown for protection from line fault conditions. Thermal shutdown is designed to occur at junction temperature of approximately
160°C. The receiver features a typical input impedance of
12 kn, an input sensitivity of ± 200 mV, and a typical input hysteresis of 50 mY.
•
•
•
•
•
•
A
Outputs
D
Enable
DE
A
B
H
L
X
H
H
L
H
L
Z
L
H
Z
Function Table (Receiver)
Bidirectional Transceiver
Meets EIA Standard RS-422A And RS-485
Designed For Multipoint Transmission
Three-State Driver And Receiver Enables
Individual Driver And Receiver Enables
Wide Positive And Negative Input/Output Bus
Voltage Ranges
Driver Output Capability ± 60mA Maximum
Thermal Shutdown Protection
Driver Positive And Negative Current-Limiting
High Impedance Receiver Input
Receiver Input Sensitivity Of ± 200 mV
Receiver Input Hysteresis Of 50 mV Typical
Operates From Single 5.0 V Supply
Low Power Requirements
Differential Inputs
A-B
Enable
RE
Output
VID;;;'0.2 V
-0.2 V < VID < 0.2 V
VID<-0.2 V
X
L
L
L
H
H
?
L
H = High Level
L = Low Level
? = Indeterminate
X = Immaterial
Z = High Impedance (off)
9-97
R
Z
MA96176
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1, 2
8L-Ceramic DIP
8L-Molded DIP
Supply Voltage 3
Differential Input Voltage
Enable Input Voltage
Notes
1. TJ Max
~
-65°C to + 175°C
-65°C to + 150°C
O°C to +70°C
1.30 W
0.93 W
7.0 V
±25 V
5.5 V
150·C for the Molded DIP, and 175·C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 8L-Ceramic DIP at 8.7 mWrC, and the 8L-Molded DIP at
7.5 mwrc.
1. All voltage values, except differential input/output bus voltage, are with
respect to network ground terminal.
Recommended Operating Conditions
Symbol
VCC
Characteristic
Supply Voltage
Min
Typ
Max
Unit
4.75
5.0
5.25
V
12
V
_7.0 1
VI or VCM
Voltage at any Bus Terminal (Separately or Common Mode)
VID
Differential Input Voltage 2
±12
V
IOH
Output Current HIGH
-60
mA
IOL
Output Current LOW
TA
Operating Temperature
Driver
Receiver
Driver
Receiver
voltage and threshold voltage levels only.
2. Differential input! output bus voltage is measured at the noninverting
terminal A with respect to the inverting terminal B.
9-98
J.LA
60
mA
16
0
Notes
1. The algebraic convention, where the less positive (more negative) limit is
designated minimum, is used in this data sheet for common mode input
-400
25
70
°C
J.lA96176
I.lA96176
Electrical Characteristics Over recommended temperature, common mode input voltage, and supply voltage
ranges, unless otherwise specified.
Driver Section
Symbol
VIH
Characteristic
Condition
Input Voltage HIGH
Min
Typ1
Max
2.0
V
Vil
Input Voltage LOW
VOH
Output Voltage HIGH
IOH =-20mA
VOL
Output Voltage LOW
10l =20mA
VIC
Input Clamp Voltage
11=-18 mA
IVOD11
Differential Output Voltage
10= 0 mA
IVOD21
Differential Output Voltage
Rl = 100
2.0
2.25
Rl = 54
1.5
2.0
"'IVODI
Change in Magnitude of
Differential Output Voltage 2
Voc
Common Mode Output Voltage3
"'IVocl
Change in Magnitude of
Common Mode Output Voltage 2
10
Output Current4
(Includes Receiver II)
Output Disabled
Input Current HIGH
VI = 2.4 V
20
IIH
0.8
Rl = 54
n
V
0.85
V
6.0
or 100
n,
Fig. 1
IVo=12V
IVo = -7.0
V
3.1
-1.5
n, Fig. 1
n, Fig. 2
Unit
V
V
V
±0.2
V
3.0
V
±0.2
V
1.0
mA
-0.8
J.l.A
III
Input Current LOW
VI =0.4 V
-100
JJ.A
los
Short Circuit Output Current
Vo=-7.0V
-250
mA
Vo=O V
-150
Icc
Supply Current
Vo=Vcc
150
Vo = 12 V
250
I Outputs Enabled
I Outputs Disabled
No Load
9-99
35
40
mA
•
MA96176
~A96176 (Cont.)
Electrical Characteristics Over recommended temperature, common mode input voltage, and supply voltage
ranges, unless otherwise specified.
Drive Switching Characteristics Vcc = 5 V, TA = 25°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
too
Differential Output Delay Time
RL = 60 n, Fig. 4
15
25
ns
tTD
Differential Output Transition Time
RL = 60 n, Fig. 4
15
25
ns
tpLH
Propagation Delay Time,
Low-to-High Level Output
RL = 27 n, Fig. 5
12
20
ns
tpHL
Propagation Delay Time,
High-to-Low Level Output
RL = 27 n, Fig. 5
12
20
ns
tpZH
Output Enable Time to High Level
RL = 110 n, Fig. 6
25
35
ns
tpzL
Output Enable Time to Low Level
RL = 110 n, Fig. 7
25
35
ns
tpHZ
Output Disable Time from High Level
RL = 110 n, Fig. 6
20
25
ns
tpLZ
Output Disable Time from Low Level
RL = 110 n, Fig. 7
29
35
ns
Typ1
Max
Unit
Receiver Section
Symbol
Characteristic
Condition
Min
VTH
Differential Input High
Threshold Voltage
Vo = 2.7 V, 10 = -0.4 mA
VTL
Differential Input Low
Threshold Voltage
Vo = 0.5 V, 10 = 8.0 mA
VT+ -VT_
Hysteresis6
VCM = 0 V
VIH
Enable Input Voltage HIGH
VIL
Enable Input Voltage LOW
VIC
Enable Input Clamp Voltage
11=-18 mA
VOH
Output Voltage HIGH
VIO = 200 mY, 10H = -400 pA, Fig. 3
VOL
Output Voltage LOW
VIO = -200 mY, Fig. 3
0.2
-0.2 5
V
50
mV
2.0
loz
High Impedance State Output
Vo = 0.4 V to 2.4 V
II
Line Input Current?
Other Input = 0 V
IIH
Enable Input Current HIGH
VIH =2.7 V
IlL
Enable Input Current LOW
VIL
RI
Input Resistance
los
Short Circuit Output Current
Icc
Supply Current (total package)
= 0.4
V
0.8
V
-1.5
V
2.7
V
I 10L = 8.0 mA
0.45
IIOL=16 mA
0.50
/lA
I VI = 12 V
1.0
mA
I VI =-7.0 V
0.8
20
-100
12
-15
IOutputs Enabled
IOutputs Disabled
9-100
V
±20
V
No Load
V
pA
/lA
kn
-85
mA
40
mA
!-LA96176
Receiver Switching Characteristics Vee = 5.0 V, TA = 25°C
Symbol
Typ
Max
Unit
16
25
ns
16
25
ns
CL = 15 pF, Fig. 9
15
22
ns
15
22
ns
CL = 5.0 pF, Fig. 9
14
30
ns
24
40
ns
Characteristic
Condition
tpLH
Propagation Delay Time,
Low-to-High Level Output
VID = 0 V to 3.0 V
CL = 15 pF, Fig. 8
tpHL
Propagation Delay Time,
High-to-Low Level Output
tPZH
Output Enable Time to High Level
tPZL
Output Enable Time to Low Level
tpHZ
Output Disable Time from High Level
tpLZ
Output Disable Time from Low Level
Min
Notes
1. All typical values are at Vee = 5.0 V and TA = 25'C.
2. "IVool and "lVoel are the changes in magnHude of Voo and Voe,
respectively, that occur when the input is changed from a high level to
a low level.
3. In EIA Standard RS-422A and RS-485, Voe, which is the average of the
two output voltages wHh respect to GND, is called output offset voltage,
•
Vos·
4. This applies for both power-on and power-off. Refer to EIA Standard
RS-485 for exact conditions.
5. The algebraic convention, where the less positive (more negative) limit is
designated minimum, is used in this data sheet for common mode input
voltage and threshold voltage levels only.
6. Hysteresis is the difference between the positive-going input threshold
voltage, VT + , and the negative-going input threshold voltage, VT - .
7. This applies for both power-on and power-off. Refer to EIA Standard
RS-485 for exact conditions.
Parameter Measurement Information
Figure 2 Driver VOD with Varying Common Mode
Voltage
Figure 1 Driver VOD and Voc
~~
(Note 3)
t
3750
-7Vto +12V
3750
Figure 3 Receiver VOH and VOL
v~rl'>-I
ov=:1 ntlot..
J 't
(+)
Gt
9-101
MA96176
Parameter Measurement Information (Cont.)
Figure 4 Driver Differential Output Delay and Transition Times
IN
GENERATOR
500
(Note 1)
OUT
Figure 5 Driver Propagation Times
IN
2.3V
RL=270
y
OUT
---0---,--'-- OUT
GENERATOR
(Note 1)
500
Z
3V
OUT
Figure 6 Driver Enable and Disable Times (tpZH. tpHZ)
--":>-"1'-~- OUT
OVor3V
IN
RL= 1100
d.5V
1.J
J,9
toHz
PZH
GENERATOR
500
OUT
(Note 1)
.
-.:..L
3V
ov
VOH
0.5V
2.3V
VOFF~
Figure 7
Driver Enable and Disable Times (tpZL. tpLZ)
5V
3V
RL= 1100
---0---,.....-
IN
OUT
~ ov
1.5V
l.5V
~
PZL
OUT
tpLZ
2.3V
5V
0.5V
-rVOL
9-102
OV
MA96176
Parameter Measurement Information (Cont.)
Figure 8 Receiver Propagation Delay Times
IN
OUT
:1:.5V
1'1
tJ.v
3V
ov
l:ev~
VOL
OV--------------~
CFI01061F
Figure 9 Receiver Enable and Disable Times
81
I.5V
52
O---5V
GENERATOR
~1)
~
1JozH
IN
OUT
tnL
3V 81101.5V
1.5V
OV
52 OPEN
S3CLOSED
IN
---(:E V~
£L
""'"
I.5V
~
D.5V
OUT
3V
SI1D-1.5V
S2 CLOSED
OV S30PEN
;:-.:;r-~4.5V
OUT
- - OV
IN
~
1.5V
~
----I'
toLz
3V SI1D1.5V
IN
52 CLOSED
OV S3CLOSED
V~
OUT
---~I.3V
VOL
V
~
:J=\=~1.3V
1.5V
3
SI1D-l.5V
S2CLOSED
OV S3CLOSED
o.sV
VOl.
Wf'00481F
Notes
1. The input pulse is supplied by a generalor having the following
characteristics: PRR - 1.0 MHz, 50% duty cycle, t," 6.0 ns, tf" 6.0 ns,
Zo- 50 n.
2. CL includes probe and stray capacitance.
3. ",,96176 Driver enable is Active-High
4. All diodes are 1N916 or equivalent.
9-103
J,lA96176
Typical Application
~A96176
~A96176
~----~~----r--------------------~--~~--
__~
/,--,-+-~~~~-------------------~~~--~--~~
UP TO 32
TRANSCEIVERS
Note
The line length should be terminated at both ends of its characteristic impedance.
Stub lengths off the main line should be kept as short as possible.
9-104
J.LA96177 • J.LA96178
Differential Bus Repeaters
FAIRCHILD
A Schlumberger Company
Linear Division Interface Products
Description
The JlA96177 and JLA96178 Differential Bus Repeaters are
monolithic integrated devices each designed for one-way
data communications on multipoint bus transmission lines.
These devices are designed for balanced transmission bus
line applications and meet EIA Standard RS-485 and
RS-422A. Each device is designed to improve the performance of the data communication over long bus lines.
The JLA96177 and JLA96178 are identical except for the
Enable inputs, which are complementary. The JLA96177 is
an active high Enable. The JlA96178 is an active low Enable. These complementary Enables allow the devices to
be used in pairs for bidirectional communication.
Connection Diagram
8-Lead DIP
(Top View)
IJA96177
SA}BUS
IN
Jo--.r" B
BUS
} OUT
The JlA96177 and JLA96178 feature positive and negative
current limiting and three-state outputs for the receiver and
driver. The receiver features high input impedance, input
hysteresis for increased noise immunity, and input sensitivity of 200 mV over a common mode input voltage range
of -12 V to + 12 V. The driver features thermal shutdown
for protection from line fault conditions. Thermal shutdown
is designed to occur at a junction temperature of approximately 160'C. The driver is designed to drive current
loads up to 60 mA maximum.
~A96178
y .........- - ,
6
Order Information
Device Code
Package Code
JLA96177RC
6T
JLA96177TC
9T
JLA96178RC
6T
JLA96178TC
9T
• Meets EIA Standard RS-422A And RS-485
• Designed For Multipoint Transmission On Long Bus
Lines In Noisy Environments
• Three-State Outputs
• Bus Voltage Range -7.0 V To 12 V
• Positive And Negative Current Limiting
• Driver Output Capability ± 60 mA Max
• Driver Thermal Shutdown Protection
• Receiver Input High Impedance
• Receiver Input Sensitivity Of ± 200 mV
• Receiver Input Hysteresis Of 50 mV Typical
• Operates From Single 5.0 V Supply
• Low Power Requirements
Vlo~0.2 V
-0.2 V < VIO < 0.2 V
VID';;;;-0.2 V
X
T
H
H
H
L
H
?
L
Z
Differential Inputs
A-B
VIO~0.2 V
-0.2 V < VID < 0.2 V
Vlo';;;;-0.2 V
X
H = High Level
L = Low Level
? = Indeterminate
X = Immaterial
Z = High Impedance (off)
Outputs
Y
Z
H
?
L
Z
OUT
Package Description
Ceramic DIP
Molded DIP
Ceramic DIP
Molded DIP
Function Table JLA96178
Function Table JlA96177
Enable
E
Z} BUS
......."'-_-;<1 Y
The IlA96177 and IlA96178 are designed for optimum performance when used on transmission buses employing the
IlA96172 and IlA96174 differential line drivers, JLA96173
and JLA96175 differential line receivers, or IlA96176 differential bus transceiver.
Differential Inputs
A-B
S A } BUS
B
IN
L
?
H
Z
9-105
Enable
E
T
L
L
L
H
H
?
L
Z
Outputs
Y
Z
H
?
L
Z
L
?
H
Z
tlA96177 • tlA96178
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1,2
8L-Ceramic DIP
8L-Molded DIP
Supply VoltageS
Input Voltage
-65°C to + 175°C
-65°C to + 150°C
O°C to +70°C
1.30 W
0.93 W
7.0 V
5.5 V
Notes
1. TJ Max = 150·C for the Molded DIP, and 175°C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 8L·Ceramic DIP at 8.7 mWrC, and the 8L-Molded DIP at
7.5 mWrC.
3. All voltage values are with respect to network ground terminal.
Recommended Operating Conditions
Symbol
Min
Characteristic
Vcc
Supply Voltage
VI or VCM
Voltage at any Bus Terminal (Separately
or Common mode)
VID
Differential Input Voltage2
IOH
Output Current HIGH
IOL
Output Current LOW
Typ
4.75
5.0
_7.0 1
Driver
Units
5.25
V
12
V
±12
V
-60
mA
-400
!1A
Driver
60
mA
Receiver
16
Receiver
TA
Max
Operating Temperature
0
Notes
1. The algebraic convention, where the less positive (more negative) limit is
designated minimum, is used -in this data sheet for common mode input
voltage and threshold voltage levels only.
2. Differential input! output bus voltage is measured at the noninverting
terminal A with respect to the inverting terminal B.
9-106
25
70
°C
MA96177 • MA96178
IlA96177, IlA96178
Electrical Characteristics Over recommended temperature, common mode input voltage, and supply voltage
ranges, unless otherwise specified.
Driver Section
Symbol
Characteristic
Condition
Min
Typl
VIH
Input Voltage HIGH
VIL
Input Voltage LOW
VIC
Input Clamp Voltage
11=-18 rnA
IVODll
Differential Output Voltage
10= 0 rnA
IVOD21
Differential Output Voltage
RL = 100
2.0
2.25
RL = 54
1.5
2.0
Max
2.0
V
0.8
V
-1.5
V
6.0
n Fig. 2
n Fig. 1
n or 100 n,
Change in Magnitude of Differential
Output Voltage 2
Voc
Common Mode Output Voltage 3
~IVocl
Change in Magnitude of Common Mode
Output Voltage 2
10
Output Current with Power off
Vcc=O V, Vo=-7.0 V to 12 V
loz
High Impedance State Output Current
Vo=-7.0 V to 12 V
IIH
Input Current HIGH
VI = 2.7 V
20
IlL
Input Current LOW
VI = 0.5 V
los
Short Circuit Output Current
Fig.l
±0.2
V
3.0
V
±0.2
V
±100
IlA
±200
-100
!lA
!lA
!lA
Vo=-7.0 V
-250
rnA
Vo=O V
-150
Vo=Vcc
150
±50
Vo = 12 V
Icc
Supply Current
V
V
~IVODI
RL = 54
Unit
No Load
9-107
250
IOutputs
IOutputs
Enabled
35
Disabled
40
rnA
•
MA96177 • MA96178
jJA96177, tlA96178 (Cont.)
Electrical Characteristics Over recommended temperature, common mode input voltage, and supply voltage
ranges, unless otherwise specified.
Drive Switching Characteristics Vcc = 5.0 V, TA = 25°C
Typ
Max
Unit
15
25
ns
RL = 60 n, Fig. 4
15
25
ns
RL = 27 n, Fig. 5
12
20
ns
Propagation Delay Time,
High-to-Low Level Output
RL = 27 n, Fig. 5
12
20
ns
tPZH
Output Enable Time to High Level
RL = 110 n, Fig. 6
25
45
ns
tPZL
Output Enable Time to Low Level
RL = 110 n, Fig. 7
25
40
ns
tpHz
Output Disable Time from High Level
RL = 110 n, Fig. 6
20
25
ns
tpLZ
Output Disable Time from Low Level
RL = 110 n, Fig. 7
29
35
ns
Symbol
Characteristic
Condition
too
Differential Output Delay Time
RL
tTD
Differential Output Transition Time
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
= 60
Min
n, Fig. 4
Receiver Section
Symbol
Characteristic
Condition
Min
Typ1
Max Unit
VTH
Differential Input High Threshold Voltage
Vo = 2.7 V, 10 = -0.4 mA
VTL
Differential Input Low Threshold Voltage
Vo = 0.5 V, 10 = 8.0 mA
0.2
VT+-VT_
Hysteresis6
VIH
Enable Input Voltage HIGH
VIL
Enable Input Voltage LOW
VIC
Enable Input Clamp Voltage
11=-18 mA
VOH
High Level Output Voltage
VID = 200 mY, 10H = -400 pA, Fig. 3
VOL
Low Level Output Voltage
VIO = -200 mY, Fig. 3 jlOL = 8.0 mA
loz
High-Impedance State Output
Va = 0.4 V
-360
Vo=2.4 V
20
-0.2 5
V
50
VCM = 0 V
Line Input Currentl
V
Other Input = 0 V
Enable Input Current HIGH
VIH = 2.7 V
IlL
Enable Input Current LOW
VIL = 0.4 V
RI
Input Resistance
los
Short Circuit Output Current
Icc
Supply Current (total package)
0.8
V
-1.5
V
0.45
V
2.7
V
0.50
1.0
JVI = 12 V
pA
mA
-0.8
IVI = -7.0 V
IIH
mV
2.0
jlOL = 16 mA
II
V
20
-100
p.A
pA
~~-
12
-15
No Load
9-108
kn
-85
mA
I Outputs Enabled
35
mA
IOutputs Disabled
40
MA96177 • MA96178
JJA96177, J.!A96178 (Cont.)
Electrical Characteristics Over recommended temperature, common mode input voltage, and supply voltage
ranges, unless otherwise specified.
Receiver Switching Characteristics Vcc = 5.0 V, TA = 25°C
Symbol
Characteristic
tpLH
Propagation Delay Time,
Low-to-High Level Output
tpHL
Propagation Delay Time,
High-to-Low Level Output
Min
Condition
VID = 0 V to 3.0 V
CL = 15 pF, Fig. 8
tPZH
Output Enable Time to High Level
tPZL
Output Enable Time to Low Level
tpHZ
Output Disable Time from High Level
tpLZ
Output Disable Time from Low Level
CL
CL
= 15 pF, Fig.
9
= 5.0 pF, Fig.
9
Typ
Max
Unit
16
25
ns
16
25
ns
15
22
ns
15
22
ns
14
30
ns
24
40
ns
Notes
1. 1. All typical values are at Vee - 5.0 V and TA - 25"C.
2. Dol Vao I and Dol Vae I are the changes in magnitude of Vao and Vae,
respectively, that occur when the input is changed from a high level to
a low level.
3. In EIA Standard RS-422A and RS-485, Vae, which is the average of the
two output voltages with respect to GND, is called output offset voltage.
Vos·
4. The algebraic convention, where the less positive (more negative) limit is
designated minimum, is used in this data sheet for common mode input
voltage and threshold voltage levels only.
5. Hysteresis is the difference between the positive-going input threshold
voltage, VT+ and the negative-going input threshold voltage, VT_.
6. Refer to EIA Standard RS-485 for exact conditions.
Parameter Measurement Information
Figure 2
Figure 1 Driver VOD2 and Voc
Driver VOD2 with Varying Common Mode
Voltage
3750
~
'----'--------'
-7Vto +12V
Voc
RL
~
CROO130F
Figure 3
ENABLED
(_3)
Receiver VOH and VOL
V'Drf'>-/
OV~ I6tIOL
J 't
(+)
t
IOH
(-)
9-109
3750
•
J.lA96177 • J.lA96178
Parameter Measurement Information (Cont.)
Figure 4 Driver Differential Output Delay and Transition Times
IN
GENERATOR
(Note 1)
OUT
Figure 5 Drive Propagation Times
IN
2.3 V
RL=271l
--<~....,..+--
y
OUT
OUT
GENERATOR
(Note 1)
ENABLED
(Nota3)
Z
OUT
Figure 6 Driver Enable and Disable Times (tpZH. tpHZ)
'-o-_-oSl
--C>-T-~- OUT
OVor3V
IN
RL=110n
GENERATOR
d.
sv
1.j
~
ZH
SOil
(Note 1)
OUT
3V
OV
tPHZ
2.3V
~VOH
O.SV
VOFF"=OV
Figure 7 Driver Enable and Disable Times (tpZlo tpLZl
SV
RL= looll
-"'0--,"'+-
OUT
9-110
f.lA96177 • f.lA96178
Parameter Measurement Information (Cont.)
Figure 8 Receiver Propagation Delay Times
IN
~'5V
I.]
LH
OUT
3V
OV
~
IPH~
1.3V
VOH
1.3V
VOL
ENABLED - - - - - - - - '
(NoI.3)
Figure 9 Receiver Enable and Disable Times
S2
o--SV
(~A96177)
IPZH
(~A96177)~
IN
I.SV
(~A96178)
~
3V Sllol.SV
S20PEN
OV 53 CLOSED
IN
(~A96178)
tpZL
~
1.5V
VOH
I.SV
~
OUT.J
VOL
- - OV
( A96177)
~
IN
IpLl
IpHZ
~ 3V Sllol.SV
~I~ L -
SIIo-I.5V
S2CLOSED
OV 53 OPEN
~i=-~4.5V
PZH
OUT
3V
(~A96177)~ 3V Silo -1.SV
IN
(~A96178)
S2CLOSED
(~A96178) l : : :IpHZ
f = t 1 . 5 V ::H 53 CLOSED
1.5V
:F\=
S2CLOSED
OV 53CLOSED
PLZ
--~1.3V
OUT
OUT
--~1.3V
O.5V
VOL
Notes
I. The input pulse is supplied by a generator having the following
characteristics: PRR = 1.0 MHz, duty cycle::::::50%, tr ~ 6.0 ns, tf'::::;;; 6.0 n5,
Zo ~ 50 [2.
2. CL includes probe and stray capacitance.
3. !lA96178 Enable is active low, !lA96177 Enable is active high.
4. All diodes are 1N916 or equivalent.
9-111
MA96177 • MA96178
Typical Application
Note
The line length should be terminated at both ends in its characteristic
impedance.
Stub lengths off the main line should be kept as short .as possible.
9-112
JlA9636A
RS-423 Dual Programmable
Slew Rate Line Driver
FAIRCHIL.D
A Schlumberger Company
Linear Division Interface Products
Connection Diagram
8-Lead DIP
(Top View)
Description
The I1A9636A is a TTL/CMOS compatible, dual, single
ended line driver which has been specifically designed to
satisfy the requirements of EIA Standard RS-423.
The I1A9636A is suitable for use in digital data transmission systems where signal wave shaping is desired. The
output slew rates are jointly controlled by a single external
resistor connected between the wave shaping control lead
(WS) and ground. This eliminates any need for external
filtering of the output signals. Output voltage levels and
slew rates are independent of power supply variations.
Current-limiting is provided in both output states. The
I1A9636A is designed for nominal power supplies of
± 12 V.
WAVESHAPE
CONTROL
INA
OUT A
INB
OUTB
v-
GND
Order Information
Inputs are TTL compatible with input current loading low
enough (1/10 UL) to be also compatible with CMOS logic.
Clamp diodes are provided on the inputs to limit transients
below ground.
•
•
•
•
•
V+
Device Code
Package Code
!1A9636ARM
!1A9636ARC
!1A9636ATC
6T
6T
9T
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
Programmable Slew Rate Limiting
Meets EIA Standard RS-423
Commercial Or Extended Temperature Range
Output Short Circuit Protection
TTL And CMOS Compatible Inputs
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Extended (I1A9636AM)
Commercial (!1A9636AC)
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1,2
8L-Ceramic DIP
8L-Molded DIP
V+ Lead Potential to Ground Lead
V - Lead Potential to Ground Lead
V+ Lead Potential to V- Lead
Output Potential to Ground Lead
Output Source Current
Output Sink Current
-65°C to + 175°C
-65°C to + 150°C
-55°C to +125°C
O°C to +70°C
1.30 W
0.93 W
V-to+15V
+0.5 V to -15 V
o V to +30 V
± 15 V
-150 mA
150 mA
Notes
1. T J Max ~ 175·C for the Ceramic DIP, and 150·C for the Molded DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 8L·Ceramic DIP at S.7 mWI"C, and the SL·Molded DIP at
7.5 mW/·C.
.iL
9-113
IlA9636A
Equivalent Circuit
r---------------~
TO
OTHER
CHANNEL
TO
OTHER
CHANNEL
I
WSCIN
I
I
I
I
R18
[
4COn
~~
R7
CU6
08
I
I
026"'a.,1
L.o"015
~
I
I 022~~
I
• t'021
I
I
027
I
I
I
I
R17
I
8.58kn
I
I
I
I
I
I
~
h:-
"Q28
~
~
W
[f
U10
~il-015
t016
~~017
I
I
I
I
I ~ il- 02O
I
I
I
I
I
K~
~~
~ ~018
~
,..
TO
OTHER
CHANNEL
:;122
TO
020 .........
OTHER
CHANNEL
;
,
500 n
lOOn
013
~
f- ~10
-
'~
,.--<
,..,.
R5
~ OUT
Rl
7I
'''02
I"
R19
V 011
R4
Cl
'--
~01
~02
[ ~CU3
r--
,.......,
'Cu9
V016
.""
"
R6
2.53 k!l
R6
R9
25kH
910 H
a..
,.....017
V 018
'I
v-
o
-
~
R2
61
701
V019
R15
10 kO
'~03
1;;0
L _______________ .J
-
09'"
'7014
R13
lOkI!
R14
"
>-012·
70
V03
~
~~011
,.......,~
CUii' ,......
R12
"
,
05
08'"
,.....012
GNO
~..
CU5
~
~
I
I
I
TO
OTHER
CHANNEL
032
Q6
*-4::
TO
OTHER
CHANNEL
IN
= COMMON TO BOTH CHANNELS
= CROSSUNOER
9-114
MA9636A
Recommended Operating Conditions
!lA9636A
Characteristic
Symbol
V+
Positive Supply Voltage
V-
Negative Supply Voltage
TA
Operating Temperature
Rws
Wave Shaping Resistance
Min
IlA9636AC
Typ
Max
Min
Typ
Max
Unit
10.8
12
13.2
10.8
12
13.2
-13.2
-12
-10.8
-13.2
-12
-10.8
V
70
·C
1000
kil
-55
25
10
125
0
500
10
25
V
/-LA9636A
Electrical Characteristics Over recommended operating temperature, supply voltage and wave shaping
resistance ranges unless otherwise specified.
DC Characteristics
Symbol
VOHI
Characteristic
Output Voltage HIGH
Condition
RL to GND (RL = 00)
VOH2
RL to GND (RL = 3.0 kil)
VOH3
RL to GND (RL
Min
Typ
Max
Unit
5.0
5.6
6.0
V
5.0
5.6
6.0
V
4.0
5.5
6.0
V
RL to GND (RL = 00)
-6.0
-5.7
-5.0
V
VOL2
RL to GND (RL = 3.0 kil)
-6.0
-5.6
-5.0
V
VOL3
RL to GND (RL = 450 il)
-6.0
-5.4
-4.0
V
25
50
il
-150
-60
-15
rnA
15
60
150
rnA
+100
!lA
VOL1
Output Voltage LOW
= 450
Ro
Output Resistance
450 il";';RL
los+
Output Short Circuit Current1
Vo=O V, VI=O V
il)
Vo = 0 V, VI = 2.0 V
losICEX
Output Leakage Current
Vo = ± 6.0 V, Power-Off
-100
VIH
Input Voltage HIGH
VIL
Input Voltage LOW
VIC
Input Clamp Diode Voltage
11= 15 rnA
-1.5
-1.1
IlL
Input Current LOW
VI = 0.4 V
-80
-16
IIH
Input Current HIGH
VI = 2.4 V
1.0
10
VI = 5.5 V
10
100
13
18
2.0
V
0.8
1+
Positive Supply Current
Vcc=±12 V, RL=oo,
Rws = 100 kil, VI = 0 V
1-
Negative Supply Current
Vcc=±12 V, RL=oo,
Rws = 100 kil, VI = 0 V
Notes
1. Only one output should be shorted at a time.
9-115
-18
-13
V
V
!lA
p.A
mA
rnA
J.lA9636A
J.(A9636A (Cont.)
Electrical Characteristics Over recommended operating temperature, supply voltage and wave shaping
resistance ranges unless otherwise specified.
AC Characteristics Vcc=±12 V±10%, TA = 25°C, see AC Test Circuit
Symbol
Characteristic
Condition
Rws = 10
Fall Time
tj
Typ
Max
0.8
1.1
1.4
8.0
11
14
Min
kn
Rws = 100 kn
Rws = 500 kn
Rws = 1000 kn
Rws = 10 kn
Rws = 100 kn
Rws = 500 kn
Rws = 1000 kn
Rise Time
t,
40
55
70
80
110
140
0.8
1.1
1.4
8.0
11
14
40
55
70
80
110
140
Unit
J.lS
J.lS
Typical Performance Curves
Input/Output Transfer
Characteristic vs Temperature
Yle~L2~ -
200
Rl~450ll
150
Rws"'" 100kn
>
I
6.0
!i
4.0
...
~
g
i
125"C
2-0
70"e
0
-2.0
-
I J
-55°C
Y~e ~I± 12'y
rRws = 100 ktl
,..
fl - f-.
-55°C
~
2S°C
f-
-200
1.2
0.6
I-J:o;.
TA=25"C
1I
~
II:
30
20
V, =2V
10
a
~ ~:
o
0
0
0
/v,-OY
lLl
125"C
-40
-50
1.8
1.6
125"C
VCC=±12V
Aws= 100k{l-
0
-30
-55°C
-6.0
~H
I"'"
~
-150
25"C
1/
DOC
50
r-U
II
2S°C
-4.0
OA
Output Current vs Output Voltage
(Power On)
Input Current vs Input Voltage
-1.0
INPUT VOLTAGE - V
0
1.0 2.0
3.0 4.0 5.0 6.0 7.0
-
10 8.0 6.0 4.0 2.0
INPUT VOLTAGE - V
0
j,./
2.0 4.0 6.0 8.0
10
OUTPUT VOLTAGE - V
PC06101F
Output Current vs Output Voltage
(Power Off)
100
1/
60
..
~
tz...
VCC=y,""DV
60 I - FD600 DIODE CONNECTED
IN SERIES WITH Vee PIN
40
20
}
II:
a:
::>
"5
-20
Supply Current vs Temperature
I
r
..e
.....
20
Z
10
0:
0:
..".
LOGIC
JlY'~O- ~
V, == 1
A~OG'C
VI=1
1-
_"'LOGIC_
V, '" 0
en
-60
-30
so
-40
-100
-10 -8.0 -6.0 -4.0 -2.0
0
2.0 4.0
OUTPUT VOLTAGE - V
6.0 8.0 10
-55
,
25
::i
if
r-
II:
125
100
0°'2.±!
IIII
2S°C
7ooe" 125"C
Q
~
TEMPERATURE _ °C
~
10
oV
~
1.
10 K 20 K 50 K 100 K 300 K 1.0 M
3.0 M
WAVE SHAPING RESISTANCE PC06121F
9-116
I
~
r-
I I
11
70
'1
;::
1t~OG'C
1+
~ -10
::> -20
0
55°C
jWS'1 'OOOll -
30
I
1000
Jee ~I± 12'y
40
::>
1= -40
::>
Transition Time vs Rws
II
J..lA9636A
AC Test Circuit and Waveforms
+12V
V,--.....- - t
I'>o--.....- -.....-Vo
450!l
SUI
CL
30pf
-12V
V,
Amplitude: 3.0 V
Offset: 0 V
Pulse Width: 500 IlS
PRR: 1.0 kHz
tr=tf~10 ns
Note
el includes jig and probe capacitance
RS-423
System Application
V+
V-
Note
1. Use Fairchild's 1N4448.
9-117
IlA9637A
Dual Differential
Line Receiver
FAIRCHILD
A
Schlumbe~$ler
Company
Linear Division Interface Products
Description
The 1lA9637A is a Schottky dual differential line receiver
which has been specifically designed to satisfy the requirements of EIA Standards RS-422 and RS-423. In addition,
the 1lA9637A satisfies the requirements of MIL-STD 188114 and is compatible with the International Standard
CCITT recommendations. The 1lA9637A is suitable for use
as a line receiver in digital data systems, using either single ended or differential, unipolar or bipolar transmission. It
requires a single 5.0 V power supply and has Schottky
TTL compatible outputs. The 1lA9637A has an operational
input common mode range of ± 7.0 V either differentially
or to ground.
•
•
•
•
•
•
•
•
•
Dual Channels
Single 5.0 V Supply
Satisfies EIA Standards RS-422 And RS-423
Built-In ± 35 mV Hysteresis
High Common Mode Range
High Input Impedance
TTL Compatible Output
Schottky TechnolC)gy
Extended Temperature Range
Connection Diagram
8-Lead DIP and 50-8 Package
(Top View)
+IN A
-INA
OUTB
+IN B
GNO
-IN B
Order Information
Device Code
1lA9637ARM
1lA9637ARC
1lA9637ATC
1lA9637ASC
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Extended (1lA9637 AM)
Commercial (1lA9637 AC)
Lead Temperature
Ceramic DIP (soldering, 30 s)
Molded DIP and SO Package
(soldering, 10 s)
Internal Power Dissipation 1. 2
8L-Ceramic DIP
8L-Molded DIP
SO-8
Vcc Lead Potential to Ground
Input Potential to Ground
Differential Input Voltage
Output Potential to Ground
Output Sink Current
Vee
OUT A
-65°C to +175°C
-65°C to + 150°C
-55°C to +125°C
O°C to +70°C
300°C
265°C
1.30 W
0.93 W
0.81 W
-0.5 V to 7.0 V
± 15 V
± 15 V
-0.5 V to +5.5 V
50 mA
Notes
1. TJ Max = 17S·C for Ihe Ceramic DIP. and IS0·C for Ihe Molded DIP.
2. Ralings apply 10 ambienl lemperalure al 2S·C. Above Ihis temperature.
derale Ihe 8L-Ceramic DIP al 8.7 mWrC. Ihe 8L-Molded DIP al 7.5
mWrC. and Ihe SO-8 al 6.5 mWrC.
9-118
Package Code
6T
6T
9T
KC
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
Molded Surface Mount
MA9637A
Equivalent Circuit
r---------.-------~~-----_.------_.-_.-------~----~c
R7
RS
R24
R14
R15
R23
as
02
Rll
Cl
5 pF
-IN
---~W-
__...
R3
Vee
OUT
•
- I N - -.....~W-_-+---I_--_+
R19
RS
GNO
Recommended Operating Conditions
f,lA9637A
Symbol
Characteristic
Vee
Supply Voltage
TA
Operating Temperature
f,lA9637AC
Min
Typ
Max
Min
Typ
Max
Unit
4.5
5.0
5.5
4.75
5.0
5.25
V
-55
25
125
0
25
70
·C
9-119
tLA9637A
,uA9637A
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, unless
otherwise specified.
DC Characteristics
Symbol
Characteristic
Condition 1
Min
Typ2
Max
Unit
VTH
Differential Input
Threshold Voltage 3
-7.0 V
VCM
.;;;
+7.0 V
-0.2
+0.2
V
VTH(R)
Differential Input
Threshold Voltage4
-7.0 V .;;; VCM
.;;;
+7.0 V
-0.4
+0.4
V
II
Input CurrentS
3.25
mA
.;;;
1.1
VI = 10 V, 0 V .;;; Vcc .;;; +5.5 V
VI=-10 V, 0 V .;;; Vcc .;;; +5.5 V
VOL
Output Voltage LOW
10L = 20 mA, Vcc = Min
VOH
Output Voltage HIGH
IOH=-1.0 mA, Vcc=Min
los
Output Short Circuit Current6
Va = 0 V, Vcc = Max
Icc
Supply Current
Vcc = Max, VI+ = 0.5 V,
VI- =GND
VHYST
Input Hysteresis
VCM =
± 7.0
-3.25
-1.6
0.35
0.5
V
V
2.5
3.5
-40
-75
-100
mA
35
50
mA
mV
70
V (See Curves)
AC Characteristics Vcc = 5.0 V, TA = 25°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
tpLH
Propagation Delay Time
Low to High
See AC Test Circuit
15
25
ns
tpHL
Propagation Delay Time
High to Low
See AC Test Circuit
13
25
ns
n
Notes
1. Use MiniMax values specified in recommended operating conditions.
2. Typical limits are at Vee = S.O V and TA = 2S·C.
3. VO'FF (Differential Input Voltage) = (V,+) - (V,-). VeM (Common Mode
Input Voltage) = V,+ or V,-.
4. 500
± 1% in series with inputs.
5. The input not under test is tied to ground.
6. Only one output should be shorted at a time.
Typical Input/Output Transfer Characteristics
Vee" 5.25 V
I
w
"~
g
!:;
0.
l-
S
il
I
,.
I~::-:
I
I
I
:I
>
I
I
I
I:
I
:
"i!....
g
...
I
!:;
o
I
I
I
I:
I VCM
I
1
I
I
== +7 V
I:
I
~
V--" I
lr---~r+lr-~---HI~----~
VCM - 0
I~
I
w
VeM"!7V
VCM" OV--"
I
I
I
I
I
II
II
o
-100
'NPUT VOLTAGE-mV
50
INPUT VOLTAGE-mV
9-120
100
JlA9637A
AC Test Circuit and Waveforms
Vee = s.ov
Vee = s.ov
Vo
+O.5V
392
v,
n
V,
-o.SV
51 !)
C,
15 pF
3.92 kn
Notes
CL includes jig and probe capacitance.
All diodes are FD700 or equivalent.
V,
Amplitude: 1.0 V
Offset: 0.5 V
Pulse Width: 100 ns
PRR: 5.0 MHz
tr=tf N ' - - -...
Rl4
Rl5
~---..,.--+--.
Rll
Vee
OUT
Rl
-IN----J>N'---~---~--_+
R2
R6
O~ ~----_+--~~
RS
Rl9
GNO
Recommended Operating Conditions
Characteristic
Symbol
Vee
Supply Voltage
TA
Operating Temperature
9-127
Min
Typ
Max
4.75
5.0
5.25
Unit
V
0
25
70
°C
MA9639A
pA9639A
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, unless
otherwise specified.
DC Characteristics
Condition 1
Typ2
Max
Unit
VTH
Differential Input
Threshold Voltage3
-7.0 V------.. OTHER
RECEIVERS
R20
-
-
c::J
~ COMMON CIRCUITRY
~ CROSSUNDER
I
I
I
I
I
I
-.J
I
L
__
-
TO ONE
OTHER
RECEIVER
"
9-131
J,LA9640(26510)
Recommended Operating Conditions
Extended 4
Symbol
Characteristic
Min
Typ
Commercial 5
Max
Min
Typ
Max
Unit
Vee
Supply Voltage
4.50
5.0
5.5
4.75
5.0
5.25
V
TA
Operating Temperature
-55
25
125
0
25
70
°C
1lA9640(26S10)
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, unless
otherwise specified.
DC Characteristics
Symbol
Condition 1
Characteristic
Min
Typ2
Extended 4
2.5
3.4
Comm 5
2.7
3.4
Max
Output Voltage HIGH
(Receiver Outputs)
Vee = Min,
IOH=-1.0 mA,
VI = VIL or VIH
VOL
Output Voltage LOW
(Receiver Outputs)
Vee = Min, 10L = 20 mA,
VI = VIL or VIH
VIH
Input Voltage HIGH
(Except Bus)
Guaranteed Input Logic HIGH
for All Inputs
VIL
Input Voltage LOW
(Except Bus)
Guaranteed Input Logie LOW
for All Inputs
Vie
Input Clamp Voltage
(Except Bus)
Vee = Min, 11=-18 mA
IlL
Input Current LOW
Vee = Max,
VI = 0.4 V
Vee = Max,
VI=2.7 V
ENABLE
20
DATA
30
VOH
IIH
Input Current HIGH
Vee
los
lee
-= Max,
Unit
V
0.5
V
V
2.0
0.8
V
-1.2
V
ENABLE
-0.36
mA
DATA
-0.54
VI = 5.5 V
IlA
100
Extended4
-20
-55
Comm 5
-18
-60
Output Short Circuit
Current (Except Bus)3
Vee = Max
Supply Current
Vee = Max, VI = VIH, Enable = GND
45
70
mA
mA
AC Characteristics Vee = 5.0 V, TA = 25°C
Symbol
Condition6
Characteristic
Min
Typ2
Max
Rs=50 n,
Cs =50 pF
10
15
14
18
Bus to Receiver Out
Rs = 50 n, RL = 280 n,
Cs = 50 pF, CL = 15 pF
10
15
Ir
Rise Time Bus
If
Fall Time Bus
Rs = 50 n,
CB = 50 pF
tpD
Data Input to Bus
Enable Input 10 Bus
9-132
Unit
ns
4.0
10
ns
2.0
4.0
ns
IlA9640(26S10)
J.lA9640(26S10) (Cont.)
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, unless
otherwise specified.
Bus Input/Output Characteristics
Symbol
VOL
Vcc= Min
Extended 4
Comm s
ICEX (ON)
Bus Leakage Current
Cl
0.42
0.7
IOL = 100 mA
0.51
0.8
p.A
2.4
V
Comm s
2.0
2.25
Extended4
Comm s
Vee
(NOTE 2)
5 PF
-=- (NOTE')
BUS
TEST
POINT
Note
I. Includes probe and jig capacitance.
2. All Diodes 1N916 or equivalent.
9-133
p.A
100
Rl
280 {}
I'
IOL = 70 mA
V
2.0
Figure 1 AC Test Circuit
-=-
0.5
Unit
Extended4
Notes
1. For conditions shown as Min or Max, use the appropriate value specified
under Electrical Characteristics for the applicable device type.
2. Typical limits are at Vee - S.O V, TA - 2SoC ambient and maximum
loading.
3. Not more than one output should be shorted at a time. Duration of the
short circuit test should not exceed one second.
4. Extended temperature range, ceramic DIP.
5. Commercial temperature range, ceramic or molded DIP.
6. CB and CL include probe and jig capacitance.
I
0.8
0.33
100
Bus Enable = 2.4 V,
Vcc= Min
RECEIVER
OUT
0.51
IOL = 40 mA
Vo=4.5 V
Receiver Input
Threshold LOW
TEST
POINT
IOL = 100 mA
Comm s
Bus Enable = 2.4 V,
VCC= Max
0F
0.7
200
Vo=4.5 V, VCc=O V
CS
0.42
-50
Bus Leakage Current
50
IOL = 70 mA
Vo= 4.5 V
Receiver Input
Threshold HIGH
(NOTE')
0.5
Extended 4
ICEX (OFF)
Vee
Max
0.33
Min
Vo= 0.8 V
Vcc= Max
VTH+
VTH-
Typ2
IOL =40 mA
Condition 1
Characteristic
Output Voltage LOW
1.6
2.0
1.75
2.0
V
J.LA9640(26S 10)
Figure 2
Waveforms
p.A9640
, INPUT
ENABLE
INPUT
BUS
TEST
POINT
t f
. ~ f ~,~ {
'PH'
~
RECEIVEROUT _ _ _ _
TEST POINT
_t_;;:
j
'i_v
~ fW ~ {___==~"
r- -1
\l
"'
'PHL
t-'PLH
_!vr~~~~\
T-
I ____~":HV
"
~----' - - - - - V O L
CR01781F
9-134
J..lA9643
Dual TTL To MOS/CCD
I=AIRCHIL.O
A Schlumberger Company
Driver
Linear Division Interface Products
Description
Connection Diagram
8-Lead DIP
(Top View)
The /JA9643 is a dual positive logic "AND" TTL-to-MOS
driver. The 1JA9643 is a functional replacement for the
SN75322 with one important exception: the two external
PNP transistors are no longer needed for operation. The
1JA9643 is also a functional replacement for the 75363
with the important exception that the VCC3 supply is not
needed. The lead connections normally used for the external PNP transistors are purposely not internally connected
to the 1JA9643.
INA
E
IN B
GND
• Satisfies CCD Memory And Delay Line Requirements
• Dual Positive Logic TTL To MOS Driver
• Operates From Standard Bipolar And MOS Supply
Voltages
• High Speed Switching
• TTL And DTL Compatible Inputs
• Separate Drivers Address Inputs With Common
Strobe
• VOH And VOL Compatible With Popular MOS RAMs
• Does Not Require External PNP Transistors Or VCC3
• VOH Minimum Is VCC2-0.5 V
Order Information
Device Code
1JA9643TC
Package Description
Molded DIP
Truth Table
INPUT
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1, 2
Supply Voltage Range of VCCI 3
Supply Voltage Range of VCC2
Input Voltage
Inter-Input Voltage4
Package Code
9T
-65°C to + 150°C
O°C to +70°C
265°C
0.93 W
-0.5 V to +7.0 V
-0.5 V to +15 V
5.5 V
5.5 V
Notes
I. TJ Max-ISO'C
2. Ratings apply to ambient temperature at 2S·C. Above this temperature,
derate at 7.5 mWrC.
3. Voltage values are with respect to network ground terminals unless
otherwise noted.
4. This rating applies between any two inputs of anyone of the gates.
9-135
ENABLE
OUTPUT
L
L
L
L
H
L
H
L
L
H
H
H
MA9643
Equivalent Circuit (1/2 of Circuit)
At
VCC1
10kn
01~
Cl
R3
Rl
lkn
3kn
R2
+--.---I----1--t' Q14
1.5kU
03
t---------i:OS·
07
OUT
011
02
Rll
eoOn
o
CROSSUNDER
R4
soon
014
GNO
EOOO27OF
Recommended Operating Conditions
Symbol
Characteristic
Min
Typ
Max
Unit
Vce1
Supply Voltage
4.75
5.0
5.25
VCC2
Supply Voltage
11.4
12
12.6
V
TA
Operating Temperature
0
25
70
·C
V
me
1lA9643
J.LA9643
Electrical Characteristics Over recommended operating temperature and VCC1, VCC2 ranges, unless otherwise
specified.
DC Characteristics
Symbol
Characteristic
Condition
Typ1
Min
Max
VIH
Input Voltage HIGH
VIL
Input Voltage LOW
2.0
VOH
Output Voltage HIGH
IOH = -400 p.A
VOL
Output Voltage LOW
IOL = 10 mA
0.4
0.5
IOL = 1.0 mA
0.2
0.3
VCC2- 0.5
Input Current at Maximum
Input Voltage
VCC1 = 5.25 V, VCC2 = 11.4 V
VI =5.25 V
IIH
Input Current HIGH
VI =2.4 V
IlL
Input Current LOW
V
0.8
II
VI =0.4 V
Unit
V
V
VCC2- 0.2
V
0.1
mA
A Inputs
40
p.A
E Inputs
80
A Inputs
-0.5
E Inputs
-1.0
mA
ICC1(L)
Supply Current from VCC1
All Outputs LOW
VCC1 = 5.25 V,
VCC2 = 12.6 V
15
19
mA
ICC2(L)
Supply Current from VCC2
All Outputs LOW
VCC1 = 5.25 V,
VCC2 = 12.6 V
5.5
9.5
mA
ICC1(H)
Supply Current from VCC1
All Outputs HIGH
VCC1 = 5.25 V,
VCC2 = 12.6 V
9.0
13
mA
ICC2(H)
Supply Current from VCC2
All Outputs HIGH
VCC1 = 5.25 V,
VCC2 = 12.6 V
5.5
9.5
mA
AC Characteristics VCC1 = 5.0 V, VCC2 = 12 V, TA = 25°C
Symbol
Characteristic
tDLH
Delay Time
tDHL
Delay Time
tTLH
Rise Time
tTHL
Fall Time
tTLH
Rise Time
tTHL
Fall Time
tPLHA_
tpLHB
tPHLA_
tpHLB
Skew between outputs
A and B
Condition
CL =300 pF
CL =300 pF
RSERIES = 0
RSERIES = 10
n
CL =300 pF
.(
Min
Typ
1. All typical values are at vcc, = 5.0 V. V= = 12.0 V, and TA - 2SoC
unless otherwise noted.
9-137
Unit
5.0
9.0
17
ns
5.0
9.0
17
ns
6.0
11
17
ns
6.0
11
17
ns
8.0
14
20
ns
8.0
14
20
ns
0.5
Note
Max
ns
MA9643
AC Test Circuit and Waveforms
v,-_...r--
2.4 V - - " " L_ _.....""",_.---vo
1-<10ns
I
v,----1
.....:---VON
CFI01760F
Notea
Tha pulse generator has the following characteristics:
PRR -1.0 MHz,
Zo -
50
n
CL includes probe and jig capacitance.
9·138
J.LA9645(3245)
Quad TTL To MOS/CCD
Driver
FAIRCHILD
A Schlumberger Company
Linear Division Interface Products
Description
The j.lA9645(3245) is a high speed driver intended to be
used as a clock (high level) driver for 18 or 22·lead dy·
namic NMOS RAMs. It also satisfies the non·overlapping
2·phase clock drive requirements for CCD memories like
the F464 (64K) RAM.
Connection Diagram
16-Lead DIP
(Top View)
Vee1
VCC2
The circuit is designed to operate on nominal + 5.0 V and
+ 12 V power supplies and contains input and output
clamp diodes to minimize line reflections.
ourD
our A
INO
INA
The device features two common enable inputs, a refresh
select input and a clock control input. Internal gating
structure is organized so that all four drivers may be de·
activated for standby operation, or a single driver may be
activated for read/write operation or all four drivers may
be activated for refresh operation.
C
E,
R
E2
INC
INB
The j.lA9645(3245) is a lead for lead replacement of the
Intel 3245 Quad TTL·to·MOS Driver, with substantially reo
duced DC power dissipation.
our a
OUTC
OND
•
•
•
•
NC
Interchangeable With Intel 3245
Four High Speed, High Current Drivers
Control Logic Optimized For MOS RAMs
Satisfies CCD Memory And Delay Line Drive
Requirements
• TTL And DTL Compatible Inputs
• High Voltage Schottky Technology
Device Code
Package Code
j.lA9645DC(3245)
7B
j.lA9645PC(3245)
9B
Absolute Maximum Ratings
Truth Table
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1,2
16L·Ceramic DIP
16L·Molded DIP
Supply Voltage, VCC1
Supply Voltage, VCC2
All Input Voltages
Outputs For Clock Driver
Temperature Under Bias
Order Information
Package Description
Ceramic DIP
Molded DIP
Inputs
-65·C to + 175·C
-65·C to + 150·C
O·C to +70·C
300·C
26!?·C
1.50 W
1.04 W
-0.5 V to +7.0 V
-0.5 V to + 14.0 V
-1.0 V to V-1.0 V to
(V-) +1.0 V
-10·C to +70·C
Control
Address
C
E2
E1
INPUT
REFRESH
H
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
L
X
X
L
H- HIGH
L=LOW
Don't Care
X=
Notes
1. TJ Max -175'C for the CeramiC DIP, and 150'C for the Molded DIP.
2. Ratings apply to ambient temperature at 25·C. Above this temperature,
derate the 16L-Ceramic DIP at 10 mWrC, and the 16L-Molded DIP at
8.3 mWrC.
9·139
H
Output
H
L
L
L
L
H
H
J.LA9645(3245)
Equivalent Circuit
Vcc,
I
vi
A4
SkU
·'if
ii
71IOn
At
10lcH
......
~tD12
~
t--
"02
t
C1
10;'"
""'05
"....
""'014
"....
':"
~~D7
R14
SIUI
R15
5kn
'--
R11
300n
R18
SkU
~1U1
.:
~
~D13
r-:tI
va;-
i~~"
~ ~DI ~ ~D10
10k.l1
~
N
~~
150n
D8~
Q6
ii.
"018
D4!
......
R7
200"
~
ii,
R10
1.5k"
"017
"1
iDS
GNO
~
OUT8
!tiB
INC
INO
I
I
....;-.-
OUTC
~
OUTD
I
I
I
9-140
!t,11
""'012
.,....,.
R13
......::
.~
III
1.5 kn
~
C
1
R3
R
K~
RI
4kn
.......
OUT
A
j~D14
""011
.,....,.
':"
MA9645(3245)
Logic Diagram
!,
I!o
OUT A
INA
OUTS
INII
OUTe
INe
OUT 0
INiI
ii
C
1lA9645(3245)
Electrical Characteristics VCCl = 5.0 V ± 5%, VCC2 = 12 V ± 5%, TA = Doe to 70 oe, unless otherwise
specified.
DC Characteristics
Symbol
Characteristic
Condition
Typ
Input Load Current, IN (A,B,C,D)
VF = 0.45 V
Max
-0.25
Unit
IFD
IFE
Input Load Current, R, C, E1, E2
VF = 0.45 V
-1.0
rnA
IRD
Data Input Leakage Current
VR= 5.0 V
10
IRE
Enable Input Leakage Current
VR =5.0 V
40
iJ.A
iJ.A
VOL
Output Voltage LOW
Output Voltage HIGH
0.45
IOL = 5.0 mA, VIH = 2.0 V
IOL=-5.0 mA
VOH
Min
IOH = -1.0 mA, VIL = 0.8 V
VIL
Input Voltage LOW, All Inputs
Input Voltage HIGH, All Inputs
V
-1.0
V
VccrO.5O
IOH = 5.0 mA
VIH
rnA
VCC2 +1.0
0.8
2.0
V
V
I+H
Positive Supply Current HIGH
VCCl =5.25 V
13
20
I-H
Negative Supply Current HIGH
VCC2= 12.6 V
14
20
mA
PC(H)
Power Consumption HIGH
All Outputs HIGH
248
357
mW
Power Per Channel
mA
62
90
mW
I+L
Positive Supply Current LOW
VCCl = 5.25 V
27
35
rnA
I-L
Negative Supply Current LOW
VCC2 = 12.6 V
12
15
mA
PC(L)
Power Consumption LOW
All Outputs LOW
296
373
mW
74
94
mW
Power Per Channel
9-141
~9645(3245)
1LA9645(3245) (Cont.)
Electrical Characteristics VCC1 = 5.0 V ± 5%, VCC2 = 12 V ± 5%, TA = O°C to 70°C, unless otherwise
specified.
AC Characteristics
Symbol
t-( +)
Characteristic
Input to Output Delay
RSERIES
=0
Delay Plus Rise Time
RSERIES=O
t+(-)
Input to Output Delay
RSERIES=O
tOFt
Delay Plus Fall Time
RSERIES= 0
tT
Output Transition Time
RSERIES = 20
tOR2
Delay Plus Rise Time
RSERIES = 20
tOF2
Delay Plus Fall Time
RSERIES = 20
tORt
Mint
Condition
T yp2,4
5.0
3.0
n
n
n
10
11
18
7.0
18
13
27
24
Max3
ns
32
AC Test Circuit and Waveforms
3V~\
"K"'u_v____--'
1. - ____ _
GND _ _
v_ -
WF00111F
Note
AC Test Conditions:
Input Pulse Amplitude - 3.0 V
Input Pulse Rise and Fall Times
= 5.0
ns Between 1.0 V and 2.0 V
9-142
ns
ns
32
20
38
38
Notes
1. CL=150 pF
2. CL - 200 pF
3. CL = 250 pF
4. Typical values are measured at TA - 25°C
CROOe11F
Unit
ns
ns
ns
ns
IlA9665 • IlA9666
IlA9667 • IlA9668
High Current/Voltage
Darlington Drivers
FAIRCHILD
A Schlumberger Company
Linear Division Interface Products
Description
Connection Diagram
16-Lead DIP
(Top View)
The #lA9665, #lA9666, #lA9667, and #lA9668 are comprised
of seven high voltage, high current NPN Darlington transistor pairs. All units feature common emitter, open collector
outputs. To maximize their effectiveness, these units contain suppression diodes for inductive loads and appropriate
emitter base resistors for leakage.
INA
INS
The #lA9665 is a general purpose array which may be
used with DTL, TTL, PMOS, CMOS, etc. Input current limiting is done by connecting an appropriate discrete resistor
to each input.
INC
IND
INE
INF
The #lA9666 version does away with the need for any external discrete resistors, since each unit has a resistor and
a Zener diode in series with the input. The #lA9666 was
specifically designed for direct interface from PMOS logic
(operating at supply voltages from 14 V to 25 V) to solenoids or relays.
INO
OUTG
OND
COMMON
Order Information
Device Code
The #lA9667 has a series base resistor to each Darlington
pair, thus allowing operation directly with TTL or CMOS
operating at supply voltages of 5.0 V.
#lA9665DC
#lA9665PC
#lA9666DM
#lA9666DC
#lA9666PC
#lA9667DM
#lA9667DC
#lA9667PC
#lA9668DM
#lA9668DC
#lA9668PC
The #lA9668 has an appropriate input resistor to allow direct operation from CMOS or PMOS outputs operating
from supply voltages of 6.0 V to 15 V.
The #lA9665, #lA9666, #lA9667, and #lA9668 offer solutions
to a great many interface needs, including solenoids, relays, lamps, small motors, and LEDs. Applications requiring
sink currents beyond the capability of a single output may
be accommodated by paralleling the outputs.
•
•
•
•
•
•
•
Seven High Gain Darlington Pairs
High Output Voltage (VCE = 50 V)
High Output Current (Ic 350 mAl
DTL, TTL, PMOS, CMOS Compatible
Suppression Diodes For Inductive Loads
2 Watt Molded DIP On Copper Lead Frame
Extended Temperature Range
=
9-143
Package Code
68
98
68
68
98
68
68
98
68
68
98
Package Description
Ceramic DIP
Molded DIP
Ceramic DIP
Ceramic DiP
Molded DIP
Ceramic DIP
Ceramic DIP
Molded DIP
Ceramic DIP
Ceramic DIP
Molded DIP
J.{A9665 • IlA9666 • IlA9667 • IlA9668
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Extended (!lA96661718M)
Commercial (!lA9665/6/7/8C)
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1, 2
16L-Ceramic DIP
16L-Molded DIP
Input Voltage
Output Voltage
Emitter-Base Voltage
Continuous Collector Current
Continuous Base Current
-65·C to +175·C
-65·C to +150·C
-55·C to +125·C
O·G to +70·C
300·G
265·G
1.50 W
1.04 W
30 V
55 V
6.0 V
500 mA
25 mA
Notes
1. TJ Max -175'C for the Ceramic DIP, and 150'C for the Molded DIP.
2. Ratings apply to ambient temperature at 25'C. Above this temperature,
derate the 16L-Ceramic DIP at 10 mWI'C, and the 16L-Molded DIP at
8.3 mW/'C.
3. Under normal operating conditions, these units will sustain 350 rnA per
output with VCE(Sat) = 1.6 V at 70'C with a pulse width of 20 ms and a
duty cycle of 30%.
Equivalent Circuits
1lA9667
1lA9665
COMMON
COMMON
,---....~-=-- OUT
2.7kn
.----....~-=-- OUT
iii
1lA9666
1lA9668
CO.aN
COMMON
, - - -.....___-=--OUT
. - - - -....- - - O U T
10-5 kll
E000351F
9-144
MA9665 • MA9666 • MA9667 • MA9668
/lA9665/617/8
Electrical Characteristics TA = 25°C, unless otherwise specified.
Symbol
ICEX
Output Leakage Current
TA = 70°C for Commercial
VCE = 50 V
VCE = 50 V, VI = 6.0 V
VCE = 50 V, VI = 1.0 V
VCE(Sat)
Test
Figure
Conditions 1
Characteristic
pA9666
pA9668
Max
100
1b
500
1b
2
1.25
1.6
Ic = 200 rnA, 18 = 350 pA
2
1.1
1.3
Input Current
VI = 17 V
2
0.9
1.1
3
0.85
1.3
VI =3.85 V
pA9666
pA9667
3
0.93
1.35
VI = 5.0 V
!lA9668
3
0.35
0.5
VI = 12 V
3
1.0
1.45
4
Input Current2
TA = 70°C for Commercial
Ic = 500 pA
VI(ON)
Input Voltage3
VCE = 2.0 V, Ic = 300 rnA
65
13
2.4
VCE = 2.0 V, Ic = 250 rnA
5
2.7
VCE = 2.0 V, Ic = 300 mA
5
3.0
pA9668
5
5.0
VCE = 2.0 V, Ic = 200 mA
5
6:0
VeE = 2.0 V, Ie = 275 rnA
5
7.0
VeE = 2.0 V, Ic = 350 mA
5
VeE = 2.0 V, Ic = 350 mA
pA9665
2
pA
V
mA
pA
5
VCE = 2.0 V, Ic = 125 mA
DC Forward Current
Transfer Ratio
pA9666
pA9667
50
5
VCE = 2.0 V, Ic = 200 rnA
Unit
500
Ic = 350 mA, 18 = 500 pA
II(OFF)
hFE
Typ
Collector-Emitter
Saturation Voltage
Ic = 100 mA, 18 = 250 pA
II(ON)
Min
1a
V
8.0
1000
CI
Input Capacitance
15
30
pF
tpLH
Turn-On Delay
0.5 VI to 0.5 Vo
1.0
5.0
iJ.S
tpHL
Turn-Off Delay
0.5 VI to 0.5 Vo
1.0
5.0
iJ.S
IR
Clamp Diode
Leakage Current
VR = 50 V
6
50
pA
VF
Clamp Diode Forward
Voltage
IF=350 mA
7
2.0
V
Notes
1. All limits stated apply to the complete Darlington series except es
specified for a single device type.
2. The I'(OFF) current lim" guaranteed against partial turn-on of the output.
3. The V'(ON) voltage limit guarantees a minimum output sink current per
the spec~ied test conditions.
9-145
1.7
MA9665 • MA9666 • MA9667 • MA9668
Typical Performance Curves
Collector Current vs
Saturation Voltage
Collector Current vs Input Current
IJCO
,-
400
TYPICAL
(2 PARALLELED DEVICES)
-!
TYPICAL
I
I
TYPICAL
(SINGLE DEVlCE)-
,
'
I,
o
I
1.0
I
,,
MAX/
I
Z
1.5
1.0
:::>
;!;
0.5
E
ffi
i
a
/ '
~
1.0
5
~0.5 ./'
,/.'
3.0
./
I
/,
"
o
2.0
oC 1.5
V ,
w
:::>
~o
s.o
6.0
7.0
a.o
V
V
","
,/
TYP
, "
o
5.0
9.0
INPUT YOLTAGta - v
Peak Collector Current va
Duty Cycle arid Number of
Outputs (Molded package)
""
6.0
7.0
8.0
9.0
10
11
12
INPUT VOLTAGE - V
Peak Collector Current vs
Duty Cycle and Number of
Outpl,lts (Ceramic Package)
.
E'
I
~300I--H--\--,H-"*""---+'~-I----l
~
~
~ 2ODr---~~~~~~~~--~
~
~
DUTY CYCLE - "10
.."
1.0
0.5
,
/
V
..'
..
.
TY:~ ~'
~'
DUTY CYCLE - %
9·146
12
14
16
18
20
22
INPUT VOLTAGE - V
~
TYP,
/ ,
E
600
2.0
V ~'
,
/
,
o
400
1lA9668 Input Current vs
Input Voltage
2.5
2.0
~
z
INPUT CURRENT -
1lA9667 Input Current vs
Input Volt!lge
.
..
...
...."
iB
-
20D
SATURATION VOLTAGE - V
'"
I
,'1
o
o
1.5
V
""V/
/
~ 1.5
V
I
/UMIT
MA)
I
I
V
"
0.5
I
/
---/-. ~'
I
o
,,
2.0
V
MAXI
I
I
1lA9666 Input Current vs
Input Voltage
24
26
JlA9665 • JlA9666 • JlA9667 • JlA9668
Test Circuits
Figure 1a
Figure 1b
Figure 2
OPEN +50V
OPEN+50V
~~r"
Figure 3
OPEN
'ifIT"
Figure 4
OPEN
OPEN +50V
rr'mA
vi"':'"
-=
Figure 6
Figure 7
+50V
,-
~
~
"
OPEN
-!Of
iF
9-147
#+
t
t
-:-
Figure 5
OPEN
rffi
Ie
l-:-v
eE
:-:-
t
tlA9665 • tlA9666 • tlA9667 • tlA9668
Typical Applications
Buffer for Higher Current Loads
PMOS to Load
V,
II:!
V,
V2
16
16
15
15
14
14
13
l
"A9666
13
12
~9667
12
11
10
PMOS
OUTPUT
-=
TTL
-=
OUTPUT
TTL to Load
V,
V2
16
15
14
13
~9668
~~
10
1
CMOS
OUTPUT
-=
12
-=
-=
9-148
-=
t~
IlA9679
Differential Bus Repeater
FAIRCHILD
A Schlumberger Company
Linear Division Interface Products
Description
Connection Diagram
8-Lead DIP
(Top View)
The J.lA9679 Differential Bus Repeater is a monolithic integrated circuit designed for bidirectional data communication
on balanced bus transmission lines. The repeater meets
EIA Standard RS-422A.
The J.lA9679 combines a three-state differential line driver
and a differential input line receiver, both of which operate
from a single 5.0 volt power supply. The driver and receiver are operated from a single enable lead. When one device is active, the other device is disabled. This feature
allows for complete isolation of the driver from the receiver function.
The driver is designed to handle loads up to 60 mA of
sink or source current. The driver features positive and
negative current limiting and thermal shutdown protection
for line fault conditions. Thermal shutdown is designed to
occur at a junction temperature of "" 160°C. The receiver
features a typical input impedance of 12 kU, an input sensitivity of ± 200 mV and a typical input hysteresis of
50 mV.
•
•
•
•
•
•
•
•
•
•
•
T
B
E
z
GND
y
Package Code
J.lA9679TC
9T
Package Description
Molded DIP
Function Table Receiver
Differential Inputs
Enable Output
Driver
A-B
E
T
VID;;' 0.2 V
L
H
Z
-0.2 V <; VID
< 0.2
L
?
Z
VID<;-0.2 V
V
L
L
Z
X
H
Z
See Function
Table Driver
Function Table Driver
Absolute Maximum Ratings
Driver Input
-65°C to + 150°C
O°C to +70°C
265°C
0.93 W
7.0 V
5.5 V
= 150"C.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate at 7.5 mWrC.
3. AU voltage values are with respect to network ground terminal.
9-149
Enable
Output
Receiver
A-B
E
y
H
H
H
L
Z
L
H
L
H
Z
H = High Level
L = Low Level
? = Indeterminate
X = Immaterial
Z = High Impedance (off)
Notes
1. TJ Max
A
Order Information
Device Code
Meets EIA Standard RS-422A
Three-State Control
Common Enable For Isolation
Driver Output Capability ± 60 mA
Thermal Shutdown Protection
Positive And Negative Current Limiting
High Impedance Receiver Input
Receiver Input Sensitivity Of ± 200 mV
Receiver Input Hysteresis Of 50 mV Typical
Operates From Single 5.0 V Supply
Low Power Requirements
Storage Temperature Range
Operating Temperature Range
Lead Temperature
Molded DIP (soldering, 10 s)
Internal Power Dissipation I, 2
Supply Voltage 3
Input Voltage
Vcc
Z
J-lA9679
Recommended Operating Conditions
Symbol
Characteristic
Min
Typ
Max
Units
V
Vcc
Supply Voltage
VID
Differential Input Voltage 1
10H
Output Current HIGH
Driver
-400
p.A
10L
Output Current LOW
Driver
60
mA
Receiver
16
4.75
5.0
5.25
Receiver
Operating Temperature
TA
0
25
±12
V
-60
mA
70
°C
Note
1. The algebraic convention where the less positive (more negative) limit is
designated minimum is used in this data sheet for common mode input
voltage and threshold voltage levels only.
j.lA9679
Electrical Characteristics Over recommended operating temperature and supply voltage ranges, unless
otherwise specified.
Driver Section
Symbol
Characteristic
Condition
VIH
Input Voltage HIGH
VIL
Input Voltage LOW
VIC
Input Clamp Voltage
11=-18mA
I VOD11
Differential Output Voltage
10=0 V
RL=100
Typ1
Max
2.0
.n
IVOD21
Differential Output Voltage
.-I
ov~
n!IOL
J 'i
(+)
!
lOti
(-)
9·152
3750
JlA9679
Parameter Measurement Information (Cont.)
Figure 4 Driver Differential Output Delay and Transition Times
IN
GENERATOR
(Note 1)
son
J:'SV
!no
1.]
3V
OV
!no
"""",....,90%=...--
~ 2.SV
OIlT
Figure 5 Drive Propagation Times
IN
2.3V
RL=27n
~>-"""'''''''-OUT
y
OIlT
GENERATOR
(Note 1)
ENABLED
(Note 3)
Figure 6
Z
OIlT
Driver Enable and Disable Times (tpZH. tpHZ)
, -_ _.oSI
---C>--r---t--
OVor3V
OIlT
IN
RL= 110n
GENERATOR
(Note 1)
d. 'j
J.9
sv
H
son
OIlT
3V
OV
..... ..:..L-VOH
2.3V
O.SV
VOFF""'OV
Figure 7
Driver Enable and Disable Times (tpZL. tpLZ)
sv
RL= loon
IN
~>-"""'''''''-OUT
d.
sv
3V
ov
~r
OUT
l.j
-1IpLZr/SV
~SV
t
9-153
VOL
}.tA9679
Parameter Measurement Information (Cont.)
Figure 8 Receiver Propagation Delay Times
-d.
5V
IN
1.)
3V
OV
~:
~
OUT
1.3V
ENABLED _ _ _ _ _ _ _...J
VOH
1.3V
VOL
(Note 3)
Figure 9 Receiver Enable and Disable Times
51
o--5V
IPZH
.
-cE
IPZL
(1IA9679)~.
INPUT
1.5V
((lA9679)~
3V S1t01.5V
INPUT
S2 OPEN
S3CLOSED
OV
VOH
--.I
INPUT
1.5V
~
PHZ
O.5V
OUTPUT
IPLZ
IpHZ
_9~3V
~~~4.5V
~VOL
OUTPUT
- - OV
("'-7 )
S2 CL05ED
OV S30PEN
1.5V
OUTPUT
3V 5110 -1.5V
1.5V
("A9679)~
<-.
S1101.5V
S2 CLOSED
INPUT.l
3V 511o-1.5V
1.5 V
52 CL.OSED
\
OV S3CLOSED
OV S3 CLOSED
PLZ
~
--~1.3V
VOH
OUTPUT
--~1.3V
O.5Y
VOL
Notes
1. The input pulse is supplied by a generator having the following
characteristics: PRR = 1.0 MHz, duty cycle"'50%, t,';; 6.0 ns, tf';; 6.0 ns,
Zo=50n.
2. CL includes probe and stray capaCitance.
3. ,.A96178 Enable is active low, ,.A96177 Enable is active high.
4. All diodes are 1N916 or equivalent.
9-154
OAC08
8-Bit Multiplying
01 A Converter
FAIRCHIL.D
A Schlumberger Company
Linear Division Data Acquisition
Description
Connection Diagram
16-Lead DIP
(Top View)
The DAC08 is an 8-bit multiplying digital-to-analog converter constructed using the Fairchild Planar Epitaxial process.
Advanced circuit design achieves very high speed performance with outstanding applications capability and low
cost.
• Fast Settling Time To 1/2 LSB 85 ns
• Full Scale Current Prematched To ± 1 LSB
• Direct Interface To TTL, CMOS, ECL, HTL, PMOS,
DTL
• Linearity To ± 0.19% Max Over Temperature Range
• High Output Compliance -10 V To +18 V
• True And Complemented Outputs
• Wide Range Multiplying Capability
• Low Full Scale Current Drift + 10 ppml"C TYP
• Wide Power Supply Range ± 4.5 V To ± 18 V
• Low Power Consumption 33 mW at ± 5 V
• External Compensation For Max Bandwidth
• Low Cost
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Extended (DAC08M)
Commercial (DAC08C)
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, lOs)
Internal Power Dissipation 1. 2
16L-Ceramic DIP
16L-Molded DIP
V+ to VLogic Inputs
VLC
Reference
Reference
Voltage
Reference
Inputs (V14' V15)
Input Differential
(V14, V15)
Input Current IREF (14)
-65°C to + 175°C
-65°C to + 150°C
Order Information
Device Code
-55°C to +125°C
O°C to 70°C
DAC08DM
DAC08EDC
DAC08EPC
DAC08CDC
DAC08CPC
300°C
265°C
1.50 W
1.04 W
36 V
V- to (V-) + 36 V
V- to V+
V- to V+
± 18 V
5.0 mA
Notes
1. TJ Max
= 150°C
for the Molded DIP, and 175°C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 16L·Molded DIP at 8.3 mwrc, the 16L·Ceramic DIP at
10 mW/oC.
10-3
Package Code
78
78
98
78
98
Package Description
Ceramic DIP
Ceramic DIP
Molded DIP
Ceramic DIP
Molded DIP
•
DAC08
Block Diagram
LSB
B8
MSB
V+
COMP
61
B2
B3
B4
B5
B7
B6
V-
DAC08, DAC08E, and DAC08C
Electrical Characteristics TA = O°C to 70°C for the DAC08E and DAC08C, -55°C to + 125°C for the DAC08;
Vee = ± 15 V, IREF = 2.0 mA. Output characteristics refer to both lOUT and lOUT.
Symbol
Characteristic
Min
Condition
Typ
Max
RESO
Resolution
B.O
B.O
B.O
MONO
Monotonicity
B.O
B.O
B.O
NL
Nonlinearity
ts
tpLH
Settling Time
Propagation Delay
DACOB, DACOBE
±0.19
DACOBC
±0.39
To ± h LSB, all bits
switched, ON or OFF
TA = 25°C
TA = 25°C
tpHL
I
B5
135
B5
150
Each bit
35
60
All bits switched
35
60
DACOB
I DACOBE/C
±10
TCIFS
Full Scale Temperature
Coefficient
Vac
Output Voltage Compliance
Full scale current change
Ra > 20 mil
IFS4
Full Scale Current
VREF = 10.000 V, R14 , R15 = 5.000 kil,
TA = 25°C
IFSS
Full Scale Symmetry
IFs4 -I Fs2
Izs
IFSR
Zero Scale Current
Output Current Range
VIL
Logic Input Voltage LOW
VIH
Logic Input Voltage HIGH
IlL
Logic Input Current LOW
< 1,12
LSB,
-10
Unit
bits
bits
% FS
ns
ns
ppmrC
+1B
V
1.990
2.Q40
mA
DACOB/E
± 1.0
±B.O
pA
DACOBC
±2.0
±16
DACOB/E
0.2
2.0
DACOBC
0.2
4.0
1.940
p.A
mA
R14. 15 = 5.000 kil
VREF = + 15.000 V, V- = -10 V
2.1
VREF=+25.000 V, V-=-12 V
4.2
VLC = 0 V
O.B
V
-10
p.A
2.0
VLC=O V, VI=-10 V to +O.B V
10-4
-2.0
DAcoa
DAC08 Series (Cant.)
Electrical Characteristics TA = O°C to 70°C for the DAC08E and DAC08C, -55°C to + 125°C for the DAC08;
Vee = ± 15 V, IREF = 2.0 rnA. Output characteristics refer to both lOUT and lOUT.
Symbol
Characteristic
Min
Condition
IIH
Logic Input Current HIGH
VI=+2.0 V to +18 V
VIS
Logic Input Swing
V- =-15 V
VTHR
Logic Threshold Range
Vee=±15 V
115
Reference Input Bias
Current
dl/dt
Reference Current Slew
Rate
PSSIFS+
Power Supply Sensitivity
Typ
pA
-10
+18
V
-10
+13.5
V
-3.0
pA
4.0
8.0
V+ = +4.5 V to + 18 V,
IREF = 1.000 mA
0.01
0.002
0.01
Vee = ± 5.0 V, IREF = 1.000 mA
11+
V+ = +5.0 V, IREF = 2.000 mA,
V- = -15 V
I1+
Vee=±15 V, IREF = 2.000 mA
1Power Consumption
Pc
mAillS
0.0003
V- = -4.5 V to -18 V,
IREF = 1.000 mA
Power Supply Current
Unit
10
-1.0
PSSIFS1+
Max
0.002
2.3
3.8
-4.3
-5.8
2.4
3.8
-6.4
-7.8
2.5
3.8
-6.4
-7.8
33
48
V+ = +5.0 V, V- =-15 V,
IREF = 2.000 mA
108
136
Vee = ± 15 V, IREF = 2.000 mA
135
174
Vee = ± 5.0 V, IREF = 1.000 mA
%/%
mA
•
mW
Typical Performance Curves
Full Scale Current vs
Reference Current
Reference Input
Frequency Response
5.0
e-
TA
4.0
~
I
...z
w
'"'":J
0
...:J
...
:J
..
3.0
2.0
/
0
1.0
V
°°
SMALL SIGNAL
VI = 50 mVp-p
CENTERED AT 200 mY
=T"'N Tb TJAX
ALL BITS "HIGH"
;I
/
V
V
V
..
VI
I
...
~
v- = -15V
~
l'LlMITFOR
1-
/
- = j"0J-
'"
2.0
3.0
REFERENCE CURRENT -
4.0
5.0
mA
~
LARGE SIGNAL
VI = 2.0 Vp-p
CENTERED AT 1.0 V
-6
-10
t
-I'
C-VR'i = i V'tf = 15
0.1
0.2
0.5
FREQUENCY -
Note
1. Positive common mode range is always (V +) -1.5 V
10-5
MHz
2.0
1.6
VL'S IV
v- =
I
II
-S.O
v
IREF = 2.0mA
~ 1.2
o
\
2.0
ffi
§'"
o
:J
\
r
2.4
....
\
1.0
ALL BITS "ON"
V~ = -IJV
I
~
R14 = R15 = 1.0 kO
!-RL~500n
TA = TMIN TO TUAX
2.•
\
II
ALL BITS "ON"
1.0
"
-2
!50
w
>
3.2
-
./ \
III
LIMIT FOR
Reference AMP Common Mode
Range (Note 1)
5.0
0.8
IREF = 1.0 mA_
I
I I
0.4
10
°
~
IREF = 0.2 mA-
4
~
4
6
ro
t-r--
N
REFERENCE COMMON MODE VOLTAGE -
U
V
DAC08
Typical Performance Curves (Cont.)
Output Current vs Output Voltage
(Output Voltage Compliance)
3.2
~
2.4
I-
2.0
I
Z
V-·-15V
1.6
!:;
1.'
0
0.8
.."S"
II
[
w
II:
II:
16
I
v_J-S.O~
1.6
1.'
E
u
IREF
~
= 1.0 mA
r-...
14
~
I
-50
50
~
ALL BITS "HIGH" OR "LOW"
II
0.6
~
IAr'I2.°j'
~- ~
~- r - -":I-
8:
i
->
0.4
0.'
I-
Z
II:
II:
4.0
,
'A,""I ·O j
IREF
2.0
""
,-
=O.2mA
4.0
-4.0
,-
.. -15V
8.0
IREF
= 2.0mA
5.0
W
4.0
~ 3.0
."
8:
,.
B4
,.
Y+=+1SY
'.0
1.0
I
011
-1'
B3
I
,-
~
B'
V~
8.0
I
f il :lI:
150
oc
Supply Current vs
Temperature
7.0
Bl
100
8.0
Z
0
50
TEMPERATURE -
I-
II:
II:
!:;
-4.0
ALL B'TS "H'GH" OR "LOW"
20
"
o
o
.....0
-8.0
-1'
-16
NEGAnVE SUPPLY VOLTAGE -
LOGIC INPUT VOLTAGE - V
V
-20
-50
50
TEMPERATURE -
100
150
oc
Supply Current vs
Positive Supply Voltage
8.0
ALL BITS "HIGH" OR "LOW"
1-
~ 8.0
I
ffi
~
4.0
~
~..
,.
Note
1. B1 through B8 have identical transfer characteristics. Bits are fully
switched, with less than 1/2 LSB error. At less than ± 100 mV from
actual threshold, these switching pOints are guaranteed to lie between
0.8 and 2.0 V over the operating temperature range (VLe - 0.0 V).
2.0
o
o
4.0
8.0
12
16
POSITIVE SUPPLY VOLTAGE -
20
V
10-6
-
re~"..g~~TVC~:~:~~· GRAPH.) -
-50
8.0
IAE~' 2.6mA
1.0
=-15 V
4.0
oc
Supply Current vs
Negative Supply Voltage
w 0.8
I-
RANGE FOR V-
-12
150
100
TEMPERATURE -
I-
."""
or-
-&.0
1.'
~
8.
J.eRJ'SS'~LE ~uJ.n. tOL~AGE I
IREF:52.0 mA
0.4
18
Bit Transfer
Characteristics (Note 1)
" f-
i!
~
0.8
OUTPUT VOLTAGE - V
1.4
~
!--
o.ZmA
10
r-...
I
o
r-
I= I
IREF
>
,;
I
0.4
r-...
Vr·,5V
IIA'i' 2.imA
I
20
2.0
I
TA = TMIN TO TMAX
ALL BITS "ON"
2.8
Output Voltage Compliance vs
Temperature
VTH-VLC vs
Temperature
DAC08
Test Circuits
Figure 1 Settling Time Measurement
FOR TURN-ON, VL " 2.7 V
+SV
Yt.
FOR TURN-OFF, VL = 0.1 V
0.11-1F
1kOJ
J50~
+0.4 V
>--....- ....""""""-+---4
~~
PRO:?::
-0.4 v
R15
0.1
~J+15V
-15 V
Typical Applications
Figure 2 Basic Positive Reference Operation
MSB
LSB
B1 B2 B3 B4B5B6 B7BB
-
1
FS ""
RREF
x
255
256
IO+Io=IFS
For all logic states
IREF
VREF+
+YR..
14
RAEF
(R14)
10
DAC08
VAEF-
10
15
Yt.c
COMP
Cc
0.1 pF
For fixed reference, TTL operation,
typical values are:
VREF = +10.000 V
RREF
13
R15
-=
+VREF
=5.000 k
R15 "" RREF
Cc = 0.01 ,uF
VLe " 0 V (GROUND)
V+
10-7
DAC08
Typical Applications (Cont.)
Figure 3
Recommended Full Scale Adjustment Circuit
Figure 4
LOWT.C.
4.5kn
r-""",_-i14
--
, - -......-"""'_--114
IREF'" 2 mA
"'10 V
Basic Negative Reference Operation
DACOS
DACOS
R15
-VREF--'VI_-I15
50 kCl~--"~TlV!.-_-I15
POT
~5kO
Note
RREF sets IFs; R15 is for bias current cancellation.
Figure 5
Basic Unipolar Negative Operation
MSB
LSB
Bl B2 B3 B4 B5 B6 B7 B8
Eo
10
IREF
= 2.000 mA
14
DAC08
iii
5.000 kCl
-=
EO
B1
B2
B3
B4
B5
B6
B7
Full Scale
Full Scale - LSB
iO
B8
10 mA
Eo
Eo
1
0
1.992
1.984
.000
.008
-9.960
-9.920
.000
- .040
mA
Half Scale + LSB
Half Scale
Half Scale - LSB
1
1
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
1.008
1.000
.992
.984
.992
1.000
-5.040
-5.000
-4.960
-4.920
-4.960
-5.000
Zero Scale + LSB
Zero Scale
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
.008
.000
1.984
1.992
- .040
.000
-9.920
-9.960
10-8
DAC08
Typical Applications (Cont.)
Figure 6 High Noise Immunity Current To Voltage Conversion
Bl B2 B3 B4 B5 BI B7 BI
5k!l
IREF
=2mA
5kCl
+10Y
VAEF+
10
DACOI
VREF-
V+
Eo
10
v-
ec
VLC
5 kCl
5 kCl
C\,;:,.
-::-
ECY
':'
+15V -15V
':'
Provides isolation from ground loops
Symmetrical ± 10 V output
Useful within systems between boards
True complementary/differential current transmission
High speed analog signal transmission
B1
B2
B3
B4
B5
B6
B7
Pos Full Scale
Pos Full Scale - LSB
(+) Zero Scale
B8
Eo
1
0
+9.920
+9.840
1
0
0
0
0
0
0
1
0
0
H Zero Scale
+0.040
-0.040
Neg Full Scale + LSB
Neg Full Scale
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
-9.840
-9.920
Figure 7 Basic Bipolar Output Operation
10.000
IREF
= 2.000 mA =0;: 1.
DACOI
•
v
10.000 kCl
10
Eo
10 Eo
10.000 kCl
2
CflOV41F
B1
B2
B3
B4
B5
B6
B7
Pos Full Scale
Pos Full Scale - LSB
Zero Scale + LSB
Zero Scale
Zero Scale - LSB
1
0
Neg Full Scale + LSB
Neg Full Scale
0
0
B8
Eo
Eo
1
0
- 9.920
- 9.840
+10.000
+ 9.920
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
- 0.080
0.000
+ 0.080
+ 0.160
+ 0.080
0.000
0
0
0
0
0
0
0
0
0
0
0
0
1
0
+ 9.920
+10.000
- 9.840
- 9.920
10-9
•
DAC08
Typical Applications (Cont.)
Figure 8
Positive Low Impedance Output Operation
DAC08
For complementary output (operation as negative logic DAe).
connect inverting input of Op-Amp to 10 (Lead 2); connect 10 (Lead 4)
to ground.
Figure 9
Negative Low Impedance Output Operation
DACOS
IFS ....
~IREF
For complementary output (operation as negative logic DAC),
connect inverting input of Op-Amp to 10 (Lead 2); connect 10 (Lead 4)
to ground.
Figure 10 Pulsed Reference Operation
+VAEF
I
ovJl...
I
~RREF
I
R,
I
OPTIONAL RESISTOR
FOR OFFSET INPUTS
-U-
14
REQ
Rp
DAC08
~200
..n..
TYPICAL VALUES:
R, =5kO
i-V. = 10V
10
":"
":"
":'
NO CAP
10-10
DAcoa
Typical Applications (Cont.)
Figure 11
Accommodating Bipolar References
+VREF
V,~
tF
+VAEF~W.....--;14
~WIr-""-I14
-Do-
A,
II~
DACOS
DACOS
A15 (OPTIONAL) 15
HIGH INPUT---.
IMPEDANCE
RREF "" R15
f,---15_ - - - I I
+VAEF must be above peak positive swing of VI
IREF ~ peak negative swing of II
Figure 12 Interfacing With Various Logic Families
TTL, DTL
YrH = 1.4 V
YrN =VLC + 1.4V
15 V CMOS, HTL, HNIL
YrH = 7.5 V
12VTO
15V
15 V
DAC08
10kO
PMOS
YrH=OV
•
1N4148
9.1kO
VLe
6.2 V
10 kO
ZENER
-5 V TO -10 V
10kO ECl
YrH' -1.29 V
10VCMOS
YrH = s.o v
DACOS
10V
6.2kO
VLe
VLe
3.6 kO
1N4148
r~1"F
3.9kO
1 kO
CR02840F
-5.2 V
CI'10285OF
Note
Do not exceed negative logic input range of DAC
10-11
OAC 14081 1508 Series
8-Bit Multiplying
01 A Converters
FAIRCHILD
A Schlumberger Company
Linear Division Data Acquisition
Description
The DAC1408/1508 Series are mOnolithic B-bit multiplying
digital-to-analog converters constructed using the Fairchild
Planar Epitaxial process. It is designed for use where the
output current is a linear product of an B-bit digital word
and an analog input vqltage. The DAC1408/150B Series
are lead-for-Iead replacements for the MC 140B and SSS
140B devices.
Connection Diagram
16-Lead DIP
(Top View)
16
NC
• Relative Accuracy ±0.19"1o Error Maximum DAC1408A
• 7 And 6-Blt Accuracy Available DAC1408B,
DAC1408C
• Fast Settling Time To 112 LSB - 85 ns
• Non-Inverting Digital Inputs are TTL And CMOS
Compatible
• Output Voltage Swing +0.5 V to -5.0 V
• High-speed Multiplying Input Slew Rate 4.0 mA//.ls
• Standard Supply Voltages +5.0 V And -5.0 V To
-15 V
• Low Full Scale Current Drift + 10 ppmrC Typically
• Low Power Consumption 33 mW at ± 5 V
• Low Cost
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Extended (DAC1508M)
Commercial (DAC140BC)
Lead Temperature
Ceramic DIP (soldering. 60 s)
Molded DIP (soldering. 10 s)
Internal Power Dissipation 1, 2
16L-Ceramic DIP
16L-Molded DIP
V+
VDigital Input Voltage (5 Vto 12 V)
Applied Output Voltage
Reference Current (114)
Reference Amplifier Inputs (V14. V1S)
COMP
GND
VREF-
v-
VREF+
v+
lOUT
(MSB) Al
A8(LSB)
A2
A7
A3
A6
A4
AS
Order Information
-65°C to + 175°C
-65°C to + 150°C
-55°C to + 125°C
O°C to +70°C
1.50 W
1.04 W
5.5 V
-16.5 V
5.5 V
0.5 V to -5.2 V
5.0 mA
5.5 V. -16.5 V
Device Code
DAC140BADC
DAC140BAPC
DAC140B8DC
DAC14088PC
DAC1408CDC
DAC1408CPC
DAC1508DM
Package Code
78
98
78
98
78
98
78
Package Description
Ceramic DIP
Molded DIP
Ceramic DIP
Molded DIP
Ceramic DIP
Molded DIP
Ceramic DIP
Equivalent Circuit
Al
A2
A3
A4
AS
AS
A7
A8
GND
Notes
VR ...
1. TJ Max = 1S0·C for the Molded DIP, and 17S·C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 2S·C. Above this temperature,
derate the 16L·Molded DIP at 8.3 mW rc, the 16L-Ceramic DIP at
10 mwrC.
-i-.-------,
V+
REFERENCE
CURRENT
AMPUFIER
VREF--+---I
COMP
-V-
CURRENT SOURCE PAIR
10-12
DAC1408/1508 Series
DAC1408/1508 Series
Electrical Characteristics T A = O°C to 70°C for the DAC1408, -55°C to + 125°C for the DAC1508;
V+ = +5.0 V, V- = -15 V, VREF/R14 = 2.0 mA. All digital inputs at HIGH logic level.
Symbol
E,
Max
Unit
DAC140SAlDAC150S
± 0.19
%
DAC140SB 1
±0.39
DAC140SC1
±0.7S
Characteristic
Min
Condition
Relative Accuracy (Error Relative
to Full Scale 10)
Y2
ts
Settling Time to Within
(Includes tpLH)
LSB
tpLH. tpHL
Propagation Delay
TClo
Output Full Scale Current Drift
VIH
Logic Input Voltage HIGH
VIL
Logic Input Voltage LOW
Typ
TA = 25°C2
S5
135
ns
TA = 25°C
30
100
ns
±20
ppm 1°C
2.0
V
O.S
IIH
Logic Input Current HIGH
VIH = 5.0 V
0
0.04
IlL
Logic Input Current LOW
VIL = O.S V
-0.4
-O.S
115
Reference Input Bias Current
-1.0
-5.0
pA
lOR
Output Current Range
mA
V- =-5.0 V
0
2.0
2.1
V- = -6.0 to -15 V
0
2.0
4.2
1.9
1.99
2.1
mA
4.0
pA
-0.55,
+0.4
V
10
Output Current
VREF = 2.000 V, R14 = 1.0
10 Min
Output Current
All bits LOW
Voc
Output Voltage Compliance
E,~0.19%
at
kn
0
V- =-5.0 V
TA = 25°C
V- below -10 V
dl/dt
Reference Current Slew Rate
PSRR (-)
Output Current Supply Sensitivity
1+
Supply Current
-5.0,
+0.5
4.0
Power Supply Voltage Range
Power Consumption
2.7
pAN
+22
mA
-7.5
-13
+4.5
+5.0
+5.5
-4.5
-15
-16.5
All bits LOW, V- = -5.0 V
105
170
305
TA = 25°C
VRPc
mAlps
+13.5
0.5
All bits LOW
1VR+
mA
All bits LOW. V- = -15 V
190
All bits HIGH, V- = -5.0 V
90
All bits HIGH, V- = -15 V
160
Notes
1. All current switches are tested to guarantee at least 50% of rated
output current.
2. All bits switched.
10-13
V
mW
•
DAC1408/1508 Series
Test Circuits
Figure 1 Notation Definitions
Typical values: R14
~
R15
~
1k
VREF ~ .20 V
Co 15 pF
V1 and 11 apply to inputs A1 thru AS
The resistor tied to lead 15 is to temperature compensate the bias
current and may not be necessary for all applications.
10
~ K [-~. ~'L + -'iF-' ~:
+~+~+R+Ml
32
64
128 256
~----------~-~~TPUT
RL
where K
~
VFI'l't
and An • "1" if An is at HIGH level
An • "0" if An is at LOW level
Figure 2 Relative Accuracy Test Circuit
MSB
A1
A2
A3
12-BIT
D/A
0 TO 10 V OUTPUT
CONVERTER
AS
(±o.o2%
A6 ERROR MAX)
SkO
A7
I
A4
..--ro-
..-
A8
A9A10A11A12
5OkO
LSBllll
VREf"'2V
1000
--~
1
1/
WO.1'#~
/zA714
r
R14
9500
MSB 14
13
5
-::-
6
7
8
8-BIT
COUNTER
•
DAC1408
SERIES
~
10
11
12
LSBofffII
1.0kO
-
c
V-
-= ":;"
10-14
ERROR
(1V.1%)
DAC1408/1508 Series
Test Circuits (Cent.)
Figure 3 Transient Response and Settling Time
V+
V,
1.4 V
+2..0 V
14
tf =
1.01<0
15
It::; 10 ne
0.1 pF-
USE RL TO GND FOR
TURN OFF
MEASUREMENT
V,
DAC1408
1 '0"'"
SERIES
~::~~;;T~IME
(ALL BITS SWITCHES
LOW TO HIGH)
10
11
SETTLING TIME
FOR FIGURE 1
16
1. = 300 na TYPICAL
Vo
TO t1i2 LBS
12
TRANSIENT
RESPONSE
-~If-............- - -...... 15 pF 1_co';; 25 pF
5.1 0 ....
0.1 pF-
"'"
V-
Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Tracking al d Converters
Successive Approximation aId Converters
2 112 Digit Panel Meters and DVMs
Waveform Synthesis
Sample and Hold
Peak Detector
Programmable Gain and Attenuation
CRT Character Generation
Audio Digitizing and Decoding
Programmable Power Supplies
Analog-Digital Multiplication
Digital-Digital Multiplication
Analog-Digital Division
Digital Addition and Subtraction
Speech Compression and Expansion
Stepping Motor Drive
10-15
DAC1408/1508 Series
Applications (Cont.)
Figure 5
Negative VREF
V+
Figure 4 Positive VREF
V+
RI4
~
RI4
~
RIS
.,.....
RIS
+VREF
AI
A2
14
S
6
-=
A3
AI
DACI408
SERIES
A2
A4
A3
A4
AS
A6 10
AS
A6 10
A8 12
A7 II
A7 II
C
A8 12
y-
V-
Figure 6
Use with Current-to-Voltage Converting OP AMP
VREF
V+
MSB
5
AI
Theoretical YO
= 2.0 VdC
RI4 = RI5 • 1.0 kQ
Ro = 5.0 kQ
YREF
t'1,-,4_-",,,,,_--VREF
RI4
A2
A5
A6
SERIES
A7
A8
10
A3
A4
A6
A7
AS
J
Adjust VREF R14 or Ra so that Va with all digital inputs at HIGH
level is equal to 9.961 Volts.
DACI408
AS
A2
+"32+ &\+ 128+ 2ss-
A3
A4
[AI
Va· Ri4(Ro) 2+4+8+16
2V
Va • Ti( (5 k)
RO
[,
1
1
1
2" + "4
+ "8 + 16
'1
11
12
1
1
1
+32+64+128+256
Vo
• 10 V
~~~
V-
10-16
= 9.961
V
,uA565
Digital to Analog Converter
FAIRCHILD
A Schlumberger Company
Linear Division Data Acquisition
Description
The J.LA565 is a fast 12-bit digital-to-analog converter combined with a high stability voltage reference on a single
monolithic chip. The J.LA565 chip uses 12 precision, high
speed bipolar current steering switches, control amplifier,
laser-trimmed thin film resistor network, and buried zener
voltage reference to produce a high accuracy analog output current.
Connection Diagram
24-Lead DIP
(Top View)
NC
NC
V+
The internally buried zener reference is laser-trimmed to
10 V with a ± 1% maximum error. The reference voltage
is available externally and can supply up to 1.5 mA beyond that required for the reference and bipolar offset resistors.
REF OUT (+10 V ± 1%)
ANALOG COM
REFERENCE IN
VBIPOLAR OFFSET IN
The chip also contains additional SiCr thin film resistors
which can be used either with an external op amp to provide a precision voltage output or as input resistors for a
successive approximation AID converter. The resistors are
matched to the internal ladder network to guarantee a low
gain temperature coefficient and are laser-trimmed for minimum full scale and bipolar offset errors.
DAC OUT
13
BIT 12 (lSB) IN
The J.LA565 is available in four performance grades. The
J,LA565J and J,LA565K are specified for use over the 0 to
70°C temperature range, and the J,LA565S and J.LA565T are
specified for the -55°C to + 125°C range.
Order Information
Device Code
Package Code
J.LA565SJM
J.LA565TJM
J.LA565JJC
J.LA565KJC
•
•
•
•
•
•
Single Chip Construction
Very High Speed, Settles To 1/2 LSB In 200 ns
Full Scale Switching Time - 30 ns
High Stability Buried Zener Reference On Chip
Monotonicity Guaranteed Over Temperature
Linearity Guaranteed Over Temperature - 112 LSB
Max (J,lA565K)
• Low Power, 225 mW Including Reference
10-17
7R
7R
7R
7R
Package Description
Ceramic (Side Brazed)
Ceramic (Side Brazed)
Ceramic (Side Brazed)
Ceramic (Side Brazed)
•
J.LA565
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Extended (/JA565M)
Commercial (1JA565C)
Lead Temperature
Ceramic (Side Brazed)
(soldering, 60s)
Internal Power Dissipation 1, 2
24L-Ceramic (Side Brazed)
V+ to Digital Common
V- to Digital Common
Analog Common to Digital Common
Voltage on DAC Output (Lead 9)
Digital Inputs (Leads 13 to 24) to
Digital Common
Ref In to Analog Common
Bipolar Offset to Analog Common
10 V Span R to Analog Common
20 V Span R to Analog Common
Ref Out
-55°C to +125°C
O°C to +70°C
2.50 W
OVto+18V
o V to -18 V
Notes
1. TH!ax=175"C.
2. Ratings apply to ambient temperature at 25"C. Above this temperature,
derate at 16.7 mWrC.
Block Diagram
REF OUT
BIPOLAR OFFSET IN
V+
,.A56S
9.95 kO
20VSPAN
5kO
10 V SPAN
19.95kO
REF IN
5kO
--
CAC
10
ANALOG
COMMON
10 = 4
lit
IREF
)I
8kO
CODE
.".
CODE INPUT
V-
DIGITAL
COMMON
"::"
MSB
INPUT BITS 1-12
10-18
~
LSB
DAC
OUT
± 1.0 V
-3.0 V to +12 V
-1.0 V to +7.0 V
± 12 V
± 12 V
± 12 V
± 12 V
Indefinite Short
to either Common
Momentary Short
to V+
MA565S/J and MA565T/K
Electrical Characteristics TA=+25°C, V+ =+15 V, V-=-15 V, unless otherwise specified. 1
!lA565T/K 1
IlA565S/J 1
Symbol
Characteristic
Units
Condition
Min
VIH
VIL
IIH
IlL
Data Input
Voltage
Logic "1"
Bit ON
Logic "0"
Bit OFF
Data Input
Current
Logic "1"
Bit ON
Logic "0"
Bit OFF
Unipolar
All bits ON (Fig 1)
RESO
Resolution
IFS
Output
Current
Typ
2.0
5.5
Min
Typ
2.0
0.8
120
Bipolar
Output Resistance
(exclusive of span
resistors)
IlS
Output
Offset
All bits ON or OFF
(Fig 2)
Max
5.5
0.8
120
260
35
75
35
75
12
Bits
-2.0
-2.4
-1.6
-2.0
-2.4
mA
± 0.8
± 1.0
± 1.2
± 0.8
± 1.0
± 1.2
6.0
8.0
10
6.0
8.0
10
-1.6
Unipolar
(Fig 1)
0.01
0.05
0.01
0.02
Bipolar
R2 = 50 n fixed
(Fig 2)
0.05
0.15
0.05
0.1
Co
Output Capacitance
Voe
Output Compliance
Voltage
EA
Accuracy (error relative
to full scale)
TA
to
Min
-1.5
IMax
to TA
+10
± 1,14
±h
± 1,18
± 1,14
(0.012)
(0.003)
(0.006)
:r4
± 1,14
± 1,12
(0.018)
(0.006)
(0.012)
:r4
± 1,14
± 1,12
(0.012)
± 1,12
Differential Nonlinearity
TA
Min
to TA
Max
+10
(0.006)
± 1,12
Max
-1.5
±
±
IlA
kn
% of FS
pF
25
25
IMin
V
260
12
Ro
DNL
Max
V
LSB
% of FS
LSB
% of FS
LSB
Monotonicity
Guaranteed
Monotonicity
Guaranteed
TCllS
Temperature Coefficient
of Unipolar Zero
TA
Min
to TA
Max
1.0
2.0
1.0
2.0
ppm/oC
TCllS
Temperature Coefficient
of Bipolar Zero
TA
Min
to TA
Max
5.0
10
5.0
10
ppmrC
TCIFS
Temperature Coefficient
of Gain (Full Scale)
TA
Min
to TA
Max
15
30
10
20
ppm/oC
TCONL
Temperature Coefficient
of Differential Nonlinearity
TA
Min
to TA
Max
2.0
ts
Settling Time to h LSB
All Bits ON-to-OFF
or OFF-to-ON
200
10-19
ppmrC
2.0
400
200
400
ns
•
J.LA565
IlA565S/J and IlA565T/K (Cant.)
Electrical Characteristics TA= +25°C, V+ = + 15 V, V- = -15 V, unless otherwise specified. 1
1lA565S/J 1
Symbol
Characteristic
Units
Min
tpLH
Full Scale Transition
tpHL
1+
Power Requirements
IPSSIFS
POR
Power Supply Sensitivity
Typ
Typ
Min
30
15
30
90% to 10%
Delay plus Fall
Time
30
50
30
50
V+ =+13.5 V to
+16.5 V
3.0
5.0
3.0
5.0
V- = -13.5 V to
-16.5 V
-12
-18
-12
-18
V+ =+15 V,
± 10%
3.0
10
3.0
10
V- =-15 V,
± 10%
15
25
15
25
o to
o to
+5.0
-2.5 to +2.5
o to
-10 to +10
V
± 0.25
± 0.1
± 0.25
% of FS
± 0.05
± 0.15
± 0.05
± 0.1
± 0.25
Izs Rl
Bipolar Zero
Adjustment Range
± 0.15
± 0.15
Current (avail. for
external loads)
IREF
Pc
V
± 0.1
± 0.25
Voltage
V
+ 10
-10 to +10
Gain Error with
Fixed 50 IJ.
Resistor for R2
Gain Adjustment
Range
Reference Output
V
15
20
25
15
20
25
9.90
10.00
10.10
9.90
10.00
10.10
1.5
2.5
1.5
2.5
Power Consumption
225
Note
1. TA Min and TA Max are aoc and 70 0 e for J and K grade, and -55°C to
+ 125°C for Sand T grade.
10-20
ppm of
FS/%
-5.0 to +5.0
IFS R2
VREF
mA
-5.0 to +5.0
Bipolar Zero Error
with Fixed 50 IJ.
Resistor for R1
Reference Input
Impedance
ns
V
+5.0
-2.5 to +2.5
+ 10
Izs Rl
ZI
Max
15
Programmable Output
Range
External Adjustments
Max
10% to 90%
Delay plus Rise
Time
o to
IFS R2
1lA565T/K 1
Condition
345
225
kIJ.
V
mA
345
mW
MA565
Typical Performance Curve
Typical Applications
Typical Negative Compliance Range vs
Negative Supply
Buffered Voltage
The standard current-to-voltage conversion connections using an operational amplifier are shown in Figure 1 with the
preferred trimming techniques. If a low offset operational
amplifier (1lA714L, 1lA725A) is used, excellent performance
can be obtained in many situations without trimming (an
op amp with less than 0.5 mV max offset voltage should
be used to keep offset errors below 1,12 LSB). If a 50 n
fixed resistor is substituted for the 100
trimmer, typically
the unipolar zero will be within ± 1,12 LSB (plus op amp
offset), and full scale accuracy will be within 0.1 % (0.25%
max). Substituting a 50 n resistor for the 100 n bipolar
offset trimmer will give a bipolar zero error typically within
±2 LSB (0.05%).
n
Y ~
/(=-2mA
10 = 0 mA
The 1lA771 is recommended for buffered voltage output
applications which require a settling time to ± 1,12 LSB of
two microseconds. The feedback capacitor is shown with
the optimum value for each application; this capacitor is
required to compensate for the 25 pF DAC output capacitance.
16.5 V
13.5 V
NEGATIVE SUPPLY -
v-
Figure 1 0 V to + 10 V Unipolar Voltage Output
+15 V
+15 V
V+
BIPOLAR
OFFSETIN 8
9.95kO
-=
,-_+11'--,20 V SPAN
-=-
SkQ
10
5 kO
DAC
-
10
10 = 41{ IREF x CODe
DAC
8kO OUT
2.4kO
CODE INPUT
V-
-15V
DIGITAL
COMMON
(NOTE 1)
12
-=
MSB - - - - - - - -__
.. LSB
Note 1
Digital and analog common must have a common current return path.
*See typical applications continued for proper connections.
10-21
•
pA565
This unipolar configuration (Figure 1) will provide a unipolar
+ 10 V output range. In this mode, the bipolar terminal, lead 8, should be grounded if not used for trimming.
Please note that it is not necessary to trim the op amp to
obtain full accuracy at room temperature. In most bipolar
situations, an op amp trim is unnecessary unless the untrimmed offset drift of the op amp is excessive.
o to
Step I, Zero Adjust
Turn all bits OFF and adjust zero trimmer, R1, until the
output reads 0.000 volts (1 LSB = 2.44 mY). In most cases this trim is not needed, but lead 8 should then be
connected to lead 5.
The /lA565 can also be easily configured for a unipolar
to + [) V range or ± 2.5 V and ± 10 V bipolar ranges
by using the additional 5 kil application resistor provided
at the 20 V span R terminal, lead 11. For a 5 V span (0
to + 5 or ± 2.5), the two 5 kil resistors are used in parallel by shorting lead 11 to lead 9 and connecting lead 10
to the op amp output and the bipolar offset either to
ground for unipolar or to REF OUT for the bipolar range.
For the ± 10 V range (20 V span) use the 5 kil resistors
in series by connecting only lead 11 to the op amp output
and the bipolar offset connected as shown. The ± 10 V
option is shown in Figure 3.
oV
Step II, Gain Adjust
Turn all bits ON and adjust 100 il gain trimmer, R2, until
the output is 9.9976 V. (Full scale is adjusted to 1 LSB
less than nominal full scale of 10.000 V.) If a 10.2375 V
full scale is desired (exactly 2.5 mY/bit), insert a 120 il
resistor in series with the gain resistor at lead 10 to the
op amp output.
Figure 2 bipolar configuration, will provide a bipolar output
voltage from -5.000 V to +4.9976 V, with positive full
scale occurring with all bits ON (all "1"s).
Internal/External Reference Use
The /.lA565 has an internal low-noise buried zener diode
reference which is trimmed for absolute accuracy and temperature coefficient. This reference is buffered and optimized for use in a high speed DAC and will give
long-term stability equal or superior to the best discrete
zener reference diodes. The performance of the /lA565 is
specified with the internal reference driving the DAC since
all trimming and testing (especially for full scale and bipolar) are done in this configuration.
Step I, Offset Adjust
Turn OFF all bits. Adjust 100 il trimmer R1, to give
-5.000 V output.
Step II, Gain Adjust
Turn ON all bits, adjust 100 il gain trimmer, R2, to give a
reading of +4.9976 V.
Figure 2 ± 5 V Bipolar Voltage Output
REf OUT
Rl
100 II
+15 V
V+
3
BIPOLAR
OfFSET IN 8
"A565
R2
lOO11
11
9.95kll
5 kll
10
DAC
10
=4 w IREF., CODE
CODE INPUT
DIGITAL
COMMON
V(NOTE 1)
-15 V
12
-=-
..
MSB -
10-22
LSB
20V SPAN
-=-
10VSPAN
MA565
circuit is shown in Figure 4. The input line can be modelled as a 30 kU resistance connected to -0.7 V rail.
The JlA565 can be used with an external reference, but
may not have sufficient trim range to accommodate a reference which does not match the internal reference.
Application of Analog and Digital Commons
The J.LA565 brings out separate analog and digital grounds
to allow optimum connections for low noise and high
speed performance. The two ground lines can be separated by up to 200 mV without any loss in performance.
There may be some loss in linearity beyond that level. Up
to ± 1.0 V can be tolerated between the ground lines without damage to the device. If the JlA565 is to be used in
a system in which the two grounds will be ultimately connected at some distance from the device, it is recommended that parallel back-to-back diodes be connected
between the ground lines near the device to prevent a
fault condition.
The internal reference has sufficient buffering to drive external circuitry in addition to the reference currents required for the DAC (typically 0.5 mA to REF IN and
1.0 mA to BIPOLAR OFFSET IN, if used). A minimum of
1.5 mA is available for driving external circuits. The reference is typically trimmed to ± 0.2%, then tested and guaranteed to ± 1.0% max error. The temperature coefficient is
comparable to that of the full scale TC for a particular
grade.
Digital Input Considerations
The J.LA565 uses a standard positive true straight binary
code for unipolar outputs (all" 1"s give full scale output),
and an offset binary code for bipolar output ranges. In the
bipolar mode, with all "0" s on the inputs, the output will
go to negative full scale; with 100... 00 (only the MSB
on), the output will be 0.00 V; with all "1 "s, the output
will go to positive full scale.
The analog common at lead 5 is the ground reference
point for the internal reference and is thus the "high quality" ground for the J.LA565: it should be connected directly
to the analog reference point of the system. The digital
common at lead 12 can be connected to the most convenient ground reference point; analog power return is preferred, but digital ground is acceptable. If digital common
contains high frequency noise beyond 200 mY, this noise
may feed through the converter, so that some caution will
be required in applying these grounds.
The threshold of the digital input circuitry is set at 1.4 V
and does not vary with supply voltage. The input lines can
interface with any type of 5 V logic, TTL/DTL or CMOS,
and have sufficiently low input currents to interface easily
with unbuffered CMOS logiC. The configuration of the input
Figure 3 ± 10 V Bipolar Voltage Output
+15 V
Y+
Rl
1000
BIPOLAR
OFFSET IN
3
R2
8
lOY
11
9.95 kO
1000
20YSPAN
5kO
+-_-¥10:"'10Y SPAN
5 kO
DAC
10
=4
II
IREF
DAC
OUT
II
81<0
CODE
2.41<0
CODE INPUT
7
DIGITAL 12
Y_ COMMON
-15 Y (NOTE 1) ":"
MSB
- - - - - - - - - <..~
10-23
LSB
•
iJA565
Output Voltage Compliance
The 1JA565 has a typical output compliance range from
-2 V to + 10 V. The current-steering output stages will be
unaffected by changes in the output terminal voltage over
that range. However, there is an equivalent output impedance of 8k in parallel with 25 pF at the output terminal
which produces an equivalent error current if the voltage
deviates from analog common. This is a linear effect
which does not change with input code. Operation beyond
the compliance limits may cause either output stage saturation or breakdown which results in nonlinear performance. Compliance limits are not affected by the positive
power supply, but are a function of output current and
negative supply.
Figure 4 Equivalent Digital Input Circuit
DIGITAL INPUTS
(LEADS 13 TO' 24)
I
r.".
SPF
DIGITAL...!
COMMON
30kQ
'" -0.7 V
TO LOGIC
'"
CR02500F
10-24
J,lA571
Analog to Digital Converter
FAIRCHIL.D
A Schlumberger Company
Linear Division Data Acquisition
Description
Connection Diagram
18-Lead DIP
(Top View)
The MA571 is a 10-bit successive approximation AID converter consisting of a DAC, voltage reference, clock, comparator, successive approximation register and output
buffers - all fabricated on a single chip. No external components are required to perform a full accuracy 10-bit conversion in 25 J.Ls.
18
BIT 10LSB
17 "'DA"":rAMR""ETlAD"'Y
18
DIGITAL COM
15
BIPOLAR OFFSET
14
ANALOG COM
BIT 8
BIT 7
The device offers true 10-bit accuracy and exhibits no
missing codes over its entire operating temperature range.
BIT 6
BIT 5
Operation is guaranteed with -1 5 V and + 5 V to + 15 V
supplies. The device will also operate with a -12 V supply.
BIT4
BIT 3
BIT 2
Operating on supplies of + 5 V to ± 15 V, the MA571 will
accept analog inputs of 0 V to + 10 V unipolar, or ± 5 V
bipolar, externally selectable. As the BLANK and
CONVERT input is driven LOW, the 3-state outputs will be
open and a conversion starts. Upon completion of the
conversion, the DATA READY line will go LOW and the
data will appear at the output. Pulling the BLANK and
CONVERT input HIGH blanks the outputs and readies the
device for the next conversion. The J.LA571 executes a
true 10-bit conversion with no missing codes in approximately 25 J.Ls.
V+
MSB BIT 1
Order InfC?rmation
Device Code
J.LA571SJM
MA571JJC
J.LA571KJC
Package Code
Package Description
FD
FD
FD
Ceramic (Side Brazed)
Ceramic (Side Brazed)
Ceramic (Side Brazed)
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Extended (MA571 M)
Commercial (MA571C)
Lead Temperature
Ceramic (Side Brazed)
(soldering, 60 s)
Internal Power Dissipation 1, 2
18L-Ceramic (Side Brazed)
V+ to Digital Common
V- to Digital Common
Analog Common to Digital Common
Analog Input to Analog Common
Control Inputs
Digital Outputs (Blank Mode)
The J.LA571 is available in two versions for the O·C to
+ 70·C temperature range, the J.LA571 J and K. The
J.LA571S guarantees lO-bit accuracy and no missing codes
from -55·C to + 125·C. All three grades are packaged in
an 18-lead ceramic side brazed package.
•
•
•
•
•
•
Complete AID Converter With Reference And Clock
Fast Successive Approximation Conversion - 25 J.LS
No Missing Codes Over Temperature
Digital Multiplexing - 3-State Outputs
18-Lead Ceramic Side Brazed Package
Low Cost Monolithic Construction
-65·C to + 175·C
-55·C to + 125·C
O·C to +70·C
300·C
1.74 W
+7 V
-16.5 V
±1 V
± 15 V
o to V+
o to V+
o to
o to
Notes
1. TJ Max~ 17S"C.
2. Ratings apply to ambient temperature at 2S"C. Above this temperature,
derate at 11.6 mWrC.
10-25
•
IlA571
Block Diagram
DIGITAL
V+
V-
COMMON
I
I
I
BU(
(C!IilV)
'[
I
...
B+C
I-
SIeO
~
ANALOG IN
I-
,
1'"
~
~
~
-*" ..-
10-BIT
CURRENT
OUTPUT
DAC
+
COMPARAT,A
f-
lO-BIT
SAA
~
r-----'
I
I
f-
!NT
I
I CLOCK
IL _____ JI
- -----
--~
f-
1
I
I
TEMPERATURE COMPENSATED
BURIED ZENER REFERENCE
AND DAC CONTROL
L....
~
~
~
t
DATA
OUTPUTS
L
....
fBIPOLAR
OFFSET
BIT 1
L
......
~
....
ANALOG
COMMON
MSB
t
'L
......
'L
LSB
BIT 10
3-STATE
BUFFERS
I
DATAREADV
EOO0451F
10·26
J.lA571
~571J
and IlA571K
Electrical Characteristics TA = 25°C, TA Min = O°C, TA Max = 70°C, V+ = + 5.0 V, V- = -15 V, all voltages
measured with respect to digital common, unless otherwise specified.
/.lA571J
Symbol
Characteristic
Min
Condition
Typ
/.lA571K
Max
Min
Typ
Max
10
10
Resolution
EA
Relative Accuracy 1
VFS
Full Scale Calibration 2
Vzs
Unipolar Offset
± 1.0
±Y2
Bipolar Offset
± 1.0
±Y2
TA
Min
to TA
± 1.0
Max
Differential Nonlinearity
TCvzs
Temperature Coefficient
of Unipolar Offset
25°C to TA
Temperature Coefficient
of Bipolar Offset
25°C to TA
Temperature Coefficient
of Full Scale Calibration
25°C to TA Min or TA Max,
with 15 n. Resistor or
50 n. Trimmer
TCVFS
PSRR
Power
Supply
Rejection
Ratio
CMOS Pos
Supply
±13.5
TTL Pos
Supply
+4.5
Negative
Supply
-16.5
9.0
Max
Min
Min
or TA
or TA
Max
Max
V~V+ ~+16.5
V~V+ ~5.5
10
± 1.0
44
22
±2.0
± 1.0
44
22
±4.0
±2.0
88
44
± 1.0
V
3.0
5.0
±2.0
± 1.0
±2.0
± 1.0
LSB
ppm/oC
LSB
ppml"C
LSB
7.0
3.0
7.0
kn.
10
0
10
V
-5.0
+5.0
-5.0
+5.0
5.0
Analog Input Impedance
VIR
Analog
Input
Ranges
Unipolar
Output
Coding
Unipolar
Positive True
Binary
Positive True
Binary
Bipolar
Positive True
Offset Binary
Positive True
Offset Binary
OC
LSB
ppm/oC
0
ZI
Bipolar
LSB
Bits
±2.0
V
V
V~V+ ~-13.5
LSB
10
10
TA Min to TA
LSB
±Y2
±2.0
±2.0
With 15 n. Resistor in
Series with Analog Input
DNL
TCvzs
±Y2
± 1.0
Units
Bits
RESO
IOL
Output Sink Current
Va = 0.4 V Max,
TA Min to TA Max
3.2
3.2
mA
10H
Output Source Current3
(Bit Outputs)
Va = 2.4 V Min,
TA Min to TA Max
0.5
0.5
mA
BC IIH
Output Leakage When
Blanked
±40
10-27
±40
/.lA
•
MA571
J.LA571J and J.LA571K (Cont.)
Electrical Characteristics TA = 25°C, TA Min = O°C, TA Max = 70°C, V+ = + 5.0 V, V- = -15 V, all voltages
measured with respect to digital common, unless otherwise specified.
J.lA571J
Symbol
BC IlL
Characteristic
Blank & Convert Input
Condition
Min
Typ
o VOOOO:~I:fmxs
yvvOOOOO
1'lt:/IX._ _ _....;~y
CRO~620F
•
10-33
MA9650
FAIRCHILD
4-Bit Current Source
A Schlumberger Company
Linear Division Data Acquisition
Description
The !1A9650 is a high speed 4-bit precision current
source, intended for use in DI A and AID converters with
up to 12-bit accuracy. It is constructed on a single silicon
chip, using the Fairchild Planar Epitaxial process and consists of a reference transistor and four logic operated precision current sources connected to a single output
summing line. Logic inputs are fully TTL compatible under
all temperature and supply conditions. A clamp circuit is
provided to prevent turn-on latch up on the reference input.
•
•
•
•
Connection Diagram
16-Lead DIP
(Top View)
16
V+
MSB OUT
BIT 2 OUT
BIT 3 OUT
200 ns Settling Time (12 ± 1/2 LSB)
Variable Bit Currents
Reference Compensation
TTL Compatible
VREF2
LSB OUT
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Internal Power Dissipation 1. 2
16L-Ceramic DIP
Logic Input Voltage
V+
VMSB Current
VREF Inputs
Output (VREF voltage ;;;. -7.0 V)
-65°C to + 175°C
O°C to +70°C
lOUT
IREF
300°C
1.50 W
+5.5 V
+7 V
-18 V
2.0 mA
+7 V to V+18 V to VREF
Notes
1. TJ MAX = 175"C.
2. Ratings apply to ambient temperature at 25"C. Above this temperature,
derate the 16L-Ceramic DIP at 10 mW"C.
Order Information
Device Code
Package Code
!1A96501 DC
!1A96502DC
IlA96503DC
6B
6B
6B
Package Description
Ceramic DIP
Ceramic DIP
Ceramic DIP
Truth Table
Logic
Input
Nominal
Output
Current (mA)
Logic
Input
Nominal
Output
Current (mA)
0000
0001
0010
0011
0100
0101
0110
0111
1.875
1.750
1.625
1.500
1.375
1.250
1.125
1.000
1000
1001
1010
1011
1100
1101
1110
1111
0.875
0.750
0.625
0.500
0.375
0.250
0.125
0.000
I-IA9650 Kits Required to Build DI A-AID
Converters
Temperature Range
O°C to +70°C
Type And No. of Unit
96501C
96502C
96503C
0
0
1
0
1
1
2
2
1
Accuracy to:
8 Bits
10 Bits
12 Bits
10-34
J,tA9650
Equivalent Circuit
BIf3
IN
LS8
IN
BIT 2
MS8
IN
IN
vAl
SIlO
A3
12110
03
A4
1110
AS
8110
04
AI
A2
2.5 110
3.3 110
AI
1110
...
AIO
2AkCl
2.3 kCl
All
2.5 110
Q2
lOUT
I...
GND
... (1.2)
L-~-----;------+-~-----;r-----~-+------t-----~--~~~4---~r-V
A14
120
L-----4-----~----+-----~~--_+------~----t_----~~--_+------_+----~--+-v-
LSB
OUT
BITS
OUT
BIT 2
OUT
10-35
USB
OUT
AEF
OUT
J,lA9650
~A96501C· ~A96502C· ~A96503C
Electrical Characteristics TA = 25°C, V+ = 5.0 V, V- = -15 V, unless otherwise specified.
Symbol
EA
IFSER
PSCIFS
Characteristic
Accuracy
Full Scale Output Current Error
Power Supply Coefficient of
Full Scale Output Current
VSE
VSE Range
hFE
hFE of Reference Transistor
Zo
Output Impedance
Condition
(J.tA9650 1C)
Min
Typ
-
Max
Unit
±0.01
% of
IFS
(J.tA96502C)
±0.05
(J.tA96503C)
±0.2
(IlA96501C)
±0.1
(J.tA96502C)
±0.2
(IlA96503C)
±0.4
(J.tA9650 1C)
±0.003
(J.tA96502C, J.tA96503C)
± 0.012
620
%
%IV
mV
1000
All Bits On
5.0
Mn
The following specifications apply for O°C";;; T A ,,;;; 70°C
EA
IFSER
Accuracy
Full Scale Output Current Error
(IlA96501C)
±0.025
(MA96502C)
±0.1
(J.tA96503C)
±0.3
(IlA96501C)
0.2
(IlA96502C)
0.3
(J.tA96503C)
0.6
% of
IFS
%
PSSIFS
Power Supply Sensitivity of
Full Scale Output Current
(IlA96501C)
±0.006
(J.tA96502C, J.tA96503C)
±0.024
VIL
Input Voltage LOW
Each Bit On
VIH
Input Voltage HIGH
Each Bit Off
IlL
Input Current LOW
VIL = 0.4 V
-1.6
IIH
Input Current HIGH
VIH = 2.4 V
40
J.tA
10
Output Current
Bit 1 (MSB)
2.0
mA
0.8
2.0
10
Vo
Output Current
Output Voltage
Bit 2
0.5
1.0
Bit 3
0.25
0.5
0.125
0.25
(IlA96501C)
5.0
250
(J.tA96502C, J.tA96503C)
5.0
500
All Bits Off
Reference Current
mA
nA
Feeding Op Amp Summing Junction
Resistive Load
IR
V
V
1.0
Bit 4 (LSB)
%IV
Using Compensation Transistor
10-36
0
-4.0
V
V+
1.0
mA
MA9650
1-/A96501C 'IlA96502C '1-/A96503C (Cont.)
Electrical Characteristics TA = 25°C, V+
Symbol
5.0 V, V-
=
Characteristic
-15 V, unless otherwise specified.
=
Condition
Min
Typ
Max
± 1.0
Current
Unit
±2.2
mA
IVR
VREF
ILiM
Reference Limit Current
VREF=
75
mA
1+
Positive Supply Current
(pA96501 C, pA96502C)
8.0
mA
(pA96503C)
10
1-
Negative Supply Current
20
0 V
(pA96501C, pA96502C)
-11
(pA96503C)
-15
mA
Typical Performance Curves
Switching Time vs
MSB Current (50% In to 10% Out)
Settling Time vs
Load Resistance (0 to FSI Output
± 1'2 LSB)
Output Current Settling Time vs
MSB Current (0 to FSI Output
± 1'2 LSB)
1.0
175
70
SUMMING JUNCTION LOAD
r-~:= ~:~
80
TA= :l5"C
---
~
1 onA IISB CURRENT
r-V+=5.0V
BUMMING JUNCTION LOAD
150 _~+. 5.0 V
V-=-15V
TA = 2$OC
t
I
!:It
I
25
o
o
1••
1.0
2.0
1.8
1.4
Input Logic Threshold Voltage vs
Ambient Temperature
2.00
"-
>
I 1.50
~~
1.25
gl.oo
I~
~
1.305
~ 1.300
~
1.295
1.285
0.25
-75
1.280
0
25
50
10
Full Scale Output Current Drift vs
Ambient Temperature
75
AMBIENT TEMPERATURE-'C
100
125
M~B
IlonA
CJRREJ..
-Y+_ 5.0Y
v-= -15 V
----
i--
l/
/
4.5
-14
,...
I--
V
/
11.280
o.so
T"1 1O PfRL I
~
~
I"-
TLnl2 Eo/LSBI_
! .....
o.ooa
>
V ./
LOAD RESISTANCE-lin
TAo II 2f5OC
'r--...
-25
2.0
•
v: V
~~
o
o
1.310
0.75
-50
1.•
1.315
v-= -15V
"
1.8
/
~
0.2
Input Logic Threshold Voltage vs
Supply Voltage
v+=s.ov
'r--...
~
.7
/'
MSB CURRENT-onA
MSB CURRENT -mA
1.75
v#
0.8
~G.4
... IT
10
1A
I'
;:
BIT
1.0
~ :2
V-a -15 V
0.8 r-TA= :l5"C
V
5.0
-15
SUPPLY VOLTAGE-V
10-37
5.5
-18
-O.ooa
-75 -50
-25
25
50
75
AMBIENT TEMPERATURE-"C
100
125
jJA9650
Typical DC Test Circuit (Note 1)
BIT INPUTS
V·
LSB
7
12
3
R8
100 k ±O.1%
51
R9
52
2 MSB
PRECISION
VOLTMETER
~A9650
8 11
13
14
ZERO
ADJUST
15 5
I
_--.J
R5
10k
R4
80 k
R3
R2
40k 20k
5M
5k
-=-
R1
10k
5k
V-
(NOTE 2)
-=-
Notes
1. All resistor values in ohms.
2. Required resistor ratio tolerances of R1- R5 to test the various grades
are as follows: io---~_IcIP
0 ~
V
OUT
_
'---1:; ~
Cora ,.------
1/48002~~~
oJ----------.........-SERIALDATA
L-...
..-+--4---1-------+------'
1/4~n
CLOCK
1/r_
.....
"
y
EOAoA,A.
""_
HIT ADDRESSABLE LATCH
C01234567
LJ
~~~--------------~~ l:~~LEL
+-~~-+~
10V
VR£F
FULO.ADJ
____________________
__ OUT
~_____
~~-+~~4-+_--------------------+_----MSB
""728
312
5k
--LSB
ak
~
""m
2 _
aa
~
~
4:0.1 pF
J
30pF
1000
FDmf ::S~FDm
~
-=-
T
2k
ANALOG
INPUT
V
J,
10-40
220 k
-15 V
5k
Note.
1. All resistor values in ohms.
2. Digital GND indicated by
Analog GND indicated by
15k
100k
1k
--=-
IlA224 0
Programmable
Timer/Counter
FAIRCHILD
A Schlumberger Company
Linear Division Special Functions
Connection Diagram
16-Lead DIP
(Top View)
Description
The IJA2240 Programmable Timer/Counter is a monolithic
controller capable of producing accurate microsecond to
five day time delays. Long delays, up to three years, can
easily be generated by cascading two timers. The timer
consists of a time-base oscillator, programmable 8-bit
counter and control· flip-flop. An external resistor capacitor
(RC) network sets the oscillator frequency and allows delay times from 1 RC to 255 RC to be selected. In the
astable mode of operation, 255 frequencies or pulse patterns can be generated from a single RC network. These
frequencies or pulse patterns can also easily be synchronized to an external. signal. The trigger, reset and outputs
are all TTL and DTL compatible for easy interface with
digital systems. The timer's high accuracy and versatility in
producing a wide range of time delays makes it ideal as a
direct replacement for mechanical or electromechanical devices.
00
Vee
o.
REGULATOR
our
TlIlE-BASE
our
RESISTORI
CAPACrroR IN
MODULATION
IN
TRIGGER
IN
RESET
•
•
•
•
•
•
•
•
Accurate Timing From Microseconds To Days
Programmable Delays From 1 RC To 255 RC
TTL, DTL And CMOS Compatible Outputs
Timing Directly Proportional To RC Time Constant
High Accuracy
External Sync And Modulation Capability
Wide Supply Voltage Range
Excellent Supply Voltage Rejection
GND
Order Information
Device Code
!lA2240DC
!lA2240PC
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1, 2
16L-Ceramic DIP
16L-Molded DIP
Supply Voltage
Output Current
Output Voltage
Regulator Output Current
-65°C to + 175°C
-65°C to + 150°C
O°C to 70°C
300°C
265°C
1.50 W
1.04 W
18 V
10 mA
18 V
5.0 mA
Notes
1. TJ Max -150·C for the Molded DIP, and 175·C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 25·C. Above this temperature,
derate the 16l-Ceramic DIP at 10 mW'·C, and the 16l-Molded DIP at
8.3 mWrC.
11-3
Package Code
78
98
Package Description
Ceramic DIP
Molded DIP
•
J.LA2240
Block Diagram
v~-t~-----------------------.----,
RI
5kCl
R
M~~ -t-+------1
R2
8.59 kQ
RESET
L...---1__ TRIGGER IN
GND
TB OUT
O.
O.
0,28
I~------------~~------------~a~I~"~---------C~~;R----------a.I~"r---~a~I~~g~
..
~A2240C
Electrical Characteristics TA = 25°C, Vee = 5.0 V, R = 10 k.Q, C = 0.1
Symbol
Characteristic
~F,
unless otherwise specified.
Condition
Unit
General Characteristic
Vee
Supply Voltage
For Vee <;;;4.5 V, Short Lead 15 to
Lead 16
Icc
Supply
Current
Vee = 5.0 V, VTR = 0 V, VRS = 5.0 V
Vee = 15 V, VTR = 0 V, VRS = 5.0 V
Total Circuit
4.0
Counter Only
VREG
Regulator Output
15
V
4.0
7.0
rnA
13
18
1.5
I
I
Measured at Lead 15
Vee=5.0 V
3.9
4.4
Vee = 15 V
5.8
6.3
6.8
3.5
5.0
V
Time-Base
tAee
Timing Accuracy 1
VRS = 0, VTR = 5.0 V
Lltl LlT
Temperature Drift
O°C <;;; TJ <;;; 75°C
Lltl LlV
Supply Drift
Vee ~ 8.0 V (See Performance Curves)
fMax
Max Frequency
R = 1.0 kQ, C = 0.007 /.IF
VMOD
Modulation Voltage Level
Measured at Lead 12
RT
Recommended Range of
Timing Components Timing
Resistor
I Vee = 5.0 V
IVee = 15 V
I Vee = 5.0 V
IVee = 15 V
(See Performance Curves)
11-4
200
%
ppmfOC
80
0.08
0.3
130
2.80
3.50
%/V
kHz
4.20
V
10.5
0.001
10
MQ
MA2240
IlA2240C (Cont.)
Electrical Characteristics TA = 25°C, Vee = 5.0 V, R = 10 kS1, C = 0.1 IlF, unless otherwise specified.
Symbol
CT
Characteristic
Condition
Timing Capacitor
Min
Typ
0.01
Max
Unit
1000
J.l.F
Trigger/Reset Controls
VTR
Trigger Threshold
Measured at Lead 11, VRS = 0 V
1.4
ITR
Trigger Current
VRS = 0 V, VTR = 2.0 V
10
JJ.A
ZT
Trigger Impedance
25
kS1
Time2
tRSPT
Trigger Response
VRS
Reset Threshold
Measured at Lead 10, VTR = 0 V
VTR = 0 V, VRS = 2.0 V
IR
Reset Current
ZR
Reset Impedance
tRSPT
Reset Response Time2
2.0
1.0
1.4
V
J.l.s
2.0
V
10
JJ.A
25
kS1
0.8
J.l.S
1.5
MHz
20
kS1
Counter
TRMax
Max Toggle Rate
ZI
Input Impedance
VTH
Input Threshold
tr
Output Rise Time
Measured at Lead 14
VRS = 0 V, VTR = 5.0 V
1.0
Measured at Leads 1 through 8
RL = 3.0 kS1, CL = 10 pF
tf
Fall Time
10-
Sink Current
VOL <0.4 V
ICEX
Leakage Current
VOH=15 V
1.4
V
180
ns
180
2.0
4.0
0.01
Notes
1. Timing error solely introduced by 1lA2240 measured as % of ideal
time·base period of T - RC.
2. Propagation delay from application of trigger (or reset) input to
corresponding state change in counter output at Lead 1.
11-5
mA
15
J.l.A
J,LA2240
Typical Performance Curves
Supply Current vs
Supply Voltage in Reset Condition
16
10M,--r-;
,/
I
ffi
a
'"
/
/
6
~
~
1.0M
./
~ 12
il!
/
4
V
1.0K
o
o
10
12
14
16
18
100
SUPPLY VOLTAGE - V
•
POOa090F
Minimum Trigger/Retrigger Timing
vs Timing Capacitor
Time-Base Period Drift vs
Supply Voltage
3.0
100~R~=-'0~M~Q-r---r--70~~~
3.0
750C
250C
!!.
;F.
%
~
I
I 2.5
....
e
a
a
~
w
O"C
.
~ 2.0
::>
W
1.5
w
2.0
...........
\
ii:
~
w
750C
.......
:E
.~
1.0
0
~
0:
"....a:
1000
TIMING CAPACITOR - p.F
Minimum Trigger Pulse Width vs
Trigger and Reset Amplitude
CI
Time-Base Period vs
External RC
Recommended Range of
Timing Component Values
;:: 10
0:
W
~
~
co
25·C-
w
:E
;::
O·C
"....S!
-
0:
C = 0.1 ""
-
w 1.0
R = 10kO
~1.0
'"
0:
r---
W
"S!....
0:
MINIMUM TRIGGER DELAY
A _ _ TIME SUBSEQUENT TO
APPLICATION OF POWER
MINIMUM RETRIGGER
:E
::>
:E
Z
1.0
1.0
iii
-2.0
1.5
2.0
2.5
10
4
3.0
SUPPLY VOLTAGE -
TRIGGER OR RESET AMPLITUDE - V
Normalized Change in Time-Base
Period vs Modulation Voltage
12
I
a
"
a
~
a:
o
:;l
:E 1.0
0:
0
Y
Z
0.5
V
...............
w
/
:E
;::
...0
-1.0
"~:r:
-2.0
-3.0
1
MOOULAnON VOLTAGE -
R=~
"
o
V
i
~=1kn
w
./
o
1.0
~
...............
co
25
50
75
TEMPERATURE - OC
11-6
100
Yee!,5Y
;F.
1.0
.'"
/
!j!
10
jJ.F
2.0
~
Yee 5 V
C =0.1 IJ.F
ii:
~
w
Yee=51
;:: 1.5
1.0
Time-Base Period vs
Temperature
0
z
i
RESET INPUT
0.1
TIMING CAPACITOR -
2.0
;F.
B - - TIME SUBSEQUENT TO A
.01
0.01
V
Time-Base Period vs
Temperature
2."
2.0
14
"
100
illt=
...o
-1.0
--
c=
j' ""
-~
R=10M~
w
i'"
-2.0
" -3.0
o
25
50
TEMPERATURE _
75
0
C
100
J,tA2240
Functional Description
(Figure 1 and Block Diagram)
When power is applied to the jAA2240 with no trigger or
reset inputs, the circuit starts with all outputs HIGH. Application of a positive going trigger pulse to trigger lead 11,
initiates the timing cycle. The trigger input activates the
time-base oscillator, enables the counter section and sets
the counter outputs LOW. The time-base oscillator generates timing pulses with a period T = 1 RG. These clock
pulses are counted by the binary counter section. The timing sequence is completed when a positive going reset
pulse is applied to Reset, lead 10.
In most timing applications, one or more of the counter
outputs are connected to the reset terminal with S1
closed (Figure 3). The circuit starts timing when a trigger
is applied and automatically resets itself to complete the
timing cycle when a programmed count is completed. If
none of the counter outputs are connected back to the
reset terminal (switch S1 open), the circuit operates in an
astable or free running mode, following a trigger input.
Once triggered, the circuit is immune from additional trigger inputs until the timing cycle is completed or a reset
input is applied. If both the reset and trigger are activated
simultaneously, the trigger takes precedence.
Reset (R) (lead 10) sets all outputs HIGH.
Important Operating Information
Ground connection is lead 9.
Trigger (TRIG) (lead 11) sets all outputs LOW.
Time-base output (TBO) (lead 14) can be disabled by
bringing the RG input (lead 13) LOW via a 1.0 kn resistor.
Figure 2 gives the timing sequence of output waveforms
at various circuit terminals, subsequent to a trigger input.
When the circuit is in a reset state, both the time-base
and the counter sections are disabled and all the counter
outputs are HIGH.
Normal TBO (lead 14) is a negative going pulse greater
than 500 ns.
Figure 1 Logic Symbol
13
11
Figure 3
12
TRIG
VREG
Basic Circuit Connection
for Timing Applications
Monostable: S1 Closed
Astable: S1 Open
15
r----------------,-----~c
10
RL
10kO
R
1412345678
0.01 "F
C
Vee = Lead 16
GND = Lead 9
J
TRIGGER
JL
J
13
12
RC
MOD
11 TRIG
Figure 2 Timing Diagram of Output Waveforms
~n
I-~..u_-------
_____
..L..._
hnnnnnnnnnnnr""
1j.JUUUUlJUUlJlJl.Uo..L..J
........~....................
h
I
I
I
I
I
15
20 kO
47kO
LEAD 11
~'~BASE
LEAD 14
I
tLn.n..n..n..n._1
b
VREG
JL
TRIGGER
IIN
I I" III"" I" "II" III "
h
pA2240
RESET
'I_I_I
---I
~~~NTER
LEAD 1
1 T < To < 255 T
WHERE T RC
=
LEAD 2
TRIGGER
-I"LLEAD 3
~
-I To I-
LEAD 4
LEAD 5
11-7
•
J.LA2240
Note: Under the conditions of high supply voltages
(Vee> 7.0 V) and low values of timing capacitor
(CT < 0.1 MF), the pulse width of TBO may be too narrow
to trigger the counter section. Thi~ can be corrected by
connecting a 600 pF capacitor from TBO (lead 14) to
ground (lead 9).
The time-base can be synchronized by setting T to be an
integer multiple of the sync pulse period (Ts). This can be
done by choosing the timing components Rand C at lead
13 such that:
Reset (lead 10) stops the time-base oscillator.
where:
T = RC = (Ts/m)
m is an integer, 1.0';;; m';;; 10
Outputs (0 0 ... 0128) (leads 1 - 8) sink 2.0 mA current
with VOL';;; 0.4 V.
Figure 5 gives the typical pull-in range for harmonic synchronization for various values of harmonic modulus, m.
For m < 10, typical pull-in range is greater than ± 4% of
time-base frequency.
For use with external clock, minimum clock pulse amplitude should be 3.0 V, with greater than 1.0 MS pulse duration.
Circuit Controls
RC Terminal (lead 13)
The time-base period T is determined by the external RG
network connected to RC, lead 13. When the time-base is
triggered, the waveform at lead 13 is an exponential ramp
with a period T= 1 RG.
Counter Outputs (00 •.• 0128, leads 1 thru 8)
The binary counter outputs are buffered open collector
type stages, as shown in the block diagram. Each output
is capable of sinking 2.0 mA at 0.4 V VOL. In the reset
condition, all the counter outputs are HIGH or in the nonconducting state. Following a trigger input, the outputs
change state in accordance with the timing diagram of
Figure 2. The counter outputs can be used individually, or
can be connected together in a wired-OR configuration, as
described in the programming segment of this data sheet.
Time·Base Output (TBO, lead 14)
The time-base output is an open-collector type stage as
shown in the block diagram, and requires a 20 kn pull-up
resistor to lead 15 for proper circuit operation. In the reset
state, the time-base output is HIGH. After triggering, it produces a negative going pulse train with a period T = RG,
as shown in the diagram of Figure 2. The time-base output is internally connected to the binary counter section
and can also serve as the input for the external clock
Signal when the circuit is operated with an external time
base. The counter section triggers on the negative going
edge of the timing or clock pulses generated at TBO, lead
14. The trigger threshold for the counter section is
Reset and Trigger Inputs (R and TRIG, 10 and 11)
The circuit is reset or triggered with positive going control
pulses applied to leads 10 and 11 respectively. The
threshold level for these controls is approximately two diode drops ("'" 1.4 V) above ground. Minimum pulse widths
for reset and trigger inputs are shown in the Performance
Curves. Once triggered, the circuit is immune to additional
trigger inputs until the end of the timing cycle.
Figure 5 Typical Pull·ln Range for
Harmonic Synchronization
Modulation and Sync Input (MOD, lead 12)
The oscillator time-base period (T) can be modulated by
applying a DC voltage to MOD, lead 12 (see Performance
Curves). The time-base oscillator can be synchronized to
an external clock by applying a sync pulse to MOD, lead
12, as shown in Figure 4. Recommended sync pulse
widths and amplitudes are also given.
t 20
~
Figure 4 Operation with External Sync Signal
T•
o
..........
..J /4-0.3 T < T. < 0.8 T
=3\...
JLJ[ --L
~
0.1~
SYNC --;
IN
12
,.,42240
5.1 kO
I--Ts--j
o
o
11-8
i'--.r-..,
r---
10
RATIO OF TIME-BASE PERIOD TO
SYNC-PULSE PERIOD - Trrs
12
MA2240
Monostable Operation
'" + 1.4 V. The counter section can be disabled by clamping the voltage level at lead 14 to ground.
Precision Timing
In precision timing applications, the IlA2240 is used in its
monostable or self-resetting mode. The generalized circuit
connection for this application is shown in Figure 3. The
output is normally HIGH and goes LOW following a trigger
input. It remains LOW for the time duration (To) and then
returns to the HIGH state. The duration of the timing cycle
To is given as:
When using high supply voltages (Vee> 7.0 V) and a
small value timing capacitor (Or < 0.1 IlF), the pulse width
at TBO lead 14 may be too narrow to trigger the counter
section. This can be corrected by connecting a 600 pF
capacitor from lead 14 to ground.
Regular Output (VREG. lead 15)
The regulator output VREG is used internally to drive the
binary counter and the control logiC. This terminal can
also be used as a supply to additional 1lA2240 circuits
when several timer circuits are cascaded (see Figure 6) to
minimize power dissipation. For circuit operation with an
external clock, VREG can be used as the Vee input terminal to power down the internal time-base and reduce power dissipation. When supply voltages less than 4.5 V are
used with the internal time-base, lead 15 should be shorted to lead 16.
Figure 6
TO = nT= NRC
where T = RC is the time-base period as set by the
choice of timing components at RC lead 13 (see Performance Curves) and n is an integer in the range of
1 < n < 255 as determined by the combination of counter
outputs (00 ... 0128), leads 1 through 8, connected to the
output bus.
Low Power Operation of Cascaded Timers
Vee
Vee
R
Vee
RL
47 kO
30ko
i}
J
TRIGGER
.J'1..
L
I
TRIG
MOD
RC
,.A2240 #1
RESET ~r- R
Jl..
I
I
RC
MOD
TRIG
TBO 00 02 04
VAEG
a, 0,6032064 0128
11111 IllY
-
,.A2240 #2
Ii
Iii
r-
VAEG
r-
R
Tao 00 02 04 080160320640,28
I
OUT
150kO
Vee = Lead 16
GND = Lead 9
11-9
IlA2240
Counter Output Programming
The binary counter outputs, 0 0 ... 0 128 , leads 1 through 8
are open collector type stages and can be shorted together to a common pull-up resistor to form a wired-OR connection; the combined output will be LOW as long as any
one of the outputs is LOW. The time delays associated
with each counter output can be added together. This is
done by Simply shorting the outputs together to form a
common output bus as shown in Figure 3. For example, if
only lead 6 is connected to the output and the rest left
open, the total duration of the timing cycle, To, is 32 T.
Similarly, if leads 1, 5, and 6 are shorted to the output
bus, the total time delay is To = (1 + 16 + 32) T = 49 T. In
this manner, by proper choice of counter terminals connected to the output bus, the timing cycle can be programmed to be 1 T ~ To ~ 255 T.
In cascaded operation, the time-base section of Unit 2 can
be powered down to reduce power consumption by using
the circuit connection of Figure 6. In this case, the Vee
terminal (lead 16) of Unit 2 is left open, and the second
unit is powered from the regulator output of Unit 1 by
connecting the VREG (lead 15) of both units together.
Astable Operation
The J.lA2240 can be operated in its astable or free running
mode by disconnecting the reset terminal (lead 10) from
the counter outputs. Two typical circuits are shown in Figures 8 and 9. The circuit in Figure 8 operates in its free
running mode with external trigger and reset signals. It
starts counting and timing following a trigger input until an
external reset pulse is applied. Upon application of a positive going reset signal to lead 10, the circuit reverts back
to its reset state. This circuit is essentially the same as
that of Figure 3 with the feedback switch 81 open.
Ultra Long· Time Delay Application
Two /1A2240 units can be cascaded as shown in Figure 7
to generate extremely long time delays. Total timing cycle
of two cascaded units can be programmed from To = 256
RC to To = 65,536 RC in 256 discrete steps by selectively
shorting one or more of the counter outputs from Unit 2
to the output bus. In this application, the reset and the
trigger terminals of both units are tied together and the
Unit 2 time base is disabled. Normally, the output is HIGH
when the system is reset. On triggering, the output goes
LOW where it remains for a total of (256)2 or 65,536 cycles of the time-base oscillator.
The circuit of Figure 9 is deSigned for continuous operation. It self triggers automatically when the power supply is
turned on, and continues to operate in its free running
mode indefinitely. In astable or free running operation,
each of the counter outputs can be used individually as
synchronized oscillators, or they can be interconnected to
generate complex pulse patterns.
Figure 7 Cascaded Operation for Long Delays
Vee
Vee
Vee
RL
47 kO
R
10 kO
C
1 kO
MOD
RC
RC
TRIGGER
Jl...
",,2240 #2
REmrr--~~--+-------------------+---~~~~~~~~+-+-~----~--OUT
Jl...
47 kO
Vee = Lead 16
GND = Lead 9
11-10
MA2240
Binary Pattern Generation
In astable operation, as shown in Figure 8, the output of
the j.lA2240 appears as a complex pulse pattern. The
waveform of the output pulse train can be determined directly from the timing diagram of Figure 2 which shows
the phase relations between the counter outputs. Figures
10 and 11 show some of the complex pulse patterns that
can be generated. The pulse pattern repeats itself at a
rate equal to the period of the highest counter bit connected to the common output bus. The minimum pulse
width contained in the pulse train is determined by the
lowest counter bit connected to the output.
Figure 9
Free Running or
Continuous Operation (Note 1)
Vee
Vee
10 kll
Vee
RL
10 kll
R
C
0.01 pF
J
J
TRIG
RC
MOD
....2240
0.047pF
Figure 8 Operation with Trigger
and Reset Inputs (Note 1)
r---------....- - Vee
RL
10 kll
R
C
J:
~
TRIGGER
J1..
CR02970F
0.01 pF
RC
Figure 10 Binary Pulse Patterns Obtained
by Shorting Various Counter Outputs
MOD
TRIG
A. 2 LEAD PATTERNS
.JUUUUL
I1IlIlI"L-.JlIl
T
....2240
RESET
~!-I3T
J1..
= RC
-ITt-
1--8T--f-rr-/
LEADS 1 AND 2 SHORTED
B. 3 LEAD PATTERN
JULJlJl
rrn""---_
3T~5T+I ~1.:::==;21;:T·':-=-=-=-=-="::"'i"1
LEADS " 3, AND 5 SHORTED
Note
1. Vee = Lead 16
GND = Lead 9
11 -11
Figure 11
Vee
Continuous Free run Operation Examples of Output
vee
RC
MOD
-lRC\-
RC WAVEFOR"
n"E-8ASEOUTPUT
(h OUTPUT
rYYYYYY1/ /fYYYYYYY1
I I I I I I 1/ /
IIIIIIII
ruuu// LIU1.S1S
II-______
~~-lRCIIn____
I.
256RC
~~
..
I
.IlSLj
j----fiSL
I..
.1
256RC
j"'F,'~t//~
I--256RC
Vee'" Lead 16
GND:; Lead 9
..
I
F=L/j~
I..
~1
256RC
11-12
}1A3046 • J,LA3086
General Purpose
Transistor Arrays
FAIRCHILD
A Schlumberger Company
Linear Division Special Functions
Description
Connection Diagram
14-Lead DIP and 50-14 Package
(Top View)
The J.lA3046 and /.lA3086 are general purpose transistor
arrays. Each contains a differentially connected pair and
three individually isolated transistors. Each part is designed
for general purpose, low power applications for consumer
and industrial applications.
•
•
•
•
Low Input Offset Voltage
Wideband Operation
Low Noise
Matched Differential Amplifier
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP and SO-14
Operating Temperature Range
/.lA3046
/.lA3086
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP and SO-14
(soldering, 10 s)
Internal Power DisSipation 1, 2
14L-Ceramic DIP
14L-Molded DIP
SO-14
Collector-to-Emitter Voltage
Collector-to-Base Voltage
Collector-to-Substrate Voltage 3
Emitter-to-Base Voltage
Collector Current
(Each Transistor)
-65°C to + 175°C
-65°C to +150°C
O°C to +70°C
-40°C to +85°C
C1
C5
Bl
E5
SUBSTRATE
El,2
B5
B2
C4
C2
E4
B3
B4
E3
C3
Order Information
Device Code
1.36 W
1.04 W
0.93 W
15 V
20 V
20 V
5.0 V
50 mA
Package Code
Package Description
9A
KD
6A
9A
KD
Molded DIP
Molded Surface Mount
Ceramic DIP
Molded DIP
Molded Surface Mount
/.lA3046PC
/.lA3046SC
/.lA3086DV
/.lA3086PV
/.lA3086SV
Equivalent Circuit
E5
Notes
1. TJ Max = 150°C for the Molded DIP and SO-14. and 175°C for the
Ceramic DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature.
derate the 14L-Ceramic DIP at 9.1 mWfOC. The 14L·Molded DIP at
8.3 mW/oC, and the SO-14 at 7,5 mW/oC.
3. Substrate must be connected to the most negative voltage to maintain
C5
SUBSTRATE 85
C4
E4
B4
C3
B3
E3
04
normal operation.
Cl
11-13
Bl
E1,2
B2
C2
MA3046 • MA3086
IlA3046
Electrical Characteristics TA = 25°C unless otherwise specified.
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
V(SR)CSO
Collector-to-Base Breakdown
Voltage
Ic=10 /lA, IE=O
20
60
V
V(SR)CEO
Collector-to-Emitter Breakdown
Voltage
Ic = 1.0 rnA, Is = 0
15
24
V
V(SR)CIO
Collector-to-Substrate Breakdown
Voltage
Ic=10
/lA,
Ic=O
20
60
V
V(SR)ESO
Emitter-to-Base Breakdown
Voltage
IE= 10
/lA,
Ic=O
5.0
7.0
V
Icso
Collector Cutofl Current
VCS = 10 V, IE=O
0.002
40
nA
ICEO
Collector Cutoff Current
VCE = 10 V, Is=O
See
Curve
0.5
/lA
hIe
Static Forward Current-Transfer
Ratio (Static Beta)
VCE = 3.0 V
AIIO
Input Oflset Current for Matched
Pair 0 1 and 02 I hOI - 11021
VCE = 3.0 V, Ic = 1.0 rnA
VSE
Base-to-Emitter Voltage
VCE = 3.0 V
100
Ic=10 rnA
Ic = 1.0 rnA
Ic = 10
/lA
40
100
54
0.3
IE = 1.0 rnA
0.715
IE= 10 rnA
0.800
/lA
V
AVSE
Magnitude of Input Offset
Voltage for Differential Pair
IVSEI - VSE21
VCE = 3.0 V, Ic = 1.0 rnA
0.45
5.0
mV
AVSE
Magnitude of Input Offset
Voltage for Isolated Transistors
IVSE3- VSE41, IVSE4- VSESI,
IVSES - VSE31
VCE = 3.0 V, Ic = 1.0 rnA
0.45
5.0
mV
AVSE/AT
Temperature Coefficient of Baseto-Emitter Voltage
VCE = 3.0 V, Ic = 1.0 rnA
-1.9
mVloC
VCE(Sat)
Collector-to-Emitter Saturation
Voltage
Is = 1.0 rnA, Ic = 10 rnA
0.23
V
IAVlol/AT
Temperature Coefficient of
Magnitude of Input-Offset Voltage
VCE=3.0 V, Ic= 1.0 rnA
1.1
/lVloC
NF
Low Frequency Noise Figure
1= 1.0 kHz, VCE = 3.0 V,
Ic = 100 /lA, Rs = 1.0 kfl
3.25
dB
11-14
I1A3046 • I1A3086
J.LA3086
Electrical Characteristics TA = 25°C unless otherwise specified.
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
V(BR)CBO
Collector-to-Base Breakdown
Voltage
Ic=10 !lA, IE=O
20
60
V
V(BR)CEO
Collector-to-Emitter Breakdown
Voltage
Ic = 1.0 mA, IB = 0
15
24
V
V(BR)CIO
Collector-to-Substrate Breakdown
Voltage
Ic = 10 !lA, Ic = 0
20
60
V
V(BR)EBO
Emitter-to-Base Breakdown
Voltage
IE = 10
!lA, Ic = 0
5.0
7.0
V
ICBO
Collector Cutoff Current
VCB = 10 V, IE = 0
0.002
100
nA
ICEO
Collector Cutoff Current
VCE = 10V,IB=0
See
Curve
5.0
!lA
hie
Static Forward Current Transfer
Ratio (Static Beta)
VCE = 3.0 V
Ic=10 mA
Ic = 1.0 mA
Ic = 10 !lA
~IIO
Input Offset Current for Matched
Pair 01 and 02 11101 - 11021
VCE = 3.0 V, Ic = 1.0 mA
VBE
Base-to-Emitter Voltage
VCE = 3.0 V
100
40
100
54
0.3
IE = 1.0 mA
0.715
IE = 10 mA
0.800
!lA
V
~VBE
Magnitude of Input Offset
Voltage for Differential Pair
IVBE1- VBE21
VCE = 3.0 V, Ic = 1.0 mA
0.45
mV
~VBE
Magnitude of Input Offset
Voltage for Isolated Transistors
IVBE3- VBE41, IVBE4- VBE51,
IVBE5 - VBE31
VCE = 3.0 V, Ic = 1.0 mA
0.45
mV
~VBE/~T
Temperature Coefficient of Baseto-Emitter Voltage
VCE
-1.9
mY/DC
VCE(sat)
Collector-to-Emitter Saturation
Voltage
IB = 1.0 rnA, Ic = 10 rnA
0.23
V
I~Vlol/~T
Temperature Coefficient of
Magnitude of Input-Offset Voltage
VCE = 3.0 V, Ic = 1.0 rnA
1.1
!lVrC
NF
Low Frequency Noise Figure
f = 1.0 kHz, VCE = 3.0 V,
Ic = 100 !lA, Rs = 1.0 kS"l
3.25
dB
=
3.0 V, Ic = 1.0 rnA
11-15
•
MA3046 • MA3086
MA3046 and ~A3086
Electrical Characteristics T A = 25°C unless otherwise specified.
Symbol
Characteristic
Condition
Unit
Low Frequency, Small Signal Equivalent Circuit Characteristics
hIe
Forward Current Transfer
Ratio
hie
Short Circuit Input
Resistance
hoe
Open Circuit Output
Conductance
h,e
Open Circuit Reverse
Voltage Transfer Ratio
Yle
Admittance Characteristics:
Forward Transfer Admittance
110
f = 1.0 kHz, VCE = 3.0 V, Ic = 1.0 rnA
3.5
kS1
15.6
J..Imho
1.8 x 10- 4
31 - j1.5
f= 1.0 MHz, VCE=3.0 V, Ic= 1.0 rnA
0.3
+ jO.04
0.001
+ jO.03
Vie
Input Admittance
Yoe
Output Admittance
Y,e
Reverse Transfer Admittance
fT
Gain Bandwidth Product
VCE = 3.0 V, Ic = 3.0 rnA
500
MHz
0.6
pF
0.58
pF
2.8
pF
See
Curve
CEs
Emitter-to-Base Capacitance
VES = 3.0 V, IE = 0
CCS
Collector-to-Base
Capacitance
VCS = 3.0 V, Ic = 0
CCI
Collector-to-Substrate
Capacitance
Vcs = 3.0 V, Ic = 0
300
Typical Performance Curves
20
JOE=I3.JJ
-Rs =500n
=25°C
T.
15
20
,
l/~y~~
~.#j
~~
~
-
"~
'""-f-
Vdo='3.~V
-
As
TA
I.~
= 1000 n
.l~("I, -' f-----1
=2SOC
15
R~7
/
~'f
10
/
"~
lk~""
.-/
O.OS
0.1
0.2
COLLl!CTOR CURRENT -
0.5
rnA
,---JOE!
3.h J
,---!,s = 10 k!l
TA
I
a::
~
-
/
1.0
o
0.01
0.02
0.05
0.1
~,
~<:i
o~
/'
11-16
1.0
---=
0.01
0.02
/'"
/
-(kHz
./
o
0.5
rnA
V
V
V
0.2
/
Il-.~
/ , kHz
COLLECTOR CURRENT -
~,,-->~
:----
Q~'I'
10
/"
J:""
25<'C
15
10 kHz
0.02
25
~'ii
10';;;;
00.01
30
20
V
Q4?
~Q
~
10
Noise Figure vs
Collector Current
Noise Figure vs
Collector Current
Noise Figure vs
Collector Current
.......--r-
0.05
0.1
0.2
COLLECTOR CURRENT -
10kHz-
0.5
mA
1.0
J.lA3046 • J.lA3086
Typical Performance Curves (Cont.)
Forward Transfer Admittance vs
Frequency
I
.
Input Admittance vs
Frequency
COMM~~MITTER ClRC~IT,BA
N-E~lr E CIRCUIT, BASE I~~
C
1 30
w
IN.
r-T"VeE-• aOy
we
T• • WC YCE= aoY .. _
",,-!c = '.DmA
I - !If.
Output Admittance vs
Frequency
• '.DmA
-I
0:"
~~
20
.. !i!
~ iJ
10
~w
...
8 -20
0.1 0.2
0.5 1.0 2.0
'.0
5.0 10
20
50 100 200
'l!
"Z
-1.S
I"
~
8
0
10
20
50
FREQUENCY - MHz
100
'20
a: 110
I
~
f-~l.l Uv
"'~C
T
/
90
V
0:
a
80
o
V
0:
J0:
70
~
"
!i
Iii
"ty
'00
..
50
"
\,
hFE11
hFE2
.0
0.8
0.5 1.0
2.0
EMITTER CURRENT - mA
"l5V_ f--
'0
""II:
-
VeE
'0- 3
~
:::t
V
5V
10- 2
8
50
25
10-3
75
'00
o
'25
25
~~
!
0.5
5.0
10
D.'-75
VeE
=3V
100
'25
Static Base-to-Emitter Voltage and
Input Offset Voltage vs
Emitter Current
FOR DIFFERENTIAL PAIR AND
_ .... RED ISOLATED TRA~SISTORS7
VeE
~~~
e"
0.6
75
0.8
w
2
50
AMBIENT TEMPERATURE _ °C
0.9
~
= 10V
U 10-1
Base-to-Emitter Voltage Characteristic
vs Temperature for Each Transistor
6:;;
50 100 200
,Q2 ~18"0
~
I 0.8
0
~
0.05 0.1 0.2
zW
0:
0:
'DV
10-2
>
OR IhFE1
""E2[
V
0.01 0.02
,.,
10 20
Collector-to-Emitter Cutoff Current
vs Temperature for Each
Transistor
..
Vee'" 15
10-4 0
200
...,"'''''
s.o
I
~ 0.7
!
0.5 1.0 2.0
FREQUENCY - MHz
AMBIENT TEMPERATURE _ °C
Static Forward Current Transfer
and Beta Ratio for Transistors
01, 02 vs Emitter Current
o
0.1 0.2
11
~
"a:
0
!i0:
o
50 100 200
Vol"
r-IE"'O
i
~
II: ,0-,
_b.
" -2.0 ,
'0
I
,l.
-0.5
-1.0
g
5.0 10 20
..
LESS THAN 500 MHz
w"
O:z
0.5 1.0 2.0
Collector-to-Base Cutoff Current vs
Temperature for Each Transistor
"0:
Ilio
>w
/
/
FREQUENCY - MHz
1 1
= '.0 mA
.1, .( '+J..~cQUENCIES
g,. IS SMALL AT
Ii!~
lib
""
~~
0.1 0.2
MHz
i-~CE= '.0 V
0:"
W ..
o
~~M=M2~"tMITT~R CIRCUIT, BASE INjouT
Ic
V
'.L
Reverse Transfer Admittance vs
Frequency
0.5
I
I
/""
V
FREQUENCY -
I
w
.../
V
'"'
-10
E
E
we
Ie .'.0
II'
\.
--.
i:!
j
...
Vee-aOy
TA ".
,/
\.
0
i"
COMMON-EMITTER CIRCUIT, BASE INPUT
h
I~
~~
fo'
= 3.0 v
VeE
_ TA = 25'C
/
V
f--
I
,/
/
~ 8:~
~~"~
~~~~
-50
-25
25
50
75
AMBIENT TEMPERATURE _ °c
11-17
"
100
125
INPUT OFFSET VOLTAGE
0.'
0.01 0.02
II
0.05 0.1 0.2
"./
II
0.5 1.0
2.0
EMITTER CURRENT -
mA
o
5.0 10
MA3046 • MA3086
Typical Performance Curves (Cont.)
Input Offset Current for
Matched Transistor Pair
Q1, Q2 vs Collector Current
Input Offset Voltage for Differential
Pair and Paired Isolated Transistors
vs Ambient Temperature
..
0
10
5.0
VeE = 3.0 V
TA = 250C
>
~
2.0
~
1.0
i
0.5
E
I
o~
..
i
I
/
at:i
3.0
~
~
o
v~ = 3.~V
V
2-0
'00
~~ V
-
VCE=3.0V hie = 110
..,.
0:
W
w
i
0.1
o
./
0.05
~
!
-
0.05 0.1 0.2
0.5 1.0 2.0
COllECTOR CURRENT - InA
5.0 10
-
~ f.-
0.50
f"'"'j
0.'5
o
-75
IE
-50
-25
25
800
i
400
I
v..: = 3.~V
0
:l
Q
0
800
II:
./
l:
:;
..
Q
Z
C
~
"
V
f
200
o
o
9
COLLECTOR CURRENT -
50
75
AMBIENT TEMPERATURE _ °C
TAo = 250C
..
.
~::.
I/t.~
.......
"w
Q
N
iI,.
'.0
./~
0:
0
Z
i'..V
V
""\:;~
10
rnA
11-18
100
125
h"
h ..
h ••
v;...
Gain Bandwidth Product vs
Collector Current
i
I III.
if
PCOS300F
1000
10
l.!
0.02
0.01
0.01 0.02
}
~A ~~~~:: ~:a~'0-4 AT1m~=
h
hoe = 15.6 ~mho
II!
In
> 0.75
0.2
Normalized h Parameters vs
Collector Current
0.1
0.01 0.02
hi'
0.05 0.1 0.2
0.5 1.0 2.0
COLLECTOR CURRENT -
mA
5.0 10
J1A3680
Quad Telephone
Relay Driver
FAIRCHILD
A Schlumberger Company
Linear Division Special Functions
Description
The MA3680 Relay Driver is a monolithic integrated circuit
designed to interface -48 V relays to TTL or other logic
systems in telephony applications. The device has a
50 mA source capability and operates from -48 V battery
power. The quad configuration increases board density in
typical line card applications. Since there can be considerable noise and IR drop between logic ground and battery
ground, these drivers are designed to operate with a high
common mode range (± 20 V referenced to battery
ground). Also, each driver has common mode range separate from the other drivers in the package. Low differential
input current (typically 100 MA) draws low power from the
driving circuit. Differential inputs permit either inverting or
non-inverting operation. A clamp network is incorporated in
the driver outputs, eliminating the need for an external
network to quench the high voltage inductive backswing
caused when the relay is turned off. A fail-safe feature is
incorporated to insure that the driver will be off in the
VI + input or both inputs are open. Standby power (driver
off) is very low, typically 50 MW per driver.
•
•
•
•
•
•
•
-48 V Battery Operation
50 rnA Output Capability
TTl/CMOS Compatible Comparator Input
High Common Mode Input Voltage Range
Very Low Input Current
Fail-Safe Disconnect Feature
Built-In Output Clamp Diode
Connection Diagram
14-Lead DIP and SO-14 Package
(Top View)
+IN A
BATGND
-IN A
our A
-IN B
our B
+IN B
our C
+IN C
our D
-IN C
BAT NEG
-IN D
+IN 0
Order Information
Device Code
J.LA3680DV
J.LA3680PV
J.LA3680SV
Package Code
6A
9A
KD
Package Description
Ceramic DIP
Molded DIP
Molded Surface Mount
Absolute Maximum Ratings 1
Storage Temperature Range
Ceramic DIP
Molded DIP and SO-14
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 5)
Molded DIP and SO-Package
(soldering, 10 s)
Internal Power Dissipation 2, 3
14L-Ceramic DIP
14L-Molded DIP
SO-14
Differential Input Voltage
Output Current (LL';;; 5.0 H)
Output Current (RLl
BAT NEG
Input Voltage
(BAT NEG ;;;'-50 V)
-65°C to + 175°C
-65°C to + 150°C
-25°C to +85°C
300°C
265°C
1.36 W
1.04 W
0.93 W
±20 V
50 rnA
100 rnA
Max
+0.5 V
+20 V
Min
-70 V
BAT NEG
-0.5 V
Notes
1. All voltages are with respect to BAT GND.
2. TJ Max = IS0·C for the Molded DIP and SO-14, and 17S·C for the
Ceramic DIP.
3. Ratings apply to ambient temperature at 2S·C. Above this temperature,
derate the 14L-Ceramic DIP at 9.1 mWrC, the 14L-Molded DIP at
8.3 mW'·C, and the 50-14 at 7.5 mWrC.
11-19
MA3680
Recommended Operating Conditions
Max
Unit
-60
-10
V
-10
+10
V
+2
+10
V
Logic Off Voltage (VI+-VI-)
-10
+0.8
V
Temperature Range
-25
+85
°C
Characteristic
Min
Battery Voltage (BAT NEG)
Input Voltage
Logic On Voltage (VI+-VI-)
Electrical Characteristics Over Recommended Operating Conditions unless otherwise specified. TA = 25°C,
BAT NEG = -52 V.
Symbol
Characteristic
VIH
Logic "1" Differential Input Voltage
VIL
Logic "0" Differential Input Voltage
IINH
Logic "1" Input Current
IINL
Logic "0" Input Current
Conditions
Min
Typ
1.3
0.8
Max
2.0
40
100
VI+ = 7.0 V, VI- = 0 V
375
1000
+0.01
+5.0
VI+ =-7.0 V, VI- =0 V
-100
-1.0
V
V
1.3
VI+ = 2.0 V, VI- = 0 V
VI+ = 0.4 V, VI- = 0 V
Unit
JJA
JJA
VOL
Output ON Voltage
IOL =-50 rnA
-2.1
-1.6
V
IOFF
Output Leakage
Vo = BAT NEG
-100
-2.0
IFS
Fail-Safe Output Leakage
Vo = BAT NEG (Inputs open)
-100
-2.0
-100
-2.0
JJA
JJA
JJA
-1.2
-0.9
ILC
Output Clamp Leakage Current
Vo=BAT GND
Vc
Output Clamp Voltage
ICLAMP = -50 rnA, Referenced to BAT NEG
Vp
Positive Output Clamp Voltage
ICLAMP = +50 rnA, Referenced to BAT GND
IB(ON)
Supply Current
All Drivers On
-4.4
-2.0
IB(OFF)
Supply Current
All Drivers Off
-100
-1.0
tpLH
Propagation Delay, Output
Low-to-High
L = 1.0 H, RL = 1.0 kn
1.0
10
J.LS
tpHL
Propagation Delay, Output
High-to-Low
L = 1.0 H, RL = 1.0 kn
1.0
10
J.LS
11-20
0.9
V
1.2
V
rnA
JJA
MA3680
Equivalent Circuit (1/4 of circuit)
DC Test Circuit
At
_IN --"t-~W\r----,
A4
Dt
D4
-IN--t-----,~r
>-~-------
- - - - - .,
r ~~-,
1tva L_:_-.J
D5
'::'
I
-52 V
BAT NEG
OUT
D3
L-__~~~~______~__________________~___
::~
I
I
L ____ .J
•
9 BAT NEG
AC Test Circuit and Waveforms
-52 V
Typical Applications
+5.0 V
r --l-~
74XXI
I
L=tH
I __ I~_--,
I
I
I
I
)0--------'-1
-52 V
-48 V
CRO"""
CR03040F
11-21
J.LA555
Single Timing Circuit
FAIRCHILD
A Schlumberger Company
Linear Division Special Functions
Description
The J.lA555 Timing Circuit is a very stable controller for
producing accurate time delays or oscillations. In the time
delay mode, the delay time is precisely controlled by one
external resistor and one capacitor; in the oscillator mode,
the frequency and duty cycle are both accurately controlled with two external resistors and one capacitor. By
applying a trigger signal, the timing cycle is started and an
internal flip-flop is set, immunizing the circuit from any further trigger signals. To interrupt the timing cycle a reset
signal is applied ending the time-out.
Connection Diagram
8-Lead DIP and 50-8 Package
(Top View)
TRIGGER
DISCHARGE
OUT
THRESHOLD
The output, which is capable of sinking or sourcing
200 mA, is compatible with TTL circuits and can drive relays or indicator lamps.
•
•
•
•
•
•
•
•
Timing Control, J.lS To Hours
Astable Or Monostable Operating Modes
Adjustable Duty Cycle
200 rnA Sink or Source Output Current
TTL Output Drive Capability
Temperature Stability Of 0.005% Per °C Typ
Normally On Or Normally Off Output
Direct Replacement For SE555INE555
CONTROL
VOLTAGE
RESET
Order Information
Device Code
J.LA555TC
J.lA555SC
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 10 s)
Internal Power Dissipation 1, 2
8L-Molded DIP
SO-8
Supply Voltage
vee
GND
-65°C to + 150°C
O°C to +70°C
265°C
0.93 W
0.81 W
+18 V
Notes
1. TJ Max -150°C.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 8L-Molded DIP at 7.5 mWrC, and SO-8 at 6.5 mWrC.
11-22
Package Code
Package Description
9T
KC
Molded DIP
Molded Surface Mount
J,LA555
Block Diagram
Vcc--+....5.0kO
THRESHOLD
CONTROL
VOLTAGE
DISCHARGE
--++-1
R
FLIP-FLOP
5.0 kO
TRIGGER
-++-1
Q
S INHIBITI
RESET
-~I""-T"- OUT
5.0 kO
RESET
_+_________..J
GND
Equivalent Circuit (Note 1)
CONTROL
VOLTAGE
VCC-~~---~~-----'-~~-----~-----~---1~-----1---~----+-----~
THRESHOLD
OUT
TRIGGER-------+----iJ
RESET
---------i:-'
DISCHARGE-----,
GND' _ _ _-4_~~~-------4---4--~~------4--------4---4-------J
Note
1. All resistor values in ohms.
11-23
JlA555
/JA555
Electrical Characteristics TA = 25°C, V+ = +5.0 V to +15 V, unless otherwise specified.
Symbol
Characteristic
Vee
Supply Voltage
Icc
Supply Current 1
tD
Timing
Error
Initial Acc\.lracy
Drift with Temperature
Condition
Min
VTR
Threshold Voltage
Trigger Voltage
Max
Unit
16
V
3.0
6.0
mA
Vee = 15 V, RL=oo
LOW State
10
15
RI = 2.0 kS1 to 100 kS1
C = 0.1 IlF
1.0
%
50
ppm/DC
0.1
%V
Vee = 5.0 V, RL =
00
Drift with Supply Voltage
VTH
Typ
4.5
Vee = 5.0 V
2.6
3.33
4.0
Vee=15 V
9.0
10
11
Vee = 15 V
4.0
5.0
6.0
Vee = 5.0 V
1.1
1.67
2.2
0.5
5.0
V
V
ITR
Trigger Current
VR
Reset Voltage
0.7
1.0
V
IR
Reset Current
0.1
1.5
mA
ITH
Threshold Current2
0.1
0.25
!lA
Vev
Control Voltage Level
VOL
VOH
Output Voltage LOW
Output Voltage HIGH
0.4
Vee=15 V
9.0
10
11
Vee = 5.0 V
2.6
3.33
4.0
Vee=15 V, 10-=10 mA
0.1
0.25
10- = 50 mA, Vee = 15 V
0.4
0.75
10- = 100 mA, Vee = 15 V
2.0
2.5
10- = 200 mA, Vee = 15 V
2.5
3.5
Vee = 5.0 V, 10- = 8.0 mA
0.3
10- = 5.0 mA, Vee = 5.0 V
0.25
10+ = 200 mA, Vee = 15 V
11.0
12.5
10+ = 100 mA, Vee = 15 V
12.75
13.3
Vee = 5.0 V, 10+ = 100 mA
2.75
Rise Time of Output
100
tf
Fall Time of Output
100
IDIS
Discharge Leakage Current
20
11-24
V
V
0.35
V
3.3
tr
Notes
1. Supply Current is typically 1.0 mA less when output is HIGH.
2. This will determine the maximum value of R1 + R2. For 15 V operation,
the maximum total R = 10 Mil.
IlA
ns
ns
100
nA
MA555
Typical Performance Curves
Minimum Pulse Width Required
for Triggering
150
2.0
10
125
~
4: 8.0
I
l:
....
e
i
...
w
oJ
E
100
~
15
'"
50
Z
li
T;
I
...-...- ~
:>
:IE
:>
25
"u 4.0
f..-
~
~
.....
~
~
~....1•• ,O·j
~
V
./
!:;
§l1.0
..50.6
50.8
....
0.4
o
5.0
0.4
10
TA
>
=250C
1.0
I
"~
'"'
>
SUPPLY VOLTAGE -
-
=S.OV
V
~
~ 0.1
0.01
1.0
5.0
50
10
TA = 25°C /
~
S 1.000
e
1.0
•
./
V
i
5.0
10
SINK CURRENT -
50
100
rnA
Propagation Delay vs
Voltage Level of Trigger Pulse
1.015
~ol--r--+--+--+--+--jL-I--~
1.010
\
--
\
N
::;
---I
- 1.005
o. 1
~
5
SINK CURRENT -
1.015
"'i='"
:>
t--t-+-t-t/-=-...-!::......-t-H+--l
SINK CURRENT-mA
Delay Time vs
Supply Voltage
J
~
o
>
....
O.O~'::.0---L.-l.....L5:'.0:--:",0:--'-LJ...,5':0-~,00
100
100
(
1,. 0
w
o
./
50
>
1.01--II-H+-+-+-++I1--I
>
e
10
Vee = 15, V
~"
k..-'
0.1
1'5 v
5.0
0
o
t:;
s
Output Voltage LOW vs
Output Sink Current
>
0
I ,cct
SOURCE CURRENT - mA
Vee::: 10 V
~
r-5.0
o1.0
15
Output Voltage LOW vs
Output Sink Current
Vee
a:
~ 1.2
./
2.0
0.3
....-
TA = 25°C
>
11.4
w
0.2
0.2
10
:e
1.8
1.6
ijl
Output Voltage LOW vs
Output Sink Current
:>
V
V
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE - x Vee
......
=2~'C V V
./
./
/
6.0
a:
a:
'/!f>'C ....-
0.1
~
Output Voltage HIGH vs
Output Source Current
Total Supply Current vs
Supply Voltage
~
i=
>- 1.005
~
--
o
-- r-
S 200 1 - - + - + - 1 - - + - - ) 9 ; 4 - + - - 1
-
~
oz
150
a:
"~
100
z
if
~ 1.000
::;
~ 0.995
o
!
I
l - i"- t--
o
Z
0.990
0.990
0.985
0.985
10
SUPPLY VOLTAGE -
15
V
20
fi
I--t~;.j-"""'+--f--+-+-+---j
50
-50
-25
25
50
75
AMBIENT TEMPERATURE -
11-25
100
~C
i 25
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE- x Vee
J..LA555
Typical Applications
Figure 1 Monostable Mode
~C=~OVT015V----------------~---------,
Monostable Operation
In the monostable mode, the timer functions as a one
shot. Referring to Figure 1 the external capacitor is initially
held discharged by a transistor inside the timer.
Rl
RESET---
When a negative trigger pulse is applied to lead 2, the
flip-flop is set, releasing the short circuit across the external capacitor and driving the output HIGH. The voltage
across the capacitor increases exponentially with the time
constant T = R1 C1. When the voltage across the capacitor
equals
Vee, the comparator resets the flip-flop which
then discharges the capacitor rapidly and drives the output
to its LOW state. Figure 2 shows the actual waveforms
generated in this mode of operation.
TRIGGER
;,tA555
:r3
The circuit triggers on a negative going input signal when
the level reaches h Vee. Once triggered, the circuit remains in this state until the set time elapsed, even if it is
triggered again during this interval. The duration of the
output HIGH state is given by t = 1.1 R1C1 and is easily
determined by Figure 3. Notice that since the charge rate
and the threshold level of the comparator are both directly
proportional to supply voltage, the timing interval is independent of supply. Applying a negative pulse simultaneously to the Reset terminal (lead 4) and the trigger terminal
(lead 2) during the timing cycle discharges the external
capacitor and causes the cycle to start over. The timing
cycle now starts on the positive edge of the reset pulse.
During the time the reset pulse is applied, the output is
driven to its LOW state.
r
Figure 2 Monostable Waveform
t = 01 ms/DIV
INPUT"" 2.0 V/DIV
I-
OUTPUT VOLTAGE
=::
l J
~
II
'/
- ir-f
5.0 V/OIV
I--
/
ir-f LI-- J
CAPACITOR VOLTAGE - 2.0 VIOl V
When Reset is not used, it should be tied HIGH to avoid
any possibility of false triggering.
R1 = 9.1 kil, C1
=:
0.01 i'F. RL '" 1.0 kJl
Figure 3 Time Delay vs R1 and C1
100 r---,---.,.----.--..,.,..-..-r--,
10r---+---+---~~~~-+~~
0.01
I+--W---h''---H<---I7<--+--~
1.0
TIME DELAY
11-26
10
CONTROL
YOLTAGE
0.01 "F
JlA555
Astable Operation
When the circuit is connected as shown in Figure 4 (leads
2 and 6 connected) it triggers itself and free runs as a
multivibrator. The external capacitor charges through R1
and R2 and discharges through R2 only. Thus the duty
cycle may be precisely set by the ratio of these two resistors.
Figure 4
Astable Mode
~c=~OVT015V------------------~~---------,
Rl
OUT------i
In the astable mode of operation, C1 charges and discharges between h Vee and 5'3 Vee. As in the triggered
mode, the charge and discharge times and therefore frequency are independent of the supply voltage.
R2
CONTROL
VOLTAGE
Figure 5 shows actual waveforms generated in this mode
of operation.
0.01
~F
I
The charge time (output HIGH) is given by:
Figure 5 Astable Waveform
tl = 0.693 (R1 + R2) C1
-
t - 0.5 milDlY
and the discharge time (output LOW) by:
t2
= 0.693 (R2) C1
OUTPUT VOLTAGE
5.0 VIDIV
I I I I
Thus the total period T is given by:
T = tl + t2 = 0.693 (R1 + 2R2) C1
/ V ~ ~ / \Y~
The frequency of OSCillation IS then;
'"
1.44
f=-=----T (R1 + 2R2) C1
CAPACITOR VOLTAGE = 1.0 VIOIV
Rl = R2 = 4.8 ko, Cl = 0.1 "F, RL = 1 kO
and may be easily found by Figure 6.
The duty cycle is given by:
Figure 6
R2
DC=---
Free Running Frequency vs
R1, R2, and C1
R1 + 2R2
"fw
1.0
(J
Z
;!
~
0.1
"
(J
0.01
FREE RUNNING FREQUENCY -Hz
11-27
•
JlA556
Dual Timing Circuits
FAIRCHILD
A Schlumberger Company
Linear Division Special Functions
Description
The J.LA556 Timing Circuits are very stable controllers for
producing accurate time delays or oscillations. In the time
delay mode, the delay time is precisely controlled by one
external resistor and one capacitor; in the oscillator mode,
the frequency and duty cycle are both accurately controlled with two external resistors and one capacitor. By
applying a trigger signal, the timing cycle is started and an
internal flip-flop is set, immunizing the circuit from any further trigger Signals. To interrupt the timing cycle a reset
signal is applied, ending the time-out.
Connection Diagram
14-Lead DIP
(Top View)
DISCHARGE
THRESHOLD
DISCHARGE
CONTROL
VOLTAGE
THRESHOLD
The output, which is capable of sinking or sourcing
200 mA, is compatible with TTL circuits and can drive relays or indicator lamps.
RESET
OUT
The J.LA556 Dual Timing Circuit is a pair of J.LA555s for
use in sequential timing or applications requiring multiple
timers.
•
•
•
•
•
•
•
Timing Control, JIS To Hours
Astable Or Monostable Operating Modes
Adjustable Duty Cycle
200 mA Sink Or Source Output Current
TTL Output Drive Capability
Temperature Stability Of 0.005% Per °c Typ
Normally On Or Normally Off Output
TRIGGER
GND
RESET
OUT
TRIGGER
Order Information
Device Code
J.LA556PC
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 10 s)
Internal Power Dissipation 1, 2
Supply Voltage
CONTROL
VOLTAGE
-65°C to + 150°C
O·C to +70°C
265°C
1.04 W
+18 V
Notes
1. TJ Max = 150·C.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate at 8.3 mwrc.
11-28
Package Code
9A
Package Description
Molded DIP
MA556
(112
Block Diagram
of circuit)
Vcc--+....S.OkO
THRESHOLD
CONTROL
VOLTAGE
DISCHARGE
-++-1
R
FUP-FLOP
S.OkO
TRIGGER
-++--f
Q
S INHIBITI
RESET
-"""1, ....-,..-- OUT
5.0 kO
RESET
_+_________....1
GND
Equivalent Circuit (';2 of circuit) (Note 1)
CONTROL
VOLTAGE
VCC-~~_---~-----~~~-----~_---~-~----p--~--~---,
THRESHOLD
OUT
TRIGGER--------Ir---~
RESET - - - - - i : '
DISCHARGE----,
Note
1. All resistor values in ohms.
11-29
tlA556
pA556
Electrical Characteristics TA = 25°C, V+ = + 5.0 V to + 15 V, unless otherwise specified.
Symbol
Condition
Characteristic
Supply Voltage
lee
Supply Current (Total) 1
Vee = 5.0 V, RL =
Vee = 15 V, RL =
LOW State
to
Timing Error
(Monostable)
Min
Initial Accuracy
Drift with Temperature
00
00
teH, DIS
Initial Accuracy
Drift with Temperature
ITH
Threshold Current2
VTR
Trigger Voltage
ITR
Trigger Current
VR
Reset Voltage
IR
Reset Current
Vev
Control Voltage Level
VOL
VOH
V
6.0
12
mA
20
28
%
R 1 , R2 = 2.0 kn to 100 kn
C = 0.1 J..IF
2.25
%
150
ppmfOC
50
ppm/oC
0.1
%V
%V
0.3
Threshold Voltage
Vee = 5.0 V
2.6
3.33
4.0
Vee=15 V
9.0
10
11
30
250
nA
Vee = 15 V
4.0
5.0
6.0
V
Vee = 5.0 V
1.3
1.67
2.0
0.5
5.0
0.4
0.1
Output Voltage LOW
Output Voltage HIGH
V
10
11
2.6
3.33
4.0
10- = 10 mA, Vee = 15 V
0.1
0.25
10- = 50 mA, Vee = 15 V
0.4
0.75
2.75
10- = 100 mA, Vee = 15 V
2.0
10- = 200 mA, Vee = 15 V
2.5
3.5
10- = 5.0 mA, Vee = 5.0 V
0.25
0.35
Vee = 5.0 V, 10+ = 100 mA
12.5
2.75
V
3.3
Rise Time of Output
100
tf
Fall Time of Output
100
lOIS
Discharge Leakage Current
Ato
Matching
Characteristics
ns
ns
20
100
0.1
2.0
±10
Drift with Supply Voltage
0.2
Notes
1. Supply current when output is HIGH is typically 1.0 mA less.
2. This will determine the maximum value of R1 + R2 for 15 V operation.
The maximum total R = 10 Mil.
3. Matching characteristics refer to the difference between performance
characteristics of each timer section.
11-30
V
12.75 13.3
t,
Initial Timing Accuracy
V
mA
9.0
11
J..IA
1.5
Vee = 5.0 V
Vee = 15 V, 10+ = 100 mA
V
1.0
Vee=15 V
Vee = 15 V, 10+ = 200 mA
Timing Drift with Temperature
Unit
16
0.75
Drift with Supply Voltage
VTH
Max
Rl = 2.0 kn to 100 kn
C = 0.1 J..IF
Drift with Supply Voltage
Timing Error
(Astable)
Typ
4.5
Vcc
nA
%
ppmfOC
0.5
%V
J-tA556
Typical Performance Curves
Minimum Pulse Width
Required for Triggering
Total Supply Current vs
Supply Voltage
150
20
125
~
16
I
...c
:t 100
ffi
i
w
~ 75
:>
:>
:IE
50
Z
i
25
f.-
00
a
.iil
~ 8.0
~
~ P""
12
a:
a:
?!>'C l.-V ..-- ~
~
"{,. ;:. 10°,....
k;:::
..
:IE
/'
TA = 25'C/'
/'
V
Output Voltage HIGH vs
Output Source Current
2.0
vV
1/
1.8
1.6
CI 1.2
V
V
g~ 1.0
...
~ 0.8
5 0. 6
/'
4.0
0.4
0.2 ;-5.0
o
0.4
0.3
0.2
0.1
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE -
10
SUPPLY VOLTAGE - V
5.0
II Vee
Output Voltage LOW vs
Output Sink Current
o
15
TA = 250C
,.-
~
~
.....
0.01
1.0
~
50
0.1
"
0.01
1.0
mA
•
..........
TA = 25°C
.,/'
5.0
10
SINK CURRENT -
50
100
mA
Propagation Delay vs
Voltage Level of Trigger Pulse
Delay Time vs
Ambient Temperature
1.015
1.010
1.01 0
C 1,000
~
o
SINK CURRENT -
w
:!l
...
:>
O.O~'::.0---'--l.....J.5:'-.0:--:"0:--'_L-L5::0,--7.'00
100
1.01 5
c
>
.....-
o
5.0
10
SINK CURRENT-mA
j
o
:>
Delay Time vs
Supply Voltage
>- 1,005
100
{
I 1.0
w
~ 0.1 f-_f-+T_At-~+-25.'...C""V"'---f_H+_--l
~
:>
w
50
>
1.0f--+-+-H--\--\-+-ffl---\
~
o
>
":l
10
Vee == 15 V
>
g
,.
5.0
Output Voltage LOW vs
Output Sink Current
Vee"" 10 V
I
"~
0.1
YC1~ ,15 V
10
>
I 1.0
w
.
~
SOURCE CURRENT - mA
Output Voltage LOW vs
Output Sink Current
Vee = S.OV
...
...
I
1.0
10
:>
0
TA = 25°C
>
I 1.4
w
\
-
\
~
1'---
:l:Ii 0.99 5
250~-r--+--+--+--+--~-4--~
~
2
"~
>- 1.005
--
C
~ 1.000
--r-- r--
- -r-
::;
~ 0.995
a:
a:
o
z
o
z
0.990
0.990
0.98 5
0.985
10
SUPPLY VOLTAGE -
15
V
20
I
~
w
200 t---+-+-f--+-~4-+--l
~
150
c
ii
"If: 100 I--f:::;;:;..j-""'+--+--+-+-+---I
~
50
-50
-25
25
50
75
AMBIENT TEMPERATURE _
_ _ _ _ _ _ _ _ _ _ _ _.c,·
11-31
100
ec
125
0.4
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE-. Vee
MA556
Typical Applications
Figure 1 Monostable Mode
~C=~OVT015V----------------~---------,
Monostable Operation
In the monostable mode, the timer functions as a one
shot. Referring to Figure 1 the external capacitor is initially
held discharged by a transistor inside the timer.
14
When a negative trigger pulse is applied to lead 6, the
flip-flop is set, releasing the short circuit across the external capacitor and drives the output HIGH. The voltage
across the capacitor, increases exponentially with the time
constant T = R1C1. When the voltage across the capacitor
equals :r3 Vee, the comparator resets the flip-flop which
then discharges the capacitor rapidly and drives the output
to its LOW state. Figure 2 shows the actual waveforms
generated in this mode of operation.
The circuit triggers on a negative going input Signal when
the level reaches h Vee. Once triggered, the circuit remains in this state until the set time has elapsed, even if
it is triggered again during this interval. The duration of
the output HIGH state is given by t = 1.1 R1C1 and is
easily determined by Figure 3. Notice that since the
charge rate and the threshold level of the comparator are
both directly proportional to supply voltage, the timing interval is independent of supply. Applying a negative pulse
simultaneously to the Reset terminal (lead 4) and the trigger terminal (lead 6) during the timing cycle discharges
the external capacitor and causes the cycle to start over.
The timing cycle now starts on the positive edge of the
reset pulse. During the time the reset pulse is applied, the
output is driven to its LOW state.
R.
RESET---
TRIGGER
1/2/JA5S6
OUT
r
CONTROL
YOLTAGE
0.01 p.f
CAOQ521F
Figure 2
Monostable Waveform
t
= 0.1
mS/DIV
INPUT = 2.0 VlDIV
I-
OUTPUT VOLTAGE = 5.0 V/DIV
J
V
'11
I--
W
/
f-- ..J
CAPACITOR VOLTAGE
When Reset is not used, it should be tied HIGH to avoid
any possibility of false triggering.
/
-li
2.0 V/DIV
Rl = 9.1 k!l. C1 = 0.01 J.lF, Rl = 1.0 kll
Figure 3 Time Delay vs R1 and C1
l00r---~--,---~---r,r-~~~
.
~
~ 1.0
<.>
z
~
..1l
~ 0.1
0.0'
f+--+,.<---J7
\
0.2
100K
01
100M
10M
FREQUENCY - Hz
10K
1M
J
I
-0.2
10
o
II ~ GAIN 1
'/
0
D 1.0
~I /
GAIN 2--'"
0.8
:.J
\
S
~ 20
8:E
1.2
>
..~
..... r-..,
=
Vee t6 V
TA = 25°C
RL= 1 kO
1.4
"z 5.0
so
o
1.8
~~v
veU
TA = :WC
RL=1kfl
,:. &.0
r-..,
70
Pulse Response
7.0
5
10
50 100
-0.,
-15 -10 -5
500 1000
0
5 10 15
TIME-ns
FREQUENCY - MHz
20 25
30 35
PC07730F
Differential Overdrive
Recovery Time
70
.~V
veA=
TA =:WC
I GAN2
..
.ffi40
260
1
/
:Eso
;:
V
8:l3O
~
!!i2O
ffi
is 10
1.6
00
20 40
GAIN 2
TA = 250C
RL=1kO
Vee = taV
1.4
7
1.2
>
..
l/
/"
- I -. /
I
1.0
"~
0.8
~
Q.6
5
0.4
S
II
0.2
1
Z 1.05
~
1&1
~
= £ev
'\ ........ ~+ r-- l ~
\
t-......
0
5
10 15
0.'
60
100
TEMPERATURE - ·c
!~
-0.4_15 -10 -5
0
5
10 15
TIME-
20
25 30 35
na
Voltage Gain vs
Supply Voltage
III
40
TAI.U~c
~~ III
~ ~irc
~
~30
~
..fi
020
10
-10
=25°C
1.4
T~YriC
~ ~loc
IT~I= 12~
Ii
140
TA= 125D C
TA
;.-. TA= 7O"C
j
D.2
20 25 30 35
Vcc=tBV
RL-1 leO
~ 0
\
20
:-&l
rj
0
'II
;
\
-20
-- ,
-0.2
-0.4
-15 -10 -5
z
~
2\
0.65
0.80
-80
0.6
TlME-n.
\.\;
w
"
TA = -55"C
..5
ISO
> 0.90
TA = 00
0.8
...:::>
60
Ve
gUS
5..
..
~
Gain vs Frequency
vs Temperature
\
1.00
RL=1kCl
1.2
>
1 1.0
:.J
.J
GAIN 2
Vee = ±6V
1.4
-0.2
80 100 120 140 160 180 200
60
Voltage Gain vs
Temperature
~ 1.10
1.8
~
'/
0
/
Vee = ±6V
Vee = ±3V
DIFFERENTIAL INPUT VOLTAGE - mV
1.15
Pulse Response vs
Temperature
Pulse Response vs
Supply Voltage
1
5
10
so 100
FREQUENCY - MHz
11-37
I
jJ
5001000
TA·25·C
~I
1.3
12
.
:
1.0
~
0.9
..g
~
Ii
0.8
0.7
~ 0.6
0.5
f"'"
~ 1.1
I-
GJ.,....
'll-" I-" p-
~ ~ ~~"/
/
~
...... .-
V
,/
V
0. 4 3
SUPPLY VOLTAGE - tV
MA592
Typical Performance Curves (Cont.)
Output Voltage and Current Swing
vs Supply Voltage
Voltage Gain Adjust Circuit
Voltage Gain vs RADJ
lOGO
7.0
TAI=
J.c
D.2,.F
T
T
~
i..;'
~
#:¥
~
V
.
~ ~ '"
P"
I
·z
':'
Rod,
...
~
10
~
"
:..I
§!
...
~Z
...a:
1.0
"
0.1
I
"
.ot
8.0
5.0
6.0
7.0
SUPPLY VOLTAGE - +Y
4.0
...........
100
~
D.2 .F
~v."
Vee = tlV
1= 100 11Hz
TA = 25'C
>
1
10
lK
100
10K
100K
1M
RodI- n
PC07671F
PC07810F
Output Voltage Swing vs
Load Resistance
7.0
we
J8.0
I
~ 5.0
V-
~a.o
{
80
...I
70
~
80
§!
50
:..I
6z
!i2.0
...
I!
L.o
ii!
;!;
.....
500 1 K
LOAD RESISTANCE -
TAD
B
5K 10K
n
~24
30
20
12
01 2 1 0
100
lK
BOURCE RESISTANCE -
'/
,/
I'
./
8
~
18
5
18
a::!
17
i
18
~
,.
...... .......
.......
...... ~
15
!/
20
i
MHz
I'
./
I
18
=1
40
TA= 25"C
E
we
I
28
!
20
I
Supply Current vs
Supply Voltage
!i
Vee. t8V
VCC'- t8V
10
50 100 200
10
21
G~IN~III
90
...
g
0
100
Vee = t6V
TAo-
!... 4.0
Supply Current vs
Temperature
Input Noise Voltage vs
Source Resistance
/
3
SUPPLY VOLTAGE - tY
11-38
n
10K
14
-80
-20
20
80
TEMPERATURE - 'C
100
140
p.A733
Differential Video
Amplifier
FAIRCHILD
A Schlumberger Company
Linear Division Special Functions
Description
The IlA733 is a monolithic two-stage differential input, differential output video amplifier constructed using the
Fairchild Planar Epitaxial process. Internal series shunt
feedback is used to obtain wide bandwidth, low phase distortion, and excellent gain stability. Emitter follower outputs
enable the device to drive capacitive loads and all stages
are current source biased to obtain high power supply and
common mode rejection ratios. It offers fixed gains of 10,
100 or 400 without external components, and adjustable
gains from 10 to 400 by the use of a single external resistor. No external frequency compensation components
are required for any gain option. The device is particularly
useful in magnetic tape or disc file systems using phase
or NRZ encoding and in high speed thin film or plated
wire memories. Other applications include general purpose
video and pulse amplifiers where wide bandwidth, low
phase shift, and excellent gain stability are required.
Connection Diagram
10-Lead Metal Package
(Top View)
vNote
Pin 5 connected to case.
Order Information
Device Code
•
•
•
•
120 MHz Bandwidth Typ
250 kf2 Input Resistance Typ
Selectable Gains Of 10, 100, And 400
No Frequency Compensation Required
Absolute Maximum Ratings
Storage Temperature Range
Metal Can and Ceramic DIP
Molded DIP and SO-14
Operating Temperature Range
Extended (1lA733M)
Commercial (1lA733C)
Lead Temperature
Metal Can and Ceramic DIP
(soldering, 60 s)
Molded DIP and SO-14
(soldering, 10 s)
Internal Power Dissipation " 2
10L-Metal Can
14L-Ceramic DIP
14L-Molded DIP
SO-14
Supply Voltage
Differential Input Voltage
Common Mode Input Voltage
Output Current
Package Code
1lA733HM
1lA733HC
5X
5X
Package Description
Metal
Metal
Connection Diagram
14-Lead DIP and 50-14 Package
(Top View)
-65°C to +175°C
-65°C to + 150°C
14
-55°C to + 125°C
O°C to +70°C
1.07 W
1.36 W
1.04 W
0.93 W
±S.O V
±5.0 V
±6.0 V
10 mA
IN2
INt
NC
Ne
G..
G...
G.
a".
v-
v+
Ne
Ne
OUTt
OUT 2
COO124OF
Order Information
Device Code
Notes
1. TJ Max -150°C for the Molded DIP, and 175°C for the Metal can and
Ceramic DIP.
2. Ratings apply to ambient temperature at 25°C. Above this temperature,
derate the 10l-Metal Can at 7.1 mWrC, the 14l-Ceramic DIP at
9.1 mWrC, the 14l-Molded DIP at 8.3 mWrC, and the 50-14 at
7.5 mWrC.
1lA733DM
1lA733DC
1lA733PC
1lA733SC
11-39
Package Code
Package Description
6A
6A
9A
KD
Ceramic DIP
Ceramic DIP
Molded DIP
Molded Surface Mount
•
pA.733
Equivalent Circuit
V+
IN1
+--+-O'UT1
UT2
R14
400Cl
V-
~733 and ~733C
Electrical Characteristics TA = 25°C, Vee = ± 6.0 V unless otherwise specified.
p.A733
Symbol
Avo
BW
Condltlon 1
Characteristic
Differential Voltage Gain
Bandwidth
Rs=50
n
,-
t,
tpo
ZI
Risetime
Propagation Delay
Input Impedance
Input Capacitance
Input Offset Current
Max
Min
Typ
Max
Unit
V/V
Gain 1
300
400
500
250
400
600
90
100
110
80
100
120
Gain 3
9.0
10
11
8.0
10
12
Gain 1
40
40
Gain 2
90
90
Gain 3
120
120
Rs=50 n,
Vo = 1.0 Vp_p
Gain 1
10.5
10.5
Gain 2
4.5
Gain 3
2.5
2.5
Rs=50 n,
Vo = 1.0 Vp_p
Gain 1
7.5
7.5
Gain 2
6.0
Gain 3
3.6
Gain 1
Gain 3
110
Typ
Gain 2
Gain 2
CI
p.A733C
Min
Gain 2
4.5
10
6.0
ns
12
ns
10
3.6
4.0
20
kn
4.0
10
30
250
30
250
2.0
0.4
11-40
10
MHz
2.0
3.0
0.4
pF
5.0
pA
#J,A733
/.IA733 and 1.IA733C (Cant.)
Electrical Characteristics T A = 25°C, Vee =
± 6.0
V unless otherwise specified.
p.A733
Symbol
Condition!
Characteristic
liB
Input Bias Current
en
Input Noise Voltage
Min
Input Voltage Range
CMR
Common Mode Rejection
VCM
PSRR
Supply Voltage Rejection
Ratio
tJ.Vcc = ± 0.5 V, Gain 2
Vos
Output Offset Voltage
= ± 1.0
V, Gain 2
Typ
Max
9.0
20
Min
12
Rs=50 n,
BW = 1.0 kHz to 10 MHz
VIR
p.A733C
Typ
Max
9.0
30
Unit
IJA.
12
IlVrms
± 1.0
± 1.0
60
86
60
86
dB
50
70
50
70
dB
V
Gain 1
0.6
1.5
0.6
1.5
Gain 2 and Gain 3
0.35
1.0
0.35
1.5
2.9
3.4
2.9
3.4
VOCM
Output Common Mode
Voltage
2.4
2.4
V
V
VOP
Output Voltage Swing
3.0
4.0
3.0
4.0
Vp-p
10-
Output Sink Current
2.5
3.6
2.5
3.6
rnA
Ro
Output Resistance
20
Icc
Supply Current
18
20
24
18
n
24
rnA
The following specifications apply over the range of -55·C";;TA";;125·C for 1JA.733 and 0·C";;TA";;70·C for 1JA.733C.
Avo
Differential Voltage Gain
Gain 1
200
600
250
600
Gain 2
80
120
80
120
Gain 3
8.0
12
8.0
12
Gain 2
8.0
ZI
Input Impedance
8.0
110
Input Offset Current
5.0
6.0
liB
Input Bias Current
40
40
VIV
kn
IJA.
IJA.
VIR
Input Voltage Range
±1.0
±1.0
V
CMR
Common Mode Rejection
50
50
dB
PSRR
Power Supply
Rejection Ratio
50
50
dB
Vos
Output Offset Voltage
Gain 1
1.5
1.5
Gain 2 and Gain 3
1.2
1.5
VOP
Output Swing
2.5
2.8
10-
Output Sink Current
2.2
2.5
Icc
Supply Current
27
Note.
1. Gain Select leads G'A and G'8 connected together for Gain 1.
2. Gain Select leads G2A and G28 connected together for Gain 2.
3. All Gain Select leads open for Gain 3.
11-41
V
Vp.p
27
rnA
rnA
JlA733
Typical Performance Curves
Phase Shift vs
Frequency
Phase Shift vs
Frequency
I'-
.."'II!
"'
-5
S
"-
I
..5
-15
I..
-20
-25
N
""
.....
-3SO
10
Vee.
I
1
5
.0
30
~
I
8
1.4
II!. " 1 00
1.2
I 5.0
i:
:!I
vc~1J~v
TAo ="J5OC
~
r-...
!;
.....
500 1000
RL = 1 kQ
1.0
"'
0.8
Gl'N
~
0..
:>
0..
:>
0.2
Q
\
Vcc=tBY
Gl'N
....
~
2.0
~
20
50 100
TA = 25°C
>
I
"~
..0
gt.o
'"
10
FREQUENCY - MHz
1.6
,:.
~
5
500 1000
Pulse Response
.. 8.0
70
~
l~
'\
f-
10
50 100
FREQUENCY - MHz
t6V
TA. 25°C
i
f-
.r
7.0
80
i
.......
GAIN 3
Output Voltage Swing vs
Frequency
GAIN ~I_
90
\
~~
~i
-300
•
100
GAIN 2
G>
Common Mode Rejection Ratio vs
Frequency
2
1\
~
FREQUENCY - MHz.
III
TA= 25"C
GAIN 1
1\
• •
o
Vee ~_~_I V
=
~\
r--..
-10
Q
-so
&0
Vee = t6V
TAo soc
f::: ~t--
GAIN 2
YCC' t6_ IITAO:; 2SOC
Voltage Gain vs
Frequency
r
.......
I
...<:
I
'GAIN
/
J
01.0
-0.2
10
o
10K
100K
0,
1M
10M
FAEQUENCY - Hz
100M
5
so
10
FREQUENCY -
100
-0.4
-15 -10 -5
500 1000
5101520253035
TIMe-ne
MHz
PC07900F
PC07880F
PC07910F
I
Differential Overdrive
Recovery Time
Pulse Response vs
Supply Voltage
1.8
70
7'
/'
I
., ,so
..
1540
;:
8II!
V
30
~
/
/,V
1
20
010
r-r- V
00
20
V
40 10 80 100 120 140 160 180 200
DIFFERENnAL INPUT VOLTAGE - mY
TA- 25'C-
1.4
Vcc=tlY
TA - 2SOC
80
GAIN 2
GAIN.
oJN21.
2
Pulse Response vs
Temperature
R
1.2
>
I
1.0
""'~
0.8
...
S
~
0.1
:>
0.'
0
0..
Vcc=tBV
II
I
VCf" fllV
j
vcc ..
§
0.8
!j
~
0.6
t3V
'/
S
I!:
il
1
Vee" t8_ VAL= 1 kO
I
1.0
TA= 0
TA= -55°C
C
rm~.
r ~\
-I
v..
Q.4
j
•
0.
TA = 1250C
TAo = 25°C
TA'" 7()I'C
I
0
-0.2
-0.,
-15 -10 -5
1.'
1.'
= 1 k!l
-0.2
0
5 10 15
TIME-ni
11-42
20
2S
30 35
-0.
•
-15 -10
-5
0
5
10
15
TIME-ns
20
25
30
35
1lA733
Typical Performance Curves (Cont.)
Voltage Gain vs
Temperature
1.15
~
,
\
1.1 0
1&1
!
~
Vee = tay
1-
1.0
-I-
~
1-
_\
'\ ....... ~'I'..
\
~
\
0.85
0.90
-60
I- 0"111 3
~
~ -~
0.8
'"2:
0.7
II!
0.8
\
-
20
20
TEMPERATURE - OC
L...- ~
au
~
0.5
100
25~C
V
'" ~ ""'J,,'J...!o.o
~ ~~
I-
....... j--..
~ 0.90
II!
1.2
1
z1.1
~Na-
0.05
T••
l.a
.-
1 , .05
3
Voltage Gain vs
Supply Voltage
Gain vs Frequency vs
Temperature
7
1/
/
'/
140
FREQUENCY -
SUPPLY VOLTAGE - tY
MHz
"."'OF
7.0
Gain vs Frequency vs
Supply Voltage
Output Voltage Swing vs
Load Resistance
Output Voltage and Current
Swing vs Supply Voltage
7.0
T.I.Jc
GAINZ
TAo = ZS-C
~~:~
::;..-
~
TAo
'II
z
./
./
a
40
~
30
'"
V
~
20
'\
~
10
~
i
~4~~
Z
If
Vee-tlV
ii
.......
7.0
5.0
8.0
SUPPLY VOLTAGE - tV
8.0
ZSOC
Ycc=:!:8Y
Z
4.0
II:
50
1
./
1/ ~ . /
•
80
Vcc=t8V
50 100 aGO
500 1 K
V,Cj{3V
-10
5K 10K
1
LOAD RESISTANCE - 0
5
10
80 100
FREQUENCY - MHz
500 1000
""'' oaF
Input Noise Voltage vs
Source Resistance
Voltage Gain Adjust Circuit
Voltage Gain vs Rad)
100
1000
Vcc= tlV
oAINJ 111_
vcc·tev
~~==~~C"Hz-
u~
0
I
0
V
0,2,.,.F
-
~
10
o
1
TA = HOC
~
1
z
iii
"'"
~
i
100
\,
~
~
II:
I
i'...
10
5 10
50100
5001K
10 K
"""""
SOURCE RESISTANCE - (}
11-43
r""
10
100
1K
Rul-Q
10K
#J,A733
Typical Performance Curves (Cont.)
Input Impedance vs'
Temperature
Supply Current vs
Supply Voltage
Supply Current vs
Temperature
.
..
70
GAIN 2
Vee = t6V
28
v~=t~V
TA-
20
24
'/
./
/'
/'
/
./
1/
/'
V
o
-60
r--..
V
V
i'
V
V
... V
10
............
1/
12
-20
.
15
20
100
TEMPERATURE _ °C
,.-eo
140
-20
./
.
20
100
TEMPERATURE _ °C
140
Oscillator Frequency for Various Capacitor Values
107
r--.... ..........
~
1 leO
r--'
6200
c
pA733>
Lf/"
1
~
___ MEASURED
"""
CALCULATED/
I--T-I
~
ru
~
...
..........
1=1IT
I =
I I
.......
~
1
2(R1 • R2)CLn
[AIr --'!!.L -1]
A1 +R2
''''3.4 x 103c
'0;00
1K
10K
100K
1M
FREQUENCY - Hz
11-44
3
SUPPLY VOLTAGE - tV
Typical Applications
10S
/
8
"
10M
25~
JJ,A7392
DC Motor Speed
Control Circuit
I=AIRCHILD
A Schlumberger Company
Linear Division Special Functions
Description
The p.A7392 is designed for precision, closed loop, motor
speed control systems. It regulates the speed of capstan
drive motors in automotive and portable tape players and
is useful in a variety of industrial and military control applications, e.g., floppy disc drive systems and data cartridge
drive systems. The device is constructed using the
Fairchild Planar Epitaxial process.
Connection Diagram
14-Lead DIP
(Top View)
+MOTOR
STALL TIMER
DRIVE IN
-MOTOR
HlC
DRIVE IN
The p.A7392 compares actual motor speed to an externally
presettable reference voltage. The motor speed is determined by frequency to voltage conversion of the input signal provided by the tachometer generator. The result of
the comparison controls the duty cycle of the pulse width
modulated switching motor drive output stage to close the
system's negative feedback loop.
-TACH IN
OUT EMITTeR
GND
MOTOR DRIVE
OUT
CLAMPING DIDOE
+TACH IN
V+
PULSEnMING
Thermal and over voltage shutdown are included for selfprotection, and a stall-timer feature allows the motor to be
protected from burn out during extended mechanical jams.
•
•
•
•
Precision Performance
High Current Performance
Wide Range Tachometer Input
Thermal Shutdown, Over Voltage And Stall
Protection
• Internal Regulator
• Wide Supply Voltage Range 6.3 V To 16 V
REGULATOR
OUT
PULSE OUT
"",....
Order Information
Device Code
p.A7392DV
p.A7392PV
Package Code
6A
9A
Package Description
Ceramic DIP
Molded DIP
Absolute Maximum Ratings
Storage Temperature Range
Ceramic DIP
Molded DIP
Operating Temperature Range
Lead Temperature
Ceramic DIP (soldering, 60 s)
Molded DIP (soldering, 10 s)
Internal Power Dissipation 1 - 3
14L-Ceramic DIP
14L-Molded DIP
Supply Voltage (V+), V9,
Vl0, Vll
Regulator Output Current, 18
Voltage Applied to Lead 6
(Tachometer Pulse Timing)
-65·C to + 175·C
-65·C to + 150·C
-40·C to + 85·C
300·C
265·C
1.36 W
1.04 W
24 V
15 rnA
7.0 V
Voltage Applied Between Leads 3
and 5 (Tachometer Inputs)
Continuous Current through
Leads 11 and 12 Motor Drive
Output ON
Repetitive Surge Current through
Leads 11 and 12 (Motor Drive ON)
Repetitive Surge Current through
Leads 10 and 11 (Motor Drive OFF)
± 6.0 V
0.3 A
1.0 A
0.3 A
Notes
1. TJ Max = 150'C for the Molded DIP, and 17S'C for the Ceramic DIP.
2. Ratings apply to ambient temperature at 25'C. Above this temperature,
derate the 14L·Ceramic DiP at 9.1 mW/'C, the 14L·Molded DIP at
B.3 mWI"C.
3. Internally UmHed.
11-45
pA7392
Block Diagram
SUPPLY
r - - 1 r -....- -....- VOLTAGE
V+
1
SPEED
ADJUST
PULSE TIMING
TACHOMETER
INPUTS
~
PULSE
MOTOR
DRIVER
INPUTS
V+
OUTPUT
CLAMPING
DIODE
./LJLf
I
I
REGULATOR
OUTPUT
PROTECTIVE
CIRCUITS
VOLTAGE REGULATOR
SECTION
L---T--------------------------+
IL_______________ I
STALL TIMER
~
~
_________
~
EQ(J0540F
11-46
MA7392
IlA7392
Electrical Characteristics TA = 25·C, V+
Symbol
= 14.5
V, unless otherwise specified.
Characteristic
Unit
Condition
Voltage Regulator Section (Test Circuit 1)
Icc
Supply Current
VReg
Regulator Output Voltage
LlNEReg
Regulator Output Line
Regulation (~Va)
V+ = 10 V to 16 V
V+ = 6.3 V to 16 V
Regulator Output Load
Regulation (~Va)
la from 10 rnA to 0
40
mV
2.4
V
LOADReg
Excluding Current into Lead 11
4.5
7.5
10
rnA
5.0
5.5
V
6.0
20
mV
12
50
Frequency to Voltage Converter Section (Test Circuit 2)
VIN
Tachometer (-) Input Bias
Voltage
liN
Tachometer (+) Input Bias
Current
Vs=Va
VOIFF
Tachometer Input Positive
Threshold
(Vs-Va)
VHY
Tachometer Input Hysteresis
1.0
10
!1A
10
25
50
mVp. p
20
50
100
mVp•p
300
500
n
50
55
%Va
R
Pulse Timing ON Resistance
VTH
Pulse Timing Switch Threshold
tr
Output Pulse Rise Time
It
Output Pulse Fall Time
VSat.LOW
Pulse Output LOW Saturation
(V7)
0.13
0.25
V
VSat.HI
Pulse Output HIGH Saturation
(Va- V7)
0.12
0.2
V
ISource
Pulse Output HIGH Source
Current
V7 = 1.0 V
-260
-180
SVS
Frequency-to-Voltage Conversion
Supply Voltage Stabilityl
VFV = 0.25 Va2
V + = 10 V to 16 V
0.1
%
TS
Frequency-to-Voltage Conversion
Temperature Stabilitya
VFV = 0.25 Va2
TA = -40·C to + 85°C
0.3
%
V6 = 1.0 V
45
0.3
jl.S
0.1
-340
jI.S
!1A
Motor Drive Section
VIO
Input Offset Voltage
liS
Input Bias Current
CMR
Common Mode Range
0.1
VSAT
Motor Drive Output Saturation
111
ILEAK
Motor Drive Output Leakage
10
Flyback Diode Leakage
20
mV
10
!1A
2.5
V
2.0
V
V 11 = V1 0 = 16 V
5.0
V10 = 16 V, Vll = 0 V
30
!1A
!1A
0.8
= 300 rnA
11-47
1.3
J.LA7392
~7392 (Cont.)
Electrical Characteristics TA = 25°C, V+
Symbol
= 14.5
V, unless otherwise specified.
Characteristic
Condition
Flyback Diode Clamp Voltage
VD
Min
111 = 300 mA
Motor Drive Output OFF
Typ
Max
Unit
1.1
1.3
V
Protective Circuits
J-TOC
Thermal Shutdown
Junction Temperature4
Over Voltage
Overvoltage Shutdown4
18
VTH
Stall Timer Threshold Voltage 5
2.5
ITH
Stall Timer Threshold Current5
°C
160
V
24
21
2.9
3.5
V
0.3
3.0
JJ.A
Notes
1. Frequency·to·voltage conversion, supply voltage stabilny is defined as:
VFV(16 V) _ VFV(10 V)
V.(16 V)
+ VFV(14.5
V.(10 V)
V) x 100%
V.(14.5 V)
2. VFV is the integrated DC output voltage from the pulse generator
(Lelld 7)
3. Frequency-Io-voltage conversion temperature stability is defined as:
VFV(8S0C) _ VFv(-40·C)
V8(8S°C)
V8(-40°C)
+ VFv(2S·C) x 100%
V8(2S°C)
4. Motor Drive circuitry is disabled when these limits are exceeded. If the
condition continues for the duration set by the external stall timer
components, the circuit is latched off until reset by temporarily opening
the power suppty input tine.
S. If stall timer protection is not required, tead 14 should be grounded.
Typical Performance Curves
Overvoltage Shutdown Voltage vs
Junction Temperature
Stall Timer Threshold Voltage vs
Junction Temperature
Stall Timer Threshold Current vs
Junction Temperature
0.8
25
v. " 14.Jv
"---- r--
"" "'-
~
u
i
125
·c
150
-50
-25
25
50
j!:
i'-..
75
ffi
"
100
JUNCTION TEMPERATURE -
11-48
0.8
1\
0.5
0..
\
\.
r"....
a:
2.0
25
50
75 100
JUNCTION TEMPERATURE _
t 0.7
!Z...
"
V+I: 14. V
1.
125
+c
!!
0.2
.
0.1
......
~
150
0.3
0
-so
-25
""
25
"-
50
r- I-7S
100
JUNCTION TEMPERATURE _ °C
125
150
IlA7392
Typical Performance Curves (Cont.)
2
T,I= .Joe
SA
T.'= 2~oe
>
'0
"'"~
§!
....
I
I
I
I
I
11
/
o
12
16
SUPPLY VOLTAGE -
3
l'i
2
~
II
o
V
i
I
I
I
I
1
J
I
i
1
!
12
16
SUPPLY VOLTAGE -
V
1./
'"
V
V
V
u
"'4.7
I
!
.......
5.'
5
I!: 5.0
ila:: ••9
g
I
I
o
24
~
I
,
~
20
'"5.2
,
II
:l
I
,
I
4
it
5
!(
!
,
I
I
o
!
!
v+'= ".Iv
>5.3
15
i....-' I-""
o
Regulator Output Voltage vs
Junction Temperature
Regulator Output Voltage vs
Supply Voltage
Supply Current vs
Supply Voltage
20
24
U
-60
-25
V
25
50
75 100 125
JUNcnON TEMPERATURE - DC
150
PCD11370F
Flyback Diode Current (D3) vs
Flyback Diode Voltage
Tachometer Input Hysteresis vs
Junction Temperature
58
800
v;=,Jv
v+
1
--
....... ..,.
!ii
1
500
u 400
~
g300
I
~200
~
""'00
o
42
-60
-25
25
50
75 100
JUNCTION TEMPERATURE -
oe
125
150
o
/
FLYBACK DIODE VOLTAGE - V
>
"M
!i!j
1.42
§!
/
!:! '.36
ii:
Q
1.34
I!i
1.32
./
V
V
.,- V
V
1.30
-50
-25
25
50
75
100
/
/
125
/
/
/
/
Motor Drive Output ON Voltage vs
Ambient Temperature
'M
! 1. •
~ 1.3.
il
V+
TJ = TA = .DC
1 600
V
"...,...
/
=114.S J
J
=1 14•5
TJ = TA = 2SOC
700
./
Motor Drive Output ON Current vs
Motor Drive Output ON Voltage
150
11-49
/
/
MOTOR DRIVE OUTPUT ON VOLTAGE - V
tJA7392
Test Circuits
Test Circuit
Test Circuit 2
20 kO
TACH INPUT
VOLTAGES
14
13
100 0
14
12
10 kO
13
11
0.1 pE
12
100 0
10
TACH
INPUT
VOLTAGE
ADJUST
11
V=G.3V...
'NOM = 1000 Hz
L-____________DC
10
~~~
100 kO
REGULATOR VOLTAGE
+
-=-14.5 V
(INTEGRATED
FREQ-TO-VOLTAGE
CONVERTER
OUTPUT VOLTAGE)
PULSE
PULSE
x
t--------------<~-TIMING
OUTPUT--------~
VOLTAGE
00025 p,F
Typical Application Using MagnetiC Tachometer
33OkO
ch
RS
9.1 kO
SPEED
ADJUST
100 kCl
10kO
O.Ol"F
A-
I
2kO
1
141-
2
13
"hfll
*
1
3
4
"::"
r--- 5
RF
l00kO
,6
7
:r
F
Cp
H~
"::"
Rp
100 kCl
11
"::"
l°h
9
sf-
I
I
I
I
I
I
(:>
Typical comp onent values:
•
CP=4~PF
Cp'DCpto 1000 C de endin
system requirements
on
Cs:: 2 X stal~~me-out
AMotor 2:: 5
n
11-50
1
100 kO
10VT016V
5 "F
TACHOME TER
(I = NOMI NAL
TACHOME TER
FREQUEN CY)
VOLTAGE
FSP100
Programmable Digital Filter
FAIRCHILD
A Schlumberger Company
Preliminary
Advanced Signal Processing Division
Description
Connection Diagram
(Top View)
The Fairchild FSP100 is a device optimized for use in one
dimensional data stream processing. It efficiently implements both recursive and non-recursive filter structures. It
has, on-chip, all the functions necessary to perform most
common filter primitives in a Single instruction. The advanced architecture has separate data and instruction
paths to avoid input-output bottlenecks, and utilizes a high
performance crosspoint switch to efficiently route data between the processing elements. A transparent pipeline allows simultaneous instruction fetch, execution and data
input/output. The serial data path permits variable data
word lengths between 20 and 32-bits, which allows efficient single-chip implementations that have not been possible with previous single chip digital signal processors.
REsET
IDLE
The FSP100 uses an external byte-wide program memory
for maximum design flexibility without compromising performance. Multiprocessing is straightforward because the
FSP100 is directly cascadeable.
RESERVED
OPSO
FLAG
OPRQ
PA7
INRQ
PA6
INCK
PA5
INSD
PA'
INOR
PA3
HOLD
PA2
OPCK
Voo
GNO
PAl
ClK
PAO
OPOR
PB2
NOT USED
PBl
NOT USED
The FSP100 instruction set implements familiar digital signal processing primitives such as Pole-pairs, Zeros, Peak
Detectors and Oscillators.
The FSP100 comes with a comprehensive software support system, including an assembler and a simulator, which
runs under the UNIX', VMS" and MS-DOS operating systems. A hardware development system which allows real
time verification of applications software completes the
support package.
NXT
PBO
OVER
07
SIGN
06
DO
05
01
D.
02
03
Order Information
Device Code
Package Code
Package Description
FSP100DC
FSP100LC
Consult Factory
Consult Factory
40-Lead Ceramic DIP
44-Lead LCC
• Requires No External Synchronization Between
Input/Output Clocks and Processor Clocks
• Optional Data Input and Output Formats and Word
Lengths
• External Program Memory for Maximum Design
Flexibility
• On-Chip Data Memory for Storing State Variables
• Complete Software and Hardware Support Package
for Design Development
• Single-Phase 16 MHz Processor Clock Frequency
• Single-Phase 10 MHz Data Input and Output Clock
Frequency
• 40-Lead Ceramic DIP and 44-Lead LCC Packages
• TTL- and CMOS-Compatible Input/Outputs
• Fu" Performance Over -55°C to + 125°C Operating
Temperature Range
• 2-Micron CMOS Process
• Single-Chip Programmable Digital Filter
• Programmed in the Language of Filter Designers (in
Terms of Poles and Zeros)
• Programmable Internal Data Word Lengths Between
20 and 32-Bits
• Executes Complete Filter Functions in a Single
Instruction Cycle
• Triple Multiplier-Accumulator Provides 3 Million
Multiplies Per Second
• Sample Rates up to 200 KHz for Single-Chip
Applications
• Simply Cascade Processors with no Intermediate
Logic for Higher Sample Rates
• Separate Data and Instruction Paths On- and OffChip
• Separate Processor and Data Input/Output Clocks
for Ease of System Design
#< A trademark of AT&T
**A trademark of Digital Equipment Corporation
11-51
FSP100
Logic Symbol
PROGRAM
AODRESS
PROGRAM
DATA BUS
00·07
OATA
INPUT
PORT
INDR
OPDR
INRQ
OPRQ
FSP100
INCK
OPCK
OPSD
PROGRAM
CONTROL
IDLE
CONTROL
I
DATA
OUTPUT
PORT
PROCESSOR
CONTROL
+POWER/CLOCK
Architecture
General Description
The data path contains all of the components necessary
to execute a two·pole filter section with a single instruc·
tion:
• A triple multiplier·adder.
• An editing unit which modifies the result from the triple
multiplier to obtain saturation and other non·linear
effects.
• Scratch pad registers.
• An accumulator with extension bits and scaler.
• A sequential access memory with two data channels for
state variable storage.
• A crosspoint switch for passing data between the
blocks.
• An input and an output interface, which can synchronize
the chip with the input and/or output data rate.
The control path is
thus eliminating the
program sequencer
is also provided for
quencer, if desired.
path are:
totally independent of the data path,
need for pipeline flushing. A simple
is provided on·chip, but a clock output
use with an external program se·
The major elements of the control
• A program sequencer, providing branching and looping.
• An instruction decoder for configuring the crosspoint
switch.
Triple Multiplier-Adder
Most of the arithmetic unit consists of a triple multiplieradder. During each instruction cycle, it forms the sum of
products:
R = Xg • Gamma + Xa • Alpha + Xb • Beta
The X's are Signal data streams emerging from the crosspoint switch. Alpha, Beta and Gamma are coefficients. Alpha is in the range -2 to +2. Beta is in the range -1 to
+ 1. Gamma is normally a power of two scaling factor in
the range of -2 to +2, but it is possible to feed Signal
data to the Gamma coefficient input to effect the signalby-signal multiplications required for modulation, veo's and
time-varying filters.
Normally the multiplier rounds the final sum·of·products.
However, recursive filtering instructions may invoke random
switching between rounding and truncation in order to de·
feat limit cycles.
The triple multiplier includes a fast carry chain. This fast
carry chain provides an overflow and sign output in ad·
vance of the serial data output, in order to control the
saturation and non·linear function logic in the editing unit.
The triple multiplier uses Booth encoders operating directly
on the incoming data bit-pairs. These Booth encoders can
also perform non-linear functions. Signals from the control
section can cause the input data streams to be masked
to zero or inverted as they enter the arithmetic unit, to
provide half or full wave rectification or a sign·dependent
gain.
• A bus for distributing the instruction bytes for local
decoding.
11·52
FSP100
Figure 1 Block Diagram
INSTRUCTION BUS
-...
z ...
-
f~
:Zz
00
a:U
U
ADDRESS COUNTERS
DATA MEMORY
~
I-~
I--
-
H
~
0VA.N
SCRATCH REGISTERS
REGISTER FILE
r-IPSO
OPSD
---
ACCUMULATOR SCALER
RI
FAST CARRY CHAIN
r--
~ ::cU
,.--
~
EOITING UNIT
1
r--!!-
~
INSTRUCTION DECODER
i
-- ..
--
~ ...a:w
>
~ !
..
Q
'"z ~ z
~ ...
5
,.!!- '":I'"
..L '"'"
a:
..
TRIPLE MULTIPLIER
WITH ADDER
I-- 00-07
Q
U
t
INPUT INTERFACE
2.
OUTPUT INTERFACE
-!-
t
t
t
INSTRUCTION SEQUENCER
BYTE COUNTER
____ PO-P7
~FO-F2
"---
unit: one for the filter output, and the other for the new
state variable value_
Editing Unit
The primary function of the editing unit is to saturate the
result from the multiplier to prevent overflow osciiiations in
recursive filters_
Scratch Pad Registers
The scratch pad registers are a group of six variablelength registers_ Two registers serve as working stores;
each one is connected between a crosspoint switch output
and input The use of these registers is determined by the
FUNCTION code_
The saturation logic consists of a multiplexer which can
select between the multiplier output, + 1, -1 or 0_ A control PLA sets the switches according to the FUNCTION
code and the sign/overflow flags, to achieve either saturation or the more complex behavior required for the other
non-linear operators_
A dual-port connects another crosspoint switch output and
input four-word register file_ This register file is directly addressable by an instruction field_ It can be used to store
intermediate results for more complex filter topologies.
Another function of the editing unit is to provide some
commonly used, computationally simple filter zeros_ This
function allows execution of some biquadratic sections in a
single instruction cycle_ When this function is used, the
output of the filter is different than the new value of the
state variable (which needs to be stored in the data memory)_ There are, therefore, two outputs from the editing
Accumulator
An accumulator is also connected to an output from the
crosspoint switch. It is used primarily for implementing FIR
and parallel IIR summing nodes. It has six extension bits
11-53
FSP100
which permit accumulation of up to 64 values without the
risk of overflow. The accumulator output is connected to a
crosspoint switch input via a power-of-four scaling circuit,
the scaling factor being determined by the SETUP instruction.
Data Memory
The data memory is organized as a 64-column, 32-row array of 2-port, 3-transistor RAM cells. It functions logically
as an adjustable length shift register, with two data channels each two bits wide. The length of the "shift register"
is set up during initialization.
The rows are written sequentially. Each row receives 16
bits from each of four input bit streams (two data channels) for an effective register length of a multiple of 32
bits per channel. Adjustable length shift registers on the
input increase the length resolution to four bits per channel.
The serial access memory restricts operation to algorithms
in which the data flows in an ordered stream, such as
filters and correlators. However, this memory organization
can efficiently store data of arbitrary word length. Also, the
instruction word does not require a memory address field.
Input and Output
The input! output data is single bit wide serial with four
possible arithmetic formats. It may be either most- or
least-significant bit first. The input and output word lengths
are independent both of each other and of the internal
word length.
Associated with both the input and output port are two
handshake lines; one indicates that the external device is
ready, the other that the FSP100 is ready. The FSP100
can suppress its ready signal until the external device is
ready, thus enabling the processor to directly control the
transfer.
The input and output ports each have their own clock.
These clocks may be asynchronous with respect to each
other and with respect to the processor clock. The interface logic is deSigned to have an arbitrarily low error rate
without reducing the interface throughput.
While the processor is waiting for an external device to
become ready, the I/O interface stops the execution of
the program. Execution resumes upon completion of the
I/O transfer. The processor thus synchronizes itself to the
sample rate of the rest of the system.
data transfers for one instruction cycle to take place simultaneously, with no contention, at effective data rates up
to 240M bits per second.
The crosspoint switch is double-buffered, so that it may be
set up for the next instruction during the execution of the
current instruction. The connection pattern determines the
signal processing algorithm.
Program Sequencer
The program sequencer is built around an eight bit instruction counter and a three-bit byte counter. The byte counter
addresses the eight bytes of one instruction. To avoid the
need for a branch address field in the program counter,
the branch address is loaded with the SETUP instruction
into the label register. The program sequencer also contains a loop counter and loop control logic. The branch
logic can perform unconditional branches and conditional
branches depending on the state of the "Flag" pin.
Instruction Decoder
Instruction decoding is performed by two PLA's operating
on the function code. One PLA generates the crosspoint
switch configuration; the other controls the non-linear functions in the editing unit. The remainder of the instruction
word is decoded locally by the small control sections associated with each data path component.
Pipelining
The FSP100 incorporates instruction-level pipelining to
eliminate time lost in many processors fetching the next
instruction from memory and storing the results of the previous instruction back into memory.
The following Table 1 depicts this action. Time slot T3 is
typical. The result of instruction N is stored in memory.
Instruction N + 1 is executed within the FSP100 and the
64 bits of the instruction N + 2 are fetched from the external memory. During the time slot T4 the progress of each
instruction advances. Instruction N + 1's results are stored
back in memory. Instruction N + 2 is executed within the
FSP100 and instruction N + 3 is fetched from external
memory.
Pipelining continues in this fashion without conflict since
the time to either fetch an instruction or store a result is
always less than or equal to the time required by the
FSP100 to execute an instruction.
Crosspoint Switch
The crosspoint switch replaces the data busses of more
conventional architectures. It enables all the necessary
11-54
FSP100
Signal Processing Functions
Table 1 Pipelining
The following list presents the functions selectable by the
FUNCTION code. Those functions that require more than
one instruction cycle are implemented as two separate instructions. The software support package allows these
multiple instruction sequences to be coded as a single instruction. The list does not include functions for testing,
initialization and control, because the user does not usually
code these functions directly.
TIME PERIODS
INST. N
T1
T2
T3
FETCH
EXECUTE
STORE
FETCH
EXECUTE
STORE
FETCH
EXECUTE
STORE
FETCH
EXECUTE
INST. N+1
INST. N+2
T4
INST. N+3
Name
T5
T6
STORE
Number of Instructions
Function
Filter Poles:
POLES
CPOLES
APOLES
RPOLE
RPOLES
1
2
2
1
2
Direct form pole-pair
State-space pole-pair
Adaptive pole-pair
Real pole with well-defined gain
Two independent real poles with well-defined gain
Filter Zeros:
ZERO
ZEROS
NOTCH
FIR
Real zero with well-defined gain
Direct form zero pair
Adaptive notch
Two taps of an FIR
Combined Poles and Zeros:
POLEP
POLEN
POLEZERO
BIO
BIOR
BIOU
BlOT
BIOPP
BIOPN
BIONN
LAD DR
1
1
1
2
2
2
3
1
1
2
Real pole with well-defined gain; zero at Z = + 1
Real pole with well-defined gain; zero at Z = -1
Real pole and zero
Direct form second order section
Second order section for parallel forms
Second order section with zeros in unit circle
Transposed form second order section
Direct form second order section, zeros at Z = + 1
Direct form second order section, zeros at Z = ± 1
Direct form second order section, zeros at Z = -1
Ladder form filter section
Miscellaneous Linear Functions:
GAIN
SUM
INTEGS
Gain and offset
Weighted sum of two signals
Resettable integrator
Signal Generators:
RAMP
EXPVCO
SINEGEN
RANDY
PULSE
PULSERT
Ramp/sawtooth generator
Exponential ramplVCO
Sinewave oscillator
Pseudo random noise
Pulse generator
Retriggerable pulse generator
11-55
•
FSP100
Name
Number of Instructions
Function
Point Non-Linearities:
BREAKPT
SDGAIN
SDOFF
SDLEVEL
SDSRC
CCLIP
SUBIZ
SUBIT
LIMIT
MAXVAL
MINVAL
RESTORE
Breakpoint (for piecewise linear functions)
Sign dependent gain
Sign dependent offset
Sign dependent level
Sign dependent source
Center clipping
Substitute zero inside window
Substitute data inside window
Limiting function (like saturation)
Maximum of two signals
Minimum of two signals
Restore sign removed by absolute value
Non-Linearities with State:
SAMPLE
PEAKHOLD
LEVELDET
ZCROSS
Sample and hold
Tracks and holds peaks
Comparator with hysteresis
Zero crossing detector
Housekeeping:
GETMEM
PUTMEM
LOADB
LOADC
LOADBC
Recover state variables
Save value to memory
Load B register
Load C register
Load Band C register
Notes
Instruction names are preliminary.
"Well-defined" means that the gain coefficient is not restricted to a power of 2.
Table 2 Instruction Format
Table 2.1
......-- bytes 0 .• 3 - . . . . . - - . bytes 4 .. 7 - - .
FUNC + microcode fields
II
Multiplier coeftts
SETUP + microcode fields
II
Setup parameters
INIT
~
Default Microcode Format - All Function Codes Except INIT
- - - - - - - - - - - - - bytes 0 ...3 - - - - - - - - - - - - -..
2+2
I
defines fixed operating MODE parameters
""co"'"
4+1 -
Y-output/Pi-load
Temp file r/w addresses
Temp register source select
Accumulator control
Source nonlinearity
Source data for FUNC to operate on
Sequence control - Next, Jump, Loop, Flag
Instruction function code - e9 POLES or PEAK DETECT
11-56
It of bits used
I
Gamma coelnt
FSP100
Table 2.2 Coefficient Format (all Function
Codes Except INIT And SETUP)
Table 2.3 SETUP Parameter Format (only Applies For
SETUP Function Code)
_ - - - - - - - b y t•• 4 ...7 - - - - - - -_
_ - - -_ _ byt•• 4 ...7 _ _ _ _ _•
~
...
I,L_A_B_E_L.....I....,N,-L_O_O_p-.JI.,.R_E_S--.JII....rA_S_C_A_L...t..,P_R_U_P_D_A_T_E...JI
I
I
8+4
16
16 -
I
Range -1 .•. <+1
I
I
Range -2 ...<+2
I
I
1
3
8 -
I
I
l,ogram update addr••• byte
# of bits used
# of bits used
Accumulator output scaling
Reserved for future use
'nltlal value for loop counter
Jump address for branch instructions
Table 2.4
Special INIT Instruction Format
- - - - - - - - - - - - - - - - b y t•• O...3 - - - - - - - - - - - - - - _ . -
~
6
2
j
1
4 -
#ofbUsused
I
!nput upsampling
Passive (active) mode
Data direction
Dither duty cycle
1
Operating wordlenglh
Memory cycle force
Immediate/delayed mode
Reserved for future use
Memory length parameter
NEXT sequence code
INIT function code
- - - - - - - - - - - - - - - - - - - - - b y t e s 4 ... 7 - - - - - - - - - - - - - - - - - - - -__
4
I
4
8
4
1
I
I
1 -
• of bits used
IInvert Magnitude Bits
Invert Sign Bit
Invert Magnitude Bits
I
Invert Sign Bit
Reserved for future use
Output subsampling factor
Reserved for future use
Passive (active) mode
Data direction
Input injection position
Y output wordlength
X input wordlength
Noles
The XFORMAT field operates on the incoming data stream AFTER it has
entered the PDF and it has been subject to the XMODE data direction
field. Thus, it regards the Most Significant bit of incoming data as the sign
bit and the remaining bits as the magnitude bits.
The YFORMAT field operates on the outgoing data stream while it is still
in the internal two's complement format. Thus, it regards the Most
Significant bit of internal data as the sign bit and the remaining bits as the
magnitude bits. The data is still subject to bit reversing as specified in the
YMODE data direction field.
11-57
FSP100
Signal Descriptions
Name
110
VCC
GND
INCK
INDR
INRQ
INSD
OPCK
OPDR
OPRQ
OPSD
RESET
HOLD
IDLE
ClK
OVER
SIGN
NXT
FLAG
PAO-?
PBO-2
DO-?
I
I
I
I
0
I
I
I
0
0
I
I
0
H/L
H
H
H
H
H
H
H
H
l
H
H
I
0
0
0
I
0
0
I
H
H
H
H
H
H
H
Description
Power
Power
Input clock
Input device ready
Input request
Input serial data
Output clock
Output device ready
Output request
Output serial data
Reset
Force processor wait
Indicates forced processor wait
Processor clock
Overflow
Sign
External sequencer clock
Flag (branch control)
Program word address (tri-state)
Program byte address (tri-state)
Program byte input
Program Memory Operation
The FSPi00 is designed to operate with an external program memory with no impact on the data throughput. To
achieve this, a separate instruction bus is utilized with
dedicated address and data lines. Internally, a 64-bit instruction word is used, but it is time-multiplexed into eight
bytes.
The ii-bit program address bus can address a total of
256 instructions with the least significant three bits addressing both the eight bytes of the current instruction and
the eight most significant bits of the program counter. This
configuration means that, when using a byte-wide memory,
no additional external interface logic is required.
Figure 2 illustrates the typical configuration of an FSPi00
and its program memory, in this case a 1 K x 8-bit PROM.
A timing diagram follOWS.
Data Input/Output Operation
The FSPi00 has a dedicated data input-output port that
allows maximum utilization of the processor while requiring
a minimum of external logic. To achieve this, dedicated
input and output channels are available that can be asynchronous from the CPU and each other in a variety of
configurations, according to external requirements. Further,
to simplify multiprocessor systems, the ports are configured
such that processors can be directly tied output to input
with no additional logic.
The operation of the two ports is largely
the exception of the data pin itself. Both
one bit wide, and come with a variety of
pendently configure each channel. These
follows:
the same with
ports are serial,
options to indeoptions are as
Clock Frequency: This determines the rate at which the
bits are serially clocked into and out of the data pins. It is
individually selectable for each channel and need not be
synchronous with the CPU clock.
Data Word Length: The input-output ports can operate
with any data word length from 8 up to 32 bits in increments of 2 bits. Further, this word length does not have
to be the same as that used internally; the FSPi00 automatically adjusts for the value selected.
Data Format: This indicates the arithmetic format of the
external serial data stream. The options for the incoming
arithmetic format are two's complement, inverted two's
complement, offset binary and inverted offset binary. The
FSP100 will automatically convert between the format
specified and its' own internal two's complement format.
Data Direction: This determines the direction in which the
bits are passed into and out of the data pins. The data
can be either least- or most- significant-bit first. The
FSP100 automatically adjusts for this choice internally.
11-58
FSP100
Figure 2
FSP100 With External Program Memory
Yoo
F93451
A3-As
PAOPA6
Ao-A2 01-08
PA7
PBOPB2
POOP07
FSP-100
Program Memory Timing Diagram (20-Bit Operation)
I,
10
CPU CLOCK
I
PROGRAM BYTE
fpc:.~~;:~ LINES
_ _P_R_O_G_RA_M_BYT_E_7-+1_.II"_ _ _ _B_YT_E_0_-+_JX,-_ _B_Y_TE_l_ __
---l
PROGRAM
fp,!~~;;:' LINES
PROGRAM MEMORY
g~i:~~NES
PC n
.JX
I
--I
Ipc -
PC (n+l)
I'A -
____
(00-07)
:::j
ISETUP
I--
~,.---:"---:R~O"'D-O---C
l---- 'MA =:::.j
I R007
NOTE: tMA =65 ns @ 16 MHz (Typical)
t PC = 25 ns Typical @ 30pF Loading
Handshake Mode: This determines whether the FSP100
behaves as a master or slave during the input and output
handshake operation. The two modes are called "ACTIVE" and "PASSIVE" mode. In active mode, the FSP100
determines when the transfer begins. In passive mode, the
FSP100 waits until the device ready line goes high before
beginning a transfer.
Figure 3 shows a typical data path configuration for a cascaded pair of FSP100s being driven by a standard A-D
input and D-A output. Input and Output timing diagrams
follow.
11-59
FSP100
Figure 3 Dual Processor Configuration with Analog Input and Output
ANALOG TO
DIGITAL
SUBSYSTEM
STATUS
PASSIVE
-
*
[
Voo
*
PASSIVE
*
ACTIVE
OPDR
INRQ
OPDR
INDR FSP100 OPRQ
OPSD
INSD
INDR
FSP100 0PRQ
OPSD
OPCK
INCK
INRQ
SERIAL DATA
ACTIVE
INCK
INSD
I
CLK
*
ENABLE
OPCK
DIGITAL TO
ANALOG
SUBSYSTEM
SERIAL DATA
~
* HAND SHAKE MODE
Data Input Timing/Handshake Timing ("n" Bit Data)
ACTIVE/FSP100 READY
INCK
INRQ
_-+-,i/
-0 L
\1...._ _ _ __
IROAR
INDR
INSD
---ii,
DON'T CARE OCr--BI-T-O-"'X
,----------------r
-------------------~\
!
X'-_ _-I
BtT 1
:BIT(n-l)
X~__~B~IT~n~_JX~__~D~O~N_'T_C~A_R~E~___
--If--t,OL
ACTIVE/NOT READY AND PASSIVE/NOT READY
INCK
tNRQ
tNDR
__-,I
INSD
_ _ ___iX~_ _ _ _ _ _ _ _
BI_T_O_ _ _ _ _ _ ___iX
,,------------------------------------BIT 1
--------------"'\
\
!
8 ___
B
__'__
T_n___E ' T CARE
PASSIVE/READY
INCK
~
INRQ
\~--
INDR
INSD
,--------
I
________
D_O_N_'T_C_A_R_E_ _ _ _ _-'X
BIT 0
X
BIT 1
----------~-------~\ !
: BIT (n-l)
X~_B_I_T_n_ _ _ _ __
WFOO57QF
11-60
FSP100
Data Output Timing ("n" Bit Data)
ACTIVE/FSP100 READY
OPCK
OPRQ
,-----
~
I
- - - - I !--tROAR
I\---------------------~
OPDR - - - - - - - ' /
-+'IX
OPSD _ _ _ _ _ _ _B_I_T_O_ _ _ _
BIT t
--l ~IOSD
X
x:
BIT 2
,~-------------\
BI~
BIT n
Xr-UN-D-E-F-IN-E-D
ACTIVE/NOT READY AND PASSIVE/NOT READY
OPCK
--l
!--tROANR
OPRQ ____________________________~I
OPDR
-.I
f
_~(---~,~_ _
,---------------------------------
,,
--------------~
J
OPSD ____U_N_D_E_F_IN_E_D_ _
-'X~_________B_IT__O____________~x:: BI~~___BI_T_n___~D
PASSIVE/READY
OPCK
OPRQ ________________________- - J
J
(~(---~',-_ _
I
OPSD
,
--------------~
OPOR ___________________________________~I
)
::::==J(~________________B_IT_O_________________...x::BI~----B-I-T-n-----------
PFD Reset Operation
CPU CLOCK
(ClK)
RESET
PROGRAM COUNTER
(PAO-PA7)
TRI-STATE
BYTE COUNTER
(PBO-PB2)
TRI-STATE
PROGRAM DATA
(00-07)
DON'T CARE
ADDRESS
DON'T CARE
DON'T CARE
NEXT
1 - - - - - - TAESET-------!
NOTE: TRESET must be the greater time period of 25 CPU clock cycles of three (3) Input Data Clock cycles.
11-61
•
FSP100
Absolute Maximum Ratings 1
Symbol
Characteristic
VDD
Supply Voltage
VI
Input Voltage
II
dc Input Current
TSTG
Storage Temperature
Ceramic Package
Plastic Package
TA
TL
Range
Unit
-0.5 to +6.0
V
-0.5 to VDD +0.5
V
±20
mA
°C
-65 to + 150
-40 to +125
Ambient Temperature
Under Bias2
Commercial/Industrial
°C
-40 to +70
Lead Temperature (Soldering, 10 s)
300
°C
Electrical Characteristics Voo = 5.0 V ± 0.25 V, 0 to 70 0 e
Symbol
Characteristic
Conditions
Min
Max
Unit
VIH
Input HIGH Voltage CMOS Input
TTL Input
Guaranteed Input HIGH Voltage
3.5
2.0
VDD
VDD
V
VIL
Input LOW Voltage CMOS Input
TTL Input
Guaranteed Input LOW Voltage
-0.5
-0.5
1.5
0.8
V
V
VOH
Output HIGH Voltage
70°C, VDD
V
VDD
-0.05
V
VOL
Output LOW Voltage
70°C,
V
liN
Input Leakage Current
VIN
loz
Three-State Output Leakage
Current
= 4.5
VDD = 4.5
= VDD or GND
VOUT = VDD or GND
0.1
V
-10
10
p.A
-10
10
p.A
CIN
Input Capacitance
Excluding Package
5.0
pF
COUT
Output Capacitance
Excluding Package
5.0
pF
Notes
1. Stresses greater than those listed under Absolute Maximum Ranges may
cause permanent damage to the device. This is a stress rating only;
operation of the device at any condition above those indicated in the
operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
2. Junction temperature may not exceed ambient temperature by more than
20·C.
11-62
F2224· F2212
2400/1200/600/300 bps
Full Duplex Modem
FAIRCHILO
A Schlumberger Company
Advance Information, June 1986
Advanced Signal Processing Division
Description
Connection Diagram
28-Lead DIP
(Top View)
The F2224 and F2212 are single-chip full-duplex modem
circuits, operating at 2400 (F2224 only), 1200, 600 and
0-300 bps. The F2224 is compatible with the CCITI V.22
bis modem specification, and both chips are compatible
with V.22B, Bell 212A, Bell 103, V.21, V.23 and Bell 202.
The ICs perform all signal processing functions, and feature both a parallel microprocessor interface with integral
UART and an alternate four line serial control and separate data interface.
Voo
Vss
GND
NC
XTL1
The F2212, under control of a host processor or dedicated microcontroller, provides a complete low-cost solution
to data transmission at speeds up to 1200 bps and is pin
for pin and functionally compatible with the F2224, which
provides an upgrade path to 2400 bps operation, with minimal changes to existing firmware. Handshaking protocols
are included on-chip, which will reduce control-processor
firmware requirements.
XTL2
BCLK
RXIN
TX01
TX02
IN1
IN2
An on-chip hybrid simplifies connection to the telephone
network and uncommitted I/O lines are provided for DAA
control and RS232 implementation if required. DTMF dialing and call progress tone detection are included.
oun
OUT2
• V_22 bis (F2224 Only), V.22B, 212A, 103, V.21, V.23
And Bell 202 Compatible
• V.23 And 202 Modes Have Selectable 75 Or 150 bps
Backward Channels
• Performs All Signal Processing Functions
• Parallel J.l.P Interface With Integral UART
• Alternate Serial Control And Data Interface
• Register Control Of Modem And UART Operation
• DTMF Tone Generation And Call Progress Tone
Detection For Smart Dialer Applications
• 1300 Hz Calling Tone Generator On Chip
• On-Chip Hybrid And Programmable 1/0 For DAA
Control And RS232 Implementation
• Very Few External Components Required
• Low Power Dissipation And A Very Low Power
Standby Mode
• 28-Lead Ceramic DIP, Plastic DIP And Surface Mount
Packages
Order Information
Device Code
F2224DC
F2224PC
F2224QC
F2212DC
F2212PC
F2212QC
11-63
Package Code
Package Description
FM
Ceramic DIP
Molded DIP
Molded Surface Mount
Ceramic DIP
Molded DIP
Molded Surface Mount
FM
•
F=AIRCHILO
A Schlumberger Company
F30S54/F30S57
Monolithic Serial Interface
CMOS CODEC/FILTER
Preliminary
Advanced Signal Processing Division
Description
The F30S54, F30S57 family consists of Jl-Iaw and A-law
monolithic PCM CODEC/FILTERS utilizing the AID and
0/ A conversion architecture shown in Figure 1, and a serial PCM interface. The F30S54, F30S57 operate in the
synchronous mode only and are pin compatible with the
F3054 and F3057 respectively. The devices are fabricated
using Fairchild's advanced Double Poly Silicon-Gate CMOS
process.
Connection Diagram
(Top View)
The transmit portion of each device consists of an input
gain adjust amplifier, an active RC pre-filter, a switchedcapacitor band-pass filter, and a compressing encoder with
auto-zero circuitry. The active RC pre-filter eliminates very
high frequency noise, and the switched-capacitor filter rejects signals below 200 Hz and above 3400 Hz. The compressing encoder samples the filtered signal and encodes
it in the compressed Jl-Iaw and A-law PCM format. The
receive portion of each device consists of an expanding
decoder, which reconstructs the analog signal from the
compressed Jl-Iaw or A-law code, a low-pass filter which
corrects for the sin x/x response of the decoder output
and rejects signals above 3400 Hz and is followed by a
single-ended power amplifier capable of driving low impedance loads. The devices require a 1.536 MHz, 1.544 MHz
or 2.048 MHz master clock and an 8 kHz frame sync
pulse. The timing of the frame sync pulses and PCM data
is compatible with both industry· standard formats.
16
v••
VFxt+
GND
VFxl-
VFRO
GS.
vee
TSx
NC
FS
DR
Ox
CLKSEL
NC
PDN
Order Information
Device Code
Package Code
F30S54DC
FW
F30S57DC
FW
• Pin Compatible with F3054, F3057
• Complete Codec and Filtering System Including:
• Transmit High-Pass and Low-Pass Filtering
• Receive Low-Pass Filter with Sin X/X Correction
• Active RC Noise Filters
• Jl-Law or A-Law Compatible Coder and Decoder
• Internal Precision Voltage Reference
• Serial 110 Interface
• Internal Auto-Zero Circuitry
• Jl-Law, 16 Pin - F30S54
• A-Law, 16 Pin - F30S57
• Meets or Exceeds all D3/D4 and CCITT
Specifications
• ± 5 V Operation
• Low Operating Power-Typically 40 mW
• Power-Down Standby Mode - Typically 1.7 mW
• Automatic Power-Down
• TTL or CMOS Compatible Digital Interfaces
• Maximizes Line Interlace Card Circuit Density
11-64
MCLK
Package Description
Ceramic DIP
Ceramic DIP
F30S54/F30S57
Figure 1 Block Diagram
R,
GSx
------------------------------------------------------ -----~
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ANAL~ _-'V'VI/1F..x_' ....-..!.-f
RC
ACllVE
FILlER
I
I
I
I
I
SWITCHED
CAPACITOR
BAND-PASS
FILlER
I
I
I
I
AID
VOLTAGE
REFERENCE
XMT
REGISTER
CONTROL
LOGIC
Dx
COMPARATOR
POWER
AMPLIFIER
VFRO
SWITCHED
-----,c-<
ReV
CAPACITOR
LOW-PASS
REGISTER
RLlER
llMNG AND CONTROL
+5V
-SV
Vee
Va.
GND
MCLK
11-65
PDN
CLKSEL
FS
DR
F30S54/F30S57
Pin Description
Pin No.
Function
Name
1
2
3
4
5
6
7
VBB
GND
VFRO
Vee
N.C.
DR
CLKSEL
8
9
10
11
12
PDN
MCLK
N.C.
Dx
FS
13
14
15
16
TSx
GSx
VFxl VFxl +
Negative power supply pin. VB B = -5.0 V ± 5%.
Ground. All Signals are referenced to this pin.
Analog output of the receive filter.
Positive power supply pin. Vee = + 5.0 V ± 5%.
No internal connection.
Receive data input. PCM data is shifted into DR following the FS leading edge.
Logic input which selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock.
MCLK is used for both transmit and receive directions (see Table 1).
Power Down. The device is powered up when PDN is held low.
Master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz.
No internal connection.
The 3-state PCM data output which is enabled by FS.
Frame sync pulse input which enables MCLK to shift out the PCM data on Dx.
FS is an 8 kHz pulse train; see Figures 2 and 3 for timing details.
Open drain output which pulses low during the encoder time slot.
Analog output of the transmit input amplifier. Used to externally set gain.
Inverting input of the transmit input amplifier.
Non-inverting input of the transmit input amplifier.
Functional Description
Power-Up
When power is first applied, power-on reset circuitry initializes the device and places it into the power-down mode.
All non-essential circuits are deactivated and the Dx and
VFRO outputs are put in high impedance states. To power-up the device, a logical low level must be applied to
the PDN pin and FS pulses must be present. Thus, two
power-down control modes are available. The first is to
pull the PDN pin high; the second is to hold the FS input
continuously low - the device will power-down approximately 2 ms after the last FS pulse. Power-up will occur
on the first FS pulse. The 3-state PCM data output, Dx,
will remain in the high impedance state until the second
FS pulse.
Synchronous Operation
Synchronous operation requires only one masterclock for
both the transmit and receive directions. Table 1 indicates
the frequencies which can be selected, depending on the
state of CLKSEL. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each
frame.
Table 1 Selection of Master Clock Frequencies
Master Clock
Frequency Selected
CLKSEL
11-66
F30S57
F30S54
o
1.536 MHz or
1.544 MHz
2.048 MHz
1 (or Open
Circuit)
2.048 MHz
1.536 MHz or
1.544 MHz
F30S54/F30S57
Functional Description (Cont.)
gains in excess of 20 dB across the audio passband to
be realized. The op amp drives a unity-gain filter consisting of an RC active pre-filter, followed by an eighth order
switched-capacitor bandpass filter clocked at 128 kHz. The
output of this filter directly drives the encoder sample-andhold circuit. The A/D is of compressing type according to
!.I-law (F30S54) or A-law (F30S57) coding conventions. A
precision voltage reference is trimmed in manufacturing to
provide an input overload level (tMAX) of nominally 2.5 V
peak (see table of Transmission Characteristics). The FS
frame sync pulse controls the sampling of the filter output,
and then the successive-approximation encoding cycle begins after the decode cycle. The 8-bit code is then loaded
into a buffer and shifted out through Dx at the next FS
pulse. The total encoding delay will be approximately
165 !.Is (due to the transmit filter) plus 125 !.IS (due to
encoding delay), which total 290 !.Is. Any offset voltage
due to the filters or comparator is cancelled by sign bit
integration.
Short Frame Sync Operation
The device can utilize either a short frame sync pulse or
a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, the
frame sync pulse, FS, must be one MCLK period long,
with timing relationships specified in Figure 2. With FS
high during a falling edge of MCLK, the next rising edge
of MCLK enables the Dx 3-state output buffer, which will
output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge
disables the Dx output. The corresponding eight falling
edges of the same clock pulses will clock in the receive
data.
Long Frame Sync Operation
To use the long frame sync mode, the frame sync pulse,
FS, must be three or more MCLK periods long, with timing
relationships specified in Figure 3. Based on the sync, FS,
the device will sense whether short or long frame sync
pulses are being used. The Dx 3-state output buffer is
enabled with the rising edge of FS or the rising edge of
MCLK, whichever comes later, and the first bit clocked out
is the sign bit. The following seven MCLK rising edges
clock out the remaining seven bits. The Dx output is disabled by the eighth falling edge of MCLK, or by FS going
low, whichever comes later. Provided the frame sync FS is
greater than three MCLK periods, the Dx output will be
enabled for eight MCLK periods, independent of the actual
length of the FS pulse.
Receive Section
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 128 kHz. The decoder is A-law (F30S57) or
•
!.I-law (F30S54) and the 5th order low pass filter corrects
for the sin x/x attenuation due to the 8 kHz sample/hold.
The filter is then followed by a power amplifier capable of
driving a 600 n load to a level of 7.2 dBm. The receive
section is· unity gain. Upon the occurrence of FS the data
at the DR input is clocked in on the falling edge of the
next eight MCLK periods. At the end of the time slot, the
decoding cycle begins, and 10 !.IS later the decoder DAC
output is updated. The total decoder delay is approximately 10 !.IS (decoder update) plus 110 !.IS (filter delay) plus
62.5 !.IS (Y2 frame), which gives approximately 180 !.Is).
Transmit Section
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see Figure 1. The low noise and wide bandwidth allow
11-67
F30S54/F30S57
Absolute Maximum Ratings
Vee to GND
VSS to GND
Voltage at any Analog Input
or Output
Voltage at any Digital Input
or Output
7.0 V
-7.0 V
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)
Vee + 0.3 V to
Vss-0.3 V
Vee+0.3 V to
GND-0.3 V
-25°C to + 125°C
-65°C to + 150°C
300°C
Electrical Characteristics Unless otherwise noted: Vee = 5.0 V ± 5%, Vaa - 5.0 V ± 5%, GND = 0 V, TA = O°C
to 70°C; typical characteristics specified at Vee = 5.0 V, Vaa = -5.0 V, TA = 25°C; all
signals are referenced to GND.
Symbol
Characteristic
Condition
Unit
Operating Current
leeO
Power-Down Current
0.3
1.5
rnA
IssO
Power-Down Current
0.03
0.3
rnA
lee1
Active Current
4.0
7.0
rnA
Iss1
Active Current
4.0
7.0
rnA
0.6
V
0.4
0.4
V
V
10
p.A
Digital Interface
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
Dx, IH = -3.2 rnA
IlL
Input Low Current
GND .;;; VIN .;;; VIL, All Digital Inputs
-10
IIH
Input High Current
VIH .;;; VIN .;;; Vee
-10
10
p.A
102
Output Current in High
Impedance State
Dx, GND';;;Vo';;;Vee
-10
10
iJ.A
200
2.2
V
*IL=3.2 rnA
T x, IL = 3.2 rnA, Open Drain
2.4
V
Analog Interface With Transmit Amplifier Input
IIXA
Input Leakage Current
-2.5 V';;;V';;; +2.5 V, VFxl + or VFxl-
-200
RIXA
Input Resistance
-2.5 V';;; V';;; +2.5 V, VFxl + or VFxl-
10
RoXA
Output Resistance
Closed Loop, Unit Gain
RLXA
Load Resistance
GSx
CLXA
Load Capacitance
GSx
VoXA
Output Dynamic Range
GSx, RL ;;;>10 kn
±2.8
V
AvXA
Voltage Gain
VFxl + to GS x
5000
VIV
1.0
3.0
10
n
kn
50
1.0
nA
Mn
pF
FuXA
Unity Gain Bandwidth
VosXA
Offset Voltage
-20
20
VeMXA
Common-Mode Voltage
-2.5
2.5
CMRRXA
Common-Mode Rejection Ratio
60
dB
PSRRXA
Power Supply Rejection Ratio
60
dB
Analog Interface With Receive Amplifier Output
RoRF
Output Resistance
Pin VFRO
RLRF
Load Resistance
VFRO = ± 2.5 V
11-68
2.0
MHz
mV
V
F30S54/F30S57
Electrical Characteristics (Cont.) Unless otherwise noted: Vee = 5.0 V ± 5%, Vss - 5.0 V ± 5%, GND = 0 V,
TA = O°C to 70°C; typical characteristics specified at Vee = 5.0 V, Vss = -5.0 V,
TA = 25°C; all signals are referenced to GND.
Symbol
Characteristic
Condition
CLRF
Load Capacitance
VFRO to GND
VOSRO
Output DC Offset Voltage
VFRO to GND
Min
Typ
-200
Max
Unit
25
pF
200
mV
Timing Specifications
-
1/tpM
Frequency of Master Clock
tWMH
Width of Master Clock High
160
tWML
Width of Master Clock Low
160
tRM
Rise Time of Master Clock
50
ns
tFM
Fall Time of Master Clock
50
ns
tHMF
Holding Time from Master
Clock Low to Frame Sync
Long Frame Only
0
ns
tHOLO
Holding Time from Master
Clock High to Frame Sync
Short Frame Only
0
ns
tSFM
Set-Up Time from Frame Sync
to Master Clock Low
Long Frame Only
80
ns
tOMO
Delay Time from MCLK High to
Data Valid
Load = 150 pF plus 2 LSTTL Loads
txop
Delay Time to TSx Low
Load
tozc
Delay Time from MCLK Low to
Data Output Disabled
tOZF
Delay Time to Valid Data from
FS or MCLK, Whichever
Comes Later
tSOM
Set-Up Time from DR Valid to
MCLK Low
50
ns
tHMO
Hold Time from MCLK Low to
DR Invalid
50
ns
tSF
Set-Up time from FS to MCLK
Low
Short Frame Sync Pulse (1 or 2 Clock
Periods Long) (Note 1)
50
ns
tHF
Hold Time from MCLK Low to
FS
Short Frame Sync Pulse (1 or 2 Clock
Periods Long) (Note 1)
100
ns
tHMFI
Hold Time from 3rd Period of
Master Clock Low to Frame
Sync FS
Long Frame Sync Pulse (from 3 to 8
Clock Periods Long)
100
ns
Note
short frame sync timing,
For
FS
Depends on the CLKSEL Pin
= 150
1.536
1.544
2.048
0
pF plus 2 LSTTL Loads
CL = 0 pF to 150 pF
must go high while the Master Clock is high,
11-69
MHz
MHz
MHz
ns
ns
180
ns
140
ns
50
165
ns
20
165
ns
F30S54/F30S57
Transmission Characteristics Unless otherwise specified: T A = ooe to 70 oe, Vee = 5.0 V ± 5%, VBB = -5.0 V
± 5%, GND = 0 V, f = 1.02 kHz, VIN = 0 dBmO, transmit input amplifier
connected for unity-gain non-inverting.
Symbol
Unit
Condition
Characteristic
Amplitude Response
Absolute Levels
Vrms
Nominal 0 dBmO Level is 4 dBm
(600 n)
o dBmO
F30S54
F30S57
tMAX
Max Overload Level
F30S54 (3.17 dBmO)
F30S57 (3.14 dBmO)
GXA
Transmit Gain, Absolute
TA = 25°C, Vcc = 5 V, VBB = -5 V
Input at GSx = 0 dBmO at 1020 Hz
GXR
Transmit Gain, Relative to GXA
f = 16 Hz
f = 50 Hz
f = 60 Hz
f = 200 Hz
f = 300 Hz - 3000 Hz
f = 3300 Hz
f = 3400 Hz
f = 4000 Hz
f = 4600 Hz and Up, Measure
Response from 0 Hz to 4000 Hz
GXAT
Absolute Transmit Gain
Variation with Temperature
TA = O°C to 70°C
GXAV
Absolute Transmit Gain
Variation with Supply Voltage
Vce = 5 V ± 5%, VBB = -5 V ± 5%
GXRL
Transmit Gain Variations with
Level
Sinusoidal Test Method
Reference Level = -10 dBmO
VFxl + = -40 dBmO to + 3 dBmO
VFxl + = -50 dBmO to -40 dBmO
VFxl + = -55 dBmO to -50 dBmO
1.2276
1.2276
2.501
2.492
-0.15
VPK
VPK
0.15
dB
-40
-30
-26
-0.1
0.15
0.05
0
-14
-32
dB
dB
dB
dB
dB
dB
dB
dB
dB
±0.1
dB
±0.05
dB
-0.2
-0.4
-1.2
0.2
0.4
1.2
dB
dB
dB
-1.8
-0.15
-0.35
-0.7
GRA
Receive Gain, Absolute
TA = 25°C, Vee = 5 V, VBB = -5 V
Input = Digital Code Sequence for
o dBmO Signal at 1020 Hz
-0.15
0.15
dB
GRR
Receive Gain, Relative to GRA
f
f
f
f
-0.15
-0.35
-0.7
0.15
0.05
0
-14
dB
dB
dB
dB
GRAT
Absolute Receive Gain Variation
with Temperature
TA = O°C to 70°C
±0.1
dB
GRAV
Absolute Receive Gain Variation
with Supply Voltage
Vee = 5 V ± 5%, VBB = -5 V ± 5%
±0.05
dB
GRRL
Receive Gain Variations with
Level
Sinusoidal Test Method; Reference
Input PCM Code Corresponds to an
Ideally Encoded-10 dBmO Signal
PCM Level = -40 dBmO to +3 dBmO
PCM Level = -50 dBmO to -40 dBmO
PCM Level = -55 dBmO to -50 dBmO
-0.2
-0.4
-1.2
0.2
0.4
1.2
dB
dB
dB
-2.5
2.5
V
VRo
Receive Output Drive Level
=
=
=
=
0 Hz
3300
3400
4000
RL = 600
to 3000 Hz
Hz
Hz
Hz
n
11-70
F30S54/F30S57
Transmission Characteristics (Cont.) Unless otherwise specified: TA = O·C to 70·C, Vee = 5.0 V ± 5%,
Vss = -5.0 V ± 5%, GND = 0 V, f = 1.02 kHz, VIN = 0 dBmO, transmit input
amplifier connected for unity-gain non-inverting.
Symbol
Characteristic
Unit
Condition
Envelope Delay Distortion With Frequency
DXA
Transmit Delay, Absolute
f=1600 Hz
290
315
IlS
DXR
Transmit Delay, Relative to DXA
f = 500 Hz - 600 Hz
f=600 Hz-800 Hz
f = 800 Hz-1000 Hz
f = 1000 Hz -1600 Hz
f = 1600 Hz - 2600 Hz
f = 2600 Hz - 2800 Hz
f = 2800 Hz - 3000 Hz
195
120
50
20
55
80
130
220
145
75
40
75
105
155
IlS
IlS
IlS
IlS
IlS
IlS
IlS
DRA
Receive Delay, Absolute
1=1600 Hz
180
DRR
Receive Delay, Relative to DRA
f
f
f
f
f
=
=
=
=
=
500 Hz - 1000 Hz
1000 Hz -1600 Hz
1600 Hz - 2600 Hz
2600 Hz - 2800 Hz
2800 Hz - 3000 Hz
-40
-30
200
Ils
-25
-20
70
100
145
90
125
175
IlS
IlS
IlS
IJ.S
IlS
dBrn
Noise
co
Nxe
Transmit Noise, C Message
Weighted
F30S54 VFxl + = 0 V
12
15
Nxp
Transmit Noise, P Message
Weighted
F30S57 VFxl + = 0 V
-74
-69
(Note 1)
NRC
Receive Noise, C Message
Weighted
F30S54 PCM Code Equals Alternating
Positive and Negative Zero
NRP
Receive Noise, P Message
Weighted
F30S57 PCM Code Equals Positive
Zero
NRS
Noise, Single Frequency
1 = 0 kHz to 100 kHz, Loop Around
Measurement, VFxl + = 0 Vrms
PPSRx
Positive Power Supply
Rejection, Transmit
VFxl + = 0 Vrms,
Vee = 5.0 Voe + 100 mVrms
1 = 0 kHz - 50 kHz
40
dBC
NPSRx
Negative Power Supply
Rejection, Transmit
VFxl + = 0 Vrms,
VB B = -5.0 Voe + 100 mVrms
1 = 0 kHz - 50 kHz
40
dBC
PPSRR
Positive Power Supply
Rejection, Receive
PCM Code Equals Positive Zero
Vee = 5.0 Voe + 100 mVrms
1=0 Hz-4000 Hz
1 = 4 kHz - 25 kHz
1 = 25 kHz - 50 kHz
40
40
36
dBC
dB
dB
PCM Code Equals Positive Zero
VBB = -5.0 Voe + 100 mVrms
1 = 0 Hz-4000 Hz
1 = 4 kHz - 25 kHz
1 = 25 kHz - 50 kHz
40
40
36
dBC
dB
dB
NPSRR
Negative Power Supply
Rejection, Receive
11-71
dBmOp
dBrnCo
8.0
11
-82
-79
dBmOp
-53
dBmO
F30S54/F30S57
Transmission Characteristics (Cont.) Unless otherwise specified: TA = O°C to 70°C, Vee = 5.0 V ± 5%,
Vss = -5.0 V ± 5%, GND = 0 V, f = 1.02 kHz, VIN = 0 dBmO, transmit input
amplifier connected for unity-gain non-inverting.
Symbol
SOS
Characteristic
Spurious Out-ot-Band Signals at
the Channel Output
Condition
Typ
Min
Unit
Max
Loop Around Measurement, 0 dBmO,
300 Hz - 3400 Hz Input Applied to
VFxl +, Measure Individual Image
Signals at VFRO
4600 Hz - 7600 Hz
7600 Hz - 8400 Hz
8400 Hz - 100,000 Hz
-32
-40
-32
dB
dB
dB
Distortion
STDx
STDR
Signal to Total Distortion
Transmit or Receive
Half-Channel
SFDx
Single Frequency Distortion,
Transmit
-46
dB
SFDR
Single Frequency Distortion,
Receive
-46
dB
IMD
Intermodulation Distortion
Loop Around Measurement,
VFxl + = -4 dBmO to -21 dBmO,
Two Frequencies in the Range
300 Hz - 3400 Hz
-41
dB
Transmit to Receive Crosstalk,
o dBmO Transmit Level
f = 300 Hz - 3400 Hz
DR = Steady PCM Code
-75
dB
Receive to Transmit Crosstalk,
Receive Level
f = 300 Hz - 3400 Hz, VFxl =
-70
dB
Sinusoidal Test Method
Level = 3.0 dBmO
= 0 dBmO to -30 dBmO
= -40 dBmO XMT
RCV
= -55 dBmO XMT
RCV
33
36
29
30
14
15
dBC
dBC
dBC
dBC
dBC
dBC
Crosstalk
CTX_R
CTR_X
o dBmO
-90
oV
-90
(Note 2)
Notes
1. Measured by extrapolation from the distortion test result.
2. CT R-X is measured with a - 40 dBmO activating signal applied at VFxl + .
Encoding Format At Ox
F30S54
Il-Law
VIN (at GSx) = + Full-Scale
VIN (at GSx) = 0 V
VIN (at GSx) = - Full-Scale
1 0
F30S57
A·Law
(Includes Even Bit Inversion)
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0 0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
[~
11-72
Figure 2 Timing Diagrams Short Frame Sync Timing
TS.
MCLK
FS
OR
D.
Figure 3
,
(X2){
X
X
XiX
>8--
Long Frame Sync Timing
TSx
MCLK
.:..
FS
'"
"TI
DR
Ox
I" I
¢(
"'--__, I"
1
X
1'...._ __
flI.,,"--- ~ .
,'....-----"
>¢
),
"
"
"
,~
'\....:-oL
W
o
en
C1'I
01:1......
"TI
W
o
en
C1'I
.....
F30S54/F30S57
Applications Information
T-Pad Attenuator
I
I
I
Z1i
R2
I
I
I
II
iZ2
800n
I
I
I
L_____ _ ___..1
R1
=Z1 (N2+'
)_ 2V Z1 ,Z2 (~)
~-1
tf2-1
R2=2V Z1 ,Z2
All ground connections to each device should meet at a
common point as close as possible to the GND pin. This
minimizes the interaction of ground return currents flowing
through a common bus impedance. 0.1 /-IF supply decoupiing capacitors should be connected from this common
ground point to Vee and Vss.
For best performance, the ground point of each CODECI
FILTER on a card should be connected to a common
card ground in star formation, rather than via a ground
bus. This common ground point should be decoupled to
Vee and Vss with 10 /-IF capacitors.
10
>-_300wn'v--:I_-. -,..;'
. V'.-...-""j-r--_-"';""-,...-_'+I_,':V2
Power Supplies
While the pins of the F30S54 family are well protected
against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is
connected to the device before any other connections are
made. In applications where the printed circuit board may
be plugged into a "hot" socket with power and clocks
already present, an extra long ground pin in the connector
should be used.
Wh
ere
N-V
-
(;.J
POWERIN
POWER OUT
and
s=~
Also: Z= VZSco Zoe
Where Zsc = Impedance with short clrcuH termination
and Zoe = impedance with open circuit termination
1T-Pad Attenuator
,....-----------,
300n
Receive Gain Adjustment
For applications where a F30S54 family CODEC/FILTER
receive output must drive a 600
load, but a peak swing
lower than ± 2.5 V is required, the receive gain can be
easily adjusted by inserting a matched T-pad or 1T-pad at
the output. Table II lists the required resistor values for
600
terminations. As these are generally non-standard
values, the equations can be used to compute the attenuation of the closest practical set of resistors. It may be
necessary to use unequal values for the R1 or R4 arms
of the attenuators to achieve a precise attenuation. Generally it is tolerable to allow a small deviation of the input
impedance from nominal while still maintaining a good return loss. For example a 30 dB return loss against 600
is obtained if the output impedance of the attenuator is in
the range 282 n to 319 n (assuming a perfect transformer).
I
R3
I
R-'4M~,...R4-+1Z2-'
>---'\M-Z1-l1-......
n
I
I
I
I
I
,
L__________ J
n
R3=V¥(~;1)
R3=Z1(~)
tt2-2NS+ 1
n
11-74
"0
1:"1/2
600n
F30S54/F30S57
Applications Information (Cont.)
Table II. Attentuator Tables for Z1
(All Values in Q)
dB
R1
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
13
14
15
16
18
20
1.7
3.5
5.2
6.9
8.5
10.4
12.1
13.8
15.5
17.3
34.4
51.3
68
84
100
115
179
143
156
168
180
190
200
210
218
233
246
Figure 4
=Z2 =300
Q
R2
R3
R4
26k
13k
6.7k
6.5k
5.2k
4.4k
3.7k
3.3k
2.9k
2.6k
1.3k
850
650
494
402
380
284
244
211
184
161
142
125
110
98
77
61
3.5
6.9
10.4
13.8
17.3
21.3
24.2
27.7
31.1
34.6
70
107
144
183
224
269
317
370
427
490
550
635
720
816
924
i.17k
1.5k
52k
26k
17.4k
13k
10.5k
8.7k
7.5k
6.5k
5.8k
5.2k
2.6k
1.8k
1.3k
1.1k
900
785
698
630
527
535
500
473
450
430
•
413
386
I
366
Typical Synchronous Application
-sv
V,,
VFxl +
GNO
VFx l -
FROMSlIC
*O.,"F
-&
*O.,"F
+5V
Vee
TO sue
VFRO
-----------
GSx
F30S54
F30S57
~
R2
~
ANALOG INTERFACE
----------------- -----------.
DIGITAL INTERF ACE
FS
Fs
Ox
5VorGND
PON
CLKSEL
BCLK
PON
MCLK
:I
MCLK
(2.048 MHz/ 1.544 MHz/1.536 MHz)
. =20 x log (01+02) ; (R1+ R2) > 10K!!
Note 1: XMITgaln
~
11-75
F=AIRCHILO
A Schlumberger Company
F30S64/F30S67
Monolithic Serial Interface
CMOS CODEC/FILTER
Preliminary
Advanced Signal Processing Division
Description
Connection Diagram
(Top View)
The F30S64, F30S67 family consists of !.I-law and A-law
monolithic PCM CODEC/FILTERS utilizing the AID and
D/ A conversion architecture shown in Figure 1, and a serial PCM interface. The F30S64, F30S67 operate in the
synchronous mode only and are pin compatible with the
TP3064 and TP3067 respectively. Similar to the F30S54
and F30S57, these devices feature an additional Receive
Power Amplifier to provide push-pull balanced output drive
capability. The receive gain can be adjusted by means of
two external resistors for an output level of up to ± 6.6 V
across a balanced 600
load. Also included is an analog
loopback switch and TSx output. The devices are fabricated using Fairchild's advanced Double Poly Silicon-Gate
CMOS process.
20
VPO+
GND
vpoVPI
VFnO
.n
The transmit portion of each device consists of an input
gain adjust amplifier, an active RC pre-filter, a switchedcapacitor band-pass filter, and a compressing encoder with
auto-zero circuitry. The active RC pre-filter eliminates very
high frequency noise, and the switched-capacitor filter rejects Signals below 200 Hz and above 3400 Hz. The compressing encoder samples the filtered Signal and encodes
it in the compressed !.I-law or A-law PCM format.
VB.
VFxl+
VFxlGSx
ANLB
Vee
TSx
NC
FS
DR
Ox
CLKSEL
PDN
NC
MCLK
Order Information
Device Code
F30S64DC
F30S67DC
Package Code
FL
FL
Package Description
Ceramic DIP
Ceramic DIP
The receive portion of each device consists of an expanding decoder, a switched-capacitor low-pass filter, and two
power amplifiers. The decoder reconstructs the analog signal from the compressed !.I-law or A-law code, and the
low-pass filter corrects for the sin x/x response of the
decoder output. The two power amplifiers are in a bridged
configuration and are capable of driving low impedance
loads.
The devices require a 1.536 MHz, 1.544 MHz or
2.048 MHz master clock and an 8 kHz frame sync pulse.
The timing of the frame sync pulses and PCM data is
compatible with both industry standard formats.
• Pin Compatible with TP3064, TP3067
• Complete Codec and Filtering System Including:
• Transmit High-Pass and Low-Pass Filtering
• Receive Low-Pass Filter with Sin X/X Correction
• Receive Push-Pull Power Amplifier
• Analog Loopback
• Active RC Noise Filters
• !.I-Law or A-Law Compatible Coder and Decoder
• Internal Precision Voltage Reference
• Serial I/O Interface
• Internal Auto-Zero Circuitry
• !.I-Law, 20 Pin - F30S64
• A-Law, 20 Pin - F30S67
• Meets or Exceeds all 03/04 and CCITT
Specifications
• ± 5 V Operation
•
•
•
•
•
11-76
Low Operating Power - Typically 45 mW
Power-Down Standby Mode - Typically 1.7 mW
AutomatiC Power-Down
TTL or CMOS Compatible Digital Interfaces
Maximizes Line Interface Card Circuit Density
F30S64/F30S67
Figure 1 Block Diagram
!
ANALOG
LOOPBACK
-----
GSx
--~--------------------------------------------------- ---l
/
I
I
/
/
I
I
I
I
I
I
I
I
I
I
/
R
I
I
RC
ACTIVE
FILTER
SWITCHED
CAPACITOR
BAND-PASS
FILTER
AID
CONTROL
LOGIC
VOLTAGE
REFERENCE
VPO
XUT
REGISTER
Ox
RCV
REGISTER
DR
R.
COMPARATOR
VPI
A4
VFRO
TIMING AND CONTROL
+5V
-SV
Vee
Va.
:
---------+---+----1 ----------!~!~-~~~~------- ----- ----- ----- ____J
eND
MCLK
11-77
PDN
CLKSEL
FS
F30S64/F30S67
Pin Description
Pin No.
Function
Name
1
2
3
4
VPO+
GND
VPOVPI
5
6
7
8
9
VFRO
Vee
N.C.
DR
CLKSEL
10
11
12
13
14
PDN
MCLK
N.C.
Dx
FS
15
16
TSX
ANLB
17
18
19
20
GSx
VFxl VFxl +
Vss
The non-inverted output of the receive power amplifier.
Ground. All signals are referenced to this pin.
The inverted output of the receive power amplifier.
Inverting input to the receive power amplifier. Also powers down both amplifiers
when connected to Vss.
Analog output of the receive filter.
Positive power supply pin. Vee = + 5 V ± 5%.
No internal connection.
Receive data input. PCM data is shifted into DR following the FS leading edge.
Logic input which selects either 1.536 MHz, 1.544 MHz or 2.048 MHz for master
clock. MCLK is used for both transmit and receive directions (See Table 1).
Power down. The device is powered up when PDN is held low.
Master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz.
No internal connection.
The 3-state PCM data output which is enabled by FS.
Frame sync pulse input which enables MCLK to shift out the PCM data on Dx and
shift in data on DR. FS is an 8 kHz pulse train, see Figures 2 and 3 for timing
details.
Open drain output which pulses low during the encoder time slot.
Analog Loopback control input. Must be set to logic '0' for normal operation. When
pulled to logiC '1', the transmit filter input is disconnected from the output of the
transmit preamplifier and connected to the VPO + output of the receive power
amplifier.
Analog output of the transmit input amplifier. Used to externally set gain.
Inverting input of the transmit input amplifier.
Non-inverting input of the transmit input amplifier.
Negative power supply pin. Vss = -5 V + 5%.
Functional Description
Power-Up
When power is first applied, power-on reset circuitry initializes the device and places it into the power-down mode.
All non-essential circuits are deactivated and the Dx and
VFRO outputs are put in high impedance states. To power-up the device, a logical low level must be applied to
the PDN pin and FS pulses must be present. Thus, two
power-down control modes are available. The first is to
pull the PDN pin high; the second is to hold the FS input
continuously low - the device will power-down approximately 2 ms after the last FS pulse. Power-up will occur
on the first FS pulse. The 3-state PCM data output, Dx,
will remain in the high impedance state until the second
FS pulse.
Synchronous Operation
Synchronous operation requires only one master clock for
both the transmit and receive directions. Table 1 indicates
the frequencies which can be selected, depending on the
state of CLKSEL. For 1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each
frame.
Table 1. Selection of Master Clock Frequencies
Master Clock
Frequency Selected
CLKSEL
11-78
F30S67
F30S64
o
1.536 MHz or
1.544 MHz
2.048 MHz
1 (or Open
Circuit)
2.048 MHz
1.536 MHz or
1.544 MHz
F30S64/F30S67
Functional Description (Cont.)
Short Frame Sync Operation
The device can utilize either a short frame sync pulse or
a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, the
frame sync pulse, FS, must be one MCLK period long,
with timing relationships specified in Figure 2. With FS
high during a falling edge of MCLK, the next rising edge
of MCLK enables the Dx 3-state output buffer, which will
output the sign bit. The following seven rising edges clock
out the remaining seven bits, and the next falling edge
disables the Dx output. The corresponding eight falling
edges of the same clock pulses will clock in the receive
data.
Long Frame Sync Operation
To use the long frame sync mode, the frame sync pulse,
FS, must be three or more MCLK periods long, with timing
relationships specified in Figure 3. Based on the sync, FS,
the device will sense whether short or long frame sync
pulses are being used. The Dx 3-state output buffer is
enabled with the rising edge of FS or the rising edge of
MCLK, whichever comes later, and the first bit clocked out
is the sign bit. The following seven MCLK rising edges
clock out the remaining seven bits. The Dx output is disabled by the eighth falling edge of MCLK, or by FS going
low, whichever comes later. Provided the frame sync FS is
greater than three MCLK periods, the Dx output will be
enabled for eight MCLK periods, independent of the actual
length of the FS pulse.
Transmit Section
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see Figure 1. The low noise and wide bandwidth allow
gains in excess of 20 dB across the audio passband to
be realized. The op amp drives a unity-gain filter consisting of an RC active pre-filter, followed by an eighth order
switched-capacitor bandpass filter clocked at 128 kHz. The
output of this filter directly drives the encoder sample-andhold circuit. The AID is of compressing type according to
/-I-law (F30S64) of A-law (F30S67) coding conventions. A
precision voltage reference is trimmed in manufacturing to
provide an input overload level (tMAX) of nominally 2.5 V
peak (see table of Transmission Characteristics). The FS
frame sync pulse controls the sampling of the filter output,
and then the successive-approximation encoding cycle begins after the decode cycle. The 8-bit code is then loaded
into a buffer and shifted out through Dx at the next FS
pulse. The total encoding delay will be approximately
165 /-IS (due to the transmit filter) plus 125 p.s (due to
encoding delay), which totals 290 p.s. Any offset voltage
due to the filters or comparator is cancelled by sign bit
integration.
Receive Section
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 128 kHz. The decoder is A-law (F30S67) or
/-I-law (F30S64) and the 5th order low pass filter corrects
for the sin x/x attenuation due to the 8 kHz sample/hold.
The filter is then followed by a 2nd order RC active postfilter with its output at VFRO. The receive section is unitygain, but gain can be added by using the power
amplifiers. Upon the occurrence of FS the data at the DR
input is clocked in on the falling edge of the next eight
MCLK periods. At the end of the time slot, the decoding
cycle begins, and 10 p.s later the decoder DAC output is
updated. The total decoder delay is -10 p.s (decoder update) plus 110 p.s (filter delay) plus 62.5 /-IS (1'2 frame),
which gives approximately 180 p.s.
Receive Power Amplifiers
Two inverting mode power amplifiers are provided for directly driving a matched line interface transformer. The
gain of the first power amplifier can be adjusted to boost
the ± 2.5 V peak output signal from the receive filter up to
± 3.3 V peak into an unbalanced 300 .Q load, or ± 4.0 V
into an unbalanced 15 k.Q load. The second power amplifier is internally connected in unity-gain inverting mode to
give 6 dB of Signal gain for balanced loads.
Maximum power transfer to a 600 .Q subscriber line termination is obtained by differentially driving a balanced transformer with a \12:1 turns ration, as shown in Figure 4. A
total peak power of 15.6 dBm can be delivered to the
load plus termination.
Both power amplifiers can be powered down independently
from the PDN input by connecting the VPI input to Vee,
saving approximately 8 mW of power.
11-79
•
F30S64/F30S67
Absolute Maximum Ratings
Vcc to GND
VBB to GND
Voltage at any Analog Input
or Output
Voltage at any Digital Input
or Output
7.0 V
-7.0 V
Vcc + 0.3 V to
GND-0.3 V
-25°C to +125°C
-65°C to + 150°C
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(Soldering, 10 seconds)
Vcc+0.3 V to
Vss-0.3 V
Electrical Characteristics Unless otherwise noted: Vee = 5.0 V± 5%, VBB - 5.0 V± 5%, GND = 0 V, TA = DoC to
70°C; typical characteristics specified at Vee = 5.0 V, VBB = -5.0 V, TA = 25°C; all
signals are referenced to GND.
Symbol
Unit
Condition
Characteristic
Operating Current
ICCO
Power-Down Current
0.3
1.5
mA
IBBO
Power-Down Current
0.03
0.3
mA
Icc1
Active Current
Power Amplifier Active, VPI = 0 V
4.3
7.0
mA
IBB1
Active Current
Power Amplifier Active, VPI = 0 V
4.3
7.0
mA
0.6
V
Digital Interface
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
Ox, IH
IlL
Input Low Current
GND ~ VIN
IIH
Input High Current
loz
Output Current in High
Impedance State
2.2
V
Ox, IL = 3.2 mA
TSx, IL = 3.2 mA,Open Drain
= -3.2
~
0.4
0.4
2.4
mA
V
V
V
-10
10
VIH ~ VIN ~ Vcc
-10
10
J.LA
Ox, GND~Vo~Vcc
-10
10
JlA
V, VFxl+ or VFxl-
-200
200
+ 2.5 V, VFxl+ or VFxl-
10
VIL, All Digital Inputs
J.LA
Analog Interface With Transmit Input Amplifier
V~V~+2.5
IIXA
Input Leakage Current
-2.5
RIXA
Input Resistance
-2.5 V ~ V
RoXA
Output Resistance
Closed Loop, Unity Gain
RLXA
Load Resistance
GSx
CLXA
Load Capacitance
GSx
~
nA
MSl
1.0
3.0
10
Sl
kSl
50
pF
VoXA
Output Dynamic Range
GSx, RL ;;;'10 kSl
±2.8
V
AvXA
Voltage Gain
VFxl+ to GSx
5000
VIV
1.0
2.0
MHz
FuXA
Unity Gain Bandwidth
VosXA
Offset Voltage
-20
20
mV
XCMXA
Common-Mode Voltage
-2.5
2.5
V
CMRRXA
Common-Mode Rejection
Ratio
60
11-80
dB
F30S64/F30S67
Electrical Characteristics (Cont.) Unless otherwise noted: Vee = 5.0 V± 5%, VBB - 5.0 V± 5%, GND = 0 V,
TA = DoC to 70°C; typical characteristics specified at Vee = 5.0 V, VBB = -5.0 V,
T A = 25°C; all signals are referenced to GND.
Symbol
PSRRXA
Characteristic
Condition
Power Supply Rejection
Ratio
Min
Typ
Max
60
Unit
dB
Analog Interface With Receive Amplifier Output
RoRF
Output Resistance
Pin VFRO
RLRF
Load Resistance
VFRO= ±2.5 V
CLRF
Load Capacitance
VFRO to GND
VOSRO
Output DC Offset Voltage
VFRO to GND
1.0
3.0
10
n
kn
500
pF
-200
200
mV
-100
100
nA
Analog Interface With Power Amplifiers
IPI
Input Leakage Current
-1.0 V ~ VPI
~
1.0 V
-1.0 V ~ VPI
~
1.0 V
RIPI
Input Resistance
VIOS
Input Offset Voltage
ROP
Output Resistance
10
Mn
-25
Inverting Unity-Gain at VPO+ or VPO-
Fe
Unity-Gain Bandwidth
Open Loop (VPO-)
CLP
Load Capacitance
RL>1500 n
RL =600 n
RL =300 n
GAp+
Gain, VPO- to VPO+
RL = 300 n VPO+ to GND
Level at VPO- = 1.77 Vrms
(+3 dBmO)
PSRRp
Power Supply Rejection of
Vee or Vss
25
1.0
n
kHz
400
100
500
1000
1 VPO+
or
VPO- to
GND
mV
-1.0
pF
pF
pF
V/V
VPO - Connected to VPI
o kHz-4 kHz
o kHz-50 kHz
60
36
dB
dB
Timing Specifications
lItpM
Frequency of Master Clock
Depends on the CLKSEL Pin
tWMH
Width of Master Clock High
160
ns
tWML
Width of Master Clock Low
160
ns
tRM
Rise Time of Master Clock
50
ns
tFM
Fall Time of Master Clock
50
ns
tHMF
Holding Time from Master
Clock Low to Frame Sync
Long Frame Only
0
ns
tHOLD
Holding Time from Master
Clock High to Frame Sync
Short Frame Only
0
ns
tSFM
Set-Up Time from Frame
Sync to Master Clock Low
Long Frame Only
80
ns
11-81
1.536
1.544
2.048
MHz
MHz
MHz
F30S64/F30S67
Electrical Characteristics (Cont.) Unless otherwise noted: Vee = 5.0 V± 5%, Vss - 5.0 V± 5%, GND = 0 V,
TA = O°C to 70°C; typical characteristics specified at Vee = 5.0 V, Vss = -5.0 V,
TA = 25°C; all signals are referenced to GND.
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
tDMD
Delay Time from MCLK High
to Data Valid
Load
= 150
pF plus 2 LSTTL Loads
tXDP
Delay Time to TSx Low
Load
= 150
pF plus 2 LSTTL Loads
tDze
Delay Time from MCLK Low
to Data Output Disabled
tDZF
Delay Time to Valid Data
from FS or MCLK,
Whichever Comes Later
tSDM
Set-Up Time from DR Valid
to MCLK Low
50
ns
tHMD
Hold Time from MCLK Low
to DR Invalid
50
ns
tSF
Set-Up time from FS to
MCLK Low
Short Frame Sync Pulse (1 or 2 Clock
Periods Long) (Note 1)
50
ns
tHF
Hold Time from MCLK Low
to FS
Short Frame Sync Pulse (1 or 2 Clock
Periods Long) (Note 1)
100
ns
tHMFI
Hold Time from 3rd Period of
Master Clock Low to Frame
Sync FS
Long Frame Sync Pulse (from 3 to 8
Clock Periods Long)
100
ns
CL
=0
pF to 150 pF
Note
For short frame sync timing, FS must go high while the Master Clock is high.
11-82
0
180
ns
140
ns
50
165
ns
20
165
ns
Figure 2 Timing Diagram Short Frame Sync Timing
TSx
MCLK
FS
DR
Ox
Figure 3 Timing Diagram Long Frame Sync Timing
TSX
MCLK
ex,
FS
w
."
DR
Co)
o
en
I'
fJ)
Ox
\."
1
X
'i
),
"
"
"
''----L
~
......
."
Co)
o
en
fJ)
......
•
F30S64/F30S67
Transmission Characteristics Unless otherwise specified: TA = ooe to 70 oe, Vee = 5.0 V ± 5%, VBB = -5.0
V ± 5%, GND = 0 V, f = 1.02 kHz, VIN = 0 dBmO, transmit input amplifier
connected for unity-gain non-inverting.
Symbol
Characteristic
Unit
Condition
Amplitude Response
Absolute Levels
Nominal 0 dBmO Level is 4 dBm
(600 .12)
o dBmO
F30S64
F30S67
Max Overload Level
F30S64 (3.17 dBmO)
F30S67 (3.14 dBmO)
tMAX
GXA
Transmit Gain, Absolute
TA = 25°C, Vee = 5 V, Vss = -5 V
Input at GSx = 0 dBmO at 1020 Hz
GXR
Transmit Gain, Relative to
GXA
f = 16 Hz
f=50 Hz
f = 60 Hz
f=200Hz
f = 300 Hz - 3000 Hz
f= 3300 Hz
f= 3400 Hz
f = 4000 Hz
f = 4600 Hz and Up, Measure
Response from 0 Hz to 4000 Hz
ooe
GXAT
Absolute Transmit Gain
Variation with Temperature
TA =
GXAV
Absolute Transmit Gain
Variation with Supply Voltage
Vee = 5 V ± 5%, Vss = -5 V ± 5%
GXRL
Transmit Gain Variations with
Level
Sinusoidal Test Method
Reference Level = -10 dBmO
VFxl+ = -40 dBmO to +3 dBmO
VFxl+ = -50 dBmO to -40 dBmO
VFxl+ = -55 dBmO to -50 dBmO
Receive Gain, Absolute
TA = 25°C, Vee = 5 V, Vss = -5 V
Input = Digital Code Sequence for
o dBmO Signal at 1020 Hz
GRR
Receive Gain, Relative to
GRA
f=
f=
f=
f=
GRAT
Absolute Receive Gain
Variation with Temperature
TA = O°C to 70°C
GRAV
Absolute Receive Gain
Variation with Supply Voltage
Vee=5 V±5%, Vss=-5 V±5%
to 3000 Hz
Hz
Hz
Hz
11-84
Vrms
Vrms
2.501
2.492
VPK
VPK
0.15
dB
-40
-30
-26
-0.1
0.15
0.05
0
-14
-32
dB
dB
dB
dB
dB
dB
dB
dB
dB
±O.1
dB
±0.05
dB
-0.2
-0.4
-1.2
0.2
0.4
1.2
dB
dB
dB
-0.15
0.15
dB
-0.15
-0.35
-0.7
0.15
0.05
0
-14
dB
dB
dB
dB
±O.1
dB
±0.05
dB
-1.8
-0.15
-0.35
-0.7
to 70°C
GRA
0 Hz
3300
3400
4000
-0.15
1.2276
1.2276
F30S64/F30S67
Transmission Characteristics (Cant.) Unless otherwise specified: TA = O°C to 70°C, Vee = 5.0 V ± 5%,
Vss = -5.0 V ± 5%, GND = 0 V, f = 1.02 kHz, VIN = 0 dBmO, transmit input
amplifier connected for unity-gain non-inverting.
Symbol
GRRL
VRo
Characteristic
Receive Gain Variations with
Level
Receive Filter Output at
VFRO
Condition
Min
Typ
Max
Unit
Sinusoidal Test Method; Reference
Input PCM Code Corresponds to an
Ideally Encoded -10 dBmO Signal
PCM Level = -40 dBmO to + 3 dBmO
PCM Level = -50 dBmO to -40 dBmO
PCM Level = -55 dBmO to -50 dBmO
-0.2
-0.4
-1.2
0.2
0.4
1.2
dB
dB
dB
RL = 10 kQ
-2.5
2.5
V
Envelope Delay Distortion With Frequency
DXA
Transmit Delay, Absolute
f=1600 Hz
290
315
J.ls
DXR
Transmit Delay, Relative to
DXA
f = 500 Hz - 600 Hz
f=600 Hz-800 Hz
f = 800 Hz - 1000 Hz
f = 1000 Hz -1600 Hz
f = 1600 Hz - 2600 Hz
f = 2600 Hz - 2800 Hz
f = 2800 Hz - 3000 Hz
195
120
50
20
55
80
130
220
145
75
40
75
105
155
J.ls
J.lS
J.lS
J.lS
J.lS
J.lS
J.lS
DRA
Receive Delay, Absolute
f=1600 Hz
180
DRR
Receive Delay, Relative to
DRA
f = 500 Hz -1000 Hz
f
f
f
f
= 1000 Hz-1600 Hz
-40
-30
= 1600 Hz - 2600 Hz
= 2600 Hz - 2800 Hz
= 2800 Hz - 3000 Hz
200
J.lS
-25
-20
70
100
145
90
125
175
J.lS
J.lS
J.lS
J.lS
J.ls
Noise
Nxe
Transmit Noise, C Message
Weighted
F30S64 VFxl+ = 0 V
12
15
dBrnCO
Nxp
Transmit Noise, P Message
Weighted
F30S67 VFxl+ = 0 V
-74
-69
(Note 1)
dBmOp
NRe
Receive Noise, C Message
Weighted
F30S64 PCM Code Equals
Alternating Positive and Negative Zero
NRP
Receive Noise, P Message
Weighted
F30S67 PCM Code Equals
Positive Zero
NRS
Noise, Single Frequency
f = 0 kHz to 100 kHz, Loop Around
Measurement, VFxl+ = 0 Vrms
PPSRx
Positive Power Supply
Rejection, Transmit
VFxl+ = 0 Vrms,
Vee = 5.0 Vac + 100 mVrms
f = 0 kHz - 50 kHz
40
dBC
NPSRx
Negative Power Supply
Rejection, Transmit
VFxl+ = 0 Vrms,
VBB = -5.0 Vae + 100 mVrms
f = 0 kHz - 50 kHz
40
dBC
11-85
8.0
-82
11
dBrnCO
-79
dBmOp
-53
dBmO
F30S64/F30S67
Transmission Characteristics (Cont.) Unless otherwise specified: TA = O°C to 70°C, Vee = 5.0 V ± 5%,
Vss = -5.0 V ± 5%, GND = 0 V, f = 1.02 kHz, VIN = 0 dBmO, transmit input
amplifier connected for unity-gain non-inverting.
Symbol
PPSRR
NPSRR
SOS
Characteristic
Positive Power Supply
Rejection, Receive
Negative Power Supply
Rejection, Receive
Spurious Out-of-Band Signals
at the Channel Output
Condition
Min
Typ
Max
Unit
PCM Code Equals Positive Zero
Vee = 5.0 Voc + 100 mVrms
f=O Hz-4000 Hz
f=4 kHz-25 kHz
f=25 kHz-50 kHz
40
40
36
dBC
dB
dB
PCM Code Equals Positive Zero
VBB = -5.0 Voc + 100 mVrms
f=O Hz-4000 Hz
f=4 kHz-25 kHz
f=25 kHz-50 kHz
40
40
36
dBC
dB
dB
Loop Around Measurement, 0 dBmO,
300 Hz - 3400 Hz Input Applied to
VFxl+, Measure Individual Image
Signals at VFRO
4600 Hz - 7600 Hz
7600 Hz - 8400 Hz
8400 Hz - 100,000 Hz
-32
-40
-32
dB
dB
dB
Distortion
STDx
STDR
Signal to Total Distortion
Transmit or Receive
Half-Channel
SFDx
Single Frequency Distortion,
Transmit
-46
dB
SFDR
Single Frequency Distortion,
Receive
-46
dB
IMD
Intermodulation Distortion
Loop Around Measurement,
VFxl+ = -4 dBmO to -21 dBmO,
Two Frequencies in the Range
300 Hz - 3400 Hz
-41
dB
CTx.R
Transmit to Receive
Crosstalk, 0 dBmO Transmit
Level
f = 300 Hz-3400 Hz
DR = Steady PCM Code
-90
-75
dB
CTR.X
Receive to Transmit
Crosstalk, 0 dBmO Receive
Level
f = 300 Hz - 3400 Hz, VFxl = 0 V
-90
-70
(Note 2)
dB
Sinusoidal Test Method
Level = 3.0 dBmO
= 0 dBmO to -30 dBmO
= -40 dBmO XMT
RCV
= -55 dBmO XMT
RCV
33
36
29
30
14
15
dBC
dBC
dBC
dBC
dBC
dBC
Crosstalk
11-86
F30S64/F30S67
Transmission Characteristics (Cont.) Unless otherwise specified: TA = O°C to 70°C, Vee = 5.0 V ± 5%,
Vss = -5.0 V ± 5%, GND = 0 V, f = 1.02 kHz, VIN = 0 dBmO, transmit input
amplifier connected for unity-gain non-inverting.
Symbol
Characteristic
Condition
Unit
Power Amplifiers
VOL
S/Dp
Maximum 0 dBmO Level for
Better than ± 0.1 dB Linearity
Over the Range -10 dBmO
to +3 dBmO
Balanced Load, RL Connected
Between VPO+ and VPORL = 600 n
RL = 1200 n
RL = 30 kn
3.3
3.5
4.0
Vrms
Vrms
Vrms
Signal/Distortion
RL = 600 n, 0 dBmO
50
dB
Notes
1. Measured by extrapolation from the distortion test result.
2. eT R.X is measured with a -40 dBmO activating signal applied at VFxl+.
Encoding Format At Ox
F30S64
J.L-Law
VIN (at GSx) = + Full-Scale
VIN (at GSx) = 0 V
VIN (at GSx) = - Full-Scale
[
F30S67
A-Law
(Includes Even Bit Inversion)
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
Applications Information
All ground connections to each device should meet at a
common pOint as close as possible to the GND pin. This
minimizes the interaction of ground return currents flowing
through a common bus impedance. 0.1 J.LF supply decoupiing capacitors should be connected from this common
ground point to Vee and VBB.
Power Supplies
While the pins of the F30S60 family are well protected
against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is
connected to the device before any other connections are
made In applications where the printed circuit board may
be plugged into a "hot" socket with power and clocks
already present, an extra long ground pin in the connector
should be used.
For best performance, the ground point of each CODEC/
FILTER on a card should be connected to a common
card ground in star formation, rather than via a ground
bus. This common ground point should be decoupled to
Vee and VBB with 10 J.LF capacitors.
11-87
•
F30S64/F30S67
Figure 4 Typical Synchronous Application
300
R3
R1
R4
ANALOG
LOOPBACK
TSx
CLKSEL
FS
DR
Dx
MCLK
PDN
Note 1: Transmit gain
= 20
Note 2: Receive gain
= 20 x
x log (R1;2R2 ),(R1 +R2)?: 10k!}
log (2 ~4R3 ) • R42! 10k!}
11-88
F3054/F3057
Monolithic Serial Interface
CMOS CODEC/FILTER
FAIRCHILD
A Schlumberger Company
Advanced Signal Processing Division
Description
Connection Diagram
(Top View)
The F3054, F3057 family consists of /l-Iaw and A-law
monolithic PCM CODEC/FILTERS utilizing the AID and
DI A conversion architecture shown in Figure 1, and a serial PCM interface. The devices are fabricated using
Fairchild's advanced Double-Poly Silicon Gate CMOS process.
16
The transmit portion of each device consists of an input
gain adjust amplifier, an active RC pre-filter, a switchedcapacitor band-pass filter, and a compressing encoder with
auto-zero circuitry. The active RC pre-filter eliminates very
high frequency noise, and the switched-capacitor filter rejects signals below 200 Hz and above 3400 Hz. The compressing encoder samples the filtered signal and encodes
it in the compressed /l-Iaw or A-law PCM format. The receive portion of each device consists of an expanding decoder, which reconstructs the analog signal from the
compressed /l-Iaw or A-law code, a low-pass filter which
corrects for the sin xIx response of the decoder output
and rejects signals above 3400 Hz and is followed by a
single-ended power amplifier capable of driving low impedance loads. The devices require two 1.536 MHz,
1.544 MHz or 2.048 MHz transmit and receive master
clocks, which may be asynchronous, transmit and receive
bit clocks, which may vary from 64 kHz to 2.048 MHz,
and transmit and receive frame sync pulses. The timing of
the frame sync pulses and PCM data is compatible with
both industry standard formats.
v••
VFxl+
GND
VFx l -
VFRO
GSx
Vee
TSx
FSR
FSx
DR
Ox
BCLKRI
BLCKx
CLKSEL
MCLKRi
MCLKx
PDN
Order Information
Device Code
F3054DC
F3057DC
• Complete Codec and Filtering System Including:
• Transmit High-Pass and Low-Pass Filtering
• Receive Low-Pass Filter With Sin XIX Correction
• Active RC Noise Filter
• /l-Law or A-Law Compatible Coder and Decoder
• Internal Precision Voltage Reference
• Serial 1/0 Interface
• Internal Auto-Zero Circuitry
• /l-Law, 16 Pin-F3054
• A-Law, 16 Pin - F3057
• Meets or Exceeds All 03/04 and CCITT
Specifications
• ± 5.0 V Operation
• Low Operating Power - Typically 60 mW
• Power-Down Standby Mode - Typically 3.0 mW
• Automatic Power-Down
• TTL or CMOS Compatible Digital Interfaces
• Maximizes Line Interface Card Circuit Density
11-89
Package Code
FW
FW
Package Description
Ceramic DIP
Ceramic DIP
F3054/F3057
Figure 1 Block Diagram
RF
GS,
r------------------------------------------------------------------
II
I
I
I
I
I
I
I
~~~~'-~-+l--;
RC
I
AC1lVE
FILla!
VFx l +
XMT
VOLTAGE
REGISTER
REFERENCE
DE
TIMING AND CONTROL
L-----~i:--~i:---}------------~~~~~~~~----------~---i-----1--------Vee
Vaa
GND
MCLKx MCLKA' BCLKx BCLKA'
PDN
CLKSEL
11-90
FSA
FSx
Ox
F3054/F3057
Pin Description
Pin No.
Function
Name
1
2
3
4
5
6
7
8
MClKR/PDN
9
MClKx
10
BClKx
11
12
Ox
FSX
13
14
15
16
TSX
GSX
VFxlVFxl+
Negative power supply pin. VBB = -5 V ± 5%.
Ground. All signals are referenced to this pin.
Analog output of the receive filter.
Positive power supply pin. Vee = +5 V ± 5%.
Receive frame sync pulse which enables BClKR to shift PCM data into DR. FSR is
an 8 kHz pulse train. See Figures 2 and 3 for timing details.
Receive data input. PCM data is shifted into OR following the FSR leading edge.
The bit clock which shifts data into DR after FSR leading edge. May vary from
64 kHz to 2.048 MHz, but must be synchronous with MCKlR. Alternatively, may be
a logic input which selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master
clock in synchronous mode and BClKx is used for both transmit and receive
directions (see Table 1).
Receive master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. When
MClKR is connected continuously low, MClKx is selected for all internal timing.
When MClKR is connected continuously high, the device is powered down.
Transmit master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MClKR.
The bit clock which shifts out the PCM data on Dx. May vary from 64 kHz to
2.048 MHz, but must be synchronous with MClKx.
The 3-state PCM data output which is enabled by FSx.
Transmit frame sync pulse input which enables BClKx to shift out the PCM data
on Ox. FSx is an 8 kHz pulse train; see Figures 2 and 3 for timing details.
Open drain output which pulses low during the encoder time slot.
Analog output of the transmit input amplifier. Used to externally set gain.
Inverting input of the transmit input amplifier.
Non-inverting input of the transmit input amplifier.
Functional Description
Synchronous Operation
For synchronous operation, the same master clock and bit
clock should be used for both the transmit and receive
directions. In this mode, a clock must be applied to
MClKx and the MClKR/PDN pin can be used as a power-down control. A low level on MClKR/PON powers up
the device and a high level powers down the device. In
either case, MClKx will be selected as the master clock
for both the transmit and receive circuits. A bit clock must
also be applied to BClKx and the BClKR/ClKSEl can be
used to select the proper internal divider for a master
clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For
1.544 MHz operation, the device automatically compensates for the 193rd clock pulse each frame.
Power-Up
When power is first applied, power-on reset circuitry initializes the device and places it into the power-down mode.
All non-essential circuits are deactivated and the Dx and
VFRO outputs are put in high impedance states. To power-up the device, a logical low level or clock must be applied to the MClKR/PDN pin and FSx and/or FSR pulses
must be present. Thus, two power-down control modes are
available. The first is to pull the MClKR/PON pin high; the
second is to hold both FSx and FSR inputs continuously
low - the device will power-down approximately 2 ms after
the last FSx or FSR pulse. Power-up will occur on the first
FSx or FSR pulse. The 3-state PCM data output, Ox, will
remain in the high impedance state until the second FSx
pulse.
11-91
•
F3054/F3057
Functional Description (Cont.)
With a fixed level on the BClKR/ClKSEl pin, BClKx will
be selected as the bit clock for both the transmit and
receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of
BClKR/ClKSEL. In this synchronous mode, the bit clock,
BClKx, may be from 64 kHz to 2.048 MHz, but must be
synchronous with MClKx.
Each FSx pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled Ox output on the positive edge of BClKx. After 8
bit clock periods, the 3-state Ox output is returned to a
high impedance state. With an FSR pulse, PCM data is
latched via the DR input on the negative edge of BClKx
(or BClKR if running). FSx and FSR must be synchronous
with MClKx/R.
Table 1 Selection of Master Clock Frequencies
Master Clock
Frequency Selected
BCLKR/CLKSEL
F3057
Clocked
2.048 MHz
0
1.536 MHz or
1.544 MHz
2.048 MHz
1 (or Open
Circuit)
F3054
1.536 MHz or
1.544 MHz
2.048 MHz
1.536 MHz or
1.544 MHz
Asynchronous Operation
For asynchronous operation, separate transmit and receive
clocks may be applied. MClKx and MClKR must be
2.048 MHz for the F3057, and 1.536 MHz or 1.544 MHz
for the F3054 and need not be synchronous. For best
transmission performance, however, MClKR should be synchronous with MClKx, which is easily achieved by applying only static logic levels to the MClKR/PON pin. This
will automatically connect MClKx to all internal MClKR
functions (see Pin Description). For 1.544 MHz operation,
the device automatically compensates for the 193rd clock
pulse each frame. FSx starts each encoding cycle and
must be synchronous with MClKx and BClKx. FSR starts
each decoding cycle and must be synchronous with
BClKR, which must be a clock. The logic levels shown in
Table 1 are not valid for asynchronous operation. BClKx
and BClKR may operate from 64 kHz to 2.048 MHz.
Short Frame Sync Operation
The device can utilize either a short frame sync pulse or
a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, both
frame sync pulses, FSx and FSR, must be one bit clock
period long, with timing relationships specified in Figure 2.
With FSx high during a falling edge of BClKx, the next
riSing edge of BClKx enables the Ox 3-state output buffer,
which will output the sign bit. The following seven rising
edges clock out the remaining seven bits, and the next
falling edge disables the Ox output. With FSR high during
a falling edge of BClKR (BClKx in synchronous mode),
the next falling edge of BClKR latches in the sign bit.
The following seven falling edges latch in the seven remaining bits. Both devices may utilize the short frame
sync pulse in synchronous or asynchronous operating
mode.
Long Frame Sync Operation
To use the long frame sync mode, both the frame sync
pulses, FSx and FSR, must be three or more bit clock
periods long, with timing relationships specified in Figure 3.
Based on the transmit frame sync, FSx, the device will
sense whether short or long frame sync pulses are being
used. For 64 kHz operation, the frame sync pulse must be
kept low for a minimum of 160 ns. The Ox 3-state output
buffer is enabled with the rising edge of FSx or the rising
edge of BClKx, whichever comes later, and the first bit
clocked out is the sign bit. The following seven BClKx
rising edges clock out the remaining seven bits. The Ox
output is disabled by the falling BClKx edge following the
eighth rising edge, or by FSx going low, whichever comes
later. A rising edge on the receive frame sync pulse, FSR,
will cause the PCM data at DR to be latched in on the
next eight falling edge of BClKR (BClKx in synchronous
mode). Both devices may utilize the long frame sync pulse
in synchronous or asynchronous mode.
Transmit Section
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
see Figure 4. The low noise and wide bandwidth allow
gains in excess of 20 dB across the audio passband to
be realized. The op amp drives a unity-gain filter consisting of an RC active pre-filter, followed by an eighth order
switched-capacitor bandpass filter clocked at 128 kHz. The
output of this filter directly drives the encoder sample-andhold circuit. The AID is of compressing type according to
/-L-Iaw (F3054) or A-law (F3057) coding conventions. A precision voltage reference is trimmed in manufacturing to
provide an input overload (tMAX) of nominally 2.5 V peak
(see table of Transmission Characteristics). The FSx frame
sync pulse controls the sampling of the filter output, and
then the successive-approximation encoding cycle begins.
The 8-bit code is then loaded into a buffer and shifted out
through Ox at the next FSx pulse. The total encoding delay will be approximately 165 /-LS (due to the transmit filter)
plus 125 /-LS (due to encoding delay), which total 290 /-Ls.
11-92
F3054/F3057
Any offset voltage due to the filters or comparator is cancelled by sign bit integration.
Receive Section
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 128 kHz. The decoder is A-law (F3057) or
M-Iaw (F3054) and the 5th order low pass filter corrects
for the sin x/x attenuation due to the 8 kHz sample/hold.
The filter is then followed by a power amplifier capable of
driving a 600 il load to a level of 7.2 dBm. The receive
section is unity-gain. Upon the occurrence of FSA. the
data at the DA input is clocked in on the falling edge of
the next eight BClKA (BClKx> periods. At the end of the
decoder time slot. the decoding cycle begins. and 10 MS
later the decoder DAC output is updated. The total decoder delay is -10 MS (decoder update) plus 110 MS (filter
delay) plus 62.5 MS (Y2 frame). which gives approximately
180 MS.
Absolute Maximum Ratings
Vee to GND
Vss to GND
Voltage at any Analog Input
or Output
Voltage at any Digital Input
or Output
7.0 V
-7.0 V
Vee + 0.3 V to
Vss-0.3 V
Vcc+0.3 V to
GND-0.3 V
-25°C to +125°C
-65°C to + 150°C
Operating Temperature Range
Storage Temperature Range
lead Temperature
(Soldering. 10 seconds)
300°C
Electrical Characteristics Unless otherwise noted: Vee = 5.0 V ± 5%. Vaa - 5.0 V ± 5%. GND = 0 V. TA = O°C
to 70°C; typical characteristics specified at Vee = 5.0 V. Vaa = -5.0 V. TA = 25°C; all
signals are referenced to GND.
Symbol
Characteristic
Conditions
Operating Current
leeO
Power-Down Current
0.5
1.5
rnA
IssO
Power-Down Current
0.05
0.3
rnA
lee1
Active Current
6.0
9.0
rnA
Iss1
Active Current
6.0
9.0
rnA
0.6
V
Digital Interface
VIL
Input low Voltage
VIH
Input High Voltage
VOL
Output low Voltage
Ox. IL = 3.2 rnA
TSx. IL = 3.2 rnA. Open Drain
VOH
Output High Voltage
Ox. IH = -3.2 rnA
2.2
V
0.4
0.4
2.4
V
V
V
IlL
Input low Current
GND ..;; VIN ..;; VIL. All Digital Inputs
-10
10
IIH
Input High Current
VIH ";;VIN ";;Vee
-10
10
loz
Output Current in High
Impedance State
Ox. GND";; Vo";; Vee
-10
10
MA
MA
MA
200
nA
Analog Interface With Transmit Input Amplifier
IIXA
Input leakage Current
-2.5 V";;V";;+2.5 V.
VFxl + or VFxl-
-200
RIXA
Input Resistance
-2.5 V";;V";;+2.5 V.
VFxl + or VFxl-
10
RoXA
Output Resistance
Closed loop. Unity Gain
11-93
Mil
1.0
3.0
il
F3054/F3057
Electrical Characteristics (Cont.) Unless otherwise noted: Vee = 5.0 V ± 5%, Vss - 5.0 V ± 5%, GND = 0 V,
TA = DoC to 70°C; typical characteristics specified at Vee = 5.0 V, Vss = -5.0 V,
T A = 25°C; all signals are referenced to GND.
Symbol
Characteristic
Conditions
Min
Typ
Max
RLXA
load Resistance
GSx
CLXA
load Capacitance
GSx
VoXA
Output Dynamic Range
GSx, RL;;" 10 kn
±2.8
AvXA
Voltage Gain
VFxl + to GS x
5000
FuXA
Unity Gain Bandwidth
VosXA
Offset Voltage
-20
20
VCMXA
Common-Mode Voltage
-2.5
2.5.
10
kn
50
1.0
Unit
pF
V
VIV
2.0
MHz
mV
V
CMRRXA Common-Mode Rejection Ratio
60
dB
PSRRXA
60
dB
Power Supply Rejection Ratio
Analog Interface With Receive Amplifier Output
RORF
Output Resistance
Pin VFRO
VFRO= ±2.5 V
RLRF
load Resistance
CLRF
load Capacitance
VOSRO
Output DC Offset Voltage
1.0
3.0
n
500
pF
200
mV
600
n
-200
Timing Specifications
Frequency of Master Clocks
Depends on the Device Used and
the BClKR/ClKSEl Pin
MClKx and MClKR
tWMH
Width of Master Clock High
MClKx and MClKR
160
ns
tWML
Width of Master Clock low
MClKx and MClKR
160
ns
tRM
Rise Time of Master Clock
MClKx and MClKR
50
ns
tFM
Fall Time of Master Clock
MClKx and MClKR
50
ns
tSBFM
Set-Up Time from BClKx High
(and FSx in long Frame Sync
Mode) to MClKx Falling Edge
First Bit Clock after the leading
Edge of FSx
1/tpM
1.536
1.544
2.048
MHz
MHz
MHz
100
ns
tpB
Period of Bit Clock
tWBH
Width of Bit Clock High
tWBL
Width of Bit Clock low
tRB
Rise Time of Bit Clock
tFB
Fall Time of Bit Clock
tHBF
Holding Time from Bit Clock
low to Frame Sync
long Frame Only
0
ns
tHOLD
Holding Time from Bit Clock
High to Frame Sync
Short Frame Only
0
ns
485
= 2.2 V
= 0.6 V
tps = 488 ns
tpB = 488 ns
VIH
160
VIL
160
11-94
488
15,725
ns
ns
ns
50
ns
50
ns
F3054/F3057
± 5%, Vaa - 5.0 V ± 5%, GND = 0 V,
T A = O°C to 70°C; typical characteristics specified at Vee = 5.0 V, Vaa = -5.0 V,
T A = 25°C; all signals are referenced to GND.
Electrical Characteristics (Cont.) Unless otherwise noted: Vee = 5.0 V
Symbol
Characteristic
Conditions
Min
Typ
Max
80
Unit
tSFB
Set-Up Time from Frame Sync
to Bit Clock Low
Long Frame Only
tDBD
Delay Time from BCLKx High
to Data Valid
Load = 150 pF plus 2 LSTTL
Loads
tXDP
Delay Time to TSx Low
Load = 150 pF plus 2 LSTTL
Loads
tDZC
Delay Time from BCLKx Low to
Data Output Disabled
tDZF
Delay Time to Valid Data from
FSx or BCLKx, Whichever
Comes Later
tSDB
Set-Up Time from DR Valid to
BCLKR/X Low
50
ns
tHBD
Hold Time from BCLKR/X Low to
DR Invalid
50
ns
tSF
Set-Up time from FSX/R to
BCLKx/R Low
Short Frame Sync Pulse (1 or 2
Bit Clock Periods Long)(Note 1)
50
ns
tHF
Hold Time from BCLK)4!R Low
to FSX/R
Short Frame Sync Pulse (1 or 2
Bit Clock Periods Long)(Note 1)
100
ns
tHBFl
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
(FSx or FSR)
Long Frame Sync Pulse (from 3
to 8 Clock Periods Long)
100
ns
tWFL
Minimum Width of the Frame
Sync Pulse (Low Level)
64K Bitls Operating Mode
160
ns
CL = 0 pF to 150 pF
Note
1. For short frame sync timing, FSx and FSR must go high while their respective bH clocks are high.
11-95
ns
180
ns
140
ns
50
165
ns
20
165
ns
0
F3054/F3057
Figure 2 Timing Diagram Short Frame Sync Timing
BLCKX
FSx
-------«~~X\__
r---:~.
_IX'__........_ ....X'__-'X,....'-==:X'-__
~
Figure 3 Timing Diagram Long Frame Sync Timing
--IICLKx
FSx
IICLKa
~
-
11-96
F3054/F3057
Transmission Characteristics Unless otherwise specified: TA = O·G to 70·G, Vee = 5.0 V ± 5%,
Vee = -5.0 V ± 5%, GND = 0 V, f = 1.02 kHz, VIN = 0 dBmO, transmit input
amplifier connected for unity-gain non-inverting.
Symbol
Characteristic
Unit
Conditions
Amplitude Response
Absolute Levels
Nominal 0 dBmO Level is 4.0 dBm
(600 il)
o dBmO
F3054
F3057
Max Overload Level
F3054 (3.17 dBmO)
F3057 (3.14 dBmO)
tMAX
GXA
Transmit Gain, Absolute
TA = 25·C, Vce = 5 V, VBB = -5 V
Input at GSx = o dBmO at 1020 Hz
GXR
Transmit Gain,
Relative to GXA
1 = 16 Hz
1= 50 Hz
1 = 60 Hz
1 = 200 Hz
1 = 300 Hz - 3000 Hz
1 = 3300 Hz
1 = 3400 Hz
1= 4000 Hz
1 = 4600 Hz and Up, Measure
Response Irom 0 Hz to 4000 Hz
GXAT
Absolute Transmit Gain
Variation with Temperature
TA = O°C to 70·C
GXAV
Absolute Transmit Gain
Variation with Supply
Voltage
Vee = 5 V ± 5%, VBB = -5 V ± 5%
GXRL
Transmit Gain Variations
with Level
Sinusoidal Test Method
Relerence Level = -10 dBmO
VFxl + = -40 dBmO to +3 dBmO
VFxl + = -50 dBmO to -40 dBmO
VFxl + = -55 dBmO to -50 dBmO
1.2276
1.2276
Vrms
Vrms
2.501
2.492
VPK
VPK
-0.15
-1.8
-0.15
-0.35
-0.7
±0.1
0.15
dB
-40
-30
-26
-0.1
0.15
0.05
0
-14
-32
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
±0.05
dB
-0.2
-0.4
-1.2
0.2
0.4
1.2
dB
dB
dB
GRA
Receive Gain, Absolute
TA = 25·C, Vee = 5 V, VBB = -5 V
Input = Digital Code Sequence for
o dBmO Signal at 1020 Hz
-0.15
0.15
dB
GRR
Receive Gain, Relative to
GRA
1=0 Hz
1= 3300
1= 3400
1= 4000
-0.15
-0.35
-0.7
0.15
0.05
0
-14
dB
dB
dB
dB
GRAT
Absolute Receive Gain
Variation with Temperature
TA = O·C to 70·C
±0.1
dB
GRAV
Absolute Receive Gain
Variation with Supply
Voltage
Vee = 5 V ± 5%, VBB = -5 V ± 5%
±0.05
dB
to 3000 Hz
Hz
Hz
Hz
11-97
•
F3054/F3057
Transmission Characteristics (Cant.) Unless otherwise specified: TA = O°C to 70°C, Vee = 5.0 V ± 5%,
VBB = -5.0 V ± 5%, GND = 0 V, f = 1.02 kHz, VIN = 0 dBmO, transmit input
amplifier connected for unity-gain non-inverting.
Symbol
GRRL
VRO
Characteristic
Receive Gain Variations
with Level
Receive Output Drive
Level
Conditions
Min
Typ
Max
Unit
Sinusoidal Test Method; Relerence
Input PCM Code Corresponds to an
Ideally Encoded -10 dBmO Signal
PCM Level = -40 dBmO to + 3 dBmO
PCM Level = -50 dBmO to -40 dBmO
PCM Level = -55 dBmO to -50 dBmO
-0.2
-0.4
-1.2
0.2
0.4
1.2
dB
dB
dB
RL = 600 Q
-2.5
2.5
V
Envelope Delay Distortion With Frequency
DXA
Transmit Delay, Absolute
1 = 1600 Hz
290
315
IlS
DXR
Transmit Delay,
Relative to DXA
1=500 Hz-600 Hz
1 = 600 Hz - 800 Hz
1 = 800 Hz - 1000 Hz
1 = 1000 Hz -1600 Hz
1 = 1600 Hz - 2600 Hz
1 = 2600 Hz - 2800 Hz
1 = 2800 Hz - 3000 Hz
195
120
50
20
55
80
130
220
145
75
40
75
105
155
IlS
IlS
IlS
IlS
IlS
IlS
IlS
DRA
Receive Delay, Absolute
1= 1600 Hz
180
DRR
Receive Delay,
Relative to DRA
1=
1=
1=
1=
1=
500 Hz - 1000 Hz
1000 Hz-1600 Hz
1600 Hz - 2600 Hz
2600 Hz - 2800 Hz
2800 Hz - 3000 Hz
-40
-30
200
IlS
-25
-20
70
100
145
90
125
175
IlS
IlS
IlS
IlS
IlS
Noise
Nxe
Transmit Noise,
C Message Weighted
F3054 VFxl + = 0 V
12
15
dBrnCO
Nxp
Transmit Noise,
P Message Weighted
F3057 VFxl + = 0 V
-74
-69
(Note 1)
dBmOp
NRe
Receive Noise,
C Message Weighted
F3054 PCM Code
Equals Alternating Positive and
Negative Zero
8.0
11
dBrnCO
NRP
Receive Noise,
P Message Weighted
F3057 PCM Code Equals
Positive Zero
-82
-79
dBmOp
NRS
Noise, Single Frequency
1 = 0 kHz to 100 kHz, Loop Around
Measurement, VFxl + = 0 Vrms
-53
dBmO
PPSRx
Positive Power Supply
Rejection, Transmit
VFxl + = 0 Vrms
Vec = 5.0 Voe + 100 mVrms
1 = 0 kHz - 50 kHz
40
dBC
NPSRx
Negative Power Supply
Rejection, Transmit
VFxl + = 0 Vms,
VBB = -5.0 Voe + 100 mVrms
1 = 0 kHz - 50 kHz
40
dBC
11-98
F3054/F3057
Transmission Characteristics (Cont.) Unless otherwise specified: TA = O°C to 70°C, Vee = 5.0 V ± 5%,
VBB = -5.0 V ± 5%, GND = 0 V, f = 1.02 kHz, VIN = 0 dBmO, transmit input
amplifier connected for unity-gain non-inverting.
Symbol
PPSRR
NPSRR
SOS
Characteristic
Positive Power Supply
Rejection, Receive
Negative Power Supply
Rejection, Receive
Spurious Out-of-Band
Signals at the Channel
Output
Conditions
Min
Typ
Max
Unit
PCM Code Equals Positive Zero
Vcc = 5.0 Voc + 100 mVrms
f = 0 Hz - 4000 Hz
f = 4 kHz - 25 kHz
f = 25 kHz - 50 kHz
40
40
36
dBC
dB
dB
PCM Code Equals Positive Zero
VBB = -5.0 Voc + 100 mVrms
f = 0 Hz - 4000 Hz
f=4 kHz-25 kHz
f = 25 kHz - 50 kHz
40
40
36
dBC
dB
dB
Loop Around Measurement, 0 dBmO,
300 Hz - 3400 Hz Input Applied to
VFxl +, Measure Individual Image
Signals at VFRO
4600 Hz - 7600 Hz
7600 Hz - 8400 Hz
8400 Hz - 100,000 Hz
-32
-40
-32
dB
dB
dB
Distortion
STDx
STDR
Signal to Total Distortion
Transmit or Receive
Half-Channel
Sinusoidal Test Method Level
=3.0 dBmO
= 0 dBmO to -30 dBmO
= -40 dBmO XMT
RCV
= -55 dBmO XMT
RCV
SFDx
Single Frequency
Distortion, Transmit
-46
dB
SFDR
Single Frequency
Distortion, Receive
-46
dB
IMD
Intermodulation Distortion
Loop Around Measurement,
VFxl + = -4 dBmO to -21 dBmO,
Two Frequencies in the Range
300 Hz - 3400 Hz
-41
dB
Transmit to Receive
Crosstalk, 0 dBmO
Transmit Level
f = 300 Hz - 3400 Hz
DR = Steady PCM Code
-90
-75
dB
Receive to Transmit
Crosstalk, 0 dBmO
Receive Level
f = 300 Hz - 3400 Hz, VFxl = 0 V
-90
-70
(Note 2)
dB
33
36
29
30
14
15
dBC
dBC
dBC
dBC
dBC
dBC
Crosstalk
CTX_R
CTR_X
Notes
1. Measured by extrapolation from the distortion test result.
2. CT A.X is measured with a -40 dBmO activating signal applied at VFxl + .
11-99
F3054/F3057
Encoding Format At Ox
F3054
Il-Law
F3057
A-Law
(Includes Even Bit Inversion)
VIN (at GSx) = + Full-Scale
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
VIN (at GSx) = 0 V
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
VIN (at GSx) = -Full-Scale
[
Applications Information
T -Pad Attenuator
I
I
I
z1i
R2
I
I
I
iZ2"
l_____ _ ___ J
R1=Z1 ("'+')-2YZ1.Z2
N2_1
R2=2V Z1 ,Z2 (N~')
All ground connections to each device should meet at a
common pOint as close as possible to the GND pin. This
minimizes the interaction of ground return currents flowing
through a common bus impedance. 0.1 IlF supply decoupiing capacitors should be connected from this common
ground point to Vee and Vss.
For best performance, the ground point of each CODECI
FILTER on a card should be connected to a common
card ground in star formation, rather than via a ground
bus. This common ground point should be decoupled to
Vee and Vss with 10 IlF capacitors.
10
>--'11300"'!!Ir-...!.I_-..J-v;1",-_-...-_-"-,,,;,,-_-+1_-,1 :V2
Power Supplies
While the pins of the F3054 family are well protected
against electrical misuse, it is recommended that the standard CMOS practice be followed, ensuring that ground is
connected to the device before any other connections are
made. In applications where the printed circuit board may
be plugged into a "hot" socket with power and clocks
already present, an extra long ground pin in the connector
should be used.
Where N
soon
I
I
I
(~)
~-1
V
=
POWER IN
POWER OUT
and
s=~
Also:' Z= yZSC'
Zoe
=Impedance with shon circuit termination
and Zoe =Impedance with open circuit termination
Where Zsc
1T-Pad Attenuator
,-----------,
R3
I
300!! I
110
1:V2
W
">--'lNY-Z1-+!--R4 Ir-- 10Kn
11-101
IlAV22
1200 bps
Full Duplex Modem
I=AIRCHILO
A Schlumberger Company
Advance Information May 1986
Advanced Signal Processing Division
Description
Connection Diagram
28-Lead Dip
(Top View)
The pAV22 1200 bps full duplex modes I.C. is fabricated
in Fairchild's advanced Double-Poly Silicon-Gate CMOS
process. The monolithic I.C. performs all the signal processing functions required of a CCITT V.22, alternative 8
compatible modem. Handshaking protocols, dialing control
and mode control functions can be handled by a general
purpose, single chip J.lC. The pAV22, J.lC and several components to perform the telephone line interface and control provide a high performance, cost effective and
ultra-low power solution for V.22-compatible modem designs.
SLIM
The modem chip performs the modulation, demodulation,
filtering and certain control and self-test functions required
for a CCITT V.22-compatible modem, as well as additional
enhancements. 80th 550 Hz and 1800 Hz guard tones
and notch filters and DTMF tone generator are on-chip.
Switched-capacitor filters provide channel isolation, spectral
shaping and fixed compromise equalization. A novel
switched-capacitor modulator and a digital coherent demodulator provide 1200 DPSK operation.
Voo
LIM
27
Vss
RXIN
26
AGNO
DOT
25
TXO
ETC
24
alA.
SYNC
23
TXSQ
EDET
22
SCT
HS
21
MOD1
SCRM
20
MOD2
TXD
10
19
TEST
XTL2
11
18
DGND
XTL1
17
HSK2
SCR
16
HSK1
RXD
15
RLST
The receive filter and energy detector may be configured
for call progress tone detection (dialtone, busy, ringback,
voice) providing the front end for a smart dialer.
Order Information
• Functions as a CCITT V.22-compatible modem
• Interfaces to Single Chip J.lC Which Handles
Handshaking Protocols and Mode Control Functions
• DTMF Tone Generation and Call Progress Tone
Detection for Smart Dialer Applications
• 1300 Hz Calling Tone Generator On Chip
• Pin and function compatible with the J.lA212A
• On Chip Oscillator Uses 3.6864 MHz Crystal
• Few External Components Required
• Operates from +5 and -5 Volt Supplies
• Low Operating Power: 35 mW Typical
• 550 Hz and 1200 Hz guard tones and notch filters
are on-chip
Device Code
pAV22DC
pAV22PC
J.lAV22QC
*Consult Factory
Absolute Maximum Ratings
Voo to DGND or AGND
Vss to DGND or AGND
Voltage at any Input
Voltage at any Digital Output
Voltage at any Analog Output
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10
seconds)
7.0 V
-7.0 V
Voo + 0.3 to
Vss -0.3 V
Voo + 0.3 V to
DGND -0.3V
Voo + 0.3 V to
Vss -0.3 V
O°C to 70°C
-65°C to + 150°C
11-102
Package Code
FM
Package Description
Ceramic DIP
Molded DIP
Molded Surface Mount
MA212A· MA212AT
1200/300 bps
Full Duplex Modem
FAIRCHILD
A Schlumberger Company
Advanced Signal Processing Division
Description
Connection Diagram
28-Lead Dip
(Top View)
The IlA212A and the IlA212AT 1200 bps modem circuits
are fabricated in Fairchild's advanced Double-Poly SiliconGate CMOS process. Either monolithic chip performs all
signal processing functions required for a Bell 212A/1 03
compatible modem. Dialing, handshaking protocols, and
mode control functions can be provided by a general purpose single-chip IlC. The IlA212A or IlA212AT and IlC;
along with several components to handle the control and
telephone line interfaces, provide a high performance,
cost-effective solution for an intelligent Bell 212A-compatible modem design.
SUM
Either modem chip performs the modulation, demodulation,
filtering and certain control and self-test functions required
for a Bell 212A-compatible modem, as well as additional
functional enhancements. Switched capacitor filters provide
channel isolation, spectral shaping and fixed compromise
equalization for both high and low speed modes.
A novel switched-capacitor modulator and a digital coherent demodulator provide 1200 bps QPSK operation while a
separate digital FSK modulator and demodulator handle
the 0-300 bps requirement. The /lA212AT includes an integral DTMF tone generator on-chip. The IlA212A without
DTMF generator, is cost optimal for answer-only applications or if an external dialer is present. The IlA212A and
J.!A212AT are otherwise pin and firmware compatible. Existing IlA212A applications can be easily upgraded to the
J.!A212AT with minor software changes (see technical bulletin M-1 appended.) The receive filter and energy detector
may be configured for call progress tone detection (dialtone, busy, ringback, voice), providing the front end for a
smart dialer on either the J.!A212A or J.!A212AT.
• Functions as 212A and 103 Compatible Modem
• Performs all Signal Processing Functions
• Interfaces to Single Chip IlC Which Handles
Handshaking Protocols and Mode Control Functions
• DTMF Tone Generation (!lA212AT)
• IlA212A is Pin and Firmware Compatible with the
!lA212AT for Easy Upgrade
• Call Progress Tone Detection for Smart Dialer
Applications
• On Chip OSCillator Uses Standard 3.6864 MHz Crystal
• Few External Components Required
• Industrial Temperature Range Option (-40°C to
+85°C)
• Operates from +5 and -5 Volt Supplies
• Low Operating Power: 35 mW Typical
• 28-Lead Ceramic DIP, 28-Lead Plastic DIP, and
28-Lead Surface Mount Packages
• A IlA212A DeSigner's Kit Is Available
Voo
LIM
27
Vss
RXIN
26
AGNO
DOT
25
TXO
ETC
24
oiA
SYNC
23
TXSQ
EOET
22
SCT
HS
21
MOD1
SCRM
20
MOO2
TXO
10
XTL2
11
XTL1
12
17
HSK2
SCR
13
16
HSK1
RXO
14
15
RLST
19
TEST
DGNO
Order Information
Type
Temperature
Range
Code Package
IlA212ATDC o to +70°C
IlA212ATDV -40°C to +85°C
J.!A212ATPC o to +70°C
J.!A212ATQC o to +70°C
IlA212ADC
IlA212ADV
IlA212APC
o to + 70°C
-40°C to + 85°C
o to + 70°C
FM 28-Lead Ceramic DIP
FM 28-Lead Ceramic DIP
28-Lead Molded DIP
28-Lead Molded
Surface Mount
FM 28-Lead Ceramic DIP
FM 28-Lead Ceramic DIP
28-Lead Molded DIP
'Consult Factory
Absolute Maximum Ratings
VDD to DGND or AGND
Vss to DGND or AGND
Voltage at any Input
Voltage at any Digital Output
Voltage at any Analog Output
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10 s)
11-103
7.0 V
-7.0 V
VDD + 0.3 to
Vss -0.3 V
VDD + 0.3 V to
DGND -0.3 V
VDD + 0.3 V to
Vss -0.3 V
O°C to 70°C
-65°C to + 150°C
300°C
•
J.lA212A • J.lA212AT
Pin No.
28
Pin Description
Positive power supply VDD = + 5 V
VDD
26
Pin No.
21
20
Pin Description
MOD1
Selects character length (ASYNC) or
TX clock (SYNC). In ASYNC mode,
MOD2
selects 8, 9, 10 or 11 bit character
length; in SYNC mode, selects internal, external or recovered RCV
clock as XMTR data clock source.
Active only if HS = 1. (See Table 1)
(Note)
AGND
Analog Ground
18
DGND
Digital Ground
27
Vss
Negative power supply Vss = -5 V
3
RXIN
Line signal to modem. From active
or passive Hybrid output.
25
TXO
Line signal from modem. To active
or passive Hybrid input.
10
TXD
XMIT Data. Serial data from host.
Disconnected when in digital loop.
24
O/A
Orig/answer Mode Select. Assigns
channels to XMTRS/RCVRS.
1 = Originate mode, 0 = Answer
mode. (Note)
14
RXD
RCVD Data. Serial data to host, Intern ally clamped to mark (= 1)
when modem is in digital loop or
EDET is inactive (= 1).
23
TXSQ
Squelch XMTRS in date mode.
XMTRS off; 1 = turns on
XMTR selected by HS pin.
iJA212AT: In dialer mode, 0 = DTMF
generator OFF/call progress detection. 1 = DTMF generator ON.
iJA212A: In dialer mode call progress detection only. TXSQ must be
set to O.
22
SCT
Serial Clock Transmit. 1200 Hz
clock providing XMTR timing in
SYNC mode. SCT source (INT.,
EXT., SLAVE) selected by MOD1,
MOD2 pins. TXD changes on negative edge, sampled on positive
edge. Internal clock provided in
ASYNC mode.
5
ETC
9
SCRM
Scrambler. "0" disables scrambler
and descrambler for testing purposes.
12
11
XTL1
XTL2
Frequency control. 3.6864 MHz
XTAL oscillator, operating parallel
mode. Provides timing, sample
clocks and L.O.'s.
External Transmit Clock. 1200 Hz
external clock providing XMTR timing in SYNC mode, selected by
MOD1, MOD2 pins. TXD changes
on negative edge, sampled on positive edge. Provided on SCT pin if
selected.
13
SCR
Serial Clock Receive. In SYNC
mode, 1200 Hz bit clock recovered
from RCVD Signal. May be pin-selected (MOD1, MOD2) as local
transmit clock (SLAVE mode); provided on SCT pin if selected. RXD
changes on negative edge, sampled
on positive edge. Undefined in ASYNC mode.
7
EDET
Energy Detect. In data mode,
EDET = 0 if valid signal above
threshold is present for 155 ± 50
ms, EDET = 1 if signal below
threshold for > 17 ± 7 ms. In dialer
mode, follows on/off variations of
call-progress tones, when TXSQ = 0
o = Both
8
HS
Selects modem speed. 1 selects
1200 bps. 0 selects 300 bps. (Note)
6
SYNC
Selects CHAR ASYNC or BIT SYNC
mode. 1 = ASYNC mode: enables
XMIT & RCV buffers, sets character
length according to MOD1, MOD2
pins. 0 = SYNC mode: disables buffers, selects TX clock source according to MOD1, MOD2 pins.
Active only if HS = 1.
Note
For IlA212AT in dialer mode, a/A, HS, MOD1 and MOD2 select the DTMF
to be generated (see Table 2).
11-104
J-LA212A • J-LA212AT
Pin No.
15
2
Pin Description
RLST
Remote Loop Status, used in RDL
mode. Responding modem: sets
RLST = 0 upon receipt of unscrambled mark for 154 - 231 ms. initiating modem: asserts RLST = 0 upon
receipt of scrambled mark for
231 - 308 ms. (See Table 3).
SLIM
Soft Limiter Output. Connect external 0.033 J.lF capacitor here.
LIM
Comparator input. Connected external 0.033 J.lF capacitor here.
4
19
16
17
by MOD1 and MOD2 internal, external or derived from the
recovered received data. A scrambler preceeds encoding
to ensure that the line spectrum is sufficiently distributed
to avoid interference with the in-band supervisory singlefrequency signaling system employed in most Bell System
toll trunks. The randomized spectrum also facilitates timing
recovery in the receiver. The scrambler is characterized by
the following recursive equation:
Yi = Xi EB Yi-14 EB Yi-17
If HS = 1, forces a 1200 bps dotting
pattern on the transmit path, for use
when programming the 212AT high
speed self-test mode. Both RCV
and XMIT paths are in SYNC mode
during dotting transmission, overriding the setting of SYNC, and of
HSK1, HSK2. If HS = 0, DOT forces
a 155 bps dotting pattern for use in
lowspeed self-test mode. 1 = Normal
Path, 0 = Dotting.
TEST
HSK1,
HSK2
When the TEST pin is inactive
(high), HSK1 and HSK2 select one
of four transmit conditions, for use
when programming the Handshake
sequences. (See Table 1). When
TEST is active (low), the HSK1 and
HSK2 pins select one of three test
conditions, or, alternatively, the dialer mode used for call progress tone
detection and DTMF tone generation, J.lA212AT only.
where Xi is the scrambler input bit at time i. Yi is the
scrambler output bit at time i and EB denotes the XOR
operation.
212A-type modems achieve full-duplex 1200 bps operation
by encoding transmitted data by bit-pairs (dibits), thereby
halving the apparent data rate. The resultant reduced
spectral width allows both frequency channels to coexist in
a limited bandwidth telephone channel with practical levels
of filtering. The four unique dibits thus obtained are graycoded and differentially phase modulated onto a carrier at
either 1200 Hz (originate mode) or 2400 Hz (answer
mode). Each dibit is encoded as a phase change relative
to the phase of the preceding signal dibit element:
Dibit
Phase Shift (deg)
00
01
+90
11
-90
180
10
Functional Description*
Refer to Figure 1.
Transmitter
The transmitter consists of high-speed and low-speed modulators, a transmit buffer and scrambler, and a transmit
filter and line driver. In high-speed asynchronous mode,
transmit data from the Data Terminal Equipment enters the
transmit buffer, which synchronizes the data to the internal
1200 bps clock. Data which is underspeed relative to 1200
bps periodically has the last stop bit sampled twice resulting in an added stop bit. Similarly, overspeed input data
periodically has unsampled - and therefore deleted - stop
bits. The MOD1 and MOD2 pins choose 8, 9, 10 or 11 bit
character lengths. In synchronous mode the transmit buffer
is disabled. The transmitter clock source may be chosen
o
At the receiver, the dibits are decoded and the bits are
reassembled in the correct sequence. The left-hand digit
of the dibit is the one occurring first in the data stream as
it enters the modulator after the scrambler. The lowspeed
transmitter generates phase-coherent FSK using one of
two programmable tone generators. Answer mode mark
(2225 Hz) is also utilized as answer tone in both low and
high speed operation.
In Dialer mode, both tone generators are employed to
generate DTMF tone pairs. The summed modulator outputs
drive a lowpass filter which serves as a fixed compromise
amplitude and delay equalizer for the phone line and reduces output harmonic energy well below maximum specified levels. The filter output drives an output buffer
amplifier with low output impedance. The buffer provides
700 mVrms in data mode, for a nominal -9 dBm level at
the line, assuming 2 dB loss in the data access arrangement.
* For additional information contact sales office for Applications Note ASP-1
"Theory of Operation-IlA212A" and Technical Bulletins M1, M3 & M4.
11-105
•
JlA212A· JlA212AT
mode the descrambler output is identically the received
data, while in asynchronous mode the descrambler output
stream is selectively processed by the receive buffer. Underspeed data presented to the transmitting modem passes essentially unchanged through the receive buffer.
Overspeed data, which had stop bits deleted at the transmitter, has those stop bits reinserted by the receive buffer.
(Generally, stop bit lengths will be elastic). The receive
buffer output is then presented to the receive data pin
(RXD) at a nominal intracharacter rate of 1219.05 bps.
DTMF Tone Generation
The ~212AT includes on-chip DTMF generation, using
two programmable tone generators. Dialer mode must be
selected on TEST, HSK1 and HSK2 for DTMF dialing. The
a/A, HS, MOD1 and MOD2 pins are used to select the
required digit according to the encoding scheme shown in
Table 2, and the tones are turned on and off by the logic
level on TXSO. The generated tones meet the applicable
CCITT and EIA requirement for tone dialing. DTMF output
levels are 1.0 Vrms (low group) and 1.25 Vrms (high
group).
Receiver
The received signal from the line-connection circuitry passes through a lowpass filter which performs anti-aliasing
and compromise amplitude and delay equalization of the
incoming signal. Depending upon mode selection (originate/answer) the following mixer either passes or down
converts the signal to the 1200 Hz bandpass filter. In analog loopback mode, the receiver originate and answer
mode assignments are inverted, which forces the receiver
to operate in the transmitter frequency band. The 1200 Hz
bandpass filter passes the desired received signal while
attenuating the adjacent transmitted signal component reflected from the line (talker echo). The chosen passband
shape converts the spectrum of the received high-speed
signal to 100% raised cosine to minimize intersymbol interference in the recovered data. Following the filter is a soft
limiter and a signal energy detector. An external capacitor
is used to eliminate offset between the soft limiter output
and the following limiter.
The energy detector provides a digital indication that energy is present within the filter passband at a level above a
preset threshold. Approximately 3 dB of hysteresis is provided between on and off levels to stabilize the detector
output. In dialer mode, the detector output is used to provide logic level indication of the presence of call progress
tones.
The limiter output drives the OPSK demodulator and the
carrier and clock recovery phase-locked loops. The low
speed FSK demodulator shares part of the clock recovery
loop. The OPSK demodulator and carrier loop form a digital coherent detector. This technique offers a 2 dB advantage in error performance compared to a differential
demodulator. The demodulator output are in-phase (I) and
quadrature (0) binary Signals which together represent the
recovered dibit stream. The dibit decoder circuit utilizes the
recovered clock signal to convert this dibit stream to serial
data at 1200 bps.
The recovered bit stream is then descrambled, using the
inverse of the transmit scrambler algorithm. In synchronous
Master Clock/Oscillator/Divider Chain
The I.lA212A or I.lA212AT may be controlled by either a
quartz crystal operating in parallel mode or by an external
signal source at 3.6864 MHz. The crystal should be connected between XTL 1 and XTL2 pins, with a 30 pF capacitor from each pin to digital ground (see Figure 1).
Crystal requirements; Rs < 150 ohms, CL = 18 pF, parallel
mode, tolerance (accuracy, temp, aging) less than ± 75
ppm. An external TTL drive may be applied to the XTL2
pin, with XTL 1 grounded. Internal divider chains provide
the timing Signals required for modulation, demodulation,
filtering, buffering, encoding/decoding, energy detection and
remote digital loopback. Timing for line connect and disconnect sequences (handshaking) derives from the host
controller, ensuring maximum applications flexibility.
Control Considerations
The host controller, whether a dedicated microcontroller or
a digital interface, controls the ~212A or I.lA212AT as
well as the line connect circuit and other IC's. On-Chip
timing and logiC circuitry has been specifically designed to
simplify the development of control firmware.
Operating and Test Modes
Table 1 indicates the operating and test modes defined by
the eight control pins. The ~212A and ~212AT (together with the host controller) supports analog loopback, and
local and remote digital loopback modes. Analog loopback
forces the receiver to the transmitter channel. The controller forces the line control circuit on-hook but continues to
monitor the ring indicator. This mode is available for lowspeed, highspeed synchronous and highspeed asynchronous operation. In local digital loop, the modem I.C.
isolates the interface, slaves the transmit clock to SCR
(high-speed mode), and loops received data back to the
transmitter. In remote digital loop, local digital loop is initiated in the far-end modem by request of the near-end
modem, if the far-end modem is so enabled. The I.lA212A
and I.lA212AT includes the handshake sequences required
for this mode; the controller merely monitors RLST and
controls remote loopback according to Table 3. Remote
loop is only available in high-speed mode.
11-106
Figure 1 Block Diagram
.0331JF
SLIM I
EOET
SCR
LIM
RECEIVE FILTER
,-------------------------------------1
:
I
RXIN
:
BALANCED
ANTI_ALIAS
I
I
~~:
r:::;:-l
r'\
I AANnp.&~~ I :
1_,
I.
SCRM
3.6864 MHz
30"
~
RLST
D
30pF T
1---+--_--+1->
XTL1
(OGNO)
~
0
.....
RXC
ETC
SCT
•
I
,.
TXO
AGNO DGND
Voo
Txsa
Vss
'I'A212AT only
•
O/A
HSKl
HSK2
TEST
i.
DOT
MOD1 MOD2 SYNC
HS
TXO
JiA212A· JiA212AT
Answer Tone In this mode, 2225 Hz answer tone is
transmitted provided TXSQ is inactive high
( = 1). Receive speed is selected as normal
with the HS pin. This permits the speed of
the originating modem to be determined
while answer tone is continuously
transmitted.
Force
Continuous
Mark
Disconnects TXD pin from the transmitter
and forces the signal internally to a mark
(logic 1).
Force
Continuous
Space
Disconnects TXD pin from the transmitter
and forces the signal internally to a space
(logic 0).
Analog Loop Receiver is forced to the transmitter
channel. With modem on-hook
(disconnected from line) signal from TXO is
reflected through hybrid to RXIN.
Local Digital
Loop
Internally connects RXD to TXD and SCR
to SCT. Transmitted data (TXD) and clock
(ETC) are ignored. SCR and SCT are
provided. RXD is forced to 1.
Remote
Digital
Loop
Initiating modem: If RDL is initiated
(TEST = 0, HSK1 = 1, HSK2 = 0), TXD is
isolated, RXD is clamped to a 1 and
unscrambled mark is transmitted. When
high speed scrambled dotting pattern is
detected, scrambled mark is transmitted. At
this point, upon receipt of scrambled mark,
RLST is set to O.
Responding modem: Upon receipt of
unscrambled mark when in data mode
(TEST = HSK1 = HSK2 = 1), RLST is set to
O. Upon detecting this the controller
responds by setting TEST and HSK2 to 0,
and the modem I.e. isolates TXD, clamps
RXD to 1, and transmits a 1200 bps
scrambled dotting pattern. At this pOint,
upon receipt of a scrambled mark signal,
the modem I.C. internally loops RCVR data
and clock to the XMTR, and sets RLST
back to 1. (See Table 3)
Dialer Mode
The IlA212AT provides DTMF tone
generation and energy indication at EDET
pin to identify call progress tones, i.e. dial,
busy and ringback. The DTMF digit is
selected by the levels on 0/1\, HS. MOD1
and MOD2 according to Table 2. Tone
generation is turned on and off by the
level on TXSQ. 1 = on, 0 = off. The
J.lA212A provides call progress indication
only. TXSQ must be set to O.
11-108
J-lA212A· J-lA212AT
Electrical Characteristics Unless otherwise noted: VDD = 5.0 V ± 5%, Vss = -5.0 V ± 5%, DGND = AGND = 0
V, TA = O°C to 70°C, typical characteristics specified at VDD = 5.0 V, Vss = -5.0 V,
TA = 25°C; all digital signals are referenced to DGND, all analog signals are
referenced to AGND.
Table 1 Operating and Test Modes
DOT
0
1
1
1
1
1
1
1
1
1
1
HS
SYNC
-
X
-
1
1
1
1
1
1
1
-
-
-
1
1
1
1
1
1
0
X
1
MOD1
X
MOD2
TEST
HSK1
HSK2
X
1
1
1
1
1
1
1
1
1
1
1
0
0
0
-
1
0
0
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
0
-
-
0
0
0
1
0
0
-
-
-
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
Key:
SCT - TX Buffer and PSK Modulator Clock
SCR - Receive Clock
ETC - External Clock Input
SCT
Dotting Pattern (155 or 1200 bps)
Answer Tone
Force Continuous Mark
Force Continuous Space
ASYNC, 8 Bit
ASYNC, 9 Bit
ASYNC, 10 Bit
ASYNC, 11 Bit
SYNC, Internal
SYNC, Slave
SYNC, External
Analog Loop
Local Digital Loop
Response to Far End Request for RDL
Low Speed Mode
Dialer Mode, Note 1
Remote Digital Loop Initiate
INT
X
X
X
INT
INT
INT
INT
INT
SCR
ETC
ETC
SCR
SCR
X
X
X
INT - Internal 1200 Hz Clock
x - Don't Care
- - Set as appropriate for desired operating condition.
Table 2 DTMF Encoding 2 (J.LA212AT only)
O/A
HS
MOD1
MOD2
DTMF Digit
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
2
3
1
0
0
1
1
0
0
1
1
0
0
1
1
Description
4
5
6
7
8
9
#
A
B
C
0
Notes
1. DTMF digit is selected according to Table 2 for the jlI\212AT. 'i'XSQ
enables the tone generator: 1 = ON, 0 = OFF. TXSQ = 0 allows energy
detection of call progress tone in both the jlI\212A and jlI\212AT.
2. For DTMF to operate dialer mode must be asserted. Trn, HSKI and
HSK2 must be = O.
11-109
JIA212A • JIA212AT
Table 3 Remote Digital Loopback (RDL) Command Sequences
Modem Action
Controller Action
TEST
HSK1
HSK2
RLST
1
1
1
1
0
1
0
1
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
1
1
1
1
1
l'
1
0
1
Data Mode
Initiate RDL:
Disable scrambler
Disconnect TXD
Force 1 on RXD
Transmit unscrambled mark (U.M.)
"INITIATE RDL"
Recognize Dotting for 231 - 308 ms
Enable scrambler
Transmit scrambled mark (S.M.)
Recognize S.M. for 231 - 308 ms
Connect TXD
Unclamp RXD
"RDL ESTABLISHED"
Response to far end request:
U.M. recognized for 154 - 231 ms
"RDL REQUESTED"
"RDL RESPONSE OK"
Disconnect TXD
Force 1 on RXD
Force Sync Slave Mode
Transmit Dotting
S.M. recognized
Internally loop Receiver to Transmitter
"RDL ESTABLISHED"
Terminate RDL:
Reset to Data Mode
"TEST
~
HSKl
~
HSK2
~
1
TXSQ active 80 ms
may be asserted at anytime after
'"RDL ESTABLISHED··
and before terminating.
Energy Detector
Symbol
Characteristic
Condition
Vthon
Vthoff
OfflOn Threshold
OnlOff Threshold
Voltage Level at RXIN
Pin In Data Mode
ton
toff
Energy Detect Time
Data Mode
Loss of Energy Detect Time
at EDET Pin
Vthon
Vthon
Vthon
Dialer Mode
OfflOn Threshold Dialtone
OfflOn Threshold Busy/Ringback
ton
Energy Detect
(Detecting Call
Energy Detect
(Detecting Call
toff
in the Dialer Mode
Progress Tones)
in the Dialer Mode
Progress Tones)
Min
11-110
Max
6.5
5.2
105
10
Voltage Level at RXIN
Pin in Dialer Mode
At EDET Pin
Typ
155
17
Units
mV rms
205
24
10
4.6
ms
ms
mVrms
25
30
35
ms
30
36
42
ms
J.LA212A • J.LA212AT
System Performance
Symbol
BER
Characteristic
Condition
Min
= -30 dBm
= -44 dBm
Bit Error Rate: SNR required for
BER = 10- 5 @ 1200 bps on a
3002-CO line, with 5 kHz white noise
referred to 3 KHz. Figures shown are
for originate mode. (Note: Pline values
assume 4 dB net gain from line to
RXIN)
Pline
Pline
Telegraph Distortion
Back-to-Back, 300 bps
(Low Speed Mode)
Typ
Max
Units
13
14
dB
dB
10
% Peak
Figure 2 Bit Error Rate vs Signal-to-Noise Ratio
10-2 , . . - - - - , - - - , - - - , - - - , - - - , - - - ,
I
PIN :::;:-30dBm
I
10- 3 t----1~r__1~\-1-_t-_t-_t
w
!;;
a:
a:
~
10-41--t-----1/--'\-/t--\-t---t----I
ill
...iii
10-' f--j---t-+t-+--'ct--\-t----I
10-' ' - - - - - - - , ' - - ' - - - - , . ' - - : ' ' - - ' - - - '
'6
4
SIGNAL TO NOISE RATIO (SNR) -
dB
Note
SER measured in synchronous mode, using an AEA S3A channel simulator.
Analog Line Interface
Symbol
Vline
Vlenh
Vlenl
VTXSQ
Pext
Vee
Characteristic
Output Level at TXO:
Output Level at TXO:
Output Level at TXO:
Output level at TXO:
Extraneous frequency
DTMF power.
Output Offset at TXO
Condition
Data Mode
DTMF HIGH Group
DTMF LOW Group
output relative to
Min
Typ
Max
Units
-20
Vrms
Vrms
Vrms
mVrms
dB
0.7
1.1
0.9
0.5
Any DTMF digit
5.0
11-111
mV
/-LA212A· /-LA212AT
Masterclock Input
Symbol
Characteristic
Fclock
Tolclk
Vexth
Clock Frequency
Clock Frequency Tolerance
External Clock Input HIGH
Vextl
External Clock Input LOW
Condition
Min
Typ
Max
3.6864
-.01
4.5
XTL2 driven and XTL 1
grounded
XTL2 driven and XTL 1
grounded
Units
MHz
+.01
%
V
0.5
V
Digital Interface
Symbol
Characteristic
VIL
VIH
VOL
VOH
IL
Input Voltage LOW
Input Voltage HIGH
Output Voltage LOW
Output Voltage HIGH
Input Current LOW
IIH
100
Input Current HIGH
Operating Current
Iss
Operating Current
Condition
Min
Typ
Max
0.6
2.2
IL =2.0 mA
IL =-2.0 mA
DGND ,,;; VIN ,,;; VIL.
All Digital Inputs
VIH ,,;; VIN ,,;; Voo
Voo = 5.0 V
No Analog Signals
Vss = -5.0 V
No Analog Signals
0.6
3.0
-100
-50
Units
V
V
V
V
/lA
4.3
10
p.A
mA
-2.7
-5.0
mA
Transmit Buffer (Character Asynchronous Mode)
Symbol
Characteristic
Ltxchar
Input Character Length
Rtxchar
Lbreak
Intracharacter Signaling Rate
Input Break Sequence Length
Condition
Start bit + data
bits + stop bit
At TXD pin
At TXD pin
11-112
Min
Typ
8
1170
23
1200
Max
Units
11
bits
1212
bps
bits
J.lA212A • J.lA212AT
Receive Buffer (Character Asynchronous Mode) Carrier Frequencies and Signaling Rates
Symbol
Characteristic
Condition
Min
Typ
Max
Units
Rtxehar
Fexr (ORIG)
Fexr (ANS)
Baud
Intracharacter Signaling Rate
HS Cxr Freq. (Orig. Mode)
HS Cxr Freq. (Ans. Mode)
Dibit Rate
At RXD pin
Unmodulated Carrier
Unmodulated Carrier
High Speed Mode
1219.05
1200
2400
600
bps
Hz
Hz
Baud
Fmark (ORIG)
Fspaee (ORIG)
Mark Frequency Originate Mode (1270)
Space Frequency Originate Mode (1070)
Low Speed Mode
Low Speed Mode
1269.42
1066.67
Hz
Hz
Fmark (ANS)
Low Speed Mode
2226.09
Hz
Fspace (ANS)
Mark Frequency
Answer Mode/Answer Tone (2225)
Space Frequency Answer Mode (2025)
Low Speed Mode
2021.05
Hz
Ftonl
DTMF Low Frequency Tone Group
Dialer Mode
698.2
771.9
853.3
942.3
Hz
Ftonh
DTMF High Frequency Tone Group
Dialer Mode
1209.4
1335.7
1476.9
1634.0
Hz
Tol
Tolerance of all above
Frequencies/Data Rates
Data Rate
Low Speed Mode
bps
11-113
-0.01
0
+0.01
300
%
bps
•
DTMF Dialing, the
J,lA212A and J,lA212AT
FAIRCHILD
A Schlumberger Company
Technical Bulletin M-1
April 1986
Garry Shapiro, Advanced Signal Processing Division
The /lA212A-the world's first and lowest power 1200/
300 b/s single-chip modem - will be joined, at about midyear, by the /lA212AT. The second in a series of Fairchild
modem IC products, the /lA212AT is pin-compatible with
the /lA212A with the addition of an integral DTMF tone
generator. This Bulletin summarizes factors to be considered in current /lA212A-based modem designs for migration to the /lA212AT.
DTMF Access
The /lA212AT DTMF tone generator is accessed via the
Dialer mode, which is asserted by setting
TEST = HSK1 = HSK2 = O. In the /lA212A, Dialer mode offers only call-progress tone detection, but, in the
/lA212AT, both call-progress tone detection and DTMF
tone generation are provided. The DTMF output is enabled
by TXSQ = 1 and disabled by TXSQ = 0; EDET should be
ignored when DTMF tones are being generated. See
Table 1.1.
Table 1.1. Dialer Mode
TXSQ
J,tA212A
/lA212AT
o
Call-progress
Call-progress
Call-progress
DTMF generation
DTMF Tone-Pair Selection
The /lA212AT employs 4 pins (O/A, HS, MOD1, and
MOD2) to generate 1 each of the 4 LOW and 4 HIGH
group DTMF tones; nominal tone frequencies are shown in
Table 1.2. Table 1.3 displays the DTMF Encoding matrix.
Therefore, if Data mode output power to a 600 n load is
-9 dBm, tone output power is -7 dBm (Low group) and
-5 dBm (HIGH group). These levels, as well as harmonic
and out-of-band energy values conform to the requirements of EIA RS-496.
p.A212AT Design-In Considerations
The /lA212A and /lA212AT are pin-compatible and functionally identical for all modes except DTMF tone generation. The /lA212AT can therefore replace the /lA212A in
all current and future designs, provided that the following
considerations are observed:
• Ensure Proper Control Of The TXSQ Pin When In
Dialer Mode. See Table 1.1.
• Provide /lController Lines For The a/A, HS, MOD1
And MOD2 Pins, if any are not presently provided.
• Plan For Replacement Of The Present Tone Dialing
Scheme. Current /lA212A designs with DTMF dialing
often employ a dialer chip or a DAC. Ensure that
downstream removal of such parts will not affect the
design.
• Allow ROM Space. Since DTMF control code replaces
the previous scheme, this should not usually be a
problem.
Table 1.3 DTMF Encoding Matrix
(TEST HSK1 HSK2 0, TXSQ 1)
=
=
=
=
a/A
HIS
MOD1
MOD2
DTMF Digit
0
0
0
0
0
1
0
1
0
1
2
3
0
0
0
1
0
1
4
5
6
7
0
0
0
1
0
1
8
9
Table 1.2 Tone Frequencies (Hz)
Low Group
F (Nom.)
697
770
852
941
High Group
F (Act.)
F (Nom.)
698.2
771.9
853.3
942.3
1209
1336
1477
1633
0
F (Act.)
1209.4
1335.7
1476.9
1634.0
0
Output Characteristics
0
0
Table 1.4 summarizes nominal output levels at the TXO
pin for Data mode, and for the DTMF Low and High tone
groups. Absolute values and values relative to Data mode
are shown.
Mode
Data
DTMF Low
DTMF High
Vtxo(rms)
Relative (dB)
0.70
0.88
1.11
+2
o
+4
11-114
0
1
0
#
A
B
C
D
FAIRCHILD
A Schlumberger Company
IlA212K
1200/300 bps Full Duplex
Modem Designer's Kit
Advanced Signal Processing Division
Description
The /lA212K Designer's Kit supports the Fairchild /lA212A
modem. The purpose of the kit is essentially threefold:
• To provide a convenient means of demonstrating the
capabilities, features and performance of the /lA212Athe world's first single-chip 212A modem IC.
• To facilitate the design of applications-specific control
firmware for the /lA212A.
• To provide a FCC registered DAA design reference and
Hybrid design support.
The Designer's Kit includes the following materials:
1. The j.tA212A Modem Board is a 1200/300 b/s, fullduplex, originate/answer, stand alone "smart" 212A modem board. Compatible with the Hayes Smartmodem
1200™ command set, Demo Board supports features not
found on Smartmodem™, including call progress tone detection (in addition to audio line monitoring) and support of
the Remote Loopback test mode. Demo Board showcases
all features and modes of the /lA212A IC, except the use
of 8 and 9 bit asynchronous characters, which are incompatible with the Hayes "AT" protocol. Synchronous operation is available, and is particularly useful for bit error rate
testing. All modes and options are via software control.
Demo Board operates with received line signals from -45
to > -10 dBm, and transmits at a nominal -10 dBm into
load.
a 600
n
2. The j.tA212A Designer's Manual
a. Overview and Hardware. This part summarizes features,
interface requirements (power, control, telephone line), and
modem architecture. It enables the user to quickly go online and to become familiar with modem operation.
b. pA212A Modem Demonstration Program (Ver. 1.27).
This is an extensive discussion of Demo Board control
firmware, and is primarily intended to assist designers developing firmware for /lA212A-based products. It is presented within the framework of the familiar Hayes
Smartmodem 1200™ command set, and may be considered a superset of that de-facto industry standard. Although written for the 6801 microcontroller, the
organization and modularization of the code are applicable
to most of the microcontrollers currently available.
3. To Assist Hardware and Firmware Development
a. a circuit schematic diagram and parts list
b. Technical Bulletin M3: DAAIHybrid Design Programs for
the pA212A
c. a 5.25" floppy disk containing 6801 source listings and
utilities. Object listings are also available to those requiring
them.
Consult your local Fairtech™ Center, Salesoffice or Advanced Signal Processing Division for further details, reference materials and information regarding new modem and
design support products.
Figure 1 #lA212K
11-115
Aerospace and Defense
Processing
FAIRCHIL.D
A Schlumberger Company
Aerospace and Defense Processing
ing, test methods, laboratory suitability, product assurance
program, and personnel training. Facilities and documentation are audited by DESC prior to certification and periodically thereafter.
Processing to MIL-M-38510 and MIL-STD-883 is performed
by a totally dedicated Business Unit within the Linear Division of Fairchild to serve the unique Linear components
requirements of our various military customers. Fairchild
Linear has been committed to the Linear Hi Rei program
for many years and intends to continue to maintain a
leadership position in that market segment.
Fairchild Linear maintains a very active MIL-M-38510 Qualified Products List (QPL) Program and has maintained a
leadership position in the total number of Linear QPL's for
many years.
The Aerospace and Defense program offers four levels of
processing flows as noted below. These flows would normally satisfy a majority of customer requirements.
An outline of the JM35810 Class "B" flow is given in
Figure 1.
DESC Selected Item Drawings
• Jan-Level "8" - Full compliance to MIL-M-38510 Jan
program and QPL listings as published by Defense
Electronics Supply Center.
DESC Selected Item Drawings or Military Drawings provide
and industry standard specification in compliance with
Class "B" requirements for devices that are not JAN qualified. These products are dual marked with the DESC Military Drawing Number as well as the industry standard
device number.
• Military (DESC) Drawing - Conformance to Class "8"
process requirements to DESC selected item
drawings.
Linear "Q8" Flow (MIL-STD-883 Class "8")
Fairchild's "QB" process flow can fill customer needs
when a desired product is not available on JAN QPL or
when system requirements call for a cost effective but reliable alternative to the full JAN program. The product is
processed to MIL-STD-883 methods as specified in Figure
1. Electrical testing is performed to Fairchild Standard
Schematic as defined on the data sheets.
• "Q8" Flow - Conformance to Class "8" process
requirements of MIL-STD-883 to Fairchild MIL
temperature range data sheet electricals.
• "QS" Flow - Conformance to Class "S" process
requirements of MIL-STD-883 to Fairchild MIL
temperature range data sheet electricals and
including wafer lot acceptance per Figure 3A.
JAN Qualified (MIL-M-38510) Class "8" Program
The JAN Program offers the customer a standard of product processing, quality and reliability that is well documented by the manufacturer and monitored by the Defense
Electronics Supply Center (DESC) of the U.S. Government.
The products are manufactured in the U.S. in a government certified facility to the requirements of MIL-M-38510
and individual product specifications as called out in the
MIL-M-38510 "Slash Sheets". The DESC certification is
based on standardized documentation for design, process-
"QS" Flow
Fairchild Linear offers a capability to fulfill basic processing
requirements of Class "S" at wafer fabrication, assembly,
environmental screening and test/finish on selected popular devices. It is our intent to standardize the processing
of Class "S" products to the "QS" flow shown in Figures
3A, 38, and 3C so that customer requirements for Class
"S" can be accommodated. Fairchild does not currently
hold a Class "S" certification from DESC.
12-3
•
Aerospace and Defense Processing
Figure 1 "08" and JAN Class "8" Process Flow
Description
I
Internal Visual
"OB" Flow
MIL-STD-883
Test Method
and Description
JAN Class "B" Flow
MIL-STD-883
Test Method
and Description
2010 Condo B
2010 Condo B
1008 Condo C
(note 1)
1008 Condo B
(note 1)
1010 Condo C
1010 Condo C
I
Stabilization Bake
I
Temperature Cycling
I
Constant Acceleration
(Centrifuge)
I
Interim (Pre Burn-In)
Electrical Parameters
2001 Condo E
2001 Condo
y 1 Orientation only
y 1 Orientation only
(note 2)
(note 2)
Per Applicable Test Spec.
Per Applicable Device
Specification (Slash Sheet)
1015, 160 Hrs. at 125°C or
Per Table 1 of Method 1015
1015, 160 Hrs. at 125°C or
Per Table 1 of Method 1015
Per Applicable Test Spec.
Per Applicable Device
Specification (Slash Sheet)
5%
5%
Per Applicable Test Spec.
Per Applicable Device
Specification (Slash Sheet)
1014
1014
5005 Groups A, B, C and D
Limits and Conditions Per
Applicable Linear "OB"
Data Sheet
5005 Groups A, B, C and D
Limits and Conditions Per
Applicable Device Specification
(Slash Sheet)
2009
2009
I
Burn-In Test
I
Interim (Post Burn-In)
Electrical Parameters
I
Percent Defective
Allowable (PDA)
Calculation
I
Final Electrical Test
I
Seal (Hermiticity)
I
Ouality Conformance
Inspection
I
External Visual
Notes:
1, Defines minimum time and temperature, greater temperature and/or
longer time used for some packages types.
2. Or lower G levels as allowed for larger packages per MIL-STD-883.
Method 5004.
12-4
Aerospace and Defense Processing
Figure 2
JAN Part Numbering System
J M
385101 101 01 B G C
__
~
JAN Designator
Cannot be market with "J"
General
unless qualified on Part I
Spec
Procurement
or Part II of the QPL
T1~-=------
Refers to Detail Spec
Defines
Device
101 Op Amps
102 Voltage Regulators
Type
103 Comparators
104 Interface
106 Voltage Followers
107 Positive Fixed Voltage Regulators
108 Transistor Arrays
109 Timers
110 Quad Op Amps
112 Voltage Comparator
113 D to A Converter
115 Negative Fixed Voltage Regulators
117 Positive Adjustable Voltage Regulators
118 Negative Adjustable Voltage Regulators
119 Low Power, Low Noise, Bi-Fet Op Amps
Processing
Level
S
B
Package Type
A 14-lead 1/4 x 1/4 Flatpak
B 14-lead 114 x 112 Flatpak
C 14-lead 1/4 x 3/4 Dip
D 14-lead 1/4 x 3/8 Flatpak
E 16-lead 1/4 x 7/8 Dip
F 16-lead 1/4 x 3/8 Flatpak
G 8-lead Can
H 10-lead 114 x 114 Flatpak
I 10-lead Can
J 24-lead 1/2 x 1 1/4 Dip
K 24-lead 3/8 x 5/8 Flatpak
L 24-lead 3/8 x 112 Flatpak
X 3-lead TO-5 Can
Y 2-lead TO-3 Can
Z 24-lead 114 x 3/8 Flatpak
2 20 Terminal LCC
Lead Finish
A Hot Solder Dip
B Tin Plate
C Gold Plate
X Any Finish
Above
Linear JAN Generic Part Numbers
M38510/
01
02
03
04
05
06
07
08
101
741
747
101A
108A
2101A
2108A
118
1558
78M24
7805
7812
7815
7905
7912
7915
7924
102
723
103
710
711
111
2111
9614
9615
104
55107
55108
106
110
2110
107
109
78M05
78M12
78M15
4156
4136
124
79M15
79M24
138
108
3045
109
555
110
148
112
139
113
0802
0801
115
79M05
79M12
117
117H
117K
150
119
771
772
774
Note
Dated material. Please contact Fairchild for latest revisions.
12-5
09
7824
10
Aerospace and Defense Processing
"as"
Processing
The flow charts that follow provide the major steps and
acceptance criteria utilized for the processes and should
form the basis for any Class "5" business negotiations
with Linear Marketing. These flow charts will also provide
a prospective customer with Fairchild Linear's capabilities
in Class "5" processing.
The Linear Division has a standardized "OS" flow for all
processing steps through Assembly, Test, Burn-In and Finish that will meet the requirements of a majority of customers and thus reduce the need for custom Class "5"
process flows.
Figure 3A
"QS" Minimum Wafer Lot Acceptance Steps
CV TEST WAFERS FOR FIELD OXIDE OUALITY
GlASSIVATION THICKNESS MEASUREMENT
CV TEST WAFERS FOR EVAPORATOR CLEANLINESS
TOP SIDE METAL THICKNESS MEASUREMENT
SAMPLE PROBE
TEST FOR
DIFFUSION
PARAMETERS
AU THICKNESS MEASUREMENT
SEM ACCEPTANCE OF METAL PATTERN: MIL-STO-S83
METHOD 2018
VISUAL INSPECTION & ACCEPTANCE FOR OlE BANK
WITH FUll TRACEABiliTY
"OS" DIE INVENTORY
12-6
Aerospace and Defense Processing
Figure 38
"QS" Assembly Flow
INCOMING "OS"
WAFERS WITH TRACEABILITY
DIE VISUAL
CONDITION "A"
METHOO 2010
DIE SHEAR
MONITOR
METHOD 2019
DIE ATTACH
BOND PULL
MONITOR
METHOD 2011
WIRE BOND
NON-DESTRUCTIVE
BOND PULL
METHOD 2023
INTERNAL VISUAL
CONDITION "A"
METHOD 2010
OC INTERNAL VISUAL AND
CUSTOMER SOURCE PRE-CAP
IF REOUIRED
SEAL
Note
Piece part traceability maintained when desired.
12-7
Aerospace and Defense Processing
Figure 3C
(Typical)
"QS" Test, Burn-In and Final Acceptance (Typical)
"QS" Environmental and Finish Processing
PRE-BURN-IN ELECTRICAL PER APPLICABLE DEVICE SPECIFICATION
(SLASH SHEET)
ASSEMBLED CLASS "S" LOT
STABILIZATION BAKE CONOITION C
(Note 1)
METHOD 1008
TEMPERATURE CYCLING CONDITION C
BURN-IN 240 HOURS AT 12S'C OR PER FIGURE 1015-1 OF
MIL-STD-883
POST BURN-IN ELECTRICAL PER APPLICABLE DEVICE
SPECIFICATION
(SLASH SHEET)
METHOD 1010
CONSTANT ACCELERATION Yl ORIENTATION
CONDITION E
(Note 2)
METHOD 2001
PARTICLE IMPACT NOISE DETECTION (PIND) CONDITION A
PERCENT DEFECT ALLOWABLE (PDA) CALCULATION
METHOD 2020
FINE AND GROSS LEAK TEST -
METHOD 1014
FINE LEAK TEST - METHOD 1014, CONDITION B
GROSS LEAK TEST - METHOD 1014, CONDITION C
QUALITY CONFORMANCE INSPECTION, METHOD 5005
GROUPS A, B, C, AND D. LIMITS AND CONDITIONS PER
APPLICABLE DEVICE SPECIFICATIONS
(SLASH SHEET)_
EXTERNAL VISUAL -
RADIOGRAPHIC
(X-RAY) (2 VIEWS)
METHOD 2012
METHOD 2008
25°C SCREEN
EXTERNAL VISUAL AND PACK -
SERIALIZATION AND MARKING
(MAXIMUM 4 CHARACTERS AND ON FLATPACK
SERIALIZATION ON BOTTOM ONLY)
PLANT CLEARANCE
METHOD 2009
SHIP
QSOOO31F
Notes
1. Defines minimum time and temperature, greater temperature and/or
longer time used for some packages types.
2. Or lower G levels as allowed for larger packages per MIL-STD-883,
Method 5004.
12-8
MA10SQB
FAIRCHILD
Voltage Regulator
A Schlumberger Company
MIL-STD-883
November 1985 - Rev 05
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
8-Lead Can
(Top View)
The IlA 10508 is a monolithic positive voltage regulator
constructed using the Fairchild Planar Epitaxial process.
Applications for this device include both linear and switching regulator circuits with output voltages greater than
4.5 V. This device will not oscillate when confronted with
varying resistive and reactive loads and will start reliably
regardless of the load within the ratings of the circuit. It
also features fast response to both load and line transients. 6
REG
OUT
BOOSTER
OUT
• Low Standby Current Drain
• Adjustable Output Voltage From 4.5 To 40 V
• High Output Current Exceeding 10 A With External
Components
• Load Regulation Better Than 0.1 %, Full Load With
Current-Limiting
FEEDBACK
COMMON
Lead 4 connected to case.
Order Information
Part No.
!1A105HM08
Casel
Finish
GC
Package Code
MiI-M-38510, Appendix C
A-1 8-Lead Can
•
13-3
IlA10SQB
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 12
Can
Input Voltage
Input/Output Voltage Differential
-65°C to + 175°C
-55°C to + 125°C
300°C
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
330 mW
50 V
40 V
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
Static tests at
Static tests at
Static tests at
Dynamic tests
25°C
125°C
-55°C
at 25°C
Group C and D Endpoints: Group A, Subgroup
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. V'R and V,- Vo are guaranteed by the FBSV test.
8. VOR is guaranteed by the FBSV and the VR LOAD tests.
9. The line and load regulation specifications are given for the condition
of constant chip temperature. Temperature drift effects must be taken
into account separately for high dissipation conditions.
10. The output currents given, as well as the load regulation, can be
increased by the addition of external transistors. The improvement
factor will be approximately equal to the composite current gain of the
added transistor.
11. With no external pass transistor.
12. Rating applies to ambient temperatures up to 125·C. Above 125·C
ambient, derate linearly at 150·C/W.
13-4
/JA10SQB
J.LA10SQB
Electrical Characteristics These specifications apply for input and output voltages within the ranges given and
for a divider impedance seen by the feedback terminal of 2 kn unless otherwise
specified.
Symbol
Characteristic
Subgrp
Condition
Min
Max
Unit
Note
VI = 50 V, Va = 20 V
1.63
1.81
V
1
1
VI = 8.5 V, Va = 4.5 V
1.63
1.81
V
1
1
8.5
50
V
1
1
VOR
Output Voltage Range 8
4.5
40
V
1
1
VI-Va
Input/Output Voltage
Differential?
3.0
30
V
1
1
VR LINE
Line Regulation 9
1
FBSV
Feedback Sense Voltage
VIR
Input Voltage Range?
VR LOAD
Ts
Load Regulation 9 ,10
Temperature Stability of FBSV
9.5 V ";VI "; 11.5 V, Va = 4.5 V
0.03
%/V
1
25 V"; VI"; 50 V, Va = 20 V
0.03
1
0.03
%N
%N
1
46 V"; VI"; 50 V, Va = 40 V
1
1
8.5 V"; VI"; 9.5 V, Va = 4.5 V
0.06
%/V
1
1
VI = 50 V, Va = 40 V,
o rnA"; IL .,; 12 rnA,
Rsc=10 n
0.05
%
1
1
0.1
%
1
2,3
25°C"; T A"; 125°C
1.0
%
4
2
-55°C"; T A"; 25°C
1.0
%
4
3
2.0
rnA
1
1
375
mV
1
1
0.02
%/V
4
4
%/1000
hrs
4
1
ISCD
Standby Current Drain
VI = 50 V, Va = 20 V
VCLS
Current Limit Sense Voltage 11
9.0 V"; VI"; 40 V, Va = 0 V,
Rsc= 10 n
llVI/ !:No
Ripple Rejection
CREF = 10 tJ.F, f = 10 kHz
S
Long Term Stability of FBSV
225
1.0
13-5
JiA10SQB
Primary Burn-In Circuit
CURRENT
LIMIT
BOOSTER
OUT
10 kfl
REG
OUT
COMP
SHUT·
DOWN
1/4W
0.47 p.F
60V
30V
UNREG
IN
FEEDBACK
O.'~F
2 kCl
100 V
COMMON
1/4W
REF
BYPASS
";"
-=Equivalent Circuit
r-----------~t_----------------~------~---UNREGULATEDIN
R10
6002
BOOSTER OUT
+--'VVv~~-- CURRENT LIMIT
; - - - - - - REGULATED OUT
+-______...._________ ~~~:rf~~~TlON
:l--I---+------~--- FEEDBACK
'-------1------1--4
L---~~~--~~------------~----
___________ REFERENCE BYPASS
__ _______________
~
COMMON
13·6
JlA109QB
F=AIRCHIL.O
5 Volt Regulator
A Schlumberger Company
MIL-STD-883
November 1985 - Rev 0 5
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
3-Lead TO-39 Can
(Top View)
The /lA 10908 is a complete 5 volt regulator constructed
using the Fairchild Planar Expitaxial process. This regulator
employs internal current-limiting, thermal shutdown and
safe-area compensation, making it essentially indestructible.
It is intended for use as a local regulator, eliminating
noise and distribution problems associated with single point
regulation. If adequate heat sinking is provided, this regulator can provide over 1 A output current. The /lA 10908 is
intended primarily for use with TTL and DTL logic and is
completely specified under worst case conditions to match
the power supply requirements of these logic families. In
addition to use as a fixed 5 V regulator, this device can
be used with external components to obtain adjustable
output voltages and currents and as the power pass element in precision regulators. 6
COMMON
OUT
Lead 3 connected to case.
Connection Diagram
2-Lead TO-3 Can
(Top View)
• Output Current In Excess Of 1 A
• Specified To Match Worst Case TTL And DTL
Requirements
• No Internal Components
• Internal Thermal Overload Protection
• Output Transistor Safe-Area Compensation
C~~~~~~OUT
o
0
1
IN
Order Information
Part No.
/lA109HM08
!1A109KM08
Casel
Finish
XC
YC
JAN Product Available
10701
8XC
13-7
Package Code
MiI-M-38510, Appendix C
3-Lead Can
2-Lead Can
3-Lead Can
•
J1A109QB
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
-65°C to
+ 175°C
Operating Temperature Range
-55°C to
300°C
+ 125°C
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 10
Can Without Heat Sink HMOSll
Can With Heat Sink HMOS12
Can Without Heat Sink KMOS13
Can With Heat Sink KMOS14
Input Voltage
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
0.18 W
0.5 W
0.71 W
Group A Electrical Tests Subgroups:
W
5.6
35
V
1. Static tests at 25°C
2. Static tests at 125°C
3. Static tests at -55°C
4. Dynamic tests at 25°C
9. AC tests at 25°C
Group C and D Endpoints: Group A, Subgroup
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests. Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. All characteristics except line and load transient response and noise
are measured using pulse techniques (tw -< 10 ms, duty cycle < 5%).
Output voltage changes due to changes in the internal temperature
must be taken into account separately.
8. Conditions given will result in the following: Po « 4 W for HM08 and
Po«15 W for KM08.
9. Device shall turn-on at VI < 9 V and shall remain on when the input is
returned to 10 V.
10. Internally limited.
11. Rating applies to
derate linearly at
12. Rating applies to
derate linearly at
13. Rating applies to
derate linearly at
ambient temperatures up to 125°C. Above 125°C,
140°C/W.
ambient temperatures up to 125°C. Above 125°C,
50°C/W.
ambient temperatures up to 125°C. Above 125°C,
35°C/W.
14. Rating applies to ambient temperatures up to 125 C. Above 12S C,
Q
D
derate linearly at 4.46°C/W.
13-8
pA109QB
1lA109HQB, 1lA109KQB
Electrical Characteristics CI = 0.33ILF, Co = 0.1 ILF, unless otherwise specified. 7
Symbol
Characteristic
Condition
HMQB
Vo
Output Voltage
Min
Max
Unit
Note
4.7
4.6
Subgrp
5.3
V
1
1
5.4
V
1
1,2,3
KMQB
VI = 10 V
IL = 350 rnA
IL = 500 rnA
Vo
Output VoltageS
B.O V';;; VI .;;; 20 V,
5.0 rnA';;; IL .;;; IMax
l:J.Vo/l:J.T
Average Temperature
Coefficient of Output Voltage
VI = 7.0 V
IL=5.0 rnA, 25°C';;;TA';;;125°C
2.0
mVloC
4
2
VI =7.0 V
IL = 5.0 rnA, -55°C';;; T A';;; 25°C
2.0
mVrC
4
3
7.0 V.;;; VI .;;; 25 V
50
mV
1
1
100
mV
1
1
10
rnA
1
1
O.B
rnA
1
1,2,3
0.5
rnA
1
1,2,3
2.0
A
1
1
IMax = 350 rnA
VR LINE
Line Regulation
IL =200 rnA
IMax= 1.0 A
IL = 500 rnA
VR LOAD
Load Regulation
VI=10 V, 5.0 mA';;;IL';;;IMax
ISCD
Standby Current Drain
7.0 V';;;VI';;;25 V
IMax = 500 rnA
IL =350 rnA
IMax = 1.0 A
IL =500 rnA
l:J.ISCD
(LINE)
Standby Current Drain Change
(vs Line Current)
B.O V.;;; VI .;;; 25 V
l:J.ISCD
(LOAD)
Standby Current Drain Change
(vs Load Current)
VI=10 V, 5.0 mA~IL';;;IMax
IMax = 350 rnA
IMax= 1.0 A
los
Output Short Circuit Current
VI =35 V
HMOB
VSTART
Voltage Start9
l:J.VI/l:J.VO
Ripple Rejection
VI=10 V, f=2400 Hz
No
Noise
VI=10 V, 10 Hz';;;f';;;10 kHz
IL =200 rnA
IL =500 rnA
KMOB
IL = 125 rnA
IL =50 rnA
l:J.VO/l:J.VI
Line Transient Response
Load Transient Response
Long Term Stability of Vo
1
1
V
1
1
60
dB
1
4
125
IN,ms
4
9
15
mVIV
4
9
2.0
mV/mA
4
9
0.5
%/1000
hrs
4
9
IL = 350 rnA
VI = 10 V (Vpulse = 3.0 V)
IL =5.0 rnA
VI = 10 V
IL =50 rnA
l:J.IL = 200 rnA
S
2.B
IL=100 rnA
IL = 5.0 rnA
l:J.VO/l:J.IL
A
4.7
VI = 10 V
13-9
IL = 100 rnA
l:J.IL =400 rnA
J).A109QB
Primary Burn-In Circuit
(38510/10701 may be used by FSC as an alternate.)
30V
IN
OUT
Equivalent Circuit
IN
R9
400 0
(NOTE 2)
R4
100 kCl
R13
10 kO
R1B
500 0
...------+-----i: 014
"]---<1"'::::::"':':+--">/111....--+ Rll
012
RS
~~~
___-+__ ___
~
0.& 0
(NOTE 2)
~~~_~_~O~T
3.3kCl
R16
&.0 kO
(NOTE 2)
RI
2.7 kCl
011
Rl
Dl
1.0 kO
R19
R7
S.O kO
SOOO
Rl0
L-__
~~~~
__
~
6.0 kCl
____
~
__
~~
R14
6.0kO
______4-__
__
~
~~
________
Note
1. Capaci10r value necessary to suppress oscillations.
2. pAl09HMOB: A9-400
pAl09KMOB: A9 -100
n. All =0.6 n, A16=6 kn.
n. All - 0.3 n, A16 - 2 kn.
13-10
~_______
COMMON
IlA117HQ8
3-Terminal Positive
Adjustable Regulator
FAIRCHILD
A Schlumberger Company
MIL-STD-883
November 1985 - Rev 05
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
3-Lead TO-39 Can
(Top View)
The /lA 117HQB is a 3-terminal adjustable positive voltage
regulator capable of supplying in excess of 0.5 A over an
output voltage range of 1.2 V to 37 V. This voltage regulator is exceptionally easy to use and requires only two
external resistors to set the output voltage. Further, it employs internal current-limiting, thermal shutdown and safearea compensation, making it essentially blow-out proof.
The /lA 117HQB serves a wide variety of applications including local, on-card regulation. This device also makes
an especially simple adjustable switching regulator, and a
programmable output regulator; or by connecting a fixed
resistor between the adjustment and output, the
/lA117HQB can be used as a precision current regulator. 6
IN
Order Information
Part No.
/lA117HMQB
•
•
•
•
Output Current In Excess Of 0.5 A
Output Adjustable Between 1.2 V And 37 V
Internal Thermal Overload Protection
Internal Short Circuit Current-Limiting Constant
Temperature
• Output Transistor Safe-Area Compensation
• Floating Operation For High Voltage Applications
13-11
Casel
Finish
XC
Package Code
MiI-M-38510, Appendix C
3-Lead Can
IlA117HQ8
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation9
Can Without Heat Sink10
Can With Heat Sink11
Input/Output Differential Voltage
Processing: MIL-STD-883, Method 5004
-65°C to + 175°C
-55°C to + 125°C
300°C
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
0.18 W
0.5 W
Quality Conformance Inspection: MIL-STD-883,
Method 5005
40 V
Group A Electrical Tests Subgroups:
1. Static tests at 25°C
2. Static tests at 125°C
3. Static tests at -55°C
4. Dynamic tests at 25°C
9. AC tests at 25°C
Group C and D EndpOints: Group A, Subgroup
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make dete sheet revisions available.
Contact local sales representative for the latest revision.
6. For more Information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. All characteristics except line and load transient response and noise
are measured using pulse techniques (tw';; 10 ms, duty cycle';; 5%).
Output voltage changes due to changes in the internal temperature
must be taken into account separately.
8. Conditions given will resul1 in the following: Po';; 4 W.
9. Internally limited.
10. Rating applies to ambient temperatures up to 125°C. Above 125°C,
derate lineariy at 140°C/W.
11. Rating applies to ambient temperatures up to 125°C. Above 125°C,
derate linearly at 50°C/W.
13-12
MA117HQ8
/lA117HQB
Electrical Characteristics IL = 50 rnA, unless otherwise specified?
Symbol
Va
VR LINE
VR LOAD
Characteristic
Output VoltageS
Line Regulation
Load Regulation
Condition
Min
Max
VI = 4.25 V, IL = 5.0 mA
1.2
VI = 4.25 V, IL = 500 mA
1.2
VI = 41.3 V, IL = 5.0 mA
1.2
VI=41.3 V, IL=50 mA
1.2
4.25 V < VI < 41.3 V
VI = 6.25 V, Va = VREF,
5.0 mA < IL < 500 mA
Unit
Note
Subgrp
1.3
V
4
1
1.3
V
1
1,2,3
1.3
V
1
1,2,3
1.3
V
1
1
9.0
mV
1
1
18.5
mV
1
2,3
12
mV
1
1
12
mV
1
2,3
ladi
Adjustment-Lead Current
VI = 6.25
100
pA
1
1,2,3
Aladi
(LINE)
Adjustment-Lead Current
Change (vs Line Voltage)
3.75 V--IN
OUT
AOJ
~
(NOTE 1)
I
1200
(NOTE 1)
~
-'
Note
1. Capacitor value necessary to suppress oscillations.
Equivalent Circuit
Refer to the Fairchild Linear Data Book Commercial
Section
13-18
fJA138Q8
FAIRCHILD
A Schlumberger Company
S-Amp Positive
Adjustable Regulator
MIL-STD-883
November 1985 - Rev 01
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
2-Lead TO-3 Can
(Top View)
The !1A 13808 is an adjustable 3-terminal positive voltage
regulator capable of supplying in excess of 5.0 A over a
1.2 V to 32 V output range. It is exceptionally easy to use
and requires only two resistors to set the output voltage.
A unique feature of the /.LA 13808 is time dependent current-limiting. The current-limit circuitry allows peak currents
of up to 12 A to be drawn from the regulator for short
periods of time. This allows it to be used with heavy transient loads and also speeds start-up under full-load conditions. Under sustained loading conditions, the current-limit
decreases to a safe value protecting the regulator. Also
included on the chip are thermal overload protection and
safe-area protection for the power transistor. Overload protection remains functional even if the adjustment lead is
accidentally disconnected. 2
•
•
•
•
•
•
•
•
•
(C1'S~T~2
o
0
IN
.0
ADJ
Order Information
Part No.
/.LA138KM08
High Peak Output Current
High Output Current
Output Adjustable Between 1.2 V And 32 V
Low Load Regulation
Low Line Regulation
Internal Thermal Overload Protection
Internal Short Circuit Current-Limiting
Output Transistor Safe-Area Compensation
Floating Operation For High Voltage Applications
Noles
1. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
2. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
13-19
Casel
Finish
YC
Package Code
MiI-M-38510, Appendix C
2-Lead Can
FAIRCHILO
A Schlumberger Company
llA150QB
3-Amp Positive
Adjustable Regulator
MIL-STD-883
November 1985 - Rev 0 '
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
2-Lead TO-3 Can
(Top View)
The I1A 15008 is ~an adjustable 3-terminal positive voltage
regulator capable of supplying in excess of 3.0 A over a
1.2 V to 33 V output range. It is exceptionally easy to use
and requires only two external resistors to set the output
voltage. A unique feature of the I1A 15008 is time dependent current-limiting. The current-limit circuitry allows peak
currents of up to 6.0 A to be drawn from the regulator for
short periods of time. This allows it to be used with heavy
transient loads and also speeds start-up under full-load
conditions. Under sustained loading conditions, the currentlimit decreases to a safe value protecting the regulator.
Also included on the chip are thermal overload protection
and safe-area protection for the power transistor. Overload
protection remains functional even if the adjustment lead is
accidentally disconnected. 2
IN
(C~s":Q2
o
ADJ
Order Information
Part No.
•
•
•
•
•
•
•
•
High Output Current
Output Adjustable Between 1.2 V And 33 V
Low Load Regulation
Low Line Regulation
Internal Thermal Overload Protection
Internal Short Circuit Current-Limiting
Output Transistor Safe-Area Compensation
Floating Operation For High Voltage Applications
0
10
11A150KM08
Notes
1. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
2. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
13-20
Casel
Finish
YC
Package Code
MiI-M-38510, Appendix C
2-Lead Can
IlA431 QB
Adjustable Precision
Shunt Regulator
FAIRCHILD
A Schlumberger Company
MIL-STD-883
July 1986-Rev 01
Aerospace and Defense Data Sheet
Linear Products
Description
The pA4310B is a 3-lead adjustable shunt regulator with
guaranteed temperature stability over the entire temperature range. The output voltage may be set at any level
greater than 2.5 V (VREF) up to 36 V merely by selecting
two external resistors that act as a voltage divided network. Due to the sharp turn-on characteristics this device
is an excellent replacement for many zener diode applications. 2
.
Connection Diagram
a-Lead DIP
(Top View)
CATHODE
• Typical Temperature Coefficient 50 ppmrC
• Temperature Compensated For Operation Over The
Full Temperature Range
• Programmable Output Voltage
• Fast Turn-On Response
• Low Output Noise
Notes
1. When changes occur. FSC will make data sheet revisions available.
eontsct local sales representstive for the latest revision.
2. For more information on device function. refer to the Fairchild Unear
Oats Book Commercial Section.
REFERENCE
NC
NC
NC
ANODE
NC
NC
Connection Diagram
20-Terminal CCP
(Top View)
....
u
z:
~u
zu
......
~
NC
NC
NC
NC
NC
NC
NC
ANODE
NC
NC
U
z:
U
z
U
z:
U
z
U
Z
eR053."
Order Information
Casel
Part No.
Finish
pA431RMOB
PA
pA431LMOB
2C
13-21
Package Code
Mil-M-38510, Appendix C
0-4 8-Lead DIP
C-2 20-Terminal CCP
FAIRCHILD
A Schlumberger Company
IlA494QB
Pulse Width Modulated
Control Circuit
MIL-STD-883
July 1986-Rev 01
Aerospace and Defense Data Sheet
Linear Products
Description
The #LA494QB is a monolithic integrated circuit which includes all the necessary building blocks for the design of
pulse width modulated (PWM) switching power supplies, including push-pull, bridge, and series configurations. The
device can operate at switching frequencies between
1.0 kHz and 300 kHz and output voltages up to 40 V. 2
Connection Diagram
16-Lead DIP
(Top View)
• Uncommitted Output Transistors Capable Of 200 mA
Source Or Sink
• On-Chlp Error Amplifiers
• On-Chip 5.0 V Reference
• Internal Protection From Double Pulsing Of Outputs
With Narrow Pulse Widths Or With Supply Voltages
Below Specified Limits
• Dead Time Control Comparator
• Output Control Selects Single-Ended Or Push-Pull
Operation
• Easily Synchronized (Slaved) To Other Circuits
Notes
1. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
2. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
+INt
+IN2
-INt
-IN 2
COMPENI
PWM COMP IN
VREF
DEAD TIME
OUTCONTRDL
CONTROl.
C.
Vee
II,-
C2
GND
E2
Cl
El
(DO,,,,,,
Connection Diagram
20-Terminal CCP
(Top View)
~
.
z
()
z
.. ..
..
z
~
COMPEN/PWM
VREF
COMP INPUT
OUT CONTROL
DEAD TIME CONTROL
HC
NC
CT
Vee
RT
C2
"z
"
Order Information
Casel
Part No.
Finish
#LA494DMQB
EB
#LA494LMQB
2C
13-22
U
()
z
iii
III
"""'_
Package Code
MII-M-38510, Appendix C
D-2 16-Lead DIP
C-2 20-Terminal CCP
J.lA723Q8
Precision Voltage
Regulator
FAIRCHILD
A Schlumberger Company
MIL-STD-883
July 1986-Rev 25
Aerospace and Defense Data Sheet
Linear Products
Description
The /lA723QB is a monolithic voltage regulator constructed
using the Fairchild Planar Epitaxial process. The device
consists of a temperature compensated reference amplifier,
error amplifier, power series pass transistor and currentlimit circuitry. Additional NPN or PNP pass elements may
be used when output currents exceeding 150 mA are required. Provisions are made for adjustable current limiting
and remote shutdown. In addition to the above, the device
features low standby current drain, low temperature drift
and high ripple rejection. The /lA723QB is intended for
use with positive or negative supplies as a series, shunt,
switching, or floating regulator. Applications include laboratory power supplies, isolation regulators for low level data
amplifiers, logic card regulators, small instrument power
supplies, airborne systems, and other power supplies for
digital and linear circuits. 6
Connection Diagram
10-Lead Can
(Top View)
•
•
•
•
•
CURRENT
LIMIT
Connection Diagram
14-Lead DIP
(Top View)
Positive Or Negative Supply Operation
Series, Shunt, Switching, Or Floating Operation
Low Line And Load Regulation
Output Voltage Adjustable From 2 V To 37 V
Output Current To 150 rnA Without External Pass
Transistor
,.
...
FREQ
COMP
CURRENT
SENSE
v+
-IN
Vc
+IN
OUT
o
Z
'"
CURRENT
LIMIT
...IE
t-
u
NC
NC
Connection Diagram
20-Terminal CCP
(Top View)
i::;
v-
Lead 5 connected to case.
Vz
..".
u
u
z
u
z
u
Z
v-
It.
CURRENT
NC
V+
SENSE
NC
NC
-IN
lie
NC
NC
+IN
OUT
Order Information
Casel
Part No.
Finish
/lA723DMQB
/lA723HMQB
I-IA723LMQB
CA
IC
2C
Package Code
MiI-M-38510, Appendix C
D-1 14-Lead DIP
A-2 10-Lead Can
C-2 20-Terminal CCP
JAN Product Available
I
>-
u
z
u
z
10201
10201
10201
10201
,;
13-23
BCA
BCB
BIA
BIC
D-1
D-1
A-2
A-2
14-Lead DIP
14-Lead DIP
10-Lead Can
10-Lead Can
IlA723Q8
Absolute Maximum Ratings
Storage Temperature Range
-65°C to + 175°C
Operating Temperature Range
-55°C to +125°C
Lead Temperature (soldering, 60 s)
300°C
Internal Power Dissipation 8
Can
350 mW
DIP and CCP
400 mW
Pulse Voltage from V+ to V-, (50 ms) 50 V
40 V
Continuous Voltage from V+ to VInput/Output Voltage Differential
40 V
Differential Input Voltage
±5 V
Voltage Between Non-Inverting
Input and V8 V
Current from Vz
25 mA
15 mA
Current from VREF
Processing: MIL-STD-883, Method 5004
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
Static tests at
Static tests at
Static tests at
Dynamic tests
25°C
125°C
-55°C
at 25°C
Group C and 0 Endpoints: Group A, Subgroup
Notes
I. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. The line and load regulation specifications are given for the condition
of constant chip temperature. Temperature drift effects must be taken
into account separately for high dissipation conditions.
8. Rating applies to ambient temperatures up to 125·C. Above 125·C
ambient, derate linearly at 140·C/W for the Can and 120·C/W for the
DIP and CCP.
13-24
MA723QB
llA723QB
Electrical Characteristics VI
= V+ = Ve";; 12 V, V- = 0 V, Vo = 5.0 V, IL
CREF = 0 IlF, unless otherwise specified.
Symbol
Characteristic
VREF
Reference Voltage
AVREF
(LOAD)
Reference Voltage Change
With Load
Condition
= 1.0
rnA, Rse
Min
6.95
o mA";; IREF";; 5.0
Max
7.35
20
mA
= 0 n,
C1
Unit
= 100
pF,
Note Subgrp
V
1
1,2,3
mV
1
1
VIR
Input Voltage Range
9.5
40
V
1
1
VOR
Output Voltage Range
2.0
37
V
1
1
VI-VO
Input/Output Voltage Diff.
3.0
38
V
1
1
Vz
Zener Voltage
Iz = 1.0 mA
5.8
7.2
V
1
1
VR LINE
Line Regulation?
12 V";;VI";;15 V
0.1
%Vo
1
1
12 V";;VI";;40 V
0.2
%Vo
1
1
12 V";;VI";;15 V
0.3
%Vo
1
2,3
0.15
1
VR LOAD
Load Regulation?
Tc Vo
Average Temp. Coefficient
of Output Voltage
ISCD
Standby Current Drain
los
Output Short Circuit Current
.lVI/AVo
Ripple Rejection
1.0 mA";; IL ,,;; 50 mA
%Vo
1
0.6
2,3
%Vo
1
25°C";; TA";; 125°C
-0.010
+0.010
%I"C
4
2
-55°C";; TA";; 25°C
-0.015
+0.015
VI = 30 V, IL = 0 mA
%I"C
4
3
3.5
mA
1
1
4.0
mA
4
2
2.4
mA
4
3
85
mA
4
1
Vo = 0 V, Rsc = 10 .11
45
f = 10 kHz, CREF = 0 p.F
64
dB
3
4
f = 10kHz, CREF = 5.0 p.F
76
dB
3
4
p.Vrms
3
4
7.0
J.lVrms
3
4
10
mVIV
3
4
mV/mA
3
4
I CREF = 0 p.F
I CREF = 5.0 J.lF
No
Noise
100 Hz";;f";;
10 kHz
AVo/AVI
Line Transient Response
AVI=3.0 V
AVo/AIL
Load Transient Response
IL = 40 mA, AIL = 10 mA
13-25
120
-1.5
IlA723QB
Block Diagram
Primary Burn-In Circuit
(38510/10201 may be used by FSC
as an alternate)
CURRENT CURRENT
SENSE
LIMIT
COMFI
f--
FREO
COMP
-IN
FREO.
V+
I
3GV
1000 pF
[
5.1 kO
1'4W
+IN
V+
VREF
VC
V-
OUT
-
EQOO560F
0.47 "F
-
I100V
Equivalent Circuit
v+
Rl
50011
03
R3
25
kll
R4
R5
l.Okll
1.0
07
Vc
kll
D1
6.5Y
OUT
D3
6.5 V
Vz
t-------~~:
""1-_____ ~I~~~ENT
L-_ _ _ _ _ _ ~~:::NT
+IN
V-
-IN
,a,lO'''''
13-26
IlA78MOSQB
FAIRCHILD
A Schlumberger Company
3-Terminal Positive
Voltage Regulator
MIL-STD-883
July 1986-Rev 25
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
3-Lead TO-39 Can
(Top View)
The IlA78M05QB 3-Terminal Medium Current Positive Voltage Regulator is constructed using the Fairchild Planar Epitaxial process. This regulator employs internal currentlimiting, thermal shutdown and safe-area compensation,
making it essentially indestructible. If adequate heat sinking
is provided, it can deliver in excess of 500 rnA output
current. It is intended as a fixed voltage regulator in a
wide range of applications including local, on-card regulation for eliminat:on of noise and distribution problems associated with single point regulation. In addition to use as a
fixed voltage regulator, this device can be used with external components to obtain adjustable output voltages and
currents. s
•
•
•
•
•
OUT
Lead 3 connected to case.
Output Current In Excess Of 0.5 A
No External Components
Internal Thermal Overload Protection
Internal Short Circuit Current-Limiting
Output Transistor Safe-Area Compensation
Connection Diagram
20-Terminal CCP
(Top View)
NC
Ne
NC
Ne
Ne
NC
NC
OUT
NC
NC
Order Information
Casel
Part No.
Finish
Package Code
MiI-M-38510, Appendix C
1.IA78M05HMQB
IlA78M05LMQB
3-Lead Can
C-2 20-Terminal CCP
XC
2C
JAN Product Available
10702
13-27
BXC
3-Lead Can
IlA78M05QB
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 9
Can Without Heat Sink 10
Can With Heat Sink 11
CCP Without Heat Sink12
Input Voltage
Processing: MIL-STD-883, Method 5004
-65°C to + 175°C
-55°C to + 125°C
300°C
0.18 W
0.5 W
0.4 W
35 V
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1. Static tests at 25°C
2. Static tests at 125°C
3. Static tests at -55°C
4. Dynamic tests at 25°C
9. AC tests at 25°C
Group C and 0 Endpoints: Group A, Subgroup 1
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests. Group C
4. Guaranteed but not tested
S. When changes occur. FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. All characteristics except line and load transient response and noise
are measured using pulse techniques (tw';; 10 ms. duty cycle';; S%).
Output voltage changes due to changes in the internal temperature
must be taken into account separately.
B. Conditions given will result in the following: PD ';; 4 W.
9. Internally limited.
10. Rating applies to ambient temperatures up to 12S·C. Above 12S·C,
derate linearly at 140·C/W.
11. Rating applies to ambient temperatures up to 12S·C. Above 12S·C.
derate linearly at SO·C/W.
12. Rating applies to ambient temperatures up to 12S·C. Above 12S·C.
derate linearly at 120·C/W.
13-28
MA78MOSQB
IlA78MOSQB
Electrical Characteristics V, = 10 V, IL = 350 mA, C, = 0.33 IlF, Co = 0.1 IlF, unless otherwise specified.
Symbol
Characteristic
Condition
5.0 mA < IL < 350 mA
tNol!::.T
VR
Max
4.8
5.2
V
1
1
IV, = 8.0 V
4.7
5.3
V
1
1,2,3
[VI = 20 V
4.7
Output VoltageS
Vo
LINE
Average Temperature
Coefficient of Output Voltage
Line Regulation
Load Regulation
Note Subgrp
5.3
V
1
1,2,3
IL = 5.0 rnA, 25°C .Vo/ !J.T
Average Temperature
Coefficient of Output Voltage
IL = 5.0 mA, 25°C";;; T A";;; 125°C
3.6
mV/oC
4
2
IL = 5.0 mA, -55°C";;; T A";;; 25°C
3.6
mVI"C
4
3
VR
Line Regulation
-30 V";;;VI";;;-14.5 V
80
mV
1
1
120
mV
1
2.3
1
LINE
-30 V";;; V I
< 15 V
-25 V";;;VI";;;-15 V
VR LOAD
Load Regulation
ISCD
Standby Current Drain
5.0 mA";;; IL ,,;;; 500 mA
50
mV
1
75
mV
1
2.3
240
mV
1
1.2.3
2.0
rnA
1
1
3.0
mA
1
2.3
!J.lsCD
(LINE)
Standby Current Drain
Change (vs Line Voltage)
-30 V";;;VI";;;-14.5 V
0.4
mA
1
1.2.3
!J.ISCD
(LOAD)
Standby Current Drain
Change (vs Load Current)
5.0 mA";;; IL ,,;;; 350 mA
0.4
mA
1
1.2,3
2.3
V
1
1
1.0
A
1
1.2.3
2.0
A
1
1.2.3
120
mV
3
1
V
1
1.2.3
dB
1
4.5,6
VDO
Dropout Voltage
los
Short Circuit Current
VI = -35 V
IPk
Peak Output Current
VI-Vo=-10 V
VRTH
Thermal Regulation
VI = -22 V, IL = 500 mA
VSTART
Voltage Start9
!J.VI/!J.VO
Ripple Rejection
VI = -17 V, IL = 125 rnA,
ej = 1.0 Vrms , f = 2400 Hz
No
Noise
VI=-17 V, IL=50 mA,
10 Hz";;;f";;;10 kHz
600
pVrms
4
9
!J.VO/!J.VI
Line Transient Response
VI = -17 V, IL = 5.0 mA,
Vpulse = -3.0 V
30
mVlV
4
9
!J.VO/!J.IL
Load Transient Response
VI = -17 V, IL = 50 mA,
!J.IL =200 mA
2.5
mV/mA
4
9
0.5
-4.75
13-77
50
tlA79M12QB
Primary Burn-In Circuit
(38510/11502 may be used by FSC as an alternate)
-30 V
IN
OUT
(NOTE 1)
Equivalent Circuit (Note 2)
r-----~----------~r_------~--~--------------~------------~--------_r----~COMMON
.2
Uk
t-------t:"os
025
4.5 k
TO 6.3 k
.23
4.0 k
A2'
+------r-----t:::017
1.7k
TO 18 k
OUT
01
+--+-i:: 020
.
800
L-____~----~----~~----~_4
A22
0.1
A13
__
~--------------~~~~------------
Noles
1. Capacitor value necessary to suppress oscillations.
2. All resistor values in ohms.
13-78
__
0.2
~------4__IN
IlA79M1SQB
3-Terminal Negative
Voltage Regulator
I=AIRCHILD
A Schlumberger Company
MIL-STD-883
July 1986-Rev 25
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
a-Lead TO-a9 Can
(Top View)
The IlA79M15QB 3-Terminal Medium Current Negative
Voltage Regulator is constructed using the Fairchild Planar
Epitaxial process. This regulator employs internal currentlimiting, thermal shutdown and safe-area compensation,
making it essentially indestructible. If adequate heat sinking
is provided, it can deliver up to 500 mA output current. It
is intended as a fixed voltage regulator in a wide range of
applications including local, on-card regulation for elimination of noise and distribution problems associated with single point regulation. In addition to use as a fixed voltage
regulator, this device can be used with external components to obtain adjustable output voltages and currents. 6
•
•
•
•
Output Current In Excess Of 0.5 A
Internal Thermal Overload Protection
Internal Short Circuit Current-Limiting
Output Transistor Safe-Area Compensation
13-79
MA79M15QB·
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 10
Can Without Heat Sink 1.1
Can With Heat Sink12
CCP Without Heat Sink13
Input Voltage
-65°C to + 175°C
-55°C to +125°C
300°C
0.18 W
0.5 W
0.4 W
-35 V
Burn-In: Method 1015, Condition A, PDA. calculated
using Method 5005, $ubgroup 1 .
Quality Conformance Inspectlon:MIL-STD-883,
Method 5005
.
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. All characteristics except line and load transient response and noise
are measured using pulse techniques (tw< 10 ms, duty cycle <5%).
Output vonage changes due to changes in the internal temperature
must be taken into account separately.
8. Conditions given will result in the following: Po < 4 W.
9. Slowly ramp input voltage up to -8.0 V. When circuit starts, output
voltage will be as specified.
10. Internally limited.
11. Rating applies to ambient temperatures up to 125°C. Above 125°C,
derate linearly at 140°C/W.
12. Rating applies to ambient temperatures up to 125°C. Above 125°C,
derate linearly at 50·C/W.
13. Rating applies to ambient temperatures up to 125°C. Above 125°C,
derate linearly at 120"C/W.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°(;
Dynamic tests at 25" C
DynamiC tests at 1250 C
Dynamic tests at -550 C
AC tests at 25°C
..
Group C and D Endpoints: Group A; Subgroup 1
13-80
J-lA79M15QB
/-IA79M15QB
Electrical Characteristics VI
Symbol
Vo
= -23
V, 350 rnA, CI = 2.0 /-IF, Co
Characteristic
= 1.0
/-IF, unless otherwise specified?
Condition
Output VoltageS
5.0 mA";;IL";;350 mA IVI=-17.5 V
VR liNE
VR LOAD
Average Temperature
Coefficient of Output
Voltage
Line Regulation
Load Regulation
Max
Unit
Note
-14.4
V
1
1
-15.75 -14.25
V
1
1,2,3
-15.75 -14.25
Subgrp
V
1
1,2,3
IL = 5.0 mA, 25°C";; TA";; 125°C
4.5
mY/DC
4
2
IL = 5.0 mA, -55°C";; T A ";; 25°C
4.5
mY/DC
4
3
1
I VI = -30 V
D.Vo/D.T
Min
-15.6
-30 V";;VI";;..,.17.5 V
80
mV
1
-'-30 V";; VI";; 18.5 V
150
mV
1
2,3
-28 V";; VI <-18 V
50
mV
1
1
5.0 mA";; iL < 500 mA
80
mV
1
2,3
240
mV
1
1
300
mV
1
2,3
2.0
mA
1
1
ISCD
Standby Current Drain
3.0
mA
1
2,3
D.ISCD
(LINE)
Standby Current Drain
Change (vs Line Voltage)
-30 V";;V I ";;-17.5 V
0.4
mA
1
1,2,3
D.ISCD
(LOAD)
Standby Curreni Drain
Ch~nge (vs Load Current)
5.0 mA";; IL ";;350 mA
0.4
mA
1
1,2,3
2.3
V
1
1
1.0
A
1
1,2,3,
2.0
A
1
1,2,3
150
mV
4
1
VDO
Dropout Voltage
los
Short Circuit Current
VI = -35 V
IPk
Peak Output Current
VI-Vo=-10 V
VRTH
Thermal Regulation
VI = -25 V, IL = 500 mA
VSTART
Voltage Start 9
D.VI/ D.Vo
Ripple Rejection
VI = -20 V, IL = 125 mA,
ej = 1.0 V,ms, f = 2400 Hz
No
Noise
VI =-20 V, IL = 50 mA,
10Hz";; f ,,;; 10kHz
D.Vo/ D.V I
Line Transient Response
D.Vo/ D.IL
Load Transient· Response
0.5
-4.75
V
1
1,2,3
dB
1
4,5,6
700
f.lV,ms
4
9
VI = -20 V, IL = 5.0 mA,
Vpul se = -3.0 V
30
mVIV
4
9
VI= -20 V, IL = 50 mA,
D.IL = 200 mA
2.5
mV/mA
4
9
13-81
50
MA79M15QB
Primary Burn-In Circuit
(38510/11503 may be used by FSC as an alternate)
-30 V
OUT_
>---IN
COMMON
:
~(NOTE
1)
1
(NOTE 1)
Equivalent Circuit (Note 2)
;-----~----------~--------_,--~--------------,_------------_r--------~----r_COMMON
0'
Uk
+---;:::05
025
4.5k
TO 6.3 k
R23
4.0k
+-----......----~a17
024
Uk
TO 18k
OUT
01
01.
Cl
15pF
R"
•. 1
09
7.5k
..,
01.
7.Sk
R13
IN
Noles
1. Capacitor value necessary to suppress oscillations.
2. All resistor values in ohms.
13-82
J,LA790SQB
3-Terminal Negative
Voltage Regulator
FAIRCHILD
A Schlumberger Company
MIL-STD-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
2-Lead TO-3 Can
(Top View)
The IlA79050B 3-Terminal Negative Voltage Regulator is
constructed using the Fairchild Planar Epitaxial process.
This negative regulator is intended as a complement to
the popular !lA78050B Positive Voltage Regulator. The
IlA79050B employs internal current-limiting, safe-area protection, and thermal shutdown, making it virtually indestructible. 6
•
•
•
•
OUT
Output Current In Excess Of 1 A
Internal Thermal Overload Protection
Internal Short Circuit Current-Limiting
Output Transistor Safe-Area Compensation
Order Information
Casel
Part No.
IlA7905KMOB
Finish
YC
Package Code
MiI-M-38510, Appendix C
2-Lead Can
JAN Product Available
11505
11505
13-83
BYA
BYC
2-Lead Can
2-Lead Can
J,lA790SQB
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 9
Can Without Heat Sink10
Can With Heat Sink 11
Input Voltage
Processing: MIL-STD-883, Method 5004
-65°C to + 175°C
-55°C to +125°C
300°C
0.71 W
5.6 W
-35 V
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
Notes
1.
2.
3.
4.
5.
100% Test and Group A
Group A
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dy nam ic tests at 1250 C
Dynamic tests at -550 C
AC tests at 25°C
Group C and 0 Endpoints: Group A, Subgroup 1
Periodic tests, Group C
Guaranteed but not tested
When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book' Commercial Section.
7. All characteristics except line and load transient response and noise
are measured using pulse techniques (tw~10 ms, duty cycle :::;;:;;5%).
Output voltage changes due to changes in the internal temperature
must be taken into account separately.
8. Conditions given will result in the following: Po';; 15 W.
9. Internally limited.
10. Rating applies to ambient temperatures up to 125·C. Above 125·C.
derate linearly at 35·C/W.
11. Rating applies to ambient temperatures up to 125·C. Above 125·C.
derate linearly at 4.46·C/W.
13-84
IlA790SQB
J.lA790SQB
Electrical Characteristics VI = -10 V, IL = 500 rnA, CI = 2.0 J.lF, Co = 1.0 J.lF, unless otherwise specified?
Symbol
Characteristic
Condition
Output VoltageS
Vo
5.0 mA ~ IL ~ 1.0 A
t:.Vo/t:.T
VR
LINE
Average Temperature
Coefficient 01 Output
Voltage
Line Regulation
Unit
Note
-4.8
V
1
1
1,2,3
-5.3
-4.7
V
1
-5.3
-4.7
V
1
1,2,3
mV/oC
4
2
IL = 5.0 mA, -55°C ~ T A ~ 25°C
1.5
mVrC
4
3
1
1
-25
V~VI~-7.0
V
50
mV
~-s.O
V
75
mV
V~VI~-8.0
V
25
mV
50
mV
1
2,3
5.0 mA ~ IL ~ 1.5 A
100
mV
1
1,2,3
1
~
VI
250 mA ~ IL ~ 750 mA
ISCD
Subgrp
1.5
-12
VR LOAD
Max
-5.2
IL = 5.0 mA, 25°C ~TA ~ 125°C
-25 V
Load Regulation
IVI = -8.0 V
IVI =-20 V
Min
Standby Current Drain
t:.ISCD
(LINE)
Standby Current Drain
Change (vs Line Voltage)
-25 V ~VI ~-s.O V
t:.ISCD
(LOAD)
Standby Current Drain
Change (vs Load Current)
5.0 mA
~
IL ~ 1.0 A
I
1
2,3
1
1
35
mV
1
60
mV
1
2,3
2.0
mA
1
1
3.0
mA
1
2,3
1.3
mA
1
1,2,3
0.5
mA
1
1,2,3
VDO
Dropout Voltage
IL = 1.0 A
2.3
V
1
1
los
Short Circuit Current
VI =-35 V
2.0
A
1
1,2,3
4.0
A
1
1,2,3
50
mV
1
1
V
4
1,2,3
dB
1
4,5,6
Ipk
Peak Output Current
VI = -S.O V, t:.Vo = 0.48 V
VRTH
Thermal Regulation
VI=-15 V, IL=1.0 A
VSTART
Voltage Start
VI = -20 V, RL = 5.0
t:.VI/t:.VO
Ripple Rejection
VI = -10 V, IL = 350 mA,
ej = 1.0 Vrrns , 1 = 2400 Hz
No
Noise
VI=-10 V, IL=100 mA,
10Hz ~ 1 ~ 10kHz
250
p.V rrns
4
9
t:.VO/t:.VI
Line Transient Response
VI = -10 V, IL = 5.0 mA,
Vpul se = -3.0 V
30
mVIV
4
9
t:.VO/t:.IL
Load Transient Response
VI = -10 V, IL = 100 mA,
t:.IL = 400 mA
2.5
mV/mA
4
9
13-85
n
1.0
-5.25
-4.75
45
~7905QB
Primary Burn-In Circuit
(38510/11505 may be used by FSC as an alternate)
-30 V
IN
OUT
(NOTE 1)
Note
1. Capacitor value necessary to suppress oscillations.
Equivalent Circuit
r---~r-------------~--------~~r---------------r--------------.--------~----~-eOMMON
A2
UkO
+----11::'05
A25
4.5kO
TO 6.3 kO
A2'
4.0kO
A2.
1.7 kO
TO 18 kO
OUT
A5
4200
01
01.
el
15"
.
15 kO
020
AI.
S.3kn
e'
'pF
Al0
A16
4.7 k(}
15 kO
AI.
2.3kO
A17
3.0'"'
A21
17,",
A30
2000
A22
0.040
A13
0.050
IN
13-86
p.A7912QB
FAIRCHILD
A Schlumberger Company
3-Terminal Negative
Voltage Regulator
MIL-STD-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
2-Lead TO-3 Can
(Top View)
The f.,lA79120B 3-Terminal Negative Voltage Regulator is
constructed using the Fairchild Planar Epitaxial process.
This negative regulator is intended as a complement to
the popular f.,lA78120B Positive Voltage Regulator. The
f.,lA 79120B employs internal current-limiting, safe-area
protection, and thermal shutdown, making it virtually
indestructible. 6
•
•
•
•
OUT
Output Current In Excess Of 1 A
Internal Thermal Overload Protection
Internal Short Circuit Current-Limiting
Output Transistor Safe-Area Compensation
Order Information
Part No.
f.,lA7912KMOB
Casel
Finish
YC
Package Code
MiI-M-38510, Appendix C
2-Lead Can
JAN Product Available
11506
11506
13-87
BYA
BYC
2-Lead Can
2-Lead Can
MA7912QB
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
-65°C to + 175°C
-55°C to + 125°C
300°C
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 9
Can Without Heat Sink 10
Can With Heat Sink II
Input Voltage
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
0.71 W
5.6 W
-35 V
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
Notes
I, 100% Test and Group A
2, Group A
3, Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
0
Group C and 0 Endpoints: Group A, Subgroup
7. All characteristics except line and load transient response and noise
are measured using pulse techniques (tw 10 ms, duty cycle
5%).
Output voltage changes due to changes in the internal temperature
must be taken into account separately,
8, Condttions given will result in the following: Po';; 15 W,
9, Internally limited,
10. Rating applies to ambient temperatures up to 125"C, Above 125"C,
derate linearly at 35"C/W.
II, Rating applies to ambient temperatures up to 125"C, Above 125"C,
derate linearly at 4.46"C/W,
-<
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dynam ic tests at 125 C
Dynam ic tests at -550 C
AC tests at 25°C
<
13-88
JlA7912QB
/.IA7912QB
Electrical Characteristics VI = -19 V, IL = 500 mA, CI = 2.0 /.IF, Co = 1.0 /.IF, unless otherwise specified'?
Symbol
Vo
Characteristic
Condition
Output Voltage 8
5.0 mA < IL < 1.0 A
t:.Vo/t:.T
VR LINE
VR LOAD
Average Temperature
Coefficient of Output
Voltage
Line Regulation
Load Regulation
I VI = -15.5 V
IVI =-27 V
Min
Max
UnIt
Note
-12.5
-11.5
V
1
1
-12.6
-11.4
V
1
1,2,3
-12.6
-11.4
V
1
1,2,3
IL=5.0 mA, 25°C--"(:> OUT
-IN
NC
-OFFSET NULL!
FREQ COMP
NC
-IN
FREQ
COMP
C::=::J-...J
V+
+lNC=:J---'
NC
-OFFSET NULL!
FREQ COMP
NC
v- - - - -. . ._ _ _ _ _....---NULL
+OFFSET
FREQ
COMP
-IN
V+
Order Information
+IN
OUT
Part No.
+OFFSET
!1A101DMOB
!1A1 01HMOB
!1A101FMOB
V-
NC
YC=:::JOUT
NULL
Casel
Finish
CA
GC
HA
Package Code
MiI-M-38510, Appendix C
D-1 14-Lead DIP
A-1 8-Lead Can
F-4 10-Lead Flatpak
NC
JAN Product Available
10103
10103
10103
10103
10103
10103
10103
10103
14-7
BCA
BCB
BGA
BGC
BHA
BHB
BPA
BPB
D-1
D-1
A-1
A-1
F-4
F-4
D-4
D-4
14-Lead DIP
14-Lead DIP
8-Lead Can
8-Lead Can
10-Lead Flatpak
10-Lead Flatpak
8-Lead DIP
8-Lead DIP
•
J-lA101QB
Processing: MIL-STD-883, Method S004
Absolute Maximum Ratings
-65°C to + 175°C
-55°C to + 125°C
300°C
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal PoWer DisSipation 11
Can and Flatpak
DIP
Supply Voltage
Differential Input Voltage
Input Voltage 12
Short Circuit Duration 13
Burn-In: Method 10.1S, Condition A, PDA calculated
. using Method SOOS, Subgroup 1
Quality Conformance Inspection: MIL"STD-883,
MethodSOOS
330 mW
400 mW
±22 V
±30 V
±20 V
Indefinite
Group A Electrical Tests. Subgroups:
1.
2.
3.
4.
5.
6.
9.
10.
11.
Static tests. at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
Dynamic tests at -55°C
AC tests at 25°C
AC tests at 125°C
AC tests at -55°C
Group C and 0 Endpoints: Group A,. Subgroup
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more ihformation on device function, refer to the Fairchild Linear
Data Book Commercial Section,
7. Z, is guaranteed by liB: Z, ~ 4.0 Vrll'B' Vr
125'C, and 19mV at -55'C.
B. Pc is guaranteed by Icc: Pc
= 40
~
26 mV at 25'C, 34 mV at
Icc-
9. V,R is guaranteed by the CMR test.
10. BW is guaranteed by t,: BW ~ 0.35/t,.
11. Rating applies to ambient temperatures up to 125'C. Above 125'C
ambient, derate linearly at 150'C/W for the Can and Flatpak and
120'C/W for the DIP.
12. For supply voltages less than ± 20 V, the absolute maximum input
voltage is equal to the supply voltage.
13. Short circuit may be to ground or either supply. Rating applies to
125°C case temperature or 75°C ambient temperature.
14-8
J.lA101QB
JlA101QB
Electrical Characteristics Vee = ± 20 V, unless otherwise specified .
Symbol
Vlo
. Characteristic
Input Offset Voltage
Condition
±5.0 V';;;Vcc';;;±20 V,
Rs = 50 Q
VCM =0 V
. 25°C';;;TA ';;;125°C
!:lVlol!:lT
Input Offset Voltage
Temperature Sensitivity
VIO adj
Input Offset Voltage Adjustment
Range
Radj = 5.1 MQ
110
Input Offset Current
VCM =0 V
!:lllol!:lT
liB
Input Offset CUrrent
Temperature Sensitivity
Input Bias Current
ZI
Input Impedance7
Icc
Supply Current
Pc
~55°C';;;
TA';;; +25°C
25°C';;; TA ,;;; 125°C
-55°C ';;;TA';;; +25°C
Input Voltage Range 9
VCM=±15 V, Rs=50 Q
PSRR
Power Supply Rejection Ratio
±5.0 V';;;Vcc';;;±20 V,
Rs=50Q
los
Output Short Circuit Current
VCC=±15V
Avs
Large. Signal Voltage Gain
Vcc=±15 V, Vo=±10 V,
RL = 2.0 kQ
. Output Voltage Swing
Vcc = ± 15 V
...
Transient
Response
TR(os)
Rise Time
Overshoot
BW
Bandwidth 10
SR
Slew Rate
mV
1
1
mV
1
2,3
25
pV 1°C
4
2
25
IlV/oC
4
3
mV
1
1,2,3
200
nA
1
1,2
500
nA
1
3
0.1
nArC
4
2
0.2
nA/oC
4
3
340
nA
1
1
750
nA
1
2,3
1
MQ
1
3.0
mA
1
1
2.5
mA
1
2
3
3.5
mA
1
mW
1
1
100
mW
1
2
70
dB
1
1,2,3
±15
V
1
1,2,3
IlV/v
1
1,2,3
316
mA
1
1,2,3
50
V/mV
1
4
25
V/mV
1
5,6
±12
V
1
4,5,6
±10
V
1
4,5,6
800
ns
3
9, 10, 11
25
%
3
9, 10, 11
0.437
MHz
3
9, 10, 11
0.3
V/IlS
3
9,10
0.2
V/IlS
3
11
VI=50 mV,
RL = 2.0 kQ, CL = 100 pF,
Av = 1.0
RL = 2.0 kQ, Av = 1.0
Subgrp
5.0
60
I RL = 10 kQ
I RL = 2.0 kQ
Note
120
Power ConsumptionS
Common Mode Rejection
Unit
6.0
0.3
CMR
TR(t,)
Max
1.0
±5.0 V';;;Vcc<±20 V,
VCM = 0 V
VIR
VOP
Min
NI (BB)
Noise Broadband
BW= 5.0 kHz
15
IlV,ms
4
9
NI (PC)
Noise Popcorn
BW = 5.0 kHz
80
IlVpk
4
9
14-9
MA101QB
Primary Burn-In Circuit
(38510/10103 may be used by FSC as an alternate)
30 pF
-OFFSET
NULLIFREQ
COMP
-
FREQ
COMP
+15V
~
r--
-IN
V+
+IN
OUT
+OFFSET
NULL
V-
I
r----
-15V
Equivalent Circuit
-OFFSET
NULLI
FREO COMP
FREQ
COMP
~--------~~------'--+----+-------~--------------~-----V+
-IN
----+-----------1------(;.
+IN----+-------~(
Rll
25 n
+-......__ OUT
L...__
Rl
5kn
R2
2OkO
R3
10kn
R8
1 kO
L-~~~__~----~~-----------4----------------~--~--~---~
R4
250n
+ OFFSET NULL
14-10
J.lA108AQB
Super Beta
Operational Amplifier
FA. RCH. L.O
A Schlumberger Company
MIL-STD-883
July 1986-Rev 25
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
8-Lead Can
(Top View)
The p.A 108AOB Super Beta Operational Amplifier is constructed using the Fairchild Planar Epitaxial process. High
input impedance, low noise. low input offsets, and low
temperature drifts are made possible through use of super
beta processing, making the device suitable for applications requiring high accuracy and low drift performance.
The p.A 108AOB is specially selected for extremely low offset voltage and drift, and high common mode rejection,
giving superior performance in applications where offset
nulling is undesirable. Increased slew rate without performance compromise is available through use of feedforward
compensation techniques, maximizing performance in high
speed sample-and-hold circuits and precision high speed
summing amplifiers. The wide supply range and excellent
supply voltage rejection assure maximum flexibility in voltage follower, summing, and general feedback applications. 6
•
•
•
•
•
FREQ
CaMP 2
yLead 4 connected to case.
Connection Diagram
10-Lead Flatpak
(Top View)
Guaranteed Low Input Offset Characteristics
High Input Impedance
Low Offset Current
Low Bias Current
Operation Over Wide Supply Range
10
NC
Connection Diagram
14-Lead DIP
(Top View)
-IN
FREQ
CaMPI
FREQ
NC
CQMP2
C:=::J-...J
v+
+INL"':"":...J-...J
OUT
NC
y-
14
NC
NC
FREQ
CQMPI
NC
NC
FREQ
CQMP2
-IN
v+
+IN
OUT
NC
NC
Order Information
Part No_
p.A 108ADMOB
p.A 108AHMOB
p.A 108AFMOB
Casel
Finish
CA
GC
HA
Package Code
MiI-M-38510, Appendix C
D-1 14-Lead DIP
A-1 8-Lead Can
F-4 10-Lead Flatpak
JAN Product Available
v-
10104
10104
10104
10104
10104
10104
HC
14-11
BCA
BCC
BGA
BGC
BHA
BHB
D-1
D-1
A-1
A-1
F-4
F-4
14-Lead DIP
14-Lead DIP
8-Lead Can
8-Lead Can
10-Lead Flatpak
10-Lead Flatpak
p.A.108AQB
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature 'Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation9
Can and Flatpak
DIP
Supply Voltage
Differential Input Voltage
Input Voltage 10. ..
Short Circuit Duration 11
Differential Input Current12
Processing: MIL-STD-883, Method 5004
-65°C to + 175°C
-55°C to +125°C
300°C
330 mW
400 mW
±22 V
±5.0 V
±20 V
Indefinite
±10 mA
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1..
2.
3.
4.
5.
6.
9.
10.
11.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
DynamiC tests at -55°C
AC tests at 25°C
AC tests at 125°C
AC tests at -55°C
Group C and 0 Endpoints: Group A, Subgroup .1
Notea
1.
2.
3.
4.
5.
6.
7.
8.
9.
10..
11.
12.
100% Test and Group A
Group A
.
Periodic. tests, Group C
Guaranteed but not tested
When changes occur, FSC will make data sheet revisions available.
Contact local saies representative for the latest revision.
For more information on device function, refer to the Fairchild Linear
Data Book Commerciai Section.
ZI is guarantaed by liB: ZI- 2[(VT/IIB) + l00lRe(lO-~I, VT - 26 mV at
25·C, Re - 170.0.
VIR is guaranteed by the CMR test.
Rating applies to ambient temperatures up fo 125·C. Above 125·C
arnbien~ derate lineerly at 15o.·C/W for the Can and Flalpak and
12o.·C/W for the DIP.
For Supply Voltages less than ±2O V, the absol~ maximum input
voltage is equal to the BUppIy voltage.
Short circuit may be to ground or e"her BUpply. Rating applies to
125·C caSe temperature or 75·C ambient temperature.
The inputs are shunted with back-to-back diodes for overvoltage
protection. Therefore, excessive current will flow if a· differential input
voltage in excess of 1.0. V is applied between the inputs' unless
adecjuata limiting resistance is used.
n.
14-12
p,A108AQB
1lA108AQB
Electrical Characteristics ± 5.0 V ~ Vee ~ ± 20V. unless otherwise specified.
Symbol
VIO
I1Vlo/l1T
Characteristic
Input Offset Voltage
Condition
Min
Rs=50 n, VCM=O V
Input Offset Voltage
Temperature Sensitivity
Max
Unit
Note
0.5
mV
1
1
Subgrp
1.0
mV
1
2,3
25°C';;; TA';;; 125°C
5.0
p'vrc
4
2
-55°C';;; TA';;; +25°C
5.0
p'vrc
4
3
0.2
nA
1
1
2,3
110
Input Offset Current
VCM =0 V
0.4
nA
1
11110/l1T
Input Offset Current
Temperature Sensitivity
25°C';;; TA';;; 125°C
2.5
pArc
4
2
-55°C';;; TA';;; +25°C
5.0
pArc
4
3
1.9
nA
1
1
3.0
nA
1
2,3
Mn
1
1
liB
Input Bias Current
ZI
Input Impedance7
Icc
Supply Current
VCM =0 V
30
0.6
mA
1
1,2
0.8
mA
1
3
96
dB
1
1,2,3
± 13.5
V
1
1,2,3
Vcc=±20 V
CMR
Common Mode Rejection
Vcc = ± 15 V,
VCM = ± 13.5 V,
Rs=50 n
VIR
Input Voltage RangeS
VCC=±15V
PSRR
Power Supply Rejection Ratio
±5.0 V';;;Vcc';;;±20 V,
Rs=50 n
16
p.VN
1
1,2,3
los
Output Short Circuit Current
Vcc=±15 V
15
mA
3
1,2,3
Avs
Large Signal Voltage Gain
Vcc=±15 V,
Vo=±10V,
RL = 10 kn
80
V/mV
1
4
VlmV
1
5,6
Vcc=±15 V,
RL = 10 kn
±13
V
1
4,5,6
1000
ns
3
9,10,11
50
0/0
3
9,10,11
Vlp.s
3
9,10,11
VOP
Output Voltage Swing
TR(t,)
Transient Response
Rise Time
Overshoot
TR(os>
40
Vcc=±20 V,
VI = 50 mY,
RL =2.0 kn,
CL = 100 pF, Av = 1.0
SR
Slew Rate
Vcc= ±20 V,
RL = 2.0 kn, Av = 1.0
NI (BB)
Noise Broadband
Vcc= ±20 V,
BW = 5.0 kHz
15
p.V,ms
4
9
NI (PC)
Noise Popcorn
Vcc=±20 V,
BW=5.0 kHz
40
/JVpk
4
9
14-13
0.05
~A108AQB
Primary Burn-In Circuit
(38510/10104 may be used by FSC as an alternate)
30 pF
1\
L....-- FREa
COMPl
~
FAEa
COMP2
-IN
Y+
+IN
OUT
-1r:- Y-
NC
t---
jY
t---
Equivalent Circuit
FREQ
FREa
co....
co. 1
r---------~~--~~_1--_.------~--_r--~------------------~~---------Y+
AS
R4
2D1--£:=:::1 OUT
LAG!
FREOCOMP
LEADI
v- - -..._ _ _ _.......,----- FREO COMP
Order Information
Part No.
~702HMQB
GC
~702FMQB
HA
CA
~702DMQB
14-55
Casel
Finish
Package Code
MiI-M-38510, Appendix C
A-l 8-Lead Can
F-4 10-Lead Flatpak
0-1 14-Lead DIP
J1A702QB
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 11
Can and Flatpak
DIP
Supply Voltage
Differential Input Voltage
Input Voltage 12
Peak Output Current
-65°C to + 175°C
-55°C to + 125°C
300°C
330 mW
400 mW
21 V
±5.0 V
+1.5 V to -6.0 V
50 rnA
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
Dynamic tests at -55°C
AC tests at 25°C
Group C and 0 Endpoints: Group A, Subgroup
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. ZI is guaranteed by liB: ZI = 2.0 VTIIIB, VT = 26 mV at 25'C, 34 mV at
125'C, and 19 mV at -55'C.
B. Pc, is guaranteed by Icc,: Pc, = (12 V)(lccl + (6.0 V)(lcc,).
9. VIR is guaranteed by the CMR test.
10. Pc2 is guaranteed by Icc.: Pc2 = (6.0 V)(ICC2) + (3.0 V)(lcc21·
11. Rating applies to ambient temperatures up to 125'C. Above 125'C
ambient, derate linearly at 150'C/W for the Can and Flatpak and
120'C/W for the DIP.
12. For supply voltage of 21 V.
Transient Response Test Circuits
Figure 1 Unity-Gain Amplifier
(Lag Compensation)
Figure 2 X100 Amplifier
(Lead Compensation)
2kCl
>-............-_Vo
14-56
JlA702QB
JlA702QB
Electrical Characteristics V+ = 12 V, V- = -6.0 V, unless otherwise specified.
Symbol
Characteristic
Condition
n,
Min
Max
Unit
Note
2.0
mV
1
1
mV
1
2,3
p.V/oC
4
2
p.V/oC
4
3
VIO
Input Offset Voltage
Rs = 50
3.0
t:Nlo/AT
Input Offset Voltage
Temperature Sensitivity
25°C < TA < 125°C
10
-55°C ---<0 OUT
-IN
•
•
•
•
•
•
•
•
Low Offset Voltage
Low Offset Voltage Drift
Low Bias Current
Low Input NOise Current
High Open Loop Gain
Low Input Offset Current
High Common Mode Rejection
Wide Power Supply Range
vLead 4 connected to case.
Order Information
Part No.
1lA714HMQ8
Casel
Finish
GC
Package Code
MiI-M-38510, Appendix C
A-1 8-Lead Can
•
14-67
J.lA714Q8
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering. 60 s)
Internal Power Dissipation 10
Can'
Supply Voltage
Differential Input Voltage
Input Voltage 11
Processing: MIL-STD-883, Method 5004
-65°C to + 175°C
-55°C to + 125°C
300°C
330 mW
±22 V
±30 V
±22 V
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
Static tests at
Static tests at
Static tests at
Dynamic tests
Dynamic tests
Dynamic tests
25°C
125°C
-55°C
at 25°C
at 125°C
at -55°C
Group C and D Endpoints: Group A, Subgroup 1
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur I FSC will make data sheet revisions available.
Contact loca1 sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
Pc1 is guaranteed by ICC1; Pc1 - 30 ICC1.
Pc2 is guaranteed by ICC2; Pc2 = 6 ICC2.
V,R is guaranteed by the CMR test.
Rating applies to ambient temperatures up to 125'C. Above 125'C
ambient, derate linearly at 150'C/W.
11. For supply voltages less than ±22 V, the absolute maximum input
vOltage is equal to the supply voltage.
7.
8.
9.
10,
14-68
fJA714QB
~A714QB
Electrical Characteristics Vee = ± 15 V, unless otherwise specified.
Symbol
Via
Characteristic
Input Offset Voltage
Condition
Min
Rs = 50 Q, VCM = 0 V
Max
Unit
Note
Subgrp
75
p.V
1
1
200
p.V
1
2,3
110
Input Offset Current
VCM =0 V
2.8
nA
1
1
5.6
nA
1
2,3
liB
Input Bias Current
VCM =0 V
3.0
nA
1
1
6.0
nA
1
2,3
1
ICC1
Supply Current
Vo=O V
4.0
mA
1
ICC2
Supply Current
VCC = ± 3.0 V, Va = 0 V
1.0
mA
1
1
Pc1
Power Consumption?
Vo=O V
120
mW
1
1
Pc2
Power ConsumptionS
Vcc = ± 3.0 V, Va = 0 V
6.0
1
CMR
Common Mode Rejection
VCM = ± 13 V, Rs = 50 Q
VIR
Input Voltage Range 9
PSRR
Power Supply Rejection Ratio
Avs
Large Signal Voltage Gain
Output Voltage Swing
1
dB
1
1
106
dB
1
2,3
1,2,3
± 13.0
V
1
10
p.VN
1
1
20
p.VN
1
2,3
200
V/mV
1
4
150
V/mV
1
5,6
150
V/mV
1
4
±3.0 V";;Vcc";;±18 V,
Rs = 50 Q
Va = ± 10 V, RL = 2.0 kQ
Vcc =±3.0 V, Vo =± 0.5 V,
RL = 500 Q
VoP
mW
110
RL = 10 kQ
± 12.5
V
1
4
RL = 2.0 kQ
± 12.0
V
1
4,5,6
RL = 1.0 kQ
± 10.5
V
1
4
14-69
J.tA714QB
Primary Burn-In Circuit
-
+OFFSET
NULL
-OFFSET
NULL
r--15 V
~
r--
-IN
V+
+IN
OUT
V-
NC
I
I--
-15 V
Equivalent Circuit
RIA
R1B
+IN
-IN
R3
"I
029
as~Q6~~~~6
07
M~~
;
R12
09
Q28(~
~
riLl
+OF~~~_ -OF~~~~ _
Cl
C2
Q34~019
~C31~ ~
~~
R9
016
f0~
OUT
RIO
~
~
J 02
J
R5
1'1
R23
R24
')~2
~.
R16
R7
010)-
I
p'
V+
.)
0301.,.
R2B (NOTE 1)
R2A (NOTE 1)
L<039
;::L.KQ44
1 015
03~
0.3
R17
032
R18
03'
R21
...
",020
~5
018
R8
R.9
038>
R14
R13
R15
040
035>-
R26
R20
R25
V-
Note
1. R2A and R2B are electronically adjusted on a chip at the factory for
minimum offset voltage.
14-70
J.lA71SQ8
High Speed
Operational Amplifier
FAIRCHIL.D
A Schlumberger Company
MIL-STD-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
10-Lead Can
(Top View)
The p.A715QB is a high speed, high gain, monolithic operational amplifier constructed using the Fairchild Planar Epitaxial process. It is intended for use in a wide range of
applications where fast signal acquisition or wide bandwidth is required. The p.A715QB features fast settling time,
high slew rate, low offsets and high output swing for large
signal applications. In addition, the device displays excellent temperature stability and will operate over a wide
range of supply voltages. The p.A715QB is ideally suited
for use in AID and 01 A converters, active filters, deflection amplifiers, video amplifiers, phase-locked loops.. multiplexed analog gates, precision comparators, sample-andholds, and general feedback applications requiring DC wide
bandwidth operation. 6
•
•
•
•
•
y-
Lead 5 connected to case.
High Slew Rate
Fast Settling Time
Wide Bandwidth
Wide Operating Supply Range
Wide Input Voltage Ranges
Order Information
Part No.
p.A715HMQB
14-71
Casel
Finish
IC
Package Code
MII-M-38510, Appendix C
A-2 10-Lead Can
JlA715QB
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power DiSSipation9
Can
Supply Voltage
Differential Input Voltage
Input Voltage 10
-65°C to + 175°C
-55°C to + 125°C
300°C
350 mW
±18 V
±15 V
±15 V
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
Dynamic tests at -55°C
AC tests at 25°C
Group C and D Endpoints: Group A, Subgroup 1
N_
1.
2.
3.
4.
5.
6.
7.
6.
9.
10.
100% Test and Group A
Group A
Periodic tests, Group C
Guaranteed but not tested
When changes occur, FSC will make data shea! revisions available.
Contact local sales representative for the latest revision.
For more information on device function, refer to the Fairchild Unear
Data Book Commercial Section.
Pc is guansnteed by Icc: Pc - 30 Icc.
VIR is guaranteed by the CMR test.
Rating applies to ambient temperatures up to 125'C. Above 125'C
ambien~ derate linearly at 140'C/W.
For supply voltages le99 than ± 15 V, the absolute maximum input
voltage is equal to the supply voltage.
14-72
MA71SQ8
~715QB
Electrical Characteristics Vee = ± 15 V, unless otherwise specified.
Symbol
Via
Characteristic
Input Offset Voltage
Condition
Rs = 50
n,
Min
VCM = 0 V
Max
Unit
Note
Subgrp
5.0
mV
1
1
7.5
mV
1
2,3
1'0
Input Offset Current
VCM =0 V
250
nA
1
1,2
800
nA
1
3
I'B
Input Bias Current
VCM =0 V
750
nA
1
1,2
4.0
3
IJA
1
Icc
Supply Current
7.0
mA
1
1
Pc
Power Consumption 7
210
mW
1
1
CMR
Common Mode Rejection
1,2,3
VIR
Input Voltage RangeS
PSRR
Power Supply Rejection Ratio
±7.0 V~Vcc~±18 V,
Rs=10 kn
Avs
Large Signal Voltage Gain
Vo=±10 V, RL = 2.0
VOP
Output Voltage Swing
TR(t,)
Transient
Response
TR(os)
SR
Slew Rate
I Rise Time
I Overshoot
VCM = ± 10 V, Rs = 10
RL = 2.0
kn
kn
kn
74
dB
1
±10
V
1
1,2,3
p.VlV
1
1,2,3
15
V/mV
1
4
10
VlmV
1
5,6
V
1
4,5,6
60
ns
2
9
40
%
2
9
Vlp.s
2
9
300
±10
V, = 400 mV, Av = 1.0
Av= 1.0
15
•
14-73
#lA71SQB
Primary Burn-In Circuit
COMP 11
CaMP lA
CASCaDE
CaMP 2B
30V
.----i-IN
t-----I+IN
t-----Iv-
V+ t - - - -...
COMP fA
OUT
Equivalent Circuit
r--------.----.------~-----~--~--~~--r_--~-v+
R24
10 kn
R7
COMPIA
400n
R20
son
R21
OUT
25 kn
-IN
R2
Rl
400n
an
R27
son
+IN
~~~~~m-~~--------------------1(Q9
R22
300U
R23
3 IeIl
R25
75 U
L-__~----~--------------------~----_+----~----~--~
14-74
FAIRCHILD
A Schlumberger Company
J,lA725AQB
Instrumentation
Operational Amplifier
MIL-STD-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
a-Lead Can
(Top View)
The JJA725AQB is a monolithic instrumentation operational
amplifier constructed using the Fairchild Planar Epitaxial
process. It is intended for precise, low level signal amplification applications where low noise, low drift and accurate
closed loop gain are required. The offset null capability,
low power consumption, very high voltage gain as well as
wide power supply voltage range provide superior performance for a wide range of instrumentation applications. The
JJA725AQB is lead compatible with the popular JJA741AQB
operational amplifier. 6
•
•
•
•
•
•
•
•
Low Input Noise Current
High Open Loop Gain
Low Input Offset Current
Low Input Voltage Drift
High Common Mode Rejection
High Input Voltage Range
Wide Power Supply Range
Offset Null Capability
-OFFSET
NULL
vLead 4 connected to case.
Order Information
Part No.
JJA725AHMQB
14-75
Casel
Finish
GC
Package Code
MII-M-38510, Appendix C
A-1 8-Lead Can
MA725AQB
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 10
Can
Supply Voltage
Differential Input Voltage
Input Voltage 11
Voltage Between Offset Null and V+
Short Circuit Duration 12
Processing: MIL-STD-883, Method 5004
-65°C to + 175°C
-55°C to + 125°C
300°C
330 mW
±22 V
±5.0 V
±22 V
±0.5 V
Indefinite
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
Dynamic tests at -55°C
AC tests at 25°C
Group C and D Endpoints: Group A, Subgroup 1
Notes
1. 100% Test and Group A
2. Group A
3. Periodic _ , Group C
4. Guaranteed but not tested
S. When changes occur, FSC will make data sheet revisions available.
Contect local seles representative for the latest revision.
6. For more information on device function, refer to the Fairchild Unear
Data Book Commercial Section.
7. Pel is guaranteed by ICC1 : Pel - 30 ICC1 '
8. Pc2 is guaranteed by ICC2: Pc2 = 6.0 ICC2.
9. VIR is guaranteed by the CMR test.
10. Rating applies to ambient temperatures up to 12S"C. Above 12S"C
ambient, derate linearly at 150"C/W.
11. For supply voltages less than ± 22 V, the absolute maximum input
voltage is equal to the supply voltage.
12. Short circuit may be to ground or either supply. Rating applies to
12S"C case temperature or 7S"C ambient temperature.
14-76
MA725AQB
}lA725AQB
Electrical Characteristics Vee = ± 15 V, unless otherwise specified.
Symbol
VIO
flVlolflT
110
Characteristic
Condition
1
1
1
2,3
2.0
p'vrc
4
2
-55°C ~ TA ~ +25°C
5.0
p'vrc
4
3
VCM = 0 V
5.0
nA
1
1
4.0
nA
1
2
18
nA
1
3
90
pArc
4
2
-55°C ~TA ~ +25°C
90
pArc
4
3
VCM = 0 V
75
nA
1
1
70
nA
1
2
Input Offset Current
ICCl
Supply Current
ICC2
Supply Current
~TA ~
125°C
25°C ~TA ~ 125°C
Pel
Pe2
Power ConsumptionS
Vcc = ±3.0 V
CMR
Common Mode Rejection
VCM=±13.5 V, Rs=50 n
VIR
Input Voltage Range9
PSRR
Power Supply Rejection Ratio
±5.0 V~Vcc~±22 V,
Rs= 50 n
Avs
Large Signal Voltage Gain
Vo= ±10 V, Rl = 2.0 kn
Output Voltage Swing
180
nA
1
3
4.0
I11A
1
1
1.0
mA
1
1
120
mW
1
1
6.0
mW
1
1
120
dB
1
1
110
dB
1
2,3
± 13.5
V
1
1,2,3
p.VIV
1
1
Vcc = ±3.0 V
Power Consumption 7
VOP
Subgrp
mV
25°C
Input Bias Current
Note
mV
Input Offset Voltage
Temperature Sensitivity
(Without External Trim)
lis
Unit
0.5
Rs = 50 n, VCM = 0 V
Input Offset Current
Temperature Sensitivity
Max
0.75
Input Offset Voltage
(Without External Trim)
flldflT
Min
5.0
p.VIV
1
2,3
1000
V/mV
1
4,5
500
V/mV
1
6
8.0
Rl = 10 kn
±12.5
V
1
4
RL = 2.0 kn
±10
V
1
5,6
nV/v'HZ
4
9
No
Noise Voltage
f = 10 Hz
100 Hz ~ 1 ~ 1.0 kHz
12
nV/v'HZ
4
9
NI
Noise Current
f = 10 Hz
1.2
pA/v'HZ
4
9
1=100 Hz
0.6
pAlv'HZ
4
9
f = 1.0 kHz
0.25
pA/v'HZ
4
9
15
14-77
•
MA725AQB
Primary Burn-In Circuit
+OFFSET
NULL
-OFFSET
NULL
30 V
V+
,------I-IN
OUT
.....- - - - -... +IN
~----_fv-
1--____-1
FREQ
COMP
Equivalent Circuit
r--~r---1----1----~---~----~----~----t-----t----~-----~-Y+
R15
18 k!l
+IN
OUT
026
-IN--+--_____...J
R1.
4.Skn
L------------~~
__
~----~
__ __--__
~
~~~~~~
14-78
_______
R12
lkH
R13
15()O
~--~--
R14
__ 300n
______
~
~v-
p.A72SQ8
FAIRCHIL.D
A Schlumberger Company
Instrumentation
Operational Amplifier
MIL-STD-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
8-Lead Can
(Top View)
The /lA 7250B is a monolithic instrumentation operational
amplifier constructed using the Fairchild Planar Epitaxial
process. It is intended for precise, low level signal amplification applications where low noise, low drift and accurate
closed loop gain are required. The offset null capability,
low power consumption, very high voltage gain as well as
wide power supply voltage range provide superior performance for a wide range of instrumentation applications. The
/lA7250B is lead compatible with the popular /lA7410B
operational amplifier. 6
•
•
•
•
•
•
•
•
-OffSET
NULL
Low Input Noise Current
High Open Loop Gain
Low Input Offset Current
Low Input Voltage Drift
High Common Mode Rejection
High Input Voltage Range
Wide Power Supply Range
Offset Null Capability
y-
Lead 4 connected to case.
Order Information
Part No.
/lA725HMOB
Casel
Finish
OC
Package Code
Mil-M-38510, Appendix C
A-1 8-Lead Can
•
14-79
JlA725Q8
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 9
Can
Supply Voltage
Differential Input Voltage
Input Voitage 10
Voltage Between Offset Null and V+
Short Circuit Duration 11
-65°C to + 175°C
-55°C to + 125°C
300°C
330 mW
±22 V
±5.0 V
±22 V
±0.5 V
Indefinite
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
Static tests at 25°C
Static tests at 125°C
Static tests at - 55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
DynamiC tests at -55°C
9. AC tests at 25°C
Group C and D Endpoints: Group A, Subgroup
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild linear
Data Book Commercial Section.
7. Pc is guaranteed by Icc: Pc ~ 30 Icc.
8. V,R is guaranteed by the CMR test.
9. Rating applies to ambient temperatures up to 125·C. Above 125·C
ambient, derate linearty at 150·C/W.
10. For supply voltages less than ± 22 V, the absolute maximum input
voltage is equal to the supply voltage.
11. Short circuit may be to ground or either supply. Rating applies to
125°C case temperature or 75°C ambient temperature.
14-80
}lA725QB
IlA725Q8
Electrical Characteristics Vee = ± 15 V, unless otherwise specified.
Symbol
Characteristic
Condition
n,
Min
Max
1.0
Unit
Note
mV
1
Subgrp
VIO
Input Offset Voltage
(Without External Trim)
Rs = 50
1.5
mV
1
2,3
AVIO/AT
Input Offset Voltage
Temperature Sensitivity
(Without External Trim)
25°C';; TA';; 125°C
5.0
jJ.V/oC
4
2
-55°C';; TA';; +25°C
7.0
jJ.V/oC
4
3
Input Offset Current
VCM =0 V
20
nA
1
1,2
40
nA
1
3
150
pAloC
4
2
-55°C ';;TA';; +25°C
150
pAloC
4
3
VCM =0 V
100
nA
1
1,2
200
nA
1
3
110
AIIO/AT
Input Offset Current
Temperature Sensitivity
lis
Input Bias Current
VCM = 0 V
25°C';; TA';; 125°C
1
Icc
Supply Current
4.0
mA
1
1
Pc
Power Consumption?
120
mW
1
1
CMR
Common Mode Rejection
110
dB
1
1
100
dB
1
2,3
1,2,3
VIR
PSRR
VCM=±13.5 V, Rs=50
n
Input Voltage RangeS
Power Supply Rejection Ratio
± 13.5
V
1
10
jJ.VN
1
1
20
jJ.VN
1
2,3
1000
V/mV
1
4,5
±5.0 V';;Vcc';;±22 V,
Rs= 50 n
Avs
Large Signal Voltage Gain
Vo=±10V, RL = 2.0
VOP
Output Voltage Swing
RL = 10
kn
RL = 2.0 kn
14·81
kn
250
V/mV
1
6
±12
V
1
4
±10
V
1
4,5,6
•
/lA72SQ8
Primary Burn-In Circuit
+OFFSET
NULL
-OFFSET
NULL
30V
.-------1 -IN
....- - - - - - 1
V+I------'
OUT
+IN
""'-----1 V-
FREQ
COMP
Equivalent Circuit
r---~-~~--~---~---~----~----~----t-----t-----t-----~-V+
I
I
R2A
+
-"""r
10k!!
+ OFFSET
NULL
R1A
42 kU
100 kO
EXTERNAL
R2B
10kH
R3
29 kH
-OFFSET
NULL
R1B
42 ktl
R16
25 !l
+IN
OUT
t----1i::
-IN
026
--+---------'
Jr----+---~~~_i~~-_i~~-+_----+_~017
R6
5.1 kH
R8
2.4 kn
L-____________~____~----~--+_--
____
R18
5.1 kll
~~~~--------
14-82
R12
1 kO
__ __
~
R13
150 Jl
R14
300 !I
~--~------~-~
JlA741AQ8
Operational Amplifier
F=AIRCHILO
A Schlumberger Company
MIL-STD-883
July 1986-Rev 25
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
8-Lead Can
(Top View)
The J.lA741AQB is a high performance monolithic operational amplifier constructed using the Fairchild Planar Epitaxial process. It is intended for a wide range of analog
applications. High common mode voltage range and absence of latch-up tendencies make the IlA741 AQB ideal
for use as a voltage follower. The high gain and wide
range of operating voltage provide superior performance in
integrator, summing amplifier, and general feedback applications. 6
Ne
>-....:..c;.> OUT
-IN
•
•
•
•
No Frequency Compensation Required
Short Circuit Protection
Offset Voltage Null Capability
Large Common Mode And Differential Voltage
Ranges
• Low Power Consumption
• No Latch-Up
vLead 4 connected to case.
Connection Diagram
8-Lead DIP
(Top View)
Connection Diagram
10-Lead Flatpak
(Top View)
Ne
Ne
+OFFSET
NULL
Ne
_INr----......J
+OFFSET
NULL
NC
-IN
v+
+IN
OUT
v+
v- - - - , ._ _ _ _ _. r - -
-OFFSET
NULL
v-
YC:::C:::J OUT
+IN
-OFFSET
NULL
c000761F
Order Information
Connection Diagram
14-Lead DIP
(Top View)
Casel
Finish
NC
NC
Part No.
IlA741ADMQB
IlA741AHMQB
!1A741AFMQB
IlA741ARMQB
NC
Ne
JAN Product Available
+QFFSET
NULL
NC
-IN
v+
+IN
OUT
,.
vNe
10101
10101
10101
10101
10101
10101
10101
10101
-OFFSET
NULL
He
14-83
CA
GC
HA
PA
BCA
BCB
BGA
BGC
BHA
BHB
BPA
BPB
Package Code
MiI-M-38510, Appendix C
D-1 14-Lead DIP
A-1 8-Lead Can
F-4 10-Lead Flatpak
D-4 8-Lead DIP
D-1
D-1
A-1
A-1
F-4
F-4
D-4
D-4
14-Lead DIP
14-Lead DIP
8-Lead Can
8-Lead Can
10-Lead Flatpak
10-Lead Flatpak
8-Lead DIP
8-Lead DIP
MA741AQ8
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 11
Can and Flatpak
DIP
Supply Voltage
Differential Input Voltage
Input Voltage 12
Short Circuit Duration 13
-65°C to + 175°C
-55°C to +125°C
300°C
330 mW
400 rnW
±22 V
±30 V
±20 V
Indefinite
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
10.
11.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
Dynamic tests at -55°C
AC tests at 25°C
AC tests at 125°C
AC tests at -55°C
Group C and 0 Endpoints: Group A, Subgroup
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. Z, is guaranteed by I'B: Z, - 4.0 VTIi'B, VT = 26 mV at 25°C, 34 mV at
125°C and 19 mV at -55°C.
B. Pc is guaranteed by Icc: Pc = 40 Icc.
9. V'R is guaranteed by the CMR test.
10. BW is guaranteed by t,: BW = 0.35/t,.
11. Rating applies to ambient temperatures up to 125°C. Above 125°C
ambient, derate linearly at lSOoC/W for the Can and Flatpak and
120°C/W for the DIP.
12. For supply voltages less than ± 20 V, the absolute maximum input
voltage is equal to the supply voltage.
13. Short circuit may be to ground or either supply. Rating applies to
125°C case temperature or 75°C ambient temperature.
14-84
MA741AQ8
/lA741AQ8
Electrical Characteristics Vee =
Symbol
Via
t:J.Vlolt:J.T
± 15
V, unless otherwise specified.
Max
Unit
Note
3.0
mV
1
1
4.0
mV
1
2,3
25°C <;TA <; 125°C
15
INloC
4
2
-55°C <;TA <; +25°C
15
pV 1°C
4
3
mV
1
1,2,3
Characteristic
Input Offset Voltage
Condition
Input Offset Voltage
Temperature Sensitivity
Via adi
Input Offset Voltage Adjustment
Range
Vcc=±20 V
110
Input Offset Current
VCM = 0 V
t:J.llolt:J.T
118
ZI
Icc
Pc
Input Offset Current
Temperature Sensitivity
Input Bias Current
5.0
30
nA
1
1
nA
1
2,3
25°C <; TA <; 125°C
0.5
nA/oC
4
2
-55°C <; TA <; +25°C
0.5
nAloC
4
3
80
nA
1
1
210
nA
1
2,3
1.0
Mn
1
1
0.5
Mn
1
2
VCM =0 V
Input Impedance7
Supply Current
Vcc=±20 V
Power ConsumptionS
Vcc=±20 V
Common Mode Rejection
Vec=±20 V, VCM=±15 V,
Rs=50 n
VIR
Input Voltage Range 9
Vee = ±20 V
PSRR
Power Supply Rejection Ratio
V+ = 10 V, V- = -20 V to
V+ = 20 V, V- = -10 V,
Rs = 50 n
los
Output Short Circuit Current
Avs
Large Signal Voltage Gain
TR(tr)
Transient Response
TR(os)
Vee=±20 V
I Rise Time
I Overshoot
3.750
mA
1
1
3.375
mA
1
2
4.125
mA
1
3
150
mW
1
1
135
mW
1
2
165
mW
1
3
80
dB
1
1,2,3
±15
V
1
1,2,3
50
pVIV
1
1
100
pV/V
1
2,3
mA
1
1,2,3
50
V/mV
1
4
32
V/mV
1
5,6
10
V/mV
1
4,5,6
±16
V
1
4,5,6
±15
V
1
4,5,6
ns
3
9,10,11
60
Vee=±20 V, Vo=±15 V,
RL = 2.0 kn
Vee = ± 5.0 V, Va = ± 2.0 V,
RL = 2.0 kn
Output Voltage Swing
Subgrp
70
CMR
VoP
Min
Rs= 50 n,
VCM = 0 V
I RL = 10 kn
I RL = 2.0 kn
Vee = ± 20 V, VI = 50 mY,
RL = 2.0 kn, CL = 100 pF,
Av = 1.0
800
%
3
9,10,11
0.437
25
MHz
3
9,10,11
0.3
Vips
3
9,10,11
pVrms
4
9
pVpk
4
9
BW
Bandwidth 10
SR
Slew Rate
Vee = ±20 V, RL = 2.0 kn,
Av = 1.0
NI (BB)
Noise Broadband
Vee=±20 V, BW=5.0 kHz
15
NI (PC)
Noise Popcorn
Vee = ±20 V, BW = 5.0 kHz
40
14-85
pA741AQB
Primary Burn-In Circuit
(38510/10101 may be used by FSC as an alternate)
-
+OFFSET
NULL
-
NC
15V
*
r-
-IN
V+
+IN
OUT
I
-
-OFFSET
NULL
V-
-15 V
Equivalent Circuit
-IN
r1~------i-----~------~~--------~---.--------------------~-V+
R6
+IN
27
n
OUT
R7
22 n
+OFFSET
NULL
Rl
lkn
R3
50kn
Rll
50 kn
R2
1 kn
L---~~~~--~---+------
__
~
__
~
____-4__-+____
-OFFSET
NULL
14-86
~
____-+__
~~~~v_
p.A741Q8
I=AIRCHILO
Operational Amplifier
A Schlumberger Company
MIL-STD-883
July 1986-Rev 25
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
8-Lead Can
(Top View)
The J.LA 741 QB is a high performance monolithic operational
amplifier constructed using the Fairchild Planar Epitaxial
process. It is intended for a wide range of analog applications. High common mode voltage range and absence of
latch-up tendencies make the J.LA741QB ideal for use as a
voltage follower. The high gain and wide range of operating voltage provide superior performance in integrator,
summing amplifier, and general feedback applications. 6
Ne
-IN
•
•
•
•
No Frequency Compensation Required
Short Circuit Protection
Offset Voltage Null Capability
Large Common Mode And Differential Voltage
Ranges
• Low Power Consumption
• No Latch-Up
Connection Diagram
10-Lead Flatpak
(Top View)
>---QOUT
vLead 4 connected to case.
Connection Diagram
8-Lead DIP
(Top View)
NC
NC
+OFFSET
NULL
+OFFSET
NUll.
NC
-IN
v+
V+
+IN
OUT
-IN
+IN
v-
C:=:::J-.J
C:=:::J-.J
Y==JOUT
-OFFSET
NULL
v-
-OFFSET
----~__________~----NULl.
Connection Diagram
14-Lead DIP
(Top View)
Order Information
Part No.
J.LA741DMQB
JJA741HMQB
J.LA741FMQB
JJA741RMQB
14
NC
NC
NC
NC
+OFFSET
NUll.
NC
-IN
V+
+IN
OUT
vNC
Casel
Finish
CA
GC
HA
PA
JAN Product Available
10101
BCA
10101
BCB
10101
BGA
10101
BGC
10101
BHA
10101
BHB
10101
BPA
10101
BPB
-OFFSET
NULL
NC
COO2{l20F
14-87
Package Code
MiI-M-38510, Appendix C
D-1 14-Lead DIP
A-1 8-Lead Can
F-4 10-Lead Flatpak
D-4 8-Lead DIP
D-1
D-1
A-1
A-1
F-4
F-4
D-4
D-4
14-Lead DIP
14-Lead DIP
8-Lead Can
8-Lead Can
10-Lead Flatpak
10-Lead Flatpak
8-Lead DIP
8-Lead DIP
J.lA741Q8
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 11
Can and Flatpak
DIP
Supply Voltage
Differential Input Voltage
Input Voltage 12
Short Circuit Duration 13
Processing: MIL-STD-883, Method 5004
-65°C to + 175°C
-55°C to + 125°C
300°C
330 mW
400 mW
±22 V
±30 V
±20 V
Indefinite
Burn-In: Method 101.5, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
10.
11.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
Dynamic tests at -55°C
AC tests at 25°C
AC tests at 125°C
AC tests at -55°C
Group C and 0 Endpoints: Group A, Subgroup
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. Z, is guranteed by I'B: Z, ~ 4.0 VT/I'B, VT ~ 26 mV at 2S'C, 34 mV at
12S'C and 19 mW at - SS·C.
8. Pc is guaranteed by Icc: Pc = 30 Icc
9. V'R is guaranteed by the CMR test.
10. BW is guaranteed by t,: BW ~ 0.3S/t,.
11. Rating applies to ambient temperatures up to 12S·C. Above 12S'C
ambient, derate linearly at lS0'C/W for the Can and Flatpak and
120'C/W for the DIP.
12. For supply voltages less than ± 20 V, the absolute maximum input
voltage is equal to the supply voltage.
13. Short circuit may be to ground or either supply. Rating applies to
125°C case temperature or 75°C ambient temperature.
14-88
J,tA741Q8
J,!A741Q8
Electrical Characteristics Vee = ± 15 V, unless otherwise specified.
Symbol
Max
Unit
Note
5.0
mV
1
1
mV
1
2,3
/lVrC
4
2
/lVrC
4
3
mV
1
1,2,3
200
nA
1
1,2
500
nA
1
3
25°C ';;;TA';;; 125°C
1.0
nArC
4
2
-55°C';;; TA';;; +25°C
1.0
nArC
4
3
340
nA
1
1
500
nA
1
2
3
Characteristic
Condition
Min
VIO
Input Offset Voltage
50 n,;;;Rs';;;10 kn, VCM=O V
6.0
tl.Vloltl.T
Input Offset Voltage
Temperature Sensitivity
25°C ';;;TA';;; 125°C
15
-55°C ';;;TA';;; + 25°C
15
VIO
adj
110
tl.1 101 tl.T
118
Input Offset Voltage
Adjustment Range
Vcc=±20 V
Input Offset Current
VCM=O V
Input Offset Current
Temperature Sensitivity
Input Bias Current
5.0
VCM =0 V
1500
ZI
Icc
Pc
CMR
VIR
PSRR
Input Impedance7
nA
1
0.3
Mn
1
1
0.2
Mn
1
2
2.8
mA
1
1
2.5
mA
1
2
3.3
mA
1
3
85
mW
1
1
75
mW
1
2
100
3
Supply Current
Power ConsumptionS
Common Mode Rejection
Input Voltage Range9
VCM=±12 V, Rs=50 n
Power Supply Rejection
Ratio
±5.0 V';;;Vcc';;;±22 V, Rs = 50 n
mW
1
70
dB
1
1,2,3
±12
V
1
1,2,3
IlVN
1
1,2,3
150
los
Output Short Circuit Current
Avs
Large Signal Voltage Gain
Va = ± 10 V, RL = 2.0 kn
VOP
Output Voltage Swing
RL = 10 kn
±12
RL =2.0 kn
±10
TR(t,)
TR(os)
Transient
Response
I Rise Time
I Overshoot
mA
1
1,2,3
50
V/mV
1
4
25
V/mV
1
5,6
V
1
4,5,6
V
1
4,5,6
800
ns
3
9,10,11
25
%
3
9,101
0.437
MHz
3
9,101
0.3
V/IlS
3
9,101
IlV,ms
4
9
/lVpk
4
9
60
Vee = ±20 V, VI = 50 mY,
RL = 2.0 kn, CL = 100 pF, Av = 1.0
BW
Bandwidth 10
SR
Slew Rate
NI (BB)
Noise Broadband
Vce = ± 20 V, BW = 5.0 kHz
15
NI (PC)
Noise Popcorn
Vee = ±20 V, BW = 5.0 kHz
40
Vcc = ±20 V, RL = 2.0 kn,
Av = 1.0
14-89
Subgl"J
1lA741Q8
!»rimary Burn-In Circuit
:38510/10101 may be used by FSC as an alternate)
-
+OFFSET
NU~~
Ne ~
15V
~
r-
-IN
V+
+IN
OUT
I
-OFFSET
v-
~
N~~
-1SV
CA05190F
Iquivalent Circuit
-IN
r1~---------;-------t----------~~------------~---~~----------------------------t--V+
R6
+IN
270
OUT
R7
220
+OFFSET
NULL
Rl
1kO
R3
SOkO
R11
R2
1 kO
50 kO
L..---~~~~---+-----4------------~---~------~
-OFFSET
NULL
14-90
__-4______~______-4___~~___~v_
#lA747AQ8
Dual
Operational Amplifier
FAIRCHILD
A Schlumberger Company
MIL-STD-883
July 1986-Rev 25
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
10-Lead Can
(Top View)
The #lA747AQB is a pair of high performance monolithic
operational amplifiers constructed using the Fairchild Planar
Epitaxial process. They are intended for a wide range of
analog applications where board space or weight are important. High common mode voltage range and absence
of latch-up make the #lA747AQB ideal for use as a voltage follower. The high gain and wide range of operating
voltage provide superior performance in integrator, summing amplifier, and general feedback applications.
Ne
The /lA747AQB is short circuit protected and requires no
external components for frequency compensation. The internal 6 dB/octave roll-off insures stability in closed loop
applications. 6
y-
Lead 5 connected to case.
•
•
•
•
No Frequency Compensation Required
Short Circuit Protection
Offset Voltage Null Capability
Large Common Mode and Differential Voltage
Ranges
• Low Power Consumption
• No Latch-Up
Connection Diagram
14-Lead Flatpak
(Top View)
+INA'
y-
'--1L..=:J OUT A
y-
NC
-OFFSET
NULLa
-IN A
-OFFSET
NULL A
......C=:J OUT a
+IN a
C::=::J-....I_.J
-IN a
[==t:~:""
OUT A
NC
Order Information
Casel
Finish
Part No.
Package Code
MiI-M-38510, Appendix C
F-1 14-Lead Flatpak
0-1 14-Lead DIP
A-2 10-Lead Can
+IN B
Y+ a
-IN a
+ OFFSET
NULL a
JAN Product Available
NULL B
V+B
__...J==J NULL
+OFFSET
a
V+ A
#lA747AFMQB
#lA747ADMQB
#lA747AHMQB
-OFFSET
Y+A
'--
-OFFSET
NULLA
Connection Diagram
14-Lead DIP
(Top View)
+IN A
+OFFSET
NULLA
-INA,-_....r...,
OUT a
10102
10102
10102
10102
10102
10102
COOO781F
14-91
AA
CA
IC
BAA
BAB
BCA
BCB
BIA
BIC
F-1
F-1
0-1
0-1
A-2
A-2
14-Lead Flatpak
14-Lead Flatpak
14-Lead DIP
14-Lead DIP
10-Lead Can
10-Lead Can
MA747AQB
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 12
Can and Flatpak
DIP
Supply Voltage
Differential Input Voltage
Input Voltage 13
Short Circuit Duration 14
-65°C to + 175°C
-55°C to + 125°C
300°C
350 mW
400 mW
±22 V
±30 V
±20 V
Indefinite
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
10.
11.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
Dynamic tests at -55°C
AC tests at 25°C
AC tests at 125°C
AC tests at -55°C
Group C and D Endpoints: Group A, Subgroup 1
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
S. When changes occur, FSC will make date sheet revisions availeble.
Contee! local sales representetive for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Date Book Commercial Section.
7. Not availeble on /AA747AHMQB.
8. ZI is guaranteed by liB: ZI = 4.0 VT/IIB, VT = 26 mV at 2S·C, 34 mV at
12S·C, and 19 mV at -SS·C.
9. Pc is guaranteed by Icc: Pc = 40 Icc.
10. VIR is guaranteed the CMR test.
11. BW is guaranteed by t,: BW = 0.3S/t,..
12. Rating applies to ambient temperatures up to 12S·C. Above 12S·C
ambient, derate linearly at 140·C/W for the can and Flatpak and
120·C/W for the DIP.
13. For supply vonages less than ± 20 V, the absolute maximum input
voltege is equal to the supply voltege.
14. Short circuR may be to ground or eRher supply. Rating applies to
12S·C case temperature or 7S·C ambient temperature.
14-92
J.LA747AQ8
/-LA747AQB
Electrical Characteristics ± 5.0 V
Symbol
VIO
t!.Vlolt!.T
« Vee « ± 20
V, unless otherwise specified.
Characteristic
Input Offset Voltage
Condition
Rs = 50 kn,
VCM = 0 V
Input Offset Voltage
Temperature Sensitivity
25°C ~TA
~
Input Offset Voltage Adjustment
Range?
Vcc= ±20 V
110
Input Offset Current
VeM = 0 V
lis
Input Offset Current
Temperature Sensitivity
Input Bias Current
125°C
-55°C ~TA ~ +25°C
VIO adi
t!.llolt!.T
Min
25°C
~ TA ~
-55°C ~TA
125°C
+25°C
VCM = 0 V
Input Impedance8
Vee=±20 V
Icc
Supply Current (Total)
Vec=±20 V
Unit
Note
3.0
mV
1
1
4.0
mV
1
2,3
15
/-LVrC
4
2
15
/lV/oC
4
3
mV
1
1,2,3
5.0
~
ZI
Max
30
nA
1
1
70
nA
1
2,3
0.2
nA/oC
4
2
0.5
nAloC
4
3
80
nA
1
1
210
nA
1
2,3
Mn
1
1
2
1.0
Mn
1
7.50
mA
1
1
6.75
mA
1
2
8.25
mA
1
3
300
mW
1
1
270
mW
1
2
330
mW
1
3
dB
1
1,2,3
0.5
Pc
CMR
Power Consumption (Total)9
Common Mode Rejection
VIR
Input Voltage Range 10
PSRR
Power Supply Rejection Ratio
Vec=±20 V
Vec=±20 V, VCM=±15 V,
Rs=50 n
±15
los
Output Short Circuit Current
Avs
Large Signal Voltage Gain
TR(t,)
TR(os)
BW
Output Voltage Swing
Transient
Response
Vee=±20 V
Rise Time
Overshoot
V
1
1,2,3
50
/lVIV
1
1
100
/lV/V
1
2,3
60
Vee=±20 V, Vo=±15 V,
RL = 2.0 kn
Vec=±5 V, Vo =±2 V,
RL = 2.0 kn
VOP
80
V+ =10 V, V-=-20 V to
V+ = 20 V, V- = -10 V,
Rs= 50 n
I RL=10 kn
I RL = 2.0 kn
mA
1
1,2,3
V/mV
1
4
32
V/mV
1
5,6
10
V/mV
1
4,5,6
±16
V
1
4,5,6
±15
V
1
4,5,6
800
ns
3
9, 10, 1
25
%
3
9, 10, 1
MHz
3
9, 10, 1
50
Vee = ±20 V, VI = 50 mV,
RL = 2.0 kn, CL = 100 pF,
Av = 1.0
Bandwidth 11
0.437
14-93
Subgrp
J.LA747AQB (Cont.)
Electrical Characteristics ± 5.0 V';;;; Vee';;;; ± 20 V, unless otherwise specified.
Symbol
Characteristic
Condition
Min
Max
Unit
Note
Subgrp
VIIlS
3
9,10,1
SR
Slew Rate
Vee = ±20 V, RL = 2.0 kQ,
Av = 1.0
0.3
CS
Channel Separation
Vee=±20 V
100
dB
1
9, 10, 1
NI (BB)
Noise Broadband
Vee = ± 20 V, BW = 5.0 kHz
15
IlVrms
4
9
NI (PC)
Noise Popcorn
Vee = ± 20 V, BW = 5.0 kHz
40
IlVpk
4
9
Primary Burn-In Circuit
(38510/10102 may be used by FSC as an alternate)
15 V
NC
OUT A
V+A
OUTB
-IN A
V+B
+INA
-IN B
V-
+INB
-=-15 V
-=-
Equivalent Circuit
-IN
r1--------r---~--------._--------~--~------------------~--V+
R6
+ IN
27
n
OUT
R7
22
n
+OFFSET
NULL
R1
1 kfl
R3
50 kO
L---~
Rl1
R2
1 kn
__
~
____
50 k!1
~
__
~
________
~
__
~
-+__ ____ ____ __ __
____
-OFFSET
NULL
14-94
~
~
~
~
~~V_
J.LA747Q8
Dual
Operational Amplifier
F=AIRCHILC
A Schlumberger Company
MIL-STO-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
10-Lead Can Package
(Top View)
The !LA7470B is a pair of high performance monolithic operational amplifiers constructed using the Fairchild Planar
Epitaxial process. They are intended for a wide range of
analog applications where board space or weight are important. High common mode voltage range and absence
of latch-up make the !LA74 70B ideal for use as a voltage
follower. The high gain and wide range of operating voltage provide superior performance in integrator, summing
amplifier, and general feedback applications.
The !LA7470B is short circuit protected and requires no
external components for frequency compensation. The internal 6 dB/octave roll-off insures stability in closed loop
applications. 6
•
•
•
•
No Frequency Compensation Required
Short Circuit Protection
Offset Voltage Null Capability
Large Common Mode And Differential Voltage
Ranges
• Low Power Consumption
• No Latch-Up
NC
vLead 5 connected to case.
Connection Diagram
14-Lead Flatpak
(Top View)
+OFFSET
NULLA
-INA~~---,""
+INA
V+ A
-OFFSET
NULLA
Connection Diagram
14-Lead DIP
(Top View)
YC=JOUTA
NC
V-OFFSET
NULLB
r - I C = J OUT B
+INB~~_r-
-IN A
+IN A
-OFFSET
NULL A
v-
+ OFFSET
--'"'"L._ _ _ _ _. .- - NULL B
V+ A
OUT A
Order Information
NC
Part No.
Case I
Finish
+IN B
V+ B
/.lA747FMOB
/.lA747DMOB
/.lA747HMOB
-IN B
+ OFFSET
NULL B
JAN Product Available
-OFFSET
NULL B
V+ B
+OFFS£T
-IN B
NULL A
OUT B
10102
10102
10102
10102
10102
10102
14-95
AA
CA
IC
BAA
BAB
BCA
BCB
BIA
BIC
Package Code
Mil-M-38510, Appendix C
F-1 14-Lead Flatpak
D-1 14-Lead DIP
A-2 10-Lead Can
F-1
F-1
D-1
D-1
A-2
A-2
14-Lead Flatpak
14-Lead Flatpak
14-Lead DIP
14-Lead DIP
10-Lead Can
10-Lead Can
MA747Q8
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 12
Can and Flatpak
DIP
Supply Voltage
Differential Input Voltage
Input Volt~ge13
Short Circuit Duration 14
Processing: MIL-STD-883, Method 5004
-65°C to + 175°C
-55°C to +125°C
300°C
350 mW
400mW
±22 V
±30 V
±20 V
Indefinite
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
10.
11.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
Dynamic tests at -55°C
AC tests at 25°C
AC tests at 125°C
AC tests at -55°C
Group C and 0 EndpOints: Group A, Subgroup 1
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guara'1lGed but not tested
5. When cpanges occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For mo(e information on device function, refer to the Fairchild Unear
Data Bqpk Commercial Section.
7. Not available on "A747HMQB.
8. Z, is g~anteed by I'B: Z, - 4.0 VTIi'B, VT - 26 mV at 25·C, 34 mV at
125·C, and 19 mV at -55·C.
9. Pc is guaranteed by Icc: Pc - 30 Icc.
10. V'R is i'aranteed by the CMR test.
11. BW is guaranteed by 1,: BW - 0.35/1,.
12. Rating applies to ambient temperatures up to 125·C. Above 125·C
ambient, derate linearly at 140·C/W for the Can and Flatpak and
120·C/W for the DIP.
13. For supply voltages less than ± 20 V, the absolute maximum input
voltage is equal to the supply voltage.
14. Short circuit may be to ground or either supply. Rating applies to
125°C case temperature or 75°C ambient temperature.
14-96
}lA747QB
JJA747QB
Electrical Characteristics Vee
Symbol
Via
~Vlo/~T
=
± 15 V, unless otherwise specified.
Characteristic
Input Offset Voltage
Input Offset Voltage
Temperature Sensitivity
Condition
'"
Min
Max
Unit
Note
Subgrp
1
5.0
mV
1
6.0
mV
1
2,3
25°C ";;;TA";;; 125°C
15
/NloC
4
2
-55°C ";;;TA";;; +25°C
15
pV/oC
4
3
mV
4
1,2,3
nA
1
1,2
3
Rs=10 kn, VCM=O V
Via adi
Input Offset Voltage
Adjustment Rangel
110
Input Offset Current
VeM =0 V
500
nA
1
~llo/~T
Input Offset Current
Temperature Sensitivity
25°C ";;;TA";;; 125°C
1.0
nArC
4
2
-55°C";;; TA";;; +25°C
1.0
nA/oC
4
3
340
nA
1
1
500
nA
1
2
3
liB
Input Bias Current
5.0
200
VeM = 0 V
1500
ZI
lee
Pc
Input ImpedanceS
VIR
Input Voltage Range 10
PSRR
Power Supply Rejection Ratio
los
Output Short Circuit Current
Avs
Large Signal Voltage Gain
TR(os)
1
1
0.2
Mn
1
2
Power Consumption (Total)9
Common Mode Rejection
TR(t,)
1
Mn
Supply Current (Total)
CMR
VoP
nA
0.3
Output Voltage Swing
Transient
Response
I Rise Time
I Overshoot
VeM = ± 12 V, Rs = 50 n
5.6
mA
1
1
5.0
mA
1
2
3
6.6
mA
1
170
mW
1
1
150
mW
1
2
200
3
mW
1
70
dB
1
1,2,3
±12
V
1
1,2,3
pVIV
1
1,2,3
V+ =10 V, V-=-20 V to
V+ =20 V, V-=-10 V, Rs=50 n
150
mA
1
1,2,3
50
V/mV
1
4
25
V/mV
1
5,6
60
Vo=±10 V, RL=2.0 kn
RL = 10 kn
±12
V
1
4,5,6
RL = 2.0 kn
±10
V
1
4,5,6
800
ns
3
g, 10, 1
25
%
3
g, 10,11
Vee = ± 20 V, VI = 50 mV,
RL = 2.0 kn, CL = 100 pF, Av = 1.0
BW
Bandwidth 11
0.437
MHz
3
g, 10, 1
SR
Slew Rate
Vee=±20V, RL = 2.0 kn,
Av = 1.0
0.3
V/IlS
3
g, 10, 1
CS
Channel Separation
Vee =±20 V
80
dB
1
9
NI (BB)
Noise Broadband
Vee = ± 20 V, BW = 5.0 kHz
15
IlV,ms
4
9
NI (PC)
Noise Popcorn
Vee = ±20 V, BW = 5.0 kHz
40
IlVpk
4
9
14-97
•
MA747Q8
Primary Burn-In Circuit
(38510/10102 may be used by FSC as an alternate)
15 V
Ne
OUT A
V+A
OUTB
-INA
V+ B
+INA
-INB
V-
+INB
"::"
-15 V
"::"
CR05210F
Equivalent Circuit (1/2 of circuit)
-IN
~~------~----.-------~~---------.---,__------------------~--V+
R6
+IN
'7
n
OUT
R7
•• n
·OFFSET
NULL
R1
R3
1kn
50kn
R11
R2
1 kn
50 kn
L---~~~~--t---~--------4---~--~-4--~----4-----~--~~~~V-
-OFFSET
NULL
14-98
F=AIRCHILO
A Schlumberger Company
J,lA7S9QB
Power
Operational Amplifier
MIL-STD-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
8-Lead Can
(Top View)
The J,lA759QB is a high performance monolithic operational
amplifier constructed using the Fairchild Planar Epitaxial
process. The amplifier provides high output current and
features small signal characteristics better than the
J,lA741QB. The amplifier is designed to operate from a single or dual power supply and the input common mode
range includes the negative supply. The high gain and
high output power provide superior performance whenever
an operational amplifier is needed. The J,lA759QB employs
internal current-limiting, thermal shutdown and safe-area
compensation making it essentially indestructible. It is intended for a wide range of applications including voltage ..
regulators, audio amplifiers, servo amplifiers, and power
drivers. s
•
•
•
•
•
High Output Current
Internal Short Circuit Current-Limiting
Internal Thermal Overload Protection
Internal Output Transistors Safe-Area Protection
Input Common Mode Voltage Range Includes Ground
Or Negative Supply
NC
vLead 4 connected to case.
Order Information
Part No.
J,lA759HMQB
14-99
Casel
Finish
GB
Package Code
MII-M-38510, Appendix C
A-1 8-Lead Can
J.LA759QB
Proce~ing:
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 10
Can
Supply Voltage
Differential Input Voltage
Input Voltage 11
-65°C to +175°C
-55°C to +125°C
300°C
330 mW
±18 V
±15 V
(V- - 0.3 V) to V+
MIL-STD-883, Method 5004
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
Static tests at
Static tests at
Static tests at
Dynamic tests
Dynamic tests
Dynamic tests
25°C
125°C
-55°C
at 25°C
at 125°C
at -55°C
Group C and D Endpoints: Group A, Subgroup 1
NotH
1. 100% Test and Group A
2. Group A
3.. Periodic 18sts, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data shein revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Lineer
Oata Book Commercial Section.
7. ZI Is guaranteed by liB: ZI = 4.0 VT/IIB, VT = 26 mV at 25°C, 34 mV at
125°C, and 19 mV at -55°C.
B. VIA Is guaranteed by the CMR test.
9. Vo - ± 12 V is guaranteed by worse case Vo - ± 5 V.
10. Rating applies to ambient temperatures up to 125°C. Above 125°C
ambient. derate linearly at lSOoC/W.
11. For Supply voltages kiss then ± 15 V, the ab.soIute maximum input
voltage is equal to the supply voltage.
.
14-100
IlA759QB
~759QB
Electrical Characteristics Vee = ± 15 V, unless otherwise specified.
Symbol
Input Offset Voltage
VIO
VIO
Characteristic
adj
110
Condition
Rs = 50 il, VCM = 0 V
Input Offset Voltage
Adjustment Range
Input Offset Current
liB
Input Bias Current
ZI
Input Impedance7
Min
Unit
Note
3.0
mV
1
1
4.5
mV
1
2,3
mV
1
1
30
nA
1
1
60
nA
1
2,3
150
nA
1
1
2,3
Max
6.0
VCM=O V
VCM=O V
nA
1
Mil
1
1
mA
1
1
dB
1
1,2,3
V
1
1,2,3
/lVlV
1
1,2,3
mA
1
1
50
VlmV
1
4
25
V/mV
1
5,6
V
1
4,5,6
300
Icc
Supply Current
CMR
Common Mode Rejection
VIR
Input Voltage RangeS
0.25
18
-15 V";;;VCM";;;13 V, Rs=10 kil
80
-15
PSRR
Power Supply Rejection Ratio
±5.0 V";;;Vcc";;;±18 V, Rs=10 kil
IPk
Peak Output Current9
5.0 V";;;Vo";;;12 V,
-12 V";;;Vo";;;-5.0 V
Avs
Large Signal Voltage Gain
RL = 50
n,
VoP
Output Voltage Swing
RL=50
n
Vo = ± 10 V
13
100
±325
±10
14·101
Subgrp
J.LA759Q8
Primary BlI,fn-ln Circuit
-
·OFFSET
NULL
NC
r---15V
-IN
V+
+IN
OUT
J
.,1-
r---
V-
+OFFSET
NULL
r----
-15 V
~uivaleQt
Circuit
-IN
+IN--~--~-----r-----+---+--------~
-OfFSET
NULL
+ OFFSET
NULL
EOOOO21F
•
14-102
FAIRCHILD
A Schlumberger Company
p.A7718Q8
Operational Amplifier
MIL-STD-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
8-Lead Can
(Top View)
This monolithic JFET input operational amplifier incorporates well matched ion-implanted JFETs on the same chip
with standard bipolar transistors. The key feature of this
op amp is low input bias currents in the sub nanoamp
range plus high slew rate and wide bandwidth. 6
•
•
•
•
NC
Low Input Bias Current
Low Input Offset Current
High Slew Rate
Wide Bandwidth
>--"-0 OUT
-IN
vLead 4 connected to case.
Connection Diagram
8-Lead DIP
(Top View)
+OFFSET
NULL
-IN
v+
+IN
OUT
-OffSET
v-
NULL
Order Information
Part No_
1lA771BHMQB
1lA771 BRMQB
14-103
Casel
Finish
GC
PA
Package Code
MII-M-38510, Appendix C
A-1 8-Lead Can
D-4 8-Lead DIP
~A771BQB
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 10
Can
DIP
Supply Voltage
Differential Input Voltage
Input Voltage 11
Short Circuit Duration 12
-65°C to + 175°C
_55°C to + 125°C
300°C
Burn-in: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
330 mW
400 mW
±18 V
±30 V
±16 V
Indefinite
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
10.
11.
Not••
1. 100% Test and Group A
2. Group.A
3. PeriodiC tests, iJrolJp C
4. Guaranteed but not tested
5. When changes OccUr, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For mOre information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. The input bias currents are junction leakage curre.nts whiCh
approximately double for every 10"C increase in the junction
temperature, TJ. Due to IimHed production test time, the input bias
currents measured are correlated to junction temperature. In normal
operation the junction temperature rises above the ambient temperature
as a result of Internal dissipation, Po. TJ - TA + 6jA PD where OjA is
the thermal rGsistance from junction to ambient. Use of a heat sink is
recommended ij input bias current is to be kept to a minimum.
8. VIA is guaranteed by the CMR test.
9. VOP·is guaranteed by the Avs test.
10. Rating applies to ambient temperatures up to 12S"C. Above 12S"C
ambient, derate linearly at 150"C/W for the can and 120"C/W for the
DIP.
11. For negative supply voltages less than -16 V, the negative input
vOltage is equal to the negative supply voltage.
12. Short circuit may be to ground or eHher supply. Rating applies to
12S"C case temperature or 7S"C ambient temperature.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
Dynamic tests at -55°C
AC tes.ts at 25" C
AC tests at 125" C
AC tests at ~55" C
Group C and 0 Endpoints: Group A, Subgroup
14-104
MA771BQB
~771BQB
Electrical Characteristics Vee = ± 15 V, unless otherwise specifies.
Symbol
Via
!lVlol !IT
Characteristic
Input Offset Voltage
Condition
Input Offset Voltage
Temperature Sensitivity
1
2
-55°C';;; TA';;; + 25°C
30
4
3
mV
4
1,2,3
Input Voltage Range8
PSRR
Power Supply Rejection Ratio
los
Output Short Circuit Current
Avs
Large Signal Voltage Gain
VoP
TR(t,)
B.O
VCM =0 V
VIR
1
2,3
4
VCM = 0 V
Common Mode Rejection
Subgrp
mV
Input Offset Current?
CMR
1
p'vrc
p'vrc
110
Supply Current
Note
mV
30
VCM = 0 V
Icc
Unit
5.0
B.O
Input Offset Voltage Adjustment
Range
Input Bias Current?
Max
25°C';;; TA';;; 125°C
VIO adi
liB
Min
Rs = 50 n, VCM = 0 V
VCM = ± 11 V,
Rs=50 kn
50
pA
1
1
20
nA
1
2,3
100
pA
1
1
5Q
nA
1
2,3
2.B
mA
1
1
3.4
mA
1
2,3
dB
1
1,2,3
BO
± 11
±10 V';;;Vcc';;;±lB V,
Rs=50 kn
100
1
1,2,3
1
1,2,3
mA
1
1,2,3
50
VlmV
1
4
25
VlmV
1
5,6
BO
Vo=±10 V,
RL = 2.0 kn
V
p.VIV
Output Voltage Swing
RL = 10 kn
±12
V
1
4,5,6
Output Voltage Swing9
RL = 2.0 kn
±10
V
1
4,5,6
ns
4
9,10,11
Transient Response
I Rise Time
I Overshoot
TR(os)
VI = 50 mY, RL = 2.0 kn,
CL = 100 pF, Av = 1.0
SR
Slew Rate
RL = 2.0 kn, Av = 1.0
ts
Settling Time
Av = 1.0
200
40
7.0
1500
%
4
9,10,11
V/p.s
4
9,10,11
ns
4
9
NI (BB)
Noise Broadband
BW= 10 kHz
15
p.V,ms
4
9
NI (PC)
Noise Popcorn
BW=10 kHz
BO
P.Vpk
4
9
14-105
IlA771BQB
Primary Burn-In Circuit
(38510/11904 may be used by FSC as an alternate)
-
+OFFSET
NULL
Ne
r-15 Y
y-
_IN
OUT
.,1r-
1
-IN
Y-
-OFFSET
NULL
-
-15Y
Equivalent Circuit
r-------------~----------~~--------~------------------_r----~----,_~
J8
-0""'" NULL
+ OFFSET NULL
14-106
F=AIRCHILD
A Schlumberger Company
MA772BQB
Operational Amplifier
MIL-STO-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
8-Lead Can
(Top View)
This monolithic JFET input operational amplifier incorporates well matched ion-implanted JFETS on the same chip
with standard bipolar transistors. The key feature of this
op amp is low input bias currents in the sub nanoamp
range plus high slew rate and wide bandwidth. 6
•
•
•
•
v+
Low Input Bias Current
Low Input Offset Current
High Slew Rate
Wide Bandwidth
vLead 4 connected 10 case.
Connection Diagram
8-Lead DIP
(Top View)
v+
OUTB
-INB
+INB
Order Information
Part No.
j.JA772BHMQB
j.JA772BRMQB
Casel
Finish
GC
PA
Package Code
Mil-M-38S10, Appendix C
A-1 8-Lead Can
0-4 8-Lead DIP
JAN Product Available
11905
14-107
BPB
0-4 8-Lead DIP
J.LA772BQB
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 10
Can
DIP
Supply Voltage
Differential Input Voltage
Input Voltage 11
Short Circuit Duration12
-65°C to + 175°C
-55°C to + 125°C
300°C
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
330 mW
400 mW
±18 V
±30 V
±16 V
Indefinite
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
10.
11.
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Unear
Data Book Commercial Section.
7. The input bias currents ere junction leakage currenta which
approximately double for every 10°C increeae in the junction
temperature, TJ. Due to limited production test time, the input bias
currents measured ere correlated to junction temperature. In normal
operation thll junction temperature rises above the ambient temperature
as a resuU of internal dissipation, Po. TJ - TA + IJjA Po where OjA is
the thermal resistance from junction to ambient. Use of a heat sink is
recommended H input bias current is to be kept to a minimum.
8. VIR Is gU!lranteed by the CMR test.
9. Vop is guaranteed by the Avs test.
10. Rating applies to ambient temperatures up to 125°C. Above 125°C
ambient, derate linearly at 150°CIW for the Can and 120°C/W for the
DIP.
11. For negative supply voltages less then -16 V, the negative input
voltage is equal to the negative supply voUBge.
12. Short circuit may be to ground or either supply. Rating applies to
125°C case temperature or 75°C ambient temperature.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
DynamiC tests at 25°C
DynamiC tests at 125°C
Dynamic tests at -55°C
AC tests at 25° C
AC tests at 125" C
AC tests at -55" C
Group C and D Endpoints: Group A, Subgroup 1
14-108
~A772BQB
~772BQB
± 15 V, unless otherwise specified.
Electrical Characteristics Vee =
Symbol
Characteristic
Condition
= 50
Min
Max
Unit
Note
5.0
mV
1
1
mV
1
2,3
4
2
30
p'vrc
p'vrc
4
3
VIO
Input Offset Voltage
Rs
8.0
tNlo/AT
Input Offset Voltage
Temperature Sensitivity
25°C';;; TA';;; 125°C
30
-55°C';;; TA';;; +25°C
Input Offset Currene
VCM=O V
110
liB
Input Bias Currene
Icc
Supply Current (Total)
VCM =0 V
CMR
Common Mode Rejection
VIR
Input Voltage RangeS
PSRR
Power Supply Rejection Ratio
los
Output Short Circuit Current
Avs
Large Signal Voltage Gain
VOP
Output Voltage Swing
Output Voltage SWing 9
TR(t,.)
Transient Response
TR(oS>
n, VCM = 0 V
I Rise Time
I Overshoot
VCM = ±11 V,
Rs=50 kn
RL = 2.0 kn, Av = 1.0
NI (BB)
Noise Broadband
BW=10 kHz
NI (PC)
Noise Popcorn
BW=10 kHz
CS
Channel Separation
pA
1
1
2,3
1
6.8
mA
1
2,3
80
dB
1
1,2,3
± 11
V
1
1,2,3
100
p.VIV
1
1,2,3
80
mA
1
1,2,3
50
V/mV
1
4
25
V/mV
1
5,6
V
1
4,5,6
4,5,6
V
1
200
ns
4
9,10,11
40
%
4
9,10,11
V/p.s
4
9,10,11
ns
4
9
15
p.V rms
4
9
80
P.Vpk
4
9
dB
1
9
7.0
1500
80
14-109
100
1
RL =2.0 kn
Av = 1.0
2,3
1
VI = 50 mV, RL = 2.0 kn
CL=100 pF. Av=1.0
Settling Time
1
1
nA
±10
Slew Rate
1
nA
mA
±12
SR
pA
50
RL = 10 kn
ts
50
20
5.6
±10 V';;;Vcc';;;±18 V,
Rs=50 kn
Vo=±10 V,
RL =2.0 kn
Subgrp
J.lA772BQB
Primary Burn-In Circuit
(38510/11905 may be used by FSC as an alternate)
15V
OUT A
V+
-INA
OUTB
+INA
-INB
V-
+INB
-=
-15
Ii
-=
CI'ID5180F
Equivalent Circuit
r-------------------------~~----------------1_~----------------~------------------------------------~--------~--------._~
J6
RS
RI6
~~~----~--------~----~----~------------4_~----_4----------------~----------------------------~------------~~~~
14-110
f=AIRCHILD
A Schlumberger Company
JlA774BQB
Operational Amplifier
MIL-STO-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
14-Lead DIP
(Top View)
This monolithic JFET input operational amplifier incorporates well matched ion-implanted JFETS on the same chip
with standard bipolar transistors. The key feature of this
op amp is low input bias currents in the sub nanoamp
range plus high slew rate and wide bandwidth. 6
•
•
•
•
OUT"
Low Input Bias Current
Low Input Offset Current
High Slew Rate
Wide Bandwidth
-IN"
+IN"
y+
+IN D
y-
+IN B
+IN C
-IN B
-IN C
OUTB
OUT C
Order Information
Part No.
1LA774BDMQB
14-111
Casel
Finish
PA
Package Code
MII-M-38S10, Appendix C
0-1 14-Lead DIP
J,LA7748Q8
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 10
DIP
Supply Voltage
Differential Input Voltage
Input Voltage 11
Short Circuit Duration 12
Processing: MIL-STD-883, Method 5004
-65°C to +175°G
-55°C to +125°C
300°C
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
400 mW
± 18 V
±30 V
± 16 V
Indefinite
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
10.
11.
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests. Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data. sheet revisions available.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
Dynamic tests at -55°C
AC tests at 25" C
AC tests at 125" C
AC tests at -55" C
Group C and D Endpoints: Group A, Subgroup
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. The input bias currents are junction leakage currents which
approximately double for every 10°C increase in the junction
temperature, TJ. Due to limited production test time, the input bias
currents measured are correlated to junction temperature. In normal
operation the junction temperature rises above the a~ient temperature
as a result of internal dissipation, Po. TJ = TA + OjA Pfwhere OjA is
the thermal resistance from junction to ambient. Use of a heat sink is
recommended if input bias current is to be kept to a minimum.
S. V,R is guaranteed by the CMR test.
9. Vop is guaranteed by the Avs test.
10. Rating applies to ambient temperatures up to 12S·C. Above 12S·C
ambient, derate linearly at 120·C/W.
11. For negative supply voltages less than -16 V, the negative input
voltage is equal to the negative supply voltage.
12. Short circuit may be to ground or either supply. Rating applies to
125°C case temperature or 75°C ambient temperature.
14-112
fJ.A774BQB
j.tA774BQB
Electrical Characteristics Vee = ± 15 V, unless otherwise specified.
Symbol
Characteristic
Condition
Min
Max
Unit
Note
5.0
mV
1
Subgrp
1
Via
Input Offset Voltage
Rs = 50 n, VCM = 0 V
8.0
mV
1
2,3
!:Nlol AT
Input Offset Voltage
Temperature Sensitivity
25°C -~:>OUT
-IN
vLead 4 connected to case.
Order Information
Casel
Part No.
pA776HMOB
14-115
Finish
GB
Package Code
MiI-M-38510, Appendix C
A-1 8-Lead Can
J,LA776Q8
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power DisSipation 10
Can
Supply Voltage
Differential Input Voltage
Input Voltage 11
Short Circuit Duration 12
Voltage E;letween Offset Null and VISET (Max Current at ISET)
VSET (Max Voltage to GND at ISET)
Processing: MIL-STD-883, Method 5004
-65°C to + 175°C
-55°C to + 125°C
300°C
330 mW
± 18 V
±30 V
±15 V
Indefinite
±0.5 V
500 iJ.A
(V+ - 2 V)
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
~VSET~V+
Static tests at
Static tests at
Static tests at
Dynamic tests
Dynamic tests
Dynamic tests
25°C
125°C
-55°C
at 25°C
at 125°C
at -55°C
Group C and D Endpoints: Group A, Subgroup
Notes
1. ~100% Test and Group A
Group A
3~ Periodic tests, Group C
4~ Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
2~
6. For more information on device function, refer to the Fairchild Unear
Data Bbok Commercial Section.
PC1 is guaranteed by ICC1: Pc1 ~ 30 ICC1~
8. Pc2 is guaranteed by ICC2: Pc2 = 6 ICC2'
9~ V,R is guaranteed by the CMR test.
1o~ Rating applies to ambient temperatures up to 125"C~ Above 125"C
ambient derate linearly at 150"C/W~
11. For supply voltages less than ±15 V, the absolute maximum input
voltage is equal to the supply voltage~
12~ Short circuit may be to ground or either supply~ Rating applies to
125°C case temperature or 75°C ambient temperature for
ISET < 30 MA~
7~
14-116
J-lA776Q8
JlA7760B
Electrical Characteristics ± 3.0 V .;;; Vee';;; ± 15 V, 1.5 JlA';;; ISET .;;; 15 JlA, unless otherwise specified.
Symbol
VIO
110
Characteristic
Input Offset Voltage
Input Offset Current
Condition
Rs = 50
n,
Min
VCM = 0 V
ISET = 1.5 pA
VCM = 0 V
ICC1
Input Bias Current
Supply Current
VeM = 0 V
Vce=±15 V
Supply Current
Vee = ±3.0 V
Power Consumption?
Vcc=±15V
Power ConsumptionS
Vec=±3.0 V
Common Mode Rejection
Subgrp
6.0
mV
1
2,3
3.0
nA
1
1
5.0
nA
1
2
10
nA
1
3
1
1,2
1
3
ISET = 1.5 pA
7.5
nA
1
1,2
20
nA
1
3
ISET = 15 pA
50
nA
1
1,2
120
nA
1
3
ISET = 1.5 pA
ISET = 1.5 pA
ISET = 1.5 pA
ISET = 1.5 pA
ISET = 15 pA
CMR
1
nA
ISET = 15 pA
Pc2
1
nA
ISET= 15 pA
Pc1
Note
mV
15
ISET = 15 pA
ICC2
Unit
5.0
40
ISET = 15 pA
liB
Max
25
pA
1
1
30
pA
1
2,3
180
pA
1
1
200
pA
1
2,3
20
pA
1
1
25
pA
1
2,3
160
pA
1
1
180
pA
1
2,3
0.75
mW
1
1
2,3
0.9
mW
1
5.4
mW
1
1
6.0
mW
1
2,3
120
pW
1
1
150
pW
1
2,3
960
pW
1
1
1080
pW
1
2,3
Vec=±15 V, VCM=±10 V,
Rs= 50 n
70
dB
1
1,2,3
Vce=±3.0 V, VeM=±1.0 V,
Rs = 50 n
70
dB
1
1,2,3
V
1
1,2,3
V
1
1,2,3
pVIV
1
1,2,3
VIR
Input Voltage Range 9
Vee=±15 V
±10
Vee = ±3.0 V
± 1.0
PSRR
Power Supply Rejection Ratio
±3.0 VIN
CI--+-~-OUT
R11
-IN--~-i3
130 0
Q15
R12
8000
R13
40
L----4------~~GND
V-
15-6
p.A139Q8
F=AIRCHILO
Quad Comparator
A Schlumberger Company
MIL-STO-883
July 1986-Rev 25
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
14-Lead DIP
(Top View)
The jJ.A 1390B consists of four independent precision voltage comparators designed specifically to operate from a
single power supply. Operation from split power supplies is
also possible and the low power supply current drain is
independent of the supply voltage range. Darlington connected PNP input stages allow the input common mode
voltage to include ground. 6
• Single Supply Operation
• Dual Supply Operation
• Allow Comparison Of Voltages Near Ground
Potential
• Low Current Drain
• Compatible With All Forms Of Logic
• Low Input Bias Current
• Low Input Offset Current
• Low Offset Voltage
OUT A
OUTD
V-orGND
-INA
+IN 0
+INA
-IN D
-IN B
+IN C
+INB
-INC
Connection Diagram
14-Lead Flatpak
(Top View)
Q
§ §
Y+
OUTC
Y+
Connection Diagram
20-Terminal CCP
(Top View)
<.>
OUTB
OUT B
Y- OR GND
[::==}::::;~::~['4==~ OUT C
OUT D
NC
NC
Y- OR GND
-IN A
- L - _.... +IND
+IN 0
'-____r---, -IN
NC
NC
-IN
+IN A
BL_y'i"'....
.-'-'
D
I +IN C
+IN B - - - " _ _ _
".
.. .
-~
J""- -IN C
-IN D
CD01470F
<.>
<.>
Z
.,
i!i
+
Order Information
Part No.
MA 139FMOB
MA 139DMOB
jJ.A139LMOB
Casel
Finish
AA
CA
2C
Package Code
MiI-M-38510, Appendix C
F-1 (14-Lead Flatpak)
D-1 (14-Lead DIP)
C-2 (20-Terminal CCP)
JAN Product Available
11201
11201
15-7
BCA
BCB
D-1 (14-Lead DIP)
D-1 (14-Lead DIP)
J1A139QB
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 8
Flatpak
DIP and CCP
Supply Voltage
Differential Input Voltage9
Input Voitage 10
Input Current
Short Circuit Duration 11
-65°C to 175°C
-55°C to 125°C
300°C
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
350 mW
400 mW
± 18 V or 36 V
36 V
-0.3 V to 36 V
10 mA
Indefinite
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
10.
11.
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests. Group C
4. Guaranteed but not tested
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynam ic tests at 25° C
Dynamic tests at 1250 C
Dynamic tests at -55c C
AC tests at 25°C
AC tests at 125°C
AC tests at -55°C
Group C and D Endpoints: Group A, Subgroup 1
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. VIR is guaranteed by the VIO test.
8. Rating applies to ambient temperatures up to 125·C. Above 125·C
ambient, derate linearly at 140·C/W for the Flatpak and 120·C/W for
the DIP and CCP.
9. The differential input voltage shall not exceed the supply voltage.
10. For supply voltages less than ± 18 V, the absolute maximum input
voltage is equal to the supply voltage. The input common mode
voltage or either signal input voltage should not be allowed to go
negative more than 0.3 V.
11. Short circuit may be to ground or negative supply. Rating applies to
125°C case temperature or 75°C ambient temperature. Short circuit
from output to V+ can cause extensive heating and eventual
destruction. No more than one amplifier should be shorted at the
same time as the maximum junction temperature will be exceeded.
15-8
p.A139QB
Electrical Characteristics V+ = 5 V, V- = 0 V, unless otherwise specified.
Symbol
VIO
Max
Unit
Note
o V.
ti~
ell.
OUT A2
w"a.
w"
PULtt~~~ C:=J--I
:1:':'
u
z
~
L-=:J----....-.,--4-- Vo
ii,
STROBE
CR02040F
Use V, or
'ii"
ground other input.
16-20
J.LA9615QB
fJA961SQB
Electrical Characteristics
Symbol
Characteristic
Condition
VOL
Output Voltage LOW 7 ,8
Vee = 4.5 V, 10L = 15 rnA,
VOIFF = 0.5 V
VOH
Output Voltage HIGH 7 ,8
Vee = 4.5 V, 10H = -5.0 rnA,
VOIFF = -0.5 V
leEx
Output Leakage Current8
Vee = 4.5 V, VeEx = 12 V,
VOIFF = 4.5 V
Min
Subgrp
Max
Unit
Note
0.40
V
1
1,2,3
V
1
1,2
3
2.4
2.2
V
1
!J.A
1
1
200
!J.A
1
2,3
-15
rnA
1
1,2,3
100
los
Output Short Circuit Currentl,8
Vee = 5.5 V, Vo = 0 V,
VOIFF = -0.5 V
-80
11L1
Low Level Input Current
(Data Input)
Vee = 5.5 V, VI = 0.4 V,
Other Input = 5.5 V
-0.7
rnA
1
1,2
-0.9
rnA
1
3
IIL2
Low Level Input Current8
(Strobe)
Vee = 5.5 V, VI = 0.4 V,
VOIF F = 0.5 V
-2.4
-2.4
rnA
rnA
1
4
1
2,3
IIL3
Low Level Input CurrentS
(Response Control)
Vee = 5.5 V, VOIFF = 0.5 V
rnA
rnA
1
4
1
2,3
VIR
Input Voltage Range 9
Vee = 5.0 V, VOIFF = 1.0 V
15
V
1
1,2,3
IIH
High Level Input Current8
(Strobe)
Vee = 4.5 V, VOIFF = -0.5 V,
VR = 4.5 V
RI
Input Resistor
Vee = 5.0 V, VI(R) = 1.0 V,
+Input = GND
VTH
Differential Input Threshold
Voltage
-1.2
-1.2
-15
2.0
!J.A
1
1
5.0
!J.A
1
2,3
77
167
Q
1
1
Vee = 4.5 V, VeM = 0 V
-500
500
rnV
1
1,2,3
Vee=5.0 V, VeM= ±15 V
-1.0
1.0
V
1
1,2,3
50
rnA
1
1,2,3
-1.5
V
3
1
5.5
V
4
1,2,3
lee
Supply Current
Vee = 5.5 V, -Inputs = 0 V,
+ Inputs = 0.5 V
Vie
Input Clarnp Voltage (Strobe)
Vee = 4.5 V, lie = -12 rnA
BVI
High Level Input Breakdown
Voltage (Strobe)
Vee = 5.5 V, 11= 1.0 rnA
tpLH1
Propagation Delay to High Level
(Inputs A and B to Output)
Vee = 5.0 V, CL = 30 pF,
RL = 3.9 kQ (See Fig. 1)
50
ns
2
9
75
ns
3
10, 11
tPHL1
Propagation Delay to Low Level
(Inputs A and B to Output)
Vee = 5.0 V, CL = 30 pF,
RL = 390 Q (See Fig. 1)
50
75
ns
ns
2
3
9
10, 11
tpHL2
Propagation Delay to Low Level
(Strobe to Output)
Vee = 5.0 V, CL = 30 pF,
RL = 390 Q
15
ns
ns
4
9
10, 11
tpLH2
Propagation Delay to High Level
(Strobe to Output)
Vee = 5.0 V, CL = 30 pF,
RL = 3.9 kQ
ns
ns
4
16-21
22
15
25
3
3
9
10, 11
•
Primary Burn-In Circuit
(38510/10404 may be used by FSC as an alternate)
5V
1
5100
510 0
OUTA
Vee
1 kO
-
ACTIVE
PULL-UP A
OUTB
STAOBE A
ACTIVE
PULL-UP B
AESPA
STROBE B
RESP B
+INA
-
RA
F
r--
+IN B
-INA
AB
GNO
-IN B
r--
il-
Equivalent Circuit (1/2 of circuit)
AESP
Vee
A4
All
1.64 kU
1.5
STAOBE
A18
1.8kll
k~k
R22
R2.
80 !!
2.0 k!!
A19
900U
013
A
A2
8.36kJ!
Al
130 !!
A3
8.36 kH
04
R23
4.0 k!1
+IN
r--------l
I Vee
I
I
I
I
I
I
-IN
A7
7.0kU
A6
7.0kfl
010
R15
2.5 k!l
R27
2.5 kll
OUT
R20
3.0 k!l
R16
soon
TO
OTHEA
RECEIVEA
R8
lOOn
RIO
132 n
R9
300 !l
GNO
-
~
R25
100 n
10 k!!
IL
.".
Rl'
2.5 k~l
Ll
- -
ACTIVE
PULL-UP
07
R28
100 HI
_______
02
I
I
.JI
COMMON TO BOTH CHANNELS
16-22
R26
9OJ!
A21
1.0 kll
.".
.".
MA9616HQB
F=AIRCHILO
Triple Line Driver
A Schlumberger Company
MIL-STD-883
July 1986-Rev 25
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
14-Lead DIP
(Top View)
The 1lA9616HQB is a triple line driver which meets the
electrical interface specifications of EIA RS-232-C and
CCITT V.24 and/or MIL-STD-188C. Each driver converts
TTL/DTL logic levels to EIAICCITT and/or MIL-STD-188C
logic levels for transmission between data terminal equipment and data communications equipment. The output
slew rate is internally limited and can be lowered by an
external capacitor; all output currents are short circuit limited. The outputs are protected against RS-232-C fault conditions. A logic HIGH on the inhibit terminal interrupts
signal transfer and forces the output to a VOL (EIAICCITT
MARK) state.
INA1
v+
INA2
INB1
INHIBrrA
INB2
OUTA
For the complementary function, see the 1lA9627QB Dual
EIA RS-232-C and MIL-STD-188C Line Receiver.6
• Internal Slew Rate Limiting
• Meets EIA R8-232-C And CCITT V.24 And/Or
MIL-STD-188C
• Logic True Inhibit Function
• Output Short Circuit Current-Limiting
• Output Voltage Levels Independent Of Supply
Voltages
INHIBITB
INC
OUTB
INHIBITC
OUTC
v-
GND
Connection Diagram
20-Terminal CCP
(Top View)
cj!;
~
j!;
"z
+
>
Iii
j!;
INHIBrrA
INB2
NC
NC
INHIBrrB
OUTA
NC
NC
OUTB
INC
..
I"
z
C!I
"z
,L
"50
j!;
"""""
Order Information
Part No.
1lA9616HDMQB
1lA9616HLMQB
16-23
Casel
Finish
CA
2C
Package Code
Mil-M-38510, Appendix C
D-1 14-Lead DIP
C-2 20-Terminal CCP
~9616HQB
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 10
DIP and CCP
Supply Voltage
Input or Inhibit Voltage
Output Signal Voltage
-65°C to + 175°C
-55°C to + 125°C
300°C
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
400 mW
± 15 V
-1.5 V to +6.0 V
± 15 V
Group A Electrical Tests Subgroups:
1.
2.
3.
9.
10.
11.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
AC tests at 25°C
AC tests at 125°C
AC tests at -55°C
Group C and 0 Endpoints: Group A, Subgroup 1
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests. Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact locel sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. VIH and VIL are guaranteed by the VOH and VOL tests.
8. All input and supply leads are grounded.
9. An external capacitor may be needed to meet signal wave shaping
requirements of MIL-STD-188C at the applicable modulation rate. No
external capacitor is needed to meet RS-232-C.
10. Rating applies to ambient temperatures up to 125"C. Above 12S"C
ambient, derate linearly at 120"C/W.
Figure
Switching Time Test Circuit and Waveforms
INt 012
(INHIBIT = LOW)
v"
.><>----0 OUT
V,.
OV
VOH-__",."..t
INHIBIT
OUT
Omit VI 2 for channel 'C'.
Input PRR - 50 kHz
Pulse Width - 20 /.IS
Ir = tf = 10 ± S.O ns
16-24
OV-------r~~~------~~---
pA9616HQB
1AA9616HQB
Electrical Characteristics ± 10.8 V';;; Vee';;; ± 13.2 V, RL = 3.0 kil, unless otherwise specified.
Symbol
Characteristic
Condition
VOH
Output Voltage HIGH
VI1 and lor
VI2 = VINHIBIT = 0.8 V
VOL
Output Voltage LOW
VI1
VOH to
VOL
Output Voltage HIGH to Output
Voltage LOW Magnitude
Matching Error
los+
Positive Output Short Circuit
Current
RL = 0 n, VI1 and lor
VI2 = VINHIBIT = 0.8 V
los-
Negative Output Short Circuit
Current
RL =0 n,
VI1 = VI2 = VINHIBIT = 2.0 V
VIH
Input Voltage HIGH7
VIL
Input Voltage LOW7
IIH
Input Current HIGH
IlL
Input Current LOW
1+
Positive Supply Current
1-
Negative Supply Current
Ro
Output Resistance, Power
SR+
Positive Slew Rate9
SR-
Negative Slew Rate9
= VI2 = VINHIBIT = 2.0
V
Min
Max
5.0
7.0
-7.0
1
1,2,3
-5.0
V
1
1,2,3
±10
%
1
1,2,3
-45
-12
rnA
1
1,2,3
12
60
rnA
1
1,2,3
V
1
1,2,3
V
1
1,2,3
0.8
V
40
p.A
1
1,2,3
VI1 = VI2 = 5.5 V
1.0
1
1,2,3
1
1,2,3
1
1,2,3
1
1,2,3
1
1,2,3
1
1,2,3
1
1,2,3
1
9
VI1
= VI2 = 0.4 V
VI1 = VI2 = VINHIBIT = 0.8
VI1 = VI2 = VINHIBIT = 2.0
VI1 = VI2 = VINHIBIT = 0.8
VI1 = VI2 = VINHIBIT = 2.0
V
-1.0
V
-25
rnA
rnA
rnA
rnA
rnA
rnA
300
n
-1.6
VI1
Offl
Note Subgrp
V
2.0
= VI2 = 2.4
Unit
V
25
V
15
-2.0 V"; Va"; 0.5 V
CL = 2500 pF, RL = 3.0 kn
(See Fig. 1)
4.0
30
4.0
30
CL = 2500 pF, RL = 3.0 kn
(See Fig. 1)
-30
-4.0
-30
-4.0
VIlIS
VIlIS
VIlIS
VIlIS
2
10,11
1
9
2
10,11
•
16-25
J.lA9616HQB
Primary Burn-In Circuit
12V
-
INAl
V+
INA2
INB1
INHIBIT A
INB2
OUT A
I-----J
INHIBIT B
-:
INC
OUTB
I--
INHIBITC
OUTC
I--
v-
ii
GND
-
-12 V
Equivalent Circuit (1/3 of circuit)
v+
INHIBIT
--i<.r--r---".!VI.-T----4-------
(J
Z
,(
Part No.
J.LA9622DMOB
J.LA9622LMOB
J.LA9622FMOB
ID
z
T
16-27
Casel
Finish
CA
2C
AA
Package Code
MiI-M-38510, Appendix C
D-1 14-Lead DIP
C-2 20-Terminal CCP
F-1 14-Lead Flatpak
•
J.LA9622QB
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 8
Flatpak
DIP and CCP
V+ to GND
Input Voltage
Voltage Applied to Outputs
for Output High State
V- to GND
Enable to GND
Processing: MIL-STD-883, Method 5004
-65°C to + 175°C
-55°C to + 125°C
300°C
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
350 mW
400 mW
-0.5 V to +7.0 V
± 15 V
Method 5005
Group A Electrical Tests Subgroups:
1. Static tests at 25°C
2. Static tests at 125°C
-0.5 V to + 13.2 V
-0.5 V to -12 V
-0.5 V to +15 V
3. Static tests at -55°C
9. AC tests at 25°C
Group C and 0 Endpoints: Group A, Subgroup
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. When S3 is connected to V-, open inputs cause output to be high.
When V+ = 5 V, V- = -10 V and S3 is connected to ground, open
inputs cause output to be low.
8. Rating applies to ambient temperatures up to 12S·C. Above 12S·C
ambient, derate linearly at 140·C/W for the Flatpak and 120·C/W for
the DIP and CCP.
Figure 1 Switching Time Test Circuit and Waveforms
VI3'::~~~:V
j~:v
Yo
0.2V
1.5V
1.5V
OV======~--------------~~
16-28
MA9622QB
I.IA9622QB
Electrical Characteristics
Symbol
Characteristic
Condition
VOL
Output Voltage LOW
V+ = S3 = 4.5 V, V- = -11 V,
VDIFF = 2.0 V, 10L = 12.4 mA,
EN = open
VOH
Output Voltage HIGH
V+ = 4.5 V, V- = -9.0 V,
S3 = 0 V, VDIFF = 1.0 V,
10H = -0.2 mA, EN = open
Unit
Note
V
1
3.0
V
1
1
2.9
V
1
2
3
Min
Max
0.4
2.8
ICEX
los
Output Leakage Current
Output Short Circuit Current
Enable Input Leakage
Current
V+ = S3 = 4.5 V, V- =-11 V,
IN = open, EN = 4.0 V
IF(EN)
Enable Input Forward
Current
V+ = 5.5 V, V- = -9.0 V,
VI = open, EN = S3 = 0 V
IF(+IN)
+ Input Forward Current
V+ = 5.0 V, V- =-10 V,
VI+ = 0 V, VI- = GND,
EN = S3 = open
IR(EN)
IFHN)
-Input Forward Current
V+ = S3 = 5.0 V, V- = -10 V,
VI+ = GND, V I- = 0 V,
EN = open
V
1
1
1
200
1
2
50
JlA
1
3
-3.1
-1.4
mA
1
1
-3.1
-1.3
mA
1
2,3
2.0
JlA
1
1
5.0
I.IA
1
2
-1.5
mA
1
1,2,3
100
-2.1
mA
1
1
-2.0
mA
1
2
-2.3
mA
1
3
-2.4
mA
1
1
-2.3
mA
1
2
3
-2.6
VIL(EN)
Input Voltage LOW
4.5 V--..,....I--fo)
~
~~~LHIr-
OUT
PRR = 500 kHz
Amplitude = -10 V
Pulse Width = 1 ~s
tr =tj = 20 ns
Vo
~1.5V
CR05060F
TESTS
tpLH, tpHL
CONDITIONS
(0C)
V+
(Volts)
V(Volts)
R
(kil)
25
5.0
-13
3.75
TA
16-36
IlA962SQB
/-IA9625QB
Electrical Characteristics
Symbol
Characteristic
Condition
Min
Unit
Note
V
1
1
V
1
2,3
V
1
1,2,3
V
1
1,2,3
-3.0
V
1
1,2,3
V
1
1,2,3
210
IJ.A.
1
1,2,3
Max
VOH
Output Voltage HIGH
V+ = 4.5 V, V- = -11 V,
IOH =-60 IJ.A.
2.6
VOL
Output Voltage LOW
V+ = 5.5 V, V- =-11 V,
IOL = 1.5 mA
0.5
V+=4.5V,V-=-11 V,
IOL = 1.2 mA
0.5
2.5
Subgrp
VIH
Input Voltage HIGH 7
VIL
Input Voltage LOWs
IF
Input Load Current
V+ =5.0 V, V-=-13 V,
VF = -3.0 V
ICEX
Output Leakage Current
V+ = VCEX = 4.5 V,
V- =-13 V
50
IJ.A.
1
1
I+ L
Positive Supply Current LOW
V+ = 5.5 V, V- = -15 V,
VI =-10 V
4.8
mA
1
1
I+H
Positive Supply Current HIGH
V+ = 5.5 V, V- =-15 V,
VI=O V
2.1
mA
1
1
1-
Negative Supply Current
V+ =5.5 V, V-=-15 V,
Input Open or Gnd
-9.0
mA
1
1
I-Max
Negative Supply Current Maximum
V+ = 8.0 V, V- = -20 V,
VI =0 V
-25
mA
1
1
tpLH
Propagation Delay to High Level
V+ = 5.0 V, V- =-13 V,
(See Fig. 1)
100
ns
2
9
tpHL
Propagation Delay to Low Level
150
ns
2
9
-9.0
16-37
J,lA9625QB
Primary Burn-In Circuit
5V
-15V
Equivalent Circuit
V+
10kQ
5kQ
5kQ
10kQ
OUTA OUTB
22kQ
INB
3kQ
3kQ
V-
16-38
MA9627QB
FAIRCHILD
Dual Line Receiver
A Schlumberger Company
MIL-STO-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
16-Lead DIP
(Top View)
The J-!A96270B is a dual line receiver which meets the
electrical interface specifications of EIA RS-232C and
MIL-STD-188C. The input circuitry accomodates ±25 V input signals and the differential inputs allow user selection
of either inverting or non-inverting logic for the receiver
operation. The fJA96270B provides both a selectable hysteresis range and selectable receiver input resistance.
When lead 1 is tied to V-, the typical switching pOints are
at 2.6 V and -2.6 V, thus meeting RS-232-C requirements.
When lead 1 is open, the typical switching points are at
50 fJA and -50 fJA, thus satisfying the requirements of
MIL-STD-188C LOW level interface. Connecting the R lead
to the (-) input yields an input impedance in the range of
3 kn to 7 kn and satisfies RS-232-C requirements; leaving R unconnected, the input resistance will be greater
than 6 kn to satisfy MIL-STD-188C.
16
HYSTERESIS
OUTA
OUTB
STROBE A
STROBEB
NC
NC
-INA
-INB
RA
The output circuitry is TTL/DTL compatible and will allow
"collector-dotting" to generate the wired-OR function. A
TTL/DTL strobe is also provided for each receiver.6
•
•
•
•
•
•
•
•
v+
RB
+INA
+INB
v-
GNO
EIA RS-232-C Input Standards
MIL-STD-188C Input Standards
Variable Hysteresis Control
High Common Mode Rejection
R Control (5 kn Or 10 kn)
Wired-OR Capability
Choice Of Inverting And Non-Inverting Inputs
Outputs And Strobe TTL Compatible
Order Information
Part No.
fJA9627DMOB
Case I
Finish
EA
Package Code
MiI-M-38510, Appendix C
D-2 16-Lead DIP
•
16-39
tLA9627QB
Absolute Maximum Ratings
Processing: MIL-STD-883, Method 5004
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation?
DIP
V+ to GND
V- to GND
Input Voltage Referred to GND
Strobe to GND
Applied Output Voltage
-65°C to + 175°C
-55°C to +125°C
300°C
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
400 mW
OVto+15V
OVto-15V
±25 V
-0.5 V to +5.5 V
-0.5 V to +15 V
Group A Electrical Tests Subgroups:
1.
2.
3.
9.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
AC tests at 25°C
Group C and 0 Endpoints: Group A, Subgroup
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
?
Data Book Commercial Section.
Rating applies to ambient temperatures up to 12S"C. Above 12S"C
ambient, derate linearly at 120°C/W.
Figure 1 Switching Time Test Circuit and Waveforms
Vo
-S.OV
+IN
R
PRR = 10kHz
PW = SOfLS
t,=t,=Sns
V,
-IN
-5.0V
3.92kQ
- - - v+
=12V
±1%
~GND
Vo
- - - V-=-12V
HYSOPEN
15 pF includes jig capacttance.
All diodes are FD777 or equivalent.
16-40
MA9627QB
J,lA9627QB
Electrical Characteristics Hysteresis, -IN A, -IN B, RA, and RB Open for MIL-STD-1BBC, unless otherwise
specified.
Symbol
Characteristic
Condition
Min
VOL
Output Voltage LOW
V+ = 10.8 V, V- = -13.2 V,
VI+ = 0.6 V, IOL = 6.4 mA
VOH
Output Voltage HIGH
V+ = 10.8 V, V- =-13.2 V,
VI+ = 0.6 V, 10H = -0.5 mA
2.4
los
Output Short Circuit Current
V+ = 13.2 V, V- = -10.8 V,
VI+ = 0.6 V, Outputs
Grounded
-3.0
IIH(ST)
Input Current HIGH (Strobe)
V+ = 10.8 V,
V- =-13.2 V,
VI+ =0.6 V
Unit
Note
V
1
Subgrp
1,2,3
V
1
1,2,3
mA
1
1,2,3
40
p.A
1
1,2,3
VST = 5.5 V
1.0
mA
1
1,2,3
kU
1
1,2,3
/lA
1
1,2,3
p.A
1
1,2,3
V
1
1,2,3
V
1
1,2,3
18
mA
1
1,3
12.4
mA
1
2
-16
mA
1
1,3
-11.4
mA
1
2
Input Resistance
V+ = 13.2 V, V- =-13.2 V,
-3.0 V~VI+ ~3.0 V
ITH+
Positive Threshold Current
± 10.8 VS.Vccs. ± 13.2 V,
Vo = 2.4 V
ITH-
Negative Threshold Current
±10.8 V~Vcc~ ±13.2 V,
Vo = 0.4 V
VldST)
Input Voltage LOW (Strobe)
VI+ =-0.6 V
VIH(ST)
Input Voltage HIGH (Strobe)
V+ = 13.2 V, V- =-10.8 V,
VI+ =-0.6 V
1+
Positive Supply Current
±10.8 V~Vcc~ ±13.2 V
VI+ =-0.6 V
Negative Supply Current
0.4
VST = 2.4 V
RI
1-
Max
6.0
100
-100
0.8
±10.8 V~Vcc~ ±13.2 V
VI+ = 0.6 V
2.0
Electrical Characteristics +IN A and -IN B connected to ground, AA and AB connected to -IN A and
-IN B, and Hysteresis connected to V- for RS-232C, unless otherwise specified.
Symbol
RI
Characteristic
Input Resistance
Condition
3.0
V~VI~25
-3.0 V ~ VI
VI
V
~-25
V
Input Voltage
VTH+
Positive Threshold Voltage
VTH-
Negative Threshold Voltage
Min
Max
Unit
Note
Subgrp
3.0
7.0
kU
1
1,2,3
3.0
7.0
kU
1
1,2,3
-2.0
2.0
V
1
1,2,3
3.0
V
1
1,2,3
V
1
1,2,3
-3.0
Electrical Characteristics Vee = ± 12 V for MIL-STD-1BBC and AS-232C
Symbol
Characteristic
Condition
tpLH
Propagation Delay to High Level
(See Fig. 1)
tpHL
Propagation Delay to Low Level
(See Fig. 1)
16-41
Min
Max
Unit
Note
250
ns
2
9
250
ns
2
9
Subgrp
Primary Burn-In Circuit
y
1.2kO
1/4W_
2 kO
12V
HVS
1
V+
1.2 kO
1/4W
1/4W
OUTA
STROBE A
-
NC
-INA
-
RA
+INA
> - - - GNO
OUT B
STROBE B
NC
-
-INS
RB
+INB ~
V-
~
r-----
-=
-12 V
Equivalent Circuit (112 of circuit)
v+----------------~----_.------~------~------------------------_1--_.------~--------C1
1.1pF
+ IN
Rl1
R43
1.2BkQ
700Q
--...,..-i'(-.,--,
Rl
8kQ
R2
11.3kQ
R
R4
2kQ
=
R34
11.3kQ
R41
3.2kQ
07
v- ______~~----+_----~----~------------~----------~-----------+--~----~-HVS---------4----~------------------------------------------------------------------
16-42
IlA9636AQB
Dual Programmable
Slew Rate Line Driver
FAIRCHIL.D
A Schlumberger Company
MIL-STD-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
8-Lead DIP
(Top View)
The IlA9636AOB is a TTL/CMOS compatible, dual, single
ended, line driver which has been specifically designed to
satisfy the requirements of EIA Standard RS-423.
The IlA9636AOB is suitable for use in digital data transmission systems where Signal wave shaping is desired.
The output slew rates are jointly controlled by a single
external resistor connected between the wave shaping
control lead (WS) and ground. This eliminates any need
for external filtering of the output signals. Output voltage
levels and slew rates are independent of power supply
variations. Current limiting is provided in both output
states. The IlA9636AOB is designed for nominal power
supplies of ± 12 V.
WAVESHAPE
CONTROL
INA
OUT A
INB
OUTB
GND
V-
Order Information
Inputs are TTL compatible with input current loading low
enough (1/10 UL) to be compatible with CMOS logic also.
Clamp diodes are provided on the inputs to limit transients
below ground. 6
•
•
•
•
V+
Part No.
J.LA9636AR MOB
Casel
Finish
PA
Package Code
MiI-M-38510, Appendix C
D-4 8-Lead DIP
Programmable Slew Rate Limiting
Meets EIA RS-423 Requirements
Output Short Circuit Protection
TTL And CMOS Compatible Inputs
II
16-43
/JA9636AQB
Absolute Maximum Ratings
Processing: MIL-STD-883. Method 5004
-65°C to + 175°C
-55°C to + 125°C
300°C
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 10
DIP
V+ to GND
V- to GND
V+ to VOutput to GND
Output Source Current
Output Sink Current
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
400 mW
V- to +15 V
0.5 V to -15 V
o to +30 V
± 15 V
-150 mA
150 mA
Group A Electrical Tests Subgroups:
1.
2.
3.
9.
Static tests
Static tests
Static tests
AC tests at
at 25°C
at 125°C
at -55°C
25°C
Group C and D Endpoints: Group A, Subgroup
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests. Group C
4. Guaranteed but not tested
5. When changes occur. FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. Only one output shorted at a time.
8. VIH is guaranteed by the VOH test.
9. V,L is guaranteed by Ihe VOL test.
10. Rating applies to ambient temperatures up to 125·C. Above 125·C
ambient, derate linearly at 120·C/W.
Figure 1 Switching Time Test Circuit and Waveforms
+ 12V
v,-........p---I
,~o---p---p---vo
4500
510
CL
30pF
-12 V
C L includes jig and probe capacitance
V,
Amplitude - 3.0 V
Offset - 0 V
Pulse Width - 500 IlS
PRR = 1 kHz
t,-I,-10ns
16-44
MA9636AQB
1lA9636AQB
Electrical Characteristics 10.8 V'" V+ '" 13.2 V, -13.2 V'" V- '" -1 0.8 V, and 10 kS1 '" Rws '" 500 kS1,
unless otherwise specified.
Symbol
Characteristic
Condition
Min
Max
Unit
Note
5.0
6.0
V
1
1,2,3
5.0
6.0
V
1
1,2,3
4.0
6.0
V
1
1,2,3
-6.0
-5.0
V
1
1,2,3
RL to GND (RL = 3.0 kS1)
-6.0
-5.0
V
1
1,2,3
RL to GND (RL = 450 S1)
-6.0
-4.0
V
1
1,2,3
50
S1
1
1,2,3
VOH1
Output Voltage HIGH
RL to GND (RL = 00)
VOH2
Output Voltage HIGH
RL to GND (RL = 3.0 kS1)
VOH3
Output Voltage HIGH
RL to GND (RL = 450 S1)
Vou
Output Voltage LOW
RL to GND (RL = 00)
VOL2
Output Voltage LOW
VOL3
Output Voltage LOW
Ro
Output Resistance
RL =450 S1
los+
Positive Output Short Circuit Current?
Vo = 0 V, VI = 0 V,
Rws =10 kS1
los-
Negative Output Short Circuit Current?
Vo = 0 V, VI = 2.0 V,
Rws=10 kS1
ICEX
Output Leakage Current
Vcc= 0 V, Vo= ± 6.0 V,
Rws = 10 kS1
VIH
Input Voltage HIGH8
VIL
Input Voltage LOW9
VIC
Input Clamp Diode Voltage
II = 15 mA
-1.5
IlL
Input Current LOW
VI = 0.4 V
-80
IIH
Input Current HIGH
VI = 2.4 V
10
VI = 5.5 V
-150
-15
mA
1
1,2,3
15
150
rnA
1
1,2,3
-100
100
p.A
1
1,2,3
V
1
1,2,3
0.8
V
1
1,2,3
V
1
1,2,3
p.A
1
1,2,3
p.A
1
1,2,3
100
p.A
1
1,2,3
18
mA
1
1,2,3
rnA
1
1,2,3
1.4
/lS
1
9
2.0
1+
Positive Supply Current
V+ = 12 V, V- =-12 V,
RL = 00, Rws = 100 kS1,
VI=O V
1-
Negative Supply Current
V+ = 12 V, V- =-12 V,
RL = 00, Rws = 100 kS1,
VI=O V
t,
Rise Time
Rws = 10 kS1
0.8
(See Fig. 1)
tf
Subgrp
-18
Rws = 100 kS1
8.0
14
/lS
1
9
Rws =500 kS1
40
70
/lS
1
9
Rws = 1000 kS1
80
140
/lS
1
9
Fall Time
Rws =10 kS1
0.8
1.4
JJ.S
1
9
(See Fig. 1)
Rws = 100 kS1
8.0
14
/lS
1
9
Rws = 500 kS1
40
70
JJ.S
1
9
Rws= 1 MS1
80
140
/lS
1
9
16-45
Primary Burn-In Circuit
100kO
1/4W
15Y
y.
+------1 IN A
OUT A
+------1 IN B
OUTB
t - - - - - - i GND
Y-
-15Y
Equivalent Circuit
r---------------~
R18
400U
TO
D22~t"
WClM
--;l
J
~
*~~027
~
~D15
Rl7
8.58 kU
A
~~
R7
~
~01S
I
~
r---<
r K-->
D12'
~
D13
...
...... D5
......
D8~7
7D3
~
~
~10
r--
7D1
R19
V
a.
~=
~
~~D18
10
OTHER
CHANNEL
t;122
TO
020 ........
OTHER
CHANNEL
.......
R13
10kU
R12
SOOU
~
RS
R4
[~CU3
~
,........,
'cii9'
V 016
.....
V019
......
R15
10 kO
01
r-J(02
C1
'---
..-.~
cu;; "
R14
380U
k
012
......
GND
R1
71
702
Io,~
J-
~ OUT
'04
....
......011
CHANNEL
R2
81
r.:f
~7D14
OTHER
U'D
V03
.......-
D20
~~D17
i7
~
~t'D11
o
05
D8~"
[ CU5
...-
D16
O~
as
I
I
......028
~~D21
I
I
I
I
I
I
I
I
I
I
IN
I
I
I
I
028~
OTHER
CHANNEL
TO
I
WSCIN
10
OTHER
CHANNEL
R6
25kU
R6
2.53 kll
V 017
......
V
018
"f
R9
910U
TO
OTHER
CHANNEL
L _______________ .J
-
-
Y-
o
-
= COMMON TO BOTH CHANNELS
= CROBSUNDER
16-46
JlA9637AQB
FAIRCHIL.O
A Schlumberger Company
Dual Differential
Line Receiver
MIL-STD-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
a-Lead DIP
(Top View)
The !1A9637 AOB is a Schottky dual differential line receiver which has been specifically designed to satisfy the requirements of EIA Standards RS-422 and RS-423. In
addition, the !1A9637 AOB satisfies the requirements of
MIL-STD 188-114 and is compatible with the International
Standard CCITT recommendations. The MA9637 AOB is
suitable for use as a line receiver in digital data systems,
using either single ended or differential, unipolar or bipolar
transmission. It requires a single 5 V power supply and
has Schottky TTL compatible outputs. The MA9637AOB
has an operational input common mode range ± 7 V either
differentially or to ground. 6
•
•
•
•
•
•
•
•
Dual Channels
Single 5 V Supply
Satisfies EIA Standards RS-422 and RS-423
Built In ± 35 mV Hysteresis
High Common Mode Range
High Input Impedance
TTL Compatible Output
Schottky Technology
Vee
+INA
OUT A
-INA
OUTB
+lNB
GND
-INS
Order Information
Part No.
MA9637ARMOS
Casel
Finish
PA
Package Code
MiI-M-38510, Appendix C
D-4 8-Lead DIP
•
16-47
IlA9637AQB
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power DissipationS
DIP
Supply Voltage
Input Voltage
Differential Input Voltage
Output Voltage
Output Sink Current
-65°C to + 175°C
-55°C to + 125°C
300°C
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
400 mW
-0.5 V to +7.0 V
± 15 V
± 15 V
-0.5 V to +5.5 V
50 mA
Group A Electrical Tests Subgroups:
1.
2.
3.
9.
Static tests
Static tests
Static tests
AC tests at
at 25°C
at 125°C
at -55°C
25°C
Group C and D EndpOints: Group A, Subgroup
Notes
1.
2.
3.
4.
5.
100% Test and Group A
Group A
Periodic tests, Group C
Guaranteed but not tested
When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. Only one output should be shorted at a time.
8. Rating applies to ambient temperatures up to 125·C. Above 125·C
ambient. derate linearly at 120·C/W.
Figure 1 Switching Time Test Circuit and Waveforms
Vee =5.0V
Vee
=S.ov
-O~V----'~~
51!)
Vo
CL includes jig and probe capacitance.
All diodes are FD700 or equivalent
-b.
+0.5V------,-----_
v,
---I1r---,·5V,.5V\,----
V,
Amplitude ~ 1.0 V
Offset ~ 0.5 V
Pulse Width ~ 100 ns
PRR ~ 5.0 MHz
t r =tf=5.0 ns
16-48
JlA9637AQB
IlA9637AQB
Electrical Characteristics 4.5 V';;; Vee';;; 5.5 V, unless otherwise specified.
Symbol
Characteristic
Min
Max
Unit
Note
VTH
Differential Input Threshold Voltage
VCM = !7.0 V
Condition
-0.2
0.2
V
1
1,2,3
VTH(R)
Differential Input Threshold Voltage
Resistor
VCM = !7.0 V
-0.4
0.4
V
1
1,2,3
II
Input Current
o V';;;Vec';;;5.5
3.25
mA
1
1,2,3
mA
1
1,2,3
V
1
1,2,3
V
1
1,2,3
-40
rnA
1
1,2,3
V
I VI+ = 10 V
I VI+ =-10 V
-3.25
Subgrp
VOL
Output Voltage LOW
Vee = 4.5 V, 10L = 20 mA
VOH
Output Voltage HIGH
Vee = 4.5 V, 10H = -1.0 rnA
los
Output Short Circuit Current?
Vee = 5.5 V, Vo = 0 V
Icc
Supply Current
Vee = 5.5 V, VI+ = 0.5 V,
VI- =GND
50
rnA
1
1,2,3
tpLH
Propagation Delay to High Level
Vec = 5.0 V (See Fig. 1)
25
ns
2
9
tpHL
Propagation Delay to Low Level
25
ns
2
9
16-49
0.5
2.5
-100
I-lA9637AQB
Primary Burn-In Circuit
5V
+IN A I - - - - - - i
OUT A
-INA
OUTB
+IN B
GNO
-INB
1 - - - 1 - -......
Cfl04180F
Equivalent Circuit
r--------~-------_.-----~---~-_t-----t_--VCC
R7
RS
R24
R23
RIS
+-------t--,
02
Cl
5pF
+IN ---<~-.NI/'-""'--4
OUT
-IN ------ El.2
B5-
>--- 82
C4
100 kCl
1/4W
100 kO
1/4W
C2
E4_
> - - - 83
84_
>--- E3
C3
.".
100 kCl
1/4W
18-6
I1A555Q8
Single Timing Circuit
FAIRCHILD
A Schlumberger Company
MIL-STD-883
July 1986-Rev 15
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
8·Lead DIP
(Top View)
The MA555QB Timing Circuit is a very stable controller for
producing accurate time delays or oscillations. In the time
delay mode, the delay time is precisely controlled by one
external resistor and one capacitor; in the oscillator mode,
the frequency and duty cycle are both accurately controlled with two external resistors and one capacitor. By
applying a trigger signal, the timing cycle is started and an
internal flip-flop is set, immunizing the circuit from any further trigger Signals. To interrupt the timing cycle a reset
Signal is applied ending the time-out.
TRIGGER
DISCHARGE
OUT
THRESHOLD
The output is compatible with TTL circuits and can drive
relays or indicator lamps.6
•
•
•
•
•
•
•
Vee
GND
CONTROL
VOLTAGE
RESET
Timing Control, IJS To Hours
Astable Or Monostable Operating Modes
Adjustable Duty Cycle
High Sink Or Source Output Current
TTL Output Drive Capability
Low Temperature Stability
Normally ON Or Normally OFF Output
Connection Diagram
8·Lead Can
(Top View)
Vee
RESET
Order Information
Part No.
MA555HMQB
IlA555RMQB
Casel
Finish
GC
PA
JAN Product Available
10901
BGC
10901
BPA
10901
BPB
18-7
Package Code
MII-M-38510, Appendix C
A-1 (8-Lead Can)
D-4 (8-Lead DIP)
A-1 (a-Lead Can)
D-4 (8-Lead DIP)
D-4 (8-Lead DIP)
#-lA555QB
Processing: MIL-STD-883, Method 5004
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation 7
Can
DIP
Supply Voltage
Discharge Current
Output Sink Current
Output Source Current
-65°C to 175°C
-55°C to 125°C
300°C
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
330 mW
400 mW
±18 V
200 mA
200 mA
-200 mA
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
10.
11.
Static tests at 25°C
Static tests at 125°C
Static tests at -55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
Dynamic tests at -55°C
AC tests at 25°C
AC tests at 125°C
AC tests at -55°C
Group C and D Endpoints: Group A, Subgroup 1
Notes
1. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. Rating applies to ambient temperatures up to 125·C. Above 125'C
ambient, derate linearty at 150'C/W for the Can and 120'C/W for the
DIP.
18-8
IlA555Q8
Electrical Characteristics 4.5 V';;; Vee';;; 16.5 V, unless otherwise specified.
Symbol
Characteristic
Condition
Min
Max
Unit
Note
12
mA
1
1,2,3
5.0
mA
1
1,2,3
10.3
V
1
1,2,3
V
1
1,2,3
1,2,3
Icc
Supply Current
Vee=15 V, RL=oo
VTH
Threshold Voltage
Vee=15 V
9.7
Vee = 5.0 V
3.0
3.6
Vee = 5.0 V, RL =
VTA
Trigger Voltage
00
Vee=15 V
4.8
5.2
V
1
Vee = 5.0 V
1.45
1.9
V
1
1,2,3
Vee = 15 V
-5.0
/lA
1
1,2,3
ITA
Trigger Current
VA
Reset Voltage
5.0 V';;;Vee<15 V
IA
Reset Current
Vee=15 V
ITH
Threshold Current
Vee=15 V
Vev
Control Voltage Level
Vee=15 V
9.6
10.4
Vee = 5.0 V
2.9
3.8
VOL
Output Voltage LOW
Vee=15 V
0.1
1.0
V
1
1,2,3
-1.6
0
mA
1
1,2,3
0.25
/lA
1
1,2
2.5
/lA
1
3
V
1
1
V
1
1
0.15
V
1
0.25
V
1
0.5
V
1
0.7
V
1
2
2.2
V
1
1
2.8
V
IOL = 200 mA
3.5
V
1
1
IOL =8.0 mA
0.25
V
1
1
0.35
V
1
2,3
IOL = 10 mA
IOL = 50 mA
IOL = 100 mA
Vee = 5.0 V
VOH
Output Voltage HIGH
Vee=15 V
Vee = 5.0 V
1
2
1,3
--2,3
--- ---
IOH =-200 mA
11
V
1
1
13
V
1
1,2,3
IOH =-100 mA
3.0
V
1
1,2
2.0
V
1
3
nA
1
1
1,3
2
Discharge Leakage
Current
Vee = 15 V, VD = 15 V
VSAT
Discharge Saturation
Voltage
Vee = 5.0 V, IOL = 5.0 mA
tpLH
Propagation Delay to
High Level (Monostable)
tTLH
Transition Time to High
Level (Monostable)
tTHL
Transition Time to Low
Level (Monostable)
tD(OH)
Time Delay High
(Monostable)
RT = 1.0 kn, CT = 0.1 /IF
Drift in Time Delay vs.
Change in Supply
Voltage (Monostable)
~Vee
---
1,3
---
IOH =-100 mA
leEx
~tD(OH)/
Subgrp
95
5.0
/lA
0.25
0.4
V
1
1
1,3
V
RT = 1.0 kn, CT = 0.1 /IF
900
ns
3
10
800
ns
3
9,11
RT = 1.0 kn, CT = 0.1 /IF
300
ns
3
9,10,11
300
ns
3
9,10,11
106.7
113.3
/lS
3
9,10,11
RT = 100 kn, CT = 0.1 /IF
10.67
11.33
ms
3
9,10,11
~Vee = 12 V, RT = 1.0 kn,
CT = 0.1 /IF
-220
220
nslV
4
9
18-9
2
•
JIA555QB
MA555QB (Cont.)
Electrical Characteristics 4.5 V < Vee < 16.5 V, unless otherwise specified.
Symbol
Characteristic
Condition
Min
kn, CT = 0.1 /IF
tPHL
Propagation Delay Time
(Threshold to Output)
(Monostable)
RT = 1.0
~tpH(OH)1
Temperature Coefficient
of Time Delay
(Monostable)
Vcc = 16.5 V
Capacitor Charge Time
(Astable)
CT= 0.1 /IF
tDIS
Capacitor Discharge
Time (Astable)
CT = 0.1 IlF
~teHI
Drift in Capacitor
Charge Time vs Change
in Supply Voltage
(Astable)
~Vce=
12 V, RTA = RTS = 1.0
CT=O.l/lF
Temperature Coefficient
of Capacitor Charge
Time
Vcc = 16.5 V
RTA = RTB
= 1.0 kn,
CT = 0.1 /IF
Reset Time
Vce = 16.5 V,
RTA = RTB = 1.0
CT= 0.1 /IF
~T
tCH
~Vce
tCH/~T
tres
Note
Subgrp
/lS
3
9,10,1
-11
11
ns/oC
3
10
-55°C
<: TA <: 25°C
-11
11
nsrC
3
11
RTA
RTB = 1.0
kn
120
156
/lS
3
9,10,1
kn
11.3
15
ms
3
9,10,1
57.5
80
/lS
3
9,10,1
=
RTA = RTB = 100
RTA = RTB = 1.0
kn
kn
5.4
7.7
ms
3
9,10,1
-820
820
ns/V
4
9
25°C <: TA <: 125°C
-68
68
ns/oC
3
10
<: TA <: 25°C
-68
68
ns/oC
3
11
2.0
/lS
3
10
1.5
/lS
3
9,11
RTA = RTB = 100
-55°C
kn,
kn
Block Diagram
12 V
~
Unit
12
<: TA <: 125°C
25°C
Primary Burn-In Circuit
(38510/10901 may be used by FSC as an alternate)
GND
Max
Vee
Vee
5.0 kO
DISCH
THRESHOLD
CONTROL
VOLTAGE
10kO
TRIGGER DISCHARGE
R
FLlP·FLOP
~
OUT
--
RESET
1 kO
THRESHOLD
CONTROL
VOLTAGE
5.0 kO
r-
S INHIBIT!
RESET
TRIGGER
5.0 kO
RESET
GND
18·10
"::"
Q
OUT
JlA733Q8
FAIRCHILO
A Schlumberger Company
Differential Video
Amplifier
MIL-STD-883
July 1986-Rev 25
Aerospace and Defense Data Sheet
Linear Products
Description
Connection Diagram
10-Lead Can
(Top View)
The !lA73308 is a monolithic two-stage differential input,
differential output video amplifier constructed using the
Fairchild Planar Epitaxial process. Internal series shunt
feedback is used to obtain wide bandwidth, low phase distortion, and excellent gain stability. Emitter follower outputs
enable the device to drive capacitive loads and all stages
are current source biased to obtain high power supply and
common mode rejection ratios. It offers fixed gains of 10,
100 or 400 without external components, and adjustable
gains from 10 to 400 by the use of a single external resistor. No external frequency compensation components
are required for any gain option. The device is particularly
useful in magnetic tape or disc file systems using phase
or NRZ encoding and in high speed thin film or plated
wire memories. Other applications include general purpose
video and pulse amplifiers where wide bandwidth, low
phase shift, and excellent gain stability are required. 6
•
•
•
•
G2A
vLead 5 connected to case.
Connection Diagram
14-Lead DIP
(Top View)
Wide Bandwidth
High Input Resistance
Selectable Gains Of 10, 100, And 400
No Frequency Compensation Required
14
IN'
NC
Connection Diagram
14-Lead Flatpak
(Top View)
GOA
G'A
IN 2
IN'
NC
NC
G,.
G2A
G,.
G'A
V+
NC
v-
v+
NC
NC
OUT 2
OUT'
OUT 1
Order Information
Part No.
!lA733DM08
!lA733HM08
IlA733FM08
Casel
Finish
CA
IC
AA
Package Code
MiI-M-38510, Appendix C
0-1 14-Lead DIP
A-2 10-Lead Can
F-1 14-Lead Flatpak
•
18-11
IlA733Q8
Absolute Maximum Ratings
Storage Temperature Range
Operating Temperature Range
Lead Temperature (soldering, 60 s)
Internal Power Dissipation9
Can and Flatpak
DIP
Supply Voltage
Differential Input Voltage
Input Voltage
Output Current
Processing: MIL-STD-883, Method 5004
-65°C to 175°C
-55°C to 125°C
300°C
330 mW
400 W
±8 V
±5 V
±6 V
10 mA
Burn-In: Method 1015, Condition A, PDA calculated
using Method 5005, Subgroup 1
Quality Conformance Inspection: MIL-STD-883,
Method 5005
Group A Electrical Tests Subgroups:
1.
2.
3.
4.
5.
6.
9.
Static tests at 25°C
Static tests at 125°C
Static tests at - 55°C
Dynamic tests at 25°C
Dynamic tests at 125°C
Dynamic tests at -55°C
AC tests at 25°C
Group C and 0 Endpoints: Group A, Subgroup 1
Notes
I. 100% Test and Group A
2. Group A
3. Periodic tests, Group C
4. Guaranteed but not tested
5. When changes occur, FSC will make data sheet revisions available.
Contact local sales representative for the latest revision.
6. For more information on device function, refer to the Fairchild Linear
Data Book Commercial Section.
7. VIR is guaranteed by the CMR test.
8. Gain Select leads GIA and GI B are connected together for Gain I,
Gain Select leads G2A and G2B are connected together for Gain 2,
and all Gain Select leads are left open for Gain 3.
9. Rating applies to ambient temperatures up to 125·C. Above 125·C
ambient, derate linearly at 140·C/W for the Can, 150·C/W for the
Flatpak, 120·C/W for the DIP.
18-12
J..LA733Q8
Electrical Characteristics Vee = ± 6.0 V, unless otherwise specified.
Symbol
110
Characteristic
Condition
Min
Input Offset Current
liB
Input Bias Current
ZI
Input Impedance
Max
Note
3.0
JJ.A
1
1
5.0
jJA
1
2,3
20
JJ.A
1
1
2,3
40
Icc
Gain 2
JJ.A
1
20
kn
1
1
8.0
kn
1
2,3
Supply Current
CMR
Common Mode Rejection
VIR
Input Voltage Range?
PSRR
Power Supply Rejection Ratio
5.5 V~V+ ~S.5 V,
V- = -S.O V, Gain 2
Vos
Output Offset Voltage
Gain 1
Gain 2,3
VCM = ± 1.0 V, Gain 2
24
mA
1
1
27
mA
1
2,3
60
dB
1
1
50
dB
1
2,3
± 1.0
V
1
1,2,3
50
dB
1
1,2,3
1.5
V
1
1,2,3
1.0
V
1
1
1.2
V
1
2,3
3.4
V
1
1
mA
1
1
VCMO
Output Common Mode Voltage
2.4
10-
Output Sink Current
2.5
A
Differential Voltage Gains
2.2
Gain 1
Gain 2
Gain 3
VOP
Output Voltage Swing
tR
Risetime
Rs = 50 n, Vo = 1 Vp _ p,
Gain 2
tpD
Propagation Delay
Rs=50
Gain 2
n,
Vo=1 Vp _ p,
18-13
Subgrp
Unit
mA
1
2,3
300
500
VIV
1
4
200
SOO
VIV
1
5,6
4
90
110
VIV
1
80
120
VIV
1
5,S
9.0
11
VIV
1
4
8.0
12
5,6
VIV
1
3.0
Vp _ p
1
4
2.5
Vp _ p
1
5,S
10
ns
2
9
10
ns
2
9
JlA733QB
Primary Burn-In Circuit
IV
IN 1
GOA
IN2
G,.
G..
V+
G,.
oun
v-
OUT 2
12 V
":"
OR_
Equivalent Circuit
V+
IN1
t---;--oUT 1
UT2
R14
4000
VEOOOS11F
18-14
Package Outlines
FAIRCHILD
A Schlumberger Company
3 Lead Molded Package
In Accordance with JEDEC TO·92
EI
1..-.195 (4.95)--1
I
.175 (4.45)
I
Notes
Leads are solder dipped copper alloy.
Lead No. 2 connected to die pad.
Package material is plastic.
Package weight is 0.19 gram.
,,, -- ,
.190 (4.83)
.170 (4.32)
SEATING
PLANE
I
'_ ... "
t
Dimensions -.055 (1.40)
and -.105 (2.67)
are measured
.045
.525 (13.34)
.475 (12.07)
~
,
I
I
.:~~g~~ - H
.
1.14
.095
2.41
at the body of package .
~ ~ .022 (0.56)
.016(0.41)
:~~ ~~:~~~
LEAD NO. 3
LEAD NO. 2
LEAD NO. 1
.105 (2.87)
.080 (2.03)
POOOO10F
3 Lead Metal Package
In Accordance with JEDEC TO·39
Fe
.370 (9.40)
.350(8.89)
Notes
Leads. are gold plated kovar.
Leads 1 and 2 are electrically isolated with glass .
Lead No. 3 connected to case.
Eyelet is gold plated kovar.
Can is Grade A nickel.
Package weight is 1.23 grams.
DIA
~ .335
(8.51)1
. 315 (8.00)
DlA
~
.034(0.864)
--L-
.165 (4.19)
~
3 PlNS___
0.19 (0.48)
0.I':,l~·41)
--+SEATING PLANE
~
.565 (14.35)
.500 (12.70)
!
PIN 2
All dimensions in inches (bold) and millimeters (parentheses)
19-3
Package Outlines
18 Lead Ceramic DIP
Side Brazed Package
.
915(2324)
~-"'."
1.
FD
Notes
Leads are nickel and gold plated alloy 42 or kovar.
Package material is alumina.
Combo-lid is gold plated kovar or alloy 42 .
I
440 (".,8)-----1
.425(10.80)
18
.050(1.27) R
NOM
~
~
,-
~
INDEX MARK
17
Leads are intended for insertion in hole rows on .300
11
10
I
.305(7.75)
.285(7.24)
8
.155(3.94)
.110(2.79)
1
.160(4.06)
.140(3.56)
t
.110(2.79)TYP
.090(2.29)
~
l
f
.325(8 .26)
.295(7 .49)
9~
- - -- -
2
(7.62) centers.
Board drilling dimensions should equal your practice for
.020 (0.51) diameter leads.
Package weight is 1.5 grams .
1
.012(0.30)
.009(0.23)
TYP
j
:~~ ~g~~l TYP
L·020(051)
.016(0 41) TYP
.310(7.87)
.290(7.37)
STANDOFF
WIDTH
20 Lead Ceramic DIP
FL
Notes
Leads are tin-plated alloy 42.
Leads are intended for insertion in hole rows on .300
.025(0.64)R
(7.62) centers.
They are purposely configured with "positive"
misalignment to facilitate insertion.
Board-drilling dimensions should equal your practice for
.020 (0.51) diameter lead.
Hermetically sealed alumina package.
'The .035-.045 (0.89-1.14) dimension does not apply to
the corner leads.
Package weight is 2.8 grams.
NOM
•165(4.19)
.125(3.16)
1..-.410(10.41)--1
NOM
All dimensions in inches (bold) and millimeters (parentheses)
19-4
Package Outlines
28 Lead Ceramic DIP
FM
Note.
Leads are tin-plated alloy 42.
Leads are intended for insertion in hole rows on .600
.025(O.64}A
NOM.
•, 9014.83}
.'~
(IS, 24) centers.
They are purposely configured with "positive"
misalignment to facilitate insertion.
Board drilling dimensions should equal your practice for
.020 (0, 51) diameter lead.
Hermetically sealed alumina package.
Package weight is 8.32 grams.
R=;:::;=;:::;==;::::r=;:::r;:::r=;:::r=;=r"W=;:::;=;:::;==;::::r=;:::r;:::r=;:l:l
I
·20015.OS}
.'2s13.'8}
+
.110(2,79}
·09012,29}
24 Lead Cerpak
.0601'.52}
,0481' .22}
.01510.38}
r
~
.27717.04}+ .3951'O.03}
.36519.27}
.25716,53}"
.0'510.38
015(038} I
I
}!":1
}l
FN
.2771 7.04
.25716.53)
..
Note.
Leads are tin-plated alloy 42.
Increase maximum limits by .003 (0,08) if leads are
solder dipped.
Package weight is 0.68 grams.
.0501'·27}TVP
.O'610.40}
.OOI(0.02}
1213
t=-~::::J:====!:t
.OOSI0.'5}
,G0410.'0}
.0451'·'4}
MAX
All dimensions in inches (bold) and millimeters (parentheses)
19-5
Package Outlines
24 Lead Flatpak
·.330(S.3S)
.310(7.87)
.2S0(7.11)
,.260(6.60).
FR
.330(S.38)
.310(7.87)
Notes
Leads are gold plated alloy 42.
If solder-dipped leads are used, the maximum limits for
these dimensions may be increased by .003 (0,08) .
Package weight is 0.53 grams.
. 015(0.38)
-.i
1
.567(14.40)
10 1213 15
~
.006(0.15)
.004(0.10)
.025(0.64)
.015(0.38)
I
r
.410(10.14)
.3S5 (9.7S)
.300(7.62)
L
JL
REIF
.068(1.73)
.058(1.47)
~--~*~~I~~~I~*~=
~.37)
.050!1.27)
TYP
.090(2.29)
.065(1.65)
r-Ej---r
T
.200(5.0S)
.185(4.70)
32 Lead Flatpak
.32O(S.13)
.300(762)
rl
.767(19.48)
REF
L
.006(0.15)
.004(0.10)
~
.520(13.21)
.480(1219)
[~IN No.1
"'07
32
D
+ :4J34)
J
.800(20.32)
.050(1.27)
TYP
~
l1
1;.37O(9.40
1:-'00(101s)i
Leads are gold plated alloy 42 .
If solder·dipped leads are used, the maximum limits for
these dimensions may be increased by .003 (0,08).
Package weight is 1.97 grams.
I
.440(11.1S)
L
•
17
16
Notes
.040(1.02)
•030t-7S)
I
INDEX
1.
FS
.320(S.13)
.300(762)
.019(0.4S)
.015(0.3S)
TYP
.080(2.03)
.064(1.63)
---.-l
I
-.J
I
.095(2.41)
.075(1.91)
---I
l-
t
.020(0.51 )
.010(0.25)
.370(9.40)
All dimensions in inches (bold) and millimeters (parentheses)
19-6
Package Outlines
2 Lead Metal TO-3
with Moly-Pad
FT
Notes
.072(1.83)
.052(1.32)
.295(7.49)
. 265(6.73)
450~
Base is nickel plated steel.
I
Can is nickel plated steel.
Leads are solder dipped over nickel plated alloy 52 .
Leads 1 and 2 electrically isolated from case with glass .
c::j:I==::;:;:===:q:o---1
1
.
.400(10.16)
Case is third electrical connection .
Package weight is 12.3 grams.
t
Lead No.2
::::i~~~; DIA
2 HOLES
+
Lead No.1
3 Lead Molded Package
In Accordance with JEDEC TO-220
GH
Notes
Leads are solder dipped over nickel plated copper alloy.
Lead No. 2 is electrical contact with the mounting tab.
Mounting tab is nickel plated copper alloy.
Package material is plastic.
Package weight is 2.0 grams.
t*
.060 ('.52)
.045 (1.14)
.185 (4.70)
'"',,,65;-:(;;;4,,",...9)...L_ _-.-_
SEATING
PLANE
'-"'-t-'-'----.'----------';-:~~~ g~!~
.055 (1.40)
.045(1.14)
.030 (0.76)
.013 (0.33)
t
t
~
--I L
-~l
r
SECTION
.040 (1.02)
.025 (0.64)
x-x
All dimensions in inches (bold) and millimeters (parentheses)
19-7
Package Outlines
2 Lead Metal Package
In Accordance with JEDEC TO-3
HJ
Noles
.072 (1.83)
Base is nickel plated steel.
.052 (1.32)
Can is nickel plated steel.
Leads are solder dipped over nickel plated alloy 52.
:;;:;:;:=:J+D~
t
Leads 1 and 2 electrically isolated from case with glass.
Case is third electrical connection.
Package' weight is 12.3 grams .
. 185 (4.70)
.165 (4.19)R
2 PLACES
8 Lead Plastic sOle
KC
Noles
All tolerances are ± .002 (0.05) unless noted.
Leads are solder plated (90Sn/10Pb).
Package material is plastic.
I
t
.154(3.91)
REF ..242(6.15)
.025(0.64)
.230(5.841
=:~J£ I
l"';:;;;==i"'i=::r=:;=;;:;:;;;;;;;::!l
r----1,---
8-------r
.189(480)
--=='11
.050(1'27~.016(0411
TYP.
r- ,
~
)It==========t0:--t .060(1.53)REF.
.010(025)
CIA.TYP.
~
TYP.
.015(O.38)X45~j
.015(0,38)
CIA.TYP.
.197(5 OO)-----j
--------~--~-~~
.024(0,61)
.020(0.51)
All dimensions in inches (bold) and millimeters (parentheses)
19·8
Package Outlines
14 Lead Plastic SOIC
KD
Notes
All tolerances are ± .002 (0.05) unless noted.
Leads are solder plated (90Sn/10 Pb).
Package material is plastic .
1 - - - - - - .340(8,64) - - - - - - 1
.015(0,38)
.015(0,38)
DIA.TYP.
x 45
0
REF'1
.010(0,25)
DIA.TYP.
,
.025(0,64)
~======7==*'n
08O( 53)"EF.
.024(0,61)
.020(0,51)
28 Lead PLCC
.D4S(1.14}><4S0
n'i-----
r
I-=-
.490(\245)
I
LEAD No.1
-'T---L
I
.454111.53)
U'
L'
454 111 5 3 I j
I
r----490(12451=j
1-----+-.172(4.371
KH
Notes
All tolerances are ± .003 unless otherwise noted.
The leads are solder dipped or solder plated copper
alloy.
Package material is plastic.
All dimensions in inches (bold) and millimeters (parentheses)
19-9
Package Outlines
44 Lead PLCC
LEAD No.1 IDENTIFIER
.04S(1.14)X4S"
POLISHED
.654
_____
(1.14)
SEATING PLANE
I
r-
i
.690
.04S
D t
.045(1.14)DIA
SURFACE SPOT
I
.045
(1.14)
+i ____ _
"f '
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date : 2013:08:08 17:35-08:00
Modify Date : 2013:08:09 06:48:21-07:00
Metadata Date : 2013:08:09 06:48:21-07:00
Producer : Adobe Acrobat 9.55 Paper Capture Plug-in
Format : application/pdf
Document ID : uuid:9f36d65c-9d17-2f49-a6d3-2b055ab3b22e
Instance ID : uuid:d00786e0-6829-d844-8242-ad3177dfbbf1
Page Layout : SinglePage
Page Mode : UseNone
Page Count : 1154
EXIF Metadata provided by EXIF.tools