1987_Hitachi_8_16_Bit_Peripheral_LSI_Data_Book 1987 Hitachi 8 16 Bit Peripheral LSI Data Book
User Manual: 1987_Hitachi_8_16_Bit_Peripheral_LSI_Data_Book
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8/16·BIT PERIPHERAL LSI
DATA BOOK
#U70·A
•
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
MEDICAL APPLICATIONS
Hitachi's products are not authorized for use in MEDICAL APPLICATIONS, including, but not limited to, use in life support devices without the
written consent of the appropriate officer of Hitachi's sales company. Buyers
of Hitachi's products are requested to notify Hitachi's sales offices when
planning to use the products in MEDICAL APPLICATIONS.
When using this manual, the reader should keep the following in mind:
1.
This manual may, wholly or partially, be subject to change without
notice.
2.
All rights reserved: No one is permitted to reproduce or duplicate, in
any form, the whole or part of this manual without Hitachi's permission.
3.
Hitachi will not be responsible for any damage to the user that may result
from accidents or any other reasons during operation of his unit according to this manual.
4.
This manual neither ensures the enforcement of any industrial properties or other rights, nor sanctions the enforcement right thereof.
5.
Circuitry and other examples described herein are meant merely to
indicate characteristics and performance of Hitachi semiconductorapplied products. Hitachi assumes no responsibility for any patent infringements or other problems resulting from applications based on the
examples described herein.
6.
No license is granted by implication or otherwise under any patents or
other rights of any third party or Hitachi, Ltd.
August 1987
© Copyright
1987, Hitachi America Ltd.
Printed in U.S.A.
~HITACHI
ii
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
CONTENTS
• GENERAL INFORMATION
• Quick Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• Introduction of Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• Reliability and Quality Assurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
• Reliability Test Data of Microcomputer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
1
12
18
• DATA SHEETS
HD6321
HD6821
HD6340
HD6840
Peripheral Interface Adapter (CMOS) ..........................................
Peripheral Interface Adapter (NMOS) ..........................................
Programmable Timer Module (CMOS) .........................................
Programmable Timer Module (NMOS) .........................................
.
.
.
.
27
27
49
49
HD6844
HD6345
HD6445
HD6845R
Direct Memory Access Controller (NMOS) ...................................... .
CRT Controller (CMOS) ..................................................... .
CRT Controller (CMOS) ..................................................... .
CRT Controller (NMOS) ..................................................... .
66
99
99
139
HD6845S
HD6350
HD6850
HD6852
HD46508
CRT Controller (NMOS) ..................................................... .
Asynchronous Communications Interface Adapter (CMOS) ....................... .
Asynchronous Communications Interface Adapter (NMOS) ....................... .
Synchronous Serial Data Adapter (NMOS) ...................................... .
Analog Data Acquisition Unit (NMOS) ......................................... .
139
181
181
193
207
HD46508A
HD63084
HD63085Y
HD68230
HD63310
Analog Data Acquisition Unit (NMOS) .........................................
Document Image Pre-Processor (CMOS) ........................................
Document Image Compression and Expansion Processor (CMOS) ..................
Parallel Interface Timer (NMOS) ..............................................
Smart Dual Port RAM (CMOS) ...............................................
.
.
.
.
.
207
227
259
273
305
HD63450
HD68450
HD63463
HD63484
Direct Memory Access Controller (CMOS) ...................................... .
Direct Memory Access Controller (NMOS) ...................................... .
Hard Disk Controller (CMOS) ................................................ .
Advanced CRT Controller (CMOS) ............................................ .
307
356
404
472
HD63485
HD63486
HD68562
HD63645
Graphic Memory Interface Controller (Hi-Bi CMOS) ............................. .
Graphic Video Attribute Controller (Hi-Bi CMOS) ............................... .
Dual Universal Serial Communications Controller (NMOS) ....................... .
LCD Timing Controller (CMOS) .............................................. .
531
567
600
603
HD64941
HDl46818
Asynchronous Communications Interface (NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real Time Clock Plus RAM (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hitachi Sales Offices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .
641
644
663
iii
iv
GENERAL
INFORMATION
• Qu ick Reference Gu ide
• I ntroduction of Packages
• Reliability and Quality Assurance
• Reliability Test Data of Microcomputer
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
v
vi
QUICK REFERENCE GUIDE
• 8-BIT MICROCOMPUTER PERIPHERAL
LSI Characteristics
Clock
Type Nol
DIvIsion
Process Frequency
(MHz!
Old Type Name
CMOS
HD6821
HD46821
HD68A21
HD468A21
HD68B21
HD468B21
NMOS
50
-20-+75
15
5.0
-20-+75
Peripheral I ntariaee
FP-54
Adapter
DP-40
1
1.5
5.0
-20-+75
DP-28
5.0
-20-+75
DP-28
2
HD63B40'
1
HD6840
NMOS
1.5
2
HD68840
HD6844
HD46504
HD68A44
HD46504-1
1
HD68B44
HD46504-2
NMOS
1.5
50
-20-+75
DP-4Q
2
1
H06345*
CMOS
HD63A45'
15
HD6845
HD46505R
HD68A45
HD46506R-l
-20-+75
DP-4Q
5.0
-20-+76
DP-4Q
HD68B45
HD46505R-2
HD6B45S
HD46505S-1
HD68A45S
HD46505S-1
HD68B45S
HD46505S-2
1
NMOS
1.5
1
1.5
Adapter
R,ference
Page
27
MC6821
MC68A21
27
MC68B21
Programmable Timer
49
Module
Programmable Timer
Module
Direct Memory
Access Controller
MC6840
MC68A40
49
MC68840
MC6844
MC68A44
66
MC68844
(4.5 MHz HIgh
Speed Dlsplav!
6800 type bus tim Ing
CRT Controller
2
NMOS
Peripheral Interface
Compatibility
CRT Controller
5.0
2
HD63B45'
Function
DP-40
2
CMOS
HD68A40
CRTC
15
1
HD63A40'
DMAC
('C)
2
HD63B21'
HD6340'
PTM
(V!
1
HD6321'
HD63A21'
PIA
qp.rating···
~~PPIV
oltege Tem~rature Packaget
(3.0 MHz HlIIh
Speed D,splav)
99
MC6845
MC68A46
139
MC68B45
CRT Controller
5.0
-20-+75
DP-4Q
5.0
-20-+75
DP-40
2
139
(3_7 MHz HIgh
Speed Dlsplav!
CRT Controller
HD6445-4'
CMOS
4
(4.5 MHz High
Speed Dlsplav)
99
80 type bus timing
HD6350
1
'CMOS
HD63A50
ACIA
HD63B50
1.5
HD6850
HD46850
HD68A50
HD468A50
DIPP
DICEP
•
Asynchronous
Communications
I nterface Adapter
-20-+75
DP·24
Asynchronous
Communications
Interface Adapter
MC6850
5.0
HD6852
HD46852
Synchronous Senal
Data Adapter
MC6852
HD68A52
HD468A52
1
NMOS
1
1.5
50
-20-+75
DP-24
5.0
-20-+75
DP-24
AqulSltlon Unit
5.0
0-+70
DP-24
FP-24
Reel Tune Clock
plu.RAM
DP-B4S
Documem Image
Pre-Processor
181
181
MC68A50
MC68A52
193
1
HD46508-1
NMOS
HD46508A
HD46608A-l
RTC
DP-24
1.5
HD46608
ADU
-20-+75
2
NMOS
SSDA
5.0
1.5
1
Analog Dati
207
1.5
HDI46818
CMOS
CMOS
HD63084'
HD63085'
CMOS
g-PRAM
HD63310"
CMOS
LCTC
HD63646"
CMOS
ACI
HD64941··
NMOS
Preliminary·· Under development
1
10lmaxl
5.0
32lmax)
5.0
2
50
0-+70
0-+70
PC-72
5.0
0-+70
DP-48
5.0
-20-+75
FP-80
0-+70
DP-24N
••• Wide temperature range (-40_+85°C)
MCI46818
227
Document Image ComprelSlon and Expansion Proceuor
Smart Dual Port
259
305
RAM
603
LCD Timing Controller
Asynchronous CommunlCltionslnterfece
644
SCN2B41
641
version II available.
top: PlastiC DIP, FP: Flat Plastic Package, DC: Ceramic DIP PGA: Pin Gnd Array. PC: Ceramic Pin Grid Arrav.
CP: PlastiC Leaded Chip Carrier
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
vii
QUICK REFERENCE G U I D E - - - - - - - - - - - - - - - - - - - - - - - • 16-BIT MICROCOMPUTER PERIPHERAL
LSI Characteristics
Division
Type No.
HD68230P8*
PItT
HD68230Pl0*
8
NMOS
10
HD63450-6*
6
HD63450-8*
8
HD63450-10'
HD63450-12*
DMAC
Process
Clock
Frequency
(MHz)
CMOS
10
4
HD66450-6
6
8
NMOS
HD68450-10
HD63463-6
6
8
HD63484-4
HD63484-6
GVAC
HD63485**
HD6348S'*
DUSCC
* Preliminary
HD68562*'
0-+70
DP-48
0-+70
DC-64
DP.e4
DP.e4S
PGA-68
CP-68
5.0
0-+70
DP-64
PGA-68
5.0
0-+70
5.0
Function
Compatibility
Parallel Interface
MC68230L8
Timer
MC68230L10
Direct Memory
273
307
Access Controller
Direct Memory
MC68450L4
MC68450L6
Access Controller
MC68450L8
356
6
5.0
0-+70
8
Hi-Bi
CMOS
NMOS
5.0
4 (max)
Hard Disk
404
Controller
DC-64
DP-64
Advanced CRT
Controller
472
DP-64S
Graphic Memory
CP-68
Interface Controller
531
DP.e4S
Graphic
CP-68
Attribute Controller
CP-68
5.0
Hi-Bi
CMOS
DP-48
CP-52
5.0
0-+70
0-+70
0-+70
DC-48
vidao
567
Dual Universal
MC68562
Serial Communications Controller
SCN68562
*. Under development
~HITACHI
viii
Reference
Page
DC-48
4
CMOS
HD63484-8
GMIC
5.0
(DC)
4
CMOS
HD63463-8
ACRTC
Package
Operating
10
HD63463-4
HOC
Temperature
12.5
HD66450-4
HD66450-8
Supply
Voltage
(V)
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
600
- - - - - - - - - - - - - - - - - - - - - - - - - Q U I C K REFERENCE GUIDE
• 8/16 BIT MICROCOMPUTER PERIPHERAL
LSI Characteristics
Type No.
Division
Clock
Process Frequency
(MHz)
HD6845
NMOS
HD68B45
NMOS
HD68B45S
-20-+75'
DP40
1.5
5.0
-20-+75
DP40
5.0
-20-+75
DP40
5.0
-20-+75
DP-40
1
eE
HD63B45*
>
ro
HD6445-4*
CMOS
CMOS
LCTC
HD63645**
CMOS
4
HD63484-6
GMIC
GVAC
HD63485**
HD63486**
HD6850
CMOS
ACIA
"
HD63A50
'N
HD63B50
"
HD6852
~
E SSDA
E
-20-+75
FP-80
6
5.0
0-+70
Hi-BI
5.0
Hi-8i
5.0
CMOS
DP-64
1
5.0
1.5
0-+70
0-+70
-20-+75
DP-64S
CP-68
DP-64S
CRT Controller
(3.7 MHz HIgh
Speed Display)
139
139
(4.5 MHz High
Speed Display)
6800 type bus timing
99
(4.5 MHz High
Speed Display)
99
NMOS
DUSCC
HD68562**
NMOS
ACI
HD64941**
NMOS
NMOS
HD68B40
HD6340*
DP-24
Asy nch ronous
Communications
I nterface Adapter
1.5
5.0
-20-+75
DP-24
1
1.5
5.0
-20-+75
DP-24
HD63A40*
i;
HD63B40*
PitT
HD146818
HD68230P8*
HD68230P10*
CMOS
CMOS
NMOS
0-+70
DC-48
5.0
0-+70
DP-24N
Asynchronous
Communications
I "terface Adapter
Synchronous Senal
1.5
181
MC6852
Data Adapter
MC68A52
Dual Universal Serial
Communications Control
SCN68562
Asynchronous CommUnications Control
181
MC68A50
193
600
MC68562
SCN2641
641
MC6840
5.0
-20-+75
DP-28
Programmable Timer
Module
MC68A40
49
MC68B40
HD63463-6
1.5
5.0
-20-+75
DP-28
1
8
5.0
0-+70
DP-24
FP-24
10
5.0
0-+70
4
CMOS
HD63463-8
* Preliminary
5.0
567
MC6850
Programmable Timer
Module
49
2
HD63463-4
~~
.c HOC
4 (max)
531
1
0
RTC
Graphic Memory
Interface Controller
2
u
E
472
CRT Controller
1
HD68A40
PTM
603
r.P-flR
2
HD68A52
LCD Timing Controller
Advanced
Graphic Video
Attribute Controller
1
CMOS
HD6840
U
MC68A45
MC68B45
CP-68
0
"-0
MC6845
DC-64
CMOS
HD6350
0
5.0
8
NMOS
HD68A50
2
4
HD63484-8
0
Page
80 type bus timing
ACRTC
,::
Reference
CAT Controller
1.5
2
HD63484-4
eE
(3.0 MHz High
Speed Display)
Compatibility
CRT Controller
8
U
Function
CRT Controller
1.5
2
HD6345'
HD63A45*
.:
5.0
t
Package
1
HD68A45S
~l!!
('C)
2
HD6845S
].
15
Operati~g*
Temperature
(V)
1
HD68A45
CRTC
Supply
Voltage
** Under development
6
8
DP-48
Real Time Clock
Plus RAM
Parallel Interface
Timer
MC146818
644
MC68230L8
MC6R230L10
273
DC-48
5.0
0-+70
DP48
Hard Disk Controller
404
CP-52
*** Wide temperature range (-40'"" +8SoC) version
IS
available)
tOP: Plastic DIP, DC: CeramiC DIP, FP: Flat Plastic Package, PGA: Pm Grid Array,
PC: Ceramic Pin Grid Array, CP: Plastic Leaded Chip Carrier
~HITACHI
Hitachi America Ltd
• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
ix
QUICK REFERENCE GUIDE - - - - - - - - - - - - - - - - - - - - - - - •
8/16 BIT MICROCOMPUTER PERIPHERAL
LSI Characteristics
Tvpe No.
Division
Process
Clock
Frequency
(MHz)
NMOS
1.5
HD6844
~
HD68B44
DMAC
E
i
HD68450-4
4
HD68450-6
6
NMOS
HD68450-10
6
HD63460.s"
a
CMOS
HD63450-12"
HD63310""
PIA
~
~
.
l
E
CMOS
DIPP
~
1.5
1.5
Function
Compatibility
a·Bit Direct
MC6844
MemorvAcc...
MC68A44
Controller
MC68B44
16-bit Diract
Memory Access
Controller
MC68450L6
Referance
Page
66
0-+70
DC-64
DP-64
DP-64S
PGA-68
CP-68
5.0
0_+70
DP-48
5.0
-20-+75
DP-40
356
MC6B450L8
MC68450L10
16-Bit Direct
Memory Access
Controller
307
Smart Dual Port
305
RAM
MC6821
5.0
-20-+75
5.0
-20-+75
DP-40
FP-54
Peripheral I nterfeea
Adapter
MC68A21
27
MC68B21
Peripheral Interface
Adapter
27
1
HD46508-1
HD68230PS"
HD68230Pl0"
HD63084"
0-
PGA-6B
5.0
2
NMOS
HD46508A-l
.... 8
E if!!
g£e
DICEP
C
0-+70
1
HD6321"
HD46608A
Plrr
5.0
DC-64
2
HD68B21
HD46608
ADU
0.
DP-40
1
HD63B21"
~
10
CMOS
NMOS
HD63A21"
.J::
t
Package
MC68450L4
12.5
HD6821
HD68A21
.
-20-+75
a
10
HD63450-6"
HD63450-10"
SDPRAM
5.0
Temperature
(OC)
2
HD6B460-8
CIl
Operating···
1
HD68A44
8
Supply
Voltage
(V)
1.5
1
DP-40
Analog pata
207
AcquiSition UOit
1.5
NMOS
8
10
5.0
0-+70
DP-48
CMOS
10 (max)
5.0
0-+70
DP-64S
Parallel Interface
MC68230L8
Timer
MC68230L10
Document Image
Pre-Processor
273
227
Document Image
HD63086"
CMOS
32 (max)
6.0
0-+70
PC-72
Compression and
259
Expansion Processor
... Preliminary
** Under development
••• Wide temperature range (-40 ,.,. +85°C) version is available.
t DP: Plastic DIP, DC: Ceramic DIP, FP: Flat Plastic Package PGA: Pin Grid Array, PC: Ceramic Pin Grid Array, CP: Plast'c leaded chip carrier
•
x
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
INTRODUCTION OF PACKAGES
Hitachi microcomputer devices include various types of
package which meet a lot of requirements such as ever smaller,
thinner and more versatile electric appliances. When selecting a
package suitable for the customers' use, please refer to the
following for Hitachi microcomputer packages.
multi-function types, applicable to each kind of mounting
method. Also, plastic and ceramic materials are offered according to use.
Figure 1 shows the package classification according to the
mounting types on the Printed Circuit Board (PCB) and the
materials.
1. Package Classification
There are pin insertion types, sUFface mounting types and
Standard Oud ine
Plastic DIP
Pin Insertion Type
Ceramic DIP
Shrink Outtine
Shrink Type
Ple.ti~
DIP
Shrink Type Ceramic DIP
Package Classification
Flat Package
FPP (Plastic)
Surface Mounting Type
Multi-function Type
SOP (Plastic)
Ch ip Carrier
PLCC (Plastic)
EPROM on the Package
(Gla .. Sealed Ceramic)
Type
DIP; DUAL IN LINE PACKAGE
S-DIP;SHRINK DUAL IN LINE PACKAGE
PGA: PIN GRID ARRAY
FLAT-DIP; FLAT DUAL IN LINE PACKAGE
FLAT-QUIP; FLAT QUAD IN LINE PACKAGE
CC: CHIP CARRIER
SOP;SMALL OUTLINE PACKAGE
FPP; FLAT PLASTIC PACKAGE
PLCC; PLASTIC LEADED CHIP CARRIER
LCC; LEADLESS CHIP CARRIER
Figure 1 Package Classification according to the Mounting Type on the Printed Circuit Board and the Materials.
•
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
INTRODUCTION OF PACKAGES---------------------------------------------2. Type No. and Package Code Indication
Type No. of Hitachi 8/16 bit microcomputer peripheral
device is followed by package material and outline specifica·
tions, as shown below. The package type used for each device
is identified by code as follows, illustrated in the data sheet of
each device.
When ordering, please write the package code beside the type
number.
Type No. Indication
HDxxXXP
(Note) The HD63450 with shrink type plastic DIP (DP-64S) has a dif·
ferent type No. from other deVices.
Type No.;
Packaae Classification
No Indication Ceramic DIP
P
Plastic DIP
F (FP)
SOp. FPP
CP
PLC~
V
PGA (16·bit microcomputer device)
H D63450PS8
Package Code Indication
DP-64S
Materials
Qsu!inJ.
D
C
F
P
;
;
;
;
P ; Plastic
G ; Glass Sealed
ceramic
C ; Ceramic
DIP
CC
FLAT
PGA
(Note) PGA packages of
16~bit
Package Code Indication;
microcomputer devices have a different indication.
PGA-68
•
2
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------INTRODUCTION OF PACKAGES
ages shown in Table I according to the mounting method on
the PCB.
3. Package Dimensional Outline
Hitachi multi.chip microcomputer device employs the pack.
Table 1 Package List
Method of Mounting
Package Classification
Package Material
Plastic
Standard Outline (DIPI
Flat Package
DP·24N
DP·28
DP-40
Ceramic
DC-48
DC-64
SoDIP
Plastic
DP-64S
PGA
Glass Sealed Ceramic
FLAT-QUIP (FPPI
PGA-BII PC-72
FP-24
FLAT-DIP (SOPI
Surfece Mounting Type
DP·24
DP·64
Pin Insertion Type
Shrink Outline
Package Code
Plastic
FP-54
FP-80
Plastic DIP
Scale: 1/1
• DP-24
31 6( 1244)
32 5ma•.( I 280ma•.)
/24
13 1
[:::::::::~H
I
II
12
12
--I~7)
1524
r--;;;;:;;;;:;:;::;::;::;:;::;::;::;:;::~~-l ~ j~0600)!
tTrrt
anO,...N
,r"""nr"\n.n/'I"IT"l,,..,,r\l
0
S.
~~
~~
~~\\
~2
254±025
-l1048±0I:l8
(OIOO±OOIO)
(0019±0004) N;; 0'-15'
'II\'!
\OOIO!l.
(Unit: mml
.DP-24N
Scale: 1/1
316(1244)
325m....(1 280m...)
/ ~4
131
[:::::::::::11
J"" ,
.
~.~, ".4,. .."
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"- ~~I~~
5
1ft
:;
(0400)
O,...N
c:i S. 11')8
~i!l,\\
.
254±025
048±01
~S
~25 !l,'II\'!
(Unit: mml
•
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
3
INTRODUCTION OF P A C K A G E S - - - - - - - - - - - - - - - - - - - - - -
Scale: 1/1
• DP-28
35.6(1.402)
36.6mlx.l!.44Imax.1
128
151
(Unit: mml
Scale: 1/1
• DP-40
52.8(2.079)
54.0max.(2.I26mlx.)
40
21
20
Unit (mml
• DP-48
6212(2446)
63.50mlx.(2.579mlx.)
48
~
25
~~"~""""n
I;;
0
'j'
w
w
--=..ri-h3(0.051l
w
w
w
24
(Unit: mml
•
4
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------INTRODUCTION OF PACKAGES
•
Scale: 1/1
DP-64
;:::
ii:l
.8
0
0
N
.
~
.8
(Unit: mm)
•
HITACHI
Hitachi America Ltd .•. 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
5
INTRODUCTION OF PACKAGES----------------------------------------------
ICer.mic DIP I
Scale: 1/1
eDC-48
60 42(2 379)
2S
48
I\!!
:!d
F=:>
0
I
--=..rl127(0.050)
24
0.48±0.1
2.SHO.25
(0.019±0.004) (O.IOO±O.OIO)
(Unit; mm)
Scale: 1/1
eDC·84
8128
(3.200)
33
64
ill
!:i
0
~
32
H
0.25~
(0.010!i:1i8I)
$
6
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
(Unit; mm)
----------------------------------------------INTRODUCTION OF PACKAGES
Shrink Type Plaltic 01 P
Scale: 1/1
• DP·64S
57.6(2.268)
58.6mIK.(2.307mIK.)
64
33
o
32
(Unit: mm)
Pin Grid Array
• PGA·68
22.86±045
(0900±0.0187)
Scale: 1/1
S.OBmlx. 2.54min
(0.200m.,) (O.IOOmin.)
2642
(1040)
~
~
@
D
(Unit: mm)
• PC·72
(0.200m",.,"!)-Ft,-"-
(1.079 )
~
~
t'CJ
Scale: 1/1
S.08max.
274
1.27typ.
(0.050typ.)
D
(Unit: mm)
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
7
INTRODUCTION OF PACKAGES-----------------------------------------------Plastic Leaded Chip Carrier
•
Scale: 1/1
CP-52
-
~'''''I~i~~
~!
!
H' D ' ~!
"
l~;
~
21
33
1912
(Unit: mm)
Scale: 1/1
• CP-68
25 15
~
0 12
(0990+0005)
o
.§
~~
:r&\WWiiiiiJwa~!
~~~I
(Unit: mm)
8
o
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------INTRODUCTION OF PACKAGES
Flat Package
Scale: 1/1
eFP-24
15 10(0 6U)
(Unit: mm)
eFP-54
Scale: 3/2
256±04
(1.008±0.016)
29max
(0 114ma,)
~
:e
§
:!
"';;.,
0
~
s'
0.15±0.05
(0.006 ± 0.002)
(Unit: mm)
Scale: 3/2
e FP-80
(0.014±0.004)
..J\u.uUUUIlllUUqUUqIUlIUlIllUU~0.-15.
\.~0.0\2)
(Unit: mm)
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
9
INTRODUCTION OF PACKAGES-----------------------------------------------4. Mounting Method on Board
Lead pms of the package have surface treatment, such as
solder coating or solder plating, to make them easy to mount
on the PCB. The lead pins are connected to the package by
eutectic solder. The following explains the common connecting
method ofleads and precautions.
4.1 Mounting Method of Pin Insertion Type Package
Insert lead. pins of the package into through.holes (usually
about q,0.8mm) on the PCB. Soak the lead part of the package
in a wave solder tub.
Lead pins of the package are held by the through-holes.
Therefore, it is easy to handle the package through the process
up to soldering, and easy to automate the soldering process.
When soldering the lead part of the package In the wave solder
tub , be careful not to get the solder on the package, because
the wave solder will damage it.
4.2 Mounting Method of Surface Mounting Type Package
Apply the specified quantity of solder paste to the pattern
on any printed board by the screen printing method, and put a
package on it. The package is now ~emporarily fixed to the
pnnted board by the surface tension of the paste. The solder
paste melts when heated in a reflowing furnace, and the leads
of the package and the pattern of the printed board are fixed
together by the surface tension of the melted' solder and the
self ahgnment.
The size of the pattern where the leads are attached, partly
depending on paste material or furnace adjustment, should be
l.l to 1.3 times the leads' width.
The temperature of the reflowing furnace depends on package material and also package types. Fig. 2 lists the adjustment
of the reflowing furnace for FPP. Pre-heat the furnace to 150°C.
The surface temperature of the resin should be kept at 23SoC
max. for 10 minutes or less.
Ensure good heater or temperature controls because the
material of a plastic package is black epoxy-resin which damages
easily. When an infrared heater is used, if the temperature is
higher than the glass transition point of epoxy-resin (about
IS0°C), for a long time, the package may be damaged and the
reliability lowered. Equalize the temperature inside and outside
the packages by l~ssening the heat of the upper surface of the
packages.
Leads of FPP may be easily bent under shipment or during
handling and cannot be soldered onto the printed board. If
they are, heat the bent leads again with a soldering iron to reshape them.
Use a rosin flux when soldering. Don't use a chloric flux
because the chlorine in the flux tends to remain on the leads
and lower the reliability of the product.
Even if you use a rosin flux, remaining flux can cause the
leads to deteriorate. Wash away flux from packages with
alcohol, chlorothene or freon. But don't leave these solvents
on the packages for a long time because the marking may
disappear.
5. Marking
Hitachi trademark, product type No., etc. are printed on
packages. Case I and Case II give examples of marks and Nos.
Case I applies to products which have only a standard type No.
Case II applies to products which have an old type No. and a
standard type No.
(1) The temperature of the leads should be kept at 260°C
for 10m inutes or less.
(2) The temperature of the resin should be kept at 235°C
for 10m inutes or less.
(3) Below is shown the temperature profile when soldering a
package by the reflowing method.
Tlme------+
Figure 2 Reflowing Furnace Adjustment for FPP
•
10
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------INTRODUCTION OF PACKAGES
Case I; I neludes a standard type No.
(d)
D~B~rsJ
Case II; Includes an old type No. and a standard type No.
(a)
(b)
'. mDB
(e)
B 0 ~ BBOB SB
(d)D~B~rsJ
(c)
BDB8~BSB
Meaning of Each Mark
(01
(bl
Hitachi Trademark
Lot Code
(el
(dl
Standard Type No.
(el
Old Type No.
Japan Mark
@HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
11
RELIABILITY AND QUALITY ASSURANCE
1. VIEWS ON QUALITY AND REI-lABILITY
Basic views on qUality in Hitachi are to meet individual
user's purchase purpose and quality required, and to be at the
satisfied quality level considering general marketability. Quality
required by users is specifically clear if the contract specifica·
tion is provided. If not, quality required is not always defmite.
In both cases, efforts are made to assure the reliability so that
semiconductor devices delivered can perform their ability in
actual operating circumstances. To realize such quality in
manufacturing process, the key points should be to establish
quality control system in the process and to enhance morale
for quality.
In addition, quality required by users on semiconductor
devices is going toward higher level as performance of electronic system in the market is going toward higher one and is
expanding size and application fields. To cover the situation,
actual bases Hitachi is performing is as follows;
(1) Build the reliability in design at the stage of new product
development.
(2) Build the quality at the sources of manufacturing process.
(3) Execute the harder inspection and reliability confirmation
of fmal products.
(4) Make quality level higher with field data feed back.
(5) Cooperate with research laboratories for higher quality
and reliability.
With the views and methods mentioned above, utmost efforts
are made for users' requirements.
2. RELIABILITY DESIGN OF SEMICONDUCTOR
DEVICES
2.1 Reliability Targets
Reliability target is the important factor in manufacture
and sales as well as performance and price. It is not practical to
rate reliability target with failure rate at the certain common
test condition. The reliability target is determined correspond·
ing to character of equipments taking design, manufacture,
inner process quality control, screening and test method, etc.
into conSideration, and conSidering operating circumstances
of equipments the semiconductor device used in, reliability
target of system, derating applied in design, operating condition,
maintenance, etc.
2.2 Reliability Design
To achieve the reliability required based on reliability targets,
timely sude and execution of design standardization, device
design (including process design, structure design), design
review, reliability test are essential.
(I) Design Standardization
Establishment of design rule, and standardization of parts,
material and process are necessary. As for design rule, critical
items on quality and reliability are always studied at circuit
deSign, device design, layout design, etc. Therefore, as long as
standardized process, material, etc. are used, reliability risk is
extremely small even in new development devices, only except
for in the case special requirements in function needed.
(2) Device DeSign
It is important for device design to consider total balance
of process design, structure design, circuit and layout design.
Especially in the case new process and new material are employed, technical study is deeply executed prior to device
development.
(3) Reliability Evaluation by Test Site
Test site is sometimes called Test Pattern. It is useful method
for design and process reliability evaluation of IC and LSI which
have complicated functions.
1. Purposes of Test Site are as follows;
• Making clear about fundamental failure mode
• Analysis of relation between failure m04e and manufacturing process condition
• Search for failure mechanism analysis
• Establishment of QC point in manufacturing
2. Effectiveness of evaluation by Test Site are as follows;
• Common fundamental failure mode and failure mechanism in devices can be evaluated.
• Factors dominating failure mode can be picked up, and
comparison can be made with process having been experienced in field.
• Able to analyze relation between failure causes and manufactUring factors.
• Easy to run tests.
etc.
2.3 Design Review
Design review is organized method to confirm that design
satisfies the performance required including users' and design
work follows the specified ways, and whether or not technical
improved items accumulated in test data of individual major
fields and field data are effectively built in. In addition, from
the standpoint of enhancement of competitive power of products, the major purpose of design review is to ensure quality
and reliability of the products. In Hitachi, design review is
performed from the planning stage for new products and even
for design changed products. Items discussed and determined
at design review are as follows;
(1) Description of the products based on specified design
documents.
(2) From the standpoint of specialty of individual participants,
design documents are studied, and if unclear matter is
found, sub·program of calculation, experiments, investigation, etc. will be carried out.
(3) Determine contents of reliability and methods, etc. based
on design document and drawing.
(4) Check process ability of manufacturing line to achieve
design goal.
(5) Discussion about preparation for production.
(6) Planning and execution of sub-programs for design change
proposed by indiVidual specialist, and for tests, experiments
and calculation to confirm the design change.
(7) Reference of past failure experiences with similar devices,
confmnation of method to prevent them, and planning
and execution of test program for confmnation of them.
These studies and decisions are made using check lists
made individually depending on the objects.
3. QUALITY ASSURANCE SYSTEM OF SEMICONDUCTOR
DEVICES
3.1 Activity of Quality Assurance
General views of overall quality assurance in Hitachi are as
follows;
(l) Problems in individual process should be solved in the
~HITACHI
12
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - R E L I A B I L I T Y AND QUALITY ASSURANCE
process. Therefore, at fmal product stage, the. potential
failure factors have been already removed.
(2) Feedback of infonnation should be made to ensure satisfied
level of process ability.
(3) To assure reliability required as an result of the things
mentioned above is the purpose of quality assurance.
The followings are regarding device design, quality approval
at mass production, inner process quality control, product
inspection and reliability tests.
in manufacturing department, quality assurance department,
which are major, and other departments related. The total
function flow is shown in Figure 2. The main points are
described below.
3.3.1 Quality Control of Parts and Material
As the perfonnance and the reliability of semiconductor
devices are getting higher, importance is increasing in quality
control of material and parts, which are crystal, lead frame,
fme wire for wire bonding, package, to build products, and
materials needed in manufacturing process, which are mask
pattern and chemicals. Besides quality approval on parts and
materials stated in section 3.2, the incoming inspection is,
also, key in quality control of parts and materials. The in·
coming inspection is perfonned based on incoming inspection
specification following purchase specification and drawing,
and sampling inspection is executed based on MIL·STD·105D
mainly.
The other activities of quality assurance are as follows:
(1) Outside Vendor Technicallnfonnation Meeting
(2) Approval on outside vendors, and guidance of outside
vendors
(3) Physical chemical analysis and test
The typical check points of parts and materials are shown in
Table 1.
3.2 Quality Approval
To ensure quality and reliability required, quality approval
is carried out at trial production stage of device design and
mass production stage based on reliability design descnbed at
section 2.
The views on quality approval are as follows;
(I) The third party perfonns approval objectively from the
standpoint of customers.
(2) Fully consider past failure experiences and infonnation
from field.
(3) Approval is needed for design change and work change.
(4) Intensive approval is executed on parts material and pro·
cess.
(5) Study process ability and fluctuation factor, and set up
control points at mass production stage.
Considering the views mentioned above, quality approval
shown in Figure 1 is performed.
3.3.2 Inner Process Quality Control
Inner process quality control is performing very important
function in quality assurance of semiconductor devices. The
following is description about control of semi·fmal products,
fmal products, manufacturing facilities, measuring equipments,
3.3 Quality and Reliability Control at Mass Production
For quality assurance of products in mass production,
quality control is executed with organic division of functions
Contents
Step
/:Target
Specification
I
Purpose
Design Review
~
Materials, Parts II
Approval
II
9
l;esi
Trial n
Production
Characteristics of Material and
Parts
Appearance
Dimension
Confirmation of
Characteristics and
Reliability of Materials
and Parts
Heat Resistance
Mechanical
Electrical
Others
ILCharacteristics Approval
Electrica'
Characteristics
Function
Confirmation of Target
Spec. Mainly about
Electrical Characteristics
Voltage
Current
Temperature
Others
Appearance, Dim.ns,ion
Qual itv Approval (1
Reliability Test
Life Test
Confirmation of Quality
and Reliability in Design
Thermal Stress
Moisture Resistance
Mechanical Stre..
Others
Qualit'j< Approval (2)
~
I~ass
Production
J
Reliability Test
Process Check same as
Quality Approval (1)
Confirmation of Quality
and Reliebility in Ma..
Production
Figure 1 Flow Chart of Quality Approval
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
13
RELIABILITY AND QUALITY A S S U R A N C E - - - - - - - - - - - - - - - - - - - - circumstances and sub-materials. The quality control in the
manufacturing process is shown in Figure 3 corresponding to
the manufacturing process.
(1) Quality Control of Semi-fmal Products and Final Products
Potential failure factors of semiconductor devices should be
removed preventively in manufacturing process. To achieve it,
check points are set-up in each process, and products which
have potential failure factor are not transfer to the next process.
Especially, for high reliability semiconductor devices, manufacturing line is rigidly selected, and the quality control in the
manufacturing process is tightly executed - rigid check in
each process and each lot, 100% inspection in appropriate ways
to remove failure factor caused by manufacturing fluctuation,
and execution of screening needed, such as high temperature
aging and temperature cycling. Contents of inner process
quality control are as follows;
• Condition control on individual equipments and workers,
and sampling check of semifmal products.
• Proposal and carrying-out improvement of work
• Education of workers
• Maintenance and improvement of yield
• Picking-up of quality problems, and execution of counter-
measures
• Transmission of information about quality
(2) Quality Control of Manufacturing Facilities and Measuring
Equipment
Equipments for manufacturing semiconductor devices have
~een developing extraordinarily with necessary high performance devices and improvement of production, and are important
factors to determine quality and reliability. In Hitachi, automatization of manufacturing equipments are promoted to improve manufacturing fluctuation, and controls are made to
maintain proper operation of high performance equipments
and perform the proper function. As for maintenance inspection
for quality control, there are daily inspection which is performed daily based on specification related, and periodical inspection
which is performed periodically. At the inspection, inspection
points listed in the specification are checked one by one not to
make any omission. As for adjustment and maintenance of
measuring equipments, maintenance number, speCification are
checked one by one to maintain and improve qUality.
(3) Quality Control of Manufacturing Circumstances and Submaterials
Quality and reliability of semiconductor device is highly
Quality Control
Process
Method
Material,
Parts
Confirmation of
Devices
Qual ity Level
Manufacturing Equipment,
Environment. Sub-material.
Worker Control
Inner Process
Quality Control
100% I nspection on
Appearance and Electrical
Characteristics
Products
Sampling Inspection on
Appearance and Electrical
I
I
I
I
Lot Sampl ing,
Inspection on Material and
Parts for Semiconductor
Confirmation of
Qual ity Level
Lot Sampl ing,
Confirmation of
Quality Level
Testing.
Inspection
Lot Sampling
Characteristics
I
I
'Confirmation of
~----
Reliability Test
Quality Level, Lot
Sampling
Feedback of
r ---------------,
Quality Information
I
"
Claim
:
I
Field Experience
I
I
Information
General Quality
I nformation
L _________________
...I
Figure 2 Flow Chart of Quality Control in Manufacturing Process
~HITACHI
14
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - R E L I A B I L I T Y AND QUALITY ASSURANCE
affected by manufacturing process. Therefore, the controls of
manufacturing circumstances - temperature, humidity, dust and the control of submaterials - gas, pure water - used in
manufacturing process are intensively executed. Dust control
is described in more detail below.
Dust control is essential to realize higher integration and
higher reliability of devices. In Hitachi, maintenance and improvement of cleanness in manufacturing site are executed
with paying intensive attention on buildings, facilities, airconditioning systems, materials delivered-in, clothes, work, etc.,
and periodical inspection on floating dust in room, falling dusts
and dirtiness of floor.
Table 1 Quality Control Check Points of Material and Parts
(Examplel
Material,
Parts
Wafer
Mask
3.3.3 Final Product Inspection and Reliability Assurance
(1) Final Product Inspection
Lot inspection is done by quality assurance department for
products which were judged as good products in 100% test,
which is fmal process in manufacturing department. Though
100% of good products is expected, sampling inspection is
executed to prevent mixture of failed products by mistake of
work, etc. The inspection is executed not only to confmn that
the products meet users' requirement, but to consider potential
factors. Lot inspection is executed based on MIL-STD-105D.
(2) Reliability Assurance Tests
To assure reliability of semiconductor devices, periodical
reliability tests and reliability tests on individual manufacturing
lot required by user are performed.
Fine
Wire for
Wire
Bonding
Frame
Ceramic
Package
Plastic
Important
Control Items
Appearance
Dimension
Sheet Resistance
Defect Density
Crystal Ax is
Appearance
Dimension
Resistoration
Gradation
Appearance
Dimension
Purity
Elongation Ratio
Appearance
Dimension
Processing
Accuracy
Plating
Mounting
Characteristics
Appearance
Dimension
Leak Resistance
Plating
Mounting
Characteristics
Electrical
Characteristics
Mechanical
Strength
Composition
Electrical
Characteristics
Thermal
Characteristics
Molding
Performance
Mounting
Characteristics
Point for Check
Damage and Contamination on Surface
Flatness
Resistance
Defect Numbers
Defect Numbers, Scratch
Dimension Level
Uniformity of Gradation
Contamination, Scratch,
Bend, Twist
Purity Level
Mechanical Strength
Contamination, Scratch
Dimension Level
Bondability, Solderability
Heat Resistance
Contamination, Scratch
Dimension Level
Airtightness
Bondability, Solderability
Heat Resistance
Mechanical Strength
Characteristics of
Plastic Material
Molding Performance
Mounting Characteristics
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (40B) 435-B300
15
RELIABILITY AND QUALITY A S S U R A N C E - - - - - - - - - - - - - - - - - - - - -
Process
Control Point
Purpose of Control
Purchase of Material
Wafer
Wafer
Characteristics, Appearance
Scratch, Removal of Crystal
Appearance, Thickness of
Oxide Film
Pinhole, Scratch
Defect Wafer
Surface Oxidation
Assurance of Resistance
Oxidation
Inspection on Surface
Oxidation
Photo
Resist
Photo Resist
Inspection on Photo Resist
Dimension, Appearance
o POC Level Check
Diffusion
Diffusion
Dimension Level
Check of Photo Resist
Diffusion Depth, Sheet
Diffusion Status
Resistance
Inspection on Diffusion
o POC Level Check
Gate Width
Control of Basic Parameters
Characteristics of Oxide Film
Breakdown Voltage
(VTH, etc.) Cleanness of surface,
Prior Check of VIH
Breakdown Voltage Check
Evaporation
Thickness of Vapor Film,
Scratch, Contamination
Wafer Inspection
Wafer
Inspection on Chip
Elec;trical Characteristics
Chip
Thickness, VTH Characteristics
Electrical Characteristics
Evaporation
Assurance of Standard
Thickness
Inspection on Evaporation
o POC Level Check
Chip Scribe
Prevention of Crack,
Quality Assurance of Scribe
Appearance of Chip
Inspection on Chip
Appearance
o POC Lot Judgement
Frame
Assembling
Assembling
Appearance after Chip
Bonding
Appearance after Wire
Bonding
Pull Strength, Compression
o POC Level Check
Width, Shear Strength
Ouality Check of Chip
Bonding
Ouality Check of Wire
Bonding
Prevention of Open and
Short
Appearance after Assembling
Inspection after
Assembling
o POC Lot Judgement
Package
Sealing
o POC Level Check
Final Electrical Inspection
o Failure Analysis
Sealing
Appearance after Sealing
Outline, Dimension
Marking
Marking Strength
Analysis of Failures, Failure
Mode, Mechanism
Guarantee of Appearance
and Dimension
Feedback of Analysis Information
Appearance Inspection
Sampling Inspection on
Products
Receiving
Shipment
Figure 3 Example of Inner Process Quality Control
@HITACHI
16
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - R E L I A B I L I T Y AND QUALITY ASSURANCE
r------------ - - - - - - - - - - - - - - - - - - - - - 1
I
I
I
I
I
r-----~----~
I
Countermeasure
Execution of
Countermeasure
I
I
I
I
I
Failure Analysis
I
I
I
I
I
I
I
I
Report
I
I
II
I
I
I
I
I
Quality Assurance Dept.
I
Follow-up and Confirmation
of Countermeasure Execution
I
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _Report
_________________
II
I
I
I
~
Sales Engineering Dept.
Reply
Customer
Figure 4 Process Flow Chart of Field Failure
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
17
RELIABILITY TEST DATA OF MICROCOMPUTER
1. INTRODUCTION
2. PACKAGE AND CHIP STRUCTURE
Microcomputer is required to pr"vlde higher reliability and
qUality with increasing function, enlarging scale and widening
application. To meet this demand, Hitachi is improving the
quality by evaluating reliability, building up quality in process,
strengthening inspection and analyzing field data etc ..
This chapter describes reliability and quality assurance data
for Hitachi 8-bit and 16-bit microcomputer Peripheral based on
test and failure analysis results. More detail data and new infor.
mation wiD be reported in another reliability data sheet.
2.1 Package
The reliability of plastic molded type has been greatly im·
proved, recently their applications have been expanded to automobiles measuring and control systems, and computer terminal
equipment operated under relatively severe conditions and
production output and application of plastic molded type will
continue to increase.
To meet such requirements, Hitachi has considerably improved moisture resistance, operation stability, and chip and
plastic manufacturing process.
Plastic and ceramic package type structure are shown in
Figure I and Table I.
(1) Ceramic DIP
<>
(2) Plastic DIP
Lid
(3) Plastic Flat Package
Bonding wire
Chip
Figure 1 Package Structure
Table 1 Package Material and Properties
Item
Plastic DIP
Ceramic DIP
Plastic Flat Package
Package
Alumina
Epoxy
Epoxy
Solder dipping Alloy 42 or Cl
Solder plating Alloy 42
Lead
Tin plating Brazed Alloy 42
Seal
Au-Sn Alloy
N.A
N.A
Die bond
Au-Si
Au-Si or Ag paste
Au-Si or Ag paste
Wire bond
Ultrasonic
Thermo compression
Thermo compression
Wire
AI
Au
Au
~HITACHI
18
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - R E L I A B I L I T Y TEST DATA OF MICROCOMPUTER
2.2 Chip Structure
Hitachi microcomputers are produced in NMOS E/D technology or low power CMOS technology. Si-gate process is used
in both types because of high reliability and high density.
Chip structure and basic circuit are shown in Figure 2_
Si-Gate N-channel E/D
Drain
Source
FETI
Drain
Si-Gate CMOS
SiO l
Source
Source
DrBln
FET2
FET2
N
PA,
PA,
PA,
PA,
PB.
PB,
PB,
PB,
PB,
PB,
D,
D,
D,
..... _ ... U
CCa)CDCCU
...... 0 0 >
<:U)(I)(I)
(Top View)
(Top View)
•
,0.a:ooow
01" -
BLOCK DIAGRAM
eA,
'00..
eA,
0.
0,
0,
0,
D.
D.
p..
PA,
PA,
PA,
P..
0,
0,
..'"
,
'A,
.o.
v"
v..
PB,
'B,
PB,
CSO
cs,
fJ;
oSo
os,
oiW
.a.
Po.
P"
PB,
•
110
,-
CB,
CB,
.HITACHI
28
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------HD6321/HD6821
• ABSOLUTE MAXIMUM RATINGS
Item
Value
Symbol
Unit
Supply Voltage
Vee •
--{l.3 - +7.0
HD6821
-{l.3- +7.0
Input Voltage
Vin·
-{l.3 - +7.0
-{l.3 - +7.0
V
-
mA
Maximum Output Current
Maximum Total Output Current
Operating Temperature
Storage Temperature
HD6321
110 1**
11:1 0 1**.
10
Topr
100
-20- +75
Tstg
-55- +150
V
mA
·C
-20 - +75
-55-+150
·C
• With respect to VSS (SYSTEM GNDI
** Maximum output current is the maximum current which can flow in or flow out from one output terminal and I/O common
terminal. (PAo-PA7. CA2. PBo-PB7. CB2. 00-071
** .. Maximum total output current i. the total sum of output current which can flow in or flow out simultaneously from output
tarminals and I/O common terminals. (PAo-PA7. CA2. PBo-PB7. CB2. 00-071
(NOTEI Permanent LSI damage may occur if maximum ratings are exceeded. Normel operation should be under recommended
operating conditions. If these conditions are exceeded, it could affect reliability of LSI.
•
RECOMMENDED OPERATING CONDITIONS
.
Item
Symbol
Supply Voltage
Input "Low" Voltage
Input "High"
voltage
Do-D 7 .PAoPA 7 • CAl. CA2
PB o -PB 7
CBI. CB2
S,!ltW.CSo•
CS2• CSI • RSo.
RS I • RES
Operating Temperature
Vee
VIL·
min.
4.5
-0.3
HD6321
tVD
5.0
max .
5.5
-
0.8
2.2
HD6821
tvD
5.0
max.
Unit
5.25
0.8
V
-
2.0
-
Vee
V
-20
25
75
·C
V
Vee
-
VIH·
3.0"
Topr
min.
4.75
-0.3
-20
Vee
25
75
• With respect to Vss (SYSTEM GNOI
** Characteristics will be improved.
$
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
29
HD6321/HD6821--------------------------------------------------------•
•
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (HD6321; Vee = 5V ±10%, HD6821; Vee
Item
Symbol
Do-D 7 • PAo -PA 7 •
CA, CA,. PBo-PB7,
CB" CB,
Input "High" Voltage
E, R/W, CSo, CS,
HD6321
Test Condition
All Inputs
Input leakage Current
RIW, RES, RSo, RS"
CSo, CS" CS" CA"
CB" E
Three State (Off State)
PAo-PA7, CA,
VIL
1m
ITSI
Input CUrrent
Do-D 7, PBo-PB7, CB,
Input "High" Current
PAo-PA7, CA,
IIH
Input "Low" Current
PAo-PA7. CA2
IlL
Vin =0 -Vee
Vin = 0.4- Vee
Output "High" Voltage
VOH
PBo - PB 7, CB,
oO-07,IROA,IROS
PAo-PA7, CA,
max
2.2
-
Vee
3.0**
-
Vee
-0.3
-
0.8
-2.S
-
2.S
-
10
-------
-10
-
-
IOH <-10~A
Vee -Q.l
-
IOH =-400~A
4.1
-
-
-
-
lo~
< -1O~A
V cc -o. 1
VOL
Do - 0,
PAo-PA7, CA,
10H
PBo-PB7, CB,
Output Leakage Current
1011 State I
IRQA,IROS
Output Capacitance
Supply Current ****
CA" CB" Do -D 7
RIW, RES, RS o, RS,
CSo, CS" CS" CA,
CB ,E
iRQA", IROB
-
-
0.4
IOL = 3.2mA
-
-
0.6
~
-
-
10
VIn = OV
-
-
12.S
Cm
Ta = 25°C
I =1.0MHz
-
-
10
Vin :::OV
T.=2SoC
I =1.0MHz
-
-
10
E = 1.0MHz
-
-
300
E = 1.SMHz
-
-
400
E = 2.0MHz
-
-
SOO
E = 1.0MHz
-
-
4
E =l.SMHz
-
-
6
-PAo -PA7, CA2, PBoPB 7 , CB2 are specified
as Input.
_Chip is not selected.
-Input level
V,Hmm=V cc -08V
Icc
-PAo""PA7, CA2 and
PB o ""PB 7 , CB2 are
specified as Input.
_Under Data Bus A/W
operation.
Power Dissipation
E = 2.0MHz
PD
S
tvp*
max
2.0
-
Vee
V
-0.3
-
0.8
V
2.S
~A
---
-'l.S
-
-10
10
-
-
~A
VIL = 0.4V
-
-
-'l.4
mA
-
-
10~A
2.4
~
2.4***
Vee -Q.l
2.4
-
-
-
0.'1
10L = 1.6mA
-
IOL = 3.2mA
-
-
0.6
-
IOL=I.6mA
0.4
VOH = 2.4V
~20S
VOH = 2.411""
-'l00
VOH =1.SV
-1.0
VOH = Vee
-
-
Yin = OV
Ta = 2SoC
-
-
12.5
1= 1.0MHz
-
-
10
-
-
10
Ta = 2SoC
1= 1.0MHz
V
-
-10
10
V
~A
~A
mA
~A
pF
~
~
260
S50
Ta = 2S'C, V ce = 5.0V
Characteristics will be improved.
HD68B21; VOH = 2.2V min IPA o -PA 7, CA,I
Supply current is defined on the condition that there is no current flow from output terminals. Supply current will be increased when the
current from output terminal eXists. Also the current will be increased for charging and discharging the capacitive load. Please take this
case into consideration in estimating system power.
~HITACHI
30
~A
-'l00
Vm=OV
v,L max = O.8V
Unit
min
VIH = 2.4V
IOH =-
VOH = Vee
Cout
Yin = 0.4-2.4V
IOH = -'lOO~A
ILOH
PAo -PA 7 , PBo-PB7
Input Capacitance
Vin = 0 -Vee
IOH = -200~A
IOL=I.6mA
PBo -PB 7, CB,
Output "High" Current
Test Condition
IOH=-20S/lA
~
PAo-PA,. CA2
Output" Low" Voltage
typ*
4.1
IOH - -400,uA
00- 0 7
PA o-PA 7 , CA 2
PBo -PB 7, eB,
HD6821
min.
V IH
CS" RSo, RS" RES
Input" Low" Voltage
=5V ±5%, Vss = OV, Ta =-20 -+75°C, unless otherwise noted.)
Hitachi America ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
pF
~A
mA
mW
HD6321/HD6821
• AC CHARACTERISTICS (HD6321; Vee = 5V ± 10%, HD6821; Vee= 5V ± 5%, Vss = OV, Ta = -20 - +75°C unless otherwise noted)
1.
PERIPHERAL TIMING
HD68B21
min
200
135
100
ns
0
0
0
ns
HD63A21
min
min
min
Fig. 1
100
100
100
Fig. 1
0
0
0
Test Condition
Pertpheral Data Setup Time
tPDSU
Peripheral Data Hold Time
tpDH
HD6321
max
HD63B21
HD66A21
min
isV mbol
Item
HD6821
Umt
Delay Time, Enable negative
Transition to CAl negative
transition
Enable -+ CA2 Negative
'CA2
Fig. 2, Fig. 3
200
200
200
1000
670
500
Delay Time, Enable negative
transition to CA2 positive
transition
Enable-+CA2 Positive
'flSl
FIg. 2
200
200
200
1000
670
500
Rise and Fall Times for CAl
and CA2 input Signals
CAl, CA2
tptf
Fig. 3
100
100
100
1000
1000
1000
CAl -+CA2
'RS2
Fig. 3
300
300
300
2000
1350
1000
ns
Fig. 4, Fig. 5
300
300
300
1000
670
500
ns
2000
1350
1000
ns
1000
670
500
ns
Delay Time from CAl
active transition to CA2
pOSitive tranSItion
Delay Time, Enable negative
transition to Peripheral Data
Valid
Delay TIme, Enable negative
transition to Peripheral
CMOS Data Valid
Enable-+Peripheral Data 'POW
Enable -+ Peripheral
Data
PAo-PA 7, CAz
Delay Time, Enable pOSitive
transition to CBl negative
position
Enable -+- CB l
Delay Time, Peripheral Data
Valid to CB z negative
tranSition
Peripheral Data -+- CB z
Delay Time, Enable positive
transition to CBz pOSitive
transition
'CMOS
Vcc-30% Vee
Flg.4
tCB2
Fig. 6, Fig. 7
'DC
Fig. 5
Enable-+- CB z
'RSl
Fig. 6
CA, CB,
PWCT
Fig. 2, Fig. 6
----------20
200
200
200
200
20
20
20
200
670
1000
200
Peripheral Control Output
Pulse Width, CA,/CB2
375
550
250
CBt, CBz
tr,'tf
Flg.7
100
100
100
Delay Time, CSt active
transition to CB2 positive
transition
CBI -+-CS2
'RS2
Fig. 7
300
300
'IR
Flg.9
800
400
Interrupt Release Time,
IRCA and IRQS
IRCA,IRQS
Interrupt Response Time
IROA, IROB
tRS3
Fig.8
Interrupt Input Pulse Width
CAt, CA2, CSt, CB 2
PWI
Fig. 8
Reset "Low" Time
RES·
'RL
Fig. 10
"
U
500
500
550
550
Rise and Fall Time for CB 1
and CS z input Signals
ns
20
20
ns
ns
ns
1000
1000
1000
ns
300
2000
1350
1000
ns
800
BOO
1600
1100
850
ns
400
400
1000
1000
1000
ns
lE
lE
lE
cycle
cycle
cycle
200
200
200
500""
1000
-
500"
500"
ns
660
500
ns
The Reset line must be "High" a minimum of 1.0~s before addressmg the PIA.
At least one Enable "High" pulse should be mcluded in this period.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
31
HD6321/HD6821------------------------------------------------------2.
BUS TIMING
1)
READ
Ho6321
Item
Symbol
Test Condition
Ho63A21
max
min
max
min
668
-
220
Enable Cycle Time
~eE
Fig. 11
'1000
Enable Pulse Width. "High"
PWEH
Fig. 11
450
Enable Pulse Width. "Low"
PWEL
Fig. 11
430
Enable Pulse Rise and Fall Times
tEr. tEt
Fig. 11
-
25
-
25
tAS
Fig. 12
80
-
60
tAH
Fig. 12
10
-
10
-
Data Dalav Time
tooR
Fig. 12
-
280
Data Hold Time
toHR
Fig. 12
20
100
Setup Time
IAddr.... R/W-Enabl.
Address Hold Tim.
Ho63B21
Ho6821
Ho68A21
HD68B21
Unit
min
-
280
280
500
210
-
max
min
max
min
-
1000
-
668
450
430
-
280
-
25
-
20
140
10
-
-
180
-
150
-
20
100
20
100
10
50"
10
280
max
min
-
500
-
max
-
ns
220
-
ns
210
-
ns
26
-
25
ns
-
140
-
70
-
ns
10
-
10
-
ns
320
-
220
-
180
ns
-
10
-
ns
-
10
* Characteristics will be Improved.
2)
WRITE
HD6321
Symbol
Item
Ho63A21
Test Condition
min
max
min
min
-
500
Enable Cycle Time
leye E
Fig. 11
1000
-
668
Enable Pulse Width. "High"
PWEH
Fig. 11
450
-
280
En.ble Pulse Width. "Low"
PWEL
Fig. 11
430
-
280
-
Enable Pulse Rise and Fall Times
tEr. tEt
Fig. 11
-
26
-
25
tAS
Fig. 13
80
I Address. R/W·Enable tAH
Fig. 13
10
-
60
10
-
Setup Tim.
Address Hold Time
HD63B21
max
-
20
60'
10
Data Setup Tim.
tosw
Fig. 13
165
-
80
-
60
Data Hold Tim.
toHW
Fig. 13
10
-
10
-
10
-
Unit
•
min
max
-
500
220
-
210
-
ns
1000
-
666
450
-
280
430
-
280
-
n.
ns
-
25
-
25
-
25
ns
140
-
140
-
ns
10
-
10
-
70
10
-
ns
196
-
80
60
-
ns
10
-
10
10
-
n.
• Characteristics will be improved.
32
Ho68B21
max
min
-
210
H068A21
max
min
-
220
H06821
max
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose. CA 95131 • (408) 435-8300
-
---------------------------------------------------------HD6321/HD6821
Enable
PA.-PA,
PB.-PB,
Enable
• Assumes part was deselected dUring
the prevIous E pulse.
Figure 1 Peripheral Data Setup and Hold Times (Read Mode)
Figure 2 CAl Delay Time
(Read Mode; CRA5=CRA3=1, CRA4=0)
Enable
Enable
CA,
PA.-PA,--~~~--~~~--~~~-------
_tCA~2
CA,
CA,
------J"'F=......;~-----
tf
VOL max"
'1---""""':"1
Figure 3 CAl Delay Time
(Read Mode; CRA5=1, CRA3=CRA4=0)
Figure 4 Peripheral Data Delay Times
(Wr.ite Mode; CRA5=CRA3~1, CRA4=O)
Enable
Enable
PB. -PB,
toe:!
~
ca,
INotel
ca,
CB,
•••
• Assumes part was deselected dunng the
previous E pulse.
goes "Low" as a result of the
positive transition of Enable.
Figure 5 Peripheral Data and CBl Delay Times
(Write Mode; CRB5=CRB3=1, CRB4=0)
Figure 6 CBl Delay Time
(Write Mode; CRB5=CRB3=1, CRB4=0)
Enable
1 - - - - PWI---.)
CA"CA,
VIHmin
VI max
ca,
~i
ca,
CB" CB,
IH min
V 1L max
tRS2*
O.4V
~max**
• Assumes Interrupt Enable Bits are set.
* Assumes part was deselected durmg
any previous E pulse.
Figure 7 CB, Delay Time
(Write Mode; CRB5=1, CRB3=CRB4=0)
Figure 8 Interrupt Pulse Width and IRQ Response
O.6V for H06321 , O.4V for H06821
2.4V for H 06821
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
33
HD6321/HD6821---------------------------------------------------------
Enable
I---
ifv;Hmin
---f
t'R
p
1-----tRL - -RE-S
VIL max
Vee -2.oV***
* The RES line must be a V1H for a minimum of
1.0 $'s before addresSing the PIA.
IRQ _ _ _ _ _ _ _ _ _......J
Figure 9 IRQ Release Time
Figure 10 RES Low Time
Figure 11 Enable Signal CharacterIStiCS
V,Hmm
Data Bus
V1H min
----------------~I
VILmax
Figure 12 Bus Read Tlmong Characterostlcs
(Read Information from PIA)
Figure 13 Bus Write Timing Characterostlcs
(Write Information onto PIA)
O.6V for HD6321, O.4V for HD6821.
2.4V for HD6821.
LOAD A
(PA"-PA,, PB,-PB" CA" CB, I
LOAD B
(0,-0,)
5.0V
Test Point
+-
5.0V
IOL
Test Pomt
o-~--1r-(c.--f
C
C
C-4OpF
R=10kO (HD6321), 12kO (HD6821)
R
C=13OpF
R=10kO (HD6321 I. llkO (HD6821)
All diodes arelS207460r equivalent.
Adjust RL so that IOL a 1.6mA, then test VOL
Adjust RL so that IOL • 3.2mA, then test VOL
LOAD C
LOAD 0 (HD68211
(Tmi Only)
5.0V
Test POIOt
~
I
(CMOS Load) Test Point
3kO
1
°O
PF
Figure 14 Bus Timing Test Loads
34
$
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------HD6321/HD6821
• PIA INTERFACE SIGNALS FOR MPU
Input
The PIA interfaces to the H06800 MPU with an eight-bit
bi-directional data bus, three chip select lines, two register select
lines, two interrupt request lines, read/write line, enable line and
reset line. These signals, in conjunction with the HD6800
VMA output, permit the MPU to have complete control over
the PIA. VMA should be utilized in conjunction with an MPU
address line into a chip select of the PIA.
• Bi-Directional Data 10 0 -0 7 1
Input
These three input signals are used to select the PIA. CS o and
CS I must be "High" and CS, must be "Low" for selection of
the device. Data transfers are then performed under the control
of the E and R/W signals. The chip select lines must be stable
for the duration of the E pulse. The device is deselected when
any of the chip selects are in the inactive state.
• Register Select IRS o and RSII
Pin No. 33 - 26 (DP-40)
Pin No. 43 - 36 (FP-54)
Input
The bi-directional data lines (Do - D7 ) allow the transfer of
data between the MPU and the PIA. The data bus output drivers
are three-state devices that remain in the high-impedance (off)
state except when the MPU performs a PIA read operation. The
R/W line is in the Read ("High") state when the PIA is selected
for a Read operation.
•
Enable lEI
Input/Output
Pin No. 21 (DP-40)
Pin No. 28 (FP-54)
This signal is generated by the MPU to control the direction
of data transfers on the Data Bus. A "Low" state on the PIA
line enables the input buffers and data is transferred from the
MPU to the PIA on the E signal if the device has been selected.
A "High" on the R/W line sets up the PIA for a transfer of data
to the bus. The PIA output buffers are enabled when the proper
address and the enable pulse E are present.
• Reset IRES)
Input
Pin No. 34 (DP-40)
Pin No. 44 (FP-54)
The active "Low" RES line is used to reset all register bits in
the PIA to a logical zero "Low". This line can be used as a
power-on reset and as a master reset during system operation.
•
Chip Select ICSo. CSI and cs.1
The two register select lines are used to select the various
registers inside the PIA. These two lines are used in conjunction
with internal Control Registers to select a particular register that
is to be written or read.
The register and chip select lines should be stable for the
duration of the E pulse while in the read or write cycle.
Input
ReadlWrite IR/W)
Input
Pin No. 36,35 (DP-40)
Pin No. 50,45 (FP-54)
• Interrupt Request URQA and IROBI
Pin No. 25 (DP-40)
Pin No. 32 (FP-54)
The enable pulse, E, is the only timing signal that is supplied
to the PIA. Timing of all other signals is referenced to the
leading and trailing edges of the E pulse. This signal will
normally be a derivative of the HMCS6800 System q" Clock.
This signal must be continuous clock pulse.
•
Pin No. 22, 24,23 (DP-40)
Pin No. 29, 31, 30 (FP-54)
Pin No. 38, 37 (DP-40)
Pin No. 52, 51 (FP·54)
The active "Low" Interrupt Request lines (IRQA and IRQB)
act to interrupt the MPU either directly or through interrupt
priority circuitry. These lines are "open drain" (no load device
on the chip). This permits all interrupt request linp,s to be tied
together in a wire-OR configuration.
Each I~line has two internal interrupt flag bits that can
cause the IRQ line to go "Low". Each flag bit is associated with
a particular peripheral interrupt line. Also four interrupt enable
bits are provided in the PIA which may be used to inhibit a
particular interrupt from a peripheral device.
Servicing an mterrupt by the MPU may be accomplished by a
software routine that, on a prioritized basis, sequentially reads
and tests the two control registers in each PIA for interrupt flag
bits that are set.
The interrupt flags are cleared (zeroed) as a result of an MPU
Read Peripheral Data Operation of the corresponding data
register. Mter being cleared, the interrupt flag bit cannot be
enabled to be set until the PIA is deselected during an E pulse.
The E pulse is used to condition the interrupt controf lines
(CAl, CA, , CB I , CB,). When these lines are used as interrupt
inputs at least one E pulse must occur from the inactive edge to
the active edge of the interrupt input signal to condition the
edge sense network. If the interrupt flag has been enabled and
the edge sense circuit has been properly conditioned, the
interrupt flag will be set on the next active transition of the
interrupt input pin.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
35
H06321/H06S21------------------------_
• PIA PERIPHERAL INTERFACE LINES
The PIA provides two 8·blt bl-dlrectlonal data buses and four
Interrupt/control line. for interfacing to peripheral devices.
There is difference between 806821 and HD6321 In Port
structure. Fig. 1S shows the block diagram of Port A and Port
Bin 806321. The output drivers of Port A and Port B consist
of three-state drivers, allowing them to enter a High·impedance
state when the peripheral data line Is used as an Input. Port A
and Port B have the same output buffer. But the circuit con·
figuration is slightly different and this makes the difference on
data flow when MPU reads Port A and Port B in the case each
Port is specified al output. AI shown In Fig. 1S, the output of
the peripheral data A II transferred to internal data bus when
used as output. On the other hand, In the case of Port B the
contents of output register (ORB) Is directly transferred to
Internal data bUI through the multiplexor.
Secondly the equivalent circuit of the port In 806821 Is
shown In Fig. 16. The output circuits of A port is different
from that of B port. When the port Is used as Input, the Input
Is pullup to Vcc side through load MOS in A port and B port
becomes "Orf' (high Impedance).
g'.1I 8u.--..---------
la) Port A
Ib) Port B
Figure 15 Block Diagram of Port A and Port B (HD6321)
From DDR B
+5
+5
o
MOS
---+-< 1-------1f+---<~PA'
To Data
From ORA
Bus
1..<>e(l--+---f--+--PBx
Is) Port A
Ib) Port B
Figure 16
Circuit of Port A and Port B (HD6821)
•
36
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---------------------------------------------------------HD6321/HD6821
• Peripheral Control (CA,)
• Port A Peripheral Data (PAo-PA 7 )
Input/Output
Pin No.2 - 9 (DP-40)
Pin No. 2- 5,9- 12 (FP·54)
Input/Output
Each of the peripheral data lines can be programmed to act
as an input or output. TIlis is accomplished by setting a "I" in
the corresponding Data Direction Register bit for those lines
which are to be outputs. A "0" in a bit of the Data Direction
Register causes the corresponding peripheral data line to act as
an input. During an MPU Read Peripheral Data Operation, the
data on peripheral lines programmed to act as inputs appears
directly on the corresponding MPU Data Bus lines.
The data in Output Register A will appear on the peripheral
data lines that are programmed to be outputs. A logical "I"
written into the register will cause a "High" on the correspond·
ing peripheral data line while a "0" results in a "Low". Data in
Output Register A may be read by an MPU "Read Peripheral
Data A" operation when the corresponding lines are programm·
ed as outputs.
But concerning HD682 I , this data will be read properly if
the voltage on the peripheral data lines is greater than 2.0 volts
for a logic "I" output and less than 0.8 volt for a logic "0"
output. Loading the output lines such that the voltage on these
lines does not reach full voltage causes the data transferred into
the MPU on a Read operation to differ from that contained
in the respective bit of Output Register A.
•
Pin No. 39 (DP-40)
Pin No. 53 (FP·54)
The peripheral control line CA, can be programmed to act
as an interrupt input or as a peripheral control output.
The function of this signal is programmed by the Control
Register A. When used as an input, this signal is in High·im·
pedance state.
• Peripheral Control (CB,)
Input/Output
Pin No. 19 (DP-40)
Pin No. 26 (FP·54)
The peripheral Control line CB, may also be programmed to
act as an interrupt input or peripheral control output.
This line is programmed by Control Register B.
When used as an input, this signal is in High.impedance.
Port B Peripheral Data (PBo - PB 7 )
Input/Output Pin No. 10 - 17 (DP-40)
Pin No. 13 - 18,23 - 24 (FP·54
Each of the Port B peripheral data bus can be programmed
to act as an input or output like PAo - PA 7 •
PB o - PB 7 are in High·impedance condition because they
are three·state outputs just like PAo - PBo when the peripheral
buses are used as inputs, when programmed as outputs, MPU
read of Port B make it possible to read the output register
regardless of PBo - PB 7 loads and concerning HD6821, these
line may be used as a source of up to 2.5 milliampare (typ.)
at 1.5 volt to directly drive the base of transistor switch.
• Interrupt Input (CAl and CB I
Input
)
Pin No. 40, 18 (DP-40)
Pin No. 54, 25 (FP·54)
The peripheral Input lines CAl, and CB I are input only lines
that set the interrupt flags of the control registers. The active
transition for these signals is also programmed by the two con·
trol registers.
•
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37
H08321/H08S21--------------------------(NOTE I 1.
Pulle width of Interrupt Inputs CAl, CAt, CBI and
CSt IIhaII be lreater than • E cycle time. In the cue
that "HIah" tim. of E IlpW II not contained In
Interrupt pulle, an Interrupt !lal may not be Mt.
control the operation of the four peripheral control line. CAl,
CA2 ,CB I and CB2 • In addition they allow the MPU to enable
the Interrupt line. and monitor the statu. of the Interrupt flap.
Bill 0 throuah 5 of the two rellat,r. may be written or read by
the MPU when the proper chip Mlect and regilter Mleet alanal.
are applied. Bit. 6 and 7 of the two rep.ten are read only and
are modified by external interrupti occurring on control line.
CAl, CA2 , CB I or CB2 • The format of the control word. II
shown In Table 2.
rlble 2 Control Word Format
• INTERNAL CONTROLS
There are Iix locations within the PIA accessible to the MPU
data bus: two Peripheral Registers, two Data Direction Registers, and two Control Registers. Selection of theM locations Is
controlled by the RS o and RS I Inputs together with bit 21n the
Control Register, as shown In Table 1.
CRA
CRB
Table 1 Intemal Addressing
RS,
RS.
0
0
0
1
1
1
0
0
1
0
0
1
Control
Regilter Bit
CRB2
CRA2
1
0
x
x
x
x
x
x
x
1
0
x
Location Selected
Peripheral Regiltor A*
Dati Direction Regilter A
Control Register A
Peripheral Register B·
Data Direction Regilter B
Control Registe, B
)( = Don't Care
• Peripheral interface register is a generic term containing peripheral
data bus and output register.
• Initialization
A "Low" reset line has the effect of zeroing all PIA registers.
This will set PAo -PA7 , PHo -PB, ,CA2 and CB2 as Inputs, and
all interrupts disabled. The PIA must be configured during the
restart program which follows the reset.
Details of possible configurations of the Data Direction and
Control Register are as follows.
• Data Direction Registers (DORA and DDRB)
The two Data Direction Registers allow the MPU to control
the direction of data through each corresponding peripheral
data line. A Data Direction Register bit set at "0" configures the
corresponding peripheral data line as an input; a "I" results In
an output.
•
Data Dlraction Accesl Control Bit (CRA2 and CRB2)
Bit 2 In each Control register (CRA and CRB) allows
selection of either a Peripheral Interface Register or the Data
Direction Register when the proper register select signals are
applied to RS o and RS,.
Intarrupt Flags (CRA6, CRA7, CRB6, Ind CRB7)
The four interrupt flag bits are set by active transitions of
signals on the four Interrupt and Peripheral Control lines when
those lines are programmed to be inputs. These bits cannot be
set directly from the MPU Data Bus and are reset indirectly by a
Read Peripheral Data Operation on the appropriate section.
Control of CA, Ind CB, Interrupt Lines (CRAO, CRBO, CRA1,
and CRB1)
The two lowest order bits of the control registers are used to
control the interrupt input lines CA, and CB, . Bits CRAO and
CRBO are used to enable the MPU Interrupt signals IRQA and
IRQB, respectively. Bits CRAI and CRBI determine the active
transition of the interrupt input signals CA, and CB, (Table 3l
Control of CA2 and C~ Peripheral Control Lines (CRA3,
CRA4. CRA5, CRB3, CRB4. and CRB5)
Bits 3, 4 and 5 of the two control registers are used to
control the CA2 and CB2 Peripheral Control lines. These bits
determine if the control lines will be an interrupt input or an
output control signal. If bit CRAS (CRBS) is "0" CAl (CB2)
is an interrupt input line similar to CAl (CB)) (Table 4). When
CRAS (CRBS) is "I", CA 2 (CB 2) becomes an output signal
that may be used to control peripheral data transfers. When in
the output mode, CAl and CB, have slightly different
characteristics (Table Sand 6).
Control Registars (CRA and CRB)
The two Control Registers (CRA and CRB) allow the MPU to
~HITACHI
38
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-----------------------------------------------------HD6321/HD6821
Table 3 Control of Interrupt Input' CA. and CB.
CRAO
(CRBO)
0
0
~
0
1
~ Active
1
0
t Active
Set "'" on t of CA.
(CB I )
1
1
t
Set "'" on t of CAl
(CB I )
(Not .. )
Interrupt Input
CA. (CB.)
MPU Interrupt
CRA1
(CRBU
Interrupt Flag
CRA7 (CRB7)
Active
Active
Requ.1t
(TIm'I)
rmA
Set "'" on ~ of CA.
(CB.)
Ol,.bl.d - IRQ remain,
"High"
Set "'" on'" of CA.
(CB.)
GOI' "Low" wh.n the Int.r·
rupt fllg bit CRA7 (CRB7)
got, "'"
Cillbild - IRQ r.mlln,
"High"
Goes "Low" when the inter·
rupt flag bit CRA 7 (CR B7)
goes "1"
1. t indicat .. pOlitivltronlition ("Low" to "High")
2. ~ indicatll negative transition ,"High" to "Low")
3. Tho Interrupt flig bit CFlA 7 i. cl.ored by an MPU Fle.d of the A Peripheral Flegister
Ind CFlB7 II c'.lrod by an MPU Flead of the B Peripherll Flegiste,.
4. If CFlAOJCB.BO) il "0" whln In Interrupt occurs (Interrupt disabled) and is later brought ",".
TFmA flROIl accu" Ifter CFlAO (CFlBO) i. written to. ",".
Table 4. Control of CAl and CB, as Interrupt Inputs - CRA5 (CRB5) is "0"
CRA5
(CRB5)
CRA4
(CRB4)
CRA3
(CRB3)
0
0
0
0
0
0
1
0
,
Interrupt Input
CAl (CB,)
Interrupt Flag
CRA6 (CRB6)
MP U Interrupt
Request
IRQA (lROB)
,
~
Active
Set "'" on ~ of CAl
(CB,)
Disabled - IRO remains
"High"
~
Active
Set "'" on ~ of CAl
(CB, )
Goes" Low" when the interrupt flag bit CRA6 (CRB6)
0
t Active
Set "I" on t of CA,
(CB,)
t
Set "'" on t of CA,
(CB,)
,
Active
goes "'"
Disabled - IRO remains
"High"
Goes "Low" when the interrupt flag bit CRA6 (CRB6)
goes "'"
(Notes)
1. t indiClltel positive transition ("Low" to "High")
2. -" indicates negative transition ("High" to "Low")
3. The interrupt fleg bit CFlA6 is cleared by an MPU Flead of the A Peripheral FleglSter and eFlB6
c ....ed by an MPU Fleed of the B Peripheral Flegister.
4. If CR~RJ!3ljs "0" when an interrupt occurs (Interrupt disabled) and IS later brought
",", IFiOA (TmlEi) occurs after CFlA3 (CFlB31 "written to a"'''.
Table 5 Control of CB2 as an Output - CRB5
IS
IS "'"
CB,
,
,
CRB4
0
CRB3
0
0
,
1
1
0
CRB5
Cleared
"Low" on the positive transition of
the first E pulse after MPU
Write "B" Data Register operation.
"LoW" on the positive transition of
the first E pulse after an MPU Write
"B" Data Register operation.
Set
"High" when the interrupt flag bit
CRB7 is set by an active transition
of the CB I signal. (See Figure '6)
"High" on the positive edge of the
first "E" pulse following an "E"
pulse which occurred while the
part was deselected. (See Figure 16)
"Low"
(The content of CRB3 is output on CB,)
1
1
1
"High"
(The content of CRB3 is output on CB, )
~HITACHI
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39
HD6321/HD6821--------------------------------------------------------Table 6 Control of CAl as an Output - CRA5
CRA5
1
CRA4
CRA3
0
0
1
0
1
1
1
0
1
1
1
Cleared
"Low" on negative transition of E
after an MPU Read" A" Data Operation.
"Low" on negative transition of E
after an MPU Read "A" Data operatic,m.
"1"
CAl
IS
Set
"H igh" when the interrupt flag bit
CRA7 is set by an active transition
of the CAl signal. (See Figure 16)
"High" on the negative edge of the
first "E" pulse which occurs during
a deselect. (See Figure 16)
"Low"
(The content of CRA3 is output on CAl)
"High"
(The content of CRA3 is output on CAl)
• PIA OPERATION
•
Initialization
When the external reset input RES goes "Low". all internal
registers are cleared to ''0''. Periperal data port (PAo -PA7.
PBo-PB,) is dermed to be input and control lines (CAl. CAl.
CB I and CB2 ) are dermed to be the interrupt input lines. PIA is
also initialized by software sequence as follows.
• Program the data direction register access bit of the control
register to "0" to allow to access the dada direction register.
Cle.r the control reglstlr
Laad input/output direction data into ACC
Store the contants of ACC into the
data dl rection register
Load the control data to be written Into ACC
• The data of the control line function is set into the accumuIator. of which Data Direction Register Access Bit shall be
programmed to "I".
• Transfer the control data from the accumulator into the
control register.
Store the contents of ACe into the control register
Input/output procassing
• ReadMlrite Operation Not Using Control Lines
Set the data direction register to
''~O''
Initialize the control register
Clear the DDRA access bit of the control register to "0".
Clear all bits of the dada direction register.
• Set DDRA access bit of the control register to "I" to allow
to access the peripheral interface register.
CLR
CLR
LOAA
STAA
CRA
•
DORA •
LOAA
PIRA
#$04
CRA
Load the contents of the peripheral
interface register into the accumulator
•
40
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-----------------------------------------------------H06321/H06S21
SIt the dIIte dl ...ctlon ..gllter to "FF"
Inltl.II •• the control regllter
Store thl d.t. In thl eccumul.tor Into
outPut regllter
CL.R
L.OAA
STAA
L.OAA
STAA
CRA
I
Set OORB accell bit of the control reiliter to "0".
~~:B}
I
Set all bltl of the data direction regilter to "PP".
/;~}
I
Set OORB acce.. bit of the control reillter to "1" to allow to
acee.. the peripheral Interface relilter.
I
Write the data Into the peripheral Interface rqilter.
,
CRB
I
DATA}
PIRB
I
I
LOAA
STAA
A_IWr. ()perItint IJIlnt Control LI....
Read/write request from peripherals shall be put Into the
control Unal u an interrupt 1ipIal, and then MPU reads or
writes after detecting interrupt request.
I
The following cue II that Port A II used and that the riIInB
edge of CA, Indicates the request for read from periphera1e.
SIt the dote direction ...gllter to "00"
CLR
CLR
CRA •
DORA I
L.OAA /;$06
'n Itlallu thl control I'IIllIIr
Lood the f.:;~~: ::'~~uf.~~~OI register
1-_ _ _ _ _ _-,-_ _ _ _ _ _---1
STAA CRA
I
Set the OORA access bit to "0".
Set all bits of the data direction rqlatar to "0".
Prosram the rising edge of CA, to be active. iiQA II muked
and OORA accesl bit II let to 1.
LOOP LOAA CRA )
BPL LOOP
•
Check whether the read request comes from peripherals
or not.
No
Lood the contents of the peripheral
interfe"l'IIllter into the ..cumulator
LOAA PIRA
• Load the data from the peripheral interface register into the
accumulator. CRA flag is reset after this read operation.
To read the peripheral data, the data is directly transfered to
the data buses 0 0 -01 through PAo-PA1 or PBo-PB, and
they are not latched in the PIA. If necessary, the data should be
held in the extema1latch until MPU completes reading it.
When initiallzing the control register, interrupt flag bit
(CRA7, CRA6, CRB7, CRB6) cannot be written from MPU. If
necessary the interrupt flag must be reset by dummy read of
Peripheral Register A and B.
Write operation UIing the interrupt signal II u followa. In
this ca•• B port II used and interrupt request is input to CB, .
And the
flag is let at the rising edge of CB, .
om
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41
HD6321/HD6821---------------------------------------------------------
I
Set the data direction register to "FF"
CLR
LDAA
STAA
j
Initialize the control register
I
CRB
•
Set DDRB access bit to "0"
#$FF }
DDRB
•
Set all bits ofDDRB to output "I".
LDAA
#$06
STAA
CRB
LOOP LDAA
CRB
Program the rising edge of CBI to be active. IRQB is masked
and DDRB access bit is set to "I".
t
Load the content. of the control
register into the accumulator
No
BPI-
LOOP
• Check whether the write request comes from peripherals
or not.
4?>
Ves
load the contents of the output
register in the accumulator
LDAA
PIRB
• Reset the CRB7 flag by the dummy read of the
peripheral interface register.
STAB
PIRB
• Store the data of the accumulator B to the peripheral
interface register.
l
Store the contents of the accumulator
into the output register
!
Interrupt request flag bits (CRA 7, CRA6, CRB7 and CRB6)
cannot be written and they cannot be also reset by write
operation to the peripheral interface register. So dummy read of
peripheral interface register is needed to reset the flags.
To accept the next interrupt, it is esaential to reset indirectly
the interrupt flag by dummy read of peripheral interface
register.
Software poling method mentioned above requires MPU to,
continuously monitor the control register to detect the read/
write request from peripherals. So other programs cannot run at
the aame time. To avoid this problem. hardware interrupt may
be used. The MPU is interrupted by IRQA or IRQB when the
read/write request is occurred from peripherals and then MPU
analyzes cause of the interrupt request during interrupt procesaing.
• Handshake Mode
The functions of CRA and CRB are similar but not identical
in the hand-shake modes. Port A is used for read hand-shake
operation and Port B is used for write hand-shake mode.
CAl and CBI are used for interrupt input requests and CA2
and CB2 are control outputs (answer) in hand-shake mode.
Fig. 17, Fig. 18 and Fig. 19 show the timing of hand-shake
mode.
< Reed Hand-shak. Mode>
CRAS="I", CRA4="O" and CRA3="0"
CD A peripheral device puts the S-bit data on the peripheral
data lines after the control output CAl goes "Low".
a:J The peripheral requests MPU to read the data by using CAl
input.
Q) CRA 7 flag is set and CA2 becomes "High" (CA2 automatically becomes "High" by the interrupt CAl). This
indicates the peripheral to maintain the current data and
not to tranafer the next data.
@ MPU accepts the read request by IRQA hardware interrupt
or CRA read. Then MPU reads the peripheral register A.
@ CA 2 goes "Low" on the following edge of read Enable
pulse. This informs that the peripheral can set the next data
to port A.
CRBS = "I", CRB4= "0" and CRB3 = "0"
eRAS = "1", CRA4= "0" and CRA3 = "I"
CRBS = "I", CRB4 = "0" and CRB3 = "1"
This mode is shown in Figure 17, Figure 20 and Figure 21.
~HITACHI
42
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
---------------------------------------------------------HD6321/HD6821
CRA5 CRA4 CRA3
:m
CS oRS,oFi5.
I
~-~
I
:
~------~i---------------I
>----;--------------
PA.-PA,
CA,
"",..--
READ Request
CRA7
CA,
o
o
o
Busy
CRB5 CRB4 CRB3
E
Rm
®
CSoRs,oRS;;
D.-D?
i
!.,
PB.-PB,
t:
...
0
CB,
dummy Read
Reset
@
CB,
0
®
PB. -PB, dote is old.
0
0
CB,
Figure 17
Busy
Busy
Timing of Hand-shake Mode and Pulse Mode
~HITACHI
Hitachi America LId . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
43
HD6321/HD6821--------------------------------------------------------G_"HIgh"an
t ....ition of CA,
(lROAl FI811bit oetl
Gol. "Low" when detll on
"A" lid ..... been r.... by
MPU after filling edge
~ of anobillienil
(LOA A PIRA)
\J~----------~/r
CA,
J
EnabI,"ignol (E)
Handshaking with peripheral on 'A' side
Dote
PIRA
CA,I.-____________;
Periph.ral
PIA
Peripheral Sovs:
Here's new dota
(Sou CRA7)
Figure 18
8 its 5, 4, 3 of CRA = 100 (Hand-shake Mode)
G_ "Low" on first
positive edge of anoble
signal after the MPU
::3'--'"
Goes "High" or transition
ltorl' dati to the "Bu
side_ (STA A PIRB)
:·I-·--~r_
Enob~Sl-IL-
lignol
(E)
Handshaking with peripheral on 'B' side
Dote
I
I
PIRB
I
CB,
PIA
CB,
,
Oft,
•
Ixlol'lolol'lol'l
7"----
ISTA A PIRB)
Bits 5, 4, 3 of CRB = 100 (Hand-shake Mode)
•
44
Peripherll
Per·op.....
Request for dlte
Says: Heres new~te
Figure 19
J
HITACHI
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------HD6321/HD6821
Goes "High" on
CA, Normally
"High"
tho negatiw
Goes "Low" aftor a "Reed a side
data" Instruction (LOA)
edge of the
next E puis.
(Negative transition of E)
aft• •
"Reed a
sido dote"
Instruction
(LOA)
Enable
signal ( E ) I L ._ _ _ _ _~
Pulse mode
Pulse output on 'A' side
Data
l!~
1
HI
I
PIRA
PIA
Peripheral
CA,
CRA
7
0
1-1 1' 101'1'1-1-1
0
Figure 20
CB, Normally
"High"
Bits 5, 4, 3 of CRA = 101 (Pulse Mode)
Goe. "High" on the
Goes "Low" on the positive
transition of the first
E pulse after I "write B
next poSItive E
pulse after A
"write B
side data"
instruction
lide data" instruction
(STAI
(STA)
Enable
Ilgnal
(E)
IL.-__
..J
ItI
I
Pulse mode
Pulse output on 'B' side
Data
JJl
I
PIRB
PIA
Peripheral
CB,
7
CAB
0
1,101'1 0 1'1'1-1-1
Pu..
I In It I• ted .. • I'ftU It
of
~n~~~~)"lda
';\!J.:"
Figure 21
Xew
dota presented
at port
for peripheral
Bits 5, 4, 3 of CRB = 101 (Pulse Mode)
•
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45
HD6321/HD6821--------------------------------------------------------• SUMMARY OF CONTROL REGISTERS CRA AND CRB
•
Control registers CRA and CRB have total control of CA. ,
CA., CB., and CB. lines. The status of eight bits of the control
registers may be read into the MPU. However, the MPU can only
write into Bit 0 through Bit 5 (6 bits), since Bit 6 and Bit 7 are
set only by CAl, CA., CB. , or CB•.
(True~ 0.4 volts), the following procedure should be used.
When all the outputs of given PIA port are to be active "Low"
a)
b)
c)
d)
e)
• Addressing PIAs
Before addressing PIAs, the data direction (DDR) must first
be loaded with the bit pattern that defines how each line is to
function, i.e., as an input or an output. A logic "I" in the data
direction register defines the corresponding line as an output
while a logic "0" defines the corresponding line as an input.
Since the DDR and the peripheral interface resister have the same
address, the control register bit 2 determines which register is
being addressed. If Bit 2 in the control register is a logic "0",
then the DDR is addressed. If Bit 2 in the control register is a
logic "I", the peripheral interface register is addressed. There·
fore, it is essential that the DDR be loaded first before setting
Bit 2 of the control register.
Given a PIA with an address of 4004,4005,4006, and 4007.
4004 is the address of the A side peripheral interface register.
4005 is the address of the A side control register. 4006 is the
address of the B side peripheral interface register. 4007 is the
address of the B side control register. On the A side, Bits 0, 1,2,
and 3 will be defined as inputs, while Bits 4, 5,6, and 7 will be
used as outputs. On the B side, all lines will be used as outputs.
I.
2.
3.
4.
5.
6.
7.
PIA lAD = 4004
PIAIAC = 4005
PIAIBD = 4006
PIAlBC = 4007
(DORA, PlRA)
(CRA)
(DDRB, PIRB)
(CRB)
LOA A #%11110000
STAA
PIAIAD
LOA A #% 11111111
STA A
PIAIBD
LOA A #0/000000 I 00
STAA
PIAIAC
STA A
PIAIBC
(4 outputs, 4 inputs)
(Loads A DDR)
(All outputs)
(Loads BOOR)
(Sets Bit 2)
(Bit 2 set in A control register)
(Bit 2 set in B control register)
PIA Programming Via The Index Register
The program shown in the previous section can be accom·
plished using the Index Register.
I.
2.
3.
4.
LOX
STX
LOX
STX
#$ F004
PIA lAD
#$FF04
PIAIBD
Set Bit 2 in the control register.
Store allis ($FF) in the peripheral interface register.
Clear Bit 2 in the control register.
Store allis ($FF) in the data direction register.
Store control word (Bit 2 = I) in control register.
The B side of PIAl is set up to have all active low outputs.
CB. and CB. are set up to allow interrupts in the HANDSHAKE MODE and CB. will respond to positive edges
("Low"-to-"High" transitions). Assume reset conditions. Addresses are set up and equated to the same labels as previous
example.
I.
2.
3.
4.
5.
6.
7.
8.
LOA A #4
STA APIAIBC
LOA B #$FF
STA B PIAIBD
CLR PIAIBC
STA BPIAIBD
LOA A #$27
STA A PIAIBC
Set Bit 2 in PIAIBC (control register)
AllIs in peripheral interface register
Clear Bit 2
All I s in data direction register
00100111 .......... control register
The above procedure is required in order to avoid outputs
going "Low", to the active "Low" TRUE STATE, when allIs
are stored to the data direction register as would be the case if
the normal configuration procedure were followed.
•
Statement 2 addresses the DDR, since the control register
(Bit 2) has not been loaded. Statements 6 and 7 load the control
registers with Bit 2 set, so addressing PIA lAD or PIA IBD
accesses the peripheral interface register.
•
Active Low Outputs
Interchanging RSo And RS.
Some system applications may require movement of 16 bits
of data to or from the "outside world" via two PIA ports (A
side + B side). When this is the case it is an advantage to
interconnect RS. and RSo as follows.
RS o to Al (Address Line AI)
RS. to AO (Address Line AO)
This will place the peripheral interface registers and control
registers side by side in the memory map as tollows.
Table
Example
PIAIAD
PIAIBD
PIAIAC
PIAIBC
$4004
$4005
$4006
$4007
Addr~ss
$FO.....PIA lAD ;$Q4.....PIAI AC
The index register or stackpointer may be used to move the
16-bit data in two 8-bit bytes with one instruction. As an
example:
LOX PIAIAD
PIAIAD .......... IXf·r: PIAIBD -- (XL
$FF.....PIAIBD;$04.....PIAIBC
• PI A - After Reset
Using the index register m this example has saved six bytes of
program memory as compared to the program shown in the
previous section.
When the RES (Reset Line) has been held "Low " for a
minimum of one microsecond, all registers in the PIA will be
cleared.
Because of the reset conditions, the PIA has been defined as
~HITACHI
46
(DORA, PIRA)
(DDRB, PIRIl)
(CRA)
(CRB)
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------------HD6321/HD6821
follows.
1. All I/O lines to the "outside world" have been defined as
inputs.
2. CAL, CA2 , CB" and CB2 have been defined as interrupt
input lines that are negative edge sensitive.
3. All the interrupts on the control lines are masked. Setting of
interrupt flag bits will not cause IRQA or IRQB to go "Low".
• SUMMARY OF CA2 -CB2 PROGRAMMING
Bits 5, 4, and 3 of the control registers are used to program
the operation of CA 2 -CB2 .
CA2 -CB 2
Input ~
Mode
• SUMMARY OF CAL ·CB I PROGRAMMING
Bits I and 0 of the respective control registers are used to
program the interrupt input control lines CAL and CB, .
bl
bO
o
o
1
o
1
o
1
1
CA2 -CB 2
Output ~
Mode
m
b5
b4
0
0
0(-)
0(-)
1(+)
o
ill
1
1
1
1(+)
b3
o
(Mask) CA 2 -CB 2 Input Mode
(Allow) b4 = Edge (0 = -, 1 = +)
(Mask) b3 = Mask (0 = Mask,
(Allow)
1 = Allow)
1
o
1
o-
Handshake Mode
1 - Pulse Mode
0
0
1
1
~
I
b3 Following Mode
bl = Edge (0 = -, 1 = +)
bO = Mask (0 = Mask, 1 = Allow)
Note that this is the same logic as Bits 4 and 3 for CA2 -CB 2
when CA 2.CB2 are programmed as inputs.
I.-------CA,
I------+CA,
I-------+PA,
i+------ PA ,
I/O As Follow:
Control Li oes:
CAl - Positive Edge, Allow Interrupt
CA, - Pu Is. Mode
- Negative Edge, Mask interrupt
CB, - Hand Shake Mode
t-----.....,~ PA,
"A"
t-----.....,~ PA,
es 1
1-_________+
Assume Reset Condition
PIAIAO
PIAIAC
PIAIBO
PIA1BC
1+____________
PA,
t-----.....,~ PA,
------------1+------------ CB,
PIA Configuration Solytlon
LOA A #$BC
STA A PIAIAO
LOA A #$FF
STA A PIAIBO
LOA A #$2F
STA A PIAIAC
LOA A #$24
STA A PIA1BC
PA,
1+------------ PA.
1-----------+ CB,
10111100
I/O to DORA
11111111
I/O to OORB
00101111
To "A" Control
00100100
To "8" Control
t------~ PB,
"B"
1-----------+
Figure 22
PB.
PIA Configuration Problem
@HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
47
HD6321/HD6821------------------------------------------------------•
NOTE FOR USE
Compatibility with NMOS PIA (HD682l1
Table 7 Comparison CMOS PIA (HD6321) with NMOS PIA (HD6821)
CMOS PIA (HD6321)
Item
NMOS PIA (HD6821)
Pull·up output
Three·state output
+5V
PortA
Output
8uffer
+5V
DoRA~
PA.-PA,
CA,
ORA
Internal ~~.AL.."/""-----"'"
Date Bus
t
Read Signal
Measure for Input floating
Three ..tate output
Thrae..tate output
+5V
Port 8
Output
Buffer
+5V
-~
PMOS
DDRB
t-___
,...~PB. -PB,
ORB_
CB,
Internal
Data Bus
NMOS
t---_-.PB. - PB,
CB,
ORB
Internal
Date Bus
/
Read'ignal
Measure for Input floating
Thera is no differance between CMOS PIA and NMOS PIA in pin arrangement.
•
48
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
HD6340/HD6840---------PTM (Programmable Timer Module)
The HD6340/HD6840 (PTM) is a programmable subsystem
component of the HMCS6800 family designed to provide
variable system time intervals.
The PTM has three l6-bit binary counters, three corresponding control registers and a status register. These counters are
under software control and may be used to cause system interrupts and/or generate output signals. The PTM may be utilized
for such tasks as frequency measurements, event counting,
interval measuring and similar tasks. The device may be used for
square wave generation, gated delay signals, single pulses of
controlled duration, and pulse width modulation as well as
system interrupts.
•
•
•
•
•
•
•
•
•
FEATURES
Operates from a Single 5 volts Power Supply
Single System Clock Required (E)
Selectable Prescaler on Timer 3 Capable of 4 MHz for the
HD6340/HD6840, 6 MHz for the HD63A40/HD68A40 and
8 MHz for the HD63B40/HD68B40.
Programmable Interrupts (lRO) Output to MPU
Readable Down Counter Indicates Counts to Go until Timeout
Selectable Gating for Frequency or Pulse-Width Comparison
Three Asynchronous External Clock and Gate/Trigger
Input Internally Synchronized
Three Maskable Outputs
HD6340P, HD6840P
(DP-28)
The specifications of the HD6340 are for preliminary and
may change hereafter.
Please make an inquire at sales office upon adoption of the
HD6340.
-HD6340• Wide Range Operating Voltage (Vee = 5V ±10%)
• Low-Power, High-Speed, High-Density CMOS
• Compatible with NMOS PTM (HD6840)
-HD6840• Compatible with MC6840, MC68A40 and MC68B40
C,
Vss
G,
A,
0,
G,
C,
D.
G,
D,
0,
D,
C,
D,
RES
D,
IRO
Ds
D.
•
TYPE OF PRODUCTS
Type
Process
HD6340
HD63A40
Clock -Frequency
CMOS
1.5 MHz
2.0 MHz
HD6840
1.0 MHz
HD68B40
Package
E
CS,
1.0 MHz
HD63B40
HD68A40
D,
RS,
NMOS
1.5 MHz
CSo
DP-28
(Top View)
DP-28
2.0 MHz
~HITACHI
H,tachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
49
HD6340/HD6840------------------------------------------------------• ABSOLUTE MAXIMUM RATINGS
Value
HD6840
HD6340
Symbol
.
Item
Unit
Supply Voltage
Vee
-0.3-+7.0
-0.3-+7.0
Input Voltage
Vine
-0.3-+7.0
Maximum Output Current
Iioin
10
Operating Temperature
Topr
-20-+75
Storage Temperature
Tstg
-55-+150
----
v.. (SYSTEM
V
-0.3-+7.0
V
mA
-20-+75
·C
- 55-+150
·C
•
Wlt~
.*
Maximum output current is the maximum currents which can flow out from one output
respect to
GND)
terminal or 110 common terminal. (Do - ~. 01 (NOTE)
~,
Tfi(i)
Permanent LSI damage may occur if maximum ratings are exceeded. Normal
operation should be under recommended operating conditions. If th_
conditions are exceeded, it could affect reliability of LSI.
• RECOMMENDED OPERATING CONDITIONS
Item
Symbol
··
Supply Voltage
Vee
Input "Low Voltage
VIL
·
Input "High"l EI Rm
Voltage
Other Inputs
VIH
Operating Temperature
Topr
I
HD6840
HD6340
Unit
min typ max min typ max
4.5 5.0 5.5 4.75 5.0 5.25 V
0
-
0.8
2.6"
-
Vee
2.2
-20 25
-0.3
-
0.8
V
2.2
-
Vee
V
75
·C
Vee
75
-20 25
• With respect to V.. (SYSTEM GNO)
•• Characteristics to be improved.
$
50
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------HD6340/HD6840
•
•
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (HD6340; Vee
HD6340
Symbol
Item
= 5V ±10%, HD6840; Vee = 5V ±5%, Vss = OV, 1a = -2D--+75°C, unless otherwise noted.)
Test Condition
HD6840
min
wp*
Input "Low" Voltage
V IL
Input Leakage Current
l,n
Vm =0""" Vee (Except 00-07)
-2.5
-
Three-State Input
Current (Off-state)
I TSI
Vm = 0.4,.., Vee,
Vee = 5.5V 100-071
-10
-
-
Input "High" Voltage
I E,R/W
Other
Inputs
2.6**
V IH
2.2
-0.3
4.1
ILOAD = -400~A iDo-D71
Ivee -0.1
ILOAD:;; 10!,A 100- 0 71
Output "High" Voltage
V OH
I LOAD = -400!'A 10ther Outputsl
O_utput Leakage Current
10ff·statel
ILOAD = 1.6mA 100-071
VOL
I LOH
VOH = Vee liRTIl
Vee
-0.3
0.8
V
Vin=O ...... V cc (Except Do""" 07) -2.5
-
2.5
~A
10
V ,n = 0.4-2.4V
Vee = 5.25V 100-071
-
10
~A
-
ILOAD = -20S!'A 10,-0,1
2.4
-
-
V
-
-
04
V
-
-
10
!'A
-
-
-
0.4
-
-
10
I LOAD
= -200!'A Ig~~~~tsl
ILOAD
= 1.6mA
100-0 71
VO H = 2.4V IIRQI
E = 2.0 MHz
-
-
2.0
E = 1.0 MHz
-
-
3.0
E = 1.5 MHz
-
-
4.0
E = 2.0 MHz
-
-
6.0
• Data bus in RIW
operation.
• Counters are operating.
• 01 ""03 0 perating
with load.
E=1.0MHz
-
E=1.5MHz
8.0
E = 2.0 MHz
-
-
10.0
Vm '" OV.
Do - 0,
-
-
12.5
Ta = 25°C
f = 1 MHz
V in = OV.
Ta =: 2SoC
Other Input
7.5
f = 1.0 MHz Other Input
not selected
Input level (Except E)
-10
ILOAD = 3.2mA.
10 -0 IRQ)
1.5
IS
mA
5.0
Po
Con
Cout
0 0 -0 7
Vm=OV.
IRQ
-
-
5.0
T a =25°C,
f = 1 MHz
-
-
Vm =: OV
Ta "" 25°C
0 1. O2. 03
100
f = 1.0 MHz 0 1.02.03
** VIH '" 2.2V at Vce = 5V ±5%, Ta
V
25
1.0
• Counters are operating.
Unit
0.8
-
VIL max = 0.8V
* Ta "" 2Soc, Vcc = S.OV
-
-
{VIH min = Vcc-O.S
Output Capacitance
2.2
-
o
Input Capacitance
-
-
• 01'" 03 operating
with load.
Power DiSSipation
max
E = 1.0 MHz
• Chip
Icc
tvp*
E=1.5MHz
• Input level (Except E)
{VIH mm=Vcc-O.8V
V)L max = 0.8V
Supply Current
min
Vee
ILOAD = 3.2mA 10,-03, IRQ)
• Chip is not selected.
o All cou nter latches
are preset.
• 01 -03 outputs are
masked.
Test Condition
Vee
-
V ee -D.1
I LOAD';; 10!,A 10ther Outputsl
Output "Low" Voltage
4.1
max
IRO
330
550
-
-
12.5
-
-
7.S
-
-
10.0
-
mW
pF
5.0
pF
= O...... 70°C. Characteristics to be improved.
~HITACHI
HitachI America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
51
HD8340/HD8S40------------------------• AC CHARACTERISTICS (HD8340; Vee -8V :1:10%, HD8840; 8V :1:8%, VII- OV, T. - -20"'+78°C, unl ... otharwl.. noted.1
1. MPU READ TIMING
l
Symbol
111m
HCB340
Till
Condilion min
mIX
HCB3A40
min
mIX
HCB3B40
min
mi.
HCB840
min
mIX
HCeeB40
min
mi.
HCBSA40
min
mi.
Unit
Enlbll Cyell Tlml
IcyeE
1000
10000 BeS
10000 600
10000 1000
10000 BBe
10000 600
10000
nl
Enlbll "High" PUIII Width
PW!H
460
S600 260
9800 220
9600 460
4600 2S0
4600 220
4800
nl
Enlbll "L.ow" Pul .. Width PWEL.
430
S600 2BO
S600 210
9600 430
-
-
-
-
-
-
Enlbll Rill Ind F." Tlml
IEr' lEI
Addr..1 SoI.Up Tlml
lAS
CIII CIIIY Tim.
ICCA
ISO
-
160
CIII Hold Tlml
IHR
20
100
20
100
20
100
10
IAH
10
-
10
-
10
tACC
-
-
10
Add,," Hold Tim.
Cltl Accl.. Time
Fig. I
25
-
SO
-
26
-
eo
-
290
-
370
20
-
40
-
240
-
26
-
140
-
-
-
10
-
nl
-
nl
lao
nl
-
10
10
-
360
nl
26
70
220
10
480
-
-
-
-
-
210
25
140
320
-
190
2S0
n,
n,
n,
260
2. MPU WRITE TIMING
Symbol
Itlm
HC6340
Tesl
Condition min
ma.
HC63B40
min
ma.
HC63A4O
min
ma.
HC6840
min
ma.
HC6SA40
min
ma.
HC68B4O
min
ma.
Unit
teyeE
1000
10000 666
10000 600
10000 1000
10000 666
10000 600
10000
Enable "High" Pul.e Width PWEH
460
9500 280
9500 220
9600 460
4600 280
4600 220
4600
ns
Enable uLow" Pulse Width
PWEL
430
9600 280
9600 210
9600 430
-
n.
Enable Aise and Fa" Time
tEr' tEl
-
26
-
80
-
60
Enable Cycle Time
Address
Set~up
Time
Fig. 2
tAS
Data Setwup Time
tcsw
165
Data Hold Time
tHW
10
-
Addr... Hold Time
tAH
10
-
-
26
60
10
-
10
-
10
-
10
-
80
-
20
40
-
280
-
210
n.
26
-
25
-
140
-
140
-
140
196
-
80
-
60
-
10
-
10
-
ns
10
10
-
10
-
ns
-
10
25
ns
n.
n.
3 TIMING OF PTM SIGNAL
Item
Input Rise and Fall
Time
c;n, Fm!
Input "Low" Pulse
Width
c,1'i,m
Input "High"
Pulse Width
c.1'i
Symbol
Test Condition
t r, tl
Fig. 3, Fig. 4
Fig. 3
PW L
Asynchronous
PWH
Asynchronous
Mode
Fig.4
C:CJ,"RES
Input Setup Time
Input Hold Time
Input Pul.e Width
Mode
Fig. 5
iC~8 Pre· tsu
scalar Mode)
c.G,"RES
Synchronous
Mode
Fig. 5
C3 (+8 Pre· tHO
.calar Mode)
Synchronous
C3 (... 8 Pre· PWL
scaler Mode) PWH
Asynchronous
Output Delay Time 0,-03
~
Mode
Mode
Fig. 6
HD6340
min
max
-
1000'
H063A4O
rna.
min
-
tcycE
+tSU
+tHo
-
tcycE
+tsu
+tHo
tcycE
+tSU
+tHO
-
tcycE
+tSU
+tHD
H063B4O
max
min
666'
-
-
tcycE
+tSU
+tHo
600'
-
-
tcycE
+tSU
+tHD,
75
-
200
-
120
170
-
200
-
170
50
-
50
-
50
126
-
60
50
-
50
-
60
-
80
-
60
-
200
-
200
-
200
-
~
tamos
Interrupt Releell Tim.
IIA
Flg.7
-
1200
•
52
-
666'
teyeE
+tSU
+tHO
50
120
-
teyeE
+tSU
+tHo
-
-
170
1000'
tcycE
+tSU
+tHo
-
120
tcycE
+tsu
+tHO
H068A40
max
min
-
200
200
H06840
min
max
900
-
700
-
-
50
-
84
700
-
-
60
450
900
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (4081435-8300
tcycE
+tsu
+tHD
-
ns
75
-
ns
B2.6
1360
n.
n.
460
500'
-
170
450
-
-
Unit
tcycE
+tsu
+tHO
-
2000
1200
HD68B40
ma.
min
60
-
50
-
-
ns
ns
ns
-
ns
340
n.
340
n.
1000
n.
700
n.
---------------------------------------------------------HD6340/HD6840
E
RS,
CS, Rm
Data Bus
Figure 1 Bus Read Timing
(Read Information from PTM)
Figure 2 Bus Write Timing
(Write Information into PTM)
Figure 3 Input Pulse Width "Low"
Figure 4
E
Input Pulse Width "High"
E
temos···
c;-c"a.-G"
0, -0,
RES
VOH (CMOS)
Figure 5
•
Input Setup and Hold Times
_l=m-t-·~-R-J---V-C-C---2-.0-V.
=0.7 x Vee
Figure 6 Output Delay
• 2.4V for HD6840
*., *** HD6840 only
IRQ _ _ _ _ _ _ _ _ _
....
Figure 7
I RQ Release Time
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
53
H08340/H08S40------------------------Lo.d A
(D,
D,)
!.OV
Lo.d B
(0 •• 0,.0,)
N
-.-*-..
-.--!4-..
T.lt Polnto-.....
130 pF
Tell Point 0-.....
All dlod.l.r.
lS2074
or equlv.
40 pF
e
10 kn'
10kn"
Adlull R~
that lo~ -.3.2 mA
thin till Vo~
10
All diode.. "
182074 eor equiv.
LOld C
6.0V
Lold D
(Tlm0;jIV)
(~
1.3kn
T.II Polnl
100pF
.Cl.!.Os)
(CMOS Load)
(MOS)
TellPol"t
I
1
T 30pF
rh
Figure 8 Test Loads
• 11 kn for HD6840
•• 12 kn for HD6840
• GENERAL DESCRIPTION
activated).
The PTM is part of the HMCS6800 microprocessor family
and is fully bus compatible with H06800 systems. The three
timers in the HD6340/H06840 operate independently and in
several distinct modes to fit a wide variety of measurement and
synthesiS applications.
The PTM is an integrated set of three distinct counter/
timers. It consists of three 16·bit data latches, three 16·bit
counters (clocked independently), and the comparison and
enable circuitry necessary to implement various measurement
and synthesis functions. In addition, it contains interrupt drivers
to alert the processor that a particular function has been
completed.
in a typical application, a timer will be loaded by first storing
two bytes of data into an associated Counter Latch. This data is
then transferred into the counter via a Counter initialization
cycle. If the counter is enabled, the counter decrements on each
subsequent clock period which may be an external clock, or
Enable (E) until one of several predetermined conditions causes
it to halt or recycle. The timers are thus programmable, cyclic in
nature, controllable by external inputs or the MPU program,
and accessible by the MPU at any time.
• Chip Select
This signal is generated by the MPU to control the direction
of data transfer on the Data Bus. With the PTM selected, a
"Low" state on the PTM R/W line enables the input buffers and
data is transferred from the MPU to the PTM on the trailing
edge of the Enable (System 1/l2) signal. Alternately, (under the
same conditions) R/W = "High" and Enable "High" allows data
in the PTM to be read by the MPU.
• PTM INTERFACE SIGNALS FOR MPU
•
The Programmable Timer Module (PTM) interfaces to the
HMCS6800 Bus with an eight.bit bidirectional data bus, two
Chip Select lines, a Read/Write line, an Enable (System 1P2) line,
an Interrupt Request line, an external Reset line, and three
Register Select lines. These signals, in conjunction with the
H06800 VMA output, permit the MPU to control the PTM.
VMA should be utilized in conjunction with an MPU address
line into a Chip Select of the PTM, when the H06800, H06802
are used.
•
Input
=
Input
Enable
Pin No. 13
lEI
Input
Pin No. 17
This signal synchronizes data transfer between the MPU and
the PTM. It also performs an equivalent synchronization function on the external ciock, reset, and gate inputs of the PTM.
• Interrupt Request (fIfOl
Output (open drain) Pin No.9
Pin No. 2S - 18
The bidirectional data lines (0 0 -0 7 ) allow the transfer of
data between the MPU and PTM. The data bus output drivers
are three06tate devices which remain in the high·impedance (off)
state except when the MPU performs a PTM read operation
(Read/Write and Enable lines "High" and PTM Chip Selects
•
54
Pin No. 15, 16
These two signals are used to activate the Oata Bus interface
and allow transfer of data from the PTM. With CS;; = "Low"
and CS. "High", the device is selected and data transfer will
occur.
• Reacl/Write IR/Wl
Bidirectional Data (Do - 0 7 )
Input/Output
ICSO. CS 1 )
The active "Low" Interrupt Request signal is normally tied
directly (or through priority interrupt circuitry) to the IRQ
input of the MPU. This is an "open drain" output (no load
device on the chip) which permits other similar interrupt reo
quest lines to be tied together in a wire·OR configuration.
The IRQ line is activated if, and only if, the Composite Inter·
rupt Flag (Bit 7 of the Internal Status Register) is asserted. The
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 •. (4081435·8300
------------------------------------------------------HD6340/HD6840
conditions under which the iRO line is activated are discussed in
conjunction with the Status Register.
• Reset (RES)
Pin No.8
Input
A "Low" level at this input is clocked into the PTM by the
Enable (System q,2) input. Two Enable pulses are required to
synchronize and process the signal. The PTM then recognizes the
active "Low" or inactive "High" on the third Enable pulse. If
the
signal is asynchronous, an additional Enable period is
required if setup times are not met. The RES input must be
stable "High"'''Low'' for the minimum time stated in the AC
Characteristics.
Recognition of a "Low" level at this input by the PTM
causes the following action to occur:
a. All counter latches are preset to their maximal count
values.
b. All Control Register bits are cleared with the exception of
CRIO (internal reset bit) which is set.
c. All counters are preset to the contents of the latches.
d. All counter outputs are reset and all counter clocks are
disabled.
e. All Status Register bits (interrupt flags) are cleared.
• Register Select Lines (RS o• RS 1 • RS 2 )
These inputs are used in conjunction with the R(W line to
select the internal registers, counters and latches as shown in
Table 1.
m
.
Aagilter
Select Inpull
AS, AS. AS,
L
L
L
L
L
L
H
H
L
H
H
L
L
H
H
H
L
H
L
H
H
H
L
H
Input
Pin No. 10, 11, 12
It has been previously stated that the PTM is accessed via
MPU Load and Store operations in much the same manner as a
memory device. The instructions available with the HMCS6800
family of MPUs which perform operations directly on memory
should not be used when the PTM is accessed. These instructions actually fetch a byte from memory, perform an operation,
then restore it to the same address location. Since the PTM used
the R(W line as an additional register select input, the modified
data may not be restored to the same register if these instructions are used.
• PTM ASYNCHRONOUS INPUT/OUTPUT SIGNALS
Each of the three timers within the PTM has external clock
and gate inputs as well as a counter output line. The inputs are
high impedance, TTL compatible lines and outputs are capable
of driving two standard TTL loads.
• Clock Input. (Cj. C;. C; )
Input
Pin No. 28, 4, 7
Input pins ~, C;, and c; will accept asynchronous TTL
voltage level signals to decrement Timers 1, 2, and 3, respectively. The "High" and "Low"levels of the external clocks must
each be stable for at least one system clock period plus the sum
T..... 1 Aagilter Selection
Opemi.....
A/W-"Low"
CR20 = ''0'' Write Control Regilter #3
CA20- "I" Write Control Regl.ter #1
Write Control Register #2
Write MSB Buffer Aegllter
Write Timer #1 Latch ..
Write MSB Buffer Reglloter
Write Timer #2 Latch ..
Write MSB Buffer Regllter
Write Timer #3 Latch ..
Afii- "High"
Ali bill "0"
Resd Stetu. Regilter
Aesd Timer #1 Counter
Aesd LIB Buffer Regllter
Resd Timer #2 Counter
Resd LIB Buffer Aagl.ter
Resd Timer #3 Counter
Aesd LIB Buffer Regllter
• L; "Low"leveI. H; "High" level
of the setup and hold times for the inputs. The asynchronous
clock rate can vary from dc to the limit imposed by Enable
(System til2 ) Setup, and Hold time.
The external clock inputs are clocked in by Enable (System
q,2) pulses. Three Enable periods are used to synchronize and
process the external clock. The fourth Enable pulse decrements
the internal counter. This does not affect the input frequency, It
merely creates a delay between a clock input transition and
internal !!cognltlon of that transition by the PTM. All references to C Inputs in this document relate to Internal recognition
of the Input transition. Note that a clock "High" or "Low" level
which does not meet setup and hold time specifications may
require an additional Enable pulse for recognition. When observing recurring events, a lack of synchronization will result in
'~Itter" being observed on the output of the PTM when using
asynchronous clocks and gate input signals. There are two types
of jitter. "System jitter" Is the result of the input signals being
out of synchronization with the Enable (System q,2), permitting
$
signals with marginal setup and hold time to be recognized by
either the bit time nearest the input transition or the subsequent
bit time.
"Input jitter" can be as great as the time between Input
signal negative going transitions plus the system jitter, if the
first transition is recognized during one system cycle, and not
recognized the next cycle, or vice versa_
External clock input C; represents a special case when TImer
#3 is programmed to utUize its optional +8 presca1er mode. The
maximum Input frequency and allowable duty cycles for this
case are specified under the AC Characteristics. The output of
the +8 presca1er is treated in the same manner as the previously
discussed clock inputs. That is, it is clocked into the counter by
Enable pulses, is recognized on the fourth Enable pulse
(provided setup and hold time requirements are met), and must
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
~~
-
~--~-----------
------ ----------
55
HD6340/HD6840--------------------------------------------------------produce an output pulse at least as wide as the sum of an Enable
period, setup, and hold times.
#.3. Thus, with all Register selects and R/W inputs at "Low"
level. Control Register #1 will be written into if CR20 is a logic
"I". Under the same conditions, control Register #.3 can also be
written into after a RES "Low" condition has occurred, since
all control register bits (except CRIO) are cleared. Therefore,
one may write in the sequence CR3, CR2, CRI.
En.ble~~
Input~r--
Recog~-- t-Input
Either
or Here
Here
---1
• CR10
I--
System
. . Bit Time
Output _ _ _ _ _ _ _ _ _ _ _....'~-n
J
Jitter
• Gate Inputs (~,G" G; I
Pin No. 26, 2, 5
Input
Input pins G., G2 , and G 3 accept asynchronous TTLcompatible signals which are used as triggers or clock gating
functions to Timers 1,2, and 3, respectively. The gating inputs
are clocked into the PTM by the Enable (System q,2) signal in
the same manner as the previously discussed clock inputs. That
is, a Gate transition is recognized by the PTM on the fourth
Enable pulse (provided setup and hold time requirements are
met), and the "High" or "Low" levels of the Gate input must be
stable for at least one system c1oc~period plus the sum of setup
and hold times. All references to G transition in this document
relate to internal recognition of the input transition.
The Gate inputs of all timers directly affected the internal
16-bit counter_ The operation of G; is therefore independent of
the +8 prescaler selection.
• Timer Outputs (0 1 , O2 , 0 3 1
Output
Pin No. 27, 3, 6
• CONTROL REGISTER
Each timer in the HD6340 has a corresponding write-only
Control Register. Control Register #2 has a unique address
space (RSO="High", RSI ="Low", RS2="Low") and therefore
may be written into at any time. The remaining Control
Registers (#1 and#.3) share the Address Space selected by a
"Low" level on all Register Select inputs.
CR20
The least-significant bit of Control Register #2 (CR20) is
used as an additional addressing bit for Control Registers #1 and
•
56
•
CR30
The least-significant bit of Control Register #3 is used as a
selector for a +8 prescaler which is available with Timer #3
only. The prescaler, if selected, is effectively placed between the
clock input circuitry and the input to Counter #.3. It can therefore be used with either the internal clock (Enable) or an external clock source.
• CRX1 - CRX7 (X=1-31
The functions depicted in the foregoing discussions are
tabulated in Table 2 for ease of reference.
Control Register Bits CRIO, CR20, and CR30 are unique in
that each selects a different function. The remaining bits (I
through 7) of each Control Register select common functions,
with a particular Control Register affecting only its corresponding timer.
• CRX1
Timer outputs 0 1 , O2 , and 0 3 are capable of driving up to
two TTL loads and produce a defined output waveform for
either Continuous or Single-Shot Timer modes. Output waveform defmition is accomplished by selecting either Single 16-bit
or Dual 8-bit operating modes. The single 16-bit mode will
produce a square-wave output in the continuous timer mode
and will produce a single pulse in the Single-Shot Timer mode.
The Dual 8-bit mode will produce a variable duty cycle pulse in
both the continuous and single shot Timer modes. "I" bit of
each Control Register (CRX7) is used to enable the corresponding output. If this bit is cleared, the output will remain
"Low" (Yo d regardless of the operating mode.
If it is cleared while the output is high the output will go low
during the first enable cycle following a write to the Control
Register.
The Continuous and Single-Shot Timer Modes are the only
ones for which output response is defmed in this data sheet.
Signals appear at the outputs (unless CRX7 = "0") during Frequency and Pulse Width comparison modes, but the actual
waveform is not predictable in typical applications.
•
The least-significant bit of Control Register #1 is used as an
internal Reset bit. When this bit is a logic "0", all timers are
allowed to operate in the modes prescribed by the remaining
bits of the control registers. Writing a "I" into CRIO causes all
counters to be preset with the contents of the corresponding
counter latches, all counter clocks to be disabled, and the timer
outputs and interrupt flags (Status Register) to be reset.
Counter Latches and Control Registers are undisturbed by an
Internal Reset and may be written into regardless of the state
ofCRIO.
Bit I of Control Register #1 (CRII) selects whether an internal or external clock source is to be used with Timer #1.
Similarly, CR21 selects the clock source for Timer #2, and
CR31 performs this function for Timer #.3. The function of
each bit of Control Register "X" can therefore be defined as
shown in the remaining section of Table 2.
• CRX2
Control Register Bit 2 selects whether the binary information
contained in the Counter Latches (and subsequently loaded into
the counter) is to be treated as a single 16-bit word or two 8-bit
bytes. In the single 16-bit Counter Mode (CRX2=0) the counter
will decrement to zero after N + I enabled (G="Low") clock
periods, where N is defmed as the 16-bit number in the Counter
Latches. With CRX2 = I, a similar Time Out will occur after (L
+ I)-(M + I) enabled clock periods, where Land M, respectively, refer to the LSB and MSB bytes in the Counter Latches.
• CRX3-CRX7
Control Register Bits 3, 4, and 5 are explained in detail in the
Timer Operating Mode section. Bit 6 is an interrupt mask bit
which will be explained more fully in conjunction with the
Status Register, and bit 7 is used to enable the corresponding
Timer Output. A summary of the control register programming
modes is shown in Table 3.
• STATUS REGISTER/INTERRUPT FLAGS
The PTM has an internal Read-Only Status Register which
contains four Interrupt Flags. (The remaining four bits of
the register are not used, and default to "O"s when being read.)
Bits 0, I, and 2 are assigned to Timers 1,2, and 3, respectively,
as individual flag bits, while Bit 7 is a Composite Interrupt Flag.
This flag bit will be asserted if any of the individual flag bits is
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (4081435-8300
------------------------------------------------------HD6340/HD6840
Tlble 2 Control Regi.ter Bit.
CR10
jlntarnal Reset Bit
CONTROL REGISTER #3
CONTROL REGISTER #2
CONTROL REGISTER #1
CR20
1Control Register Addr... Bit
CR30
I
Timer #3 Clock Control
"0" All timers allowed to operate
"0" CR #3 may be ",ntten
"0" T3 Clock is not presealed
"'" All timers held in preset state
"1" CR #1 may be written
"'" T3 Clock is presealed by
CRX1*
Timer #X Clock Source
"0"
TX uses external clock source on
"1"
TX uses Enable clock
CRX2
ex input
Timer #X Counting Mode Control
"0"
TX configured for normal (16-blt) counting mode
"1"
TX configured for dual 8-bit counting mode
CRX3 CRX4 CRX5
CRX6
Timer #X Counter Mode and Interrupt Control (See Table 3)
Timer #X Interrupt Enable
"0"
Interrupt Flag masked on IRQ
"1"
Interrupt Flag enabled to IRQ
CRX7
+8
Timer #X Counter Output Enable
"0"
TX Output masked on output OX
"1"
TX Output enabled on output OX
* Control Register for Timer 1, 2, or 3, Bit 1.
set while Bit 6 of the corresponding Control Register is at a
logic "1". The conditions for asserting the Composite Interrupt
Flag bit can therefore be expressed as:
INT = II ·CR16 + 12 ·CR26 + 13 ·CR36
where INT = Composite Interrupt Flag (Bit 7)
II = Timer #1 Interrupt Flag (Bit 0)
12 = Timer #2 Interrupt Flag (Bit 1)
13 = Timer #3 Interrupt Flag (Bit 2)
STATUS REGISTER
An interrupt flag is cleared by a Timer Reset condition, i.e.,
External RES = "Low" or Internal Reset Bit (CRIO) = "1". It
will also be cleared by a Read Timer Counter Command provided that the Status Register has previously been read while the
interrupt flag was set. This condition on the Read Status
Register - Read Timer Counter (RS-RT) sequence is designed
to prevent missing interrupts which might occur after the status
register is read, but prior to reading the Timer Counter.
An Individual Interrupt Flag is also cleared by a Write Timer
Latches (W) command or a Counter Initialization (CI) sequence, provided that W or CI affects the Timer corresponding to
the individual Interrupt Flag.
• COUNTER LATCH INITIALIZATION
Each of the three independent timers consists of a 16-bit
addressable counter and 16 bits of addressable latches. The
counters are preset to the binary numbers stored in the latches.
Counter initialization results in the transfer of the latch contents to the counter. See notes in Table 5 regarding the binary
number N, L, or M placed into the Latches and their relationship to the output waveforms and counter Time-Outs.
Since the PTM data bus is 8-bits wide and the counters are
I6-bits wide, a temporary register (MSB Buffer Register) is
provided. This "write only" register is for the Most Significant
Byte of the desired latch data. Three addresses are provided for
the MSB Buffer Register (as indicated in Table 1), but they all
lead to the same Buffer. Data from the MSB Buffer will automatically be transferred into the Most Significant Byte of Timer
#Xwhen a Write Timer #X Latches Command is performed. So
it can be seen that the PTM has been designed to allow transfer of two bytes of data into the counter latches provided that
the MSB is transferred first.
In many applications, the source of the data will be as
HMCS6800 MPU. It should be noted that the I6-bit store ojlerations of the HMCS6800 microprocessors (STS and STX etc.)
transfer data in the order required by the PTM. A Store Index
Register Instruction, for example, results in the MSB of the X
register being transferred to the selected address, then the LSB
of the X register being written into the next higher location.
Thus, either the index register or stack pointer may be transfered directly into a selected counter latch with a single instruction.
A logic "Low" at the RES input also initializes the counter
latches. In this case, all latches will assume a maximum count of
(65,536)10. It is important to note that an Internal Reset (Bit 0
of Control Register 1 Set) has no effect on the counter latches.
• COUNTER INITIALIZATION
Counter Initialization is defined as the transfer of data from
the latches to the counter with subsequent clearing of the Individual Interrupt Flag associated with the counter. Counter
Initialization always occurs when a reset condition (RES =
"Low" or CRIO = "1 ") is recognized. It can also occur depending on Timer Mode with a Write Timer Latches command or recognition of a negative transition of the Gate input.
Counter recycling or re-initialization occurs when a negative
transition of the clock input is recognized after the counter has
reached an all-zero state. In this case, data is transferred from
the Latches to the Counter.
• TIMER OPERATING MODES
The PTM has been designed to operate effectively in a
wide variety of applications. This is accomplished by using three
bits of each control register (CRX3, CRX4, and CRX5) to
.HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
57
HD6340/HD6840--------------------------------------------------------• WAVE SYNTHESIS MODES
defined different operating modes of the Timers. These modes
are divided into Wave Synthesis and Wave Measurement modes,
and outlined in Table 3.
•
The continuous mode will synthesize a continuous wave with
a period proportional to the preset number in the particular
timer latches.
Any of the timers in the PTM may be programmed to
operate in a continuous mode by writing "O"s into bits 3 and 5
of the corresponding control register. Assuming that the timer
output is enabled (CRX7 = "1 "), either a square wave or a variable duty cycle waveform will be generated at the Timer
Output, OX. The type of output is selected via Control Register
Bit 2.
Either a Timer Reset (CRIO = "1" or External RES =
"low") condition or internal recognition of a negative transition of the Gate input results in Counter Initialization. A Write
Timer Latches command can be selected as a Counter Initialization signal by clearing CRX4.
The counter is enabled by an absence of a Timer Reset condition and a "Low" level at the Gate input. In the l6-bit mode,
the counter will decrement on the first clock cycle during or
after the counter initialization cycle. It continues to decrement
on each clock signal so long as G remains "Low" and no reset
condition exists. A Counter Time Out· (the first clock after all
Table 3 Operating Mode.
Control Register
CRX3
0
0
1
1
*
CRX4
CRX5
Timer Operating Mode
"
"
0
1
Continuous
.
Frequency Comparison
0
1
..
Wave
SynthesIs
Slngle·Shot
"
Pulse Width Comparison
Continuous Operating Mode (Table 4)
Wave
Measurement
Defmes Additional Timer Functions .
One of the WAVE SYNTHESIS modes is the Continuous
Operating mode, which is useful for cyclic wave generation.
Either symmetrical or variable duty·cycle waves can be gen·
erated in this mode. The other wave synthesis mode, the SingleShot mode, is similar in use to the Continuous operating mode,
however, a single pulse is generated, with a programmable preset
width.
The WAVE MEASUREMENT modes include the Frequency
Comparison and Pulse Width Comparison modes which are used
to measure cyclic and singular pulse widths, respectively.
In addition to the four timer modes in Table 3, the remaining
control register bit is used to modify counter initialization and
enabling or interrupt conditions.
Table 4 Continuous Operating Modes
CONTINUOUS MODE
(CRX3 = "0", CRX5 = "0")
Control Register
CRX2
Counter Initialization
0
GI+W+R
0
1
GI+R
1
0
GI+W+R
1
1
GI+R
0
G~
Initialization/Output Waveforms
CRX4
"Timer Output (OX) (CRX7
r-(N+l)(T1 T!N+1)(T)T(N+1)( TI
II
I
I
t,
TO
TO
= "''')
1
I-VOH
I
f--IL+lI1M+lIITI~IL+lI1M+lIITI--i
-
VOL
TO
v
~-OH
I
t,
---1
ILiITI
I-TO
--l
ILIITI
r--
TO
"" Negative transition of Gate input.
W = Write Timer Latches Command.
R
= Timer Reset
(CR10
= "I" or External
RES
= "Low")
N = 16-Bit Number in Counter Latch.
L
=
a-Bit Number in LSB Counter Latch.
M
=
a-Bit Number in MSB Counter Latch.
T = Clock Input Negative Transitions to Counter.
t, = Counter Initialization Cycle.
TO= Counter Time Out (All Zero Condition).
* All time intervals shown above assume the Gate (0) and Clock (C) Signals are synchrOnized to Enable
(System CPt) with the specified setup and hold time requirements.
~HITACHI
58
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------------HD6340/HD6840
Control Register Bits
Timer #X Counter Output Enable
TX Output masked on output OX
CRX7
0
1
TX Output enabled on output OX
CRX6
0
1
Timer #X Interrupt Enable
Interrupt Flag masked on IRQ
Interrupt Flag enabled to IRQ
.\ '7~~~' I T,~." ~"....", H".".ru,"""."'" T~'" I
Control Register X
17
6 15 14 1 3
21 1 1 0 LX=1,2or3
::::::-.
/
Timer #x Counting Mode Control
CRX2
0
1
TX configured for normal (16·blt) counting mode
TX configured for dual 8-bit counting mode
CRX1
0
1
0
1
CR 10 loternal Reset Bit
All timers allowed to operate
All timers held In preset state
X
=1
Timer #x Clock Source
TX uses external clock sou ree on
TX uses Enable clock
ex mput
CR20 Control Register Address Bit
0 CR#3 may be written
1 CR#1 may be written
CR30 Timer #3 Clock Control
0 T3 Clock IS not prescaled
1 T3 Clock IS prescaled by + 8
X=2
X =3
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
59
HD6340/HD6840--------------------------------------------------_______
Example: Contents of MSB = 03 = M
Contents of LSB = 04 = L
r.--------------------
M(L+1)+1
Algebraic Expression
03(04 + 1) + 1
16 Enables
,,
,
=
,
----_0-- 1 + L
1+L
5 Enable
Pulses
,
----t~...,:...I - - -
1+L ~
5 Enable
Pulses
,
J+--+---------!--+:------I• ,
,
:
(M
+ i)
0:' + 1)
------'--1----------01
.--
j~l
I
I
,i
**
I
r---+'
t
I:
--'
I
**
* 1
I
Algebraic ExpreSSion
(04 + 1) (03 + 1)
=20 Enable or
External Clock Pulses
(M + 1) (L + 1) = Period
M(L + 1) + 1 = "Low" portion of period
L = Pu Ise width
* Preset LSB and MSB to Respective Latches on the negative transition of the E.
** Preset LSB to LSB Latches and Decrement MSB by one on the negative transition of the E.
Figure 9 Timer Output Waveform Example
(Continuous Dual 8-Bit Mode using Internal Enable)
counter bits = "0") results in the Individual Interrupt Flag being
set and re-initialization of the counter.
In the dual 8-bit mode (CRX2= "1") [Refer to the example
in Fig. 9] the MSB decrements once for every full countdown
of the LSB + 1. When the LSB = "0", the MSB is unchanged; on
the next clock pulse the LSB is reset to the count in the LSB
Latches and the MSB is decremented by I (one). The output, if
enabled, remains "Low" during and after initialization and will
remain "Low" until the counter MSB is all "O"s. The output
will go "High" at the beginning of the next clock pulse. The
output remains "High" until both the LSB and MSB of the
counter are all "O"s. At the beginning of the next clock pulse
the defmed Time Out (TO) will occur and the output will go
"Low". In the Dual8-bit mode the period of the output of the
example in Fig. 9 would span 20 clock pulses as opposed to
the 1546 clock pulses using the Normal 16-bit mode.
A special time-out condition exists for the dual 8·bit mode
(CRX2 = "1") if L ="0". In this case, the counter will revert to
a mode similar to the siRgie 16-bit mode, except Time Out
occurs after M+ 1 clock pulses. The output, if enabled, goes
"Low" during the Counter Initialization cycle and reverses state
at each Time Out. The counter remains cyclical (is re-initialized
at each Time Out) and the Individual Interrupt Flag is set when
Time Out occurs. If M = L = "0", the internal counters do not
change, but the output toggles at a rate of 1/2 the clock frequency.
The discussion of the Continuous Mode has assumed that the
application requires an output signal. It should be noted that
the Timer operates in the same manner with the output disabled
(CRX7 = "0"). A Read Timer Counter command is valid regardless of the state of CRX7.
•
Single-Shot Timer Mode
This mode is identical to the Continuous Mode with three
exceptions. The first of these is obvious from the name - the
output returns to a "Low" level after the initial Time Out and
remains "Low" until another Counter Initialization cycle
occurs. The waveforms available are shown in Table 5.
As indicated in Table 5, the internal counting mechanism
remains cyclical in the Single-Shot Mode. Each Time Out of the
counter results in the setting of an Individual Interrupt Flag and
re-initialization of the counter.
The second major difference between the Single-Shot and
Continuous modes is that the internal counter enable is not
dependent on the Gate input level remaining in the "Low" state
for the Single-Shot mode.
Another special condition is introduced in the Single-Shot
mode. If L =M ="O"(Dual 8-bit) or N ="0" (Single 16-bit), the
output goes "Low" on the fIrst clock received during or after
Counter Initialization. The output remains "Low" until the
Operating Mode is changed or nonzero data is written into the
Counter Latches. Time Outs continue to occur at the end of
each clock period.
The three differences between Single-Shot and Continuous
Timer Modes can be summarized as attributes of the Single-Shot
~HITACHI
60
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------HD6340/HD6840
mode:
1. Output is enabled for only one pulse until it is reinitia1ized.
2. Counter Enable is independent of Gate.
3. L =M ="0" or N ="0" disables output.
Aside from these differences, the two modes are identical.
Tabla 5 Slngla·Shot Operating Modes
Slngle·Shot Mode
(CRX3 = "0", CRX7 = ",", CRX5· ",")
Control Register
Initialization/Output Waveforms
CRX2
CRX4
Counter Initialization
0
0
GI+W+R
0
I
GI+R
I
0
GI+W+R
1
1
GI+R
Symbols are as defined
In
h
Tim.. Output (OX)
(N+l )(T) ;=::r-(N+1 )(T)1
i--CN)(T)
~
I
to
TO
TO
rCL+l)(M+l)(T)~L+1)(M+l )(T)l
--j(L)(T)
I ITO
t.
TO
Table 5
• WAVE MEASUREMENT MODES
The Wave Measurement Modes are the Frequency (period)
Measurement and Pulse Width Comparison Modes, and are provided for those applications which require more flexibility of
interrupt generation and Counter Initia1ization. Individual interrupt Flags are set in these modes as a function of both Counter
Tune Out and transitions of the Gate input. Counter Initia1ization is also affected by Interrupt Flag status.
A timer's output is normally not used in a Wave Measurement mode, but it is defmed. If the output is enabled, it will
operate as follows. During the period between reinitia1ization of
the timer and the first Time Out, the output will be a logical
zero. If the frrst Time Out is completed (regardless of its
method of generation), the output will go "High". If further
TO's occur, the output will change state at each completion of a
Time-Out.
The counter does operate in either Single 16-bit or Dual 8-bit
modes as programmed by CRX2. Other features of the Wave
Measurement Modes are outlined in Table 6.
TIbia 5 Wave Measurement Modes
CRX3 = ,.,,.
CRX4
0
CRX5
0
Appli_ion
Frequency Comparison
Condition for Setting Individullinterrupt Flog
Interrupt Generated if Gate Input Period (1/F) is less
than Counter Time Out (TO)
0
1
Frequency. Comparison
1
0
Pulse Width Comparison
Interrupt Generated if Gate Input Period ('/F) is groater
than Counter Time Out (TO)
Interrupt Generated if Gate Input "Down Time" is less
than Counter Time Out (TO)
1
1
Pulse Width Comparison
Interrupt Generated if G8ti Input "Down Time" is greater
than Counter Time Out (TO)
• Frequencv Comparison or Period Measurement Mode ICRX3
= "1", CRX4 = "0")
The Frequency Comparison Mode with CRXS = "I" is
straightforward; If Time Out occurs prior to the fust nega!ive
transition of the Gate input after a Counter Initia1ization cycle,
an Individual Interrupt Flag is set, The counter is disabled, and a
Counter Initia1izatkm cycle cannot be~ until the interrupt flag
is cleared and a negative transition on G is detected.
If CRX 5 = "0", as shown in Table 6 and Table 7, an interrupt is generated if Gate input returns "Low" prior to a Time
Out. If Counter Time-Out occurs fust, the counter is recycled
and continues to decrement, A bit is set within the timer on the
initial Time Out which precludes further individual interrupt
generation until a new Counter Initia1ization cycle has been
completed. When this internal bit is set, a negative transition of
the Giiie input starts a new Counter Initialization cycle. (The
•
condition of (;'/"I'TO is satisfied, since a Time Out has occurred and no individual Interrupt has been generated.)
Any of the timers within the PTM may be programmed to
compare the period of a pulse (giving the frequency after calculations) at the Gate input with the time period re~ted for
Counter Tinte-Out. A negative transition of the Girte input
enables the counter and starts a Counter Initia1ization cycle provided that other conditions as noted in Table 7 are satisfied.
The counter decrements on each clock signal recogni2ed during
or after Counter Initialization until an Interrupt is generated, a
Write Timer Latches command is issued, or a Timer Reset condition occurs. It can be seen from Table 7 that an interrupt
condition will be generated if CRX 5 =''0'' and the period of the
pulse (single pulse or measured separately repetitive pulses) at
the Gate input is less than the Counter Time Out period. If
CRX 5 ="I" , an interrupt is generated If the reverse is true.
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
61
HD6340/HD6840----------------------------------------------------------Assume now with CRX 5 = "1" that a Counter lnitialization
has occurred and that the Gate input has returned "Low" prior
to Counter Time Out. Since there is no Individual Interrupt
Flag generated, this automatically starts a new Counter Initialization Cycle_ The process will continue with frequency comparison being performed on each Gate input cycle until the
mode is changed, or a cycle is determined to be above the
predetermined limit.
• Pulse Width Comparison Mode (CRX3 = "1", CRX4 ="1"1
This mode is similar to the Frequency Comparison Mode
except for a positive, rather than negative, transition of the Gate
input terminates the count. With CRX5 = "0", an Individual
lnterrupt Flag will be generated if the "Low" level pulse applied
to the Gate input is less than the time period required for
Counter Time Out. With CRX 5 = "1" , the interrupt is generated
when the reverse condition is true.
As can be seen in Table 8, a positive transition of the Gate
input disables the counter. With CRX5 = "0", it is therefore
possible to directly obtain the width of any pulse causing an
interrupt. Similar data for other Time Interval Modes and
conditions can be obtained, if two sections of the PTM are
dedicated to the purpose.
Table 7 Frequency Comparison Mode
CRX3
=",",
CRX4 =''0''
Control Reg
Bit 5ICRX5)
Counter
Counter Enable
Counter Enable
Initialization
Flip-Flop Sot ICE I
Flip-Flop Roset ICEI
Sot III
0
G.' HCE+TOI+R
G.-w·R·1
W+R+I
GI Before TO
1
GI'I+R
GI'W'R-I
W+R+I
TO Before G.
Interrupt Flag
I represents the interrupt for a given timer.
Table 8 Pulse Width Comparison Mode
CRX3 = ",", CRX4 = "'"
Control Reg
Bit 51CRX51
Initialization
Counter Enable
Flip-Flop Sot ICEI
Flip-Flop Resot ICEI
Interrupt F leg
Sot III
0
G.-I+R
G.-w-R-T
W+R+I+G
Gt Before TO
1
G.'I+R
m-W-R-I
W+R+I+G
TO Before Gt
Counter
Counter Enable
G = Level senSitive recognition of -Gate input.
~HITACHI
62
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
_________________________________________________________ HD6340/HD6840
Table 9 Control Register Programming
Register 1
Register 2
Register 3
All Tomers Operate
Reg #3 May Be Written
T3 Clk'" 1
All Timers Preset
Reg #1 May Be Written
T3 elk -;- 8
External Clock
(CX
Input)
Internal Clock (Enable)
Normal (IS-Bit) Count Mode
Dual 8-Bot Count Mode
Continuous Operating Mode: Gate J. or Write to Latches or Reset Causes Counter Initialization
Ln
Frequency Companson Mode: Interrupt if Gate
IS
< Counter Time
Out
Continuous Operating Mode: Gate .j, or Reset Causes Counter Initialization
Pulse Width Comparison Mode: Interrupt if Gate
L--.J is < Counter Time Out
Single Shot Mode: Gate.£. or Write to Latches or Reset Causes Counter Initialization
Frequency Companson Mode: Interrupt If Gate
Smgle Shot Mode: Gate
.j,
lS+IS > Counter Time Out
or Reset Causes Counter Initialization
Pulse Width Companson Mode: Interrupt If Gate
L---l is> Counter Time Out
Interrupt Flag Masked (lAO)
Interrupt F lag Enabled (I Ra)
Timer Output Masked
Timer Output Enable
(NOTE) Reset
IS
Hardware or Software Reset (RES'" "Low" or CR10 = "1 ").
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
63
HD6340/HD6840-------------------------------------------------------NOTE FOR USE (HD6340 only)
Input signal, which is not necessary for user's application,
should be used ftxed to "High" or "Low" level. This is applicable to the following signal pins.
•
~ C2 , C3 , C;-, G2 , G3
• Notes for the 0 1 - 0 3 Outputs Noise
(1) Phenomenon
When the excessive load capacitance is connected to data
bus and GND wiring impedance is not neglectable in the system
using HD6340, the noise appears in 0 1 - 0 3 outpus in the read
cycle as indicated in Fig. 10 which may cause the erroneous
operation of the system .
• RESTRICTION FOR USE
\'-___--1
E
AS
CS
\'------1
__________ ______________
x~
~x~
_____
A/W
___ _________________ _______________
~x~
Figure 10 The 0 1
x~
-
0 3 Outputs Noise in the MPU Read Cycle
(2) Cause
When the data buffer turns from "H" to "L", the excessive
transient current runs to the GND (the discharge current of the
data bus load capacity). Therefore, the noise occurs in the GND
pin of the LSI because of the impedance of the GND wiring
(resistance and inductance). See Fig. II for the details.
Fig. 12 indicates the dependence of the noise voltage upon
each parameter.
0,
D.
I H~~
_ _ _..J
Figure 11 Cause of the Noise
Vn
Vn
Vee
Cd
Z9
N
Vn: Noise voltage
Zg: GND impedance
Cd: Data bus load capacitance
N : Number of data bus which changes
according to H -+ L.
Figure 12 The Dependence of the Noise Voltage upon Each Parameter
~HITACHI
64
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------HD6340/HD6840
However, it is important to consider the fact that the noise voltage
varies according to the type of parameter as indicated in Fig. 12.
(3) Countermeasures
When the noise cause the erroneous operation of the system, the
coWUermeasures to be taken are as follows.
(a) Latch the 0, -030utputs by the falling edge of the signal "E".
6303
~~o, 1-_-+l~1741-___
E --+--E_v
elK
1....--
The latch added to prevent
the noisa (74lS174).
• Precautions when using Timer 3 IHD6340 only)
When using the HD63B40P Timer 3 under the conditions
1) external clock mode (CR3l = 0)
2) ->- 8 prescaler unused (CR30 = 0)
and changing the bits of the control register #3 except for the
CR30 bit (e.g. in a case where the interrupt mask bit and 0 3
output enable bit are changed and the CR30 is not), there is
the possibility that one decrement clock may be omitted .
•
This phenomenon occurs when tosw (data setup time;
standard spec. 60ns minimum) is less than 8Ons, and does not
occur when tosw is greater than 8Ons.
Therefore, please avoid to use the HD63B40P in the above
status when tosw is less than 80ns.
(This phenomenon doesn't occur in the HD6340P and
HD63A40P.)
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
65
HD6844, HD68A44,
HD68B44
DMAC (Direct Memory Access
The HD6844 Direct Memory Access Controller (DMAC)
performs the function of transferring data directly between
memory and peripheral device controllers. It controls the
address and data buses in place of the MPU in bus organized
systems such as the HMCS6800 Microprocessor System.
The bus interface of the H06844 includes select, read/
write, interrupt, transfer request/grant, and bus interface logic
to allow the data ti'.lnsfer over an 8-bit bidirectional data bus.
The functional configuration of the DMAC is programmed via
the data bus. The internal structure provides for control and
handling of four individual channels, each of which is separately
configured. Programmable control registers provide control for
the transfer location and length, individual channel control and
transfer mode configuration, priority of servicing, data chaining,
and interrupt control. Status and control lines provide control
to the peripheral controllers.
The mode of transfer for each channel can be programmed as
cycle-stealing or a burst transfer mode.
Typical applications would be with the Floppy Disk Controller (FDC), etc ..
Controller)
HD6844P, HD68A44P, HD68B44P
(DP-40)
• PIN ARRANGEMENT
o
q,2 DMA
REs
DGRNT
i5RQT
i5RQH
•
•
FEATURES
Four DMA Channels, Each Having a 16-Bit Address
Register and a 16-Bit Byte Count Register
• 1 M Byte/Sec (HD6844), 1.5 M Byte/Sec (HD68A44),
2.0 M 8yte/Sec (HD68844)
Maximum Data Transfer Rate
TxAKA
TxSTa
iRO/O'EN'O
TxAo"
HD6844
TxRQ 2
• Selection of Fixed or Rotating Priority Service Control
• Separate Control Bits for Each Channel
•
•
•
TxAQ~
D,
D,
D,
Data Chain Function
Address Increment or Decrement Update
Programmable Interrupts and DMA End to Peripheral
Controllers
D.
D,
• Compatible with MC6844, MC68A44, MC68B44
• BLO(,( DIAGRAM
(Top View)
Address/Control and Interrupt
Data
Bus
Channel
Request
Grant
Control
Four
Channel
Controls
~HITACHI
66
TxRQ 1
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------HD6844,HD68A44,HD68B44
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Vee *
-0.3-+7.0
Unit
V
Operating Temperature
Vi" *
Top,
-0.3-+7.0
-20 -+75
V
°c
Storage Temperature
TS1Il
-55-+150
°c
Supply Voltage
Input Voltage
• With respect to Vss (SYSTEM GND)
(NOTE)
Permanent LSI damage may occur If maximum ratings are exceeded. Normal operation should be
under recommended operating conditions. If these conditions are exceeded, It could affect
reloeb,loty of LSI.
• RECOMMENDED OPERATING CONDITIONS
...
Item
Symbol
min
Power Supply Voltage
Vee
V 1L
V IH
4.75
typ
5.0
-0.3
-
2.0
-
Top,
-20
25
Input Voltage
Operating Temperature
max
Unit
5.25
0.8
V
V
Vee
75
V
°c
• W,th respect to Vss (SYSTEM GND)
• ELECTRICAL CHARACTERISTICS (Vcc·5V±5%, Vss-oV, Ta~-2o-+75°C, unl_ otherwise noted.)
• DC CHARACTERISTICS
max
Unit
V IH
min
2.0
typo
Input "High" Voltage
-
V
Input "Low" Voltage
V 1L
-0.3
-
Vee
0.8
2.5
p.A
10
p.A
Item
Symbol
Test Condition
Input Leakage Current
TxRClo-3,9>2 DMA,
RES, DGRNT
lin
V;n=o-5.25V
-2.5
Three·State (off state)
Leakage Current
Ao-A 15 , Do-D 7, R/W
I TS1
Vln =0.4-2.4V
-10
Do-D 7
A o-A 15 , R/W
All Other Outputs
IOH=-205p.A
2.4
-
-
Output "High" Voltage
V OH
IOH--145p.A
IOH=-l00p.A
2.4
-
-
Output "Low" Voltage
Source Current
VOL
CS/TxAKB
Power D issipatio n
Input Capacitance
Output Capacitance
9>2 DMA
Do..::D7' CS, Ao-~,
R/W
TxRQo-3, RES,
DGRNT
less
Po
Vln=OV, T.=25°C
f=1.0MHz
Cln
Cout
•
IOL=1.6mA
Fig. 10
V;n~V,
V;n=OV, T.=25°C, f=lMHz
2.4
-
500
-
-
-
-
-
10
V
V
0.4
V
16
1000
20
rnA
12.5
mW
pF
10
12
pF
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
~~~---------
67
HD6844,HD68A44,HD68B44-------------------------------------------------• AC CHARACTERISTICS (Load Condition Fig. 9)
1. CLOCK TIMING
Item
Symbol
HD6644
Test
Condition
min
HD66A44
typ
mex
min
typ
I/>,DMA Cycle Tima
teyel/>
Fig.2
1000
666
-
PWI/>H
Fig. 2
450
-
-
1/>, DMA Pulse Width ["High" Level
-
280
-
Level
PWI/>~
Fig. 2
400
-
-
230
-
tq,r,tq,f
Fig. 2
-
-
25
I "Low"
1/>, DMA Rise end Fall Tima
HD68844
mex
min
-
500
-
235
210
25
tYP
max
-
-
Unit
ns
ns
-
n.
25
n.
2. DMA TIMING (Load Condition Fig. 9)
Item
Symbol
min
tYP
max
min
tYP
max
120
-
-
120
-
-
120
-
-
210
-
-
210
-
-
155
-
-
tTOHl
20
-
-
10
-
-
-
20
-
-
10
-
10
125
-
10
-
n.
10
-
-
-
-
10
I/>,DMA Falling
tTOH2
Edge
-
-
180
-
-
160
ns
Edge
tTasl
Edge
DGRNT Setup Time
DGRNT
tOGS
DGRNT Hold Time
DGRNT
tOGH
Addre.. Output
Deley Time
A.-A", R/W,
tAD
TxSTB
Addre.. Output
Hold Time
TxSTB
Addre .. Th ree.state
Delay Time
Addre.. Three·State
Recovery Time
ns
Fig.3
Fig. 4
155
10
Fig.6
-
Fig.6
Fig.7
30
A.-A",R/iii tATSO
Fig. 7
-
A.-A", R/iii
Fig. 7
Fig.5
-
tTKO'
Fig. 5
-
DGRNT Rising
tTK02
Edge
Fig. 8
A.-A", RIW
tAHO
tATSR
DROH,DRQT toaD
1/>, DMA Rising
TxAK Delay Time
Unit
max
1/>, DMA R isi ng
Delay Time
HD68844
typ
I/>,DMA Falling
tTas2
Edge
TxRO Hold Time
HD68A44
min
1/>, DMA Ri.ing
TxRO Setup Time
HD6844
Test
Condition
Edge
-
ns
115
-
270
-
-
20
-
-
20
-
-
35
-
-
-
-
ns
35
-
270
-
-
270
n.
-
270
-
-
270
ns
250
-
-
210
ns
250
-
270
-
270
-
-
375
-
-
-
400
-
-
3'0
-
-
-
-
190
.-
-
160
-
210
125
35
ns
I RO/i5EriiD Delay
Edge
tOED'
Fig.6
-
-
300
-
-
250
-
-
Time
DGRNT Rising
'OE02
Edge
Fig.8
-
-
190
-
-
160
-
-
1/>, DMA Falling
150
n.
3. BUS TIMING
1) READ TIMING
Item
Addre.. Setup Time
Address Input Hold
Time
Symbol
A.-A.,RIW,
CS
~-A.,R/W,
CS
HD6844
Test
Condition
tAS
tAHI
HD68B44
max
min
typ
max
min
tYP
max
140
-
-
140
-
-
70
-
-
ns
10
-
-
-
320
460
-
°,-
01
tOOR
Date Acce.. Time
0 0 -0"
tACC
-
-
Data Output Hold
Time
0 0 -0.,
tOHR
10
-
10
-
-
10
-
-
ns
-
-
220
-
-
180
ns
-
360
-
-
280
ns
10
-
-
10
-
-
ns
~HITACHI
68
Unit
tYP
Data Delay Time
Fig. 2
HD68A44
min
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
-------------------------HD6844,HD68A44,HD68B44
21 WRITE TIMING
Item
Address Se.up Tome
Address Inpu. Hold
Time
Da.a Setup Tome
Da •• Inpu. Hold
Time
Svmbol
HD6844
Test
Condition
~-A.,RIW,
'AS
CS
A,-A., RIW,
CS
°0- 0 7
°0- 0 7
'AHI
Fog. 2
HD68A44
HD68B44
Unit
min
'Vp
max
min
tvP
max
min
'VP
max
140
-
-
140
-
-
70
-
-
ns
10
-
-
10
-
-
10
-
-
ns
·OSW
195
-
-
80
-
-
60
-
-
ns
'OHW
10
-
-
10
-
-
10
-
-
ns
IRQ/
CS/TxAK8
DRQT
--_+----i
~----~r---~
_______
_
#0 H ..1I _______
L
DRQ
#I
H/T
H:
L
-#2-"H- -~---i:- ---
~----+--~.'~~--,
-ii-H--~---C---
BYTE COI.WT REGISTER
(18X4)
"DMA----~------------_1
1_--------TxAQ
T.~ 1---------TxRQ,
M~IN
~.AKI---------TxAQ
I_------T._
CONTROL
TxSTB
t..;;.IDICOr-- T.AKA
ROVce-
v •• ~
Figure 1 Expanded Block Diagram
$
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
69
HD6844,HD68A44,HD68B44------------------------------------------------f------------
toyo
---------1
.DMA
A.=.A, \Input)
R1W(lnput)
CS (Input)
D. -0, (Output)
(Read Operation)
0.-0, (Input)
(Write Operation)
Figure 2 ReadlWrite Sequence
Figure 3 Timing of TxRQ Input
•
70
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
------------------------HD6844,HD68A44,HD68B44
Set Up Timing
~
IP,DMA
~2.0V
tD~-1
__________
,.,.,....----- ----- ----
2.0V
DGRNT
O.BV
Hold Timing
IP,DMA
DGRNT
Figure 4 Timing of DGRNT Input
2.0V
IP,DMA
2.4V
O.4V
2.4V
TxAKA
CS/TxAKB (Output)
O.4V
Figure 5 Timing of DROH, DROT, TxAK Outputs
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
71
HD6844,HD68A44,HD68B44-------------------------
,DMA
2.4V
A.:::..A,. (Output!
R1W (Output)
"i'XSTB
O.4V
tOE Ox'
2.4V
O.4V
------------~
------------------
Figure 6 Timing of Address and I RQ/DEND Outputs
Recovery Time of Address Three-state
,DMA (or DGRNT)
2.4V
O.4V
Delay Time of Address Three-state
, DMA (or DGRNT)
tAHO
Figure 7 Timing of Address Three-state
•
72
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
------------------------HD6844.HD68A44.HD68B44
DGRNT
CS/T.AKB IOutput)
O.4V
'""'1
/1
-IRQ/DEND
2 4V
.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
Figure 8 Timing of Synchronous OGRNT Output
5.0V
2.4kO
Test terminal
0 0 -0,
Ao-A 15 • R/W
CS/TxAKB
All other outputs
Test terminal o--......,--~--filI---+
R
C
0,
0,
C
130 pF
90 pF
50 pF
30 pF
R
11 kn
16kn
24kn
24kn
0, -0, : 152074 <8l or equivalant.
0,
Figure 9 Load Circuit
,-- -- --- - -- --- ---------------,
I
I
I
I
HD6844
Vee
I
0'
TxAKB output
>---::]X)-l------ll
~
less
~
OFF
D.C. Ammeter
Vln-OV
Vss
T.AK ENABLE
I
VSS
CS input
~-------------------------~
Figure 10 Source Current Measurement Circuit for CSlTxAKB Terminal
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose. CA 95131 • (408) 435-8300
73
HD6844,HD68A44,HD68B44--------------------------------------_____________
• DEVICE OPERATION
The DMAC has fifteen addressable registers, eight of them
are sixteen bits in length, Each channel has a separate Address
Register and a Byte Count Register, each of which is sixteen
bits, There are also four Channel Control Registers, The three
General Control Registers common to all four channels are the
Priority Control Register, the Interrupt Control Register, and
the Data Chain Register,
To prepare a channel for DMA, the Address Registers must
be loaded with the starting memory address and the Byte Count
Register loaded with the number of bytes to be transferred, The
bits in the Channel Control Register establish the direction of
the transfer, the mode, and the address increment or decrement
after each cycle, Each channel can be set for one of three
transfer modes: Three-State Control (TSC) Steal, Halt Steal, or
Halt Burst Two read-only status bits in the Channel Control
Register indicate when the channel is busy transferring data and
when the DMA transfer is completed,
The Priority Control Register enables the transfer requests
from the peripheral controllers and establishes either a fixed
priority or rotating priority scheme of servicing these requests.
When the DMA transfer for a channel is complete (the Byte
Count Register is zero), a DMA End signal is directed to the
peripheral controller and an IRQ goes to the MPU. Enabling of
these interrupts is done in the interrupt Control Register, The
IRQ flag bit is read from tWs register.
Chaining of data transfers is controlled by the Data Chain
Register, When enabled, the contents of the Address and Byte
Count Registers for channel #3 are put into the registers of the
channel selected for chaining when its Byte Count Register
becomes zero. This allows for repetitively reading or writing a
block of memory.
During the DMA mode, the DMAC controls the address bus
and data bus for the system as well as providing the R/W
line and a signal to be used as VMA. When a peripheral
device controller desires a DMA transfer, it is requested by a
Transfer Request Assuming this request is enabled and meets
the test of highest priority, the DMAC will issue a DMA
Request When the DMAC receives the DMA Grant, it gives a
Transfer Acknowledge to the peripheral device controller, at
wWch time the data is transferred. When the channel's Byte
Count Register equals zero, the transfer is complete and a DMA
"ElliI is given to the peripheral device controller, and an IRQ is
given to the MPU.
• Initialization
During a power-on sequence, the DMAC is reset via the RES
input. All registers, with the exception of the Address and Byte
Count Registers, are- set to a logic "0" state. This disables all
requests and the Data Chain function while masking all
interrupts. The Address, Byte Count, and Channel Control
Registers must be programmed before the respective transfer
request bit is enabled in the Priority Control Register.
• Transfer Modes
There are three ways in wWch a DMA transfer may be done.
The one used is determined by the data transfer rate required,
the number of channels attached, and the hardware complexity
allowable. Refer to Figures 12, 16 and 17.
Two of the modes, TSC Steal and Halt Steal, are done by
cycle-stealing from the MPU. The Three-State Control (TSC)
Steal mode is initiated by the DMAC bringing the DRQT line
"Low". TWs line goes to the system clock driver wWch returns a
"High" on DGRNT on the rising edge of the system q" clock.
•
74
The DGRNT signal must cause the address control and data
lines to go to the Wgh impedance state. The DMAC now
supplies the address from the Address Register of the channel
requesting. It also supplies the R/W signal as determined from
the Channel Control Register, After one byte is transferred,
control is returned to the MPU. TWs method stretches the q"
and q,2 clocks while the DMAC uses the memory.
The second method of cycle-stealing is the Halt Steal mode.
TWs method actually halts the MPU instead of stretching the q"
clock for the transfer period. TWs mode is initiated by the
DMAC bringing the DRQH line "Low". TWs line connects to
the MPU HALT input. The MPU Bus Available (BA) line is the
DGRNT input to the DMAC. While the MPU is halted, its
Address Bus, Data Bus, and R/W are in the high impedance
state. The DMAC now supplies the address and R/W line. After
one byte is transferred, the HALT line is returned "High" and
the MPU regains control. In this mode, the MPU stops internal
activity and is removed from the system while the DMAC uses
the memory.
The third mode of transfer is the Halt Burst mode. TWs
mode is similar to the Halt Steal mode, except that the transfer
does not stop with one byte. The MPU is halted while an entire
block of data is transferred. When the channel's Byte Count
Register equals zero, the transfer is complete and control is
returned to the MPU. This mode gives the highest data transfer
rate, at the expense of the MPU being inactive during the
transfer period.
• INPUT/OUTPUT FUNCTIONS
• DMAC Interface Signals for the MPU
The DMAC interfaces with the HMCS6800 MPU through the
eight-bit bidirectional data bus, the CS line, five address lines,
an IRQ line, the Read/Write line, and the RES line. These signals, in conjunction with the HMCS6800 VMA output, permit
the MPU to have access to the DMAC. Four other lines associated with the MPU and the clock driver are the DRQT,
DRQH, DGRNT, and the q,2 DMA.
Bidirectional Data (Do ~D7)
The Bidirectional Data lines (Do ~D7) allow for data transfer
between the DMAC and the MPU. The data bus output drivers
are three-state devices that remain in the high impedance state
except when the MPU performs DMAC read operations.
Chip SelectlTransfer Acknowledge B (CSIT x AKB)
TWs line is multiplexed, serving both as an input and an
output. CS/TxAKB is an output in the four-channel mode
during the DMA transfer. At all other times, it is a high
impedance TTL compatible input used to address the DMAC.
The DMAC is selected when CS/TxAKB is "Low". VMA must
be used in generating this input to insure that false selects will
not occur, Transfers of data to and from the DMAC are then
performed under the control of the q,2 DMA, Read/Write, and
Ao~A.. address lines. In the four-channel mode when TxAKB is
needed, the CS gate must have an open-collector output (a
pull-up resistor should not be used). In the two-channel mode,
CS/TxAKB is always an input.
Address Lines (Ao ~ A. )
Address lines Ao ~A. are both input and output lines. In the
MPU mode, these are high impedance inputs used to address the
DMAC registers. In the DMA mode, these lines are outputs
wWch are set to the contents of the Address Register of the
channel being processed.
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Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
------------------------HD6844,HD68A44,HD68B44
Interrupt Request/DMA End (lRO/DEND)
IRQ/DEND is a TTL compatible, active "Low" output that
is used to interrupt the MPU and to signal the peripheral
controller that the data block transfer has ended. If the
Interrupt has been enabled, the IRQ/DEND line will go "Low"
after the last DMA cycle of a transfer. An open collector gate
must be connected to DGRNT and IRQ/DEND to prevent false
interrupts from the DEND signal when interrupts are not
enabled. Refer to the section of "DMA End Control".
ReadJWrite (R/W)
Read/Write is a TTL compatible line that is a high impedance
input in the MPU mode and an output in the DMA mode. In the
MPU mode, it is used to control the direction of data flow
through the DMAC's input/output data bus interface. When
Read/Write is "High" (MPU read cycle) and the chip is selected,
DMAC data output buffers are turned on and a selected register
is read. When it is "Low", the DMAC output drivers are turned
off and the MPU writes into a selected r~gister.
In the DlI4A mode, Read/Write is an output to drive the
memory and peripheral controllers. Its state is determined by
bit 0 of the Channel Control Register for the channel being
serviced. When Read/Write is "High", the memory is read and
the data from the memory is written into the peripheral
controller. When it is "Low", the peripheral controller is read
and its data stored in the memory. In the DMA mode, the
DMAC data buffers are off.
Reset (RES)
The RES input provides a means of reset~the DMAC from
an external source. In the "Low" state, the RES input causes all
registers, with the exception of the Address and Byte Count
Registers, to be reset to the logic "0" state. This disables all
transfer requests, masks all interrupts, disables the data chain
function, and puts each Channel Control Register into the
condition of memory write, Halt Steal transfer mode, and
address increment.
• Transfer Signals to the MPU
Two DMA request output lines and a DMA Grant input line,
together with the system clock, synchronize the DMAC with the
MPUsystem.
DMA Request Three-State Control Steal (DRaT)
This active "Low" output requests a DMA transfer for a
channel configured for the TSC Steal transfer mode. This line is
connected to the system clock driver, requesting a tPl clock
stretch. It will remain in the "Low" state until the transfer has
begun.
DMA Request Halt (DROH)
This active "Low" output requests a DMA transfer for a
channel programmed for the Halt Steal or Halt Burst mode
transfer. This line is connected directly to the MPU HALT input
and remains "Low" until the last byte has begun to be
transferred.
DMA Grant (DGRNT)
This is a high impedance input to the DMAC, giving it
control of the system busses. For the TSC Steal mode, the signal
comes from the system clock drive circuit (OM A Grant),
indicating that the clock is being stretched. For either of the
Halt modes, this signal is the Bus Avallable from the MPU,
•
indicating that the MPU has halted and turned control of its
busses over to the DMAC. For a design involving TSC Steal and
Halt mode transfers, this input must be the OR of the clock
driven DMA Grant and the MPU BA.
tP2DMA
Transferring in and out of the DMAC registers, aarnpling
of channel request lines and gating of other control signals to
the system is done internally in conjunction with the tP2 DMA
high impedance input. This input must be the system memory clock (non-stretched tP2 clock).
• Transfer Signals From the Peripheral Controller
Transfer Request (TxROo-TxR03 )
Each of the four channels has its own high impedance input
request for transfer line. The peripheral controller requests a
transfer by setting its TxRQ line "High" (a logic "I "). The lines
are sampled according to the priority and enabling established in
the Priority Control Register. In the Steal mode and the ftrst
byte of the Halt Burst mode, the TxRQ signals are tested on the
positive edge of tP2 DMA and the highest priority channel is
strobed. Once strobed, the TxRQs are not tested until that
channel's data transfer is fmished. In the succeeding bytes of the
Halt Burst mode transfer, the TxRQ is tested on the negative
edge of tP2 DMA, and data is transferred on the next tP2 DMA
cycle ifTxRQ is "High".
• Transfer Signals to the Peripheral Controller
Two encoded lines select the channel to be serviced. A strobe
line acknowledges the request and performs the transfer. The
OEm> line signals to the peripheral controller that the DMA
transfer is completed.
Transfer Acknowledge A IT x AKA)
The Transfer Acknowledge A (TxAKA) is a TTL compatible
output used in conjunction with the CS/TxAKB llne to select
the channel to be strobed for transfer and to give the DMA End
Signal. In the two-channel mode, only TxAKA is used to select
channel 0 or channell, and CS/TxAKB is always an input.
Chip Seleet/Transfer Acknowledge B (CSlTxAKB)
In the DMA mode, this dual purpose line is encoded together
with TxAKA to select the channel being serviced. Table I shows
the encoding order.
Table 1 Encoding Order
CS/TxAKB
TXAKA
0
0
0
0
1
1
1
0
1
2
3
1
Channel
#
Transfer Strobe ITxSTB)
The TxSTB causes acknowledgement to be given to the
peripheral controller and transfers the data to or from the
memory. This line is also intended to be the VMA signal for the
system in the DMA mode. In a one-cl1annel system, TXSTB may
be inverted and run to the peripheral controller's Acknowledge
input. In a two or four-channel system, TxSTB enables the
decode of TxAKA and CS/TxAKB to select the device
controller to be acknowledged.
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75
HD6844,HD68A44,HD68B44-------------------------Interrupt Request/DMA End (lRQ/DEND)
and Data Chain Control Register (OCR) that controls data chain
function. Refer to Table 2 and Figure I.
These are Read/Write registers and MPU can exchange the
data with DMAC when CS is at "Low" level. Ao-A4 specifies
the address of the registers. How to specify the registers is
shown in Table 2.
2-byte ADR and BCR can be read or written by one instruction, using 2-byte instruction of the MPU.
In the DMA mode, this dual purpose line is "Low" for the
last byte of transfer, indicating a DMA End. This occurs when
the Byte Count register decrements to zero.
This line, through the decode of TxAKA and CS/TxAKB,
can be used to strobe a DMA End to each device controller.
•
Address Lines to the Memory
Address Lines (Ao-A,,)
• Function of Internel Registers
ADR (Address Register)
These output lines are in the high impedance state during the
MPU mode. In the DMA mode, these lines are outputs which are
set to the contents of the Address Register of the channel being
processed.
Each channel has l6-bit Address Register. Initial address of
memory used for DMA transfer is programmed to this register.
The contents of ADR are output to address bus (Ao-Au)
during DMA transfer operation. When I-byte transfer has completed, the 16-bit address is incremented or decremented by
one.
The address which the MPU reads out is the renewed one,
that is, the memory address for the next transfer. When I-block
transfer has completed, final memory address +1 or -1 is read
out.
• THE DMAC REGISTERS
The H06844 (DMAC) has Address Register (ADR), Byte
Count Register (BCR), Channel Control Register (CHCR), and
General Control Register (GCR).
General Control Register (GCR) is composed of Priority
Control Register (PCR) that controls priority among the chan·
nels, Interrupt Control Register (ICR) that controls interrupt
Table 2 Internal Registers of the DMAC
Symbol
Channel
Address Register
AORH
AORl
Byte Count Register
Register Name
Address Bus Signal
Address
(HexadecimaH
A4
A3
A,
AI
Au
0
0
0
0
0
0
0
0
0
0
0
1
00
01
BCRH
BCRl
0
0
0
0
0
0
0
0
1
1
0
1
02
03
Address Register
AORH
AORl
1
1
0
0
0
0
1
1
0
0
0
1
04
05
Byte Count Register
BCRH
BCRl
1
1
0
0
0
0
1
1
1
1
0
1
06
07
Address Register
AORH
AORl
2
0
0
1
1
0
0
0
0
2
0
1
OB
09
Byte Count Register
BCRH
BCRl
2
2
0
0
1
1
0
0
1
1
0
1
OA
OB
Address Register
AORH
AORl
3
3
0
0
1
1
1
1
0
0
0
1
OC
00
Byte Count Register
BCRH
BCRl
3
3
0
0
1
1
1
1
1
1
0
1
OE
OF
Channel Control Register
CHCR
CHCR
CHCR
CHCR
0
1
2
3
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
10
11
12
13
Priority Control Register
PCR
0
1
0
0
14
ICR
-
1
Interrupt Control Register
1
0
1
0
1
15
Data Chain Control Register
OCR
-
1
0
1
1
0
16
(NOTE)
II All the registe .. can be acc....d by Reed/Write operation. Unused bit _of the regi'tor is reed out "0".
21 H/L of ADR and SCA means the higher (HI 8 bit,/thelower ILl 8 bits of. 16-bit registor.
31 Being allocated to continuous .ddr.... 16-bit ADA and SCA can be read or written by on. instruction. using MPU's 2-byte
LOAD/STORE instruction.
Aegi.ter Addre..
•.g. LDX
$~.
DC
•........... [!ADAH 3) -
Address of DMAC
(lndu Aegister HI]
(ADRL 3) - (Index Aegister II
@HITACHI
76
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose. CA 95131 • (408) 435-8300
--------------------------HD6844,HD68A44,HD68844
BCR (Byte Count Register)
Each channel has a l6-bit Byte Count Register. Number of
DMA transfer words is programmed into this register. The con·
tent of the Byte Count Register is decremented by one every time
one-byte transfer has completed. When it becomes "0", DEND
output goes "Low" level and informs I/O controller of the end
of one·block DMA transfer. When IRQ is not masked, IRQ output goes "Low" level and MPU is interrupted to be informed of
the end of DMA transfer. Moreover, IRQ and DEND signals are
output, multiplexed with IRQ/DEND pin.
used to program the control information of its corresponding
channel. Structure ofCHCR is shown in Table 3.
(I) R/W Control (specifies the direction oftransfer)
Bit - CHCR Bit 0
This bit controls the direction of DMA transfer. When it
is at "1", R/W signal of'DMAC goes "High" level during
DMA transfer operation. This means to read out memory
and write into I/O controller, that is, data is transferred
from memory to I/O controller.
When it is at "0", R/W output goes "Low" level and
data is transferred from I/O controller to memory.
CHCR (Channel Control Register)
Each channel has Channel Control Register. This register is
Table 3 Bit Structure of CHCR (Channal Control Ragistar)
Bit
No.
Name
0
RIW
R/W
1
R/W
RIW
R/W
4
5
Burst/Cycle Steal
TSC/HALT
Address down/up
Not used
Not used
6
Busy/Ready Flag
R
7
DEND Flag
R
2
3
Function
ReadlWrite
"1"
Transfer from memory
to I/O controller
(R/W output = "High")
Burst Mode
TSCMode
Address: -1
-
"0"
Transfer from I/O
controller to memory
(R/W output = "Low")
Cycle Steal Mode·
HALT Mode·
Address: +1
-
-
-
-
Busy
(DMA Transfer Operation)
DMA End & Interrupt
Ready
(No DMA Transfer Operation)
No Interrupt
• Burst transfer in TSC mode is prohibited. R: Read, W: Write
Note that during DMA transfer operation, the function of
R/W signal is accommodated to the memory Read/Write
operation. Therefore, on the side of I/O device during DMA
transfer operation, R/W input should be interpreted in
inverse of the MPU Read/Write. That is, data should be output when R/W input is at "Low" level (In the case of
MPU's read operation, I/O device outputs the data when it
is at "High" level).
This arises from that during DMA transfer operation,
I/O side performs data transfer independently instead of
MPU. Moreover, such fam"!!y LSI as H06843 (FDC), etc.
has this function and R/W signal is automatically interpreted inversely.
(2) Burst/Cycle Steal Bit - CHCR Bit I
This bit is used to decide that DMA transfer should
be performed in burst mode or cycle steal mode. When it
is at "I ", it specifies burst mode. That is, once DMA transfer is performed, MPU remains stopped until one-block data
transfer is completed.
When this bit is "0", it specifies cycle steal mode. That
is, every time one-byte transfer has completed, MPU takes
back the bus control, and DMA transfer and MPU operation
are performed in time sharing.
(NOTE) Only in the case of HALT mode, burst mode can
be specified. In TSC mode, burst mode cannot
be specified.
(3) TSC/HALT Mode Bit - CHCR Bit 2
This bit is used to decide that DMA transfer should be
•
performed by using MPU's TSC function or HALT function. When it is at "0", DMA transfer request signal is output
from DRQH of DMAC.
When it is at "I", DMA transfer request signal is output
from DRQ'f of DMAC.
(4) Address down/up Bit - CHCR Bit 3
This bit is used to decide that the address of memory
region used for DMA transfer should be renewed up (increment of address) or down (decrement of address). When it
is at "I", the address is decremented by one after one-byte
transfer. When it is at "O"l the address is incremented by
one.
(5) Busy/Ready Flag Bit - CHCR Bit 6
This bit is a status flag to indicate whether its corresponding channel is performing DMA transfer or not.
(READ only)
When it receives the first TxRQ of its corresponding
channel, it goes to "I". When one-block transfer is completed and BCR becomes ''0'', it is reset to "0".
Also this flag is cleared when corresponding TxRQ_,
Enable Bit in the PCR becomes "0".
(6) DEND Flag Bit - CHCR Bit 7
This bit is an interrupt flag to indicate that one-block
DMA transfer of its corresponding channel has completed.
(READ only).
When one-block transfer of its corresponding channel is
completed and BCR becomes "0", it goes to "I". As soon
as this flag is read out, i.e. CHCR of this channel is read
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Hitachi Amenca Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
77
HD6844,HD68A44,HD68B44-------------------------out, it is reset to "0".
Moreover, this bit is connected to IRQ output. When it
is at "I" and IRQ enable bit (within ICR register described
later) is at "1", IRQ output goes "Low" level.
PCR (Priority Control Register)
Priority Control Register is a S-bit register to decide the
operation mode of priority control circuit. Structure of PCR is
shown in Table 4.
Table 4 Bit Structure of PCR (Priority Control Register)
Bit
No.
Function
Read
/Write
"1"
R/W
TxRO of Channel 0 is accepted.
"0"
TxRO of Channel 0 is not accepted.
1
TxRO Enable #0 (TxEN o )
TxRO Enable #1 (TxEN,)
R/W
TxRO of Channel 1 is accepted.
TxRO of Channel 1 is not accepted.
2
TxRO Enable #2 (TxEN 2 )
R/W
TxRO of Channel 2 is accepted.
3
TxRO Enable #3 (TxEN 3 )
R/W
TxRO of Channel 3 is accepted.
TxRO of Channel 2 is not accepted.
TxRO of Channel 3 is not accepted_
-
-
-
0
Name
4
Not used
-
Rotate Control
R/W
5
6
7
Rotate Mode
The order of priority is fixed at
numerical order.
R: Read, W: Write
(I) TxRQ Enable Bit (TxENo -TxEN 3) - PCR Bit 0-3
Each channel has this TxRQ Enable bit. When it is at
"I ", TxRQ input of its corresponding channel is accepted
to perform DMA transfer. When it goes to "0", TxRQ of its
corresponding channel is masked not to be received and
TxAK is not output. During DMA transfer operation, when
this bit goes to "0" before BCR becomes "0", follOwing
TxRQ input is not accepted and DMA transfer is interrupted. Then contents of ADR and BCR remain unchanged.
When it rises to "1" again, DMA transfer is reopened.
Therefore, in the case of cycle steal DMA, it is possible for
the program to change the priority of the specific channel
temporarily by manipulating this bit.
(2) Rotate Control Bit - PeR Bit 7
When this bit is at "0", the order of priority among
DMA channels is fIxed at numerical order. That is, Channel
o is given a fIrst priority and then is followed by Channel
1->2->3.
When this bit is at "1", priority control is due to rotate
mode. That is, the channel that ended in the fIrst time is
given a fIrst priority and the channel ended in the last time
is controlled to be given a last priority.
ICR (Interrupt Control Register)
Interrupt Control Register is a S-bit register to control IRQ
output. Its structure is shown in Table 5.
(I) IRQ Enable Bit - ICR Bit 0-3
Each channel has IRQ Enable Bit. When this bit is at "1"
and DEND Flag of its corresponding channel is set to "1",
IRQ output goes "Low" level. But when it is at "0", IRQ
output is masked not to be output even if DEND Flag is set
to at ".
These bits enable to control to output only a necessary
channel to IRQ.
(2) IRQ Flag - ICR Bit 7
This is a read-only bit and the status of IRQ output is
directly reflected on it. That is, when IRQ output goes to
"Low" level, it becomes "I".
IRQ output of DMAC is output as logical OR of 4channel DEND Flag according to the following equation.
IRQ = (DEND o ' IRQ Enableo) + (DEND, •IRQ
Enable,) + (DEND2 •IRQ Enable 2) +
(DEND3 ·IRQ Enable3)
OCR (Data Chain Control Register)
Data Chain Control Register is a 4-bit register and three of
those bits are used to control data chain function. Remaining
one bit is used to specify 2-channel/4-channel mode.
Structure of DCR is shown in Table 6.
(I) Data Chain Enable Bit - DCR Bit 0
When this bit is at "1", data chain function of DMAC
is enabled. That is, when DMA transfer of a specified channel has completed and BCR goes to "0", the contents of
ADR and BCR of Channel #3 are automatically transferred
to ADR and BCR of the specifIed channel.
(2) Data Chain Channel Bit - OCR Bit 1-2
These bits are used to specify which channel should
be used for the data chain. How to specify the channel is
shown in Table 7. Data Chain Channel bit specifies the
channel to which data should be transfered from Channel
#3. Channel #3 contains the data for replacement. Channel
#3 is fIxed and cannot be changed.
(3) 2/4-channel Mode Bit - DCR Bit 3
This bit has no relation to the data chain function.
It is used to specify whether CS/TxAKB is used for only
input pin or I/O pin. When this bit is "0", CS/TxAKB be·
comes CS input pin in 2-channel mode since TxAKB output
is not necessary for application up to 2-channeL
When this bit is "I", CS/TxAKB becomes I/O pin in
4-channel mode (See Fig. 11).
~HITACHI
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--------------------------HD6844,HD68A44,HD68B44
Tabla 5 ICR (Interrupt Control Register)
Bit
No.
Function
Read
/Write
Name
"0"
"1"
0
I RQ Enable #0
R/W
fRO of Channel 0 is able to be output. i"Fm output of Channel 0 is masked.
1
IRQ Enable #1
R/w
I RQ of Channel 1 is able to be output.
I RQ output of Channel 1 is masked.
2
IRQ Enable #2
R/W
I RQ of Channel 2 is able to be output.
I RQ output of Channel 2 is masked.
3
I RQ Enable #3
R/W
I RQ of Channel 3 is able to be output.
I RQ output of Channel 3 is masked.
Not used
-
-
4
5
6
7
fRO output "Low"
i"Fm output "High"
IRQ Flag
R
-
(off state)
R: Read, W: Wrote
Table 6 Bit Structura of OCR (Date Chain Control Register)
Bit
No.
0
1
2
3
4
5
6
7
Name
Data Chain Enable
R/W
Data Chain Channel
~
2/4·Channel Mode
R/W
)
Function
Read
/Write
R/W
Data Chain is not performed.
Data Chain is performed.
The channel which performs Data Chain is specified.
(The channel where contenU of AOR and BCR of Channel
#3 are loaded.)
2·Channel Mode (CS/TxAKB is
4·Channel Mode (CS/TxAKB is
designated to only input pin.)
1/0 pin.)
Not used
"0"
"1"
-
-
-
-
-
-
-
R: Read, W: Write
Tabla 7 How to specify Date
Chain Channel
OCR
Bit 1
Specified
Channel
OCR
Bit 2
0
0
Channel #0
1
0
Channel #1
0
1
Channel #2
1
1
TTL Input
,--------I
! r.- (BA of MPU)
I
I
- - - - CS Input
CS
or
r------OGRNT
-to<.r --- CS
Input
I
I
:
----2DMA
TxRQ
DGRNT
Both the MPU and the DMAC are )
( in the wait state until the
next TxRQ input.
Figure 15 Extraordinary TxRQ Input (2)
( In the case where TxAQ doesn't fall to "Low" after
the transfer has been completed.
~HITACHI
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--------------------------HD6844,HD68A44,HD68B44
@ When BCR is not "0", TxRQ is checked at the falling edge
HALT Burst Mode
In the case of cycle steal mode, MPU gets into Instruction
Cycle everytime I-byte transfer has completed. But in the case
of burst mode, MPU remains stopped until I-block transfer is
finished. That is, DRQH continues to be output "Low" level
until BCR becomes "0" .
Its timing chart and flow chart are shown in Fig. 16 and Fig.
13 respectively. Procedure of transfer is the following (No. G)
- ® in Fig. 16 correspond to the following items).
G) TxRQ input is checked at the rising edge of q,. DMA. When
it is at "High" level, it gest into the following operation.
® DRQH="Low" level is given and MPU is requested to stop its
operation.
@TxAKA is driven.
@MPU stops and DMAC waits for DGRNT rising "High" level.
® When DGRNT rises "High" level, DMAC drives TxAKB, Ao
- A IS , and R/Wlines.
® TxSTB is sent out to perform DMA transfer.
Address is incremented or decremented by one and number
of transfer words is decremented by one.
® TxRQ falls to "Low" level.
® When number of transfer words is 0, from ® to @
operations are performed.
of q,. DMA.When TxRQ is at "High" level, DMA transfer is
performed through ® - ® again. When TxRQ is not at
"High" level, DMAC waits for becoming "High" level.
® IRQ/DEND output goes to "Low" level.
@ DRQH output rises to "High" level and MPU gets into
Instruction Cycle again.
@ Ao - AI. and R/W get into high impedance state.
® DGRNT falls to "Low" level.
The transfer of the first byte (G) - ®) is performed in the
same way as that in HALT cycle steal mode. But in the secondbyte and subsequent transfer, TxRQ is checked at the falling
edge of q,. DMA and if TxRQ is at "High" level, DMA transfer
is performed at the following cycle. Therefore, a high-speed
response (MAX. I by tell cycle) is feasible.
In burst mode, TxRQ should be also, in principle, set to
"High" when 1/0 request is asserted, and reset to "Low" when
TxSTB goes to "Low". If TxRQ is asserted as level input without being reset, DMA transfer is performed at all cycles of
q" DMA since TxRQ is always at "High" level at the falling edge
of q,. DMA. Its example is shown in the second-byte and the
third-byte transfer in Fig. 16.
o
-r
First.lJyte
Second-byte Final-byte
DMA TDunwny
D M A T D M A -j Dead
r!lzDMA
DRQH
DGRNT
..
-:
TxAKA
~tTKD2
i
~
TxAKB
:-tTKD2
: \l~l
(output)
CS(,nput)
~
I
x
7
i
I
(output)
x
IS
A.-AlS. R/W
A.-A<. R/W
,
~tATSD
x
x
:@
. : !I
I
(input)
IRQ/DEND
Figure 16 HALT Burst Mode
TSC Cycle Steel Mode
In the above-mentioned modes, DMA is performed by using
the HALT function of the MPU. In TS::: cycle steal mode, DMA
is performed by using the TSC function of the MPU.
Its timing chart and flow chart are shown in Fig. 17 and
Fig. 13 respectively.
Basic operation of the DMAC is the same as that in HALT
cycle steal mode, but the detailed timing is different. The difference is explained in the following.
(1) DRQT is used for DMA transfer request instead of DRQH.
(2) DRQT is sent to the external clock control circuit to
•
extend clock E (q,.) of MPU.
(3) To DGRNT, the external clock control circuit inputs
response signals.
In TSC mode, there isn't a burst mode. Because the MPU
clock cannot be extended for a long time because MPU performs dynamic operation. When TSC mode is specified, DRQT
returns to "High" and the MPU gets into the instruction cycle
every time I-byte transfer has fmished.
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
83
HD6844,HD68A44,HD68B44-------------------------
E 1.)
TxRQ
DGRNT
I
I
I
•
:.---~@:.
: tTKDI
TxAKA
I
tTKDI
~I:
~
.--,
: \;
---------+-.. .I""""'t'~.:..:....;....----+-tTKDI...: -)+-_------
TxAKB
(output)
CS(intput)
Ao-AlS, R/W
(output)
Ao-A•• R/W
- : :-tAHO
__-2M~P~U~_1Xl__!M~P~U~+-~>>---~--------:i--<<:,---~--M~P~U-----Xn--
(input)
HtDED'
I
\ : . __
HtDED!
._.J
HtDEDI
- - - -_ _...l. When
IFfel is
put out
Figure 17 TSC Cycle Steal Mode
• Priority Control
Balic priority Control
There are two kinds of the DMAC priority control function.
One is to mask TxRQ on each channel by TxRQ Enable bit
of PCR. The other is priority·order·determining.circuit which
the DMAC has as a hardware.
Moreover, the priority- order- determining- circuit has two
operation modes (the rotate mode and the normal mode).
Structure of the priority control circuit is shown in Fig. 18.
As shown in Fig. 18, TxRQ of the channel whose TxRQ Enable
bit is at "1" level becomes an input of the priority-order.deter.
mining-circuit. Then it is checked whether TxRQ is at "High"
level or not.
(Note) In this case. ZERO flag needs to be at "I" level. ZERO
flag will be described later.
If one of TxRQo-TxRQ3 is at "High" level, its channel is
selected, being given a first priority. Then it is latched by an
executing.channel.number.latch.circuit to perform DMA trans·
fer. Once an executing channel is determined and latched, it is
unchanged until its DMA transfer has been completed. That is,
the channel number strobe signal of DMAC doesn't go to "I"
and the contents of the channel·number·latch·circuit are un·
changed. In the cycle steal mode, the channel is fixed until
I·byte transfer has completed. In the burst mode, it is fixed
until BeR becomes "0".
~HITACHI
84
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose. CA 95131 • (408) 435-8300
-------------------------HD6844,HD68A44,HD68B44
Rotat. Mode BIt
TxRO Enabl. Bit of PCR
3
Chann.1 Number Strobe SIgnal (Synchronous with
X
(putput)
A.- A15.R!W
X
Input)
RQ/DENo
x
>
X
\.._--
Figure 23 Channel Change (HALT Mode -+ HALT Mode)
MPU
E (1/1,)
~
MPU
_ _ _ _ _ _ _ _ ___',..,L._ _ _ _ _ _ _ _ _ _r_"L.._
NDMA
Tx_
TxRQB
DRQT
DGRNT
-----------~----~'_____¥r-------ti---~'-----'r--------------
,
'Hi:I
!
:
I
:
,
,
TxAKA
TxAKB
(output)
cs (,nput)
I
'
;'--
<
>
\.... .. __! ______________ J <.....
~
_.~
Figure 25 Channel Change (HALT Mode .... TSC Mode .... HALT Mode)
+2DMA
TxRQ
DRQH
JjJJ
YliZ!J
6~7
,'-------
!!17
\
TxSTB'
TxAKB
I
1\
\
DGRNT
TxAKA
\\\\\\
LJ
I
\
I
\
I
\
\
I
* Executing Period of One Instruction
Figure 26 Successive 2-byte Transfer of One Channel (HALT Cycle Steal Mode)
HALT .... HA LT (by one channel)
•
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
89
HD6844,HD68A44,HD68B44------------------------•
Status Flag
DMAC has BUSY Flag, DEND Flag and ZERO Flag on each
channel. The former two of these flags can be read out by
MPU, but ZERO Flag cannot be read out. Set and reset timing
of each flag are shown in Fig. 27.
BUSY/READY Flag
This flag is set to "1" when it accepts the first·byte TxRQ
of its corresponding channel. After I·block transfer has com·
pleted and BCR becomes "0", it is reset to "0". Therefore,
while this flag is "I ", that is, its corresponding channel is being
used, the next block transfer cannot be performed.
Also this flag is cleared when corresponding TxRQ Enable
Bit it. the PCR becomes "0".
DEND Flag
This is the interrupt flag to indicate the end of DMA trans·
fer of its corresponding channel. After I·block transfer has com·
pleted and BCR becomes "0", this flag is set to "I". This flag is
reset to "0" immediately after the Channel Control Register
having this flag is read out.
ZERO Flag
This is the internal flag to indicate whether the data stored in
the BCR is "0" or not (It cannot be read out).
MPU
MPU
~2OMA
TxRQ
~/DEND-------r------------'
~
__.,.. _________
In the case where
is masked.
-::"_~Q
BUSy/READY--------~
Flag
DEND Flag _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _\--..l
ZERO Flag
MPUWrlte
BCR
MPUR••d
~
BCR
_ ______________
~nL._
.
-
CHCR that has the flag
CHCR
is read out.
Figure 27 Timmg of Status Flag (Suppose that BCR is 2 in the initial state)
When BCR is "0", ZERO Flag is "0". When BCR is not "0",
it is HI".
In the reset state, this flag is "0". If data that is not "0" is
written into BCR, this flag is set to "I". When BCR btl{;omes
"0" after I·block data transfer has completed, or MPU writes
"0" into BCR, this flag is reset to "0" .
The function of ZERO Flag is to prohibit accepting TxRQ
of its corresponding channel while this flag is "0" (that is, BCR
is "0") (See Fig. 18). While ZERO Flag is "0", TxRQ is not
accepted even if TxEN is "I". This function avoids an false
operation even if "High" input is provided to TxRQ before the
initialization of the register.
When RES pin goes to "Low", this flag becomes "0", but the
number in BCR is not reset to "0". Therefore, the state of this
flag and BCR are not the same. In this case new data should be
written into BCR (Then ZERO Flag becomes" I ").
• DMA End Control
Function of IRQ/DEND Pin
~MAC has IRQ output and DEND output to perform
DMA End Control. These are multiplexed outputs to IRQ/
DENDpin.
The function of DEND output is to inform I/O controller of
the end of I·block transfer. After l·block transfer has been
completed and BCR becomes "0", DEND output provides
"Low" pulse whose cycle is one clock, being synchronous with
the final I·byte data transfer. 4 channels have only one I>EN'D
output in common, so each channel determines whether DENI>
output is its own output or not, combining with TxAK signal.
When TxAK of the channel is "High" and DEND is "Low",
it shows that the cycle is the last one of DMA (See Fig. 29 and
30).
The function of IRQ output is to inform MPU of the end of
I·block transfer by interrupting it. As shown in Fig. 28, IRQ
output is logical AND·OR of the interrupt flag (DEND Flag)
and IRQ Enable bit of each channel.
IRQ and DEND outputs are multiplexed. IRQ/DEND pin is
used as DEND output during DMAC cycle and IRQ output
during MPU cycle. Moreover, DGRNT signal separates DEND
and IRQ by its "High" or "Low". In detail, see Fig. 29 and
Fig. 30.
~HITACHI
90
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
-------------------------HD6844.HD68A44.HD68844
#0
# 1
»---- IRQ Output
DEND Flag
(CHCR BIt 71
#3
#3 #2 # 1 # 0
~
IRQ Enable Bit (PCR Bit 0-31
Figure 28 Logic of I RQ Output
~2DMA
T.AK
l #O----------~~~I--------~
# 1 _ _ _ _ _ _ _ _ _ _~fiNlL_ _ _+ _ - -
DGRNT
iiEiiii
\#0
#1
-------7'------------------------~
Figure 29 Timing of I ROIDEND Output
$
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-~------
91
~~~~~~-
HD6844.HD68A44.HD68B44-------------------------IRQ
DMAGRANT
Open Collector TTL
DGRNT
Channel Number
IRQ/OENO
--'LJo~-
TxSTB
# 'OJ OENO
# I
OMAC
TxAKA
b-DD--+---- :;)
TxAK
CS/TxAKB
Decoder
Figure 30 How to Use IROIDEND Output Signal
Unusual DMA End
Following section describes how to terminate or change
normal sequence of DMA transfer.
(I) When "0" is written into BCR
When "0" is written into BCR before it becomes "0",
subsequent TxRQ are not accepted and this causes the termination of the DMA transfer since the internal ZERO
Flag is reset to "0". In this case, note that DEND pulse is
not provided.
(2) When "I" is written into BCR
When "I", instead of "0", is written into BCR, only the
next TxRQ is accepted and I-byte DMA transfer is performed. In this case, DEND pulse is provided, being synchronous with the last transfer.
(3) When another value is written into ADR & BCR during the
transfer
When the data in ADR & BCR are changed during the transfer, the follOwing transfer is performed according to the
change of the data.
(4) When "0" is written into TxRQ Enable bit
When TxEN is reset to "0" during the transfer, this causes
TxRQ comes not to be accepted and the transfer halts. But
the state is different from that in the case (I), the number
in BCR remains unchanged. Therefore, when TxEN is set to
"," again, the transfer is performed again.
(5) When RES pin is set to "Low"
When RES is provided during the transfer, the transfer
stops.
Then all of the control registers and their internal flags are
reset to "0". But the data in ADR & BCR are not reset.
(Supplement)
It is only in the cycle steal mode that DMAC registers such as
BCR and ADR can be read or written during the transfer. In the
burst mode, it is usually impossible (But special external circuits
enable it).
•
Data Chain Function
The data chain function of DMAC is to transfer the contents
of ADR & BCR of Channel #3 to ADR & BCR of a specified
channel automatically and renew the data of them after the
channel has completed I-block transfer.
•
92
ADR
~
(
eCR
#0
#0
#1
# I
#2
#2
#3
#3
OCR specifies
the channel to
which the contents
of Channe' #3 are
transfered.
~
Channel #3 has address
and number of transfer
words for the renewal.
Figure 31 Data Chain Operation
Its detailed timing is shown in Fig. 32 and Fig. 33. As shown
in these figures the contents of ADR & BCR of Channel #3
are transfered to the channel during the clock cycle next to the
last one of I-block transfer (which provides DEND pulse). Then
DRQH or DRQT provides "Low" output for one more clock
cycle than in the normal case. Therefofe, MPU takes back the
bus control again I-clock later than in the normal case, that is,
after the data renewal of the specified channel by the data
chain from Channel #3.
In the TSC mode, the stretching period of cJocktPl is longer
than in the normal case.
The contents of ADR & BCR of Channel #3 remain unchanged as long as new data are not written by MPU, even if
the data chain is executed.
As for DEND output, DEND Flag and BUSY Flag in the case
of data chain execution, they function in the same way as in the
normal case. They provide DEN'D pulse every time I-block transfer has completed, and then DEND Flag is set to "'''. Therefore, in the case where more than 3-block data chain is needed,
DEND Flag is used for the execution. Its sequence is shown in
Fig. 34. First, DEND Flag="'" that shows the end of the firstblock data chain is read out. Next, the data of ADR & BCR for
the third-block data chain need to be written into Channel #3,
in parallel with the execution of the second-block data chain.
(This data chain is feasible only in the cycle steal mode.)
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose. CA 95131 • (408) 435-8300
-------------------------HD6844,HD68A44,HD68B44
Cycle under the execution of
Data Chain
- - - - - - MPU
------I
I'
f-DMA
I
!- M P U - -
TxAQa
-----~,~
_ _ _ _ _ _ _ _i__J/~--------
,'-----T.I\KA
iiiij>iiEND
__
u
u
. . _______________ u
_________ u
__ . /
' ' _ __ _
~~/--_ _. . ;
'C
The contents of ADR .. BCR
of Channel #3 are tranderad
to Channal a.
Figure 32 Data Chain Operation (HALT Mode)
- - MPU
Cycle under the execution of
Data Chain
I- DMA-+I'---oj
~
MPU - - - - -
T._
--------"------------~~,~~---------------I
---------------------~''----~-II----_r-------------------------
,
,
TxAKA
TxAKB
CS(,.pul)
C!1ii
,
CHa
I
......
x
x
<
AD-All, R/W
(outpul)
(onput)
==~xc==>~--~--~<====~xc==
iliQ/5iiIi
~~~~~~~.~~~~~--~\~
Ao-A..R/W
.. .. .. .. .. .. .. .. .. ..
__~,r--~------.-..-.-..-..-..-.-..-..-_.-.-_.
The ocntants of ADR .. SCR of
Channel #3 are trensfered
to Chan nel a.
Figure 33 Oata Chain Operation (TSC Mode)
_HITACHI
I·litachi America Ltd. • 2210 O'Toole Ayenue • San Jose, CA 95131 • (408) 435·8300
93
HD6844,HD68A44,HD68B44-------------------------
T_AK
u
u
DEND Flag
BUSY Flag
Channel #3
ADR)
BCR
The data of ADR & BCR
for the third block
are written.
Wrote Signal
Read Signal
of CHCR of the
SpecIfied Channel
Figure 34 Sequence of More than 3-block Data Chain
•
DMAC PROGRAMMING
Preparation of a channel for a DMA transfer requires:
1) Load the starting address into the Address Register.
2) Load the number of bytes into the Byte Count Register.
3) Program the Channel Control Register for the transfer
characteristics: direction (bit 0), mode (bits 1 and 2), and
the address update (bit 3)_
The channel is now configured. To enable the transfer
request, set the appropriate enable bit (bits 0-3) of the Priority
Control Register, as well as the Rotate Control bit.
If an interrupt on DMA End is desired, the enable bit (bits
0--3) of the Interrupt Control Register must be set.
If data chaining for the channel is necessary, it is programmed into the Data Chain Register and the appropriate
data must be written into the Address and Byte Count Registers
for channel #3.
Table B DMAC Programming Model
Register
Channel
Address
(He_)
,..
Control
PriOrity
14
Control
Interrupt
Bit6
Bit 5
Bit4
Bit 2
Bit 1
Bit 0
DMA End
Flog
(DEND)
Busy/Reedy
Flog
Not Used
Not Used
Address
Up/Down
Bit3
TSC/
Halt
Burst/
Steal
ReadiWrite
(RiW)
Rotate
Control
Not Used
Not Used
Not Used
T_RQ
Enable #3
(T_EN3)
T_RQ
Enable #2
(T_EN2)
T_RQ
Enab!~
(TxENll
T_RQ
Eneble #0
(TxENO)
#1
15
IRQ
Flog
Not Used
Not Used
Not Usod
IRQ
Enable #3
(lE3)
IRQ
Enable #2
(lE2)
IRQ
Enable #1
(lE1)
IRQ
Enable #0
(lEO)
16
Not Usod
Not Used
Not Used
Not Used
Two/Four
Channel
Select (2/4)
Data Chain
Channel
Select B
Data Chain
Data Chain
Enable
Control
Data Chain
Register Content
Bit 7
C~annel
Select A
* The x represents the binary equivalent of the channel desired.
A comparison of the response times and maximum transfer
rates is shown in Table 9. The data are shown for a system
clock rate of 1 MHz.
The two 8-bit bytes that form the registers in Table 10 are
placed in consecutive memory locations, making it very easy to
use the MPU index register in programming them.
•
94
Fig. 38 shows an example of its mmunum structure (1
channel, HALT mode, combination with FDC). Fig. 39 shows
an example of its maximum structure. (but only one DMAC is
used.) -
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (4OB) 435-B3OO
--------------------------HD6844,HD68A44,HD68844
Table 9 Maximum Transfer Speed & Response Time of the DMAC when tcvc!/> equals 1 Ilsec.
HALT Cycle Steal
HALT
Burst
Response Time (Ilsec)
Maximum Transfer
Speed (Ilsec/byte)
maximum
minimum
(executing time of
one instruction) + 3
(executing time
of one instruction)
3.5+ tTCS1
Mode
first byte
+1.5 - tTOH1
1
since second
byte
4
TSC Cycle Steal
2 - t TOH2
1 + tTCS2
3.5-tTOH1
2.5+ tToH1
Table 10 Address and Byte Count Registers
mll (Open Collector)
Register
--==-
Do---......
DEND.
T.AK.
~/T.AK
Figure 35 One Channel
Channel
Address
(Hex)
Address High
Address Low
Byte Count High
Byte Count Low
0
0
0
0
0
Address High
Address Low
Byte Count High
Byte Count Low
1
1
1
1
4
Address High
Address Low
Byte Count High
Byte Count Low
2
2
2
2
Address High
Address Low
Byte Count High
Byte Count Low
3
3
3
3
1
2
3
5
6
7
8
9
A
B
C
D
E
F
DEND.
DGRNT
iRa/i5EiiiDII_-I>:I-......----+-I-/~
DEND,
IRQ (Open Co "ector)
T.STBI_-t)~::+=:[==~~---I
T.AK.
DEND. DEND, DEND, DEND,
r-+---- T.AK,
T.AKAI--t:>o-L./":I;;.=t.__
DGRNT
IRQ/DEND~--~~~-~--------~--~--~--~
T.STBI_-4J~I_-~
Figure 36 Two Channel
T.AKA~---~.~~b--f~~-_+-~~-~-TxAK
CSIT.AK
(Open
Collector)
T.AK
TxAK
T.AK
CS
Figure 37 Four-Channel
•
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
95
HD6844,HD68A44,HD68B44--------------~-----------
Address Bua
(16)
Deg au.
(8)
,.
Ao-AI5
IRT
::=:)
0.-0,
H06800
(MPU)
.---
-
h
~
SA
+5V
3.3kQ
-
VMA
;:::v- -
o.MPU
O,MPU
0.-0, HM6810
-
R/W
IRQ
HALT
II
CS, Ao-A.
R/W(RAM)
HM6810
(RAM)
-·· ,.
..,TTL
-
HD26501
(CPG)
DGRNT
i·
DRQH
5
-
As-Au
"
IRQ
~
FD-
--'I
0.-0,
-t>
R/W
CS
H06843
E
(FDC)
0.-0,
--I
8
(DMAC)
I
II
Decoder
Ao-A.
HD6844
oil
-
TdK
T,RQo
-
T,RQ
R/W
-
- ......
'--
-
TxSTi
il_
rr
RES
CS/T,AKB
Vee
Floppy Disk Drive
o.coder
VS.
hDMA
Figure 38 Example of DMA System Structure (1) (minimum)
$
96
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-------------------------HD6844,HD68A44,HD68B44
DB
110-0.
R/W
r--
-,
r- -.
VMA
TSC
IIA
I
--
~rv-
HD26501
(CPG)
DRQ
~
-
-
I-- I-
TxST1l
TxAKA
CS/Tx_
r-
H> l·
~
!
~
1'-1
~)
~-
I.
H>
H>
I-- A
I
r~
.,i
r--
-.1
r--
HD74188
""'c'-o
-
D
c=J
-;:u
DM_
:;::-
RlW
t-
K::::
TxM
TxM
I/O
CS
DB
DEVICE
CION'IROU..I!II HD8843
(FDC)
TxRQ
0 #0-3
[}(;-~-
TxRQo-TxRQo
,
REF~
~
RES
Vee
HM6810
,
.
AI-Au
(DMAC)
~MEM
r-- READY
At-At
HD8844
DB
AS
S~!
110-0.
V..
I-- f-
~
~
r
IRQ/DEN!
I
~
DRQH
DRQT
~MEM
-R£Q
_MEM
MRDY
' - AMPU
' - - - ftMPU
L.-
,
IRQ
HALT
VMA
R~IIII'RQ
~
~
Ao-Als
HD6600
(MPU)
AS
CS
J...)'
o.....J
-
RtW
"DMA
-
• QNn Collector
--
E
ole.
#2
D
Figure 39 Example of DMA Systam Structura (21 (maximum 1
•
Hitachi America Ltd.
0
HITACHI
2210 O'Toole Avenue
0
San Jose, CA 95131 • (408) 435-8300
97
HD6844'HD68A44'HD68B44-------------.,..------------• APPENDIX
Contents of the DMAC Registers
(1 ADR on each channel)
(1) ADRO - ADRJ (Address Register)
L
H
16bitx4
(1 BCR on each channel)
(2) BCRO - BCRJ (Byte Count Register)
L
H
16 bit x 4
(1 CHCR on each channel) (6 bit x 4)
(3) CHCRO - CHCRJ (Channel Control Register)
"I"
Transfer
Direction
Transfer
Mode
Address
up/down
B/R
DEND
"0"
Read
Write
Bunt
TSC
Cycle stoal
HALT
-1
+1
Ready
Busy
DMA END / NOT END
]--"
) Status flag
(5 bit x I)
(4) PCR (Priority Control Register)
7
0
I~R~~~~~T~E~,~I·T~EJ,~~IE~I~I·T~EJ.I.---------+--"+I'-'---'+~'_'_____________
1 1 0-'1
L---,
+
Enable/ Mask
#3
Specify Rotate
Rotate / FIxed
(5) ICR (Interrupt Control Register)
(5 bit x 1)
0
7
II
l
TxRQ #0
#1
Enable #2
"I"
IE, liE, IIEI liE. I
Jt----=]
"0"
#0
#1
IRQ
Enable #2
#3
IRQ Flag
Enable / Mask
IRQ output / NOT IRQ output
Status Flag
(6) OCR (Data Chain Control Register)
(4 bit xl)
o
7
~4/21
~
[I L1
' - - -]
-
"'"
"0"
Executed / NOT executed
=i:?'haln
Specify Data
Chain Chlnnel
Specify
4/2.channel
00
o 1
10
#3
#0
#3 -+ #1
#3-+#2
4-Channel mode / 2..,hannel mode
mode
•
98
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
HD6345
CRTC- II
,-,1(,:,
(CRT Controller)
.:: k:I'((h:
/,
~\(lVC'"
The H06345IH06445 CRTC-II provides an interface between MPU and a raster scan CRT display. Both are upwardcompatible with the NMOS CRTC H06845S in pin and software. The power dissipation is lowered by adopting the CMOS
process.
The H06345/H06445 offers a variety of functions under
MPU control, such as programmable timmg signal outputs for
CRT momtor and display screen control operation. It can be
widely applied to the various types of CRT display systems.
•
q~
HD6345, HD63A45, HD63B45,
HD6445-4
FEATURES
HD6345 PIN AND SOFTWARE COMPATIBLE WITH
HD6845S
HD6445 SOFTWARE COMPATIBLE WITH 6845S
FLEXIBLE SCREEN FORMAT
• Programmable numbers of characters per screen and rasters
per character row
• Programmable horizontal/vertical sync signals and d,splay
timing signals
• Up to 16k words refresh memory (14 bltsi addressable
• Programmable raster scanning modes: non-Interlace, inter·
lace sync, or interlace sync and video modes
• Up to 256 character rows per field
• High·speed display operation at 4.5 MHz character clock
• Double·slze vertical d,splay by raster interpolation
VERSATILE DISPLAY FUNCTIONS
• Screen split (max.4 screens conf,gurable, hOrlzontallyi
• Paging and scrolling for each screen
• Smooth scrolling
• Two cursors with programmable width
• Programmable refresh memory width
FACILITATED SYSTEM CONFIGURATION
• 68 system bus Interface (HD6345)
• 80 system bus Interface (HD6445)
• Three-state control of memory address and raster address
• External synchrOnization In master-slave or TV sync modes
• Interrupt request by vertical blanking or light pen strode
detection
• Programmable tImIng signal for dual-port RAM In DRAM mode
(DP·40)
• PIN ARRANGEMENT
HSYNC/EXHSYNC'
RAo
RA,
RA,
RA,
RA,
Do
D,
D,
D,
D,
D.
D,
Cs
RS
E*, RO+
(Top V.ewi
SINGLE +5 V POWER SUPPLY
Additional functions to the HD6845S
, HD6445
* HD6345
CMOS PROCESS
• TYPE OF PRODUCTS
Type No.
Bus Timing
HD6345
HD63A45
HD63B45
HD6445-4
1.0
1.5
2.0
4.0
MHz
MHz
MHz
MHz
CRT Display Timing
4.5 MHz Max.
$HITACHI
I
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
... _-_.-
_._-----
99
HD6345/HD6445--------------------------------------------------------------------•
INTERNAL BLOCK DIAGRAM
r---------------------------------------------lI
I
I
I
I
I
SCREEN CONTROL
LIGHT PEN CONTROL
R1S, RH, R28
HORIZONTAL TIMING CONTROL
RO, Rl, R2
CLK --+-~-I
I
LPSTB
I
I
I
I
I
CURSOR CONTROL
Rl0, R1 1, R14. R1S. R34
R3B, R3S, R37, R38, R39
I
CUDISPI
I IRa/ACI
I
I
RASTER CONTROL
At
INTERLACE CONTROL
AS
I
I
REs
DISPTMG
DISPLAV CONTROL
SMOOTH SCROLLING CONTROL
R29
VERTICAL TIMING CONTROL
R4, RB, RB, R7, R27
DECODER
W
HSVNCI
EXHSVNC
VSVNCI
EXVSVNC
SYNC CONTROL
R3
CONTROL REGISTERS
R30, R31, R32
STATUS REGISTER
R31
MPU INTERFACE
RS
I'ili
MAO-MAil
L..._ _ _ _ _ _ _t-i-vf RAo-RA.
I
I
~---------------------DATA 100-0,1
• SYSTEM BLOCK DI~GRAM
1------.....- - - - - - - - - . _ - - - - - - - - - - -
ADDRESS BUS lAo-A" 1
MPU
~---~-4_----------+_---------_r-------- DATA BUS 100-0,1
\
RAo-RA.
DOT CLOCK
LPSTB
•
100
LIGHT
PEN
CONTROL
HITACHI
Hitachi America Ltd, • 2210 O'Toaie Avenue • San Jase, CA 95131 • (408) 435-8300
----------------------------------------------------------------------------HD6345/HD6445
•
FUNCTION TABLE
Programmable
Screen Format
Screen Split
Remarks
Descriptions
Item
Programmable by char. clock time
Programmable by char. row time
Programmable by raster time
Horizontal scanning cycle
Vertical scanning cycle (by row)
Vertical scanning cycle (Adjust)
Number of displayed chars. / row
Number of char. rows / screen
Number of rasters / char. row
Horizontal display position
Vertical display position
Vertical sync pOSition (Adjust)
HSYNC pulse width
VSYNC pulse width
DISPTMG skew
Enabled by programml ng sync Signal output timings
Programmable by raster time
1 or 2 character skew
4 spilt-screens start pOSitions programmable
Two 14-bit Cursor registers
1 or 2 cursors displayed
Display start/end rasters programmable within a row
Programmable by char. clock time
1/16 or 1/32 field rate selectable
DIScretely programmable
Cursor display position
Cursor Control
Discretely programmable (Unit: row)
2/3/4 screens format selectable
Cursor height
Cursor width
Cursor blink
Simultaneous output of 2 cursors
(Only 1 available in DPRAM mode)
Cu rsor display mode
CUDISP skew
OR/EaR mode selectable
1 or 2 character skew
Either one of three modes selectable
Raster
Scanning Mode
Non-interlace mode
Interlace sync mode
Interlace sync and video mode
Memory Format
Memory width set
Memory width programmable wider than dISplay
width (Unit: char.)
Smooth
Scrolling
Display start raster address set
Target screen set
Programmable by char. clock time
Any screen selectable
Raster
Interpolation
Double-size vertical display
Vertical scanning cycle doubled
Same raster address supplied twice
External
Synchronization
Synchronization with external sync Signals
Superimposed display enhabled on other CRT or
TV screens
Interrupt
Request
Interrupt request signal caused by vertical blankIng period or light pen input (Disabled In
DPRAM model
Interrupt request mode programmable
Light Pen
14-bit I ight pen regISter
Light pen raster register
Light pen raster address detected
Refresh
Memory
Addressing
14-bit refresh memory address output
Four 14-bit screen start regs.
(Display start address programmable for each
screen)
Up to 16k words refresh memory accessible
Paging and scrolling enabled for each screen
Three-State
Control
Three-state control on MA and RA
Controlled by TSC pin input
Programmable
Timing Output
Programmable timing signal supplied from access
inhibit pin
In DPRAM mode
•
HITACHI
Hitachi America Ltd_ • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
101
H06345/H 0 6445,------------------------------------------------------------------------
• PIN FUNCTION
Pin No.
1
2
Symbol
Vss
Pin Name
Vss
Inputl
Output
-
Functions
Ground (GNO) pin
RES
Reset
Input
Performs external reset on CRTC-II
RES assertion causes CRTC-II:
(1 ) Clear all the internal counters
(2) Set all the output signals at low
(00-07 are excluded)
(3) Clear registers R30 (Control 1), R31 (Control 21
Status), and R32 (Control 3)
(Other registers are not affected at all)
~ is valid only while lPSTB is low
lPSTB
light Pen Strobe
Input
Informs light pen strobe pulse detection
TSC
Three State
Control
Input
Performs threa-state control on memory end raster
address
MAo-MA,3
Memory Address
0-13
Output
DISPTMG
Display Timing
Output
Indicates a screen display period
3"
4-17
1B
19'
Supplies memory address for periodical memory refresh
CUDISP
Cursor Display
Output
Displays curso~n a screen
Enabled during ISPTMG is high
ACI
Access Inhibit
Output
Supplies
Output
Indicates interru;I~~eqUest to MPU
Enabled during 01 PTMG is low
IRQ
Interrupt Request
-
DPRA~ access inhibit timing (programmable)
20
Vcc
Vcc
21
ClK
Character Clock
Input
Receives character clock timing
22
WR
Write
Input
Inputs write signal from MPU
E
Enable (HD6345)
Input
Enables register readlwrite strobe signals from MPU
RD
Read (HD6445)
Input
Inputs read signal from MPU
23
Power supply (+ 5V) pin
24
RS
Register Select
Input
Selects either of address register or other registers
Address reg. selected when at low, and others at high
Norm,ally, requested to connect to "Ao" of MPU address
bus
25
CS
Chip Select
Input
Performs addressing on CRTC-II
MPU readlwrite upon CRTC-II registers enabled when
CS is low
00-07
Data Bus 0-7
Inputl
Output
Bidrectional bus for data transfer between MPU and CRTC-II
RAo-RA.
Raster Address
0-4
Output
Supplies rater address for selecting raster on character
generator
HSYNC
Horizontal Sync
Output
Supplies horizontal sync signal
EXHSYNC
External
Horizontal Sync
Input
VSYNC
Vertical Sync
Output
EXVSYNC
External
Vertical Sync
Input
26-33
I
34-38
39"
Receives external horizontal sync signal
Supplies vertical sync signal
40'
Receives external vertical sync signal
Note: * -marked pin function is alterable according to the register setting.
_HITACHI
102
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
..
------------------------------------------------------------------------HD6345/HD6445
•
INTERNAL REGISTER ASSIGNMENT
*: Verticil: raster I Horizontal: character
2) . : "0" I. to be .et, .Ince these bit. may be used In the future.
Notes 1)
eH1TACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
103
HD6345/HD6445--------------------------------------------------------------__________
•
FUNCTIONAL DESCRIPTION
Table 1 Programmed Values in Each Register
Register
PROCRAMMABLE SCREEN FORMAT
HOrizontal Total Characters (Nht+1)
HOrizontal DIsplayed Characters (Nhd)
I
(A •
,
} Character
Row
HOrizontal
Retrace
Penod
(Non·
DISplay)
Display Period
RO
Horizontal Total Characters
Nht
Rl
HOrizontal Displayed
Nhd
R2
HOrizontal Sync Position
R3
Sync Width
R4
Vertical Total Rows
Nvt
R5
Vertical Total Adjust
NadJ
R6
Vertical Displayed Rows
Nvd
R7
Vertical Sync Position
Nvsp
R9
Max. Raster Address
R12
Screen 1 Start Address (H)
0
R13
Screen 1 Start Address (L)
0
R30
Control 1
R31
Control 2
R32
Control 3
Nr
0
I Status
0
0
Notes 1) Nhd < Nht. Nvd < Nvt
2) R30. R31. and R32 are cleared by • device reset.
C
Vertical Total AdjUst (NadJ)
Figure 1 CRT Screen Format
Raster Address
N~
\
t-IOrlzontal Dlsplav Period
HOrizontal Rl!trace Period
\ £r 1 Ch.r----------"-'-..:....:.:..---------,
"-------------------,
,
, ,
0
o{:
1
Nhd+ 1
N..
•
{, •
Nhd+1
2N""
2Nhi+1
2N ..
2Nhd+1
>{":,
N
-
:
--
1) Nhd IN.. 11 N...+l
t
Nil(! Nhd+1
NVI Nhd
NVI Nhd+1
Nvt Nhd
NY! Nhd+1
I
:
,
•
•
Nvd Nhd
l
IN_Y
2N ..
N..
-
:
3Nhcl
-1
NvcI Nhcl
:
1
(N ... +IlN.. 1
t
(N ... +llN...-l
I
:
N~c+r+'
1 (N YI +1) Nhd IN.. +l) N...+l
-
•
•
Nvd Nhd
t
Nvd Nhd
(Nvd+ 1)N hcI
1
-
• -
(N w +1)Nhd
(NVI +1}Nhd
*
1
(N vt +1)Nhd
(N vt +2) Nhd
(N .. +2)N ... -l
(NYI+\)-Nhcl
(N .. +l)N".-1
IN.. +2)N ...
•
NIId+N ht
2 N hdf N ht
2NhcI+Nht
,...
---
---
I
1) N.. +N"
t
(N ... -II N.. +N
Nw Nl+Nhl
Nvd Nhd+Nhl
I
I
("",+I)N".
t
NOtt
Nhd+Nht
--
I
Nvd Nhd -1
-
NOtt
• -
2N ..
3Nhcl
1
3Nl'
3N
--
2Nhcl
I
r N -1 Nh (
1 N +1
Nvd Nhd
Nvd Nhd+1
,:
,
I
No< 1
2N .. 1
I I
(Nvd
N
I
:
. t
1
N""
1
°
N""
I
NVI NhcI+Nt..
:
Nyt-Nhd+Nht
1N..+Ui+M",
N +lINh +N~
Valid memory addresses [0 thru (Nvd-1) or 0 thru (Nhd-1)] are shown WIthin the
thick-line square Memory addresses are provided even dUring hOrizontal and vertical
retrace penod ThiS IS an example In the case where the programmed value of start
address register IS 0
Figure 2 Memory Address and Raster Address
•
104
Nhsp
Nvsw, Nhsw
Vertical Retrace Penod
J--- (Non.DlSplay)
Row
Programmed
Values
Characters
\
c
Register Name
No
Figure 1 illustrates the screen format example, in nonInterlace mode, when programming CRTC-II registers as listed
in Table I. Figure 2 shows the relation between memory address
(MAo-MAn), raster address (RAo-RA4) and the location on the
CRT screen.
The timing charts of CRT interface signals are shown in
Figure 3, and those details are partially shown m Figure 4 and 5.
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
Olaracter Clock Time
1:
H
:
eLK
:I:
~.
DtSPTMG
HSYNe
Nt...
~ Horizontal DIsPlaYed Chat'8etelS
L...f1...I""1JL ____________ JUl... __
~
~Horizontal
I
NhdoTe--l
Display
Horizontal SV'nc Position
N.... +1
~
a
:
"I
I
1
2
__________________ ..I1.. _____ _
I
I
Nt-Tc---!
I
Horizontal Timing
I :
I
,-
I
Raster Cycle Tr
= (Nht+ll Te
1
I
~
Raster Cycle
I
o
eLK
i.
-
~:t
""
lii ~
CJ)(')
-
%
Tr
-,
___________________ J
I
ri&i
L.flJlIL _________llIln.. __________ JU1.fL -------------llIlfL----------..nJlJln..-------JlllIlfl---II
II
I:
lEE_ _=
MAo-M~::::_~:::--TITtrrr--:-------::::.::..J '0 EL::::n
:::IXJ ?
RAo-R" ~
0
t
L=:::::-_-::: t
~
~ "~o
t
N",
No.
Nt.
N",
Nt...
N.. I
N",+2
Nild
N... +2
1
~Tr
.1
I
I•
II
Row Cycle Timing
Row Cvcle TI
= (Nr+l)·Tr
Ma" RHterAddrea
I
~~~~r!
i
Row Cycle
TI
•I
_______ I
~
I
I
~---------
~
:.
Row
--t--t-T~
:
I"~I
101,121
I '-
:.
DISPTMG
Venical Display
Nvd·TI
,~i......
~-:.:.. Row
.m:ID.___.J11IC~:=::==:::-___-___-_-_-_·: __::===:::___:::____-::=@IUIl__J__v.rt''''.''''''
I
VSVNC
II,
Frame Cycle TFRM
Number I
i
Horizontal Total Olal'8Ctl'rs
I
nn
,:
q
~
r
.....
t+------fHorizontal Retrace:
I
I
N_Tc
___
r
N_
MAo-M~:::::==:::~=~x=x:=:::=:====::::::=~:==:=:::::---------::_~::::
RAo-R"4l
0
~
~.
~
N...-l
:
.
CD
~
2
'.
§"
....
~
1
-4'
2:
~
/
0 I
~-----------------------
' ...... _... A(See Fig. 4)
..,n
,"_I
I
:
'----
-::~::, Syne
: :
~T_
.r-l~
1.. ':011
'-+--t
,J--k
=::-1 Total
{ i IULlt.r:.-:JUU[~=
"--"''''815ee Fig. 5)
______________________________
Vertical Timing
TFRM : Frame Cvcle
TFRM = (Nvt + ll·TI + Tadi
Tad): Adjustment Period of
Frame Cycle
Tadj = Nod) • Tr
Tvsw: Vertical Sync Pulse Width
Tvsw = Nvsw·Tr
:I:
C
m
w
Horizontal and vertical wavefonns when values shown in Table 1 are set into each register.
CJ1
J:
....
c
m
o(J'I
.j>.
.j>.
Figure 3
~
.j>.
CRTC-II TIming Chart (Non-Interlace mode)
CJ1
HD6345/HD6445,-------------------------------------------------------------------------
.,:f-.~------Vertlcal
,:;-'.~------,
:,
I'
R~-RA.:~O~~1-1~2~1~3_1L-----~.=,-LI~o~I~1-L~2~1~3_1L_____~I~.~,~I~o~I_'~1~2~~3_L1___________
,,
_ _ VertIcal D I 5 P I 8 Y - - - - - - - - - - - - - - - - <•
Row Number
!,
Nvd 2
,
DISPTMG
Retr8CI-------
Nvd 1
n.r-u-u--r:.-_-_-_-_
Nvd
______=_-JLn'--__________________
_=_~-.:_
Figure 4 Vertical Display / Retrace Timing
(A detail drawing of Fig. 3 A)
,
f - : . o _ - - - - - - - - - v e n l c e l Retrace ----------O.~I;-.o----------Vertlca' D l l p 1 a v - - - - - - -
,1
i
Row Number
,,,
,
~ Frame Cycle Adjustment Tlmlng----'
l
T.d,_ ••d,T,
:
Nvt
DISPTMG",'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '
,,
Figure 5 Frame Cycle Adjustment T,ming
(A detail drawing of Fig.3 B)
SCREEN SPLIT
A display screen can be diVIded mto up to four parts in the
horizontal direction. Divided four parts are defined as sphtscreen I, split·screen 2, split-screen 3, and split-screen 4. Splitscreen are controlled by using bits SP. and SP, of the control
I register (R30) and screen start position registers (RI8, R21,
Row
Number
o
1
2
3
4
R24).
Starting positions of each spht-screen are determined in the
number of character row. Split-screen I is the base screen, and
always starts at row 0, whlie the other three split·screens start
at any row except row O. Paging or scrolling (by character) is
performed in each spht·screen independently.
The following IS the example of screen split:
Row,
Number
Display Screen
0
1
2
3
Split·Screen 1
Split-Screen 1
5
6
7
8
Split-Screen 4
Programmed Value of Screen 2 Start Position Register
Register
Programmed Value of Screen 4 Start Position Register'" 6
= Programmed Value of Screen 3 St8rt POSition
Figure 6-B Screen Split (Example 2)
Split·Screen 2
Row
Number
Display Screen
o
Spilt-Screen 1
4
5
6
7
8
Display Screen
Split-Screen 3
1
2
3
Split-Screen 4
Programmed Value of Screen 2 Start POSition Register == 1
Programmed Value of Screen 3 Start POSition Register"" 3
Programmed Value of Screen 4 Start POSition Register == 7
4
5
6
Split·Screen 4
7
Split·Screen 2
8
F'gure 6-A Screen Split (Example 1 )
When the same value IS programmed mto more than one screen
start pOSition registers, split·screens corresponding to these registers are not displayed.
Programmed Value of Screen 2 Start Position Register = 6
Programmed Value of Screen 3 Start POSition Register G8
Programmed Value of Screen 4 Start POSition Register = 4
Figure 6-C Screen Split (Example 3)
$
106
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------------------HD6345/HD6445
Raster Add ress
HOrizontal Display Period
Row Number
\ r'1 Char
0
oC,
"'
..
1
.
I
C,
o
0
1
Nhd
Nhd+1
Ns2
,
.
~
Ns2+1
\
HOrizontal Retrace Period
---
/r--------------------~
Nhd·1
Nhd
I
Nhd·1
Nhd
2Nhd·1
2Nhd
I
Nht
-
Nhd+Nht
Spilt-Screen 2
Ns2+Nhd
Ns2+Nht
+1
I
:
I
Ns4
,
I
Ns4+Nhd
Ns4+1
: Ns4+Nhd Ns4+Nhd
+1
Ns4+
Nhd+Nht
,
:
+
~~~~~~It
--
·Nhd
, Ns4+INvt
-Nvd+21
1
Spilt-Screen 1
Nht
'Nhd
Figure 7 Memory Address and Raster Address
In
Ns2'
Start Address
of Spllt-Screen2
Ns4
Start Address
of Spllt-Screen4
Ns4+
INvt-N vd+21
·Nh d+Nht
Split·Screens
3) Cursor Widths
The Widths of the cursor I and the cursor 2 can be speci·
fied mdependentiy in units of characters by using the
cursor width registers (R38, R39), and bits CW I and CW z
of the control 3 register (R32), If the cursor width
extends over the following row, the cursor m the follow·
ing row is not displayed
4) Cursor Blink
Cursor display, non·display, and bhnk rate can be controlled by using bits B I and PI of the cursor I start
register (RIO), and bits Bz and Pz of the cursor 2 start
register (R34),
5) Cursor Display Mode
When the cursor I and the cursor 2 are overlapped on the
screen, cursor display mode m the overlapped area can
be specified by the eM bit of the control 3 register (R32),
as shown in Figure 9,
CURSOR CONTROL
The HD6345/HD6445 can display two separate cursors (cursor I, cursor 2) simultaneously on the screen. These two cursors
are controlled independently. The cursor I is always valid, while
the cursor 2 becomes valid by setting the C, bit of the control 3
register (R32), In the DPRAM mode, the cursor 2 cannot be
displayed,
The HD6345/HD6445 controls cursors as follows:
I) Starting Position
Starting position is controlled by using the cursor I
address registers (RI4, RI5), and the cursor 2 address
registers (R36, R37),
2) Cursor Heights
The heights of the cursor I and the cursor 2 can be
specified independently m units of rasters by using the
cursor start registers (RIO, R34), and the cursor enC
registers (RII R35)
Display Screen
HITACHI
~ursorl
Cursor 2
+
~
CRTe-II
•
i
,
----<10
_
Cu rsor 2 Start Raster
Cu rsor 2 End Raster
Cursor Height
Curso, Width
Figure 8 Cursors
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
107
i
HD6345/HD6445----------------------------------------------------------------------------
OR MODE ICM=ll
EOR MODE ICM=O)
DIsplay Screen
DIsplay Screen
Cursor 1
Cursor 1
Cursor 2
Cursor 2
"EOR" of the cursor 1
and the cursor 2
"OR" of the cursor 1
and the cursor 2
Figure 9 Cursor Display Mode
RASTER SCANNING MODE
The HD6345/HD6445 performs a character display in three
types of raster scanning modes: non-interlace mode, interlace
sync mode, and interlace sync and video mode. The bits V and S of
the interlace mode and skew register (RS) control these modes.
to the top of the raster line is designated as 'one field'. In the
non·interlace mode, one field configures a single frame (Figure
10). In the interlace sync mode and the interlace sync and video
mode, a single frame period is shared between two alternating,
even and odd, fields (Figure 10).
The period that the raster scans across a screen and returns
Retrace
even fIeld
odd field
Non·1 nterlaced Scanning
Interlaced Scanning
Figure 10 Raster Scanning
In the Interlace sync mode, the scanning lines m the odd
field are placed downward by 1/2 raster line space from those
in the even field because of the dIfference in HSYNC/VSYNC
phases between two alternating fields.
In the mterlace sync and VIdeo mode, the placement of the
scanning lInes IS the same as 10 the interlace sync mode. However, the alternatmg even and odd raster lines are displayed in
the alternatIng even and odd fields. For a given number of
rasters per character, thIs mode allows twice as many characters
to be dIsplayed In the vertIcal direction as the non-interlace and
the interlace sync modes Note that the raster address is supplied 10 the different way accordIng to the total number of rasters
In a row, even or odd, as shown in Table 2.
Mode
Table 2 Start Raster Address for Each Row
(In interlace sync and video mode)
Total Number
of Rasters
In a Row
~
Even
Odd
\It
I
Even Char. Row'
Odd Char. Row'
The start row address
15
Even Field
Odd Field
Even address
Odd address
Even address
Odd address
Odd address
Even address
assumed to be "0" (even).
~HITACHI
108
Hitachi America ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------------------IHD6345/HD6445
Figure 11 illustrates the raster scanning example in each mode.
Raster Address
Raster Address
0---------------
----------------0
•
••
•
•
•
•••••••••
•
•
•
•
•
•
•
•
2
3
4
6
8
9
A
l---i.-----------i..._
--1
Row 0
[.I;KZZZ
_ 5
6---i.[~--'----------_H..._
-~ ~--------6
7 ~.----~t--
r--------
-
--- -----
-- 8
-.., r--------
-- 9
8 -H.._--------__-
Interlace Sync Mode
Raster Address
o
2
2
6
---------------
8
-3
RowO
.....
--------
-,
6
8
~
--------
....
-1
~--------
-- 3
~
-- 5
---------
-
RowO
7
8---i.--------~._
~-9
---------
1
----------------0
--------..., r-2
t-- 1
-
-9
A-----------------
2----1. .---~__
4
Raster Address
~--------
6~t_---~t_
~-7
o ---------------------
-..,
4
-5
A------------------- ------------B
-~
7
A----------------B------------------------------8
Raster Address
--------
RowO
9-H.._--------__-
0------------------ ----- --1
.....
-- 1
3 ~__- - - - - - - - . -~ - - - - - - - -3
4---i__--------~5 --'...
~ H-.-H:;..-H;..:-H--.-H_-~..._-- 4
Non-I nterlace Mode
4
------ --
2 ---4__- - - - - - - -__--1 ---------1 t-- 2
B
Aaster Address
Raster Address
Raster Address
0
3~t_---~t_
3
5
5 -- ~..;;:_;,;:~;.-..;;.
-- 4
r~-~.:-:..:-:.::""-
r-6
---------
-- 8
Row 1
Row 1
7
-- 7
--1
9---i.--------~._
--------- - 9
A------------------------------- B
---------------A
-~
Interlace Sync and Video Mode
(odd rasters per row)
Interlace Sync and Video Mode
(even rasters per row)
Note: Refer to Table 2 for raster address output
In the interlace sync and video mode.
even field
odd field
Figure 11
Raster Scanning Example
_HITACHI
Hitachi America Ltd_ • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
------
~-
- - --------
109
I
oCJ)
~
~
o
w
"'"
(Jl
(1) Interlace Sync Mod!!
I
o
Frame--------,----------- - -- - - - - - - - - - ' - - - - - - - - - - - - - - - Even Field
:
~:-
~
3Cl)
:
~
Row#1 ---:
-x::i!Ct!:X::i:X
"$YMC~T'-1
=.
»
.
-~;-
Row#O
~""-AA.~
::I:
'
Row#Nvsp,
~
: Adjust
-
:
I
'-- Row#Nvt --:- Ras~W#O - - - Row#1
-:x!EX -:c:n::cc -~i·p.=:j
"
~
CJ)
Odd Field - - - - - - - - - - - "
o:.ox
-~...
l~o..""'YR"",
----:
~
Row#Nvsp
'
,
~--
-----i
:
Adjust
:
Row#Nvt - : - Raster-:
:x::EX: - tI:x:J:x
XIX .... XI::XIX:
JG:X:E--,[""
:b:xrr ~fi
~ ~
:
--~~-=.
~ J;
f'
,
:
--;;'r:=-==;
,
:
Even; Ad.ust '
/.
J;
:
:
.
.
- :p:::rrx: ~
~;
",
•
!
:
ROwHNv~ster~RowH0A ~W#1*1ff :.-RoW#NvsP,-;iff.,
- :h:rrx
_moo· .f::::fu:rr ~,2' :+'0
-~~-±:un: "b:
--< " ~ ••••••--;
>--.
,
-e'
-
Z
:
~
:
:
Adjust
:
-f:5
"
f
Adjust ,
:Row#N~~l;-J+l Raster---;_z
:x::IJcrX 1::::X:Dc
.
E
.
;
,
, Adjust ,
~RoW#N~~~ Raster ~
:x:n::nc 1:::Px,JE$' •
~~~------------------~
Figure 12 Raster Scanning Timing
:
,--.-.-Row#Nvsp~
:--Row#Nvt~1
'1' Raster---:
,
~z'
~
Z_l~
nn--..L.....L
~- __ n_~
,Row#Nvsp (
:-2~+1
•
Z
--~
-- -::c:x-:x:rr:zx: ~ T. r==.::=;'
:.
t
~
: :
~[~I Raster-:
_Row#O-I-.·-;~_Row#1_.I
••
1
~.~ _ _ 12
z_,
~
~
Z -2
-x:::::x:u::
0'
r - - - 1 : ;,
:ROw#NVSe~'2 :--Row#Nvt .ti'1+zRaster::-;-Row#"'~,~Row#1~.2
:IT,GX
..:Ex:-XECrr nn~ £J6::x::rru~
~
~;'~cl:
:x:D2X
~DurnnJy_.':
I·
: : .
Adjust , 1 :
Row#Nvt
' :
"
/ Even : Adjust
,. Even"
27
ZNH,Z
:
::x::IX2X
-~~.~ ,
;
Nvt = Even Nvsp = Even
,
':
'
._,-Row#O~Row#l0"ff'l
."~:
I.
~
'r---1
f-.. -
-:-RowHO
Adjust
' R #0
'
'Row#Nvsp,
"
_RoW#Nvt.-.:::rl-I~1 Ras~ -~-1--Row#1~1'
1""'1
:--ROW#N.v.t~I' Raster--
Nvt = Odd Nvsp ~ Odd
Odd:
"
, Row#N:SP
:
~I~
~lh~
:..--.
-rIO.'
:-...-Row#O
,
, - >2
.-,.['
-:t.~i'l:'
...~:
I
!
"'"'""
(Jl
----------------------------------------------------------------------------HD6345/HD6445
MEMORY WIDTH SETTING
The offset value which is the difference between the display
screen width and the display memory width m the honzontal
direction can be specified in umts of characters. (See Fig. 13)
Scrolling in any direction can be accompllshed m umts of
characters, by setting the display memory width (horizontal
direction) and the offset value, and by changmg the start addresses of spilt-screens 1-4. This IS performed by the memory
width offset register (R33) and the MW bit of the control 3
register (R32).
HITACHI
HITACHI
HITACHI
CRTC-II
CRTC-I1
CRTC-I1
HITACHI
HITACHI
HITACHI
CRTC-I1
CRTC-I1
CRTC-I1
HITACHI
HITACHI
HITACHI
CRTC-I1
CRTC-I1
CRTC-I1
DISplay Screen
HITACHI
HITACHI
HITACHI
CRTC-I1
CRTC-I1
CRTC-II
Change of Start Address
Display Screen
Width
HITACHI
HITACHI
HITACHI
CRTC-I1
CRTC-I1
CRTC-I1
Offset Value
Figure 13 Memory Width
HITACHI
HITACHI
HITACHI
CRTC-I1
CRTC-I1
CRTC-I1
HITACHI
HITACHI
HITACHI
CRTC-I1
CRTC-I1
CRTC-I1
HITACHI
HITACHI
HITACHI
CRTC-I1
CRTC-I1
CRTC-I1
01 spl ay Screen
Figure 14 Scrolling by Memory Width Setting
Raster Address
\
Row Number
~C,
~
~
1
,r
HOrizontal Display Penod
- h------=--=....:.::-=....:::::..:....:...::.:..:.:=------....\
1- C
ar.
0
1
Nhd-l
,
I
0
•
•
•
•
1
C,
Nhd
+NOF
Nhd+NoF
+1
/
HOrizontal Retrace Penod
,
Nhd
Nhd-1
Nhd
2(N",,+NoFl
2(Nhd
+NOFI
-I
t
---
\
Nht
I
Nht
Nhd+NOF
+Nht
~
~
o
j
~
~
:,
j
(N v d-lI
(N ... -l1
(N",,+NoF)
(Nhd+NOFI
+N.
N~
N~
,
(Nhd+NoFI
(Nhd+NOFI
+N".
~
N••
IN,,,,+No.oI
,,
(N .... +l)
(NIId+NoFI
(N ...,+ll
(Nhd+NQfl
NOF
+N.
offset value written
In
the memory Width offset register (R23)
Figure 15 Memory Address and Raster Address in Memory Width Setting
~HITACHI
Hitachi America Ltd_ • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
111
HD6345/HD6445----------------------------------------------------________________________
SMOOTH SCROLLING
Smooth scrolling in the vertical direction can be accomplished by changmg the start raster address in a character row. Whether scrolling in each split-screen is available or not can be
selected. Selected split-screens scroll m the same way up to
four spht-screens simultaneously.
•1••••1••
•• ••
RA=O
Row Number N
3
4
Smooth scrolling is performed by bits SSt -SS. of the control 2 regIster (R3l), and the smooth scrolling register (R29).
Smooth scrolling can be used in the non-interlace mode and
the interlace sync mode, but not in the interlace sync and video
mode.
RA=2
4
Row Number N
• •
RA=O
•••
•
•••
Data In the
follOWing row
(R29) Programmed value = 0
•••••••
I I
• •
(R29) Programmed value = 2
Figure 16 Smooth Scrolling
Raster Address
Row Number-
HOrizontal Retrace Penod
HOrizontal Display Penod
r-~~------------------------~/r--------------1 Char
Row
Number
o{
I{
o{:§EEE'~~.~Nh~d~
Raster
*l
Nr
Address
o
g
0
1
Nhd
•
Nhd-'
Nhd
17hd+,
~I\! ~~----¥----t----------------~----i-----t-----_t----_l
Ie
N,
0
1
2
N,
0
1
2
N,
1 I 2Nhd/
~
N2r~
2Nhd
+1
N.,
/
0
".{ NOl
(Nvd·' )
• Nhd
-1
: ··h
Nvd Nhd
"t>
0
2
~
~
]
z
~
~
>
lNv~+11
N""
N,
B
N'd,-l
NOdi
+1
I
(N",,+l) N""
(N)'d+2) NM
(Nvd+2)·Nhd+Nht
Figure 17 Memory Address and Raster Address in Smooth Scrolling (R29=2)
$
112
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------------------------IHD6345/HD6445
+
r
HITACHI
CAT
Spllt-Screen 1
CONTROLLER
r------;CmRTI~T~~M~r--------~
CONTROLLER
Spilt-Screen 2
*
Figure 18 Smooth Scrolling In the Spirt-Screens
(Spilt-screen 2 IS scrolling.)
RASTER INTERPOLATION
In raster interpolation, the raster address IS Incremented
every two rasters, thus the displayed image is doubled in the
vertical direction. The vertical scanning cycle is also doubled.
Raster interpolation is performed by the RI bit of the control 2
register (R3I) This function can be used In the non-Interlace
mode and the interlace sync mode, but not In the Interlace sync
and video mode.
Figure 19 is an example of display With raster interpolation.
Raster Address
--------i_-
o .......------........,Aaste r Address
O .....
lH
Repeated Raster
Address
1
>
2
3
I
4
4
Normal Scanning
Raster Interpolation Scanning
Figure 19 Raster Interpolation
Normal Scanning
~~~~~~s
~
Raster :VCle Tr
1~---......,Xr-------.X,..--3--,X,.----4---
{
Raster Interpolalron
Scanning
===x_______
o______~x~
______~____~x~______
Figure 20 Raster Address Output and Raster Interpolation
•
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
113
HD6345/HD6445i----------------------------------------------------------------------------(I) Phase of master CRTC-I1 clock matches with slave
EXTERNAL SYNCHRONIZATION
External synchronization (EX sync) has master-slave mode
and TV sync mode. The EX sync mode is controlled by bits VE,
VS, and TV of the control 1 register (R30).
Master-slave mode is used to synchronize slave CRTC-I1's
with a master CRTC-I1 by VSYNC of a master CRTC-I1. When
superimposing a master screen with slave screens on the same
CRT, clocks of a master and slave CRTC-I1's can operate in
different frequency on conditions shown below.
CRTC-I1 clock at rising edge of VSYNC.
(2)Both master and slave CRTC-I1's have the same horizontal/vertical scanning cycle.
In the interlace sync mode and interlace sync and video mode,
the control I register must be set as to provide VSYNC output in
odd fields of master CRTC-I1.
Figure 21 illustrates the system configuration.
MPU
Figure 21
Master·Slave Mode
TV sync mode is used to synchronize the CRTC-I1 with the
HSYNC and VSYNC signals of a TV's video signal.
In the TV sync mode, VSYNCjEXVSYNC and HSYNCj
EXHSYNC pins function as input pins. The length of horizont·
al back porch IS specified by the bits 0-3 of the sync width
register (R3) and determines the dIsplay positIOn in the horizontal direction.
In the interlace sync and video mode, the TV sync mode cannot be used.
In the IV sync mode, when performing slave CRIC raster
interpolation, interlace sync mode or interlace sync and video
mode must not be set in a master CRIC; otherwise the screen to
move up and down by one raster.
FIgure 22 illustrates the system configuration.
TV
MPU
Figure 22 TV Sync Mode
•
114
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------------------HD6345/HD6445
External sync is valid on the conditions shown in Table 3.
Table 3 External Sync
~e
Sync Mode
Non·lnterlace
Master Mode
Master·Slave Mode
TV Sync Mode
(V: valid, I. invalid, -: program Inhibited)
I nterlace Sync Mode
I nterlace Sync
and Video Mode
Non·lnterlace Mode
V
I
I
Interlace Sync Mode
I
V
V
Interlace Sync and
Video Mode
I
V
V
Non·lnterlace Mode
V
-
Interlace Sync Mode
V
-
-
Interlace Sync and
Video Mode
V
-
-
Note) Slave CRTCs are always non-Interlace mode
In
TV sync mode.
INTERRUPT REQUEST
An interrupt request SIgnal to the MPU is output 10 the timing shown in FIgure 23. An interrupt request IS generated by the
vertical blanking period, or the light pen input.
Reading the status register (R31) clears an interrupt request
signal. Thus, IfMPU does not read the status register (R31) when
the mterrupt request IS generated, an interrupt request sIgnal is
output durmg the horizontal and vertical retrace period.
In the DPRAM mode, an mterrupt request sIgnal is not output.
ThIs functIOn IS controlled by usmg blls IB and IL of the
cantrall regIster (R30).
/t Retrace Penod
Display Penod
11---_
--If--Iul
_T
~
DISPTMG--------.,U
I
CUDISP
---J~--7~
t
Cursor
1
I
I
I
Status Read
---------------------~~
Figure 23
I nterrupt Request Signal
When an Interrupt request
occurs dUring the display
penod "T", an Interrupt
request Signal IS output
dUring the blanking penod.
An Interrupt request Signal
cleared by reading the status
regISter (R31)
IS
Interrupt Timing
_HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
115
HD6345/HD6445--------------------------------------------------______________________
By using this function, multiplexer (MPX) which selects ad·
dress lines from MPU and CRTC-II for refresh memory is not
needed.
THREE·STATE CONTROL OF MA/RA
Memory address (MA) and raster address (RA) outputs can
be three·stated, using the TSC input pin. Three·state control is
enabled by setting the TC bit of the control 3 register (R32).
ADDRESS BUS
MPU
DATA BUS
GBUFFER
!
--
MPX
,...
I
L_
LPSTB
-.,
I-,j
REFRESH
MEMORY
MA.IRA)
CRTC
'----Note. When uSing DRAM as refresh memor y, DRAM refresh Circuit is needed.
Figure 24 Three·State Control
DPRAM MODE
When the DPRAM mode is selected, the HD6345/HD6445
generates a programmable timing signal from the access inhibit
pin. This signal, shown in Figure 25 as access inhibit period,
provides the timing for the MPU to access to dual-port memory.
ClK
~-----,
,
1
1
=:x
r~~~~~~
1
1
1
1
I
I
I
(
__
i
Cursor'
I
1 The Programmed Value of
1··
:
I
I
I
::
The AI Bit Iblt 7) of the
Status RegISter I R31 )
~1 Char=!
1
(BI
Display Pertod
i
I
I
. - - - - - - - - - - - 1 1I
IAI
..
I
1
------------,j.I
1
L..
: :
'
I
I
1
~ 1 Char
1
Figure 25 DPRAM Mode Output Timing
•
I
1
1
o The AI bit mdlcates the access Inhibit period (A)
and the first character penod (8) In each raster
116
I
1
=1
!
!:
~~I
l : :
: : I :'
I
~1~-----I~th-e-C-u-rs-o-r-2-W-'-dt-h-R-e~9-IS-te-r-IR-3-9-)__
1
1
1
1
FAccess Inhibit Period
1
:
I
Retrace Penod
I
I
t=
¥
X
1
1
Period
----'l<--,
I
I,
X
X
1
I
iI
I1
1
1
1
I
I
I
CUDI.SP
I
I
I
1 - - - - Display
DISPTMG
I
1
I
1
MA
In the DPRAM mode, an interrupt request signal is not out·
put, and the cursor 2 is not displayed.
This timing signal is available by using the DR bit of the
control 3 register (R32), and the cursor 2 width register (R39).
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
(BI
L
------------------------------------------------------------------------HD6345/HD6445
•
INTERNAL REGISTERS
H06345/H06445 has one address register (AR) and forty
data registers (RO - R39). One register out of 40 data registers IS
selected by writing the address number of the register mto the
address register. Then the MPU can transfer data to or from the
selected data register
Write 0 to unused data bits (appear as r=J in the register
table), since these bits are reserved for the future extensIOns.
pulse Width IS programmed from ]·to·16 raster times m the
hlgh·order four bits When 0 IS programmed m the hlgh·order
four bitS, a vertical sync pulse Width IS 16 raster times (16H),
Table 4 HOrizontal Sync Pulse Width
HSW
o
o
o
o
ADDRESS REGISTER (ARI
This register specifies the address number of the data register
to be accessed. When both RS and CS are at low level, thiS
register IS selected. Programming the data from 40 to 63 produces no result.
o
o
0
0
2'
2'
0
0
0
1
0
2
1
o
0
0
3
4
o
o
o
0
1
5
0
6
1
7
o
0
o
0
o
o
1
0
0
0
0
0
CH
HORIZONTAL SYNC POSITION REGISTER (R21'
Table 5 Vertical Sync Pulse Width
2'
2'
2'
0
0
0
0
0
0
0
1
0
0
0
0
Pulse Width
16
2
0
1
3
4
0
0
0
0
0
1
5
6
8
9
10
11
12
13
14
15
1
1
1
0
1
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
0
H
H Raster Time
VERTICAL TOTAL ROWS REGISTER (R4)
SYNC WIDTH REGISTER (R3)
Data Bit
VSW
2'
0
0
This register is used to program honzontal sync position as a
multiple of the character clock time. The programmed value IS
the character number of horizontal sync pOSItion, mmuts one.
Any number equal to or less than the horizontal total characters register value (RO) can be programmed. When the pro·
grammed value of this register is increased, the display pOSItion
on the screen is shifted to the left. When the programmed value
is decreased, the display position is shifted to the right. Thus
the optimum horizontal position can be determined.
8
9
10
11
12
13
14
15
Character Clock Time
HORIZONTAL DISPLAYED CHARACTERS REGISTER (R11
This register specifies the number of displayed characters per
row. Any number less than the total number of characters can
be programmed mto this register.
Not Used
1 CH
1
HORIZONTAL TOTAL CHARACTERS REGISTER (ROI
This register determines the horizontal scanning cycle. The
programmed value is the total number of displayed and non·
displayed characters per raster, minus one.
In the interlace sync mode, the programmed value, Nht,
must be odd.
Pulse Width
R/w
I Program Unit I R/W I
I H: Character I W I
7 I 6 I 5 I 4 I 3 I 2 I 1 I 0
Wv, IWv, IWv, IWvo IWh, IWh, IWh, IWho I V' Raster
This register determines the widths of both honzontal sync
pulse and vertical sync pulse. The horizontal sync pulse Width is
programmed from I-to-15 character clock times in the low·
order four bits. Zero cannot be programmed. The vertical sync
Nvt INa. of Char, Rows - 1)
W
This register determmes the vertical scannmg cycle. The programmed value is the total number of character rows m a field,
minus one.
_HITACHI'
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
117
HD6345/HD6445,---------------------------------------------------------------------------VERTICAL TOTAL ADJUST REGISTER (R5)
Data Bit
I 6 I 5
7
J
- 1- 1- 1
1
C,
Program Unit
4/ 3 / 2 / 1 / 0 /
Nadl (No, of Rastersl
1
RNI
j
I I
1
w
Raster
CUDISP
No skew
One character skew
Two character skew
Not available
Co
0
0
0
0
This register determines the number of additional rasters to
adjust total number of rasters in a field, The optimum number
from O-to-31 can be programmed, Thus fine adjustment of
vertical scanning cycle is performed,
VERTICAL DISPLAYED ROWS REGISTER (R6)
ClK
1 Program Unit J RNI
Data Bit
7 / 6 / 5 / 4 / 3 / 2 I 1 / 0
Nvd (DISplayed Char, Rowsl
i
IW
Row
CUDISP
[ ~---------
;------1 One Character Skew
This register speCifies the number of displayed character rows
in each field, Any number less than the total number of character rows can be programmed into this register.
DISPTMG
/ Program Unit / RNI
16 1 5 14 1 3 1 2 1 1 1 0
Nvsp (Vertical Sync Position - 11
i
No Skew
lone Character ~~~~----~
[
VERTICAL SYNC POSITION REGISTER (R7)
Data Bit
ILn ___ nn
Skew
1
Iw I
Row
rs-_--' -o~~cj,aracte~
"-s..;.ke.,;,w'--__
This register is used to program vertical sync position on the
screen as a multiple of the character row time, The programmed
value is the character number of vertical sync position, minu,s
one, Any number equal to or less than the vertical total rowS'
register value (R4) can be programmed, When the programmed
value of this register is increased, the display position is shifted
up, When the programmed value is decreased, the display position is shifted down, Thus the optimum vertical position can be
determined,
Figure 26 D ISPTMG and CUDISP (One character skew)
MAXIMUM RASTER ADDRESS REGISTER (R9)
This register determines the number of rasters per character
row. When n means the number of rasters, the programmed value
is as follows:
non-interlace mode, interlace sync mode: n - 1
• interlace sync and video mode
:n - 2
INTERLACE MODE AND SKEW REGISTER (R8)
Data Bit
1 Program
Unit 1RNI 1
II
w
7161514131211101
C, 1Co 10, 1Do j - 1 - 1 vis 1
This register selects the raster scanning mode and controls
the skew (delay) of CUDISP and DISPTMG outputs,
•
Raster Scanning Mode (V, S)
The low-order two bits select the raster scanning mode,
v
o
o
S
o
1
o
1
o
Number of rasters
1
Programmed value : Nr
: 5
=4
2----
Raster
Address
0-------
- - - . even fIeld
----------- ....
--------- : odd field
Number of rasters
Programmed val ue . Nr = 4
3 ------
4----In the interlace sync mode, a half number of rasters per row
mInUS one should be programmed.
(3) Interlace sync and video mode
Raster
Address
0---------
- - - - - . even field
2 ------------- 1} Row
No skew
One character skew
Two character skew
Not available
4
----------- 3
------- : odd fteld
,
Number of resters . 5
Progremmed velue : Nr = 3
In the interlace sync and video mode, the sum of rasters per
row minus two should be programmed .
•
118
0-------
4------
Raster Scanning Mode
Non-interlace mode
Interlace sync mode
Non-Interlace mode
Interlace sync and video mode
DISPTMG
0
Raster
Address
(2) Interlace sync mode
• Skew (C" Co, D" Do)
The bits 0,/0 0 and C ,/Co specify the skew of DISPTMG
and CUDISP outputs, respectively, Skew control makes these
output timings match with the serial video signals by delaying
these outputs as programmed, in order to assure the access time
to refresh memory and character generator.
o
o
(1) Non-Interlace mode
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------------------HD6345/HD6445
CURSOR 1 START REGISTER (Rl0)
Data Bit
Program Unit
AIW
7 16151 4 131 2 1 1 10
Nes I (Aaster Addressl
B,
Raster
W
- I p, I
LIGHT PEN REGISTER (H, L) (R16, R17)
(R16)
Program Unit
Data BIt
7 161514131211101
Memory Address (HI
I
TIus register determmes the start raster address and selects
the cursor blink mode for the cursor 1. The low-order five bits
detennines the start raster address. BIts B, and P I select the
cursor bhnk mode.
- I- I
PI
o
o
0
1
No blink
o
Blink, 1/16 field rate
Blink, 1/32 field rate
.1 Program Unit
Data Bit
7 1615141312111°J
Memory Address (LI
OFF
SCREEN 2 START POSITION REGISTER (R1B)
1/32 Field Rate
Data Bit
7 16151413121
Start Aow - 1
CURSOR 1 END REGISTER (Rll)
1 Program UnIt J AIWJ
Daata Bit
716151413121110
Neel (Aaster Address)
- I- I- I
I
I
~~
Iwl
This register determines the end raster address for the cursor·
I.
Data Bit
Program Unit
7 1 6 1 5 1 4 1 3 1 2 1 1 10
Memory Address (H)
Address
J 1
15 1 4 1 3
2
Memory Address ( L)
1
l0
I
I
Aow
Data BIt
Program Unit
Memory
- I- I
AIW
AIW
AIW
Address
AIW
AIW
(R201
Data BIt
I Program UnIt IAIW I
J
0 1
716151413121110
Memory Address (HI
(R13)
Data Bit
I
ThIs regJster determmes the start row of the spht·screen 2.
The programmed value is the start row number mmus one.
If the split·screen 3 (or 4) start positIOn register (R2I (or
R24» has already been programmed wllh the identical data,
both of the spht·screens 2 and 3 (or 4) will be disabled.
AIW
Memory
- I- I
I Program Unit
1
SCREEN 2 START ADDRESS REGISTER (H, L) (19, R20)
(RIg)
SCREEN 1 START ADDRESS REGISTER (H, L) (R12, R13)
(R12)
7 1 6
A
These regIsters store the hght pen detectIon address. The
high-order two bIts of Rl6 are always read as 0 s
Note that the stored address will be different from the actual
address due to the following delays: address output delay, video
sIgnal output delay, hght pen detection to LPSTB delay, and
LPSTB to mternal recognition delay. The relations between the
LPSTB mput and the memory address, raster address are shown
m Figures 32, 33 in electrIcal charactenstlcs.
Blmk Rate
1/16 or
AIW
I
No cursor
ON
A
I
(R17)
Cursor Blink Mode
BI
AIW
Memory
Address
IAIW
I
I
These regIsters determine the start memory address for the
split-screen 1 dIsplay. Paging or scrolling is enabled by renewmg
these registers. The high·order two bits of Rl2 are always read
as as.
7
I6 I
I
I
Program Unit
I
5
4
3
2
Memory Address (L)
I
·1
I
0
Memory
Address
AIW
AIW
These registers determme the start memory address for the
split-screen 2 dIsplay. Paging or scrolhng is enabled by renewing
these registers. The hlgh·order two bits of Rl9 are always read
as as.
SCREEN 3 START POSITION REGISTER (R21)
CURSOR 1 ADDRESS REGISTER (H, L) (R14, R15)
(R14)
Data Bit
I
7161514131211[oJ
Memory Address (HI
- I- I
I
I
Program Unltl AIW
Memory
Address
I
AIW
(R15)
Data BIt
7 J61514131211Lo
Memory Address (LI
Program Unit
Memory
Address
AIW
AIW
Data Bit
1716[51413121110
Start Aow - 1
I
Program Unit
I AIW
Aow
I AIW
This regIster determines the start row of the split-screen 3.
The programmed value is the start row number minus one.
If the split-screen 2 (or 4) start position register (R18 (or
R24» has already been programmed with the identical data,
both of the spht-screens 3 and 2 (or 4) WIll be dIsabled.
These registers determine the cursor 1 display memory address. The high-order two bits of R14 are always read as as.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (40B) 435-8300
119
HD6345/HD6445---------------------------------------------------------------------------SCREEN 3 START ADDRESS REGISTER (H, L) (R22, R23)
(R22)
I Program Unit
Data Bit
7 16151413121'101 Memory
Memory Address (HI
- I- I
I Address
R/W
R/w
(R231
I Program Unit IR/W I
I 0 J Memory IR/W I
I Address
I
Data Bit
7
I6 I
I
I
I
5
4
3
2
Memory Address (LI
I
These registers determine the start memory address for the
split-screen 3 display. Paging or scrolling is enabled by renewing
these registers. The high-order two bits of R22 are always read
as Os.
SCREEN 4 START POSITION RECISTER (R24)
Data Bit
Program Unit
R/W
7 161 5 1 4 1 3 1 2 1'10
Row
R/w
Start Row - ,
This register determmes the start row of the split-screen 4.
The programmed value is the start row number minus one.
If the split-screen 2 (or 3) start position register (R18 (or
R21)) has already been programmed with the identical data,
both of the split-screens 4 and 2 (or 3) will be disabled.
SCREEN 4 START ADDRESS REGISTER (H, L) (R25, R26)
(R25)
Data Bit
Program Unit
71615141 3 1 2 1'10
Memory
-
I -
I
I
I
R/W
R/W
Address
Memory Address (HI
(R26)
J Program Unit 1R/W
Data Bit
7
6
5 I 4 I 3 I 2
Memory Address ( LI
I
I
0
I
I
Memory
Address
Program Unit
Raster
Data Bit
I Program Unit
0
J
J
R/W
-
R
This register stores the light pen detectIOn raster address and
the detection period. The raster address is detected and stored
into this register when the LPSTB mput is asserted. The OP(bit 7)
mdicates the peflod in which the light pen strobe IS detected.
"OP = I" is stored when the LPSTB is asserted during the display period, and "OP = 0" is stored when lt occurs during the
blanking period.
SMOOTH SCROLLING REGISTER (R29)
I
Data Bit
j
171615141312 l'jOJ
I - 1 - 1 - 1 Nss (Raster Addressl J
Program Unit
~~
R/W
R/w
This register determmes the start raster address within a row.
By renewing this register, smooth scrolling is provided for the
screen specified by the bits SSI - SS. of the control 2 register.
The programmable number IS equal to or less than the maximum
raster address register value (R9).
ThiS register is vahd only in the non-mterlace mode and the
interlace sync mode.
Data Bit
IR/W I
I W
,
716151413121 1
Raster Address
DP I - I - I
CONTROL 1 REGISTER (R30)
VERTICAL SYNC POSITION ADJUST REGISTER (R27)
Data Bit
LIGHT PEN RASTER REGISTER (R28)
IR/W
These registers determine the start memory address for the
split-screen 4 display. Paging or scrolling is enabled by renewing
these registers. The high-order two bits of R25 are always read
as Os.
7161514131 2 1'1 0
- I - I - I Nvad (No. of Rastersl
This register performs a fine adjustment on the vertical sync
signal output in units of rasters. The VSYNC signal is supplied
after the delay of Nvad rasters. Nvad is equal to or less than the
maximum raster address register value (R9).
This register IS enabled when "SY (bit 3) = I" is set into the
control I register (R30). If an adjustment is not required, the
SY bit or this register (R27) is requested to be set as O.
716151413121'10
VE I VS I IB IlL I Sy I TV ISP,JSPo
Program Unit
R/W
w
-
ThiS register controls the followmg by the corresponding
bits. A device reset clears all bits of this register.
VE, VS, TV
External synchronization control
lB, IL
Interrupt control
SY
Vertical sync position adjust control
SP I , SP 0
Screen spht control
!
Raster Address _5~",-_~
Vertical Sync Position (
Fine Adjustment
-+_________,:J--------+--------~~
_ _____
SY=o
___
SY=1 (R27=31
Figure 27
Vertical Sync POSition (Vertical Sync Pulse Width = 6)
•
120
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------------------HD6345/HD6445
•
External Synchronization Control (VE, VS, TV)
•
Interrupt Control (lB, IL)
(I) Operation mode alteration
Control 1 Register
IB
IL
VE
Function
o
EXVSYNC/vSYNC corresponds to VSYNC output
EXVSYNC/vSYNC corresponds to EXVSYNC Input
o
o
DISPTMG
VS
o
IRQ Signal
0
Not supplied
1
Supplied by light pen strobe
o
Supplied by vertical blanking
Supplied by light pen strobe
or vertical blanking
Activated
Keeps low
The IRQ signal
IS low
Notel
TV
Function
o
EXHSYNC/HSYNC corresponds to HSYNC output
Sync width register (R3) defines the HSYNC pulse
width
EXHSYNC/HSYNC corresponds to EXHSYNC Input
Sync width register (R3) defines the horizontal back
porch period
•
IS
supplied from the IRQ pin while the DISPTMG
Vertical Sync Position Adjust Control (SY)
Control 1 Register
SY
Vertical Sync POSItion Adjust Aeg. (R27)
o
Disabled
Enabled
(2) EXVSYNC and VSYNC control
•
VS TV
0
0
1
1
0
Signal supplied to EXVSYNC is ignored
1
EXVSYNC/VSYNC corresponds to EXVSYNC
Input and synchronized with the external Signal
0
1
Screen Split Control (SP I , SPo)
EXVSYNC
Control 1 Aeglster
SP I
SPo
o
VSYNC
I nterlace Sync
VS Non·lnterlace
VSYNC signal
supplied
Note) • Attention to the limitation Item described 10 Notel of Table 6
for Interlace sync and video mode.
Table 6 External Synchronization Control
CONTROL 2/ STATUS REGISTER (R31)
Data Bit
716151413121110
55.lss,jSs,~SSI I RI I - I - I AI I 0 I 0 I 0 I 0 I E I 5B I SL
0
0
0
Set as master CRTC In master·slave mode'
1
Set as master CATC In master·slave mode, in
interlace sync mode or interlace sync and video
mode, upon synchronization
0
0
1
0
Set as slave CATC In master·slave mode
1
1
Set as slave CATC in master·slave mode, upon
synch ron i zation
1
0
0
0
Program inhibited
1
1
Program inhibited
1
1
0
Set as slave CATC In TV sync mode"
1
1
1
Set as slave CRTC in TV sync mode, upon
synchronization * *
IS
Program Unit
-
RIWI
wi
5tatus~
----------
~
Control 2
0
0
"000"
Screen 2 and 3 start position regs.
(A1S, A21) enabled
Screen 2 to 4 start position regs.
(R1S, A21, A24) enabled
Function
TV VE VS
Note)·
o
I and
Interlace Sync
Video'
VSYNC signal supplied
VSYNC signal supplied only in
odd field scanning
0
1
Screen 2 start position register (A1S)
enabled
o
-
o
Function
Screen start position regs. (A IS, A21,
A24) disabled
During a write transaction, this register specIfies the screen
to be scrolled smoothly and proVides the double,slze vertical
display with the raster interpolatIOn function. A device reset
clears the bits of the control 2 register.
During a read transaction, this register indicates the status
such as display field, vertIcal blanking, light pen strobe and
access inhibIt in DPRAM mode. A device reset clears the AI bit
and SL bit of the status register.
Refer to Table 10 Reset State of Internal Registers for details.
< Control 2 Register>
SS., SS3, SS" SSI
Smooth scrolling control
RI
Raster interpolation control
< Status Register>
AI, E, SB, SL
Status indication
to be set also when not performing the external
synchronization.
In TV sync mode, DISPTMG IS supplIed after the back porch
period.
.HITACHI
Hitachi America ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
121
HD6345/HD6445,---------------------------------------------------------------------------• Smooth Scrolling Control (SS1-SS4)
Settmg the bits SSI to SS4 enables smooth scrolling on the
split-screens I to 4, respectively. The smooth scrolhng register
(R29) is enabled for the speCified split-screen.
Smooth Scrolling
,
,
SSt
0
Disabled on the split-screen 1
SS2
0
Disabled on the split-screen 2
SS3
0
Disabled on the split-screen 3
1
Enabled on the spilt-screen 3
,
Disabled on the split-screen 4
0
SS4
CONTROL 3 REGISTER (R32)
Data Bit
Enabled on the split-screen 2
Enabled on the split-screen 4
•
• Raster Interpolation Control (RI)
Settmg 1 mto this bit performs a raster mterpolatlOn. The
raster address is incremented every two rasters, doubhng the
vertical scanning cycle.
This function is provIded only in the non-Interlace mode and
the mterlace sync mode.
CM
Cursors Display Mode
o
EaR mode
OR mode
• Cursor 2 Enable (C2 )
Cursor 2
o
Status
DISabled
Enabled
• Cursor 1 Width Control (CW,)
Refresh memory access allowed
Refresh memory access inhibited
CW,
Cursor' Width Register (R38)
Disabled
I-character Width speCified as cursor' width
Enabled
Set value in R38 speCified as cursor' Width
o
Display Field Status Bit: E
E
Status
o
Dunng odd field display
Dunng even field display
Note) E
IS
always "0"
In
• Cursor 2 Width Control (CW 2 )
CW 2
Cursor 2 Width Register (R39)
o
the non-Interlace mode.
Disabled
I-character Width specified as cursor 2 Width
Enabled
Set value In R39 speCified as cursor 2 Width
Vertical Blanking Status Bit· SB
Status
S8
o
• Memory Width Control (MW)
Not dunng vertical blanking
Dunng vertical blanking
MW
Memory Width Offset Register (R33)
o
Disabled
Linear address supplied as memory address
Light Pen Strobe Status Bit· SL
SL
o
Enabled
Memory width definable
Status
• Three-State Control (TC)
Light pen strobe not detected
Light pen strobe detected
TC
Reading this register clears the SL, but not SB. Also, the IRQ
output sIgnal goes low upon read access of thIS register. The bits
3-6 of the status register are always read as Os.
o
MA and RA Outputs
Three-state control disabled
When TSC is low, memory address supplied on MAo - i3
and RA o- 4
When TSC is high, MAo -13 and RAo -4 stated
Into high- Impedance
~HITACHI
122
W
Cursors Display Mode Control (CM)
C2
• Status Indication (AI, E, S8, SL)
Access Inhibit Status Bit: AI
o
-
R/W
ThiS register controls the following by the corresponding
bits. A device reset clears this register
CM
Cursor dIsplay mode control
C2
Cursor 2 enable
CW,
Cursor 1 width control
Cursor 2 width control
CW2
MW
Memory Width control
TC
Three-state control
DR
DPRAM mode selection
Enabled on the split-screen 1
AI
Program Unit
716151413121110
CM I C, Icw, Icw, jMW I TcjDR 1-
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------------------HD6345/HD6445
•
DPRAM Mode Selection (DR)
DR
o
13 2
P,
0
0
0
DPRAM Mode Selection
DPRAM control signal not supplied
Enters DPRAM mode
Cursor Blink Mode
No blink
No cursor
Blink, 1/16 field rate
Blink, 1/32 field rate
0
MEMORY WIDTH OFFSET REGISTER (R33)
Data Bit
I Program Unit
716151413121 1 1 0 1
Nof (Offset Address)
I
RIW
Blink Rate
ON
RIW
Character
This register specIfies the offset value to be supplemented to
the memory address, in units of characters, in order to define the
start memory address of the next row. Adding the offset value to
the memory address makes the memory width wider than the
display width. Reprogramming the start memory address enables the display screen to be scrolled in any direction within a
memory space by character. If this register is set to the offset
value M, the start address of the next row will be the last displayed character address + M + I.
This register is enabled when "MW (bIt 3) = I" IS set into the
control 3 regIster (R32). If an offset value IS not required, the
MW bit of R32 or this regrster (R33) IS requested to be set as
OFF
1/16 or 1/32 Field Rate
CURSOR 2 END REGISTER (R35)
Data Bit
7
1 6 1 5 1 41 3 1 2 1 1 1 0
I Program Unit 1 RIW
I
Raster
I
w
ThIS regIster determInes the end raster address for the cursor
2.
If the C, bIt of the control 3 register IS 0, or
mode, thIS leglster IS mvaiid
In
the DPRAM
CURSOR 2 ADDRESS REGISTER (H, L) (R36, R37)
(R36)
O.
I·
Data Bit
Memory Width
·1
7
Program Unit
16151413121110
-I - I
1RIW
Memory
Address
Memory Address (H)
IRIW
(R37)
Data Bit
7
M
1 Program
1 6 1 5 1 4 13 1 2 1 1 1 0 1
Memory Address ( L)
I
Unit
Memory
Address
1R/W
I
RIW
These regIsters determine the cursor 2 dIsplay memory
address The hlgh·order two bIts of R36 are always read as Os.
This register is disabled in DPRAM mode or when "C, =0"
is set in the control 3 regIster (R32).
Display Width
CURSOR 1 WIDTH REGISTER (R38)
Data Bit
7
16151 4 1 3 1 2 1110
New] (Number of Characters)
Program Unit
RIW
Character
RIW
ThIs regIster specIfIes the cursor I WIdth In umts of
characters. WritIng 0 into thIS register dIsables the cursor 1
display.
ThIS register IS enabled when "CWI (bIt 5) = 1" IS set into
the control 3 regrster (R32).
Offset Val ue = M
Figure 28 Memory Width Offset
CURSOR 2 WIDTH REGISTER (R39)
CURSOR 2 START REGISTER (R34)
I
Data Bit
1716151413121110
I - I B, I P, I
Nes, (Raster Address)
Data Bit
Program Unit
RIW
Raster
W
This register determines the start raster address and selects
the cursor blink mode for the cursor 2. The low-order five bits
determines the start raster address. Bits B2 imd P, select the
cursor blink mode.
If the C2 bit of the control 3 register is 0, or in the DPRAM
mode, this register is invalid.
•
7
16151413121 1 1 0
New, (Num ber of Characters)
Program Unit
RIW
Character
RIW
ThIs regrster specifies the cursor 2 WIdth In umts of
characters. Wnting 0 into this register disables the cursor 2
dIsplay.
ThIS regIster is enabled when "CW, (bIt 4) = 1" is set into
the control 3 regIster (R32).
In DPRAM mode, this regIster specifies the ACI signal output
timing, not affected by the CW, bit at all .
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
123
HD6345/HD6445,----------------------------------------------------------------------------
•
LIMITATION FOR PROGRAMMING
The register programmed value is limited as listed in Table 7.
Table 7
limitation on Register Programmed Value
Associated Reg.
Register Programmed Value Range
Function
Screen Format
1 < Nhd < Nht + 1 :5:: 256
o < Nvd < Nvt + 1 ~ 256
Rl, RO
0:5:: Nhsp:5:: Nht
R2, RO
0:5:: Nvsp:5:: Nvt'
R7, R4
2:5:: Nr:5::30 (Interlace sync and video mode)
R9
Nvad
R6, R4
< Nr
R27, R9
3~ Nht
(Interlace sync mode and Interlace sync and video mode)
5~
(Non-Interlace mode)
Nht
RO
0:5:: Ncs, ~ Nce,
Nce, ~ Nr
< Nr
Nce,
o ~ Ncs,
Cursor Control
O~
Rll, R9
(Interlace sync and video mode)
~ Nce,
Nce, ~ Nr
Nce,
R10, Rll
(Non-interlace mode and (Interlace sync mode)
< Nr
R34, R35
(Non-interlace mode and interlace sync mode)
R35, R9
(Interlace syne and video mode)
Newl ~255
R38
0:5:: New, :5:: 255
R39
Smooth Scroll ing
Nss:5::Nr
R29, R9
Memory Width Setting
o ~ Nof ~ 255
R33
Notes 1)
" In the Interlace sync mode, If the vertical sync signal assertIOn stndes over the next field, the signal pulse width IS alternately
Increased or decreased by 1/2 raster period In the following fields.
2) Refer to INTERNAL REGISTER ASSIGNMENT for symbols
•
Table 8
RESET
The RES functions as a reset Input signal only while the
LPSTB IS low. "Reset" is definable in two stages.
___
(1) "During a reset state" indicates the period that the RES
remains "low".
(2) "After a reset state" indicates the state after the RES transItion from low to high
~~~o_j+--------~
ov
8V
A reset has occurred
Note
DUring
a Reset State
1. HD6345/HD6445 sets "6845S mode'"
Control registers R30, R31, and R32
cannot be programmed
After
a Reset State
1. HD6345/HD6445 remains "6845S
mode" until control registers R30, R31,
R32 are programmed
2 In external sync mode, the additional
Circuit IS required to prevent the
DUring
After
a reset state
The RES assertIOn at power-on does not define the internal
registers. The internal operation remains undefined until all the
internal registers have been programmed.
Reset Definition
The note for a reset is listed in Table 8, and the pin status
during a reset state is In Table 9.
Note)
"6845S mode"
The 6845S mode causes the HD6345/HD6445 to Implement
the HD6845S functions The HD6345/HD6445 IS softwarecompatible With the HD6845S, and IS provided With the extended functIOns of the HD6845S Programming the control
registers enables the extended functIOns
The control registers are Initialized dUring a reset state
The HD6345 has 68-compatible bus Interface It IS pmcompatible With NMOS CRTC-II HD6845S
HD6445 has 80-compatlble bus Interface Note that HD6445
IS not pm-compatible With NMOS CRTC HD6845S.
~HITACHI
124
conten~
tlon between syne signals (VSYNC,
HSYNC) of a master and those of a
slave
_
a reset state
Figure 29
Note for a Reset
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------------------IHD6345!HD6445
Table 9 Pin Status during a Reset State
Pin No.
1
2
Symbol
Input!
Output
Pin Name
Vss
Vss
-
-
RES
Reset
Input
lPSTB
light Pen Strobe
Input
TSC
Three State Control
Input
low level signal requested to be supplied
3
4-17
Functions
MAo-MAI3
Memory Address 0-13
Output
Goes low immediately after reset
18
DISPTMG
Display Timing
Output
Goes low Immediately after reset
CUDISP
Cursor Display
Output
19
ACI
Access Inhibit
Output
IRQ
Interrupt Request
Output
Vcc
Vcc
20
-
Goes low immediately after reset
-
21
ClK
Character Clock
Input
Not affected
22
WR
Write
Input
Not affected
Not affected
E
Enable (HD6345)
Input
RD
Read (HD6445)
Input
Not affected
24
RS
Register Select
Input
Not affected
25
CS
Chip Select
23
Input
Not affected
Input!
Output
Not affected
26-33
Do-D,
Data Bus 0-7
34-38
RAo-RA4
Raster Address 0-4
Output
Goes low immediately after reset
HSYNC
HOrizontal Sync
Output
Corresponds to HSYNC until external
sync mode is set into the control register
after reset
39
EXHSYNC
External Horizontal Sync
VSYNC
Vertical Sync
EXVSYNC
External Vertical Sync
Input
Output
40
Input
•
Corresponds to VSYNC until esternal
sync mode is set into the control register
after reset
HITACHI
Hitachi America ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
125
HD6345/HD6445i--------------------------------------------------------------------Table 10 Reset State of Internal Registers
Reg
No
R/W
RegIster Name
AR
Address RegISter
W
RO
R1
HOrizontal Total Characters
W
W
Hbrlzontal Dlsplay"if Characters
R2
HOrizontal Sync POSItion
Sync Width
R4
R5
R6
Vertical Total Rows
Vertical Total Adjust
W
Vertical DlSplayed~
R7
R8
R9
Vertical Sync POSItion
Interlace Mode and Skew
Maximum Raster Address
W
W
W
R10
Cursor 1 Start
R11
Curso~
R12
R13
Screen 1 Start Address (H)
Screen 1 Start Address (L)
R/W
R/W
R14
R15
Cursor 1 Address (H)
Curso~
R/W
R/w
R16
R17
R18
R19
R20
R21
~,'t,<';,
W
Light Pen (H)
R
LlohiPOnlLl
R
Screen 2 Start POSItIOn
R/W
Screen 2 Start Address (H)
Screen2St;;rt~ (L)
R/w
R/w
R/W
R/W
R24
Screen 4 Start POSItIOn
R/W
R25
R26
Screen~(H)
R/W
R/w
R27
Screen 4 Start Address (L)
Vertical S\'-n~-p~~,t,~~ Adjust
R28
R29
Light Pen Raster
Smooth Scrolling
R30
Control 1
' t.
l,;',;;'l
Screen 3 Start Address I L
"';~;
',::;,
.),.
,·i . ' ' .,;
~(r
I'!H','l';'
W
R
Control 2
Status
'Co~trol3
Memory~
1133
R34
R/w
W
0
0
W
R
W
0
0
0
0
0
0
0
0
R35
R36
Cursor 2 Address (H)
R37
-Fd8
Cursor 2 Address (L)
Cu rsor--,--w,(jth
:~~
Cursor 2 Width
R/w
Notel
c::::::::J
UJ
o:::::J
becomes "0"
~
becomes "0"
0
0
0
0
0
0
.
0
0
o
1
I
0_
R/W
Cursor 2 Start
Cursoa-E-';c:j
R39
0
r:;;;;,
W
R/w
-R32
0
'~;,'-
"
~\.:,;:
W
W
Screen~
R31
0
W
W
Screen 3 Start Address (H)
Rn
R23
1
'J
lJ"
R3
Data Bit (Reset State)
-4
2
3
-5
6
7
R/W
I
I
I
not affected
(After power-on, the value
-
IS
not fixed until
It IS
programmed I
becomes "1"
becomes "'"
In
In
the non-Interlace mode
the Interlace sync mode and Interlace sync and Video mode
(After power-on,
Its
status IS not fixed until the raster scanning mode IS set)
not used
•
(2) Refer to the RESET section for notes on a reset at power·
on,
NOTES AND LIMITATIONS FOR HD6445
NOTES
(1) The CRTC·II HD6345/HD6445 is the CMOS LSI, It
should be noted, peculiar to CMOS LSIs, that the input
pins of the HD63451HD6445 must not be left discon·
nected, etc,
$
126
LIMITATION FOR PROGRAMMING
Refer to "Table 7 LImitation on Register Programmed
Value" for details,
HITACHI
Hitachi America Ltd, • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------------------------!HD6345/HD6445
ANOMALOUS OPERATION BY REGISTER REPROGRAMMING DURING SCREEN DISPLAY
The temporary erroneous operation may occur If programRegister reprogrammIng IS:
ming the internal register during a screen display period. Gener0
Allowable
D.: Allowable with some conditions
ally, the device starts the newly specified operation on and after
A temporary flicker may occur upon deviation of the
the following field after a renewal.
conditIOns.
Whether or not the register reprogramming IS allowed dunng
X
Not recommended
a display IS shown by the symbols 0 L, and x in the follOWIng
table.
A temporary flicker may occur upon register renewal.
Reg.
No.
RO
Rl
Register Name
R2
HOrizontal Total Characters
Horizontal Displayed
Characters
HOrizontal Sync Position
R3
Sync Width
R4
Vertical Total Rows
R5
Vertical Total Adjust
R6
Vertical Displayed Rows
R7
Vertical Sync Position
R8
Interlace Mode and Skew
R9
Maximum Raster Address
Rl0
Rll
Cursor 1 Start
Cursor 1 End
R12
R13
Screen 1 Start Address (H)
Screen 1 Start Address (LI
R14
R15
R16
R17
R18
R19
R20
R21
Cursor 1 Address (HI
Cursor 1 Address (LI
Phenomenon and Renewal Recommended Period
HOrizontal scanning cycle IS "regularized.
DISPTMG width may be set shorter than specified only dUring 1 raster period
because of a momentary misrecognltlon of thiS register data.
HSYNC Will not be supplied as required, or a nOise may occur. It may be
supplied as programmed on and after the following field.
Sync pulse Width may be set shorter than speCified when registers are
reprogrammed dUring high of HSYNC and VSYNC
Vertical scanning cycle may be "regularized when reprogrammed during the last
raster scanning period within a row.
The speCified number of adjust rasters will not be supplemented when
reprogrammed within the last character clock time dUring adjust raster scanning
period.
Raster scanning may be suspended (DISPTMG goes low. I Immediately after
being reprogrammed within a field. The programmed display IS enabled on and
after the follOWing field.
VSYNC Will not be supplied as required, or a nOise may occur. It may be
supplied as programmed on and after the following field.
Reprogramming the scanning mode bit "regularizes vertical scanning cycle.
Reprogramming the skew bit neglects the programmed position for screen and
cursor displays.
Vertical scanning cycle IS "regularized.
Cursor raster scanning may be "regularized or blink period be temporarily set
shorter when reprogrammed within the last character clock time during raster
scanning period.
Except dUring the last raster scanning period within a row, register
reprogramming IS allowable. HOrizontal/vertical display period is espeCially
recommended for reprogramming. If R 12 and R 13 are separately reprogrammed
in the different fields, a screen display will temporarily start from the partially
reprogrammed address.
The cursor Will not temporarily be displayed at the speCified address when
reprogrammed dUring display period HOrizontal/vertical retrace period IS
espeCially recommended for reprogramming. If R 14 and R 15 are separately
reprogrammed In the different fields, a cursor Will be temporarily displayed on
the partially reprogrammed address
light Pen (HI
Light Pen (LI
Screen 2 Start Position
Screen 2 Start Address (HI
Screen 2 Start Address (LI
Screen 3 Start Position
-Except dUring raster scanning period prior to the split-screen 2 start row,
reprogramming IS allowable. Horizontal/vertical retrace period is espeCially
recommended for reprogramming.
Except dUring raster scanning period prior to the split-screen 2 start row,
reprogramming IS allowable. Horizontal/vertical retrace period IS espeCially
recommended for reprogramming If R 19 and R20 are separately reprogrammed
In the different fields, a screen display Will temporarily start from the partially
reprogrammed address
Except dUring raster scanning period prior to the split-screen 3 start row,
reprogramming is allowable. Horizontal/vertical retrace period IS espeCially
recommended for reprogramming.
$
x
0
x
L,
L,
L,
0
x
x
x
L,
0
0
0
0
0
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
127
HD6345/HD6445,------------------------------------------------------------------------
Reg.
No.
R22
R23
Register Name
Phenomenon and Renewal Recommended Period
Screen 3 Start Address (H)
Screen 3 Start Address (L)
R24
Screen 4 Start Position
R25
R26
Screen 4 Start Address (H)
Screen 4 Start Address (L)
R27
Vertical Sync Position
Adust
Light Pen Raster
Smooth Scrolling
Except during raster scanning period prior to the split-screen 3 start row,
reprogramming is allowable. Horizontal/vertical retrace period is especially
recommended for reprogramming. If R22 and R23 are separately reprogrammed
in the different fields, a screen display will temporarily start from the partially
reprogrammed address.
Except during raster scanning period prior to the split-screen 4 start row,
reprogramming is allowable. Horizontal/vertical retrace period is especially
recommended for reprogramming.
Except during raster scanning period prior to the split-screen 4 start row,
reprogramming is allowable. Horizontal/vertical retrace period is especially
recommended for reprogramming. If R25 and R26 are separately reprogrammed
in the different fields, a screen display will temporarily start from the partially
reprogrammed address.
The programmed position for VSYNC output will not be satisfied.
R28
R29
R30
Control 1 ·VE
·TV
'VS,18,IL
'SY
'SPo,SP,
R31
Control 2
'SS" -SS.
'RI
R32
--For a screen not performing smooth scroll, reprogramming is allowable except
during the last raster scanning period within each row. For a screen performing
smooth scroll, reprogramming is allowable except during rater scanning period
on the address of "programmed value-1". Horizontal/vertical retrace period is
especially recommended for reprogramming.
Reprogramming is allowable except at VSYNC output.
Reprogramming is allowable except at HSYNC output when DISPTMG is low.
Reprogramming is allowable.
VSYNC will not be supplied as required or a nOise may occur. It may be supplied
as programmed on and after the following field.
Temporary disturbance may occur on a screen when reprogrammed during the
display period. Vertical retrace period is especially recommended for
reprogramming.
Temporary disturbance may occur on a screen when reprogramming during
display period. Vertical retrace period is especially recommended for
reprogramming
Vertical raster scanning cycle is irregularized.
---
Status
Control 3
'CM,C,
'CW"CW,
'MW
R33
'TC, DR
Memory Width Offset
R34
R35
Cursor 2 Start
Cursor 2 End
R36
R37
Cursor 2 Address (H)
Cursor 2 Address (L)
R38
R39
Cursor 1 Width
Cursor 2 Width
~
Temporary disturbance may occur on a cursor when reprogrammed during
display period. Vertical retrace period is especially recommended for
reprogramming.
Temporary disturbance may occur on a screen when reprogrammed during
display period. Vertical retrace period is especially recommended for
reprogramming.
Reprogramming is inhibited.
The specified address for cursor display will not temporarily be satisfied upon
reprogramming during display period. Horizontal/vertical retrace period is
especially recommended for reprogramming.
Cursor raster scanning may be irregularized or blink period be temporarily set
shorter when reprogrammed within the last character clock time during raster
scanning period.
The specified address for cursor display will not temporarily be satisfied when
reprogrammed during the display period. Horizontal/vertical retrace period is
especially recommended for reprogramming. If R36 and R37 are separately
reprogrammed in the different fields, a cursor will be temporarily displayed at
the partially reprogrammed address.
The specified cursor width will not temporarily be satisfied when reprogrammed
during display period. Horizontal/vertical retrace period is especially
recommended for reprogramming.
~HITACHI
128
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
a
a
a
x
f::,
a
a
a
f::,
f::,
f::,
x
f::,
f::,
x
a
f::,
a
f::,
----------------------------------------------------------------------------HD6345/HD6445
• ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Unit
-0.3 - +7.0
V
Input Voltage
Vee "
Von "
Operating Temperature
Too,
-0.3 - Vee+0.3
-20-+75
V
°c
T,to
-55 - +150
°c
5
rnA
Item
Supply Voltage
Storage Temperature
Allowable Output Current
I
Data Bus
I
Others
1101""
11: 10 I"""
Total Allowable Output Current
• This value IS
In
reference to
3
rnA
50
rnA
vss = OV
** The allowable output current IS the maximum current that may be drawn from, or flow out to, one output pin or one Input/output common pin .
••• The total allowable output current
IS the total sum of currents that may be drawn from, or flow out to. output PinS or input/output common pins
Notel USing an LSI beyond Its maximum ratings may result In Its permanent destruction. LSI's should usually be under recommended operating
conditions. Exceeding any of these conditions may adversely affect Its reliability .
•
RECOMMENDED OPERATING CONDITIONS
Symbol
Item
Input Low Level Voltage
Vee "
V,L "
Input High Level Voltage
V,H
Operating Temperature
Top,
Supply Voltage
* ThiS value IS
•
In
reference to
vss
.
Min
Typ
Max
4.75
5.0
5.25
V
0.8
V
Vee
75
°c
-
-03
2.0
25
-20
Unit
V
= OV
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee = 5.0V±5%. Vss = OV. Ta = -20 - +75°C unless otherwise noted)
Typ"
Max
Unit
Input High Level Voltage
V,H
2.0
-
V
Input Low Level Voltage
V,L
-0.3
-
Vee
0.8
2.5
p.A
Symbol
Item
Measuring Condition
Min
V
Input Leak Current
Inputs except
Do- D7
Ion
Von = 0- 5.25 V
-2.5
-
Three State (Off State)
Input Current
Do - D7
Memory Address
Raster Address
ITSI
Von = 0.4 - 2.4 V
Vee=525V
-10
-
10
Output High Level
Voltage
Do - D7
Others
VOH
1= -205p.A
1=-l00p.A
2.4
-
-
V
VOL
1- 1 5mA
-
-
0.4
V
Von =0 V
Ta = 25°C
f = 1.0 MHz
-
-
12.5
pF
Con
-
-
10
pF
Cout
Von = 0 V
Ta = 25°C
f = 1 MHz
-
-
10
pF
Po
feLK = 4.5 MHz
fE = 2 MHz
Vee = max, No Load
V'H=Vee- 1.OV
V'L=0.8V
-
50
Output Low Level Voltage
Do - D7
EXVSYNC
EXHSYNC
Input Capacity
Others
Output Capacity
Power Dosslpatlon
" T. = 25°e, Vee
-
p.A
mW
=5 OV
~HITACHI
Hitachi Ameroca Ltd • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
129
HD6345/HD6445-----------------------------------------------------------------------AC CHARACTERISTICS (VCC
= 5V±10%, Vss = OV, Ta = -20 -
+75°C, unless otherwise noted.)
1. TIMING OF CRTC SIGNAL
Max
Min
Test Condition
Symbol
Item
Unit
Clock Cycle Time
Clock High Pulse Width
teyeC
220
-
ns
PWCH
100
-
ns
Clock Low Pulse Width
100
-
ns
Rise and Fall Time for Clock Input
PWCL
ter, tcf
-
20
ns
Memory Address Delay Time
tMAO
-
80
ns
Raster Address Delay Time
tRAO
-
80
ns
D ISPTMG Delay Time
tOTO
-
120
ns
CUDISP Delay Time
tcoo
-
120
ns
Horizontal Sync Delay Time
tHSO
-
100
ns
Vertical Sync Delay Time
tvso
-
120
ns
Light Pen Strobe Pulse Width
PWLPH
60
-
ns
Light Pen Storobe Uncertain Time of
Acceptance
tLPOl
Memory Address Three-State Off Time
tMAZ
Raster Address Three-State Off Time
tRAZ
Fig. 30
Fig 32,33
70
ns
0
ns
50
ns
50
ns
Min
Max
Unit
ns
-
tLP02
Fig. 31
2. EXTERNAL SYNC TIMING
Item
Test Condition
Symbol
Clock Halt Time
tCLKST
100
External Horizontal Sync Pulse Width
tPWHS
1000
-
-
20
ns
-
20
ns
1660
-
ns
tVr
-
20
ns
tV!
-
20
ns
External Horizontal Sync Rise and Fall Time
tH r
Fig. 34
tH!
External Vertical Sync Pulse Width'
External Vertical Sync Rise and Fall Time
.. : External Vertlcel Sync Pulse Width
tpwvs
tpwvs = 1000 ns + 3·tcyc
ns
C
3. HD6345 MPU BUS TIMING
Item
Symbol
Test Condition
6345
63A45
63B45
Min
Max
Min
Max
Min
Max
Unit
666
-
500
ns
280
-
220
-
Enable Cycle Time
tcycE
1000
Enable "High" Pulse Width
PWEH
450
Enable "Low" Pulse Width
PWEL
400
-
Enable Rise and Fall Time
tEr, tEf
-
20
-
20
-
20
ns
Address Set Up Time
tAS
80
-
80
40
tosw
195
-
80
-
ns
Data Set Up Time
-
Data Delay Time
tooR
Data Hold Time
tH
Address Hold Time
tAH
Data Access Time
tACC
Input Signal Rise and Fall Time
(RES, LPSTB, RS, CS, R/W)
tr, tf
Fig. 35
Fig. 36
10
10
-
200
280
100
280
10
-
140
210
60
-
-
10
10
ns
ns
120
ns
-
ns
ns
220
-
160
ns
100
-
100
ns
~HITACHI
130
ns
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
____________________________________________________________________________ HD6345/HD6445
4. HD6445 MPU BUS TIMING
l
HD6445-4
Symbol
Item
Min
Test Condition
Max
Unit
Read Address Set Up Time
tAR
a
-
ns
Read Low Level Time
tRR
160
-
ns
Read Address Hold Time
tRA
-
ns
Write Address Set Up Time
tAW
a
a
-
ns
Write Low Level Time
tww
190
-
ns
Write Address Hold Time
tWA
a
-
ns
Data Delay Time
tRO
120
ns
-
Fig. 37
Fig 38
Data Hold Time (Read)
tOF
10
-
ns
Data Set Up Time
tow
60
-
ns
Data Hold Time (Write)
two
a
-
ns
Access Inhibit Time
tOIS
210
-
ns
t,-
-
100
ns
Input Signal RISe Time
Fall Time
(RES, LPSTB, RS, CS, RD, WR)
tf
toyoC
PWCl
20V
08V
O'V
eLK
I'--------...JI
O'V
O'V
'"
2 4V
+---..J
MAO-MAl) _______________
24V
DISPTMG
tOTO
CUDISP
ICOD
HSYNC
VSYNC
tHSO
IVSD
---A
2OV
lPSTB
PW~PH
K
Figure 30 CRle Timing Chart
~HITACHI
Hitachi America Ltd
• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
131
HD6345/HD6445----------------------------------------------------------------------------
lPSTB
\
(TC= 1)
20V
I
o BV
\
MAo-MA13
/
r----
I----
tMAD
tMAZ
\
J
l"-
i----
tRAO
tRAZ
Note) tMAZ and tRAZ show the timing when outputs are completely
turned off. Actual waveform vanes according to loads conditions.
Figure 31 Three-State Delay Timing (Three-state mode: TC = 1)
ClK
MAo-MA13
~_ _~L_ _~'L_
__
~~:~---~
\'------
lPSTB
20V
lPSTB
When LPSTB rises in this period,
memory address "M+2" is set
into the light pen registers.
tLPD1. tLP02 : LPSTB's invalid time of acceptance
Figure 32 CRTC-CLK, MAO-MA13, and LPSTB Timing
~HITACHI
132
Hitachi America Ltd_ • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------------------HD6345/HD6445
ClK
M
lPSTB
M+l
____________Ji OBV
When LPSTB rises after this timing,
raster address 'M+l"
IS
set
Into
the light pen registers.
tLPD3
LPSTB's invalid time of acceptance
Figure 33 CRTC·ClK, RAo - RA4 and lPSTB Timing
tclkst
ClK
I
20V
EXHSYNC
°
BV.f-
iHr
°
BV
20V
°
BV
tpwHS
tH!
2 OV
EXVSYNC
'"'4
.
tpwVS
Figure 34
' 'l"'
tv!
tvr
External Sync Timing
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
133
HD6345/HD6445----------------------------------------------------------------------------
1---------tcvcE -----<001
Dav
R/W, RS
DO- 0 7 ----------~
Q4V
Figure 35
04V
HD6345 Read Sequence
1------tCyce------<.,f
Dav
CS
;:-:---,
RS
Figure 36
HD6345 Write Sequence
cs
RS
DO-07
(Read~
Figure 37
HD6445 Read Sequence
~HITACHI
134
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
------------------------------------------------------------------------HD6345/HD6445
cs
RS
2.0V
o 8V
O.8V
I - - - - - - t , . - - -__I+-.,
0 0- 0 7
IWrlte)
24V
24V
o 4V
O.4V
Figure 38
HD6445 Write Sequence
TEST LOAD
50V
0,
Test POlnt
o---_---..---+....__~
0,
0,
i',"
04
Figure 39
c= 130pF 100 - 071
= 40pF (Output signals except Do - 0,)
R= l1kn IDa - 071
= 24kfl (Output Slgnlils except Do - 0,)
01 - 04 are IS207443)or equivalent.
Test Load
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
135
HD6345/HD6445-----------------------------------------------------------------------•
COMPARISON BETWEEN HD6345/HD6445 AND HD6845S
HD6845S
HD6345/HD6445
elK: 4.5 MHz CMOS
68 System Bus Interface (HD63451
ClK: 3.7 MHz NMOS
6800 System Bus Interface
80 System Bus Interface (HD64451
1. Refresh Memory Address (16k words)
1. Refresh Memory Address (16k wordsl
2. Paging, Scrolling
2 Paging, Scrolling
3. light Pen
4. TTL Compatible
4. TTL Compatible
3. Light Pen
5. Software Programmable:
Number of Displayed Characters on Screen
Number of Rasters per Character Row
HonzontallVertlcal Sync Signal
Raster Scanning Mode
5. Software Programmable:
Number of Displayed Characters on Screen
Number of Rasters per Character Row
HorizontallVertical Sync Signal
Raster Scanning Mode
Cursor
Cursor
I
I
6. Screen Spilt (Up to 4)
I
I
I
7. Smooth Scroll Ing
I
I
I
:
B. External Synchronization
I
I
9. I nterrupt Request
I
10. Raster Interpolation
I
I
I
11. Sync Position Adjustment
,I
!
12. light Pen Raster Address
I
13. Second Cursor
I
I
I
I
I
I
14. Display Memory Width Setting
15. Up to 256 Character Rows
I
:
16. Timing Signal for Dual Port RAM
I
I
17. Three-State Control of Memory Address and Raster
Address
•
136
I
I
HITACHI
Hitachi America Ltd_ • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------------------HD6345/HD6445
• CHARACTERISTICS DIFFERENCES BETWEEN HD6345 AND HD6845S
No.
Item
Symbol
HD6845S
HD6345
Min
Typ
Max
-
1
Power Dissipation
Po
-
50
2
Clock Cycle Time
tcycc
220
3
Clock "High" Pulse Width
PWCH
100
-
4
Clock "Low" Pulse Width
PWCL
100
-
5
Memory Address Delay Time
tMAO
6
Raster Address Delay Time
tRAO
7
Display Timing Delay Time
tOTO
8
Horizontal Sync Delay Time
tHSO
9
Vertical Sync Delay Time
tvso
-
10
Cursor Display Delay Time
tcoo
-
11
Enable CYGle Time
tCYCE
500
-
12
Enable "High" Pulse Width
PWEH
220
13
Enable "Low" Pulse Width
PWEL
210
14
Enable Rise and Fall Time
tEr, tEl
-
15
Address Set Up Time
tAS
40
16
Data Set Up Time
tosw
60
17
Data Delay Time
tOOR
18
Data Access Time
tACC
19
Input Signal Rise and Fall Time
t" tf
-
Unit
Min
Typ
Max
-
600
1000
mW
270
-
ns
-
ns
160
ns
160
ns
250
ns
200
ns
250
ns
100
-
120
-
-
120
-
-
250
ns
-
1000
-
ns
-
-
450
-
-
-
-
400
-
-
ns
-
ns
320
ns
460
ns
-
ns
80
80
120
20
130
130
-
-
140
120
-
160
100
195
ns
ns
ns
ns
• CHARACTERISTICS DIFFERENCES BETWEEN HD6445 AND HD6845S
No.
Item
HD6845S
HD6445
Min
Typ
Max
-
-
50
220
-
2
Clock Cycle Time
Po
tcycC
3
4
Clock High Pulse Width
PWCH
100
-
Clock Low Pulse Width
PWCL
100
5
Memory Address Delay Time
tMAO
-
-
6
Raster Address Delay Time
tRAO
-
1
Power Dissl pation
Symbol
7
Display Timing Delay Time
tOTO
8
Horizontal Sync Delay Time
tHSO
-
9
Vertical Sync Delay Time
tvso
-
10
Cursor Display Delay Time
tcoo
-
Unit
Min
Typ
Max
-
600
1000
mW
270
-
-
ns
160
ns
160
ns
250
ns
200
ns
250
ns
250
ns
130
130
80
-
-
80
-
-
120
-
100
-
120
-
120
-
ns
ns
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
137
HD6345/HD6445---------------------------------------------------------------------------•
PACKAGE DIMENSIONS [Unit: mm (inchtl
Scale 1/1
528(2079)
540max (2126ma)l)
~nn
21
,nnnn
•
-$i
-
10
41
(DP-40)
Note) Inch value Indicated for your reference.
~HITACHI
138
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
HD6845R/HD6845S
CRT Controller (CRTC)
The CRTC is a LSI controller which is designed to provide
an interface for microcomputers to raster scan type CRT displays.
The CRTC belongs to the HD6800 LSI Family and has full
compatibility with MPU in both data lines and control lines. Its
primary function is to generate timing signal which is necessary
for raster scan type CRT display according to the specification
programmed by MPU. The CRTC is also designed as a programmable controller, so applicable to wide-range CRT display from
small low-functioning character display up to raster type full
graphic display as well as large high-functioning limited graphic
display.
•
•
FEATURES
Number of Displayed Characters on the Screen, Vertical
Dot Format of One Character, HOrizontal and Vertical
Sync Signal, Display Timing Signal are Programmable
•
3.7 MHz High Speed Display Operation
•
•
•
•
•
•
•
Line Buffer-less Refreshing
14-bit Refresh Memory Address Output (16k Words
max. Access)
Programmable Interlace/Non-Interlace Scan Mode
Built-in Cursor Control Function
Programmable Cursor Height and its Blink
Built-in Light Pen Detection Function
Paging and Scrolling Capability
•
•
TIL Compatible
Single +5V Power Supply
HD6845SP, HD68A45SP, HD68B45SP
HD6845RP, HD68A45RP, HD68B45RP
(DP-40)
•
PIN ARRANGEMENT
VSYNC
HSVNC
RA.
RA,
MA,
RA,
MA,
RA,
MA,
RA,
MA,
D.
HD6845S
HD6845R
0,
0,
0,
0,
0,
0,
• SYSTEM BLOCK DIAGRAM
0,
Cs'
RS
1-----+-.----+--,------ 0Data-0,Bus
Aiw
0
ClK
(Top View)
•
ORDERING INFORMATION
CRTC
Bus Timing
CRT Display
Timing
HD6845S
HD68A45S
HD68B45S
1.0 MHz
1.5 MHz
2.0 MHz
3.7 MHz max.
HD6845R
HD68A45R
HD68B45R
1.0 MHz
1.5 MHz
2.0 MHz
3.7 MHz max.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
139
HD6845R/HD6845S - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
•
ABSOLUTE MAXIMUM RATINGS
Item
·
•
Vee
Input Voltage
V,n
Operating Temperature
Storage Temperature
W'th respect to Vss (SYSTEM GNDI
[NOTE]
Value
Unit
-0.3-+7.0
·
V
-0.3-+7.0
V
Topr
- 20- + 75
°c
T otg
- 55- +150
°c
Permanent LSI damage may occur If maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI.
R,ECOMMENDED OPERATING CONDITIONS
Item
Vee
V IL
Input Voltage
V IH
Operating Temperature
•
.
Symbol
Supply Voltage
•
.
Symbol
Supply Voltage
·
·
min
typ
max
Unit
4.75
5,0
5,25
V
-0.3
-
0.8
V
2.0
-
Vee
75
V
°c
- 20
Topr
25
Woth respect to Vss (SYSTEM GNDI
ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee = 5V ± 5%, Vss = OV, Ta = -20-+75°C, unless otherwise noted.)
Item
Symbol
typO
max
Unit
Vce
0.8
V
-2.5
-
2.5
p.A
- 10
-
10
p.A
2,4
-
-
V
-
-
0.4
V
Do - D,
-
12.5
pF
Other Inputs
-
-'
10.0
pF
-
10.0
pF
600
1000
mW
Test Condition
min
Input "High" Voltage
V IH
2.0
Input "Low" Voltage
V IL
-0,3
Input Leakage Current
lin
V ln = 0 - 5,25V (Except Do-D,)
Three-State Input Current
(off-state)
I TSI
V ln = 0,4 - 2.4V
Vee = 5.25V (Do- D,)
Output "High" Voltage
Output "Low" Voltage
V OH
I LOAD = -205p.A (Do- D,)
I LOAD = -100 p.A (Other Outputs)
VOL
I LOAD = 1.6 mA
Cin
V,n = 0
Ta = 25°C
f = 1.0 MHz
Output Capacitance
Cout
Vi" =OV, Ta = 25°C, f = 1.0 MHz
Power Dissipation
Po
Input Capacitance
I
I
-
• Ta= 25° C, Vee = 5.0V
~HITACHI
140
Hitachi America Ltd, • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
V
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6845R/HD6845S
•
AC Characteristics
(Vee = 5V ± 5%, T.
= -20
- + 75°C, unless otherwise noted.)
1. TIMING OF CRTC SIGNAL
No.
Item
1
Clock Cycle Time
HD6845S
HD6845R
Test
Condition
Symbol
min
typ
tcycC
330
-
min
typ
-
270
-
max
max
Unit
-
ns
2
Clock "High" Pulse Width
PWCH
150
-
-
130
-
-
ns
3
Clock "Low" Pulse Width
PWCL
150
-
-
130
-
-
ns
4
Rise and Fall Time for Clock Input
Tcr tCI
-
-
15
-
-
20
ns
5
Horizontal Sync Delay Time
t HSO
-
-
250
-
-
200
ns
6
Light Pen Strobe Pulse Width
PW LPH
80
-
-
60
-
-
Light Pen Strobe
Uncertain Time of Acceptance
-
-
80
-
-
70
ns
7
t LPo2
-
-
10
-
-
0
ns
8
Memory Address Delay Time
t MAO
-
-
160
-
160
ns
9
Raster Address Delay Time
t RAO
-
-
160
-
-
160
ns
-
-
250
-
-
250
ns
Fig. 1
t LP01
Fig. 2
ns
10
DISPTMG Delay Time
toTO
11
CUDISP Delay Time
tcoo
-
-
250
-
-
250
ns
12
Vertical Sync Delay Time
tvso
-
-
250
-
-
250
ns
HDS8B45R
HD68B45S
typ
min
max
Unit
Fig. 1
2. MPU READ TIMING
Item
Symbol
Test
Condition
HDS845R
HD6845S
min
typ
max
-
-
25
-
140
-
-
140
tOOA
-
320
-
tH
10
tAH
10
-
10
Address Hold Time
Data Access Time
tAcc
-
-
460
-
Enable Cycle yinje
t eVeE
Enable "High" Pulse Width
PW EH
0.45
Enable "Low" Pulse Width
PWEL
0.40
Enable Rise and Fall Time
tEr. tEl
Address Set Up Time
tAS
Data Delay Time
Data Hold Time
1.0
Fig. 3
-
HDS8A45R
HD68A45S
min
typ
max
0.666
0.28
0.28
10
-
-
-
/lS
0.21
-
0.5
0.22
/lS
/lS
25
-
-
-
25
ns
70
-
ns
220
-
-
-
10
-
-
10
360
-
-
180
ns
-
ns
250
ns
ns
3. MPU WRITE TIMING
Item
Symbol
Test
Condition
HD6845R
HD6845S
min
typ
max
Enable Cycle Time
t eveE
Enable "High" Pulse Width
PW EH
0.45
Enable "Low" Pulse Width
PW EL
0.40
Enable Rise and Fall Time
tEr. tEf
Address Set Up Time
tAS
140
Data Set Up Time
195
Data Hold Time
t"sw
tH
Address Hold Time
tAH
1.0
Fig. 4
-
-
10
-
10
-
HD68A45R
'HD68A45S
typ
min
max
-
0.666
-
0.28
0.28
25
-
-
140
80
10
10
-
25
-
HD68B45R
HD68B45S
typ
min
max
10
-
10
-
0.5
0.22
0.21
70
60
Unit
-
/lS
25
ns
-
/ls
/.ts
ns
ns
ns
ns
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
141
HD6845R/HD6845S - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
cvcc
2.0V
/
1\
o SV rClK --'
--
1-
PW CH
ICt
ICr
V
PW CL
20V--'f-
-. O.SV
OSV
L2.4V
--'~
tMAD
tMAD
24V
/
--'~
tRAD
tRAD
/
DISPTMG
2.4V
/
CUDISP
~.4V
-
~
!L2.4V
4V
teDo
teDo
/
2.4V
~
tHSD
IHSD
tvso
tVSD
4V
~
~~-2-.0-V---------P-W-L-PH-------~~--------------------ThiS Figure shows the relation," time between
eLK signal and each output signals. Output
sequence rs shown In FIgs. 10-15.
Figure 1 Time Chart of the CRTC
~HITACHI
142
---'
tOTO
tOTO
lPSTB ________
O.SV
-
/
HSYNC
VSYNC
--'
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6845R/HD6845S
tLPD1
eLK
M+2
LPSTB
\\....---
--------11
-+___20V
LPSTB _ _ _ _ _ _ _
-J
~
When LPSTB rises In this pertOd,)
Refresh Memory Address "M+2"
15 set IOta the light pen registers.
tLPD1' tLPD2
LPSTB's uncertain time of acceptance
Figure 2 LPSTB Input Timing & Refresh Memory Address that
IS
set Into the light pen registers.
~------------t~E
08V
e---------+--__JI
cs-------.
R/W. RS-------'
0,-0, __________________________--(
O.4V
O.4V
Figure 3 Read Sequence
•
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
143
HD6845R/HD6845S-----------------------------------------------------------1------------tC'/
~
u
~
.t:
a:
~
.
u
]I
x
~
{?
ti
'f
~
>
'0
HOrizontal
Retrace
i
Period
~
a
i5
ti
t' ~
~~
'0
Display Period
!E ~.
~
~
z .t:
U
~
.0
E
~
Z
-
Vertical Retrace Period
Vertical fotal Adjust (NadJ I
Figure 7 CRT Screen Format
~HITACHI
150
Hitachi Amenca Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6845R/HD6845S
Table 8 Programmed Values mto the Registers
Value
Register
RO
Honzontal Total
Nht
Rl
HOrIZontal Displayed
Nhd
R9
RIO
Nhsp
Nvsw. Nhsw
Rll
Cursor End Raster
Rl2
Start Address (H)
0
0
Register
Reg Ister Name
Register Name
Nr
Cursor Start Raster
R2
Horizontal Sync Position
R3
Sync Width
R4
Vertical Total
Nvt
Rl3
Start Address (L)
R5
Vertical Total Adjust
Nadj
R14
Cursor (H)
Cursor (L)
R6
Vertical Displayed
Nvd
R15
R7
Vertical Sync Position
Nvsp
Rl6
Light Pen (H)
R8
Interlace & Skew
Rl7
Light Pen (L)
[NOTE]
Value
Max Raster Address
Nhd--6
7 -:-:::-:. __
~
7
8 •
8
--G--- - - - - - - - . . --8
9
8
8
A --0---------·--<>--9
e
e e
---- - - -- -- ------ ---0
--8--- - - - - -
2 •
8
- -0- - -- - --- ---8-- 2
3 •
8
-:t-.-.-.-.-.--:-h
_____
__
B -_-_-_-_-_-_-_--_-_-_-_-_--_-_-A
- - - - - - - - - - - - - - -- B
B
Non-mterlace Mode
Interlace Sync Mode
~~r~~~~----:~=:f-~~
j
-:-e
e-t-6-
-CI -Cl .. ·
5
~1~~----~--~~ ~ =~t~~
A--=------=~
~--~ ~
0_-0- ___________ 8-_ ' ]
2
4
Ime #0
(l~~:---~:~:~:.t~~
6 •
•
•
.-8--.-.-.. . •
5
lone #0
:j~~ =~=~~~~-j:~ ~
,--0-----------0--- 2 j
.
5--:--.--.-.--.-.--:-- 4
8
=1=:-----------------
--Sn _____ u __ :. __ 3
--0-.-
.
A ________________ 0
]
3
Ime #1
~
8- -:----- -- -- -- :---7
A--O---- - - - ----0--9
----- - - ----- -- ----- B
Interlace Sync & Video Mode
(Total number of rasters in a line IS even)
•
8
Ione#'
- .. ----------.-- 6
ng __ -------- -i---
8
- - - - - - ----------- A
Interlace Sync & Video Mode
(Total number of rasters In a line
IS
odd.)
Figure 8 Example of Raster Scan Display
$
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue. San Jose, CA 95131 • (408) 435-8300
151
HD6845R/HD6845S - - - - - - - - - - - - - - - - - - - - - - - - - - - - Interlace Sync & Video Mode Control
In interlace sync & video mode, the output raster address
when the number of rasters is even is different from that when
the number of rasters is odd.
T~
Number of
Rasters in a Line
Even
Odd
•
I
I
1-++++-+-H-
2-+-++-+-+-+-+-
Table 9 The Output of Raster Address in
Interlace Sync & Video Mode
Even Field
O-+-++-+-+-+-+-
3-+--+-t-IH-+-+4 -+--+-t-IH-+-+-
Odd Field
Even Address
Odd Address
Even Line"
Even Address
Odd Address
Odd Line"
Odd Address
Even Address
s -+-I--+--+-+-H6-+-I--+--+-+-H7-+-I--+--+-+-H-
•
4-+--+t-IH-+-+-
s-+-+-+-+-+-+-+6-+-I--+--+-+-H7-+-++-+-+-+-+-
s-+--+-t-IH-++-
10 -+-+-+-+-+-+-+-
10-6..................
:0
9
Cursor End Address" 9
1) Total number of rasters in a line is even;
When number of rasters is programmed to be even, even
raster address is output in the even field and odd raster address
is output in the odd field.
2) Total number of rasters in a line is odd;
When total number of rasters is programmed to be odd, odd
and even addresses are reversed according to the odd and even
lines in each field. In this case, the difference in numbers of dots
displayed between even field and odd field is usually smaller the
case of 1). Then interlace can be displayed more stably.
[NOTE] The wide disparity of dots between number of dots
between even field and odd field influences beam
current of CRT. CRT, which has a stable high·voltage
part, can make interlace dIsplay normal. On the con·
trary, CRT, which has unstable high·voltage part,
moves deflection angle of beam current and also dots
dIsplayed in the even and odd fields may be shifted.
Characters appears dlstrotlOg on a border of the
screen. So 2) programming has an effect to decrease
such evil influences as mentIoned above. Fig. 13
shows fine chart in each mode when IOteriace is
performed.
2-+--++-H-++-
3-+-++-+-+-+-+-
s-+--+-+-H-+-+-
9 -G>-e. . . . .e-e-Cursor Start Address
Internal line address begins from 0
O-+--++-H-++-
9 .......IHHll.......
Cursor Start Address = 9
Cursor End Address =
o-++++-+-H-
1 .......IHHll......
2-G. . . . . .e-e--
3 .......IHHll......
4~...~~......- . -
S .......IHHll......
6-+--+-t-IH-+-+s -+++--+-+-H-
9-+--++-H-++10 -+-+++-+-HCursor Start Address = 1
Cursor End Address = 5
Figure 9 Cursor Control
Cursor Control
Fig. 9 shows the display patterns where each value is
programmed to the cursor start raster register and the cursor
end raster register. Programmed values to the cursor start raster
register and the cursor end raster register need to be under the
following condition.
Cursor Start Raster Register ~ Cursor End Raster Register ~
Maximum Raster Address Register.
Time chart ofCUDlSP IS shown in FIg. 14 and Fig. 15.
~HITACHI
152
HItachi AmerIca Ltd . • 2210 OToole Avenue • San Jose, CA 95131 • (408) 435-8300
10
Character Clock PerIOd
Tc
Number of Harolontal Dlsplaved Characters
/
/
_________ nn __
c----I
N~ 1
eLK
Nhd
Hor'lontal Sync POSition
Nhsp
Number 01 Horlzontdl Total Characters
Nhsp + 1
___________ --I"1-
NO'
HorIzontal Til'" Chlln
Ho"wnlal D,splay Pertod Nh,"T
OISPTMG
:I:
I-
~
;<.
-I-
Nhsp-Tc
Nh$W'Tc
HSYNC
==1
Tr
~
INhH1!oT c
»
3
MA.-MA"Y 0 Y 1 12 I
~
~'---J\.....
~r
a~
.......
________
~
RA.-RA~
!:
?~
eLK
o
.,o~.•
~J:
00(')
~ J:
<...
________
---"--
___ _
-----------------J
r
U'U1..fL ______ JlJ1Il
_______ Jl.flJl __________ J1JUl __
------.rtn.rm ______ JlIlJlfl.. __ _
~::::H:~::::Y2I..~~-=::::::::~::::==E"::~"?::
MA._MA€,
_
~ ~
..........
~r------------------
r----------------RasterP""odTr
o
CD
-------~-v--v-------------~--------------v-----__ ...... __
RA,-AA,
_
0
~
,--~r
1
-,_:::::::=t==
X
=+==0
N,
I
\,,,m,mR"'" Add:",
1
TIme Chart 01 Ra51er
LIne Period
L,n.e Penod
TL -INr+OoTr
Line
r
~
-
lone Penod T L - - - - - - - - - - - - - - - - - - - - - - i
()
»
-r=
~
~
~
~
~
~
r
D~Plaved Characters
Vert,cal D'sp1ay Period Nvd-T L
~_'@
~.._JIUL_JUUlJUUl._
nnn--nnn--nnn - -.•••••
- - - -___
• - ••
- -___________________
- - - - - - - - - - - - - - - - - - •~
\ V",,,,1 R.."" ',,,od
.1..
Number of Vertlci"l
~
DISPTMG
-1 i
FramePe"odT FAM
,_
/' SeeFIg 11
____
Tadl
NIIsp
"
~~~"1':~ Sync
t-- ~~~~~h~:a~,e;r,~ca'
/~- ,@
I
!--TIISW
- - - - - - - - - - - - N v s p o TL - - - - - - - - - - -
VSYNC
\
nlt-llll-J\IlJI.--.-'
_ _ _
-' SeeF,g 12
Verllcal T,me Chart
Frame Per,od TFRM
~
(N VT +1)oT l +TadJ
Tadl
FIne Adlu5lmem
Period of Frame
Tadl - NadJoTr
Tvsw VertIcal Sync
PulseW,dlh
TV$w -lIrIvswoTr
::c
o
0>
0)
Figure 10 CRTC Time Chart
(
Output waveform of hOrizontal & vertical diSPlaV)
to the case where values shown In Table 8 are
Programmed to each r~lster
0
01
to)
~
01
:lJ
J:
o
0>
0)
~
01
en
HD6845R/HD6845S------------------------------------------------------------
- i - - - - - - - - - - - - V e r t l c a l Display Period
------------t-~----
Vertical Retrace Period - - - - - - -
L'"e~----------~N~w~-~2------------L------------N~W~-~'------------L---~N~W~-------DI SPTMG
Ih
____________________
---- -- - -___
- - - ...J
-,.-,U ,.-,1_ _ _ _ _ _ _ _ _ _ _ __
U ,.,U r---1U , . ,L
___- ...J, . ,U , . ,U r---1U, . ,U , . ,U , . ,L-
Figure 11 Switching from Vertical Display Period over to Vertical Retrace Period (Expansion of Fig. 10-
1 - - - - - - - - - Vertical
Lme
DISPTMG
Retrace Penod
FlOe Adjustment Period of
Frame Period
Tad] = Nad)' Tr
~::::::::JN~~~:::::::::::::::l~~~~~~~~~~~:::::::::::::J[:::::::::::::t::::::::I:::::
1---------------------------------------------------'
Figure 12 Fme Adjustment Period of Frame m Vertical Display
(Expansion of Fig. 10- (ij)
~HITACHI
154
®)
-::----:-,---c:---:--:---t--------Vertlcal Display Period - - - - - - - - -
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - HD6845R/HD6845S
JJO "xm
. t:Bl~
J
.
,
I
'
I
~ .J~
:~
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
155
::c
o(l)
en
(l)
00
~
01
:xl
X
o
(l)
I
Line "1
Lone "'0
00
Line ""2
~
01
CJ)
:I:
I
i>1
";!.
RA.-AA.
»
o
1 11' 131-------1
o
N,
1 1 1 ' 1 3 1- - - - - - - 1
N,
1
0
1 1 I ' 1
3
1 - - - - - - -I
N,
/--- ----- . . ,'©
3
CD
6
: n n n
CUDISP
'p.."
!:
\
J
" --------- /
Figure 14 Relation between Line' Raster and CUDISP
N
N
a
0
oi@
Q. •
'7"
MAo -MA,
CD
~
::>
~
cnO
RAo-AA.
CD
'" ::t
:::l
I
- - - - - - -I
Nnl" !\In,
-------1
1 NhO 1
I
::t
C
Nhd
1 NhO 1
-------1
Nhd + Nh
Nh
'"Y'''''
'7"
NhtJ
I
1
1- - - - - - -I
I
I
I
I
I
rCUOISP
t-
o(f)
5"
Cursor register = Nhd+2
()
»
(
«>
c;.
~
)
Cursor Start
Raster Register = 1
Cursor End
Raster Register = 3
are Programmed m cursor dIsplay mode
~
0
.,.
'"Co
'"
$
In bltnk mode, It IS changed Into display or
non-dlsplay mode when field period IS 16 or
c;.
0
0
Figure 15 CUDISP Timing (Expansion of Fig. 14. ©)
1
32-tlme penod
I
~
Raster address ~
Line number
-=t ,? ' char
~
'0
»
3
~
g
!'l-
:.
~
"!!
<5
o
~ I)
>
is
(}~
•
!2.
2
0
I
Nhd·'
Nhd
I
I
0
I
I
I
I
Nhd
Nhd+l
Nhd
Nhd+l
I
2Nhd
2Nhd+l
I
2Nhd
2Nhd+ 1
I
j
I
C
\
«>
S
~::I
~
~
(flO
~ ::I
<-
g
~
()
»
CD
r.n
~
~
I
I
I
I tNvd- 1 I Nhd Hvlf.l1 Nhd+l
•r INlld-l).Nhd
I
I
(Nvd-lINhd+l
NVd-{
~
i.
I
!
Nvd
,
I
Nvd Nhd+ 1
I
Nvd Nhd+ 1
j
j
!
Nvt·Nhd
Nvt -Nhd+ 1
NI,
Nvt·Nhd
) )
Il~
Nvt
>
Nvd·Nhd
Nvd·Nhd
N
~
a:
HOrizontal Retrace Penod
\ /
C,
[
c;"
III
!;
HOrizontal Display Period
\
I
I
I
Nvt ·Nhd+l
~ ,Nvt+ tNhd Nvt+'l.,.hd+
Nad,· i (Nvt+l).Nhd Nvt+l1-Nhd+
---
Nhd-l
Nhd
2Nhd-l
2Nhd
I
2Nhd
3Nhd
I
3Nhd·'
I
I
-----
--
I
2Nhd·'
3Hhd-l
I
3Nhd
Nvd Nhd
I
Nvd Nhd·'
I
Nvd Nhd
(Nvd+l)Nhd·' (Nvd+ lJNhd
I
I
I
I
(Hvc1+1)Nhd-1 tNvd+ ')Nhd
I
(Hvt+ 1lNhd
I
(Hvt+ ljNhd 1
(Nvt+l )Nhd
(Nvt+2JHhd-l
INIJt+21·Nhd
I
I
Nht
---
I
Nvd Nhd-'
(Nvt+l}Nhd·'
Nht
I
(Nvt+2I Nhd.lj(Nvt+2).Nhd
Nhd+Nht
I
Nhd+Nht
2Nhd+Nht
I
2Nhd+Nht
I
---
(Nvd 1) Nhd+NhI
I
(Nvd 1) Nlw:t+ Hhl
Nvd Nhd+Nhl
I
Nvd Nhd+Hht
I
--
--
HVI NM+Nht
I
Nvt Nhd+Nht
Valid refresh memory address (O...... Nvd·Nhd-1)
are shown within the thick·line square.
Refresh memory address are provided even
during hOrizontal and Vertical retrace period.
This IS an example in the case where the
programmed value of start address register is O.
(NVI+l)Nhd+Nhl
I
NvHlINhd+N"',
~
~
Figure 16 Refresh Memory Address (MAo-MA 13 )
:r
o
OJ
(Xl
+>
(J1
J:I
:co
(J1
.....
OJ
(Xl
+>
(J1
(Jl
HD6845R/HD6845S-----------------------------------------------------------• How to Use the CRTC
• Interface to MPU
As shown in Fig. 17, the CRTC is connected with the standard bus of MPU to control the data transfer between them. The
CRTC address is determined by CS and RS, and the Read/Write
operatIOn is controlled by R/W and E. When CS 1S "Low"
and RS 1S also "Low", the CRTC address register 1S selected.
When CS is "Low" and RS is "High", one of 18 internal regis-
ters is selected.
RES is the system reset signal. When RES becomes "Low",
the CRTC internal control logic is reset. But internal registers
shown in Table I (RO- R17) are not affected by RES and remain unchanged.
The CRTC 1S designed so as to provide an interface to microcomputers, but adding some external circuits enables an interface to other data sources.
Ao - A15
RS
DECODER
VMA
cs
R/W
R/W
CRTC
HD6800
MPU
E
Do - 07
°0-D 7
RES
RES
Sv stem ¢2 clock
RES
Figure 17 Interface to MPU
•
Dot Timing Generating Circuit
CRTC's CLK mput (21 pm) 1S prov1ded with CLK wh1ch
defines honzontal character time period from the outs1de.
This CLK 1S generated by dot counter shown in F1g. 18. F1g.
18 shows a example of circuit where honzontal dot number
of the character 1S "9". F1g. 19 shows the operation I1me chart
of dot counter shown m F1g. 18. As this example shows exphC1tly, CLK 1S at "Low" level !n the former half of horizontal
character I1me and at "H1gh" level !n the latter half. It 1S necessary to be careful so as not to m1stake th1S polarity.
L-_----<...._ _ lOAD PIS REG-N
-+________________
L-________
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _
DOTCP-P
l
to PIS SHI FT
REGISTER
CHCP-P to CRTC (ClK)
Figure 18 Example of Dot Counter
~HITACHI
158
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6845R/HD6845S
6
8
0
23456780
2
3
4
7
8
0
DOTCP-P
a.
a,
a,----..L...-+-_ _ _...J
a, ___....J
lOAD PIS AEG-N
CHCP-P (ClK)
I - - - - O n . Honzontal-----l
Character Time
Figure 19 Time Chart of Dot Counter
• INTERFACE TO DISPLAY CONTROL UNIT
Fig. 20 shows the interface between the CRTC and display
control unit. Display control unit is mamly composed of
Refresh Memory, Character Generator, and Video Control
circuit. For refresh memory, 14 Memory Address line
(0-16383) max are provided and for character generator, 5
Raster Address line (0-31) max are provided. For video control
cirCUit, DISPTMG, CUDISP, HSYNC, and VSYNC are sent
out. D1SPTMG IS used to control the blank penod of video
signal. CUDISP IS used as video signal to display the cursor on
the CRT screen. Moreover, HSYNC and VSYNC are used as
drive SignalS respectively for CRT honzontal and vertical deflec·
lion CirCUitS.
Outputs from video control circuit, (video signals and sync
signals) are provided to CRT display unit to control the
deflection and brightness of CRT, thus characters are displayed
on the screen.
Fig. 21 shows detailed block diagram of display control unit .
ThiS shows how to use CUDISP and DISPTMG. CUDISP and
DISPTMG should be used bemg latched at least one lime
at external fllp·flop FI and F2. Fhp·flop FI and F2 functIOn
to make one-character delay lime so as to synchrOnize them
with video Signal from parallel-serial converter. High-speed
D type flip-flop as TTL IS used for thiS purpose. After bemg
delayed at FI and F2 DISPTMG IS AND-ed with character
video signal, and CUDISP IS Or-ed With output from AND
gate. By using thiS ClfCUltry, blankmg of honzontal and verlical
retrace lime is controlled. And cursor video IS mixed With
character video signal.
Fig. 21 shows the example in the case that both refresh
memory and Character Generator can be accessed for honzontal
one character lime. Time chart for thiS case IS shown m Fig. 24.
This method IS used when a few character needed to be displayed In honzontal dlfectlon on the screen.
~HITACHI
Hitachi Amertca Ltd • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
159
HD6845R/HD6845S-------------------------------------------------------
14max
Refresh
Memory
6 max
Character
Generator
MA
RA
II
CRTC
~
DISPTMG
V Ideo Control
HSYNC
Sync
Sognals
VSYNC
ClK
0
Vodeo
Signals
CUDISP
0
0
I
f
Figure 20 Interface to Display Control Unit
Fl
CUDISP
CHCP·N
F2
DISPTMG
VIDEO
CRTC
MA
P
Refresh
Character
Memory
Generator
~
5
RA
ClK
CHCP·P
DOT COUNTER
OSC
Figure 21 Display Control Unit (1)
•
160
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6845R/HD6845S
When many characters are displayed in horizontal direction
on the screen, and honzontal one-character time is so short
that both refresh memory and Character Generator cannot be
accessed, the circuitry shown in Flg_ 22 should be used. In thIs
case refresh memory output shall be latched and Character
Generator shall be accessed at the next cycle. The time chart
in thIs case IS shown in Fig. 25 CUDISP and DISPTMG should
be provided after being delayed by one-character time by using
skew bit of mterlace & skew register (R8). Moreover, when
there are some troubles about delay time of MA during horizontal one-character I1me on high-speed display operation,
system shown in Fig. 23 IS adopted. The time chart m this case
IS shown in Fig. 26. Character video SIgnal is delayed for twocharacter time because each MA outputs and refresh memory
outputs are latched, and they are made to be m phase with
CUDISP and DISPTMG by delaymg for two-character time.
Table 10 shows the Clfcultry selection standard of display units.
Table 10 Circuitry Standard of Display Control Unit
Case
1
2
3
tCH
> RM Access + CG Access + tMAD
RM Access + CG Access + tMAD £ tCH > RM Access + tMAD
RM Access + tMAD £ tCH > RM Access
tCH
CHCP Penod, tMAD
Interlace & Skew Register
Bit Programming
Block
Diagram
Relation among tCH Refresh Memory and Character Generator
Cl
CO
Dl
DO
Fig. 21
0
0
0
0
Fig. 22
0
1
0
1
Fig. 23
1
0
1
0
MA Delay
RM. Refresh Memory CG Character Generator
Fl
CUDISP
CHCP-N
DISPTMG
CRTC
P
MA
Refresh
Memory
S
RA
ClK
CHCP·P
L -_____________________________________ I
DOT COUNTER
OSC
Figure 22 Display Control Unit (2)
Fl
CUDISP
DISPTMG
CRTC
MA
l
A
T
C
H
Refresh
Memory
(21
RA
ClK
~----------------------------------~C~H~C~P!-P~ED~O~T~C~O~U~N~T~E~R~----1--1 0SC
Figure 23 Display Control Unit (For high-speed display operation) (3)
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
161
HD6845R/HD6845S---------------------------------------------------------
CHCP·P
MA
DISPTMG
--+---~
CUDISP
- - t - - -.......__"""'-t-------t-----'
F2·Q
Fl·Q
CGOUT
VIDEO
--+---'
-+------' \
CRT DISplay
•••••••
Figure 24 Time Chart of DISplay Control Unit (1)
CHCP·P
MA
DISPTMG
CUDISP
--4-------~----~_+--~--~----"
F2·Q
Fl·Q
CGOUT
VIDEO
CRT DISplay
•••••••
Figure 25 Time Chart of DISplay Control Unit (2)
~HITACHI
162
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6845R/HD6845S
-~ ~ ~ ~ ~ ~ L J
MA
-~
-~-\
DISPTMG
o
X
1
r- --------
\r-- r-
CUDISP
X
2
X
3
X
4
X
L
5
I
--=l r -----"'\
Two-Character skew
I
\
/
\
\
}
LATCH(2 )
F1-Q
I
--
--~"Illlh
~r
~
r - - - - ~ ;YilllC2 r-_........2.
- - - - "JIllii
......
---
--y-ro
---~
- - -~~
-~ Yx- ...... --Tx1" r
LATCH!1 )
CGOUT
4
3
1\
\
F2-Q
RMOUT
2
1
0
0
1
.......
h
r----
~--
VIDEO
\
CRT Dl5pla y
••••
~
4
3
2
X
......
..
Figure 26 Time Chart of Display Unit (3)
• HOW TO DECIDE PARAMETERS SET ON THE CRTC
•
How to Decide Parameters Based on Specification of CRT
Display Unit (Monitor)
Number of Horizontal Total Characters
Horizontal deflection frequency fh is gIven by specification
of CRT display unit. Number of horizontal total characters IS
determined by the follOWing equation.
fh
=
I
te (Nhl
+ I)
where,
te
Cycle Time of CLK (Character Clock)
Nhl : Programmed Value of Horizontal Total RegIster
(RO)
Number of Vertical Total Characters
Vertical deflectlon frequency is given by specification of
CRT dIsplay umt. Number of vertical Total characters is
determined by the followmg equatIOn.
I) Non-interlace Mode
Rt = (Nvt + I) (Nr + I) + NadJ
2) Interlace Sync Mode
Rt = (Nvt + I HNr + I) + NadJ + 0.5
3) Interlace Sync & VIdeo Mode -
Rt=
(Nvt + I) (Nr + 2). + 2NadJ
2
............. (a)
Rt = (Nvt + I )(Nr + 2) + 2NadJ +I
2
(b)
(a) is applied when both total numbers of vertIcal characters
(Nvt + I) and that of rasters m a Ime (Nr + 2) are odd.
(b) is applied when total number of rasters (Nr + 2) IS even, or
when (Nr + 2) is odd and total number of vertical characters
(Nvt + I) IS even.
where,
Rt
Number of Total Rasters per frame
(Including retrace period)
Nvt
Programmed Value ofVerttcal Total
RegIster (R4)
Nr
Programmed Value of Maximum Raster
Address Register (R9)
Programmed Value of Vertlcal Total Adjust
Register (RS)
Horizontal Sync Pulse Width
Honzontal sync pulse WIdth IS programmed to low order
4-blt of honzontal sync WIdth regIster (R3) m unit of honzontal
character time. Programmed value can be selected wlthm from I
to 15.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
163
HD6845R/HD6845S------------------------------------------------------Horizontal Sync Position
Vertical Sync Position
As shown in Fig. 27, horizontal sync position is normally
selected to be in the middle of horizontal retrace period. But
there are some cases where is optimum sync position is not
located in the middle of horizontal retrace period according to
specification of CRT. Therefore, horizontal sync position
should be determined by specification of CRT. Horizontal sync
pulse position is programmed in unit of horizontal character
time.
As shown in Fig. 28, vertical sync position is normally
selected to be in the middle of vertical retrace period. But there
are some cases where its optimum sync position is not located in
the middle of vertical retrace period according to specification
of CRT. Therefore, vertical sync position should be determined
by specification of CRT. Vertical sync pulse position is pro·
grammed to vertical sync position register (R 7) in unit of line
period.
I'
OISf"TMG
---.J
1
•
• How to Decide Parameters Basad on Screen Format
Dot Number of Charaeta,. (Horizontal)
Dot number of characters (horizontal) is determined by
L-
I
I- =:;::.. -+=:':.:,,::4-- ~::r:::~od --I ,
HSVNC-"Io---------"n---------
character font and character space. An example is shown in Fig.
29. More strictly, dot number of characters (horizontal) N is
determined by external N·counter. Character space is set by
means shown in Fig. 30.
Dot Number of Characters (Vertical)
Dot number of characters (vertical) is determined by
characters font and line space. An example is shown in Fig. 29.
Dot number of characters (vertical) is programmed to maximum
raster address (R9) of CRTC.
Figure 27 Time Chart of HSYNC
Vertical Sync Pulse Width
Vertical'Sync Pulse Width is programmed to high order 4·bit
of vertical sync pulse width register (RJ) in unit of raster
period. Programmed value can be selected within from I to 16.
t----- Vertical
Displey Period
j•
I
-""1-jSJ 1 1
DISPTMG---.Ji--""I
I
Vertical
Retrace Period
1
'I '
.--------I
I
i-I--r......,I~J~
Vertical
Displey Period
1 Frame------
VSYNC ______________________
~nL
________________________
Figure 28 Time Chart of VSYNC
Character Font
r
'-..
Don Number of
HOrizontel Characte~
arBeter
•• •• •
•
•
•
•
•
• •
•
••
•
•
•
• •• •• • •
•
•
•••
•
••• • • •
•
••
• • • ••
•
•
Dot Number of
Vertical Characte..
(Number of Rastersl
•
J
Line
Spece
Dot Number of Horizontal Charecter.
{ Dot Number of Vertical Characters
7x9 Cheracter generator used.
I.
10
13
Figure 29 Dot Number of Horizontal and Vertical Characters
•
164
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6845R/HD6845S
Character Font
\
•••••
•
•
•
•
•
•
• • ••
•
•
•
•
•
•
• • • ••
Sena I Data
"0"
..0 ....0 ..
I
I I
I I I I I I I
Shift Register
F,gure 30 How to Make Character Space
Horizontal Deflection Period (th) =
Honzontal Display Period
1
fh
Honzontal Retrace Period
Number of Horizontal Displayed Characters
~
HOrizontal Display Period
Honzontal Character Time
= --:-:--:----:--'-:---'------:--:-::-----:-----:-===Number of Horizontal Displayed Characters
F,gure 31 Number of Horizontal D,splayed Characters
Number of Horizontal Displayed Characters
Number of horizontal displayed characters is programmed to
horizontal displayed register (RI) of the CRTC. Programmed
value is based on screen format. Horizontal display penod,
wluch is given by specIfication of horizontal deflection fre·
quency and horizontal retrace penod of CRT display unit,
determines horizontal character time, being divided by number
of horizontal displayed characters. Moreover, its cycle time and
access time which are necessary for CRT display system are
determined by horizontal character time.
Number of Vertical Displayed Characters
Number of vertical displayed characters is programmed to
vertical displayed register (R6). Programmed value is based on
screen format. As specification of vertical deflection frequency
of CRT determines number of total rasters (Rt) including verti·
•
cal retrace penod and the relation between number of vertical
displayed character and total number of rasters on a screen is
as mentioned above, CRT which is suitable for desired screen
format should be selected.
For optimum screen format, it is necessary to adjust number
of rasters per line, number of vertical displayed characters, and
total adjust raster (Nadj) within speCification of vertical
deflection frequency.
Scan Mode
The CRTC can program three·scan modes shown in Table II
to interlace mode register (R8). An exampb of character display
in each scan mode is shown In Fig. 8.
HITACHI
HItachI Amenca Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
165
HD6845R/HD6845S--------------------------------------------------------Table 11 Program of Scan Mode
v
S
Scan Mode
Mam Usage
0
1
0
0
Non·mterlace
Normal D,splay of Characters
& Figures
0
1
Interlace Sync
1
1
Interlace Sync
& V,deo
[NOTE]
Fme Display of Characters
& F,gures
D,splay of Many Characters
& Flgure~ WIthout Using
Hlgh·resolutlon CRT
In the interlace mode, the number of times per
sec. 10 raster scannmg on one spot on the screen
is half as many as that 10 non·mterlace mode.
Therefore, when persistence of luminescence IS
short, flickering may happen. It IS necessary to
seiect optImum scan mode for the system, takmg
characterIstics of CRT, raster scan speed, and
number of displayed characters and f,gures into
account.
Cursor Display Method
Cursor start raster register and cursor end raster register
(RIO, RII) enable programming the display modes shown in
Table 7 and display patterns shown in Fig. 9. Therefore, it is
possible to change the method of cursor display dynamically
according to the system conditions as well as to realize the
cursor display that meets the system requirements.
Start Address
Start address resisters (RI2, R13) give an offset to the
address of refresh memory to read out. Th,s enables paging and
scrolling eas!ly.
Cu rsor Register
Cursor registers (RI4, RIS) enable programming the cursor
display position on the screen. As for cursor address, it is not X,
V address but linear address that is programmed.
• Applications of the CRTC
• Monochrome Character Display
Fig. 32 shows a system of monochrome character display.
Character clock signal (CLK) is provided to the CRTC through
OSC and dot counter. It is used as basic clock which drives
internal control circuits. MPU is connected with the CRTC by
standard bus and controls the CRTC initialization and read!
WrIte of internal registers.
Refresh memory is composed of RAM which has capacity of
one frame at least and the data to be displayed is coded and
stored. The data to refresh memory is changed through MPU
~====~~======================~~==================~AIS-Ao
MPU
REFRESH
MEMORY
IRAM)
RA
CRTC
OISPTMG
CUDISP
HSYNC
VIDEO
VIDEO
SYNC
CONTROL
SIGNAL
0
0
0
VSYNC
Figure 32 Monochrome Character Display
.HITACHI
166
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD6845R/HD6845S
bus, while refresh memory is read out successively by the CRTC
to display a static pattern on the screen. Refresh memory is
accessed by both MPU and the CRTC, so it needs to change its
address selectively by multiplexer. The CRTC has 14 MA
(Memory Address output), but in fact some of them that are
needed are used according to capacity of refresh memory .
Code output of refresh memory is provided to character
generator. Character generator generates a dot pattern of a
specified raster of a specified character in parallel according to
code output from refresh memory and RA (Raster Address
output) from the CRTC. Parallel-serial converter is normally
composed of shift register to convert output of character
generator into a serial dot pattern. Moreover, D1SPl'MG,
CUDlSP, HSYNC, and VSYNC are provided to video control
CIrCUit. It controls blanking for output of parallel-serial converter, mixes these signals with cursor video signal, and generates sync signals for an interface to monitor.
• Color Character Display
Fig. 33 shows a system of color character display. In this
example, a 3-bit color control bit (R, G, B) is added to refresh
memory in parallel with character code and provided to video
control circuit. Video control circuit controls coloring as well
as blanking and provides three primary color video signals (R,
G, B signals) to CRT display device to display characters in
seven kinds of color on the screen.
1====;-r============;r=====~AIS -Ao
MPU
~==~~~==========~===~=>D,-Do
Configuration of the Refresh Memorv
REFRESH
MEMORY
(RAM)
CRTC
Blink
RA
COLOR BIT IR, G, B)
DISPTMG
R. VIDEO
CUDISP
G. VIDEO
VIDEO CONTROL
HSYNC
B. VIDEO
0
0
0
VSYNC
SYNC SIGNAL
Figure 33 Color Character Display
• Color limited Graphic Display
Umited graphic display is to display simple figures as well as
character display by combination of picture element which
are defmed in unit of one character.
As shown in Fig. 34, graphic pattern generator is set up in
parallel with character generator and output of these generators are wire-ORed. Which generator is accessed depends on
$
coded output of refresh memory.
In this example, graphic pattern generator adopts ROM, so
only the combination of picture elements which are programmed to it is used for this graphic display system. Adopting RAM
instead of ROM enables dynamically writable symbols in any
combination on one display by changing the contents of them.
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA l5131 • (408) 435-8300
167
HD6845R/HD6845S-------------------------------------------------------
1===:::::;-r============:;r=======~Au-Ao
MPU
MA
REFRESH
MEMORY
IRAMI
CRTC
COLOR BIT IR, G, BI
R. VIDEO
G. VIDEO
CUDISP
VIDEO CONTROL
HSYNC
VSYNC
~======~~~~-JL-
B. VIDEO
o
o
______________________
--JSYNCSIGNAL
Figure 34 Color Limited Graphic Display
~HITACHI
168
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6845R/HD6845S
• Monochrome Full Graphic Display
Fig. 35 shows a system of monochrome full graphic display.
While simple graphic display is figure display by combination of
picture elements in unit of I picture elements, full graphic display is display of any figures in unit of I dot. In this case,
refresh memory is dot memory that stores all the dot patterns,
so its output is directly provided to parallel·serial converter to
be displayed. Dot memory address to refresh the screen is set
up by combination of MA and RA of CRTC.
r-MPU
---~
OSC
MA
COUNTER
RA
BUS DRIVER]
1
MULTIPLEXER
H
DOT MEMORY
(RAM)
CRTC
P
11
-
S
J
DISPTMG
HSYNC
VIDEO
SYNC
VIDEO
CONTROL
SIGNAL
0
0
0
VSYNC
Figure 35 Monochrome Full Graphic Display
.HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
169
HD6845R/HD6845S-----------------------------------------------------------Fig. 36 shows an example of access to refresh memory
by combination ofMA and RA. Fig. 36 shows a refresh memory
address method for full graphic display. Correspondence be-
tween dot on the CRT screen and refresh memory address is
shown in Fig. 37.
RA,
RA,
RA,
MA,
MA,
MA,
MA,
MA,
MA,
MA,
MA,
MA,
MA,
CRTC
mall
mall
malO
~I
-
rna,
rna,
rna,
rna,
rna,
rna,
rna,
rna,
rna,
rna,
Refresh Memory
Address
Figure 36 Refresh Memory Address Method for Full Graphic Display
32 Characters x 8 dots = 256 dots
I
8 rasters
11 line)
0
32
64
96
224
b' I
./ 1 b yte 18-It
1
33
65
97
31
63
95
127
255
225
:
241lne5
:
x 8 rasters
:
= 192 rasters
,
6112
6148
6113
\
Value of rna
Figure 37 Memory Address and Dot Display Position on the Screen for Full Graphic Display
~HITACHI
170
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6845R/HD6845S
•
Color Full Graphic Display
their output is provided to three parallel·serial converters. Then
video control circuit adds the blanking control to output of
these converters and provides it to CRT display device as red,
green, and blue video signals with sync signals.
Fig. 38 shows a system of color full graphic display by 7·
color display.· Refresh memory is composed of three dot
memories which are respectively used for red, green, and blue.
These dot memories are read out in parallel at one time and
r--MPU
0........-
OSC
DOT
COUN·
TER
r
BUS
DRIVER
MA
BUS
DRIVER
BUS
DRIVER
RA
Jill
MULTIPLEXER
B
G
R
DOT
MEMORY (RAM)
CRTC
16
It
P
-
S
]J
RED VIDEO
DISPTMG
HSYNC
VIDEO
CONTROL
GREEN
VIDEO
BLUE
VIDEO
0
0
0
VSYNC
SYNC SIGNAL
Figure 38 Color Full Graphic Display
• Cluster Control of CRT Display
The CRTC enables cluster control that is to control CRT
display of plural devices by one CRTC. Fig. 39 shows a system
of cluster control. Each display control unit has refresh memory,
character generator, parallel-serial converter, and video control
circuit separately, but these are controlled together by the
CRTC.
In this system, it is possible for plural CRT display devices to
have their own display separately.
@HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
171
I
o
CJ)
-..J
OJ
N
"'"
A1S~Ao
01
::0
J:
o
MPU
CJ)
OJ
"'"
en
01
I
~
:!
:P
3
~
coOJ
r:
c.
~
o
o
c}~
•
Q.
CD
l:I
:J
-
g ~
(flO
~
C-
:I
o
If>
OISPTMG
()
CUOISP
5"
:P
*
~
..
'"
HSYNC
§
VIDEO
CONTROL
VSYNC
$
en
Co
'"oo
~
~
o
o
~
L.::-J
o
o
Figure 39 Cluster Control by the CRTC
~
~
o
o
-------------------------------------------------------HD6845R/HD6845S
•
EXAMPLES OF APPLIED CIRCUIT OF THE CRTC
Fig. 41 shows an example of application of the CRTC to
monochrome character display. Its specification
IS
shown in
Table 12. Moreover, specification of CRT display unit is shown
in Table 13 and initializing values for the CRTC are shown in
Table 14.
Table 12 Specification of Applied CirCUit
Item
Specification
Character Format
5 x 7 Dot
Character Space
Horizontal: 3 Dot Vertical: 5 Dot
One Character Time
Ills
40 characters x 16 lines; 640 characters
Number of Displayed Characters
Access Method to Refresh Memory
Snychronous Method (DISPTMG Read)
Refresh Memory
640 B
2 15 214 :213 2'2 211 2 10 2"
Address Map
23 22
28
2'
26
2'
2'
x
x
x
X
x
x
X
X
X
0
{
x
x
X
X
X
X
"
x
1
Refresh
Memory
0
0
0
0
0
0
. . . . . . . . . 2".
CRTC
Address
Register
0
0
0
1
0
0
CRTC
Control
Register
0
0
0
1
0
0
21
x ... don't care, ••.• Oor 1
Synchronization Method
HVSYNC Method
Table 13 SpeCification of Character Display
Item
SpeCification
Scan Mode
Non'lnterlace
Honzontal Deflection Frequency
15.625 kHz
Vertical Deflection Frequency
60.1 Hz
Dot Frequency
8MHz
Character Dot (Horizontal x Vertical)
8 x 12 (Character Font 5 x 7)
Number of Displayed Characters (Row x Line)
40x 16
HSYNCW,dth
4 lIS
3H
VSYNCWidth
Cursor Display
Raster 9 - 10, Blink 16 Field Period
Paging, Scrolling
Not used
•
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
173
HD6845R/HD6845S--------------------------------------------------------Table 14 Initializing Values for Character Display
Register
Symbol
Name
InitialiZIng Value
Hex (Decimal)
RO
Horizontal Total
Nht
3F
Rl
HOrIZontal Displayed
Nhd
28
(40)
R2
Horizontal Sync POSition
Nhsp
34
(52)
R3
Sync Width
Nvsw, Nhsw
34
R4
Vertical Total
Nvt
14
R5
Vertical Total Adjust
08
( 8)
R6
Vertical Displayed
Nadj
Nvd
10
(16)
R7
Vertical Sync Position
Nvsp
13
(19)
R8
Interlace & Skew
R9
Maximum Raster Address
RIO
Cursor Start Raster
B, P, NCSTART
All
Cursor End Raster
NCEND
R12
Start Address (H)
R13
R14
R15
(20)
00
Nr
OB
(11)
49
OA
(10)
00
( 0)
Start Address (L)
00
( 0)
Cursor (H)
00
( 0)
Cursor (L)
00
( 0)
tc
1 J.LS
i01234567io123456J01234567I
1.lm:J.11
\
Cursor
11!!.1
III
Figure 40 Non-interlace Display (Example)
@HITACHI
174
(63)
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
...
.TTL
./fl
_hhhhhh~~~
•••
~~
••
ii,
O. D. 0
!!!!lW
::c
~
~ ~
:!
»
HD.6.T.6
'5. D.
5, If.
I
3
C Ml'U A _ (WhentlsP™G. 'a.-"j
l'
.J,
i
i
J
l~~~~~~~~~~=i~~~=====i~~~~========~S'~~~T~'.~======~~~~~[)~
H07400
I
I
=i
c:::=
H8
486
1i
____
i
'=
I
'
VIDEO-P
HVSYNC_P
FI,5IO
:::c
o
Ol
CO
"'"
U1
:0
J:
o
....
U1
Ol
CO
Figure 41 Example of Applied Circuit of the CRTC (Monochrome Character Displav)
"'~"
HD6845R/HD6845S - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
•
DISPLAY SEQUENCE AFTER
An
RELEASE OF HD6845S (I)
HD6845S starts the display operation immediately after the
release of RES. The operation at the first field is different from
the normal subsequent display operation.
[Operation at the first field after the RES release)
(2)
(3)
DISPTMG and CUDISP are not output. (They remain at
"Low" level. The display is inhibited.)
The data programmed in the start address register is not
used. (MA and RA start at "0".)
The sequences are shown in the following figures.
Display Operation Starts (first field)
elK
RES
------k'
MAx
0
Figure 42
RES Release Sequence
~--------.:;f,c::rs"t..:.f:.::'e::.:ld~--------__f--- Normal Operation
RES _
~--------~F,~.m~e~~~"=oo~------~
Adjust
~~~~D
~
n
n
$I
n
VSYN,!:.C_ _ _ _---..l
AdJust
Nvsp
L.._ _ _ _ _ _ _ _....J
#Nvt
:=0
#1
# Nvsp
L.._ _ _ _ _ _ _ _- - '
#Nvt
#0
#1
uNvsp
'-_ _ _ _ _ _ _ _ _ _,
n
L
Figure 43 RES Release Sequence in The Non-interlace Mode
~--------...:fc::ir~st'-f:.::'e:.:l:::.d---------+_-NOfmal
I_
OperatIon
I---------------------------Fr.me-------------------------~:'tl~----------Field ----------·-il----------Od~ F:eld
Even
Even. Fleldl-------~+_---------- Even
RA'~ ~
x;;;rx;;x;x X[;;[. ~ ~ ~
VSYN~C~~~__________~~L------"__N~__"__A._:d_J~U_.st.__"__' ____~~L-------0N>rt
____~
__A~_:d_'~u_st:__' __
0 __•__
'-____~rhL_______'__
N"__"___
:Ad _~'U_"s_t__" __
' __
" __
2
h~____________________~h~________________________~h~_____________________
V$YNC$
VSYNCt!
Interlace Sync Control
VSYNC(J:
Interlace Sync & Video Control (Nr+2=Even)
Interlace Sync & Video Control (Nr+2=Qdd, Nvt=Odd, Nvsp=Even)
Interlace Sync & Video Control (Nr+2=Qdd, Nvt=Qdd, Nvsp=Qdd)
Figure 44 RES Release Sequence in The Interlace Mode (1)
1-________-'f~ir~st'_f:.::ie:.:I"'d__________+---Normal Operation
I.
~-----------------------Frame------------------------~17----------------
t ---------+---------- Even Field
Even leld
I
Odd Field
--------:f~------- Even---
RA'~~~~~~~
VSYN~C~C
I
Adjust
1
AdjUst: :
~~~----------------------~f1L--------------------~rh~--------____________________
_'h
h
hL._____________
____________
VSyN~c:::.@_ _ _ _ _
VSYNCC
VSYNC@
Interlace Sync & Video Control (Nr+2=Odd, Nvt=Even, Nvsp=Even)
Interlace Sync & Video Control (Nr+2=Odd, Nvt=Even, Nvsp=Odd)
Figure 45 RES Release Sequence in The I nterlace Mode (2)
~HITACHI
176
Adjust
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------------HD6845R/HD6845S
•
ANOMALOUS OPERATIONS IN HD6845S CAUSED BY REWRITING REGISTERS DURING THE DISPLAY OPERATION"
RegIster
#
Anomalous operatIons caused by rewriting registers & Conditions to avoid
Register Name
those operations
--
Rewrltlng**
OK or NG
r-----~-
X
0
RO
Rl
HOrizontal Total
The hOrizontal scan period IS dIsturbed
HOrizontal Displayed
There are some cases where the width of DISPTMG becomes shorter than the
R2
HOrizontal
Sync Position
R3
Sync Width
R4
Vertical Total
When a rewnte operation IS performed dunng the last raster period In the line, there IS
a possibility that the disturbance occurs dUring the vertical scan penod There IS no
problem of a reWrite operation dUring raster penod except this penod
6
Vertical Total
Adjust
When a rewrite operation IS performed In the last character time of the raster penod,
there are some cases where the numbers of Adjust Raster, specified by program, are
not added. (Only dUring the adjust raster penod)
6
R6
Vertical Displayed
After the moment of a rewnte operation, there are some cases where the Display IS
rnhlblted However, the display according to the programmed value IS performed
from the next field
0
R7
Vertical Sync
Position
There are some cases where VSYNC IS placed on the posItion different from the
programmed value or the nOIse IS output
X
X
programmed value at the moment of a reWrite operation. An error operation
occurs only durmg one raster period
R5
I
X
There are some cases where HSY NC IS placed on the position different from
the programmed value or the nOise IS output
----,
When a rewnte operation IS performed at a "High" level on HSYNC pulse or VSYNC
pulse, there are some cases where the width pulse becomes shorter than the
programmed value at the moment of a rewnte operation
jI,
--
R8
Interlace & Skew
Neither scan mode bit nor skew bit IS rewritten dynamically
DynamiC Rewnte rnto scan mode bit and skew bit IS prohibIted
R9
MaXimum Raster
Addre5::i
The mternal operatIOn will be disordered by a rewrite operation
X
RlO
Cursor Start Raster
When a rewrite operation IS performed In the last character time of the raster
period, there are some cases where the Jitter occurs on the cursor raster or the cursor
IS not displayed correctly. There IS also a possibility that the blink rate becomes
temporally shorter than usual.
6
Rll
Cursor End Raster
When a rewrite operation IS performed 10 the last character time of the raster period,
there are some cases where the jitter occurs on the cursor raster or the cursor
IS not displayed correctly Moreover, there are also some cases where the blink rate
becomes temporally shorter than normal operation
jI,
R12
Start Address (H)
0
R13
Start Address (L)
R12 and R13 are used rn the last raster period of the field A rewrite operation can
be performed except dUring this period However, when R 12 and R 13 are rewritten In
each field separately, the display operation, whose start address IS determrned
temporally by programming sequence, Will be performed.
A rewrite operation should be performed dUring the hOrizontal/vertical display
period.
R14
Cursor (H)
0
R15
Cursor (L)
When a rewrite operation IS performed dunng the display period, there are some
cases where the cursor IS temporally displayed at the address different from the
programmed value. A rewrrte operation should be performed durmg the hOrlzontal/
vertical retrace penod. Also, when R14 and R15 are rewntten rn each fletd separately,
the cursor IS displayed temporally at the temporal address determined by programmmg
sequence
------- -_.
I
----~-------.
-_._---
0
0
means temporary abnormal operatIOns In rewntlng the Internal register dunng the display operation Normally, after a rewrite operation,
the LSI performs the speCified display operation from the next field
(The operations In this table are outside our guarantee and are regarded as matenals for reference)
.. {~
X .
A reWrite operation IS possible without affecting the screen In the display so much.
If conditions are satisfied, a rewrite operatIon IS possible If conditIOns are not satisfied, there are some cases where a flicker and
so on occur temporally
When a rewrite operation IS performed, there are some cases where a flicker and so on occur temporally.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
177
HD6845R/HD6845S-----------------------------------------------------------• COMPARISON BETWEEN HD6845S AND HD6845R
• Comparison of function between HD6845S and HD6845R
No.
Functional Difference
Interlace
Sync
&
Video Mode
DISplay
1-106845
HD6845S
Programming Cnaracter line address.
Method
of
N~~r~r~aff
Characters
Character line address
I
0 ~_~_~______________________________ rrog~ammlngb
~~~er~I~~lum
of vertical
1 ---------------------------------- characters
2
characters
2 ------------------------------
3r-----------------~
4r-------______________
~
5r-------____________~
6r---------------______~
7~-------.--------------~
8r-__________________~
3 --- - -- - - -- --- -- --- - - -- - - ---- - --.--
4 ----- -- - - -- ---- - - - - --- -- ---- ----
9L-__________________~
In H06845, number of characters is vertically programmed In unit of two lines, as Illustrated above.
(Number of vertical total characters, Number of
vertical displayed characters, Vertical Sync POSItion)
Number of
Rasters Per
Character
Line
I r - - - - - - - - - - - - - ,...,
0 ABC
u:~~i~~~~~~gber
er 1
In HD6845S, number of characters IS vertically programmed In unit of one line, as illustrated above.
(Number of vertical total characters, Number of
vertical displayed characters, Vertical Sync POSItion)
Example of above figure
Example of above figure
Programmed number into Vertical Displayed
Register = 5
Programmed number Into Vertical Displayed
Only even number can be specified.
Both even number and odd number can be specified
Character I ine address
Character line address
Register = 10
~
Character line address
!h--h--l-'lt ~-"8""--- ---t--'}.
-4>---------9--3
:~~JO
r--Number of raster
a
= 10 scan
line (specified)
However, number which IS programmed IOto register IS calculated at follows.
Programmed number (Nr)
== (Number specified) - 1
6~:-::1r::7
--------------.O}
i~---~~~-~-~-~~;} ~3~~'
------- --3
:-------- --5
-- ~-e -0-----7
8 ____ ____ _ 9
Number of raster
4~50
,
;~6
----------- ---8
When number of raster
per character line IS
ODD
Number of raster
== 9 scan line
(speCified)
When number of raster
per character line is
EVEN.
Number of raster
== 10 scan line
(specified)
However, number which IS programmed into register
IS calculated as follows.
Programmed number (Nr)
== (Number specified) -2
Cursor
Display
Cursor IS displayed In either EVEN field or 000
field.
Cursor IS displayed
field.
In
both EVEN field and ODD
0----------
---------------,
-EVEN number
~~3 _EVEN number
-EVEN number
6~5
8---------------7
o ____________ ,
2 -e-e-G-~_o_--3 -ODD number
4 --o.._o_-e--o-_o_--5 -ODD number
6
______ ___ 7
8--------
-EVEN number
~---------------,
=~_:_i_~_itit-::3 -ODD number
4~5
6--------
-ODD number
8 --------------7
0---------
---------------,
2~
-EVEN number
4~~ -ODD number
6______
_
_ --7
8----------
(to be continued)
~HITACHI
178
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD6845R/HD6845S
No.
Funcllonal Difference
HD6845R
HD6845S
.-~
2
Fixed at 16 raster scan cycle (16H)
Vertical Sync
Pulse Width
P i xed at 16
f.-
Programmable (1 ..... 16 raster scan cycle)
~
scan cycle
(VSYNC output)
Specified by
high order
4 bit of R3
-1
VS~
V~
R3~JJJJ
R3
Attached bits
Not used
3
SKEW Function
Honzontal Sync Width
@BJQJ
HOrizontal Sync
Width
Vertical Sync
Width
SKEW function IS newly Included
Not Included
In
DISPTMG,
CUDIS? signals
Attached byte
RS
Rs~vlsi
~vlsl
CUDISP DISPTMG
Not used
Example of D1SPTMG output
~Notskewed
~ne character skew
H
4
Start Address Register
5
RESET Signal (RES)
Impossible to READ
MAo "'-' MAl) Output
RAo - RA. Output
Other Outputs
1
J.
Two character skew
1 character time
2 character time
Possible to READ
Synchronous reset
Asynchronous reset
Output signals of MAo ..... MA IJ , RAo ..... RA .. ,
synchroOlzlng with DLK "Low" level, go to
"Low" level, after RES has gone to "Low"
Other outputs go to "Low" Immediately after
RES has gone to "Low" level
• COMPATIBILITY OF HD6845S AND HD6845R
Non-tnterlace mode control }. Fully compatible with HD6845R*
Interlace sync mode control 'HD6845Rcanbedirectlyreplaced
by HD6845S in these modes.
Interlace sync & VIdeo mode control.
Not compatible with HD6845R
in regard to programming and
MAo ....... MAn Outputl
RAo ..... RA4 OutPUt
Other Outputs
J
. . Asynchronous reset
Output signals of MAo"'" MA l3 , RAo ..... RA .. and
others go to "Low" ievellmmedlately after R"ES
has gone to "Low" level.
--
data for vertical direction need to
be changed.
* The functions added to HD6845S utilize undefined bits of the
Control Register in HD6845R. If "0" is programmed to the
undefined bits in the initial set, it is possible to replace
HD6845R with HD6845S without changing the parameters.
Note) The restriction on programming of HD6845S and HD6845R
should be taken into consideration.
~HITACHI
Hitachi Amenca Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
179
HD6845R/HD6845S---------------------------------------------------------
~HITACHI
180
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
HD6350, HD6850
Asynchronous Communications
Interface Adapter (CMOS) (NMOS)
The HD6350/HD6850 Asynchronous Communications Interface Adapter provides the data formatting and control to
interface serial asynchronous data communications information
to bus organized systems such as the HMCS6800 Micro-processing Unit.
The bus interface of the HD6350/HD6850 includes select,
enable, read/write, interrupt and bus interface logic to allow
data transfer over an 8-bit bi-directional data bus. The parallel
data of the bus system is serially transmitted and received by
the asynchronous data interface with proper formatting and
error checking.
The functional configuration of the ACIA is programmed
via the data bus during system initialization. A programmable
Control Register provides variable word lengths, clock division
ratios, transmit control, receive control, and interrupt control.
For peripheral or modern operation three control lines are
provided.
HD6350P, HD6850P
(DP-24)
•
PIN ARRANGEMENT
FEATURES
• Serial/Parallel Conversion of Data
• Eight and Nine-bit Transmission
• Optional Even and Odd Parity
• Parity, Overrun and Framing Error Checking
• Peripheral/Modem Control Functions (Clear to Send CTS,
Request to Send RTS, Data Carrier Detect DCD)
• Optional-;- 1,+ 16, ancl+ 64 Clock Modes
• One-or Two-Stop Bit Operation
• Double Buffered
-H06350• Low-Power, High-Speed, High-Density CMOS
• Compatible with NMOS ACIA (HD6850)
• Wide Range Operating Voltage (Vcc = 5V ±10%)
• Up to 1Mbps Transmission
- HD6850• Compatible with MC6850 and MC68A50
• Up to 500Kbps Transmission
(Top View)
TYPE OF PRODUCTS
Type
Process
HD63A50
CMOS
HD68A50
•
Package
1.5MHz
DP-24
2.0MHz
HD63B50
HD6850
Clock Frequency
1.0MHz
HD6350
NMOS
1.0MHz
DP-24
1.5MHz
Flat Package in Development for HD6350
~HITACHI
Hitachi America Ltd • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
181
HD6350/HD6850--------------------------------------________________
• BLOCK DIAGRAM
Tx ClK 4
E
R/W
t
1 - - - - 8 TxD...
1-4_--24C'B
Do
D,
D,
D,
Do
Do
Do
D,
22
21
2D
II
7
ilW
~===-~~~~23~
II
17
r---~--4-4-----5
II
~
II
2
Ax Dato
IIxClK 3 - - - - -_ _ _ _~I 01....
• ABSOLUTE MAXIMUM PATINGS
Symbol
Item
Value
HD6350
HD6850
Supply Voltage
Vee "
-0.3-+7,0
-0.3-+7.0
Input Voltage
Vin"
-0.3-+7.0
-0.3-+7.0
Maximum Output Current"'
110 I
10
Operating Temperature
Topr
-20 -+75
Storage Temperature
Tstg
-55 -+150
Unit
V
V
-----
mA
°c
°c
-20 -+75
-55 -+150
• With respect to VIS (SYSTEM GNO)
** Maximum output current is the maximum current which can flow out from one
output terminal or 1/0 common terminal (Do -07, RTS, Tx Data, IRQ).
(NOTE)
Permanent LSI damage may occur if maximum fatings are exceeded. Normal
operation should be under recommended operating conditions. If these
conditions are exceeded, it could affect reliability of LSI.
• RECOMMENDED OPERATING CONDITIONS
HD6850
HD6350
Unit
typ max min typ max
~
Symbol
Item
.
min
Supply Voltage
Vee
4.5 5.0
5.25
V
Input "low" Voltage
Vil "
0
-
0.8 -0.3
-
0.8
V
2.0
-
Vee
-
Vee
V
2.2
-
Vee
-20
25
75
25
75
°e
Input "H igh"
Voltage
Do-D 7 , RS, Tx ClK, DC5,
Rx Data
CTS
eso , CS 2 , es., RIW, E, Rx ClK
Operating Temperature
VIH*
Topr
5.5 4.75 5.0
2.0
-20
• With respect to Vss (SYSTEM GNO)
f>HITACHI
182
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------HD6350/HD6850
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (HD63S0; Vee· SV ±lO%, HD68S0; Vee· SV ±S%, V,,· OV, Ta· -20 -+7SoC, unle•• otherwise noted.)
Symbol
Item
Telt Condition
HD6350
min
00 . . . 07. RS, Tx elK,
Ax Data
151m, E~,
Input "High" Voltage
CSo, cs" CS" A/iii, E
Ax ClK
max
2.0
-
Vee
2.2
-
Vee
V IH
Input "Low" Voltat.
All Inputs
Vil
Input Leakage Current
A/iii, CSa, CS" CS" E
I in
Vin·O"'" Vee
-2.5
00 - 0 7
ITS I
Vin • 0.4 .... Vee
-10
Three-State (Off St8te)
Input Current
-0.3
IDH' -4oo~A
00"'" D7
Output "High" Voltage
VO H
Tx Data,"Fiff
IOH';;
-10~A
IOH'
-400~A
4.1
V cc
-o· 1
4.1
IOH $. -10~A
HD6650
typ.
Vee-0.1
-
-
Output Leakage Current
iRiS
ILDH
VO H "" Vee
-
-
C,n
1-1.0 MHz
-
-
-
Cout
-
l-l.0MHz
Vin '"
~, TxDa..
Output Capacitance
TIm
Vin"
av, Ta "" 2SoC,
av, Ta -
E -1.0 MHz
• Under transmitting an
Receiving operation
-
• Chip is not selected.
e500 kbps
E '1.0 MHz
-
• Under non transmitting
E' 1.6 MHz
-
E· 2.0 MHz
-
.500 kbp.
• Data bus
operation
Supply Current
2SoC,
E = 1.5 MHz
In
RIW
E .. 2.0 MHz
and receiving operation
elnput level (ExcePt E)
VIH min" V cc -O.8V
10
Vin • 0.4 - 2.4V
-
IOH •
-205~A,
-
-
0.4
10
IOH'
-lOO~A,
typ*
max
2.0
-
Vee
-0.3
-
O.B
V
-2.6
-
2.6
IJA
-10
-
10
IJA
2.4
-
-
V
2.4
-
-
V
-
-
0.4
V
-
-
10
IJA
-
12.5
Enable
IOl' 1.6mA, Enable
Pulse Width $. 25",1
VOH' 2.4V
12.5
7.6
10
5.0
Unit
min
Enable
Pu Ise W idth ~ 251o&s
IOH ·1.6mA
E, Tx ClK, Ax ClK,
AIW, AS, AX Data, CSo,
CS cs:, CTS i5Ci5
Vin - 0 - 6.26V
-
VOL
00"" 0 7
2.6
Pulse Width ~ 25",1
All Outputs
Input Capacitance
O.B
- - -
Output "Low" Voltage
IOftStata)
Test Condition
Vin' OV, Ta' 26°C,
1'1.0 MHz
-
Vin = av, Ta = 2SoC
1·1.0MHz
- - -
V
pF
7.6
10
pF
5.0
3
4
-
200
-
300
5
mA
250
Vil max - O.BV,
Power Dissipation
300
Po
626
mW
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
183
HD6350/HD6850--------------------------------------------------------•
AC CHARACTERISTICS (HD6350; Vee= 5.0V ±10%.HD6850; Vee= 5V ±5%. Vss = OV. Ta = -20-+75°C. unless otherwise noted.!
1. TIMING OF DATA TRANSMISSION
Symbol
Item
Test
Condition
+1 Mode
Minimum Clock Pulse
Width
+16,+64 Modes
PW CL
Fig. 1
+1 Mode
+16, +64 Modes
PW CH
r.-16, +64 Modes
Clock-to-Data Delay for Transmitter
Receive Data Setup Time +1 Mode
Receive Data Hold Time
IC
tTOD
tRDSU
+1 Mode
tRDH
IRQ Release Time
tlR
RTS Delay Time
tRTS
Rise Time and Fall Time (or 10% of the
pulse width if smaller)
tr,tl
900
-
600
-
900
-
600
-
Fig. 3
-
500
-
BOO
-
600
250
-
Fig. 5
250
-
Flg.6
-
Fig.6
Fig. 4
max
min
max
min
HD68S0
IHD68ASO
min
max
Unit
500
-
900
-
ns
-
280
-
600
-
ns
650
-
500
-
900
-
ns
450
-
2BO
-
600
-
ns
650
-
450
Fig.2
+1 Mode
Clock Frequency
max
min
HD63B50
HD63A50
HD6350
-
750
-
1000
-
500
-
1000
-
1500
-
BOO
-
540
-
460
-
1000
100
-
100
-
kHz
30
-
500
30
-
500
1200
-
900
-
700
-
560
-
4BO
-
400
-
1000
-
500
-
250
ns
-
ns
-
ns
-
1200
ns
-
1000
ns
-
1000
ns
2. BUS TIMING CHARACTERISTICS
1! READ
Item
Symbol
HD6350
Test
Condition
min
max
HD63A50
min
max
HD63B50
min
max
HD6850
min
max
HD68A50
min
max
Unit
Enable Cycle Time
teyeE
Fig. 7
1000
-
666
Fig.7
450
-
280
220
-
1000
PWEH
-
500
Enable "High" Pulse Width
Enable "Low" Pulse Width
PWEL
Fig.7
430
-
2BO
-
210
-
430
-
2BO
-
ns
-
40
-
140
-
140
-
ns
lBO
-
150
-
320
220
ns
Setup Time, Address and R/W Valid
lAS
Fig.7
80
-
60
Data Delay Time
tDDR
Fig. 7
-
290
-
Data Hold Time
tH
Fig. 7
20
100
20
tAH
Fig. 7
10
-
10
-
tEr' tEl
Fig. 7
25
-
25
Symbol
Test
Condition
min
to Enable Positive Transition
Address Hold Time
Rise and Fall Time for Enable Input
2!
-
100
450
25000
666
280
-
25000
ns
ns
20
100
10
-
10
-
ns
10
-
10
-
10
-
ns
25
ns
-
20
-
25
-
WRITE
Item
HD6350
max
HD63A50
min
max
H063B50
min
max
HD6850
min
Enable Cycle Time
leyeE
Fig. 8
1000
-
666
Fig. 8
450
-
280
220
-
1000
PWEH
-
500
Enable "High" Pulse Width
Enable "Low" Pulse Width
PWEL
Fig. 8
430
-
280
-
210
-
430
tAS
Fig. 8
80
-
60
-
40
-
165
-
80
-
60
Setup Time, Addre .. and R!W Valid
to Enable Positive Transition
Data Setup Time
450
max
25000
HD68A50
min
666
max
-
Unit
ns
280
25000
n.
-
280
-
ns
140
-
140
-
ns
-
195
-
80
-
ns
tDSW
Fig. 8
Data Hold Time
tH
Fig.8
10
-
10
-
10
-
10
-
10
-
ns
Address Hold Time
tAH
Fig. 8
10
-
10
-
10
-
10
-
10
-
ns
Rise and Fall Time for Enable Input
tEr' tEf
Fig. 8
-
25
ns
-
25
-
25
-
20
-
25
~HITACHI
184
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------HD6350/HD6850
Tx C l K - - C ] \ - ' H m i n
or
Rx ClK
PWCH
Figure 2 Clock Pulse Width, "High" State
Figure 1 Clock Pulse Width, "Low" State
O.BV
tTDD)l
Tx O.t.
_ _ _ _--'.
vee -2.0V."
~.-..ljO.:l.4~V----
Figure 4 Receive Data Setup Time (+1 Mode)
Figure 3 Transmit Data Output Delay
ffi
---4----+-,~~---
• (11 iROR., .... Tim••pplied to Rx O.ta Register reed operation.
(21 iRa R., •••• Tim•• ppll.d to Tx O.t. Register writ. operation.
(31 iRa R., •••• Tim •• pplled to control R.gl.t.r writ. TIE = 0,
RIE = 0 oper.tlon.
•• iRQ R.I •••• Time .pplled to Rx O.t. Register read oper.tion
right .ft.r r••d .t.tu. regllter, wh.n iRO I.....rted by Di:!l:i
riling edge.
Figure 5 Receive Data Hold Time (+1 Mode)
_.- 2.4V for H06860.
(Not.1 Not. that followings take pl.ce wh.n IRQ i.....rted by the
d.tectlon of tr.n.mit data regl.ter .mpty .tatu.. iRO I.
rel ...ed to "High" ••ynchronou.'y with E ,'gn.' wh.n
CTS go.. "High". (Ref.r to Figure 141
Figure 6 RTS Delay and I RQ Release Time
Enable
RS,CS, R/W _ _- J
O.t. Bus
Figure 7 Bus Read Timing Characteristics
(Read information from ACIA)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
185
HD6350/HD6850-----------------------------------------------------------
Enable
Data Bus
Figure S Bus Write Timing Characteristics
(Write information into ACIA)
Load B
Load A
5.0V (Vee)
(D. -D,. RTS. Tx Data)
(lROOnly)
RL - 2.4kn
Test
Test POint o-.,....~-.f4.--i
C
~
3kn
fOOpF
R
C = 130pF for D.-D,
= 30pF for RT5 and Tx Data
R*o 10kn for D. - D,.
pOint
5'OV
• HD6B40
R = l1kn for Do-D7
= 24kn for RTS and Tx Data.
RTS and Tx Data
All diode•• ,e.1520749 or Equivalent.
Figure 9 Sus Timing Test Loads
MARKING
ur--r--r--r--r--r-l--l--n-I
I
I
I
:::::,
'.00
I
I
I
I
I
I
I
I
I
I
I
I
I
~-L_-l __ -l__ ~;;;-~,;_-l __ -'__
I
'--
msec
START
BIT
D.
D,
0,
0,
D.
0,
0,
PARITY
BIT
STOP STOP
BIT BIT
f---------CHARACTER TIME @ 10 CPS (11 BITS) - - - - - - - - - 0 1
100 msec
Figure 10 110 Baud Serial ASCII Data Timing
~HITACHI
186
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
START
BIT
D.
D,
D,
D,
D,
PARITY STOP
BIT
BIT
D,
i-------CHARACTER TIME @ 15 & 30 CPS (10 B I T S ) - - - - - " 1
(SEE TABLE BELOW)
BAUD RATE
150
300
CHARACTERS/SEC
15
30
BIT TIME (m,.c)
6.67
3.33
CHARACTER TIME (msec)
66.7
33.3
BIT TIME.
SEC
BAUD RATE
Figure 11 150 & 300 Baud Serial ASC) I Data Timing
MARK
I
I
START
I
D,
D,
D,
D,
PARITY
STOP
STOP
NEXT
CHAR.
SPACE
Figure 12 Send a 7 Bit ASCII Char. "H" Even Parity
- 2 Stop Bits H = 4B I6 = 10010002
• ACIA OPERATION
• Master Reset
• DATA OF ACIA
ACIA is an interface adappter which controls transmission
and reception of Asynchronous serial data. Some examples of
serial data are shown in Figs. 10 - 12.
•
INTERNAL STRUCTURE OF ACIA
ACIA provides the following; 8·bit Bi·directional Data
Buses (Do - D7 ), Receive Data Input (Rx Data), Transmit
Data Output (Tx Data). three Chip Selects (CSo • CS I • C8;).
Register Select Input (RS). Two Control Input (Read/Write:
RIW. Enable: E). Interrupt Request Output(IRQ). Oear·toSend (CTS) to control the modem. Request·ta-Send (IUS).
Data Carrier Detect(DCl'» and Clock Inputs(Tx CLK. Rx CLK)
used for synchronization of received and transmitted data. This
ACIA also provides four registers; Status Register. Control
Register. Receive Register and Transmit Register.
24-pin dual-in-Iine type package is used for the ACIA. Inter·
nal Structure of ACIA is illustrated in Fig. 13.
ACIA has an internal master reset function controlled
by software. since it has no hardware reset pin. Bit 0 and
bit 1 of control register should be set to "11" to execute
master reset. also bit 5 and bit 6 should be programmed to
get predetermined RTS output accordingly. To release the
master reset. the data other than "11" should be written
into bit O. bit I of the control register. When the master
reset is released, the control register needs to be programmed
to get predetem1ined options such as clock divider ratios.
word length. one or two stop bits. parity(even. old. or none).
etc.
It may happen that "Low" level output is provided in
IRQ pin during the time after power-on till master reset.
In the system using ACIA. interrupt mask bit of MPU should
be released after the master reset of ACIA. (MPU interrupt
should be prohibited until MPU progranl completes the master
reset of ACIA.) Transmit Data Register (TDR) and Receive
Data Register (RDR) can not be reset by master reset.
~HITACHI
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
187
HD6350/HD6850------------------------------------------------------
r-------------------------------,
-i
~
I
I D.I 0.1 I I I I 0.1
ACIA
1::0.
TRANSMIT DATA REGISTER (TOR)
~+~
WRITE ONLY
0.
0.' OJ
0,
0,
T. o..!
SERIAL DATA OUT
i ~~ ~--_r--,_~~~~~~,_--r__,
}~!/JJJJ
D,
•
r
TO SERIAL CONVERTER)
D,
DATA
LINES
D.
FROM
0,
TO
DR
MPU
0,
CONTROL REGISTER ICR)
IR:.I·Tt ·141~.121'ClDI
D.
D.
WAITE
ONLY
~L~f---~f:C:V~tT~:G~:r:R~D~lf ' CSr' -lB'- ~rr r
r
IR'CLK
II
READ
ONLY
D.
0,
0,
OJ
D.
DOD
I
•
- -C
O
RECEIVE
INTe,.~RUPT
~~AD
MPU
~~6't:
CLOCK
TRANSMIT
CLOCK
Mf'U
A_ [)al.
SERIAL DATA IN
•
-
-
..FCD
~EAR
ENABLE
IAOI
REGISTER
:~~'?AL
:';'~~M
J
~~QUeST
;~ND
'-----...----'
~~t~T
CHIP SEL.ECT
FROM MPU
~1~~E'iS
MPU
ADDRESS
MODEM
DATA
g:~:t~R
FROM
MODEM
LINE
Figure 13 Internal Structure of ACI A
•
Tr...mit
A typical transmitting sequence consists of reading the ACIA
Status Register either as a result of an interrupt or in the
ACIA's tum in a polling sequence. A character may be written
into the Transmit Data Register If the status read operation has
indicated that the Transmit Data Register is empty. This
character is transferred to a Shift Register where it is serialized
and transmitted from the Transmit Data output preceded by a
start bit and followed by one or two stop bits. Internal parity
(odd or even) can be optionally added to the character and will
occur between the last data bit and the first stop bit. After the
first character IS written in the Data Register, the Status
RegIster can be read again to check for a Transmit Data Register
Empty condition and current peripheral status. If the register is
empty, another character can be loaded for transmission even
though the first character is in the process of being transmitted
(because of double buffering). The second character will be
automatically transferred into the Shift Register when the first
character transmission is completed. This sequence continues
until all the characters have been transmitted.
•
Receive
Data is received from a peripheral by means of the Receive
Data input. A divideobyoone clock ratio is provided for an
externally synchronized clock (to its data) while the divide-by16 and 64 ratios are provided for internal synchronization. Bit
synchronization in the divide-by-16 and 64 modes is initiated by
the detection of the leading mark-space transition of the start
bit. False start bit delection capability insures that a full half bit
of a start bit has been received before the internal clock is
synchronized to the bit time, As a character is being received,
parity (odd or even) wIll be checked and the error indication
will be available in the Status Register along with framing error,
overrun error, and Receive Data Register full. In a typical
receivIng sequence, the Status Register is read to determine if a
character has been received from a peripheral. If the Receiver
Da... Register is full, the character is placed on the 8-bit ACIA
bus when a Read Data command is received from the MPU.
When parity has been selected for an 8-bit word (7 bits plus
parity), the receiver strip the parity bit (07="0") so that data
alone is transferred to the MPI,I. This feature reduces MPU
programming. The Status Register can continue to be read again
to determine when another character is available in the Receive
Data Register_ The receiver is also double buffered so that a
character can be read from the data register as another character
is being received in the Sluft register, The above sequence continues until all characters have been received.
• ACIA INTERNAL REGISTERS
The ACIA provides four registers; Transmit Data Register
(TOR), Receive Data Register(RDR), Control Register(CR) and
Status Register(SR). The content of each of the registers is
summarized in Table I.
~HITACHI
188
Hitachi America Ltd • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------HD6350/HD6850
....
Table 1 Definition of ACIA Register Contents
Buffet
Address
RS=l' R/W=O
RS=l • R/W=l
RS=O'RtW=O
RS=O'RtW=l
Data Bus
Transmit Data
Register
Receiver Data
Register
Control Register
Status Register
(Write Only)
(Read Only)
(Write Only)
Counter Divide
Select (CRO)
Counter Divide
Select (CR1)
0
Data Bit O·
Data Bit 0
1
Data Bit 1
Data Bit 1
2
Data Bit 2
Data Bit 2
3
Data Bit 3
Data Bit 3
4
Data Bit 4
Data Bit 4
Word Select 1
(CR2)
Word Select 2
(CR3)
Word Select 3
(CR4)
5
Data Bit 5
Data Bit 5
Tx Contrail
(CR5)
6
Data Bit 6
Data Bit 6
7
Data Bit 7 00 •
Data Bit 7 0 •
(Read Only)
Rx Data Reg. Full
(RDRF)
Tx Data Reg. Empty
(TORE)
Data Carrier Detect
(DCD)
Clear to Send
(CTS)
Fram ing Error
(FE)
Tx Control 2
(CR6)
Rx Interrupt Enable
(CR7)
Overrun
(OVRN)
Parity Error
(PE)
Interrupt Request
(IRQ)
* Leading bit· LSB = Bit 0
* .. Data bit will be zero in 7-bit plus parity modes .
••• Dati bit is "don't car." in 7--bit plus parity mode•.
•••• 1 .• , "High" level, 0 , •• "Low" level
T....mit o.ta Regimr (TORI
Data is written in the Transmit Data Register during the
negative transition of th,! enable (E) when the ACIA has been
addressed and RS' R/W is selected. Writing data into the
register causes the Transmit Data Register Empty bit in the
Status Register to go "0". Data can then be transmitted. If the
transmitter is idling and no character is being transmitted, then
the transfer will take place within 2 bit time + several E cycles
of the trailing edge of the Write command. If a character is
being transmitted, the new data character will commence as
soon as the previous character is complete. The transfer of
data causes the Transmit Data Register Empty (TORE) bit to
indicate empty.
•
•
Receive o.ta Regil1IIr (RDR)
Data is automatically transferred to the empty Receive Data
Register (RDR) from the receiver deserializer (a shift register)
upon receiving a complete character. This event causes the
Receive Data Register Full bit (RDRF) on the status buffer to
go "I" (full). Data may then be read through the bus by ad·
dressing the ACIA and Rftij "High" when the ACIA is enabled.
The non-destructive read cycle causes the RDRF bit to be
cleared to empty although the data is retained in the RDR. The
status is maintained by RDRF as to whether or not the data
is current. When the Receive Data Register is full, the automatic
transfer of data from the Receiver Shift Register to the Data
Register is inhibited and the RDR contents remain valid with its
current status stored in the Status Register.
• Control Regilter
The ACIA Control Register consists of eight bits of writeonly buffer that are selected when RS and R/W are "Low". This
register controls the functien of the receiver, transmitter,
interrupt enables, and the Request·ta-Send (RTS) peripheral/
modem control output.
Counter Divide Select Bits (CRO Ind CR1)
The Counter Divide Select Bits (CRO and CRI) determine
the divide ratios utilized in both the transmitter and receiver
section of the ACIA. Additionally, these bits are used to provide
a master reset for the ACIA which clears the Status Register
(except for external conditions on ers and OCD) and initializes
both the receiver and transmitter. Master reset does not affect
other Control Register bits. Note that after power-on or a power
fail/restart, these bits must be set "I" to reset the ACIA. Mter
resetting, the clock divide ratio may be selected. These counter
select bits provide for the following clock divide ratios:
Table 2 Function of Counter Devide Select Bit
CRl
0
0
CRO
0
1
0
Function
:1
+16
+64
Master Reset
Word Select Bits (CR2. CR3.1nd CR4)
The Word Select bits are used to select word length, parity,
and the number of stop bits. The encoding format is as follows:
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
189
HD6350/HD6850--------------------------------------------------------•
Table 3 Function of Word Select Bit
CR4
CR3
CR2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Function
7 Bits + Even Parity + 2 Stop Bits
7 Bits + Odd Parity + 2 Stop Bits
7
7
8
8
8
8
Bits + Even Parity + 1 Stop Bit
Bits + Odd Parity + 1 Stop Bit
Bits + 2 Stop Bits
Bits + 1 Stop Bit
Bits + Even Parity + 1 Stop Bit
Bits + Odd Parity + 1 Stop Bit
Word length, Parity Select, and Stop Bit changes are not
buffered and therefore become effective immediately.
Transmitter Control Bits (CR5 and CR6)
Two Transmitter Control bits provide for the control of
the interrupt from the Transmit Data Register Empty condition,
the Request-ta-Send (RTS) output, and the transmission of a
Break level (space). The following encoding format is used:
Table 4 Function of Transmitter Control-Bit
CR6
CR5
o
o
0
RTS = "Low", Transmitting Interrupt Disabled.
1
RTS = "Low", Transmitting Interrupt Enabled.
RTS = "High", Transmitting Interrupt
Disabled.
o
Function
RTS = "Low", Transmits a Break level on
the Transmit Data Output.
Transmitting Interrupt Disabled.
Receive Interrupt Enable Bit (CR7)
The following interrupts will be enabled by a "\" in bit
position 7 of the Control Register (CR7): Receive Data
Register Full, Overrun, or a "Low" to "High" transistion on the
Data Carrier Detect (DC D) signal line.
RORF F'-e
[
Reotilier
AlE
'"'''M' ROAF FI..
OVRN FIll;
iRQ
DCOFl,mg
Tran,mltter
[,""m"TDRO
FI..
Cis Inpo,il
TORE FIll\!
Figure 14 IRQ Internal Circuit
Status Regilter
Information on the status of the ACIA is available to the
MPU by reading the ACIA Status Register. This read-only
register is selected when RS is "Low" and R/W is "High".
Information stored in this register indicates the status of the
Transmit Data Register, the Receive Data Register and error
logic, and the peripheral/modem status inputs of the ACIA.
Receive Data Regilter Full (RDRF), Bit 0
RDRF indicates that received data has been transferred to
the Receive Data Register. RDRF is cleared after an MPU read
of the Receive Data Register or by a master reset. The cleared or
empty state indicates that the contents of the Receive Data
Register are not current. Data Carrier Detect (DC D) being
"High" also causes RDRF to indicate empty.
Transmit Data Register Empty (TORE), Bit 1
The Transmit Data Register Empty bit being set "I"
indicates that the Transmit Data Register contents have been
transferred and that new data may be entered. The "0" state
indicates that the register is full and that transmission of a new
character has not begun since the last write data command.
foeD), Bit 2
The OCD bit will be "\" when the DCD input from a modem
has gone "High" to indicate that a carrier is not present. This bit
going "I" causes an Interrupt Request to be generated when the
Receive Interrupt Enable is set. It remains" I" after the ocr>
input is returned "Low" until cleared by first reading the Status
Register and then the Data Register or until a master reset
occurs. If the DCD input remains "High" after read status and
read data or master reset has occurred, the interrupt is cleared,
the DCD status bit remains "I" and will follow the DCD input.
Data Carrier Detect
Clear-to-Send Iml, Bit 3
The CTS bit indicates th~ state of the CTS input from a
modem. A "Low" CTS input indicates that there is a CTS from
the modem. In the "High" state, the Transmit Data Register
Empty bit is inhibited and the CTS status bit will be "1".
Master reset does not affect the Clear-to-Send Status bit.
Framing Error (FE), Bit 4
FE flag indicates that the received character is improperly
framed by a start and a stop bit and is detected by the absence
of the 1st stop bit. This error indicates a synchronization error,
faulty transmission, or a break condition. The FE flag is set or
reset during the receive data transfer time. Therefore, this error
indicator is present throughout the time that the associated
character is available.
Receiver Overrun IOVRN), Bit 5
Overrun is an error flag that indicates that one or more
characters in the data stream were lost. That is, a character or a
number of characters were received but not read from the
Receive Data Register (RDR) prior to subsequent characters
being received. The overrun condition begins at the midpoint of
the last bit of the second character received in succession
without a read of the RDR having occurred. The overrun does
not occur in the Status Register until the valid character prior to
Overrun has been read. The RDRF bit remains set until the
Overrun is reset. Character synchronization is maintained during
the Overrun condition. The Overrun indication is reset after the
reading of data from the Receive Data Register or by a Master
Reset.
~HITACHI
190
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------------HD6350/HD6850
Parity Error (PE), Bit 6
The PE flag indicates that the number of "I"s (highs) in the
character does not agree with the preselected odd or even
parity. Odd parity is defined to be when the total number of
ones is odd. The parity error indication will be present as long as
the data character is in the RDR. If no parity is selected, then
both the transmitter parity generator output and the receiver
parity check results are inhibited.
Interrupt Request (IRQ), Bit 7
The IR~ bit indicates the state of the IRQ output. Any
interrupt condition with its applicable enable will be mdicated
in this status bit. Anytime the IRQ output is "Low" the IRQ bit
will be "I" to indicate the interrupt or service request status.
IRQ is cleared by a read operation to the Receive Data Register
or a write operation to the Transmit Data Register. (Refer to
Figure 14.)
is present and the appropriate interrupt enable within the ACIA
is set.
Clock Inputs
Separate high impedance TTL compatible inputs are provided for clocking of transmitted and received data. Clock
frequencies of I, 16 or 64 times the data rate may be selected.
Transmit Clock (Tx ClK)
The Tx CLK input is used for the clocking of transmitted
data. The transmitter initiates data on the negative transition of
the clock.
Receive Clock (Rx ClK)
The Rx CLK input is used for synchronization of received
data. (In the .;. I mode. the clock and data must be
synchronized externally.) The receiver samples the data on the
positive transition of the clock .
• SIGNAL FUNCTIONS
• Serial I nput/Output Lines
•
Interface Signal for MPU
Bi-Directional Data Bus (0 0 -0 7 1
The bi-directional data bus (Do -0 7 ) allow for data transfer
between the ACIA and the MPU. The data bus output drivers
are three-state devices that remain in the high impedance (off)
state except when the MPU performs an ACIA read operatIOn.
Receive Data (Rx Data)
The Rx Data line is a high impedance TTL compatible input
through which data is received In a serial format. Synchronization with a clock for detection of data is accomplished internally when clock rates of 16 or 64 times the bit rate are used. Data
rates are in the range of 0 to 500 kbps when external
synchronization is utilized.
Enable (E)
The Enable signal, E, is a high impedance TTL compatible
input that enables the bus input/output data buffers and clocks
data to and from the ACIA. This signal will normally be a
derivative of the HMCS6800 q,2 Clock. The ACIA accepts both
continuous pulse signal and strobe type signal as Enable input.
Transmit Data (Tx Datal
The Tx Data output line transfers senal data to a modem or
other peripheral. Data rates in the range of 0 to 500 kbps when
external synchronization is utilized.
ReadIWrite (R/W)
The R!W line is a high impedance input that is TTL
compatible and is used to control the direction of data flow
through the ACIA's input/output data bus interface. When R/W
is "High" (MPU Read cycle), ACIA output drivers are turned on
and a selected register is read. When it is "Low", the ACIA
output drivers are turned off and the MPU writes into a selected
register. Therefore, the R/W signal is used to select read-only or
wri te-only registers within the ACIA.
Chip Select (CSo , CS, , CS,)
These three high impedance TTL compatible input lines are
used to address the ACIA. The ACIA is selected when CS o and
CS, are "High" and CS; is "Low". Transfers of data to and
from the ACIA are then performed under the control of the
Enable signal, Read/Write, and Register Select.
Register Select (RS)
The RS line is a high impedance input that is TTL
compatible. A "High" level is used to select the Transmit/
Receive Data Registers and a "Low" level the Control/Status
Registers. The R/W signal line is used in conjunction with
Register Select to select the read-only or write-only register in
each register pair.
Modem Control
The ACIA includes several functions that permit limited
control of a p~eral or modem. The functions included aie
CTS, RTS and DCD.
Clear-ta-Send (eTS)
This high impedance TTL compatible input provides automatic control of the transmitting end of a communications link
via the modem CTS active "Low" output by inhibiting the
Transmit Data Register Empty (TORE) status bit. (Refer to
Figure 15.)
Request-to-Send (RTS)
The RTS output enables the MPU to control a peripheral or
modem via the data bus. The RTS output corresponds to the
state of the Control Register bits CR5 and CR6. When CR6=O
or both CR5 and CR6=1, the RTS output is "Low" (the active
state). This output can also be used for Data Terminal Ready
(DTR). (Refer to Figure 15.)
Interrupt Request (IRQ)
IRQ is a TTL compatible, open-drain (no internal pullup),
active "Low" output that is used to interrupt the MPU. The
IRQ output remains "Low" as long as the cause of the interrupt
~HITACHI
Hltach, America Ltd
• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
191
HD6350/HD6850--------------------------------------------------------Tx Data
TORE flag
Control Register
Write
Status Register
Read
Tx Data Register
Write
Transmit operation is not disabled. even if
CfS goes
"High".
Figure 15 RTS and CTS Timing Chart (Example of 2 bytes transmission)
Dam Carrier Detect (OCD)
OCD is the input signal corresponding to the "carrier
detect" signal which shows £arrier detect of modem.
OCD signal is used to control the receiving operation. When
OCD input goes "High", ACIA stops all the receiving operation
and sets receiving part in reset status. It means that receive
shift register stops shifting, error detection circuit and synchro, 'zation circuit of receive clock are reset. When OCD is
in "High" level, the receiving part of ACIA is kept in initial
OCO input
OCO flag
rno
(RIE = "1")
status and the operation in the receiving part is prohibited.
When OCD goes "Low", the receiving part is allowed to
receive data. In this case, the following process is needed to
reset OCD flag and restarts the receive operation. (Refer to
Figure 16.)
(l) Return OCD input from "High" to "Low".
(2) Read status register. (OCD flag ="I")
(3) Read receive data register (Uncertain data will be read.)
~
I
~
l\
/
..l
,1
r~
Status Register Read
Rx Data Register Read
/.
-/
~
All the receiving operation are prohibitad and ACIA is stoppad
in this period.
Figure 16 DCD Flag Timing Chart
• Nom for Use (H06350 ohly)
Input Signal, which is not necessary for user's application,
should be used fIXed to "High" or "Low" level. This is
applicable to the following signal pins.
Rx Data, Rx CLK, Tx CLK, CTS, i5Ci)
~HITACHI
192
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
HD6852, HD68A52
SSDA (Synchronous Serial
The HD6852 Synchronous Serial Data Adapter provides a
bi·directional serial interface for synchronous data information
interchange. It contains interface logic for simultaneously
transmitting and receiving standard synchronous communica·
tions characters in bus organized systems such as the
HMCS6800 Microprocessor systems.
The bus interface of the HD6852 includes select, enable,
read/write, interrupt, and bus interface logic to allow data
transfer over an 8-bit bi·directional data bus. The parallel data
of the bus system is serially transmitted and received by the
synchronous data interface with synchronization, fill charar-ter
insertion/deletion, and error checking. The functional con·
fJgllration of the SSDA is programmed via the data bus during
system initialization.
Programmable control registers provide control for variable
word length, transmit control, receive control, synchronization
control and interrupt cO!1troL Status, timing and control lines
provide peripheral or modem control.
1»picaI applications include data communications terminals,
floppy disk controllers, cassette or cartridge tape controllers and
numerical control systems.
Data Adapter)
HD6852P, HD68A52P
(DP-24)
• PIN ARRANGEMENT
• fEATURES
• Programmable Interrupts from Transmitter, Receiver,
and Error Detection Logic
• Character Synchronization on One or Two Sync Codes
• External Synchronization Available for Parallel·Serial
Operation
• Programmable Sync Code Register
• Up to 1 Mkbps Transmitter
• Peripheral/Modem Control Functions
• Three Bytes of FIFO Buffering on Both Transmit and
Receive
• 6, 7, or B Bit Data Transmission
• Optional Even and Odd Parity
• Parity, Overrun, and Underflow Status
•
(Top View)
Compatible with MC6B52 and MC68A52
C$
10
RS
11
8
TUF
"
23
0C0
7
iRa
2
3
RlI Datil
Rx eLK
5
SM/6'fR
D.
0,
21
01
20
D.
19
D.
18
0,
17
O.
16
D.
IS
fiiS
9
@HITACHI
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
193
HD6852,HD68A52---------------------------------------------------------• ABSOLUTE MAXIMUM RATINGS
.
Item
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
Symbol
Topr
Value
-0.3-+7.0
-0.3-+7.0
- 20-+75
T Itg
-55 - +150
Vee
V'n *
Unit
V
V
·C
·C
• With respect to vss ISYSTEM GNO)
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded, it could affect reliability of LSI.
•
RECOMMENDED OPERATING CONDITIONS
Item
Supply Voltage
Input Voltage
Operating Temperature
•
•
•
Symbol
min
typ
Vee *
V1L *
V1H *
4.75
-0.3
5.0
-
2.0
- 20
Topr
max
5.25
Unit
V
V
V
·C
0.8
Vee
75
25
With respect to Vss (SYSTEM GNO)
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee = 5V ± 5%, Vss = OV, Ta = -20-+75'C, unless otherwise noted.)
Symbol
Item
Input "High" Voltage
Input "Low" Voltage
All Input
All Input
Do -D 7
VOH
Tx Data
DTR, TUF
VOH
Output "Low" Voltage
All Output
VOL
Input Leakage Current
TxCLK, RxCLK,
Rx Data, E,
RES, RS, R/W
CS, DCD, CTS
lin
Three·State Input Current
(Off State)
Do-D 7
ITS1
IRO
I LOH
Output "High" Voltage
Output Leakage Current
(Off State)
Power Dissipation
Input Capacitance
IOH - -205/.LA,
PW EH , PWEL~ 25/.Ls
IOH - -l00/.LA,
PW EH , PW EL S:25/.LS
IOL - 1.6 mA,
PWEH , PWEL~ 25/.Ls
Vin =0-5.25V
Vin - 0.4 - 2.4V,
Vee = 5.25V
VOH = 2.4V
Po
Do- D7
RxData, RxCLK,
TxCLK, RES,
CS, RS, R/W, E,
DCD,CTS
Output Capacitance
Test Condition
V,H
V,L
TxData, DTR, TUF,
IRO
,
Vi" = OV,
Ta = 25'C,
Cin
Cout
f = 1 MHz
Vi" = OV, Ta=25'C
f = 1 MHz
min
2.0
-0.3
typo
max
-
-
-
0.8
Unit
V
V
2.4
-
-
V
2.4
-
-
V
-
-
0.4
V
-2.5
-
2.5
/.LA
-10
-
10
/.LA
-
-
10
/.LA
-
300
-
-
525
12.5
-
-
7.5
-
-
10
5.0
pr
-
• Ta = 25" C, Vee = 5V
~HITACHI
194
mW
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
pF
----------------------------------------------------------HD6852,HD68A52
•
AC CHARACTERISTICS
(Vcc=5V±5%, VSS=OV, Ta=-20-+75"C, unless otherwise noted.)
1. TIMING OF THE DATA TRANSFER
Item
Test
Condition
Symbol
HD6852
min
typ
Clock Frequency
fc
Receive Data Setup Time
tROSU
Fig. 3
350
-
Receive Data Hold Time
tRoH
Fig.3
350
Sync Match Delay Time
tSM
Fig.3
Clock-to-Data Delay for
Transmitter
tTOO
Transmitter Underflow
DTR Delay Time
max
HD68A52
typ
max
min
-
-
200
-
-
-
200
-
-
-
1.0
-
-
0.666
IlS
Fig. 4,6
-
-
1.0
-
-
0.666
IlS
tTUF
Fig. 4
-
0.666
IlS
1.0
Fig. 5
0.8
IlS
RES Pulse Width
tRES
CTS Setup Time
tCTS
-
IlS
ns
DCD Setup Time
Input Rise and Fall Times(Except E
-
IlS
tlR
-
0.666
I RQ Release Time
-
-
Fig. 5
-
1.0
tOTR
Clock "Low" Pulse Width
PWCL
Fig. 1
700
Clock "High" Pulse Width
PWCH
Fig. 2
700
*
-
1.0
Fig.6
200
toco
Fig.7
500
t" tf
0.8V to 2.0V
-
-
400
-
400
600
1.2
-
0.666
1.0'
-
150
350
-
Unit
1,000
-
1.0'
ns
ns
kHz
ns
ns
ns
Ils
1.0", or 10%of the pulse width. whichever is smaller.
2. BUS TIMING
1) READ
Symbol
Item
Test
Condition
HD6852
min
HD68A52
max
max
min
Unit
Enable Cycle Time
teveE
-
0.666
-
IlS
Enable "High" Pulse Width
PW EH
0.45
25
0.28
25
IlS
Enable "Low" Pulse Width
PW EL
0.43
-
0.28
-
IlS
140
-
140
-
ns
1.0
Setup Time, Address and RIW valid
to Enable positive transition
tAS
Data Delay Time
tOOR
-
320
-
220
ns
Data Hold Time
tH
10
-
10
-
ns
Address Hold Time
tAH
10
80
10
ns
Rise and Fall Time for Enable input
tEr,
-
25
-
80
25
Fig. 8
tef
ns
2) WRITE
Symbol
Item
Test
Condition
HD6852
min
max
HD68A52
max
min
Unit
Enable Cycle Time
teveE
1.0
-
0.666
-
Ils
Enable Pulse Width, "High"
PW EH
0.45
25
0.28
25
IlS
Enable Pulse Width, "Low"
PW EL
0.43
-
0.28
-
IlS
Setup Time, Address and R/W valid
to Enable positive transition
tAS
140
-
140
-
ns
80
ns
ns
Fig.9
Data Setup Time
tosw
Data Hold Time
tH
10
-
10
Address Hold Time
tAH
10
-
10
-
Rise and Fall Time for Enable input
tE" tEf
-
25
-
25
195
ns
ns
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
195
HD6852,HD68A52--------------------------------------------------------
TXCLK~.OV
or
Rx CLK
Tx CLK
or
Rx CLK
PWCH
Figure 2 Clock Pulse Width ("High" level)
Figure 1 Clock Pulse Width ("Low" level)
Rx CLK
Rx Data
n = Number of bits
~=
In
character
Don't care
Sync Matc_h__________________________________________J
O.4V
'" Rx CLK
Period
Figure 3 Receive Data Setup and Hold Times and Sync Match Delay Time
Tx
CLK
Enable
tOTR
Tx
Data -----,~o.\!.o:Wf_----.:.:...--J
TUF _ _ _ _ _ _ _ _ _J
n
= Number of
IRQ
bits
• iRa A.I.... Tim••ppli.d to TxO.t. FIFO writ. oper.tion .nd
in character
AxOat. FI FO r•• d op.ration .
Figure 4 Transmit Data Output Delay and
Transmitter Underflow Delay Time
•• iRa A.I •••• Tim••ppli.d to writ. "1" op.r.tion to AxAS, TxAS,
CTUF, CI •• r CTS bits.
Figure 5 DTR and IRQ Release Time
~O.8V
•
~_---Jr
""'~
@
Tx CLK
~
@
®
Notes:
@ Mu.t occur before OCO goes low.
@ First d.t. bit pl.ced in Ax 'hift register.
© Last d.t. bit of byte pl.ced In Ax 'hift register.
Tx O.ta
@A'Dat.bytetr.nsferredfro.m shift re~r to A. FIFO.
@ Clock edga required for g.ner.tlon of fFlOby ADA .t.tu •.
Note: Aefer to Figure 3 for the A. O.te .etup and hold times.
Figure 7 DCD Setup Time
Figure 6 CTSSetup Time
~HITACHI
196
Hitachi A'Tlerica Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------HD6852,HD68A52
Enable
Enable
RS, CS, R/W -
.......'l'JjoIi~_+-_Pr"'_;'7':':--
RS, CS,R/W
Data Bus
Data Bus
Figure 9 Sus Write Timing Characteristics
(Write information into SSDA)
Figure S Sus Read Timing Characteristics
(Read information from SSDA)
Load A
Load B
(IRQ Only)
(0, - D., DTR, Tx Data, TUF)
5.0V
RL - 2.4K
Test point
Test point
C
R
~
r
5'OV
3k
l00pF
C-13OpF for 0, -0,
-3OpF for DTR, Tx Data, and TUF
All diodes are 1S2074 ® or Equivalent
R=llkll for 0,-0.
=24kll for DTR, Tx Data, and TUF
Figure 10 Test Loads
• DEVICE OPERATION
At the bus interface, the SSDA appears· as two addressable
memory locations. Internally, there are seven registers: two
read-only and five write-only registers. The read-only registers
are Status and Receive Data; the write-only registers are Control
I, Control 2, Control 3, Sync Code and Transmit Data. The
serial interface consists of serial input and output lines with
independent clocks, and four peripheral/modem control lines.
Data to be transmitted is transferred directly into the 3-byte
Transmit Data First-In First-Out (FIFO) Register from the data
bus. Availability of the input to the FIFO is indicated by a bit
in the Status Register; once data is entered, it moves through
the FIFO to the last empty location. Data at the output of the
FIFO is automatically transferred from the FIFO to the
Transmitter Shift Register as the shift register becomes available
to transmit the next character. If data is not available from the
FIFO (underflow condition), the Transmitter Shift Register is
automatically loaded with either a sync code or an all "I "s
character. The transmit section may be programmed to append
even, odd, or no parity to the transmitted word. An external
control line (C'fS) is provided to inhibit the transmitter without clearing the FIFO.
Serial data is accumulated in the receiver based on the
synchronization mode selected. In the external sync mode used
for parallel-serial operation, the receiver is synchronized by the
Data Carrier Detect (DCD) input and transfers successive bytes
of data to the input of the Receiver FIFO. The single-synccharacter mode ~equires that a match occur between the Sync
Code Register and one incoming character before data transfer
to the FIFO begins. The two-sync-character mode requires that
two sync codes be received in sequence to establish synchronization. Subsequent to synchronization in any mode, data is
accumulated in the shift register, and parity is optionally
checked. An indication of parity error is carried through the
Receiver FIFO with each character to the last empty location.
Availability of a word at the FIFO output is indicated by a bit
in the Status Register, as is a parity error.
The SSDA and its internal registers are selected by the
address bus, Read/Write (R/W) and Enable control lines. To
configure the SSDA, Control Registers are selected and the
appropriate bits set. The Status Register is addressable for
reading status.
Other I/O lines, in addition to Clear-to-Send (CTS) and Data
Carrier Dete£!..J.DCD), include Sync Match/Data Terminal
Ready (SM/DTR) and Transmitter Underflow (TUF). The
transmitter and receiver each have individual clock inputs
allowing simultaneous operation under separate clock control.
Signals to the microprocessor are the Data bus and Interrupt
Request (iRQ).
~HITACHI
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HD6852,HD68A52-------------------------------------------------------•
Initialization
During a power-on sequence, the SSDA is reset via the RES
input and internally latched in a reset condition to prevent
erroneous output transmissions. The Sync Code Register,
Control Register 2, and Control Register 3 should be programmed prior to the programmed release of the Transmitter
and/or Receiver Reset bits; these bits in Control Register I
should be cleared after the RES line has gone "High".
In the external sync mode, TDRA is unaffected by CTS in
order to provide Transmit Data FIFO status for preloading and
operating the transmitter under the control of the CTS input.
When the Transmitter Reset bit (Tx Rs) is set, the Transmit
Data FIFO is cleared and the TDRA status bit is cleared. Mter
one E clock has occurred, the Transmit Data FIFO becomes
available for new data with TDRA inhibited.
•
• Transmitter Operation
Data is transferred to the transmitter section in parallel form
by means of the data bus and Transmit Data FIFO. The
Transmit Data FIFO is a 3-byte register whose status is
indicated by the Transmitter Data Register Available status bit
(TDRA) and its associated interrupt enable bit. Data is
transferred through the FIFO on negative edges of Enable (E)
pUlses. Two data transfer modes are provided in the SSDA. The
I-byte transfer mode provides for writing data to the transmitter section (and reading from the receiver sectionYone byte
at a time. The 2-byte transfer mode provides for writing two
data characters in succession.
Data will automatically transfer from the last register
location in the Transmit Data FIFO (when it contains data) to
the Transmitter Shift Register during the last half of the last bit
of the previous character. A character is transferred into the
Shift Register by the Transmitter Clock. Data is transmitted
LSB first, and odd or even parity can be optionally appended.
The unused bit positions in short word length characters from
the data bus are "don't cares". (Note: The data bus inputs may
be reversed for applications requiring the MSB to be transferred
taken, e.g., IBM format for floppy disks; however, care must be
taken to properly program the control registers - Table 1 will
have its bit positions reversed.)
When the Shift Register becomes empty, and data is not
available for transfer from the Transmit Data FIFO, an
"underflow" occurs, and a character is inserted into the
transmitter data stream to maintain character synchronization.
The character transmitted on underflow will be either a "Mark"
(all "I "s) or the contents of the Sync Code Register, depending
upon the state of the Transmit Sync Code on Underflow control
bit. The underflow condition is indicated by a pulse ('" Tx CLK
"High" period) on the Underflow putput (when in Tx Sync on
underflow mode). The Underflow output occurs coincident
with the transfer of the last half of the last bit preceding the
underflow character. The Underflow status bit is set until
cleared by means of the Clear Underflow control bit. This
output may be used in floppy disk systems to synchronize write
operations and for appending CRCC.
Transmission is initiated by clearing the Transmitter Reset
bit in Control Register 1. When the Transmitter Reset bit is
cleared, the first full positive half-cycle of the Transmit Clock
will initiate the transmit cycle, with the transmission of data or
underflow characters beginning on the negative edge of the
Transmit Clock pulse which started the cycle. If the Transmit
Data FIFO was not loaded, an underflow character will
be transmitted.
The Clear-to-Send (CTS) input provides for automatic
control of the transmitter by means of external system
hardware; e.g., the modem CTS out~provides the control in a
data communications system. The CTS input resets and inhibits
the transmitter section when "High", but does not reset the
Transmit Data FIFO. The TDRA status bit is inhibited by CTS
being "High" in either the one-sync character or two-synccharacter mode of operation.
Receiver Operation
Data and a presynchronized clock are provided to the SSDA
receiver section by means of the Receive Data (Rx Data) and
Receive Clock (Rx CLK) inputs. The data is a continuous
stream of binary data bits without means for identifying character boundaries within the stream. It is, therefore, necessary to
achieve character synchronization for the data at the beginning
of the data block. Once synchronization is achieved, it is
assumed to be retained for all successive characters within the
block.
Data communications systems utilize the detection of sync
codes during the initial portion of the preamble to establish
character synchronization. This requires the detection of a
single code or two successive sync codes. Floppy disk and
cartridge tape units require sixteen bits of defmed preamble and
cassettes require eight bits of preamble to establish the reference
for the start of record. All three are functionally, equivalent to
the detection of sync codes. Systems which do not utilize code
detection techniques require custom logic external to the SSDA
for character synchronization and use of the parallel-to-serial
(external sync) mode.
(Note: The Receiver Shift Register is set to ones when reset)
•
Synchronization
The SSDA provides three operating modes with respect to
character synchronization: one-syne-character mode, two-synccharacter mode, and external sync mode. The external sync
mode requires synchronization and control of the receiving
section through the Data Carrier Detect (DCD) input. This
external synchronization could consist of direct line control
from the transmitting end of th~ serial data link or from
external logic designed to detect the start of the message block.
The one-sync-<:haracter mode searches on a bit-by-bit basis until
a match is achieved between the data in the Shift Register and
the Sync Code Register. The match indicates character synchronization is complete and will be retained for the message block.
In the two-sync-<:haracter mode, the receiver searches for the
fllst sync code match on a bit-by-bit basis and then looks for a
second successive sync code -character prior to establishing
character synchronization. If ~ second sync code character is
not received, the bit-by-bit search for the first sync code is
resumed.
Sync codes received prior to the completion of synchronization (one or two character) are not transferred to the
Receive Data FIFO. Redundant sync codes during the preamble
or sync codes which occure as "fill characters" can automatically be stripped from the data, when the Strip Sync control bit
is set, to minimize system loading. The character synchronization will be retained until cleared by means of the Clar Sync bit,
which also inhibits synchronization search when set.
• Receiving Date
Once synchronization has been achieved, subsequent characters are automatically transferred into the Receive Data FIFO
and clocked through the FIFO to the last empty location by E
pulses (MPU System 4>2). The Receiver Data Available status bit
~HITACHI
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Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------HD6852,HD68A52
(RDA) indicates when data is available to be read from the last
FIFO location (#3) when in the I-byte transfer mode. The
2-byte transfer mode causes the RDA status bit to indicate data
is available when the last two FIFO register locations are full.
Data being available in the Receive Data FIFO causes an
interrupt request if the Receiver Interrupt Enable (RIE) bit is
set. The MPU will then read the SSDA Status Register, which
will indicate that data is available for the MPU read from the
Receiver Data FIFO register. The IRQ and RDA status bits are
reset by a read from the FIFO. If more than one character has
been received and is resident in the Receive Data FIFO,
subsequent E clocks will cause the FIFO to update and the
RDA and IRQ status bits will again be set. The read data
operation for the 2-byte transfer mode requires an intervening E
clock between reads to allow the FIFO data to shift. Optional
parity is automatically checked as data is received, and the
parity status condition is maintained with each character until
the data is read from the Receive Data FIFO. Parity errors will
cause an interrupt request if the Error Interrupt Enable (EIE)
has been set. The parity bit is not transferred to the data bus
but must be checked in the Status Register. NOTE: In the
2-byte transfer mode, parity should be checked prior to reading
the second byte, since a FIFO read clears the error bit.
Other status bits which pertain to the receiver section are
Receiver Overrun and Data Carrier Detect (OCD). The Overrun
status bit is automatically set when a transfer of a character to
the Receive Data FIFO occurs and the first register of the
Receive Data FIFO is full. Overrun causes an interrupt if Error
Interrupt Enable (EIE) has been set. The transfer of the
overrunning character into the FIFO causes the previous
character in the FIFO input register location to be lost. The
Overrun status bit is cleared by reading the Status Register
(when the overrun condition is present), followed by a Receive
Data FIFO Register read. Overrun cannot occur and be cleared
without providing an opportunity to detect its occurrence via
the Status Register.
A positive transition on the OCI> input causes an interrupt if
the EIE control bit has been set. The interrupt caused by DCD
is cleared by reading the Status Register when the DCD s~
bit is "1", followed by a Receive Data FIFO read. The OCD
status bit will subsequently follow the state of the OCD input
when it goes "Low".
• SSDA REGISTERS
Seven registers in the SSDA can be accessed by means of the
bus. The registers are dermed as read-only or write-only
according to the direction of information flow. The Register
Select (RS) input selects two registers in each state, one being
read-only and the other write-only, The Read/Write (R/W) input
dermed which of the two selected registers will actually be
accessed, Four registers (two read-only and two write-only) can
be addressed via the bus at any particular time. These registers
and the required addressing are defined in Table I.
•
Control Reglater 1 (C11
Control Register I is an 8-bit wirte-only register that can be
directly addressed from the data bus. Control Register I is
addressed when RS = "Low" and R/W = "Low".
Receiver Reset (Rx Ral. C1 Bit 0
The Receiver Reset control bit provides both a reset and
inhibit function to the receiver section. When Rx Rs is set, it
clears the receiver control logic, error logic, Rx Data FIFO
Control, Parity Error status bit, and DCD interrupt. The
Receiver Shift Register is set ones. The Rx Rs bit must be
cleared after the occurrence of a "Low" level on RES in order
to enable the receiver section of the SSDA.
Transmitter Reset (Tx Rs). C1 Bit 1
The Transmitter Reset control bit provides both a reset and
inhibit to the transmitter section. When Tx Rs is set, it clears
the transmitter control section, Transmitter Shift Register, Tx
Data FIFO Control (the Tx Data FIFO can be reloaded after
one E clock pulse), the Transmitter Underflow status bit, and
the CTS interrupt, and inhibits the TDRA status bit (in the
one-sync-(;haracter and two-sync-(;haracter modes). The Tx Rs
bit must be cleared after the occurrence of a "Low" level on
RES in order to enable the transmitter section of the SSDA. If
the Tx FIFO is not preloaded, it must be loaded immediately
after the Tx Rs release to prevent a transmitter underflow
condition.
Strip Synchronization Characters (Strip Sync). C1 Bit 2
If the Strip Sync bit is set, the SSDA will automatically strip
all received characters which match the contents of the Sync
Code Register. The characters used for synchronization (one or
two characters of sync) are always stripped from the received
data stream.
Clear Synchronization (Claar Sync). C1 Bit 3
The Clear Sync control bit provides the capability of
dropping receiver character synchronization and inhibiting
resynchronization. The Clear Sync bit is set to clear and inhibit
receiver synchronization in all modes and is reset to zero to
enable resynchronization.
Transmitter Interrupt Enable (TIEl. C1 Bit 4
TIE enable both the Interrupt Request (IRQ) output and
Interrupt Request status bit to indicate a transmitter service
~est. When TIE is set and the TDRA status bit is "I", the
IRQ output will go "Low" (the active state) and the IRQ status
bit will go "I".
Receiver Interrupt Enable (RIEl. C1 Bit 5
RIE enable both the Interrupt Request output (IRQ) and the
Interrupt Request status bit to indicate a receiver service
request. When RIE is set and the RDA status bit is "I", the IRQ
output will go "Low" (the active state) and the iRQ status bit
will go "I".
Addre.. Control 1 (AC1) and Address Control 2 (AC21. C1
Blt16 and 7
ACI and AC2 select one of the write-only registers - Control
2, Control 3, Sync Code, or Tx Data FIFO - as shown in Table
1, when RS = "High" and R/W = "Low".
•
Control Regilter 2 (C21
Control Register 2 is an 8-bit write-only register which can be
programmed from the bus when the Address Control bits in
Co,!!trol Register I (ACI and AC2) are reset, RS = "High" and
R/W="Low".
Peripheral Control 1 (PC1) and Peripheral Control 2 (PC2I.
C2 Bits 0 and 1
Two control bits, PCl and PC2, determine the operating
characteristics of the Sync Match/DTR output. PCl, when
"High", selects the Sync Match mode. PC2 provides the inhibit/
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
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HD6852,HD68A52---------------------------------------------------------enable control for the SM/DRT output in the Sync Match mode.
A one-bit-wide pulse is generated at the output when PC2 is "0",
and a match occurs between the contents of the Sync Code
Register and the incoming data even if sync is inhibited (Clear
Sync bit = "1 "). The Sync Match pulse is referenced to the
negative edge of Rx CLK pulse causing the match.
The Data Terminal Ready (OTR) mode is selected when PCI
is "0". When PC2 = "I" the SM/OTR output = "Low" and vice
versa. The operation of PC2 and PCI is summarized in Table 4.
1-Byte!2-Byte Transfer (1-Byte!2-Byte), C2 Bit 2
When I-Byte/2-Byte is set, the TORA and RDA status bits
will indicate the availability if their respective data FIFO
registers for a single byte data transfer. Alternately, if I-Byte/
2-Byte is reset, the TORA and ROA status bits indicate when
two bytes of data can be moved without a second status read.
An intervening Enable pulse must occur between data transfers.
Word Length Selects IWS1, WS2, WS3), C2 Bits 3, 4, 5
Word lengtll Select bits WSI, WS2, and WS3 select word
length of 7,8, or 9 bits including parity as shown in Table 3.
Transmit Sync Code on Underflow ITx Sync), C2 Bit 6
When Tx Sync is set, the transmitter will automatically send
a sync character when data is not available for transmission. If
Tx Sync is reset, the transmitter will transmit a Mark character
(including the parity bit position) on underflow. When the
underflow is detected, a pulse approximately a Tx CLK "High"
period wide will occur on the underflow output if the Tx Sync
bit is "I". Internal parity generation is inhibited during
underflow except for sync code fill character transmission in 8
bit plus parity word lengths.
Error Interrupt Enable lEI E), C2 Bit 7
When EIE is set, the IRQ status bit will go "I" and the IRQ
output will go "Low" if:
I) A receiver overrun occurs. The interrupt is cleared by reading
the Status Register and reading the Rx Data FIFO.
2) fiCO input has gone to a "High". The interrupt is cleared by
reading the Status Register and reading the Rx Data FIFO.
3) A parity error exists for the character in the last location
(#3) of the Rx Data FIFO. The interrupt is cleared by
reading the Rx Data FIFO. The interrupt is cleared by
reading the Rx Data FIFO.
4) The CTS input has gone to a "High". The interrupt is cleared
by writing a "I" in the Clear crs bit, C3 bit 2, or by a Tx
Reset.
5) The transmitter has underflowed (in the Tx Sync on
Underflow mode). The interrupt is cleared by writing a "I"
into the Clear Underflow, C3 bit 3, or Tx Reset.
When EIE is a "0", the ffiQ status bit and the IRQ output
are disabled for the above error conditions. A "Low" level on
the RES input resets EIE to "0".
• Control Register 3 IC3)
Control Register 3 is a 4-bit write-only register which can be
programmed from the bus when RS = "High" and R/W
"Low" and Address Control bit ACI = "1" and AC2 = "0".
External/Internal Sync Mode Control IE!I Sync), C3 Bit 0
When the Ell Sync Mode bit is "I ", the SSOA is in the
external sync mode and the receiver synchronization logic is
disabled. SynchrOnization can be achieved by means of the DCI)
input or by starting Rx CLK at the midpoint of data bit "0" of
a character with DCO "Low". Both the transmitter and receiver
sections operate as parallel - serial converters in the External
Sync mode. The Clear Sync bit in Control Register 1 acts as a
receiver sync inhibit when "High" to provide a bus controllable
inhibit. The Sync Code Register can serve as a transmitter fill
character register and a receiver match register in this mode. A
"Low" on the RES input resets the E/I Sync Mode bit placing
the SSOA In the internal sync mode.
One-Sync-Character!Two-Sync-Character Mode, Control 11
Sync!2 Sync), C3 Bit 1
When the 1 Sync/2 Sync bit is set, the SSOA will
synchronize on a single match between the received data and
the contents of the Sync Code Register. When the I Sync/2
Sync bit is reset, two successive sync characters must be
received prior to receiver synchronization. If the second sync
character is not detected, the bit by bit search resumes from the
fIrst bit in the second character. See the description of the Sync
Code Register for more details.
Clear CTS Status IClear CTS), C3 Bit 2
When a "I" is written into the Clear CTS bit, the stored
status and interrupt are cleared. Subsequently, the CTS status
bit reflects the state of the CTS input. The Clear ,~ control
bit does not affect the CTS. input nor its inhibit of the
transmitter secton. The Clear CTS command bit is self-clearing,
and writing a ''0'' into this bit is a nonfunctional operation.
Clear Transmit Underflow Status (CTUF), C3 Bit 3
When a "I" is written into the crUF status bit, the CTUF
bit and its associated interrupt are reset. The CTUF command
bit is self-clearing and writing a "0" into this bit is a
nonfunctional operation.
• Sync Code Register
The Sync Code Register is an 8-bit register for storing the
programmable sync code required for received data character
synchronization in the one-sync-character and two-synccharacter modes. The Sync Code Register also provides for
stripping the sync/fill characters from the received data (a
programmable option) as well as automatic insertion of fill
characters in the transmitted data stream. The Sync Code
Register is not utilized for teceiver character synchronization in
the external sync mode; however, it provides storage ofreceiver
match and transmit fill characters.
The Sync Code Register can be loaded when AC2 and ACI
are a "I" and "0" respectively, and R/W = "Low" and RS =
"High".
The Sync Code Register may be changed after the detection
of a match with the received data (the first sync code having
been detected) to synchronize with a double-word sync pattern.
(This sync code change must occur prior to the completion of
the second character.) The sync match (SM) output can be used
to interrupt the MPU system to indicate that the first eight bits
have matched. The service routine would then change the sync
match register to the second half of the .pattern. Alternately, the
one-sync-character mode can be used for sync codes for 16 or
more bits by using software to check the second and subsequent
bytes after reading them from the FIFO.
The detection of the sync code can be programmed to appear
on the Sync Match/OTR output by writing a "I" in PCI (C2 bit
0) and a "0" in Pe2 (C2 bit I). The Sync Match output will go
"High" for one bit time beginning at the character interface
between the sync code and the next character.
~HITACHI
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Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------HD6852,HD68A52
• Parity for Sync CharllCter
Tranlmitter
Transmitter does not
except 9-bit mode.
9-bit (8-bit + parity) 8-bit (7-bit + parity) 7-bit (6-bit + parity) -
generate parity for the sync character
8-bit sync character + parity
8-bit sync character (no parity)
7-bit sync character (no parity)
•
R_iver
. At Synchronization
Receiver automatically strips the sync character(s) (two sync
characters if '2 sync' mode is selected) which is used to establish
synchronization. And parity is not checked for these sync
characters.
Mter Synchronization is Established
When 'strip sync' bit is selected, the sync characters (fill
characters) are stripped and parity is not checked for the
stripped sync (fill) characters. When 'strip sync' bit is not
selected (0), the S)'!Ic character is assumed to be normal data
and it is transferred into FIFO after parity checking. (When
non-parity format is selected, parity is not checked.)
Strip Sync
(C1 Bit 2)
Data Format
1
x
Operation
(C2 Bit 3-5)
0
With Parity
0
Without Parity
No transfer of sync
code.
No par ity check of
sync code.
·Transfer data anG
sync codes.
Par ity check.
·Transfer data and
sync codes.
No parity check.
• Subsequent to Iynchronization
x ..... don't cere
It is necessary to pay attention to the selected sync character
in the following cases.
I) Data format is (6 + parity), (7 + parity),
2) Strip sync is not selected ("0").
3) Mter synchronization when sync code is used as a fill
character.
Transmitter sends sync character without parity, but receiver
checks the parity as if it is normal data. Therefore, the sync
character should be chosen to match the parity che~k selected
for the receiver in this special case.
•
bit. The Overrun bit will be set when the overrun occun and
remains set until the Status Register is read, followed by a read
of the Rx Data FIFO.
Unused data bits for short word lengths (including the parity
bit) will appear as "O"s on the data bus when the Rx Data FIFO
is read.
R_ve Data Fint-In Flnt-Out Register
IRx Data FIFO)
The Receive Data FIFO Register consists of three 8-bit
reglsten which are used for buffer storage of received data. Each
8-bit reglstor has an intema! status bit which moniton its full or
empty condition. Data is always transferred from a full register
to an adjacent empty reglstor. The transfer from register to
register occurs on E pulses. The. RDA status bit will be "1"
when data is avanable in the last locetioll of the Rx Data FIFO.
In an Overrun condition, the overrunning character will be
transferred into tho full flnt stage of the FIFO registor and will
cause the loss of that data character. !laceessive overruns
continue to overwite the fint registor of the FIFO. This
destruction of data' is indicated by means of the Overrun status
Tranlmit Data Fint-In Fint-Out Regilter
(Tx Data FIFO)
The Transmit Data FIFO Reglstor consists of three 8-bit
registors which are used for buffer storage of data to be
transmitted. Each 8-bit register has an internal status bit which
monitors its full or empty condition. Data is always transferred
from a full register to an adjacent empty registor. The transfer is
clocked by E pulses.
The TDRA status bit will be "High" if tho Tx Data FIFO is
available for data.
Unused data bits for short word lengths will be handled as
"don't cares". The parity bit is not transferred over the data
bus since the SSDA generates parity at transmission.
When an Underflow occurs, the Underflow character will be
either the contents of tho Sync Code Register or an all "I "s
character. The underflow will be stored in the Status Register
until cleared and will appear on the Underflow output as a pulse
approximately a Tx CLK "High" period wide.
•
Status Register
The Status Register is an 8-bit read-only register which
provides the real-time status of the SSDA and the associated
seria1 data channel. Reading the Status Register is a non-destructive process. The method of clearing status bits depends upon
the function each bit represents and is discussed for each bit in
the register.
R_iver Data Available (RDA), S Bit 0
The Receiver Data Available status bit indicates when
receiver data can be read from the Rx Data FIFO. The receiver
data being present in the last register (#3) of the FIFO causes
RDA to be "1" for the I-byte transfer mode. The RDA bit
being "I" indicates that the last two registors (#2 and #3) are
full when in the 2-byte transfer mode. The second character can
be read without a second status rad (to determine that the
charactor is available). And E pulse must occur between reads of
the Rx Data FIFO to allow the FIFO to shift. Status must be
read on a word-by-word basis if receiver data error checking is
important. The RDA status bit is reset automatically when data
is not available.
Transmitter Data Register AvallabielTDRA), S Bit 1
The TDRA status bit indicates that data can be loaded into
the Tx Data FIFO Register. The fint register (#1) of the Tx
Data FIFO being empty will be indicated by a "I" in the TDRA
status bit in the I-byte transfer mode. The ftnt two registen
(#1 and #2) muat be empty for TDRA to be "I" when in the
2-byte transfer mode. The Tx Data FIFO can be loaded with
two bytes without an intervening status read; however, one E
pu1se must occur between loads. TDRA is inhibited by the Tx
Reset or ~. When Tx Reset is set, the Tx Data FIFO Is
cleared and then released on the next E clock pu1se. The Tx
Data FIFO can then be loaded with up to three character& of
data, even though TDRA is inhibitod. This feature allows
preloa~ta prior to the release ofTx Reset. A "High"lovol
on the CTS' input inhibits the TDRA status bit in either sync
mode of operation (one-sync-cl!aracter or two-sync-character).
does not affect TDRA in the extema! sync mode. This
m
~HITACHI
Hitachi America Ltd, • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
201
HD6852,HD68A52---------------------------------------------------------enables the SSDA to operate under the control of the ffi input
with TDRA indicating the status of the Tx Data FIFO. The CTS
input does not clear the Tx Data FIFO in any operating mode.
Data Carrier Detect (DCD), S Bit 2
A positive transition on the DCD input is stored in the SSDA
until cleared by reading both Status and Rx Data FIFO. A "1"
written into Rx Rs also clears the stored DCD status. The DCD
status bit, when set, indicates that the DCD input has gone
"High", The reading of both Status and Receive Data FIFO
allows Bit 2 of subsequent Status reads to indicate the state of
the DeD input until the next positive transition.
Clear-to-Send (CTS), S Bit 3
A positive transiton on the CTS input is stored in the SSDA
until cleared by writing a "1" into the Clear CTS control bit or
the Tx Rs bit. The CTS status bit, when set, indicates that the
CfS input has gone "High". The Clear CTS command (a "I"
into C3 Bit 2) allows Bit 3 of subsequent Status reads to
indicate the state of the CTS input until the next positive
transition.
Transmitter Underflow (TUF), S Bit 4
When data is not available for the transmitter, an underflow
occurs and is so indicated in the Status Register (in the Tx Sync
on underflow mode). The underflow status bit is cleared by
writing a "I" into the Clear Underflow (CTUF) control bit or
the Tx Rs bit. TUF indicates that a sync character will be
transmitted as the next character. A TUF is indicated on the
output only when the contents of the Sync Code Register is to
be transferred (transmit sync code on underflow = "I").
Receiver Overrun (Rx Ovrn), S Bit 5
Overrun indicates data has been received when the Rx Data
FIFO is full, resulting in data loss. The Rx Ovrn status bit is set
when Overrun occurs. The Rx Ovrn status bit is cleared by
reading Status followed by reading the Rx Data FIFO or by
setting the Rx Rs control bit.
Rec:eiver Parity Error (PE), S Bit 6
The parity error status bit indicates that parity for the
character in the last register of the Rx Data FI FO did not agree
with selected parity. The parity error is cleared when the
character to which it pertains is read from the Rx Data FIFO or
when Rx Rs occurs. The DCD input does not clear the Parity
Error or Rx Data FIFO status bits.
Interrupt Request (IRQ), S Bit 7
The Interrupt Request status bit indicates when the IRQ
output is in the active state (IRQ output = "Low"). The IRQ
status bit is subject to the same interrupt enables (RIB, TIE, and
EIB) as the fIUJ output. The IRQ status but Simplifies status
inquiries for polling systems by 'providing single bit indication of
service requests.
Table 1 SSDA Programming Model
Control*
Inputs
Register
Status (5)
AS
A/W
0
1
Address
Control
AC2
Register Content
AC1
Bit 7
Bit6
Bit 5
Bit4
Bit 3
Bit 2
Bit 1
BitO
X
Interrupt
Receiver
Receiver
Transmitter
Clear-to-
Transmitter
Receiver
R~st
Parity
Overrun
Underflow
liAQ)
Error
(Ax Ovrn)
(TUF)
Send
(CTS)
Data Carrier
Detect
Data
Register
Data
Available
(ADA)
X
(DCD)
(PEl
Control 1
0
0
X
X
(C1)
...
Receive
Address
Control 1
(AC2)
IAC1)
Enable
(AlE)
Enable
(TIE)
0,
D.
Receiver Transmitter
Interrupt
Interrupt
1
X
X
0,
0,
1
0
0
0
Error
Interrupt
Enable
Transmit
Sync Code
Word
Length
Select 3
(EIE)
on
Underflow
(Tx Sync)
(WS3)
Word
Length
Select 2
(WS2)
Not Used
Not Used
Not Used
Not Used
(C2)
Control 3
(C3)
Address
Control 2
1
Data FIFO
Control 2
Available
(TDAA)
1
0
0
1
Strip Sync
Characters
Transmitter
Reset
Receiver
Reset
(Strip Sync)
(Tx As)
{Ax As)
0,
0,
D.
Word
Length
1·Byte/2·Byte
Peripheral
Peripheral
Transfer
Select 1
(1·Byte/2·Byte)
Control 2
IPC2)
Control 1
(PC1)
Clear
Sync
0,
(WS1)
Clear
Transmitter
Underflow
$ync
~d:*
Transmit
Data FIFO
Clear
CfS
One-Sync·
Characterl
Two·Sync
Status
(Clearers.)
Status
Character
(CTUF)
Mode Control
(1 Syncl
2 Sync)
Internal
1
0
1
0
0,
0
0
0
0
0
0
0
1
0
1
1
0,
0,
0,
D.
0,
0,
0,
D.
• 0; "Low" level,
1; "High" level
** "FF" should not be used as Sync Code.
*** When the SSDA is used in applications requiring the MSB of data to be receive and transmitted first, the data bus inputs to the SSDA
may be reversed (Do to 1 < etc.). Caution must be used when this is done since the bit positions in this table will be reversed, and the
°
parity should not be selected.
~HITACHI
202
Externall
Sync Mode
Control
(Ell Sync)
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131'. (408) 435-8300
--------------------------------------------------------HD6852,HD68A52
Table 2 Functions of SSDA Register
Register
Bit
Symbol
7
iRa
(I
---------PE
Read Rx Data FIFO, or a "1" into
When parity error is detected in
receive data.
-----------------When receive data FIFO overruns.
Rx Rs (CI Bit 01.
--------------------Read Status and then Rx Data FI FO,
4
---------TUF
When under flow is occurred In
3
-c'TS------
·v.,;h;mffl~ig,;alris;":-------
or a "1" Into Rx Rs (Cl Bit 01.
-A"7.,.:-i;;toCTUF(CiBlt3rciinto--Tx Rs (Cl Bit 11.
-A "1"";'i;;toCI...--;-cis-(C3Bit2)-";---
5
Stetus
RegISter
lSI
Function
The i1m flag IS cleared when the source of the IRQ is cleared. The source is determined by
the enables in the Control Registers: TIE, RIE, EIE.
----------Rx Ovrn
2
---------
---
---------
the transmitter.
ConditIOns
for Sat
DCD
When
Conditions
for Reset
DC15 signal rises.
1 Byte Transfer Mode; when
the transmit data FIFO (#11
isempty.
----------------2 Byte Transfer Mode; when the
TDRA
_! ::~:';!!.t~!~~!..(.9!"!!'i!.!) ______ _
Read Status and then Rx Date FIFO
or a "1" into Rx Rs lCl Bit 01
Write Into Tx Data FIFO.
transmit data FIFO (#1, #21 is
---
---------
o
RDA
7
AC2
!~t!.
____________ _
1 Byte Transfer Mode; when the
data is received in the receive
data FIFO (#31.
2 Byte Transfer Mode; when the
data is received in the receive
date FIFO (#2, #31.
Used to access other registers, as shown Table 1 •
----------------
Reed Rx Data FI FO.
... ~ .....~~~ ............\ .............................................................................................................................................
5
Control
Register 1
(CU
RIE
When "1", enables interrupt on RDA (S Bit 0),
:::~::: ::!.~~::::::::::::::::: :::~~~~:~:~::~~~~~~~~:~~~!.~~~~:~~:i.~~~:(~:~~!:!j;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
___ ~_._ .. ~~~~!.~~!!~ .. __ .... ___ ~_~~.~.:·.~::.. ~.I~!'!.~!'!:~~~~_~_~~!~~~~!.~!l.~~!!~!l.i.~~!~?!~: ....... __ ........ __ .. _____ ........................ __ ............. ___ ..
2
Strip Sync
... ," ... --Tx' Ai···· .. --_ .. ----'0'"
--Rx'R~"--""--""
7
EIE
When "1", striPS all sync codas from the received data stream •
.0.
:;';;i8i;-;;';ciin"hibiii- the' i;.a-~;;itt;;; ';;ti~~:"" ...
........................................__ ............ --.. _--_ ... .
\fihe~' ;;i;;
_0 • • • • • • • • • • • • • 0 • • • • • • • • _ _ • • • • • • _0 • • • • • • • • • • • • _ _ _ _ . 0 • • - • • • • • • •
-"wh;;~-;'-;;;:~_i~'i;;d'i;"h;biu'th~';~;iw~MCtio"r;:"'-'"
When "1", enables the PE, Rx Ovrn, TUF, CTS, and DCD interrupt flogs IS Bits 6 through 21 •
........ ....................... ···wlij,;;·;;';;:iili;,;;;~·iV;;.;·i:od;;·co;;j;,;;U·;;,·bi.. i;~;;iie~;:~d·o~·;;~d~;:il;,;;;;ii~d·,;;;~bl;;;·itijiTUF·······················
Control
Register 2
(C21
6
Tx Sync
StatuI bit and output. When "0". an all mark character is transmitted on underflow.
"'5'"
·Wii3················
.........................................................................................................................................
.
4
3
WS2
WSI
Word Length Select
2
I.Byte/2.Byte
When "1", enables 1he,TDRA and RDA bits to indICate when al-byte transfer can occur; when
1
o
PC2
PCl
SM/I5'fl!i Output Control
3
CTUF
When "1", cleers TUF (S Bit 41, and IRQ if enabled.
..................................::~::~.~~.:!"!?~.~.~~~.r:':~~.~!~~.!~!~~.~.~~~~.~.~..~.~~.!~~!!~~~.~.~~.?~~~~: ....... .-................................... .
Control
Register 3
(C31
"'2'" ..
.. ····· .................................................................
cl;;~;·rn········ ···wh.·~·;;;;;:;;I;;,;;;·rn·is·Bii·3y:~;;dnm·ij·~·~~bi~d
...., ... ",:SyiiCi2:Sync'"
···wti;;~·;;;;;:~I;;i:u·ih~·O;;HV,;;;.;;h;;~~i:t;;.;·riiOii.·;·~h;;;;;iY;:·;;i;,;;i;t·h~·t~~y;;;,:;;.;.;,~;;.;i~~·;;;~d,;:················
---0--- --eji"svi,c·--------- -"-W"hen-;;P;;ielecu-ihe-externai"iYiic-n.;0d8;w-hen-;'O;i:ie"lt;cii-ihe";.;terniriy".;c-mode:-----------------------""-----
Table 3 Word Length
Bit 5
WS3
0
0
0
0
1
1
1
1
Bit 4
WS2
0
0
1
1
0
0
1
1
Bit3
WSI
0
1
0
1
0
1
0
1
Word Length
6 Bits + Even Parity
6 Bits + Odd Parity
7 Bits
8 Bits
7 Bits + Even Parity
7 Bits + Odd Parity
8 Bits + Even Parity
8 Bits + Odd Parity
~HITACHI
Hilachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
203
HD6852,HD68A52-------------------------------------------------------•
Table 4 SM/DTR Output Control
Bit 1
PC2
0
0
1
1
Bit 0
PCl
0
1
0
1
SM/DTR Output at Pin 5
"High" level·
Pulse --.r-Ll-Bit Wide, on SM
"low" level·
SM Inhibited, "low'"
• OUTPUT level is fixed by the data written into PC2, PC1 .
•• When "10" or "11 ", output is fixed at "low".
Register Select (RS)
The Register Select line is a high impedance input that is
TIL compatible. A "High" level is used to select Control
Registers C2 and C3, the Sync Code Register, and the
Transmit/Receive Data Registers. A "Low" level selects the
Control 1 and Status Registers (see Table I).
•
Interrupt Request (I RQ)
IRQ is a TTL compatible, open-drain (no internal pullup),
active "Low" output that is used to interrupt the MPU. The
IRQ remains "Low" until cleared by the MPU.
•
RDA'PE
Rx Dvm
CTS
DCD
TUF
TDRA
RDA
•
INTERFACE SIGNALS FOR MPU
The SSDA interfaces to the HD6800 MPU with an 8-bit
bi-directional data bus, a chip select line, a register select line, an
interrupt request line, read/write line, an enable line, and a reset
line. These signals, in conjunction with the HD6800 VMA
output, permit the MPU to have complete control over the
SSDA.
•
Bi-Directional Data Bus (0 0 -07 )
• CLOCK INPUTS
The bi-directional data bus (Do -D 7 ) allow for data transfer
between the SSDI\ and the MPU. The data bus output drivers
are three-state devices that remain in the high impedance (off)
state except when the MPU performs an SSDA read operation.
•
Enable (E)
The Enable signal, E, is a high impedance TTL compatible
input that enables the bus input/output data buffers, clocks
data to and from the SSDA, and moves data through the FIFO
Registers. This signal is normally the continuous HMCS6800
System <1>2 clock, so that incoming data characters are shifted
through the FIFO.
•
Reset (RES)
The RES input provides a means of resettin~e SSDA from
an external source. In the "Low" state, the RES input causes
the following:
I) Receiver Reset (Rx Rs) and Transmitter Reset (Tx Rs) bits
are set causing both the receiver and transmitter sections to
be held in a reset condition.
2) Peripheral Control bits PCI and PC2 are reset to zero,
causing the SM/DTR output to be "High".
3) The Ertor Interrupt Enable (EIE) bit is reset.
4) An internal synchronization mode is selected.
5) The Transmitter Data Register Available (TDRA) status bit is
cleared and inhibited.
When RES returns "High" (the inactive state), the transmitter and receiver sections will remain in the reset state until the
Receiver Reset and Transmitter Reset bits are cleared via the
bus under software control. The control Register bits affected
by RES (Rx Rs, Tx Rs, PCI, PC2, EIE, and E/I Sync) cannot be
changed when RES is "Low".
Read/Write (R/WI
The Read/Write line is a high impedance input that is TIL
compatible and is used to control the direction of data flow
through the SSDA's input/output data bus interface. When
Read/Write is "High" (MPU read cycle), SSDA output drivers
are turned on if the chip is selected and a selected register is
read. When it is "Low", the SSDA output drivers are turned off
and the MPU writes into a selected register. The Read/Write
signal is also used to select read-only or write-only registeres
within the SSDA.
Separate high impedance TIL compatible inputs are provided for clocking of transmitted and received data.
• Transmit Clock (Tx ClK)
The Transmit Clock input is used for the clocking of
transmitted data. The transmitter shifts data on the negative
transition of the clock.
•
Receive Clock (Rx ClK)
The Receive Clock input is used for clocking in received data.
The clock and data must be synchronized externally. The
receiver samples the data on the positive transition of the clock.
• SERIAL INPUT/OUTPUT LINES
• Receive Data (Rx Data)
The Receive Data line is a high impedance TIL compatible
input through which data is received in a serial format. Data
rates are from 0 to 600 kbps.
•
Transmit Data (Tx Data)
The Transmit Data output line transfers serial data to a
modem or other peripheral. Data rates are from 0 to 600 kbps.
• PERIPHERAL/MODEM CONTROL
OIl
Chip Select ICS)
'This high impedance TTL compatible input line is used to
address the SSDA. The SSDA is selected when CS is "Low".
VMA should be used in generating the CS input to insure that
false selects will not occur. Transfers of data to and from the
SSDA are then performed under the control of the Enable
signal, Read/Write, and Register Select.
The SSDA includes several functions that permit limited
control of a peripheral or modem. The functions included are
C'rS, SM/DTR, DCD, and TUF.
•
Clear-to-Send ICTS)
The CTS' input provides a real-time inhibit to the transmitter
~HITACHI
204
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------HD6852,HD68A52
section (the Tx Data FIFO is not disturbed). A positive ers
transition resets the Tx Shift Register and inhibits the TDRA
status bit and its associated interrupt in both the one-synccharacter and tw is stored within the SSDA to
insure that its occurrence will be acknowledged by the system.
(if enabled)
The stored Den information and its associated
are cleared by reading the Status Register and then the Receiver
FIFO, or by writing a "1" into the Receiver Reset bit. The J5CI)
status bit sub~ently follows the DeD input when it goes
"Low". The DCIJ input provides character synchronization
timing for the receiver during the external sync mode of
operation. The receiver will be initialized and data will be
sampled on the positive transition of the fl1"St full Receive Clock
om
cycle after release of Den (see Figure 7).
•
Sync Mach/Datil Terminal Ready (SM/DTR)
The SM/D'fR output provides four functions (see Table 4)
depending on the state of the PCl and PC2 control bits. When
the Sync Match mode is selected (PC 1 = "I", PC2 = "0"), the
output provides a one-bit-wide pulse when a sync code is
detected. ·This pulse occurs for each sync code match even if the
receiver has already attained synchronization. The SM output is
inhibited when PC2 = "I". The ~ mode (PCI = ''0'')
provides an output level corresponding to the complement of
PC2 (DfR = "0" when PC2 = "I ".) (see Table 4.)
•
Transmitter Underflow (TUF)
The Underflow output indicates the occurrence of a transfer
of a "fill character" to the Transmitter Shift Register when the
last location (#3) in the Transmit Data FIFO is empty. The
Underflow output pulse is approximately a Tx CLK "High"
period wide and occurs during the last half of the last bit of the
character preceding the "Underflow" (see Figure 4). The
Underflow output pulse does not occur when the Tx Sync bit is
in the reset state.
• NOTE FOR USAGE
If the hold time of CS signal and R/W signal is within 50230 ns, there is a case that Transmit Data FIFO is not cleared
and TDRA flag is not set when software reset using TxRS
(TxRS=I) is executed. Hmal program for data transmission will
start to send the data as shown in Fig. II and Fig. 12.
In this case, the data of the first three bytes are not preset
and unexpected data which is remaining in Transmit Data FIFO
are sent in the first two bytes.
DTA
TxAs
RxRs
#3
TxData
1!14
RxData
TORA
When addrlll hold time
IS
Within 50-230 nt, sometlmel
TOR A flag IS not set.
Figure 12 Transmission Start Sequence
Figure 11 Normal Flow of Starting
the Transmission and Reception
In case of SSDA, Address Hold Time should be from 20 to
50 ns or over 230 ns.
•
OeD Input in External Synchronization Mode
In case of receiving data in External Synchronization Mode,
Receive data is put off by one bit at times, when DeD is drived
like..f1. in RxCLK cycle in which RDA flag is set.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 951:31 • (408) 435-8300
205
HD6852,HD68A52--------------------------------------------------------
,
D. starts at RxCLK risa after 1lCD""L
(Usual easa)
RxCLK
0,
0,
0,
RxData
D.
0,
D.
0,
0,
RDA flag-:....--...II'~--t-_If_------------------I ,~_ _ __
t
Road oparation of Racai...
Data FIFO aftar road
_ _ operation of Status Ragister
DCD input
Road operation of Raeai ... Data FIFO aftar
road oparation of Status Ragist..
(Data $FO)
RxCLK
RxData
0,
D.
0,
0,
0,
D.
D.
0,
0,
0,
RDA flag
~------~~I'~------------------------------~,~---
I
Read oporation of Racai ... Data FIFO aftar
read oporation of Status Ragistar
Road oporation of Racai... Data FIFO after road
operation of Status Ragistar (Data $78)
DCD input
------+---..1
Figure 13 Exceptiona) External Sync Operation
To avoid this case, use SSDA in the following method.
(1) DCD Land RxCLK L should meet the relation shown
in Fig. 14.
RxCLK
!
""!_..JX
RxData,_ _ _ _ _ _ _--!-o!
o
o
o
o
0
'
0
0
D.
X...__D..;,'__
0
0
0
0
~
. tl . t2 •
t, ~ 500 nsec
t, >0
Figure 14 OeD Input Timing in External Sync Mode
(2) RxData should be input regarding the second RxCLK rise
as Do bit, after DCD~.
~HITACHI
206
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
HD4650S, HD4650S-1,
HD4650SA, HD4650SA-1
ADU (Analog Data Acquisition Unit)
The H046508 is a monolithic NMOS device with a IO-bit
analog-t
I
0>
U1
_r----,.o----
LATCH
TRI-STATE BUFFER
(
I
='-
»
3
CD
".
()
'!:'"
CLK
?-
'"'"0
0
o1~
Q.
'"~
•
~C~
~
T
(flC")
EXPAND
'" 1:
.'0"
CONTROL
:::>
'"
::>
c....
0
~
,I,J,
rl
I
REG.O
~,~:
I
r
tJ
REG. 1
REG.4
~ '.
T".,
-
r'l
I
(Reg. 0)
L1
II
I
CH. MPX
0
0+-
Tj
11
~!~!:::,k----
CS,
CIRCUIT
RS,
~
'::c
RS,
0>
CD
'"~
RES
f---
AI,
RESISTANCE &
DECODER)
~
@,®
MODE SELECT
& GAINSEL
OONffiOL
AI,
L..._ _ _ _ _ _...,..._ _--'
,
:
,
ANALOG
MPX
I---
:
:
,
:
/:-
:
L+~----~~C
:
0
S
...
AilS
COMPARATOR
'"'"Co
1
w
0
0
®
DO-D3 (Reg. 1)
MI
GAINSEL
REF(+) REFH
Figure 1 Internal Block Diagram
0
(Xl
~
(Regl'~' 1)
.J
~
0
.j:>
0>
(J>
»
0
(Xl
:J:
R/W
I
D/A
(1024 LADDER
REGISTER
i--ST
(Reg.O)
0
.j:>
U1
}>
/
SUCCESSIVE
APPROXIMATION
PC, GS, GO, Gl
C{J
U1
~
@
.j:>
0>
U1
@"""I
lJ
CS,
••
~----I
BASIC
TIMING
GENERATOR
1:
'c:"
I
CH. MPX
IRQ
~
()
J
:J:
0
-
J
0
E
s.o
COMPIN
COMMON
"206" : Fixed Data for Auto Range-Switching x 4
"410": Fixed Data for Auto Range-Switching x 2
- - - - - - - - - - - - - - - - - - - H D4650B,HD4650B-1,HD4650BA,HD4650BA-1
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Supply Voltage
Vcc
VIn·
Input Voltage
Analog Input Voltage
·
Operating Temperature
VAin
T oDr
Storage Temperature
T ltg
·
Value
Unit
-0.3-+7.0
V
-0.3-+7.0
V
-0.3-+7.0
V
·C
- 20- +75
- 55- +150
·C
• Wnh_t to Vss (SYSTEM GNDI
[NOTE) Pe"""nent LSI de~ may occur if maximum ratingsara exceeded. Normal """ration should be uncler "",ommendad operllling conditions.
If theaa condition. era ex088dad, It could affect raliability of LSI.
•
RECOMMENDED OPERATING CONDITIONS
Item
Supply Voltage
Symbol
min
Vcc·
V,H
V ,L
4.75
2.0
..
·
Input "High" Voltage
Input "Low" Voltage
Analog Input Voltage
VAin
-0.3
VREF(-l
Operating Temperature
Topr
V
-
V""
0.8
V
V
V
-
-
VREF(+1
Vcc+O.25
-0.1
0
-
Vcc
-2-
-20
25
VREF(+1 + VREF(-l
2
Voltage Centar of Ladder
Unit
5.25
Vee
0
..
max
-
VREF(+I·
Reference Voltage
typ
5.0
V
V~C+O.25
V
·C
75
·With respect to Vss (SYSTEM GNO)
• J:LECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS<1> (Vee -6V ± 5%, Vss -OV. Ta - -20-+75·C.unless otherwise notad.)
Item
Input "High" Vultage
Symbol
Input "Low" Voltage
Do -0 7
Output "High" Voltage
Output "Low" Voltage
Test Condition
GAINSEL
VOH
IRQ
-0.3
IOH
IOH
=-205IlA
z
-200,.tA
VOL
2.4
2.4
typ
max
Unit
-
Vcc
0.8
V
-
-
V
V
IOL =3.2mA
-
-
-2.5
-
2.5
p.A
-10
-
10
p.A
-
-
10
p.A
500
12.5
mW
pF
=-lOj.tA
IOL = 1.6mA
IOH
0.-0" GAINSEI,
min
2.0
V'H
V,L
Vcc- 1.O
0.4
0.4
V
E.CLK, R/W
Input Leakage Current
RES. Rio. RS I
lin
Vin
=0 -
=0.4- 2.4V
5.25V
CSO. CS I
Three-State (off state)
Input Current
Do - 0 7
ITSI
Vin
OutPUt Leakage
Current
IRQ
I LOH
VOH
Power Dissipation
=2.4V
Po
0 0 -07
Input Capacitance
C'n
f
=OV. Ta = 25·C
= 1 MHz
-
-
10.0
pF
Cout
Vin =OV, Ta = 25"C
f= 1 MHz
-
-
10.0
pF
E.CLK. R/W
RES. Rio, RS I
Vin
CSo. CSI
Output Capacitance
IRQ. GAINSEL
~HITACHI
Hitachi Amenca Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
209
H D46508,HD46508-' ,H D 4 6 5 0 8 A , H D 4 6 5 0 8 A - 1 - - - - - - - - - - - - - - - - - - - •
DC CHARACTERISTICS <2> (Vee = 5V ± 5%, Vss = OV, Ta - -20-+75°C, unless otherwise noted.)
Item
Test Condition
VAin
Analog Multiplexer ON Resistance
= 5.0V,
Vee = 4.75V, Ta = 25°C
VAin = 5.0V
Vee = 4.75V, Ta = 25°C
min
typ
max
-
-
1
k!l
-
10
100
nA
-10
-
nA
-
-
7.5
pF
10
-
40
k!l
Unit
COMMON=OV
OF F Channel Leakage Current
VAin = OV, Ta = 25°C
-100
Vee = 4.75V, COMMON = 5V
Analog Multiplexer Input Capacitance
Ladder Resistance
V REF
(from REF(+) to REF(-))
VREF H
(+)
= 5.0V
= OV, Ta = 25°C
• CONVERTER SECTION (Ta = 25°C, Vee = VREF (+) = 5.0V, tcyoC - 1111, unless otherwise noted.)
1. 10-BIT AID CONVERSION
Resolution
Non-linearity Error
Zero-Error
Absolute Accuracy
typ
min
·
Full-Scali Error
Ouantization Error
HD46508, HD46508·1
HD46508A, HD46508A·l
Item
·
-
typ
max
Unit
max
min
-
bits
±1
±3
LSB
±112
±1
LSB
±112
±1
LSB
±112
LSB
±2
±4
LSB
10
-
±112
±1
±1/2
±3/4
±1/4
±1/2
-
±112
-
±1
±3/2
-
10
-
2. 8-BIT AID CONVERSION
min
typ
8
-
-
bits
±1/4
-
8
±1/8
±1/4
±3/4
LSB
±1/4
±3/8
-
±3/8
±1/2
LSB
-
±1/4
±3/8
-
±3/8
±112
LSB
-
-
±1/2
-
-
±1/2
LSB
±5/8
±3/4
-
±3/4
±5/4
LSB
typ
-
Full-Scali Error
Ouantization Error
Zero-Error
Absolute Accuracy
·
·
Unit
max
min
Resolution
Non-linearity Error
HD46508, HD46508-1
HD46508A, HD46508A-l
Item
max
3. PROGRAMMABLE VOLTAGE COMPARISON (PC)
HD46508A, HD46508A-l
Item
Resolution
Non-linearity Error
Zero-Error
Full-Scali Error
Absolute Accuracy
·
·
HD46508, HD46508-1
typ
max
min
typ
max
-
8
-
8
-
bits
±1/8
±1/4
-
±1/4
±3/4
LSB
±1/4
±3/8
±3/8
±1/2
LSB
±1/4
±3/8
±3/8
±1/2
LSB
±3/8
±5/8
±112
±1
LSB
-
'Temperature Coefficient; 25 ppm of FSAfc (max)
~HITACHI
210
Unit
min
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - H D46508,H D46508-1 ,H D46508A,HD46508A-1
•
AC CHARACTERISTICS (Vee= 5.0V ± 5%, Vss = OV, Ta = -20- +75°C, unless otherwise noted.)
1. CLOCK WAVEFORM
Item
Test
Conditions
Symbol
ClK Cycle Time
ClK "High" Pulse Width
tcvcc
PW CH
ClK "low" Pulse Width
PW CL
-
10
0.5
-
5
liS
4.5
0.22
2.2
liS
4.0
0.21
-
2.1
liS
-
25
-
-
25
ns
0.40
-
tCr, tCf
ClK
max
1.0
Rise and Fall Time of
Unit
typ
0.45
Fig. 2
CD" = 1
CD" = 0
min
min
typ
max
" eo: ClK Divider bit
2.0V
2.0V
O.8V
CLK
~------PWCH--------~tCf~------PWCL--------·
~----------------------tcvcC ----------------------'"1
Figure 2 ClK Waveform
2. IRQ, GAINSEl OUTPUT
Item
I RQ Release Time
GAINSEl Delay Time
Symbol
tlR
t GSD1
Test condition
Fig. 3
Fig.4
tGS02
min
-
typ
max
Unit
-
750
ns
750
ns
750
ns
tGS01: TTL Load
tGS 02: CMOS Load
- - - I E/
Figure 3 IRQ Release Time
@HITACHI
Hitachi America Ltd • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
211
H D4650S,HD4650S-1,H D4650SA,H D 4 6 5 0 S A - 1 - - - - - - - - - - - - - - - - - - (1) Sample & Hold
2.0V
CLK_ _ _- ,
~
Vee"O.7·
. .",.--------------
GAINS_E_L_ _ _ _~------'
'CMOS Load
tGS01
'aS02
(2) x2, x4 Auto Range·Switching, Programmable Gain
CLK
O.BV
------Vcc xO.7* ,.,
1-+-----'CMOS Load
Figure 4 GAINSEL Delay Time
3. BUS TIMING CHARACTERISTICS
READ OPERATION SEQUENCE
Item
Symbol
Test
Condition
min
typ
Enable Cycle Time
tcycE
1.0
-
Enable "High" Pulse Width
PWEH
0.45
-
Enable "Low" Pulse Width
PWEL
0.40
Rise and Fall Time of Enable
t Er tEf
-
Address Set Up Time
tAS
Data Delay Time
tOOR
-
Data Access Time
tAee
-
Fig. 5
H 046508· 1
HD46508A·l
HD46508
HD46508A
140
Data Hold Time
tH
10
Address Hold Time
tAH
10
-
Unit
min
typ
-
0.666
-
0.28
-
220
ns
-
360
ns
-
-
ns
max
0.28
25
-
-
140
320
-
460
-
10
10
max
-
/oIs
-
/oIS
25
/oIS
ns
-
ns
ns
@HITACHI
212
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
- - - - - - - - - - - - - - - - - - - H D46508,HD46508-1 ,HD46508A,HD46508A-1
WRITE OPERATION SEQUENCE
Item
Symbol
Enable Cycle Time
Enable "High" Pulse Width
Enable "Low" Pulse Width
tcvcE
PWEH
PWE
tEr, tEf
tAS
Rise and Fall Time of Enable
Address Set Up Time
Data Set Up Time
Data Hold Time
Address Hold Time
Test
Condition
Fig. 6
tosw
tH
tAH
HD4650S
HD4650SA
typ max
min
1.0
0.45
0.40
25
140
195
10
10
-
-
-
HD4650S·1
HD4650SA·l
typ max
min
-
0.666
0.2S0
0.280
-
-
-
140
80
10
-
10
-
-
-
25
-
Unit
/1.5
/1.5
ItS
ns
ns
ns
ns
ns
tcycE
-
2.DV
IEr_
__lAS
RS., RS,
R/W,CS.
~
PWEH
I--IOOFl_
O.BV
O.BY
PWEL
!-IAH·
2.DV
2.DV-'
r O.BY
t ACC
0.-0,
!2.0V
\f.-IEf
O.sv
E
cs,
/r-
2.0V
,
2.4V
-
O.sv
IH
O.4V
K
I-~2.4V
1/
O.4V
Figure 5 Read Timing
~HITACHI
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
213
HD4650B,HD4650B-1,H D4650BA,H D 4 6 5 0 B A - 1 - - - - - - - - - - - - - - - - - - tcvcE
~~2.0V
tEr_
O.SV
E
--
V
I+-
-tAS
RS" RS,
CS,
~
2
\ _ t Er
ov
•
O.SV
O.SV
PWEL
PWEH
_tDSW_
Cs" A/W
1
2.0V
~tAH'"
2.0V
2.0V
O.SV
O.SV
K
- -X
K
tH
2.0V
2.0V-'
O.SV
O.SV
Figure 6 Write Timing
5.0V
5.0V
R
TNt Point 0 - -....-
.....--1. .---.
Telt Point
o--....._.---+..~
r!
R
!
LOAD A
(D,~D,.
AL
R
GAINSELI
• 2.4kO
• llkO
C
• 130pF
LOAD B (iRQl
Rc
R
C
Diode· 152074(8
• 2.4kO
• 3kO
• l00pF
Diode· 152074S
or Equivalent
or Equivalent
LOAD C (GAIN5ELI
Figure 7 Test Load
~HITACHI
214
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - H D46508,HD46508-1 ,HD46508A,HD46508A-1
does not affect this signal.
• SIGNAL DESCRIPTION
• Analog Date Interflce
Analog Input (Al o-AI 15 )
• Proceaor Interface
Date Bu. (00 -0,)
The Bi-directional data lines (Do -D,) allow data transfer
between the ADU and MPU. Data bus output drivers are
three state buffers that remain in the high·impedance state
except when MPU performs a ADU read operation.
Enable (E)
The Enable signal (E) is used as strobe signal in MPU R/W
operation with the ADU internal registers. This signal is
normally derived from the HMCS6800 system clock (~).
(CSo,CSI )
Chip Select
The Chip Select lines (CSo , CS I ) are used to address the
ADU. The ADU is selected when CSo is at "High" and CSI is
at "Low" level.
ReadlWrite (R/W)
The R/W line controls the direction of data transfer between the ADU and MPU. When R/W is at "High"level, data
of ADU is transferred to MPU. When R/W is at "Low" level,
data ofMPU is transfemd to ADU.
Register Select (RSo, RS I )
The Register Select line (RS o , RS I ) are used to select one
of the 4 ADU internal registers. Table 1 shows the relation
between (RSo, RS I) address and the selected register. The
lowest 2 address lines of MPU are usually used for these
signals.
Reset (RES)
This input is used to reset the ADU. An input "Low" level
on RES line forces the ADU into following status.
1) All the shift-registers in ADU are cleared and the conversion operation is stopped.
2) The GAINSEL output goes down to "Low" level. The
IRQ output is made "Off" state and the Do -D, are made
high impedance state.
Interrupt Requllt
mrn)
(Open Drlin OutpUt)
This output line is used to inform the AID conversion end
signal to the MPU. This signal becomes active "Low" level
when IE bit in the control register I is "I" and IRQ bit in
the control register 2 goes "I" at the end of conversion. And
this signal returns to "High" right after The MPU reads the
!tD Data Register (R3). Programmable voltage comparison
The Input Analog Data to be measured is applied to these
Analog Input (Alo-AI ls ). These are multiplexed by internal
16 channel multiplexer and output to COMMOM pin. A
particular input channel is selected when the multiplexer
channel address is programmed into the control Register 1
(Rt).
Multipllxer Common Output (COMMON)
This signal is the output of the 16 channel analog multiplexer, and may be connected to the input of pre-amplifier
or sample/hold circuit according to user's purposes. When no
external circuit needed, this output should be connected to
the COMPIN input.
Comparltor Input (COMPIN)
This is a high impedance input line that is used to transmit
selected analog data to comparator. The COMMON line is
usually connected to this input. When external Pre-amplifier
or Sample/hold circuit is used, output of these circuits may
be connected to this input.
Reference Voltage (+) (REF (+))
This line is used to apply the standard voltage to the internalladder resistors.
Reference Voltage (-) (REF
(-II
This line is connected to the analog ground.
• ADU Control
Conversion Clock (ClK)
The CLK is a standard clock input signals which defines
internal timing for AID conversion and PC operation.
Glln Select (GAINSEl) (CMOS Compatible Output)
This output is used to control the external circuit. The
function of this signal is programmable and it is specified
by (GI, GO) bits in Control Register O. By using this output,
user can control the auto-range-switching of external preamplifier, also control external sample & hold circuit, etc. as
well.
[NOTE) This LSI is different from other HMCS6800 famBy
LSIs in following function
doesn't affect IE bit of RO
•m
• FUNCTION OF INTERNAL REGISTERS
• Structure
Table 1 Internal Registers of the ADU
(Notel
0 - •• VES
x ·--NO
$
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
215
H 046508,H 046508-1 ,H 0 4 6 5 0 8 A , H 0 4 6 5 0 8 A - 1 - - - - - - - - - - - - - - - - - - - Control Register 0 (RO)
Mode Select
Not Used
Not Used
"1"
See Table 2
"0"
Not Used
II'------- :
Settling Time
Available
Not Available
ClK Divider
Interrupt Enable'
ClK/2
Enable IRQ
ClK
Mask IRQ
·RES doesn't affect IE bit.
Figure 8 Control Register 0
Control Register 1 (R1)
17161514131211101
1 sc 1 GS 1 PC 1 MI 1 D3 1 D2 1 D1 1 DO 1
I'
I
"1"
'•
MPX Channel Address
"0"
See Table 3
MPX Inhibit
Inhibited
Not Inhibited
Prog. Comparator Select
Prog. Comparator mode
AID Converter mode
GAINSEl Enable
GAINSEl Enable
GAINSEL Disable
Short-cycle Conversion
8-bit length
10-bit length
Figure 9 Control Register 1
Status & AID Data Register (H)
17161514131211101
IIRQIBSVlpco ~ OV 1 DW 1 C9 1 C8 1
I
"1"
L
Upper bit (10 bit data) ,
Data Weight
Data Over Scale flag
"0"
See Table 4.
Data is over scale
With in the scale
Programmable
Comparator Output
VAin >Vp
VAin PCO
VAin >Vp
"0" -> PeO
VAin < Vp
VAin: Analog Input
Voltage to be
compared
Vp : Programmed Voltage
• = See Table 6
[NOTE] CO bit and ST bit are effective in every cas•.
Status & AID Data Register (H) (R2)
This register is a 7·bit read only register that is used to
store the upper 2-bit data (C8, C9), data weight (OW), data
overscale (OV), programmable comparator output (PCO),
busy (BSY) and interrupt request(iRQ).
(C8, C9)
These bits store upper 2-bit data mea·
(Upper bit data) sured by 10 bit length conversion.
(R4)
BSYbit
(Busy)
This bit indicates that the ADU is now
under conversion.
IRQ bit
(interrupt
Request)
This bit is set when the AID conversion
has completed and cleared by reading
the R3.
AID Data Register (L) (R3)
OW bit
(Data weight)
This bit indicates data weight when
Auto range-switching mode is selected.
This bit is set or reset when the conversion has completed. The conditions
are shown in following Table.
In this mode GAINSEL output also goes
"High" or "Low" on the same condition shown in Table 5.
Other status of OW bit is shown in
Table 6.
This register is an 8-bit read-only register that is used to
store the lower 8 bits data of lO·bit conversion or full 8 bits
data of the 8-bit conversion.
PC Data Register (R4)
This register is an 8-bit write-only register prepared for
Programmable Voltage comparison. Stored data is converted
to digital voltage, and compared with analog input to be
measured. The result of comparison is set into PeO bit.
Table 5 Data Weight (DW) Set or Reset Condition
~
Set
Mode
("1")
Auto Range-Switching (x2)
V .
Aln
< 1024
410 • V
REF(+)
Auto Range-Switching (x4)
VAin
< 1024 • V REF (+)
206
Reset
410
VAin> 1024 • V REF (+)
206
VAin> 1024 • V REF (+)
VAin
: Analog Input Voltage to be measured
VREF(+) . Voltage Applied to REF(+)
~HITACHI
21S
("0")
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
WRITE WAITE
Reg 0 Reg 1
J:
~
o
I
•
I
I
I
I
I
I
I
I
I
I
I
:
i
:
I
I
I
:
! :
~
I
:
"~':lE'-"-
3
~-=.'==
°0-°7
~
o·
III
~
mOl
~
o
\
Contml
Register
~I
o
•
ol~
0W//uH4@X
to
_
~J:
CD
;
mO
~
<-
~
51>
I II
ilh
K
ClK
o
~
I
I
I
Afil'l.CS,
»
I
I
I
I
Cst
~
READ READ
Reg 2 Reg 3
~~~,,,on~
MPX Out
Analog
J:
MSBI2')
II
2"
lSBI2")
~
=
=~=-================:::::::3lll::::=::::~L~==nllfTl
1,1
BSV
"
ConversIon end
iRa
tI
~
~
~
~
~
$
~
i
J:
o
.j:>
Ol
(J1
o
~
Status & AID
~a;f Register
(HI
AID Data
Register (U
IR3)
•
W}}}}"~
J:
o.j:>
Ol
~~~~-----------Figure 13 AID Conversion Timing Chart (Basic Sequence)
(J1
o
CfJ
J:
o
.j:>
Ol
(J1
o(Xl
"J>
J:
o
.j:>
Ol
(J1
N
~
CD
o
(Xl
~
HD4650S,HD4650S-1,HD4650SA,H D 4 6 5 0 S A - 1 - - - - - - - - - - - - - - - - - - • AID Conversion and PC sequence
10 bits AID Conversion
(tcvc=1Ils)
Conversion Start
,) Basic Sequence
Conversion End
( ~~: ::g::)
20
(LSB)
GS= "0"
2) Basic Sequence
(When overscale
is detected)
Overscale check Cycle
(Analog Input is compared with V REF (+).)
3) Expanded Sequence
(
"0")
SC =
ST = "'"
GS= "0"
MSB cycle is expanded to compensate external amplifier's settling delay.
4) Auto Range-
Switching Control
Sequence
SC = "0"
ST = "0"
GS= "'"
GO= "0"
(G,
9j.ts=.:J---- Auto Range-switching cycle
(Analog Input is compared with '/2 V REF (+) or '/4 V REF (+)
at this cycle)
= ",,,)
or
( GO = "''')
G, = "0"
al Analog Input < 1/2 V REF (+) or 114 V REF (+)
5) Auto Range-
Switching & Expansion
Control
Sequence
SC = "0"
r - - - -.... "GAINSEL"goes "High"
ST
= "'"
GS =
"'" 1~r.r.<.i;~""'~~"""'L::.::.::~--4--L---L-.......J--..L---L---lL--..L.,;=:.:.J
GO= "0"
(G,
= ",,,)
or
b) Analog Input> l/2V REF (+) or 1/4VREF (+)
,GO= "'"
\G1 = "0")
6) Sample & Hold
Control Sequence
( ~~: ::g::)
GS= "'"
GO= "0"
G, = "0"
~HITACHI
220
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - H D4650B.H D4650B-1.HD4650BA.HD4650BA-1
7) Programmable
Gain Control
Sequence
"GAINSEL" always goes "High"
( ~~: ::g::)
GS= "I"
GO= "I"
Gl = "I"
8) Programmable
Gain & Expansion
Control Sequence
SC = "0")
ST = "I"
( GS= "I"
GO= "I"
Gl ="I"
8 Bit AID Convarsion
1) Basic Sequence
SC = "I"
"0")
( ST GS= "0"
Additional conversion cycle
for rounding the LSB - 1 Bit .
./.
2) Expanded Sequence
"I")
=
( SC
ST = "I"
GS= "0"
Programmable Voltage Comparison
1) Basic Sequence
( PC = "1")
ST
= "0"
2) Expanded Sequence
( PC =
ST = "I"
"I")
• HOW TO USE THE ADU
• Functions of GAINSEL
The ADU is equipped with programmable GAINSEL output signal. By using GAlNSEL output and external circuit,
the ADU is able to implement following control.
1) Auto Range-Switching (Auto Gain) Control
2) Programmable Gain control
3) Sample & Hold control
GAINSEL output is controlled by Mode Select bit (GO,
GI) when GAINSEL enable bit (GS) is "I".
Table 6 GAINSEL Control
GS
Gl
0
x
1
1
1
1
•
GO
x
GAINSEL
"Low"
0
0
0
"High"
1
0
..
1
1
"High"
1
Control Mode
Normal Use (GAINSEL is not used)
Sample & Hold control
Auto Range S~itching x 2 control
Auto Range Switching x 4 control
Programmable Gain control
OW
0
0
....
1
GAINSEL goel "High" or "Low" according to the condition shown in Table 5.
Sao, Table 5.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
221
H D46508,HD46508-1 ,H D 4 6 5 0 8 A , H D 4 6 5 0 8 A - 1 - - - - - - - - - - - - - - - - - - +8V
How to Control External Circuit
(I) Sample & Hold Control (GI=O, GO=O)
An example of Sample & Hold circuit is shown in Fig. 14.
When ADU is set in Sample & Hold Control Mode, GAINSEL
becomes "High" level on conversion and controls the data holding.
(2) Automatic Range Switching Control (GI=O, GO=I or GI=
I, GO=O)
The GAINSEL signal controls the external amplifier which can
change the ratio of voltage amplification. (GAIN: 1 .... 2 times or
I .... 4 times). Fig. 15 shows Automatic Range Switching Control. In this case, when the input voltage is lower than 206/1024
V REF(+), GAINSEL becomes "High"'evel. This makes the GAIN
of the amplifier change from I to 4 times, and 4 times value
of the input voltage is AID converted. Using this function even
if an input signal is small, it is possible to execute AID conversion in nearly full scale. In this mode, when GAINSEL signal
becomes "High", DW bit becomes "I" to show the range
switching is in a progress.
(3) Programmable GAIN Control (GI=I, GO=I)
The GAINSEL signal is used for controlling the external
amplifier of any GAIN which is fit to the system.
In this mode, GAINSEL always becomes "High" at the
beginning of AID conversion, so the change of range is controlled by GS bit. Converted data need to be corrected in software in accordance with GAIN of the amplifier.
This mode is effective in the case of converting very small
input voltage.
(Note) Refer to "ADU Function Sequence" (AID Conversion
and PC Sequence) for the timing in which GAINSEL signal becomes "High". GAINSEL signal becomes
"Low" in accordance with "I" .... "0" change of BSY
bit. Refer to Fig. 13.
GAIN
v ..
REF (-I COMPIN
SEL
ADU
Figure 15 Pre-amplifier Circuit
(xl, x4 Auto-Range Switching)
•
Overseale Check
ADU is equipped with hardware overscale detection
function. The overscale detection is performed automatically when the result of AID conversion is 2n-1 (all
bits = I). When analog input VAin is higher than VREF(+),
overscale bit (OY) is set to "I". The defmition ofthe overscale is illustrated in Fig. 17. And the flow of overscale
check is shown in Fig. 16.
x1 Sample & Hold
HD14066
OR EQU
Figure 16 Overscale Check Flow
2"
r------------------I
2"-111,:
ff1
"
8
I
1101
: overseale area
I
~AOU
'0':
I
I
I
,
'00,
I
I
COMMON
Vss
GAINSEL
REF(-)
COMPIN
ADU
I
I
0101
I
I
I
I
0011
I
000
Figure 14 Sample & Hold Circuit
I
01,1
I
I
I
I
I
0: lIB: 1/4: 3/8: 1/2 15/8: 3/4: 718
I
I
I
1
:
::
R/2 R
R
3A/2
S'/8overseale
refmvoltage
VREF(+I
(FS)
NORMALIZED ANALOG INPUT
Figure 17 Definition ADU's Oversea Ie
~HITACHI
222
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - HD46508,HD46508-1 ,HD46508A,HD46508A-1
•
Usage of the PC
output is stored into PeO bit at the end of comarison.
The programmable voltage comparison time is so short
that the interrupt is not requested at this mode. The end of
comparison needs to be conf"mned by reading the 1-+0 transition of the BSY bit in R2.
The ADU has a progranunable threshold voltage comparator (PC) function. The threshold voltage is pre-setable
from OV to SV range with 8 bit resolution. The comparator's
r------~p~-----------------I
to
>--- Reg. R2 -
MPU
from
I
MPU
I
I
I ________________________ _
L
Figure 18 Function Diagram of the PC
~
0
Rq SC
GS
PC
MI
1 03 1
0
R211RQ
R41 B7
I I I
BSY
PCO
B6
B51
84
address
~
021 01 1
DO
OV
I I
OW
C9
C8
B3
B2
Bl
BO
1
PC=Q : AID conversion mode
PQ;=1 . Programmable Voltage
Comparison Mode
pca :
Programmable compardtor
output (1 bit data)
B,-B, : Vp setting byte (upper
byte of 10 bit O/A.
Lower byte IS set to 0)
Figure 19 Registers of the PC Mode
(a) General PC
(c) Check and AID eonv.
(b) Window comparator
Figure 20 PC Application F)ow Chart Examples
~HITACHI
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
223
H D46508,HD46508-1 ,HD46508A,HD46508A-1-----------_ _ _ _ _ _ __
• How to use MI bit
MI bit (RI) functions as follows.
Ml = I: Internal MPX channel is inhibited in order to use
{
attached external MPX channel.
MI =0: Internal MPX channel is enabled.
Ml bit used to select either of External MPX and Internal
MPX. External ~ is connected as follows.
(Bb't AID
conversion)
EXlernal MPX
T
(Addressed at MI=I)
COMMON
(Programmable
Voltage
Comparison)
COMPIN
ADU
[NOTE]
When exlernal MPX
IS
used as Ihe way figure 20.
1 dammy AD converSion or PC at MI=l should be
performed.
Figure 21 How to use External MPX
(d) Voltage Comparison between two channels.
Figure 20 PC Application Flow Chart
Ex~mples
(continued)
• EXAMPLE OF APPLIED CIRCUIT OF THE ADU
RtW
AI.
RtW
CS,
Au
CS.
VMA
AI,
,,
,,
,
,,
,,,
,
,
!
;;@
HD4650B
ADU
HD6BOO
MPU
A.
A,
Alu
+5V
iAQ
Figure 22 Single ADU System
~HITACHI
224
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - H D4650B,HD4650B-1 ,HD4650BA,H D4650BA-1
r---
E
AI.
RfW
AI,
,
Signal
Source
~
-A"
~ CS.
I
I
I
I
Ails
,
HD46508
ADU
RS.
RS,
A.
A,
T
II
0 0 -0,
i.....-
[
A,
AI.-A,
HD6800
MPU
+5Vi
COMMON
nm
I-r-
COMPIN
CLK
t--t-
GAINSEL REF(+)
~REr)1
I
I
I
r--
CLOCK
AI.
E
RIW
AI,
cs,' CS.
I
Signal
Source
I
I
I
I
I
AI ..
Lfft
HD46508
ADU RS.
RS,
A.
~
f=§
REF
0.-0,
r-------..,
i
I
:
PA
:
I
I
l______ J
•
_MO' '""
COMPIN
CLK
iGAINSEL REF(+)
1REr)
I
'SEE
GAIN SEL
USAGE
Figure 23 Multi ADU System
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
225
H D4650S,HD4650S-1 ,H D4650SA,H D4650SA-1 - - - - - - - - - - - - - - - - - - _
• DEFINITIONS OF ACCURACY
Definitions of accuracy applyed to HD46508 are as follows.
(1) Resolution ... The number of output binary digit.
(2) Offset Error ... The difference between actual input volt·
age and ideal input voltage for the fust transition. (when
digital output code is changed from 000 ... 00 to 000 ...
01.)
(3) Full Scale Error ... The difference between actual input
voltage and ideal input voltage for the fmal transition.
(when digital output code is changed from III ... 10 to
Digital Output Code
111 ... 11.)
(4) Quantizing Error ... Error equipped in A/D converter
inherently. Always ±~ LSB is applied.
(5) Non-linearity Error ... The maximum deviation of the
actual transfer line from an ideal straight line. This error
doesn't include Quantizing Error, Offset, or Full Scale
Errors.
(6) Absolute Accuracy ... The deviation of the digital output
code from an analog input voltage. Absolute accuracy includes all of (2), (3), (4), (5).
Digital Output Code
Full Scale Error
Analog
Input
Voltage
4/8 FS
Analog
Input
JL-+-_____________-'-Voltage
Figure 24 Definition of Accuracy
~HITACHI
226
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
H063084---------------01 PP (Document
Image Pre-Processor)
-PRELIMINARY-
The HD63084 (DIPP) is an document image processor used
as a peripheral of a microcomputer. It reads analog image signals
that have been photoelectrically converted by CCD line sensors
or other optical devices, corrects the shading distortion of the
signals, then converts the signals to digital form.
• FEATURES
• High speed reading of image signals
. 5M pixel/sec (at input clock frequency of 10 MHz)
• Highly accurate processing of image signals
Peak level of image signals. 0.1 V - 2.0V
Built·in a·bit peak value detection circuit
Built·in 7·bit successive approximation pixel A/D and
D/A converter
Built·in 4·bit flash·type AID converter
• Various output modes
Binary data output mode
Dithered data output mode (Programmable dithered
pattern of 16 pixel x 16 pixel)
4·bit coded data mode (16 gradations)
• Automatic judgement of horizontal and vertical resolutions
• Interfaceable with either Motorola type or Intel type MPU
• Programmable magnification and reduction rates
Reduction of read image signal
: 0.125 - 1 times (about 1000 gradations)
Magnification of image signal to be recorded
: 1 - a times (about 1000 gradations)
• Implements the following functions on a single chip
(Built·in) sample and hold circuit
(Built·in) shading distortion correction RAM
(Built·in) sensor interface
Parallel to serial conversion of the image signal to be
recorded.
• 2.5 11m CMOS process technology
• Single 5V supply
HD63084P
(DP·64S)
• PIN ARRANGEMENT
RST, @
MAa/MIWR
MAa/lSTN
MA,o/MPRD
, MAn/PDEN/MBE
lNSl ,
Plf[j 3
l'WR' •
4>TG
ClKI
4>"
7 4>'
MADs
9
MADs
1
TRIG
lOUT
MAD4 "
MAD3 1
AVss
ISIN,
, ISIN,
MAD2 1
Voo
1
MADt
1
Vss
1
MADo
1
1 VCL
AVOD
PEAKO
PEAKI
7 VBl
DAo
SLICE,
SLICE,
VT
2 Vss
, lNST/IWIN
T/R SCAN
T/R DACK
8 R/W
37 OS
TMSK,
T/R ClK ,
T/R DATA
T/R ORO 21
RClKI ,
TIMO,
Do
03
7
D.
0,
D.
AS
CS
68/80
- ._ _ _ _ _ _-r-"
Voo
(Top View)
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
227
HD63084----------------------------------------------------------1.1
1.1.1
Absolute Maximum Rating
Internal Digital Circuits
(Voltages referenced to VSS
OV.
Ta
25·C)
No.
Item
Symbol
Value
1
Supply Voltage
VDD
-0.3 to +7.0
V
2
(D~gital Input)
VI
-0.3 to VDD +0.3
V
VIT
-0.3 to VDD +0.3
V
Unit
Input Voltage
Plns
Input Voltage
3
(D~gital
Plns
I/O)
$
228
HITACHI
Hitachi America Ltd.• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63084
1.1.2
Internal Analog Circuits
(Voltages referenced to AVss
OV.
Ta
25°C)
No.
Item
Symbol
Value
1
Supply Voltage
AVnn
-0.3 to +7.0
V
2
Reference
Voltage
V2.5
VCL
VBL
-0.3 to Vnn +0.3
V
Input Voltage
Input)
Pl.ns
VIA
-0. 3 to Vnn+O. 3
V
3
(A~alog
Unit
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
.--~
---------
229
HD63084---------------------------------------------------------------1.1.3
Common Characteristics between Digital and Analog Circuits
No.
Item
Symbol
Value
Unit
1
Operating
Temperature
Topr
o
to +70
°c
2
Storage
temperature
Tstg
-55 to +125
°c
3
Power
Consumption *1
Pc
500
mW
Precaution in Using the DIPP
o
Applying overvoltage more than the maximum rating to the input terminals due
to overshooting or under shooting may cause latch-up, electro-static breakdown, etc.
o
Precaution is needed in noise protection and shield for the analog terminals .
•
230
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue. San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63084
1. 2
Electrical Characteristics
1. 2.1
Internal Digital Circuits
1. 2 .1.1
DC Characteristics
(Vnn=5.0V±5i., VSS=OV, Ta=O to +70°C)
No.
Item
Symbol
Test Condition
min
typ
max
Unit
1
Input High
Voltage
VIH
Vnn =5.25V
2.0
-
VDn
V
2
Input Low
Voltage
VIL
Vnn=4.75V
-0.3
-
0.8
V
3
Output High
Voltage
VOH
VDD =4.75V
IO H=-400lJA
VIH =2.0V
VIL =0.8V
3.0
-
-
V
-
-
0.4
V
4
Output Low
Voltage
VOL
Vnn=4.75V
VIH 2.0V
VIL=0.8V
Other output
pins : Low
IOL =1. 6rnA
5
Input Leakage
Voltage
lIN
Vnn=5.25V
VI =0 to Vnn
-10
*1
-
10
\lA
IOZH
Vnn=5.25V
Vo =VnD
-10
-
10
\lA
6
Three-State
(Off State)
Leakage Current
IOZL
VDn =5.25V
Vo =V SS
-10
-
10
\lA
*1) The minimum leakage current at pin 34 (68/80) is
-lOOIlA because it has an internal pull-up resistor.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
231
HD63084---------------------------------------------------------------1. 2.1. 2
AC Characteristics
(VDD=5.0V±5%, VSS=OV, Ta=O to +70°C)
(1)
Motorola MPU Interface Timing (68000, etc.)
Item
Test
Condition
Symbol
1/0
DS Pulse Width
tWDS6
I
Fig. 1-1
DS to R/W
Setup Time
tSRW6
I
DS to R/W
Hold Time
tHRW6
DS to CS
Setup Time
Applicable
Pin
min
typ
DS
Fig. 1-1
I
tSCS6
DS to CS
Hold Time
max
Unit
450
-
-
ns
R/W
140
-
-
ns
Fig. 1-1
R/W
10
-
-
ns
I
Fig. 1-1
CS
140
-
-
ns
tHCS6
I
Fig. 1-1
CS
10
-
-
ns
DS to RS
Setup Time
tSRS6
I
Fig. 1-1
-RS
140
-
-
ns
DS to ks
Hold Time
tHRS6
I
Fig. 1-1
RS
50
-
-
ns
Read Data Access
Time
tRAC6
0
Fig. 1-1
DO to D7
-
-
320
ns
Read Data Hold
Time
tRH6
0
Fig. 1-1
DO to D7
10
-
-
ns
Write Data Setup
Time
tWS6
I
Fig. 1-1
DO to D7
200
-
-
ns
Write Data Hold
Time
tWH6
I
Fig. 1-1
DO to D7
40
-
-
ns
DS to T/RDACK
Setup Time
tSDK6
I
Fig. 1-2
T/RDACK
(140)
-
-
ns
DS to T/RDACK
Hold Time
tHDK6
I
Fig. 1-2
T/RDACK
(10)
-
-
ns
~HITACHI
232
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
------------------------------HD63084
(2)
Intel MPU Interface Timing (8080, 8086, etc.)
Item
DS (RD) Pulse
Width
R/W (WR) Pulse
Width
RD to CS
Setup Time
Test
Applicable
Condition Pin
min
typ
max
Unit
I
Fig. 1-3
DS
300
-
-
ns
tWRW8
I
Fig. 1-3
R/W
250
-
ns
tSRC8
I
.Fig. 1-3
CS
125
-
-
ns
tHRC8
I
Fig. 1-3
CS
0
-
ns
tSWC8
I
Fig. 1-3
CS
125
tHWC8
I
Fig. 1-3
CS
20
Symbol
I/O
tWDS8
lID to CS
Hold Time
ii!R to CS
Setup Time
WR to CS
Hold Time
RD to RS
Setup Time
RD to RS
Hold Time
tSRR8
I
Fig. 1-3
RS
125
tHRR8
I
Fig. 1-3
RS
50
WR to RS
Setup Time
tSWR8
I
Fig. 1-3
RS
125
70
WR to RS
Hold Time
Read Data Access
Time
tHWR8
I
Fig. 1-3
RS
tRAC8
0
Fig. 1-3
DO to D7
-
-
Read Data Hold
Time
tRH8
0
Fig. 1-3
DO to D7
10
-
Write Data Setup
Time
tWS8
I
Fig. 1-3
DO to D7
180
-
Write Data Hold
Time
tWH8
I
Fig. 1-3
DO to D7
50
-
-
tSDK8
I
Fig. 1-4
T/RDACK
(125)
-
-
ns
tHDK6
I
Fig. 1-4
T7RDACK
(0)
-
ns
tSRK8
I
Fig. 1-4
T7RDACK
(125)
tHRK8
I
Fig. 1-4
T/RDACK
(25)
-
RD to T/RDACK
Setup Time
RD to T/RDACK
Hold Time
WR to T/RDACK
Setup Time
WR to T/RDACK
Hold Time
•
-
-
ns
ns
-
ns
-
ns
-
ns
300
ns
ns
ns
ns
ns
ns
ns
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
233
HD63084---------------------------------------------------------------(3)
MPU Interface Timing (common to Motorola MPU and Intel
MPU)
Symbol
I/O
Test
Condition
Applicable
Pin
min
typ
max
Unit
T/RDRQ Positive
Edge Delay
tDRQH
0
Fig. 1-5
T/RDRQ
-
-
200
ns
T/RDRQ Negative
Edge Delay
tDRQL
0
Fig. 1-5
T/RDRQ
-
-
200
ns
INT Positive
Edge Delay
tINTH
0
Fig. 1-6
INT
-
-
300
ns
T/RSCAN input to
INT Negative
Edge Delay
tINTL
0
Fig. 1-6
INT
-
-
100
ns
DS input to INT
Negative Edge
Delay
tDSIL
0
Fig. 1-1
Fig. 1-3
INT
-
-
(300)
ns
Applicable
Pin
min
typ
max
Unit
100
-
1000
ns
10 6
ns
Item
(4) Clock and Control Input Timing
Item
Symbol
I/O
Test
Condition
CLKI
*2
RCLKI
*2
CLKI Cycle Time
tCYC
I
Fig. 1-7
RCLK Cycle Time
tRCYC
I
Fig. 1-7
TSCAN Pulse Width
tTSW
I
Fig. 1-7
T/RSCA..'11
ex
tCYC
-
-
ns
RSCAN Pulse Width
tRSW
I
Fig. 1-7
T/RSCAN
(~C;C) -
-
ns
RST Pulse Width
tRSTW
I
Fig. 1-7
RS'f
2
(tCYC
-
ns
TRIG Pulse Width
tTRIG
I
Fig. 1-7
TRIG
-
\.IS
200
x) -
(8)
-
*2) Both CLKI and RCLKI input frequencies provide duty cycle of 50% •
•
234
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD63084
(5) Serial Output Timing
Item
Symbol
I/O
Test
Condition
Applicable
Pin
min
typ
max
Unit
CLKI Input to
TMSK Output Delay
tTMDT
0
Fig. 1-8
TMSK
-
-
200
ns
CLKI Input to
TMSK Output Hold
tTMHT
0
Fig. 1-8
TMSK
-
-
200
ns
TDATA Output
Delay
tTDD
0
Fig. 1-8
T/PJ)ATA
-
-
200
ns
TDATA Output
Hold
tTDH
0
Fig. 1-8
T/RDATA
-
-
250
ns
TCLK Positive
Edge Delay
tTCH
0
Fig. 1-8
T/RCLK
-
-
200
ns
TCLK Negative
Edge Delay
tTCL
0
Fig. 1-8
T/RCLK
-
-
200
ns
RCLK Output to
TMSK Output Delay
tTMDR
0
Fig. 1-9
TMSK
-
-
(200)
*3
ns
RCLK Output to
TMSK Output Delay
tTMHR
0
Fig. 1-9
TMSK
RDATA Output
Delay
tRDD
0
Fig. 1-9
T/RDATA
-
-
(200)
*3
(200)
*3
RDATA Output
Hold
tPJ)H
0
Fig. 1-9
T/RDATA
-
-
RCLK Positive
Edge Delay
tRCH
0
Fig. 1-9
T/RCLK
-
-
RCLK Negative
Edge Delay
tRCL
0
Fig. 1-9
T/RCLK
-
-
(200)
*3
(200)
*3
(200)
*3
*3)
ns
ns
ns
ns
ns
Values for reference.
eHITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
235
HD63084-------------------------------------------------------------(6) Application Output and Sensor Interface Timing
Symbol
I/O
Test
Condition
Applicable
Pin
min
typ
max
Unit
TIMO Output
Delay
tTO
0
Fig. 1-10
TUIO
-
-
200
ns
LNST/IWIN Output
Delay
tLN
0
Fig. 1-10
(IWIN)
LNST/IWIN
-
-
250
ns
"TG Output
Positive Edge
Delay
t<&TD
0
Fig. 1-11
"TG
-
-
150
ns
"TG Output
Negative Edge
Delay
t<&TH
0
Fig. 1-11
<&TG
-
-
160
ns
iiI Output Delay
t<&lD
0
Fig. 1-11
iiI
-
-
100
ns
iiI Output Hold
t<&lH
0
Fig. 1-11
,,1
-
-
130
ns
<&R Positive Edge
Delay
t<&RD
0
Fig. 1-13
liR
-
-
100
ns
liR Positive Edge
Hold
t<&RH
0
Fig. 1-13
<&R
-
-
100
ns
min
type
max
Unit
Item
(7) Memory Bus Interface Timing
I/O
Test
Condition
tMASD
0
Fig. 1-14,
-16, -18,
-19, -20,
MAS/MDS
-
-
200
ns
MAS/MDS Negative
Edge Delay
tMASH
0
Fig. 1-14,
-16, -18,
-19, -20,
MAS/MDS
-
-
200
ns
LNSL Output
Delay
tLSD
0
Fig. 1-14,
-8, -19,
LNSL
-
-
200
ns
MA8 to 11 Output
Delay *4
tMAUD
0
Fig. 1-14,
-8, -19,
MA8/MIWR
to MAll/
PDEN/MBE
-
-
200
ns
LRD Negative
Edge Delay
tLRD
0
Fig. 1-14,
-8, -19,
LRD
-
-
200
ns
LRD Positive
Edge Hold
tLRH
0
Fig. 1-14,
-8, -19,
LRD
-
-
200
ns
LWR Negative
Edge Delay
tLWD
0
Fig. 1-14,
-8, -19,
LWR
-
-
200
ns
Item
Symbol
MAS/MDS Positive
Edge Delay
Applicable
Pin
(To be
cont~nued)
*4) Values for reference.
~HITACHI
236
Hitachi Amenca Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------------HD63084
(Continued)
Item
Symbol
I/O
Test
Condition
Applicable
Pin
min
typ
max
Unit
LWR
-
-
200
ns
LWR positive
Edge Hold
t LWH
0
Fig. 1-14
Fig. 1-19
MAD 0 to 7 Delay
tMADD
0
Fig. 1-14
etc.
MADO-7
-
-
200
ns
MADO to 7 Hold
tMADH
0
Fig. 1-14
etc.
MADO-7
-
-
200
ns
MADO to 7
Setup Time
tRDS
I
Fig. 1-14
MADO-8
50
-
-
ns
MADO to 7
Hold Time
tRDH
I
Fig. 1-14
MADO-7
50
-
-
ns
MBE Negative
Edge Delay
tMBEL
0
Fig. 1-15
MBE
-
-
200
ns
T/RDACK Input to
MAS Negative Edge
Delay
tBASL
0
Fig. 1-17
MAS/MDS
-
-
200
ns
T/RDACK Input to
MAS Positive Edge
Delay
tBASH
0
Fig. 1-17
MAS/MDS
-
-
200
ns
T/RDACK Input to
T/RDRQ Negative
Edge Delay
tBTDR
0
Fig. 1-17
T/RDRQ
-
-
400
ns
MLNST positive
Edge Delay
tMLNH
0
Fig. 1-16
Fig. 1-17
Fig. 1-18
MA9/LNSTN
-
-
250
ns
MLNST Negative
Edge Delay
tMLNL
0
Fig. 1-16
Fig. 1-17
Fig. 1-18
MA9/LNSTN
-
-
300
ns
PRD Negative
Edge Delay
tPRD
0
Fig. 1-16
Fig. 1-19
PRD
-
-
200
ns
PRD positive
Edge Hold
tpRH
0
Fig. 1-16
Fig. 1-19
PRD
-
-
200
ns
PWR Negative
Edge Delay
tpWD
0
Fig. 1-18
Fig. 1-20
PWR
-
-
200
ns
tpWH
0
Fig. 1-18
Fig. 1-20
PWR
-
-
200
ns
tMIWL
0
Fig. 1-16 MA8/MIWR
-
-
400
ns
t M1WH
0
Fig. 1-16
MA8/MIWR
-
-
200
ns
tMPRL
0
Fig. 1-18
MAlO/MPRD
-
-
250
ns
MPRD Positive
Edge Delay
tMPRH
0
Fig. 1-18
MAlO/MPRD
-
-
250
ns
PDEN Negative
Edge Delay
tpDEL
0
Fig. 1-18
MAll/PDEN
/MBE
-
-
200
ns
PWR Positive
Edge Hold
MIWR Negative
Edge Delay
MIWR
Edge
MPRD
Edge
positive
Delay
Negative
Delay
-
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
237
HD63o84------------------------------------------------------------------(Note 1)
Bus Timing Test Loads
Other output and I/O pins
(excluding analog pins)
DO to D7 pins
Test point
Test point
Output
pin
~~~~K
Output D---,.....K
pin
[Notes) 1. CL includes stray capacitance caused by the probe and load
capacitance.
2. Diodes are 152074
(Note 2)
®
or equivalents.
I/O Signal Test Points
1,.---------. - - - - - - - - - - - - - - - --- 3. OV
2.0V
2.0V
Input
Output
~~--------------OV
0.4V
2.4V
~HITACHI
238
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD63084
DS(2)
tSRW6
R/W
INT
Note) r/RDACK input must be fixed high.
Fig. 1-1
Motorola MPU Access Timing
DS (<1>2)
R/W
~
T/RDACK
------«
INPUT
__---Jr
>--
~------«
OUTPUT
Note) CS input must be fixed high.
Fig. 1-2
DMA Operation Timing (Using Motorola MPU)
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
239
HD63084-------------------------------------------------------------I---twnss_
\
DS (RD)
-
I---tWRWS-
\
-
f-f-tSRCS
-I-- I-tHRCS
V
\
)~
~
tRAcs-
tSWCS
--
tSWRS
f-- tHWRS
>-
-
f-tRHS
tWSSf-----
... INPUT
OUTPUT
f-----
IF
S
\
-f-f- tHRRS
- f - f- tSRRS
f-
C
r-tWHS
Ir-----
tDSIL
\
iNT
Note) T/RDACK
Fig. 1-3
~nput
must be fixed
h~gh.
Intel MPU Access Timing
DS(RD)
R/W(WR)
tSDKS
T/RDACK
--------«
OUTPUT
>~-------~(
Note)
Fig. 1-4
INPUT ) - - - -
CS input must be fixed high.
DMA Operation Timing (Using Intel MPU)
~HITACHI
240
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
______________________________________________________________ HD63084
CLKI
/RCLK
T/RDRQ
T/RDACK -------------------------1r--------~
Fig. 1-5
T/RDRQ Output Timing
CLKI
INT
T/RSCAN ____________________________-.J
Fig. 1-6
INT Output Timing
~HITACHI
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
241
HD63084----------------------------------------------------------------
CLK!
RCLK
J
tCYC
J
t RCYC
,..
T/RSCAN~
RST
--{
Fig. 1-7
\
\
~i~~
1
L
1
L
.,
\
tRSTW
1
CLKI, RCLK, T/RSCAN, RST and TRIG Input Timing
~HITACHI
242
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63084
CLKI
TMSK
TDATA
TCLK
Fig. 1-8
Serial Output Timing (in Read (T) Mode)
RCLKI
TMSK
TDATA
RCLK
Fig. 1-9
Serial Output Timing ( in Receive (R) Mode)
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
243
HD63084-------------------------------------------------------------eLKI
TIMO
LNST/IWIN
Fig. 1-10
Application Output Timing
eLK I
¢TG
¢l
Note) The SMOO, SMOI and SMD2 bits in the R09 register
must be 0,0 and 0 or 0,0 and 1 respectively.
Fig. 1-11
cpTG and
cp1 Output Timing
(1)
eLKI
¢TG
¢l
Note) The SMOO, SMOI and SM02 bits must be 0,1 and
o or 0,1 and 1 respectively.
Fig. 1-12
cpTG and
cp1 Output Timing
(2)
eLKI
¢l
Fig. 1-13
cp1
and cpR Output Timing
~HITACHI
244
Hitachi America Ltd . • 2210 O'Toole Avenue • San
Jose, CA 95131
• (408) 435·8300
I
~
(')
::.
~
3
!!1
o·
eLKI
II>
~
IMA[I/MDS
N
N
0
0
~.
~J:
::>
~
(f)e')
c:
'"
~
c...
0
J:
LNSL
MA8-10
tLRH
~
LRD
I
I
\'--_ _- - - ' r - - - - - - - - -
en
~
0
~
(()
Ul
LWR
.
0
~
I
tRDH
~
~
MADO-7
DATA INPUT
DATA INPUT
\
DATA OUTPUT
....
'"
'"'"
Ul
0
0
MAll/
PDEN/ IMBEI
I
o
0>
(.)
I\.)
o
.j>.
-
0"1
Fig. 1-14
Memory Bus Interface Timing in A Mode (1) During Image Data Processing
:r:
oOl
i')
Ol
"""
~
CLKI
~
PI
"»
3
~
c;-
III
r
!i
IMASJ/MDS
N
LNSL
N
o
H or L
o
•
.,Q.~~
~:::t
MAS-IO
~ ~
LRD
000
LWR
:>
~
<-
~
If'
-
t
'{------~
- -------r(
:::t
MADO-7
11
()
If
~;~O~TPUT
X
ADR.OUTPUT
c=(
»
1!l
~
T/RURQ
,
~
T7RDACK
~
MAH/PDEN/IMBEI
'~
~L _ _~
'~
tMBEL
.!'!!
x=jl~ADQ!R[.oQiU!lTfjPU!lTji~----
cia
8
Fig. 1-15
Memory Bus Interface Timing in A Mode (2)
During Burst DMA Transfer
I
~
(')
:!
eLKI
»
3
&
c.>
MAIOI I MPRUI
MAlll I PDENI IMBE
0
0
Fig. 1-16
I\)
.j>.
......
Memory Bus Interface Timing in B Mode (1)
During 4-bit Coded Data Output
I
o
m
c.>
o
CD
.j>.
~
f\.)
"'"
(Xl
CLKI
~
~tMLNL
-+
tMLNH
~
:!:
- L-
0
MA9/1LNSTNI
»
3
~
.,c;
-
r
---i
LRD
a
-.
J
MAS I I MDsl
'"'"0
.r
-H=.tMASD
fi
joe-
-4
JtBASL rt1l
tBASH
tLRD
\
~
J
I
LWR
I
PRD
I
PWR
I
oi
*~
~:I
_
~ ~
(flO
~ :I
'-0
MADO-7
HIZ
I
51>
()
»
I
MAS I I MIWRI
'"'
(]1
~
~
,
MAlO/1 MPRDI -
~
0
~
..,.
Co>
(]1
'"
Co>
0
0
0
~
~
I
:::l
::c
MAll I
I PDEN liMBE
T/RDRQ
-
...j. >-
tDRQH
.:t
r-
T/RDACK
Fig. 1-17
'B'~~
Memory Bus Interface Timing in B Mode (2),
During Burst DMA Transfer
-
::t
S
eLK I ~ ~~ ~J-:r=--J\-.}. ~ ~~w:
tMLNH
"2:
>
3
-+NL
CD
:::!.
0
MA9/iLNSTNf
I»
~
MAS !I MDS
N
I
T
tMASD-
.
..
..
-t-- H-tMASH
T
T
I
~
0
~.
~%
LWR
%
<0
!:D
()
>
eo
~
~
~
~
PRD
PWR
MADO-7
tpWD
-K=
tMADD
~
-~ .
DATA OUTPUT
~
DATA OUTPUT
/I
J
MAIO/IMPRDI
q
'T
1--+MADH
DATA OUTPUT
l--
tMIWH
-j
MAB/IMIWRI
--
tMADH \
I
..
..
tMPRH
I
~
'"g
tMADD
1--
tPWH
- f - t - tMIWL
~
to
~
R
rn()
.,
~
-
~ ~
~
J
LRD
0
::l
~
tpDEL
I
MAll/lpDEMI/MBE
~
T
- + tMPRL
.1.
'"
-"
.1.
::J:
~
CO
Fig. 1-18
Memory Bus Inte1"face Timing in B Mode (3)
During Pel Correction Data Detection
om
~
~
I
oC1l
I'V
(J'1
o
~
~
:I:
eLKI
So
:!:
»
3
~
15
IMASI/MDS
'c:"
a.
LNSL
I\)
I\)
MA8-11
0
0
~
~~
LRD
'" ~
cnO
LWR
~J:
:::l
c
!!l
'-0
-'()'""
J:
PRD
PWR
»
to
'"~
MADO-7
OUTPUT
~
0
$
~
'"'"
'"'"
0
0
Fig. 1-19
Memory Bus Interface Timing in C or D Mode (1)
During Image Data Processing
::J:
iii'
0
;<.
»
CLKI
JV'~ J\.J\...t\F\.f J
LNSTN
-f,\
\JU.JV'~\..J\..r\JJ\JI...r
3
~
0"
I»
~
tMASDN
N
oi.
iMASi/MDS
0
a
Q.
CD
~J:
~
c:
CD
~
"0
'"
.!D
0
»
W
o
(l)
....
HD63084------------------------------__________________________________
1.2.1.3
Capacitance
Item
*
Input
Capac i tance
CIN
Output
Capacitance
COUT
Input/Output
Capac itance
Cin/out
Test Condition
f
= 100kHz
min
typ
max
Unit
-
-
12.5
pF
-
-
12.5
pF
-
-
12.5
pF
These parameters are sample values.
1.2.2
Internal Analog Circuits
1.2.2.1
Item
Input
Current
Input
Voltage
Range
Output
Current
Supply
Current
252
Symbol
DC Characteristics
De tai led Item
Symbol
Test
Condition
min
typ
max
Unit
VBL
LBL
VBL=3.5V
-
-
1.0
rnA
ISIN1,2
VISIl ,2
1.5
-
3.5
-
3.0
PEAKI
VINP
1.5
SLICEl
VINSl
1.5
SLICE2
VINS2
1.5
VBL
VIBL
VCL
VICL
0.3 x
VDD
0.3 x
VDD
lOUT
1010
-16.0
-
PEAKO
IO PK
-5.0
-
-0.7
DAO
10DO
-6.0
-
-0.7
Standby
IDS
-
Operating
IDD
-
CLKI=lOMHz
3.5
V
3.5
0.7 x
VDD
0.7 x
VDD
-4.0
rnA
1
60
(to be cont~nued)
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63084
(continued)
Item
Detailed Item
Output
Voltage
Resistance
VPO
Chain
Step 0
PEAKO
Resistance
Vp255
Chain
Step 255
Resistance
VDO
Chain
DAO Step 0
Resistance
VD1 27
Chain
Step 127
VIOUT
lOUT
Input
Leakage
Current
1. 2.2.2
Symbol
ISINl
ILISl
ISIN2
I LIS 2
PEAKI
ILPI
SLICE 1
I LSLI
SLICE2
I LSL 2
VCL
ILVCL
Test
Condition
min
typ
max
3.20
-
3.40
1. 25
-
1. 65
1.40
-
1.60
2.60
-
3.00
VISINl =
2.5V
2.40
-
2.65
VIN =
VDD
-10
-
10
VCL=V BL
=3.4V
PEAK I =
1.5V
o to
Unit
V
IlA
AC Characteristics
Item
Detailed Item
Symbol
Test
Condition
min
typ
max
Unit
Input
Voltage
Range
Peak to Peak
Voltage
VIP
fCLK=lOMHz
0.1
-
2.0
V
Image Signal
Operating Reading
Frequency Frequency
VIF
VBL =3.4V
VSLICE
0.5
-
5.0
MHz
= 1.8V
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
253
-----,
N
....
(11
I
0
0')
(0)
0
....0>
'"
....'"'l
I
~
~
"»"3
,..,
0
,::
::;
l\)
(PIN NO.)
hj
l\)
I
1/,7\
(51)
Um
VCL
I I
:==~~------------~~~=>r---------------------r-----~~~~~J
['eak ,","oJ
~
'"'l
!:
?-
R19 (7) MODE
MPUAE
J:
~
00(')
'"~
0
(")
0
c:
Z
'i
po
H
''""
....c+a
::;
()
»
to
(11
~
~
0
I--'
a
Otl
a
"I !
255
'"
D:l-fferenc:e
data
ROt (5)
'"0
MODE
Sensor
output
Sensor
~
(")
WCOM
0
c:
) (17)
(15)
127
(13)
"I
MAD7 (8)
I DO(24)
1
a
~
D7 (31)
J
(52)
I--'
'1:1
lout
'i
a
ro
ro
(55)
AVSS PEAKI
(54)
(48)
CD
....::;
OQ
VCL
VBL
VH
/-
to
aQ
Area of digitization
by 4-bit AID
f-
VL
PEAKO
(49)
VpEAK
'=
AGND---------------------
(l
(1)
Ul
Ul
I--'
A
B
C
D
Binary,Dither"d
1I~" .. rJ/.Dtth .. nd
Blnary,Dnt,,'red
(Binary coding for edge emphasis)
SLICE2 (Dithered coding or 4-bit coding for edge emphasis)
--t>=8:>-Q--
i>;"
'd
H
0
0
po
output B
P
III
I-'
t:>:I
ROO 0, 2)
I.
0
0
MADO
0
1
2
....
C/1
Q
(11
_
Otl
~
'"cD
'"
~
:Po
P
~
~
III
"o J: S"
po
0
DMODEl
C
"::;....,a
CD
p
~3/1a
Inltial
po
I--'
....
Q. •
ol~
~
rt
[7 bit AID/A]
::;
0
CD
....0
LOAD
Q
0
~
-VBL-l0amV
....ac+
I\)
I\)
CD
(l
I>
[}etection
III
"c:
"p
Unity Gain AMP
Analog Comparator
Analog Switch
(l
?;'
I
----------------------------------------------------------------HD63084
r
1. 2
Relation between Horizontal Resolution Conversion Ratio ({3) and Parameters
Table 1-1
B
m
.125
.15
.16
.18
.2
.22
.25
.28
.3
.32
7
6
6
5
4
4
3
3
3
3
.j)
L.
.375
.4
.44
.45
.5
.52
.55
.56
.6
.6129
.625
.65
.68
.7
.7073
.72
.75
.76
.78
.8
.8163
.8167
.825
.84
.86
.866
.8661
.875
.9
.925
.95
.975
1.0
1.024
1.03
1.062
1.081
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
4
4
4
5
5
5
6
7
7
7
7
8
8
8
8
8
8
8
8
8
k
1
3
4
9
1
Relation between Horizontal Resolution Conversion Ratio ({3) and
Parameters (1)
9'I' '0 ' HRCM
1
2
1
5
1
11
6
1
1
7
4
3
1
8
1
7
6
2
3
2
1
11
3
9
2
1
0
12
1
9
2
11
3
2
1
12
7
3
2
7
6
8
1
3
1
12
5
7
4
1
1
6
1
11
6
1
1
9
4
11
5
7
5
4
1
2
11
13
6
15
7
1
1
5
1
5
2
5
3
5
4
1
1
16 13
13
9
15
8
5
2
0
1
3
4
0
5
0
3
2
7
1
1
1
8
7
1
11
7
8
1
5
1
1
7
2
7
3
0
5
5
0
5
6
2
3
9
7
8
0
4
3
2
1
0
3
4
7
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A3+B5
A3+A4, B4+B5
B4+A4
B4->-A4
A3->-B4, A4->-B5
A3->-B4, A4+B5
B
m
k
1.1
1.12
1.15
1.1548
1.16
1.18
1.2
1. 2264
1.2273
1.24
1.26
1.28
1.3
1.32
1. 35
1. 375
1.4
1. 4138
1. 4167
1.44
1.45
1.48
1.5
1.52
1.55
1.56
1.6
1.6316
1. 6363
1. 65
1. 6667
1. 6875
1.7
1.7222
1. 75
1.7692
1.8
1.8235
1.8421
1. 8667
1. 8824
1.9
1. 9231
1. 9412
2.0
2.0625
2.0833
2.1
8
8
7
7
7
6
5
5
5
5
4
4
4
4
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
11
7
3
13
4
9
1
12
5
6
14
7
3
8
7
3
2
12
5
11
9
12
1
13
11
14
3
12
7
13
2
11
7
13
3
10
4
14
16
13
15
9
12
16
1
16
12
10
9'I' '0' HRCM
3
1
2
6
1
5
1
5
2
1
11
4
1
1
6
2
1
5
2
3
2
1
1
12
9
11
2
7
4
7
1
5
3
5
1
3
1
3
3
2
2
1
1
1
0
1
1
1
8
6
1
7
3
4
0
7
3
5
3
3
2
7
1
1
1
7
3
8
7
11
0
1
2
3
1
5
3
6
1
6
4
8
2
7
3
11
13
11
13
8
11
15
1
15
11
9
0
0
0
0
0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
B5+A4, B4+A3
A4->-B4
A4->-B4
A4->-A3-> B5->-B4
A4+A3, B5+B4
B5->-A3
B5+A3
@HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
255
HD63084--------------------------------------------------------___________
Table 1-1
Relation between Horizontal Resolution Conversion Ratio
Parameters (2)
9-
S
m
k
2.125
2.1429
2.1667
2.1875
2.2143
2.25
2.2727
2.3
2.3333
2.3637
2.3846
2.4167
2.4449
2.4667
2.5
2.5385
2.5625
2.6154
2.6364
2.6667
2.6923
2.7143
2.7333
2.7692
2.7857
2.8125
2.8333
2.8571
2.875
2.9
2.9167
2.9333
3.0
3.0625
3.0833
3.1111
3.125
3.1429
3.1667
3.1875
3.2143
3.2308
3.2667
3.2857
3.3077
3.33
3.3636
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
8
7
6
16
14
4
11
10
3
11
13
12
9
15
2
13
16
13
11
3
13
7
15
13
14
16
6
7
8
10
12
15
1
16
12
9
8
7
6
16
14
l3
15
7
13
3
11
'1'
1
1
1
3
3
1
3
3
1
4
5
5
4
7
1
7
9
8
7
2
9
5
11
10
11
13
5
6
7
9
11
14
1
1
1
1
1
1
1
3
3
3
4
2
4
1
4
'0 '
7
6
5
13
11
3
8
7
2
7
8
7
5
8
1
6
7
5
4
1
4
2
4
3
3
3
1
1
1
1
1
1
0
15
11
8
7
6
5
13
11
10
11
5
9
2
7
HRCM
S
m
k
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3.3846
3.4167
3.4375
3.4545
3.5
3.5333
3.5556
3.5714
3.6
3.625
3.6667
3.6923
3.7
3.7277
3.75
3.7778
3.8
3.8572
3.8889
3.9091
3.9231
3.9375
4.0
4.0625
4.0833
4.1
4.125
4.1429
4.1667
4.1818
4.2
4.2222
4.25
4.2667
4.2857
4.3077
4.3334
4.3572
4.3946
4.4167
4.4375
4.4545
4.5
4.5333
4.5556
4.5833
4.625
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
13
12
16
11
2
15
9
7
5
8
3
13
10
11
4
9
5
7
9
11
13
16
1
16
12
10
8
7
6
11
5
9
4
15
7
13
3
14
l3
12
16
11
2
15
9
12
8
9-
'1'
5
5
7
5
1
8
5
4
3
5
2
9
7
8
3
7
4
6
8
10
12
15
1
1
1
1
1
1
1
2
1
2
1
4
2
4
1
5
5
5
7
5
1
8
5
7
5
'0'
8
7
9
6
1
7
4
3
2
3
1
4
3
3
1
2
1
1
1
1
1
1
0
15
11
9
7
6
5
9
4
7
3
11
5
9
2
9
8
7
9
6
1
7
4
5
3
un and
HRCM
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
~HITACHI
256
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63084
Table 1-1
m
S
4.6429 4
4.6666 4
4.6875 4
4.7143 4
4.7333 4
4.75
4
4.7779 4
4.8
4
4.8333 4
4.8572 4
4.875
4
4.9
4
4.9167 4
4.9333 4
5.0
4
5.0625 5
5.0833 5
5.1
5
5.125
5
5.1429 5
5.1667 5
5.1875 5
5.2143 5
5.2308 5
5.2667 5
5.2857 5
5.3077 5
5.333
5
5.3636 5
5.3846 5
5.4167 5
5.4375 5
5.4546 5
5.5
5
5.5385 5
5.5556 5
5.5714 5
5.6
5
5.625
5
5.6429 5
5.6667 5
5.6923 5
5.7143 5
5.7333 5
5.7692 5
5.7857 ~
5.8182 5
5.8461 5
k
14
3
16
7
15
4
9
5
6
7
8
10
12
15
1
16
12
10
8
7
6
16
14
13
15
7
13
3
11
13
12
16
11
2
13
9
7
5
8
14
3
13
7
15
13
14
11
13
Relation between Horizontal Resolution Conversion Ratio ((3) and
Parameters (3)
9-
'I' '0
9
5
2
1
11
5
2
5
11
4
3
1
7
2
4
1
5
1
6
1
7
1
9
1
11
1
14 1
1
0
1 15
1 11
1
9
1
7
1
6
1
5
3 13
3 11
3 10
4 11
2
5
4
9
1
2
7
4
5
8
5
7
7
9
5
6
1
1
7
6
5
4
4
3
2
3
5
3
9
5
2
1
9
4
2
5
11
4
10
3
11
3
2
9
11
2
HRCM
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S
5.867
5.8889
5.9091
5.9231
5.9375
6.0
6.0625
6.0667
6.0833
6.1
6.125
6.1428
6.1667
6.1818
6.2
6.2222
6.25
6.2727
6.3
6.3333
6.3636
6.3846
6.4167
6.4375
6.4615
6.5
6.5334
6.5556
6.5833
6.6154
6.6364
6.6667
6.6923
6.7143
6.75
6.7778
6.8
6.8334
6.8572
6.8889
6.909
6.9286
6.9375
7.0
7.0625
7.0833
7.1
7.125
m
k
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
15
9
11
13
16
1
16
15
12
10
8
7
6
11
5
9
4
13
10
3
11
13
12
16
13
2
15
9
12
13
11
3
13
7
4
9
5
6
7
9
11
14
16
1
16
12
10
8
9-
'I' '0 '
2
13
8
1
10
1
12
1
1
15
1
0
1 15
1 14
1 11
1
9
1
7
1
6
1
5
2
9
1
4
2
7
1
3
3 10
7
3
2
1
4
7
5
8
5
7
7
9
6
7
1
1
7
8
5
4
7
5
8
5
7
4
2
1
9
4
2
5
3
1
7
2
4
1
5
1
6
1
8
1
10
1
13
1
15
1
1
0
1 15
1 11
1
9
1
7
1L1\CH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
257
HD63084------------------------------------------------------------------Relation between Horizontal Resolution Conversion Ratio ({3) and
Parameters (4)
Table 1-1
S
m
k
7.1429
7.1667
7.1875
7.2143
7.25
7.2727
7.3
7.3333
7.375
7.4
7.4286
7.4445
7.4615
7.5
7.5385
7.5625
7.5833
7.6154
7.6364
7.6666
7.6923
7.7143
7.7334
7.7692
7.8
7.8333
7.8571
7.875
7.9
7.9231
7.9336
8.0
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
16
14
4
11
10
3
8
5
7
9
13
2
13
16
12
13
11
3
13
7
15
13
5
6
7
8
10
13
15
1
Q,
'1 ' '0'
1
6
1
5
3 13
3 11
1
3
8
3
7
3
1
2
3
5
2
3
3
4
4
5
6
7
1
1
7
6
7
9
7
5
8
5
7
4
2
1
4
9
2
5
11
4
10
3
4
1
5
1
6
1
7
1
1
9
12
1
1
14
1
0
HRCM
S
m
k
Q,
'1 '
'0'
HRCM
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
$HITACHI
258
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
HD63085---------------DICEP(Document Image Compression and
Expansion Processor)
- PRELIMINARVThe HD63085 (DICEP) is a LSI that compresses (or encodes)
and expands (or decodes) the digital data representing a docu·
ment image. The DICEP uses Modified Huffman (MH) coding
scheme, Modified Relative Element Address Designate (MR)
coding scheme and Modified MR (M'R) coding scheme which
are compatible with the CCITT (Comite Consultatif Interna·
tional Telegraphique et TeJephonique) recommendations for
Group 3 and Group 4 facsimile apparatus.
As the DICEP stores coding and decoding algorithms in the
microprogram ROM as firmare, a single MPU command allows
this LSI to encode or decode a scan line of digital data.
This LSI is suitable for Group 3 and Group 4 facsimile appa·
ratus, file serves, intelligent copies, terminals, word processors,
laser beam printers and other office automation systems.
HD63085Y·B
(PC·72)
•
•
•
•
•
•
•
•
•
•
FEATURES
Various coding schemes ..... MH, MR, M'R and Run
length cod i ng
Compatible with the CCITT recommendation for Group 3
and Group 4 facsimile apparatus
Interfaceable with either Motorola type MPU or Intel type
MPU
DMA capability through the document image bus
4M Byte/sec (at input clock frequency of 32 MHz)
A variety of programmable parameters
The length of a scan line: 0 - 65535 bits
The number of RTC or EOl code words: 0 - 65535
Programmable starting address
Coding and decoding of a desired part of a document
Selectable document image bus size
Document image bus : 8 bits or 16 bits
System bus
: B bits
64K Bytes of document image memory is available inde·
pendently of the MPU
2 !.1m CMOS process technology
Single 5V supply
• PIN ARRANGEMENT
® @) @@
@
@@
@
@@
®@®@®®@ @@
@
@ @ @
(0 ®
@ @
@ @
@@
@@
@®
@@
e®
®
@
@
@
@
@@
@@@ @®@®@®@
e
@@
@®
® ®000000000
.
Pm No
MA/MDo
MAlMO,
MAfM0 4
MAlMO.
MAlMO,
MA/MO,o
MAlMO ..
MA/MD'4
v.
TESTO
"
13
TOATA
VOS
fiii
""
"
"
"
"
32
33
"
"
"
"'"
NO
RESET
v"
D.
D,
D.
D.
V"
READY
MAS
MAlM01
MAlMD3
MAlMO!)
16
v.
MA/MD7
MAlMD9
iOR
MAlM011
"
DTC
"
"
SET
MA/MD13
RtW
AG'
DS
DACKI
iiAcK
MAlM015
"
v.
45
TEST1
.."
IDs
MOEN
.
50
"
"
Funo::tlOn
v.
"""
;ow
DACKO
DRaTl
NC
as
57
ORQTO
BROT
68
"
"
"
"
"
"
"
!ROT
V"
D,
D,
D.
D,
V"
He
M.i.EN
NC
"72
~HITACHI
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
259
HD63085---------------------------------------------------------------1.1
Absolute Maximum Rating
Nc
Item
Symbol
1
Supply Voltage
VDD
2
Input Voltage
Vin
3
Operating
Temperature
Topr
0 to +70
°C
4
Storage
Temperature
Tstg
-55 to +150
°C
*
Value
Unit
*
-0.3 to +7.0
V
*
-0.3 to +7.0
V
Voltages referenced to Vss=OV.
No
Item
Symbol
1
Supply Voltage
VDD
*
ViL
ViH
2
-
typ
max
Unit
4.75
5
5.25
V
*
-0.3
-
0.8
V
*
2.2
-
VDD
V
25
70
°C
min
Input Voltage
3
4
*
Operating
Temperature
Topr
0
Voltages referenced to Vss=OV.
@HITACHI
260
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
-------------------------------------------------------------------HD63085
1.2
DC Characteristics
VDD=5.0V±5%, Vss=OV, Ta=O to +70°C )
min
typ
max
Unit
VIH
2.2
-
VDD
V
Input Low
Voltage
VIL
-0.3
-
0.8
V
3
Input Leakage
Voltage
IIN
Vin=O to
5.25V
-10
-
10
pA
4
Three-State
(Off State)
Leakage Current
Vin=O to
5.25V
-10
-
10
pA
Itsi
5
Output High
Voltage
VOH
IOH=-400pA
2.4
-
-
V
6
Output Low
Voltage
VOL
IOL= 2mA
-
-
0.4
V
7
Standby Current
IDDS
-
-
1
rnA
8
Power
Dissipation
150
-
mW
typ
max
Unit
8
pF
10
pF
12
pF
Ne
Item
Symbol
1
Input High
Voltage
2
Test Condition
PD
ItErl«;..----
DS
tAS
VIL
R/W
AO-A2
DO-D7
(SYSTEM BUS
VIH
-+
VIL
DICEP)
tDHR
DO-D7
(DICBP
-+
SYSTEM BUS)
_ _ _ _ _ _
tIRQ1
VOL~
IRQT
Fig. 1-2
System Bus Read/Write Timing
(68 Type MPU)
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
267
HD63085----------------------------------------------------------------
tAR
AO-A2
~------tRW------~
DS
DO-D7
(DICEP -+ SYSTEM BUS)
"~T=:L
IRQT
VOL
Fig. 1-3
System Bus Read Timing
(80 Type MPU)
AO-A2
1o------tWW-------.l
R/W
tWD
DO-D7
VIR
~V~IL=------_!_II
(SYSTEM BUS -+ DICEP)
Fig. 1-4
System Bus Write Timing
(80 Type MPU)
•
268
tDW
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------------HD63085
tCYCE
tE:*--
PWEH --~
DS
R/W
I
~
DO-D7
(SYSTEM
VIH
BUS~
DICEP)
VIL
tDHR
VOH
DO-D7
(DICEP...., SYSTEM BUS)
VOL
HITACHI
Hitachi Amenca Ltd
• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
287
HD68230---------------------------------------------------------------• Counter Preload Register H,M,L (CPRH-L)
Counter Preload Register H,M,L (CPRH-L)
7
6
5
4
3
2
1
0
BIt
Bit
Bit
BIt
Bit
BIt
Bit
Bit
23
22
21
20
19
18
17
16
Bit
Bit
BIt
BIt
BIt
Bit
Bit
Bit
15
14
13
12
11
10
9
8
BIt
Bit
Bit
Bit
Bit
BIt
BIt
Bit
7
6
5
4
3
2
1
0
CPRH
CPRM
CPRl
The Counter Preload Registers (CPRH-L) are a group of three
8-bit registers used for storing data to be transferred to the
counter. Each of the registers is individually addressable, or the
group may be accessed with the MOVEP. L or the MOVEP, W
instructions. The address one less than the address of CPRH is
the null register, and is reserved so that zeros are read in the
upper 8 bits of the destination data register when a MOVEP.L is
used. Data written to this address is ignored.
The registers are readable and writeable at all times. A read
cycle proceeds independently of any transfer to the counter,
which may be occuring simultaneously_
To insure proper operation of the PI/T Timer, a value of
$000000 may not be stored in the Counter Preload Registers
for use with the counter.
The RESET pin does not affect the contents of these registers.
• Count Register H,M,L (CNTRH-L)
Count Register H,M,L (CNTRH-L)
7
6
5
4
3
2
1
0
Bit
Bit
BIt
Bit
BIt
Bit
BIt
BIt
23
22
21
20
19
18
17
16
BIt
Bit
BIt
Bit
BIt
BIt
BIt
BIt
15
14
13
12
11
10
9
8
Bit
BIt
Bit
BIt
BIt
BIt
Bit
Bit
7
6
5
4
3
2
1
0
CNTRH
The count registers (CNTRH-L) are a group of three 8-bit
addresses at which the counter can be read. The contents of the
counter are not latched during a read bus cycle; thus, the data
read at these addresses is not guaranteed if the timer is in the
run state. (Bits 2, 1 , and 0 of the Timer Control Register specify
the state.) Write operations to these addresses result in a normal
bus cycle but the data is ignored.
Each of the registers is indiVidually addressable, or the
group may be accessed with the MOVEP.L or the MOVEP.W
instructions. The address one less than the address of CNTRH is
the null register, and is reserved so that zeros are read in the
upper 8 bits of the destination data register when a MOVEP.L
is used. Data written to this address is ignored .
• Timer Status Register (TSR)
Timer Status Register (TSR)
I I I I I I I Iz:s I
7
6
5
4
3
2
1
The Timer Status Register (TSR) contains one bit from
which the zero detect status can be determined. The ZDS
status bit (bit 0) is an edge-sensitive flip-flop that is set to 1
when the 24-bit counter decrements from $000001 to $000000.
The ZDS status bit is cleared to 0 following the direct clear
operation (similar to that of the ports), or when the timer is
halted. Note also that when the RESET pin is asserted the
timer is disabled, and thus enters the halt state.
This register is always readable without consequence. A
write access performs a direct clear operation if bit 0 in the
written data is 1. Following that, the ZDS bit is O.
This register is constructed with a reset dominant S-R flipflop so that all cleaning conditions prevail over the possible
zero detect condition.
Bits 7-1 are unused and are read as O.
CNTRM
CNTRl
~HITACHI
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Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD68230
•
PORT CONTROL STRUCTURE
The primary focus of most applications will be on Ports A
and B, the handshake pins, the port interrupt pins, and the
DMA request pin. They are controlled in the following way:
the Port General Control Register contains a 2-bit field that
specifies a set of four operation modes. These govern the
overall operation of the ports and determine their interrela-
tionships. Some modes require additional information from
each port's control register to further define its operation.
In each port control register, there is a 2-bit submode field
that serves this purpose. Each port mode/submode combination
specifies a set of programmable characteristics that fully define
the behavior of that port and two of the handshake pins.
This structure is summarized in Table 4 and Figure 8.
Mode 0 Submode 01
Mode 0 Submode 00
Mode 0 Submode 1 X
A (B)
B
DoublewBuffered
Output
Mode 1 Port B Submode XO
HI
(H3)
H2
(H4)
B.tl/O
1"""1---- HI (H3)
1"""1--____ H2 (H4)
Mode 1 Port B Submode XI
I"""I----Hl
1"""1--__0- H2
A and B
Aand B
(16)
(16)
Double-Buffered
Output
I"""1----H3
I"""1--_....-H4
Mode 3
Mode 2
~AandB
Y-V
WA(S)
(16)
Bit I/O
W
Bidirectional 16 Bit
v
HI
H2
B (8)
H3
Bidirectional 8-Bit
HI
H2
>----
L----f----i_H4
>->--
Output
Transfers
Input
Transfers
Output
Transfers
H3 >--Input
L--1'-_._H4
Transfers
Figure 8
Port Mode Layout
~HITACHI
Hitachi Amerrca Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
289
HD68230------------------------------------------------------------------•
PORT GENERAL INFORMATION AND CONVENTIONS
The following paragraphs introduce concepts that are generally applicable to the PIfT ports independent of the chosen
mode and submode. For this reason, no particular port or
handshake pins are mentioned; the notation HI (H3) indicates
that, depending on the chosen mode and sub-mode, the statement given may be true for either the HI or H3 handshake pin.
•
Unidirectidnal vs Bidirectional
Figure 8 shows the configuration of Ports A and B and each
of the handshake pins in each port mode and submode. In
Modes 0 and 1, a data direction register is associated with each
of the ports. These registers contain one bit for each port pin
to determine whether that pin is an input or an output. Modes
o and 1 are, thus, called unidirectional modes because each pin
assumes a constant direction, changeable only by a reset condition or a programming change. These modes allow doublebuffered data transfers in one direction. This direction, determined by the mode and submode definition, is known as
the primary direction. Data transfers in the primary direction
are controlled by the handshake pins. Data transfers not in
the primary direction are generally unrelated, and single or
unbuffered data paths exist.
In Modes 2 and 3 there is no concept of primary direction
as in Modes 0 and 1. Except for Port A in Mode 2 (Bit I/O),
the data direction registers have no effect. These modes are
bidirectional, in that the direction of each transfer (always 8
or 16 bits, double-buffered) is determined dynamically by the
state of the handshake pins. Thus, for example, data may be
transferred out of the ports, followed very shortly by a transfer
into the same port pins. Transfers to and from the ports are
independent and may occur in any sequence. Since the in-
stantaneous direction is always determined by the external
system, a small amount of arbitration logic may be required.
•
Control of Double-Buffered Data Paths
Generally speaking, the PIfT is a double-buffered device.
In the primary direction, double-buffering allows orderly transfers by using the handshake pins in any of several programmable
protocols. (When Bit I/O is used, double-buffering is not
available and the handshake pins are used as outputs or statusf
interrupt inputs.)
Use of double-buffering is most beneficial in situations
where a peripheral device and the computer system are capable
of transferring data at roughly the same speed. Double-buffering
allows the fetch operation of the data transmitter to be overlapped with the store operation of the data receiver. Thus,
throughput measured in bytes or words-per-second may be
greatly enhanced. If there is a large mismatch in transfer
capability between the computer and the peripheral, little or
no benefit is obtained. In these cases there is no penalty in
using double-buffering.
•
Double-Buffered Input Transfers
In all modes, the PIfT supports double-buffered input
transfers. Data that meets the port setup and hold times is
latched on the asserted edge of Hl(H3). Hl(H3) is edge-sensitive, and may assume any duty-cycle as long as both high and
low minimum times are observed. The PIfT contains a Port
Status Register whose HIS(Ir3S) status bit is set anytime any
input data is present in the double-buffered latches that has
not been read by the bus master. The action of H2(H4) is
programmable; it may indicate whether there is room for more
data in the PIfT latches or it may serve other purposes. The
Table 4 Port Mode Control Summary
Mode 0
(UmdlrectlOnal 8-Blt model
PortA
Submode 00
Mode 1
Mode 2
(UmdlrectlonaI16-Blt
model
(Bidirectional 8·Blt model
Mode 3
(Bidirectional 16'81t mode)
Port A - Double-Buffered Data (Most
51 mflcant
Port A - Bit I/O (With no handshaking
Pins)
Port A - Double-Suffered Data (Most
Submode XX (not used)
Hl - Status/Interrupt generating
Input
H2 - StatUS/interrupt generating
Input or general-purpose
output
Submode XX (not used)
Submode XX (not used)
Port B - Double-Buffered Data
(Leastslgmflcant)
Port B - Bidirectional B-81t Data
(Double-Buffered)
Port B - Double-Buffered Data
(Leastslgmflcant)
Submode XX (not used)
Hl - mdlcates output data received
by peTipheral
H2 - Operation With H1 m the
mterlocked or pulsed output
handshake protocols
H3 - latches Input data
H4 - Operation With H3 m the
Interlocked or pulsed Input
handshake protocols
Submode XX (not used)
Hl - Indicates outpUt data received
by peTipheral
H2 - Operation With Hl m the
mterlocked or pulsed output
handshake protocols
H3 - latches mput date
H4 - Operation With H3 In the
Interlocked or pulsed mput
handshake protocols
SI mflcant)
Double-Buffered Input
H 1 - Latches Input data
H2 - Status/mterrupt generating
Input, general-purpose output,
or operation With Hl In the
Interlocked or pulsed mput
handshake protocols
Submode 01 - Double-Buffered
Output
Hl - Indicates data received by
peripheral
H2 - Status/Interrupt generating
Input, general-purpose output,
or operation With H 1 In the
Interlocked or poised output
handshake protocols
Submode 1 X - Bit I/O
H1 - Status/interrupt generating
mput
H2 - Status/Interrupt generating
Input or general.purpose
output
Port B
H3 and H4 - Identical to Port A,
Hl and H2
Submode XO - Umdlrectlonal 16·
Sit Input
H3 - Latches mput data
H4 - Status/interrupt generatmg
Input, general-purpose out·
put, or operation With H3
m the mterlocked or pulsed
Input handshake protocols
Submode Xl - Unidirectional 16-81t
Outpu1
H3 - Indicates data received by
peripheral
H4 - Status/Interrupt generatHlg
Input, general-purpose output.
or operation With H3 In the
Interlocked or pulsed output
handshake protocols
~HITACHI
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Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------------------HD68230
following options are available, depending on the mode.
(1) H2(H4) may be an edge-sensitive input that is independent
of Hl(H3) and the transfer of port data. On the asserted
edge of H2(H4), the H2S(H4S) status bit is set. It is
cleared by the direct method (refer to Direct Method of
Resetting Status), the RESET pin being asserted, or when
the Hl2 Enable (H34 Enable) bit of the Port General
Control Register is O.
(2) H2(H4) may be a general purpose output pin that is
always negated. The H2S(H4S) status bit is always O.
(3) H2(H4) may be a general purpose output pin that is always
asserted. The H2S(H4S) status bit is always O.
(4) H2(H4) may be an output pin in the interlocked input
handshake protocol. It is asserted when the port input
latches are ready to accept new data. It is negated
asynchronously follOWing the asserted edge of the Hl(H3)
input.
As soon as the input latches become ready, H2(H4) is
again asserted. When the input double-buffered latches are
full, H2(H4) remains negated until data is removed. Thus,
anytime the H2(H4) output is asserted, new input data
may be entered by asserting Hl(H3). At other times transi-
tions on Hl(H3) are ignored. The H2S(H4S) status bit is
always O. When Hl2 Enable (H34 Enable) is 0, H2(H4)
is held negated.
(5) H2(H4) may be an output pin in the pulsed input handshake proto~ol. It is asserted exactly as in the interlocked
input protocol, but never remains asserted longer than
4 clock cycles. Typically, a four clock cycle pulse is
generated. But in the case that a subsequent HI(H3)
asserted edge occurs before termination of the pulse,
H2(H4) is negated asynchronously. Thus, anytime after
the leading edge of the H2(H4) pulse, new data may be
entered in the PI/T double-buffered input latches. The
H2S(H4S) status bit is always O. When Hl2 Enable (H34
Enable) is 0, H2(H4) is held negated.
A sample timing diagram is shown in Figure 9. The H2(H4)
interlocked and pulsed input handshake protocols are shown.
The DMAREQ pin is also shown assuming it is enabled. All
handshake pin sense bits are assumed to be 0 (refer to Port
General Control Register); thus, the pins are in the low state
when asserted. Due to the great similarity between modes, this
timing diagram is applicable to all double-buffered input transfers.
Read
Read
Port Data
Hl(H3)
H2(H4) Interlocked
H2(H4) Pulse
Figure 9 Double-buffered Input Transfers
•
Double-Buffered Output Transfers
The PI/T supports double-buffered output transfers in all
modes. Data, written by the bus master to the PI/T, is stored
in the port's output latch. The peripheral accepts the data by
asserting Hl(H3), which causes the next data to be moved to
the port's output latch as soon as it is available. The function
of H2(H4) is programmable; it may indicate whether new data
has been moved to the output latch or it may serve other
purposes. The HlS(H3S) status bit may be programmed for
two interpretations. Normally the status bit is a I when there is
at least one latch in the double-buffered data path that can
accept new data. After writing one byte/word of data to the
ports, an interrupt service routine could check this bit to
determine if it could store another byte/word; thus, filling
both latches. When the bus master is fmished, it is often useful
to be able to check whether all of the data has been transferred
to the peripheral. The HlS(H3S) Status Control bit of the
Port A and B Control Registers provide this flexibility. The
programmable options of the H2(H4) pin are given below,
depending on the mode.
(1) H2(H4) may be an edge-sensitive input pin independent
of Hl(H3) and the transfer of port data. On the asserted
edge of H2(H4), the H2S(H4S) status bit is set. It is reset
by the direct method (refer to Direct Method of Resetting
(2)
(3)
(4)
(5)
Status), the ltIlSET pin being asserted, or when the Hl2
Enable (H34 Enable) bit of the Port General Control
Register is O.
H2(H4) may be a general-purpose output pin that is always
negated. The H2S(H4S) status bit is always O.
H2(H4) may be a general-purpose output pin that is always
asserted. The H2S(H4S) status bit is always O.
H2(H4) may be an output pin in the interlocked output
handshake protocol. H2(H4) is asserted two clock cycles
after data is transferred to the double-buffered output
latches. The data remains stable and H2(H4) remains asserted until the next asserted edge of the Hl(H3) input. At that
time, H2(H4) is asynchronously negated. As soon as the
next data is available, it is transferred to the output latches.
When H2(H4) is negated, asserted transitions on HI(H3)
have no effect on the data paths. As is explained later,
however, in Modes 2 and 3 they do control the threestate output buffers of the bidirectional port(s). The
H2S(H4S) status bit is always O. When Hl2 Enable (H34
Enable) is 0, H2(H4) is held negated.
H2(H4) may be an output pin in the pulsed output handshake protocol. It is asserted exactly as in the interlocked
output protocol above, but never remains asserted longer
than four clock cycles. Typically, a four clock pulse is
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
291
HD68230---------------------------------------------------------------generated. But in the case that a subsequent HI(H3)
asserted edge occurs before tennination of the pulse,
H2(H4) is negated asynchronously shortening the pulse.
The H2S(H4S) status bit is always O. When HI2 Enable
(H34 Enable) is 0 H2(H4) is held negated.
Write
Port Data
A sample timing diagram is shown in Figure 10. The H2(H4)
interlocked and pulsed output handshake protocols are shown.
The DMAREQ pin is also shown assuming it is enabled. All
handshake pin sense bits are assumed to be 0; thus, the pins
are in the low state when asserted. Due to the great similarity
between modes, this timing diagram is applicable to all double·
buffered output transfer.
Write
~~~------r----~~-----------~
H2(H41 Interlocked
---j-----"
H2(H41 Pulse
H1(H31
Figure 10 Double·buffered Output Transfers
• Requesting Bus Master Service
The PI/T has several means of indicating a need for service
by a bus master. First, the processor may poll the Port Status
Register. It contains a status bit for each handshake pin,
plus a level bit that always reflects the instantaneous state of
that handshake pin. A status bit is I when the PI/T needs
serviCing, i.e., generally when the bus master needs to read
or write data to the ports, or when a handshake pin used as a
simple status input has been asserted. The interpretation of
these bits is dependent on the chosen mode and submode.
Second, the PI/T may be placed in the processor's interrupt
structure. As mentioned previously, the PI/T contains Port A
and B Control Registers that configure the handshake pins.
Other bits in these registers enable an interrupt associated with
each handshake pin. This interrupt is made available through
the PC5/PIRQ pin, if the PIRQ function is selected. Three
additional conditions are required for PIRQ to be asserted:
(I) the handshake pin status bit set, (2) the corresponding
interrupt (service request) enable bit is set, (3) and DMA requests are not associated with that data transfer (HI and H3
only). The conditions from each of the four handshake pins
and corresponding status bits are ORed to detennine PIRQ.
The third method of requesting service is via the PC4/
f5MA'IrnO pin. This pin can be associated with double-buffered
transfers in each mode. If it is used as a DMA controller request, it can initiate requests to keep the PI/T's input/output
double-buffering empty/full as much as possible. It will not
overrun the DMA controller. The pin is compatible with the
HD68450 Direct Memory Access Controller (DMAC).
• Vectored, Prioritized Port Interrupts
Use of HD68000-compatible vectored interrupts with the
PI/T requires the PIRQ and PlACK pins. When PlACK is asserted, the PI/T places an 8-bit vector on the data pins Do -D7 .
Under normal conditions, this vector corresponds to highest
priority, enabled, active port interrupt source with which the
f5MAlrnO pin is not curremly associated. The most-significant
six bits are provided by the Port Interrupt Vector Register
(PNR), with the lower two bits supplied by prioritization
logic according to conditions present when PlACK is asserted.
It is important to note that the only affect on the PI/T caused
by interrupt acknowledge cycles is that the vector is placed
on the data bus. Specifically, no registers, data, status, or other
internal states of the PI/T are affected by the cycle.
Several conditions may be present when the PlACK input
is asserted to the PI/T. These conditions affect the PI/T's
response and the tennination of the bus cycle. If the PI/T
has no interrupt function selected, or is not asserting 'PIRQ,
the PI/T will make no response to PI'Acr{ (~ will not be
asserted). If the PI/T is asserting PIRQ when'P'iA(;f{ is received,
the PI/T will output the contents of the Port Interrupt Vector
Register and the prioritization bits. If the PIVR has not been
initialized, SOF will be read from this register. These conditions
are summarized in Table 5.
Table 6 Response to Port Interrupt Acknowledge
PI RQ negated OR interrupt
request function not selected
PI RQ asserted
PIVR has not been initialized
since RESET
No response from P liT.
No DTACK.
PI/T provides $OF, the
Uninitialized Vector.'
PIVR has been initialized
since RESET
No response from PI/T.
NoDTACK.
PI/T provides PI V R contents
with prioritization bits.
Conditions
. . The uninitialized vector is the value returned from an interrupt vector register before it has been initialized.
~HITACHI
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--------------------------------------------------------------HD68230
The vector table entries for the PI/T appear as a contiguous
block of four vector numbers whose common upper six bits
are programmed in the PIVR. The following table pairs each
interrupt source with the 2-bit value provided by the prioriza·
tion logic, when interrupt acknowledge is asserted.
HI
H2
H3
H4
source
source
source
source
00
01
10
II
• Autovectored Port Interrupts
Autovectored interrupts use only the PIRQ pin. The opera·
tion of the PI/T with vectored and autovectored interrupts is
identical except that no vectors are supplied and the PC6/
PlACK pin can be used as a Port C pin.
•
Direct Method of Resetting Status
In certain modes one or more handshake pins can be used
as edge·sensitive inputs for sole purpose of setting bits in the
Port Status Register. These bits consist of simple flip·flops.
They are set (to I) by the occurrence of the asserted edge of
the handshake pin input. Resetting a handshake status bit can
be done by writing an 8-bit mask to the Port Status Register.
This is called the direct method of resetting. To reset a status
bit that is resettable by the direct method, the mask must
contain a I in the bit position of the Port Status Register cor·
responding to the desired bit. Other positions must contain
O's. For status bits that are not resettable by the direct method
in the chosen mode, the data written to the port status register
has no effect. For status bits that are resettable by the direct
method in the chosen mode, a 0 in the mask has no effect.
• Handshake Pin Sense Control
The PIjT contains exclusive·OR gates to control the sense of
each of the handshake pins, whether used as inputs or outputs.
Four bits in the Port General Control Register may be program·
med to determine whether the pins are asserted in the low or
high voltage state. As with other control registers, these bits
are reset to 0 when the RESET pin is asserted, defaulting the
asserted level to be low.
• Enabling Ports A and B
Certain functions involved with double·buffered data trans·
fers, the handshake pins, and the status bits, may be disabled by
the external system or by the programmer during initialization.
The Port General Control Register contains two bits, HI2 Ena·
ble and H34 Enable, which control these functions. These bits
are cleared to the 0 state when the RESET pin is asserted, and
the functions are disabled. The functions are the following.
(1) Independent of other actions by the bus master or peri·
pheral (via the handshake pins), the PI/T's disabled hand·
shake controller is held to the "empty" state, i.e., no data
is present in the double·buffered data path.
(2) When any handshake pin is used to set a simple status
flip·flop, unrelated to double·buffered transfers, these
flip·flops are held reset to O. (See Table 4.)
(3) When H2(H4) is used in an interlocked or pulsed hand·
shake with Hl(H3), H2(H4) is held negated, regardless
of the chosen mode, submode, and primary direction.
Thus, for double·buffered input transfers, the programmer
may signal a peripheral when the PI/T is ready to begin
transfers by setting the associated handshake enable bit
to 1.
• The Port A and B Alternate Registers
In addition to the Port A and B Data Registers, the PI/T
contains Port A and B Alternate Registers. These registers are
read·only, and simply proVide the instantaneous level of each
port pin. They have no effect on the operation of the hand·
shake pins, double·buffered transfers, status bits, or any other
aspect of the PI/T, and they are mode/submode independent.
•
PORT MODES
This section contains information that distinguishes the
various port modes and submodes.
• Mode 0 - Unidirectional B-Bit Mode
In Mode 0, Ports A and B operate independently. Each
may be configured in any of its three possible submodes:
Submode 00 - Double·Buffered Input
Submode 01 - Double·Buffered Output
Submode IX - Bit I/O
Handshake pins HI and H2 are associated with Port A and
configured by programming the Port A Control Register.
(The HI2 Enable bit of the Port General Control Register,
enables Port A transfers.) Handshake pins H3 and H4 are
associated with Port B and configured by programming the
Port B Control Register. (The H34 Enable bit of the Port
General Control Register enables Port B transfers.) The Port
A and B Data Direction Registers operate in all three sub·
modes. Along with the submode, they affect the data read
and written at the associated data register according to Table
6. They also enable the output buffer associated with each
port pin. The DMAREQ pin may be associated with either
(not both) Port A or Port B, but does not function if the Bit
I/O submode is programmed for the chosen port.
~HITACHI
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293
HD68230-----------------------------------------------------------Table 6 Mode 0 Port Data Paths
Read Port A/B
Data Register
Mode
o Submode
o Submode
o Submode
Write Port A/B
Data Register
DDR=O
DDR = 1
00
FIL. D.B.
FOL Note 3
FOL. S.B.
Note 1
01
Pin
FOL Note 3
10LlFOL. D.B.
Note 2
IX
Pin
FOL Note 3
FOL. S.B.
Note 1
Abbreviations:
10L - Initial Output Latch
Final Output Latch
FOL FIL - Final Input Latch
Note 1:
Note 2:
Note 3:
DDR = X
S.B. - Single Buffered
D.B. - Double Buffered
DDR - Data Direction Register
Data is latched in the output data registers (final output latch) and will be single buffered at the pin if the DDR
is 1. The output buffers will be turned off if the DD R is O.
Data is latched in the double-buffered output data registers. The data in the final output latch will appear on
the port pin if the DDR is a 1.
The output drivers that connect the final output latch to the pins are turned on.
(1) Port A or B Submode 00 (8-Bit Double-Buffered Input)
__
AIBI
8
Double-Buffered
Output
Hl
(H3)
H2
(H4)
Figure 12 Mode 0 Submode 01
Figure 11 Mode 0 Submode 00
In Mode 0, double-buffered input transfers of up to 8-bits are
available by programming Submode 00 in the desired port's
control register. The operation of H2 and H4 may be selected
by programming the Port A and Port B Control Registers,
respectively. All five double-buffered input handshake options,
previously mentioned in the Port General Information and
Conventions section, are available.
For pins used as outputs, the data path consists of single
latch driving the output buffer. Data written to the port's
data register does not affect the operation of any handshake
pin, status bit, or any other aspect of the PI/T. Output pins
may be used independently of the input transfer. However,
read bus cycles to the data register do remove data from the
port. Therefore, care should be taken to avoid processor instructions that perform unwanted read cycles.
Refer to PARALLEL PORTS Double-Buffered Input
Transfers for a sample timing diagram. (Figure 9)
(2) Port A or B Submode 01 (8·Bit Double-Buffered Output)
In Mode 0, double-buffered output transfers of up to 8 bits
are available by programming submode 01 in the desired port's
control register. The operation of H2 and H4 may be selected
by programming the Port A and Port B Control Registers,
respectively. All five double-buffered output handshake op-
tions, previously mentioned in the Port General Information
and Conventions section, are available.
For pins used as inputs, data written to the associated data
register is double-buffered and passed to the initial or final
output latch, as usual, but the output buffer is disabled.
Refer to PARALLEL PORTS Double-Buffered Output
Transfers for a sample timing diagram (Figure 10)
(3) Port A or B Submode 1 X (Bit I/O)
¢)A~B)
Bit I/O
t---
Hl (H3)
H2 (H4)
Figure 13 Mode 0 Submode 1 X
In Mode 0, simple Bit I/O is available by programming Submode IX in the desired port's control register. This submode
is intended for applications in which several independent
devices must be controlled or monitored. Data written to the
@HITACHI
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Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
HD68230
Handshake pins H3 and H4, configured by programming the
Port B Control Register, are associated with the 16-bit doublebuffered transfer. These 16-bit transfers, are enabled by the
H34 Enable bit of the Port General Control Register. Handshake pins HI and H2 may be used as simple status inputs
not related to the 16-bit data transfer or H2 may be an output.
Enabling of the H I and H2 handshake pins is done by the H12
Enable bit of the Port General Control Register. The Port A
and B Data Direction Registers operate in each sub-mode.
Along with the submode, they affect the data read and written
at the data register according to Table 7. They also enable the
output buffer associated with each port pin. The DMAREQ
pin may be associated only with H3.
Mode I can provide convenient, high-speed 16-bit transfers.
The Port A and B data registers are addressed for compatibility
with the HD68000 Move Peripheral (MOVEP) instruction and
with the HD68450 DMAC. To take advantage of this, Port A
should contain the most-significant byte of data and always be
read or written by the bus master first. The interlocked and
pulsed handshake protocols are keyed to accesses to the Port B
Data Register in Mode I. If it is accessed last, the 16-bit doublebuffered transfers proceed smoothly.
associated data register is single-buffered. If the data direction register bit for that pin is a I (output), the output buffer
is enabled. If It is 0 (input), data written is still latched, but is
not available at the pin. Data read from the data register is
the instantaneous value of the pin or what was written to the
data register, depending on the contents of the data direction register. HI(H3) is an edge-sensitive status input pin
only and it controls no data-related function. The HIS(H3S)
status bit is set following the asserted edge of the input waveform. It is reset by the direct method, the RESET pin being
asserted, or when the HI2 Enable (H34 Enable) bit is O.
H2(H4) can be programmed as a simple status input (identical to HI(H3)), or as an asserted or negated output. The
interlocked or pulsed handshake configurations are not available.
• Mode 1 - Unidirectional 16-Bit Mode
In Mode I, Ports A and B are concatenated to form a single
16-bit port. The Port B Submode field controls the configuration of both ports. The possible submodes are:
Port B Submode XO - Double-Buffered Input
Port B Submode XI - Double-Buffered Output
Table 7 Mode 1 Port Data Paths
Read Port AlB
Register
Mode
DDR = 0
1, Port B
1, Port B
Note 3:
DDR =0
i;>DR = 1
FOL, S.B.
FOL
FOL, S.B.
Note 3
Note 2
Note 2
FOL
IOLlFOL.
IOLlFOL.
Pin
Submode Xl
Note 2:
DDR = 1
FIL. D.B.
Submode XO
Note 1:
Write Port AlB
Register
Note 3
D.B.,
D.B.,
Note 1
Note 1
Data written to Port A goes to a temporary latch. When the Port B data register is later written, Port A data is
transferred to IOLlFOL.
Data is latched in the output data registers (final output latch) and will be single buffered at the pin if the DDR
is 1. The output buffers will be turned off if the DDR is O.
The output drivers that connect the final output latch to the pins are turned on.
Abbreviations:
IOL I nitial Output Latch
FOL Final Output Latch
FIL Final Input Latch
S.B. D.B. DDR -
Single Buffered
Double Buffered
Data Direction Register
(1) Port B Sub mode XO (16-Bit Double-Buffered Input)
In Mode I Port B Submode XO, double-buffered input transfers
of up to 16 bits may be obtained. The level of all 16 pins is
asynchronously latched with the asserted edge of H3. The
processor may check H3S status bit to determine if new data
is present. The DMAREQ pin may be used to signal a DMA
controller to empty the input buffers. Regardless of the bus
master, Port A data should be read first. (Actually, Port A
data need not be read at all.) Port B data should be read last.
The operation of the internal handshake controller, the H3S
bit, and DMAREQ are keyed to the reading of the Port B
data register. (The HD68450 DMAC can be programmed to
perform the exact transfers needed for compatibility with the
PI/T.) H4 may be programmed for all five of the handshake
options mentioned in the Port General Information and Conventions section.
For pins used as outputs, the data path consists of a single
latch driving the output buffer. Data written to the port's
data register does not affect the operation of any handshake
pin, status bit, or any other aspect of the PI/T. Thus, output
pins may be used independently of the input transfer.
However, read bus cycles to the Port B Data Register do remove
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
295
HD68230----------------------------------------------------------------data, so care should be taken to avoid unwanted read cycles.
For pins used as inputs, data written to either data register
is double-buffered and passed to the initial or fmal output
latch, as usual, but the output buffer is disabled.
Refer to PARALLEL PORTS Double-Buffered Input/Output Transfer for a sample timing diagram (Figure 10).
• Mode 2 - Bidirectional 8-Bit Mode
WA(S)
WB(8)
Bit 1/0
Figure 14 Mode 1 Port B Submode XO
(2) Port B Submode Xl (16·Bit Double-Buffered Output)
Bi-directional 8 Bit
i----Hl
H1
....~-tI~ H2
H2
___
Output
>-- Transfers
H3>-- Input
AandB
L-...r-......-H4
Transfers
(16)
Double-Buffered
Output
Figure 16 Mode 2
....~--H3
....f---tl~ H4
Figure 15 Mode 1 Port B Submode Xl
Refer to PARALLEL PORTS Double-Buffered Input Transfers for a sample timing diagram (Figure 9).
In Mode I Port B Submode XI, double-buffered output transfers of up to 16 bits may be obtained. Data is written by
the bus master (processor or DMA controller) in two bytes.
The first byte (most-significant) is written to the Port A Data
Register. It is stored in a temporary latch until the next byte
is written to the Port B Data Register. Then all 16 bits are
transferred to the fmal output latches of Ports A and B. Both
options for interpretation of the H3S status bit, mentioned in
Port General Information and Comments section, are available
and apply to the 16-bit port as a whole. The DMAREQ pin may
be used to signal a DMA controller to transfer another word to
the port output latches. (The HD68450 DMAC can be programmed to perform the exact transfers needed for compatibility
with the PI/T.) H4 may be programmed for all five of the
handshake options mentioned in Port General Information and
Comments section.
In Mode 2, Port A is used for simple bit I/O with no associated handshake pins. Port B is used for bidirectional 8-bit doublebuffered transfers. HI and H2, enabled by the HI2 Enable bit
in the Port General Control Register, control output transfers,
while H3 and H4, enabled by the Port General Control Register
bit H34 Enable, control input transfers. The instantaneous
direction of the data is determined by the HI handshake pin.
The Port B Data Direction Register is not used. The Port A
and Port B submode fields do not affect PI/T operation in
Mode 2.
(1) Double-Buffered 110 (Port B)
The only aspect of bidirectional double-buffered transfers
that differs from the uni-directional modes lies in controlling
the Port B output buffers. They are controlled by the level of
HI. When HI is negated, the Port B output buffers (all 8) are
enabled and the pins drive the bidirectional bus. Generally, HI
is negated in response to an asserted H2, which indicates that
new output data is present in the double-buffered latches.
Following acceptance of the data, the peripheral asserts HI,
disabling the Port B output buffers. Other than controlling the
output buffer, HI is edge-sensitive as in other modes. Input
transfers proceed identically to the double-buffered input
protocol described in the Port General Information and Conventions Section. In Mode 2, only the interlocked and pulsed
Table 8 Mode 2 Port B Data Paths
Mode
Read Port B
Data Register
Write Port B
Data Register
2
FIL,D.B.
10LlFOL, D.B.
Abbreviations:
IOL FOL -
Initial Output Latch
Final Output Latch
D.B.
FIL
-
Double Buffered
Final Input Latch
~HITACHI
296
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD68230
monitored. Data written to the Port A data register is singlebuffered. If the Port A Data Direction Register bit for that
pin is I (output), the output buffer is enabled. If it is 0, data
written is still latched but not available at the pin. Data read
from the data register is either the instantaneous value of the
pin or what was written to the data register, depending on the
contents of the Port A Data Direction Register. This is summarized in Table 9.
handshake pin options are available on H2 and H4. The
DMAREQ pin may be associated with either input transfers
(H3) or output transfers (HI), but not both. Refer to Table 8
for a summary of the Port B Data Register responses in Mode 2.
(2) Bit I/O (Port A)
Mode 2, Port A performs simple bit I/O with no associated
handshake pins. This configuration is intended for applications
in which several independent devices must be controlled or
Table 9 Mode 2 Port A Data Paths
Read Port A
Data Register
Mode
Write Port A
Data Register
DDR=O
DDR = 1
DDR =0
DDR = 1
Pin
FOL
FOL
FOL, S.B.
2
Abbreviations:
S.B. FOL -
Single Buffered
Final Output Latch
DDR
• Mode 3 - Bidirectional 16- Bit Double
Buffered I/O
~AandB
'\r-V
(16)
Bi·directional 16·Bit
Hl
Output
H2 >--- Transfers
H3>--- Input
L--J--_... H4
Transfers
Figure 17 Mode 3
In Mode 3, Ports A and B are used for bidirectional 16-bit
double-buffered .transfers. HI and H2 control output transfers, while H3 and H4 control input transfers. (HI and H2 are
enabled by the HI2 Enable bit while H3 and H4 are enabled by
the H34 Enable bit of the Port General Control Register.) The
instantaneous direction of the data is determined by the HI
handshake pin, and thus, the data direction registers are not
used. The Port A and Port B submode fields do not affect
PIIT operation in Mode 3.
The only aspect of bidirectional double-buffered transfers
that differs from the unidirectional modes lies in controlling
the Port A and B output buffers. They are controlled by the
level of HI. When HI is negated, the output buffers (all 16)
are enabled and the pins drive the bidirectional bus. Generally, HI is negated in r~sponse to an asserted H2, which indicates
-
Data Direction Register
that new output data is present in the double-buffered latches.
Following acceptance of the data, the peripheral asserts HI,
disabling the output buffers. Other than controlling the output
buffers, HI is edge-sensitive as in other modes. Input transfers
proceed identically to the double·buffered input protocol
described in the Port General Information and Conventions
section. Port A and B data is latched with the asserted edge of
H3. In Mode 3, only the interlocked and pulsed handshake
pin options are available to H2 and H4. The DMAREQ pin
may be associated with either input transfers (H3) or output
transfers (HI), but not both. H2 indicates when new data is
available in the Port B (and impliCitly Port A) output latches,
but unless the buffer is enabled by HI, the data is not driving
the pins.
Mode 3 can provide convenient high-speed 16-bit transfers.
The Port A and B Data Registers are addressed for compatibility with the HD68000's Move Peripheral (MOYEP) instruction and with the HD68450 DMAC. To take advantage of this,
Port A should contain the most-significant data and always be
read or written by the bus master first. The interlocked and
pulsed handshake protocols are keyed to accesses to the Port B
Data Register in Mode 3. If it is accessed last, the 16-bit doublebuffered transfer proceed smoothly. Refer to Table 10 for a
summary of the Port A and B data paths in Mode 3.
•
DMA REQUEST OPERATION
The Direct Memory Access Request (DMAREQ) pulse can
be associated with output or input transfers to keep the initial
and final output latches full or initial and final input latches
empty respectively. Figure 18 and 19 show all the possible
paths in generating DMA requests.
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
297
HD68230-------------------------------------------------------------Table 10 Mode 3 Port A and B Data Paths
Mode
Read Port A and B
Data Register
Write Port A and B
Data Register
3
FIL,D.B.
IOLlFOL. D.B., Note 1
Data written to Port A 90es to a temporary latch. When the Port B data register is later written. Port A data is
transferred to IOLlFOL.
Note 1:
Abbreviations:
IOL
FOL
FIL
-
S.B.
D.B.
Initial Output Latch
Final Output Latch
Final Input Latch
-
-
Data in Output Latches
Data in Input Latches
~~~
Bus Write
~
OMA~
~
...
No DMA Request
Bus Write
~~
Peripheral Provides Data
~
Peripheral Accepts Data
•
~
OMA>GV../
DMAREQ Associated with Output Transfers
TIMER
The HD68230 timer can provide several facilities needed
by HD68000 operating systems. It can generate periodic interrupts, a square wave, or a single interrupt after a programmed
time period. Also, it can be used for elapsed time measurement
or as a device watchdog. This section describes the programmable options available, capabilities, and restrictions that apply
to the timer.
The PI/T timer contains a 24-bit synchronous down counter
that is loaded from three 8·bit Counter Preload Registers.
The 24·bit counter may be clocked by the output of a 5-bit
(divide-by-32) prescaler or by an external timer input TIN. If
the prescaler is used, it may be clocked by the system clock
(CLK pin) or by the TIN external input. The counter signals
the occurrence of an event primarily through zero detection.
(A zero is when the counter of the 24-bit timer is equal to
zero.) This sets the zero defect status (ZOS) bit in the Timer
Status Register. It may be checked by the processor or may be
used to generate a timer interrupt. The ZOS bit is reset by
writing a 1 to the Timer Status Register in that bit position.
The general operation of the timer is flexible and easily
programmable. The timer is fully confIgured and controlled
by programming the 8·bit Timer Control Register. It controls:
(1) the choice between the Port C operation and the timer
Figure 19
DMAREQ Associated with Input Transfers
operation of three timer pins,
(2) whether the counter is loaded from the Counter Preload
Register or rolls over when zero detect is reach,
(3) the clock input,
(4) whether the prescaler is used, and
(5) whether the timer is enabled.
• RUN/HALT Definition I
The overall operation of the timer is described in terms of
the run or halt states. The control of the current state is determined by programming the Timer Control Register. When
in the halt state, all of the following occur.
(1) The prior contents of the counter is not altered and is
reliably readable via the Count Registers.
(2) The prescaler is forced to $1 F whether or not it is used.
(3) The ZOS status bit is forced to 0, regardless of the possible
zero contents of the 24-bit counter.
The run state is characterized by:
(1) The counter is clocked by the source programmed in
the Timer Control Register.
(2) The counter is not reliably readable.
(3) The prescaler is allowed to decrement if programmed for
use.
(4) The ZOS status bit is set when the 24-bit counter transitions from $000001 to $000000.
~HITACHI
298
,
DMA Request
~
No DMA Request
"--~../
Figure 18
No DMA Request
~
om
DMA Request
No DMA Request
Single Buffered
Double Buffered
Hitachi America ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------------------HD68230
• Timer Rules
This section provides a set of rules that allow easy application of the timer.
•
TIMER APPLICATIONS SUMMARY
This section outlines programming of the Timer Control
Register for several typical examples.
(1) When the RESET pin is asserted, all bits of the Timer
Control Register go to 0, configuring the dual function
pins as Port C inputs.
(2) The contents of the Counter Preload Registers and counter
are not affected by the RESET pin.
(3) The Count Registers provide a direct read data path from
each portion of the 24-bit counter, but data written to
their addresses is ignored. (This results in a normal bus
cycle.) These registers are readable at any time, but their
contents are never latched. Unreliable data may be read
when the timer is in the run state.
(4) The Counter Preload Registers are readable and writable
at any time and this occurs independently of any timer
operation. No protection mechanisms are provided against
iII-timed writes.
(5) The input frequency to the 24-bit counter from the TIN
pin or prescaler output, must be between 0 and the input frequency at CLK pin divided by 32 regardless of the
configuration chosen.
(6) For configurations in which the prescaler is used (with the
CLK pin or TIN pin as an input), the contents of the
Counter Preload Register (CPR) is transferted to the
counter the first time that the prescaler passes from $00 to
$1 F (rolls over) after entering the run state. Thereafter,
the counter decrements or is loaded from the Counter
Preload Register when the prescaler rolls over.
(7) For configurations in which the prescaler is not used,
the contents of the Counter Preload Registers are transferred to the counter on the first asserted edge of the TIN
input after entering the run state. On subsequent asserted
edges the counter decrements or is loaded from the Counter
Preload Registers.
(8) The lowest value allowed in the Counter Preload Register
for use with the counter is $000001.
(1) Periodic Interrupt Generator
7
I
I
6
5
4
3
z.o.
TOUT/TIACK
Control
Ct,l.
.
x
a
a
2
I
1
a
Clock
Control
TImer
Enable
000,1X
changed
In this configuration the timer generates a periodic interrupt. The TOUT pin is connected to the system's interrupt
request circuitry and the TIACK pin may be used as an interrupt acknowledge input to the timer. The TIN pin may be
used as a clock input.
The processor loads the Counter Preload Registers and
Timer Control Register, and then enables the timer. When
the 24-bit counter passes from $000001 to $000000 the ZDS
status bit is set and the TOUT (interrupt request) pin is asserted.
At the next clock to the 24-bit counter it is again loaded with
the contents of the CPR's, and thereafter decrements. In
normal operation, the processor must direct clear the status
bit to negate the interrupt request. (Figure 20)
Timer
Enable
Run-------
J
$FFFFFF
24-bit
counter
$000000
• Timer Interrupt Acknowledge Cycles
Several conditions may be present when the timer interrupt
acknowledge pin (TIACK) is asserted. These conditions affect
the PI/T's response and the termination of the bus cycle. (see
Table 11)
TIACK
Figure 20 Periodic Interrupt Generator
Table 11
Response to Timer Interrupt
Acknowledge
(2) Square Wave Generator
Square Wave Generator
Response to Asserted TIACK
PC3/TOUT Function
7
PC3 - Port C Pin
No response.
No DTACK.
TOUT - Square Wave
No response.
No DTACK.
TOUT - Negated Timer
Interrupt Request
No response.
NoDTACK.
TOUT - Asserted
Timer Interrupt
Request
Timer Interrupt Vector Contents.
DTACK Asserted.
J
6
I
5
TOUT/TIACK
Control
a
4
3
z.o.
.
Ct,l.
x
a
a
2
I
1
Clock
Control
00
0'
IX
a
Timer
Enable
changed
In this configuration the timer produces a square wave at
the TOUT pin. The TOUT pin is connected to the user's circuitry and the TIACK pin is not used. The TIN pin may be
used as a clock input.
The processor loads the Counter Preload Registers and
Timer Control Register, and then enables the timer. When
the 24-bit counter passes from $000001 to $000000 the ZDS
~HITACHI
Hitachi America Ltd
• 22tO O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
299
HD68230-------------------------------------------------------------status bit is set and the TOUT (square wave output) pin is
toggled. At the next clock to the 24·bit counter it is again
loaded with the contents of the CPRs, and thereafter decre·
ments. In this application there is no need for the processor
to direct clear the ZDS status bit; however, it is possible for
the processor to sync itself with the square wave by clearing
the ZDS status bit, then polling it. The processor may also
read the TOUT level at the Port C address.
Note that the Pe 3 /TOUT pin functions as PC3 following
the negation of RESET. If used in the square wave configuration a pullup resistor may be required to keep a known
level prior to programming. Prior to enabling the timer, TOUT
is high. (Figure 21)
Timer
Enable
J
f ..l . . . . . .- - - - - -
This configuration is similar to the periodic interrupt generator except that the Zero Detect Control bit is set. This forces
the counter roll over after Zero Detect is reached, rather than
reloading from the CPRs. When the processor takes the interrupt it can halt the timer and read the counter. This allows the
processor to measure the delay time from Zero Detect (interrupt request) to entering the service routine. Accurate knowledge of the interrupt latency may be useful in some applications. (Figure 22)
• Elapsed Time Measurement
Elapsed time measurement takes several forms; two are
described below.
(1) System Clock
Run
System Clock
7
$FFFFFF
24-Si'
Counter
\'--_--'f
TOUT
,-
Figure 21
Square
L
Wave----
Square Wave Generator
(3) Interrupt After Timeout
Interrupt After Timeout
I
I
6
4
3
TOUT/i'iACK
5
Z.O.
Control
Ctrl.
.
x
o
2
I
1
0
Clock
Timer
Control
Enable
00 or 1 X
changed
In this configuration the timer generates an interrupt after
a programmed time period has expired. The TOUT pin is
connected to the system's interrupt request circuitry and the
TIACK pin may be an interrupt acknowledge input to the
timer. The TIN pin may be used as a clock input.
Timer
Control
J
..,
Run
3
TOUTITIACK
Z.O.
Control
Ctrl.
.
o
24·Bit
Counter
$000000
r---l
ZDS
===========~I
U
TIACK
Figure 22
L-
~
TOUT
5
o
X
1
Clock
0
Timer
Enable
Contrel
o
o
changed
External Clock
7
I
4
3
TOUT/TIACK
Z.O.
Control
Ctrl.
.
I
6
o
5
X
o
2
I
1
0
Clock
Timer
Control
Enable
X
changed
This configuration allows measurement (counting) of the
number of input pulses occurring in an interval in which the
counter is enabled. The TIN input pin provides the input pUlses.
Generally the TOUT and TIACK pins are not used.
This configuration is identical to the Elapsed Time Measurement/System Clock configuration except that the TIN pin is
used to provide the input frequency. It can be connected to a
simple oscillator, and the same methods could be used. Alternately, it could be gated off and on externally and the number
of cycles occurring while in the run state can be counted.
However, minimum pulse width high and low specifications
must be met. (Figure 23)
Interrupt After Timeout
Hitachi Amenca Ltd
T
(2) External Clock
~HITACHI
300
2
This configuration allows time interval measurement by
software. No timer pins are used.
The processor loads the Counter Preload Registers (generally with all Is) and Timer Control Register, and then enables
the timer. The counter decrements until the ending event
takes place. When it is desired to read the time interval, the
processor must halt the timer, then read the counter.
For applications in which the interval could have exceeded
that programmable in this timer, interrupts can be counted
to provide the equivalent of additional timer bits. At the end,
the timer can be halted and read.
o
$FFFFFF
I
4
o
$000000
7
I
6
• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD68230
Enable
•
Run
J
Timer
$FFFFFF
Elapsed
Time
24-bl.
counter
$000000
Figure 23
Elapsed Time Measurement
• Device Watchdog
Device Watching
7
I I
6
TOUT/TIACK
Control
5
4
3
Z.O.
Ctrl.
.
o
x
2
I
1
Clock
Control
o
0
Timer
Enable
changed
This configuration provides the watchdog function needed
in many systems_ The TIN pin is the timer input whose period
at the high (1) level is to be checked. Once allowed by the
processor, the TIN input pin controls the run/halt mode. The
TOUT pin is connected to external circuitry requiring notification when the TIN pin has been asserted longer than the
programmed time. The TIACK pin (interrupt acknowledge)
is only needed if the TOUT pin is connected to interrupt
circuitry.
The processor loads the Counter Preload Register and Timer
Control Register, and then enables the timer. When the TIN
input is asserted (1, high) the timer transfers the contents of
the Counter Preload Register to the counter and begins counting. If the TIN input is negated before Zero Detect is reached,
the TOUT output and the ZDS status bit remain negated. If
Zero Detect is reached while the TIN input is still asserted the
ZDS status bit is set and the TOUT output is asserted. (The
counter rolls over and keeps on counting.)
In either case, when the TIN input is negated the ZDS
status bit is 0, the TOUT output is negated, the counting
stops, and the prescaler is forced to all Is. (Figure 24)
Timer
Enable
J
TIN
$FFFFFF
24-81.
Counter
$000000
IL.
=============:\L.J,---
zos
TOUT
Figure 24
Device Watchdog
BUS INTERFACE CONNECTION
The PI/T has an asynchronous bus interface, primarily
designed for use with the HD68000 microprocessor. With
care, however, it can be connected to synchronous microprocessor buses. This section completely describes the PI/T's
bus interface, and is intended for the asynchronous bus designer
unless otherwise mentioned_
In an asynchronous system the PI/T CLK may operate at a
significantly different frequency, either higher or lower, than
the bus master and other system components, as long as all
bus specifications are met. The HD68230 CLK pin has the
same specifications as the HD68000 CLK, and must not be
gated off at any time.
The follow!.!!g signals generate n~al read and write cycles
to the PI/T: CS (Chip Select), R/W (Read/Write)_ RSI-RS5
(five Register Select bits), 0 0 -0, (the 8-bit bidirectional data
bus), and DTACK (Data Transfer Acknowledge). To generate
interrupt acknowledge cycles PC s /PIACK or PC, /TIACK is
used instead of CS, and the Register Select pins are ignored_
No combination of the folloWing pins may be asserted simultaneously: CS, PlACK, or TIACK.
• Read Cycles Via Chip Select
This category includes all register reads, ~ept port or
timer interrupt acknowledge cycles. When CS is asserted,
the Register Select and R/W inputs are latched internally.
They must meet small setup and hold time requirements with
respect to the asserted edge of CS. (See the AC ELECTRICAL
CBARACTERISTICS table_) The PI/T is not protected against
aborted (shortened) bus cycles generated by an Address Error
or Bus Error exception in which it is addressed.
Certain operations triggered by normal read (or write) bus
cycles are not complete within the time allotted to the bus
cycle. On example is transfers to/from the double-buffered
latches that occur as a result of the bus cycle. If the bus
master's CLK is significantly faster than the PI/T's the possibility exists that, following the bus cycle, CS can be negated
then re-asserted before completion of these internal operations.
In this situation the PI/T does not recognize the re-assertion of
CS until these operations are complete_ Only at that time
does it b~in the internal sequencing necessary to react to the
asserted CS. Since CS also controls the DTArK response, this
"bus cycle recovery time" can be related to the CLK edge on
which IITACK is asserted for that cycle. The PI/T will recognize the subsequent assertion of CS three (3) CLK periods after
the CLK edge on which DTACK was previously asserted.
The Register Select and R/W inputs pass through an internal
latch that is transparent when the PI/T can recognize a new CS
pulse (see above paragraph). Since the internal data bus of the
PI/T is continuously enabled for read transfers, the read access
time (to the data bus buffers) begins when the Register Selects
are stabilized internally. Also, when the PI/T is ready to begh,
a new bus cycle, the assertion of CS enables the data bus buffers
within a short propagation delay_This does not contribute to
the overall read access time unless CS is asserted Significantly
after the Register Select and R/W inputs are stabilized (as may
occur with synchronous bus microprocessors).
. In addition to Chip Select's previously mentioned duties, it
controls the assertion of DTACK and latching of read data at
the data bus interface. Except for controlling input latches
and enabl~ the data bus buffers, all of these functions occur
only after CS has been recognized internally and synchronized
with the internal clock. Chip Select is recognized on the falling
edge of the CLK if the setup time is met, DTACK is asserted
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
301
HD68230-------------------------------------------------------------(low) on the next falling edge of the CLK. Read data is latched
at the PIIT's data bus interface at the same time DTACK is
asserted. It is stable as long as Chip Select remains asserted
independent of other external conditions.
From the above discussion it is clear that if the CS setup
time prior to the falling edge of the CLK is met, the PllT can
consistently respond to a new read or write bus cycle every
four (4) CLK cycles. This fact is especially useful in deSigting
the PI/T's clock in synchronous bus systems not using DTA K.
(An extra CLK period is required in interrupt acknowledge
cycles, see Read Cycles via Interrupt Acknowledge.)
In asynchronous bus systems in which the PI/T's CLK
differs from that of the bus master, generally there is no way to
guarantee that the CS setup time with respect to the PIIT
CLK is met. Thus, the only way to determine that the PIIT
recognized the assertion of CS is to wait for the assertion of
DTACK. In this situation, all latched bus inputs to the PIIT
must be held stable until DTACK is asserted. These include
Register Select, R/W, and write data inputs (see below).
System specifications impose a maximum delay from the
tr¥ling (negated) edge of Chip Select to the negated edge of
D ACK. As system speeds increase this becomes more dif·
ficult to meet with a simple pullup resistor tied to the DTACK
line. Therefore, the PI/T provides an internal active pullup
device to reduce the rise time, and a level-sensitive circuit
that later turns this device off. DTACK is negated asynchronously as fast as possible following the rising edge of Chip
Select, then three-stated to avoid interference with the next
bus cycle.
The system designer must take care that DTACK is negated
and three-stated quickly enough after each bus cycle to avoid
interference with the next one. With the HD68000 this necessitates a relatively fast external path from the data strobe to
CS going negated.
• Write Cycles
. In many ways write cycles are similar to normal read cycles
(see above). On write cycles, data at the Do -D, pins must
me~ the same setup specifications as the Register Select and
RIW lines. Like these signals, write data is latched on the
asserted edge of CS, and must meet small setup and hold time
requirements with respect to that edge. The same bus cycle
recovery conditions exist as for normal read cycles. No other
differences exist.
• Read Cycles Via Interrupt Acknowledge
Special internal operations take place on PIIT interrupt
acknowledge cycles. The Port Interrupt Vector Register or
the Timer Interrupt Vector Register aririmP1Citly addressed
by the assertion of PC 6 /PIArK or PC, lAC . respectively.
The signals are first synchronized with the falling edge of the
CLK. One clock period after they are recognized the data bus
buffers are enabled and the vector is driven onto the bus.
DT ACK is asserted after another clock period to allow the
vector some setup time prior to DTACK.DTACK is negated,
then three-stated as with normal read or write cycle, when
PlACK or TIACK is negated.
~HITACHI
302
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
_______________________________________________________________ HD68230
Do
015
-.-
DATA & ADDRESS
--v
p
Aa-A23
BUS INTERFACE
Q
I~ I~ ~ 1~18 «/<
'a,
AT-A,
CS
AS
ID"
HD68450
DMAC
~
I--
I--
CPG
ClK
3
::0:
11l
~0
-
(PC.)
+5V
::J
a:
$I
0
f-~
PlACK (PC.)
(PC,)
fiACK
i5'TACK PiliO TOUT
PCs) PC
( 3)
-
PB •• ,
I--- Hl
1---,H4
PC2
I--- (TIN)
I--- PC,
i---- PC.
I--HITACHI
308
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63450
• PIN ARRANGEMENT
eHD63450, HD63450P, HD63450PS
I'CG
5
DDIR
DBEN
HIBYTE
UAS
OWN
PITi
6
jffi
pel,
PClo
7
BG
8
BGACK
9
'Fi'ETIJll
R'EO'2:
2
ROQ,
REQo
DTe
DTACK
0
3
1
4
eHD63450Y
t
A,
11
A,
9 Vss
As /00
7 A9 /Dl
AlO/Dz
4 All/OJ
(Bottom View)
Pm No
NIC
A12/D4
A13/D5
2 A14/Ds
41 AIS/D7
AlB/OS
3 A17/Ds
A13/05
iJD<
AIO/D2
21
AS
5
As/Do
.,
22
RIW
NIC
----.-
A,
A,
A,
A2o/D12
10
NIC
11
3
12
'"'
13
14
~
16
17
~e
r-;,-- r-
Pelt"
DiACK -
4
35 A2l/013
3
-._ _ _ _ _ _....rA23/D1s
Function
18
20
37 AI9/D"
AZ2/D14
Pm No
AlI/03
38 AlB/OlD
(Top View)
Function
lJAS
I5mf
REQi
=
REQO
"PeG
23
b==~
25 eLK
~~
28
29
30
I
=
ACKo
BECi"
FC,
Pm No
Function
35
36
A19/01l
~~-
All/D9
r·_~LD7
Pin No
±
41
42
43
"
45
46
~CI
"
32
33
A2l/Dls
49
An/D14
50
34
A20/0l2
51
48
53
54
Function
==
V"
55
V"
A9/DJ
56
DONE
AJ2/D4
~- r - - - -
"
52
V"
57
IR()
V"
A,
58
59
ACK2
A,
60
61
62
63
64
SG
OWN
HIBYTE
=
REQl
rPcG
65
66
fiNO
67
NIC
68
BEC2
BECo
FCo
A2dOn
AlB/OW
"-~~
A14/D6
A,
"'"
AO
RjW
UDS
1®
LOS
\:lJ
DOIA
\
®
\
.-~
r'" H
®
,.--
DBEN
,--
"\
J
®
CS
~
II
3
~
..r---'
i!j;
1<
CV - ...
J!]
Data In
* Data
" "
I
DTACK
"
~l-
r-
~
~
~
lID-
f
4-J
are latched at the end of clock 25
Figure 3
AC Electrical Waveforms-MPU Read/Write
CLK
REQ
(Failing
~l~
~e:;..:;:p"::.:k~-"~PI-fo==....=+1:_----.. . ,---..,,,.-------f_:_~I----+---l!
BGACK3~~~~~
BUS Cycle
®
MPU Cycle
DMA Cycle
MPU
Cycle
CLK
*REQ" IS picked up at the rlsmg
edge of elK
Figure 4
In
cycle steal and burst modes.
AC Electrical Waveforms-Bus Arbitration
@HITACHI
314
t=
®- --:
Hitachi Amenca Ltd_ • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------------HD63450
34
78
45
910
CLKF\J'~~~~rur\ r ' \-j.~~~rLf\BGACK
Read Cycle
FCo-FC
}.
,)I
Write Cycle
f----,rnt
'----+---j-Jlr---n
!¢
;r~1t----
1LErrr-----
DTC
ACKo
ACK
*DTACK IS picked up at the rlsmg edge of eLK This IS different from HD68000
timing IS not related to DMA Read/Write (Single Cycle) sequence
* *This
Figure 5
AC Electrical Waveforms-DMA Read/Write (Single Cycle)
~HITACHI
HitachI America Ltd
• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
315
HD63450--------------------------------------------------------------
7'
4
ClK
9
8
10
FV\...r\.Jrvv-'~r-v-'~~'r-I'J\.
h
X
Read Cycle
WrIte Cycle
IX
-111------
Data In
~
r-r--
K
t"\
X
..!!.
\-! -
)-----
~
~
-@
I-- ~
I-- h
®
t- h
1\
[h
R/W
OWN
,-
""'
@-l~
-@
\
@
f.--!...-l
I
I
AC K
\
.t-!
I
\
L-.J
DTC
"
~
@r-
!t
- @f-
LJ'
I
~
~
@
"
J
• Data are latched at the end of clock 7 ThiS timing IS the same as HD68000
• ",ThiS tlmlOg IS not related to DMA Read/Wnte (Dual Cycle) sequence ThiS timing IS only applicable when 1/8 clock pulse mode IS selected
IS applicable when a bus exception occurs
* '" '" ThiS tlmmg
Figure 6 AC Electncal Waveforms-DMA Read/Wnte (Dual Cycle)
$
316
HITACHI
Hitachi America Ltd . • '2210 O'Toole Avenue· San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------------HD63450
a
9
10
1
4
5
6
8
9
10
11
12
13
14
eLK
A1-A7
>------q-n_
\\
,,--
ClK.flIln
~
ruuuuuuu-
MPU cycle-+-Idle--+--DMA cycle---01-- MPU cycle-+-DMA cycle-or Idle
. Figure 17
Cycle Steal Mode Request Timing
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
329
HD63450----------------------------------------------------------------
CLKIllL
REO'LJ"
BR--,
BG----~"'\~------J
BGACK
BUS
--~
)
CyC~~~------J ~--J{~"~=;rjr_+---~==llJT--------~~~~~
U
U_________
DTC---
Q
DONE _______~~~~~~::~~~~~~~::::~~~~~
CLKI1Jl
MPU cycle --i--Idle
--+0---------
Figure 18 Cycle Steal Bus Hold Mode Request Timing
in the previous paragraphs. In the cycle steal request mode, when
there are two or more transfers between the DMAC and the
peripheral device during one operand transfer, the request is not
recognized until the last transfer between the DMAC and the 1/
o device starts.
• Mixed Request Generation
A single channel can mix two request generation methods. By
programming the REQG bits of the OCR to "11", when the
channel is started, the DMAC auto·requests the first transfer.
Subsequent requests are then generated externally by the device.
The ACK and PCL lines perform their normal functions in this
operation.
.DATA TRANSFERS
All DMAC data transfers are assumed to be between memory and
the peripheral device. The word "memory" means a 16-bit
HD68000 bus compatible device. By programming the DCR, the
characteristics of the peripheral device may be assigned. Each
channel can communicate using any of the following protocols.
DTYP
00
01
10
11
Device Type
HD68000 compatible device
} D I Add
.
HD6800 compatible device
ua
ressmg
Device with ACK
} .
.
Device with ACK and READY Smgle Addressmg
• Dual Addressing
HD68000 and HD6800 compatible devices may be expliclty addressed. This means that before the peripheral transfers data,
a data register within the device must he addressed. Because the
address bus is used to address the peripheral, the data cannot be
directly transferred to/from the memory because the memory
also requires addressing. Instead, the data is transferred from the
source to the DMAC and held in an internal DMAC holding
register. A second bus transfer between the DMAC and the
destination is then required to complete the operation. Because
both the source and destination of the transfer are explicitey
addressed, this protocol is called dual addressing.
HD68000 Compatible Device Transfers
In this operation, when a request is received, the bus is obtained
and the transfer is completed using the protocol as shown in
Figures 19 and 20. Figures 21 through 24 show the transfer
timings. Figures 21 and 24 show the operation when the memory
is the source and the peripheral device is the destination. Figures
22 and 23 show the transfer in the opposite direction. The
peripheral device is a 16·bit device in Figures 21 and 22, and a 8·
bit device in Figures 23 and 24.
(1)
(2) HD6800 Compatible DeVice Transfers
When a channel is programmed to perform HD6800 compatible
transfers, the PCL line for that channel is defined as an Enable
clock input. The DMAC performs data transfers between itself
and the peripheral device using the HD6800 bus protocol, with the
ACK output providing the VMA (valid memory address) signal.
Figure 25 illustrates this protocol. Refer to Figure 26 for the read
cycle timing and Figure 27 for the write cycle timing. In Figure
26, the DMAC latches the data at the falling edge of clock 19, so a
latch to hold the data is necessary as shown in the figure.
@>HITACHI
330
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63450
1)
2)
3)
4)
5)
6)
DMAC
Address Device
Set R/W to Read
Place Address on AI ~A23
Place Function Codes on FCo~FC2
Assert Address Strobe (AS)
Assert Upper Data Strobe (UDS)
and Lower Data Strobe (LDS)
Assert Acknowledge (AQ<)
HD68000 Device
~I--------------------------------------------------------------~
prese~t
1)
2)
3)
Data
Decode address
Place Data on Do~D15
Assert Data Transfer
Acknowledg (DTACK)
r
t
1)
2)
3)
4)
AcqUire Data
Load Data Into Holding RegIster
Assert Device Transfer Complete (DTC)
Negate UDS and LDS
Negate AS, ~LC_K_a_n_d_D_T_C____________________________________________________,
,
1)
2)
+ Cycle
Terminate
Remove Data from Do~D15
Negate DT ACK
I
Start Next Cycle
Figure 19
1)
2)
3)
4)
5)
6)
7)
Word Read Cycle Flowchart HD68000 Type DeVice
DMAC
Address DeVice
Place Address on Al ~A23
Place Function Codes on FCo~FC2
Assert Address Strobe (AS)
Set R/W to write
Place Data on Do~D15
Assert Acknowledge (ACK)
Assert Upper Data Strobe (UDS)
and Lower Data Strobe (LDS)
HD68000 Device
I
+
1)
2)
3)
Accept Data
Decode Address
Store Data on Do~D15
Assert Data Transfer
Acknowledge (DTACK)
I
1)
2)
3)
4)
5)
Terminate Output Transfer
Assert Device Transfer Complete (D'f'C)
Negate UDS and LDS
Negate AS, ACK and DTC
Remove Data from Do~D15
Set R/W to Read
~I--------------------------------------------------------------~+
~rmlnate
1)
Negate
D'I'I)CK
Cylce
f
Start Next Cycle
Figure 20
Word Write Cycle Flowchart HD68000 Type DeVice
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
331
HD63450---------------------------------------------------------------ClK
Data Out
As/Do
-A23/D15
X!?O-X015
(External System Data Bus)
UAS
AS
~
UDS
lDS
__~%_------~m~---~
m
....__l1I\ll
\~"~
R/W
__________war___
OWN
\\\
DDIR
OJ
m
\\\
DBEN
\\\
HIBYTE
DTACK
~
DTC
ACK
DONE
ClK
Write One Word
To DeVice
The Last Transfer
Figure 21
Dual Addressmg Mode, Read/Write Cycle,
Destmatlon= 16-blt DeVice, Word Operand
ClK
1
FCo--FC,
A, -A,
2
3 4
-:::::::::JJ.~/~I;;;;;;;;;;;;;;;;;;~;;;;;;;;;;;;~JJWIl~~~~~~~~
::=xlUnL..l_____-lJJIU./L. I_______..JU~
Address Out
As/Do-A23/D15
XDo-XD15
(External System Data Bus)
UAS
AS
UDS
lDS
Data In
Address Out rrr_....;D;.;;a",ta;..o;;;u;;.;t_....,
~
lIIull
~~~V~~m~~~~U========~~
~
ULJJJ
~
~
Q1
£0
R/W
\ll
\ll
\U
OWN
~
DDIR
DBEN
\S\
ill
117
HIBYTE
DTACK
DTC
~
llJ
'UL.JJJ
ACK
m
\i\
ur
ur
~
DONE
ClK
1 2
3 4
_.---1---
Figure 22
5
6
7
8
9 10 11 121314151617181920 2122
Read One Word
- - t - - - Write One Word
From DeVice
To Memory
The Last Transfer
Dual AddreSSing Mode, Read/Write Cycle,
Source= 16·blt Device, Word Operand
~HITACHI
332
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63450
Data In
Address Out
~
(External System Data Bus)
UAS
'fJ1l
=:J1l>---QlIll
(External System Data Bus)
Address Out
Data Out
YfI[:::::::::JJ
As/Do -A23/D'5
XDo-XD,S
m
~\
m
m
IIT"'&
m
",-fJJ
or
IIT"'&
\\\
\\\
'ULJJJ
ACK
ClK
12345678910111213141516171819202122232425262728293031
--+--Read One Word
From Memory
Figure 24
Wrrte One Byte
I
To DeVice
Write One Byte
I
To DeVice
Dual Addressing Mode, Read/Write Cycle,
Destlnatlon=8-bIt Device, Word Operand
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
333
HD63450
HD6800 Device
DMAC (MASTER)
Initiate Cycle
1) Start a normal Read or Wnte
Cycle
2) Momtor Enable until It IS low
3) Assert Acknowledge (ACK)
~I----------------------------------------------~t
Transfer Data
1) Walt until Enable IS active
2) Transfer the Data
I
TermmJte Cycle
1) The master walts until Enable
goes low. (On a Read cycle the
data IS latched as clock goes
low when 0'I'l:: is asserted.)
2) Assert Device Transfer Com·
plete (0'I'l::)
3) Negate AS, DDS, LOS, ACK
and DTC
l
Start Next Cycle
Figure 25
HD6S00 Cycle Flowchart
ClK
Address Out
XDo-XD15
(External System Data Bus)
UAS
AS
uos
lOS
R/N
OWN
OOIR
OBEN
HIBYTE
OTACK
---n\L:\"____________#rr-!!.....
__
1/
....nr-lI
--~==============================~-------
~m--------------------------
ACK
PCllE Clockl
ClK
rr-
Q.
OTC
U--
--.J
I
I
I
r
nJ1IUUUUUl.IUU1u1J
JL.fUUUUL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
---t- Sync
on E Clock
-t- Read
One Byte From 6800 DeVIce -1-1- - - -
Figure 26 Dual Addressing Mode, HD6S00 Compatible Device,
Read Cycle
~HITACHI
334
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63450
I
I,
I"
ClK
i
Data Out
I!
As/Do -Az3/Dt5
XDo-XD16
(External System Data Bus)
UAS
AS
iJi55
u---n~
lOS
R/W
______________________
~,__
"
OWN
U--
"
OOIR
OBEN
HIBYTE
OTACK
\=======;r~"~:::::::::::::::::]"b:=================;~u--
:
\lD
u...u--
ACK
OTC
PClIE Clock)
---~_L"~"..""..".......lr-----1_====.;----:'_L""..",,..,,=_=,..
ClK
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
------+--8 Sync
on E Clock --;--Wnte One Byte To 6800 Device - ; - - -
Figure 27 Dual Addressing Mode, HD6S00 Compatible Device,
Write Cycle
(3) An Example of a Dual Address Transfer
This seetion contains an example of a dual address transfer using
Table 2 of Dual-Address Sequencing. The transfer mode of this
example is the following.
1. Device Port size=8 bits
2. Operand size=Long Word (32 bits)
3. Memory to Device Transfer
4. Source (Memory) Counts up, Destination (Device) Counts
Down
In this mode, a data transfer from the source (memory) is done
according to the 6th row of Table 2, since the port size of the
memory is always 16 bits. A data transfer to the destination
(device) is done according to the 3rd row of Table 2. Table 3
shows the data transfer sequence.
The port size in Table 2 is not related to the DPS bit of the DCR.
The DPS defines the port size of the device only. The DPS is set
to "0" in this example as the device port size is 8 bits.
The memory map of this example is shown in Table 4. The
operand consists of BYTE A through BYTE D in memory of
Table 4. Prior to the transfer, MAR and DAR are set to 00000012
and 00000108 respectively. The operand is transferred to the 8-bit
port device according to the order of transfer numher in Table 3.
Table 2 Dual-Address Sequencing
Operand Size
Operand
Part Size
Row No.
Port Size
1
S
BYTE
BYTE
A
BYTE
BYTE
Operand Part Addresses
Address Increment
+
+2
=
-
0
-2
A, A+2
A, A+2, A+4, A+6
·S
'3 '5
'7
+4
0
-4
+S
0
-S
"10
A
+P
0
-P
2
S
WORD
@
S
LONG
4
16
BYTE
5
16
WORD
WORD
A
+2
0
-2
@
16
LONG
WORD
'2
A, A+2
'1 '6
+4
'9
0
-4
*Numbers
In
Table 2 correspond to ones
10
'4
PACK (BYTE
or WORD)"
Tables 3 and 4
• oRefer to Address Sequencing on Operand Part Size and PACK
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (40S) 435-S300
335
HD63450-------------------------------------------------------------Table 3 An Example of a Data Transfer for One Operand
SRC: Source (Memory), DST Destination (DeVice), HR: Holding Register (DMAC Internal Reg.)
Transfer
No.
Data Transfer
Address
Output
Data Size
on Bus
0
-
-
-
1
SRC--HR
00000012
'1
2
HR --DST
3
DMAC Registers after Transfer
MAR
DAR
00000012
00000108
WORD
'2
00000014
00000108
00000108
'3
BYTE
00000014
0000010A
HR --DST
0000010A
'5
BYTE
00000014
0000010C
'10
4
SRC--HR
00000014
'6
WORD
'2
00000016
'9
0000010C
5
HR --DST
0000010C
'7
BYTE
00000016
0000010E
6
HR --DST
0000010E
'8
BYTE
00000016
00000110
'10
6'
-
-
-
00000016
00000110
Comment
Initial Register Setting
'4
'4
'4
'4
Higher order 16 bits of opera nd
fetched.
IS
Higher order 16 bits of operand
transferred.
IS
Lower order 16 bits of operand
fetched.
IS
Lower order 16 bits of opera nd
tra nsferred.
IS
MAR, DAR are pOinting the next operand
addresses when the transfer is complete.
Mode Port 5Ize=8, operand slze=Long Word, Memory to DevIce. Source (Memory) Counts Up. Destination (DeVice) Counts Down
Table 4
Memory Map for the Example of the Data Transfer
ADDRESS
ADDRESS
ADDRESS
00000010
00000011
00000106
00000013
00000108
00000015
0000010A
00000017
0000010C
00000012
00000014
BYTE A
'1
BYTE C
'6
BYTE B
'1
BYTE 0
'6
00000016
0000010E
Source (Memory)
00000107
BYTE A
'3
BYTE B
'5
BYTE C
'7
BYTE 0
'8
00000110
00000109
0000010B
00000100
0000010F
00000111
Destination (DeVice)
• Single Addressing Mode
ACT{ to inform the I/O device that the transfer request has been
Implicitly addressed devices are peripheral devices selected not
by address but by ACK They do not require addressing of data
register during data transfer. Transfers between memory and
these devices are controlled by the request/acknowledge protocol. Such peripherals require only one bus cycle to transfer
data, and the DMAC internal holding register is not used.
Because only the memory is addre..sed during a data transfer and
a transfer is done in only one bus cycle, this protocol is called
single-addressing.
(1) DeVice With ACl( Transfers
Under this protocol, the communication between peripheral
device and the DMAC is performed with a two signal REQ'/ACK
handshake. When a request is generated using the request
method programmed in the DMAC's internal control registers,
the DMAC obtains the bus and responds with ACK. The DMAC
asserts all the bus control signals required for the memory
access_ Refer to Figure 28 for the flowchart of the data transfer
from memory to the device with ACK. Figure 29 shows the
flowchart of the data transfer from the device with ACK' to
memory. Receiving the transfer request, the DMAC obtains the
bus. Then the DMAC outputs the memory address and asserts
acknowledged. When the DMAC accepts D'l'A:CK from memory,
it asserts J:>'IT: and informs the peripheral device of the transfer
termination.
.
Figures 30 and 31 show the transfer timings of the device with
ACT{: the port size for the former figure is 8-bit and the latter is
16-bit respectiveiy.
When the transfer is from memory to a device, data is valid when
DTACK is asserted and remains valid until the data strobes are
negated. The assertion of Il'l'C from the DMAC may be used to
latch the data as data strobes are not negated half clock period
after the assertion of DTC:
When the transfer is from device to memory, data must be valid on
the HD68000 bus before the DMAC asserts the data
strobes. The data strobes are asserted 'One clock period after
ACK is asserted. When the DMAC obtains the bus and starts a
DMA cycle, the three-state of the OWN line is cancelled a half
clock earlier than other control lines. If the DMA Cycle terminates and the DMAC relinquishes the bus, all the control
signals get three-stated a half clock before OWN. The m:mr and
.HITACHI
336
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63450
mode, As/Do-A"/D,, are outputted for only one and a half clock
from the beginning of the DMA bus cycle. Therefore, As/Do
through A"/D,, need to be latched externally just like in the dual
addressing mode.
DBEN lines are not asserted in the single addressing mode. Fourclock cycle is the smallest bus cycle for the transfer from
memory to device. Five-clock cycle is the smallest bus cycle for
the transfer from device to memory. If the device port size is
8bits, either LDS or UDS is asserted. In the single addressing
1)
2)
3)
4)
5)
6)
ACK Device
Memory
DMAC
Address Memory
Set R/W to Read
Place Address on AI-A23
Place Function Codes on FCo-FC2
Assert Address Strobe (AS)
Assert Upper Data Strobe (UDS) and
Lower Data Strobe (LDS)
Assert Acknowle,...d_g_e_(_A_C_K_)_ _ _ _ _ _ _ _ _ _---,
prese~t
1)
2)
3)
Data
Decode Address
Place Data on Do-DI5
Assert Data Transfer Acknowledge
(DTACK)
1)
f
1)
2)
3)
ACgUlrt Data
Load Data
I
Terminate Transfer
Assert DeVice Transfer Complete (DTC)
Negate UDS and LDS
Negate AS, ACK and DTC
~I----------------------~
Termlnlte Cycle
1) Negate DT ACK
I
I
Start Next Cycle
Figure 28
1)
2)
3)
4)
5)
Word from Memory to DeVice With ACK
DMAC
Address Memory
Place Address on AI-A23
Place Function Codes on FCo-FC2
Assert Address Strobe (AS)
Set R/W to Write
Assert Acknowledge (ACK)
ACK Device
Memory
...,----------------------------------------------------------~----.
,
1)
1)
Pres est ~ata
Place Data ,on Do-DI5
Enable Data
Assert Upper Data Strobe (UDS) and
(LDS)
Lower Data Strobe
IL-________________________
--,
1)
2)
3)
AcceJt Data
Decode address
Load Data
Assert Data Transfer
(DTACK)
Acknowledge
I
t
1)
Terminate Transfer
Assert DeVice Transfer Complete
2)
3)
Negate U DS and LDS
Negate AS,
K_a_n_d_D_T_C___________•
(om
ACf..
t
1)
Start
Terminate Cycle
Negate DTACK
I
~ext Cycl~
Figure 29
Word from DeVice With ACK to Memory
~HITACHI
Hitachi America Ltd
• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
337
HD63450---------------------------------------------------------------ClK
r'---
QJ/
QJ/
FCc-Fez
Al-A7
As/Do-A23/D1s
10 11 12 13
,
BGACK
JIll
JIll
UAS
AS
UOS
lDS
R/W
OWN
~I
---fJJI::::::::)
um
XDo-XD,s
ImllQWHm
----~
~
-=::=:rr-m~~====m---m~~~~L:==~m-'~-\\\
",.--.---------""\\\
OJ
====:J--~====~--~\~"
_________war~---
ar---
- .
OOIR
OBEN
\\\
HIBYTE
Dmmm
\\\
DTACK
\1L.IJJ
DTC
ACKo
ACK,
ar--"mmoo
m
UL..../JT'
__________~u=\========,~moc::::-------===~-------
ClK
1 2 3
-Idle
4
5
6
7
8
9 10111213141516171819202122 23 2425
I
Idle--
--t-- Memory to DeVice-+- DeVice to Memory
Channel 0
Figure 30
Channell
Single Addressing Mode with 8·Bit DeVices as
Source and Destination (Read,Wrlte Cycles)
ClK
1234
FCo-FC,
A,-A,
Aa/Do-A23/D15
XDo-XD"
::JIll
10111213
JIll
::=un
vII
cm:::::::::Jl~;:I~Ii=====::;;-':'
-=-YlICJ
::::::::JJJl}--
~
oror-
U~
(]J
ill
low
OWN
DDIR
High
DBEN
High
HIBYTE
DTACK
'flO.
'!l11
-=::JIll.
High
--..lIf-m
PCl (READY)
DTC
\i~
ACKo
m
OJ
lTl
\lLJU
lTl
m
m
roro-
\I\
\\\
ACK,
ur
~
or
ClK
Figure 36
Single Addressing Mode With 8·blt DeVice as Source and
Destination With PCl Used as a READY Input (Read·Wrote Cycles)
~HITACHI
Hitachi America Ltd
• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
341
HD63450---------------------------------------------------------------Table 5 Operation Combinations
Addressing
Dual
Dual
Dual
I
10:
11:
68000, 6800
68000, 6800
68000, 6800
ACK or
ACK & Jm\1)'(
a : supported
REQG
Port
with
Single
00:
01:
Device Type
Operand
Word
Long Word
8
16
16
0
0
0
0
0
0
0
0
00, 01, 10, 11
00,01
10,11
8
16
0
x
X
X
00, 01, 10, 11
00, 01, 10, 11
x
0
X
X : not supported
Auto request at a limited rate
Auto request at a maximum rate
"'RECJ line requests the operand transfer
First operand is auto requested, and subsequent operands
are externally requested.
part is the minimum of the port size and the operand size .
The number of the operand part is the operand size divided
by the port size.
• Address Sequencing
The sequence of addresses generated depends upon the port size,
whether the addresses are to count up, down or not change and
whether the transfer is executed in the single addressing mode or
the dual addressing mode. The memory address count method
and the peripheral device address count method is programmed
using the Memory address count (MAC) bit and the Device
address count (DAC) bit in the Sequence Control Register (SCR).
(i)
REQG bits of OCR
Byte
In the dual addressing mode, memory is regarded as a
device whose port size is 16 bits and the operand size is a
byte or a word. When the operand is transferred to the
memory from the I/O device whose port size is 8 bits and
the operand size is byte, the DMAC reads 2-byte operand
one byte at a time from the I/O device and writes 2 bytes
at the same time to the memory, or reads one byte from
the I/O device and writes one byte to the memory. Thus,
when the port size is 8 bits and the operand size is byte,
two-operand transfer which is performed at the same time
is called PACK. Utilizing the PACK, the DMAC may
improve the DMA bus efficiency. However, packing is not
performed if the address does not count. When the port
size is 8 bits and the operand size is byte (port size: 8 bits,
without PACK) with the DMAC in the dual addressing
mode, the DMAC repeats the following cycles:
CD READ BYTE (reads data from the I/O device or the
memory)
CZI WRITE BYTE (writes data to the I/O device or the
memory)
Table 7 shows the dual addressing sequencing
Single addressing mode
In the single addressing mode, memory address sequencing
is shown in Table 6. If the operand size is byte, the memory
address increment is one (1). If the operand size is word,
the memory address increment is two (2). If the memory
address register does not count, the memory address is
unchanged after the transfer.
(ii) Dual addressing mode
In the dual addressing mode, the operand size need not
match the port size. Thus the transfer of an operand may
require several DMA bus cycles. Each DMA bus cycle,
between memory and DMAC and between DMAC and the
device, is called the operand part and transfers a portion
or all of the operand. The addresses of the operand parts
are in a linear increasing sequence. The step between the
addresses of the operand is two. The size of the operand
Table 6
Port Size
Operand Size
8
16
Byte
Word
Single Address Sequencing
Memory Address Increment
+ (increment)
=(unchanged)
-(decrement)
+1
+2
0
-1
-2
°
Table 7 Dual Address Sequencing
Port Size
Operand Size
Byte
Word
Long
Byte
Word
Long
8
8
8
16
16
16
P -1 If packing IS not done
=2 If packing is done
Part Size
Byte
Byte
Byte
Pack
Word
Word
Address Increment
Operand Part
Address
+
A
A, A+2
A, A+2, A+4, A+6
A
A
A, A+2
+2
+4
+8
+P
+2
+4
Pack;;;; byte If packing IS not done
=word If packing IS done
=
-
°°
°°
°
-2
-4
-8
-P
-2
-4
~HITACHI
342
Hitachi America ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
0
----------------------------------------------------------------HD63450
.INITIATION AND CONTROL OF CHANNEL OPERATION
e Channel Status Register (CSR)
e Operation Initiation
The channel status register contains the status of the channel at
the channel operation termination. The register is cleared by
writing a one (1) into each bit of the register to be cleared.
To initiate the operation of a channel, the STR bit of the CCR is
set to start the operation. Setting the STR bit causes the
immediate activation of the channel, the channel will be ready to
accept requests immediately. The channel initiates the operation
by resetting the STR bit and setting the channel active bit in the
CSR. Any pending requests are cleared, and the channel is then
ready to receive requests for the new operation. If the channel is
configured for an illegal operation, the configuration error is
signaled, and no channel operation is run. The illegal operations
include the selection of any of the options marked "(undefined,
reserved)". If the MTC is set to zero in any mode other than the
chaining mode, or BTC is set to zero in the array chaining mode,
then the count error is signaled and the channel is not activated.
The channel cannot be started if any of the ACT, COC, BTC,
NDT or ERR bit is set in the CSR. In this case, the channel
signals the operation timing error.
eOperation Continuation (Continue Mode)
When the STR bit or the ACT bit in the CSR is set, setting the
CNT (Continue) bit in the CCR allows multiple blocks to be
transferred as in the chaining modes. The CNT bit is set in order
to continue the current channel operation. To set the CNT bit,
the initial address of the next block to be transferred, the
corresponding function code, and the number of words to be
transferred must be previously set to the BAR, BFC and BTC. If
the CNT bit is set when either the STR or the ACT bit is not set,
the operation timing error is signaled. The configuration error is
signaled when the CNT bit is set in the chaining modes.
COC
The channel operation complete (COC) bit is set if the channel
operation has completed. The COC bit must be cleared in order
to start another channel operation. The COC bit is cleared only
by writing a one to this bit or resetting the DMAC.
PCS
The peripheral status (PCS) bit reflects the level of the PCL line
regardless of its programmed function. If PCL is at "High" level,
the PCS bit reads as one. If J5L1.:' is at "Low" level, the PCS bit
reads as zero. The PCS bit is unaffected by writing to the CSR.
PCT
The peripheral control transition (PCT) bit is set, if a falling edge
transition has occurred on the PCL line. (The PCL line must
remain at "low" level for at least two clock cycles.) The PCT bit
is cleared by writing a one to this bit or resetting the DMAC.
BTC
Block transfer complete (BTC) bit is set when the continue
(CNT) bit of CCR is set and the memory transfer counter (MTC)
is exhausted. The BTC bit must be cleared before the another
continuation is attempted (namely, setting the CNT bit again),
otherwise an operation timing error occurs. The BTC bit is
cleared by writing a one to this bit or resetting the DMAC.
NOT
eOperation Halting (Halt)
The CCR has a halt bit which allows suspension of the operation
of the channel. If this bit is set, a request may still be generated
and recognized, but the DMAC does not attempt to acquire the
bus or to make transfers for the halted channel. When this bit is
reset, the channel resumes operation and services any request
that may have been received while the channel was halted.
However, in the burst request mode, the transfer request should
be kept asserted until the initiation of the first transfer after
clearing the halt bit.
Normal device termination (NDT) bit is set when the peripheral
device terminates the channel operation by asserting the DONE
line while the peripheral device was being acknowledged. The
NDT bit is cleared by writing a one to this bit or resetting the
DMAC.
ERR
Error (ERR) bit is set if any errors have been signaled, When the
ERR bit is set, the code corresponding to the kind of the error
that occured is set in the CER. The ERR bit is clered by writing
a one to this bit or resetting the DMAC.
e Operation Abort by Software (Software Abort)
Setting the software abort bit (SAB) in the CCR allows the
current operation of the channel to be aborted. In this case, the
ERR bit and the COC bit in the CSR are set and the ACT bit is
reset. The error code for the software abort is set in the CER.
The SAB bit i's designed to be reset if the ERR bit is reset. When
the CCR is read, the SAB always reads as zero(O).
ACT
The active (ACT) bit is asserted after the STR bit has been set
and the channel operation has started. This bit remains set until
the channel operation is terminated. The ACT bit is unaffected
by write operations. This bit is cleared by the termination of the
channel or resetting the DMAC.
.CHANNEL OPERATION TERMINATION
DIT
As part of the transfer of an operand, the DMAC decrements the
memory transfer counter(MTC). If the chaining mode is not used
and the CNT bit is not set or the last block is transferred in the
chaining mode, the operation of the channel is complete when the
last operand transfer is completed and the MTC is zero. The
DMAC notifies the peripheral device of the channel completion
via the DONE output.
Done input transition (DIT) bit is set if the DONE input is
generated while the multiple block transfer mode with DONE is
being set. The DIT bit is cleared by writing a one to this bit or
resetting the DMAC.
However, in the continue mode, DONE is outputted at the
termination of every data block transfer. When the channel
operation has been completed, the ACT bit of the CSR is cleared,
and the COC bit of the CSR is set.
The occurrence of errors, such as the bus error, during the DMA
bus cycle also terminates the channel operation. In this case, the
ACT bit in the CSR is cleared, the ERR and the COC bits are set,
and at the same time the code corresponding to the error that
occurred is set in the CER.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
343
HD63450------------------------------------------------------------------• Interrupts
have interrupt requests, the determination of which channel
presents its interrupt vector is made using the same priority
scheme defined for the channel operations.
The DMAC can signal the termination of the channel operation
by generating an interrupt request. The interrupt request is
generated by the following condition.
(!) INT=1
and
~ COC=1 or BTC=1 or ERR=1 or NDT=1 or PCT=1
(the PCL line is an interrupt input)
This may be represented as
IRQ-INT· (CDC + BTC+ERR+ NDT+PCT*)
('PCL line is programmed as an interrupt input.)
The bus cycle in which the DMAC provides the interrupt vector
when receiving an lACK from the MPU is called the interrupt
acknowledge cycle. The interrupt vector returned to the MPU
comes from either the nomal or the error interrupt vector
register. The norroal interrupt register is used unless the ERR bit
of CSR is set, in which case the error interrupt vector register is
used. The content of the interrupt vector register is placed on As/
Do-A"/D,, and DTACK is asserted to indicate that the vector is
on the data bus. If a reset occurs, all interrupt vector registers are
set to (00001111)2, the value of the uninitialized interrupt vector
of the HD68000 MPU. The timing of the interrupt acknowledge
cycle is shown in Figure 36. The HD68000 MPU outputs the
interrupt level into AI-A, and "1" into A,· A, during the interrupt
acknowledge cycle, but the HD63450 DMAC ignores these
signals.
When the IRQ line is asserted, changing the INT bit from one to
zero to one will cause the IRlJ output to change from "low" to
"high" to "low" again. The IRlJ should be negated by clearing the
CDC, the BTC, the ERR, the NDT and the PCT bits.
If the DMAC receives lACK from the MPU during asserting the
IRlJ, the DMAC provides an interrupt vector. If multiple channels
ClK
30
31
32
33
34
35
36
- ......Ull
01
\\\
\\\
37
38
>--
OOl
II
\\:
\\\
1/
10
----~~-=~~~========~\~--------~r~lli________~/~-A ,6/D8 - A23/D,5
A8/Do--A,5/D7
--------~f~~ll~n;;::::::~):--------J1H.fmll
II>--
XDo-XD,5
(External System Data Bus)
D~CK ------------~:-----~--------Dnr'---ClK
LSl...JlJ1
1
2
3
Figure 37
4
5
30 31
32
33
34 35
36 37
38
MPU lACK Cycle to DMAC
• Multiple Data Block Transfer Operation
Array Chaining
When the memory transfer counter (MTC) is exhausted, the
channel operation still continues if the channel is set to the array
chaining mode or the linked array chaining mode, and the chain
is not exhausted. The channel operation also continues if the
continue bit (CNT) of the CCR is set. The DMAC provides the
initialization of the memory address register and the memory
transfer counter in these cases so that the DMAC can transfer the
multiple blocks.
This type of chaining uses an array in memory consisting of
memory addresses and transfer counts. Each entry in the array is
six bytes long and, consists of four bytes of address followed by
two bytes of transfer count. The beginning address of this array
is in the base address register, and the number of entries in the
array is in the base transfer counter. Before starting any block
transfers, the DMAC fetches the entry currently pointed to by the
base address register. The address information is placed in the
memory address register, and the count information is placed in
the memory transfer counter. As each chaining entry is fetched,
the base transfer counter is decremented by one. After the
chaining entry is fetched, the base address register is incremented
Continued Operation
The continued operation is described in the Initiation and the
Control of the Channel Operation section.
~HITACHI
344
Hitachi America Ltd • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------------HD63450
--
Bit 15
top address of
the table
memory
Bit 0
memory address A(H)
memory address A(l)
transfer count A
memory address B(H)
memory address B(l)
transfer count B
memory address C(H)
memory address C(l)
Array table -
transfer count C
memory
address C
....
--
""
block C
transfer
) count C
block A
}
H063450
OMAC
H068000
MPU
MAR
memory
....
address A
*
DAR peripheral device address
~
{
transfer
count A
BAR top address of the table
MTC~-nn~um~~er~*~o~~o~c~s~-i
BTCL-~b~el~n~t~ra~n~s~fe~re~d~__J
I
memory
address B
'to be loaded from the array table
transfer
count B
block B
.....
Note
The number of data blocks bemg
transferred m this example IS 3
Figure 38
peripheral
device
address
...-
...
-~--
peripheral device
or
memory
Transfer Example of the Array Chainmg Mode
to point the next entry. When the base transfer counter reaches
a terminal count of zero, the chain is exhausted, and the entry
just fetched determines the last block of the channel operation.
An example of the array chaining mode operation and the
memory format for supporting for array chaining is shown in
Figure 38. The array must start at an even address, or the entry
fetch results in an address error. If a terminal count is loaded into
the memory transfer counter or the base transfer counter, the
count error is signaled.
Linked Array Chaining
This type of chaining uses a list in memory consisting of memory
address, transfer counts, and link addresses. Each entry in the
chain list is ten bytes long, and consists of four bytes of memory
address, two bytes of transfer count and four bytes of link
address. The address of the first entry in the list is in the base
address register, and the base transfer counter is unused. Before
starting any block transfers, the DMAC fetches the entry
currently pointed to by the base address register. The address
information is placed in the memory address register, the count
information is placed in the memory transfer counter, and the
link address replaces the current contents of the base address
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
345
HD63450---------------------------------------------------------------register. The channel then begins a new block transfer. As eacb
chaining entry is fetched, the update base address register is
examined for the terminal link which has all 32 bits equal to zero.
When the new base address is the terminal address, the chain is
exhausted, and the entry just fetched determines the last block of
the channel operation.
An example of the linked array chaining mode operation and the
memory format for supporting it is shown is Figure 39.
In Figure 39, the DMAC transfers data blocks in the order of
Block A, Block B, and Block C. In the linked array chaining
mode, the BTC is not used. When the DMAC refers to the linked
array table, the value of the BFC is outputted as the function
code. The values of the function code registers are unchanged by
the linked array chaining operation.
This type of chaining allows entries to be easily removed or
inserted without having to reorganize data within the chain.
Since the end of the chain is indicated by a terminal link, the
number of entries in the array need not be specified to the
DMAC.
The linked array table must start at an even address in the linked
array chaining mode. Starting the table at an odd address results
in an address error. If "0" is initially loaded to the MTC, the
count error is signaled. Because the MPU can read all of the
DMAC registers, all necessary error recovery information is
available to the operating system.
The comparison of both chaining modes is shown in Table 8.
Table 8 Chammg Mode Address/Count Information
Base Address
Register
Chaining Mode
Base Transfer
Counter
Array Chalnmg
address of the
array table
number of data
blocks bemg
transferred
Base Transfer
Count=O
Linked Array
Chalnmg
address of the
hnked array
table
(not used)
Linked
Address::;::Q
memory
Btt 15
hnk
address X
-
memory address B(H)
memory address B(l)
transfer count B
link address Y(H)
hnk address Y(l)
link
hnked array table ......
address Y
memory address C(H)
memory address C(l)
transfer count C
"All 0" terminator
"All 0" terminator
top address of
the table
memory address A(H)
memory address A(L)
transfer count A
-link address X(H)
link address X(L)
HOBB450
OMAC
memory
addressC-
H06BOOO
~::~P~.'-'P~h,-,,~I~d'-V,-'.-'~d~d,-,,~,
MPU
~
block C
}
transfer
count C
BAR top address of the table
~;~r---I-no-t~:-se-d-I--~
memory
address A -block A
transfer
count A
J
·to be loaded from the hnked array table
memory
address B -block B
penpheral
deVIce
address
}
transfer
count B
peripheral deVice
or memory
Figure 39 Transfer Example of the Lmked Array Chaining Mode
~HITACHI
346
Completed
When
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63450
Halt
Multi·Block Transfer with DONE Mode
The multi· block transfer with DONE mode is set by setting BTD
bit of the OCR. In this mode, data block transfer continues even
if the '!:XJNE signal is inputted during the DMA bus cycle. If
DONE is inputted during the DMA bus cycle when the multi·
block transfer is not performed, the DMAC resets ACT bit of the
CSR, sets NDT and COC bits, and terminates the DMA
operation.
When DONE is inputted from the I/O device during the DMA bus
cycle in which ACK is outputted, the DMAC terminates the
operand transfer and then the current block transfer. Then,
maintaining the bus, the DMAC sets DIT bit of the CSR and
reads the data block transfer information from the memory.
After that, the DMAC transfers the next block as required.
In the continue mode, if DONE is inputted from the I/O device
during the DMA bus cycle in which ACK is outputted, the DMAC
terminates the operand transfer and terminates the current block
transfer. Then the DMAC shifts the data in BAR, BFC and BTC
to MAR, MFC and MTC, waits for the transfer request, and
transfers the next block. If the value of BAR, BFC and BTC is
the same as that of MAR, MFC and MTC, the DMAC repeats
transferring the same block.
. The timing diagram of halt is shown in Figure 40. This diagram
shows halt being generated during a read cycle from the 68000
compatible device in the dual addressing mode. If the halt
exception is asserted during a DMA bus cycle, the DMAC does
not terminate the bus cycle immediately The DMAC waits for
the assertion of lJ"fACK before terminating the bus cycle so that
the bus cycle is completed normally. In the halted state, the
DMAC puts all the control signals to high impedance and
relinquishes the bus to the MPU. The DMAC does not output the
BR until halt exception is negated. When halt exception is
negated, the DMAC acquires the bus again and proceeds the
DMA operation. In order to insure a halt exception operation, the
BEe-lines must be set to halt at least until the assertion of DTC.
If the halt is asserted when the DMAC has the bus but is not
executing any bus cycle, the DMAC relinquishes the bus as soon
as halt exception is·asserted.
AID BUS
UAS
AS
As stated above, the multi· block transfer with DONE mode
realizes termination (stops the current block transfer) and restart
(starts transferring the next block) of the multi·block transfer in
the high·speed data transfer system without MPU interposition.
UDS
R/W
\.....0....-1"\
11'<----.
OWN
• Bus Exception Conditions
IIfI-...--J
DDIR
The DMAC has three lines for inputting bus exception conditions
called BEC" BEC" and BEC,. The priority encoder can be used
to generate these signals externally. These lines are encoded as
shown in Table 9.
DBEN
'--<----'
HIBYTE
DTACK
DTe
Table 9
BEC Bus Exception Condition
BEC2
BEC,
BECD
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
AeK
HALT
(BECo-BEC2)'
Exception Condition
--,'6
--m
un
.
,
Iff'--+----..
BGACK
No exception condition
Halt
Bus error
Retry
RelinqUish bus and retry
(undellOed, reserved)
(undellOed, reserved)
Reset
/I
BR
'---.1/
BG
eLK
--+-
Read
Other Pus Master
from DeVice
__
- - H a l t Asserted
'sECo-l3EC2"'(011 )
In order to guarantee reliable decoding, the DMAC verifies that
the incoming code has been stable for two DMAC clock cycles
before acting on it. The DMAC picks up BECo·BEC, at the rising
edge of the clock. If BECo' BEC, is asserted to the undefined code,
the operation of the DMAC does not proceed. For example, when
the DMAC is waiting for DTACK, inputting DT ACK does not
result in the termination of the cycle if BECo' BEC, is asserted to
the undefined code. In addition, when the transfer request is
received, BR is not output if the BEC,· BEC, is not set to code
Write
~r~~t~a=- to Memory --+---
- + - ~::d --t---- DMA cycle
Figure 40
Halt Operation
(lll).
If exception condition, except for HALT, is inputted during the
DMA bus cycle prior to, or in coincidence with DTACK, the
DMAC terminates the current channel operation immediately.
Here coincident means meeting the same set up requirements for
the same sampling edge of the clock. BECo- BEC, is ignored in
the current DMA bus cycle if it is input after DTACK If a bus
exception condition exists, the DMAC does not generate any bus
cycles until it is removed. However, the DMAC still recognizes
requests.
~HITACHI
Hitachi America Ltd
• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
347
HD63450---------------------------------------------------------------Bus Error
The bus error exception is generated by external circuitry to
indicate the current transfer cannot be successfully completed
and is to be aborted. As soon as the DMAC recognizes the bus
error exception, the DMAC immediately terminates the bus cycle
and proceeds to the error recovery cycle. In this cycle, the DMAC
adjusts the values of the MAR, the DAR, the MTC and the BTC
to the values when the bus error exception occurred. 24 clocks
are required for the error recovery cycle in the single addressing
mode and in the read cycle of the dual addressing mode. 28 clocks
are required in the write cycle of the dual addressing mode. If the
DMAC does not have any transfer request in the other channels
after the error recovery cycle, the DMAC relinquishes the bus.
thus wi11 not honor any requests until it is removed. However, the
DMAC sti11 recognizes requests. The retry timing is shown in
Figure 42.
Relinquish and Retry (R & R)
The relinquish and retry exception causes the DMAC to
relinquish the bus and three-state all bus master controls and
when the exception is removed, rearbitrate for the bus to retry
the previous operation.
The diagram of the relinquish and retry timing is shown in
Figure 43.
The diagram of the bus error timing is shown in Figure 41.
AID BUS
eLK
AID BUS
=
R/W
DOS
OWN
AS
~~
ill
---.
---4
"""" -----..
DlACK
~~
'--II--------'
-11/ \\\\\\\\\\\\\\\\\\\\\\\\\\W4 u-----~~
DTe
'-I~
I
R/W
OWN
DOl A
~;~~~
HIBYTE
mumiumm,.
= -'
DTACK
'-II--------'
--------------~~~~---------
ISECo-BtC2)'
8/
AeK
~
U/////UIJ/U/
U
BGACKI===============~~~~~
BR
1'1
~UI---~
Bus Error
(~~~I'
--------------~I~
eLK
elK
123'
5"
189'0"'2'3'4'5'61".'9
3'"2~J'~3.J7
-+-SERR on Write to Devlce---4-- Error --+----Other Channels·"
~
Recovery Cycle··
Read
RelinqUish and
Retry Asserted
Other Master
and --+--Read Retry
Rearbltratlon
-+-
-+-
*an:o-~"'(lOl)
• *jn the s,ngle addreSSIng mode aoo In the ,,,,,d cycle of the dual addreSSing mode 24 clods
In the w"tecycle of the dual addressmg mode 28clocks
••• The DMAC keeps the bus tJeca~se the other CMn~s have requests pending It other channels do not have r
~>
~
~
74LS04
........
OWN
r
UAS
16
1
G
G
OE
16
AB/Do-A23/D'5
16
00
D
74LS373
X2
HD63450
DMAC
+5V ~
r+-
AB-A23 (Address Bus)
I-
~
~
~A
DBEN
DDIR
G
DIR
74LS245
B~ Do-D7
(Data Bus)
.!.A
FIgure 46
G
74LS245
B~ DB-D'5
DIR
An Example of the Demultoplexed Address Data Bus
.HITACHI
HItachI America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
351
HD63450---------------------------------------------------------------• APPLICATIONS
Examples of how to interface HD63450 to an HD68000 based
system are shown in Figures 46 and 47.
directional buffer 74LS245. These signals are three-stated at
active low, which requires pull-up resistors.
Figure 47 shows an ex~ of inter-device connection in the
HD68000 system. REQ, ACK, 'PC[, DTC, and DONE are used to
control I/O devices.
Figure 46 shows an example of how to demultiplex the address/
data bus. OWN and UAS are used to control 74LS373 for latching
the address. DBEN and DDIR are used to control the bi-
".
Do
Do
015
,....--
~
FOC,
etc
Data & Address
Bus Interface
--
I~
'---
I~ll~I"'" Ii I§
' - REOo
~ ACKo
015
r-
As-A23
::>
c ---
6
8~
~'"
-
'-r---
"0(1)
:J
00
'"
AS ~
~
f+5V
"0
Cl
0
0
0
00
'"
00
'"'"~
"0
«
0
0
0
:J
co
Cl
I
00
co
+5V
Cl
I
Do-D7
OE
1D
I
8D
l
1
Q
G
10~
t
_§
~
0
HD63450
DMAC
Do-D7
Select
0
c;;:
i.-
R/W
~~+5V
~ Ao/Do
-A23/D,5
Do-D,5
~
J5CG
ACK2
PeG
~ -AClG
I ~
80
As-A23
AS
~
74L5373
r'....-'
E
JIlII:,. . - g:~;'"
1I!-8
I--
Do-D7
dl
---
D81;N
DDIR
Figure 48 An Example of Connection with HD6800 type Peripheral Devices
(channel 2 and 3 are used)
$HITACHI
Hitachi Amenca Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
353
HD63450---------------------------------------------------------------• PACKGE DIMENSIONS (Unit: mm (inch»
scale: 1/1
eDC·64
8128
(3200)
33
64
:!l
~
@>
ff=="
32
H
025!J.!!!-
(OOIO:!:88S1)
scale: 1/1
ePGA·68
22 86±O 45
(0900±OOI81)
5 OSrnax
2 S4mm
(0 200m3x) (0 I DOmin )
2642
{I 040)
~
~
I)
D
<;
+1
lii
e
scale: 1/1
eDP·64
8204 (3 230)
83 22max (3 276maJl)
3J
64
2286
(0 gOO)
_
I
H~!I_~
II
254±025
048±0I
(OIOO±OOIO)
(OOIHOOD4)
~!1l
O'~IS'
~'/.f:I:'\\\
\O"\"'~~~
@HITACHI
354
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63450
scale· 1/1
eDP-64S
64
576(2268)
58 6max (2 307mall)
33
o
32
J..l!Too39)
scale: 3/2
2S I5±O 12
{D 990±D DOS)
*Inch value mdlcated for your reference
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
355
HD68450
Direct Memory Access Controller (NMOS)
Microprocessor implemented systems are becoming increasingly complex, particularly with the advent of high-performance
l6-bit MPU devices with large memory addressing capability. In
order to maintain high throughput, large blocks of data must be
moved within these systems in a quick, efficient manner with
minimum intervention by the MPU itself.
The HD68450 Direct Memory Access Controller (OMAC)
is designed specifically to complement the performance and
architectural capabilities of the H068000 MPU by providing the
following features:
HD68000 8us Compatible
4 independent DMA Channels
Memory·to-Memory, Memory-to-Device, Device-to-Memory
Transfers
MMU Compatible
Array-Chained and Linked-Array-Chained Operations
On-Chip Registers that allow Complete Software Control by
the System MPU
Interface Lines for Requesting, Acknowledging, and
Incidental Control of the Peripheral Devices
Variable System Bus Bandwidth Utilization
Programmable Channel Prioritization
2 Vectored interrupts for each Channel
Auto-Request and External-Request Transfer Modes
+5 Volt Operation
uy" stands for Pin Grid
Array Package.
The DMAC functions by transfering a series of operands (data)
between memory and peripheral device; operand sizes can
be byte, word, or long word. A block is a sequence of operations; the number of operands in a block is determined by a
transfer count. A single-channel operation may involve the
transfer of several blocks of data between memory and device.
co,.....
StaM AlgI.Ie'
CO."'..
Error .... ,1IeI'
e...... _
-~
Channal
eM"......w
Type No.
Bus Timing
'I} On. P.r DMAC
HD68450-8
8MHz
DC-64
10MHz
DC-64
HD68450Y-8
8MHz
PGA-68
HD68450Y-10
10MHz
PGA-68
E,_
t-..;;ln;;:"7.~~=Pt='::.=":::to:...'--H (6:~t Per
PriorIty Rlliliter
M.mo.y
Function Codft
15
L
1-
I
I
I
•
Narmal
IntarruptVector
Packaging
HD68450-10
356
Canlt'OlAeg ..ltlr
•
Memory AddrnI
FunctIcInCodn
MemcHVl'nnIhI·C-,-.
... ,.,........ CDllIIh.
""'*"',
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
Channel)
________________________________________________________________ HD68450
• PIN ARRANGEMENT
• HD68450
•
HD68450Y
@~rQ\~@~t0~~~?m1
~B9 60 61 6BB< ,t:::',
OOIR
OBEN
HIBYTE
~O\2lIOi@5@@5@@i01~
6~S~'
d§
'UAS
o
\0
~@s
@5'I"
00 53
0
0°~
BR
1m
i
A,
A,
A,
A.
A.
A,
1
0
a"
OWN
S~67
&&
0
J
a'
~~S
~}£i6
@rQ\
"P7
d'~~.
&-rQ'\&
~~50 '~~);:;{~§},:;,9
rD1~&.7OJ&&.0.&.&&.
@(2)'@@6@S@'@'@'@~C
Vee
A,
Vss
A./D o
A,/D.
(Bottom View)
AIO/Dl
AII/Ds
A12/D4
AulDs
AulD,
, AulD,
A.,/D,
An/D,
3 AIIIDID
7 AI9/DII
A20/01l
An/Oil
AulD ••
......_ _ _ _ _ _,....Au /0 15
HIBYTE
(Top View)
~~~~~(~
DD1R
64
REa.
6'
66
67
-~
P L.
N/C
6.
A'6/Ds
A,./Ds
A,
DTC
ACK,
~HITACHI
Hitachi America Ltd. • 22tO O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
357
HD68450---------------------------------------------------------------• ABSOLUTE MAXIMUM RATINGS
Item
..
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 - +7.0
V
Input Voltage
V,n
Operating Temperature Range
Topr
-0.3 - +7.0
0-+70
V
°c
Storage Temperature
T"",
-55-+150
°c
• With respect to
INOTE)
Vss (SYSTEM GND)
Permanent LSI damage may occur If maximum ratings are exceeded Normal operation should be under recommended operating conditions
If these conditions are exceeded, It could affect reliability of lSI.
• RECOMMENDED OPERATING CONDITIONS
Item
Supply Voltage
Symbol
Vee
V'H
Input Voltage
V'L
Operating Temperature
• W'th respect to
Topr
··
·
min
4.75
typ
2.0
-
5.0
-0.3
0
25
max
5.25
Unit
Vee
O.S
70
V
V
°c
V
VSS (SYSTEM GNDI
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee = 5V ±5% Vss = OV Ta = 0-+70°C, unless otherwise noted.)
min
typ
max
Unit
V'H
2.0
-
V'L
Vss-0.3
-
Vee
O.S
V
V
I,n
-
-
10
p.A
AS, UD ,lD ,R/W, OAS,
DTACK, SGACK, OWN, DTC,
HIBYTE, DDIR, DBEN,
FC. -FC,
ITS'
-
-
10
p.A
IRO, DONE
100 ,
-
-
20
p.A
V
Symbol
Item
Input "High" Voltage
Input "Low" Voltage
Test Condition
~ lACK, BG", ClK,
Input leakage Current
SEC. - BEC,
REO.-RE0 3
& ~'ibSDlsLA. -A'3,
Three-5tate (Off State)
I nput Current
Open Drain (Off State)
I nput Current
A, - A" D. - DIS/A. - A'3,
AS", ODS, LOS, R/W. OAS,
Output "High" Voltage
Output "low" Voltage
Power Dissipation
Capacitance
DTACK, BGACK, BR, OWN,
DTC, HIBYTE, DDIR, DBEN,
ACK. - ACK3, PCl. - PCl3,
FC. - FC,
V OH
IOH = -400p.A
2.4
-
-
A, - A" FC. - FC,
D. -DIS/A. -A'3, AS, UDS,
lOS, RIW, DTACK. B~
OWN, DTC. HIBYTE, DDIR,
DBEN, ACK. - ACi<;, OAS,
PCl. -PCl3, BGACK
VOL
IOL - 3.2mA
-
-
0.5
VOL
IOL =5.3mA
-
-
0.5
IRO, DONE
VOL
10L =S.9mA
-
-
0.5
1.4
2.0
W
-
-
15
pF
Po
C,n
f = 8 MHz,Vee =5.0 V
Ta = 25°C
V,n=OV,
Ta = 25°C, f= 1 MHz
~HITACHI
358
H,taehi America ltd. • 2210 OToole Avenue • San Jose, CA 95131 • (40B) 435-8300
V
----------------------------------------------------------------HD68450
LOAD A
LOAD B
LOAO C
+5V
+5V
+5V
Test
POint
1 11kO
5000
r
7100
Test
POint
130pF
6 Ok\?
, 52074 H
"
EquIValent
IRQ DONE
A, - A" FC o - FC,
Figure 1 Test Loads
• AC ELECTRICAL SPECIFICATIONS (Vee = 5V ±5%, VSS = OV, Ta = 0-+70°C)
Item
No
Symbol
H;6~~~0.8
Hci~~4~O
1'
Test
10
Co n d II Ion I--=H",0"'''1''4",50"-Y:"'-+--:"HO""",84 5,,,OY=-"',,,0-l
Frequency 01 Operation
Clock Period
5
Clock Width low
'CL
Clock Fall Time
'Cl
126
65
65
Clock Rise Time
Asynchronous Input Setup Time
500
250
250
10
10
20
Data In to OBEN low
tOIOBL
OTACK low to Oata Invalid
tOTLOI
100
45
45
10
500
250
250
10
10
15
Addreu on to AS on low
10
lOA
AS. "D'S on High 10 Address on Invalid
DS In High to CS High
11
Clock High to DOIR low
12
Clock High to OOIR High
tSIHAIV
tDSHCSH
13
OS In High to DOIR High Impedance
tOSHORZ
14
Clock low to OBrn low
tCLDSL
15
Clock low to DBEN High
tCLOSH
tOSH08Z
16
I5s on High to DBEN High Impedance
17
Clock High to Data Out Valid IMPU readl
tCHOVM
1S
DS on High to Data Qut Invalid
IOSHOZn
19
OS on High to Data High Impedance
tOSHOZ
20
Clock low to DTACK low
tCLDTL
21
DS on High to DTACK High
tOSHOTH
22
DTACK Width High
10TH
23
OS on High to DTACK High Impedance
tOSHOTZ
24
OTACK low to OS',n High
tOTLDSH
25
REO Width low
tREal
20
26
RECI low to SR low
tAElBAL
250
27
Clock High to SR low
tCHBAL
28
Clock High to SA High
tCHBAH
29
BG low to aGACK Low
tBGLBL
30
SR Low 10 MPU Cycle End (AS on Hlghl
IBAlASH
31
MPU Cycle End lAS on Hlghl to BGACKI_ow
IASHBL
32
REG low to SGACK Low
33
Clock High 10 SGACK High
tCHBL
34
Clock High to BGACR High
tCHBH
35
Clock low to 8GACK High Impedance
36
Clock High to FC Valid
tCHFCV
37'
Clock High to Address Valid
ICHAV
38
Clock High to Address/FC/Data High Impedance
'CHAZx
Clock High to Address/FC/Data Invalid
tCHAZn
40
Clock low to Address High Impedance
tCLAZ
41
Clock High to UAS Low
tCHUL
42
Clock High to UAS High
tCHUH
43
Clock Low to UAS High Impedance
tCLUZ
44
OAS: High to Address Invalid
tUHAI
45
Clock High to AS, US low
tCHSL
46
Clock low to OS Low (wrlTel
tCLOSl
47
Clock Low to AS, OS High
tCLSH
48
Clock low to As., OS High Impedance
tCLSZ
49
AS Width low
50
l5S Width low
51
AS, OS Width HIQh
52
Address/FC Valid to AS, 05 Low
'SH
53
AS, OS High to Address/FCIData Invalid
tSHAZ
54
Clock High to R/W low
tCHRL
55
Clock High to R/W High
'0
110
160
110
60
110
10
10
160
180
20
clk per
200
'0
70
70
45
45
120
elk per
60
60
110
60
120
70
110
60
45
55
45
120
'0
100
120
100
100
70
70
80
elk per
55
elk per
clk per
60
60
70
90
110
100
70
70
tCLBZ
39
10
10
70
70
120
70
70
120
180
ICHORl
tCHORH
-
90
60
60
70
20
30
65
65
60
70
60
60
70
'0
195
145
105
20
20
255
190
150
30
30
70
70
60
60
(to be contlOuedl
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
359
HD68450
No
Item
Svmbol
H~68~~O-8
Test
Condition
H~:'~~~
H068450Y 8
10
HD68450Y 10
80
70
Clock Low to R/W HIgh Impedance
tCLAZ
57
Address/Fe Valid to AfW Low
lAVAL
20
10
58
59
RM Low to DS Low (wflte)
US High to R/1111 High
tRLSL
120
tSHRH
40
90
20
60
61
Clock Low to OWN Low
Clock low to OWN High
felOH
70
62
Clock High to OWN High Impedance
tCHOZ
80
63
64
OWN Low to BGACK low
BGACK High
65
OWN Low to UAS Low
66
Clock High to ACK Low
tCHACL
70
67
68
Clock Low to ACK low
tCLACL
Clock HIgh to ACK HIgh
tCHACH
70
70
69
ACK low to OS Low
tACLDSL
100
70
30
56
70
ICLOL
to OWN High
IOLBL
30
tBHOH
30
IOLUL
30
60
60
70
20
20
20
60
60
60
80
20
OS High to ACK High
tOSHACH
71
Clock High to HIBYTE Low
tCHHIL
70
60
72
Clock Low to HIBYTE Low
tCLHIL
73
Clock High to HIBYTE High
tCHHIH
70
70
60
74
Clock low to HIBYTE High Impedance
ICLHIZ
80
75
76
Clock High to oTe Low
tCHDTL
i5ie" High
Clock High to
tCH01H
77
Clock Low to DTC Hlqh Impedance
78
DTC Width Low
tOTCL.
tCLOTZ
60
70
60
70
60
70
70
80
Fig 1 Fig 8
105
80
79
0
Low to OS High
tOTLOH
80
Clock High to DONE Low
tCHDOL.
70
60
81
Clock Low to
iJ'O'fii"E Low
tCL.oOL.
70
82
Clock High to UUNI: High
tCHOOH
130
60
120
83
84
Clock Low to
High Impedance
tCL.ORZ
Clock Low to DBEN High Impedance
tCL.OBZ
80
80
85
UDII" LOIN 10 OBtN Low
tOAL.oBL.
30
86
OBEN High to
tOBHOAH
30
i5l5iR
'OIR High
20
30
70
70
20
20
87
OBEN Low 10 Address/Data High Impedance
tOBLAZ
17
17
88
Clock Low to PCL Low (1/8 clock I
tCLPL
70
60
89
Clock Low to
tCL.PH
70
60
90
Pcr:" High
(1/8 clock}
peL Width Low (1/a clock I
tpeL.L.
91
OTACK Low 10 Data In (setup tlmel
toALol
92
OS High to Data Invalid (hold tlmel
tSHol
93
OS High to OTACK High
tSHOAH
94
95
Data Out Valid 10 OS Low
tOOSL
Data In to Clock Low (setup time)
tOICL
BEC Low 10 DTACK Low
tBECoAL.
B'EC"Wldth Low
tBECL
96
97
98
99
100
101
102
103
104
105
Clock High to
i'R'IT Low
Clock High to IRQ High
HI:AUl In to
i5TC" Low (Read)
40
elk per
40
150
115
120
90
15
15
50
50
20
clk per
20
tCHIAL
70
60
tCHIRH
130
120
tRAL.oTL
145
REAm In to i5SLow (Wrltel
tRALOSL
205
OS High 10 REA'[5"9"Hlgh
tOSHAAH
UUNI: In L.ow to UI AL:K L.ow
toOLOAL
50
OS High to DONE In High
tOSHOOH
0
Asynchronous Input Hold Time
tASIH
Unit
120
170
120
0
50
90
120
0
15
90
15
(I'
Figure 2 Input Clock Waveform
•
360
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------HD68450
28
ClK
29
30
31
32 33
34
35
36
5
23
24
.
25
26
27
28
29
30
~~~~~r_nf1__JL_f'f-" r--u-L
,.
----<
MPU READ CYCLE
I
AS
MPU WRITE CYCLE
\
lOS
t·
• r-
11
.
UDS
\
10j
\.
CS
R/Itv
- r-I
1OA
~
DBEN
,---;
.
::,
17
F--
\
~
r .. H
1.
\
\
\
1.
DOIA
1.
h
1.
1.
A./Do-
An/D,
4
1
7
-po.
1.
Data In
20
24
i--T---
r- ~
~
•
r
21
lE}-
f
~
2.
Data are latched at the end of clock 25
Figure 3 AC Electrical Waveforms - MPU ReadlWrite
ClK
REO
(Falltng
III-
::gl!e.!:p:!:"!.k~"P:!.I_I===~="=Ril_-------4>----=--------_+"""'_+_'Ir--;r---r-----
2.
..
~~~~~~3~O~~~~~~~~~
~~
~-=
ill
.2
DTC _ _ _
~
_ _ _ _ _ _ _ _ _ _ _ _I f _ _ - - - - - - - - - - - - - ' r
ClK
* REO
'8'R
IS pIcked up at the rISing edge of eLK In cycle steal and Burst modes
Isn't asserted while some BEC exception condition eXists or OMAC IS accessed by MPU.
Figure 4 AC Electncal Waveforms - Bus Arbitration
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
361
HD68450-------------------------------------------------------------9
CLKF\.FI'-J ; :
10
~C-Jrur;"-,~ r;~_.r\.Fv\~~rLf\-
BGACK
FCo-FCz
64
38
38
[}
Re d Cycle
37
Write Cycle
I)
AI/DoAn/O'5
UAS
41
x
42
L44
4.
AS
43
.. -f
47
t~
SO
1
~~ Pi
58
~
DOIR
.M_r
OREN
"'-'
r-:;;5
J
L
ACKo
~-
ACK,
DONE
.J8
1
- ~.r
..~~__~-\\~----------_tJr_-------
70
..
~
fIIQ- ~----------~~======F~l-+~
","-
"I
.. DTACK IS picked up at the rising edge of eLK. This IS different from H068000.
This timing IS not related to DMA Read/Write (Smgle Cycle) sequence
Figure 5 AC Electrical Waveforms - DMA Read/Wrlte (Single Cycle)
•
362
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD68450
7· •
ClK
8
9
10
F\..f\J\j~ '-J~~~~JL
h
FCo-
X
Read Cycle
FC~
Write Cycle
lX
A.;Oo-
..........
A2J/DI$
-"
Data In
~
UDS
~
lOS
~
~
9.
K
1\
~ t-
----
-----~
~
91
r----
-53
I-- n
I-- h
51
i -n
1\
In
R/W
r
OWN
11
~ 1"'
_
"
t
PCl
BEC
,~
I
\ - "l-
....
J
\
'L-J
oTC
..
...
1$
~
DTACK
ACK
,.
14
J ..
DBEN
HIBYTE
~
12f---
~
I
90
~
97
I
Data are latched at the end of clock 7 ThiS timing IS the same as H06aOOD
ThiS timing IS not related to DMA Read/Write (Dual Cycle) sequence ThiS timing IS only applicable when 1/8 clock pulse mode IS selected
ThiS timing IS applicable when a bus exceptIOn occures
If #6 IS satisfied for both DTACK and BEC, #96 may be Ons
If the propagation delay of the external bidirectional buffer LS245 IS less than 17nsec, the conflict may occur between the address output of the
DMAC and the system data blls In thiS case, the output of DBEN must be delayed externally
Figure 6 AC Electrical Waveforms - DMA Read/Wnte IDual Cycle)
@HITACHI
Hitachi Amenca Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
363
HD68450---------------------------------------------------------------2
3
4
5
6
8
9
10
1
2
3
4
5
6
8
9
10 11
12
13
14
ClK
XD, - XD"
UAS
M
---I
>---<:::========}----~(===========:J>"---J
'---I
'\~__________~I
\~__________________~;----
RtW
OWN
Low
100
101
ClK
1
2
4
6
8
9
10
1
4
5
6
7
8
9
10
11
12 13
Figure 7 AC Electrical Waveforms - DMA Read/Wnte (Single Cycle with PCl)
~HITACHI
364
Hitachi America Ltd • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
14
-------------------------------------------------------------------HD68450
ClK
AI -A,
XDo ...... X0 15
UAS
AS
UDS
lOS
RfW
OWN
HI BYTE
low
High
DTACK
,.4
104
DONE IN
ACK o
ACK,
DTC
ClK
If #615 satisfied for both DTACK and DONE, #103 may be Ons
Fi,9ure 8 AC Electrical Waveforms - DONE Input
(NOTES for Figure 3 through 81
1) Setup time for the asynchronous Inputs eG. BGACK, CS, lACK, AS, UOS, LOS, and RM guarantees their recognition at the next
failing edge of the clock Setup time for BECo .... BEC 1 • REOo ..... FfEQ3, PCLo ..... Pel 3 , DTAC K, and i5"O'N'E guarantees their
recognition at the next rising edge of the clock
2) Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 a volts
3) These waveforms should only be referenced In regard to the edge-to-edge measurement of the timing specificatIOns. They are not
Intended as a functional description of the Input and output Signals Refer to other functional descriptIOns and their related diagrams
for device operation
~HITACHI
Hitachi America Ltd, • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
365
HD68450-------------------------------------------------------------• Address Bus (A, through A,)
• SIGNAL DESCRIPTION
The following section identifies the signals used in the
DMAC In the definitions, "MPU mode" refers to the state
when the DMAC is chip selected by MPU. The term "DMA
mode" refers to the state when the DMAC assumes ownership of
the bus. The DMAC IS in the "IDLE mode" at all other times.
Moreover, the DMA bus cycle refers to the bus cycle that IS
executed by the DMAC In the "DMA mode".
NOTE) In this data sheet, the state of the SignalS IS
descnbed with these words: active or assert, Inactive
or negate.
ThiS is done to avoid confUSIOn when dealing with a mixture
of "active-low" and "active-high" Signals. The term assert or
assertIOn IS used to indicate that a Signal is actIVe or true independent of whether that voltage IS low or high The term negate
or negatIOn is used to md,cate that a signal is inactive or false.
Input/Output
Active-high
Three-statable
In the MPU mode, the DMAC mternal registers are accessed
with these lines and LDS, UDS. The address map for these
registers IS shown in Table I. Dunng a DMA bus cycle, A I -A,
are outputs containing the low order address bits of the location
being accessed.
•
Function Code (FC. through FC,)
Output
Active-high
Three-statable
These output signals provide the functIOn codes during
DMA bus cycles They are three-stated except in the DMA bus
cycles. They are used to control the HD68000 memones.ISee Atten-
tion on Usage, Note (6) /
• Clock (ClK)
Ae-A23
DO-DIS
--REOo
-ACKo
PClo
A, -A1
CS
AS
REO,
ACK,
lDS
UDS
RW
DTACK
peL,
SA
i!G
HD6S450
BGACK
DMAC
Input
This IS the mput clock to the HD68450, and should never be
terminated at any time. ThiS clock can be different from the
MPU clock since HD68450 operates completely asynchronously
• Chip Select ((;8)
Input
Active low
REO,
ACK,
i'CG
iRQ
REO,
lACK
~
PCl,
OWN
1J"AS
This input Signal is used to chip select the DMAC in "MPU"
mode. If the CS Input IS asserted dunng a bus cycle which IS
generated by the DMAC, the DMAC internally termmates the
bus cycle and Signals an address error ThIS function protects
the DMAC from accessmg its own reglster.ISee AttentIOn on Usage,
Note (5)./
RmY'fE
i5!Ei'.f
• Address Strobe (AS)
DDIR
DONE
Input/Output
Active low
SECo
m;
BEC,
DTC
FCo
FC,
FC,
Vss12)
Figure 9 Input and Output Signals
Three-statable
In the "MPU mode", thIS line IS an input indicating valid
address input, and during the DMA bus cycle It IS an output
indicating valid the address output from the DMAC on the
address bus.
The DMAC mom tors these mput lines dunng bus arbitratIOn
to determme the completIOn of the bus cycle by the MPU or
other bus masters.
• Upper Address Strobe (UAS)
Output
ActIVe low
• Address/Data Bus (As/D. through A'3/D,,)
Input/Output
Active-high
Three-statable
Three-statable
These lines arc time multiplexed for address and data bus
The lines DDlR, DBEN, UAS and OWN are used to control the
demultlplexmg of the data and address lines externally. Demultlplexmg IS explained in the later section The bi-directlOnal
data bus IS used to transfer data between DMAC, MPU, memory
and I/O deVices
Address lines are outputs to address memory and I/O devices.
This line is an output to latch the upper address lines on the
multiplexed data/address lines It is three-stated except m the
"DMAmode".
• Own (OWN)
Output
Active low
Three-statable
~HITACHI
366
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD68450
ThIS line IS asserted by the DMAC durmg DMA mode, and IS
used to control the output of the address hne latch ThIS hne
may also be used to control the dlCectlOn of bl-d,rectlOnal
buffers when loads on AS, LDS, UDS, R/W and other Signals
exceed the drive capability It IS three-stated m the "MPU
mode" and the "IDLE mode"
•
Data Direction
fooiR)
Outputs
Thlee-statable
Active low (when data dlCecllon IS mput to
the DMAC)
Active lugh (when the data duectlOn IS output
from the DMAC)
This hne controls the dlfectlon of data through the bidirectional
buffer which lS used to demultiplex the datal address hnes It IS threestated durmg the "IDLE mode"
In the "MPU mode", thIS line IS an output mdlcatmg the
completion of Read/Wnte bus cycle by the MPU
In the "DMA mode", the DMAC mOOitors this hne to determme when a data transfer has completed. In the event that a
bus exceptIOn IS requested, except for HALT, pnor to or concurrent with DTACK, the DTACK response IS Ignored and the
bus exceptIOn IS honored In the "IDLE mode", thIS signal IS
three-stated
•
These Imes proVide an encoded signal mput md,catmg an
exceptIOnal conditIOn 10 the DMA bus cycle. Sec bus exceptIOn
sectIOn for detads
Bus Request (SR)
Data Bus Enable (DBEN)
Output
Active low
Output
Active low
Three-statable
ThlS hne controls the output enable hne of bldlCectlOnal
buffers on the multiplexed data/address hnes It IS a three-stated
during the "IDLE mode"
ThlS output hne lS used to request ownership of the bus by the
DMAC.[See AttentIOn on Usage, Notes (8), (9) J
• Bus Grant (eG)
Input
Achve low
• High Byte (ffiBYfE)
Output
Active low
Three-statable
ThIS hne lS used when the operand Size IS byte 10 the smgle
addressmg mode It IS asselted when data IS present on the
upper eight bits of the data bus It IS used to control the output
of b,dlCectlOnal buffers which connects the upper eight bits of
the data bus with the lower eight bits It IS three-stated dunng
the "MPU mode" and the "IDLE mode"
•
(BEe;; through BEc,)
Input
Active low
•
•
Bus Exception Controls
ThIS hne IS used to indicate to the DMAC that It IS to be the
next bus master The DMAC cannot assume bus owne,sh,p untd
both AS and BGACK becomes mactive Once the DMAC acquires the bus, It does not contmue to monitor the BG mput
•
Bus Grant Acknowledge (BGACK)
Input/Output
ActIVe low
Three-statable
Read/Wrlte (R!W)
ThIS Ime is an mput m the "MPU mode" and an output
dunng the "DMA mode". It IS three-stated dunng the "IDLE
mode". It IS used to control the direction of data flow
Bus Grant Acknowledge (BGACK) IS a bidHectional control
hne. As an output, It is generated by the DMAC to md,cate that
It IS the bus master
As an mput, BGACK IS momtored by the DMAC, m hmlted
rate auto-request mode, to determme whether or not the
current bus master IS a DMA device or not. BGACK IS also
mOOitored durmg bus arbitratIOn 10 order to assume bus ownership
[See AttentIOn on Usage, Notes (8), (9) J
• Upper Data Strobe (ODS). Lower Data Strobe (iJ5S)
•
Input/Output
ActIVe low (wntc)
ActIVe high (read)
Input/Output
Active low
Three-statable
Output
Active low
These lines are extensions of the address Imes indicating
which byte or bytes of data of the addressed word are being
addressed These hnes combmed corresponds to address line
Ao in table I.
•
Interrupt Request (IRO)
Three-statable
This line IS used to request an interrupt to the MPU.
•
Interrupt Acknowledge (lACK)
Input
Active low
Data Transfer Acknowledge (i5'fACK)
In pu t/ Ou tput
Active low
Three-statable
Open drain
This line is an input to the DMAC indicating that the current
bus cycle is an interrupt acknowledge cycle by the MPU The
eHITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
367
HD68450---------------------------------------------------------------DMAC responds the interrupt vector of the channel with the
highest priority requesting an interrupt. There are two kinds of
the interrupt vectors for each channel: normal (NIV) or error
(EIV). lACK is not serviced if the DMAC has not generated
IRQ.
• Channel Request
(CSR)
"-~~~:g~~)
(OCR)
(SCR)
(CCR)
(NIV)
(EIV)
(REO;; through REa,)
~~~~(CPR)
f..t!"~~Li(MFC)
f-.!'~_£2!!!!.-I(DFC)
Input
Active low or fallIng edge
These lmes are the DMA transfer request mputs from the
peripheral devices
These lines are falling edge sensitive inputs when the request
mode is cycle steal They are low-level sensitive when the
request mode is burst.
• Channel Acknowledge
=.
i'----..L..!''''~"''''~~'-!!!!.._I (8FC)
f--"':-=':!.'':....
::
.:::'_~~~__I{MTCI
"-_ _ _ _ _-~~"~~~~~~~'~--------~(MAR)
"-_____
......
_,..,--,-_-=._._______-i(DAR)
"'-=....::..:.:-:..-=________...J(BAR)
L._ _ _ _ _
Clln1?':'7:.@,.t« I(GCR) - ~~e:cr
Figure 10 Internal Registers
•
These lmes mdlcate to the I/O deVIce reque&ting a transfer
that the request is acknowledged and the transfer is to be performed. These lines may be used as a part of the enable CirCUIt
for bus mterface to the penpheral.
• Peripheral Control Line
Input/Output
ActIve low
(PCLo through PeL, )
Three-statable
Table 1 Internal Register AddreSSing ASSignments
Address Bits
Register
Channel Status Register
Channel Error Register
DeVice Control Register
Operation Control Register
Sequence Control Register
Channel Control Register
Memory Transfer Counter
Memory Address Register
DeVice Address Register
Base Transfer Counter
Base Address Register
Normal Interrupt Vector
Error Interrupt Vector
Channel Priority Register
Memory Function Codes
DeVice Function Codes
Base Function Codes
General Control Register
Note (2).J
Done (DONE)
Input/Output
Active low
Register Organization
The internal reglster addresses arc represented in Table I.
Address space not used wlthm the address map IS reserved for
future expansIOn. A read from an unused location m the map
results in a normal bus cycle WIth all ones for data A wnte
to one of these locatIOns results m a normal bus cycle but no
write occurs.
Unused bIts of the defined regIsters in Table I read as zeros
The four lines (PCL. - PeL,) are mUlti-purpose lines which
may be individually programmed to be a START output, an
Enable Clock input, a READY input, an ABORT input, a
STATUS input, or an INTERRUPT input. [See Attention on Usage,
Open Dram
As an output, thIS line is asserted concurrently with the
ACKx timing to indicate the last data transfer to the peripheral
device As an input, it allows the peripheral device to request a
normal terminatIOn of the DMA transfer. [See Attention on Usage,
7 6 5 4
c
c
c
c
c
c
c
c
c
c
c
c
c
c
3 2
0 0 0 0
0
0
0
0
0
0
0
0
c c 0
c c 0
1
1
1
1
1
1
1
0 0
0 0
0 0
0 0
0 0
0 1
0 1
1 0
1
0
0
0
0
0
1
1
1 0
1 1
0 1
0 1
1 1
1 0
1
1
1
1
1
a
a
1
1
s
0
1
0
0
1 0 0 0
1 1 0 0
1
1
Mode
0 R W·
R
R
R
R
1 R
b R
R
s R
b R
R
R
R
R
R
R
R
R
0 0 1
1 0 0
1 0 1
1 1 0
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
cc OO-Channel :;; 0,0 1-Channel :# 1 ,
10-Channel :I; 2,11-Channel :#: 3,
ss OO-hlgh-order, 01-upper middle,
10-lower mlddle,11-low-order
b O-hlgh-order,
1-low-order
see Channel Status Register Section
Note (2).J
•
channel
r _____.".--,.,,--,J....,-_.c-=''''......
=''''~=.·_ __«BTCI
(ACK. through ACK,)
Output
Active low
•
One.1 per
*
Device Transfer Complete (DTC),
Output
Active low
•
Three-statable
This line IS asserted when the DMA bus cycle has terminated
normally with no exceptions. It may be used to supply the data
latch hmmg to the peripheral device. In this case, data is valid at
the fallIng edge of DTC.
• INTERNAL ORGANIZATION
The DMAC has four independent DMA channels. Each channel has its own set of channel registers. These registers define
and control the activity of the DMAC in processing a channel
operation.
•
368
Device Control Register (OCR)
The OCR is a device oriented control register. The XRM bits
specifies whether the channel is in burst or cycle steal request
mode. The DTYP bits define what type of device is on the
channel. If the DTYP bits are programmed to be a HD6800 device,
the PCL definition is ignored and the PCL line is an Enable clock
mput If the DTYP bits are programmed to be a deVIce with READY,
the PCL definition is ignored and the PCL line is a READY input.
The DPS bit defmes the port size (eight or sIxteen bits) of peripheral
device. (A port size IS the largest data which the peripheral devieecan
transfer during a DMA bus cycle.) the PCL bits define the function of
the PCL lme. If the DTYP bits are programmed to be HD6800
device, or DeVIce with ACK and READY, these definitions are ignored. The XRM bits are ignored if an auto-request mode (REQG =
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD68450
00 or 01
10
Operatum Control Register) IS selected
10
II
XRM
DTYP
PCl
DPS
XRM
00
01
10
II
DTYP
00
01
10
II
DPS
()
I
PCl
00
01
10
II
Bit 2
REQ Ime requests an operand transfer
Auto-request the fllSt operand, external request fOI
subsequent operands
Brt 6 Not Used
o
6
(EXTERNAL REQUEST MODE)
BUist Transfci Mode
(undefmed, leselved)
Cycle Steal Mode wnhout Hold
Cycle Steal Mode wilh Hold
(DEVICE TYPE)
HD6HOOO compatrble devlCe, CxpllCilly addressed
(dual addlessmg mode)
HD6ROO compatible device, expliCitly addressed
(dual addrcsslllg mode)
Device With ACK, Impircltly addressed
(smgle addresslllg mode)
Device With ACK and READY, Impircilly addressed
(srngle addresslllg mode)
(DEVICE PORT SIZE)
R bn pOlt
16 hil port
(PERIPHERAL CONTROL LINE)
Status Input
Status Input With Interrupt
Start Pulse
Abol t Input
Not Used
•
Operation Control Register (OCR)
The OCR IS an operatIOn control register. The DIR bit
defmes the dnectlon of the transfer The SIZE bils define the
size of the operand The CHAIN bils define the type of the
CHAIN mode 111e REQG bits denne how requests for transfcrs
arc generated
4
SIZE
CHAIN
• Sequence Control Register (SCR)
The SCR IS used to define the sequencrng of memory and
deVIce addresses
4
6
o
•
Channel Control Register (CCR)
The eCR IS used to start or termmate the operation of a
channel ThiS register also determrnes rf an rnterrupt request IS
to be generated Settrng the STR brt causes rmmediate actlvatron of the channel, the channel wrll be ready to accept request
Immediately The STR and CNT brts of the regrster cannot
be reset by a wnte to the regrster The SAB bit rs used to
termrnate the operatron forcedly Settrng the SAB bit wrll reset
STR and CNT Settrng the Hl T brt wrll hal t the channel operatron, and clearing the HlT brt wrll resume the operatron. Setting
start bIt must be done by byte access OtherWise, trmrng error
occurs.
REQG
DIR
(DIRECTION)
Transfer from memory to device
(transfer from MAR address to DAR address)
Transfer from device to memory
(transfer from DAR address to MAR address)
SIZE (OPERAND SIZE)
00
Byte (8 bilS)
01
Word (16 bits)
10
Long Word (32 bits)
II
See Note Below
CHAIN (CHAINING OPERATION)
00
Cham operatlOn is disabled
01
(undefined, reserved)
10
Array Chaining
II
Linked Array Chaining
REQG (DMA REQUEST GENERATION METHOD)
00
Auto-request at transfer rate hmIled by General Control
Register (Lrmrted Rate Auto-Request)
01
Auto-request at maximum rate
STR
o
If the DMAC I ....et to dual addre..,~mg mode. port ~lze 8 bit'>, external rcque"t
mode, and the data tran.,fcr l~ from penpheral devIce to memory, ..,et SIZE = II
the OperatIOn Control Register (OCR)
In
DAC
MAC (MEMORY ADDRESS COUNT)
00
Memory address regIster does not count
oI Memory address register counts up
10
Memory addre" regrster counts down
II
(undefined, reserved)
DAC (DEVICE ADDRESS COUNT)
00
DeVIce address regIster does not count
01
DeVIce address register counts up
10
Devrce address regrster counts down
II
(undefined, reserved)
BIts 7,6,5,4 Not Used
6
NOTE
MAC
CNT
o
4
HlT
SAB
INT
o
STR
(START OPERATION)
No operatron rs pending
I
Start operatron
CNT (CONTINUE OPERATION)
o No contrnuatron rs pendrng
I
Continue operatron
HLT (HALT OPERATION)
o Operatron not hal ted
I
Operation halted
SAB (SOFTWARE ABORT)
o Channel operation not aborted
I
Abort channel operation
INT
(INTERRUPT ENABLE)
o No interrupts enabled
I
Interrupts enabled
BItS 2, 1,0 Not Used
o
•
Channel Status Register (CSR)
The CSR is a register containrng the status of the channel.
~HITACHI
Hitachi Amenca Ltd
• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
369
HD68450----------------------------------------------------------------
COC
BTC
o
4
6
NDT
ERR
ACT
o
PCT
PCS
COC
(CHANNEL OPERATION COMPLETE)
Channel operallon mcomplete
Channel operatIOn complete
(BLOCK TRANSFER COMPLETE)
o Block transfer incomplete
I
Block transfer complete
NDT (NORMAL DEVICE TERMINATION)
o No normal devICe terminatIOn by DONE mput
1
Device terminated operation normally by DONE Illput
ERR (ERROR BIT)
o No errors
I
Error as coded III CER
ACT (CHANNEL ACTIVE)
o Channel not active
Channel actIve
I
PCT (pCL TRANSITION)
o No PCL transitIOn occurred
I
PCL trans ItlOn occurred
PCS
(THE STATE OF THE PCL INPUT LINE)
o PCL "Low"
I
PCL "High"
BIt 2 Not Used
o
I
BTC
Channel Error Register (CER)
The CER IS an error condItIOn status regIster. The ERR bIt of CSR
indicate:;, If there IS an error or not Bits 0-4 mdicate what type of error
occurred. [See AttentIOn on Usage, Note (3).[
•
6
o
o
CP
00
01
10
11
Bit
(CHANNEL PRIORITY)
Priority level 0
Pnority level 1
Priority level 2
Pnority level 3
7 through 2 Not Used
General Control Register (GCR)
The GCR IS used to define what portIOn of the bus cycles IS
available to the DMAC for hrnlted rate auto-Iequest generatIOn.
GCR IS also used to specify the hold time for cycle steal mode
WIth hold.
•
6
4
o
o
o
BT
BR
BT (BURST TIME)
The number of DMA clock cycles pel bUlst that the DMAC
allows m the auto-request at a lImIted rate of transfer IS controlled by these two bIts. The number is 2(BT+4) (two to the BT+4
power)
BR (BANDWIDTH RATIO)
The amount of the bandWIdth utllrzed by the auto-request at
a lrmlted rate transfer IS controlled by these two bits. The ratIo IS
2(BR+ I) (two to the BR + 1 power).
The hold tIme for cycle steal mode WIth hold IS defined to
be minrmum of 1 sample mterval and maxImum of 2 sample
mtervals. A sample mtervalls defmed to be 2(BT+BR+5) (two to the
BT + BR + 5 power) clock cycles.
BIts 7 through 4 Not Used
Address Registers (MAR, DAR, BAR)
Three 32-bit registers are utlhzed to implement the Memory
Address RegIster, DevIce Address RegIster, and the Base Address
Regrstcr. Only the least significant twenty-four bIts are connected to the address output pms. The content of the MAR IS
outputted when the memory IS accessed m slOgle or dual adressing mode. The content of the DAR IS outputted when the
penpheral device is accessed. The contents of the BAR IS outputted when readmg chain mformation from memory m the
Array Chaming Mode or the Lmked Array Chammg Mode. It IS
also used to set the top address of the next block transfer in
Continue mode.
•
4
o
ERROR CODE
Errol Code
00000 No error
00001 ConfiguratIOn error
00010 Operation tlmmg error
0010 I Address error in MAR
00110 Address error m DAR
00111 Address error in BAR
01001
Bus error in MAR
01010 Bus error m DAR
01011
Bus error in BAR
01101 Count error in MTC
01111 Count error in BTC
10000 External abort
1000 I Software abort
BIIs 7,6, 5 Not Used
•
Function Code Registers (MFC, DFC, BFC)
The DMAC has three function code regIsters per channel
the Memory FunctIOn Code Register (MFC), Device Function
Code Register (DFC), and the Base Function Code Register
(BFC). The contents of these registers are outputted from FC o
through FC, Imes when an address is outputted from MAR,
DAR, or BAR, respectively The BFC is also used to set the
MFC for the transfer of the next data block in the Continue
mode.
•
Channel Priority Register (CPR)
The CPR IS used to define the pnonty level of the channel.
Pnority level 0 is the highest and priority level 3 is the lowest
priority.
1
6
o
o
4
o
o
o
FC2
FC1
FCO
Bits 3 through 7 Not Used
o
o
o
o
o
o
o
CP
• Transfer Count Registers (MTC, BTC)
Each channel has two 16-bit counters' the Memory Transfer
Counter (MTC) and the Base Transfer Counter (BTC). The MTC
~HITACHI
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Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD68450
counts the number of transfer words m one block, and IS decreased by one for every operand transfer
The BTC IS used to count the number of data blocks 10 the
Array Chammg Mode. BTC IS also used to set the number of
operands to transfer for the next data block in the Continue
Mode.
•
ReadIWrite of the DMAC Registers by MPU
The MPU reads and wntes the DMAC internal regIsters and
controls the DMA transfer FIgure II mdlcates the IImmg diagram when the MPU reads the contents of the DMAC register
The MPU outputs AI-A", FCo-FC" AS, RjW, UDS, and LDS,
and accesses the DMAC mternal register The specific mternal
regIster IS selected by AI·A7, LDS and UDS The CS and lACK
Imes are generated by the external cIrcuIt WIth As-A" and
FCo-FC, The DMAC outputs data on the data bus, togethel
WIth DDlR, DB EN and DTACK The DDlR and DBEN contlol
the bIdirectIOnal buffer on the bus and the DT ACK mdlcates
that the data has been sent or receIved by the DMAC Read
Cycle is eIghteen CLKs FIgure 12 shows the MPU wnte cycle
Write cycle IS fifteen CLKs.
Note the following points.
(I) The clock reference shown 10 thIS figure is the DMAC mput
clock.
(2) The DDlR and the DBEN are three-stated at the begmnmg
whIch detects CS and the endmg of the cycle
(3) Dunng the MPU lead cycle, the DTACK IS asserted after
the data IS valid on the system bus
(4) Dunng the MPU wnte cycle, fhe DDlR Ime WIll be dnven
low to duect the data buffers toward to DMAC before the
buffers are enabled
(5) Dunng the MPU wnte cycle, the DMAC wIll latch the data
before assertmg DTACK. Then It WIll negate DBEN- and
DDlR 10 the proper order
(6) After the MPU cycle and the LDS and the UDS arc negated
by the MPU, the DMAC will put DBEN, olYfR and the
address data lInes to a hIgh Impedance state.
(7) DT ACK will once go "Hlgh" and then to a hIgh Impedance
state after negating LDS and UDS.
•
Interrupt Vector Registers (NIV, EIV)
Each channel has a Normal Interrupt Vector regIster and an
Error Interrupt Vector regIster.
When an mterrupt acknowledge cycle occurs, an rnterrupt
vector is outputted from one of those registers If the error bit
(CSR) IS set for the channel wIth rnterrupt pendmg, then content of EIV IS outputted, otherwise content of NIV IS outputted
• OPERATION DESCRIPTION
A DMAC channel operatIon proceeds in three prinCIpal
phases. Dunng the inrtlahzatlon phase, the MPU sets the channel
control regIsters, supply the initial address and the number of
transfer WOlds, and stal ts the channel Dunng the transfel
phase, the DMAC accepts requests for data operand transfers,
and prOVIdes addressmg and bus contlols for the transfers The
termmatlon phase occurs after the operatIOn IS completed.
ThIS sectIOn descnbes DMAC operatIons A descnptlOn of
the MPUjDMAC communrcatlon IS gIVen first Next, the transfer
phase IS covered, mcludmg how the DMAC recognIzes requests
and how the DMAC arranges for data transfer Followrng this,
the mltlahzatron phase is described The termmatlon phase IS
covered, introducrng chainrng, error slgnalrng, and bus exceptrons A descnptron of the channel prioJlty scheme rounds out
the section
AS
~ __ • _ _ _ _ _ _--MJ~w._ _
CS
~.
________--MJ~w......_ _
RW
.IIIor-w..w.__
UDS
~ __________
LDS
~____
DDIR
~w._ _
~.--.--------'_
_ __ ' , _
DBEN
_ _ __flJ--~,- --.J,- .. ---"m\~'\\\
U1
III
AB/Do-A23/D'5
------- --))>-----
XDo-XD,5
(External system data busl
DTACK
---
--------~[r<==:=J}}>_)
- - , i l L '_...llJUT''-----Figure 11 MPU Read from DMAC - Word
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
371
HD68450----------------------------------------------------------------
A,-A'3
FCo-FC,
___
AS
---w.W~
CS
~
R/W
---w.W____
~
__
tUl~__
tw~
UDS
LOS
DDIR
,----- , " ' ' - -_ _ _1J,l
DBEN
,-----
A./Do-A,,/D,s
XDo-XD'5
(External System Data Bus)
'I~
HI
_ _ _ _ _ _ _ _......
[0
ill
10
m
,--
--------C---=====:Jl»>>---({c
-----------««<<<==:J»~~
----~"\L__ _1DT'~--------Figure 12 MPU Wllte to DMAC - Word
Bus Arbitration
The following is the description of the bus arbitration, The DMAC
must obtain the ownership of the bus in order to transfer.
data, Figure 13 1Od,cates the DMAC bus arbitratIOn tlm1Og, It IS
completely compatible with that of HD68000 MPU, The DMAC
asserts the Bus Grant (BG) to request the bus mastership, The
MPU recognizes the request and asserts BG, then it grants the
•
ownership 10 the next bus cycle, After the end of the cunent
cycle (AS IS negated), the MPU relinquIShes the bus to the
DMAC, The DMAC asserts the bus grant acknowledge (BGACK)
to 10dicate that It has the bus ownership, A half clock before
BGACK IS asserted, the DMAC asserts owN. OWN IS kept
asserted for a half clock after BGACK is negated at the end of
the DMA cycle. BR IS negated one clock after BGACK IS
asserted.
elK
-
r-----;
-f
1.5 - ':'5 clocks
2 ...... 3.5 clocks*
~
AeK
o clock"'"
MPU Cycle
("
I
,
OWN
BUS Cycle
II
-J
BG
168000 output)
l!llACK
I
\
II
r-
~.-----f'--
1MPU Cvcle
4.5""" 5 5 clocks
~:=>---@
DMA Cycle
Cy ,,.
max 125 clocks + lMPU Cycle
elK
* ThiS case assumes that no exception condition eXists and DMAC Isn't accessed by MPU
Figure 13 DMAC Bus Arbitration Timing
~HITACHI
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Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (40B) 435-8300
----------------------------------------------------------------HD68450
•
Device/DMAC Communication
CommuflicatlOn between peripheral devIces and the DMAC IS
accomodated by five signal hnes Each channel has REQ, ACK
and PCl, and the last two lines the DONE and DTC hne., are
shared among the four channels
(1) Request (R EQ)
The penpheral devIces assert REQ to request data transfers
Sec the "Requests" sectIOn for detaIls
(2) Acknowledge (ACK)
TIllS hne IS used to Imphcltly address the devIce whIch IS
transfernng the data (11llS devIce IS not selected by address
hnes) It IS also asserted when the content of DAR IS outputted dunng memory-ta-memory l1ansfcr except for the autorequest mode at a limIted Fate or at the maximum rate
(3) Perrpheral Control Line (PCl)
The functIOn of thIS line is qUlte flexIble and IS determmed
by the OCR (DeVIce Control RegIster).
The DTYP bIts of the OCR define what type of devIce
IS on the channel If the DTYP blls are programmed to be a
HMCS6800 devIce, the PCl defmitlOn IS Ignored and the PCl
hne IS an Enable clock (E clock) mpu!. If the DTYP bIts arc programmed to be a device wllh READY, the PCl definrtlOn as
Ignored and the PCl line IS a ready mput.
PCl As a Status Input
The PCl Ime may be proglammed as a status input The
status level of tillS hne can be determmed by the PCS bit 10 the
CSR. regardless of the PCl functIOn determlOed by the OCR
If a negatIve transItIon occurs and remams stable for a minI·
mum of two clocks, the PCT bll of the CSR IS set. ThIS PCT
bIt IS cleared by resettmg the DMAC or the wntlOg "I" to the
PCTblt
PCl As an Interrupt
The PCl line may be programmed to generate an interrupt
on a negatIve tranSItIOn This enables an interrupt which IS requested If the PCT bIt of the CSR IS set When usmg thIS functIOn, It IS necessary to reset the PCT bll 10 the CSR before the
PCl bJt 10 the DCR IS set to mterrupt, 10 order to avoId
assertion of IRQ Ime at thIS hme.
PCl As a Starting Pulse
The PCl hne may be programmed to output a starting pulse
ThIS actIve low starting pulse is outputted when a channel IS
actIvated. and is "low" for a penod of four clock cycles.
PCl As an Abort Input
The PCl Ime may be programmed to be a negative tranSitIOn
above lOput whIch termmates an operatIon by settmg the external abort error 10 CER. It IS necessary to reset the PCT bIt 10
the CSR before activating the channel (Setting the ACT bit of
CCR) so that the channel operahon IS not immediately aborted {See
AttentIOn on Usage, Note (2) J
PCl As an Enable Clock IE Clockllnput
If the DTYP bIts are programmed to be a HD6800 deVIce, the
PCl deflOltIon IS Ignored and the PCL line IS an Enable
Clock input The Enable clock downtime must be as long as five
clock cycles, and must be high for a minimum of three DMAC
clock cycles, but need not be synchronous with the DMAC's
clock
PCl As a READY Input
If the DTYP bits are programmed to be a device with
READY, the PCL definition is ignored and the PeL line is a
READY mput. The READY is an active low input.
(4) DONE (DONE)
This hne is an active low Input/Output signal with an open
drain. It is asserted when the memory transfer count is exhausted in a single block transfer. In the chaining operation,
DONE IS asserted only at the last transfer to the peripheral
deVice of the last data block. In the contmue mode, DONE IS
asserted for each data block. It IS asserted and negated 10 comcldent with the ACK hne for the last data transfer to the
penpheral device It is also outputted 10 comcident WIth the
ACK hne of the last bus cycle, in which the address IS outputted
from the DAR, in the memory-to-memory transfer (dual
addressmg mode) that uses the ACK line
The DMAC also mOflltors the state of the DONE Ime dunng
the DMA bus cycle If the deVIce asserts DoNE dunng ACK
active, the DMAC WIll terminate the operatIOn after the transfer
of the current operand If DONE is asserted on the first byte of
2 byte operation or the first word of long word operatIOn, the
DMAC does not termmate the opera !Jon before the whole operand transfer is completed. If DONE IS asserted, then the DMAC
terminates the operation by cleanng the ACT bIt of the CSR,
and settmg the COC and NDT bIts of the CSR If both the
DMAC and the deVIce assert DONE, the deVIce termmatlOn is
not recognIZed, but the channel operatIOn does termmate.
DONE IS outputted again for the retry exceptIOns bus cycles
(5) Data Transfer Complete (DTC)
DTC is an active low SIgnal which IS asserted when the actual
data transfer IS accomphshed It is also asserted in the bus cycle
whIch read a cham mformation from memory m the Chammg
mode However, If exceptIOns are generated and the DMA bus
cycle teemmates, DTC IS not asserted DTC IS asserted one half
clock before lDS and UDS are negated, and negated one half
clock after lDS and UDS are negated.
•
Requests
Requests may be externally generated by clfcurtry m the
penpheral deVice, or mternally generated by the auto-request
mechanism. The REQG bas of the OCR determme these modes
The DMAC also supports an operatIOn m whIch the DMAC
auto-requests the first transfer and then wait for the peripheral
deVIce to request the following transfers.
(1) Auto-request Transfers
The auto-request mechanism provides generatIOn of requests
WIthin the DMAC. These requests can be generated at ellher of
two rates maximum-rate and lImIted-rate. In the former case.
the channel always has a request pendmg.
The Iimlled rate auto-request functIOns by momtonng the
bus II tIhzatlOn
limited-rate Auto-request
TIME
-7
Previous
Sample Interval
Next
Sample Interval
Figure 14 DMAC Sample Intervals
In the hmlted-rate auto-request the DMAC devldes !Jme mto
equal length sample intervals by counting clock cycles The end
of one sample interval makes the beginmng of the next. Dunng
a sample mterval, the DMAC monitors by means of BGACK pin
the system bus activity of the DMAC and other bus master
devices. At the end of the sample interval, decision is made
whether or not to perform the channel's data transfer during
the next sample mterval. Namely, based on the activIty of
the DMAC or other bus master deVIces dunng the current
sample mterval, the DMAC allows limIted-rate auto-requests for
some initial portion of the next sample interval.
The length of the sample mterval, and the portion of the
sample interval during which limIted-rate auto-requests can be
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
373
HD68450---------------------------------------------------------------made (the limIted-rate auto-request interval) are controlled by
the BT and BR bits in the GCR. The length in clock cycles of
the hmited-rate auto-request interval is 2(BT+4) (2 raISed to the BT +4
power). For example, if BT equals 2 and the DMA uohzation of the bus was low dunng the previous sample interval,
then the DMAC generates the auto-request transfers dunng the
first 64 clock cycles.
The ratIO of the length of the sample interval to the length
of the hmited-rate auto-request interval is controlled by the BR
bIts. The ratIO of the system bus utilizatIOn of the MPU to
other bus master devices includmg the DMAC IS 2(BR+ I) (2 raised to
the BR + 1 power). If the fraction of DMA clock cycles during the
sample interval exceeds the programmed utIlizatIOn level, the DMAC
will not allow limited-rate auto-requests during the next sample
Interval.
For example, If BR equals 3, then at most one out of 16
clock cycles dunng a sample mterval can be used by the DMAC
and other bus master devices, and stIll the DMAC would allow
limIted rate auto-request dunng the next sample mterval.
Therefore, from the viewpoint of long period, the ratIo of the
system bus utilization of the MPU to I/O devices mcluding the
DMAC IS about 16.1. The sample interval length is not a direct
parameter, but it IS equal to 2(BT+BR+5) clock cycles. Thus, the
sample mterval can be programmed between 32 and 2048 clock
cycles.
The DMAC uses the BGACK to differentiate between the
MPU bus cycle and DMAC or other bus master devices. If
BGACK is active, then the DMAC assumes that the bus is used
by a DMAC or other bus master devices. If It is macllve, then
the DMAC assumes that It IS used by the MPU.
Maximum~rate Auto-request
If the REQG bits in the OCR indIcate auto-request at the
maximum rate, the DMAC acquires the bus after the start bit is
set and keeps It until the data transfer is completed.
If a request is made by another channel of hIgher priority,
the DMAC services that channel and then resumes the autorequest sequence. If two or more channels are set to equal
priority level and maximum rate auto-request, then the channels
WIll rotate in a "round robbin" fashion.
If the HD68000 compaoble device IS connected to a channel, the
ACK Ime IS held mactlve during an auto-request operation. Consequently, any channel may be used for the memory-to-memory transfer WIth the auto-request function m addition to the operation of data
transfer between memory and peripheral device WIth usmg the REQ
pm. Refer to FIgure 15 for the oming of the memory-to-memory
transfer. In this mode, the ACK, HIBYTE and DONE outputs are
always mactive.
ClK
1 2 3
~
XIII
FCo-FC2::JD/
A,-A, -:::JJ!:;,,======~Xl~n=======:=;X1-;:,/~7=======~
A /0
Address Out
Data In
Address Out
Data Out
Address Out
A;3/;~~,#1=7====;r:.,~~~/~lr=====~'IIlI::::JI.~II
XDo- XD'5llIllI1)--{///
IExternal System Data ~~~ ~
nnm----
L-
\\\
U/
11/
\\\
\\\
m
\\\
10
\\\
11/
ill
III
\\\
OWN====;~--------mr=========~--------_,n===
DDIR
\\\
10
\\\
DBEN
\\\
ill
\\\
10
orrrr-m
HIBYTE------.:~====~~--~=============-!:!!--~====~~-DTACK
\\\
III
/0
\\\
\1LJD
\\\
\1LJD
ClK
Read One Word
From Memory
Write One Word
to Memory
Read One Word
From Memory
Figure 15 Memory-to·Memory Transfer
Read-Write·Read Cycles
~HITACHI
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Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD68450
(2) External Requests
If the REQG bIlS of the OCR mdicate that the REQ Ime
generates requests, the transfer requests are generated externally. The request Ime assocIated wIth each channel allows the
devIce to externally generate requests for DMA transfers When
the devIce wants an operand transferred, it makes a request by
assertIng the request lIne The external request mode IS determmed by the XRM bIts of the OCR, whIch allows both burst
and cycle steal request modes. The burst request mode allows a
channel to request the transfer of multIple operands usmg
consecutIve bus cycles The cycle steal request mode allows
a channel to request the transfer of a smgle opeland. The
followmgs are the descnptron of the burst and the cycle steal
modes
Burst Request Recognition
In the burst request mode, the REQ Ime IS an actIve low
mput. The level sampled at the nsmg edge of the clock. Once
the burst request IS asserted, It needs to be held low untIl the
first DMA bus cycle starts 10 order to msure at least one data
transfel operation In order to stop the bUlst mode transfer
after the current bus cycle, the REQ Ime has to be negated
one clock before the DTC output clock of tills cycle Refer to
FIgure 16 or the burst mode tmllng.
ClK Jl.JlJlJUlJl..f'l..fUUUUU1JUU1
REQ~~~~~-- ,~--_r~====~~~~~
BG
__
BR __~~~~----~--~
BGACK:::::::;:~~~~~~~::::~~::::~
BUS
CYCLES
ACK
DTC---_-----<
CLK
MPU cycle
-+-
Idle
--t----
DMA cycfe
-+
MPU cycle
or Idle
--r-- DMA cycle --r-
Idle
Figure 16 Burst Mode Request Timing
(Only one channel is active)
Cycle Steal Request Recognition
In the cycle steal request mode, the penpheral deVIce requests the DMA transfer by generatmg an falling edge at the
REQ Ime TI10 REQ Ime needs to be held "low" for at least 2
clock cycles In the cycle steal mode, if the REQ lIne changes
from "HIgh" to "Low" between ACK output and one clock before the clock that outputs DTC, then the next DMA transfer
IS performed WIthout relInqUlshmg the bus If the bus IS not
relInquIshed, then maXUTIum of 5 Idle clocks IS 111serted between
bus cycles. Refer to FIgure 17 for the request tl111111g of the
cycle steal mode. If the XRM bIts speCIfy cycle steal without hold, the DMAC WIll relInquIsh the bus. If the XRM bIts
specify cycle steal WIth hold, the DMAC will retain ownershIp.
The bus is not given up for arbitratIon until the channel opera-
MPU cycle
--+
Idle
+---
tiOn termmates or untIl the deVice pauses. The deVIce IS determmed to have paused If It does not make any requests dunng
the next full sample mterval The sample mterval counter IS free
running and IS not leset or modified by thIs mode of operatIOn
The sample mterval counter IS the same counter that is used for
LImited Rate Auto Request and is programmed via the GCR.
FIgure 18 shows the request tIm 109 in the cycle steal bus
hold If the REQ IS mputted during the hold time, the ACK
IS au tpu tted after a maximum of 7.5 clock cycles from the
pIcked-up clock. On the cycle steal with hold mode, the DMAC
will hold the bus even when the transfer count is exhausted and
the last data has been transferred If DMA transfer is requested
from other channels dunng this penod, they are executed
normally.
micro cleanup
DMA cycle
Figure 17 Cycle Steal Mode Request Timing
~HITACHI
Hitachi Amenca Ltd .• 2210 O'Toole Avenue. San Jose, CA 95131 • (408) 435-8300
375
HD68450--~------------------------------------------------------------
LJ1Jl1'LnJlJlIlrulJ1..n.nn..ruln.JIUlflJ111JlJl.
R~~
'~:
~ '-k.-.J:
CLKJlJl
\. ,.=----_f~
B"G----,
r--"'~--"""":''';'':''~\-=----IIo'- - - - - ~'
'7
:H
Hold the bus
BGACK
BUS
:.-.
-
max 5clocks
- _______ .
max 75,ciOCkS.:
I
CYC.!-~~---~~4~
DTC--,~"
U'
Figure 18 Cycle Steal 8us Hold Mode Request Timing
Request Recognition in Dual·address Transfers
(1) Dual Addressing
In a following section dual-address transfers are defined. Dual
address transfer IS an exception to the request recogmtion rules
m the previous paragraphs. In the cycle steal request mode,
when there are two or more than transfers between the DMAC
and the penpheral device dunng one operand transfer, the request is not recognized until the last transfer between the
DMAC and the I/O device starts.
HD68000 and HD6800 compatIble devices may be explICItly addressed. This means that before the penpheral transfers data, a data
register withIn the devIce must be addressed. Because the address bus
is used to address the penpheral, the data cannot be dIrectly transferred to/from the memory because the memory also requires addressIng. Instead, the data is transferred from the SOUlce to the DMAC and
held In an internal DMAC holdIng regIster. A second bus transfer
(3) Mixed Request Generation
between the DMAC and the destmatIOn IS then reqUIred to complete
the operation Because both the source and destinatIOn of the transfer
A single channel can mIx the two request generatIOn
methods. By programming the REQG bIlS of the OC R to "I I",
when the channel is started, the DMAC auto-requests the first
transfer. Subsequent requests are then generated externally by
the device. The ACK and PCL lines perform their normal functions in this operation.
•
Data Transfers
All DMAC data transfers are assumed to be between memory
and the peripheral device. The word "memory" means a 16-blt
HD68000 bus compatIble devIce. By programmIng the DCR, the
characteristIcs of the penpheral devIce may be assigned. Each channel can commUnicate usmg any of the followmg protocols
DTYP
~
01
10
II
Device Type
HD68000 compatIble devIce
}
HD6800 compatIble devIce
}
DevIce WIth ACK
Device WIth ACK and READY
are expliCItly addressed, thIS protocol IS called dual-addressed.
HD68000 Compatible Device Transfers
In this operatIOn, when a request is received, the bus IS
obtamed and the transfer IS completed using the protocol as
shown in FIgures 19 and 20 F,gures 21 through 24 show the
transfer tImmgs. FIgure 21 and 24 show the operatIOn when
the memory IS the source and the peripheral deVICe is the destination. FIgures 22 and 23 show the transfer In the opposIte
directIOn The penpheral deVIce IS a 16-bn deVIce m F,gures 21
and 22, and a 8-bn deVIce In FIgures 23 and 24.
Dual Addressing
Single Addressmg
~HITACHI
376
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
HD68450
HD68000 Device
DMAC
Address Device
11 Set R/W to Read
2) Place Address on AI ..... An
3) Place Function Codes on
FC o "'" FC 2
4) Assert Address Strobe (AS)
5) Assert Upper Data Strobe
IL1i5S1 and Lower Data
Strobe (LDSI
6) Assert Acknowledge lACK)
I
PreseJt Data
11 Decode Address
2) Place Data on 00 ..... Ou
3) Assert Data Transfer
Acknowledge (DTACKI
I
AcqUire Data
1) Load Data IOto Holdmg
Register
2) Assert DeVice Transfer
Complete (DTCI
31 Negate TIi5S and LDS
41 Negate AS, ACK and DTC
Terminate Cycle
11 Remove Data from Do"'" 015
21 Negate 1J'f'ACK
I
f
Start Next Cycle
Figure 19 Word Read Cycle Flowchart HD68000 Type DeVice
HD68000 Device
DMAC
Address Device
1) Place Address on AI - A33
21 Place Function Codes on
FC o "" Fe,
3) Assert Address Strobe (AS)
Am
41 Set
to Wrtte
5) Place Data on Do
..... DIS
61 Assert Acknowledge (ACKI
7) Assert Upper Data Strobe
(UDS) and Lower Data
Strobe (LDSI
~I------------------------------------~,
Accept Data
1 J Decode Address
21 Store Data on Do -. DIS
31 Assert Data Transfer
Acknowledge (DTACKI
I
f
11
21
31
41
51
Terminate Output Transfer
Assert DeVice Transfer
Complete (DTCI
Negate U5S and LDS
Negat. AS, ACK and DTC
Remove Data from Do ...... DIS
Set RM to Read
I
t
Terminate Cycle
,
11 Negate DTACK
I
Start Next Cycle
Figure 20 Word Write Cycle Flowchart HD68000 Type DeVice
~HITACHI
Hitachi America Ltd, • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
377
HD68450----------------------________________________________________
ClK
As/Do
-A23/D15
XDo-XD15
(External System Data Bus)
UAS
AS
UDS
lOS
RW
OWN
iiDiR
III
\\\
DBEN
\\\
ur
\\\
/0
HIBYTE
~
DTACK
\\\
/0
'ULJl1
llTC
ACK
DONE
ClK
1234567891011121314151617181920212223
Wnte One Word
From Memory
To DeVice
--r----- Read One Word ------t-----
--r-
The Last Transfer
Figure 21 Dual AddresSing Mode, ReadIWnte Cycle,
Destination = 16·bit Device, Word Operand
elK
~~o--------~vmo'-----------~~
-:=J,IO
-A23/ D15
XDo-XD1!>
(External System Data Bus)
UAS
AS
UDS
~
WI
Address Out
As/Do
Data In
Address Out..,....__=-Oa::.:,;:.a.::.O",u',--_
-=:mr::::::Jlrr:.~U~~~'fJJf:=:iJ.~~O~==~'flIC.~
=::JIJ:r-41J.,
11111/)
~
'ULJl1
~/~iI__------~\\~\----~or---
L -____
/0\\\
IlL-_--.-Jor---W
lOS
\W"~__________
RW
urw
OWN
DDIR
DBEN
0/
\\\
\\\
HiBYi'E
m
\\\
ur
ACK
DONE
ClK
------+--- Read One Word - - t - From DeVice
The Last Transfer
Wnte One Word
To Memory
Figure 22 Dual Addressing Mode, ReadIWrite Cycle,
Source = 16·bit Device, Word Operand
~HITACHI
378
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------------HD68450
CLK
As/Do
~A23/D15
XDo-XD15
(External System Data Bus)
UAS
AS
UOS
III
LOS
III
RW
OWN
DDrn
DilEN
ffiliVIT
liTACK
\~'I~-----n~nr-ln~~~~----~a~r--_,n
---1JT\\\
III
III
\\I
\\I
OTC
ACK
CLK
-----t--- Read One Byte -----+---- Read One Byte -------+------- Write One Word
From DeVice
From DeVice
To Memory
Figure 23 Dual AddreSSing Mode, Read/Wnte Cycle
Source = 8-blt DeVice, Word Operand
CLK
Aa/Do
-An/DIs
XDo-XD15
(External System Data Bus)
UAS
AS
Dos
III
[OS
OWN
OOIR
OTACK
0/
- ,
\\I
5llEN
JD
III
III
OJ
~X~
0/
[[JW.
\!.\
RW
m
rrr[JJ
ffT
[[JW.
\\\
\\\
'&.....-JJJ
OTC
ACK
CLK
-+- Read One Word --t--From Memory
Write One Byte
Write One Byte
To DeVice
To DeVice
Figure 24 Dual AddreSSing Mode, Read/Wnte Cycle,
Destination = 8-blt DeVice, Word Operand
~HITACHI
Hitachi America Ltd_ • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
379
HD68450------------------------------------------------------------------HD6800 Compatible Device Transfers
When a channel IS programmed to perform HD6800 compatible
transfers, the PCL hne for that channel is defmed as an Enable clock
mput. The DMAC performs data transfers between Itself and the
penpheral devIce usmg the HD6800 bus protocol, wIth the ACK
output providmg the VMA (valtd memory address) sIgnal FIgure 25
Illustrates thIS protocol Refer to FIgure 26 for the read cycle timmg
and FIgure 27 for the wnte cycle tlmmg. In FIgure 26, the DMAC
latches the data at the falhng edge of clock 19, so a latch to hold the
data IS necessary as shown In Figure 47.
H 06800 Device
OMAC (MASTER)
Initiate Cycle
1) Start a normal Read or Wnte
Cycle
2) Monitor Enable until It IS low
3) Assert Acknowledge (ACK)
I
Aata
Transfer
1) Walt until Enable IS active
2) Transfer the Data
•
Terminate Cycle
1) The master walts until Enable
goes low
2) Assert DeVice Transfer Complete
(oTC)
(On a Read cycle the
data IS latched as clock goes low
when i5TE 15 asserted.)
3) Negate AS, UOS, LOS, ACK
and DTC
~
Start Next Cycle
Figure 25 HD6800 Cycle Flowchart
ClK
Address Out
As/Do
~A23/D15
XDo-XD15
(External System Data Bus)
UAS
Data In
=::JC)Jmmoommmmnmmnllllll
(JOWIIII
AS
UDS
0--
lDS
RW
OWN
DDIR
DBEN
HIBYTE
DTACK
ACK
DTC
PCllE
Clock)
___________\~\============~u---u--_,--=-=----,r
ClK
Figure 26 Dual Addressing Mode, HD6800 Compatible
DeVice, Read Cycle
~HITACHI
380
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD68450
ClK
------~-------------------------~
~8~~~D"
IExtsmal
------~--------------------------~
mmmm
Anotrt=-______. . : :D"'at"'a.: o'-'u: .t_________c..
Systs,:~~~ax~~:) 41~~II~I~t7===I!!'r---
block C
*
DAR
peripheral device address
BAR
top address of the table
MTC
BTC
}
transfer count C
<===:> memor'L..I--------~1
(not used)
address A
'-------------'
transfer count A
block A
memor'!:..~
* to be loaded from the Imked array table
address B
block B
} transfer count B
peripheral
device address
-+
peripheral device
or memory
Figure 38 Transfer Example of the Linked Array Chaining Mode
•
392
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD68450
mode, the BTC IS not used. When the DMAC refers to the linked
array table, the value of the BFC IS outputted as the function
code. The values of the function code regIsters are unchanged
by the hnked array chainmg operation.
ThIS type of chaining allows entnes to be easily removed or
Inserted without havmg to reorganize data wIthin the cham.
Since the end of the chain IS mdlcated by a termmal hnk, the
number of entnes m the array need not be specIfied to the
DMAC.
The hnked array table must start at an even address in the
hnked array chainmg mode. Startmg the table at an odd address
results m an address error. If "0" IS inItIally loaded to the
MTC, the count error IS sIgnaled. Because the MPU can read
all of the DMAC registers, all necessary error recovery mformatlon IS avaIlable to the operatmg system.
The companslOn of both chammg modes IS shown In Table 8.
Table B Chaining Mode Address/Count Information
Chaining Mode
Array Chaining
Base Address
Base Transfer
Register
Counter
address of the
array table
number of data
blocks being
transferred
address of the
Linked Array
Chaining
(unused)
linked array
table
Completed
When
Base Transfer
Count"" 0
Lmked
Address
='
0
(4) Bus Exception Conditions
The DMAC has three hnes for inputtmg bus exception conditIOns called BEC o , BEC I , and BEC,. The priority encoder can
be used to generate these SIgnals externally. These hnes arc
encoded as shown m Table 9.
Table 9
BEC,
BEC I
BEC~
1
1
1
No exception condition
1
1
0
Halt
1
0
0
1
Bus error
0
1
1
1
0
0
0
1
Retry
Relinquish bus and retry
(undefined, reserved)
lundefined, reserved)
0
Reset
1
0
0
0
0
Exception Condition
In order to guarantee, rehable decoding, the DMAC verifies that
the incoming code has been statable for two DMAC clock cycles
before acting on it. The DMAC pIcks up BECo-BEC, at the
rising edge of the clock If BECo-BEC, is asserted to the undefined code, the operation of the DMAC does not proceed.
For example, when the DMAC IS waiting for DTACK, inputtmg
DTACK does not result in the termination of the cycle if BEC oBEC, is asserted to the undefined code. In addItIOn, when the
transfer request is receIved, BR is not asserted if the BEC oBEC, is not set to no exception condition
If exceptIOn conditIOn, except for HALT, is inputted during
the DMA bus cycle prior to, or in coincidence with DTACK,
the DMAC terminates the current channel operation immediately. Here coincident means meeting the same set up reqUIrements for the same samplmg edge of the clock. If a bus exception condition exists, the DMAC does not generate any bus
cycles until it is removed. However, the DMAC still recogmzes
requests.
Halt
The timmg dIagram of halt is shown in FIgure 39. This
dIagram shows halt being generated during a read cycle from the
68000 compatIble devIce In the dual addressmg mode. If the
halt exceptIOn IS asserted dunng a DMA bus cycle, the DMAC
does not terminate the bus cycle ImmedIately. The DMAC
walts for the assertion of DTACK before terminating the
bus cycle so that the bus cycle IS completed normally. In
the halted state, the DMAC puts all the control SIgnals to hIgh
Impedance and relinqUIshes the bus to the MPU. The DMAC
does not output the BR until halt exception is negated. When
halt exception IS negated, the DMAC acquires the bus again and
proceeds the DMA operation. In order to insure a halt exception operation, the BEC lines must be set to halt at least until
the assertion of DTC.
If the DMAC has the bus, but IS not executmg any bus
cycle, the DMAC relInquIShes the bus as soon as halt exception
IS asserted.
~HITACHI
Hitachi America Ltd. • 22tO O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
393
HD68450-------------------------------------------------------------CLK
n..rt.I1.J1J1..i..I1..Il..rU1.
123 4
AID BUS
:=JUII
5 8
1 8 9101112131415161718192021222324252627282930313233
'I/IC::..
}--4~
UAS~~
AS
UDS~~
[J)5~~
R!W
........,
III'l.
~
rmiR
--------------~~~==========
DB£N
- - -....
\\\
OWN
HIBYTE
l>TACK
~~~_ _ _ _ _ _ _ _ _ __w~
1If\.-.4~
-----------,~~r---------
nr-U
\\\
~_ _ _ _ _
ur-
--------~~----r------~
\wU~
HALT
(BECo- BEC2).
BGACK
1m
BG
_ _ _ _ _mm
-----tmu
ur-
~
~.~'--------------------
--------------~~-.~--~------------------------------~'\~_-wm
--------------------~"~~----~
CLK
6
7
8
910111213141516171
Read
from Device
Halt Asserted
19
21222324252627282930313233
Other Bus Master
I
Rear~~t~a~
Wnte
to Memory
---+1 DMA Halted -r-----
DMA cycle
• BEc" - BEC. = (011)
Figure 39 Halt OperatIon
Bus Error
The bus error exception is generated by external circuitry
to Indicate the current transfer cannot be successfully completed and is to be aborted. The recognition of this exception
during a DMAC bus cycle signals the internal bus error condIllon for the channel for whIch the current bus cycle is being
run. As soon as the DMAC recognizes the bus error exception,
the DMAC immediately terminates the bus cycle and proceeds
to the error recovery cycle. In this cycle, the DMAC adjusts the
•
394
values of the MAR, the DAR, the MTC and the 8TC to the
values when the bus error exception occurred. 25 clocks are
reqUired for the error recovery cycle In the sIngle addreSSIng
mode and In the read cycle of the dual addreSSIng mode. 29
clocks are reqUired in the write cycle of the dual addreSSIng
mode. If the DMAC does not have any transfer request In the
other channels after the error recovery cycle, the DMAC rehnqUishes the bus.
The dIagram of the bus error lImIng IS shown In FIgure 40.
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD68450
CLK
AID BUS
UAS
AS
~\U~_ _ _ _.J/J~~
UOS
LOS
J----\\\
R/W
~~
gr-n
\\\
OVVN
OOIR
II
~m----------------------~II-----,~
~mA
OBEN
_____________m~1
'---
HIBYTE
DTACK
"m"m \m \\\\\YfH
--'
OTC
ACK
Bus Error
(lIECo-liECz) •
CLK
--+-
Berr on Write to Dava
I•
I
Error
Recovery Cycle"
Oth.r Chann.I ... •
• BEC,-BEC, • (1011
•• In the lingle addressing mode and In the read cycle of the dual addressing mode. 25 clocks
In the wnte cycle of the dual addreSSing mode' 29 clocks
... The DMAC keeps the bus because the other channels have requests pending. If other channels
do not have requests, the OMAC relinquishes the bus after the error recovery cycle.
FIgure 40 Bus Error OperatIon
Retry
The retry exception causes the DMAC to terminate the
present operation and retry that operation when retry is re-
$
moved, and thus wIll not honor any requests until it IS removed_
However, the DMAC still recognizes requests_ The retry timmg
IS shown in Figure 4 L
HITACHI
Hitachi Amenca Ltd_ • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
395
HD68450----------------------------------------------------------------
m
\\\
A/W
\\\
\\\
/0
i'D
III
III
'ULJIl
m.....JIJ
\\\
'\1\"
~
",-",--
m-
DDIA ==LO:W========================================================
High
eml l---"""""\\\
mHIBYTE ~H~19~h------~==================~--------~============~--D~CK =---1U===~___~\I~\\\~\\~\\~\\\~I\~m~"~\\~\\~\\~\\~\\~\\~\\~\~\\~W~/_____\~\\~==nI~or--rnNN
liB"EN ....:..:;~--....
\\\
~
DTC
or---
/0
\\\
(~!~.-----m ~----~~~~====~~------~==========~~--ACK
CLK
--1---- Wnte to DeVice Retry Asserted - - - - - - \ - - - Wnte Cycle Retry - - f - - - -
. BECo·BEC, =
10011
Figure 41 Retry Operation
Relinquish and Retry (R&RI
The relinquish and retry exception causes the DMAC to
relinqUish the bus and three·state all bus master controls and
when the exception is removed, rearbltrate for the bus to retry
•
396
the prevIous operation.
The diagram of the relinquish and retry timing IS shown
Figure 42.
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
In
-------------------------------------------------------------------HD68450
ClK
AID BUS
nnnnnnnnr~
., 'y' 3'" 5 "r' 7'" 9 'io'"I;r'13'1t,S'rit17 18 192021 22 23 24 25 26 27 28 29 30 31
::::»II
~!--4l1-==
UAS~~
AS~~
UDS~~
lDS~~
\""';-r----'
R/IN
~~~_______________
OWN
\\1iL_ _ _ _---MJIIf\..-1~
DDIR
DBEN
---\\\
,--.....,.~
HIBYTE
--------------------~~~r---------------
DTACK
--.J/I
""",,"',,"\\\\.
ACK
R&R
- -...."
r-
~
>74LS04
...
• 1
....
OWN
G
G
UAS
OE
OE
16
16
16
Q
D
As/Do - A23/D 15
Q~ As - A23
(Addre.. Bus)
74LS373
X2
HD68450
DMAC
+5V,?
~
-!.A
DBEN
DDIR
G
74LS245
B J - . Do-D,
DIR
(Data Bus)
~
A
L..-......
G
74LS245
B~
DIR
Figure 45 An Example of the Demultlplexed Address Data Bus
.HITACHf
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
399
HD68450---------------------------------------------------------------
~1~:::::::D~O::D:,,::::::~---~::~====:_------lk~D:O~D:,,~
~
~
Data & Address
-y
Aa-A23
Bus Interface
F DC
etc'
I--------
i----
k:
1=
~
~
~
t=
MEM &MMU
-
I--- f-----------
AS
f--------. lOS
I-------< ODs
I-------< A/iN
I---
DTACK
:::
-
AS
lOS
UDS
l-
I--
A/iN
I-
1-0
DTACK
VPA
VMA
l-
I-
l-
I-
ll-
II-
E
T
A,-An
)
C ~
C \---
A,-An
MPU
I
-J-
00-0,5
HD68000
00-015
~
l - f.--.
l- f-.
l- f-.
l- f-.
FCo-FC2
I )
3
I-
-r;r
Ene
The address bus and the system control bus
are omitted In thIS Figure.
In
1-0
I-
l-
I-
lL-
each device
Figure 46 An Example of Inter-device Connection
In
the HD68000 System
$
400
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD68450
•
DMAC latches the data when DTC IS asserted and not at the
falhng edge of E clock The 74LS373 need to be proVIded externally as shown In FIgure 47 so that the data from the 6800
devlee can be held on the bus for a large penod of tIme untIl
the DMAC can latch the correct data.
ATTENTION ON USAGE
(11 How to interface various 6800 type peripheral devices to
the DMAC based system.
When the DMAC IS readIng data from the 6800 devlee, the
r--
-r
00-07
00-07
E
6800 Type
W
'--
~~ t---
~
ES
Device
AS
AS
E
00-07
00-07
~
'--
~-g
"u
".
w
w
I----
C)
'-
-:;:~
I-lLI
...J x
RWDATA
¥
'---
a;
!::
f.-
~
:::I
oC)
w
>C)
a;
:::
u.!!:
...... -
PRE.COMPEN}
SATION
IDX/TRKO
-
MFM
WRITE DATA
SEEK COMPLETE
I NDEX
TRACKOOO
MULTI·
PLEXER
a;
rm.
w
READY
WFLT
USELD
RCLK
WCLK
u.
u.
READY
WRITE FAULT
DRIVE SELECTED
:::I
III
VFO·CLOCK
-~
IOSCILLATOR
MFM
READ DATA
a
r--
SCP
STEP
REDUCED
WRITE CURRENT
DIRECTION·IN
-
Figure 3 ST506 Interface Circuit
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
411
HD63463----------------------------------------------------------------
HD63463
r---
BUSR/Wr----I
BUSLIFf
UTAG
TAG5
TAG3
TAG2
TAG1
a:
w
t::
~
r-r-r-r-r--
~
DRIVE
~
UNIT SELECT TAG
TAG 5
TAG 4
TAG 3
TAG 2
TAG 1
~
01-
a:-
I-::J
ZU
or:!:
UU
~r--L--rTl-C~=============:J
BUSo!BUSs
I
I
w
!¢:==:::;;:==!>I.
UNIT SELECT
20 -2 2
- a:
u..
u..
BITO-4
::J
til
BUS.!BUS 9
-
a:
w
>
~
BIT 5 - 9
w
-
a:
-==
a:
Ii
w
>
w
t::::J
-
til
:s
c. -..
~t------I
«
0 .......- - - - - - 1
!;:::J ~ r= .......- - - - - - I
RWDATA .....-----------I"'~ ~ ~ ~I-------t
a: a: I- U 1 - - - - - - - - - 1
rRCLK .......- - - I
WCLK .....- - - I
USELD .......- - - I
SEC .......- - - I
INDEX ......- - - i
a: 1 4 - - - -.......'
w
I
u..
u..
STATUSO-5
READ DATA
READ CLOCK
SERVO CLOCK
WRITE DATA
WRITE CLOCK
UNIT SELECTED
::J
til
+5V--'II\_-t
_
SECTOR
INDEX
OPEN CABLE
DETECT
Figure 4 SMD Interface Circuit
~HITACHI
412
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------------HD63463
SOFTWARE INTERFACE
The HOC is furnished with 22 commands, which are classified
into 6 categories; specification, head positioning, disk access,
data transfer, drive check, and others.
Table 2 List of Commands
Category
Command
Mnemonic
Specifications
Specify
SPC
Head Positiong
Recalibrate
RClB
Seek
SEK
Read Data
RD
Read Erroneous Data
Read ID
RED
RID
Read 10 Skew
RIS
Disk Access
Read 10 - Reads ID areas from specified number of sectors.
Read 10 Skew - Reads ID area of a sector formatted by Write
Format Skew command.
Find 10 - Reads ID areas and stores the data in data buffers.
ID area containing a CRC error is skipped reading, and the
subsequent ID area without any CRC error is searched for.
Check Data - Checks if there is any ECC or CRC error in
DATA area of specified sectors. No data is transferred to data
buffers or to the main memory while checking.
Compare Data - Compares the data in data buffers and the data
read from specified sectors.
Write Data - Writes the data stored in data buffers into DATA
area of specified sectors.
(Note 1)
Find 10
FID
Check Data
CKD
Write Format - For the hard sector, formats a specified number
of sectors starting with a specified physical sector address. For
the soft sector, formats a track.
Compare Data
CMPD
Write Data
WD
Write Format
WFM
Write Format Skew
WFS
Memory to Buffer - Transfers data from the main memory to
the data buffer by DMA transfer.
MTB
Buffer to Memory - Transfers data stored in the data buffer
to the main memory by DMA transfer.
Write Format Skew - Formats a sector specified by a physical
sector address by skewing ID area by 64 bytes.
(Note 1)
Data Transfer
Drive Check
Others
Memory to Buffer
Buffer to Memory
BTM
Open Buffer Write
OPBW
Open Buffer Read
OPBR
Polling
POL
Check Drive
CKV
Abort
ABT
Check ECC
CKE
Polling Disable
POD
Open Buffer Write - Provides initialization of pointer to write
data into the data buffer starting from an address specified by
Pointer Offset. The data buffer is written in the PIO mode after
the command execution ends.
Open Buffer Read - Provides initialization to read the data
stored in the data buffer from an address specified by Pointer
Offset. The data buffer is read in the PIO mode after the command execution ends.
Recall
RCAl
Polling - Monitors drive status including seek end.
Test
TST
Check Drive - Sets result parameters indicating status of a
specified drive to Parameter Block.
(Note 1) Valid only for the hard sector. Disabled for the soft sector.
Abort - Stops all operations being executed by the HOC.
Specify - Specifies the HDC's operation mode, data transfer
mode, etc.
Recalibrate - Moves the drive head to the outermost track
(track 0).
Seek - Moves the drive head onto a track specified by the Next
Cylinder Address.
Read Data - Reads the data of specified sectors and stores it in
the data buffer.
Check ECC - For ECC errors occurred during RD and RED
command execution, reports result parameters indicating addresses and patterns of erroneous data.
Polling Disable - Stops Polling command execution.
Recall - Clears all bits of the status register and sets a buffer
pointer to the start address of parameter block so that command parameters can be accepted.
Test - Makes the output pins of the HOC's drive interface
three-stated.
Read Erroneous Data - Reads disk data and stores it in the data
buffer no matter a CRC error occurs or not in ID area.
@HITACHI
Hitachi America Ltd • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
413
HD63463-----------Table 3 Command Code, Interrupt Request, and DMA Data Transfer
Command Code
Command Name
Interrupt Factor Bits
Binary
HEX
Specify
1110 1000
E8
DMA Transfer
CED
SED
DER
0
DTM = 0
DTM = 1
Recalibrate
1100 1000
C8
0
0
Seek
1100 0000
CO
0
0
0
Read Data
0100 0000
40
0
0
0
0
Read Erroneous Data
0111 0000
70
0
0
0
0
Read ID
0110 0000
60
Read ID Skew
0
0110 1000
0
0
68
0
0
Find ID
01100001
61
0
0
0
Check Data
0100 1000
48
0
0
0
Compare Data
1000 1000
88
0
0
0
0
Write Data
10000111
87
0
0
0
0
Write Format
10100011
A3
Write Format Skew
1010 1011
AB
10
0
0
Memory to Buffer
1001 0000
90
0
0
0
Buffer to Memory
0101 0000
50
0
0
0
Open Buffer Read
0011 0000
30
Open Buffer Write
0011 1000
38
Polling
0001 0000
10
Check Drive
0010 1000
28
Abort
1111 ****
FO-FF
Check ECC
0010 0000
20
Test
11100000
EO
Polling Disable
0001 1000
18
Recall
0000 1000
08
1101 ****
DO-OF
Inhibited
DMA: DIrect Memory Access
0
0
0
0
0
0
\
Y
0: Set at the end of command
execution.
0
"
.
I
0: DMA transfer is performe d.
DTM: Data Transfer Mode
*;
don't care
PROGRAMMING MODEL
Figure 5 shows the internal configuration of the HOC and a
programming model. The HOC internally provides an 8-bit STR
(Status register), an 8-bit CMR (Command register), a l6-byte
PB (parameter Block) and two 256-byte data buffers (DBUFO
and DBUFl). The data can be written to/read from PB, DBUFO
and DBUFI by externally accessing DTR (Data Transfer
register). Their address are specified by a pointer, and is incremented for each access. Internal processors set pointer value,
or select one of PB, DBUFO and DBUFI to be connected to
DTR. These internal processors are initialized by writing a command from the MPU to CMR. The result of command execution
is reflected in the STR.
At the beginning of the command execution, internal processors read command parameters in PB written by the MPU and
determine the command operation mode. At the end of the.
command execution, the MPU reads result parameters in PB
written by internal processors.
When the HDC writes data to a disk, the host system sends disk
write data to DBUF, then internal processors write the contents
of DBUF into the disk. When the HDC reads data from a disk,
internal processors read the contents of the disk and stores them
into DBUF, then the host system reads data from DBUF. The
MPU can access STR, CMR, and DTR while the DMAC can
access only DTR in the single addressing mode.
~HITACHI
414
Hitachi Amerrca Ltd, • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63463
When used in 8-bit mode, the HOC requires 2-byte address
space. One byte (RS (Resister Select signal) = 0) is an 8-bit read
only STR or an 8-bit write only CMR. Another byte (RS = I)
is an 8-bit DTR.
8·bit mode
When used in a 16-bit mode, the HOC requires 2-word address
space. One word (RS =0) consists of an 8-bit CMR and an 8-bit
read only STR. Another word (RS = I) serves as a 16-bit DTR.
16-bit mode
Pins
Pins
RS
R/W
0
1
0
0
1
110
RS
R/W
STR
0
I/O
CMR
1
I/O
7
0
-------
0
87
15
I
STR
-::1
CMR
OTR
1
OTR
STR: Status register (read only)
CMR: Command register (write only for a-bit mode)
I
DTR. Data Transfer register
Programming Model
Internal
($0000 - $OOFF)
processor
H
. .J-..
Address
0000'"1/'
POinter
-
'-------'
OBUFO
(256 bytes)
PB
(16 bytes)
\
Host bus
I
Pack/Unpack
I
11
I
"?-
($8000 - $80FF)
Address
t:J CJ [J
i
Pointer
'--------I
1-
...
.
l::::::::::::::::::::::::::::1 :
OBUF 1
(256 bytes)
Externally accessible register
I
PB: Parameter block
OBUF: Oata buffer
Figure 5
Internal Configuration
Internal Configuration and Programming Model
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
415
HD63463------------------------------------------------------------------When the HOC is either in idle state or command execution end
state, the MPU can access PB by accessing OTR. While the HOC
is executing a command (during data transfer), DBUFO or
DBUFI can be accessed by accessing DTR. Before accessing
DBUFO or OBUFI, the MPU must issue a command to open
the buffer.
STATUS REGISTER
The bit configuration of the Status register is shown in the
figure below, and each bit is described in Table 4.
I
7
BSY
5
6
I CPR I CEO I
3
4
SED
2
I OER I ABN 1
1
0
POL
1" 0 "J
l
l
blank bit
Polling
Abnormal End
Drive Error
Seek End
Command End
Command Parameter Rejection
Busy
Table 4 Status Register Bit Description
Bit
Abbr.
Bit Name
Set "1"
Reset "0"
Condition
Condition
7
BSY
Busy
Command
acknowledged
6
CPR
Command
Parameter
CEO
Command
End
DeSCription
Command executlon end (except
for POL command)
While HOC is executing a command, BSY bit is
set to "1".
Command
RCAL
execution
command
With this bit reset to "0". command parameters
can be written.
Command
execution end
RCAL
Rejection
5
Interrupt
Source Bit
received
command
0
Set to "1" when command shown in table 3
ends. When this bIt IS set, H DC asserts I RQ signal.
received
4
3
SED
OER
Seek End
Drive Error
Drive seek end
detected
RCAL
command
received
0
If detecting dnve seek end during execution of
command shown in table 3, HOC sets "1" in this
bit at the end of command execution.
Drive error
detected
RCAL
command
received
0
If detecting drive error during execution of command shown in table 3, HOC sets "1" in this bit
at the end of command execution.
2
ABN
Abnormal End
Error detected
RCAL
command
received
If acknowledging errors such as Illegal command,
drive faults, data over/under run, the HOC sets "1"
to ABN at the end of command execution. The
SSB contains the error code.
I
POL
Polling
POL command
received
POD command
received, seek
operation end
detected, drive
error detected
Set to "1" during execution of POL command.
0
Blank bit, always set to "0".
0: An interrupt is generated when this bit is set.
~HITACHI
416
Hitachi America LId. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63463
HOC CONTROL PROCEDURE
Some commands do not require either or both of the command
parameter and result parameter. For some commands, the CED
bit, SED bit, or DER bit is set to "I", which enables the HDC
to generate an interrupt request to the MPU.
The MPU's procedure to control the HDC is shown in figure 6.
To control the HDC, the MPU must read STR of the HDC. The
MPU may issue command parameters to PB in the HDC only
when both BSY and CPR bits are cleared.
This enables the HDC to change its status from idle state to
command wait state. Although a data buffer pointer does not
indicate the start address ofPB under command wait state, STR
has the same contents as in the idle state. It is impossible to
distinguish these two internal HDC states externally.
In the DMA (direct memory access) mode, data transfer takes
place between the main memory and the HOC when a disk
access command is received. For this reason, the MPU must
initialize the DMAC before issuing a disk access command to
the HDC. Data such as system memory address and number of
transfer words are written into the DMAC register.
After this, the MPU issues a command. The HDC executes a
command after setting BSY bit to "I". At the end of command
execution, result parameters are stored in PB, the CPR bit is set
to "1", and BSY bit is cleared. Under this condition, the MPU
reads result parameters from PB. Issuing Recall command after
this enables the HOC state to change from command execution
end state to idle state.
When the MPU writes data into internal control register in the
DMAC, the DMAC state changes from the idle state to transfer
(tquest wait state. Upon reception of a transfer request signal
REQ) from the HDC, the DMAC transfers data to/from the
HDC and system memory until specified number of words are
transferred. The DMAC may genemte an interrupt request to
the MPU when the transfer is completed.
OMAC
n
MPU
I]
HOC
I]
BSY-O
CPR=O
~
(
Idle
Idle
.;v--
Issue
command
parameters
~
Transfer
request wait
Command
walt
Issue command
BSY = 1 •
...J..~
... ,.
Transfer data (PIO)
-
Data transfer
;.
Command
execution
(Data transfer)
(OMA)
InterrUP\
Fetch result
parameters
H
BSY=O
CPR = 1
1
End of
command axecution
..!J.
Issue
Recall
command
Figure 6 HOC Control Procedure
•
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
417
HD63463--------------------------------------------------------------__
COMMAND PARAMETERS
Command parameters are listed in Table 5. Command parameters used by the HOC to control ST506 type hard disk drive
are listed in the upper row of each command, and those for the
SMD type in the lower row.
Table 5 Command Parameter (byte organization)
Commands
Parameters
( Upper row: ST506)
lower row: SMD
OMO OM1 OM2 CUl TO/NCH NCl NH NS SHIRL GPll GPl2 GPl3 lCCH lCCl
PCCH PCCl
OMO OM1 OM2 CUl TO/NCH NCl NH NS SHIRL GPll GPl2 RGTlT
Specify
Reca librate
US $00
US $00
Seek
US $00 NCAH NCAl
US $00 NCAH NCAl
Read Data
US PHA
lCAH lCAl lHA lSA SCNTH SCNTl
US PHA $00 FLAG lCAH leAL lHA lSA SCNTH SCNTl
Read Erroneous Data
US PHA
SCNTH SCNTl
US PHA $00 PSA SCNTH SCNTl
Read ID
Read ID Skew (Note 1)
US PHA $00 OFFSET $00 SCNTl
US PHA $00 PSA
$00 SCNTl
Find ID
US PHA $00 OFFSET $00 SCNTl
US PHA $00 PSA
$00 SCNTl
Check Data
US PHA
lCAH lCAl lHA lSA SCNTH SCNTl
US PHA $00 FLAG lCAH lCAl lHA lSA SCNTH SCNTl
Compare Data
US PHA
lCAH lCAl lHA lSA SCNTH SCNTl
US PHA $00 FLAG lCAH lCAl lHA lSA SCNTH SCNTl
Write Data
US PHA
lCAH lCAl lHA lSA SCNTH SCNTl
US PHA $00 FLAG lCAH lCAl lHA lSA SCNTH SCNTl
Write Format
Write Format Skew (Note 1)
US PHA
SCNTH SCNTl
US PHA $00 PSA SCNTH SCNTl
Memory to Buffer
POFFH POFFl
POFFH POFFl
Buffer to Memory
POFFH POFFl
POFFH POFFl
Open Buffer Read
POFFH POFFl
POFFH POFFl
Open Buffer Write
POFFH POFFl
POFFH POFFl
Polling
None
Check Drive
US $00
US $00
Abort
None
Check ECC
None
Test
None
Polling Disable,
None
Recall
--.
(Note 1)
None
Read 10 Skew and Write Format Skew are valid only for SMD Interface.'
~HITACHI
418
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63463
are specified by a bit, and Table 8 lists parameters which are
specified by 3-16 bits.
SPECIFY COMMAND PARAMETERS
Parameters of SPC command may be used to specify the HOC
operation mode and the disk format. Parameters are listed in
Table 6. Contents of these parameters are different according to
which type of drive is used: either ST506 or SMD. Each parameter is described in Tables 7 and 8. Table 7 lists parameters which
The HOC supports soft sector format (in ST506 interface) and
hard sector format (in SMO interface) which are shown in
Figure 7.
Table 6 Specify Command Parameter Organization
oMO
oMl
oM2
SECT
OTM
I
I
MOD
BRST
I
I
OIF
CEOM
3
4
5
6
Bit 7
I
I
PAOP
SEOM
I
I
ECO
OERM
o
2
I
I
CRCP
0
I
I
CRCI
AMEX
1
I
ACOR
PSK
SL (ST506)
"
CUL
1
TO
NCH
NCL
NH
NS
I
SH
RL
GPLl
GPL2
GPL3
LCC High (LCCH)
LCC Low (LCCL)
PCC High (PCCH)
PCC Low (PCCL)
(SMD)
OM2
o
o
o
o
SOFM
SOFP
STBL
STBE
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
419
HD63463------------------------------------------------------------------Table 7 Specify Command Parameters (a)
Abbreviation
*
Name
ST506
SMD
SECT
Sector Organization
0
Soft Sector
Hard Sector
0
1
MOD
Data Modulation
MFM
NRZ
0
1
DIF
Drive Interface
ST506
SMD
0
1
1
PADP
PAD Pattern
$00
$4E
*
0
ECD
Error Check Code
CRC
ECC
*
*
CRCP
CRC Polynomial
X l6 + 1
X l6 + Xl> + X S + 1
*
*
CRCI
CRC Initial Value
$0000
$FFFF
*
*
ACOR
Automatic Correction
Disabled
Enabled
*
*
DTM
Data Transfer Mode
PIO
DMA
*
*
BRST
DMA Burst Mode
Cycle Steal
Burst
*
*
CEDM
Command End Mask
Unmasked
Masked
*
*
SEDM
Seek End Mask
Unmasked
Masked
*
*
DERM
Drive Error Mask
Unmasked
Masked
*
*
AMEX
Address Mark Exclude
Included
Not Included
*
*
PSK
Parallel Seek
Normal
Parallel
*
1
SOFM
Servo Offset Minus
Normal
Minus
None
*
SOFP
Servo Offset Plus
Normal
Plus
None
*
STBL
Strobe Late
Normal
Late
None
*
STBE
Strobe Early
Normal
Early
None
*
ST506
SMD
EIther 0 or 1
Table 8 Specify Command Parameters (b)
Abbreviation
Name
SL
Step Pu Ise Low
8 bits
None
CUL
Connecting Unit List
4 bits
8 bits
TO
Read/Write Time-over
6 bits
6 bits
NC
Number of Cylinders
10 bits
10 bits
NH
Number of Heads
3 bits
5 bits
NS
Number of Sectors
8 bits
8 bits
SH
Step Pulse High
5 bits
None
RL
Record Length
3 bits
3 bits
GPL1
Gap Length 1 (8 bits)
GAP1
HEAD SCAT
GPL2
Gap Length 2 (8 bits)
GPL3
Gap Length 3 (8 bits)
GAP3
LCC
Low Current Cylinder
16 bits
None
PCC
Precompensation Cylinder
16 bits
None
PLO SYNC PLO SYNC
~HITACHI
420
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
RGATE
Latency
Soft Sector Format Supported by H DC
.'
lOX
.J""""'L
ill
(from 2nd sector to N-1th sector)
::c
~
Topsecto
»
3
PLOSYNC
GAP1
"
:!"
I
L
AM LCA LHA S
A
I
I
I
I
CRC
I
PLOSYNC
10 PAD
I
AM OM
,
,
AM OM
DATA
I
ECC
orCRC
DATA
,
I
DATA
PAD
,
Next
Sector
GAP3
,
,
CD
g
GPL1
GPL2
~
$4E
$00
N
~
ct.
o
q
o
CD
•
~l:
CD
Nth (final)
sector
PLO SYNC
AM LCA
_
~ ~
-----
-
L
H
A
L
S
A
CRC
IDPAD
PLOSYNC
ECCor
CRC
DATA
PAD
GAP4
____ L ___
I
00(')
~
<-
~
()
»
~
!!1
1
i
l:
Hard Sector Format Supported by HDC
lOX/SEC
lOX/SEC
S""L
HEAD SCAT
PLOSYNC
S
Y
N
C
P
A
T
.J""""L
S
Y
F
L
A
G
LCA
L
H
A
L
S
A
CRC
10 PAD
PLOSYNC
N
C
P
A
T
DATA
ECCor
CRC
DATA
PAD
END REC
Next
sector
RL
:J:
C
a>
~
~
Figure 7 Disk Format
w
~
a>
w
HD63463---------------------------------------------------------------OMO (Operation Mode 0)
G(x) = (x21 + I)(x ll + x 2 + I)
= X 32 + X23 + X21 + XII + x 2 + 1
(1) SECT (Sector Format) bit
This bit specifies the format of the drive to be connected to
the HDC. There are two drive formats available: hard sector
and soft sector.
SECT = 1: Hard Sector Format
CRC enables error detection, but not error correction. A
2-byte CRC code is added to the end of DATA area. A
generation polynominal G(x) of CRC is specified by the
CRCP bit.
(6) CRCP (CRC Polynominal) bit
This bit determines the polynominal G(x) that generates
eRC of ID and DATA areas when ECD = O.
SECT = 0: Soft Sector Format
(2) MOD (Modulation) bit
This bit specifies modulation mode for data written to/read
from the drive.
CRCP = 1: G(x) = x l6 + Xl2 + X S + 1
CRCP = 0: G(x) = X l6 + 1
MOD = 1: NRZ (Non Return to Zero)
(7) CRCI (CRC Initial) bit
MOD = 0: MEM (Modified FM)
This bit sets the initial value of CRC.
(3) DIF (Drive Interface) bit
CRCI = 1: Initial value = $FFFF
This bit specifies the type of drive interface: either ST506
or SMD. The pin function of the HDC changes according
to the interface type.
CRCI = 0: Initial value = $0000
(8) ACOR (Automatic Correction) bit
This bit selects whether or not the HDC will automatically
correct an error detected in DATA area during RD command execution.
OIF = 1: SMO Interface
OIF = 0: ST506 Interface
In SMD interface, the HDC performs seek instruction, head
specification, drive status check, etc to the drive through
5-bit bi-directional buffer BUSo/BUS s -BUS 4 /BUS 9 •
In ST506 interface, the HDC makes the drive perform seek
operation by issuing step pulses.
(4) PADP (PAD Pattern) bit
This bit specifies the data pattern of PAD area that follows
ID and DATA areas. The value of the PADP bit gives the
data pattern of PAD area that is written into the drive by
WFM or WD command execution.
Hard Sector
Soft Sector
PAOP = 1
Prohibited
$4E
PAOP=O
$00
$00
ACOR = 1: Automatic correction is performed.
ACO R = 0: Automatic correction is not performed.
Automatic correction mode is valid when ECC is specified
as the error check code of DATA area and the sector length
is 256 bytes (RL = $01, ECD = I). For any other cases
specify "0" to the ACOR bit.
OM1 (Operation Mode 1)
(I) DTM (Data Transfer Mode) bit
This bit is used to specify data transfer operation between
the HDC and the main memory during the execution of the
follOWing commands:
RID
RD
RED
WD
RIS
FID
WFS
CMPD
WFM
These commands normally perform transfer between drive
and memory via HDC data buffers. However, it is possible
to cease transfer between the HDC and memory during
these command execution by utilizing DTM bit.
(5) ECD (Error Check Code) bit
This bit specifies the error check code which is added to the
end of the DATA area. CRC code is always specified for the
ID area regardless of ECD bit.
OTM = 1: OMA mode
OTM = 0: PIO mode
ECO = 1: ECC (Error Correction Code)
ECO = 0: CRC (Cyclic Redundancy Check Code)
ECC enables error detection and correction. A 4-byte ECC
code is added '0 the end of DATA area. A generation
polynominal G(x) of ECC is as follows (the initial value is
fixed to "00").
In DMA mode, the HDC performs transfer between drive
and memory via HDC data buffer. In this case, DMA
transfer is performed between the HDC and memory, and
transfer mode is specified by BRST bit.
In PIO mode, the HDC performs transfer between drive and
the HDC. In this case, transfer between the HDC and main
~HITACHI
422
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63463
memory must be supported by the host system using one
of four buffer access commands of the HDC: MTB, BTM,
OPBR, and OPBW.
(2) BRST (DMA Burst) bit
This bit specifies DMA transfer mode of buffer access
commands and drive access commands which perform
transfer between the HDC and the main memory.
(5) PSK (parallel Seek) bit
This bit specifies seek operation mode, and is valid only
in ST506 interface (in SMD interface, PSK must be fixed
to "I"). The HDC specifies step pulse issue timing by
utilizing the value of OM2, SH, and PSK bits.
PSK = 0: Normal Seek mode
PSK = 1: Parallel Seek mode
BRST = 1: Burst mode
BRST = 0: Cycle Steal mode
(3) CEDM, SEDM, DERM bits
CEDM (Command End Mask), SEDM (Seek End Mask),
and DERM (Drive Error Mask) bits specify whether the
IRQ signal is to be asserted or not. CEDM, SEDM, and
DERM correspond to CED (Command End), SED (Seek
End), and DER (Drive Error) bits in STR (Status register).
1: IRQ is masked (not asserted).
0: I RQ is not masked (asserted).
Mask bit
In Normal Seek mode, the HDC issues step pulses in long
cycle (0.1-32 ms). SEK and RCLB command execution
ends when the HDC issues step pulses and then detects
seek end.
In Parallel Seek mode, the HDC issues step pulses in short
cycle (0.5-115 jIS). SEK and RCLB command execution
ends when the HDC issues step pulses. Since the HDC does
not check the seek end, parallel seek operation in multiple
drives is realized by issuing SEK or RCLB command to
these drives. Seek end is to be checked by using POL
command.
OM2 (Operation Mode 2)
This 8-bit register specifies step pulse low width in STS06 interface, and specifies drive control output signal during disk read
command execution in SMD interface.
Corresponding bits in STR
CEDM
CEO
bit 5
SEDM
SED
bit 4
DERM
DER
bit 3
(4) AMEX (Address Mark Excluded) bit .
This bit specifies whether or not the byte-synchronization
pattern marking the beginning of ID area or DATA area
(AM in soft sector, SYNCPAT in hard sector) is to be
included in the CRC or ECC error detection span. The
AMEX bit affects the byte length of ID PAD area and
DATA PAD area.
AM or SYNCPAT
PAD length
AMEX = 1
Excluded
2 bytes
AMEX=O
Included
3 bytes
Seek Mode
In STS06 interface, OM2 indicates SL which specifies step pulse
low width (STPL: Step Pulse Low). Low-speed seek mode
(Normal Seek mode) is selected when PSK = 0, and high-speed
seek mode (parallel Seek mode) is selected when PSK = 1.
Highest seek speed is realized when PSK = I and SL = $FF. The
relation between step pulse low width and SL is shown in the
following Table (see Step Pulse High/Record Length regiSter to
specify step pulse high width).
Step Pulse Low (SL)
STPl (step pulse low)
Sl
Normal seek (PSK = 0)
Parallel seek (PSK = 1)
Sl = $00
STPl = 9B8 ClK
$01 ~Sl~$FE
(1)
(254)
STPl = (Sl - 1) x 1280 + 2364 ClK
(2364 ClK ~ STPl ~ 326204 ClK)
Sl = $FF
Disabled
Sl = $00
STPl= 27ClK
$01 ~Sl~$FE
(1 )
(254)
STPl = Sl x 6 + 28 ClK
(34ClK ~ STPl ~ 1152 ClK)
Sl = $FF
STPl= 5ClK
•
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
423
HD63463-----------------------------------------------------------------
-
-
7
6
5
4
3
2
0
1
J J ..!.
mtO
Drileu
Drive Unit
1
Drive Unit 2
Drive Unit 3
Drive Unit 4
Drive Unit 5
Drive Unit 6
Drive Unit 7
STPL
In SMD interface, OM2 specifies drive control output signal
from the HDC during data read command execution. In data
write command (alI the commands that assert WGATE signal)
and SEK, RCLB command execution, outputs of drive control
signals are low regardless of the contents of OM2. Bits 4-7 in
OM2 are to be set to "0".
SOFM bit: With SOFM = I, the drive head is offset from
the normal position away from the spindle.
SOFP bit: With SOFP
I, the drive head is offset from
the normal pOsition towards the spindle.
STBL bit: With STBL = 1, the data from the drive PLO
data separator is strobed later than usual.
STBE bit: With STBE = 1, the data from the drive PLO
data separator is strobed earlier than usual.
=
7
6
5
4
0
0
0
0
3
2
1
J.
J Str~be
(1) TO (Read/Write Time Over)
The high-order 6 bits in TO/NCH are used to assign the ID
search time: time-over (tover). According to the value of
TO, the HDC sets time-over period as follows.
$01 ~ TO ~ $3F (TO = $00 is prohibited.)
TO x 8 X 10' CLK~tover~(TO+ 1) x 8 X 10' CLK
(2) NC (Number of Cylinders)
The low-order 2 bits of TO/NCH and 8 bits of NCL specify
the number of cylinders (NC). NC is 1023 at a maximum.
Its value is number of cylinders minus 1.
The HDC uses NC to issue NC + 10 step pulses during
RCLB command execution (ST506 interface), or to check
whether or not the command parameter NCA (Next
Cylinder Address) exceeds NC during SEK command
execution.
0
SOFM SOFP STBL STBE
I
TO/NCH, NCL (Read/Write Time Over, Number of Cylinders
High/Low)
NCH and NCL registers specify the number of cylinders in disk
drive, and time-over during disk access command execution.
Early
Strobe Late
Servo Offset Plus
Servo Offset Minus
CUL (Connecting Unit List)
This register stores bit-map information indicating which drive
is connected to the HDC.
15 1 141 13 1 12 ) 11 ) 10
9 ) 8
ReadIWrite Time Over
NCH
71615141312J1)0
Number of Cylinders Low
In STS06 interface, bits 0-3 correspond to drives 0-3 respectively. To connect a drive, write "1" into the corresponding bit
(up to 4 drives can be connected).
7
6
5
4
0
0
0
0
3
2
1
NH (Number of Heads)
This register indicates the number of heads. Its value is to be
number of drive heads minus 1.
0
I I J
Drile1 Unit 0
Drive Unit
Drive Unit 2
Drive Unit 3
In SMD interface, bits 0-7 correspond to drives 0-7 respectively. To connect a drive, write "1" into the corresponding bit (up
to 8 drives can be connected).
•
424
.
Number of Cylinders High
In disk access command execution, the HOC checks whether or
not PHA (Physical Head Address) specified by command parameters exceeds NH. When PHA exceeds NH, the HOC sets IPH
(Invalid Physical Head Address) to result parameter SSB (Sense
Status Byte) and abnormally terminates the execution.
To select a head during multiple track operation in disk access
command execution, the HOC checks whether PHA exceeds NH
or not. When PHA exceeds NH, the HOC sets IPH to SSB and
abnormally terminates the execution .
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63463
In SMD interface, the high-order 5 bits are to be fIXed to
"0",
Number of Heads
-
In ST506 interface, up to 8 heads can be selected ($00
~
-
-
NH ~ $07). Bits 3-7 must be fIXed to "0".
.~
STPL
In 5MB interface, up to 32 heads can be selected ($00 ~ NH
~ $lF). Bits 5-7 must be fIXed to "0".
7
6
5
4
3
2
1
0
0
0
0
2'
2'
2'
2'
2'
STPH (step pulse high)
SH
SH ='
* : don't care
STPH = 2 elK (Note 1)
SH = $00
STPH = 3 elK
$01 ~SH~$lF
(1)
(31)
STPH = SH x 3 + 1 ClK
(4 ClK ~ STPH ~ 94 elK)
(Note 1) Highest-speed seek mode (PSK = 1, SL - $FF)
NS (Number of Sectors)
This register indicates the number of sectors. Its value is number
of sectors/track minus 1 ($00 ~ NS ~ $FE).
(2) RL (Record Length)
The low-order 3-bit SHIRL indicates record length per
sector.
In data read/write command execution, the HDC checks
whether LSA (Logical Sector Address) exceeds NS or not.
In multiple sector operation in data read/write command
execution, the HDC checks whether LSA exceeds NS or not
each time LSA is incremented after one sector operation. If
LSA exceeds NS, the HDC sets "0" to LSA, increments LHA
and PHA, and compares NH and PHA. If NH exceeds PHA, the
HDC executes multiple track operation. IfPHA exceeds NH, thll
HDC sets !PH (Invalid Physical Head Address) to result parameter SSB and abnormally terminates the execution.
Number of Sectors
I
6
I
5
I
4
I
Step Pulse High (SH)
3
2
I
1
I
Record Length
Bit 1
Bit 0
0
0
0
0
0
1
256 bytes
0
1
0
512 bytes
0
1
1
1024 bytes
Inhibited
1
0
0
2048 bytes
1
0
1
4096 bytes
1
1
0
Inhibited
1
1
1
Inhibited
GPl1,2 (Gap Length 1,2)
These registers specify the length of gap and SYNC area in the
sector during WD and WPM command execution.
SHIRL (Step Pulse High/Record length)
7
RL
Bit 2
0
Record length
(Rl)
(1) SH (Step Pulse High)
The high-order 5-bit SHIRL indicates step pulse high width
(STPH: Step Pulse High) in ST506 interface.
GPLl specifies the length of gap areas (GAPl in soft sector,
HEAD SCAT in hard sector) that follow an index or a sector
pulse by byte. It is used for WPM command execution. These
areas are formatted 6 bytes longer than the value set to GPLl
during the command execution. [$00 ~ GPLl ~ $FF]
7
STPH is fIXed to 2CLK in highest speed seek mode (pSK
= 1 and SL =$FF). Otherwise, SH sets STPH regardless of
the PSK bit. The relation between STPH and SH is shown
in the following table. SH is ignored when maximum speed
seek mode is selected in ST506 interface.
o
6
Gap length 1
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
425
HD63463---------------------------------------------------------------GPL2 specifies the length of SYNC area located at the beginning of ID and DATA areas by byte. It is used for WD and
WFM commands. This area is formatted 3 bytes longer than the
value set to GPL2 during the command execution. [$08 ~
GPL2~$FF)
7
5
6
4
2
3
Gap Length 2
PCC (Precompensation Cylinder)
This register specifies the address of the outermost cylinder
from where compensation of the bit data timing is required.
This is valid only in ST506 interface. When a disk write command is executed to any cylinder whose address is equal to or
greater than PCC, either EARLY or LATE signal is generated
in accordance with the bit data timing. [$0000 ~ PCC ~ NCj
15 114
I 13
112 111
I 10 I
9
I
8
Pre-compensation Cylinder High
GPL3/RGTLT (Gap L~ngth 3, Read Gate Latency)
GPL3/RGTLT specifies the length of GAP3 for the soft sector
and read gate latency delay for the hard sector by byte.
Pre-compensation Cylinder Low
GPL3 specifies the length of GAP3 located at the end of a
sector in soft sector format by byte. It is used for WFM command. This area is formatted 3 bytes longer than the value set
to GPL3. [$09 ~ GPL3 ~ $FF)
2
RGTLT specifies the time period between the detection of an
index or a sector pulse and the assertion of RGATE in unit of
byte. It is used for disk read commands. RGATE is asserted 5
bytes later than the value set to RGTLT. RGTLT must be set
to assert RGATE at the beginning of or before PLO SYNC area
in the ID field. During RlS command execution, 64 bytes are
added to the amount of latency automatically. [$00 ~ RGTLT
~$FF)
16 J
5
I
4
1 3
1 2 J 11
0
RGATE Latency
LCCH, LCCL (Low Current Cylinder High/Low)
For the inner cylinders of the drive, it is necessary to reduce
write current during WFM and WD command execution. These
registers specify address of the outermost cylinder from where
write current is reduced. This is valid only in ST506 interface.
When a disk write command is executed to any cylinder whose
address is equal to or greater than LCC, the HDC asserts the
LCT pin to high. [$0000 ~ LCC ~ NC (Number of Cylinders))
15
I 14 I 13 I 12 I 11 I 10 I 9 I
8
OTHER COMMAND PARAMETERS
The following describes command parameters other than SPC
command parameters in alphabetical order.
(I) FLAG
This parameter is used to specify the FLAG byte of ID area
of a hard sector that the HOC will access. If the FLAG
given by the command parameter does not match the
FLAG read from ID area of the disk, the HDC will not
access the sector.
(2) LCA (Logical Cylinder Address)
This parameter is used to specify the logical cylinder address of ID area (16 bits: the high-order 8 bits for LCAH
and the low-order 8 bits for LCAL) of a sector that the
HDC will access. If LCA given by the command parameter
does not match LCA read from ID area, the HOC will not
access the sector. In soft sector format, it is prohibited to
specify $F8 to the high-order 8 bits (LCAH).
(3) LHA (Logical Head Address)
LHA is used to specify the logical head address of ID area
of a sector that the HOC will access. If LHA given by the
command parameter does not match the LHA read from ID
area, the HDC will not access that sector. In multiple track
operation, LHA is automatically incremented by one. Since
LHA is logical, it may exceed the number specified by the
parameter NH (number of heads).
(4) LSA (Logical Sector Address)
LSA is used to specify the logical sector address of ID area
that the HDC will access. If LSA given by the command
parameter does not match LSA read from ID area, the HOC
will not access the sector. In multiple sector operation, LSA
is automatically incremented by one. Since LSA is
compared with the control register NS (number of sectors)
for switching of heads, the LSA must not exceed the NS.
Low Current Cylinder High
Low Current Cylinder Low
(5) NCA (Next Cylinder Address)
This parameter is used to specify the physical address (10
bits) of a cylinder to which the head will move when a SEK
command is issued. The outermost cylinder address is
$0000. The high-order 8 bits of NCA are used for NCAH
and the low-order 8 bits for NCAL. The high-order 6 bits
of NCAH must be fixed to "0". If NCA exceeds NC, com-
~HITACHI
426
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------------HD63463
mand execution abnormally terminates.
(6) OFFSET
OFFSET specifies how many sectors to be skipped reading
after an index pulse. Then the HOC reads ID fields, and
stores them into the data buffer.
(7) PHA (Physical Head Address)
The MPU specifies PHA when issuing a disk access command. Unlike LHA, PHA is physical, and the bit status of
PHA is directly output as HSEL signals. The high-order 5
bits of PHA must be fixed to "0" for ST506 interface, and
the high-order 3 bits for SMD interface. In multiple track
operation, PHA is automatically incremented by one within the HOC if another head switching is required. If PHA
exceeds the value given by NH, the command execution
will abnormally terminate.
(8) POFF (pointer Offset)
The MPU specifies a transfer start address (16 bits) when
issuing a command for accessing the data buffer. The MSB
of the high-order 8 bits (POFFH) selects one of two data
buffers, and the remaining 7 bits must be fixed to "0".
The low-order 8 bits (POFFL) specifies a transfer start
address of the selected data buffer (256 bytes). For the
16-bit data bus, POFF is limited to an even address only.
(9) PSA (Physical Sector Address)
This parameter is used to specify a physical address of a
hard sector at which the execution of RID, RIS, FID,
WFM, or WFS starts. If PSA is $00, the sector following an
index pulse is specified.
(10) SCNT (Sector Count)
This parameter is used to specify the number of sectors
(16 bits) that the HOC will continuously access in a disk
access command execution. Upper 8 bits are SCNTH, and
lower 8 bits are SCNTL. Up to 1024 sectors are specified
in ST506 interface (128 sectors x 8 heads), and up to 8160
sectors are specifiable in SMD interface (255 sectors x 32
heads). For commands relating to the ID (RID and WFM),
they perform no multiple track operation. In addition,
maximum number of sectors that can be formatted at
time by WFM command is 128 for soft sector, and 102 for
hard sector.
a
(11) US (Unit Select)
The MPU specifies the address (8 bits) of a target drive
when issuing a head positioning, disk access or drive check
command. The contents of US are directly output from
USEL signals. The high-order 6 bits of US must be fixed to
"0" for ST506 interface, and the high-order 5 bits for SMD
interface. US is the high-order 8 bits of a 16-bit word, and
the low-order 8 bits of the word are PHA or $00. It is not
necessary to issue $00 to the low-order 8 bits when CKV or
RCLB command is issued.
RESULT PARAMETERS
Result parameters are listed in Table 9. In this table, result
parameters used by the HOC to control STS06 type hard disk
drive are found in the upper row of each command, and those
for SMD type in the lower row.
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
427
HD63463---------------------------------------------------------------Table 9 Result Parameters (Byte-organized)
Command
Parameter
(Upper row: ST506)
lower row: SMD
Recalibrate
$00 SSB US VUl
$00 SSB US VUl
Specify
($00 SSB)
($00 SSB)
Seek
$00 SSB US VUl
$00 SSB US VUl
Read Data
$00 SSB US PHA
$00 SSB US PHA $00 FLAG
lCAH lCAl lHA lSA SCNTH SCNTl
lCAH lCAl lHA lSA SCNTH SCNTl
Read Erroneous Data
$00 SSB US PHA
$00 SSB US PHA $00 PSA
SCNTH SCNTl
SCNTH SCNTl
Read ID
Read ID Skew
$00 SSB US PHA
$00 SSB US PHA $00 PSA
$00 SCNTl
$00 SCNTl
$00 SSB US PHA
$00 SSB US PHA $00 PSA
$00 SCNTl
$00 SCNTl
Check Data
$00 SSB US PHA
$00 SSB US PHA $00 FLAG
lCAH lCAl lHA lSA SCNTH SCNTl
lCAH lCAl lHA lSA SCNTH SCNTl
Compare Data
$00 SSB US PHA
$00 SSB US PHA $00 FLAG
lCAH lCAl lHA lSA SCNTH SCNTl
lCAH lCAl lHA lSA SCNTH SCNTl
Write Data
$00 SSB US PHA
$00 SSB US PHA $00 FLAG
lCAH lCAl lHA lSA SCNTH SCNTl
lCAH lCAl lHA lSA SCNTH SCNTl
Write Format
Write Format Skew (Note 1)
$00 SSB US PHA
$00 SSB US PHA $00 PSA
SCNTH SCNTl
SCNTH SCNTl
Memory to Buffer
($00 SSB)
($00 SSB)
Buffer to Memory
($00 SSBI
($00 SSB)
Open Buffer Read
($00 SSB)
($00 SSB)
Open Buffer Write
($00 SSB)
($00 SSB)
Polling
$00 SSB US VUl
$00 SSB US VUl
Check Drive
$00 SSB US $00 DSTO $00
$00 SSB US $00 DSTO DSTl DST2 DST3
Abort
$00 SSB
(Note 1)
Find ID
$00 SSB
Check ECC
Test
$00 SSB EAO EA 1 EPO EPl EP2 $00
$00 SSB EAO EAl EPO EPI EP2 $00
($00 SSB)
($00 SSB)
Polling Disable
($00 SSB US VUl)
($00 SSB US VUl)
Recall
($00 SSB US VUl)
($00 SSB US VUl)
(Note 1) Read ID Skew and Wnte Format Skew are valid only for SMO.
(Note 2) ParenthesIzed parameters are reported when a command IS ISsIJed--I-mder the Illegal condition.
@HITACHI
428
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63463
DST (Drive Status)
Table 10 Drive List (DST)
Bit
ST506
DSTO
DSTO
DSTl
SMD
DST2
DST3
7
6
5
READY
SCP
TRKO
·
·
·
·
·
·
·
·
.
4
3
2
1
0
WFlT
0
0
0
0
WPRT
FlT
SKERR
OCYl
URDY
SElER
WERR3
WERR2
WERRl
SERR2
SERRl
SAD32
SAD16
SAD8
SAD4
SAD 2
SAD 1
DTP32
DTP16
DTP8
DTP4
DTP2
DTPl
• Depends on the stete of BUS,/BUS, - BUS,/BUS•.
(11) for DST bits indicating error status.
Each bit of DST indicates drive interface input signal level.
DSTO (I byte) is reported in STS06 interface, and DSTO-3
(4 bytes) are reported in SMD interface.
(S) WPRT (Write Protected)
This bit indicates that a selected drive is write protected.
In STS06 interface, the WFLT bit in DSTO indicates the signal
level of WFLT pin. Even if WFLT signal is momentarily
asserted, the internal latch memorizes this and reflects its state
on WFLT bit. When WFLT signal is negated, the latch read
operation by the HOC clears this latch.
(6) SERRI (Status Error I)
(7) SERR2 (Status Error 2)
(8) WERRI (Write Error I)
In SMD interface, the HOC reads 8 bits by 4 words of the
drive status signal which is selected by signals TAG2 and TAGS.
TAG2
TAG5
o
o
o
o
r
(9) WERR2 (Write Error 2)
(10) WERR3 (Write Error 3)
Status
DSTO
(11) SELER (Select Error)
DSTl
(12) SADI-32 (Sector Address)
DST2
(13) DTPI-32 (Drive Type)
DST3
EA (Error Address)
Following (I) through (S) are read during CKV command
execution and checked during disk access command execution.
DSTl through DST3 are referred to during CKV command
execution.
Status that each bit in DSTl-3 indicates may vary according to
the drive connected to the HOC. Following descriptions indicate
DST bit function when the HOC is connected to a Hitachi 8"
disk drive, DK-812S.
(1) URDY (Unit Ready)
This bit indicates that a selected drive is in ready state.
Reports the start address (16 bits) of a byte from where the
burst error that is detected during CKE command execution
exists. The high-order 8 bits are EAO, and the low-order 8 bits
are EAI. As the HOC corrects up to II bits of burst error, the
MPU corrects contiguous 3 bytes starting from a byte specified
by EA. EA = $0000 indicates a start address of sector data.
EP (Error Pattern)
Reports EPO, EPI, and EP2 as the pattern required for error
correction as a result of CKE command execution. The MPU
exc1usive-OR 3-byte data containing errors with EPO, BPI, and
EP2.
FLAG (Flag)
(2) OCYL (On Cylinder)
This bit indicates that a head is positioned correctly on a
track.
Reports the same value as FLAG specified by command
parameters.
(3) SKERR (Seek Error)
This bit indicates that errors have been detected in a drive
during seek operation.
Reports the same value as LCA specified b}' command
parameters.
(4) FLT (Fault)
This bit indicates that errors relevant to disk access have
been detected in the drive. Result parameter DSTl
indicates what type of error has occurred. See (6) through
Bit organization of LHA is the same as that of the command
parameter LHA. In multiple track operation, LHA is incremented by one each time access to one track ends.
leA (logical Cylinder Address)
lHA (logical Head Address)
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
429
HD63463---------------------------------------------------------------SCNT reaches "0" , command execution normally terminates.
LSA (Logical Sector Addresst
Bit organization of LSA is the same as that of the command
parameter LSA. In multiple sector operation, LSA is incremented by one each time access to one sector ends.
SSB (Sense Status Bytet
This is the area where 8-bit error code is set ($00 is set for
normal termination). There are 25 error codes which notify
what kind of error has occurred during the command execution
(See Tables 11-14).
PHA (Physical Head Addresst
Bit organization of PHA is the same as that of the command
parameter PHA. In multiple track operation, PHA is incremented by one each time access to one track ends.
US (Unit Selectt
Reports the same value as US specified by command parameters.
PSA (Physical Sector Addresst
Bit organization of PSA is the same as that of the command
parameter PSA. In multiple sector operation, PSA is incremented by one each time access to one sector ends.
SCNT (Sector Cound
Bit organization of SCNT is the same as that of the command
parameter SCNT. In multiple sector operation, SCNT is decremented by one each time access to one sector ends. When
VUL (Valid Unit Lisd
VUL is a bit-mapped list which gives the address of a drive that
is ready to accept a head positioning or a disk access command.
Its bit organization is the same as that of CUL. This bit is set
when seek operation in the drive is terminated, or when SPC
command is executed. This bit is reset when seek operation
starts, when drive error occurs, or when the bit in CUL corresponding to the drive is not set to "I" .
Table 11 Error Codes Relevant to Host Interface
Mnemonic
ABT
Name
Command Aborted
Contents
Error Code
04
ABT command has been accepted.
IVC
Invalid Command
08
An invalid command has been accepted.
PER
Parameter Error
DC
The command parameter has not been stored in an appropriate area in PB.
NIN
Not Initialized
10
Head positioning, disk access, and drive check commands
have been accepted, before SPC command is executed.
RTS
Rejected Test
14
The TST command is received after SPC command has been
received.
Table 12 Error Codes Relevant to Drives
Mnemonic
Name
Contents
Error Code
NUS
No USELD
18
USELD signal for a selected drive has not been returned.
WFL
Write Fault
1C
WFL Tsignal (ST506 interface) or FL Tsignal (SMD
interfacet has been detected.
NRY
Not Ready
20
READY signal has been negated.
Table 13 Error Codes Relevant to Head Positioning Commands
Mnemonic
Name
Contents
Error Code
NSC
NoSCP
24
SCP signal (ST506 interfacet or the SKEND signal (SMD
interfacet has not been returned in a certain period.
ISE
In Seek
28
SE K, or a disk access command has been issued for a drive
in seek operation.
INC
Invalid NCA
2C
NCA (Next Cylinder Address) greater than NC (number of
cylinders) has been specified.
ISR
Invalid Step Rate
30
The highest-speed seek has been specified in the normal
seek mode.
SKE
Seek Error
34
SEK or a disk access command has been issued to a drive
which is in seek error state (SMD only).
~HITACHI
430
Hitachi Amenca Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------------------HD63463
Table 14 Error Codes Relevant to Disk Read/Write Commands
Mnemonic
Name
Contents
Error Code
Over Run
38
A transfer between the main memory and data buffers has
not caught up with a transfer between a drive and data
buffers.
IPH
Invalid PHA
3C
PHA (Physical Head Address) greater than NH (Number of
Heads) has been specified.
DEE
DATA Field ECC Error
40
A data error has been detected by ECC (Error Correction
Code).
DCE
DATA Field CRC Error
44
A CRC (Cyclic Redundancy Check Code) error has occurred
in DATA area.
ECR
Error Corrected
48
An ECC error detected in DATA area has been
automatically corrected.
OVR
DFE
DATA Field Fatal Error
4C
A fatal ECC error has occurred in DATA area.
NDA
No DATA AM
60
The address mark in DATA area has not been detected.
NHT
Not Hit
50
In CMPD command execution, data from the host and disk
data have not coincided with each other.
ID Field CRC Error
54
A CRC error in ID area has been detected in RID
command execution in SMD interface.
TOV
Time Over
58
ID has not been found in the period specified by TO (Time
Over).
NIA
No ID AM
5C
The ID area that begins with improper address mark has been
detected.
NWR
Not Writable
64
WD command has been issued to a drive where the write
protect signal is asserted (SMD interface)
ICE
CONTROL SEQUENCE FOR ST506 TYPE DRIVE
DISK READ
The ID search timing for RD or WD command execution is
shown in Figure 27. (a) is the timing where AM is found. SYNC
signal is negated 4-bit period (on the basis of disk data) after
CRC pattern of ID area is completed. After reading CRC, the
HDC switches the clock in the satellite processor from RCLK to
WCLK and then negates SYNC signal.
RCLK and WCLK clock signals are independent each other. To
remove the hazard during switching, the switching signal and the
clock signal must be synchronized. Therefore, SYNC is normally
negated 4-bit period after reading CRC to switch the clock in
the satellite processor from RCLK to WCLK.
RGATE signal is usually negated 4-bit period after SYNC signal
is negated, and then asserted again one to two-byte period later
to read SYNC area preceding DATA area. RGATE is asserted
for l-byte period when the AMEX bit is set to "I" during SPC
command execution, and for 2-byte period when set to "0".
When AM is not found as shown in (b), the HOC searches for
AM again by negating both SYNC and RGATE signals. RGATE
signal is usually negated 4-bit period after SYNC signal is
negated, and is negated for 2-byte period.
As the MFM is specified during SPC command execution, the
frequency of clock signals synchronizing with disk data (such as
RCLK, WCLK) is doubled compared to the data transfer rate.
Therefore, "4-bit period" or "I-byte period" description is
formally expressed as "8 WCLK cycles" or "16 WCLK cycles"
respectively.
After reading DATA area and ECC or CRC area by RD command execution, RGATE and SYNC signals are negated in the
same timing as they are negated after reading ID CRC area (see
Figure 27 (a)).
DISK WRITE
The timing of WeATE signal for WD command execution is
shown in Figure 28. The HDC negates ReATE signal after
reading ID area. Then WeATE signal is asserted 1 or 2-byte
period after ReATE is negated (2-byte when AMEX specified by
SPC command is at "0", I-byte when AMEX is at "1"). WeATE
signal is negated immediately after PAD of DATA field ends.
The relation between IDX signal and weATE signal during
WFM command execution is shown in Figure 29. weATE
signal rises almost simultaneously with IDX signal (refer to electrical characteristics), and falls 3-byte or 4-byte period after IDX
signal rises. The condition of EARLY and LATE signal generation is shown in Figure 8.
HEAD POSITIONING
The relation between DIR, STEP, and SEEK signals is shown in
Figure 30. The unit is the number of CLK cycles (tcyc).
When 8 MHz clock signal is supplied to CLK, STEP Signal is
output at least 33.8 J.l.S after DIR signal becomes valid.
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
431
HD63463-------------------------------------------------------------Data
RWDATA
EARLY
,
,,,
I,
,,,
I
n
v=F\
J
I
I
I
Data bit
Data
I
,
I
0
I
I,
,,I
I
,I
,
,
,,
\
,
,:
I
LATE
,I
J
,
I
:
0
I
0
,
RWDATA
EARLY
Data
I
I
I
I
I
1
0
,
,
,I
0
,
,, 0¥>
I
I
I
'[
I
,
,
,
,,
I
JL
,,I \
I
1
I
1
1
0
,
,
,,
,,
I
I
LATE
I
,
,
1
RWRLY
I
I
I
:[
I
Clock bit
,
1#\
,,
I
,,
,
I
I
\
I
I
*
IlJ,
,
I
I
Data
I
I
r¥>:,,
,,
*
I
I
RWDATA
:
:
,,,
0
,,,
,
,
,I
1
0
1""'L-
I \
I
,,
,
Figure 8 Write Precompensation
CONTROL SEQUENCE FOR SMD TYPE DRIVE
DRIVE SELECTION, STATUS CHECK, FAULT CLEAR
The HOC performs drive selection, status check, and Fault
Clear, for all disk control command execution. Figure 35
shows the drive selection timing. The drive receives BUS o/BUS s
-BUS 4 /BUS. from the HOC and latches them using UTAG
signal. If the drive judges that its own drive number is specified,
it returns USELD signal within 9 CLK after the detection of
UTAG signal. Figure 36 shows the drive status check sequence.
The HOC changes the direction of BUS o /BUS s -BUS 4 /BUS.
before reading the status. Then the HOC sets BUSL!H signal to
high, therefore, the external circuit of the HDC can supply drive
status signal to the HOC during this period. At this time,
BUSL!H is in high, and lower 5 bits are input to the HOC.
The HDC resets FLT after reading the drive status which
includes Fault, and the timing is shown in Figure 37. To set the
high -order 5 bits of BUS outputs to low, the HOC sets BUSo/
BUS s -BUS 4 /BUS 9 to low, and asserts TAG3 signal with
maintaining BUSL!H in low. In external circuits of the HDC,
BUSo/BUS s -BUS 4 /BUS. is latched by using TAG3 signal as a
strobe signal. If BUSL!H is in low, external circuits must be
used not to supply TAG3 signal of the HDC to the drive. Then,
the HDC outputs the low·order 5-bit information to BUS o/
BUSs - BUS 4 /BUS., sets BUSL!R signal to high, and asserts
TAG3 signal. The external circuits provide the drive with above
mentioned 5-bit latch outputs, the low-order 5-bit outputs on
BUSo/BUSs -BUS 4 /BUS., and TAG3. In Fault Clear, BUSL/R
signal is in high, and only BUS 4 /BUS. is in high.
Head selection is performed by disk access commands. Figure
40 shows the head selection timing. Upper 5 bits are in low,
and the head address is supplied from the low-order 5 bits of
BUS. At this time, TAG2 signal is used as a strobe signal.
Further, in the execution of disk access command group, the
HDC asserts TAG3 and generates RGATE or WGATE signal:
Figures 41, 42 and 43 show the total sequence. When TAG3 is
asserted, the high-order 5 bits of BUS output Strobe Early/
Late and RTZ (it is not used for disk access). Then, the HOC
outputs the low-order 5 bits. Servo offset is specified in figure
42. When TAG3 is asserted along with BUS2 /BUS 7 or BUS,/
BUSs, servo offset is performed in the drive. Therefore, the
head is moved and the HOC waits until SKEND signal is returned from the drive. Then, the HOC asserts BUS! /BUS 6 and
supplies RGATE signal to the drive to perform the read
operation.
Figure 43 shows assert/negate timing of RGATE and WGATE
signals which correspond to the disk format. During disk access
command or ID read command execution, RGATE signal is
~HITACHI
432
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63463
asserted after a time period corresponding to byte count of disk
data has elapsed since IDX or SEC signal is detected. After reading CRC, the HOC itself switches the clock to WCLK signal,
then negates RGATE signal with a typical delay time equivalent
to 8 bits of disk data.
To read the data field, the HOC asserts RGATE again with a
dwell time of 1-2 bytes period. RGATE is negated for I-byte
period when AMEX bit is set to "I" during SPC command execution, and 2-byte period when AMEX bit is set to "0". The
HOC negates RGATE signal 8-bit period after reading CRC or
ECC in data field.
To write the DATA field, the HDC reads ID area and asserts
WGATE signal 1-2 bytes period after RGATE signal is negated.
WGATE signal is to be negated when DATA PAD ends. During
WFM command execution, WGATE signal rises in the same
timing as IDX signal, and is negated 3-4 bytes period after IDX
or SEC signal is detected.
Figure 38 shows the execution timing of RCLB command. RTZ
instruction is supplied to the drive through BUS, /BUS 6 and
TAG3. Figure 39 shows the execution timing of SEK command.
10-bit cylinder address is output through BUSo/BUSs -BUS 4 /
BUS.,S bits at a time. Strobe signal is TAGI at this time.
Figures 44,45,46 and 47 shows the execution timing of CKV
command. The HDC reads 8-bit drive status through BUSo/
BUS s -BUS 4 /BUS.,3 bits first and then 5 bits. Then the HOC
reads status four times by switching TAG2 and TAGS signals.
Switching order is: [TAG2 = 0, TAGS = 1], [TAG2 =0, TAGS
= I], [TAG2 = 1, TAGS =0], [TAG2 = I, TAGS = I].
execution abnormally terminates when erroneous data is
detected during any command execution. Then $40 is set to
SSB when an error is correctable, $4C when not correctable.
When DTM = I, the HOC sends I·sector data including an error
during RD or RED command execution and then abnormally
terminates the command execution. After confirming that $40
is set to SSB, the host issues CKE command to the HOC.
When DTM = 0, the HOC abnormally terminates the command
execution after I·sector data including an error is stored in the
data buffer during RD or RED command execution. After confirming that $40 is set to SSB, the host issues BTM command to
the HDC after DMAC's initialization, or, issues OPBR command
and reads data buffers using move and load instructions and
then stores buffer data to the main memory. Then, the host
issues CKE command to the HDC.
Receiving CKE command, the HDC calculates an error address
(EA) and an error pattern (EP), and then sends result parameters to the host. The erroneous data exists in three contiguous
bytes of the corresponding sector in main memory. EA indicates
start address of this 3-byte area ($0000 indicates a start address
of sector data). The host exclusive-OR the 3-byte area and EP
to correct erroneous data.
The host judges CKE command execution end from status
change of BSY bit from "I" to "0". When SSB is $4C, CKE
command issue is prohibited as it causes the erroneous
operation of the HOC. Even if errors are reported to be correctable (SSB = $40) during RD or RED command execution
and the host issues CKE command, these errors may turn out
to be not correctable after CKE command execution.
COMMON CONTROL
DMA DATA TRANSFER
The control which is common to both ST506 and SMD interfaces is described in this section.
AUTOMATIC CORRECTION
In SPC command execution, the HOC operates in automatic
correction mode if the host sets both ECD and ACOR bits in
OMO to "1". If a sector with correctable errors is detected, the
erroneous data is corrected in data buffers. Automatic correction is normally performed only when the sector length is
256 bytes. Specification of the automatic correction mode is
prohibited when the sector length is longer than 512 bytes
because it causes the erroneous operation of the HOC.
If DTM (Data Transfer Mode) bit in OMO is set to "I" as well
as ECD and ACOR bits during SPC command execution, the
HOC transfers the corrected data to the main memory in DMA
mode after the automatic correction. Then, the command
execution abnormally terminates. When DTM = 0, the command
execution abnormally terminates after the automatic correction
and data transfer is not performed. If the HOC finds the data
uncorrectable, the command execution abnormally terminates
without data transfer regardless of the state of DTM bit.
CORRECTION BY HOST
The host corrects erroneous data detected during RD command
execution when it sets ECD and ACOR bits in OMO to "I" and
"0" respectively. When ECD bit is set to "I", the host corrects
erroneous data detected during RED command execution if
necessary, regardless of the status of ACOR bit. The command
In DMA data transfer, the HOC selects one of two modes:
Burst mode and Cycle Steal mode. DMA transfer mode is
specified by BRST (burst) bit which is a command parameter
of SPC command.
In Burst mode (BRST = 1), the HOC maintains DREQ signal at
low level until data transfer is terminated. DREQ signal is
negated when DONE signal is input synchronously with DACK
signal, or when DMA transfer of data in 256-byte internal data
buffer is finished.
In Cycle Steal mode (BRST = 0), the HOC asserts DREQ signal
until DACK signal is asserted. The HOC negates DREQ signal
when DACK ~assertion is detected. DREQ signal will be
reasserted if DACK is negated and the HOC has the transfer
request. The DMA transfer conditions of Cycle Steal mode are
the same as those of Burst mode.
DATA TRANSFER IN HOST INTERFACE
DMA Data Transfer in Disk Access
DMA data transfer mode, either Burst mode or Cycle Steal
mode, is selected by BRST bit specified by SPC command.
Figure 9 shows DMA data transfer sequence during RD and
RED command execution. For 2S6-byte sector, (a) shows the
case that the host computer reads the disk data from data
buffers (DBUFO and DBUFI) by DMA at a high speed. The
capacity of two data buffers is 256 bytes for each.
~HITACHI
Hitachi Amenca Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
433
HD63463-------------------------------------------------------------If data buffers are not provided, most of high-speed host bus is
occupied by transferring drive data during low-speed reading of
drive data.
Internal data buffers can separate high-speed host bus timing
and low-speed drive data timing, which effectively shorten drive
data transfer time in host bus. Therefore, host system throughput is notably improved. The data transfer from data buffers to
the main memory is performed only when the HOC is reading
ID area or DATA area of the disk, but is exceptional when data
in the last sector is transferred to the main memory during the
multiple sector operation.
Figure 9 (b) shows the low-speed DMA transfer of the host in
256-byte sector organization. According to the figure, DBUFO
receives data of the sector l, and DBUFl receives that of the
sector i+ 1. While DBUFl is receiving the data of sector i+ l, the
data transfer from DBUFO to the main memory cannot be
finished because the host cannot operate promptly. Therefore,
being unable to receive the data of i+2, DBUFO waits until the
disk makes one rotation (all data of DBUFO is sent to the main
manner, no data overrun occurs even if operation speed of the
host is slow. Therefore, an interleave format is not required.
Figure 9 (c) indicates the sequence in 512-byte sector organization. Capacity of buffers is 256 bytes tor each, and each
buffer stores disk data and transfers the data to the main
memory alternately. Therefore, buffers effectively operates in
toggle fashion even if sector length exceeds 256 bytes, and host
system throughput is improved. If operation speed of the host is
too slow, data overrun may occur because data buffer cannot be
emptied to receive disk data. The data transfer from data buffer
to main memory must be terminated while the HOC is accessing
disk data in ID or DATA area.'
If the HOC receives DONE signal from the DMAC during RD
or RED command execution, the HOC immediately terminates
DMA data transfer. Disk reading operation continues until the
HOC finishes reading the sector which has been read when
DONE signal is applied.
OlSk
Format
OBUFO
OBUFI
Host Bus
(a) Sector Length = 256 bytes (Fast Host Bus)
- O-sector interleave Disk
Format
OBUFO
OBUFI
Host Bus
(b) Sector Length = 256 bytes (Slow Host Bus)
- Free from Data Overrun Disk
Format
OBUFO
OBUFI
Host Bus
(c) Sector Length = 512 bytes
~. Disk ___ Data Buffer
~
: Data Buffer ----.MalO Memory
Figure 9 DMA Data Transfer in Read Data and Read Erroneous Data Command Execution
~HITACHI
434
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63463
DMA data transfer during WD and CMPD command execution
is shown in Figure 10. This figure differs from Figure 9 (a) in
data transfer direction, DMA transfer order, and access method
of first and last sectors. In Figure 10, the host is fast and sector
length is 256 bytes. When the host is slow and sector length is 256
bytes, or when sector length is 512 bytes or more, data transfer
sequence is the same as Figure 9.
When the HDC receives DONE signal from the DMAC during
WD command execution, the HOC immediately terminates
DMA data transfer. Then all data stored in DBUFO and DBUFI
are written to DATA area of the sector. If there is any room in
DATA area after writing buffer data, the old data in buffers is
written to DATA area. After DATA area is ftIled with buffer
data, command execution terminates.
When the HOC receives DONE signal from the DMAC during
CMPD command execution, the HDC immediately terminates
DMA data transfer. However, the data of the sector which has
been accessed when DONE is received, ~used for comparison
with disk data, further, the reading operation continues until
reading of the sector is fmished. Therefore, $50 (Not Hit) is
set to SSB in most cases when reading of the sector is finished,
and then the command execution abnormally terminates.
DMA data transfer during RID or FID command execution is
performed as follows (see Figure 11). When DBUFO is fUied with
ID information, DBUFI receives the succeeding ID information. DMA data transfer is not performed unless all the ID information is stored in data buffer. After DBUFO with/without
DBUFI finishes accepting ID information from specified
number of sectors, data are sent to the main memory by DMA.
DMA data transfer continues until 512-byte transfer is finished.
DMA data transfer can be stopped when the DMAC sends
DONE to the HOC. Therefore, the host can store only the
necessary ID information to the main memory by setting the
number of ID areas to be read, to the DMAC.
DMA data transfer during WFM command execution is shown
in Figure 12. The HDC starts formatting operation when both
DBUFI and DBUFI are fUied with ID information from the
host. The HOC writes data buffer data to the ID area of a
specified sector, and writes fixed pattern to other area such as
DATA area. When DBUPO becomes empty during formatting
operation, DBUPI becomes the source in tum. When the DMAC
issues DONE signal to the HDC, the HOC stops data transfer to
data buffers and starts formatting. Therefore, the host can write
only the necessary ID information to data buffer by setting data
of how many ID areas to be transferred, to the DMAC.
Disk
Format
OBUFO
OBUFI
Host Bus
mm
Data Buffer -+ Disk
Main Memory -+ Data Buffer
~
Figure 10 DMA Data Transfer in Write Data, Compare Data Command Execution
(Sector Length = 256 bytes)
Disk·
Format
gctor i
~ctor i+11 ~5
i
ctor j
I I
i
ctor j+1
I
OBUFO
OBUFI
Host Bus
~ : Disk -+ Data Buffer
~ : Data Buffer -+ Main Memory
Figure 11 DMA Transfer in Read 10, Find 10 Command Execution
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
435
HD63463--------------------------------------------------------------
Disk
Format
OBUFO
OBUFI
Host Bus
r-___-...,~ctor i
~ctor i+11
hl--------I
IllIIIIIIIl
~
Data Buffer -+ Disk
Main Memory -> Oa.ta Buffer
Figure 12 DMA Data Transfer in Write Format Command Execution
DMA Data Transfer by Data Transfer Commands
Accepting data transfer commands, the HDC can perform DMA
data transfer between the main memory and data buffers without disk access. Either Burst mode or Cycle Steal mode is
selected by the BRST bit of SPC command parameter. There
are two commands available, BTM and MTB.
Selection of either DBUFO or DBUF I, and access start address
of each buffer (address 0 to 250 are specifiable), are specified
by POFF (pointer Offset). POFF is set to the data buffer
pointer by command execution.
Data buffer pointer is incremented each time the DMAC
accesses data butter t +2 for 16-bit bus mode, + 1 for 8-bit bus
mode). Data buffer data is not guaranteed if data buffer pointer
exceeds address 255. Receiving DONE signal from the DMAC,
the command execution immediately terminates normally, and
the CED bit in STR is set to "1". Receiving above data transfer
commands, the HDC requests transfer by issuing DREQ signal
to the DMAC within 150 CLK cycles.
Data Buffer Access by PIO
The host MPU can access data buffers by move or load/store
instruction (programmed I/O). In this case, the host issues
OPBR or OPBW command prior to PIO access. Receiving these
commands, the HDC sets BSY bit in STR to "1". Then the HDC
sets data buffer pointer, sets BSY bit to "0", and terminates
the command execution. It takes up to 100 CLK cycles from
the command reception to BSY bit clear. Before issuing above
commands, POFF must be specified by command parameters.
POFF specifies either DBUFO or DBUFI to be accessed, and
access start address (specifiable range is address 0 to 255).
The host issues move instruction to the HDC after confirming
that BSY = O. Data buffer pointer is incremented each time the
HDC receives move instruction (+2 for 16-bit bus mode, +1 for
8-bit bus mode). If the pointer exceeds address 255 during data
transfer in PIO mode, the buffer data is not guaranteed. The
host must issue RCAL command to close the buffer.
Notes on Data Buffer
~
(Byte)
Item
High Speed DMA
(O-sector interleave)
PIO
Low Speed DMA
(free from over·
run)
Automatic
Correction
256
512
1024
2048
4096
a
a
a
a
a
a
a
a
a
a
Others
Recell command - After the host issues RCAL command, the
HDC finishes the operation within up to 40 CLK cycles and
clears all bits in STR.
Test command - After the host issues TST command, the HDC
makes drive ou~ pins floated within 60 CLK cycles. To
cancel this state, RES signal is to be externally supplied.
Specify command - After the host issues SPC command, the
HDC makes the drive interface pins fitted for either ST506 or
SMD, and clears BSY bit within 250 cycles.
Abort command - After the host issues ABT command, the
HDC negates all tlrive output pins within up to 180 CLK cycles,
terminates all operation within 300 CLK cycles, and clears BSY
bit. Receiving this command, the HDC clears all internal flipflops, but the value of the control register which has been set
by SPC command still remains.
Reset - Reset is not a command, but after receiving RES signal,
the HDC terminates initialization within up to 150 CLK cycles
and clears BSY bit.
~HITACHI
436
Provided
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63463
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unot
Supply Voltage
Item
Vee *1
V
Input Voltage
Vin *1
Output Current per Pin
Total Output Current
110 I *2
I ~Io I *3
Operating Temperature
Top,
Storage Temperature
Tstg
-0.3 - +7.0
-0.3 - VCC + 0.3
5
80
0-+70
-55 - +150
mA
°c
°c
= OV.
*1
This value
*2
The allowable output current is the maximum current that may be drawn from, or flow out to, one output terminal or one Input/output
common terminal.
*3
The total allowable output current
common term IOsls.
(Note)
IS In
reference to Vss
V
mA
IS
the total sum of currents that may be drawn from, or flow out to, output terminals or Input/output
USing an LSI beyond its maximum ratings may result In Its permanent destruction. LSI's should usually be used under recommended
operating conditions. Exceeding any of these conditions may adversely affect Its reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
Supply Voltage
Vee *
5.0
Input Low Level Voltage
VIL *
4.75
0
2.2
0
5.25
0.8
V
Item
Input High Level Voltage
VIH*
Operating Temperature
Topr
25
V
Vee
V
70
°c
* This value is in reference to Vss = av.
.HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
437
HD63463---------------------------------------------------------------ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (VCC = 5.0V ± 5%, VSS = OV, Ta = 0 - 70°C, unless otherwise noted)
Item
Symbol
6MHz
Version
S MHz
Version
HD63463-6
HD63463-S
Unit
Test
Condition
min
max
min
max
Input High Level
Voltage
All Inputs
VIH
2.2
Vee
2.2
Vee
V
Input Low Level
Voltage
All Inputs
VIL
-0.3
O.S
-0.3
O.S
V
Input Leak Current
R/W, CS,
RS, RES
DACK,
CLK
DONE
liN
-2.S
2.S
-2.S
2.S
p.A
V," = O-Vee
-10
10
-10
10
p.A
Vin
VOH
vee-,·a
-
Vee-1.C
-
v
IOH = -400 p.A
VOL
-
O.S
-
0.5
V
IOL
ILOH
-
10
-
10
p.A
Three State
(Off State) Input
Current
STS06
SMD
IDX/
TRKO
IDX
SCP
USELD
WCLK
RCLK
RWDATA
SYNC"'
WGATE"2
EARLY/
RGATE"'
SEC
USELD
WCLK
RCLK
RWDATA ITSI
SKEND
BUSo/BUS s
BUS I /BUS6
= O.4-Vee
LATE/
BUS 2 /BUS 7
STEP"'
WFLT
BUS 3 /BUS.
LCT/DIR" BUS./BUS 9
READY
BUSLlH*'
Do - DIs
Output High Level
Voltage
All Outputs
Output Low Level
Voltage
Output Leak Cu. ent
(Off State)
IRQ
= 2.2 rnA
VOH = Vee
(to be continued)
*1
These signals are defined when HOC is in Test mode or when drive mterface is not specified. Otherwise, these signals are not defined since these
*2
This signal is defined when HOC is In test mode, otherwise this signal is not defined.
are switched to output signals.
~HITACHI
438
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63463
Item
Symbol
RES
DONE
RS
R/W
CS
DACK
Do - DIs
CLK
IRQ
Signal Capacity
ST506
6MHz
Version
8MHz
Version
HD63463-6
HD63463-8
Unit
min
max
min
max
-
17
-
17
Test
Condition
Vin =OV
Cpon
pF
Ta = 25°C
f = 1.0 MHz
SMD
RWDATA RWDATA
WCLK
WCLK
RCLK
RCLK
SKEND
BUSo/BUSs
BUSdBUS6
BUS2 /BUS.
WFLT
BUS 3 /BUS.
BUS4 /BUS.
lOX
IDX/
TRKO
SEC
SCP
USELD
USELD
READY
-
-
-
Current Consumption
ICC
-
65
-
mA
80
• Data bus in read/
write operation
• Commar,.l execution in progress
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
439
HD63463------------------------------------------------______________
AC CHARACTERISTICS (VCC
Clock Timing
Item
No.
1
Symbol
:
! Clock Cycle time
70°C, unless otherwise noted.)
6MHz Version
8MHz Version
HD63463-6
HD63463-8
Unit
min
max
min
max
167
500
125
500
ns
tPWCL
75
250
55
250
ns
tPWCH
75
250
55
250
ns
tCYC
Clock Low Level
2
=5V ± 5%, VSS =OV, Ta =0 -
Test
Condition
Pulse Width
Clock High Level
3
Pulse Width
4
Clock Rise Time
tCR
-
10
-
10
ns
5
i Clock Fall Time
i Write Clock
tCF
-
10
-
10
ns
tWCYC
62.5
250
50
250
ns
tPWCL
25
115
20
115
ns
tWCH
25
115
20
115
ns
6
: Cycle time
7
i Write Clock
Low
: Level Pulse Width
8
! Write Clock
9
i Write Clock
See Figure 15
High
Level Pulse Width
! Rise
tWCR
-
10
-
10
ns
tWCF
-
10
-
10
ns
62.5
250
50
250
ns
Time
10 : Write Clock
:
: Fall Time
11 : Read Clock
tRCYC
12
i Cycle Time
i Read Clock Low
i Level Pulse Width
tRCL
25
115
20
115
ns
13
! Read
tRCH
25
115
20
115
ns
Clock High
: Level Pulse Width
14
i Read Clock
tRCR
-
10
-
10
ns
tRCF
-
10
-
10
ns
: Rise Time
15 : Read Clock
! Fall
Time
@HITACHI
440
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
------------------------------------------------------------HD63463
Data Bus Configuration and IRQ
Item
No.
Symbol
!
21
RES Input
tRES
6MHz Version
8MHz Version
HD63463·6
HD63463-8
min
max
min
max
10
-
10
-
tcyc
-
100
-
ns
Unit
Test
Condition
Pulse Width
22
DACK Setup Time
-for RES
tDACKSR
100
23
DACK Hold Time
tDACKHR
0
80
0
See Figure 16
50
ns
150
ns
See Figure 17
10
jlS
See Figure 16
-For RES
24 IRQ Delay Time I
26
RES Rise Time
tiRO I
-
200
tRESR
-
10
-
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
441
HD63463-----------------------------------------------------+---------MPU Interface
Item
No.
Symbol
6MHz Version
8MHz Version
HD63463-6
HD63463-S
min
i R/W Setup Time
i for CS Assert
32 i R/W Hold Time
tRWS
33 : RS Setup Time
tRSS
31
max
min
Unit
Test
Condition
max
60
50
ns
60
50
ns
ns
tRWH
i for CS Assert
34 : RS Hold Time
ns
tRSH
i CS Setup Time
i CS Negate Hold Time
: cs Negate Width
tCSS
40
40
ns
tCSNH
40
40
ns
tCSNW
80
80
ns
38 : Write Data
tWDS
60
40
ns
i Setup Time
39 i Write Data
tWDH
10
10
ns
35
36
37
See Figures
18 and 19
: Hold Time
i DTACK Delay Time
tDTKZL
85
80
ns
41 : DTACK Hold Time
tDTKLH
60
60
ns
43 ' Data Sus 3 State
tDSR
40
ns
: Recovery Time
44
~
Read Data
tRDAC
ns
70
80
: Access Time
45 : Read Data
tRDH
10
ns
10
: Hold Time
cs Fall Time
: cs Rise Time
46 :
tCSF
tcyc
47
tCSR
tcyc
~HIT~CHI
442
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63463
DMA Interface
:
51
8MHz Version
HD63463-8
Svmbol
i DREQ Assert
i Delay Time I
tDRAOI
-
80
-
80
ns
tORNOI
-
80
-
80
ns
tDRA02
-
80
-
80
ns
min
:
50
6MHz Version
HD63463-6
Item
No.
DREQ Negate
max
min
Unit
Test
Condition
max
Delay Time 1
! (Cycle
52
Steal Mode)
i DREQ Assert
Delay Time 2
(Cycle Steal Mode)
53
i DREQ Negate
i Delay Time 2
tORN02
-
80
-
80
ns
54
DREQ Negate
tORN03
-
80
-
80
ns
tDRWS
60
-
50
-
ns
tDRWH
0
-
0
-
ns
tOACKS
40
-
40
ns
tOACKHN
40
-
40
-
ns
Delay Time 3
i (DONE Assert)
55
DMA R/W Setup
See Figures
20 and 21
Time
56
DMA R/W
Hold Time
57
58
DACK Setup Time
DACK
Negate
Hold
Time
59
DACK Negate Width
tDAKNW
80
-
ns
DMA Write Data
tDWDS
60
-
80
60
40
-
ns
tDWDH
10
-
10
-
ns
tODTZL
-
85
-
80
ns
tDDTLH
-
60
-
60
ns
Setup Time
61
DMA Write Data
Hold Time
62
DMA DTACK Delay
Time
63
DMA DTACK Hold
Time
(to be continued)
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
443
HD63463----------------------------------------------------------------
Item
No.
Symbol
8MHz Version
HD63463-8
min
:
65
6MHz Version
HD63463·6
! DONE Input
max
min
tPWDN
1.5
-
1.5
tDDBR
0
-
0
Unit
Test
Condition
max
teye
: Pulse Width
66
DMA Data Bus
-
ns
3 State
: Recovery Time
tDRDAC
-
80
-
70
ns
tDRDH
10
-
10
-
ns
DACK Fall Time
tDACKF
-
1
-
1
tcyc
70 : DACK Rise Time
tDACKR
-
1
-
1
tcyc
67
! DMA
68
! DMA
Read Data
See Figures
20 and 21
i Access Time
Read Data
: Hold Time
69
~HITACHI
444
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63463
STS06lntarfaceC8
:
No.
Svmbol
Item
6MHz Version
8MHz Version
HD63463-6
HD63463-B
min
tUSLDS
liD! USELD Setup
max
min
Unit
max
-
5
-
150
Itcyc
-
24twcyc
-
-
5
tcyc
See Figure 22
i Time (for USEL)
111 l WGATE Delay Time
tWGTIOX
i for Index
112 i WFLT Pulse Width
tWFLT
113ll ndex Pulse Width
tlDXW
-
100
I
ns
See Figure 23
2
24twcyc
i
Test
Condition
2
Itcyc
tcyc
-
114 WGATE Delay Time
tWGTD
-
130
-
125
ns
111 l Write Data
tWDD
-
130
-
125
ns
tELD
-
130
-
125
ns
-
ns
125
ns
(Note 1)
See Figure 23
i Delay Time
l1Bl LATE/EARLY
See Figure 24
i Delay TIme
120: LATE/EARLY
tWOS
0
-
0
Setup Time
(for Write Data)
i
tRGTD
i
tSYND
i
tRDS
121 RGATE Delay Time
123 SYNC Delay Time
125 Read Data
-
130
130
20
-
-
125
ns
-
ns
15
-
ns
70
-
tcyc
80
-
tcyc
15
See Figure 25
i Setup Time
tRDH
12& l Read Data
20
-
i Hold Time
i
WS-DIR
70
i
tSTPUS
BO
127 USELD-DIR Time
121 STEP-USEL Time
i
tDiRSTP
270
130 STP-DIR TIme
i
tSTPDlR
Bo
i
132 i SCP Wait Time
tSCP
129 DIR-STEP Time
131 SEEK-USEL Time
tSEKUS
1
-
-
270
1.0Xl0'
-
BO
1
1.oXlo'
tcyc
tcyc
See Figure 26
tcyc
tcyc
(Note 1) The index pulse width must setisfy min 8 teye and min 24 !Weye.
•
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
445
HD63463-------------------------------------------------------------SMD Interface
;
Item
No.
Symbol
!
I
tlDXW
150 Index Pulse Width
6MHz Version
8MHz Version
Ho63463-6
Ho63463-8
min
max
Itcyc
51tcyc
12twcyc
tUSLDS
151 : USEL.D Setup
min
max
Itcyc
50tcyc
Unit
-
12twcyc
-
-
7
7
i
tPWSET
Btcyc
50tcyc
12twcyc
153: WGATE Delay Time
tWGTSEC
8tcyc
(Note 2)
See Figure 32
tcyc
See Figure 31
i Time
152 Sector Pulse Width
Test
Condition
50tcyc
-
12twcyc
(Note 2)
See Figure 32
-
150
-
125
ns
-
130
-
125
ns
-
ns
See Figure 32
: for SEC/lOX
156: REGATE Delay Time
tRGTo
tRDS
158: Read Data
20
-
15
See Figure 33
: Setup Time
tRDH
159: Read Data
20
-
15
-
ns
125
ns
125
ns
: Hold Time
165: WGATE Delay Time
169: Write Data
tWGTO
-
130
tWOO
-
130
-
See Figure 34
: Delay Time
(Note 2) The index sector pulse width must satisfy mm 8 tcyc and min 12 twcyc .
•
446
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------------------HD63463
Signal
Do - DIs
DTACK
DREO
RWDATA
5.0V
Q
?
~
Load Condition
RL = 1.8 kn
~----------~----------~
ST506
RL
SYNC
WGATE
EARLY/
RGATE
LATE/
STEP
Test Point
I~
"
~,
~,
LCT/DIR
USELO
USELl
HSELO
HSEL1
HSEL2
SEEK
-'
7.7-
SMD
C=40pF
R=10kn
BUSo/BUSs
BUS I /BUS 6
BUS 2 /BUS 7
All diodes are
BUS 3 /BUS.
BUS./BUS.
TAGl
TAG2
TAG3
UTAG
TAG5
BUSR/W
BUSL/H
lS2074 @'s or
the equivalent.
Figure 13 Test Load Circuit A
2.2 V
0.8 V
CLK (in)
{
@
RL=l.S kn
C=40 pF
2.2V
0.8 V
@J
Figure 14 Test Load Circuit B
Figure 15 CLOCK
~HITACHI
Hitachi Amenca Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
447
HD63463-------------------------------------------------------------@
RES (in)
~
---
0.8 V
0.8 V
@--
I--@
2.2 V
~
1/ 0.8V
0.8 V'
DACK (in)
Figure 16 RES - DACK Input Timing (Data Bus Width Selection)
ClK (in)
TIm (out)
Figure 17 I RQ Output Timing
o
2
CLK (in)
R/W (in)
RS (in)
CS (in)
Do - 015 (out)
DTACK (out)
Vcc-2.0V
-----------------1IlI
--,u-~=-,--~__::_+--__::::_; 0.8 V
___________________
~8_-b_it
@,~~~-:~~~V J=4~~~CC~-~2~.0_V~
_______
10.8 V
(Note I) When using IS-bot date bus, DTACK is asserted from stete 4, shown by a dotted line.
(Note 2) When n .. 5 in a-bit date bus or n .. 7 in IS-bit date bus, it is not necessary to
satisfy @ and @
Figure 18 MPU Read Cycle
HDC ..... MPU
~HITACHI
448
Hitachi America Ltd • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
________
----------------------------------------------------------------HD63463
n = min 5
o
2
3
................. n -1
n
o
ClK (in)
Rm (in)
RS (in)
0.8 V
2.2 V
0.8 V
CS(in)
2.2 V
0.8 V 1..-_ _ _ _-+_____=....:..,-,1
@'It-0 0 -0" (in)
0.8 V "f----+i""
OTACK (out)
--------------------------------i~0~.8~V~______~
(Note 1) When n ~ 5, It is not necessary to satisfy
@
and
@
Figure 19 MPU Write Cycle
MPU-+ HOC
(8 or 16·bit data bus)
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
449
:::J:
C
.j:>.
U1
o
Q)
n = min 7 (16-bit data bus)
n = min 5 ( 8-bit data bus)
o
2
n -1
o
n
2··· .....
ClK (in)
::I:
~
=~
<1l
OREQ (out)
~
R/W(in)
~.
0.8 V
~
o
OACK (in)
o
c}~
•
!2.
<1l
~:I
l6 ~
m(")
-
Do - 0" (out)
c....
:I
OTACK (out)
:::>
~
.. -
_...,..
, ----------1
®l'~-----J~----J
-~
(')
>
DONE (in)
~
~
(Note 1) Th,s is the timing to negetel5REQ signal when the 256th
byte data is transferred to the HDC data buffer.
(Note 2) DONE must be asserted to low while DTACK remains
1...
low.
(Note 3) As shown by dotted lines. DACK is output synchronously
with the falling edge of state 4 clock.
(Note 4) When n" 5 in 8-bit data bus or n .. 7 in 16-bit data bus.
it is not necessary to satisfy ~ and ~ .
i
Figure 20 OMA Read Cycle
HOC ..... Memory
*
CAl
n = min 5
:c
5r
:r.
"
»
I
3
ClK (in)
CD
15
"'r
DREQ
(out)
p:
'"'"0
0
•
a1~
R/W
(in)
Q.
CD
~:I
::l
c:
CD
~
wO
"' :I
::l
'-
DACK
(in)
I Do -
0 15
(in)
0
'"
51'
0
»
CD
~
~
-:;;:
DTACK
(out)
DONE
(in)
0
oS
l>
W
~
(Note 1) When n
~ 5, it is not necessary to satisfy
®
and
~
W
0
0
Figure 21 DMA Write Cycle
Memory -+ HOC
.j>.
U1
:x:
o
Ol
CtJ
.j>.
Ol
CtJ
HD63463--------------------------------------------------------------
USELl (out)
USELO (out)
USELO
(in)
Figure 22 USEL, USELO Timing (ST506)
A
@
_ ____2_._2 V
J .
WFLT (in)
(Note 1)
\-2_.2_V_ _ _ _ _ _ _ __
_
2.2V
lOX (in)
1\2.2 V
/
~
WGATE (out)
/
(Note 2)
Vcc-2.0 V
----.........I
(Note 1)
(Note 2)
@
@
is minimum pulse width which HOC can recognize.
is WGATE assert timing for lOX during Write Format command execution.
Figure 23 WFLT, lOX, WGATE Timing (ST506)
~HITACHI
452
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
WGATE (out)
,
J:
~2:
§"
CD
is
III
~
LATE/EARLY (out)
~
o
Figure 24 Write Operation (ST506)
Q
i~
CD
_
~:I
~ ~
0(')
WCLK (in)
<-
RCLK (in)
~
~
'GATE
~:I
~
~
~
i
'00"
SYNC ''"'"
RWDATA (in)
1'"F-,·o ~~
'--'
~1ivv-----it-----___.....{\:--=1
2.2V
0.8 V
Figure 25 Read Operation (ST506)
:::r
c
"'W"
U1
0)
~
0)
w
HD63463--------------------------------------------------------------
>
co
......-~-.->
c::i
~~r;~---r-t-~~~--------~~
I
~
>
......
:l
:l
.£.£
...
:l
...
.,.
.£
"-
w
w
en
:l
0_
.£
.£
ww
enen
a:
w
.....
en
..J..J
:::>:::>
C
:l
~
£
"u
en
@HITACHI
454
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
-----------------------------------------------------------------HD63463
(a) AM is detected.
)
Sector formst
L
C
A
L
L
A C
M A
H
PLO SYNC
L
H
A
L
S
A
C
A
C
PAD
PLO SYNC
~mandissue
I
ir---------------------------------------------------~:-,(
AGATE
\
,
10r2 (NOTE)
B
typ 8 bits ........
: ~:i".,.....;.y-te-s...~:
1
1
'~---(-A-EA--O-)~
:L-..J,
SYNC
i~
/
--II
1
I
1
typ 4bits~
I
"~
----1 ,VYM' I ' "
WGATE
(NOTE)
1 byte when AM is not included in error
detection span, 2 bytes when AM is included.
(b) AM is not detected.
'00' pattern
'00' pattern
Sector format
typ
Comma nd
issue
f
AGATE
\
Y
SYNC
4bit~!
I
1
1
1
,
:,
2 bytes
...,,
1
/.
Aetry
1
"-.\
Figure 27 10 Search Timing Chart (ST506)
Sector format
1
10
C
R
C
10
I I
PAD
,
PLO SYNC
I
I
,;"
ECC
or
CRC
DATA
PAD
:---typ 8 bits
AGATE
----------~'--------------------Ir__---------------~r__----L
II
I
1
,
SYNC
,
1
,
~ t 4 j - typ 4 bits
_ _ _ _ _. . , ' I
't:
I
1 or 2 bytes
I
,
WGATE
U
~
I
---+:
14--0 bit
,..------------------llt------------------------~1
L-,
1
-----------~.,
Figure 28 Write Data Timing (ST506)
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
455
HD63463--------------------------------------------------------------
f\
I
n
IDx---'l
\~_____________________________________________________________J.
: I
~-------
:
I
-
---..: """-Electrical characteristic @
I
I
I
I
3to4
bytes
I
f4-
I
I
WGATE~~--------------------------------------------------~~
Figure 29 Write Format Timing (ST506)
I
I
---:
USELO
USELI
1
I
I
I
I
'+-I
X'-------------i:t_-min
I
;70 --:
!
LCT/DIR
x,------{:~t-- _ r _
I
I
I
: . . - - min
I
270
------!
LATE/STEP
SEEK
~
n ,
I
J+-- min -----,
~
I
I
Command execution finished
(Unit: CLK cycle)
Figure 30
Seek, Recalibrate Command Execution Timing (ST506)
~HITACHI
456
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63463
..
VCC-2.0VC
UTAG (out) ___________
.....
W~2.2V
USELO (in)
Figure 31
UTAG, USELO Timing (SMO)
~
J
2.2V
,
0.8 V
lOX (in)
"-
il@
J
SEC (in)
2.2 V
~
10.8 V
(Note 1)
Vcc-2.0 V
J
WGATE
BUSo/BUSs
(out)
(Note 1)
@
i. WGATE assert timing for IDX/SEC during
Write Format command execution.
Figure 32 lOX/SEC, WGATE Timing (SMO)
•
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
457
:I:
o
"'co"
(11
CJ)
w
"'"
CJ)
w
WCLK (in)
I
RCLK (in)
~
:!"
»
3
RGATE
BUS./BUS 6 (out)
'5'"
I»
~
RWDATA (in)
Rl
<5
o
•
oi~
Q.
'"
~:I
~ ~
Figure 33 Read Operation (SMD)
'"
",C')
~
"-
:I
g
!D
§;
WCLK (in)
CD
~
~
~
WGATE
BUSo/BUS s (out)-.-J
$
~
'I'
~
o
RWDATA (out)
<
C~l' u.u y
I\ .:u~.o: . . :.v_ __
Figure 34 Write Operation (SMD)
::I:
~
>
UTAG (out)
'-
3
'"
BUS L/H (out)
~.
III
~
13 tcyc
BUS RiW (out)
~
o
6 tcyc
o
c)~
•
'~J:
"
!2.
~
16
BUSo/BUS s BUS./BUS 9 (out)
-~
(1)0
~ J:
c....
USELD (in)
-
I
Vcc-2.0 V
0.8 V
32 tcyc
Vcc-2.0V
0.8 V
Drive Select
~
@
~~V2.2V
;
~
~
~
1
i
20 tcyc
Pm
Output Signal Name
Abbreviation
BUS./BUS9
BUS3 /BUS.
BUS,/BUS,
BUS.tBUS6
BUSo/BUSs
-
-
Unit Select 2
Unit Select 1
Unit Select 0
-
USLL2
USEL1
USELO
Figure 35 Drive Select Operation (SMD)
:::t
o
""
01
co
0)
~
0)
W
:J:
C
Ol
""
~
Ol
Ol
o
Ct.)
:t:
~
:r.
~
\
/
TAG 1,2,3,5 I..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--J
2
(outl
~
BUS R/W (outl
20 tcyc
~
o
oi.
o
Q.
CD
BUS L/H (outl
max 7 tcyc
•
_
~:I
CD
~ ~
:~~:::~~:~nl
min 5 tcyc
---X(««<<««(I:~:~ ~
~.8 v"'f»»»)»»»))»»))»>>)>>>>X~_ _ _ __
00(')
~
<-
:I
Pin
BUS4 /BUS 9
BUS 3 /BUS.
BUS2 /BUS,
BUS,/BUS6
BUSo/BUS.
~
~
co
~
~
j
j
Figure 36 Drive Check Operation (SMDI
Input Signal Name
Write Protect
Fault
Seek Error
On Cylinder
Unit Ready
Abbreviation
WPRT
FLT
SKERR
OCYL
URDY
I
,
TAG 3 (out}
:t:
~
19 tcyc
'"
20 tcyc
»
3
III
~
ct.
c5
q
!2.
~
BUS R/W (out}
Rl
CD
6 tcyc
19 tcyc
8 tcyc
f
BUS L/H loud
~
15
I
•
typ 20 tcyc
6 tcyc
BUSo/BUS.BUS4 /BUS 9 (out}
min 6 tcyc
typ 6 tcyc
(
-.J
~J:
CD
_
~ ~
We)
~ J:
<..
~
~
~
!:1
BUSL/H = high
BUSLiH= low
p,"
BUS4/BU~
BUS 3 /BUS.
BU5,/BUS7
BUSt/BUS.
BUSo/BUS.
Output Sianal Name
(Reserve}
Strobe Late
Strobe Early
Return to Zero
Reserve
Pin
Abbreviation
Level
0
STBL
low
BUS4 /BUS9
low
STBE
low
RTZ
0
Output Signal Name
Abbreviation
Level
Fault Clear
FCLR
high
BUS 3 /BUS8
Servo Offset Minus
SOFM
low
BU5,/BUS 7
Servo Offset Plus
SOFP
low
low
BUSt/BUS.
Read Gate
RGATE
low
low
BUSo/BUS.
Write Gate
WGATE
low
j
i
Figure 37 Fault Clear Operation (SMD}
J:
C
....""'
,0)
0)
Co)
.j:>.
0)
Co)
:I:
o
.j:>
Cl
w
Cl
I'.)
.j:>
Cl
W
TAG 3 (out)
19 tcyc
20 tcyc
19 tcyc
8 tcyc
6 tcyc
}
BUSL!H (out)
i.
min 20 tcyc
I
~
BUSR/VV(out
'i!
.\
»
6 tcyc
3
~
BUSo/BUS s BUS./BUS. (out
.,o·
~
Wp 20tcyc
,=1
min 6 tcyc
typ 6 tcyc
X
J(
max 1.0 x 10· tcyc
a'"'"
maxl.aX10· tcyc
o
•
ol~
Q.
~:I
(fl(')
:I
BUSLIH = low
PO"
BUSL!H = high
Output Signal Name
Reserve
Abbreviation
Level
0
low
BUS./BUS'I
BUS 3 /BUS.
Strobe Late
STBL
low
BUS,/BUS 7
Strobe Early
STBE
low
»
BUSdBUS.
high
BUSo/BUSs
Return to Zero
Reserve
RTZ
<0
U1
0
low
~
c...
g
!"
()
~
I
~~
SEEK ERRO R (in)
CD
~ ~
J
~~~
ON CYLINDE R (in)
Pin
Output Signal Name
FCLR
BUS 3 /BUS.
Servo Offset Minus
SOFM
low
BUS,/BUS 7
Servo Offset Plus
SOFP
low
BUS\/BUS.
Read Gate
RGATE
low
Write Gate
WGATE
low
o
(Note)
On Cylinder and Seek Error afe checked by POlling command .
8
Figure 38
low
BUSo/BUSs
~
...
Level
Fault Clear
~
~
00
Abbreviation
BUS./BUS.
Recalibrate Command Execution Timing (SMD)
;!=
~
"-
-'
TAG 1 (out)
:.>
3
19 tcyc
<1>
~.
Il>
BUS
Ii
~
•
ot~
Q.
<1>
_
~J:
<1>
~ ~
00(")
'-
:.>
(l)
01
§
-:;;:
~
....
~
6 tcyc
19 tcyc
J
1
-l
UH" (out)
Q
1i<1>l
o
a tcyc
I
BUS R!W (out
<5
~
20 tcyc
J:
6 tcyc
BUSoBUS,BUS.BUS. (out)
typ 20 tcyc
X
X
Cylinder Address High
J
L
Cylinder Address Low
BUSL/H = high
BUSL/H = low
P'n
min 6 tcyc
typ 6 tcyc
Output SIgnal Name
AbbrevIatIon
Pm
BUS./BUS.
BUS 3 /BUS s
BUS./BUS.
Cylinder Address 9
CAD 9
BUS 3 /BUSs
Cylinder Address
a
BUS2 /BUS 7
BUS./BUS6
Cylinder Address 7
Cyl inder Address 6
CAD
CAD 7
BUSo/BUS,
Cylinder Address 5
(Note)
a
Output SIgnal Name
T
AbbreviatIon
Cylinder Address 4
CAD 4
Cylinder Address 3
CAD 3
CAD 2
BUS2 /BUS 7
Cylinder Address 2
CAD 6
BUS./BUS 6
Cylinder Address 1
CAD 1
CAD5
BUSo/BUS,
Cylinder Address 0
CAD 0
j
After outputting the cylinder address, the minimum wait time until
On Cylinder and Seek Error are returned from the drive is
equivalent to that of Recalibrate operation .
eX>
~
o
Figure 39 Seek Command Execution Timing (SMD)
:I:
.j:>
0)
W
o
0)
w
.j:>
0)
W
::J:
o
m
~
~
m
m
w
~
I
TAG 2 (out)
~;;r.
19 tcyc
>
CD
~
BUS R!W (out)
,
I\)
•
oI~
CD
o
BUSo!BUSsBUS4 !BUS. (out)
6 tcyc
typ 20 tcyc
X
-=-
typ 6 tcyc
min 6 tcyc
r
Head Address High (all 0)
J
t
8 tcyc
6 tcyc
~
o
q
19 tcyc
8 tcyc
-J
BUS L!H (out)
£'
I
20 tcyc
3
Head Address Low
r-
_
~:t
CD
~ ~
BUSL!H =low
BUSL!H = high
000
PO"
Output Signal Name
Abbreviation
PO"
BUS4 !BUS.
He&d Address 9
HAD9
BUS4 !BUS.
Head Address 4
c..
BUS 3 !BUS.
Head Address 8
HAD8
BUS 3 !BUS.
Head Address 3
BUS2 !BUS 7
Head Address 7
HAD 7
BUS2 !BUS 7
Head Address 2
BUSdBUS6
Head Address 6
HAD6
BUSdBUS 6
Head Address 1
HAD 2
HAD 1
HAD5
BUSo!BUS s
Head Address 0
HAD 0
~
J
~
~
:t
BUSo!BUSs
Head Address 5
~
~
(Note) Head Address 5 - 9 are fixed at low level.
~
Co
g
Figure 40 Head Selection Operation (SMD)
Output Signal Name
Abbreviation
I
HAD41
HAD 3
I
,------------------------------,
i
i
! Read/Write Operation (2) (See Figure 42)
II
-
TAG 3 (out)
19 tcyc
8US
I
~;r.
-'
i
9 tcyc
'
10 tcyc
!
iJ
L/H (out)
11I
typ 8 tcyc
i
»
~r
BUS RtW (out)
~
BUSo/BUSsBUS./BUSg (out)
I
i
3
~
I
typ 8 tcyc
6 tcyc
)(
i
min 8 tcyc
I
IX
!
I
.
0)
Read/Write Operation (3) (See Figure 43)
I
i
L ____________________ j
en
Figure 42 ReadIWrite Operation (,2) (SMD)
I
, (Note)
I
If either SOFP or SOFM is asserted
to high, the HOC remains in the
wait state until the SKEND is
asserted to high.
:I:
o
0)
w
.j>.
0)
w
J:
o
~
0)
0)
0)
lOX/SEC (in)
RWDATA
::I:
~
(in/out)
2:
RGATE
(BUStlBUS 6 ) (out)
g.
ri.
~
o
•
:::J
_
~J:
~ ~
cnO
~
~
~
!!i~
j
~
8
~F
,_ rl~.-rI-_TI~.rl--~--~------,1
Next Sector
'I
(ii) WRITE DATA
RGATE
(BUStlBUS6 ) (out)
o
'-
I
1 or 2 bytes (Note 2)
~
CD
r
~
W
( i) READ DATA
>
~
2.
w
0)
'I
/
1 or 2 bytes (Note 2)
WGATE
(BUSo/BUS~s)~(~ou~t~)__~__________________________- - J
(iii) WRITE FORMAT
J:
WGATE
(BUSo/BUSs) (out)
I~
~~_
Vcc-2 0 V
.
;B V
(Note 11 RGATE must be asserted at the beginning of PLO SYNC area or earlier.
(Note 21 2 bytes when SYNC PAT is included in error detection span (AM EX = 01.1 byte
when it is not included (AMEXc 11. However, RGATE and WGATE rise at the
beginning of PLO SYNC area.
Figure 43 ReadlWrite Operation (3) (SMD)
TAG2, TAG5 (out)
I
~
:r.
BUS l/R' (out)
>
3
~
0'
20 tcyc
Ol
BUS RiW (out)
C
Cl.
o'"'"
BUSo/BUS sBUS./BUS9 (in)
o
•
01~
o
'~:I
"
(I)
_
~ ~
000
~ :I
<~
~
~
~
BUSL/H = high
BUSl/R' = low
Pin
I nput Signal Name
Abbreviation
Pin
Input Signal Name
Abbreviation
BUS./BUS 9
BUS 3 /BUS.
BUS 2 /BUS 7
BUSdBUS.
BUSo/BUSs
-
-
*
*
*
*
*
*
BUS./BUS 9
BUS3 /BUS.
BUS 2 /BUS 7
BUS,/BUS.
BUSo/BUSs
Write Protected
Fault
Seek Error
On Cylinder
Unit Ready
WPRT
FlT
SKERR
OCYl
URDY
-----
-
(Note 1) Names of signals which are read from a drive when the HOC
IS
connected to the DK8125 (Hitachi).
(Note 2) User Area
~
$
~
~
g
+>
Ol
......
Figure 44 Sense Drive Operation (1) (SMD)
:I:
o
Ol
W
+>
Ol
W
:J:
o
0)
"'"
0)
CAl
co
"'CAl"
0)
TAG2 (out)
TAG5 (out)
8 tcyc
I
~
:!
BUS
l>
6 tcyc
8 tcyc
26 tcyc
L/Ff (out)
3
16 tcyc,
6 tcyc
!!l
20 tcyc
I 6 tcyc
0'
III
BUS R/W (out)
J:'
P.
3 tcyc 4 tcyc
3 tcyc 4 tcyc
BUSo/BUSsBUS./BUS. (in)
~
o
o
•
ol~
o
CD
~J:
'"
-
~ ~
(1)(')
~
'-
o(Jl
5"
()
J:
Pm
p,n
Input Signal Name (Note 1)
Abbreviation
Write Error 3
WERR3
BUS 3 /BUS.
BUS 3 /BUS.
Write Error 2
WERR2
BUS2 /BUS7
BUS2 /BUS 7
Write Error 1
WERR1
BUS,/BUS6
Status Error 2
SERR2
BUSo/BUSs
Status Error 1
SERR1
~
~
BUSo/BUSs
~
Abbreviation
BUS./BUS.
BUS,/BUS6
~
Input Signal Nam,e (Note 1)
BUS./BUS.
l>
eo
BUSLIH = high
BUSLIH = low'
}(Note 2)
SELECT ERROR
SELER
(Note 1) Names of signals which are read from a drive when the HOC is connected
to the DK812S (Hitachil,
(Note 2) User Area
~
~
g
Figure 45 Check Drive Status (2) (SMD)
-
'1
TAG2 (out)
8 tcyc,
8 tcyc
:r:
~
:::
»
TAG5 (out)
3
.
(J)
(0
o
w
.j>.
(J)
(J)
W
:I:
C
en
.j>.
w
-..J
.j>.
o
en
w
:I:
'1
TAG2, TAG5 (out)
~
O.BV
B tcyc
=-
>
3
min 33tcyc
CD
B tcyc
1
26 tcyc
16 tcyc
'~"
BUS
BUS R!W (out)
ciA
~'EV
~J:
~ ~
000
~
~~
~
~
~
1
i
I " __ 00_ .
6 tcyc
~
o
o
t...
L1H (out) ~
J:
3 tcyc
4tcyc
6 tcyc
----=--
g"
1:-lD-j '-1
'I
6 tcyc
3
_
4tcyc
BUSo/BUS s BUS4 /BUSg (in)
BusLIil = high
BUSL/il = low
Input S'gnal Name (Note 1)
P,n
P,n
Input Signal Name (Note 11
Abbreviation
BUS4 /BUSg
BUS4 /BUS g
BUS3/BUS.
BUS3/BUS.
Device Type 16
Device Type B
DTP16
DTPB
BUS 2 /BUS 7
Device Type 4
DTP4
BUSt/BUS.
BUSo USs
Device Type 2
DTP2
DTP1
BUS2 /BUS 7
BUSt/BUS.
BUSo/BUS.
Abbreviation
}(NO~21
Device Type 32
DTP32
I
/i3
Device Type 1
(Note 1) Names of Signals which are read from a drive when the HOC is connected
to the DK812S (Hitachil.
(Note 21 User Area
Figure 47 Check Drive Status (4) (SMD)
--------------------------------------------------------------HD63463
4.5 V
/
Vcc (in)
0.8 V
t2CH
< 100 ms
~
/2.2V
elK (in)
tRESR ;;;:
10 !-IS
I----REH>l00
ms
:7
k'v
2.2 V
Figure 48 Timing Requirement during Power·On.
~HITACHI
Hitachi America ltd .• 2210 O'Toole Avenue. San Jose, CA 95131 • (408) 435-8300
471
HD63484--------------ACRTC (Advanced
CRT Controller)
The Advanced CRT Controller (ACRTC) is a CMOS VLSI
microcomputer peripheral device capable of controlling rasterscan CRTs to display both graphics and characters. The ACRTC
is a new generation CRT controller that is based on a bit-mapped
technology. It executes high-level drawing commands, like Line,
Ellipse, Paint, Pattern, and Copy, issued by the MPU in X-Y
coordinates, and performs address translation to draw into frame
memory. It can draw in up to 64K colors, on 3 split screens and
an independent window, and perform area clipping and hitting. It
has more display control functions than an HD6845S (CRTC).
The ACR TC controls a CR TC in one of three modes; character only, graphic only and multiplexed character/graphic modes.
Therefore, the ACRTC has many applications, from character
only display devices to large full-graphic systems.
The ACRTC can reduce CPU software overhead and enhance
system throughput.
• FEATURES
• High-speed graphics
• Drawing rate: Maximum 500 ns/pixel (Color draWing)
• Commands.
Dot. Line, Rectangle, Poly-line, Polygon, Circle, Ellipse, Paint. Copy, etc.
· Colors:
16 bits/word
1, 2, 4, 8, 16 bits/pixel (5 types) monochrome to max. 64k colors.
• Pattern RAM (32 bytes)
• Conversion of logical X-V coordinates Into phYSical address.
· Color operation and conditional drawing
• Drawing area control for hardware cliPPing and hitting
• Large frame-memory space
• Maximum 2M bytes graphic memory and 128k bytes character memory separated from the MPU memory
• Maximum, resolution 4096 x 4096 (1 bit/pixel mode)
• CRT display controls
• Split screens (3 displays and 1 window)
· Zooming up (1 to 16 times)
• Scroll (Vertical and hOrizontal)
• Interleaved Access mode for flash less display and superimposition
• External synchronization between ACRTC. or between the
ACRTC and external deVice (ex. TV system or other controller)
• DMA interface
• Two programmable cursors
• Three scan modes
• Non-interlaced
• Interlace sync.
• Interlace sync. and video
• 256 characters/line, 32 rasters/line, 4096 rasters/screen
(DC-64)
HD63484P-8,
HD63484P-98
(DP-64)
HD63484CP-8,
HD63484CP-98
(CP-68)
HD63484Y-8,
HD63484Y-98
• TYPE OF PRODUCTS
Clock
Frequency (2CLK)
Package
HD63484-8
HD63484-98
8MHz
9.8 MHz
DC-64
64 Pin Ceramic DIP
HD63484P-8
HD63484P-98
8MHz
9.8 MHz
DP-64
64 Pin Ceramic DIP
HD63484CP-8
HD63484CP-98
8MHz
9.8 MHz
CP-68
64 Pin Ceramic PLCC
HD63484Y-8
HD63484Y-98
8MHz
9.8 MHz
PGA-68
64 Pin Ceramic PGA
Product type
HD63484-8,
HD63484-98
(PGA-68)
~HITACHI
472
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63484
• HD63484CP
• PIN ARRANGEMENT (Top View)
• HD63484, HD63484P
~1
CHR
MRD
LPSTB
R/iN :)
CoNE
"5ii'ffi
H'Sv"N'C
AS
VSYNC
MCYC
MAD,
t/lAO,
Vee
Vss
v"
EXSYNC 1
MAO,
1
MAO,
DACK [9
OTACK
1iRAW
MAD.
I
RES s
ilIlll
i5iSPi
DiS'Pf
V"
2ClK
V"
vee
Do
~
MADs
MADs
iiffi "
HSv"Nc ,
VSvNC
1
Vee
I
i
EXSYNC ,
Vss
'
0,
,
0,
D.
0,
2CLK
v"
MAD.
MAD'2
MAD,
!l!
MAO;
MAD.
21
MAD,.
2
MAD"
0,
1 MAD"
D.
MAO,.
MALo,.
0,
0,.
MAD,o
MAD,!
~nTnorrrTnTn~~nrnorrr~~
MAD.
0,
0,
MAD7
MADe
MAO g
~~,yc
~: ~
0,
0,
(Top View)
MAO,.
1
0"
7 MA,elRA.
0"
MA,/RA,
0"
MA,JRA.
• HD63484Y-8
• HD63484Y-98
MA,,.IRA,
0" 31
0" _ _ _ _ _ _ _1'"' ft••
lstPm
r
fnde)(
(Top View)
D
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratmg
Unit
Vee
-0.3 to + 7.0
V
Supply Voltage
Input Voltage
V,n*
-0.3 to Vee +0.3
V
1101"
5
mA
IElol'"
120
mA
To,
Oto +70
·C
Allowable Output Current
Total Allowable Output Current
Operating Temperature
Storage Temperature
·C
-55 to + 150
T"g
(Bottom View)
(TOp Vtew)
Pin
No
*: i~: :If~~~~no~~:~~~~~r!~t~~'h; ~~xlmum
current that may be drawn
from, or flow out to, one output termmal or one inpuUoutput common
termmal.
* * * The total allowable output current IS the total sum of currents that may be
drawn from, or flow out to, output terminals or inpuUoutput common
terminals.
(Note) Using an LSI beyond its maximum ratings may result in Its permanent
destruction. LSI's should usually be used under recommended operatmg
conditions. Exceeding any of these conditions may adversely affect Its
reliability.
• RECOMMENDED OPERATING CONDITIONS
Signal
Oescnptlon
Pin
No
Signal
Descnptlon
Pin
No
Signal
DescriptIon
1
MAD14
18
RS
Pin
No
35
MA1SIRA2
52
2
MAD11
19.
3
MADg
4
MADe
5
Signal
Description
OREa
36
MA,e/RAe
53
HSYNC
20
DTAl:R
iiiil
37
MAD 13
54
EXSYNC
21
VSYNC
38
MA0 10
55
DO
MA06
22
Vee
39
MA07
56
04
6
Vee
23
Vss
40
MADs
57
Os
7
Vss
24
Vss
41
2CLK
56
O.
8
VSS
25
01
42
MCYC
59
09
9
AS
26
O2
43
DRAW
60
011
10
MRO
27
05
44
MA04
61
01•
11
MADs
28
08
45
MA02
e2
RA.
12
MA0 1
29
010
.6
MAOo
63
MA17/RA1
Symbol
Min
Typ
Max
Unit
13
iiiSP2
30
012
47
iifIDl1"
64
MA0 1S
Supply Voltage
Vee
4.75
5.0
5.25
V
14
LPSTB
31
013
48
CU01
e5
MA0 12
Input "Low" Level Voltage
V 1L ..
0
-
0.7
V
15
Vee
32
0 15
49
cs
66
CHR
16
CUD2
33
VSS
50
RES
87
IiAllK
17
RIW
34
MA1g1RA3
51
iiliNE
68
07
Item
Input "High" Level Voltage
Operating l1>mperature
V IH
..
Toor
2.2
-
Vee
V
0
25
70
·C
'This value Is In reference to Vss - OV
• TIMING MEASUREMENT
The timing measurement point for the output "low" level is
defined at 0, BV throughout this specification.
The output "low" level at stable condition (DC characteristics) is defined at O,5V.
The output "high" level is defined at VCC-2,OV.
.HITACHI
Hitachi America Lid. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
473
HD63484----------------------------------------------------------------
--
--------=~~~~
o measuring pOint
__L-__
Vo L at the timing measurement (0 BV)
-_-_-~rVOL at the DC level (O.5V)
t
VOL Reference at Timing Measurement
• Electrical Characteristics
• DC Characteristics (Vcc
= S.OV
± 5%, Vss
= OV, T. = 0 to 70°C unless otherwise noted)
Item
Symbol
8 MHz
Version
Measuring
Condition
Min
Max
9.8 MHz
Version
Min
Max
Unit
Input "high" level voltage
All Inputs
V IH
2.2
Vcc
2.4
Vcc
V
Input "low" level voltage
All Inputs
V IL
-0.3
0.7
-0.3
0.7
V
Input leak current
R!W,CS, RS,
RES, DACK,
2CLK,LPSTB
Ion
-2.5
2.5
-2.5
2.5
I"A
Three state (off state)
Input current
Do-D 15 ,
EXSYNC,
MAD o-MAD 15
ITSI
V,n + 0.4 to Vcc
-10
10
-10
10
I"A
Output "high" level
voltage
Do-D 1S '
MAD o-MAD 1s ,
CUD1, CUD2,
DREQ, DTACK,
HSYNC,
VSYNC,
EXSYNC,
DISP1, DISP2,
CHR, MRD,
DRAW, AS,
MCYC,
MA 16!RAoMA 19!RA3 , RA 4 ,
IRQ, DONE
VOH
IOH + - 4OO I'A
Vce
-1.0
-
Vee
-1.0
-
V
VOL
IOL : 2.2 mA
-
0.5
-
0.5
V
-
0.5
-
0.5
V
10
10
I"A
Output "low" level
voltage
V ,n : Oto Vcc
VOL
IOL : 2.5 mA
Output leak current
(off state)
IRQ, DONE
ILOO
VOH : Vce
Input capacity
Do-D 15 ,
EXSYNC,
MAD o-MAD 15
C,n
Von: OV
T A :25°C
f : 1.0 mHz
-
17
-
17
pF
Von: OV
T A :25°C
f : 1.0 mHz
-
17
-
17
pF
Cout
V In : OV
T A :25°C
f : 1.0 mHz
-
15
-
15
pF
Ice
-Chip not selected
-Display in progress
-
100
-
120
mA
-Data bus in read!
write operation
-Display in progress
-Command execution in progress
-
100
-
120
mA
RIW, CS
RS, RES,
DACK,2CLK,
LPSTB
Output capacity
Current consumption
IRQ, DONE
~HITACHI
474
Hitachi America Ltd. - 2210 O'Toole Avenue • San Jose, CA 95131 - (408) 435-8300
--------------------------------------------------------------HD63484
• AC Characteristics (Vee = 5.0 ± 5%, Vss = OV, T. = 0 to 70·C unless otherwise noted)
Clock Timing
No.
Item
Operation Frequency of 2 ClK
Reference
Figure
Number
Symbol
9.S MHz
Version
SMHz
Version
Min
Min
Unit
Max
1
S
1
9.S
!evc
125
1000
102
1000
ns
Clock "High" level Pulse Width
tpWCH
55
500
46
500
ns
3
Clock "Low" level Pulse Width
t pwCL
55
500
46
500
ns
4
Clock Rise Time
Ie,
5
ns
5
Clock Fall Time
tCI
5
ns
1
Clock Cycle Time
2
f
Max
1
-
10
10
-
MHz
MPU ReadlWrite Cycle Timing
No.
Item
Reference
Figure
Number
Symbol
9.S MHz
Version
SMHz
Version
Unit
Min
Max
Min
Max
ns
6
RIW Setup Time
tAWS
50
-
50
7
RIW Hold Time
t AWH
0
-
0
S
RS Setup Time
50
-
50
-
9
RS Hold Time
tASH
0
-
0
-
ns
10
CS Setup Time
tcss
40
-
40
ns
11
CS "High" level Width
2,3
60
-
60
-
0
-
0
-
ns
2,4
-
SO
-
SO
ns
2-4
tASS
tWCSH
ns
ns
ns
12
13
Read Wait Time
t AWAI
14
Read Data Access Time
t AOAC
15
Read Data Hold Time
t AOH
10
-
10
-
ns
16
Read Data Turn Off Time
t Aoz
-
60
-
60
ns
17
DTACK Delay Time (Z to l)
tOTKZL
2-4
-
70
-
70
ns
1S
DTACK Delay Time (0 to l)
tOTKOL
2,4
-
ns
19
DTACK Release Time (l to H)
20
DTACK Turn Off Time (H to Z)
tOTKZ
21
Data Bus 3 State Recovery
Time 1
tOBATl
22
Write Wait Time
tWWAI
23
Write Data Setup Time
twos
24
Write Data Hold Time
t WOH
tOTKLH
2-4
0
-
0
SO
-
SO
ns
100
-
100
ns
2,4
0
-
0
-
ns
0
40
-
ns
40
-
0
3,4
10
-
ns
10
•
-
ns
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
475
HD63484----------------------------------------------------------DMA R••dlWrlt. Cycle Timing
No.
Item
Symbol
Reference
Figure
Number
8MHz
Version
9.8 MHz
Version
Max
Min
Max
110
-
110
ns
70
ns
ns
60
-
0
25
DREQ Delay Time 1
tOROO1
26
DREQ Delay Time 2
tOROO2
-
27
DMA RIW Setup Time
tOMRWS
50
28
DMA RIW Hold Time
29
DACK Setup Time
tOMRWH
t OAKS
40
30
DACK "High" Level Width
tWOAKH
60
-
0
-
5-8
Unit
Min
0
70
50
0
40
ns
ns
ns
31
32
DMA Read Wait Time
33
DMA Read Data Access Time
34
DMA Read Data Hold Time
35
-
ns
-
80
-
80
ns
10
-
10
-
ns
-
60
-
60
ns
-
70
-
70
ns
-
ns
tORW
5,6
DMA Read Data Turn Off Time
tOROAC
tOROH
tOROZ
36
DMA DTACK Delay Time (Z to L)
tOOTZL
5-8
37
DMA DTACK Delay Time (D to L)
tOOTOL
5,6
38
39
DMA DTACK Release Time (L to H) tOOTLH
DMA DTACK Turn Off Time (H to Z) tOOTHZ
40
DONE Output Delay Time
t ONO
41
DONE Output Turn Off Time (L to Z)
tONLZ
42
Data Bus 3 State Recovery Time 2
43
DONE Input Pulse Width
44
DMA Write Wait Time
toww
45
DMA Write Data Setup Time
46
DMA Write Data Hold Time
towos
tOWOH
tOBRT2
tONPW
5-8
0
-
0
-
80
-
80
ns
100
-
100
ns
-
70
-
70
ns
-
80
-
80
ns
5,6
0
5,8
2
7-8
40
0
10
-
0
-
Clk.
-
0
-
ns
40
-
10
ns
-
ns
2
47
$
476
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
ns
----------------------------------------------------------------HD63484
Frame Memory Read/Write Cycle Timing
No.
Item
Symbol
Reference
Figure
Number
8 MHz
Version
9.8 MHz
Version
Unit
Min
Max
Min
Max
-
ns
50
ns
48
AS "Low" Level Pulse Width
t pwASL
25
-
20
49
Memory Address Hold Time 2
tMAH2
10
-
5
50
AS Delay Time 1
tASDl
-
60
51
AS Delay Time 2
tASD2
5
65
5
40
ns
52
Memory Address Delay Time
tMAD
15
70
10
50
ns
53
Memory Address Hold Time 1
tMAHl
25
-
15
-
ns
54
Memory Address Turn Off
Time (A tol)
tMAAZ
-
50
-
35
ns
55
Memory Read Data Setup Time
t MRDS
35
tMRDH
10
-
ns
Memory Read Data Hold Time
-
30
56
57
MAIRA Delay Time
tMARAD
9-12
-
80
-
60
ns
58
MAIRA Hold Time
tMARAH
9-11
10
-
5
-
ns
59
MCYC Delay Time
t MCYCD
9-13
5
60
5
40
ns
60
MRD Delay Time
61
MRD Hold Time
62
DRAW Delay Time
63
9-12
9, 10, 12
10
tMRDD
-
70
tMRH
10
-
t DRWD
-
70
DRAW Hold Time
t DRWH
10
-
64
Memory Write Data Delay Time
t MWDD
-
70
65
Memory Write Data Hold Time
t MWDH
10
110
Memory Address Setup Time 1
t MASl
9-12
10
112
Memory Address Setup Time 2
t MAS2
9-12
10
-
9-12
11
-
0
5
5
5
10
10
ns
ns
50
ns
-
ns
50
ns
-
ns
50
ns
-
ns
ns
ns
NOTE 1) Characteristic of No. 52 is defined independently of 2CLK operation frequency (f) and timing of No. 51
and No. 110.
.HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
477
HD63484-------------------------------------------------------------Display Control Signal Output Timing
No.
Item
Symbol
67
HSYNC Delay Time
tHSD
68
VSYNC Delay Time
tVSD
69
DISP1, DISP2 Delay Time
tDSPD
70
CUD1, CUD2 Delay time
71
EXSYNC Output Delay Time
!cUDD
I EXD
72
CHR Delay Time
Reference
Figure
Number
12-14
13
tCHD
8MHz
Version
9.8 MHz
Version
Min
Max
Min
-
70
70
-
20
70
-
70
70
70
Unit
Max
50
ns
50
ns
50
ns
50
ns
15
50
ns
-
50
ns
73
74
EXSYNC Input timing
No.
Item
Symbol
75
EXSYNC Input Pulse Width
t EXSW
76
EXSYNC Input Setup Time
I EXS
77
EXSYNC Input Hold Time
I EXH
8MHz
Version
9.8 MHz
Version
Reference
Figure
Number
Min
3
-
3
50
-
30
-
t eve
14
10
-
ns
Max
15
Min
Unit
Max
ns
LPSTB Input Timing
No.
Item
Symbol
Reference
Figure
Number
8 MHz
Version
Unit
Min
Max
Min
Max
45
10
-
ns
10
-
4
-
4
-
t eve
78
LPSTB Uncertain Time 1
I LPD1
70
79
LPSTB Uncertain Time 2
t LPD2
10
80
LPSTB Input Hold Time
I LPH
81
LPSTB Input Inhibit Time
t LPI
15, 16
9.8 MHz
Version
10
ns
ns
RES Input and DACK Input Timing
No.
Item
82
DACK Setup Time for RES
83
DACK Hold Time for RES
84
RES Inpulse Pulse Width
Symbol
Reference
Figure
Number
tDAKSR
17
tDAKHR
tRES
•
478
9.8 MHz
Version
8MHz
Version
Unit
Min
Max
Min
Max
100
-
100
0
10
-
10
-
0
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
ns
ns
t eve
--------------------------------------------------------------HD63484
IRQ Output, Video Attributes Output Cycle Timing
No.
Item
Symbol
85
IRQ Delay Time 1
86
IRQ Delay Time 2
tlR01
tlR02
87
ATR Delay Time 1
tATR01
88
ATR Hold Time 1
tATRH1
Reference
Figure
Number
18, 19
12
9.8 MHz
Version
8MHz
Version
Unit
Min
Max
Min
Max
-
150
ns
500
ns
80
-
150
500
60
ns
10
-
5
-
ns
-
80
-
60
ns
10
-
5
-
ns
89
90
ATR Delay Time 2
tATR02
91
ATR Hold Time 2
tATRH2
12
MPU Read/Write Cycle Timing (synchronous bus),
DMA Read/Write Cycle Timing (synchronous bus)
No.
Item
100 CS Cycle Time
101
CS "Low" Level Width
102
CS "High" Level Width
Symbol
9.8 MHz
Version
Min
Max
Min
Max
4
2
-
4
2,3
2
-
-
2
tcsc
tWCSL
tWCSH
8MHz
Version
Reference
Figure
Number
2
2
Unit
tCYC
tCYC
tCYC
103
104
DACK Cycle Time
tDACKC
105
DACK "Low" Level Width
tWDACKL
106 DACK "High" Level Width
tWDACKH
4
6,8
2
2
4
2
-
tcvc
tc c
t cvc
Jc----:L 2 .2V
O.7V
Figure 1
2CLK Waveform
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
479
:r
o
@
@)1@5
.j>.
co
o
en
w
.j>.
co
.j>.
2CLK
R/W
I
~
-----'
:!.
»
3
~
o·
III
RS
~
v''"+r:1 7.% I
IIII
I~!=ttY.i14ri.
I vI
"
I,
I~rt'Y IV
*t~.IV
~I
v IV
hlfT
•
-tt VI~I
. IV
cs
Rl
o
o
•
oi~
o(j)
I--~-I~-I
«< Vcc
D0 - D15
1"10\1
20V
"
if
I~~~I
VcC2b'IT
~{{Vcc 2.0V
II
no\}
AO\}
!I
if
I~
VcC2.V
II
1"10\/
~MI I
n
:arVcc
2~·--.-.
1'\0\1
II
...........
CD _
?tI:
~ ~
tv.v.
DTACK
000
gJ
'-
o
~
I:
,.
I~
Asynchronous bus timing (1)
.(.
Asynchronous bus timing (2)
.(_
Synchronous bus timing
(The MPU read cycle timing
.1
IS
fixed.)
()
»
"'CDr->"
W
T,
T3
To T7 To T, T2 T3 T. Ts To T7 T. T9 TID Tll T12 T'3 To
T3 T. _Ts To
T2 T3 T. Ts
2CLK
I
~
RIW-
~
»
3
:on
'"
RS
III
~
~
CS
o
01.
o
o
ro
•
-
Do-DIS
rnO
~ :I
'-
DTACK
~:I
:;)
c:
~
'" ):Ii
@
~
()
(Note) When the MPU read cycle Immediately follows the MPU writ~e execution, DTACK and
the read data responses delay (by 3 tcyc) even though spec Q£3) IS satlsfled_
»
~
~
~
-!!!
'"
~
00
g
Figure 4 MPU ReadlWrite Cycle Timing (MPU -
ACRTC)
CD
"'"
"'"
Figure 5 DMA Read Cycle Timing (System Memory
....
(Xl
CAl
+-
ACRTC)
J:
o
Ol
CAl
....
(Xl
....
:I:
o
C»
w
"""
~
it
"""
2CLK
:I:
ii
0
DREO
:!:
l>
3
CD
5"
D>
RIW
!:
?I\)
I\)
DACK
0
0
~.
00-0,.
~%
:::J
c:
CD
~
000
~ %
<0
~
DTACK
(READY!
DONE (Output!
(')
l>
co
~
~
~
.!!!
....
~
co
~
@.
@ ,
(Note) DACK "high" level width must satIsfy spec
Unless satisfying spec
DTACK and the read data delay to the succeeding cycle
When the ACRTC is used with the synchronous bus tlmmg, specificatIOns
and @must be satisfied
@ ,@
• DONE needs to be asserted "Low" while
DACK remaIns "Low". DONE "Low" width
must satisfy spec.
@.
0
Figure 6 DMA Read Cycle Timing (System Memory -
ACRTC): Burst Mode
,rlh
v.,y~
2CLK
\....1
To
\
\
T,
T2
T3
T.
,,r-f!-\
,
~
...J
----,
:I:
S
0
DREO
I
Tn-2
Tn-1
Tn
\
\
~
I--
08V
=.
>
3
CD
B
III
RIW
!:::
P-
I\>
~
01.
/I
0
0
Q.
CD
DACK
2.2V
tl
.+22V
•
_
~J:
::l
~ ~
Do-D,.
~2.2V
IIH
~
c-
r.:
(')
DTACK
(READY)
.l.O.8V
,
co
;
00iiiE
(Ouputj
i"0.8V
@.
~
0
!!!
~
8'"
@
J:
>
~
~
O.7V
I@I
000
o
~22V
O.7V
(I
II
DONE Onput)
~O.7V
Figure 7 DMA Write Cycle Timing (System Memory -
I~
}
*'i5Q"NE needs to be asserted "Low" while
i5AcK remains "LOw"~ONE "low" WIdth
must satlsfv the spec
ACRTC)
:I:
0
""
00
C1I
C»
W
""
""
00
J:
C
co
Co)
~
co
co
i
2CU<
r'
"
"
-.I
~_
:I:
~
DREQ
:r.
~
CD
5'
0>
I I'
II
RiW
~
2,2V
DACK
~
o
O, 7V
o
~.'
~:t
2.
CD
CD
•
~ ~
~
t...
;
'1;!.!:t1
Do-D15
_
(J)()
t
@
.1 ,.
(i4)---+I
DTACK
(READY)
:t
DONE (Output)
~
!!i~
~
i
DONE (Input)
II
"
®
@d
~
0l'IL J7V
II
@.
(Note) DACK "hlQh" level width must satISfy spec
Unless satisfying spec
DTACK response delays to the succeedIng cycle,
When the ACRTC IS used with the synchronous bus timing. specifIcatIons
and @must be satisfied.
@ .@
,...-------
whJ!!!..
• DONE needs to be asserted "Low"
DACK remaIns "low".
DONE "low" width must satisfy spec ~
Figure 8 DMA Write Cycle Timing (System Memory
--+
ACRTC): Burst Mode
--------------------------------------------------------------HD63484
2CLK
MADo-MAOI~
MAD 1f;/RAo- MA .91RA3
RA.
MCYC
MRD
DRAW
-----+-'
Figure 9 Display Cycle Timing
2CLK
MAD.-MAD"
MADla/RAo -MAIg/RA3,
RA.
MCYC
MRD
Figure 10 Frame Memory Read Cycle Timing
(ACRTC - Frame Memory)
•
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
487
HD63484----------------------------------------------------------------2CLK
+ __...(1
MAD, - MAD" _ _ _ _ _
MAD 16/RAo-MA 19/RA3 ,
-----+--.. 1=......,=~--+--------".-i:;-;;,d.
RA.
MCYC
MAD
Figure 11 Frame Memory Write Cycle Timing
(ACRTC -+ Frame Memory)
Refresh Cycle
Attribute Control Information Output Cycle
2CLK
MAD, -MAD,;
----+-{I~=-....ilJ~~1
MADlfl/RAo-MAI9/RA3,
RA.
MCYC
MAD
----+.
------+e,
DAAW - - - - + - e ,
HSYNC
*When
AS IS "H Igh"
Figure 12 Frame Memory RefreshNideo Attribute Output Cycle Timing
~HITACHI
488
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
--------------------------------------------------------------HD63484
2CLK
07V
MCYC
Vcc- 20V
VCC~
20V
Vee-20V
EXSYNC
Vcc- 20V
oav
(Output)
Vcc- 20V
CHR
oav
Figure 13 Display Control Signal Output Timing
22V
2CLK
HSYNC
(SLAVE)
(Sync Cycle)
Tl
T2
T3
T4
T5
T6
2CLK
EXSYNC
-G:
MCYC
MCYC
-'-.,
(Phase Not Shiftecl
(When the leading edge of EXSYNC enters this penod, ACRTC shifts the internal phase according to
the above sequence.)
Figure 14 EXSYNC Input Timing
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
489
HD63484---------------------------------------------------------------Smgle Access Mode
Display Cycle
(LPSTB RISe Cycle)
2CLK
MCYC
MAD,
-MAD,s
LPSTB
(hen LPSTB rISes In thIS period, memory address "M + 2" IS set
Pen Address register
In
the Light
Note 1 Memory addresses "M", "M+ 1", "M+ 2", and "M+ 3" denote the display addresses
Note 2 Memory address set In the Light Pen Address register dUring H~sync cycle
may not be proper
Figure 15 lPSTB Input Timing (Single Access Model
Interleave Mode/Supenmpose Mode (Dual Access Mode all)
1 - - - - - - - Display
Cycle - - -
2CLK
MCYC
LPSTB
LPSTB
Note 2
Note 1 Memory Addresses "M", "M+ 1", and "M+ 2" denote the display addresses In 'the Interleave Mode, and
those of the background screen In the Superimpose Mode
Note 2 When LPSTB nses In the penod (1), memory address "M+ 1" IS set In the Light Pen Address register
Note 3 When lPSTB rises In the penod lZI, memory address "M+ 2" IS set In the lIght Pen Address regIster
Note 4 Memory address set In the LIght Pen Address regIster dunng H-sync cycle may not be proper
Figure 16 lPSTB Input Timing (Dual Access Model
~HITACHI
490
Hitachi America Ltd, • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63484
°
7V
1---+1-"1
°
7V
22V
1-_ _ _ _-\07V
Figure 17 RES Input and DACK Input Timing
(System Reset and 16-bit/8-bit Selection)
2CLK
Figure 18 IRQ Output Timing
2CLK
00-015
---~_1~Hl:~~~]-----II--t:;:_-------_1_:;:_--@
TRQ ----------------1J~--_'I Vee - 20
This is an IRQ output timing example. In this case, IRQ is generated by status
flag RFF (Read FIFO FuJI).
When issuing read commands (RD) which transfer data exceeding Read FIFO
space (8 words), the FIFO becomes full, and the command execution pauses (RFF:
set, IRQ: generated). By reading out I-word data, spare occurs in the FIFO, and the
ACRTC resets RFF flag and then negates IRQ, while on the other hand the
ACRTC resumes the internal operation (command execution) to fill the FIFO, and
sets RFF flag and then asserts IRQ again.
In this case, the timing from IRQ negate to assert is 3 cycles (tcyc).
Figure 19 IRQ Ou~put Timing (Example: Read FIFO Full interrupt Enable)
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
491
HD63484--------------------------------------------------------------
Stgnal
s.ov
load conditton
Do - 0,.
DTACK
DREO
MADo - MAD,.
MA'6/RAo - MA,oIRA3
RA,
VSYNC.~
EXSYNC
MCYC. AS'. MRD
DRAW. CHR
DISP1.~
CUD1, 'CUI5!
RL
Rl= 1.SKO
C=40pF
R = 10 KO
AU diodes are
1S2074H's or
the equivalent
Figure 20 Test Load Circuit A
s.ov
Figure 21 Test Load Circuit B
Power on Sequence
(Note)
When tumlng power on. 2ClK and RES tImIngs must be
as shown in ftgure E22 The delav ttme from Vee risIng to
2ClK nsmg (t:2CH) must be under 100 ms. and that from
Vee nsmg to RES risIng (IREH) must be above 100 ms
Vee
2.2V
2ClK
-----t-.-.............L K . - IREH> 100 ms
RES
07V
. Figure 22 Power On Sequence
.HITACHI
492
HItachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (40S) 435-8300
Ringing Noise and Damping Resistor
If excessive ringing noise occurs on CRT data bus (figure E23), damping resistors may be required for the data bus as shown in figure E24.
Vout
MADoL-~\1\1\
ACRTC
t
Damping Resistors
Note The nngmg level depends on the load
0 1V
capacity. and It can be VOL
(50-100n)
+
Figure 23 Ringing Noise
Figure 24 Damping Resistor
Note for Designing Power Supply Circuit
r - -
-L-........--I.....L.~_ - - ,
I
I
I
I
I
Vss (55)
Vcc
1-....--4-vss
(14) Vcc Vss (51)
(16) Vss Vcc (49)
1-""--4-Vcc
Vss
+
1/
20
~
DRAW
MRD
CHR
MPU
Interface
II
CCUD
,
CRT
Interface
~ CDi5'i.
CUD2
GCUD
2
HSYNC
VSYNC
- F '
~
EXSYNC
Timing
Processor
-
-
VSYNC
1-- EXSYNC
DISP
1- DISP 1. DISP2
MCLK
f-
2
AS
2CLK
MCYC
f-
1-'-- 2CLK
f2 t2
Vcc Vss
Figure 27
•
Block Diagram
HITACHI
Hitachi America Ltd • 2210 O'Toole Avenue • San Jose, CA 95131 • (40B) 435-8300
495
HD63484-----------------------------------------------------------coded start dot address which is used to control the external
shift register load timing and data. HSD usually corresponds
to the start dot address of the background screens. However,
if the window smooth scroll (WSS) bit of OMR (Operation
Mode Register) is set to 1, HSD outputs the start dot address
of the window screen segment.
Note) HSD outputs the valid value only within the specified
raster area. Changing the register contents during the
scanning does not cause any external etTects, because
the value loaded at the beginning of the area is reserved.
Video Attribute.
The ACRTC outputs 20 bits of video attributes (Figure 28) on
MADo-MAD I5 and MAI6/RAo-MA19/RA3' These attributes are
output at the last cycle prior to the rising edge of HSYNC and
should be latched externally. Thus, video attributes can be set on
a raster by raster basis.
BLlNK2
BLINK1
SPL2
SPL1
MA,.
MA,.
MA17
MA,.
HZ3
MAD,.
l
I
I
Blink
Split Screen Number
Horizontal Zoom Factor (HZO-HZ3: MAD I2 -MAD 16)
These lines output the encoded (1-16) horizontal zoom factor
as stored in the Zoom Factor Register (ZFR). Horizontal
zoom is accomplished by the ACRTC repeating a single display address and using the HZ outputs to control the external
shift register clock. Horizontal zoom can only be applied to
the Base screen.
Horizontal Zoom
MAD,.
MAD"
HZO
HSD3
Honzontal Scroll Dot
HSDO
ATC7
Split Screen Code (SPL1-SPL2: MA .. -MA 17)
These lines present the encoded information showing the split
screen currently being displayed by the ACRTC.
Attribute Code
ATCO
Figure 28
Video Attributes
Attribute Code (ATCO-ATC7: MADo-MAD,)
These are user-defined attributes. The programmed contents
of the Attribute Control bits (ATR) of the Display Control
Register (OCR) are output on these lines.
Note) The data written into ATR can be externally used after
the completion of current raster scanning.
Attribute Code (ATCO-ATC7) Application
The following shows some application examples.
(I) Amount of horizontal dot shift for window smooth scroll.
(2) Horizontal width of crosshair cursor and the amount of
horizontal dot shift (including Block cursor).
(3) Frame butTer specification in blocks (used for the base
register).
(4) Back ground screen color or character color code.
(5) Display screen selection during screen blink (used with
SPL).
(6) Interrupt vector address storage.
(7) Polarity selection of horizontal/vertical synchronization
signal.
(8) Blinking signal for indicator lights.
(9) Code storage (max. 8 bit), selection signal, etc.
Horizontal Scroll Dot (HSDO-HSD3: MAD,-MAD ll )
These are used in conjunction with external circuitry to implement smooth horizontal scroll. These lines contain the en-
•
496
SPL2 SPLl
o
0
Out of background screen
o
1
Base Screen
1
0
Upper Screen
1
1
Lower Screen
Even if the split screen display is prohibited, SPL is output if
the area is specified.
Blink (BLlNKI-BLINK2: MAlO-MAID)
The lines alternate from high to low periodically as defined in
the Blink Control Register (BCR). the blink frequency is specified in units of 4 field times. A field is defined as the period
between successive VSYNC pulses. These lines are used to
implemen t character and screen blinking.
•
ADDRESS SPACE
The ACRTC allows the host to issue commands using logical
X-Y coordinate addressing. The ACRTC converts these to physical linear word addresses with bit field otTsets in the frame butTer.
Figure 26 shows the relationship between a logical X-Y screen
address and the frame butTer memory, organized as sequential 16
bit words. The host may specify that a logical pixel consists of 1,
2, 4, 8 or 16 physical bits in the frame butTer. In the example, 4
bits per logical pixel is used allowing 16 colors or tones to be
selected.
Up to four logical screens (Upper, Base, Lower, and Window)
are mapped into the ACRTC physical address space. The host
specifies a logical screen physical start address, logical screen
physical memory width (number of memory words per raster),
logical pixel physical memory width (number of bits per pixel)
and the logical origin physical address. Then, logical pixel X-Y
addresses issued by the host or by the ACRTC Drawing processor are converted to physical frame butTer addresses. The
ACRTC also performs bit extraction and masking to map logical
pixel operations un the example, 4 bits) to 16-bit word frame
butTer accesses.
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63484
Loglca' Actd ....8lng
PhYllcol Add.... lng
Display Screen
IF..me Buffo.1
bit
o
SAD
bit
16
y
Y-~~V
!
Ongl"
-----
Figure 29
-----
X
.--- ---.---
Logical/Physical Addressing
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
497
HD63484----------------------------------------------------------------
7
15
I
I
Address
R~ister
0
Hardware ,,/
I} Aeces;!:",,'"
I
Status Register
L~~ -_-~ -}JfQJ~!ri~=====$
I
I
I
\
Command Control Register
0eeration Mode R~ister
I
I
Display Control Register
~
Timing ~ontrol RAF1I
-~~~~~~~""'-----------------~
////
0
__ ___
o
15
,-,
\
Write FIFO
\
,,
,,
\
Raster Counter
Horizontal sync.
Horizontal Display
Vertical Sync.
........ ,
-
,,
,,
,
Read FIFO
\
Vertical Display
~t
Spilt Screen Width
Command ~ster
Blink Control
Horizontal Window
Isp ay
Vertical Window Display
Control
Register
Direct
fo.ccess
Graphic Cursor
Display Control RAM
Split Screen
o·
Pattern
16 X 16
RAM
Control
(Upper Screen)
Split Screen 1
Control
(Base Screen)
FIFO Access
Split Screen 2
Control
(Lower Screen)
Color 0
Color 1
Color Comparison
Edge 0 or
Mask
Split Screen 3
Control
(Window Screen)
Block Cursor
Pattern RAM Control
DraWing
Parameter
Register
Area Definition
Cursor Oe inltlon
Zoom Facter
ReadIWrite Pointer
Light Pen Address
Drawing Pointer
Current Pointer
Figure 30
Programming Model
~HITACHI
498
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
----------------------------------------------------------------HD63484
Table 1
CS RS
:w ~~g
I
0 0 0
0 0 I
Programming Model (Hardware Access, Direct Access Registers)
Register Name
AR Address Register
SR Status Register
'/0 rOO FIFO Entry
Vi r02 Command Control
Va r04 Operation Mode
'/0 r06 Display Control
rOB
(undefmed)
Abbre
AR
SR
FE
CCR
OMR
DCR
15
14
13
DATA (H)
12 11
10
.- ....... _------
1/0 r86 Vertical Sync
I/o r88 Vertical Display
Vo rSA
Vo~
Spilt Screen Width
V6
I/o
raE
r90 Bhnk Control
1/0 r92 HOrIZontal Window Display
:~~
CER ARO CEO LPO RFF RFR WFR WFE
FE
GBM
CRE ARE CEE LPE RFE RRE WRE WEE
RAM
GAl
ACM
DSK
RSM
AT R
SE3
----_ ... _---------_ ...
RCR
HSR
HDR
VSR
VOR
RC
HC
H0 S
HSW
HDW
VC
V DS
V S W
S P I
S PO
S P2
BON2
SSW
BCR
HWR
Vertical Window Display
VWR
Graphic Cursor
GCR
1/0 r98
l/o~
Address
ABT PSE DDM COM DRC
MIS STR ACP WSS CSK
DSP SEI
SE~
SE2
r1E
1 rBO Raster Count
1/0 r8Z HOrIZontal Sync
r84 HOrizontal 01 splay
DATA (L)
4
3
...... -_. __ .... -.---
BOFFI
BONI
H WS
C X E
C X S
CYS
C Y E
1/0 r9C
-
r9E
-
~
I/o
raE
rCO
_._._ .. _.... _---
(undefined)
Raster Addr 0
BOFF2
HWW
V WS
VWW
RARO
LRAO
F RA0
l/o~ Upper ~M'iCe=m:::orc'Yc;:W"'ld;.thc--nO+.i:.;;;<;.+=,,----'-----,-'~~------l--~=-L---'--"-'-'-"-----1
MWRO CHR
MWD
~~
1/0 rCS
Screen Start Addr.O
4~Ba~
~~
Raster Addr 1
SARO
RARI
SDAO
SAOH/SRAO
SAOL
L RA I
F RA I
r.M'iCe=m=or~yc;:W~,d~th~IiT.~~~~-----'----,~~~----~----ov""~----~~~------1
MWRI CHR
MWI
Screen Start Addr
SARI
S D A I
SA1H/SRAI
SA I L
RAR2
L RA 2
F R A 2
~~
~R'iCa~~e~r~Ac;:d~d~r2~+T.:.;;;<;.+~,,_-----'---_.-'~~~-----l----~~~----~~~----__1
l/og Lower Memory Width 2 MWR2 CHR
M W2
:~~
SDA2
SA2H/SRA2
SAR2
SA 2 L
Raster Addr 3
RAR3
L RA 3
F R A 3
l/o~ Wmdow r.M'iCe=m=orc'yc;:W~,d'"'thc--n3+.i:.;;;<;.+=,,----'-----,-'~-"-'---~---..-,""~---'--"-'"'-"-----1
MWR3 CHR
MW3
SDA3
SA3
H/SRA3
~~ Screen Start Addr 3
SAR3
SA 3 L
B C WI
B C SRI
BC E R I
BCURI
:~~ Block Cursor 1
B CA I
B C W2
BCSR2
B C E,R 2
BCUR2
~~ Block Cursor 2
BCA2
1/0 rES Cursor Definition
COFFI
CDR
CON2
COFF2
CM
CONI
1/0 rEA Zoom Factor
ZFR
HZ F
VZ F
CHR
l~,
L~A~
LPAR
1 I rEE ILight Pen Address
LPAL
rFO
Screen Start Addr 2
I/o rDS
---_ .. ---------
rfE (undefined)
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
499
HD63484-----------------------------------------------------------ABT
ACM
ACP
: Abort
: Access Mode
: Access PriOrity
MIS
PSE
RAM
RC
RFE
RFF
RFR
RRE
RSM
SEa
SEI
SE2
SE3
STR
VC
VDS
VSW
WEE
WFE
WFR
WRE
WSS
: Area Detect
: Area Detect Interrupt Enable
: Attribute Control
: Coomoan
.j:>
co
DA 1 (SUPERIMPOSED ACCESS MODE)
.j:>
Display Cycle
2CLK
AS
~:~
I
~.
;!
»
3
~
1';-
'HIGH'
'"
. ~ !': !';
liRAW
~
AS
oI@
Q. •
MA/RA/CH
o
MAD
~:I
;
-
A
A
oU>
I-
As
MAO
~
MA/AA/c';HR
~
.$
...
.1
ZOOMING CYCLE
Drawing Cycle
()
§
~
MAD
ORA~HIG~H~--------------------------------------------------------------------------------------------4---
on
»
~
f----J
A
A
A
A
A
0
A
~
A
0
A
MCVC
~
r-
MRO
DRAW
READ
'"00
U1
'"
:5
~
A
A
MCYC
UlC')
:I
A
A
A
CD
?lc-
A
WINDOW
BACK GROUND
Display Cycle (x2 Zoomed)
I\)
I\)
~
~
DISPLAY CYCLE
o
::J
~';
Figure 41
Superimposed Access Mode Timing
WRITE
C!:::J.
Note) Figure 42 shows the tlmmg when
display has PriOrity, and no drawing
IS done Broken hnes mdlcate
that when drawing IS performed
CD
Split Screen
Display Cycle
Refresh Address
Output Cycle
!In DRAM mode)
~
Window
Display Cycle
CD
CI:) . Attribute Output cycle
c::::E>
Drawing-Possible
Cycle
In this cycle,
the output IS
(when no drawing
fixed at "0"
IS executed, the
output IS fixed at
(Attribute cycle)
"0")
2CLK
I
~
MCYC
»
HSYNC
~
DISPI
'3"
o·
III
[SA]
AS
o'"'"
MAD
o
MA/RA
o
•
c}~
MRD
co
~J:
-
~ ~
mO
~
c-
o(J)
!D
o
»
3\
~
-:;;;
~
-I>
'"
()1
Co
g
I----'
DISP2 IWSS=O )
~
~
f-rv vv- vv- vv- ~ ~ J\J\.J\F I-r\rVVVL
V W- w- V ~ ~ L.J\.....J ~
J:
I-'
\.J
J
~'A
~
~
o·
~
DRAW
:::E
0
0
.... ___ -1
'----"'"
"---_ ....
_ _ _ _ oJ
V- ~ ~ ~
~
~ T
5
S
T
S
S
w J.
S
',..1
\.l
\J
~ Q}---{D-- ffi--{]}-{])0
w
w
w
0
0
s J.. s
~
'- ___ J
\ _____
i\.. ___
.... _----------
AS
MAD
MAiRA
O· (Al.
I
1'-I
DRAW
DISP2 IWSS="1 "
[DA1]
AS
MA/RA
MRD
I
f-I
~"
T
'A"-1r
~ --:--
MRD
MAD
I
I
I
I
[DAO]
DISP2IWSS="1 ')
~
r'-J
J
:E
s
0
I-'
I\.. ___ J
--I
,'- _ _ _ J
I
I
I
I
I
o I
f-I
:L
s
0
'-J
~
:L
w
:E
0
\"---1
'-----'
.... -
1,. _ _ _ '
' - _ _ _ oJ
'- ___ .1
w
__ .1
,.
J
LJ
:L
~
:L
s
0
J
0
' - _ __ J
\.._--,
'----
0
0
o J..
0
.... ___ J
'-J
'J
~
___ ,
0
\- _ _ _ .1 .... - _ -
------------
I
I
I
I\..~
U
I\.J
~
~
o·
0
I
1'- - - - '
S
0
f-I
\.)
~ f..I
LJ
,'- _
__ J
1'----'
,
,
'
LJ
\oJ
,
'LJ
LJ
~~
0
S
S
0
I
1'----1
I
:E
I
,'- ___ J
A
:L
s
0
.-
'-J
~
i.e'
i
'--
--'
\... _ _ J
Figure 42
(11
~
DISP2 IWSS=·'" ')
DRAW
(11
...L
\..._---1
S
W
S
W
~
' - _ _ _ oJ
Horizontal Scan Sequence
0
S
1-- _
0
__ I
"- _ _
0
0
.1.1.. _ _ _ 1\.. _ _
'----- ------------
J:
C
Ol
CAl
.j>.
CO
.j>.
HD63484----------------------------------------------------------------(2) Graphic Address Increment Mode (GAl)
During display operation, the ACRTC can be programmed to
control the graphic display address in seven ways including increment by 1, 2, 4, 8 and 16* words, 1 word every two display cycles and no increment.
Setting GAl to increment by 2, 4, 8 or 16 words per display
cycle achieves linear increases in the video data rate i.e. for a
given configuration setting GAl to 2, 4, 8 or 16 words will
achieve 2, 4, 8 or 16 times the video data rate corresponding to
GAl = 1. This allows increasing the number of bits/logical pixel
and logical pixel resolution while meeting the 2CLK maximum
frequency constraint.
Table 6
-.........
Dot Rate
16 MHz
Graphic Address Increment Modes
32 MHz
~
SA
DA
SA
250 ns
-
500 ns
+1/2
+112
+1
2
250 ns
500 ns
+1/2
+1
+1
+2
4
250 ns
500 ns
+1
+2
250 ns
500 ns
250 ns
+4
500 ns
+S
Number of
Sits/Pixel
1
8
16
64 MHz
DA
SA
+1/2
+1
+1
+1
+2
+2
+2
+2
+2
+4
+4
+2
+4
+4
+4
+8
+S
+S
+8
+16'
+16'
+16'
+16'
12S MHz
DA
SA
+1
+2
+2
+4
+2
+2
+4
+4
+4
+8
+4
+4
+4
+8
+S
+S
+16'
+4
+S
+4
+S
+16'
+S
+16'
+8
+8
+8
+16'
+18'
+16'
-
DA
Memoryeyc
Dynamic RAM Refresh
When dynamic RAMs (DRAMs) are used for the frame
buffer memory, the ACRTC can automatically provide DRAM
refresh addressing.
The ACRTC maintains an 8 bit DRAM refresh counter which
is decremented on each frame buffer access. During ~
low, the ACRTC will output the sequential refresh addresses on
MAD. The refresh address assignment depends on Graphic Address Increment (GAl) mode as shown in Table 7.
The ACRTC provides "0" output on the remaining address
line of MAD and MA/RA.
DRAM r~Sy~crcle timing must be factored into the deterlow pulse width (HSW - specified in units
mination of
of frame buffer memory cycles).
If the horizontal scan rate is Fh (kHz), number of DRAM refresh cycles is N and the DRAM refresh cycle time is Tr (msec)
then horizontal sync width (HSW) is specified by the following
equation:
,
HSW ~ N / (Tr X Fh)
For example, if the scan rate is 15.75 kHz and the DRAMS
•
516
Table 6 shows the summary relationship between 2CLK, Display Access Mode, Graphic Address Increment, number of bits/
logical pixel, memory access time and video data rate. The frame
buffer cycle frequency (Fc) is shown by the following equation
where:
Fv
Dot Clock
N
Number of bits/logical pixel
D
Display Access Mode
1 for Single Access Mode
2 for Interleaved and Superimposed Access Modes
Graphic Address Increment (1/2, 1, 2, 4, 8, 16)
A
(Fv X N X D)/(A X 16)
Fc
-
-
+16'
+16'
-
-
-
-
-
have 128 refresh cycles of 2 ms, HSW must be greater than or
equal to 5.
HSW ~ 128/ (2 X 15.75)
4.06
=
Table 7
GAl and DRAM Refresh Addressing
Graphic Address
Increment Mode
+0 (GAI=101)
Refresh Address Output
Terminal
+ 1 (GAI=OOO)
+2 (GAI=001)
MADo-MAD7
MAD,-MAD.
+4 (GAI=010)
MAD 2 -MAD.
+S (GAI=011)
MAD.-MAD,"
+16 (GAI=100)'
MAD 4 -MAD"
+ 1/2 (GAI= 111)
110
MADo-MAD7
MADo-MAD7
HITACHI
Hitachi America Ltd .• :!210 O'Toole Avenue • San Jose, CA 95131 • (40S) 435-S300
--------------------------------------------------------------HD63484
2CLK
DiSP
tiSYNc
AS
MAD
A
MA/RA
RA'
eHR
DRAW
"High"
MRD
"High"
Figure 43
DRAM Refresh Timing
External Synchronization
The ACRTC EXSYNC pin allows synchronization of multiple
ACRTCs or other video signal generators. The ACRTC may be
programmed as a single Master device, or as one of a number of
Slave devices.
~chronize multiple ACRTCs, simply connect all the
EXSYNC pins together.
For synchronizing to other video signals, the connection
scheme depends on the raster ~de. In Non-Interlace
mode, EXSYNC corresponds to VSYNC. In Interlace modes,
EXSYNC corresponds to VSYNC of the odd field.
Note 1) The ACRTC performs the synchronization every time it
accepts the pulse input from EXSYNC in the slave
mode.
It is recommended that the synchronous pulse should
be input from EXSYNC only when the synchronization
gap between the synchronous signal of the master device and that of ACRTC in the slave mode (liSYNC
and VSYNC are output also in the slave mode.).
Note 2) The ACRTC needs to be controlled not to draw during
EXSYNC input.
Clock
Signal
~ 2CLK
ACRTC
(slave)
L. 2CLK
EXSYNC
ACRTC
(Master)
EXSYNC
e MPU INTERFACE
MPU Bus Cycle
The ACRTC interfaces to the MPU as an 8 or 16 bit peripheral as configured during RES.
An MPU bus cycle is initiated when CS is asserted (following
the assertion of RS and R/W). The ACRTC responds to CS low
by asserting DTACK low to complete the data transfer. DTACK
will be returned to the MPU in between 1 and 1.5 2CLK cycles.
MPU WAIT states will be added in the following two cases.
(a) If the ACRTC 2CLK input is much slower than the MPU
clock, continuous ACRTC accesses may be delayed due to
internal processing of the previous bus cycle.
Note) <::S "High" width must not be less than two 2CLK
cycles.
(b) If a read cycle immediately follows a write cycle, a WAIT
state may occur due to ACRTC preparation for bus 'turnaround'. However, MPUs (for example 68000) normally
have no instruction which lets a read cycle follow a write cycle immediately.
For connection to synchronous bus interface MPUs, DTACK
can simply be left open assuming the system design guarantees
that WAIT states cannot occur as described above. If WAIT
states may occur, DTACK can be used with external logic to
synthesize a READY signal.
DMA Transfer
The ACRTC can interface with an external DMA controller
using three handshake signals, DMA Request (DREQ), DMA
Acknowledge (DACK) and DMA Done (DONE).
The ACRTC uses the external DMAC for two types of transfers, Command/Parameter DMA and Data DMA. For both
types, DMA transfers use the ACRTC read and write FIFOs.
(1) Command/Parameter DMA
The MPU initiates this mode by setting bit 12 (CDM) in the
ACRTC Command Control Register to 1. Then, the ACRTC will
automatically request DMA transfer for commands and their aslong the write FIFO has space. Only cycle
sociated parameters
steal request mode DREQ pulses low for each data transfer) can
be used. Command/Parameter DMA is terminated when the
MPU resets bit 12 in CCR to 0 or the external DONE input is
asserted.
r
Leo 2CLK
ACRTC
(slave)
EXSYNC
(2) Data DMA
Data DMA is used to move data between the MPU system
Figure 44 External Synchronization
•
HITACHI
Hitachi America ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
517
HD63484-------------------------------------------------------------memory and the ACRTC frame buffer.
The MPU sets-up the transfer by specifying the frame buffer
transfer address (and other parameters of the transfer, such as
'on-the fly' logical operations) to the ACRTC. Next, when the
MPU issues a Data Transfer Command to the ACRTC, the
ACRTC will request DMA transfer to and from system memory.
The ACRTC will request DMA, automatically monitoring FIFO
status, until the DMA Transfer Command is completed.
Data DMA request mode can be cycle steal (as in Command/
Parameter DMA) or burst mode in which DREQ is a low level
control output to the DMAC which allows multiple data transfers
during each acquisition of the MPU bus.
programmable. A typical application might use the Base screen
for the bulk of user interaction, using the Lower screen for a
'status line(s)' and the Upper screen for 'pull-down menu(s)'.
The Window screen is unique, sinoe the ACRTC usually gives
the Window screen higher priority than Background screens.
Thus, when the Window, whose size and position is fully programmable, overlaps a Background screen, the Window screen is
displayed. The exoeption is the ACRTC Superimposed Access
Mode, in which the Window has the same display priority as
Background screens. In this case, the Window and Background
screen are 'superimposed' on the display.
Upper
Interrupts
The ACRTC recognizes eight separate conditions which can
generate an interrupt including command error detection, command end, drawing edge detection, light pen strobe and four
FIFO status conditions. Each condition has an associated mask
bit for enabling/disabling the associated interrupt. The ACRTC
removes the interrupt request when the MPU performs appropriate interrupt service by reading or writing to the ACRTC.
Base
Lower
1
2
3
Screen Name
Base
Base
Lower
Window
The ACRTC allows division of the frame buffer into four
separate logical screens.
o
Upper
Upper
• DISPLAY FUNCTION
• SCREEN DISPLAY CONTROL
Logical Display Screens
Screen Number
Window
Lower
Figure 45
Screen Group Name
Upper screen}Base Screen
Background Screens
Lower Screen
Window Screen
Screen Combination Examples
Frame Memory Setup
In the simplest case, only the Base screen parameters must be
defined. Other screens may be selectively enabled, disabled and
blanked under software control.
The Background (Upper, Base and Lower) screens partition
the display into three horizontal splits whose positions are fully
The ACRTC can have two types of independent frame
memories, 2M byte frame buffer and 128k byte refresh memory,
and CHR signal controls which memory to be accessed.
For the frame memory, memory width is defined by setting
up Memory Width Register (MWR), and horizontal display
width is independently defined by Horizontal Display Register
(HDR). Therefore the frame memory area can be specified
bigger than display area as shown in Figure 46.
J.o~t--------MemOry Widthl----------.,.~I
Start Address
'1
~
Vertical
Display
Display Screen Area
.. 1dth
....... ..... ,,"
:
Frame Image
:
\.
Figure 46
HoriZontal
Display Width
Frame Memory and Display Screen Area
•
518
..I
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------------------HD63484
Each screen has its own memory width, start address, vertical
display width, and attribution of frame memory (character/
graphic), and those are specified by the control registers.
Display Control
Figure 47 shows the relation between the frame memory and
the display screens.
Frame Buffer
Defined Frame Buffer
0000 for Characte-,___________ ~========-M~W~O~=======:1·1
p-~---------
----------,
i File Name: MOS
:
L_______________________ J
SARO
1--__--1.,,_,_ - - -- - - - - _.1-_ _ _ _ _ _ _ _ _ _ _ _ _ _...:::....:::-...--_ _ _--1
""""
FFFFL----l
1------MW2-----~
" , ' 1 - - - - - - - - - - - - : -1
::..:1- -- - - - - - - - - - - - - - - - - - ,
SAR2
: Left
,: Right
.......................
: Layout
: Symbol
:
!,
l . _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ...
"
Frame Buffer
for Graphic
00000
-----______
t------ MW1---!
:- -----------l
m
SAR1
I
I
I
I
I
I
lI _______________ .JI
File Name: MOS
--- -- ------ -------r---, ---- --
'.::.~----------
,
'''''''
"" r----- MW3---j
SAR3
00 !-1~
~ qp
i
________________ l ________ _
FFFFFL-__--l
Left
Right
""'"
",
"
Layout
: Symbol
......- - l_ _ _.-J
Figure 47
Frame Memory and Display Screens
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
519
HD63484-------------------------------------------------------------control are set in units of rasters.
Note a display width specified by * marked register is:
(Display width) = (Setup value) + 1 memory cycles
Figure 48 shows the relation between the control registel sand
the display screens. Registers for horizontal display control are
set in units of memory cycles, and registers for vertical display
He'
,
,
,,,
!.
,
,,
,
,,,
HSYNCl
HSW
HWS'
,, ,
'HDS"
:. !
,
-I
,,
HWW'
I.
I
!
,,
,
I
,,,
HOW'
,
,,I
~
,
,
,,
,,
,
:
Display Screen Period
~I
,,
,
Ul
------------
"0 - -
o
(Upper)
-
(Window)
(Base)
(Base)
<
n
------- - - - -
Ul
"0
'"
(Lower)
Retrace Period
Figure 4B
•
520
Display Screen Specification
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
Horizontal Sequence
Memory~
:I:
~
2CU(
>
MCYC
;;r.
3
F
CD
2"
i.
HSYNf
DiSI'i
~
DiSP2
~
o
:
I.
cJ.
CD
i!-
~
-;
g
!!i~
~
i
%
. . . .1W"mdowSIlIIt
HonzolHWS+U"M
'1.
------- -- --
• H = tHC+lI-M
Vertical Sequence
I
rnO
<..
=1
_oM
I·
•
~%
~
!Ii
(----(HDW+UoM
..
_ I Sync
WidIh
o
2.
Horlzontal~ ~
HSYNf
___
~
VSYNC
iii§ii
-11----+......
D_ I
l!iSI'2
Verda!
:-e~
I:
Vertical
syncWkIth
D_WoIth
SPo.H--......oIl••>----~
S1Irt
VDSft..
VWSoH
~erticII Window
s.t
-I· Vaticll Window Width
VSW-H
1
vww· H
I'
VCoH-:-----------------_..I1
Vlrtlcal
Cycle
Figure 49
Display Scan Sequence IHDrizDntal and Vertical)
:r
0'1
'"
c
(J)
fA)
i
HD63484----------------------------------------------------------------Graphic/Character Address Spaces
The ACRTC controls two separate logical address spaces. The
CHR pin allows external decoding if physically separate frame
memories are desired.
Each of the four logical screens (Upper, Base, Lower and
Window) is programmed as residing in the Graphics address
space or the Character address space.
ACRTC accesses to Graphics screens are treated as bit mapped using a 20 bit frame buffer address, with an address space of
one megaword (1M by 16 bit).
ACRTC accesses to Character screens are treated as character
generator mapped. In this case, a 64k word address space is used
and 5 bits of raster address are output to an external character
generator.
Multiple logical screens defined as Character can be externally
decoded to use separate character generators or different addresses within a combined character generator. Also, each Character screen may be defined with separate line spacing, separate
cursors, etc.
•
CURSOR CONTROL
The ACRTC has two Block Cursor Registers and a Graphic
Cursor Register.
- - - - - - - - - - - 1F
A Block cursor is used with Character screens. The cursor
start and ending raster addresses are fully programmable. Also,
the cursor width can be defined as one to eight memory cycles.
A Graphic cursor is defined by specifying the start/end memory cycle in the X dimension and the start/end raster in the Y
dimension.
The Graphic cursor can be output on character and Graphic
screens.
The ACR TC provides two separate cursor outputs, CUD I and
CU02. These are combined with two character cursor registers
and a graphic cursor register to provide three cursor modes.
(1) Block Mode
Two Block cursors are output on CUD 1 and CUD2 respectively.
(2) Graphic Mode
The Graphic cursor is output on CUDI. Using an external
cursor pattern memory allows a graphic cursor of various
shapes. Two Block cursors are multiplexed on CU02.
(3) Crosshair Mode
The horizontal and vertical components of the Graphic cursor are output on CUOI and CU02 respectively. This allows
simple generation of a crosshair cursor control signal.
- - - First Raster Address
--to-+-----tO-+---oo
(FAA)
HITACHI
--+O+-----~O-+--- 01
--~0T-----~04----02
~ Cursor1
---I0f-*-0*0-1i0~0~0*--03
--+-0+-------t0-+----04
-~0T-----~04----05
--+-0+-----t0-+---- 06
---------------07
L
---------------------08
ACRT[9
- - Last Aaster Address
~ Cursor2
(LAA)
Raster Address
Figure 51
Figure 50
Two Separate Block Cursors
Character Screen Raster AddreSSing
-------1F
000000
000000
000000
000000
000000
000000
000000
BCSR=07
BCER=07
BCSR=02
BCER=07
Figure 52
000000
000000
000000
00
01
02
03
-------04
-------05
-------06
-------07
-------08
BCSR=OO
BCER=02
Block Cursor Examples
~HITACHI
522
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63484
-------,Ur -------------.§/-7
-,'
o
Figure 53
Graphic Cursor
.<
;.
n
!!!.
HOrizontal Cursor Signal
________~nL______~n~_______
n
c
iil
Q
'"!!!.
ii
~
Figure 54
•
SCROLLING
Vertical Scroll
Each logical screen performs independent vertical scroll. On
Character Screens, vertical smooth scroll is accomplished using
the programmable Start Raster Address (SRA). Line by line
scroll is accomplished by increasing or decreasing the screen start
address by one unit of horizontal memory width.
On Graphics screens, vertical smooth scroll is accomplished by
increasing or decreasing the screen start address by one unit of
horizontal memory width.
~I
Crosshair Cursor
Horizontal Scroll
Horizontal scroll can be performed in units of characters for
Character screens and units of words (multi logical pixels) for
Graphic screens by increasing or decreasing the screen start address by 1.
For smooth horizontal scroll, the ACRTC has dot shift video
attributes which can be used with an external circuit which conditions shift register load/clocking.
Since this dot shift information is output each raster, horizontal smooth scroll is limited to either the Background screens or
the Window screen at any'given time. However, horizontal
smooth scroll is independent for each of the Background screens
(Upper, Base, Lower).
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 •. (408) 435-8300
523
HD63484----------------------------------------------------------------Defined Frame Buffer
([) Sta rt Address (SAR)
SAR
!
SAR'
-
--r-----------
,
I
I
I
I
--,
I
I
,
,
<2> Sta rt Address (SAR')
aD
I
I
I
I
I
:
if' ,
I
I
MOS
I
I
I
I
\crO~I~~- - ,-- - - - - -- - ~
/
,
I
I
r----L --- --- --,,
,
I
,,
I
aD
.
MOS
([) D,splay (SAR)
Figure 55
I
I
I
I
,
aD
MOS
I
I
I
I
,
I
,,
I
I
I
,
I
L ______________ .J
<2> D,splay (SAR')
Scrolling by SAR (Start Address Register) Rewrite
~L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~
Memory
Address
F'gure 56
Horizontal Smooth Scroll - Background Screen
~HITACHI
524
Hitachi Amenca ltd, • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
--------------------------------------------------------------HD63484
Background
EJ
DISP1~~____________________________~r_
DISP2 - - - - - - - - - - - - - - ,
1 Display Cycle
fFBul- E- --1.. !W'@i+,jW2E------ja..rw.!O+1!- E- --1.. ;-1
MAD
B
Background Address
Empty Cycle or Drawing Cycle
Window Addre••
W
Figure
•
57 Horizontal Smooth Scroll - Window Screen (WSS= 1)
RASTER SCAN MODES
The ACRTC has three software selectable raster scan modes
- Non-Interlace, Interlace Sync and Interlace Sync & Video. In
Non-Interlace mode a frame consists of one field. In the Interlace
modes, a frame consists of two fields, the even and odd fields.
The Interlace modes allow increasing screen resolution while
avoiding limits imposed by the CRT display device, such as
maximum horizontal scan frequency or maximum video dot rate.
Interlace Sync mode simply repeats each raster address for
both the even and odd fields. This is useful for increasing the
quality of a displayed figure when using an inter1aced CRT device
such as a Television Set with RF modulator.
Interlace Sync & Video mode displays alternate even and odd
rasters on alternate even and odd fields. For a given number of
rasters/character, this mode allows twice as many characters to be
displayed in the vertical direction as Non-Interlace mode.
Note that for Interlace modes, the refresh frequency for a
given dot on the screen is one-half that of the Non-Interlace
mode. Interlace modes normally require the use of a CRT with a
more persistent phosphor to avoid a flickering display.
Even----
Odd-----
IF
00
01
02
IF _______________ _
e
e
e
e
e
e
03 €XXXXXXX)()
04
05
06
e
e
e
e
e
e
lE---------
-IF
00 --f-i~------_____Af_
00
02 ---€E-*-3E-5)--e-E-*-3E::"~~f-- 01
---------=-/ - 03
01
02
04_-~~~_-_-_-_-_-_-_-_-_-_~-_05
03~~~~~
06-----------
04
08 -;::;:~~::::::::;:::_-
-----------------07
- ----09
05
06
- -00
OE~;:::;;:::;:::;;:::~~-
07
07
08
08 ______________ _
10~~~~:"='::=
---------------11
Non-Interlace
Interlace Sync.
Interlace Sync. &
Video
Figure 58
•
Raster Scan Modes
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
525
HD63484----------------------------------------------------------------
Dummy
[INTERLACE-SYNC)
RCR~~
1~~
1VSYNC
~ ~: ~,I~:J~================~~~~~====t==It=========::=================:==:::=========~;;;;;;;;!r---= = = = = = = =- E-V-E-N-F-'E-L-D- ~ ~ n_-l:~_+:~_-~ ~-=-F- <:~ Io :I-E- - - - - - - - - - - -_-_-_- =_O_D_D_,'_'E_lD_________---IrVSYNC
[lNT~~AC~~S~Y~N~C~&~V~I~D~E~O~)~V~~~=~O~O~O~~~~~~~H~/~2~~~V~C~~D~u~m~~~~1~~~~~~~~~~~~~~~~V~C~4~~V~C~~~
0
(~:~::~,I:::===============-EV-E-N-'F-'-E-LO-----------~=~=~=======--F.=A~I:.E-----------------_-_-_-_-____-_-_O_D_D_,'_'E_LD_________~:~~
H/2
r____
-l
(Ve Vertical Cycle)
Figure 59
•
Raster Scan Timing
ZOOMING
The ACRTC supports a zoom function for the Base screen
(Screen 1). Note that ACRTC zooming is performed by controlling the CRT timing signals. The contents of the frame buffer
area being zoomed are not changed.
The ACRTC allows specification of zoom factors (I to 16) independently in the X and Y directions.
For horizontal zoom, the programmed zoom factor is output
as video attributes. An external circuit uses this factor to condition the external shift register clock to accomplish horizontal
zooming.
For vertical zoom, no external circuit is required. The
ACRTC will scan a single raster multiple times to accomplish
vertical zooming.
lxl
3xl
~[H]
I
I
I
I
~I-
Attribute
Latch
\)
2CLKOUT
WSS
DAM
SCKE
~
I
DRAM
Control
I
/
I
~
Zoom
Control
WEO
WE1
WE2
WE3
I
I
WE
Control
~
m
ADRA- l,AADRC
j'-rLatch
I~ RAM
Add-
y
Select
~Sh~~
1-_
11
.1
V
ADRA-ADRC
Figure 2.
536
~ Addres!
,-----'
--'--
MAOIMO IM1
MA18
GMIC Block Diagram
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
FAO-FA7
----------------------------------------------------------------HD63485
2CLK Generator
Address Shifter
The 2CLK generator generates 2CLKOUT for the
ACRTC and itself by dividing the external DOTCK
signal. The ratio of DOTCK to 2CLKOUT is set externally by the CDM 1 and CDM 0 inputs.
The address shifter stores memory addresses
(MA 18-MA 0) sent from the ACRTC. It supplies
them to the RAM address section according to the
timesharing mode selected by the graphic increment
mode (1M I, 1M 0).
Attribute Latch
ADRA·ADRC Latches
The attribute latch temporarily stores the attribute
codes input from the ACRTC on MA 18-MA 0 used
for horizontal zoom (HZ 3-HZ 0) and horizontal
scroll dot (HSD 3-HSD 0).
The ADRA-ADRC latches store the lower or upper
address bits which are not supplied to FA 7-FA 0
from the memory address sent from the ACRTC. It
outputs them for the whole memory cycle.
Zoom Control
RAM Address Selection
Zoom control generates the SCKE signal from
OOTCK to control the GV AC clock for horizontal
display zooming.
The RAM address selection circuits output the
time shared row and column addresses to the frame
buffers according to the RAS and CAS timing.
Scroll Control
DRAM Control and WE Control
Scroll control generates shift load signals (SLDB,
SLDW) which control video signal generation for
the GVAC.
The DRAM and WE control circuits generate RAS,
CAS, OE, and WE signals for frame buffer access
from the ACRTC output signals.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
537
HD63485----------------------------------------------------------------
System Description
Applications
System Configuration
The GMIC provides communications between the
ACRTC and frame buffers. It contains control
circuits for generating signals necessary for the
ACRTC to access a frame buffer. In addition it
generates basic signals for operating the ACRTC
and control signals for the GVAC (Graphic Video Attribute Controller), which generates the video signals
for a CRT display.
The typical graphic system application for the
GMIC and GVAC shown in figure 3 uses two
GVACs, but the number of GV ACs used can be
changed to accommodate CRT resolution and
color/grey scale per pixel for various applications.
The GMIC receives memory addresses (MADl5"
MAD" MAI.-MAI.), address strobe (AS), memory
cycle (MCYC), draw (DRAW), memory read
(MRD) , and other ACRTC outputs, and generates
control signals for the frame buffers. The frame
buffers are generally constructed from DRAM,
since graphic systems require large memory
capacity frame buffers. The GMIC therefore uses a
DRAM-compatible multiplexing system. Through
this multiplexing, the GMIC delivers address
outputs and control signals such as RAS, CAS, WE,
and OE, acting as a direct interface between the
ACRTC and the frame buffers. Furthermore, the
GMIC generates a basic clock signal for the
ACRTC (ZCLK) by dividing the high-speed dot
clock. It also generates control signals for the
GVAC.
The GMIC's operation mode can be controlled by its
program pins. This makes the GMIC suitable for a wide
range of operations, from small, low-speed systems to
large, high-speed systems, and it allows it to flexibly
change to suit system specification changes.
Figure 3 shows a graphic system configuration
using an ACRTC, GMIC, and GVACs. Using a
GMIC for interface to the frame buffers and GVACs for
CRT video signal generation creates a flexible, highperformance graphic system with a minimum component count.
DOTCK
Frame
Buffer
MPU
Interface
MAo- FAo- r---A"C"d-:-d-:-r-e-ss-...J
MA'8 FA7
MA,sMA, 8 1--=-......-1
HM50464
HD63485
GMIC
SCKE,5[5 .ADRA -ADRC.DSPCYC
2CLK
ACRTC
-Data-
MRD, MCYC
GVAC x2
Figure 3. System Application Example
•
538
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63485
Operation
Basic Clock
Timing for signals to and from the GMIC is based
on the dot clock (DOTCK) supplied to the GMIC
and the clock output (2CLKOUT) generated by
the GMIC. 2CLKOUT is generated by dividing the
OOTCK input by the ratio selected by the CDM 1
and CDM 0 inputs. Figure 4 shows the relation
between DOTCK and 2CLKOUT. The frequency of
OOTCK depends on the speed and resolution of the
CRT display. DOTCK (in MHz) equals the horizontal resolution (pixels/raster line) by the
horizontal display raster scan period (ps per
raster) .
= [Horizontal resolution (pixels/raster) ] /
[Horizontal display period (ps) ] (MHz)
fDOTeK
The dot clock dividing mode should be chosen
considering the frame buffer cycle time and the
speed of the ACRTC used. For high· speed drawing,
a smaller division ratio should be used to supply a
higher frequency chock to the ACRTC. For
applications using low-speed frame buffers and
extermal circuits, larger division rations should be
selected to supply a lower frequency clock to the
ACRTC.
Note: The maximum DOTCK frequency is
sometimes limited by the OOTCK division ratio. If
the division ratio is 8 or 16, the maximum frequency
is allowed, but if a division ratio of 4 is used, the
DOTCK frequency is limited to 32 MHz.
Frame Buffer Control
The GMIC is designed for use with DRAM frame
buffer memories. Therefore, the GMIC generates
DRAM access signals RAS, CAS, WE, and OE.
Also, it outputs row and column addresses to the
RAM, timeshared according to RAS and CAS.
Table 5 shows the GMIC frame buffer access
modes. The memory cycles are roughly divided into
six types. They are distinguished by the ACRTC's
COM1 a
COMO ~--------------------------------------------------------OOTCK
2CLKOUT
(a)
4-division ratio mode
COM1
COMO~,_-------------------------------------------------------
OOTCK
2CLKOUT "\'-_ _ _-'
(b)
a-division ratio mode
COM1 ~-----------------------------------------------------------COMO ~-----------------------------------------------------------OOTCK
2CLKOUT
~L______________~
(e)
1 6-division ratio mode
Figure 4. DOTCK Division
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
539
HD63485----------------------------------------------------------------output signals (AS, HSYNC, DRAW, MRD).
Figure 5 shows RAS only refresh cycle timing.
Figure 6 and 7 show read and write cycle timing,
respectively.
Table 5.
Memory Cycles
AS
HSYNC
DRAW
MRD
Cycle Mode
Low
Low
High
High
Refresh cycle
RAS only refresh
Low
Low
Drawing write cycle
Memory wnte
Low
High
Drawing read cycle
Memory read
High
Low
Window screen cycle
Memory read
High
High
Background screen display
Memory read
High
High
pulse
High
High
High
Memory Cycle
No access
Note: The GMIC performs a frame buffer refresh dUring a honzontal sync penod (HSYNC=low). with DRAW high and
a refresh cycle, only RAS IS output. ~ and DE are not output.
DOTCK
AS pulse applied Dunng
{~
®
2CLKOUT ,'-_ _ _ _ _ _-'
\.
MCYC''--______________________- J
\.
HSYNC_J~____________________________________________________~r
t
AS ,'--_ _ _ _--"
~
DRAW ]
MRD
J
~
M~-MA,5 ~C==========================~--------------------------~C
:J
(
RAS~
[
MA,.-MA,.
CAS
OJ
OE~
WE~
FAO-FA7 =x~
________~R~o~w~A~d~d~r~e~ss~________JX~____________C~o~l~um~n~A~d~d~re~$~________~X
Note: DOTCK, from which 2CLKOUT is generated, is represented in
CD
16 divide, ~ 8 divide, and @ 4 divide modes.
Figure 5. RAS Only Refresh Timing
~HITACHI
540
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD63485
CD
{
DOTCK
0
@
MCYC
AS
,~
__________________________~
'1-_____
l
-1
DRAW_~~
____________________________________________________~[~
l
MRDJ
MA o-MA'5
MA'6-MA,.
~[============================~--------------------------_1[
J
(
r
RAS~
r
r
CAS~
OE~
WE~
FAO-FA7 ~~______~R=o~w~A~d=d~re=s~s________A __ _ _ _ _ _ _ _ _ _~Co~l~um~n~A~dd~r~es~s~_________(
Note: DOTCK, from which 2CLKOUT is generated, is represented in
CD 16 divide, ~ 8 divide, and @ 4 divide modes.
Figure 6. Read Cycly Timing
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose. CA 95131 • (408) 435-8300
541
HD63485----------------------------------------------------------------
DOTCK
{~
®
L
L
2CLKOUT , ' - -__________-'
MCyC\L________________________~
l
AS\~__________~
DRAW\~
____________________________________________________~[~
MRD\_~__________________________________________________~[~
M~-MA,6~[========================:J~----------------------~C
MA,e-MA,. :J
RAS~
(
r
CAS~
r
OE~
r
WE~
r
FAO-FA7
::x
Row Address
Column Address
Note: DOTCK, from which 2CLKOUT is generated, is represented in
<
...J
u
u ~
N
i:;
0...
0
a: u
:;:!l:;
Z
u
0
...
N
..,
..,.
fD
FD,
2CLK
FD,
SELO
FD3
0,
SEll
SEL2
FD.
0,
Do
FDs
FD.
03
D.
0,
FD7
Os
FDll
0,
FD.
D.
07
Vss
FD"
FD"
NC
Vss
Vss
D3
FD,
D.
FDlO
Os
FO'l
FO'2
FO'3
D.
07
COLO"'ItMN ..... CO,.....COIl)
<...JO
U
0 0
0
'"
:; :;
...
0
(II
U
cSoo>
u.u.u.
(DP-64S)
U
~
~
w
~
•
M
z 000 000 0 0
u.u.u. u.u.u. u. u.
(CP-68)
Figure 1. Pin Arrangement
~HITACHI
568
U'I
uCQOCQOO
>u..u..u..u..u..u..u..
MCYC
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63486
Power Supply (Vee, V88)
Vss and Vee are the GV AC power supply pins. V cc
pins are + 5 V ± 5% supply pins. Vss are the
ground pins. Be sure to connect all four V ss pins to
ground and both Vee pins to the power supply.
ACRTC Signals
Clock (2CLK): The 2CLK input must be the same
as the 2CLK input to the ACRTC. It is usually
supplied by the GMIC 2CLKOUT output. 2CLK is
used for data transfer between the ACRTC and
frame buffers and as a timing signal for display
data input.
Memory Cycle (MCYC): The MCYC input
specifies frame buffer access by the ACRTC. It
must be low when the ACRTC is in address cycle,
and high when the ACRTC is in data cycle. MCYC
controls the data buffers. It is usually supplied by
the ACRTC's MCYC output.
Memory Read (MRD): The MRD input controls
frame buffers. When MRD is high, the GV ACs
transfer data from the frame buffers to the ACRTC.
When MRD is low, the GVACs transfer data from
the ACRTC to the frame buffers. MRD must be held
high during a display read data cycle. Only during a
display cycle for superimposed screen data (dual
access mode!) does the ACRTC input MRD low.
This signal is usually supplied by the MRD output.
Display (DISP): The DISP input is a composite
signal indicating the screen's horizontal and ver·
tical display period. Display timing output (DISP!)
is input when the ACRTC's DSP (display signal
control) bit is set to 1. For superimposed display
(dual access mode 1), DISPl must be input to a
GV AC for background screens, while DISP2 must
be input the window screen from the ACRTC.
Data Bus (D7-Do): Dr-Do are the 8·bit data
input/output for data transfer between the ACRTC
and frame buffers. Usually, Dr-Do are connected to
8 bits of the memory address data bus (MAD 18 MADo) according to the operation mode selected
by the MODI, MODO inputs.
the direction of transfers between the ACRTC and
Table 1. Pin Description
Pin Number
Signal
DIP-64
PLCC-68
Vee
32,64
34,68
Vss
16,17, 17,18,
48,49 51, 52
2CLK
4
5
I
Clock
MCYC
3
4
I
Memory Cycle
MRD
1
2
I
Memory Read
DISP
24
26
I
Display
I/O
Description
+ 5 V power
supply
Ground
D7-Do
15-8
16-9
I/O
Data Bus
MODI,
MODO
28,27
30,29
I
Operation Mode
AM
22
24
I
Access Mode
DSPCYC
2
3
I
Display Cyele
SEL2SELO
7-5
8-6
I
Select
SCKE
25
27
I
Shift Clock Enable
SLD
26
28
I
Shift Load
FD31FDo
29-31, 31-33, I/O
33-47, 36-50,
50-63 54-67
DOrCK
23
25
I
Dot Clock
VIDEOAVIDEOD
21-18
23-20
0
Video Outputs
Frame Buffer Data
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
569
HD63486----------------------------------------------------------------
Operation Mode (MODI, MODO): The MOm
and MODO inputs specify the length of the GV AC's
internal video signal shift register and the operation
mode for the control data bus data multiplexing
between the ACRTC and the frame buffers. The
operation mode setting is closely related to the
ACRTC's graphic address increment mode (GAl),
the graphic bit mode (GEM) which specifies the
number of bits per pixel, and the frame buffer's
access mode (ACM). These settings determine the
shift length of one display cycle, and thus the
settings for MOm and MODO. The GMIC's clock
division mode (CDM1, CDMO) is also related to
MOm and MODO. Table 2 shows how GV AC's
operation mode is related to the ACRTC and GMIC
settings. Other settings are allowed in a graphic
syster with ACRTC, GMIC, GV AC, and additional
circuits. For a description of GEM, GAl, and ACM,
see the ACRTC User's Manual. For a description of
CDM and DAM, see the GMIC Data Sheet.
GMIC Interface Signals
Display Cycle (DSPCYC): The DSPCYC input
indicates whether a display cycle has been entered.
DSPCYC set low signifies a nondisplay cycle,
during which data is transferred between frame
buffers and the ACRTC. DSPCYC set high indicates
a display cycle, during which data from the frame
buffers is transferred to the GV ACs. The display
cycle signal (DSPCYC) output from the GMIC is
used for this in put.
Select (SEL2-SELO): The SEL2-SELO inputs
are the lower three bits of the address specifying a
particular word is the frame buffers to be transferred to the ACRTC. Since SEL2-SELO control the
address bus connection between frame buffers and
the ACRTC, it must be valid during a data cycle
when MCYC is set high. The address outputs
(ADRA-ADRC) from the GMIC usually supply
these signals.
Access Mode (AM): The AM input sets the
GV ACs to superimposed display mode. When the
ACRTC's access mode (ACM) set to dual access
mode 1 (ll), AM switches between two GV ACs for
background and superimposed screens. In single
access mode and dual access mode 0, AM must be
set low. In dual access mode 1, AM should be set
low for a background screen GV AC, and high for a
superimposed screen GV AC.
Table 2.
Operation Mode and GV AC, ACRTC, and GMIC Settings
GVAC
ACRTC
GMIC
MOD
0 1
GBM
GAl
ACM
1098
654
3
0
010
010
0
1
1
0
1
0
1
Shift Clock Enable (SCKE): The SCKE input
specifies the timing for driving the GV AC's
parallel-to-serial converter (shift register) for
generating video signals (VIDEOA-VIDEOD). The
GV AC's perform serial-to-parallel conversion by
shifting one bit of display data every shift clock
cycle. Using SCKE, the GV ACs generate a lower
frequency shift clock. Extending one shift clock
cycle this way allows zooming. The SCKE output
from the GMIC supplies this input.
01 1
010
01 1
01 1
01 0
o1 1
DAM
2
CDM
1 0
Bits/
Pixel
Shift
Length
Max Dot
Rate(MHz)
1
0
0
4
16
64
0
1
1
4
16
32
1
1
0
4
32
64
1
0
1
4
32
64
0
1
0
8
8
64
1
0
0
8
16
32
0
1
1
8
16
32
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
0
0
0
1
1
0
1
1
@HITACHI
570
Hitachi Amenca Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------------------HD63486
For systems with a superimpose function, SCKE
must be held high for the superimposed window's
GVAC (AM input high).
buffers. The 32 bits are read simultaneously from the
frame buffer, and FD31_FDo can be directly connected
to the frame buffer data I/O pins.
Shift Load (SLD): The SLD input specifies the
CRT Display Interface
timing in which display data temporarily stored in
the GVACs is supplied to the shift register. SLD is
asserted for one period of the dot clock. Horizontal
scrolling is implemented by shifting SLD on a dot
clock basis during a single display cycle. SLD must
be asserted once during each display cycle (shift
length). SLD is usually input from the GMIC SLDB
output for background screen GV ACs (AM input
low), and SLDW for window screen GV ACs (AM
input high).
Dot Clock (DOTCK): The OOTCK input is the
basic video signal generating clock. The DOTCK
frequency is determined by the CRT horizontal
resolution (pixel count) and the horizontal scan
display period. This clock is usually the same signal
applied to the GMIC DOTCK input.
Video Outputs (VIDEOA-VIDEOD): VIDEOA
- VIDEOD are the four bits output from the GV AC's
parallel-to-serial conversion shift register. They are
supplied during a display period specified by the
display signal (DISP). Which outputs are usable
depends on the operation mode (MODI, MODO)
input. Table 3 shows the usable video signals and
corresponding MODI and MODO signals.
Frame Buffer Data (FD31-FDo)
The 32-bit FD 31 -FDo frame buffer data I/O bus
transfers data between the ACRTC and frame
buffers and inputs display data from the frame
Table 3. Operation Mode and Video Outputs
Video Output
Mode
Bits/
MOD!
MODO
VIDEOA
VIDEOB
VIDEOC
VIDEOD
Pixel
0
0
Avail
Not avail
Avail
Not avail
4
16
0
1
Avail
Not avail
Not avail
Not avail
4
32
0
Avail
Avail
Avail
Avail
8
8
Avail
Not avail
Avail
Not avail
8
16
Shift Length
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
571
HD63486-----------------------------------------------------------------
Functional Description
Figure 2 is a block diagram of the GV AC.
SELOMODO MOD1 SEL2
ir-
d
Data
buffer
-- - - ----
;t--1\
y----y
Data
multiplexer
~
1\
A
['r-
I
----v
~
II
II
Frame
memory
data
buffer
b
I
I
I
I
I
2CLK
MCYC
DSPCY C
MRD
AM
DOTC K
SCKE
SLD
DISP
I
I
I
I
I
I
I
I
...
I
7
Latch
,,
I
I
Shift regIster
I
----{}----~
VIDEOAVIDEOD
Figure 2. GVAC Block Diagram
~HITACHI
572
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------------------HD63486
Frame Memory Data Buffer
The 32-bit bidirectional frame memory data buffer
consists of input and output buffers to transfer data
to and from the frame buffers in response to data
transfer requests from the ACRTC.
The three·state output buffer is enabled only during
a memory write cycle by memory cycle (MCYC)
and memory read (MRD) signals from the ACRTC,
and display cycle (DSPCYC) from the GMIC. A 32bit output buffer to be enabled is selected by select
signals (SEL2-SELO) from the GMIC and the
operation mode (MODI, MODO) set externally.
by select signals (SEL2-SELO) and the operation
mode (MODI, MODO) set externally to enable
transfer between the ACRTC and frame buffers.
Latch
The latch recognizes a display data read cycle by
memory cycle (MCYC) and memory read (MRD)
signals from the ACRTC, and clock (2CLK) and
display cycle (DSPCYC) from the GMIC, and the
access mode (AM) input. During a display data
read cycle, the latch temporarily stores 32-bit
display data input from a frame memory data
buffer. It sends the stored data to the shift register
for parallel·to·serial conversion.
The input buffer reads data from the frame buffers.
Shift Register
Data Buffers
The 8-bit input/output buffer transfers data
between the ACRTC and frame buffers.
The output buffer is a three·state buffer which is
enabled during a frame buffer read cycle by
memory cycle (MCYC) and memory read (MRD)
signals from the ACRTC, and display cycle (D·
SPCYC) from the GMIC.
The input buffer supplies drawing data from the
ACRTC to the frame buffers.
Data Multiplexer
The data multiplexer is a direct connection
between the frame buffers and the data buffer's
data bus which leads to the ACRTC's and frame
buffer's data bus. The bus connection in controlled
The 32-bit shift register performs parallel·to·serial
conversion on display data stored in the latch to
provide video signal output. When the latch
receives the shift load (SLDB, SLDW) and shift
clock enable (SCKE) signals from the GMIC, it
feeds the display data it has stored to the shift
register. The shift register supplies one bit of
display data every dot clock cycle while SCKE is
asserted. When the ACRTC's display cycle signal
(DISP) is negated, the shift register does not output
a video signal.
When the GMIC shifts the timing of the shift load
(SLDB, SLDW) output on a dot clock basis, the
GVAC performs horizontal smooth scrolling. When
the GMIC extends the shift clock enable signal
(SCKE) based on the dot clock, it performs
horizontal zoom.
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
573
HD63486------------------------------------------------------------__
System Description
Applications
The system example in figure 3 uses two GV ACs,
but the number of GV ACs can be varied to meet
different CRT resolution and color per pixel (or
grey scale) applications.
The GV AC internal circuits perform three major
functions:
•
•
•
Converting parallel display data read from the
frame buffers by the ACRTC to serial from and
delivering them to the CRT as video signals
Transferring data between the ACRTC and
frame buffers
Zooming and horizontal smooth scrolling
according to signals from the GMIC
The GV ACs recognize a display data read cycle by
decoding ACRTC output signals such as memory
cycle (MCYC) and memory read (MRD) and
GMIC output signals such as display cycle
(DSPCYC). In the display data read cycle, the
GV ACs latch display data from the frame buffers.
They pass the display data to the internal shift
register for parallel-to-serial conversion when they
receive the shift load signal (SLDB or SLDW) from
the GMIC. The GV ACs perform successive parallel·
to-serial conversion synchronously with the dot
clock when they receive the shift clock enable
(SCKE) output from the GMIC. This generates the
video signals.
Furthermore, the GV ACs' operation mode can be
set according to the ACRTC's operation mode by
the program input signals. This programmability
makes the GV AC suitable for a wide range of
applications, from slow, small systems to fast, large
systems. It also permits the GV ACs to accommodate system specification changes.
A GV AC can receive 32-bit display data (FD31 FDo) from one frame buffer. Furthermore, it
provides a connection from the ACRTC's data bus
(D7 -Do) to the frame buffers data bus (FD31 -FDo),
enabling direct data transfer between the two. The
GV ACs also implement horizontal smooth scrolling
and zooming, controlled by the shift load (SLDB,
SLDW) and shift clock enable (SCKE) signals
from the GMIC.
Figure 3 shows a graphic system configuration
using an ACRTC, GMIC and GVACs. With the
GMIC used for interfacing with frame buffers and
the GV ACs generating the video signals, a flexible,
high-performance graphic system is constructed
with a minimum number of parts.
System Configuration
DoreK
Frame
Buffer
MAo- FAo- r----A-dd-r-e-ss---'
MA'8 FA7
MPU
Interface
HM50464
HD63485
GMIC
ACRTC 1-_+--1
HD63484
2CLK
-DataMRD, MCYC
GVACx2
Figure 3. System Application Example
@HITACHI
574
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63486
Operation
Data Transfer
The GVACs contain control circuits for bidirectional transfer between the ACRTC and frame
buffers. To transfer data, the GVACs receive the
ACRTC's memory cycle (MCYC) and memory
read (MRD) signals, and the GMIC's display cycle
(DSPCYC). From these signals, the GV ACs
recognize a drawing data transfer cycle. Connection between the ACRTC's data bus and the frame
buffer's data bus is controlled by the select signals
(SEL2-SELO) from the GMIC and the operation
mode (MODI, MODO) inputs.
The GV ACs recognize a nondisplay cycle when
DSPCYC is low. In nondisplay cycles, the data
transfer direction is determined by the memory
read signal (MRD). MRD high signifies a read
cycle to transfer data from frame buffers to the
ACRTC. MRD low signifies a write cycle to
transfer data from the ACRTC to the frame buffers.
Timing for the data transfer is determined ~y the
MCYC input. When MCYC is high, frame buffers or
the ACRTC three-state output buffers are enabled
for transfer.
Drawing Write Cycle: The GVACs recog!1ize a
drawing write cycle when both DSPCYC and MRD
are low. Figure 4 shows the timing for a drawing
write cycle.
When MCYC is high during this cycle, the GV ACs
enable the frame memory data buffer, and output
data from the ACRTC one word at a time to the
frame buffers, based on the operation mode
(MODI, MODO) inputs and the select signals (SEL2
-SELO) from the GMIC. Table 4 shows the connections between FD and D pins when MODI and
MODO are set to 00. When SEL2-SELO are set to
000 Do-D, from the ACRTC are output to FDo-FD"
D,-D, are output to FD I6 -FD I9 , and the other FD
pins are high-impedance. Table 5-7 show the
relation of D to FD in other modes.
I
\
I
L
2CLK
"\
MCYC
"\
DSPCYC
"\
C
MRD
"\
C
SELO-SEL2
::l
C
I
x«( «( «««« ««( «««
FDo-FD"
L
}-
:::)>------------
0 0 -0 7
:J
L
I
(
)-
Figure 5. Drawing Read Cycle
(Frame buffer --+ [FD] GVAC [0]
--+
ACRTC [MAD])
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
577
HD63486
TableS.
Number of GVAC's
ACRTC
GVAC
Words
Read
Bits
Read
16
16
1 (2)'
2
32
32
2 (4)'
1
16
8
1 (2)'
2
32
16
1 (2)'
64
32
2 (4)'
32
8
1 (2)'
64
16
2 (4)
4 (8)
GBM
1)98
GAl
MOD
654
1
0
000
000
0
0
00 1
0
1
000
1
0
2
00 1
0
0
2
010
0
1
2
4
00 1
1
0
4
2
010
0
0
4
4
01 1
0
001
010
01 1
1 00
Notes: I.
2.
Bits/
Pixel
Shift
Length
1
4
8
128
32
01 0
0
8
4
64
8
2 (4)
o1 1
1
8
8
128
16
4 (8)
01 1
0
16
8
128
8
4 (8)'
'Indicates that data transfers between frame buffers and the ACRTC requires external CirCUits Since the GVACs to ACRTC data transfer
function cannot be used directly.
Parenthesized values are the number of GVACs required for superimpose mode (dual access mode 1) applications.
HM50464
Frame buffers
HD63486
GVAC1
HD63484
ACRTC
Plane 0
MAD 0, 4, 8,12
iA
D3 -D o
MAD 1,5,9,13
A
.J\
v
'I
D, -D.
Data
multiplexer
Data
multiplexer
"
...
FD'5- FD o "
....
v
I...
FD 3 ,-FD'6 '"
Plane 1
v
HD63486
GVAC2
Plane 2
MAD 2, 6,10,14
MAD 3, 7, 11, 15
A
D3-D o
1'1
A
'I
"
"
D, -D.
"v
Data
multiplexer
Data
multiplexer
IA
FD'5-FD o .J\
1'1
"
FD 3 ,-FD'6 "
1'1
Figure 6. FD Pin Connection (MODl, MODO
Plane 3
v
= 00)
~HITACHI
578
Number of
GVACs
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63486
Data Connections
Figure 6 illustrates the data pin connection with
MODl, MODO set to 00. In this mode, one pixel
consists of 4 bits, and four words (64 bits) are read
from the frame buffers at one time.
GVAC and Graphic Data: The GVAC's must be connected to handle data on a one-pixel bit plane
basis. Table 9 shows the relationshio between
operation mode 1 (MODl) , pixel number, bit plane
number, and ACRTC data.
ACRTC and GVAC Connection
Connection Between GV ACs and ACRTC:
The connection to the ACRTC depends on the
operation mode (MODl, MODO). Table 10 shows
the connection with MODl, MODO = 00. In this
mode, each pixel is four bits. GVAC1 handles bit
planes 0 and 1, and GVAC2 handles bit planes 2
and3. The conne~tion between the ACRTC and
GVAC's is determined by bit plane number and pixel
number for one word from the ACRTC. In Table 9,
for example, ACRTC pin MADO corresponds to bit
plane 0 for pixel number O. From table 10, therefore,
bit plane number 0 for GVAC1 is connected to pin
Do for pixel number 1. Connection to the ACRTC in
other modes are shown in Table 11-13.
ACRTC Display Data Bit Configuration: The
ACRTC handles display data on a pixel basis, the
ACRTC's mimimum unit. The ACRTC transfers
data on a word (l6·bit) basis. One memory word
can consist of one or more pixels. The ACRTC's
graphic bit mode (GBM) selects one of five types of
pixel count. The GVAC's directly support data transfers
of 4 bits or 8 bits per pixel. In 4 bit/pixel mode, 16 colors
or shades of grey can be implemented at one time. In 8
bit/pixel mode, 256 colors or 256 shades of grey can be
realized. Figure 7 shows pixel data processed by the
ACRTC depending on operation mode pin 1 (MODI).
For details on the graphic bit mode, see the ACRTC
User's Manual, 5.5.6 Graphic Bit Mode.
Table 9.
Pixel Number and Plane Number
MAD
MODI
a
ACRTC
Pixel No.
3
3
Bit Plane No.
1
11 1101 9 1 8
2
15 1 14 1 13 1 12
2
1
2
3
a
Pixel No.
1
7 16 1 5
1
3
a
2
J
1
4
0
7
6
5
4
3
1
2
7
a
6
bit 15
MOD1="a"
3
2
1
a
3
2
1
a
a
1
Bit Plane No.
3J2JIJ 0
a
4
5
bit a
~~i~~~~~~~~~~~~~__~~!~
One pixel
bit 15
bit a
MOD1="1"1~~i~~~~~~~~~~~~~~~~
One pixel
MAD 0
MAD 15
..
I
I
I
One word
Figure 7.
•
Pixel Data and MODI
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
579
HD63486--------------------------____________________________________
= 00
Table 10. ACRTC and GVAC Pin Connection, MODI, MODO
Mode)
MAD
Connection
15
14
13
12
11
Pin Connection
GVAC
10
9
8
D6
D6
D2
22112
33332
2
1
2
2
2
Bit Plane
3
3
2
1
0
Frame Buffer
Pixel Number
33332
2
2
2
Pixel Number
2
1
0
7
6
5
4
2
2
1
1
2
2
1
1
1
1
o
0
o
0
3
o
2
= 01
Table 11. ACRTC and GVAC Pin Connection, MODI, MODO
Mode)
MAD
Connection
15
14
13
12
Pin Connection
GVAC
4
Pixel Number
333
321
3
3
3
Bit Plane
Frame Buffer
Pixel Number
3
2
3
0
3
9
8
(4 Bits/Pixel, 16-Bit Shift
7
11
D2
10
4
2
2
1
4
2
3
2
2
1
3
2
1
o
3
2
2
2
2
5
6
4
o
2
2
3
2
o
0
1
0
o
o
0
(4 Bits/Pixel, 32-Bit Shift
2
3
3
3
2
Do
1
o
Do
Do
Do
4
3
2
o
o
o
3
2
o
o
o
o
o
o
Note: 0,-0, cannot used In this mode
Table 12. ACRTC and GVAC Pin Connection, MODI, MODO
Mode)
MAD
Connection
15
14
13
12
11
10
9
8
7
6
= 10 (8 Bits/Pixel, 8-Bit Shift
5
GVAC
4
3
2
Do
Pin Connection
2
1
2
2
2
2
1
0
o
0
o
o
o
o
7
6
5
4
3
2
o
o
0
o
o
o
Table 13. ACRTC and GVAC Pin Connection, MODI, MODO
Mode)
MAD
= 11
Pixel Number
Bit Plane
7
2
1
6
221
1
1
5
4
3
2
Frame Buffer
Pixel Number
Connection
15
14
13
GVAC
4
4
Pixel Number
1
1
Bit Plane
7
6
8
3
3
D5
2
2
1
4
4
3
3
2
2
1
0
o
o
o
o
o
5
4
3
2
o
7
6
5
4
3
2
o
o
o
o
o
o
9
In
6
5
Do
Frame Buffer
Pixel Number
Note: 07, 06, Oa. 02 cannot be used
7
11
10
4
3
Do
Do
o
o
o
o
o
2
1
Do
thiS mode
~HITACHI
580
o
(8-Bits/Pixel, 16-Bit Shift
12
Pin Connection
1
D2
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
o
Do
o
o
o
o
o
----------------------------------------------------------------HD63486
Connection Between Frame Buffers and
GVACs: Like the connection to the ACRTC, the
data connection to the frame buffers is made on the
basis of a bit plane consisting of one word, sequentially from the lower pixel address_ Table 14
shows pixel number for the frame buffer's word (16
bits) vs bit plane number for one pixel in relation to
operation mode 1 (MODI)_
and frame buffers with MODI, MODO = 00_ In this
mode, the ACRTC's graphic address increment
(GAl) is set to +4 mode, and 4-word data is
simultaneously read' from the frame buffers_
GVAC1 handles bit planes 0 and 1, and GV AC2
handles bit planes 2 and 3_ For example, pin FDo of
GV AC1 is connected to a data pin of pixel number
o of the n + 0 address of bit plane number 0_
Connections in other modes are shown in tables 16-
Table 15 shows the connection between the GVACs
18.
Table 14.
One-Word Frame Buffer Pixel Number and Corresponding Bit Plame Number
One word of frame buffer
Pixel Number
-lsTi-4-rii"i""i"2- -iiJ"iol-g}-s-- --:'--1"6-1"5"J4-- --3]-2}-;'-}-0--
MOD!
0
Bit Plane No.
3
I2 I1 I0
1
Bit Plane No.
I2 I1 I0
7
6
3
I2 I1 I0
2
5
4
3
2
3
I 21
1
1
0
7
6
1 1 0
0
5
4
1
Pixel No.
Table 15.
3
3
Pixel No.
3
2
1
0
0
GVAC and Frame Buffer Pin Connection, MODI, MODO = 00 (4 Bits/Pixel, I6-Bit
Shift Mode)
F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F
0 o 0 o 0 o 0 o 0 o 0 o 0 o 0 o 0 o 0 DOD 0 0 0 0 0 o 0 0 0
o
GVAC
3130 2928 27 26 2524 2322 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
BIt Plane No.
P,xel No.
Word Address
o
n+3
3 2 1
3 2 1
Word Address
o
n+3
3 210 3 2 1
n+O
3 2 1
3 2 1
o
o
3 2 1
n+2
n+3
o
n+1
3 210
n+O
2
3 2 1
o
n+1
3 2 1
o
n+O
3 2 1
o
3 2 1
o
n+2
n+3
3 2 1
o
n+1
1
3 2 1 0
n+O
F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F
0 o 0 o 0 o 0 o 0 o 0 o 0 o 0 o 0 o 0 DOD 0 0 0 0 0 0 0 0 0
o
Pixel No.
3 2 1
BIt Plane No.
Pixel No.
o
n+7
0
3 2 1 0 312 1 032 11013121 1 101312 1
n+2
n+4
n+3
n+6
n+5
o
3 2 1
o
n+1
3 2 1 0
n+O
1
Word Address
BIt Plane No
P,xel No.
3121110131211101312 1
n+7
n+5
1 n+6
o
3 2 1
o
n+4
3 2 1
o
3 2 1
o
3 2 1
n+2
n+3
o
n+1
3 2 1 0
n+O
2
Word Address
3121110131211
n+7
n+6
o
3 2 1
o
3 2 1
o
n+4
n+5
Bit Plane No.
4
o
3130 2928 2726 2524 2322 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word Address
3
n+1
n+2
BIt Plane No.
2
o
GVAC and Frame Buffer Pin Connection, MODI, MODO = 01 (4 Bits/Pixel, 32-Bit
Shift Mode)
GVAC
1
3 2 1
3
Pixel No.
Table 16.
o
n+2
Bit Plane No.
2
0
1
3 2 1
3 2 1
o
3 2 1
o
3 2 1
n+2
n+3
o
n+1
3 2 1 0
n+O
3
Pixel No.
3 2 1
Word Address
n+7
o
3 2 1
n+6
o
3 2 1
n+5
o
3 2 1
n+4
o
3 2 1
n+3
o
3 2 1
o
3 2 1
n+2
n+1
o
3 2 1 0
n+O
~HITACHI
HitachI America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
581
HD63486---------------------------------------------------------------Video Signal Generation
A GV AC performs parallel-to-serial conversion on
32-bit data read from frame buffers using the shift
register, and produces 4-bit video signals (VIDEOA
-VIDEOD).
The GV AC recognizes the cycle in which display
data is read from frame buffers by memory cycle
(MCYC) and memory read (MRD) signals from
the ACRTC, display cycle (DSPCYC) from GMIC,
and access mode (AM) signal externally set. The
GVAC then latches 32-bit data supplied from FDoFD31 pins.
The latched display data is fed to the shift register
on the falling edge of the dot clock (DOTCK) when
the shift load (SLD) input is asserted. This data is
then shifted on the falling edge of the dot clock
(OOTCK) when shift clock enable (SCKE) is
asserted.
As seen in figure 8, 32-bit display data is output
sequentially to four video signal pins one bit by one
bit per dot clock (DOTCK).
•
•
•
•
VIDEOA:
VIDEOB:
VIDEOC:
VIDEOD:
32 bits of FDo-FD31
24 bits of FD,-FD31
16 bits of FD ,.-FD31
8 bits of FD 24 -FD31
Using the display timing signal (DISP) from the
ACRTC, 4-bit shift register output data can be
masked. That is, while DISP is asserted, shift
register output is provided as video signals, and
while it is negated, shift register output is held low,
and video signals are not output. The required
number of dot cycles per display cycle is the same
as the shift length value set by the operation mode
(MODI, MODO).
Table 19 shows the dot clock cycle count per
display cycle vs operation mode (MODI, MODO).
Table 17. GVAC and Frame Buffer Pin Connection, MODI, MODO = 10 (8 Bits/Pixel, 8·Bit
Shift Mode)
F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F
o 0 o 0 o 0 o 0 o 0 o 0 o 0 o 0 o 0 o 0 DOD 0 0 0 0 0 0 0 0 0
31 30 2928 2726 2524 2322 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GVAC
1
2
Bit Plane No.
Pixel No.
Word Address
Bit Plane No.
Pixel No.
Word Address
3
1 0 1 o 1 0
n+3 n+2 n+l
7
1 0 1 0 1 0
n+3 n+2 n+l
2
1 0 1 0 1 0[1[0[1[0
n+O n+3 n+2[n+l[n+0
6
1 0 1 0 1 0 1 0 1 0
n+O n+3 n+2 n+l n+O
1
1 0 1 o 1 0
n+3 n+2 n+l
5
1 0 1 0 1 0
n+3 n+2 n+l
0
1 0 1 0 1 o 1 0
n+O n+3 n+2 n+l
4
1 0 1 0 1 0 1 0
n+O n+3 n+2 n+l
1 0
n+O
1 0
n+O
Table 18. GV AC and Frame Buffer Pin Connection, MODI, MODO = 11 (8 Bits/Pixel, 16·Bit
Shift Mode)
F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F F
o 0 o 0 o 0 o 0 o 0 o 0 o 0 o 0 o 0 o 0 DOD 0 0 o 0 0 0 0 0 0
31 30 2928 2726 2524 2322 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GVAC
1
2
3
4
Bit Plane No.
Pixel No.
Word Address
Bit Plane No.
Pixel No.
Word Address
Bit Plane No.
Pixel No.
Word Address
Bit Plane No.
Pixel No.
Word Address
1
1 0 1 0 1 0 1 0[1[0[1[0[1 0 1 0
n+7 n+6 n+5 n+4[n+3[n+2[n+l n+O
3
1 0 1 0 1 0 101 0 1 0 1 0 1 0
n+7 n+6 n+5 n+4 n+3 n+2 n+l n+O
5
1 0 1 0 1 0 1 o 1 0 1 0 1 0 1 0
n+7 n+6 n+5 n+4 n+3 n+2 n+l n+O
7
1 0 1 0 1 0 -1 o 1 0 1 0 1 0 1 0
n+7 n+6 n+5 n+4 n+3 n+2 n+l[n+O
0
1 0 1 0 1 o 1 o 1 0[1[0[1[0 1 0
n+7 n+6 n+5 n+4 n+3 n+2 n+l n+O
2
1 0 1 0 1 0 101 0 1 0 1 0 1 0
n+7 n+6 n+5 n+4 n+3 n+2 n+l n+O
4
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
n+7 n+6 n+5 n+4 n+3 n+2 n+l n+O
6
1 0 1 0 1 0 1 010 1 0 1 0 1 0
n+7[n+6 n+5 n+4 n+3 n+2 n+l[n+O
~HITACHI
582
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63486
Figure 9, 10 and 11 show ACRTC frame buffer
access vs video outputs in single access mode, dual
access mode 0, and dual access mode 1. Super·
imposed display in dual access mode 1 requires that
the window smooth scroll input (WSS) be high.
bit shift mode. When shift load (SLD) is asserted,
display data (FD3I - FDo) is sent to the shift register
at the rising edge of the dot clock (DOTCK) to
provide the sequential outputs. That is, video
output A (VIDEOA) receives sequential outputs
starting with FDo, and the other video pins receive
display data likewise. Figure 13 shows the video
signals output in GMIC divide·by·4 mode, GVAC in
16·bit shift mode, and the ACRTC set in dual access
mode O. Figure 14 shows video outputs in the 8·bit
shift mode, with the other conditions the same as in
figure 13.
The GV AC provides display data output se·
quentia\1y from four video outputs VIDEOAVIDEOD synchronously with the dot clock while
the shift clock enable input (SCKE) is asserted.
Figure 12 shows the video signals output in GMIC
divide·by·16 mode, GVAC's MOm, MODO == 01,32·
Table 19. Shift Length and Shift Clock
Shift
Length
Dot Clocks/
Display Cycle
MOD!
MODO
0
0
16
16
1
32
32
0
8
8
16
16
0
£~
I~~------D-i-s-PI-a-y-d-a-ta----------
"'31
bit 0
Latch ------- ..
Set timing
...
bit 0
bit 31
Shift register
Shift direction
DOTCK .I"""\J"
/
SCKE r - L - _ _S_h_i_ft_t_im_i_ng_.J.
I
bit 16
bit 24
bit 8
bit 0
VIDEOD
VIDEOC
VIDEOS
VIDEOA
'~------~~-~~-_ _ _ _ _~I
Video signal
Figure 8. Video Signal Generation
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA95131 • (408) 435·8300
583
HD63486-------------------------------------------------------------------
Base Display
~~~~~:yW-
"VV' 'JV1 f/V1 VV' f/V1 VV' /f\F J\..f1 VV"' J\...f1 VV"' VV' VV'~
-L.J ~ ~ V
~ ~ ~ 'I..-J ~ 'I..-J ~ V Vi . .
2CLK
MCVC
--
I-
l5fSP
(OISP1)
-V
V
V- V--V-- ....r- lJ"" V- u
~
MA/MAO
r--
r-
-
r-
rL
r-"
ru ru .....,
~
""'
r-
r"
I....
~
MAD
DSPCVC
r
-I---
FO
-
~
!ml
-
=
=
I +0 Scroll]
I
(SLOB)
""
l~
I
.rl<
1
VIDEO
J
!ml
,.,..
l~ ~r-
I
I
(+n Scroll)
IU
(SLOB)
,...
n<'
1
1~11
II
n dot
rru-
IU
ru- I1I
IU
VIDEO
R Refresh Cycle
A Attribute Cycle
o DraWing Cycle
Bn Base Display Cycle
Wn Wmdow Display Cycle
Figure 9. Video Output Timing (Single Access Mode)
~HITACHI
584
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-----------------------------------------------------------------HD63486
Base DIsplay
f--W,ndow_
Display
2CLK
""'.f\ji
MCYC
-~
lrv' Vv .fV1 Vv' VV' VV' ~ VV' ~ ~ ~ VV"'~
V V ~ W- W- W- W- ~ ~ V V f.-r~
--
~
01SP
(DISP')
-V
AS
MA/MAD
ru u
V
MAD
-f--- ~ 1..-~
FD
""
SLD
(SLDB)
-
'--~
\.J
[U
.."
I'---
,..,
[U
[U
Ir...
i.-
U
~
-
~
I'---
,---
"'"
1'-,..,
...
,---
-
~
~
[+0 Scroll}
I
I
ndot
I+n Scroll]
~
'1i
lr-I-
I
r - +- B'
VIDEO
SLD
(SLDB)
[U
-.... - -
Ir...
1'--
,---
[U
[U
-
Ir...
'---
1>---
DSPCYC
V
- -
"-
Ir...~ ~
W,- I-T- B 3 - I-.
H
U
IB'
VIDED
R Refresh Cycle
A Attribute Cycle
o Drawing Cycle
r--w,
B3
B4-
I-.
Bn Base Display Cycle
Wn Window Display Cycle
Figure 10. Video Output Timing (Dual Access Mode 0)
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
585
HD63486--------------------------------------------____________________
t--------8a5e Dlsplay---------i
1'4----
Window DIsplay ----<~
[Base GVAC/AM=O: )
DISP
(DISP1)
I
I
{+O Scroll}
SLD
(SLOB)
I
I
VIDEO
ndot
[+n Scroll]
~
(SLOB)
U
r--r-
I
H
U
u
VIDEO
I
(Window GVAC (AM=l»)
DiSP
(DISP2)
I I
[+0 Scroll)
"SID
(SLOW)
1
VIDEO
ndot
[+n Scroll]
"SiD
U
(SLOW)
H
2
U
Wl
VIDEO
R. Refresh Cycle
A Attnbute Cycle
o Drawing Cycle
Figure 11.
Sn Base DIsplay Cycle
Wn Window Display Cycle
Video Output Timing (Dual Access Mode 1)
~HITACHI
586
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
DOTCK
I
I
I
SUi
I
~
L1J
W-
I
:!"
»
VIDEOA
3
CD
:::!.
C)
VIDEOS
OJ
!:"
P.
16117118119120121122123124125126127128129130131\
VIDAOC
~
I
o
I
~~----------------------------------------------------------~------
VIDEOD
o
cJ.@
Q. •
I
I
CD
Number used in this timing chart are FD pin numbers.
l:I
~ ~
cnO
~ :I
c....
~
Figure 12. Video Signal Output (32·Dot Shift)
W U U U U U U U U U U U U U U U :I
~
I
o
»
~
~
I
I
I
I
I
-sID
I
L-ll
UJ
I
I
~
VIDEOA
o
~
VIDEOS
8
VIDEOC
16
VIDEOD
24
..
$
gJ
o
Number used in this timing chart are FD pin numbers.
en
CD
......
Figure 13. Video Signal Output (16·Dot Shift)
:c
cOl
~
~
I
o
0>
(11
OJ
OJ
*
0>
::t:
~
::!
»
3
,,"9a
0>
!:
".
DOTCK
~
o
•
oI~
~ J:
VIDEOA
g~
VIDEOB
o
CD
_
(flO
~ J:
<-
~
§;
'"~
~
~
S
...
~
'"g
J
~t
q
.
HR
MRD
DSPCYC
-I--
Ir--D
FD
D
61
~
~
Ir-
r-61
61
61
62
,D
62[)...........62
~
,D
D
~ ...JL1 f--.n.-I f--.n.-I ..JLJ ...JL1 f--.n.-I ~
SCKE
SU5
(SLD6)
l
l
61 .
62-
VIDEO
:-l.
o DraWing Cycle
Sn Base Display Cycle
R Refresh Cycle
A Attnbute Cycle
Figure 15. Zoom Display Timing (Single Access Mode, Quadruple Zoom)
Base Display
2CLK
MCYC
..., .li.J"'
fJVl J\J1 VV' ~ fJV' J\J1 ~ .li.J"' fJV' :,J\.n ~ VV"'J
- L J L J L I f....-J ~ L.J W- W-- ~ W-- f....-J f....-J L.J,,-
--
1'-
ffiSI'
(DiSP1)
-IJ
MA/MAD
MRO
DSPCYC
FD
~
IJ
-~ ~
IJ
~
~~
'---
'---
I'--
-r-- ' - - - rr---
D
61
~
IJ
~
~~~ ~
~
IJ
~
I'-'
IJ
~
~
~
~ r-
1'R
'---
rr--0
~
61
0
~
~
62
~
Ir0
62
~
~
0
0
~
-
,0
,0
~
nruu fIUlJU lJtnru ruuu ~ :nnnr ~~
SCKE
lm:j
(SL06)
l
61
VIDEO
R Refresh Cycle
A Attnbute Cycle
62-
h
o DraWing Cycle
Bn Base Display Cycle
Figure 16. Zoom Display Timing (Dual Access Mode 0, Double Zoom)
~HITACHI
590
Hitachi America ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
-------------------------------------------------------------------HD63486
I - - - - - - - - B a s e DIsplay - - - - - - - - t
I - - - - - W . n d o w Display - - -___
2CLK
MCYC
MA/MAO
MAD
OSPCYC
FO
[Base GVAC (AM~O)
(jJSP
(OISP1)
SCKE
SLO
(SLOB)
J
111111ti±Rift
(WIndow GVAC (AM ~ 1) J
(O~
I I I I I I
(+0 Scroll]
R Refresh Cycle
A Attnbute Cycle
~
I I I
r
I I I
Bn Base Display Cycle
Wn WIndow Display Cycle
D Drawing Cycle
Figure 17. Zoom Display Timing (Dual Access Mode 1, Double Zoom)
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
591
HD63486----------------------------------------------------------------
Absolute Maximum Ratings
(All voltages referenced to Vss
= 0 V)
Item
Symbol
Rating
Unit
Supply voltage
Vee
-0.3 to + 7.0
V
Input voltage
-0.3 to Vee +0.3
V
Output voltage
Vout
5.5
V
o to
Operating temperature
Storage temperature
+70
-55 to +150
Tstr
Notes: Usmg an LSI beyond Its maximum ratmgs may result In Its permanent destruction. LSI's should usually be operated under the recommended
operatmg conditions. Exceedmg any of these conditions may adversely affect Its reliaMy
Recommended Operating Conditions
(All voltages referenced to Vss = 0 V)
Symbol
Min
Typ
Max
Unit
Supply voltage
Vee
4.75
5.00
5.25
V
Input voltage low
VIL
0
0.7
V
Input voltage high
VIH
2.2
Vee
V
Operating temperature
Topr
0
70
'C
Item
25
~HITACHI
592
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD63486
Electrical Characteristics
DC Characteristics (Vee
= 5.0 V
± 5%. Vss
= 0 V. Ta = o'e
to +70'e. unless otherwise noted)
Item
Symbol
Min
Max
Unit
Input voltage high
VIH
2.2
Vee
V
I nput voltage low
Vil
-0.3
0.7
V
Input elamp voltage
VI
-1.5
V
Test Condition
Output voltage high
VOH
Output voltage low
VOL
0.5
V
= 4.75 V. I,n = -18 mA
Vee = 4.75 V. IOH = -400 mA
Vee = 4.75 V. 10l = 8 mA
I nput current high
hH
20
IJA
Vee
I nput current low
hl
-400
IJA
Vee
Output short circuit current
los
-120
mA
Current consumption
lee
160
mA
Input capacitance
Cin
10
pF
DrDo.
10zH
20
IJA
Vec
FD31-FDo
lozl
-20
IJA
Vee
Off·state output current
AC Characteristics (Vee
= 5.0 V
2.7
-40
± 5%. Vss
= 0 V.
Ta
= O'e
Symbol
Min
Max
= 5.25 V. VI = 2.7 V
= 5.25 V. VI = 0.4 V
Vee = 5.25 V
Vee = 5.25 V
= 5.25 V. Vo = 2.7 V
= 5.25 V. Vo = 0.4 V
to +70'e)
48 MHz
32 MHz
No Item
Vee
V
Min
Max
64 MHz
Min
48
Max
Unit
64
MHz
DOTCK operation frequency
f
CD
DOTCK cycle time
te
31.3
20.8
15.6
ns
~
DOTCK high level pulse width
ns
32
tHw
12
9
6
@ DOTCK low level pulse width
tlw
12
9
6
@
DOTCK rise time
tR
5
5
5
ns
@
DOTCK fall time
tF
5
5
5
ns
@ SCKE setup time
Figure
18
ns
tseKs
6
2
0
ns
SCKE hold time
tseKH
5
5
5
ns
@ SLD setup time
tSlDS
6
2
0
ns
®
SLD hold time
tSlDH
3
3
3
@
VIDEO delay time
tVD
3
@ 2CLK setup time
t2CKS
6
2
0
ns
@
tMeyeS
30
30
30
ns
@ MCYC hold time
tMeyeH
0
0
0
ns
@
FD three!state recovery time
tFDR
5
5
5
ns
20
@
FD setup time
tFDS
30
30
30
ns
21
tFDH
5
5
5
ns
(J)
MCYC setup time
@ FD hold time
24
3
17
3
ns
14
ns
19-21
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
593
HD6~86------------------------
____________________________________
AC Characteristics (cont)
48 MHz
32 MHz
No
Item
@
o three state recovery time
o hold time
@
@ FD delay time from 0
@
Min
Unit
Fiaure
tOR
5
5
5
ns
19
tOH
5
5
5
ns
Max
Min
30
30
tFOOLY
o delay time from FD
64 MHz
Symbol
tOOLY
Max
Min
30
30
Max
18
18
ns
ns
@ SEL setup time
tSELS
10
10
10
ns
@ SEL hold time
tSELH
5
5
5
ns
@ DSPCYC setup time
tosps
20
20
20
ns
@ DSPCYC hold time
tOSPH
5
5
5
ns
@ MRD setup
tMROS
tMROH
@ DISP setup time
tOISPS
20
10
20
20
10
20
20
10
20
ns
@ MRD hold time
_L
DOTCK
®
ns
®
L®
~
I
t
\
\
®
SCKE
CD
\I
\II
/\
j\
®
®
\
/
\
/
~
\1
VIDEO
/\
Figure 18. Dot Clock
~HITACHI
594
19-21
ns
CD
®
20
19
19,20
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
21
-----------------------------------------------------------------HD63486
OOTCK
.:;
2ClK
I~
,1{\-I-
@
©
@.J
--==:{
MCYC
\
-I-
FOO-F031
~
~
00-07
®
@
J
I
¥
@
@
I
@
@
~
SElO-SEl2
I
I.
@
-¥-
~
OSPCYC
~
@
-'I.
~
MRO
Figure 19. Read Cycle
OOTCK
2ClK
,W
-:{
-¥-
I@
MCYC
,W
I
@
©
-I
3-
--=--{
\
A
FOOF031
I@
I@
00-07
®
SELOSEl2
OSPCYC
MRO
~
*"
~
@
"'"
@
.J
-I
~
@
-~
¥-
Figure 20. Write Cycle
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
595
HD63486-----------------------------------------------------------------
DOTCK
2ClK
-,
I~
I~
I
+
MCYC
/
@
©
@I
~-
\
-¥-
@
FDOFD31
I
DSPCYC
@I
@
~..,.,
@
~
...~
MRD
~
"*
@
:,;
Figure 21. Display Cycle
(a)
(b)
Totem Pole Output
Three State Output
(0 0 -0 7 , FOo-F0 3 d
(VOUTA-VOUTO)
1
Vee
Vee
~ 6679
RL=2K9
Test Point
Test Point
5K9
CL
=40pF L...-_ _ _,.
note: All diodes are 1S2074@'s or the equivalent.
S,
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
ON
Figure 22. Test Load Circuit
~HITACHI
596
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
------------------------------~--------~--~-------------------HD63486
Input
Input
Output
Output
( Enable
)
Disenable
Figure 23. Input/Output waveforms
•
HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
597
HD63486--------------------------------------------------------------
Package Dimensions
Unit: mm(inches)
DP-64S
576(2268)
58.6ma. (2 301max.)
64
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(OOI9±0004)
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Note)
Inch valve indicated for your reference.
~HITACHI
598
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
--------------------------------------------------------------HD63486
Reference Literature
Product
Data Sheet
User's Manual
H063484 ACRTC
10 #U149
10 #U75
H063485 GMIC
10 #U175
•
Application Note
Others
Introduction to ACRTC
Applications, Circuits
and Software 10 #U90
HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
599
HD68562
DUSCC (Dual
Universal Serial
Communications Controller)
-ADVANCE INFORMATIONThe HD68562 Dual Universal Serial Communications Controller (DUSCC) transforms parallel data which is transferred
from central processing unit into serial data_ It is a single chip
MOS-LSI communications device designed to be a foundation
of universal high-performance data-communication subsystems,
particularly for the 68000 family microprocessors_
The DUSCC provides two independent, multi-protocol, full
duplex receiver/transmitter channels in a single package_ Since
the DUSCC supports a wide range of protocols, it handles data
communications with the minimum intervention, usually just a
few commands from its host processor. The controller's data
rate is maximum 4M bits/s which meets the requirement of the
presently most powerful systems. A high-speed, high-performance communication system is realized with minimum
extemallogic at low cost through a variety of functions prOvided by the chip: 16-bit multi-function counter/timer, a digital
phase locked loop (DPLL), a parity/CRC generator and checker,
and baud rate generator.
The DUSCC is useful for communication between host
computer and terminals, electric mail, VIDEOTEX, local area
network (LAN), communications network among personal computers, etc.
•
(DC-48)
• PIN ARRANGEMENT
lACK'
FEATURES
• Channel data rate: 4M bps maximum
• Receiver/Transmitter: Two channels, dual full-duplex synsynchronous/asynchronous
• MUlti-protocol BOP (Bit Oriented Protocol)
operation: BCP (Byte Controlled Protocol)
COP (Character Oriented Protocol)
ASYNC (Asynchronous)
• High data transfer efficiency: Four-character receiver/transmitter FIFOs
• Parity and FCS (Frame Check Sequence): VRC, LRC-8,
CRC-16, CRC-CCITT
• Programmable data encoding/decoding: NRZ, NRZI, FMO,
FM1, Manchester
• DMA interface: Compatible with Hitachi HD68450/HD63450 DMAC and other DMA controllers
• Multi-function programmable l6-bit CIT: Baud rate generator, etc.
• Clock oscillator: On-chip oscillator for crystal
• Power supply: Single +5V
Al 4
RTXDAKB/GPiIe 5
IRQ 6
RESET
RTSB/SYNOUTB
TRXCB 9
RTXCB ,
DCDB/SYNIB
RXDS
TXDB
TXDAKii/GPI2B
12
,
,
@HITACHI
600
3
RTXCA
11
H,tachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
TXDA
___________________________________________________________ HD68562
• MAJOR FUNCTIONS OF DUSCC
FUNCTION
Item
Maximum operating frequency
4MHz
Maximum data transfer rate
4 Mbits/s
Data length
5·S bits
Bus interface
Compatible with HD68000 (S bits bus)
FIFO
4 bytes for each receiver/transmitter
Number of channels
2 channels
Error check
Parity, framing, over run, under run, FCS
Channel mode
Half·duplex, full·duplex, auto·echo, local loopback
Data tra nsfer mode
Polled, interrupt, DMA, wait
Protocol operation
ASYNC
COP
BCP
BOP
: 5·S bits plus optional parity
: BISYNC, X.21
: DDCMP
: HDLC/ADCCP, SDLC, SDLC Loop, Link Level,
X.75 Link Level
Baud rate generator
Built·in
Selection of baud rate
(1) 16 fixed rates: 50 to 3S.4K baud.
(2) Optional baud rate by timer.
Encoding/Decoding
NRZ, NRZI, FMO, FM1, Manchester
Digital phase locked loop
Built·in
DMA interface
Compatible with HD68450/HD63460
Half or full duplex operation
Single or dual address data transfer
Interrupt capabilities
(1) Daisy chain option
(2) Vector output (fixed or modified by status)
(3) Maskable interrupt conditions
(4) Programmable internal priorities
Model control
RTS, CTS, DCD
Four general purpose I/O pins per channel
16·bit counter ti mer
Built·in
Oscillator
Built·in
Package
Ceramic DIP 4S·pin
Power supply
6V:I: 10%
Power dissipation
Typ.l W
Ta - 0 to 70·C
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-S300
601
HD68562-------------------------------------------------------------•
INTERNAL BLOCK DIAGRAM
TXDA
TXDB
RXDB
RXDA
CONTROL
'"::>
..
Ol
-'
TIMING
z
ffi
....---+----I~
RTXCA
TRXCA
RTXCB
TRXCB
X1/CLK
-I
LK SELECT...._ _ _-+___
AND B R G
A/B
....-----~-I
DMA
CONTROL
x2/Ti5C
RTXDROA/GP01 A
RTXDROB/GP01 B
"f'XilRllA/GP02A/RTS
TXDROB/GP02B/RTSB
RTXDAKA/GPI 1A
RTXDAKB/GPI1 B
TXDAKA/GPm
TXDAKB/Gl'l2l!
DTC
DONE
--Vee
-GND
Figure 1 DUSCC Block Diagram
• SYSTEM CONFIGURATION
MPU
DMAC
HD6BOOO
HD68450
HD63450
SYSTEM BUS
MAIN
MEMORY
······
···
Figure 2 System Configuration Example
~HITACHI
602
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
HD63645F/HD64645F
LCD Timing Controller (LCTC)
Pin Arrangement
Description
The HD63645F /HD64645F LCTC is a control LSI
for large size dot matrix liquid crystal displays.
The LCTC is software compatible with the HD6845
CRTC, since its programming method of internal
registers and memory addresses is based on the
CRTC. A display system can be easily converted
from a CRT to an LCD.
MOO
M01
M02
M03
M04
M05
The LCTC offers a variety of functions and per·
formance features such as vertical and horizontal
scrolling, and various types of character attribute
functions such as reverse video, blinking, nondisplay (white or black), and an OR function for
simple superimposition of character and graphic
displays. The LCTC also provides DRAM refresh
address output.
'
,
,
•
,
•
Moe '
M07
•
MOB'
M09
10
A compact LCD system with a large screen can be
configured by connecting the LCTC with the
HD61104 (column driver) and the HD61105 (common driver) by utilizing 4-bit x 2 data outputs.
Power dissipation has been lowered by adopting the
CMOS process.
.
!!IN
001a: ua:
00
:::>zWIOOOO
U(!)
) is
Features
•
•
•
•
•
•
•
•
•
•
•
•
Software compatible with the HD6845 CRTC
Programmable screen size:
-Up to 1024 dots (height)
-Up to 4096 dots (width)
High-speed data transfer:
-Up to 20 Mbits/sec in character mode
-Up to 40 Mbits/sec in graphic mode
Selectable single or dual screen configuration
Programmable multiplexing duty ratio: static
to 1/512 duty cycle
Programmable character font:
-1-32 dots (height)
-8 dots (width)
Versatile character attributes: reverse video,
blinking, nondisplay (white), nondisplay
(black)
OR function: superimposing characters and
graphics display
Cursor with programmable height, blink rate,
display position, and on/off switch
Vertical smooth scrolling and horizontal scrolling by the character
Versatile display modes programmable by
mode register or external pins: display on/off,
graphic or character, normal or wide, attributes, and blink enable
Refresh address output for dynamic RAM
•
•
•
•
•
•
for
HD64645F
4- or 8-bit parallel data transfer between LCTC
and LCD driver
Recommended LCD driver: HD61104
(column) and HD61105 (common)
CPU interface: 68 family (HD63645F),
80 family (HD64645F)
CMOS process
Single +5 V ±10%
80-pin flat plastic package (FP-80)
Type of Products
Type No.
Bus Timinl
Bus Interface
Packale
HD63645F
2MHz
68 System
so.pin FPP
HD64645F
4 MHz
so System
so.pin FPP
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
603
H D63645F/H D64645F
Pin Description
Symbol
Pin Number
Name
Vecl, Vce2
17, 32
Vee
GNDl, GND2
37,59
Ground
LUO-LU3
22-25
LCD Up Panel Data 0-3
LDO-LD3
18-21
LCD' Down Panel Data 0-3
CLl
28
Clock One
CL2
29
Clock Two
FLM
27
First Line Marker
M
26
M
MAO-MA15
65-80
Memory Address 0-15
RAO-RA4
60-64
Raster Address 0-4
MDO-MD7
1-8
Memory Data 0-7
MD8-MDI5
9-16
Memory Data 8-15
I
DBc-DB7
43-50
Data Bus 0-7
I/O
CS
39
Chip Select
E
41
Enable (HD63645F Only)
R/W
42
Read/Write (HD63645F Only)
WR
41
Write (HD64645F Only)
RD
42
Read (HD64645F Only)
RS
40
Register Select
RES
38
Reset
DCLK
33
D Clock
I
MCLK
34
M Clock
0
0
0
DISPTMG
35
Display Timing
CUDISP
36
Cursor Display
Skew 0
SKO
30
SKI
31
Skew 1
ON/OFF
53
On/Off
BLE
51
Blink Enable
AT
57
Attribute
G/C
58
Graphic/Character
WIDE
54
Wide
LS
56
Large Screen
D/S
55
Dual/Single
MODE
52
Mode
~HITACHI
604
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
I/O
0
0
0
0
0
0
0
0
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD63645F/HD64645F
Pin Functions
Power Supply (Vec1, 2, GND)
enables MPU read/write of the LCTC internal
registers.
Power Supply Pin (+5 V): Connect Veel and
Vee 2 with + 5 V power supply circuit.
Enable (E): E receives an enable clock.
(HD63645F only).
Ground Pin (0 V): Connect GNDl and GND2
with OV.
Read/Write (R/W): R/W enables MPU read of
the LCTC internal registers when R/W is high, and
MPU write when low. (HD63634F only).
LCD Interface
Write (WR): WR receives MPU write signal.
(HD64645F Only)
LCD Up Panel Data (LUO-LU3), LCD Down
Panel Data (LDO-LD3): LUO-LU3 and LDOLD3 output LCD data as shown in table 1.
Read (RD): RD receives MPU read signal.
(HD64645F Only)
Clock One (CLl): CLl supplies timing clocks for
display data latch.
Register Select
(Refer to table 5.)
Clock Two (CL2): CL2 supplies timing clock for
display data shift.
(RS): RS selects registers.
First Line Marker (FLM): FLM supplies first
line marker.
Reset (RES): RES performs external reset of the
LCTC. Low level of RES stops and zero-clears the
LCTC internal counter. No register contents are
affected.
M (M): M converts liquid crystal drive output to
AC.
Timing Signal
Memory Interface
D Clock (DCLK): DCLK inputs the system clock.
Memory Address (MAO-MAl5): MAO-MAI5
supply the display memory address.
M Clock (MCLK): MCLK indicates memory
cycle; DCLK is divided by four.
Raster Address (RAO-RA4): RAO-RA4 supply
the raster address.
Display Timing (DISPTMG): DISPTMG high
indicates that the LCTC is reading display data.
Memory Data (MDO-MD7): MDO-MD7 receive
the character dot data and bit-mapped data.
Cursor Display (CUDISP): CUDISP supplies
cursor display timing; connect with MDl2 in
character mode.
Memory Data (MDS-MDl5): MD8-MDl5
receive attribute code data and bit-mapped data.
Skew 0 (SKO) /Skew 1 (SKl): SKO and SKI
control skew timing. Refer to table 2.
MPU Interface
Mode Select
Data Bus (DBO-DB7): DBO-DB7 send/receive
data as a three-state I/O common bus.
Chip Select (CS): CS selects a chip. Low level
The mode select pinsON/OFF, BLE, AT, G/C, and
WIDE are ORed with the mode register (R22) to
determine the mode.
Table 1. LCD Up Panel Data and LCD Down Panel Data
SinKle Screen
Pin name
4-Bit Data
8-Blt Data
Dual Screen
LUO-LU3
LDO-LD3
Data output
Disconnected
Data output
Data output
Data output for upper screen
Data output for lower screen
•
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
605
HD63645F/HD64645F-----------------------------------------------------------
On/Off (ON/OFF): ON/OFF switches display
on and off. (High == display on).
and wide display mode (high == wide display, low
== normal display).
Blink Enable (BLE): BLE high level enables
attribute code "blinking" (MD13) and provides
normal/blank blinking of specified characters for
32 frames each.
Large Screen (LS): LS controls a large screen.
LS high provides a data transfer rate of 40 Mbits/s
for a graphic display. Also used to specify 8-bit LCD
interface mode. For more details, refer to page 26.
functions.
Dual/Single (D/S): D/S switches between single
and dual screen display (dual screen display when
high).
Graphic/Character (G/C): G/C switches
between graphic and character display mode
(graphic display when high).
Mode (MODE): MODE controls easy mode.
Wide (WIDE): WIDE switches between normal
9.)
Attribute (AT): AT controls character attribute
MODE high sets duty ratio, maximum number of
rasters, cursor start/end rasters, etc. (Refer to table
Table 2. Skew Signals
SKO
SKI
Skew Function
o
o
o
No skew
I-character time skew
2-character time skew
Inhibited combination
o
@HITACHI
606
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD63645F/HD64645F
Function Overview
LCD and CRT Display Systems
Main Features of HD63645F/HD64645F
Figure 1 shows a system using both LCD and CRT
displays.
Main features of the LCTC are:
High-resolution liquid crystal display screen
control (up to 720 X 512 dots)
Software compatible with HD6845 (CRTC)
Built-in character attribute control circuit
Table 3 shows how the LeTC can be used.
Table 3. Functions, Application, and Configuration
Classification
Item
Description
Functions
Screen Format
Programmable horizontal scanning cycle by the character clock period
Programmable multiplexing duty ratio from static up to 1/512
Programmable number of displayed characters per character row
Programmable number of rasters per character row (number of vertical
dots within a character row + space between character rows)
Cursor Control
Programmable cursor display position, corresponding to RAM address
Programmable cursor height by setting display start/end rasters
Programmable blink rate, 1/32 or 1/64 frame rate
Memory
Rewriting
Time for rewriting memory set either by speCifying number of horizontal
total characters or by cycle steal utilizing MCLK
Memory
Addressing
16-bit memory address output, up to 64 kbytes x 2 memory accessible
DRAM refresh address output
Paging and
Scrolling
Paging by updating start address
Horizontal scrolling by the character, by setting hOrizontal virtual screen
width
Vertical smooth scrolling by updating display start raster
Application
Configuration
Character Attributes
Reverse video, blinking, nondisplay (white or black) character attributes
CRTC Compatible
Facilitates system replacement of CRT display with LCD.
OR Function
Enables superimposing display of character screen and graphic screen
LCTC
Configuration
Single 5 V power supply
I/O TTL compatible except RES, MODE, SKO, SKI
Bus connectable with HMCS 6800 family (HD63645F)
Bus connectable with 80 family (HD64645F)
CMOS process
Internal logic fully static
80-pin flat plastic package
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
607
HD63645F/HD64645F - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Liquid crystal
display
CRT
(monochrome)
LCD display signals
Video signals
MPU
6301
Figure 1. LCD and CRT Displays
$
608
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - HD63645F/HD64645F
Internal Block Diagram
Figure 2 is a block diagram of the LCTC.
(WR) (AD)
E RiW
Cl2
M
MAO-MA15~===Tr=====~~~~~~~
G/C
AT
LS
Dis
WIDE
ONIOFF
MODE
RAO-RA4~==~~======~================~
LE
_1MOO-M015
CUDISP
SKO SK 1
( ) IS for HD64645F (80 types bus Interface)
Figure 2. LCTC Block Diagram
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
609
HD63645F/HD64645F - - - - - - - - - - - - - - - - - - - - - - - - - - - -
System Block Configuration Examples
Figure 3 is a block diagram of a character/graphic
display system. Figure 4 shows two exa!llples using
LCD drivers.
HD63645F/HD64645F
MPU Bus
(WR) (RD)
E,R/W
DBO-DB7
G/C
AT
LS
MAO-MA15
D/S
WIDE
MODE
ON/OFF
MCLK
BLE
DISPTMG
CS,RS
2345678
122334455667788
WIDE='High'
WIDE='Low'
Figure 13. Example of Wide Display
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
621
HD63645F/HD64645F----------------------------
The attribute functions are offered only in character mode, and controlled either by bit 0 of the mode
register (R22) or the AT pin_ As shown in figure 15,
a character attribute can be specified by placing the
character code on MDO-MD7, and the attribute
code on MDll-MOl5_ MDB-MOlD are invalid_
Attribute Functions
A variety of character attribute functions such as
reverse video, blinking, nondisplay (white) or
nondisplay (black) can be implemented by storing
the attribute data in A-RAM (attribute RAM)_
Figure 14 shows a display example using each
attribute function_
1_ Black
2. White
D
3. Blinking
[8J~D~[8J
4. Cursor
5. Reverse Video
Ii]
Figure 14. Display Example Using Attribute Functions
MD Input
15
14
13
12
11
10-8
7-0
Function
Nondisplay
(black)
Nondisplay
(white)
Blinking
Cursor
Reverse
video
***
Character Code
"': Invalid
Figure 15. Attribute Code
~HITACHI
622
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD63645F/HD64645F
OR Function -Superimposing Characters and
Graphics
data) in the LCTC and transfers this data as 1 byte.
The OR function (figure 16) generates the OR of
the data entered into MDO-MD7 (e.g. character
data) and the data into MD8-MDl5 (e.g. graphic
This function is offered only in character mode, and
controlled by bit 0 of the mode register (R22) or by
the AT pin. Any attribute functions ar,e disabled
when using the OR function.
Graphic data
(Character data)
I MD15 MD14 - - - -
Character data
(Graphic data)
MD9
MDf;
'MD7
MD6 - - - -
MDl
,. ------ ------ ---1- -- --- ------ --
-L ---
MDO
I
-0 - - - - -
a-bit
data
-
6
7
L _______________________________________ - - - _ - - - - -
_I
Figure 16. OR Function
@HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
623
HD63645F/HD64645F----------------------------
DRAM Refresh Address Output Function
The LCTC outputs the address for DRAM refresh
while CLl is high, as shown in figure 17. The 16
refresh addresses per scanned line are output 16
times, from $OO-$FF.
Skew Function
The LCTC can specify the skew (delay) for
CUDISP, DISPTMG, CL2 outputs and MD inputs.
If buffer memory and character generator ROM
display period, the access is retarded to the next
cycle by inserting a latch to memory address output
and buffer memory output. The skew function
retards the CUDISP, DISPTMG, CL2 outputs, and
MD inputs in the LCTC to match phase with the
display data signal.
By utilizing this function, a low· speed memory can
be used as a buffer RAM or a character generator
ROM.
This function is controlled by pins SKO and SKI as
shown in table 7.
cannot be accessed within one horizontal character
Table 7. Skew Function
SKO
SKl
Skew
o
o
o
No skew
1 character time skew
2 character time skew
Inhibited combination
1
o
Function
DISPTMG
L
Cll
MCLK
MAO-7
Display
Memory
Address
•
I
DRAM Refresh
of
Address
Figure 17. DRAM Refresh Address Output
•
624
I
••
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
Display
Memory
Address
-----------------------------------------------------------HD63645~HD64645F
Easy Mode
This mode utilizes software for systems using the
CRTC (HD6845). By setting MODE pin to high, the
display mode and screen format are fixed as shown
in table 8. With this mode, software for a CRT
screen can be utilized in a system using the LCTC,
without changing the BIOS.
Table 8. Fixed Values in Easy Mode
Reg. No.
Register Name
Fixed Value (decimal)
R9
RIO
Maximum raster address
Cursor start raster
Cursor end raster
Horizontal virtual screen width
Multiplexing duty ratio (H)
Multiplexing duty ratio (L)
Display start raster
Mode register
7
6
7
Rll
R18
RI9
R20
R21
R22
Same value as (R 1)
99 (In dual screen mode)
199 (in single screen mode)
o
o
~HITACHI
Hitachi Amenca Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
625
HD63645F/HD64645F----------------------------
System Configuration and Mode Setting
LCD System Configuration
Hardware Configuration and Mode Setting
The screen configuration, single or dual, must be
specified when using the LCD system (figure 18).
The LCTC supports the following hardware con·
figurations:
Using the single screen configuration, you can con·
struct an LCD system with lower cost than a dual
screen system, since the required number of column
drivers is smaller and the manufacturing process for
mounting them is simpler. However, there are some
limitations, such as duty ratio, breakdown voltage
of a driver, and display quality of the liquid crystal,
in single screen configuration. Thus, a dual screen
configuration may be more suitable to an applica·
tion.
The LCTC also offers an 8·bit LCD data transfer
function to support an LCD screen with a smaller
interval of signal input terminals. For a general size
LCD screen, such as 640 x 200 single, or 640 x 400
dual, the usual 4·bit LCD data transfer is satisfac·
tory.
Single or dual screen configuration
4·or 8·bit LCD data transfer
and the following screen format:
Character, graphic I, or graphic 2 display
Normal or wide display (only in character
mode)
OR or attribute display (only in character
mode)
Also, the LCTC supports up to 40 Mbits/s of large
screeen mode (mode 13) for large screen display.
This mode is provided only in graphic 1 mode.
Table 9 shows the mode selection method according
to hardware configuration and screen format. Ta·
ble 10 shows how they are specified.
4
Data
---..,,---~
Column Driver (Upper panel)
.~
LCD Upper Panel
oc:
o
Dma --~~-.1:
(a)
E
____~C~o~lu~m~n~D~riv~e~r____~
§
LCD Lower Panel
u
Single screen
4
Data ---,"--+1 Column Driver (Lower panel)
(b)
Dual screen
Figure 18. Hardware Configuration According
to Screen Format
~HITACHI
626
Hitachi America Ltd .• 2210 O'Toole Avenue· San Jose, CA 95131 • (408) 435-8300
H D63645F/H D64645F
Table 9.
Mode Selection
Hardware Configuration
Screen Format
LCD Data
Transfer
Screen
Configuration
Screen
Size
Character/
Graphic
Normal/
Wide
4·bit
Single
Normal
Character
Normal
Attribute/
OR
AT
Maximum
data transfer
speed (MBPS)
Mode No.
20
5
10
6
OR
Wide
AT
OR
Dual
Normal
Graphic 1
20
7
Graphic 2
20
8
Character
Normal
AT
20
OR
Wide
AT
10
2
Graphic 1
20
3
Graphic 2
20
4
Large
Graphic 1
40
13
Normal
Character
20
9
10
10
Graphic 1
20
11
Graphic 2
20
12
OR
8·blt
Single
Normal
AT
OR
Wide
AT
OR
Note: Maximum data transfer speed Indicates amount of the data read out of a memory Thus, the data transfer speed sent to the LCD driver In
wide function IS 20 Mbps.
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
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HD63645F/HD64645F
Mode List
Table 10. Mode List
Pin Name
No. Mode Name
Dual-screen
character
2
Dual-screen
wide character
3
Dual-screen graphic
1
4
Dual-screen graphic
2
5
Single-screen
character
DIS GIC LS
0 0
0 0
0 0
0 0
0
0
0
0
0
0
6
Single-screen
wide character
7
Single-screen
graphic 1
S
Single-screen
graphic 2
0
9
S-bit character
0
0
0
0
0
0
10
8-bit wide
character
11
12
13
S-bit graphic 1
8-bit graphic 2
Large screen
0
0
0
0
0
0
0
0
WIDE AT
0
0
0
1
Wide
Screen
Graphicl
Data
Confg.
Character
Transfer
Display
Attribute
Dual
screen
Character
4-bit
x2
Normal
OR
Wide
OR
0
AT
AT
0
Graphic
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Single
screen
Character
4-bit
Normal
OR
Wide
OR
AT
0
AT
Graphic
0
Character
S-bit
Normal
OR
Wide
OR
AT
1
0
AT
1
0
0
0
1
Graphic
0
Dual
screen
4-bit
X2
The LCTC display mode is determined by pins DrS (pin 55), G!C (pin 58), LS (pin 56), WIDE (pin 54), and AT (pin 57). As for G/C, WIDE, and
AT, the DR is taken between data bits 0, 2, and 3 of the mode register (R22). The display mode can be controlled by either one of the external
pins or the data bits of R22.
Note:
The above 5 pins heve 32 status combinations (high and low). Any combinations other than the above are inhibited, because they may
cause melfunctions. If you set an inhibited combination, set the right combination again.
~HITACHI
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Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - HD63645F/HD64645F
Internal Registers
The HD63645F /HD64645F has one address register
and fourteen data registers~ In order to select one
out of fourteen data registers, the address of the
data register to be selected must be written into the
address register. The MPU can transfer data to/
from the data register corresponding to the written
address.
To be software compatible with the CRTC
(HD6845), registers R2-R8, R16, and R17, which are
not necessary for an LCD are defined as invalid for
the LCTC.
Address Register (AR)
AR register (figure 19) specifies one out of 14 data
registers. Address data is written into the address
register when RS is low. If no register correspond·
ing to a specified address exists, the address data is
invalid.
Horizontal Total Characters Register (RO)
RO register (figure 20) specifies a horizontal scan·
ning period. The total number of horizontal char·
acters less 1 must be programmed into this 8·bit
register in character units. The "Nht" indicates the
horizontal scanning period including the period
when the CPU occupies memory (total number of
horizontal characters minus the number of hori·
zontal displayed characters). Its unit is, then,
converted from time into the number of characters.
This value is to be specified according to the speci·
fication of the LCD system to be used.
Horizontal Displayed Characters Register (RI)
Rl register (figure 21) specifies the number of
characters displayed per row. The horizontal char·
Data Bit
acter pitches are 8 bits for normal character display
and 16 dots for wide character display and graphic
display.
The "Nhd" must be less than the total number of
horizontal characters.
Maximum Raster Address Register (R9)
R9 register (figure 22) specifies the number of ras·
ters per row in characters mode, consisting of 5 bits.
The programmable range is 0 (1 raster/row) to 31
(32 rasters/row).
Cursor Start Raster Register (RIO)
RIO register (figure 23) specifies the cursor start
raster address and its blink mode. Refer to table 11.
32- or 64-frame
Cursor End Raster Register (RIl)
Rll register (figure 24) specifies the cursor end
raster address.
Start Address Register (H/L) (RI2/RI3)
R12/R13 register (figure 25) specifies a buffer
memory read start address. Updating this register
facilitates paging and scrolling. R14/R15 register
can be read and written to/from the MPU.
Progra m Unit R/W
716151413121110
- 1- 1- 1 Register address
Data Bit
716151 4 131 21110
-
W
Nhd (Displayed characters)
Figure 19. Address Register
Data Bit
Character
W
Figure 21. Horizontal Displayed
Characters Register
Program Unit R/W
Data Bit
Program Unit R/W
7161514131211 10
716151413121110
Nht (Total characters - 1)
Program Unit R/W
Character
W
Figure 20. Horizontal Total
Characters Register
-l-'j-I
Raster
W
Figure 22. Maximum Raster Address
Register
~HITACHI
Hitachi America Ltd . •
Nr
2210 O'Toole Avenue
• San Jose, CA
95131 • (408) 435·8300
629
HD63645F/HD64645F - - - - - - - - - - - - - - - - - - - - - - - - - - -
Cursor Address Register (H/L) (R14/R15)
R14/R15 register (figure 26) specifies a cursor dis·
play address. Cusor display requires setting RIO and
Rll, and CUDlSP should be connected with MD12
(in character mode). This register can be read from
and written to the MPU.
Multiplexing Duty Ratio Register (H/L) (R19/
R20)
R19/R20 register (figure 28) specifies the number
of vertical dots of the display screen. The pro·
grammed value differs according to the LCD screen
configura tion.
Horizontal Virtual Screen Width Register (RI8)
RI8 register (figure 27) specifies the memory width
to determine the start address of the next row. By
using this register, memory width can be specified
larger than the number of horizontal displayed
characters. Updating the display start address
facilitates scrol1ing in any direction within a memo
ory space.
In single screen configuration:
(Programmed value) = Number of vertical dots
-1.
The start address of the next row is that of the
previous row plus Nir. If a larger memory width
than display width is unnecessary, Nir should be set
equal to the number of horizontal displayed char·
acters.
Display Start Raster Register (R21)
R2I register (figure 29) specifies the start raster of
the character row displayed on the top of the
screen. The programmed value should be equal or
less than the maximum raster address. Updating
In dual screen configuration:
(Programmed value) = Number of vertical dots
2
-1.
Table 11 Cursor Blink Mode
Data Bit
B
P
Cursor blink mode
o
o
0
1
Cursor on; without blinking
Cursor off
Blinking once every 32 frames
Blinking once every 64 frames
o
1
Program Unit R/W
7161s141312111°
Memory address (H) (R14)
Memory
Memory address (L) (R1S)
address
R/W
Figure 26. Cursor Address Register
Data Bit
Program Unit R/W
-[ B
I P I Ncs (Raster address)
Program Unit R/W
Data Bit
71 6 1 sI 4 1 3 1 2 J1jo
Raster
W
716151413121110
Nir (No. of chars. of virtual width)
Character
W
Figure 23. Cursor Start Raster Register
Figure 27. Horizontal Virtual Screen
Width Register
Data Bit
Program Unit R/W
716151413121110
- I- I -
I Nce (Raster address)
Raster
Data Bit
W
Program Unit R/W
716151413121110
Figure 24. Cursor End Raster Register
-1-\-\-\-\-\IA1Q,\Ndh'
Raster
W
Ndl (Number of rasters - I) (R20)
*: Number of rasters
Data Bit
Program Unit R/W
7161 S 1413121 1 10
Figure 28. Multiplexing Duty Ratio Register
Memory address (H) (R12)
Memory
Memory address (L) (R13)
address
R/W
Figure 25. Start Address Register
~HITACHI
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD63645F/HD64645F
this register allows smooth scrolling in character
mode.
The OR of the data bits of R22 (figure 30) register
and the external terminals of the same name
determines a particular mode. (figure 31)
Mode register (R22)
Program Unit R/W
Data Bit
~I~I~I
Raster address
7
Raster
I6 I5 I
ION/OFF IG/CIWIDEI BlE IAT
41 3 1 2 1 1 1 0
~ I~ I~
W
Figure 29. Display Start Raster Register
-
W
Figure 30. Mode Register
6 6 B
~
AT
Program Unit R/W
Data Bit
716151413121110
(data bit 0)
BlE
(data bit 1)
WIDE
(data bit 2)
G/C
(data bit 3)
ON/OFF
(data bit 4)
~
Mode Register
(R22)
Notes: 1.
ON/OFF
G/C
(Pin 53)
(Pin 58)
WIDE
(Pin 54)
BlE
(Pin 51)
G/G
AT (valid only when
IS low (character mode))
AT = High: Attribute functions enabled, OR function disabled
AT = low: OR function enabled, attribute functions disabled.
G/G
2.
BlE (valid only when
IS low (character mode))
BlE = High: Blinking enable on the character specified by attribute RAM
BlE = low: No blinking
3.
WIDE (valid only when
IS low (character mode))
WIDE = High: Wide display enabled
WIDE = low: Normal display
4.
G/G
G/G
G/C = High: Graphic 1 display (when AT
G/C = low: Character display
5
AT
(Pin 57)
=
low) or Graphic 2 display (when AT
=
High)
ON/OFF
ON/OFF = High: Display on state
ON/OFF = low: Display off state
Figure 31. Correspondence between Mode Register and External Pins
~HITACHI
Hitachi America Ltd
• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
631
HD636458HD64645F-----------------------------------------------------------
Reset
RES pin determines the internal state of LSI
counters and the like. This pin does not affect
register contents nor does it basically control output terminals.
"Reset" is defined as follows (Figure 32) :
o
o
o
At reset: the time when RES goes low
During reset: the period while RES remains
low
After reset: the period on and after the RES
transition from low to high
RES pin should be pulled high by users during
operation.
level according to the timing when the reset
signal is input:
DISPTMG, CUDISP, MAO-MA15
(4) Fixed at high or low according to mode:
CL2
(5) Unaffected:
DBo-DB7
Reset State of Registers
RES pin does not affect register contents. There·
fore, registers can be read or written even during a
reset state; their contents will be preserved
regardless of reset until they are rewritten to.
Notes for HD63645F/HD64645F
Reset State of Pins
RES pin does not basically control output pins, and
operates regardless of other input pins.
Preserves states before reset:
LUO-LU3, LDO-LD3, FLM, CLl, RAO-RA4
(2) Fixed at high level:
MLCK
(3) Preserves states before reset or fixed at low
(1)
(1) The HD63645F /HD64645F are CMOS LSIs,
and it should be noted that input pins must not
be left disconnected, etc.
(2) At power-on, the state of internal registers
becomes undefined. The LSI operation is undefined until all internal registers have been
programmed.
V
RES - - - - - " " ' \
During reset
After reset
At reset
Figure 32. Reset Definition
~HITACHI
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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - HD63645F/HD64645F
Absolute Maximum Ratings
Item
Supply voltage
Symbol
Value
2
2
Note
Vee
-0.3 to + 7.0 V
Terminal voltage
Y,n
-0.3 to Vee +0.3 V
Operating temperature
Topr
-20'C to + 75'C
Storage temperature
Tstg
-55'C to +125'C
Notes: 1
2
Permanent LSI damage may occur If maximum ratmgs are exceeded Normal operation should be under recommended operating
conditions (Vee = 5.0 V ± 1 0%, GNO = 0 V, Ta = - 20'e to + 75'e) If these conditIOns are exceeded, It could affect reliability of
LSI.
Width respect to GROUNO (GNO = 0 V)
Electrical Characteristics
DC characteristics (Vee = 5.0V ±1O%. GND = OV. Ta = -20'C to +75'C. unless otherwise
noted.)
Item
Input high voltage
RES, MODE, SKO, SKI
Symbol
Min
V,H
Vee-0.5
Vee+0.3
V
2.2
Vee+0.3
V
DCLK, ON/OFF
All others
Typ
Max
Unit
2.0
Vee+0.3
V
Input low voltage
All others
V,L
-0.3
0.8
V
Output high voltage
TTL I nterfaee'
VOH
2.4
CMOS Interfacel
Output low voltage
TTL Interface
Input leakage current
All Inputs except
DBa-DB?
Three state (off-state)
leakage current
DBa-DB7
Current dissipation'
Notes: 1
3.
V
V
Vee-0.8
VOL
CMOS Interface
0.4
V
0.8
V
IlL
-2.5
+2.5
"A
IrSL
-10
+10
"A
10
mA
Ice
Test
Condition
TTL Interface; MAO-MA15, RAO-RA4, DlSPTMG, CUOISP, OBO-OB7, MCLK
C·MOS Interface, LUO-LU3, LOO-L03, Cll, CL2, M, FLM
Input/output current IS excluded. When Input IS at the intermediate level with CMOS, excessive current flows through the Input CirCUit
to power supply. Input level must be fixed at high or low to avoid thiS condition.
If the capacity loads of LUO-LU3 and LOO-L03 exceed the rating, nOise over 08 V may be produced on CUDISP, OISPTMG, MCLK,
FLM and M In case the loads of LUO-LU3 and LOO-L03 are larger than the ratings, supply Signals to the LCO module through buffers
~HITACHI
Hitachi Amenca Ltd • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
633
HD63645F/HD64645F
AC Characteristics
CPU Interface (HD63645F -
68 family)
Typ
Item
Symbol
Min
Unit
Figure
Enable cycle time
tCYCE
500
ns
33
Enable pulse width (high)
PWEH
220
ns
Enable pulse width (low)
PWEL
220
Max
ns
tEr
25
ns
tEl
25
ns
Enable rise time
Enable fall time
es,
es,
RS, RjW setup time
tAS
70
ns
RS, RjW hold time
tAH
10
ns
DBo-DB? setup time
tDS
60
ns
DBa-DB? hold time
tDHW
10
DBa-DB? output delay time
tDDR
DBa-DB? output hold time
tDHR
ns
150
20
ns
ns
\4-------tcVCE ------~
2.0Vl.foo_ __
E
O.8V
CS
RS
R/W
DBa-DB7
(input)
DB a-DB 7
(output)
Figure 33. CPU Interface (HD63645F)
~HITACHI
634
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
HD63645F/HD64645F
CPU Interface (HD64645F -
80 family)
Item
Symbol
Min
RD high level width
tWROH
RD low level width
tWROL
WR high level width
tWWOH
190
190
190
190
0
0
60
0
WR low level width
tWWOL
Cs, RS setup time
tAS
CS,
tAH
RS hold time
DBo-DB7 setup time
tosw
DBo-DB7 hold time
tOHW
DBo-DB7 output delay time
tOOR
DBo-DB7 output hold time
tOHR
,
o.svj r-
-'
'-
~
~
~
tAs
twAOL
O.SV
ns
ns
ns
ns
:~
!-to
tAs
tAH
-'
twAOH
i\
~
~
tWWOL
"
2.0V~
~r
DBo-D B7
ns
ns
twwOH
J
34
ns
...
2.0V-'
Filure
ns
ns
J
1\
Unit
ns
150
II
RS
Max
20
2.0V~ r
CS
Typ
-
i\
tDOA
tOHA
,
tosw
.I-~
I
2.4V,fOAV
-
O.SV
output
i\.
t-
J'-
~
O.S V
If
,
~ tOHW
input
i\.
J
Figure 34. CPU Interface (HD64645F)
•
HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
635
HD63645F/HD64645F
AC Characteristics (Cont)
Memory Interface
Item
Symbol
Min
Unit
Figure
DClK cycle time
tCYCO
100
ns
35
DClK high level width
tWOH
30
ns
DClK low level width
twOL
30
ns
DClK rise time
to,
20
ns
DClK fall time
to!
20
ns
MClK delay time
tOMO
70
ns
MClK rise time
tM,
30
ns
MClK fall time
tM!
30
ns
MAO-MA15 delay time
tMAO
150
ns
MAO-MA15 hold time
tMAH
RAO-RA4 delay time
tRAO
RAO-RA4 hold time
tRAH
DISPTMG delay time
tOTO
Typ
Max
10
ns
150
10
ns
150
DISPTMG hold time
tOTH
CUDISP delay time
tcoo
CUDISP hold time
tCOH
CLl delay time
tCLIO
Cl1 hold time
tCLlH
CLl rise time
ns
10
ns
ns
150
10
ns
ns
150
10
ns
ns
tCLl,
50
ns
CLl fall time
tCLlf
50
ns
MDO-MD15 setup time
tMOS
80
ns
MDO-MD15 hold time
tMOH
15
ns
•
636
HITACHI
Hitachi Amenca Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
- - - - - - - - - - - - - - - - - - - - - - - - - - - HD63645F/HD64645F
teyeD
DClK
MClK
Cl1
MDO-MD15
(input)
Figure 35. Memory Interface
~HITACHI
Hitachi America ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
637
HD63645F/HD64645F
AC Characteristics (Cont)
LCD Interface
Item
Symbol
Min
Unit
Figure
Display data setup time
tLDS
50
Typ
Max
ns
36
Display data hold time
tLDH
100
ns
CL2 high level width
tWCL2H
100
ns
CL2 low level width
tWCL2L
100
ns
FLM setup time
tFS
500
ns
FLM hold time
tFH
300
ns
CLl rise time
tCLlr
50
ns
CLl fall time
tCLl!
50
ns
CL2 rise time
tCL2r
50
ns
CL2 fall time
tCL2!
50
ns
Note: At fCL2 = 3 MHz
;
1/
LUO-LU3
LDO-LD3
I4--tos---l
CL2
(
Vee- O.BV
O.BV
I
tOH
Vee- O.BV
~
O.BV
tweL2H
tweL2L
teL2!
tCL2r
1/
\
CL1
Vee- O.BV
O.BV
tcur
tell!
.,
FLM
tFH
tFS
-I.-
f
Vee- O.BV
O.BV
\
~
Figure 36. LCD Interface
~HITACHI
638
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (40B) 435·B300
- - - - - - - - - - - - - - - - - - - - - - - - - - - - HD63645F/HD64645F
AC Characteristics
TTL Load
Terminal
RL
R
C
Remarks
DBc-DB7
2.4 kCl
MAO-MAI5, RAO-RA4, DISPTMG, CUDISP
2.4 kCl
11 kCl
130 pF
tr, tf: Not specified
llkCl
40 pF
MCLK
2.4 kCl
11 kCl
30 pF
-------------------------~--
tr, tf: Specified
All diodes; 1S20742
R/W
8085
Bus
Internal
Signals
6801
Bus
OS
Read Eneble
R/W
Write Enable
Figure 13 Functional Diagram of the Bus Control Circuit
•
ADDRESS MAP
Figure 14 shows the address map of the HD146818. The
memory consists of 50 general purpose RAM bytes, 10 RAM
bytes which normally contain the time, calendar, and alarm
data, and four control and status bytes. All 64 bytes are
directly readable and writable by the processor program except Registers C and D which are read only. Bit 7 of Register
A and the seconds byte are also read only. Bit 7, of the second
byte, always reads "0". The contents of the four control and
status registers are described in the Register section.
• Time, Calendar, and Alarm Locations
The processor program obtains time and calendar information by reading the appropriate locations. The program
o
14
00
may initialize the time, calendar, and alarm by writing to
these RAM locations. The contents of the 10 time, calendar,
and alarm byte may be either binary or binary-coded decimal
(BCD).
Before initializing the internal registers, the SET bit in
Register B should be set to a "I" to prevent time/calendar
updates from occurring. The program initializes the I 0 locations in the selected format (binary or BCD), then indicates
the format in the data mode (DM) bit of Register B. All 10
time, calendar, and alarm bytes must us.~ the same data mode,
either binary or BCD. The SET bit may now be cleared to
allow updates. Once initialized the real-time clock makes
all updates in the selected data mode. The data mode cannot
be changed without reinitializing the 10 data bytes.
o
Bytes
13
00
14+--------+
50
Bytes
User
RAM
1
63
-'----------'-
Seconds
00
Sec Alarm
0
Minutes
02
Min Alarm
03
Hours
04
Hr Alarm
05
Day of Wk
06
Date of Mo
07
Month
08
Year
09
Register A
0A
Register B
0B
Register C
0C
Register 0
0o
Binary
or BCD
Contents
Figure 14 Address Map
@HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
653
HD146818---------------------------------------------------------------Table 2 shows the binary and BCD formats of the 10 time,
calendar, and alarm locations. The 24/12 bit in Register B
establishes whether the hour locations represent l-to-12 or
0-to-23. The 24/12 bit cannot be changed without reinitializing
the hour locations. When the 12-hour format is selected the
high-order bit of the hours byte represents PM when it is a "I".
The time, calendar, and alarm bytes are not always accessable by the processor program. Once-per-second the 10
bytes are switched to the update logic to be advanced by one
second and to check for an alarm condition. If any of the 10
bytes are read at this time, the data outputs are undefined.
The update lockout time is 248 JJ.S at the 4.194304 MHz and
1.048567 MHz time bases and 1948 JJ.S for the 32.768 kHz time
base. The Update Cycle section shows how to accommodate
the update cycle in the processor program.
The three alarm bytes may be used in two ways. When
the program inserts an alarm time in the appropriate hours,
minutes, and seconds alarm locations, the alarm interrupt is
initiated at the specified time each day if the alarm enable bit
is "I". The alternate usage is to insert a "don't care" state in
one or more of three alarm bytes. The "don't care" code is
any hexadecimal byte from CO to FF. That is, the two mostsignificant bits of each byte, when set to "I", create a "don't
care" situation. An alarm interrupt each hour is created with
a "don't care" code in the hours alarm location. Similarly, an
alarm is generated every minute with "don't care" codes in
the hours and minutes alarm bytes. The "don't care" codes
in all three alaro bytes create an interrupt every second.
Table 2 Time, Calendar, and Alarm Data Modes
Address
Location
Range
Example*
Function
Decimal
Range
Binary Data Mode
BCD Data Mode
Binary
Data Mode
0
Seconds
0-59
$00-$3B
$00-$59
15
21
1
Seconds Alarm
0-59
$00-$3B
$00-$59
15
21
2
Minutes
0-59
$00-$3B
$00-$59
3A
58
3
Minutes Alarm
0-59
$00-$3B
3A
58
Hours
(12 Hour Mode)
1-12
$01-$OC (AM) and
$81 -$8C (PM)
$00-$59
$01-$12 (AM) and
$81 -$92 (PM)
05
05
Hours
(24 Hour Mode)
0-23
$00-$17
$00-$23
05
05
Hours Alarm
(12 Hour Mode)
1-12
$01 -$OC (AM) and
$81 -$8C (PM)
$01 -$12 (AM) and
$81 -$92 (PM)
05
05
Hours Alarm
(24 Hour Mode)
0-23
$00-$17
$00-$23
05
05
05
4
5
BCD
Data Mode
6
Day of the Week
Sunday = 1
1-7
$01 -$07
$01 -$07
05
7
Day of the Month
1 -31
$01-$1F
$01-$31
OF
15
8
Month
1-12
$Ol-$OC
$01 -$12
02
02
9
Year
0-99**
$00-$63
$00-$99
4F
79
* Example: 5:58:21 Thursday 15th February 1979
** Set the lower two digits of year
•
In
AD. If this number is multiple of 4, update applied to leap year is excuted.
Static CMOS RAM
•
The 50 general purpose RAM bytes are not dedicated within
the HD 146818. They can be used by the processor program,
and are fully available during the update cycle.
When time and calendar information must use battery
back-up, very frequently there is other non-volatile data that
must be retained when main power is removed. The 50 user
RAM bytes serve the need for low-power CMOS batterybacked storage, and extend the RAM available to the program.
When further CMOS RAM is needed, additional HDI46818s
may be included in the system. The time/calendar functions
may be disabled by holding the dividers, in Register A, in the
reset state by setting the SET bit in Register B or by removing
the oscillator. Holding the dividers in reset prevents interrupts
or SQW output from operating while setting the SET bit allows
these functions to occur. With the dividers clear, the available
user RAM is extended to 59 bytes. Bit 7 of Register A, Registers
C and D, and the high-order Bit of the seconds byte cannot
effectively be used as general purpose RAM.
INTERRUPTS
The RTC plus RAM includes three separate fully automatic
sources of interrupts to the processor. The alarm interrupt
may be programmed to occur at rates from once-per-second
to one-a-day. The periodic interrupt may be selected for rates
from half-a-second to 30.517 JJ.s. The update~nded interrupt
may be used to indicate to the program that an up-date cycle
is completed. Each of these independent interrupt conditions
are described in greater detail in other sections.
The processor program selects which interrupts, if any, it
wishes to receive. Three bits in Register B enable the three
interrupts. Writing a "I" to a interrupt~nable bit permits
that interrupt to be initiated when the event occurs. A "0" in
the I interrupt~nable bit prohibits the IRQ pin from being
asserted due to the interrupt cause.
If an interrupt flag is already set when the interrupt becomes
enabled, the IRQ pin is immediately activated, though the
interrupt initiating the event may have occurred much earlier.
Thus, there are cases where the program should clear such
~HITACHI
654
Hitachi Amenca Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435·8300
-------------------------------------------------------------HD146818
earlier initiated interrupts before fust enabling new interrupts.
When an interrupt event occurs a flag bit is set to a "I" in
Register C. Each of the three interrupt sources have separate
flag bits in Register C, which are set independent of the state
of the corresponding enable bits in Register B. The flag bit
may be used with or without enabling the corresponding enable
bits.
In the software scanned case, the program does not enable
the interrupt. The "interrupt" flag bit becomes a status bit,
which the software interrogates, when it wishes. When the
software detects that the flag is set, it is an indication to software that the "interrupt" event occurred since the bit was
last read.
However, there is one precaution. The flag bits in Register
C are cleared (record of the interrupt event is erased) when
Register C is read. Double latching is included with Register
C so the bits which are set are stable throughout the read
cycle. All bits which are high when read by the program are
cleared, and new interrupts (on any bits) are held until after
the read cycle. One, two, or three flag bits may be found to
be set when Register C is read. The program should inspect
all utilized flag bits every time Register C is read to insure that
no interrupts are lost.
The second flag bit usage method is with fully enabled
interrupts. When an interrupt-flag bit is set and the corresponding inter~-enable bit is also set, the IRQ pin is asserted
"Low". IRQ is asserted as long as at least one of the three
interrupt sources has its flag and enable bits both set. The
IRQF bit in Register C is a "I" whenever the IRQ pin is being
driven "Low".
The processor program can determine that the RTC initiated
the interrupt by reading Register C. A "I" in bit 7 (IRQF bit)
indicates that one of more interrupts have been initiated by
the part. The act of reading Register C clears all the then-active
flag bits, plus the IRQF bit. When the program finds IRQF set,
it should look at each of the individual flag bits in the same
byte which have the corresponding interrupt-mask bits set
and service each interrupt which is set. Again, more than one
interrupt-flag bit may be set.
• DIVIDER STAGES
The HD146818 has 22 binary-divider stages following the
time base as shown in Figure 10. The output of the dividers is
a I Hz signal to the update-cycle logic. The dividers are controller by three divider bus (DV2, DVI, and DVO) in Register
A.
• Divider Control
The divider-control bits have three uses, as shown in Table
3. Three usable operating time bases may be selected (4.194304
MHz, 1.048576 MHz, or 32.768 kHz). The divider chain may
be held reset, which allows precision setting of the time. When
the divider is changed from reset to an operating time base,
the first update cycle is. one second later. The divider-control
bits are also used to facilitate testing the HD146818.
Table 3 Divider Configurations
Time-Base
Frequency
4.194304 MHz
1.048576 MHz
32.768 kHz
Any
Any
DV2
0
0
0
1
1
Divider Bits
Register A
DVl
0
0
1
1
1
DVO
0
1
0
0
1
Operation
Mode
Divider
Reset
Bypass First
N-Divider Bits
Yes
Yes
Yes
No
No
-
-
N=O
N =2
N=7
Yes
Yes
-
(NOTE) Other combinations of divider bits are used for test purposes only.
• Square-Wave Output Selection
Fifteen of the 22 divider taps are made available to a l-of-15
selector as shown in Figure 10. The fust purpose of selecting
a divider tap is to generate a square-wave output signal m the
SQW pin. Four bits in Register A establish the square-wave
frequency as listed in Table 4. The SQW frequency selection
shares the l-of-15 selector with periodic interrupts.
Once the frequency is selected, the output of the SQW pin
may be turned on and off under program control with the
square-wave enable (SQWE) bit in Register B. Altering the
divider, square-wave output selection bits, or the SQW outputenable bit may generate an asymetrical waveform at the time
of execution. The square-wave output pin has a number of
potential uses. For example, it can serve as a frequency standard
for external use, a frequency synthesizer, or could be used to
generate one or more audio tones under program control.
• Periodic Interrupt Selection
The periodic interrupt allows the IRQ pin to be triggered
from once every 500 ms to once every 30.517 j.lS. The periodic
interrupt is separate from the alarm interrupt which may be
output from once-per-second to once-per-day.
Table 4 shows that the periodic interrupt rate is selected
with the same Register A bits which select the square-wave
frequency. Changing one also changes the other. But each
function may be separately enabled so that a program could
switch between the two features or use both. The SQW pin
is enabled by the SQWE bit. Similarly the periodic interrupt is
enabled by the PIE bit in Register B.
Periodic interrupt is usable by practically all real-time systems. It can be used to scan for all forms of input from contact
closures to serial receive bits or tyes. It can be used in multiplexing displays or with software counters to measure inputs,
create output intervals, or await the next needed software function.
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
655
HD146818---------------------------------------------------------------Table 4 Periodic Interrupt Rate and Square Wave Output Frequency
Rate Select
Control Register 1
RS3
RS2
RSI
RSO
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
4.194304 or 1.048576 MHz
Time Base
Periodic
SQWOutput
Interrupt Rate
Frequency
tpi
None
None
30.517 liS
32.768 kHz
61.035 liS
16.384 kHz
8.192 kHz
122.070 liS
4.096 kHz
244.141115
488.281115
2.048 kHz
1.024 kHz
976.562115
512 Hz
1.953125 ms
3.90625 ms
256 Hz
7.8125 ms
128 Hz
15.625 ms
64 Hz
31.25 ms
32 Hz
62.5 ms
16 Hz
125 ms
8 Hz
250 ms
4 Hz
500ms
2 Hz
• Initialization of the Time and the Start Sequence
The first update of the time occurs about 500ms later after
the SET bit of control register B is reset. So keep followings in
mind when initializing and adjusting the time.
Procedure of time initialization
(1) Set the SET bit of control register B. (SET = "I")
(2) Set "1" into all the DVO, I, 2 bits of control register A.
(DVO =DVI =DV2 = "1")
(3) Set the time and calendar to each RAM.
(4) Set the frequency in use into DVO, 1 and DV2.
(5) Reset the SET bit. (SET = "0")
U"B
..
('IIII_rA)
15OOm1-15111
Ln~
~ ~
!4MHJ'IMHZL-J
Ttm.,nOl'-'n
(SETbJtl ..... 01
2441'1+24811S
i24411.+1!J84j1S(38kHz})
I
1 Second
32.768 kHz
Time Base
Periodic
Interrupt Rate
tpi
None
3.90625 ms
7.8125 ms
122.070115
244. 141 115
488.281115
976.562115
1.953125 ms
3.90625 ms
7.8125 ms
15.625 ms
31.25 ms
62.5 ms
125 ms
250ms
500ms
None
256 Hz
128 Hz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
512 Hz
256 Hz
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
day shown below.
Calendar, Time of day
Examples
& Status after Update
If 29th 23:59:59 in all the months is initial·
Mar. 29th
ized, update to 1st in the next month is
--Apr. 1st
executed. (Jan. - Dec. However except for
Feb. 29th in leap year)
If 30th 23: 59 :59 in Apr., June, Sept., and
Apr. 30th
Nov. is initialized, update to 31st in each
--Apr. 31st
month is executed.
If Feb. 28th 23:59:59 (not in leap year) is
Feb. 28th,1983
initialized, update to Feb. 29th is executed. -- Feb. 29th,1983
If Feb. 28th 23:59: 58 (in leap year) is ini·
Feb. 28th,1984
tialized, update to Mar. 1st is executed.
--Mar.lst,1984
1 Second
Figure 15 Time Initialization and the First Update
Restriction on Time-of-day and Calendar Initialization
There is a case in HDI46818 (RTC) that update is not executed correctly if time of day and calendar shown below are
initialized. Therefore, initialize the RTC without using time of
• UPDATE CYCLE
The HDI46818 executes an update cycle once-per-second,
assuming one of the proper time bases is in place, the divider
is not clear, and the SET bit in Register B is clear. The SET bit
in the "I" state permits the program to initialize the time and
calendar bytes by stopping an existing update and preventing
a new one from occurring.
The primary function of the update cycle is to increment
the seconds byte, check for overflow, increment the minutes
byte when appropriate and so forth through to the year of
the century byte. The update cycle also compares each alarm
byte with the corresponding time byte and issues an alarm
if a match or if a "don't care" code (11 XXXXXX) is present
in all three positions.
With a 4.194304 MHz or 1.048576 MHz time base the up-
~HITACHI
656
SQWOutput
Frequency
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
----------------------------------------------------------------HD146818
date cycle takes 248 j.ts while a 32.768 kHz time base update
cycle takes 1984 j.ts. During the update cycle, the time, calendar, and alarm bytes are not accessable by the processor
program. The HD146818 protects the program from reading
transitional data. This protection is provided by switching
the time, calendar, and alarm portion of the RAM off the
microprocessor bus during the entire update cycle. If the
processor reads these RAM locations before the update is
complete the output will be undefined. The update in progress
(UIP) status bit is set during the interval.
A program which randomly accesses the time and date information finds data unavailable statistically once every 4032
attempts. Three methods of accommodating nonavailability
during update are usable by the program. In discussing the
three methods it is assumed that at random points user programs are able to call a subroutine to obtain the time of day.
The first method of avoiding the update cycle uses the
update-ended interrupt. If enabled, an interrupt occurs after
every update cycle which indicates that over 999 ms are available to read valid time and date information. During this time
a display could be updated or the information could be transfered to continuously available RAM. Before leaving the interrupt service routine, the IRQF bit in Register C should be
cleared.
The second method uses the update-in-progress bit (UIP)
in Register A to determine if the update cycle is in progress
or not. The UIP bit will pulse once-per-second. Statistically,
the UIP bit will indicate that time and date information is
unavailable once every 2032 attempts. After the UIP bit goes
"I", the update cycle begins 244 j.ts later. Therefore, if a "0"
is read on the UIP bit, the user has at least 244 j.tS before the
time/calendar data will be changed. If a "I" is read in the
UIP bit, the time/c~endar data may not be valid. The user
should avoid interrupt service routines that would cause the
time needed to read valid time/ calendar data to exceed 244 j.tS.
The third method uses a periodic interrupt to determine if
an update cycle is in progress. The UIP bit in Register A is set
"I" between the setting of the PF bit in Register C (see Figure
16) Periodic interrupts that occur at a rate of greater than
tDue + tue allow valid time and date information to be read
at each occurrence of the periodic interrupt. The reads should
be completed within (tPI + 2) + tDue to insure that data is
not read during the update cycle.
•
POWER-DOWN CONSIDERATIONS
In most systems, the HDI46818 must continue to keep
time when system power is removed. In such systems, a conversion from system power to an alternate power supply,
usually a battery, must be made. During the transition from
system to battery power, the deSigner of a battery backed-up
RTC system must protect data integrity, minimize power
consumption, and ensure hardware reliability according to
the specification described in the section regarding Battery
Backed-up operation.
The chip enable (CE) pin controls all bus inputs (R/W, OS,
AS, ADo - AD,). CEo when negated, disallows any unintended
modification of the RTC data by the bus. CE also reduces
power consumption by reducing the number of transitions
seen internally.
Power consumption may be further reduced by removing
resistive and capacitive loads from the clock out (CKOUT)
pin and the squarewave (SQW) pin.
During and after the power source conversion, the V IN
maximum specification must never be exceeded. Failure to
meet the VIN maximum specification can cause a virtual
SCR to appear which may result in excessive current drain
and destruction of the part.
r----1
UIP bit in
Register A - - - - - - - - - - - - - t - a u - c - - J - - " i - n n m
....,t
' -uc------
I
UF bit in
Register C
-
PF bit inC
Register
~
tpi
!---tPI+2---j
tPI--ll
r-tPI+2--j
tlmm
L-_ _ _ _ _ _ _ _ _ _ _....
tlmm
......" -_ _ _ __
= Periodic Interrupt Time Interval (500 ms, 250 ms, 125 ms, 62.5 ms, etc.)
tue = Update Cycle Time (248"" or 1984".1
taue = Delay Time 8efore Update Cycle (244 ".1
Figure 16. Update-Ended and Periodic Interrupt Relationship
~HITACHI
Hitachi America Ltd . • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
657
H0146S1S---------------------------------------------------------------• SIGNAL DESCRIPTIONS
The block diagram in Figure 10, shows the pin connection
with the major internal functions of the HDI46818 Real-Time
Clock plus RAM. The following paragraphs describe the function of each pin.
• Vee. Vss
DC power is provided to the part on these two pins, Vee
being the most positive voltage. The minimum and maximum
voltages are listed in the Electrical Characteristics tables.
• OSC •• OSC, - Time Base
Input
by four. Table 5 summarizes the effect ofCKFS.
Table 5 Clock Output Frequencies
Time Base
(OSC,)
Frequency
4.194304 MHz
4.194304 MHz
1.048576 MHz
1.048576 MHz
32.768 kHz
32.768 kHz
Clock Frequency
Select Pin
(CKFS)
"High"
"Low"
"High"
"Low"
"High"
"Low"
Clock Frequency
Output Pin
(CKOUT)
4.194304 MHz
1.048576 MHz
1.048576 MHz
262.144 kHz
32.768 kHz
8.192 kHz
Pin No.2, 3
• saw The time base for the time functions may be an external
signal or the crystal oscillator. External square waves at
4.194304 MHz, 1.048576 MHz, or 32.768 kHz may be connected to OSC. as shown in Figure 17 The time-base frequency
to be used is chosen in Register A.
~
VCC
Optional
Square Wave
Output
Pin No. 23
The SQW pin can output a signal one of 15 of the 22
internal-divider stages. The frequency and output enable of
the SQW may be altered by programming Register A, as shown
in Table 4. The SQW signal may be turned on and off using
a bit in Register B.
(V cc -1.0V)
• ADo - AD7 - Multiplexed Bidirectional Address/Data Bus
4.194304 MHz
or
1.048576 MHz - - - - - <.......---..::.....j OSC.
Input/Output
or
32.768 kHz
(Open)
~
OSC,
HD146818
Figure 17 External Time·Base Connection
The on~hip oscillator is designed for a parallel resonant
crystal at 4.194304 MHz or 1.048576 MHz or 32.768 kHz frequencies. The crystal connections are shown in Figure 11.
• CKOUT - Clock Out
Output
Multiplexed bus processors save pins by presenting the
address during the first portion of the bus cycle and using
the same pins during the second portion for data. Addressthen-data multiplexing does not slow the access time of the
HD 146818 since the bus reversal from address to data is occurring during the internal RAM access time.
The address must be valid just prior to the fall of AS/ALE
at which time the HDI46818 latches the address from ADo to
ADs. Valid write data must be presented and held stable during
the latter portion of the DS or WR pulses. In a read cycle,
the HDl46818 outputs 8 bits of data during the latter portion
of the DS or RD pulses, then ceases driving the bus (returns
the output drivers to three-state) when DS falls in the HD6801,
HD6301 case or RD rises in the other case.
• AS - Multiplexed Address Strobe
Pin No. 21
The CKOUT pin is an output at the time-base frequency
divided by I or 4. A major use for CKOUT is as the input clock
to the microprocessor; thereby saving the cost of a second
crystal. The frequency of CKOUT depends upon the time-base
frequency and the state of the CKFS pin as shown in Table 5.
• CKFS - Clock Out Frequency Select
Input
Pin No.4 - II
Input
Pin No. 14
A positive going multiplexed address strobe pulse serves
to demultiplex the bus. The falling edge of AS or ALE causes
the address to be latched within the HD146818. The bus
control circuit in the HDl46818 also latches the state of the
DS pin with the falling edge of AS or ALE.
• OS - Data Strobe or Read
Pin No. 20
The CKOUT pin is an output at the time-base frequency
divided by 1 or 4. CKFS tied to Vee causes CKOUT to be the
same frequency as the time base at the OSC. pin. When CKFS
is at V ss , CKOUT is the OSC, time-base frequency divided
Input
Pin No. 17
The DS pin has two interpretations via the bus control
circuit. When emanating from 680 I family type processor,
~HITACH.
658
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
---------------------------------------------------------------HD146818
DS is a positive pulse during the latter portion of the bus
cycle, and is variously called DS (data strobe), E (enable), and
1/>2 (1/>2 clock). During read cycles, DS signifies the time that the
RTC is to drive the bidirectional bus. In write cycles, the trailing edge of DS causes the Real-Time Clock plus RAM to latch
the written data.
The second interpretation of DS is that of RD, MEMR, or
!/OR emanating from the 8085 type processor. In this case,
DS identifies the time period when the real-time clock plus
RAM drives the bus with read data. This interpretation of
DS is also the same as an output-
HD146818P (X type ..... Marked as follows)
Xor RX
r-----------~--~
•
2B2
H0146B1BP
JAPAN
< Restriction on usage>
Please set "0" to DSE bit (Daylight Saving Enable bit) on initializing the control register B.
DSE = "1" is prohibited.
RESTRICTION ON HD146818 USAGE (2)
Access to HD146818 needs to be performed under following conditions.
(i) Chip-enable (CE) must be asserted to active "Low" level only when MPU performs read/write operation from/into
internal RAM (Time and Calendar RAM, Control register, User RAM).
(ii) User RAM and control register must be accessed in less than 1/4 frequency shown below.
(Example: After one access, non-access cycles more than three cycles are necessary to be inserted.)
[Example
11
Addres.
~
Non·Access
Access to H0146818
[Example 21
Addre..
CE
~
Access to HD146818 (Two Continuous Accesses)
As shown in the above (example 2], when HD146818 is accessed continuously. continuous access must
not be executed over fifty times.
(iii) The application that User RAM is used for program area should be avoided. (Inhibit continuous access.)
(iv) Minimize the noise by inserting noise bypass condenser between power supply and ground pin (Vcc-V ss).
(Insert noise bypass condenser as near HD146818 as possible.)
RESTRICTION ON H0146818 USAGE (3)
Chip-enable (CE) must be stable between falling edge of OS and rising edge of AS shown below. (Address decoder hazard
needs to be externally suppressed in this period.)
AS
os
L..:. Eliminate hazard in this period.
662
~HITACHI
Hitachi America Ltd .• 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
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NOTES
NOTES
NOTES
Source Exif Data:
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