1987_Intersil_Component_Data_Catalog 1987 Intersil Component Data Catalog

User Manual: 1987_Intersil_Component_Data_Catalog

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ao

011.

Component Data
Catalog

1987

INTERSIL, INC., 10600 RIDGEVIEW COURT, CUPERTINO, CA 95014
Printed in U.S.A. @ Copyright 1987, Intersil, Inc., All Rights Reserved

(408) 996·5000 TWX: 910·338·2014
GE a n d . are registered trademarks of General Electric Company, U.S.A.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIeS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE All typical values have been characterized but are not tested.

Table of Contents

SELECTOR GUIDES
A/D CONVERTERS DISPLAY TYPE
A/D CONVERTERS

~P

TYPE

0/ A CONVERTERS
POWER SUPPLY SUPERVISORY
SPECIAL ANALOG
OPERATIONAL AMPLIFIERS
ANALOG SWITCHES
MULTIPLEXERS
DISCRETES
DATA COMMUNICATIONS
DIGITAL SIGNAL PROCESSING
DISPLAY DRIVERS
TIMERS/CLOCKS/COUNTERS WITH DISPLAY DRIVERS
HIGH RELIABILITY
ORDERING AND MARKING INFORMATION

II

•IIII

II
III

•DI

III

II

III
II
II
II
ILl

III

Functional Table of Contents
Page

Description

Section 1 -

Selector Guides

Section 2 -

AID Converters Display Type

ICL7106 3 YrDigit LCD Single-Chip AID Converter..................................
ICL71073 %-Digit LED Single-Chip AID Converter...................................
ICL7116 3 %-Digit with Display Hold Single-Chip AID Converter. . . . . . . . . . . . . . . . . . . . . . .
ICL71173 %-Digit with Display Hold Single-Chip AID Converter.......................
ICL7126 3 %-Digit Low-Power Single-Chip AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7129 4 % Digit LCD Single-Chip AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL71363 YrDigit LCD Low Power AID Converter...................................
ICL7137 3 %-Digit LED Low Power Single-Chip AID Converter. . . . . . . . . . . . . . . . . . . . . . . .
ICL7139 3%-Digit Autoranging Multimeter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7149 Low Cost 3%-Digit Autoranging Multimeter ..................................
ICL7182 101 Segment LCD Bargraph AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 3 -

3-1
3-1
3-1
3-19
3-19
3-39
3-58
3-60
3-74

DIA Converters

AD7520 10/12-Bit Multiplying D/A Converter........................................
AD7521 10/12-Bit Multiplying D/A Converter........................................
AD7530 10/12-Bit Multiplying D/A Converter........................................
AD7531 10/12-Bit Multiplying D/A Converter........................................
AD7523 8-Bit Multiplying DI A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AD7533 10-Bit Multiplying D/A Converter............................................
AD7541 12-Bit Multiplying D/A Converter............................................
ICL7121 16-Bit Multiplying Microprocessor-Compatible DI A Converter ..................
ICL7134 14-Bit Multiplying p,P-Compatible 01 A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IM2110 256 x 12 Color Lookup Table and DAC.......................................

Section 5 -

2-1
2-1
2-13
2-13
2-24
2-35
2-47
2-58
2-67
2-81
2-95

AID Converters p,P Type

ADC0802 8-Bit p,P-Compatible AID Converter .......................................
ADC0803 8-Bit p,P-Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
ADC0804 8-Bit p,P-Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
ICL7104/1CL8052 12/14/16-Bit p,P-Compatible 2-Chip AID Converter.................
ICL7104/1CL8068 12/14/16-Bit p,P-Compatible 2-Chip AID Converter.................
ICL7109 12-Bit p,P-Compatible AID Converter.......................................
ICL7112 12-Bit High-Speed CMOS p,P-Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . .
ICL711514-Bit High-Speed CMOS p,P-Compatible AID Converter.....................
ICL71354 %-Digit BCD Output AID Converter.......................................

Section 4 -

1-1

4-1
4-1
4-1
4-1
4-8
4-13
4-18
4-25
4-32
4-46

Power Supply Supervisory

ICL7660 CMOS Voltage Converter..................................................
ICL7660S Super Voltage Converter.................................................
ICL7662 CMOS Voltage Converter..................................................
ICL7663 CMOS Programmable Micropower Positive Voltage Regulator..................
ICL7663S CMOS Programmable Micropower Positive Voltage Regulator................
ICL7665 Micropower Under/Over Voltage Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7665S CMOS Micropower Over/Under Voltage Detector...........................

5-1
5-10
5-20
5-28
5-37
5-44
5-53

Functional Table of Contents
Description

Section 5 ICL7667
ICL7673
ICL7675
ICL7676
ICL7677
ICL7680
ICL8211
ICL8212

Page

Power Supply Supervisory (Continued)

Dual Power MOSFET Driver................................................ 5-63
Automatic Battery Back-up Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71
Switched-Mode Power Supply Controller Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79
Switched-Mode Power Supply Controller Set................ ................. 5-79
Power Fail Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-89
+ 5V to ± 15V Voltage Converter/Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-101
Programmable Voltage Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5:103
Programmable Voltage Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-103

Section 6 -

Special Analog

AD590 2-Wire Current Output Temperature Transducer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8013 Four Quadrant Analog Multiplier................................ ... .........
ICL8038 Precision Waveform Generator/Voltage Controlled Oscillator. . . . . . . . . . . . . . . . . .
ICL8048 Logarithmic Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8049 Antilog Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8069 Low Voltage Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 7 -

6-1
6-12
6-21
6-30
6-30
6-39

Operational Amplifiers

ICH8500/ A Ultra Low Input-Bias Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1
ICL7600 Com mutating Auto-Zero (CAZ) Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . .
7-7
ICL7601 Commutating Auto-Zero (CAZ) Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . .
7-7
ICL7605 Commutating Auto-Zero (CAZ) Instrumentation Amplifier...................... 7-19
ICL7606 Commutating Auto-Zero (CAD) Instrumentation Amplifier. . . . . . . . . . . . . . . . . . . . . . 7-19
ICL76XX Series Low Power CMOS Operational Amplifiers............................. 7-31
ICL7650 Chopper-Stabilized Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46
ICL7650S Super Chopper-Stabilized Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54
ICL7652 Chopper-Stabilized Low-Noise Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . 7-64
ICL7652S Super Chopper-Stabilized Low-Noise Operational Amplifier. . . . . . . . . . . . . . . . . . . 7-72
ICL8007 JFET Input Operational Amplifier............................... ............ 7-82
ICL8021 Low Power Bipolar Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-86
ICL8023 Triple Low Power Bipolar Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-86
ICL8043 Dual JFET Input Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-91
ICL8063 Power Transistor Driver/Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-99
LM4250 Programmable Operational Amplifier ........................................ 7-108

Section 8 -

Analog Switches

D123 SPST 6-Channel JFET Switch Driver..........................................
D125 SPST 6-Channel JFET Switch Driver................................. .........
D129 4-Channel Decoded JFET Switch Driver .......................................
DG 123 SPST 5-Channel Driver With Switch. .. . . .. . . .. .. .. . . . .. . . .. . .. . . . . . . .. . . . . .. .
DG 125 SPST 5-Channel Driver With Switch. .. . . . . . . .. . . . .. . . .. .. . . . . .. . . . . . . . . .. . .. .
DG126 Dual DPST 80 Ohm JFET Analog Switch.....................................
DG129 Dual DPST 30 Ohm JFET Analog Switch .....................................
DG133 Dual SPST 30/35 Ohm JFET Analog Switch..................................
DG134 Dual SPST 80 Ohm JFET Analog Switch......................................
DG140 Dual DPST 10/15 Ohm JFET Analog Switch..................................

8-1
8-1
8-5
8-7
8-7
8-11
8-11
8-11
8-11
8-11

Functional Table of Contents
Page

Description

Section 8 -

Analog Switches (Continued)

DG141 Dual SPST 10 Ohm JFET Analog Switch......................................
DG151 Dual SPST 15 Ohm JFET Analog Switch......................................
DG152 Dual SPST 50 Ohm JFET Analog Switch......................................
DG153 Dual DPST 15 Ohm JFET Analog Switch .....................................
DG154 Dual DPST 50 Ohm JFET Analog Switch.....................................
DG139 DPDT 30 Ohm Differentially Driven JFET Switch...............................
DG142 DPDT 80 Ohm Differentially Driven JFET Switch...............................
DG143 SPDT 80 Ohm Differentially Driven JFET Switch...............................
DG144 SPDT 30 Ohm Differentially Driven JFET Switch...............................
DG145 DPDT 10 Ohm Differentially Driven JFET Switch...............................
DG146 SPDT 10 Ohm Differentially Driven JFET Switch...............................
DG161 SPDT 15 Ohm Differentially Driven JFET Switch...............................
DG162 SPDT 50 Ohm Differentially Driven JFET Switch...............................
DG163 DPDT 15 Ohm Differentially Driven JFET Switch...............................
DG164 DPDT 50 Ohm Differentially Driven JFET Switch...............................
DG180 Dual SPST 10 Ohm High-Speed Driver With JFET Switch.......................
DG181 Dual SPST 30 Ohm High-Speed Driver With JFET Switch.......................
DG182 Dual SPST 75 Ohm High-Speed Driver With JFET Switch.......................
DG183 Dual DPST 10 Ohm High-Speed Driver With JFET Switch.......................
DG184 Dual DPST 30 Ohm High-Speed Driver With JFET Switch.......................
DG185 Dual DPST 75 Ohm High-Speed Driver With JFET Switch. . . . . . . . . . . . . . . . . . . . . . .
DG186 SPDT 10 Ohm High-Speed Driver With JFET Switch ...........................
DG187 SPDT 30 Ohm High-Speed Driver With JFET Switch...........................
DG188 SPDT 75 Ohm High-Speed Driver With JFET Switch ...........................
DG189 Dual SPDT 10 Ohm High-Speed Driver With JFET Switch.......................
DG190 Dual SPDT 30 Ohm High-Speed Driver With JFET Switch. . . . . . . . . . . . . . . . . . . . . . .
DG191 Dual SPDT 75 Ohm High-Speed Driver With JFET Switch. . . . . . . . . . . . . . . . . . . . . . .
DG200 Dual SPST CMOS Analog Switch ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DG201 Quad SPST CMOS Analog Switch...........................................
DG201A Quad Monolithic SPST CMOS Analog Switches..............................
DG202 Quad Monolithic SPST CMOS Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DG211 SPST 4-Channel Analog Switch .............................................
DG212 SPST 4-Channel Analog Switch.............................................
DG300A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DG301 A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . . . .
DG302A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DG303A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGM181 Dual SPST 50 Ohm High-Speed CMOS Analog Switch........................
DGM182 Dual SPST 50/75 Ohm High-Speed CMOS Analog Switch ....................
DGM184 Dual DPST 50 Ohm High-Speed CMOS Analog Switch.......................
DGM185 Dual DPST 50/75 Ohm High-Speed CMOS Analog Switch ....................
DGM190 Dual SPDT 50 Ohm High-Speed CMOS Analog Switch ....... :...............
DGM191 Dual SPDT 50/75 Ohm High-Speed CMOS Analog Switch....................
IH311 High Speed SPST 4-Channel Analog Switch . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . . . .
IH312 High Speed SPST 4-Channel Analog Switch...................................
IH401 QUAD Varafet Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH401A QUAD Varafet Analog Switch...............................................
IH5009 Quad 100 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5010 Quad 150 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii

8-11
8-11
8-11
8-11
8-11
8-17
8-17
8-17
8-17
8-17
8-17
8-17
8-17
8-17
8-17
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-28
8-32
8-36
8-36
8-41
8-41
8-44
8-44
8-44
8-44
8-49
8-49
8-49
8-49
8-49
8-49
8-54
8-54
8-59
8-59
8-65
8-65

Functional Table of Contents
Page

Description

Section 8 -

Analog Switches (Continued)

IH5011 Quad 100 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5012 Quad 150 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5013 Triple 100 Ohm Virtual Ground Analog Switch.................................
IH5014 Triple 150 Ohm Virtual Ground Analog Switch.................................
IH5015 Triple 100 Ohm Virtual Groung Analog Switch.................................
IH5016 Triple 150 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5017 Dual 100 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5018 Dual 150 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5019 Dual 100 Ohm Virtual Ground Analog Switch..................................
IH5020 Dual 150 Ohm Virtual Ground Analog Switch..................................
IH5021 Single 100 Ohm Virtual Ground Analog Switch ................................
IH5022 Single 150 Ohm Virtual Ground Analog Switch ................................
IH5023 Single 100 Ohm Virtual Ground Analog Switch ................................
IH5024 Single 150 Ohm Virtual Ground Analog Switch ................................
IH5040 SPST 75 Ohm High-Level CMOS Analog Switch...............................
IH5041 Dual SPST 75 Ohm High-Level CMOS Analog Switch..........................
IH5042 SPDT 75 Ohm High-Level CMOS Analog Switch...............................
IH5043 Dual SPDT 75 Ohm High-Level CMOS Analog Switch..........................
IH5044 DPST 75 Ohm High-Level CMOS Analog Switch.. .. . . .. . .. .. .. .. .. . .. . . .. . . .. .
IH5045 Dual DPST 75 Ohm High-Level CMOS Analog Switch..........................
IH5046 DPDT 75 Ohm High-Level CMOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5047 4PST 75 Ohm High-Level CMOS Analog Switch...............................
IH5048 Dual SPST 35 Ohm High-Level CMOS Analog Switch..........................
IH5049 Dual DPST 35 Ohm High-Level CMOS Analog Switch..........................
IH5050 SPDT 35 Ohm High-Level CMOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5051 Dual SPDT 35 Ohm High-Level CMOS Analog Switch..........................
IH5052 QUAD CMOS Analog Switch................................................
IH5053 QUAD CMOS Analog Switch................................................
IH5140 SPST High-Level CMOS Analog Switch.......................................
IH5141 Dual SPST High-Level CMOS Analog Switch..................................
IH5142 SPDT High-Level CMOS Analog Switch......................................
IH5143 Dual SPDT High-Level CMOS Analog Switch..................................
IH5144 DPST High-Level CMOS Analog Switch......................................
IH5145 Dual DPST High-Level CMOS Analog Switch..................................
IH5148 Dual SPST High-Level CMOS Analog Switch..................................
IH5149 Dual DPST High-Level CMOS Analog Switch..................................
IH5150 SPDT High-Level CMOS Analog Switch ......................................
IH5151 Dual SPDT High-Level CMOS Analog Switch..................................
IH5341 Dual SPST CMOS RFlVideo Switch ..........................................
IH5352 QUAD SPST CMOS RFlVideo Switch ........................................
MM450 Dual Differential High Voltage Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM451 Four Channel High Voltage Multiplexer.......................................
MM452 Quad SPST High Voltage Analog Switch .....................................
MM455 Three SPST High Voltage Analog Switch.....................................
MM550 Dual Differential High Voltage Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM551 Four Channel High Voltage Multiplexer.......................................
MM552 Quad SPST High Voltage Analog Switch .................. :..................
MM555 Three SPST High Voltage Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iv

8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-72
8-72
8-72
8-72
8-72
8-72
8-72
8-72
8-81
8-81
8-81
8-81
8-86
8-86
8-92
8-92
8-92
8-92
8-92
8-92
8-103
8-103
8-103
8-103
8-111
8-117
8-122
8-122
8-122
8-122
8-122
8-122
8-122
8-122

Functional Table of Contents
Description

Section 9 -

Page

Multiplexers

IH5108 8-Channel Fault Protected Analog Multiplexer....................... ..........
IH511616-Channel Fault Protected Analog Multiplexer................................
IH5208 4-Channel Differential Fault Protected Analog Multiplexer......................
IH5216 8-Channel Differential Fault Protected Analog Multiplexer ......................
IH6108 8-Channel CMOS Analog Multiplexer ........................................
IH6116 16-Channel CMOS Analog Multiplexer ............................. . . . . . . . . . .
IH6201 Dual CMOS DriverlVoltage Translator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH6208 4-Channel Differential CMOS Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH6216 8-Channel Differential CMOS Analog Multiplexer..............................
IH9108 8-Channel High-Voltage Multiplier with Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 10 -

9-1
9-10
9-14
9-23
9-27
9-33
9-40
9-44
9-50
9-56

Discretes

2N2607 P-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N2608 P-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N2609 P-Channel JFET General Purpose Amplifier..................................
2N2609JAN P-Channel JFET General Purpose Amplifier..............................
2N3684 N-Channel JFET Low Noise Amplifier .......................................
2N3685 N-Channel JFET Low Noise Amplifier .......................................
2N3686 N-Channel JFET Low Noise Amplifier .......................................
2N3687 N-Channel JFET Low Noise Amplifier .......................................
2N381 0/ A Monolithic Dual Matched PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . .
2N3811 / A Monolithic Dual Matched PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . .
2N3821 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3821JAN N-Channel JFET High Frequency Amplifier......................... ......
2N3821 JTX N-Channel JFET High Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3821 JTXV N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822JAN N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822JTX N-Channel JFET High Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822JTXV N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3823 N-Channel JFET High Frequency Amplifier...................................
2N3823JAN N-Channel JFET High Frequency Amplifier...............................
2N3823JTX N-Channel JFET High Frequency Amplifier...............................
2N3823JTXV N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3824 N-Channel JFET Switch ...................................................
2N3921 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3922 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3954 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N3954A Monolithic Dual N-Channel JFET General Purpose Amplifier......... .........
2N3955 Monolithic Dual N-Channel JFET General Purpose Amplifier.......... .........
2N3955A Monolithic Dual N-Channel JFET General Purpose Amplifier..................
2N3956 Monolithic Dual N-Channel JFET General Purpose Amplifier .......... . . . . . . . ..
2N3957 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N3958 Monolithic Dual N-Channel JFET General Purpose Amplifier .......... . . . . . . . ..
2N3970 N-Channel JFET Switch ...................................................
2N3971 N-Channel JFET Switch ...................................................
2N3972 N-Channel JFET Switch ...................................................
2N3993 P-Channel JFET General Purpose Amplifier/Switch. . . . . . . . . . . . . . . . . . . . . . . . . ..
v

10-1
10-1
10-1
10-1
10-2
10-2
10-2
10-2
10-3
10-3
10-5
10-5
10-5
10-5
10-5
10-5
10-5
10-5
10-7
10-7
10-7
10-7
10-8
10-9
10-9
10-11
10-11
10-11
10-11
10-11
10-11
10-11
10-13
10-13
10-13
10-15

Functional Table of Contents
Description

Section 1 0 -

Page

Discretes (Continued)

2N3994 P-Channel JFET General Purpose Amplifier/Switch. . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4044 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N4045 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N41 00 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N4878 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier...........
2N4879 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N4880 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N4091 JANTX N-Channel JFET Switch ............................................
2N4091 N-Channel JFET Switch ...................................................
2N4092 JANTX N-Channel JFET Switch............................................
2N4092 N-Channel JFET Switch...................................................
2N4093 JANTX N-Channel JFET Switch ............................................
2N4093 N-Channel JFET Switch ...................................................
ITE4091 N-Channel JFET Switch ...................................................
ITE4092 N-Channel JFET Switch ...................................................
ITE4093 N-Channel JFET Switch...................................................
2N4117 N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4117 AN-Channel JFET General Purpose Amplifier ................................
2N4118 N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4118A N-Channel JFET General Purpose Amplifier ................................
2N4119 N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4119A N-Channel JFET General.Purpose Amplifier ................................
2N4220 N-Channel JFET General Purpose Amplifier/Switch...........................
2N4221 N-Channel JFET General Purpose Amplifier/Switch. . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4222 N-Channel JFET General Purpose Amplifier/Switch...........................
2N4223 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4224 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4338 N-Channel JFET Low Noise Amplifier .......................................
2N4339 N-Channel JFET Low Noise Amplifier .......................................
2N4340 N-Channel JFET Low Noise Amplifier .......................................
2N4341 N-Channel JFET Low Noise Amplifier .......................................
2N4351 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch .....
2N4391 N-Channel JFET Switch ...................................................
2N4392 N-Channel JFET Switch ...................................................
2N4393 N-Channel JFET Switch ...................................................
ITE4391 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITE4392 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITE4393 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4416/ AN-Channel JFET High Frequency Amplifier ................................
ITE4416 N-Channel JFET High Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4856 N-Channel JFET Switch ...................................................
2N4856JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4857 N-Channel JFET Switch ...................................................
2N4857JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4858 N-Channel JFET Switch ...................................................
2N4858JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4859 N-Channel JFET Switch ...................................................
2N4859JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4860 N-Channel JFET Switch ...................................................
vi

10-15
10-16
10-16
10-16
10-16
10-16
10-16
10-19
10-19
10-19
10-19
10-19
10-19
10-19
10-19
10-19
10-21
10-21
10-21
10-21
10-21
10-21
10-22
10-22
10-22
10-23
10-23
10-24
10-24
10-24
10-24
10-25
10-26
10-26
10-26
10-26
10-26
10-26
10-28
10-28
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30

Functional Table of Contents
Description

Section 1 0 -

Page

Discretes (Continued)

2N4860JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4861 N-Channel JFET Switch ...................................................
2N4861JAN,JTX,JTXV N-Channel JFET Switch....................... ...............
2N4867 / AN-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4868/ AN-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4869/ AN-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5018 P-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5019 P-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5114 P-Channel JFET Switch. . . .. . .. . .. .. .. .. . .. . . .. . .. . .. .. . . .. . .. . .. .. .. . .. . ..
2N5114JAN,JTX,JTXV P-Channel JFET Switch.............. ........................
2N5115 P-Channel JFET Switch. . . .. . . .. .. .. .. .. . . .. . . . . . . . .. .. . . .. . .. . .. .. .. . . .. ..
2N5115JAN,JTX,JTXV P-Channel JFET Switch ......................................
2N5116 P-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5116JAN,JTX,JTXV P-Channel JFET Switch........... ...........................
2N5117 Dielectrically Isolated Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . ..
2N5118 Dielectrically Isolated Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . ..
2N5119 Dielectrically Isolated Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . ..
2N5196 Dual N-Channel JFET General Purpose Amplifier.............................
2N5197 Dual N-Channel JFET General Purpose Amplifier.............................
2N5198 Dual N-Channel JFET General Purpose Amplifier.............................
2N5199 Dual N-Channel JFET General Purpose Amplifier .............................
2N5397 N-Channel JFET High Frequency Amplifier...................................
2N5398 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5432 N-Channel JFET Switch ...................................................
2N5433 N-Channel JFET Switch ...................................................
2N5434 N-Channel JFET Switch ...................................................
2N5452 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5453 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5454 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5457 N-Channel JFET General Purpose Amplifier/Switch...........................
2N5458 N-Channel JFET General Purpose Amplifier/Switch...........................
2N5459 N-Channel JFET General Purpose Amplifier/Switch...........................
2N5460 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5461 P-Channel JFET Low Noise Amplifier........................................
2N5462 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5463 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5464 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5465 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5484 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5485 N-Channel JFET High Frequency Amplifier...................................
2N5486 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5515 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5516 Dual N-Channel JFET Low Noise Amplifier...................................
2N5517 Dual N-Channel JFET Low Noise Amplifier ...................................
2N5518 Dual N-Channel JFET Low Noise Amplifier ...................................
2N5519 Dual N-Channel JFET Low Noise Amplifier .. : ................................
2N5520 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5521 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5522 Dual N-Channel JFET Low Noise Amplifier...................................
vii

10-30
10-30
10-30
10-32
10-32
10-32
10-33
10-33
10-35
10-35
10-35
10-35
10-35
10-35
10-37
10-37
10-37
10-39
10-39
10-39
10-39
10-41
10-41
10-43
10-43
10-43
10-45
10-45
10-45
10-47
10-47
10-47
10-48
10-48
10-48
10-48
10-48
10-48
10-50
10-50
10-50
10-52
10-52
10-52
10-52
10-52
10-52
10-52
10-52

Functional Table of Contents
Description

Section 10 -

Page

Discretes (Continued)

2N5523 Dual N-Channel JFET Low Noise Amplifier...................................
2N5524 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5638 N-Channel JFET Switch ...................................................
2N5639 N-Channel JFET Switch ...................................................
2N5640 N-Channel JFET Switch ...................................................
2N5902 Monolithic Dual N-Channel JFET General Purpose Amplifier................ ...
2N5903 Monolithic Dual N-Channel JFET General Purpose Amplifier...................
2N5904 Monolithic Dual N-Channel JFET General Purpose Amplifier . . . . . . . . . . . . . . . . . ..
2N5905 Monolithic Dual N-Channel JFET General Purpose Amplifier...................
2N5906 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5907 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5908 Monolithic Dual N-Channel JFET General Purpose Amplifier...................
2N5909 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5911 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5912 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT5911 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT5912 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITC5911 Dual N-Channel JFET High Frequency Amplifier .............................
ITC5912 Dual N-Channel JFET High Frequency Amplifier .............................
2N6483 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N6484 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N6485 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3N161 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose
Amplifier/Switch..............................................................
3N163 P-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch......
3N164 P-Channel Enhancement Mode MOSFET General Purpose/Switch..............
3N165 Monolithic Dual P-Channel Enhancement Mode MOSFET General Purpose
Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3N166 Monolithic Dual P-Channel Enhancement Mode MOSFET General Purpose
Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3N170 N-Channel Enhancement Mode MOSFET Switch ..............................
3N171 N-Channel Enhancement Mode MOSFET Switch..............................
3N172 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose
Amplifier/Switch..............................................................
3N173 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose
Amplifier/Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . ..
3N188 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier........
3N189 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier. . . . . . ..
3N190 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ........
3N191 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ........
10100 Dual Low Leakage Diode....................................................
ID101 Dual Low Leakage Diode ....................................................
IT100 P-Channel JFET Switch.................... ..................................
IT101 P-Channel JFET Switch ......................................................
IT120 Dual NPN General Purpose Amplifier..........................................
IT120A Dual NPN General Purpose Amplifier.........................................
IT121 Dual NPN General Purpose Amplifier..........................................
IT122 Dual NPN General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT126 Monolithic Dual NPN General Purpose Amplifier ................................
viii

10-52
10-52
10-54
10-54
10-54
10-56
10-56
10-56
10-56
10-56
10-56
10-56
10-56
10-58
10-58
10-58
10-58
10-58
10-58
10-60
10-60
10-60
10-62
10-63
10-63
10-65
10-65
10-67
10-67
10-69
10-69
10-71
10-71
10-71
10-71
10-73
10-73
10-75
10-75
10-76
10-76
10-76
10-76
10-78

Functional Table of Contents
Page

Description

Section 1 0 -

Discretes (Continued)

IT127 Monolithic Dual NPN General Purpose Amplifier ................................
1T128 Monolithic Dual NPN General Purpose Amplifier ................................
1T129 Monolithic Dual NPN General Purpose Amplifier................................
1T130 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT130A Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT131 Monolithic Dual PNP General Purpose Amplifier.................................
1T132 Monolithic Dual PNP General Purpose Amplifier.................................
IT136 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT137 Monolithic Dual PNP General Purpose Amplifier.................................
IT138 Monolithic Dual PNP General Purpose Amplifier.................................
1T139 Monolithic Dual PNP General Purpose Amplifier.................................
IT500 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT501 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT502 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT503 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT504 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT505 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT1700 P-Channel Enhancement Mode MOSFET General Purpose Amplifier. . . . . . . . . . . ..
IT1750 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch.....
J105 N-Channel JFET Switch .. .. . .. .. .. . .. .. . .. . .. . .. . .. .. . .. .. . .. .. . .. .. .. . . . .. ..
J106 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
J107 N-Channel JFET Switch......................................................
J108 N-Channel JFET Switch......................................................
J109 N-Channel JFET Switch......................................................
J110 N-Channel JFET Switch......................................................
J111 N-Channel JFET Switch ......................................................
J112 N-Channel JFET Switch......................................................
J113 N-Channel JFET Switch......................................................
J174 P-Channel JFET Switch ......................................................
J175 P-Channel JFET Switch ......................................................
J176 P-Channel JFET Switch ......................................................
J177 P-Channel JFET Switch ......................................................
J201 N-Channel JFET General Purpose Amplifier ....................................
J202 N-Channel JFET General Purpose Amplifier ....................................
J203 N-Channel JFET General Purpose Amplifier....................................
J204 N-Channel JFET General Purpose Amplifier ....................................
J308 N-Channel JFET High Frequency Amplifier .....................................
J309 N-Channel JFET High Frequency Amplifier.....................................
J310 N-Channel JFET High Frequency Amplifier.....................................
LM 114/H Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM 114A1 AH Monolithic Dual NPN General Purpose Amplifier . . . . . . . . . . . . . . . . . . . . . . . . ..
M116 Diode Protected N-Channel Enhancement Mode MOSFET General Purpose
Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
U200 N-Channel JFET Switch ......................................................
U201 N-Channel JFET Switch ......................................................
U202 N-Channel JFET Switch ......................................................
U231 Dual N-Channel JFET General Purpose Amplifier ...............................
U232 Dual N-Channel JFET General Purpose Amplifier ...............................
U233 Dual N-Channel JFET General Purpose Amplifier ...............................
ix

10-78
10-78
10-78
10-80
10-80
10-80
10-80
10-82
10-82
10-82
10-82
10-84
10-84
10-84
10-84
10-84
10-84
10-87
10-88
10-89
10-89
10-89
10-90
10-90
10-90
10-91
10-91
10-91
10-92
10-92
10-92
10-92
10-94
10-94
10-94
10-94
10-95
10-95
10-95
10-97
10-97
10-99
10-100
10-100
10-100
10-101
10-101
10-101

Functional Table of Contents
Description

Section 10 -

Page

Discretes (Continued)

U234 Dual N-Channel JFET General Purpose Amplifier .......•....................... 10-101
U235 Dual N-Channel JFET General Purpose Amplifier ............................... 10-101
U257 Dual N-Channel JFET High Frequency Amplifier ................................ 10-103
U304 P-Channel JFET Switch ...................................................... 10-104
U305 P-Channel JFET Switch ...................................................... 10-104
U306 P-Channel JFET Switch ...................................•.................. 10-104
U308 N-Channel JFET High Frequency Amplifier ..................................... 10-106
U309 N-Channel JFET High Frequency Amplifier ..................................... 10-106
U310 N-Channel JFET High Frequency Amplifier ..................................... 10-106
U401 Dual N-Channel JFET Switch ................................................. 10-108
U402 Dual N-Channel JFET Switch ................................................. 10-108
U403 Dual N-Channel JFET Switch .........•........•.............................. 10-108
U404 Dual N-Channel JFET Switch ................................................. 10-108
U405 Dual N-Channel JFET Switch ................................................. 10-108
U406 Dual N-Channel JFET Switch ................................................. 10-108
U1897 N-Channel JFET Switch ..................................................... 10-110
U1898 N-Channel JFET Switch ..................................................... 10-110
U1899 N-Channel JFET Switch .........................•........................... 10-110
VCR2N Voltage Controlled Resistors ................................................ 10-112
VCR3P Voltage Controlled Resistors ................................................ 10-112
VCR4N Voltage Controlled Resistors ................................................ 10-112
VCR5P Voltage Controlled Resistors ................................................ 10-112
VCR7N Voltage Controlled Resistors ................................................ 10-112
VCR11N Voltage Controlled Resistors ............................................... 10-115

Section 11 -

Data Communications

IM26C91 Universal Asynchronous Receiver/Transmitter (UART) .......................
IM4702/4712 Baud Rate Generator.................................................
IM6402 Universal Asynchronous Receiver Transmitter (UART) .........................
IM6403 Universal Asynchronous Receiver Transmitter (UART) .........................
ICL232 + 5 Volt Powered Dual RS-232 Transmitter/Receiver . . . . . . . . . . . . . . • . . . . . . . . . ..

Section 12 -

11-1
11-19
11-26
11-26
11-36

Digital Signal Processing

IM29C128 Finite Impulse Response Filter Controller.................................. 12-1
IM29C510 CMOS 16 x 16 Bit, Multiplier/Accumulator................................. 12-7
EVK-128 Data Conversion and FIR Filtering System................................... 12-19

Section 13 -

Display Driver.

ICM7211 4-Digit LCD/LED Display Driver. . .. . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . .. . . . . . . .
ICM7212 4-Digit LCD/LED Display Driver............................................
ICM7218 8-Digit LED Multiplexed Display Driver......................................
ICM7228 8-Digit LED Multiplexed Display Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7231 Numeric Triplexed LCD Display Driver ........ ;.............................
ICM7232 Numeric Triplexed LCD Display Driver ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7233 Alphanumeric Triplexed LCD Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7243 8-Character LED ,...P-Compatible Display Driver .•..................•........
x

13-1
13-1
13-12
13-23
13-36
13-36
13-36
13-55

Functional Table of Contents
Description

Section 14 -

Page

Timers/Clocks/Counters with Display Drivers

ICM7170 p,P-Compatible Real-Time Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICM7207 / A CMOS Timebase Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7208 7-Digit LED Display Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7209 Timebase Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7215 6-Digit LED Display 4-Function Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7216A 8-Digit Multi-Function Frequency Counter/Timer . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7216B 8-Digit Multi-Function Frequency Counter/Timer . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7216C 8-Digit Frequency Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7216D 8-Digit Frequency Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7217 4-Digit LED Display Programmable Up/Down Counter. . . . . . . . . . . . . . . . . . . . . . ..
ICM7227 4-Digit LED Display Programmable Up/Down Counter. . . . . . . . . . . . . . . . . . . . . . ..
ICM72244 %-Digit LCD/LED Display Counter .......................................
ICM72254 %-Digit LCD/LED Display Counter .......................................
ICM7226A1B 8-Digit Multi-Function Frequency Counter/Timer.........................
ICM72364 %-Digit CounterlVacuum Fluorescent Display Driver.......................
ICM7240 Programmable Timer .....................................................
ICM7250 Programmable Timer .....................................................
ICM7242 Long-Range Fixed Timer ..................................................
ICM7249 5%-Digit LCD p,-Power Event/Hour Meter ..................................
ICM7555 General Purpose Timer ...................................................
ICM7556 Dual General Purpose Timer ...............................................

14-1
14-14
14-19
14-26
14-29
14-36
14-36
14-36
14-36
14-54
14-54
14-72
14-72
14-80
14-93
14-98
14-98
14-108
14-114
14-123
14-123

Section 15 -

High Reliability...........................................

15-1

Section 16 -

Ordering and Marking Information....... . . . . . . . . . . .

16-1

xi

Alphanumeric Index
2N2607 P-Channel JFET General Purpose Amplifier..................................
2N2608 P-Channel JFET General Purpose Amplifier..................................
2N2609 P-Channel JFET General Purpose Amplifier..................................
2N2609JAN P-Channel JFET General Purpose Amplifier..............................
2N3684 N-Channel JFET Low Noise Amplifier .......................................
2N3685 N-Channel JFET Low Noise Amplifier .......................................
2N3686 N-Channel JFET Low Noise Amplifier .......................................
2N3687 N-Channel JFET Low Noise Amplifier.......................................
2N381 0/ A Monolithic Dual Matched PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . .
2N3811/ A Monolithic Dual Matched PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . .
2N3821 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3821 JAN N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3821JTX N-Channel JFET High Frequency Amplifier...............................
2N3821JTXV N-Channel JFET High Frequency Amplifier..............................
2N3822 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822JAN N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822JTX N-Channel JFET High Frequency Amplifier .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822JTXV N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3823 N-Channel JFET High Frequency Amplifier...................................
2N3823JAN N-Channel JFET High Frequency Amplifier...............................
2N3823JTX N-Channel JFET High Frequency Amplifier...............................
2N3823JTXV N-Channel JFET High Frequency Amplifier..............................
2N3824 N-Channel JFET Switch ...................................................
2N3921 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . • . . . . .
2N3922 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3954 Monolithic Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . ..
2N3954A Monolithic Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . ..
2N3955 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N3955A Monolithic Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . ..
2N3956 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N3957 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N3958 Monolithic Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . ..
2N3970 N-Channel JFET Switch ...................................................
2N3971 N-Channel JFET Switch...................................................
2N3972 N-Channel JFET Switch...................................................
2N3993 P-Channel JFET General Purpose Amplifier/Switch ...........................
2N3994 P-Channel JFET General Purpose Amplifier/Switch. . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4044 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N4045 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier...........
2N4091 JANTX N-Channel JFET Switch............................................
2N4091 N-Channel JFET Switch ........................... ~.......................
2N4092 N-Channel JFET Switch...................................................
2N4092 JANTX N-Channel JFET Switch ............................................
2N4093 JANTX N-Channel JFET Switch ............................................
2N4093 N-Channel JFET Switch ...................................................
2N4100 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier...........
2N4117 N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4117 AN-Channel JFET General Purpose Amplifier ................................
2N4118 N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..
2N4118A N-Channel JFET General Purpose Amplifier ................................
2N4119 N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4119A N-Channel JFET General Purpose Amplifier ................................
2N4220 N-Channel JFET General Purpose Amplifier/Switch...........................
xii

10·1
10·1
10"1
10·1
10·2
10·2
10·2
10·2
10·3
10·3
10·5
10·5
10·5
10-5
10-5
10-5
10-5
10·5
10-7
10-7
10-7
10-7
10-8
10-9
10-9
10-11
10-11
10-11
10-11
10-11
10-11
10-11
10-13
10-13
10-13
10-15
10-15
10-16
10-16
10-19
10-19
10-19
10-19
10-19
10-19
10-16
10-21
10-21
10-21
10-21
10-21
10-21
10-22

Alphanumeric Index

(Continued)

2N4221 N-Channel JFET General Purpose Amplifier/Switch...........................
2N4222 N-Channel JFET General Purpose Amplifier/Switch...........................
2N4223 N-Channel JFET High Frequency Amplifier...................................
2N4224 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4338 N-Channel JFET Low Noise Amplifier.......................................
2N4339 N-Channel JFET Low Noise Amplifier.......................................
2N4340 N-Channel JFET Low Noise Amplifier .......................................
2N4341 N-Channel JFET Low Noise Amplifier.......................................
2N4351 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch .....
2N4391 N-Channel JFET Switch ...................................................
2N4392 N-Channel JFET Switch ...................................................
2N4393 N-Channel JFET Switch ...................................................
2N4416/ A N-Channel JFET High Frequency Amplifier ................................
2N4856 N-Channel JFET Switch ...................................................
2N4856JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4857 N-Channel JFET Switch ...................................................
2N4857JAN,JTX,JTXV N-Channel JFET Switch......................................
2N4858 N-Channel JFET Switch ...................................................
2N4858JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4859 N-Channel JFET Switch ...................................................
2N4859JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4860 N-Channel JFET Switch ...................................................
2N4860JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4861 N-Channel JFET Switch ...................................................
2N4861 JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4867 / A N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4868/ A N-Channel JFET Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4869/ A N-Channel JFET Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4878 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N4879 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier...........
2N4880 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier...........
2N5018 P-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5019 P-Channel JFET Switch ....................................................
2N5114 P-Channel JFET Switch....................................................
2N5114JAN,JTX,JTXV P-Channel JFET Switch ......................................
2N5115 P-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5115JAN,JTX,JTXV P-Channel JFET Switch ......................................
2N5116 P-Channel JFET Switch ....................................................
2N5116JAN,JTX,JTXV P-Channel JFET Switch ......................................
2N5117 Dielectrically Isolated Dual PNP General Purpose Amplifier.....................
2N5118 Dielectrically Isolated Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . ..
2N5119 Dielectrically Isolated Dual PNP General Purpose Amplifier. . . . . . . . . . . . .. . . . . . ..
2N5196 Dual N-Channel JFET General Purpose Amplifier.............................
2N5197 Dual N-Channel JFET General Purpose Amplifier.............................
2N5198 Dual N-Channel JFET General Purpose Amplifier.............................
2N5199 Dual N-Channel JFET General Purpose Amplifier.............................
2N5397 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5398 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5432 N-Channel JFET Switch ...................................................
2N5433 N-Channel JFET Switch ............................... -. . . . . . . . . . . . . . . . . . ..
2N5434 N-Channel JFET Switch .................................................. :
2N5452 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5453 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
xiii

10-22
10-22
10-23
10-23
10-24
10-24
10-24
10-24
10-25
10-26
10-26
10-26
10-28
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-32
10-32
10-32
10-16
10-16
10-16
10-33
10-33
10-35
10-35
10-35
10-35
10-35
10-35
10-37
10-37
10-37
10-39
10-39
10-39
10-39
10-41
10-41
10-43
10-43
10-43
10-45
10-45

Alphanumeric Index

(Continued)

2N5454 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5457 N-Channel JFET General Purpose Amplifier/Switch...........................
2N5458 N-Channel JFET General Purpose Amplifier/Switch...........................
2N5459 N-Channel JFET General Purpose Amplifier/Switch...........................
2N5460 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5461 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5462 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5463 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5464 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5465 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5484 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5485 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5486 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5515 Dual N-Channel JFET Low Noise Amplifier...................................
2N5516 Dual N-Channel JFET Low Noise Amplifier...................................
2N5517 Dual N-Channel JFET Low Noise Amplifier ...................................
2N5518 Dual N-Channel JFET Low Noise Amplifier...................................
2N5519 Dual N-Channel JFET Low Noise Amplifier...................................
2N552Q Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5521 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5522 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5523 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5524 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5638 N-Channel JFET Switch ...................................................
2N5639 N-Channel JFET Switch ...................................................
2N5640 N-Channel JFET Switch ...................................................
2N5902 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5908 Monolithic Dual N-Channel JF[::T General Purpose Amplifier ...................
2N5904 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5905 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5906 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5907 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5908 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5909 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5911 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5912 Dual N-Channel JFET High Frequency Amplifier..............................
2N6483 Dual N-Channel JFET Low Noise Amplifier...................................
2N6484 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N6485 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3N161 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose
Amplifier/Switch..............................................................
3N163 P-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch......
3N164 P-Channel Enhancement Mode MOSFET General Purpose/Switch..............
3N165 Monolithic Dual P-Channel Enhancement Mode MOSFET General Purpose
Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3N166 Monolithic Dual P-Channel Enhancement Mode MOSFET General Purpose
Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3N170 N-Channel Enhancement Mode MOSFET Switch ..............................
3N171 N-Channel Enhancement Mode MOSFET Switch ..............................
3N172 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose
Amplifier/Switch..............................................................
3N173 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose
Amplifier/Switch.................... ..........................................
xiv

10-45
10-47
10-47
10-47
10-48
10-48
10-48
10-48
10-48
10-48
10-50
10-50
10-50
10-52
10-52
10-52
10-52
10-52
10-52
10-52
10-52
10-52
10-52
10-54
10-54
10-54
10-56
10-56
10-56
10-56
10-56
10-56
10-56
10-56
10-58
10-58
10-60
10-60
10-60
10-62
10-63
10-63
10-65
10-65
10-67
10-67
10-69
10-69

Alphanumeric Index

(Continued)

3N188 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier........
3N189 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier........
3N190 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier........
3N191 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier........
AD590 2-Wire Current Output Temperature Transducer. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
AD7520 10/12-Bit Multiplying D/A Converter........................................
AD7521 10/12-Bit Multiplying D/A Converter........................................
AD7523 8-Bit Multiplying D/ A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AD7530 10/12-Bit Multiplying D/A Converter........................................
AD7531 10/12-Bit Multiplying D/A Converter........................................
AD7533 10-Bit Multiplying DI A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AD7541 12-Bit Multiplying D/A Converter............................................
ADC0802 8-Bit J.LP-Compatible AID Converter.......................................
ADC0803 8-Bit J.LP-Compatible AID Converter.......................................
ADC0804 8-Bit J.LP-Compatible AID Converter.......................................
D123 SPST 6-Channel JFET Switch Driver..........................................
D125 SPST 6-Channel JFET Switch Driver..........................................
D129 4-Channel Decoded JFET Switch Driver .......................................
DG123 SPST 5-Channel Driver With Switch..........................................
DG 125 SPST 5-Channel Driver With Switch.. .. .. . .. . . .. . . .. . .. .. .. .. .. . .. .. .. . . . .. . .
DG126 Dual DPST 80 Ohm JFET Analog Switch.....................................
DG129 Dual DPST 30 Ohm JFET Analog Switch.....................................
DG133 Dual SPST 30/35 Ohm JFET Analog Switch..................................
DG134 Dual SPST 80 Ohm JFET Analog Switch......................................
DG139 DPDT 30 Ohm Differentially Driven JFET Switch...............................
DG140 Dual DPST 10/15 Ohm JFET Analog Switch..................................
DG141 Dual SPST 10 Ohm JFET Analog Switch......................................
DG142 DPDT 80 Ohm Differentially Driven JFET Switch...............................
DG143 SPDT 80 Ohm Differentially Driven JFET Switch...............................
DG144 SPDT 30 Ohm Differentially Driven JFET Switch...............................
DG145 DPDT 10 Ohm Differentially Driven JFET Switch...............................
DG146 SPDT 10 Ohm Differentially Driven JFET Switch...............................
DG151 Dual SPST 15 Ohm JFET Analog Switch......................................
DG152 Dual SPST 50 Ohm JFET Analog Switch......................................
DG153 Dual DPST 15 Ohm JFET Analog Switch.....................................
DG154 Dual DPST 50 Ohm JFET Analog Switch.....................................
DG161 SPDT 15 Ohm Differentially Driven JFET Switch...............................
DG162 SPDT 50 Ohm Differentially Driven JFET Switch...............................
DG163 DPDT 15 Ohm Differentially Driven JFET Switch...............................
DG164 DPDT 50 Ohm Differentially Driven JFET Switch...............................
DG180 Dual SPST 10 Ohm High-Speed Driver With JFET Switch.......................
DG181 Dual SPST 30 Ohm High-Speed Driver With JFET Switch.......................
DG182 Dual SPST 75 Ohm High-Speed Driver With JFET Switch.......................
DG183 Dual DPST 10 Ohm High-Speed Driver With JFET Switch.......................
DG184 Dual DPST 30 Ohm High-Speed Driver With JFET Switch.......................
DG185 Dual DPST 75 Ohm High-Speed Driver With JFET Switch.......................
DG186 SPDT 10 Ohm High-Speed Driver With JFET Switch...........................
DG187 SPDT 30 Ohm High-Speed Driver With JFET Switch...........................
DG188 SPDT 75 Ohm High-Speed Driver With JFET Switch...........................
DG189 Dual SPDT 10 Ohm High-Speed Driver With JFET Switch.......................
DG190 Dual SPDT 30 Ohm High-Speed Driver With JFET Switch.......................
DG191 Dual SPDT 75 Ohm High-Speed Driver With JFET Switch. . . . . . . . . . . . . . . . . . . . . . .
DG200 Dual SPST CMOS Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xv

10-71
10-71
10-71
10-71
6-1
4-1
4-1
4-8
4-1
4-1
4-13
4-18
3-1
3-1
3-1
8-1
8-1
8-5
8-7
8-7
8-11
8-11
8-11
8-11
8-17
8-11
8-11
8-17
8-17
8-17
8-17
8-17
8-11
8-11
8-11
8-11
8-17
8-17
8-17
8-17
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-28

Alphanumeric Index

(Continued)

DG201 Quad SPST CMOS Analog Switch ........................................... 8-32
DG201 A Quad Monolithic SPST CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
DG202 Quad Monolithic SPST CMOS Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
DG211 SPST 4-Channel Analog Switch ............................................. 8-41
DG212 SPST 4-Channel Analog Switch ............................................. 8-41
DG300A TTL Compatible CMOS Analog Switches .................................... 8-44
DG301 A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44
DG302A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44
DG303A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44
DGM181 Dual SPST 50 Ohm High-Speed CMOS Analog Switch........................
8-49
DGM182 Dual SPST 50175 Ohm High-Speed CMOS Analog Switch....................
8-49
DGM184 Dual DPST 50 Ohm High-Speed CMOS Analog Switch.......................
8-49
DGM185 Dual DPST 50175 Ohm High-Speed CMOS Analog Switch....................
8-49
DGM190 Dual SPOT 50 Ohm High-Speed CMOS Analog Switch ....................... 8-49
DGM191 Dual SPOT 50175 Ohm High-Speed CMOS Analog Switch .................... 8-49
EVK-128 Data Conversion and FIR Filtering System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-19
ICH85001 A Ultra Low Input-Bias Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1
ICL232 +5 Volt Powered Dual RS-232 Transmitter/Receiver .......................... 11-36
ICL7104/1CL8052 12/14/16-Bit /lP-Compatible 2-Chip AID Converter.................
3-19
ICL7104/1CL8068 12/14/16-Bit /l-P-Compatible 2-Chip AID Converter.................
3-19
ICL71063 %-Digit LCD Single-Chip AID Converter..................................
2-1
ICL71073 %-Digit LED Single-Chip AID Converter...................................
2-1
ICL7109 12-Bit /l-P-Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
ICL7112 12-Bit High-Speed CMOS /l-P-Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . 3-58
ICL711514-Bit High-Speed CMOS /l-P-Compatible AID Converter.....................
3-60
ICL71163 %-Digit with Display Hold Single-Chip AID Converter.......................
2-13
ICL7117 3 %-Digit with Display Hold Single-Chip AID Converter. . . . . . . . . . . . . . . . . . . . . . . 2-13
ICL7121 16-Bit Multiplying Microprocessor-Compatible 01 A Converter ..................
4-25
ICL71263 %-Digit Low-Power Single-Chip AID Converter............................
2-24
ICL71294 % Digit LCD Single-Chip AID Converter...................................
2-35
ICL7134 14-Bit Multiplying /l-P-Compatible 01 A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
ICL7135 4 %-Digit BCD Output AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74
ICL71363 %-Digit LCD Low Power AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
ICL7137 3 %-Digit LED Low Power Single-Chip AID Converter. . . . . . . . . . . . . . . . . . . . . . . . 2-58
ICL7139 3%-Digit Autoranging Multimeter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
ICL7149 Low Cost 3%-Digit Autoranging Multimeter .................................. 2-81
ICL7182 101 Segment LCD Bargraph AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-95
ICL7600 Commutating Auto-Zero (CAZ) Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . .
7-7
ICL7601 Commutating Auto-Zero (CAZ) Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . .
7-7
ICL7605 Commutating Auto-Zero (CAZ) Instrumentation Amplifier......................
7-19
ICL7606 Commutating Auto-Zero (CAD) Instrumentation Amplifier......................
7-19
ICL7650 Chopper-Stabilized Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46
ICL7650S Super Chopper-Stabilized Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54
ICL7652 Chopper-Stabilized Low-Noise Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . 7-64
ICL7652S Super Chopper-Stabilized Low-Noise Operational Amplifier. . . . . . . . . . . . . . . . . . . 7-72
ICL7660 CMOS Voltage Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
ICL7660S Super Voltage Converter................................................. 5-10
ICL7662 CMOS Voltage Converter.................................................. 5-20
ICL7663 CMOS Programmable Micropower Positive Voltage Regulator..................
5-28
ICL7663S CMOS Programmable Micropower Positive Voltage Regulator ................
5-37
ICL7665 Micropower Under/Over Voltage Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5·44
ICL7665S CMOS Micropower Over/Under Voltage Detector...........................
5-53
ICL7667 Dual Power MOSFET Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63
xvi

Alphanumeric Index

(Continued)

ICL7673 Automatic Battery Back-up Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7675 Switched-Mode Power Supply Controller Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7676 Switched-Mode Power Supply Controller Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7677 Power Fail Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7680 + 5V to ± 15V Voltage Converter/Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICL76XX Series Low Power CMOS Operational Amplifiers.............................
ICL8007 JFET Input Operational Amplifier ...........................................
ICL8013 Four Quadrant Analog Multiplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8021 Low Power Bipolar Operational Amplifier ....................................
ICL8023 Triple Low Power Bipolar Operational Amplifier...............................
ICL8038 Precision Waveform GeneratorlVoltage Controlled Oscillator. . . . . . . . . . . . . . . . . .
ICL8043 Dual JFET Input Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8048 Logarithmic Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8049 Antilog Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8063 Power Transistor Driver/Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8069 Low Voltage Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8211 Programmable Voltage Detector............................................
ICL8212 Programmable Voltage Detector....................... .....................
ICM7170 fA-P-Compatible Real-Time Clock...........................................
ICM7207 / A CMOS Timebase Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7208 7-Digit LED Display Counter...............................................
ICM7209 Timebase Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7211 4-Digit LCD/LED Display Driver............................................
ICM7212 4-Digit LCD/LED Display Driver............................................
ICM7215 6-Digit LED Display 4-Function Stopwatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7216A 8-Digit Multi-Function Frequency Counter/Timer...........................
ICM7216B 8-Digit Multi-Function Frequency Counter/Timer...........................
ICM7216C 8-Digit Frequency Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7216D 8-Digit Frequency Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7217 4-Digit LED Display Programmable Up/Down Counter. . . . . . . . . . . . . . . . . . . . . . ..
ICM7218 8-Digit LED Multiplexed Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM72244 %-Digit LCD/LED Display Counter.......................................
ICM72254 %-Digit LCD/LED Display Counter.......................................
ICM7226A1B 8-Digit Multi-Function Frequency Counter/Timer.........................
ICM7227 4-Digit LED Display Programmable Up/Down Counter. . . . . . . . . . . . . . . . . . . . . . ..
ICM7228 8-Digit LED Multiplexed Display Driver . . .. .. . .. .. . . .. . . . . . . . . . . . . . . . . . . . . . ..
ICM7231 Numeric Triplexed LCD Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7232 Numeric Triplexed LCD Display Driver ......................................
ICM7233 Alphanumeric Triplexed LCD Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM72364 %-Digit CounterlVacuum Fluorescent Display Driver.......................
ICM7240 Programmable Timer .....................................................
ICM7242 Long-Range Fixed Timer ..................................................
ICM7243 8-Character LED fA-P-Compatible Display Driver .............................
ICM7249 5%-Digit LCD fA--Power Event/Hour Meter ..................................
ICM7250 Programmable Timer .....................................................
ICM7555 General Purpose Timer ...................................................
ICM7556 Dual General Purpose Timer ...............................................
ID100 Dual Low Leakage Diode............... .....................................
ID101 Dual Low Leakage Diode ....................................................
IH311 High Speed SPST 4-Channel Analog Switch...................................
IH312 High Speed SPST 4-Channel Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH401 QUAD Varafet Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH401 A QUAD Varafet Analog Switch ...............................................
xvii

5-71
5-79
5-79
5-89
5-101
7-31
7-82
6-12
7-86
7-86
6-21
7-91
6-30
6-30
7-99
6-39
5-103
5-103
14-1
14-14
14-19
14-26
13-1
13-1
14-29
14-36
14-36
14-36
14-36
14-54
13-12
14-72
14-72
14-80
14-54
13-23
13-36
13-36
13-36
14-93
14-98
14-108
13-55
14-114
14-98
14-123
14-123
10-73
10-73
8-54
8-54
8-59
8-59

Alphanumeric Index

(Continued)

IH5009 Quad 100 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5010 Quad 150 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5011 Quad 100 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5012 Quad 150 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5013 Triple 100 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5014 Triple 150 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5015 Triple 100 Ohm Virtual Groung Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5016 Triple 150 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5017 Dual 100 Ohm Virtual Ground Analog Switch..................................
IH5018 Dual 150 Ohm Virtual Ground Analog Switch..................................
IH5019 Dual 100 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5020 Dual 150 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5021 Single 100 Ohm Virtual Ground Analog Switch ................................
IH5022 Single 150 Ohm Virtual Ground Analog Switch ................................
IH5023 Single 100 Ohm Virtual Ground Analog Switch ................................
IH5024 Single 150 Ohm Virtual Ground Analog Switch ................................
IH5040 SPST 75 Ohm High-Level CMOS Analog Switch...............................
IH5041 Dual SPST 75 Ohm High-Level CMOS Analog Switch..........................
IH5042 SPDT 75 Ohm High-Level CMOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5043 Dual SPDT 75 Ohm High-Level CMOS Analog Switch..........................
IH5044 DPST 75 Ohm High-Level CMOS Analog Switch...............................
IH5045 Dual DPST 75 Ohm High-Level CMOS Analog Switch..........................
IH5046 DPDT 75 Ohm High-Level CMOS Analog Switch...............................
IH5047 4PST 75 Ohm High-Level CMOS Analog Switch...............................
IH5048 Dual SPST 35 Ohm High-Level CMOS Analog Switch..........................
IH5049 Dual DPST 35 Ohm High-Level CMOS Analog Switch..........................
IH5050 SPDT 35 Ohm High-Level CMOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5051 Dual SPDT 35 Ohm High-Level CMOS Analog Switch..........................
IH5052 QUAD CMOS Analog Switch........... .....................................
IH5053 QUAD CMOS Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5108 8-Channel Fault Protected Analog Multiplexer ..... :...........................
IH5116 16-Channel Fault Protected Analog Multiplexer................................
IH5140 SPST High-Level CMOS Analog Switch.......................................
IH5141 Dual SPST High-Level CMOS Analog Switch..................................
IH5142 SPDT High-Level CMOS Analog Switch......................................
IH5143 Dual SPDT High-Level CMOS Analog Switch..................................
IH5144 DPST High-Level CMOS Analog Switch......................................
IH5145 Dual DPST High-Level CMOS Analog Switch..................................
IH5148 Dual SPST High-Level CMOS Analog Switch..................................
IH5149 Dual DPST High-Level CMOS Analog Switch.................... ..............
IH5150 SPDT High-Level CMOS Analog Switch ......................................
IH5151 Dual SPDT High-Level CMOS Analog Switch ..................................
IH5208 4-Channel Differential Fault Protected Analog Multiplexer. . . . . . . . . . . . . . . . . . . . . .
IH5216 8-Channel Differential Fault Protected Analog Multiplexer......................
IH5341 Dual SPST CMOS RFlVideo Switch ..........................................
IH5352 QUAD SPST CMOS RFlVideo Switch ........................................
IH6108 8-Channel CMOS Analog Multiplexer........................................
IH6116 16-Channel CMOS Analog Multiplexer.......................................
IH6201 Dual CMOS DriverlVoltage Translator .............................. , . . . . . . . . .
IH6208 4-Channel Differential CMOS Analog Multiplexer ... . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH6216 8-Channel Differential CMOS Analog Multiplexer..............................
IH9108 8-Channel High-Voltage Multiplier with Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IM2110 256 x 12 Color Lookup Table and DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xviii

8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-72
8-72
8-72
8-72
8-72
8-72
8-72
8-72
8-81
8-81
8-81
8-81
8-86
8-86
9-1
9-10
8-92
8-92
8-92
8-92
8-92
8-92
8-103
8-103
8-103
8-103
9-14
9-23
8-111
8-117
9-27
9-33
9-40
9-44
9-50
9-56
4-46

Alphanumeric Index

(Continued)

IM26C91 Universal Asynchronous Receiver/Transmitter (UART) .......................
IM29C128 Finite Impulse Response Filter Controller..................................
IM29C510 CMOS 16 x 16 Bit, Multiplier/Accumulator.................................
IM4702/4712 Baud Rate Generator .................................................
IM6402 Universal Asynchronous Receiver Transmitter (UART) ...................... ...
IM6403 Universal Asynchronous Receiver Transmitter (UART) .........................
IT100 P-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT101 P-Channel JFET Switch ......................................................
IT120 Dual NPN General Purpose Amplifier..........................................
IT120A Dual NPN General Purpose Amplifier.........................................
IT121 Dual NPN General Purpose Amplifier..........................................
IT122 Dual NPN General Purpose Amplifier..........................................
IT126 Monolithic Dual NPN General Purpose Amplifier................................
IT127 Monolithic Dual NPN General Purpose Amplifier.................. ..............
IT128 Monolithic Dual NPN General Purpose Amplifier................................
IT129 Monolithic Dual NPN General Purpose Amplifier................................
IT130 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT130A Monolithic Dual PNP General Purpose Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT131 Monolithic Dual PNP General Purpose Amplifier.................................
IT132 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT136 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT137 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT138 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT139 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT1700 P-Channel Enhancement Mode MOSFET General Purpose Amplifier. . . . . . . . . . . ..
IT1750 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch .....
IT500 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT501 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT502 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT503 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT504 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT505 Monolithic Dual Cascoded N-Channel J FET General Purpose Amplifier. . . . . . . . . . ..
IT5911 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT5912 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITC5911 Dual N-Channel JFET High Frequency Amplifier .............................
ITC5912 Dual N-Channel JFET High Frequency Amplifier.............................
ITE4091 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITE4092 N-Channel JFET Switch...................................................
ITE4093 N-Channel JFET Switch...................................................
ITE4391 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITE4392 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITE4393 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITE4416 N-Channel JFET High Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
J105 N-Channel JFET Switch ......................................................
J106 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
J107 N-Channel JFET Switch.................................. ....................
J108 N-Channel JFET Switch ......................................................
J109 N-Channel JFET Switch......................................................
J110 N-Channel JFET Switch........................................ ..............
J111 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
J112 N-Channel JFET Switch......................................................
J113 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
J174 P-Channel JFET Switch ......................................................
xix

11-1
12-1
12-7
11-19
11-26
11-26
10-75
10-75
10-76
10-76
10-76
10-76
10-78
10-78
10-78
10-78
10-80
10-80
10-80
10-80
10-82
10-82
10-82
10-82
10-87
10-88
10-84
10-84
10-84
10-84
10-84
10-84
10-58
10-58
10-58
10-58
10-19
10-19
10-19
10-26
10-26
10-26
10-28
10-89
10-89
10-89
10-90
10-90
10-90
10-91
10-91
10-91
10-92

Alphanumeric Index

(Continued)

J175 P-Channel JFET Switch...................................................... 10-92
J176 P-Channel JFET Switch...................................................... 10-92
J177 P-Channel JFET Switch...................................................... 10-92
J201 N-Channel JFET General Purpose Amplifier.................................... 10-94
J202 N-Channel JFET General Purpose Amplifier.................................... 10-94
J203 N-Channel JFET General Purpose Amplifier.................................... 10-94
J204 N-Channel JFET General Purpose Amplifier.................................... 10-94
J308 N-Channel JFET High Frequency Amplifier..................................... 10-95
J309 N-Channel JFET High Frequency Amplifier .......................... ;.......... 10-95
J310 N-Channel JFET High Frequency Amplifier..................................... 10-95
LM114/H Monolithic Dual NPN General Purpose Amplifier ............................. 10-97
LM 114A1 AH Monolithic Dual NPN General Purpose Amplifier . . . . . . . . . . . . . . . . . . . . . . . . .. 10-97
LM4250 Programmable Operational Amplifier........................................ 7-108
M116 Diode Protected N-Channel Enhancement Mode MOSFET General Purpose
Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-99
MM450 Dual Differential High Voltage Analog Switch.................................. 8-122
MM451 Four Channel High Voltage Multiplexer....................................... 8-122
MM452 Quad SPST High Voltage Analog Switch ..................................... 8-122·
MM455 Three SPST High Voltage Analog Switch..................................... 8-122
MM550 Dual Differential High Voltage Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-122
MM551 Four Channel High Voltage Multiplexer....................................... 8-122
MM552 Quad SPST High Voltage Analog Switch ..................................... 8-122
MM555 Three SPST High Voltage Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-122
U1897 N-Channel JFET Switch ..................................................... 10-110
U1898 N-Channel JFET Switch ..................................................... 10-110
U1899 N-Channel JFET Switch ..................................................... 10-110
U200 N-Channel JFET Switch ...................................................... 10-100
U201 N-Channel JFET Switch ..........................•........................... 10-100
U202 N-Channel JFET Switch ...................................................... 10-100
U231 Dual N-Channel JFET General Purpose Amplifier ............................... 10-101
U232 Dual N-Channel JFET General Purpose Amplifier ............................... 10-101
U233 Dual N-Channel JFET General Purpose Amplifier ............................... 10-101
U234 Dual N-Channel JFET General Purpose Amplifier ............................... 10-101
U235 Dual N-Channel JFET General Purpose Amplifier ............................... 10-101
U257 Dual N-Channel JFET High Frequency Amplifier ................................ 10-103
U304 P-Channel JFET Switch ...................................................... 10-104
U305 P-Channel JFET Switch ...................................................... 10-104
U306 P-Channel JFET Switch ...•.................................................. 10-104
U308 N-Channel JFET High Frequency Amplifier ..................................... 10-106
U309 N-Channel JFET High Frequency Amplifier ..................................... 10-106
U310 N-Channel JFET High Frequency Amplifier ..................................... 10-106
U401 Dual N-Channel JFET Switch ................................................. 10-108
U402 Dual N-Channel JFET Switch ................................................. 10-108
U403 Dual N-Channel JFET Switch ................................................. 10-108
U404 Dual N-Channel JFET Switch ................................................. 10-108
U405 Dual N-Channel JFET Switch ................................................. 10-108
U406 Dual N-Channel JFET Switch ................................................. 10-108
VCR 11 N Voltage Controlled Resistors ...................................~ ............ 10-115
VCR2N Voltage Controlled Resistors ................................................ 10-112
VCR3P Voltage Controlled Resistors ................................................ 10-112
VCR4N Voltage Controlled Resistors ................................................. 10-112
VCR5P Voltage Controlled Resistors ................................................ 10-112
VCR7N Voltage Controlled Resistors ................................................ 10-112
xx

408-996-5000
TWX: 910-338-2014

10600 Ridgeview Court, Cupertino, CA 95014

ALPHANUMERIC CROSS REFERENCE
ALTERNATE
SOURCE PRODUCT

100S
lOOU

INTERSIL
EQUIVALENT

2N5458
2N3684

ALTERNATE
SOURCE PRODUCT

2N2606
2N2607

103M

2N5686
2N5457
2N5457

2N2608
2N2609
2N2639

103S

2N5459

104M

2N5458

105M

2N5459

lO5U

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT
2N3332
2N3333
2N3334

2N2607
2N2607
2N2608

INTERSIL
EQUIVALENT

2N5268
ITI32

2N2609
iTI20

2N3335

ITl32
ITl32

2N3336

lTl32

2N2640
2N2641

ITI22
ITI22

2N3347

ITl3!

2N3348

2N2642
2N2643

106M

2N5485

2N2644

lTI20
ITI22
ITI22

2N3349

2N4340

ITI3B
1T139
tTl3!
ITl3B

107M
IIOU
120U

2N5485

2N2652

2N368S

2N2652A
2N2720

1T120
ITi20
ITI20
1T122
tTl 20

2N3352
2N3365

In39

102M

102S

12SU

1277A
1278A
1279A
12SOA

2N3686
2N4339
2N3822

2N2721
2N2722

2N3821
2N3821

2N2802
2N2803

2N4224

2N2804

2N3350
2N3351

2N3815
2N3816
2N3816A
2N3817
2N3817A

INTERSIL
EQUIVALENT
ITI32
tTI3C
ITl30A
tTI30
ITI30A

2N3822

2N5484
2N2608
2N3821
2N3822

2N3823

lN3823

2N3819
2N3820
2N3821

2N3824
2N3907
2N3908
2N3909

2N3368

ITl39
2N4340
2N4338
2N4338
2N4341

2N3909A

2N2609
2N2609

2N3369
2N3370
2N3376

2N4339
2N4338
2N2608

2N3921
2N3922
2N3949

2N3921
2N3922
ITI32

2N3366
2N3367

ITI39
1T139

ALTERNATE
SOURCE PRODUCT

2N3824

ITI20
ITI20

m~~

~~~~~~

~~~~g~

:n~~

~~~~~

~~~~gg

~~~~~~

~~~~54

1283A
1284A

2N4340
2N4222
2N3821

2N2807
2N2841
2N2842

ITI39
2N2607
2N2607

2N3382
2N3384
2N3386

2N3994
2N3993
2N5114

2N3954A
2N3955
2N3955A

2N3954A
2N3955
2N3955A

g~~A

~~;~~7

~~~~:~

~~~~g~

~~~:n

:m~

~~~m

~~~m

1325A

2N4222
2N4339
2N4224

2N2903

135U
14T

2N2903A
2N2910

ITI22
ITI20
ITI22

2N3411
2N3423
2N3424

ITI22
ITI22

2N3966
2N3967
2N3967A

2N4416
2N4221
2N4221

m~

~~!;~

~~m~

I~m

i~~ji

~Jti41

~~~~~~A

~~~~~~

1825
1835
1975

2N4391
2N3823
2N4338

2N2915

2N3437
2N3438
2N3452

2N4340
2N4338
2N4220

2N3969
2N3969A
2N3970

2N3686
2N3686
2N3970

l~g~

~~:~:o

~~~~W

tTI20
tTI20
ITI20
ITI20
TI22

~~~!~~

~~m~

~~m~

~~~m

2000M

2N3823

2N2918
2N2919
2N2919A

tTI22
ITI20
tTI20

2N3455
2N34S6
2N3457

2N4340
2N4338
2N4338

2N3993
2N3993A
2N3994

2N3993
2N3993
2N3994

1285A

2N2915A
2N2916

1T122

2aOlM

2N3823

200S

2N4392

~g?~

~~~~~1

~~~~~gA

~~~~~g

~~~!~g

~~:~;~

~~~66~A

FT~~~94

2025

2N4392
2N3821
2N3821

2N2936
2N2937
2N2972

ITI20
ITI20
ITI22

2N3460
2N3513
2N3514

2N4338
ITI22
tTI22

2N4010
2N4011
2N4015

ITI32
ITI32
ITI39

203S
2045

~g~g~

~~m~

~~~m

'mil

~~m~

:~lg

~~121~

::n~~

2080A
2a8lA
2093M

2N3955A

2N2975

2N3955A

2N2976

2N3517
2N3S21

2N3687

2N2977

ITI20
ITI20
ITI20

2N3522

2N4018
2N4019
2N4020

ITl39
tT139
tTI39

~g~~~

~~~~g~

~~~~~g

:mg

ITl22
tTI22
tTI22

~~m~

~~~~g~

~~12g

:m~

2098A
2099A
2IOU
2130U

2N3954
2N3955A

2N29SO
2N2981

2N4416

2N2982

ITI21
ITI22
ITI22

2N3578
2N3587
2N3608

2N2608
ITI22
3NI72

2N4023
2N4024
2N4025

tTl37
ITl37
ITl37

~~~!~~

~~~g:~

:m~

~~~~~~

~T~i~84

~~:g~~

~~ml

2134U
2136U
2138U

2N3956
2N3957

2N3045
2N3046
2N3047

ITI22
ITI21
ITI22

2N3684A

2N3684
2N3685
2N3685

2N4039
2N4065
2N4066

2N4351
3N163
3Nl66

m~~

~~~~~g

~~~g!g

:m~

~~~~g~A

~~~~g~

~~:g~;

~~1~~4

2148U
2149U

2N3958
2N3958
2N3954

ITl39
tTI39
ITl29

2N3687

231S

2N3050
2N3051
2N3052

2N3687A
2N3726

2N3687
2N3687
1T131

2N4083
2N4084
2N4085

2N3955
2N3954
2N3955

m~

~~~~~~

~~~g~~

~Jli4o

~~~~~~

~~12~lA

~~12~1

2345

2N3957

2N3067

235S

2N3958

2N3068

2N3729
2N3800

241U

2N4869

2N3069

2N4338
2N4338
2N4341

ITI21
1T132
ITI32

2N409IJAN
2N4091JANTX
2N4091JANTXV

2N409lJAN
2N4091 JANTX
2N4091 JANTXV

~~?~

~~!~1

~~~g~o

~~!m

~~~~g~

:i~~~

~~12~~A

~~12~~

2N2060
2N2060A
2N2060B

ITI20
ITt21
IT121
ITI22
ITI21

2N3084
2N3085
2N3086

2N4339
2N4339

2N4339

2N3804
2N3804A
2N3805

2N4092JAN
2N4092JANTX
2N4092JANTXV

2N4092JAN
2N4092JANTX
2N4092JANTXV

~~!m

~~~~g~A

tTI30
ITl30A
tTl 30
1T130A
ITI22

~~!g~~A

~~!g~~

2N2608

2N3088A
2N3089

2N4339
2N4339
2N4339

2N3807
2N3808
2N3809

ITI22
ITl22
ITI22

2N4093JAN
2N4093JANTX
2N4093JANTXV

2N4093JAN
2N4093JANTX
2N4093JANTXV

2 32

2N2223
2N222 A
2N2386
2N2386A
2N2453

~~~!~~A
2N2480A
2N2497
2N2498
2N2499
2N2500

2N3958

2N2608
ITI22

::nn
tTI21
2N2608

~~~g~~
2N3089A

2N3685A

2N3801

:mg

~~~m

~~~~g~

~~~~lgA

~~~m,

~~!IO~

~~~107

2N3278

2N2607
2N5265
2N5267
2N5268
2N5270

2N3811
2N3811A
2N3812
2N3813
2N3814

2N3811
2N3811A
ITI32
ITI32
ITI32

2N4117A
2N4118
2N4118A
2N4119
2N4119A

2N4117A
2N4118
2N4118A
2N4119
2N4119A

2N2608

2N3328
2N3329

2N2609
2N2608

2N3331

··CONSULT FACTORY

2N3685

2N3330

XXI

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

2N4120
2N4139

3N163

2N5021

2N3822

2N4220
2N4220A
2N4221

2N4220
2N4220
2N4221

2N5033
2NS045
2N5046
2N5047

2N4222

2N4221
2N4222

2N4222A
2N4223
2N4224

2N4222
2N4223
2N4224

2N4267
2N4268
2N4302
2N4303

3N163

2N4304

2N4221A

2N5078
2N5090
2N5103

ALTERNATE

INTERSIL

EQUIVALENT
2N2607
2N5460
2N5453

SOURCE PRODUCT

INTERSIL

EQUIVALENT

INTERSIL
EQUIVALENT

2N6485

2N6485

2N6502
2N6503
2N6550
2N6568

ITI22
1T122
2N4868A
2N5432

2SC294
2SJll

2N5S18
2N5519

2N5515
2N5516
2N5517
2NS518
2N5519

1T122
2N2607
2N2607
2N5270
2N2607

2N5520
2NS521
2N5S22
2N5523
2N5524

2NS520
2N5S21
2N5522
2N5523
2N5524

2SJ16
25J47

2N5475
2N5476
2N5484
2N5485
2N5486

2N5265
2N5266

2N5397
ITI22
2N4416

2N5515

2N5454
2N5454

ALTERNATE
SOURCE PRODUCT

2N5516

2N5517

2N5484
2NS485
2N5486

25J12
2SJ13
2SJ15

2N5104

2N4416

2N5105

2N4416
2NS114
2NSl14JAN

2N5458

2NS114
2NSl14JAN
2N5114JANTX
2N5114JANTXV
2N5115

2N5115

2N4338
2N4339
2N4340
2N4341
2N4342

2N4338
2N4339
2N4340
2N4341
2N5461

2N5l15JAN
2N511SJANTX
2N5115JANTXV
2N5116
2NS116JAN

2N5l15JAN
2N5115JANTX
2N5115JANTXV
2N5116
2N5116JAN

2N4343
2N4351
2N4352
2N4353
2N4360

2N5462
2N4351
3N163
3Nl72
2N5460

2N5116JANTX
2N5116JANTXV
2N5117
2N5118
2N5119

2N5116JANTX
2N5116JANTXV
2N5117
2N5118
2N5119

2N5120
2N5121
2N5122
2N5123
2N5124

ITl31
ITl32
ITl32
ITl31
ITl32

2N5563
2N5592

U404

2N3822

2N5593
2N5594
2N5638

2N3822
2N3822
2N5638

2SK178

2N5125
2NS158
2N5159

ITl32
2NS434
2NS433

2N5639

2N5639

2N5640
2N5647

2N5163

2N3822

2N5648

2N5640
2N4117A
2N4117A
2N4117A

2SK180
2SK19
2SK23
2SK30

2SK32

ITE4416
2NS459
2N5458
2N3822

2N5638

2SK33

2N5397

2SK34

2N3822
2N5484
2N5459

3Nl6!
2N4302
2N5459

2N5114JANTX
2N5114JANTXV

2N5546

2N5545

2N3954
2N3955Ao

2N5547

2N3955

2N5549
2N5555
2N5556

2N5557
2N5558
2N5561
2N5562

2N4381

2N2609

2N4382

2N5115

2N4391
2N4393

2N4391
2N4392
2N4393

2N4416
2N4416A
2N4417
2N4445
2N4446

2N4416
2N4416A
2N4416
2N5432
2N5434

2N5196

2NS196

2N5649

2N4447

2NS197
2N5198
2N5199
2N5245
2N5246

2N5197

2N5653
2N5654

2N4856
2N4856A
2N4856JAN

2N5432
2N5434
2N4856
2N4856A
2N4856JAN

2N4856JANTX
2N48S6JANTXV
2N4857
2N4857A
2N4857JAN

2N4856JANTX
2N4856JANTXV
2N4857
2N48571>
2N4857JAN

2N5247

2N4857 JANTX
2N4857 JANTXV
2N4858
2N4858A
2N4858JAN

2N485 7JANTX
2N4857 JANTXV

2N5257
2N5258

2N5457

2N4858

2N5259

2N5459

2N4858A
2N4858JAN

2N5265
2N5266

2N4858JANTX
2f114858JANTXV

2N4858JANTX
2N4858JANTXV

2N5267

2N4859

2N4859

2N4859A
2N4859JAN

2N4859A
2N4859JAN

2N4859JANTX
2N4859JTXV

2N4392

2N4448

2N5198

2N4093
J310
2N3685
2N3684
2N3684
U401
U402

2SJ48
2SJ49

2SJ50
2SJ78
2SJ79
2SJ80
2SKll

2SK12

......

~~2607

......

2N5457
2N5457

2SK135

....
..

2SK15

2N4868

2SKl7

2.~5484

2SK13
2SK132
2SKl33
2SK134

2SK179
2SK18

2.~5457

..
..

2N3821

2N5668
2N5669
2N5670

2N5639
2N5484
2N5485
2N5486

2N5793
2NS794
2NS795
2N5796

ITl29
ITl29
ITl39
ITl39

2SK48

2N3821

2N5797

2N2608

2SK49

2N5484

2N2608
2N2608
2N2608

2N2607

2N5798
2N5799
2N5800
2N5801

2N2607

2N5802

2N4393

2SK50
2SK54
2SK55
2SK56
2SK61

ITE4416
2N3822
2N3822
2N5459
2N5397

2N2608

2N5803

2N5268
2N5269
2N5270
2N5277

2N2608
2N2609
2N2609
2N4341

2N5843
2N5844
2N5902
2N5903

2N4392
ITl30
ITl30
2N5902
2N5903

2SK65
2SK66
2SK68
2SK72

3GS

J201
2N3821
2N3822
2N5196
2N3821

2N5278

2N4341
2N4220

2N5904

2N5904
2N5905

3N145

3N163

2N5358

3Nl46

3N163

2N5359

2N4220

2N5906

2N5360

2N4221

2N5907

2N5906
2N5907

2N5361

2N4221

2N5908

2N5908

3N147
3Nl48
3N149

3N189

2N4860A
2N4860JAN

2N4859JANTX
2N4859JTXV
2N4860
2N4860A
2N4860JAN

2N4860JANTX
2N4860JTXV

2N4860JANTX
2N4860JTXV

2N5362

2N4222
2N4222

2N5909

2N4861

2N4861

2N4222

2N5912

3N150
3NlSl
3N155

3N163
3N190
3N163

2N4861A
2N486IJAN

2N4861A
2N486IJAN

2N4867A
2N4868A

3N155A

3N163

2N5950

2N5909
2N5911
2N5912
2N5486
2N5486

3N156

3N163

2N486IJANTX
2N4861JANTXV
2N4867
2N4867A
2N4868

2N4861JANTX
2N486IJANTXV
2N4867
2N4867A
2N4868

2N5393
2N5394
2N5395

2N4869A
2N4869A

2N5951
2N5952

2N5486

2N4869A

2N5953

3N163
3N163
3N163

2N4869A
2N5397

2N6085

2N5397

2N5484
1T122
ITl22

3N156A
3N157
3N157A
3N158

2N4868A
2N4869
2N4869A
2N4878
2N4879

2N4868A
2N4869
2N4869A
2N4878
2N4879

2N5398
2N5432

2N5398
2N5432

2N6087
2N6088

2N5433

2N5433

2N6089

2N5434
2N5452

2N5434
2N5452

2N6090
2N6091

2N4880

2N4880

2N5453

2N4937
2N4938

1T131

2N5454

2N6092
2N6441

ITI32
1T132
ITl32

2N5457
2NS458
2N54S9

2N5453
2N5454
2N5457

2N5458

2N6443

2N5459

2N6444

2N5460
2N5461
2N5462

2N5460
2N5461
2N5462

2N6445
2N6446
2N6447

2N5463

2N5463

2N4977

ITl31
1T132
1T122
1T122
2N5433

2N5464

2N5464

2N4978
2N4979
2N5018
2N5019

2N5433
2N4859
2N5018
2N5019

2N5465
2N5471
2N5472
2N5473

2N5465
2N5265
2N5265
2N5265

2N5020

2N2843

2N5474

2N5265

2N4860

2N4939
2N4940
2N4941
2N4942
2N4955

2N4956

"CONSULT FACTORY

2N5248
2N5254
2N5255
2N5256

2N5363
2N5364
2N5391

2N5392

2N5396

2N5199
ITE4416

2N5484
2N5486
2N5486
ITl32
ITl32
ITl30
2N5458

2N5905

2N5911
2N5949

2N6086

2N5484

2SK41
2SK42
2SK43
2SK44

2SK46

3N158A

1T121
1T121
1T122
ITl21
IT121

3N160

1T121
ITl22
1T122
ITl22
1T122

3N166

3N171
3Nl72

2N6448

ITl21
ITl21
1T121
ITl21

2N6451

U310

2N6452
2N6453

2N6454

U310
U310
U310

2N6483
2N6484

2N6483
2N6484

2N6442

XXII

2N4393

2SK37

3N161
3N163
3N164

3N165
3Nl67
3Nl68
3N169
3Nl70

3N173
3N174
3NI7S

2N3822
ITE4092
ITE4416

2N5459

3N189
3N161

3N163
3N163
3N161
3N161
3N163
3N164
3N165
3N166
3Nl61

3N161
3N170

3N170
3Nl71
3Nl72
3N173
3N163

3N170

3NI76

3N170

3Nl77

3N171
3Nl72
3NI72
3Nl72

3NI78

3N179
3N180

ALTERNATE
SOURCE PROOUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

3Nl6!

AD7520SD

3N161
3N161
3N188
3N189

AD7520TD
AD7520UD
AD7521JD
AD7521JN

3N190
3N191
3N207
3N208
3SK22

3N190
3N191
3N190
3N188
2NS486

AD7521KD
AD7521KN
AD7521LD
AD7521LN
AD7521SD

3SK23
3SK28
42T
4360TP
5033TP

2N5397
2N5397
2N4392
2N5462
2N5460

3NlSl
3N182
3N183
3N188
3N189

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

AD7520S0

AH0141D

DG141AP

BFB05

AD7520TD
AD7520UD

AHOl4} 0/883

DG141AP/883B

AH0142CD

DG142BK

AD752IJD

AH0142D
AH0142D/883

DG142AK
DG142AK/8838

BFB06
BF808
BF810
BFa!1

AD7521KD
AD7521KN
AD7521LD
AD7521LN
AD7521SD

AH0143CD

DG143BK

8F81S

AH0143D

DG143AK

BFBIG

AHO 1430/883

BFa17

AH0144CD

DG 143AK/883B
DGl44BK

AH0144D

DG144AK

AD7521TD
AD752lUD
AD7523AD
AD7523BD
AD7523CD

A07521TD
AD752lUD
AD7523AD
AD7523BD
AD7523CD

AH0144D/883

DG144AK/883B

AD7521JN

BF818
BFQ10

~~8g

AH0145CD

OG145BP

AH0145D
AH0145D/883
AH0146CD

DG145AP
DG145AP/883B
DG146BP

BF 13

AD7523JN
AD7523KN
AD7523LN
AD7523SD
AD7523TD

AH0146D

DG146AP
OG146AP/8838

BFQ16
BFQ23

DG151BK
DG 151 AK/883B
DG152BK

AD7523UD
AD7530JD
AD7530JN
AD7530KD

AH0152D
AH0152D/883
AH0153CD
AH0153D

g

BF 14
SF 15

INTERSIL
EQUIVALENT
2N4869
2N4869
2N4868
2N4858
2N48S8
2N4858
2N4858
2N4858
2N4858
U401

U401
U402
U403
U404
U405

BFQ45

U406
IT5912
U403
IT5912
IT5912

OG152AK

2N30S5

AHQ153D/S8a

DG 152AK/883B
DG153BP
DG153AP
DG153AP/883B

21
8FS21A

2N3958
2N3958
2N5199
2N5199

AH0154CD
AH0154D
AH0154D/883
AH0155D
AH0161CD

DG154BK
DG154AK
DG143AK/883B
DG151AK
DG161BP

8FS67

2N3821

BFS67P
BFS68
BFS68P
BFS70

2N3823
2N4416
2N3821

588U
58T
59T
703U
704U

2N4416
2N5457
2N4416
2N4220
2N4220

AD7523JN
AD7523KN
AD7523LN

705U
707U
714U
734EU
734U

2N4224
2N4860
2N3822
2N4416
2N5516

AD7523UO

AD7530KN

75lU
752U
753U
754U
755U

2N434O
2N434O
2N4341
2N4340
2N4341

AD7530LD
AD7530LN
AD7531JD
AD7531JN
AD7531KD

AD7530LD
AD7530LN
AD7531JD
AD7531JN
AD7531KD

756U
A190
A191
A192
A193

2N4340
ITE4416
ITE4416
2N4416
2N5484

AD7531KN

AD7531KN

AD7531LO
AD7531LN
AD7533AD
AD7533BD

AD7531LD
AD7531LN
AD7533AD
AD7533BD

AHOIGID
AHO 1610/883

A194
A195
A196
A197
A198

2N5484
2N5484

AD7533CD
AD7533JN
AD7533KN
AD7533LN
AD7533SD

AD7533CD
AD7533JN
AD7533KN
AD7533LN
AD7533SD
AD7533TD

2N5484
2N5484
2N4416
2N4341

AD7533TD
AD7533UD
AD7541AD
AD7541BD
AD7541JN

AD7533UD
AD7541AD
AD7541BD
AD7541JN

AH5009CN
AH5010CN
AH5012CN
AH5013CN

BFW12

2N5019
2N3823
2N3822
2N4416

AD7541KN
AD7541SD
AD7541TD
AD810
AD8ll

AD7541KN

AH5014CN
AH5015CN

IH5014CPD

BFW13

2N4867

IH5015CPE

AH5016CN
ALD555

IH5016CPE
ICM7555

BFW39
BFW39A

AD3954A

2N5460
2N5461
2N5462
2N3954
2N3954A

ALD556

ICM7556

BFW55

AD3955
AD3956
AD3958
AD589
AD590

2N3955
2N3956
2N3958
ICL8069
AD590

AD812
AD813
AD814
AD815
AD816

AM5011CN
BC264
BC264A
BC264B
BC264C

IH5011CPE

BFW56
BFW61

AD5905
AD5906
AD5907
AD5908
AD5909

2N5905
2N5906
2N5907
2N5908
2N5909

AD818
AD820
AD821
AD822
AD830

BC264D

AD7506/COM/CHIPS
AD7506/MIUCHIPS
AD7506JD
AD7506JD/883B
AD7506JN

IH6116C/D
IH6116M/D
IH6ll6CJI
IHS116CJI/883B.

AD7506KD
AD7506KD/883B
AD7506KN
AD7506SD
AD7506SD/883B

IH6116CJI

A199
A5T3821
A5T3822
A5T3823
A5T3824
A5T5460
A5T5461
A5T5462
AD3954

ITE4416

ITE4391
ITE4392
"ITE4393

IH6116CPI
IH6116CJI/883B

IH6116CPI
IH6116MJI

IH6116MJ1/883B

AD7506TD

AD7523SD

AD7523TD
AD7530JD
AD7530JN
AD7530KD
AD7530KN

AD7541SD
AD7541TD
2N4878
2N4878
2N4878
2N4878
1T124

1T124
1T120A
1T140
1T132

AHO 1460/883
AH0151CD

AH0151 0/883
AH0152CD

~~8~~

2NS459

DG161AP

BFS71

2N3822

DG161AP/883B
DG162BK
DG162AK
DG 162AK/883B

BFS72
BFS73
BFS74
BFS75

2N3823
2N3821
2N4856
2N4857

AH0183CD
AH0163D
AHO 1630/883
AH0164CD
AH0164D

DG163BP
DG163AP
DG163AP/883B

BFS76
BFsn
BFS78
BFS79
BFS80

AHOI64D/8S3

DG 16AAK/883B

AH0162CD
AH0162D
AH0162D/883B

DG164BK

DG164AK
IH5009CPD
IH5010CPD
IH5012CPE
IH5013CPD

2N5458
2N5457
2N5458

BFTlO
BFT11

BFW10
BFWll

BFW54

2N4858

2N4859
2N4860

2N4861
2N4416A
2N5397

IT129

1T120
2N3822
2N3822
2N4860

BFXll
BFX15

2N4224
1T132
1T122

2N5458

BFX36

1Tl31

BFX70

IT122

BFX71
BFX72

1Tl22

BFX78

1T130A

BCYS7
BCY88

1T130A

BCY89

2N4416
1T121
1T122
1T122

2N5520

BF244

2N5486

BFX82

2N5397
2N5019

AD831
AD832
AD833
AD833A
AD835

2N5521

BF244A
BF244B

2N5484

BFX83

2N5019

2N54S5

2N5523
2N5524
2N3954

BF244C

2N5486
2N5486

BFX99
BFY20

ITl20A
IT122
ITl22

AD836
AD837
AD838
AD839
AD840

2N3955
2N3955
2N3956
2N3957
2N5520

BF245B
BF245C

BF246
BF246A
BF246B
BF246C
BF247

2N5638
2N4091

BF247A
BF247B

2N4091

2N5522

IH6ll6MJI
AD7506TD/883B
IH6ll6MJI/883B
AD7507/COM/CHIPS IH6216C/D

AD841

2N5521

AD842

AD7507/MIL/CHIP$

BF245

BF245A

1T122

2N4416

8FY81
BFY82

1T122

2N4416

BFY83

1Tl22

2N4416

BFY84

ITl22

2N5485

BFY85

1Tl22

2N5639

BFY86
BFY91

1Tl22

2N5638

BFY92

1T122
1T122
ITl22
2N4416

IH6216M/D

AH0126D/883

AD7507JD

IH6216CJI

AH0129CD

2N5523
DG126AP
DG126AP/883B
DG129BK

BF247C

2N4091

BN209
BSV22
BSV78
BSV79

AD7507 JD/883B
AD7507JN
AD7507KD
AD7507KD/883B

IH6216CJI/883B
IH6216CPI
IH6216CJI
IH6216CJI/883B

DG129AK
DG 129AK/883B
DG133BK
DG133AK
DG 133AK/883B

BF256

2N5484

BSV80

2N4858A

BF256A
BF2568

2N5484

BSX82

2N4416

C21
cn06
C38

2N3822
2N3821
2N5196

BF320A
BF320B
BF320C

AH0126D

2N4091

AD7507KN

IH6216CPI

AH0129D
AH0129D/883
AH0133CD
AH0133D
AH0133D/883

AD7507SD

AH0134CD
AH0134D

DG134BK

AD7507SD/883B

IH6216M/O
IH6216MJI/8838

AD7507TD
AD7507TD/883B
AD7520JD

IH6216MJI
IH6216MJI/883B
AD7520JD

AH0134D/883
AH0139CD
AH0139D

DG 134AK/883B
DG139BK

BF346

2N5461
2NS462
ITE4392

DG139AK

BF347

J201

AD7520JN
AD7520KD
AD7520KN
AD7520LD
AD7520LN

AD7520JN

AH0139D/883
AH0140CD

DG139AK/883B

BF348

C614

BF800

AH0140D/883

DG140BP
DG140AP
DG140AP/8838

J310
2N4867
2N4867
2N4338

AH0141CD

DG141BP

2N4338

C622

AD7520KO

AD7520KN
AD7520LD
AD7520LN

"CONSULT FACTORY

AH0140D

BF256C
BF320

DG134AK

BF801

BF802
BF804

XXIII

2N4416
2N5461

2N5460

C413N
C610

C611
C612
C613
C615
C620
C621

2N4856A
2N4857A

2N4338
2N5434
2N4392
2N4221

2N4221
2N4221
2N4220
2N4221
2N4220
2N4220
2N4220

ALTERNATE

SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

C623
C624
C625
C650
C651

2N4220
2N4220
2N4220
2N4220
2N4220

D123AL
D123AP

O123AL

DG152AP

OG152AK

D123AK

DG152BP·

DG152BK

D1238P
D123BP
D125AL

D123BK
D123BJ
D125AL

DG153Al

DGlS3AL

DG153AP

OG153AP

DG153BP

C652
C653
C6690
C6691
C6692

2N4220
2N4220
2N4341
2N4341
2N4339

DGl54Al

C673
C674
C680
C680A
C681

2N4341
2N4341
2N4338
2N4338
2N4338

C681A
C682

2N4338

01422

2N4339

D2T2218

2N4869
1Tl29

C682A

2N4339

D2T2218A

ITl29

DG164AL

C683

2N4339

D2T2219

1Tl29

DG164AP

C683A

2N4339

D2T2219A

ITl29

DG164BP

DG164AL
DG164AK
DG164BK

C684

2N4220

DG180AA
DG180AL

DG180AA
DG180AL

DG180AP

DG180AK

DG180BA
DG180SP

DG180BA

D125BP

D125AP
D125BK

D129AL

D129AL

D129AP
DI29BP

D129AK
D129BK

01301
01302

2N4222
2N4220
2N4220
2N4868
2N3822

D125AP

01303
01420
01421

C684A

2N4220

C685

2N4220

D2T2904
D2T2904A
D2T2905

ITl39
ITl39
ITl39

C685A

2N4220

D2T2905A

1Tl39

C80

2N4338

D2T918

ITl29

C81
C84
C85
C91
C92

2N4338

DA102

2N4338
2N4338
2N4858

DA402
DACI020LCD
DAC1020LD

2N6196
2N5196
AD7520LD
AD7520UD

2N4091

DAC1021LCD

AD7520KD

C93
C94
C94E
C95
C95E

2N4393

DAC1021LD

AD7520TD

2N5457

DACI022LCD
DACI022LD
DACl218LCD

AD7520JD

2N5467

2N5459

DAC1218LCN

AD7541LN

DAC1218LCN

AD7541KN
AD7541AD

C98E
CA555
CA556

2N5484
2N3822
2N3822
ICM7555
ICM7556

CC4445
CC4446

2N5432
2N5434

CC697

2N4856

CD22001H

C96E
C97E

CD22015E
CF2386
CF24
CFMl3026
CM600
CM601

2N5457

DAC1219LCD

DG153BP

DG154AL
DG154AK
DG154BK
DG161Al
DG161AP

DGI9IBP
DG200AAA
DG200AAK
DG200AAL
DG200ABA

OGl91BK
DG200AA
DG200AK
DG200AL
DG200BA

DG161BP

DGIGIBP

DG200ABK

DG162AL

DG162AL
DG162AK
DG162BK
DG163AL

DG200ACJ

DG163AP

DG163AP

DG163BP

DG163BP

DG211CJ
DG212CJ
DG381AA
DG381AK

DGIG2BP
DG163AL

DG381AP
DG381BA
DG381BK
DG381BP
DG38lCJ
DG384AK

DG384AP
DG384CJ
DG387AA

DGl81AP
DG181BA
DG181BA
DGl8lBP

DGl81AK
DGM181BA
DGl81BA
DGM181CJ
DGM181BK

DG387BP

DG181BK
DGM182AA
DG182AA
DGMIB2AL

DG390BP

DG182AL

DG390CJ

DGM182AK
DG182AK

DG503

DGl81BP
DG181BP
DG182AA

DGMIBIAK

DAC1220LD
DAC1221LCD
DAC1221LD
DAC1222LCO

AD7521KD
AD7521TD
AD752IJD

DG182AP
DG182AP
DG182BA

DGM182BA

ICMl424C
ICM7051A

DAC1222LD

AD7521SD

DG182BA

DG182BA

DG123AL

DG123AL

DG182BP

DGM182CJ

2N5458
2N3824

DG123AP
DG123BP
OG125Al
DG125AP

DG123AP

DG182BP

DG123BP

DG182BP

DGM182BK
DG182BK

DG125Al
OG125AP

DG183AL
OG183AP

DG125BP

DG125BP

DG183BP

2N4091

DG126AK

DG126AP

2N4091
2N4093
2N4093

DG126AL

DG126AL

DG126BP

DG126BP

DG129AL

DG129AL

DG184AL
DGl84AL
DG184AP
DG184AP

CM642

2N4093

DG129AP

DG129AK

DG184BP

CM643
CM644

2N4092

DG184BP

2N4092

DG129BK
DG133AL

CM645

2N4092

DGl29BP
OG133AL
DG133AP

DGl33AK

DG201AK
DG201CJ

DGM181AA
DG181AA
DGM181AL

DG181AL

DG184BP
DG185AL
DG185AL
DG185AP

2N4092

DG133BP

DG133BK

CM647

2N4091

DG134AL

DG134AL

CM650

2N5432

DG134AK
DG134BK
DG139AL

DG185AP

DG384BK

DG384BP

DG387AK
DG387AP
DG387BA
DG387BK
DG390AK
DG390AP
DG390BK

DGMlS48K
DG184BK

DG5044CK
DG5045AK
DG5045CJ
DG5045CK

IH5044CJE
IH5045MJE
IH5045CPE
IH5045CJE
IH6116MJI

DGM185AL
DG18SAL
DGMl85AK

DG506AAK

DG18SAK
DGM185CJ
DGM185BK
DG185BK
DG186AA

DG506ABK

DG507ACJ

IH6116CJI
IH6116CPI
IH6216MJI
IH6216CJI
IH6216CPI

DG186Al
OG186AP
DG186BA
DG186BP
DG187AA

DG508AAK
DGS08ABK
DG50SACJ
OG509AAK
DG509ABK

IH6108MJE
IH6108CJE
IH6108CPE
IHS208MJE
IH6208CJE

DG187AL
DG187AK
OG187BA
DG187BK
DG188AA

DG509ACJ
OG5140AK
DG5140CJ
DGS140CK
DG5141AK

IH6208CPE
IH5140MJE
IH5140CPE
IH5140CJE
IH5141MJE

DG5141CJ
DG5141CK
DG5142AK
DG5142CJ
OG5142CK

IH5141CPE
IH5141CJE
IH5142MJE
IH5142CPE
IH5142CJE
IH5143MJE
IH5143CPE
IH5143CJE
IH5144MJE
IH5144CPE

2N5433

DG139AP
DGl39BP

DG139AK
DG139BK

DG185BP

2N5433
2N5433

DGl40AL
DG140AP

DG186AL

2N5433

OGl40AL
DGl40AP

CM860

2N486SA

DGl40BP

DGl40BP

DG186BA

CMX740
CP640

2N5432
2N4091

DG141AP

DG141AP

DG187AA

CP643
CP650
CP651
CP652
CP653

2N5434
2N5432

DG141BP

DG141BP

OGl42Al

2N5433
2N5433
2N5433

DG142AP
DG142BP

DGl42AL
DGl42AK
DG142BK

DG187AL
DG187AP

DG143AL

DG143AL

DG188AA

01101

2N3821
2N3821
2N4338
2N3821

DG143AP
DG143BP

DG143AK

DG143BK

DG188AL
DG188AP

DGl44AL

DGl44AL

DG188BA

DG188Al
DG188AK
DG188BA

DG144AP

DGl44AK

DG188BP

DG188BK

01178

2N3821

DG144BP

DGI44BK

DG189AL

OGl89AL

01179
01180
01181
01182
01183

2N4338

DG14SAl

DG5143AK

DG145AP

DG189BP

DG145BP

OG145BP

DG189AP
DG189BP
DG190AL

DG189AP

2N3S22
2N4338
2N4338

DG145AL
DG145AP

OGMl90AL

DG5143CJ
DG5143CK

DG146AL

DG146AL

DG5144AK

DGl46AP

DG146AP

DG190Al
DG190AP

DG190AL

2N4341

DGMl90AK

DG5144CJ

01184
01185
01201
01202
01203

2N4340
2N4339

DG146BP

DG146BP

DG190AP

DG190AK

DG151AL

DG151AL

DGl90BP

DGM190CJ

2N4224
2N3821

DG151AP
DG151BP
DG152AL

DG151AK
DG151BK
DG152AL

DG190BP

DGM190BK
DG190BK
DGM191AL

DG5144CK
OG5145AK
DG5145CJ

01102
01103

01177

2N4220

"CONSULT FACTORY

DGl90BP

DG191AL

XXIV

DGM191AK
DGM191AK
DGM190BK
DGM190BK
DGM190CJ

IH5043MJE
IH5043CPE
IH5043CJE
IH5044MJE
IH5044CPE

CM800
CM856

DGl87BA
DGIS7BP

DGM188AK
DGM188AK
DGM187BA
DGM187BK
DGM187BK

DG5043AK
DG5043CJ
DG5043CK
DGS044AK
DG5044CJ

CM697

DG186BP

DGM185AK
DGM184BK
OGM184BK
DGMl84CJ
DGM188AA

DGMl84AL
DG184AL
DGMl84AK
DG184AK
DGM184CJ

CM653

DG141AL

DGM181BA
DGMl81BK
DGM181BK
DGM181CJ
OGM185AK

IH5041CPE
IH5041CJE
IH5042MJE
IH5042CPE
IH5042CJE

2N5433

DG141AL

DGM182AA
DGMl82AK
DGM182AK

DG5041CJ
DG5041CK
DG5042AK
DG5042CJ
DG5042CK

2N5432

DG186AP

DG212CJ

DG183AP
DG183BP

DG183AL

CM652

DG186AA

DG2llCJ

AD503
IH5040MJE
IH5040CPE
IH5040CJE
IH5041MJE

CM6S1

DGlS5BP

DG201BK

DG5040AK
DG5040CJ
DG5040CK
DG5041AK

DG134AP
DG134BP
OG139AL

DG185BP

DG2QOBK
DG200CJ

DG201ABK
DG201ACJ

DG181AL

DG181AA

CM602
CM603
CM640
CM641

CM646

DG180BK

DGM191CJ
DGM191BK

DG201AAK

DG181AL
DG181AP

DG181AA

DG182AA
DG182AL
DG182AL

2N4092
2N4091

AD7541JN

DG191AL
OGM191AK

DG191AK

AD7521LD
AD7521UD

2N4858

DAC1219LCN
DAC1220LCD

DG191AL
DG191AP

DGl62AP

..>

INTERSIL
EQUIVALENT

DG191AP
DGl91BP
DGI9IBP

DG154AP
DG1548P
OG161AL
DG161AP

AD7520SD
AD7541BD

ALTERNATE
SDURCE PRODUCT

DG506ACJ
DG507AAK
DG507ABK

DG5145CK

IHS144CJE
IH5145MJE
IH5145CPE
IH5145CJE

DN3066A

2N3821

ALTERNATE
SOURCE PRODUCT
ON3067A
ON3068A
DN3069A
DNJ010A
DN3071A

ON3365A
DN3365B
DN3366A
DN3366B
DN3367A

INTERSIL
EQUIVALENT
2N4338
2N4338
2N3822
2N3821

2N4338

ALTERNATE
SOURCE PRODUCT

INTERSIL
EjlUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

E411
E412
E413
E414
E415

IT5911
IT5911
2NS454
2N3956
2N3957

FM3956
FM3957
FM3958
FP4339
FP4340

2N3956

HII-0507A-8

2N3957
IT5911
2N4339
2N4340

Hll·0508·2
HI 1-0508-5
HIl-0508-8
HIl·0508A~2

IH5216MJI/8S3B
IH610BMJE
IH610BCJE
IH6108MJE/8838
IH510BMJE

£420

IT5911
IT5912
J309(X2)
J310(X2)
U401

FT0654A
FT0654B
FT0654C
FT0654D
FT3820

2N5486
2N5486
2N4221
2N4221
2N5460

HII-0508A-5
HII-050SA-8
HI1-0509-2
HI1-0509-5
HI 1·0509·8

IH5108IJE
tH5108MJE/8838
IH6208MJE
IH6208CJE
IH6208MJE/8838

2N4220
2N4091
2N3686
2N4091
2N3687

E421
E430
E431
E5M25

2N5019

HIl-0509A-2

IH5208MJE

2N4093
2N5457

2N5019
aN161
3N163
G1l8Al

HIl-0509A·5

FT703
FT704
G118Al

HIl-0509A-8
HIl-5040-2
HIl-5040-5

IH520BIJE
IH5208MJE/8838
IH5040MJE
IH5040CJE

2N5459
2N5458
2N5432
2N5434
2NS432

G118AP
G123AL
G123AP
GETS4S7
GET54S8

G1l8AK
G123Al
Gl23AK
2NS457
2NS4S8

HIl-S040-8
HIl-5041·2
Hll-S041-5
Hll-S041-8
HI 1-5042-2

IH5040MJE/8838
IH5041MJE
IH5041CJE
IH5041MJE/8838
IH5042MJE

ESM4448
FE0654A
FE0654B
FElOO
FElOOA

2N5434
2N4386
2N5485
2N3821
2N3821

GET54S9
HA2720
HA7807
HA7809
HD43871

2N5459
ICL8021
ITl32
ITl32
ICM70S0H

HI 1-5042·5
HII-5042-8
HI 1-5043-2
HII-5043-5
HI 1-5043-8

IH5042CJE
IH5142MJE/883B
IH5143MJE
IH5143CJE
IH5143MJE/883B

2N4339
2N4220
2N4338
2N4220
2N4338

FE 102
FEl02A
FE104
FE104A
FE1600

2N4119
2N4119
2N4118
2N4118
2N4092

HD43871
HDIGI030
HEP801
HEP802
HEP803

ICM70S0G
3N163
2N3822
2N5484
2N5019

HIl·S044·2
HIl-5044-5
HIl-5044·8
HII-5045·2
HIl-5045·5

IH5144MJE
IH5144CJE
IH5144MJE/883B
IH5145MJE
IH5145CJE

DNX2
DNX3
DNX4
DNX5
DNX6

2N4338
2N4338
2N4869
2N4868
2N4338

FE200
FE202
FE204
FE300
FE302

2N3821
2N3821
2N3821
2N3822
2N3821

HEPF0021
HEPFl035
HEPF2004
HEPF2005
HI0-0201·6

2NS484
J176
2N5484
2N5459
DG201C/D

HIl-S045·8
HIl-5046·2
HII-5046-5
HII-5046-8
HI1-5047·2

IHS14SMJE/8838
IH5046MJE
IH5046CJE
IH5046MJE/8838
IH5047MJE

DNX7
DNX8
DNX9
D5OO26
DS0026

2N4416
2N4416
2N4339
ICL7667
ICl7667

FE304
FE3819
FE4302
FE4303
FE4304

2N3821
2N5484
2N5457
2N5459
2NS458

HI0-0381-6
HI0-0384·6
HI0-0387·6
HI0-0390-6
HI0-OS06-6

DGM181C/D
OGMl84C/D
DGM187C/D
DGM190C/O
IH6116C/O

HII-5047·5
HI1-5047·8
HII-5049-2
HI1-5049-S
HIl-5049-8

IH5047CJE
IHS047MJE/8838
IHS149MJE
IHS149CJE
IHS149MJE/8838

DU4339
DU4340
ElOO
ElOl
El02

2N5397
2N5398
2NS458
J204
2N5457

FES24S
FE5246
FE5247
FES457
FES458

2N4416
2N5484
2N5486
2N5457
2N5458

HIO-OS06A-6
HIO-OS07-6
HIO-0507A-6
HIO-OS08-6
HIO-0508A-6

IHS116C/D
IH6216C/D
IHS216C/D
IH6108C/D
IHSI08C/D

HIl-S050-2
HI1-5050-5
HIl-5050-8
HIl-5051-2
HIl-50S1-5

IHS1SQMJE
IH5150CJE
IH5150MJE/8838
IH5151MJE
IH51S1CJE

El03
El05
El06
E107
El08

2N5459
J105
Jl06
J107
JI05

FE5459
FES484
FE5485
FE5486
FF400

2N5459
2NS484
2N5485
2N5486
2N5457

HIO-0509-6
HIO-0509A-6
HIO-5040-6
HIO-5041-6
HIO-5042-6

IH6208C/D
IH5208C/O
IH514DC/D
IHS141C/O
IH5142C/D

HIl-5051-8
HI2-0200-2
HI2-0200-4
HI2-0200-5
HI2-02oo-8

IH5151 MJE/8838
DG200AA
DG200BA
DG2008A
DG2ooAAl883B

El09
EIIO
Elll
El115
ElllA

J106
JI07
JIll
ICMll15A
Jill

FMI100
FMl100A
FMll01A
FMl102
FMII02A

2N3954A
2N5906
2N5906
2N3954
2N5906

HI0-5043-6
HI0-5044-6
HI0-5045-6
HI0-5046-6
HIO-5047-6

IH5143C/O
IH5144C/O
IH5145C/D
IH5046C/D
IH5047C/O

HI2-0381-2
HI2-0381-5
HI2-03BI-B
HI3-0200-5
HI3-020l-5

DGM182AA
DGM1818A
DGMI81AA1B83B
DG200CJ
DG201CJ

E112
E112A
E1l3
E113A
Ell4

J112
J1l2
J113
J1l3
J204

FMl103
FMll03A
FMll04
FMl104A
FMll05

2N3955
2N5908
2N3957
2N5909
2N3954A

HIO-5049-6
HIO-5050-6
HI0-5051-6
HIl-0200-2
HU-0200-4

IH5149C/O
IH5150C/O
IH5051C/O
OG200AK
DG200BK

HI3-0381-5
HI3-0384-5
HI3-0390-5
HI3-0506·5
HI3-0S06A-5

DGM181CJ
OGM184CJ
DGM190CJ
IH6116CPI
IH5116CPI

Ell51
E1426
El74
El75
E176

ICM11158
ICM7050U
J174
J17S
J176

FMll05A
FMII06
FMI106A
FMl107
FMII07A

IT500
2N3954A
IT500
2N3954
1T500

HIl-0200-S
HI 1-0200-6
Hll-0200-8
HIl-0201-2
HIl-0201-4

DG200BK
DG200C/D
DG200AK/883B
OG201AK
DG2018K

HI3-0507-5
H13-0507A-5
H13-OS08-5
HI3-0S08A-5
HI3-0S09·S

IH6216CPI
IH5216CPI
IH6108CPE
IH5108CPE
IH6208CPE

EI77
E201
E202
E203
E204

JI77
J201
J202
J203
J204

FMII08
FMI108A
FMl109
FM1109A
FMl110

2N3955
ITS02
2N3957
1T503
2N3955

HII-0201-5
HII-0201-8
Hll-0381-2
HI1-0381-S
HII-0381-8

DG20l8K
DG201AK/8838
OGM182AK
DGM181BK
OGM 182AK/8838

HI3·0509A-5
ICl7611
ICl7612
ICl7621
tCl7631

IH5208CPE
ICl76l1
ICl7612
ICl7621
ICl7631

E210
E211
E212
E230
E231

2N5397
2N5397
2N5397
2N4867
2N486B

FMl110A
FMllll
FM1111A
FMll12
FM1200

2N5908
2N3957
2N5909
2N5196
2N3954

HII-0384-2
HI 1-0384-5
HIl-0384-8
HIl-0387·2
HIl-0387-5

DGM185AK
DGM1848K
OGM185AK/8838
DGM188AK
DGM187BK

ICl7641
ICl7642
ICL7650
ICL7652
ICL7660

ICl7641
ICl7642
ICL7650
ICL7652
ICL7660

E232
E270
E271
E300
E304

2N4869
J270
J271
2NS397
2N5486

FM1201
FM1202
FM1203
FM1204
FM120S

2N3954
2N3954
2N3955A
2N3955
2N3954

HIl-0387-8
HIl·0390-2
HI1-0390-5
HI 1-0390-8
HIl-0506-2

DGM188AK/8838
OGM191AK
DGM190BK
DGM191AK/883B
IH6116MJI

ICL7663
ICL7665
ICL8069
ICM7240
ICM7242

ICL7663
ICL7665
ICL8069
ICM7240
ICM7242

E305
E308
E309
E310
E311

2N5484
J308
J309
J310
J310

FM1206
FM1207
FM1208
FM1209
FM1210

2N3954
2N3954
2N3955A
2N3955
2N3955A

HIl-0506-5
HIl-OS06-8
HIl-0506A·2
Hll·0506A-5
HIl-0506A-8

IH6116CJI
IH6116MJII883B
IH5116MJI
IH51161J1
IHSl16MJI/8838

ICM7250
lCM7555
lCM7556
ICNOOM7555
10100

ICM7250
ICM7555
ICM7556
ICM7555
10100

E312
E400
E401
E402
E410

2N5397
2N3955
2N3955
2N3957
2N3955

FM1211
FM3954
FM3954A
FM395S
FM3955A

IT5911
2N39S4
2N3954A
2N39S5
2N3955A

HIl-0507-2
HIl-0507-5
HIl-OS07-8
HIl-0507A-2
HIl-0507A-5

IH6216MJI
IH6216CJI
IH6216MJI/8838
IH5216MJI
IH52161J1

ID10l
IMF3954
IMF3954A
IMF3955
IMF3955A

IDlOl
2N3954
2N3954A
2N3955
2N3955A

DN33678
DN3368A
DN33688
DN3369A
DN3369B

2N4091
2N4341
2N4221
2N4339

ESM25A
E5M4091
ESM4092
E5M4093

2N4220

ESM4302

DN3370A
DN3370B
DN3436A
DN3436B
DN3437A

2N4338
2N4338
2N4341
2N4222
2N434O

ESM4303
E5M4304
ESM4445
ESM4446
E5M4447

DN34378
DN3438A
DN3438B
DN3458A
DN34588

2N4220
2N4338
2N4339
2N4341
2N4222

DN34S9A
DN34598
DN3460A
DN3460B
DNXI

"CONSULT FACTORY

U401
2N4091
2N4092

FT3B20
FT3909

xxv

ALTERNATE

SOURCE PRODUCT

INTERSIL
EQUIVALINT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

2N3956
2N3957
2N3958
IMF5911
IMF5912

ITE2913

IMF3958
IMF5911
IMF5912

ITE2915
ITE2916
ITE2917

1Tl22
1T122
ITl20
ITl20
ITl22

JI13A
J1l3A·18
J114
J1401
J1402

J113
J113
2N5555
IT501
IT502

J4869
J4869A
J4869RR
J5103
JS104

IMF648S
1Tl00
1Tl01
1Tl08
ITl09

IMF6485
1Tl00
ITlOI
ITE4416
ITE4416

ITE291S
ITE2919
ITE2920
ITE2936
ITE2937

1Tl22
1Tl20
ITl20
1Tl20
1Tl20

J1403

IT503
ITS03
ITS04
ITS05
JI74

JS105
J5163
K114·18
K210·18
K211·18

2N5486

J140S
J1406
J174

1Tl20
1T120A
ITl21
ITl22
ITl26

1Tl20
1Tl20A
1Tl21
1Tl22
1Tl26

ITE2972

ITl22
ITI22
ITI20
1Tl20
1Tl20

J174·18
J175
J17S·18
J176
J176·18

J174
J175
J17S
J176
J176

K212·18

ITE2974
ITE2975
ITE2976

K304-18
K305·18
K308·18

2N5397
2N5397
2N5486
2N5484
J308

ITl27
ITl28
ITl29
ITl30
1T130A

1Tl27
1Tl28
1Tl29
1Tl30
1Tl30A

ITE2977
ITE2978
ITE2979
ITE3066
ITE3067

1Tl20
1T120
1Tl20
2N3685
2N3686

JI77
JI77·18
J201
J201-1S
J202

JI77
JI77
J201
J201
J202

K309-18
K310-18
KE3684
KE3685
KE3686

J309
J310
2N3684
2N3685
2N3686

ITl31
ITIl2
ITl36
1Tl37
1Tl38

1Tl31
1T132
1Tl36
1Tl37
1Tl3S

ITE306S

2N3687

Ill37
1Tl38
1Tl39
1Tl37

J202·1S
J203
J203·18
J204
J204·18

J202
J203
J203
J204
J204

KE3687

ITE3347

ITE3348
ITE3349
ITE3350

KE3970
KE3971
KE3972

2N3687
2N3823
ITE4391
ITE4392
ITE4393

1Tl39
1Tl40
1T1700
1T1701
ITl702

1Tl39
ITl40
ITl700
3N172
3NI63

ITE3351
ITE3680
ITE3S00
ITE3802
ITE3804

1Tl3S
1T120
1T132
1Tl32
ITl30

J210
J211
J212
J230
J231

2N5397
2N5397
2NS397
2N4867
2N4868

KE4091
KE4092
KE4093
KE4220
KE4221

ITE4091
ITE4092
ITE4093
2N5457
2N5459

1Tl750
IT2700
IT2701
IT400
IT500

1T1750

ITE3806
ITE3S07
ITE3808
ITE3809
ITE3810

1Tl32
1Tl32
1T132
1T132
ITl30

J232

3N165
2N4392
ITSOO

J270·18
J271
J271-18

2N4S69
J270
J270
J271
J271

KE4222
KE4223
KE4391
KE4392
KE4393

2N5459
J204
ITE4391
ITE4392
ITE4393

ITSOOP
IT501
ITS01P
IT502
ITS02P

ITSOO
IT501
IT501
IT502
ITS02

ITE3811
ITE3907
ITE3908
ITE4017
ITE4018

ITl30
1Tl20
1Tl20
1Tl39
1Tl39

J300
J304
J305
J308
J309

2NS397
2N5486
2N5484
J308
J309

KE4416
KE48S6
KE4857
KE48S8
KE4859

ITE4416
ITE4391
ITE4392
ITE4393
ITE4391

ITS03

ITS03
ITS03
ITS04
ITSOS
ITS50

ITE4019

J310
J31S
J316
J317
J3970

KE4860

ITE4021
ITE4022
ITE4023

1Tl39
ITl39
1Tl39
1Tl39
1Tl37

J310

IT504
IT50S
ITS50
IT5911
ITS912
ITC2972
ITC2973
ITC2974

ITS911
IT5912
1Tl22
1Tl22
1Tl20

ITE4024
ITE402S
ITE4091
ITE4092
ITE4093

1Tl37
1Tl37
ITE4091
ITE4092
ITE4093

J3971
J3972
J401
J402
J403

ITC297S
ITC2976
ITC2977
ITC2978
ITC2979

1Tl20
ITI20
1Tl20
1Tl20
1Tl20

ITE4117
ITE4118
ITE4119
ITE4338
ITE4339

2N4117
2N4118
2N4119
2N4338
2N4339

J404
J40S
J406
J4091
J4092

ITC3347
ITC334S
ITC3349
ITC33S0
ITC33S1

1Tl37
1Tl3S
ITl39
ITl37
1Tl38

ITE4340
ITE4341
ITE4391
ITE4392
ITE4393

2N434O
2N4341
ITE4391
ITE4392
ITE4393

ITC33S2
ITC3800
ITC3802
ITC3804
ITC3806

1Tl39
ITI32
1T132
1Tl30
1Tl32

ITE4416

ITE4416

ITE4867

2N4867

ITE4868
ITE4869
JlOO

2N4868
2N4869
2NS4S8

J4221
J4222
J4223

ITC3807
ITC3808
ITC3809
ITC3810
ITC3811

1T132
1Tl32
1Tl32
1Tl30
1Tl30

JIOI
JI02
JI03
Jl05
Jl05-IS

2N4338
2NS4S7
2N5459
Jl05
Jl05

ITC4017
ITC4018
ITC4019
ITC4020
ITC4021

1Tl39
1Tl39
1Tl39
1T139
1Tl39

JI06
Jl06-IS
JI07
J107·18
JIOS

JI06

ITC4022
ITC4023
ITC4024
ITC4025
ITE2453

1Tl39
1Tl37
1Tl37
1Tl37
ITl20

ITE2639
ITE2640
ITE2641
ITE2642
ITE2643
ITE2644
ITE2720
ITE2721
ITE2722
ITE2903

IMF3956
IMF3957

ITS03P

3Nl65

ITE2914

ITE2973

ITE4020

J1404

J270

K300-18

KE3823

2N4869
2N4869A
2N4869

2N5484
2NS48S
2NS486

2NS55S
2NS397
2N5397

ITE4392

2NS397

KE4861

ITE4393

U309
U310
ITE4391

KES10
KES103
KES104

ITE4393
J204
ITE4416

ITE4392
ITE4393
IT501
IT502
IT503

KES10S
KE511
KH5196
KH5197
KH5198

ITE4416
ITE4392
2N5196
2N5197
2N5198

IT503
ITS05
ITE4091
ITE4092

KH5199
KS6183
KS524OBOIH
KS524OBOlJ
KS524OBIOH

2NS199
ICM7269
ICM724SB
ICM7245A
ICM72450

J4093
J410
J411
J412
J420

ITE4093
IT502
IT503
ITS03
ITS911

KS524OBI2H
KSS240B20H
KS524OU01E
LOF603
LOF604

ICM7245E
ICM7245F
ICM724SU
2N4221
2N4221

J421

IT5912
J202
J203
J202

LOF60S
LF1l201D
LFl1201D/883
LF115080
LFlI508D/8B3

2N4221
DG201AK
DG201AK/8B38
IH6108MJE
IH6108MJE/8B38

J4224
J430
J4302
J4303
J4304

J202
J309(X2)
2N4302
2N5459
2N5458

LFll509D
LFlI5090/883
LFI32010
LFl320lN
LFl35080

IH6208MJE
IH6208MJE/8B3B
OG2018K
DG20lCJ
IH6108CJE

J431

J4220

IT504

J204

J433

~~~~W)

LFI3508N

J106

JI07
JI07
JI05

J4338
J4339
J4391

2N5457
2N5457
ITE4391

LFI3509N
LM113
LMI14

IH610SCPE
IH6208CJE
IH620SCPE
ICL8069
1Tl20

J108·18
JI09
J109·18
JI10
Jllo-18

JI05
JI06
JI06
JI07
JI07

J4392
J4393
J4416
J4856
J4857

ITE4392
ITE4393
ITE4416
ITE4856
ITE4857

LMI14A
LMI14AH
LMI14H
LMI15
LM115A

1Tl20A
ITl20A
1T120
1Tl20
1T120A

1Tl20
1Tl22
1T122
1Tl20
1Tl22

Jill
JI1I·18
Jl11A
JI1IA-18
JI12

Jill
Jill
Jill
Jill
J112

J4858
J4859
J4860
J4861
J4867

ITE4858
ITE4860
ITE4861
2N4867

LM1l5AH
LM115H
LM185
LMI94
LM394

1Tl20A
ITI20
ICL8069
ITl20A
1Tl20A

1Tl22
1Tl20
1Tl22
1Tl20
1Tl22

J112·18
J112A
J112A·18
JI13
J113·18

J112
JI12
J112
JI13
JI13

J4867A
J4867RR
J4868
J4868A
J4868RR

2N4867A
2N4867
2N4868
2N4868A
2N4868

LM4250
LM4250
LM555
LM556
LMC555

LM4250
ICL8021
ICM7555
ICM7556
ICM7555

"CONSULT FACTORY

XXVI

ITE4859

LF13509D

ALTt:RNATE
SOURCE PRODUCT

INTI!RSIL
I!QUIVALI!NT

ALTERNATE
SOURCE ....ODUCT

lMC556
lMC668
l53069
l53070
lS3071

ICM7556

lS3458
l53459
lS3460

J204
J204
J204
2N3684
2N3685

M58436-DOIP
M58437-DOIP
MA7807
MA7809

LS3686

2N3686
2N3687
2N5484
2N5457
2N5458

lS3823
l53921
l53922
l53966
l53967

2N5458
2N3921
2N3922
ITE4416

lS3684
lS3685
l53687
lS3819
lS3821
lS3822

ICl7650
2N5458
2N5458
2N5458

ITE4416

M511
M511A

INTERSIL
EQUIVALENT

3Nl72

MS17

3N172
3N163

M58434P
M58435P

ICM11158

ICM7038D

ALTERNATE
SOURCE ~RODUCT

M08002

M0800~

MD918
M0918A
M0918B

MF818
MFE2000

MFE2005

2N5459
2N4341

MFE2006
MFE2007
MFE2008
MFE2009
MFE2010

MEF3684

2N4339
2N4341
2N4339
2N4338
2N3684

MEF3685
MEF3686
MEF3687
MEF3821
MEF3822

2N3685
2N3686
2N3687
2N3821
2N3822

MFE2012

MAT·OIAH
MAT-OIFH
MAT-OIGH
MAT-OIH
MAX232
MAX420

1T140
lT140
1T140
ICl232
lCl420

MEF3070
MEF3458
MEF3459
MEF3460

MAX663
MAX665
MAX8211
MAX8212

lCL7663

MEF3069

IT£4416

MBI03

ICM7245E

MEF3823

ITE4416
J204
J202
J203

M8105
M8107
M8108
M8143

ICM7245U
ICM72450
ICM7245E
ICM7245A

MEF3954
MEF3955
MEF3956
MEF3957

l54223
l54224
lS4338
lS4339
l54340

J202
J202
2N5457
2N5457
2N5457

M8144
MB510
M8511
MB512
MB513

ICM7245F
ICM1115B
ICM7050H
ICM7050H
ICM7050G

MEF3958
MEF4223
MEF4224

LS4341

2N5458
ITE4391
ITE4392
ITE4393

MB521

MB522
MB531
MB533
MB541

IT59068
IT59068
ICM7050H
ICM7050H
ICM7052

ITE4416

MF803

MFE2004

LS3968
lS3969
l54220
L$4221
l54222

lS4391
lS4392
lS4393
lS4416

MEM9558
MF510

2N5457

M0982
M0984
MEFI03
MEFI04

MBlOl

1T120
ITl22
1T122
1T122
1T122

ALTI!RNATE
SOURCE ....ODUCT

In3g
1T139

ICM7050G
lCM7070l
1T132
1T132
ITl40

ICl7665
ICl8211
ICl8212
ICM7245B

INTERSIL
EQUIVALENT

MFE2001

MFE2011
MFE20l2
MFE2093

MFE2094
MFE2095
MFE2133

2N3823
2N3954

MFE2912

2N3955

MFE3003

MFE3002

INTI!RSIL
EQUIVALENT

3NI90
2N4092
2N4338
2N4858
2N4416
2N4416
2N4093
2N4092
2N4091
2N4860
2N4859
2N4859
2N4859
2N5433
2N5434
2N5433
2N4338
2N4339
2N4340
2N4860
2N5433
3NI70
3NI64

2N3956

MFE3020

3NI66

2N3957

MFE3021

3NI66

MFE4007

MEF4391
MEF4392

2N3958
2N4223
2N4224
ITE4391
ITE4392

2N3686
2N3686
2N3685
2N2608
2N2608

MEF4393
MEF4416

ITE4393
ITE4416

MEF4856
MEF4857
MEF4858

2N4856
2N4857
2N4858

MFE4008
MFE4009

MFE4010
MFE4011
MFE4012

MFE823
MHW590
MJ41
MJ6

2N2609
ITl700
A0590
ICMI424C
ICM7220

lS4856
lS4857
lS4858
lS4859
lS4860

ITE409 I
ITE4093
ITE409 I
ITE4092

MB542
MB7B
MCC14440
MCCl4483
M01120

ICM7052
ICM7245U
ICMI424C
ICM7210
1T122

MEF4859
MEF4860
MEF4861
MEF5103
MEF5104

2N4859
2N4860
2N4861
ITE4416
IT[4416

MM452F

lS486 I
lS5103
lS5104
lS5105
lS5245

ITE4093

M01121

1T122

MEF510S

MM455H

MM455H

2N5484
2N5485
2N5486
ITE4416

M01122

1T122
1T139
1T129
1T139

MEF5245
MEF5246

ITE4416
ITE441G
2NS484

MM550H

MM550H

MEF5248

2N5486
2N5486

2N5484

M02218
M02218A
M02219

1T129

MM555H
MMFI
MMF2

1T129

MEF5284
MEF5285
MEF5286
MEF5561

2N5485
2N5486

MD2219A

U401

MMF3

M02369

1T129

MMF4

lS5246
lS5247
lS5248
lS5358
lS5359
LS5360

lS5361
lS5362
LS5363

lS5364
lS5391
lS5392
lS5393
lS5394
lS5395

ITE4092

2N5486

2N5486
J204
J204
J202
J202
J203
J203
J203
2N4867A

MOl123

M01129
M01130

1T129

1T129

MEF5562

U402

MD2369A

1T129

MEF5563

MEM511

U403
3NI72

MD2904

1T122
1T139

MEMSIIA

3Nl72

M02904A
M02905

1T139
1T139

MEM511C

3NI72

MEM517

M02905A

1T139

2N4868A

MD2974

M02975

2N4869A

M02978

1T120
1T120
1T120

2N4869A

M02979

1T120

l55396
lS5457
lS5458
lS5459
lS5484

2N5458
2N5459
2N5484

M03251A

lS5485
lS5486
lS5556
lS5557
lS5558

2N5485
2N5486
2N3685
2N3684
2N3684

M03409
M03410
M03467

1T139

M03725
M03762

1T129
1T139

LS5638

2N5638

M04957

ITl32

lS5639

2N5639
2N5640
ICl7660
ICl7652

M05000

1T132

MD5000A

1T132
1T132

LS5640

lTCI044
lTCI052

2NS484

M02369B

2N4869A

2N4869A
2N5457

MEF5247

MD3008

M03250
M03250A
MD3251

M05000B
M07000

1T120
1T132

MKIO
MM400H
MM4S1H

MM4520

MM5S1H

MM5S1H

MM5520

MM552J
MM552F

MM552F

MM555H
2N5197
2N3921
2N5198
2N3922

MMF5

2NS199

MMF6
MMT3823

2N3955A
2N3823

3Nl72

MN6091
MN6092A

ICM7038E

MEM517A
MEMSl7B

3NI72

MN6093

3Nl72

MN6252

rCM70SOG

MEM517C
MEM550
MEM550C

3NI72

MP301
MP302

1T124

3N189

3NI89

MP303

1T124

ICM7051A
rT124

3N189
3N190

MP310
MP311

2N4045
2N4045

3NI89
3Nl72

1T124

1T131

MEM556C

3NI72

MP312
MP313
MP318

1T129

MEM560

3NI61

MP350

1T132

1T129

MEM560C

MP351

1T130

MEM561

3Nl61
3N163

MP352

MEM561C

3NI63
2N4351

MP358
MP360

1T130
1T130A
ITI32

2N43S1

2N4351

1T129

ICl7650

MD7001

ICL7652

3NI61

M07002
M07002A

1T122

3Nt61

MD7002B

1T122

MI06

3NI66

1T139
1T122

MEM550F

rCM70388

MEM556

MI04

MEM562
MEM562C
MEM563

MP361

1T130A

2N4351

MP362
MP3954

1T130A
2N3954

M116

MP3954A

2N3954A

MIl6

MP3955

2N3955

MEM712A
MEM713
MEM806

MIl6
3N170

MP3956
MP3957

3NI63

MP3958

MEM806A
MEM807

3N163

MP5905
MP5906

2N3956
2N3957
2N3958
2N5905
2N5906

M07003

1T132

3N189

MD7003A

3NI91
3NI61
3NI61
M116

M07003B
M07004
M07007
M07007A

1T132
ITl32
1T129
1T129

MEM816
MEM817

1T129

MEM823

MFE823

M117
M119
MI63

2N4351

M07007B
M0708
M070BA

1T129

3NI63
3N164

MD7088

MEM954
MEM954A
MEM9548
MEM955

3NI88
3NI88
3NI88

M164

3Nl90

MP7520JN
MP7520KO
MP7520KN

MooOI

ICM7269

M08001

MEM955A

3NI90

MP7520LD

1T129

1T120A

MEM711
MEM712

MI07

1T129
1T129
1T120

2N4044

MEM563C

MI08
MI13
M114
M116

"CONSULT FACTORY

MM452F

MEM551
MEM551C

1T131
1T132

lTCI052
lTC7652
MI03

3N161

2N4416
MM450H
MM4S1H
MM452J

MEM807A
MEM814

XXVII

3NI72
3Nl72

MP5907

2N5907

3NI61
3NI72

MP5908

2N5908
2N5909

3Nl72

MP5909
MP5911
MP5912
MP7520JD

2N5911
2N5912
AD7520JD
AD7520JN
AD7520KD

A07!>20KN
AD7520LD

ALTERNATE
SOURCE PRODUCT
MP7520LN
MP7520SD
MP7520TD
MP7520UD

INTERSIL
EQUIVALENT

AD7520lN

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

INTERSIL
EQUIVALENT

SJM187BCC
SJM187BIC
SJM188BCC
SJM188BIC
SJM190BEC

JM38510/11105BCC
JM3851 0/111 0581C

SJM191BEC

JM38510/11108BEC

AD7520SD
AD7520TD
AD7520UO
AD7521JD

NF51Ql
NF5102
NF5103
NF511
NF5163

2N4867
2N4867
2N4867
2N4860
2N4341

PN3687
PN4091
PN4092
PN4093
PN4220

AD7S2IJN
AD7521KD
AD7521KN
A07521LD
AD7521LN

NF520
NFS21
NF522
NF523
NF530

2N3684
2N3685

PN4221

2N4341

PN4222
PN4223
PN4224
PN4342

MP7521TD
MP7521UD
MP7523JN
MP7S23KN

AD7521SD
AD7521TD
AD7521UD
AD7523JN
AD7S23KN

NF5301
NF5301-1
NF5301-2
NF5301-3
NF531

2N4118A
2N4117A
2N4118A
2N4118A
2N4339

PN4360
PN4391
PN4392
PN4416
PN4856

5l362C
5M50l1
5M5510
5M55308

ITl29
ITl29
ICM7050G
ICM1l158
tCM7070P

MP7523lN
MP7621AO
MP7621BO
MP762IJN
MP7621KN

AD7523LN
AD7541AD
AD754180
A07541JN
AD7541KN

NF532
NF533
NF5457
NF5458
NF5459

2N4341
2N4339
2N5457
2N5458
2N5459

PN4857
PN4858
PN4859
PN4860
PN4861

2N4857
2N4858
2N4859
2N4860
2N4861

5U2OO0
5U2020
5U2021
5U2022
5U2023

2N4340
2N3954
2N3954
2N3954
2N3954

MP7621SD
MP7621TD
MP804
MP830
MP831

AD754150
A07541TD
2N5520
2N5520
2N5521

NF5484
NF5485
NF5486
NF5555
NF5638

2NS484
2N5485
2N5486
2N5484
2N5638

PN5033
PTC151
PTC152
RC555
RC556

2N5460
2N5484
2N5485
ICM7555
ICM7556

SU2024
5U2025
5U2026
5U2027
5U2028

2N3954
2N3954
2N3954
2N3954
2N3954

MP832
MP833
MP835
MP836
MP837

2N5522
2N5523
2N3954
2N3955
2N3955

NF5639
NF5640
NF5653
NF5654
NF580

2N5639
2N5640
2N4860
2N4861
2N5432

SI424
SA2253
SA2254
SA2255
5A2644

ICM1424C
ITI22
ITI22
IT122
ITI20

5U2029
5U2029
SU2030
5U2030
SU2031

2N5197
2N3954
2N3955
2N3954
2N5198

MP838
MP839
MP840
MP841
MP842

2N3956
2N3957
2N5520
2NS521
2N5523

NF581
NF582
NF583
NF584
NF585

2N5432
2N5433
2N5434
2N5433
2N4859

5A2648
5A2710
5A2711
SA2712
SA2713

ITI20
lTI20
ITI20
ITI21
ITI21

5U2031
5U2032
SU2033
SU2034
SU2034

2N3954
2N3954
2N3954
2N3955
2N3954

MPFlD2
MPF103
MPFl04
MPF105
MPFl06

2N5486
2N5457
2N5458
2N5459
2N5485

NF6451
NF6452
NF6453
NF6454
NKT80111

U310
U310
U310
U310
2N4220

SA2714
SA2715
5A2716
SA2717
SA2718

ITI22
ITI20
ITI20
ITI21
ITI22

SU2035
SU2035
SU2074
SU2075
SU2076

2N3955
2N3954
2N3954
2N3954
2N3954

MPFI07
MPFI08
MPFI09
MPFllI
MPFl12

2N5486
2N5486
2N5484
2N5458
2N5458

NKT80112
NKT80113
NKT80211
NKT80212
NKT80213

2N4220
2N3821
2N4339
2N4339
2N4339

SA2719
SA2720
SA2721
SA2722
SA2723

ITI20
ITI21
1T122
ITI20
1Tl21

SU2077
SU2077
SU2078
SU2079
SU2080

2N3955
2N3954
2N3955
2N39S5
U404

MPF161
MPF208
MPF209
MPF256
MPF4391

2N5398
2N3821
2N3821
ITE4416
ITE4391

NKT80214
NKT8021S
NKT80216
NKT80421
NKT80422

2N4339
2N4339
2N4339
2N4220
2N4220

SA2724
SA2726
SA2727
SA2738
5A2739

ITI22
ITI22
tTI22
ITI20A
ITI20

SU2081
5U2098
5U2098A
SU20988
5U2099

U404
2N5197
2N5197
2N5196
2N5197

MPF4392
MPF4393
MPF820
MPF970
MPF971

ITE4392
ITE4393
J310
J175
J175

NKT80423
NKT80424
NPCI08
NPC21lN
NPC212N

2N4220
2N4220
2N5484
2N4338
2N4338

5CL54301
5CL5478
SDFlOOl
SDFlO02
5DFlO03

ICM1424C
ICM7269
2N5432
2N5433
2N5434

SU2099A
5U2365
SU2365A
SU2366
5U2366A

2N5197
2N3954
2N3954
2N3955
2N3955

MP55010
M5M5001
M5M5011
M5M5977
MTFlOI

ICL8069
ICM7269
ICM1424C
ICM1424C
2N5484

NPC213N
NPC214N
NPC2l5N
NPC216N
NPD8301

2N4338
2N4339
2N4339
2N4339
2N3954

5DF5oo
SOF501
50F502
50F503
SDF504

2N5520
2N5520
2N5520
2N5520
2N5520

5U2367
SU2367A
5U2368
SU2368A
SU2369

2N3955
2N3955
2N3956
2N3956
2N3957

MTFl02
MTFI03
MTFt04
ND5700
ND5701

2N5484
2N54S7
2N5459
ITl20A
ITl20A

NPD8302
NP08303
OT3
P1004
PI005

2N3955
2N3956
2N4338
2N5116
2N5115

SDF505
SOF506
SDF5D7
50F508
5DF509

2N5520
2N5520
2N5520
2N5520
2N5520

SU2369A
5U2410
5U2411
5U2412
5U2652

2N3957
2N5907
2N59D8
2N5909
U401

ND5702
NDF9401
NOF9402
NDF9403
NOF9404

ITl20
IT500
IT501
IT502
IT503

PI027
PlO28
PI029
PI069E
P1086E

2N5267
2N5270
2N5270
2N2609
2N5115

SDF510
50FS12
SOF513
50F514
SDF661

2N3954
2N3954
2N3954
2N3954
1Tl22

SU2652M
5U2653
5U2653M
5U2654
SU2654M

U401
U401
U40l
U401
U40l

NOF9405
NOF9406
NOF9407
NDF9408
NDF9409

ITS04
IT500
IT501
IT502
IT503

Pl087E
Pll17E
Pll18E
Pl119E
PF510

2N5516
2N5640
2N564l
2N5640
2N5115

SOF662
SDF663
SE555
5E556
SES3819

ITl22
ITI22
ICM7555
ICM7556
2N5484

SU2655
SU2655M
SU2656
5U2656M
SX3819

U402
U402
U404
U404
2N5484

NDF9410
NE555
NE556
NE590
NF3819

IT504
ICM7555
ICM7556
A0590
2N5484

PF5101
PF5102
PF5l03
PF511
PF5301

2N4867
2N4867
2N4867
2N5114
2N4118A

SFT601
SFT602
5FT603
5FT604
5G4250

2N4338
2N4338
2N4339
2N4339
LM42S0

SX3820
TC803lP
TC8032P
TC8051P
TC8052P

2N2608
ICM7038A
ICM7038F
lCM70388
ICM7038E

NF43D2
NF4303
NF4304
NF4445
NF4446

2N5457
2N5459
2N5458
2N5432
2N5433

PF5301-1
PF5301-2
PF5301-3
PLl091
PLl092

2N4117A
2N4118A
2N4118A
2N3823
2N3823

517135CPI
517652
517660
517661
SJM181BCC

ICL7l35CPI
tCL7652
ICL7660
ICL7662
JM3851O/II101BCC

TC8056PA
TC8057P
TDlOO
TOIOI
T0102

ICMll158
ICM70380
ITI29
ITl29
ITl29

NF4447
NF4448
NF500
NF501
NF506

2N5433
2N5433
2N4224
2N4224
2N4416

PLlO93
PLlO94
PN3684
PN3685
PN3686

2N3823
2N3823
2N3684
2N3685
2N3686

SJM181BIC
SJM1828CC
SJM18281C
SJM184BEC
5JM185BEC

JM38510/11101BIC
JM38Sl01l11028CC
JM38510/11102BIC
JM3851OIlI103BEC
JM38510/l1 104BEC

TD200
T0201
TD202
T02219
T0224

ITl29
ITl29
ITl29
ITl29
ITI22

MP752IJD
MP752IJN
MP7521KD
MP7521KN
MP7521LD
MP7521LN

MP1521SD

··CONSULT FACTORY

2N3686
2N3865

XXVIII

2N3687
ITE4091
ITE4092
ITE4093

ALTERNATE
SOURCE PRODUCT

J204
J202
J2D3

J204

Sl301AT
Sl301BT

J202

SL30lCT

2NS461

Sl301ET

2N5460
ITE4391
ITE4392
ITE4416
2N4856

Sl36DC

JM38510111106BCC
JM38510/11106BIC

JM38510/11107BEC

ITl29
ITl29
ITl29
ITl29

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

TD225

lTl22

TD226

lTI22
1T122
ITl22

TIS73
TI574

TI569
llS70

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PROOUCT

INTERSIL
EQUIVALENT

ALTERNATE

SOURCE PRODUCT

INTERSIL
EQUIVALENT

U1179
U1180
U1I81
U1182
U1277

2N3821
2N4221
2N4220
2N3821
2N3684

U300
U3000
U3OO1
U3OO2
U301

2N5114
2N4341
2N4339
2N4338
2N5115

2N4341
2N434O
2N4338
U304
U305

ITI22

TI575

2N3955A
2N3956
IT[4391
ITE4392
ITE4393

TD230
T0231
TD232
T0233
T0234

ITI21
ITI21
ITI22
ITI22

TIS88
TIS88A
TIXS33
TIXS35
TIXS36

2N4416
2N4416
2N4392
2N4857
2N4391

U1278

2N3685

U1279
U1280
U1281
U1282

2N3686
2N4341

U3010
U301l
U3012
U304
U305

TD235
T0236

ITI22

T0239

ITI22
ITI22
ITl22
ITI22

TIXS41
TIXS42
TIXS59
TIXS78
TIXS79

2N4859
2N5639
2N5459
2N4341
2N4341

U1283
U1284
U1285
U1286
U1287

2N4340
2N4341
2N4220
2N4341
2N4092

U306
U308
U309
U310
U311

U306
U308
U309
U310
U310

TD240
TD241

1T12l
1T121

Tl182CL
TLl82CN

U312

2N5397

U314

2N5555

TL1821L
TL1821N
TL182ML

U1321
U1322
U1323

2N3822

ITl20A
ITl20A
ITl29

OGM182BA
DGM182CJ
DGM182BA

2N4860

TD242
TD243
TD244

2N3822

DGM182CJ

U1324

2N3687

U315
U316

DGM182AA

U1325

2N3686

U317

2N5397
U309
U310

TD245

ITl29
ITl29
ITl29
ITl29
1T120A

U133

2N5433

TLl851J

IH5045CJE
IH5045CPE
IH5045CJE
IH5045CPE
IH504SMJE

U320

TD246
TD247
TD248
TD2S0

TD2905

1Tl39

UI47

TD400

1T139
1T139
ITl39
In39

TLl88ML

IH5042CTW
IH5042CPE
IH5042CTW
IH5042CPE
IHS042MTW

TL191CJ
TL19ICN
TL1911J
TL1911N
TLl9IMJ

IH5043CJE
IHS043CPE
IH5043CJE
IH5043CPE
IH5043MJE

TLC251
TLC252
TLC254
TLC271

ICL7612
ICL7611
ICL7621
ICL7642
ICL7612

TD227
T0228
TD229

TD237
T0238

TD401
T0402

TD500

ITI22

TL185CJ
TL185CN
TL1851N
TL185MJ
TL188CL
TL188CN
TL1881L
TL1881N

2N3684

2N3822

U1420

2N2608
2N3821

U1421

2N3822

U1422
U146

2N3822

2N2608

Ul49

2N2608
2N2608
2N2609

U168

2N2609

Ul714

2N4340

U1715

2N4340

U182

2N4857

U183
U1837E
U184

2N3824

U148

U321
U322
U328
U329
U330
U331

2N5434

..
......

2N5433

U350
U401
U402

U401
U402

U403
U404
U405
U406
U410

U403
U404
U40S
U406
2N395S

TDSOl
TD502
TDS09
TDSlO
TOSll

In39
In39
In32

TOS12

TOSI8

ITl32
ITl32
1T132
ITl32
1T132

T0519
T0520
T0521
T0522
T0523

ITl32
ITl39
ITl39
In39
ITl39

TLC271
TlC272
TlC274
TLC274
TLC555

ICL7611
ICL7621
ICL7642
ICL7641
ICM7S55

T0524
T0525
TD526
TD527
TD528

ITl39
ITl32
ITl32
IT131
ITl31

TLC556
TN41I7
TN4117A
TN4118
TN4118A

ICM7556
2N4117
2N4117A
2N4118
2N4118A

T05432
T05433
T05434

2N5432
2N5433
2N5434
1T129
2N5902

TN4119
TN4119A

U234

UCIIO
UCIl5

TN4338

U235

U235

UC120

2N3686

TN4339
TN4340

2N4119
2N4119A
2N4338
2N4339
2N4340

U240
U241

2N5432
2N5433

UC130

2N3687
2N4416

TN4341
TN5277
TN5278

2N4341
2N4341
2N4341

U242

2N5432

UCI700

TD5903A

2N5902
2N5903
2N5903

U243

UC1764

TD5904
TD5904A

2N5904
2N5904

TP5114

2N5114
2N5115

U248
U248A

2N5433
2N5433
2N5902
2N5906

UC201

2N3824

TD5905

2N5905

TD5905A

TPS116
TSC426
TSC7106CJl

U249

2N5903

U249A

2N5907

UC21
UC210

2N3687

TSC7106CPL

TD5907

U250
U250A
U251

2N5904

TD5906A

2N5905
2N5906
2N5906

TD513
TOS14

TD517

TD550
TD5902
TD5902A
TD5903

ITl32
1T132

TLC251

TP5115

U1897E
U1898E
Ul97

U1899
2N4338

U41l
U412
U421
U422

U198

2N434O

U423

U199

U202

2N4859

U424
U425
U426
U430
U431

2NS908
2NS908
2N5909

U201

2N4341
2N4416
2N4861
2N4860

U2047E
U221
U222

2N4416
2N4391
2N4391

U440
U441

U231

U231

U232

U232

IT5911
IT5912
ICM7555
ICM7556
2N3684

U1899E

U1994E

U200

U233
U234

U244

2N5907

TSC7106RCPl

2NS116
ICl7667
ICl7106CJL
ICl7106CPl
ICL7106RCPL

TD5907A

2N5907

TD5908

2N5908

TD5908A

TD5909

2N5908
2N5909
2N5909

ICL7107CJL
ICl7107CPL
ICl7107RCPl
ICL7109CPL
ICL7109IJL

U251A
U252
U253

TD5909A

TSC7107CJl
TSC7107CPl
TSC7107RCPL
TSC7109CPl
TSC7109IJl

TD5911

1T5911
IT5911
IT5912
IT5912
ITI22

TSC7109MJl
TSC7116CJl
TSC7116CPL
TSC7117CJL
TSC7117CPL

ICL7109MJL
ICL7116CJl
ICl7116CPl
ICl7117CJL
ICl7117CPl

U256

ICl7126CJl
ICL7126RCPL
ICL7135CJI
ICL7135CPf
ICL7650

TD5906

T05911A
T05912
TD5912A
T0700
T0701

1T122

TSC7126CJL

TD709

1Tl22

T0710

ITl22
ITI22
ITl22

TSC7126RCPL
TSC7135CJI
TSC7135CPI
TSC7650

TD711
TD713
TIS14
TIS25
TIS26

2N4340
2N3954
2N3954

TIS27

2N3955

TIS34

2NS486

TIS41
TIS42

2N4859

TIS58
TIS59
TIS68

2N4393
2N5484
2N5486
2N39S5A

"CONSULT FACTORY

TSC7660
TSC9491

TI-590
U110
U111
U112
Ul13
Ul14

Ul177
UIl78

ICL7660
ICL8069
AD590

2N2608

2N5486
2N5397

U254

U255
U257
U257/TO·71

U266
U273
U273A

U1897

U1898

U233

2N5908

2N5905
2N5909

U284

U285
U290
U291
U295
U296

XXIX

2N3824

UC2130
UC2132
UC2134
UC2136

2N4416
2NS452
2N5453
2NS454
2NS4S4
2N5454

2N3958

2N4861
U257

UC2149
UC220

2N3958

U257/TO-71

UC240

2N4869

2N4856
2N4118A

UC241

2N4869

UC250

2N4091

UC251

2N4392
3NI66

2N4119A

2N2608

3N163
3N163
2N3686

UC2138

U275A

2N2608
2N2608
2N2608
2N4220
2N3821

UC20

UC200

UC2139
UC2147
UC2148

2N4118A
2N4119A
2N4119A

U281

2N3685
2N4340

2N4859
2N4860

2N4119A

U282
U283

J309(X2)
J31O(X2)

IT5912

U274A

U280

UC155

2N5908
2NS908
2N5909

IT5911

U275

U274

UA555
UA556
UClOO

2N3956

2N3958

2NS4S2
2N54S3
2N5453

2N5453
2N5454
2N5454

2N5432
2N5434

2N5432
2N5434

UC2766

UC300
UC310
UC320
UC330
UC340

UC40
UC400
UC401

UC41
UC410
UC420
UC450
UC451

2N3958

2N3958
2N3822

2N2608
2N2607

2N2607
2N2607
2N2607

2N2608
2N5270
2N5116
2N2608
2N5268
2N5267

2N5114
2N5116

ALTERNATE
SOURCE PRODUCT'

INTERalL
EQUIVALENT

UC5BB
UC703
UC704
UC705
UC707

2N4416
2N4220
2N4220
2N4224
2N4860

UC714
UC714E
UC734
UC734E
UC751

2N3B22
2N4341
2N4416
2N4416
2N4340

UC752
UC753
UC754
UC755
UC756

2N4340
2N4341
2N4340
2N4341
2N4340

UC805
UC807
UCB14
UCB51
UCB53

2N5270
2N5115
2N5270
2N260B
2N260B

UCB54
UC855
UCN·4111M
UCN-4112M
UCN-4113M

2N260B
2N2609
ICM703BC
ICM7051A
ICM703BB

UPD1952P
UPD1962C
UPD1963C
UPDB15C
UPD816C

ICM7220MFA
ICM7050G
ICM7050
ICM7038E
ICM703BB

UPD820C
UPD833G

ICM1l15B
ICM7223
2N5397
2N5397
1Tl26

unoo
unOl

UXC2910
veRION
VCRllN
VCR12N

VCR13N
VCR20N

VCR2N
VCR3P
VCR4N

VCR5P
VCR6P

VCR7N
VF28

VF811
VF815
VFW40

VFW40A
VR-8069
W245A

W245B
W245C

A!.TEIINATE
SOURCE PRODUCT

'INTERaIL
IQUIVAUNT

AL,",RNATE
SQURCE PROOUCT

2N4869
VNRllN
2N3958
2N3958
2N4341
VCR2N
VCR2P

VCR4N
VCR5P
VCR6P
VCR7N
2N4392
2N4858
2N4858

ITl22
ITl20
ICL8069
ITE4416
ITE4416
ITE4416

W300
W300A
W300B
W300C
W300D

2N5398
2N5397
2NS397
2N5397

WG-8038
WK5457
WK5458
WK54S9
XR555

ICL8038
2N5457
2N5458
2N5459
ICM7555

XR556
XR8038
ZOT40
ZDT41
ZDT42

ICM7556
ICL8038
1Tl29
ITl29

ZOT44
ZOT45

1Tl29
lTl29

2N5398

ITl29

"CONSULT FACTORY

xxx

' IN,",RIIL
IQUIVALENT

ALTeRNATe

SOURCE PRODUCT

INT.RaIL
EQUIVALENT

Section 1 -

Selector Guides

INTERSIL
YOUR COMPLETE SOURCE
FOR INTEGRATED SIGNAL PROCESSING
COMPONENTS
Intersil, founded in 1967, is a wholly owned subsidiary of General Electric
Company U.S.A., and a component of the GE/RCA Solid State Division,
headquartered in Somerville, New Jersey.
Intersil's Semiconductor Business charter has been the development of
an extensive analog/digital component complement focusing on the commercial, industrial, instrumentation and military markets. Based on the most
advanced innovations in CMOS technology, it has established itself as a
frontrunner in products serving the explosive data conversion and digital
signal processing marketplace.
Intersil's expanding product line is headed by a respected portfolio of
data converters, analog switches and multiplexers, display drivers, digital
controls and sophisticated linear circuitry. Technology innovations include
an operational 130-volt CMOS process with 3/-L and 4/-L feature sizes, and
a 5-inch wafer fabrication system. Intersil's new digital signal processing
products use advanced very large scale integration (AVLSI) processes with
a 1.5/-L feature size, and a 1.25/-L process is in the final stages of development. Intersil's next-generation MaS/bipolar (BiMOS) process that combines the best attributes of MaS and bipolar processing on a single chip.
Product quality and reliability are fundamental considerations in Intersil's
manufacturing facilities. Clean-room environments, Class 100 in critical
wafer processing areas and Class 5000 in manufacturing areas, easily
meet recommended standards. A high degree of factory automation has
phased out slower and less reliable manual operations.
And, overall, a high dedication to customer service reflects the Intersil
commitment to be one of the most respected semiconductor suppliers in
the industry.

DATA ACQUISITION
The proliferation of microprocessors and the general swing
to digital signal processing has caused an explosion in the
need for data acquisition products. In turn, the associated
data translation requirements from the analog world to digital
format, and vice versa, have spurred considerable effort
toward making AlD-D/A converters progressively smaller,
cheaper, and more reliable. Toward that end, Intersil has
developed a family of integrated circuits designed to meet
the varying requirements of the system designer.
All of Intersil's converters are fabricated using CMOS technology, which equates, inherently, to extremely low power
consumption. All maximize on-chip componentry for the
intended application in order to reduce the external component requirements to a minimum.
To facilitate acquaintance with Intersil products, a number
of AID converters are available in the form of low-cost Eval-

uation Kits. The Kits combine the specified converter with a
number of additional components required to assemble a
functional subsystem. They include components PC board
and appropriate assembly instructions.

Content:
AID Converter Systems
Digital Multimeter
Instrumentation
Bargraph
AID Converters
Display Type
ILP Type
Evaluation Kits
D/A Converters

Analog To Digital Converters
AID Converters
with Display Drivers

41/0 Digit LCD
ICL7129
7-Segment Displays
For High Quality Battery Operated Instruments

Integrating ND Converters are characterized by high inherent
accuracy, excellent noise rejection, non-critical associated components and low cost. They are relatively slow with conversion rates
up to 30 conversions per second. All Intersil integrating converters
provide fully precise Auto-Zero, Auto-Polarity (including ± null indicalion), single reference operation, very high input impedance. true
input integration over a constant period (for maximum EMI rejection).
fully ratiometric operation. overrange indication and a medium-quality
built-in reference.

Very high performance ND Converter for direct drive of multiplexed LCOs. Ideal for high-resolution, hand-held digital multi meters
and other battery powered (9V) instruments. Accuracy is better than
0.005% of full scale, with resolution down to 10/LV per count. Overrange and underrange outputs permit design of autoranging instruments with 10:1 range changing input. Instant continuity check gives
both visual indication and a logic-level output for enabling an external
audible transducer. Provisions for detection and indication of Low
Battery condition.

For 31/0 Digit LCD/LED
7-Segment Displays
30/4 Digit LCD
7-Segment Displays
ICL7139
For Low-Cost Autoranging Digital Multimeters ICL7149

These 3%-digit ND Converters contain all the necessary active
devices on a single CMOS integrated circuit. Included are AID Converters, 7-segment decoders, display drivers, a reference and a
clock. All feature auto-zero to less than 1OIL V, zero-input drift of less
than '/LVrC, input bias current of 10pA max., and rollover and linearity errors of less than one count. True differential inputs and reference provide wide applications versatility over a temperature range
from 0 to + 70°C.

These monolithic autoranging multi meter circuits always display
the results of a conversion on the correct range. Measure AC and
DC voltage, DC current and resistance in the following ranges:
DC Voltage - 400mV, 4V, 40V, 400V
AC Voltage - 400V (ICL7139)
(Optional ac circuit with 2 ranges (ICL7149))
DC Current - 4mA, 40mA, 400mA, 4A
Resistance - 4K, 40K, 400K, 4M
On-chip duplex display drivE!, includes three decimal points and 11
annunciators. Less than 20mW power dissipation provides 1000
hours typical battery life. Continuity output drives piezoelectric beeper. Guaranteed zero reading for 0 Volts input on all ranges.

101-Segment LCD Bargraph
A-D Converter

ICL7106/7116,ICL713617126
ICL7137-7107,ICL7117

ICL7106 ICL7116 For Liquid
Crystal
Displays

ICL7136 -

ICL7126-

Earlier version of iCL7136. Recommended for exact
replacement requirement only.

ICL7137 -

Low-power, direct drive ADC for commonanode, 7-segment LED displays. Requires
positive and negative 5V supply voltages,
with supply current of less than 200I'A. 0.1
to 4 conversions per second.

ICL7107-

ICL7107 - Earlier version ot ICL.7137. Recommended for
exact replacement requirements only.

ICL7117 -

Similar to ICL7137. but requires I.SmA
(max.) 01 supply current and provides up to
15 conversions per second. Hold Reading
allows indefinite retention of display reading,

ICL7182
For LED
Displays

The ICL7182 is a complete analog-to-digital converter that directly
drives a multiplexed liquid crystal display. Included are a chargebalance AID converter, a 2.56V bandgap reference, display decode
and driver, and a 50KHz oscillator. A complete analog bargraph
generator requires only the addition of an external display, two passive components and a 350/LA, 5V power source.

1-2

Direct drive; 0.1 to 15 conversions per
second; supply current = 1.BmA max.
Similar to above, but features a Hold
Reading input which allows indefinite
retention of a display reading
Low-power version of ICL71 06, but with
maximum supply current of only 100JLA
gives SOOO hours typical 9V battery life. 0.1
to 4 conversions per second.

IIU~UlL

DATA ACQUISITION
p,P Compatible AID Converters
Integrating

ICL71 04-14
ICL71 04-16
ICL8052

Intersi! integrating /LP-Compatible AID 'Converters contain
both monolithic versions and 2-chip sets, with up to 16-bit
resolution. All utilize CMOS processing for lowest power consumption, and all have a guaranteed accuracy of 1 count.

ICL8068-

4'1. Digit AID Converter
with Multiplexed BCD Output

ICL7135

Successive Approximation

This precision AID Converter is suitable for display applications as well as microprocessor and UART interface. Count
accuracy of ± 1 in 20,000 makes it ideal for the visual display
DVM/DPM market, while added functions such as Strobe,
Run/Hold, Busy, Overrange and Underrange allow operation
in more sophisticated systems. Chip contains all necessary
active devices except display drivers, reference and clock.
All outputs are TTL compatible.
12·Bit /LP·Compatible
AID Converter

Successive Approximation Converters are generally associated with high speed, ranging up to 100,000 conversions
per second. Allintersil Successive Approximation Converters
are /LP compatible.

8·Bit AID Converters
for 8080A MPU Interface

ADC0802
ADC0803
ADC0804

This Successive Approximation AID Converter was
designed to operate with the 8080A or Z-80 microprocessor
control bus via three-state outputs with no additional interfacing requirements, but permits easy interface to most other
microprocessors. Differential analog input range is 0 to 5V
with a single + 5V supply. With a conversion time of less than
100 /LS, it provides up to 8888 conversions per second with
a clock frequency of 640KHz.
ADC0802 Total unadjusted error = ± 1/2LSB
ADC0803 Total full-scale adjust error = ± 1/2LSB
ADC0804 Total unadjusted error = ± 1LSB

ICL7109

This monolithic 12-bit binary AID converter may be directly
accessed under control of two byte-Enable inputs, and a Chip
Select input, for a simple parallel-bus interface. A UART
handshake mode operates in conjunction with industry-standard UARTs to provide serial data transmission. Operates at
up to 30 conversions per second. Available in three temperature ranges: - 55°C to + 125°C, - 25°C to + 85°C, and O°C
to + 70°C.
14/16-Bit ,.P·Compatible
Two·Chip AID Converter Sets

14-BitADC
16-BitADC
Low input leakage current (30pA max.)
analog processing circuit.
Typical noise = 30/LV.
Low noise (2/LV typical) analog
processing circuit. Input leakage current
= 165pA.

ICL8052/ICL7104
ICL8068/ICL7104

14·Bit High·Speed
AID Converter

Available with 14-bit and 16-bit resolution, this twO-Chip set
performs the analog signal processing on one chip (ICL8052
or ICL8068) and the switching and digital functions on the
other (ICL71 04). A combination of chips may be ordered for
either 14-bit or 16-bit operation and for low-noise or lowleakage alternatives. All combinations, however, offer threestate, latched, binary outputs plus Polarity and Overrange.
All combinations operate over a temperature range of O°C to
+ 70°C.

ICL7115

With a conversion speed of 40/Ls (max), this 14-bit ADC
has a byte organized digital output for bus interface to 8 and
16-bit microprocessor systems. CMOS circuitry, thin-film
resistors and an on-Chip PROM calibration table combine to
achieve 13-bit linearity (without laser trimming) and a very
low (60mW) power diSSipation. Available in three temperature
ranges: O°C to + 70°C, - 25°C to + 85°C, and - 55°C to
+ 125°C.

1-3

DATA ACQUISITION
Digital to Analog Converters
Intersil supplies digital-to-analog converters (D/A converters) with a-bit, 10-bit, 12-bit, 14-bit and 16-bit resolution. All
are four-quadrant multiplying D/A converters using thin-film

Digital
Input

Type

Format

Settling Time
(To 0.05% FS)

resistors and CMOS circuitry for high accuracy and low power
dissipation. All are microcomputer compatible, with input protection against damage from electrostatic discharge.

Output
Current
(Max)

Gain

Power
Supply
I(Max)

Linearity% FS

Error

Linearity
Tempo

(Sulfix)

(%FS)

PPM/'C

Non

Gain

~

0.2% (J)
O.l%(K)
0.05% (L)

10-BIT
AD7520'
AD7530

Binaryl
Offsel
Binary

500 ns
(Typ)

±VREFA
10K!)

0.2% (J)
O.l%(K)
0.05% (L)

0.3%
(Max)

10
2

+15V
2mA

AD7533

Binaryl
Offset
Binary

600 ns
(Typ)

±VREFA
10Kll

0.2% (J)
O.l%(K)
0.05% (L)

1.4%
(Max)

10
2

+15V
2mA

AD7521,
AD7531

Binary/
Offset
Binary

500 ns
(Typ)

±VREFA
10Kll

0.2% (J)
O.l%(K)
0.05% (L)

0.3%
(Typ)

10
2

+15V
2mA

AD7541

Binaryl
Offset
Binary

1 I'S
(Max)

±VREFA
10Kll

0.02% (J)
0.01% (K)
0.01% (L)

0.3'%
(Max)

-

--

12-BIT

2

+15V
2mA

0.1% (J)
0.006% (K)
0.003% (L)

•AD7530 and AD7531 are identical to AD7520 and AD7521, respectively, except for output leakage current and feed-through specifications.

ICL7121
16-8it "P-Compatible
01 A Converter
This high-performance 16-bit D/A converter achieves
0.003% linearity without laser trimming by combining the
converter with a unique on-Chip PROM-controlled correction circuit. This insures long-term stability and accuracy
even over the full military temperature range. Silicon-gate
CMOS circuitry keeps the power dissipation to a very low
25mW.
Designed and programmed for bipolar operation, it can be
connected to provide a true 2's complement input transfer
function without any external resistors. Microprocessor bus
interfacing is eased by standard memory WRite cycle timing
and control signal use. The device is available in a 2a-pin
CERDIP package in both O°C to + 70°C, and - 55°C to
+ 125°C temperature ranges.

ICL7121 Example of Bipolar, Four Quadrant Operation

1-4

DATA ACQUISITION
AID Converter
Evaluation Kits
The following Evaluation Kits are available to permit rapid
assembly, testing and evaluation of specific AID converters.
Each Kit comes complete with a prewired printed circuit board
and all necessary components (except batteries) for a suitable demonstration circuit. Assembly and operating instruction are supplied.

ICL7136EVIKit

ICL7129EV/Kit

ICL7139EV/Kit

This Kit permits evaluation of the IntersillCL7129 4'/2 digit,
LCD, 7-segment display in a functional DC digital voltmeter
circuit. It includes the AID converter IC, a liquid crystal display,
a 120KHz crystal, a voltage reference IC and all necessary
passive components and hardware items.
ICL7139EV/Kit
ICL7106/07EV/Kit
ICL7136EV/Kit

This Kit uses the Intersil ICL7139 to build a complete 3%
digit autoranging multimeter, capable of directly measuring
voltage, current, and resistance. Included in the Kit are the
ICL7139 IC, circuit board, liquid crystal display, and all necessary passive components and hardware.

Intersil's ICL7136 is a low-power version of the 3V2 digit
LCD AID converters. This Kit contains all the components
necessary to build a battery-operated 3'12 digit panel meter.
It includes the AID converter IC, a circuit board, liquid crystal
display, passive components, and miscellaneous hardware.

ICL7182EV/Kit
With this Kit, the user can easily evaluate a 101 segment
LCD bargraph AID convetter using Intersil's ICL7182. Everything necessary to build the completed circuit is included in
the Kit: The ICL7182 IC, circuit board, 101 segment LCD,
passive components, and miscellaneous hardware.

ICL7106EV/Kit,ICL7107EV/Kit
To ease evaluation of these unique circuits, Intersil offers
kits which contain all the necessary components to build a
3V2 digit panel meter. Two kits are offered, the ICL7106EVI
Kit and the ICL7107EV/Kit. Both contain the appropriate IC,
a circuit board, a display (LCD for the ICL7106EV/Kit, LEDs
for the ICL7107EV/Kit), passive components, and miscellaneous hardware.

GRAPHICS
IM2110
256 X 12 Color Lookup
Table and DAC
The IM211 0 is designed specifically for color graphics, and
integrates a 256 x 12 color lookup table, three 4-bit DACs,
and a microprocessor interface.
The color lookup table is stored in a RAM and may be
written asynchronously by an 8- or 16-bit microprocessor.
Three overlay registers are provided for overlaying cursors,
grids, text, etc. The chip is capable of simultaneously displaying 256 out of 4096 colors at a 25 MHz rate, for a 640 x
480 non-interlaced display.
The IM2110 generates RS-343-A compatible red, green
and blue analog signals, and is capable of driving doublyterminated 75 n coaxial cables directly.
The circuit is available in a 40-pin plastic package and
operates over a temperature range of O°C to + 70°C.

elK

1-5

VDO

VAA

GND

POWER SUPPLY SUPERVISORY CIRCUITS

ICL7660S/ICL7662S
Voltage Converters
These voltage converters transform a positive (+) input
voltage from a power supply to a corresponding negative ( - )
output, resulting in complementary output voltages of - 1.5V
to - 12.0V for the ICL7660, and - 4.5V to - 20V for the
ICL7662. Only two non-critical external capacitors are
needed to perform the conversions. The converters can also
be connected as voltage doublers and will generate output
voltages of + 18.6V and 22.6V, respectively.
Available in two temperature ranges, O'C to 70'C and
- 55'C to + 125'C, and three packages, TO-99, 8-pin
MiniDIP (ICL7660S only) and SOIC.

Simple Negative Converter Configuration

ICL7663S
Programmable Micropower Voltage Regulators
The ICL7663 (positive) series regulators are low-power,
high-efficiency devices which accept inputs from 1.6V to 16V
and provide adjustable outputs over the same range at currents up to 40mA. Operating current is typically less than
4f,LA, regardless of load.
Output current sensing and remote shutdown are available,
thereby providing protection for the regulators and the circuits
they power.
The ICL7663 is available in 8-pin plastiC, TO-99 metal can,
CERDIp, and SOIC packages, in two temperature ranges O'C to + 70'C and - 25'C to + 85'C.

Basic Applications of ICL7663 as
Positive Regulator with Current Limit

ICL7667
Dual Power MOSFET Driver
The ICL7667 is a dual monolithic high-speed driver
designed to convert TTL level signals into high current outputs at voltages up to 15V. Its high speed and peak current
output enable it to drive large capacitive loads with high slew
rates and low propagation delays. With an output voltage
swing only millivolts less than the supply voltage and a maximum supply voltage of 15V, the ICL7667 is well suited for
driving power MOSFETs in high frequency switched-mode
power converters.
Available in commercial and military temperature ranges,
and in 8-pin plastiC DIP, SOIC, CERDIP and TO-99 metal
packages.

Direct Drive of MOSFET Gates

ICL7673
Automatic Battery Back-Up Switch

+ 5 VOLT ----'-I
PRIMARY
SUPPLY

The ICL7673 automatically switches from the main power
supply to a battery back-up supply in the event of power loss,
and back again when power is restored. Ideal for on-board
battery back-up for real-time clocks, timers, volatile RAMs,
or portable instruments. Available in 8-pin MiniDIP and TO-99
packages.

GND--+-----+-------ICL7673 Battery Backup Circuit

1-6

POWER SUPPLY SUPERVISORY CIRCUITS
ICL7665
Micropower Under/Over Voltage Detector
The ICL7665 contains two individually programmable voltage detectors on a single chip. Requiring only 3pA, typical,
for operation, the device is intended for battery-operated systems and instruments which require high or low voltage warnings, settable trip pOints, or fault monitoring and corrections.
Available in 8-lead CERDIP, MiniDIp, TO-99 metal can and
SOIC packages with a temperature range from O'C to 70'C.

Ifl1
Lhd_OETl
ICL7665 Functional Diagram
and Transfer Characteristics of Simple Threshold
Detector

ICL8211/1CL8212
Programmable Voltage Detector
These circuits consist of an accurate voltage reference, a
comparator and a pair of output buffer/drivers.
The ICL8211 provides a 7mA current limited output sink
when the voltage applied to the 'THRESHOLD' terminals is
less than 1.15 volts (the internal reference). The ICL8212
requires a voltage in excess of 1.15 volts to switch its output
on (no current limit). Both devices have a low current output
(HYSTERESIS) which is switched on for input voltages in
excess of 1.15V. The HYSTERESIS output may be used to
provide positive and noise free output switching using a simple feedback network.
Available in 8-lead MiniDip, TO-99 metal can and SOIC
packages, in commercial and rnilitary temperature ranges.

INPUT
~O~T,l.GE

IRECOMMENOEDAANGE!TO
5 VOLTS)

Voltage Level Detection with ICL821118212

ICL8069
Low Voltage Reference

ICL7677
Power Fail Detector

ICL8069 is a 1.2V temperature compensated voltage reference. It uses the band-gap principal to achieve excellent
stability and low noise at reverse currents down to 50pA
Applications include analog-to-digital converters, threshold
detectors, and voltage regulators. Its low power consumption
makes it especially suitable for battery operated equipment.
Available in TO-92 plastic and TO-52 metal packages with
O'C to 70'C and - 55'C to + 125'C temperature ranges
(metal only) and with temperature coefficients of 0.005 and

0.01/'C.

ICL7677 is a Power Fail Detector which can be incorporated either into the primary or the secondary side of a power
supply to give the fastest possible power-fail indication. On
the primary side, it can simultaneously monitor AC line voltage, the reservoir capacitor voltage, primary side current and
ambient temperature. On the secondary side, it can simultaneously monitor up to two DC voltages, one load current
and the ambient temperature. The circuit has an on-chip
bandgap-voltage reference to conveniently program the
detection thresholds.

ICL7675/1CL7676
Switched-Mode Power Supply Controller Set

ICL7680
5V to ± 15V Voltage Converter

The ICL7675/7676 two-chip set provides the necessary
control circuitry for regulation of an isolated flyback type
switching power supply. Specifically designed to operate in
this type of configuration, the Intersil controller chip-set is
trimmed to provide a regulated 5V output. The isolated flyback
converter is the most widely used configuration for switchedmode power supplies in 50W to 150W range because of its
simplicity. The chip-set features soft-start and power switch
over-current protection.

The ICL7680 is a simple boost-type switched-mode
converter/inverter chip using minimal external components
to convert + 5V to ± 15V regulated outputs. An internal
oscillator is user programmable to optimize efficiency for
various load conditions. The device features current limiting
protection together with external shut-down.

1-7

SPECIAL ANALOG FUNCTIONS
ICM7206
Touch·Tone Encoder

LP,

The ICM7206 is a 2-of-8 sinewave DTMF generator for use in
telephone dialing systems. Requires a 3.58 MHz crystal and will
operate with both 3x4 and 4x4 keypads. This low-cost circuit has a
high current bipolar output driver providing low harmonic distortion.
Supply voltage range is 3 to 6 volts with power dissipation of less
than 5.5mW at 5.5 volts. Single and dual tone capability.
Available in 16-pin plastic DIP with a temperature range from
- 40°C to + 85°C.

"DO

COL 1

ROW'

COL4

DISA8LE

Vss """'L..._ _•

esc IN

Pin Configuration

ICL8013
Four Quadrant Analog Multiplier
The ICL8013 is a bipolar, four-quadrant analog multiplier whose
output is proportional to the algebraic product of two input signals.
Feedback around an internal op-amp provides level shifting and can
be used to generate division and square root functions. A simple
arrangement of potentiometers may be used to time gain accuracy,
offset voltage and feedthrough performance.
Available in 1O-pin TO-l 00 metal package in both commercial and
military temperature ranges.

OUTPUT

ICL8013 Functional Diagram

ICL8038
Precision Waveform GeneratorlVoltage Controlled
Oscillator

SINE WAVE
ADJUST

SINE WAVE
OUT
TRIANGL.E

The ICL8038 Waveform Generator is capable of producing high
accuracy sine, square, triangular, sawtooth and pulse waveforms
with a minimum of external components. The frequency (or repetition
rate) can be selected externally from .001 Hz to more than 300KHz
using either resistors or capacitors, and frequency modulation, and
sweeping can be accomplished with an external voltage.
The 14-pin CERDIP package is available with O°C to + 70°C, and
- 55°C to + 125°C temperature ranges.

l'

OUT

DUTY
CYCLE
FREQUENCY
ADJUST

5

FM
BIAS

10

6~~~gITOR

9

~~~ARE WAVE

8

i~~~EEP

'----'
Pin Configuration

AD590
2·Wire, Current·Output Temperature Transducer
The AD590 is a 2-wire integrated-circuit temperature transducer
which produces an output current proportional to absolute temperature. The device acts as a high impedance constant current regulator, passing 1"AI"K for supply voltages between + 4V and + 30V.
Laser trimming of the chip's thin-film resistors is used to calibrate
the device to 298.2 "A output at 298.2°K ( + 25°C).
The AD590 could be used in any temperature-sensing application
between - 55°C and + 150°C in which conventional electrical temperature sensors are currently employed.
Plastic (TO-92) packaged device covers temperature ranges from
O°C to + 70C; Metal packaged device (TO-52) covers - 55°C to
+ 150°C range. With slope and offset trimming circuit it is possible
to adjust devices to give less than 0.1 % error over the temperature
range from O°C to 90°C.

R,
Sk!l

AD590 Slope and Offset Trimming Circuit

1-8

_O~OIl

AMPLIFIERS
Special Purpose Amplifiers

Content:

ICL420/421
± 15V Chopper Stabilized
Operational Amplifier

Special Purpose Amplifiers
Instrumentation Amplifiers
Log/Antilog Amplifiers
Drive Amplifier for Power Transistors
Operational Amplifiers
General Purpose
Low Power
Low Input Offset Voltage
Low Input Bias Qurrent

These chopper-stabilized CMOS operational amplifiers are
designed for signal conditioning, precision and instrumentation type applications. They offer a wide input and operating
supply range, allowing virtual plug-in replacements for conventional lower-performance amplifiers, requiring only two
additional external capacitors.
The ICL420 (8-pin) and ICL421 (14-pin) devices draw a
maximum supply current of 2 mA and are available in all
temperature ranges.
ICL7605/7606
Commutating Auto-Zero (CAZ)
Instrumentation Amplifier, CMOS
The ICL7605/ICL7606 CMOS com mutating auto-zero
(CAZ) instrumentation amplifiers are intended for lowfrequency operation in applications such as strain gauge
amplifiers which require voltage gains from 1 to 1000 and
bandwidths from DC to 10Hz. Since the CAZ amp automatically corrects itself for internal errors, the only periodic adjustment required is that of gain, which is established by two
external resistors. This, combined with extremely low offset
and temperature coefficient figures, makes the CAZ instrumentation amplifier very desirable for operation in severe
environments (temperature, humidity, toxicity, radiation, etc.)
where equipment service is difficult.
Available in three temperature ranges.

Features:
• Input Offset Voltage - 2p,V
• Input Offset Voltage Drift - 0.2p,V/Year
• Common Mode Input Voltage Range - 0.3V Above
Supply Rail
• Common Mode Rejection Ration -100 dB
• Operates at Supply Voltages As Low As ± 2V
• Short Circuit Protection On Outputs
• Compensated (ICL7605) or Uncompensated (ICL7606)
Versions

ICL8048/ICL8049
Log/Antilog Amplifier
The 8048 is a monolithic logarithmic amplifier capable of
handling six decades of current input, or three decades of
voltage input. It is fully temperature compensated and is nominally designed to provide 1 volt of output for each decade
change of input. For increased flexibility, the scale factor,
reference current and offset voltage are externally adjustable.
The 8049 is the antilogarithmic counterpart of the 8048; it
nominally generates one decade of output voltage for each
1 volt change in the input.

Features:

• v.% Full Scale Accuracy
•
•
•
•
•

Temperature Compensated for O·C to + 70·C
Scale Factor 1V/Decade, Adjustable
120dB Dynamic Current Range (8048)
60dB Dynamic Voltage Range (8048 & 8049)
Dual JFET-Input Op-Amps

ICL8063
Power Transistor Driver/Amplifier
Features:

The ICL8063 is a monolithic transistor driver and amplifier
primarily intended for driving complementary output stages.
The ICL8063 takes the output levels (typical ± 11 V) from
an op amp and boosts them to ± 30V to drive power transistors, (e.g. 2N3055 (NPN) and 2N3789 (PNP)). The outputs
from the ICL8063 supply up to 100mA to the base leads of
the external power transistors.

• When Used in Conjunction with General-Purpose Op
Amps and External Complementary Power Transistors, System Can Deliver >50 Watts to External Loads
• Built-In Safe Area Protection and Short-Circuit
Protection
• Built-In ± 13V Regulators to Power Op Amps or Other
External Functions

1-9

AMPLIFIERS
Operational Amplifiers
Intersi! offers a range of single and multiple monolithic operational amplifiers suitable for a number of specific applications categories. Included are bipolar Super-Beta and
Chopper-Stabilized CMOS devices for very low input offset
requirement, a selection of PMOS and JFET-input devices

for very low bias currents, as well as general-purpose and
low-power amplifiers for a broad range of applications.
All monolithic operational amplifiers are available in a variety of packages and in die form.

Operational Amplifiers: General Purpose

Description

ICL7611

CMOS, Selectable 10

ICL8007M
ICL8007C

JFET Input Op-Amp
JFET Input Op-Amp

o to +70
-55 to + 125
-55 to + 125
o to +70

2,5,15

50

1.6

1.4

INT

±9

20
50

20
50

6
6

1.0
1.0

INT
INT

±18
±18

2,5,15

50

0.16

0.48

INT

±9

20
50

20
50

6
6

1.0
1.0

INT
INT

±18
±18

o to +70
-55 to + 125
-55 to + 125
o to +70

INT
INT
INT
INT

010+70&
-55 to + 125
-5510 + 125
010 +70

DUALS
ICL7621

CMOS, Fixed 10

ICl8043M
ICL8043C

JFET Input Op-Amp
JFET Input Op-Amp

TRIPLES
CMOS, Selectable 10

CMOS, Fixed 10

Low Power

Type

Description

SINGLES
ICL7611
ICL7612
ICL8021M
ICL8021C

CMOS,
CMOS.
Bipolar,
Bipolar,

Selectable 10
Extended CMVR
Selectable 10
Selectable 10

10
10
30
30

±9
±9
±18
±18

TRIPLES
CMOS, Selectable 10
Triple 8021 M
Triple 8021 C

CMOS, Fixed 10

1010

2,5,15
2,5,15
3
6

0.05
0.05
20
30

0.044
0.044
0.27
0.27

AMPLIFIERS
Operational Amplifiers: Special Purpose
Low/Ultra-low Input Offset Voltag~

Description

SINGLES
ICL7650C
ICL76501
ICL7650M
ICL7652C
ICL76521
ICL7652M

CMOS, Chopper-stabilized
CMOS, Chopper-stabilized
CMOS, Chopper-stabilized
Low-noise 7650C
Low-noise 76501
Low-noise 7650M

±8
±10
±20
±7
±10
±50

±0.02
±0.02
±0.03
±0.01
±0.02
±0.1

50
50
20
4.0
50
4.0
0.1
0.01

0.5
0.5
0.5
0.2
0.5
0.2

50

100
100
100
100
100
100

20
50
500
30
30
500

2.0
2.0
2.0
0.5
0.5
0.5

±9
±9
±9
±9
±9
±9

o to + 70
-25 to +85
-55 to + 125
o to + 70
-25 to +85
-55 to + 125

Oto+70&
-55 to +125
-55 to + 125
-55 to +125
o to + 70
a to + 70
-25 to +85
-25 to +85

Low Input Bias Current

Description

SINGLES
ICL7611
ICL7612
ICLS007M
ICLS007AM
ICLS007C
ICLS007AC
ICHS500
ICHS500A

CMOS, Selectable IQ
CMOS, Extended CMVR
JFET Input Op-Amp
JFET Input, Low Bias
JFET Input Op-Amp
JFET Input, Low Bias
PMOS Input
PMOS Inpuf, Low Bias

-

2,5,15
2,5,15
20
30
50
30
50
50

1.4
1.4
1.0
1.0
1.0
1.0
0.7
0.7

INT
INT
INT
INT
INT
INT
INT
INT

±9
±9
±IS
±IS
±IS
±18
.±o18
±18

0.5

2,5,15

0.48

INT

±9

-

DUALS
ICL7621

CMOS, Fixed IQ

a to

+ 70
&

ICL8043M
ICL8043C

JFET Input Op-Amp
JFET Input Op-Amp

20
50

0.5
0.5

20
50

1.0
1.0

INT
INT

±18
±18

50

0.5

5,10,20

1.4

INT

±9

-55 to +125
-55 to + 125
a to + 70

TRIPLES
CMOS, Selectable IQ

QUADS
ICL7641

CMOS, Fixed IQ

o to

+ 70
&

ICL7642

CMOS, Fixed IQ

50

0.5

5,10,20

1-11

0.044

INT

±9

-55 to +125

ANALOG SWITCHES AND MULTIPLEXERS
Content:
General Purpose Analog Switches
Drivers for FET Switches
Low Cost, Virtual Ground Switch Family
RFlVideo Switch Family
Multiplexers

General Purpose Analog Switches
Intersil offers two general-purpose switch lines, each with
various switch configurations. The first consists of bipolar
drivers controlling an associated set of field-effect switching
transistors in a multi-Chip structure that provides a wide
choice of parameters at low cost. The second is a monolithic
CMOS structure capable of improved performance and

greater reliability. All have break-before-make switch action.
All switches are available in commercial and military temperature ranges. Package options include Plastic DIP, CERDIP, Flat Pack and Metal Can (not all options are available
for all device types).

General Purpose Analog Switches
Switch Parameters
Switch
Family

Special
Features

Switch
Type

RDS(ON) IID(OFF) I
tON
I tOFF I Analog Voltage Range
(n Max)
(nA Max)
(ns Max) (ns Max)
(VSUPPLY = ±15V)

Multichip
DG123-125

Inverting/non-inverting logic
inputs

DG126-154
DG139-164

Dual Channel
Single Channel

DG180-191

Mature, Industry-standard switch,
JAN3851 0 Approved

PMOS

600

4

300

1000

-

N-JFET

10
15
30
50
80

10
10
1
1
1

tOOO
1000
600
600
600

2500
2500
1600
1600
1600

-

N-JFET

10
30
75

10
1
1

300
150
250

250
130
130

-7.5 to +15
-7.5 to +15
-IOta +15

2.0
0.5

250
450

200
250

-15to +15
-15to +15

Monolithic
DGM181-191

Monolithic replacement for
DG180 family

CMOS

50
75

DG200/201

Industry-standard low cost

CMOS

70/80

2.0

1000

500

-15to +15

DG211
DG212

Inverting
Noninverting

CMOS

175

5.0

1000

500

-15to +15

DG300A-303A

TTL compatible, low power

CMOS

50

1.0

300

250

-15to +15

IH311
IH312

High Speed Inverting
Noninverting

CMOS
CMOS

175

100

300

150

-15to +15

IH5040-47
IH5048-51
IH5052-53

Low quiescent current
Low RDS(ON)

CMOS

75
40
75

1.0
1.0
1.0

750
500
500

350
250
250

-IOta +10
-IOta +10
-11 to +11

IH5140-45

High speed, low power, low
leakage

CMOS

50

0.5

100

75

-11 to +11

IH5148-51

Low RDS(ON), high speed, low
power

CMOS

25

0.5

250
350
500

200
250
250

-14to+14

Separate Driver/Switch Combinations
IIH6201

I TTL level translator/driver

IIH401/A

I Low charge injection switch

I N-JFET I
I

I

30
30/50

I
I

0.5

I 50 (Typ) 1150 (Typ) I

15 pop (Min)

0.5

I 50 (Typ) 1150 (Typ) I

20 pop (Min)

Drivers for FET Switches

Output Swing

Monolithic bipolar drivers convert low-level positive logic
to high-level positive and negative voltages necessary to
drive FET switches.

1-12

Type

Number of
Channels

Positive
(V Max)

Negative
(V Max)

tON
ns
Max

tOFF
ns
Max

D123
D125
D129
IH6201

6TTUDTL
6 TTL
4 TTUDTL
2 TTL

VSupply
VSupply
VSupply
+14.0

-19.7
-19.7
-19.3
-14.0

250
250
250
200

400-800
400-800
1000
300

ANALOG SWITCHES AND MULTIPLEXERS
Switch Configurations

6

:

7

:

~I

8

~6"--_ _-<>O

~

o

()"'I"'~

I

~

Switch Configuration (Diagram)

SPST
(1)

I

Dual

SPST
(2)

I

Quad

SPST

I

4PST
(4)

(3)

I

Five

SPST

I

SPOT
(6)

(5)

I

Dual

SPOT
(7)

I

DPST
(8)

I

Dual

DPST

I

DPDT

(9)

(10)

OG140
OG153
OG129
OG154
OG126

OG145
OG163
OG139
OG164
OG142

OG123
OG125
OG141
OG151
OG133
OG152
OG134

OG146
OG161
OG144
OG162
OG143

OG180
OG181
OG182

OG186
OG187
OG188

OGM182
OG200

OG189
OG190
OG191

OG183
OG184
OG185

OGM190
OGM191

OGM184
OGM185

OG303A

OG302A

OG201
OG211
OG212

OG301A

OG300A
IH311
IH312

IH5040

IH5041
IH5048
IH5052/53

IH5140

IH5043
IH5051

IH5044

IH5045
IH5049

IH5142

IH5143

IH5144

IH5145

IH5150

IH5151

IH5042

IH5047

IH5050

IH5141
IH5148

IH5149

IH401/A

I

1-13

IH5046

Analog Switches and Multiplexers
Virtual GroundSw,tches, JFETs (P·Channel)

1H5017/5018

Each package contains up to four channels of analog gating
designed to eliminate the need for extemal drivers. The oddnumbered devices are designed to be driven directly from
TTL open-collector logic (15V). Each channel simulates a
SPOT switch. The parts are intended for high-performance
multiplexing and commutating use. All have turn-on/turn-oll
times of 500 ns and a leakage current (10(011» of 0.2 nA.

+i}?4=;
.
I

(12)

I

,

'"

IH5019/5020

~*S.~.'
----+-0:;"
o,,~

Switch Configuration
SPST

Dual
SPST

Triple
SPST

Quad Special Switch rDS(on)
SPST Features Typa (0 Max)

IH5021 IH5017 IH5013 IH5009 Common
IH5022 IH5018 IH5014 IH5010 Output
IH5023 IH5019 IH5015 IH5011 Separate
IH5024 IH5020 IH5016 IH5012 Output

P.JFET

100
150

,,
0"

Examples of Common Output and Separate Output
Switch Configurations

100
150

./:f

RFNideo Switches, CMOS
Designed for high-frequency operation, these switches utilize a "T" configuration where a shunt switch is closed when
the switch is open. This provides superior isolation between
input and output and greatly improves performance in the
video and RF region. Switch attenuation varies less than 3 dB
from dc to·100 MHz. Available in three (commercial and military) temperature ranges and in 14-pin plastiC DIP and 10-pin
T0-100 metal package.

CIRCUIT OF SWITCH CHANNEL
SWITCH
SOURCEo------ 7V), the
COMMON voltage will have a low voltage coefficient
(0.001 %N), low output impedance ('" 15n), and a temperature coefficient typically less than 80ppml'C.
The limitations of the on-chip reference should also be
recognized, however. With the 7107, the internal heating
which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastiC parts are poorer in this respect than ceramic.
The combination of reference Temperature Coefficient
(TC), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25 p.V to
80p.Vp-p. Also the linearity in going from a high dissipation
count such as 1000 (20 segments on) to a low dissipation
count such as 1111 (8 segments on) can suffer by a count or
more. Devices with a positive TC reference may require
several counts to pull out of an overrange condition. This is
because overrange is a low dissipation mode, with the three
least significant digits blanked. Similarly, units with a negative TC may cycle between overrange and a nonoverrange
count as the die alternately heats and cools. All these problems are of course eliminated if an external reference is
used.
The 7106, with its negligible dissipation, suffers from
none of these problems. In either case, an external reference can easily be added, as shown in Figure 5.

v·

TEST
The TEST pin serves two functions. On the 7106 it is
coupled to the internally generated digital supply through a
soon resistor. Thus it can be used as the negative supply
for externally generated segment drivers such as decimal
points or any other presentation the user may want to include on the LCD display. Figures 6 and 7 show such an
application. No more than a 1mA load should be applied.

y.

1Mu

7106

TO LCD

INTERSIL
1T17SO

DECIMAL POINT

v'

0335-7

Figure 6: Simple Inverter for Fixed Decimal Point

8.1Ik1l

7106/7107

7106/7107

l'Z

ICllOl9

y'
COMMON

7106

v(01

8P

-(
POINT
&eLECT

(01

0335-6

Figure 5: Using an External Reference
TEST

0335-8

Figure 7: Exclusive 'OR' Gate for
Decimal Point Drive
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE ANO SHALL BE IN LIEU OF ALL OTHER WARRANTIeS. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bun characterized but are not tesfBd.

2-5

n
I'"

......

0

~

n
I'"
...

0
...

•

ICL 71 08/ICL 7107
DISPLAY FONT
C:~3'{S6'89

Figure 8: Digital Section 7106

0336-9

0123"156789

--------,

I
I

I

I

I
I
I

I
I

,
I

,,
I

I

I
I

I

.,,,
I

--~~----~~--~------_+--_r--r_~----------~~
37 I TEST

IIOOU

L-__
D8C1

I

-+~=-~--_4~------------------------~~--~.,~1
D'~~
3!. ____________________________ ..J GROUND

Dec.

Dies

Figure 9: Digital SectIon 7107

0335-10

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY DSLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.
Nm'F:AH _ _ ha.. _ _ bu/.,.not_

2·6

ICL 71 06/ICL 7107
The second function is a "lamp test". When TEST is
pulled high (to V +) all segments will be turned on and the
display should read - 1888. The TEST pin will sink about
10mA under these conditions.
Caution: on the 7106, in the lamp test mode, the segments have a constant DC voltage (no square-wave) and
may burn the LCD display if left in this mode for several
minutes.

The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
three convert-cycle phases. These are signal integrate
(1000 counts), reference de-integrate (0 to 2000 counts)
and auto-zero (1000 to 3000 counts). For signals less than
full scale, auto-zero gets the unused portion of reference
deintegrate. This makes a complete measure cycle of 4,000
counts (16,000 clock pulses) independent of input voltage.
For three readings/second, an oscillator frequency of
48kHz would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz,
33%kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 66% kHz, 50kHz,
40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50 and 60Hz (also 400 and
440Hz).

DIGITAL SECTION
Figures 8 and 9 show the digital section for the 7106 and
7107, respectively. In the 7106, an internal digital ground is
generated from a 6 volt Zener diode and a large P channel
source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency
divided by 800. For three readings/second this is a 60Hz
square wave with a nominal amplitude of 5 volts. The segments are driven at the same frequency and amplitude and
are in phase with BP when OFF, but out of phase when ON.
In all cases negligible DC voltage exists across the segments.
Figure 9 is the Digital Section of the 7107. It is identical to
the 7106 except that the regulated supply and back plane
drive have been eliminated and the segment drive has been
increased from 2 to 8 mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19)
must sink current from two LED segments, it has twice the
drive capability or 16mA.
In both devices, the polarity indication is "on" for negative analog inputs. If IN LO and IN HI are reversed, this
indication can be reversed also, if desired.

COMPONENT VALUE SELECTION
Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 100,..A of quiescent current. They can
supply 20,..A of drive current with negligible non-linearity.
The integrating resistor should be large enough to remain in
this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 2 volt full scale, 470kO is near
optimum and similarly a 47kO for a 200.0 mV scale.

Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing (approx. 0.3 volt from either supply). In the 7106 or the 7107, when the analog
COMMON is used as a reference, a nominal ± 2 volt full
scale integrator swing is fine. For the 7107 with ±5 volt
supplies and analog COMMON tied to supply ground, a
± 3.5 to ± 4 volt swing is nominal. For three readings/ second (48kHz clock) nominal values for CINT are 0.22,..F and
0.10,..F, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing.
An additional requirement of the integrating capacitor is
that it must have a low dielectric absorption to prevent rollover errors. While other types of capacitors are adequate
for this application, polypropylene capacitors give undetectable errors at reasonable cost.

System Timing
Figure 10 shows the clocking arrangement used in the
7106 and 7107. Three basic clocking arrangements can be
used:
1.
An external oscillator connected to pin 40.
2.
A crystal between pins 39 and 40.
3.
An R-C oscillator using all three pins.

I

710117107

I

I

:

I
I
I

TO
:
COUNTERt

I

I

I

I
I

I
I

L _______ _
I

3,!1________

~

I

________ J

Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence
on the noise of the system. For 200mV full scale where
noise is very important, a 0.47,..F capacitor is recommended. On the 2 volt scale, a 0.047,..F capacitor increases the
speed of recovery from overload and is adequate for noise
on this scale.

EXTERNAL
OSCILLATOR
TEST (7101)
OlGND(7107)

0335-11

Figure 10: Clock Circuits

INTERSIL·S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values hSV6 b6en characterized but are not tested.

2-7

•

.O~OIl.

S
... ICL7106/ICL7107

...

d
~

o

...
...

d_

In fact, in selected applications no negative supply is required. The conditions to use a single + 5V supply are:
1.
The input signal can be referenced to the center of
the common mode range of the converter.
2.
The signal is less than ± 1.5 volts.
3.
An external reference is used.

Reference Capacitor
A 0.1).'F capacitor gives good results in most applications. However, where a large common mode voltage exists
(I.e. the REF LO pin is not at analog COMMON) and a
200mV scale is used, a larger value is required to prevent
roll-over error. Generally 1.0).'F will hold the roll-over error
to 0.5 count in this instance.

TYPICAL APPLICATIONS

Oscillator Components

The 7106 and 7107 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatility of these AID converters.

For all ranges of frequency a 100kO resistor is recommended and the capacitor is selected from the equation
0.45
f='RC' For 48kHz clock (3 readings/second), C= 100pF.

Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is: VIN = 2VREF. Thus, for the 200.0mV and
2.000 volt scale, Vref should equal 100.0 mV and 1.000 volt,
respectively. However, in many applications where the AID
is connected to a transducer, there will exist a scale factor
other than unity between the input voltage and the digital
reading. For instance, in a weighing system, the designer
might like to have a full scale reading when the voltage from
the transducer is 0.682V. Instead of dividing the input down
to 200.0mV, the designer should use the input voltage directly and select VREF=0.341V. Suitable values for integrating resistor and capacitor would be 120kO and 0.22).'F.
This makes the system slightly quieter and also avoids a
divider network on the input. The 7107 with ± 5V supplies
can accept input signals up to ±4V. Another advantage of
this system occurs when a digital reading of zero is desired
for VIN*O. Temperature and weighing systems with a variable tare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset
voltage between COMMON and IN LO.

71"
'-'

To pin 1
40
011(:1
OSC2
011(:'
TEST

l00Kn
Sel VREF'" l00.OnIY

/

1000F

REF HI

REFLO
CREF
C REF
COMMON

1KU

Do.1p.F

22Kn

lMn

INHI
INLO

+
IN

_".OI,F

-

O.47~F

AlZ
BUFF
INT
y-

.7Kn

0.22 F

~tV

T

O,
C,
ITO DISPLAY

A3
0,
B'

f---

TO BACK PLANE

21

0335-13

Figure 12: 7106 using the internal reference_
Values shown are for 200_0 mV full scale,
3 readings per second, floating supply
voltage (9V battery)_

7107 Power Supplies
The 7107 is designed to work from ±5V supplies. However, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors, and an
inexpensive I.C. Figure 11 shows this application. See
ICL7660 data sheet for an alternative.

0335-12

Figure 11: Generating Negative Supply
from +5V

INTER$IL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical va//JfJS havs been characterized but 8f9 not tested.

2-8

IIlD~OIL

ICL 71 06/ICL 7107

n
r-

......
o
GI

"07
~

To,," ,

7107

40
OIC'
01C2
ole 3
TEST
AIFHI
RIFLO
C REF

C REF
COMMON

'-'

100Kn
. ., VREF '" 100.OnI.V

.00;..

,/
.'A

DO"J,.tF

22KU

IN HI

• •OlJ..tF

.,#"

O.

Afl

47KlI

BUFF

INT
VG,
e,
A,
G,
GND

,
,,
,

!

~ TO DISPLAV

i
2'

. --------- --- -----_.

OND

710117107

osc 1
OSC 3
TEST
REF HI
REF LO
C REF

C REF

••

Afl
INT
VG,
e,

A:o
G,
GND

":"

To pin 1
40

.....
p ..,

100KH

OSe2
OSC 3

l00Ktl

'Kl! ,

At,

REF HI

/

REF LO

10Kn

.~,

'.~',;.

1

C REF
v+

C REF
COMMON
IN HI
INLO

.... •2V (leL8069)
lMI1

0.47/.1F ..
47KH

0.22 F

,

iTO DISPLAY

'"

:I

25KH

V+
24Kn

+
IN

.047JlF

...:-

470Kn

0.221/oF

V-

iTO DISPLAV

A:o

:

/

.'A

1Mn

INT
VG,
e3

V-

SttVREF'" 1.ooov

• •011/0'

BUFF

I
I
I

:I

DO,'J..tF

Afl

IN

1Ip.0l"F

....

'

TEST

Set VREF = too.OmY

IHHI

BUFF

h

'-' OSC'

COMMON
INLO

f TO DISPLAY
I

Figure 15: 7107 with Zener diode reference.
Since low T.C. zeners have breakdown voltages
- 6.aV, diode must be placed across the total
supply (10V). As in the case of Figure 15, IN LO
may be tied to either COMMON or GND.

To pin 1

OSC2

-5V

0335-16

0335-14

'-'

0.22J..tF

21

Figure 13: 7107 using the Internal reference.
Values shown are for 200.0mV full scale, 3
readings per second. IN LO may be tied to either
COMMON for Inputs floating with respect to
supplies, or GND for single ended inputs. (See
discussion under Analog COMMON.)

7107

41KII

G'p:
e'l=
A'I=
G'I=

-=-

IN

O.47j.1F ...

INT
V'

-5V

_IV

'~K" '.:l ~ •••Y

.,OlJ,.tF

BUFF

••22,F

\..,{
1KIl

...

1oo.OmY

lM11

INHI
INLO
All

IN

Set YREF

DO""[

COMMON

+

.....

100Kli

C REF

,Mn

INLO

40
OIC'
ole 2
OSC3

TlST
AEF HI
RIFLe
e AEF

+5V

tKH

5r......
o

To 1M" 1

OP/GND

21~-------------- .J

2'

0335-17

Figure 16: 710617107: Recommended
component values for 2.000V full scale.

0335-15

Figure 14: 7107 with an external band-gap
reference (1.2V type). IN LO is tied to COMMON,
thus establishing the correct common mode
voltage. If COMMON is not shorted to GND, the
input voltage may float with respect to the
power supply and COMMON acts as a preregulator for the reference. If COMMON is
shorted to GND, the input is single ended
(referred to supply ground) and the preregulator is over-ridden.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been chBracterizsd but are not tested.

2-9

•

..
......

:; ICL7106/ICL7107

()

..~...
o

~

~

OSCl

'-./

'0
s.t~REF

,AlA - "

REFLO
C REF
C REF F P O I .
COMMON
IN HI
INlO

,A

DO.,••L

IN HI

100KJl

~"K"

471<11

lUFF
INT
V-

0.22 ... '

a,

0.22 F

C,
A,
G,

I TO DIS'LA.

"'

SNK:on HPN
UPS 3704 01

IintH.,

hti----~

22OK1I

\HfoadJu.t

0 ..17... '

IoIZ

IN

G'I=

-

"'---

..:.,9Y

~

ITODIS.LA.

I-- -

TO BACK PLANE

21

GND

0335-20

21

Figure 19: 7106 used as a digital centigrade
thermometer. A silicon diode-connected
transistor has a temperature coefficient of
about - 2mY
Calibration is achieved by
placing the sensing transistor in ice water and
adjusting the zeroing potentiometer for a 000.0
reading. The sensor should then be placed in
boiling water and the scale-factor potentiometer
adjusted for 100.0 reading.

0335-18

Figure 17: 7107 operated from single +5Y
supply. An external reference must be used in
this application, since the voltage between Y+
and Y- is insufficient for correct operation of
the internal reference.

7107

~

1MO

,Ol~F-.

INlO

--<>

47KI1

e'F
A'F
G'F

/'

1 Kn

COMMON

~1.2V(ICL80")
1M!1
• .01 ... F

~fllClofactj"'t

lOOp.

TEST
REF HI
REFLO
CAEF
C REF

+5V

lKn • .,,'0K,iT 15K"

0.47,,'

A/Z
BUFF
INT
V-

100KII

Olel

100.OmY

,

100pF

REF HI

OSCI
OSC2

l00Ku

OSC 2

ose3
TEST

To pin 1
'0

710.

To pin 1

7107

rc.

v+

To pin 1

40
OSCl
OSC2
OSe3
TEST

1DOKn

100pF

REF HI
AEF LO
C REF
C REF

COMMON
INHf
IN LO

A/Z
BUFF

INT
VG,

c,

A,
Cl:l
GND

.47j.1F
47KII

O.22/.1F

I
1TO DISPLAV

0335-19

Figure 18: 7107 measuring ratiometric values of
Quad Load Cell. The resistor values within the
bridge are determined by the desired sensitivity.

0335-21

Figure 20: Circuit for developing Underrange
and Overrange signals from 7106 outputs.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CCNDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but 8r6 not tested.

2-10

ICL 71 06/ICL 7107

-

-

v+

D.

"'" o.ci

TEST

C.

R.,HI

A.

_LO

CR.,

O'

I'
D.

Vee

111en

.
.
.

C2

CRI'

CDIIIION
INHI

AI
FI

.INLO

INT

DS

-

A016
A017
A018

v-

V-

Go
Co

...

Fa

A14

POL

APPLICATION NOTES

AIr

lun

es

..

..

o.c.
o.cs

••
••

To

al components required, then wiring a breadboard, can often cause delays of days or sometimes weeks. To avoid this
problem and facilitate evaluation of these unique circuits,
Intersil is offering a kit which contains all the necessary
components to build a 3Yz-digit panel meter. With the help
of this kit, an engineer or technician can have the system
"up and running" in about half an hour•
Two kits are offered, the ICL710SEVIKIT and the
ICL7107EVlKIT. Both contain the appropriate IC, a circuit
board, a display (LCD for 7106EVlKIT, LEOs for 7107EVI
Kin, passive components, and miscellaneous hardware.

Go

OND

A023

21

A032

or 74C10

A046

0335-22

Figure 21: Circuit for developing Underrange
and Overrange signals from 7107 outputs. The
LM339 Is required to ensure logic compatibility
with heavy display loading.

A052

"Selecting AID Converters", by David Fullagar.
"The Integrating AID Converter", By Lee Evans.
"Do's and Don'ts of Applying AID Converters", by
Peter Bradshaw and Skip Osgood.
"Low Cost Digital Panel Meter Designs", by David
Fullagar and Michael Dufort.
"Understanding the Auto-Zero and Common Mode
Performance of the ICL710S/7/9 Family", by Peter
Bradshaw.
"Building a Battery-Operated Auto Ranging DVM
with the ICL7106", by Larry Goff.
"Tips for Using Single-Chip 3Va-Digit AID Converters", by Dan Watson.

7106/7107 EVALUATION KITS
After purchasing a sample of the 710S or the 71 07, the
majority of users will want to build a simple voltmeter. The
parts can then be evaluated against the data sheet specifications, and tried out in the intended application. However,
locating and purchasing even the small number of addition-

7101

.

To pin 1

=~LJo_"""",,'_IIOKI~1

Scale lactor HI""
(VAeF ::. 1QOmY lor AC to RUI)

OIC S 0-..".=,It--...J

TI.T~:::::~===:-:;Y
RI.HI[

RIF LOO--"'""1r-"VIN+'V\I\r-4
CRIF
COMMON~~~~~~~r:t:=~~~j:~~~,-~~~3l~Ej~
IN~~

ACIN

CRI.

IN HI

..7.'

__

-+~

O.22~F

Bun Lr_"""""4,,,7K..n...

'::~=~~~a~F~-L___~~t:=::~::::::::::::::====~_~
C,

::
...

}

TO DI'PLAY
TO BACK PLANt

0035-23

Figure 22: AC to DC Converter with 7106. TEST Is used as a common mode reference level to ensure
compatibility with most op-amps.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OSUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANnES. EXPRESS. IMPUED OR STATUTORY. INCLUDING THE IMPLIED WARRANnES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typIc8I values have bBsn chsracterlzeKJ but BTS not fBsl8d.

2-11

•

...~
...
U

ICL7106/ICL7107

too

=::.
G

...otoo

2

0335-24

Figure 23: Display Buffering for increased drive current. Requires four DM7407 Hex Buffers. Each buffer is
capable of sinking 40 mAo

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANnES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARnCULAR USE.

NOTE: AU typical vsJuss have bssn _terlzsd

but.,. not

tostsd.

2-12

D~DlLe......

ICL7116/7117
3%-Digit LCD/LED
Single-Chip A/D Converter
with Display Hold

.........
0)

......

.....

GENERAL DESCRIPTION

FEATURES

The Intersil ICL7116 and 7117 are high performance, low
power 3-% digit AID converters. All the necessary active
devices are contained on a single CMOS I.C., including seven segment decoders, display drivers, reference, and a
clock. The 7116 is designed to interface with a liquid crystal
display (LCD) and includes a backplane drive; the 7117 will
directly drive an instrument-size light emitting diode (LED)
display.
The 7116 and 7117 have almost all of the features of the
7106 and 7107 with the addition of a HoLD Reading input.
With this input, it is possible to make a measurement and
then retain the value on the display indefinitely. To make
room for this feature the reference input has been referenced to Common rather than being fully differential. These
circuits retain the accuracy, versatility, and true economy of
the 7106 and 7107. They feature auto-zero to less than
1O,...V, zero drift of less than 1,...VI'C, input bias current of
10pA maximum, and roll over error of less than one count.
The versatility of true differential input is of particular advantage when measuring load cells, strain gauges and other
bridge-type transducers. And finally, the true economy of
single power supply operation (7116) enables a high performance panel meter to be built with the addition of only
eleven passive components and a display.

•
•
•
•
•
•

•
•
•
•
•

HoLD Reading Input Allows Indefinite Display Hold
Guaranteed Zero Reading for 0 Volts Input
True Polarity at Zero for Precise Null Detection
1pA Input Current Typical
True Differential Input
Direct Display Drive - No External Components
Required - LCD ICL7116
- LED ICL7117
Low Noise - Less Than 15,...V pk-pk Typical
On-Chip Clock and Reference
Low Power Dissipation - Typically Less Than 10mW
No Additional Active Circuits Required
New Small Outline Surface Mount Package Available

ORDERING INFORMATION
Part
Number

Temperature
Range

Package

ICL7116CPL
ICL7116CM44

O°C to + 70°C
O°C to +70~C

40-Pin Plastic DIP
44-Pin Surface Mount

ICL7117CPL

40-Pin Plastic DIP

HLOR r-I'!I--'"""!-'--'lI'I!Ih osc 1
01
OSC2

iii
t:

~

1~~

-

A1
F1
G1
E1
02

1

~~;/
ICL7116 (LCD)
ICL7117 (LED)

REF HI
REF LO
C+REF
C-REF

~ ~~

:~ ~6

AF22

AlZ
BUFF

~

~T

~

c;~ {

03
83

~~E3
~

(1000) AB4

POL
(MINUS)

G2

COMMON
TEST

C3

OSC 3

A3

OSC 2

BP

G3

v-

G2 (TENS)

~}~
A3g

G3 ~
BP/GNO
(7116V(7117)

ose 1

POL

Hl. OR

AU

0'

E3

C,

F3

B'

B3

0338-1

0338-2

Figure 1: Pin Configurations

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

2-13

•

... ICL7116/7117
....

....

CD ABSOLUTE MAXIMUM RATINGS
;:

!:i

2

ICL7116

ICL7117

Supply Yoltage (Y+ to Y-) ........................ 15Y
Analog Input Yoltage (either input) (Note 1) ..... Y+ to YReference Input Yoltage (either input) ......... Y+ to YHLDR, Clock Input ......................... Test to Y+
Power Dissipation (Note 2)
Ceramic Package .......................... 1000mW
Plastic Package ............................. 800mW
Operating Temperature ................... O'C to + 70'C
Storage Temperature ................ - 65'C to + 150'C
Lead Temperature (Soldering, 1Osee) ............. 300'C

Supply Yoltage Y + .............................. + 6Y
Y- .............................. -9Y
Analog Input Yoltage (either input) (Note 1) ..... Y+ to YReference Input Yoltage (either input) ......... Y+ to YHLDR, Clock Input ......................... Gnd to Y+
Power Dissipation (Note 2)
Ceramic Package .......................... 1000mW
Plastic Package ............................. 800mW
Operating Temperature ................... O'C to + 70'C
Storage Temperature ................ -65'C to + 150'C
Lead Temperature (Soldering, 1Osee) ......•...... 300'C

Note 1: Input voltages may exceed the supply voltages provided the input current is limited to ± 1OOIlA.

Note 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specificalions is not implied. Exposure to absolute
maximum rating conditions for extended periods may aHect device reliability.

ELECTRICAL CHARACTERISTICS
Parameter

(Note 3)

Test Conditions

Min

Typ

Max

Unit

-000.0

±OOO.O

+000.0

Digital Reading

Zero Input Reading

YIN=O.OY
Full Scale=200.0mY

Ratiometric Reading

YIN=YREF
YREF=100mY

999

999/1000

1000

Digital Reading

I YIN I '" 200.0mY

-1

±0.2

+1

Counts

Lineari! (Max. deviation from
best straight line fit)

Full Scale=200mY
or Full Scale = 2.000Y (Note 7)

-1

±0.2

+1

Counts

Common Mode Rejection Ratio
(Note 4)

YCM= ±1Y, YIN = OY,
Full Scale=200.0mY

50

",Y/V

Noise (Pk - Pk value not exceeded
95% of time)

YIN=OY
Full Scale=200.0mY

15

",y

Leakage Current

YIN = OY (Note 7)

1

10

pA

0.2

1

",Y/'C

1

5

ppml'C

0.8

1.8

mA

0.6

1.8

mA

2.8

3.2

Y

Rollover Error (Difference in
reading for equal positive and
~ ·eading near Full Scale)

@

Input

Zero Reading Drift
Scale Factor Temperature
Coefficient
Y + Supply Current (Does not
include LED current for 7117)

YIN=O
O'C7V), the COMMON voltage will have a low voltage coefficient (.001 %N), low output impedance ('" 150),
and a temperature coefficient typically less than 80ppmrC.
The limitations of the on-chip reference should also be
recognized, however. With the 7117, the internal heating
which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic.
The combination of reference Temperature Coefficient
(TC), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25,..,V to
80,..,Vpk-pk. Also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low dissipation count such as 1111 (8 segments on) can suffer by a
count or more. Devices with a positive TC reference may
require several counts to pull out of an overload condition.
This is because overload is a low dissipation mode, with the
three least significant digits blanked. Similarly, units with a
negative TC may cycle between overload and a nonoverload count as the die alternately heats and cools. All these
problems are of course eliminated if an external reference is
used.
The 7116, with its negligible dissipation, suffers from
none of these problems. In either case, an external reference can easily be added, as shown in Figure 5.

TEST
The TEST pin serves two functions. On the 7116 it is
coupled to the internally generated digital supply through a
5000 resistor. Thus it can be used as the negative supply
for externally generated segment drivers such as decimal
points or any other presentation the user may want to include on the LCD display. Figures 6 and 7 show such an
application. No more than a 1mA load should be applied.

y+

7116

TO LCD
DECIMAL POINT

0338-7

Figure 6: Simple Inverter for Fixed Decimal Point

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THI;: IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical valuss haV9 been characterized but sre not 18sted.

2-17

•

.......~
....UI
......
.......

ICL7116/7117
Figure 9 is the Digital Section of the 7117. It is identical to
that of the 7116 except the regulated supply and back plane
drive have been eliminated and the segment drive has been
increased from 2 to 8mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19)
must sink current from two LED segments, it has twice the
drive capability or 16mA.
In both devices the polarity indicator is ON for negative
analog inputs. This can be reversed by simply reversing IN
LO and IN HI.

r-----------------,V+
V+

2

B,~:~D+-l
D--t-1

I

7116

I

DECIMAL
POINT
SELECT

[

,
I

I
D+I

TO LCD
DECIMAL
POINTS

: D+I
I

CD4030

....- T ' " -.... V-o- = DP ON,
L__
GROUND = DP OFF.

1
I

__.J

HOLD Reading Input

\OND

The HLDR input will prevent the latch from being updated
when this input is at a logiC "1 ". The chip will continue to
make AID conversions, however, the results will not be updated to the internal latches until this input goes low. This
input can be left open or connected to TEST (7116) or
GROUND (7117) to continuously update the display. This
input is CMOS compatible, and has a 70kO typical resistance to either TEST (7116) or GROUND (7117).

0338-8

Figure 7: Exclusive 'OR' Gate for
DeCimal Point Drive
The second function is a "lamp test". When TEST is
pulled to high (to V+) all segments will be turned on and the
display should read - 1888. [Caution: on the 7116, in the
lamp test mode, the segments have a constant DC voltage (no square-wave) and will burn the LCD display If
left in this mode for several minutes.)

DIGITAL SECTION
Figures 8 and 9 show the digital section for the 7116 and
7117, respectively. In the 7116, an internal digital ground is
generated from a 6 volt Zener diode and a large P channel
source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency
divided by 800. For three readings/second this is a 60Hz
square wave with a nominal amplitude of 5 volts. The segments are driven at the same frequency and amplitude and
are in phase with BP when OFF, but out of phase when ON.
In all cases negligible DC voltage exists across the segments.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterfzed but are not t9St6(i.

2·18

ICL7116/7117
DISPLAY FONT

02 :1 '-I 5 6"18 9

--------------·---·-------------------·-----4-------++-1+lH+--HH!·I+--++++H-!----:..'==~:;_

•
--~---4--+---~.-

--------------------------6'=--OSC.

OSC3

0338-9

Figure 8: Digital Section 7116

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values haVB been characterized but are not tested.

2-19

..........
........o
......

ICL7116/7117

o
,.,. C,

....
....
2

'c,·

.'.'.
•

--~~------~~~-----------4----~-4---+------------~VT
37
500

n

TEST
I

I

211 OIGITAL

~---1~~~----~~--------------~,_==_=_=_=_~_4-_-_-_~_--_-_~_~~~G.OUND
HLOA

osc.

OSCI

osc.

0338-10

Figure 9: Digital Section 7117
The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
three convert-cycle phases. These are Signal integrate
(1000 counts), reference de-integrate (0 to 2000 counts)
and auto-zero (1000 to 3000 counts). For signals less than
full scale, auto-zero gets the unused portion of reference
deintegrate. This makes a complete measure cycle of 4,000
(16,000 clock pulses) independent of input voltage. For
three readings/second, an oscillator frequency of 48kHz
would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz,
33%kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 66%kHz, 50kHz,
40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/ second) will reject both 50 and 60Hz (also 400 and
440Hz).

System Timing
Figure 10 shows the clocking arrangement used in the
7116 and 7117. Three basic clocking arrangements can be
used:
1.
An external oscillator connected to pin 40.
2.
A crystal between pins 39 and 40.
3.
An R-C oscillator using all three pins.

I

711117117

I

I

I

i

I
I

TO
:
COUNTE"I
I

I

,
,iL _______ _

~--------

..

,
i
'

_________ J

IXTIRMAL

OSCILLATOR

TEST (7"1)
or GNO (7117)

0338-11

Figure 10: Clock Circuits

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-20

tIlO~OIL C;
r-

ICL7116/7117

digital reading. For instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.682V. Instead of dividing the
input down to 200.0mV, the designer should use the input
voltage directly and select VREF=0.341V. Suitable values
for integrating resistor and capacitor would be 120kO and
0.22",F. This makes the system slightly quieter and also
avoids a divider network on the input. The 7117 with ± 5
volts supplies can accept input signals up to ± 4 volts. Another advantage of this system occurs when a digital reading of zero is desired for VIN*O. Temperature and weighing
systems with a variable tare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset voltage between COMMON and IN LO.

COMPONENT VALUE SELECTION
Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 100",A of quiescent current. They can
supply 20",A of drive current with negligible non-linearity.
The integrating resistor should be large enough to remain in
this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 2 volts full scale, 470kO is near
optimum and similarly a 47kO resistor is optimum for a
200.0mV scale.

Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing (approx. 0.3 volt from either supply). In the 7116 or the 7117, when the analog
COMMON is used as a reference, a nominal ±2 volt full
scale integrator swing is fine. For the 7117 with ± 5 volt
supplies and analog common tied to supply ground, a ± 3.5
to ±4 volt swing is nominal. For three readings/second
(48kHz clock), nominal values for CINT are 0.22",F and
0.10",F, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing.
An additional requirement of the integrating capacitor is it
have low dielectric absorption to prevent roll-over errors.
While other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at
reasonable cost.

7117 Power Supplies
The 7117 is designed to work from ± 5 volt supplies.
However, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors,
and an inexpensive I.C. Figure 11 shows this application.
See ICL7660 data sheet for an alternative.

v+

osc.
osc ...........-ll-..J

7117

Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence
on the noise of the system. For 200mV full scale where
noise is very important, a 0.47",F capacitor is recommended. On the 2 volt scale, a 0.047",F capacitor increases the
speed of recovery from overload and is adequate for noise
on this scale.

v·

0338-12

Figure 11: Generating Negative Supply
from +5v

Reference Capacitor
A 0.1 ",F capacitor gives good results in most applications. If rollover errors occur a larger value, up to 1.0",F may
be required.

In fact, in selected applications no negative supply is required. The conditions to use a single + 5V supply are:
1.
The input signal can be referenced to the center of
the common mode range of the converter.
2.
The signal is less than ± 1.5 volts in magnitude.
3.
An external reference is used.

Oscillator Components
For all ranges of frequency a 100kO resistor is recommended and the capacitor is selected from the equation
0.45
f"'FiC' For 48kHz clock (3 readings/second), C= 100pF.

TYPICAL APPLICATIONS
The 7116 and 7117 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatility of these A/ D converters.

Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is: VIN=2VREF' Thus, for the 200.0mV and
2.000 volt scale, VREF should equal 100.0mV and 1.000
volt, respectively. However, in many applications where the
AID is connected to a transducer, there will exist a scale
factor other than unity between the input voltage and the

lNTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been characterized but ar9 not tested

2-21

..........

....0.....

......

....

•

........ ICL7116/7117
....

......
...
IS)

S2

711.
'-" Gee 1

....., osc.

1HKl1

PICa

lei 'lREF

Gee.
TaT
R.PHI
V+
CREF
C RE'
COMMON
INH.

/

100P'

10n

c:::5=o.1#'F

'.':Y

'"

}TO DISPLAY

ar

'00p'

-

C REF

-A

/
A',

.S.Ii

==:;:0.1J.lF

C REF

COMMON

+

...-

.7Kll

".H.'

Set VAEF '" 1.000V

OSC.
TEST

220.1

0.4710"

y0,
C,

ep

V

1Mn

aUFF
INT

Cl3

·.oo....

11'.01,.

All

,A 1OOKll

osc 2

AEFHI
y.

A'A

'-

INLO

..

7116/7117

40

1Mn

INHI
IN LO

IN

-

AlZ

.:,.8V

BUFF

..01 .... F

y+

.

IN

,047,.F

;',.J

470KH

'.r.22j.1.F

INT

•

G,
C3

-"on

F

y-

I TO DISPLAY

A31=
G3
.P/GND

El

••

TO lACK PLANE

0338-15

Figure 14: 711617117: Recommended
component values for 2.000V full scale.

0338-13

Figure 12: 7116 using the internal reference.
Values shown are for 200.0mV full scale,
3 readings per second, floating supply
voltage (9V battery).

7117
40
'-' OSC1

.....,

lOOKti

osc.
osc.

7117

4O

OSC1
08C2

100Ktl

Set VREF = i00AmY

osc,

'oOP'

TEST

REFH.
y+
C REF
C REF

All
BUFF

INT
y-

,'A

c:::5=O.1Io'F

,

1Mn

IN LO
A/Z

+

47Kfl

C,
}TODISPLAY

=;

s.t VAEF =l00.amY

/
~ 10KJ;T 15KU
1I"l •.•V(ICL ....)

+5Y

1M!1

• . Ot••

IN

0.47,1

r
v·

U;

t:

~
-

Cl
Bl
Al
Fl
Gl
El

r-r
_

~

w
!:.

C2

B2
A2
F2
E2

~

833
~
F3
E3
(1000) AB4
POL
(MINUS)

:~~~:Ei:9Ntt~>

OSCl
OSC2
OSC3
TEST
REF HI
REF LO

~~t..)c.JB!:~~~== I

C+REF

C-REF
COMMON
INHI
INLO

G2
C3
A3
G3
BP
POL
AB4
E3
F3
B3

TEST
OSC 3
OSC 2
OSC 1
y+
Ol
Cl
Bl

A/Z

BUFF
INT

v-

G2 (TENS)
C3j"::
A3
g
G3 ~
BP

_ _ .... . - N N f N N N N C " )

cu..eWQ(,)ccccu..WQ

0339-1

0339-2

Figure 1: Pin Configurations

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, eXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-24

ICL7126
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V + to V -) ........................ 15V
Analog Input Voltage (Either Input) (Note 1) .... V+ to VReference Input Voltage (Either Input) ......... V+ to VClock Input ............................... TEST to V+

Power Dissipation (Note 2)
Ceramic Package ............................ 1000mW
Plastic Package ..........•.................... 800mW
Operating Temperature ................... O·C to + 70·C
Storage Temperature ................ -65·C to + 150·C
Lead Temperature (Soldering, 10sec) ............. 300·C

NOTE 1: Input voltages may exceed the supply voltages provided the input current is limited to ± 100,..A.
NOTE 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the speCifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliabillly.

ELECTRICAL CHARACTERISTICS
Characteristics

(Note 3)

Test Conditions

Min

Typ

Max

Unit

-000.0

±OOO.O

+000.0

Digital Reading

Zero Input Reading

VIN=O.OV
Full Scale=200.0mV

Ratiometric Reading

VIN=VREF
VREF=100mV

999

999/1000

1000

Digital Reading

Rollover Error (Difference in
reading for equal positive and
negative reading near Full Scale)

1- VIN 1= + VIN "" 200.0mV

-1

±0.2

+1

Counts

Linearity (Max. deviation from
best straight line fit)

Full scale = 200mV
or full scale = 2.000V

-1

±0.2

+1

Counts

Common Mode Rejection Ratio
(Note 4)

VCM= ±1V, VIN=OV
Full Scale = 200.0mV

50

ILVN

Noise (Pk • Pk value not exceeded
95% of time)

VIN=OV
Full Scale = 200.0mV

15

fLY

Leakage Current @ Input

VIN=OV

1

10

pA

Zero Reading Drift

VIN=O
O·C ....--_ TO DIGITAL SECTION

1
1

IN"'G'~3'~-4~~~__+-__~~-+______-J

,

INT

I
I
I
I

COMMON

'32
IHI'UT
LOW

I

I ..
INLO

L___

__________________ ..!:

..!~T

~

________________________ .. ___________ _
0339-3

Figure 2: Analog Section of 7126

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typics/ values have been characterized but are not tssteci

2·26

.D~DIL

ICL7126

n
r-

.......
I\)

TEST CIRCUITS

01

0339-6

Figure 5: Clock Frequency 48kHz.
(3 readings/sec)

0339-4

Figure 3: ICL7126 with Liquid Crystal Display

DETAILED DESCRIPTION
Analog Section

IN

Figure 2 shows the Functional Diagram of the Analog
Section for the ICL7126. Each measurement cycle is divid·
ed into three phases. They are (1) auto·zero (A·Z), (2) signal
integrate (I NT) and (3) de·integrate (DE).

Auto-zero phase
During auto·zero three things happen. First, input high
and low are disconnected from the pins and internally short·
ed to analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Third, a feedback loop is
closed around the system to charge the auto·zero capacitor
CAZ to compensate for offset voltages in the buffer amplifi·
er, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the
noise of the system. In any case, the offset referred to the
input is l!lsS then 10,..V.

Signal Integrate phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and
low are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a
wide common mode range; within one Volt of either supply.
If, on the other hand, the input signal has no return with
respect to the converter power supply, IN LO can be tied to
analog COMMON to establish the correct common-mode
voltage. At the end of this phase, the polarity of the integrated signal is determined.

0339-5

Figure 4: 7126 Clock Frequency
16kHz. (1 reading/sec)

De-integrate phase
The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and in-

INTERSIL·S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHAlL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical VBIuss MIIB btHm charactBrIzBd but tIfI1 not t6st6d.

2-27

•

..d...

:: ICL7126
-

put high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the
capacitor will be connected with the correct polarity to
cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the
input signal. Specifically the digital reading displayed is

ature changes of 2 to 8°C, typical for instruments, can givt;l a
scale factor error of a count or more. Also the common
voltage will have a poor voltage coefficient when the total
supply voltage is less than that which will cause the zener to
regulate «7V). These problems are eliminated if an external reference is used, as shown in Figure 6.

1000 ( VIN ).
VREF
y-

Differential Input

y'

The input can accept differential voltages anywhere within the common mode rante of the input amplifier; or specifically from 0.5 Volts below the positive supply to 1.0 Volt
above the negative supply. In this range the system has a
CMRR of 86 db typical. However, since the integrator also
swings with the common mode voltage, care must be exercised to assure the integrator output does not saturate. A
worst case condition would be a large positive commonmode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator
positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the
recommended 2V full scale swing with little loss of accuracy. The integrator output can swing within 0.3 Volts of either
supply without loss of linearity.

271<11

COMMON

Vo

I')

Ib)

0339-7

Figure 6: Using an External Reference

The reference voltage can be generated anywhere within
the power supply voltage of the converter. The main source
of common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage,
the reference capaCitor can gain charge (increase voltage)
when called up to de-integrate a positive Signal but lose
charge (decrease voltage) when called up to deintegrate a
negative input signal. This difference in reference for ( + ) or
(-) input voltage will give a roll-over error. However, by
selecting the reference capaCitor large enough in comparison to the stray capacitance, this error can be held to less
than 0.5 count for the worst case condition. (See Component Value Selection.)

Analog COMMON is also used as the input low return
during auto-zero and de-integrate. If IN LO is different from
analog COMMON, a common mode voltage exists in the
system and is taken care of by the excellent CMRR of the
converter. However, in some applications IN LO will be set
at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied
to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently referenced
to analog COMMON, it should be since this removes the
common mode voltage from the reference system.
Within the IC, analog COMMON is tied to an N channel
FET that can sink 3mA or more of current to hold the voltage 2.8 Volts below the positive supply (when a load is trying to pull the common line positive). However, there is only
1p.A of source current, so COMMON may easily be tied to a
more negative voltage thus over-riding the internal reference.

Analog COMMON

TEST

This pin is included primarily to set the common mode
voltage for battery operation or for any system where the
input signals are floating with respect to the power supply.
The COMMON pin sets a voltage that is approximately 2.8
Volts more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about
6V. However, analog COMMON has some of the attributes
of a reference voltage. When the total supply voltage is
large enough to cause the zener to regulate « 7V), the
COMMON voltage will have a low voltage coefficient
(0.001 %1%), low output impedance ('" 150), and a temperature coefficient typically less than 80ppml"C.
The limitations of the on-Chip reference should also be
recognized, however. The reference temperature coefficient
(Te) can cause some degradation in performance. Temper-

The TEST pin serves two functions. It is coupled to the
internally generated digital supply through a 500n resistor.
Thus it can be used as the negative supply for externally
generated segment drivers such as decimal pOints or any
other presentation the user may want to include on the LCD
display. Figures 7 and 8 show such an application. No more
than a 1mA load should be applied.
The second function is a "lamp test." When TEST is
pulled high (to V+) all segments will be turned on and the
display should read - 1888. The TEST pin will sink about
10mA under these conditions.
Caution: In the lamp test mode, the segments have a
constant D-C voltage (no square-wave) and may burn
the LCD display if left in this mode for extended periods.

Differential Reference

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOrE.· All typics/ values havs bsBn chsracteriz6d but Sf6 not tested.

2-28

ICL7126

v+
1un

7126

INTEASIL
IT1750

7126

TO LCD
DECIMAL POINT

~--

BP't-----.-'-',

~.;?{

L..._.,._...I~;~:~~dPOFFL_:040~_",:
' -_ _ _ _ _ _ _ _ _...l '
1Mn

IN HI

INLO
AlZ
BUFF

y+

To"," ,
40

To pin 1
~

.P

TO BACK PLANE

2'

}TODIOPLAY

.,

TOBACK
PLANE

0339-'7

0339-,5

Figure 14: 7126 with Zener diode
reference.

Figure 16: 7126 measuring ratiometrlc
values of Quad Load Cell.

Since low T.C. zeners have breakdown voltages
- 6.8V, diode must be placed across the total
supply (10V). As in the case of Figure 13, IN LO
may be tied to COMMON.

The resistor values within the bridge are
determined by the desired sensitivity.

.

To pin ,

osc,

OSC'L.Jo--'V""'_....

Ole 3

To pin 1

'-'

!A~V"

OSC2
OSC3
TEST

REF HI
REF LO

C REF
C REF

PO.,,11

IOKn ~'OOKt>1 27K';'"
~1.2V(ICLIO.'1
1M!!

IN HI

• •01.uF

.

;..•. 'IOKn

}

G,

..,

C,

COMMON
IN HI
INLO

....... +5V

.~!

o.~~~

INTq=::::!~==y-[

+

IN

-

o.33.F

G,
;:

::: IV

____.:§

}
TO DISPLAY

G3
I'

TO BACK PUNE
21

:

TO DISPLAY -

G,

.liCon NPN

UPS 37040'
.Imll.,

~::~~~~----\-Q
~

/
• .1.

COMMON
INLO
AlZ
BUFF
INT
V-

REF LO[

Set Vref = 100.OmV

sOPF

ScM ,_tor ad....'

R!:s.:. q==...:JlF~!:\);/V----"'M~I;.,1r-~

4.

OSCt

0339-,8

Figure 17: 7126 used as a digital
centigrade thermometer.

GND ~TO BACK PLANE
2'

A silicon diode-connected transistor has a
temperature coefficient of about -2mVrC.
Calibration is achieved by placing the sensing
transistor in ice water and adjusting the zeroing
potentiometer for a 000.0 reading. The sensor
should then be placed In boiling water
and the scale-factor potentiometer
adjusted for 100.0 reading.

0339-,6

Figure 15: 7126 operated from
single + 5V supply.
An external reference must be used in this
application, since the voltage between V + and
v- is insufficient for correct operation of the
internal reference.

'Values depend on clock frequency. See Figures", , 2, 13.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not testsd.

2-32

.O~OIL

ICL7128

P
...N....
G

•

0339-19

Figure 18: Circuit for developing Underrange and Overrange
signals from 7126 outputs.

..

T....

OIC'
OICl
OICO
TIlT

. ,.

1CIIt . .1or . . . .

(YMI .. 1OOnIY 101 AC to 11111)

110Kll

... .0
C . .'
COIF

....

CC"'OH~~~
•N.o
AIZ

..",

.NT
y-

E

}TCNPLAY

--....:..
;;;.t,I1;;~ TO BACK PLANI
0339-20

Figure 19: AC to DC Converter with 7126. Test Is used as a common mode reference
level to ensure compatibility with most op-amps.

INTERSIL'S SOLE AND EXCWSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT BTATED IN THE WARRANTV ARTICLE OF THE CONDmON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCWDING THE IMPLIED WARRANTIES OF
MERCHANTABILlTV AND FITNESS FOR A PARTICULAR USE.
NOTE: An typIcs/ VBIuss have bssn chiJrBt:teIIzBd but IU8 not testBd.

2-33

.....= ICL7126

g APPLICATION NOTES
A016
A017
A018
A023
A032

A046
A052

7126 EVALUATION KIT
After purchasing a sample of the 7126, the majority of
users will want to build a simple voltmeter. The parts can
then be evaluated against the data sheet specifications,
and tried out in the intended application.
To facilitate evaluation of this unique circuit, Intersil is offering a kit which contains all the necessary components to
build a 3%-digit panel meter. With the ICL7126EV/KIT and
the small number of additional components required, an engineer or technician can have the system "up and running"
in about half an hour. The kit contains a circuit board, a
display (LCD), passive components, and miscellaneous
hardware.

"Selecting AID Converters", by David Fullagar.
"The Integrating AID Converter", by Lee Evans.
"Do's and Don'ts of Applying AID Converters", by
Peter Bradshaw and Skip Osgood.
"Low Cost Digital Panel Meter Designs", by David
Fullagar and Michael Dufort.
"Understanding the Auto-Zero and Common Mode
Performance of the ICL7106/7/9 Family", by Peter
Bradshaw.
"Building a Battery-Operated Auto Ranging DVM
with the ICL7106", by Larry Goff.
"Tips for Using Single-Chip 3%-Digit AID Converters", by Dan Watson.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: Ail typJca/ va/uss have been chlUllCtsriz6d but are not testBd.

2-34

D~DIl!...

ICL7129
4% Digit LCD Single-Chip
AID Converter

N

G

GENERAL DESCRIPTION

FEATURES

The IntersillCL7129 is a very high-performance 4%-digit
analog-to-digital converter that directly drives a multiplexed
liquid crystal display. This single-chip CMOS integrated circuit requires only a few passive components and a reference to operate. It is ideal for high-resolution hand-held digital multi meter applications.
The performance of the ICL7129 has not been equaled
before in a single-chip AID converter. The successive integration technique used in the ICL7129 results in accuracy
better than 0.005% of full-scale and resolution down to
10 /IV/count.
The ICL7129, drawing only 1mA from a 9V battery, is well
suited for battery powered instruments. Provision has been
made for the detection and indication of a "LOW/BATTERY" condition. Autoranging instruments can be made
with the ICL7129 which provides overrange and underrange
outputs and 10:1 range changing input. The ICL7129 instantly checks for continuity, giving both a visual indication
and a logic level output which can enable an external audible transducer. These features and the high performance of
the ICL7129 make it an extremely versatile and accurate
instrument-on-a-chip.

• ± 19,999 Count AID Converter Accurate to ± 4 Count
• 10,..V Resolution On 200mV Scale
• 110dB CMRR'
• Direct LCD Display Drive
• True Differential Input and Reference
• Low Power Consumption
• Decimal Point Drive Outputs
• Overrange and Underrange Outputs
• Low Battery Detection and Indication
.10:1 Range Change Input

ORDERING INFORMATION
Part
Number

Temperature

Package

ICL7129CPL

O'Cto +70'C

40-Pin Plastic

-

Evaluation Kit

ICL7129EV/KIT

UJW BATTERY CONTINUITY

-I.B.B.B.B
SEGMENT DRIVES

BACKPLANE
DRIVES

,...-...,

0SC1

DISPLAY
OUTPUT
LINES

OSC3

v·

....J
V- DONO

TOPYfEW

0340-1

Figure 1: Functional Diagram

0340-2

Figure 2: Pin Configuration
(outline dwg PL)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

301663-003

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have be8n characterized but are not tested.

2-35

•

: ICL7129

.......
s!

ABSOLUTE MAXIMUM RATINGS
Supply Voltages (V+ to V-) ....................... 15V
Reference Voltage (REF HI or REF La) ........ V+ to VInput Voltage (Note 1)
(IN HI or IN La) ........................... V+ to VVDISP ............................ DGND -0.3V to V+
Digital Input Pins
1,2,19,20,21,22,27,
37,38,39,40 .......................... DGND to V+

Power Dissipation (Note 2)
Plastic package ............................. 800mW
Operating Temperature ................... O'C to + 70'C
Storage Temperature ................ - 65'C to + 150'C
Lead Temperature (Soldering, 10sec) ............. 300'C

Note 1: Input voltages may exceed the supply voltages provided that input current is limited to ± 400p.A. Currents above this value may result in invalid display
readings but will not destroy the device if limited to ± 1rnA.

Note 2: Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.

NOTE: Stresses above those listed under "Abso/ute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
v- to v+ =9V, VREF= 1.00V. TA = +25'C, fCLK= 120kHz, unless otherwise noted.
Characteristics

Test Conditions

Zero Input Reading

VIN=OV
200mVScaie

Zero Reading Drift

VIN=OV
O'C_4--.:'~9 YOISP
5k >"'e---I!.1'

' - - -.....-

ICL7129

36 DGND

.....-;YOISP

ICL7129

DGND

75k

'--_ _ _~------... 23

-+ 23

L--_ _ _ _

Y-

Y-

0340-14

Figure 14: Two Methods for Temperature Compensating the Liquid Crystal Display
optimum integrator swing at full-scale. A large integrator
swing will reduce the effect of noise sources in the comparator but will affect rollover error if the swing gets too close
to the positive rail (:::: 0.7V). This gives an optimum swing of
:::: 2.5V at full-scale. For a 150kO integrating resistor and 2
conversions per second the value is 0.10,."F. For different
conversion rates, the value will change in inverse proportion. A second requirement for good linearity is that the capacitor have low dielectric absorption. Polypropylene caps
give good performance at a reasonable price. Finally the foil
side of the cap should be connected to the integrator output
to shield against pick-up.
The only requirement for the reference cap is that it be
low leakage. In order to reduce the effects of stray capacitance, a 1.0,."F value is recommended.

DISPLAY TEMPERATURE
COMPENSATION
For most applications an adequate display can be obtained by connecting VOISP (pin 19) to DGND (pin 36). In
applications where a wide temperature range is encountered, the voltage drive levels for some triplexed liquid crystal displays may need to vary with temperature in order to
maintain good display contrast and viewing angle. The
amount of temperature compensation will depend upon the
type of liquid crystal used. Display manufacturers can supply the temperature compensation requirements for their
displays. Figure 14 shows two circuits that can be adjusted
to give a temperature compensation of :::: + 1OmVI'C between V+ and VOISP. The diode between DGND and VOISP
should have a low turn-on voltage to assure that no forward
current is injected into the chip if VOISP is more negative
than DGND.

CLOCK OSCILLATOR
The ICL7129 achieves its digital range changing by integrating the input signal for 1000 clock pulses (2,000 oscillator cycles) on the 2V scale and 10,000 clock pulses on the
200mV scale. To achieve complete rejection of 60Hz on
both scales, an oscillator frequency of 120kHz is required,
giving two conversions per second.
In low resolution applications, where the converter uses
only 31f2 digits and 100,."V resolution, an R-C type oscillator
is adequate. In this application a C of 51 pF is recommended
and the resistor value selected from fosc=0.45/RC. However, when the converter is used to its full potential (41f2
digits and 10,."V resolution) a crystal oscillator is recom-

COMPONENT SELECTION
There are only three passive components around the
ICL7129 that need special consideration in selection. They
are the reference capacitor, integrator resistor, and integrator capacitor. There is no auto-zero capacitor like that found
in earlier integrating AID converter designs.
The integrating resistor is selected to be high enough to
assure good current linearity from the buffer amplifier and
integrator and low enough that PC board leakage is not a
problem. A value of 150kO should be optimum for most
applications. The integrator capacitor is selected to give an

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but 8r6 not tested.

2-44

Ij]D~DIl.

ICL7129

n

I'"

...
.....

mended to prevent the noise from increasing as the input
signal is increased due to frequency jitter of the R-C oscillator. Both R-C and crystal oscillator circuits are shown in
Figure 15.

N
0

+5Y

24
y+

I

I

REF HI

I

I

I

ICL7129

I

_ _ _ ..JI

I

L_

REF LO
ICL7129

2

DGND

COM
IN HI

I

I
I

ICL7129

I
I

___ J

L_

IN LO

I
I

ICL8089
35
28
33

+
YIN

32

Y-

I

23

2
-5Y

5pF

120kHz

0340-16

10pF

Figure 16: Powering the ICL7129 from
- 5V Power Supplies

V+o-1 ~Ul--+-l ~ V+

+ 5V and

When a battery voltage between 3.8V and 7V is desired
for operation, a voltage doubling circuit should be used to
bring the voltage on the ICL7129 up to a level within the
power supply voltage range. This operating mode is shown
in Figure 17.

0340-15

Figure 15: RC and Crystal Oscillator Circuits

POWERING THE ICL7129
The ICL7129 may be operated as a battery powered
hand-held instrument or integrated into larger systems that
have more sophisticated power supplies. Figures 16, 17,
and 18 show various powering modes that may be used
with the ICL7129.
The standard supply connection using a 9V battery is
shown in Figure 3.
The power connection for systems with +5V and -5V
supplies available is shown in Figure 16. Notice that measurements are with respect to ground. COMMON is also
tied to INLO to remove any common-mode voltage swing
on the integrator amplifier inputs.
It is important to notice that in Figure 16, digital ground of
the ICL7129 (DGND pin 36) is not directly connected to
power supply ground. DGND is set internally to approximately 5V less than the V + terminal and is not intended to
be used as a power input pin. It may be used as the ground
reference for external logic, as shown in Figure 7 and 8. In
Figure 7, DGND is used as the negative supply rail for external logic provided that the supply current for the external
logic does not cause excessive loading on DGND. The
DGND output can be buffered as shown in Figure 8. Here,
the logic supply current is shunted away from the ICL7129
keeping the load on DGND low. This treatment of the
DGND output is necessary to insure compatibility when the
external logic is used to interface directly with the logic inputs and outputs of the ICL7129.

+
:

3.8VT08V

I"'-+~p-'_.--o+

+

~
10~F

ICL7_

23

0340-17

Figure 17: Powering the ICL7129
from a 3_8V to 6V Battery

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

2-45

•

: ICL7129
.......

d
-

VOLTAGE REFERENCES

Again measurements are made with respect to COMMON
since the entire system is flojiting. Voltage doubling is accomplished by using an ICL7660 CMOS voltage converter
and two inexpensive electrolytic capacitors. The same principle applies in Figure 18 where the ICL7129 is being used
in a system with only a single + 5V power supply. Here
measurements are made with respect to power supply
ground.
A single polarity power supply can be used to power the
ICL7129 in applications where battery operation is not appropriate or convenient only if the power supply is isolated
from system ground. Measurements must be made with respect to COMMON or some other voltage within its input
common-mode range.

The COMMON output of the ICL7129 has a temperature
coefficient of ±80ppml"C typically. This voltage is only suitable as a reference voltage for applications where ambient
temperature variations are expected to I:)e minimal. When
the ICl7129 is used in most environments, other voltage
references should be considered. The diagram in Figures 3
and 18 show the ICL8069 1.2V band-gap voltage source
used as the reference for the ICL7129, and the COMMON
output as its pre-regulator. The reference voltage for the
ICL7129 is set to 1.000V for both 2V and 200mV full-scale
operation.

+5Y'o----1~--~--------_t------_,

ICL8089

0.1 ; 7V), the COMMON voltage will have a low voltage coefficient (0.001 %/
%), low output impedance (""35n), and a temperature coefficient typically less than 150ppmrC.

DE-INTEGRATE PHASE
The next phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-50

ICL7136
V'

V'

V'REF
I-~
HI
REFLO
ICL7138

:

f+

V'

'~8.8VOLT
~

'--

1.2 VOLT

r-

ICL7136

ZENER

REFERENCE

l~

REF HI
REFLO

- ....

1-+:

: ,

~ (INTERSlL

j ~

ICL8088)

1---<"""-

COMMON I - -

V-

(a)

(b)
0343-7

0343-8

Figure 6: Using an External Reference
The limitations of the on-chip reference should also be
recognized, however. The reference temperature coefficient
(TC) can cause some degradation in performance. Temperature changes of 2°C to 8°C, typical for instruments, can
give a scale factor error of a count or more. Also, the COMMON voltage will have a poor voltage coefficient when the
total supply voltage is less than that which will cause the
zener to regulate «7V). These problems are eliminated if
an external reference is used, as shown in Figure 6.
Analog COMMON is also used as the input low return
during auto-zero and de-integrate. If IN LO is different from
analog COMMON, a common-mode voltage exists in the
system and is taken care of by the excellent CMRR of the
converter. However, in some applications IN LO will be set
at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied
to the same point, thus removing the common-mode voltage from the converter. The same holds true for the reference voltage. If the reference can be conveniently referred
to analog COMMON, it should be since this removes the
common-mode voltage from the reference system.
Within the IC, analog COMMON is tied to an N channel
FET which can sink 3mA or more of current to hold the
voltage 3.0V below the positive supply (when a load is trying
to pull the common line positive). However, there is only
1p.A of source current, so COMMON may easily be tied to a
more negative voltage, thus overriding the internal reference.

TEST
The TEST pin serves two functions. It is coupled to the
internally generated digital supply through a 5000 resistor.
Thus, it can be used as the negative supply for external
segment drivers such as for decimal points or any other
presentation the user may want to include on the LCD display. Figures 7 and 8 show such an application. No more
than almA load should be applied.
The second function is a "lamp test." When TEST is
pulled high (to V+) all segments will be turned on and the
display should read -1888. The TEST pin will sink about
10mA under these conditions.
Caution: In the lamp test mode, the segments have a
constant DC voltage (no square-wave). This may burn
the LCD display If maintained for extended periods.

v'

_

.,1---_.-i--\1"""

-

to LCD

DlClMAI.
POINT

DECIMAl.
POINTS

,
L_
-_I

L-____________

..I

~a.

0343-10

Figure 8: Exclusive "OR" Gate for
Decimal Point Drive
V'

lMn

DETAILED DESCRIPTION
ICL7138

BP' "2"'1+-11+--

TESTh3""7+~-

(Digital Section)

TO LCD
DECIMAL POINT

Figure 9 shows the digital section for the 7136, An internal digital ground is generated from a 6V Zener diode and a
large P channel source follower, This supply is made stiff to
absorb the relatively large capacitive currents when the
backplane (BP) voltage is switched. The BP frequency is
the clock frequency divided by 800, For three readings/second this is a 60Hz square-wave with a nominal amplitude of
5V, The segments are driven at the same frequency and

:~J7~SIL
TO LCD
BACKPLANE

0343-9

Figure 7: Simple Inverter for Fixed
Decimal Point
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPREss, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typical valu6s have b8tm charact6rizsd but sre not tested.

2-51

•

.= ICL7136
too

s;!

DISPLAY FONT

0:23'-156189
-----------.--.-~-------·---------------·-+·-----i·l~~+~-·--~I~~ii~+··-~4+~~+~-··--~e~~~-

-----""'--=4> v------------------------e~;----,OSC3

Ole

0343-11

Figure 9: Digital Section
amplitude and are in phase with BP when OFF, but out of
phase when ON. In all cases negligible DC voltage exists
across the segments. The polarity indication is "ON" for
negative analog inputs. If IN La and IN HI are reversed, this
indication can be reversed also, if desired.

System Timing
L

Figure 10 shows the clock oscillator provided in the 7136.
Three basic clocking arrangements can be used:
1.
An external oscillator connected to pin 40.
2.
A crystal between pins 39 and 40.
3.
An RC oscillator using all three pins.
The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the

oJ

0343-12

Figure 10: Clock Circuits

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typIcsl vslues have beBn chstacf6rizsd but 11M not tsstsd.

2·52

ICL7136
four convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (0 counts to 2000 counts),
zero integrator (11 counts to 140 counts") and auto-zero
(910 counts to 2900 counts). For signals less than fullscale, auto-zero gets the unused portion of reference de-integrate and zero integrator. This makes a complete measure cycle of 4000 (16,000 clock pulses) independent of
input voltage. For three readings/second, an oscillator frequency of 48kHz would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of the 60Hz period. Oscillator frequencies of 60kHz, 48kHz, 40kHz, 33YskHz, etc.
should be selected. For 50Hz rejection, oscillator frequencies of 66%kHz, 50kHz, 40kHz, etc. would be suitable. Note
that 40kHz (2.5 readings/second) will reject both 50Hz and
60Hz (also 400Hz and 440Hz). See also A052.

Oscillator Components
For all ranges of frequency a 50pF capacitor is recommended and the resistor is selected from the approximate
equation f- 0.45/RC. For 48kHz clock (3 readings/second), R=180kO, for 16kHz, R=560kO.

Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is VIN = 2VREF. Thus, for the 200.0mV and
2.000V scale, VREF should equal100.0mV and 1.000V, respectively. However, in many applications where the AID is
connected to a transducer, there will exist a scale factor
other than unity between the input voltage and the digital
reading. For instance, in a weighing system, the designer
might like to have a full-scale reading when the voltage from
the transducer is 0.682V. Instead of dividing the input down
to 200.0mV, the designer should use the input voltage directly and select VREF = 0.341V. A suitable value for the
integrating resistor would be 330kO. This makes the system
slightly quieter and also avoids the necessity of a divider
network on the input. Another advantage of this system occurs when a digital reading of zero is desired for VIN#O.
Temperature and weighing systems with a variable tare are
examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and
COMMON and the variable (or fixed) offset voltage between
COMMON and IN LO.

COMPONENT VALUE SELECTION
(See also A052)

Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 6/kA of quiescent current. They can supply - 1/kA of drive current with negligible non-linearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full-scale, 1.8MO is near optimum,
and similarly 180kO for a 200.0mV scale.

TYPICAL APPLICATIONS

Integrating Capacitor

The 7136 may be used in a wide variety of configurations.
The circuits which follow show some of the possibilities, and
serve to illustrate the exceptional versatility of these AID
converters.

The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing (approx. 0.3V from either
supply). When the analog COMMON is used as a reference,
a nominal ± 2V full-scale integrator swing is fine. For three
readings/second (48kHz clock) nominal values for CINT are
0.047/kF, for 1 reading/second (16kHz) 0.15/kF. Of course,
if different oscillator frequencies are used, these values
should be changed in inverse proportion to maintain the
same output swing.
The integrating capacitor should have low dielectric absorption to prevent roll-over errors. While other types may
be adequate for this application, polypropylene capacitors
give undetectable errors at reasonable cost.

40
~

TOI)I"'-

OSC 1

18Ok0

05C2
0$e3
TEST
REF HI
REF LQ
C REF
C REF
COMMON
INHI
IN LO

Auto-Zero Capacitor

Set Yr&1 '" lOG.OmY

~O.'"F

101en

221lk!l
1M!}

::;t 0.01,11F
0.47pF

A·Z

1801<0

BUFF

The size of the auto-zero capacitor has some influence
on the noise of the system. For 200mV full-scale where
noise is very important, a 0.47/kF capacitor is recommended. The ZI phase allows a large auto-zero capacitor to be
used without causing the hysteresis or overrange hangover
problems that can occur with the ICL7126 or ICL7106 (see
A032).

/

SO.F

INT

0.047"F

y-

-=

::r

..

IN

9V

G,
C,
A, UTODISPLAY

8.
G,

TO BACKPLANE
21

Reference Capacitor

0343-13

Figure 11: 7136 Using the Internal
Reference

A 0.1/kF capacitor gives good results in most applications. However, where a large common-mode voltage exists
(Le., the REF LO pin is not at analog COMMON) and a
200mV scale is used, a larger value is required to prevent
rOil-over error. Generally, 1.0/kF will hold the roll-over error
to 0.5 count in this instance.

Values shown are for 200.0mV full-scale,
3 readings/sec, floating supply voltage
(9V battery).

"'After an overranged conversion of more than 2060 counts, the zero integrater phase will last 740 counts, and auto-zero will last .260 counts.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charaotedzed but are not tested.

2-53

fJI

= ICL7136
......

.D~DIl.

...

S:!
'-"

To". 1 -

40
OSC 1
OSC2
OSC 3
TEST
REF HI
REF LO

Set Vref '" l00.OmY

SOpF

,/

201<0

200'0

C REF

V+

REF HI
RlfLO
CREF
CREF
COMMON
IN HI
INLO
A.z

,
IN

*0.01,F
O.47pF
180kO

BUFF

'.~0.15 .. F

INT
V-

§
"

V-

\...1
101<0

- -'1Mn

'.j

1M11

+
IN

-

.33/o1F
1~
'.': v-

..A

·5Y

ruv

___ ~G.01pF

.NT

C,

Se' yret =tOO.OnIY

:=!0o...,!

aUFF

G,

G,
8P

'v-

sCj"

TEIT

""'.2V (IClao••)
1M!1

OBC1
OBC'

08C.

27~~

, TV

COMMON
INHI
IN lO
A·Z

~

...

~O.lJ.'

CREF

.

To ... 1

560Icll

V}TO DISPLAY

-5Y

0,
C,

..,

D-TO BACKPLANE
21

}TOD.SPLAY

.,

0,
.P

>---

TO BACKPlANE

0343-14

Figure 12: 7136 with an External
Band-Gap Reference (1.2V Type)

0343-16

Figure 14: 7136 with Zener Diode
Reference

IN LO is tied to COMMON, thus establishing the
correct common-mode voltage. COMMON acts
as a pre-regulator for the reference. Values
shown are for 1 reading/sec.

.....,

-

To pin 1
40

oaCl
OSC2

osc.
TEST
REFHI
REFLO

50pf

CREF
CREF

~O.lJjF

To pin 1

/

COMMON

-

1MIl

.II.01F

INLO
A,z
aUFF
INT
y-

.....,

Se. Vref '" 1.000v

250Idl

IN HI

Since low TC zeners have breakdown voltages
~ 6.8V, diode must be placed across the total
supply (10V). As in the case of Figure 13, IN LO
may be tied to COMMON.

y+

..,..,

.

Set v .... :: l00.amV

/

50pf

REF HI
REFLO
CREF
CAEF

+
IN

COMMON

0°.

1."

1MU

INLO
A,z
aUFF

".~

y-

}TODISPlAY

.',,-

}

C,

21

G,
GND

+
IN

-

;':,18OkO

.,

t--- TO BACKPlANE

.0.01 ..'

0.'7 F

.NT
VG,

C,

+SY

T

20Idl ..., 1001dl 27110
"'l1 •• Y('C~

IN HI

1.IMU

G,

BP

••

OSC 3
TEST

0.10,.F ..

0.047/o1F

OSCl
OSC2

:

TO DISPLAY -

t---==-- TO BACKPlANE
21

0343-15

Figure 13: Recommended Component
Values for 2.000V Full-Scale,
3 Readings/Sec

0343-17

Figure 15: 7136 Operated from
Single + 5V Supply

For 1 reading/sec, change CINT, Rose to values
of Figure 12.

An external reference must be used in this
application, since the voltage between V+ and
V- is insufficient for correct operation of the
internal reference.

'Values depend on clock frequency. See Figures 11, 12, 13.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

2-54

ICL7136

.

~T~opn~1r--------------------9Y'
OSC1
asC2
OSCI
TEST
REf HI
RIFLO
C REF

C NtF
COMMON
INHI
INLO

G.47

A-Z

""'T

BUFF
lilT

y-

O,

C,

...'"

}TO OISPLAY

0,

21

TO
BACKPLANE

0343-18

Figure 16: 7136 Measuring Ratiometric Values of Quad Load Cell
The resistor values within the bridge are determined by the desired sensitivity.

To pin 1

OSCl

••

OSC 2

OSC 3 D----il------'

Sc••• factor adJu.t

A~=~ D---SOp---,,=,,-,. /

~Ilcon

NPH

MPS 3704 Of

1M!1

CRE'

}S
_or

R"LO[}---f=~Atv-~0Vv-~

••••

C REF

COMMON~~~~~===t~~:;.~~-t~
INHI[
INLO~~~~~~~
_ _ _ _~~
A.Z t
0.47 F
aUFF Lt----".IV\i38Ok=O,..

::: IV

INTq==::::::~====~
Y-[
0,
C,

____j

}TO DISPLAY

'"

0,

BP

TO BACKPLANE

21

0343-19

Figure 17: 7136 used as a Digital Centigrade Thermometer

rc.

A silicon diode-connected transistor has a temperature coefficient of about - 2mV
Calibration is
achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0
reading. The sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for
a 100.0 reading. See ICL807% and AD590 data sheets for alternative circuits.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OA STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

2-55

•

=

....... ICL7136

...
~

v·

-

va
0'
C'

..,,

To

Vee

F1
G,

I'
02
C2
B2

AI
PI

12
D3

~

......
••

Uiii.nte

40
GeC'

DlCa

_HI

OSC3

naT

RIFLO
CRI'
CRII'
COMMON
INHI

To_
GNO

.IHLO
AoZ

INT

V-

0.

...

PI

C3

POI.

.P

CI3

20
C-

or 74C10

CD4077

0343-20

Figure 18: Circuit for Developing Underrange and Overrange Signals from 7136 Outputs

To ..... '

loll. tRtor adJUit
(Vrel '" 100mV tor AC to RMI)

40

'OOId)

"CIN

0343-21

Figure 19: AC to DC Converter with 7136
Test is used as a common-mode reference level to ensure compatibility with most op amps.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR

use.

NOTE: All typical values havs been characterized bul are not tested.

2-56

ICL7136
APPLICATION NOTES

7136 EVALUATION KIT

A016
A017
A018

After purchasing a sample of the 7136, the majority of
users will want to build a simple voltmeter. The parts can
then be evaluated against the data sheet specifications,
and tried out in the intended application.
To facilitate evaluation of this unique circuit, Intersil is offering a kit which contains all the necessary components to
build a 3%-digit panel meter. With the ICL7136EV/Kit and
the small number of additional components required, an engineer or technician can have the system "up and running"
in about half an hour. The kit contains a circuit board, a
display (LCD), passive components, and miscellaneous
hardware.

A023
A032

A046
A047
A052

"Selecting AID Converters," by David Fullagar.
"The Integrating AID Converter," by Lee Evans.
"Do's and Dont's of Applying AID Converters," by
Peter Bradshaw and Skip Osgood.
"Low Cost Digital Panel Meter Designs," by David
Fullagar and Michael Dufort.
"Understanding the Auto-Zero and Common-Mode
Behavior of the ICL71 06/7/9 Family," by Peter
Bradshaw.
"Building a Battery-Operated Auto Ranging DVM
with the ICL7106," by Larry Goff.
"Games People Play with Intersil's AID
Converters," edited by Peter Bradshaw.
"Tips for Using Single-Chip 3%-Digit AID Converters," by Dan Watson.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have ~ characterized but are not tested.

2-57

..

::; ICL7137
!:i 3%-Digit LED Low Power
g Single-Chip AID Converter
GENERAL DESCRIPTION

FEATURES

The Intersil ICl7137 is a high performance, very low power 3Y.-digit AID converter. All the necessary active devices
are contained on a single CMOS IC, including seven-segment decoders, display drivers, reference, and clock. The
7137 is designed to interface with a light emitting diode
(lED) display. The supply current (exclusive of display) is
under 200",A, ideally suited for battery operation.
The 7137 brings together an unprecedented combination
of high accuracy, versatility, and true economy. The device
features auto-zero to less than 1O",V, zero drift of less than
input bias current of 10pA max., and rollover error
1",V
of less than one count. The versatility of true differential
input and reference is useful in all systems, but gives the
designer an uncommon advantage when measuring load
cells, strain gauges and other bridge-type transducers. And
finally the true economy of the ICl7137 allows a high performance panel meter to be built with the addition of only 10
passive components and a display.
The ICl7137 is an improved version of the ICl71 07, eliminating the overrange hangover and hysteresis effects, and
should be used in its place in all applications, changing only
the passive component values.

• First-Reading Recovery From Overrange allows
Immediate "OHMS" Measurement
• Guaranteed Zero Reading for OV Input
• True Polarity at Zero for Precise Null Detection
• lpA Typical Input Current
• True Differential Input and Reference
• Direct LED Display Drive - No External Components
Required
• Pin Compatible With The ICL7107
• Low Noise -15",Vp-p Without Hysteresis or
Overrange Hangover
• On-Chip Clock and Reference
.,Improved Rejection of Voltage On COMMON Pin
• No Additional Active Circuits Required
• Evaluation Kit Available ICL7137EV/Kit

rc,

ORDERING INFORMATION*
Part Number

Temperature Range

ICl7137CPl

O°C to

+ 70°C

ICl7137RCPl

O°C to

+ 70°C

Package
40-Pin Plastic
40-Pin Plastic

ICl7137EVIKIT

EVALUATION KIT

v' ,-no--.:-r-'""!1!t-, osc 1

;;!:

eo"

TO
DIGITAL
SECTION

jNHI9"t~i}-7V), the COMMON voltage will have a low voltage coefficient (0.001 %/
%), low output impedance( "" 350), and a temperature coefficient typically less than 150ppm1'C.
The limitations of the on-chip reference should also be
recognized, however. The reference temperature coefficient
(TC) can cause some degradation in performance. Temperature changes of 2·C to S·C, typical for instruments, can
give a scale factor error of a count or more. Also, the COMMON voltage will have a poor voltage coefficient when the
total supply voltage is less than that which will cause the
zener to regulate «7V). These problems are eliminated if
an external reference is used, as shown in Figure 6.

DE·INTEGRATE PHASE
The next phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the
capacitor will be connected with the correct polarity to
cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the
input signal. Specifically; the digital reading displayed is
1000(VINiVREF)'

ZERO INTEGRATOR PHASE
The final phase is zero integrator. First, input low is shorted to analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Finally, a feedback loop is
closed around the system to input high to cause the integrator output to return to zero. Under normal conditions, this
phase lasts for between 11 to 140 clock pulses, but after a
"heavy" overrange conversion, it is extended to 740 clock
pulses.

V REF_>HI

Differential Input

REF LO~:
~:

The input can accept differential voltages anywhere within the common-mode range of the input amplifier; or specifically from 0.5V below the positive supply to 1.0V above the
negative supply. In this range the system has a CMRR of
90dS typical. However, since the integrator also swings with
the common-mode voltage, care must be exercised to assure the integrator output does not saturate. A worst case
condition would be a large positive common-mode voltage
with a near full-scale negative differential input voltage. The
negative input signal drives the integrator positive when
most of its swing has been used up by the positive common-mode voltage. For these critical applications the integrator swing can be reduced to less than the recommended
2V full-scale swing with little loss of accuracy. The integrator output can swing within 0.3V of either supply without
loss of linearity.

ICL7137

". '"' 8.8 VOLT
.~ ZENER

-

l~

(al
0344-6

v+
v+
ICL7137

Differential Reference

--'

REF HI

The reference voltage can be generated anywhere within
the power supply voltage of the converter. The main source
of common-mode error is a roll-over voltage caused by the
reference capacitance losing or gaining charge to stray capacity on its nodes. If there is a large common-mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but
lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for
(+ ) or (-) input voltage will give a roll-over error. However,
by selecting the reference capacitor large enough in comparison to the stray capacitance, this error can be held to
less than 0.5 count for the worst case condition (see Component Value Selection).

f..

1.2 VOLT
REFERENCE

-+! '.4 .. ~=L

REF LO --< ..........

COMMON-

(b)
0344-7

Figure 6: Using an External Reference
Analog COMMON is also used as the input low return
during auto-zero and de-integrate. If IN LO is different from
analog COMMON, a common-mode voltage exists in the
system and is taken care of by the excellent CMRR of the
converter. However, in some applications IN LO will be set
at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied
to the same pOint, thus removing the common-mode v')ltage from the converter. The same holds true for the reference voltage. If the reference can be conveniently referred
to analog COMMON, it should be since this removes the
common-mode voltage from the reference system.

Analog Common
This pin is included primarily to set the common-mode
voltage for battery operation or for any system where the
input signals are floating with respect to the power supply.
The COMMON pin sets a voltage that is approximately 3.0V
more negative than the positive supply. This is selected to
give a minimum end-of-life battery voltage of about 6V.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY ANO FITNESS FOR A PARTICULAR USE.

NOTE: AU typical values hsvs bsen charsctetized but Sf6 not tested.

2-61

p
.......

Col
....

::; ICL7137

...
i
~

Within the IC, analog COMMON is tied to an N channel
FET which can sink 100Jl-A or more of current to hold the
voltage 3.0V below the positive supply (when a load is trying
to pull the common line positive). However, there is only
1fJ.A of source current, so CO!VIMON may easily be tied to a
more negative voltage, thus· overriding the intemal reference.

TEST
The TEST pin is coupled to the internal digital supply
through a 5000 resistor, and functions as a "lamp test."
When TEST is pulled high (to V+) all segments will be
turned on and the display should read - 1888. The TEST
pin will sink about 10mA under these conditions.

DISPLAY FONT

a

:·2 3 '-ISS -: 8 9

--------,I
I
I
I

I

I
I
I
I

I

soo H

,
I

'--_-+::-'-~-___rc::--------------+--=.:2.~'
DIDITAl.
38
38
GROUND

--------1---------------------------I

'Three Inverters.
One inverter shown for clarity.

osc:,

_.J

osc 31
'--_ _ _ _....._-I~
OBC 2

0344-8

Figure 7: Digital Section

DETAILED DESCRIPTION

(Digital Section)
Figure 7 shows the digital section for the 7137. The segments are driven at 8mA, suitable for instrument size common anode' LED displays. Since the 1000 output (pin 19)
must sink current from two LED segments, it has twice the
drive capability or 16mA. The polarity indication is "ON" for
negative analog inputs. If IN LO and IN HI are reversed, this
indication can be reversed also, if desired.
Figure 8 shows a method of increasing the output drive
current, using four DM7407 Hex Buffers. Each buffer is capable of sinking 40mA.

....

0344-9

Figure 8: Display Buffering for
Increased Drive Current

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGAnON WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANlY ARTICLE OF THE CONDITION OF SALE.
THE WAARANlY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANnES OF
MERCHANTABILIlY AND FITNESS FOR A PARnCULAR USE.

NOTE: AN typIcsJ VBIu8s haV6 bB8n charsctetIz9d but aM not f6sted.

2-62

ICL7137
supply). When the analog COMMON is used as a reference,
a nominal ± 2V full-scale integrator swing is fine. For three
readings/second (48kHz clock) nominal values for CINT are
O.047!,-F, for 1 reading/second (16kHz) O.15!,-F. Of course,
if different oscillator frequencies are used, these values
should be changed in inverse proportion to maintain the
same output swing.
The integrating capaCitor should have low dielectric absorption to prevent roll-over errors. While other types may
be adequate for this application, polypropylene capaCitors
give undetectable errors at reasonable cost.

System Timing
Figure 9 shows the clock oscillator provided in the 7137.
Three basic clocking arrangements can be used:
1.
An external oscillator connected to pin 40.
2.
A crystal between pins 39 and 40.
3.
An RC oscillator using all three pins.

Auto-Zero Capacitor
L

The size of the auto-zero capaCitor has some influence
on the noise of the system. For 200mV full-scale where
noise is very important, a 0.47!,-F capaCitor is recommended. The 21 phase allows a large auto-zero capacitor to be
used without causing the hysteresis or overrange hangover
problems that can occur with the ICL7107 or ICL7117 (See
Application Note A032).

oJ

Reference Capacitor

0344-10

Figure 9: Clock Circuits

A 0.1!,-F capacitor gives good results in most applications. However, where a large common-mode voltage exists
(Le., the REF LO pin is not at analog COMMON) and a
200mV scale is used, a larger value is required to prevent
roll-over error. Generally, 1.0!,-F will hold the roll-over error
to 0.5 count in this instance.

The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
four convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (0 counts to 2000 counts),
zero integrator (11 counts to 140 counts·) and auto-zero
(910 counts to 2900 counts). For Signals less than fullscale, auto-zero gets the unused portion of reference de-integrate and zero integrator. This makes a complete measure cycle of 4000 (16,000 clock pulses) independent of
input voltage. For three readings/second, an oscillator frequency of 48kHz would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of the 60Hz period. Oscillator frequencies of 60kHz, 48kHz, 40kHz, 33%kHz, etc.
should be selected. For 50Hz rejection, oscillator frequencies of 66%kHz, 50kHz, 40kHz, etc. would be suitable. Note
that 40kHz (2.5 readings/ second) will reject both 50Hz and
60Hz (also 400Hz and 440Hz.) See also A052.
• After an overranged conversion of more than 2060 counts, the zero

Oscillator Components
For all ranges of frequency a 50pF capaCitor is recommended and the resistor is selected from the approximate
equation f '" 0.45/RC. For 48kHz clock (3 readings/second), R= 180kO, while for 16kHz (1 reading/sec),
R=560kO.

Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is: VIN = 2VREF. Thus, for the 200.0mV and
2,000V scale, VREF should equal 100.0mV and 1.000V, respectively. However, in many applications where the AID is
connected to a transducer, there will exist a scale factor
other than unity between the input voltage and the digital
reading. For instance, in a weighing system, the deSigner
might like to have a full-scale reading when the voltage from
the transducer is 0.682V. Instead of dividing the input down
to 200.0mV, the designer should use the input voltage directly and select VREF=0.341V. A suitable value for the
integrating resistor would be 330kO. This makes the system
slightly quieter and also avoids the necessity of a divider
network on the input. Another advantage of this system occurs when a digital reading of zero is desired for VIN*O.
Temperature and weighing systems with a variable tare are
examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and
COMMON and the variable (or fixed) offset voltage between
COMMON and IN LO.

inte~

grator phase will last 740 counts, and auto-zero will last 260 counts.

COMPONENT VALUE SELECTION
(See Application Note A052)

Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 6!,-A of quiescent current. They can supply -1!,-A of drive current with negligible non-linearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full-scale, L8MO is near optimum,
and similarly 180kO for a 200.0mV scale.

TYPICAL APPLICATIONS

Integrating CapaCitor

The 7137 may be used in a wide variety of configurations.
The circuits which follow show some of the possibilities, and
serve to illustrate the exceptional versatility of these AID
converters.

The integrating capaCitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing (approx. O.3V from either

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-63

•

........ ICL7137

I.IlD~DI!..

~

~

~

..

ose.

To .... -

08C3
TEST
REFH,

set v.... '" too.amv

~

/

DO""I

IN LO

0.471"

I.Z

IUF'
INT

0.047.1o!'

V-

G,
C,
A,
G,
OND

tUH

T

.0.0'",

IN

=:3: 0.1,.,

-5V

IMlI
IN

;'·,1.8MIl

INT
V-

,,

V·
240kD

'50100

_90.01/1'

A·Z

I

/

0.471"

BUFF

I
I

}TODISPLAY

,
t

COMMON
INH,
INLO

-

I
I
I
I

... v...r = 1.000V

.0;..

TEST
REF HI
REFLO
C REF
CREF

22OkO

'01<0

.-

IN HI

.-

ose 3
+5V

COMMON

OSCI

ose.

RIFLO
CREF
CAEF

..

To pin 1

.-,

....

OSC2

O.047J,AF

V-

G,
C,
A,

OV

•• 7

G,
OND

}TO DISPLAY

.,

OV

0344-11

Figure 10: 7137 Using the Internal
Reference.

0344-13

Figure 12: Recommended Component Values for
2.000V Full-Scale,
3 Readings/Sec.

Values shown are for 200.0mV full-scale, 3
readings/sec. IN LO may be tied to either
COMMON for inputs floating with respect to
supplies, or GND for single ended inputs. (See
discussion under Analog COMMON.)

'-" OSC 1

For 1 reading/sec, change C'NT, Rose to values
of Figure 11.

..

~

Topln",-

40

OSC'
580kD

....

08C2
08e3
TEST
REF HI
REF LO

Set ~"f

2OkO

C REF

,

"".'V"CLI".)

COMMON

1Mll

IN HI

IPO.O'.I"

IN LO
A·Z

OSC.
TEST

.71<0

T

R£FLO
CRE'

V+

CA.F

.

INLO

7.

A-Z

a_

180kO

INT

INT

V-

O.15~F

V-

Itt

v,.. ""

I
100.GmV

\v!

Do"I"

COMMON
IN HI

IN

O.47I'F_1l

BUFF

....

_HI

100.OmY

200kD

.,-

po...

C REF

i

OSC2

'0lI0

.-

J1MIl

tMn

.0.0'1"

'5V

';j lUV

.

IN

-

-5V

Ih

G,

C,

C,
}TODISPLAY

A,
0,
aND

}TDDISPLAY

Ao
Cb
OND

--, - " " - - - 0 OV

7'

0344-12

••

aOV

0344-14

Figure 11: 7137 with an External Band-Gap
Reference (1.2V Type).

Figure 13: 7137 with Zener Diode Reference.
Since low TC zeners have breakdown voltages
- 6.aV, diode must be placed across the total
supply (10V). As in the case of Figure 11, IN LO
may be tied to COMMON.

IN LO is tied to COMMON, thus establishing the
correct common-mode voltage. COMMON acts
as a pre-regulator for the reference. Values
shown are for 1 reading/sec.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not test9d.

2-64

ICL7137

'-'

Toptn 1
40

oee.
Oac2
oeeo

.

-

TES'
REF HI
RIFLO
CREF
CREF

~O.'~

COMMON
IN HI

....

INLO

• 02
BU,F
INT

y-

G,
C,

40

oac 2U---,\fV'v--4
let Yrel = 'OO.DMV

0-------..

-'~;~Imo

.EF HI
.EF L O O - - - - - -___
CREF
CREF

+IV

P'J"'Y(IC~
1MII

.G.OI.F

.

08C
TUTOO---It----'
_

/

COMMON

H'1:;=i;~=~
!~I:
RtNT
0.•7 F

IN

IN
IN

lUFF

'1QIdl

O...:.:!!"-'INIr--4

q=~~==-.,

INT
y-[

}TOOIS.IoAV

I.,

0,
GND

To,," 1

08C'

..

ov

2•

0344-16

0344-15

Figure 14: 7137 Operated from
Single + 5V Supply.

Figure 15: Measuring Ratlometrlc Values of
Quad Load Cell.

An external reference must be used in this
application, since the voltage between V+ and
V - is Insufficient for correct operation of the
Internal reference.

The resistor values within the bridge are
determined by the desired sensitivity.

+tv
y+

-

OSCI
OSC2
08C3
TEIT

AI
fI
GI

REFLO

D2
C2

CREF
COMMON
INHI
INLO

.,

.,

To

v"

01
CI

12Kn

.,
A2

.

REFHI

c ...

Al'
BUFF

.NT

0344-17

Figure 16: Circuit for developing Underrange and
Overrange signals from outputs.
The LM339 is required to ensure logic compatibility with heavy display loading.

'Values depend on clock frequency. See Figures 10. 11. and 12.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-65

....::;... ICL7137

S:!

~~~~~1'-----------~----4r--------------------------------~~+5V
40

Seel. l.etor "lUll
(V,.. '" 100ntV lor AC to AMI)

OSC1

osc.
OSC.
TEST
REF HI
REFLO
CREF
C REF

COMMON
INHf

IN LO
A-Z
BUFF

'NT

v-

G,
C,

'"

G3
GND

"
0344-18

Figure 17: AC to DC Converter with 7137

APPLICATION NOTES

ICL7137 EVALUATION KITS

A016
A017
A018

After purchasing a sample of the 7137, the majority of
users will want to build a simple voltmeter. The parts can
then be evaluated against the data sheet specifications,
and tried out in the intended application.
To facilitate evaluation of this unique circuit, Intersil is offering a kit which contains all the necessary components to
build a 3%-digit panel meter. With the ICL7137EV/Kit, an
engineer or technician can have the system "up and running" in about half an hour. The kit contains a circuit board,
LED display, passive components, and miscellaneous hardware.

A023
A032

A046
A047
A052

"Selecting AID converters," by David Fullagar.
"The Integrating AID Converter," by Lee Evans.
"Do's and Dont's of Applying AID Converters," by
Peter Bradshaw and Skip Osgood.
"Low Cost Digital Panel Meter Designs," by David
Fullagar and Michael Dufort.
"Understanding the Auto-Zero and Common-Mode
Behavior of the ICL7106/7/9 Family," by Peter
Bradshaw.
"Building a Battery-Operated Auto Ranging DVM
with.the ICL7106," by Larry Goff.
"Games People Play with Intersil's AID Converters" edited by Peter Bradshaw.
"Tips for Using Single-Chip 3%-Digit AID Converters," by Dan Watson.

'NTERS'L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typIcal va/IIBs have bgem charaotsrized but are not tested.

2-66

ICL7139
33/4-Digit
Autoranging Multimeter
GENERAL DESCRIPTION

s"",}..~

The Intersil ICL7139 is a high perfor
wer,
auto-ranging digital multimeter IC. Unlike
utoranging
multimeter ICs, the ICL7139 always displays the result of a
conversion on the correct range. There is no "range hunting" noticeable in the display. The unit will autorange between the four different ranges. A manual switch is used to
select the 2 high group ranges. DC current ranges are 4 mA
and 40 mA in the low current group, 400 mA and 4A in the
high current group. Resistance measurements are made on
4 ranges, which are divided into two groups. The low resistance ranges are 4/40 kilohms. High resistance ranges are
0.4/4 megohms. Resolution on the lowest range is 1 ohm.

• 13 Ranges:
4 DC Voltage-400 mV, 4V, 40V, 400V
1 AC Voltage-400V
4 DC Current-4 mA, 40 mA, 400 mA, 4A
4 Resistanc_4 KO, 40 KO, 400 KO, 4 MO
• Autoranglng-Flrst Reading Is Always on Correct
Range
• On-Chip Duplex LCD Display Drive Including Three
Decimal Points and 11 Annunciators
• No Additional Active Components Required
• Low Power Dissipation-Less than 20 mW-1000
Hour Typical Battery Life
• Average Responding Converter for Sinewave Inputs
• Display Hold Input
• Continuity Output Drives Piezoelectric Beeper
• Low Battery Annunciator with On-Chip Detection
• Guaranteed Zero Reading for 0 Volts Input on All
Ranges

ORDERING INFORMATION
Part
Number

Temperature
Range

Package

ICL7139CPL

O°Cto + 70°C

40 Pin Plastic DIP

'ICL7139CM44

O°Cto +70°C

44 Pin Surface Mount

'Consult Factory for DetaIls.
SWITCHES

I

B

I
I
I
I

OfGITALCOMMON

_ _ _ _ _ _ _ -.J
yt.

V-COM

0079-1

EXTERNAL
RESISTORS
AN.
CAPACITORS

0079-2

Figure 2: Functional Diagram

Figure 1: Pin Configuration

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTieS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

301671-003

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values hsve been characfBriz9d but are not tested.

2-67

....= ICL7139
~

2

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (V + to V -) ......................... 15V

Storage Temperature Range ........... - 65'C to + 130'C
Lead Temperature (Soldering, 10 sec) .............. 300'C

Reference Input Voltage (VREF to COM) .......•....... 3V
Analog Input Current. ........................... 100 J10A
(IN + Current or IN + Voltage)
Clock Input Swing ........................ V+ to V+ - 3

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated In the operational sections of the specifications is not
impll6d. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Power Dissipation (Plastic Package) •............ 800 mW
Operating Temperature Range ............. O'C to + 70'C

ELECTRICAL CHARACTERISTICS v+ = + 9.0V, TA
volts, test circuit as shown in Figure 3. Crystal = 120 kHz.

=

+ 25'C, VREF adjusted for -3.700 reading on DC

Test Conditions

Parameter
Zero Input Reading

VIN or liN or RIN = 0.00

Rollover Error (Note 1)

VIN or liN = ± Full Scale1

Min

Typ

-00.0

Max

Units

+00.0

V,I,Ohms

4
-1

Counts
+1

Counts

±1

% ofRDG + 1

~ccuracy DC V, 400 Volt Range Excluded

±0.2

% ofRDG + 1

Accuracy Ohms, 4K and 400K Range

±0.5

% ofRDG + 8

Linearity (Best Straight Line) (Note 6)
Accuracy DC V, 400 Volt Range Only

f'.ccuracy Ohms, 40K and 4 Meg Range
Accuracy DC I, Unadjusted for FS
Accuracy DC I, Adjusted for FS
Accuracy AC V (Note 5)

@60Hz

Noise (Note 2, 95% of Time)

VIN = 0, DC Volts
VIN = 0, AC Volts
VIN = 0, DC Voltage Range

Analog Common (with Respect to V +)

< 10 J10A
ICOMMON < 10 J1oA, Temp
ICOMMON < 100 J10A
Average DC < 50 mV

Backplane/Segment Drive Voltage

% ofRDG + 1

±0.2

%ofRDG + 1
%ofRDG

VREF

V

0.1

LSB

4

Noise (Note 2, 95% of Time)
Supply Current

Output Impedance of Analog Common

% ofRDG + 9

±0.5
±2

Open Circuit Voltage for Ohms Measurements RUNKNOWN = Infinity

Temperature Coefficient of Analog Common

±1

2.7

ICOMMON

LSB

1.5

2.4

2.9

3.1

-100

= 0-70'C

2.8

Backplane/Segment Display Frequency

mA
V
ppml'C

1

10

3.0

3.2

75

Ohms
V
Hz

-50

+50

J10A

Switch Input Levels (High Trip Point)

V+ - 0.5

V+

V

Switch Input Levels (Mid Trip Point)

V- + 3

V+ - 2.5

V

Switch Input Levels (Low Trip Point)

V-

V- + 0.5

V

100

J10s

2000

Counts

Switch Input Current (Note 3)

Beeper Output Drive (Rise or Fall Time)

VIN = V+ toV-

25

CLOAD = 10nF

Beeper Output Frequency

kHz

2

Continuity Detect

Range = Low Ohms, VREF = 1.00V

Power Supply Functional Operation

V+ toV-

7

9

11

V

Low Battery Detect (Note 4)

V+ toV-

6.5

7

7.5

V

500

NOTE 1: Rollover is defined as absolute value of negative reading minus absolute value of positive reading.
2: Noise is defined as the width of the uncertainty window (where the display will flicker) between two adiacent codes.
3: Applies to pins 17-20.
4: Analog Common falls out of regulation when the Low Battery Detect is asserted. however the ICL7139 will continue to operate correctly with a supply
voltage above 7 volts and below 11 volts.
5: For 50 Hz use a 100 kHz crystal.
6: Guaranteed by design. not tested.
RDG

~

Reading

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-68

ICL7139
3%-Dlglt Autoranglng DMM Using Intersil's ICL7139

r----.....-t
10llll 9
10 Mll12
II

3.3nF

LO BAT

DEINTEGRATE
TO
DISPLAY

INTEGRATE (V/ ll)

10llll 7

AC

-3999

kllMll

LOll
lMll 8

BEEPER 16
OUTPUT
4

Hill
1 Mll 11

INTEGRATE (I)

INPUTS
9.9ll
V!ll!p.A
m A o - - - - -..

10
r o l l o - - - -....~_.~~ ANALOG
COMMON

N/C~

SIB

-

•

v+

ICL7139

O.lll

N/C+!-'--

mAVp.A

17

V+~.-~~--~ mA/p.A

N/C~

V"

5

Hill, DC 19
LOll,AC

S2A

S2B

Hill/DC
LOll/AC
• OFF

~V+

~N/C
~

y+~
N/C+!-'--

SIC

18 ll/V/A

V"~.-~~--...

V"~
~V+
e!!!!4N/C

0079-3

Figure 3: ICL7139 Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2·69

.....:= ICL7139
~

1/0

Table 1: Pin Numbers and Function
Pin Function
Pin Number

0
0
0

3

Backplane 1

I

4

I

1

Segment Driver POLl AC

2

Backplane 2

5

V+
V-

I

6

Reference Input

0
0

7

LoOhms

8

Hi Ohms

DETAILED DESCRIPTION
General
Figure 2 is a simplified block diagram of the ICL7139. The
digital section includes all control logic, counters, and display drivers. The digital section is powered by V+ and Digital Common, which is about 3V below V+. The oscillator is
also in the digital section. Normally 120 kHz for rejection of
60 Hz AC interference and 100 kHz for rejection of 50 Hz
AC, the oscillator output is divided by two to generate the
internal master clock. The analog section contains the integrator, comparator, reference section, analog buffers, and
several analog switches which are controlled by the digital
logic. The analog section is powered from V + and V - .

1/0

9

Deintegrate

1/0

10

Analog Common

I

11

Int I

I

12

IntV/Ohms

I

13

Triple Point

I

14

Auto Zero Capacitor (CAZ)

I

15

Integrate Capacitor (CINT)

0

16

Beeper Output

I

17

mAl/LA

I

18

OhmslV/A

I

19

Hi Ohms DC/Lo Ohms AC

I

20

Hold

0

21

Oscillator Out

Range 1 Integrate

I

22

Oscillator In

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

23

Segement DRIVER kIm

24

Segment Driver Ohmsl A

25

Segment Driver M Ohmsl/LA

26

Segment Driver Lo BallV

27

Segment Driver Bo/Co

The ICL7139 performs a full autorange search for each
reading, beginning with range 1. During the range 1 integrate period, internal switches connect the INT V10hm terminal to the Triple Point (Pin 13). The input signal is integrated for 10 clock cycles, which are gated out over a period of 1000 clock cycles to ensure good normal mode rejection of AC line interference.

28

Segment Driver Ao/Do

29

Segment Driver Go/Eo

30

Segment Driver Fo/DPl

31

Segment Driver Bl/Cl

32

Segment Driver Al/Dl

DC VOLTAGE MEASUREMENT
Autozero
Only those portions of the analog section which are used
during DC voltage measurements are shown in Figure 5. As
shown in the timing diagram (Figure 6), each measurement
starts with an autozero (AZ) phase. During this phase, the
integrator and comparator are configured as unity gain buffers and their non-inverting inputs are connected to Common. The output of the integrator, which is equal to its offset, is stored on CAz-the autozero capacitor. Similarly, the
offset of the comparator in stored in CINT. The autozero
cycle equals 1000 clock cycles which is one 60 Hz line cycle with a 120 kHz oscillator or one 50 Hz line cycle with a
100 kHz crystal.

Range 1 Deintegrate

35

Segment Driver B2/C2

36

Segment Driver A2/D2

37

Segment Driver G2/E2

38

Segment Driver F2/DP3

39

Segment Driver Ba/Ca

At the beginning of the deintegrate cycle, the polarity of
the voltage on the integrator capacitor (CINT) is checked,
and either the DEINT+ or DEINT- is asserted. The integrator capacitor CINT is then discharged with a current equal to
VREF/RDEINT. The comparator monitors the voltage on
CINT. When the voltage on CINT is reduced to zero (actually
to the Vas of the comparator), the comparator output
switches, and the current count is latched. If the CINT voltage zero-crossing does not occur before 4000 counts have
elapsed, the overload flag is set. "OL" (overload) is then
displayed on the LCD. If the latched result is between 360
and 3999, the count is transferred to the output latches and
is displayed. When the count is less than 360, an underrange has occurred, and the ICL7139 then switches to
range 2-the 40V scale.

40

Segment Driver ADG3/E3

Range 2

33

Segment Driver Gl/El

34

Segment Driver Fl/DPl

The range 2 measurement begins with an autozero cycle
similar to the one that preceded range 1 integration. Range
2 cycle length however, is one AC line cycle, minus 360
clock cycles. When performing the range 2 cycle, the signal
is integrated for 100 clock cycles, distributed throughout

NOTE: For segment drivers, segments are listed as (segment for backplane
1)/(segment for backplane 2). Example: pin 27; segment Bo is on

backplane 1, segment Co is on backplane 2.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTI!=S OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical values have been characterized but Sf9 not tested.

2-70

ICL7139
one line cycle. This is done to maintain good normal mode
rejection. Range 2 sensitivity is ten times greater than range
1 (100 vs. 10 clock cycle integration) and the full scale voltage of range 2 is 40V. The range 2 deintegrate cycle is
identical to the range 1 deintegrate cycle, with the result
being displayed only for readings greater than 360 counts. If
the reading is below 360 counts, the ICL7139 again asserts
the internal underrange signal and proceeds to range 3.

surement is transferred to the output latches and displayed
even if the reading is less than 360.

Autozero
After finding the first range for which the reading is above
360 counts, the display is updated and an autozero cycle is
entered. The length of the autozero cycle is variable which
results in a fixed measurement period of 24,000 clock cycles (24 line cycles).

Range 3
The range 3 or 4V full scale measurement is identical to
the range 2 measurement, except that the input signal is
integrated during the full 1000 clock cycles (one line frequency cycle). The result is displayed if the reading is greater than 360 counts. Underrange is asserted, and a range 4
measurement is performed if the result is below 360 counts.

DIGIT 3
LOW
BATT

,

\

~

"

- _/0

Range 4

AC

This measurement is similar to the range 1, 2 and 3 measurements, except that the integration period is 10,000
clock cycles (10 line cycles) long. The result of this mea-

DP3

\

00
"
/
" "/
-

0

DP2

DPl

0079-4

Figure 4: Display Segment Nomenclature

ROEINT

CAZ

CINT

CAZ

CINT

RDEINT

OEIHT-

OEIHT AZ

INTWI!

VIN

-=-

R"mI

Ym

-=Ym
OEINT+

COMPARATOR

-=v+
1.7V

COMMON

COMMON

T - (INT)(AR}(AZ)
Aft • AUTORANGE CHOPPER
AZ • AUTOZERO
INT = INTEGRATE

v- t-------...J
0079-5

Figure 5: Detailed Circuit Diagram for DC Voltage Measurement
tNTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONOITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL Be IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characteriz(Jd but are not testsd.

2-71

•

......:=

ICL7139

...

2

--.rL

FIRST AUTO·ZERO

--1"1-

FIRST INTEGRATE

L
t -.J

FIRST DEINTEGRATE

I

UNDERRANGE

-..JL
--fl-

AUTO·ZERO
SECOND AUTO·ZERO
SECOND INTEGRATE

L

_____.....1I
UNDERRANGE

~

t.J

_____...rl..-.
______r I -

:
________L
UNDERRANGE

SECOND DEINTEGRATE
__________________
AUTO·ZERO

~I

'--

THIRD AUTO·ZERO
THIRD INTEGRATE

L THIRD DEINTEGRATE
..J~--------------~I
AUTO·ZERO
'-FOURTH AUTO·ZERO

--------.....

~----""L

FOURTH INTEGRATE

L
..-.r-L.

FOURTH DEINTEGRATE
AUTO·ZERO

II I I I I I I I I II I II I I I I I I I I I I

o

1 2 3 4 5 6 7 8 9 10 11 12 1314 15 16 17 18 19 20 21 22 2324

LINE FREQUENCY CYCLES (1 CYCLE = 1000 INTERNAL CLOCK PULSES = 2000
OSCILLATION CYCLES)

0079-6

Figure 6: Timing Diagram for DC Voltage Measurement
By using the lower value integration resistor, and only the
2 most sensitive ranges, the voltage drop across the current
sensing resistor is 40 mV maximum on the 4 mA and
400 mA ranges; 400 mV maximum on the 40 mA and 4A
scales. With some increase in noise, these "burden" voltages can be reduced by lowering the value of both the current sense resistors and the RINT I resistor proportionally.
The DC current measurement timing diagram is similar to
the DC voltage measurement timing diagram, except in the
DC current timing diagram, the first and second integrate
and deintegrate phases are skipped.

OCCURRENT
Figure 7 shows a simplified block diagram of the analog
section of the ICL7139 during DC current measurement.
The DC current measurements are very similar to DC voltage measurements except: 1) The input voltage is developed by passing the input current through a 0.1 ohm (HI
current ranges), or 9.9 ohm (LOW current ranges) current
sensing resistor; 2) Only those ranges with 1000 and 10,000
clock cycles of integration are used; 3) The RINT I resistor is
1 megohm, rather than the 10 megohm value used for the
RINT v resistor.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typ;csl values hsvtJ been characterized but are not tested.

2-72

.D~DIL

ICL7139
AC VOLTAGE MEASUREMENT

effectively deintegrating the voltage across a known resistor
(RKNOWN1 or RKNOWN2 of Figure 9). The shunting effect of
RINTV does not affect the reading because it cancels exactly between integration and deintegration. Like the current
measurements, the ohm measurements are split into two
sets of ranges. LO ohms measurements use a 10 kilohm reference resistor, and the full scale ranges are 4 and
40 kilohms. HI ohms measurements use a 1 megohm reference resistor, and the full scale ranges are 0.4 and 4 megohms. The measurement phases and timing are the same
as the measurement phases and timing for DC current except: 1) During the integrate phases the input voltage is the
vo!tage across the unknown resistor Rx, and; 2) During the
delntegate phases, the input voltage is the voltage across
the reference resistor RKNOWN1 or RKNOWN2.

. As shown in Figure. 8, the AC input voltage is applied
directly to the ICL7139 Input resistor. No separate AC to DC
?onversion ci~uitry is n.eeded. The AC measurement cycle
IS begun by disconnecting the integrator capacitor and using the integrator as an autozeroed comparator to detect
the positive-going zero crossing. Once synchronized to the
AC input, the autozero loop is closed and a normal integra~e/deintegrate cycle begins. The ICL7139 resynchronize~ Itself ~o .the I1:C input pri~r to every reading. Because
~Iode D4 IS In senes WIth the Integrator capaCitor, only positive current from the integrator flows into the integrator capacitor, CINT. Since the voltage on CINT is proportional to
t~e half-wave rectified average AC input voltage, a conversion factor must be applied to convert the reading to RMS.
This conversion factor is '7f'1J2 = 1.107, and the system
clock is manipulated to perform the RMS conversion. As a
result the deintegrate and autozero cycle times are reduced
by 10%.

When the ICL7139 is in the LO ohms measurement
mode, the continuity circuit of Figure 10 will be active. When
the voltage across Rx is less than approximately 100 mY,
the beeper output will be on. When R3 is 10 kilohms, the
beeper output will be on when Rx is less than 1 kilohm.

Ratlometrlc Ohms Measurement

RDEIIT
CAl

C'IIT
RDEIIIT

C'IIT
n'
LOW I

ftl

INT I

1.111

CD

Continuity Indication

. The r~tiometric ohms measurement is performed by first
Integrating the voltage across an unknown resistor, Rx, then

R"m

P
...
r:

mlITftl

-:

VRE~

-:
VREf

DEINT+
HIGH I
-:

1.7V

0.10

T • IINTIIARlli%)
Aft • AUTDRANGE CHOI't'Eft
ftl. AUTOZ£RO
INT z INTEGRATE

COMMON

0079-7

Figure 7: Detailed Circuit Diagram for DC Current Measurement
INTERSIL'S SOlE AND EXCLUSIVE WARRANTY OBUGAnON WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE

:~~~:~~ITYSHA~~ ~~~L~~~,,! ~:~T~~~~ ~~~ LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPUED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
NOTE: AU typ/CIIJ vMJee have bssn chIuactt!JrIzed but we not tftt«J.

2-73

2

:: ICL7139
.......

~ Common Voltage

pin is not designed to drive large external loads, loading on
this pin should not exceed a single CMOS input. The oscillator frequency is internally divided by two to generate the
ICL7139 clock. The frequency should be 120 kHz to reject
60 Hz AC signals, and 100 kHz to reject 50 Hz signals.

The analog and digital common voltages of the ICL7~39
are generated by an on-chip resistor/zener/diode combInation, shown in Figure 11. The resistor values are chose~ .so
the coefficient of the diode voltage cancels the positive
temperature coefficient of the zener voltage. This volta~e is
then buffered to provide the analog common and the digital
common voltages. The nominal voltage betw(;jen V+ ~nd
analog common is 3V. The analog common buffer can sink
about 20 mA, or source 0.01 mA, with an output impedance
of 10 ohms. A pullup resistor to V+ may be used if more
sourcing capability is desired. Analog common may be used
to generate the reference voltage, if desired.

Display Drivers
Figure 13 shows typical LCD Drive waveforms, RMS ON,
and RMS OFF voltage calculations. Duplex multiplexing is
used to minimize the number of connections between the
ICL7139 and the LCD. The LCD has two separate backplanes. Each drive line can drive two individual segments,
one referenced to each backplane. The ICL7139 drives 3%
7-segment digits, 3 decimal points, and 11 annunciators.
Annunciators are used to indicate polarity, low battery condition, and the range in use. Peak drive voltage across the
display is approximately 3V. An LCD with approximately
1.4V RMS threshold voltage should be used. The third voltage level needed for duplex drive waveforms is generated
through an on-chip resistor string. The DC component of
the drive waveforms is guaranteed to be less than 50 mY.

Oscillator
The ICL7139 uses a parallel resonant-type crystal in a
Pierce oscillator configuration, as shown in Figure 12, and
requires no other external components. The crystal eliminates the need to trim the oscillator frequency. An external
signal may be capacitively coupled in OSC IN, with a signal
level between 0.5 and 3V pk-pk. Because the OSC OUT

ROEINT

I -- -- -

~------~

TRIPLE POINT

---I

I
I
I
I
I

ACS

RINTV

ACINT

"V
INTVIO

~------0 BEEPER OUTPUT

L
0079-10

Figure 10: Continuity Beeper Drive Circuit
NOTE 1: The ICL7139 contains a comparator that is enabled on the lowest ohms range. It trips at approximately V. of the full scale value of that range and enables
the beeper driver to oscillate (between V- and V+) at 2 kHz. The beeper driver is capable of driving a piezo-eleclric transducer. The beeper output
response is Independent of the state of the conversion; therefore appears instantaneous to the user. Some applications may require a 150 pF capacitor
between pin 4 and pin 8 to insure a sharp onloff continuity detection.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE 'WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typicBI vs/uBS hal/9 b86n ch8rsct6rized but tuB not tBsted.

2-76

ICL7139
r---~r---------------~------------------~---------------~

+

6.7V

3V
125K
ANALOG

+r---'--_
3.WL..._..,._ _..1

COMMON
(PIN10)

LO BAT

DIGITAL

COMMON
(INTERNAL)

5K

180K

+
L-----------------------~~--------------------_+--------~--~----V0079-11

Figure 11: Analog and Digital Common Voltage Generator Circuit

Crystal

Meter Protection

The ICL7139 is designed to use a parallel resonant
120 kHz or 100 kHz crystal with no additional external components. The Rs parameter should be less than 25 kilohms
to ensure oscillation. Initial frequency tolerance of the crystal can be a relatively loose 0.05%.

The ICL7139 and its external circuitry should be protected against accidental application of 11 0/220V AC line voltages on the ohms and current ranges. Without the necessary precautions, both the 7139 and its external components could be damaged under such fault conditions. For
the current ranges, fast-blow fuses should be used between
S5A in Figure 15 and the 0.1 ohm and 9.9 ohm shunt resistors. For the ohms ranges, no additional protection circuitry
is required. However, the 10 kilohm resistor connected to
pin 7 must be able to dissipate 1.2W or 4.SW for short periods of time during accidental application of 11 OV or 220V
AC line voltages respectively.

Switches
Because the logic input draws only about 5 ",A, switches
driving these inputs should be rated for low current, or "dry"
operations. The switches on the external inputs must be
able to reliably switch low currents, and be able to handle
voltages in excess of 400V AC.

Reference Voltage Source
A voltage divider connected to V+ and Common is the
simplest source of reference voltage. While minimizing external component count, this approach will provide the
same voltage tempco as the ICL7139 Common-about 100
PPMI'C. To improve the tempco, an ICLS069 bandgap reference may be used (see Figure 14). The reference voltage
source output impedance must be :;:; RDEINT/4000.

33DK

Applications, Examples, and Hints
A complete autoranging 3% digit multi meter is shown in
Figure 15. The following sections discuss the functions of
specific components and various options.

J!0PF

0079-12

Figure 12: Internal Oscillator Circuit Diagram

INTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but am not tested.

2-77

::
,.. ICL7139
r0-

Y Printed Circuit Board Layout

The rollover error causes the width of the + 0 count to be
larger than normal. The ICL7139 will thus read zero until
several hundred microvolts are applied in the positive direction. The ICL7139 will read -1 when approximately
-100)J-V is applied.
The rollover error can be minimized by guarding the Triple
Point ,and CAZ nodes with a trace connected to the CINT
pin, which is driven by the output of the integrator. Guarding
these nodes with the output of the integrator reduces the
stray capacitance to ground, which minimizes the charge
error on CINT and CAZ. If possible, the guarding should be
used on both sides of the PC board.

Considerations

Particular attention must be paid to rollover performance,
leakages, and guarding when designing the PCB for a
ICL7139-based multimeter.

Rollover Performance, Leakages, and
Guarding
Because the ICL71.39 system measures very low currents, it is essential that the PCB have low leakage. Boards
should be properly cleaned after soldering. Areas of particular importance are: 1) The INT VIn and INT I Pins; 2) The
Triple Point; 3) The ROEINT and the CAZ pins.
The conversion scheme used by the ICL7139 changes
the common mode voltage on the integrator and the capacitors CAZ and CINT during a positive deintegrate cycle. Stray
capacitance to ground is charged when this occurs, removing some of the charge on CINT and causing rollover error.
Rollover error increases about 1 count for each picofarad of
capacitance between CAZ or the Triple Point and ground,
and is seen as a zero offset for positive voltages. Rollover
error is not seen as gain error.

BACKPLANE

SEGMENT ON

SEGMENT OFF

~

I

L
I

.J
JL--,

VSEGMENT ON

---1

I

Stray Pickup
While the ICL7139 has excellent rejection of line frequency noise and pickup in the DC ranges, any stray coupling
will effect the AC reading. Generally, the analog circuitry
should be as close as possible to the ICL7139. The analog
circuitry should be removed or shielded from any 120V AC
power inputs, and any AC sources such as LCD drive waveforms. Keeping the analog circuit section close to the
ICL7139 will also help keep the area free of any loops, thus
reducing magnetically coupled interference coming from
power transformers, or other sources.
V·

VPEAK

VPEAKI2

0

DCOM

VRMS

Vf

VPEAK

ON

\/PEAK

OFF

VRMS

= (f

VPEAK

= 3V ± 10%

VPEAK

0
2.37V
RMS ON _
RMSOFF_1.06V

VPEAK

0
:VPEAK

(VOLTAGE ACROSS ON SEGMENn

Lr--J _

2VPEAK

VPEAK
VSEGMENT OFF

(VOLTAGE ACROSS OFF SEGMENT)

o
- VPEAK

0079-13

Figure 13: Duplexed LCD Drive Waveforms

INTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIeD OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valU9S have been characterized but are not tested.

2-78

ICL7139
10MEG

-""''''''-1

OEINTEGRATE

TRIPLE POINT

EXTERNAL
REFERENCE

INTEGRATE VOLT/OHM
INTEGRATE CURRENT

ICL8069

lM.g

' - - - - - - - - 1 REFERENCE INPUT

'-.....---------1 ANALOG COMMON

0079-14

Figure 14: External Voltage Reference Connection to ICL7139

...-J.,f.>/Ir.....--I 3.3 nF

•

10t.t.O.

IOMIl12

DEINT

LO BAT

DISPLAY
DRIVE
OUTPUTS

INT(V/Il)
10 kll 7

AC

mAVJ-IA

-3999

kllMIl

LOll
1 Mil 8
Hill

BEEPER

1 Mil 11
INT(I)
9.91l

0.11l
2W

10
18

ICL8069

V-

COMMON

VREF
V/Il/A
HIIl-DC/LOIl-AC

17

NOTE 1:
2:
3:
4:

y+

ICL7139

S4B

mA

16

mA/J-IA

HOLD

19

52

20

53

-lV'
-lV'

' - - - -.....-

Figure 15: Basic Multimeter Application Circuit for ICL7139

...... PIN 10

S2 Closed: Hill·DC
S3 Closed: Hold Reading
0079-15

Crystal is a Statek or SaRonix eX·lv type.
Multimeter protection components have not been shown,
Display is from LXD, part number 3BD3R02H.
Beeper is from muRata, part number PKM24·4AO.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH AESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FDA A PARTICULAR

use.

NOTE: All typicsl VSIUBS hSV9 been characterized but are not tested.

2·79

=
.. ICL7139

......

!:!

ICL7139

0079-16

Figure 16: PC Board Layout

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL

ae

IN LIEU OF ALL OTHER WAARANTIE:S, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY ANO FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-80

ICL7149
Low Cost 33/4-Digit
Autoranging Multimeter
GENERAL DESCRIPTION
The Intersil ICL7149 is a high perfor
autoranging digital multimeter IC. Unlike
anging
multimeter ICs, the ICL7149 always displays the result of a
conversion on the correct range. There is no "range hunting" noticeable in the display. The unit will autorange between the four different ranges in the DC voltage, DC current and resistance measurement modes. A manual switch
is used to select the 2 high group ranges. DC current ranges
are 4 mA and 40 mA in the low current group, 400 mA and
4A in the high current group. Resistance measurements are
made on 4 ranges, which are divided into two groups. The
low resistance ranges are 4/40 kilohms. High resistance
ranges are 0.414 megohms. Resolution on the lowest range
is 1 ohm.

• 18 Ranges:
4 DC Voltag_400 mY, 4V, 40V, 400V
2 AC Voltag_wlth Optional AC Circuit
4 DC Current-4 mA, 40 mA, 400 mA, 4A
4 AC Current with Optional AC Circuit
4 Reslstance-4 ko., 40 ko., 400 ko., 4 Mo.
• Autoranglng-Flrst Reading Is Always on Correct
Range
• On-Chip Duplex LCD Display Drive Including Three
Decimal Points and 11 Annunciators
• Low Power Dissipation-Less than 20 mW-1000
Hour Typical Battery Life
• Display Hold Input
• Continuity Output Drives Piezoelectric Beeper
• Low Battery Annunciator with On-Chip Detection
• Guaranteed Zero Reading for 0 Volts Input on All
Ranges

POL/AC
BP2
BP1

ORDERING INFORMATION

v+

Part
Number

V-

VREF
LOD.
HID.
DEINT

Temperature
Range

Package

ICL7149CPL

O·Cto +70·C

40 Pin Plastic DIP

*ICL7149CM44

O·Cto +70·C

44 Pin Surface Mount

'Consult Factory for Details

ANALOG - cOt.nol0N 10

HI.o.-DC/LO.o.-AC 19

0094-1

Figure 1: Pin Configuration

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

301672-001

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-81

•

ICL7149
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+ to V-) ......................... 15V

Storage Temperature Range ........... -65'C to + 130'C
Lead Temperature (Soldering, 10 sec) .............. 300'C

Reference Input Voltage (VREF to COM) ............... 3V
Analog Input Current. ........................... 100 /kA
(IN + Current or IN + Voltage)
Clock Input Swing ........................ V+ to V+ - 3

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
imp/led. Exposure to absolute maximum rating conditions for extended peri~

Power Dissipation (Plastic Package) ............. 800 mW
Operating Temperature Range ............. O'C to + 70'C

ods may affect device reliability.

ELECTRICAL CHARACTERISTICS v+ = +9.0V, TA
Yolts, test circuit as shown in Figure 3 Crystal Frequency = 120 kHz.
Parameter

=

+ 25'C, VREF adjusted for -3.700 reading on DC

Test Conditions

Zero Input Reading

YIN or liN or RIN = 0.00

Rollover Error (Note 1)

YIN or liN

=

Typ

Min
-00.0

Max

Units

+00.0

Y,l,Ohms

4

± Full Scale

Counts

-1

Linearity (Best Straight Line) (Note 5)
Accuracy DC Y, 400 Yolt Range Only

+1

Counts

±1

%ofRDG + 1

Accuracy DC Y, 400 Yolt Range Excluded

±0.2

% ofRDG + 1

Accuracy Ohms, 4K and 400K Range

±0.5

%ofRDG + 8

±1

%ofRDG + 9

Accuracy Ohms, 40K and 4Meg Range
Accuracy DC I, Unadjusted for FS

±0.5

%ofRDG + 1

Accuracy DC I, Adjusted for FS

±0.2

%ofRDG + 1

=

Open Circuit Yoltage for Ohms Measurements

RUNKNOWN

Noise (Note 2, 95% of Time)

YIN = 0, DC Yolts

Infinity

= 0, DC Yoltage Range

Supply Current

YIN

Analog Common (with Respect to Y+)

ICOMMON

Temperature Coefficient of Analog Common

ICOMMON < 10 p,A,
Temp = O'C-70'C

< 10 p,A

2.8

ICOMMON

Backplane/Segment Drive Yoltage

Average DC

2.7

Backplane/Segment Display Frequency
Switch Input Current (Note 3)

Y

0.1

LSB

1.5

2.4

3.0

3.2

-100

< 100 p,A
< 50 mY

Output Impedance of Analog Common

YREF

YIN

=

1

10

2.9

3.1

Y+

Ohms
Y
Hz

-50

Y+ toY-

Y
ppmrC

75

Switch Input Levels (High Trip Point)

mA

0.5

+50

p,A

Y+

Y
Y

Switch Input Levels (Mid Trip Point)

Y- + 3

Y+ - 2.5

Switch Input Levels (Low Trip Paint)

Y-

Y- + 0.5

Y

100

p,s

2000

Counts

Beeper Output Drive (Rise or Fall Time)

CLOAD

=

25

10 nF

Beeper Output Frequency

2

kHz

Continuity Detect

Range = Low Ohms,
YREF = 1.00Y

Power Supply Functional Operation

Y+ toY-

7

9

11

Y

Low Battery Detect (Note 4)

Y+ toY-

6.5

7

7.5

Y

500

NOTE 1: Rollover is defined as absolute value of negative reading minus absolute value of positive reading.

2: Noise is defined as the width of the uncertainty window (where the display will flicker) between two adjacent codes.
3: Applies to pins 17 -20.
4: Analog Common falls out of regulation when the Low Battery Detect is asserted, however the ICL7149 will continue to operate correctly with a supply
voltage above 7 volts and below 11 volts.
5: Guaranteed by design, not tested.
RDG = Reading

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE !N LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but arB not tested.

2-82

ICL7149
SWITCHES

V·V-COM

EXTERN.L
RESISTORS
.ND
C.P.CITORS

0094-2

Figure 2: Functional Diagram
33;'·Olglt Autoranglng OMM Using Intersn's ICL7149

LO B.T
TO
DlSPL.V

m.V;LA

-3999

.c

kliMIi

BEEPER 16
OUTPUT
V·

INPUTS
V!Il!;LA

•

ICL7149

m.o----....

-=- 9V
-=-BmERV

0.111

S2.

10 .NALOG
COM o----.....-1r-', COMMON

N/C~

N/C.Y---.

-=

SIB

17

v·~~r....,:;,:,:;-~ m./;LA

y-

I

Hill/DC
LOIl/.C

• OFF

HIIl.DC 19
LOIl ••C

S2B

N/C.e!-

~V·

~N/C

..2!!-

V+~

N~:~ :~r....,;;.SI",C_.:.la'in/V/A
v·.e!~v+

~N/C
0094-3

Figure 3: ICL7149 Test Circuit

INTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typiCal values have been characterized but are not tested.

2·83

.......~ ICL7149
g
1/0

Table 1: Pin Numbers and Functions
Pin Function
Pin Number

0
0
0

3

Backplane 1

I

4

V+

I

5

V-

I

6

Reference Input

0
0

7

LoOhms

8

Hi Ohms

1

Segment Driver, POll AC

2

Backplane 2

I/O

9

Deintegrate

I/O

10

Analog Common

I

11

Int I

I

12

IntV/Ohms

I

13

Triple Point

I

14

Auto Zero Capacitor (CAZ)

I

15

Integrate Capacitor (CINT)

0

16

Beeper Output

I

17

mAi/LA

I

18

OhmslV/A

DETAILED DESCRIPTION
General
Figure 2 is a simplified block diagram of the ICL7149. The
digital section includes all control logic, counters, and display drivers. The digital section is powered by V+ and Digital Common, which is about 3V below V+. The oscillator is
also in the digital section. Normally 120 kHz for rejection of
60 Hz AC interference and 100 kHz for rejection of 50 Hz
AC, the oscillator output is divided by two to generate the
internal master clock. The analog section contains the integrator, comparator, reference section, analog buffers, and
several analog switches which are controlled by the digital
logic. The analog section is powered from V + and V - .

DC VOLTAGE MEASUREMENT
Autozero

I

19

Hi Ohms-Dc/Lo Ohms-AC

Only those portions of the analog section which are used
during DC voltage measurements are shown in Figure 5. As
shown in the timing diagram (Figure 6), each measurement
starts with an autozero (AZ) phase. During this phase, the
integrator and comparator are configured as unity gain buffers and their non-inverting inputs are connected to Common. The output of the integrator, which is equal to its offset, is stored on CAZ, the autozero capacitor. Similarly, the
offset· of the comparator is stored in CINT. The autozero
cycle equals 1000 clock cycles, which is one 60 Hz line
cycle with a 120 kHz crystal, or one 50 Hz line cycle with a
100 kHz crystal.

I

20

Hold

Range 1 Integrate

0

21

Oscillator Out

I

22

Oscillator In

The ICL7149 performs a full autorange search for each
reading, beginning with range 1. During the range 1 integrate period, internal switches connect the INT V/Ohm terminal to the Triple Point (Pin 13). The input Signal is integrated for 10 clock cycles, which are gated out over a period of 1000 clock cycles to ensure good normal mode rejection of AC line interference.

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

23

Segment Driver kim

24

Segment Driver Ohms/ A

25

Segment Driver M Ohms/ /LA

26

Segment Driver Lo BatlV

Range 1 Deintegrate

27

Segment Driver Bo/Co

28

Segment Driver Ao/Do

At the beginning of the deintegrate cycle, the polarity of
the voltage on the integrator capacitor (CINT) is checked,
and either the DEINT+ or DEINT- is asserted. The integrator capacitor CINT is then discharged with a current equal to
VREF/RDEINT. The comparator monitors the voltage on
CINT. When the voltage on CINT is reduced to zero (actually
to the Vas of the comparator), the comparator output
switches, and the current count is latched. If the CINT voltage zero-crossing does not occur before 4000 counts have
elapsed, the overload flag is set. "OL" (overload) is then
displayed on the LCD. If the latched result is between 360
and 3999, the count is transferred to the output latches and
is displayed. When the count is less than 360, an underrange has occurred, and the ICL7149 then switches to
range 2-the 40V scale.

29

Segment Driver Go/Eo

30

Segment Driver Fo/DP1

31

Segment Driver B1/C1

32

Segment Driver A1/D1

33

Segment Driver G1 /E1

34

Segment Driver F1/DP1

35

Segment Driver B2/C2

36

Segment Driver A2/D2

37

Segment Driver G2/E2

38

Segment Driver F2/DP3

39

Segment Driver B3/C3

40

Segment Driver ADG3/E3

NOTE: For segment drivers, segments are listed as
(segment for backplane 1)/(segment for backplane 2).
Example: pin 27; segment BO is on backplane 1, segment CO is on
backplane 2.
INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical values have been characterized but are not tested

2-84

ICL7149
Range 2

Range 4

The range 2 measurement begins with an autozero cycle
similar to the one that preceded range 1 integration. range 2
cycle length however, is one AC line cycle, minus 360 clock
cycles. When performing the range 2 cycle, the signal is
integrated for 100 clock cycles, distributed throughout one
line cycle. This is done to maintain good normal mode rejection. Range 2 sensitivity is ten times greater than range 1
(100 vs 10 clock cycle integration) and the full scale voltage
of range 2 is 40V. The range 2 deintegrate cycle is identical
to the range 1 deintegrate cycle, with the result being displayed only for readings greater than 360 counts. If the
reading is below 360 counts, the ICL7149 again asserts the
internal underrange signal and proceeds to range 3.

This measurement is similar to the range 1, 2 and 3 measurements, except that the integration period is 10,000
clock cycles (10 line cycles) long. The result of this measurement is transferred to the output latches and displayed
even if the reading is less than 360.

Autozero
After finding the first range for which the reading is above
360 counts, the display is updated and an autozero cycle is
entered. The length of the autozero cycle is variable which
results in a fixed measurement period of 24,000 clock cycles (24 line cycles).

a. a. $. .til::, : •

DIGIT

Range 3
LOW

The range 3 or 4V full scale measurement is identical to
the range 2 measurement, except that the input signal is
integrated during the full 1000 clock cycles (one line frequency cycle). The result is displayed if the reading is greater than 360 counts. Underrange is asserted, and a range 4
measurement is performed if the result is below 360 counts.

BAT

AC

3

2

DP3

o

I

DP2

DPI

0094-4

Figure 4: Display Segment Nomenclature

ROEINT

VIN

INT

DEINTAZ

vin

o-.I\I\/'v--...:..-+--......-oc:r-.

VREF -«II-<....- ....- - - - - - - t

V+t-------e-~

6.7V

-+<

COMMONo-_ _C.;.;O;.:;t.1~M.;.;ON~.....

T= (lNT)(AR)(Az)
AR AUTORANGE CHOPPER
AZ AUTO ZERO
INT INTEGRAIT

=
=
=

V-t=======~

___________________________

~

0094-5

Figure 5: Detailed Circuit Diagram for DC Voltage Measurement

INTERSIL'S SOLE AND EXCWSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charact6rizeci but are not tssted.

2-85

.....

: ICL7149
..I

S:!

---I"L-

FIRST AUTO-ZERO

~

FIRST INTEGRATE

L

FIRST DEINTEGRATE

UNDERRANGE : _ _ _..I

----L.

L

AUTO-ZERO

SECOND AUTO-ZERO
SECOND INTEGRATE
SECOND DEINTEGRATE

___L

THIRD AUTO- ZERO

____rL-

THIRD INTEGRATE

L
UNDERRANGE :

L

AUTO-ZERO

UNDERRANGE : - - - . . I

THIRD DEINTEGRATE

---..I

____L

L

AUTO-ZERO

FOURTH AUTO-ZERO

L

FOURTH INTEGRATE

L

FOURTH DEINTEGRATE

L

AUTO-ZERO

I I1 2I 3I 4I 5I 6I 7I 8I 9I 10I 11I 12I 13I 14I 15I 16I 17I 18I 19I 20I 21I 2223
I I 24I

o

0094-6

Line Frequency Cycles
(1 Cycle = 1000 Internal Clock Pulses

= 2000 Oscillation Cycles)
Figure 6: Timing Diagram for DC Voltage Measurement

DC CURRENT

By using the lower value integration resistor, and only the
2 most sensitive ranges, the voltage drop across the current
sensing resistor is 40 mV maximum on the 4 mA and
400 mA ranges; 400 mV maximum on the 40 mA and 4A
scales. With some increase in noise, these "burden" voltages can be reduced by lowering the value of both the current sense resistors and the RINT I resistor proportionally.
The DC current measurement timing diagram is similar to
the DC voltage measurement timing diagram, except in the
DC current timing diagram, the first and second integrate
and delntegrate phases are skipped.

Figure 7 shows a simplified block diagram of the analog
section of the ICL7149 during DC current measurement.
The DC current measurements are very similar to DC voltage measurements except: 1) The input voltage is developed by passing the input current through a 0.1 ohm (HI
current ran~es), or 9.9 ohm (LOW current ranges) current
sensing resistor; 2) Only those ranges with 1000 and 10 000
clock cycles of integration are used; 3) The RINT I resist~r is
1 megohm, rather than the 10 megohm value used for the
RINT V resistor.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAi STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE

~~~~~~~~~~L~~~~L~ ~~N~~;L~;~~ ::~Tl~~~~ ~;~~

LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES

NOTE: All typical values have been characterized but are not tested.

2-86

OF

IiID~Do..

ICL7149
AC VOLTAGE MEASUREMENT

Oscillator

The ICL7149 is designed to be used with an optional AC
to DC voltage converter circuit. It will autorange through two
voltage ranges (400V and 40V), and the AC annunciator is
enabled as with the ICL7139. A typical averaging AC to DC
converter is shown in Figure 8, while an RMS to DC converter is shown in Figure 9. AC current can also be measured with some simple modifications to either of the two
circuits in Figures 8 and 9.

The ICL7149 uses a parallel resonant-type crystal in a
Pierce oscillator configuration, as shown in Figure 13, and
requires no other external components. The crystal eliminates the need to trim the oscillator frequency. An external
signal may be capacitively coupled to OSC IN, with a signal
level between 0.5V and 3V pk-pk. Because the OSC OUT
pin is not designed to drive large external loads, loading on
this pin should not exceed a single CMOS input. The oscillator frequency is internally divided by two to generate the
ICL7149 clock. The frequency should be 120 kHz to reject
60 Hz AC signals, and 100 kHz to reject 50 Hz signals.

Ratiometrlc Ohms Measurement
The ratiometric ohms measurement is performed by first
integrating the voltage across an unknown resistor, Rx, then
effectively deintegrating the voltage across a known resistors (RKNOWN1 or RKNOWN2 of Figure 10). The shunting
effect of RINTV does not affect the reading because it cancels exactly between integration and deintegration. Like the
current measurements, the ohm measurements are split
into two sets of two ranges. LO ohms measurements use a
10 kilohm reference resistor, and the full scale ranges are 4
and 40 kilohms. HI ohms measurements use a 1 megohm
reference resistor, and the full scale ranges are 0.4 and 4
megohms. The measurement phases and timing are the
same as the measurement phases and timing for DC current except: 1) During the integrate phases the input voltage
is the voltage across the unknown resistor Rx, and; 2) During the deintegrate phases, the input voltage is the voltage
across the reference resistor RKNOWN1 or RKNOWN2.

Figure 14 shows typical LCD Drive waveforms, RMS ON,
and RMS OFF voltage calculations. Duplex multiplexing is
used to minimize the number of connections between the
ICL7149 and the LCD. The LCD has two separate backplanes. Each drive line can drive two individual segments,
one referenced to each backplane. The ICL7149 drives 3%
7-segment digits, 3 decimal points, and 11 annunciators.
Annunciators are used to indicate polarity, low battery condition, and the range in use. Peak drive voltage across the
display is approximately 3V. An LCD with approximately
1.4V RMS threshold voltage should be used. The third voltage level needed for duplex drive waveforms is generated
through an on-chip resistor string and the DC component of
the drive waveforms is guaranteed to be less than 50 mY.

Continuity Indication

Ternary Input

When the ICL7149 is in the LO ohms measurement
mode, the continuity circuit .of Figure 11 will be active. When
the voltage across Ax is less than approximately 100 mV,
the beeper output will be on. When R3 is 10 kilohms, the
beeper output will be on when Rx is less than 1 kilohm.

The OhmslVolts/ Amps logiC input is a ternary, or 3-level
input. This input is internally tied to the common voltage
through a high-value resistor, and will go to the middle, or
"Volts" state, when not externally connected. When connected to V -, approximately 5 p.A of current flows out of
the input. In this case, the logiC level is the "Amps", or low
state. When connected to V +, about 5 p.A of current flows
into the input. Here, the logic level is the "Ohms", or high
state. For other pins, see Table 2.

Display Drivers

Common Voltage
The analog and digital common voltages of the ICL7149
are generated by an on-chip resistor/zener/diode combination, shown in Figure 12. The resistor values are chosen so
the coefficient of the diode voltage cancels the positive
temperature coefficient of the zener voltage. This voltage is
then buffered to provide the analog common and the digital
common voltages. The nominal voltage between V+ and
analog common is 3V. The analog common buffer can sink
about 20 mA, or source 0.01 mA, with an output impedance
of 10 ohms. A pullup resistor to V+ may be used if more
sourcing capability is desired. Analog common may be used
to generate the reference voltage, if desired.

Table 2: Ternary Inputs Connections
Pin
Number

y+

OPEN
or COM

y-

17

mA

p.A

Test

18

Ohms

Volts

Amps

19

HiO/DC

LoO/AC

Test

20

Hold

Auto

Test

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typk;sJ_ ""ve betJn _ _ but.,. not __

2-87

n
I'"

......
CD

~

ICL7149

i

COMPONENT SELECTION

......

For optimum performance while maintaining the low-cost
advantages of the ICL7149, care must be taken when selecting external components. This section reviews specifications and performance effects of various external components.

Integrator Capacitor, CINT
As with all dual-slope integrating convertors, the integration capacitor must have low dielectric absorption to reduce
linearity errors. Polypropylene capacitors add undetectable
errors at a reasonable cost, while polystyrene and polycarbonate may be used in less critical applications. The
ICL7149 is designed to use a 3.3 nF (0.0033 ,...F) CINT with

an oscillator frequency of 120 kHz and an RINTV of 10 megohms. With a 100 kHz oscillator frequency (for 50 Hz line
frequency rejection), both CINT and RINTV affect the voltage
swing of the integrator. Voltage swing should be as high as
possible without saturating the integrator, which occurs
when the integrator output is within 1V of either V + or V - .
Integrator voltage swing should be about ± 2V when using
standard component values. For different RINTV and oscillator frequencies the value of CINT can be calculated from:
CINT =

(Integrate Time) x (Integrate Current)
(Desired Integrator Swing)
(10,000

x 2 x Oscillator Period) x O.4V/RINTV
(2V)

ROEINT

DEINTAZ

INT I

LOW I
RINTI

9.9.0.
YREF
HIGH I

y+
0.1.0.

COMMON

6.7Y

COMMON

Y-t::====~

=
=
=

T (INT)(AR)(AZ)
AR = AUTO RANGE CHOPPER
AZ AUTOZERO
INT INTEGRATE

_________--1
0094-7

Figure 7: Detailed Circuit Diagram for DC Current Measurement

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but 8(9 not tested.

ICL7149

100 kD.

20MD.

.ltll.fItr---------.........-=i

YINo-....
o-400YAC
0-1000 Hz

100kD.

50kD.

20MD.

ICL7149

COM o-_ _ _...._ _ _ _ _ _ _ _~.....- - - - - - - - - -......
l0"'l COMMON
0094-8

NOTE: Diodes are low-leakage 10100.

Figure 8: AC Voltage Measurement Using Optional Averaging Circuit
2.2~F

...cr
YIN
0-400VAC
50-1000Hz

y+

10MD.

12

ICL7149

y+

4.99 kD.

INT(V/D.)

V30kD.
10

COM

COMMON
0094-9

Figure 9: AC Voltage Measurement Using Optional RMS Converter Circuit

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIeD WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical va/uss have been characterized but are not tested.

2-89

.......~

.D~DI!..

ICL7149

...g
ROEINT
ROEINT

INT

AZ

Y/.o.

RX
LO.o.
RKNOWN 1
HI.o.

T=INT+ OEINT
AZ = AUTOZERO
INT = INTEGRATE

RKNOWN2
COMMON

0094-10

Figure 10: Detailed Circuit Diagram for Ratiometric Ohms Measurement
LO OHM r

-------

- - - - - - .,

RKNOWN

RUNKNOWN

BEEPER OUTPUT

Rx

I
COM

I

.

Vx = 100 mY

--

-- --- - .

0094-11

Figure 11: Continuity Beeper Drive Circuit

NOTE: The ICL7139 contains a comparator that is enabled on the lowest ohms range. It trips at approximately y. of the full scale value of that range and enables
the beeper driver to OSCillate (between V- and V+) at 2 kHz. The beeper driver is capable of driving a piezo-electric transducer. The beeper output
response is independent of the state of the conversion; therefore appears instantaneous to the user. Some applications may require a 150 pF capacitor
between pin 4 and pin 8 to insure a sharp onloff continuity detection.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICL.E OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLieD WARRANTies OF

MERCHANTABILlTX, AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but ar8 not tested.

2·90

ICL7149
The ideal CAZ is a low leakage polypropylene or Teflon
capacitor. Other film capacitors such as polyester, polystyrene, and polycarbonate introduce negligible errors. If a few
seconds of settling time upon power-up is acceptable, the
CAZ may be a ceramic capacitor, provided it does not have
excessive leakage.

Integrator Resistors
The normal values of the RINT v and RINT I resistors are
10 megohms and 1 megohm respectively. Though their absolute values are not critical, unless the value of the current
sensing resistors are trimmed, their ratio should be 10:1,
within 0.05%. Some carbon composition resistors have a
large voltage coefficient which will cause linearity errors on
the 400V scale. Also, some carbon composition resistors
are very noisy. The class" A" output of the integrator begins
to have nonlinearities if required to sink more than 70 ",A
(the sourcing limit is much higher). Because RINT v drives a
virtual ground point, the input impedance of the meter is
equal to RINT V.

Ohms Measurement Resistors
Because the ICL7149 uses a ratiometric ohms measurement technique, the accuracy of ohms reading is primarily
determiner:! by the absolute accuracy of the RKNOWNI and
RKNOWN2. These should normally bEllO kilohms and 1 meg6hm, with an absolute accuracy of at least 0.5%.

Current Sensing Resistors

Deintegration Resistor, ROEINT

The 0.1 ohm and 9.9 ohm current sensing resistors convert the measured current to a voltage, which is then measured using RINT I. The two resistors must be closely
matched, and the ratio between RINT I and these two resistors must be accurate-normally 0.5%. The 0.1 ohm resistor must be capable of handling the full scale current of 4
amps, which requires it to dissipate 1.6 watts.

Unlike most dual-slope AID converters, the ICL7149 uses
different resistors for integration and deintegration. RDEINT
should normally be the same value as RINTV, and have the
same temperature coefficient. Slight errors in matching may
be corrected by trimming the reference voltage.

Autozero Capacitor, CAZ

Continuity Beeper

The CAZ is charged to the integrator's offset voltage during the autozero phases, and subtracts that voltage from
the input Signal during the integrate phases. The integrator
thus appears to have zero offset voltage. Minimum CAZ value is determined by: 1) Circuit leakages; 2) CAZ self-discharge; 3) Charge injection from the internal autozero
switches. To avoid errors, the CAZ voltage change should
be less than 'Ao of a count during the 10,000 count clock
cycle integration period for the 400 mV range. These requirements set a lower limit of 0.047 ",F for CAZ but 0.1 ",F
is the preferred value. The upper limit on the value of CAZ is
set by the time constant of the autozero loop, and the line
cycle time period allotted to autozero. CAZ may be several
10s of microfarads before approaching this limit.

The Continuity Beeper output is designed to drive a piezoelectric transducer at 2 kHz (using a 120 kHz crystal), with a
voltage output swing of V+ to V-. The beeper output off
state. is at the V+ rail. When crystals with different frequencies are used, the frequency needed to drive the transducer
can be calculated by dividing the crystal frequency by 60.

Display
The ICL7149 uses a custom, duplexed drive display with
range, polarity, and low battery annunciators. With a 3 volt
peak display voltage, the RMS ON voltage will be 2.37V
minimum; RMS OFF voltage will be 1.06V maximum. Because the display voltage is not adjustable, the display
should have a 10% ON threshold of about 1.4V. Most

~~~--------------~--------------~------------v+
+

3V

ANALOG
COMMON

(PIN 10)

LO BAT

~----------------~~----------~~----t-~--V0094-12

Figure 12: Analog and Digital Common Voltage Generator Circuit

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are not tested.

2-91

II

.d... ICL7149
GI
'II'

-

display manufacturers supply a graph that shows contrast
versus RMS drive voltage. This graph can be used to determine what the contrast ratio will be when driven by the
ICL7149. Most display thresholds decrease with increasing
temperature, and the threshold at the maximum operating
temperature should be checked to ensure that the "off"
segments will not be turned "on" at high temperatures.

Applications, Examples, and Hints
A complete autoranging 3% digit multi meter is shown

in
Figure 16. The following sections discuss the functions of
specific components and various options.

Meter Protection
The ICL7149 and its external circuitry should be protected against accidental application of 11 0/220V AC line voltages on the ohms and current ranges. Without the necessary precautions, both the 7149 and its external components could be damaged under such fault conditions. For
the current ranges, fast-blow fuses should be used between
S5A in Figure 16 and the 0.1 ohm and 9.9 ohm shunt resistors. For the ohms ranges, no additional protection circuitry
is required. However, the 10 kilohm resistor connected to
pin 7 must be able to diSSipate 1.2W or 4.BW for short periods of time during accidental application of 11 OV or 220V
AC line voltages respectively.

Crystal
The ICL7149 is designed to use a parallel resonant
120 kHz or 100 kHz crystal with no additional external components. The Rs parameter should be less than 25 kilohms
to ensure oscillation. Initial frequency tolerance of the crystal can be a relatively loose 0.05%

Switches
Because the logic input draws only about 5 ",A, switches
driving these inputs should be rated for low current, or "dry"
operations. The switches on the external inputs must be
able to reliably switch low currents, and be able to handle
voltages in excess of 400V AC.

Reference Voltage Source
A voltage divider connected to V+ and Common is the
simplest source of reference voltage. While minimizing external component count, this approach will provide the
same voltage tempco as the ICL7149 Common-about
100 PPM/'C. To improve the tempco, an ICLB069 bandgap
reference may be used (see Figure 15). The reference voltage source output impedance must be ,;; RDEINT/4000.

330K

0094-13

Figure 13: Internal Oscillator Circuit Diagram

VPEAK

BACKPLANE

~
.
VOPEAK/2

V+
YAMS

~ ~ VPEAK

ON

YAMS

~ ~ VPEAK

OFF

DCOt.4

SEGt.4ENT ON

SEGt.4ENT OFr

1 . .___. .

VPEAK ~ 3V ± 10%

RMS ON -+ 2.37V
RMSOFF -+ 1.06V

--.J
VpEAK

(VOLTAGE ACROSS ON SEGMENT)

a
VSEGMENT ON
-2VpEAK

~

_ VPEAK

(VOLTAGE ACROSS OFr SEGt.4ENT)

~0

VSEGMENTOrr -

-VPEAK

0094-14

Figure 14: Duplexed LCD Drive Waveforms
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vsJu8S have been characterized but are not tested.

2-92

.D~OI!..

ICL7149

The rollover error causes the width of the + 0 count to be
larger than normal. The ICL7139 will thus read zero until
several hundred microvolts are applied in the positive direction. The ICL7139 will read -1 when approximately
-100 /JoV are applied.
The rollover error can be minimized by guarding the Triple
Point and CAZ nodes with a trace connected to the CINT
pin, which is driven by the output of the integrator. Guarding
these nodes with the output of the integrator reduces the
stray capaCitance to ground, which minimizes the charge
error on CINT and CAZ. If possible, the guarding should be
used on both sides of the PC board.

Printed Circuit Board Layout
Considerations
Particular attention must be paid to rollover performance,
leakages, and guarding when designing the PCB for a
ICL7149-based multimeter.

Rollover Performance, Leakages,
and Guarding
Because the ICL7139 system measures very low currents, it is essential that the PCB have low leakage. Boards
should be properly cleaned after soldering. Areas of particular importance are: 1) The INT v/n and INT I Pins; 2) The
Triple Point; 3) The ROEINT and the CAZ pins.
The conversion scheme used by the ICL7139 changes
the common mode voltage on the integrator and the capaci·
tors CAZ and CINT during a positive deintegrate cycle. Stray
capacitance to ground is charged when this occurs, remov·
ing some of the charge on CINT and causing rollover error.
Rollover error increases about 1 count for each picofarad of
capacitance between CAZ or the Triple Point and ground,
and is seen as a zero offset for positive voltages. Rollover
error is not seen as gain error.

While the ICL7149 has excellent rejection of line frequency noise and pickup in the DC ranges, any stray coupling
will affect the AC reading. Generally, the analog Circuitry
should be as close as possible to the ICL7149. The analog
circuitry should be removed or shielded from any 120V AC
power inputs, and any AC sources such as LCD drive waveforms. Keeping the analog circuit section close to the
ICL7149 will also help keep the area free of any loops, thus
reducing magnetically coupled interference coming from
power transformers, or other sources.
10MEG

10MEG
1 MEG

~

ICL8069~ ~

~

L

....
....

U»

Stray Pickup

- .... V+
10K

P

TRIPLE POINT
DEINTEGRATE
INTEGRATE VOLTjOHM
INTEGRATE CURRENT

EXTERNAL
REFERENCE

REFERENCE INPUT
ANALOG COMMON
0094-15

Figure 15: External Voltage Reference Connection to ICL7149

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPUED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AJI typical values have besn charscterized but arB not tested

2-93

•

....

: ICL7149

~

9

INPUTS
y/.n

10 M.n 7
1 t.1.n 8
1 t.1.n 11
A
S5A

LO BAT

DISPLAY
DRIYE
OUTPUTS

10 t.1.n12

AC

LO.n
HI.n

BEEPER

INT(I)

mAY#A

-3999

16

y+ 4

9.9.n

k.nM.n

PIN 4

ICL7149

10 k.n
1#F

COt.1t.10N

0.1.n
2W

10
18

S4B

y-

COt.1MON

YREF
y/.n/A
HI.n-DC/LO.n-AC

17

mA/#A

HOLD

ICL8069
6
19

S2

20

S3

.-J
.-J

......- - 4_ _-+ PIN 10
Y+
Y+

mA
0094-16
52 Closed: Hill·DC
53 Closed: Hold Reading

Figure 16: Basic Multlmeter Application Circuit for ICL7149
NOTE 1: Crystal is a 5tatek CX-1V type.
2: Multimeter protection components have not bean shown.

3: Display is from LXD. part number 38D3R02H.

4: Beeper is from muRata, part number PKM24-4AO.

0094-17

Figure 17: PC Board Layout

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typk;sJ vsluss have b86n chsracterized but are not tested.

2-94

ICL7182
101 Segment LCD Bargraph
AID Converter

."'."~\"<,,c

GENERAL DESCRIPTION

The Intersil ICL7182 is a complete an g- q,~T converter (ADC) that directly drives a mUltiple~1)~uid crystal
display (LCD). Included are a charge-balanced ADC, a
2.56V bandgap reference, display decode and driver, and a
50 kHz oscillator. Only a display and three passive components are required for a complete analog bargraph.
The fully differential analog and reference inputs may be
operated anywhere between and including the supply rails.
This allows sensing either ground-referenced Signals or
bridge configurations. Linearity and zero offset errors are
guaranteed to be less than 0.5% for a 1V full-scale input.
The full-scale differential input range is 200 mV to 1.1V.
The low drift 50 ppm/'C reference is trimmed to 1.5%
accuracy and, when used with a simple resistor divider, can
set the full-scale input voltage. The reference, when used
with an IntersillCL7660, extends the operating supply range
from 3V to 40V and allows sensing input signals below
ground.
The backplane and segment drivers supply the LCD with
the proper waveforms to create a discrete series of segments forming a 101 segment bar which is proportional to
the input voltage, with a plus or minus annunciator to indicate the polarity. In addition, three independent TIL controllable annunciators are provided for limit or unit indication.
The bargraph multiplexing scheme provides duplex contrast
ratio and allows the complete system to be placed in a standard 40 pin DIP. The LCD operating voltage is externally set
to adjust contrast for a range of fluid types and temperature.
The internal oscillator requires no external components
and establishes the conversion rate and backplane clock
frequency. The nominal conversion rate of 25 per second
can be easily changed between 15 to 40 conversions per
second by adding a Single capacitor or overdriving the oscillator.

•
•
•
•
•
•

1% Resolution ••• 100 Data Segments Plus Zero
No Missing Segments Guaranteed
Single 5V Supply Operation
Only Three Passive Components Required
True Differential Input and Reference
Direct LCD Display Drive Provides Duplex Contrast
Ratio
Overrange and Polarity Indication
Three User Defined Annunciators-Easily
Expandable
Precision On-Chip Reference ••• 50 ppml'C
Low Average Power Consumption ••• 1.8 mW
40 Pin DIP or 44 Pin Surface Mount Package
Extended Temperature Range Operation

T5

SEa.

Ax

SEGy

Ay

SEG>

Ax

SIGN

Tl

SEG7

OSC

SEGS

vee

SEG5

VRout

SEG4

REF HI

SEG3

REFLO

SEG2

INHI

SEGI

INLO

ORDERING INFORMATION
Part
Number

•
•
•
•
•
•

SEGO

COMMON

BPI

VSS

BP2

VDS

BP3
BP4

Temperature
Range

Package

BP13
BP12

BPS

ICL7182CPL

O'Cto +70'C

40 Pin Plastic

BPll

BPe

ICL71821PL

- 25'C to + 85'C

40 Pin Plastic

BPS

°ICL7182CM44

O'Cto +70'C

BP7

BPIO
21

BPS

44 Pin Plastic
0093-1

'Consult factory for details.

Figure 1: Pin Configuration

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
310675-001
NOTe: All typical VS//J9S hsve besn characterized but are not tested.

2-95

= ICL7182

.......

W ABSOLUTE

MAXIMUM RATINGS
Operating Temperature Range .......•.. - 2S·C to + as·c
Continuous Total Power Dissipation (TA = 2S·C)
40 Pin DIP Plastic Package ................... SOO mW
44 Pin CM Plastic Package ................... 37S mW

Supply Voltage (Vee to Vss) ........................ 1OV
Supply Voltage (Vee to Vos) ........................ 11 V
Display Drive Pin Voltage ...... (Vee + 0.3V) to (Vos -0.3V)
Analog or Reference Inputs .... (Vee + 0.3V) to (Vss - 0.3V)
Com, Osc, Ax, Ay,
Az, Tl, TS Pins ............. (Vee + 0.3V) to (Vss-0.3V)
Reference Output Current ......................... a rnA
Lead Temperature (Soldering, 10 sec) .............. 300·C
Storage Temperature Range ........... - 6S·C to + IS0·C

NOTE: Sfr9sses above those listed under ''Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended peri·
ods may affect device reliability.

ELECTRICAL CHARACTERISTICS Unless otherwise stated: Vee = S.OV, VSS = VOS = GND, TA = 2S·C,
VREF = 1.000V, VINeM = VREFeM = 2.SV, pin 6 open (Note 1)
Parameter
Zero Input Reading
Unadjusted Gain Error
Linearity Error
Rollover Error
Conversion Time
Display Update Rate
Input Referred Noise
DC Power Supply Rejection

Limits

Test Conditions

Units

Min

Typ

Max

-0
-1
-0.63
-O.S

±O
±O
±0.2
±0.1
400
2S
SOO
0.02

+0
+1
+0.63
+O.S

0.1
1.1

VIN = 1.0V (Note S)

0.02
1.0
1.3

SegslV
V
nA

VREFeM = O.SV to 4.SV
(Note 6)

0.01
6

0.1

SegslV
nA

2.S60
SO
1.3
20

2.S90
200
S

a

2

V
ppml"C
0
p.A
mA
p.V

VIN = O.OV
VIN = VREF
(Note 2)
VIN = - VREF (Note 3)

(Note 4)
Vee = 4.S to 6.OV

0.3

Segs
Segs
Segs
Segs
p.s
Hz
p.V
SegslV

ANALOG INPUT
Common Mode Rejection Ratio
Differential Mode Input
Average Input Current

VINeM = OV to SV, VIN "" OV

REFERENCE INPUT
Common Mode Rejection Ratio
Average Input Current
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
Output Impedance
Current Into VRout Pin
Current Out of VRout
Output Noise

Vee - VRout, lout = 0 p.A
- 2S·C < TA < as·c, lout = 0 p.A
lout = + 10 p.A to -2 mA

2.S20

10
0.1 Hz to 10 Hz (Note 4)

110

(Note 6)
(Note 6)
Guaranteed by PSRR

4.S

3S0
I.S
S.O

SOO
2.0
6.0

p.A
mA
V

Osc Pin Open
Osc Pin Open

26
2S

SI
SO

72
70

kHz
Hz

-SO

70
±10
60

200
SO
120

kO
mV
p.A

POWER SUPPLY
Supply Current Average
Supply Current Peak
Supply Voltage Range
OSCILLATOR
Oscillator Frequency
Backplane Frequency
DISPLAY DRIVE
Display Output Impedance
DC Component of Display
Vos Supply Current

Vee - Vos = 3Vt07V
Vee - Vos = 3Vt07V
Vee - Vos = 3V to 7V (Note 7)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical

Va/USB

have be9n characterized but are not tested.

2-96

ICL7182
ELECTRICAL CHARACTERISTICS (Continued) Unless otherwise stated: Vee =
= 25'C, VREF = 1.000V, VINeM = VREFeM = 2.5V, pin 6 open (Note 1)

5.0V, VSS

=

VOS

=

GND,

TA

Parameter

Limits

Test Conditions

Units

Typ

Max

0.001

0.8
+1

Min
ANNUNCIATOR INPUTS
Input High Voltage
Input Low Voltage
Input Leakage

Operating Temp Range
Operating Temp Range
Operating Temp Range

2.4
-1

NOTE 1: The differential mode input voltages are defined as: VIN ~ (IN HI - IN LO) and VREF ~ (REF HI
and VREFCM, is defined as the average differential input voltage with respect to ground.

-

REF

V
V
IJ-A

LO). The common mode input voltage,

VINCM

2: The linearity error is the deviation from a straight line which passes through negative full scale and postive full scale readings.
3: The rollover error is defined as the difference in reading for equal positive and negative inputs near full·scale.
4: Peak to peak value not exceeded 95% of the time (±2 standard deviations).
5: Defined as the average current flowing into the input with a 1.0

/,F

capacitor across

VIN

or VREF inputs and the common mode voltage at

Va vee.

6: The average supply current is measured with a supply bypass capacitor and annunciator inputs tied to VSS.
7: The supply current for

VDS

flows from the

VCC

pin.

PIN DESCRIPTION AND FUNCTION
Pin No.

Symbol

Description

1

T5

Test pin #5, buffered OSCillator frequency divided by two that can typically source and sink 2 mA.

2

Ax

Annunciator Segx select, low turns on Segx, high turns off Segx.

3

Ay

Annunciator Segy select, low turns on Segy, high turns off Segy.

4

Az

Annunciator Segz select, low turns on Segz, high turns off Segz.

5

T1

Test pin # 1, normally left open or tied to Vss.

6

Osc

50 kHz free running oscillator control and clock input pin. The internal oscillator may be
overdriven by a 30 to 80 kHz external clock driving pin 6, or the free running frequency can be
reduced by adding an external capaCitor between pin 6 and Vee.

7

Vee

Positive supply voltage.

8

VRout

Bandgap reference buffered output, down 2.56V from Vee.

9

REFHI

Positive Reference Input.

10

REFLO

11

INHI

Positive Analog Input.

12

INLO

Negative Analog Input.

13

Common

Negative Reference Input.

Internally generated voltage which is typically within ± 50 mV of Yo (Vee - Vss) and has 1.4 kO
output impedance. This pin is normally left open or bypassed with a 0.1 IJ-F capaCitor to signal
ground.

14

Vss

Negative supply voltage, normally ground.

15

Vos

Display negative voltage, establishes the pk-pk display drive.

16-28

BP13-BP1

29-36

SegO-Seg7

37

Sign

Positive sign segment driver.

38

Segz

Annunciator driver selected by Az.

39

Segy

Annunciator driver selected by Ay.

40

Segx

Annunciator driver selected by Ax.

LCD backplane drivers.
LCD segment drivers.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: All typical valU8S have b8en characterized but 8r9 not test9d.

2-97

......... ICL7182

.D~On..

~

CD

!i

,------------

Ax

Ay

A.

I

SEGX

OSC

SEGY
ANNUN·
CIATOR
DRIVERS

SEGZ
SIGN

I
I
VCC

SEGMENT
DECODE
AND
DRIVE

SOK
LCD
PHASE
GENERATOR
SOK
15
VDS
MSB

BACKPLANE
DECODE
AND
DRIVE

29-36 1
SEGO-SEG7

16-28
BP1-BP13

13

I

REFHI~
REF

n

LO~I-.:C~-(S()----'"
I

I

IN HI
IN LO LJ--~:r-:;S..
COMMON
VCC

STATE
MACHINE
VRout

STDBY

VSS

I
1

I
I
L _____ - -- - - - - - - -

I
I

______ ..J

0093-2

Figure 2: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been ch8rsctsrlzed but are not testBd.

2·98

IID~DIL

ICL7182

P
...
...

CD
N

ANNUNCIATORS
SIGN
OVERRANGE

lOG-=-

+5Vo-~~------~~

90

==

IN Hlo----------------\

GNDO------------+--~

20-=-

10

==

O'="
0093-3

Figure 3: ICL7182 using the internal reference.
Values shown are for 1.000V full-scale, 25 readings
per second, single 5V supply.

TYPICAL PERFORMANCE CHARACTERISTICS

C

s.
c

Average Analog Input Current vs.
Frequency and Common Mode Voltage

Average Reference Input Current vs.
Frequency and Common Mode Voltage

4 VIN _ O.OSOV
VREF
1.00V

18
VIN
0.050V
16 VREF
1.0iV

=

~

.'"

0

-1

I! -2

~

----r=
VCM

U

.5

--- -

VCM =

::I

5<>.

I

-3
-4

20

I!)!..

.....-

--

!

~

"

u

5<>.

I

.
.'"

.5

~M=5V

30

40

50

60

70

I!
~

-.....
80

./
. / .....

C 14

2.5V

I i"""- 'I

=
=

./

12

VCM = 4V./

10

./ ~

8

~
~~

6

.,.

"""..........
VCM = OV

'7

~

2

20

90

.JI'

30

40

50

60

70

80

90

Oscillator Frequency (kHz)

Oscillator Frequency (kHz)

0093-5

0093-4

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANnES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not testBd.

2·99

=
... ICL7182

...
i!

TYPICAL PERFORMANCE CHARACTERISTICS

(Continued)

Oscillator Frequency VB. Temperature
and Supply Voltage

Oscillator Frequency VS. Pin #6 Capacitor

I

24

25

23
22

4

i ~:
~

18

C5

12

........
......

:"

1

~

~

~

W

~

m

H

=

4.5V

L. ~

,I\-. vee = 5.OV

I........
5

-

~

glW

["'0..

o

5.5V~

"""~vee
V~ rr"

2
~

114
10

vee =

7

~40 -m

U

~

Pin .. Capacitance (pF)

0

20

40

80

80

100

Temperatura (OC)

0093-6

0093-7

Backplane Output Impedance VS.
Vos and Temperature

Annunciator Input Threshold VS.
Power Supply Voltage

~ 110

--'-

B 100

i1 :0 i\--'
0

\'

70

a
!

./

VT= 85·
...,.
~ ....... ...... TA = 25~
~"'" ~.l
TA =,:;(.'

50

1

'"

,~

60

40

./
./

,

~::r-

Iii 30

2345678

./

4.5

Display Voltage (VCC-VDS) (Volta)

5.0

5.5

8.0

Power Supply Voltage (VoIIs)

0093-8

Reference Bias Current VS.
Breakdown Voltage

30mA

~
H 2.580

~

15 10mA
~

0093-9

a 1mA
i 300uA
§ 100uA

J ~uA

~

i""'"

10UA
0.5

1.0

1.5

2.0

Referance Output Voltage WAr

2.5

2.575

i

2.570

"

2.560

I

V

3uA 0

~

t
I

3mA

3.0

vee (Vo1Is)

Reference Output va.Temperature

2.565

~

2.555

2.550
2.545

~

~

V

/

2.540
-55

-25

o

25

50

75

100

125

Temperature (OC)

0093-11

0093-10

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDmON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE· AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, ·El

-1
~)~C~~l
+

I

I,

~1
1

~1~
1

0--0

VSS

~

POINTS
ANNUNCIATORS,

ETC.

~1
I

D-T

LC~O..J

VDS

ND

0093-22

Figure 13: Using Exclusive 'OR' Gate for additional annunciator drivers.

V+

GND
TO DISPLAY
BACKPLANES

0093-23

Figure 14: 7182 measuring ratlometrlc values of Quad Load Cell.
The resistor values within bridge are determined by the desired sensitivity.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2·107

:: ICL7182
.......

g APPLICATIONS

(Continued)

- rVOO

V+
5.0V
R,
lOOK

R,
2.7M

17

4

L~

8

"'7
ICM
7555
U'

~

3

3

11 IN HI

1

U2

NC

0---1
INPUT

2

FROM

SW'<"'---o-

C, ...
',F

v-

,

'f

S ENSOR

2

'50K

R,
lOOK

ICL

+ 7621

R,

C,
220pF

VOO

100pF
2
C

w

R,
11M

ICL
7182

C,
0.47F

U3

NO

12

J

Roo

I/'V'"
::s 2:: LEOl
OPTIONAL

R"
4K
OPTIONAL

1M

~5
7
ICL
7621

CUT OFF 2N

"'-L

222r

r-----a

R,
12K

Roo
400K

R,
'OK

R
lOOK

VROlJT

9 REF HI

U2~6

()
IGNITION

.Y!lf!.

.Y.~

~

IN LO

'---

10 REF LO

R,
VSS

R,
12K

12K

1'4

GND

v0093-24

Vo =
VIN

1/RC
S + 1/R3C3

Ic = _ _
1_
211'R3C3

Switch SPST
@

Period

600

10

100 ms

1000

16.7

60ms

5000

SW1 Momentary
VIN = 264 mV
4 Stroke V8

Hz

RPM

10,000

83

No. of

Events

Strokes

Cylinders

Per Cycle

Per Cycle

12 ms

166,7

6ms

5000 RPM

1

0.5

4

4

2

4

6

3

4

8

4

4

Figure 15: Tachometer with Set Point

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not test9d.

2-108

ICL7182
APPLICATIONS

(Continued)
V+
ANNUNCIATORS
SIGN
OVERRANGE

VDD(7)
R,

4K
L-

R,

~

REF LO(10)
90

R

ICL7182
R,

-------------------

100-=-

REFHI(9)

~;- INHI(ll)

~

==
··

•

·
-------------------------------

20-=~ VROUT(9)

IN LO(12)

+

~AD580

10"="
R.

=

24K

VSS(14)

O"="

V0093-25

Figure 16: Basic digital thermometer, Celsius and Fahrenheit scales.
This Vos pin can be connected as shown in Figure 11.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valUBs haV9 been characterizsd but are not tssfed

2·109

Section 3 -

AID Converters
~p Type
ADC0802 ............... 3-1
ADC0803 ............... 3-1
ADC0804 ............... 3-1
ICL7104/1CL8052 ...... 3-19
ICL7104/1CL8068 ...... 3-19
ICL71 09 ............... 3-39
ICL7112 ............... 3-58
ICL7115 ............... 3-60
ICL7135 ............... 3-74

ADC0802-ADC0804
8-Bit JLP-Compatible
AID Converters
GENERAL DESCRIPTION

FEATURES

The ADCOS02 family are CMOS S-bit successive approximation AID converters which use a modified potentiometric
ladder. and are designed to operate with the SOSOA control
bus via three-state outputs. These converters appear to the
processor as memory locations or 1/0 ports. and hence no
interfacing logic is required.
The differential analog voltage input has good commonmode-rejection. and permits offsetting the analog zero-input-voltage value. In addition. the voltage reference input
can be adjusted to allow encoding any smaller analog voltage span to the full S bits of resolution.

• 80C48 and 80C80/85 Bus Compatible - No
Interfacing Logic Required
• Conversion Time < 100,...s
• Easy Interface to Most Microprocessors
• Will Operate In a "Stand Alone" Mode
• Differential Analog Voltage Inputs
• Works With Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• OV to 5V Analog Voltage Input Range (Single
Supply)
• No Zero-Adjust Required

+ 5V

ORDERING INFORMATION
Part
Number

Error

Temperature
Range

Package

ADCOS02LCN
ADCOS02LCD
ADCOS02LD

± '12 bit no adjust
± % bit no adjust
± 1 bit no adjust

O'Cto +70'C
-40'C to + S5'C
-55'C to + 125'C

20 pin Plastic DIP
20 pin CERDIP
20 pin CERDIP

ADCOS03LCN
ADCOS03LCD
ADCOS03LD

± '12 bit adjusted full-scale
± % bit adjusted full-scale
± 1 bit adjusted full-scale

O'Cto +70'C
-40'Cto +S5'C
- 55'C to + 125'C

20 pin Plastic DIP
20 pin CERDIP
20 pin CERDIP

ADCOS04LCN
ADCOS04LCD

± 1 bit no adjust
± 1 bit no adjust

O'Cto +70'C
-40'Cto +S5'C

20 pin Plastic DIP
20 pin CERDIP

cs

1
2
RD
3
WR
5
INTR
11
DB,
12
DBo
13
Oils
14
Os.
15
DB,
16
DB.
17
DB,
18
DBo

Y+

cs u:~~ V+ORVREF

-;-0.

CLKR
eLKIN
AID
I.INI +)
1.11«-1

4

10k

...!..o}
2..0_
8

8

AD [!
WR [!

d~

CLK IN

f·BIT RESOLUTION
DIFF
OYER ANY DESIRED
INPUTS ANALOG INPUT
YOLTAGE RANGE

AGND
YREFI2

I.INI+I

~

I.INI-)

[!:

ADC0804

AGND

':'

DGND
0334-1

Figure 1: Typical Application

ADC0802-

~
YREFI2 [!:

..!..o YREF121

DGND~

INTR

~
[!

~

~

CLKR

~

DBo (LSB)

1m DB,
1m DB.
~

DB,

~
~

DBs

~

DBo

~

DB, (MSB)

Os.

TOP VIEW
0334-2

(Outline dwg. CD, CN)
Figure 2: Pin Configuration

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been charact9rizsd but arB not f9stiJd.

3-1

•

~

co
o

§
I

.D~Dn.

ADC0802-ADC0804
iii) 2

READ

C\I

o

"1" = RESET SHIFT REGISTER
"0" - BUSY AND RESET STATE

CO

i

RESET

INPUT PROTECTION
FOR ALL LOGIC INPUTS

j::

INPUT

CLK

TOINTERNAL
CIRCUITS
BV .. 30V

V+
(VAEF)

START
CONVERSION

20

J"L

0".--....----+1

VAEFI2

LADDER
AND
DECODER

I+++-+- 1kO). If input bypass capacitors are necessary for noise filtering and high
source resistance is desirable to minimize capacitor size,
the effects of the voltage drop across this input resistance,
due to the average value of the input current, can be compensated by a full-scale adjustment while the given source
resistor and input bypass capacitor are both in place. This is
possible because the average value of the input current is a
precise linear function of the differential input voltage at a
constant conversion rate.

R
VREF/2

9

,R

~}-

II DECODE

I I
DIGITAL
CIRCUITS

•

H I
ANALOG
CIRCUITS

~}-

Input Source Resistance
Large values of source resistance where an input bypass
capacitor is not used, will not cause errors since the input
currents settle out prior to the comparison time. If a lowpass filter is required in the system, use a low-value series
resistor (';; 1k!l) for a passive RC section or add an op amp
RC active low-pass filter. For low-source-resistance applications, (';; 1k!l), a 0.1,..F bypass capacitor at the inputs will
minimize EMI due to the series lead inductance of a long
wire. A 100!l series resistor can be used to isolate this capacitor (both the Rand C are placed outside the feedback
loop) from the output of an op amp, if used.

AGND 8

DGN,!;';'O

-==
0334-22

Figure 7: The VREFERENCE Design on the

Ie

Notice that the reference voltage for the IC is either 'fa of
the voltage which is applied to the V+ supply pin, or is
equal to the voltage which is externally forced at the VREFI
2 pin. This allows for a pseudo-ratiometric voltage reference
using, for the V+ supply, a SV reference voltage. Alternatively, a voltage less than 2.SV can be applied to the VREFI
2 input. The internal gain to the VREF/2 input is 2 to allow
this factor of 2 reduction in the reference voltage.
Such an adjusted reference· voltage can accommodate a
reduced span or dynamic voltage range of the analog input
voltage. If the analog input voltage were to range from O.SV
to 3.SV, instead of OV to SV, the span would be 3V. With
O.SV applied to the VIN(-) pin to absorb the offset, the reference voltage can be made equal to % of the 3V span or
1.SV. The AID now will encode the VIN( +) signal from O.SV
to 3.SV with the O.SV input corresponding to zero and the
3.SV input corresponding to full-scale. The full 8 bits of resolution are therefore applied over this reduced analog input
voltage range. The requisite connections are shown in Figure 8. For expanded scale inputs, the circuits of Figures 9
and 10 can be used.

Stray Pickup
The leads to the analog inputs (pins 6 and 7) should be
kept as short as possible to minimize stray signal pickup
(EM I). Both EMI and undesired digital-clock coupling to
these inputs can cause system errors. The source resistance for these inputs should, in general, be kept below Sk!l.
Larger values of source resistance can cause undesired signal pickup. Input bypass capacitors, placed from the analog
inputs to ground, will eliminate this pickup but can create
analog scale errors as these capcitors will average the transient input switching currents of the AID (see Analog Input
Current). This scale error depends on both a large source
resistance and the use of an input bypass capacitor. This
error can be compensated by a full-scale adjustment of the
AID (see Full-Scale Adjustment) with the source resistance and input bypass capacitor in place, and the desired
conversion rate.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

3-11

g ADC0802-ADC0804
CD

o

g
C
I

(\I

o

digital output code. In absolute conversion applications,
both the initial value and the temperature stability of the
reference voltage are important accuracy factors in the operation of the AID converter. For VREF/2 voltages of 2.5V
nominal value, initial errors of ± 1OmV will cause conversion
errors of ± 1LSB due to the gain of 2 of the VREF/2 input. In
reduced span applications, the initial value and the stability
of the VREF/2 input voltage become even more important.
For example, if the span is reduced to 2.5V, the analog
input LSB voltage value is correspondingly reduced from
20mV (5V span) to 10mV and 1LSB at the VREF/2 input
becomes 5mV. As can be seen, this reduces the allowed
initial tolerance of the reference voltage and requires correspondingly less absolute change with temperature variations. Note that spans smaller than 2.5V place even tighter
requirements on the initial accuracy and stability of the reference source.
In general, the reference voltage will require an initial adjustment. Errors due to an improper value of reference voltage appear as full-scale errors in the AID transfer function.
IC voltage regulators may be used for references if the ambient temperature changes are not excessive.

VREF
(5V)

CD

§

> .....,.,.,,..,..,..... TO
VREF/2

C
~r-~

__

~~~~

____________-.TO
VIN(-)

0334-23

Figure 8: Offsetting the Zero of the ADC0802 and
Performing an Input Range (Span) Adjustment

Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not ground,
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage by biasing the AID VIN(-) input at this VIN(MIN) value
(see Applications section). This utilizes the differential
mode operation of the AID.
The zero error of the AID converter relates to the location of the first riser of the transfer function and can be
measured by grounding the VIN(-) input and applying a
small magnitude positive voltage to the VIN( +) input. Zero
error is the difference between the actual DC input voltage
which is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal % LSB
value (% LSB = 9.8mV for VREF/2 = 2.500V).

5V

(VREF)
R
VIN

"

2R

6 V'N(.)

:tl0V
2R

~

v+

~

$'O#F

ADC0602ADC0604
V,N(-)

":::0334-24

Figure 9: Handling ± 10V Analog Input Range

Full-Scale Adjust
The full-scale adjustment can be made by applying a differential input voltage which is 1% LSB down from the desired analog full-scale voltage range and then adjusting the
magnitude of the VREF/2 input (pin 9) for a digital output
code which is just changing from 11111110 to 1111 1111.
When offsetting the zero and using a span-adjusted VREF/2
voltage, the full-scale adjustment is made by inputting VMIN
to the VIN(-) input of the AID and applying a voltage to the
VIN(+) input which is given by:

5V

(VREF)
R
V,N

:tsv

"

R

6 V'N(.)

v+ 20

ADC0602ADC0604

~

-+

f

'O• F

.
[(VMAX-VMIN)]
256
'
VIN(+)fsadJ=VMAX-l.5

V'N(-)

where:
VMAX=the high end of the analog input range
and
VMIN=the low end (the offset zero) of the analog range.
(Both are ground referenced.)

0334-25

Figure 10: Handling ± 5V Analog Input Range

Reference Accuracy Requirements
The converter can be operated in a pseudo-ratiometric
mode or an absolute mode. In ratio metric converter applications, the magnitude of the reference voltage is a factor in
both the output of the source transducer and the output of
the AID converter and therefore cancels out in the final

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3-12

ADC0802-ADC0804
Clocking Option

Restart During a Conversion

The clock for the AID can be derived from an external
source such as the CPU clock or an external RC network
can be added to provide self-clocking. The ClK IN (pin 4)
makes use of a Schmitt trigger as shown in Figure 11.
Heavy capacitive or DC loading of the ClocK R pin
should be avoided as this will disturb normal converter operation. loads less than 50pF, such as driving up to 7 AID
converter clock inputs from a single ClK R pin of 1 converter, are allowed. For larger clock line loading, a CMOS or low
power TTL buffer or PNP input logic should be used to minimize the loading on the ClK R pin (do not use a standard
TTL buffer).

If the AID is restarted (CS and WR go low and return
high) during a conversion, the converter is reset and a new
conversion is started. The output data latch is not updated if
the conversion in progress is not completed. The data from
the previous conversion remain in this latch.

Continuous Conversions
In this application, the CS input is grounded and the WR
input is tied to the INTR output. This WR and INTR node
should be momentarily forced to logic low following a power-up cycle to insure circuit operation. See Figure 12 for
details.

ADC0802ADCOS04

CLK R
19

>C>-~.CLK

1
'elK= 1.1 RC
R=10kO

0334-26

Figure 11: Self-Clocking the AID

10k

r-~-o--1:-tCS
2Rl)

r-~----.-~~3~WR
N.O.L.----+-~...:4=iCLK IN

~

START

: INTR
ANALOG

7 VIN(+)

ADCOB02ADC0804

INPUTSO-C~:i
8 VIN(-)

r------2 clock. All 110 devices are memorymapped in the 6800 system, and a special signal, VMA,
indicates that the current address is valid. Figure 16 shows
an interface schematic where the AID is memory-mapped
in the 6800 system. For simplicity, the CS decoding is
shown using % DM8092. Note that in many 6800 systems,
an already decoded % line is brought out to the common
bus at pin 21. This can be tied directly to the CS pin of the
AID, provided that no other devices are addressed at HEX
ADDR: 4XXX or 5XXX.
In Figure 19 the ADC0802 series is interfaced to the
MC6800 microprocessor through (the arbitrarily chosen)
Port B of the MC6820 or MC6821 Peripheral Interface
Adapter (PIA). Here the CS pin of the AID is grounded since
the PIA is already memory-mapped in the MC6800 system
and no CS decoding is necessary. Also notice that the AID
output data lines are connected to the microprocessor bus
under program control through the PIA and therefore the AI
D RD pin can be grounded.

This converter has been designed to directly interface
with 8080/85 or Z-80 Microprocessors. The 3-state output
capability of the AID eliminates the need for a peripheral
interface device, although address decoding is still required
to generate the appropriate CS for the converter. The AID
can be mapped into memory space (using standard memory-address decoding for CS and the MEMR and MEMW
strobes) or it can be controlled as an 110 device by using
the 110 Rand lID W strobes and decoding the address bits
AO --+ A7 (or address bits A8 --+ A15, since they will
contain the same 8-bit address information) to obtain the
CS input. Using the 110 space provides 256 additional addresses and may allow a simpler 8-bit address decoder, but
the data can only be input to the accumulator. To make use
of the additional memory reference instructions, the AID
should be mapped into memory space. See A020 for more
discussion of memory-mapped vs lID-mapped interfaces.
An example of an AID in 110 space is shown in Figure 16.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: An typical values havs be8n charsoterized but are not tested.

3-15

•

~

ADC0802-ADC0804

CD

§
I

&\I

o

INT(14)

.".

CD

o

UOWR(27)·

§

iiOiiD (25).
10k
yy

'-'

1CS

RD
~-

Y+
CLKR

~Wii
4

ANALOG
INPUTS

...

-

!_

(LSB)DBo

CLKIN

DB1
DBa
ADC0802ADC0804
DBa
DB4
DBs
Die
(MSB)DB7

INTR

7

V\N(+)
V\N(-)
150pFrt AGND

-T ":' o!o
1

~

YREFJ2
DGND

~5Y
18
17
16
15
14
13
12
11

~101'F

r

DSo(13)"
DB1 (16)·
DBa (11)·
DBa (9).
DB4(5)·
Des (16)·
Die (20)·
DB7m·

5Y

I

~

OUT

Y+

I

~

Ts
T4
'--- T3
r-- T2
~ T1
~ To

......

T

8131
BUS
COMPARATOR

Bs
B4
Ba

B2
B1
So

1

Ao,s (36)
Ao,4 (39)
Ao,3 (38)
Ao,2 (37)
Ao,1 (40)
Ao,o (1)

1

,h
0334-31
Note: Pin numbers for 8228 system controller: others are 8080A

Figure 16: ADC0802 to 8080A CPU Interface

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3-16

.o~on..

ADC0802-ADC0804

CD

APPLICATION NOTES

o

N

Some applications bulletins that may be found useful are
listed here:
A016 "Selecting AID Converters," by Dave Fullagar.
A018 "Do's and Oont's of Applying AID Converters," by
Peter Bradshaw and Skip Osgood.
A020
A030
R005

I

iffi2
ADC0802-

"A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing," by Ed Sliger.
"The ICL7104 - A Binary Output AID Converter for
Microprocessors," by Peter Bradshaw.
"Interfacing Data Converters & Microprocessors,"
by Peter Bradshaw et ai, Electronics, Dec. 9, 1976.

WR3

.....

5

INPUTS ,..

-

7

F

"-/

,,:,"-

/"/1

( ABC]
5V(8) 123

'='

18

00(33)(31)

.... 1.

(LSB)D80 17
ADCOI02ADC0804

~ AGNO
'lReF12

o-fo-

150pF .......

CLK R .!!...

CLKIN

YlNC+)
YlNC-)

Dt (32)(2tJ

DI2 15

DBa
DB4

DIs

Dz(31)[KJ

~

Da(3O)'IHl

14
13

D4(28)(32J

Ds(2I1U3OJ

O. 12
(MSB)DB7 11

DONO

•

RIW(34)[I]

r::lt,
V+~~ '1:'"10,.

~ RD

"--ic Viii
• iiffili

CD

0334-32

.

CS

.

o

Figure 17: Mapping the AID as an I/O device for
use with the Z-80 CPU

~
1

ADC0804

§

74C32

.A

ANALOG

§

De(27)jij

~

D7(28)f,ij

¥
1
2

•.r-3
~O~4
5

Al2 (22) 134)

.A

....~

.....

Al3 (23)INJ

, Al4 (24)IMJ

,

All (25) (33)

VMA (5) IFJ
0334-33

'Nota 1: Numbers in parentheses refer to MC6800 CPU pinout.
"Note 2: Numbers or letters In brackets refer to standard MC6800 system oommon bus oede.

Figure 18: ADC0802 to MC6800 CPU Interface

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDlTION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical values have b8en chsrscteriz6d but are not testsd.

3-17

~

at

ADC0802-ADC0804

i
i
I

(II

18

at

19

o

1CIIc

CB1
CEb

yy

1

1
2

J.,

~
4

iiD
\iii
CLKIN

5
e- iNfR

....
ANALOG

7

INPUTS
150p

-

CS

F=~

8

40

\/aN(+)
YlN(-)

AGND
VREFI2
DGND

'\".J

MC8820
(MCS862O)

y+ 20

~5Y

CLKR
(LSB)D80
D81
ADC0802DEb
ADC0804
D83

18
17
18
15
14
13
DBs
12
DBs
11

De..

(MS81D87

10
11
12
13
14
15
16
17

PBo

PIA

PB1
PEb

psa
pe..

PBs
PBs
P87

Ii 7¥
0334-34

Figure 19: ADC0802 to MC6820 PIA Interface

INTERSIL'S SOLE AND EXClUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE ODNDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vaIuss have bstm chsracfBtfud but lU8 not tssted.

3-18

ICL8052/ICL 7104
and ICL8068/ICL7104
14/16-Bit p,P-Compatible
2-Chip AID Converter
GENERAL DESCRIPTION

FEATURES

The ICL71 04, combined with the ICL8052 or ICL8068,
forms a member of Intersil's high performance AID converter family. The ICL7104-16, performs the analog switching
and digital function for a 16-bit binary AID converter, with
full three-state output, UART handshake capability, and other outputs for easy interfacing. The ICL7014-14 is a 14-bit
version. The analog section, as with all Intersil's integrating
converters, provides fully precise Auto-Zero, Auto-Polarity
(including ± 0 null indication), single reference operation,
very high input impedance, true input integration over a constant period for maximum EMI rejection, fully ratio metric operation, over-range indication, and a medium quality built-in
reference. The chip pair also offers optional input buffer
gain for high sensitivity applications, a built-in clock oscillator, and output signals for providing an external Auto-Zero
capability in preconditioning Circuitry, synchronizing external
multiplexers, etc.

• 16/14 Bit Binary Three-State Latched Outputs Plus
Polarity and Overrange
• Ideally Suited for Interface to UARTs and
Microprocessors
• Conversion On Demand or Continuously
• Guaranteed Zero Reading for Zero Volts Input
• True Polarity at Zero Count for Precise Null
Detection
• Single Reference Voltage for True Ratlometrlc
Operation
• Onboard Clock and Reference
• Auto-Zero; Auto-Polarity
• Accuracy Guaranteed to 1 Count
• All Outputs TTL Compatible
• ± 4V Analog Input Range
• Status Signal Available for External Sync, AIZ In
Preamp, etc

ORDERING INFORMATION
Part Number

Temp. Range

ICL8052CPD
ICL8052CDD
ICL8052ACPD
ICL8052ACDD
ICL8068CJD
ICL8068ACJD

O·Cto
O·Cto
O·Cto
O·Cto
O·Cto
O·Cto

+70·C
+70·C
+70·C
+70·C
+70·C
+70·C

Package

Part Number

14-Pin Plastic DIP
14-Pin CeramiC DIP
14-Pin Plastic DIP
14-Pin Ceramic DIP
14-Pin CERDIP
14-Pin CERDIP

ICL7104-14CJL
ICL7104-14CPL
ICL7104-14CDL
ICL7104-16CJL
ICL7104-16CPL
ICL7104-16CDL

Package

Temp. Range
O·Cto
O·Cto
O·Cto
O·Cto
O·Cto
O·Cto

-70·C
+70·C
+70·C
+70·C
+70·C
+70·C

40-Pin CERDIP
40-Pin Plastic DIP
40-Pin Ceramic DIP
40-Pin CERDIP
40-Pin Plastic DIP
40-Pin Ceramic DIP

0346-1

Figure 1: ICL8052A (8068A)IICL7104 16/14 Bit AID Converter Functional Diagram

lNTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

3-19

p
CD

o

GI

....CD
n
r-

....
....
o

•

~

ICL8052/ICL 7104 and ICL8068/ICL 7104

cj

ABSOLUTE MAXIMUM RATINGS

co
CD
o
co

Power Dissipation (1) All Devices ................ 500mW
Storage Temperature ................ - 65'C to + 150'C
Operating Temperature ................... O'C to + 70'C
Lead Temperature (Soldering, 1Osee) ............. 300'C

.......

=::.

...
2

'a

.....
C

CO

o

......

()

=::.
(\I
II)

o

a
CO
_

ICL7104
V+ Supply(GNDtoV+) .......................... 12V
V + + to V- .................................... 32V
Positive Supply Voltage (GND to V + + ) ............ 17V
Negative Supply Voltage (GND to V -) .............. 17V
Analog Input Voltage (Pins 32 - 39) (4) ...... V + + to VDigital Input Voltage
(Pins 2 - 30) (5) ........... (GND-0.3V) to (V+ +0.3V)

ICL8052, 8068
Supply Voltage ................................. ±18V
Differential Input Voltage (8068) .................. ± 30V
(8052) ................ ±6V
Input Voltage (2) ............................... ± 15V
Output Short Circuit Duration,
All Outputs (3) ............................. Indefinite

e.

NOTE 1 Dissipation rating assumes device is mounted with all leads welded or soldered to printed circuit board in ambient temperature below + 70
For higher
temperatures, derate 1OmW 1°C.
2: For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
3: Short circuit may be to ground or either supply. Rating applies to + 70'C ambient temperature.
4 Input voltages may exceed the supply voltages provided the input curren1 is limited to ± 100"A.
5: Connecting any digital inputs or outputs to voltages greater than V + or less than GND may cause destructive device latchup. For this reason it is
recommended that no inputs from sources not on the same power supply be applied to the ICL7104 before its power supply is established.
G

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device ,sl/ability.

INTEGRATOR
OUT
COMP
OUT

BUFFER
(+IN)

REF
CAP

INTEGRATOR
(+IN)

REF
PASS

INTEGRATOR
(-IN)

GND

BUFFER
(-IN)

REF
OUT

BUFFER
OUT

REF
SUPPLY

y+

Yo.
DIGGND
STTS
POL.
O.R.
BIT 16
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BITS
BITS
BIT 4
BIT 3
BIT 2

V..

YCOMPIN
REFCAP 1
YREF

DIGGND
STTS
POL
O.R.
BIT 14
BIT 13
BIT 12
ICL7104
BIT 11
BIT 10
" -16
11
BIT 9
N.C.
N,C.
BIT 8
15
BIT 7
BITS
t7
BITS
BIT 4
BIT 3
BIT 2

AZ

ANALOG GND
REFCAP 2
BUF IN
ANALOG liP
Y+

eE7CD

,."
,.

SEN
Rlii
MODE
CLOCK 2
CLOCK 1

"
,."

.

0346-2

(OUTLINE OWGS DO, JO, PO)

0346-3

(OUTLINE OWGS OL, JL, PL)
Figure 2: Pin Configurations

ICL7104 ELECTRICAL CHARACTERISTICS
Symbol

(V+ = +5V, V + + = +15V, v-= -15V, TA=25'C)

Characteristics

Test Conditions

Min

Typ

Max

Unit

liN

Clock Input

CLOCK 1

Vin= + 5V to OV

±2

±7

±30

/J- A

liN

Comparator lIP

COMP IN (Note 1)

Vin=OVto +5V

-10

±0,OO1

+10

/J- A

MODE

VIN= +5V

+1

+5

+30

/J- A

Vin=OV

-10

±O.01

+10

/J- A

IIH

Inputs

IlL

with Pulldown

IIH

Inputs

SEN,R/H

Vin= +5V

-10

±0.01

+10

/J- A

IlL

with
Pull ups

LBEN, MBEN,
HBEN, CE/LD

Vin=OV

-30

-5

-1

/J- A

}

(Note 2)

INTERS1L'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not t88tsri.

3-20

.D~DI!.

ICL8052/ICL7104 and ICL8068/ICL7104
ICL7104 ELECTRICAL CHARACTERISTICS

(V+=+5V,V++ =+15V,V-=-15V,TA=25°C)

::
....

(Continued)
Symbol

Characteristics

VIH

Input High Voltage

All Digital Inputs

VIL

Input Low Voltage

All Digital Inputs

Test Conditions

VOL

Digital

LBEN

IOL =1.SmA

VOH

Outputs

MBEN (1S-only)

IOH= -10/-LA

VOH

Three-Stated
On

HBEN
CE/LD
BIT n, POL, OR

IOH=-240/-LA

(Note 3)

Min

Typ

Max

Unit

2.5

2.0

-

V

1.5

1.0

V

0.27

.4

V

4.5

-

V

3.5

-

V

2.4

Digital Outputs
Three-Stated Off

BIT n, POL, OR

O::;;Vout::;;V+

VOL

Non-Three State

SITS

IOL=3.2mA

-

IOH=-400/-LA

2.4

Digital

VOL

Output

CLOCK 2

-10

CLOCK 3 (-14 ONLY)

±.001

+10

/-LA

0.3

.4

V

3.3

-

V

IOH=-320/-LA

4.5

IOL =1.SmA

0.27

V
V
.4

V

2.4

3.5

V

25k

Switches 4,5,S, 7 ,8,9

-

Switch Leakage

-

15

Clock

Clock Freq. (Note 4)

DC

Supply Currents

+ 5V Supply Current
All outputs high impedance

Freq. = 200kHz

1++

+ 15V Supply Current

Freq. = 200kHz

1-

-15V Supply Current

Freq. = 200kHz
Note 5

IOH=-320/-LA

VOH
Switch 1

ROS(on)

Switches 2,3

ROS(on)
ROS(on)

Switch

10(011)

1+

4k

20k

2k

10k

n
n
n

200

400

kHz

200

SOO

/-LA

.3

1.0

mA

25

200

/-LA

4.0

+11.0

V

pA

V+

Supply Voltage

Logic Supply

V++

Range

Positive Supply

+10.0

+1S.0

V

Negative Supply

-1S.0

-10.0

V

VNOTES: 1.
2.
3.
4.
5.

...
~

..i.
o

2
o

This spec applies when not in Auto·Zero phase.
Apply only when these pins are inputs, i.e., the mode pin Is low, and the 7104 is not in handshake mode.
Apply only when these pins are outputs, i.e., the mode pin is high or the 7104 is in handshake mode.
Clock circuH shown in Figs. 15 and 16.
V + must not be more posHive than V + + .

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESB, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE; AU typical vs/ues have been characfBrizsd but IUS not tested.

3-21

....CD
,.n

...

..
~

0.5

IOL = 320/-LA

VOH
VOL

,.n

Gt

IOL

VOH

n

I;
o

o

•

.. ICL8052/ICL7104 and ICL8068/ICL7104
ii
..
~

l"-

ICL8068 ELECTRICAL CHARACTERISTICS

(VSUPPLY= ±15V unless otherwise specified)

:::::.
CD

o

Symbol

a
"Ii

..
...
o

8068

Test Conditions

Min

Typ

Max

8068A

Min

Typ

Unit
Max

EACH OPERATIONAL AMPLIFIER
VOS

Input Offset Voltage

VCM=OV

20

65

20

65

mV

liN

Input Current (either input) (Note 1)

VCM=OV

175

250

80

150

pA

CMRR

Common-Mode Rejection Ratio

VCM= ±10V

Non-Linear Component of CommonMode Rejection Ratio (Note 2)

VCM= ±2V
RL =50k!l

I"-

g
.....

Characteristics

70

90

70

90

dB

110

dB

6

6

V/ILS

110

Av

Large Signal Voltage Gain

C\I

SR

Slew Rate

o

GBW

Unity Gain Bandwidth

2

2

MHz

Isc

Output Short-Circuit Current

5

5

mA

10

...CD
g

20,000

20,000

VIV

COMPARATOR AMPLIFIER
AVOL

Small-signal Voltage Gain

+VO

Positive Output Voltage Swing

RL =30k!l
+12

4000
+13

+12

+13

VIV
V

-yo

Negative Output Voltage Swing

-2.0

-2.6

-2.0

-2.6

V

Vo

Output Voltage

1.60

1.75

Ro

Output Resistance

TC

Temperature Coefficient

VSUPPLY

Supply Voltage Range

ISUPPLY

Supply Current Total

VOLTAGE REFERENCE
1.5

2.0

5
50

V
!l

40
±16

ppml'C

±10

14

Characteristics

1.90

5

±10

ICL8052 ELECTRICAL CHARACTERISTICS
Symbol

1.75

±16

V

14

mA

8

(VSUPPLY = ± 15V unless otherwise specified)
8052

Test Conditions
Min

8052A

Typ

Max

Min

Typ

Max

I Unit

EACH OPERATIONAL AMPLIFIER
VOS

Input Offset Voltage

VCM=OV

20

75

20

75

mV

liN

Input Current (either input) (Note 1)

VCM=OV

5

50

2

10

pA

CMRR

Common-Mode Rejection Ratio

VCM= ±10V

Non-Linear Component of CommonMode Rejection Ratio (Note 2)

VCM= ±2V

Av

Large Signal Voltage Gain

RL =50k!l

SR

Slew Rate

GBW

Unity Gain Bandwidth

Isc

Output Short-Circuit Current

70

90

70

90

dB

110

dB

6

V/ILS

1

1

MHz

20

20

mA

110
20,000

20,000
6

VIV

COMPARATOR AMPLIFIER
AVOL

Small-signal Voltage Gain

+Vo

Positive Output Voltage Swing

+12

-yo

Negative Output Voltage Swing

-2.0

RL =30k!l

4000

VIV

+13

+12

+13

V

-2.6

-2.0

-2.6

V

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but ar6 not testBd.

3-22

BlO~OIL

ICL8052/ICL 7104 and ICL8068/ICL 71 04

n
I'"

CD

ICL8052 ELECTRICAL CHARACTERISTICS
Symbol

Characteristics

(VSUPPLY= ± 15V unless otherwise specified) (Continued)
8052A

8052

Test Conditions
Min

Typ

Unit

Max

Min

Typ

Max

2.0

1.60

1.75

1.90

VOLTAGE REFERENCE
Vo

Output Voltage

1.5

1.75

V

Ro

Output Resistance

5

5

n

TC

Temperature Coefficient

50

40

ppml"C

VSUPPLY

Supply Voltage Range

ISUPPLY

Supply Current Total

±10

±16
6

±10

12

±16

V

12

mA

6

NOTES: 1. The input bias currents are junction leakage currents which approximately double for every 100G increase in the junction temperature, TJ. Due to limited
production test time, the input bias currents are measured with junctions at ambient temperature. In normal operation the junction temperature rises
above the ambient temperature as a result of internal power dissipation, Pd. TJ=TA+R8JAPd where R8JA is the thermal resistance from junction to
ambient. A heat sink can be used to reduce temperature rise.
2. This is the only component that causes error in dual·slope converter.

SYSTEM ELECTRICAL CHARACTERISTICS: ICL806817104

(V + + = +15V,

v+ =

+5V,

V- = -15V, Clock Frequency = 200kHz)
Characteristics

8068A/7104-16

8068A17104-14

Test Conditions
Min

Typ

Max

Min

Typ

Unit

Max

Zero Input Reading (4)

Hexadecimal
Vin=O.OV
-0.0000 ±O.OOOO +0.0000 -0.0000 -0.0000 +0.0000
Reading
Full Scale = 4.000V

Ratiometric Reading (1) (4)

Vin=VRef.
Full Scale = 4.000V

1FFF

2000

2001

Linearity over ± Full Scale (error
of reading from best straight line) -4V,;;Vin';; +4V
(4)

0.5

1

Differential Linearity (difference
between worst case step of
adjacent counts and ideal step)

.01

-4V,;;Vin';; +4V

Rollover error (Difference in
reading for equal positive & neg· -Vin= +Vin '" 4V
ative voltage near full scale) (4)

0.5

Noise (p.p value not exceeded
95% of time)

Vin=OV
Full scale = 4.000V

Leakage Current at Input (2) (4)

Vin=OV

100

Zero Reading Drift (A)

Vin=OV
0'C,;;TA,;;70'C

0.5
2

8000

8001

0.5

1

.01

1

2

Vin= +4V
Scale Factor Temperature (3) (4)
0,;;TA';;50'C
Coefficient
ext. ref. Oppml'C

7FFF

0.5

100

1

2

LSB

fJ- V
165

0.5
5

LSB

LSB

2
165

Hexadecimal
Reading

pA
fJ-VI'C

5

ppml'C

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTe: All typical values have been characterized but are not tested.

3·23

o

(II

....N

n
I'"

......
o
....

II

::a

Q.

n
I'"
CD

o

o

....CD
n
I'"

......
o
....

•

..... ICL8052/ICL7104 and ICL8068/ICL7104
g~!~~~5~ c~~~;!~~~~~o~~:RACTERISTICS:

.D~Do..

~

ICL805217104

G

o

a

1

....
~

o

i....
C\I
10

o

a

Characteristics

(V + + = + 15V, v+ = +5V,

8052A17104-14

Teat Conditions

Typ

Min

8052A17104·16

Max

Min

Typ

Unit

Max

Zero Input Reading

Hexadecimal
Vln=O.OV
-0.0000 ±o.oOOO +0.0000 -0.0000 ±0.0000 +0.0000
Full Scale=4.000V
Reading

Ratiometric Reading (3) (4)

Vin= VRef.
Full Scale=4.000V

2000

2001

Linearity over ± Full Scale (error
of reading from best straight line) -4V~Vin~ +4V
(4)

0.5

1

Differential Linearity (difference
between worst case step of
adjacent counts and ideal step)

-4V~Vin~

.01

Rollover error (Difference in
reading for equal positive &
negative voltage near full scale)

-Vln= + Vin:::::4V

0.5

Noise (p.p value not exceeded
95% of time)

Vin=OV
Full scale=4.000V

30

Leakage Current at Input (2) (4)

Vin=OV

20

Zero Reading Drift (4)
Scale Factor Temperature
Coefficient (4)

1FFF

+4V

Vin=OV
0~TA~70"C

7FFF

8000

8001

0.5

1

.01

1

0.5

20

LSB

LSB

1

LSB

p,V

30
30

Hexadecimal
Reading

30

pA

0.5

0.5

p,VI"C

2

2

ppml"C

Vln=+4V
0~TA~70"C

(ext. ref. Oppm/OC)

NOTES: 1. Tested with low dielectric absorption integrating capacitor.
2. the input bias currents are junction leakage currents which approximately double for every 10'C increase in the junction temperature. TJ. Due to limited
production test time, the input bias currents are measured with junctions at ambient temperature. In normal operation the junction temperature rises
above the ambient temperature as a result of Internal power dissipation. Pd. TJ= TA+ RSJAPd where ROJA is the thermal resistance from junction to
ambient. A heat sink can be used to reduce temperature rise.
3. The temperature range can be mended to 70'C and beyond If the Auto-Zero and Reference capecltors are Increased to absorb the high temperature
leakage of the 8068. See note 2 above.
4. Parameter has been characterized but Is not production tested.

INTERSIL·S SOLE AND EXCLUSIVE WARRANTY OBLIGAnON WITH RESPECT TO THIS PROOUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL, OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARnCULAR USE.

NOTE; AU Iyp/caIvsIues have bNn charscIetfzod but.", not _

3·24

.O~OI!..

ICL8052/ICL 7104 and ICL8068/ICL 7104

,.n
C»

o

CII

....
n
,.
II)

COHVDT

CONTIIOL

......
o
....

:'1.

-

III
~

A.

IOI2AI

7104

P

-1'

C»

o

ell
C»

....
n
,.

,.--..
1 -=t: or CHIP ALiCT I
1....-.......--..4-........._

......
o

0346-4

Figure 3: Full 18 Bit Three State Output

COHVDT

IOI2AI

lallA

-

7104

011

011

POL

POL

IOI2AI

lallA

7104

La

La

CONTIIOL

CONTIIOL

- 011

POL

1052A1

7104

0346-5

Figure 4: Various Combinations of Byte Disables

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charact8rlzrJd but SIB not fBsted.

3·25

....

•

......~

d
::::
GI)

ICL8052/ICL 7104 and ICL8068/ICL 7104
AC CHARACTERISTICS
AS INPUT

g

lI\IEII

I:IElII

......

HIGH BYTE
DATA

....
o

...

i.....
CII

...
i

+5V, V- = -15V)

=

URI!
AS INPUT

AS INPUT

.....

MIOOLE BYTE
.fD'1.fA\...
ENABLE
--------------------------~--------

II)

o
GI)

+ 15V, V+

AS INPUT

.

1

=

CElLO

U)

oGI)

(V + +

LOW BYTE

ENABLE

-------------------------------,------,--t~~-----

- - - - - - - =HIGH IMPEDANCE

0346-6

Figure 5: Direct Mode Timing Diagram
Table 1: Direct Mode Timing Requirements (Note: Not tested In production)
Symbol

Description

tbaa

XBEN Min, Pulse Width

tdab

Data Access Time from XBEN

tdhb

Data Hold Time from XBEN

Icas

CElLO Min, Pulse Width

Idse

Data Access Time from CElLO

tdhe

Data Hold Time from CElLO

tcwh

CLOCK 1 High Time

Max

300
300
200
350
350
280
1000

Table 2: Handshake Timing Requirements
Name

Typ

Min

Description

tmw

MODE Pulse (minimum)

tsm

MODE pin set-up time

tma

MODE pin high to low Z CElLO high delay

tmb

MODE pin high to XBEN low Z (high) delay

teal

CLOCK 1 high to CElLO low delay

teah

CLOCK 1 high to CElLO high delay

tebl

CLOCK 1 high to XBEN low delay

tebh

CLOCK 1 high to ~ high delay

tedh

CLOCK 1 high to data enabled delay

tcdl

CLOCK 1 low to data disabled delay

Iss

Send ENable set-up time

tebz

CLOCK 1 high to XBEN disabled delay

Icaz

CLOCK 1 high to CElLO disabled delay

tcwh

CLOCK 1 High Time

Unit

ns

(Note: Not tested in production,)
Min

Typ

1250

20
-150
200
200
700
600
900
700
1100
1100
-350
2000
2000
1000

Max

Unit

ns

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: An typJcsJ values haV6 bHn charactsrlzsd but BffI not tested.

3-26

·o~on..

ICL8052/ICL 7104 and ICL8068/ICL 7104

c;
rCD

o

CIt

....
I\)

c;

CLOCK 1 (PIN 25)

...o...r-

.

lITHeR:
_PIN
011:
INTERNAL LATCH

III
::I

PUl.8I1' MODE "Hr.

a.

UNIT

INTERNAl. MODI

c;

NOIIM--~-..I.--:-"I

r-

CD

o
ca

....
CD

SEN

(EXTERNAL SIGNAL)

OIR,POL01-14

BITS 1-5

~...

.

'
H_ _ _~~~:~~_ _ ~-----

_ _- '_ _~_ _~_ _~_ _-"-'S~~_~~(::~D~A~T~A~Y~AL~I~D.~S~T!AB~;i:=:>~-~----~-~HANDSHAKE MODE TRIGGERED BY ·····DR---14 BIT VERSION SHOWN

THREE-8TATE _

THREE-STATE W PULWP ~

-16 HAS EXTRA (MBEN) PHASE

0346-7

Figure 6: Handshake Mode Timing Diagram

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are not tested

3-27

...o

.

•

g.... ICL8052/ICL 7104 and ICL8068/ICL 7104

.......
g

....CD

Table 3: Pin Descriptions
Pin

Symbol

Option

++)

Description

CD

1

V(

...gCD

2

GND

Digital Ground .OV, ground return

3

STTS

STaTuS output. HI during
Integrate and Deintegrate until
data is latched. La when analog
section is in Auto-Zero
configuration.

o

"

.

C
1\1

........o

...

4

POL

&\I

5

OR

o

6

BIT16
BIT14

-16
-14

7

BIT 15
BIT 13

-16
-14

8

BIT14
BIT12

-16
-14

9

BIT13
BITll

-16
-14

10

BIT12
BIT10

-16
-14

11

BITll
BIT9

-16
-14

12

BIT10
nc

-16
-14

13

BIT9
nc

-16
-14

II)

...
g
CD

14

BIT8

15

BIT7

16

BIT6

17

BIT5

18

BIT4

19

BIT3

20

BIT2

24 CLOCK3
Pin

Symbol

Least significant bit.

LBEN

Low By1e ENable. If not in
handshake mode (see pin 27)
when La (with CEILD, pin 30)
activates low-order byte outputs,
BITS 1-8
When in handshake mode (see
pin 27), serves as a low-byte flag
output. See Figures 12, 13, 14.

MBEN

-16

HBEN

-14

Description

Clock output. Crystal or RC oscillator.

27

MODE

Input La; Direct output mode where CEI
LD, HBEN, MBEN and LBEN act as
inputs directly controlling by1e outputs. If
pulsed HI causes immediate entry into
handshake mode (see Figure 14).
If HI, enables CEILD, HBEN, MBEN, and
LBEN as outputs. Handshake mode will
be entered and data output as in Figures
12 & 13 at conversion completion.

28 RIH

Run/Hold: Input HI-conversions
continously performed every 217 ( -16) or
2 15( -14) clock pulses. Input LOconversion in progress completed,
converter will stop in Auto-Zero 7 counts
before input integrate.

29 SEN

Send-ENable: Input controls timing of
byte transmission in handshake mode. HI
indicates 'send'.

30

CEILD

Chip-Enable/LoaD. With MODE (pin 27)
La, CEILD serves as a master output
enable; when HI, the bit outputs and POL,
OR are disabled. With MODE HI, pin
serves as a Loa5 strobe ( - ve going)
used in handshake mode. See Figures 12
& 13.

31

V(+)

Positive Logic Supply Voltage. Nominally
+5V.

32 AN,IN

ANalog INput. High side.

33

BUF IN

BUFfer INput to analog chip (ICL8052 or
ICL8068)

34

REFCAP2 REFerence CAPaCitor (negative side)

35 AN.GND.

ANalog GrouND. Input Ibw side and
reference low side.

36 A-Z

Auto-Zero node.

37 VREF

Voltage REFerence input (positive side).

38

Mid By1e ENable. Activates BITS
9-16, see LBEN (pin 22)
High Byte ENable.
Activates BITS 9-14, POL, OR,
see LBEN (pin 22)

-14

Description
High By1e ENable. Activates
POL, OR, see LBEN (pin 22).
RC oscillator pin. Can be used
as clock output.

26 CLOCK2

Data Bits, Three-state outputs.
See Table 4 for format
of ENables and bytes.
HIGH=true

BIT 1

-16

Clock input. External clock or ocsillator.

(Most significant bit)

22

Option

25 CLOCKI

OverRange. Three-state output.

21

23

Symbol
HBEN

POLarity. Three-state output. HI
for positive input.

()

:::::.

Pin

Positive Supply Voltage
Nominally + 15V

REFCAPI REFerence CAPacitor (positive side).

39 CaMP-IN

COMParator INput from 8052/8068

40 V(-)

Negative Supply Voltage. Nominally
-15V.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTe: All typical values have been characterized but are not tested.

3-28

·D~DIL

ICL8052/ICL 7104 and ICL8068/ICL 7104

P
CIII

o

Table 4: Three-State Byte Formats and ENable Pins

MBEN

HBEN

UI
N

....

n
r-

CElLO

.......o

LBEN

.

l

7104-16 POLIOIR B161 B151 B14J B131 B121 B11[ B10 B9 BSJB71B61B51 B4 1B3 1B2JB1
HBEN
7104-14

LBEN

II
::I

POL 1OIR 1B141 B13lB121B111 B10 1B9 BsIB71B6IB5[B4IB3IB2IB1

A-

Figure 1 shows the functional block diagram of the operating system. For a detailed explanation, refer to Figure 7 below.

n
rCIII

o

01

....
n
rCIII

D

Q

CL

POL

CL
0346-8

Figure 7A: Phase I Auto-Zero

AN
liP

D

Q

ZERO
CROSSING

F/F

CL

POL

CL
0346-9

Figure 7B: Phase II Integrate Input

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

3-29

.......

.
o

ZERO
CROSSING
F/F

•

~

ICL8052/ICL 7104 and ICL8068/ICL 7104

d

DETAILED DESCRIPTION

.......o

::::. Analog Section
CD
CD

o

CD

g
"
C
1\1

Auto-Zero Phase I Figure 7A
During Auto-Zero, the input of the buffer is shorted to
analog ground thru switch 2, and switch 1 closes a loop
around the integrator and comparator. The purpose of the
loop is to charge the Auto-Zero capacitor until the integrator
output no longer changes with time. Also, switches 4 and 9
recharge the reference capacitor to VREF.

Figure 7 shows the equivalent Circuit of the Analog Section of both the ICL7104/S052 and the ICL71 04/8068 in the
3 different phases of operation. If the Run/Fiold pin is left
open or tied to V +, the system will perform conversions at
a rate determined by the clock frequency: 131,072 for - 16
and 32,368 for - 14 clock periods per cycle (see Figure 9
conversion timing).

~

...o....
...
u

::::.
(II
."

o

D

3

Q

ZERO
CROSSING

~

F/F
CL

POL

CL

0346-10

Figure 7C: Phase III + Deintegrate

t(

ZERO
CROSSING

6

9

-

Q

D

F/F

7

CL

+

CRE.

POL

CL

0346-11

Figure 7D: Phase 111- Deintegrate

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTiE: All typical values have been characterized but are not tested.

3-30

ICL8052/ICL7104 and ICL8068/ICL7104
phase, the input voltage required to give a full scale
reading = 2VREF.

Input Integrate Phase II Figure 7B
During input integrate the Auto-Zero loop is opened and
the analog input is connected to the buffer input thru switch
3. (The reference capacitor is still being charged to VREF
during this time.) If the input signal is zero, the buffer, integrator and comparator will see the same voltage that existed in the previous state (Auto-Zero). Thus the integrator
output will not change but will remain stationary during the
entire Input Integrate cycle. If VIN is not equal to zero, an
unbalanced condition exists compared to the Auto-Zero
phase, and the integrator will generate a ramp whose slope
is proportional to VIN. At the end of this phase, the sign of
the ramp is latched into the polarity F/F.

Note: Once a zero crossing is detected, the system automatically reverts to
Auto-Zero phase for the leftover Deintegrate time (unless Run/Rold is manipulated, see Run/Rold Input in detailed description, digital section).

Buffer Gain
At the end of the auto-zero interval, the instantaneous
noise voltage on the auto-zero capacitor is stored, and subtracts from the input voltage while adding to the reference
voltage during the next cycle. The result is that this noise
voltage effectively is somewhat greater than the input noise
voltage of the buffer itself during integration. By introducing
some voltage gain into the buffer, the effect of the auto-zero
noise (referred to the input) can be reduced to the level of
the inherent buffer noise. This generally occurs with a buffer
gain of between 3 and 10. Further increase in buffer gain
merely increases the total offset to be handled by the autozero loop, and reduces the available buffer and integrator
swings, without improving the noise performance of the system. The circuit recommended for doing this with the
ICL8068/1CL7104 is shown in Figure 8. With careful layout,
the circuit shown can achieve effective input noise voltages
on the order of 1 to 2 ".V, allowing full 16-bit use with full
scale inputs of as low as 150mV. Note that at this level,
thermoelectric EMFs between PC boards, IC pins, etc., due
to local temperature changes can be very troublesome. For
further discussion, see App. Note A030.

Deintegrate Phase III Figure 7C & D
During the Deintegrate phase, the switch drive logic uses
the output of the polarity F IF in determining whether to
close switches 6 and 9 or 7 and 8. If the input signal was
positive, switches 7 and 8 are closed and a voltage which is
VREF more negative than during Auto-Zero is impressed on
the buffer input. Negative inputs will cause + VREF to be
applied to the buffer input via switches 6 and 9. Thus, the
reference capacitor generates the equivalent of a (+) reference or a (-) reference from the single reference voltage
with negligible error. The reference voltage returns the output of the integrator to the zero-crossing point established
in Phase I. The time, or number of counts, required to do
this is proportional to the input voltage. Since the Deintegrate phase can be twice as long as the Input integrate

0346-12

Figure 8: Adding Buffer Gain to ICL8068

Table 5: Typical Component Values
ICL8052/8068 with

(V++ =+15V,V+=5V,V-=-15V,ClockFreq=200kHz)

ICL7104-14

ICL7104-16

Unit

200

800

4000

100

4000

mV

Buffer Gain

10

1

1

10

1

V/V
k!1

Full scale VIN

RINT

100

43

200

47

180

CINT

.33

.33

.33

0.1

0.1

".F

CAZ

1.0

1.0

1.0

1.0

1.0

".F

10

1.0

1.0

10

1.0

".F

VREF

100

400

2000

50

2000

mV

Resolution

3.1

12

61

6.1

244

".V

Cre!

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN lIEU OF ALL OTHER WARRANTIES, eXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3·31

II

l

(;
I""
CIO

o

GI

CIO
......

(;
I""

...

~

o

•

•

....... ICL8052/ICL7104 and ICL8068/ICL7104
~

S:!
.....

POLARITY

CD
fO

o

...S:!CD

"
.......o"

.
t:

INTEGRATOR
OUTPUT

I

DET~ECTED

I

ZERO CROSSING
OCCURS

I.....
II
I---AZ PHASE I--I-INT PHASE II-t---+i~"'-DEINT PHASE I11--1--AZI

-......"

INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT

h.r ~ J1IlItil..
I

I
I

I

I

I
I
I

I

I

I

I

I

I
I

I

I
'I

NUMBER OF COUNTS TO ZERO CROSSING/
PROPORTIONAL TO V,N

f!

~

I

f~

I

I

IMHN
I (-16 only)

I

I
I

!

TO
ANALOG
SECTION

I

~~~~~~Lt~~1 ~

COMPOUT

AZ
INT
DEINT(+)
DEINT(-)

I

I
2.L ___ J
STaTuS

Rill

CLOCK
1

MODE

I

SEND
0346-14

Figure 10: Digital Section

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTieS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but 8/9 not (ssted

3-33

CII
N

"(IS...

.......
o

!

a.
_

n
...
c»

0
ell

~

(IS
...

....

..
..

During a conversion cycle, the STaTuS output goes high
at the beginning of Input Integrate (Phase II), and goes low
one-half clock period after new data from the conversion
has been stored in the output latches. See Figure 9 for details of this timing. This signal may be used as a "data valid"
flag (data never changes while STaTuS is lOw) to drive interrupts, or for monitoring the status of the converter.

POL OIR 814 813 812 811 810 89

o

o

...g.... ICL8052/ICL 7104
...
u

and ICL8068/ICL 7104

=::.
co
co
o
co

2
""

OPTION
MIN
MAX

~

d
=::.

I

DEINT TERMINATED

I

ATZEROCROSS~NG
INTEGRATOR
OUTPUT

I:

.......o

-14
-16
7161 28665
8185 32761

INTERNAL CLOCK

-

~..---

~

1

-

,

,

I

j

-'-'

I~

1 - - 7 COUNTS---1

V '"lr1nrl. J111nI1..l11L. Jl,.flItI1I1.. ~ -utIl.JlJ1J1.I1
1

INTERNAL LATCH

1

n

STaTuS OUTPUT

RUN/HOLD INPUT

INT
i-PHASEI

1 STATICIN

I HOLD STATE

------....£ETECTION:

-------""Lr------.....,

&"I

i

I

l

_-----!f-'--------1---""
!

-------~--------------~

1ft

i

1

0346-15

o
~

Figure 11: Run/Hold Operation

g Run/Hold Input

grate (Phase II) begins seven clock periods after the high
level is detected.

When the Run/Rold input is connected to V + or left open
(this input has a pullup resistor to ensure a high level when
the pin is left open), the circuit will continuously perform
conversion cycles, updating the output latches at the end of
every Deintegrate (Phase III) portion of the conversion cycle
(See Figure 9). (See under "Handshake Mode" for exception.) In this mode of operation, the conversion cycle will be
performed in 131,072 for 7104-16 and 32768 for 7104-14
clock periods, regardless of the resulting value.
If Run/Rold goes low at any time during Deintegrate
(Phase III) after the zero crossing has occurred, the circuit
will immediately terminate Deintegrate and jump to AutoZero. This feature can be used to eliminate the time spent in
Deintegrate after the zero-crossing. If Run/Rold stays or
goes low, the converter will ensure a minimum Auto-Zero
time, and then wait in Auto-Zero until the Run/Rold input
goes high. The converter will begin the Integrate (Phase II)
portion of the next conversion (and the STaTuS output will
go high) seven clock periods after the high level is detected
at Run/Rold. See Figure 11 for details.
Using the Run/Rold input in this manner allows an easy
"convert on demand" interface to be used. The converter
may be held at idle in Auto-Zero with Run/Rold low. When
Run/Rold goes high the conversion is started, and when
the STaTuS output goes low the new data is valid (or transferred) to the UART - see Handshake Mode). Run/Rold
may now go low terminating Deintegrate and ensuring a
minimum Auto-Zero time before stopping to wait for the
nex1 conversion. Alternately, Run/Rold can be used to minimize conversion time by ensuring that it goes low during
Deintegrate, after zero crossing, and goes high after the
hold point is reached. The required activity on the Run/Rold
input can be provided by connecting it to the CLOCK3 (-14),
CLOCK2 (-16) Output. In this mode the conversion time is
dependent on the input value measured. Also refer to Intersil Application Bulletin A030 for a discussion of the effects
this will have on Auto-Zero performance.
If the RunlRold input goes low and stays low during AutoZero (Phase I), the converter will simply stop at the end of
Auto-Zero and wait for Run/Rold to go high. As above, Inte-

Direct Mode
When the MODE pin is left at a low level, the data outputs
[bits 1 through 8 low order byte, see Table 4 for format of
middle (-16) and high order bytes] are accessible under
control of the byte and chip ENable terminals as inputs.
These ENable inputs are all active low, and are provided
with pullup resistors to ensure an inactive high level when
left open. When the chip ENable input is low, taking a byte
ENable input low will allow the outputs of that byte to become active (three-stated on). This allows a variety of parallel data accessing techniques to be used. The timing requirements for these outputs are shown under AC Characteristics and Table 1.
It should be noted that these control inputs are asynchronous with respect to the converter clock - the data may be
accessed at any time. Thus it is possible to access the data
while it is being updated, which could lead to scrambled
data. Synchronizing the access of data with the conversion
cycle by monitoring the STaTuS output will prevent this.
Data is never updated while STaTuS is low. Also note the
potential bus conflict described under "Initial Clear Circuitry".

Handshake Mode
The handshake output mode is provided as an alternative
means of interfacing the ICL7104 to digital systems, where
the AID converter becomes active in controlling the flow of
data instead of passively responding to chip and byte
ENable inputs. This mode is specifically designed to allow a
direct interface between the ICL7104 and industry-standard
UARTs (such as the Intersil CMOS UARTs, IM6402/3) with
no external logic required. When triggered into the handshake mode, the ICL7104 provides all the control and flag
Signals necessary to sequence the three (lCL7106-16) or
two (ICL7104-14) bytes of data into the UART and initiate
their transmission in serial form. This greatly eases the task
and reduces the cost of designing remote data acquisition
stations using serial data transmission to minimize the number of lines to the central controlling processor.

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANlY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED DR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILIlY AND FITNESS FOR A PARTICULAR USE.
NOTE; All typical values have been characterized but are not tested

3-34

ICL8052/ICL7104 and ICL8068/ICL7104
once every clock pulse, and if it is high, the next (or first)
byte is enabled on the next rising CLOCK 1 (pin 25) clock
edge, the corresponding byte ENable line goes low, and the
Chip ENable/LoaD pin (pin 30) (CE/LD) goes low for one
full clock pulse only, returning high.
On the next falling CLOCK 1 clock pulse edge, if SEN
remains high, or after it goes high again, the byte output
lines will be put in the high impedance state (or three-stated
off). One half pulse later, the byte ENable pin will be cleared
~h, and (unless finished) the CE/LD and the next byte
ENable pin will go low. This will continue until all three (2 in
the case of the 14 bit device) bytes have been sent. The
bytes are individually put into the low impedance state i.e.:
three-stated on during most of the time that their byte
ENable pin is (active) low. When receipt of the last byte has
been acknowledged by a high SEN, the handshake mode
will be cleared, re-enabling data latching from conversions,
and recognizing the condition of the MODE pin again. The
byte and chip ENable will be three-stated off, if MODE is
low, but held high by their (weak) pullups. These timing relationships are illustrated in Figure 12,13, and 14, and Table
2.

Entry into the handshake mode will occur if either of two
conditions are fulfilled; first, if new data is latched (i.e. a
conversion is completed) while MODE pin (pin 27) is high, in
which case entry occurs at the end of the latch cycle; or
secondly, if the MODE pin goes from low to high, when
entry will occur immediately (if new data is being latched,
entry is delayed to the end of the latch cycle). While in the
handshake mode, data latching is inhibited, and the MODE
pin is ignored. (Note that conversion cycles will continue in
the normal manner). This allows versatile initiation of handshake operation without danger of false data generation; if
the MODE pin is held high, every conversion (other than
those completed during handshake operations) will start a
new handshake operation, while if the MODE pin is pulsed
high, handshake operations can be obtained "on demand."
When the converter enters the handshake mode, or when
the MODE input is high, the chip and byte ENable terminals
become TTL-compatible outputs which provide the control
signals for the output cycle. The Send ENable pin (SEN)
(pin 29) is used as an indication of the ability of the external
device to receive data. The condition of the line is sensed

,,/OCCURS

INTEGRATOR
OUTPUT
INTERNAl.
CLOCK

'.,-11 _ _ - - .

~~OBSING
DETEC'IED

"'-

--I""L-I-- __
I

INTERNAl.
LATCH

~ I-- H..-J-I - - rl....-J I - -r-L-

STATUS

OUTPUT

MOOE
INPUT

MODE HIGH ACTIVATES

mmm,RRR.CIIIJiI

!

INTERNAl. UART
NORM

MOOE

...----

SEN

~

BEN
SENBED _____

---

INPUT

j

I\
f

I\

HIGH BYTE
OATA

LOW BYTE
DATA

LOW BYTE
DATA

--------- - -- '"
----------- fo--

BEN
_ SENSEO----...,

f

f

IN.....:=~':.=

DATA VALID

>--

--------

-------- -- '"

OISABLES OUTPUTS eI7[I!
__

_R.!.'!:~i!,!!

DATA VALID

I'-J. _J._

~-J.-

~ -----~_J._

I

-- -------- --- ------

------------------------------------ '"

_=

1/

TERMINATES
UARTMODE

,..----

DATA VALID

~------I

--'--= THRU-8TATE WITH PUUUP

DONT CARE

0346-16

Figure 12: Handshake with SEN Held Positive

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE· All typical values have been charactenzed but are not tested.

3-35

II
:::I
Q.

n
rCO

o

GI
CO

....
n
r-

......

.
o

•

~
...d...

ICL8052/ICL 7104 and ICL8068/ICL 7104
drives the TBRL (Transmitter Buffer Register Load) input to
the UART. The data outputs are paralleled into the eight
Transmitter Buffer Register inputs.
Assuming the UART Transmitter Buffer Register is empty,
the SEN input will be high when the handshake mode is
entered after new data is stored. The CElLO and HBEN
terminals will go low after SEN is sensed, and the high order
byte outputs become active. When CElLO goes high at the
end of one clock period, the high order byte data is clocked
into the UART Transmitter Buffer Register. The UART
TBRE output will now go low, which halts the output cycle
with the HBEN output low, and the high order byte outputs
active. When the UART has transferred the data to the
Transmitter Register and cleared the Transmitter Buffer
Register, the TBRE returns high. On the next ICL71 04 internal clock high to low edge, the high order byte outputs are
disabled, and one-half internal clock later, the HBEN output
returns high. At the same time, the CElLO and MBEN (-16)
or LBEN outputs go low, and the corresponding byte outputs become active. Similarly, when the CElLO returns high
at the end of one clock period, the enabled data is clocked
into the UART Transmitter Buffer Register, and TBRE again
goes low. When TBRE returns to a high it will be sensed on
the next ICL7104 internal clock high to low edge, disabling
the data outputs. For the 16 bit device, the sequence is
repeated for LBEN. One-half internal clock later, the handshake mode will be cleared, and the chip and byte ENable
terminals return high and stay active (as long as MOOE
stays high).

Figure 12 shows the sequence of the output cycle with
SEN held high. The handshake mode (Internal MOOE high)
is entered after the data latch pulse (since MOOE remains
Ie) high the CElLO, LBEN, MBEN and HBEN terminals are aco tive as outputs). The high level at the SEN input is sensed
on the same high to low internal clock edge. On the next to
~ high internal clock edge, the CElLO and the HBEN outputs
assume a low level and the high-order byte (POL and OR,
and except for -16, Bits 9 -14) outputs are enabled. The
II CElLO output remains low for one full internal clock period
'lit only, the data outputs remain active for 1-% internal clock
o periods, and the high byte ENable remains low for two clock
... periods. Thus the CElLO output low level or low to high
edge may be used as a synchronizing signal to ensure valid
... data, and the byte ENable as an output may be used as a
::::. byte identification flag. With SEN remaining high the conCI! verler completes the output cycle using CElLO, MBEN and
LBEN while the remaining byte outputs (see Table 4) are
CD activated. The handshake mode is terminated when all
... bytes are sent (3 for -16,2 for -14).
~
Figure 13 shows an output sequence where the SEN input is used to delay portions of the sequence, or handshake, to ensure correct data transfer. This timing diagram
shows the relationships that occur using an industry-standard IM6402/3 CMOS UART to interface to serial data
channels. In this interface, the SEN input to the ICL7104 is
driven by the TBRE (Transmitter Buffer Register Empty)
output of the UART, and the CElLO terminal of the ICL7104
::::.
CD

3

I

rl

:g

"-

ZEROoCROSSING
ILOCCURS

I'

I'ZERQoCR08SING
DETECTED

JILr-~ ~~ I"- r-u-t-~ ~

r

INTERNAL
LATCH

r-u-t-r rut-

STATUS
OUTPUT
MODE
INPUT

INTERNAL U....T
MODE NDRM

SENtNPUT

C::::

(UAlIT TaRE)

::!7Il)OUTPUT
(UARTTBRL)

HIGH BYTE
DATA

-------- 1---

MIOOLEBYTE
DATA

--------

LOWeYTE

--------

DATA

U=

~

III

-

DATA VALID

------~~-

- ------..

= DON'T CARE

~-

~.

-------1"..- -

-

DATAYA~t:: ~.

-- ------.., -- r-

i'----/'
-------l~-- r-r------

-------t~--

r- ------

1\

...

DATA VALID

~-

------

- - - '" THREE-STATE HIOH IMPEDANCE

0346-17

Figure 13: Handshake - Typical UART Interface Timing
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY ANO FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3-36

~U~UI!..

ICL8052/ICL 7104 and ICL8068/ICL 7104

c;
rCD

o

(II
~

....

--fi;:NG

~OCROSSINGDETECTED

::~~:~ --1-+----01 "_'::UT=AR::.:T~MFO:::D:;.E_,,,-~-LL~1~;'~~""""1"-' ~ _-1-+--LATCH

STATUS OUTPUT
UNAFFECTED BY

STATUS

-I-+--

,,"U:::A:::R:.:.T;:M::::O:::DE~_ _ _ _ _

OUTPUT POSITIVE TRANSITION CAUSES

c;
.......r-

...o

II
:::I
Do

c;

MODE ENTRY INTO
INPUT UART MODe

rCD
o
GI

....CD
c;

I

HIGH

-t---~ ~-+-"\. ~_

I I

1.'--'- ,

~~! --------.. ~--i-i

________ .. Jo-

r,----IJ

DATAVA~It::}1------oIJo--t-1---- - - . Jo--

iiIEN _____ .r---i--+----~,
MIDDLE ~~!

r-

-""""1I

RRJj _ _ _ _ _ r---+~

_ _ _ _ _ _. . _ - - _

i

DATAVALq-

... _

-r---1

--+--\..

_ _ _ _ _ _ . , __

-.&..
LDW~m

_ _ _ _ _ _ _ _ -1 Jo-

B

------..

~----------oIJo_-

- - - = THREE-STATE HIGH IMPEDANCE

=DOHTCARE

Figure 14: Handshake Triggered By Mode

With the MODE input remaining high as in these exam·
pies, the converter will output the results of every conversion except those completed during a handshake operation.
By triggering the converter into handshake mode with a low
to high edge on the MODE input, handshake output sequences may be performed on demand. Figure 14 shows a
handshake output sequence triggered by such an edge. In
addition, the SEN input is shown as being low when the
converter enters handshake mode. In this case, the whole
output sequence is controlled by the SEN input, and the
sequence for the first (high order) byte is similar to the sequence for the other bytes. This diagram also shows the
output sequence taking longer than a conversion cycle.
Note that the converter still makes conversions, with the
STaTuS output and Run/Rold input functioning normally.
The only difference is that new data will not be latched
when in handshake mode, and is therefore lost.

-.&.- = THREE·STATE WITH PULLUP
0346-18

ters if the supply voltage "glitches" to a low enough value.
Additionally, if the supply voltage comes up too fast, this
clear pulse may be too narrow for reliable clearing. In gener·
ai, this is not a problem, but if the UART internal "MODE"
FIF should come up set, the byte and chip ENable lines will
become active outputs. In many systems this could lead to
bus conflicts, especially in non·handshake systems. In any
case, SEN should be high (held high for non-handshake
systems) to ensure that the MODE FIF will be cleared as
fast as possible (see Figure 12 for timing). For these and
other reasons, adequate supply bypass is recommended.

Oscillator
The ICL7104-14 is provided with a versatile three terminal
oscillator to generate the internal clock. The oscillator may
be overdriven, or may be operated as an RC or crystal oscillator.
Figure 15 shows the oscillator configured for RC operation. The internal clock will be of the same frequency and
phase as the voltage on the CLOCK 3 pin. The resistor and
capacitor should be connected as shown. The circuit will
oscillate at a frequency given by f = .45/RC. A 50 - 100kO
resistor is recommended for useful ranges of frequency. For
optimum 60Hz line rejection, the capacitor value should be
chosen such that 32768 (·16), 8192 (·14) clock periods is
close to an integral multiple of the 60Hz period.

Initial Clear Circuitry
The internal logic of the 7104 is supplied by an internal
regulator between V + + and Digital Ground. The regulator
includes a low-voltage detector that will clear various registers. This is intended to ensure that on initial power-up, the
control logic comes up in Auto-Zero, with the 2nd, 3rd, and
4th MSB bits cleared, and the "mode" F IF cleared (i.e. in
"direct" mode). This, however, will also clear these regis-

lNTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been charBcteriz9d but are not tested.

3·37

.......o
...

•

......~

ICL8052/ICL 7104 and ICL8068/ICL 7104

..I
()

POWER SUPPLY SEQUENCING

=::.

Because of the nature of the CMOS process used to fabricate the ICL7104, and the multiple power supplies used,
there are certain conditions of these supplies under which a
disabling and potentially damaging SCR action can occur.
All of these conditions involve the V + supply (nom. + 5V)
being more positive than the V + + supply. If there is any
possibility of this occuring during start-up, Shut down, under
transient conditions during operation, or when inserting a
PC board into a "hot" socket, etc., a diode should be placed
between V+ and V + + to prevent it. A germanium or
Schottky rectifier diode would be best, but in most cases a
silicon rectifier diode is adequate.

co

o
o

co

..I

~

"
o
......
C
1\1

24

26

25

CLOCK

CLOCK
1

3

"III'

losc = .45/RC

..I
()

Figure 15: RC Oscillator

=::.
&\I

II)

Note that CLOCK 3 has the same output drive as the bit outputs.

o

As a result of pin count limitations, the ICL7104-16 has
only CLOCK 1 and CLOCK 2 available, and cannot be used
as an RC oscillator. The internal clock will correspond to the
inverse of the signal on CLOCK 2. Figure 16 shows a crystal
oscillator Circuit, which can be used with both 7104 versions. If an external clock is to be used, it should be applied
to CLOCK 1. The internal clock will correspond to the signal
applied to this pin.

3
~

~

ANALOG AND DIGITAL GROUNDS

0346-19

Extreme care must be taken to avoid ground loops in the
layout of ICL8068 or ICL8052/7104 circuits, especially in
16-bit and high sensitivity circuits. It is most important that
return currents from digital loads are not fed into the analog
ground line. A recommended connection sequence for the
ground lines is shown in Figure 17.

APPLICATIONS INFORMATION
Some applications bulletins that may be found useful are
listed here:
A016 "Selecting AID Converters", by Dave Fullagar
A017 "The Integrating AID Converter", by Lee Evans
A018 "Do's and Dont's of Applying AID Converters", by
Peter Bradshaw and Skip Osgood
A025 "Building a Remote Data Logging Station", by Peter
Bradshaw
A030 "The ICL7104 - A Binary Output AID Converter for
Microprocessors", by Peter Bradshaw
R005 "Interfacing Data Converter & Microprocessors", by
Peter Bradshaw et ai, Electronics, Dec. 9, 1976.

'CAPACITOR VALUE
DEPENDS ON CRYSTAL.
TYP 0-30pF.

Figure 16: Crystal Oscillator

0346-20

BUf'
OUT

.I,:/"" --'VV\r- -

--1·

1

lIP
VIN

:~ER

REF
VOLTAGE

BUF
-IN

Vref

EXTERNAL
REFERENCE
(IF USED)

+15V

-15V

1 1

8068 PIN 2

0./

DIGITAL

LOGIC

K

I

OIGONO
ICL7104
PINZ

BOARDi
EDGE

I

.J:L

DEVICE PIN

lT Y
r
T
T

>SUPPLY
RETURN

I
EP)

+sv SUPPLY BYPASS CAPACITOR(S}

Figure 17: Grounding Sequence

0346-21

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but am not tested.

3-38

ICL7109
12-Bit p,P-Compatible
AID Converter
GENERAL DESCRIPTION

FEATURES

The ICL7109 is a high performance, CMOS, low power
integrating AID converter designed to easily interface with
microprocessors.
The output data (12 bits, polarity and overrange) may be
directly accessed under control of two byte enable inputs
and a chip select input for a simple parallel bus interface. A
UART handshake mode is provided to allow the ICL7109 to
work with industry-standard UARTs in providing serial data
transmission, ideal for remote data logging applications.
The RUN/HOLD input and STATUS output allow monitoring
and control of conversion timing.
The ICL7109 provides the user with the high accuracy,
low noise, low drift, versatility and economy of the dualslope integrating AI D converter. Features like true differential input and reference, drift of less than 1p. Vrc, maximum
input bias current of 10pA, and typical power consumption
of 20mW make the ICL7109 an attractive per-channel alternative to analog multiplexing for many data acquisition applications.

• 12 Bit Binary (Plus Polarity and Overrange) Dual
Slope Integrating Analog-to-Digital Converter
• Byte-Organized TTL-Compatible Three-State Outputs
and UART Handshake Mode for Simple Parallel or
Serial Interfacing to Microprocessor Systems
• RUN/HOLD Input and STATUS Output Can Be Used
to Monitor and Control Conversion Timing
• True Differential Input and Differential Reference
• Low Noise-Typically 15p.V pop
• 1pA Typical Input Current
• Operates At Up to 30 Conversions Per Second
• On-Chip Oscillator Operates With Inexpensive
3_58MHz TV Crystal Giving 7.5 Conversions Per
Second for 60Hz Rejection May Also Be Used With
An RC Network Oscillator for Other Clock
Frequencies

ORDERING INFORMATION
Part Number

Temp. Range

Package

ICL7109MDL
ICL71091DL
ICL71091JL
ICL7109CPL

-55'C to + 125'C
- 25'C to + 85'C
- 25'C to + 85'C
O'C to 70'C

40-Pin Ceramic DIP
40-Pin Ceramic DIP
40-Pin CERDIP
40-Pin Plastic DIP

f

TOP VIEW

GND---! 1 GND
Y+40 )---<>+5Y
2 STATUS
REF IN-39
3 POL
DIFFERENTIAL
REF CAP-39
REFERENCE
4 OR
HIGH
REF CAP + 37 ~::JI:1Io'F
ORDER
5 B12
REF IN .. 36
+
BYTE
, !l
R'
6811
INPUT HIGH
IN HI 35
vvOUTPUTS
• .O,"F
7810
INPUT lOW
IN lO 34
L- 889
GND
COMMON 33
INT
988
INT 32
ICl7109
II CAl .,""f"
'087
AZ 3'
11 86
8UF 30
LOW
ORDER
12 B5
REF OUT 29
BYTE
'3 B4
Y-28
lk!l - R E F I N +
'4 B3
OUTPUTS
SEND 27
'5 B2
RUN/HOLD 26
y+
'6 Bl
BUF OSC OUT 25
+SYc>-- 17 TesT
24k!l
osc SEL 24 ;.--GND
8YTE r
'8 LliEN
OSC OUT 23
19 HIm
CONTROLl
OSC IN 22
3.5795 MHz
INPUTS _ 20~
TY CRYSTAL
MODE 21

f

,. . . ,".':t:"".".

l

rU

·RINT = 20k( l FOR O.2V REF

• 200k!l FOR 2.0Y REF
0336-'
(See Figure 2 for typical connection to a UART or Microcomputer)

Figure 1: Pin Configuration and Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
301655-003

NOTE: AI! typical values have been characterized but are not tested.

3-39

.......~

ICL7109

2 ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (GND to V +) . . . . . . . . . . . .. + 6.2V
Negative Supply Voltage (GND to V-) ............. -9V
Analog Input Voltage (Lo or Hi) (Note 1) ........ V+ to VReference Input Voltage (Lo or Hi) (Note 1) ..... V+ to VDigital Input Voltage
V+ +0.3V
(Pins 2-27) (Note 2) ....................... GND -0.3V

Power Dissipation (Note 3)
Ceramic Package ...................... 1W @ + 85'C
Plastic Package .................... 500mW @ + 70'C
Operating Temperature
Ceramic Package (MDL) ........... - 55'C to + 125'C
Ceramic Package (IDL) .............. - 25'C to + 85'C
Plastic Package (CPL) .................. O'C to + 70'C
Storage Temperature ................ -65'C to + 150'C
Lead Temperature (Soldering, 10sec) ........... +300'C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
opBration of the device at these O( any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (V+ = +5V, v-= -5V, GND=OV, TA=25'C, fCLK = 3.58 MHz, unless
otherwise indicated.) Test circuit as shown on first page of this data sheet.
ANALOG SECTION
Symbol

Parameter

Test Conditions

Zero Input Reading

VIN=O.OV
Full Scale = 409.6mV

Ratiometric Reading

VIN=VREF
VREF=204.8mV

Non-Linearity (Max deviation
from best straight line fit)

Full Scale = 409.6mV to 2.048V
Over full operating temperature
range. (Note 4), (Note 6)

Roll-over Error (difference
in reading for equal pos. and
neg. inputs near full scale)

Full Scale = 409.6mV to 2.048V
(Note 5), (Note 6)

Min

-OOOOs

Typ

Max

Unit

Octal
±OOOOs +OOOOs
Reading

3777s

3777s
4000s

4000 8

Octal
Reading

-1

±.2

+1

Counts

-1

±.2

+1

Counts

CMRR

Common Mode Rejection Ratio

VCM ±1VVIN=OV
Full Scale=409.6mV

VCMR

Input Common Mode Range

Input Hi, Input Lo, Common (Note 4)

en

Noise (p-p value not
exceeded 95% of time)

VIN=OV
Full Scale = 409.6mV

15

IILK

Leakage current at Input

VIN = 0 All devices at 25'C
ICL7109CPL O'CsTAs + 70'C (Note 4)
ICL71091DL -25'CsTAs +85'C (Note 4)
ICL7109MDL -55'CsTAs + 125'C

1
20
100
2

10
100
250
5

pA
pA
pA
nA

0.2

1

",VI'C

1

5

ppm/'C

50

",VIV
V+ -1.0

V-+1.5

V
",V

Zero Reading Drift

VIN=OV R1 =00 (Note 4)

Scale Factor Temperature
Coefficient

VIN=408.9mV= > 7770s
reading
Ext. Ref. 0 ppm/'C (Note 4)

1+

Supply Current V + to
GND

VIN=O, Crystal Osc
3.58MHz test circuit

700

1500

",A

Isupp

Supply Current V + to V-

Pins 2-21 , 25, 26, 27, 29; open

700

1500

",A

VREF

Ref Out Voltage

Referred to V + , 25kO
between V+ and REF OUT

-2.8

-3.2

V

Ref Out Temp. Coefficient

25kO between V+ and REF OUT

-2.4

80

ppml'C

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

3-40

.o~on. (Ii
r-

ICL7109

.......

i

ELECTRICAL CHARACTERISTICS (V+ = +5V, V- = -5V, GND=OV, TA=25'C, unless otherwise
indicated.) Test circuit as shown on first page of this data sheet. (Continued)
DIGITAL SECTION
Symbol

Parameter

Test Conditions

VOH

Output High Voltage

IOUT=100fLA
Pins 2-16,18,19,20

VOL

Output Low Voltage

IOUT=1.6mA

Output Leakage Current

Pins 3-16 high impedance

Control 110 Pull up
Current

Pins 18, 19, 20VOUT=V+ -3V
MODE input at GND

Control 1/0 Loading

HBEN Pin 19 LBEN Pin 18 (Note 4)

VIH

Input High Voltage

Pins 18-21, 26, 27
referred to GND

Vil

Input Low Voltage

Pins 18-21, 26, 27
referred to GND

Min

Typ

3.5

4.3

Max

Unit

V

0.2

0.4

V

±.01

±1

fLA

5

fLA
50

2.5

pF
V

1

V

Input Pull-up Current

Pins 26,27 VOUT=V+ -3V

5

/LA

Input Pull-up Current

Pins 17, 24 VOUT=V+ -3V

25

/LA

Input Pull-down Current

Pin 21 VOUT=GND +3V

5

/LA

High

VOUT=2.5V

1

mA

OOH

Oscillator Output

OOl

Current

Low

VOUT=2.5V

1.5

mA

BOOH

Buffered Oscillator

High

VOUT=2.5V

2

mA

BOOl

Output Current

Low

VOUT=2.5V

5

mA

tw

MODE Input Pulse Width

(Note 4)

50

ns

NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ± 100I'A
2. Due to the SeR structure inherent in the process used to fabricate these devices, connecting any digital inputs or outputs to voltages greater than V +
or less than GND may cause destructive device latchup. For this reason it is recommended that no inputs from sources other than the same power
supply be applied to the ICL7109 before its power supply is established, and that in multiple supply systems the supply to the ICL7109 be activated first.
3. This limit refers to that of the package and will not be obtained during normal operation.
4. This parameter is not production tested, but is guaranteed by design.
S. Roll-over error for TA= - 55°C to + 125°C is ± 3 counts maximum.
6. A full scale voltage of 2.048V is used because a full scale voltage of 4.096V exceeds the devices Common Mode Voltage Range.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charsct8lized but are not tested

3-41

......~

~

ICL7109
TABLE 1: Pin Assignment and Function Description
Pin

Symbol

Description

Pin

t

GND

Digital Ground, OY. Ground return for all digital
logic.

2

STATUS

Output High during integrate and deintegrate
until data is latched.
Output Low when analog section is in AutoZero configuration.

3

POL

Polarity - HI for Positive input.

4

OR

Overrange - HI if Overranged.

5

B12

Bit12

6

Bll

Bitll

Symbol

21

MODE

Description
Input Low - Direct output mode where
CE7I15Al5 (Pin 20), HBEN (Pin 19) and LBEN
(Pin 18) act as inputs directly contrOlling byte
outputs.
Input Pulsed High - Causes immediate entry
into handshake mode and output of data as in
Figure 10.
Input High - Enables CE/[OAD (Pin 20),
HBEN (Pin 19), and LBEN (Pin 18) as
outputs, handshake mode will be entered and
data output as in Figures 8 and 9 at
conversion completion.

(Most Significant Bit)

7

Bl0

Bnl0

All

22

OSCIN

Oscillator Input

8

B9

Bit 9

three

23

OSCOUT

Oscillator Output

state

24

OSCSEL

Oscillator Select -Input high configures
OSC IN, OSC OUT, BUF OSC OUT as RC
oscillator - clock will be same phase and
duty cycle as BUF OSC OUT.
- Input low configures OSC IN, OSC OUT for
crystal oscillator - clock frequency will be
1/58 of frequency at BUF OSC OUT.

9

B8

Bit 8

10

B7

Bit 7

HI = true

output

11

BS

BitS

data

12

B5

Bit 5

bits

13

B4

Bit4

14

B3

Bn3

15

B2

Bit 2

16

Bl

Bnl

17

TEST

18

LBEN

25

BUF OSC OUT Buffered Oscillator Output

26

RUN/FiO[i)

Input High - Normal Operation.
Input Low - Forces all bit outputs high.
Note: This input is used for test purposes only.
Tie high if not used.

Input High - Conversions continuously
performed every 8192 clock pulses.
Input Low - Conversion in progress
completed, converter will stop in Auto-Zero 7
counts before integrate.

27

SEND

Low Byte Enable - With Mode (Pin 21) low,
and CE7I15Al5 (Pin 20) low, taking this pin low
activates low order byte outputs Bl - B8.

Input - Used in handshake mode to indicate
ability of an external device to accept data.
Connect to + 5Y if not used.

28

Y-

Analog Negative Supply - Nominally -5Y
with respect to GND (Pin 1).

29

REF OUT

Reference Yoltage Output - Nominally 2.8Y
down from Y' (Pin 40).

(Least Significant Bit)

- With Mode (Pin 21) high, this pin serves as a
low byte flag output used in handshake mode.
See Figures 8, 9, 10.
19

HBEN

High Byte Enable - With Mode (Pin 21) low,
and CE/LOAD (Pin 20) low, taking this pin low
activates high order byte outputs B9 - B12,
POL,OR.
- With Mode (Pin 21) high, this pin serves as a
high byte flag output used In handshake mode.
See Figures 8, 9, 10.

20

CE/LOAD

Chip Enable Load - With Mode (Pin 21) low.
CE/LOAD serves as a master output enable.
When high, Bl - B12, P~L, OR outputs are
disabled.
- With Mode (Pin 21) high, this pin serves as a
load strobe used in handshake mode. See
Figures 8, 9, 10.

30

BUFFER

Buffer Amplifier Output

31

AUTO-ZERO

Auto-Zero Node -Inside foil of CAZ

32

INTEGRATOR

Integrator Output - Outside foil of CINT

33

COMMON

Analog Common - System is Auto-Zeroed to
COMMON

34

INPUTLO

Differential Input Low Side

35

INPUT HI

Differential Input High Side

36

REF IN

37

REF CAP

38

REF CAP

Reference Capacitor Negative

39

REF IN

Differential Reference Input Negative

40

Y+

Positive Supply Yoltage - Nominally
with respect to GND (Pin 1).

+

Differential Reference Input Positive

+

Reference Capacitor Positive

+ 5V

Note: All dignallevels are positive true.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typic81 vaJU98 hsVB bssn chsracterlzsd but BI6 not tested.

3-42

.D~DIl.

ICL7109

n
r-

.......o
I&)

-SV
OND
.IV

1 V·

OND

'SV

2.TATUI

1000 pF

GND
.IV

3-8
"-III2.POL.OR

T'::;~I-------''I------+'''f-It~-\a

1-

V·40
REF IN- 311------... :- - -GND

=::::: :;,.,

TRU4
ORR"
DR It
TIRL 23
TIRE 22
MR21

• IV

17 niT
" tIIlI
21 MODI

20 erm!m

27 SEND

GND

CMOS UART

Iln=~1

3I1~:~~~~;.~

I~ ~ :

ItHIIN

13'1
14 FE
IS DE
" SFD

IGND

t - - - - - - ; 1--------i.IUF DIC OUT

2 DSC CONTROL
3 GND
4 RRD
5-12
RIRI-8

GND

AI'C~~
IN .. ~

.u

31
IUF30
REF OUT 21
V-2'

RUNiHOLaa

OSC IEL 24

INT

~v

INPUT

.15 F

HINT 2OkO O.2V AEF
_n2VRIF

.IV OROPIN
GND

ose OUT 23 ,------::JOSC IN 22

FOR ~OWIIT POW'" CONSUMPTION,
TlR'·T.... INN" SHOU&.D HAYl,OOtn
NLLUP "ISIITORI TO +SY

ICL71"
CMOS AID CONVERTER
0336-2

Figure 2A: Typical Connection Diagram UART Interface - To transmit latest result, send any word to UART

.,V
OND
.IV

'IV

40 v'
1 GND
17 TIST

ICL71"
QND

a

RUNJRl5IlS
2 STATUI
11 LIIR

.IV
'SV
_SV
-SV

ItRm

12-1t
080-087
QND

20-

iilho

RlFIN 3S
.REF CAP - 3t
RIF CAP. 37
REF IN. 31
IN HI 35
IN LO 34
COM 33
INT 32

=--OND
EXTERNAL
REFERENCE

1.F

:.NPUT
~N~'.F

.u31

aUF 30
REF OUT a

v-a

SEND 27
IUF OSC OUT 2'..
OSC SIL 2'
OSC OUT H
OIC IN 22
MODE 21

H.NT 2Ok0 O.2Y AEF.

-tV
.IV

_navRIF.

OND

0336-3

Figure 2B: Typical Connection Diagram Parallel Interface With 8048 Microcomputer
Auto-Zero Phase

DETAILED DESCRIPTION
Analog Section

During auto-zero three' things happen. First, input high
and low are disconnected from their pins and internally
shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback
loop is closed around the system to charge the auto-zero
capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the ioop, the AZ accuracy is limited only by
the noise of the system. In any case, the offset referred to
the input is less than 101-'V.
.

Figure 3 shows the equivalent circuit of the Analog Section of the ICL71 09. When the RUNIHOLD input is left open
or connected to V + , the circuit will perform conversions at a
rate determined by the clock frequency (8192 clock periods
per cycle). Each measurement cycle is divided into three
phases as shown in Figure 4. They are (1) Auto-Zero (AZ),
(2) Signal Integrate (I NT) and (3) Deintegrate (DE).

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characteriz9d but are not tested

3-43

.......~
...
S:!

ICL7109

CREF

AEFCAP,.

r--I

I
I
I

INPUT HIGH ~-()(}-""T-t---...,..---I----f
135

I

I
I
I

1

I

COMMONQt~-~-~

_ _~

6.2V

133

I

AZT FROM CONTROL
IN
LOGIC
DEINT (+) DIGITAL SECTION
DEINT(-)-

I

INPUTLOQr-()(}---~---------------~

134

I
I

I
29'-----+
~---------------------REF OUT

40

v+
0336-4

Figure 3: Analog Section

I
INTEGRATOH
OUTPUT

POLARITY
DETECTEO~

ZERO CROSSING
OCCURS
ZERO CROSSING

I

I
______~I~~~' ~
DETECTED
I
--~
I
I--AZ
PHASE I--i-'NT PHASE 1I~t---+-i-,..L-DEINT PHASE III---1--AZ-

INTERNAL CLOCK

h..r ~ J1J1I1h.. .Jl11SLfl.r' '1.I1J1..hn..r

INTERNAL LATCH

II.
1

II

II

h

II

I

I
I
I

I
I
I

I
I
1

I

STATUS OUTPUT I

I

2048
I
FIXED
I---COUNTS~ 2048
1
MIN.
I
COUNTS

I

I

NUMBER OF COUNTS TO ZERO CROSSING
PROPORTIONAL TO V,N

I

"

I "

I

4096 COUNTS---.j
MAX

I

""-AFTER ZERO CROSSING,
ANALOG SECTION WILL
BE IN AUTOZERO
CONFIGURATION
0336-5

Figure 4: Conversion Timing (RUN/HOLD Pin High)

Signal Integrate Phase

De-Integrate Phase

During signal integrate the auto-zero loop is opened, the
internal short is removed and the internal high and low inputs are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time of 2048 clock periods. Note that this differential voltage must be within the common mode range of
the inputs. At the end of this phase, the polarity of the integrated Signal is determined.

The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged (during
auto-zero) reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct
polarity to cause the integrator output to return to zero
crossing (established in Auto Zero) with a fixed slope. Thus
the time for the output to return to zero (represented by the
number of clock periods counted) is proportional to the input signal.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPAESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3-44

~U~UIL C;

ICL7109

r"'

reduced further. This will increase both noise and rollover
errors. To improve the performance, supplies of ± 6V may
be used.

Differential Input
The input can accept differential voltages anywhere within the common mode range of the input amplifier; or specifically from 1.0 volts below the positive supply to 1.5 volts
above the negative supply. In this range the system has a
CMRR of 86dB typical. However, since the integrator also
swings with the common mode voltage, care must be exercised to assure the integrator output does not saturate. A
worst case condition would be a large positive common
mode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator
positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the
recommended 4V full scale with some loss of accuracy. The
integrator output can swing within 0.3 volts of either supply
without loss of linearity.
The ICL7109 has, however, been optimized for operation
with analog common near digital ground. With power supplies of + 5V and - 5V, this allows a 4V full scale integrator
swing positive or negative thus maximizing the performance
of the analog section.

Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 100!,-A of quiescent current. They supply
20!,-A of drive current with negligible non-linearity. The integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 4.096 volt full scale, 200kO, is near optimum and similarly a 20kO, for a 409.6mV scale. For other
values of full scale voltage, RtNT should be chosen by the
relation
R
full scale voltage
tNT
20!,-A

Integrating Capacitor
The integrating capacitor CtNT should be selected to give
the maximum integrator output voltage swing without saturating the integrator (approximately 0.3 volt from either supply). For the ICL7109 with ± 5 volt supplies and analog
common connected to GND, a ± 3.5 to ± 4 volt integrator
output swing is nominal. For 7-% conversions per second
(61.72kHz clock frequency) as provided by the crystal oscillator, nominal values for CtNT and CAl are 0.15!,-F and
0.33!,-F, respectively. If different clock frequencies are used,
these values should be changed to maintain the integrator
output voltage swing. In general, the value of CtNT is given
by
(2048 x clock period)(20!,-A)
CtNT integrator output voltage swing

Differential Reference
The reference voltage can be generated anywhere within
the power supply voltage of the converter. The main source
of common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage,
the reference capacitor can gain charge (increase voltage)
when called up to deintegrate a positive signal but lose
charge (decrease voltage) when called up to deintegrate a
negative input signal. This difference in reference for (+) or
( -) input voltage will give a roll-over error. However, by
selecting the reference capacitor large enough in comparison to the stray capacitance, this error can be held to less
than 0.5 count for the worst case condition (see Component
Values Selection below).
The rOil-over error from these sources is minimized by
having the reference common mode voltage near or at analog COMMON.

An additional requirement of the integrating capacitor is
that it have low dielectric absorption to prevent rOil-over errors. While other types of capacitors are adequate for this
application, polypropylene capacitors give undetectable errors at reasonable cost up to 85'C. For the military temperature range, Teflon® capacitors are recommended. While
their dielectric absorption characteristics vary somewhat
from unit to unit, selected devices should give less than 0.5
count of error due to dielectric absorption.

Component Value Selection

Auto-Zero Capacitor

For optimum performance of the analog section, care
must be taken in the selection of values for the integrator
capacitor and resistor, auto-zero capacitor, reference voltage, and conversion rate. These values must be chosen to
suit the particular application.
The most important consideration is that the integrator
output swing (for full-scale input) be as large as possible.
For example, with ±5V supplies and COMMON connected
to GND, the nominal integrator output swing at full scale is
± 4V. Since the integrator output can go to 0.3V from either
supply without significantly affecting linearity, a 4V integrator output swing allows 0.7V for variations in output swing
due to component value and oscillator tolerances. With
± 5V supplies and a common mode range of ± 1V required,
the component values should be selected to provide ± 3V
integrator output swing. Noise and rollover errors will be
slightly worse than in the ± 4V case. For larger common
mode voltage ranges, the integrator output swing must be

The size of the auto-zero capacitor has some influence
on the noise of the system: the smaller the capacitor the
lower the overall system noise. However, CAl cannot be
increased without limits since it, in parallel with the integrating capacitor forms an R-C time constant that determines
the speed of recovery from overloads and more important
the error that exists at the end of an auto-zero cycle. For
409.6mV full scale where noise is very important and the
integrating resistor small, a value of CAl twice CtNT is optimum. Similarly for 4.096V full scale where recovery is more
important than noise, a value of CAl equal to half of CtNT is
recommended.
For optimal rejection of stray pickup, the outer foil of CAl
should be connected to the R-C summing junction and ~he
inner foil to pin 31. Similarly the outer foil of CtNT should be
connected to pin 32 and the inner foil to the R-C summing
junction. Teflon®, or equivalent, capacitors are recommended above 85'C for their low leakage characteristics.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PAATICULAR USE.

NOTE All typ;cal values have been characterized but are not tested

3-45

.......
0

CD

.....

! ICL7109
~ Reference Capacitor

Note that if pins 29 and 39 are tied together and pins 39
and 40 accidentally shorted (e.g .• during testing). the reference supply will sink enough current to destroy the device.
This can be avoided by placing a 1kn resistor in series with
pin 39.

A 1J.tF capacitor gives good results in most applications.
However. where a large reference common mode voltage
exists (Le. the reference low is not at analog common) and
a 409.6mV scale is used. a larger value is required to prevent roll-over error. Generally 10J.tF will hold the roll-over
error to 0.5 count in this instance. Again. Teflon®. or equivalent capacitors should be used for temperatures above 85'C
for their low leakage characteristics.

DETAILED DESCRIPTION
Digital Selection
The digital section includes the clock oscillator and scaling circuit. a 12-bit binary counter with output latches and
TTL-compatible three-state output drivers. polarity. overrange and control logic. and UART handshake logic. as
shown in Figure 5.
Throughout this description. logic levels will be referred to
as "fow" or "high". The actual logic levels are defined in the
Electrical Characteristics Table. For minimum power consumption. all inputs should swing from GND (low) to V+
(high). Inputs driven from TTL gates should have 3-5kn
pullup resistors added for maximum noise immunity.

Reference Voltage
The analog input required to generate a full scale output
of 4096 counts is VIN = 2VREF. Thus for a normalized scale.
a reference of 2.048V should be used for a 4.096V full
scale. and 204.8mV should be used for a 0.4096V full scale.
However. in many applications where the AID is sensing
the output of a transducer. there will exist a scale factor
other than unity between the absolute output voltage to be
measured and a desired digital output. For instance. in a
weighing system. the designer might like to have a full scale
reading when the voltage from the transducer is 0.682V.
Instead of dividing the input down to 409.6mV. the input
voltage should be measured directly and a reference voltage of 0.341V should be used. Suitable values for integrating resistor and capacitor are 33kn and 0.15J.tF. This avoids
a divider on the input. Another advantage of this system
occurs when a zero reading is desired for non-zero input.
Temperature and weight measurements with an offset or
tare are examples. The offset may be introduced by connecting the voltage output of the transducer between common and analog high. and the offset voltage between common and analog low. observing polarities carefully. However. in processor-based systems using the ICL7109. it may
be more efficient to perform this type of scaling or tare subtraction digitally using software.

MODE Input
The MODE input is used to control the output mode of the
converter. When the MODE pin is low or left open (this input
is provided with a pulldown resistor to ensure a low level
when the pin is left open). the converter is in its "Direct"
output mode. where the output data is directly accessible
under the control of the chip and byte enable inputs. When
the MODE input is pulsed high. the converter enters the
UART handshake mode and outputs the data in two bytes.
then returns to "direct" mode. When the MODE input is left
high. the converter will output data in the handshake mode
at the end of every conversion cycle. (See section entitled
"Handshake Mode" for further details).

STATUS Output

Reference Sources

During a conversion cycle. the STATUS output goes high
at the beginning of Signal Integrate (Phase II). and goes low
one-half clock period after new data from the conversion
has been stored in the output latches. See Figure 4 for details of this timing. This signal may be used as a "data valid"
flag (data never changes while STATUS is low) to drive interrupts. or for monitoring the status of the converter.

The stability of the reference voltage is a major factor in
the overall absolute accuracy of the converter. The resolution of the ICL7109 at 12 bits is one part in 4096. or
244ppm. Thus if the reference has a temperature coefficient
of 80ppml"C (onboard reference) a temperature difference
of 3'C will introduce a one-bit absolute error.
For this reason. it is recommended that an external highquality reference be used where the ambient temperature is
not controlled or where high-accuracy absolute measurements are being made.
The ICL7109 provides a REFerence OUTput (pin 29)
which may be used with a resistive divider to generate a
suitable reference voltage. This output will sink up to about
20mA without significant variation in output voltage. and is
provided with a pullup bias device which sources about
10J.tA. The output voltage is nominally 2.8V below V+. and
has a temperature coefficient of ± 80ppml"C typo When using the onboard reference. REF OUT (Pin 29) should be
connected to REF - (pin 39). and REF + should be connected to the wiper of a precision potentiometer between
REF OUT and V+. The circuit for a 204.8mV reference is
shown in the test circuit. For a 2.048mV reference. the fixed
resistor should be removed. and a 25kn precision potentiometer between REF OUT and V+ should be used.

RUN/HOLD Input
When the RUN/HOLD input is high. or left open. the circuit will continuously perform conversion cycles. updating
the output latches after zero crossing during the Deintegrate (Phase III) portion of the conversion cycle (See Figure
4). In this mode of operation. the conversion cycle will be
performed in 8192 clock periods. regardless of the resulting
value.
If RUN/HOLD goes low at any time during Deintegrate
(Phase III) after the zero crossing has occurred. the circuit
will immediately terminate Deintegrate and jump to AutoZero. This feature can be used to eliminate the time spent in
Deintegrate after the zero-crossing. If RUN/HOLD stays or
goes low. the converter will ensure minimum Auto-Zero
time. and then wait in Auto-Zero until the RUN/HOLD input
goes high. The converter will begin the Integrate (Phase II)
portion of the next conversion (and the STATUS output will
go high) seven clock periods after the high level is detected
at RUN/HOLD. See Figure 6 for details.

lNTERSIL'S SOLE AND EXCLUSiVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOT£: All typical values have been characterized but are not tested.

3-46

~O~OIl.

ICL7109

TEST

t

HIGH ORDER ~ LOW ORDER

BYTE OUTPUTS

POL OR

BYTE OUTPUTS

;-;I

o

CD

BBBBBBBBBBBB
12 11 10 9 8 7 6 5 4 3 2 1

17

[:=~~::::::~~'8~~

HiiEN
CEiLi5AI'i

19

20

I
I
I

I
I
I
I

I
I
I

COMP OUT
TO AZ
ANALOG { INT
SECTION DEINT("t')
DEINT(-)
~"',...----r....l

STATUS

RUN/

HOiJ'i

I
I
I

---i-J

_21 _ _ 27
MODE
SEND

asc osc osc aUF

GND

IN OUT SEL OSC
OUT

0336-6

Figure 5: Digital Section

-------

~:':R6E~~6~~i~~

f---A~~~~~~O-J

t-:::'~SE"

"
I MIN 1790 COUNTS I. STATIC IN
I
..--~TECTION
--...... '_J'\.I
MAX 2041 COUNTS I HOLD STATE
~ .--+-1 1 - - 7 COUNTS------"; - - - ...
INTERNAL CLOCK Lr '111.I1J'1..
.l1IU1.rtI1J1.. ..11J1.nn.n..
~
-uu-t.rtnnJ1Jl.
I
I
INTERNAL LATCH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...n
I
I
INTEGRATOR
OUTPUT

STATUS OUTPUT
RUN/HOLD INPUT

======~--;":...----------------------..,L_rI..__

r--

-.J L ________:___ _
0336-7

Figure 6: Run/Hold Operation
Using the RUN/HOLD input in this manner allows an
easy "convert on demand" interface to be used. The converter may be held at idle in auto-zero with RUN/HOLD low.
When RUN/HOLD goes high the conversion is started, and
when the STATUS output goes low the new data is valid (or
transferred to the UART - see Handshake Mode). RUN/
HOLD may now be taken low which terminates deintegrate
and ensures a minimum Auto-Zero time before the next
conversion.
Alternately, RUN/HOLD can be used to minimize conversion time by ensuring that it goes low during Deintegrate,
after zero crossing, and goes high after the hold point is
reached. The required activity on the RUN/HOLD input can
be provided by connecting it to the Buffered Oscillator Output. In this mode the conversion time is dependent on the
input value measured. Also refer to Intersil Application BUlletin A032 for a discussion of the effects this will have on
Auto-Zero performance.

If the RUN/HOLD input goes low and stays low during
Auto-Zero (Phase I), the converter will simply stop at the
end of Auto-Zero and wait for RUN/HOLD to go high. As
above, Integrate (Phase II) begins seven clock periods after
the high level is detected.

Direct Mode
When the MODE pin is left at a low level, the data outputs
(bits 1 through 8 low order byte, bits 9 through 12, polarity
and over-range high order byte) are accessible under control of the byte and chip enable terminals as inputs. These
three inputs are all active low, and are provided with pullup
resistors to ensure an inactive high level when left open.
When the chip enable input is low, taking a byte enable
input low will allow the outputs of that byte to become active
(three-stated on). This allows a variety of parallel data accessing techniques to be used, as shown in the section entitled "Interfacing." The timing requirements for these outputs are shown in Figure 7 and Table 2.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have bgen characterized but are not tested.

3-47

(;
...r-....

GI

....0....
...

ICL7109
ICL7109 provides all the control and flag signals necessary
to sequentially transfer two bytes of data into the UART and
initiate their transmission in serial form. This greatly eases
the task and reduces the cost of designing remote data acquisition stations using serial data transmission.
Entry into the handshake mode is controlled by the
MODE pin. When the MODE terminal is held high, the
ICL7109 will enter the handshake mode after new data has
been stored in the output latches at the end of a conversion
(See Figures 8 and 9). The MODE terminal may also be
used to trigger entry into the handshake mode on demand.
At any time during the conversion cycle, the low to high
transition of a short pulse at the MODE input will cause
immediate entry into the handshake mode. If this pulse occurs while new data is being stored, the entry into handshake mode is delayed until the data is stable. While the
converter is in the handshake mode, the MODE input is
ignored, and although conversions will still be performed,
data updating will be inhibited (See Figure 10) until the converter completes the output cycle and clears the handshake
mode.
When the converter enters the handshake mode, or when
the MODE input is high, the chip and byte enable terminals
become TTL-compatible outputs which provide the control
signals for the output cycle (See Figures 8, 9, and 10).
In handshake mode, the SEND input is used by the converter as an indication of the ability of the receiving device
(such as a UART) to accept data.
Figure 8 shows the sequence of the output cycle with
SEND held high. The handshake mode (Internal MODE
high) is entered after the data latch pulse, and since MODE
remains high the CE/LOAD, LBEN and HBEN terminals are
active as outputs. The high level at the SEND input is
sensed on the same high to low internal clock edge that
terminates the data latch pulse. On the next low to high
internal clock edge the CE/LOAD and the HBEN outputs
assume a low level, and the high-order byte (bits 9 through
12, POL, and OR) outputs are enabled. The CE/LOAD output remains low for one full internal clock period only, the
data outputs remain active for 1-% internal clock periods,
and the high byte enable remains low for two clock periods.
Thus the CE/LOAD output low level or low to high edge
may be used as a synchronizing signal to ensure valid data,
and the byte enable as an output may be used as a byte
identification flag. With SEND remaining high the converter
completes the output cycle using CE/LOAD and LBEN
while the low order byte outputs (bits 1 through 8) are activated. The handshake mode is terminated when both bytes
are sent.
Figure 9 shows an output sequence where the SEND input is used to delay portions of the sequence, or handshake
to ensure correct data transfer. This timing diagram shows
the relationships that occur using an industry-standard
IM640% CMOS UART to interface to serial data channels.
In this interface, the SEND input to the ICL7109 is driven by
the TBRE (Transmitter Buffer Register Empty) output of the
UART, and the CE/LOAD terminal of the ICL7109 drives
the TBRL (Transmitter Buffer Register Load) input to the
UART. The data outputs are paralleled into the eight Transmitter Buffer Register inputs.

Table 2 - Direct Mode Timing
Requirements

!:!

(See Note 4 of Electrical Characteristics)
SYMBOL

DESCRIPTION

MIN

TYP

tBEA

Byte Enable Width

350

220

tOAB

Data Access Time
from Byte Enable

210

350

ns

tOHB

Data Hold Time
from Byte Enable

150

300

ns

tCEA

Chip Enable Width

tOAC

Data Access Time
from Chip Enable

260

400

ns

tOHC

Data Hold Time
from Chip Enable

240

400

ns

400

MAX

UNIT

ns

260

ns

IIImI

AS INPUT

[J!R
AS INPUT

LOW:!:::: ______________

~

~_

- - - - = HIGH IMPEDANCE

0336-8

Figure 7: Direct Mode Output Timing
It should be noted that these control inputs are asynchronous with respect to the converter clock - the data may be
accessed at any time. Thus it is possible to access the
latches while they are being updated, which could lead to
erroneous data. Synchronizing the access of the latches
with the conversion cycle by monitoring the STATUS output
will prevent this. Data is never updated while STATUS is
low.

Handshake Mode
The handshake output mode is provided as an alternative
means of interfacing the ICL7109 to digital systems, where
the AID converter becomes active in controlling the flow of
data instead of passively responding to chip and byte enable inputs. This mode is specifically designed to allow a
direct interface between the ICL7109 and industry-standard
UARTs (such as the Intersil1M6402/3) with no external logic required. When triggered into the handshake mode, the

tNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valU9s have been characterized but are not tested.

3-48

ICL7109
UROCROUIHG

"-

lNTlGRATOft
OUTPUT

INTERNAL
CLOCI(

INTERNAL

L
HRO eRO"'NO
!/DITECTED

IOCCURS

~~t--~t--~r-rtr-

LATCH

STATUI
OUTPUT

110"
INPUT
MODE HIGH ACTIVATeS

INTERNAL UART
MODE NDO.

CI1mD,~, tIIR

---

.....

INPUT

HIGHaYrE
DATA

LOWBYT£

DATA

-

1.:=, /"

f.--......____
liN'

J

"".1 _.1_

'~~DI LOW. NOT

k::: ~_.1_

J

1\

--------\------

:=~:~Dlf!7mID.RI1

DATA-VALID

1---

---------r---

------------ --- ---------r---

DATAYALID

_"'GoneM!

_.L_..t.._

- - - - = THIIH·I'ATE HIGH .PlDANCI

TIRMINATI,
UMTMODI

,tIIR

~:'s===

--- ------TttfID-ITATIWlTHIIUI.LIJP

0336-9

Figure 8: Handshake With Send Held Positive

INTIRNAl.
CLOCK

INTERNAL

LATCH _ _ _ _.....I

STATUI - - - - - - - /

OUTPUT
INPUT
"O.E

1--+----- ,...-+-t----- --1-+---

- - i ' l. .I1111111111 . . . . ._

_ _ _ _-

- I,....-+-----.. ,...--+-+------ --+--tTlRMINATII

INTERNAL UART

MODE ::NO:::;"::"_ _ _ _

SfND INPUT
(UART
TaRE)

\IM'MODI

11J1lIIIIlIIIIlIIIIlIIIIlII1IIrr'
:::::f=:::'--;;>.
.I

~OUTPUT
(UARTT8R1.) ------~-~
iiiiR

-------+-_l,

HIGH:m _________ _

'-----<

- -------11------ ----

LowaTTI

DA'AVAUI) _ _~-,r

DATA - - - - - - - - - -

III .

DON'T CARl!

- - - - .. THflII4TATI HIGH IMPEDANCE

0336-10

Figure 9: Handshake - Typical UART Interface Timing

tNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been characterized but are not tested.

3-49

•

.....g ICL7109
~

UIIOCR08$ING
OC:CURS
ZERO CROSSING DETECTED

::
STATUS

~

_ - + - + - - - - -_ _-+....:p:..::::=..1.,;;...."'-1_--!-.....,f----

OUTPUT

POSITIVE TRANSITION CAUSIlS

=~ ~~YM':~ '"

11I'1I.1l111l1l11l.1l.!I.mllllll'.~___

_--1--1-----_ - - - ! - - I - - - - - - _--!--IURMINATES
UAATMOOE

I

I

, . . - - - - -..

HIGtt:m __________

~

LiiN _.1_...1 __V - LOW:~:

__________ ...,
•

• DON'" CARl

~----

OATAVALID

-

~-_+-_l

-------~I---

---..1------ --+--{
'-----

-

)oj

~--------

---

. . _--..( ,. . __

.!._...!._

--+~

.J._.i_

DATA VALID

=THAII-ITATI: HIGH IMPEDANCE _.1._ .. THREe-STATE WITH PULL-UP
0336-11

Figure 10: Handshake Triggered By Mode
With the MODE input remaining high as in these examples, the converter will output the results of every conversion except those completed during a handshake operation.
By triggering the converter into handshake mode with a low
to high edge on the MODE input, handshake output sequences may be performed on demand. Figure 9 shows a
handshake output sequence triggered by such an edge. In
addition, the SEND input is shown as being low when the
converter enters handshake mode. In this case, the whole
output sequence is controlled by the SEND input, and the
sequence for the first (high order) byte is similar to the sequence for the second byte. This diagram also shows the
output sequence taking longer than a conversion cycle.
Note that the converter still makes conversions, with the
STATUS output and RUN/HOLD input functioning normally.
The only difference is that new data will not be latched
when in handshake mode, and is therefore lost.

Assuming the UART Transmitter Buffer Register is empty,
the SEND input will be high when the handshake mode is
entered after new data is stored. The CE/LOAD and HBEN
terminals will go low after SEND is sensed, and the high
order byte outputs become active. When CE/LOAD goes
high at the end of one clock period, the high order byte data
is clocked into the UART Transmitter Buffer Register. The
UART TBRE outP~ will now go low, which halts the output
cycle with the HB N output low, and the high order byte
outputs active. When the UART has transferred the data to
the Transmitter Register and cleared the Transmitter Buffer
Register, the TBRE returns high. On the next ICL7109 internal clock high to low edge, the high order byte outputs are
disabled, and one-half internal clock later, the HBEN output
returns high. At the same time, the CE/LOAD and LBEN
outputs go low, and the low order byte outputs become active. Similarly, when the CE/LOAD returns high at the end of
one clock period, the low order data is clocked into the
UART Transmitter Buffer Register, and TBRE again goes
low. When TBRE returns to a high it will be sensed on the
next ICL7109 internal clock high to low edge, disabling the
data outputs. One-half internal clock later, the handshake
mode will be cleared, and the CE/LOAD, HBEN, and LBEN
terminals return high and slay active (as long as MODE
stays high).

Oscillator
The ICL7109 is provided with a versatile three terminal
oscillator to generate the internal clock. The oscillator may
be overdriven, or may be operated with an RC network or
crystal. The OSCILLATOR SELECT input changes the internal configuration of the oscillator to optimize it for RC or
crystal operation.

INTERSll·S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charsctsrfZBd but srB not test9d.

3,50

[lJD~DIl.

ICL7109
When the OSCILLATOR SELECT input is high or left
open (the input is provided with a pullup resistor), the oscillator is configured for RC operation, and the internal clock
will be of the same frequency and phase as the signal at the
BUFFERED OSCILLATOR OUTPUT. The resistor and capacitor should be connected as in Figure 11. The circuit will
oscillate at a frequency given by f=0.45/RC. A 100k!1 resistor is recommended for useful ranges of frequency. For
optimum 60Hz line rejection, the capacitor value should be
chosen such that 2048 clock periods is close to an integral
multiple of the 60Hz period (but should not be less than
50pF).

If at any time the oscillator is to be overdriven, the overdriving signal should be applied at the OSCILLATOR INPUT, and the OSCILLATOR OUTPUT should be left open.
The internal clock will be of the same frequency, duty cycle,
and phase as the input signal when OSCILLATOR SELECT
is left open. When OSCILLATOR SELECT is at GND, the
clock will be a factor of 58 below the input frequency.
When using the ICL71 09 with the IM6403 UART, it is possible to use one 3.58MHz crystal for both devices. The
BUFFERED OSCILLATOR OUTPUT of the ICL7109 may be
used to drive the OSCILLATOR INPUT of the UART, saving
the need for a second crystal. However, the BUFFERED
OSCILLATOR OUTPUT does not have a great deal of drive
capability, and when driving more than one slave device,
external buffering should be used.

-r
SEL

22

23

25

osc

OSC
OUT

BUFFERED
OSC
OUT

IN

When the TEST input is taken to a level halfway between
V+ and GND, the counter output latches are enabled, allowing the counter contents to be examined anytime.
When the TEST input is connected to GND, the counter
outputs are all forced into the high state, and the internal
clock is disabled. When the input returns to the % (V +
-GND) voltage (or to V+) and one clock is applied, all the
counter outputs will be clocked to the low state. This allows
easy testing of the counter and its outputs.

----

R
C

V+ OR OPEN

f osc =.45IRC
0336-12

Figure 11: RC Oscillator

INTERFACING
Direct Mode

When the OSCILLATOR SELECT input is Iowa feedback
device and output and input capacitors are added to the
oscillator. In this configuration, as shown in Figure 12, the
oscillator will operate with most crystals in the 1 to 5MHz
range with no external components. Taking the OSCILLATOR SELECT input low also inserts a fixed + 58 divider
circuit between the BUFFERED OSCILLATOR OUTPUT
and the internal clock. Using an inexpensive 3.58MHz TV
crystal, this division ratio provides an integration time given
by:
T = (2048 clock periods) x

Figure 13 shows some of the combinations of chip enable
and byte enable control signals which may be used when
interfacing the ICL71 09 to parallel data lines. The CE/LOAD
input may be tied low, allowing either byte to be controlled
by its own enable as in Figure 13A. Figure 138 shows a
configuration where the two byte enables are connected
together. In this configuration, the CE/LOAD serves as a
chip enable, and the HBEN and LBEN may be connected to
GND or serve as a second chip enable. The 14 data outputs
will all be enabled simultaneously. Figure 13C shows the
HBEN and LBEN as flag inputs, and CE/LOAD as a master
enable, which could be the READ strobe available from
most microprocessors.
Figure 14 shows an approach to interfacing several
ICL7109s to a bus, ganging the HBEN and i1iEN Signals to
several converters together, and using the CE/LOAD inputs
(perhaps decoded from an address) to select the desired
converter.

[~M8
] = 33.18ms
3.58 Hz

This time is very close to two 60Hz periods or 33.33ms. The
error is less than one percent, which will give better than
40dB 60Hz rejection. The converter will operate reliably at
conversion rates of up to 30 per second, which corresponds
to a clock frequency of 245.8kHz.
v+--~-------1~

24

ISEL

GND

G

Test Input

24

-t~

,..c;...
...0

osc
IN

osc

o

OUT

BUFFERED

osc

OUT

CRYSTAL

0336-13

Figure 12: Crystal Oscillator

INTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

3-51

•

.....g.... ICL7109

5:!

A.

GND

C.
8.

CHIP SELECT

GND

CHIP SELECT 1

GND

B9-812
POL, OR

89-B12
POL. OR

81~B12

81-88

POL. OR

14
B1-B8

ICL7109

ANALOG
IN

ANALOG

RUN/HOt:D

ICL7109

ANALOG
IN

ICL7109

IN
CONVERT

RUN/HOLD
RUN/iiOLD

CONVERT

CONVERT

CONTROL
BYTE FLAGS

0336-14

0336-16

0336-15

Figure 13: Direct Mode Chip and Byte Enable Combinations

CONVERTER
SELECT

CONVERTER
SELECT

CONVERTER
SELECT

8-BITBUS

GND

GND
MODE

CE/LOAD

GND
MODE

89·812
POL,OR

~

MODE

B9-B12
POL. OR

ICL7109

89-B12
POL. OR

a'-B8

ANALOG

8

B1-B8

ANALOG

IN

6

ICU109

tCL7109

81·88

~

8

ANALOG

IN

IN

.sv

RUN/HOLD

RUN/HOLD

-sv

LBEN

BYTE SELECT FLAGS

<
0336-17

Figure 14: Tri-stating Several 7109's to a Small Bus
Some practical circuits utilizing the parallel three-state
output capabilities of the ICL7109 are shown in Figures 15
through 20. Figure 15 shows a straightforward application to
the Intel 8048/80/85 microprocessors via an 8255PPI,
where the ICL7109 data outputs are active at all times. The
1/0 ports of an 8155 may be used in the same way. This
interface can be useJ ~" a read-anytime mode, although a
read performed while the u;;.t8. latches are being updated
will lead to scrambled data. This will occur very rarely, in the
proportion of setup-skew times to conversion time. One way
to overcome this is to read the STATUS output as well, and
if it is high, read the data again alter a delay of more than %

converter clock period. If STATUS is now low, the second
reading is correct, and if it is still high, the first reading is
correct. Alternatively, this timing problem is completely
avoided by using a read-alter-update sequence, as shown
in Figure 16. Here the high to low transition of the STATUS
output drives an interrupt to the microprocessor causing it
to access the data latches. This application also shows the
RUNIHOLD input being used to initiate conversions under
software control.
A similar interface to Motorola MC6800 or Rockwell
R650X systems is shown in Figure 17. The high to low transition of the STATUS output generates an interrupt via the

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHAll BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE All typical values have been characterized but are not tested.

3-52

ICL7109

(

~

ADDRESS BUS

I I

~

I I

1''1
I I

D

t} ~J

CDNTRDL BUS

I I

<

I I
DATA BUS

GND

I

I

MOOE

CEILOAD

~J ~} ~J

RD WA

89-BI2
PDL. DR

6

07-00

PAs-PAs

AO-A1

S
\

a

RUNIHOLD - + 5 V

ICl7109

9

a

Bl-B8

PBr-PBo

8255
(MDDEO)

8008.8080.
8085._ETC

r
STATUS

IN

GND

HiiiN

LiEN

I

I

r-S£Ewrr-

PCs

0336-18

Figure 15: Full-time Parallel Interface to 8048/80/85 Microprocessors

(

ADDRESS BUS

1r

I I

)

CDNTRDLBUS

I I

(

I I

I I

I I

DATA BUS
GND

I

I

MDDE

CEILDAD
89-812
POL. DR

tJ

RD
6

WR

t}
D7-DO

tJ

~J

AG·Al

t}

S

"S

~J

a

PAs·PAc

V
PC<;

RUNIHOLD
ICL7101

9

STATUS

IN

HI

GND

LBEN

I

I

8008.8080.

P87-PBo

J
STS"

1.F

HiiiN

8255

a

Bl-B8

8085._ETC

PC.

IOkH
PC<;

INTRA

INTR

+5V
SEE TEXT

0336-19

Figure 16: Full-time Parallel Interface to 8048/80/85 Microprocessors With Interrupt
Control Register B CBl line. Note that CB2 controls the
RUN/HOLD pin through Control Register B. allowing soft·
ware·controlled initiation of conversions in this system as
well.
The three·state output capability of the ICL7109 allows
direct interfacing to most microprocessor busses. Examples
of this are shown in Figures 18 and 19. It is necessary to
carefully consider the system timing in this type of interface.

to be sure that requirements for setup and hold times. and
minimum pulse widths are met. Note also the drive limita·
tions on long buses. Generally this type of interface is only
favored if the memory peripheral address density is low so
that simple address decoding can be used. Interrupt han·
dling can also require many additional components. and us·
ing an interface device will usually simplify the system in this
case.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3-53

•

......... ICL7109
CI

0

5i

GNO

MODE
89-812
POL,OR
ICL7109
81 ....
ANALOG
IN

•
•

PA0-6
CRI!--llR-Gll

MC880X
OR
MCS850X

P80-7
MC8820

STATUS

Cll

RUNIHOLO

CI2

GND
ADDRESS
IUS

DATA
IUS

CONTROL
IUS
0336-20

Figure 17: Full-time Parallel Interface to MC680X or MCS650X Microprocessors

eooa, SOlO, 8085

ICL7109
I1-BS

8

ANALOG
IN

CEiLciADt------'
°MEMR 01iOii
lar IlO8O/822II System

GND

+5V
0336-21

Figure 18: Direct Interface -ICL7109 to 8080/8085

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AN typ/c8I VBIuBs

""vo

~

_ _ but aro not tested.
3-54

ICL7109

GND

89-812

POL. OR

MctIOX
OR

"NALOG
IN

MCS850X
H1BIrnr-------------~

~~------------~

ADDRESS
BUS

D"TA
BUS

CONTROL
BUS

0336-22

Figure 19: Direct ICL7109 - MC680X Bus Interface
under software control. Note that one port of the 8255 is not
used, and can service another peripheral device. The same
arrangement can also be used with the 8155.
Figure 21 shows a similar arrangement with the MC6800
or MCS650X microprocessors, except that both MODE and
RUN/HOlD are tied high to save port outputs.
The handshake mode is particularly convenient for directly interfacing to industry standard UARTs (such as the Intersil IM6402/6403 or Western Digital TR1602) providing a
minimum component count means of serially transmitting
converted data. A typical UART connection is shown in Figure 2A. In this circuit, any word received by the UART causes the UART DR (Data Ready) output to go high. This drives
the MODE input to the ICl7109 high, triggering the ICl7109
into handshake mode. The high order byte is output to the
UART first, and when the UART has transferred the data to
the Transmitter Register, TBRE (SEND) goes high and the
second byte is output. When TBRE (SEND) goes high
again, lBEN will go high, driving the UART ORR (Data
Ready Reset) which will signal the end of the transfer of
data from the ICl7109 to the UART.
Figure 22 shows an ex1ension of the one converterone UART scheme to severallCl7109s with one UART. In
this circuit, the word received by the UART (available at the
RBR outputs when DR is high) is used to select which converter will handshake with the UART. With no external components, this scheme will allow up to eight ICl7109s to interface with one UART. Using a few more components to
decode the received word will allow up to 256 converters to
be accessed on one serial line.

Handshake Mode
The handshake mode allows ready interface with a wide
variety of external devices. For instance. external latches
may be clocked by the rising edge of CE/lOAD, and the
byte enables may be used as byte identification flags or as
load enables.
Figure 20 shows a handshake interface to Intel microprocessors again using an 8255PPI. The handshake operation with the 8255 is controlled by inverting its Input Buffer
Full (IBF) flag to drive the SEND input to the ICl71 09, and
using the CE/LOAD to drive the 8255 strobe. The internal
control register of the PPI should be set in MODE 1 for the
port used. If the 7109 is in handshake mode and the 8255
IBF flag is low, the next word will be strobed into the port.
The strobe will cause IBF to go high (SEND goes low),
which will keep the enabled byte outputs active. The PPI will
generate an interrupt which when executed will result in the
data being read. When the byte is read, the IBF will be reset
low, which causes the ICl7109 to sequence into the next
byte. This figure shows the MODE input to the ICl7109 connected to a control line on the PPI. If this output is left high.
or tied high separately, the data from every conversion (provided the data access takes less time than a conversion)
will be sequenced in two by1es into the system.
If this output is made to go from low to high, the output
sequence can be obtained on demand, and the interrupt
may be used to reset the MODE bit. Note that the RUNI
HOLD input to the ICl7109 may also be driven by a bit of
the 8255 so that conversions may be obtained on command

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

~~~~:~~~~JL~T~~~L~ ~~N~~~L~~~V~ ::~TI~~~~ ~~t LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
NOTE All typical values have been characterized but are not tested

3-55

•

....

IID~DIL

: ICL7109

it

~

(

ADDIIE88aul

1"'1

I I

i

(

CONTROL.US

I I

~

~JWR

RD
81-.12

POL. DR
1eL71"
.1'"

8

---

CEiLDAD
lEND

IN

li
m.

~

I I

I I

JI

~J

~J

t} I I

DATA BUS

t}
D7-DO

AD·Al

~

Ci

PA,-PAo

_.8010.

121&

(MODI 1)

PC<

1015.I00I1 ETC

Pes

RUNIHOLD

Pes

MODE

PC?

Pes

INTR

0336-23

Figure 20: Handshake Interface -ICL7109 to 8048, 80/85

.sv-.....--..,

MCIIOO

ICL71"

OR.

MC8850X

ANALOG
IN
CA2

AODRESS

.US

DATA

BUS

CONTROl.
BuS

0336-24

Figure 21: Handshake Interface -ICL7109 to MC6800, MCS650X

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF BALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE:AH /ypk»I_havobHn

_but.,. not

tos/od.

3-56

IID~Dn.

ICL7109

p
...

..
o

CO

SERIAl. OUTPUT

IJ

_CUOSUART

•'-.1
ANALOG
IN

.'-.1 8
ANALOG
IN

RUN/HOLD

.'-.1 8
ANALOG
IN

RUN/HOLO

+5V

0336-25

Figure 22: Multiplexing Converters with Mode Input
The applications of the ICL7109 are not limited to those
shown here. The purpose of these examples is to provide a
starting point for users to develop useful systems, and to
show some of the variety of interfaces and uses of the
ICL7109. Many of the ideas suggested here may be used in
combination; in particular the uses of the STATUS, RUNI
HOLD, and MODE signals may be mixed.

APPLICATION NOTES
A016
A017
A018
A030
A032

ROOS

"Selecting AID Converters," by David Fullagar
"The Integrating AID Converters," by Lee Evans
"Do's and Don'ts of Applying AID Converters," by
Peter Bradshaw and Skip Osgood
"The ICL7104 - A Binary Output AID Converter for
Microprocessors," by Peter Bradshaw
"Understanding the Auto-Zero and Common Mode
Performance of the ICL7106 Family," by Peter
Bradshaw
"Interfacing Data Converters & Microprocessors,"
by Peter Bradshaw et ai, Electronics, Dec. 9, 1976.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AH!J'pk:IJI ..IuosMVObHn

_but_not_

3-57

•

D~D[6

...~ ICL7112
~

12-Bit High-Speed
g CMOS p.P-Compatible
AID Converter
GENERAL DESCRIPTION

FEATURES

The ICL7112 is a monolithic 12-bit resolution, fast successive approximation AID converter. It uses thin film resistors and CMOS circuitry combined with an on-chip PROM
calibration table to achieve 12-bit linearity without laser trimming. Special design techniques used in the DAC and comparator result in high speed operation, while the fully static
silicon-gate CMOS circuitry keeps the power dissipation
very low.
Microprocessor bus interfacing is eased by the use of
standard memory WRite and ReaD cycle timing and control
signals, combined with Chip Select and Address pins. The
digital output pins are byte-organized and three-state gated
for bus interface to 8- and 16-bit systems.
The ICL7112 provides separate Analog and Digital
grounds for increased system accuracy. Operating with
± 5V supplies, the ICL7112 accepts OV to + 10V input with
a -10V reference or OV to -10V input with a + 10V reference.

• 12·Bit Resolution and Accuracy
• No Missing Codes
• Microprocessor Compatible Byte·Organized Buffered
Outputs
• Auto-Zeroed Comparator for Low Offset Voltage
• Low Linearity and Gain Temperature Coefficients
• low Power Consumption (60 mW)
• No Gain or Offset Adjustment Necessary
• Provides 3% Useable Overrange
• Fast Conversion (30 ,..sec_)

ORDERING INFORMATION
Part
Number

Resolution
with No
Missing
Codes

Temperature
Range

Package

tCL7112JCDL
ICL7112KCDL

11 Bits
12 BHs

O'Cto +70'C
O'Cto +70'C

40 Pin Ceramio
40 Pin Ceramic

tCL7112JtDL
ICL7112KIDL

11 Bits
12 Bits

- 25'C to + 85'C
- 25'C to + 85'C

40 Pin Ceramio
40 Pin Ceramio

ICL7112JMDL
tCL7t12KMDL

11 Bits
12 Bits

- 55'C to + 125'C 40 Pin Ceramic
- 55'C to + 125'C 40 Pin Ceramio

NC
SC

AGND

OSC2

OSC!

CS

VREF

Ao

VIN
COMP

V"
AGND

DGND

CAZ

(MSB)D l1 8

WR
OSC2
OSC!

TEST

OVR

OVR

Dld MSB)
Do (LSB)

0107-1

Figure 1: ICl7112 Functional Diagram
0107-2

Figure 2: Pin Configuration
(Outline Dwg. Dl)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
301657-001
NOTE: All typ;caJ vsluss have b6en characterized but arB not tested.

3-58

ICL7112
Operating Temperature
ICL7112XCXX .......................... O·C to + 70·C
ICL7112XIXX ....................... - 2S·C to + 70·C

ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage V + to DGND ............ - 0.3V to + 6.SV
Supply Voltage V- to DGND ............ + 0.3V to -6.SV
VREF, VIN to DGND .............................. ± 2SV
AGND to DGND ........................... + 1V to -1V

ICL7112XMXX ..................... - SS·C to + 12S·C
Storage Temperature ................. -6S·C to + 1S0·C
Power Dissipation (Note 2) ...................... SOO mW

VREF, VIN, AGND Current ........................ 2S mA
Digital 1/0 Pin Voltages ............ - 0.3V to (V + + 0.3V)
PROG to DGND Voltage ............... V- to (V+ +0.3)

derate above 70·C @10 mWrC
Lead Temperature (soldering, 10 sec.) ............. 300·C

Nole 1: All voltages with respect to DGND, unless otherwise noted.
2: Assumes all leads soldered or welded to printed circuit board.
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

D.C. ELECTRICAL CHARACTERISTICS
v+

= +SV, v- = -SV, VREF = -10.0V, TA = +2S0C, fclk = SOO kHz unless otherwise noted.

Symbol

Test Conditions

Parameter

Min

Integral Linearity Error

Note 1

TC(ILE)

Temperature Coefficient of ILE

TA

RES(NMC)

Resolution with No Missing Codes

FSE

Full Scale Calibration Error
Zero Error

Max

Units

±.024

%FSR

12

Resolution
ILE

ZE

Typ

I
I

K

= Operating Range

I
I

Bits

J

1

J

11

K

12

Power Supply Rejection Ratio

VIN

Analog Input Range (VIN, VREF) 111

RIN

Input Resistance (VIN, VREF)

ISUPPLY

Supply Current 1+, 1-

VSUPPLY

Supply Voltage Range

..

~

VIL

Low State Input Voltage

VIH

High State Input Voltage

ILiH

Logic Input Current

0< VIN < V+

VOL

Low State Output Voltage

lOUT

= 1.6 mA
= 200 /LA

ppm/·C

±0.1

%FSR

±1

LSB

±1

LSB

0

10

V

4

9

kO

2
Functional Operation Only

%FSR

1.S

Bits

Not

PSRR

±.012

±4.5

4

mA

±6.0

V

O.B

V

10

/LA

0.4

V

2.4

VOH

High State Output Voltage

lOUT

lox

Three-State Output Current

0< VOUT < V+

CR

Conversion Rate

V
1

V

2.B
1

/LA

30

/Ls

Nole 1: Full Scale Range (FSR) is 10 V (reference adjusted).
2: Assume all leads soldered or welded to printed circuit board.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED.lN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE' All typical values have been characterized but are not tested.

3-59

•

...~ ICL7115

!:i 14-Bit High-Speed
S:!

CMOS ILP-Compatible
AID Converter
GENERAL DESCRIPTION

FEATURES

The ICL7115 is the first monolithic 14-bit resolution, fast
successive approximation AID converter. It uses thin film
resistors and CMOS circuitry combined with an on-chip
PROM calibration table to achieve 13-bit linearity without
laser trimming. Special design techniques used in the DAC
and comparator result in high speed operation, while the
fully static silicon-gate CMOS circuitry keeps the power dissipation very low.
Microprocessor bus interfacing is made easy by the use
of standard WRite and ReaD cycle timing and control signals, combined with Chip Select and Address pins. The digital output pins are by1e-organized and three-state gated for
bus interface to 8 and 16-bit systems.
The ICL7115 provides separate Analog and Digital
grounds. Analog ground, voltage reference and input voltage pins are separated into force and sense lines for increased system accuracy. Operating with ±5V supplies, the
ICL7115 accepts OV to + 5V input with a - 5V reference or
OV to - 5V input with a + 5V reference.

• 14-Bit Resolution (LSB=305!,-V)
• No Missing Codes
• Microprocessor Compatible Byte-Organized Buffered
Outputs
• Fast Conversion (40!,-s)
• Auto-Zeroed Comparator for Low Offset Voltage
• Low Linearity and Gain Tempco
(1.5ppmI'C, 5ppml'C)
• Low Power Consumption (60mW)
• No Gain or Offset Adjustment Necessary
• Provides 3% Useable Overrange
• FORCE/SENSE and Separate Digital and Analog
Ground Pins for Increased System Accuracy

ORDERING INFORMATION
Part
Number

Resolution
with No
Missing Codes

Temp.
Range

Package

ICL7115JCDL
ICL7115KCDL

12 Bits
13 Bits

O'Cto +70'C
O'Cto +70'C

40 Pin Ceramic
40 Pin Ceramic

ICL7115JIDL
ICL7115KIDL

12 Bits
13 Bits

- 25'C to + 85'C
- 25'C to + 85'C

40 Pin Ceramic
40 Pin Ceramic

ICL7115JMDL
ICL7115KMDL
ICL7115JMLL
ICL7115KMLL

12 Bits
13 Bits
12 Bits
13 Bits

- 55'C to
- 55'C to
- 55'C to
-55'C to

40 Pin Ceramic
40 Pin Ceramic
40 Pin LCC
40 Pin LCC

+
+
+
+

125'C
125'C
125'C
125'C

INTERSll'S SOLE AND EXCLUSIVE WARAANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHEA WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

301659-003

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical val/J8s have been characterized but are not tested.

3-60

ICL7115
ABSOLUTE MAXIMUM RATINGS

(Note 1)
Supply Voltage V+ to DGND ........... -O.3V to +6.5V
Supply Voltage V- to DGND ........... +O.3V to -6.5V
VREFs. VREFf, VINs, VINf to DGND ........ + 25V to - 25V
AGNDs, AGND, to DGND ................. + 1V to -1V
Current in FORCE and SENSE Lines .............. 25mA
Digital 1/0 Pin Voltages ............ - O.3V to V + + O.3V
PROG to DGND Voltage .............. V- to V+ +O.3V

Operating Temperature Range
ICL7115XCXX ......................... O'Cto +70'C
ICL7115XIXX ...................... - 25'C to + 85'C
ICL7115XMXX .................... -55'Cto + 125'C
Storage Temperature Range . . . . . . . . .. - 65'C to + 150'C
Power Dissipation ............................. 500mW
derate above 70'C @ 1OOmW I'C
Lead Temperature (Soldering, 1Osee) ............. 300'C

NOTE 1: All voltages with respect to DGND, unless otherwise noted.

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absOlute
maximum rating conditions for extended penOds may affect device reliability.

.s
z

~

5

l:e It! li
4

3

2

It ..
~$

1

r!r

~

j J

...

~

VREFf

40 39 38:f1 36

6

35

CAl

33

Wli

32

sc

31
30

OSC2
OSC1

12

29

TEST

13

28

PROG

14

27

10
11

ICL7115

15
16

17 18

19 20 21

26
22 23 24 25

es

v~

34

III

RO

An
BUS

(MSB) 0'3
012

V·

011

DIIR

0'0

c5 & rS rS Q

~

~ .0 .0

d.

~

&

0337-17

(Outline DWG LL)

0337-1

(Outline DWG DL)
Figure 1: Pin Configuration

lNTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

3-61

........1ft ICL7115
....

...

!:!
lIRE,.

~N.

sa

+--'Y\,.,..-OIlREFI

OSC1

0SC2

IIIN
AGNDt
AGND.

17
DGNDC>--+

17·BITSAR
CONTROL LOGIC

V-O--+

1~4~------------OWR

r---------------O EOC
r----'\......J\ OVR
Dt3(MSB)

L-:l~-r"T"-"""" Do (LSB)

CS Ail

BUS
0337-2

Figure 2: ICL7115 Functional Diagram

INTERSIL'$ SOLE AND EXCLUSiVE WARRANTY OBLIGATION WITH RESPECT TO THIS PAODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

3·62

ICL7115
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS V+ = +5.0V, V- = -5.0V, VREFs= -5.0V, TA= + 25°C, fCLK=500kHz,
SC= VIH unless otherwise noted.
Parameter

Symbol
Resolution

ILE
TC(ILE)

Integral Linearity Error
Temperature Coefficient of ILE

Test Conditions

14

SC=VIL

12

Note 1

Min Resolution with No Missing Codes
TA = Operating Range (Note 2)

FSE
TC(FSE)

Typ

J

±0.01B
±0.012
1

J

12

K

13

J

11

K

12
±0.1

K

±O.OB

T A = Operating Range

Zero Error

Notes 1,2

Temperature Coefficient of ZE

TA = Operating Range

PSRR

Power Supply Rejection Ratio

2

TA=25°C

±%

Input Resistance (VINs, VREFs)

Supply Current, I + , 1-

Functional Operation Only

VIL

Low State Input Voltage

Operating Temperature Range

VIH

High State Input Voltage

Operating Temperature Range

ILiH

Logic Input Current

OV+

VOL

Low State Output Voltage

IOUT=1.6mA
Operating Temperature Range

VOH

High State Output Voltage

IOUT= - 2OOfLA
Operating Temperature Range

lox

Three-State Output Current

OV+

CIN

Logic Input Capacitance

COUT

Logic Output Capacitance

2

±1

LSB

kO
ppmrC

4

mA

6
±4.5

±6.0

V

O.B

V
V

2.4
1

10
0.4

2.B

fLA
V
V

1
15

Three-State

ppmrC

9

T A = Operating Range
Supply Voltage Range

LSB

1

-300

TA=25°C

VSUPPLY

ppmrC

V

4

Note 3

5

%FSR

±1

+5

T A = Operating Range

Tc(RIN)
ISUPPLY

o to

(VINs, VREFs)

ppmrC

±2

T A = Operating Range
Analog Input Range

%FSR

Bits

(Adjustable to Zero)

ZE

RIN

1.5

J

Temperature Coefficient of FSE

Unit
Bits

Full Scale Calibration Error

TC(ZE)

VIN

Max

K
T A = Operating Range
TA=25°C
RES(NMC)

Min

SC=VIH

fLA
pF

15

NOTES: 1. Full-scale range (FSR) is 5V (reference adjusted).
2. Assume all leads soldered or welded to printed circuit board.
3. Assume all leads soldered or welded to printed circuit board.

INTERStL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: Alf typical values have been characterized but are not tested

3-63

......= ICL7115

IID~DII.

~

--r

~ ~~~~~________~VA~L~ID~-.____

1III=~1
Do-D..

IN71_
.

--------------------~---«

•~ ~~~~-----------~---------r---------------~

= DON'T CARE
0337-3

Figure 3: Read Cycle Timing

~

= DON'T CARE
0337-4

Figure 4: Write Cycle Timing

AC ELECTRICAL CHARACTERISTICS v+ = + 5.0V, v- = -5.0V, TA = + 25°C, fclk= 500kHz unless
otherwise noted. Data derived from extensive characterization testing. Parameters are not 100% production tested.
Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

READ CYCLE TIMING
RD Low, Ao Valid
CS Low, RD Low
CS Low, Ao Valid

tcd

Prop. Delay CS to Data

tad

Prop. Delay Ao to Data

trd

Prop. Delay RD to Data

toe

Prop. Delay Data to Three State

100

ted

Prop. Delay EOC High to Data

200

200
200
200

ns

WRITE CYCLE TIMING
twr

W'RLowTime

twe

Prop. Delay WR Low to EOC Low

tao

EOC High Time

teonv

100
Wait Mode
Free-Run Mode

Conversion Time

ns

1

2

0.5

1.5

'SC=VIH

20

'SC=VIL

18

1lfclk

INTeRSIL'S SCLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE:AH/yp/coI_"" .. _ _ bulaIOnJ)/1M/fd.

3-64

ICL7115
TABLE 1: PIN DESCRIPTIONS
PIN NAME

PIN

NAME

1

VREFf

FORCE line for reference input.

FUNCTION

30

OSC1

Oscillator inverter input

2

AGNDt FORCE input for analog ground

31

OSC2

Oscillator inverter output

FUNCTION

3

CS

Chip Select enables reading and writing
(active low)

32

"SC

Short cycle input (high = 14-bit,
low = 12-bit operation)

4

RD

ReaD (active low)

33

WR

5

Ao

Byte select (low = Do - 07,
high = De - 013, OVR)

WRite pulse input (low starts new
conversion)

34

CAZ

Auto-zero capacitor connection

6

BUS

35

V-

36

COMP

7

Bus select (low = outputs enabled by Ao,
high = all outputs enabled together)

DGND Digital GrouND return

Negative power supply input
Used in test, tie to V-

37

VINs

38

VREFs

SENSE line for reference input

39

AGNDs

SENSE line for analog ground

40

VINf

FORCE line for input voltage

SENSE line for input voltage

8

013

Bit 13 (most significant)

9

012

Bit 12

10

011

Bit11

11

010

Bit 10

12

09

Bit 9

Output

13

De

Bit 8

Data

14

07

Bit 7

Bits

0

0

x

x

x

Initiates a Conversion

15

06

Bit 6

(High = True)

1

x

x

x

x

Disables all Chip Commands

16

05

Bit 5

0

x

0

0

0

Low Byte is Enabled

17

04

Bit 4

0

x

0

1

0

High Byte is Enabled

18

03

Bit 3

0

x

0

x

1

Low and High Bytes Enabled Together

x

x

1

x

x

Disables Outputs (High-Impedance)

19

High Byte

02

Bit 2

20

01

Bit 1

21

Do

Bit 0 (least significant)

22

B15

23

B16

24

B17

25

EOC

TABLE 2: 1/0 CONTROL
CS WR RD Ao BUS

Low Byte

FUNCTION

TABLE 3: TRANSFER FUNCTION
INPUT VOLTAGE
VREF= -5.0V

Used for programming only (leave open)

End Of Conversion flag (low = busy,
high = conversion complete)

26

OVR

OVerRange flag (valid at end of conversion
when output code exceeds full-scale, threestate output enabled with high byte)

27

V+

Positive power supply input

28

PROG Used for programming only. Tie to V+ for
normal operation

29

TEST

EXPECTED OUTPUT CODE
OVR MSB

LSB

0
+0.0003

0
0

0
0

000000000000
000000000000

0
1

+0.150

0

0

000011110101

1
1
0

+2.4997
+2.500

0
0

0
1

111111111111
000000000000

+4.9994
+4.9997
+5.000
+5.0003

0
0
1
1

1
1
0
0

111111111111
111111111111
000000000000
000000000000

0
1
0
1

+5.150

1

0

000011110101

1

Used for programming only. Tie to V+ for
normal operation

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATEO IN THE WARRANTY ARTIClE OF THE ODNDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPUED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typicsI values hBve besn charBcl6lized but MS not tHffId.

3-65

......... ICL7115
~

!::!

nates the effect of small voltage drops which can appear
between the input pin of the IC package and the actual resistor on the chip. If the small gauge wire and the bonds
that connect the chip to its package have more than 300mO
of total series resistance, the result can be a voltage error
equivalent to 1LSB. If no op-amps are used for VIN and
VREF, connections should be made directly to the SENSE
lines. The external op-amps also serve to transform the relatively low impedance at the VIN and VREF pins into a high
impedance. The input offset voltages of these amplifiers
should be kept low in order to maintain the overall A/D converter system accuracy.
When using A/D converters with more than 12 bits of
resolution, special attention must be paid to grounding and
the elimination of potential ground loops. A ground loop can
be formed by allowing the return current from the ICL7115's
DAC to flow through traces that are common to other analog circuitry. If care is not taken, this current can generate
small unwanted voltages that add to or detract from the
reference or input voltages of the AID converter.
Ground loops can be eliminated by the use of the analog
ground FORCE and SENSE lines provided on the ICL?11.5
as shown in Figures 5 and 6. In Figure 5 the FORCE line IS
the only point that is connected to system analog ground. In
Figure 6, the op-amp A3 forces the voltage at AGND to be
equal to analog system ground. The addition of this op-amp
overcomes the main deficiency of the arrangement in Figure 5: the VIN and VREF sources are not referenced to true
analog system ground.
The clamp diodes in Figure 6 are required because spurious op-amp output on AGNDf during power-on can exceed
the absolute max rating of ± 1.0V between AGDf and
DGND. The two inverse-parallel diodes clamp the voltage
between AGNDs and DGND to ±0.7V.

DETAILED DESCRIPTION

The ICL7115 is basically a successive approximation A/D
converter with an internal structure much more complex
than a standard SAR-type converter. Figure 2 shows the
functional diagram of the ICL7115 14-bit AID converter.
The additional circuitry incorporated into the ICL7115 is
used to perform error correction and to maintain the operating speed in the 40fA-s range.
The internal 17-bit DAC of the ICL7115 is designed
around a radix of 1.85 rather than the traditional 2.00. This
radix gives each bit of the DAC a weight of approximately
54% of the previous bit. The result is a useable range that
extends to 3% beyond the full-scale input of the AID. The
actual value of each bit is measured and stored in the onchip PROM. The absolute value of each bit weight then becomes relatively unimportant because of the error correction action of the ICL7115.
The output of the high-speed auto-zeroed comparator is
fed to the data input of a 17-bit successive approximation
register (SAR). This register is uniquely designed for the
ICL7115 in that it tests bit pairs instead of individual bits in
the manner of a standard SAR. At the beginning of the conversion cycle, the SAR turns on the MSB (B16) and the
MSB-4 bit (B12)' The sequence continues for each bit pair,
Bx and BX-4' until only the four LSBs remain. The sequence
concludes by testing the four LSBs individually.
The SAR output is fed to the DAC register and to the
preprogrammed 17-word by 17-bit PROM where it acts as
PROM address. PROM data is fed to a 17-bit full-adder/accumulator where the decoded results from each successive
phase of the conversion are summed with the previous results. After 20 clock cycles, the accumulator contains the
final binary data which is latched and sent to the three-state
output buffers. The accuracy of the AID converter depends
primarily upon the accuracy of the data that has been programmed into the PROM during the final test portion of the
manufacturing process.
The error correcting algorithm built into the ICL7115 reduces the initial accuracy requirements of the DAC. The
overlap in the testing of bit pairs reduces the accuracy requirements on the comparator which has been optimized for
speed. Since the comparator is auto-zeroed, no external adjustment is required to get ZERO code for ZERO input voltage.
Twenty clock cycles are required for the complete 14-bit
conversion. The auto-zero circuitry associated with the
comparator is employed during the last three clock cycles
of the conversion to cancel the effect of offset voltage. Also
during this time, the SAR and accumulator are reset in preparation for the start of the next conversion. When the Short
Cycle (SC) input is low, 18 clock cycles are required to complete a 12-bit conversion.
The overflow output of the 17-bit full-adder is also the
OVerRange (OVR) output of the ICL7115. Unlike standard
SAR-type AID converters, the ICL7115 has the capability of
providing valid useable data for inputs that exceed the fullscale range by as much as 3%.

INPUT WARNING
As with any CMOS integrated circuit, no input voltages
should be applied to the ICL7115 until the ± 5V power supplies have stabilized.

INTERFACING TO DIGITAL SYSTEMS
The ICL7115 provides three-state data output buffers,
CS, RD, WR, and bus select inputs (Ao and BUS) for interfacing to a wide variety of microcomputers and digital systems. The I/O Control Truth Table shows the functions of
the digital control lines. The BUS select and Ao lines are
provided to enable the output data onto either 8-bIt or 16-blt
data buses. A conversion is initiated by a WR pulse (pin 33)
when CS (pin 3) is low. Data is enabled on the bus when the
chip is selected and RD (pin 4) is low.
Figure 7 illustrates a typical interface to an 8-bit microcomputer. The "Start and Wait" operation requires the fewest external components and is initiated by a low level on
the WR input to the ICL7115 after the I/O or memorymapped address decoder has brought the CS input low. After executing a delay or utility routine for a period of time
greater than the conversion time of the ICL7115, the processor issues two consecutive bus addresses to read output
data into two bytes of memory. A low level on Ao enables
the LSBs and a high level enables the MSBs.

OPTIMIZING SYSTEM PERFORMANCE
The FORCE and SENSE inputs for VIN and VREF are also
shown driven by external op-amps. This technique elimi-

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: Ali typical values have been characterized but are not tested

3-66

ICL7115

' - - - - - - - I VINs

VREFf
ICL7115

.....- - - - - - 1 VREF•
'-------~AGNOs

...------IAGNDf
r---iOGNO
0337-5

Figure 5: VIN and VREF Input Buffers

> - - - - I VINf

' - - - - - - - - f VIN.

>----1 VREff
ICL7115

' - - - - - - - - 1 VREF•
r - - - - - - - I AGNDs

> .....~~-I AGNOf
L -.....--10GND

0337-6

Figure 6: Using a Forced Ground

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characteriz9d but are not tested

3-67

•

......
...

10

ICL7115

...

S:!
ADDRESS IUS

\

.... ....

Ao

I

Ao

""III

~

ADDRESS
DECODE

I

,

Ao-AN

~

RD

lim

WR

WR

.,

ICL7I15

IUS

n

OVR
Do-D7

,

~

Do-Of
~

DrD13

~""'Ii

"""
""'Ii!

"..

,

I

DATA BUS

0337-7

START
CONVERSION

WAlT

READ

READ

LOW BYTE

HIGH BYTE
0337-8

Figure 7: "Start and Walt" Operation

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOrc: AU typical values have beBn charsctsrized but BrfI not testsd.

3-68

IID~On.

ICL7115

a conversion time of 40/-Ls. Output data is controlled by the
BUS and Ao inputs. Here they are set for B-bit bus operation
with BUS grounded and Ao under the control of the address
decode section of the external system.
Because the ICL7115's internal accumulator generates
accurate output data for input signals as much as 3% greater than full-scale, and because the converter's OVR output
flags overrange inputs, a simple microprocessor routine can
be employed to precisely measure and correct for system
gain and offset errors. Figure 12 shows a typical data acquisition system that uses a 5.0V reference, input signal multiplexer, and input Signal Track/Hold amplifier. Two of the
multiplexer's input channels are dedicated to sampling the
system analog ground and reference voltage. Here, as in
Figure 11, bipolar operation is accommodated by an offset
resistor between the reference voltage and the summing
junction of A1. A flip-flop in IC3 sets IC2'S Track/Hold input
after the microprocessor has initiated a WR command, and
resets when EOC goes high at the end of the conversion.
The first step in the system calibration routine is to select
the multiplexer channel that is connected to system analog
ground and initiate a conversion cycle for the ICL7115. The
results represent the system offset error which comes from
the sum of the offsets from IC1, IC2, and A1. Next the channel connected to the reference voltage is selected and
measured. These results, minus the system offset error,
represent the system full-scale range. A gain error correction factor can be derived from this data. Since the ICL7115
provides valid data for inputs that exceed full-scale by as
much as 3%, the OVR output can be thought of as a valid
15th data bit. Whenever the OVR bit is high, however, the
total 14-bit result should be checked to insure that it falls
within 100% and 103% of full-scale. Data beyond 103% of
full-scale should be discarded.
The ICL7115 provides an internal inverter which is
brought out to pins OSC1 and OSC2, for crystal or ceramic
resonator oscillator operation. The clock frequency is calculated from:

By adding a three-state buffer and two control gates, the
End-of-Conversion (EOC) output can be used to control a
"Start and Poll" interface (Figure B). In this mode, the Ao
and CS lines connect the EOC output to the data bus al~
with the most significant byte of data. After pulsing the WR
line to initiate a conversion, the microprocessor continually
reads the most significant byte until it detects a high level
on the EOC bit. The "Start and Poll" interface increases
data throughput compared with the "Start and Wait" method by eliminating delays between the conversion termination and the microprocessor read operation.
Other interface configurations can be used to increase
data throughput without monopolizing the microprocessor
during waiting or polling operations by using the EOC line as
an interrupt generator as shown in Figure 9. After the conversion cycle is initiated, the microprocessor can continue
to execute routines that are independent of the AID converter until the converter's output register actually holds valid data. For fastest data throughput, the ICL7115 can be
connected directly to the data bus but controlled by way of
a Direct Memory Access (DMA) controller as shown in Figure 9.

APPLICATIONS
Figure 11 shows a typical application of the ICL7115 14bit AID converter. A bipolar input voltage range of + 5V to
- 5V is the result of using the current through R2 to force a
% scale offset on the input amplifier (A2). The output of A2
swings from OV to -5V. The overall gain of the AID is varied by adjusting the 100kn trim resistor, Rs. Since the
ICL7115 is automatically zeroed every conversion, the system gain and offset stability will be superb as long as a
reference with a tempco of 1ppml'C and stable external
resistors are used.
In Figure 11, note that the 0.22/-LF auto-zero capacitor is
connected directly between the CAZ. pin and analog ground
SENSE. A:l forces the analog ground of the ICL7115 to be
the zero reference for the input Signal. Its offset voltage is
not important in this example because the voltage to be
digitized is referred to the analog ground SENSE line rather
than system analog ground. It is important to note that Since
the 7115's DAC current flows in A1, A2 and A3 these amplifiers should be wideband (GBW> 20M Hz) types to minimize
errors.
The clock for the ICL7115 is taken from whatever system
clock is available and divided down to the 500kHz level for

.
fCLK = -20- f or 14-b·It operation
!cony

and
.
fCLK = -1B- f or 12-b·It operation
tconv

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valuss have been characterized but are not tested.

3-69

il
......
...

CII

•

......
......
10

ICL7115

S!

(A)

Wfi~------;-t----iWR

CS I+-------H
RD~------~+_--_iRD

ICL7115

~p

EOC
BUS

DATA BUS
0337-9

(8)
END OF

READ

POLL----+--

HIGHIYTE

READ

LOW BYTE
0337-10

Figure 8: "Start and Poll" Operation

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIeD OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR

use.

NOTE: All typical values hsve b6en characterized but are not tested.

3·70

.O~OIL

ICL7115

c;
I'"

.......
ell

Cs

R5

RD
WR

WR

ICL7115

j.£p

INT

•

0337-11

READ
LOWIYTE

CONVERSION

READ
HIGH BYTE
0337-12

Figure 9: Using EOC as an Interrupt

lNTERSIL'S SOLE AND EXCLUSIVE WAARANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARAANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

3-71

..... ICL7115
1ft

g

BUS

AO

WR

EOCI-------.IORO"

DMA

ICL711S

CONTROLLER

IUS

DATA IUS
0337-13

EOC

Ao
READ
LOW BYTE
ENDOF
CONVERSION

READ
HIGH BYTE

START
CONVERSION
0337-14

Figure 10: Data to Memory via DMA Controller

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have be6n characterized but are not test8d.

3-72

ICL7115
+5V

500 kHz
SYSTEM
CLOCK

OSC
5V
REFERENCE

EOC

.,,[

ICL7115
INPUT VOLTAGE
+5V TO -5V

OUT

WR

21
33

ifIj

CS
I{" DGND BUS

36

-5V

•

Ao

7

DIGITAL
GROUND

0337-15

Figure 11: Typical Application with Bipolar Input Range, Forced Ground, and 5 Volt Ultra-Stable Reference

Vee

r---t-----t-----1AD

t------t----i-t-~WR

ANALOGI
INPUTS

y.
74125

0337-16

Figure 12: Multi-Channel Data Acquisition System with Zero and Reference Lines Brought to Multiplexer for
System Gain and Offset Error Correction

tNTERStL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicB.1 values have bBBn characterized but arB not test6(/.

3-73

D~DIL

=:... ICL7135

C)_~

4%-Digit BCD Output
AID Converter

GENERAL DESCRIPTION

FEATURES

The Intersi! ICL7135 precision AID converter, with its
multiplexed BCD output and digit drivers, combines dual·
slope conversion reliability with ± 1 in 20,000 count accura·
cy and is ideally suited for the visual display DVM/DPM
market. The 2.0000V full scale capability, auto·zero and
auto·polarity are combined with true ratio metric operation,
al most ideal differential linearity and true differential input.
All necessary active devices are contained on a single
CMOS I.C., with the exception of display drivers, reference,
and a clock.
The intersil ICL7135 brings together an unprecedented
combination of high accuracy, versatility, and true economy.
It features auto·zero to less than 10,..V, zero drift of less
than 1,..VrC, input bias current of 10 pA max., and rollover
error of less than one count. The versatility of multiplexed
BCD outputs is increased by the addition of several pins
which allow it to operate in more sophisticated systems.
These include STROBE, OVERRANGE, UNDER· RANGE,
RUN/HOLD and BUSY lines, making it possible to interface
the circuit to a microprocessor or UART.

• Accuracy Guaranteed to ± 1 Count Over Entire
± 20,000 Counts (2.0000 Volts Full Scale)
• Guaranteed Zero Reading for 0 Volts Input
• 1pA Typical Input Current
• True Differential Input
• True Polarity at Zero Count for Precise Null
Detection
• Single Reference Voltage Required
• Over-Range and Under-Range Signals Available for
Auto-Range Capability
• All Outputs TTL Compatible
• Blinking Outputs Gives Visual Indication of Overrange
• Six Auxiliary Inputs/Outputs Are Available for
Interfacing to UARTs, Microprocessors or Other
Circuitry
• Multiplexed BCD Outputs

ORDERING INFORMATION
Part Number

Temp. Range

Package

ICL7135CJI

O·Cto +70·C

28·Pin CERDIP

ICL7135CPI

O·Cto +70·C

2B·Pin Plastic DIP

Evaluation Kit
ICL7135EV/KIT
(PC Board, active, passive components)

GND
ANALOGO~~~~~~~~

ANODE
DRIVER
TRANSISTORS
SIGNAL

INPUT

SEVEN
BEG.

DECODE

0342-1

Figure 1: ICL7135 Connection Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTlCLE OF THE OONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typical VSIU8S hsVB been ohatscterized but srtI not fBSt«J.

3·74

ICL7135
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Note 2)
Ceramic Package .......................... 1000mW
Plastic Package ............................. 800mW
Operating Temperature ................... O'C to + 70'C
Storage Temperature ................ - 65'C to + 150'C
Lead Temperature (Soldering, 10sec) ............. 300'C

SupplyVoltageV+ .............................. +6V
v- .............................. -9V
Analog Input Voltage (either input) (Note 1) ..... V+ to VReference Input Voltage (either input) ......... V+ to VClock Input ................................ Gnd to V+
Nole I:

Input voltages may exceed the supply voltages provided the input current is limijed to

+ 100"A.

Note 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress rafings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum. rating conditions for extended periods may affect device reliability.

Y-

UNDERRANGE
OYE_GE

REFERENCE

STROBE

ANALOG COMMON
INTOUT
AZIN

•

Rlit
24 DIGITAL GND
POL

BUFF OUT

iiEF."cAP7-'
REF. CAP. +

INLO

INKI
y+
(MSD)DS
(LSI)S1

B2

-------

0342-2

Figure 2: Pin Configuration
Outline dwgs JI, PI)

ELECTRICAL CHARACTERISTICS

(Note 1)
(V+ = +5V, V- = -5V, TA=25'C, Clock Frequency Set for 3 Reading/Sec)
Symbol

Test Conditions

Min

Typ

Max

Unit

Zero Input Reading

VIN=O.OV
Full Scale = 2.000V

-0.0000

±O.OOOO

+0.0000

Digital
Reading

Ratiometric Reading (2)

VIN '" VREF
Full Scale=2.000V

+0.9998

+0.9999

+ 1.0000

Digital
Reading

-2V"VIN,,+2V

0.5

1

+ 2V

.01

Characteristics

ANALOG (Note 1) (Note 2)

Linearity over ± Full Scale
(error of reading from
best straight line)
Differential Linearity
(difference between worse
case step of adjacent counts
and ideal step)
Rollover error (Difference in
reading for equal positive &
negative voltage near full scale)

-2V"VIN"

-VIN'" +VIN :::: 2V

0.5

Digital
Count
Error
LSB

1

Digital
Count
Error

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not testsd.

3-75

.....=: ICL7135
~

S:!

ELECTRICAL CHARACTERISTICS

(Note 1)
(V+ = +5V, V- = -5V, TA = 25'C, Clock Frequency Settor 3 Reading/Sec) (Continued)
Symbol

Characteristics

en

Noise (P-P value not
exceeded 95% of time)

IILK

Leakage Current at Input
Zero Reading Drift

TC

Scale Factor Temperature
Coefficient (3)

Test Conditions

Min

Typ

Max

Unit

VIN=OV
Full scale = 2.000V

15

VIN=OV

1

10

pA

VIN=OV
0':0: TA:O: 70'C

0.5

2

p,VI'C

2

5

ppml'C

2.2
1.6
0.02
0.1

0.8
0.1
10

VIN= +2V
O:O:TA:O:70'C
(ext. ref. 0 ppml'C)

p,V

DIGITAL
INPUTS
VINH
VINL
IINL
IINH

2.8
Clock in, Run/Hold, See Figure 4

VIN=O
VIN= +5V

V
mA
p,A

OUTPUTS
VOL
VOH
VOH

All Outputs
Bl, B2, B4, Ba
Dl, D2, D3, D4, D5
BUSY, STROBE,
OVER-RANGE, UNDER-RANGE
POLARITY

IOL =1.6mA
IOH= -lmA

2.4

0.25
4.2

IOH= -10p,A

4.9

4.99

+4

+5

0.40

V
V
V

SUPPLY
V+

+ 5V Supply Range

V-

- 5V Supply Range

1+

+ 5V Supply Current

1CPD

- 5V Supply Current
Power Dissipation Capacitance

-3

+6

V

-5

-8

V

fc=O

1.1

3.0

mA

fc=O

0.8

3.0

vs. Clock Freq

40

pF

CLOCK
Clock Freq. (Note 4)

DC

2000

1200

kHz

NOTES: 1. Tested in 4-% digit (20,000 count) circuit shown in Figure 3, clock frequency 120kHz.
2. Tested with a low dielectric absorption integrating capacitor and RINT = O. See Component Selection Section.
3. The temperature range can be extended to + 700 e and beyond as long as the auto~zero and reference capacitors are increased to absorb the higher
leakage of the ICL7135.
4. This specification relates to the clock frequency range over which the ICL7135 will correctly perform its various functions. See "Max
Clock Frequency" section for limitations on the clock frequency range in a system.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE All typical values have been characterized but are not tested

3-76

ICL7135
y+

CLOCK
IN
120kHz

' - - - 6 - - - 0 I G GND

0342-4

Figure 4: 7135 Digital Logic Input
0342-3

Figure 3: 7135 Test Circuit

•

Coe'
CREF+

r--I

REF HI
8

-------2

AUTO

eRe.

BUFFER
-----7

~£.:...--

I

I
I
I
I
I
I
I

INPUT
HIGH

I

INHI ~~~D(~~-+----~---4--------~--~{x1------------4--~----C~OMPARATOR

Z-I
INPUT
LOW

INLO $-~~>C~--~---------------------------------------J
L _________________

~~---------------------------0342-5

Figure 5: Analog Section of ICL7135

INTERSIL'9 SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

3-77

=: ICL7135

...
......

!:!

DETAILED DESCRIPTION
Analog Section

DE·INTEGRATE PHASE
The Third phase is de-integrate, or reference integrate.
Input LOW is internally connected to analog COMMON and
input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the
capacitor will be connected with the correct polarity to
cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the
input signal. Specifically the digital reading displayed is

Figure 5 shows the Block Diagram of the Analog Section
for the ICL7135. Each measurement cycle is divided into
four phases. They are (1) auto-zero (A-Z), (2) signal-integrate (I NT), (3) deintegrate (DE) and (4) zero-integrator (ZI).

AUTO·ZERO PHASE
During auto-zero three things happen. First, input high
and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Third, a feedback loop is
closed around the system to charge the auto-zero capacitor
CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the
noise of the system. In any case, the offset referred to the
input is less than 1O)J-V.

10,000

(V~~F)'

ZERO INTEGRATOR PHASE
The final phase is zero integrator. First, input low is shorted to analog COMMON. Second, a feedback loop is closed
around the system to input high to cause the integrator output to return to zero. Under normal condition, this phase
lasts from 100 to 200 clock pulses, but after an overrange
conversion, it is extended to 6200 clock pulses.

SIGNAL INTEGRATE PHASE

Differential Input

During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and
low are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a
wide common mode range; within one volt of either supply.
If, on the other hand, the input signal has no return with
respect to the converter power supply, IN LO can be tied to
analog COMMON to establish the correct common-mode
voltage. At the end of this phase, the polarity of the integrated signal is latched into the polarity F/F.

The input can accept differential voltages anywhere within the common mode range of the input amplifier; or specifically from 0.5 volts below the positive supply to 1.0 volt
above the negative supply. In this range the system has a
CMRR of 86 dB typical. However, since the integrator also
swings with the common mode voltage, care must be exercised to assure the integrator output does not saturate. A
worst case condition would be a large positive commonmode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator
positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the
recommended 4V full scale swing with some loss of accuracy. The integrator output can swing within 0.3 volts of either
supply without loss of linearity.

I

y+

y+

I

6.8 VOLT
ZENER

REFHIf-

~~

G.akO

y+

-

7135

COMMON 1--'-

j Iz

20

REF HI

~ ~~. ICLB069

1.2V
REFERENCE

7135

COMMON~--~---.

,!.

0342-6

0342-7

(a)

(b)

Figure 6: Using an External Reference

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not testsd.

3-78

.D~DIl.

ICL7135

auto-zero when not BUSY, so it may also be considered a
(ZI + AZ) signal. A very simple means for transmitting the
data down a single wire pair from a remote location would
be to AND BUSY with clock and subtract 10,001 counts
from the number of pulses received - as mentioned previously there is one "NO-count" pulse in each reference integrate cycle.

Analog Common
Analog COMMON is used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system
and is taken care of by the excellent CMRR of the converter. However, in most applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
pOint, thus removing the common mode voltage from the
converter. The reference voltage is referenced to analog
COMMON.

Reference
The reference input must be generated as a positive voltage with respect to COMMON, as shown in Figure 6.

DETAILED DESCRIPTION
Digital Section
Figure 7 shows the Digital Section of the 7135. The 7135
includes several pins which allow it to operate conveniently
in more sophisticated systems. These include:
Run/HOLD (Pin 25). When high (or open) the AID will freerun with equally spaced measurement cycles every 40,002
clock pulses. It taken low, the converter will continue the full
measurement cycle that it is doing and then hold this reading as long as RIA is held low. A short positive pulse (greater than 300ns) will now initiate a new measurement cycle,
beginning with between 1 and 10,001 counts of auto zero. If
the pulse occurs before the full measurement cycle (40,002
counts) is completed, it will not be recognized and the converter will simply complete the measurement it is doing. An
external indication that a full measurement cycle has been
completed is that the first strobe pulse (see below) will occur 101 counts after the end of this cycle. Thus, if Runl
HOLD is low and has been low for at least 101 counts, the
converter is holding and ready to start a new measurement
when pulsed high.
STROBE (Pin 26). This is a negative going output pulse that
aids in transferring the BCD data to external latches,
UARTs or microprocessors. There are 5 negative going
STROBE pulses that occur in the center of each of the digit
drive pulses and occur once and only once for each mea·
surement cycle starting 101 pulses after the end of the full
measurement cycle. Digit 5 (MSD) goes high at the end of
the measurement cycle and stays on for 201 counts. In the
center of this digit pulse (to avoid race conditions between
changing BCD and digit drives) the first STROBE pulse
goes negative for % clock pulse width. Similarly, after digit
5, digit 4 greS high (for 200 clock pulses) and 100 pulses
later the S ROBE goes negative for the second time. This
continues through digit 1 (LSD) when the fifth and last
STROBE pulse is sent. The digit drive will continue to scan
(unless the previous signal was overrange) but no additional
STROBE pulses will be sent until a new measurement is
available.
BUSY (Pin 21). BUSY goes high at the beginning of signal
integrate and stays high until the first clock pulse after zerocrossing (or after end of measurement in the case of an
overrange). The internal latches are enabled (i.e., loaded)
during the first clock pulse after busy and are latched at the
end of this clock pulse. The circuit automatically reverts to

0342-8

Figure 7: Digital Section of the 7135
OVER-RANGE (Pin 27). This pin goes positive when the
input signal exceeds the range (20,000) of the converter.
The output FIF is set at the end of BUSY and is reset to
zero at the beginning of Reference integrate in the next
measurement cycle.
UNDER-RANGE (Pin 28). This pin goes positive when the
reading is 9% of range or less. The output F IF is set at the
end of BUSY (if the new reading is 1800 or less) and is
reset at the beginning of Signal integrate of the next reading.
POLARITY (Pin 23). This pin is positive for a positive input
signal. It is valid even for a zero reading. In other words,
+ 0000 means the signal is positive but less than the least
significant bit. The converter can be used as a null detector
by forCing equal frequency of (+) and (-) readings. The
null at this point should be less than 0.1 LSB. This output
becomes valid at the beginning of reference integrate and
remains correct until it is re·validated for the next measurement.
Digit Drives (Pins 12, 17, 18, 19 and 20). Each digit drive is
a positive going signal that lasts for 200 clock pulses. The
scan sequence is Ds (MSD), D4, Ds, D2 and D1 (LSD). All
five digits are scanned and this scan is continuous unless
an over-range occurs. Then all digit drives are blanked from
the end of the strobe sequence until the beginning of Reference Integrate when D5 will start the scan again. This can
give a blinking display as a visual indication of over-range.
BCD (Pins 13, 14, 15 and 16). The Binary coded Decimal
bits B8, B4, B2 and B1 are positive logic Signals that go on
simultaneously with the digit driver signal.

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANlY ARTICLE OF THE OONDITION OF SALE.
THE WARRANlY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILIlY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typicsl va/uss have besn chsract8rfz6d but are not testsd.

3-79

P

.....

W
CII

: ICL7135

......

2 COMPONENT VALUE SELECTION
For optimum performance of the analog section, care
must be taken in the selection of values for the integrator
capacitor and resistor, auto-zero capacitor, reference voltage, and conversion rate. These values must be chosen to
suit the particular application.

INTEGRATOR

OUTP\IT

WT~-I SImf'L~
10,GOOl

~

10JAY,

COUNTS COU

Integrating Resistor

AEFEAENCU
INTEGRATE

COU=~AX.

FULL MEASUAEMENT CYCLE

OO,Q02COUNTS

The integrating resistor is determined by the full scale input voltage and the output current of the buffer used to
charge the integrator capacitor. Both the buffer amplifier
and the integrator have a class A output stage with 100,..A
of quiescent current. They can supply 20,..A of drive current
with negligible non-linearity. Values of 5 to 40,..A give good
results, with a nominal of 20,..A, and the exact value of integrating resistor may be chosen by
R
_ full scale voltage
INT20,..A

8USY--.J

WH~N~~~:~iIIII~~~~~
I EXPA:~~g:CALE

FOAo~~~~12~~~D'
~D.

~D3

Integrating Capacitor

---IL-.l1...-.. D,
-J"l...-Il-D,

The product of integrating resistor and capacitor should
be selected to give the maximum voltage swing which ensures that the tolerance built-up will not saturate the integrator swing (approx. 0.3 volt from either supply). For ± 5 volt
supplies and analog COMMON tied to supply ground, a
± 3.5 to ± 4 volt full scale integrator swing is fine, and
0.47,..F is nominal. In general, the value of CINT is given by

fcb~~sI

*FIRST Os OF AZ AND
REF .NT ONE COUNT LONGER

mmRiilli

r.-

AUTO ZERO

DIGIT SCAN· 0
FOR OYEA.AANGE

SIGNAL INTEGRATE

n=-,---------1.
J1:0.~

C =( [1 0,000 X clock period] XIINT )
INT integrator output voltage swing
(10,000) (clock period) (20,..A)
integrator output voltage swing
A very important characteristic of the integrating capacitor is that it has low dielectric absorption to prevent roll-over
or ratio metric errors. A good test for dielectric absorption is
to use the capacitor with the input tied to the reference.
This ratiometric condition should read half scale 0.9999,
and any deviation is probably due to dielectric absorption.
Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors
may also be used in less critical applications.

___~.~_~~

0342-9

Figure 8: Timing Diagram for Outputs

Auto-Zero and Reference Capacitor
The size of the auto-zero capacitor has some influence
on the noise of the system, a large capacitor giving less
noise. The reference capacitor should be large enough
such that stray capacitance to ground from its nodes is negligible.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIeD WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested,

3-80

IID~Dn.

ICL7135

To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz,
40kHz, 33%kHz, etc. should be selected. For 50Hz rejection, oscillator frequencies of 250kHz. 166%kHz, 125kHz.
100kHz, etc. would be suitable. Note that 100kHz (2.5 readings/second) will reject both 50 and 60Hz.
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators are
shown in the Applications section. The multiplexed output
means that if the display takes significant current from the
logic supply, the clock should have good PSRR.

The dielectric absorption of the reference cap and autozero cap are only important at power-on or when the circuit
is recovering from an overload. Thus, smaller or cheaper
caps can be used here if accurate readings are not required
for the first few seconds of recovery.

Reference Voltage
The analog input required to generate a full-scale output
is VIN=2 VREF·
The stability of the reference voltage is a major factor in
the overall absolute accuracy of the converter. For this reason, it is recommended that a high quality reference be
used where high-accuracy absolute measurements are being made.

p

....
Cot

CII

Zero-Crossing Flip-Flop
The flip-flop interrogates the data once every clock pulse
aiter the transients of the previous clock pulse and halfclock pulse have died down. False zero-crossings caused
by clock pulses are not recognized. Of course, the flip-flop
delays the true zero-crossing by up to one count in every
instance, and if a correction were not made, the display
would always be one count too high. Therefore, the counter
is disabled for one clOCk pulse at the beginning of phase 3.
This one-count delay compensates for the delay of the
zero-crOSSing flip-flop, and allows the correct number to be
latched into the display. Similarly, a one-count delay at the
beginning of phase 1 gives an overload display of 0000 instead of 0001. No delay occurs during phase 2, so that true
ratiometric readings result.

Rollover Resistor and Diode
A small rollover error occurs in the 7135, but this can be
easily corrected by adding a diode and resistor in series
between the INTegrator OUTput and analog COMMON or
ground. The value shown in the schematics is optimum for
the recommended conditions, but if integrator swing or
clock frequency is modified, adjustment may be needed.
The diode can be any silicon diode, such as 1N914. These
components can be eliminated if rollover error is not important, and may be altered in value to correct other (small)
sources of rollover as needed.

Max Clock Frequency
The maximum conversion rate of most dual-slope AID
converters is limited by the frequency response of the comparator. The comparator in this circuit follows the integrator
ramp with a 3,..s delay, and at a clock frequency of 160kHz
(6,..s period) half of the first reference integrate clock period
is lost in delay. This means that the meter reading will
change from 0 to 1 with a 50,..V input, 1 to 2 with 150,..V, 2
to 3 at 250,..V, etc. This transition at mid-point is considered
desirable by most users; however, if the clock frequency is
increased appreciably above 160kHz, the instrument will
flash "1" on noise peaks even when the input is shorted.
For many-dedicated applications where the input signal is
always of one polarity, the delay of the comparator need not
be a limitation. Since the non-linearity and noise do not increase substantially with frequency, clock rates of up to
- 1MHz may be used. For a fixed clock frequency, the extra
count or counts caused by comparator delay will be constant and can be subtracted out digitally.
The clock frequency may be extended above 160kHz
without this error, however, by using a low value resistor in
series with the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase.
By careful selection of the ratio between this resistor and
the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be compensated
and the maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second order breaks will cause significant nonlinearities in the
first few counts of the instrument - see Application Note
A017.
The minimum clock frequency is established by leakage
on the auto-zero and reference caps. With most devices,
measurement cycles as long as 10 seconds give no measurable leakage error.

EVALUATING THE ERROR SOURCES
Errors from the "ideal" cycle are caused by:
1.
Capacitor droop due to leakage.
2.
Capacitor voltage change due to charge "suck-out"
(the reverse of charge injection) when the switches
turn off.
3.
Non-linearity of buffer and integrator.
4.
High-frequency limitations of buffer, integrator and
comparator.
5.
Integrating capacitor non-linearity (dielectric absorption.)
6.
Charge lost by CREF in charging Cstray.
7.
Charge lost by CAZ and CINT to charge Cstray.
Each of these errors is analyzed for its error contribution
to the converter in application notes listed on the back
page, specifically A017 and A032.

NOISE
The peak-to-peak noise around zero is approximately
15,..V (pk-to-pk value not exceeded 95% of the time). Near
full scale, this value increases to approximately 30,..V. Much
of the noise originates in the auto-zero loop, and is proportional to the ratio of the input signal to the reference.

ANALOG AND DIGITAL GROUNDS
Extreme care must be taken to avoid ground loops in the
layout of ICL7135 circuits, especially in high-sensitivity circuits. It is most important that return currents from digital
loads are not fed into the analog ground line.

INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are not test6d.

3-81

•

.

=: ICL7135

......

2

A suitable circuit for driving a plasma-type display is
shown in Figure 10. The high voltage anode driver buffer is
made by Dionics. The 3 AND gates and caps driving 'BI' are
needed for interdigit blanking of multiple-digit display elements, and can be omitted if not needed. The 2.5k!l & 3k!l
resistors set the current levels in the display. A similar arrangement can be used with Nixie® tubes.
The popular LCD displays can be interfaced to the OIP of
the ICL7135 with suitable display drivers, such as the
ICM7211 A as shown in Figure 11. A standard CMOS 4030
QUAD XOR gate is used for displaying the % digit, the polarity, and an 'overrange' flag. A similar circuit can be used
with the ICL7212A LED driver and the ICM7235A vacuum
fluorescent driver with appropriate arrangements made for
the 'extra' outputs. Of course, another full driver circuit
could be ganged to the one shown if required. This would
be useful if additional annunciators were needed. The Figure shows the complete circuit for a 4-% digit (± 2,000V)
AID.
Figure 12 shows a more complicated circuit for driving
LCD displays. Here the data is latched into the ICM7211 by
the STROBE signal and 'Overrange' is indicated by blanking
the 4 full digits.

POWER SUPPLIES
The 7135 is designed to work from ±5V supplies. However, in selected applications no negative supply is required.
The conditions to use a single + 5V supply are:
1. The input signal can be referenced to the center of the
common mode range of the converter.
2. The signal is less than ± 1.5 volts.
See "differential input" for a discussion of the effects this
will have on the integrator swing without loss of linearity.

TYPICAL APPLICATIONS
The circuits which follow show some of the wide variety of
possibilities, and serve to illustrate the exceptional versatility of this AID converter.
Figure 9 shows the complete circuit for a 4-% digit
(±2.000V) full scale) AID with LED readout using the
ICLB069 as a 1.2V temperature compensated voltage reference. It uses the band-gap principal to achieve excellent
stability and low noise at reverse currents down to 50fLA.
The circuit also shows a typical R-C input filter. Depending
on the application, the time-constant of this filter can be
made faster, slower, or the filter deleted completely. The %
digit LED is driven from the 7 segment decoder, with a zero
reading blanked by connecting a D5 signal to RBI input of
the decoder. The 2-gate clock circuit should use CMOS
gates to maintain good power supply rejection.

=""'t::T't-;-=:-t'-:-:--------o.av
I~

•b
t:=~:::~:

'---"""--it

81
12
14

•

;=

-=.'::.*'lIon on see" faclor ac:Ijwt. 101". 10 tum pol or a small pot In ..rie. with.
0342-10

Figure 9: 4-112 Digit AID Converter with a Multiplexed Common Anode LED Display

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPlIEO OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characteriz8d but are not tested.

3-82

ICL7135

C::....
r----j~::Jr>:-pJfl_:;JEl/IB 0 0

4-112 OIGIT LCO OISPLAY

"""'"

~

S~HI V~LTAGE

V+F:

I

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9 RBO
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47K

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......} - 4 - - - - - '

1.02

2.SK

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7409

88

ICL7135

Bl

t-:=.r±:l.i-"J-I-Cl
REF
...
lCiiii....
"r=;;;;;;==:;-i.' ANALOG

~~ALDi'~ =i!

COMMOM

-::-GND
'DDKO

~~'DUT

'~_~=i'NTOUT
1.0pF :

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288'

L

L-----------------+~-~-_~-j--+----~'7ID

TTl T

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3SV
OV

2,3.4

t-

8·'8
37-4D~

OPTIOIIAL
CAPACITOR

OSCl8

V·,

--4t---+5V
"-'DOoF

·5V

0342-14

Figure 12: Driving LCD Displays

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3-83

•

: ICL7135

....

...
....

S!

A problem sometimes encountered with both LED & plasma-type display driving is that of clock source supply line
variations. Since the supply is shared with the display, any
variation in voltage due to the display reading may cause
clock supply voltage modulation. When in overrange the
display alternates between a blank display and the 0000
overrange indication. This shift occurs during the reference
integrate phase of conversion causing a low display reading
just after overrange recovery. Both of the above circuits
have considerable current flowing in the digital supply from
drivers, etc. A clock source using an LM311 voltage comparator with positive feedback (Figure 13) could minimize
any clock frequency shift problem.
The 7135 is designed to work from ± 5 volt supplies.
However, if a negative supply is not available, it can be generated with an ICL7660 and two capacitors (Figure 14).

,......-----
20Kll

AD7521SD

~

r'1

1

1:r'1 =-

_0

~

Ioun

~

.~a

0

louTt
RF£EDBACK

0330-1

(Switches shown for Digital Inputs "High")
(Resistor values are nominal)
Figure 1: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
300105-003
NOTE: All typIcs/ values havs bes" characterized but IU6 not t88t9d.

4-1

~...

CII

...
...ICII
CII
...
to)

~
Co»

•

c; AD7520/AD7530
~ AD7521/AD7531

!.

(II

10

....
~
o
(II)

10

....

ABSOLUTE MAXIMUM RATINGS

(TA=25'C unless otherwise noted)
Supply Voltage (V +) ............................ + 17V
Operating Temperature
VREF ......................................... ± 25V
IN, KN, LN Versions ................... O'C to + 70'C
Digital Input Voltage Range ................. V+ to GND
JD, KD, LD Versions .................. -25'C to 85'C
Output Voltage Compliance ............. -100mVto V+
SD, TD, UDVersions ............... -55'C to +125'C
Power Dissipation (package)
Storage Temperature .................. -65'C to 150'C
up to + 75'C ............................... 450mW
Lead Temperature (Soldering, 10sec) ............. 300'C
derate above + 75'C @ . . . . . . . . . . . . . . . . . . . . . 6mWI'C
CAUTION:

!o

1) The digital control inputs afe zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep
unused units in conductive foam at all times.

....10
~

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of /he device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

(II

2) Do not apply voltages higher than Voo or less than GND potential on any terminal except VREF and RFEEOBACK·

TOP YIEW

AD7521 (AD7531)

AD7520 (AD7530)
IOUT1

16 RFEEOBACK

IOUT2

YREF

GND

y+

IOUT1

RFEEOBACK

IOUT2

YREF

GND

y+

BIT 1 (MSB)

BIT 12 (LSB)

BIT 10 (LSB)

BIT 2

BIT 11

BIT 2

BIT 9

BIT 3

BIT 10

BIT 3

BIT 8

BIT 4

BIT 9

BIT 4
BIT 7
BIT 5 --._ _ _....._ BIT 6

BIT 5

BIT 8

BIT 1 (MSB)

BIT 8 '"""1...._ _J'= BIT 7
0330-3

0330-2

Figure 2: Pin Configurations

ELECTRICAL CHARACTERISTICS
Parameter

(V+ = + 15V, VREF= + 10V, TA =25'C unless otherwise specified)
AD7520
(AD7530)

Test Conditions

I

AD7521
(AD7531)

Unit

Limit

DC ACCURACY (Note 1)
Resolution

10

Nonlinearity
(Note 2)
VERSION

12

Bits

0.2 (8-Bit)

% ofFSR

Max

K
T

Fig. 3

0.1 (9-Bit)

%ofFSR

Max

L -10V,;;VREF';; + 10V
U

Fig. 3

0.05 (1 O-Bit)

%ofFSR

Max

-

Nonlinearity Tempco
(Notes 2 and 3)
Gain Error (Note 2)

I

J S, T, U: over - 55'C to + 125'C Fig. 3
S

2
-10V,;;VREF,;;+10V

0.3

Gain Error Tempco
(Notes 2 and 3)

10

ppm of FSRI'C Max
%ofFSR

Typ

ppm of FSRI'C Max

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values haVl1 biNln character/zoo but are not tested.

4-2

IfIO~On.. ~

AD7 520/AD7 530
AD7 521/AD7 531

...en

N

ELECTRICAL CHARACTERISTICS

io

(V + = + 15V. VREF = + 10V. TA = 25'C unless otherwise specified)

...en

(Continued)
Parameter

AD7520
(AD7530)

Power Supply Rejection (Note 2)

AD7521
(AD7531)

Co)

Limit

o

200
(300)

nA

Max

...en~

Fig. 4

±0.005

% of FSR/%

Typ

Fig. 8

500

ns

Typ

Over the specified temperature
range

Output Leakage Current
(either output)

I

Unit

Test Conditions

..
...
..
N

~

AC ACCURACY (Note 3)
Output Current Settling Time

To 0.05% of FSR (All digital
inputs low to high and high to
low)
VREF=20V PP. 100kHz
(50kHz) All digital inputs low

Feedthrough Error

Fig. 7

All digital inputs high
IOUT1 at ground.

10

mVpp

Max

5k
10k
20k

0

Min
Typ
Max

ANALOG OUTPUT
Voltage Compliance (both outputs)

(Note 3)

Output Capacitance
(Note 3)

IOUT1
IOUT2

All digital inputs high

Fig. 6

See absolute max. ratings
120
37

pF
pF

Typ
Typ

IOUT1
IOUT2

All digital inputs low

Fig. 6

37
120

pF
pF

Typ
Typ

Output Noise (both outputs)
(Note 3)

Fig. 5

Equivalent to 10kO
Johnson noise

Typ

DIGITAL INPUTS
Low State Threshold

Over the specified temp range

High State Threshold
Input Current (low to high state)
Input Coding

See Tables 1 & 2

0.8

V

Max

2.4

V

Min

1

",A

Typ

Binary/Offset Binary

POWER REQUIREMENTS
Power Supply Voltage Range

1+

+5to +15

V

All digital inputs at OV or V +

1

",A

Typ

All digital inputs high or low

2

mA

Max

20

mW

Typ

Total Power Dissipation
(Including the ladder network)
NOTES: 1.

Full scale range (FSR) is 10V for unipolar and ± 10V for bipolar modes.
2. Using internal feedback resistor, RFEEDBACK.
3. Guaranteed by design, not subiect to test.
4. Accuracy not guaranteed unless outputs at GND potential.

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

4-3

en
Co)

REFERENCE INPUT
Input Resistance

CI

;; AD7520/AD7530
~ AD7 521/AD7 531

!...
N

II)

....
~

TEST CIRCUITS NOTE: The following test circuits
apply for the AD7520. Similar circuits are used for the
AD7530, AD7521 and AD7531 .

He

--_.....

BIT 1 (MS8) 15

h--~'

oC')

,.15

,.

'4

Ne

II)

....

100 mV,.,
1MHz

!o

0330-7

Figure 6: Output Capacitance

N

II)

....

.::II

C

VAEF

=

20V

p.p 100 kHz SINE WAVE

+1SV

BIT 1 (MSB)

81T11

BIT 12

0330-4

BIT 10 (LSB)

Figure 3: Nonlinearity

0330-8

Figure 7: Feedthrough Error

+15V
..10 V

,!~IUU1
DIGITAL INPUT

"VA",',-'_ _,

st: 1% SETTLlNQ (1 mY)
81: 0.03% SETTLING
t=rIA lime

,

i
0330-9

0330-5

Figure 8: Output Current Settling Time

Figure 4: Power Supply Rejection

DEFINITION OF TERMS

.;.l1Y (ADJUST FOR Vour = OV)

NONLINEARITY: Error contributed by deviation of the DAC

+15Y

transfer function from a best straight line function. Normally
expressed as a percentage of full scale range. For a multiplying DAC, this should hold true over the entire VREF
range.
RESOLUTION: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2- n) (VREF). A
bipolar converter of n bits has a resolution of [2 - (n -1 l]
[VREF]. Resolution in no way implies linearity.
SETTLING TIME: Time required for the output function of
the DAC to settle to within % LSB for a given digital input
stimulus, i.e., 0 to Full Scale.
GAIN: Ratio of the DAC's operational amplifier output voltage to the nominal input voltage value.
FEEDTHROUGH ERROR: Error caused by capacitive coupling from VREF to output with all switches OFF.

0330-6

Figure 5: Noise

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOT£: All typical values have been characterized but arB not tested.

4-4

AD7 520/ AD7 530
AD7521/AD7531
OUTPUT CAPACITANCE: Capacitance from IOUT1 and
IOUT2 terminals to ground.
OUTPUT LEAKAGE CURRENT: Current which appears on
IOUT1 terminal with all digital inputs LOW or on IOUT2 terminal when all inputs are HIGH.

~---~r-~---~---r--

DETAILED DESCRIPTION
The AD7520 (AD7530) and AD7521 (AD7531) are monolithic, multiplying DI A converters. A highly stable thin film R2R resistor ladder network and NMOS SPDT switches form
the basis of the converter circuit, CMOS level shifters permit
low power TTLICMOS compatible operation. An external
voltage or current reference and an operational amplifier
are all that is required for most voltage output applications.
A simplified equivalent circuit of the DAC is shown in Figure 9. The NMOS SPDT switches steer the ladder leg currents between IOUT1 and IOUT2 buses which must be held
either at ground potential. This configuration maintains a
constant current in each ladder leg independent of the input
code.

DTLlTTUCMOS
INPUT

0330-11

Figure 10: CMOS Switch

+15V
VREF - - - - ,

BIT 1 (MU)
10Kn

10Kn

10lUl

10KU

DIGITAL

(15117)

INPUT

15

1
:

~1Oi:w~13~;....J
BIT 10 (LSS)

Your

GND

"'"

PIT: '-t--.....-

...........- -......- ........---o:~~~

::

0330-12

Figure 11: Unipolar Binary Operation
(2-Quadrant Multiplication)

RFEEoaACK

(18/11)

TABLE 1
CODE TABLE - UNIPOLAR BINARY OPERATION

0330-10
(Switches shown for Digital Inputs ""High"")

Figure 9: 752017521 Functional Diagram

Digital Input

Analog Output

Converter errors are further reduced by using separate
metal interconnections between the major bits and the outputs. Use of high threshold switches reduces the offset
(leakage) errors to a negligible level.
The level shifter circuits are comprised of three inverters
with a positive feedback from the output of the second to
the first, (Figure 10). This configuration results in TTL!
CMOS compatible operation over the full military temperature range. With the ladder SPDT switches driven by the
level shifter, each switch is binarily weighted for an ON resistance proportional to the respective ladder leg current.
This assures a constant voltage drop across each switch,
creating equipotential terminations for the 2R ladder resistors and highly accurate leg currents.

1111111111

-VREF (1-2- n)

1000000001

-VREF(%+2- n)

1000000000

-VREF/2

0111111111

-VREF (%-2- n)

0000000001

-VREF (2- n)

0000000000

0

NOTE: 1. LSB=2- n VREF
2. n= 10 for 7520,7530
n= 12 for 7521, 7531

APPLICATIONS

Unipolar Binary Operation
The circuit configuration for operating the AD7520
(AD7530) and AD7521 (AD7531) in unipolar mode is shown
in Figure 11. With positive and negative VREF values the
circuit is capable of 2-Quadrant multiplication. The "Digital
Input Codel Analog Output Value" table for unipolar mode is
given in Table 1.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical va/tHIs have bgen characterized but are not tested

4-5

•

~

AD7520/AD7530
~ AD7521/AD7531
.::II

..

~
(II
II)

....

~

o
ell)

2.

Adjust the offset zero adjust trimpot of the output
operational amplifier for OV ± 1 mV at VOUT.

GAIN ADJUSTMENT
1.

Connect all AD7520 (AD7530) or AD7521 (AD7531)
digital inputs to V + .
Monitor VOUT for a -VREF (1-2-n) reading. (n=10
for AD7520 (AD7530) and n = 12 for AD7521
(AD7531)).
To decrease VOUT, connect a series resistor (0 to
500n) between the reference voltage and the VREF
terminal.
To increase VOUT, connect a series resistor (0 to
500n) in the IOUTl amplifier feedback loop.

II)

....

2.

~
o
(II

3.

.::II

II)

....
.::II

C

A "Logic 1" input at any digital input forces the corresponding ladder switch to steer the bit current to IOUTl bus.
A "Logic 0" input forces the bit current to IOUT2 bus. For
any code the IOUTl and IOUT2 bus currents are complements of one another. The current amplifier at IOUT2 changes the polarity of IOUT2 current and the transconductance
amplifier at IOUTl output sums the two currents. This configuration doubles the output range but halves the resolution
of the DAC. The difference current resulting at zero offset
binary code, (MSB = "Logic 1", All other bits = "Logic 0"), is
corrected by using an external resistor, (10 Megohm), from
VREF to IOUT2·

ZERO OFFSET ADJUSTMENT
Connect all digital inputs to GND.
1.

4.

OFFSET ADJUSTMENT
1.
2.
3.

Bipolar (Offset Binary) Operation

4.

The circuit configuration for operating the AD7520
(AD7530) or AD7521 (AD7531) in the bipolar mode is given
in Figure 12. Using offset binary digital input codes and positive and negative reference voltage values, 4-Quadrant
multiplication can be realized. The "Digital Input Codel Analog Output Value" table for bipolar mode is given in Table 2.

5.

Adjust VREF to approximately + 10V.
Connect all digital inputs to "Logic 1".
Adjust IOUT2 amplifier offset adjust trimpot for OV
± 1mV at IOUT2 amplifier output.
Connect MSB (Bit 1) to "Logic 1" and all other bits
to "Logic 0".
Adjust IOUTl amplifier offset adjust trimpot for OV
± 1 mV at VOUT.

GAIN ADJUSTMENT
1.
2.

...

~"------~--~------~VVv-------~

3.
4.

Connect all digital inputs to V + .
Monitor VOUT for a -VREF (1-2-(n-l») volts reading. (n = 10 for AD7520 and AD7530, and n = 12 for
AD7521 and AD7531).
To increase VOUT, connect a series resistor of up to
500n between VOUT and RFEEDBACK'
To decrease VOUT, connect a series resistor of up
to 500n between the reference voltage and the
VREF terminal.

POWER DAC DESIGN USING AD7520
A typical power DAC designed for 8 bit accuracy and 10
bit resolution is shown in Figure 13. An INTERSIL ICH8510
power operational amplifier (1 Amp continuous output at up
to ±25V) is driven by the AD7520.
A summing amplifier between the AD7520 and the
ICH8510 is used to separate the gain block containing the
AD7520 on-chip resistors from the power amplifier gain
stage whose gain is set only by the external resistors. This
approach minimizes drift since the resistor pairs will track
properly. Otherwise the AD7520 can be directly connected
to the ICH8510, by using a 25V reference for the DAC.
An important note on the AD7520/1 01 A interface concerns the connection of pin 1 of the DAC and pin 2 of the
101 A. Since this pOint is the summing junction of an amplifier with an AC gain of 50,000 or better, stray capaCitance
should be minimized; otherwise instabilities and poor noise
performance will result. Note that the output of the 101 A is
fed into an inverting amplifier with a gain of - 3, which can
be easily changed to a non-inverting configuration. (For
more information see: INTERSIL Application Bulletin A021:
Power D/A Converters Using The IH8510 by Dick
Wilenken.)

0330-13

Figure 12: Bipolar Operation
(4-Quadrant Multiplication)

TABLE 2
CODE TABLE -

BIPOLAR (OFFSET BINARY)
OPERATION

DIGITAL INPUT

ANALOG OUTPUT

1111111111

-VREF (1-2-(n-l»)

1000000001

-VREF (2-(n-l»)

NOTE: 1.

1000000000

0

0111111111

VREF (2-(n-l»)

0000000001

VREF (1-2-(n-l»)

0000000000

VREF

LSB~2-(n-1)

VREF
2. n ~ 10 for 7520 and 7521
~ 12 for 7530 and 7531

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

4-6

AD7 520/AD7 530
AD7 521/ AD7 531

.

30Kn

II

. . - - - -.... 3

BIT
-SWITCH!I

{

,

VAEF (±10Y)

,.

+15Y

•I==L 13
•

12

•
7

11
"

•

LaB}

•

10Kfl

:~ITCH!I
100pl

1.IKO

....
-1SY

0330-14

Figure 13: Basic Power DAC

•

Analog/Digital Division
With the AD7520 connected in its normal multiplying configuration as shown in Figure 13, the transfer function is:

+15V

A1 A2 A3
An)
VO= -VIN ( 21"+ 22 + 23 + ... 2n
where the coefficients Ax assume a value of 1 for an ON bit
and 0 for an OFF bit.
By connecting the DAC in the feedback of an operational
amplifier, as shown in Figure 14, the transfer function becomes:

Vo = (A1

,.

BIN (MSI) 15

::;::==1:

II

V,N

DIGITAL:
INPUT

i

a1T~10 (LBB)

-~~N

YOUT

13

3

0330-15

A2
An)
21"+22 +23 +"'2n

Figure 14: Analog/Digital Divider
For further information on the use of this device, see the
following Application Bulletins:

This is division of an analog variable (VIN) by a digital
word. With all bits off, the amplifier saturates to its bound,
since division by zero isn't defined. With the LSB (Bit-10)
ON, the gain is 1023. With all bits ON, the gain is 1 (± 1
LSB).

A016
A018
A020
A021

"Selecting AID Converters," by David Fullagar
"Do's and Don'ts of Applying AID Converters," by
Peter Bradshaw and Skip Osgood
"A Cookbook Approach to High-Speed Data Acquisition and Microprocessor Interfacing" by Ed Sliger
"Power DIA Converters Using the IH8510," by Dick
Wilenken

INTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

4-7

= AD7523

II)

too

8-Bit Multiplying

~ 01 A Converter

GENERAL DESCRIPTION

FEATURES

The AD7523 is a monolithic, low cost, high performance,
10 bit accurate, multiplying digital-to-analog converter
(DAC), in a 16-pin DIP.
Intersil's thin-film resistors on CMOS circuitry provide 8bit resolution (8, 9 and 10-bit accuracy), with TIL/CMOS
compatible operation.
The AD7523's accurate four quadrant multiplication, full
military temperature range operation, full input protection
from damage due to static discharge by clamps to V + and
GND, and very low power dissipation make it a very versatile converter.
Low noise audio gain controls, motor speed controls, digitally controlled gain and attenuators are a few of the wide
range of applications of the 7523.

• 8, 9 and 10 Bit Linearity
•
•
•
•

Low Gain and Linearity Temperature Coefficients
Full Temperature Range Operation
Static Discharge Input Protection
DTL/TIL/CMOS Compatible
• + 5 to + 15 Volts Supply Range
• Fast Settling Time: 150ns Max at 25·C
• Four Quadrant Multiplication

ORDERING INFORMATION
Part Number/Package

Nonlinearity
Plastic DIP

CERDIP

CERDIP

0.2%
(8 Bit)

AD7523JN

AD7523AD

AD7523SD

0.1%
(9 Bit)

AD7523KN

AD7523BD

AD7523TD

0.05%
(10 Bit)

AD7523LN

AD7523CD

AD7523UD

O·Cto +70·C

- 25·C to + 85·C

-55·Cto +125·C

TEMPERATURE RANGE

VREFIN

10Kn

10KU

10KU

10KU

OUT1

?

(15)

2OKU;> 20KU;> 2OK1!

SPO!

r'! , rh r'it

SWIT~':t~~ I :,
I

6

I

I

I

I

I

I

o

o

USB

BITZ

BITa

(4)

(5)

(6)

,

II ~ ~ AFEEO.ACK

OUT2

[!

j!!l VAEFIN

GNO

11

IBJ V+

BIT 1 (USB)

[!

AD7523

~ NC

1m NC

BIT 2 (]

IOUT2(2)
10uTI (1)

BIT 3

[!

~ BIT 8 (LSB)

RFEEDBACK

BIT 4

I!

BIT 5

[!

~ BIT 7
~ BITS

10KI!

~(16)

TOP VIEW
0331-1

Figure 1: Functional Diagram
(Switches shown for Digital Inputs "High")

0331-2

Figure 2: Pin Configuration
Outline Drawings DE, PE

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR use.

NOTE: All typIcsl valuss MVS bHn cluiract6riztNJ but are not tHt«l

4-8

AD7523
ABSOLUTE MAXIMUM RATINGS (TA = 25'C unless otherwise noted)
Supply Voltage (V +) ............................ + 17V
Ceramic PackageVREF ......................................... ±25V
up to 75'C ................................. 450mW
Digital Input Voltage Range ................. V+ to GND
derate above 75'C by ....................... 6mW/'C
Output Voltage Compliance ............. -100mV to V+
Operating Temperatures
Power Dissipation:
IN, KN, LN Versions ................... O'C to + 70'C
Plastic Package AD, BD, CD Versions . . . . . . . . . . . . . . .. - 25'C to + B5'C
up to + 70'C ............................... 670mW
SD, TD, UD Versions . . . . . . . . . . . . . .. - 55'C to + 125'C
derate above + 70'C by ................... B.3mWI'C
Storage Temperature ................ -65'C to + 150'C
Lead Temperature (Soldering, 10sec) ........... + 300'C
CAUTION:
1. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused
units in conductive foam at all times.
2. Do not apply voltages higher than VDD and lower than GND to any terminal except VREF+ RFEEDBACK.

NOTE: Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only snd functionsl
operation of the device st these or any other conditions above those indicated in the operationsl sec/ions of the specificstions is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V+ = + 15V, VREF = + 10V unless otherwise specified)
Test Conditions

Parameter

TA
Min-Max

TA
+ 25'C

Unit

Limit

DC ACCURACY (Note 1)
Resolution
Nonlinearity (Note 2)

(±% LSB)

B

B

Bits

Min

±0.2

±0.2

%ofFSR

Max

(±%LSB)

-10V,,;VREF,,;+10V

±0.1

±0.1

% ofFSR

Max

(±Ys LSB)

VOUT1 =VOUT2=OV

±0.05

±0.05

%ofFSR

Max

Gain Error (Note 2)

Digital Inputs high.

±1.5

% ofFSR

Max

Nonlinearity Tempco (Notes 2 and 3)

-10VVREF +10V

Monotonicity

Guaranteed
±1.B

ppm of FSRI'C Max

2

Gain Error Tempco (Notes 2 and 3)

10

Output Leakage Current (either output)

ppm of FSRI'C Max

VOUT1 =VOUT2=O

±50

±200

nA

Max

ACACCURACY
Power Supply Rejection (Note 2)
Output Current Settling Time (Note 3)
Feedthrough Error (Note 3)

V+ = 14.0 to 15.0V

0.02

0.03

% ofFSR

Max

To 0.2% of FSR, RL = 1000

150

200

ns

Max

VREF = 20V pp, 200kHz sine wave.
All digital inputs low.

±%

±1

LSB

Max

0

r---

REFERENCE INPUT
5K
Input Resistance (Pin 15)

All digital inputs high. IOUT1 at ground.

Temperature Coefficient (Note 3)

Min

Max

20K
-500

ppml'C

Max

100

pF

Max

30

pF

Max

ANALOG OUTPUT
Output Capacitance
(Note 3)

COUT1

All digital inputs high (VINH)

COUT2
COUT1

All digital inputs low (VINL)

COUT2

30

pF

Max

100

pF

Max

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: Aft typical values have been charactBrizsd but are not tested.

4·9

•

= AD7523

.D~Dn.

...

10

~ ELECTRICAL CHARACTERISTICS

(v+ = + 15V, VREF= + 10V unless otherwise specified) (Continued)

Parameter

Test Conditions

TA
+ 25°C

I

TA
Min-Max

Unit

Limit

DIGITAL INPUTS
Low State Threshold (VINU

0.8

V

Max

High State Threshold (VINH)

2.4

V

Min

p,A

Max

4

pF

Max

+5to +16

V

I

rnA

Input Current (Low or high)

VIN=OVor +15V

±1

Input Coding

See Tables 1 & 2

Binary/Offset Binary

Input Capacitance (Note 3)
POWER REQUIREMENTS
Power Supply Voltage Range

Accuracy is tested and guaranteed
at V+ = +15V, only.

1+

All digital inputs low or high.

NOTES: 1.
2.
3.
4.

2

2.5

Max

Full scale range (FSR) 18 10V for unipolar and ± 10V for bipolar modes.
Using Internal feedback resistor. RFEEDBACK.
Guaranteed by design; not subiect to test.
Aocuracy not guarantesd unleBB outputs at ground potential.

Table 1. Unipolar Binary Code Table

APPLICATIONS

Digital Input
MSB LSB

UNIPOLAR OPERATION
!1DV

v""'

+'IV

..
R,

NOTa:
1. "' AND

Analog Output

(255)
256

11111111

-VREF

10000001

-VREF

10000000

-VREF

C29)
C28)=-

01111111

-VREF

C27)

00000001

-VREF

(2~6)

00000000

-VREF

(2~6)=0

fl. U81D OtI.Y IP GAIN

AlNUlTMENT 18 RIQUIRID.

a. Cllt1 PROTECTS AD71D AGAfNer
NEGATIYI TftAN8IENTI•
"21k

DATA lua8
..PUTS· L. . 11

0331-3

256

256

VREF
2

256

Figure 3: Unipolar Binary Operation

NOTE: 1 LSB=(2- 8) (VREF)=

C!s)

(VREF)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical vsJuss"... bHn _

but oro not _ _

4-10

IIJD~DI!. ~

AD7523

...
CII

Table 2. Bipolar (Offset Binary) Code Table

BIPOLAR OPERATION

Digital Input
::10V

MSB

"15V

:

Analog Output

LSB

VREF

11111111

-VREF

10000001

-VREF

0331-4

Figure 4: Bipolar Operation

NOTE:

128

C~8)
0

10000000

NOTES:
1. R3/R4 MATCH 0.1% OR BEITER.
2. Rl, R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
3. R5·R7 USED TO ADJUST VOUT~OV AT INPUT CODE
10000000.
4. CRl & CR2 PROTECT AD7523 AGAINST NEGATIVE TRAN·
SIENTS.

C27)

C~8)

01111111

+VREF

00000001

+VREF

C27)

00000000

+VREF

C28)

1LSB~(2-7)

(VREF)~ (1~8)

128

128

(VREF)

A typical power DAC designed for 10 bit accuracy and 8
bit resolution is shown in Figure 5. The Intersil ICH8510
power operational amplifier (1 Amp continuous output with
up to + 25V) is driven by the AD7523.
A summing amplifier between the AD7523 and the
ICH8510 is used to separate the gain block containing the
AD7520 on-chip resistors from the power amplifier gain
stage, whose gain is set only by the external resistors. This
approach minimizes drift since the resistor pairs will track
properly. Otherwise AD7523 can be directly connected to
the ICH8510, by using a 25 volt reference for the DAC.

POWER DAC DESIGN USING AD7523
,----------;1

16~--------------------_,
VREF (±10V)

.-----12
15
.....- - - - - - 1 3
14
4 INTERSIL 13
5 AD7523 12

-

{

BIT
SWITCHES

11
10

+15V
NC
NC
}

O.68n

10Kll

VOUT

BIT
SWITCHES

100pf

0.6an
7.5Kn

0331-5

Figure 5: Basic Power DAC Design

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

4-11

•

: AD7823
II)

....
~

DEFINITION OF TERMS
NONLINEARITY: Error contributed by deviation of the DAC
transfer function from a best straight line function. Normally
expressed as a percentage of full scale range. For a multiplying DAC, this should hold true over the entire VREF
range.
RESOLUTION: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2- n) (VREF). A
bipolar converter of n bits has a resolution of [2 - (n -1 l]
[VREF]. Resolution in no way implies linearity.
SETTLING TIME: Time required for the output function of
the DAC to settle to within % LSB for a given digital input
stimulus, i.e., 0 to Full Scale.
GAIN: Ratio of the DAC's operational amplifier output voltage to the nominal input voltage value.
FEEDTHROUGH ERROR: Error caused by capacitive coupling from VREF to output with all switches OFF.
OUTPUT CAPACITANCE: Capacity from IOUT1 and IOUT2
terminals to ground.
OUTPUT LEAKAGE CURRENT: Current which appears on
IOUT1 terminal with all digital inputs LOW or on IOUT2 terminal when all inputs are HIGH.

AD7523
OUT1

t

VOUT "" - VIN/o

3

WHERE:
VREF

o ==

BIT1

21

+ !IT! +... !!.!!
22

28

( O400k
for effective input offset less than 25", V).
The reference inverting amplifier used in the bipolar mode
circuit must also be selected carefully. If 14-bit accuracy is
desired without adjustment, low input bias current (less than
1nA), low offset voltage (less than 50",V), and high gain
(greater than 400k) are recommended. If a fixed reference
voltage is used, the gain requirement can be relaxed. For
highest accuracy (better than 13 bits), an additional op-amp
may be needed to correct for IR drop on the Analog
GrouND line (op-amp A2 in Figure 11). This op-amp should
be selected for low bias current (less than 2nA) and low
offset voltage (less than 50",V).

The V+ (pin 25) power supply should have a low noise
level, and no transients exceeding 7 volts. Note that the
absolute maximum digital input voltage allowed is V+,
which therefore must be applied before digital inputs are
allowed to go high. Unused digital inputs must be connected to GND or V+ for proper operation.

Unipolar Binary Operation (lCL7134U)
The circuit configuration for unipolar mode operation
(ICL7134U) is shown in Figure 10. With positive and negative VREF values the circuit is capable of two-quadrant multiplication. The "digital input code/analog output value" table
for unipolar mode is given in Table 3. The Schottky diode
(HP5082-2811 or equivalent) protects lOUT from negative
excursions which could damage the device, and is only necessary with certain high speed amplifiers. For applications
where the output reference ground point is established
somewhere other than at the DAC, the circuit of Figure 11
can be used. Here, op-amp A2. removes the slight error due
to IR voltage drop between the internal Analog GrouND
node and the external ground connection. For 13-bit or lower accuracy, omit A2 and connect AGNDF and AGNDs directly to ground through as Iowa resistance as possible.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AJI typical values haV9 been characterized but are not tested.

4-38

ICL7134
ZERO OFFSET ADJUSTMENT
1.
Connect all data inputs and WR, CS, Ao and A1 to
DGND.
2.
Adjust offset zero-adjust trim-pot of the operational
amplifier A2, if used, for a maximum of OV ±50",V
at AGNDs.
3.
Adjust the offset zero-adjust trim-pot of the output
op-amp, A1, for a maximum of OV ±50",V at VOUT.
GAIN ADJUSTMENT (OPTIONAL)
1.
Connect all data inputs to V + , connect WR, CS, Ao
and A1 to DGND.
2.
Monitor VOUT for a -VREF (1 - % 14) reading.
3.
To decrease VOUT, connect a series resistor of
loon or less between the reference voltage and
the VRFM and VRFL terminals (pins 20 and 18).
4.
To increase VOUT, connect a series resistor of
lOOn or less between A1 output and the RFB terminal (pin 21).

VflEF IN - - - . . - - - - ,

DATA
INPUTS

+sv

17

0341-10

Figure 10: Unipolar Binary, Two-Quadrant
Multiplying Circuit

Bipolar (2'5 Complement) Operation
(ICL7134B)
The circuit configuration for bipolar mode operation
(ICL7134B) is shown in Figure 12. Using 2's complement
digital input codes and positive and negative reference voltage values, four-quadrant multiplication is obtained. The
"digital input codel analog output value" table for bipolar
mode is given in Table 4. Amplifier A3, together with internal
resistors RINV1 and RINV2, forms a simple voltage inverter
circuit. The MSB ladder leg sees a reference input of approximately - VREF, so the MSB's weight is reversed from
the polarity of the other bits. In addition, the ICL7134B's
feedback resistance is switched to 2R under PROM control,
so that the bipolar output range is + VREF to - VREF
(1 - % 13). Again, the grounding arrangement of Figure 11
can be used, if necessary.

DATA
INPUTS

ICl7134U

Table 4: Code Table - Bipolar
(2's Complement) Operation
Digital Input

Analog Output

01111111111111
00000000000001
00000000000000
11111111111111
10000000000001
10000000000000

-VREF(1-'!213)
-VREF('!213)
0
VREF('!213)
VREF(1-%13)
VREF

0341-11

Figure 11: Unipolar Binary Operation
with Forced Ground

Table 3: Code Table - Unipolar Binary
Operation
Digital Input

Analog Output

11111111111111
10000000000001
10000000000000
01111111111111
00000000000001
00000000000000

-VREF(1-'!214)
-VREF(%+'!214)
-VREF/2
-VREF('/2-% 14)
-VREF('!214)
0

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTAB1L1TY AND F1TNESS FOR A PARTICULAR USE.
NOTE: A/J typical values haV9 been characterized but are not tested.

4-39

:: ICL7134

...
too

g
YRIFIN
18
YRFL
RlNY1

18
15

18
RlNY
RlNV2

20
YAFM Y+

o,a(MSB)

RF8

21

0,2

loUT
DATA
INPUTS

ICL7134B

3
+5Y 17

Do(LSB)
PROG

0341-12

Figure 12: Bipolar (2'8 Complement), Four-Quadrant Multiplying Circuit

OFFSET ADJUSTMENT
1.
2.

3.

4.
5.

Connect all data inputs and WR', ~, Ao and A1 to
DGND.
Adjust the offset zero-adjust trim-pot of the operational amplifier A2, if used, for a maximum of OV
±50",V at AGNDs.
Set data to 00000 .... 00. Adjust the offset zeroadjust trim-pot of the output op-amp A1, for a maximum of OV ±50",V at VOUT.
Connect D13 (MSB) data input to V+.
Adjust the offset zero-adjust trim-pot of op-amp Aa
for a maximum of OV ±50",V at the RINV terminal
(pin 19).

3.
4.

5.

Processor Interfacing
The ease of interfacing to a processor can be seen from
Figure 13, which shows the ICL7134 connected to an 8035
or any other processor such as an 8049. The data bus
feeds into both register inputs; three port lines, in combination with the WR line, control the byte-wide loading into
these registers and then the DAC register. A complete DAC
set-up requires 4 write instructions to the port, to set up the
address and ~ lines, and 3 external data transfers, one a
dummy for the final transfer to the DAC register.

GAIN ADJUSTMENT (OPTIONAL)
1.
2.

Monitor VOUT for a -VREF (1-Yz13) reading.
To increase VOUT, connect a series resistor of
2000 or less between the A1 output and the RFB
terminal (pin 21).
To decrease VOUT, connect a series resistor of
1000 or less between the reference voltage and
the VRFL terminal (pin 18).

Connect WR', ~, Ao and A1 to DGND.
Connect Do, D1 ... D12 to V+, D13 (MSB) to
DGND.

IN1ERSIL'S SOLE AND EXCL.USIV£ WARRANTY OBUGATION WITH REBFECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE ODNDmON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR Use.
NOTE:AHtypIcM _ _ _ _ bul .... , . , , _ .

4-40

IfID~Ol\.

ICL7134

P
...

....
61

+5V IN

.sv

.........
"'0-17

} OTHER

IN

...

.

'"::,010

Do

...

0,
0,

loUT

'MIOC35

P"

,/0

Co
A,

805D

"41
ETC.

DB,

Viii

leLM34

Do
AGNo.

Do,

Viii
0341-14

Figure 14: Interface to 80ao System
0341-13

Figure 13: ICL7134 Interface to 8048 System

Aa-,.t=======~=--'--------------.--------.
8212

ICL7134

0341-15

Figure 15: 8085 System Interface

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH REBPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE OCNDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIEB OF
MERCHANTABILITY AND FITNEBS FOR A PARTICULAR USE.

NOTe: AU typicBI .../USS have b66n chJJrsc/orfzod but are not tos/sd.

4-41

.......~

d_

.D~OIl.

ICL7134

ure 15. The decoding of the 10/M line, which controls memory-mapped or I/O-mapped operation, is arbitrary, and can
be omitted if not necessary. Neither the MC6BOX nor R650X
processor families offer specific I/O operations. Figure 16
shows a suitable interface to either of these systems, using
a direct connection. Several other decoding options can be
used, depending on the other control signals generated in
the system. Note that the R650X family does not require
VMA to be decoded with the address lines.

A similar arrangement can be used with an BOBOA, B22B,
and B224 chip set. Figure 14 shows the circuit, which can
be arranged as a memory-mapped interface (using ~EMW)
or as an I/O-mapped interface (using I/O WRIT ). See
A020 and R005 for discussions of the relative merits of
memory-mapped versus I/O-mapped interfacing, as well as
some other ideas on interfacing with BOBO processors. The
BOBS processor has a very similar interface, except that the
control lines available are slightly different, as shown in Fig-

1CL7134

MC.680X
MCIH50X

L-_ _---' OPTIONAL

GATE
(SEE TEXT)

0341-17
0341-16

Figure 17: Avoiding Digital Feedthrough
in an 8048 to ICL7134 Interface

Figure 16: R650X and MC680X
Families' Interface to ICL7134

INTERSIL
III8OC48
INTEL
8080
8085

ANALOG~
CIRCUIT

L-...y'

ETC.

0341-18

Figure 18: ICL7134 to 8048/80/85 Interface with Low Feedthrough

INTERSIL'S SOLE AND exCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTV ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE exCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITV AND FITNESS FOR A PARTICULAR USE.

NOTE: An fMJ/OII- ""VB bHn _

but Me not tfi/od.

4-42

IIU~UIL

ICL7134
Digital Feedthrough

visable (see A053). The clock, using two Schmitt trigger TTL
gates, runs at a slower rate for the first 8 bits, where settling-time is most critical, than for the last 6 bits. The shortcycle line is shown tied to the 15th bit; if fewer bits are
required, it can be moved up accordingly. The circuit will
free-run if the HOLD/RUN input is held low, but will stop
after completing a conversion if the pin is high at that time.
A low-going pulse will restart it. The STATUS output indicates when the device is operating, and the falling edge
indicates the availability of new data. A unipolar version may
be constructed by tying the MSB (D13) on an ICL7134U to
pin 14 on the first AM25L03, deleting the reference inversion amplifier A4, and tying VRFM to VRFL.

All of the direct interfaces shown above can suffer from a
capacitive coupling problem. The 14 data pins, and 4 control pins, all tied to active lines on a microprocessor bus,
and in close proximity to the sensitive DAC circuitry, can
couple pseudo-random spikes into the analog output. Careful board layout and shielding can minimize the problems
(see PC layout), and clearly wire-wrap type sockets should
never be used. Nevertheless, the inherent capacitance of
the package alone can lead to unacceptable digital feedthrough in many cases. The only solution is to keep the
digital input lines as inactive as possible. One easy way to
do this is to use the peripheral interface circuitry available
with all the systems previously discussed. These generally
allow only 8 bits to be updated at anyone time, but a little
ingenuity will avoid difficulties with DAC steps that would
result from partial updates. The problem can be solved for
the 8048 family by tying the 14 port lines to the data input
lines, with CS, Ao and A1 held low, and using only the WR
line to enter the data into the DAC (as shown in Figure 17).
WR is well separated from the analog lines on the ICL7134,
and is usually not a very active line in 8048 systems. Additional "protection" can be achieved by gating the processor
WR line with another port line. The heavy use of port lines
can be alleviated by use of the IM82C43 port expander. The
same type of technique can be employed in the 8080/85
systems by using an 8255 PIA (peripheral Interface adapter)
(Figure 18) and in the MC680X and R650X systems by using an MC6820 (R6520) PIA.

PC BOARD LAYOUT
Great care should be taken in the board layout to minimize ground loop and similar "hidden resistor" problems, as
well as to minimize digital signal feedthrough. A suitable layout for the immediate vicinity of the ICL7134 is shown in
Figure 20, and may be used as a guide.

APPLICATION NOTES
Some applications bulletins that may be found useful are
listed here:

Successive Approximation AID
Converters
Figure 19 shows an ICL7134B-based circuit for a bipolar
input high speed AID converter, using two AM25L03s to
form a 14-bit successive approximation register. The comparator is a two-stage circuit with an HA2605 front-end amplifier, used to reduce settling time problems at the summing node (see A020). Careful offset-nulling of this amplifier
is needed, and if wide temperature range operation is desired, an auto-null circuit using an ICL7650 is probably ad-

A016

"Selecting AID Converters," by Dave Fullagar.

A017

"The Integrating AID Converter," by Lee Evans.

A018

"Do's and Dont's of Applying AID Converters," by
Peter Bradshaw and Skip Osgood.

A020

"A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing," by Ed Sliger.

A021

"Power AID Converters Using the ICH8510," by
Dick Wilenken.

A030

"The ICL71 04 - A Binary Output AID Converter for
Microprocessors," by Peter Bradshaw.

R005

"Interfacing Data Converters & Microprocessors,"
by Peter Bradshaw et ai, Electronics, Dec. 9, 1976.

Most of these are available in the Intersil Data Acquisition
Handbook, together with other material.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

4-43

n...
.......

Col

...

.......~

ICL7134

g

-2- ~>
+15V

f+

~5V

18

19

DGND VAL
f-J CS
~ -WR

~
~

A;,
A,

+

.... HP2IIOO

VIN

.;

.....

A3

0;..

1'-

22)

-

20

24
IItNY VAMAGNDs

r}
!*"

~l17f

+5V

23
21
25
PROG V + AGND. R.B louT

HAae05

ICL7134B

+

MSB
16 15 1413 12 1110 9

"7

LSB
8 7 8 5 4 3

LSBL _

IN827A

':,j r'
to.

-15V

+5V.

+

~"~

5V
8800

+LM311

OUT

*

HP2IIOO

-15V

~-

lMIl
1301l
~

-15V

--t++-. BLUE
256x12 RAM

PO-P7

AND

OVO-OV1

r-t-HI-+

RED

3x 12 OVERLAY
REGISTERS

~.-t-H"'" GREEN

BRIGHT
BLANK
HSYNC
VSYNC

4

Figure 1: Functional Diagram

0082-1

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALlE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
601140-001
NOTe: AU typical valUflS haVB bsBn chsractetfZ6d but sre not tested.

4-46

IIU~OIl..

IM2110
ABSOLUTE MAXIMUM RATINGS
Supply Voltages .................................. 6.0V
VIH (Input Logic "1" Voltage) ......... 2.0V to Voo + 0.5V
VIL (Input Logic "0" Voltage) .............. -0.5V to O.BV
Power Dissipation (Plastic Package) ............. 600 mW
Operating Temperature .................... O'C to + 70'C
Storage Temperature ................. - 65'C to + 150'C
Lead Temperature (Soldering, 10 sec.) ............. 300'C

ADD

VDD

AD'

P7

AD2

P6

AD3

PS

AD4

P4

ADS

P3

AD6

P2

AD7

P'
PO

ADa

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AD9

BIAS

AD,O

BLUE

AD"
elK

VAA

RED

cs

GREEN

ALE

IREF

ViR

GND

R5

BRIGHT

TEST

BLANK

ovo
ov,

VSYNe

HSYNe

0062-2

Figure 2: Pin Configuration

OPERATING CONDITIONS
Symbol

Parameter

Voo, VAA

Positive Supply Voltage

TA

Ambient Temperature

RSET

Typ

Min

Max

Units

4.5

5.5

V

0

+70

'C

Resistive Load on DAC Outputs

37.5

n

Capacitive Load on DAC Outputs

50

pF

1050

n

Full Scale Adjust Resistor

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Symbol
Icc

Parameter

Min

Average Power Supply Current

Typ

DAC Resolution
DAC Accuracy
Integral Linearity
Differential Linearity
Monotonicity
Zero Offset
Gain Error (Adjustable to Zero)
Differential Accuracy (between
Different Outputs on Same Device)

Vo
IREF

Max
- - 150

--

Units
mA

4

Bits

+%
+'/4

LSB
LSB

-Va
-%

+Va
+%

LSB
LSB

-1

+1

LSB

-%
-'/4
Guaranteed

DAC Output Characteristics
Full Scale Output Current (Green)
Full Scale Output Current (Red, Blue)
Maximum Output Voltage

26.7
19.05
2.0

REFERENCE
Reference Current (at IREF Pin)
Reference Voltage (at IREF Pin)
Voltage Temperature Coefficient
Power Supply Rejection
(VAA = Voo = 5V ±5%)

mA
mA
V
-1.2
1.4

1.0
200
1.0

mA
V
ppml'C
%VREF

INTERSIL S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

4-47

iI\)

......
0

......o

IM2110

!

AC Test Conditions

(\I

Input Pulse Levels .......................... O.4V to 2.4V
Input Rise & Fall Times ................... 5 ns maximum
Input Timing Reference Level ...................... 1.5V

AC CHARACTERISTICS
Symbol

VDD

=

5V +10%
TA
-

=

O'Cto +70'C

Parameter

Min

Typ

Max

Units

tcHCH

Clock Period

38

ns

tCLCH

Clock Width Low

10

ns

tCHCL

Clock Width High

10

ns

Clock Rise & Fall Times

5

ns

tAC

Pixel Address (or OVERLAY,
BLANK, SYNC, BRIGHT) Set-Up Time

10

ns

tCA

Pixel Address (or OVERLAY, BLANK,
SYNC, BRIGHT) Hold Time

10

ns

tCDA

Clock to DAC Output (Note 1)

33

ns

DAC Full Scale Settling Time (Note 2)

15

DAC 10-90% Rise Time (Note 3)

8

ns

DAC Output Glitch Energy

50

pVs

ns

tLL

ALE Width

35

ns

tAL

Address (and CS) to Latch Set-Up Time

15

ns

tLA

Address (and CS) Hold Time after Latch

15

ns

tLW

Latch to WRITE

-10

ns

tww

WRITE Pulse Width

80

ns

tAW

Data to WRITE Set-Up Time

90

ns

tWA

Data Hold Time after WRITE

0

ns

tWL

WRITE to next ALE

20

ns

tLE

ALE to ENABLE

25

ns

tEW, tEE

WRITE Duration

80

ns

tAR

Address Float to READ

10

ns

tRR

READ Pulse Width

130

ns

tRL

READ to next ALE

30

tRD

Valid Data from READ

100

ns

tRF

Data Valid after READ

30

ns

ns

NOTE 1: To O.2V on Red and Blue outputs, to O.4SV on Green output.
2: To within

% LSB of final value.

3: Capacitive load on DAC output of 10pF maximum.

PIN DESCRIPTION
Pin Name

Pin Number

ADO-AD12

1-12

PO-P7

32-39

Description
Microprocessor Address/Data. The 8 bits of RAM address and the 2 bits of overlay address
are latched into the IM211 0 when ALE is High. The 8-bit or 12-bit data is then written into the
RAM and the overlay registers or read from them, depending on the state of WR and RD.
Pixel address. The address on these pins is latched on the first rising edge of the clock and
decoded to select one of 256 colors stored in the color lookup table.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

4-48

IIJD~DI!..

IM2110
PIN DESCRIPTION
Pin Name

(Continued)

Pin Number

Description

CLK

13

Pixel clock. Latches PO-P7, OVO, OV1, HSYNC, VSYNC, BLANK and BRIGHT. Transfers
address information from the input latches to the RAM decoder, and transfers RAM data
from the DAC registers to the DAC inputs. Two clock transitions plus the DAC settling time
are required from data address input to a valid output.

CS

14

Chip select for microprocessor interface (active low). CS is latched on the falling edge of
ALE. When CS is low, the microprocessor port is enabled, and the DAC outputs go to the
reference black level. (However, if the HYSNC, VSYNC or BLANK signals are applied, the
DAC outputs are set to those respective levels).

ALE

15

Address Latch Enable. Latches ADO-AD9 inputs into address registers when High, and the
state of CS into the CS register on the falling edge. Used as the" AS" control with a
Motorola microprocessor.

WR

16

Write. Logic "0" selects Write operation. Used as the "READ/WRITE" pin with a Motorola
microprocessor.

RD

17

Read. Logic "0" selects Read operation onto the microprocessor bus, for manufacturer's
testing purposes only. Used as the "ENABLE" or "DATA STROBE" control with a Motorola
microprocessor.

TEST

18

Test. Logic "0" enables operation in test mode. Used for manufacturer's testing purposes
only. This pin should always be tied to Voo.

19,20

Overlay select. Enable and select one of the three overlay registers for Video Read. When
accessing the overlay registers, PO-P7 are ignored.

OVO,OV1

VSYNC, HSYNC

21,22

OV1

OVO

0
0
1
1

0
1
0
1

Color Table RAM
Overlay Register 1
Overlay Register 2
Overlay Register 3

Green Vertical and Horizontal Sync. These two signals are exclusive-ORed inside the chip,
to produce a composite SYNC signal.
SYNC resets all DAC registers and forces all outputs to OV.
These inputs have priority over data inputs from the RAM and the overlay registers.

BLANK

23

DAC Blanking. Logic "1" resets all DAC registers. Red and Blue outputs fall to OV, Green
output falls to 286 mV (blanking levels). This input has priority over data inputs from the
RAM and the overlay registers.

BRIGHT

24

10% Bright. Logic "0" turns on an additional current source in each DAC. This produces an
overbright pixel when a "White" input (all 1's) is applied to the DAC inputs.

IIREF

26

Reference Current. A resistor is connected from this pin to Ground in order to set a 1 LSB
current. The nominal voltage output at this pin is 1.2V, and the nominal value of the resistor
should be 10500 for a 37.50 output termination.

BIAS

31

Internal current source bias is provided with a temperature compensated reference. This
pin is used for compensating the Bias line. 0.1 ",F and 0.01 ",F capacitors are normally
connected in parallel from this pin to VAA.

R,G,B

29,27,30

Red, Green, and Blue Current Outputs. These analog outputs are intended to drive a
minimum load of 37.50. If terminated with a 750 resistor and a coaxial cable with 750
impedance, reflection is minimized by matched termination of the cable. The full scale
current needed at these outputs is adjusted with the resistor at IREF.

Voo

40

Digital 5V positive supply.

VAA

28

Analog 5V positive supply, providing the high DAC output current. VAA = Voo.

GND

25

Digital and analog ground.

INTERSIL S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values hsvs been chsrsr:terized but ars not tested.

4-49

i

......
o
N

...~

IM2110

!

FUNCTIONAL DESCRIPTION

(II

When writing to the IM2110, the state of CS and the address are latched on the falling edge of ALE. Data is then
transferred when WR is low.
An Intel microprocessor may be used as described
above. A Motorola microprocessor may be used by taking
into account the following pin correspondence (see timing
diagrams, Figure 3 and Figure 4):

Microprocessor Interface
As illustrated in the functional diagram, the IM211 0 has a
256 x 12 RAM and three 12-bit overlay registers. The MPU
bus interface allows the writing of data into the RAM and
the overlay registers, and operates asynchronously with the
video data.
The device can be addressed either through the 12-bit
microprocessor interface for writing data, or through the 8bit video interface for transferring data to the video outputs.
The microprocessor port is selected when Chip Select is
active, and the video port is selected otherwise.
An 8-bit status register must be written to first, after power is applied to the part, in order to set an "8-bit" or a "12bit" mode. Depending on the value stored at bit DO in this
register, data to the RAM and the overlay registers will be
written 8 or 12 bits at a time. See Table for address mapping.
The lowest four data bits (DO-D3) contain the Red intensity information, the next four bits (D4-D7) contain the Blue
intensity information, and the highest four bits (D8-D11)
contain the Green intensity information.

Intel

Motorola

ALE
RD
WR

AS
EorDS
R/W

While the microprocessor port is selected, all the DAC
outputs are set to the reference 'Black' level, unless the
'BLANK', 'VSYNC' or 'HSYNC' signals are applied.
The content of the RAM (but not of the overlay registers)
can be read back onto the AD bus, 12 bits at a time. This
feature is used primarily for testing the part. The timing diagram and the specifications for this Read function are supplied for information purposes only. Note that in this mode
the video clock must be operating at a frequency at least
double that of ALE. (See Figure 5.)

1 - - - - - - tAW - - - - - I

ALE

tWL

r----

~-I---+lI--------\ww -------4-~-_I

WR - - - - - - . . . . .

0082-9

Figure 3: Microprocessor Write Timing (Intel)

x

.x
ADO-AD11

-

ADDRESS
tAL

xxx
DATA

I

tLA

~

tAW

f

AS
tLL

tLW

tww

'\

R/W
tAL

'I

)

tEW

tLE

}-

E,DS

tWL

~
tEE

I

0082-4

Figure 4: Microprocessor Write Timing (Motorola)
lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

~~~~~~~~~J~T~~~~ ~~N~~~L~~~~ ~~~T~~~~ ~;~~ LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
NOTE: All typical values have been characterized but are not tested.

4-50

tIlD~OIL

IM2110
FUNCTIONAL DESCRIPTION

(Continued)

0082-3

Figure 5: Microprocessor Read (Timing Test)

ADDRESS MAP
Table 1
Address
(ADo-ADg)

12-Bit Mode

8-Bit Mode

Location

Data

Location

Data

OOOh
001h
002h
003h

ramO
ram 1
ram 2
ram 3

DO-D11
DO-D11
DO-D11
DO-D11

•
•

•
•

ramO
ram 1
ram 2
ram 3

DO-D7
DO-D7
DO-D7
DO-D7

OFEh
OFFh

•
•

•
•

•
•

ram 254
ram 255

DO-D11
DO-D11

ram 254
ram 255

DO-D7
DO-D7

100h
101h

ramO
ram 1

DO-D11
DO-D11

•
•

ram 0
ram 1

DS-D11
DS-D11

•
•

•
•

•

•

•

•

1FEh
1FFh

ram 254
ram 255

DO-D11
DO-D11

ram 254
ram 255

DS-D11
DS-D11

201h
202h
203h

ovly 1
ovly2
ovly3

DO-D11
DO-D11
DO-D11

ovly 1
ovly2
ovly3

DO-D7
DO-D7
DO-D7

301h
302h
303h

ovly 1
ovly2
ovly 3

DO-D11
DO-D11
DO-D11

ovly 1
ovly2
ovly3

DS-D11
DS-D11
DS-D11

3FFh

status register

DO-D7

status register

DO-D7

other locations

unused

unused

Status register: DO = 1: 12 bit mode. DO = 0: S bit mode. All other bits unused. When an address is loaded, the levels on
AD10-AD11 are indifferent. In the S-bit mode, the data for Do-D7 must be present on ADo-AD7' and the data for Ds-D11 on
ADo-AD3. The levels on the other AD pins are indifferent.

INTERSIL'8 SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AJI typical values have been characterized but are not tested.

4-51

iII)

......
o

...~

IM2110

(II

!

FUNCTIONAL DESCRIPTION

(Continued)

Color lookup Table

Bright, Blank, Sync

As illustrated in Figure 6, 8 bits of lookup table address
and 2 bits of overlay address are latched into the address
registers on the rising edge of the clock. On the following
rising edge, the 12 bits of color information are latched into
the DAC registers, decoded, and used to turn on or off the
DAC current sources. If ova or OV1 is High, the information
in the overlay registers overrides the pixel data on PO- P7.
The overlay registers allow the use of additional bit planes
in the frame buffers and may be controlled by external character, cursor or grid logic.

These inputs are also sampled on the rising edge of the
clock, and internally pipelined to maintain synchronization
with the data (see Table 3).
When BRIGHT is active, the intensity of the color addressed in the RAM or the overlay registers is increased by
a value of 10% of the Reference White level.

CLOCK

R,G,B-------------------------t---'
0082-8

Figure 6: Video Input/Output Timing
Table 2
Green

Red, Blue

(mV)

(rnA)

(mV)

(mA)

Peak White
Reference White

1071
1000

28.56
26.67

785
714

20.93
19.04

Reference Black
Blanking

357
286

9.52
7.62

71
0

1.89
0

0

0

0

0

Synch

PEAK WHITE

REfERENCE WHITE

REfERENCE BLACK

Jl

'\ / \

BLANK

\

1

1

SYNC

0082-6

Figure 7: Video Output Levels
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTc; All typical values have been charactedz9d but are not tested.

4-52

.O~OR.

IM2110

i

......
o
II)

TRUTH TABLE
Table 3. Voltage and Current Output with Standard Setup
(adjusted for Green Reference White level = 1000 mV, 37.50 load on outputs)
BRIGHT

BLANK

HSYNC

VSYNC

OVO

OV1

PO-P7

Data

Level

0
1

0
0

0
0

0
0

0
0

0
0

addr
addr

255
255

peak white
ref white

•
•
•

•
•
•

•
•
•

1

0

0

0

0

0

addr

1
1
1

0
0
0

0
0
0

0
0
0

1
0
1

0
1
1

X
X
X

(ovly1)
(ovly2)
(ovly3)

X
X
X
X

1
X
X
X

0
1
0
1

0
1
1
0

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

ref black

blank
blank
sync
sync

The 12 bits of color information, in combination with the
SYNC, BLANK or BRIGHT selected at the time of address
input, are used to form the composite output current. This
current, through output loads from 37.50 to 750, provides
the 1 Vp-p RS343A output voltage.
An on-chip temperature-compensated reference and external resistor set the full scale output current of all three
DAC's. A current of one LSB (1.143 mA for 37.50 output
load) is sourced from IREF. Varying RSET adjusts the full
scale output and LSB weight.

Voltage Reference
The internal band gap reference provides a temperature
compensated voltage bias to all three DAC's. Full scale out·
put current is set by using the reference and an external
resistor. The reference voltage at IREF divided by the resist·
ance from IREF to GND is equal to a nominal one LSB of
DAC current. An RSET resistor consisting of a 5000 fixed
resistor in series with a 1 kO variable resistor should be
used to adjust the full scale output voltage for a doubly-terminated 750 system. This adjustment eliminates any gain
error and its range is wide enough to guarantee 1V peak-topeak Green output (Sync tip to Reference White level). Selection of RSET for RS343A output is made by using the
equation:
- Vref x R (load)
R
SET 42.86 mV

0

Reference Adjustment Procedure
A Reference White must be present at the DAC outputs.
The RSET resistor at IREF can then be adjusted to precisely
set this output voltage. The following procedure may be
used:
1) Write all 1's to Overlay register 1. The video clock need
not be active.
2) Transfer the data into the DAC registers by moving the
video clock from Low to High at least twice, while maintaining the following levels on the video input pins:
PO-P7
X
OVO
1
OV1
0
BRIGHT
1
0
BLANK
VSYNC
0
HSYNC
0
3) Measure the voltage at the Green output, and adjust the
resistor value at IREF until that voltage is 1.000V.

(42.86 mV = 1 LSB)

With a nominal 1.2V reference voltage, RSET will be
10500 for a 37.50 (doubly terminated) system and 21000
for a 750 system. Matching the temperature coefficients of
RSET and the load resistors will provide a system with an
output voltage temperature coefficient of typically
200 ppml"C.
The internal voltage generated for current source bias is
present at the BIAS pin. 0.1 fLF and 0.01 fLF capacitors are
connected in parallel from BIAS to VAA.

01 A CONVERTERS
Each DAC consists of 15 equal-weight current sources
providing the gray scale output. This configuration guarantees monotonicity, reduces glitch energy, and ensures high
integral and differential linearity. In addition, SETUP and
BRIGHT current sources are included for RS343A output
and cursor display options. The Green DAC has an additional SYNC current source, for RS343A compatibility.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: All typical values have been characterized but are not tested.

4-53

•

......o

IM2110

!

PC BOARD LAYOUT CONSIDERATIONS

&\I

VDD
+SVDC

BIAS
VAA
C3
GND

GROUND
Rl

11.12110

R3
R2

R4
RS

IREF

7S.!l COAX

BLUE
RED
GREEN
0082-7

Figure 8: IM2110 Typical Power Supply and Output Connections
Rt: 500n metal film resistor
R2: 1 kn cermet potentiometer

Cl, C2, C3: 0.1 I'F and O.Ot I'F monolithic ceramic capacitors in parallel
R3, R4, A5: 750 1% metal film resistor

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but ar8 not tested.

4-54

Section 5

Power Supply
Supervisory
ICL7660 ................ 5-1
ICL7660S ............. 5-10
ICL7662 ............... 5-20
ICL7663 ............... 5-28
ICL7663S ............. 5-37
ICL7665 ............... 5-44
ICL7665S ............. 5-53
ICL7667 ............... 5-63
ICL7673 ............... 5-71
ICL7675 ............... 5-79
ICL7676 ............... 5-79
ICL7677 ............... 5-89
ICL7680 .............. 5-101
ICL8211 .............. 5-103
ICL8212 .............. 5-103

~

a:.

D~D162

ICL7660
CMOS Voltage Converter

ell
ell

o

GENERAL DESCRIPTION

FEATURES

The Intersil ICL7660 is a monolithic CMOS power supply
circuit which offers unique performance advantages over
previously available devices, The ICL7660 performs supply
voltage conversion from positive to negative for an input
range of + 1,5V to + 10,OV, resulting in complementary output voltages of -1 ,5V to -10,OV, Only 2 non-critical external capacitors are needed for the charge pump and charge
reservoir functions, The ICL7660 can also be connected to
function as a voltage doubler and will generate output voltages up to + 18,6V with a + 10V input. Note that an additional diode is required for VSUPPLY > 6,5V,
Contained on chip are a series DC power supply regulator, RC oscillator, voltage level translator, and four output
power MOS switches, A unique logic element senses the
most negative voltage in the device and ensures that the
output N-channel switch source-substrate junctions are not
forward biased, This assures latchup free operation,
The oscillator, when unloaded, oscillates at a nominal frequency of 10kHz for an input supply voltage of 5,0 volts.
This frequency can be lowered by the addition of an external capacitor to the "osc" terminal, or the oscillator may
be overdriven by an external clock.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV) operation. At medium to high voltages (+ 3,5 to + 10.0 volts),
the LV pin is left floating to prevent device latchup,
An enhanced direct replacement for this part called
ICL7660S will become available shortly and will be more
appropriate for new designs.

• Simple Conversion of + 5V Logic Supply to ± 5V
Supplies
• Simple Voltage Multiplication (Vour=(-) nVIN)
• 99.9% Typical Open Circuit Voltage Conversion
Efficiency
• 98% Typical Power Efficiency
• Wide Operating Voltage Range 1_5V to 10.0V
• Easy to Use - Requires Only 2 External
Non-Critical Passive Components

APPLICATIONS
• On Board Negative Supply for Dynamic RAMs
• Localized fL-Processor (8080 Type) Negative
Supplies
• Inexpensive Negative Supplies
• Data Acquisition Systems

ORDERING INFORMATION
Part Number

Temp. Range

ICL7660CTV

0' to + 70'C

ICL7660CBA

O'C to +70'C

ICL7660CPA

0' to + 70'C

ICL7660MTV*

-55' to + 125'C

Package
TO-99
8PINSOIC
8 PIN MINI DIP
TO-99

-Add 18838 to part number if 8838 processing is required.

v+ (and CASE)
V+

ose
LV

0319-1

(Outline Dwg BA)
8 LEAD MlnlDIP

0319-2

(Outline Dwg TV)
8 LEAD TO-99

0319-3

(Outline Dwg PAl

Figure 1: Pin Configurations

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

302063-004

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

5-1

•

~

...

ICL7660

CD

..I

!:!

ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
ICL7660M ........................ - 55'C to + 125'C
ICL7660C ............................ O'Cto +70'C
Storage Temperature Range .......... - 65'C to + 150'C
Lead Temperature
(Soldering, 10sec) .............................. 300'C

Supply Voltage ................................. 10.5V
LV and OSC Input Voltage
(Note 1) ............ - 0.3V to (V ± + 0.3V) for V + < 5.5V
(V+ -5.5V)to(V+ +0.3V)forV+>5.5V
Current into LV (Note 1) ............. 20fLA for V+ >3.5V
Output Short Duration (VSUPPLy,;;5.5V) ....... Continuous
Power Dissipation (Note 2)
ICL7660CTV ............................... 500mW
ICL7660CPA ............................... 300mW
ICL7660MTV ............................... 500mW

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

r---------------~----------------r_------_r-----------------------oV+

r----------------------o CAP +
RC
OSCILLATOR

, - - - - - - - - - - 0 CAP-

VOUT

OSC

LV

LOGIC
NETWORK

VOLTAGE
REGULATOR

0319-7

Figure 2: Functional Diagram

OPERATING CHARACTERISTICS

v+ =5V, TA=25'C, Cosc=O, Test Circuit Figure 3 (unless otherwise specified)
Symbol

Parameter

L.imits

Test Conditions
Min

Units

Typ

Max

170

500

1+

Supply Current

RL =

V~,

Supply Voltage Range - Hi
(Dx out of Circuit) (Note 3)

O'C,;;TA,;;70'C, RL = 10kO, LV Open

3.0

6.5

V

-55'C';;TA';;125'C, RL = 10kO, LV Open

3.0

5.0

V

Vt,

Supply Voltage Range - Lo
(Dx out of circuit)

MIN,;;TA,;;MAX, RL =10kn, LV to GROUND

1.5

3.5

V

V~2

Supply Voltage Range - Hi
(Dx in circuit)

MIN,;;TA,;;MAX, RL =10kO, LV Open

3.0

10.0

V

V~

Supply Voltage Range - Lo
(Dx in circuit)

MIN,;;TA,;;MAX, RL = 10kO, LV to GROUND

1.5

3.5

V

00

fLA

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

5-2

ICL7660
OPERATING CHARACTERISTICS
Y+ = 5Y, TA = 25'C, Case = 0, Test Circuit Figure 3 (unless otherwise specified) (Continued)
Symbol

Parameter

Limits

Test Conditions
Min
lOUT = 20mA, T A = 25'C

Max

55

100

0

120

0

+ 70'C
55'C:5: T A:5: + 125'C (Note 3)

IOUT= 20mA, O'C:5:TA:5:

150

0

Y+ =2Y,loUT=3mA, LYto GROUND
O'C:5:TA:5: + 70'C

300

0

Y+ =2Y,loUT=3mA, LY to GROUND,
- 55'C:5: TA:5: + 125'C, Dx in circuit (Note 3)

400

0

lOUT = 20mA, ROUT

Output Source Resistance

Units

Typ

fose

Oscillator Frequency

10

kHz

PEf

Power Efficiency

RL =5kO

95

98

%

YOUTEf

Yoltage Conversion Efficiency

RL =00

97

99.9

%

Zose

Oscillator Impedance

Y+=2Yolts

1.0

MO

Y=5Yolts

100

kO

Notes: 1. Connecting any input terminal to voltages greater than V + or less than GROUND may cause destructive latchup. It is recommended that no inputs from
sources operating from external supplies be applied prior to "power up" of the ICL7660.
2. Derate linearly above 50"C by 5.5mW I'C.
3. ICL7660M only.

TYPICAL PERFORMANCE CHARACTERISTICS
OPERATING VOLTAGE AS A
FUNCTION OF TEMPERATURE

:::- 10K

~A

:::.
w

~

w

~ ~:~I~~~~~~~~

(Circuit of Figure 3)

OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF SUPPLY VOLTAGE

iil ::~~~·!:i~~t~~~~tj
~~5~~~5~O~~~~+~75~~~­

= 1 mA

-- - -

"""~=+2Y

~

.-"

I"--..

~

Y+=5Y

10

o

TEMPERATURE C'C)

lOUT

./

~
£ 100
o

g350

!25,b=

..~1000

~ 5.01r--r~--+--+--+--+~

OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF TEMPERATURE

1

4

7

SUPPLY VOLTAGE (y+)

0319-8

0319-10

0319-9

INTERS1L'S SOLE AND EXCLUSIVE WARAANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTc: All typical values have been characterized but are not tested.

5-3

o

CD
CD

ICL7660

....

g TYPICAL PERFORMANCE CHARACTERISTICS
POWER CONVERSION EFFICIENCY
AS A FUNCTION OF OSC.
FREQUENCY

l'OO T -+25·V. I

I.. :
~

louT-15mA

~ ~

~
~

-

1\

~

8

O
..

?i

i"-o

I
I

90

V+

82
80
100

"

"a

..
~ '8

SV

lK
FREQUENCY lose (Hz)

10

10K

100
1000
Cose (pI)

v· = +5V

~ 2

o

-1

-4

"

. /I ' SLOPE 550

~o

60

ro ~ ~ ~ ~ 90

ro

\

40 '+

30~

/

TA""+25°C- 20 ~
= +5V
10 ~

y+

1,-

10
20
30
40
50
lOAD CURRENT IL (rnA)

90

~

m
50 ~

,/

,/

60

o

0 +25 +50 +75 +100 +125
TEMPERATURE ('C)

0319-14

TA

~ +2$'C

V+=2V

\

\

..1+1

~
g

\

~

\

)
./

0_1

~

0319-15

LOAD CURRENT !L(mA)

+2

..

70 "

1/

/
".

-25

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

80 !(

7

/

I-

~

r-....

6

~o

0319-13

90·~

r

~

0

II

"o -2
-3

l3

100 ..

"""'

I:

1

> 0

..........

0319-12

:

r-- iA = J25·b

10K

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT
5

y+ = +5V

u

0319-11

!:i

""

~ 12

~AIII+2n

+=+SV

osc.

.

18

~ 6~
M14
> 1

0

84

4

UNLOADED OSCILLATOR
FREQUENCY
AS A FUNCTION OF TEMPERATURE
"N 20

I

lOUT = 1 mA

92

(Circuit of Figure 3) (Continued)

FREQUENCY OF OSCILLATION AS
A FUNCTION OF EXTERNAL
OSC. CAPACITANCE

~
-2 .L'

V ...... lOPEI'~{

0123456
LOAD CURRENT IL (mA)
0319-16

SUPPLY CURRENT & POWER CONVERSION EFFICIENCY
AS A FUNCTION OF LOAD CURRENT

NOTE 4. These curves include in the supply current that current fed directly
into the load RL from Y+ (see Figure 3). Thus, approximately half the supply

20.0

~

li
~

90

8.0

'tI

through tile ICL7660, to the negative side of the load. Ideally, YOUT '" 2 YIN,

8

6.0

§

7

4.0

Is '" 2 IL, so YIN • Is '" YOUT· IL·

$

g

6

2.0

ll00

~50

.!
I

ao -

~

3

6.0

(J

2

4.0

1°0

o

~

o.o~

...
~ 40

..5

current goes directly to the positive side of the load, and the other half,

~

2.0

....

~

OmA
1.5
3.0
4.5
6.0
7.5
LOAD CURRENT IL (mAl

9.0

0319-17

INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHAll BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHAll BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vs/uss have been characterized but are not tested

5-4

ICL7660
IS v+
t------_--<--o(+5V)

------,

I,

I

:
I
I

-

I
I

RL

·casel
Dx

:::;::

,,-l4-,, '"

~VOUT
0319-19

Figure 4: Idealized Negative Voltage Converter

0319-18
NOTES: 1. For large values of Cosc (> 1000pF) the values of C,
and C2 should be Increased to 100f'F.
2. Dx is required for supply voltages greater than 6.SV @
-SS"C<:TA<:+7Il"C; refer to performance curves for

THEORETICAL POWER EFFICIENCY
CONSIDERATIONS

additional in1ormation.

In theory a voltage converter can approach 100% efficiency if certain conditions are met:
A
The drive circuitry consumes minimal power.
S
The output switches have extremely low ON resistance and virtually no offset.
C
The impedances of the pump and reservoir capacitors are negligible at the pump frequency.
The ICL7660 approaches these conditions for negative
voltage conversion if large values of C1 and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E=YzC1 (V12-V22)
where V1 and V2 are the voltages on C1 during the pump
and transfer cycles. If the impedances of C1 and C2 are
relatively high at the pump frequency (refer to Figure 4)
compared to the value of RL, there will be a substantial
difference in the voltages V1 and V2. Therefore it is not only
desirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly
large value for C1 in order to achieve maximum efficiency of
operation.

Figure 3: ICL7660 Test Circuit

DETAILED DESCRIPTION
The ICL7660 contains all the necessary circuitry to complete a negative voltage converter, with the exception of 2
external capacitors which may be inexpensive 10!£F polarized electrolytic types. The mode of operation of the device
may be best understood by considering Figure 4, which
shows an idealized negative voltage converter. Capacitor
C1 is charged to a voltage, V +, for the half cycle when
switches 51 and 53 are closed. (Note: 5witches 52 and 54
are open during this half cycle.) During the second half cycle of operation, switches 52 and 54 are closed, with 51 and
53 open, thereby shifting capacitor C1 negatively by V +
volts. Charge is then transferred from C1 to C2 such that the
voltage on C2 is exactly V+, assuming ideal switches and
no load on C2. The ICL7660 approaches this ideal situation
more closely than existing non-mechanical circuits.
In the ICL7660, the 4 switches of Figure 4 are M05 power switches; 51 is a P-channel device and 52, 53 & 54 are
N-channel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of 53 & 54
must always remain reverse biased with respect to their
sources, but not so much as to degrade their "ON" resistances. In addition, at circuit startup, and under output short
circuit conditions (VOUT=V+), the output voltage must be
sensed and the substrate bias adjusted accordingly. Failure
to accomplish this would result in high power losses and
probable device latchup.
This problem is eliminated in the ICL7660 by a logic network which senses the output voltage (VOUT) together with
the level translators, and switches the substrates of 53 & 54
to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7660 is an integral
part of the anti-Iatchup circuitry, however its inherent voltage drop can degrade operation at low voltages. Therefore,
to improve low voltage operation the "LV" pin should be
connected to GROUND, disabling the regulator. For supply
voltages greater than 3.5 volts the LV terminal must be left
open to insure latchup proof operation, and prevent device
damage.

DO'S AND DON'TS
1.
2.
3.

4.

5.
6.

Do not exceed maximum supply voltages.
Do not connect LV terminal to GROUND for supply
voltages greater than 3.5 volts.
Do not short circuit the output to V + supply for supply voltages above 5.5 volts for extended periods,
however, transient conditions including startup are
okay.
When using polarized capacitors, the + terminal of
C1 must be connected to pin 2 of the ICL7660 and
the + terminal of C2 must be connected to
GROUND.
Add diode Dx as shown in Figure 3 for high-voltage,
elevated temperature applications.
Add capacitor (- 0.1 !£F, disc) from pin 8 to ground
to limit rate of rise of input voltage to approximately
2V/!£s.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILrTY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typIcsl valUfJB hsvs b68n chat'llC'ltHiz6d but Nfl not tnttld.

5-5

~
~

ICL7660

...!=!....

'NOTE: 1. YOUT = -l(+ FOR
1.5Y:5 Y+:5 8.5V
2. YOUT = -(v+-Y,ox)
FOR 8.5 :5 v+ :5 10.0V

>---01,---.. . .

0 VOUT'

i10~F

0319-20

Figure 5: Simple Negative Converter

RL

0319-21

Figure 6: Paralleling Devices

V+

Ox

r-M-...,
h--<>VOUT'

L __ .J

.1. .• ~

X10~F

·NOTE· 1. VOUT = -nV+ FOR
-=+
1.5Y :5 V+ :5 8.5V
2. Your = -n(Y+-Wox) FOR
6.SV:5 V+ :5 10.0Y
0319-22

Figure 7: Cascading Devices for Increased Output Voltage

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

5-6

IIU~UI!:.

ICL7660
CONSIDERATIONS FOR HIGH
VOLTAGE & ELEVATED
TEMPERATURE

where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approx·
imately the weighted sum of the individual ICl7660 ROUT
values.

The ICl7660 will operate efficiently over its specified tem·
perature range with only 2 external passive components
(storage & pump capacitors), provided the operating supply
voltage does not exceed 6.5 volts at + 70°C and 5.0 volts at
+ 125°C. Exceeding these maximums at the temperatures
indicated may result in destructive latchup of the ICl7660.
(Ref: Graph "Operating Voltage Vs. Temperature")
Operation at supply voltages of up to 10.0 volts over the
full temperature range without danger of latchup can be
achieved by adding a general purpose diode in series with
the ICl7660 output, as shown by "Ox" in the circuit dia·
grams. The effect of this diode on overall circuit perform·
ance is the reduction of output voltage by one diode drop
(approximately 0.6 volts).

Changing the ICL7660 Oscillator
Frequency

~-I"---- 2000V
• Improved SCR Latchup Protection
• Simple Conversion of + SV Logic Supply to ± SV
Supplies
• Simple Voltage Multiplication VOUT=(-)nVIN
• Easy to Use-Requires Only 2 External
Non-Critical Passive Components
• Improved Direct Replacement for Industry-Standard
ICL7660 and Other Second-Source Devices

APPLICATIONS
• Simple Conversion of + SV to ± SV Supplies
• Voltage Multiplication VOUT = ±nVIN
• Negative Supplies for Data Acquisition Systems &
Instrumentation
• RS232 Power Supplies
• Supply Splitter, VOUT = ±Vs/2

ORDERING INFORMATION
Part Number

Temp. Range

Package

ICL766DSCBA

O'C to + 7D'C

8-PinSOIC

ICL766DSCPA

D'C to +70'C

8-Pin Minidip

ICL766DSIBA

D'C to +7D'C

8-PinSOIC

ICL7660SCTV

D'C to + 70'C

TO-99

ICL7660SIPA

- 25'C to + 85'C

8-Pin Minidip

ICL7660SITV

- 25'C to + 85'C

TO-99

ICL7660SMTV'

-55'C to + 125'C

TO-99

• Add 18838 to part number if 8838 processing is required.

0088-1

(BA)

0088-2

(TV)

0088-3

(PA)

Figure 1: Pin Configurations

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

302163-002

NOTE: All typical values have been characterized but are not tested

5-10

IfID~DIL

ICL7660S

NOTE: Stresses above thoss Hsted undBr "Absoluts Maximum Ratings"
may CBusa permanent dBfT18{J6 to the device. Thsss IU9 s/r9ss ratings only
and functionsl operation of the device at th9ss or any other oonditions
above thoss indicated in the operationsl sections of the specifications is not
Imp/ted. Exposure to sbsoIul9 maximum rating conditions for _ _ periods may affect device f9!lsbl1lty.

ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................. 13.0V
LV and OSC Input Voltage
(Note 1) .......... -0.3Vto(V+ + 0.3V)forV+<5.5V
............ (V+ - 5.5V)to(V+ + 0.3V) forV+ >5.5V
CurrentintoLV(Notel) ............. 20p.AforV+ > 3.5V
Output Short Duration (VSUPPLY ,;; 5.5V) ....... Continuous
Power Dissipation (Note 2)
ICL7660SCTV ..........••...•....•.....•...• 500 mW
ICL7660SCPA .............................. 300 mW
ICL7660SCBA .•.••.....•..............•.... 300 mW
ICL7660SITV ............................... 500 mW
ICL7660SIPA ............................... 300 mW
ICL7660SIBA ............................... 300 mW
ICL7660SMTV .............................. 500 mW
Operating Temperature Range
ICL7660SM ........................ - 55·C to + 125·C
ICL7660SI .......................... -25·C to +85·C
ICL7660SC ............................ OOC to + 70·C
Storage Temperature Range ........... - 65·C to + 1500C
Lead Temperature
(Soldering, 10 sec) ............................. 300·C

BOOST

r---------O CAp•
r------OCAP-

VOUT

0088-4

Figure 2: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANlY ARTICLE OF THE CONDITION OF SALE.
THE WARRANlY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILllY AND FITNESS FOR A PARTICULAR USE.

5-11

CII
CII

a

•

~--------~----~~~---.--------------o~

NOTE: AN typical vsIues haIlS bHn charsctsrfzed but IUfJ not tested.

P
...

ICL7660S
~
U)
U)

.......

ELECTRICAL CHARACTERISTICS

g v+

= 5V, TA = 25'C, OSC = Free running, Test Circuit Figure 3 (unless otherwise specified)

Symbol

Parameter

Limits

Test Conditions
Min

1+

Units

Typ

Max

80

160
180
180
200

p.A

Supply Current
(Note 3)

RL =

V~

Supply Voltage Range-HI
(Note 4)

RL =10K, LV Open
Tmin

"'0
"'0:

90
88

""

86

0:

84

3
...J

82

U

80
100

Vl

0

1k

50k

10k

10
8

7

IIII III

\

UNLOADED OSCILLATOR
FREQUENCY
AS A FUNCTION OF TEMPERATURE

'N'

20

'"en
U

18

""t;

16

\

...::>

14

\

e:

12

:I:

V+=5V II
TA= 25°C

0

z

5
4

3
2
1
0
1

8
0:

3

'\

...J

U

Vl

0

10

100

1K

\

/~V+=10V

'" "<

,V+= 5V

~

10

/-----

r--z

8
-50 -25

0

25

------

50

-----

-

75 100 125

TEMPERATURE (OC)

OSC FREQUENCY FOS C(Hz)
0088-9

0088-8

0088-10

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: All typical values hav6 been characterized but ar6 not tested

5-13

•

! ICL7660S

.D~DlL

co
co

!:i

TYPICAL PERFORMANCE CHARACTERISTICS

S:!

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

£
!oJ

r-....

0

"

-1

0

-2

>

...::>
::>
0

-3

-5

/""

.,..
./

-4

o

/

V
/

10

20

T.= 2500

1/

V·=5
TA= 250 C

~=5V

-

/
10

40

30

20

30

40

50

70
60
50
40
30
20
1o

60

~=2V
TA = 2500

E:...

1

80

~
~

II-

1/

[>0..,.

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

100
90

~

;5
...J

(Circuit of Figure 3) (Continued)

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

1

'">!

~

...J

o

g

'"'"
II

l-

::>

.

i!:
::>

~

1

0

::>

~~

III

-2

o

o

./

)

2 3 4 5 6 7 8 9
LOAD CURRENT(mA)

LOAD CURRENT(mA)-

LOAD CURRENT (mA) -

~

....
~

0088-13

0088-12

0088-11

OUTPUT SOURCE RESISTANCE
AS A FUNCTION OF
OSCILLATOR FREQUENCY

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

g

100

~

90

~

80

~

t:;
z
o

iii

~

..........
'I-.

70
60
50

-

~
V·=2V
TA=250 C

40

.....
/

16.0
14.0

~

><...

12.0
10.0

.......

8.0

/

30
20

6.0
4.0

/

10

o/
o

1:
...z
'"::>'"u

3

4.5

6

7.5

z

300

~

..

'"::>

~

i!:
::>

::>

III

';2.OC

T. -5V

1\ 1=1

10mA

II

~:I=~~j~~

!U~2= ~oIJF

C

200

I-

1'\

'\

100

i\

0

2.0
0

1.5

400

...u

I-

~

s:","

o Cl =~=100J.&f'
100

9

lK

10K

lOOK

OSCILLATOR fREQUENCY (Hz)

LOAD cURRENT(mA)

0088-15

0088-14

NOTE 4: These curves include in the supply current that current fed directly into the load RL from V + (see Figure 3). Thus, approximately half the supply current
goes directly to the positive side of the load, and the other half, through the ICL7660S, to the negative side of the load. Ideally, VOUT '" 2 Y,N, Is '" 21lo
so Y,N • Is '" VOUT· 'L.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been chsracterizsd but 819 not tssted.

5-14

ICL7660S
IS

y+

181-----_-+-o (+5V)

0088-16

NOTE 1: For large values of COSC (> 1000pF) the values of Cl and
C2 should be increased to 100f'F.

0088-17

Figure 4: Idealized Negative Voltage Converter

Figure 3: ICL7660S Test Circuit

THEORETICAL POWER EFFICIENCY
CONSIDERATIONS

DETAILED DESCRIPTION
The ICl76608 contains all the necessary circuitry to complete a negative voltage converter, with the exception of 2
external capacitors which may be inexpensive 10"F polarized electrolytic types. The mode of operation of the device
may be best understood by considering Figure 4, which
shows an idealized negative voltage converter. Capacitor
C1 is charged to a voltage, V+, for the half cycle when
switches 81 and 83 are closed. (Note: 8witches 82 and 84
are open during this half cycle.) During the second half cycle of operation, switches 82 and 84 are closed, with 81 and
83 open, thereby shifting capacitor C1 negatively by V+
volts. Charge is then transferred from Cl to C2 such that the
voltage on C2 is exactly V + , assuming ideal switches and
no load on C2. The ICl76608 approaches this ideal situation more closely than existing non-mechanical circuits.
In the ICl76608, the 4 switches of Figure 4 are M08
power switches; 81 is a P-channel device and 82, 83 & 84
are N-channel devices. The main difficulty with this approach is that in integrating the switches, the substrates of
83 & 84 must always remain reverse biased with respect to
their sources, but not so much as to degrade their "ON"
resistances. In addition, at circuit startup, and under output
short circuit conditions (VOUT=V+), the output voltage
must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power
losses and probable device latchup.
This problem is eliminated in the ICl76608 by a logic network which senses the output voltage (VOUT) together with
the level translators, and switches the substrates of 83 & 84
to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICl76608 is an integral part of the anti-Iatchup circuitry, however its inherent
voltage drop can degrade operation at low voltages. Therefore, to improve low voltage operation the "lV" pin should
be connected to GROUND, disabling the regulator. For supply voltages greater than 3.5 volts the lV terminal must be
left open to insure latchup proof operation, and prevent device damage.

In theory a voltage converter can approach 100% efficiency if certain conditions are met:
A
The drive circuitry consumes minimal power.
S
The output switches have extremely low ON resistance and virtually no offset.
C
The impedances of the pump and reservoir capacitors are negligible at the pump frequency.
The ICl76608 approaches these conditions for negative
voltage conversion if large values of C1 and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E= % C1 (V12-V22)
where V1 and V2 are the voltages on C1 during the pump
and transfer cycles. If the impedances of C1 and C2 are
relatively high at the pump frequency (refer to Figure 4)
compared to the value of RL, there will be a substantial
difference in the voltages V1 and V2. Therefore it is not only
deSirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly
large value for C1 in order to achieve maximum efficiency of
operation.

DO'S AND DON'TS
1. Do not exceed maximum supply voltages.
2. Do not connect lV terminal to GROUND for supply voltages greater than 3.5 volts.
3. Do not short circuit the output to V+ supply for supply
voltages above 5.5 volts for extended periods, however,
transient conditions including startup are okay.
4. When using polarized capacitors, the + terminal of C1
must be connected to pin 2 of the ICl76608 and the +
terminal of C2 must be connected to GROUND.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABiLiTY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

5-15

!o

ICL7660S

o

....

..I

g

1.-_...._-0 VOUT'

.:c1 0 J.LF
0088-18

'NOTE 1: VOUT

=

-V+ for 1.SV'; V+ ,; 12V.

Figure 5: Simple Negative Converter

0088-19

Figure 6: Paralleling Devices

0088-20

'NOTE 1: VOUT = -nV+ for 1.SV ,; V+ ,; 12V.

Figure 7: Cascading Devices for Increased Output Voltage

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTe: All typical values have been characterized but are not tested.

5-16

tI1D~DI!:. C;

ICL7660S

I'"

....

Increasing the oscillator frequency can also be achieved
by overdriving the oscillator from an external clock, as
shown in Figure 8. In order to prevent device latchup, a
100 kO resistor must be used in series with the clock output. In a situation where the designer has generated the
external clock frequency using TTL logic, the addition of a
10 kO pullup resistor to V + supply is required. Note that the
pump frequency with external clocking, as with internal
clocking, will be % of the clock frequency. Output transitions occur on the positive-going edge of the clock.

TYPICAL APPLICATIONS
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660S for generation of negative supply voltages. Figure
5 shows typical connections to provide a negative supply
where a positive supply of + 1.5V to + 12V is available.
Keep in mind that pin 6 (LV) is tied to the supply negative
(GND) for supply voltages below 3.5 volts.
The output characteristics of the circuit in Figure 5 are
those of a nearly ideal voltage source in series with 55
ohms. Thus for a load current of -10mA and a supply voltage of + 5 volts, the output voltage will be -4.3 volts. The
dynamic output impedance due to the capacitor impedances is approximately 1/CIlC, where:
C=Cl=C2

CMOS

GATE

.
.
1
1
which gives -C =
f
5 '" 3 ohms
CIl
21T PUMpX10for C= 10",F and fpUMP=5kHz

~S~---'----~OVOUT

(% of oscillator frequency)

: [ ,10 .u F

Paralleling Devices
Any number of ICL7660S voltage converters may be paralleled to reduce output resistance. The reservoir capacitor,
C2, serves all devices while each device requires its own
pump capacitor, Cl' The resultant output resistance would
be approximately:

0088-21

Figure 8: External Clocking
It is also possible to increase the conversion efficiency of
the ICL7660S at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 9. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (Cl) and reservoir (C2) capacitors; this is overcome
by increasing the values of Cl and C2 by the same factor
that the frequency has been reduced. For example, the addition of a 1OOpF capacitor between pin 7 (Osc) and V + will
lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and thereby necessitate
a corresponding increase in the value of Cl and C2 (from
10",F to 100",F).

R
= ROUT (of ICL7660S)
OUT n (number of devices)

Cascading Devices
The ICL7660S may be cascaded as shown to produce
larger negative multiplication of the initial supply voltage.
However, due to the finite efficiency of each device, the
practical limit is 10 devices for light loads. The output voltage is defined by:
VOUT= -n (VIN),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7660S ROUT
values.

Cosc

Changing the ICL7660S Oscillator
Frequency
It may be desirable in some applications, due to noise or
other considerations, to alter the oscillator frequency. This
can be achieved simply by one of several methods described below.
By connecting the Boost Pin (Pin 1) to V + , the oscillator
charge and discharge current is increased and, hence, the
oscillator frequency is increased by approximately 3%
times. The result is a decrease in the output impedance and
ripple. This is of major importance for surface-mount applications where capacitor size and cost are critical. Smaller
capacitors, e.g. 0.1 ",F, can be used in conjunction with the
Boost Pin in order to achieve similar output currents compared to the device free running with Cl = C2 = 10 ",F or
100 ",F. (Refer to graph of Output Source Resistance as a
Function of Oscillator Frequency).

sl--1I---oVOUT

0088-22

Figure 9: Lowering Oscillator Frequency

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical valut:Js have been characterized but are not test6(/.

5-17

GI
GI

~

~

cg
cg

.D~DI!..

ICL7660S

...S!....
Vour =
2V+- 2V F

.-+--......--oVOUT =-VIN

0088-23

NOTE: D1 & D2 can be any suHable diode.

0088-24

Figure 10: Positive Voltage Doubler

Figure 11: Combined Negative Voltage
Converter and Positive Doubler

Positive Voltage Doubling

Voltage Splitting

The ICL7660S may be employed to achieve positive voltage doubling using the circuit shown in Figure 10. In this
application, the pump inverter switches of the ICL7660S are
used to charge C1 to a voltage level of V+ -VF (where V+
is the supply voltage and VF is the forward voltage drop of
diode 01). On the transfer cycle, the voltage on C1 plus the
supply voltage (V+) is applied through diode 02 to capacitor C2. The voltage thus created on C2 becomes
(2V+)-(2VF) or twice the supply voltage minus the combined forward voltage drops of diodes 01 and 02.
The source impedance of the output (VOUT) will depend
on the output current, but for V + = 5 volts and an output
current of 10mA it will be approximately 60 ohms.

The bidirectional characteristics can also be used to split
a higher supply in half, as shown in Figure 12. The combined load will be evenly shared between the two sides, and
a high value resistor to the LV pin ensures start-up. Because the switches share the load in parallel, the output
impedance is much lower than in the standard circuits, and
higher currents can be drawn from the device. By using this
circuit, and then the circuit of Figure 7, + 15V can be converted (via +7.5, and -7.5) to a nominal -15V, although
with rather high series output resistance (- 250.0.).

,-~~------"""--------'-V+

Combined Negative Voltage Conversion
and Positive Supply Doubling
Figure 11 combines the functions shown in Figures 5 and
10 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for
example, suitable for generating +9 volts and -5 volts
from an existing + 5 volt supply. In this instance capacitors
C1 and C3 perform the pump and reservoir functions respectively for the generation of the negative voltage, while
capacitors C2 and C4 are pump and reservoir respectively
for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will
be somewhat higher due to the finite impedance of the
common charge pump driver at pin 2 of the device.

v+-v-

+

VOUT = - -

2

50}'F

~~~----------+-------------4-~
0088-25

Figure 12: Splitting A Supply In Half

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicIJ/ values havtllHKm chsractsriz9d but BM not ffttsd.

5-18

ICL7660S
date the 7660S, while maintaining adequate feedback. An
increase in pump and storage capacitors is desirable, and
the values shown provides an output impedance of less
than 50. to a load of 10mA.

Regulated Negative Voltage Supply
In some cases, the output impedance of the ICL7660S
can be a problem, particularly if the load current varies substantially. The circuit of Figure 13 can be used to overcome
this by controlling the input voltage, via an ICL7611 lowpower CMOS op amp, in such a way as to maintain a nearly
constant output voltage. Direct feedback is inadvisable,
since the ICL7660S's output does not respond instantaneously to change in input, but only after the switching delay. The circuit shown supplies enough delay to accommo+BV

OTHER APPLICATIONS
Further information on the operation and use of the
ICL7660S may be found in A051 "Principals and Applications of the ICL7660 CMOS Voltage Converter".

50k

56k
50k

+
lOOk

VOUT

BOOk

250k
VOLTAGE
ADJUST

•

0088-26

Figure 13: Regulating the Output Voltage

+5V LOGIC SUPPLY

12
TTL DATA
INPUT

11

16
",-+~-oRS232 DATA

OUTPUT

+5V n
- 5V I

n

L-...J L..
0088-27

Figure 14: RS232 Levels From A Single 5V Supply

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGAnON WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical valUflS have been charscftHlz8d but are not t9sted.

5-19

:ICL7662

~ CMOS Voltage Converter
~ GENERAL DESCRIPTION

FEATURES

The Intersil ICL7662 is a monolithic high-voltage CMOS
power supply circuit which offers unique performance advantages over previously available devices. The ICL7662
performs supply voltage conversion from positive to negative for an input range of + 4.5V to + 20.0V, resulting in
complementary output voltages of -4.5V to -20V. Only 2
non-critical external capacitors are needed for the charge
pump and charge reservoir functions. The ICL7662 can also
function as a voltage doubler, and will generate output voltages up to + 38.6V with a + 20V input.
Contained on chip are a series DC power supply regulator, RC oscillator, voltage level translator, four output power
MOS switches. A unique logic element senses the most
negative voltage in the device and ensures that the output
N-channel switch source-substrate junctions are not forward biased. This assures latchup free operation.
The oscillator, when unloaded, oscillates at a nominal frequency of 10kHz for an input supply voltage of 15.0 volts.
This frequency can be lowered by the addition of an external capacitor to the "OSC" terminal, or the oscillator may
be overdriven by an external clock.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV) operation. At medium to high voltages (+10 to +20Vl, the LV
pin is left floating to prevent device latchup.

• No External Diode Needed OVer Entire Temperature
Range
• Pin Compatible With ICL7660
• Simple Conversion of + 15V Supply to -15V Supply
• Simple Voltage Multiplication (VOUT=(-) nVIN)
• 99.9% Typical Open Circuit Voltage Conversion
Efficiency
• 96% Typical Power Efficiency
• Wide Operating Voltage Range 4.5V to 20_0V
• Easy to Use - Requires Only 2 External Non-Crltlcal
Passive Components

APPLICATIONS
• On Board Negative Supply for Dynamic RAMs
• Localized ",-Processor (8080 Type) Negative
Supplies
• Inexpensive Negative Supplies
• Data Acquisition Systems
• Up to - 20V for Op Amps

v+

ORDERING INFORMATION
Part Number

GROUND

Temperature Range

Package

ICL7662CTV

O·Cto +70·C

TO-99

ICL7662CPA

O·Cto +70"C

8 PIN MINI DIP

ICL7662MTV*

-55·Cto + 125·C

0320-1

(outline dwg PAl
0320-2

TO-99

(outline dwg TV)

Figure 1: Pin Configurations

• Add 1883B 10 Part Number for 883B Processing.

r-----------~------------~------_r----------------__ov+

..----------------0 CAP +
, - - - - - - - . g CAP-

vour

0320-3

Figure 2: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE ODNDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
302064-004
NOTE: AU typical vsIues havs bHn chsracterlZBd but BffI not testBd.

5-20

ICL7662
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................... 22V
Oscillator Input Voltage (Note 1) ....................... .
-0.3V to (V+ +0.3V) forV+ <10V
(V+ -10V) to (V+ +0.3V) forV+ >10V
Current into LV (Note 1) .............. 20fLA for V+ > 10V
Output Short Duration ...................... Continuous

Power Dissipation (Note 2)
ICL7662CTY ............................... 500mW
ICL7662CPA ............................... 300mW
ICL7662MTY ............................... 500mW
Lead Temperature (Soldering, 1Osee) ............. 300'C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

v+ = 15V, TA = 25'C, Cosc = 0, unless otherwise stated. Test Circuit

Figure 3.
Symbol

Parameter

Limits

Test Conditions
Min

Typ

Units
Max

V+L
V+H

Supply Voltage Range-Lo
Supply Voltage Range-Hi

RL = 10kn, LV=GND
RL = 10kn, LV=Open

Min
0

./
V

.....-

-- -- --

V

70
60

5.
-55

+25

-20

'R" 11

l:

~

Z
UI
:>

9
•

lil

7

~

5

5

a
fl

/

65

/

V

/

I
II

3

4

350

300

25.

0

c

....
....

."

C

200

,J R,

150

'"~
~

Z
0
m

~

50

,K

Fosc(Hz)

,.K

100K

FREQUENCY OF OSCILLATION
AS A FUNCTION OF EXTERNAL
OSC. CAPACITANCE

10K

---

V+ - 15V

N'

TA = +25 ·C

:5-

RL =

>
z

(J

'LV= OPEN

00

I

w lK
:::>
aw

II:
LL

II:

0

~

2
2

0320-5

0320-7

V
1

9 10 11 12 13 14 15 16 17 18 19 20

0320-6

/

3

8

100

100

V

4

7

+12S

+7.

LV = GND /

6

""-

17

/

Ii: •

5

V+ = S~~
I = 3MA
fA
~2S0C

OSCILLATOR FREQUENCY
vs SUPPLY VOLTAGE
RL = 00
Cosc = 0
TA = +2SoC

4

EFII

-V+ = SV
IL = 3mA

TEMPERATURE (Oc)

.. ,.

3

P

-

./

80

2

POWER CONVERSION EFFICIENCY
AND OUTPUT SOURCE RESISTANCE
AS A FUNCTION OF OSCILLATOR
FREQUENCY

./

110

OO

1

i

./

130

100

100

/V+ = 1SV I---IL = 20mA -

./

- +-

IJ

V+ (VOLTS)

/'

18.
17.
(J

o

0320-4

OUTPUT SOURCE RESISTANCE AS
A FUNCTION OF TEMPERATURE

§

r;;:
LV = OPEN

40

10 11 12 13 14 15 16 17 18 19 00

160

I'.:

70

30

1

r-....

90

eo

50

LV = OPEN

40

LV = ~~D

11.

60

t-i-

)

,. o

100

S
0

T"'::-"

130

12.

t-

\

140

j!!

:::l
0-

~

1\

150

II:

~

1\

11.

lTA = +2soclCosc = 0
I-

17.

\

~140
W 130

Z

~:lm1'

160

180

17.

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

~

100

--'

(j

SUPPLY VOLTAGE (V)

f:l

0320-8

10

1

10

100

Cosc(pF)

1000

10K

0320-9

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHEA WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

5-22

ICL7662
TYPICAL PERFORMANCE CHARACTERISTICS
UNLOADED OSCILLATOR FREQUENCY
AS A FUNCTION OF TEMPERATURE

15K

." 14K

;;
~

12K

15::>
fir
II:

10K

II:

'K

~

BK

"0

~0

"-

13K

11K

<:.
...........
............

7K

............

BK
5K
--20

-55

en

ot:i
...........

+25

~

TEMPERATURE ('C)

--

-4

-5

-7

-8

>

-10

-

......

-9

.....

-11

....
S
-12

I-""

..... 1-""

....

....

-13
-14

0320-10

--

-6

~

~

I I
V+ = 15V
TA = +25°C
LV = OPEN

-3

W

6

+125

+70

OUTPUT VOLTAGE AS A
FUNCTION OF LOAD CURRENT

-1

V+ = 15V
COSC = 0

'" "

(See Test Circuit of Figure 3) (Continued)

SLOPE = 650

~

-15

10

20

30

40

50

60

70

80

90

100

LOAD CURRENT IL (mA)
0320-11

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

OUTPUT VOLTAGE AS A
FUNCTION OF LOAD CURRENT

I

100

I
C- V+ 1=1 15V

t

c- TA = +25°C
- LV = GND

~
~

~

~

g

....::>
I!:::>
0

-1

.....

-3

......

"""I-""

"""SLOPE

-4

1

2

= 1400

I

.... 103

4

5

6

7

8

"

i

85

W

""

I I

9 10 11 12 13 14 15 16 17 18 19 00

i'

!!!

~

I"

-2

-5

V+ = 5V
TA = +25°C c-

z

w

CI

r-...

os



~

20

FosclKHZ)

V+ = 15V eTA = +25°Cc-

.....

g
ill

24

LOAD CURRENT IL (mA)

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

I'

!(

38
2

......

0320-12

r.::..

o ~

1

LOAD CURRENT "(mA)

lDO

4

32

L.-'

80

8

L.-'

V

V

./

LV = OPEN_r-

V
/

lDO

LOAD CURRENT IL (rnA)
1

0320-14

2

3

4

5

6

7

8

9 10 11 12 13 14 15 18 17 18 19 20

v+

(VOLTS)

0320-15
INTERSIL'S SOLE AND EXCLUSIVE WARAANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

5-23

: ICL7662

......

II)

This problem is eliminated in the ICL7662 by a logic net~
work which senses the output voltage (VOUT) together with
the level translators, and switches the substrates of 83 & 84
to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7662 is an integral
part of the anti-Iatchup circuitry, however its inherent voltage drop can degrade operation at low voltages. Therefore,
to improve low voltage operation the "LV" pin should be
connected to GROUND, disabling the regulator. For supply
voltages greater than 11 volts the LV terminal must be left
open to insure latchup proof operation, and prevent device
damage.

TYPICAL PERFORMANCE
~ CHARACTERISTICS
(See Test Circuit of Figure 3) (Continued)

150

130

-v+
~ W
-RL =

120

- TA = +25OC

140

1.

'+

SUPPLY CURRENT AS A FUNCTION OF
OSCILLATOR FREQUENCY
II

00

i ::..

!

G

~

so
70

LOAD CURRENT IL (mAl

!!; so
11)

..

IS

50

V+

rat-------,......c-o(+ 5V

V

30

20
10
10

100

1K

10K

Gl

OSCILLATOR FREQUENCY

0320-16

·Cosc i

?

NOTE 4.

Note that these curves include in the supply current that current fed directly
into the load RL from V+ (see Figure 3). Thus, approximately half the supply
current goes directly to the positive side of the load, and the other half,
through the ICL7662, to the negative side of the load. Ideally, VLOAD ..
2VIN, Is '" 2 IL' so VIN • Is '" VLOAD· IL

PVO

UT

0320-17
NOTE: For large value of Cose (> 1000pf) the values of C, and C2
should be increased to 100f'F.

CIRCUIT DESCRIPTION
The ICL7662 contains all the necessary circuitry to complete a negative voltage converter, with the exception of 2
external capacitors which may be inexpensive 1OI'-F polarized electrolytic capacitors. The mode of operation of the
device may be best understood by considering Figure 4,
which shows an idealized negative voltage converter. CapaCitor C, is charged to a voltage, V + , for the half cycle
when switches 8, and 83 are closed. (Note: 8witches 82
and 84 are open during this half cycle.) During the second
half cycle of operation, switches 82 and S4 are closed, with
8, and 83 open, thereby shifting capaCitor C, negatively by
V + volts. Charge is then transferred from C, to C2 such
that the voltage on C2 is exactly V +, assuming ideal
switches and no load on C2. The ICL7662 approaches this
ideal situation more closely than existing non-mechanical
circuits.
In the ICL7662, the 4 switches of Figure 4 are MOS power switches; 8, is a P-channel device and 82, 83 & 84 are
N·channel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of 83 & 84
must always remain reverse biased with respect to their
sources, but not so much as to degrade their "ON" resistances. In addition, at circuit startup, and under output short
circuit conditions (VOUT=V+), the output voltage must be
sensed and the substrate bias adjusted accordingly. Failure
to accomplish this would result in high power losses and
probable device latchup.

Figure 3: ICL7662 Test Circuit

0320-18

Figure 4: Idealized Negative Converter

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPAESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values havs been charact9lizsd but are not tested.

5-24

ICL7662
THEORETICAL POWER EFFICIENCY
CONSIDERATIONS

TYPICAL APPLICATIONS
Simple Negative Voltage Converter

In theory a voltage multiplier can approach 100% efficiency if certain conditions are met:
A
The drive circuitry consumes minimal power
B
The output switches have extremely low ON resistance and virtually no offset.
The impedances of the pump and reservoir capacitors are negligible at the pump frequency.
The ICL7662 approaches these conditions for negative
voltage multiplication if large values of C1 and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E=%C1 (V12-V22)
where V1 and V2 are the voltages on C1 during the pump
and transfer cycles. If the impedances of C1 and C2 are
relatively high at the pump frequency (refer to Figure 4)
compared to the value of RL, there will be a substantial
difference in the voltages V1 and V2. Therefore it is not only
desirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly
large value for C1 in order to achieve maximum efficiency of
operation.

The majority of applications will undoubtedly utilize the
ICL7662 for generation of negative supply voltages. Figure
5 shows typical connections to provide a negative supply
where a positive supply of + 4.5V to 20.0V is available.
Keep in mind that pin 6 (LV) is tied to the supply negative
(GND) for supply voltages below 11 volts.
The output characteristics of the circuit in Figure 5 are
those of a nearly ideal voltage source in series with 65
ohms. Thus for a load current of -10mA and a supply voltage of + 15 volts, the output voltage will be 14.35 volts. The
dynamic output impedance due to the capaCitor impedances is approximately 1/roC, where:

e

C=C1=C2

.

3.

1

1

which gives - =
f
0 5 = 3 ohms
roC 27T pumpx 1 for C = 10 ",F and fpump = 5kHz (% of oscillator frequency)

Paralleling Devices
Any number of ICL7662 voltage converters may be paralleled to reduce output resistance. The reservoir capaCitor,
C2, serves all devices while each device requires its own
pump capacitor, C1. The resultant output resistance would
be approximately
ROUT (of ICL7662)
ROUT n (number of devices)

DO'S AND DON'TS
1.
2.

.

Do not exceed maximum supply voltages.
Do not connect LV terminal to GROUND for supply
voltages greater than 11 volts.
When using polarized capacitors, the + terminal of
C1 must be connected to pin 2 of the ICL7662 and
the + terminal of C2 must be connected to
GROUND.

Cascading Devices
The ICL7662 may be cascaded as shown to produce larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical
limit is 10 devices for light loads. The output voltage is defined by:
VOUT= -n (VIN),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7662 ROUT
values.

,..--------_---0

YOUT

=-

y+

--,
~

51-----'
0320-19

Figure 5: Simple Negative Converter

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE' All typical values have been characterized but are not tested

5-25

•

.,...= ICL7662
g

0320-20

Figure 6: Paralleling Devices
v+

1 - - - - - - r - o O VOUT

:Ii 10~F
0320-21

Figure 7: Cascading Devices for Increased Output Voltage
Y+

It is also possible to increase the conversion efficiency of
the ICL7662 at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is
achieved by connecting an additional capacitor, Cosc, as
shown in Figure 9. However, lowering the oscillator frequency will cause an undesirable increase in the impedance of
the pump (Cl) and reservoir (C2) capacitors; this is overcome by increasing the values of C, and C2 by the same
factor that the frequency has been reduced. For example,
the addition of a 100pF capacitor between pin 7 (Osc) and
V+ will lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and thereby necessitate a corresponding increase in the value of C, and
C2 (from 10ll-F to 100ll-F).

Y+

lOOk

CMOS
ClATE

1 - - - - - - - - , - - - - < l Y OUT

0320-22

Figure 8: External Clocking

Changing the ICL7662 Oscillator
Frequency

V+

It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an external clock, as shown in Figure 8. In order to prevent possible
device latchup, a 1OOkO resistor must be used in series with
the clock output. In the situation where the designer has
generated the external clock frequency using TTL logic, the
addition of a 10kO pullup resistor to V+ supply is required.
Note that the pump frequency with external clocking, as
with internal clocking, will be Yz of the clock frequency. Output transitions occur on the positive-going edge of the
clock.

ICL7662

Cose

t------~---o

VO UT

0320-23

Figure 9: Lowering Oscillator Frequency

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typIcsJ vaJuss have bHn charscfBrlzed but 8rB not fBsted.

5-26

ICL7662
Positive Voltage Doubling

Voltage Splitting

The ICL7662 may be employed to achieve positive voltage doubling using the circuit shown in Figure 10. In this
application, the pump inverter switches of the ICL7662 are
used to charge C, to a vOltage level of V+ -VF (where V+
is the supply voltage and VF is the forward voltage drop of
diode D,). On the transfer cycle, the voltage on C, plus the
supply voltage (V +) is applied through diode D2 to capacitor C2. The voltage thus created on C2 becomes
(2V+)-(2VF) or twice the supply voltage minus the combined forward voltage drops of diodes D, and D2.
The source impedance of the output (VOUT) will depend
on the output current, but for V + = 15 volts and an output
current of 10mA it will be approximately 70 ohms.

The bidirectional characteristics can also be used to split
a higher supply in half, as shown in Figure 12. The combined load will be evenly shared between the two sides and,
a high value resistor to the LV pin ensures start-up. Because the switches share the load in parallel, the output
impedance is much lower than in the standard circuits, and
higher currents can be drawn from the device. By using this
circuit, and then the circuit of Figure 7, + 30V can be converted (via + 15V, and -15V) to a nominal -30V, although
with rather high series output resistance (- 2500).

v+

y+

L---~~~-1-v0320-26

Figure 12: Splitting A Supply in Half
NOTE:
01 " D2 CAN BE ANV
SUITABLE DIODE

Regulated Negative Voltage Supply
In some cases, the output impedance of the ICL7662 can
be a problem, particularly if the load current varies substantially. The circuit of Figure 13 can be used to overcome this
by controlling the input voltage, via an ICL7611 low-power
CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since
the ICL7662's output does not respond instantaneously to a
change in input, but only after the switching delay. The circuit shown supplies enough delay to accommodate the
7662, while maintaining adequate feedback. An increase in
pump and storage capacitors is desirable, and the values
shown provides an output impedance of less than 50 to a
load of 10mA.

0320-24

Figure 10: Positive Voltage Doubler

Combined Negative Voltage Conversion
and Positive Supply Doubling
Figure 11 combines the functions shown in Figures 5 and
10 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for
example, suitable for generating + 9 volts and - 5 volts
from an existing + 5 volt supply. In this instance capacitors
C, and Cs perform the pump and reservoir functions respectively for the generation of the negative voltage, while
capacitors C2 and C4 are pump and reservoir respectively
for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will
be somewhat higher due to the finite impedance of the
common charge pump driver at pin 2 of the device.

-....
SOl<

....

ICL8089

0320-27

Figure 13: Regulating the Output Voltage

OTHER APPLICATIONS

0320-25

Further information on the operation and use of the
ICL7662 may be found in A051 "Principals and Applications
of the ICL7660 CMOS Voltage Converter".

Figure 11: Combined Negative Converter
and Positive Doubler

lNTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPAESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characten'zed but are not tested.

5-27

D~DIb

:: ICL7663

~ CMOS Programmable
!:! Micropower Voltage Regulators
GENERAL DESCRIPTION

FEATURES

The ICL7663 positive voltage regulator is a low-power,
high-efficiency device which accepts inputs from 1.6V to
l6V and provides adjustable outputs over the same range
at currents up to 40mA. Operating current is typically less
than 4p.A, regardless of load.
Output current sensing and remote shutdown are available, providing protection for the regulator and the circuits it
powers. A unique feature is a negative temperature coefficient output. This can be used, for example, to efficiently
tailor the voltage applied to a multiplexed LCD through the
driver e.g., ICM7231/2/3 so as to extend the display operating temperature range many times.
An enhanced direct replacement for this part called
ICL7663S is now available and is more appropriate for new
designs.
The ICL7663 is available in 8-pin plastic, TO-99 can,
CERDIP, and SOIC packages.

• Ideal for Battery·Operated Systems: Less Than 4p.A
Typical Current Drain
• Will Handle Input Voltages From 1.6V to l6V
• Very Low Input·Output Differential Voltage
• 1.3V Bandgap Voltage Reference
• Up to 40mA Output Current
• Output Shutdown Via Current·Llmlt Sensing or
External Logic Signal
• Output Voltages Programmable From 1.3V to l6V
• Output Voltages With Programmable Negative
Temperature Coefficients

ORDERING INFORMATION
Positive Regulator
Part Number
ICL7663CBA
ICL7663CPA
ICL7663CJA
ICL7663CTV

Temperature Range
O°C to
O°C to
O°Cto
O°C to

+ 70°C
+ 70°C
+ 70°C
+ 70°C

+

Y,N

Package
8-LeadSOIC
8-Lead MiniDIP
8-Lead CERDIP
8-Lead TO-99

0..:.-_. . . ,.
8

r-+---+--------oVOUT1
L......W_t-------'O"OVOUT2

,~-------_'<>SENSE

Vl------------__''<> VSET

>-.....-=-OVTC
'---11---+---------=.0 SHUTDOWN
o-----~~-~-------~GND

0321-1

ICL7663
Figure 1: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE'IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typ;caf values haV9 been characterized but are not tssted.

5-28

ICL7663
ABSOLUTE MAXIMUM RATINGS, ICL7663 POSITIVE REGULATOR
Input Supply Voltage ... . . . . . . . . . . . . . . . . . . . . . . . .. + 18V
Any Input or Output Voltage (Note 1) (Terminals 1, 2, 3,
5,6,7) ................ (GND -O.3V) to (V+IN +O.3V)
Output Source Current
(Terminal 2) ........•......................... 50mA
(Terminal 3) .................................. 25mA

Output Sinking Current (Terminal 7) ............. -10mA
Power Dissipation (Note 2)
MiniDIP ........................•........... 200mW
TO-99 Can ................................. 300mW
Operating Temperature Range ............ O'C to + 70'C
Storage Temperature ................ - 65'C to + 150'C
Lead Temperature (Soldering, 1Osee) ............. 300'C

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operationsl sections of the speclficstions is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliabIlity.
NOTE:

ICL7663 Positive Regulator
SENSE
VOUT2
VOUT1
GROUND

0321-4

GROUND

0321-3

(outline dwg PA, JA)

(outline dwg TV)
Figure 2: Pin Configurations

(outline dwg BA)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

5-29

•

C")

U)
U)

.......
2

ICL7663
ICL7663 ELECTRICAL CHARACTERISTICS
VIN+ =9V, VOUT=5V, TA = + 25'C, unless otherwise specified. See Test Circuit Figure 3.

Symbol

Parameter

Limits

Test Conditions
Min

Typ

1.5
1.6

Units
Max
16.0
16.0

V

4.0
3.5

12
10

J-tA

1.3

1.4

V

VIN

Input Voltage

TA= + 25'C
O'C:S:TA:S:+70'C

10

Quiescent Current

{ Rl = 00
}
I.4V:S:VOUT:S:8.5V

VSET

Reference Voltage

aVSET
AT

Temperature Coefficient

8.5V
3:

VOUT~R2+R1
R,

VSET

4: 10 quiescent current is measured at GND pin by meter M.
5: 83 when ON, permits normal operation, when OFF, shuts
down both VOUT1 and VOUT2·

RL

R,
1,.AMIH

ON

S.
OFF
lUQ
'-----'WIr--01.4V 4.970 Ht-Hllllt-ttlltllt-tttlllllt-tttt. .tillitil
4.965 1-+I-fM-HlIlfIII--I+I!!111-+Hiilllf-++HI1III

4.980 Hf-Hllllf--ffiHll!-+HfIIIIH+!!IIIII-+iKflll
4.955 Hf-Hllllf--ffiIllllf-+HfIIIIH+!!IIIII-+iKflll

I
I

1.4 1-1-

VI~=2V 1 J

.1 +1 1
VIN =9V

0.4
0.2

.Yf

lOUT (rnA)

~

-I- ~:::: ~ ~15V- -

o J,.~
o 2 4

4.950 WL.IJIIIU...J..U.UJIII....LJJllIJlL..L.J.WJIL.WUlJIII
1,.A 10,.A 100,.A 1.0 10.0 100.0

"7 ~

I I

VIN= +9.0V
 .....-OVOUT

0321-20

R2
R2
EO.1: VOUT=VSET(1 +-) +-R(VSET-VTC)
R1
3
EO.2: TC VOUT= - ::(TCVTcl in mVrC
WHERE: VSET= 1.3V
VTC=0.9V
TCVTC = + 2.5mV

rc

Figure 4: Generating Negative Temperature
Coefficients

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

5-33

01

ICL7663
APPLICATIONS

•

VIN

SENSE
RCL
VOUT2

r-

"I =7.,.,••

VOUTl
ICL7663
VTC '-"-

.,1
VOUT

VSET

GND SHDN

1

1

~

Rl

1
V OUT =R2+Rl VSET
ICL = O.7V
RCL
0321-21

Figure 5: Basic Application of ICL7663 as
Positive Regulator with Current Limit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not t6Sted

5-34

ICL7663
ICL7663B ADDENDUM TO THE ICL7663 DATASHEET
This Addendum to the standard ICL7663 datasheet describes changes and/or modifications to the DC Operating
characteristics applicable to the ICL7663B devices. The following table indicates those limits to which the ICL7663B is
tested and/or guaranteed operational.

ICL7663B POSITIVE REGULATOR
ORDERING INFORMATION
Positive Regulator
ICL7663BCBA
ICL7663BCJA
ICL7663BCPA
ICL7663BCTV

O·Cto 70"C
O·Cto 70·C
O"Cto 70"C
0·Ct070·C

B-pin S.O.I.C.
B-pin CERDIP
B-pin MiniDIP
TO-99

ABSOLUTE MAXIMUM RATINGS ICL7663B
Output Sinking Current (Terminal 7) ............. -10mA
Power Dissipation (Note 2)
MiniDIP ......•............................. 200mW
TO-99 Can ................................. 300mW

Input Supply Voltage ......•.•.•...•..•.......... + 12V
Any Input or Output Voltage (Note 1) Terminals 1, 2, 3, 4, 5,
6, 7) ............•...•..• (GND -0.3V) to (V+ IN + 0.3V)
Output Source Current
(Terminal 2) .....................•.....•...... 50mA
(Terminal 3) ..................•.........•...•. 25mA

NOTE: Stresses above those listed under "Absolute Maximum Ralfngs" may cause permt1nsnt damage to the device. Thase are stress ratings only and functional
operation of Iha device at lhasa or any other conditions abovelhose Indicated in Iha operationsl sections of Iha specifications Is not impHed. Exposure to absolute
maximum rating conditions for extended periods may sffscl device reliability.

ICL7663B OPERATING CHARACTERISTICS

V+IN=9V, VOUT= 5V, TA= + 25·C, unless otherwise

specified.
Symbol

Parameter

Limits

Test Conditions
Min

Input Voltage

TA= +25·C
20·CS:TAS: +70"C

IQ

Quiescent Current

{Rl=OO
}
1.4VS:VOUTS:B.5V

VSET

Reference Voltage

V+IN

aVSET
aT
aVSET
VSETaVIN
ISET
ISHDN

1.2

V

3.5

10

",A

1.3

1.4

V

±200

ppm

Line Regulation

2V2000V

APPLICATIONS
-

Low·Powar Portable InstNmantatlon
Pagera
Handhald InatNmanta
LCD DlllPlay Modules
Ramota bafa LoaaBattary-Powared-Syatams

ORDERING INFORMATION

TOPYIEW

PART
NUMBER
ICL7883SCBA
ICL7883SCPA
ICL7883SCJA
ICL7883SCTV
ICL7883SACPA
ICL7883SACJA
ICL7883BACTY
ICL7883SIBA
ICL7883SIPA
ICL7883SIJA
ICL7883SITV
ICL7883SAIPA
ICL7883SA1JA
ICL7883SAITV

OUTUM DWG (SAl

TEMPERATURE
RANGE
."C to +70"C

PACKAGE
8 Laad SOIC
8 Laad Mlnldip
8 Lead CERDIP

1t).88

8 Lead Mlnldlp
8 Lead CERDIP

"10-118

-25"C 10 +85·

8 Lead SOlO

:t=~~n~tfp

1t).88

: t::l ~~~Jfp

1t).88

-.

GROUND

......
,r-+.:;;~===:::t
,

OUTLINE DWG (Till

OUTLINE DWG (PA, JAI

'--+--1------'<>' SHU11tOWN

C>----+-........----..!o' aN'
Figure 2: ICL7613S Functional Diagram

Figure 1: Pin CClntlgumklns

0092-1

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TC THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
302166.001

NOTE: AU typIcsJ _

have bHn _

but.,. not 1BtJ/BtI.

5·37

= ICL7663S
10

...10
..I

g

ABSOLUTE MAXIMUM RATINGS
Stresses above those Hsted under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or
any other conditions above thOse indicated in the operational
sections of the specifications is not imp/ted. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.

Input Supply Voltage ................................................... + 18V
Any Input or Output Voltage (Note 1)
(Terminals 1,2,3,S,6,7,)..............(VIN +0.3) to (GND -0.3)V
Output Source Current
(Terminal 2) ..........................................................SOmA
(Terminal 3) ..........................................................2SmA
Output Sinking Current
(Terminal 7) ....................................................... -10mA
Lead Temperature (Soldering, 10 sec) .......................300·C
Storage Temperature Range ........................ -6S· to IS0·C
Operating Temp. Range
ICL7663SC .............................................0·C to + 70·C
ICL7663SI.. ....................................... -2S·C to +8S·C
Total Power Dissipation (Note 2)
SOIC .................................................................. 200mW
Minidip ............................................................... 200mW
T0-99 Can .........................................................300mW
CERDIP ............................................................. SOOmW

ELECTRICAL CHARACTERISTICS Specifications below applicable to bOth ICL7663S and ICL7663SA unless otherwise stated. V,. - 'JI/, VOUT = SV, TA = 2S"C, unless otherwise stated. See Test
Circuit, Figure 3.
LIMITS
SYMBOL

V.,

PARAMETER

InputVo/1age

TEST CONDITIONS

MIN

1CL7663$
TA = 2S'C
O'C < TA < 70'C
-2S'CIour

TEST CONDITIONS

VSHDN HI: Both VOUT Disabled
VSHDN LO: Both VOUT Enabled

MIN

TYP

MAX

UNITS

:to.Ol

10

nA

0.3

V
V

10

nA

50
35

350
100
70

0
0
0

1
2

3
10

0
0

1.4

0.01
0.5

'N. loun • 1rnA
V+ IN - av. 'oun • 2mA
V+ IN - 15V• .Ioun • SmA
lmA < 10UT2 < 20mA
5Oj