1987_Intersil_Component_Data_Catalog 1987 Intersil Component Data Catalog

User Manual: 1987_Intersil_Component_Data_Catalog

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ao

011.

Component Data
Catalog

1987

INTERSIL, INC., 10600 RIDGEVIEW COURT, CUPERTINO, CA 95014
Printed in U.S.A. @ Copyright 1987, Intersil, Inc., All Rights Reserved

(408) 996·5000 TWX: 910·338·2014
GE a n d . are registered trademarks of General Electric Company, U.S.A.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIeS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE All typical values have been characterized but are not tested.

Table of Contents

SELECTOR GUIDES
A/D CONVERTERS DISPLAY TYPE
A/D CONVERTERS

~P

TYPE

0/ A CONVERTERS
POWER SUPPLY SUPERVISORY
SPECIAL ANALOG
OPERATIONAL AMPLIFIERS
ANALOG SWITCHES
MULTIPLEXERS
DISCRETES
DATA COMMUNICATIONS
DIGITAL SIGNAL PROCESSING
DISPLAY DRIVERS
TIMERS/CLOCKS/COUNTERS WITH DISPLAY DRIVERS
HIGH RELIABILITY
ORDERING AND MARKING INFORMATION

II

•IIII

II
III

•DI

III

II

III
II
II
II
ILl

III

Functional Table of Contents
Page

Description

Section 1 -

Selector Guides

Section 2 -

AID Converters Display Type

ICL7106 3 YrDigit LCD Single-Chip AID Converter..................................
ICL71073 %-Digit LED Single-Chip AID Converter...................................
ICL7116 3 %-Digit with Display Hold Single-Chip AID Converter. . . . . . . . . . . . . . . . . . . . . . .
ICL71173 %-Digit with Display Hold Single-Chip AID Converter.......................
ICL7126 3 %-Digit Low-Power Single-Chip AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7129 4 % Digit LCD Single-Chip AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL71363 YrDigit LCD Low Power AID Converter...................................
ICL7137 3 %-Digit LED Low Power Single-Chip AID Converter. . . . . . . . . . . . . . . . . . . . . . . .
ICL7139 3%-Digit Autoranging Multimeter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7149 Low Cost 3%-Digit Autoranging Multimeter ..................................
ICL7182 101 Segment LCD Bargraph AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 3 -

3-1
3-1
3-1
3-19
3-19
3-39
3-58
3-60
3-74

DIA Converters

AD7520 10/12-Bit Multiplying D/A Converter........................................
AD7521 10/12-Bit Multiplying D/A Converter........................................
AD7530 10/12-Bit Multiplying D/A Converter........................................
AD7531 10/12-Bit Multiplying D/A Converter........................................
AD7523 8-Bit Multiplying DI A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AD7533 10-Bit Multiplying D/A Converter............................................
AD7541 12-Bit Multiplying D/A Converter............................................
ICL7121 16-Bit Multiplying Microprocessor-Compatible DI A Converter ..................
ICL7134 14-Bit Multiplying p,P-Compatible 01 A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IM2110 256 x 12 Color Lookup Table and DAC.......................................

Section 5 -

2-1
2-1
2-13
2-13
2-24
2-35
2-47
2-58
2-67
2-81
2-95

AID Converters p,P Type

ADC0802 8-Bit p,P-Compatible AID Converter .......................................
ADC0803 8-Bit p,P-Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
ADC0804 8-Bit p,P-Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
ICL7104/1CL8052 12/14/16-Bit p,P-Compatible 2-Chip AID Converter.................
ICL7104/1CL8068 12/14/16-Bit p,P-Compatible 2-Chip AID Converter.................
ICL7109 12-Bit p,P-Compatible AID Converter.......................................
ICL7112 12-Bit High-Speed CMOS p,P-Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . .
ICL711514-Bit High-Speed CMOS p,P-Compatible AID Converter.....................
ICL71354 %-Digit BCD Output AID Converter.......................................

Section 4 -

1-1

4-1
4-1
4-1
4-1
4-8
4-13
4-18
4-25
4-32
4-46

Power Supply Supervisory

ICL7660 CMOS Voltage Converter..................................................
ICL7660S Super Voltage Converter.................................................
ICL7662 CMOS Voltage Converter..................................................
ICL7663 CMOS Programmable Micropower Positive Voltage Regulator..................
ICL7663S CMOS Programmable Micropower Positive Voltage Regulator................
ICL7665 Micropower Under/Over Voltage Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7665S CMOS Micropower Over/Under Voltage Detector...........................

5-1
5-10
5-20
5-28
5-37
5-44
5-53

Functional Table of Contents
Description

Section 5 ICL7667
ICL7673
ICL7675
ICL7676
ICL7677
ICL7680
ICL8211
ICL8212

Page

Power Supply Supervisory (Continued)

Dual Power MOSFET Driver................................................ 5-63
Automatic Battery Back-up Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-71
Switched-Mode Power Supply Controller Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-79
Switched-Mode Power Supply Controller Set................ ................. 5-79
Power Fail Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-89
+ 5V to ± 15V Voltage Converter/Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-101
Programmable Voltage Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5:103
Programmable Voltage Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-103

Section 6 -

Special Analog

AD590 2-Wire Current Output Temperature Transducer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8013 Four Quadrant Analog Multiplier................................ ... .........
ICL8038 Precision Waveform Generator/Voltage Controlled Oscillator. . . . . . . . . . . . . . . . . .
ICL8048 Logarithmic Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8049 Antilog Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8069 Low Voltage Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 7 -

6-1
6-12
6-21
6-30
6-30
6-39

Operational Amplifiers

ICH8500/ A Ultra Low Input-Bias Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1
ICL7600 Com mutating Auto-Zero (CAZ) Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . .
7-7
ICL7601 Commutating Auto-Zero (CAZ) Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . .
7-7
ICL7605 Commutating Auto-Zero (CAZ) Instrumentation Amplifier...................... 7-19
ICL7606 Commutating Auto-Zero (CAD) Instrumentation Amplifier. . . . . . . . . . . . . . . . . . . . . . 7-19
ICL76XX Series Low Power CMOS Operational Amplifiers............................. 7-31
ICL7650 Chopper-Stabilized Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46
ICL7650S Super Chopper-Stabilized Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54
ICL7652 Chopper-Stabilized Low-Noise Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . 7-64
ICL7652S Super Chopper-Stabilized Low-Noise Operational Amplifier. . . . . . . . . . . . . . . . . . . 7-72
ICL8007 JFET Input Operational Amplifier............................... ............ 7-82
ICL8021 Low Power Bipolar Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-86
ICL8023 Triple Low Power Bipolar Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-86
ICL8043 Dual JFET Input Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-91
ICL8063 Power Transistor Driver/Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-99
LM4250 Programmable Operational Amplifier ........................................ 7-108

Section 8 -

Analog Switches

D123 SPST 6-Channel JFET Switch Driver..........................................
D125 SPST 6-Channel JFET Switch Driver................................. .........
D129 4-Channel Decoded JFET Switch Driver .......................................
DG 123 SPST 5-Channel Driver With Switch. .. . . .. . . .. .. .. . . . .. . . .. . .. . . . . . . .. . . . . .. .
DG 125 SPST 5-Channel Driver With Switch. .. . . . . . . .. . . . .. . . .. .. . . . . .. . . . . . . . . .. . .. .
DG126 Dual DPST 80 Ohm JFET Analog Switch.....................................
DG129 Dual DPST 30 Ohm JFET Analog Switch .....................................
DG133 Dual SPST 30/35 Ohm JFET Analog Switch..................................
DG134 Dual SPST 80 Ohm JFET Analog Switch......................................
DG140 Dual DPST 10/15 Ohm JFET Analog Switch..................................

8-1
8-1
8-5
8-7
8-7
8-11
8-11
8-11
8-11
8-11

Functional Table of Contents
Page

Description

Section 8 -

Analog Switches (Continued)

DG141 Dual SPST 10 Ohm JFET Analog Switch......................................
DG151 Dual SPST 15 Ohm JFET Analog Switch......................................
DG152 Dual SPST 50 Ohm JFET Analog Switch......................................
DG153 Dual DPST 15 Ohm JFET Analog Switch .....................................
DG154 Dual DPST 50 Ohm JFET Analog Switch.....................................
DG139 DPDT 30 Ohm Differentially Driven JFET Switch...............................
DG142 DPDT 80 Ohm Differentially Driven JFET Switch...............................
DG143 SPDT 80 Ohm Differentially Driven JFET Switch...............................
DG144 SPDT 30 Ohm Differentially Driven JFET Switch...............................
DG145 DPDT 10 Ohm Differentially Driven JFET Switch...............................
DG146 SPDT 10 Ohm Differentially Driven JFET Switch...............................
DG161 SPDT 15 Ohm Differentially Driven JFET Switch...............................
DG162 SPDT 50 Ohm Differentially Driven JFET Switch...............................
DG163 DPDT 15 Ohm Differentially Driven JFET Switch...............................
DG164 DPDT 50 Ohm Differentially Driven JFET Switch...............................
DG180 Dual SPST 10 Ohm High-Speed Driver With JFET Switch.......................
DG181 Dual SPST 30 Ohm High-Speed Driver With JFET Switch.......................
DG182 Dual SPST 75 Ohm High-Speed Driver With JFET Switch.......................
DG183 Dual DPST 10 Ohm High-Speed Driver With JFET Switch.......................
DG184 Dual DPST 30 Ohm High-Speed Driver With JFET Switch.......................
DG185 Dual DPST 75 Ohm High-Speed Driver With JFET Switch. . . . . . . . . . . . . . . . . . . . . . .
DG186 SPDT 10 Ohm High-Speed Driver With JFET Switch ...........................
DG187 SPDT 30 Ohm High-Speed Driver With JFET Switch...........................
DG188 SPDT 75 Ohm High-Speed Driver With JFET Switch ...........................
DG189 Dual SPDT 10 Ohm High-Speed Driver With JFET Switch.......................
DG190 Dual SPDT 30 Ohm High-Speed Driver With JFET Switch. . . . . . . . . . . . . . . . . . . . . . .
DG191 Dual SPDT 75 Ohm High-Speed Driver With JFET Switch. . . . . . . . . . . . . . . . . . . . . . .
DG200 Dual SPST CMOS Analog Switch ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DG201 Quad SPST CMOS Analog Switch...........................................
DG201A Quad Monolithic SPST CMOS Analog Switches..............................
DG202 Quad Monolithic SPST CMOS Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DG211 SPST 4-Channel Analog Switch .............................................
DG212 SPST 4-Channel Analog Switch.............................................
DG300A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DG301 A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . . . .
DG302A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DG303A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGM181 Dual SPST 50 Ohm High-Speed CMOS Analog Switch........................
DGM182 Dual SPST 50/75 Ohm High-Speed CMOS Analog Switch ....................
DGM184 Dual DPST 50 Ohm High-Speed CMOS Analog Switch.......................
DGM185 Dual DPST 50/75 Ohm High-Speed CMOS Analog Switch ....................
DGM190 Dual SPDT 50 Ohm High-Speed CMOS Analog Switch ....... :...............
DGM191 Dual SPDT 50/75 Ohm High-Speed CMOS Analog Switch....................
IH311 High Speed SPST 4-Channel Analog Switch . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . . . .
IH312 High Speed SPST 4-Channel Analog Switch...................................
IH401 QUAD Varafet Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH401A QUAD Varafet Analog Switch...............................................
IH5009 Quad 100 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5010 Quad 150 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii

8-11
8-11
8-11
8-11
8-11
8-17
8-17
8-17
8-17
8-17
8-17
8-17
8-17
8-17
8-17
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-28
8-32
8-36
8-36
8-41
8-41
8-44
8-44
8-44
8-44
8-49
8-49
8-49
8-49
8-49
8-49
8-54
8-54
8-59
8-59
8-65
8-65

Functional Table of Contents
Page

Description

Section 8 -

Analog Switches (Continued)

IH5011 Quad 100 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5012 Quad 150 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5013 Triple 100 Ohm Virtual Ground Analog Switch.................................
IH5014 Triple 150 Ohm Virtual Ground Analog Switch.................................
IH5015 Triple 100 Ohm Virtual Groung Analog Switch.................................
IH5016 Triple 150 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5017 Dual 100 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5018 Dual 150 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5019 Dual 100 Ohm Virtual Ground Analog Switch..................................
IH5020 Dual 150 Ohm Virtual Ground Analog Switch..................................
IH5021 Single 100 Ohm Virtual Ground Analog Switch ................................
IH5022 Single 150 Ohm Virtual Ground Analog Switch ................................
IH5023 Single 100 Ohm Virtual Ground Analog Switch ................................
IH5024 Single 150 Ohm Virtual Ground Analog Switch ................................
IH5040 SPST 75 Ohm High-Level CMOS Analog Switch...............................
IH5041 Dual SPST 75 Ohm High-Level CMOS Analog Switch..........................
IH5042 SPDT 75 Ohm High-Level CMOS Analog Switch...............................
IH5043 Dual SPDT 75 Ohm High-Level CMOS Analog Switch..........................
IH5044 DPST 75 Ohm High-Level CMOS Analog Switch.. .. . . .. . .. .. .. .. .. . .. . . .. . . .. .
IH5045 Dual DPST 75 Ohm High-Level CMOS Analog Switch..........................
IH5046 DPDT 75 Ohm High-Level CMOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5047 4PST 75 Ohm High-Level CMOS Analog Switch...............................
IH5048 Dual SPST 35 Ohm High-Level CMOS Analog Switch..........................
IH5049 Dual DPST 35 Ohm High-Level CMOS Analog Switch..........................
IH5050 SPDT 35 Ohm High-Level CMOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5051 Dual SPDT 35 Ohm High-Level CMOS Analog Switch..........................
IH5052 QUAD CMOS Analog Switch................................................
IH5053 QUAD CMOS Analog Switch................................................
IH5140 SPST High-Level CMOS Analog Switch.......................................
IH5141 Dual SPST High-Level CMOS Analog Switch..................................
IH5142 SPDT High-Level CMOS Analog Switch......................................
IH5143 Dual SPDT High-Level CMOS Analog Switch..................................
IH5144 DPST High-Level CMOS Analog Switch......................................
IH5145 Dual DPST High-Level CMOS Analog Switch..................................
IH5148 Dual SPST High-Level CMOS Analog Switch..................................
IH5149 Dual DPST High-Level CMOS Analog Switch..................................
IH5150 SPDT High-Level CMOS Analog Switch ......................................
IH5151 Dual SPDT High-Level CMOS Analog Switch..................................
IH5341 Dual SPST CMOS RFlVideo Switch ..........................................
IH5352 QUAD SPST CMOS RFlVideo Switch ........................................
MM450 Dual Differential High Voltage Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM451 Four Channel High Voltage Multiplexer.......................................
MM452 Quad SPST High Voltage Analog Switch .....................................
MM455 Three SPST High Voltage Analog Switch.....................................
MM550 Dual Differential High Voltage Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MM551 Four Channel High Voltage Multiplexer.......................................
MM552 Quad SPST High Voltage Analog Switch .................. :..................
MM555 Three SPST High Voltage Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iv

8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-72
8-72
8-72
8-72
8-72
8-72
8-72
8-72
8-81
8-81
8-81
8-81
8-86
8-86
8-92
8-92
8-92
8-92
8-92
8-92
8-103
8-103
8-103
8-103
8-111
8-117
8-122
8-122
8-122
8-122
8-122
8-122
8-122
8-122

Functional Table of Contents
Description

Section 9 -

Page

Multiplexers

IH5108 8-Channel Fault Protected Analog Multiplexer....................... ..........
IH511616-Channel Fault Protected Analog Multiplexer................................
IH5208 4-Channel Differential Fault Protected Analog Multiplexer......................
IH5216 8-Channel Differential Fault Protected Analog Multiplexer ......................
IH6108 8-Channel CMOS Analog Multiplexer ........................................
IH6116 16-Channel CMOS Analog Multiplexer ............................. . . . . . . . . . .
IH6201 Dual CMOS DriverlVoltage Translator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH6208 4-Channel Differential CMOS Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH6216 8-Channel Differential CMOS Analog Multiplexer..............................
IH9108 8-Channel High-Voltage Multiplier with Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 10 -

9-1
9-10
9-14
9-23
9-27
9-33
9-40
9-44
9-50
9-56

Discretes

2N2607 P-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N2608 P-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N2609 P-Channel JFET General Purpose Amplifier..................................
2N2609JAN P-Channel JFET General Purpose Amplifier..............................
2N3684 N-Channel JFET Low Noise Amplifier .......................................
2N3685 N-Channel JFET Low Noise Amplifier .......................................
2N3686 N-Channel JFET Low Noise Amplifier .......................................
2N3687 N-Channel JFET Low Noise Amplifier .......................................
2N381 0/ A Monolithic Dual Matched PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . .
2N3811 / A Monolithic Dual Matched PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . .
2N3821 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3821JAN N-Channel JFET High Frequency Amplifier......................... ......
2N3821 JTX N-Channel JFET High Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3821 JTXV N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822JAN N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822JTX N-Channel JFET High Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822JTXV N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3823 N-Channel JFET High Frequency Amplifier...................................
2N3823JAN N-Channel JFET High Frequency Amplifier...............................
2N3823JTX N-Channel JFET High Frequency Amplifier...............................
2N3823JTXV N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3824 N-Channel JFET Switch ...................................................
2N3921 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3922 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3954 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N3954A Monolithic Dual N-Channel JFET General Purpose Amplifier......... .........
2N3955 Monolithic Dual N-Channel JFET General Purpose Amplifier.......... .........
2N3955A Monolithic Dual N-Channel JFET General Purpose Amplifier..................
2N3956 Monolithic Dual N-Channel JFET General Purpose Amplifier .......... . . . . . . . ..
2N3957 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N3958 Monolithic Dual N-Channel JFET General Purpose Amplifier .......... . . . . . . . ..
2N3970 N-Channel JFET Switch ...................................................
2N3971 N-Channel JFET Switch ...................................................
2N3972 N-Channel JFET Switch ...................................................
2N3993 P-Channel JFET General Purpose Amplifier/Switch. . . . . . . . . . . . . . . . . . . . . . . . . ..
v

10-1
10-1
10-1
10-1
10-2
10-2
10-2
10-2
10-3
10-3
10-5
10-5
10-5
10-5
10-5
10-5
10-5
10-5
10-7
10-7
10-7
10-7
10-8
10-9
10-9
10-11
10-11
10-11
10-11
10-11
10-11
10-11
10-13
10-13
10-13
10-15

Functional Table of Contents
Description

Section 1 0 -

Page

Discretes (Continued)

2N3994 P-Channel JFET General Purpose Amplifier/Switch. . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4044 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N4045 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N41 00 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N4878 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier...........
2N4879 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N4880 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N4091 JANTX N-Channel JFET Switch ............................................
2N4091 N-Channel JFET Switch ...................................................
2N4092 JANTX N-Channel JFET Switch............................................
2N4092 N-Channel JFET Switch...................................................
2N4093 JANTX N-Channel JFET Switch ............................................
2N4093 N-Channel JFET Switch ...................................................
ITE4091 N-Channel JFET Switch ...................................................
ITE4092 N-Channel JFET Switch ...................................................
ITE4093 N-Channel JFET Switch...................................................
2N4117 N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4117 AN-Channel JFET General Purpose Amplifier ................................
2N4118 N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4118A N-Channel JFET General Purpose Amplifier ................................
2N4119 N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4119A N-Channel JFET General.Purpose Amplifier ................................
2N4220 N-Channel JFET General Purpose Amplifier/Switch...........................
2N4221 N-Channel JFET General Purpose Amplifier/Switch. . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4222 N-Channel JFET General Purpose Amplifier/Switch...........................
2N4223 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4224 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4338 N-Channel JFET Low Noise Amplifier .......................................
2N4339 N-Channel JFET Low Noise Amplifier .......................................
2N4340 N-Channel JFET Low Noise Amplifier .......................................
2N4341 N-Channel JFET Low Noise Amplifier .......................................
2N4351 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch .....
2N4391 N-Channel JFET Switch ...................................................
2N4392 N-Channel JFET Switch ...................................................
2N4393 N-Channel JFET Switch ...................................................
ITE4391 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITE4392 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITE4393 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4416/ AN-Channel JFET High Frequency Amplifier ................................
ITE4416 N-Channel JFET High Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4856 N-Channel JFET Switch ...................................................
2N4856JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4857 N-Channel JFET Switch ...................................................
2N4857JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4858 N-Channel JFET Switch ...................................................
2N4858JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4859 N-Channel JFET Switch ...................................................
2N4859JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4860 N-Channel JFET Switch ...................................................
vi

10-15
10-16
10-16
10-16
10-16
10-16
10-16
10-19
10-19
10-19
10-19
10-19
10-19
10-19
10-19
10-19
10-21
10-21
10-21
10-21
10-21
10-21
10-22
10-22
10-22
10-23
10-23
10-24
10-24
10-24
10-24
10-25
10-26
10-26
10-26
10-26
10-26
10-26
10-28
10-28
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30

Functional Table of Contents
Description

Section 1 0 -

Page

Discretes (Continued)

2N4860JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4861 N-Channel JFET Switch ...................................................
2N4861JAN,JTX,JTXV N-Channel JFET Switch....................... ...............
2N4867 / AN-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4868/ AN-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4869/ AN-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5018 P-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5019 P-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5114 P-Channel JFET Switch. . . .. . .. . .. .. .. .. . .. . . .. . .. . .. .. . . .. . .. . .. .. .. . .. . ..
2N5114JAN,JTX,JTXV P-Channel JFET Switch.............. ........................
2N5115 P-Channel JFET Switch. . . .. . . .. .. .. .. .. . . .. . . . . . . . .. .. . . .. . .. . .. .. .. . . .. ..
2N5115JAN,JTX,JTXV P-Channel JFET Switch ......................................
2N5116 P-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5116JAN,JTX,JTXV P-Channel JFET Switch........... ...........................
2N5117 Dielectrically Isolated Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . ..
2N5118 Dielectrically Isolated Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . ..
2N5119 Dielectrically Isolated Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . ..
2N5196 Dual N-Channel JFET General Purpose Amplifier.............................
2N5197 Dual N-Channel JFET General Purpose Amplifier.............................
2N5198 Dual N-Channel JFET General Purpose Amplifier.............................
2N5199 Dual N-Channel JFET General Purpose Amplifier .............................
2N5397 N-Channel JFET High Frequency Amplifier...................................
2N5398 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5432 N-Channel JFET Switch ...................................................
2N5433 N-Channel JFET Switch ...................................................
2N5434 N-Channel JFET Switch ...................................................
2N5452 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5453 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5454 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5457 N-Channel JFET General Purpose Amplifier/Switch...........................
2N5458 N-Channel JFET General Purpose Amplifier/Switch...........................
2N5459 N-Channel JFET General Purpose Amplifier/Switch...........................
2N5460 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5461 P-Channel JFET Low Noise Amplifier........................................
2N5462 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5463 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5464 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5465 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5484 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5485 N-Channel JFET High Frequency Amplifier...................................
2N5486 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5515 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5516 Dual N-Channel JFET Low Noise Amplifier...................................
2N5517 Dual N-Channel JFET Low Noise Amplifier ...................................
2N5518 Dual N-Channel JFET Low Noise Amplifier ...................................
2N5519 Dual N-Channel JFET Low Noise Amplifier .. : ................................
2N5520 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5521 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5522 Dual N-Channel JFET Low Noise Amplifier...................................
vii

10-30
10-30
10-30
10-32
10-32
10-32
10-33
10-33
10-35
10-35
10-35
10-35
10-35
10-35
10-37
10-37
10-37
10-39
10-39
10-39
10-39
10-41
10-41
10-43
10-43
10-43
10-45
10-45
10-45
10-47
10-47
10-47
10-48
10-48
10-48
10-48
10-48
10-48
10-50
10-50
10-50
10-52
10-52
10-52
10-52
10-52
10-52
10-52
10-52

Functional Table of Contents
Description

Section 10 -

Page

Discretes (Continued)

2N5523 Dual N-Channel JFET Low Noise Amplifier...................................
2N5524 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5638 N-Channel JFET Switch ...................................................
2N5639 N-Channel JFET Switch ...................................................
2N5640 N-Channel JFET Switch ...................................................
2N5902 Monolithic Dual N-Channel JFET General Purpose Amplifier................ ...
2N5903 Monolithic Dual N-Channel JFET General Purpose Amplifier...................
2N5904 Monolithic Dual N-Channel JFET General Purpose Amplifier . . . . . . . . . . . . . . . . . ..
2N5905 Monolithic Dual N-Channel JFET General Purpose Amplifier...................
2N5906 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5907 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5908 Monolithic Dual N-Channel JFET General Purpose Amplifier...................
2N5909 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5911 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5912 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT5911 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT5912 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITC5911 Dual N-Channel JFET High Frequency Amplifier .............................
ITC5912 Dual N-Channel JFET High Frequency Amplifier .............................
2N6483 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N6484 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N6485 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3N161 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose
Amplifier/Switch..............................................................
3N163 P-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch......
3N164 P-Channel Enhancement Mode MOSFET General Purpose/Switch..............
3N165 Monolithic Dual P-Channel Enhancement Mode MOSFET General Purpose
Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3N166 Monolithic Dual P-Channel Enhancement Mode MOSFET General Purpose
Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3N170 N-Channel Enhancement Mode MOSFET Switch ..............................
3N171 N-Channel Enhancement Mode MOSFET Switch..............................
3N172 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose
Amplifier/Switch..............................................................
3N173 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose
Amplifier/Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . ..
3N188 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier........
3N189 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier. . . . . . ..
3N190 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ........
3N191 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ........
10100 Dual Low Leakage Diode....................................................
ID101 Dual Low Leakage Diode ....................................................
IT100 P-Channel JFET Switch.................... ..................................
IT101 P-Channel JFET Switch ......................................................
IT120 Dual NPN General Purpose Amplifier..........................................
IT120A Dual NPN General Purpose Amplifier.........................................
IT121 Dual NPN General Purpose Amplifier..........................................
IT122 Dual NPN General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT126 Monolithic Dual NPN General Purpose Amplifier ................................
viii

10-52
10-52
10-54
10-54
10-54
10-56
10-56
10-56
10-56
10-56
10-56
10-56
10-56
10-58
10-58
10-58
10-58
10-58
10-58
10-60
10-60
10-60
10-62
10-63
10-63
10-65
10-65
10-67
10-67
10-69
10-69
10-71
10-71
10-71
10-71
10-73
10-73
10-75
10-75
10-76
10-76
10-76
10-76
10-78

Functional Table of Contents
Page

Description

Section 1 0 -

Discretes (Continued)

IT127 Monolithic Dual NPN General Purpose Amplifier ................................
1T128 Monolithic Dual NPN General Purpose Amplifier ................................
1T129 Monolithic Dual NPN General Purpose Amplifier................................
1T130 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT130A Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT131 Monolithic Dual PNP General Purpose Amplifier.................................
1T132 Monolithic Dual PNP General Purpose Amplifier.................................
IT136 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT137 Monolithic Dual PNP General Purpose Amplifier.................................
IT138 Monolithic Dual PNP General Purpose Amplifier.................................
1T139 Monolithic Dual PNP General Purpose Amplifier.................................
IT500 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT501 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT502 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT503 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT504 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT505 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT1700 P-Channel Enhancement Mode MOSFET General Purpose Amplifier. . . . . . . . . . . ..
IT1750 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch.....
J105 N-Channel JFET Switch .. .. . .. .. .. . .. .. . .. . .. . .. . .. .. . .. .. . .. .. . .. .. .. . . . .. ..
J106 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
J107 N-Channel JFET Switch......................................................
J108 N-Channel JFET Switch......................................................
J109 N-Channel JFET Switch......................................................
J110 N-Channel JFET Switch......................................................
J111 N-Channel JFET Switch ......................................................
J112 N-Channel JFET Switch......................................................
J113 N-Channel JFET Switch......................................................
J174 P-Channel JFET Switch ......................................................
J175 P-Channel JFET Switch ......................................................
J176 P-Channel JFET Switch ......................................................
J177 P-Channel JFET Switch ......................................................
J201 N-Channel JFET General Purpose Amplifier ....................................
J202 N-Channel JFET General Purpose Amplifier ....................................
J203 N-Channel JFET General Purpose Amplifier....................................
J204 N-Channel JFET General Purpose Amplifier ....................................
J308 N-Channel JFET High Frequency Amplifier .....................................
J309 N-Channel JFET High Frequency Amplifier.....................................
J310 N-Channel JFET High Frequency Amplifier.....................................
LM 114/H Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LM 114A1 AH Monolithic Dual NPN General Purpose Amplifier . . . . . . . . . . . . . . . . . . . . . . . . ..
M116 Diode Protected N-Channel Enhancement Mode MOSFET General Purpose
Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
U200 N-Channel JFET Switch ......................................................
U201 N-Channel JFET Switch ......................................................
U202 N-Channel JFET Switch ......................................................
U231 Dual N-Channel JFET General Purpose Amplifier ...............................
U232 Dual N-Channel JFET General Purpose Amplifier ...............................
U233 Dual N-Channel JFET General Purpose Amplifier ...............................
ix

10-78
10-78
10-78
10-80
10-80
10-80
10-80
10-82
10-82
10-82
10-82
10-84
10-84
10-84
10-84
10-84
10-84
10-87
10-88
10-89
10-89
10-89
10-90
10-90
10-90
10-91
10-91
10-91
10-92
10-92
10-92
10-92
10-94
10-94
10-94
10-94
10-95
10-95
10-95
10-97
10-97
10-99
10-100
10-100
10-100
10-101
10-101
10-101

Functional Table of Contents
Description

Section 10 -

Page

Discretes (Continued)

U234 Dual N-Channel JFET General Purpose Amplifier .......•....................... 10-101
U235 Dual N-Channel JFET General Purpose Amplifier ............................... 10-101
U257 Dual N-Channel JFET High Frequency Amplifier ................................ 10-103
U304 P-Channel JFET Switch ...................................................... 10-104
U305 P-Channel JFET Switch ...................................................... 10-104
U306 P-Channel JFET Switch ...................................•.................. 10-104
U308 N-Channel JFET High Frequency Amplifier ..................................... 10-106
U309 N-Channel JFET High Frequency Amplifier ..................................... 10-106
U310 N-Channel JFET High Frequency Amplifier ..................................... 10-106
U401 Dual N-Channel JFET Switch ................................................. 10-108
U402 Dual N-Channel JFET Switch ................................................. 10-108
U403 Dual N-Channel JFET Switch .........•........•.............................. 10-108
U404 Dual N-Channel JFET Switch ................................................. 10-108
U405 Dual N-Channel JFET Switch ................................................. 10-108
U406 Dual N-Channel JFET Switch ................................................. 10-108
U1897 N-Channel JFET Switch ..................................................... 10-110
U1898 N-Channel JFET Switch ..................................................... 10-110
U1899 N-Channel JFET Switch .........................•........................... 10-110
VCR2N Voltage Controlled Resistors ................................................ 10-112
VCR3P Voltage Controlled Resistors ................................................ 10-112
VCR4N Voltage Controlled Resistors ................................................ 10-112
VCR5P Voltage Controlled Resistors ................................................ 10-112
VCR7N Voltage Controlled Resistors ................................................ 10-112
VCR11N Voltage Controlled Resistors ............................................... 10-115

Section 11 -

Data Communications

IM26C91 Universal Asynchronous Receiver/Transmitter (UART) .......................
IM4702/4712 Baud Rate Generator.................................................
IM6402 Universal Asynchronous Receiver Transmitter (UART) .........................
IM6403 Universal Asynchronous Receiver Transmitter (UART) .........................
ICL232 + 5 Volt Powered Dual RS-232 Transmitter/Receiver . . . . . . . . . . . . . . • . . . . . . . . . ..

Section 12 -

11-1
11-19
11-26
11-26
11-36

Digital Signal Processing

IM29C128 Finite Impulse Response Filter Controller.................................. 12-1
IM29C510 CMOS 16 x 16 Bit, Multiplier/Accumulator................................. 12-7
EVK-128 Data Conversion and FIR Filtering System................................... 12-19

Section 13 -

Display Driver.

ICM7211 4-Digit LCD/LED Display Driver. . .. . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . .. . . . . . . .
ICM7212 4-Digit LCD/LED Display Driver............................................
ICM7218 8-Digit LED Multiplexed Display Driver......................................
ICM7228 8-Digit LED Multiplexed Display Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7231 Numeric Triplexed LCD Display Driver ........ ;.............................
ICM7232 Numeric Triplexed LCD Display Driver ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7233 Alphanumeric Triplexed LCD Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7243 8-Character LED ,...P-Compatible Display Driver .•..................•........
x

13-1
13-1
13-12
13-23
13-36
13-36
13-36
13-55

Functional Table of Contents
Description

Section 14 -

Page

Timers/Clocks/Counters with Display Drivers

ICM7170 p,P-Compatible Real-Time Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICM7207 / A CMOS Timebase Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7208 7-Digit LED Display Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7209 Timebase Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7215 6-Digit LED Display 4-Function Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7216A 8-Digit Multi-Function Frequency Counter/Timer . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7216B 8-Digit Multi-Function Frequency Counter/Timer . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7216C 8-Digit Frequency Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7216D 8-Digit Frequency Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7217 4-Digit LED Display Programmable Up/Down Counter. . . . . . . . . . . . . . . . . . . . . . ..
ICM7227 4-Digit LED Display Programmable Up/Down Counter. . . . . . . . . . . . . . . . . . . . . . ..
ICM72244 %-Digit LCD/LED Display Counter .......................................
ICM72254 %-Digit LCD/LED Display Counter .......................................
ICM7226A1B 8-Digit Multi-Function Frequency Counter/Timer.........................
ICM72364 %-Digit CounterlVacuum Fluorescent Display Driver.......................
ICM7240 Programmable Timer .....................................................
ICM7250 Programmable Timer .....................................................
ICM7242 Long-Range Fixed Timer ..................................................
ICM7249 5%-Digit LCD p,-Power Event/Hour Meter ..................................
ICM7555 General Purpose Timer ...................................................
ICM7556 Dual General Purpose Timer ...............................................

14-1
14-14
14-19
14-26
14-29
14-36
14-36
14-36
14-36
14-54
14-54
14-72
14-72
14-80
14-93
14-98
14-98
14-108
14-114
14-123
14-123

Section 15 -

High Reliability...........................................

15-1

Section 16 -

Ordering and Marking Information....... . . . . . . . . . . .

16-1

xi

Alphanumeric Index
2N2607 P-Channel JFET General Purpose Amplifier..................................
2N2608 P-Channel JFET General Purpose Amplifier..................................
2N2609 P-Channel JFET General Purpose Amplifier..................................
2N2609JAN P-Channel JFET General Purpose Amplifier..............................
2N3684 N-Channel JFET Low Noise Amplifier .......................................
2N3685 N-Channel JFET Low Noise Amplifier .......................................
2N3686 N-Channel JFET Low Noise Amplifier .......................................
2N3687 N-Channel JFET Low Noise Amplifier.......................................
2N381 0/ A Monolithic Dual Matched PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . .
2N3811/ A Monolithic Dual Matched PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . .
2N3821 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3821 JAN N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3821JTX N-Channel JFET High Frequency Amplifier...............................
2N3821JTXV N-Channel JFET High Frequency Amplifier..............................
2N3822 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822JAN N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822JTX N-Channel JFET High Frequency Amplifier .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3822JTXV N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3823 N-Channel JFET High Frequency Amplifier...................................
2N3823JAN N-Channel JFET High Frequency Amplifier...............................
2N3823JTX N-Channel JFET High Frequency Amplifier...............................
2N3823JTXV N-Channel JFET High Frequency Amplifier..............................
2N3824 N-Channel JFET Switch ...................................................
2N3921 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . • . . . . .
2N3922 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2N3954 Monolithic Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . ..
2N3954A Monolithic Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . ..
2N3955 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N3955A Monolithic Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . ..
2N3956 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N3957 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N3958 Monolithic Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . ..
2N3970 N-Channel JFET Switch ...................................................
2N3971 N-Channel JFET Switch...................................................
2N3972 N-Channel JFET Switch...................................................
2N3993 P-Channel JFET General Purpose Amplifier/Switch ...........................
2N3994 P-Channel JFET General Purpose Amplifier/Switch. . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4044 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N4045 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier...........
2N4091 JANTX N-Channel JFET Switch............................................
2N4091 N-Channel JFET Switch ........................... ~.......................
2N4092 N-Channel JFET Switch...................................................
2N4092 JANTX N-Channel JFET Switch ............................................
2N4093 JANTX N-Channel JFET Switch ............................................
2N4093 N-Channel JFET Switch ...................................................
2N4100 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier...........
2N4117 N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4117 AN-Channel JFET General Purpose Amplifier ................................
2N4118 N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..
2N4118A N-Channel JFET General Purpose Amplifier ................................
2N4119 N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4119A N-Channel JFET General Purpose Amplifier ................................
2N4220 N-Channel JFET General Purpose Amplifier/Switch...........................
xii

10·1
10·1
10"1
10·1
10·2
10·2
10·2
10·2
10·3
10·3
10·5
10·5
10·5
10-5
10-5
10-5
10-5
10·5
10-7
10-7
10-7
10-7
10-8
10-9
10-9
10-11
10-11
10-11
10-11
10-11
10-11
10-11
10-13
10-13
10-13
10-15
10-15
10-16
10-16
10-19
10-19
10-19
10-19
10-19
10-19
10-16
10-21
10-21
10-21
10-21
10-21
10-21
10-22

Alphanumeric Index

(Continued)

2N4221 N-Channel JFET General Purpose Amplifier/Switch...........................
2N4222 N-Channel JFET General Purpose Amplifier/Switch...........................
2N4223 N-Channel JFET High Frequency Amplifier...................................
2N4224 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4338 N-Channel JFET Low Noise Amplifier.......................................
2N4339 N-Channel JFET Low Noise Amplifier.......................................
2N4340 N-Channel JFET Low Noise Amplifier .......................................
2N4341 N-Channel JFET Low Noise Amplifier.......................................
2N4351 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch .....
2N4391 N-Channel JFET Switch ...................................................
2N4392 N-Channel JFET Switch ...................................................
2N4393 N-Channel JFET Switch ...................................................
2N4416/ A N-Channel JFET High Frequency Amplifier ................................
2N4856 N-Channel JFET Switch ...................................................
2N4856JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4857 N-Channel JFET Switch ...................................................
2N4857JAN,JTX,JTXV N-Channel JFET Switch......................................
2N4858 N-Channel JFET Switch ...................................................
2N4858JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4859 N-Channel JFET Switch ...................................................
2N4859JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4860 N-Channel JFET Switch ...................................................
2N4860JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4861 N-Channel JFET Switch ...................................................
2N4861 JAN,JTX,JTXV N-Channel JFET Switch ......................................
2N4867 / A N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4868/ A N-Channel JFET Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4869/ A N-Channel JFET Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N4878 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier. . . . . . . . . ..
2N4879 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier...........
2N4880 Dielectrically Isolated Monolithic Dual NPN General Purpose Amplifier...........
2N5018 P-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5019 P-Channel JFET Switch ....................................................
2N5114 P-Channel JFET Switch....................................................
2N5114JAN,JTX,JTXV P-Channel JFET Switch ......................................
2N5115 P-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5115JAN,JTX,JTXV P-Channel JFET Switch ......................................
2N5116 P-Channel JFET Switch ....................................................
2N5116JAN,JTX,JTXV P-Channel JFET Switch ......................................
2N5117 Dielectrically Isolated Dual PNP General Purpose Amplifier.....................
2N5118 Dielectrically Isolated Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . ..
2N5119 Dielectrically Isolated Dual PNP General Purpose Amplifier. . . . . . . . . . . . .. . . . . . ..
2N5196 Dual N-Channel JFET General Purpose Amplifier.............................
2N5197 Dual N-Channel JFET General Purpose Amplifier.............................
2N5198 Dual N-Channel JFET General Purpose Amplifier.............................
2N5199 Dual N-Channel JFET General Purpose Amplifier.............................
2N5397 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5398 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5432 N-Channel JFET Switch ...................................................
2N5433 N-Channel JFET Switch ............................... -. . . . . . . . . . . . . . . . . . ..
2N5434 N-Channel JFET Switch .................................................. :
2N5452 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5453 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
xiii

10-22
10-22
10-23
10-23
10-24
10-24
10-24
10-24
10-25
10-26
10-26
10-26
10-28
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-30
10-32
10-32
10-32
10-16
10-16
10-16
10-33
10-33
10-35
10-35
10-35
10-35
10-35
10-35
10-37
10-37
10-37
10-39
10-39
10-39
10-39
10-41
10-41
10-43
10-43
10-43
10-45
10-45

Alphanumeric Index

(Continued)

2N5454 Dual N-Channel JFET General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5457 N-Channel JFET General Purpose Amplifier/Switch...........................
2N5458 N-Channel JFET General Purpose Amplifier/Switch...........................
2N5459 N-Channel JFET General Purpose Amplifier/Switch...........................
2N5460 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5461 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5462 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5463 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5464 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5465 P-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5484 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5485 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5486 N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5515 Dual N-Channel JFET Low Noise Amplifier...................................
2N5516 Dual N-Channel JFET Low Noise Amplifier...................................
2N5517 Dual N-Channel JFET Low Noise Amplifier ...................................
2N5518 Dual N-Channel JFET Low Noise Amplifier...................................
2N5519 Dual N-Channel JFET Low Noise Amplifier...................................
2N552Q Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5521 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5522 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5523 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5524 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5638 N-Channel JFET Switch ...................................................
2N5639 N-Channel JFET Switch ...................................................
2N5640 N-Channel JFET Switch ...................................................
2N5902 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5908 Monolithic Dual N-Channel JF[::T General Purpose Amplifier ...................
2N5904 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5905 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5906 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5907 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5908 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5909 Monolithic Dual N-Channel JFET General Purpose Amplifier ...................
2N5911 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N5912 Dual N-Channel JFET High Frequency Amplifier..............................
2N6483 Dual N-Channel JFET Low Noise Amplifier...................................
2N6484 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2N6485 Dual N-Channel JFET Low Noise Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3N161 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose
Amplifier/Switch..............................................................
3N163 P-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch......
3N164 P-Channel Enhancement Mode MOSFET General Purpose/Switch..............
3N165 Monolithic Dual P-Channel Enhancement Mode MOSFET General Purpose
Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3N166 Monolithic Dual P-Channel Enhancement Mode MOSFET General Purpose
Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3N170 N-Channel Enhancement Mode MOSFET Switch ..............................
3N171 N-Channel Enhancement Mode MOSFET Switch ..............................
3N172 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose
Amplifier/Switch..............................................................
3N173 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose
Amplifier/Switch.................... ..........................................
xiv

10-45
10-47
10-47
10-47
10-48
10-48
10-48
10-48
10-48
10-48
10-50
10-50
10-50
10-52
10-52
10-52
10-52
10-52
10-52
10-52
10-52
10-52
10-52
10-54
10-54
10-54
10-56
10-56
10-56
10-56
10-56
10-56
10-56
10-56
10-58
10-58
10-60
10-60
10-60
10-62
10-63
10-63
10-65
10-65
10-67
10-67
10-69
10-69

Alphanumeric Index

(Continued)

3N188 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier........
3N189 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier........
3N190 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier........
3N191 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier........
AD590 2-Wire Current Output Temperature Transducer. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
AD7520 10/12-Bit Multiplying D/A Converter........................................
AD7521 10/12-Bit Multiplying D/A Converter........................................
AD7523 8-Bit Multiplying D/ A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AD7530 10/12-Bit Multiplying D/A Converter........................................
AD7531 10/12-Bit Multiplying D/A Converter........................................
AD7533 10-Bit Multiplying DI A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AD7541 12-Bit Multiplying D/A Converter............................................
ADC0802 8-Bit J.LP-Compatible AID Converter.......................................
ADC0803 8-Bit J.LP-Compatible AID Converter.......................................
ADC0804 8-Bit J.LP-Compatible AID Converter.......................................
D123 SPST 6-Channel JFET Switch Driver..........................................
D125 SPST 6-Channel JFET Switch Driver..........................................
D129 4-Channel Decoded JFET Switch Driver .......................................
DG123 SPST 5-Channel Driver With Switch..........................................
DG 125 SPST 5-Channel Driver With Switch.. .. .. . .. . . .. . . .. . .. .. .. .. .. . .. .. .. . . . .. . .
DG126 Dual DPST 80 Ohm JFET Analog Switch.....................................
DG129 Dual DPST 30 Ohm JFET Analog Switch.....................................
DG133 Dual SPST 30/35 Ohm JFET Analog Switch..................................
DG134 Dual SPST 80 Ohm JFET Analog Switch......................................
DG139 DPDT 30 Ohm Differentially Driven JFET Switch...............................
DG140 Dual DPST 10/15 Ohm JFET Analog Switch..................................
DG141 Dual SPST 10 Ohm JFET Analog Switch......................................
DG142 DPDT 80 Ohm Differentially Driven JFET Switch...............................
DG143 SPDT 80 Ohm Differentially Driven JFET Switch...............................
DG144 SPDT 30 Ohm Differentially Driven JFET Switch...............................
DG145 DPDT 10 Ohm Differentially Driven JFET Switch...............................
DG146 SPDT 10 Ohm Differentially Driven JFET Switch...............................
DG151 Dual SPST 15 Ohm JFET Analog Switch......................................
DG152 Dual SPST 50 Ohm JFET Analog Switch......................................
DG153 Dual DPST 15 Ohm JFET Analog Switch.....................................
DG154 Dual DPST 50 Ohm JFET Analog Switch.....................................
DG161 SPDT 15 Ohm Differentially Driven JFET Switch...............................
DG162 SPDT 50 Ohm Differentially Driven JFET Switch...............................
DG163 DPDT 15 Ohm Differentially Driven JFET Switch...............................
DG164 DPDT 50 Ohm Differentially Driven JFET Switch...............................
DG180 Dual SPST 10 Ohm High-Speed Driver With JFET Switch.......................
DG181 Dual SPST 30 Ohm High-Speed Driver With JFET Switch.......................
DG182 Dual SPST 75 Ohm High-Speed Driver With JFET Switch.......................
DG183 Dual DPST 10 Ohm High-Speed Driver With JFET Switch.......................
DG184 Dual DPST 30 Ohm High-Speed Driver With JFET Switch.......................
DG185 Dual DPST 75 Ohm High-Speed Driver With JFET Switch.......................
DG186 SPDT 10 Ohm High-Speed Driver With JFET Switch...........................
DG187 SPDT 30 Ohm High-Speed Driver With JFET Switch...........................
DG188 SPDT 75 Ohm High-Speed Driver With JFET Switch...........................
DG189 Dual SPDT 10 Ohm High-Speed Driver With JFET Switch.......................
DG190 Dual SPDT 30 Ohm High-Speed Driver With JFET Switch.......................
DG191 Dual SPDT 75 Ohm High-Speed Driver With JFET Switch. . . . . . . . . . . . . . . . . . . . . . .
DG200 Dual SPST CMOS Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xv

10-71
10-71
10-71
10-71
6-1
4-1
4-1
4-8
4-1
4-1
4-13
4-18
3-1
3-1
3-1
8-1
8-1
8-5
8-7
8-7
8-11
8-11
8-11
8-11
8-17
8-11
8-11
8-17
8-17
8-17
8-17
8-17
8-11
8-11
8-11
8-11
8-17
8-17
8-17
8-17
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-22
8-28

Alphanumeric Index

(Continued)

DG201 Quad SPST CMOS Analog Switch ........................................... 8-32
DG201 A Quad Monolithic SPST CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
DG202 Quad Monolithic SPST CMOS Analog Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
DG211 SPST 4-Channel Analog Switch ............................................. 8-41
DG212 SPST 4-Channel Analog Switch ............................................. 8-41
DG300A TTL Compatible CMOS Analog Switches .................................... 8-44
DG301 A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44
DG302A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44
DG303A TTL Compatible CMOS Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44
DGM181 Dual SPST 50 Ohm High-Speed CMOS Analog Switch........................
8-49
DGM182 Dual SPST 50175 Ohm High-Speed CMOS Analog Switch....................
8-49
DGM184 Dual DPST 50 Ohm High-Speed CMOS Analog Switch.......................
8-49
DGM185 Dual DPST 50175 Ohm High-Speed CMOS Analog Switch....................
8-49
DGM190 Dual SPOT 50 Ohm High-Speed CMOS Analog Switch ....................... 8-49
DGM191 Dual SPOT 50175 Ohm High-Speed CMOS Analog Switch .................... 8-49
EVK-128 Data Conversion and FIR Filtering System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-19
ICH85001 A Ultra Low Input-Bias Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1
ICL232 +5 Volt Powered Dual RS-232 Transmitter/Receiver .......................... 11-36
ICL7104/1CL8052 12/14/16-Bit /lP-Compatible 2-Chip AID Converter.................
3-19
ICL7104/1CL8068 12/14/16-Bit /l-P-Compatible 2-Chip AID Converter.................
3-19
ICL71063 %-Digit LCD Single-Chip AID Converter..................................
2-1
ICL71073 %-Digit LED Single-Chip AID Converter...................................
2-1
ICL7109 12-Bit /l-P-Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
ICL7112 12-Bit High-Speed CMOS /l-P-Compatible AID Converter. . . . . . . . . . . . . . . . . . . . . . 3-58
ICL711514-Bit High-Speed CMOS /l-P-Compatible AID Converter.....................
3-60
ICL71163 %-Digit with Display Hold Single-Chip AID Converter.......................
2-13
ICL7117 3 %-Digit with Display Hold Single-Chip AID Converter. . . . . . . . . . . . . . . . . . . . . . . 2-13
ICL7121 16-Bit Multiplying Microprocessor-Compatible 01 A Converter ..................
4-25
ICL71263 %-Digit Low-Power Single-Chip AID Converter............................
2-24
ICL71294 % Digit LCD Single-Chip AID Converter...................................
2-35
ICL7134 14-Bit Multiplying /l-P-Compatible 01 A Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
ICL7135 4 %-Digit BCD Output AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74
ICL71363 %-Digit LCD Low Power AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
ICL7137 3 %-Digit LED Low Power Single-Chip AID Converter. . . . . . . . . . . . . . . . . . . . . . . . 2-58
ICL7139 3%-Digit Autoranging Multimeter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
ICL7149 Low Cost 3%-Digit Autoranging Multimeter .................................. 2-81
ICL7182 101 Segment LCD Bargraph AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-95
ICL7600 Commutating Auto-Zero (CAZ) Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . .
7-7
ICL7601 Commutating Auto-Zero (CAZ) Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . .
7-7
ICL7605 Commutating Auto-Zero (CAZ) Instrumentation Amplifier......................
7-19
ICL7606 Commutating Auto-Zero (CAD) Instrumentation Amplifier......................
7-19
ICL7650 Chopper-Stabilized Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46
ICL7650S Super Chopper-Stabilized Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54
ICL7652 Chopper-Stabilized Low-Noise Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . 7-64
ICL7652S Super Chopper-Stabilized Low-Noise Operational Amplifier. . . . . . . . . . . . . . . . . . . 7-72
ICL7660 CMOS Voltage Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
ICL7660S Super Voltage Converter................................................. 5-10
ICL7662 CMOS Voltage Converter.................................................. 5-20
ICL7663 CMOS Programmable Micropower Positive Voltage Regulator..................
5-28
ICL7663S CMOS Programmable Micropower Positive Voltage Regulator ................
5-37
ICL7665 Micropower Under/Over Voltage Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5·44
ICL7665S CMOS Micropower Over/Under Voltage Detector...........................
5-53
ICL7667 Dual Power MOSFET Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63
xvi

Alphanumeric Index

(Continued)

ICL7673 Automatic Battery Back-up Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7675 Switched-Mode Power Supply Controller Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7676 Switched-Mode Power Supply Controller Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7677 Power Fail Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL7680 + 5V to ± 15V Voltage Converter/Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICL76XX Series Low Power CMOS Operational Amplifiers.............................
ICL8007 JFET Input Operational Amplifier ...........................................
ICL8013 Four Quadrant Analog Multiplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8021 Low Power Bipolar Operational Amplifier ....................................
ICL8023 Triple Low Power Bipolar Operational Amplifier...............................
ICL8038 Precision Waveform GeneratorlVoltage Controlled Oscillator. . . . . . . . . . . . . . . . . .
ICL8043 Dual JFET Input Operational Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8048 Logarithmic Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8049 Antilog Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8063 Power Transistor Driver/Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8069 Low Voltage Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICL8211 Programmable Voltage Detector............................................
ICL8212 Programmable Voltage Detector....................... .....................
ICM7170 fA-P-Compatible Real-Time Clock...........................................
ICM7207 / A CMOS Timebase Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7208 7-Digit LED Display Counter...............................................
ICM7209 Timebase Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7211 4-Digit LCD/LED Display Driver............................................
ICM7212 4-Digit LCD/LED Display Driver............................................
ICM7215 6-Digit LED Display 4-Function Stopwatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7216A 8-Digit Multi-Function Frequency Counter/Timer...........................
ICM7216B 8-Digit Multi-Function Frequency Counter/Timer...........................
ICM7216C 8-Digit Frequency Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7216D 8-Digit Frequency Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7217 4-Digit LED Display Programmable Up/Down Counter. . . . . . . . . . . . . . . . . . . . . . ..
ICM7218 8-Digit LED Multiplexed Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM72244 %-Digit LCD/LED Display Counter.......................................
ICM72254 %-Digit LCD/LED Display Counter.......................................
ICM7226A1B 8-Digit Multi-Function Frequency Counter/Timer.........................
ICM7227 4-Digit LED Display Programmable Up/Down Counter. . . . . . . . . . . . . . . . . . . . . . ..
ICM7228 8-Digit LED Multiplexed Display Driver . . .. .. . .. .. . . .. . . . . . . . . . . . . . . . . . . . . . ..
ICM7231 Numeric Triplexed LCD Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM7232 Numeric Triplexed LCD Display Driver ......................................
ICM7233 Alphanumeric Triplexed LCD Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICM72364 %-Digit CounterlVacuum Fluorescent Display Driver.......................
ICM7240 Programmable Timer .....................................................
ICM7242 Long-Range Fixed Timer ..................................................
ICM7243 8-Character LED fA-P-Compatible Display Driver .............................
ICM7249 5%-Digit LCD fA--Power Event/Hour Meter ..................................
ICM7250 Programmable Timer .....................................................
ICM7555 General Purpose Timer ...................................................
ICM7556 Dual General Purpose Timer ...............................................
ID100 Dual Low Leakage Diode............... .....................................
ID101 Dual Low Leakage Diode ....................................................
IH311 High Speed SPST 4-Channel Analog Switch...................................
IH312 High Speed SPST 4-Channel Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH401 QUAD Varafet Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH401 A QUAD Varafet Analog Switch ...............................................
xvii

5-71
5-79
5-79
5-89
5-101
7-31
7-82
6-12
7-86
7-86
6-21
7-91
6-30
6-30
7-99
6-39
5-103
5-103
14-1
14-14
14-19
14-26
13-1
13-1
14-29
14-36
14-36
14-36
14-36
14-54
13-12
14-72
14-72
14-80
14-54
13-23
13-36
13-36
13-36
14-93
14-98
14-108
13-55
14-114
14-98
14-123
14-123
10-73
10-73
8-54
8-54
8-59
8-59

Alphanumeric Index

(Continued)

IH5009 Quad 100 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5010 Quad 150 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5011 Quad 100 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5012 Quad 150 Ohm Virtual Ground Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5013 Triple 100 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5014 Triple 150 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5015 Triple 100 Ohm Virtual Groung Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5016 Triple 150 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5017 Dual 100 Ohm Virtual Ground Analog Switch..................................
IH5018 Dual 150 Ohm Virtual Ground Analog Switch..................................
IH5019 Dual 100 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5020 Dual 150 Ohm Virtual Ground Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5021 Single 100 Ohm Virtual Ground Analog Switch ................................
IH5022 Single 150 Ohm Virtual Ground Analog Switch ................................
IH5023 Single 100 Ohm Virtual Ground Analog Switch ................................
IH5024 Single 150 Ohm Virtual Ground Analog Switch ................................
IH5040 SPST 75 Ohm High-Level CMOS Analog Switch...............................
IH5041 Dual SPST 75 Ohm High-Level CMOS Analog Switch..........................
IH5042 SPDT 75 Ohm High-Level CMOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5043 Dual SPDT 75 Ohm High-Level CMOS Analog Switch..........................
IH5044 DPST 75 Ohm High-Level CMOS Analog Switch...............................
IH5045 Dual DPST 75 Ohm High-Level CMOS Analog Switch..........................
IH5046 DPDT 75 Ohm High-Level CMOS Analog Switch...............................
IH5047 4PST 75 Ohm High-Level CMOS Analog Switch...............................
IH5048 Dual SPST 35 Ohm High-Level CMOS Analog Switch..........................
IH5049 Dual DPST 35 Ohm High-Level CMOS Analog Switch..........................
IH5050 SPDT 35 Ohm High-Level CMOS Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5051 Dual SPDT 35 Ohm High-Level CMOS Analog Switch..........................
IH5052 QUAD CMOS Analog Switch........... .....................................
IH5053 QUAD CMOS Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH5108 8-Channel Fault Protected Analog Multiplexer ..... :...........................
IH5116 16-Channel Fault Protected Analog Multiplexer................................
IH5140 SPST High-Level CMOS Analog Switch.......................................
IH5141 Dual SPST High-Level CMOS Analog Switch..................................
IH5142 SPDT High-Level CMOS Analog Switch......................................
IH5143 Dual SPDT High-Level CMOS Analog Switch..................................
IH5144 DPST High-Level CMOS Analog Switch......................................
IH5145 Dual DPST High-Level CMOS Analog Switch..................................
IH5148 Dual SPST High-Level CMOS Analog Switch..................................
IH5149 Dual DPST High-Level CMOS Analog Switch.................... ..............
IH5150 SPDT High-Level CMOS Analog Switch ......................................
IH5151 Dual SPDT High-Level CMOS Analog Switch ..................................
IH5208 4-Channel Differential Fault Protected Analog Multiplexer. . . . . . . . . . . . . . . . . . . . . .
IH5216 8-Channel Differential Fault Protected Analog Multiplexer......................
IH5341 Dual SPST CMOS RFlVideo Switch ..........................................
IH5352 QUAD SPST CMOS RFlVideo Switch ........................................
IH6108 8-Channel CMOS Analog Multiplexer........................................
IH6116 16-Channel CMOS Analog Multiplexer.......................................
IH6201 Dual CMOS DriverlVoltage Translator .............................. , . . . . . . . . .
IH6208 4-Channel Differential CMOS Analog Multiplexer ... . . . . . . . . . . . . . . . . . . . . . . . . . . .
IH6216 8-Channel Differential CMOS Analog Multiplexer..............................
IH9108 8-Channel High-Voltage Multiplier with Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IM2110 256 x 12 Color Lookup Table and DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xviii

8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-65
8-72
8-72
8-72
8-72
8-72
8-72
8-72
8-72
8-81
8-81
8-81
8-81
8-86
8-86
9-1
9-10
8-92
8-92
8-92
8-92
8-92
8-92
8-103
8-103
8-103
8-103
9-14
9-23
8-111
8-117
9-27
9-33
9-40
9-44
9-50
9-56
4-46

Alphanumeric Index

(Continued)

IM26C91 Universal Asynchronous Receiver/Transmitter (UART) .......................
IM29C128 Finite Impulse Response Filter Controller..................................
IM29C510 CMOS 16 x 16 Bit, Multiplier/Accumulator.................................
IM4702/4712 Baud Rate Generator .................................................
IM6402 Universal Asynchronous Receiver Transmitter (UART) ...................... ...
IM6403 Universal Asynchronous Receiver Transmitter (UART) .........................
IT100 P-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT101 P-Channel JFET Switch ......................................................
IT120 Dual NPN General Purpose Amplifier..........................................
IT120A Dual NPN General Purpose Amplifier.........................................
IT121 Dual NPN General Purpose Amplifier..........................................
IT122 Dual NPN General Purpose Amplifier..........................................
IT126 Monolithic Dual NPN General Purpose Amplifier................................
IT127 Monolithic Dual NPN General Purpose Amplifier.................. ..............
IT128 Monolithic Dual NPN General Purpose Amplifier................................
IT129 Monolithic Dual NPN General Purpose Amplifier................................
IT130 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT130A Monolithic Dual PNP General Purpose Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT131 Monolithic Dual PNP General Purpose Amplifier.................................
IT132 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT136 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT137 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT138 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT139 Monolithic Dual PNP General Purpose Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT1700 P-Channel Enhancement Mode MOSFET General Purpose Amplifier. . . . . . . . . . . ..
IT1750 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch .....
IT500 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT501 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT502 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT503 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT504 Monolithic Dual Cascoded N-Channel JFET General Purpose Amplifier. . . . . . . . . . ..
IT505 Monolithic Dual Cascoded N-Channel J FET General Purpose Amplifier. . . . . . . . . . ..
IT5911 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IT5912 Dual N-Channel JFET High Frequency Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITC5911 Dual N-Channel JFET High Frequency Amplifier .............................
ITC5912 Dual N-Channel JFET High Frequency Amplifier.............................
ITE4091 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITE4092 N-Channel JFET Switch...................................................
ITE4093 N-Channel JFET Switch...................................................
ITE4391 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITE4392 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITE4393 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ITE4416 N-Channel JFET High Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
J105 N-Channel JFET Switch ......................................................
J106 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
J107 N-Channel JFET Switch.................................. ....................
J108 N-Channel JFET Switch ......................................................
J109 N-Channel JFET Switch......................................................
J110 N-Channel JFET Switch........................................ ..............
J111 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
J112 N-Channel JFET Switch......................................................
J113 N-Channel JFET Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
J174 P-Channel JFET Switch ......................................................
xix

11-1
12-1
12-7
11-19
11-26
11-26
10-75
10-75
10-76
10-76
10-76
10-76
10-78
10-78
10-78
10-78
10-80
10-80
10-80
10-80
10-82
10-82
10-82
10-82
10-87
10-88
10-84
10-84
10-84
10-84
10-84
10-84
10-58
10-58
10-58
10-58
10-19
10-19
10-19
10-26
10-26
10-26
10-28
10-89
10-89
10-89
10-90
10-90
10-90
10-91
10-91
10-91
10-92

Alphanumeric Index

(Continued)

J175 P-Channel JFET Switch...................................................... 10-92
J176 P-Channel JFET Switch...................................................... 10-92
J177 P-Channel JFET Switch...................................................... 10-92
J201 N-Channel JFET General Purpose Amplifier.................................... 10-94
J202 N-Channel JFET General Purpose Amplifier.................................... 10-94
J203 N-Channel JFET General Purpose Amplifier.................................... 10-94
J204 N-Channel JFET General Purpose Amplifier.................................... 10-94
J308 N-Channel JFET High Frequency Amplifier..................................... 10-95
J309 N-Channel JFET High Frequency Amplifier .......................... ;.......... 10-95
J310 N-Channel JFET High Frequency Amplifier..................................... 10-95
LM114/H Monolithic Dual NPN General Purpose Amplifier ............................. 10-97
LM 114A1 AH Monolithic Dual NPN General Purpose Amplifier . . . . . . . . . . . . . . . . . . . . . . . . .. 10-97
LM4250 Programmable Operational Amplifier........................................ 7-108
M116 Diode Protected N-Channel Enhancement Mode MOSFET General Purpose
Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-99
MM450 Dual Differential High Voltage Analog Switch.................................. 8-122
MM451 Four Channel High Voltage Multiplexer....................................... 8-122
MM452 Quad SPST High Voltage Analog Switch ..................................... 8-122·
MM455 Three SPST High Voltage Analog Switch..................................... 8-122
MM550 Dual Differential High Voltage Analog Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-122
MM551 Four Channel High Voltage Multiplexer....................................... 8-122
MM552 Quad SPST High Voltage Analog Switch ..................................... 8-122
MM555 Three SPST High Voltage Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-122
U1897 N-Channel JFET Switch ..................................................... 10-110
U1898 N-Channel JFET Switch ..................................................... 10-110
U1899 N-Channel JFET Switch ..................................................... 10-110
U200 N-Channel JFET Switch ...................................................... 10-100
U201 N-Channel JFET Switch ..........................•........................... 10-100
U202 N-Channel JFET Switch ...................................................... 10-100
U231 Dual N-Channel JFET General Purpose Amplifier ............................... 10-101
U232 Dual N-Channel JFET General Purpose Amplifier ............................... 10-101
U233 Dual N-Channel JFET General Purpose Amplifier ............................... 10-101
U234 Dual N-Channel JFET General Purpose Amplifier ............................... 10-101
U235 Dual N-Channel JFET General Purpose Amplifier ............................... 10-101
U257 Dual N-Channel JFET High Frequency Amplifier ................................ 10-103
U304 P-Channel JFET Switch ...................................................... 10-104
U305 P-Channel JFET Switch ...................................................... 10-104
U306 P-Channel JFET Switch ...•.................................................. 10-104
U308 N-Channel JFET High Frequency Amplifier ..................................... 10-106
U309 N-Channel JFET High Frequency Amplifier ..................................... 10-106
U310 N-Channel JFET High Frequency Amplifier ..................................... 10-106
U401 Dual N-Channel JFET Switch ................................................. 10-108
U402 Dual N-Channel JFET Switch ................................................. 10-108
U403 Dual N-Channel JFET Switch ................................................. 10-108
U404 Dual N-Channel JFET Switch ................................................. 10-108
U405 Dual N-Channel JFET Switch ................................................. 10-108
U406 Dual N-Channel JFET Switch ................................................. 10-108
VCR 11 N Voltage Controlled Resistors ...................................~ ............ 10-115
VCR2N Voltage Controlled Resistors ................................................ 10-112
VCR3P Voltage Controlled Resistors ................................................ 10-112
VCR4N Voltage Controlled Resistors ................................................. 10-112
VCR5P Voltage Controlled Resistors ................................................ 10-112
VCR7N Voltage Controlled Resistors ................................................ 10-112
xx

408-996-5000
TWX: 910-338-2014

10600 Ridgeview Court, Cupertino, CA 95014

ALPHANUMERIC CROSS REFERENCE
ALTERNATE
SOURCE PRODUCT

100S
lOOU

INTERSIL
EQUIVALENT

2N5458
2N3684

ALTERNATE
SOURCE PRODUCT

2N2606
2N2607

103M

2N5686
2N5457
2N5457

2N2608
2N2609
2N2639

103S

2N5459

104M

2N5458

105M

2N5459

lO5U

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT
2N3332
2N3333
2N3334

2N2607
2N2607
2N2608

INTERSIL
EQUIVALENT

2N5268
ITI32

2N2609
iTI20

2N3335

ITl32
ITl32

2N3336

lTl32

2N2640
2N2641

ITI22
ITI22

2N3347

ITl3!

2N3348

2N2642
2N2643

106M

2N5485

2N2644

lTI20
ITI22
ITI22

2N3349

2N4340

ITI3B
1T139
tTl3!
ITl3B

107M
IIOU
120U

2N5485

2N2652

2N368S

2N2652A
2N2720

1T120
ITi20
ITI20
1T122
tTl 20

2N3352
2N3365

In39

102M

102S

12SU

1277A
1278A
1279A
12SOA

2N3686
2N4339
2N3822

2N2721
2N2722

2N3821
2N3821

2N2802
2N2803

2N4224

2N2804

2N3350
2N3351

2N3815
2N3816
2N3816A
2N3817
2N3817A

INTERSIL
EQUIVALENT
ITI32
tTI3C
ITl30A
tTI30
ITI30A

2N3822

2N5484
2N2608
2N3821
2N3822

2N3823

lN3823

2N3819
2N3820
2N3821

2N3824
2N3907
2N3908
2N3909

2N3368

ITl39
2N4340
2N4338
2N4338
2N4341

2N3909A

2N2609
2N2609

2N3369
2N3370
2N3376

2N4339
2N4338
2N2608

2N3921
2N3922
2N3949

2N3921
2N3922
ITI32

2N3366
2N3367

ITI39
1T139

ALTERNATE
SOURCE PRODUCT

2N3824

ITI20
ITI20

m~~

~~~~~~

~~~~g~

:n~~

~~~~~

~~~~gg

~~~~~~

~~~~54

1283A
1284A

2N4340
2N4222
2N3821

2N2807
2N2841
2N2842

ITI39
2N2607
2N2607

2N3382
2N3384
2N3386

2N3994
2N3993
2N5114

2N3954A
2N3955
2N3955A

2N3954A
2N3955
2N3955A

g~~A

~~;~~7

~~~~:~

~~~~g~

~~~:n

:m~

~~~m

~~~m

1325A

2N4222
2N4339
2N4224

2N2903

135U
14T

2N2903A
2N2910

ITI22
ITI20
ITI22

2N3411
2N3423
2N3424

ITI22
ITI22

2N3966
2N3967
2N3967A

2N4416
2N4221
2N4221

m~

~~!;~

~~m~

I~m

i~~ji

~Jti41

~~~~~~A

~~~~~~

1825
1835
1975

2N4391
2N3823
2N4338

2N2915

2N3437
2N3438
2N3452

2N4340
2N4338
2N4220

2N3969
2N3969A
2N3970

2N3686
2N3686
2N3970

l~g~

~~:~:o

~~~~W

tTI20
tTI20
ITI20
ITI20
TI22

~~~!~~

~~m~

~~m~

~~~m

2000M

2N3823

2N2918
2N2919
2N2919A

tTI22
ITI20
tTI20

2N3455
2N34S6
2N3457

2N4340
2N4338
2N4338

2N3993
2N3993A
2N3994

2N3993
2N3993
2N3994

1285A

2N2915A
2N2916

1T122

2aOlM

2N3823

200S

2N4392

~g?~

~~~~~1

~~~~~gA

~~~~~g

~~~!~g

~~:~;~

~~~66~A

FT~~~94

2025

2N4392
2N3821
2N3821

2N2936
2N2937
2N2972

ITI20
ITI20
ITI22

2N3460
2N3513
2N3514

2N4338
ITI22
tTI22

2N4010
2N4011
2N4015

ITI32
ITI32
ITI39

203S
2045

~g~g~

~~m~

~~~m

'mil

~~m~

:~lg

~~121~

::n~~

2080A
2a8lA
2093M

2N3955A

2N2975

2N3955A

2N2976

2N3517
2N3S21

2N3687

2N2977

ITI20
ITI20
ITI20

2N3522

2N4018
2N4019
2N4020

ITl39
tT139
tTI39

~g~~~

~~~~g~

~~~~~g

:mg

ITl22
tTI22
tTI22

~~m~

~~~~g~

~~12g

:m~

2098A
2099A
2IOU
2130U

2N3954
2N3955A

2N29SO
2N2981

2N4416

2N2982

ITI21
ITI22
ITI22

2N3578
2N3587
2N3608

2N2608
ITI22
3NI72

2N4023
2N4024
2N4025

tTl37
ITl37
ITl37

~~~!~~

~~~g:~

:m~

~~~~~~

~T~i~84

~~:g~~

~~ml

2134U
2136U
2138U

2N3956
2N3957

2N3045
2N3046
2N3047

ITI22
ITI21
ITI22

2N3684A

2N3684
2N3685
2N3685

2N4039
2N4065
2N4066

2N4351
3N163
3Nl66

m~~

~~~~~g

~~~g!g

:m~

~~~~g~A

~~~~g~

~~:g~;

~~1~~4

2148U
2149U

2N3958
2N3958
2N3954

ITl39
tTI39
ITl29

2N3687

231S

2N3050
2N3051
2N3052

2N3687A
2N3726

2N3687
2N3687
1T131

2N4083
2N4084
2N4085

2N3955
2N3954
2N3955

m~

~~~~~~

~~~g~~

~Jli4o

~~~~~~

~~12~lA

~~12~1

2345

2N3957

2N3067

235S

2N3958

2N3068

2N3729
2N3800

241U

2N4869

2N3069

2N4338
2N4338
2N4341

ITI21
1T132
ITI32

2N409IJAN
2N4091JANTX
2N4091JANTXV

2N409lJAN
2N4091 JANTX
2N4091 JANTXV

~~?~

~~!~1

~~~g~o

~~!m

~~~~g~

:i~~~

~~12~~A

~~12~~

2N2060
2N2060A
2N2060B

ITI20
ITt21
IT121
ITI22
ITI21

2N3084
2N3085
2N3086

2N4339
2N4339

2N4339

2N3804
2N3804A
2N3805

2N4092JAN
2N4092JANTX
2N4092JANTXV

2N4092JAN
2N4092JANTX
2N4092JANTXV

~~!m

~~~~g~A

tTI30
ITl30A
tTl 30
1T130A
ITI22

~~!g~~A

~~!g~~

2N2608

2N3088A
2N3089

2N4339
2N4339
2N4339

2N3807
2N3808
2N3809

ITI22
ITl22
ITI22

2N4093JAN
2N4093JANTX
2N4093JANTXV

2N4093JAN
2N4093JANTX
2N4093JANTXV

2 32

2N2223
2N222 A
2N2386
2N2386A
2N2453

~~~!~~A
2N2480A
2N2497
2N2498
2N2499
2N2500

2N3958

2N2608
ITI22

::nn
tTI21
2N2608

~~~g~~
2N3089A

2N3685A

2N3801

:mg

~~~m

~~~~g~

~~~~lgA

~~~m,

~~!IO~

~~~107

2N3278

2N2607
2N5265
2N5267
2N5268
2N5270

2N3811
2N3811A
2N3812
2N3813
2N3814

2N3811
2N3811A
ITI32
ITI32
ITI32

2N4117A
2N4118
2N4118A
2N4119
2N4119A

2N4117A
2N4118
2N4118A
2N4119
2N4119A

2N2608

2N3328
2N3329

2N2609
2N2608

2N3331

··CONSULT FACTORY

2N3685

2N3330

XXI

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

2N4120
2N4139

3N163

2N5021

2N3822

2N4220
2N4220A
2N4221

2N4220
2N4220
2N4221

2N5033
2NS045
2N5046
2N5047

2N4222

2N4221
2N4222

2N4222A
2N4223
2N4224

2N4222
2N4223
2N4224

2N4267
2N4268
2N4302
2N4303

3N163

2N4304

2N4221A

2N5078
2N5090
2N5103

ALTERNATE

INTERSIL

EQUIVALENT
2N2607
2N5460
2N5453

SOURCE PRODUCT

INTERSIL

EQUIVALENT

INTERSIL
EQUIVALENT

2N6485

2N6485

2N6502
2N6503
2N6550
2N6568

ITI22
1T122
2N4868A
2N5432

2SC294
2SJll

2N5S18
2N5519

2N5515
2N5516
2N5517
2NS518
2N5519

1T122
2N2607
2N2607
2N5270
2N2607

2N5520
2NS521
2N5S22
2N5523
2N5524

2NS520
2N5S21
2N5522
2N5523
2N5524

2SJ16
25J47

2N5475
2N5476
2N5484
2N5485
2N5486

2N5265
2N5266

2N5397
ITI22
2N4416

2N5515

2N5454
2N5454

ALTERNATE
SOURCE PRODUCT

2N5516

2N5517

2N5484
2NS485
2N5486

25J12
2SJ13
2SJ15

2N5104

2N4416

2N5105

2N4416
2NS114
2NSl14JAN

2N5458

2NS114
2NSl14JAN
2N5114JANTX
2N5114JANTXV
2N5115

2N5115

2N4338
2N4339
2N4340
2N4341
2N4342

2N4338
2N4339
2N4340
2N4341
2N5461

2N5l15JAN
2N511SJANTX
2N5115JANTXV
2N5116
2NS116JAN

2N5l15JAN
2N5115JANTX
2N5115JANTXV
2N5116
2N5116JAN

2N4343
2N4351
2N4352
2N4353
2N4360

2N5462
2N4351
3N163
3Nl72
2N5460

2N5116JANTX
2N5116JANTXV
2N5117
2N5118
2N5119

2N5116JANTX
2N5116JANTXV
2N5117
2N5118
2N5119

2N5120
2N5121
2N5122
2N5123
2N5124

ITl31
ITl32
ITl32
ITl31
ITl32

2N5563
2N5592

U404

2N3822

2N5593
2N5594
2N5638

2N3822
2N3822
2N5638

2SK178

2N5125
2NS158
2N5159

ITl32
2NS434
2NS433

2N5639

2N5639

2N5640
2N5647

2N5163

2N3822

2N5648

2N5640
2N4117A
2N4117A
2N4117A

2SK180
2SK19
2SK23
2SK30

2SK32

ITE4416
2NS459
2N5458
2N3822

2N5638

2SK33

2N5397

2SK34

2N3822
2N5484
2N5459

3Nl6!
2N4302
2N5459

2N5114JANTX
2N5114JANTXV

2N5546

2N5545

2N3954
2N3955Ao

2N5547

2N3955

2N5549
2N5555
2N5556

2N5557
2N5558
2N5561
2N5562

2N4381

2N2609

2N4382

2N5115

2N4391
2N4393

2N4391
2N4392
2N4393

2N4416
2N4416A
2N4417
2N4445
2N4446

2N4416
2N4416A
2N4416
2N5432
2N5434

2N5196

2NS196

2N5649

2N4447

2NS197
2N5198
2N5199
2N5245
2N5246

2N5197

2N5653
2N5654

2N4856
2N4856A
2N4856JAN

2N5432
2N5434
2N4856
2N4856A
2N4856JAN

2N4856JANTX
2N48S6JANTXV
2N4857
2N4857A
2N4857JAN

2N4856JANTX
2N4856JANTXV
2N4857
2N48571>
2N4857JAN

2N5247

2N4857 JANTX
2N4857 JANTXV
2N4858
2N4858A
2N4858JAN

2N485 7JANTX
2N4857 JANTXV

2N5257
2N5258

2N5457

2N4858

2N5259

2N5459

2N4858A
2N4858JAN

2N5265
2N5266

2N4858JANTX
2f114858JANTXV

2N4858JANTX
2N4858JANTXV

2N5267

2N4859

2N4859

2N4859A
2N4859JAN

2N4859A
2N4859JAN

2N4859JANTX
2N4859JTXV

2N4392

2N4448

2N5198

2N4093
J310
2N3685
2N3684
2N3684
U401
U402

2SJ48
2SJ49

2SJ50
2SJ78
2SJ79
2SJ80
2SKll

2SK12

......

~~2607

......

2N5457
2N5457

2SK135

....
..

2SK15

2N4868

2SKl7

2.~5484

2SK13
2SK132
2SKl33
2SK134

2SK179
2SK18

2.~5457

..
..

2N3821

2N5668
2N5669
2N5670

2N5639
2N5484
2N5485
2N5486

2N5793
2NS794
2NS795
2N5796

ITl29
ITl29
ITl39
ITl39

2SK48

2N3821

2N5797

2N2608

2SK49

2N5484

2N2608
2N2608
2N2608

2N2607

2N5798
2N5799
2N5800
2N5801

2N2607

2N5802

2N4393

2SK50
2SK54
2SK55
2SK56
2SK61

ITE4416
2N3822
2N3822
2N5459
2N5397

2N2608

2N5803

2N5268
2N5269
2N5270
2N5277

2N2608
2N2609
2N2609
2N4341

2N5843
2N5844
2N5902
2N5903

2N4392
ITl30
ITl30
2N5902
2N5903

2SK65
2SK66
2SK68
2SK72

3GS

J201
2N3821
2N3822
2N5196
2N3821

2N5278

2N4341
2N4220

2N5904

2N5904
2N5905

3N145

3N163

2N5358

3Nl46

3N163

2N5359

2N4220

2N5906

2N5360

2N4221

2N5907

2N5906
2N5907

2N5361

2N4221

2N5908

2N5908

3N147
3Nl48
3N149

3N189

2N4860A
2N4860JAN

2N4859JANTX
2N4859JTXV
2N4860
2N4860A
2N4860JAN

2N4860JANTX
2N4860JTXV

2N4860JANTX
2N4860JTXV

2N5362

2N4222
2N4222

2N5909

2N4861

2N4861

2N4222

2N5912

3N150
3NlSl
3N155

3N163
3N190
3N163

2N4861A
2N486IJAN

2N4861A
2N486IJAN

2N4867A
2N4868A

3N155A

3N163

2N5950

2N5909
2N5911
2N5912
2N5486
2N5486

3N156

3N163

2N486IJANTX
2N4861JANTXV
2N4867
2N4867A
2N4868

2N4861JANTX
2N486IJANTXV
2N4867
2N4867A
2N4868

2N5393
2N5394
2N5395

2N4869A
2N4869A

2N5951
2N5952

2N5486

2N4869A

2N5953

3N163
3N163
3N163

2N4869A
2N5397

2N6085

2N5397

2N5484
1T122
ITl22

3N156A
3N157
3N157A
3N158

2N4868A
2N4869
2N4869A
2N4878
2N4879

2N4868A
2N4869
2N4869A
2N4878
2N4879

2N5398
2N5432

2N5398
2N5432

2N6087
2N6088

2N5433

2N5433

2N6089

2N5434
2N5452

2N5434
2N5452

2N6090
2N6091

2N4880

2N4880

2N5453

2N4937
2N4938

1T131

2N5454

2N6092
2N6441

ITI32
1T132
ITl32

2N5457
2NS458
2N54S9

2N5453
2N5454
2N5457

2N5458

2N6443

2N5459

2N6444

2N5460
2N5461
2N5462

2N5460
2N5461
2N5462

2N6445
2N6446
2N6447

2N5463

2N5463

2N4977

ITl31
1T132
1T122
1T122
2N5433

2N5464

2N5464

2N4978
2N4979
2N5018
2N5019

2N5433
2N4859
2N5018
2N5019

2N5465
2N5471
2N5472
2N5473

2N5465
2N5265
2N5265
2N5265

2N5020

2N2843

2N5474

2N5265

2N4860

2N4939
2N4940
2N4941
2N4942
2N4955

2N4956

"CONSULT FACTORY

2N5248
2N5254
2N5255
2N5256

2N5363
2N5364
2N5391

2N5392

2N5396

2N5199
ITE4416

2N5484
2N5486
2N5486
ITl32
ITl32
ITl30
2N5458

2N5905

2N5911
2N5949

2N6086

2N5484

2SK41
2SK42
2SK43
2SK44

2SK46

3N158A

1T121
1T121
1T122
ITl21
IT121

3N160

1T121
ITl22
1T122
ITl22
1T122

3N166

3N171
3Nl72

2N6448

ITl21
ITl21
1T121
ITl21

2N6451

U310

2N6452
2N6453

2N6454

U310
U310
U310

2N6483
2N6484

2N6483
2N6484

2N6442

XXII

2N4393

2SK37

3N161
3N163
3N164

3N165
3Nl67
3Nl68
3N169
3Nl70

3N173
3N174
3NI7S

2N3822
ITE4092
ITE4416

2N5459

3N189
3N161

3N163
3N163
3N161
3N161
3N163
3N164
3N165
3N166
3Nl61

3N161
3N170

3N170
3Nl71
3Nl72
3N173
3N163

3N170

3NI76

3N170

3Nl77

3N171
3Nl72
3NI72
3Nl72

3NI78

3N179
3N180

ALTERNATE
SOURCE PROOUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

3Nl6!

AD7520SD

3N161
3N161
3N188
3N189

AD7520TD
AD7520UD
AD7521JD
AD7521JN

3N190
3N191
3N207
3N208
3SK22

3N190
3N191
3N190
3N188
2NS486

AD7521KD
AD7521KN
AD7521LD
AD7521LN
AD7521SD

3SK23
3SK28
42T
4360TP
5033TP

2N5397
2N5397
2N4392
2N5462
2N5460

3NlSl
3N182
3N183
3N188
3N189

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

AD7520S0

AH0141D

DG141AP

BFB05

AD7520TD
AD7520UD

AHOl4} 0/883

DG141AP/883B

AH0142CD

DG142BK

AD752IJD

AH0142D
AH0142D/883

DG142AK
DG142AK/8838

BFB06
BF808
BF810
BFa!1

AD7521KD
AD7521KN
AD7521LD
AD7521LN
AD7521SD

AH0143CD

DG143BK

8F81S

AH0143D

DG143AK

BFBIG

AHO 1430/883

BFa17

AH0144CD

DG 143AK/883B
DGl44BK

AH0144D

DG144AK

AD7521TD
AD752lUD
AD7523AD
AD7523BD
AD7523CD

A07521TD
AD752lUD
AD7523AD
AD7523BD
AD7523CD

AH0144D/883

DG144AK/883B

AD7521JN

BF818
BFQ10

~~8g

AH0145CD

OG145BP

AH0145D
AH0145D/883
AH0146CD

DG145AP
DG145AP/883B
DG146BP

BF 13

AD7523JN
AD7523KN
AD7523LN
AD7523SD
AD7523TD

AH0146D

DG146AP
OG146AP/8838

BFQ16
BFQ23

DG151BK
DG 151 AK/883B
DG152BK

AD7523UD
AD7530JD
AD7530JN
AD7530KD

AH0152D
AH0152D/883
AH0153CD
AH0153D

g

BF 14
SF 15

INTERSIL
EQUIVALENT
2N4869
2N4869
2N4868
2N4858
2N48S8
2N4858
2N4858
2N4858
2N4858
U401

U401
U402
U403
U404
U405

BFQ45

U406
IT5912
U403
IT5912
IT5912

OG152AK

2N30S5

AHQ153D/S8a

DG 152AK/883B
DG153BP
DG153AP
DG153AP/883B

21
8FS21A

2N3958
2N3958
2N5199
2N5199

AH0154CD
AH0154D
AH0154D/883
AH0155D
AH0161CD

DG154BK
DG154AK
DG143AK/883B
DG151AK
DG161BP

8FS67

2N3821

BFS67P
BFS68
BFS68P
BFS70

2N3823
2N4416
2N3821

588U
58T
59T
703U
704U

2N4416
2N5457
2N4416
2N4220
2N4220

AD7523JN
AD7523KN
AD7523LN

705U
707U
714U
734EU
734U

2N4224
2N4860
2N3822
2N4416
2N5516

AD7523UO

AD7530KN

75lU
752U
753U
754U
755U

2N434O
2N434O
2N4341
2N4340
2N4341

AD7530LD
AD7530LN
AD7531JD
AD7531JN
AD7531KD

AD7530LD
AD7530LN
AD7531JD
AD7531JN
AD7531KD

756U
A190
A191
A192
A193

2N4340
ITE4416
ITE4416
2N4416
2N5484

AD7531KN

AD7531KN

AD7531LO
AD7531LN
AD7533AD
AD7533BD

AD7531LD
AD7531LN
AD7533AD
AD7533BD

AHOIGID
AHO 1610/883

A194
A195
A196
A197
A198

2N5484
2N5484

AD7533CD
AD7533JN
AD7533KN
AD7533LN
AD7533SD

AD7533CD
AD7533JN
AD7533KN
AD7533LN
AD7533SD
AD7533TD

2N5484
2N5484
2N4416
2N4341

AD7533TD
AD7533UD
AD7541AD
AD7541BD
AD7541JN

AD7533UD
AD7541AD
AD7541BD
AD7541JN

AH5009CN
AH5010CN
AH5012CN
AH5013CN

BFW12

2N5019
2N3823
2N3822
2N4416

AD7541KN
AD7541SD
AD7541TD
AD810
AD8ll

AD7541KN

AH5014CN
AH5015CN

IH5014CPD

BFW13

2N4867

IH5015CPE

AH5016CN
ALD555

IH5016CPE
ICM7555

BFW39
BFW39A

AD3954A

2N5460
2N5461
2N5462
2N3954
2N3954A

ALD556

ICM7556

BFW55

AD3955
AD3956
AD3958
AD589
AD590

2N3955
2N3956
2N3958
ICL8069
AD590

AD812
AD813
AD814
AD815
AD816

AM5011CN
BC264
BC264A
BC264B
BC264C

IH5011CPE

BFW56
BFW61

AD5905
AD5906
AD5907
AD5908
AD5909

2N5905
2N5906
2N5907
2N5908
2N5909

AD818
AD820
AD821
AD822
AD830

BC264D

AD7506/COM/CHIPS
AD7506/MIUCHIPS
AD7506JD
AD7506JD/883B
AD7506JN

IH6116C/D
IH6116M/D
IH6ll6CJI
IHS116CJI/883B.

AD7506KD
AD7506KD/883B
AD7506KN
AD7506SD
AD7506SD/883B

IH6116CJI

A199
A5T3821
A5T3822
A5T3823
A5T3824
A5T5460
A5T5461
A5T5462
AD3954

ITE4416

ITE4391
ITE4392
"ITE4393

IH6116CPI
IH6116CJI/883B

IH6116CPI
IH6116MJI

IH6116MJ1/883B

AD7506TD

AD7523SD

AD7523TD
AD7530JD
AD7530JN
AD7530KD
AD7530KN

AD7541SD
AD7541TD
2N4878
2N4878
2N4878
2N4878
1T124

1T124
1T120A
1T140
1T132

AHO 1460/883
AH0151CD

AH0151 0/883
AH0152CD

~~8~~

2NS459

DG161AP

BFS71

2N3822

DG161AP/883B
DG162BK
DG162AK
DG 162AK/883B

BFS72
BFS73
BFS74
BFS75

2N3823
2N3821
2N4856
2N4857

AH0183CD
AH0163D
AHO 1630/883
AH0164CD
AH0164D

DG163BP
DG163AP
DG163AP/883B

BFS76
BFsn
BFS78
BFS79
BFS80

AHOI64D/8S3

DG 16AAK/883B

AH0162CD
AH0162D
AH0162D/883B

DG164BK

DG164AK
IH5009CPD
IH5010CPD
IH5012CPE
IH5013CPD

2N5458
2N5457
2N5458

BFTlO
BFT11

BFW10
BFWll

BFW54

2N4858

2N4859
2N4860

2N4861
2N4416A
2N5397

IT129

1T120
2N3822
2N3822
2N4860

BFXll
BFX15

2N4224
1T132
1T122

2N5458

BFX36

1Tl31

BFX70

IT122

BFX71
BFX72

1Tl22

BFX78

1T130A

BCYS7
BCY88

1T130A

BCY89

2N4416
1T121
1T122
1T122

2N5520

BF244

2N5486

BFX82

2N5397
2N5019

AD831
AD832
AD833
AD833A
AD835

2N5521

BF244A
BF244B

2N5484

BFX83

2N5019

2N54S5

2N5523
2N5524
2N3954

BF244C

2N5486
2N5486

BFX99
BFY20

ITl20A
IT122
ITl22

AD836
AD837
AD838
AD839
AD840

2N3955
2N3955
2N3956
2N3957
2N5520

BF245B
BF245C

BF246
BF246A
BF246B
BF246C
BF247

2N5638
2N4091

BF247A
BF247B

2N4091

2N5522

IH6ll6MJI
AD7506TD/883B
IH6ll6MJI/883B
AD7507/COM/CHIPS IH6216C/D

AD841

2N5521

AD842

AD7507/MIL/CHIP$

BF245

BF245A

1T122

2N4416

8FY81
BFY82

1T122

2N4416

BFY83

1Tl22

2N4416

BFY84

ITl22

2N5485

BFY85

1Tl22

2N5639

BFY86
BFY91

1Tl22

2N5638

BFY92

1T122
1T122
ITl22
2N4416

IH6216M/D

AH0126D/883

AD7507JD

IH6216CJI

AH0129CD

2N5523
DG126AP
DG126AP/883B
DG129BK

BF247C

2N4091

BN209
BSV22
BSV78
BSV79

AD7507 JD/883B
AD7507JN
AD7507KD
AD7507KD/883B

IH6216CJI/883B
IH6216CPI
IH6216CJI
IH6216CJI/883B

DG129AK
DG 129AK/883B
DG133BK
DG133AK
DG 133AK/883B

BF256

2N5484

BSV80

2N4858A

BF256A
BF2568

2N5484

BSX82

2N4416

C21
cn06
C38

2N3822
2N3821
2N5196

BF320A
BF320B
BF320C

AH0126D

2N4091

AD7507KN

IH6216CPI

AH0129D
AH0129D/883
AH0133CD
AH0133D
AH0133D/883

AD7507SD

AH0134CD
AH0134D

DG134BK

AD7507SD/883B

IH6216M/O
IH6216MJI/8838

AD7507TD
AD7507TD/883B
AD7520JD

IH6216MJI
IH6216MJI/883B
AD7520JD

AH0134D/883
AH0139CD
AH0139D

DG 134AK/883B
DG139BK

BF346

2N5461
2NS462
ITE4392

DG139AK

BF347

J201

AD7520JN
AD7520KD
AD7520KN
AD7520LD
AD7520LN

AD7520JN

AH0139D/883
AH0140CD

DG139AK/883B

BF348

C614

BF800

AH0140D/883

DG140BP
DG140AP
DG140AP/8838

J310
2N4867
2N4867
2N4338

AH0141CD

DG141BP

2N4338

C622

AD7520KO

AD7520KN
AD7520LD
AD7520LN

"CONSULT FACTORY

AH0140D

BF256C
BF320

DG134AK

BF801

BF802
BF804

XXIII

2N4416
2N5461

2N5460

C413N
C610

C611
C612
C613
C615
C620
C621

2N4856A
2N4857A

2N4338
2N5434
2N4392
2N4221

2N4221
2N4221
2N4220
2N4221
2N4220
2N4220
2N4220

ALTERNATE

SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

C623
C624
C625
C650
C651

2N4220
2N4220
2N4220
2N4220
2N4220

D123AL
D123AP

O123AL

DG152AP

OG152AK

D123AK

DG152BP·

DG152BK

D1238P
D123BP
D125AL

D123BK
D123BJ
D125AL

DG153Al

DGlS3AL

DG153AP

OG153AP

DG153BP

C652
C653
C6690
C6691
C6692

2N4220
2N4220
2N4341
2N4341
2N4339

DGl54Al

C673
C674
C680
C680A
C681

2N4341
2N4341
2N4338
2N4338
2N4338

C681A
C682

2N4338

01422

2N4339

D2T2218

2N4869
1Tl29

C682A

2N4339

D2T2218A

ITl29

DG164AL

C683

2N4339

D2T2219

1Tl29

DG164AP

C683A

2N4339

D2T2219A

ITl29

DG164BP

DG164AL
DG164AK
DG164BK

C684

2N4220

DG180AA
DG180AL

DG180AA
DG180AL

DG180AP

DG180AK

DG180BA
DG180SP

DG180BA

D125BP

D125AP
D125BK

D129AL

D129AL

D129AP
DI29BP

D129AK
D129BK

01301
01302

2N4222
2N4220
2N4220
2N4868
2N3822

D125AP

01303
01420
01421

C684A

2N4220

C685

2N4220

D2T2904
D2T2904A
D2T2905

ITl39
ITl39
ITl39

C685A

2N4220

D2T2905A

1Tl39

C80

2N4338

D2T918

ITl29

C81
C84
C85
C91
C92

2N4338

DA102

2N4338
2N4338
2N4858

DA402
DACI020LCD
DAC1020LD

2N6196
2N5196
AD7520LD
AD7520UD

2N4091

DAC1021LCD

AD7520KD

C93
C94
C94E
C95
C95E

2N4393

DAC1021LD

AD7520TD

2N5457

DACI022LCD
DACI022LD
DACl218LCD

AD7520JD

2N5467

2N5459

DAC1218LCN

AD7541LN

DAC1218LCN

AD7541KN
AD7541AD

C98E
CA555
CA556

2N5484
2N3822
2N3822
ICM7555
ICM7556

CC4445
CC4446

2N5432
2N5434

CC697

2N4856

CD22001H

C96E
C97E

CD22015E
CF2386
CF24
CFMl3026
CM600
CM601

2N5457

DAC1219LCD

DG153BP

DG154AL
DG154AK
DG154BK
DG161Al
DG161AP

DGI9IBP
DG200AAA
DG200AAK
DG200AAL
DG200ABA

OGl91BK
DG200AA
DG200AK
DG200AL
DG200BA

DG161BP

DGIGIBP

DG200ABK

DG162AL

DG162AL
DG162AK
DG162BK
DG163AL

DG200ACJ

DG163AP

DG163AP

DG163BP

DG163BP

DG211CJ
DG212CJ
DG381AA
DG381AK

DGIG2BP
DG163AL

DG381AP
DG381BA
DG381BK
DG381BP
DG38lCJ
DG384AK

DG384AP
DG384CJ
DG387AA

DGl81AP
DG181BA
DG181BA
DGl8lBP

DGl81AK
DGM181BA
DGl81BA
DGM181CJ
DGM181BK

DG387BP

DG181BK
DGM182AA
DG182AA
DGMIB2AL

DG390BP

DG182AL

DG390CJ

DGM182AK
DG182AK

DG503

DGl81BP
DG181BP
DG182AA

DGMIBIAK

DAC1220LD
DAC1221LCD
DAC1221LD
DAC1222LCO

AD7521KD
AD7521TD
AD752IJD

DG182AP
DG182AP
DG182BA

DGM182BA

ICMl424C
ICM7051A

DAC1222LD

AD7521SD

DG182BA

DG182BA

DG123AL

DG123AL

DG182BP

DGM182CJ

2N5458
2N3824

DG123AP
DG123BP
OG125Al
DG125AP

DG123AP

DG182BP

DG123BP

DG182BP

DGM182BK
DG182BK

DG125Al
OG125AP

DG183AL
OG183AP

DG125BP

DG125BP

DG183BP

2N4091

DG126AK

DG126AP

2N4091
2N4093
2N4093

DG126AL

DG126AL

DG126BP

DG126BP

DG129AL

DG129AL

DG184AL
DGl84AL
DG184AP
DG184AP

CM642

2N4093

DG129AP

DG129AK

DG184BP

CM643
CM644

2N4092

DG184BP

2N4092

DG129BK
DG133AL

CM645

2N4092

DGl29BP
OG133AL
DG133AP

DGl33AK

DG201AK
DG201CJ

DGM181AA
DG181AA
DGM181AL

DG181AL

DG184BP
DG185AL
DG185AL
DG185AP

2N4092

DG133BP

DG133BK

CM647

2N4091

DG134AL

DG134AL

CM650

2N5432

DG134AK
DG134BK
DG139AL

DG185AP

DG384BK

DG384BP

DG387AK
DG387AP
DG387BA
DG387BK
DG390AK
DG390AP
DG390BK

DGMlS48K
DG184BK

DG5044CK
DG5045AK
DG5045CJ
DG5045CK

IH5044CJE
IH5045MJE
IH5045CPE
IH5045CJE
IH6116MJI

DGM185AL
DG18SAL
DGMl85AK

DG506AAK

DG18SAK
DGM185CJ
DGM185BK
DG185BK
DG186AA

DG506ABK

DG507ACJ

IH6116CJI
IH6116CPI
IH6216MJI
IH6216CJI
IH6216CPI

DG186Al
OG186AP
DG186BA
DG186BP
DG187AA

DG508AAK
DGS08ABK
DG50SACJ
OG509AAK
DG509ABK

IH6108MJE
IH6108CJE
IH6108CPE
IHS208MJE
IH6208CJE

DG187AL
DG187AK
OG187BA
DG187BK
DG188AA

DG509ACJ
OG5140AK
DG5140CJ
DGS140CK
DG5141AK

IH6208CPE
IH5140MJE
IH5140CPE
IH5140CJE
IH5141MJE

DG5141CJ
DG5141CK
DG5142AK
DG5142CJ
OG5142CK

IH5141CPE
IH5141CJE
IH5142MJE
IH5142CPE
IH5142CJE
IH5143MJE
IH5143CPE
IH5143CJE
IH5144MJE
IH5144CPE

2N5433

DG139AP
DGl39BP

DG139AK
DG139BK

DG185BP

2N5433
2N5433

DGl40AL
DG140AP

DG186AL

2N5433

OGl40AL
DGl40AP

CM860

2N486SA

DGl40BP

DGl40BP

DG186BA

CMX740
CP640

2N5432
2N4091

DG141AP

DG141AP

DG187AA

CP643
CP650
CP651
CP652
CP653

2N5434
2N5432

DG141BP

DG141BP

OGl42Al

2N5433
2N5433
2N5433

DG142AP
DG142BP

DGl42AL
DGl42AK
DG142BK

DG187AL
DG187AP

DG143AL

DG143AL

DG188AA

01101

2N3821
2N3821
2N4338
2N3821

DG143AP
DG143BP

DG143AK

DG143BK

DG188AL
DG188AP

DGl44AL

DGl44AL

DG188BA

DG188Al
DG188AK
DG188BA

DG144AP

DGl44AK

DG188BP

DG188BK

01178

2N3821

DG144BP

DGI44BK

DG189AL

OGl89AL

01179
01180
01181
01182
01183

2N4338

DG14SAl

DG5143AK

DG145AP

DG189BP

DG145BP

OG145BP

DG189AP
DG189BP
DG190AL

DG189AP

2N3S22
2N4338
2N4338

DG145AL
DG145AP

OGMl90AL

DG5143CJ
DG5143CK

DG146AL

DG146AL

DG5144AK

DGl46AP

DG146AP

DG190Al
DG190AP

DG190AL

2N4341

DGMl90AK

DG5144CJ

01184
01185
01201
01202
01203

2N4340
2N4339

DG146BP

DG146BP

DG190AP

DG190AK

DG151AL

DG151AL

DGl90BP

DGM190CJ

2N4224
2N3821

DG151AP
DG151BP
DG152AL

DG151AK
DG151BK
DG152AL

DG190BP

DGM190BK
DG190BK
DGM191AL

DG5144CK
OG5145AK
DG5145CJ

01102
01103

01177

2N4220

"CONSULT FACTORY

DGl90BP

DG191AL

XXIV

DGM191AK
DGM191AK
DGM190BK
DGM190BK
DGM190CJ

IH5043MJE
IH5043CPE
IH5043CJE
IH5044MJE
IH5044CPE

CM800
CM856

DGl87BA
DGIS7BP

DGM188AK
DGM188AK
DGM187BA
DGM187BK
DGM187BK

DG5043AK
DG5043CJ
DG5043CK
DGS044AK
DG5044CJ

CM697

DG186BP

DGM185AK
DGM184BK
OGM184BK
DGMl84CJ
DGM188AA

DGMl84AL
DG184AL
DGMl84AK
DG184AK
DGM184CJ

CM653

DG141AL

DGM181BA
DGMl81BK
DGM181BK
DGM181CJ
OGM185AK

IH5041CPE
IH5041CJE
IH5042MJE
IH5042CPE
IH5042CJE

2N5433

DG141AL

DGM182AA
DGMl82AK
DGM182AK

DG5041CJ
DG5041CK
DG5042AK
DG5042CJ
DG5042CK

2N5432

DG186AP

DG212CJ

DG183AP
DG183BP

DG183AL

CM652

DG186AA

DG2llCJ

AD503
IH5040MJE
IH5040CPE
IH5040CJE
IH5041MJE

CM6S1

DGlS5BP

DG201BK

DG5040AK
DG5040CJ
DG5040CK
DG5041AK

DG134AP
DG134BP
OG139AL

DG185BP

DG2QOBK
DG200CJ

DG201ABK
DG201ACJ

DG181AL

DG181AA

CM602
CM603
CM640
CM641

CM646

DG180BK

DGM191CJ
DGM191BK

DG201AAK

DG181AL
DG181AP

DG181AA

DG182AA
DG182AL
DG182AL

2N4092
2N4091

AD7541JN

DG191AL
OGM191AK

DG191AK

AD7521LD
AD7521UD

2N4858

DAC1219LCN
DAC1220LCD

DG191AL
DG191AP

DGl62AP

..>

INTERSIL
EQUIVALENT

DG191AP
DGl91BP
DGI9IBP

DG154AP
DG1548P
OG161AL
DG161AP

AD7520SD
AD7541BD

ALTERNATE
SDURCE PRODUCT

DG506ACJ
DG507AAK
DG507ABK

DG5145CK

IHS144CJE
IH5145MJE
IH5145CPE
IH5145CJE

DN3066A

2N3821

ALTERNATE
SOURCE PRODUCT
ON3067A
ON3068A
DN3069A
DNJ010A
DN3071A

ON3365A
DN3365B
DN3366A
DN3366B
DN3367A

INTERSIL
EQUIVALENT
2N4338
2N4338
2N3822
2N3821

2N4338

ALTERNATE
SOURCE PRODUCT

INTERSIL
EjlUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

E411
E412
E413
E414
E415

IT5911
IT5911
2NS454
2N3956
2N3957

FM3956
FM3957
FM3958
FP4339
FP4340

2N3956

HII-0507A-8

2N3957
IT5911
2N4339
2N4340

Hll·0508·2
HI 1-0508-5
HIl-0508-8
HIl·0508A~2

IH5216MJI/8S3B
IH610BMJE
IH610BCJE
IH6108MJE/8838
IH510BMJE

£420

IT5911
IT5912
J309(X2)
J310(X2)
U401

FT0654A
FT0654B
FT0654C
FT0654D
FT3820

2N5486
2N5486
2N4221
2N4221
2N5460

HII-0508A-5
HII-050SA-8
HI1-0509-2
HI1-0509-5
HI 1·0509·8

IH5108IJE
tH5108MJE/8838
IH6208MJE
IH6208CJE
IH6208MJE/8838

2N4220
2N4091
2N3686
2N4091
2N3687

E421
E430
E431
E5M25

2N5019

HIl-0509A-2

IH5208MJE

2N4093
2N5457

2N5019
aN161
3N163
G1l8Al

HIl-0509A·5

FT703
FT704
G118Al

HIl-0509A-8
HIl-5040-2
HIl-5040-5

IH520BIJE
IH5208MJE/8838
IH5040MJE
IH5040CJE

2N5459
2N5458
2N5432
2N5434
2NS432

G118AP
G123AL
G123AP
GETS4S7
GET54S8

G1l8AK
G123Al
Gl23AK
2NS457
2NS4S8

HIl-S040-8
HIl-5041·2
Hll-S041-5
Hll-S041-8
HI 1-5042-2

IH5040MJE/8838
IH5041MJE
IH5041CJE
IH5041MJE/8838
IH5042MJE

ESM4448
FE0654A
FE0654B
FElOO
FElOOA

2N5434
2N4386
2N5485
2N3821
2N3821

GET54S9
HA2720
HA7807
HA7809
HD43871

2N5459
ICL8021
ITl32
ITl32
ICM70S0H

HI 1-5042·5
HII-5042-8
HI 1-5043-2
HII-5043-5
HI 1-5043-8

IH5042CJE
IH5142MJE/883B
IH5143MJE
IH5143CJE
IH5143MJE/883B

2N4339
2N4220
2N4338
2N4220
2N4338

FE 102
FEl02A
FE104
FE104A
FE1600

2N4119
2N4119
2N4118
2N4118
2N4092

HD43871
HDIGI030
HEP801
HEP802
HEP803

ICM70S0G
3N163
2N3822
2N5484
2N5019

HIl·S044·2
HIl-5044-5
HIl-5044·8
HII-5045·2
HIl-5045·5

IH5144MJE
IH5144CJE
IH5144MJE/883B
IH5145MJE
IH5145CJE

DNX2
DNX3
DNX4
DNX5
DNX6

2N4338
2N4338
2N4869
2N4868
2N4338

FE200
FE202
FE204
FE300
FE302

2N3821
2N3821
2N3821
2N3822
2N3821

HEPF0021
HEPFl035
HEPF2004
HEPF2005
HI0-0201·6

2NS484
J176
2N5484
2N5459
DG201C/D

HIl-S045·8
HIl-5046·2
HII-5046-5
HII-5046-8
HI1-5047·2

IHS14SMJE/8838
IH5046MJE
IH5046CJE
IH5046MJE/8838
IH5047MJE

DNX7
DNX8
DNX9
D5OO26
DS0026

2N4416
2N4416
2N4339
ICL7667
ICl7667

FE304
FE3819
FE4302
FE4303
FE4304

2N3821
2N5484
2N5457
2N5459
2NS458

HI0-0381-6
HI0-0384·6
HI0-0387·6
HI0-0390-6
HI0-OS06-6

DGM181C/D
OGMl84C/D
DGM187C/D
DGM190C/O
IH6116C/O

HII-5047·5
HI1-5047·8
HII-5049-2
HI1-5049-S
HIl-5049-8

IH5047CJE
IHS047MJE/8838
IHS149MJE
IHS149CJE
IHS149MJE/8838

DU4339
DU4340
ElOO
ElOl
El02

2N5397
2N5398
2NS458
J204
2N5457

FES24S
FE5246
FE5247
FES457
FES458

2N4416
2N5484
2N5486
2N5457
2N5458

HIO-OS06A-6
HIO-OS07-6
HIO-0507A-6
HIO-OS08-6
HIO-0508A-6

IHS116C/D
IH6216C/D
IHS216C/D
IH6108C/D
IHSI08C/D

HIl-S050-2
HI1-5050-5
HIl-5050-8
HIl-5051-2
HIl-50S1-5

IHS1SQMJE
IH5150CJE
IH5150MJE/8838
IH5151MJE
IH51S1CJE

El03
El05
El06
E107
El08

2N5459
J105
Jl06
J107
JI05

FE5459
FES484
FE5485
FE5486
FF400

2N5459
2NS484
2N5485
2N5486
2N5457

HIO-0509-6
HIO-0509A-6
HIO-5040-6
HIO-5041-6
HIO-5042-6

IH6208C/D
IH5208C/O
IH514DC/D
IHS141C/O
IH5142C/D

HIl-5051-8
HI2-0200-2
HI2-0200-4
HI2-0200-5
HI2-02oo-8

IH5151 MJE/8838
DG200AA
DG200BA
DG2008A
DG2ooAAl883B

El09
EIIO
Elll
El115
ElllA

J106
JI07
JIll
ICMll15A
Jill

FMI100
FMl100A
FMll01A
FMl102
FMII02A

2N3954A
2N5906
2N5906
2N3954
2N5906

HI0-5043-6
HI0-5044-6
HI0-5045-6
HI0-5046-6
HIO-5047-6

IH5143C/O
IH5144C/O
IH5145C/D
IH5046C/D
IH5047C/O

HI2-0381-2
HI2-0381-5
HI2-03BI-B
HI3-0200-5
HI3-020l-5

DGM182AA
DGM1818A
DGMI81AA1B83B
DG200CJ
DG201CJ

E112
E112A
E1l3
E113A
Ell4

J112
J1l2
J113
J1l3
J204

FMl103
FMll03A
FMll04
FMl104A
FMll05

2N3955
2N5908
2N3957
2N5909
2N3954A

HIO-5049-6
HIO-5050-6
HI0-5051-6
HIl-0200-2
HU-0200-4

IH5149C/O
IH5150C/O
IH5051C/O
OG200AK
DG200BK

HI3-0381-5
HI3-0384-5
HI3-0390-5
HI3-0506·5
HI3-0S06A-5

DGM181CJ
OGM184CJ
DGM190CJ
IH6116CPI
IH5116CPI

Ell51
E1426
El74
El75
E176

ICM11158
ICM7050U
J174
J17S
J176

FMll05A
FMII06
FMI106A
FMl107
FMII07A

IT500
2N3954A
IT500
2N3954
1T500

HIl-0200-S
HI 1-0200-6
Hll-0200-8
HIl-0201-2
HIl-0201-4

DG200BK
DG200C/D
DG200AK/883B
OG201AK
DG2018K

HI3-0507-5
H13-0507A-5
H13-OS08-5
HI3-0S08A-5
HI3-0S09·S

IH6216CPI
IH5216CPI
IH6108CPE
IH5108CPE
IH6208CPE

EI77
E201
E202
E203
E204

JI77
J201
J202
J203
J204

FMII08
FMI108A
FMl109
FM1109A
FMl110

2N3955
ITS02
2N3957
1T503
2N3955

HII-0201-5
HII-0201-8
Hll-0381-2
HI1-0381-S
HII-0381-8

DG20l8K
DG201AK/8838
OGM182AK
DGM181BK
OGM 182AK/8838

HI3·0509A-5
ICl7611
ICl7612
ICl7621
tCl7631

IH5208CPE
ICl76l1
ICl7612
ICl7621
ICl7631

E210
E211
E212
E230
E231

2N5397
2N5397
2N5397
2N4867
2N486B

FMl110A
FMllll
FM1111A
FMll12
FM1200

2N5908
2N3957
2N5909
2N5196
2N3954

HII-0384-2
HI 1-0384-5
HIl-0384-8
HIl-0387·2
HIl-0387-5

DGM185AK
DGM1848K
OGM185AK/8838
DGM188AK
DGM187BK

ICl7641
ICl7642
ICL7650
ICL7652
ICL7660

ICl7641
ICl7642
ICL7650
ICL7652
ICL7660

E232
E270
E271
E300
E304

2N4869
J270
J271
2NS397
2N5486

FM1201
FM1202
FM1203
FM1204
FM120S

2N3954
2N3954
2N3955A
2N3955
2N3954

HIl-0387-8
HIl·0390-2
HI1-0390-5
HI 1-0390-8
HIl-0506-2

DGM188AK/8838
OGM191AK
DGM190BK
DGM191AK/883B
IH6116MJI

ICL7663
ICL7665
ICL8069
ICM7240
ICM7242

ICL7663
ICL7665
ICL8069
ICM7240
ICM7242

E305
E308
E309
E310
E311

2N5484
J308
J309
J310
J310

FM1206
FM1207
FM1208
FM1209
FM1210

2N3954
2N3954
2N3955A
2N3955
2N3955A

HIl-0506-5
HIl-OS06-8
HIl-0506A·2
Hll·0506A-5
HIl-0506A-8

IH6116CJI
IH6116MJII883B
IH5116MJI
IH51161J1
IHSl16MJI/8838

ICM7250
lCM7555
lCM7556
ICNOOM7555
10100

ICM7250
ICM7555
ICM7556
ICM7555
10100

E312
E400
E401
E402
E410

2N5397
2N3955
2N3955
2N3957
2N3955

FM1211
FM3954
FM3954A
FM395S
FM3955A

IT5911
2N39S4
2N3954A
2N39S5
2N3955A

HIl-0507-2
HIl-0507-5
HIl-OS07-8
HIl-0507A-2
HIl-0507A-5

IH6216MJI
IH6216CJI
IH6216MJI/8838
IH5216MJI
IH52161J1

ID10l
IMF3954
IMF3954A
IMF3955
IMF3955A

IDlOl
2N3954
2N3954A
2N3955
2N3955A

DN33678
DN3368A
DN33688
DN3369A
DN3369B

2N4091
2N4341
2N4221
2N4339

ESM25A
E5M4091
ESM4092
E5M4093

2N4220

ESM4302

DN3370A
DN3370B
DN3436A
DN3436B
DN3437A

2N4338
2N4338
2N4341
2N4222
2N434O

ESM4303
E5M4304
ESM4445
ESM4446
E5M4447

DN34378
DN3438A
DN3438B
DN3458A
DN34588

2N4220
2N4338
2N4339
2N4341
2N4222

DN34S9A
DN34598
DN3460A
DN3460B
DNXI

"CONSULT FACTORY

U401
2N4091
2N4092

FT3B20
FT3909

xxv

ALTERNATE

SOURCE PRODUCT

INTERSIL
EQUIVALINT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

2N3956
2N3957
2N3958
IMF5911
IMF5912

ITE2913

IMF3958
IMF5911
IMF5912

ITE2915
ITE2916
ITE2917

1Tl22
1T122
ITl20
ITl20
ITl22

JI13A
J1l3A·18
J114
J1401
J1402

J113
J113
2N5555
IT501
IT502

J4869
J4869A
J4869RR
J5103
JS104

IMF648S
1Tl00
1Tl01
1Tl08
ITl09

IMF6485
1Tl00
ITlOI
ITE4416
ITE4416

ITE291S
ITE2919
ITE2920
ITE2936
ITE2937

1Tl22
1Tl20
ITl20
1Tl20
1Tl20

J1403

IT503
ITS03
ITS04
ITS05
JI74

JS105
J5163
K114·18
K210·18
K211·18

2N5486

J140S
J1406
J174

1Tl20
1T120A
ITl21
ITl22
ITl26

1Tl20
1Tl20A
1Tl21
1Tl22
1Tl26

ITE2972

ITl22
ITI22
ITI20
1Tl20
1Tl20

J174·18
J175
J17S·18
J176
J176·18

J174
J175
J17S
J176
J176

K212·18

ITE2974
ITE2975
ITE2976

K304-18
K305·18
K308·18

2N5397
2N5397
2N5486
2N5484
J308

ITl27
ITl28
ITl29
ITl30
1T130A

1Tl27
1Tl28
1Tl29
1Tl30
1Tl30A

ITE2977
ITE2978
ITE2979
ITE3066
ITE3067

1Tl20
1T120
1Tl20
2N3685
2N3686

JI77
JI77·18
J201
J201-1S
J202

JI77
JI77
J201
J201
J202

K309-18
K310-18
KE3684
KE3685
KE3686

J309
J310
2N3684
2N3685
2N3686

ITl31
ITIl2
ITl36
1Tl37
1Tl38

1Tl31
1T132
1Tl36
1Tl37
1Tl3S

ITE306S

2N3687

Ill37
1Tl38
1Tl39
1Tl37

J202·1S
J203
J203·18
J204
J204·18

J202
J203
J203
J204
J204

KE3687

ITE3347

ITE3348
ITE3349
ITE3350

KE3970
KE3971
KE3972

2N3687
2N3823
ITE4391
ITE4392
ITE4393

1Tl39
1Tl40
1T1700
1T1701
ITl702

1Tl39
ITl40
ITl700
3N172
3NI63

ITE3351
ITE3680
ITE3S00
ITE3802
ITE3804

1Tl3S
1T120
1T132
1Tl32
ITl30

J210
J211
J212
J230
J231

2N5397
2N5397
2NS397
2N4867
2N4868

KE4091
KE4092
KE4093
KE4220
KE4221

ITE4091
ITE4092
ITE4093
2N5457
2N5459

1Tl750
IT2700
IT2701
IT400
IT500

1T1750

ITE3806
ITE3S07
ITE3808
ITE3809
ITE3810

1Tl32
1Tl32
1T132
1T132
ITl30

J232

3N165
2N4392
ITSOO

J270·18
J271
J271-18

2N4S69
J270
J270
J271
J271

KE4222
KE4223
KE4391
KE4392
KE4393

2N5459
J204
ITE4391
ITE4392
ITE4393

ITSOOP
IT501
ITS01P
IT502
ITS02P

ITSOO
IT501
IT501
IT502
ITS02

ITE3811
ITE3907
ITE3908
ITE4017
ITE4018

ITl30
1Tl20
1Tl20
1Tl39
1Tl39

J300
J304
J305
J308
J309

2NS397
2N5486
2N5484
J308
J309

KE4416
KE48S6
KE4857
KE48S8
KE4859

ITE4416
ITE4391
ITE4392
ITE4393
ITE4391

ITS03

ITS03
ITS03
ITS04
ITSOS
ITS50

ITE4019

J310
J31S
J316
J317
J3970

KE4860

ITE4021
ITE4022
ITE4023

1Tl39
ITl39
1Tl39
1Tl39
1Tl37

J310

IT504
IT50S
ITS50
IT5911
ITS912
ITC2972
ITC2973
ITC2974

ITS911
IT5912
1Tl22
1Tl22
1Tl20

ITE4024
ITE402S
ITE4091
ITE4092
ITE4093

1Tl37
1Tl37
ITE4091
ITE4092
ITE4093

J3971
J3972
J401
J402
J403

ITC297S
ITC2976
ITC2977
ITC2978
ITC2979

1Tl20
ITI20
1Tl20
1Tl20
1Tl20

ITE4117
ITE4118
ITE4119
ITE4338
ITE4339

2N4117
2N4118
2N4119
2N4338
2N4339

J404
J40S
J406
J4091
J4092

ITC3347
ITC334S
ITC3349
ITC33S0
ITC33S1

1Tl37
1Tl3S
ITl39
ITl37
1Tl38

ITE4340
ITE4341
ITE4391
ITE4392
ITE4393

2N434O
2N4341
ITE4391
ITE4392
ITE4393

ITC33S2
ITC3800
ITC3802
ITC3804
ITC3806

1Tl39
ITI32
1T132
1Tl30
1Tl32

ITE4416

ITE4416

ITE4867

2N4867

ITE4868
ITE4869
JlOO

2N4868
2N4869
2NS4S8

J4221
J4222
J4223

ITC3807
ITC3808
ITC3809
ITC3810
ITC3811

1T132
1Tl32
1Tl32
1Tl30
1Tl30

JIOI
JI02
JI03
Jl05
Jl05-IS

2N4338
2NS4S7
2N5459
Jl05
Jl05

ITC4017
ITC4018
ITC4019
ITC4020
ITC4021

1Tl39
1Tl39
1Tl39
1T139
1Tl39

JI06
Jl06-IS
JI07
J107·18
JIOS

JI06

ITC4022
ITC4023
ITC4024
ITC4025
ITE2453

1Tl39
1Tl37
1Tl37
1Tl37
ITl20

ITE2639
ITE2640
ITE2641
ITE2642
ITE2643
ITE2644
ITE2720
ITE2721
ITE2722
ITE2903

IMF3956
IMF3957

ITS03P

3Nl65

ITE2914

ITE2973

ITE4020

J1404

J270

K300-18

KE3823

2N4869
2N4869A
2N4869

2N5484
2NS48S
2NS486

2NS55S
2NS397
2N5397

ITE4392

2NS397

KE4861

ITE4393

U309
U310
ITE4391

KES10
KES103
KES104

ITE4393
J204
ITE4416

ITE4392
ITE4393
IT501
IT502
IT503

KES10S
KE511
KH5196
KH5197
KH5198

ITE4416
ITE4392
2N5196
2N5197
2N5198

IT503
ITS05
ITE4091
ITE4092

KH5199
KS6183
KS524OBOIH
KS524OBOlJ
KS524OBIOH

2NS199
ICM7269
ICM724SB
ICM7245A
ICM72450

J4093
J410
J411
J412
J420

ITE4093
IT502
IT503
ITS03
ITS911

KS524OBI2H
KSS240B20H
KS524OU01E
LOF603
LOF604

ICM7245E
ICM7245F
ICM724SU
2N4221
2N4221

J421

IT5912
J202
J203
J202

LOF60S
LF1l201D
LFl1201D/883
LF115080
LFlI508D/8B3

2N4221
DG201AK
DG201AK/8B38
IH6108MJE
IH6108MJE/8B38

J4224
J430
J4302
J4303
J4304

J202
J309(X2)
2N4302
2N5459
2N5458

LFll509D
LFlI5090/883
LFI32010
LFl320lN
LFl35080

IH6208MJE
IH6208MJE/8B3B
OG2018K
DG20lCJ
IH6108CJE

J431

J4220

IT504

J204

J433

~~~~W)

LFI3508N

J106

JI07
JI07
JI05

J4338
J4339
J4391

2N5457
2N5457
ITE4391

LFI3509N
LM113
LMI14

IH610SCPE
IH6208CJE
IH620SCPE
ICL8069
1Tl20

J108·18
JI09
J109·18
JI10
Jllo-18

JI05
JI06
JI06
JI07
JI07

J4392
J4393
J4416
J4856
J4857

ITE4392
ITE4393
ITE4416
ITE4856
ITE4857

LMI14A
LMI14AH
LMI14H
LMI15
LM115A

1Tl20A
ITl20A
1T120
1Tl20
1T120A

1Tl20
1Tl22
1T122
1Tl20
1Tl22

Jill
JI1I·18
Jl11A
JI1IA-18
JI12

Jill
Jill
Jill
Jill
J112

J4858
J4859
J4860
J4861
J4867

ITE4858
ITE4860
ITE4861
2N4867

LM1l5AH
LM115H
LM185
LMI94
LM394

1Tl20A
ITI20
ICL8069
ITl20A
1Tl20A

1Tl22
1Tl20
1Tl22
1Tl20
1Tl22

J112·18
J112A
J112A·18
JI13
J113·18

J112
JI12
J112
JI13
JI13

J4867A
J4867RR
J4868
J4868A
J4868RR

2N4867A
2N4867
2N4868
2N4868A
2N4868

LM4250
LM4250
LM555
LM556
LMC555

LM4250
ICL8021
ICM7555
ICM7556
ICM7555

"CONSULT FACTORY

XXVI

ITE4859

LF13509D

ALTt:RNATE
SOURCE PRODUCT

INTI!RSIL
I!QUIVALI!NT

ALTERNATE
SOURCE ....ODUCT

lMC556
lMC668
l53069
l53070
lS3071

ICM7556

lS3458
l53459
lS3460

J204
J204
J204
2N3684
2N3685

M58436-DOIP
M58437-DOIP
MA7807
MA7809

LS3686

2N3686
2N3687
2N5484
2N5457
2N5458

lS3823
l53921
l53922
l53966
l53967

2N5458
2N3921
2N3922
ITE4416

lS3684
lS3685
l53687
lS3819
lS3821
lS3822

ICl7650
2N5458
2N5458
2N5458

ITE4416

M511
M511A

INTERSIL
EQUIVALENT

3Nl72

MS17

3N172
3N163

M58434P
M58435P

ICM11158

ICM7038D

ALTERNATE
SOURCE ~RODUCT

M08002

M0800~

MD918
M0918A
M0918B

MF818
MFE2000

MFE2005

2N5459
2N4341

MFE2006
MFE2007
MFE2008
MFE2009
MFE2010

MEF3684

2N4339
2N4341
2N4339
2N4338
2N3684

MEF3685
MEF3686
MEF3687
MEF3821
MEF3822

2N3685
2N3686
2N3687
2N3821
2N3822

MFE2012

MAT·OIAH
MAT-OIFH
MAT-OIGH
MAT-OIH
MAX232
MAX420

1T140
lT140
1T140
ICl232
lCl420

MEF3070
MEF3458
MEF3459
MEF3460

MAX663
MAX665
MAX8211
MAX8212

lCL7663

MEF3069

IT£4416

MBI03

ICM7245E

MEF3823

ITE4416
J204
J202
J203

M8105
M8107
M8108
M8143

ICM7245U
ICM72450
ICM7245E
ICM7245A

MEF3954
MEF3955
MEF3956
MEF3957

l54223
l54224
lS4338
lS4339
l54340

J202
J202
2N5457
2N5457
2N5457

M8144
MB510
M8511
MB512
MB513

ICM7245F
ICM1115B
ICM7050H
ICM7050H
ICM7050G

MEF3958
MEF4223
MEF4224

LS4341

2N5458
ITE4391
ITE4392
ITE4393

MB521

MB522
MB531
MB533
MB541

IT59068
IT59068
ICM7050H
ICM7050H
ICM7052

ITE4416

MF803

MFE2004

LS3968
lS3969
l54220
L$4221
l54222

lS4391
lS4392
lS4393
lS4416

MEM9558
MF510

2N5457

M0982
M0984
MEFI03
MEFI04

MBlOl

1T120
ITl22
1T122
1T122
1T122

ALTI!RNATE
SOURCE ....ODUCT

In3g
1T139

ICM7050G
lCM7070l
1T132
1T132
ITl40

ICl7665
ICl8211
ICl8212
ICM7245B

INTERSIL
EQUIVALENT

MFE2001

MFE2011
MFE20l2
MFE2093

MFE2094
MFE2095
MFE2133

2N3823
2N3954

MFE2912

2N3955

MFE3003

MFE3002

INTI!RSIL
EQUIVALENT

3NI90
2N4092
2N4338
2N4858
2N4416
2N4416
2N4093
2N4092
2N4091
2N4860
2N4859
2N4859
2N4859
2N5433
2N5434
2N5433
2N4338
2N4339
2N4340
2N4860
2N5433
3NI70
3NI64

2N3956

MFE3020

3NI66

2N3957

MFE3021

3NI66

MFE4007

MEF4391
MEF4392

2N3958
2N4223
2N4224
ITE4391
ITE4392

2N3686
2N3686
2N3685
2N2608
2N2608

MEF4393
MEF4416

ITE4393
ITE4416

MEF4856
MEF4857
MEF4858

2N4856
2N4857
2N4858

MFE4008
MFE4009

MFE4010
MFE4011
MFE4012

MFE823
MHW590
MJ41
MJ6

2N2609
ITl700
A0590
ICMI424C
ICM7220

lS4856
lS4857
lS4858
lS4859
lS4860

ITE409 I
ITE4093
ITE409 I
ITE4092

MB542
MB7B
MCC14440
MCCl4483
M01120

ICM7052
ICM7245U
ICMI424C
ICM7210
1T122

MEF4859
MEF4860
MEF4861
MEF5103
MEF5104

2N4859
2N4860
2N4861
ITE4416
IT[4416

MM452F

lS486 I
lS5103
lS5104
lS5105
lS5245

ITE4093

M01121

1T122

MEF510S

MM455H

MM455H

2N5484
2N5485
2N5486
ITE4416

M01122

1T122
1T139
1T129
1T139

MEF5245
MEF5246

ITE4416
ITE441G
2NS484

MM550H

MM550H

MEF5248

2N5486
2N5486

2N5484

M02218
M02218A
M02219

1T129

MM555H
MMFI
MMF2

1T129

MEF5284
MEF5285
MEF5286
MEF5561

2N5485
2N5486

MD2219A

U401

MMF3

M02369

1T129

MMF4

lS5246
lS5247
lS5248
lS5358
lS5359
LS5360

lS5361
lS5362
LS5363

lS5364
lS5391
lS5392
lS5393
lS5394
lS5395

ITE4092

2N5486

2N5486
J204
J204
J202
J202
J203
J203
J203
2N4867A

MOl123

M01129
M01130

1T129

1T129

MEF5562

U402

MD2369A

1T129

MEF5563

MEM511

U403
3NI72

MD2904

1T122
1T139

MEMSIIA

3Nl72

M02904A
M02905

1T139
1T139

MEM511C

3NI72

MEM517

M02905A

1T139

2N4868A

MD2974

M02975

2N4869A

M02978

1T120
1T120
1T120

2N4869A

M02979

1T120

l55396
lS5457
lS5458
lS5459
lS5484

2N5458
2N5459
2N5484

M03251A

lS5485
lS5486
lS5556
lS5557
lS5558

2N5485
2N5486
2N3685
2N3684
2N3684

M03409
M03410
M03467

1T139

M03725
M03762

1T129
1T139

LS5638

2N5638

M04957

ITl32

lS5639

2N5639
2N5640
ICl7660
ICl7652

M05000

1T132

MD5000A

1T132
1T132

LS5640

lTCI044
lTCI052

2NS484

M02369B

2N4869A

2N4869A
2N5457

MEF5247

MD3008

M03250
M03250A
MD3251

M05000B
M07000

1T120
1T132

MKIO
MM400H
MM4S1H

MM4520

MM5S1H

MM5S1H

MM5520

MM552J
MM552F

MM552F

MM555H
2N5197
2N3921
2N5198
2N3922

MMF5

2NS199

MMF6
MMT3823

2N3955A
2N3823

3Nl72

MN6091
MN6092A

ICM7038E

MEM517A
MEMSl7B

3NI72

MN6093

3Nl72

MN6252

rCM70SOG

MEM517C
MEM550
MEM550C

3NI72

MP301
MP302

1T124

3N189

3NI89

MP303

1T124

ICM7051A
rT124

3N189
3N190

MP310
MP311

2N4045
2N4045

3NI89
3Nl72

1T124

1T131

MEM556C

3NI72

MP312
MP313
MP318

1T129

MEM560

3NI61

MP350

1T132

1T129

MEM560C

MP351

1T130

MEM561

3Nl61
3N163

MP352

MEM561C

3NI63
2N4351

MP358
MP360

1T130
1T130A
ITI32

2N43S1

2N4351

1T129

ICl7650

MD7001

ICL7652

3NI61

M07002
M07002A

1T122

3Nt61

MD7002B

1T122

MI06

3NI66

1T139
1T122

MEM550F

rCM70388

MEM556

MI04

MEM562
MEM562C
MEM563

MP361

1T130A

2N4351

MP362
MP3954

1T130A
2N3954

M116

MP3954A

2N3954A

MIl6

MP3955

2N3955

MEM712A
MEM713
MEM806

MIl6
3N170

MP3956
MP3957

3NI63

MP3958

MEM806A
MEM807

3N163

MP5905
MP5906

2N3956
2N3957
2N3958
2N5905
2N5906

M07003

1T132

3N189

MD7003A

3NI91
3NI61
3NI61
M116

M07003B
M07004
M07007
M07007A

1T132
ITl32
1T129
1T129

MEM816
MEM817

1T129

MEM823

MFE823

M117
M119
MI63

2N4351

M07007B
M0708
M070BA

1T129

3NI63
3N164

MD7088

MEM954
MEM954A
MEM9548
MEM955

3NI88
3NI88
3NI88

M164

3Nl90

MP7520JN
MP7520KO
MP7520KN

MooOI

ICM7269

M08001

MEM955A

3NI90

MP7520LD

1T129

1T120A

MEM711
MEM712

MI07

1T129
1T129
1T120

2N4044

MEM563C

MI08
MI13
M114
M116

"CONSULT FACTORY

MM452F

MEM551
MEM551C

1T131
1T132

lTCI052
lTC7652
MI03

3N161

2N4416
MM450H
MM4S1H
MM452J

MEM807A
MEM814

XXVII

3NI72
3Nl72

MP5907

2N5907

3NI61
3NI72

MP5908

2N5908
2N5909

3Nl72

MP5909
MP5911
MP5912
MP7520JD

2N5911
2N5912
AD7520JD
AD7520JN
AD7520KD

A07!>20KN
AD7520LD

ALTERNATE
SOURCE PRODUCT
MP7520LN
MP7520SD
MP7520TD
MP7520UD

INTERSIL
EQUIVALENT

AD7520lN

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

INTERSIL
EQUIVALENT

SJM187BCC
SJM187BIC
SJM188BCC
SJM188BIC
SJM190BEC

JM38510/11105BCC
JM3851 0/111 0581C

SJM191BEC

JM38510/11108BEC

AD7520SD
AD7520TD
AD7520UO
AD7521JD

NF51Ql
NF5102
NF5103
NF511
NF5163

2N4867
2N4867
2N4867
2N4860
2N4341

PN3687
PN4091
PN4092
PN4093
PN4220

AD7S2IJN
AD7521KD
AD7521KN
A07521LD
AD7521LN

NF520
NFS21
NF522
NF523
NF530

2N3684
2N3685

PN4221

2N4341

PN4222
PN4223
PN4224
PN4342

MP7521TD
MP7521UD
MP7523JN
MP7S23KN

AD7521SD
AD7521TD
AD7521UD
AD7523JN
AD7S23KN

NF5301
NF5301-1
NF5301-2
NF5301-3
NF531

2N4118A
2N4117A
2N4118A
2N4118A
2N4339

PN4360
PN4391
PN4392
PN4416
PN4856

5l362C
5M50l1
5M5510
5M55308

ITl29
ITl29
ICM7050G
ICM1l158
tCM7070P

MP7523lN
MP7621AO
MP7621BO
MP762IJN
MP7621KN

AD7523LN
AD7541AD
AD754180
A07541JN
AD7541KN

NF532
NF533
NF5457
NF5458
NF5459

2N4341
2N4339
2N5457
2N5458
2N5459

PN4857
PN4858
PN4859
PN4860
PN4861

2N4857
2N4858
2N4859
2N4860
2N4861

5U2OO0
5U2020
5U2021
5U2022
5U2023

2N4340
2N3954
2N3954
2N3954
2N3954

MP7621SD
MP7621TD
MP804
MP830
MP831

AD754150
A07541TD
2N5520
2N5520
2N5521

NF5484
NF5485
NF5486
NF5555
NF5638

2NS484
2N5485
2N5486
2N5484
2N5638

PN5033
PTC151
PTC152
RC555
RC556

2N5460
2N5484
2N5485
ICM7555
ICM7556

SU2024
5U2025
5U2026
5U2027
5U2028

2N3954
2N3954
2N3954
2N3954
2N3954

MP832
MP833
MP835
MP836
MP837

2N5522
2N5523
2N3954
2N3955
2N3955

NF5639
NF5640
NF5653
NF5654
NF580

2N5639
2N5640
2N4860
2N4861
2N5432

SI424
SA2253
SA2254
SA2255
5A2644

ICM1424C
ITI22
ITI22
IT122
ITI20

5U2029
5U2029
SU2030
5U2030
SU2031

2N5197
2N3954
2N3955
2N3954
2N5198

MP838
MP839
MP840
MP841
MP842

2N3956
2N3957
2N5520
2NS521
2N5523

NF581
NF582
NF583
NF584
NF585

2N5432
2N5433
2N5434
2N5433
2N4859

5A2648
5A2710
5A2711
SA2712
SA2713

ITI20
lTI20
ITI20
ITI21
ITI21

5U2031
5U2032
SU2033
SU2034
SU2034

2N3954
2N3954
2N3954
2N3955
2N3954

MPFlD2
MPF103
MPFl04
MPF105
MPFl06

2N5486
2N5457
2N5458
2N5459
2N5485

NF6451
NF6452
NF6453
NF6454
NKT80111

U310
U310
U310
U310
2N4220

SA2714
SA2715
5A2716
SA2717
SA2718

ITI22
ITI20
ITI20
ITI21
ITI22

SU2035
SU2035
SU2074
SU2075
SU2076

2N3955
2N3954
2N3954
2N3954
2N3954

MPFI07
MPFI08
MPFI09
MPFllI
MPFl12

2N5486
2N5486
2N5484
2N5458
2N5458

NKT80112
NKT80113
NKT80211
NKT80212
NKT80213

2N4220
2N3821
2N4339
2N4339
2N4339

SA2719
SA2720
SA2721
SA2722
SA2723

ITI20
ITI21
1T122
ITI20
1Tl21

SU2077
SU2077
SU2078
SU2079
SU2080

2N3955
2N3954
2N3955
2N39S5
U404

MPF161
MPF208
MPF209
MPF256
MPF4391

2N5398
2N3821
2N3821
ITE4416
ITE4391

NKT80214
NKT8021S
NKT80216
NKT80421
NKT80422

2N4339
2N4339
2N4339
2N4220
2N4220

SA2724
SA2726
SA2727
SA2738
5A2739

ITI22
ITI22
tTI22
ITI20A
ITI20

SU2081
5U2098
5U2098A
SU20988
5U2099

U404
2N5197
2N5197
2N5196
2N5197

MPF4392
MPF4393
MPF820
MPF970
MPF971

ITE4392
ITE4393
J310
J175
J175

NKT80423
NKT80424
NPCI08
NPC21lN
NPC212N

2N4220
2N4220
2N5484
2N4338
2N4338

5CL54301
5CL5478
SDFlOOl
SDFlO02
5DFlO03

ICM1424C
ICM7269
2N5432
2N5433
2N5434

SU2099A
5U2365
SU2365A
SU2366
5U2366A

2N5197
2N3954
2N3954
2N3955
2N3955

MP55010
M5M5001
M5M5011
M5M5977
MTFlOI

ICL8069
ICM7269
ICM1424C
ICM1424C
2N5484

NPC213N
NPC214N
NPC2l5N
NPC216N
NPD8301

2N4338
2N4339
2N4339
2N4339
2N3954

5DF5oo
SOF501
50F502
50F503
SDF504

2N5520
2N5520
2N5520
2N5520
2N5520

5U2367
SU2367A
5U2368
SU2368A
SU2369

2N3955
2N3955
2N3956
2N3956
2N3957

MTFl02
MTFI03
MTFt04
ND5700
ND5701

2N5484
2N54S7
2N5459
ITl20A
ITl20A

NPD8302
NP08303
OT3
P1004
PI005

2N3955
2N3956
2N4338
2N5116
2N5115

SDF505
SOF506
SDF5D7
50F508
5DF509

2N5520
2N5520
2N5520
2N5520
2N5520

SU2369A
5U2410
5U2411
5U2412
5U2652

2N3957
2N5907
2N59D8
2N5909
U401

ND5702
NDF9401
NOF9402
NDF9403
NOF9404

ITl20
IT500
IT501
IT502
IT503

PI027
PlO28
PI029
PI069E
P1086E

2N5267
2N5270
2N5270
2N2609
2N5115

SDF510
50FS12
SOF513
50F514
SDF661

2N3954
2N3954
2N3954
2N3954
1Tl22

SU2652M
5U2653
5U2653M
5U2654
SU2654M

U401
U401
U40l
U401
U40l

NOF9405
NOF9406
NOF9407
NDF9408
NDF9409

ITS04
IT500
IT501
IT502
IT503

Pl087E
Pll17E
Pll18E
Pl119E
PF510

2N5516
2N5640
2N564l
2N5640
2N5115

SOF662
SDF663
SE555
5E556
SES3819

ITl22
ITI22
ICM7555
ICM7556
2N5484

SU2655
SU2655M
SU2656
5U2656M
SX3819

U402
U402
U404
U404
2N5484

NDF9410
NE555
NE556
NE590
NF3819

IT504
ICM7555
ICM7556
A0590
2N5484

PF5101
PF5102
PF5l03
PF511
PF5301

2N4867
2N4867
2N4867
2N5114
2N4118A

SFT601
SFT602
5FT603
5FT604
5G4250

2N4338
2N4338
2N4339
2N4339
LM42S0

SX3820
TC803lP
TC8032P
TC8051P
TC8052P

2N2608
ICM7038A
ICM7038F
lCM70388
ICM7038E

NF43D2
NF4303
NF4304
NF4445
NF4446

2N5457
2N5459
2N5458
2N5432
2N5433

PF5301-1
PF5301-2
PF5301-3
PLl091
PLl092

2N4117A
2N4118A
2N4118A
2N3823
2N3823

517135CPI
517652
517660
517661
SJM181BCC

ICL7l35CPI
tCL7652
ICL7660
ICL7662
JM3851O/II101BCC

TC8056PA
TC8057P
TDlOO
TOIOI
T0102

ICMll158
ICM70380
ITI29
ITl29
ITl29

NF4447
NF4448
NF500
NF501
NF506

2N5433
2N5433
2N4224
2N4224
2N4416

PLlO93
PLlO94
PN3684
PN3685
PN3686

2N3823
2N3823
2N3684
2N3685
2N3686

SJM181BIC
SJM1828CC
SJM18281C
SJM184BEC
5JM185BEC

JM38510/11101BIC
JM38Sl01l11028CC
JM38510/11102BIC
JM3851OIlI103BEC
JM38510/l1 104BEC

TD200
T0201
TD202
T02219
T0224

ITl29
ITl29
ITl29
ITl29
ITI22

MP752IJD
MP752IJN
MP7521KD
MP7521KN
MP7521LD
MP7521LN

MP1521SD

··CONSULT FACTORY

2N3686
2N3865

XXVIII

2N3687
ITE4091
ITE4092
ITE4093

ALTERNATE
SOURCE PRODUCT

J204
J202
J2D3

J204

Sl301AT
Sl301BT

J202

SL30lCT

2NS461

Sl301ET

2N5460
ITE4391
ITE4392
ITE4416
2N4856

Sl36DC

JM38510111106BCC
JM38510/11106BIC

JM38510/11107BEC

ITl29
ITl29
ITl29
ITl29

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

TD225

lTl22

TD226

lTI22
1T122
ITl22

TIS73
TI574

TI569
llS70

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PROOUCT

INTERSIL
EQUIVALENT

ALTERNATE

SOURCE PRODUCT

INTERSIL
EQUIVALENT

U1179
U1180
U1I81
U1182
U1277

2N3821
2N4221
2N4220
2N3821
2N3684

U300
U3000
U3OO1
U3OO2
U301

2N5114
2N4341
2N4339
2N4338
2N5115

2N4341
2N434O
2N4338
U304
U305

ITI22

TI575

2N3955A
2N3956
IT[4391
ITE4392
ITE4393

TD230
T0231
TD232
T0233
T0234

ITI21
ITI21
ITI22
ITI22

TIS88
TIS88A
TIXS33
TIXS35
TIXS36

2N4416
2N4416
2N4392
2N4857
2N4391

U1278

2N3685

U1279
U1280
U1281
U1282

2N3686
2N4341

U3010
U301l
U3012
U304
U305

TD235
T0236

ITI22

T0239

ITI22
ITI22
ITl22
ITI22

TIXS41
TIXS42
TIXS59
TIXS78
TIXS79

2N4859
2N5639
2N5459
2N4341
2N4341

U1283
U1284
U1285
U1286
U1287

2N4340
2N4341
2N4220
2N4341
2N4092

U306
U308
U309
U310
U311

U306
U308
U309
U310
U310

TD240
TD241

1T12l
1T121

Tl182CL
TLl82CN

U312

2N5397

U314

2N5555

TL1821L
TL1821N
TL182ML

U1321
U1322
U1323

2N3822

ITl20A
ITl20A
ITl29

OGM182BA
DGM182CJ
DGM182BA

2N4860

TD242
TD243
TD244

2N3822

DGM182CJ

U1324

2N3687

U315
U316

DGM182AA

U1325

2N3686

U317

2N5397
U309
U310

TD245

ITl29
ITl29
ITl29
ITl29
1T120A

U133

2N5433

TLl851J

IH5045CJE
IH5045CPE
IH5045CJE
IH5045CPE
IH504SMJE

U320

TD246
TD247
TD248
TD2S0

TD2905

1Tl39

UI47

TD400

1T139
1T139
ITl39
In39

TLl88ML

IH5042CTW
IH5042CPE
IH5042CTW
IH5042CPE
IHS042MTW

TL191CJ
TL19ICN
TL1911J
TL1911N
TLl9IMJ

IH5043CJE
IHS043CPE
IH5043CJE
IH5043CPE
IH5043MJE

TLC251
TLC252
TLC254
TLC271

ICL7612
ICL7611
ICL7621
ICL7642
ICL7612

TD227
T0228
TD229

TD237
T0238

TD401
T0402

TD500

ITI22

TL185CJ
TL185CN
TL1851N
TL185MJ
TL188CL
TL188CN
TL1881L
TL1881N

2N3684

2N3822

U1420

2N2608
2N3821

U1421

2N3822

U1422
U146

2N3822

2N2608

Ul49

2N2608
2N2608
2N2609

U168

2N2609

Ul714

2N4340

U1715

2N4340

U182

2N4857

U183
U1837E
U184

2N3824

U148

U321
U322
U328
U329
U330
U331

2N5434

..
......

2N5433

U350
U401
U402

U401
U402

U403
U404
U405
U406
U410

U403
U404
U40S
U406
2N395S

TDSOl
TD502
TDS09
TDSlO
TOSll

In39
In39
In32

TOS12

TOSI8

ITl32
ITl32
1T132
ITl32
1T132

T0519
T0520
T0521
T0522
T0523

ITl32
ITl39
ITl39
In39
ITl39

TLC271
TlC272
TlC274
TLC274
TLC555

ICL7611
ICL7621
ICL7642
ICL7641
ICM7S55

T0524
T0525
TD526
TD527
TD528

ITl39
ITl32
ITl32
IT131
ITl31

TLC556
TN41I7
TN4117A
TN4118
TN4118A

ICM7556
2N4117
2N4117A
2N4118
2N4118A

T05432
T05433
T05434

2N5432
2N5433
2N5434
1T129
2N5902

TN4119
TN4119A

U234

UCIIO
UCIl5

TN4338

U235

U235

UC120

2N3686

TN4339
TN4340

2N4119
2N4119A
2N4338
2N4339
2N4340

U240
U241

2N5432
2N5433

UC130

2N3687
2N4416

TN4341
TN5277
TN5278

2N4341
2N4341
2N4341

U242

2N5432

UCI700

TD5903A

2N5902
2N5903
2N5903

U243

UC1764

TD5904
TD5904A

2N5904
2N5904

TP5114

2N5114
2N5115

U248
U248A

2N5433
2N5433
2N5902
2N5906

UC201

2N3824

TD5905

2N5905

TD5905A

TPS116
TSC426
TSC7106CJl

U249

2N5903

U249A

2N5907

UC21
UC210

2N3687

TSC7106CPL

TD5907

U250
U250A
U251

2N5904

TD5906A

2N5905
2N5906
2N5906

TD513
TOS14

TD517

TD550
TD5902
TD5902A
TD5903

ITl32
1T132

TLC251

TP5115

U1897E
U1898E
Ul97

U1899
2N4338

U41l
U412
U421
U422

U198

2N434O

U423

U199

U202

2N4859

U424
U425
U426
U430
U431

2NS908
2NS908
2N5909

U201

2N4341
2N4416
2N4861
2N4860

U2047E
U221
U222

2N4416
2N4391
2N4391

U440
U441

U231

U231

U232

U232

IT5911
IT5912
ICM7555
ICM7556
2N3684

U1899E

U1994E

U200

U233
U234

U244

2N5907

TSC7106RCPl

2NS116
ICl7667
ICl7106CJL
ICl7106CPl
ICL7106RCPL

TD5907A

2N5907

TD5908

2N5908

TD5908A

TD5909

2N5908
2N5909
2N5909

ICL7107CJL
ICl7107CPL
ICl7107RCPl
ICL7109CPL
ICL7109IJL

U251A
U252
U253

TD5909A

TSC7107CJl
TSC7107CPl
TSC7107RCPL
TSC7109CPl
TSC7109IJl

TD5911

1T5911
IT5911
IT5912
IT5912
ITI22

TSC7109MJl
TSC7116CJl
TSC7116CPL
TSC7117CJL
TSC7117CPL

ICL7109MJL
ICL7116CJl
ICl7116CPl
ICl7117CJL
ICl7117CPl

U256

ICl7126CJl
ICL7126RCPL
ICL7135CJI
ICL7135CPf
ICL7650

TD5906

T05911A
T05912
TD5912A
T0700
T0701

1T122

TSC7126CJL

TD709

1Tl22

T0710

ITl22
ITI22
ITl22

TSC7126RCPL
TSC7135CJI
TSC7135CPI
TSC7650

TD711
TD713
TIS14
TIS25
TIS26

2N4340
2N3954
2N3954

TIS27

2N3955

TIS34

2NS486

TIS41
TIS42

2N4859

TIS58
TIS59
TIS68

2N4393
2N5484
2N5486
2N39S5A

"CONSULT FACTORY

TSC7660
TSC9491

TI-590
U110
U111
U112
Ul13
Ul14

Ul177
UIl78

ICL7660
ICL8069
AD590

2N2608

2N5486
2N5397

U254

U255
U257
U257/TO·71

U266
U273
U273A

U1897

U1898

U233

2N5908

2N5905
2N5909

U284

U285
U290
U291
U295
U296

XXIX

2N3824

UC2130
UC2132
UC2134
UC2136

2N4416
2NS452
2N5453
2NS454
2NS4S4
2N5454

2N3958

2N4861
U257

UC2149
UC220

2N3958

U257/TO-71

UC240

2N4869

2N4856
2N4118A

UC241

2N4869

UC250

2N4091

UC251

2N4392
3NI66

2N4119A

2N2608

3N163
3N163
2N3686

UC2138

U275A

2N2608
2N2608
2N2608
2N4220
2N3821

UC20

UC200

UC2139
UC2147
UC2148

2N4118A
2N4119A
2N4119A

U281

2N3685
2N4340

2N4859
2N4860

2N4119A

U282
U283

J309(X2)
J31O(X2)

IT5912

U274A

U280

UC155

2N5908
2NS908
2N5909

IT5911

U275

U274

UA555
UA556
UClOO

2N3956

2N3958

2NS4S2
2N54S3
2N5453

2N5453
2N5454
2N5454

2N5432
2N5434

2N5432
2N5434

UC2766

UC300
UC310
UC320
UC330
UC340

UC40
UC400
UC401

UC41
UC410
UC420
UC450
UC451

2N3958

2N3958
2N3822

2N2608
2N2607

2N2607
2N2607
2N2607

2N2608
2N5270
2N5116
2N2608
2N5268
2N5267

2N5114
2N5116

ALTERNATE
SOURCE PRODUCT'

INTERalL
EQUIVALENT

UC5BB
UC703
UC704
UC705
UC707

2N4416
2N4220
2N4220
2N4224
2N4860

UC714
UC714E
UC734
UC734E
UC751

2N3B22
2N4341
2N4416
2N4416
2N4340

UC752
UC753
UC754
UC755
UC756

2N4340
2N4341
2N4340
2N4341
2N4340

UC805
UC807
UCB14
UCB51
UCB53

2N5270
2N5115
2N5270
2N260B
2N260B

UCB54
UC855
UCN·4111M
UCN-4112M
UCN-4113M

2N260B
2N2609
ICM703BC
ICM7051A
ICM703BB

UPD1952P
UPD1962C
UPD1963C
UPDB15C
UPD816C

ICM7220MFA
ICM7050G
ICM7050
ICM7038E
ICM703BB

UPD820C
UPD833G

ICM1l15B
ICM7223
2N5397
2N5397
1Tl26

unoo
unOl

UXC2910
veRION
VCRllN
VCR12N

VCR13N
VCR20N

VCR2N
VCR3P
VCR4N

VCR5P
VCR6P

VCR7N
VF28

VF811
VF815
VFW40

VFW40A
VR-8069
W245A

W245B
W245C

A!.TEIINATE
SOURCE PRODUCT

'INTERaIL
IQUIVAUNT

AL,",RNATE
SQURCE PROOUCT

2N4869
VNRllN
2N3958
2N3958
2N4341
VCR2N
VCR2P

VCR4N
VCR5P
VCR6P
VCR7N
2N4392
2N4858
2N4858

ITl22
ITl20
ICL8069
ITE4416
ITE4416
ITE4416

W300
W300A
W300B
W300C
W300D

2N5398
2N5397
2NS397
2N5397

WG-8038
WK5457
WK5458
WK54S9
XR555

ICL8038
2N5457
2N5458
2N5459
ICM7555

XR556
XR8038
ZOT40
ZDT41
ZDT42

ICM7556
ICL8038
1Tl29
ITl29

ZOT44
ZOT45

1Tl29
lTl29

2N5398

ITl29

"CONSULT FACTORY

xxx

' IN,",RIIL
IQUIVALENT

ALTeRNATe

SOURCE PRODUCT

INT.RaIL
EQUIVALENT

Section 1 -

Selector Guides

INTERSIL
YOUR COMPLETE SOURCE
FOR INTEGRATED SIGNAL PROCESSING
COMPONENTS
Intersil, founded in 1967, is a wholly owned subsidiary of General Electric
Company U.S.A., and a component of the GE/RCA Solid State Division,
headquartered in Somerville, New Jersey.
Intersil's Semiconductor Business charter has been the development of
an extensive analog/digital component complement focusing on the commercial, industrial, instrumentation and military markets. Based on the most
advanced innovations in CMOS technology, it has established itself as a
frontrunner in products serving the explosive data conversion and digital
signal processing marketplace.
Intersil's expanding product line is headed by a respected portfolio of
data converters, analog switches and multiplexers, display drivers, digital
controls and sophisticated linear circuitry. Technology innovations include
an operational 130-volt CMOS process with 3/-L and 4/-L feature sizes, and
a 5-inch wafer fabrication system. Intersil's new digital signal processing
products use advanced very large scale integration (AVLSI) processes with
a 1.5/-L feature size, and a 1.25/-L process is in the final stages of development. Intersil's next-generation MaS/bipolar (BiMOS) process that combines the best attributes of MaS and bipolar processing on a single chip.
Product quality and reliability are fundamental considerations in Intersil's
manufacturing facilities. Clean-room environments, Class 100 in critical
wafer processing areas and Class 5000 in manufacturing areas, easily
meet recommended standards. A high degree of factory automation has
phased out slower and less reliable manual operations.
And, overall, a high dedication to customer service reflects the Intersil
commitment to be one of the most respected semiconductor suppliers in
the industry.

DATA ACQUISITION
The proliferation of microprocessors and the general swing
to digital signal processing has caused an explosion in the
need for data acquisition products. In turn, the associated
data translation requirements from the analog world to digital
format, and vice versa, have spurred considerable effort
toward making AlD-D/A converters progressively smaller,
cheaper, and more reliable. Toward that end, Intersil has
developed a family of integrated circuits designed to meet
the varying requirements of the system designer.
All of Intersil's converters are fabricated using CMOS technology, which equates, inherently, to extremely low power
consumption. All maximize on-chip componentry for the
intended application in order to reduce the external component requirements to a minimum.
To facilitate acquaintance with Intersil products, a number
of AID converters are available in the form of low-cost Eval-

uation Kits. The Kits combine the specified converter with a
number of additional components required to assemble a
functional subsystem. They include components PC board
and appropriate assembly instructions.

Content:
AID Converter Systems
Digital Multimeter
Instrumentation
Bargraph
AID Converters
Display Type
ILP Type
Evaluation Kits
D/A Converters

Analog To Digital Converters
AID Converters
with Display Drivers

41/0 Digit LCD
ICL7129
7-Segment Displays
For High Quality Battery Operated Instruments

Integrating ND Converters are characterized by high inherent
accuracy, excellent noise rejection, non-critical associated components and low cost. They are relatively slow with conversion rates
up to 30 conversions per second. All Intersil integrating converters
provide fully precise Auto-Zero, Auto-Polarity (including ± null indicalion), single reference operation, very high input impedance. true
input integration over a constant period (for maximum EMI rejection).
fully ratiometric operation. overrange indication and a medium-quality
built-in reference.

Very high performance ND Converter for direct drive of multiplexed LCOs. Ideal for high-resolution, hand-held digital multi meters
and other battery powered (9V) instruments. Accuracy is better than
0.005% of full scale, with resolution down to 10/LV per count. Overrange and underrange outputs permit design of autoranging instruments with 10:1 range changing input. Instant continuity check gives
both visual indication and a logic-level output for enabling an external
audible transducer. Provisions for detection and indication of Low
Battery condition.

For 31/0 Digit LCD/LED
7-Segment Displays
30/4 Digit LCD
7-Segment Displays
ICL7139
For Low-Cost Autoranging Digital Multimeters ICL7149

These 3%-digit ND Converters contain all the necessary active
devices on a single CMOS integrated circuit. Included are AID Converters, 7-segment decoders, display drivers, a reference and a
clock. All feature auto-zero to less than 1OIL V, zero-input drift of less
than '/LVrC, input bias current of 10pA max., and rollover and linearity errors of less than one count. True differential inputs and reference provide wide applications versatility over a temperature range
from 0 to + 70°C.

These monolithic autoranging multi meter circuits always display
the results of a conversion on the correct range. Measure AC and
DC voltage, DC current and resistance in the following ranges:
DC Voltage - 400mV, 4V, 40V, 400V
AC Voltage - 400V (ICL7139)
(Optional ac circuit with 2 ranges (ICL7149))
DC Current - 4mA, 40mA, 400mA, 4A
Resistance - 4K, 40K, 400K, 4M
On-chip duplex display drivE!, includes three decimal points and 11
annunciators. Less than 20mW power dissipation provides 1000
hours typical battery life. Continuity output drives piezoelectric beeper. Guaranteed zero reading for 0 Volts input on all ranges.

101-Segment LCD Bargraph
A-D Converter

ICL7106/7116,ICL713617126
ICL7137-7107,ICL7117

ICL7106 ICL7116 For Liquid
Crystal
Displays

ICL7136 -

ICL7126-

Earlier version of iCL7136. Recommended for exact
replacement requirement only.

ICL7137 -

Low-power, direct drive ADC for commonanode, 7-segment LED displays. Requires
positive and negative 5V supply voltages,
with supply current of less than 200I'A. 0.1
to 4 conversions per second.

ICL7107-

ICL7107 - Earlier version ot ICL.7137. Recommended for
exact replacement requirements only.

ICL7117 -

Similar to ICL7137. but requires I.SmA
(max.) 01 supply current and provides up to
15 conversions per second. Hold Reading
allows indefinite retention of display reading,

ICL7182
For LED
Displays

The ICL7182 is a complete analog-to-digital converter that directly
drives a multiplexed liquid crystal display. Included are a chargebalance AID converter, a 2.56V bandgap reference, display decode
and driver, and a 50KHz oscillator. A complete analog bargraph
generator requires only the addition of an external display, two passive components and a 350/LA, 5V power source.

1-2

Direct drive; 0.1 to 15 conversions per
second; supply current = 1.BmA max.
Similar to above, but features a Hold
Reading input which allows indefinite
retention of a display reading
Low-power version of ICL71 06, but with
maximum supply current of only 100JLA
gives SOOO hours typical 9V battery life. 0.1
to 4 conversions per second.

IIU~UlL

DATA ACQUISITION
p,P Compatible AID Converters
Integrating

ICL71 04-14
ICL71 04-16
ICL8052

Intersi! integrating /LP-Compatible AID 'Converters contain
both monolithic versions and 2-chip sets, with up to 16-bit
resolution. All utilize CMOS processing for lowest power consumption, and all have a guaranteed accuracy of 1 count.

ICL8068-

4'1. Digit AID Converter
with Multiplexed BCD Output

ICL7135

Successive Approximation

This precision AID Converter is suitable for display applications as well as microprocessor and UART interface. Count
accuracy of ± 1 in 20,000 makes it ideal for the visual display
DVM/DPM market, while added functions such as Strobe,
Run/Hold, Busy, Overrange and Underrange allow operation
in more sophisticated systems. Chip contains all necessary
active devices except display drivers, reference and clock.
All outputs are TTL compatible.
12·Bit /LP·Compatible
AID Converter

Successive Approximation Converters are generally associated with high speed, ranging up to 100,000 conversions
per second. Allintersil Successive Approximation Converters
are /LP compatible.

8·Bit AID Converters
for 8080A MPU Interface

ADC0802
ADC0803
ADC0804

This Successive Approximation AID Converter was
designed to operate with the 8080A or Z-80 microprocessor
control bus via three-state outputs with no additional interfacing requirements, but permits easy interface to most other
microprocessors. Differential analog input range is 0 to 5V
with a single + 5V supply. With a conversion time of less than
100 /LS, it provides up to 8888 conversions per second with
a clock frequency of 640KHz.
ADC0802 Total unadjusted error = ± 1/2LSB
ADC0803 Total full-scale adjust error = ± 1/2LSB
ADC0804 Total unadjusted error = ± 1LSB

ICL7109

This monolithic 12-bit binary AID converter may be directly
accessed under control of two byte-Enable inputs, and a Chip
Select input, for a simple parallel-bus interface. A UART
handshake mode operates in conjunction with industry-standard UARTs to provide serial data transmission. Operates at
up to 30 conversions per second. Available in three temperature ranges: - 55°C to + 125°C, - 25°C to + 85°C, and O°C
to + 70°C.
14/16-Bit ,.P·Compatible
Two·Chip AID Converter Sets

14-BitADC
16-BitADC
Low input leakage current (30pA max.)
analog processing circuit.
Typical noise = 30/LV.
Low noise (2/LV typical) analog
processing circuit. Input leakage current
= 165pA.

ICL8052/ICL7104
ICL8068/ICL7104

14·Bit High·Speed
AID Converter

Available with 14-bit and 16-bit resolution, this twO-Chip set
performs the analog signal processing on one chip (ICL8052
or ICL8068) and the switching and digital functions on the
other (ICL71 04). A combination of chips may be ordered for
either 14-bit or 16-bit operation and for low-noise or lowleakage alternatives. All combinations, however, offer threestate, latched, binary outputs plus Polarity and Overrange.
All combinations operate over a temperature range of O°C to
+ 70°C.

ICL7115

With a conversion speed of 40/Ls (max), this 14-bit ADC
has a byte organized digital output for bus interface to 8 and
16-bit microprocessor systems. CMOS circuitry, thin-film
resistors and an on-Chip PROM calibration table combine to
achieve 13-bit linearity (without laser trimming) and a very
low (60mW) power diSSipation. Available in three temperature
ranges: O°C to + 70°C, - 25°C to + 85°C, and - 55°C to
+ 125°C.

1-3

DATA ACQUISITION
Digital to Analog Converters
Intersil supplies digital-to-analog converters (D/A converters) with a-bit, 10-bit, 12-bit, 14-bit and 16-bit resolution. All
are four-quadrant multiplying D/A converters using thin-film

Digital
Input

Type

Format

Settling Time
(To 0.05% FS)

resistors and CMOS circuitry for high accuracy and low power
dissipation. All are microcomputer compatible, with input protection against damage from electrostatic discharge.

Output
Current
(Max)

Gain

Power
Supply
I(Max)

Linearity% FS

Error

Linearity
Tempo

(Sulfix)

(%FS)

PPM/'C

Non

Gain

~

0.2% (J)
O.l%(K)
0.05% (L)

10-BIT
AD7520'
AD7530

Binaryl
Offsel
Binary

500 ns
(Typ)

±VREFA
10K!)

0.2% (J)
O.l%(K)
0.05% (L)

0.3%
(Max)

10
2

+15V
2mA

AD7533

Binaryl
Offset
Binary

600 ns
(Typ)

±VREFA
10Kll

0.2% (J)
O.l%(K)
0.05% (L)

1.4%
(Max)

10
2

+15V
2mA

AD7521,
AD7531

Binary/
Offset
Binary

500 ns
(Typ)

±VREFA
10Kll

0.2% (J)
O.l%(K)
0.05% (L)

0.3%
(Typ)

10
2

+15V
2mA

AD7541

Binaryl
Offset
Binary

1 I'S
(Max)

±VREFA
10Kll

0.02% (J)
0.01% (K)
0.01% (L)

0.3'%
(Max)

-

--

12-BIT

2

+15V
2mA

0.1% (J)
0.006% (K)
0.003% (L)

•AD7530 and AD7531 are identical to AD7520 and AD7521, respectively, except for output leakage current and feed-through specifications.

ICL7121
16-8it "P-Compatible
01 A Converter
This high-performance 16-bit D/A converter achieves
0.003% linearity without laser trimming by combining the
converter with a unique on-Chip PROM-controlled correction circuit. This insures long-term stability and accuracy
even over the full military temperature range. Silicon-gate
CMOS circuitry keeps the power dissipation to a very low
25mW.
Designed and programmed for bipolar operation, it can be
connected to provide a true 2's complement input transfer
function without any external resistors. Microprocessor bus
interfacing is eased by standard memory WRite cycle timing
and control signal use. The device is available in a 2a-pin
CERDIP package in both O°C to + 70°C, and - 55°C to
+ 125°C temperature ranges.

ICL7121 Example of Bipolar, Four Quadrant Operation

1-4

DATA ACQUISITION
AID Converter
Evaluation Kits
The following Evaluation Kits are available to permit rapid
assembly, testing and evaluation of specific AID converters.
Each Kit comes complete with a prewired printed circuit board
and all necessary components (except batteries) for a suitable demonstration circuit. Assembly and operating instruction are supplied.

ICL7136EVIKit

ICL7129EV/Kit

ICL7139EV/Kit

This Kit permits evaluation of the IntersillCL7129 4'/2 digit,
LCD, 7-segment display in a functional DC digital voltmeter
circuit. It includes the AID converter IC, a liquid crystal display,
a 120KHz crystal, a voltage reference IC and all necessary
passive components and hardware items.
ICL7139EV/Kit
ICL7106/07EV/Kit
ICL7136EV/Kit

This Kit uses the Intersil ICL7139 to build a complete 3%
digit autoranging multimeter, capable of directly measuring
voltage, current, and resistance. Included in the Kit are the
ICL7139 IC, circuit board, liquid crystal display, and all necessary passive components and hardware.

Intersil's ICL7136 is a low-power version of the 3V2 digit
LCD AID converters. This Kit contains all the components
necessary to build a battery-operated 3'12 digit panel meter.
It includes the AID converter IC, a circuit board, liquid crystal
display, passive components, and miscellaneous hardware.

ICL7182EV/Kit
With this Kit, the user can easily evaluate a 101 segment
LCD bargraph AID convetter using Intersil's ICL7182. Everything necessary to build the completed circuit is included in
the Kit: The ICL7182 IC, circuit board, 101 segment LCD,
passive components, and miscellaneous hardware.

ICL7106EV/Kit,ICL7107EV/Kit
To ease evaluation of these unique circuits, Intersil offers
kits which contain all the necessary components to build a
3V2 digit panel meter. Two kits are offered, the ICL7106EVI
Kit and the ICL7107EV/Kit. Both contain the appropriate IC,
a circuit board, a display (LCD for the ICL7106EV/Kit, LEDs
for the ICL7107EV/Kit), passive components, and miscellaneous hardware.

GRAPHICS
IM2110
256 X 12 Color Lookup
Table and DAC
The IM211 0 is designed specifically for color graphics, and
integrates a 256 x 12 color lookup table, three 4-bit DACs,
and a microprocessor interface.
The color lookup table is stored in a RAM and may be
written asynchronously by an 8- or 16-bit microprocessor.
Three overlay registers are provided for overlaying cursors,
grids, text, etc. The chip is capable of simultaneously displaying 256 out of 4096 colors at a 25 MHz rate, for a 640 x
480 non-interlaced display.
The IM2110 generates RS-343-A compatible red, green
and blue analog signals, and is capable of driving doublyterminated 75 n coaxial cables directly.
The circuit is available in a 40-pin plastic package and
operates over a temperature range of O°C to + 70°C.

elK

1-5

VDO

VAA

GND

POWER SUPPLY SUPERVISORY CIRCUITS

ICL7660S/ICL7662S
Voltage Converters
These voltage converters transform a positive (+) input
voltage from a power supply to a corresponding negative ( - )
output, resulting in complementary output voltages of - 1.5V
to - 12.0V for the ICL7660, and - 4.5V to - 20V for the
ICL7662. Only two non-critical external capacitors are
needed to perform the conversions. The converters can also
be connected as voltage doublers and will generate output
voltages of + 18.6V and 22.6V, respectively.
Available in two temperature ranges, O'C to 70'C and
- 55'C to + 125'C, and three packages, TO-99, 8-pin
MiniDIP (ICL7660S only) and SOIC.

Simple Negative Converter Configuration

ICL7663S
Programmable Micropower Voltage Regulators
The ICL7663 (positive) series regulators are low-power,
high-efficiency devices which accept inputs from 1.6V to 16V
and provide adjustable outputs over the same range at currents up to 40mA. Operating current is typically less than
4f,LA, regardless of load.
Output current sensing and remote shutdown are available,
thereby providing protection for the regulators and the circuits
they power.
The ICL7663 is available in 8-pin plastiC, TO-99 metal can,
CERDIp, and SOIC packages, in two temperature ranges O'C to + 70'C and - 25'C to + 85'C.

Basic Applications of ICL7663 as
Positive Regulator with Current Limit

ICL7667
Dual Power MOSFET Driver
The ICL7667 is a dual monolithic high-speed driver
designed to convert TTL level signals into high current outputs at voltages up to 15V. Its high speed and peak current
output enable it to drive large capacitive loads with high slew
rates and low propagation delays. With an output voltage
swing only millivolts less than the supply voltage and a maximum supply voltage of 15V, the ICL7667 is well suited for
driving power MOSFETs in high frequency switched-mode
power converters.
Available in commercial and military temperature ranges,
and in 8-pin plastiC DIP, SOIC, CERDIP and TO-99 metal
packages.

Direct Drive of MOSFET Gates

ICL7673
Automatic Battery Back-Up Switch

+ 5 VOLT ----'-I
PRIMARY
SUPPLY

The ICL7673 automatically switches from the main power
supply to a battery back-up supply in the event of power loss,
and back again when power is restored. Ideal for on-board
battery back-up for real-time clocks, timers, volatile RAMs,
or portable instruments. Available in 8-pin MiniDIP and TO-99
packages.

GND--+-----+-------ICL7673 Battery Backup Circuit

1-6

POWER SUPPLY SUPERVISORY CIRCUITS
ICL7665
Micropower Under/Over Voltage Detector
The ICL7665 contains two individually programmable voltage detectors on a single chip. Requiring only 3pA, typical,
for operation, the device is intended for battery-operated systems and instruments which require high or low voltage warnings, settable trip pOints, or fault monitoring and corrections.
Available in 8-lead CERDIP, MiniDIp, TO-99 metal can and
SOIC packages with a temperature range from O'C to 70'C.

Ifl1
Lhd_OETl
ICL7665 Functional Diagram
and Transfer Characteristics of Simple Threshold
Detector

ICL8211/1CL8212
Programmable Voltage Detector
These circuits consist of an accurate voltage reference, a
comparator and a pair of output buffer/drivers.
The ICL8211 provides a 7mA current limited output sink
when the voltage applied to the 'THRESHOLD' terminals is
less than 1.15 volts (the internal reference). The ICL8212
requires a voltage in excess of 1.15 volts to switch its output
on (no current limit). Both devices have a low current output
(HYSTERESIS) which is switched on for input voltages in
excess of 1.15V. The HYSTERESIS output may be used to
provide positive and noise free output switching using a simple feedback network.
Available in 8-lead MiniDip, TO-99 metal can and SOIC
packages, in commercial and rnilitary temperature ranges.

INPUT
~O~T,l.GE

IRECOMMENOEDAANGE!TO
5 VOLTS)

Voltage Level Detection with ICL821118212

ICL8069
Low Voltage Reference

ICL7677
Power Fail Detector

ICL8069 is a 1.2V temperature compensated voltage reference. It uses the band-gap principal to achieve excellent
stability and low noise at reverse currents down to 50pA
Applications include analog-to-digital converters, threshold
detectors, and voltage regulators. Its low power consumption
makes it especially suitable for battery operated equipment.
Available in TO-92 plastic and TO-52 metal packages with
O'C to 70'C and - 55'C to + 125'C temperature ranges
(metal only) and with temperature coefficients of 0.005 and

0.01/'C.

ICL7677 is a Power Fail Detector which can be incorporated either into the primary or the secondary side of a power
supply to give the fastest possible power-fail indication. On
the primary side, it can simultaneously monitor AC line voltage, the reservoir capacitor voltage, primary side current and
ambient temperature. On the secondary side, it can simultaneously monitor up to two DC voltages, one load current
and the ambient temperature. The circuit has an on-chip
bandgap-voltage reference to conveniently program the
detection thresholds.

ICL7675/1CL7676
Switched-Mode Power Supply Controller Set

ICL7680
5V to ± 15V Voltage Converter

The ICL7675/7676 two-chip set provides the necessary
control circuitry for regulation of an isolated flyback type
switching power supply. Specifically designed to operate in
this type of configuration, the Intersil controller chip-set is
trimmed to provide a regulated 5V output. The isolated flyback
converter is the most widely used configuration for switchedmode power supplies in 50W to 150W range because of its
simplicity. The chip-set features soft-start and power switch
over-current protection.

The ICL7680 is a simple boost-type switched-mode
converter/inverter chip using minimal external components
to convert + 5V to ± 15V regulated outputs. An internal
oscillator is user programmable to optimize efficiency for
various load conditions. The device features current limiting
protection together with external shut-down.

1-7

SPECIAL ANALOG FUNCTIONS
ICM7206
Touch·Tone Encoder

LP,

The ICM7206 is a 2-of-8 sinewave DTMF generator for use in
telephone dialing systems. Requires a 3.58 MHz crystal and will
operate with both 3x4 and 4x4 keypads. This low-cost circuit has a
high current bipolar output driver providing low harmonic distortion.
Supply voltage range is 3 to 6 volts with power dissipation of less
than 5.5mW at 5.5 volts. Single and dual tone capability.
Available in 16-pin plastic DIP with a temperature range from
- 40°C to + 85°C.

"DO

COL 1

ROW'

COL4

DISA8LE

Vss """'L..._ _•

esc IN

Pin Configuration

ICL8013
Four Quadrant Analog Multiplier
The ICL8013 is a bipolar, four-quadrant analog multiplier whose
output is proportional to the algebraic product of two input signals.
Feedback around an internal op-amp provides level shifting and can
be used to generate division and square root functions. A simple
arrangement of potentiometers may be used to time gain accuracy,
offset voltage and feedthrough performance.
Available in 1O-pin TO-l 00 metal package in both commercial and
military temperature ranges.

OUTPUT

ICL8013 Functional Diagram

ICL8038
Precision Waveform GeneratorlVoltage Controlled
Oscillator

SINE WAVE
ADJUST

SINE WAVE
OUT
TRIANGL.E

The ICL8038 Waveform Generator is capable of producing high
accuracy sine, square, triangular, sawtooth and pulse waveforms
with a minimum of external components. The frequency (or repetition
rate) can be selected externally from .001 Hz to more than 300KHz
using either resistors or capacitors, and frequency modulation, and
sweeping can be accomplished with an external voltage.
The 14-pin CERDIP package is available with O°C to + 70°C, and
- 55°C to + 125°C temperature ranges.

l'

OUT

DUTY
CYCLE
FREQUENCY
ADJUST

5

FM
BIAS

10

6~~~gITOR

9

~~~ARE WAVE

8

i~~~EEP

'----'
Pin Configuration

AD590
2·Wire, Current·Output Temperature Transducer
The AD590 is a 2-wire integrated-circuit temperature transducer
which produces an output current proportional to absolute temperature. The device acts as a high impedance constant current regulator, passing 1"AI"K for supply voltages between + 4V and + 30V.
Laser trimming of the chip's thin-film resistors is used to calibrate
the device to 298.2 "A output at 298.2°K ( + 25°C).
The AD590 could be used in any temperature-sensing application
between - 55°C and + 150°C in which conventional electrical temperature sensors are currently employed.
Plastic (TO-92) packaged device covers temperature ranges from
O°C to + 70C; Metal packaged device (TO-52) covers - 55°C to
+ 150°C range. With slope and offset trimming circuit it is possible
to adjust devices to give less than 0.1 % error over the temperature
range from O°C to 90°C.

R,
Sk!l

AD590 Slope and Offset Trimming Circuit

1-8

_O~OIl

AMPLIFIERS
Special Purpose Amplifiers

Content:

ICL420/421
± 15V Chopper Stabilized
Operational Amplifier

Special Purpose Amplifiers
Instrumentation Amplifiers
Log/Antilog Amplifiers
Drive Amplifier for Power Transistors
Operational Amplifiers
General Purpose
Low Power
Low Input Offset Voltage
Low Input Bias Qurrent

These chopper-stabilized CMOS operational amplifiers are
designed for signal conditioning, precision and instrumentation type applications. They offer a wide input and operating
supply range, allowing virtual plug-in replacements for conventional lower-performance amplifiers, requiring only two
additional external capacitors.
The ICL420 (8-pin) and ICL421 (14-pin) devices draw a
maximum supply current of 2 mA and are available in all
temperature ranges.
ICL7605/7606
Commutating Auto-Zero (CAZ)
Instrumentation Amplifier, CMOS
The ICL7605/ICL7606 CMOS com mutating auto-zero
(CAZ) instrumentation amplifiers are intended for lowfrequency operation in applications such as strain gauge
amplifiers which require voltage gains from 1 to 1000 and
bandwidths from DC to 10Hz. Since the CAZ amp automatically corrects itself for internal errors, the only periodic adjustment required is that of gain, which is established by two
external resistors. This, combined with extremely low offset
and temperature coefficient figures, makes the CAZ instrumentation amplifier very desirable for operation in severe
environments (temperature, humidity, toxicity, radiation, etc.)
where equipment service is difficult.
Available in three temperature ranges.

Features:
• Input Offset Voltage - 2p,V
• Input Offset Voltage Drift - 0.2p,V/Year
• Common Mode Input Voltage Range - 0.3V Above
Supply Rail
• Common Mode Rejection Ration -100 dB
• Operates at Supply Voltages As Low As ± 2V
• Short Circuit Protection On Outputs
• Compensated (ICL7605) or Uncompensated (ICL7606)
Versions

ICL8048/ICL8049
Log/Antilog Amplifier
The 8048 is a monolithic logarithmic amplifier capable of
handling six decades of current input, or three decades of
voltage input. It is fully temperature compensated and is nominally designed to provide 1 volt of output for each decade
change of input. For increased flexibility, the scale factor,
reference current and offset voltage are externally adjustable.
The 8049 is the antilogarithmic counterpart of the 8048; it
nominally generates one decade of output voltage for each
1 volt change in the input.

Features:

• v.% Full Scale Accuracy
•
•
•
•
•

Temperature Compensated for O·C to + 70·C
Scale Factor 1V/Decade, Adjustable
120dB Dynamic Current Range (8048)
60dB Dynamic Voltage Range (8048 & 8049)
Dual JFET-Input Op-Amps

ICL8063
Power Transistor Driver/Amplifier
Features:

The ICL8063 is a monolithic transistor driver and amplifier
primarily intended for driving complementary output stages.
The ICL8063 takes the output levels (typical ± 11 V) from
an op amp and boosts them to ± 30V to drive power transistors, (e.g. 2N3055 (NPN) and 2N3789 (PNP)). The outputs
from the ICL8063 supply up to 100mA to the base leads of
the external power transistors.

• When Used in Conjunction with General-Purpose Op
Amps and External Complementary Power Transistors, System Can Deliver >50 Watts to External Loads
• Built-In Safe Area Protection and Short-Circuit
Protection
• Built-In ± 13V Regulators to Power Op Amps or Other
External Functions

1-9

AMPLIFIERS
Operational Amplifiers
Intersi! offers a range of single and multiple monolithic operational amplifiers suitable for a number of specific applications categories. Included are bipolar Super-Beta and
Chopper-Stabilized CMOS devices for very low input offset
requirement, a selection of PMOS and JFET-input devices

for very low bias currents, as well as general-purpose and
low-power amplifiers for a broad range of applications.
All monolithic operational amplifiers are available in a variety of packages and in die form.

Operational Amplifiers: General Purpose

Description

ICL7611

CMOS, Selectable 10

ICL8007M
ICL8007C

JFET Input Op-Amp
JFET Input Op-Amp

o to +70
-55 to + 125
-55 to + 125
o to +70

2,5,15

50

1.6

1.4

INT

±9

20
50

20
50

6
6

1.0
1.0

INT
INT

±18
±18

2,5,15

50

0.16

0.48

INT

±9

20
50

20
50

6
6

1.0
1.0

INT
INT

±18
±18

o to +70
-55 to + 125
-55 to + 125
o to +70

INT
INT
INT
INT

010+70&
-55 to + 125
-5510 + 125
010 +70

DUALS
ICL7621

CMOS, Fixed 10

ICl8043M
ICL8043C

JFET Input Op-Amp
JFET Input Op-Amp

TRIPLES
CMOS, Selectable 10

CMOS, Fixed 10

Low Power

Type

Description

SINGLES
ICL7611
ICL7612
ICL8021M
ICL8021C

CMOS,
CMOS.
Bipolar,
Bipolar,

Selectable 10
Extended CMVR
Selectable 10
Selectable 10

10
10
30
30

±9
±9
±18
±18

TRIPLES
CMOS, Selectable 10
Triple 8021 M
Triple 8021 C

CMOS, Fixed 10

1010

2,5,15
2,5,15
3
6

0.05
0.05
20
30

0.044
0.044
0.27
0.27

AMPLIFIERS
Operational Amplifiers: Special Purpose
Low/Ultra-low Input Offset Voltag~

Description

SINGLES
ICL7650C
ICL76501
ICL7650M
ICL7652C
ICL76521
ICL7652M

CMOS, Chopper-stabilized
CMOS, Chopper-stabilized
CMOS, Chopper-stabilized
Low-noise 7650C
Low-noise 76501
Low-noise 7650M

±8
±10
±20
±7
±10
±50

±0.02
±0.02
±0.03
±0.01
±0.02
±0.1

50
50
20
4.0
50
4.0
0.1
0.01

0.5
0.5
0.5
0.2
0.5
0.2

50

100
100
100
100
100
100

20
50
500
30
30
500

2.0
2.0
2.0
0.5
0.5
0.5

±9
±9
±9
±9
±9
±9

o to + 70
-25 to +85
-55 to + 125
o to + 70
-25 to +85
-55 to + 125

Oto+70&
-55 to +125
-55 to + 125
-55 to +125
o to + 70
a to + 70
-25 to +85
-25 to +85

Low Input Bias Current

Description

SINGLES
ICL7611
ICL7612
ICLS007M
ICLS007AM
ICLS007C
ICLS007AC
ICHS500
ICHS500A

CMOS, Selectable IQ
CMOS, Extended CMVR
JFET Input Op-Amp
JFET Input, Low Bias
JFET Input Op-Amp
JFET Input, Low Bias
PMOS Input
PMOS Inpuf, Low Bias

-

2,5,15
2,5,15
20
30
50
30
50
50

1.4
1.4
1.0
1.0
1.0
1.0
0.7
0.7

INT
INT
INT
INT
INT
INT
INT
INT

±9
±9
±IS
±IS
±IS
±18
.±o18
±18

0.5

2,5,15

0.48

INT

±9

-

DUALS
ICL7621

CMOS, Fixed IQ

a to

+ 70
&

ICL8043M
ICL8043C

JFET Input Op-Amp
JFET Input Op-Amp

20
50

0.5
0.5

20
50

1.0
1.0

INT
INT

±18
±18

50

0.5

5,10,20

1.4

INT

±9

-55 to +125
-55 to + 125
a to + 70

TRIPLES
CMOS, Selectable IQ

QUADS
ICL7641

CMOS, Fixed IQ

o to

+ 70
&

ICL7642

CMOS, Fixed IQ

50

0.5

5,10,20

1-11

0.044

INT

±9

-55 to +125

ANALOG SWITCHES AND MULTIPLEXERS
Content:
General Purpose Analog Switches
Drivers for FET Switches
Low Cost, Virtual Ground Switch Family
RFlVideo Switch Family
Multiplexers

General Purpose Analog Switches
Intersil offers two general-purpose switch lines, each with
various switch configurations. The first consists of bipolar
drivers controlling an associated set of field-effect switching
transistors in a multi-Chip structure that provides a wide
choice of parameters at low cost. The second is a monolithic
CMOS structure capable of improved performance and

greater reliability. All have break-before-make switch action.
All switches are available in commercial and military temperature ranges. Package options include Plastic DIP, CERDIP, Flat Pack and Metal Can (not all options are available
for all device types).

General Purpose Analog Switches
Switch Parameters
Switch
Family

Special
Features

Switch
Type

RDS(ON) IID(OFF) I
tON
I tOFF I Analog Voltage Range
(n Max)
(nA Max)
(ns Max) (ns Max)
(VSUPPLY = ±15V)

Multichip
DG123-125

Inverting/non-inverting logic
inputs

DG126-154
DG139-164

Dual Channel
Single Channel

DG180-191

Mature, Industry-standard switch,
JAN3851 0 Approved

PMOS

600

4

300

1000

-

N-JFET

10
15
30
50
80

10
10
1
1
1

tOOO
1000
600
600
600

2500
2500
1600
1600
1600

-

N-JFET

10
30
75

10
1
1

300
150
250

250
130
130

-7.5 to +15
-7.5 to +15
-IOta +15

2.0
0.5

250
450

200
250

-15to +15
-15to +15

Monolithic
DGM181-191

Monolithic replacement for
DG180 family

CMOS

50
75

DG200/201

Industry-standard low cost

CMOS

70/80

2.0

1000

500

-15to +15

DG211
DG212

Inverting
Noninverting

CMOS

175

5.0

1000

500

-15to +15

DG300A-303A

TTL compatible, low power

CMOS

50

1.0

300

250

-15to +15

IH311
IH312

High Speed Inverting
Noninverting

CMOS
CMOS

175

100

300

150

-15to +15

IH5040-47
IH5048-51
IH5052-53

Low quiescent current
Low RDS(ON)

CMOS

75
40
75

1.0
1.0
1.0

750
500
500

350
250
250

-IOta +10
-IOta +10
-11 to +11

IH5140-45

High speed, low power, low
leakage

CMOS

50

0.5

100

75

-11 to +11

IH5148-51

Low RDS(ON), high speed, low
power

CMOS

25

0.5

250
350
500

200
250
250

-14to+14

Separate Driver/Switch Combinations
IIH6201

I TTL level translator/driver

IIH401/A

I Low charge injection switch

I N-JFET I
I

I

30
30/50

I
I

0.5

I 50 (Typ) 1150 (Typ) I

15 pop (Min)

0.5

I 50 (Typ) 1150 (Typ) I

20 pop (Min)

Drivers for FET Switches

Output Swing

Monolithic bipolar drivers convert low-level positive logic
to high-level positive and negative voltages necessary to
drive FET switches.

1-12

Type

Number of
Channels

Positive
(V Max)

Negative
(V Max)

tON
ns
Max

tOFF
ns
Max

D123
D125
D129
IH6201

6TTUDTL
6 TTL
4 TTUDTL
2 TTL

VSupply
VSupply
VSupply
+14.0

-19.7
-19.7
-19.3
-14.0

250
250
250
200

400-800
400-800
1000
300

ANALOG SWITCHES AND MULTIPLEXERS
Switch Configurations

6

:

7

:

~I

8

~6"--_ _-<>O

~

o

()"'I"'~

I

~

Switch Configuration (Diagram)

SPST
(1)

I

Dual

SPST
(2)

I

Quad

SPST

I

4PST
(4)

(3)

I

Five

SPST

I

SPOT
(6)

(5)

I

Dual

SPOT
(7)

I

DPST
(8)

I

Dual

DPST

I

DPDT

(9)

(10)

OG140
OG153
OG129
OG154
OG126

OG145
OG163
OG139
OG164
OG142

OG123
OG125
OG141
OG151
OG133
OG152
OG134

OG146
OG161
OG144
OG162
OG143

OG180
OG181
OG182

OG186
OG187
OG188

OGM182
OG200

OG189
OG190
OG191

OG183
OG184
OG185

OGM190
OGM191

OGM184
OGM185

OG303A

OG302A

OG201
OG211
OG212

OG301A

OG300A
IH311
IH312

IH5040

IH5041
IH5048
IH5052/53

IH5140

IH5043
IH5051

IH5044

IH5045
IH5049

IH5142

IH5143

IH5144

IH5145

IH5150

IH5151

IH5042

IH5047

IH5050

IH5141
IH5148

IH5149

IH401/A

I

1-13

IH5046

Analog Switches and Multiplexers
Virtual GroundSw,tches, JFETs (P·Channel)

1H5017/5018

Each package contains up to four channels of analog gating
designed to eliminate the need for extemal drivers. The oddnumbered devices are designed to be driven directly from
TTL open-collector logic (15V). Each channel simulates a
SPOT switch. The parts are intended for high-performance
multiplexing and commutating use. All have turn-on/turn-oll
times of 500 ns and a leakage current (10(011» of 0.2 nA.

+i}?4=;
.
I

(12)

I

,

'"

IH5019/5020

~*S.~.'
----+-0:;"
o,,~

Switch Configuration
SPST

Dual
SPST

Triple
SPST

Quad Special Switch rDS(on)
SPST Features Typa (0 Max)

IH5021 IH5017 IH5013 IH5009 Common
IH5022 IH5018 IH5014 IH5010 Output
IH5023 IH5019 IH5015 IH5011 Separate
IH5024 IH5020 IH5016 IH5012 Output

P.JFET

100
150

,,
0"

Examples of Common Output and Separate Output
Switch Configurations

100
150

./:f

RFNideo Switches, CMOS
Designed for high-frequency operation, these switches utilize a "T" configuration where a shunt switch is closed when
the switch is open. This provides superior isolation between
input and output and greatly improves performance in the
video and RF region. Switch attenuation varies less than 3 dB
from dc to·100 MHz. Available in three (commercial and military) temperature ranges and in 14-pin plastiC DIP and 10-pin
T0-100 metal package.

CIRCUIT OF SWITCH CHANNEL
SWITCH
SOURCEo------ 7V), the
COMMON voltage will have a low voltage coefficient
(0.001 %N), low output impedance ('" 15n), and a temperature coefficient typically less than 80ppml'C.
The limitations of the on-chip reference should also be
recognized, however. With the 7107, the internal heating
which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastiC parts are poorer in this respect than ceramic.
The combination of reference Temperature Coefficient
(TC), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25 p.V to
80p.Vp-p. Also the linearity in going from a high dissipation
count such as 1000 (20 segments on) to a low dissipation
count such as 1111 (8 segments on) can suffer by a count or
more. Devices with a positive TC reference may require
several counts to pull out of an overrange condition. This is
because overrange is a low dissipation mode, with the three
least significant digits blanked. Similarly, units with a negative TC may cycle between overrange and a nonoverrange
count as the die alternately heats and cools. All these problems are of course eliminated if an external reference is
used.
The 7106, with its negligible dissipation, suffers from
none of these problems. In either case, an external reference can easily be added, as shown in Figure 5.

v·

TEST
The TEST pin serves two functions. On the 7106 it is
coupled to the internally generated digital supply through a
soon resistor. Thus it can be used as the negative supply
for externally generated segment drivers such as decimal
points or any other presentation the user may want to include on the LCD display. Figures 6 and 7 show such an
application. No more than a 1mA load should be applied.

y.

1Mu

7106

TO LCD

INTERSIL
1T17SO

DECIMAL POINT

v'

0335-7

Figure 6: Simple Inverter for Fixed Decimal Point

8.1Ik1l

7106/7107

7106/7107

l'Z

ICllOl9

y'
COMMON

7106

v(01

8P

-(
POINT
&eLECT

(01

0335-6

Figure 5: Using an External Reference
TEST

0335-8

Figure 7: Exclusive 'OR' Gate for
Decimal Point Drive
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE ANO SHALL BE IN LIEU OF ALL OTHER WARRANTIeS. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bun characterized but are not tesfBd.

2-5

n
I'"

......

0

~

n
I'"
...

0
...

•

ICL 71 08/ICL 7107
DISPLAY FONT
C:~3'{S6'89

Figure 8: Digital Section 7106

0336-9

0123"156789

--------,

I
I

I

I

I
I
I

I
I

,
I

,,
I

I

I
I

I

.,,,
I

--~~----~~--~------_+--_r--r_~----------~~
37 I TEST

IIOOU

L-__
D8C1

I

-+~=-~--_4~------------------------~~--~.,~1
D'~~
3!. ____________________________ ..J GROUND

Dec.

Dies

Figure 9: Digital SectIon 7107

0335-10

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY DSLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.
Nm'F:AH _ _ ha.. _ _ bu/.,.not_

2·6

ICL 71 06/ICL 7107
The second function is a "lamp test". When TEST is
pulled high (to V +) all segments will be turned on and the
display should read - 1888. The TEST pin will sink about
10mA under these conditions.
Caution: on the 7106, in the lamp test mode, the segments have a constant DC voltage (no square-wave) and
may burn the LCD display if left in this mode for several
minutes.

The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
three convert-cycle phases. These are signal integrate
(1000 counts), reference de-integrate (0 to 2000 counts)
and auto-zero (1000 to 3000 counts). For signals less than
full scale, auto-zero gets the unused portion of reference
deintegrate. This makes a complete measure cycle of 4,000
counts (16,000 clock pulses) independent of input voltage.
For three readings/second, an oscillator frequency of
48kHz would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz,
33%kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 66% kHz, 50kHz,
40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50 and 60Hz (also 400 and
440Hz).

DIGITAL SECTION
Figures 8 and 9 show the digital section for the 7106 and
7107, respectively. In the 7106, an internal digital ground is
generated from a 6 volt Zener diode and a large P channel
source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency
divided by 800. For three readings/second this is a 60Hz
square wave with a nominal amplitude of 5 volts. The segments are driven at the same frequency and amplitude and
are in phase with BP when OFF, but out of phase when ON.
In all cases negligible DC voltage exists across the segments.
Figure 9 is the Digital Section of the 7107. It is identical to
the 7106 except that the regulated supply and back plane
drive have been eliminated and the segment drive has been
increased from 2 to 8 mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19)
must sink current from two LED segments, it has twice the
drive capability or 16mA.
In both devices, the polarity indication is "on" for negative analog inputs. If IN LO and IN HI are reversed, this
indication can be reversed also, if desired.

COMPONENT VALUE SELECTION
Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 100,..A of quiescent current. They can
supply 20,..A of drive current with negligible non-linearity.
The integrating resistor should be large enough to remain in
this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 2 volt full scale, 470kO is near
optimum and similarly a 47kO for a 200.0 mV scale.

Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing (approx. 0.3 volt from either supply). In the 7106 or the 7107, when the analog
COMMON is used as a reference, a nominal ± 2 volt full
scale integrator swing is fine. For the 7107 with ±5 volt
supplies and analog COMMON tied to supply ground, a
± 3.5 to ± 4 volt swing is nominal. For three readings/ second (48kHz clock) nominal values for CINT are 0.22,..F and
0.10,..F, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing.
An additional requirement of the integrating capacitor is
that it must have a low dielectric absorption to prevent rollover errors. While other types of capacitors are adequate
for this application, polypropylene capacitors give undetectable errors at reasonable cost.

System Timing
Figure 10 shows the clocking arrangement used in the
7106 and 7107. Three basic clocking arrangements can be
used:
1.
An external oscillator connected to pin 40.
2.
A crystal between pins 39 and 40.
3.
An R-C oscillator using all three pins.

I

710117107

I

I

:

I
I
I

TO
:
COUNTERt

I

I

I

I
I

I
I

L _______ _
I

3,!1________

~

I

________ J

Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence
on the noise of the system. For 200mV full scale where
noise is very important, a 0.47,..F capacitor is recommended. On the 2 volt scale, a 0.047,..F capacitor increases the
speed of recovery from overload and is adequate for noise
on this scale.

EXTERNAL
OSCILLATOR
TEST (7101)
OlGND(7107)

0335-11

Figure 10: Clock Circuits

INTERSIL·S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values hSV6 b6en characterized but are not tested.

2-7

•

.O~OIl.

S
... ICL7106/ICL7107

...

d
~

o

...
...

d_

In fact, in selected applications no negative supply is required. The conditions to use a single + 5V supply are:
1.
The input signal can be referenced to the center of
the common mode range of the converter.
2.
The signal is less than ± 1.5 volts.
3.
An external reference is used.

Reference Capacitor
A 0.1).'F capacitor gives good results in most applications. However, where a large common mode voltage exists
(I.e. the REF LO pin is not at analog COMMON) and a
200mV scale is used, a larger value is required to prevent
roll-over error. Generally 1.0).'F will hold the roll-over error
to 0.5 count in this instance.

TYPICAL APPLICATIONS

Oscillator Components

The 7106 and 7107 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatility of these AID converters.

For all ranges of frequency a 100kO resistor is recommended and the capacitor is selected from the equation
0.45
f='RC' For 48kHz clock (3 readings/second), C= 100pF.

Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is: VIN = 2VREF. Thus, for the 200.0mV and
2.000 volt scale, Vref should equal 100.0 mV and 1.000 volt,
respectively. However, in many applications where the AID
is connected to a transducer, there will exist a scale factor
other than unity between the input voltage and the digital
reading. For instance, in a weighing system, the designer
might like to have a full scale reading when the voltage from
the transducer is 0.682V. Instead of dividing the input down
to 200.0mV, the designer should use the input voltage directly and select VREF=0.341V. Suitable values for integrating resistor and capacitor would be 120kO and 0.22).'F.
This makes the system slightly quieter and also avoids a
divider network on the input. The 7107 with ± 5V supplies
can accept input signals up to ±4V. Another advantage of
this system occurs when a digital reading of zero is desired
for VIN*O. Temperature and weighing systems with a variable tare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset
voltage between COMMON and IN LO.

71"
'-'

To pin 1
40
011(:1
OSC2
011(:'
TEST

l00Kn
Sel VREF'" l00.OnIY

/

1000F

REF HI

REFLO
CREF
C REF
COMMON

1KU

Do.1p.F

22Kn

lMn

INHI
INLO

+
IN

_".OI,F

-

O.47~F

AlZ
BUFF
INT
y-

.7Kn

0.22 F

~tV

T

O,
C,
ITO DISPLAY

A3
0,
B'

f---

TO BACK PLANE

21

0335-13

Figure 12: 7106 using the internal reference_
Values shown are for 200_0 mV full scale,
3 readings per second, floating supply
voltage (9V battery)_

7107 Power Supplies
The 7107 is designed to work from ±5V supplies. However, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors, and an
inexpensive I.C. Figure 11 shows this application. See
ICL7660 data sheet for an alternative.

0335-12

Figure 11: Generating Negative Supply
from +5V

INTER$IL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical va//JfJS havs been characterized but 8f9 not tested.

2-8

IIlD~OIL

ICL 71 06/ICL 7107

n
r-

......
o
GI

"07
~

To,," ,

7107

40
OIC'
01C2
ole 3
TEST
AIFHI
RIFLO
C REF

C REF
COMMON

'-'

100Kn
. ., VREF '" 100.OnI.V

.00;..

,/
.'A

DO"J,.tF

22KU

IN HI

• •OlJ..tF

.,#"

O.

Afl

47KlI

BUFF

INT
VG,
e,
A,
G,
GND

,
,,
,

!

~ TO DISPLAV

i
2'

. --------- --- -----_.

OND

710117107

osc 1
OSC 3
TEST
REF HI
REF LO
C REF

C REF

••

Afl
INT
VG,
e,

A:o
G,
GND

":"

To pin 1
40

.....
p ..,

100KH

OSe2
OSC 3

l00Ktl

'Kl! ,

At,

REF HI

/

REF LO

10Kn

.~,

'.~',;.

1

C REF
v+

C REF
COMMON
IN HI
INLO

.... •2V (leL8069)
lMI1

0.47/.1F ..
47KH

0.22 F

,

iTO DISPLAY

'"

:I

25KH

V+
24Kn

+
IN

.047JlF

...:-

470Kn

0.221/oF

V-

iTO DISPLAV

A:o

:

/

.'A

1Mn

INT
VG,
e3

V-

SttVREF'" 1.ooov

• •011/0'

BUFF

I
I
I

:I

DO,'J..tF

Afl

IN

1Ip.0l"F

....

'

TEST

Set VREF = too.OmY

IHHI

BUFF

h

'-' OSC'

COMMON
INLO

f TO DISPLAY
I

Figure 15: 7107 with Zener diode reference.
Since low T.C. zeners have breakdown voltages
- 6.aV, diode must be placed across the total
supply (10V). As in the case of Figure 15, IN LO
may be tied to either COMMON or GND.

To pin 1

OSC2

-5V

0335-16

0335-14

'-'

0.22J..tF

21

Figure 13: 7107 using the Internal reference.
Values shown are for 200.0mV full scale, 3
readings per second. IN LO may be tied to either
COMMON for Inputs floating with respect to
supplies, or GND for single ended inputs. (See
discussion under Analog COMMON.)

7107

41KII

G'p:
e'l=
A'I=
G'I=

-=-

IN

O.47j.1F ...

INT
V'

-5V

_IV

'~K" '.:l ~ •••Y

.,OlJ,.tF

BUFF

••22,F

\..,{
1KIl

...

1oo.OmY

lM11

INHI
INLO
All

IN

Set YREF

DO""[

COMMON

+

.....

100Kli

C REF

,Mn

INLO

40
OIC'
ole 2
OSC3

TlST
AEF HI
RIFLe
e AEF

+5V

tKH

5r......
o

To 1M" 1

OP/GND

21~-------------- .J

2'

0335-17

Figure 16: 710617107: Recommended
component values for 2.000V full scale.

0335-15

Figure 14: 7107 with an external band-gap
reference (1.2V type). IN LO is tied to COMMON,
thus establishing the correct common mode
voltage. If COMMON is not shorted to GND, the
input voltage may float with respect to the
power supply and COMMON acts as a preregulator for the reference. If COMMON is
shorted to GND, the input is single ended
(referred to supply ground) and the preregulator is over-ridden.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been chBracterizsd but are not tested.

2-9

•

..
......

:; ICL7106/ICL7107

()

..~...
o

~

~

OSCl

'-./

'0
s.t~REF

,AlA - "

REFLO
C REF
C REF F P O I .
COMMON
IN HI
INlO

,A

DO.,••L

IN HI

100KJl

~"K"

471<11

lUFF
INT
V-

0.22 ... '

a,

0.22 F

C,
A,
G,

I TO DIS'LA.

"'

SNK:on HPN
UPS 3704 01

IintH.,

hti----~

22OK1I

\HfoadJu.t

0 ..17... '

IoIZ

IN

G'I=

-

"'---

..:.,9Y

~

ITODIS.LA.

I-- -

TO BACK PLANE

21

GND

0335-20

21

Figure 19: 7106 used as a digital centigrade
thermometer. A silicon diode-connected
transistor has a temperature coefficient of
about - 2mY
Calibration is achieved by
placing the sensing transistor in ice water and
adjusting the zeroing potentiometer for a 000.0
reading. The sensor should then be placed in
boiling water and the scale-factor potentiometer
adjusted for 100.0 reading.

0335-18

Figure 17: 7107 operated from single +5Y
supply. An external reference must be used in
this application, since the voltage between Y+
and Y- is insufficient for correct operation of
the internal reference.

7107

~

1MO

,Ol~F-.

INlO

--<>

47KI1

e'F
A'F
G'F

/'

1 Kn

COMMON

~1.2V(ICL80")
1M!1
• .01 ... F

~fllClofactj"'t

lOOp.

TEST
REF HI
REFLO
CAEF
C REF

+5V

lKn • .,,'0K,iT 15K"

0.47,,'

A/Z
BUFF
INT
V-

100KII

Olel

100.OmY

,

100pF

REF HI

OSCI
OSC2

l00Ku

OSC 2

ose3
TEST

To pin 1
'0

710.

To pin 1

7107

rc.

v+

To pin 1

40
OSCl
OSC2
OSe3
TEST

1DOKn

100pF

REF HI
AEF LO
C REF
C REF

COMMON
INHf
IN LO

A/Z
BUFF

INT
VG,

c,

A,
Cl:l
GND

.47j.1F
47KII

O.22/.1F

I
1TO DISPLAV

0335-19

Figure 18: 7107 measuring ratiometric values of
Quad Load Cell. The resistor values within the
bridge are determined by the desired sensitivity.

0335-21

Figure 20: Circuit for developing Underrange
and Overrange signals from 7106 outputs.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CCNDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but 8r6 not tested.

2-10

ICL 71 06/ICL 7107

-

-

v+

D.

"'" o.ci

TEST

C.

R.,HI

A.

_LO

CR.,

O'

I'
D.

Vee

111en

.
.
.

C2

CRI'

CDIIIION
INHI

AI
FI

.INLO

INT

DS

-

A016
A017
A018

v-

V-

Go
Co

...

Fa

A14

POL

APPLICATION NOTES

AIr

lun

es

..

..

o.c.
o.cs

••
••

To

al components required, then wiring a breadboard, can often cause delays of days or sometimes weeks. To avoid this
problem and facilitate evaluation of these unique circuits,
Intersil is offering a kit which contains all the necessary
components to build a 3Yz-digit panel meter. With the help
of this kit, an engineer or technician can have the system
"up and running" in about half an hour•
Two kits are offered, the ICL710SEVIKIT and the
ICL7107EVlKIT. Both contain the appropriate IC, a circuit
board, a display (LCD for 7106EVlKIT, LEOs for 7107EVI
Kin, passive components, and miscellaneous hardware.

Go

OND

A023

21

A032

or 74C10

A046

0335-22

Figure 21: Circuit for developing Underrange
and Overrange signals from 7107 outputs. The
LM339 Is required to ensure logic compatibility
with heavy display loading.

A052

"Selecting AID Converters", by David Fullagar.
"The Integrating AID Converter", By Lee Evans.
"Do's and Don'ts of Applying AID Converters", by
Peter Bradshaw and Skip Osgood.
"Low Cost Digital Panel Meter Designs", by David
Fullagar and Michael Dufort.
"Understanding the Auto-Zero and Common Mode
Performance of the ICL710S/7/9 Family", by Peter
Bradshaw.
"Building a Battery-Operated Auto Ranging DVM
with the ICL7106", by Larry Goff.
"Tips for Using Single-Chip 3Va-Digit AID Converters", by Dan Watson.

7106/7107 EVALUATION KITS
After purchasing a sample of the 710S or the 71 07, the
majority of users will want to build a simple voltmeter. The
parts can then be evaluated against the data sheet specifications, and tried out in the intended application. However,
locating and purchasing even the small number of addition-

7101

.

To pin 1

=~LJo_"""",,'_IIOKI~1

Scale lactor HI""
(VAeF ::. 1QOmY lor AC to RUI)

OIC S 0-..".=,It--...J

TI.T~:::::~===:-:;Y
RI.HI[

RIF LOO--"'""1r-"VIN+'V\I\r-4
CRIF
COMMON~~~~~~~r:t:=~~~j:~~~,-~~~3l~Ej~
IN~~

ACIN

CRI.

IN HI

..7.'

__

-+~

O.22~F

Bun Lr_"""""4,,,7K..n...

'::~=~~~a~F~-L___~~t:=::~::::::::::::::====~_~
C,

::
...

}

TO DI'PLAY
TO BACK PLANt

0035-23

Figure 22: AC to DC Converter with 7106. TEST Is used as a common mode reference level to ensure
compatibility with most op-amps.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OSUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANnES. EXPRESS. IMPUED OR STATUTORY. INCLUDING THE IMPLIED WARRANnES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typIc8I values have bBsn chsracterlzeKJ but BTS not fBsl8d.

2-11

•

...~
...
U

ICL7106/ICL7107

too

=::.
G

...otoo

2

0335-24

Figure 23: Display Buffering for increased drive current. Requires four DM7407 Hex Buffers. Each buffer is
capable of sinking 40 mAo

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANnES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARnCULAR USE.

NOTE: AU typical vsJuss have bssn _terlzsd

but.,. not

tostsd.

2-12

D~DlLe......

ICL7116/7117
3%-Digit LCD/LED
Single-Chip A/D Converter
with Display Hold

.........
0)

......

.....

GENERAL DESCRIPTION

FEATURES

The Intersil ICL7116 and 7117 are high performance, low
power 3-% digit AID converters. All the necessary active
devices are contained on a single CMOS I.C., including seven segment decoders, display drivers, reference, and a
clock. The 7116 is designed to interface with a liquid crystal
display (LCD) and includes a backplane drive; the 7117 will
directly drive an instrument-size light emitting diode (LED)
display.
The 7116 and 7117 have almost all of the features of the
7106 and 7107 with the addition of a HoLD Reading input.
With this input, it is possible to make a measurement and
then retain the value on the display indefinitely. To make
room for this feature the reference input has been referenced to Common rather than being fully differential. These
circuits retain the accuracy, versatility, and true economy of
the 7106 and 7107. They feature auto-zero to less than
1O,...V, zero drift of less than 1,...VI'C, input bias current of
10pA maximum, and roll over error of less than one count.
The versatility of true differential input is of particular advantage when measuring load cells, strain gauges and other
bridge-type transducers. And finally, the true economy of
single power supply operation (7116) enables a high performance panel meter to be built with the addition of only
eleven passive components and a display.

•
•
•
•
•
•

•
•
•
•
•

HoLD Reading Input Allows Indefinite Display Hold
Guaranteed Zero Reading for 0 Volts Input
True Polarity at Zero for Precise Null Detection
1pA Input Current Typical
True Differential Input
Direct Display Drive - No External Components
Required - LCD ICL7116
- LED ICL7117
Low Noise - Less Than 15,...V pk-pk Typical
On-Chip Clock and Reference
Low Power Dissipation - Typically Less Than 10mW
No Additional Active Circuits Required
New Small Outline Surface Mount Package Available

ORDERING INFORMATION
Part
Number

Temperature
Range

Package

ICL7116CPL
ICL7116CM44

O°C to + 70°C
O°C to +70~C

40-Pin Plastic DIP
44-Pin Surface Mount

ICL7117CPL

40-Pin Plastic DIP

HLOR r-I'!I--'"""!-'--'lI'I!Ih osc 1
01
OSC2

iii
t:

~

1~~

-

A1
F1
G1
E1
02

1

~~;/
ICL7116 (LCD)
ICL7117 (LED)

REF HI
REF LO
C+REF
C-REF

~ ~~

:~ ~6

AF22

AlZ
BUFF

~

~T

~

c;~ {

03
83

~~E3
~

(1000) AB4

POL
(MINUS)

G2

COMMON
TEST

C3

OSC 3

A3

OSC 2

BP

G3

v-

G2 (TENS)

~}~
A3g

G3 ~
BP/GNO
(7116V(7117)

ose 1

POL

Hl. OR

AU

0'

E3

C,

F3

B'

B3

0338-1

0338-2

Figure 1: Pin Configurations

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

2-13

•

... ICL7116/7117
....

....

CD ABSOLUTE MAXIMUM RATINGS
;:

!:i

2

ICL7116

ICL7117

Supply Yoltage (Y+ to Y-) ........................ 15Y
Analog Input Yoltage (either input) (Note 1) ..... Y+ to YReference Input Yoltage (either input) ......... Y+ to YHLDR, Clock Input ......................... Test to Y+
Power Dissipation (Note 2)
Ceramic Package .......................... 1000mW
Plastic Package ............................. 800mW
Operating Temperature ................... O'C to + 70'C
Storage Temperature ................ - 65'C to + 150'C
Lead Temperature (Soldering, 1Osee) ............. 300'C

Supply Yoltage Y + .............................. + 6Y
Y- .............................. -9Y
Analog Input Yoltage (either input) (Note 1) ..... Y+ to YReference Input Yoltage (either input) ......... Y+ to YHLDR, Clock Input ......................... Gnd to Y+
Power Dissipation (Note 2)
Ceramic Package .......................... 1000mW
Plastic Package ............................. 800mW
Operating Temperature ................... O'C to + 70'C
Storage Temperature ................ -65'C to + 150'C
Lead Temperature (Soldering, 1Osee) ......•...... 300'C

Note 1: Input voltages may exceed the supply voltages provided the input current is limited to ± 1OOIlA.

Note 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specificalions is not implied. Exposure to absolute
maximum rating conditions for extended periods may aHect device reliability.

ELECTRICAL CHARACTERISTICS
Parameter

(Note 3)

Test Conditions

Min

Typ

Max

Unit

-000.0

±OOO.O

+000.0

Digital Reading

Zero Input Reading

YIN=O.OY
Full Scale=200.0mY

Ratiometric Reading

YIN=YREF
YREF=100mY

999

999/1000

1000

Digital Reading

I YIN I '" 200.0mY

-1

±0.2

+1

Counts

Lineari! (Max. deviation from
best straight line fit)

Full Scale=200mY
or Full Scale = 2.000Y (Note 7)

-1

±0.2

+1

Counts

Common Mode Rejection Ratio
(Note 4)

YCM= ±1Y, YIN = OY,
Full Scale=200.0mY

50

",Y/V

Noise (Pk - Pk value not exceeded
95% of time)

YIN=OY
Full Scale=200.0mY

15

",y

Leakage Current

YIN = OY (Note 7)

1

10

pA

0.2

1

",Y/'C

1

5

ppml'C

0.8

1.8

mA

0.6

1.8

mA

2.8

3.2

Y

Rollover Error (Difference in
reading for equal positive and
~ ·eading near Full Scale)

@

Input

Zero Reading Drift
Scale Factor Temperature
Coefficient
Y + Supply Current (Does not
include LED current for 7117)

YIN=O
O'C7V), the COMMON voltage will have a low voltage coefficient (.001 %N), low output impedance ('" 150),
and a temperature coefficient typically less than 80ppmrC.
The limitations of the on-chip reference should also be
recognized, however. With the 7117, the internal heating
which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic.
The combination of reference Temperature Coefficient
(TC), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25,..,V to
80,..,Vpk-pk. Also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low dissipation count such as 1111 (8 segments on) can suffer by a
count or more. Devices with a positive TC reference may
require several counts to pull out of an overload condition.
This is because overload is a low dissipation mode, with the
three least significant digits blanked. Similarly, units with a
negative TC may cycle between overload and a nonoverload count as the die alternately heats and cools. All these
problems are of course eliminated if an external reference is
used.
The 7116, with its negligible dissipation, suffers from
none of these problems. In either case, an external reference can easily be added, as shown in Figure 5.

TEST
The TEST pin serves two functions. On the 7116 it is
coupled to the internally generated digital supply through a
5000 resistor. Thus it can be used as the negative supply
for externally generated segment drivers such as decimal
points or any other presentation the user may want to include on the LCD display. Figures 6 and 7 show such an
application. No more than a 1mA load should be applied.

y+

7116

TO LCD
DECIMAL POINT

0338-7

Figure 6: Simple Inverter for Fixed Decimal Point

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THI;: IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical valuss haV9 been characterized but sre not 18sted.

2-17

•

.......~
....UI
......
.......

ICL7116/7117
Figure 9 is the Digital Section of the 7117. It is identical to
that of the 7116 except the regulated supply and back plane
drive have been eliminated and the segment drive has been
increased from 2 to 8mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19)
must sink current from two LED segments, it has twice the
drive capability or 16mA.
In both devices the polarity indicator is ON for negative
analog inputs. This can be reversed by simply reversing IN
LO and IN HI.

r-----------------,V+
V+

2

B,~:~D+-l
D--t-1

I

7116

I

DECIMAL
POINT
SELECT

[

,
I

I
D+I

TO LCD
DECIMAL
POINTS

: D+I
I

CD4030

....- T ' " -.... V-o- = DP ON,
L__
GROUND = DP OFF.

1
I

__.J

HOLD Reading Input

\OND

The HLDR input will prevent the latch from being updated
when this input is at a logiC "1 ". The chip will continue to
make AID conversions, however, the results will not be updated to the internal latches until this input goes low. This
input can be left open or connected to TEST (7116) or
GROUND (7117) to continuously update the display. This
input is CMOS compatible, and has a 70kO typical resistance to either TEST (7116) or GROUND (7117).

0338-8

Figure 7: Exclusive 'OR' Gate for
DeCimal Point Drive
The second function is a "lamp test". When TEST is
pulled to high (to V+) all segments will be turned on and the
display should read - 1888. [Caution: on the 7116, in the
lamp test mode, the segments have a constant DC voltage (no square-wave) and will burn the LCD display If
left in this mode for several minutes.)

DIGITAL SECTION
Figures 8 and 9 show the digital section for the 7116 and
7117, respectively. In the 7116, an internal digital ground is
generated from a 6 volt Zener diode and a large P channel
source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency
divided by 800. For three readings/second this is a 60Hz
square wave with a nominal amplitude of 5 volts. The segments are driven at the same frequency and amplitude and
are in phase with BP when OFF, but out of phase when ON.
In all cases negligible DC voltage exists across the segments.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterfzed but are not t9St6(i.

2·18

ICL7116/7117
DISPLAY FONT

02 :1 '-I 5 6"18 9

--------------·---·-------------------·-----4-------++-1+lH+--HH!·I+--++++H-!----:..'==~:;_

•
--~---4--+---~.-

--------------------------6'=--OSC.

OSC3

0338-9

Figure 8: Digital Section 7116

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values haVB been characterized but are not tested.

2-19

..........
........o
......

ICL7116/7117

o
,.,. C,

....
....
2

'c,·

.'.'.
•

--~~------~~~-----------4----~-4---+------------~VT
37
500

n

TEST
I

I

211 OIGITAL

~---1~~~----~~--------------~,_==_=_=_=_~_4-_-_-_~_--_-_~_~~~G.OUND
HLOA

osc.

OSCI

osc.

0338-10

Figure 9: Digital Section 7117
The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
three convert-cycle phases. These are Signal integrate
(1000 counts), reference de-integrate (0 to 2000 counts)
and auto-zero (1000 to 3000 counts). For signals less than
full scale, auto-zero gets the unused portion of reference
deintegrate. This makes a complete measure cycle of 4,000
(16,000 clock pulses) independent of input voltage. For
three readings/second, an oscillator frequency of 48kHz
would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz,
33%kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 66%kHz, 50kHz,
40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/ second) will reject both 50 and 60Hz (also 400 and
440Hz).

System Timing
Figure 10 shows the clocking arrangement used in the
7116 and 7117. Three basic clocking arrangements can be
used:
1.
An external oscillator connected to pin 40.
2.
A crystal between pins 39 and 40.
3.
An R-C oscillator using all three pins.

I

711117117

I

I

I

i

I
I

TO
:
COUNTE"I
I

I

,
,iL _______ _

~--------

..

,
i
'

_________ J

IXTIRMAL

OSCILLATOR

TEST (7"1)
or GNO (7117)

0338-11

Figure 10: Clock Circuits

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-20

tIlO~OIL C;
r-

ICL7116/7117

digital reading. For instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.682V. Instead of dividing the
input down to 200.0mV, the designer should use the input
voltage directly and select VREF=0.341V. Suitable values
for integrating resistor and capacitor would be 120kO and
0.22",F. This makes the system slightly quieter and also
avoids a divider network on the input. The 7117 with ± 5
volts supplies can accept input signals up to ± 4 volts. Another advantage of this system occurs when a digital reading of zero is desired for VIN*O. Temperature and weighing
systems with a variable tare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset voltage between COMMON and IN LO.

COMPONENT VALUE SELECTION
Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 100",A of quiescent current. They can
supply 20",A of drive current with negligible non-linearity.
The integrating resistor should be large enough to remain in
this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 2 volts full scale, 470kO is near
optimum and similarly a 47kO resistor is optimum for a
200.0mV scale.

Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing (approx. 0.3 volt from either supply). In the 7116 or the 7117, when the analog
COMMON is used as a reference, a nominal ±2 volt full
scale integrator swing is fine. For the 7117 with ± 5 volt
supplies and analog common tied to supply ground, a ± 3.5
to ±4 volt swing is nominal. For three readings/second
(48kHz clock), nominal values for CINT are 0.22",F and
0.10",F, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing.
An additional requirement of the integrating capacitor is it
have low dielectric absorption to prevent roll-over errors.
While other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at
reasonable cost.

7117 Power Supplies
The 7117 is designed to work from ± 5 volt supplies.
However, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors,
and an inexpensive I.C. Figure 11 shows this application.
See ICL7660 data sheet for an alternative.

v+

osc.
osc ...........-ll-..J

7117

Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence
on the noise of the system. For 200mV full scale where
noise is very important, a 0.47",F capacitor is recommended. On the 2 volt scale, a 0.047",F capacitor increases the
speed of recovery from overload and is adequate for noise
on this scale.

v·

0338-12

Figure 11: Generating Negative Supply
from +5v

Reference Capacitor
A 0.1 ",F capacitor gives good results in most applications. If rollover errors occur a larger value, up to 1.0",F may
be required.

In fact, in selected applications no negative supply is required. The conditions to use a single + 5V supply are:
1.
The input signal can be referenced to the center of
the common mode range of the converter.
2.
The signal is less than ± 1.5 volts in magnitude.
3.
An external reference is used.

Oscillator Components
For all ranges of frequency a 100kO resistor is recommended and the capacitor is selected from the equation
0.45
f"'FiC' For 48kHz clock (3 readings/second), C= 100pF.

TYPICAL APPLICATIONS
The 7116 and 7117 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatility of these A/ D converters.

Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is: VIN=2VREF' Thus, for the 200.0mV and
2.000 volt scale, VREF should equal 100.0mV and 1.000
volt, respectively. However, in many applications where the
AID is connected to a transducer, there will exist a scale
factor other than unity between the input voltage and the

lNTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been characterized but ar9 not tested

2-21

..........

....0.....

......

....

•

........ ICL7116/7117
....

......
...
IS)

S2

711.
'-" Gee 1

....., osc.

1HKl1

PICa

lei 'lREF

Gee.
TaT
R.PHI
V+
CREF
C RE'
COMMON
INH.

/

100P'

10n

c:::5=o.1#'F

'.':Y

'"

}TO DISPLAY

ar

'00p'

-

C REF

-A

/
A',

.S.Ii

==:;:0.1J.lF

C REF

COMMON

+

...-

.7Kll

".H.'

Set VAEF '" 1.000V

OSC.
TEST

220.1

0.4710"

y0,
C,

ep

V

1Mn

aUFF
INT

Cl3

·.oo....

11'.01,.

All

,A 1OOKll

osc 2

AEFHI
y.

A'A

'-

INLO

..

7116/7117

40

1Mn

INHI
IN LO

IN

-

AlZ

.:,.8V

BUFF

..01 .... F

y+

.

IN

,047,.F

;',.J

470KH

'.r.22j.1.F

INT

•

G,
C3

-"on

F

y-

I TO DISPLAY

A31=
G3
.P/GND

El

••

TO lACK PLANE

0338-15

Figure 14: 711617117: Recommended
component values for 2.000V full scale.

0338-13

Figure 12: 7116 using the internal reference.
Values shown are for 200.0mV full scale,
3 readings per second, floating supply
voltage (9V battery).

7117
40
'-' OSC1

.....,

lOOKti

osc.
osc.

7117

4O

OSC1
08C2

100Ktl

Set VREF = i00AmY

osc,

'oOP'

TEST

REFH.
y+
C REF
C REF

All
BUFF

INT
y-

,'A

c:::5=O.1Io'F

,

1Mn

IN LO
A/Z

+

47Kfl

C,
}TODISPLAY

=;

s.t VAEF =l00.amY

/
~ 10KJ;T 15KU
1I"l •.•V(ICL ....)

+5Y

1M!1

• . Ot••

IN

0.47,1

r
v·

U;

t:

~
-

Cl
Bl
Al
Fl
Gl
El

r-r
_

~

w
!:.

C2

B2
A2
F2
E2

~

833
~
F3
E3
(1000) AB4
POL
(MINUS)

:~~~:Ei:9Ntt~>

OSCl
OSC2
OSC3
TEST
REF HI
REF LO

~~t..)c.JB!:~~~== I

C+REF

C-REF
COMMON
INHI
INLO

G2
C3
A3
G3
BP
POL
AB4
E3
F3
B3

TEST
OSC 3
OSC 2
OSC 1
y+
Ol
Cl
Bl

A/Z

BUFF
INT

v-

G2 (TENS)
C3j"::
A3
g
G3 ~
BP

_ _ .... . - N N f N N N N C " )

cu..eWQ(,)ccccu..WQ

0339-1

0339-2

Figure 1: Pin Configurations

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, eXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-24

ICL7126
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V + to V -) ........................ 15V
Analog Input Voltage (Either Input) (Note 1) .... V+ to VReference Input Voltage (Either Input) ......... V+ to VClock Input ............................... TEST to V+

Power Dissipation (Note 2)
Ceramic Package ............................ 1000mW
Plastic Package ..........•.................... 800mW
Operating Temperature ................... O·C to + 70·C
Storage Temperature ................ -65·C to + 150·C
Lead Temperature (Soldering, 10sec) ............. 300·C

NOTE 1: Input voltages may exceed the supply voltages provided the input current is limited to ± 100,..A.
NOTE 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the speCifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliabillly.

ELECTRICAL CHARACTERISTICS
Characteristics

(Note 3)

Test Conditions

Min

Typ

Max

Unit

-000.0

±OOO.O

+000.0

Digital Reading

Zero Input Reading

VIN=O.OV
Full Scale=200.0mV

Ratiometric Reading

VIN=VREF
VREF=100mV

999

999/1000

1000

Digital Reading

Rollover Error (Difference in
reading for equal positive and
negative reading near Full Scale)

1- VIN 1= + VIN "" 200.0mV

-1

±0.2

+1

Counts

Linearity (Max. deviation from
best straight line fit)

Full scale = 200mV
or full scale = 2.000V

-1

±0.2

+1

Counts

Common Mode Rejection Ratio
(Note 4)

VCM= ±1V, VIN=OV
Full Scale = 200.0mV

50

ILVN

Noise (Pk • Pk value not exceeded
95% of time)

VIN=OV
Full Scale = 200.0mV

15

fLY

Leakage Current @ Input

VIN=OV

1

10

pA

Zero Reading Drift

VIN=O
O·C ....--_ TO DIGITAL SECTION

1
1

IN"'G'~3'~-4~~~__+-__~~-+______-J

,

INT

I
I
I
I

COMMON

'32
IHI'UT
LOW

I

I ..
INLO

L___

__________________ ..!:

..!~T

~

________________________ .. ___________ _
0339-3

Figure 2: Analog Section of 7126

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typics/ values have been characterized but are not tssteci

2·26

.D~DIL

ICL7126

n
r-

.......
I\)

TEST CIRCUITS

01

0339-6

Figure 5: Clock Frequency 48kHz.
(3 readings/sec)

0339-4

Figure 3: ICL7126 with Liquid Crystal Display

DETAILED DESCRIPTION
Analog Section

IN

Figure 2 shows the Functional Diagram of the Analog
Section for the ICL7126. Each measurement cycle is divid·
ed into three phases. They are (1) auto·zero (A·Z), (2) signal
integrate (I NT) and (3) de·integrate (DE).

Auto-zero phase
During auto·zero three things happen. First, input high
and low are disconnected from the pins and internally short·
ed to analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Third, a feedback loop is
closed around the system to charge the auto·zero capacitor
CAZ to compensate for offset voltages in the buffer amplifi·
er, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the
noise of the system. In any case, the offset referred to the
input is l!lsS then 10,..V.

Signal Integrate phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and
low are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a
wide common mode range; within one Volt of either supply.
If, on the other hand, the input signal has no return with
respect to the converter power supply, IN LO can be tied to
analog COMMON to establish the correct common-mode
voltage. At the end of this phase, the polarity of the integrated signal is determined.

0339-5

Figure 4: 7126 Clock Frequency
16kHz. (1 reading/sec)

De-integrate phase
The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and in-

INTERSIL·S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHAlL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical VBIuss MIIB btHm charactBrIzBd but tIfI1 not t6st6d.

2-27

•

..d...

:: ICL7126
-

put high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the
capacitor will be connected with the correct polarity to
cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the
input signal. Specifically the digital reading displayed is

ature changes of 2 to 8°C, typical for instruments, can givt;l a
scale factor error of a count or more. Also the common
voltage will have a poor voltage coefficient when the total
supply voltage is less than that which will cause the zener to
regulate «7V). These problems are eliminated if an external reference is used, as shown in Figure 6.

1000 ( VIN ).
VREF
y-

Differential Input

y'

The input can accept differential voltages anywhere within the common mode rante of the input amplifier; or specifically from 0.5 Volts below the positive supply to 1.0 Volt
above the negative supply. In this range the system has a
CMRR of 86 db typical. However, since the integrator also
swings with the common mode voltage, care must be exercised to assure the integrator output does not saturate. A
worst case condition would be a large positive commonmode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator
positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the
recommended 2V full scale swing with little loss of accuracy. The integrator output can swing within 0.3 Volts of either
supply without loss of linearity.

271<11

COMMON

Vo

I')

Ib)

0339-7

Figure 6: Using an External Reference

The reference voltage can be generated anywhere within
the power supply voltage of the converter. The main source
of common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage,
the reference capaCitor can gain charge (increase voltage)
when called up to de-integrate a positive Signal but lose
charge (decrease voltage) when called up to deintegrate a
negative input signal. This difference in reference for ( + ) or
(-) input voltage will give a roll-over error. However, by
selecting the reference capaCitor large enough in comparison to the stray capacitance, this error can be held to less
than 0.5 count for the worst case condition. (See Component Value Selection.)

Analog COMMON is also used as the input low return
during auto-zero and de-integrate. If IN LO is different from
analog COMMON, a common mode voltage exists in the
system and is taken care of by the excellent CMRR of the
converter. However, in some applications IN LO will be set
at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied
to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently referenced
to analog COMMON, it should be since this removes the
common mode voltage from the reference system.
Within the IC, analog COMMON is tied to an N channel
FET that can sink 3mA or more of current to hold the voltage 2.8 Volts below the positive supply (when a load is trying to pull the common line positive). However, there is only
1p.A of source current, so COMMON may easily be tied to a
more negative voltage thus over-riding the internal reference.

Analog COMMON

TEST

This pin is included primarily to set the common mode
voltage for battery operation or for any system where the
input signals are floating with respect to the power supply.
The COMMON pin sets a voltage that is approximately 2.8
Volts more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about
6V. However, analog COMMON has some of the attributes
of a reference voltage. When the total supply voltage is
large enough to cause the zener to regulate « 7V), the
COMMON voltage will have a low voltage coefficient
(0.001 %1%), low output impedance ('" 150), and a temperature coefficient typically less than 80ppml"C.
The limitations of the on-Chip reference should also be
recognized, however. The reference temperature coefficient
(Te) can cause some degradation in performance. Temper-

The TEST pin serves two functions. It is coupled to the
internally generated digital supply through a 500n resistor.
Thus it can be used as the negative supply for externally
generated segment drivers such as decimal pOints or any
other presentation the user may want to include on the LCD
display. Figures 7 and 8 show such an application. No more
than a 1mA load should be applied.
The second function is a "lamp test." When TEST is
pulled high (to V+) all segments will be turned on and the
display should read - 1888. The TEST pin will sink about
10mA under these conditions.
Caution: In the lamp test mode, the segments have a
constant D-C voltage (no square-wave) and may burn
the LCD display if left in this mode for extended periods.

Differential Reference

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOrE.· All typics/ values havs bsBn chsracteriz6d but Sf6 not tested.

2-28

ICL7126

v+
1un

7126

INTEASIL
IT1750

7126

TO LCD
DECIMAL POINT

~--

BP't-----.-'-',

~.;?{

L..._.,._...I~;~:~~dPOFFL_:040~_",:
' -_ _ _ _ _ _ _ _ _...l '
1Mn

IN HI

INLO
AlZ
BUFF

y+

To"," ,
40

To pin 1
~

.P

TO BACK PLANE

2'

}TODIOPLAY

.,

TOBACK
PLANE

0339-'7

0339-,5

Figure 14: 7126 with Zener diode
reference.

Figure 16: 7126 measuring ratiometrlc
values of Quad Load Cell.

Since low T.C. zeners have breakdown voltages
- 6.8V, diode must be placed across the total
supply (10V). As in the case of Figure 13, IN LO
may be tied to COMMON.

The resistor values within the bridge are
determined by the desired sensitivity.

.

To pin ,

osc,

OSC'L.Jo--'V""'_....

Ole 3

To pin 1

'-'

!A~V"

OSC2
OSC3
TEST

REF HI
REF LO

C REF
C REF

PO.,,11

IOKn ~'OOKt>1 27K';'"
~1.2V(ICLIO.'1
1M!!

IN HI

• •01.uF

.

;..•. 'IOKn

}

G,

..,

C,

COMMON
IN HI
INLO

....... +5V

.~!

o.~~~

INTq=::::!~==y-[

+

IN

-

o.33.F

G,
;:

::: IV

____.:§

}
TO DISPLAY

G3
I'

TO BACK PUNE
21

:

TO DISPLAY -

G,

.liCon NPN

UPS 37040'
.Imll.,

~::~~~~----\-Q
~

/
• .1.

COMMON
INLO
AlZ
BUFF
INT
V-

REF LO[

Set Vref = 100.OmV

sOPF

ScM ,_tor ad....'

R!:s.:. q==...:JlF~!:\);/V----"'M~I;.,1r-~

4.

OSCt

0339-,8

Figure 17: 7126 used as a digital
centigrade thermometer.

GND ~TO BACK PLANE
2'

A silicon diode-connected transistor has a
temperature coefficient of about -2mVrC.
Calibration is achieved by placing the sensing
transistor in ice water and adjusting the zeroing
potentiometer for a 000.0 reading. The sensor
should then be placed In boiling water
and the scale-factor potentiometer
adjusted for 100.0 reading.

0339-,6

Figure 15: 7126 operated from
single + 5V supply.
An external reference must be used in this
application, since the voltage between V + and
v- is insufficient for correct operation of the
internal reference.

'Values depend on clock frequency. See Figures", , 2, 13.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not testsd.

2-32

.O~OIL

ICL7128

P
...N....
G

•

0339-19

Figure 18: Circuit for developing Underrange and Overrange
signals from 7126 outputs.

..

T....

OIC'
OICl
OICO
TIlT

. ,.

1CIIt . .1or . . . .

(YMI .. 1OOnIY 101 AC to 11111)

110Kll

... .0
C . .'
COIF

....

CC"'OH~~~
•N.o
AIZ

..",

.NT
y-

E

}TCNPLAY

--....:..
;;;.t,I1;;~ TO BACK PLANI
0339-20

Figure 19: AC to DC Converter with 7126. Test Is used as a common mode reference
level to ensure compatibility with most op-amps.

INTERSIL'S SOLE AND EXCWSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT BTATED IN THE WARRANTV ARTICLE OF THE CONDmON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCWDING THE IMPLIED WARRANTIES OF
MERCHANTABILlTV AND FITNESS FOR A PARTICULAR USE.
NOTE: An typIcs/ VBIuss have bssn chiJrBt:teIIzBd but IU8 not testBd.

2-33

.....= ICL7126

g APPLICATION NOTES
A016
A017
A018
A023
A032

A046
A052

7126 EVALUATION KIT
After purchasing a sample of the 7126, the majority of
users will want to build a simple voltmeter. The parts can
then be evaluated against the data sheet specifications,
and tried out in the intended application.
To facilitate evaluation of this unique circuit, Intersil is offering a kit which contains all the necessary components to
build a 3%-digit panel meter. With the ICL7126EV/KIT and
the small number of additional components required, an engineer or technician can have the system "up and running"
in about half an hour. The kit contains a circuit board, a
display (LCD), passive components, and miscellaneous
hardware.

"Selecting AID Converters", by David Fullagar.
"The Integrating AID Converter", by Lee Evans.
"Do's and Don'ts of Applying AID Converters", by
Peter Bradshaw and Skip Osgood.
"Low Cost Digital Panel Meter Designs", by David
Fullagar and Michael Dufort.
"Understanding the Auto-Zero and Common Mode
Performance of the ICL7106/7/9 Family", by Peter
Bradshaw.
"Building a Battery-Operated Auto Ranging DVM
with the ICL7106", by Larry Goff.
"Tips for Using Single-Chip 3%-Digit AID Converters", by Dan Watson.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: Ail typJca/ va/uss have been chlUllCtsriz6d but are not testBd.

2-34

D~DIl!...

ICL7129
4% Digit LCD Single-Chip
AID Converter

N

G

GENERAL DESCRIPTION

FEATURES

The IntersillCL7129 is a very high-performance 4%-digit
analog-to-digital converter that directly drives a multiplexed
liquid crystal display. This single-chip CMOS integrated circuit requires only a few passive components and a reference to operate. It is ideal for high-resolution hand-held digital multi meter applications.
The performance of the ICL7129 has not been equaled
before in a single-chip AID converter. The successive integration technique used in the ICL7129 results in accuracy
better than 0.005% of full-scale and resolution down to
10 /IV/count.
The ICL7129, drawing only 1mA from a 9V battery, is well
suited for battery powered instruments. Provision has been
made for the detection and indication of a "LOW/BATTERY" condition. Autoranging instruments can be made
with the ICL7129 which provides overrange and underrange
outputs and 10:1 range changing input. The ICL7129 instantly checks for continuity, giving both a visual indication
and a logic level output which can enable an external audible transducer. These features and the high performance of
the ICL7129 make it an extremely versatile and accurate
instrument-on-a-chip.

• ± 19,999 Count AID Converter Accurate to ± 4 Count
• 10,..V Resolution On 200mV Scale
• 110dB CMRR'
• Direct LCD Display Drive
• True Differential Input and Reference
• Low Power Consumption
• Decimal Point Drive Outputs
• Overrange and Underrange Outputs
• Low Battery Detection and Indication
.10:1 Range Change Input

ORDERING INFORMATION
Part
Number

Temperature

Package

ICL7129CPL

O'Cto +70'C

40-Pin Plastic

-

Evaluation Kit

ICL7129EV/KIT

UJW BATTERY CONTINUITY

-I.B.B.B.B
SEGMENT DRIVES

BACKPLANE
DRIVES

,...-...,

0SC1

DISPLAY
OUTPUT
LINES

OSC3

v·

....J
V- DONO

TOPYfEW

0340-1

Figure 1: Functional Diagram

0340-2

Figure 2: Pin Configuration
(outline dwg PL)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

301663-003

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have be8n characterized but are not tested.

2-35

•

: ICL7129

.......
s!

ABSOLUTE MAXIMUM RATINGS
Supply Voltages (V+ to V-) ....................... 15V
Reference Voltage (REF HI or REF La) ........ V+ to VInput Voltage (Note 1)
(IN HI or IN La) ........................... V+ to VVDISP ............................ DGND -0.3V to V+
Digital Input Pins
1,2,19,20,21,22,27,
37,38,39,40 .......................... DGND to V+

Power Dissipation (Note 2)
Plastic package ............................. 800mW
Operating Temperature ................... O'C to + 70'C
Storage Temperature ................ - 65'C to + 150'C
Lead Temperature (Soldering, 10sec) ............. 300'C

Note 1: Input voltages may exceed the supply voltages provided that input current is limited to ± 400p.A. Currents above this value may result in invalid display
readings but will not destroy the device if limited to ± 1rnA.

Note 2: Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.

NOTE: Stresses above those listed under "Abso/ute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
v- to v+ =9V, VREF= 1.00V. TA = +25'C, fCLK= 120kHz, unless otherwise noted.
Characteristics

Test Conditions

Zero Input Reading

VIN=OV
200mVScaie

Zero Reading Drift

VIN=OV
O'C_4--.:'~9 YOISP
5k >"'e---I!.1'

' - - -.....-

ICL7129

36 DGND

.....-;YOISP

ICL7129

DGND

75k

'--_ _ _~------... 23

-+ 23

L--_ _ _ _

Y-

Y-

0340-14

Figure 14: Two Methods for Temperature Compensating the Liquid Crystal Display
optimum integrator swing at full-scale. A large integrator
swing will reduce the effect of noise sources in the comparator but will affect rollover error if the swing gets too close
to the positive rail (:::: 0.7V). This gives an optimum swing of
:::: 2.5V at full-scale. For a 150kO integrating resistor and 2
conversions per second the value is 0.10,."F. For different
conversion rates, the value will change in inverse proportion. A second requirement for good linearity is that the capacitor have low dielectric absorption. Polypropylene caps
give good performance at a reasonable price. Finally the foil
side of the cap should be connected to the integrator output
to shield against pick-up.
The only requirement for the reference cap is that it be
low leakage. In order to reduce the effects of stray capacitance, a 1.0,."F value is recommended.

DISPLAY TEMPERATURE
COMPENSATION
For most applications an adequate display can be obtained by connecting VOISP (pin 19) to DGND (pin 36). In
applications where a wide temperature range is encountered, the voltage drive levels for some triplexed liquid crystal displays may need to vary with temperature in order to
maintain good display contrast and viewing angle. The
amount of temperature compensation will depend upon the
type of liquid crystal used. Display manufacturers can supply the temperature compensation requirements for their
displays. Figure 14 shows two circuits that can be adjusted
to give a temperature compensation of :::: + 1OmVI'C between V+ and VOISP. The diode between DGND and VOISP
should have a low turn-on voltage to assure that no forward
current is injected into the chip if VOISP is more negative
than DGND.

CLOCK OSCILLATOR
The ICL7129 achieves its digital range changing by integrating the input signal for 1000 clock pulses (2,000 oscillator cycles) on the 2V scale and 10,000 clock pulses on the
200mV scale. To achieve complete rejection of 60Hz on
both scales, an oscillator frequency of 120kHz is required,
giving two conversions per second.
In low resolution applications, where the converter uses
only 31f2 digits and 100,."V resolution, an R-C type oscillator
is adequate. In this application a C of 51 pF is recommended
and the resistor value selected from fosc=0.45/RC. However, when the converter is used to its full potential (41f2
digits and 10,."V resolution) a crystal oscillator is recom-

COMPONENT SELECTION
There are only three passive components around the
ICL7129 that need special consideration in selection. They
are the reference capacitor, integrator resistor, and integrator capacitor. There is no auto-zero capacitor like that found
in earlier integrating AID converter designs.
The integrating resistor is selected to be high enough to
assure good current linearity from the buffer amplifier and
integrator and low enough that PC board leakage is not a
problem. A value of 150kO should be optimum for most
applications. The integrator capacitor is selected to give an

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but 8r6 not tested.

2-44

Ij]D~DIl.

ICL7129

n

I'"

...
.....

mended to prevent the noise from increasing as the input
signal is increased due to frequency jitter of the R-C oscillator. Both R-C and crystal oscillator circuits are shown in
Figure 15.

N
0

+5Y

24
y+

I

I

REF HI

I

I

I

ICL7129

I

_ _ _ ..JI

I

L_

REF LO
ICL7129

2

DGND

COM
IN HI

I

I
I

ICL7129

I
I

___ J

L_

IN LO

I
I

ICL8089
35
28
33

+
YIN

32

Y-

I

23

2
-5Y

5pF

120kHz

0340-16

10pF

Figure 16: Powering the ICL7129 from
- 5V Power Supplies

V+o-1 ~Ul--+-l ~ V+

+ 5V and

When a battery voltage between 3.8V and 7V is desired
for operation, a voltage doubling circuit should be used to
bring the voltage on the ICL7129 up to a level within the
power supply voltage range. This operating mode is shown
in Figure 17.

0340-15

Figure 15: RC and Crystal Oscillator Circuits

POWERING THE ICL7129
The ICL7129 may be operated as a battery powered
hand-held instrument or integrated into larger systems that
have more sophisticated power supplies. Figures 16, 17,
and 18 show various powering modes that may be used
with the ICL7129.
The standard supply connection using a 9V battery is
shown in Figure 3.
The power connection for systems with +5V and -5V
supplies available is shown in Figure 16. Notice that measurements are with respect to ground. COMMON is also
tied to INLO to remove any common-mode voltage swing
on the integrator amplifier inputs.
It is important to notice that in Figure 16, digital ground of
the ICL7129 (DGND pin 36) is not directly connected to
power supply ground. DGND is set internally to approximately 5V less than the V + terminal and is not intended to
be used as a power input pin. It may be used as the ground
reference for external logic, as shown in Figure 7 and 8. In
Figure 7, DGND is used as the negative supply rail for external logic provided that the supply current for the external
logic does not cause excessive loading on DGND. The
DGND output can be buffered as shown in Figure 8. Here,
the logic supply current is shunted away from the ICL7129
keeping the load on DGND low. This treatment of the
DGND output is necessary to insure compatibility when the
external logic is used to interface directly with the logic inputs and outputs of the ICL7129.

+
:

3.8VT08V

I"'-+~p-'_.--o+

+

~
10~F

ICL7_

23

0340-17

Figure 17: Powering the ICL7129
from a 3_8V to 6V Battery

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

2-45

•

: ICL7129
.......

d
-

VOLTAGE REFERENCES

Again measurements are made with respect to COMMON
since the entire system is flojiting. Voltage doubling is accomplished by using an ICL7660 CMOS voltage converter
and two inexpensive electrolytic capacitors. The same principle applies in Figure 18 where the ICL7129 is being used
in a system with only a single + 5V power supply. Here
measurements are made with respect to power supply
ground.
A single polarity power supply can be used to power the
ICL7129 in applications where battery operation is not appropriate or convenient only if the power supply is isolated
from system ground. Measurements must be made with respect to COMMON or some other voltage within its input
common-mode range.

The COMMON output of the ICL7129 has a temperature
coefficient of ±80ppml"C typically. This voltage is only suitable as a reference voltage for applications where ambient
temperature variations are expected to I:)e minimal. When
the ICl7129 is used in most environments, other voltage
references should be considered. The diagram in Figures 3
and 18 show the ICL8069 1.2V band-gap voltage source
used as the reference for the ICL7129, and the COMMON
output as its pre-regulator. The reference voltage for the
ICL7129 is set to 1.000V for both 2V and 200mV full-scale
operation.

+5Y'o----1~--~--------_t------_,

ICL8089

0.1 ; 7V), the COMMON voltage will have a low voltage coefficient (0.001 %/
%), low output impedance (""35n), and a temperature coefficient typically less than 150ppmrC.

DE-INTEGRATE PHASE
The next phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-50

ICL7136
V'

V'

V'REF
I-~
HI
REFLO
ICL7138

:

f+

V'

'~8.8VOLT
~

'--

1.2 VOLT

r-

ICL7136

ZENER

REFERENCE

l~

REF HI
REFLO

- ....

1-+:

: ,

~ (INTERSlL

j ~

ICL8088)

1---<"""-

COMMON I - -

V-

(a)

(b)
0343-7

0343-8

Figure 6: Using an External Reference
The limitations of the on-chip reference should also be
recognized, however. The reference temperature coefficient
(TC) can cause some degradation in performance. Temperature changes of 2°C to 8°C, typical for instruments, can
give a scale factor error of a count or more. Also, the COMMON voltage will have a poor voltage coefficient when the
total supply voltage is less than that which will cause the
zener to regulate «7V). These problems are eliminated if
an external reference is used, as shown in Figure 6.
Analog COMMON is also used as the input low return
during auto-zero and de-integrate. If IN LO is different from
analog COMMON, a common-mode voltage exists in the
system and is taken care of by the excellent CMRR of the
converter. However, in some applications IN LO will be set
at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied
to the same point, thus removing the common-mode voltage from the converter. The same holds true for the reference voltage. If the reference can be conveniently referred
to analog COMMON, it should be since this removes the
common-mode voltage from the reference system.
Within the IC, analog COMMON is tied to an N channel
FET which can sink 3mA or more of current to hold the
voltage 3.0V below the positive supply (when a load is trying
to pull the common line positive). However, there is only
1p.A of source current, so COMMON may easily be tied to a
more negative voltage, thus overriding the internal reference.

TEST
The TEST pin serves two functions. It is coupled to the
internally generated digital supply through a 5000 resistor.
Thus, it can be used as the negative supply for external
segment drivers such as for decimal points or any other
presentation the user may want to include on the LCD display. Figures 7 and 8 show such an application. No more
than almA load should be applied.
The second function is a "lamp test." When TEST is
pulled high (to V+) all segments will be turned on and the
display should read -1888. The TEST pin will sink about
10mA under these conditions.
Caution: In the lamp test mode, the segments have a
constant DC voltage (no square-wave). This may burn
the LCD display If maintained for extended periods.

v'

_

.,1---_.-i--\1"""

-

to LCD

DlClMAI.
POINT

DECIMAl.
POINTS

,
L_
-_I

L-____________

..I

~a.

0343-10

Figure 8: Exclusive "OR" Gate for
Decimal Point Drive
V'

lMn

DETAILED DESCRIPTION
ICL7138

BP' "2"'1+-11+--

TESTh3""7+~-

(Digital Section)

TO LCD
DECIMAL POINT

Figure 9 shows the digital section for the 7136, An internal digital ground is generated from a 6V Zener diode and a
large P channel source follower, This supply is made stiff to
absorb the relatively large capacitive currents when the
backplane (BP) voltage is switched. The BP frequency is
the clock frequency divided by 800, For three readings/second this is a 60Hz square-wave with a nominal amplitude of
5V, The segments are driven at the same frequency and

:~J7~SIL
TO LCD
BACKPLANE

0343-9

Figure 7: Simple Inverter for Fixed
Decimal Point
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPREss, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typical valu6s have b8tm charact6rizsd but sre not tested.

2-51

•

.= ICL7136
too

s;!

DISPLAY FONT

0:23'-156189
-----------.--.-~-------·---------------·-+·-----i·l~~+~-·--~I~~ii~+··-~4+~~+~-··--~e~~~-

-----""'--=4> v------------------------e~;----,OSC3

Ole

0343-11

Figure 9: Digital Section
amplitude and are in phase with BP when OFF, but out of
phase when ON. In all cases negligible DC voltage exists
across the segments. The polarity indication is "ON" for
negative analog inputs. If IN La and IN HI are reversed, this
indication can be reversed also, if desired.

System Timing
L

Figure 10 shows the clock oscillator provided in the 7136.
Three basic clocking arrangements can be used:
1.
An external oscillator connected to pin 40.
2.
A crystal between pins 39 and 40.
3.
An RC oscillator using all three pins.
The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the

oJ

0343-12

Figure 10: Clock Circuits

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typIcsl vslues have beBn chstacf6rizsd but 11M not tsstsd.

2·52

ICL7136
four convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (0 counts to 2000 counts),
zero integrator (11 counts to 140 counts") and auto-zero
(910 counts to 2900 counts). For signals less than fullscale, auto-zero gets the unused portion of reference de-integrate and zero integrator. This makes a complete measure cycle of 4000 (16,000 clock pulses) independent of
input voltage. For three readings/second, an oscillator frequency of 48kHz would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of the 60Hz period. Oscillator frequencies of 60kHz, 48kHz, 40kHz, 33YskHz, etc.
should be selected. For 50Hz rejection, oscillator frequencies of 66%kHz, 50kHz, 40kHz, etc. would be suitable. Note
that 40kHz (2.5 readings/second) will reject both 50Hz and
60Hz (also 400Hz and 440Hz). See also A052.

Oscillator Components
For all ranges of frequency a 50pF capacitor is recommended and the resistor is selected from the approximate
equation f- 0.45/RC. For 48kHz clock (3 readings/second), R=180kO, for 16kHz, R=560kO.

Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is VIN = 2VREF. Thus, for the 200.0mV and
2.000V scale, VREF should equal100.0mV and 1.000V, respectively. However, in many applications where the AID is
connected to a transducer, there will exist a scale factor
other than unity between the input voltage and the digital
reading. For instance, in a weighing system, the designer
might like to have a full-scale reading when the voltage from
the transducer is 0.682V. Instead of dividing the input down
to 200.0mV, the designer should use the input voltage directly and select VREF = 0.341V. A suitable value for the
integrating resistor would be 330kO. This makes the system
slightly quieter and also avoids the necessity of a divider
network on the input. Another advantage of this system occurs when a digital reading of zero is desired for VIN#O.
Temperature and weighing systems with a variable tare are
examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and
COMMON and the variable (or fixed) offset voltage between
COMMON and IN LO.

COMPONENT VALUE SELECTION
(See also A052)

Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 6/kA of quiescent current. They can supply - 1/kA of drive current with negligible non-linearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full-scale, 1.8MO is near optimum,
and similarly 180kO for a 200.0mV scale.

TYPICAL APPLICATIONS

Integrating Capacitor

The 7136 may be used in a wide variety of configurations.
The circuits which follow show some of the possibilities, and
serve to illustrate the exceptional versatility of these AID
converters.

The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing (approx. 0.3V from either
supply). When the analog COMMON is used as a reference,
a nominal ± 2V full-scale integrator swing is fine. For three
readings/second (48kHz clock) nominal values for CINT are
0.047/kF, for 1 reading/second (16kHz) 0.15/kF. Of course,
if different oscillator frequencies are used, these values
should be changed in inverse proportion to maintain the
same output swing.
The integrating capacitor should have low dielectric absorption to prevent roll-over errors. While other types may
be adequate for this application, polypropylene capacitors
give undetectable errors at reasonable cost.

40
~

TOI)I"'-

OSC 1

18Ok0

05C2
0$e3
TEST
REF HI
REF LQ
C REF
C REF
COMMON
INHI
IN LO

Auto-Zero Capacitor

Set Yr&1 '" lOG.OmY

~O.'"F

101en

221lk!l
1M!}

::;t 0.01,11F
0.47pF

A·Z

1801<0

BUFF

The size of the auto-zero capacitor has some influence
on the noise of the system. For 200mV full-scale where
noise is very important, a 0.47/kF capacitor is recommended. The ZI phase allows a large auto-zero capacitor to be
used without causing the hysteresis or overrange hangover
problems that can occur with the ICL7126 or ICL7106 (see
A032).

/

SO.F

INT

0.047"F

y-

-=

::r

..

IN

9V

G,
C,
A, UTODISPLAY

8.
G,

TO BACKPLANE
21

Reference Capacitor

0343-13

Figure 11: 7136 Using the Internal
Reference

A 0.1/kF capacitor gives good results in most applications. However, where a large common-mode voltage exists
(Le., the REF LO pin is not at analog COMMON) and a
200mV scale is used, a larger value is required to prevent
rOil-over error. Generally, 1.0/kF will hold the roll-over error
to 0.5 count in this instance.

Values shown are for 200.0mV full-scale,
3 readings/sec, floating supply voltage
(9V battery).

"'After an overranged conversion of more than 2060 counts, the zero integrater phase will last 740 counts, and auto-zero will last .260 counts.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charaotedzed but are not tested.

2-53

fJI

= ICL7136
......

.D~DIl.

...

S:!
'-"

To". 1 -

40
OSC 1
OSC2
OSC 3
TEST
REF HI
REF LO

Set Vref '" l00.OmY

SOpF

,/

201<0

200'0

C REF

V+

REF HI
RlfLO
CREF
CREF
COMMON
IN HI
INLO
A.z

,
IN

*0.01,F
O.47pF
180kO

BUFF

'.~0.15 .. F

INT
V-

§
"

V-

\...1
101<0

- -'1Mn

'.j

1M11

+
IN

-

.33/o1F
1~
'.': v-

..A

·5Y

ruv

___ ~G.01pF

.NT

C,

Se' yret =tOO.OnIY

:=!0o...,!

aUFF

G,

G,
8P

'v-

sCj"

TEIT

""'.2V (IClao••)
1M!1

OBC1
OBC'

08C.

27~~

, TV

COMMON
INHI
IN lO
A·Z

~

...

~O.lJ.'

CREF

.

To ... 1

560Icll

V}TO DISPLAY

-5Y

0,
C,

..,

D-TO BACKPLANE
21

}TOD.SPLAY

.,

0,
.P

>---

TO BACKPlANE

0343-14

Figure 12: 7136 with an External
Band-Gap Reference (1.2V Type)

0343-16

Figure 14: 7136 with Zener Diode
Reference

IN LO is tied to COMMON, thus establishing the
correct common-mode voltage. COMMON acts
as a pre-regulator for the reference. Values
shown are for 1 reading/sec.

.....,

-

To pin 1
40

oaCl
OSC2

osc.
TEST
REFHI
REFLO

50pf

CREF
CREF

~O.lJjF

To pin 1

/

COMMON

-

1MIl

.II.01F

INLO
A,z
aUFF
INT
y-

.....,

Se. Vref '" 1.000v

250Idl

IN HI

Since low TC zeners have breakdown voltages
~ 6.8V, diode must be placed across the total
supply (10V). As in the case of Figure 13, IN LO
may be tied to COMMON.

y+

..,..,

.

Set v .... :: l00.amV

/

50pf

REF HI
REFLO
CREF
CAEF

+
IN

COMMON

0°.

1."

1MU

INLO
A,z
aUFF

".~

y-

}TODISPlAY

.',,-

}

C,

21

G,
GND

+
IN

-

;':,18OkO

.,

t--- TO BACKPlANE

.0.01 ..'

0.'7 F

.NT
VG,

C,

+SY

T

20Idl ..., 1001dl 27110
"'l1 •• Y('C~

IN HI

1.IMU

G,

BP

••

OSC 3
TEST

0.10,.F ..

0.047/o1F

OSCl
OSC2

:

TO DISPLAY -

t---==-- TO BACKPlANE
21

0343-15

Figure 13: Recommended Component
Values for 2.000V Full-Scale,
3 Readings/Sec

0343-17

Figure 15: 7136 Operated from
Single + 5V Supply

For 1 reading/sec, change CINT, Rose to values
of Figure 12.

An external reference must be used in this
application, since the voltage between V+ and
V- is insufficient for correct operation of the
internal reference.

'Values depend on clock frequency. See Figures 11, 12, 13.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

2-54

ICL7136

.

~T~opn~1r--------------------9Y'
OSC1
asC2
OSCI
TEST
REf HI
RIFLO
C REF

C NtF
COMMON
INHI
INLO

G.47

A-Z

""'T

BUFF
lilT

y-

O,

C,

...'"

}TO OISPLAY

0,

21

TO
BACKPLANE

0343-18

Figure 16: 7136 Measuring Ratiometric Values of Quad Load Cell
The resistor values within the bridge are determined by the desired sensitivity.

To pin 1

OSCl

••

OSC 2

OSC 3 D----il------'

Sc••• factor adJu.t

A~=~ D---SOp---,,=,,-,. /

~Ilcon

NPH

MPS 3704 Of

1M!1

CRE'

}S
_or

R"LO[}---f=~Atv-~0Vv-~

••••

C REF

COMMON~~~~~===t~~:;.~~-t~
INHI[
INLO~~~~~~~
_ _ _ _~~
A.Z t
0.47 F
aUFF Lt----".IV\i38Ok=O,..

::: IV

INTq==::::::~====~
Y-[
0,
C,

____j

}TO DISPLAY

'"

0,

BP

TO BACKPLANE

21

0343-19

Figure 17: 7136 used as a Digital Centigrade Thermometer

rc.

A silicon diode-connected transistor has a temperature coefficient of about - 2mV
Calibration is
achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0
reading. The sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for
a 100.0 reading. See ICL807% and AD590 data sheets for alternative circuits.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OA STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

2-55

•

=

....... ICL7136

...
~

v·

-

va
0'
C'

..,,

To

Vee

F1
G,

I'
02
C2
B2

AI
PI

12
D3

~

......
••

Uiii.nte

40
GeC'

DlCa

_HI

OSC3

naT

RIFLO
CRI'
CRII'
COMMON
INHI

To_
GNO

.IHLO
AoZ

INT

V-

0.

...

PI

C3

POI.

.P

CI3

20
C-

or 74C10

CD4077

0343-20

Figure 18: Circuit for Developing Underrange and Overrange Signals from 7136 Outputs

To ..... '

loll. tRtor adJUit
(Vrel '" 100mV tor AC to RMI)

40

'OOId)

"CIN

0343-21

Figure 19: AC to DC Converter with 7136
Test is used as a common-mode reference level to ensure compatibility with most op amps.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR

use.

NOTE: All typical values havs been characterized bul are not tested.

2-56

ICL7136
APPLICATION NOTES

7136 EVALUATION KIT

A016
A017
A018

After purchasing a sample of the 7136, the majority of
users will want to build a simple voltmeter. The parts can
then be evaluated against the data sheet specifications,
and tried out in the intended application.
To facilitate evaluation of this unique circuit, Intersil is offering a kit which contains all the necessary components to
build a 3%-digit panel meter. With the ICL7136EV/Kit and
the small number of additional components required, an engineer or technician can have the system "up and running"
in about half an hour. The kit contains a circuit board, a
display (LCD), passive components, and miscellaneous
hardware.

A023
A032

A046
A047
A052

"Selecting AID Converters," by David Fullagar.
"The Integrating AID Converter," by Lee Evans.
"Do's and Dont's of Applying AID Converters," by
Peter Bradshaw and Skip Osgood.
"Low Cost Digital Panel Meter Designs," by David
Fullagar and Michael Dufort.
"Understanding the Auto-Zero and Common-Mode
Behavior of the ICL71 06/7/9 Family," by Peter
Bradshaw.
"Building a Battery-Operated Auto Ranging DVM
with the ICL7106," by Larry Goff.
"Games People Play with Intersil's AID
Converters," edited by Peter Bradshaw.
"Tips for Using Single-Chip 3%-Digit AID Converters," by Dan Watson.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have ~ characterized but are not tested.

2-57

..

::; ICL7137
!:i 3%-Digit LED Low Power
g Single-Chip AID Converter
GENERAL DESCRIPTION

FEATURES

The Intersil ICl7137 is a high performance, very low power 3Y.-digit AID converter. All the necessary active devices
are contained on a single CMOS IC, including seven-segment decoders, display drivers, reference, and clock. The
7137 is designed to interface with a light emitting diode
(lED) display. The supply current (exclusive of display) is
under 200",A, ideally suited for battery operation.
The 7137 brings together an unprecedented combination
of high accuracy, versatility, and true economy. The device
features auto-zero to less than 1O",V, zero drift of less than
input bias current of 10pA max., and rollover error
1",V
of less than one count. The versatility of true differential
input and reference is useful in all systems, but gives the
designer an uncommon advantage when measuring load
cells, strain gauges and other bridge-type transducers. And
finally the true economy of the ICl7137 allows a high performance panel meter to be built with the addition of only 10
passive components and a display.
The ICl7137 is an improved version of the ICl71 07, eliminating the overrange hangover and hysteresis effects, and
should be used in its place in all applications, changing only
the passive component values.

• First-Reading Recovery From Overrange allows
Immediate "OHMS" Measurement
• Guaranteed Zero Reading for OV Input
• True Polarity at Zero for Precise Null Detection
• lpA Typical Input Current
• True Differential Input and Reference
• Direct LED Display Drive - No External Components
Required
• Pin Compatible With The ICL7107
• Low Noise -15",Vp-p Without Hysteresis or
Overrange Hangover
• On-Chip Clock and Reference
.,Improved Rejection of Voltage On COMMON Pin
• No Additional Active Circuits Required
• Evaluation Kit Available ICL7137EV/Kit

rc,

ORDERING INFORMATION*
Part Number

Temperature Range

ICl7137CPl

O°C to

+ 70°C

ICl7137RCPl

O°C to

+ 70°C

Package
40-Pin Plastic
40-Pin Plastic

ICl7137EVIKIT

EVALUATION KIT

v' ,-no--.:-r-'""!1!t-, osc 1

;;!:

eo"

TO
DIGITAL
SECTION

jNHI9"t~i}-7V), the COMMON voltage will have a low voltage coefficient (0.001 %/
%), low output impedance( "" 350), and a temperature coefficient typically less than 150ppm1'C.
The limitations of the on-chip reference should also be
recognized, however. The reference temperature coefficient
(TC) can cause some degradation in performance. Temperature changes of 2·C to S·C, typical for instruments, can
give a scale factor error of a count or more. Also, the COMMON voltage will have a poor voltage coefficient when the
total supply voltage is less than that which will cause the
zener to regulate «7V). These problems are eliminated if
an external reference is used, as shown in Figure 6.

DE·INTEGRATE PHASE
The next phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the
capacitor will be connected with the correct polarity to
cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the
input signal. Specifically; the digital reading displayed is
1000(VINiVREF)'

ZERO INTEGRATOR PHASE
The final phase is zero integrator. First, input low is shorted to analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Finally, a feedback loop is
closed around the system to input high to cause the integrator output to return to zero. Under normal conditions, this
phase lasts for between 11 to 140 clock pulses, but after a
"heavy" overrange conversion, it is extended to 740 clock
pulses.

V REF_>HI

Differential Input

REF LO~:
~:

The input can accept differential voltages anywhere within the common-mode range of the input amplifier; or specifically from 0.5V below the positive supply to 1.0V above the
negative supply. In this range the system has a CMRR of
90dS typical. However, since the integrator also swings with
the common-mode voltage, care must be exercised to assure the integrator output does not saturate. A worst case
condition would be a large positive common-mode voltage
with a near full-scale negative differential input voltage. The
negative input signal drives the integrator positive when
most of its swing has been used up by the positive common-mode voltage. For these critical applications the integrator swing can be reduced to less than the recommended
2V full-scale swing with little loss of accuracy. The integrator output can swing within 0.3V of either supply without
loss of linearity.

ICL7137

". '"' 8.8 VOLT
.~ ZENER

-

l~

(al
0344-6

v+
v+
ICL7137

Differential Reference

--'

REF HI

The reference voltage can be generated anywhere within
the power supply voltage of the converter. The main source
of common-mode error is a roll-over voltage caused by the
reference capacitance losing or gaining charge to stray capacity on its nodes. If there is a large common-mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but
lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for
(+ ) or (-) input voltage will give a roll-over error. However,
by selecting the reference capacitor large enough in comparison to the stray capacitance, this error can be held to
less than 0.5 count for the worst case condition (see Component Value Selection).

f..

1.2 VOLT
REFERENCE

-+! '.4 .. ~=L

REF LO --< ..........

COMMON-

(b)
0344-7

Figure 6: Using an External Reference
Analog COMMON is also used as the input low return
during auto-zero and de-integrate. If IN LO is different from
analog COMMON, a common-mode voltage exists in the
system and is taken care of by the excellent CMRR of the
converter. However, in some applications IN LO will be set
at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied
to the same pOint, thus removing the common-mode v')ltage from the converter. The same holds true for the reference voltage. If the reference can be conveniently referred
to analog COMMON, it should be since this removes the
common-mode voltage from the reference system.

Analog Common
This pin is included primarily to set the common-mode
voltage for battery operation or for any system where the
input signals are floating with respect to the power supply.
The COMMON pin sets a voltage that is approximately 3.0V
more negative than the positive supply. This is selected to
give a minimum end-of-life battery voltage of about 6V.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY ANO FITNESS FOR A PARTICULAR USE.

NOTE: AU typical values hsvs bsen charsctetized but Sf6 not tested.

2-61

p
.......

Col
....

::; ICL7137

...
i
~

Within the IC, analog COMMON is tied to an N channel
FET which can sink 100Jl-A or more of current to hold the
voltage 3.0V below the positive supply (when a load is trying
to pull the common line positive). However, there is only
1fJ.A of source current, so CO!VIMON may easily be tied to a
more negative voltage, thus· overriding the intemal reference.

TEST
The TEST pin is coupled to the internal digital supply
through a 5000 resistor, and functions as a "lamp test."
When TEST is pulled high (to V+) all segments will be
turned on and the display should read - 1888. The TEST
pin will sink about 10mA under these conditions.

DISPLAY FONT

a

:·2 3 '-ISS -: 8 9

--------,I
I
I
I

I

I
I
I
I

I

soo H

,
I

'--_-+::-'-~-___rc::--------------+--=.:2.~'
DIDITAl.
38
38
GROUND

--------1---------------------------I

'Three Inverters.
One inverter shown for clarity.

osc:,

_.J

osc 31
'--_ _ _ _....._-I~
OBC 2

0344-8

Figure 7: Digital Section

DETAILED DESCRIPTION

(Digital Section)
Figure 7 shows the digital section for the 7137. The segments are driven at 8mA, suitable for instrument size common anode' LED displays. Since the 1000 output (pin 19)
must sink current from two LED segments, it has twice the
drive capability or 16mA. The polarity indication is "ON" for
negative analog inputs. If IN LO and IN HI are reversed, this
indication can be reversed also, if desired.
Figure 8 shows a method of increasing the output drive
current, using four DM7407 Hex Buffers. Each buffer is capable of sinking 40mA.

....

0344-9

Figure 8: Display Buffering for
Increased Drive Current

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGAnON WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANlY ARTICLE OF THE CONDITION OF SALE.
THE WAARANlY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANnES OF
MERCHANTABILIlY AND FITNESS FOR A PARnCULAR USE.

NOTE: AN typIcsJ VBIu8s haV6 bB8n charsctetIz9d but aM not f6sted.

2-62

ICL7137
supply). When the analog COMMON is used as a reference,
a nominal ± 2V full-scale integrator swing is fine. For three
readings/second (48kHz clock) nominal values for CINT are
O.047!,-F, for 1 reading/second (16kHz) O.15!,-F. Of course,
if different oscillator frequencies are used, these values
should be changed in inverse proportion to maintain the
same output swing.
The integrating capaCitor should have low dielectric absorption to prevent roll-over errors. While other types may
be adequate for this application, polypropylene capaCitors
give undetectable errors at reasonable cost.

System Timing
Figure 9 shows the clock oscillator provided in the 7137.
Three basic clocking arrangements can be used:
1.
An external oscillator connected to pin 40.
2.
A crystal between pins 39 and 40.
3.
An RC oscillator using all three pins.

Auto-Zero Capacitor
L

The size of the auto-zero capaCitor has some influence
on the noise of the system. For 200mV full-scale where
noise is very important, a 0.47!,-F capaCitor is recommended. The 21 phase allows a large auto-zero capacitor to be
used without causing the hysteresis or overrange hangover
problems that can occur with the ICL7107 or ICL7117 (See
Application Note A032).

oJ

Reference Capacitor

0344-10

Figure 9: Clock Circuits

A 0.1!,-F capacitor gives good results in most applications. However, where a large common-mode voltage exists
(Le., the REF LO pin is not at analog COMMON) and a
200mV scale is used, a larger value is required to prevent
roll-over error. Generally, 1.0!,-F will hold the roll-over error
to 0.5 count in this instance.

The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
four convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (0 counts to 2000 counts),
zero integrator (11 counts to 140 counts·) and auto-zero
(910 counts to 2900 counts). For Signals less than fullscale, auto-zero gets the unused portion of reference de-integrate and zero integrator. This makes a complete measure cycle of 4000 (16,000 clock pulses) independent of
input voltage. For three readings/second, an oscillator frequency of 48kHz would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of the 60Hz period. Oscillator frequencies of 60kHz, 48kHz, 40kHz, 33%kHz, etc.
should be selected. For 50Hz rejection, oscillator frequencies of 66%kHz, 50kHz, 40kHz, etc. would be suitable. Note
that 40kHz (2.5 readings/ second) will reject both 50Hz and
60Hz (also 400Hz and 440Hz.) See also A052.
• After an overranged conversion of more than 2060 counts, the zero

Oscillator Components
For all ranges of frequency a 50pF capaCitor is recommended and the resistor is selected from the approximate
equation f '" 0.45/RC. For 48kHz clock (3 readings/second), R= 180kO, while for 16kHz (1 reading/sec),
R=560kO.

Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is: VIN = 2VREF. Thus, for the 200.0mV and
2,000V scale, VREF should equal 100.0mV and 1.000V, respectively. However, in many applications where the AID is
connected to a transducer, there will exist a scale factor
other than unity between the input voltage and the digital
reading. For instance, in a weighing system, the deSigner
might like to have a full-scale reading when the voltage from
the transducer is 0.682V. Instead of dividing the input down
to 200.0mV, the designer should use the input voltage directly and select VREF=0.341V. A suitable value for the
integrating resistor would be 330kO. This makes the system
slightly quieter and also avoids the necessity of a divider
network on the input. Another advantage of this system occurs when a digital reading of zero is desired for VIN*O.
Temperature and weighing systems with a variable tare are
examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and
COMMON and the variable (or fixed) offset voltage between
COMMON and IN LO.

inte~

grator phase will last 740 counts, and auto-zero will last 260 counts.

COMPONENT VALUE SELECTION
(See Application Note A052)

Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 6!,-A of quiescent current. They can supply -1!,-A of drive current with negligible non-linearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full-scale, L8MO is near optimum,
and similarly 180kO for a 200.0mV scale.

TYPICAL APPLICATIONS

Integrating CapaCitor

The 7137 may be used in a wide variety of configurations.
The circuits which follow show some of the possibilities, and
serve to illustrate the exceptional versatility of these AID
converters.

The integrating capaCitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing (approx. O.3V from either

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-63

•

........ ICL7137

I.IlD~DI!..

~

~

~

..

ose.

To .... -

08C3
TEST
REFH,

set v.... '" too.amv

~

/

DO""I

IN LO

0.471"

I.Z

IUF'
INT

0.047.1o!'

V-

G,
C,
A,
G,
OND

tUH

T

.0.0'",

IN

=:3: 0.1,.,

-5V

IMlI
IN

;'·,1.8MIl

INT
V-

,,

V·
240kD

'50100

_90.01/1'

A·Z

I

/

0.471"

BUFF

I
I

}TODISPLAY

,
t

COMMON
INH,
INLO

-

I
I
I
I

... v...r = 1.000V

.0;..

TEST
REF HI
REFLO
C REF
CREF

22OkO

'01<0

.-

IN HI

.-

ose 3
+5V

COMMON

OSCI

ose.

RIFLO
CREF
CAEF

..

To pin 1

.-,

....

OSC2

O.047J,AF

V-

G,
C,
A,

OV

•• 7

G,
OND

}TO DISPLAY

.,

OV

0344-11

Figure 10: 7137 Using the Internal
Reference.

0344-13

Figure 12: Recommended Component Values for
2.000V Full-Scale,
3 Readings/Sec.

Values shown are for 200.0mV full-scale, 3
readings/sec. IN LO may be tied to either
COMMON for inputs floating with respect to
supplies, or GND for single ended inputs. (See
discussion under Analog COMMON.)

'-" OSC 1

For 1 reading/sec, change C'NT, Rose to values
of Figure 11.

..

~

Topln",-

40

OSC'
580kD

....

08C2
08e3
TEST
REF HI
REF LO

Set ~"f

2OkO

C REF

,

"".'V"CLI".)

COMMON

1Mll

IN HI

IPO.O'.I"

IN LO
A·Z

OSC.
TEST

.71<0

T

R£FLO
CRE'

V+

CA.F

.

INLO

7.

A-Z

a_

180kO

INT

INT

V-

O.15~F

V-

Itt

v,.. ""

I
100.GmV

\v!

Do"I"

COMMON
IN HI

IN

O.47I'F_1l

BUFF

....

_HI

100.OmY

200kD

.,-

po...

C REF

i

OSC2

'0lI0

.-

J1MIl

tMn

.0.0'1"

'5V

';j lUV

.

IN

-

-5V

Ih

G,

C,

C,
}TODISPLAY

A,
0,
aND

}TDDISPLAY

Ao
Cb
OND

--, - " " - - - 0 OV

7'

0344-12

••

aOV

0344-14

Figure 11: 7137 with an External Band-Gap
Reference (1.2V Type).

Figure 13: 7137 with Zener Diode Reference.
Since low TC zeners have breakdown voltages
- 6.aV, diode must be placed across the total
supply (10V). As in the case of Figure 11, IN LO
may be tied to COMMON.

IN LO is tied to COMMON, thus establishing the
correct common-mode voltage. COMMON acts
as a pre-regulator for the reference. Values
shown are for 1 reading/sec.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not test9d.

2-64

ICL7137

'-'

Toptn 1
40

oee.
Oac2
oeeo

.

-

TES'
REF HI
RIFLO
CREF
CREF

~O.'~

COMMON
IN HI

....

INLO

• 02
BU,F
INT

y-

G,
C,

40

oac 2U---,\fV'v--4
let Yrel = 'OO.DMV

0-------..

-'~;~Imo

.EF HI
.EF L O O - - - - - -___
CREF
CREF

+IV

P'J"'Y(IC~
1MII

.G.OI.F

.

08C
TUTOO---It----'
_

/

COMMON

H'1:;=i;~=~
!~I:
RtNT
0.•7 F

IN

IN
IN

lUFF

'1QIdl

O...:.:!!"-'INIr--4

q=~~==-.,

INT
y-[

}TOOIS.IoAV

I.,

0,
GND

To,," 1

08C'

..

ov

2•

0344-16

0344-15

Figure 14: 7137 Operated from
Single + 5V Supply.

Figure 15: Measuring Ratlometrlc Values of
Quad Load Cell.

An external reference must be used in this
application, since the voltage between V+ and
V - is Insufficient for correct operation of the
Internal reference.

The resistor values within the bridge are
determined by the desired sensitivity.

+tv
y+

-

OSCI
OSC2
08C3
TEIT

AI
fI
GI

REFLO

D2
C2

CREF
COMMON
INHI
INLO

.,

.,

To

v"

01
CI

12Kn

.,
A2

.

REFHI

c ...

Al'
BUFF

.NT

0344-17

Figure 16: Circuit for developing Underrange and
Overrange signals from outputs.
The LM339 is required to ensure logic compatibility with heavy display loading.

'Values depend on clock frequency. See Figures 10. 11. and 12.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-65

....::;... ICL7137

S:!

~~~~~1'-----------~----4r--------------------------------~~+5V
40

Seel. l.etor "lUll
(V,.. '" 100ntV lor AC to AMI)

OSC1

osc.
OSC.
TEST
REF HI
REFLO
CREF
C REF

COMMON
INHf

IN LO
A-Z
BUFF

'NT

v-

G,
C,

'"

G3
GND

"
0344-18

Figure 17: AC to DC Converter with 7137

APPLICATION NOTES

ICL7137 EVALUATION KITS

A016
A017
A018

After purchasing a sample of the 7137, the majority of
users will want to build a simple voltmeter. The parts can
then be evaluated against the data sheet specifications,
and tried out in the intended application.
To facilitate evaluation of this unique circuit, Intersil is offering a kit which contains all the necessary components to
build a 3%-digit panel meter. With the ICL7137EV/Kit, an
engineer or technician can have the system "up and running" in about half an hour. The kit contains a circuit board,
LED display, passive components, and miscellaneous hardware.

A023
A032

A046
A047
A052

"Selecting AID converters," by David Fullagar.
"The Integrating AID Converter," by Lee Evans.
"Do's and Dont's of Applying AID Converters," by
Peter Bradshaw and Skip Osgood.
"Low Cost Digital Panel Meter Designs," by David
Fullagar and Michael Dufort.
"Understanding the Auto-Zero and Common-Mode
Behavior of the ICL7106/7/9 Family," by Peter
Bradshaw.
"Building a Battery-Operated Auto Ranging DVM
with.the ICL7106," by Larry Goff.
"Games People Play with Intersil's AID Converters" edited by Peter Bradshaw.
"Tips for Using Single-Chip 3%-Digit AID Converters," by Dan Watson.

'NTERS'L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typIcal va/IIBs have bgem charaotsrized but are not tested.

2-66

ICL7139
33/4-Digit
Autoranging Multimeter
GENERAL DESCRIPTION

s"",}..~

The Intersil ICL7139 is a high perfor
wer,
auto-ranging digital multimeter IC. Unlike
utoranging
multimeter ICs, the ICL7139 always displays the result of a
conversion on the correct range. There is no "range hunting" noticeable in the display. The unit will autorange between the four different ranges. A manual switch is used to
select the 2 high group ranges. DC current ranges are 4 mA
and 40 mA in the low current group, 400 mA and 4A in the
high current group. Resistance measurements are made on
4 ranges, which are divided into two groups. The low resistance ranges are 4/40 kilohms. High resistance ranges are
0.4/4 megohms. Resolution on the lowest range is 1 ohm.

• 13 Ranges:
4 DC Voltage-400 mV, 4V, 40V, 400V
1 AC Voltage-400V
4 DC Current-4 mA, 40 mA, 400 mA, 4A
4 Resistanc_4 KO, 40 KO, 400 KO, 4 MO
• Autoranglng-Flrst Reading Is Always on Correct
Range
• On-Chip Duplex LCD Display Drive Including Three
Decimal Points and 11 Annunciators
• No Additional Active Components Required
• Low Power Dissipation-Less than 20 mW-1000
Hour Typical Battery Life
• Average Responding Converter for Sinewave Inputs
• Display Hold Input
• Continuity Output Drives Piezoelectric Beeper
• Low Battery Annunciator with On-Chip Detection
• Guaranteed Zero Reading for 0 Volts Input on All
Ranges

ORDERING INFORMATION
Part
Number

Temperature
Range

Package

ICL7139CPL

O°Cto + 70°C

40 Pin Plastic DIP

'ICL7139CM44

O°Cto +70°C

44 Pin Surface Mount

'Consult Factory for DetaIls.
SWITCHES

I

B

I
I
I
I

OfGITALCOMMON

_ _ _ _ _ _ _ -.J
yt.

V-COM

0079-1

EXTERNAL
RESISTORS
AN.
CAPACITORS

0079-2

Figure 2: Functional Diagram

Figure 1: Pin Configuration

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTieS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

301671-003

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values hsve been characfBriz9d but are not tested.

2-67

....= ICL7139
~

2

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (V + to V -) ......................... 15V

Storage Temperature Range ........... - 65'C to + 130'C
Lead Temperature (Soldering, 10 sec) .............. 300'C

Reference Input Voltage (VREF to COM) .......•....... 3V
Analog Input Current. ........................... 100 J10A
(IN + Current or IN + Voltage)
Clock Input Swing ........................ V+ to V+ - 3

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated In the operational sections of the specifications is not
impll6d. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Power Dissipation (Plastic Package) •............ 800 mW
Operating Temperature Range ............. O'C to + 70'C

ELECTRICAL CHARACTERISTICS v+ = + 9.0V, TA
volts, test circuit as shown in Figure 3. Crystal = 120 kHz.

=

+ 25'C, VREF adjusted for -3.700 reading on DC

Test Conditions

Parameter
Zero Input Reading

VIN or liN or RIN = 0.00

Rollover Error (Note 1)

VIN or liN = ± Full Scale1

Min

Typ

-00.0

Max

Units

+00.0

V,I,Ohms

4
-1

Counts
+1

Counts

±1

% ofRDG + 1

~ccuracy DC V, 400 Volt Range Excluded

±0.2

% ofRDG + 1

Accuracy Ohms, 4K and 400K Range

±0.5

% ofRDG + 8

Linearity (Best Straight Line) (Note 6)
Accuracy DC V, 400 Volt Range Only

f'.ccuracy Ohms, 40K and 4 Meg Range
Accuracy DC I, Unadjusted for FS
Accuracy DC I, Adjusted for FS
Accuracy AC V (Note 5)

@60Hz

Noise (Note 2, 95% of Time)

VIN = 0, DC Volts
VIN = 0, AC Volts
VIN = 0, DC Voltage Range

Analog Common (with Respect to V +)

< 10 J10A
ICOMMON < 10 J1oA, Temp
ICOMMON < 100 J10A
Average DC < 50 mV

Backplane/Segment Drive Voltage

% ofRDG + 1

±0.2

%ofRDG + 1
%ofRDG

VREF

V

0.1

LSB

4

Noise (Note 2, 95% of Time)
Supply Current

Output Impedance of Analog Common

% ofRDG + 9

±0.5
±2

Open Circuit Voltage for Ohms Measurements RUNKNOWN = Infinity

Temperature Coefficient of Analog Common

±1

2.7

ICOMMON

LSB

1.5

2.4

2.9

3.1

-100

= 0-70'C

2.8

Backplane/Segment Display Frequency

mA
V
ppml'C

1

10

3.0

3.2

75

Ohms
V
Hz

-50

+50

J10A

Switch Input Levels (High Trip Point)

V+ - 0.5

V+

V

Switch Input Levels (Mid Trip Point)

V- + 3

V+ - 2.5

V

Switch Input Levels (Low Trip Point)

V-

V- + 0.5

V

100

J10s

2000

Counts

Switch Input Current (Note 3)

Beeper Output Drive (Rise or Fall Time)

VIN = V+ toV-

25

CLOAD = 10nF

Beeper Output Frequency

kHz

2

Continuity Detect

Range = Low Ohms, VREF = 1.00V

Power Supply Functional Operation

V+ toV-

7

9

11

V

Low Battery Detect (Note 4)

V+ toV-

6.5

7

7.5

V

500

NOTE 1: Rollover is defined as absolute value of negative reading minus absolute value of positive reading.
2: Noise is defined as the width of the uncertainty window (where the display will flicker) between two adiacent codes.
3: Applies to pins 17-20.
4: Analog Common falls out of regulation when the Low Battery Detect is asserted. however the ICL7139 will continue to operate correctly with a supply
voltage above 7 volts and below 11 volts.
5: For 50 Hz use a 100 kHz crystal.
6: Guaranteed by design. not tested.
RDG

~

Reading

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-68

ICL7139
3%-Dlglt Autoranglng DMM Using Intersil's ICL7139

r----.....-t
10llll 9
10 Mll12
II

3.3nF

LO BAT

DEINTEGRATE
TO
DISPLAY

INTEGRATE (V/ ll)

10llll 7

AC

-3999

kllMll

LOll
lMll 8

BEEPER 16
OUTPUT
4

Hill
1 Mll 11

INTEGRATE (I)

INPUTS
9.9ll
V!ll!p.A
m A o - - - - -..

10
r o l l o - - - -....~_.~~ ANALOG
COMMON

N/C~

SIB

-

•

v+

ICL7139

O.lll

N/C+!-'--

mAVp.A

17

V+~.-~~--~ mA/p.A

N/C~

V"

5

Hill, DC 19
LOll,AC

S2A

S2B

Hill/DC
LOll/AC
• OFF

~V+

~N/C
~

y+~
N/C+!-'--

SIC

18 ll/V/A

V"~.-~~--...

V"~
~V+
e!!!!4N/C

0079-3

Figure 3: ICL7139 Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2·69

.....:= ICL7139
~

1/0

Table 1: Pin Numbers and Function
Pin Function
Pin Number

0
0
0

3

Backplane 1

I

4

I

1

Segment Driver POLl AC

2

Backplane 2

5

V+
V-

I

6

Reference Input

0
0

7

LoOhms

8

Hi Ohms

DETAILED DESCRIPTION
General
Figure 2 is a simplified block diagram of the ICL7139. The
digital section includes all control logic, counters, and display drivers. The digital section is powered by V+ and Digital Common, which is about 3V below V+. The oscillator is
also in the digital section. Normally 120 kHz for rejection of
60 Hz AC interference and 100 kHz for rejection of 50 Hz
AC, the oscillator output is divided by two to generate the
internal master clock. The analog section contains the integrator, comparator, reference section, analog buffers, and
several analog switches which are controlled by the digital
logic. The analog section is powered from V + and V - .

1/0

9

Deintegrate

1/0

10

Analog Common

I

11

Int I

I

12

IntV/Ohms

I

13

Triple Point

I

14

Auto Zero Capacitor (CAZ)

I

15

Integrate Capacitor (CINT)

0

16

Beeper Output

I

17

mAl/LA

I

18

OhmslV/A

I

19

Hi Ohms DC/Lo Ohms AC

I

20

Hold

0

21

Oscillator Out

Range 1 Integrate

I

22

Oscillator In

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

23

Segement DRIVER kIm

24

Segment Driver Ohmsl A

25

Segment Driver M Ohmsl/LA

26

Segment Driver Lo BallV

27

Segment Driver Bo/Co

The ICL7139 performs a full autorange search for each
reading, beginning with range 1. During the range 1 integrate period, internal switches connect the INT V10hm terminal to the Triple Point (Pin 13). The input signal is integrated for 10 clock cycles, which are gated out over a period of 1000 clock cycles to ensure good normal mode rejection of AC line interference.

28

Segment Driver Ao/Do

29

Segment Driver Go/Eo

30

Segment Driver Fo/DPl

31

Segment Driver Bl/Cl

32

Segment Driver Al/Dl

DC VOLTAGE MEASUREMENT
Autozero
Only those portions of the analog section which are used
during DC voltage measurements are shown in Figure 5. As
shown in the timing diagram (Figure 6), each measurement
starts with an autozero (AZ) phase. During this phase, the
integrator and comparator are configured as unity gain buffers and their non-inverting inputs are connected to Common. The output of the integrator, which is equal to its offset, is stored on CAz-the autozero capacitor. Similarly, the
offset of the comparator in stored in CINT. The autozero
cycle equals 1000 clock cycles which is one 60 Hz line cycle with a 120 kHz oscillator or one 50 Hz line cycle with a
100 kHz crystal.

Range 1 Deintegrate

35

Segment Driver B2/C2

36

Segment Driver A2/D2

37

Segment Driver G2/E2

38

Segment Driver F2/DP3

39

Segment Driver Ba/Ca

At the beginning of the deintegrate cycle, the polarity of
the voltage on the integrator capacitor (CINT) is checked,
and either the DEINT+ or DEINT- is asserted. The integrator capacitor CINT is then discharged with a current equal to
VREF/RDEINT. The comparator monitors the voltage on
CINT. When the voltage on CINT is reduced to zero (actually
to the Vas of the comparator), the comparator output
switches, and the current count is latched. If the CINT voltage zero-crossing does not occur before 4000 counts have
elapsed, the overload flag is set. "OL" (overload) is then
displayed on the LCD. If the latched result is between 360
and 3999, the count is transferred to the output latches and
is displayed. When the count is less than 360, an underrange has occurred, and the ICL7139 then switches to
range 2-the 40V scale.

40

Segment Driver ADG3/E3

Range 2

33

Segment Driver Gl/El

34

Segment Driver Fl/DPl

The range 2 measurement begins with an autozero cycle
similar to the one that preceded range 1 integration. Range
2 cycle length however, is one AC line cycle, minus 360
clock cycles. When performing the range 2 cycle, the signal
is integrated for 100 clock cycles, distributed throughout

NOTE: For segment drivers, segments are listed as (segment for backplane
1)/(segment for backplane 2). Example: pin 27; segment Bo is on

backplane 1, segment Co is on backplane 2.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTI!=S OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical values have been characterized but Sf9 not tested.

2-70

ICL7139
one line cycle. This is done to maintain good normal mode
rejection. Range 2 sensitivity is ten times greater than range
1 (100 vs. 10 clock cycle integration) and the full scale voltage of range 2 is 40V. The range 2 deintegrate cycle is
identical to the range 1 deintegrate cycle, with the result
being displayed only for readings greater than 360 counts. If
the reading is below 360 counts, the ICL7139 again asserts
the internal underrange signal and proceeds to range 3.

surement is transferred to the output latches and displayed
even if the reading is less than 360.

Autozero
After finding the first range for which the reading is above
360 counts, the display is updated and an autozero cycle is
entered. The length of the autozero cycle is variable which
results in a fixed measurement period of 24,000 clock cycles (24 line cycles).

Range 3
The range 3 or 4V full scale measurement is identical to
the range 2 measurement, except that the input signal is
integrated during the full 1000 clock cycles (one line frequency cycle). The result is displayed if the reading is greater than 360 counts. Underrange is asserted, and a range 4
measurement is performed if the result is below 360 counts.

DIGIT 3
LOW
BATT

,

\

~

"

- _/0

Range 4

AC

This measurement is similar to the range 1, 2 and 3 measurements, except that the integration period is 10,000
clock cycles (10 line cycles) long. The result of this mea-

DP3

\

00
"
/
" "/
-

0

DP2

DPl

0079-4

Figure 4: Display Segment Nomenclature

ROEINT

CAZ

CINT

CAZ

CINT

RDEINT

OEIHT-

OEIHT AZ

INTWI!

VIN

-=-

R"mI

Ym

-=Ym
OEINT+

COMPARATOR

-=v+
1.7V

COMMON

COMMON

T - (INT)(AR}(AZ)
Aft • AUTORANGE CHOPPER
AZ • AUTOZERO
INT = INTEGRATE

v- t-------...J
0079-5

Figure 5: Detailed Circuit Diagram for DC Voltage Measurement
tNTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONOITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL Be IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characteriz(Jd but are not testsd.

2-71

•

......:=

ICL7139

...

2

--.rL

FIRST AUTO·ZERO

--1"1-

FIRST INTEGRATE

L
t -.J

FIRST DEINTEGRATE

I

UNDERRANGE

-..JL
--fl-

AUTO·ZERO
SECOND AUTO·ZERO
SECOND INTEGRATE

L

_____.....1I
UNDERRANGE

~

t.J

_____...rl..-.
______r I -

:
________L
UNDERRANGE

SECOND DEINTEGRATE
__________________
AUTO·ZERO

~I

'--

THIRD AUTO·ZERO
THIRD INTEGRATE

L THIRD DEINTEGRATE
..J~--------------~I
AUTO·ZERO
'-FOURTH AUTO·ZERO

--------.....

~----""L

FOURTH INTEGRATE

L
..-.r-L.

FOURTH DEINTEGRATE
AUTO·ZERO

II I I I I I I I I II I II I I I I I I I I I I

o

1 2 3 4 5 6 7 8 9 10 11 12 1314 15 16 17 18 19 20 21 22 2324

LINE FREQUENCY CYCLES (1 CYCLE = 1000 INTERNAL CLOCK PULSES = 2000
OSCILLATION CYCLES)

0079-6

Figure 6: Timing Diagram for DC Voltage Measurement
By using the lower value integration resistor, and only the
2 most sensitive ranges, the voltage drop across the current
sensing resistor is 40 mV maximum on the 4 mA and
400 mA ranges; 400 mV maximum on the 40 mA and 4A
scales. With some increase in noise, these "burden" voltages can be reduced by lowering the value of both the current sense resistors and the RINT I resistor proportionally.
The DC current measurement timing diagram is similar to
the DC voltage measurement timing diagram, except in the
DC current timing diagram, the first and second integrate
and deintegrate phases are skipped.

OCCURRENT
Figure 7 shows a simplified block diagram of the analog
section of the ICL7139 during DC current measurement.
The DC current measurements are very similar to DC voltage measurements except: 1) The input voltage is developed by passing the input current through a 0.1 ohm (HI
current ranges), or 9.9 ohm (LOW current ranges) current
sensing resistor; 2) Only those ranges with 1000 and 10,000
clock cycles of integration are used; 3) The RINT I resistor is
1 megohm, rather than the 10 megohm value used for the
RINT v resistor.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typ;csl values hsvtJ been characterized but are not tested.

2-72

.D~DIL

ICL7139
AC VOLTAGE MEASUREMENT

effectively deintegrating the voltage across a known resistor
(RKNOWN1 or RKNOWN2 of Figure 9). The shunting effect of
RINTV does not affect the reading because it cancels exactly between integration and deintegration. Like the current
measurements, the ohm measurements are split into two
sets of ranges. LO ohms measurements use a 10 kilohm reference resistor, and the full scale ranges are 4 and
40 kilohms. HI ohms measurements use a 1 megohm reference resistor, and the full scale ranges are 0.4 and 4 megohms. The measurement phases and timing are the same
as the measurement phases and timing for DC current except: 1) During the integrate phases the input voltage is the
vo!tage across the unknown resistor Rx, and; 2) During the
delntegate phases, the input voltage is the voltage across
the reference resistor RKNOWN1 or RKNOWN2.

. As shown in Figure. 8, the AC input voltage is applied
directly to the ICL7139 Input resistor. No separate AC to DC
?onversion ci~uitry is n.eeded. The AC measurement cycle
IS begun by disconnecting the integrator capacitor and using the integrator as an autozeroed comparator to detect
the positive-going zero crossing. Once synchronized to the
AC input, the autozero loop is closed and a normal integra~e/deintegrate cycle begins. The ICL7139 resynchronize~ Itself ~o .the I1:C input pri~r to every reading. Because
~Iode D4 IS In senes WIth the Integrator capaCitor, only positive current from the integrator flows into the integrator capacitor, CINT. Since the voltage on CINT is proportional to
t~e half-wave rectified average AC input voltage, a conversion factor must be applied to convert the reading to RMS.
This conversion factor is '7f'1J2 = 1.107, and the system
clock is manipulated to perform the RMS conversion. As a
result the deintegrate and autozero cycle times are reduced
by 10%.

When the ICL7139 is in the LO ohms measurement
mode, the continuity circuit of Figure 10 will be active. When
the voltage across Rx is less than approximately 100 mY,
the beeper output will be on. When R3 is 10 kilohms, the
beeper output will be on when Rx is less than 1 kilohm.

Ratlometrlc Ohms Measurement

RDEIIT
CAl

C'IIT
RDEIIIT

C'IIT
n'
LOW I

ftl

INT I

1.111

CD

Continuity Indication

. The r~tiometric ohms measurement is performed by first
Integrating the voltage across an unknown resistor, Rx, then

R"m

P
...
r:

mlITftl

-:

VRE~

-:
VREf

DEINT+
HIGH I
-:

1.7V

0.10

T • IINTIIARlli%)
Aft • AUTDRANGE CHOI't'Eft
ftl. AUTOZ£RO
INT z INTEGRATE

COMMON

0079-7

Figure 7: Detailed Circuit Diagram for DC Current Measurement
INTERSIL'S SOlE AND EXCLUSIVE WARRANTY OBUGAnON WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE

:~~~:~~ITYSHA~~ ~~~L~~~,,! ~:~T~~~~ ~~~ LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPUED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
NOTE: AU typ/CIIJ vMJee have bssn chIuactt!JrIzed but we not tftt«J.

2-73

2

:: ICL7139
.......

~ Common Voltage

pin is not designed to drive large external loads, loading on
this pin should not exceed a single CMOS input. The oscillator frequency is internally divided by two to generate the
ICL7139 clock. The frequency should be 120 kHz to reject
60 Hz AC signals, and 100 kHz to reject 50 Hz signals.

The analog and digital common voltages of the ICL7~39
are generated by an on-chip resistor/zener/diode combInation, shown in Figure 11. The resistor values are chose~ .so
the coefficient of the diode voltage cancels the positive
temperature coefficient of the zener voltage. This volta~e is
then buffered to provide the analog common and the digital
common voltages. The nominal voltage betw(;jen V+ ~nd
analog common is 3V. The analog common buffer can sink
about 20 mA, or source 0.01 mA, with an output impedance
of 10 ohms. A pullup resistor to V+ may be used if more
sourcing capability is desired. Analog common may be used
to generate the reference voltage, if desired.

Display Drivers
Figure 13 shows typical LCD Drive waveforms, RMS ON,
and RMS OFF voltage calculations. Duplex multiplexing is
used to minimize the number of connections between the
ICL7139 and the LCD. The LCD has two separate backplanes. Each drive line can drive two individual segments,
one referenced to each backplane. The ICL7139 drives 3%
7-segment digits, 3 decimal points, and 11 annunciators.
Annunciators are used to indicate polarity, low battery condition, and the range in use. Peak drive voltage across the
display is approximately 3V. An LCD with approximately
1.4V RMS threshold voltage should be used. The third voltage level needed for duplex drive waveforms is generated
through an on-chip resistor string. The DC component of
the drive waveforms is guaranteed to be less than 50 mY.

Oscillator
The ICL7139 uses a parallel resonant-type crystal in a
Pierce oscillator configuration, as shown in Figure 12, and
requires no other external components. The crystal eliminates the need to trim the oscillator frequency. An external
signal may be capacitively coupled in OSC IN, with a signal
level between 0.5 and 3V pk-pk. Because the OSC OUT

ROEINT

I -- -- -

~------~

TRIPLE POINT

---I

I
I
I
I
I

ACS

RINTV

ACINT

"V
INTVIO

~------0 BEEPER OUTPUT

L
0079-10

Figure 10: Continuity Beeper Drive Circuit
NOTE 1: The ICL7139 contains a comparator that is enabled on the lowest ohms range. It trips at approximately V. of the full scale value of that range and enables
the beeper driver to oscillate (between V- and V+) at 2 kHz. The beeper driver is capable of driving a piezo-eleclric transducer. The beeper output
response is Independent of the state of the conversion; therefore appears instantaneous to the user. Some applications may require a 150 pF capacitor
between pin 4 and pin 8 to insure a sharp onloff continuity detection.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE 'WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typicBI vs/uBS hal/9 b86n ch8rsct6rized but tuB not tBsted.

2-76

ICL7139
r---~r---------------~------------------~---------------~

+

6.7V

3V
125K
ANALOG

+r---'--_
3.WL..._..,._ _..1

COMMON
(PIN10)

LO BAT

DIGITAL

COMMON
(INTERNAL)

5K

180K

+
L-----------------------~~--------------------_+--------~--~----V0079-11

Figure 11: Analog and Digital Common Voltage Generator Circuit

Crystal

Meter Protection

The ICL7139 is designed to use a parallel resonant
120 kHz or 100 kHz crystal with no additional external components. The Rs parameter should be less than 25 kilohms
to ensure oscillation. Initial frequency tolerance of the crystal can be a relatively loose 0.05%.

The ICL7139 and its external circuitry should be protected against accidental application of 11 0/220V AC line voltages on the ohms and current ranges. Without the necessary precautions, both the 7139 and its external components could be damaged under such fault conditions. For
the current ranges, fast-blow fuses should be used between
S5A in Figure 15 and the 0.1 ohm and 9.9 ohm shunt resistors. For the ohms ranges, no additional protection circuitry
is required. However, the 10 kilohm resistor connected to
pin 7 must be able to dissipate 1.2W or 4.SW for short periods of time during accidental application of 11 OV or 220V
AC line voltages respectively.

Switches
Because the logic input draws only about 5 ",A, switches
driving these inputs should be rated for low current, or "dry"
operations. The switches on the external inputs must be
able to reliably switch low currents, and be able to handle
voltages in excess of 400V AC.

Reference Voltage Source
A voltage divider connected to V+ and Common is the
simplest source of reference voltage. While minimizing external component count, this approach will provide the
same voltage tempco as the ICL7139 Common-about 100
PPMI'C. To improve the tempco, an ICLS069 bandgap reference may be used (see Figure 14). The reference voltage
source output impedance must be :;:; RDEINT/4000.

33DK

Applications, Examples, and Hints
A complete autoranging 3% digit multi meter is shown in
Figure 15. The following sections discuss the functions of
specific components and various options.

J!0PF

0079-12

Figure 12: Internal Oscillator Circuit Diagram

INTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but am not tested.

2-77

::
,.. ICL7139
r0-

Y Printed Circuit Board Layout

The rollover error causes the width of the + 0 count to be
larger than normal. The ICL7139 will thus read zero until
several hundred microvolts are applied in the positive direction. The ICL7139 will read -1 when approximately
-100)J-V is applied.
The rollover error can be minimized by guarding the Triple
Point ,and CAZ nodes with a trace connected to the CINT
pin, which is driven by the output of the integrator. Guarding
these nodes with the output of the integrator reduces the
stray capacitance to ground, which minimizes the charge
error on CINT and CAZ. If possible, the guarding should be
used on both sides of the PC board.

Considerations

Particular attention must be paid to rollover performance,
leakages, and guarding when designing the PCB for a
ICL7139-based multimeter.

Rollover Performance, Leakages, and
Guarding
Because the ICL71.39 system measures very low currents, it is essential that the PCB have low leakage. Boards
should be properly cleaned after soldering. Areas of particular importance are: 1) The INT VIn and INT I Pins; 2) The
Triple Point; 3) The ROEINT and the CAZ pins.
The conversion scheme used by the ICL7139 changes
the common mode voltage on the integrator and the capacitors CAZ and CINT during a positive deintegrate cycle. Stray
capacitance to ground is charged when this occurs, removing some of the charge on CINT and causing rollover error.
Rollover error increases about 1 count for each picofarad of
capacitance between CAZ or the Triple Point and ground,
and is seen as a zero offset for positive voltages. Rollover
error is not seen as gain error.

BACKPLANE

SEGMENT ON

SEGMENT OFF

~

I

L
I

.J
JL--,

VSEGMENT ON

---1

I

Stray Pickup
While the ICL7139 has excellent rejection of line frequency noise and pickup in the DC ranges, any stray coupling
will effect the AC reading. Generally, the analog circuitry
should be as close as possible to the ICL7139. The analog
circuitry should be removed or shielded from any 120V AC
power inputs, and any AC sources such as LCD drive waveforms. Keeping the analog circuit section close to the
ICL7139 will also help keep the area free of any loops, thus
reducing magnetically coupled interference coming from
power transformers, or other sources.
V·

VPEAK

VPEAKI2

0

DCOM

VRMS

Vf

VPEAK

ON

\/PEAK

OFF

VRMS

= (f

VPEAK

= 3V ± 10%

VPEAK

0
2.37V
RMS ON _
RMSOFF_1.06V

VPEAK

0
:VPEAK

(VOLTAGE ACROSS ON SEGMENn

Lr--J _

2VPEAK

VPEAK
VSEGMENT OFF

(VOLTAGE ACROSS OFF SEGMENT)

o
- VPEAK

0079-13

Figure 13: Duplexed LCD Drive Waveforms

INTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIeD OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valU9S have been characterized but are not tested.

2-78

ICL7139
10MEG

-""''''''-1

OEINTEGRATE

TRIPLE POINT

EXTERNAL
REFERENCE

INTEGRATE VOLT/OHM
INTEGRATE CURRENT

ICL8069

lM.g

' - - - - - - - - 1 REFERENCE INPUT

'-.....---------1 ANALOG COMMON

0079-14

Figure 14: External Voltage Reference Connection to ICL7139

...-J.,f.>/Ir.....--I 3.3 nF

•

10t.t.O.

IOMIl12

DEINT

LO BAT

DISPLAY
DRIVE
OUTPUTS

INT(V/Il)
10 kll 7

AC

mAVJ-IA

-3999

kllMIl

LOll
1 Mil 8
Hill

BEEPER

1 Mil 11
INT(I)
9.91l

0.11l
2W

10
18

ICL8069

V-

COMMON

VREF
V/Il/A
HIIl-DC/LOIl-AC

17

NOTE 1:
2:
3:
4:

y+

ICL7139

S4B

mA

16

mA/J-IA

HOLD

19

52

20

53

-lV'
-lV'

' - - - -.....-

Figure 15: Basic Multimeter Application Circuit for ICL7139

...... PIN 10

S2 Closed: Hill·DC
S3 Closed: Hold Reading
0079-15

Crystal is a Statek or SaRonix eX·lv type.
Multimeter protection components have not been shown,
Display is from LXD, part number 3BD3R02H.
Beeper is from muRata, part number PKM24·4AO.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH AESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FDA A PARTICULAR

use.

NOTE: All typicsl VSIUBS hSV9 been characterized but are not tested.

2·79

=
.. ICL7139

......

!:!

ICL7139

0079-16

Figure 16: PC Board Layout

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL

ae

IN LIEU OF ALL OTHER WAARANTIE:S, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY ANO FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-80

ICL7149
Low Cost 33/4-Digit
Autoranging Multimeter
GENERAL DESCRIPTION
The Intersil ICL7149 is a high perfor
autoranging digital multimeter IC. Unlike
anging
multimeter ICs, the ICL7149 always displays the result of a
conversion on the correct range. There is no "range hunting" noticeable in the display. The unit will autorange between the four different ranges in the DC voltage, DC current and resistance measurement modes. A manual switch
is used to select the 2 high group ranges. DC current ranges
are 4 mA and 40 mA in the low current group, 400 mA and
4A in the high current group. Resistance measurements are
made on 4 ranges, which are divided into two groups. The
low resistance ranges are 4/40 kilohms. High resistance
ranges are 0.414 megohms. Resolution on the lowest range
is 1 ohm.

• 18 Ranges:
4 DC Voltag_400 mY, 4V, 40V, 400V
2 AC Voltag_wlth Optional AC Circuit
4 DC Current-4 mA, 40 mA, 400 mA, 4A
4 AC Current with Optional AC Circuit
4 Reslstance-4 ko., 40 ko., 400 ko., 4 Mo.
• Autoranglng-Flrst Reading Is Always on Correct
Range
• On-Chip Duplex LCD Display Drive Including Three
Decimal Points and 11 Annunciators
• Low Power Dissipation-Less than 20 mW-1000
Hour Typical Battery Life
• Display Hold Input
• Continuity Output Drives Piezoelectric Beeper
• Low Battery Annunciator with On-Chip Detection
• Guaranteed Zero Reading for 0 Volts Input on All
Ranges

POL/AC
BP2
BP1

ORDERING INFORMATION

v+

Part
Number

V-

VREF
LOD.
HID.
DEINT

Temperature
Range

Package

ICL7149CPL

O·Cto +70·C

40 Pin Plastic DIP

*ICL7149CM44

O·Cto +70·C

44 Pin Surface Mount

'Consult Factory for Details

ANALOG - cOt.nol0N 10

HI.o.-DC/LO.o.-AC 19

0094-1

Figure 1: Pin Configuration

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

301672-001

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2-81

•

ICL7149
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V+ to V-) ......................... 15V

Storage Temperature Range ........... -65'C to + 130'C
Lead Temperature (Soldering, 10 sec) .............. 300'C

Reference Input Voltage (VREF to COM) ............... 3V
Analog Input Current. ........................... 100 /kA
(IN + Current or IN + Voltage)
Clock Input Swing ........................ V+ to V+ - 3

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
imp/led. Exposure to absolute maximum rating conditions for extended peri~

Power Dissipation (Plastic Package) ............. 800 mW
Operating Temperature Range ............. O'C to + 70'C

ods may affect device reliability.

ELECTRICAL CHARACTERISTICS v+ = +9.0V, TA
Yolts, test circuit as shown in Figure 3 Crystal Frequency = 120 kHz.
Parameter

=

+ 25'C, VREF adjusted for -3.700 reading on DC

Test Conditions

Zero Input Reading

YIN or liN or RIN = 0.00

Rollover Error (Note 1)

YIN or liN

=

Typ

Min
-00.0

Max

Units

+00.0

Y,l,Ohms

4

± Full Scale

Counts

-1

Linearity (Best Straight Line) (Note 5)
Accuracy DC Y, 400 Yolt Range Only

+1

Counts

±1

%ofRDG + 1

Accuracy DC Y, 400 Yolt Range Excluded

±0.2

% ofRDG + 1

Accuracy Ohms, 4K and 400K Range

±0.5

%ofRDG + 8

±1

%ofRDG + 9

Accuracy Ohms, 40K and 4Meg Range
Accuracy DC I, Unadjusted for FS

±0.5

%ofRDG + 1

Accuracy DC I, Adjusted for FS

±0.2

%ofRDG + 1

=

Open Circuit Yoltage for Ohms Measurements

RUNKNOWN

Noise (Note 2, 95% of Time)

YIN = 0, DC Yolts

Infinity

= 0, DC Yoltage Range

Supply Current

YIN

Analog Common (with Respect to Y+)

ICOMMON

Temperature Coefficient of Analog Common

ICOMMON < 10 p,A,
Temp = O'C-70'C

< 10 p,A

2.8

ICOMMON

Backplane/Segment Drive Yoltage

Average DC

2.7

Backplane/Segment Display Frequency
Switch Input Current (Note 3)

Y

0.1

LSB

1.5

2.4

3.0

3.2

-100

< 100 p,A
< 50 mY

Output Impedance of Analog Common

YREF

YIN

=

1

10

2.9

3.1

Y+

Ohms
Y
Hz

-50

Y+ toY-

Y
ppmrC

75

Switch Input Levels (High Trip Point)

mA

0.5

+50

p,A

Y+

Y
Y

Switch Input Levels (Mid Trip Point)

Y- + 3

Y+ - 2.5

Switch Input Levels (Low Trip Paint)

Y-

Y- + 0.5

Y

100

p,s

2000

Counts

Beeper Output Drive (Rise or Fall Time)

CLOAD

=

25

10 nF

Beeper Output Frequency

2

kHz

Continuity Detect

Range = Low Ohms,
YREF = 1.00Y

Power Supply Functional Operation

Y+ toY-

7

9

11

Y

Low Battery Detect (Note 4)

Y+ toY-

6.5

7

7.5

Y

500

NOTE 1: Rollover is defined as absolute value of negative reading minus absolute value of positive reading.

2: Noise is defined as the width of the uncertainty window (where the display will flicker) between two adjacent codes.
3: Applies to pins 17 -20.
4: Analog Common falls out of regulation when the Low Battery Detect is asserted, however the ICL7149 will continue to operate correctly with a supply
voltage above 7 volts and below 11 volts.
5: Guaranteed by design, not tested.
RDG = Reading

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE !N LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but arB not tested.

2-82

ICL7149
SWITCHES

V·V-COM

EXTERN.L
RESISTORS
.ND
C.P.CITORS

0094-2

Figure 2: Functional Diagram
33;'·Olglt Autoranglng OMM Using Intersn's ICL7149

LO B.T
TO
DlSPL.V

m.V;LA

-3999

.c

kliMIi

BEEPER 16
OUTPUT
V·

INPUTS
V!Il!;LA

•

ICL7149

m.o----....

-=- 9V
-=-BmERV

0.111

S2.

10 .NALOG
COM o----.....-1r-', COMMON

N/C~

N/C.Y---.

-=

SIB

17

v·~~r....,:;,:,:;-~ m./;LA

y-

I

Hill/DC
LOIl/.C

• OFF

HIIl.DC 19
LOIl ••C

S2B

N/C.e!-

~V·

~N/C

..2!!-

V+~

N~:~ :~r....,;;.SI",C_.:.la'in/V/A
v·.e!~v+

~N/C
0094-3

Figure 3: ICL7149 Test Circuit

INTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typiCal values have been characterized but are not tested.

2·83

.......~ ICL7149
g
1/0

Table 1: Pin Numbers and Functions
Pin Function
Pin Number

0
0
0

3

Backplane 1

I

4

V+

I

5

V-

I

6

Reference Input

0
0

7

LoOhms

8

Hi Ohms

1

Segment Driver, POll AC

2

Backplane 2

I/O

9

Deintegrate

I/O

10

Analog Common

I

11

Int I

I

12

IntV/Ohms

I

13

Triple Point

I

14

Auto Zero Capacitor (CAZ)

I

15

Integrate Capacitor (CINT)

0

16

Beeper Output

I

17

mAi/LA

I

18

OhmslV/A

DETAILED DESCRIPTION
General
Figure 2 is a simplified block diagram of the ICL7149. The
digital section includes all control logic, counters, and display drivers. The digital section is powered by V+ and Digital Common, which is about 3V below V+. The oscillator is
also in the digital section. Normally 120 kHz for rejection of
60 Hz AC interference and 100 kHz for rejection of 50 Hz
AC, the oscillator output is divided by two to generate the
internal master clock. The analog section contains the integrator, comparator, reference section, analog buffers, and
several analog switches which are controlled by the digital
logic. The analog section is powered from V + and V - .

DC VOLTAGE MEASUREMENT
Autozero

I

19

Hi Ohms-Dc/Lo Ohms-AC

Only those portions of the analog section which are used
during DC voltage measurements are shown in Figure 5. As
shown in the timing diagram (Figure 6), each measurement
starts with an autozero (AZ) phase. During this phase, the
integrator and comparator are configured as unity gain buffers and their non-inverting inputs are connected to Common. The output of the integrator, which is equal to its offset, is stored on CAZ, the autozero capacitor. Similarly, the
offset· of the comparator is stored in CINT. The autozero
cycle equals 1000 clock cycles, which is one 60 Hz line
cycle with a 120 kHz crystal, or one 50 Hz line cycle with a
100 kHz crystal.

I

20

Hold

Range 1 Integrate

0

21

Oscillator Out

I

22

Oscillator In

The ICL7149 performs a full autorange search for each
reading, beginning with range 1. During the range 1 integrate period, internal switches connect the INT V/Ohm terminal to the Triple Point (Pin 13). The input Signal is integrated for 10 clock cycles, which are gated out over a period of 1000 clock cycles to ensure good normal mode rejection of AC line interference.

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

23

Segment Driver kim

24

Segment Driver Ohms/ A

25

Segment Driver M Ohms/ /LA

26

Segment Driver Lo BatlV

Range 1 Deintegrate

27

Segment Driver Bo/Co

28

Segment Driver Ao/Do

At the beginning of the deintegrate cycle, the polarity of
the voltage on the integrator capacitor (CINT) is checked,
and either the DEINT+ or DEINT- is asserted. The integrator capacitor CINT is then discharged with a current equal to
VREF/RDEINT. The comparator monitors the voltage on
CINT. When the voltage on CINT is reduced to zero (actually
to the Vas of the comparator), the comparator output
switches, and the current count is latched. If the CINT voltage zero-crossing does not occur before 4000 counts have
elapsed, the overload flag is set. "OL" (overload) is then
displayed on the LCD. If the latched result is between 360
and 3999, the count is transferred to the output latches and
is displayed. When the count is less than 360, an underrange has occurred, and the ICL7149 then switches to
range 2-the 40V scale.

29

Segment Driver Go/Eo

30

Segment Driver Fo/DP1

31

Segment Driver B1/C1

32

Segment Driver A1/D1

33

Segment Driver G1 /E1

34

Segment Driver F1/DP1

35

Segment Driver B2/C2

36

Segment Driver A2/D2

37

Segment Driver G2/E2

38

Segment Driver F2/DP3

39

Segment Driver B3/C3

40

Segment Driver ADG3/E3

NOTE: For segment drivers, segments are listed as
(segment for backplane 1)/(segment for backplane 2).
Example: pin 27; segment BO is on backplane 1, segment CO is on
backplane 2.
INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical values have been characterized but are not tested

2-84

ICL7149
Range 2

Range 4

The range 2 measurement begins with an autozero cycle
similar to the one that preceded range 1 integration. range 2
cycle length however, is one AC line cycle, minus 360 clock
cycles. When performing the range 2 cycle, the signal is
integrated for 100 clock cycles, distributed throughout one
line cycle. This is done to maintain good normal mode rejection. Range 2 sensitivity is ten times greater than range 1
(100 vs 10 clock cycle integration) and the full scale voltage
of range 2 is 40V. The range 2 deintegrate cycle is identical
to the range 1 deintegrate cycle, with the result being displayed only for readings greater than 360 counts. If the
reading is below 360 counts, the ICL7149 again asserts the
internal underrange signal and proceeds to range 3.

This measurement is similar to the range 1, 2 and 3 measurements, except that the integration period is 10,000
clock cycles (10 line cycles) long. The result of this measurement is transferred to the output latches and displayed
even if the reading is less than 360.

Autozero
After finding the first range for which the reading is above
360 counts, the display is updated and an autozero cycle is
entered. The length of the autozero cycle is variable which
results in a fixed measurement period of 24,000 clock cycles (24 line cycles).

a. a. $. .til::, : •

DIGIT

Range 3
LOW

The range 3 or 4V full scale measurement is identical to
the range 2 measurement, except that the input signal is
integrated during the full 1000 clock cycles (one line frequency cycle). The result is displayed if the reading is greater than 360 counts. Underrange is asserted, and a range 4
measurement is performed if the result is below 360 counts.

BAT

AC

3

2

DP3

o

I

DP2

DPI

0094-4

Figure 4: Display Segment Nomenclature

ROEINT

VIN

INT

DEINTAZ

vin

o-.I\I\/'v--...:..-+--......-oc:r-.

VREF -«II-<....- ....- - - - - - - t

V+t-------e-~

6.7V

-+<

COMMONo-_ _C.;.;O;.:;t.1~M.;.;ON~.....

T= (lNT)(AR)(Az)
AR AUTORANGE CHOPPER
AZ AUTO ZERO
INT INTEGRAIT

=
=
=

V-t=======~

___________________________

~

0094-5

Figure 5: Detailed Circuit Diagram for DC Voltage Measurement

INTERSIL'S SOLE AND EXCWSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charact6rizeci but are not tssted.

2-85

.....

: ICL7149
..I

S:!

---I"L-

FIRST AUTO-ZERO

~

FIRST INTEGRATE

L

FIRST DEINTEGRATE

UNDERRANGE : _ _ _..I

----L.

L

AUTO-ZERO

SECOND AUTO-ZERO
SECOND INTEGRATE
SECOND DEINTEGRATE

___L

THIRD AUTO- ZERO

____rL-

THIRD INTEGRATE

L
UNDERRANGE :

L

AUTO-ZERO

UNDERRANGE : - - - . . I

THIRD DEINTEGRATE

---..I

____L

L

AUTO-ZERO

FOURTH AUTO-ZERO

L

FOURTH INTEGRATE

L

FOURTH DEINTEGRATE

L

AUTO-ZERO

I I1 2I 3I 4I 5I 6I 7I 8I 9I 10I 11I 12I 13I 14I 15I 16I 17I 18I 19I 20I 21I 2223
I I 24I

o

0094-6

Line Frequency Cycles
(1 Cycle = 1000 Internal Clock Pulses

= 2000 Oscillation Cycles)
Figure 6: Timing Diagram for DC Voltage Measurement

DC CURRENT

By using the lower value integration resistor, and only the
2 most sensitive ranges, the voltage drop across the current
sensing resistor is 40 mV maximum on the 4 mA and
400 mA ranges; 400 mV maximum on the 40 mA and 4A
scales. With some increase in noise, these "burden" voltages can be reduced by lowering the value of both the current sense resistors and the RINT I resistor proportionally.
The DC current measurement timing diagram is similar to
the DC voltage measurement timing diagram, except in the
DC current timing diagram, the first and second integrate
and delntegrate phases are skipped.

Figure 7 shows a simplified block diagram of the analog
section of the ICL7149 during DC current measurement.
The DC current measurements are very similar to DC voltage measurements except: 1) The input voltage is developed by passing the input current through a 0.1 ohm (HI
current ran~es), or 9.9 ohm (LOW current ranges) current
sensing resistor; 2) Only those ranges with 1000 and 10 000
clock cycles of integration are used; 3) The RINT I resist~r is
1 megohm, rather than the 10 megohm value used for the
RINT V resistor.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAi STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE

~~~~~~~~~~L~~~~L~ ~~N~~;L~;~~ ::~Tl~~~~ ~;~~

LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES

NOTE: All typical values have been characterized but are not tested.

2-86

OF

IiID~Do..

ICL7149
AC VOLTAGE MEASUREMENT

Oscillator

The ICL7149 is designed to be used with an optional AC
to DC voltage converter circuit. It will autorange through two
voltage ranges (400V and 40V), and the AC annunciator is
enabled as with the ICL7139. A typical averaging AC to DC
converter is shown in Figure 8, while an RMS to DC converter is shown in Figure 9. AC current can also be measured with some simple modifications to either of the two
circuits in Figures 8 and 9.

The ICL7149 uses a parallel resonant-type crystal in a
Pierce oscillator configuration, as shown in Figure 13, and
requires no other external components. The crystal eliminates the need to trim the oscillator frequency. An external
signal may be capacitively coupled to OSC IN, with a signal
level between 0.5V and 3V pk-pk. Because the OSC OUT
pin is not designed to drive large external loads, loading on
this pin should not exceed a single CMOS input. The oscillator frequency is internally divided by two to generate the
ICL7149 clock. The frequency should be 120 kHz to reject
60 Hz AC signals, and 100 kHz to reject 50 Hz signals.

Ratiometrlc Ohms Measurement
The ratiometric ohms measurement is performed by first
integrating the voltage across an unknown resistor, Rx, then
effectively deintegrating the voltage across a known resistors (RKNOWN1 or RKNOWN2 of Figure 10). The shunting
effect of RINTV does not affect the reading because it cancels exactly between integration and deintegration. Like the
current measurements, the ohm measurements are split
into two sets of two ranges. LO ohms measurements use a
10 kilohm reference resistor, and the full scale ranges are 4
and 40 kilohms. HI ohms measurements use a 1 megohm
reference resistor, and the full scale ranges are 0.4 and 4
megohms. The measurement phases and timing are the
same as the measurement phases and timing for DC current except: 1) During the integrate phases the input voltage
is the voltage across the unknown resistor Rx, and; 2) During the deintegrate phases, the input voltage is the voltage
across the reference resistor RKNOWN1 or RKNOWN2.

Figure 14 shows typical LCD Drive waveforms, RMS ON,
and RMS OFF voltage calculations. Duplex multiplexing is
used to minimize the number of connections between the
ICL7149 and the LCD. The LCD has two separate backplanes. Each drive line can drive two individual segments,
one referenced to each backplane. The ICL7149 drives 3%
7-segment digits, 3 decimal points, and 11 annunciators.
Annunciators are used to indicate polarity, low battery condition, and the range in use. Peak drive voltage across the
display is approximately 3V. An LCD with approximately
1.4V RMS threshold voltage should be used. The third voltage level needed for duplex drive waveforms is generated
through an on-chip resistor string and the DC component of
the drive waveforms is guaranteed to be less than 50 mY.

Continuity Indication

Ternary Input

When the ICL7149 is in the LO ohms measurement
mode, the continuity circuit .of Figure 11 will be active. When
the voltage across Ax is less than approximately 100 mV,
the beeper output will be on. When R3 is 10 kilohms, the
beeper output will be on when Rx is less than 1 kilohm.

The OhmslVolts/ Amps logiC input is a ternary, or 3-level
input. This input is internally tied to the common voltage
through a high-value resistor, and will go to the middle, or
"Volts" state, when not externally connected. When connected to V -, approximately 5 p.A of current flows out of
the input. In this case, the logiC level is the "Amps", or low
state. When connected to V +, about 5 p.A of current flows
into the input. Here, the logic level is the "Ohms", or high
state. For other pins, see Table 2.

Display Drivers

Common Voltage
The analog and digital common voltages of the ICL7149
are generated by an on-chip resistor/zener/diode combination, shown in Figure 12. The resistor values are chosen so
the coefficient of the diode voltage cancels the positive
temperature coefficient of the zener voltage. This voltage is
then buffered to provide the analog common and the digital
common voltages. The nominal voltage between V+ and
analog common is 3V. The analog common buffer can sink
about 20 mA, or source 0.01 mA, with an output impedance
of 10 ohms. A pullup resistor to V+ may be used if more
sourcing capability is desired. Analog common may be used
to generate the reference voltage, if desired.

Table 2: Ternary Inputs Connections
Pin
Number

y+

OPEN
or COM

y-

17

mA

p.A

Test

18

Ohms

Volts

Amps

19

HiO/DC

LoO/AC

Test

20

Hold

Auto

Test

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typk;sJ_ ""ve betJn _ _ but.,. not __

2-87

n
I'"

......
CD

~

ICL7149

i

COMPONENT SELECTION

......

For optimum performance while maintaining the low-cost
advantages of the ICL7149, care must be taken when selecting external components. This section reviews specifications and performance effects of various external components.

Integrator Capacitor, CINT
As with all dual-slope integrating convertors, the integration capacitor must have low dielectric absorption to reduce
linearity errors. Polypropylene capacitors add undetectable
errors at a reasonable cost, while polystyrene and polycarbonate may be used in less critical applications. The
ICL7149 is designed to use a 3.3 nF (0.0033 ,...F) CINT with

an oscillator frequency of 120 kHz and an RINTV of 10 megohms. With a 100 kHz oscillator frequency (for 50 Hz line
frequency rejection), both CINT and RINTV affect the voltage
swing of the integrator. Voltage swing should be as high as
possible without saturating the integrator, which occurs
when the integrator output is within 1V of either V + or V - .
Integrator voltage swing should be about ± 2V when using
standard component values. For different RINTV and oscillator frequencies the value of CINT can be calculated from:
CINT =

(Integrate Time) x (Integrate Current)
(Desired Integrator Swing)
(10,000

x 2 x Oscillator Period) x O.4V/RINTV
(2V)

ROEINT

DEINTAZ

INT I

LOW I
RINTI

9.9.0.
YREF
HIGH I

y+
0.1.0.

COMMON

6.7Y

COMMON

Y-t::====~

=
=
=

T (INT)(AR)(AZ)
AR = AUTO RANGE CHOPPER
AZ AUTOZERO
INT INTEGRATE

_________--1
0094-7

Figure 7: Detailed Circuit Diagram for DC Current Measurement

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but 8(9 not tested.

ICL7149

100 kD.

20MD.

.ltll.fItr---------.........-=i

YINo-....
o-400YAC
0-1000 Hz

100kD.

50kD.

20MD.

ICL7149

COM o-_ _ _...._ _ _ _ _ _ _ _~.....- - - - - - - - - -......
l0"'l COMMON
0094-8

NOTE: Diodes are low-leakage 10100.

Figure 8: AC Voltage Measurement Using Optional Averaging Circuit
2.2~F

...cr
YIN
0-400VAC
50-1000Hz

y+

10MD.

12

ICL7149

y+

4.99 kD.

INT(V/D.)

V30kD.
10

COM

COMMON
0094-9

Figure 9: AC Voltage Measurement Using Optional RMS Converter Circuit

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIeD WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical va/uss have been characterized but are not tested.

2-89

.......~

.D~DI!..

ICL7149

...g
ROEINT
ROEINT

INT

AZ

Y/.o.

RX
LO.o.
RKNOWN 1
HI.o.

T=INT+ OEINT
AZ = AUTOZERO
INT = INTEGRATE

RKNOWN2
COMMON

0094-10

Figure 10: Detailed Circuit Diagram for Ratiometric Ohms Measurement
LO OHM r

-------

- - - - - - .,

RKNOWN

RUNKNOWN

BEEPER OUTPUT

Rx

I
COM

I

.

Vx = 100 mY

--

-- --- - .

0094-11

Figure 11: Continuity Beeper Drive Circuit

NOTE: The ICL7139 contains a comparator that is enabled on the lowest ohms range. It trips at approximately y. of the full scale value of that range and enables
the beeper driver to OSCillate (between V- and V+) at 2 kHz. The beeper driver is capable of driving a piezo-electric transducer. The beeper output
response is independent of the state of the conversion; therefore appears instantaneous to the user. Some applications may require a 150 pF capacitor
between pin 4 and pin 8 to insure a sharp onloff continuity detection.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICL.E OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLieD WARRANTies OF

MERCHANTABILlTX, AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but ar8 not tested.

2·90

ICL7149
The ideal CAZ is a low leakage polypropylene or Teflon
capacitor. Other film capacitors such as polyester, polystyrene, and polycarbonate introduce negligible errors. If a few
seconds of settling time upon power-up is acceptable, the
CAZ may be a ceramic capacitor, provided it does not have
excessive leakage.

Integrator Resistors
The normal values of the RINT v and RINT I resistors are
10 megohms and 1 megohm respectively. Though their absolute values are not critical, unless the value of the current
sensing resistors are trimmed, their ratio should be 10:1,
within 0.05%. Some carbon composition resistors have a
large voltage coefficient which will cause linearity errors on
the 400V scale. Also, some carbon composition resistors
are very noisy. The class" A" output of the integrator begins
to have nonlinearities if required to sink more than 70 ",A
(the sourcing limit is much higher). Because RINT v drives a
virtual ground point, the input impedance of the meter is
equal to RINT V.

Ohms Measurement Resistors
Because the ICL7149 uses a ratiometric ohms measurement technique, the accuracy of ohms reading is primarily
determiner:! by the absolute accuracy of the RKNOWNI and
RKNOWN2. These should normally bEllO kilohms and 1 meg6hm, with an absolute accuracy of at least 0.5%.

Current Sensing Resistors

Deintegration Resistor, ROEINT

The 0.1 ohm and 9.9 ohm current sensing resistors convert the measured current to a voltage, which is then measured using RINT I. The two resistors must be closely
matched, and the ratio between RINT I and these two resistors must be accurate-normally 0.5%. The 0.1 ohm resistor must be capable of handling the full scale current of 4
amps, which requires it to dissipate 1.6 watts.

Unlike most dual-slope AID converters, the ICL7149 uses
different resistors for integration and deintegration. RDEINT
should normally be the same value as RINTV, and have the
same temperature coefficient. Slight errors in matching may
be corrected by trimming the reference voltage.

Autozero Capacitor, CAZ

Continuity Beeper

The CAZ is charged to the integrator's offset voltage during the autozero phases, and subtracts that voltage from
the input Signal during the integrate phases. The integrator
thus appears to have zero offset voltage. Minimum CAZ value is determined by: 1) Circuit leakages; 2) CAZ self-discharge; 3) Charge injection from the internal autozero
switches. To avoid errors, the CAZ voltage change should
be less than 'Ao of a count during the 10,000 count clock
cycle integration period for the 400 mV range. These requirements set a lower limit of 0.047 ",F for CAZ but 0.1 ",F
is the preferred value. The upper limit on the value of CAZ is
set by the time constant of the autozero loop, and the line
cycle time period allotted to autozero. CAZ may be several
10s of microfarads before approaching this limit.

The Continuity Beeper output is designed to drive a piezoelectric transducer at 2 kHz (using a 120 kHz crystal), with a
voltage output swing of V+ to V-. The beeper output off
state. is at the V+ rail. When crystals with different frequencies are used, the frequency needed to drive the transducer
can be calculated by dividing the crystal frequency by 60.

Display
The ICL7149 uses a custom, duplexed drive display with
range, polarity, and low battery annunciators. With a 3 volt
peak display voltage, the RMS ON voltage will be 2.37V
minimum; RMS OFF voltage will be 1.06V maximum. Because the display voltage is not adjustable, the display
should have a 10% ON threshold of about 1.4V. Most

~~~--------------~--------------~------------v+
+

3V

ANALOG
COMMON

(PIN 10)

LO BAT

~----------------~~----------~~----t-~--V0094-12

Figure 12: Analog and Digital Common Voltage Generator Circuit

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are not tested.

2-91

II

.d... ICL7149
GI
'II'

-

display manufacturers supply a graph that shows contrast
versus RMS drive voltage. This graph can be used to determine what the contrast ratio will be when driven by the
ICL7149. Most display thresholds decrease with increasing
temperature, and the threshold at the maximum operating
temperature should be checked to ensure that the "off"
segments will not be turned "on" at high temperatures.

Applications, Examples, and Hints
A complete autoranging 3% digit multi meter is shown

in
Figure 16. The following sections discuss the functions of
specific components and various options.

Meter Protection
The ICL7149 and its external circuitry should be protected against accidental application of 11 0/220V AC line voltages on the ohms and current ranges. Without the necessary precautions, both the 7149 and its external components could be damaged under such fault conditions. For
the current ranges, fast-blow fuses should be used between
S5A in Figure 16 and the 0.1 ohm and 9.9 ohm shunt resistors. For the ohms ranges, no additional protection circuitry
is required. However, the 10 kilohm resistor connected to
pin 7 must be able to diSSipate 1.2W or 4.BW for short periods of time during accidental application of 11 OV or 220V
AC line voltages respectively.

Crystal
The ICL7149 is designed to use a parallel resonant
120 kHz or 100 kHz crystal with no additional external components. The Rs parameter should be less than 25 kilohms
to ensure oscillation. Initial frequency tolerance of the crystal can be a relatively loose 0.05%

Switches
Because the logic input draws only about 5 ",A, switches
driving these inputs should be rated for low current, or "dry"
operations. The switches on the external inputs must be
able to reliably switch low currents, and be able to handle
voltages in excess of 400V AC.

Reference Voltage Source
A voltage divider connected to V+ and Common is the
simplest source of reference voltage. While minimizing external component count, this approach will provide the
same voltage tempco as the ICL7149 Common-about
100 PPM/'C. To improve the tempco, an ICLB069 bandgap
reference may be used (see Figure 15). The reference voltage source output impedance must be ,;; RDEINT/4000.

330K

0094-13

Figure 13: Internal Oscillator Circuit Diagram

VPEAK

BACKPLANE

~
.
VOPEAK/2

V+
YAMS

~ ~ VPEAK

ON

YAMS

~ ~ VPEAK

OFF

DCOt.4

SEGt.4ENT ON

SEGt.4ENT OFr

1 . .___. .

VPEAK ~ 3V ± 10%

RMS ON -+ 2.37V
RMSOFF -+ 1.06V

--.J
VpEAK

(VOLTAGE ACROSS ON SEGMENT)

a
VSEGMENT ON
-2VpEAK

~

_ VPEAK

(VOLTAGE ACROSS OFr SEGt.4ENT)

~0

VSEGMENTOrr -

-VPEAK

0094-14

Figure 14: Duplexed LCD Drive Waveforms
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vsJu8S have been characterized but are not tested.

2-92

.D~OI!..

ICL7149

The rollover error causes the width of the + 0 count to be
larger than normal. The ICL7139 will thus read zero until
several hundred microvolts are applied in the positive direction. The ICL7139 will read -1 when approximately
-100 /JoV are applied.
The rollover error can be minimized by guarding the Triple
Point and CAZ nodes with a trace connected to the CINT
pin, which is driven by the output of the integrator. Guarding
these nodes with the output of the integrator reduces the
stray capaCitance to ground, which minimizes the charge
error on CINT and CAZ. If possible, the guarding should be
used on both sides of the PC board.

Printed Circuit Board Layout
Considerations
Particular attention must be paid to rollover performance,
leakages, and guarding when designing the PCB for a
ICL7149-based multimeter.

Rollover Performance, Leakages,
and Guarding
Because the ICL7139 system measures very low currents, it is essential that the PCB have low leakage. Boards
should be properly cleaned after soldering. Areas of particular importance are: 1) The INT v/n and INT I Pins; 2) The
Triple Point; 3) The ROEINT and the CAZ pins.
The conversion scheme used by the ICL7139 changes
the common mode voltage on the integrator and the capaci·
tors CAZ and CINT during a positive deintegrate cycle. Stray
capacitance to ground is charged when this occurs, remov·
ing some of the charge on CINT and causing rollover error.
Rollover error increases about 1 count for each picofarad of
capacitance between CAZ or the Triple Point and ground,
and is seen as a zero offset for positive voltages. Rollover
error is not seen as gain error.

While the ICL7149 has excellent rejection of line frequency noise and pickup in the DC ranges, any stray coupling
will affect the AC reading. Generally, the analog Circuitry
should be as close as possible to the ICL7149. The analog
circuitry should be removed or shielded from any 120V AC
power inputs, and any AC sources such as LCD drive waveforms. Keeping the analog circuit section close to the
ICL7149 will also help keep the area free of any loops, thus
reducing magnetically coupled interference coming from
power transformers, or other sources.
10MEG

10MEG
1 MEG

~

ICL8069~ ~

~

L

....
....

U»

Stray Pickup

- .... V+
10K

P

TRIPLE POINT
DEINTEGRATE
INTEGRATE VOLTjOHM
INTEGRATE CURRENT

EXTERNAL
REFERENCE

REFERENCE INPUT
ANALOG COMMON
0094-15

Figure 15: External Voltage Reference Connection to ICL7149

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPUED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AJI typical values have besn charscterized but arB not tested

2-93

•

....

: ICL7149

~

9

INPUTS
y/.n

10 M.n 7
1 t.1.n 8
1 t.1.n 11
A
S5A

LO BAT

DISPLAY
DRIYE
OUTPUTS

10 t.1.n12

AC

LO.n
HI.n

BEEPER

INT(I)

mAY#A

-3999

16

y+ 4

9.9.n

k.nM.n

PIN 4

ICL7149

10 k.n
1#F

COt.1t.10N

0.1.n
2W

10
18

S4B

y-

COt.1MON

YREF
y/.n/A
HI.n-DC/LO.n-AC

17

mA/#A

HOLD

ICL8069
6
19

S2

20

S3

.-J
.-J

......- - 4_ _-+ PIN 10
Y+
Y+

mA
0094-16
52 Closed: Hill·DC
53 Closed: Hold Reading

Figure 16: Basic Multlmeter Application Circuit for ICL7149
NOTE 1: Crystal is a 5tatek CX-1V type.
2: Multimeter protection components have not bean shown.

3: Display is from LXD. part number 38D3R02H.

4: Beeper is from muRata, part number PKM24-4AO.

0094-17

Figure 17: PC Board Layout

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typk;sJ vsluss have b86n chsracterized but are not tested.

2-94

ICL7182
101 Segment LCD Bargraph
AID Converter

."'."~\"<,,c

GENERAL DESCRIPTION

The Intersil ICL7182 is a complete an g- q,~T converter (ADC) that directly drives a mUltiple~1)~uid crystal
display (LCD). Included are a charge-balanced ADC, a
2.56V bandgap reference, display decode and driver, and a
50 kHz oscillator. Only a display and three passive components are required for a complete analog bargraph.
The fully differential analog and reference inputs may be
operated anywhere between and including the supply rails.
This allows sensing either ground-referenced Signals or
bridge configurations. Linearity and zero offset errors are
guaranteed to be less than 0.5% for a 1V full-scale input.
The full-scale differential input range is 200 mV to 1.1V.
The low drift 50 ppm/'C reference is trimmed to 1.5%
accuracy and, when used with a simple resistor divider, can
set the full-scale input voltage. The reference, when used
with an IntersillCL7660, extends the operating supply range
from 3V to 40V and allows sensing input signals below
ground.
The backplane and segment drivers supply the LCD with
the proper waveforms to create a discrete series of segments forming a 101 segment bar which is proportional to
the input voltage, with a plus or minus annunciator to indicate the polarity. In addition, three independent TIL controllable annunciators are provided for limit or unit indication.
The bargraph multiplexing scheme provides duplex contrast
ratio and allows the complete system to be placed in a standard 40 pin DIP. The LCD operating voltage is externally set
to adjust contrast for a range of fluid types and temperature.
The internal oscillator requires no external components
and establishes the conversion rate and backplane clock
frequency. The nominal conversion rate of 25 per second
can be easily changed between 15 to 40 conversions per
second by adding a Single capacitor or overdriving the oscillator.

•
•
•
•
•
•

1% Resolution ••• 100 Data Segments Plus Zero
No Missing Segments Guaranteed
Single 5V Supply Operation
Only Three Passive Components Required
True Differential Input and Reference
Direct LCD Display Drive Provides Duplex Contrast
Ratio
Overrange and Polarity Indication
Three User Defined Annunciators-Easily
Expandable
Precision On-Chip Reference ••• 50 ppml'C
Low Average Power Consumption ••• 1.8 mW
40 Pin DIP or 44 Pin Surface Mount Package
Extended Temperature Range Operation

T5

SEa.

Ax

SEGy

Ay

SEG>

Ax

SIGN

Tl

SEG7

OSC

SEGS

vee

SEG5

VRout

SEG4

REF HI

SEG3

REFLO

SEG2

INHI

SEGI

INLO

ORDERING INFORMATION
Part
Number

•
•
•
•
•
•

SEGO

COMMON

BPI

VSS

BP2

VDS

BP3
BP4

Temperature
Range

Package

BP13
BP12

BPS

ICL7182CPL

O'Cto +70'C

40 Pin Plastic

BPll

BPe

ICL71821PL

- 25'C to + 85'C

40 Pin Plastic

BPS

°ICL7182CM44

O'Cto +70'C

BP7

BPIO
21

BPS

44 Pin Plastic
0093-1

'Consult factory for details.

Figure 1: Pin Configuration

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
310675-001
NOTe: All typical VS//J9S hsve besn characterized but are not tested.

2-95

= ICL7182

.......

W ABSOLUTE

MAXIMUM RATINGS
Operating Temperature Range .......•.. - 2S·C to + as·c
Continuous Total Power Dissipation (TA = 2S·C)
40 Pin DIP Plastic Package ................... SOO mW
44 Pin CM Plastic Package ................... 37S mW

Supply Voltage (Vee to Vss) ........................ 1OV
Supply Voltage (Vee to Vos) ........................ 11 V
Display Drive Pin Voltage ...... (Vee + 0.3V) to (Vos -0.3V)
Analog or Reference Inputs .... (Vee + 0.3V) to (Vss - 0.3V)
Com, Osc, Ax, Ay,
Az, Tl, TS Pins ............. (Vee + 0.3V) to (Vss-0.3V)
Reference Output Current ......................... a rnA
Lead Temperature (Soldering, 10 sec) .............. 300·C
Storage Temperature Range ........... - 6S·C to + IS0·C

NOTE: Sfr9sses above those listed under ''Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended peri·
ods may affect device reliability.

ELECTRICAL CHARACTERISTICS Unless otherwise stated: Vee = S.OV, VSS = VOS = GND, TA = 2S·C,
VREF = 1.000V, VINeM = VREFeM = 2.SV, pin 6 open (Note 1)
Parameter
Zero Input Reading
Unadjusted Gain Error
Linearity Error
Rollover Error
Conversion Time
Display Update Rate
Input Referred Noise
DC Power Supply Rejection

Limits

Test Conditions

Units

Min

Typ

Max

-0
-1
-0.63
-O.S

±O
±O
±0.2
±0.1
400
2S
SOO
0.02

+0
+1
+0.63
+O.S

0.1
1.1

VIN = 1.0V (Note S)

0.02
1.0
1.3

SegslV
V
nA

VREFeM = O.SV to 4.SV
(Note 6)

0.01
6

0.1

SegslV
nA

2.S60
SO
1.3
20

2.S90
200
S

a

2

V
ppml"C
0
p.A
mA
p.V

VIN = O.OV
VIN = VREF
(Note 2)
VIN = - VREF (Note 3)

(Note 4)
Vee = 4.S to 6.OV

0.3

Segs
Segs
Segs
Segs
p.s
Hz
p.V
SegslV

ANALOG INPUT
Common Mode Rejection Ratio
Differential Mode Input
Average Input Current

VINeM = OV to SV, VIN "" OV

REFERENCE INPUT
Common Mode Rejection Ratio
Average Input Current
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
Output Impedance
Current Into VRout Pin
Current Out of VRout
Output Noise

Vee - VRout, lout = 0 p.A
- 2S·C < TA < as·c, lout = 0 p.A
lout = + 10 p.A to -2 mA

2.S20

10
0.1 Hz to 10 Hz (Note 4)

110

(Note 6)
(Note 6)
Guaranteed by PSRR

4.S

3S0
I.S
S.O

SOO
2.0
6.0

p.A
mA
V

Osc Pin Open
Osc Pin Open

26
2S

SI
SO

72
70

kHz
Hz

-SO

70
±10
60

200
SO
120

kO
mV
p.A

POWER SUPPLY
Supply Current Average
Supply Current Peak
Supply Voltage Range
OSCILLATOR
Oscillator Frequency
Backplane Frequency
DISPLAY DRIVE
Display Output Impedance
DC Component of Display
Vos Supply Current

Vee - Vos = 3Vt07V
Vee - Vos = 3Vt07V
Vee - Vos = 3V to 7V (Note 7)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical

Va/USB

have be9n characterized but are not tested.

2-96

ICL7182
ELECTRICAL CHARACTERISTICS (Continued) Unless otherwise stated: Vee =
= 25'C, VREF = 1.000V, VINeM = VREFeM = 2.5V, pin 6 open (Note 1)

5.0V, VSS

=

VOS

=

GND,

TA

Parameter

Limits

Test Conditions

Units

Typ

Max

0.001

0.8
+1

Min
ANNUNCIATOR INPUTS
Input High Voltage
Input Low Voltage
Input Leakage

Operating Temp Range
Operating Temp Range
Operating Temp Range

2.4
-1

NOTE 1: The differential mode input voltages are defined as: VIN ~ (IN HI - IN LO) and VREF ~ (REF HI
and VREFCM, is defined as the average differential input voltage with respect to ground.

-

REF

V
V
IJ-A

LO). The common mode input voltage,

VINCM

2: The linearity error is the deviation from a straight line which passes through negative full scale and postive full scale readings.
3: The rollover error is defined as the difference in reading for equal positive and negative inputs near full·scale.
4: Peak to peak value not exceeded 95% of the time (±2 standard deviations).
5: Defined as the average current flowing into the input with a 1.0

/,F

capacitor across

VIN

or VREF inputs and the common mode voltage at

Va vee.

6: The average supply current is measured with a supply bypass capacitor and annunciator inputs tied to VSS.
7: The supply current for

VDS

flows from the

VCC

pin.

PIN DESCRIPTION AND FUNCTION
Pin No.

Symbol

Description

1

T5

Test pin #5, buffered OSCillator frequency divided by two that can typically source and sink 2 mA.

2

Ax

Annunciator Segx select, low turns on Segx, high turns off Segx.

3

Ay

Annunciator Segy select, low turns on Segy, high turns off Segy.

4

Az

Annunciator Segz select, low turns on Segz, high turns off Segz.

5

T1

Test pin # 1, normally left open or tied to Vss.

6

Osc

50 kHz free running oscillator control and clock input pin. The internal oscillator may be
overdriven by a 30 to 80 kHz external clock driving pin 6, or the free running frequency can be
reduced by adding an external capaCitor between pin 6 and Vee.

7

Vee

Positive supply voltage.

8

VRout

Bandgap reference buffered output, down 2.56V from Vee.

9

REFHI

Positive Reference Input.

10

REFLO

11

INHI

Positive Analog Input.

12

INLO

Negative Analog Input.

13

Common

Negative Reference Input.

Internally generated voltage which is typically within ± 50 mV of Yo (Vee - Vss) and has 1.4 kO
output impedance. This pin is normally left open or bypassed with a 0.1 IJ-F capaCitor to signal
ground.

14

Vss

Negative supply voltage, normally ground.

15

Vos

Display negative voltage, establishes the pk-pk display drive.

16-28

BP13-BP1

29-36

SegO-Seg7

37

Sign

Positive sign segment driver.

38

Segz

Annunciator driver selected by Az.

39

Segy

Annunciator driver selected by Ay.

40

Segx

Annunciator driver selected by Ax.

LCD backplane drivers.
LCD segment drivers.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: All typical valU8S have b8en characterized but 8r9 not test9d.

2-97

......... ICL7182

.D~On..

~

CD

!i

,------------

Ax

Ay

A.

I

SEGX

OSC

SEGY
ANNUN·
CIATOR
DRIVERS

SEGZ
SIGN

I
I
VCC

SEGMENT
DECODE
AND
DRIVE

SOK
LCD
PHASE
GENERATOR
SOK
15
VDS
MSB

BACKPLANE
DECODE
AND
DRIVE

29-36 1
SEGO-SEG7

16-28
BP1-BP13

13

I

REFHI~
REF

n

LO~I-.:C~-(S()----'"
I

I

IN HI
IN LO LJ--~:r-:;S..
COMMON
VCC

STATE
MACHINE
VRout

STDBY

VSS

I
1

I
I
L _____ - -- - - - - - - -

I
I

______ ..J

0093-2

Figure 2: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been ch8rsctsrlzed but are not testBd.

2·98

IID~DIL

ICL7182

P
...
...

CD
N

ANNUNCIATORS
SIGN
OVERRANGE

lOG-=-

+5Vo-~~------~~

90

==

IN Hlo----------------\

GNDO------------+--~

20-=-

10

==

O'="
0093-3

Figure 3: ICL7182 using the internal reference.
Values shown are for 1.000V full-scale, 25 readings
per second, single 5V supply.

TYPICAL PERFORMANCE CHARACTERISTICS

C

s.
c

Average Analog Input Current vs.
Frequency and Common Mode Voltage

Average Reference Input Current vs.
Frequency and Common Mode Voltage

4 VIN _ O.OSOV
VREF
1.00V

18
VIN
0.050V
16 VREF
1.0iV

=

~

.'"

0

-1

I! -2

~

----r=
VCM

U

.5

--- -

VCM =

::I

5<>.

I

-3
-4

20

I!)!..

.....-

--

!

~

"

u

5<>.

I

.
.'"

.5

~M=5V

30

40

50

60

70

I!
~

-.....
80

./
. / .....

C 14

2.5V

I i"""- 'I

=
=

./

12

VCM = 4V./

10

./ ~

8

~
~~

6

.,.

"""..........
VCM = OV

'7

~

2

20

90

.JI'

30

40

50

60

70

80

90

Oscillator Frequency (kHz)

Oscillator Frequency (kHz)

0093-5

0093-4

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANnES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not testBd.

2·99

=
... ICL7182

...
i!

TYPICAL PERFORMANCE CHARACTERISTICS

(Continued)

Oscillator Frequency VB. Temperature
and Supply Voltage

Oscillator Frequency VS. Pin #6 Capacitor

I

24

25

23
22

4

i ~:
~

18

C5

12

........
......

:"

1

~

~

~

W

~

m

H

=

4.5V

L. ~

,I\-. vee = 5.OV

I........
5

-

~

glW

["'0..

o

5.5V~

"""~vee
V~ rr"

2
~

114
10

vee =

7

~40 -m

U

~

Pin .. Capacitance (pF)

0

20

40

80

80

100

Temperatura (OC)

0093-6

0093-7

Backplane Output Impedance VS.
Vos and Temperature

Annunciator Input Threshold VS.
Power Supply Voltage

~ 110

--'-

B 100

i1 :0 i\--'
0

\'

70

a
!

./

VT= 85·
...,.
~ ....... ...... TA = 25~
~"'" ~.l
TA =,:;(.'

50

1

'"

,~

60

40

./
./

,

~::r-

Iii 30

2345678

./

4.5

Display Voltage (VCC-VDS) (Volta)

5.0

5.5

8.0

Power Supply Voltage (VoIIs)

0093-8

Reference Bias Current VS.
Breakdown Voltage

30mA

~
H 2.580

~

15 10mA
~

0093-9

a 1mA
i 300uA
§ 100uA

J ~uA

~

i""'"

10UA
0.5

1.0

1.5

2.0

Referance Output Voltage WAr

2.5

2.575

i

2.570

"

2.560

I

V

3uA 0

~

t
I

3mA

3.0

vee (Vo1Is)

Reference Output va.Temperature

2.565

~

2.555

2.550
2.545

~

~

V

/

2.540
-55

-25

o

25

50

75

100

125

Temperature (OC)

0093-11

0093-10

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDmON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE· AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, ·El

-1
~)~C~~l
+

I

I,

~1
1

~1~
1

0--0

VSS

~

POINTS
ANNUNCIATORS,

ETC.

~1
I

D-T

LC~O..J

VDS

ND

0093-22

Figure 13: Using Exclusive 'OR' Gate for additional annunciator drivers.

V+

GND
TO DISPLAY
BACKPLANES

0093-23

Figure 14: 7182 measuring ratlometrlc values of Quad Load Cell.
The resistor values within bridge are determined by the desired sensitivity.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

2·107

:: ICL7182
.......

g APPLICATIONS

(Continued)

- rVOO

V+
5.0V
R,
lOOK

R,
2.7M

17

4

L~

8

"'7
ICM
7555
U'

~

3

3

11 IN HI

1

U2

NC

0---1
INPUT

2

FROM

SW'<"'---o-

C, ...
',F

v-

,

'f

S ENSOR

2

'50K

R,
lOOK

ICL

+ 7621

R,

C,
220pF

VOO

100pF
2
C

w

R,
11M

ICL
7182

C,
0.47F

U3

NO

12

J

Roo

I/'V'"
::s 2:: LEOl
OPTIONAL

R"
4K
OPTIONAL

1M

~5
7
ICL
7621

CUT OFF 2N

"'-L

222r

r-----a

R,
12K

Roo
400K

R,
'OK

R
lOOK

VROlJT

9 REF HI

U2~6

()
IGNITION

.Y!lf!.

.Y.~

~

IN LO

'---

10 REF LO

R,
VSS

R,
12K

12K

1'4

GND

v0093-24

Vo =
VIN

1/RC
S + 1/R3C3

Ic = _ _
1_
211'R3C3

Switch SPST
@

Period

600

10

100 ms

1000

16.7

60ms

5000

SW1 Momentary
VIN = 264 mV
4 Stroke V8

Hz

RPM

10,000

83

No. of

Events

Strokes

Cylinders

Per Cycle

Per Cycle

12 ms

166,7

6ms

5000 RPM

1

0.5

4

4

2

4

6

3

4

8

4

4

Figure 15: Tachometer with Set Point

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not test9d.

2-108

ICL7182
APPLICATIONS

(Continued)
V+
ANNUNCIATORS
SIGN
OVERRANGE

VDD(7)
R,

4K
L-

R,

~

REF LO(10)
90

R

ICL7182
R,

-------------------

100-=-

REFHI(9)

~;- INHI(ll)

~

==
··

•

·
-------------------------------

20-=~ VROUT(9)

IN LO(12)

+

~AD580

10"="
R.

=

24K

VSS(14)

O"="

V0093-25

Figure 16: Basic digital thermometer, Celsius and Fahrenheit scales.
This Vos pin can be connected as shown in Figure 11.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valUBs haV9 been characterizsd but are not tssfed

2·109

Section 3 -

AID Converters
~p Type
ADC0802 ............... 3-1
ADC0803 ............... 3-1
ADC0804 ............... 3-1
ICL7104/1CL8052 ...... 3-19
ICL7104/1CL8068 ...... 3-19
ICL71 09 ............... 3-39
ICL7112 ............... 3-58
ICL7115 ............... 3-60
ICL7135 ............... 3-74

ADC0802-ADC0804
8-Bit JLP-Compatible
AID Converters
GENERAL DESCRIPTION

FEATURES

The ADCOS02 family are CMOS S-bit successive approximation AID converters which use a modified potentiometric
ladder. and are designed to operate with the SOSOA control
bus via three-state outputs. These converters appear to the
processor as memory locations or 1/0 ports. and hence no
interfacing logic is required.
The differential analog voltage input has good commonmode-rejection. and permits offsetting the analog zero-input-voltage value. In addition. the voltage reference input
can be adjusted to allow encoding any smaller analog voltage span to the full S bits of resolution.

• 80C48 and 80C80/85 Bus Compatible - No
Interfacing Logic Required
• Conversion Time < 100,...s
• Easy Interface to Most Microprocessors
• Will Operate In a "Stand Alone" Mode
• Differential Analog Voltage Inputs
• Works With Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• OV to 5V Analog Voltage Input Range (Single
Supply)
• No Zero-Adjust Required

+ 5V

ORDERING INFORMATION
Part
Number

Error

Temperature
Range

Package

ADCOS02LCN
ADCOS02LCD
ADCOS02LD

± '12 bit no adjust
± % bit no adjust
± 1 bit no adjust

O'Cto +70'C
-40'C to + S5'C
-55'C to + 125'C

20 pin Plastic DIP
20 pin CERDIP
20 pin CERDIP

ADCOS03LCN
ADCOS03LCD
ADCOS03LD

± '12 bit adjusted full-scale
± % bit adjusted full-scale
± 1 bit adjusted full-scale

O'Cto +70'C
-40'Cto +S5'C
- 55'C to + 125'C

20 pin Plastic DIP
20 pin CERDIP
20 pin CERDIP

ADCOS04LCN
ADCOS04LCD

± 1 bit no adjust
± 1 bit no adjust

O'Cto +70'C
-40'Cto +S5'C

20 pin Plastic DIP
20 pin CERDIP

cs

1
2
RD
3
WR
5
INTR
11
DB,
12
DBo
13
Oils
14
Os.
15
DB,
16
DB.
17
DB,
18
DBo

Y+

cs u:~~ V+ORVREF

-;-0.

CLKR
eLKIN
AID
I.INI +)
1.11«-1

4

10k

...!..o}
2..0_
8

8

AD [!
WR [!

d~

CLK IN

f·BIT RESOLUTION
DIFF
OYER ANY DESIRED
INPUTS ANALOG INPUT
YOLTAGE RANGE

AGND
YREFI2

I.INI+I

~

I.INI-)

[!:

ADC0804

AGND

':'

DGND
0334-1

Figure 1: Typical Application

ADC0802-

~
YREFI2 [!:

..!..o YREF121

DGND~

INTR

~
[!

~

~

CLKR

~

DBo (LSB)

1m DB,
1m DB.
~

DB,

~
~

DBs

~

DBo

~

DB, (MSB)

Os.

TOP VIEW
0334-2

(Outline dwg. CD, CN)
Figure 2: Pin Configuration

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been charact9rizsd but arB not f9stiJd.

3-1

•

~

co
o

§
I

.D~Dn.

ADC0802-ADC0804
iii) 2

READ

C\I

o

"1" = RESET SHIFT REGISTER
"0" - BUSY AND RESET STATE

CO

i

RESET

INPUT PROTECTION
FOR ALL LOGIC INPUTS

j::

INPUT

CLK

TOINTERNAL
CIRCUITS
BV .. 30V

V+
(VAEF)

START
CONVERSION

20

J"L

0".--....----+1

VAEFI2

LADDER
AND
DECODER

I+++-+- 1kO). If input bypass capacitors are necessary for noise filtering and high
source resistance is desirable to minimize capacitor size,
the effects of the voltage drop across this input resistance,
due to the average value of the input current, can be compensated by a full-scale adjustment while the given source
resistor and input bypass capacitor are both in place. This is
possible because the average value of the input current is a
precise linear function of the differential input voltage at a
constant conversion rate.

R
VREF/2

9

,R

~}-

II DECODE

I I
DIGITAL
CIRCUITS

•

H I
ANALOG
CIRCUITS

~}-

Input Source Resistance
Large values of source resistance where an input bypass
capacitor is not used, will not cause errors since the input
currents settle out prior to the comparison time. If a lowpass filter is required in the system, use a low-value series
resistor (';; 1k!l) for a passive RC section or add an op amp
RC active low-pass filter. For low-source-resistance applications, (';; 1k!l), a 0.1,..F bypass capacitor at the inputs will
minimize EMI due to the series lead inductance of a long
wire. A 100!l series resistor can be used to isolate this capacitor (both the Rand C are placed outside the feedback
loop) from the output of an op amp, if used.

AGND 8

DGN,!;';'O

-==
0334-22

Figure 7: The VREFERENCE Design on the

Ie

Notice that the reference voltage for the IC is either 'fa of
the voltage which is applied to the V+ supply pin, or is
equal to the voltage which is externally forced at the VREFI
2 pin. This allows for a pseudo-ratiometric voltage reference
using, for the V+ supply, a SV reference voltage. Alternatively, a voltage less than 2.SV can be applied to the VREFI
2 input. The internal gain to the VREF/2 input is 2 to allow
this factor of 2 reduction in the reference voltage.
Such an adjusted reference· voltage can accommodate a
reduced span or dynamic voltage range of the analog input
voltage. If the analog input voltage were to range from O.SV
to 3.SV, instead of OV to SV, the span would be 3V. With
O.SV applied to the VIN(-) pin to absorb the offset, the reference voltage can be made equal to % of the 3V span or
1.SV. The AID now will encode the VIN( +) signal from O.SV
to 3.SV with the O.SV input corresponding to zero and the
3.SV input corresponding to full-scale. The full 8 bits of resolution are therefore applied over this reduced analog input
voltage range. The requisite connections are shown in Figure 8. For expanded scale inputs, the circuits of Figures 9
and 10 can be used.

Stray Pickup
The leads to the analog inputs (pins 6 and 7) should be
kept as short as possible to minimize stray signal pickup
(EM I). Both EMI and undesired digital-clock coupling to
these inputs can cause system errors. The source resistance for these inputs should, in general, be kept below Sk!l.
Larger values of source resistance can cause undesired signal pickup. Input bypass capacitors, placed from the analog
inputs to ground, will eliminate this pickup but can create
analog scale errors as these capcitors will average the transient input switching currents of the AID (see Analog Input
Current). This scale error depends on both a large source
resistance and the use of an input bypass capacitor. This
error can be compensated by a full-scale adjustment of the
AID (see Full-Scale Adjustment) with the source resistance and input bypass capacitor in place, and the desired
conversion rate.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

3-11

g ADC0802-ADC0804
CD

o

g
C
I

(\I

o

digital output code. In absolute conversion applications,
both the initial value and the temperature stability of the
reference voltage are important accuracy factors in the operation of the AID converter. For VREF/2 voltages of 2.5V
nominal value, initial errors of ± 1OmV will cause conversion
errors of ± 1LSB due to the gain of 2 of the VREF/2 input. In
reduced span applications, the initial value and the stability
of the VREF/2 input voltage become even more important.
For example, if the span is reduced to 2.5V, the analog
input LSB voltage value is correspondingly reduced from
20mV (5V span) to 10mV and 1LSB at the VREF/2 input
becomes 5mV. As can be seen, this reduces the allowed
initial tolerance of the reference voltage and requires correspondingly less absolute change with temperature variations. Note that spans smaller than 2.5V place even tighter
requirements on the initial accuracy and stability of the reference source.
In general, the reference voltage will require an initial adjustment. Errors due to an improper value of reference voltage appear as full-scale errors in the AID transfer function.
IC voltage regulators may be used for references if the ambient temperature changes are not excessive.

VREF
(5V)

CD

§

> .....,.,.,,..,..,..... TO
VREF/2

C
~r-~

__

~~~~

____________-.TO
VIN(-)

0334-23

Figure 8: Offsetting the Zero of the ADC0802 and
Performing an Input Range (Span) Adjustment

Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not ground,
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage by biasing the AID VIN(-) input at this VIN(MIN) value
(see Applications section). This utilizes the differential
mode operation of the AID.
The zero error of the AID converter relates to the location of the first riser of the transfer function and can be
measured by grounding the VIN(-) input and applying a
small magnitude positive voltage to the VIN( +) input. Zero
error is the difference between the actual DC input voltage
which is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal % LSB
value (% LSB = 9.8mV for VREF/2 = 2.500V).

5V

(VREF)
R
VIN

"

2R

6 V'N(.)

:tl0V
2R

~

v+

~

$'O#F

ADC0602ADC0604
V,N(-)

":::0334-24

Figure 9: Handling ± 10V Analog Input Range

Full-Scale Adjust
The full-scale adjustment can be made by applying a differential input voltage which is 1% LSB down from the desired analog full-scale voltage range and then adjusting the
magnitude of the VREF/2 input (pin 9) for a digital output
code which is just changing from 11111110 to 1111 1111.
When offsetting the zero and using a span-adjusted VREF/2
voltage, the full-scale adjustment is made by inputting VMIN
to the VIN(-) input of the AID and applying a voltage to the
VIN(+) input which is given by:

5V

(VREF)
R
V,N

:tsv

"

R

6 V'N(.)

v+ 20

ADC0602ADC0604

~

-+

f

'O• F

.
[(VMAX-VMIN)]
256
'
VIN(+)fsadJ=VMAX-l.5

V'N(-)

where:
VMAX=the high end of the analog input range
and
VMIN=the low end (the offset zero) of the analog range.
(Both are ground referenced.)

0334-25

Figure 10: Handling ± 5V Analog Input Range

Reference Accuracy Requirements
The converter can be operated in a pseudo-ratiometric
mode or an absolute mode. In ratio metric converter applications, the magnitude of the reference voltage is a factor in
both the output of the source transducer and the output of
the AID converter and therefore cancels out in the final

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3-12

ADC0802-ADC0804
Clocking Option

Restart During a Conversion

The clock for the AID can be derived from an external
source such as the CPU clock or an external RC network
can be added to provide self-clocking. The ClK IN (pin 4)
makes use of a Schmitt trigger as shown in Figure 11.
Heavy capacitive or DC loading of the ClocK R pin
should be avoided as this will disturb normal converter operation. loads less than 50pF, such as driving up to 7 AID
converter clock inputs from a single ClK R pin of 1 converter, are allowed. For larger clock line loading, a CMOS or low
power TTL buffer or PNP input logic should be used to minimize the loading on the ClK R pin (do not use a standard
TTL buffer).

If the AID is restarted (CS and WR go low and return
high) during a conversion, the converter is reset and a new
conversion is started. The output data latch is not updated if
the conversion in progress is not completed. The data from
the previous conversion remain in this latch.

Continuous Conversions
In this application, the CS input is grounded and the WR
input is tied to the INTR output. This WR and INTR node
should be momentarily forced to logic low following a power-up cycle to insure circuit operation. See Figure 12 for
details.

ADC0802ADCOS04

CLK R
19

>C>-~.CLK

1
'elK= 1.1 RC
R=10kO

0334-26

Figure 11: Self-Clocking the AID

10k

r-~-o--1:-tCS
2Rl)

r-~----.-~~3~WR
N.O.L.----+-~...:4=iCLK IN

~

START

: INTR
ANALOG

7 VIN(+)

ADCOB02ADC0804

INPUTSO-C~:i
8 VIN(-)

r------2 clock. All 110 devices are memorymapped in the 6800 system, and a special signal, VMA,
indicates that the current address is valid. Figure 16 shows
an interface schematic where the AID is memory-mapped
in the 6800 system. For simplicity, the CS decoding is
shown using % DM8092. Note that in many 6800 systems,
an already decoded % line is brought out to the common
bus at pin 21. This can be tied directly to the CS pin of the
AID, provided that no other devices are addressed at HEX
ADDR: 4XXX or 5XXX.
In Figure 19 the ADC0802 series is interfaced to the
MC6800 microprocessor through (the arbitrarily chosen)
Port B of the MC6820 or MC6821 Peripheral Interface
Adapter (PIA). Here the CS pin of the AID is grounded since
the PIA is already memory-mapped in the MC6800 system
and no CS decoding is necessary. Also notice that the AID
output data lines are connected to the microprocessor bus
under program control through the PIA and therefore the AI
D RD pin can be grounded.

This converter has been designed to directly interface
with 8080/85 or Z-80 Microprocessors. The 3-state output
capability of the AID eliminates the need for a peripheral
interface device, although address decoding is still required
to generate the appropriate CS for the converter. The AID
can be mapped into memory space (using standard memory-address decoding for CS and the MEMR and MEMW
strobes) or it can be controlled as an 110 device by using
the 110 Rand lID W strobes and decoding the address bits
AO --+ A7 (or address bits A8 --+ A15, since they will
contain the same 8-bit address information) to obtain the
CS input. Using the 110 space provides 256 additional addresses and may allow a simpler 8-bit address decoder, but
the data can only be input to the accumulator. To make use
of the additional memory reference instructions, the AID
should be mapped into memory space. See A020 for more
discussion of memory-mapped vs lID-mapped interfaces.
An example of an AID in 110 space is shown in Figure 16.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: An typical values havs be8n charsoterized but are not tested.

3-15

•

~

ADC0802-ADC0804

CD

§
I

&\I

o

INT(14)

.".

CD

o

UOWR(27)·

§

iiOiiD (25).
10k
yy

'-'

1CS

RD
~-

Y+
CLKR

~Wii
4

ANALOG
INPUTS

...

-

!_

(LSB)DBo

CLKIN

DB1
DBa
ADC0802ADC0804
DBa
DB4
DBs
Die
(MSB)DB7

INTR

7

V\N(+)
V\N(-)
150pFrt AGND

-T ":' o!o
1

~

YREFJ2
DGND

~5Y
18
17
16
15
14
13
12
11

~101'F

r

DSo(13)"
DB1 (16)·
DBa (11)·
DBa (9).
DB4(5)·
Des (16)·
Die (20)·
DB7m·

5Y

I

~

OUT

Y+

I

~

Ts
T4
'--- T3
r-- T2
~ T1
~ To

......

T

8131
BUS
COMPARATOR

Bs
B4
Ba

B2
B1
So

1

Ao,s (36)
Ao,4 (39)
Ao,3 (38)
Ao,2 (37)
Ao,1 (40)
Ao,o (1)

1

,h
0334-31
Note: Pin numbers for 8228 system controller: others are 8080A

Figure 16: ADC0802 to 8080A CPU Interface

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3-16

.o~on..

ADC0802-ADC0804

CD

APPLICATION NOTES

o

N

Some applications bulletins that may be found useful are
listed here:
A016 "Selecting AID Converters," by Dave Fullagar.
A018 "Do's and Oont's of Applying AID Converters," by
Peter Bradshaw and Skip Osgood.
A020
A030
R005

I

iffi2
ADC0802-

"A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing," by Ed Sliger.
"The ICL7104 - A Binary Output AID Converter for
Microprocessors," by Peter Bradshaw.
"Interfacing Data Converters & Microprocessors,"
by Peter Bradshaw et ai, Electronics, Dec. 9, 1976.

WR3

.....

5

INPUTS ,..

-

7

F

"-/

,,:,"-

/"/1

( ABC]
5V(8) 123

'='

18

00(33)(31)

.... 1.

(LSB)D80 17
ADCOI02ADC0804

~ AGNO
'lReF12

o-fo-

150pF .......

CLK R .!!...

CLKIN

YlNC+)
YlNC-)

Dt (32)(2tJ

DI2 15

DBa
DB4

DIs

Dz(31)[KJ

~

Da(3O)'IHl

14
13

D4(28)(32J

Ds(2I1U3OJ

O. 12
(MSB)DB7 11

DONO

•

RIW(34)[I]

r::lt,
V+~~ '1:'"10,.

~ RD

"--ic Viii
• iiffili

CD

0334-32

.

CS

.

o

Figure 17: Mapping the AID as an I/O device for
use with the Z-80 CPU

~
1

ADC0804

§

74C32

.A

ANALOG

§

De(27)jij

~

D7(28)f,ij

¥
1
2

•.r-3
~O~4
5

Al2 (22) 134)

.A

....~

.....

Al3 (23)INJ

, Al4 (24)IMJ

,

All (25) (33)

VMA (5) IFJ
0334-33

'Nota 1: Numbers in parentheses refer to MC6800 CPU pinout.
"Note 2: Numbers or letters In brackets refer to standard MC6800 system oommon bus oede.

Figure 18: ADC0802 to MC6800 CPU Interface

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDlTION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical values have b8en chsrscteriz6d but are not testsd.

3-17

~

at

ADC0802-ADC0804

i
i
I

(II

18

at

19

o

1CIIc

CB1
CEb

yy

1

1
2

J.,

~
4

iiD
\iii
CLKIN

5
e- iNfR

....
ANALOG

7

INPUTS
150p

-

CS

F=~

8

40

\/aN(+)
YlN(-)

AGND
VREFI2
DGND

'\".J

MC8820
(MCS862O)

y+ 20

~5Y

CLKR
(LSB)D80
D81
ADC0802DEb
ADC0804
D83

18
17
18
15
14
13
DBs
12
DBs
11

De..

(MS81D87

10
11
12
13
14
15
16
17

PBo

PIA

PB1
PEb

psa
pe..

PBs
PBs
P87

Ii 7¥
0334-34

Figure 19: ADC0802 to MC6820 PIA Interface

INTERSIL'S SOLE AND EXClUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE ODNDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vaIuss have bstm chsracfBtfud but lU8 not tssted.

3-18

ICL8052/ICL 7104
and ICL8068/ICL7104
14/16-Bit p,P-Compatible
2-Chip AID Converter
GENERAL DESCRIPTION

FEATURES

The ICL71 04, combined with the ICL8052 or ICL8068,
forms a member of Intersil's high performance AID converter family. The ICL7104-16, performs the analog switching
and digital function for a 16-bit binary AID converter, with
full three-state output, UART handshake capability, and other outputs for easy interfacing. The ICL7014-14 is a 14-bit
version. The analog section, as with all Intersil's integrating
converters, provides fully precise Auto-Zero, Auto-Polarity
(including ± 0 null indication), single reference operation,
very high input impedance, true input integration over a constant period for maximum EMI rejection, fully ratio metric operation, over-range indication, and a medium quality built-in
reference. The chip pair also offers optional input buffer
gain for high sensitivity applications, a built-in clock oscillator, and output signals for providing an external Auto-Zero
capability in preconditioning Circuitry, synchronizing external
multiplexers, etc.

• 16/14 Bit Binary Three-State Latched Outputs Plus
Polarity and Overrange
• Ideally Suited for Interface to UARTs and
Microprocessors
• Conversion On Demand or Continuously
• Guaranteed Zero Reading for Zero Volts Input
• True Polarity at Zero Count for Precise Null
Detection
• Single Reference Voltage for True Ratlometrlc
Operation
• Onboard Clock and Reference
• Auto-Zero; Auto-Polarity
• Accuracy Guaranteed to 1 Count
• All Outputs TTL Compatible
• ± 4V Analog Input Range
• Status Signal Available for External Sync, AIZ In
Preamp, etc

ORDERING INFORMATION
Part Number

Temp. Range

ICL8052CPD
ICL8052CDD
ICL8052ACPD
ICL8052ACDD
ICL8068CJD
ICL8068ACJD

O·Cto
O·Cto
O·Cto
O·Cto
O·Cto
O·Cto

+70·C
+70·C
+70·C
+70·C
+70·C
+70·C

Package

Part Number

14-Pin Plastic DIP
14-Pin CeramiC DIP
14-Pin Plastic DIP
14-Pin Ceramic DIP
14-Pin CERDIP
14-Pin CERDIP

ICL7104-14CJL
ICL7104-14CPL
ICL7104-14CDL
ICL7104-16CJL
ICL7104-16CPL
ICL7104-16CDL

Package

Temp. Range
O·Cto
O·Cto
O·Cto
O·Cto
O·Cto
O·Cto

-70·C
+70·C
+70·C
+70·C
+70·C
+70·C

40-Pin CERDIP
40-Pin Plastic DIP
40-Pin Ceramic DIP
40-Pin CERDIP
40-Pin Plastic DIP
40-Pin Ceramic DIP

0346-1

Figure 1: ICL8052A (8068A)IICL7104 16/14 Bit AID Converter Functional Diagram

lNTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

3-19

p
CD

o

GI

....CD
n
r-

....
....
o

•

~

ICL8052/ICL 7104 and ICL8068/ICL 7104

cj

ABSOLUTE MAXIMUM RATINGS

co
CD
o
co

Power Dissipation (1) All Devices ................ 500mW
Storage Temperature ................ - 65'C to + 150'C
Operating Temperature ................... O'C to + 70'C
Lead Temperature (Soldering, 1Osee) ............. 300'C

.......

=::.

...
2

'a

.....
C

CO

o

......

()

=::.
(\I
II)

o

a
CO
_

ICL7104
V+ Supply(GNDtoV+) .......................... 12V
V + + to V- .................................... 32V
Positive Supply Voltage (GND to V + + ) ............ 17V
Negative Supply Voltage (GND to V -) .............. 17V
Analog Input Voltage (Pins 32 - 39) (4) ...... V + + to VDigital Input Voltage
(Pins 2 - 30) (5) ........... (GND-0.3V) to (V+ +0.3V)

ICL8052, 8068
Supply Voltage ................................. ±18V
Differential Input Voltage (8068) .................. ± 30V
(8052) ................ ±6V
Input Voltage (2) ............................... ± 15V
Output Short Circuit Duration,
All Outputs (3) ............................. Indefinite

e.

NOTE 1 Dissipation rating assumes device is mounted with all leads welded or soldered to printed circuit board in ambient temperature below + 70
For higher
temperatures, derate 1OmW 1°C.
2: For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
3: Short circuit may be to ground or either supply. Rating applies to + 70'C ambient temperature.
4 Input voltages may exceed the supply voltages provided the input curren1 is limited to ± 100"A.
5: Connecting any digital inputs or outputs to voltages greater than V + or less than GND may cause destructive device latchup. For this reason it is
recommended that no inputs from sources not on the same power supply be applied to the ICL7104 before its power supply is established.
G

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device ,sl/ability.

INTEGRATOR
OUT
COMP
OUT

BUFFER
(+IN)

REF
CAP

INTEGRATOR
(+IN)

REF
PASS

INTEGRATOR
(-IN)

GND

BUFFER
(-IN)

REF
OUT

BUFFER
OUT

REF
SUPPLY

y+

Yo.
DIGGND
STTS
POL.
O.R.
BIT 16
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BITS
BITS
BIT 4
BIT 3
BIT 2

V..

YCOMPIN
REFCAP 1
YREF

DIGGND
STTS
POL
O.R.
BIT 14
BIT 13
BIT 12
ICL7104
BIT 11
BIT 10
" -16
11
BIT 9
N.C.
N,C.
BIT 8
15
BIT 7
BITS
t7
BITS
BIT 4
BIT 3
BIT 2

AZ

ANALOG GND
REFCAP 2
BUF IN
ANALOG liP
Y+

eE7CD

,."
,.

SEN
Rlii
MODE
CLOCK 2
CLOCK 1

"
,."

.

0346-2

(OUTLINE OWGS DO, JO, PO)

0346-3

(OUTLINE OWGS OL, JL, PL)
Figure 2: Pin Configurations

ICL7104 ELECTRICAL CHARACTERISTICS
Symbol

(V+ = +5V, V + + = +15V, v-= -15V, TA=25'C)

Characteristics

Test Conditions

Min

Typ

Max

Unit

liN

Clock Input

CLOCK 1

Vin= + 5V to OV

±2

±7

±30

/J- A

liN

Comparator lIP

COMP IN (Note 1)

Vin=OVto +5V

-10

±0,OO1

+10

/J- A

MODE

VIN= +5V

+1

+5

+30

/J- A

Vin=OV

-10

±O.01

+10

/J- A

IIH

Inputs

IlL

with Pulldown

IIH

Inputs

SEN,R/H

Vin= +5V

-10

±0.01

+10

/J- A

IlL

with
Pull ups

LBEN, MBEN,
HBEN, CE/LD

Vin=OV

-30

-5

-1

/J- A

}

(Note 2)

INTERS1L'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not t88tsri.

3-20

.D~DI!.

ICL8052/ICL7104 and ICL8068/ICL7104
ICL7104 ELECTRICAL CHARACTERISTICS

(V+=+5V,V++ =+15V,V-=-15V,TA=25°C)

::
....

(Continued)
Symbol

Characteristics

VIH

Input High Voltage

All Digital Inputs

VIL

Input Low Voltage

All Digital Inputs

Test Conditions

VOL

Digital

LBEN

IOL =1.SmA

VOH

Outputs

MBEN (1S-only)

IOH= -10/-LA

VOH

Three-Stated
On

HBEN
CE/LD
BIT n, POL, OR

IOH=-240/-LA

(Note 3)

Min

Typ

Max

Unit

2.5

2.0

-

V

1.5

1.0

V

0.27

.4

V

4.5

-

V

3.5

-

V

2.4

Digital Outputs
Three-Stated Off

BIT n, POL, OR

O::;;Vout::;;V+

VOL

Non-Three State

SITS

IOL=3.2mA

-

IOH=-400/-LA

2.4

Digital

VOL

Output

CLOCK 2

-10

CLOCK 3 (-14 ONLY)

±.001

+10

/-LA

0.3

.4

V

3.3

-

V

IOH=-320/-LA

4.5

IOL =1.SmA

0.27

V
V
.4

V

2.4

3.5

V

25k

Switches 4,5,S, 7 ,8,9

-

Switch Leakage

-

15

Clock

Clock Freq. (Note 4)

DC

Supply Currents

+ 5V Supply Current
All outputs high impedance

Freq. = 200kHz

1++

+ 15V Supply Current

Freq. = 200kHz

1-

-15V Supply Current

Freq. = 200kHz
Note 5

IOH=-320/-LA

VOH
Switch 1

ROS(on)

Switches 2,3

ROS(on)
ROS(on)

Switch

10(011)

1+

4k

20k

2k

10k

n
n
n

200

400

kHz

200

SOO

/-LA

.3

1.0

mA

25

200

/-LA

4.0

+11.0

V

pA

V+

Supply Voltage

Logic Supply

V++

Range

Positive Supply

+10.0

+1S.0

V

Negative Supply

-1S.0

-10.0

V

VNOTES: 1.
2.
3.
4.
5.

...
~

..i.
o

2
o

This spec applies when not in Auto·Zero phase.
Apply only when these pins are inputs, i.e., the mode pin Is low, and the 7104 is not in handshake mode.
Apply only when these pins are outputs, i.e., the mode pin is high or the 7104 is in handshake mode.
Clock circuH shown in Figs. 15 and 16.
V + must not be more posHive than V + + .

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESB, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE; AU typical vs/ues have been characfBrizsd but IUS not tested.

3-21

....CD
,.n

...

..
~

0.5

IOL = 320/-LA

VOH
VOL

,.n

Gt

IOL

VOH

n

I;
o

o

•

.. ICL8052/ICL7104 and ICL8068/ICL7104
ii
..
~

l"-

ICL8068 ELECTRICAL CHARACTERISTICS

(VSUPPLY= ±15V unless otherwise specified)

:::::.
CD

o

Symbol

a
"Ii

..
...
o

8068

Test Conditions

Min

Typ

Max

8068A

Min

Typ

Unit
Max

EACH OPERATIONAL AMPLIFIER
VOS

Input Offset Voltage

VCM=OV

20

65

20

65

mV

liN

Input Current (either input) (Note 1)

VCM=OV

175

250

80

150

pA

CMRR

Common-Mode Rejection Ratio

VCM= ±10V

Non-Linear Component of CommonMode Rejection Ratio (Note 2)

VCM= ±2V
RL =50k!l

I"-

g
.....

Characteristics

70

90

70

90

dB

110

dB

6

6

V/ILS

110

Av

Large Signal Voltage Gain

C\I

SR

Slew Rate

o

GBW

Unity Gain Bandwidth

2

2

MHz

Isc

Output Short-Circuit Current

5

5

mA

10

...CD
g

20,000

20,000

VIV

COMPARATOR AMPLIFIER
AVOL

Small-signal Voltage Gain

+VO

Positive Output Voltage Swing

RL =30k!l
+12

4000
+13

+12

+13

VIV
V

-yo

Negative Output Voltage Swing

-2.0

-2.6

-2.0

-2.6

V

Vo

Output Voltage

1.60

1.75

Ro

Output Resistance

TC

Temperature Coefficient

VSUPPLY

Supply Voltage Range

ISUPPLY

Supply Current Total

VOLTAGE REFERENCE
1.5

2.0

5
50

V
!l

40
±16

ppml'C

±10

14

Characteristics

1.90

5

±10

ICL8052 ELECTRICAL CHARACTERISTICS
Symbol

1.75

±16

V

14

mA

8

(VSUPPLY = ± 15V unless otherwise specified)
8052

Test Conditions
Min

8052A

Typ

Max

Min

Typ

Max

I Unit

EACH OPERATIONAL AMPLIFIER
VOS

Input Offset Voltage

VCM=OV

20

75

20

75

mV

liN

Input Current (either input) (Note 1)

VCM=OV

5

50

2

10

pA

CMRR

Common-Mode Rejection Ratio

VCM= ±10V

Non-Linear Component of CommonMode Rejection Ratio (Note 2)

VCM= ±2V

Av

Large Signal Voltage Gain

RL =50k!l

SR

Slew Rate

GBW

Unity Gain Bandwidth

Isc

Output Short-Circuit Current

70

90

70

90

dB

110

dB

6

V/ILS

1

1

MHz

20

20

mA

110
20,000

20,000
6

VIV

COMPARATOR AMPLIFIER
AVOL

Small-signal Voltage Gain

+Vo

Positive Output Voltage Swing

+12

-yo

Negative Output Voltage Swing

-2.0

RL =30k!l

4000

VIV

+13

+12

+13

V

-2.6

-2.0

-2.6

V

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but ar6 not testBd.

3-22

BlO~OIL

ICL8052/ICL 7104 and ICL8068/ICL 71 04

n
I'"

CD

ICL8052 ELECTRICAL CHARACTERISTICS
Symbol

Characteristics

(VSUPPLY= ± 15V unless otherwise specified) (Continued)
8052A

8052

Test Conditions
Min

Typ

Unit

Max

Min

Typ

Max

2.0

1.60

1.75

1.90

VOLTAGE REFERENCE
Vo

Output Voltage

1.5

1.75

V

Ro

Output Resistance

5

5

n

TC

Temperature Coefficient

50

40

ppml"C

VSUPPLY

Supply Voltage Range

ISUPPLY

Supply Current Total

±10

±16
6

±10

12

±16

V

12

mA

6

NOTES: 1. The input bias currents are junction leakage currents which approximately double for every 100G increase in the junction temperature, TJ. Due to limited
production test time, the input bias currents are measured with junctions at ambient temperature. In normal operation the junction temperature rises
above the ambient temperature as a result of internal power dissipation, Pd. TJ=TA+R8JAPd where R8JA is the thermal resistance from junction to
ambient. A heat sink can be used to reduce temperature rise.
2. This is the only component that causes error in dual·slope converter.

SYSTEM ELECTRICAL CHARACTERISTICS: ICL806817104

(V + + = +15V,

v+ =

+5V,

V- = -15V, Clock Frequency = 200kHz)
Characteristics

8068A/7104-16

8068A17104-14

Test Conditions
Min

Typ

Max

Min

Typ

Unit

Max

Zero Input Reading (4)

Hexadecimal
Vin=O.OV
-0.0000 ±O.OOOO +0.0000 -0.0000 -0.0000 +0.0000
Reading
Full Scale = 4.000V

Ratiometric Reading (1) (4)

Vin=VRef.
Full Scale = 4.000V

1FFF

2000

2001

Linearity over ± Full Scale (error
of reading from best straight line) -4V,;;Vin';; +4V
(4)

0.5

1

Differential Linearity (difference
between worst case step of
adjacent counts and ideal step)

.01

-4V,;;Vin';; +4V

Rollover error (Difference in
reading for equal positive & neg· -Vin= +Vin '" 4V
ative voltage near full scale) (4)

0.5

Noise (p.p value not exceeded
95% of time)

Vin=OV
Full scale = 4.000V

Leakage Current at Input (2) (4)

Vin=OV

100

Zero Reading Drift (A)

Vin=OV
0'C,;;TA,;;70'C

0.5
2

8000

8001

0.5

1

.01

1

2

Vin= +4V
Scale Factor Temperature (3) (4)
0,;;TA';;50'C
Coefficient
ext. ref. Oppml'C

7FFF

0.5

100

1

2

LSB

fJ- V
165

0.5
5

LSB

LSB

2
165

Hexadecimal
Reading

pA
fJ-VI'C

5

ppml'C

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTe: All typical values have been characterized but are not tested.

3·23

o

(II

....N

n
I'"

......
o
....

II

::a

Q.

n
I'"
CD

o

o

....CD
n
I'"

......
o
....

•

..... ICL8052/ICL7104 and ICL8068/ICL7104
g~!~~~5~ c~~~;!~~~~~o~~:RACTERISTICS:

.D~Do..

~

ICL805217104

G

o

a

1

....
~

o

i....
C\I
10

o

a

Characteristics

(V + + = + 15V, v+ = +5V,

8052A17104-14

Teat Conditions

Typ

Min

8052A17104·16

Max

Min

Typ

Unit

Max

Zero Input Reading

Hexadecimal
Vln=O.OV
-0.0000 ±o.oOOO +0.0000 -0.0000 ±0.0000 +0.0000
Full Scale=4.000V
Reading

Ratiometric Reading (3) (4)

Vin= VRef.
Full Scale=4.000V

2000

2001

Linearity over ± Full Scale (error
of reading from best straight line) -4V~Vin~ +4V
(4)

0.5

1

Differential Linearity (difference
between worst case step of
adjacent counts and ideal step)

-4V~Vin~

.01

Rollover error (Difference in
reading for equal positive &
negative voltage near full scale)

-Vln= + Vin:::::4V

0.5

Noise (p.p value not exceeded
95% of time)

Vin=OV
Full scale=4.000V

30

Leakage Current at Input (2) (4)

Vin=OV

20

Zero Reading Drift (4)
Scale Factor Temperature
Coefficient (4)

1FFF

+4V

Vin=OV
0~TA~70"C

7FFF

8000

8001

0.5

1

.01

1

0.5

20

LSB

LSB

1

LSB

p,V

30
30

Hexadecimal
Reading

30

pA

0.5

0.5

p,VI"C

2

2

ppml"C

Vln=+4V
0~TA~70"C

(ext. ref. Oppm/OC)

NOTES: 1. Tested with low dielectric absorption integrating capacitor.
2. the input bias currents are junction leakage currents which approximately double for every 10'C increase in the junction temperature. TJ. Due to limited
production test time, the input bias currents are measured with junctions at ambient temperature. In normal operation the junction temperature rises
above the ambient temperature as a result of Internal power dissipation. Pd. TJ= TA+ RSJAPd where ROJA is the thermal resistance from junction to
ambient. A heat sink can be used to reduce temperature rise.
3. The temperature range can be mended to 70'C and beyond If the Auto-Zero and Reference capecltors are Increased to absorb the high temperature
leakage of the 8068. See note 2 above.
4. Parameter has been characterized but Is not production tested.

INTERSIL·S SOLE AND EXCLUSIVE WARRANTY OBLIGAnON WITH RESPECT TO THIS PROOUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL, OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARnCULAR USE.

NOTE; AU Iyp/caIvsIues have bNn charscIetfzod but.", not _

3·24

.O~OI!..

ICL8052/ICL 7104 and ICL8068/ICL 7104

,.n
C»

o

CII

....
n
,.
II)

COHVDT

CONTIIOL

......
o
....

:'1.

-

III
~

A.

IOI2AI

7104

P

-1'

C»

o

ell
C»

....
n
,.

,.--..
1 -=t: or CHIP ALiCT I
1....-.......--..4-........._

......
o

0346-4

Figure 3: Full 18 Bit Three State Output

COHVDT

IOI2AI

lallA

-

7104

011

011

POL

POL

IOI2AI

lallA

7104

La

La

CONTIIOL

CONTIIOL

- 011

POL

1052A1

7104

0346-5

Figure 4: Various Combinations of Byte Disables

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charact8rlzrJd but SIB not fBsted.

3·25

....

•

......~

d
::::
GI)

ICL8052/ICL 7104 and ICL8068/ICL 7104
AC CHARACTERISTICS
AS INPUT

g

lI\IEII

I:IElII

......

HIGH BYTE
DATA

....
o

...

i.....
CII

...
i

+5V, V- = -15V)

=

URI!
AS INPUT

AS INPUT

.....

MIOOLE BYTE
.fD'1.fA\...
ENABLE
--------------------------~--------

II)

o
GI)

+ 15V, V+

AS INPUT

.

1

=

CElLO

U)

oGI)

(V + +

LOW BYTE

ENABLE

-------------------------------,------,--t~~-----

- - - - - - - =HIGH IMPEDANCE

0346-6

Figure 5: Direct Mode Timing Diagram
Table 1: Direct Mode Timing Requirements (Note: Not tested In production)
Symbol

Description

tbaa

XBEN Min, Pulse Width

tdab

Data Access Time from XBEN

tdhb

Data Hold Time from XBEN

Icas

CElLO Min, Pulse Width

Idse

Data Access Time from CElLO

tdhe

Data Hold Time from CElLO

tcwh

CLOCK 1 High Time

Max

300
300
200
350
350
280
1000

Table 2: Handshake Timing Requirements
Name

Typ

Min

Description

tmw

MODE Pulse (minimum)

tsm

MODE pin set-up time

tma

MODE pin high to low Z CElLO high delay

tmb

MODE pin high to XBEN low Z (high) delay

teal

CLOCK 1 high to CElLO low delay

teah

CLOCK 1 high to CElLO high delay

tebl

CLOCK 1 high to XBEN low delay

tebh

CLOCK 1 high to ~ high delay

tedh

CLOCK 1 high to data enabled delay

tcdl

CLOCK 1 low to data disabled delay

Iss

Send ENable set-up time

tebz

CLOCK 1 high to XBEN disabled delay

Icaz

CLOCK 1 high to CElLO disabled delay

tcwh

CLOCK 1 High Time

Unit

ns

(Note: Not tested in production,)
Min

Typ

1250

20
-150
200
200
700
600
900
700
1100
1100
-350
2000
2000
1000

Max

Unit

ns

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: An typJcsJ values haV6 bHn charactsrlzsd but BffI not tested.

3-26

·o~on..

ICL8052/ICL 7104 and ICL8068/ICL 7104

c;
rCD

o

CIt

....
I\)

c;

CLOCK 1 (PIN 25)

...o...r-

.

lITHeR:
_PIN
011:
INTERNAL LATCH

III
::I

PUl.8I1' MODE "Hr.

a.

UNIT

INTERNAl. MODI

c;

NOIIM--~-..I.--:-"I

r-

CD

o
ca

....
CD

SEN

(EXTERNAL SIGNAL)

OIR,POL01-14

BITS 1-5

~...

.

'
H_ _ _~~~:~~_ _ ~-----

_ _- '_ _~_ _~_ _~_ _-"-'S~~_~~(::~D~A~T~A~Y~AL~I~D.~S~T!AB~;i:=:>~-~----~-~HANDSHAKE MODE TRIGGERED BY ·····DR---14 BIT VERSION SHOWN

THREE-8TATE _

THREE-STATE W PULWP ~

-16 HAS EXTRA (MBEN) PHASE

0346-7

Figure 6: Handshake Mode Timing Diagram

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are not tested

3-27

...o

.

•

g.... ICL8052/ICL 7104 and ICL8068/ICL 7104

.......
g

....CD

Table 3: Pin Descriptions
Pin

Symbol

Option

++)

Description

CD

1

V(

...gCD

2

GND

Digital Ground .OV, ground return

3

STTS

STaTuS output. HI during
Integrate and Deintegrate until
data is latched. La when analog
section is in Auto-Zero
configuration.

o

"

.

C
1\1

........o

...

4

POL

&\I

5

OR

o

6

BIT16
BIT14

-16
-14

7

BIT 15
BIT 13

-16
-14

8

BIT14
BIT12

-16
-14

9

BIT13
BITll

-16
-14

10

BIT12
BIT10

-16
-14

11

BITll
BIT9

-16
-14

12

BIT10
nc

-16
-14

13

BIT9
nc

-16
-14

II)

...
g
CD

14

BIT8

15

BIT7

16

BIT6

17

BIT5

18

BIT4

19

BIT3

20

BIT2

24 CLOCK3
Pin

Symbol

Least significant bit.

LBEN

Low By1e ENable. If not in
handshake mode (see pin 27)
when La (with CEILD, pin 30)
activates low-order byte outputs,
BITS 1-8
When in handshake mode (see
pin 27), serves as a low-byte flag
output. See Figures 12, 13, 14.

MBEN

-16

HBEN

-14

Description

Clock output. Crystal or RC oscillator.

27

MODE

Input La; Direct output mode where CEI
LD, HBEN, MBEN and LBEN act as
inputs directly controlling by1e outputs. If
pulsed HI causes immediate entry into
handshake mode (see Figure 14).
If HI, enables CEILD, HBEN, MBEN, and
LBEN as outputs. Handshake mode will
be entered and data output as in Figures
12 & 13 at conversion completion.

28 RIH

Run/Hold: Input HI-conversions
continously performed every 217 ( -16) or
2 15( -14) clock pulses. Input LOconversion in progress completed,
converter will stop in Auto-Zero 7 counts
before input integrate.

29 SEN

Send-ENable: Input controls timing of
byte transmission in handshake mode. HI
indicates 'send'.

30

CEILD

Chip-Enable/LoaD. With MODE (pin 27)
La, CEILD serves as a master output
enable; when HI, the bit outputs and POL,
OR are disabled. With MODE HI, pin
serves as a Loa5 strobe ( - ve going)
used in handshake mode. See Figures 12
& 13.

31

V(+)

Positive Logic Supply Voltage. Nominally
+5V.

32 AN,IN

ANalog INput. High side.

33

BUF IN

BUFfer INput to analog chip (ICL8052 or
ICL8068)

34

REFCAP2 REFerence CAPaCitor (negative side)

35 AN.GND.

ANalog GrouND. Input Ibw side and
reference low side.

36 A-Z

Auto-Zero node.

37 VREF

Voltage REFerence input (positive side).

38

Mid By1e ENable. Activates BITS
9-16, see LBEN (pin 22)
High Byte ENable.
Activates BITS 9-14, POL, OR,
see LBEN (pin 22)

-14

Description
High By1e ENable. Activates
POL, OR, see LBEN (pin 22).
RC oscillator pin. Can be used
as clock output.

26 CLOCK2

Data Bits, Three-state outputs.
See Table 4 for format
of ENables and bytes.
HIGH=true

BIT 1

-16

Clock input. External clock or ocsillator.

(Most significant bit)

22

Option

25 CLOCKI

OverRange. Three-state output.

21

23

Symbol
HBEN

POLarity. Three-state output. HI
for positive input.

()

:::::.

Pin

Positive Supply Voltage
Nominally + 15V

REFCAPI REFerence CAPacitor (positive side).

39 CaMP-IN

COMParator INput from 8052/8068

40 V(-)

Negative Supply Voltage. Nominally
-15V.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTe: All typical values have been characterized but are not tested.

3-28

·D~DIL

ICL8052/ICL 7104 and ICL8068/ICL 7104

P
CIII

o

Table 4: Three-State Byte Formats and ENable Pins

MBEN

HBEN

UI
N

....

n
r-

CElLO

.......o

LBEN

.

l

7104-16 POLIOIR B161 B151 B14J B131 B121 B11[ B10 B9 BSJB71B61B51 B4 1B3 1B2JB1
HBEN
7104-14

LBEN

II
::I

POL 1OIR 1B141 B13lB121B111 B10 1B9 BsIB71B6IB5[B4IB3IB2IB1

A-

Figure 1 shows the functional block diagram of the operating system. For a detailed explanation, refer to Figure 7 below.

n
rCIII

o

01

....
n
rCIII

D

Q

CL

POL

CL
0346-8

Figure 7A: Phase I Auto-Zero

AN
liP

D

Q

ZERO
CROSSING

F/F

CL

POL

CL
0346-9

Figure 7B: Phase II Integrate Input

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

3-29

.......

.
o

ZERO
CROSSING
F/F

•

~

ICL8052/ICL 7104 and ICL8068/ICL 7104

d

DETAILED DESCRIPTION

.......o

::::. Analog Section
CD
CD

o

CD

g
"
C
1\1

Auto-Zero Phase I Figure 7A
During Auto-Zero, the input of the buffer is shorted to
analog ground thru switch 2, and switch 1 closes a loop
around the integrator and comparator. The purpose of the
loop is to charge the Auto-Zero capacitor until the integrator
output no longer changes with time. Also, switches 4 and 9
recharge the reference capacitor to VREF.

Figure 7 shows the equivalent Circuit of the Analog Section of both the ICL7104/S052 and the ICL71 04/8068 in the
3 different phases of operation. If the Run/Fiold pin is left
open or tied to V +, the system will perform conversions at
a rate determined by the clock frequency: 131,072 for - 16
and 32,368 for - 14 clock periods per cycle (see Figure 9
conversion timing).

~

...o....
...
u

::::.
(II
."

o

D

3

Q

ZERO
CROSSING

~

F/F
CL

POL

CL

0346-10

Figure 7C: Phase III + Deintegrate

t(

ZERO
CROSSING

6

9

-

Q

D

F/F

7

CL

+

CRE.

POL

CL

0346-11

Figure 7D: Phase 111- Deintegrate

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTiE: All typical values have been characterized but are not tested.

3-30

ICL8052/ICL7104 and ICL8068/ICL7104
phase, the input voltage required to give a full scale
reading = 2VREF.

Input Integrate Phase II Figure 7B
During input integrate the Auto-Zero loop is opened and
the analog input is connected to the buffer input thru switch
3. (The reference capacitor is still being charged to VREF
during this time.) If the input signal is zero, the buffer, integrator and comparator will see the same voltage that existed in the previous state (Auto-Zero). Thus the integrator
output will not change but will remain stationary during the
entire Input Integrate cycle. If VIN is not equal to zero, an
unbalanced condition exists compared to the Auto-Zero
phase, and the integrator will generate a ramp whose slope
is proportional to VIN. At the end of this phase, the sign of
the ramp is latched into the polarity F/F.

Note: Once a zero crossing is detected, the system automatically reverts to
Auto-Zero phase for the leftover Deintegrate time (unless Run/Rold is manipulated, see Run/Rold Input in detailed description, digital section).

Buffer Gain
At the end of the auto-zero interval, the instantaneous
noise voltage on the auto-zero capacitor is stored, and subtracts from the input voltage while adding to the reference
voltage during the next cycle. The result is that this noise
voltage effectively is somewhat greater than the input noise
voltage of the buffer itself during integration. By introducing
some voltage gain into the buffer, the effect of the auto-zero
noise (referred to the input) can be reduced to the level of
the inherent buffer noise. This generally occurs with a buffer
gain of between 3 and 10. Further increase in buffer gain
merely increases the total offset to be handled by the autozero loop, and reduces the available buffer and integrator
swings, without improving the noise performance of the system. The circuit recommended for doing this with the
ICL8068/1CL7104 is shown in Figure 8. With careful layout,
the circuit shown can achieve effective input noise voltages
on the order of 1 to 2 ".V, allowing full 16-bit use with full
scale inputs of as low as 150mV. Note that at this level,
thermoelectric EMFs between PC boards, IC pins, etc., due
to local temperature changes can be very troublesome. For
further discussion, see App. Note A030.

Deintegrate Phase III Figure 7C & D
During the Deintegrate phase, the switch drive logic uses
the output of the polarity F IF in determining whether to
close switches 6 and 9 or 7 and 8. If the input signal was
positive, switches 7 and 8 are closed and a voltage which is
VREF more negative than during Auto-Zero is impressed on
the buffer input. Negative inputs will cause + VREF to be
applied to the buffer input via switches 6 and 9. Thus, the
reference capacitor generates the equivalent of a (+) reference or a (-) reference from the single reference voltage
with negligible error. The reference voltage returns the output of the integrator to the zero-crossing point established
in Phase I. The time, or number of counts, required to do
this is proportional to the input voltage. Since the Deintegrate phase can be twice as long as the Input integrate

0346-12

Figure 8: Adding Buffer Gain to ICL8068

Table 5: Typical Component Values
ICL8052/8068 with

(V++ =+15V,V+=5V,V-=-15V,ClockFreq=200kHz)

ICL7104-14

ICL7104-16

Unit

200

800

4000

100

4000

mV

Buffer Gain

10

1

1

10

1

V/V
k!1

Full scale VIN

RINT

100

43

200

47

180

CINT

.33

.33

.33

0.1

0.1

".F

CAZ

1.0

1.0

1.0

1.0

1.0

".F

10

1.0

1.0

10

1.0

".F

VREF

100

400

2000

50

2000

mV

Resolution

3.1

12

61

6.1

244

".V

Cre!

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN lIEU OF ALL OTHER WARRANTIES, eXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3·31

II

l

(;
I""
CIO

o

GI

CIO
......

(;
I""

...

~

o

•

•

....... ICL8052/ICL7104 and ICL8068/ICL7104
~

S:!
.....

POLARITY

CD
fO

o

...S:!CD

"
.......o"

.
t:

INTEGRATOR
OUTPUT

I

DET~ECTED

I

ZERO CROSSING
OCCURS

I.....
II
I---AZ PHASE I--I-INT PHASE II-t---+i~"'-DEINT PHASE I11--1--AZI

-......"

INTERNAL CLOCK
INTERNAL LATCH
STATUS OUTPUT

h.r ~ J1IlItil..
I

I
I

I

I

I
I
I

I

I

I

I

I

I
I

I

I
'I

NUMBER OF COUNTS TO ZERO CROSSING/
PROPORTIONAL TO V,N

f!

~

I

f~

I

I

IMHN
I (-16 only)

I

I
I

!

TO
ANALOG
SECTION

I

~~~~~~Lt~~1 ~

COMPOUT

AZ
INT
DEINT(+)
DEINT(-)

I

I
2.L ___ J
STaTuS

Rill

CLOCK
1

MODE

I

SEND
0346-14

Figure 10: Digital Section

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTieS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but 8/9 not (ssted

3-33

CII
N

"(IS...

.......
o

!

a.
_

n
...
c»

0
ell

~

(IS
...

....

..
..

During a conversion cycle, the STaTuS output goes high
at the beginning of Input Integrate (Phase II), and goes low
one-half clock period after new data from the conversion
has been stored in the output latches. See Figure 9 for details of this timing. This signal may be used as a "data valid"
flag (data never changes while STaTuS is lOw) to drive interrupts, or for monitoring the status of the converter.

POL OIR 814 813 812 811 810 89

o

o

...g.... ICL8052/ICL 7104
...
u

and ICL8068/ICL 7104

=::.
co
co
o
co

2
""

OPTION
MIN
MAX

~

d
=::.

I

DEINT TERMINATED

I

ATZEROCROSS~NG
INTEGRATOR
OUTPUT

I:

.......o

-14
-16
7161 28665
8185 32761

INTERNAL CLOCK

-

~..---

~

1

-

,

,

I

j

-'-'

I~

1 - - 7 COUNTS---1

V '"lr1nrl. J111nI1..l11L. Jl,.flItI1I1.. ~ -utIl.JlJ1J1.I1
1

INTERNAL LATCH

1

n

STaTuS OUTPUT

RUN/HOLD INPUT

INT
i-PHASEI

1 STATICIN

I HOLD STATE

------....£ETECTION:

-------""Lr------.....,

&"I

i

I

l

_-----!f-'--------1---""
!

-------~--------------~

1ft

i

1

0346-15

o
~

Figure 11: Run/Hold Operation

g Run/Hold Input

grate (Phase II) begins seven clock periods after the high
level is detected.

When the Run/Rold input is connected to V + or left open
(this input has a pullup resistor to ensure a high level when
the pin is left open), the circuit will continuously perform
conversion cycles, updating the output latches at the end of
every Deintegrate (Phase III) portion of the conversion cycle
(See Figure 9). (See under "Handshake Mode" for exception.) In this mode of operation, the conversion cycle will be
performed in 131,072 for 7104-16 and 32768 for 7104-14
clock periods, regardless of the resulting value.
If Run/Rold goes low at any time during Deintegrate
(Phase III) after the zero crossing has occurred, the circuit
will immediately terminate Deintegrate and jump to AutoZero. This feature can be used to eliminate the time spent in
Deintegrate after the zero-crossing. If Run/Rold stays or
goes low, the converter will ensure a minimum Auto-Zero
time, and then wait in Auto-Zero until the Run/Rold input
goes high. The converter will begin the Integrate (Phase II)
portion of the next conversion (and the STaTuS output will
go high) seven clock periods after the high level is detected
at Run/Rold. See Figure 11 for details.
Using the Run/Rold input in this manner allows an easy
"convert on demand" interface to be used. The converter
may be held at idle in Auto-Zero with Run/Rold low. When
Run/Rold goes high the conversion is started, and when
the STaTuS output goes low the new data is valid (or transferred) to the UART - see Handshake Mode). Run/Rold
may now go low terminating Deintegrate and ensuring a
minimum Auto-Zero time before stopping to wait for the
nex1 conversion. Alternately, Run/Rold can be used to minimize conversion time by ensuring that it goes low during
Deintegrate, after zero crossing, and goes high after the
hold point is reached. The required activity on the Run/Rold
input can be provided by connecting it to the CLOCK3 (-14),
CLOCK2 (-16) Output. In this mode the conversion time is
dependent on the input value measured. Also refer to Intersil Application Bulletin A030 for a discussion of the effects
this will have on Auto-Zero performance.
If the RunlRold input goes low and stays low during AutoZero (Phase I), the converter will simply stop at the end of
Auto-Zero and wait for Run/Rold to go high. As above, Inte-

Direct Mode
When the MODE pin is left at a low level, the data outputs
[bits 1 through 8 low order byte, see Table 4 for format of
middle (-16) and high order bytes] are accessible under
control of the byte and chip ENable terminals as inputs.
These ENable inputs are all active low, and are provided
with pullup resistors to ensure an inactive high level when
left open. When the chip ENable input is low, taking a byte
ENable input low will allow the outputs of that byte to become active (three-stated on). This allows a variety of parallel data accessing techniques to be used. The timing requirements for these outputs are shown under AC Characteristics and Table 1.
It should be noted that these control inputs are asynchronous with respect to the converter clock - the data may be
accessed at any time. Thus it is possible to access the data
while it is being updated, which could lead to scrambled
data. Synchronizing the access of data with the conversion
cycle by monitoring the STaTuS output will prevent this.
Data is never updated while STaTuS is low. Also note the
potential bus conflict described under "Initial Clear Circuitry".

Handshake Mode
The handshake output mode is provided as an alternative
means of interfacing the ICL7104 to digital systems, where
the AID converter becomes active in controlling the flow of
data instead of passively responding to chip and byte
ENable inputs. This mode is specifically designed to allow a
direct interface between the ICL7104 and industry-standard
UARTs (such as the Intersil CMOS UARTs, IM6402/3) with
no external logic required. When triggered into the handshake mode, the ICL7104 provides all the control and flag
Signals necessary to sequence the three (lCL7106-16) or
two (ICL7104-14) bytes of data into the UART and initiate
their transmission in serial form. This greatly eases the task
and reduces the cost of designing remote data acquisition
stations using serial data transmission to minimize the number of lines to the central controlling processor.

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANlY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED DR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILIlY AND FITNESS FOR A PARTICULAR USE.
NOTE; All typical values have been characterized but are not tested

3-34

ICL8052/ICL7104 and ICL8068/ICL7104
once every clock pulse, and if it is high, the next (or first)
byte is enabled on the next rising CLOCK 1 (pin 25) clock
edge, the corresponding byte ENable line goes low, and the
Chip ENable/LoaD pin (pin 30) (CE/LD) goes low for one
full clock pulse only, returning high.
On the next falling CLOCK 1 clock pulse edge, if SEN
remains high, or after it goes high again, the byte output
lines will be put in the high impedance state (or three-stated
off). One half pulse later, the byte ENable pin will be cleared
~h, and (unless finished) the CE/LD and the next byte
ENable pin will go low. This will continue until all three (2 in
the case of the 14 bit device) bytes have been sent. The
bytes are individually put into the low impedance state i.e.:
three-stated on during most of the time that their byte
ENable pin is (active) low. When receipt of the last byte has
been acknowledged by a high SEN, the handshake mode
will be cleared, re-enabling data latching from conversions,
and recognizing the condition of the MODE pin again. The
byte and chip ENable will be three-stated off, if MODE is
low, but held high by their (weak) pullups. These timing relationships are illustrated in Figure 12,13, and 14, and Table
2.

Entry into the handshake mode will occur if either of two
conditions are fulfilled; first, if new data is latched (i.e. a
conversion is completed) while MODE pin (pin 27) is high, in
which case entry occurs at the end of the latch cycle; or
secondly, if the MODE pin goes from low to high, when
entry will occur immediately (if new data is being latched,
entry is delayed to the end of the latch cycle). While in the
handshake mode, data latching is inhibited, and the MODE
pin is ignored. (Note that conversion cycles will continue in
the normal manner). This allows versatile initiation of handshake operation without danger of false data generation; if
the MODE pin is held high, every conversion (other than
those completed during handshake operations) will start a
new handshake operation, while if the MODE pin is pulsed
high, handshake operations can be obtained "on demand."
When the converter enters the handshake mode, or when
the MODE input is high, the chip and byte ENable terminals
become TTL-compatible outputs which provide the control
signals for the output cycle. The Send ENable pin (SEN)
(pin 29) is used as an indication of the ability of the external
device to receive data. The condition of the line is sensed

,,/OCCURS

INTEGRATOR
OUTPUT
INTERNAl.
CLOCK

'.,-11 _ _ - - .

~~OBSING
DETEC'IED

"'-

--I""L-I-- __
I

INTERNAl.
LATCH

~ I-- H..-J-I - - rl....-J I - -r-L-

STATUS

OUTPUT

MOOE
INPUT

MODE HIGH ACTIVATES

mmm,RRR.CIIIJiI

!

INTERNAl. UART
NORM

MOOE

...----

SEN

~

BEN
SENBED _____

---

INPUT

j

I\
f

I\

HIGH BYTE
OATA

LOW BYTE
DATA

LOW BYTE
DATA

--------- - -- '"
----------- fo--

BEN
_ SENSEO----...,

f

f

IN.....:=~':.=

DATA VALID

>--

--------

-------- -- '"

OISABLES OUTPUTS eI7[I!
__

_R.!.'!:~i!,!!

DATA VALID

I'-J. _J._

~-J.-

~ -----~_J._

I

-- -------- --- ------

------------------------------------ '"

_=

1/

TERMINATES
UARTMODE

,..----

DATA VALID

~------I

--'--= THRU-8TATE WITH PUUUP

DONT CARE

0346-16

Figure 12: Handshake with SEN Held Positive

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE· All typical values have been charactenzed but are not tested.

3-35

II
:::I
Q.

n
rCO

o

GI
CO

....
n
r-

......

.
o

•

~
...d...

ICL8052/ICL 7104 and ICL8068/ICL 7104
drives the TBRL (Transmitter Buffer Register Load) input to
the UART. The data outputs are paralleled into the eight
Transmitter Buffer Register inputs.
Assuming the UART Transmitter Buffer Register is empty,
the SEN input will be high when the handshake mode is
entered after new data is stored. The CElLO and HBEN
terminals will go low after SEN is sensed, and the high order
byte outputs become active. When CElLO goes high at the
end of one clock period, the high order byte data is clocked
into the UART Transmitter Buffer Register. The UART
TBRE output will now go low, which halts the output cycle
with the HBEN output low, and the high order byte outputs
active. When the UART has transferred the data to the
Transmitter Register and cleared the Transmitter Buffer
Register, the TBRE returns high. On the next ICL71 04 internal clock high to low edge, the high order byte outputs are
disabled, and one-half internal clock later, the HBEN output
returns high. At the same time, the CElLO and MBEN (-16)
or LBEN outputs go low, and the corresponding byte outputs become active. Similarly, when the CElLO returns high
at the end of one clock period, the enabled data is clocked
into the UART Transmitter Buffer Register, and TBRE again
goes low. When TBRE returns to a high it will be sensed on
the next ICL7104 internal clock high to low edge, disabling
the data outputs. For the 16 bit device, the sequence is
repeated for LBEN. One-half internal clock later, the handshake mode will be cleared, and the chip and byte ENable
terminals return high and stay active (as long as MOOE
stays high).

Figure 12 shows the sequence of the output cycle with
SEN held high. The handshake mode (Internal MOOE high)
is entered after the data latch pulse (since MOOE remains
Ie) high the CElLO, LBEN, MBEN and HBEN terminals are aco tive as outputs). The high level at the SEN input is sensed
on the same high to low internal clock edge. On the next to
~ high internal clock edge, the CElLO and the HBEN outputs
assume a low level and the high-order byte (POL and OR,
and except for -16, Bits 9 -14) outputs are enabled. The
II CElLO output remains low for one full internal clock period
'lit only, the data outputs remain active for 1-% internal clock
o periods, and the high byte ENable remains low for two clock
... periods. Thus the CElLO output low level or low to high
edge may be used as a synchronizing signal to ensure valid
... data, and the byte ENable as an output may be used as a
::::. byte identification flag. With SEN remaining high the conCI! verler completes the output cycle using CElLO, MBEN and
LBEN while the remaining byte outputs (see Table 4) are
CD activated. The handshake mode is terminated when all
... bytes are sent (3 for -16,2 for -14).
~
Figure 13 shows an output sequence where the SEN input is used to delay portions of the sequence, or handshake, to ensure correct data transfer. This timing diagram
shows the relationships that occur using an industry-standard IM6402/3 CMOS UART to interface to serial data
channels. In this interface, the SEN input to the ICL7104 is
driven by the TBRE (Transmitter Buffer Register Empty)
output of the UART, and the CElLO terminal of the ICL7104
::::.
CD

3

I

rl

:g

"-

ZEROoCROSSING
ILOCCURS

I'

I'ZERQoCR08SING
DETECTED

JILr-~ ~~ I"- r-u-t-~ ~

r

INTERNAL
LATCH

r-u-t-r rut-

STATUS
OUTPUT
MODE
INPUT

INTERNAL U....T
MODE NDRM

SENtNPUT

C::::

(UAlIT TaRE)

::!7Il)OUTPUT
(UARTTBRL)

HIGH BYTE
DATA

-------- 1---

MIOOLEBYTE
DATA

--------

LOWeYTE

--------

DATA

U=

~

III

-

DATA VALID

------~~-

- ------..

= DON'T CARE

~-

~.

-------1"..- -

-

DATAYA~t:: ~.

-- ------.., -- r-

i'----/'
-------l~-- r-r------

-------t~--

r- ------

1\

...

DATA VALID

~-

------

- - - '" THREE-STATE HIOH IMPEDANCE

0346-17

Figure 13: Handshake - Typical UART Interface Timing
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY ANO FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3-36

~U~UI!..

ICL8052/ICL 7104 and ICL8068/ICL 7104

c;
rCD

o

(II
~

....

--fi;:NG

~OCROSSINGDETECTED

::~~:~ --1-+----01 "_'::UT=AR::.:T~MFO:::D:;.E_,,,-~-LL~1~;'~~""""1"-' ~ _-1-+--LATCH

STATUS OUTPUT
UNAFFECTED BY

STATUS

-I-+--

,,"U:::A:::R:.:.T;:M::::O:::DE~_ _ _ _ _

OUTPUT POSITIVE TRANSITION CAUSES

c;
.......r-

...o

II
:::I
Do

c;

MODE ENTRY INTO
INPUT UART MODe

rCD
o
GI

....CD
c;

I

HIGH

-t---~ ~-+-"\. ~_

I I

1.'--'- ,

~~! --------.. ~--i-i

________ .. Jo-

r,----IJ

DATAVA~It::}1------oIJo--t-1---- - - . Jo--

iiIEN _____ .r---i--+----~,
MIDDLE ~~!

r-

-""""1I

RRJj _ _ _ _ _ r---+~

_ _ _ _ _ _. . _ - - _

i

DATAVALq-

... _

-r---1

--+--\..

_ _ _ _ _ _ . , __

-.&..
LDW~m

_ _ _ _ _ _ _ _ -1 Jo-

B

------..

~----------oIJo_-

- - - = THREE-STATE HIGH IMPEDANCE

=DOHTCARE

Figure 14: Handshake Triggered By Mode

With the MODE input remaining high as in these exam·
pies, the converter will output the results of every conversion except those completed during a handshake operation.
By triggering the converter into handshake mode with a low
to high edge on the MODE input, handshake output sequences may be performed on demand. Figure 14 shows a
handshake output sequence triggered by such an edge. In
addition, the SEN input is shown as being low when the
converter enters handshake mode. In this case, the whole
output sequence is controlled by the SEN input, and the
sequence for the first (high order) byte is similar to the sequence for the other bytes. This diagram also shows the
output sequence taking longer than a conversion cycle.
Note that the converter still makes conversions, with the
STaTuS output and Run/Rold input functioning normally.
The only difference is that new data will not be latched
when in handshake mode, and is therefore lost.

-.&.- = THREE·STATE WITH PULLUP
0346-18

ters if the supply voltage "glitches" to a low enough value.
Additionally, if the supply voltage comes up too fast, this
clear pulse may be too narrow for reliable clearing. In gener·
ai, this is not a problem, but if the UART internal "MODE"
FIF should come up set, the byte and chip ENable lines will
become active outputs. In many systems this could lead to
bus conflicts, especially in non·handshake systems. In any
case, SEN should be high (held high for non-handshake
systems) to ensure that the MODE FIF will be cleared as
fast as possible (see Figure 12 for timing). For these and
other reasons, adequate supply bypass is recommended.

Oscillator
The ICL7104-14 is provided with a versatile three terminal
oscillator to generate the internal clock. The oscillator may
be overdriven, or may be operated as an RC or crystal oscillator.
Figure 15 shows the oscillator configured for RC operation. The internal clock will be of the same frequency and
phase as the voltage on the CLOCK 3 pin. The resistor and
capacitor should be connected as shown. The circuit will
oscillate at a frequency given by f = .45/RC. A 50 - 100kO
resistor is recommended for useful ranges of frequency. For
optimum 60Hz line rejection, the capacitor value should be
chosen such that 32768 (·16), 8192 (·14) clock periods is
close to an integral multiple of the 60Hz period.

Initial Clear Circuitry
The internal logic of the 7104 is supplied by an internal
regulator between V + + and Digital Ground. The regulator
includes a low-voltage detector that will clear various registers. This is intended to ensure that on initial power-up, the
control logic comes up in Auto-Zero, with the 2nd, 3rd, and
4th MSB bits cleared, and the "mode" F IF cleared (i.e. in
"direct" mode). This, however, will also clear these regis-

lNTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been charBcteriz9d but are not tested.

3·37

.......o
...

•

......~

ICL8052/ICL 7104 and ICL8068/ICL 7104

..I
()

POWER SUPPLY SEQUENCING

=::.

Because of the nature of the CMOS process used to fabricate the ICL7104, and the multiple power supplies used,
there are certain conditions of these supplies under which a
disabling and potentially damaging SCR action can occur.
All of these conditions involve the V + supply (nom. + 5V)
being more positive than the V + + supply. If there is any
possibility of this occuring during start-up, Shut down, under
transient conditions during operation, or when inserting a
PC board into a "hot" socket, etc., a diode should be placed
between V+ and V + + to prevent it. A germanium or
Schottky rectifier diode would be best, but in most cases a
silicon rectifier diode is adequate.

co

o
o

co

..I

~

"
o
......
C
1\1

24

26

25

CLOCK

CLOCK
1

3

"III'

losc = .45/RC

..I
()

Figure 15: RC Oscillator

=::.
&\I

II)

Note that CLOCK 3 has the same output drive as the bit outputs.

o

As a result of pin count limitations, the ICL7104-16 has
only CLOCK 1 and CLOCK 2 available, and cannot be used
as an RC oscillator. The internal clock will correspond to the
inverse of the signal on CLOCK 2. Figure 16 shows a crystal
oscillator Circuit, which can be used with both 7104 versions. If an external clock is to be used, it should be applied
to CLOCK 1. The internal clock will correspond to the signal
applied to this pin.

3
~

~

ANALOG AND DIGITAL GROUNDS

0346-19

Extreme care must be taken to avoid ground loops in the
layout of ICL8068 or ICL8052/7104 circuits, especially in
16-bit and high sensitivity circuits. It is most important that
return currents from digital loads are not fed into the analog
ground line. A recommended connection sequence for the
ground lines is shown in Figure 17.

APPLICATIONS INFORMATION
Some applications bulletins that may be found useful are
listed here:
A016 "Selecting AID Converters", by Dave Fullagar
A017 "The Integrating AID Converter", by Lee Evans
A018 "Do's and Dont's of Applying AID Converters", by
Peter Bradshaw and Skip Osgood
A025 "Building a Remote Data Logging Station", by Peter
Bradshaw
A030 "The ICL7104 - A Binary Output AID Converter for
Microprocessors", by Peter Bradshaw
R005 "Interfacing Data Converter & Microprocessors", by
Peter Bradshaw et ai, Electronics, Dec. 9, 1976.

'CAPACITOR VALUE
DEPENDS ON CRYSTAL.
TYP 0-30pF.

Figure 16: Crystal Oscillator

0346-20

BUf'
OUT

.I,:/"" --'VV\r- -

--1·

1

lIP
VIN

:~ER

REF
VOLTAGE

BUF
-IN

Vref

EXTERNAL
REFERENCE
(IF USED)

+15V

-15V

1 1

8068 PIN 2

0./

DIGITAL

LOGIC

K

I

OIGONO
ICL7104
PINZ

BOARDi
EDGE

I

.J:L

DEVICE PIN

lT Y
r
T
T

>SUPPLY
RETURN

I
EP)

+sv SUPPLY BYPASS CAPACITOR(S}

Figure 17: Grounding Sequence

0346-21

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but am not tested.

3-38

ICL7109
12-Bit p,P-Compatible
AID Converter
GENERAL DESCRIPTION

FEATURES

The ICL7109 is a high performance, CMOS, low power
integrating AID converter designed to easily interface with
microprocessors.
The output data (12 bits, polarity and overrange) may be
directly accessed under control of two byte enable inputs
and a chip select input for a simple parallel bus interface. A
UART handshake mode is provided to allow the ICL7109 to
work with industry-standard UARTs in providing serial data
transmission, ideal for remote data logging applications.
The RUN/HOLD input and STATUS output allow monitoring
and control of conversion timing.
The ICL7109 provides the user with the high accuracy,
low noise, low drift, versatility and economy of the dualslope integrating AI D converter. Features like true differential input and reference, drift of less than 1p. Vrc, maximum
input bias current of 10pA, and typical power consumption
of 20mW make the ICL7109 an attractive per-channel alternative to analog multiplexing for many data acquisition applications.

• 12 Bit Binary (Plus Polarity and Overrange) Dual
Slope Integrating Analog-to-Digital Converter
• Byte-Organized TTL-Compatible Three-State Outputs
and UART Handshake Mode for Simple Parallel or
Serial Interfacing to Microprocessor Systems
• RUN/HOLD Input and STATUS Output Can Be Used
to Monitor and Control Conversion Timing
• True Differential Input and Differential Reference
• Low Noise-Typically 15p.V pop
• 1pA Typical Input Current
• Operates At Up to 30 Conversions Per Second
• On-Chip Oscillator Operates With Inexpensive
3_58MHz TV Crystal Giving 7.5 Conversions Per
Second for 60Hz Rejection May Also Be Used With
An RC Network Oscillator for Other Clock
Frequencies

ORDERING INFORMATION
Part Number

Temp. Range

Package

ICL7109MDL
ICL71091DL
ICL71091JL
ICL7109CPL

-55'C to + 125'C
- 25'C to + 85'C
- 25'C to + 85'C
O'C to 70'C

40-Pin Ceramic DIP
40-Pin Ceramic DIP
40-Pin CERDIP
40-Pin Plastic DIP

f

TOP VIEW

GND---! 1 GND
Y+40 )---<>+5Y
2 STATUS
REF IN-39
3 POL
DIFFERENTIAL
REF CAP-39
REFERENCE
4 OR
HIGH
REF CAP + 37 ~::JI:1Io'F
ORDER
5 B12
REF IN .. 36
+
BYTE
, !l
R'
6811
INPUT HIGH
IN HI 35
vvOUTPUTS
• .O,"F
7810
INPUT lOW
IN lO 34
L- 889
GND
COMMON 33
INT
988
INT 32
ICl7109
II CAl .,""f"
'087
AZ 3'
11 86
8UF 30
LOW
ORDER
12 B5
REF OUT 29
BYTE
'3 B4
Y-28
lk!l - R E F I N +
'4 B3
OUTPUTS
SEND 27
'5 B2
RUN/HOLD 26
y+
'6 Bl
BUF OSC OUT 25
+SYc>-- 17 TesT
24k!l
osc SEL 24 ;.--GND
8YTE r
'8 LliEN
OSC OUT 23
19 HIm
CONTROLl
OSC IN 22
3.5795 MHz
INPUTS _ 20~
TY CRYSTAL
MODE 21

f

,. . . ,".':t:"".".

l

rU

·RINT = 20k( l FOR O.2V REF

• 200k!l FOR 2.0Y REF
0336-'
(See Figure 2 for typical connection to a UART or Microcomputer)

Figure 1: Pin Configuration and Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
301655-003

NOTE: AI! typical values have been characterized but are not tested.

3-39

.......~

ICL7109

2 ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (GND to V +) . . . . . . . . . . . .. + 6.2V
Negative Supply Voltage (GND to V-) ............. -9V
Analog Input Voltage (Lo or Hi) (Note 1) ........ V+ to VReference Input Voltage (Lo or Hi) (Note 1) ..... V+ to VDigital Input Voltage
V+ +0.3V
(Pins 2-27) (Note 2) ....................... GND -0.3V

Power Dissipation (Note 3)
Ceramic Package ...................... 1W @ + 85'C
Plastic Package .................... 500mW @ + 70'C
Operating Temperature
Ceramic Package (MDL) ........... - 55'C to + 125'C
Ceramic Package (IDL) .............. - 25'C to + 85'C
Plastic Package (CPL) .................. O'C to + 70'C
Storage Temperature ................ -65'C to + 150'C
Lead Temperature (Soldering, 10sec) ........... +300'C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
opBration of the device at these O( any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (V+ = +5V, v-= -5V, GND=OV, TA=25'C, fCLK = 3.58 MHz, unless
otherwise indicated.) Test circuit as shown on first page of this data sheet.
ANALOG SECTION
Symbol

Parameter

Test Conditions

Zero Input Reading

VIN=O.OV
Full Scale = 409.6mV

Ratiometric Reading

VIN=VREF
VREF=204.8mV

Non-Linearity (Max deviation
from best straight line fit)

Full Scale = 409.6mV to 2.048V
Over full operating temperature
range. (Note 4), (Note 6)

Roll-over Error (difference
in reading for equal pos. and
neg. inputs near full scale)

Full Scale = 409.6mV to 2.048V
(Note 5), (Note 6)

Min

-OOOOs

Typ

Max

Unit

Octal
±OOOOs +OOOOs
Reading

3777s

3777s
4000s

4000 8

Octal
Reading

-1

±.2

+1

Counts

-1

±.2

+1

Counts

CMRR

Common Mode Rejection Ratio

VCM ±1VVIN=OV
Full Scale=409.6mV

VCMR

Input Common Mode Range

Input Hi, Input Lo, Common (Note 4)

en

Noise (p-p value not
exceeded 95% of time)

VIN=OV
Full Scale = 409.6mV

15

IILK

Leakage current at Input

VIN = 0 All devices at 25'C
ICL7109CPL O'CsTAs + 70'C (Note 4)
ICL71091DL -25'CsTAs +85'C (Note 4)
ICL7109MDL -55'CsTAs + 125'C

1
20
100
2

10
100
250
5

pA
pA
pA
nA

0.2

1

",VI'C

1

5

ppm/'C

50

",VIV
V+ -1.0

V-+1.5

V
",V

Zero Reading Drift

VIN=OV R1 =00 (Note 4)

Scale Factor Temperature
Coefficient

VIN=408.9mV= > 7770s
reading
Ext. Ref. 0 ppm/'C (Note 4)

1+

Supply Current V + to
GND

VIN=O, Crystal Osc
3.58MHz test circuit

700

1500

",A

Isupp

Supply Current V + to V-

Pins 2-21 , 25, 26, 27, 29; open

700

1500

",A

VREF

Ref Out Voltage

Referred to V + , 25kO
between V+ and REF OUT

-2.8

-3.2

V

Ref Out Temp. Coefficient

25kO between V+ and REF OUT

-2.4

80

ppml'C

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

3-40

.o~on. (Ii
r-

ICL7109

.......

i

ELECTRICAL CHARACTERISTICS (V+ = +5V, V- = -5V, GND=OV, TA=25'C, unless otherwise
indicated.) Test circuit as shown on first page of this data sheet. (Continued)
DIGITAL SECTION
Symbol

Parameter

Test Conditions

VOH

Output High Voltage

IOUT=100fLA
Pins 2-16,18,19,20

VOL

Output Low Voltage

IOUT=1.6mA

Output Leakage Current

Pins 3-16 high impedance

Control 110 Pull up
Current

Pins 18, 19, 20VOUT=V+ -3V
MODE input at GND

Control 1/0 Loading

HBEN Pin 19 LBEN Pin 18 (Note 4)

VIH

Input High Voltage

Pins 18-21, 26, 27
referred to GND

Vil

Input Low Voltage

Pins 18-21, 26, 27
referred to GND

Min

Typ

3.5

4.3

Max

Unit

V

0.2

0.4

V

±.01

±1

fLA

5

fLA
50

2.5

pF
V

1

V

Input Pull-up Current

Pins 26,27 VOUT=V+ -3V

5

/LA

Input Pull-up Current

Pins 17, 24 VOUT=V+ -3V

25

/LA

Input Pull-down Current

Pin 21 VOUT=GND +3V

5

/LA

High

VOUT=2.5V

1

mA

OOH

Oscillator Output

OOl

Current

Low

VOUT=2.5V

1.5

mA

BOOH

Buffered Oscillator

High

VOUT=2.5V

2

mA

BOOl

Output Current

Low

VOUT=2.5V

5

mA

tw

MODE Input Pulse Width

(Note 4)

50

ns

NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ± 100I'A
2. Due to the SeR structure inherent in the process used to fabricate these devices, connecting any digital inputs or outputs to voltages greater than V +
or less than GND may cause destructive device latchup. For this reason it is recommended that no inputs from sources other than the same power
supply be applied to the ICL7109 before its power supply is established, and that in multiple supply systems the supply to the ICL7109 be activated first.
3. This limit refers to that of the package and will not be obtained during normal operation.
4. This parameter is not production tested, but is guaranteed by design.
S. Roll-over error for TA= - 55°C to + 125°C is ± 3 counts maximum.
6. A full scale voltage of 2.048V is used because a full scale voltage of 4.096V exceeds the devices Common Mode Voltage Range.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charsct8lized but are not tested

3-41

......~

~

ICL7109
TABLE 1: Pin Assignment and Function Description
Pin

Symbol

Description

Pin

t

GND

Digital Ground, OY. Ground return for all digital
logic.

2

STATUS

Output High during integrate and deintegrate
until data is latched.
Output Low when analog section is in AutoZero configuration.

3

POL

Polarity - HI for Positive input.

4

OR

Overrange - HI if Overranged.

5

B12

Bit12

6

Bll

Bitll

Symbol

21

MODE

Description
Input Low - Direct output mode where
CE7I15Al5 (Pin 20), HBEN (Pin 19) and LBEN
(Pin 18) act as inputs directly contrOlling byte
outputs.
Input Pulsed High - Causes immediate entry
into handshake mode and output of data as in
Figure 10.
Input High - Enables CE/[OAD (Pin 20),
HBEN (Pin 19), and LBEN (Pin 18) as
outputs, handshake mode will be entered and
data output as in Figures 8 and 9 at
conversion completion.

(Most Significant Bit)

7

Bl0

Bnl0

All

22

OSCIN

Oscillator Input

8

B9

Bit 9

three

23

OSCOUT

Oscillator Output

state

24

OSCSEL

Oscillator Select -Input high configures
OSC IN, OSC OUT, BUF OSC OUT as RC
oscillator - clock will be same phase and
duty cycle as BUF OSC OUT.
- Input low configures OSC IN, OSC OUT for
crystal oscillator - clock frequency will be
1/58 of frequency at BUF OSC OUT.

9

B8

Bit 8

10

B7

Bit 7

HI = true

output

11

BS

BitS

data

12

B5

Bit 5

bits

13

B4

Bit4

14

B3

Bn3

15

B2

Bit 2

16

Bl

Bnl

17

TEST

18

LBEN

25

BUF OSC OUT Buffered Oscillator Output

26

RUN/FiO[i)

Input High - Normal Operation.
Input Low - Forces all bit outputs high.
Note: This input is used for test purposes only.
Tie high if not used.

Input High - Conversions continuously
performed every 8192 clock pulses.
Input Low - Conversion in progress
completed, converter will stop in Auto-Zero 7
counts before integrate.

27

SEND

Low Byte Enable - With Mode (Pin 21) low,
and CE7I15Al5 (Pin 20) low, taking this pin low
activates low order byte outputs Bl - B8.

Input - Used in handshake mode to indicate
ability of an external device to accept data.
Connect to + 5Y if not used.

28

Y-

Analog Negative Supply - Nominally -5Y
with respect to GND (Pin 1).

29

REF OUT

Reference Yoltage Output - Nominally 2.8Y
down from Y' (Pin 40).

(Least Significant Bit)

- With Mode (Pin 21) high, this pin serves as a
low byte flag output used in handshake mode.
See Figures 8, 9, 10.
19

HBEN

High Byte Enable - With Mode (Pin 21) low,
and CE/LOAD (Pin 20) low, taking this pin low
activates high order byte outputs B9 - B12,
POL,OR.
- With Mode (Pin 21) high, this pin serves as a
high byte flag output used In handshake mode.
See Figures 8, 9, 10.

20

CE/LOAD

Chip Enable Load - With Mode (Pin 21) low.
CE/LOAD serves as a master output enable.
When high, Bl - B12, P~L, OR outputs are
disabled.
- With Mode (Pin 21) high, this pin serves as a
load strobe used in handshake mode. See
Figures 8, 9, 10.

30

BUFFER

Buffer Amplifier Output

31

AUTO-ZERO

Auto-Zero Node -Inside foil of CAZ

32

INTEGRATOR

Integrator Output - Outside foil of CINT

33

COMMON

Analog Common - System is Auto-Zeroed to
COMMON

34

INPUTLO

Differential Input Low Side

35

INPUT HI

Differential Input High Side

36

REF IN

37

REF CAP

38

REF CAP

Reference Capacitor Negative

39

REF IN

Differential Reference Input Negative

40

Y+

Positive Supply Yoltage - Nominally
with respect to GND (Pin 1).

+

Differential Reference Input Positive

+

Reference Capacitor Positive

+ 5V

Note: All dignallevels are positive true.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typic81 vaJU98 hsVB bssn chsracterlzsd but BI6 not tested.

3-42

.D~DIl.

ICL7109

n
r-

.......o
I&)

-SV
OND
.IV

1 V·

OND

'SV

2.TATUI

1000 pF

GND
.IV

3-8
"-III2.POL.OR

T'::;~I-------''I------+'''f-It~-\a

1-

V·40
REF IN- 311------... :- - -GND

=::::: :;,.,

TRU4
ORR"
DR It
TIRL 23
TIRE 22
MR21

• IV

17 niT
" tIIlI
21 MODI

20 erm!m

27 SEND

GND

CMOS UART

Iln=~1

3I1~:~~~~;.~

I~ ~ :

ItHIIN

13'1
14 FE
IS DE
" SFD

IGND

t - - - - - - ; 1--------i.IUF DIC OUT

2 DSC CONTROL
3 GND
4 RRD
5-12
RIRI-8

GND

AI'C~~
IN .. ~

.u

31
IUF30
REF OUT 21
V-2'

RUNiHOLaa

OSC IEL 24

INT

~v

INPUT

.15 F

HINT 2OkO O.2V AEF
_n2VRIF

.IV OROPIN
GND

ose OUT 23 ,------::JOSC IN 22

FOR ~OWIIT POW'" CONSUMPTION,
TlR'·T.... INN" SHOU&.D HAYl,OOtn
NLLUP "ISIITORI TO +SY

ICL71"
CMOS AID CONVERTER
0336-2

Figure 2A: Typical Connection Diagram UART Interface - To transmit latest result, send any word to UART

.,V
OND
.IV

'IV

40 v'
1 GND
17 TIST

ICL71"
QND

a

RUNJRl5IlS
2 STATUI
11 LIIR

.IV
'SV
_SV
-SV

ItRm

12-1t
080-087
QND

20-

iilho

RlFIN 3S
.REF CAP - 3t
RIF CAP. 37
REF IN. 31
IN HI 35
IN LO 34
COM 33
INT 32

=--OND
EXTERNAL
REFERENCE

1.F

:.NPUT
~N~'.F

.u31

aUF 30
REF OUT a

v-a

SEND 27
IUF OSC OUT 2'..
OSC SIL 2'
OSC OUT H
OIC IN 22
MODE 21

H.NT 2Ok0 O.2Y AEF.

-tV
.IV

_navRIF.

OND

0336-3

Figure 2B: Typical Connection Diagram Parallel Interface With 8048 Microcomputer
Auto-Zero Phase

DETAILED DESCRIPTION
Analog Section

During auto-zero three' things happen. First, input high
and low are disconnected from their pins and internally
shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback
loop is closed around the system to charge the auto-zero
capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the ioop, the AZ accuracy is limited only by
the noise of the system. In any case, the offset referred to
the input is less than 101-'V.
.

Figure 3 shows the equivalent circuit of the Analog Section of the ICL71 09. When the RUNIHOLD input is left open
or connected to V + , the circuit will perform conversions at a
rate determined by the clock frequency (8192 clock periods
per cycle). Each measurement cycle is divided into three
phases as shown in Figure 4. They are (1) Auto-Zero (AZ),
(2) Signal Integrate (I NT) and (3) Deintegrate (DE).

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characteriz9d but are not tested

3-43

.......~
...
S:!

ICL7109

CREF

AEFCAP,.

r--I

I
I
I

INPUT HIGH ~-()(}-""T-t---...,..---I----f
135

I

I
I
I

1

I

COMMONQt~-~-~

_ _~

6.2V

133

I

AZT FROM CONTROL
IN
LOGIC
DEINT (+) DIGITAL SECTION
DEINT(-)-

I

INPUTLOQr-()(}---~---------------~

134

I
I

I
29'-----+
~---------------------REF OUT

40

v+
0336-4

Figure 3: Analog Section

I
INTEGRATOH
OUTPUT

POLARITY
DETECTEO~

ZERO CROSSING
OCCURS
ZERO CROSSING

I

I
______~I~~~' ~
DETECTED
I
--~
I
I--AZ
PHASE I--i-'NT PHASE 1I~t---+-i-,..L-DEINT PHASE III---1--AZ-

INTERNAL CLOCK

h..r ~ J1J1I1h.. .Jl11SLfl.r' '1.I1J1..hn..r

INTERNAL LATCH

II.
1

II

II

h

II

I

I
I
I

I
I
I

I
I
1

I

STATUS OUTPUT I

I

2048
I
FIXED
I---COUNTS~ 2048
1
MIN.
I
COUNTS

I

I

NUMBER OF COUNTS TO ZERO CROSSING
PROPORTIONAL TO V,N

I

"

I "

I

4096 COUNTS---.j
MAX

I

""-AFTER ZERO CROSSING,
ANALOG SECTION WILL
BE IN AUTOZERO
CONFIGURATION
0336-5

Figure 4: Conversion Timing (RUN/HOLD Pin High)

Signal Integrate Phase

De-Integrate Phase

During signal integrate the auto-zero loop is opened, the
internal short is removed and the internal high and low inputs are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time of 2048 clock periods. Note that this differential voltage must be within the common mode range of
the inputs. At the end of this phase, the polarity of the integrated Signal is determined.

The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged (during
auto-zero) reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct
polarity to cause the integrator output to return to zero
crossing (established in Auto Zero) with a fixed slope. Thus
the time for the output to return to zero (represented by the
number of clock periods counted) is proportional to the input signal.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPAESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3-44

~U~UIL C;

ICL7109

r"'

reduced further. This will increase both noise and rollover
errors. To improve the performance, supplies of ± 6V may
be used.

Differential Input
The input can accept differential voltages anywhere within the common mode range of the input amplifier; or specifically from 1.0 volts below the positive supply to 1.5 volts
above the negative supply. In this range the system has a
CMRR of 86dB typical. However, since the integrator also
swings with the common mode voltage, care must be exercised to assure the integrator output does not saturate. A
worst case condition would be a large positive common
mode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator
positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the
recommended 4V full scale with some loss of accuracy. The
integrator output can swing within 0.3 volts of either supply
without loss of linearity.
The ICL7109 has, however, been optimized for operation
with analog common near digital ground. With power supplies of + 5V and - 5V, this allows a 4V full scale integrator
swing positive or negative thus maximizing the performance
of the analog section.

Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 100!,-A of quiescent current. They supply
20!,-A of drive current with negligible non-linearity. The integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 4.096 volt full scale, 200kO, is near optimum and similarly a 20kO, for a 409.6mV scale. For other
values of full scale voltage, RtNT should be chosen by the
relation
R
full scale voltage
tNT
20!,-A

Integrating Capacitor
The integrating capacitor CtNT should be selected to give
the maximum integrator output voltage swing without saturating the integrator (approximately 0.3 volt from either supply). For the ICL7109 with ± 5 volt supplies and analog
common connected to GND, a ± 3.5 to ± 4 volt integrator
output swing is nominal. For 7-% conversions per second
(61.72kHz clock frequency) as provided by the crystal oscillator, nominal values for CtNT and CAl are 0.15!,-F and
0.33!,-F, respectively. If different clock frequencies are used,
these values should be changed to maintain the integrator
output voltage swing. In general, the value of CtNT is given
by
(2048 x clock period)(20!,-A)
CtNT integrator output voltage swing

Differential Reference
The reference voltage can be generated anywhere within
the power supply voltage of the converter. The main source
of common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage,
the reference capacitor can gain charge (increase voltage)
when called up to deintegrate a positive signal but lose
charge (decrease voltage) when called up to deintegrate a
negative input signal. This difference in reference for (+) or
( -) input voltage will give a roll-over error. However, by
selecting the reference capacitor large enough in comparison to the stray capacitance, this error can be held to less
than 0.5 count for the worst case condition (see Component
Values Selection below).
The rOil-over error from these sources is minimized by
having the reference common mode voltage near or at analog COMMON.

An additional requirement of the integrating capacitor is
that it have low dielectric absorption to prevent rOil-over errors. While other types of capacitors are adequate for this
application, polypropylene capacitors give undetectable errors at reasonable cost up to 85'C. For the military temperature range, Teflon® capacitors are recommended. While
their dielectric absorption characteristics vary somewhat
from unit to unit, selected devices should give less than 0.5
count of error due to dielectric absorption.

Component Value Selection

Auto-Zero Capacitor

For optimum performance of the analog section, care
must be taken in the selection of values for the integrator
capacitor and resistor, auto-zero capacitor, reference voltage, and conversion rate. These values must be chosen to
suit the particular application.
The most important consideration is that the integrator
output swing (for full-scale input) be as large as possible.
For example, with ±5V supplies and COMMON connected
to GND, the nominal integrator output swing at full scale is
± 4V. Since the integrator output can go to 0.3V from either
supply without significantly affecting linearity, a 4V integrator output swing allows 0.7V for variations in output swing
due to component value and oscillator tolerances. With
± 5V supplies and a common mode range of ± 1V required,
the component values should be selected to provide ± 3V
integrator output swing. Noise and rollover errors will be
slightly worse than in the ± 4V case. For larger common
mode voltage ranges, the integrator output swing must be

The size of the auto-zero capacitor has some influence
on the noise of the system: the smaller the capacitor the
lower the overall system noise. However, CAl cannot be
increased without limits since it, in parallel with the integrating capacitor forms an R-C time constant that determines
the speed of recovery from overloads and more important
the error that exists at the end of an auto-zero cycle. For
409.6mV full scale where noise is very important and the
integrating resistor small, a value of CAl twice CtNT is optimum. Similarly for 4.096V full scale where recovery is more
important than noise, a value of CAl equal to half of CtNT is
recommended.
For optimal rejection of stray pickup, the outer foil of CAl
should be connected to the R-C summing junction and ~he
inner foil to pin 31. Similarly the outer foil of CtNT should be
connected to pin 32 and the inner foil to the R-C summing
junction. Teflon®, or equivalent, capacitors are recommended above 85'C for their low leakage characteristics.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PAATICULAR USE.

NOTE All typ;cal values have been characterized but are not tested

3-45

.......
0

CD

.....

! ICL7109
~ Reference Capacitor

Note that if pins 29 and 39 are tied together and pins 39
and 40 accidentally shorted (e.g .• during testing). the reference supply will sink enough current to destroy the device.
This can be avoided by placing a 1kn resistor in series with
pin 39.

A 1J.tF capacitor gives good results in most applications.
However. where a large reference common mode voltage
exists (Le. the reference low is not at analog common) and
a 409.6mV scale is used. a larger value is required to prevent roll-over error. Generally 10J.tF will hold the roll-over
error to 0.5 count in this instance. Again. Teflon®. or equivalent capacitors should be used for temperatures above 85'C
for their low leakage characteristics.

DETAILED DESCRIPTION
Digital Selection
The digital section includes the clock oscillator and scaling circuit. a 12-bit binary counter with output latches and
TTL-compatible three-state output drivers. polarity. overrange and control logic. and UART handshake logic. as
shown in Figure 5.
Throughout this description. logic levels will be referred to
as "fow" or "high". The actual logic levels are defined in the
Electrical Characteristics Table. For minimum power consumption. all inputs should swing from GND (low) to V+
(high). Inputs driven from TTL gates should have 3-5kn
pullup resistors added for maximum noise immunity.

Reference Voltage
The analog input required to generate a full scale output
of 4096 counts is VIN = 2VREF. Thus for a normalized scale.
a reference of 2.048V should be used for a 4.096V full
scale. and 204.8mV should be used for a 0.4096V full scale.
However. in many applications where the AID is sensing
the output of a transducer. there will exist a scale factor
other than unity between the absolute output voltage to be
measured and a desired digital output. For instance. in a
weighing system. the designer might like to have a full scale
reading when the voltage from the transducer is 0.682V.
Instead of dividing the input down to 409.6mV. the input
voltage should be measured directly and a reference voltage of 0.341V should be used. Suitable values for integrating resistor and capacitor are 33kn and 0.15J.tF. This avoids
a divider on the input. Another advantage of this system
occurs when a zero reading is desired for non-zero input.
Temperature and weight measurements with an offset or
tare are examples. The offset may be introduced by connecting the voltage output of the transducer between common and analog high. and the offset voltage between common and analog low. observing polarities carefully. However. in processor-based systems using the ICL7109. it may
be more efficient to perform this type of scaling or tare subtraction digitally using software.

MODE Input
The MODE input is used to control the output mode of the
converter. When the MODE pin is low or left open (this input
is provided with a pulldown resistor to ensure a low level
when the pin is left open). the converter is in its "Direct"
output mode. where the output data is directly accessible
under the control of the chip and byte enable inputs. When
the MODE input is pulsed high. the converter enters the
UART handshake mode and outputs the data in two bytes.
then returns to "direct" mode. When the MODE input is left
high. the converter will output data in the handshake mode
at the end of every conversion cycle. (See section entitled
"Handshake Mode" for further details).

STATUS Output

Reference Sources

During a conversion cycle. the STATUS output goes high
at the beginning of Signal Integrate (Phase II). and goes low
one-half clock period after new data from the conversion
has been stored in the output latches. See Figure 4 for details of this timing. This signal may be used as a "data valid"
flag (data never changes while STATUS is low) to drive interrupts. or for monitoring the status of the converter.

The stability of the reference voltage is a major factor in
the overall absolute accuracy of the converter. The resolution of the ICL7109 at 12 bits is one part in 4096. or
244ppm. Thus if the reference has a temperature coefficient
of 80ppml"C (onboard reference) a temperature difference
of 3'C will introduce a one-bit absolute error.
For this reason. it is recommended that an external highquality reference be used where the ambient temperature is
not controlled or where high-accuracy absolute measurements are being made.
The ICL7109 provides a REFerence OUTput (pin 29)
which may be used with a resistive divider to generate a
suitable reference voltage. This output will sink up to about
20mA without significant variation in output voltage. and is
provided with a pullup bias device which sources about
10J.tA. The output voltage is nominally 2.8V below V+. and
has a temperature coefficient of ± 80ppml"C typo When using the onboard reference. REF OUT (Pin 29) should be
connected to REF - (pin 39). and REF + should be connected to the wiper of a precision potentiometer between
REF OUT and V+. The circuit for a 204.8mV reference is
shown in the test circuit. For a 2.048mV reference. the fixed
resistor should be removed. and a 25kn precision potentiometer between REF OUT and V+ should be used.

RUN/HOLD Input
When the RUN/HOLD input is high. or left open. the circuit will continuously perform conversion cycles. updating
the output latches after zero crossing during the Deintegrate (Phase III) portion of the conversion cycle (See Figure
4). In this mode of operation. the conversion cycle will be
performed in 8192 clock periods. regardless of the resulting
value.
If RUN/HOLD goes low at any time during Deintegrate
(Phase III) after the zero crossing has occurred. the circuit
will immediately terminate Deintegrate and jump to AutoZero. This feature can be used to eliminate the time spent in
Deintegrate after the zero-crossing. If RUN/HOLD stays or
goes low. the converter will ensure minimum Auto-Zero
time. and then wait in Auto-Zero until the RUN/HOLD input
goes high. The converter will begin the Integrate (Phase II)
portion of the next conversion (and the STATUS output will
go high) seven clock periods after the high level is detected
at RUN/HOLD. See Figure 6 for details.

lNTERSIL'S SOLE AND EXCLUSiVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOT£: All typical values have been characterized but are not tested.

3-46

~O~OIl.

ICL7109

TEST

t

HIGH ORDER ~ LOW ORDER

BYTE OUTPUTS

POL OR

BYTE OUTPUTS

;-;I

o

CD

BBBBBBBBBBBB
12 11 10 9 8 7 6 5 4 3 2 1

17

[:=~~::::::~~'8~~

HiiEN
CEiLi5AI'i

19

20

I
I
I

I
I
I
I

I
I
I

COMP OUT
TO AZ
ANALOG { INT
SECTION DEINT("t')
DEINT(-)
~"',...----r....l

STATUS

RUN/

HOiJ'i

I
I
I

---i-J

_21 _ _ 27
MODE
SEND

asc osc osc aUF

GND

IN OUT SEL OSC
OUT

0336-6

Figure 5: Digital Section

-------

~:':R6E~~6~~i~~

f---A~~~~~~O-J

t-:::'~SE"

"
I MIN 1790 COUNTS I. STATIC IN
I
..--~TECTION
--...... '_J'\.I
MAX 2041 COUNTS I HOLD STATE
~ .--+-1 1 - - 7 COUNTS------"; - - - ...
INTERNAL CLOCK Lr '111.I1J'1..
.l1IU1.rtI1J1.. ..11J1.nn.n..
~
-uu-t.rtnnJ1Jl.
I
I
INTERNAL LATCH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...n
I
I
INTEGRATOR
OUTPUT

STATUS OUTPUT
RUN/HOLD INPUT

======~--;":...----------------------..,L_rI..__

r--

-.J L ________:___ _
0336-7

Figure 6: Run/Hold Operation
Using the RUN/HOLD input in this manner allows an
easy "convert on demand" interface to be used. The converter may be held at idle in auto-zero with RUN/HOLD low.
When RUN/HOLD goes high the conversion is started, and
when the STATUS output goes low the new data is valid (or
transferred to the UART - see Handshake Mode). RUN/
HOLD may now be taken low which terminates deintegrate
and ensures a minimum Auto-Zero time before the next
conversion.
Alternately, RUN/HOLD can be used to minimize conversion time by ensuring that it goes low during Deintegrate,
after zero crossing, and goes high after the hold point is
reached. The required activity on the RUN/HOLD input can
be provided by connecting it to the Buffered Oscillator Output. In this mode the conversion time is dependent on the
input value measured. Also refer to Intersil Application BUlletin A032 for a discussion of the effects this will have on
Auto-Zero performance.

If the RUN/HOLD input goes low and stays low during
Auto-Zero (Phase I), the converter will simply stop at the
end of Auto-Zero and wait for RUN/HOLD to go high. As
above, Integrate (Phase II) begins seven clock periods after
the high level is detected.

Direct Mode
When the MODE pin is left at a low level, the data outputs
(bits 1 through 8 low order byte, bits 9 through 12, polarity
and over-range high order byte) are accessible under control of the byte and chip enable terminals as inputs. These
three inputs are all active low, and are provided with pullup
resistors to ensure an inactive high level when left open.
When the chip enable input is low, taking a byte enable
input low will allow the outputs of that byte to become active
(three-stated on). This allows a variety of parallel data accessing techniques to be used, as shown in the section entitled "Interfacing." The timing requirements for these outputs are shown in Figure 7 and Table 2.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have bgen characterized but are not tested.

3-47

(;
...r-....

GI

....0....
...

ICL7109
ICL7109 provides all the control and flag signals necessary
to sequentially transfer two bytes of data into the UART and
initiate their transmission in serial form. This greatly eases
the task and reduces the cost of designing remote data acquisition stations using serial data transmission.
Entry into the handshake mode is controlled by the
MODE pin. When the MODE terminal is held high, the
ICL7109 will enter the handshake mode after new data has
been stored in the output latches at the end of a conversion
(See Figures 8 and 9). The MODE terminal may also be
used to trigger entry into the handshake mode on demand.
At any time during the conversion cycle, the low to high
transition of a short pulse at the MODE input will cause
immediate entry into the handshake mode. If this pulse occurs while new data is being stored, the entry into handshake mode is delayed until the data is stable. While the
converter is in the handshake mode, the MODE input is
ignored, and although conversions will still be performed,
data updating will be inhibited (See Figure 10) until the converter completes the output cycle and clears the handshake
mode.
When the converter enters the handshake mode, or when
the MODE input is high, the chip and byte enable terminals
become TTL-compatible outputs which provide the control
signals for the output cycle (See Figures 8, 9, and 10).
In handshake mode, the SEND input is used by the converter as an indication of the ability of the receiving device
(such as a UART) to accept data.
Figure 8 shows the sequence of the output cycle with
SEND held high. The handshake mode (Internal MODE
high) is entered after the data latch pulse, and since MODE
remains high the CE/LOAD, LBEN and HBEN terminals are
active as outputs. The high level at the SEND input is
sensed on the same high to low internal clock edge that
terminates the data latch pulse. On the next low to high
internal clock edge the CE/LOAD and the HBEN outputs
assume a low level, and the high-order byte (bits 9 through
12, POL, and OR) outputs are enabled. The CE/LOAD output remains low for one full internal clock period only, the
data outputs remain active for 1-% internal clock periods,
and the high byte enable remains low for two clock periods.
Thus the CE/LOAD output low level or low to high edge
may be used as a synchronizing signal to ensure valid data,
and the byte enable as an output may be used as a byte
identification flag. With SEND remaining high the converter
completes the output cycle using CE/LOAD and LBEN
while the low order byte outputs (bits 1 through 8) are activated. The handshake mode is terminated when both bytes
are sent.
Figure 9 shows an output sequence where the SEND input is used to delay portions of the sequence, or handshake
to ensure correct data transfer. This timing diagram shows
the relationships that occur using an industry-standard
IM640% CMOS UART to interface to serial data channels.
In this interface, the SEND input to the ICL7109 is driven by
the TBRE (Transmitter Buffer Register Empty) output of the
UART, and the CE/LOAD terminal of the ICL7109 drives
the TBRL (Transmitter Buffer Register Load) input to the
UART. The data outputs are paralleled into the eight Transmitter Buffer Register inputs.

Table 2 - Direct Mode Timing
Requirements

!:!

(See Note 4 of Electrical Characteristics)
SYMBOL

DESCRIPTION

MIN

TYP

tBEA

Byte Enable Width

350

220

tOAB

Data Access Time
from Byte Enable

210

350

ns

tOHB

Data Hold Time
from Byte Enable

150

300

ns

tCEA

Chip Enable Width

tOAC

Data Access Time
from Chip Enable

260

400

ns

tOHC

Data Hold Time
from Chip Enable

240

400

ns

400

MAX

UNIT

ns

260

ns

IIImI

AS INPUT

[J!R
AS INPUT

LOW:!:::: ______________

~

~_

- - - - = HIGH IMPEDANCE

0336-8

Figure 7: Direct Mode Output Timing
It should be noted that these control inputs are asynchronous with respect to the converter clock - the data may be
accessed at any time. Thus it is possible to access the
latches while they are being updated, which could lead to
erroneous data. Synchronizing the access of the latches
with the conversion cycle by monitoring the STATUS output
will prevent this. Data is never updated while STATUS is
low.

Handshake Mode
The handshake output mode is provided as an alternative
means of interfacing the ICL7109 to digital systems, where
the AID converter becomes active in controlling the flow of
data instead of passively responding to chip and byte enable inputs. This mode is specifically designed to allow a
direct interface between the ICL7109 and industry-standard
UARTs (such as the Intersil1M6402/3) with no external logic required. When triggered into the handshake mode, the

tNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valU9s have been characterized but are not tested.

3-48

ICL7109
UROCROUIHG

"-

lNTlGRATOft
OUTPUT

INTERNAL
CLOCI(

INTERNAL

L
HRO eRO"'NO
!/DITECTED

IOCCURS

~~t--~t--~r-rtr-

LATCH

STATUI
OUTPUT

110"
INPUT
MODE HIGH ACTIVATeS

INTERNAL UART
MODE NDO.

CI1mD,~, tIIR

---

.....

INPUT

HIGHaYrE
DATA

LOWBYT£

DATA

-

1.:=, /"

f.--......____
liN'

J

"".1 _.1_

'~~DI LOW. NOT

k::: ~_.1_

J

1\

--------\------

:=~:~Dlf!7mID.RI1

DATA-VALID

1---

---------r---

------------ --- ---------r---

DATAYALID

_"'GoneM!

_.L_..t.._

- - - - = THIIH·I'ATE HIGH .PlDANCI

TIRMINATI,
UMTMODI

,tIIR

~:'s===

--- ------TttfID-ITATIWlTHIIUI.LIJP

0336-9

Figure 8: Handshake With Send Held Positive

INTIRNAl.
CLOCK

INTERNAL

LATCH _ _ _ _.....I

STATUI - - - - - - - /

OUTPUT
INPUT
"O.E

1--+----- ,...-+-t----- --1-+---

- - i ' l. .I1111111111 . . . . ._

_ _ _ _-

- I,....-+-----.. ,...--+-+------ --+--tTlRMINATII

INTERNAL UART

MODE ::NO:::;"::"_ _ _ _

SfND INPUT
(UART
TaRE)

\IM'MODI

11J1lIIIIlIIIIlIIIIlIIIIlII1IIrr'
:::::f=:::'--;;>.
.I

~OUTPUT
(UARTT8R1.) ------~-~
iiiiR

-------+-_l,

HIGH:m _________ _

'-----<

- -------11------ ----

LowaTTI

DA'AVAUI) _ _~-,r

DATA - - - - - - - - - -

III .

DON'T CARl!

- - - - .. THflII4TATI HIGH IMPEDANCE

0336-10

Figure 9: Handshake - Typical UART Interface Timing

tNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been characterized but are not tested.

3-49

•

.....g ICL7109
~

UIIOCR08$ING
OC:CURS
ZERO CROSSING DETECTED

::
STATUS

~

_ - + - + - - - - -_ _-+....:p:..::::=..1.,;;...."'-1_--!-.....,f----

OUTPUT

POSITIVE TRANSITION CAUSIlS

=~ ~~YM':~ '"

11I'1I.1l111l1l11l.1l.!I.mllllll'.~___

_--1--1-----_ - - - ! - - I - - - - - - _--!--IURMINATES
UAATMOOE

I

I

, . . - - - - -..

HIGtt:m __________

~

LiiN _.1_...1 __V - LOW:~:

__________ ...,
•

• DON'" CARl

~----

OATAVALID

-

~-_+-_l

-------~I---

---..1------ --+--{
'-----

-

)oj

~--------

---

. . _--..( ,. . __

.!._...!._

--+~

.J._.i_

DATA VALID

=THAII-ITATI: HIGH IMPEDANCE _.1._ .. THREe-STATE WITH PULL-UP
0336-11

Figure 10: Handshake Triggered By Mode
With the MODE input remaining high as in these examples, the converter will output the results of every conversion except those completed during a handshake operation.
By triggering the converter into handshake mode with a low
to high edge on the MODE input, handshake output sequences may be performed on demand. Figure 9 shows a
handshake output sequence triggered by such an edge. In
addition, the SEND input is shown as being low when the
converter enters handshake mode. In this case, the whole
output sequence is controlled by the SEND input, and the
sequence for the first (high order) byte is similar to the sequence for the second byte. This diagram also shows the
output sequence taking longer than a conversion cycle.
Note that the converter still makes conversions, with the
STATUS output and RUN/HOLD input functioning normally.
The only difference is that new data will not be latched
when in handshake mode, and is therefore lost.

Assuming the UART Transmitter Buffer Register is empty,
the SEND input will be high when the handshake mode is
entered after new data is stored. The CE/LOAD and HBEN
terminals will go low after SEND is sensed, and the high
order byte outputs become active. When CE/LOAD goes
high at the end of one clock period, the high order byte data
is clocked into the UART Transmitter Buffer Register. The
UART TBRE outP~ will now go low, which halts the output
cycle with the HB N output low, and the high order byte
outputs active. When the UART has transferred the data to
the Transmitter Register and cleared the Transmitter Buffer
Register, the TBRE returns high. On the next ICL7109 internal clock high to low edge, the high order byte outputs are
disabled, and one-half internal clock later, the HBEN output
returns high. At the same time, the CE/LOAD and LBEN
outputs go low, and the low order byte outputs become active. Similarly, when the CE/LOAD returns high at the end of
one clock period, the low order data is clocked into the
UART Transmitter Buffer Register, and TBRE again goes
low. When TBRE returns to a high it will be sensed on the
next ICL7109 internal clock high to low edge, disabling the
data outputs. One-half internal clock later, the handshake
mode will be cleared, and the CE/LOAD, HBEN, and LBEN
terminals return high and slay active (as long as MODE
stays high).

Oscillator
The ICL7109 is provided with a versatile three terminal
oscillator to generate the internal clock. The oscillator may
be overdriven, or may be operated with an RC network or
crystal. The OSCILLATOR SELECT input changes the internal configuration of the oscillator to optimize it for RC or
crystal operation.

INTERSll·S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charsctsrfZBd but srB not test9d.

3,50

[lJD~DIl.

ICL7109
When the OSCILLATOR SELECT input is high or left
open (the input is provided with a pullup resistor), the oscillator is configured for RC operation, and the internal clock
will be of the same frequency and phase as the signal at the
BUFFERED OSCILLATOR OUTPUT. The resistor and capacitor should be connected as in Figure 11. The circuit will
oscillate at a frequency given by f=0.45/RC. A 100k!1 resistor is recommended for useful ranges of frequency. For
optimum 60Hz line rejection, the capacitor value should be
chosen such that 2048 clock periods is close to an integral
multiple of the 60Hz period (but should not be less than
50pF).

If at any time the oscillator is to be overdriven, the overdriving signal should be applied at the OSCILLATOR INPUT, and the OSCILLATOR OUTPUT should be left open.
The internal clock will be of the same frequency, duty cycle,
and phase as the input signal when OSCILLATOR SELECT
is left open. When OSCILLATOR SELECT is at GND, the
clock will be a factor of 58 below the input frequency.
When using the ICL71 09 with the IM6403 UART, it is possible to use one 3.58MHz crystal for both devices. The
BUFFERED OSCILLATOR OUTPUT of the ICL7109 may be
used to drive the OSCILLATOR INPUT of the UART, saving
the need for a second crystal. However, the BUFFERED
OSCILLATOR OUTPUT does not have a great deal of drive
capability, and when driving more than one slave device,
external buffering should be used.

-r
SEL

22

23

25

osc

OSC
OUT

BUFFERED
OSC
OUT

IN

When the TEST input is taken to a level halfway between
V+ and GND, the counter output latches are enabled, allowing the counter contents to be examined anytime.
When the TEST input is connected to GND, the counter
outputs are all forced into the high state, and the internal
clock is disabled. When the input returns to the % (V +
-GND) voltage (or to V+) and one clock is applied, all the
counter outputs will be clocked to the low state. This allows
easy testing of the counter and its outputs.

----

R
C

V+ OR OPEN

f osc =.45IRC
0336-12

Figure 11: RC Oscillator

INTERFACING
Direct Mode

When the OSCILLATOR SELECT input is Iowa feedback
device and output and input capacitors are added to the
oscillator. In this configuration, as shown in Figure 12, the
oscillator will operate with most crystals in the 1 to 5MHz
range with no external components. Taking the OSCILLATOR SELECT input low also inserts a fixed + 58 divider
circuit between the BUFFERED OSCILLATOR OUTPUT
and the internal clock. Using an inexpensive 3.58MHz TV
crystal, this division ratio provides an integration time given
by:
T = (2048 clock periods) x

Figure 13 shows some of the combinations of chip enable
and byte enable control signals which may be used when
interfacing the ICL71 09 to parallel data lines. The CE/LOAD
input may be tied low, allowing either byte to be controlled
by its own enable as in Figure 13A. Figure 138 shows a
configuration where the two byte enables are connected
together. In this configuration, the CE/LOAD serves as a
chip enable, and the HBEN and LBEN may be connected to
GND or serve as a second chip enable. The 14 data outputs
will all be enabled simultaneously. Figure 13C shows the
HBEN and LBEN as flag inputs, and CE/LOAD as a master
enable, which could be the READ strobe available from
most microprocessors.
Figure 14 shows an approach to interfacing several
ICL7109s to a bus, ganging the HBEN and i1iEN Signals to
several converters together, and using the CE/LOAD inputs
(perhaps decoded from an address) to select the desired
converter.

[~M8
] = 33.18ms
3.58 Hz

This time is very close to two 60Hz periods or 33.33ms. The
error is less than one percent, which will give better than
40dB 60Hz rejection. The converter will operate reliably at
conversion rates of up to 30 per second, which corresponds
to a clock frequency of 245.8kHz.
v+--~-------1~

24

ISEL

GND

G

Test Input

24

-t~

,..c;...
...0

osc
IN

osc

o

OUT

BUFFERED

osc

OUT

CRYSTAL

0336-13

Figure 12: Crystal Oscillator

INTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

3-51

•

.....g.... ICL7109

5:!

A.

GND

C.
8.

CHIP SELECT

GND

CHIP SELECT 1

GND

B9-812
POL, OR

89-B12
POL. OR

81~B12

81-88

POL. OR

14
B1-B8

ICL7109

ANALOG
IN

ANALOG

RUN/HOt:D

ICL7109

ANALOG
IN

ICL7109

IN
CONVERT

RUN/HOLD
RUN/iiOLD

CONVERT

CONVERT

CONTROL
BYTE FLAGS

0336-14

0336-16

0336-15

Figure 13: Direct Mode Chip and Byte Enable Combinations

CONVERTER
SELECT

CONVERTER
SELECT

CONVERTER
SELECT

8-BITBUS

GND

GND
MODE

CE/LOAD

GND
MODE

89·812
POL,OR

~

MODE

B9-B12
POL. OR

ICL7109

89-B12
POL. OR

a'-B8

ANALOG

8

B1-B8

ANALOG

IN

6

ICU109

tCL7109

81·88

~

8

ANALOG

IN

IN

.sv

RUN/HOLD

RUN/HOLD

-sv

LBEN

BYTE SELECT FLAGS

<
0336-17

Figure 14: Tri-stating Several 7109's to a Small Bus
Some practical circuits utilizing the parallel three-state
output capabilities of the ICL7109 are shown in Figures 15
through 20. Figure 15 shows a straightforward application to
the Intel 8048/80/85 microprocessors via an 8255PPI,
where the ICL7109 data outputs are active at all times. The
1/0 ports of an 8155 may be used in the same way. This
interface can be useJ ~" a read-anytime mode, although a
read performed while the u;;.t8. latches are being updated
will lead to scrambled data. This will occur very rarely, in the
proportion of setup-skew times to conversion time. One way
to overcome this is to read the STATUS output as well, and
if it is high, read the data again alter a delay of more than %

converter clock period. If STATUS is now low, the second
reading is correct, and if it is still high, the first reading is
correct. Alternatively, this timing problem is completely
avoided by using a read-alter-update sequence, as shown
in Figure 16. Here the high to low transition of the STATUS
output drives an interrupt to the microprocessor causing it
to access the data latches. This application also shows the
RUNIHOLD input being used to initiate conversions under
software control.
A similar interface to Motorola MC6800 or Rockwell
R650X systems is shown in Figure 17. The high to low transition of the STATUS output generates an interrupt via the

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHAll BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE All typical values have been characterized but are not tested.

3-52

ICL7109

(

~

ADDRESS BUS

I I

~

I I

1''1
I I

D

t} ~J

CDNTRDL BUS

I I

<

I I
DATA BUS

GND

I

I

MOOE

CEILOAD

~J ~} ~J

RD WA

89-BI2
PDL. DR

6

07-00

PAs-PAs

AO-A1

S
\

a

RUNIHOLD - + 5 V

ICl7109

9

a

Bl-B8

PBr-PBo

8255
(MDDEO)

8008.8080.
8085._ETC

r
STATUS

IN

GND

HiiiN

LiEN

I

I

r-S£Ewrr-

PCs

0336-18

Figure 15: Full-time Parallel Interface to 8048/80/85 Microprocessors

(

ADDRESS BUS

1r

I I

)

CDNTRDLBUS

I I

(

I I

I I

I I

DATA BUS
GND

I

I

MDDE

CEILDAD
89-812
POL. DR

tJ

RD
6

WR

t}
D7-DO

tJ

~J

AG·Al

t}

S

"S

~J

a

PAs·PAc

V
PC<;

RUNIHOLD
ICL7101

9

STATUS

IN

HI

GND

LBEN

I

I

8008.8080.

P87-PBo

J
STS"

1.F

HiiiN

8255

a

Bl-B8

8085._ETC

PC.

IOkH
PC<;

INTRA

INTR

+5V
SEE TEXT

0336-19

Figure 16: Full-time Parallel Interface to 8048/80/85 Microprocessors With Interrupt
Control Register B CBl line. Note that CB2 controls the
RUN/HOLD pin through Control Register B. allowing soft·
ware·controlled initiation of conversions in this system as
well.
The three·state output capability of the ICL7109 allows
direct interfacing to most microprocessor busses. Examples
of this are shown in Figures 18 and 19. It is necessary to
carefully consider the system timing in this type of interface.

to be sure that requirements for setup and hold times. and
minimum pulse widths are met. Note also the drive limita·
tions on long buses. Generally this type of interface is only
favored if the memory peripheral address density is low so
that simple address decoding can be used. Interrupt han·
dling can also require many additional components. and us·
ing an interface device will usually simplify the system in this
case.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3-53

•

......... ICL7109
CI

0

5i

GNO

MODE
89-812
POL,OR
ICL7109
81 ....
ANALOG
IN

•
•

PA0-6
CRI!--llR-Gll

MC880X
OR
MCS850X

P80-7
MC8820

STATUS

Cll

RUNIHOLO

CI2

GND
ADDRESS
IUS

DATA
IUS

CONTROL
IUS
0336-20

Figure 17: Full-time Parallel Interface to MC680X or MCS650X Microprocessors

eooa, SOlO, 8085

ICL7109
I1-BS

8

ANALOG
IN

CEiLciADt------'
°MEMR 01iOii
lar IlO8O/822II System

GND

+5V
0336-21

Figure 18: Direct Interface -ICL7109 to 8080/8085

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AN typ/c8I VBIuBs

""vo

~

_ _ but aro not tested.
3-54

ICL7109

GND

89-812

POL. OR

MctIOX
OR

"NALOG
IN

MCS850X
H1BIrnr-------------~

~~------------~

ADDRESS
BUS

D"TA
BUS

CONTROL
BUS

0336-22

Figure 19: Direct ICL7109 - MC680X Bus Interface
under software control. Note that one port of the 8255 is not
used, and can service another peripheral device. The same
arrangement can also be used with the 8155.
Figure 21 shows a similar arrangement with the MC6800
or MCS650X microprocessors, except that both MODE and
RUN/HOlD are tied high to save port outputs.
The handshake mode is particularly convenient for directly interfacing to industry standard UARTs (such as the Intersil IM6402/6403 or Western Digital TR1602) providing a
minimum component count means of serially transmitting
converted data. A typical UART connection is shown in Figure 2A. In this circuit, any word received by the UART causes the UART DR (Data Ready) output to go high. This drives
the MODE input to the ICl7109 high, triggering the ICl7109
into handshake mode. The high order byte is output to the
UART first, and when the UART has transferred the data to
the Transmitter Register, TBRE (SEND) goes high and the
second byte is output. When TBRE (SEND) goes high
again, lBEN will go high, driving the UART ORR (Data
Ready Reset) which will signal the end of the transfer of
data from the ICl7109 to the UART.
Figure 22 shows an ex1ension of the one converterone UART scheme to severallCl7109s with one UART. In
this circuit, the word received by the UART (available at the
RBR outputs when DR is high) is used to select which converter will handshake with the UART. With no external components, this scheme will allow up to eight ICl7109s to interface with one UART. Using a few more components to
decode the received word will allow up to 256 converters to
be accessed on one serial line.

Handshake Mode
The handshake mode allows ready interface with a wide
variety of external devices. For instance. external latches
may be clocked by the rising edge of CE/lOAD, and the
byte enables may be used as byte identification flags or as
load enables.
Figure 20 shows a handshake interface to Intel microprocessors again using an 8255PPI. The handshake operation with the 8255 is controlled by inverting its Input Buffer
Full (IBF) flag to drive the SEND input to the ICl71 09, and
using the CE/LOAD to drive the 8255 strobe. The internal
control register of the PPI should be set in MODE 1 for the
port used. If the 7109 is in handshake mode and the 8255
IBF flag is low, the next word will be strobed into the port.
The strobe will cause IBF to go high (SEND goes low),
which will keep the enabled byte outputs active. The PPI will
generate an interrupt which when executed will result in the
data being read. When the byte is read, the IBF will be reset
low, which causes the ICl7109 to sequence into the next
byte. This figure shows the MODE input to the ICl7109 connected to a control line on the PPI. If this output is left high.
or tied high separately, the data from every conversion (provided the data access takes less time than a conversion)
will be sequenced in two by1es into the system.
If this output is made to go from low to high, the output
sequence can be obtained on demand, and the interrupt
may be used to reset the MODE bit. Note that the RUNI
HOLD input to the ICl7109 may also be driven by a bit of
the 8255 so that conversions may be obtained on command

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

~~~~:~~~~JL~T~~~L~ ~~N~~~L~~~V~ ::~TI~~~~ ~~t LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
NOTE All typical values have been characterized but are not tested

3-55

•

....

IID~DIL

: ICL7109

it

~

(

ADDIIE88aul

1"'1

I I

i

(

CONTROL.US

I I

~

~JWR

RD
81-.12

POL. DR
1eL71"
.1'"

8

---

CEiLDAD
lEND

IN

li
m.

~

I I

I I

JI

~J

~J

t} I I

DATA BUS

t}
D7-DO

AD·Al

~

Ci

PA,-PAo

_.8010.

121&

(MODI 1)

PC<

1015.I00I1 ETC

Pes

RUNIHOLD

Pes

MODE

PC?

Pes

INTR

0336-23

Figure 20: Handshake Interface -ICL7109 to 8048, 80/85

.sv-.....--..,

MCIIOO

ICL71"

OR.

MC8850X

ANALOG
IN
CA2

AODRESS

.US

DATA

BUS

CONTROl.
BuS

0336-24

Figure 21: Handshake Interface -ICL7109 to MC6800, MCS650X

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF BALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE:AH /ypk»I_havobHn

_but.,. not

tos/od.

3-56

IID~Dn.

ICL7109

p
...

..
o

CO

SERIAl. OUTPUT

IJ

_CUOSUART

•'-.1
ANALOG
IN

.'-.1 8
ANALOG
IN

RUN/HOLD

.'-.1 8
ANALOG
IN

RUN/HOLO

+5V

0336-25

Figure 22: Multiplexing Converters with Mode Input
The applications of the ICL7109 are not limited to those
shown here. The purpose of these examples is to provide a
starting point for users to develop useful systems, and to
show some of the variety of interfaces and uses of the
ICL7109. Many of the ideas suggested here may be used in
combination; in particular the uses of the STATUS, RUNI
HOLD, and MODE signals may be mixed.

APPLICATION NOTES
A016
A017
A018
A030
A032

ROOS

"Selecting AID Converters," by David Fullagar
"The Integrating AID Converters," by Lee Evans
"Do's and Don'ts of Applying AID Converters," by
Peter Bradshaw and Skip Osgood
"The ICL7104 - A Binary Output AID Converter for
Microprocessors," by Peter Bradshaw
"Understanding the Auto-Zero and Common Mode
Performance of the ICL7106 Family," by Peter
Bradshaw
"Interfacing Data Converters & Microprocessors,"
by Peter Bradshaw et ai, Electronics, Dec. 9, 1976.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AH!J'pk:IJI ..IuosMVObHn

_but_not_

3-57

•

D~D[6

...~ ICL7112
~

12-Bit High-Speed
g CMOS p.P-Compatible
AID Converter
GENERAL DESCRIPTION

FEATURES

The ICL7112 is a monolithic 12-bit resolution, fast successive approximation AID converter. It uses thin film resistors and CMOS circuitry combined with an on-chip PROM
calibration table to achieve 12-bit linearity without laser trimming. Special design techniques used in the DAC and comparator result in high speed operation, while the fully static
silicon-gate CMOS circuitry keeps the power dissipation
very low.
Microprocessor bus interfacing is eased by the use of
standard memory WRite and ReaD cycle timing and control
signals, combined with Chip Select and Address pins. The
digital output pins are byte-organized and three-state gated
for bus interface to 8- and 16-bit systems.
The ICL7112 provides separate Analog and Digital
grounds for increased system accuracy. Operating with
± 5V supplies, the ICL7112 accepts OV to + 10V input with
a -10V reference or OV to -10V input with a + 10V reference.

• 12·Bit Resolution and Accuracy
• No Missing Codes
• Microprocessor Compatible Byte·Organized Buffered
Outputs
• Auto-Zeroed Comparator for Low Offset Voltage
• Low Linearity and Gain Temperature Coefficients
• low Power Consumption (60 mW)
• No Gain or Offset Adjustment Necessary
• Provides 3% Useable Overrange
• Fast Conversion (30 ,..sec_)

ORDERING INFORMATION
Part
Number

Resolution
with No
Missing
Codes

Temperature
Range

Package

tCL7112JCDL
ICL7112KCDL

11 Bits
12 BHs

O'Cto +70'C
O'Cto +70'C

40 Pin Ceramio
40 Pin Ceramic

tCL7112JtDL
ICL7112KIDL

11 Bits
12 Bits

- 25'C to + 85'C
- 25'C to + 85'C

40 Pin Ceramio
40 Pin Ceramio

ICL7112JMDL
tCL7t12KMDL

11 Bits
12 Bits

- 55'C to + 125'C 40 Pin Ceramic
- 55'C to + 125'C 40 Pin Ceramio

NC
SC

AGND

OSC2

OSC!

CS

VREF

Ao

VIN
COMP

V"
AGND

DGND

CAZ

(MSB)D l1 8

WR
OSC2
OSC!

TEST

OVR

OVR

Dld MSB)
Do (LSB)

0107-1

Figure 1: ICl7112 Functional Diagram
0107-2

Figure 2: Pin Configuration
(Outline Dwg. Dl)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
301657-001
NOTE: All typ;caJ vsluss have b6en characterized but arB not tested.

3-58

ICL7112
Operating Temperature
ICL7112XCXX .......................... O·C to + 70·C
ICL7112XIXX ....................... - 2S·C to + 70·C

ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage V + to DGND ............ - 0.3V to + 6.SV
Supply Voltage V- to DGND ............ + 0.3V to -6.SV
VREF, VIN to DGND .............................. ± 2SV
AGND to DGND ........................... + 1V to -1V

ICL7112XMXX ..................... - SS·C to + 12S·C
Storage Temperature ................. -6S·C to + 1S0·C
Power Dissipation (Note 2) ...................... SOO mW

VREF, VIN, AGND Current ........................ 2S mA
Digital 1/0 Pin Voltages ............ - 0.3V to (V + + 0.3V)
PROG to DGND Voltage ............... V- to (V+ +0.3)

derate above 70·C @10 mWrC
Lead Temperature (soldering, 10 sec.) ............. 300·C

Nole 1: All voltages with respect to DGND, unless otherwise noted.
2: Assumes all leads soldered or welded to printed circuit board.
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

D.C. ELECTRICAL CHARACTERISTICS
v+

= +SV, v- = -SV, VREF = -10.0V, TA = +2S0C, fclk = SOO kHz unless otherwise noted.

Symbol

Test Conditions

Parameter

Min

Integral Linearity Error

Note 1

TC(ILE)

Temperature Coefficient of ILE

TA

RES(NMC)

Resolution with No Missing Codes

FSE

Full Scale Calibration Error
Zero Error

Max

Units

±.024

%FSR

12

Resolution
ILE

ZE

Typ

I
I

K

= Operating Range

I
I

Bits

J

1

J

11

K

12

Power Supply Rejection Ratio

VIN

Analog Input Range (VIN, VREF) 111

RIN

Input Resistance (VIN, VREF)

ISUPPLY

Supply Current 1+, 1-

VSUPPLY

Supply Voltage Range

..

~

VIL

Low State Input Voltage

VIH

High State Input Voltage

ILiH

Logic Input Current

0< VIN < V+

VOL

Low State Output Voltage

lOUT

= 1.6 mA
= 200 /LA

ppm/·C

±0.1

%FSR

±1

LSB

±1

LSB

0

10

V

4

9

kO

2
Functional Operation Only

%FSR

1.S

Bits

Not

PSRR

±.012

±4.5

4

mA

±6.0

V

O.B

V

10

/LA

0.4

V

2.4

VOH

High State Output Voltage

lOUT

lox

Three-State Output Current

0< VOUT < V+

CR

Conversion Rate

V
1

V

2.B
1

/LA

30

/Ls

Nole 1: Full Scale Range (FSR) is 10 V (reference adjusted).
2: Assume all leads soldered or welded to printed circuit board.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED.lN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE' All typical values have been characterized but are not tested.

3-59

•

...~ ICL7115

!:i 14-Bit High-Speed
S:!

CMOS ILP-Compatible
AID Converter
GENERAL DESCRIPTION

FEATURES

The ICL7115 is the first monolithic 14-bit resolution, fast
successive approximation AID converter. It uses thin film
resistors and CMOS circuitry combined with an on-chip
PROM calibration table to achieve 13-bit linearity without
laser trimming. Special design techniques used in the DAC
and comparator result in high speed operation, while the
fully static silicon-gate CMOS circuitry keeps the power dissipation very low.
Microprocessor bus interfacing is made easy by the use
of standard WRite and ReaD cycle timing and control signals, combined with Chip Select and Address pins. The digital output pins are by1e-organized and three-state gated for
bus interface to 8 and 16-bit systems.
The ICL7115 provides separate Analog and Digital
grounds. Analog ground, voltage reference and input voltage pins are separated into force and sense lines for increased system accuracy. Operating with ±5V supplies, the
ICL7115 accepts OV to + 5V input with a - 5V reference or
OV to - 5V input with a + 5V reference.

• 14-Bit Resolution (LSB=305!,-V)
• No Missing Codes
• Microprocessor Compatible Byte-Organized Buffered
Outputs
• Fast Conversion (40!,-s)
• Auto-Zeroed Comparator for Low Offset Voltage
• Low Linearity and Gain Tempco
(1.5ppmI'C, 5ppml'C)
• Low Power Consumption (60mW)
• No Gain or Offset Adjustment Necessary
• Provides 3% Useable Overrange
• FORCE/SENSE and Separate Digital and Analog
Ground Pins for Increased System Accuracy

ORDERING INFORMATION
Part
Number

Resolution
with No
Missing Codes

Temp.
Range

Package

ICL7115JCDL
ICL7115KCDL

12 Bits
13 Bits

O'Cto +70'C
O'Cto +70'C

40 Pin Ceramic
40 Pin Ceramic

ICL7115JIDL
ICL7115KIDL

12 Bits
13 Bits

- 25'C to + 85'C
- 25'C to + 85'C

40 Pin Ceramic
40 Pin Ceramic

ICL7115JMDL
ICL7115KMDL
ICL7115JMLL
ICL7115KMLL

12 Bits
13 Bits
12 Bits
13 Bits

- 55'C to
- 55'C to
- 55'C to
-55'C to

40 Pin Ceramic
40 Pin Ceramic
40 Pin LCC
40 Pin LCC

+
+
+
+

125'C
125'C
125'C
125'C

INTERSll'S SOLE AND EXCLUSIVE WARAANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHEA WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

301659-003

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical val/J8s have been characterized but are not tested.

3-60

ICL7115
ABSOLUTE MAXIMUM RATINGS

(Note 1)
Supply Voltage V+ to DGND ........... -O.3V to +6.5V
Supply Voltage V- to DGND ........... +O.3V to -6.5V
VREFs. VREFf, VINs, VINf to DGND ........ + 25V to - 25V
AGNDs, AGND, to DGND ................. + 1V to -1V
Current in FORCE and SENSE Lines .............. 25mA
Digital 1/0 Pin Voltages ............ - O.3V to V + + O.3V
PROG to DGND Voltage .............. V- to V+ +O.3V

Operating Temperature Range
ICL7115XCXX ......................... O'Cto +70'C
ICL7115XIXX ...................... - 25'C to + 85'C
ICL7115XMXX .................... -55'Cto + 125'C
Storage Temperature Range . . . . . . . . .. - 65'C to + 150'C
Power Dissipation ............................. 500mW
derate above 70'C @ 1OOmW I'C
Lead Temperature (Soldering, 1Osee) ............. 300'C

NOTE 1: All voltages with respect to DGND, unless otherwise noted.

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absOlute
maximum rating conditions for extended penOds may affect device reliability.

.s
z

~

5

l:e It! li
4

3

2

It ..
~$

1

r!r

~

j J

...

~

VREFf

40 39 38:f1 36

6

35

CAl

33

Wli

32

sc

31
30

OSC2
OSC1

12

29

TEST

13

28

PROG

14

27

10
11

ICL7115

15
16

17 18

19 20 21

26
22 23 24 25

es

v~

34

III

RO

An
BUS

(MSB) 0'3
012

V·

011

DIIR

0'0

c5 & rS rS Q

~

~ .0 .0

d.

~

&

0337-17

(Outline DWG LL)

0337-1

(Outline DWG DL)
Figure 1: Pin Configuration

lNTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

3-61

........1ft ICL7115
....

...

!:!
lIRE,.

~N.

sa

+--'Y\,.,..-OIlREFI

OSC1

0SC2

IIIN
AGNDt
AGND.

17
DGNDC>--+

17·BITSAR
CONTROL LOGIC

V-O--+

1~4~------------OWR

r---------------O EOC
r----'\......J\ OVR
Dt3(MSB)

L-:l~-r"T"-"""" Do (LSB)

CS Ail

BUS
0337-2

Figure 2: ICL7115 Functional Diagram

INTERSIL'$ SOLE AND EXCLUSiVE WARRANTY OBLIGATION WITH RESPECT TO THIS PAODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

3·62

ICL7115
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS V+ = +5.0V, V- = -5.0V, VREFs= -5.0V, TA= + 25°C, fCLK=500kHz,
SC= VIH unless otherwise noted.
Parameter

Symbol
Resolution

ILE
TC(ILE)

Integral Linearity Error
Temperature Coefficient of ILE

Test Conditions

14

SC=VIL

12

Note 1

Min Resolution with No Missing Codes
TA = Operating Range (Note 2)

FSE
TC(FSE)

Typ

J

±0.01B
±0.012
1

J

12

K

13

J

11

K

12
±0.1

K

±O.OB

T A = Operating Range

Zero Error

Notes 1,2

Temperature Coefficient of ZE

TA = Operating Range

PSRR

Power Supply Rejection Ratio

2

TA=25°C

±%

Input Resistance (VINs, VREFs)

Supply Current, I + , 1-

Functional Operation Only

VIL

Low State Input Voltage

Operating Temperature Range

VIH

High State Input Voltage

Operating Temperature Range

ILiH

Logic Input Current

OV+

VOL

Low State Output Voltage

IOUT=1.6mA
Operating Temperature Range

VOH

High State Output Voltage

IOUT= - 2OOfLA
Operating Temperature Range

lox

Three-State Output Current

OV+

CIN

Logic Input Capacitance

COUT

Logic Output Capacitance

2

±1

LSB

kO
ppmrC

4

mA

6
±4.5

±6.0

V

O.B

V
V

2.4
1

10
0.4

2.B

fLA
V
V

1
15

Three-State

ppmrC

9

T A = Operating Range
Supply Voltage Range

LSB

1

-300

TA=25°C

VSUPPLY

ppmrC

V

4

Note 3

5

%FSR

±1

+5

T A = Operating Range

Tc(RIN)
ISUPPLY

o to

(VINs, VREFs)

ppmrC

±2

T A = Operating Range
Analog Input Range

%FSR

Bits

(Adjustable to Zero)

ZE

RIN

1.5

J

Temperature Coefficient of FSE

Unit
Bits

Full Scale Calibration Error

TC(ZE)

VIN

Max

K
T A = Operating Range
TA=25°C
RES(NMC)

Min

SC=VIH

fLA
pF

15

NOTES: 1. Full-scale range (FSR) is 5V (reference adjusted).
2. Assume all leads soldered or welded to printed circuit board.
3. Assume all leads soldered or welded to printed circuit board.

INTERStL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: Alf typical values have been characterized but are not tested

3-63

......= ICL7115

IID~DII.

~

--r

~ ~~~~~________~VA~L~ID~-.____

1III=~1
Do-D..

IN71_
.

--------------------~---«

•~ ~~~~-----------~---------r---------------~

= DON'T CARE
0337-3

Figure 3: Read Cycle Timing

~

= DON'T CARE
0337-4

Figure 4: Write Cycle Timing

AC ELECTRICAL CHARACTERISTICS v+ = + 5.0V, v- = -5.0V, TA = + 25°C, fclk= 500kHz unless
otherwise noted. Data derived from extensive characterization testing. Parameters are not 100% production tested.
Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

READ CYCLE TIMING
RD Low, Ao Valid
CS Low, RD Low
CS Low, Ao Valid

tcd

Prop. Delay CS to Data

tad

Prop. Delay Ao to Data

trd

Prop. Delay RD to Data

toe

Prop. Delay Data to Three State

100

ted

Prop. Delay EOC High to Data

200

200
200
200

ns

WRITE CYCLE TIMING
twr

W'RLowTime

twe

Prop. Delay WR Low to EOC Low

tao

EOC High Time

teonv

100
Wait Mode
Free-Run Mode

Conversion Time

ns

1

2

0.5

1.5

'SC=VIH

20

'SC=VIL

18

1lfclk

INTeRSIL'S SCLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE:AH/yp/coI_"" .. _ _ bulaIOnJ)/1M/fd.

3-64

ICL7115
TABLE 1: PIN DESCRIPTIONS
PIN NAME

PIN

NAME

1

VREFf

FORCE line for reference input.

FUNCTION

30

OSC1

Oscillator inverter input

2

AGNDt FORCE input for analog ground

31

OSC2

Oscillator inverter output

FUNCTION

3

CS

Chip Select enables reading and writing
(active low)

32

"SC

Short cycle input (high = 14-bit,
low = 12-bit operation)

4

RD

ReaD (active low)

33

WR

5

Ao

Byte select (low = Do - 07,
high = De - 013, OVR)

WRite pulse input (low starts new
conversion)

34

CAZ

Auto-zero capacitor connection

6

BUS

35

V-

36

COMP

7

Bus select (low = outputs enabled by Ao,
high = all outputs enabled together)

DGND Digital GrouND return

Negative power supply input
Used in test, tie to V-

37

VINs

38

VREFs

SENSE line for reference input

39

AGNDs

SENSE line for analog ground

40

VINf

FORCE line for input voltage

SENSE line for input voltage

8

013

Bit 13 (most significant)

9

012

Bit 12

10

011

Bit11

11

010

Bit 10

12

09

Bit 9

Output

13

De

Bit 8

Data

14

07

Bit 7

Bits

0

0

x

x

x

Initiates a Conversion

15

06

Bit 6

(High = True)

1

x

x

x

x

Disables all Chip Commands

16

05

Bit 5

0

x

0

0

0

Low Byte is Enabled

17

04

Bit 4

0

x

0

1

0

High Byte is Enabled

18

03

Bit 3

0

x

0

x

1

Low and High Bytes Enabled Together

x

x

1

x

x

Disables Outputs (High-Impedance)

19

High Byte

02

Bit 2

20

01

Bit 1

21

Do

Bit 0 (least significant)

22

B15

23

B16

24

B17

25

EOC

TABLE 2: 1/0 CONTROL
CS WR RD Ao BUS

Low Byte

FUNCTION

TABLE 3: TRANSFER FUNCTION
INPUT VOLTAGE
VREF= -5.0V

Used for programming only (leave open)

End Of Conversion flag (low = busy,
high = conversion complete)

26

OVR

OVerRange flag (valid at end of conversion
when output code exceeds full-scale, threestate output enabled with high byte)

27

V+

Positive power supply input

28

PROG Used for programming only. Tie to V+ for
normal operation

29

TEST

EXPECTED OUTPUT CODE
OVR MSB

LSB

0
+0.0003

0
0

0
0

000000000000
000000000000

0
1

+0.150

0

0

000011110101

1
1
0

+2.4997
+2.500

0
0

0
1

111111111111
000000000000

+4.9994
+4.9997
+5.000
+5.0003

0
0
1
1

1
1
0
0

111111111111
111111111111
000000000000
000000000000

0
1
0
1

+5.150

1

0

000011110101

1

Used for programming only. Tie to V+ for
normal operation

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATEO IN THE WARRANTY ARTIClE OF THE ODNDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPUED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typicsI values hBve besn charBcl6lized but MS not tHffId.

3-65

......... ICL7115
~

!::!

nates the effect of small voltage drops which can appear
between the input pin of the IC package and the actual resistor on the chip. If the small gauge wire and the bonds
that connect the chip to its package have more than 300mO
of total series resistance, the result can be a voltage error
equivalent to 1LSB. If no op-amps are used for VIN and
VREF, connections should be made directly to the SENSE
lines. The external op-amps also serve to transform the relatively low impedance at the VIN and VREF pins into a high
impedance. The input offset voltages of these amplifiers
should be kept low in order to maintain the overall A/D converter system accuracy.
When using A/D converters with more than 12 bits of
resolution, special attention must be paid to grounding and
the elimination of potential ground loops. A ground loop can
be formed by allowing the return current from the ICL7115's
DAC to flow through traces that are common to other analog circuitry. If care is not taken, this current can generate
small unwanted voltages that add to or detract from the
reference or input voltages of the AID converter.
Ground loops can be eliminated by the use of the analog
ground FORCE and SENSE lines provided on the ICL?11.5
as shown in Figures 5 and 6. In Figure 5 the FORCE line IS
the only point that is connected to system analog ground. In
Figure 6, the op-amp A3 forces the voltage at AGND to be
equal to analog system ground. The addition of this op-amp
overcomes the main deficiency of the arrangement in Figure 5: the VIN and VREF sources are not referenced to true
analog system ground.
The clamp diodes in Figure 6 are required because spurious op-amp output on AGNDf during power-on can exceed
the absolute max rating of ± 1.0V between AGDf and
DGND. The two inverse-parallel diodes clamp the voltage
between AGNDs and DGND to ±0.7V.

DETAILED DESCRIPTION

The ICL7115 is basically a successive approximation A/D
converter with an internal structure much more complex
than a standard SAR-type converter. Figure 2 shows the
functional diagram of the ICL7115 14-bit AID converter.
The additional circuitry incorporated into the ICL7115 is
used to perform error correction and to maintain the operating speed in the 40fA-s range.
The internal 17-bit DAC of the ICL7115 is designed
around a radix of 1.85 rather than the traditional 2.00. This
radix gives each bit of the DAC a weight of approximately
54% of the previous bit. The result is a useable range that
extends to 3% beyond the full-scale input of the AID. The
actual value of each bit is measured and stored in the onchip PROM. The absolute value of each bit weight then becomes relatively unimportant because of the error correction action of the ICL7115.
The output of the high-speed auto-zeroed comparator is
fed to the data input of a 17-bit successive approximation
register (SAR). This register is uniquely designed for the
ICL7115 in that it tests bit pairs instead of individual bits in
the manner of a standard SAR. At the beginning of the conversion cycle, the SAR turns on the MSB (B16) and the
MSB-4 bit (B12)' The sequence continues for each bit pair,
Bx and BX-4' until only the four LSBs remain. The sequence
concludes by testing the four LSBs individually.
The SAR output is fed to the DAC register and to the
preprogrammed 17-word by 17-bit PROM where it acts as
PROM address. PROM data is fed to a 17-bit full-adder/accumulator where the decoded results from each successive
phase of the conversion are summed with the previous results. After 20 clock cycles, the accumulator contains the
final binary data which is latched and sent to the three-state
output buffers. The accuracy of the AID converter depends
primarily upon the accuracy of the data that has been programmed into the PROM during the final test portion of the
manufacturing process.
The error correcting algorithm built into the ICL7115 reduces the initial accuracy requirements of the DAC. The
overlap in the testing of bit pairs reduces the accuracy requirements on the comparator which has been optimized for
speed. Since the comparator is auto-zeroed, no external adjustment is required to get ZERO code for ZERO input voltage.
Twenty clock cycles are required for the complete 14-bit
conversion. The auto-zero circuitry associated with the
comparator is employed during the last three clock cycles
of the conversion to cancel the effect of offset voltage. Also
during this time, the SAR and accumulator are reset in preparation for the start of the next conversion. When the Short
Cycle (SC) input is low, 18 clock cycles are required to complete a 12-bit conversion.
The overflow output of the 17-bit full-adder is also the
OVerRange (OVR) output of the ICL7115. Unlike standard
SAR-type AID converters, the ICL7115 has the capability of
providing valid useable data for inputs that exceed the fullscale range by as much as 3%.

INPUT WARNING
As with any CMOS integrated circuit, no input voltages
should be applied to the ICL7115 until the ± 5V power supplies have stabilized.

INTERFACING TO DIGITAL SYSTEMS
The ICL7115 provides three-state data output buffers,
CS, RD, WR, and bus select inputs (Ao and BUS) for interfacing to a wide variety of microcomputers and digital systems. The I/O Control Truth Table shows the functions of
the digital control lines. The BUS select and Ao lines are
provided to enable the output data onto either 8-bIt or 16-blt
data buses. A conversion is initiated by a WR pulse (pin 33)
when CS (pin 3) is low. Data is enabled on the bus when the
chip is selected and RD (pin 4) is low.
Figure 7 illustrates a typical interface to an 8-bit microcomputer. The "Start and Wait" operation requires the fewest external components and is initiated by a low level on
the WR input to the ICL7115 after the I/O or memorymapped address decoder has brought the CS input low. After executing a delay or utility routine for a period of time
greater than the conversion time of the ICL7115, the processor issues two consecutive bus addresses to read output
data into two bytes of memory. A low level on Ao enables
the LSBs and a high level enables the MSBs.

OPTIMIZING SYSTEM PERFORMANCE
The FORCE and SENSE inputs for VIN and VREF are also
shown driven by external op-amps. This technique elimi-

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: Ali typical values have been characterized but are not tested

3-66

ICL7115

' - - - - - - - I VINs

VREFf
ICL7115

.....- - - - - - 1 VREF•
'-------~AGNOs

...------IAGNDf
r---iOGNO
0337-5

Figure 5: VIN and VREF Input Buffers

> - - - - I VINf

' - - - - - - - - f VIN.

>----1 VREff
ICL7115

' - - - - - - - - 1 VREF•
r - - - - - - - I AGNDs

> .....~~-I AGNOf
L -.....--10GND

0337-6

Figure 6: Using a Forced Ground

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characteriz9d but are not tested

3-67

•

......
...

10

ICL7115

...

S:!
ADDRESS IUS

\

.... ....

Ao

I

Ao

""III

~

ADDRESS
DECODE

I

,

Ao-AN

~

RD

lim

WR

WR

.,

ICL7I15

IUS

n

OVR
Do-D7

,

~

Do-Of
~

DrD13

~""'Ii

"""
""'Ii!

"..

,

I

DATA BUS

0337-7

START
CONVERSION

WAlT

READ

READ

LOW BYTE

HIGH BYTE
0337-8

Figure 7: "Start and Walt" Operation

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOrc: AU typical values have beBn charsctsrized but BrfI not testsd.

3-68

IID~On.

ICL7115

a conversion time of 40/-Ls. Output data is controlled by the
BUS and Ao inputs. Here they are set for B-bit bus operation
with BUS grounded and Ao under the control of the address
decode section of the external system.
Because the ICL7115's internal accumulator generates
accurate output data for input signals as much as 3% greater than full-scale, and because the converter's OVR output
flags overrange inputs, a simple microprocessor routine can
be employed to precisely measure and correct for system
gain and offset errors. Figure 12 shows a typical data acquisition system that uses a 5.0V reference, input signal multiplexer, and input Signal Track/Hold amplifier. Two of the
multiplexer's input channels are dedicated to sampling the
system analog ground and reference voltage. Here, as in
Figure 11, bipolar operation is accommodated by an offset
resistor between the reference voltage and the summing
junction of A1. A flip-flop in IC3 sets IC2'S Track/Hold input
after the microprocessor has initiated a WR command, and
resets when EOC goes high at the end of the conversion.
The first step in the system calibration routine is to select
the multiplexer channel that is connected to system analog
ground and initiate a conversion cycle for the ICL7115. The
results represent the system offset error which comes from
the sum of the offsets from IC1, IC2, and A1. Next the channel connected to the reference voltage is selected and
measured. These results, minus the system offset error,
represent the system full-scale range. A gain error correction factor can be derived from this data. Since the ICL7115
provides valid data for inputs that exceed full-scale by as
much as 3%, the OVR output can be thought of as a valid
15th data bit. Whenever the OVR bit is high, however, the
total 14-bit result should be checked to insure that it falls
within 100% and 103% of full-scale. Data beyond 103% of
full-scale should be discarded.
The ICL7115 provides an internal inverter which is
brought out to pins OSC1 and OSC2, for crystal or ceramic
resonator oscillator operation. The clock frequency is calculated from:

By adding a three-state buffer and two control gates, the
End-of-Conversion (EOC) output can be used to control a
"Start and Poll" interface (Figure B). In this mode, the Ao
and CS lines connect the EOC output to the data bus al~
with the most significant byte of data. After pulsing the WR
line to initiate a conversion, the microprocessor continually
reads the most significant byte until it detects a high level
on the EOC bit. The "Start and Poll" interface increases
data throughput compared with the "Start and Wait" method by eliminating delays between the conversion termination and the microprocessor read operation.
Other interface configurations can be used to increase
data throughput without monopolizing the microprocessor
during waiting or polling operations by using the EOC line as
an interrupt generator as shown in Figure 9. After the conversion cycle is initiated, the microprocessor can continue
to execute routines that are independent of the AID converter until the converter's output register actually holds valid data. For fastest data throughput, the ICL7115 can be
connected directly to the data bus but controlled by way of
a Direct Memory Access (DMA) controller as shown in Figure 9.

APPLICATIONS
Figure 11 shows a typical application of the ICL7115 14bit AID converter. A bipolar input voltage range of + 5V to
- 5V is the result of using the current through R2 to force a
% scale offset on the input amplifier (A2). The output of A2
swings from OV to -5V. The overall gain of the AID is varied by adjusting the 100kn trim resistor, Rs. Since the
ICL7115 is automatically zeroed every conversion, the system gain and offset stability will be superb as long as a
reference with a tempco of 1ppml'C and stable external
resistors are used.
In Figure 11, note that the 0.22/-LF auto-zero capacitor is
connected directly between the CAZ. pin and analog ground
SENSE. A:l forces the analog ground of the ICL7115 to be
the zero reference for the input Signal. Its offset voltage is
not important in this example because the voltage to be
digitized is referred to the analog ground SENSE line rather
than system analog ground. It is important to note that Since
the 7115's DAC current flows in A1, A2 and A3 these amplifiers should be wideband (GBW> 20M Hz) types to minimize
errors.
The clock for the ICL7115 is taken from whatever system
clock is available and divided down to the 500kHz level for

.
fCLK = -20- f or 14-b·It operation
!cony

and
.
fCLK = -1B- f or 12-b·It operation
tconv

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valuss have been characterized but are not tested.

3-69

il
......
...

CII

•

......
......
10

ICL7115

S!

(A)

Wfi~------;-t----iWR

CS I+-------H
RD~------~+_--_iRD

ICL7115

~p

EOC
BUS

DATA BUS
0337-9

(8)
END OF

READ

POLL----+--

HIGHIYTE

READ

LOW BYTE
0337-10

Figure 8: "Start and Poll" Operation

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIeD OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR

use.

NOTE: All typical values hsve b6en characterized but are not tested.

3·70

.O~OIL

ICL7115

c;
I'"

.......
ell

Cs

R5

RD
WR

WR

ICL7115

j.£p

INT

•

0337-11

READ
LOWIYTE

CONVERSION

READ
HIGH BYTE
0337-12

Figure 9: Using EOC as an Interrupt

lNTERSIL'S SOLE AND EXCLUSIVE WAARANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARAANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

3-71

..... ICL7115
1ft

g

BUS

AO

WR

EOCI-------.IORO"

DMA

ICL711S

CONTROLLER

IUS

DATA IUS
0337-13

EOC

Ao
READ
LOW BYTE
ENDOF
CONVERSION

READ
HIGH BYTE

START
CONVERSION
0337-14

Figure 10: Data to Memory via DMA Controller

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have be6n characterized but are not test8d.

3-72

ICL7115
+5V

500 kHz
SYSTEM
CLOCK

OSC
5V
REFERENCE

EOC

.,,[

ICL7115
INPUT VOLTAGE
+5V TO -5V

OUT

WR

21
33

ifIj

CS
I{" DGND BUS

36

-5V

•

Ao

7

DIGITAL
GROUND

0337-15

Figure 11: Typical Application with Bipolar Input Range, Forced Ground, and 5 Volt Ultra-Stable Reference

Vee

r---t-----t-----1AD

t------t----i-t-~WR

ANALOGI
INPUTS

y.
74125

0337-16

Figure 12: Multi-Channel Data Acquisition System with Zero and Reference Lines Brought to Multiplexer for
System Gain and Offset Error Correction

tNTERStL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicB.1 values have bBBn characterized but arB not test6(/.

3-73

D~DIL

=:... ICL7135

C)_~

4%-Digit BCD Output
AID Converter

GENERAL DESCRIPTION

FEATURES

The Intersi! ICL7135 precision AID converter, with its
multiplexed BCD output and digit drivers, combines dual·
slope conversion reliability with ± 1 in 20,000 count accura·
cy and is ideally suited for the visual display DVM/DPM
market. The 2.0000V full scale capability, auto·zero and
auto·polarity are combined with true ratio metric operation,
al most ideal differential linearity and true differential input.
All necessary active devices are contained on a single
CMOS I.C., with the exception of display drivers, reference,
and a clock.
The intersil ICL7135 brings together an unprecedented
combination of high accuracy, versatility, and true economy.
It features auto·zero to less than 10,..V, zero drift of less
than 1,..VrC, input bias current of 10 pA max., and rollover
error of less than one count. The versatility of multiplexed
BCD outputs is increased by the addition of several pins
which allow it to operate in more sophisticated systems.
These include STROBE, OVERRANGE, UNDER· RANGE,
RUN/HOLD and BUSY lines, making it possible to interface
the circuit to a microprocessor or UART.

• Accuracy Guaranteed to ± 1 Count Over Entire
± 20,000 Counts (2.0000 Volts Full Scale)
• Guaranteed Zero Reading for 0 Volts Input
• 1pA Typical Input Current
• True Differential Input
• True Polarity at Zero Count for Precise Null
Detection
• Single Reference Voltage Required
• Over-Range and Under-Range Signals Available for
Auto-Range Capability
• All Outputs TTL Compatible
• Blinking Outputs Gives Visual Indication of Overrange
• Six Auxiliary Inputs/Outputs Are Available for
Interfacing to UARTs, Microprocessors or Other
Circuitry
• Multiplexed BCD Outputs

ORDERING INFORMATION
Part Number

Temp. Range

Package

ICL7135CJI

O·Cto +70·C

28·Pin CERDIP

ICL7135CPI

O·Cto +70·C

2B·Pin Plastic DIP

Evaluation Kit
ICL7135EV/KIT
(PC Board, active, passive components)

GND
ANALOGO~~~~~~~~

ANODE
DRIVER
TRANSISTORS
SIGNAL

INPUT

SEVEN
BEG.

DECODE

0342-1

Figure 1: ICL7135 Connection Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTlCLE OF THE OONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typical VSIU8S hsVB been ohatscterized but srtI not fBSt«J.

3·74

ICL7135
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Note 2)
Ceramic Package .......................... 1000mW
Plastic Package ............................. 800mW
Operating Temperature ................... O'C to + 70'C
Storage Temperature ................ - 65'C to + 150'C
Lead Temperature (Soldering, 10sec) ............. 300'C

SupplyVoltageV+ .............................. +6V
v- .............................. -9V
Analog Input Voltage (either input) (Note 1) ..... V+ to VReference Input Voltage (either input) ......... V+ to VClock Input ................................ Gnd to V+
Nole I:

Input voltages may exceed the supply voltages provided the input current is limijed to

+ 100"A.

Note 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress rafings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum. rating conditions for extended periods may affect device reliability.

Y-

UNDERRANGE
OYE_GE

REFERENCE

STROBE

ANALOG COMMON
INTOUT
AZIN

•

Rlit
24 DIGITAL GND
POL

BUFF OUT

iiEF."cAP7-'
REF. CAP. +

INLO

INKI
y+
(MSD)DS
(LSI)S1

B2

-------

0342-2

Figure 2: Pin Configuration
Outline dwgs JI, PI)

ELECTRICAL CHARACTERISTICS

(Note 1)
(V+ = +5V, V- = -5V, TA=25'C, Clock Frequency Set for 3 Reading/Sec)
Symbol

Test Conditions

Min

Typ

Max

Unit

Zero Input Reading

VIN=O.OV
Full Scale = 2.000V

-0.0000

±O.OOOO

+0.0000

Digital
Reading

Ratiometric Reading (2)

VIN '" VREF
Full Scale=2.000V

+0.9998

+0.9999

+ 1.0000

Digital
Reading

-2V"VIN,,+2V

0.5

1

+ 2V

.01

Characteristics

ANALOG (Note 1) (Note 2)

Linearity over ± Full Scale
(error of reading from
best straight line)
Differential Linearity
(difference between worse
case step of adjacent counts
and ideal step)
Rollover error (Difference in
reading for equal positive &
negative voltage near full scale)

-2V"VIN"

-VIN'" +VIN :::: 2V

0.5

Digital
Count
Error
LSB

1

Digital
Count
Error

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not testsd.

3-75

.....=: ICL7135
~

S:!

ELECTRICAL CHARACTERISTICS

(Note 1)
(V+ = +5V, V- = -5V, TA = 25'C, Clock Frequency Settor 3 Reading/Sec) (Continued)
Symbol

Characteristics

en

Noise (P-P value not
exceeded 95% of time)

IILK

Leakage Current at Input
Zero Reading Drift

TC

Scale Factor Temperature
Coefficient (3)

Test Conditions

Min

Typ

Max

Unit

VIN=OV
Full scale = 2.000V

15

VIN=OV

1

10

pA

VIN=OV
0':0: TA:O: 70'C

0.5

2

p,VI'C

2

5

ppml'C

2.2
1.6
0.02
0.1

0.8
0.1
10

VIN= +2V
O:O:TA:O:70'C
(ext. ref. 0 ppml'C)

p,V

DIGITAL
INPUTS
VINH
VINL
IINL
IINH

2.8
Clock in, Run/Hold, See Figure 4

VIN=O
VIN= +5V

V
mA
p,A

OUTPUTS
VOL
VOH
VOH

All Outputs
Bl, B2, B4, Ba
Dl, D2, D3, D4, D5
BUSY, STROBE,
OVER-RANGE, UNDER-RANGE
POLARITY

IOL =1.6mA
IOH= -lmA

2.4

0.25
4.2

IOH= -10p,A

4.9

4.99

+4

+5

0.40

V
V
V

SUPPLY
V+

+ 5V Supply Range

V-

- 5V Supply Range

1+

+ 5V Supply Current

1CPD

- 5V Supply Current
Power Dissipation Capacitance

-3

+6

V

-5

-8

V

fc=O

1.1

3.0

mA

fc=O

0.8

3.0

vs. Clock Freq

40

pF

CLOCK
Clock Freq. (Note 4)

DC

2000

1200

kHz

NOTES: 1. Tested in 4-% digit (20,000 count) circuit shown in Figure 3, clock frequency 120kHz.
2. Tested with a low dielectric absorption integrating capacitor and RINT = O. See Component Selection Section.
3. The temperature range can be extended to + 700 e and beyond as long as the auto~zero and reference capacitors are increased to absorb the higher
leakage of the ICL7135.
4. This specification relates to the clock frequency range over which the ICL7135 will correctly perform its various functions. See "Max
Clock Frequency" section for limitations on the clock frequency range in a system.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE All typical values have been characterized but are not tested

3-76

ICL7135
y+

CLOCK
IN
120kHz

' - - - 6 - - - 0 I G GND

0342-4

Figure 4: 7135 Digital Logic Input
0342-3

Figure 3: 7135 Test Circuit

•

Coe'
CREF+

r--I

REF HI
8

-------2

AUTO

eRe.

BUFFER
-----7

~£.:...--

I

I
I
I
I
I
I
I

INPUT
HIGH

I

INHI ~~~D(~~-+----~---4--------~--~{x1------------4--~----C~OMPARATOR

Z-I
INPUT
LOW

INLO $-~~>C~--~---------------------------------------J
L _________________

~~---------------------------0342-5

Figure 5: Analog Section of ICL7135

INTERSIL'9 SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

3-77

=: ICL7135

...
......

!:!

DETAILED DESCRIPTION
Analog Section

DE·INTEGRATE PHASE
The Third phase is de-integrate, or reference integrate.
Input LOW is internally connected to analog COMMON and
input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the
capacitor will be connected with the correct polarity to
cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the
input signal. Specifically the digital reading displayed is

Figure 5 shows the Block Diagram of the Analog Section
for the ICL7135. Each measurement cycle is divided into
four phases. They are (1) auto-zero (A-Z), (2) signal-integrate (I NT), (3) deintegrate (DE) and (4) zero-integrator (ZI).

AUTO·ZERO PHASE
During auto-zero three things happen. First, input high
and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Third, a feedback loop is
closed around the system to charge the auto-zero capacitor
CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the
noise of the system. In any case, the offset referred to the
input is less than 1O)J-V.

10,000

(V~~F)'

ZERO INTEGRATOR PHASE
The final phase is zero integrator. First, input low is shorted to analog COMMON. Second, a feedback loop is closed
around the system to input high to cause the integrator output to return to zero. Under normal condition, this phase
lasts from 100 to 200 clock pulses, but after an overrange
conversion, it is extended to 6200 clock pulses.

SIGNAL INTEGRATE PHASE

Differential Input

During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and
low are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a
wide common mode range; within one volt of either supply.
If, on the other hand, the input signal has no return with
respect to the converter power supply, IN LO can be tied to
analog COMMON to establish the correct common-mode
voltage. At the end of this phase, the polarity of the integrated signal is latched into the polarity F/F.

The input can accept differential voltages anywhere within the common mode range of the input amplifier; or specifically from 0.5 volts below the positive supply to 1.0 volt
above the negative supply. In this range the system has a
CMRR of 86 dB typical. However, since the integrator also
swings with the common mode voltage, care must be exercised to assure the integrator output does not saturate. A
worst case condition would be a large positive commonmode voltage with a near full-scale negative differential input voltage. The negative input signal drives the integrator
positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the
recommended 4V full scale swing with some loss of accuracy. The integrator output can swing within 0.3 volts of either
supply without loss of linearity.

I

y+

y+

I

6.8 VOLT
ZENER

REFHIf-

~~

G.akO

y+

-

7135

COMMON 1--'-

j Iz

20

REF HI

~ ~~. ICLB069

1.2V
REFERENCE

7135

COMMON~--~---.

,!.

0342-6

0342-7

(a)

(b)

Figure 6: Using an External Reference

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not testsd.

3-78

.D~DIl.

ICL7135

auto-zero when not BUSY, so it may also be considered a
(ZI + AZ) signal. A very simple means for transmitting the
data down a single wire pair from a remote location would
be to AND BUSY with clock and subtract 10,001 counts
from the number of pulses received - as mentioned previously there is one "NO-count" pulse in each reference integrate cycle.

Analog Common
Analog COMMON is used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system
and is taken care of by the excellent CMRR of the converter. However, in most applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
pOint, thus removing the common mode voltage from the
converter. The reference voltage is referenced to analog
COMMON.

Reference
The reference input must be generated as a positive voltage with respect to COMMON, as shown in Figure 6.

DETAILED DESCRIPTION
Digital Section
Figure 7 shows the Digital Section of the 7135. The 7135
includes several pins which allow it to operate conveniently
in more sophisticated systems. These include:
Run/HOLD (Pin 25). When high (or open) the AID will freerun with equally spaced measurement cycles every 40,002
clock pulses. It taken low, the converter will continue the full
measurement cycle that it is doing and then hold this reading as long as RIA is held low. A short positive pulse (greater than 300ns) will now initiate a new measurement cycle,
beginning with between 1 and 10,001 counts of auto zero. If
the pulse occurs before the full measurement cycle (40,002
counts) is completed, it will not be recognized and the converter will simply complete the measurement it is doing. An
external indication that a full measurement cycle has been
completed is that the first strobe pulse (see below) will occur 101 counts after the end of this cycle. Thus, if Runl
HOLD is low and has been low for at least 101 counts, the
converter is holding and ready to start a new measurement
when pulsed high.
STROBE (Pin 26). This is a negative going output pulse that
aids in transferring the BCD data to external latches,
UARTs or microprocessors. There are 5 negative going
STROBE pulses that occur in the center of each of the digit
drive pulses and occur once and only once for each mea·
surement cycle starting 101 pulses after the end of the full
measurement cycle. Digit 5 (MSD) goes high at the end of
the measurement cycle and stays on for 201 counts. In the
center of this digit pulse (to avoid race conditions between
changing BCD and digit drives) the first STROBE pulse
goes negative for % clock pulse width. Similarly, after digit
5, digit 4 greS high (for 200 clock pulses) and 100 pulses
later the S ROBE goes negative for the second time. This
continues through digit 1 (LSD) when the fifth and last
STROBE pulse is sent. The digit drive will continue to scan
(unless the previous signal was overrange) but no additional
STROBE pulses will be sent until a new measurement is
available.
BUSY (Pin 21). BUSY goes high at the beginning of signal
integrate and stays high until the first clock pulse after zerocrossing (or after end of measurement in the case of an
overrange). The internal latches are enabled (i.e., loaded)
during the first clock pulse after busy and are latched at the
end of this clock pulse. The circuit automatically reverts to

0342-8

Figure 7: Digital Section of the 7135
OVER-RANGE (Pin 27). This pin goes positive when the
input signal exceeds the range (20,000) of the converter.
The output FIF is set at the end of BUSY and is reset to
zero at the beginning of Reference integrate in the next
measurement cycle.
UNDER-RANGE (Pin 28). This pin goes positive when the
reading is 9% of range or less. The output F IF is set at the
end of BUSY (if the new reading is 1800 or less) and is
reset at the beginning of Signal integrate of the next reading.
POLARITY (Pin 23). This pin is positive for a positive input
signal. It is valid even for a zero reading. In other words,
+ 0000 means the signal is positive but less than the least
significant bit. The converter can be used as a null detector
by forCing equal frequency of (+) and (-) readings. The
null at this point should be less than 0.1 LSB. This output
becomes valid at the beginning of reference integrate and
remains correct until it is re·validated for the next measurement.
Digit Drives (Pins 12, 17, 18, 19 and 20). Each digit drive is
a positive going signal that lasts for 200 clock pulses. The
scan sequence is Ds (MSD), D4, Ds, D2 and D1 (LSD). All
five digits are scanned and this scan is continuous unless
an over-range occurs. Then all digit drives are blanked from
the end of the strobe sequence until the beginning of Reference Integrate when D5 will start the scan again. This can
give a blinking display as a visual indication of over-range.
BCD (Pins 13, 14, 15 and 16). The Binary coded Decimal
bits B8, B4, B2 and B1 are positive logic Signals that go on
simultaneously with the digit driver signal.

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANlY ARTICLE OF THE OONDITION OF SALE.
THE WARRANlY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILIlY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typicsl va/uss have besn chsract8rfz6d but are not testsd.

3-79

P

.....

W
CII

: ICL7135

......

2 COMPONENT VALUE SELECTION
For optimum performance of the analog section, care
must be taken in the selection of values for the integrator
capacitor and resistor, auto-zero capacitor, reference voltage, and conversion rate. These values must be chosen to
suit the particular application.

INTEGRATOR

OUTP\IT

WT~-I SImf'L~
10,GOOl

~

10JAY,

COUNTS COU

Integrating Resistor

AEFEAENCU
INTEGRATE

COU=~AX.

FULL MEASUAEMENT CYCLE

OO,Q02COUNTS

The integrating resistor is determined by the full scale input voltage and the output current of the buffer used to
charge the integrator capacitor. Both the buffer amplifier
and the integrator have a class A output stage with 100,..A
of quiescent current. They can supply 20,..A of drive current
with negligible non-linearity. Values of 5 to 40,..A give good
results, with a nominal of 20,..A, and the exact value of integrating resistor may be chosen by
R
_ full scale voltage
INT20,..A

8USY--.J

WH~N~~~:~iIIII~~~~~
I EXPA:~~g:CALE

FOAo~~~~12~~~D'
~D.

~D3

Integrating Capacitor

---IL-.l1...-.. D,
-J"l...-Il-D,

The product of integrating resistor and capacitor should
be selected to give the maximum voltage swing which ensures that the tolerance built-up will not saturate the integrator swing (approx. 0.3 volt from either supply). For ± 5 volt
supplies and analog COMMON tied to supply ground, a
± 3.5 to ± 4 volt full scale integrator swing is fine, and
0.47,..F is nominal. In general, the value of CINT is given by

fcb~~sI

*FIRST Os OF AZ AND
REF .NT ONE COUNT LONGER

mmRiilli

r.-

AUTO ZERO

DIGIT SCAN· 0
FOR OYEA.AANGE

SIGNAL INTEGRATE

n=-,---------1.
J1:0.~

C =( [1 0,000 X clock period] XIINT )
INT integrator output voltage swing
(10,000) (clock period) (20,..A)
integrator output voltage swing
A very important characteristic of the integrating capacitor is that it has low dielectric absorption to prevent roll-over
or ratio metric errors. A good test for dielectric absorption is
to use the capacitor with the input tied to the reference.
This ratiometric condition should read half scale 0.9999,
and any deviation is probably due to dielectric absorption.
Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors
may also be used in less critical applications.

___~.~_~~

0342-9

Figure 8: Timing Diagram for Outputs

Auto-Zero and Reference Capacitor
The size of the auto-zero capacitor has some influence
on the noise of the system, a large capacitor giving less
noise. The reference capacitor should be large enough
such that stray capacitance to ground from its nodes is negligible.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIeD WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested,

3-80

IID~Dn.

ICL7135

To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz,
40kHz, 33%kHz, etc. should be selected. For 50Hz rejection, oscillator frequencies of 250kHz. 166%kHz, 125kHz.
100kHz, etc. would be suitable. Note that 100kHz (2.5 readings/second) will reject both 50 and 60Hz.
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators are
shown in the Applications section. The multiplexed output
means that if the display takes significant current from the
logic supply, the clock should have good PSRR.

The dielectric absorption of the reference cap and autozero cap are only important at power-on or when the circuit
is recovering from an overload. Thus, smaller or cheaper
caps can be used here if accurate readings are not required
for the first few seconds of recovery.

Reference Voltage
The analog input required to generate a full-scale output
is VIN=2 VREF·
The stability of the reference voltage is a major factor in
the overall absolute accuracy of the converter. For this reason, it is recommended that a high quality reference be
used where high-accuracy absolute measurements are being made.

p

....
Cot

CII

Zero-Crossing Flip-Flop
The flip-flop interrogates the data once every clock pulse
aiter the transients of the previous clock pulse and halfclock pulse have died down. False zero-crossings caused
by clock pulses are not recognized. Of course, the flip-flop
delays the true zero-crossing by up to one count in every
instance, and if a correction were not made, the display
would always be one count too high. Therefore, the counter
is disabled for one clOCk pulse at the beginning of phase 3.
This one-count delay compensates for the delay of the
zero-crOSSing flip-flop, and allows the correct number to be
latched into the display. Similarly, a one-count delay at the
beginning of phase 1 gives an overload display of 0000 instead of 0001. No delay occurs during phase 2, so that true
ratiometric readings result.

Rollover Resistor and Diode
A small rollover error occurs in the 7135, but this can be
easily corrected by adding a diode and resistor in series
between the INTegrator OUTput and analog COMMON or
ground. The value shown in the schematics is optimum for
the recommended conditions, but if integrator swing or
clock frequency is modified, adjustment may be needed.
The diode can be any silicon diode, such as 1N914. These
components can be eliminated if rollover error is not important, and may be altered in value to correct other (small)
sources of rollover as needed.

Max Clock Frequency
The maximum conversion rate of most dual-slope AID
converters is limited by the frequency response of the comparator. The comparator in this circuit follows the integrator
ramp with a 3,..s delay, and at a clock frequency of 160kHz
(6,..s period) half of the first reference integrate clock period
is lost in delay. This means that the meter reading will
change from 0 to 1 with a 50,..V input, 1 to 2 with 150,..V, 2
to 3 at 250,..V, etc. This transition at mid-point is considered
desirable by most users; however, if the clock frequency is
increased appreciably above 160kHz, the instrument will
flash "1" on noise peaks even when the input is shorted.
For many-dedicated applications where the input signal is
always of one polarity, the delay of the comparator need not
be a limitation. Since the non-linearity and noise do not increase substantially with frequency, clock rates of up to
- 1MHz may be used. For a fixed clock frequency, the extra
count or counts caused by comparator delay will be constant and can be subtracted out digitally.
The clock frequency may be extended above 160kHz
without this error, however, by using a low value resistor in
series with the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase.
By careful selection of the ratio between this resistor and
the integrating resistor (a few tens of ohms in the recommended circuit), the comparator delay can be compensated
and the maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second order breaks will cause significant nonlinearities in the
first few counts of the instrument - see Application Note
A017.
The minimum clock frequency is established by leakage
on the auto-zero and reference caps. With most devices,
measurement cycles as long as 10 seconds give no measurable leakage error.

EVALUATING THE ERROR SOURCES
Errors from the "ideal" cycle are caused by:
1.
Capacitor droop due to leakage.
2.
Capacitor voltage change due to charge "suck-out"
(the reverse of charge injection) when the switches
turn off.
3.
Non-linearity of buffer and integrator.
4.
High-frequency limitations of buffer, integrator and
comparator.
5.
Integrating capacitor non-linearity (dielectric absorption.)
6.
Charge lost by CREF in charging Cstray.
7.
Charge lost by CAZ and CINT to charge Cstray.
Each of these errors is analyzed for its error contribution
to the converter in application notes listed on the back
page, specifically A017 and A032.

NOISE
The peak-to-peak noise around zero is approximately
15,..V (pk-to-pk value not exceeded 95% of the time). Near
full scale, this value increases to approximately 30,..V. Much
of the noise originates in the auto-zero loop, and is proportional to the ratio of the input signal to the reference.

ANALOG AND DIGITAL GROUNDS
Extreme care must be taken to avoid ground loops in the
layout of ICL7135 circuits, especially in high-sensitivity circuits. It is most important that return currents from digital
loads are not fed into the analog ground line.

INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are not test6d.

3-81

•

.

=: ICL7135

......

2

A suitable circuit for driving a plasma-type display is
shown in Figure 10. The high voltage anode driver buffer is
made by Dionics. The 3 AND gates and caps driving 'BI' are
needed for interdigit blanking of multiple-digit display elements, and can be omitted if not needed. The 2.5k!l & 3k!l
resistors set the current levels in the display. A similar arrangement can be used with Nixie® tubes.
The popular LCD displays can be interfaced to the OIP of
the ICL7135 with suitable display drivers, such as the
ICM7211 A as shown in Figure 11. A standard CMOS 4030
QUAD XOR gate is used for displaying the % digit, the polarity, and an 'overrange' flag. A similar circuit can be used
with the ICL7212A LED driver and the ICM7235A vacuum
fluorescent driver with appropriate arrangements made for
the 'extra' outputs. Of course, another full driver circuit
could be ganged to the one shown if required. This would
be useful if additional annunciators were needed. The Figure shows the complete circuit for a 4-% digit (± 2,000V)
AID.
Figure 12 shows a more complicated circuit for driving
LCD displays. Here the data is latched into the ICM7211 by
the STROBE signal and 'Overrange' is indicated by blanking
the 4 full digits.

POWER SUPPLIES
The 7135 is designed to work from ±5V supplies. However, in selected applications no negative supply is required.
The conditions to use a single + 5V supply are:
1. The input signal can be referenced to the center of the
common mode range of the converter.
2. The signal is less than ± 1.5 volts.
See "differential input" for a discussion of the effects this
will have on the integrator swing without loss of linearity.

TYPICAL APPLICATIONS
The circuits which follow show some of the wide variety of
possibilities, and serve to illustrate the exceptional versatility of this AID converter.
Figure 9 shows the complete circuit for a 4-% digit
(±2.000V) full scale) AID with LED readout using the
ICLB069 as a 1.2V temperature compensated voltage reference. It uses the band-gap principal to achieve excellent
stability and low noise at reverse currents down to 50fLA.
The circuit also shows a typical R-C input filter. Depending
on the application, the time-constant of this filter can be
made faster, slower, or the filter deleted completely. The %
digit LED is driven from the 7 segment decoder, with a zero
reading blanked by connecting a D5 signal to RBI input of
the decoder. The 2-gate clock circuit should use CMOS
gates to maintain good power supply rejection.

=""'t::T't-;-=:-t'-:-:--------o.av
I~

•b
t:=~:::~:

'---"""--it

81
12
14

•

;=

-=.'::.*'lIon on see" faclor ac:Ijwt. 101". 10 tum pol or a small pot In ..rie. with.
0342-10

Figure 9: 4-112 Digit AID Converter with a Multiplexed Common Anode LED Display

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPlIEO OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characteriz8d but are not tested.

3-82

ICL7135

C::....
r----j~::Jr>:-pJfl_:;JEl/IB 0 0

4-112 OIGIT LCO OISPLAY

"""'"

~

S~HI V~LTAGE

V+F:

I

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9 RBO
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47K

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......} - 4 - - - - - '

1.02

2.SK

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7409

88

ICL7135

Bl

t-:=.r±:l.i-"J-I-Cl
REF
...
lCiiii....
"r=;;;;;;==:;-i.' ANALOG

~~ALDi'~ =i!

COMMOM

-::-GND
'DDKO

~~'DUT

'~_~=i'NTOUT
1.0pF :

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288'

L

L-----------------+~-~-_~-j--+----~'7ID

TTl T

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3SV
OV

2,3.4

t-

8·'8
37-4D~

OPTIOIIAL
CAPACITOR

OSCl8

V·,

--4t---+5V
"-'DOoF

·5V

0342-14

Figure 12: Driving LCD Displays

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

3-83

•

: ICL7135

....

...
....

S!

A problem sometimes encountered with both LED & plasma-type display driving is that of clock source supply line
variations. Since the supply is shared with the display, any
variation in voltage due to the display reading may cause
clock supply voltage modulation. When in overrange the
display alternates between a blank display and the 0000
overrange indication. This shift occurs during the reference
integrate phase of conversion causing a low display reading
just after overrange recovery. Both of the above circuits
have considerable current flowing in the digital supply from
drivers, etc. A clock source using an LM311 voltage comparator with positive feedback (Figure 13) could minimize
any clock frequency shift problem.
The 7135 is designed to work from ± 5 volt supplies.
However, if a negative supply is not available, it can be generated with an ICL7660 and two capacitors (Figure 14).

,......-----
20Kll

AD7521SD

~

r'1

1

1:r'1 =-

_0

~

Ioun

~

.~a

0

louTt
RF£EDBACK

0330-1

(Switches shown for Digital Inputs "High")
(Resistor values are nominal)
Figure 1: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
300105-003
NOTE: All typIcs/ values havs bes" characterized but IU6 not t88t9d.

4-1

~...

CII

...
...ICII
CII
...
to)

~
Co»

•

c; AD7520/AD7530
~ AD7521/AD7531

!.

(II

10

....
~
o
(II)

10

....

ABSOLUTE MAXIMUM RATINGS

(TA=25'C unless otherwise noted)
Supply Voltage (V +) ............................ + 17V
Operating Temperature
VREF ......................................... ± 25V
IN, KN, LN Versions ................... O'C to + 70'C
Digital Input Voltage Range ................. V+ to GND
JD, KD, LD Versions .................. -25'C to 85'C
Output Voltage Compliance ............. -100mVto V+
SD, TD, UDVersions ............... -55'C to +125'C
Power Dissipation (package)
Storage Temperature .................. -65'C to 150'C
up to + 75'C ............................... 450mW
Lead Temperature (Soldering, 10sec) ............. 300'C
derate above + 75'C @ . . . . . . . . . . . . . . . . . . . . . 6mWI'C
CAUTION:

!o

1) The digital control inputs afe zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep
unused units in conductive foam at all times.

....10
~

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of /he device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

(II

2) Do not apply voltages higher than Voo or less than GND potential on any terminal except VREF and RFEEOBACK·

TOP YIEW

AD7521 (AD7531)

AD7520 (AD7530)
IOUT1

16 RFEEOBACK

IOUT2

YREF

GND

y+

IOUT1

RFEEOBACK

IOUT2

YREF

GND

y+

BIT 1 (MSB)

BIT 12 (LSB)

BIT 10 (LSB)

BIT 2

BIT 11

BIT 2

BIT 9

BIT 3

BIT 10

BIT 3

BIT 8

BIT 4

BIT 9

BIT 4
BIT 7
BIT 5 --._ _ _....._ BIT 6

BIT 5

BIT 8

BIT 1 (MSB)

BIT 8 '"""1...._ _J'= BIT 7
0330-3

0330-2

Figure 2: Pin Configurations

ELECTRICAL CHARACTERISTICS
Parameter

(V+ = + 15V, VREF= + 10V, TA =25'C unless otherwise specified)
AD7520
(AD7530)

Test Conditions

I

AD7521
(AD7531)

Unit

Limit

DC ACCURACY (Note 1)
Resolution

10

Nonlinearity
(Note 2)
VERSION

12

Bits

0.2 (8-Bit)

% ofFSR

Max

K
T

Fig. 3

0.1 (9-Bit)

%ofFSR

Max

L -10V,;;VREF';; + 10V
U

Fig. 3

0.05 (1 O-Bit)

%ofFSR

Max

-

Nonlinearity Tempco
(Notes 2 and 3)
Gain Error (Note 2)

I

J S, T, U: over - 55'C to + 125'C Fig. 3
S

2
-10V,;;VREF,;;+10V

0.3

Gain Error Tempco
(Notes 2 and 3)

10

ppm of FSRI'C Max
%ofFSR

Typ

ppm of FSRI'C Max

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values haVl1 biNln character/zoo but are not tested.

4-2

IfIO~On.. ~

AD7 520/AD7 530
AD7 521/AD7 531

...en

N

ELECTRICAL CHARACTERISTICS

io

(V + = + 15V. VREF = + 10V. TA = 25'C unless otherwise specified)

...en

(Continued)
Parameter

AD7520
(AD7530)

Power Supply Rejection (Note 2)

AD7521
(AD7531)

Co)

Limit

o

200
(300)

nA

Max

...en~

Fig. 4

±0.005

% of FSR/%

Typ

Fig. 8

500

ns

Typ

Over the specified temperature
range

Output Leakage Current
(either output)

I

Unit

Test Conditions

..
...
..
N

~

AC ACCURACY (Note 3)
Output Current Settling Time

To 0.05% of FSR (All digital
inputs low to high and high to
low)
VREF=20V PP. 100kHz
(50kHz) All digital inputs low

Feedthrough Error

Fig. 7

All digital inputs high
IOUT1 at ground.

10

mVpp

Max

5k
10k
20k

0

Min
Typ
Max

ANALOG OUTPUT
Voltage Compliance (both outputs)

(Note 3)

Output Capacitance
(Note 3)

IOUT1
IOUT2

All digital inputs high

Fig. 6

See absolute max. ratings
120
37

pF
pF

Typ
Typ

IOUT1
IOUT2

All digital inputs low

Fig. 6

37
120

pF
pF

Typ
Typ

Output Noise (both outputs)
(Note 3)

Fig. 5

Equivalent to 10kO
Johnson noise

Typ

DIGITAL INPUTS
Low State Threshold

Over the specified temp range

High State Threshold
Input Current (low to high state)
Input Coding

See Tables 1 & 2

0.8

V

Max

2.4

V

Min

1

",A

Typ

Binary/Offset Binary

POWER REQUIREMENTS
Power Supply Voltage Range

1+

+5to +15

V

All digital inputs at OV or V +

1

",A

Typ

All digital inputs high or low

2

mA

Max

20

mW

Typ

Total Power Dissipation
(Including the ladder network)
NOTES: 1.

Full scale range (FSR) is 10V for unipolar and ± 10V for bipolar modes.
2. Using internal feedback resistor, RFEEDBACK.
3. Guaranteed by design, not subiect to test.
4. Accuracy not guaranteed unless outputs at GND potential.

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

4-3

en
Co)

REFERENCE INPUT
Input Resistance

CI

;; AD7520/AD7530
~ AD7 521/AD7 531

!...
N

II)

....
~

TEST CIRCUITS NOTE: The following test circuits
apply for the AD7520. Similar circuits are used for the
AD7530, AD7521 and AD7531 .

He

--_.....

BIT 1 (MS8) 15

h--~'

oC')

,.15

,.

'4

Ne

II)

....

100 mV,.,
1MHz

!o

0330-7

Figure 6: Output Capacitance

N

II)

....

.::II

C

VAEF

=

20V

p.p 100 kHz SINE WAVE

+1SV

BIT 1 (MSB)

81T11

BIT 12

0330-4

BIT 10 (LSB)

Figure 3: Nonlinearity

0330-8

Figure 7: Feedthrough Error

+15V
..10 V

,!~IUU1
DIGITAL INPUT

"VA",',-'_ _,

st: 1% SETTLlNQ (1 mY)
81: 0.03% SETTLING
t=rIA lime

,

i
0330-9

0330-5

Figure 8: Output Current Settling Time

Figure 4: Power Supply Rejection

DEFINITION OF TERMS

.;.l1Y (ADJUST FOR Vour = OV)

NONLINEARITY: Error contributed by deviation of the DAC

+15Y

transfer function from a best straight line function. Normally
expressed as a percentage of full scale range. For a multiplying DAC, this should hold true over the entire VREF
range.
RESOLUTION: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2- n) (VREF). A
bipolar converter of n bits has a resolution of [2 - (n -1 l]
[VREF]. Resolution in no way implies linearity.
SETTLING TIME: Time required for the output function of
the DAC to settle to within % LSB for a given digital input
stimulus, i.e., 0 to Full Scale.
GAIN: Ratio of the DAC's operational amplifier output voltage to the nominal input voltage value.
FEEDTHROUGH ERROR: Error caused by capacitive coupling from VREF to output with all switches OFF.

0330-6

Figure 5: Noise

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOT£: All typical values have been characterized but arB not tested.

4-4

AD7 520/ AD7 530
AD7521/AD7531
OUTPUT CAPACITANCE: Capacitance from IOUT1 and
IOUT2 terminals to ground.
OUTPUT LEAKAGE CURRENT: Current which appears on
IOUT1 terminal with all digital inputs LOW or on IOUT2 terminal when all inputs are HIGH.

~---~r-~---~---r--

DETAILED DESCRIPTION
The AD7520 (AD7530) and AD7521 (AD7531) are monolithic, multiplying DI A converters. A highly stable thin film R2R resistor ladder network and NMOS SPDT switches form
the basis of the converter circuit, CMOS level shifters permit
low power TTLICMOS compatible operation. An external
voltage or current reference and an operational amplifier
are all that is required for most voltage output applications.
A simplified equivalent circuit of the DAC is shown in Figure 9. The NMOS SPDT switches steer the ladder leg currents between IOUT1 and IOUT2 buses which must be held
either at ground potential. This configuration maintains a
constant current in each ladder leg independent of the input
code.

DTLlTTUCMOS
INPUT

0330-11

Figure 10: CMOS Switch

+15V
VREF - - - - ,

BIT 1 (MU)
10Kn

10Kn

10lUl

10KU

DIGITAL

(15117)

INPUT

15

1
:

~1Oi:w~13~;....J
BIT 10 (LSS)

Your

GND

"'"

PIT: '-t--.....-

...........- -......- ........---o:~~~

::

0330-12

Figure 11: Unipolar Binary Operation
(2-Quadrant Multiplication)

RFEEoaACK

(18/11)

TABLE 1
CODE TABLE - UNIPOLAR BINARY OPERATION

0330-10
(Switches shown for Digital Inputs ""High"")

Figure 9: 752017521 Functional Diagram

Digital Input

Analog Output

Converter errors are further reduced by using separate
metal interconnections between the major bits and the outputs. Use of high threshold switches reduces the offset
(leakage) errors to a negligible level.
The level shifter circuits are comprised of three inverters
with a positive feedback from the output of the second to
the first, (Figure 10). This configuration results in TTL!
CMOS compatible operation over the full military temperature range. With the ladder SPDT switches driven by the
level shifter, each switch is binarily weighted for an ON resistance proportional to the respective ladder leg current.
This assures a constant voltage drop across each switch,
creating equipotential terminations for the 2R ladder resistors and highly accurate leg currents.

1111111111

-VREF (1-2- n)

1000000001

-VREF(%+2- n)

1000000000

-VREF/2

0111111111

-VREF (%-2- n)

0000000001

-VREF (2- n)

0000000000

0

NOTE: 1. LSB=2- n VREF
2. n= 10 for 7520,7530
n= 12 for 7521, 7531

APPLICATIONS

Unipolar Binary Operation
The circuit configuration for operating the AD7520
(AD7530) and AD7521 (AD7531) in unipolar mode is shown
in Figure 11. With positive and negative VREF values the
circuit is capable of 2-Quadrant multiplication. The "Digital
Input Codel Analog Output Value" table for unipolar mode is
given in Table 1.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical va/tHIs have bgen characterized but are not tested

4-5

•

~

AD7520/AD7530
~ AD7521/AD7531
.::II

..

~
(II
II)

....

~

o
ell)

2.

Adjust the offset zero adjust trimpot of the output
operational amplifier for OV ± 1 mV at VOUT.

GAIN ADJUSTMENT
1.

Connect all AD7520 (AD7530) or AD7521 (AD7531)
digital inputs to V + .
Monitor VOUT for a -VREF (1-2-n) reading. (n=10
for AD7520 (AD7530) and n = 12 for AD7521
(AD7531)).
To decrease VOUT, connect a series resistor (0 to
500n) between the reference voltage and the VREF
terminal.
To increase VOUT, connect a series resistor (0 to
500n) in the IOUTl amplifier feedback loop.

II)

....

2.

~
o
(II

3.

.::II

II)

....
.::II

C

A "Logic 1" input at any digital input forces the corresponding ladder switch to steer the bit current to IOUTl bus.
A "Logic 0" input forces the bit current to IOUT2 bus. For
any code the IOUTl and IOUT2 bus currents are complements of one another. The current amplifier at IOUT2 changes the polarity of IOUT2 current and the transconductance
amplifier at IOUTl output sums the two currents. This configuration doubles the output range but halves the resolution
of the DAC. The difference current resulting at zero offset
binary code, (MSB = "Logic 1", All other bits = "Logic 0"), is
corrected by using an external resistor, (10 Megohm), from
VREF to IOUT2·

ZERO OFFSET ADJUSTMENT
Connect all digital inputs to GND.
1.

4.

OFFSET ADJUSTMENT
1.
2.
3.

Bipolar (Offset Binary) Operation

4.

The circuit configuration for operating the AD7520
(AD7530) or AD7521 (AD7531) in the bipolar mode is given
in Figure 12. Using offset binary digital input codes and positive and negative reference voltage values, 4-Quadrant
multiplication can be realized. The "Digital Input Codel Analog Output Value" table for bipolar mode is given in Table 2.

5.

Adjust VREF to approximately + 10V.
Connect all digital inputs to "Logic 1".
Adjust IOUT2 amplifier offset adjust trimpot for OV
± 1mV at IOUT2 amplifier output.
Connect MSB (Bit 1) to "Logic 1" and all other bits
to "Logic 0".
Adjust IOUTl amplifier offset adjust trimpot for OV
± 1 mV at VOUT.

GAIN ADJUSTMENT
1.
2.

...

~"------~--~------~VVv-------~

3.
4.

Connect all digital inputs to V + .
Monitor VOUT for a -VREF (1-2-(n-l») volts reading. (n = 10 for AD7520 and AD7530, and n = 12 for
AD7521 and AD7531).
To increase VOUT, connect a series resistor of up to
500n between VOUT and RFEEDBACK'
To decrease VOUT, connect a series resistor of up
to 500n between the reference voltage and the
VREF terminal.

POWER DAC DESIGN USING AD7520
A typical power DAC designed for 8 bit accuracy and 10
bit resolution is shown in Figure 13. An INTERSIL ICH8510
power operational amplifier (1 Amp continuous output at up
to ±25V) is driven by the AD7520.
A summing amplifier between the AD7520 and the
ICH8510 is used to separate the gain block containing the
AD7520 on-chip resistors from the power amplifier gain
stage whose gain is set only by the external resistors. This
approach minimizes drift since the resistor pairs will track
properly. Otherwise the AD7520 can be directly connected
to the ICH8510, by using a 25V reference for the DAC.
An important note on the AD7520/1 01 A interface concerns the connection of pin 1 of the DAC and pin 2 of the
101 A. Since this pOint is the summing junction of an amplifier with an AC gain of 50,000 or better, stray capaCitance
should be minimized; otherwise instabilities and poor noise
performance will result. Note that the output of the 101 A is
fed into an inverting amplifier with a gain of - 3, which can
be easily changed to a non-inverting configuration. (For
more information see: INTERSIL Application Bulletin A021:
Power D/A Converters Using The IH8510 by Dick
Wilenken.)

0330-13

Figure 12: Bipolar Operation
(4-Quadrant Multiplication)

TABLE 2
CODE TABLE -

BIPOLAR (OFFSET BINARY)
OPERATION

DIGITAL INPUT

ANALOG OUTPUT

1111111111

-VREF (1-2-(n-l»)

1000000001

-VREF (2-(n-l»)

NOTE: 1.

1000000000

0

0111111111

VREF (2-(n-l»)

0000000001

VREF (1-2-(n-l»)

0000000000

VREF

LSB~2-(n-1)

VREF
2. n ~ 10 for 7520 and 7521
~ 12 for 7530 and 7531

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

4-6

AD7 520/AD7 530
AD7 521/ AD7 531

.

30Kn

II

. . - - - -.... 3

BIT
-SWITCH!I

{

,

VAEF (±10Y)

,.

+15Y

•I==L 13
•

12

•
7

11
"

•

LaB}

•

10Kfl

:~ITCH!I
100pl

1.IKO

....
-1SY

0330-14

Figure 13: Basic Power DAC

•

Analog/Digital Division
With the AD7520 connected in its normal multiplying configuration as shown in Figure 13, the transfer function is:

+15V

A1 A2 A3
An)
VO= -VIN ( 21"+ 22 + 23 + ... 2n
where the coefficients Ax assume a value of 1 for an ON bit
and 0 for an OFF bit.
By connecting the DAC in the feedback of an operational
amplifier, as shown in Figure 14, the transfer function becomes:

Vo = (A1

,.

BIN (MSI) 15

::;::==1:

II

V,N

DIGITAL:
INPUT

i

a1T~10 (LBB)

-~~N

YOUT

13

3

0330-15

A2
An)
21"+22 +23 +"'2n

Figure 14: Analog/Digital Divider
For further information on the use of this device, see the
following Application Bulletins:

This is division of an analog variable (VIN) by a digital
word. With all bits off, the amplifier saturates to its bound,
since division by zero isn't defined. With the LSB (Bit-10)
ON, the gain is 1023. With all bits ON, the gain is 1 (± 1
LSB).

A016
A018
A020
A021

"Selecting AID Converters," by David Fullagar
"Do's and Don'ts of Applying AID Converters," by
Peter Bradshaw and Skip Osgood
"A Cookbook Approach to High-Speed Data Acquisition and Microprocessor Interfacing" by Ed Sliger
"Power DIA Converters Using the IH8510," by Dick
Wilenken

INTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

4-7

= AD7523

II)

too

8-Bit Multiplying

~ 01 A Converter

GENERAL DESCRIPTION

FEATURES

The AD7523 is a monolithic, low cost, high performance,
10 bit accurate, multiplying digital-to-analog converter
(DAC), in a 16-pin DIP.
Intersil's thin-film resistors on CMOS circuitry provide 8bit resolution (8, 9 and 10-bit accuracy), with TIL/CMOS
compatible operation.
The AD7523's accurate four quadrant multiplication, full
military temperature range operation, full input protection
from damage due to static discharge by clamps to V + and
GND, and very low power dissipation make it a very versatile converter.
Low noise audio gain controls, motor speed controls, digitally controlled gain and attenuators are a few of the wide
range of applications of the 7523.

• 8, 9 and 10 Bit Linearity
•
•
•
•

Low Gain and Linearity Temperature Coefficients
Full Temperature Range Operation
Static Discharge Input Protection
DTL/TIL/CMOS Compatible
• + 5 to + 15 Volts Supply Range
• Fast Settling Time: 150ns Max at 25·C
• Four Quadrant Multiplication

ORDERING INFORMATION
Part Number/Package

Nonlinearity
Plastic DIP

CERDIP

CERDIP

0.2%
(8 Bit)

AD7523JN

AD7523AD

AD7523SD

0.1%
(9 Bit)

AD7523KN

AD7523BD

AD7523TD

0.05%
(10 Bit)

AD7523LN

AD7523CD

AD7523UD

O·Cto +70·C

- 25·C to + 85·C

-55·Cto +125·C

TEMPERATURE RANGE

VREFIN

10Kn

10KU

10KU

10KU

OUT1

?

(15)

2OKU;> 20KU;> 2OK1!

SPO!

r'! , rh r'it

SWIT~':t~~ I :,
I

6

I

I

I

I

I

I

o

o

USB

BITZ

BITa

(4)

(5)

(6)

,

II ~ ~ AFEEO.ACK

OUT2

[!

j!!l VAEFIN

GNO

11

IBJ V+

BIT 1 (USB)

[!

AD7523

~ NC

1m NC

BIT 2 (]

IOUT2(2)
10uTI (1)

BIT 3

[!

~ BIT 8 (LSB)

RFEEDBACK

BIT 4

I!

BIT 5

[!

~ BIT 7
~ BITS

10KI!

~(16)

TOP VIEW
0331-1

Figure 1: Functional Diagram
(Switches shown for Digital Inputs "High")

0331-2

Figure 2: Pin Configuration
Outline Drawings DE, PE

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR use.

NOTE: All typIcsl valuss MVS bHn cluiract6riztNJ but are not tHt«l

4-8

AD7523
ABSOLUTE MAXIMUM RATINGS (TA = 25'C unless otherwise noted)
Supply Voltage (V +) ............................ + 17V
Ceramic PackageVREF ......................................... ±25V
up to 75'C ................................. 450mW
Digital Input Voltage Range ................. V+ to GND
derate above 75'C by ....................... 6mW/'C
Output Voltage Compliance ............. -100mV to V+
Operating Temperatures
Power Dissipation:
IN, KN, LN Versions ................... O'C to + 70'C
Plastic Package AD, BD, CD Versions . . . . . . . . . . . . . . .. - 25'C to + B5'C
up to + 70'C ............................... 670mW
SD, TD, UD Versions . . . . . . . . . . . . . .. - 55'C to + 125'C
derate above + 70'C by ................... B.3mWI'C
Storage Temperature ................ -65'C to + 150'C
Lead Temperature (Soldering, 10sec) ........... + 300'C
CAUTION:
1. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused
units in conductive foam at all times.
2. Do not apply voltages higher than VDD and lower than GND to any terminal except VREF+ RFEEDBACK.

NOTE: Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only snd functionsl
operation of the device st these or any other conditions above those indicated in the operationsl sec/ions of the specificstions is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V+ = + 15V, VREF = + 10V unless otherwise specified)
Test Conditions

Parameter

TA
Min-Max

TA
+ 25'C

Unit

Limit

DC ACCURACY (Note 1)
Resolution
Nonlinearity (Note 2)

(±% LSB)

B

B

Bits

Min

±0.2

±0.2

%ofFSR

Max

(±%LSB)

-10V,,;VREF,,;+10V

±0.1

±0.1

% ofFSR

Max

(±Ys LSB)

VOUT1 =VOUT2=OV

±0.05

±0.05

%ofFSR

Max

Gain Error (Note 2)

Digital Inputs high.

±1.5

% ofFSR

Max

Nonlinearity Tempco (Notes 2 and 3)

-10VVREF +10V

Monotonicity

Guaranteed
±1.B

ppm of FSRI'C Max

2

Gain Error Tempco (Notes 2 and 3)

10

Output Leakage Current (either output)

ppm of FSRI'C Max

VOUT1 =VOUT2=O

±50

±200

nA

Max

ACACCURACY
Power Supply Rejection (Note 2)
Output Current Settling Time (Note 3)
Feedthrough Error (Note 3)

V+ = 14.0 to 15.0V

0.02

0.03

% ofFSR

Max

To 0.2% of FSR, RL = 1000

150

200

ns

Max

VREF = 20V pp, 200kHz sine wave.
All digital inputs low.

±%

±1

LSB

Max

0

r---

REFERENCE INPUT
5K
Input Resistance (Pin 15)

All digital inputs high. IOUT1 at ground.

Temperature Coefficient (Note 3)

Min

Max

20K
-500

ppml'C

Max

100

pF

Max

30

pF

Max

ANALOG OUTPUT
Output Capacitance
(Note 3)

COUT1

All digital inputs high (VINH)

COUT2
COUT1

All digital inputs low (VINL)

COUT2

30

pF

Max

100

pF

Max

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: Aft typical values have been charactBrizsd but are not tested.

4·9

•

= AD7523

.D~Dn.

...

10

~ ELECTRICAL CHARACTERISTICS

(v+ = + 15V, VREF= + 10V unless otherwise specified) (Continued)

Parameter

Test Conditions

TA
+ 25°C

I

TA
Min-Max

Unit

Limit

DIGITAL INPUTS
Low State Threshold (VINU

0.8

V

Max

High State Threshold (VINH)

2.4

V

Min

p,A

Max

4

pF

Max

+5to +16

V

I

rnA

Input Current (Low or high)

VIN=OVor +15V

±1

Input Coding

See Tables 1 & 2

Binary/Offset Binary

Input Capacitance (Note 3)
POWER REQUIREMENTS
Power Supply Voltage Range

Accuracy is tested and guaranteed
at V+ = +15V, only.

1+

All digital inputs low or high.

NOTES: 1.
2.
3.
4.

2

2.5

Max

Full scale range (FSR) 18 10V for unipolar and ± 10V for bipolar modes.
Using Internal feedback resistor. RFEEDBACK.
Guaranteed by design; not subiect to test.
Aocuracy not guarantesd unleBB outputs at ground potential.

Table 1. Unipolar Binary Code Table

APPLICATIONS

Digital Input
MSB LSB

UNIPOLAR OPERATION
!1DV

v""'

+'IV

..
R,

NOTa:
1. "' AND

Analog Output

(255)
256

11111111

-VREF

10000001

-VREF

10000000

-VREF

C29)
C28)=-

01111111

-VREF

C27)

00000001

-VREF

(2~6)

00000000

-VREF

(2~6)=0

fl. U81D OtI.Y IP GAIN

AlNUlTMENT 18 RIQUIRID.

a. Cllt1 PROTECTS AD71D AGAfNer
NEGATIYI TftAN8IENTI•
"21k

DATA lua8
..PUTS· L. . 11

0331-3

256

256

VREF
2

256

Figure 3: Unipolar Binary Operation

NOTE: 1 LSB=(2- 8) (VREF)=

C!s)

(VREF)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical vsJuss"... bHn _

but oro not _ _

4-10

IIJD~DI!. ~

AD7523

...
CII

Table 2. Bipolar (Offset Binary) Code Table

BIPOLAR OPERATION

Digital Input
::10V

MSB

"15V

:

Analog Output

LSB

VREF

11111111

-VREF

10000001

-VREF

0331-4

Figure 4: Bipolar Operation

NOTE:

128

C~8)
0

10000000

NOTES:
1. R3/R4 MATCH 0.1% OR BEITER.
2. Rl, R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
3. R5·R7 USED TO ADJUST VOUT~OV AT INPUT CODE
10000000.
4. CRl & CR2 PROTECT AD7523 AGAINST NEGATIVE TRAN·
SIENTS.

C27)

C~8)

01111111

+VREF

00000001

+VREF

C27)

00000000

+VREF

C28)

1LSB~(2-7)

(VREF)~ (1~8)

128

128

(VREF)

A typical power DAC designed for 10 bit accuracy and 8
bit resolution is shown in Figure 5. The Intersil ICH8510
power operational amplifier (1 Amp continuous output with
up to + 25V) is driven by the AD7523.
A summing amplifier between the AD7523 and the
ICH8510 is used to separate the gain block containing the
AD7520 on-chip resistors from the power amplifier gain
stage, whose gain is set only by the external resistors. This
approach minimizes drift since the resistor pairs will track
properly. Otherwise AD7523 can be directly connected to
the ICH8510, by using a 25 volt reference for the DAC.

POWER DAC DESIGN USING AD7523
,----------;1

16~--------------------_,
VREF (±10V)

.-----12
15
.....- - - - - - 1 3
14
4 INTERSIL 13
5 AD7523 12

-

{

BIT
SWITCHES

11
10

+15V
NC
NC
}

O.68n

10Kll

VOUT

BIT
SWITCHES

100pf

0.6an
7.5Kn

0331-5

Figure 5: Basic Power DAC Design

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

4-11

•

: AD7823
II)

....
~

DEFINITION OF TERMS
NONLINEARITY: Error contributed by deviation of the DAC
transfer function from a best straight line function. Normally
expressed as a percentage of full scale range. For a multiplying DAC, this should hold true over the entire VREF
range.
RESOLUTION: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2- n) (VREF). A
bipolar converter of n bits has a resolution of [2 - (n -1 l]
[VREF]. Resolution in no way implies linearity.
SETTLING TIME: Time required for the output function of
the DAC to settle to within % LSB for a given digital input
stimulus, i.e., 0 to Full Scale.
GAIN: Ratio of the DAC's operational amplifier output voltage to the nominal input voltage value.
FEEDTHROUGH ERROR: Error caused by capacitive coupling from VREF to output with all switches OFF.
OUTPUT CAPACITANCE: Capacity from IOUT1 and IOUT2
terminals to ground.
OUTPUT LEAKAGE CURRENT: Current which appears on
IOUT1 terminal with all digital inputs LOW or on IOUT2 terminal when all inputs are HIGH.

AD7523
OUT1

t

VOUT "" - VIN/o

3

WHERE:
VREF

o ==

BIT1

21

+ !IT! +... !!.!!
22

28

( O400k
for effective input offset less than 25", V).
The reference inverting amplifier used in the bipolar mode
circuit must also be selected carefully. If 14-bit accuracy is
desired without adjustment, low input bias current (less than
1nA), low offset voltage (less than 50",V), and high gain
(greater than 400k) are recommended. If a fixed reference
voltage is used, the gain requirement can be relaxed. For
highest accuracy (better than 13 bits), an additional op-amp
may be needed to correct for IR drop on the Analog
GrouND line (op-amp A2 in Figure 11). This op-amp should
be selected for low bias current (less than 2nA) and low
offset voltage (less than 50",V).

The V+ (pin 25) power supply should have a low noise
level, and no transients exceeding 7 volts. Note that the
absolute maximum digital input voltage allowed is V+,
which therefore must be applied before digital inputs are
allowed to go high. Unused digital inputs must be connected to GND or V+ for proper operation.

Unipolar Binary Operation (lCL7134U)
The circuit configuration for unipolar mode operation
(ICL7134U) is shown in Figure 10. With positive and negative VREF values the circuit is capable of two-quadrant multiplication. The "digital input code/analog output value" table
for unipolar mode is given in Table 3. The Schottky diode
(HP5082-2811 or equivalent) protects lOUT from negative
excursions which could damage the device, and is only necessary with certain high speed amplifiers. For applications
where the output reference ground point is established
somewhere other than at the DAC, the circuit of Figure 11
can be used. Here, op-amp A2. removes the slight error due
to IR voltage drop between the internal Analog GrouND
node and the external ground connection. For 13-bit or lower accuracy, omit A2 and connect AGNDF and AGNDs directly to ground through as Iowa resistance as possible.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AJI typical values haV9 been characterized but are not tested.

4-38

ICL7134
ZERO OFFSET ADJUSTMENT
1.
Connect all data inputs and WR, CS, Ao and A1 to
DGND.
2.
Adjust offset zero-adjust trim-pot of the operational
amplifier A2, if used, for a maximum of OV ±50",V
at AGNDs.
3.
Adjust the offset zero-adjust trim-pot of the output
op-amp, A1, for a maximum of OV ±50",V at VOUT.
GAIN ADJUSTMENT (OPTIONAL)
1.
Connect all data inputs to V + , connect WR, CS, Ao
and A1 to DGND.
2.
Monitor VOUT for a -VREF (1 - % 14) reading.
3.
To decrease VOUT, connect a series resistor of
loon or less between the reference voltage and
the VRFM and VRFL terminals (pins 20 and 18).
4.
To increase VOUT, connect a series resistor of
lOOn or less between A1 output and the RFB terminal (pin 21).

VflEF IN - - - . . - - - - ,

DATA
INPUTS

+sv

17

0341-10

Figure 10: Unipolar Binary, Two-Quadrant
Multiplying Circuit

Bipolar (2'5 Complement) Operation
(ICL7134B)
The circuit configuration for bipolar mode operation
(ICL7134B) is shown in Figure 12. Using 2's complement
digital input codes and positive and negative reference voltage values, four-quadrant multiplication is obtained. The
"digital input codel analog output value" table for bipolar
mode is given in Table 4. Amplifier A3, together with internal
resistors RINV1 and RINV2, forms a simple voltage inverter
circuit. The MSB ladder leg sees a reference input of approximately - VREF, so the MSB's weight is reversed from
the polarity of the other bits. In addition, the ICL7134B's
feedback resistance is switched to 2R under PROM control,
so that the bipolar output range is + VREF to - VREF
(1 - % 13). Again, the grounding arrangement of Figure 11
can be used, if necessary.

DATA
INPUTS

ICl7134U

Table 4: Code Table - Bipolar
(2's Complement) Operation
Digital Input

Analog Output

01111111111111
00000000000001
00000000000000
11111111111111
10000000000001
10000000000000

-VREF(1-'!213)
-VREF('!213)
0
VREF('!213)
VREF(1-%13)
VREF

0341-11

Figure 11: Unipolar Binary Operation
with Forced Ground

Table 3: Code Table - Unipolar Binary
Operation
Digital Input

Analog Output

11111111111111
10000000000001
10000000000000
01111111111111
00000000000001
00000000000000

-VREF(1-'!214)
-VREF(%+'!214)
-VREF/2
-VREF('/2-% 14)
-VREF('!214)
0

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTAB1L1TY AND F1TNESS FOR A PARTICULAR USE.
NOTE: A/J typical values haV9 been characterized but are not tested.

4-39

:: ICL7134

...
too

g
YRIFIN
18
YRFL
RlNY1

18
15

18
RlNY
RlNV2

20
YAFM Y+

o,a(MSB)

RF8

21

0,2

loUT
DATA
INPUTS

ICL7134B

3
+5Y 17

Do(LSB)
PROG

0341-12

Figure 12: Bipolar (2'8 Complement), Four-Quadrant Multiplying Circuit

OFFSET ADJUSTMENT
1.
2.

3.

4.
5.

Connect all data inputs and WR', ~, Ao and A1 to
DGND.
Adjust the offset zero-adjust trim-pot of the operational amplifier A2, if used, for a maximum of OV
±50",V at AGNDs.
Set data to 00000 .... 00. Adjust the offset zeroadjust trim-pot of the output op-amp A1, for a maximum of OV ±50",V at VOUT.
Connect D13 (MSB) data input to V+.
Adjust the offset zero-adjust trim-pot of op-amp Aa
for a maximum of OV ±50",V at the RINV terminal
(pin 19).

3.
4.

5.

Processor Interfacing
The ease of interfacing to a processor can be seen from
Figure 13, which shows the ICL7134 connected to an 8035
or any other processor such as an 8049. The data bus
feeds into both register inputs; three port lines, in combination with the WR line, control the byte-wide loading into
these registers and then the DAC register. A complete DAC
set-up requires 4 write instructions to the port, to set up the
address and ~ lines, and 3 external data transfers, one a
dummy for the final transfer to the DAC register.

GAIN ADJUSTMENT (OPTIONAL)
1.
2.

Monitor VOUT for a -VREF (1-Yz13) reading.
To increase VOUT, connect a series resistor of
2000 or less between the A1 output and the RFB
terminal (pin 21).
To decrease VOUT, connect a series resistor of
1000 or less between the reference voltage and
the VRFL terminal (pin 18).

Connect WR', ~, Ao and A1 to DGND.
Connect Do, D1 ... D12 to V+, D13 (MSB) to
DGND.

IN1ERSIL'S SOLE AND EXCL.USIV£ WARRANTY OBUGATION WITH REBFECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE ODNDmON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR Use.
NOTE:AHtypIcM _ _ _ _ bul .... , . , , _ .

4-40

IfID~Ol\.

ICL7134

P
...

....
61

+5V IN

.sv

.........
"'0-17

} OTHER

IN

...

.

'"::,010

Do

...

0,
0,

loUT

'MIOC35

P"

,/0

Co
A,

805D

"41
ETC.

DB,

Viii

leLM34

Do
AGNo.

Do,

Viii
0341-14

Figure 14: Interface to 80ao System
0341-13

Figure 13: ICL7134 Interface to 8048 System

Aa-,.t=======~=--'--------------.--------.
8212

ICL7134

0341-15

Figure 15: 8085 System Interface

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH REBPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE OCNDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIEB OF
MERCHANTABILITY AND FITNEBS FOR A PARTICULAR USE.

NOTe: AU typicBI .../USS have b66n chJJrsc/orfzod but are not tos/sd.

4-41

.......~

d_

.D~OIl.

ICL7134

ure 15. The decoding of the 10/M line, which controls memory-mapped or I/O-mapped operation, is arbitrary, and can
be omitted if not necessary. Neither the MC6BOX nor R650X
processor families offer specific I/O operations. Figure 16
shows a suitable interface to either of these systems, using
a direct connection. Several other decoding options can be
used, depending on the other control signals generated in
the system. Note that the R650X family does not require
VMA to be decoded with the address lines.

A similar arrangement can be used with an BOBOA, B22B,
and B224 chip set. Figure 14 shows the circuit, which can
be arranged as a memory-mapped interface (using ~EMW)
or as an I/O-mapped interface (using I/O WRIT ). See
A020 and R005 for discussions of the relative merits of
memory-mapped versus I/O-mapped interfacing, as well as
some other ideas on interfacing with BOBO processors. The
BOBS processor has a very similar interface, except that the
control lines available are slightly different, as shown in Fig-

1CL7134

MC.680X
MCIH50X

L-_ _---' OPTIONAL

GATE
(SEE TEXT)

0341-17
0341-16

Figure 17: Avoiding Digital Feedthrough
in an 8048 to ICL7134 Interface

Figure 16: R650X and MC680X
Families' Interface to ICL7134

INTERSIL
III8OC48
INTEL
8080
8085

ANALOG~
CIRCUIT

L-...y'

ETC.

0341-18

Figure 18: ICL7134 to 8048/80/85 Interface with Low Feedthrough

INTERSIL'S SOLE AND exCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTV ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE exCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITV AND FITNESS FOR A PARTICULAR USE.

NOTE: An fMJ/OII- ""VB bHn _

but Me not tfi/od.

4-42

IIU~UIL

ICL7134
Digital Feedthrough

visable (see A053). The clock, using two Schmitt trigger TTL
gates, runs at a slower rate for the first 8 bits, where settling-time is most critical, than for the last 6 bits. The shortcycle line is shown tied to the 15th bit; if fewer bits are
required, it can be moved up accordingly. The circuit will
free-run if the HOLD/RUN input is held low, but will stop
after completing a conversion if the pin is high at that time.
A low-going pulse will restart it. The STATUS output indicates when the device is operating, and the falling edge
indicates the availability of new data. A unipolar version may
be constructed by tying the MSB (D13) on an ICL7134U to
pin 14 on the first AM25L03, deleting the reference inversion amplifier A4, and tying VRFM to VRFL.

All of the direct interfaces shown above can suffer from a
capacitive coupling problem. The 14 data pins, and 4 control pins, all tied to active lines on a microprocessor bus,
and in close proximity to the sensitive DAC circuitry, can
couple pseudo-random spikes into the analog output. Careful board layout and shielding can minimize the problems
(see PC layout), and clearly wire-wrap type sockets should
never be used. Nevertheless, the inherent capacitance of
the package alone can lead to unacceptable digital feedthrough in many cases. The only solution is to keep the
digital input lines as inactive as possible. One easy way to
do this is to use the peripheral interface circuitry available
with all the systems previously discussed. These generally
allow only 8 bits to be updated at anyone time, but a little
ingenuity will avoid difficulties with DAC steps that would
result from partial updates. The problem can be solved for
the 8048 family by tying the 14 port lines to the data input
lines, with CS, Ao and A1 held low, and using only the WR
line to enter the data into the DAC (as shown in Figure 17).
WR is well separated from the analog lines on the ICL7134,
and is usually not a very active line in 8048 systems. Additional "protection" can be achieved by gating the processor
WR line with another port line. The heavy use of port lines
can be alleviated by use of the IM82C43 port expander. The
same type of technique can be employed in the 8080/85
systems by using an 8255 PIA (peripheral Interface adapter)
(Figure 18) and in the MC680X and R650X systems by using an MC6820 (R6520) PIA.

PC BOARD LAYOUT
Great care should be taken in the board layout to minimize ground loop and similar "hidden resistor" problems, as
well as to minimize digital signal feedthrough. A suitable layout for the immediate vicinity of the ICL7134 is shown in
Figure 20, and may be used as a guide.

APPLICATION NOTES
Some applications bulletins that may be found useful are
listed here:

Successive Approximation AID
Converters
Figure 19 shows an ICL7134B-based circuit for a bipolar
input high speed AID converter, using two AM25L03s to
form a 14-bit successive approximation register. The comparator is a two-stage circuit with an HA2605 front-end amplifier, used to reduce settling time problems at the summing node (see A020). Careful offset-nulling of this amplifier
is needed, and if wide temperature range operation is desired, an auto-null circuit using an ICL7650 is probably ad-

A016

"Selecting AID Converters," by Dave Fullagar.

A017

"The Integrating AID Converter," by Lee Evans.

A018

"Do's and Dont's of Applying AID Converters," by
Peter Bradshaw and Skip Osgood.

A020

"A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing," by Ed Sliger.

A021

"Power AID Converters Using the ICH8510," by
Dick Wilenken.

A030

"The ICL71 04 - A Binary Output AID Converter for
Microprocessors," by Peter Bradshaw.

R005

"Interfacing Data Converters & Microprocessors,"
by Peter Bradshaw et ai, Electronics, Dec. 9, 1976.

Most of these are available in the Intersil Data Acquisition
Handbook, together with other material.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

4-43

n...
.......

Col

...

.......~

ICL7134

g

-2- ~>
+15V

f+

~5V

18

19

DGND VAL
f-J CS
~ -WR

~
~

A;,
A,

+

.... HP2IIOO

VIN

.;

.....

A3

0;..

1'-

22)

-

20

24
IItNY VAMAGNDs

r}
!*"

~l17f

+5V

23
21
25
PROG V + AGND. R.B louT

HAae05

ICL7134B

+

MSB
16 15 1413 12 1110 9

"7

LSB
8 7 8 5 4 3

LSBL _

IN827A

':,j r'
to.

-15V

+5V.

+

~"~

5V
8800

+LM311

OUT

*

HP2IIOO

-15V

~-

lMIl
1301l
~

-15V

--t++-. BLUE
256x12 RAM

PO-P7

AND

OVO-OV1

r-t-HI-+

RED

3x 12 OVERLAY
REGISTERS

~.-t-H"'" GREEN

BRIGHT
BLANK
HSYNC
VSYNC

4

Figure 1: Functional Diagram

0082-1

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALlE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
601140-001
NOTe: AU typical valUflS haVB bsBn chsractetfZ6d but sre not tested.

4-46

IIU~OIl..

IM2110
ABSOLUTE MAXIMUM RATINGS
Supply Voltages .................................. 6.0V
VIH (Input Logic "1" Voltage) ......... 2.0V to Voo + 0.5V
VIL (Input Logic "0" Voltage) .............. -0.5V to O.BV
Power Dissipation (Plastic Package) ............. 600 mW
Operating Temperature .................... O'C to + 70'C
Storage Temperature ................. - 65'C to + 150'C
Lead Temperature (Soldering, 10 sec.) ............. 300'C

ADD

VDD

AD'

P7

AD2

P6

AD3

PS

AD4

P4

ADS

P3

AD6

P2

AD7

P'
PO

ADa

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AD9

BIAS

AD,O

BLUE

AD"
elK

VAA

RED

cs

GREEN

ALE

IREF

ViR

GND

R5

BRIGHT

TEST

BLANK

ovo
ov,

VSYNe

HSYNe

0062-2

Figure 2: Pin Configuration

OPERATING CONDITIONS
Symbol

Parameter

Voo, VAA

Positive Supply Voltage

TA

Ambient Temperature

RSET

Typ

Min

Max

Units

4.5

5.5

V

0

+70

'C

Resistive Load on DAC Outputs

37.5

n

Capacitive Load on DAC Outputs

50

pF

1050

n

Full Scale Adjust Resistor

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Symbol
Icc

Parameter

Min

Average Power Supply Current

Typ

DAC Resolution
DAC Accuracy
Integral Linearity
Differential Linearity
Monotonicity
Zero Offset
Gain Error (Adjustable to Zero)
Differential Accuracy (between
Different Outputs on Same Device)

Vo
IREF

Max
- - 150

--

Units
mA

4

Bits

+%
+'/4

LSB
LSB

-Va
-%

+Va
+%

LSB
LSB

-1

+1

LSB

-%
-'/4
Guaranteed

DAC Output Characteristics
Full Scale Output Current (Green)
Full Scale Output Current (Red, Blue)
Maximum Output Voltage

26.7
19.05
2.0

REFERENCE
Reference Current (at IREF Pin)
Reference Voltage (at IREF Pin)
Voltage Temperature Coefficient
Power Supply Rejection
(VAA = Voo = 5V ±5%)

mA
mA
V
-1.2
1.4

1.0
200
1.0

mA
V
ppml'C
%VREF

INTERSIL S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

4-47

iI\)

......
0

......o

IM2110

!

AC Test Conditions

(\I

Input Pulse Levels .......................... O.4V to 2.4V
Input Rise & Fall Times ................... 5 ns maximum
Input Timing Reference Level ...................... 1.5V

AC CHARACTERISTICS
Symbol

VDD

=

5V +10%
TA
-

=

O'Cto +70'C

Parameter

Min

Typ

Max

Units

tcHCH

Clock Period

38

ns

tCLCH

Clock Width Low

10

ns

tCHCL

Clock Width High

10

ns

Clock Rise & Fall Times

5

ns

tAC

Pixel Address (or OVERLAY,
BLANK, SYNC, BRIGHT) Set-Up Time

10

ns

tCA

Pixel Address (or OVERLAY, BLANK,
SYNC, BRIGHT) Hold Time

10

ns

tCDA

Clock to DAC Output (Note 1)

33

ns

DAC Full Scale Settling Time (Note 2)

15

DAC 10-90% Rise Time (Note 3)

8

ns

DAC Output Glitch Energy

50

pVs

ns

tLL

ALE Width

35

ns

tAL

Address (and CS) to Latch Set-Up Time

15

ns

tLA

Address (and CS) Hold Time after Latch

15

ns

tLW

Latch to WRITE

-10

ns

tww

WRITE Pulse Width

80

ns

tAW

Data to WRITE Set-Up Time

90

ns

tWA

Data Hold Time after WRITE

0

ns

tWL

WRITE to next ALE

20

ns

tLE

ALE to ENABLE

25

ns

tEW, tEE

WRITE Duration

80

ns

tAR

Address Float to READ

10

ns

tRR

READ Pulse Width

130

ns

tRL

READ to next ALE

30

tRD

Valid Data from READ

100

ns

tRF

Data Valid after READ

30

ns

ns

NOTE 1: To O.2V on Red and Blue outputs, to O.4SV on Green output.
2: To within

% LSB of final value.

3: Capacitive load on DAC output of 10pF maximum.

PIN DESCRIPTION
Pin Name

Pin Number

ADO-AD12

1-12

PO-P7

32-39

Description
Microprocessor Address/Data. The 8 bits of RAM address and the 2 bits of overlay address
are latched into the IM211 0 when ALE is High. The 8-bit or 12-bit data is then written into the
RAM and the overlay registers or read from them, depending on the state of WR and RD.
Pixel address. The address on these pins is latched on the first rising edge of the clock and
decoded to select one of 256 colors stored in the color lookup table.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

4-48

IIJD~DI!..

IM2110
PIN DESCRIPTION
Pin Name

(Continued)

Pin Number

Description

CLK

13

Pixel clock. Latches PO-P7, OVO, OV1, HSYNC, VSYNC, BLANK and BRIGHT. Transfers
address information from the input latches to the RAM decoder, and transfers RAM data
from the DAC registers to the DAC inputs. Two clock transitions plus the DAC settling time
are required from data address input to a valid output.

CS

14

Chip select for microprocessor interface (active low). CS is latched on the falling edge of
ALE. When CS is low, the microprocessor port is enabled, and the DAC outputs go to the
reference black level. (However, if the HYSNC, VSYNC or BLANK signals are applied, the
DAC outputs are set to those respective levels).

ALE

15

Address Latch Enable. Latches ADO-AD9 inputs into address registers when High, and the
state of CS into the CS register on the falling edge. Used as the" AS" control with a
Motorola microprocessor.

WR

16

Write. Logic "0" selects Write operation. Used as the "READ/WRITE" pin with a Motorola
microprocessor.

RD

17

Read. Logic "0" selects Read operation onto the microprocessor bus, for manufacturer's
testing purposes only. Used as the "ENABLE" or "DATA STROBE" control with a Motorola
microprocessor.

TEST

18

Test. Logic "0" enables operation in test mode. Used for manufacturer's testing purposes
only. This pin should always be tied to Voo.

19,20

Overlay select. Enable and select one of the three overlay registers for Video Read. When
accessing the overlay registers, PO-P7 are ignored.

OVO,OV1

VSYNC, HSYNC

21,22

OV1

OVO

0
0
1
1

0
1
0
1

Color Table RAM
Overlay Register 1
Overlay Register 2
Overlay Register 3

Green Vertical and Horizontal Sync. These two signals are exclusive-ORed inside the chip,
to produce a composite SYNC signal.
SYNC resets all DAC registers and forces all outputs to OV.
These inputs have priority over data inputs from the RAM and the overlay registers.

BLANK

23

DAC Blanking. Logic "1" resets all DAC registers. Red and Blue outputs fall to OV, Green
output falls to 286 mV (blanking levels). This input has priority over data inputs from the
RAM and the overlay registers.

BRIGHT

24

10% Bright. Logic "0" turns on an additional current source in each DAC. This produces an
overbright pixel when a "White" input (all 1's) is applied to the DAC inputs.

IIREF

26

Reference Current. A resistor is connected from this pin to Ground in order to set a 1 LSB
current. The nominal voltage output at this pin is 1.2V, and the nominal value of the resistor
should be 10500 for a 37.50 output termination.

BIAS

31

Internal current source bias is provided with a temperature compensated reference. This
pin is used for compensating the Bias line. 0.1 ",F and 0.01 ",F capacitors are normally
connected in parallel from this pin to VAA.

R,G,B

29,27,30

Red, Green, and Blue Current Outputs. These analog outputs are intended to drive a
minimum load of 37.50. If terminated with a 750 resistor and a coaxial cable with 750
impedance, reflection is minimized by matched termination of the cable. The full scale
current needed at these outputs is adjusted with the resistor at IREF.

Voo

40

Digital 5V positive supply.

VAA

28

Analog 5V positive supply, providing the high DAC output current. VAA = Voo.

GND

25

Digital and analog ground.

INTERSIL S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values hsvs been chsrsr:terized but ars not tested.

4-49

i

......
o
N

...~

IM2110

!

FUNCTIONAL DESCRIPTION

(II

When writing to the IM2110, the state of CS and the address are latched on the falling edge of ALE. Data is then
transferred when WR is low.
An Intel microprocessor may be used as described
above. A Motorola microprocessor may be used by taking
into account the following pin correspondence (see timing
diagrams, Figure 3 and Figure 4):

Microprocessor Interface
As illustrated in the functional diagram, the IM211 0 has a
256 x 12 RAM and three 12-bit overlay registers. The MPU
bus interface allows the writing of data into the RAM and
the overlay registers, and operates asynchronously with the
video data.
The device can be addressed either through the 12-bit
microprocessor interface for writing data, or through the 8bit video interface for transferring data to the video outputs.
The microprocessor port is selected when Chip Select is
active, and the video port is selected otherwise.
An 8-bit status register must be written to first, after power is applied to the part, in order to set an "8-bit" or a "12bit" mode. Depending on the value stored at bit DO in this
register, data to the RAM and the overlay registers will be
written 8 or 12 bits at a time. See Table for address mapping.
The lowest four data bits (DO-D3) contain the Red intensity information, the next four bits (D4-D7) contain the Blue
intensity information, and the highest four bits (D8-D11)
contain the Green intensity information.

Intel

Motorola

ALE
RD
WR

AS
EorDS
R/W

While the microprocessor port is selected, all the DAC
outputs are set to the reference 'Black' level, unless the
'BLANK', 'VSYNC' or 'HSYNC' signals are applied.
The content of the RAM (but not of the overlay registers)
can be read back onto the AD bus, 12 bits at a time. This
feature is used primarily for testing the part. The timing diagram and the specifications for this Read function are supplied for information purposes only. Note that in this mode
the video clock must be operating at a frequency at least
double that of ALE. (See Figure 5.)

1 - - - - - - tAW - - - - - I

ALE

tWL

r----

~-I---+lI--------\ww -------4-~-_I

WR - - - - - - . . . . .

0082-9

Figure 3: Microprocessor Write Timing (Intel)

x

.x
ADO-AD11

-

ADDRESS
tAL

xxx
DATA

I

tLA

~

tAW

f

AS
tLL

tLW

tww

'\

R/W
tAL

'I

)

tEW

tLE

}-

E,DS

tWL

~
tEE

I

0082-4

Figure 4: Microprocessor Write Timing (Motorola)
lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

~~~~~~~~~J~T~~~~ ~~N~~~L~~~~ ~~~T~~~~ ~;~~ LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
NOTE: All typical values have been characterized but are not tested.

4-50

tIlD~OIL

IM2110
FUNCTIONAL DESCRIPTION

(Continued)

0082-3

Figure 5: Microprocessor Read (Timing Test)

ADDRESS MAP
Table 1
Address
(ADo-ADg)

12-Bit Mode

8-Bit Mode

Location

Data

Location

Data

OOOh
001h
002h
003h

ramO
ram 1
ram 2
ram 3

DO-D11
DO-D11
DO-D11
DO-D11

•
•

•
•

ramO
ram 1
ram 2
ram 3

DO-D7
DO-D7
DO-D7
DO-D7

OFEh
OFFh

•
•

•
•

•
•

ram 254
ram 255

DO-D11
DO-D11

ram 254
ram 255

DO-D7
DO-D7

100h
101h

ramO
ram 1

DO-D11
DO-D11

•
•

ram 0
ram 1

DS-D11
DS-D11

•
•

•
•

•

•

•

•

1FEh
1FFh

ram 254
ram 255

DO-D11
DO-D11

ram 254
ram 255

DS-D11
DS-D11

201h
202h
203h

ovly 1
ovly2
ovly3

DO-D11
DO-D11
DO-D11

ovly 1
ovly2
ovly3

DO-D7
DO-D7
DO-D7

301h
302h
303h

ovly 1
ovly2
ovly 3

DO-D11
DO-D11
DO-D11

ovly 1
ovly2
ovly3

DS-D11
DS-D11
DS-D11

3FFh

status register

DO-D7

status register

DO-D7

other locations

unused

unused

Status register: DO = 1: 12 bit mode. DO = 0: S bit mode. All other bits unused. When an address is loaded, the levels on
AD10-AD11 are indifferent. In the S-bit mode, the data for Do-D7 must be present on ADo-AD7' and the data for Ds-D11 on
ADo-AD3. The levels on the other AD pins are indifferent.

INTERSIL'8 SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AJI typical values have been characterized but are not tested.

4-51

iII)

......
o

...~

IM2110

(II

!

FUNCTIONAL DESCRIPTION

(Continued)

Color lookup Table

Bright, Blank, Sync

As illustrated in Figure 6, 8 bits of lookup table address
and 2 bits of overlay address are latched into the address
registers on the rising edge of the clock. On the following
rising edge, the 12 bits of color information are latched into
the DAC registers, decoded, and used to turn on or off the
DAC current sources. If ova or OV1 is High, the information
in the overlay registers overrides the pixel data on PO- P7.
The overlay registers allow the use of additional bit planes
in the frame buffers and may be controlled by external character, cursor or grid logic.

These inputs are also sampled on the rising edge of the
clock, and internally pipelined to maintain synchronization
with the data (see Table 3).
When BRIGHT is active, the intensity of the color addressed in the RAM or the overlay registers is increased by
a value of 10% of the Reference White level.

CLOCK

R,G,B-------------------------t---'
0082-8

Figure 6: Video Input/Output Timing
Table 2
Green

Red, Blue

(mV)

(rnA)

(mV)

(mA)

Peak White
Reference White

1071
1000

28.56
26.67

785
714

20.93
19.04

Reference Black
Blanking

357
286

9.52
7.62

71
0

1.89
0

0

0

0

0

Synch

PEAK WHITE

REfERENCE WHITE

REfERENCE BLACK

Jl

'\ / \

BLANK

\

1

1

SYNC

0082-6

Figure 7: Video Output Levels
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTc; All typical values have been charactedz9d but are not tested.

4-52

.O~OR.

IM2110

i

......
o
II)

TRUTH TABLE
Table 3. Voltage and Current Output with Standard Setup
(adjusted for Green Reference White level = 1000 mV, 37.50 load on outputs)
BRIGHT

BLANK

HSYNC

VSYNC

OVO

OV1

PO-P7

Data

Level

0
1

0
0

0
0

0
0

0
0

0
0

addr
addr

255
255

peak white
ref white

•
•
•

•
•
•

•
•
•

1

0

0

0

0

0

addr

1
1
1

0
0
0

0
0
0

0
0
0

1
0
1

0
1
1

X
X
X

(ovly1)
(ovly2)
(ovly3)

X
X
X
X

1
X
X
X

0
1
0
1

0
1
1
0

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

ref black

blank
blank
sync
sync

The 12 bits of color information, in combination with the
SYNC, BLANK or BRIGHT selected at the time of address
input, are used to form the composite output current. This
current, through output loads from 37.50 to 750, provides
the 1 Vp-p RS343A output voltage.
An on-chip temperature-compensated reference and external resistor set the full scale output current of all three
DAC's. A current of one LSB (1.143 mA for 37.50 output
load) is sourced from IREF. Varying RSET adjusts the full
scale output and LSB weight.

Voltage Reference
The internal band gap reference provides a temperature
compensated voltage bias to all three DAC's. Full scale out·
put current is set by using the reference and an external
resistor. The reference voltage at IREF divided by the resist·
ance from IREF to GND is equal to a nominal one LSB of
DAC current. An RSET resistor consisting of a 5000 fixed
resistor in series with a 1 kO variable resistor should be
used to adjust the full scale output voltage for a doubly-terminated 750 system. This adjustment eliminates any gain
error and its range is wide enough to guarantee 1V peak-topeak Green output (Sync tip to Reference White level). Selection of RSET for RS343A output is made by using the
equation:
- Vref x R (load)
R
SET 42.86 mV

0

Reference Adjustment Procedure
A Reference White must be present at the DAC outputs.
The RSET resistor at IREF can then be adjusted to precisely
set this output voltage. The following procedure may be
used:
1) Write all 1's to Overlay register 1. The video clock need
not be active.
2) Transfer the data into the DAC registers by moving the
video clock from Low to High at least twice, while maintaining the following levels on the video input pins:
PO-P7
X
OVO
1
OV1
0
BRIGHT
1
0
BLANK
VSYNC
0
HSYNC
0
3) Measure the voltage at the Green output, and adjust the
resistor value at IREF until that voltage is 1.000V.

(42.86 mV = 1 LSB)

With a nominal 1.2V reference voltage, RSET will be
10500 for a 37.50 (doubly terminated) system and 21000
for a 750 system. Matching the temperature coefficients of
RSET and the load resistors will provide a system with an
output voltage temperature coefficient of typically
200 ppml"C.
The internal voltage generated for current source bias is
present at the BIAS pin. 0.1 fLF and 0.01 fLF capacitors are
connected in parallel from BIAS to VAA.

01 A CONVERTERS
Each DAC consists of 15 equal-weight current sources
providing the gray scale output. This configuration guarantees monotonicity, reduces glitch energy, and ensures high
integral and differential linearity. In addition, SETUP and
BRIGHT current sources are included for RS343A output
and cursor display options. The Green DAC has an additional SYNC current source, for RS343A compatibility.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: All typical values have been characterized but are not tested.

4-53

•

......o

IM2110

!

PC BOARD LAYOUT CONSIDERATIONS

&\I

VDD
+SVDC

BIAS
VAA
C3
GND

GROUND
Rl

11.12110

R3
R2

R4
RS

IREF

7S.!l COAX

BLUE
RED
GREEN
0082-7

Figure 8: IM2110 Typical Power Supply and Output Connections
Rt: 500n metal film resistor
R2: 1 kn cermet potentiometer

Cl, C2, C3: 0.1 I'F and O.Ot I'F monolithic ceramic capacitors in parallel
R3, R4, A5: 750 1% metal film resistor

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but ar8 not tested.

4-54

Section 5

Power Supply
Supervisory
ICL7660 ................ 5-1
ICL7660S ............. 5-10
ICL7662 ............... 5-20
ICL7663 ............... 5-28
ICL7663S ............. 5-37
ICL7665 ............... 5-44
ICL7665S ............. 5-53
ICL7667 ............... 5-63
ICL7673 ............... 5-71
ICL7675 ............... 5-79
ICL7676 ............... 5-79
ICL7677 ............... 5-89
ICL7680 .............. 5-101
ICL8211 .............. 5-103
ICL8212 .............. 5-103

~

a:.

D~D162

ICL7660
CMOS Voltage Converter

ell
ell

o

GENERAL DESCRIPTION

FEATURES

The Intersil ICL7660 is a monolithic CMOS power supply
circuit which offers unique performance advantages over
previously available devices, The ICL7660 performs supply
voltage conversion from positive to negative for an input
range of + 1,5V to + 10,OV, resulting in complementary output voltages of -1 ,5V to -10,OV, Only 2 non-critical external capacitors are needed for the charge pump and charge
reservoir functions, The ICL7660 can also be connected to
function as a voltage doubler and will generate output voltages up to + 18,6V with a + 10V input. Note that an additional diode is required for VSUPPLY > 6,5V,
Contained on chip are a series DC power supply regulator, RC oscillator, voltage level translator, and four output
power MOS switches, A unique logic element senses the
most negative voltage in the device and ensures that the
output N-channel switch source-substrate junctions are not
forward biased, This assures latchup free operation,
The oscillator, when unloaded, oscillates at a nominal frequency of 10kHz for an input supply voltage of 5,0 volts.
This frequency can be lowered by the addition of an external capacitor to the "osc" terminal, or the oscillator may
be overdriven by an external clock.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV) operation. At medium to high voltages (+ 3,5 to + 10.0 volts),
the LV pin is left floating to prevent device latchup,
An enhanced direct replacement for this part called
ICL7660S will become available shortly and will be more
appropriate for new designs.

• Simple Conversion of + 5V Logic Supply to ± 5V
Supplies
• Simple Voltage Multiplication (Vour=(-) nVIN)
• 99.9% Typical Open Circuit Voltage Conversion
Efficiency
• 98% Typical Power Efficiency
• Wide Operating Voltage Range 1_5V to 10.0V
• Easy to Use - Requires Only 2 External
Non-Critical Passive Components

APPLICATIONS
• On Board Negative Supply for Dynamic RAMs
• Localized fL-Processor (8080 Type) Negative
Supplies
• Inexpensive Negative Supplies
• Data Acquisition Systems

ORDERING INFORMATION
Part Number

Temp. Range

ICL7660CTV

0' to + 70'C

ICL7660CBA

O'C to +70'C

ICL7660CPA

0' to + 70'C

ICL7660MTV*

-55' to + 125'C

Package
TO-99
8PINSOIC
8 PIN MINI DIP
TO-99

-Add 18838 to part number if 8838 processing is required.

v+ (and CASE)
V+

ose
LV

0319-1

(Outline Dwg BA)
8 LEAD MlnlDIP

0319-2

(Outline Dwg TV)
8 LEAD TO-99

0319-3

(Outline Dwg PAl

Figure 1: Pin Configurations

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

302063-004

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

5-1

•

~

...

ICL7660

CD

..I

!:!

ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
ICL7660M ........................ - 55'C to + 125'C
ICL7660C ............................ O'Cto +70'C
Storage Temperature Range .......... - 65'C to + 150'C
Lead Temperature
(Soldering, 10sec) .............................. 300'C

Supply Voltage ................................. 10.5V
LV and OSC Input Voltage
(Note 1) ............ - 0.3V to (V ± + 0.3V) for V + < 5.5V
(V+ -5.5V)to(V+ +0.3V)forV+>5.5V
Current into LV (Note 1) ............. 20fLA for V+ >3.5V
Output Short Duration (VSUPPLy,;;5.5V) ....... Continuous
Power Dissipation (Note 2)
ICL7660CTV ............................... 500mW
ICL7660CPA ............................... 300mW
ICL7660MTV ............................... 500mW

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

r---------------~----------------r_------_r-----------------------oV+

r----------------------o CAP +
RC
OSCILLATOR

, - - - - - - - - - - 0 CAP-

VOUT

OSC

LV

LOGIC
NETWORK

VOLTAGE
REGULATOR

0319-7

Figure 2: Functional Diagram

OPERATING CHARACTERISTICS

v+ =5V, TA=25'C, Cosc=O, Test Circuit Figure 3 (unless otherwise specified)
Symbol

Parameter

L.imits

Test Conditions
Min

Units

Typ

Max

170

500

1+

Supply Current

RL =

V~,

Supply Voltage Range - Hi
(Dx out of Circuit) (Note 3)

O'C,;;TA,;;70'C, RL = 10kO, LV Open

3.0

6.5

V

-55'C';;TA';;125'C, RL = 10kO, LV Open

3.0

5.0

V

Vt,

Supply Voltage Range - Lo
(Dx out of circuit)

MIN,;;TA,;;MAX, RL =10kn, LV to GROUND

1.5

3.5

V

V~2

Supply Voltage Range - Hi
(Dx in circuit)

MIN,;;TA,;;MAX, RL =10kO, LV Open

3.0

10.0

V

V~

Supply Voltage Range - Lo
(Dx in circuit)

MIN,;;TA,;;MAX, RL = 10kO, LV to GROUND

1.5

3.5

V

00

fLA

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

5-2

ICL7660
OPERATING CHARACTERISTICS
Y+ = 5Y, TA = 25'C, Case = 0, Test Circuit Figure 3 (unless otherwise specified) (Continued)
Symbol

Parameter

Limits

Test Conditions
Min
lOUT = 20mA, T A = 25'C

Max

55

100

0

120

0

+ 70'C
55'C:5: T A:5: + 125'C (Note 3)

IOUT= 20mA, O'C:5:TA:5:

150

0

Y+ =2Y,loUT=3mA, LYto GROUND
O'C:5:TA:5: + 70'C

300

0

Y+ =2Y,loUT=3mA, LY to GROUND,
- 55'C:5: TA:5: + 125'C, Dx in circuit (Note 3)

400

0

lOUT = 20mA, ROUT

Output Source Resistance

Units

Typ

fose

Oscillator Frequency

10

kHz

PEf

Power Efficiency

RL =5kO

95

98

%

YOUTEf

Yoltage Conversion Efficiency

RL =00

97

99.9

%

Zose

Oscillator Impedance

Y+=2Yolts

1.0

MO

Y=5Yolts

100

kO

Notes: 1. Connecting any input terminal to voltages greater than V + or less than GROUND may cause destructive latchup. It is recommended that no inputs from
sources operating from external supplies be applied prior to "power up" of the ICL7660.
2. Derate linearly above 50"C by 5.5mW I'C.
3. ICL7660M only.

TYPICAL PERFORMANCE CHARACTERISTICS
OPERATING VOLTAGE AS A
FUNCTION OF TEMPERATURE

:::- 10K

~A

:::.
w

~

w

~ ~:~I~~~~~~~~

(Circuit of Figure 3)

OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF SUPPLY VOLTAGE

iil ::~~~·!:i~~t~~~~tj
~~5~~~5~O~~~~+~75~~~­

= 1 mA

-- - -

"""~=+2Y

~

.-"

I"--..

~

Y+=5Y

10

o

TEMPERATURE C'C)

lOUT

./

~
£ 100
o

g350

!25,b=

..~1000

~ 5.01r--r~--+--+--+--+~

OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF TEMPERATURE

1

4

7

SUPPLY VOLTAGE (y+)

0319-8

0319-10

0319-9

INTERS1L'S SOLE AND EXCLUSIVE WARAANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTc: All typical values have been characterized but are not tested.

5-3

o

CD
CD

ICL7660

....

g TYPICAL PERFORMANCE CHARACTERISTICS
POWER CONVERSION EFFICIENCY
AS A FUNCTION OF OSC.
FREQUENCY

l'OO T -+25·V. I

I.. :
~

louT-15mA

~ ~

~
~

-

1\

~

8

O
..

?i

i"-o

I
I

90

V+

82
80
100

"

"a

..
~ '8

SV

lK
FREQUENCY lose (Hz)

10

10K

100
1000
Cose (pI)

v· = +5V

~ 2

o

-1

-4

"

. /I ' SLOPE 550

~o

60

ro ~ ~ ~ ~ 90

ro

\

40 '+

30~

/

TA""+25°C- 20 ~
= +5V
10 ~

y+

1,-

10
20
30
40
50
lOAD CURRENT IL (rnA)

90

~

m
50 ~

,/

,/

60

o

0 +25 +50 +75 +100 +125
TEMPERATURE ('C)

0319-14

TA

~ +2$'C

V+=2V

\

\

..1+1

~
g

\

~

\

)
./

0_1

~

0319-15

LOAD CURRENT !L(mA)

+2

..

70 "

1/

/
".

-25

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

80 !(

7

/

I-

~

r-....

6

~o

0319-13

90·~

r

~

0

II

"o -2
-3

l3

100 ..

"""'

I:

1

> 0

..........

0319-12

:

r-- iA = J25·b

10K

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT
5

y+ = +5V

u

0319-11

!:i

""

~ 12

~AIII+2n

+=+SV

osc.

.

18

~ 6~
M14
> 1

0

84

4

UNLOADED OSCILLATOR
FREQUENCY
AS A FUNCTION OF TEMPERATURE
"N 20

I

lOUT = 1 mA

92

(Circuit of Figure 3) (Continued)

FREQUENCY OF OSCILLATION AS
A FUNCTION OF EXTERNAL
OSC. CAPACITANCE

~
-2 .L'

V ...... lOPEI'~{

0123456
LOAD CURRENT IL (mA)
0319-16

SUPPLY CURRENT & POWER CONVERSION EFFICIENCY
AS A FUNCTION OF LOAD CURRENT

NOTE 4. These curves include in the supply current that current fed directly
into the load RL from Y+ (see Figure 3). Thus, approximately half the supply

20.0

~

li
~

90

8.0

'tI

through tile ICL7660, to the negative side of the load. Ideally, YOUT '" 2 YIN,

8

6.0

§

7

4.0

Is '" 2 IL, so YIN • Is '" YOUT· IL·

$

g

6

2.0

ll00

~50

.!
I

ao -

~

3

6.0

(J

2

4.0

1°0

o

~

o.o~

...
~ 40

..5

current goes directly to the positive side of the load, and the other half,

~

2.0

....

~

OmA
1.5
3.0
4.5
6.0
7.5
LOAD CURRENT IL (mAl

9.0

0319-17

INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHAll BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHAll BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vs/uss have been characterized but are not tested

5-4

ICL7660
IS v+
t------_--<--o(+5V)

------,

I,

I

:
I
I

-

I
I

RL

·casel
Dx

:::;::

,,-l4-,, '"

~VOUT
0319-19

Figure 4: Idealized Negative Voltage Converter

0319-18
NOTES: 1. For large values of Cosc (> 1000pF) the values of C,
and C2 should be Increased to 100f'F.
2. Dx is required for supply voltages greater than 6.SV @
-SS"C<:TA<:+7Il"C; refer to performance curves for

THEORETICAL POWER EFFICIENCY
CONSIDERATIONS

additional in1ormation.

In theory a voltage converter can approach 100% efficiency if certain conditions are met:
A
The drive circuitry consumes minimal power.
S
The output switches have extremely low ON resistance and virtually no offset.
C
The impedances of the pump and reservoir capacitors are negligible at the pump frequency.
The ICL7660 approaches these conditions for negative
voltage conversion if large values of C1 and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E=YzC1 (V12-V22)
where V1 and V2 are the voltages on C1 during the pump
and transfer cycles. If the impedances of C1 and C2 are
relatively high at the pump frequency (refer to Figure 4)
compared to the value of RL, there will be a substantial
difference in the voltages V1 and V2. Therefore it is not only
desirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly
large value for C1 in order to achieve maximum efficiency of
operation.

Figure 3: ICL7660 Test Circuit

DETAILED DESCRIPTION
The ICL7660 contains all the necessary circuitry to complete a negative voltage converter, with the exception of 2
external capacitors which may be inexpensive 10!£F polarized electrolytic types. The mode of operation of the device
may be best understood by considering Figure 4, which
shows an idealized negative voltage converter. Capacitor
C1 is charged to a voltage, V +, for the half cycle when
switches 51 and 53 are closed. (Note: 5witches 52 and 54
are open during this half cycle.) During the second half cycle of operation, switches 52 and 54 are closed, with 51 and
53 open, thereby shifting capacitor C1 negatively by V +
volts. Charge is then transferred from C1 to C2 such that the
voltage on C2 is exactly V+, assuming ideal switches and
no load on C2. The ICL7660 approaches this ideal situation
more closely than existing non-mechanical circuits.
In the ICL7660, the 4 switches of Figure 4 are M05 power switches; 51 is a P-channel device and 52, 53 & 54 are
N-channel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of 53 & 54
must always remain reverse biased with respect to their
sources, but not so much as to degrade their "ON" resistances. In addition, at circuit startup, and under output short
circuit conditions (VOUT=V+), the output voltage must be
sensed and the substrate bias adjusted accordingly. Failure
to accomplish this would result in high power losses and
probable device latchup.
This problem is eliminated in the ICL7660 by a logic network which senses the output voltage (VOUT) together with
the level translators, and switches the substrates of 53 & 54
to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7660 is an integral
part of the anti-Iatchup circuitry, however its inherent voltage drop can degrade operation at low voltages. Therefore,
to improve low voltage operation the "LV" pin should be
connected to GROUND, disabling the regulator. For supply
voltages greater than 3.5 volts the LV terminal must be left
open to insure latchup proof operation, and prevent device
damage.

DO'S AND DON'TS
1.
2.
3.

4.

5.
6.

Do not exceed maximum supply voltages.
Do not connect LV terminal to GROUND for supply
voltages greater than 3.5 volts.
Do not short circuit the output to V + supply for supply voltages above 5.5 volts for extended periods,
however, transient conditions including startup are
okay.
When using polarized capacitors, the + terminal of
C1 must be connected to pin 2 of the ICL7660 and
the + terminal of C2 must be connected to
GROUND.
Add diode Dx as shown in Figure 3 for high-voltage,
elevated temperature applications.
Add capacitor (- 0.1 !£F, disc) from pin 8 to ground
to limit rate of rise of input voltage to approximately
2V/!£s.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILrTY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typIcsl valUfJB hsvs b68n chat'llC'ltHiz6d but Nfl not tnttld.

5-5

~
~

ICL7660

...!=!....

'NOTE: 1. YOUT = -l(+ FOR
1.5Y:5 Y+:5 8.5V
2. YOUT = -(v+-Y,ox)
FOR 8.5 :5 v+ :5 10.0V

>---01,---.. . .

0 VOUT'

i10~F

0319-20

Figure 5: Simple Negative Converter

RL

0319-21

Figure 6: Paralleling Devices

V+

Ox

r-M-...,
h--<>VOUT'

L __ .J

.1. .• ~

X10~F

·NOTE· 1. VOUT = -nV+ FOR
-=+
1.5Y :5 V+ :5 8.5V
2. Your = -n(Y+-Wox) FOR
6.SV:5 V+ :5 10.0Y
0319-22

Figure 7: Cascading Devices for Increased Output Voltage

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

5-6

IIU~UI!:.

ICL7660
CONSIDERATIONS FOR HIGH
VOLTAGE & ELEVATED
TEMPERATURE

where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approx·
imately the weighted sum of the individual ICl7660 ROUT
values.

The ICl7660 will operate efficiently over its specified tem·
perature range with only 2 external passive components
(storage & pump capacitors), provided the operating supply
voltage does not exceed 6.5 volts at + 70°C and 5.0 volts at
+ 125°C. Exceeding these maximums at the temperatures
indicated may result in destructive latchup of the ICl7660.
(Ref: Graph "Operating Voltage Vs. Temperature")
Operation at supply voltages of up to 10.0 volts over the
full temperature range without danger of latchup can be
achieved by adding a general purpose diode in series with
the ICl7660 output, as shown by "Ox" in the circuit dia·
grams. The effect of this diode on overall circuit perform·
ance is the reduction of output voltage by one diode drop
(approximately 0.6 volts).

Changing the ICL7660 Oscillator
Frequency

~-I"---- 2000V
• Improved SCR Latchup Protection
• Simple Conversion of + SV Logic Supply to ± SV
Supplies
• Simple Voltage Multiplication VOUT=(-)nVIN
• Easy to Use-Requires Only 2 External
Non-Critical Passive Components
• Improved Direct Replacement for Industry-Standard
ICL7660 and Other Second-Source Devices

APPLICATIONS
• Simple Conversion of + SV to ± SV Supplies
• Voltage Multiplication VOUT = ±nVIN
• Negative Supplies for Data Acquisition Systems &
Instrumentation
• RS232 Power Supplies
• Supply Splitter, VOUT = ±Vs/2

ORDERING INFORMATION
Part Number

Temp. Range

Package

ICL766DSCBA

O'C to + 7D'C

8-PinSOIC

ICL766DSCPA

D'C to +70'C

8-Pin Minidip

ICL766DSIBA

D'C to +7D'C

8-PinSOIC

ICL7660SCTV

D'C to + 70'C

TO-99

ICL7660SIPA

- 25'C to + 85'C

8-Pin Minidip

ICL7660SITV

- 25'C to + 85'C

TO-99

ICL7660SMTV'

-55'C to + 125'C

TO-99

• Add 18838 to part number if 8838 processing is required.

0088-1

(BA)

0088-2

(TV)

0088-3

(PA)

Figure 1: Pin Configurations

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

302163-002

NOTE: All typical values have been characterized but are not tested

5-10

IfID~DIL

ICL7660S

NOTE: Stresses above thoss Hsted undBr "Absoluts Maximum Ratings"
may CBusa permanent dBfT18{J6 to the device. Thsss IU9 s/r9ss ratings only
and functionsl operation of the device at th9ss or any other oonditions
above thoss indicated in the operationsl sections of the specifications is not
Imp/ted. Exposure to sbsoIul9 maximum rating conditions for _ _ periods may affect device f9!lsbl1lty.

ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................. 13.0V
LV and OSC Input Voltage
(Note 1) .......... -0.3Vto(V+ + 0.3V)forV+<5.5V
............ (V+ - 5.5V)to(V+ + 0.3V) forV+ >5.5V
CurrentintoLV(Notel) ............. 20p.AforV+ > 3.5V
Output Short Duration (VSUPPLY ,;; 5.5V) ....... Continuous
Power Dissipation (Note 2)
ICL7660SCTV ..........••...•....•.....•...• 500 mW
ICL7660SCPA .............................. 300 mW
ICL7660SCBA .•.••.....•..............•.... 300 mW
ICL7660SITV ............................... 500 mW
ICL7660SIPA ............................... 300 mW
ICL7660SIBA ............................... 300 mW
ICL7660SMTV .............................. 500 mW
Operating Temperature Range
ICL7660SM ........................ - 55·C to + 125·C
ICL7660SI .......................... -25·C to +85·C
ICL7660SC ............................ OOC to + 70·C
Storage Temperature Range ........... - 65·C to + 1500C
Lead Temperature
(Soldering, 10 sec) ............................. 300·C

BOOST

r---------O CAp•
r------OCAP-

VOUT

0088-4

Figure 2: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANlY ARTICLE OF THE CONDITION OF SALE.
THE WARRANlY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILllY AND FITNESS FOR A PARTICULAR USE.

5-11

CII
CII

a

•

~--------~----~~~---.--------------o~

NOTE: AN typical vsIues haIlS bHn charsctsrfzed but IUfJ not tested.

P
...

ICL7660S
~
U)
U)

.......

ELECTRICAL CHARACTERISTICS

g v+

= 5V, TA = 25'C, OSC = Free running, Test Circuit Figure 3 (unless otherwise specified)

Symbol

Parameter

Limits

Test Conditions
Min

1+

Units

Typ

Max

80

160
180
180
200

p.A

Supply Current
(Note 3)

RL =

V~

Supply Voltage Range-HI
(Note 4)

RL =10K, LV Open
Tmin

"'0
"'0:

90
88

""

86

0:

84

3
...J

82

U

80
100

Vl

0

1k

50k

10k

10
8

7

IIII III

\

UNLOADED OSCILLATOR
FREQUENCY
AS A FUNCTION OF TEMPERATURE

'N'

20

'"en
U

18

""t;

16

\

...::>

14

\

e:

12

:I:

V+=5V II
TA= 25°C

0

z

5
4

3
2
1
0
1

8
0:

3

'\

...J

U

Vl

0

10

100

1K

\

/~V+=10V

'" "<

,V+= 5V

~

10

/-----

r--z

8
-50 -25

0

25

------

50

-----

-

75 100 125

TEMPERATURE (OC)

OSC FREQUENCY FOS C(Hz)
0088-9

0088-8

0088-10

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: All typical values hav6 been characterized but ar6 not tested

5-13

•

! ICL7660S

.D~DlL

co
co

!:i

TYPICAL PERFORMANCE CHARACTERISTICS

S:!

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

£
!oJ

r-....

0

"

-1

0

-2

>

...::>
::>
0

-3

-5

/""

.,..
./

-4

o

/

V
/

10

20

T.= 2500

1/

V·=5
TA= 250 C

~=5V

-

/
10

40

30

20

30

40

50

70
60
50
40
30
20
1o

60

~=2V
TA = 2500

E:...

1

80

~
~

II-

1/

[>0..,.

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

100
90

~

;5
...J

(Circuit of Figure 3) (Continued)

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

1

'">!

~

...J

o

g

'"'"
II

l-

::>

.

i!:
::>

~

1

0

::>

~~

III

-2

o

o

./

)

2 3 4 5 6 7 8 9
LOAD CURRENT(mA)

LOAD CURRENT(mA)-

LOAD CURRENT (mA) -

~

....
~

0088-13

0088-12

0088-11

OUTPUT SOURCE RESISTANCE
AS A FUNCTION OF
OSCILLATOR FREQUENCY

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

g

100

~

90

~

80

~

t:;
z
o

iii

~

..........
'I-.

70
60
50

-

~
V·=2V
TA=250 C

40

.....
/

16.0
14.0

~

><...

12.0
10.0

.......

8.0

/

30
20

6.0
4.0

/

10

o/
o

1:
...z
'"::>'"u

3

4.5

6

7.5

z

300

~

..

'"::>

~

i!:
::>

::>

III

';2.OC

T. -5V

1\ 1=1

10mA

II

~:I=~~j~~

!U~2= ~oIJF

C

200

I-

1'\

'\

100

i\

0

2.0
0

1.5

400

...u

I-

~

s:","

o Cl =~=100J.&f'
100

9

lK

10K

lOOK

OSCILLATOR fREQUENCY (Hz)

LOAD cURRENT(mA)

0088-15

0088-14

NOTE 4: These curves include in the supply current that current fed directly into the load RL from V + (see Figure 3). Thus, approximately half the supply current
goes directly to the positive side of the load, and the other half, through the ICL7660S, to the negative side of the load. Ideally, VOUT '" 2 Y,N, Is '" 21lo
so Y,N • Is '" VOUT· 'L.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been chsracterizsd but 819 not tssted.

5-14

ICL7660S
IS

y+

181-----_-+-o (+5V)

0088-16

NOTE 1: For large values of COSC (> 1000pF) the values of Cl and
C2 should be increased to 100f'F.

0088-17

Figure 4: Idealized Negative Voltage Converter

Figure 3: ICL7660S Test Circuit

THEORETICAL POWER EFFICIENCY
CONSIDERATIONS

DETAILED DESCRIPTION
The ICl76608 contains all the necessary circuitry to complete a negative voltage converter, with the exception of 2
external capacitors which may be inexpensive 10"F polarized electrolytic types. The mode of operation of the device
may be best understood by considering Figure 4, which
shows an idealized negative voltage converter. Capacitor
C1 is charged to a voltage, V+, for the half cycle when
switches 81 and 83 are closed. (Note: 8witches 82 and 84
are open during this half cycle.) During the second half cycle of operation, switches 82 and 84 are closed, with 81 and
83 open, thereby shifting capacitor C1 negatively by V+
volts. Charge is then transferred from Cl to C2 such that the
voltage on C2 is exactly V + , assuming ideal switches and
no load on C2. The ICl76608 approaches this ideal situation more closely than existing non-mechanical circuits.
In the ICl76608, the 4 switches of Figure 4 are M08
power switches; 81 is a P-channel device and 82, 83 & 84
are N-channel devices. The main difficulty with this approach is that in integrating the switches, the substrates of
83 & 84 must always remain reverse biased with respect to
their sources, but not so much as to degrade their "ON"
resistances. In addition, at circuit startup, and under output
short circuit conditions (VOUT=V+), the output voltage
must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power
losses and probable device latchup.
This problem is eliminated in the ICl76608 by a logic network which senses the output voltage (VOUT) together with
the level translators, and switches the substrates of 83 & 84
to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICl76608 is an integral part of the anti-Iatchup circuitry, however its inherent
voltage drop can degrade operation at low voltages. Therefore, to improve low voltage operation the "lV" pin should
be connected to GROUND, disabling the regulator. For supply voltages greater than 3.5 volts the lV terminal must be
left open to insure latchup proof operation, and prevent device damage.

In theory a voltage converter can approach 100% efficiency if certain conditions are met:
A
The drive circuitry consumes minimal power.
S
The output switches have extremely low ON resistance and virtually no offset.
C
The impedances of the pump and reservoir capacitors are negligible at the pump frequency.
The ICl76608 approaches these conditions for negative
voltage conversion if large values of C1 and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E= % C1 (V12-V22)
where V1 and V2 are the voltages on C1 during the pump
and transfer cycles. If the impedances of C1 and C2 are
relatively high at the pump frequency (refer to Figure 4)
compared to the value of RL, there will be a substantial
difference in the voltages V1 and V2. Therefore it is not only
deSirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly
large value for C1 in order to achieve maximum efficiency of
operation.

DO'S AND DON'TS
1. Do not exceed maximum supply voltages.
2. Do not connect lV terminal to GROUND for supply voltages greater than 3.5 volts.
3. Do not short circuit the output to V+ supply for supply
voltages above 5.5 volts for extended periods, however,
transient conditions including startup are okay.
4. When using polarized capacitors, the + terminal of C1
must be connected to pin 2 of the ICl76608 and the +
terminal of C2 must be connected to GROUND.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABiLiTY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

5-15

!o

ICL7660S

o

....

..I

g

1.-_...._-0 VOUT'

.:c1 0 J.LF
0088-18

'NOTE 1: VOUT

=

-V+ for 1.SV'; V+ ,; 12V.

Figure 5: Simple Negative Converter

0088-19

Figure 6: Paralleling Devices

0088-20

'NOTE 1: VOUT = -nV+ for 1.SV ,; V+ ,; 12V.

Figure 7: Cascading Devices for Increased Output Voltage

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTe: All typical values have been characterized but are not tested.

5-16

tI1D~DI!:. C;

ICL7660S

I'"

....

Increasing the oscillator frequency can also be achieved
by overdriving the oscillator from an external clock, as
shown in Figure 8. In order to prevent device latchup, a
100 kO resistor must be used in series with the clock output. In a situation where the designer has generated the
external clock frequency using TTL logic, the addition of a
10 kO pullup resistor to V + supply is required. Note that the
pump frequency with external clocking, as with internal
clocking, will be % of the clock frequency. Output transitions occur on the positive-going edge of the clock.

TYPICAL APPLICATIONS
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660S for generation of negative supply voltages. Figure
5 shows typical connections to provide a negative supply
where a positive supply of + 1.5V to + 12V is available.
Keep in mind that pin 6 (LV) is tied to the supply negative
(GND) for supply voltages below 3.5 volts.
The output characteristics of the circuit in Figure 5 are
those of a nearly ideal voltage source in series with 55
ohms. Thus for a load current of -10mA and a supply voltage of + 5 volts, the output voltage will be -4.3 volts. The
dynamic output impedance due to the capacitor impedances is approximately 1/CIlC, where:
C=Cl=C2

CMOS

GATE

.
.
1
1
which gives -C =
f
5 '" 3 ohms
CIl
21T PUMpX10for C= 10",F and fpUMP=5kHz

~S~---'----~OVOUT

(% of oscillator frequency)

: [ ,10 .u F

Paralleling Devices
Any number of ICL7660S voltage converters may be paralleled to reduce output resistance. The reservoir capacitor,
C2, serves all devices while each device requires its own
pump capacitor, Cl' The resultant output resistance would
be approximately:

0088-21

Figure 8: External Clocking
It is also possible to increase the conversion efficiency of
the ICL7660S at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 9. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (Cl) and reservoir (C2) capacitors; this is overcome
by increasing the values of Cl and C2 by the same factor
that the frequency has been reduced. For example, the addition of a 1OOpF capacitor between pin 7 (Osc) and V + will
lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and thereby necessitate
a corresponding increase in the value of Cl and C2 (from
10",F to 100",F).

R
= ROUT (of ICL7660S)
OUT n (number of devices)

Cascading Devices
The ICL7660S may be cascaded as shown to produce
larger negative multiplication of the initial supply voltage.
However, due to the finite efficiency of each device, the
practical limit is 10 devices for light loads. The output voltage is defined by:
VOUT= -n (VIN),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7660S ROUT
values.

Cosc

Changing the ICL7660S Oscillator
Frequency
It may be desirable in some applications, due to noise or
other considerations, to alter the oscillator frequency. This
can be achieved simply by one of several methods described below.
By connecting the Boost Pin (Pin 1) to V + , the oscillator
charge and discharge current is increased and, hence, the
oscillator frequency is increased by approximately 3%
times. The result is a decrease in the output impedance and
ripple. This is of major importance for surface-mount applications where capacitor size and cost are critical. Smaller
capacitors, e.g. 0.1 ",F, can be used in conjunction with the
Boost Pin in order to achieve similar output currents compared to the device free running with Cl = C2 = 10 ",F or
100 ",F. (Refer to graph of Output Source Resistance as a
Function of Oscillator Frequency).

sl--1I---oVOUT

0088-22

Figure 9: Lowering Oscillator Frequency

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical valut:Js have been characterized but are not test6(/.

5-17

GI
GI

~

~

cg
cg

.D~DI!..

ICL7660S

...S!....
Vour =
2V+- 2V F

.-+--......--oVOUT =-VIN

0088-23

NOTE: D1 & D2 can be any suHable diode.

0088-24

Figure 10: Positive Voltage Doubler

Figure 11: Combined Negative Voltage
Converter and Positive Doubler

Positive Voltage Doubling

Voltage Splitting

The ICL7660S may be employed to achieve positive voltage doubling using the circuit shown in Figure 10. In this
application, the pump inverter switches of the ICL7660S are
used to charge C1 to a voltage level of V+ -VF (where V+
is the supply voltage and VF is the forward voltage drop of
diode 01). On the transfer cycle, the voltage on C1 plus the
supply voltage (V+) is applied through diode 02 to capacitor C2. The voltage thus created on C2 becomes
(2V+)-(2VF) or twice the supply voltage minus the combined forward voltage drops of diodes 01 and 02.
The source impedance of the output (VOUT) will depend
on the output current, but for V + = 5 volts and an output
current of 10mA it will be approximately 60 ohms.

The bidirectional characteristics can also be used to split
a higher supply in half, as shown in Figure 12. The combined load will be evenly shared between the two sides, and
a high value resistor to the LV pin ensures start-up. Because the switches share the load in parallel, the output
impedance is much lower than in the standard circuits, and
higher currents can be drawn from the device. By using this
circuit, and then the circuit of Figure 7, + 15V can be converted (via +7.5, and -7.5) to a nominal -15V, although
with rather high series output resistance (- 250.0.).

,-~~------"""--------'-V+

Combined Negative Voltage Conversion
and Positive Supply Doubling
Figure 11 combines the functions shown in Figures 5 and
10 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for
example, suitable for generating +9 volts and -5 volts
from an existing + 5 volt supply. In this instance capacitors
C1 and C3 perform the pump and reservoir functions respectively for the generation of the negative voltage, while
capacitors C2 and C4 are pump and reservoir respectively
for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will
be somewhat higher due to the finite impedance of the
common charge pump driver at pin 2 of the device.

v+-v-

+

VOUT = - -

2

50}'F

~~~----------+-------------4-~
0088-25

Figure 12: Splitting A Supply In Half

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicIJ/ values havtllHKm chsractsriz9d but BM not ffttsd.

5-18

ICL7660S
date the 7660S, while maintaining adequate feedback. An
increase in pump and storage capacitors is desirable, and
the values shown provides an output impedance of less
than 50. to a load of 10mA.

Regulated Negative Voltage Supply
In some cases, the output impedance of the ICL7660S
can be a problem, particularly if the load current varies substantially. The circuit of Figure 13 can be used to overcome
this by controlling the input voltage, via an ICL7611 lowpower CMOS op amp, in such a way as to maintain a nearly
constant output voltage. Direct feedback is inadvisable,
since the ICL7660S's output does not respond instantaneously to change in input, but only after the switching delay. The circuit shown supplies enough delay to accommo+BV

OTHER APPLICATIONS
Further information on the operation and use of the
ICL7660S may be found in A051 "Principals and Applications of the ICL7660 CMOS Voltage Converter".

50k

56k
50k

+
lOOk

VOUT

BOOk

250k
VOLTAGE
ADJUST

•

0088-26

Figure 13: Regulating the Output Voltage

+5V LOGIC SUPPLY

12
TTL DATA
INPUT

11

16
",-+~-oRS232 DATA

OUTPUT

+5V n
- 5V I

n

L-...J L..
0088-27

Figure 14: RS232 Levels From A Single 5V Supply

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGAnON WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical valUflS have been charscftHlz8d but are not t9sted.

5-19

:ICL7662

~ CMOS Voltage Converter
~ GENERAL DESCRIPTION

FEATURES

The Intersil ICL7662 is a monolithic high-voltage CMOS
power supply circuit which offers unique performance advantages over previously available devices. The ICL7662
performs supply voltage conversion from positive to negative for an input range of + 4.5V to + 20.0V, resulting in
complementary output voltages of -4.5V to -20V. Only 2
non-critical external capacitors are needed for the charge
pump and charge reservoir functions. The ICL7662 can also
function as a voltage doubler, and will generate output voltages up to + 38.6V with a + 20V input.
Contained on chip are a series DC power supply regulator, RC oscillator, voltage level translator, four output power
MOS switches. A unique logic element senses the most
negative voltage in the device and ensures that the output
N-channel switch source-substrate junctions are not forward biased. This assures latchup free operation.
The oscillator, when unloaded, oscillates at a nominal frequency of 10kHz for an input supply voltage of 15.0 volts.
This frequency can be lowered by the addition of an external capacitor to the "OSC" terminal, or the oscillator may
be overdriven by an external clock.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV) operation. At medium to high voltages (+10 to +20Vl, the LV
pin is left floating to prevent device latchup.

• No External Diode Needed OVer Entire Temperature
Range
• Pin Compatible With ICL7660
• Simple Conversion of + 15V Supply to -15V Supply
• Simple Voltage Multiplication (VOUT=(-) nVIN)
• 99.9% Typical Open Circuit Voltage Conversion
Efficiency
• 96% Typical Power Efficiency
• Wide Operating Voltage Range 4.5V to 20_0V
• Easy to Use - Requires Only 2 External Non-Crltlcal
Passive Components

APPLICATIONS
• On Board Negative Supply for Dynamic RAMs
• Localized ",-Processor (8080 Type) Negative
Supplies
• Inexpensive Negative Supplies
• Data Acquisition Systems
• Up to - 20V for Op Amps

v+

ORDERING INFORMATION
Part Number

GROUND

Temperature Range

Package

ICL7662CTV

O·Cto +70·C

TO-99

ICL7662CPA

O·Cto +70"C

8 PIN MINI DIP

ICL7662MTV*

-55·Cto + 125·C

0320-1

(outline dwg PAl
0320-2

TO-99

(outline dwg TV)

Figure 1: Pin Configurations

• Add 1883B 10 Part Number for 883B Processing.

r-----------~------------~------_r----------------__ov+

..----------------0 CAP +
, - - - - - - - . g CAP-

vour

0320-3

Figure 2: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE ODNDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
302064-004
NOTE: AU typical vsIues havs bHn chsracterlZBd but BffI not testBd.

5-20

ICL7662
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................... 22V
Oscillator Input Voltage (Note 1) ....................... .
-0.3V to (V+ +0.3V) forV+ <10V
(V+ -10V) to (V+ +0.3V) forV+ >10V
Current into LV (Note 1) .............. 20fLA for V+ > 10V
Output Short Duration ...................... Continuous

Power Dissipation (Note 2)
ICL7662CTY ............................... 500mW
ICL7662CPA ............................... 300mW
ICL7662MTY ............................... 500mW
Lead Temperature (Soldering, 1Osee) ............. 300'C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

v+ = 15V, TA = 25'C, Cosc = 0, unless otherwise stated. Test Circuit

Figure 3.
Symbol

Parameter

Limits

Test Conditions
Min

Typ

Units
Max

V+L
V+H

Supply Voltage Range-Lo
Supply Voltage Range-Hi

RL = 10kn, LV=GND
RL = 10kn, LV=Open

Min
0

./
V

.....-

-- -- --

V

70
60

5.
-55

+25

-20

'R" 11

l:

~

Z
UI
:>

9
•

lil

7

~

5

5

a
fl

/

65

/

V

/

I
II

3

4

350

300

25.

0

c

....
....

."

C

200

,J R,

150

'"~
~

Z
0
m

~

50

,K

Fosc(Hz)

,.K

100K

FREQUENCY OF OSCILLATION
AS A FUNCTION OF EXTERNAL
OSC. CAPACITANCE

10K

---

V+ - 15V

N'

TA = +25 ·C

:5-

RL =

>
z

(J

'LV= OPEN

00

I

w lK
:::>
aw

II:
LL

II:

0

~

2
2

0320-5

0320-7

V
1

9 10 11 12 13 14 15 16 17 18 19 20

0320-6

/

3

8

100

100

V

4

7

+12S

+7.

LV = GND /

6

""-

17

/

Ii: •

5

V+ = S~~
I = 3MA
fA
~2S0C

OSCILLATOR FREQUENCY
vs SUPPLY VOLTAGE
RL = 00
Cosc = 0
TA = +2SoC

4

EFII

-V+ = SV
IL = 3mA

TEMPERATURE (Oc)

.. ,.

3

P

-

./

80

2

POWER CONVERSION EFFICIENCY
AND OUTPUT SOURCE RESISTANCE
AS A FUNCTION OF OSCILLATOR
FREQUENCY

./

110

OO

1

i

./

130

100

100

/V+ = 1SV I---IL = 20mA -

./

- +-

IJ

V+ (VOLTS)

/'

18.
17.
(J

o

0320-4

OUTPUT SOURCE RESISTANCE AS
A FUNCTION OF TEMPERATURE

§

r;;:
LV = OPEN

40

10 11 12 13 14 15 16 17 18 19 00

160

I'.:

70

30

1

r-....

90

eo

50

LV = OPEN

40

LV = ~~D

11.

60

t-i-

)

,. o

100

S
0

T"'::-"

130

12.

t-

\

140

j!!

:::l
0-

~

1\

150

II:

~

1\

11.

lTA = +2soclCosc = 0
I-

17.

\

~140
W 130

Z

~:lm1'

160

180

17.

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

~

100

--'

(j

SUPPLY VOLTAGE (V)

f:l

0320-8

10

1

10

100

Cosc(pF)

1000

10K

0320-9

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHEA WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

5-22

ICL7662
TYPICAL PERFORMANCE CHARACTERISTICS
UNLOADED OSCILLATOR FREQUENCY
AS A FUNCTION OF TEMPERATURE

15K

." 14K

;;
~

12K

15::>
fir
II:

10K

II:

'K

~

BK

"0

~0

"-

13K

11K

<:.
...........
............

7K

............

BK
5K
--20

-55

en

ot:i
...........

+25

~

TEMPERATURE ('C)

--

-4

-5

-7

-8

>

-10

-

......

-9

.....

-11

....
S
-12

I-""

..... 1-""

....

....

-13
-14

0320-10

--

-6

~

~

I I
V+ = 15V
TA = +25°C
LV = OPEN

-3

W

6

+125

+70

OUTPUT VOLTAGE AS A
FUNCTION OF LOAD CURRENT

-1

V+ = 15V
COSC = 0

'" "

(See Test Circuit of Figure 3) (Continued)

SLOPE = 650

~

-15

10

20

30

40

50

60

70

80

90

100

LOAD CURRENT IL (mA)
0320-11

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

OUTPUT VOLTAGE AS A
FUNCTION OF LOAD CURRENT

I

100

I
C- V+ 1=1 15V

t

c- TA = +25°C
- LV = GND

~
~

~

~

g

....::>
I!:::>
0

-1

.....

-3

......

"""I-""

"""SLOPE

-4

1

2

= 1400

I

.... 103

4

5

6

7

8

"

i

85

W

""

I I

9 10 11 12 13 14 15 16 17 18 19 00

i'

!!!

~

I"

-2

-5

V+ = 5V
TA = +25°C c-

z

w

CI

r-...

os



~

20

FosclKHZ)

V+ = 15V eTA = +25°Cc-

.....

g
ill

24

LOAD CURRENT IL (mA)

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

I'

!(

38
2

......

0320-12

r.::..

o ~

1

LOAD CURRENT "(mA)

lDO

4

32

L.-'

80

8

L.-'

V

V

./

LV = OPEN_r-

V
/

lDO

LOAD CURRENT IL (rnA)
1

0320-14

2

3

4

5

6

7

8

9 10 11 12 13 14 15 18 17 18 19 20

v+

(VOLTS)

0320-15
INTERSIL'S SOLE AND EXCLUSIVE WARAANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

5-23

: ICL7662

......

II)

This problem is eliminated in the ICL7662 by a logic net~
work which senses the output voltage (VOUT) together with
the level translators, and switches the substrates of 83 & 84
to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7662 is an integral
part of the anti-Iatchup circuitry, however its inherent voltage drop can degrade operation at low voltages. Therefore,
to improve low voltage operation the "LV" pin should be
connected to GROUND, disabling the regulator. For supply
voltages greater than 11 volts the LV terminal must be left
open to insure latchup proof operation, and prevent device
damage.

TYPICAL PERFORMANCE
~ CHARACTERISTICS
(See Test Circuit of Figure 3) (Continued)

150

130

-v+
~ W
-RL =

120

- TA = +25OC

140

1.

'+

SUPPLY CURRENT AS A FUNCTION OF
OSCILLATOR FREQUENCY
II

00

i ::..

!

G

~

so
70

LOAD CURRENT IL (mAl

!!; so
11)

..

IS

50

V+

rat-------,......c-o(+ 5V

V

30

20
10
10

100

1K

10K

Gl

OSCILLATOR FREQUENCY

0320-16

·Cosc i

?

NOTE 4.

Note that these curves include in the supply current that current fed directly
into the load RL from V+ (see Figure 3). Thus, approximately half the supply
current goes directly to the positive side of the load, and the other half,
through the ICL7662, to the negative side of the load. Ideally, VLOAD ..
2VIN, Is '" 2 IL' so VIN • Is '" VLOAD· IL

PVO

UT

0320-17
NOTE: For large value of Cose (> 1000pf) the values of C, and C2
should be increased to 100f'F.

CIRCUIT DESCRIPTION
The ICL7662 contains all the necessary circuitry to complete a negative voltage converter, with the exception of 2
external capacitors which may be inexpensive 1OI'-F polarized electrolytic capacitors. The mode of operation of the
device may be best understood by considering Figure 4,
which shows an idealized negative voltage converter. CapaCitor C, is charged to a voltage, V + , for the half cycle
when switches 8, and 83 are closed. (Note: 8witches 82
and 84 are open during this half cycle.) During the second
half cycle of operation, switches 82 and S4 are closed, with
8, and 83 open, thereby shifting capaCitor C, negatively by
V + volts. Charge is then transferred from C, to C2 such
that the voltage on C2 is exactly V +, assuming ideal
switches and no load on C2. The ICL7662 approaches this
ideal situation more closely than existing non-mechanical
circuits.
In the ICL7662, the 4 switches of Figure 4 are MOS power switches; 8, is a P-channel device and 82, 83 & 84 are
N·channel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of 83 & 84
must always remain reverse biased with respect to their
sources, but not so much as to degrade their "ON" resistances. In addition, at circuit startup, and under output short
circuit conditions (VOUT=V+), the output voltage must be
sensed and the substrate bias adjusted accordingly. Failure
to accomplish this would result in high power losses and
probable device latchup.

Figure 3: ICL7662 Test Circuit

0320-18

Figure 4: Idealized Negative Converter

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPAESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values havs been charact9lizsd but are not tested.

5-24

ICL7662
THEORETICAL POWER EFFICIENCY
CONSIDERATIONS

TYPICAL APPLICATIONS
Simple Negative Voltage Converter

In theory a voltage multiplier can approach 100% efficiency if certain conditions are met:
A
The drive circuitry consumes minimal power
B
The output switches have extremely low ON resistance and virtually no offset.
The impedances of the pump and reservoir capacitors are negligible at the pump frequency.
The ICL7662 approaches these conditions for negative
voltage multiplication if large values of C1 and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E=%C1 (V12-V22)
where V1 and V2 are the voltages on C1 during the pump
and transfer cycles. If the impedances of C1 and C2 are
relatively high at the pump frequency (refer to Figure 4)
compared to the value of RL, there will be a substantial
difference in the voltages V1 and V2. Therefore it is not only
desirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly
large value for C1 in order to achieve maximum efficiency of
operation.

The majority of applications will undoubtedly utilize the
ICL7662 for generation of negative supply voltages. Figure
5 shows typical connections to provide a negative supply
where a positive supply of + 4.5V to 20.0V is available.
Keep in mind that pin 6 (LV) is tied to the supply negative
(GND) for supply voltages below 11 volts.
The output characteristics of the circuit in Figure 5 are
those of a nearly ideal voltage source in series with 65
ohms. Thus for a load current of -10mA and a supply voltage of + 15 volts, the output voltage will be 14.35 volts. The
dynamic output impedance due to the capaCitor impedances is approximately 1/roC, where:

e

C=C1=C2

.

3.

1

1

which gives - =
f
0 5 = 3 ohms
roC 27T pumpx 1 for C = 10 ",F and fpump = 5kHz (% of oscillator frequency)

Paralleling Devices
Any number of ICL7662 voltage converters may be paralleled to reduce output resistance. The reservoir capaCitor,
C2, serves all devices while each device requires its own
pump capacitor, C1. The resultant output resistance would
be approximately
ROUT (of ICL7662)
ROUT n (number of devices)

DO'S AND DON'TS
1.
2.

.

Do not exceed maximum supply voltages.
Do not connect LV terminal to GROUND for supply
voltages greater than 11 volts.
When using polarized capacitors, the + terminal of
C1 must be connected to pin 2 of the ICL7662 and
the + terminal of C2 must be connected to
GROUND.

Cascading Devices
The ICL7662 may be cascaded as shown to produce larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical
limit is 10 devices for light loads. The output voltage is defined by:
VOUT= -n (VIN),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7662 ROUT
values.

,..--------_---0

YOUT

=-

y+

--,
~

51-----'
0320-19

Figure 5: Simple Negative Converter

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE' All typical values have been characterized but are not tested

5-25

•

.,...= ICL7662
g

0320-20

Figure 6: Paralleling Devices
v+

1 - - - - - - r - o O VOUT

:Ii 10~F
0320-21

Figure 7: Cascading Devices for Increased Output Voltage
Y+

It is also possible to increase the conversion efficiency of
the ICL7662 at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is
achieved by connecting an additional capacitor, Cosc, as
shown in Figure 9. However, lowering the oscillator frequency will cause an undesirable increase in the impedance of
the pump (Cl) and reservoir (C2) capacitors; this is overcome by increasing the values of C, and C2 by the same
factor that the frequency has been reduced. For example,
the addition of a 100pF capacitor between pin 7 (Osc) and
V+ will lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and thereby necessitate a corresponding increase in the value of C, and
C2 (from 10ll-F to 100ll-F).

Y+

lOOk

CMOS
ClATE

1 - - - - - - - - , - - - - < l Y OUT

0320-22

Figure 8: External Clocking

Changing the ICL7662 Oscillator
Frequency

V+

It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an external clock, as shown in Figure 8. In order to prevent possible
device latchup, a 1OOkO resistor must be used in series with
the clock output. In the situation where the designer has
generated the external clock frequency using TTL logic, the
addition of a 10kO pullup resistor to V+ supply is required.
Note that the pump frequency with external clocking, as
with internal clocking, will be Yz of the clock frequency. Output transitions occur on the positive-going edge of the
clock.

ICL7662

Cose

t------~---o

VO UT

0320-23

Figure 9: Lowering Oscillator Frequency

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typIcsJ vaJuss have bHn charscfBrlzed but 8rB not fBsted.

5-26

ICL7662
Positive Voltage Doubling

Voltage Splitting

The ICL7662 may be employed to achieve positive voltage doubling using the circuit shown in Figure 10. In this
application, the pump inverter switches of the ICL7662 are
used to charge C, to a vOltage level of V+ -VF (where V+
is the supply voltage and VF is the forward voltage drop of
diode D,). On the transfer cycle, the voltage on C, plus the
supply voltage (V +) is applied through diode D2 to capacitor C2. The voltage thus created on C2 becomes
(2V+)-(2VF) or twice the supply voltage minus the combined forward voltage drops of diodes D, and D2.
The source impedance of the output (VOUT) will depend
on the output current, but for V + = 15 volts and an output
current of 10mA it will be approximately 70 ohms.

The bidirectional characteristics can also be used to split
a higher supply in half, as shown in Figure 12. The combined load will be evenly shared between the two sides and,
a high value resistor to the LV pin ensures start-up. Because the switches share the load in parallel, the output
impedance is much lower than in the standard circuits, and
higher currents can be drawn from the device. By using this
circuit, and then the circuit of Figure 7, + 30V can be converted (via + 15V, and -15V) to a nominal -30V, although
with rather high series output resistance (- 2500).

v+

y+

L---~~~-1-v0320-26

Figure 12: Splitting A Supply in Half
NOTE:
01 " D2 CAN BE ANV
SUITABLE DIODE

Regulated Negative Voltage Supply
In some cases, the output impedance of the ICL7662 can
be a problem, particularly if the load current varies substantially. The circuit of Figure 13 can be used to overcome this
by controlling the input voltage, via an ICL7611 low-power
CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since
the ICL7662's output does not respond instantaneously to a
change in input, but only after the switching delay. The circuit shown supplies enough delay to accommodate the
7662, while maintaining adequate feedback. An increase in
pump and storage capacitors is desirable, and the values
shown provides an output impedance of less than 50 to a
load of 10mA.

0320-24

Figure 10: Positive Voltage Doubler

Combined Negative Voltage Conversion
and Positive Supply Doubling
Figure 11 combines the functions shown in Figures 5 and
10 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for
example, suitable for generating + 9 volts and - 5 volts
from an existing + 5 volt supply. In this instance capacitors
C, and Cs perform the pump and reservoir functions respectively for the generation of the negative voltage, while
capacitors C2 and C4 are pump and reservoir respectively
for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will
be somewhat higher due to the finite impedance of the
common charge pump driver at pin 2 of the device.

-....
SOl<

....

ICL8089

0320-27

Figure 13: Regulating the Output Voltage

OTHER APPLICATIONS

0320-25

Further information on the operation and use of the
ICL7662 may be found in A051 "Principals and Applications
of the ICL7660 CMOS Voltage Converter".

Figure 11: Combined Negative Converter
and Positive Doubler

lNTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPAESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characten'zed but are not tested.

5-27

D~DIb

:: ICL7663

~ CMOS Programmable
!:! Micropower Voltage Regulators
GENERAL DESCRIPTION

FEATURES

The ICL7663 positive voltage regulator is a low-power,
high-efficiency device which accepts inputs from 1.6V to
l6V and provides adjustable outputs over the same range
at currents up to 40mA. Operating current is typically less
than 4p.A, regardless of load.
Output current sensing and remote shutdown are available, providing protection for the regulator and the circuits it
powers. A unique feature is a negative temperature coefficient output. This can be used, for example, to efficiently
tailor the voltage applied to a multiplexed LCD through the
driver e.g., ICM7231/2/3 so as to extend the display operating temperature range many times.
An enhanced direct replacement for this part called
ICL7663S is now available and is more appropriate for new
designs.
The ICL7663 is available in 8-pin plastic, TO-99 can,
CERDIP, and SOIC packages.

• Ideal for Battery·Operated Systems: Less Than 4p.A
Typical Current Drain
• Will Handle Input Voltages From 1.6V to l6V
• Very Low Input·Output Differential Voltage
• 1.3V Bandgap Voltage Reference
• Up to 40mA Output Current
• Output Shutdown Via Current·Llmlt Sensing or
External Logic Signal
• Output Voltages Programmable From 1.3V to l6V
• Output Voltages With Programmable Negative
Temperature Coefficients

ORDERING INFORMATION
Positive Regulator
Part Number
ICL7663CBA
ICL7663CPA
ICL7663CJA
ICL7663CTV

Temperature Range
O°C to
O°C to
O°Cto
O°C to

+ 70°C
+ 70°C
+ 70°C
+ 70°C

+

Y,N

Package
8-LeadSOIC
8-Lead MiniDIP
8-Lead CERDIP
8-Lead TO-99

0..:.-_. . . ,.
8

r-+---+--------oVOUT1
L......W_t-------'O"OVOUT2

,~-------_'<>SENSE

Vl------------__''<> VSET

>-.....-=-OVTC
'---11---+---------=.0 SHUTDOWN
o-----~~-~-------~GND

0321-1

ICL7663
Figure 1: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE'IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typ;caf values haV9 been characterized but are not tssted.

5-28

ICL7663
ABSOLUTE MAXIMUM RATINGS, ICL7663 POSITIVE REGULATOR
Input Supply Voltage ... . . . . . . . . . . . . . . . . . . . . . . . .. + 18V
Any Input or Output Voltage (Note 1) (Terminals 1, 2, 3,
5,6,7) ................ (GND -O.3V) to (V+IN +O.3V)
Output Source Current
(Terminal 2) ........•......................... 50mA
(Terminal 3) .................................. 25mA

Output Sinking Current (Terminal 7) ............. -10mA
Power Dissipation (Note 2)
MiniDIP ........................•........... 200mW
TO-99 Can ................................. 300mW
Operating Temperature Range ............ O'C to + 70'C
Storage Temperature ................ - 65'C to + 150'C
Lead Temperature (Soldering, 1Osee) ............. 300'C

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operationsl sections of the speclficstions is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliabIlity.
NOTE:

ICL7663 Positive Regulator
SENSE
VOUT2
VOUT1
GROUND

0321-4

GROUND

0321-3

(outline dwg PA, JA)

(outline dwg TV)
Figure 2: Pin Configurations

(outline dwg BA)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

5-29

•

C")

U)
U)

.......
2

ICL7663
ICL7663 ELECTRICAL CHARACTERISTICS
VIN+ =9V, VOUT=5V, TA = + 25'C, unless otherwise specified. See Test Circuit Figure 3.

Symbol

Parameter

Limits

Test Conditions
Min

Typ

1.5
1.6

Units
Max
16.0
16.0

V

4.0
3.5

12
10

J-tA

1.3

1.4

V

VIN

Input Voltage

TA= + 25'C
O'C:S:TA:S:+70'C

10

Quiescent Current

{ Rl = 00
}
I.4V:S:VOUT:S:8.5V

VSET

Reference Voltage

aVSET
AT

Temperature Coefficient

8.5V
3:

VOUT~R2+R1
R,

VSET

4: 10 quiescent current is measured at GND pin by meter M.
5: 83 when ON, permits normal operation, when OFF, shuts
down both VOUT1 and VOUT2·

RL

R,
1,.AMIH

ON

S.
OFF
lUQ
'-----'WIr--01.4V 4.970 Ht-Hllllt-ttlltllt-tttlllllt-tttt. .tillitil
4.965 1-+I-fM-HlIlfIII--I+I!!111-+Hiilllf-++HI1III

4.980 Hf-Hllllf--ffiHll!-+HfIIIIH+!!IIIII-+iKflll
4.955 Hf-Hllllf--ffiIllllf-+HfIIIIH+!!IIIII-+iKflll

I
I

1.4 1-1-

VI~=2V 1 J

.1 +1 1
VIN =9V

0.4
0.2

.Yf

lOUT (rnA)

~

-I- ~:::: ~ ~15V- -

o J,.~
o 2 4

4.950 WL.IJIIIU...J..U.UJIII....LJJllIJlL..L.J.WJIL.WUlJIII
1,.A 10,.A 100,.A 1.0 10.0 100.0

"7 ~

I I

VIN= +9.0V
 .....-OVOUT

0321-20

R2
R2
EO.1: VOUT=VSET(1 +-) +-R(VSET-VTC)
R1
3
EO.2: TC VOUT= - ::(TCVTcl in mVrC
WHERE: VSET= 1.3V
VTC=0.9V
TCVTC = + 2.5mV

rc

Figure 4: Generating Negative Temperature
Coefficients

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

5-33

01

ICL7663
APPLICATIONS

•

VIN

SENSE
RCL
VOUT2

r-

"I =7.,.,••

VOUTl
ICL7663
VTC '-"-

.,1
VOUT

VSET

GND SHDN

1

1

~

Rl

1
V OUT =R2+Rl VSET
ICL = O.7V
RCL
0321-21

Figure 5: Basic Application of ICL7663 as
Positive Regulator with Current Limit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not t6Sted

5-34

ICL7663
ICL7663B ADDENDUM TO THE ICL7663 DATASHEET
This Addendum to the standard ICL7663 datasheet describes changes and/or modifications to the DC Operating
characteristics applicable to the ICL7663B devices. The following table indicates those limits to which the ICL7663B is
tested and/or guaranteed operational.

ICL7663B POSITIVE REGULATOR
ORDERING INFORMATION
Positive Regulator
ICL7663BCBA
ICL7663BCJA
ICL7663BCPA
ICL7663BCTV

O·Cto 70"C
O·Cto 70·C
O"Cto 70"C
0·Ct070·C

B-pin S.O.I.C.
B-pin CERDIP
B-pin MiniDIP
TO-99

ABSOLUTE MAXIMUM RATINGS ICL7663B
Output Sinking Current (Terminal 7) ............. -10mA
Power Dissipation (Note 2)
MiniDIP ......•............................. 200mW
TO-99 Can ................................. 300mW

Input Supply Voltage ......•.•.•...•..•.......... + 12V
Any Input or Output Voltage (Note 1) Terminals 1, 2, 3, 4, 5,
6, 7) ............•...•..• (GND -0.3V) to (V+ IN + 0.3V)
Output Source Current
(Terminal 2) .....................•.....•...... 50mA
(Terminal 3) ..................•.........•...•. 25mA

NOTE: Stresses above those listed under "Absolute Maximum Ralfngs" may cause permt1nsnt damage to the device. Thase are stress ratings only and functional
operation of Iha device at lhasa or any other conditions abovelhose Indicated in Iha operationsl sections of Iha specifications Is not impHed. Exposure to absolute
maximum rating conditions for extended periods may sffscl device reliability.

ICL7663B OPERATING CHARACTERISTICS

V+IN=9V, VOUT= 5V, TA= + 25·C, unless otherwise

specified.
Symbol

Parameter

Limits

Test Conditions
Min

Input Voltage

TA= +25·C
20·CS:TAS: +70"C

IQ

Quiescent Current

{Rl=OO
}
1.4VS:VOUTS:B.5V

VSET

Reference Voltage

V+IN

aVSET
aT
aVSET
VSETaVIN
ISET
ISHDN

1.2

V

3.5

10

",A

1.3

1.4

V

±200

ppm

Line Regulation

2V2000V

APPLICATIONS
-

Low·Powar Portable InstNmantatlon
Pagera
Handhald InatNmanta
LCD DlllPlay Modules
Ramota bafa LoaaBattary-Powared-Syatams

ORDERING INFORMATION

TOPYIEW

PART
NUMBER
ICL7883SCBA
ICL7883SCPA
ICL7883SCJA
ICL7883SCTV
ICL7883SACPA
ICL7883SACJA
ICL7883BACTY
ICL7883SIBA
ICL7883SIPA
ICL7883SIJA
ICL7883SITV
ICL7883SAIPA
ICL7883SA1JA
ICL7883SAITV

OUTUM DWG (SAl

TEMPERATURE
RANGE
."C to +70"C

PACKAGE
8 Laad SOIC
8 Laad Mlnldip
8 Lead CERDIP

1t).88

8 Lead Mlnldlp
8 Lead CERDIP

"10-118

-25"C 10 +85·

8 Lead SOlO

:t=~~n~tfp

1t).88

: t::l ~~~Jfp

1t).88

-.

GROUND

......
,r-+.:;;~===:::t
,

OUTLINE DWG (Till

OUTLINE DWG (PA, JAI

'--+--1------'<>' SHU11tOWN

C>----+-........----..!o' aN'
Figure 2: ICL7613S Functional Diagram

Figure 1: Pin CClntlgumklns

0092-1

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TC THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
302166.001

NOTE: AU typIcsJ _

have bHn _

but.,. not 1BtJ/BtI.

5·37

= ICL7663S
10

...10
..I

g

ABSOLUTE MAXIMUM RATINGS
Stresses above those Hsted under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or
any other conditions above thOse indicated in the operational
sections of the specifications is not imp/ted. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.

Input Supply Voltage ................................................... + 18V
Any Input or Output Voltage (Note 1)
(Terminals 1,2,3,S,6,7,)..............(VIN +0.3) to (GND -0.3)V
Output Source Current
(Terminal 2) ..........................................................SOmA
(Terminal 3) ..........................................................2SmA
Output Sinking Current
(Terminal 7) ....................................................... -10mA
Lead Temperature (Soldering, 10 sec) .......................300·C
Storage Temperature Range ........................ -6S· to IS0·C
Operating Temp. Range
ICL7663SC .............................................0·C to + 70·C
ICL7663SI.. ....................................... -2S·C to +8S·C
Total Power Dissipation (Note 2)
SOIC .................................................................. 200mW
Minidip ............................................................... 200mW
T0-99 Can .........................................................300mW
CERDIP ............................................................. SOOmW

ELECTRICAL CHARACTERISTICS Specifications below applicable to bOth ICL7663S and ICL7663SA unless otherwise stated. V,. - 'JI/, VOUT = SV, TA = 2S"C, unless otherwise stated. See Test
Circuit, Figure 3.
LIMITS
SYMBOL

V.,

PARAMETER

InputVo/1age

TEST CONDITIONS

MIN

1CL7663$
TA = 2S'C
O'C < TA < 70'C
-2S'CIour

TEST CONDITIONS

VSHDN HI: Both VOUT Disabled
VSHDN LO: Both VOUT Enabled

MIN

TYP

MAX

UNITS

:to.Ol

10

nA

0.3

V
V

10

nA

50
35

350
100
70

0
0
0

1
2

3
10

0
0

1.4

0.01
0.5

'N. loun • 1rnA
V+ IN - av. 'oun • 2mA
V+ IN - 15V• .Ioun • SmA
lmA < 10UT2 < 20mA
5Oj 1.3V, OUT1 switch ON
HYST1 switch ON
VSETl < 1.3V, OUT1 switch OFF
HYST1 switch OFF
VSET2> 1.3V, OUT2 switch OFF
HYST2 switch ON
VSET2<1.3V, OUT2 switch ON
HYST2 switch OFF
• See Operating Characteristics for exact thresholds.

>-l-l-ll;;---o oun
lIT2o--t----tr
0UT1
ClND
0322-1

Figure 1: Functional Diagram

v+

OUT 1

(CASE)

v+

8

V+

7

OUT 2

ICL7885
HYST1

2

SET 1

3

GND

4

OUT 2
SET 2
HYST2

SET 2

5

HYST2
0322-4

(OutUne dwg PAl

(outline dwg BA)

GND
0322-2

(Outlln. dwg TV)
0322-3

Figure 2: Pin Configurations

INTERSlL'S SOLE AND EXCLUSIVE WARRANTY OBLIGAnON WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARnCLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUOlNG THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOlR A PARTICULAR USE.
302067 -003
NeTT!: All typical _

hBlIfI boon t:hsracIstIzed but 0IfI

not_

5-44

ICL7665
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ........................ -0.3Vto +18V
Output Voltages OUT1 and OUT2 (with respect to GND)
(Note2) ............................ -0.3Vto +18V
Output Voltages HYST1 and HYST2 (with respect to V+)
(Note2) ............................ +0.3Vto -18V
Input Voltages SET1 and SET2
(Note 2) ................. (GND-0.3V) to (V+ +0.3V)

Maximum Sink Output Current OUT1 and OUT2 .... 25mA
Maximum Source Output Current HYSTI
and HYST2 ................................ - 25mA
Power Dissipation (Note 1) ..................... 200mW
Operating Temperature Range ............ O·C to + 700C
Storage Temperature Range .......... - 55·C to + 125·C
Lead Temperature (Soldering, 10sec) .......•..•.. 300·C

NOTE: Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damB(J9 to the davice. These are stress ratings only and functional
operation of the davies at these or any othe, conditions above those indiceted in the operetionsl sections of the specifications is not Implied. Exposure to absolute
maximum rating conditions for extended periods may affect davies reliability.

ELECTRICAL CHARACTERISTICS
DC OPERATING CHARACTERISTICS

(V+ = 5V, T A = + 25·C, unless otherwise specified. See Test Circuit

Fig. 4)

Symbol

Test Conditions

Parameter

Min
V+

Operating Supply Voltage

TA= + 25·C
0·C~TA~+70·C

1+

Supply Current

VSET1
VSET2

Input Trip Voltage

~VSET

Temperature Coefficient
ofVSET

~T

~VSET

Supply Voltage Sensitivity
ofVSET1, VSET2
Output Leakage Currents
on OUT and HYST

~Vs

IOlK
IHlK

1.6
1.8

GND~VSET1' VSET2~V+
All Outputs Open Circuit
V+=2V
V+=9V
V+=15V

1.15
1.2

ROUT1' ROUT2' RHYST1, RHYST2 = 1MO
VSET=OVorVSET~2V

Limits
Typ

16
16

Output Saturation Voltages

VOUT1
VOUTI
VOUT1

V+ =2V, VSETI =2V,IOUT1 =2mA
V+ =5V, VSETl =2V, IOUT1 =2mA
V+ =9V, VSET1 =2V,IOUTI =2mA

VHYST1
VHYSTI
VHYST1

V+ =2V, VSET1 =2V,IHYST1 = -0.5mA
V+ =5V, VSETI =2V,IHYST1 = -0.5mA
V+ =9V, VSET1 =2V,IHYST1 = -0.5mA

VOUT2
VOUT2
VOUT2

V+ =2V, VSET2=OV,IOUT2=2mA
V+ =5V, VSET2=OV,loUT2=2mA
V+ =9V, VSET2=OV,IOUT2=2mA

VHYST2
VHYST2
VHYST2

V+ =2V, VSET2=2V,IHYST2= -0.2mA
V+ =5V, VSET2=2V,IHYST2= -0.5mA
V+ =9V, VSET2=2V,IHYST2= -0.5mA

ISET
~VSET

VSET1-VSET2

V

2.5
2.6
2.9

10
10
15

/loA

1.3
1.3

1.45
1.4

V

±200

ppml"C

0.004

%IV

10
-10

V+ =9V, TA=70·C
V+=9V, TA=70·C

IOlK
IHlK

Units
Max

200
-100

nA

2000
-500
0.2
0.1
0.06

0.5
0.3
0.2

-0.15
-0.05
-0.02

-0.3
-0.15
-0.10

0.2
0.15
0.11

0.5
0.3
0.25

-0.25
-0.43
0.35

-0.8
-1.0
-1.0

0.Q1

10

VSET Input Leakage Current

GND~VSET~V+

~ VSET

Input for Complete
Output Change

ROUT=4.7kO, RHYST=20kO
VOUTLO=1% V+, VOUTHI=99% V+

Difference in Trip Voltages

ROUT, RHYST=1MO

±5

Output! Hysteresis Difference

ROUT, RHYST=1MO

±1

V

nA

1
mV
±50

NOTES: 1. Derate above ±2S"C ambient temperature at4mWI"C.
2. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to voltages greater than (V+ + O.3V)
or less than (GND - O.3V) may cause destructive device latch up. For these reason, ~ is recommended that no inputs from external sources not
operating from the same power supply be applied to the device before its supply is established, and that in multiple supply systems, the supply to the
ICL766S be turned on first. If this is not pOSsible, currents into Inputs andlor outputs must be limited to ± O.SmA and voltages must not exceed those
defined above.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY 09LIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND BHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical

va/uBs have been characterized but sre not t6stBd.

5-45

,.

.D~DIl.

: ICL7665

...
co

~ AC ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Limits

Test Conditions

Typ

Min
tS01d
tsH1d
tS02d
tSH2d
ts01d
tsH2d
ts02d
tsH2d
t01r
t02r
tH1r
tH2r

1011

Output Delay Time
Input Going HI

OUT1

70
80
120
230

p.s

VSET Switched from 1.6V to 1.0V
ROUT=4.7kO, CL = 12pF
RHYST=20kO, CL =12pF

1040
610
70
30

p.s

VSET Switched between 1.0V and 1.6V
ROUT=4.7kO, CL =12pF
RHYST = 20kO, CL = 12pF

120
80
330
25

p.s

VSET Switched between 1.0V and 1.6V
ROUT = 4.7kO, CL = 12pF
RHYST=20kO, CL = 12pF

30
60
180
30

p.s

Output Rise Times

Output Fall Times

to2f
tH1I
tH2f

INPUi

VSET Switched from 1.0V to 1.6V
ROUT=4.7kO, CL = 12pF
RHYST=20kO, CL =12pF

Output Delay Time
Input Going LO

VSET1. YSET2

I

tS01d-

Units
Max

1.6V

I

-------1.0Y

-

tS01d

p- to1t

-------Y+ (5Y)
t--t01r

GND
Y+ (5Y)

HYST1

tSH1d-

1-/
I.0oI""

OUT2

tso2d-

tH1r

-tAH1d-==

I

.!l;

1\

- ~t=:-to2f

I--tH1t

-------GND
Y+ (5Y)

tio2d-

~r to2r

-------- GND
Y+ (5Y)

HYST2

tsH2d

tH2r

tiH2d-

r-

tH2f

-

......-GND
0322-5

FIgure 3: Switching Waveforms

INTERSIL'S SOLE AND exCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE exCLUSIVE AND SHALL SE IN UEU OF ALL OTHER WARRANTIEB. EXPRESS. IMPUED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN typics/ vsluss hsWJ bHn charscterizsd but IUS not tsstf1d.

5-46

ICL7665
V+

4.7kll
~----------------~--_4----~--~--------------~OUTl

.----!----.----------o HYST1

4.7kll

~--~~--+---~---+--~~----oOUT2

INPUT
1.8V-r-1

1.0V ____---l

I....-

~r---.---+--_4----+---+--_._oHYST2

0322-6

Figure 4: Test Circuits

TYPICAL PERFORMANCE CHARACTERISTICS
OUTl SATURATION VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

E 2.0

w
<:J

0

...~

0

:::>

c
!:i

1.6

Z

>
z 1.2

~
:::>

0.8

!ci
III
;::

0.4

w

a:
a:

(.)

>
oJ

...:::>...
III

:::>

0

5.0
4.5 f-- OV " ViET1'I VSjT2 " V+ _
4.0
3.5 1 - - - _ TA= -20'C -~
3.0 h " - -TA= +2S'C;:;;:;0
2.5
2.0
TA= +70'C
1.5
I I I
1.0
I I I
0.5

:::

o

4
8
12
16
20
OUT1 OUTPUT CURRENT (mA)

I I I

o

2 4 6 8 10 12 14 16
SUPPLY VOLTAGE (V+)

0322-7

OUT2 SATURATION VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

E 2.0 r---',-"-,-,,,--,,--,

w
<:J

:!
o

a:
~ 0.8 r-L-~~-1~~~-1--1

:::>

~
o~

0.4

SUPPLY CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE

zw

~ 1.2 t---IrlH--,/-T

f---.l~~O--1--1--1
'TA= +2S'C

0""--''---'---''----'
o
12
16
20
OUT2 OUTPUT CURRENT (mA)

-20 -16

-12

-8

-4

0

r:;--=::r--r---.--::::. 0

-b.,..,e-=t.-~'!--H

-0.4

1""'--r,.;L-I--TI---t--lH -0.8

*--+--+-+--1

-1.2

I--~-=-r--'::":"I---trl--l

-1.6

'--'L..!._-L_--'-_.L...lL.-J -

a:
a:

:::>

(.)

~
......:::>

III

5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5

- OVJ" ~SETt VSETi

~

~=115V
vi
~ ;.,;;
v+ =2V

"t -

2.0

-

~~
(5!!l

z(§
;~
~ ....

S

3

0322-9

HYST2 OUTPUT SATURATION VOLTAGE
VS HYST2 OUTPUT CURRENT
-5.0 -4.0 -3.0 -2.0 -1.0

0
=---___
-:-r---r----,.--"'" 0
TA= +2SOC

III

I---I----I--t......,.rt-t--t -1.0

=~v

~

HYST1 OUTPUT CURRENT (mA)

0322-8

~
...

1.6 r'---,F-'-H-

oJ

o

HYST1 OUTPUT SATURATION VOLTAGE
VS HYST1 OUTPUT CURRENT

~

~~

f---f----:l,..s.91---lf----l -2.0 (5!!l
z ..
"""'7"--7'I----+--t---+ - 3 0 (§

.

1/0--+--+-+---1

o
-20
0
+20 +40 +60
AMBIENT TEMPERATURE (0C)

0322-10

0322-11

L-L..l_-.l.._--'-_"--~

-4.0

S

~~

~ ....

3
-5.0

HYST2 OUTPUT CURRENT (mA)
0322-12

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valuss have be8n charactsrized but are not test9d

5-47

:g ICL7665

......
CI)

!:!

throughout the die. Under certain circumstances, this can
be triggered into a potentially destructive high-current
mode. This latchup can be triggered by forward-biasing an
input or output with respect to the power supply, or by applying excessive supply voltages. I.n very-low current anal?g
circuits such as the ICL7665, thiS SCR can also be triggered by applying the input power supply extremely rapidly
("instantaneously"), e.g. through a low impedance battery
and an ON/OFF switch with short lead lengths. The rate-ofrise of the supply voltage can exceed 1OOV / J.Ls in such a
circuit. A low-impedance capacitor (e.g. O.05J.LF disc ceramic) between the V+ and GrouND pins of the ICL7665 c~n
be used to reduce the rate-of-rise of the supply voltage In
battery applications. In line-operated systems, the rate-ofrise of the supply is limited by other conSiderations, and is
normally not a problem.
If the SET voltages must be applied before the supply
voltage V +, the input current should be limited to less than
O.5mA by appropriate external resistors, usually required for
voltage setting anyway. A similar precaution should be taken with the outputs if it is likely that they will be driven by
other circuits to levels outside the supplies at any time. See
M011 for some other protection ideas.

DETAILED DESCRIPTION
As shown in the Functional Diagram, the ICL7665 consists of two comparators which compare input voltages on
the SET1 and SET2 terminals to an internal 1.3V band-gap
reference. The outputs from the two comparators drive
open-drain N-channel transistors for OUT1 and OUT2, and
open-drain P-channel transistors for HYST1 and HYST2
outputs. Each section, the Under-Voltage Detector and the
Over-Voltage Detector, is independent of the other, although both use the internal 1.3V reference. The offset voltages of the two comparators will normally be unequal, so
VSET1 will generally not quite equal VSET2.
The input impedances of the SET1 and SET2 pins are
extremely high, and for most practical applications can be
ignored. The four outputs are open-drain MaS transistors,
and when ON behave as low resistance switches to their
respective supply rails. This minimizes errors in setting-up
the hysteresis, and maximizes the output flexibility. The operating currents of the bandgap reference and the comparators are around 100nA each.

PRECAUTIONS
Junction-isolated CMOS devices like the ICL7665 have
an inherent SCR or 4-layer PNPN structure distributed

APPLICATIONS
V,N

OFF

1
I

.fb1

~Rpl

V+

• Rp2

•

OUT1

:

OUT2
ICl7685

8m

8ET2

Ru

:
1

ON

_---I-----'-------'---_~ VIN

\irA!

-:b

VNOM

\lrA1

DETECTOR 2 - 1 - DETECTOR 1

0322-13

0322-14

(a) Circuit Configuration

(b) Transfer Characteristics

Figure 5: Simple Threshold Detector

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE ExCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABiliTY AND FITNESS FOR A PARTICULAR USE.
NOrc: All typics/ vsl/J6s have beM charBcteriz9d bUt sre net tested.

5-48

.O~OI!..

ICL7665
Figure 5 shows the simplest connection of the ICL7665
for threshold detection. From the graph (b), it can be seen
that at low input voltages OUT1 is OFF, or high, while OUT2
is ON, or low. As the input rises (e.g. at power-on) toward
VNOM (usually the eventual operating voltage), OUT2 goes
high on reaching VTR2. If the voltage rises above VNOM as
much as VTR1, OUT1 goes low. The equations giving VSET1
and VSET2 are, from Figure 1(a):

ditions. The addition of hysteresis, making the trip points
slightly different for rising and falling inputs, will avoid this
condition.
Figure 6(a) shows how to set up such hysteresis, while
Figure 6(b) shows how the hysteresis around each trip point
produces switching action at different pOints depending on
whether VIN is rising or falling (the arrows indicate direction
of change). The HYST outputs are basically switches which
short out R31 or R32 when VIN is above the respective trip
point. Thus if the input voltage rises from a low value, the
trip point will be controlled by R1n, R2n and R3n, until the trip
point is reached. As this value is passed, the detector
changes state, R3n is shorted out, and the trip point becomes controlled by only R1n and R2n, a lower value. The
input will then have to fall to this new point to restore the
initial comparator state, but as soon as this occurs, the trip
point will be raised again.
An alternative circuit for obtaining hysteresis is shown in
Figure 7. In this configuration, the HYST pins put the extra
resistor in parallel with the upper setting resistor. The values
of the resistors differ, but the action is essentially the same.
The governing equations are given in Table 1. These ignore
the effects of the resistance of the HYST outputs, but these
can normally be neglected if the resistor values are above
about 100kO.

R11
R12
VSET1 =VIN(R11 + R21); VSET2=VIN(R12+ R22)
Since the voltage to trip each comparator is nominally
1.3V, the value of VIN for each trip point can be found from
V
=V
(R11+ R21)
TR1
SET1
R11

13(R11+ R21)fordetector1
.
R11

and
V
=V
(R12+ R22)
TR2
SET2
R12

13(R12+ R22)fordetector2
.
R12
.

Either detector may be used alone, as well as both together, in any of the circuits shown here.
When VIN is very close to one of the trip voltages, normal
variations and noise may cause it to wander back and forth
across this level, leading to erratic output ON and OFF con-

V,N

I

~R~

I

~ HYST1

V+

HYST2

r-

SET2

l-

t-

....... r-~

I

~",

Raaf
~ SET'

I

ON

Raal

ICL7_

I

I

I
1
OVER·VOLtAGE

our,

GND

oun

Rn

1

OFF

UNDER·VOLTAGE

Vu Vuz

VL'VU'

R'2

Vu

~

I---

0322-15

DETECTOA1-

DETECTOR 2

IINoM

r-

0322-16

(a) Circuit Configuration

(b) Transfer Characteristics

Figure 6: Threshold Detector with Hysteresis

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUOING THE IMPLlEO WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been chsrsct9riz9d but are not tested.

5-49

GI
GI
'"

•

OUT

I
I 113,

,.n...

:: ICL7665
CD
...g....

1
~

t:~

Rp
"..

T

~

~

y+

•
OUT1

OUT2

HYST1

HYST2

-

:.~

"..

Ru

R3t
ICL7865

SEn

•
Rt t ~~

Rp

SET2

.
.~

:~ Rt2

.J.

-

"!!!!!!o

Figure 7: An Alternative Hysteresis Circuit

---

0322-17

Table 1. Set·Point Equations
c) HYSTERESIS PER FIGURE 7

a) NO HYSTERESIS

Rn + R21
Over-Voltage VTRIP=---XVSETl
Rn

Rn +R21
Rn
R21 R31
R11+---R21 +R31
VL1 =
R
XVSETl
11
VUl =---xVSETl

Over-Voltage VTRIP

b) HYSTERESIS PER FIGURE 6A

Over· Voltage VTRIP

Rll + R21 + R31
XVSETl
R11

Under.Voltage VTRIP

Rn +R21
XVSETl
R
11

Under.Voltage VTRIP

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical val/Jes have been characterized but are not tested.

5-50

ICL7665
ICL7665B ADDENDUM TO THE ICL7665 DATASHEET
ORDERING INFORMATION

This Addendum to the standard ICL7665B datasheet describes changes and/or modifications to the DC Operating
characteristics applicable to the ICL7665B device. The following table indicates those limits to which the ICL7665B is
tested and/or guaranteed operational.

Part Number

Temperature Range

ICL7665BCPA
ICL7665BCTV
ICL7665BCJA
ICL7665BCBA

oto + 70'C
oto +70'C
oto + 70'C
oto +70'C

Package
8 Lead MiniDIP
8 Lead TO-99
8-Lead CERDIP
8-Lead S.O.I.C.

ABSOLUTE MAXIMUM RATINGS, ICL7665B
Supply Voltage ........................ -0.3V to + 12V
Output Voltages OUT1 and OUT2 (with respect to GND)
(Note 2) ............................ - 0.3V to + 12V
Output Voltages HYST1 and HYST2 (with respect to V+)
(Note 2) ............................ + 0.3V to -12V
Input Voltages SET1 and SET2
(Note 2) ................ (GND -0.3V) to (V+ + 0.3V)

Maximum Sink Output Current OUT1 and OUT2 .... 25mA
Maximum Source Output Current HYST1
and HYST2 ................................ - 25mA
Power Dissipation (Note 1) ..................... 200mW
Operating Temperature Range .............. 0 to + 70'C
Storage Temperature Range .......... - 55'C to + 125'C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

DC OPERATING CHARACTERISTICS
Symbol

Parameter

v+ = 5V. TA = + 25'C. unless otherwise specified.
Limits

Test Conditions
Min

V+

Operating Supply Voltage

TA= + 25'C
0"TA,,+70'C

1+

Supply Current

GND"VSET1. VSET2"V+
All Outputs Open Circuit
V+=2V
V+=9V

VSET1
VSET2

Input Trip Voltage

aVSET
aT

Temperature Coefficient
ofVSET

aVSET
avs

Supply Voltage Sensitivity

IOlK
IHlK

Output Leakage Currents
on OUT and HYST

IOlK
IHlK

of VSET1. VSET2

Typ

1.6
1.8

1.15
1.2

ROUT1. ROUT2. RHYST1. RHYST2 = 1M!l
VSET=OVorVSET:?:2V
V+ =9V. TA=70'C
V+ =9V. TA=70'C

Units
Max
10
10

V

2.5
2.6

10
10

f.tA

1.3
1.3

1.45
1.4

V

±200

ppml'C

0.004

%N

10
-10

200
-100

nA

2000
-500

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

5-51

•

.O~OI!..

:: ICL7665

2... DC OPERATING CHARACTERISTICS
CC)

Symbol

Parameter

v+ = 5V, TA =

+ 25°C, unless otherwise specified. (Continued)
Limits

Test Conditions
Min

VOUTl
VOUTl
VOUT1

Output Saturation Voltages

V+ =2V, VSETl =2V, IOUTl =2mA
V+ =5V, VSETl =2V, IOUTl =2mA
V+ =9V, VSETl =2V, IOUTl =2mA

VHYSTl
VHYST1
VHYSTl

V+ =2V, VSETl =2V, IHYSTl = -0.5mA
V+ =5V, VSETl =2V, IHYSTl = -0.5mA
V+ =9V, VSETl =2V, IHYSTl = -0.5mA

VOUT2
VOUT2
VOUT2

V+ =2V, VSET2=OV, IOUT2=2mA
V+ =5V, VSET2=OV, IOUT2=2mA
V+ =9V, VSET2=OV, IOUT2=2mA

VHYST2
VHYST2
VHYST2

V+ =2V, VSET2=2V, IHYST2= -0.2mA
V+ =5V, VSET2=2V, IHYST2= -0.5mA
V+ =9V, VSET2=2V, IHYST2= -0.5mA

Units

Typ

Max

0.2
0.1
0.06

0.5
0.3
0.25

-0.15
-0.05
-0.02

-0.3
-0.15
0.15

0.2
0.15
0.11

0.5
0.3
0.3

-0.25
-0.43
0.35

-0.8
-1
-1

0.01

10

ISET

VSET Input Leakage Current

GND,;;;VSET';;;V+

aVSET

a V SET Input for Complete
Output Change

ROUT=4.7kO, RHYST=20kO
VOUTLO=1% V+, VOUTHI=99% V+

VSET1-VSET2

Difference in Trip Voltages

ROUT, RHYST=1MO

±5

Output/Hysteresis Difference

ROUT, RHYST = 1MO

±1

V

nA

1
mV
±50

NOTES: 1. Derate above ± 25°C ambient temperature at 4mW rc.
2. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to voltages greater than (V+ +O.3V)
or less than (GND - O.3V) may cause destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating
from the same power supply be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICL76658
be turned on first. If this is not possible, currents into inputs and/or outputs must be limited to ±O.5mA and voltages must not exceed those defined
above.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.
NOTE: All typical val/J6S hsve been characterized but are not tested.

5-52

D~DIL

ICL7665S

CMOS Micropower Over/Under
Voltage Detector
GENERAL DESCRIPTION

FEATURES

The ICL7665S Super CMOS Mlcropower OverIUnder Voltage
Detector contains two low power, Individually programmable
voltage detacIors on a single CMOS chip. Requiring typically 3,.A
for operation. the device is intanded lor batte~perated systems
and instruments which require high or low voltage wamlngs. setIabIe trip points. or fault monitoring and correction. The trip points
and hysteresis 01 the two voltage detectors are Individually programmed via external resistors. An internal bandgap-type reference provides an accurate threshold voltage while operating
from any supply In the 1.61/ to 16V range.

• GUlranteed 10,.A Mlxlmum Quleecent Current over
'IImperatu..
nteed Wider Operating Yo_e Range over Entl..
ODel'ltlnll 'IImperatu.. Ringe
• 1% Thl8lhold Accuracy (ICL-,eeSSAI
• DUll Complrator with 'llracilion ntlrnll Reterence
• 100 ppm/"C 'llmperaturs CoeffIcIent of Thl8lhold Yoltllge
• /ml'rolfld Direct Replecement for Indultry-Standard
ICL788SB Ind Other Sacond-80ulCe DwICH
• Up to lOrnA Output CU".nt Slnldn, Ability
• Individually PIoGrsmmable Upper Ind L.Ner1l1p VoItIg.
Ind Hystll8ll1 U!veIe
• Enhlriced ESD PIotIctlon, >2OOOV

• aul..

The Intersil ICL7665S, Super Programmable Over/Under
Voltage Detector Is a direct replacement lor the Industry standard
ICL7665B offering wider operating voltage and temperature
ranges, /mprDNd threshold accuracy (ICL7865SA). and tempersture coefficient. "".,."..,." maximum supply currant, and ESD
profecfIon in excess 0I2OOfN on all pins. All improvements are
highlighted in bold italics in the electrical characteristics section.
AI/ c~1 ,.reme"" ere ,.,.,.,.,.., ""' file entire commetelel end /ndulftlal tllmpereture renges.

APPLICATIONS
•
•
•
•
•
•
•

Pocllet Pagers
Portable lnatrumentltlon
Chargl=-ms
Memory
r lick-Up
Battary·Operstld Systems
Portable Computlrs
~I OetIctors

ORDERING INFORMATION
PART

TOPYIEW

TEMPERATURE
RANGE

NUMBER

ICL7685SCBA
ICL7685SCPA
ICL7885SCJA
ICL7665SCTV
ICL7886SACPA
ICL7685SACJA
ICL7885SACTV
ICL7665SIBA
ICL7685SIPA
ICL7685SIJA
ICL7685SITV
ICL7685SAIPA
ICL76S5SAJA
ICL7665SAITV

y+
(CASE)

lIlT,

8LeadSOlC
8 Lead Mlnldlp

OOCIO +70OC

8 Lead CERDIP
10-99

:~~~~~fp

'fO.99
8 Lead SOIC

-25OC 10 +65OC

:~~~~'1Wp

10-99
8 Lead Minidip
8 Lead CERDIP
10-99

. - - - - - - - -.....-

OND

PACKAGE

......-0 ••

. :!:-=t~r:-Htt_~~HVST2
HYIT1

Outline dwt (TV)

'>f-.J41~----O 0-OHYST2

Figure 3: Test Circuits

0090-3

INTERSIL'8 SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

5-55

ICL7665S

,.------,I------------'·ev
INPUT
~--------------,.OV

------y+ ISY)
OUT'

'SOld

~--------r_----------~-----GND

J..-----+----t-t--:------Y+ 15Y)

I""

HYST'

i"-----------GND

,,----::---ilH------------Y+ lOY)
r--_1021;;;;..________________ GND

DUT.

I,..----"*t:-:-;:'H="~---------Y+ lOY)
HYSn

~-------------GND

Flgunt 4: Switching Waveforms

A.C. ELECTRICAL CHARACTERISTICS
Limits

Symbol
'so'd
'sHld

Paramster
Output Delay TImes
Input Going HI

tS02d

Teat Conditions
VSETSWltched betWeen
RouT. 4.71<0,

CL • 12pF

R HyST • 2OkD,

CL

tSH2d
'so'd
isH'd

• 12pF

V SET SWitched between
Input Going

LO

'so2d

I.W 10 lIN

ROUT. 4.7kO,
R HYST • 201<0,

CL •
CL •

lIN 10 t!:N

12pF
12pF

'sHOd

10"
Ioz,

ROUT - 4.7kO,

1!:N 10 l.fN
CL - 12pF

t H"
IH2'

R HyST • 201<0,

CL

10"
Iozr

VSET SwItched betWeen

,.."

VSETSwltched betWeen

Outpul Rise Times

Outpul Fall Times

IH2f

RoUT • 4.71<0,
R HYST • 201<0,

• 12pF

CL •
CL •

I.W 10 l.fN

12pF
12pF

Min

~p

Max

Units

85

90

~s

55
55
75
80
80
80

~

0.8
0.8

7.5

~

0.7
0.6
0.7
4

,.

1.8
0090-4

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOT'E: All typlesl values havs been characterized but are not tested.

5·56

ICL7665S
TYPICAL PERFORMANCE CHARACTERISTICS
OUTl SATURATION YOLTAGE AS It,
FUNCTION OF OUTPUT CURRENT

OUTI SATUllATION VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

r-....,---r--r--,

2.0 r--r-....,---,~-:"..,

2.0

HYSTl OUTPUT SATUAATtON VOLTAGE
.. HVSTl OUTPUT CURRENT
-20 -tl -12 -I
-4
0
r.:-:::-::-:;:;;;;r-r--r~ 0

-b~Y'>"f-j~ -0.• ~

":t

0.5

o~~
o

1""-+7"9--7'1----j--i..,

-0.8

,k-+----j--i-i

-1.2

I---J.'-'-r=+----j-f-i

-1.6

'-'LL_.L.----l_...L..L...l -2.0

~~
C5S
~
z~

..

r~

3

101520

I..,oun

(....)

HYln OUTPUT SATURATtoN VOLTAGE

VI HYITZ OUTPUT CURRENT
-5.0 -4.0 -3.0 -2.0 -1.0

HVSTl OUTPUT CURRENT (mA)

..... 0IIT1(....)

SUPPLY CUR_T AS A
FUNCTION OF AMBIENT TEMPERATURE

0

r:-~=r-r--r~

0

I--+-+-hdll'l'l--I

-1.0

I--+-~~'I----jl--I

-2.0

:.;'I~*-+--t----1

-3.0

-Y--::-:I--:::-I-+--I

-4.0

'---'L..L.._'---L_L-~

-5.0

5.0

~":t

!

ZN
cO

~

OV ~

'.5
'.0

~SETI' VSETI s

~~

5 !:! ~~~1'5V

12 ~

~ ~:~
~ 1.0

"c

~ -4

3

2.5

vl.~v

'.5

TA= -2O"C

3.5

~

3.0

F

a: 2.5

iiii

0.'

t--0Y:s VjET1'IVSEra:s V·,_

i1: '.0 1-1- -'A=
o

Y'" =2V

2.0

"""

~

+ZS-C I - ;;;;;

TA= +7O"C

1.5
1.0

0.5

o
-25

HYST2 OUTPUT CURRENT (mA)

r

SUPPL' CURRENT AS A
FUNCTION OF SUPPL• VOLTAGE

5.0

0

+20

+40

+80

AMBIENT TEMPERATURE ('C)

o
o

2 "

6

• 10 12 1. ..

SUPPLY VOLTAGE (Y+)

0090-5

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical va/uss have been charscterized but 8f8 not f9sted.

5-57

.O~OI!..

ICL7665S
DETAILED DESCRIPTION

SIMPLE THRESHOLD DETECTOR

As shown In the Functional Diagram, Figure 2, the ICl7665S
consisIs of two comparators whiCh compare input voltages on the
sen and SE12 terminals to an intemall:N bandllap reference.
The outpUts from the two comparetors drive open-drain N-channellranslstora for OUT1 and OU1li!, and open-drain P-channel
transistors for HYSTI and HYS1li! outputs. Each section, the
Under-lfoltage Detector and the Over-Voltage Dalector, is inde·
pendent of the other, although both use the internal I :N refer·
ence. The offset voltages of the two comparators will normally be
unequal so Vsm will generally not quite equal VSET2'
The input Impedances of the SETI and SET2 pins are
extremely high, and for most practical applications can be
ignored. The four outputs are open-drain MOS transistors, and
when ON behave as low rasistance switches to their respective
supply ralls. This minimizes errors In settlng·up the hysteresis,
and maxlmizas the output flexibility. The operating currents of the
bendgap reference and the comparators are around l00nA each.

Figure 5 shows the simplest connection of the ICl7665S for
thrashokl detection. From the graph (b), n can be sean that at low
input voltages OUT1 is OFF. or high, while OUll! is ON, or low. As
the input rises (e.g. at power-on) toward YNOM(usually the even·
tual operating voltage), OU1li! goes high on rasching VTR2' lithe
voltage rises above VNOM as much as VTR1' OUT1 goas low. The
equations giving VSET1 and VSET2 are from Figure 5 (a):
Rl1
R12
VSET1 = VIN (R ll + Ret) ; VSET2 • YIN (R12 + R2zl

PRECAUTIONS

and

Since the voltage to trip each comparator is nominally I:N, the
velue VIN for each trip point can be found from
(Rll + R21 )
(Rn + R21 )
VTRI • VSET1
z 1.3
for detector 1
Rll
Rll

Junction-isolated CMOS devices like the ICL7665S have an
inherent SCR or 4-layer PNPN structure distributed throughout
the die. Under certain circumstances, this can be triggered into
a potentially destructive high-current mode. This latchup can be
triggered by forwerd-biasing an input or output with respect to the
power supply, or by applying excessive supply voltages. In verylow current analog circuits, such as the ICl7665S, this SCR can
also be triggered by applying the input power supply extremely
rapidly ("instantaneously"), e.g. through a low impedance bat·
tery and an ONIOFF switch with short lead lengths. The rate-of·
rise of the supply voltage can exceed IOCNI,. in such a circuit. A
low-impedance capacitor (e.g. O.05"F disc ceramic) between the
II< and GrouND pins of the ICl7665S can be used 10 reduce the
rate-of·rise of the supply voltage in battery applications. In line·
operated systams, the rate-of-rise of the supply is limited by other
conSiderations, and is normally not a problem.
If the SET voltages must be applied before the supply voltage
V-, the Input current should be limited to less than O.5mA by
apprapriste extsmal rasistors, usually required for voltage selling
anyway. A Similar precaution should be taken with the outputs if
it is likely that they will be driven by other circuits 10 levels outside
the supplies at any time. See MOil for some other protection
ideas.

Either detector may be used alone, as well as both together, in
any 01 the circuits shown here.
When VIN is very closs 10 one of the trip voltages, normal varia·
tions and noise may cause it 10 wander back and forth across this
level, leading 10 erratic output ON and OFF conditions. The addi·
tion of hysteresis, making the trip points slightly different for rising
and lalling inputs, will avoid this condition.

THRESHOLD DETECTOR WITH
HYSTERESIS
Figure 6(a) shows how 10 sat up such hysteresis, while Figure
SIb) shows how the hysteresis around each trip point produces
swnchlng action at different points depending on whether VIN is
rising or falling (the arrows indicate direction of change). The
HYST outputs are basically switches which short out R31 or R32
When VIN Is above the raspective trip point. Thus if the input
voltage rises from a low value, the trip point will be controlled by
R1n , R2n , and R3n , until the trip point Is reached. As this valua is

VOUT

OFF

V,.

1(:1.,....
SET'

SET2

Au

All!
ON

"="

I

YTM

'lwOM

'hilI

YIN

f--D£TECTOR 2-+-DETECTOR 1 - - \

(a) Circuit Configuration
(b) l'l1lnsfer Characteristics
Figure 5: Simpia Threshold Detector
0090-6

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THiS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE": AU typIcs/ vs/UBS have be9n charsctsriz9d but arB not tested.

5·58

ICL7665S
APPLICATIONS

~.

OUT

1
I

!

1"'1
I

,...

A..

y'

....- HYST,

ON

I
I

HYST2t--

.l

~
I

I

"II'·.,.

ICL.....

>-

amI-

SET'

I

I

I
OUT!

aN.

...

I--......--.'y,,'-:!y"'

VUYIU

uNtJIMOVtilfiiii

1

A"

OF'

l

OUT2

~~~~~y,
•
~DETECTOR
2
DETECTOR 1

Ca) Circuit Configuration
(b) 1\'ansfer Characteristics
Figure 6: Thrashold Detector with Hysteresis

v,.

•

ICL78ISS

seT!

SEU

A..

A..

Figure 7: An Alternative Hysteresis Circuit
Table 1: Set-Point Equations
c) HYSTERESIS PER FIGURE 7

e) NO HYSTERESIS

VUl =
Over-Yoltege

X VSETl

VTRIP

b) HYSTERESIS PER FIGURE 6A

+

Rll

Rz1

+ R3l

VU1 • - - - : : - - - - X VSET1
All
aver-Voltage VTR1P
VLl

V U2 ..

+ R21

Rll

=

All
R12

X VSET1

+ R22 + R32
R12

X VSET2

Under-Voltege VTAIP

Under-Voltage VTRIP
R12

Vu ..

+ R22
A12

x Vsm
0090-7

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typical vsluss have been charscteriz8d but tuB not tested.

5-59

ICL7665S
THRESHOLD DETECTOR WITH
HYSTERESIS (cont.)
passed. the detector changes state. R3n is shorted out. and the
trip point becomes controlled by only R'n and R2n • a lower value.
The input will then have to fall to this new point to restore the initial
comparator state. but as soon as this occurs, the trip point will be
raised again.

some hysteresis to prevent erratic output ON and OFF conditions. The two outputs are connected in a wired OR configuration
with a pull up resistor to generate a power OK signal.

An alternative circuit for obtaining hysteresis is shown in Figure 7. In this configuration. the HYST pins put the extra resistor in
parallel with the upper setting resistor. The values of the resistors
differ. but the action is essentially the same. The governing equations are given in Table I. These ignore the effects of the resistance of the HYST outputa. but thess can normally be negiected
if the resistor vaiues are above about lOOkS2.

The ICL7865S can simultaneously monitor several supplies
when connected as shown in Figure 9. The resistors are chossn
such that the sum of the currents through R21A • R21B • and R31 is
equal to the current through Rll when the two input voltages are
at the desired low voltage detection point. The current through
Rll at this point is equal to 1.3V/R11 . The voltage etthe VSET input
depands on the voltage of both supplies being mon~ored. The
trip voltage of one supply while the other supply is at the nominal
voltage will be different than the trip voltage when both supplies
are below their nominal voltages.

Multiple Supply Fault Monitor

APPLICATIONS
Single Supply Fault Monitor

The other side of the ICL7665S can be used to detect the
abssnce of negative supplies. The trip points for OUT! depend
on both the negative supply voltages and the actual voltage of the
+5Vsupply.

Figure 8 shows an over/under-voitage fault monitor for a single
supply. The over-voltage trip point is centered around 5.5V and
the under-voltage trip point is centered around 4.5V. Both have

~:~

"...

",sr,

'"''

ICL7&65S

UNDER VOlTAGE
DETO-4-_--- OUTPUT

"'.4V

INPUT RISE ANO
FALL TIMESslOno

15V --~::::e"-.I

OV
0323-4
0323-5

Figure 3: Test Circuit

Typical Performance Characteristics
Rise and Fall Times vs CL

TR. TF vs Temperature

100 T 01. T 02 vs Temperature
50

/

90

/

..100
c

I

...

./

TRISE

d
.... 10
I

V

1

10

l!

f

50
40
30
20

10

100

02

so

1
FA

~;~~~V-

80
70

1000

10K

lOOK pF

VCC=15V

o

--

-55

I-"

o

..--

40

-

20

C

10

E

I

f-

~

-

J~t~

I--""

~

+25
·C

70

o

+125

-55

-

+25
·C

70

+125

loo~----+-----~--~-i

loo~----~------~~--~

c

~

lnF

o

I
E

I 10~----+----7~-----i

~

loo.A
100pF

CL-lnF
VcC·15V

No Load Icc vs Frequency

1

10pF

-

10

20kHz

3.0

V

T01':::

ICC vs Frequency
30

TRI? .........-

30

10nF

VCC=15V

lOOk

1M

FREQUENCY

10M

CL= 10pF
L-___......______" -____--'

10k

lOOk

1M

10M

FREQUENCY
0323-6

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIeS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but 8re not tested.

5-65

•

~

ICL7667

10

.......

S:!

Typical Performance Characteristics

(Continued)
Rise Time vs Vcc

Delay and Fall Times vs Vcc
50

50

40

40

I"-

""-

•f30

TF

w

>=20

CL= 10pF

CL=1nF

10

o

TR=To2

:IE

T01

~

I"-,

10

5

10

o

15

5

Vec

10

15

Vec
0323-13

0323-12

power disSipation of the ICL7667 at high frequencies. It can
be minimized by keeping the rise and fall times of the input
to the ICL7667 below 1fJ-S.

DETAILED DESCRIPTION
The ICL7667 is a dual high-power CMOS inverter whose
inputs respond to TIL levels while the outputs can swing as
high as 15V. Its high output current enables it to rapidly
charge and discharge the gate capacitance of power MOSFETs, minimizing the switching losses in switchmode power
supplies. Since the output stage is CMOS, the output will
swing to within millivolts of both ground and Vee without
any external parts or extra power supplies as required by
the DS0026/56 family. Although most speCifications are at
Vee = 15V, the propagation delays and specifications are
almost independent of Vee.
In addition to power MOS drivers, the ICL7667 is well
suited for other applications such as bus, control signal, and
clock drivers on large memory of microprocessor boards,
where the load capacitance is large and low propagation
delays are required. Other potential applications include peripheral power drivers and charge-pump voltage inverters.

APPLICATION NOTES
Although the ICL7667 is simply a dual level-shifting inverter, there are several areas to which careful attention must
be paid.

GROUNDING
Since the input and the high current output current paths
both include the ground pin, it is very important to minimize
any common impedance in the ground return. Since the
ICL7667 is an inverter, any common impedance will generate negative feedback, and will degrade the delay, rise and
fall times. Use a ground plane if possible, or use separate
ground returns for the input and output circuits. To minimize
any common inductance in the ground return, separate the
input and output circuit ground returns as close to the
ICL7667 as is possible.

INPUT STAGE

BYPASSING

The input stage is a large N-channel FET with a P-channel constant-current source. This circuit has a threshold of
about 1.5V, relatively independent of the Vee voltage. This
means that the inputs will be directly compatible with TIL
over the entire 4.5 - 15V Vee range. Being CMOS, the inputs draw less than 1fJ-A of current over the entire input
voltage range of ground to Vee. The quiescent current or no
load supply current of the ICL7667 is affected by the input
voltage, going to nearly zero when the inputs are at the 0
logic level and rising to 7mA maximum when both inputs are
at the 1 logic level. A small amount of hysteresis, about 50 100mV at the input, is generated by positive feedback
around the second stage.

The rapid charging and discharging of the load capacitance requires very high current spikes from the power supplies. A parallel combination of capacitors that has a low
impedance over a wide frequency range should be used. A
4.7 fJ-F tantalum capacitor in parallel with a low inductance
0.1 fJ-F capacitor is usually sufficient bypassing.

OUTPUT DAMPING
Ringing is a common problem in any circuit with very fast
rise or fall times. Such ringing will be aggravated by long
inductive lines with capacitive loads. Techniques to reduce
ringing include:
1)
Reduce inductance by making printed circuit board
fraces as short as possible.
2)
Reduce inductance by using a ground plane or by
closely coupling the output lines to their return
paths.
3)
Use a 10 to 300. reSistor in series with the output of
the ICL7667. Although this reduces ringing, it will
also slightly increase the rise and fall times.
4)
Use good bypassing techniques to prevent supply
voltage ringing.

OUTPUT STAGE
The ICL7667 output is a high-power CMOS inverter,
swinging between ground and Vee. At Vee = 15V, the output impedance of the inverter is typically 70.. The high peak
current capability of the ICL7667 enables it to drive a
1000pF load with a rise time of only 40ns. Because the
output stage impedance is very low, up to 300mA will flow
through the series N- and P-channel output devices (from
Vee to ground) during output transitions. This crossover current is responsible for a significant portion of the internal

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valfJ8s have b96n characterized but are not tested.

5-66

[fj]D~DIl.

ICL7667

n
I'"
....

is dissipating significant amounts of power. The very high
current output of the ICL7667 is able to rapidly overcome
this high capacitance and quickly turns the MOSFET fully
on or off.

POWER DISSIPATION
The power dissipation of the ICL7667 has three main
components:
1)
Input inverter current loss
2)
Output stage crossover current loss
3)
Output stage 12R power loss
The sum of the above must stay within the specified limits
for reliable operation.
As noted above, the input inverter current is input voltage
dependent, with an Icc of 0.2mA maximum with a logic 0
input and 6mA maximum with a logic 1 input.
The output stage crowbar current is the current that flows
through the series N- and P-channel devices that form the
output. This current, about 300mA, occurs only during output transitions. Caution: The inputs should never be allowed to remain between VIL and VIH since this could leave
the output stage in a high current mode, rapidly leading to
destruction of the device. If only one of the drivers is being
used, be sure to tie the unused input to a ground. NEVER
leave an input floating. The average supply current drawn
by the output stage is frequency dependent, as can be seen
in Icc vs. Frequency graph in the Typical Characteristics
Graphs.
The output stage 12R power dissipation is nothing more
than the product of the output current times the voltage
drop across the output device. In addition to the current
drawn by any resistive load, there will be an output current
due to the charging and discharging of the load capacitance. In most high frequency circuits the current used to
charge and discharge capacitance dominates, and the power dissipation is approximately
PAC= CVcc2f
Where C = Load Capacitance
f = Frequency
In cases where the load is a power MOSFET and the gate
drive requirements are described in terms of gate charge,
the ICL7667 power dissipation will be

l'1.

1
1

III 12
10

g!:;

I
~

>

.
o

VOO-/.
SOY f/

8¥JpF/ I/" f,{VOO=

f"'V

'/

II.
I
2

E

I-

Vl30pF

I
I
I

/212pF

o

43T50 J

I

•

-2

1 '11 Y
1/

IO-1A

14

GI
GI
....

4 6 • W

n

~ ~ ~ ~

00 - NAMO COULOMOS
0323-14

Figure 4: MOSFET Gate Dynamic
Characteristics

DIRECT DRIVE OF MOSFETs
Figure 6 shows interfaces between the ICL7667 and typical switching regulator ICs. Note that unlike the OS0026,
the ICL7667 does not need a dropping resistor and speedup capacitor between it and the regulator IC. The ICL7667,
with its high slew rate and high voltage drive can directly
drive the gate of the MOSFET. The 1527 IC is the same as
the 1525 IC, except that the outputs are inverted. This inversion is needed since ICL7667 is an inverting buffer.

TRANSFORMER COUPLED DRIVE OF
MOSFETs
Transformers are often used for isolation between the
logic and control section and the power section of a switching regulator. The high output drive capability of the
ICL7667 enables it to directly drive such transformers. Figure 6 shows a typical transformer coupled drive circuit.
PWM ICs with either active high or active low outputs can
be used in this circuit, since any inversion required can be
obtained by reversing the windings on the secondaries.

PAC=OGVCCf
Where OG = Charge required to switch the gate, in
Coulombs.
f = Frequency

BUFFERED DRIVERS FOR MULTIPLE
MOSFETs
In very high power applications which use a group of
MOSFETs in parallel, the input capacitance may be very
large and it can be difficult to charge and discharge quickly.
Figure 8 shows a circuit which works very well with very
large capacitance loads. When the input of the driver is
zero, 01 is held in conduction by the lower half of the
ICL7667 and 02 is clamped off by 01. When the input goes
positive, 01 is turned off and a current pulse is applied to
the gate of 02 by the upper half of the ICL7667 through the
transformer, T1. After about 20ns, T1 saturates and 02 is
held on by its own Cgs and the bootstrap circuit of C1, 01
and R1. This bootstrap circuit may not be needed at frequencies greater than 10kHz since the input capacitance of
02 discharges slowly.

POWER MOS DRIVER CIRCUITS
POWER MOS DRIVER REQUIREMENTS
Because it has a very high peak current output, the
ICL7667 excels at driving the gate of power MOS devices.
The high current output is important since it minimizes the
time the power MOS device is in the linear region. Figure 4
is a typical curve of charge vs. gate voltage for a power
MOSFET. The flat region is caused by the Miller capacitance, where the drain-to-gate capacitance is multiplied by
the voltage gain of the FET. This increase in capacitance
occurs while the power MOSFET is in the linear region and

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

5-67

•

:; ICL7667
CI)
.......
S:!

15V

+16SVOC

AI--+-~>o-~'~IR~ ~
SG1527 B

GNO

t-+-C>O-il-..... ~ IRF730
V-

0323-15

+15

0323-16

Figure 5: Direct Drive of MOSFET Gates

15V

+1SSY

'I'F
470
SG1524

EB

~
~

OY

'I'F

- - -......-+-+-- -1SSY
YOUT

0323-17

Figure 6: Transformer Coupled Drive Circuit

tNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not testBd

5-68

ICL7667
v+

v+

Cl-SV

SL

INPUT FROM
PWMIC

0323-18

Figure 7: Very High-Speed Driver

1·250kHz

tool

IN4001

+ -

......

- 4 H-+++-+- f

SQUARE WAVE IN ---I--r"';>

~

~ i~

-t>-

I(PH'

GND
0324-1

Vp> VS, P, SWITCH ON AND Pbar SWITCH ON
VS> Vp, P2 SWITCH ON AND Sbar SWITCH ON
Figure 1: Functional Diagram

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

302070-004

NOTE: All typical values have been charscten'zed but are not tested

5-71

•

~

.O~OIl

ICL7673

G

...!:!....

ABSOLUTE MAXIMUM RATINGS
Input Supply (Vp orVs) Voltage ........... -0.3 to +18V
Output Voltages Pbar and Sbar ......... '" - 0.3 to + 18V
Peak Current
InputVp(@Vp=5V)(note1) ................... 38mA
InputVs (@ Vs=3V) .......................... 30mA
Pbar or Sbar ................................. 150mA
Continuous Current
InputVp (@Vp=5V)(note1) ................... 38mA
Input Vs (@ Vs = 3V) .......................... 30mA
Pbar or Sbar .................................. 50mA

Package Dissipation ........................... 300mW
Linear Derating Factors
TO-99
PLASTIC
5.7mWI'C
6.1mWI'C
above 50·C
above 36·C
Operating Temperature Range:
ICL7673C ............................ O·C to + 70·C
ICL76731 .......................... -25·Cto + 85·C
Storage Temperature ................ -65·C to + 150·C
Lead Temperature (Soldering, 10sec) ............. 300·C
Note I. Derate above 2S'C by O.38mAI'C.

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Vp
Va

Vp

Vs

NC

Sbar

Pbar

GilD

IIC

GND
0324-3

0324-2

(Outline Dwg TV)
8-LEAD TO-99

(Outline Dwg BA)
8-LEADSOIC

0324-4

(Outline Dwg PAl
8-LEAD Minidip

Figure 2: Pin Configurations

ELECTRICAL CHARACTERISTICS
Symbol
Vp

Parameter
INPUT VOLTAGE

Vs

(TA = 25·C unless otherwise specified)
Test Conditions

Min

Typ

Max

Vs=Ovolts
Iload=OmA

2.5

-

15

Vp=Ovolts
Iload=OmA

Units

V

2.5

-

15

1+

QUIESCENT SUPPLY
CURRENT

Vp=Ovolts
Vs=3volts
Iload=OmA

-

1.5

5

JJ-A

Rds(on)PI

SWITCH RESISTANCE
P1
(NOTE 2)

Vp=5volts
Vs=3volts
I load = 15mA

-

8

15

0

@TA=85·C

-

16

-

Vp=9volts
Vs=3volts
I load = 15mA

-

6

-

0

Vp=12volts
Vs=3volts
I load = 15mA

-

5

-

0

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typ;cal values have been chsractsrlzsd but are not tested.

5-72

ICL7673
ELECTRICAL CHARACTERISTICS

(TA = 25'C unless otherwise specified) (Continued)

Symbol

Parameter

TC(Pl)

TEMPERATURE COEFFICIENT
OF SWITCH RESISTANCE P1

Vp=5volts
Vs=3volts
I load = 15mA

SWITCH RESISTANCE
P2
(NOTE 2)

Vp=Ovolts
Vs=3volts
Iload=1mA
@TA=85'C
Vp=Ovolts
Vs=5volts
Iload=1mA
Vp=Ovolts
Vs=9volts
Iload=1mA

Rds(on)P2

Test Conditions

Min

Typ

Max

Units

-

0.5

-

%rC

-

40

100

.n

-

60

-

-

26

-

.n

-

16

-

.n

TC(P2)

TEMPERATURE COEFFICIENT
OF SWITCH RESISTANCE P2

Vp=Ovolts
Vs=3volts
Iload=1mA

-

0.7

-

%rC

IL(PS)

LEAKAGE CURRENT
(Vpto VS)

Vp=5volts
Vs=3volts
Iload=10mA

-

0.01

20

nA

@TA=85'C

-

35

-

-

0.01

50

120

-

IL(SP)

LEAKAGE CURRENT
(VstoVp)

Vp=Ovolts
Vs=3volts
Iload=1mA
@TA=85'C

VOPbar

OPEN DRAIN OUTPUT
SATURATION VOLTAGES

VOSbar

Vp=5volts
Vs=3volts
I sink = 3.2mA
Iload=OmA

nA

-

85

400

@TA=85'C

120

-

Vp=9volts
Vs=3volts
I sink = 3.2mA
Iload=OmA

-

50

-

mV

Vp= 12 volts
Vs=3volts
I sink = 3.2mA
Iload=OmA

-

40

-

mV

-

150

400

mV

@TA=85'C

210

-

Vp=Ovolts
Vs=5volts
I sink = 3.2mA
Iload=OmA

-

85

-

mV

Vp=Ovolts
Vs=9volts
I sink = 3.2mA
Iload=OmA

-

50

-

mV

Vp=Ovolts
Vs=3volts
I sink = 3.2mA
Iload=OmA

mV

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATEO IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical val/J9S havs bssn chsrsctsrlzed but are not tsstsd.

5·73

::! ICL7673
CD

.......

2

ELECTRICAL CHARACTERISTICS
Symbol

(TA = 25°C unless otherwise specified) (Continued)

Parameter

Typ

Max

Units

-

50

500

nA

-

900

-

-

50

500

@TA=85°C

900

-

Vs=3volts
I sink=3.2mA
Iload=OmA

9d

Test Conditions

OUTPUT LEAKAGE
CURRENTS
OF Pbar AND Sbar

IL Pbar

Vp=Ovolts
Vs= 15 volts
Iload=OmA
@TA=85°C

Min

Vp= 15 volts
Vs=Ovolts
Iload=OmA

ILSbar

SWITCHOVER UNCERTAINTY
FOR COMPLETE SWITCHING
OF INPUTS AND OPEN
DRAIN OUTPUTS.

Vp - Vs

0

nA

V

NOTE 2. The minimum input to output voltage can be determined by multiplying the toad current by the switch resistance.

TYPICAL PERFORMANCE CHARACTERISTICS
ON-RESISTANCE SWITCH PI AS A FUNCTION
OF INPUT VOLTAGE Vp

ON-RESISTANCE SWITCH P2 AS A FUNCTION
OF INPUT VOLTAGEVs

100

100
ILOAD

en

15mA

:IE

iL
......

......,...

"- ........

e=

e=

:='"en

ILOAD - lmA

en

:IE

N

1\

10

:='"en

-

...

;;;

..
a:

CO

o

4

6

8

10 12 14

~ 1-0...

.-

r-

10

.
;;;

.....
a:
CO

16

4

INPUT VOLTAGE Vp IV)

6

10

INPUT VOLTAGE Vs
0324-6

0324-5

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ART\CLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE; All typical values have been characterized but 8re not tested.

5-74

ICL7673
TYPICAL PERFORMANCE CHARACTERISTICS

(Continued)
Pbar OR Sbar SATURATION VOLTAGE
AS A FUNCTION OF OUTPUT CURRENT

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

5

......a:en

~

...

0.0

Do.

::;;

'"cc
!:;

cc
0

...a:
~
.......a:a:

.
0

0.6

.

>

Vo=3V

0.4

...

....cc
....en
::>
....
::>
::>

::>

::
Do.
Do.

0.2

::>

40°C
+25°C+05i C-

'L

en

1/

V
o

4

6

10

12

7

1/
)

~~

40

00

120

140

100

0324-8

Is LEAKAGE CURRENT Vp to Vs AS
A FUNCTION OF INPUT VOLTAGE

DETAILED DESCRIPTION
As shown in the functional diagram (Figure I), the
ICL7673 includes a comparator which senses the input voltages Vp and Vs. The output of the comparator drives the
first inverter and the open-drain N-channel transistor Pbar'
The first inverter drives a large P-channel switch, PI, a second inverter, and another open-drain N-channel transistor,
Sbar. The second inverter drives another large P-channel
switch P2. The ICL7673, connected to a main and a backup
power supply, will connect the supply of greater potential to
its output. The circuit provides break-before-make switch
action as it switches from main to backup power in the
event of a main power supply failure. For proper operation,
inputs Vp and Vs must not be allowed to float, and, the
difference in the two supplies must be greater than 50 millivolts. The leakage current through the reverse biased parasitic diode of switch P2 is very low.

,,..
"O~~~Lr~

10nA

'oA

OUTPUT VOLTAGE
The output operating voltage range is 2.5 to 15 volts. The
insertion loss between either input and the output is a function of load current, input voltage, and temperature. This is
due to the P-channels being operated in their triode region,
and, the ON-resistance of the switches is a function of output voltage Yo. The ON-resistance of the P-channels have
positive temperature coefficients, and therefore as temperature increases the insertion loss also increases. At low load
currents the output voltage is nearly equal to the greater of
the two inputs. The maximum voltage drop across switch PI
or P2 is 0.5 volts, since above this voltage the body-drain
parasitic diode will become forward biased. Complete
switching of the inputs and open-drain outputs typically occurs in 50 microseconds.

OOOpA

10"
'pA 1111111

Vo=15V

0- ~~

0324-7

'

/

~7

OUTPUT CURRENT (mAl

SUPPLY VOLTAGE (VI

,"0,

V

/ /' V

1/

1/

J1/ ~ ::;..-'

o

14 16

II
)

I

2

Vo=12y

I

,

3

Do.

0

!Vo=9V

4

0

;::
cc
a:

Vo=5V

1111111
8

10

12

INPUT Vp VOLTS
0324-9

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITf\lESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

5-75

•

::! ICL7673

...
G

~

INPUT VOLTAGE
+& VOLT
PRIMARY
SUPPLY

The input operating voltage range for Vp or Vs is 2.5 to 15
volts. The input supply voltage (Vp or Vs) slew rate should
be limited to 2 volts per microsecond to avoid potential
harm to the circuit. In line-operated systems, the rate-of-rise
(or fall) of the supply is a function of power supply design.
For battery applications it may be necessary to use a capacitor between the input and ground pins to limit the rate-ofrise of the supply voltage. A low-impedance capacitor such
as a O.047""F disc ceramic can be used to reduce the rateof-rise.

8 Vp

_t"'-1r-O Vo
+5 VOLTS OR
+3 VOLTS

leL
7873
2

Pbar
STATUS
1li0ieATOR

8

LITHIUM _
BATTERYGila

0324-11

STATUS INDICATOR OUTPUTS

Figure 4: ICL7673 Battery Backup Circuit

The N-channel open drain output transistors can be used
to indicate which supply is connected, or can be used to
drive external PNP transistors to increase the power switching capability of the circuit. When using external PNP power
transistors, the output current is limited by the beta and
thermal characteristics of the power transistors. The application section details the use of external PNP transistors.

+5 VOLT
PRIMARY
SUPPLY

0-.,....___..,8 Vp
leL
7873

2

APPLICATIONS

·nOLT

Va

PRIMARY

+5 VOLT OR
+3 VOLT

Gila

Applications for the ICL7673 include volatile semiconductor memory storage systems, real-time clocks, timers, alarm
systems, and overI under voltage detectors. Other systems
requiring DC power when the master AC line supply fails
can also use the ICL7673.
A typical application, as illustrated in Figure 7, would be a
microprocessor system requiring a 5 volt supply. In the
event of primary supply failure, the system is powered
down, and a 3 volt battery is employed to maintain clock or
volatile memory data. The main and backup supplies are
connected to Vp and Vs, with the circuit output Vo supplying
power to the clock or volatile memory. The ICL7673 will
sense the main supply, when energized, to be of greater
potential than Vs and connect, via its internal MaS
switches, Vp to output Vo. The backup input, Vs will be disconnected internally. In the event of main supply failure, the
circuit will sense that the backup supply is now the greater
potential, disconnect Vp from Vo, and connect Vs.
Figure 8 illustrates the use of external PNP power transistors to increase the power switching capability of the circuit.
In this application the output current is limited by the beta
and thermal characteristics of the power transistors.
If hysteresis is desired for a particular low power application, positive feedback can be applied between the input Vp
and open drain output Sbar through a resistor as illustrated
in Figure 9. For high power applications hysteresis can be
applied as shown in Figure 10.
The ICL7673 can also be used as a clipping circuit as
illustrated in Figure 11. With high impedance loads the circuit output will be nearly equal to the greater of the two
input signals.

liCAD
BATTERY

---4----.. . .- .....

....

0-------"""'---0
0324-12

STACK

G.OO-......-

Vs Gila

Figure 5: Application Requiring Rechargeable
Battery Backup

STATUS
INDICATOR

-=-

Vo
+5 VOLTS
OR
+3.8 VOLTS

4

A typical discrete battery backup circuit is illustrated in
Figure 3. This approach requires several components, substantial printed circuit board space, and high labor cost. It
also consumes a fairly high quiescent current. The ICL7673
battery backup Circuit, illustrated in Figure 4, will often replace such discrete designs and offer much better performance, higher reliability, and lower system manufacturing
cost. A trickle charge system could be implemented with an
additional resistor and diode as shown in Figure 5. A complete low power AC to regulated DC system can be implemented using the ICL7673 and ICL7663S micropower voltage regulator as shown in Figure 6.

OC POWER

_

-O
0324-10

Figure 3: Discrete Battery Backup Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN typiCII1 V6futlS htIWI bt!Itm chtuact6rized but tu8 not fHitJd.

5-76

DlU~UI!..

ICL7673

c;
r'"

.....

GI

.....

Co»

Vp 8

ICL
7673

ICL
7663

BRIDGE
RECTIFIER

II

Vo

t

6

4

4

--BATTERY

STEPDDWN
TRANSFORMER

GND

STACK
0324-13

Figure 6: Power Supply for Low Power Portable AC to DC Systems

+5VOUo-----~--------------------~------------------_,

MAIII
POWER

POWER

MICROPROCESSOR

fAIL

~

DETECTOR

r---:-:!IC~L;""-"lVs

Va

INTERRUPT SIGNAL

7673
BACKUP

CIRCUIT

r=

GND

VOLATILE
RAM

0324-14

Figure 7: Typical Microprocessor Memory Application

Rf

• .101111 SUPPLY

"

Rs
MAIII

EXTERIIAL
EQUIPMENT

lip B

Va

SUPPLY
ICL
7673

3V
8ACKUP

SUPPLY

3

S

GND

0324-15

Figure 8: High Current Battery
Backup System
0324-16

Figure 9: Low Current Battery Backup
System With Hysteresis

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

5-77

~
o

......

ICL7673

2

~

PNP

~LPNP
RF

1

lis

Vp 8

MAIN
SUPPLY

1 t-NC
ICL
7673

Vs 2

::t BACKUP

T

4

6 P

EXTERNAL
EQUIPMENT

3 S

I

BATTERY

0324-17

Figure 10: High Current Backup System With Hysteresis

--0110

\/PO-lel
7673

Vso--

:~~--

lGND
~

0324-18

Figure 11: Clipping Circuits

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PAODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPAESS, IMPLIED OR STATUTORY, INCLUDING THE IMPliED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bssn characterized but are not tested.

5-78

ICL7675/ICL7676
Switched-Mode Power Supply
Controller Set
GENERAL DESCRIPTION

FEATURES

The ICL767517676 two-chip set provides the necessary
control circuitry for regulation of a single-ended, transformer
coupled, flyback type switching power supply. Specifically
designed to operate in this type of configuration, the Intersi!
controller chip set is trimmed to provide a regulated 5V output.
The two chips comprise a primary side controller and a
secondary side controller. Referring to Figure 3, the output
of the primary side controller drives the power MOSFET
switch in the primary leg of the transformer. The switch is
always turned off at a time corresponding to the falling edge
of the internal system clock at a frequency of 50kHz. Following an initial soft-start cycle, the switch is turned on at a
time corresponding to a pulse received from the secondary
side controller via a pulse transformer. The secondary side
controller detects the power switch turn-off at the secondary of the transformer and initiates a time-out sequence with
a duration directly proportional to the output voltage being
sensed. A pulse generated at the end of the time-out period
is fed back through the pulse transformer to the primary
side controller, thereby completing the control loop.
Power for the primary side controller may be taken from
the high voltage DC input to the power transformer via a
resistor which feeds current to the on-chip zener diode. This
eliminates the need for a separate power supply for the
controller. Excessive current in the power MOSFET switch
is detected at one end of a resistor in series with the source
of the MOSFET, forcing the primary side controller into the
soft-start mode.

• Output Voltage of 5V±5% Under All Conditions
• Simple Low Current Pulse Transformer Feedback
• Power Switch Over-Current Protection
•
•
•
•
•

ORDERING INFORMATION

r-v-:

CONTROL INPUT C 1

SHUT-DOWNC 2
CURRENT SENSE C 3
GNDC ..

Part
Number

Temperature
Range

Package

ICL7675CPA

O·Cto +70·C

8 Lead MINIDIP

ICL7675CJA

O·Cto +70·C

8 Lead CERDIP

ICL76751PA

-25·Cto +85·C

8 Lead MINIDIP

ICL76751JA

- 25·C to + 85·C

8 Lead CERDIP

ICL7675MJA

-55·Cto + 125·C

8 Lead CERDIP

ICL7676CPA

O·Cto +70·C

8 Lead MINIDIP

ICL7676CJA

O·Cto +70·C

8 Lead CERDIP

ICL76761PA

- 25·C to + 85·C

8 Lead MINIDIP

ICL76761JA

- 25·C to + 85·C

8 Lead CERDIP

ICL7676MJA

-55·C to + 125·C

8 Lead CERDIP

~ PVSENSE

8 P VZENER

v+C
SYNC. INPUT C 2

7 pv+
6 POUTPUT
5

Soft-Start
No Off-Chip Trimming Required
Minimum External Components
Low Supply Current
Output Duty Cycle-5% to 75%

7 PERROR AMP INPUT

OUTPUTC 3

6 PCOt.lP.2

GNDC ..

5 ~COt.lP.l

P SOFT-START

0095-2

0095-1

ICL7675
Package Outline (PA, JA)

ICL7676
Package Outline (PA, JA)
Figure 1: Pin Configurations

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESB FOR A PARTICULAR USE.
302072-001

NOTE: AU typical values havs been charsctBtfZod but.,. not tos/Sd.

5-79

•

:eCD
...

!...
...CD

i

ICL7675/ICL7676
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range
ICL767XC ............................. O·Cto +70·C
ICL767XI ........................... - 25·C to + 85·C
ICL767XM ......................... -55·Cto + 125·C
Continuous Total Power Dissipation (TA = 25·C)
CERDIP Package •..•...••.•..••...•.••..••.• 500 mW
Plastic Package ............................. 375 mW

ICL7675
Supply Voltage (V + to GND) ...•.•••.••.....••...... 16V
Voltage on any pin ...••..... (V + + 0.3) to (GND - 0.3) V
ICL7676
Supply Voltage (Vsense to GND) ..................... 16V
Voltage on any pin .••..•• (Vsense + 0.3) to (GND - 0.3) V

NOTE: Str9sses above thoBB //Sted under "AbsolutB MsxImum Ratings"
msy csuse p6ITTItUISI7t dBmsgs to ths dBvIce. Thsss are slleBB ratings only
and functlonsl optJI'Btion of ths dBvIce at thsss or any othsr conditions
above thoBB _tBd in ths optJI'Btionsl ssctIons of ths specifications Is not
implied. Exposure to sbsolu/9 msxJmum rating conditions for extended pst/odB msyaff9ct dBvIce reliability.

ICL7675 & ICL7676
Lead Temperature (Soldering, 10 sec) •..........•.. 300"C
Storage Temperature Range .....•.•.•• - 65·C to + 150"C

0095-3

ICL7675

0095-4

ICL7676

Figure 2: Functional Diagrams

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SAle.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTIHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING TlHE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE:AH typ/OS/ " " - _ _ _
not_

but.,.

5·80

ICL 7(67 5/ICL 7676
ICL7675
ELECTRICAL CHARACTERISTICS

Unless otherwise stated: Pins 1, 2, 3, and 4 are connected to GND;
Pin 7 is connected to V+; all other pins are open; V+ = 13.5V
Limits
Test
Parameter

Conditions

TA=+25°C

O"C + 10ll-s.
where T
= time delay
C
= delay capacitance
Iblas
= bias current
Voo/2 = voltage swing at comparator
10ll-s = typical system delay.
Now, C = T X Iblas/(Voo/2)
where Ibias = 10ll-A
Voo/2 = 2.9V
Therefore, Cl = 2.5 ms x 10Il-Al2.9V = 8.6 nF
C2 = 12 ms x 10Il-A/2.9V = 41.4 nF
C4 = 1.0 ms x 10Il-Al2.9V = 3.45 nF
A 20ll-F capacitor is recommended for the decoupling capacitor, C3. If the reservoir voltage goes to zero abruptly,
the load current of the part will be about 2 mA so it can
sustain power to the part for approximately 15 ms.

1
~

f

~
j

10

5

o

voo~~

Vooi4y.J

ill
200

600

......

R9,KJI.-

I

0084-15

Ij
z:

Figure 13: Blaa Current va. Blaa Reslator

1000
900

600
700

g

600

§

400
300
200
100
0

5DO

10

50

100

150

200

250

TIME DELAY- ps
0084-13

Figure 14: CapaCitance va. Time Delay

INTERSlL·S SOLE AND EXCLUSIVE WARRANlY 08UGATION WITH RESPECT TO THIS PROOUCT SHALL SE THAT STATED IN THE WARRANlY ARTICLE OF THE CONDITION OF SALE.
THE WARRANlY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typ/cBJ _

Irs... been cI/anICtOIiZed but.,. not _ _

5-99

P
...
......
G

•

......
...

ICL7677

U)

s;!

Secondary Side Power Fail Detector
The ICll677 power fail detector can be applied on the
secondary side as shown in Figure 15. Calculations for the
external components follow the same procedure used in the
primary side application.

NOTE: R10 is used only
when VOC1 > S.SV

0084-14

Figure 15: ICL7677 Power Fail Detector
Applied on the Secondary Side of Power Supply

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE Of THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU Of ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characteriz6d but are not tested.

5·100

ICL7680

+ 5V

to + 15V Voltage
ConverterIRegulator
GENERAL DESCRIPTION
• Dual Output Voltages of ± 15V ± 5% Under All
Conditions
• Output Voltage Externally Adjustable
• Input Current Sensing
• Three Frequency OSCillator, Selectable with a Single
Pin
• Sync Pin Available
• No Off·Chlp Trimming Required
• Minimum External Components
• Low Supply Current
• Built-In Latchup Protection

The Intersil ICL7680 voltage converter
essary control circuitry for independent re
n of both a
single-ended, boost type and boost-buck (inverting) type
switched-mode power supply. Specifically designed to operate in these two configurations, the ICL7680 is trimmed to
provide both a + 15V and -15V output with a + 5V input
voltage.
The internal circuitry is divided into two similar sections
sharing a common voltage reference and oscillator: one for
the boost stage and another for the inverting stage. Each
section contains an error amplifier, comparator, and output
logic which provide a standard pulse-width moelulated output drive to an external transistor switch. The boost section
senses the positive power supply output voltage via an internal thin film resistor divider which is trimmed for + 15V.
This voltage is user adjustable by aelding an external resistor. Similarly, the inverting section senses the negative power supply output voltage at the input of an inverting amplifier
that is trimmed for -15V.
The output logic provides the proper phase to drive an
N-channel MOSFET on the boost side and a P-channel
MOSFET on the inverting side. Although bipolar devices
could be used, the chip is optimized for MOSFET drive and
these devices will give higher efficiency.
For overcurrent protection, an internal comparator senses the voltage across an external resistor between the
chip input supply pin and the current sense pin, shutting the
circuit down for a voltage exceeding the limit.
Oscillator frequencies of 25 kHz, 50 kHz, or 100 kHz can
be set with the three-state frequency select pin connected
to GND left open, or connected to Vin respectively. The
sync pin can be overdriven, allowing the circuit to be run
from an external system clock.

ORDERING INFORMATION
Part Number

Temperature
Range

ICL7680CPE

O"Cto +70"C

Package
16 Pin Plastic
16 Pin CERDIP

ICL7680CJE
ICL7680lJE

-25"Cto + 85"C

16 Pin CERDIP

ICL7680MJE

-55"C to + 125"C

16 Pin CERDIP

COt.APARATOR 1C 1

\..../

16 PCOt.APARATOR 2

ERROR AMP 1C 2

15 t:JERROR AMP 2

+15V SENSEC 3

14 p-15V SENSE

CURRENT LIMIT C 4

13 t:J INV. OP At.AP

SHUT-DOWN C 5
VINC 6
GNDC 7
SWITCH OUT 1C 8

12 ;:JFREQ. SELECT
11 t:JSYNC
10 :JGND
9 t:J SWITCH OUT 2
0097-1

(Outline Dwg. PE, JE)
Figure 1: Pin Configuration

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

302090-001

NOTE: AN typical values have been characterized but are not tested.

5-101

ICL7680
+15V
SENSE

ERROR COMPARATOR CURRENT
AMP 1
1
Llt.l1T

SHUT-DOWN

R2

SYNC
FREQ.
SELECT
-15V
SENSE

INV.
OP-AMP
GND
15
ERROR-AMP

2
0097-2

Figure 2: Functional Diagram

-15V OUT
100mA

+15V OUT
100mA

C9

0097-3

Figure 3: System Schematic

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTiCULAR USE.

NOTE: All typical values haV8 besn characterized but are not tBSted.

5·102

D~DIL2...

ICL8211/ICL8212
Programmable Voltage Detector

I\)

.......

GENERAL DESCRIPTION

FEATURES

The Intersil ICLS211 /S212 are micropower bipolar monolithic integrated circuits intended primarily for precise voltage detection and generation. These circuits consist of an
accurate voltage reference, a comparator and a pair of output buffer/drivers.
Specifically, the ICLS211 provides a 7mA current limited
output sink when the voltage applied to the 'THRESHOLD'
terminal is less than 1.15 volts (the internal reference). The
ICLS212 requires a voltage in excess of 1.15 volts to switch
its output on (no current limit). Both devices have a low
current output (HYSTERESIS) which is switched on for input voltages in excess of 1.15V. The HYSTERESIS output
may be used to provide positive and noise free output
switching using a simple feedback network.

• High Accuracy Voltage Sensing and Generation:
Internal Reference 1_15 Volts Typical
• Low Sensitivity to Supply Voltage and Temperature
Variations
• Wide Supply Voltage Range: Typ_ 1.8 to 30 Volts
• Essentially Constant Supply Current Over Full Supply
Voltage Range
• Easy to Set Hysteresis Voltage Range
• Defined Output Current Limit -ICL8211
High Output Current Capability - ICL8212

APPLICATIONS
•
•
•
•
•
•

ORDERING INFORMATION
Part Number

Temperature Range

ICLS211CPA
ICLS211CBA
ICLS211CTY
ICLS211 MTY'
ICLS212CPA
ICLS212CBA
ICLS212CTY
ICLS212MTY*

O'Cto +70'C
O'C to + 70'C
O'C to+70'C
- 55'C to + 125'C
O'C to +70'C
O'C to +70'C
O'C to +70'C
-55'C to+ 125'C

Package
Slead Mini DIP
SleadSOIC
TO-99 Can
TO-99 Can
S lead Mini DIP
Slead SOIC
TO-99 Can
TO-99 Can

Low Voltage Sensor/lndlcator
High Voltage Sensor/lndlcator
Non Volatile Out-of-Voltage Range Sensor/lndlcator
Programmable Voltage Reference or Zener Diode
Series or Shunt Power Supply Regulator
Fixed Value Constant Current Source

• Add 18838 to part number if 8838 processing is required.
VOLTAGE REFERENCE COMPARATOR OUTPUT BUFFERS

;:~::~~~:;::~::;::::::'~r::~~A::::~'~

____8!ov+

HYSTERESIS

HlCO.

8 V+
7 N/C

HYSTERESIS 2

RS

THRESHOLD

4.5k11

1:-____+ ____...;2:..., HVST

N/C

OUTPOT 4

OUTPUT 2

5 GROUNO

4
GROUND

(ouIUn. dwg PAl

Q19

(oudin. dwg TV)
0328-2

N/C

THRESHOLO

V+

HYSTERESIS

N/C

THRESHOLD

N/C

OUTPUT

GROUND

x

~R6

0328-3

(outline dwg BA)

:,. 1001

50

t:

.. 25

TA = 25"C
I I I
V' =5V
OUTPUTj OPEN CIVT":::

e~125

TA = 25"C

e~ l25 t--OUTP~TS 0tENJIRCUIT-

-

ICJ212

",VTH - O.IV

I I
0

10
20
SUPPLY VOLTAGE

e

150

~125

/
II

.......

> 50

~
iil 25

}T-Or-

v

-55

0.0 1.0 1.1 '.15 1.2 2.0 4.0
THRESHOLD VOLTAGE - VTH
(IRREGULAR SCALE)

-

"VTH = 1.3V

ICLt2~2.l

175
o

30

V· =5V
t- OUTPUTS OrEN CIRCUIT

':100

II

:;)

SUPPLY CURRENT AS A
FUNCTION OF TEMPERATURE

-

I I

-25 +5 +35 +65 +85 +125
TEMPERATURE "C

0328-15

0328-17
0328-16

OUTPUT SATURATION CURRENTS
AS A FUNCTION OF
THRESHOLD VOLTAGE
3Or--rr-r-'-"--T"'""-,01

THRESHOLD VOLTAGE TO TURN
OUTPUTS "JUST ON" AS A
FUNCTION OF TEMPERATURE
1.17

I

l25"c\

1.1'
I

125t--+t-+--7'I"-4--+-~-si

r--

TA
V' =5V

5

-loB

I--

IHYS = -7pA. VHYS = ~

~ 15

-lsi

III:

20,

III:

U

? 10

~5
o

V

~

V
./

-20 0

-25iI!!

-30~

1.14 1.15 1.16 1.17 1.16 1.19 1.20
THRESHOLD VOLTAGE

:z:

V

'.14
-55

-

lo=1m.,Vo=5V

!;

/

'1

r-

L82

-25 +5 +35

ICLU12
~1.17

,/

~~1.18

./

9
I--

+15 +85

~THOUTPU

I::::

HYSTERESi
TA = 25" C OU~PUT

:~~::~.i.~~~: ~~.

1.13

+125

TEMPERATURE "C
0328-19

0328-18

THRESHOLD VOLTAGE TO TURN
OUTPUTS "JUST ON" AS A
FUNCTION OF SUPPLY VOLTAGE

1

tE

-

2) V-

2 3 4 5 10 20304050 100
SUPPLY VOLTAGE
0328-20

INTEASIL'$ SOLE AND EXCLUSiVe WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

5·106

IID~DIL

ICL8211/ICL8212
TYPICAL PERFORMANCE CHARACTERISTICS ICL8212 ONLY
OUTPUT SATURATION ~OLTAGE
AND CURRENT AS A FUNCTION
OF TEMPERATURE

OUTPUT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

I •. ~~~~ff-~1rt~
iB t--HHitil-tirtHH::It'H
20

1

10 t-+iI'l'I-t-t"tr-tttH
1.0

10.0 30.0 100.0

OUTPUT VOLTAGE

10

B-5 F

1-10

~ -15 f-'
~

t:

....
n
I;
N

..J.1

v~r~c~ V

N

iry"j
~':1'V

ICLI211

TA'; 25~C'

ri1~11

.1 IIW

~ -10.00
-1.00
-il.10
-il.10
HYSTERESIS OUTPUT VOLTAGE

0328-22

0328-21

....
..
N

(Continued)

HYSTERESIS OUTPUT CURRENT
AS A FUNCTION OF HYSTERESIS
OUTPUT VOLTAGE

1=
!-ao

!

0328-23

R3 kT
Thus 1.15=VeE (09 or 010)+-R x-ln7
2 q

DETAILED DESCRIPTION
The ICL8211 and ICL8212 use standard linear bipolar integrated circuit technology with high value thin film resistors
which define extremely low value currents.
Components 01 thru 010 and R1, R2 and R3 set up an
accurate voltage reference of 1.15 volts. This reference
voltage is close to the value of the bandgap voltage for
silicon and is highly stable with respect to both temperature
and supply voltage. The deviation from the bandgap voltage
is necessary due to the negative temperature coefficient of
the thin film resistors (- 5000 ppm per 'C).
Components 02 thru 09 and R2 make up a constant current source; 02 and Qg are identical and form a current
mirror. Os has 7 times the emitter area of 09, and due to the
current mirror, the collector currents of Os and 09 are
forced to be equal and it can be shown that the collector
current in Os and 09 is
1 kT
le(Osor09)=-R X-ln7
2 q
or approximately 1p.A at 25'C
Where k = Soltzman's constant
q = charge on an electron
and T = absolute temperature in 'K
Transistors Os, 06, and cq assure that the Vee of 03, 04,
and 09 remain constant with supply voltage variations. This
ensures a constant current supply free from variations.
The base current of 01 provides sufficient start up current
for the constant source; there being two stable states for
this type of circuit - either ON as defined above, or OFF if
no start up current is provided. Leakage current in the transistors is not sufficient in itself to guarantee reliable startup.
~ is matched to 03 and 02; 010 is matched to Og. Thus
the Ie and VeE of 010 are identical to that .of 09 or Os. To
generate the bandgap voltage, it is necessary to sum a voltage equal to the base emitter voltage of 09 to a voltage
proportional to the difference of the base emitter voltages
of two transistors Os and Og operating at two current densities.

which provides R3 =12 (approx.)
R2
The total supply current consumed by the voltage reference section is approximately 6p.A at room .temperature. A
voltage at the THRESHOLD input is compared to the reference 1.15 volts by the comparator consisting of transistors
011 thru 017. The outputs from the comparator are limited
to two diode drops less than V + or approximately 1.1 volts.
Thus the base current into the hysteresis output transistor is
limited to about 500nA and the collector current of 019 to
100p.A.
In the case of the ICL8211, 021 is proportioned to have
70 times the emitter area of 020 thereby limiting the output
current to apprOximately 7mA, whereas for the ICL8212 almost all the collector current of 019 is available for base
drive to 021, resulting in a maximum available collector current of the order of 30mA. It Is advisable to externally limit
this current to 25mA or less.

APPLICATIONS
The ICL8211 and ICL8212 are similar in many respects,
especially with regard to the setup of the input trip conditions and hysteresis circuitry. The following discussion describes both devices, and where differences occur they are
clearly noted.

General Information
THRESHOLD INPUT CONSIDERATIONS
Although any voltage between -5V·and V+ may be applied to the THRESHOLD terminal, it is recommended that
the THRESHOLD voltage does not exceed about + 6 volts
since above that voltage the threshold input current increases sharply. Also, prolonged operation above this voltage will
lead to degradation of device characteristics.

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESSi IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical tIIl/uBs haVtl been t:haraotfIrIzed but III'tI nqt testsd.

5-107

•

~

&\II
CD

ICL8211/ICL8212

...

..

A principal application of the ICLB211 is voltage level detection, and for that reason the OUTPUT current has been
limited to typically 7mA to permit direct drive of an LED
connected to the positive supply without a series current
limiting resistor.
On the other hand the ICLB212 is intended for applications such as programmable zener references, and voltage
regulators where output currents well in excess of 7mA are
desirable. Therefore, the output of the ICLB212 is not current limited, and if the output is used to drive an LED, a
series current limiting resistor must be used.
In most applications an input resistor divider network may
be used to generate the 1.15V required for VTH. For high
accuracy, currents as large as 50,...A may be used, however
for those applications where current limiting may be desirable, (such as when operating from a battery) currents as
low as 6,...A may be considered without a great loss of accuracy. 6,...A represents a practical minimum, since it is about
this level where the device's own input current becomes a
significant percentage of that flowing in the divider network.

U

:::::.
&\II
CD

...

Y'

INPUT
VOLTAGE

(Y'MUST
EQUAL OR
EXCEED 1.'
YOLTS)

(AECO-.mm RANGE ~ TO

+5YOLTS)

g

YrHo-+-{lI

Rll

Yo

I

YHVS'

Yo,

I

Yo,

0328-24

Y~~~~~E 1.15V'-j'--\-_ _+-\_ _- j__'rV'H

V·
OV

v'

I I
I
-u--u--------LE
1

INPUT

ICL8211 OUTPUT

OV

ICL8212 OUTPUT

0328-25

Figure 3: Voltage Level Detection
R,

The outputs change states with an input THRESHOLD
voltage of approximately 1.15 volts. Input and output waveforms are shown in Figure 3 for a simple 1.15 volt level
detector.
The HYSTERESIS output is a low current output and is
intended primarily for input threshold voltage hysteresis applications. If this output is used for other applications it is
suggested that output currents be limited to lO,...A or less.
The regular OUTPUT's from either the ICLB211 or
ICLB212 may be used to drive most of the common logic
families such as TTL or C-MOS using a single pullup resistor. There is a guaranteed TTL fanout of 2 for the ICLB211
and 4 for the ICLB212.

0328-27

Figure 5: Input Resistor
Network Considerations
Case 1. High accuracy required, current in resistor network
unimportant Set 1= 50,...A for VTH = 1.15 volts
:.Rl .... 20kO.
Case 2. Good accuracy required, current in resistor network
important Set 1=7.5,...A for VTH=1.15 volts
:.Rl .... 150kO.

SETUP PROCEDURES FOR VOLTAGE LEVEL
DETECTION

y'

Case 1. Simple voltage detection - no hysteresis
Unless an input voltage of approximately 1.15 volts is to
be detected, resistor networks will be used to divide or multiply the unknown voltage to be sensed. Figure 7 shows
procedures on how to set up resistor networks to detect
INPUT VOLTAGES of any magnitude and polarity.
For supply voltage level detection applications the input
resistor network is connected across the supply terminals
as shown in Figure B.
Conditions for correct operation of OUTPUT (terminal #4).
1.
ICLB211
1.BV:o:V+ :O:30V
2.
ICLB212
O:O:V+ :O:30V

Y'H --------..:'-1

0328-26

Figure 4: Output Logic Interface

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

5-10B

IIlD~DI!.

ICL8211/ICL8212

n
reID

hysteresis is to provide positive feedback to the input trip
point such that there is a voltage difference between the
input voltage necessary to turn the outputs ON and OFF.
The advantage of hysteresis is especially apparent in
electrically noisy environments where simple but positive
voltage detection is required. Hysteresis circuitry, however,
is not limited to applications requiring better noise performance but may be expanded into highly complex systems
with multiple voltage level detection and memory applications - refer to specific applications section.
There are two simple methods to apply hysteresis to a
circuit for use in supply voltage level detection. These are
shown in Figure 9.
The circuit (a) of Figure 9 requires that the full current
flowing in the resistor network be sourced by the HYSTERESIS output, whereas for circuit (b) the current to be
sourced by the HYSTERESIS output will be a function of the
ratio of the two trip points and their values. For low values
of hysteresis, circuit (b) is to be preferred due to the offset
voltage of the hysteresis output transistor.
A third way to obtain hysteresis (ICL8211 only) is to connect a resistor between the OUTPUT and the THRESHOLD
terminals thereby reducing the total external reSistance between the THRESHOLD and GROUND when the OUTPUT
is switched on.

INPUT
VOLTAGE

0328-28

Input voltage to change the output states
= (Rl + R2) x 1.15 volts
Rl

Figure 6: Range of Input Voltage
Greater Than + 1.15 Volts

Practical Applications
a)
Low Voltage Battery Indicator
This application is particularly suitable for portable or remote operated equipment which requires an indication of a
depleted or discharged battery. The quiescent current taken
by the system will be typically 35fLA which will increase to
7mA when the lamp is turned on. R3 will provide hysteresis
if required.
b)
INon-Volatile I Low Voltage Detector
In this application the high trip voltage VTR2 is set to be
above the normal supply voltage range. On power up the
initial condition is A. On momentarily closing switch S1 the
operating point changes to B and will remain at B until the
supply voltage drops below VTR1, at which time the output
will revert to condition A. Note that state A is always retained if the supply voltage is reduced below VTRI (even to
zero volts) and then raised back to VNOM.
c)
(Non-volatile) Power Supply Malfunction Recorder
In many systems a transient or an extended abnormal (or
absence of a) supply voltage will cause a system failure.
This failure may take the form of information lost in a volatile semiconductor memory stack, a loss of time in a timer or
even possible irreversible damage to components if a supply voltage exceeds a certain value.
It is, therefore, necessary to be able to detect and store
the fact that an out-of-operatlng range supply voltage
condition has occurred, even in the case where a supply
voltage may have dropped to zero. Upon power up to the
normal operating voltage this record must have been retained and easily interrogated. This could be important in
the case of a transient power failure due to a faulty component or intermittent power supply, open circuit, etc., where
direct observation of the failure is difficult.

0328-29

Range of input voltage less than + 1.15 volts.
Input voltage to change the output states
= (Rl + R2) X 1. 15R2VREF
Rl
Rl

Figure 7: Input Resistor Network
Setup Procedures

~------------~--~v+

INPUT VOLTAGE
OR SUPPLY VOLTAGE

~-----------+-ovo

0328-30

Figure 8: Combined Input
and Supply Voltages
Case 2. Use of the HYSTERESIS function
The disadvantage of the simple detection circuits is that
there is a small but finite input range where the outputs are
neither totally 'ON' nor totally 'OFF'. The principle behind

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL 'OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTies OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but Bre not tested.

5-109

....
........
II)

n
reID

II)

....
II)

.o~ou.

ICL8211/ICL8212
r-.,.-----_-ov·

~----------~~VO

0328-34
0328-31
~------~~--~v·

Low trip voltage
(R1 +R2X1.15
]
VTR1 = [
R1)
+ 0.1 volts
High trip voltage

RL

=(R1+ R2+ R3}XI15vOlts
V
TR2
R1
.
'-----------_+.....- 0 OUTPUT

r--------4~v·

0328-35

Figure 10: Low Voltage Battery Indicator

E

~----------_+--oVO

"OFF

i

0328-32

Low trip voltage

~

RaRs
]
1·
VTR1= [ (Ra+Rs) +RP X Rp xl.15volts

~

High trip voltage

ON

B

~

t;

]II-~I

- : :A ':--- OFF§
VTR.1l

: VNOM ; VTR2

S:!

SUPPlY_
VOLTAGE

(Rp+Ra)

0328-36

VTR2=~Xl.15vOlts

Figure 11: Low Voltage Detector
and Memory

I!!

OJ

!c

~

"OFF

--rr--

o
~_

_..

~

O

ON

\

:----

ON

r------.~~------~~r

t;

i

lie

OFF~

:VTR1
:YTR2
L---~s~U~PPl~~Y~__
~~~

a

VOLTAGE

0328-33

Figure 9: Two alternative voltage
detection circuits employing
hysteresis to provide pairs of
well defined trip voltages.

0326-37

Figure 12: Schematic of Recorder

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

5-110

ICL8211/ICL8212
A simple circuit to record an out of range voltage excursion may be constructed using an ICL8211, an ICL8212
plus a few resistors. This circuit will operate to 30 volts without exceeding the maximum ratings of the I.C.'s. The two
voltage limits defining the in range supply voltage may be
set to any value between 2.0 and 30 volts.
OUTPUT ICW11
ICW12 DISCONNECTED

OUTPUT ICL8212

OUTPUT ICWll
AS PER FIGURE.
I = 25.A (ICL8212)
1= 130.A (ICL8211)

:VNOM

.VNOM

OFF-t;il

ON

I

:

:

I

I

I

I
I

IV,I 'V2IY
IUPPL Y VOLTAGE

SUPPLY VOLTAGE

0328-39

Figure 14: Constant Current
Source Applications

0328-38

Figure 13: Output States of the
ICL8211 and ICL8212 as a
Function of the Supply Voltage

6
TA = ZSOC

Referring to Figure 12, the ICL8212 is used to detect a
voltage, V2, which is the upper voltage limit to the operating
voltage range. The ICL8211 detects the lower voltage limit
of the operating voltage range, V,. Hysteresis is used with
the ICL8211 so that the output can be stable in either state
over the operating voltage range V, to V2 by making Vathe upper trip point of the ICL8211 much higher in voltage
than V2.
The output of the ICL8212 is used to force the output of
the ICL8211 into the ON state above V2. Thus there is no
value of the supply voltage that will result in the output of
the ICL8211 changing from the ON state to the OFF state.
This may be achieved only by shorting out Ra for values of
supply voltage between V1 and V2.
d)
Constant Current Sources
The ICL8212 may be used as a constant current source
of value of approximately 25p.A by connecting the
THRESHOLD terminal to GROUND. Similarly the ICL8211
will provide a 130p.A constant current source. The equivalent parallel resistance is in the tens of megohms over the
supply voltage range of 2 to 30 volts. These constant current sources may be used to provide biasing for various
circuitry including differential amplifiers and comparators.
See Typical Operating Characteristics for complete information.
e)
Zener or Precision Voltage Reference
The ICL8212 may be used to simulate a zener diode by
connecting the OUTPUT terminal to the Vz output and using a resistor network connected to the THRESHOLD terminal to program the zener voltage
(R,+ R2)
Vzener=---X 1.15 volts.

vIs

:lv-

~;,~

lli
o
0.01

5001c

r-

+

R,

- 5.F ~

YTH-

OUT

1501<

ftt·i"*"1

I

0.1

1.0

...... t

R.

ill
ffi

I

1111

I!II
10

100

SUPPLY CURRENT - I (ma)
0328-40

Figure 15: Programmable Zener
or Voltage Reference

V·o--------......---..:

Vour = R.:, R, x 1.15 VOLTS
0328-41

R,

Figure 16: Simple Voltage Regulator

Since there is no internal compensation in the ICL8212 it
is necessary to use a large capacitor across the output to
prevent oscillation.
Zener voltages from 2 to 30 volts may be programmed
and typical impedance values between 300p.A and 25mA
will range from 4 to 7n. The knee is sharper and occurs at a
significantly lower current than other similar devices available.

f)
Precision Voltage Regulators
The ICL8212 may be used as the controller for a highly
stable series voltage regulator. The output voltage is Simply
programmed, using a resistor divider network R, and R2.
Two capacitors C, and C2 are required to ensure stability
since the ICL8212 is uncompensated internally.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPREss, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valuss have been chsract9l'1z8d but Sf9 not tsstsd.

5-111

~
(\I

IIJD~DI!..

ICL8211/ICL8212

...
CD

()

any commercial regulator. Applications would therefore include battery operated equipment especially those operating at low voltages.
g)
High supply voltage dump circuit
In many circuit applications it is desirable to remove the
power supply in the case of high voltage overload. For circuits consuming less than 5mA this may be achieved using
an ICL8211 driving the load directly. For higher load currents it is necessary to use an external pnp transistor or
darlington pair driven by the output of the ICL8211. Resistors Rl and R2 set up the disconnect voltage and R3 provides optional voltage hysteresis if so desired.
h) Frequency limit detectors
Simple frequency limit detectors providing a GO/NO-GO
output for use with varying amplitude input signals may be
conveniently implemented with the ICL8211/8212. In the
application shown, the first ICL8212 is used as a zero crossing detector. The output circuit consisting of R3, R4 and C2
results in a slow output positive ramp. The negative range is
much faster than the positive range. Rs and Rs provide hysteresis so that under all circumstances the second ICL8212
is turned on for sufficient time to discharge C3. The time
constant of R7 C3 is much greater than R4 C2. Depending
upon the desired output polarities for low and high input
frequencies, either an ICL8211 or an ICL8212 may be used
as the output driver.
This circuit is sensitive to supply voltage variations and
should be used with a stabilized power supply. At very low
frequencies the output will switch at the input frequency.

v+o--.--------------~----~

::::.
.,.

.,.
(\I

r------

...
CD

:
R3
L·"v"'v"\r

~

v-~4-----------~
8

0328-46
v+~~--------------~~---,

,..-----:

R3

L_,V'v"v'

b
0328-42

Figure 17: High Voltage Dump Circuits
This regulator may be used with lower input voltages than
most other commercially available regulators and also consumes less power for a given output control current than

V''-~------~--~~r-----------------~r---------~~

C,

Re

INPUT ";H--.--£I1

'-------t-+--<>OUTPUT
TI",E CONSTANT R3 C2 « R4 C2 " R7 C3
VARY RI FOR OPTION ZERO CROSSING DETECTION
VARY R4 to SET DETECTION FREQUENCY
--1INDETER ...,NATE
BELOW

INPUT

...

!c

OFF

1--

1.15V
A

i~

1-;:)

0

1.15V
B

ON

'0

r

~

ON ...

!c

i~

I
I
I

(

to

---

OFF 0

FREQUENCY_

0328-43

Figure 18: Frequency Limit Detector
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

5-112

ICL8211/ICL8212
i)
Switch bounce filter
Single pole single throw (SPST) switches are less costly
and more available than single pole double throw (SPDT)
switches. SPST switches range from push button and slide
types to calculator keyboards. A major problem with the use
of switches is the mechanical bounce of the electrical contacts on closure. Contact bounce times can range from a
fraction of a millisecond to several tens of milliseconds depending upon the switch type. During this contact bounce
time the switch may make and break contact several times.
The circuit shown in Figure 19 provides a rapid charge up of
Cl to close to the positive supply voltage (V +) on a switch
closure and a corresponding slow discharge of Cl on a
switch break. By proportioning the time constant of Rl Cl to
approximately the manufacturer's bounce time the output
as terminal #4 of the ICL8211 18212 will be a single transition of state per desired switch closure.
j)
Low voltage power disconnector
There are some classes of circuits that require the power
supply to be disconnected if the power supply voltage falls
below a certain value. As an example, the National LM199
precision reference has an on chip heater which malfunctions with supply voltages below 9 volts causing an excessive device temperature. The ICL8212 may be used to detect a power supply voltage of 9 volts and turn the power
supply off to the LM 199 heater section below that voltage.
For further applications, see A027 "Power Supply Design
using the ICL8211 and ICL8212" by D. Watson.

~--------~~~yo

0328-44

Figure 19: Switch Bounce Filter

OUTPUT

REFERENCE

0328-45

Figure 20: Low Voltage Power
Supply Disconnect

INTERSIL'S SOLE ANO EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical vs/ues have been charact9rizsd but are not tssted.

5-113

Section 6 -

Special Analog
AD590 ................. 6-1
ICL8013 ............... 6-12
ICL8038 ............... 6-21
ICL8048 ............... 6-30
ICL8049 ............... 6-30
ICL8069 ............... 6-39

U~UlLg

AD590
2-Wire Current Output
Temperature Transducer

U)

o

GENERAL DESCRIPTION

FEATURES

The AD590 is an integrated-circuit temperature transducer which produces an output current proportional to absolute temperature. The device acts as a high impedance constant current regulator, passing 1".ArK for supply voltages
between +4V and +30V. Laser trimming of the chip's thin
film resistors is used to calibrate the device to 298.2".A output at 298.2°K (+ 25°C).
The AD590 should be used in any temperature-sensing
application between - 55°C and + 150°C (O°C and 70°C for
TO-92) in which conventional electrical temperature sensors are currently employed. The inherent low cost of a
monolithic integrated circuit combined with the elimination
of support circuitry makes the AD590 an attractive alternative for many temperature measurement situations. Linearization circuitry, precision voltage amplifiers, resistancemeasuring circuitry and cold-junction compensation are not
needed in applying the AD590. In the simplest application, a
resistor, a power source and any voltmeter can be used to
measure temperature.
In addition to temperature measurement, applications include temperature compensation or correction of discrete
components, and biasing proportional to absolute temperature. The AD590 is available in chip form making it suitable
for hybrid circuits and fast temperature measurements in
protected environments.
The AD590 is particularly useful in remote sensing applications. The device is insensitive to voltage drops over long
lines due to its high-impedance current output. Any weil-insulated twisted pair is sufficient for operation hundreds of
feet from the receiving circuitry. The output characteristics
also make the AD590 easy to multiplex: the current can be
switched by a CMOS multiplexer or the supply voltage can
be switched by a logic gate output.

•
•
•
•

Linear Current Output: 1".AI'K
Wide Range: - 55°C to + 150°C
Two-Terminal Device: Voltage In/Current Out
Laser Trimmed to ± O.soC Calibration Accuracy
(AD590M)
• Excellent Linearity: ± O.5°C Over Full Range
(AD590M)
• Wide Power Supply Range: + 4V to + 30V
• Sensor Isolation From Case
• Low Cost

ORDERING INFORMATION
Non-Linearity
eC)

Part
Number

Temperature
Range

Package

±3.0
± 1.5

AD590lH
AD590JH

- 55°C to + 150°C
- 55°C to + 150°C

TO-52
TO-52

CASE
0318-2

0318-1

Figure 1: Functional Diagram

Figure 2: Pin Configurations

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABiliTY AND FITNESS FOR A PARTICULAR USE.
300106-002

NOTE: All typical valuss have be8n characterized but are not tested.

6-1

5:

AD590

~

ABSOLUTE MAXIMUM RATINGS

II)

Forward Voltage (V+ to V-I
Reverse Voltage (V+ to V-I
Breakdown Voltage (Case to
Storage Temperature Range

(TA = + 25·C unless otherwise noted)

..................... +44V
..................... -20V
V+ or V-I ......•... ±200V
.......... -65·C to + 150"C

Rated Performance Temperature Range
TO-52 ........................... -55·C to + 150·C
Lead Temperature (Soldering, 10sec) ........... +300·C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanant damage to the device. Thase are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specificatkJns is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect davice reliability.

SPECIFICATIONS

(Typical values at TA = + 25·C, V+ = 5V unless otherwise noted)

Characteristics
Output
Nominal Output Current

@

+ 125·C(298.2"K)

Nominal Temperature Coefficient

AD5901

AD590J

Units

298.2

298.2

",A

1.0

1.0

",ArK

Calibration Error @ + 25·C (Notes 1, 5)

±10.0 max

±5.0max

·C

Absolute Error ( - 55·C to + 150·C) (Note 7)
Without External Calibration Adjustment
With External Calibration Adjustment

±20.0 max
±5.8 max

±10.Omax
±3.0max

·C
·C

Non-Linearity (Note 6)

±3.0 max

±1.5max

·C

Repeatability (Notes 2, 6)

±0.1 max

±0.1 max

·C

Long Term Drift (Notes 3, 6)

±0.1 max

±0.1 max

·C/month

Current Noise

40

40

pAlv'Hz

Power Supply Rejection:
+4V

298.2

l

z

'"'"

u

.....5

l/

!;

218

Figure 10: Average-temperature sensing
scheme. The sum of the AD590 currents appears
across R, which is chosen by the formula:
10k!}
R=-n being the numb~r of sensors.

"

/

/

218°K 298.zaK

423°K

(-55'C) (+2S'C) (+15O"C)
TEMPERATURE
0318-12

Figure 8: Simple connection. Output Is
proportional to absolute temperature.

+15V

10kO
0.1%

0318-13

Figure 9: Lowest-temperature sensing scheme.
Available current is that of the "coldest" sensor.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

6-6

AD590
.'5Vo-1---·------1---------------.---~~----~

..,
I

I~~~~

+

I

-'
R
0.1%

c

0318-15

Figure 11: Single-setpoint temperature controller. The AD590 produces a temperature-dependent voltage
across R (C Is for filtering noise). Setting R2 produces a scale-zero voltage. For the Celsius scale, make
R = 1kfi and VZERO = 0.273 volts. For Fahrenheit, R = 1.8kfi and VZERO = 0.460 volts.
ROW

SElECT
,...........,

ENA8t.E

•

(OPTIONAl.)

•

4 •

•

1

• 2 1"6108
a.CHANNEl

-f~~~~~~~~~~~~~~f-~~~7 3

MUX

12 4

".
I••

A05IO(84)

'''0

0.1%

!

VOUT

I

t

0318-16

Figure 12: Multiplexing sensors. If shorted sensors are possible, a series resistor in series
with the D line will limit the current (shown as R, above: only one is needed).
A six-bit digital word will select one of 64 sensors.

INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characteriz8d but 8te not tested.

6·7

~

.D~Dn.

AD590

II)

~
r - - -.....- - - - - - - - - O +15Y
1k!l
ZERO SET

«.2kO
1OmYI"C

118ka

101eO
0.1%

1000

2OkO
FULL·SCALE
ADJUST

-1
1OkO

2.7315Y

_I

0318-17

Figure 13: Centigrade thermometer (O"C -100·C) . the ultra-low bias current of the ICL7611 allows the use of
large-value gain-resistors, keeping meter-current error under 112%, and therefore saving the expense of an
extra meter-driving amplifier.

Y+
VoUT=(TZ·T,)(1OmVr'C)

(8Ymln)

Y-

0318-18

Figure 14: Differential thermometer. The SOk!} pot trims offsets in the devices whether internal or external,
so it can be used to set the size of the difference interval. This also makes it useful for liquid-level detection
(where there will be a measurable temperature difference).

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AI! typical values have been characterized but Sf'8 not tested.

6-8

AD590
Y+

----- --,
I

--

t

,

I
I
I

TC=
4O,N,.K

TYPEK

+

L..J

Y+
+
YOUT

f

R1
452111

Y2 = 10.98 40.211

l

0318-19

Figure 15: Cold-Junction compensation for type K thermocouple. The reference junction(s) should be in
close thermal contact with the AD590 case. Y+ must be at least 4Y, while ICLB069 current should be set at
1mA-2mA. Calibration does not require shorting or removal of the thermocouple: set R1 for Y2= 10.98mY.
If very precise measurements are needed, adjust R2 to the exact Seebeck coefficient for the thermocouple
used (measured or from table) note Y1. and set R1 to buck out this voltage (I.e., set Y2=Yd. For other
thermocouple types, adjust values to the appropriate Seebeck coefficient.

:$- p=:x--v-v----:,

-

SOO"A+
+

....

'--_

0318-20

Figure 16: Simplest thermometer. Meter displays current output directly in degrees Kelvin. Using the
AD590M, sensor output Is within ± 1.7 degrees over the entire range, and less than ± 1 degree over the
greater part of it.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANnES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical vsIuBS have been chstSctfJrfzBd but Sf6 not tssted.

6-9

~
10

AD590

~

I 'F
l 'C

Rs

RS

R

v+

9.00

4.02

2.0

12.4

10.0

o

5.00

4.02

2.0

5.11

5.0

11.8

5

L

Rn = 28kO nominal

n=1

All values in kO
The ICL7106 has a VIN span of ±2.0V, and a VCM range of (V+ -0.5)
Volts to 01- + 1) Volts; R is scaled to bring each range within VCM
while not exceeding VIN. VREF for both scales is 500mV. Maximum
reading on the Celsius range is 199.9"C, limited by the (Short-term)
maximum allowable sensor temperature. Maximum reading on the
Fahrenheit range is 199.9°F (93.3"C), limited by the number of display
digits. See note next page.

R
ICL7'06

~

r---v

~ ~ INHI

123.B

R.
COMMON
t - - - - - - 4 I N LO

v0318-2.

Figure 17: Basic digital thermometer, Celsius and Fahrenheit scales

v+

~

. L

7.5k.n •

RE~HI

2.26 k.n

:~
ADJ

5k.n

REFLO
ICL7106

15k.n

~

' - - - COM

INHI

-,,-, -,,
-",
--

1.00 k.n

+

~ AD590

INLO

"--r--

v-

0318-22

Figure 18: Basic digital thermometer, Kelvin scale. The Kelvin scale version reads from 0 to 1999'K
theoretically, and from 223'K to 473'K actually. The 2.2SkO resistor brings the input within the ICL710S VCM
range: 2 general-purpose silicon diodes or an LED may be substituted.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY" INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valUBS have been characterized but are not tested.

6-10

AD590
v+

121kO

I

7.5IcQ

SCALE r:R::!E:::F..........,

--

ZERO
J

7

.}DJ

1.r:~ ~

HI
REF LO

SkO

ICL7106

l5kO

lkO,O.I%

~3071

'-----i IN HI
~------------------iINLO

-v0318-23

Figure 19: Basic digital thermometer, Kelvin scale with zero adjust. This circuit allows "zero adjustment" as
well as slope adjustment. The ICL8069 brings the input within the common-mode range, while the 5kO pots
trim any offset at 218'K (-55'C), and set the scale factor.
Note on Figure 17, Figure 18 and Figure 19: Since ail 3
scales have narrow VIN spans, some optimization of
ICL7106 components can be made to lower noise and pre·
serve CMR. The table below shows the suggested values.
Similar scaling can be used with the ICL7126/36.

Scale

VIN Range (V)

RINT(kO)

CAZ(fLF)

K
C
F

0.223 to 0.473
-0.25 to +1.0
-0.29 to +0.996

220
220
220

0.47
0.1
0.1

For ail:
CREF = 0.1 fLF
CINT = 0.22fLF

COSC=100pF
ROSC=100kO

lNTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE; All typical valU9S have bgen characterized but are not tested.

6-11

III

D~DIb

; ICL8013

(,)_~ Four Quadrant

Analog Multiplier
GENERAL DESCRIPTION

FEATURES

The ICL8013 is a four quadrant analog multiplier whose
output is proportional to the algebraic product of two input
signals. Feedback around an internal op-amp provides level
shifting and can be used to generate division and square
root functions. A simple arrangement of potentiometers may
be used to trim gain accuracy, offset voltage and feedthrough performance. The high accuracy, wide bandwidth,
and increased versatility of the ICL8013 make it ideal for all
multiplier applications in control and instrumentation systems. Applications include RMS measuring equipment, frequency doublers, balanced modulators and demodulators,
function generators, and voltage controlled amplifiers.

•
•
•
•
•

Accuracy of ±O.5% ("A" Version)
Full ± 10V Input Voltage Range
lMHz Bandwidth
Uses Standard ± 15V Supplies
Built-In Op Amp Provides Level Shifting, Division and
Square Root Functions

ORDERING INFORMATION
Part
Number

Multiplication
Error

Temperature
Range

Package

ICL8013AM T2
ICL8013BM T2
ICL8013CM T2
ICL8013AC T2
ICL8013BC T2
ICL8013CC T2

±0.5% }
±1%
MAX
±2%

-55'C to + 125'C
-55'C to + 125'C
- 55'C to + 125'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C

10-LEAD
TO-l00

±5%}
±1% MAX
±2%

Yos

VOLTAGE TO CURRENT
CONVERTER AND
SIGNAL COMPRESSION

OUTPUT

VTOP VIEW

(outline dwg TO-l00)

Yos

0325-2

Figure 2: Pin
Configuration
0325-1

Figure 1: Functional Diagram (Multiplexer)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

302085-002

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but 8J'6 not tested.

6-12

ICL8013
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................. ± 18V
Power Dissipation (Note 1) ..................... 500mW
Input Voltages
(XIN, YIN, ZIN, Xos, Yos, Zos) ............... VSUPPLY

Operating Temperature Range:
ICL8013XC ........................... O·Cto +700C
ICL8013XM ....................... -55·Cto + 125·C
Storage Temperature Range .....•.... -65·C to + 150·C
Lead Temperature (Soldering, 10sec) ............. 3000C

NOTE 1: Derate at 6.8mW/'C for operation at ambient temperature above 75'C.
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent demtl(J8 to thB device. TheS8 a(8 stress ratings only and functional
operation of thB devic8 at thBS8 or any other conditions above /hose Indicated in thB operalion8l sections of thB 8p8Cifications is not imp/i8d. ExposurB to absolute

maximum rating conditions for extended periods may affect device re//sbility.

ELECTRICAL CHARACTERISTICS

(Unless otherwise specified TA = 25·C, VSUPPLY = ± 15V, Gain and Offset

Potentiometers Externally Trimmed)
Parameter

Test Conditions

ICL8013A
Min

Multiplier Function
Multiplication Error

Typ
XY
-10

-10

AL

±10

The fundamental element of the ICL8013 multiplier is the
bipolar differential amplifier of Figure 3.
The small signal differential voltage gain of this circuit is
given by

AL

AL <

1

%rC

0.04

DETAILED DESCRIPTION

v+

V,N

0.04

AL

~ Vour~

1

vx

,----<>

l21E

r

Ay

03.....

J-

qRL
Vour=--(Vx-Vy)
kTRy
There are several difficulties with this simple modulator:
1:
Vy must be positive and greater than YD.
2:
Some portion of the signal at Vx will appear at the
output unless IE= o.
3:
Vx must be a small signal for the differential pair to
be linear.
4:
The output voltage is not centered around ground.
The first problem relates to the method of converting the
Vy voltage to a current to vary the gain of the Vx differential
pair. A better method. Figure 5, uses another differential
pair but with considerable emitter degeneration. In this cir-

Vour = K (Vx • Vy)

liD

Vy

'0,

VD~'
Vour =

£

(Vx • Vy)
0325-4

Figure 4: Transconductance Multiplier

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLlEO OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values havs been characterized but are not tested.

6-14

IIO~OU.

ICL8013
cuit the differential input voltage appears across the common emitter resistor, producing a current which adds or
subtracts from the quiescent current in either collector. This
type of voltage to current converter handles Signals from 0
volts to ± 10 volts with excellent linearity.

In Figure SB, notice that with VIN=O any variation in the
ratio of biasing current sources will produce a common
mode voltage across the load reSistors. The differential output voltage will remain zero. In Figure SC we apply a differential input voltage with unbalanced current sources. If IE1
is twice IE2' the gain of differential pair Q1 and 02 is twice
the gain of pair 03 and 04. Therefore, the change in cross
coupled collector currents will be unequal and a differential
output voltage will result. By replacing the separate biasing
current sources with the voltage to current converter of Figure 5 we have a balanced multiplier circuit capable of four
quadrant operation (Figure 7).

v+

y.

RL

RL

... .lVOUT =0 0-"--=,,-,,

t--=:--~

v0325-5

Figure 5: Voltage to Current Converter
The second problem is called feedthrough; i.e. the product of zero and some finite input signal does not produce
zero output voltage. The circuit whose operation is illustrated by Figures SA, B, and C overcomes this problem and
forms the heart of many multiplier circuits in use today.
This circuit is basically two matched differential pairs with
cross coupled collectors. Consider the case shown in SA of
exactly equal current sources biasing the two pairs. With a
small positive signal at VIN, the collector current of 01 and
04 will increase but the collector currents of 02 and 03 will
decrease by the same amount. Since the collectors are
cross coupled the current through the load resistors remains unchanged and independent of the VIN input voltage.

21EI

0325-7

Figure 6B: No Input Signal with Unbalanced
Current Sources AVOUT= OV
Y'

v+

RL

11210

~ 10

+.l~ 1/21;-.1

0325-8

Figure 6C: Input Signal with Unbalanced
Current Sources, Differential Output Voltage
0325-6

Figure 6A: Input Signal with Balanced
Current Sources AVOUT = OV
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PROOUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN typimI va/U6s have be9n chBractsI1zed but are not tested.

S-15

e
o...
Col

.O~OD..

~
o

ICL8013

!:!

This circuit of Figure 7 still has the problem that the input
voltage VIN must be small to keep the differential amplifier
in the linear region. To be able to handle large signals, we
need an amplitude compression circuit.

....CD

v+

y+

0325-11

Figure 88: Voltage Gain with
Signal Compression
Figure 5 showed a current source formed by relying on
the matching characteristics of a diode and the emitter base
junction of a transistor. Extension of this idea to a differential circuit is shown in Figure SA. In a differential pair, the
input voltage splits the biasing current in a logarithmic ratio.
(The usual assumption of linearity is useful only for small
signals.) Since the input to the differential pair in Figure SA
is the difference in voltage across the two diodes, which in
turn is proportional to the log of the ratio of drive currents, it
follows that the ratio of diode currents and the ratio of collector currents are linearly related and independent of amplitude. If we combine this circuit with the voltage to current
converter of Figure 5, we have Figure SB. The output of the
differential amplifier is now proportional to the input voltage
over a large dynamic range, thereby improving linearity
while minimizing drift and noise factors.
The complete schematic is shown in Figure 9. The differential pair 03 and 04 form a voltage to current converter
whose output is compressed in collector diodes 01 and 02.
These diodes drive the balanced cross-coupled differential
amplifier 0710s 014/015. The gain of these amplifiers is
modulated by the voltage to current converter 09 and 010.
Transistors Os, Os, 011, and 012 are constant current
sources which bias the voltage to current converter. The
output amplifier comprises transistors 016 through 027.

0325-9

Figure 7: Typical Four Quadrant
Multiplier-Modulator

lCl-X)

10

0325-10

Figure 8A: Current Gain Cell

tNTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY ANO FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

6-16

ICL8013
v+

YIN

COMMOH

Figure 9: ICL8013 Schematic

0325-12

MULTIPLICATION
In the standard multiplier connection, the Z terminal is
connected to the op amp output. All of the modulator output
current thus flows through the feedback resistor R27 and
produces a proportional output voltage.

XiNo----=t

X,NY,N
EoUT="1O

XcsYosZos

0325-14

Figure 10B: Actual Circuit Connection
0325-13

Figure 10A: Multiplier Block Diagram

DIVISION

Multiplier Trimming Procedure
1.
2.

Set XIN = YIN = OV and adjust Zos for zero Output.
Apply a ± 10V low frequency (';; 100Hz) sweep (sine
or triangle) to YIN with XIN = OV, and adjust Xos for
minimum output.

3.

Apply the sweep signal of Step 2 to XIN with
YIN=OV and adjust Yos for minimum Output.
Readjust Zos as in Step 1, if necessary.
With XIN = 10.0V DC and the sweep signal of Step 2
applied to YIN, adjust the Gain potentiometer for
Output=YIN. This is easily accomplished with a differential scope plug-in (A + 8) by inverting one sigand
adjusting
Gain
control
for
nal
(Output- YIN) = Zero.

4.
5.

If the Z terminal is used as an input, and the output of the
op-amp connected to the Y input, the device functions as a
divider. Since the input to the op-amp is at virtual ground,
and requires negligible bias current, the overall feedback
forces the modulator output current to equal the current
produced by Z.
ZIN
Therefore 10 = XINeYIN =""R= 10ZIN
.
10ZIN
Since YIN=EOUT, EOUT=-XIN

INTERSll'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE; All typical v(lltm$ have bsBn characterized but are not test8CI.

6-17

=
ICL8013
o
CD

~

Note that when connected as a divider, the X input must
be a negative voltage to maintain overall negative feedback.

SQUARING
The squaring function is achieved by simply multiplying
with the two inputs tied together. The squaring circuit may
also be used as the basis for a frequency doubler since
cos2wt= % (cos 2wt+ 1).

Z'N

Izi R=ro

Z

0325-15

Figure 11A: Division Block Diagram
0325-17

Figure 12A: Squarer Block Diagram
Xos Yos Zos
(0 TO _ 10V)

7 10

9

X'N
Z'N<>------,,,1

0325-18

0325-16

Figure 12B: Actual Circuit Connection

Figure 11B: Actual Circuit Connection

SQUARE ROOT

Divider Trimming Procedure
1.

2.
3.
4.

5.
6.

Tying the X and Y inputs together and using overall feedback from the Op Amp results in the square root function.
The output of the modulator is again forced to equal the
current produced by the Z input.
10 = XINeYIN = ( - EOUT)2 = 10ZIN
EOUT= -Y1OZIN
The output is a negative voltage which maintains overall
negative feedback. A diode in series with the Op Amp output prevents the latchup that would otherwise occur for
negative input voltages.

Set trimming potentiometers at mid-scale by adjusting voltage on pins 7, 9 and 10 (Xos, Yos, ZOS) for
zero volts.
With ZIN = OV, trim Zos to hold the Output constant,
as XIN is varied from -10V through -1 V.
With ZIN=OV and XIN= -10.0V adjust Yos for zero
Output voltage.
With ZIN=XIN (and/or ZIN= -XIN) adjust Xos for
minimum worst-case variation of Output, as XIN is
varied from -10V to -1V.
Repeat Steps 2 and 3 if Step 4 required a large
initial adjustment.
With ZIN=XIN (and/or ZIN= -XIN) adjust the gain
control until the output is the closest average
around + 10.0V (-1 OV for ZIN = - XIN) as XIN is
varied from -10V to -3V.

Z

0325-19

Figure 13A: Square Root Block Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE ANO SHALL B~ IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not test8d.

6-18

.D~DIl.

ICL8013

Co»

XosYos Zos

GAIN

XINo-----=-t

v'1O!iN

OUTPUT = -

5k

7.5k
0325-22

Figure 15: Multiplication
0325-20

Figure 138: Actual Circuit Connection

Square Root Trimming Procedure
1.
2.
3.

4.

XIN...!!!~~~"""""'''''\

Connect the ICLB013 in the Divider configuration.
Adjust Zos. Yos. Xos. and Gain using Steps 1
through 6 of Divider Trimming Procedure.
Convert to the Square Root configuration by connecting XIN to the Output and inserting a diode between Pin 4 and the Output node.
With ZIN = OV adjust Zos for zero Output voltage.

Z,No_----,;!

Uk

VARIABLE GAIN AMPLIFIER

0325-23

Most applications for the ICLB013 are straight forward
variations of the simple arithmetic functions described
above. Although the circuit description frequently disguises
the fact. it has already been shown that the frequency doubler is nothing more than a squaring circuit. Similarly the
variable gain amplifier is nothing more than a multiplier. with
the input signal applied at the X input and the control voltage applied at the Y input.

Figure 16: Division

V+

v0325-24

Figure 17: Potentiometers for Trimming Offset
and Feedthrough
' \ / \ ; INPUT

o-----=!

CON;~~~
VOLTAGE

7.Sk

Xos Yos Zos
1N4148

OUTPUT = -

v'1OZiN

0325-21

Figure 14: Variable Gain Amplifier

L--------:G:-:Ac::IN,-·~5k

7.5k

0325-25

Figure 18: Square Root

INTERSIL'S SOLj;: AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been chsract8rlzed but SIB not tested.

6-19

.
o

TYPICAL APPLICATIONS

1N4148

2

~
o

ICL8013

a

TYPICAL PERFORMANCE CHARACTERISTICS
AMPLITUDE AND PHASE AS A
FUNCTION OF FREQUENCY

NONLINEARITY AS A
FUNCTION OF FREQUENCY

FEEDTHROUGH AS A
FUNCTION OF FREQUENCY
-10 r"T1'IM'"TTIII""TTrnn-mr,

! -20 HtIt+tttt-+H-tt++Ht-i
~

~

10

f.
25
1k

-10
10k 100k 1M 10M
FREQUENCY (Hz)
0325-26

-30

~ -40 HHt-t+Itl-Pli~I4HH

~
1 X-I

§-IO

1

~

Y-I

... I:'11t±1~nt!mj
-70

1k
100

1k
10k
FREQUENCY (Hz)

100k

10k

100k 1M 10M
FREQUENCY (Hz)

0325-28
0325-27

DEFINITION OF TERMS
Multiplication/Division £"or.· This is the basic accuracy
specification. It includes terms due to linearity, gain, and
offset errors, and is expressed as a percentage of the full
scale output.
Feedthrough: With either input at zero, the output of an
ideal multiplier should be zero regardless of the signal applied to the other input. The output seen in a non-ideal multiplier is known as the feedthrough.

Nonlinearity: The maximum deviation from the best straight
line constructed through the output data, expressed as a
percentage of full scale. One input is held constant and the
other swept through its nominal range. The nonlinearity is
the component of the total multiplication/division error
which cannot be trimmed out.

INTERSIL·S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valuss have b6sn charscteriz6d but are not testsd.

6-20

ICL8038
Precision Waveform
GeneratorIVoltage
Controlled Oscillator
GENERAL DESCRIPTION

FEATURES

The ICLB038 Waveform Generator is a monolithic Integrated circuit capable of producing high accuracy sine,
square, triangular, sawtooth and pulse waveforms with a
minimum of extemal components. The frequency (or repetition rate) can be selected extemally from .001 Hz to more
than 300kHz using either resistors or capacitors, and frequency modulation and sweeping can be accomplished with
an extemal voltage. The ICLB038 is fabricated with advanced monolithic technology, using Schottky-barrier diodes and thin film resistors, and the output is stable over a
wide range of temperature and supply variations. These devices may be interfaced with phase locked loop circuitry to
reduce temperature drift to less than 250ppm/·C.

• Low Frequency Drift With Temperature
-250ppmrC
• Simultaneous Sine, Square, and Triangle Wave
Outputs
• Low Distortion - 1% (Sine Wave Output)
• High Linearity - 0.1 % (Triangle Wave Output)
• WIde Operating Frequency Range - 0.001Hz to
300kHz
• Variable Duty Cycle - 2% to 98%
• High Level Outputs - TTL to 28V
• Easy to Use - Just A Handful of External
Components Required

ORDERING INFORMATION
Part Number

Stability

Temp. Range

Package

ICLB038CCPO

250ppm/·C typ

O·Cto +70"C

14 pin MiniOIP

ICLB038CCJO

250ppm/·C typ

O·Cto +70"C

CEROIP

ICLB038BCJO

180ppm/·C typ

O·Cto +70·(;

CEROIP

ICLB038ACJO

120ppm/·C typ 110

O·Cto +70"C

CEROIP

ICLB038BMJO*

350ppml"C max

- 55·C to + 125·C

CEROIP

ICL8038AMJO*

250ppml"C max

- 55·C to + 125·C

CEROIP

•

"Add 18838 to part number if 883 processing is required.

r------------------------..y+
CURRENT
SOURCE
.1

SINIWAWI

NC

ADJUST

IfNlWAWI

NC

OUT

_WAVE
ADJUST

TRIANGLE
OUT

~{4

FRIQUENCY
ADJUIT

CURRENT

TIMING
CAPACIT-CIR
IOUAREWAVE
OUT

5

SOURCE
112

V"orGND

11

FM

lIAS

8

:=:pu~P
0326-2

Figure 2: Pin Configuration
(Outline dwg JD)
0326-1

Figure 1: Functional Diagram

INTERSIL·S SOLE AND EXCLUSIVE WARRANTY DBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES. EXPRESS. IMPUED OR STATUTORY. INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
302600-002
NOTE:AI1typ/c81vo/ueoM",, _ _ butsrsnollos/8d.

6-21

=
ICL8038
o

...
S!

.o~on.

ell)

ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V- to v+) ........................ 36V
Power Dissipation(1) ........................... 750mW
Input Voltage (any pin) ....................... V- to V+
Input Current (Pins 4 and 5) ...................... 25mA
Output Sink Current (Pins 3 and 9) ................ 25mA

Storage Temperature Range .......... -65'C to + 150'C
Operating Temperature Range:
S03SAM, S03SBM ...•............. -55'C to + 125'C
S03SAC, S03SBC, S03SCC .............. O'C to + 70'C
Lead Temperature (Soldering, 10sec) ............. 300'C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are slr9ss ratings only and functional

operation of the devica at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
NOTE 1: Derate ceramic package at 12.SmWI'C for ambient temperatures above 100'C.

ELECTRICAL CHARACTERISTICS

(VSUPPLY = ± 10V or + 20V, T A = 25'C, RL = 10k!}, Test Circuit Unless

Otherwise Specified)
Symbol

Min
VSUPPLY
V+
V+,V-

8038BC(BM)

8038CC

General Characteristics

Typ

Max

Min

Typ

8038AC(AM)

Max

Min

Typ

Units

Max

Supply Voltage Operating Range
Single Supply

+10

+30

+10

30

+10

30

V

Dual Supplies

±5

±15

±5

±15

±5

±15

V

Supply Current (VSUPPLY= ± 10V)(2)

ISUPPLY

S03SAM, S03SBM
S03SAC,S03SBC,S03SCC

12

20

12

15

12

15

mA

12

20

12

20

mA

Frequency Characteristics (all waveforms)
f max

Maximum Frequency of Oscillation

fswe~p

Sweep Frequency of FM Input

100

Sweep FM Range(3)

affaT

100

100
10

10

35:1

35:1

35:1

FM Linearity 10: 1 Ratio

0.5

0.2

0.2

Frequency Drift With Temperature(5)
S03S AC, BC, CC O'C to 70'C

250

1S0

120

kHz

%
ppml'C

S03SAM, BM, -55'Cto 125'C
affaV

kHz

10

350

Frequency Drift With Supply Voltage
(Over Supply Voltage Range)

0.05

250

0.05

%fV

0.05

Output Characteristics
IOLK

Square-Wave
Leakage Current (Vg = 30V)

VSAT

Saturation Voltage (lsINK=2mA)

0.2

It

Rise Time (RL =4.7kn)

1S0

tf

Fall Time (RL = 4.7k!})

aD

Typical Duty Cycle Adjust (Note 6)

VTRIANGLE

Triangle/Sawtooth/Ramp
Amplitude (RTRI = 100k!})

ZOUT
VSINE
THO
THO
NOTES: 2.
3.
4.
5.
6.

1

1
0.2

0.5

1S0

0.30

9S
0.33

2
0.30

0.33

2
0.30

0.33

0.05

0.05

Output Impedance (lOUT = 5mA)

200

200

200

0.2

0.22

THO (Rs = 1M!})(4)

2.0

THD Adjusted (Use Figure 6)

1.5

0.2
5

0.22
1.5

0.2
3

1.0

O.S

%
XVSUPPLY
%
!}

0.22
1.0

V
ns

9S

0.1

p.A
ns

40
9S

Linearity
Sine-Wave
Amplitude (RSINE = 100k!})

0.4

1S0

40

40
2

1
0.2

0.4

XVSUPPLY
1.5

%
%

RA and Rs currents not included.
VSUPPLy~20V; RA and Rs~10kO, f"'10kHz nominal; can be extended 1000 to 1. See Figures 7a and 7b.
82kO connected between pins 11 and 12, Triangle Duty Cycle set at 50%. (Use RA and RB.)
Figure 3, pins 7 and 8 connected, VSUPPLY~ ± 10V. See Typical Curves for T.C. vs VSUPPLY'
Not tested, typical value for design purposes only.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PAODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not test9Ci.

6-22

ICL8038
TEST CONDITIONS
Parameter

Meaaure

RA

RB

RL

Cl

SWl

Supply Current

10kO

10kO

10kO

3.3nF

Closed

Current into Pin 6

Sweep FM Range(l)

10kO

10kO

10kO

3.3nF

Open

Frequency at Pin 9

Frequency Drift with Temperature

10kO

10kO

10kO

3.3nF

Closed

Frequency at Pin 3

Frequency Drift with Supply Voltage(2)

10kO

10kO

10kO

3.3nF

Closed

Frequency at Pin 9

Sine

10kO

10kO

10kO

3.3nF

Closed

Pk-Pk output at Pin 2

I Triangle

10kO

3.3nF

Closed

Pk-Pk output at Pin 3

3.3nF

Closed

Current into Pin 9

Output Amplitude:
(Note 4)

I

10kO

10kO

Leakage Current (off)(3)

10kO

10kO

Saturation Voltage (on)(3)

10kO

10kO

3.3nF

Closed

Output (low) at Pin 9

Rise and Fall Times (Note 5)

10kO

10kO

4.7kO

3.3nF

Closed

Waveform at Pin 9

50kO

-1.6kO

10kO

3.3nF

Closed

Waveform at Pin 9

Duty Cycle Adjust:
(Note 5)

l MAX
I MIN

-25kO

50kO

10kO

3.3nF

Closed

Waveform at Pin 9

Triangle Waveform Unearity

10kO

10kO

10kO

3.3nF

Closed

Waveform at Pin 3

Total Harmonic Distortion

10kO

10kO

10kO

3.3nF

Closed

Waveform at Pin 2

NOTES: 1. The hi and 10 frequencies can be obtained by connacUng pin 8 to pin 7 (IhI) and then connacUng pin 8 to pin 6 (Ilal. Otherwise apply Sweep Voltage at
pin 8 ("Is VSUPPLY + 2V)';VSWEEP,;VSUPPLY where VSUPPLY Is the tolalsupply voltage. In Figure 7b. pin 8 should vary batwaan 5.3V and 10V with
respect to ground.
2. 10V,;V+ ,;30V. or ±5V,;VSUPPLY'; ±15V.

3. Oscillation can be halted by forcing pin 10 to + 5 volta or - 5 volts.
4. Output Amplitude Is tasted under static conditions by!orcing pin 10 to 5.0V then to -5.0V.
5. Not tasted; for design purposes only.

Triangle Waveform Linearity. The percentage deviation
from the best-fit straight line on the rising and falling triangle
waveform.
Total Harmonic Distortion. The total harmonic distortion
at the sine-wave output.

DEFINITION OF TERMS:
Supply Voltage (VSUPPLY). The total supply voltage from
V+ to VSupply Current. The supply current required from the power supply to operate the device, excluding load currents and
the currents through RA and Re.
Frequency Range. The frequency range at the square
wave output through which circuit operation is guaranteed.
Sweep FM Range. The ratio of maximum frequency to minimum frequency which can be obtained by applying a sweep
voltage to pin 8. For correct operation, the sweep voltage
should be within the range

;-----~------~------~--~+1~

RL

1G1c

(% VSUPPLY+ 2V) 

~1.02

~

I I

w

"

I 15~~~~~~~~~~

~1.01

'""-0 1.00

i 10~~~~~~-

I

I

!!i!

;£0.99

I

~0.96
z

~

10
~UPPLY

VOLTAGE

!

!

I.U

--

!

~1.02 ~~~t-t-~~H~~

!

Ii

a

1.01

i !!

I

I!

0 1.00

I

I

\

II

i i
20

HHHH--+--+-++-¥l

If

iT

j

i I II
15

1·03I1--r~-'--;-..,-r-T"""~

I

!!i!

;to... t-~~t-t-~~H--I-+
:Ii

i o.ul-f-f-l-l-f-f-H---1H

!

!

25

125

30
TEMPERATURE 'C

SUPPLY VOLTAGE

0326-4

0326-5

0326-6

Performance of the Square-Wave Output

I ~ f--

--

!

150

-(...~

.100 H-+~iIP'I-++-H---1

25'C-

"

~~

125'

~ ~~
~~
2

~~

.... ~'IC

4

I
6

10

8

lOAD CURRENT-mA

0326-8

0326-7

Performance of Triangle-Wave Output
10

w1.2

~

!:i

~

1.1

r'

O

--f--

~ 0.8

~

I

i

~

4 6 8 10 12 14 16 18 20
lOAD CURRENT-IIIA

II

If

0.8

--f--

0.7

I

0.1
10Hz 100Hz 1kHz 10kHz 100kHz lMHz
FREQUENCY

0326-10

i
~

1

0.1

I
i

0.01
10Hz 100Hz 1kHz 10kHz l00kHzlMHz
FREQUENCY

0326-11

0326-9

Performance of Sine-Wave Output

II
i!

12

1.1

r~
a

~

II

10

~

\

8

3

6

Iia

d.'

I

~

~~

!

2

4

l

H
U A
~~D
f-AbJ~~ ~D ~-r-

o

10Hz 100Hz 1kHz 10kHz 100kHz lMHz
FREQUENCY

10Hz 100Hz 1kHz 10kHzl00kHzlMHz
FREQUENCY

0326-13

0326-12

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charar;terfzed but are not tested

6-24

ICL8038

/

k':' '\

/

""/ / '"I"V / '"

'v

I"

~

i'V

~

f'-V

"'

"",

V

"-

r\

'"",
.JII

'.........

r\

I'"

V "\

'V

:"

~V r\
"",. ~

,

....

-

0326-15

0326-14

Square-Wave Duty Cycle-80%

Square-Wave Duty Cycle-50%

Figure 4: Phase Relationship of Waveforms
controls the rising portion of the triangle and sine-wave and
the 1 state of the square-wave.
The magnitude of the triangle-waveform is set at Va VSUPPLY; therefore the rising portion of the triangle is,
CXv CXVaXVSUPPLyXRA RAXC
t1=---I
0.22XVSUPPLY
0.66
The falling portion of the triangle and sine-wave and the 0
state of the square-wave is:
1
CXaVSUPPLY

DETAILED DESCRIPTION

(See Figure 1)
An external capacitor C is charged and discharged by two
current sources. Current source "" 2 is switched on and off
by a flip-flop, while current source "" 1 is on continuously.
Assuming that the flip-flop is in a state such that current
source "" 2 is off, and the capacitor is charged with a current
I, the voltage across the capacitor rises linearily with time.
When this voltage reaches the level of comparator "" 1 (set
at % of the supply voltage), the flip-flop is triggered, changes states, and releases current source "" 2. This current
source normally carries a current 21, thus the capacitor is
discharged with a net-current I and the voltage across it
drops linearly with time. When it has reached the level of
comparator"" 2 (set at Va of the supply voltage), the flip-flop
is triggered into its original state and the cycle starts again.
Four waveforms are readily obtainable from this basic
generator circuit. With the current sources set at I and 21
respectively, the charge and discharge times are equal.
Thus a triangle waveform is created across the capacitor
and the flip-flop produces a square-wave. Both waveforms
are fed to buffer stages and are available at pins 3 and 9.
The levels of the current sources can, however, be selected over a wide range with two external resistors. Therefore, with the two currents set at values different from I and
21, an asymmetrical sawtooth appears at terminal 3 and
pulses with a duty cycle from less than 1 % to greater than
99% are available at terminal 9.
The sine-wave is created by feeding the triangle-wave
into a non-linear network (sine-converter). This network provides a decreasing shunt-impedance as the potential of the
triangle moves toward the two extremes.

2(0.22)VS'::LY _0.22VS'::LY

0.66(2RA- Re)

Thus a 50% duty cycle is achieved when RA = Re.
If the duty-cycle is to be varied over a small range about
50% only, the connection shown in Figure 5b is slightly
more convenient. If no adjustment of the duty cycle is desired, terminals 4 and 5 can be shorted together, as shown
in Figure 5c. This connection, however, causes an inherently larger variation of the duty-cycle, frequency, etc.
With two separate timing resistors, the frequency is given
by

0.33

f=FiC (for Figure 5a)
If a single timing resistor is used (Figure 5c only), the
frequency is

WAVEFORM TIMING
The symf716try of all waveforms can be adjusted with the
external timing resistors. Two possible ways to accomplish
this are shown in Figure 5. Best results are obtained by
keeping the timing resistors RA and Re separate (a). RA

f= 0.165
RC

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY oeUGATION WITH RESPECT TO THIS PROOUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPREss. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typIcBI vsiws hIIv9 bssn chlltaCt9riz9d but Br9 not tested.

6-25

•

=
ICL8038
o

3

S:!

(0)

(b)

(a)

r--"""'-_-""""'V+

r---..,-~-v+

r-----"1P-....,..OOy+

Rs

lit.

nn
ICL8038

\tv
'V\,
L-_ _- _......_ _ V""orOND

L----4>---__+-___oV""orOND

0326-18

0326-16

0326-17

Figure 5: Possible Connections for the External Timing Resistors
Neither time nor frequency are dependent on supply voltage, even though none of the voltages are regulated inside
the integrated circuit. This is due to the fact that both currents and thresholds are direct, linear functions of the supply voltage and thus their effects cancel.
To minimize sins-wave distortion the 82kO resistor between pins 11 and 12 is best made variable. With this arrangement distortion of less than 1% is achievable. To reduce this even further, two potentiometers can be connected as shown in Figure 6; this configuration allows a typical
reduction of sine-wave distortion close to 0.5%.

7

q:c

I

I

I

11

Ij--+-onn

I

1

0.22(V+-V-)

WAVEFORM OUT LEVEL CONTROL
AND POWER SUPPLIES
The waveform generator can be operated either from a
single power-supply (10 to 30 Volts) or a dual power-supply
(± 5 to ± 15 Volts). With a single power-supply the average
levels of the triangle and sine-wave are at exactly one-half
of the supply voltage, while the square-wave alternates between V + and ground. A split power supply has the advantage that all waveforms move symmetrically about ground.
The square-wave output is not committed. A load resistor
can be connected to a different power-supply, as long as
the applied voltage remains within the breakdown capability
of the waveform generator (30V). In this way, the squarewave output can be made TIL compatible (load resistor
connected to + 5 Volts) while the waveform generator itself
is powered from a much higher voltage.

aJ---o'V'v

12

R1 X (V+-V-)x 1

(Rl + R2)
RA
RA
A similar calculation holds for Rs.
The capaCitor value should be chosen at the upper end of
its possible range.

HL

fRs

ICL8038

10

are placed upon the magnitude of the charging current for
optimum performance. At the low end, currents of less than
1p.A are undesirable because circuit leakages will contribute significant errors at high temperatures. At higher currents (I> 5mA), transistor betas and saturation voltages will
contribute increasingly larger errors. Optimum performance
will, therefore, be obtained with charging currents of 10p.A
to 1mA. If pins 7 and 8 are shorted together, the magnitude
of the charging current due to RA can be calculated from:

lkll

4

8

For any given output frequency, there is a wide range of

RC combinations that will work, however certain constraints

y+

J

...

SELECTING RA. RB and C

2J---o'\JV

10k

lOO1cn
100ldl
10k
V""orOND

0326-19

Figure 6: Connection to Achieve
Minimum Sine-Wave Distortion

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical values have been characterizsd but 81'6 not tested.

6-26

rIlO~OR.

ICL8038

n
I'"
C»

0

Co»

y+

5

4

8

v+

SW~I!P
VOLTAGE

RL

• R.

ro- 7

C»

~

J!L

·r-........nn

RA

R.

4

• Re

8

5

I

---+--o11J1..

>R

r-'

......

ICL8038

ICLa038

T
FM

~,10~____~lrl____~lr2_2~~~

~~10~____~11~____~1~2_2~~~
.1k

'--------+-------_4_--___ V-orGND

~------+-------~----~V-orGND

0326-20

0326-21

Figure 7: Connections for Frequency Modulation (a) and Sweep (b)

FREQUENCY MODULATION AND
SWEEPING

r-----~r_----~r_--------4r--~v+

The frequency of the waveform generator is a direct function of the DC voltage at terminal S (measured from V +). By
altering this voltage, frequency modulation is performed.
For small deviations (e.g. ± 10%) the modulating signal can
be applied directly to pin 8, merely providing DC decoupling
with a capacitor as shown in Figure 7a. An external resistor
between pins 7 and S is not necessary, but it can be used to
increase input impedance from about SkO (pins 7 and S
connected together), to about (R + SkO).
For larger FM deviations or for frequency sweeping, the
modulating signal is applied between the positive supply
voltage and pin S (Figure 7b). In this way the entire bias for
the current sources is created by the modulating signal, and
a very large (e.g. 1000:1) sweep range is created (f=O at
Vsweep=O). Care must be taken, however, to regulate the
supply voltage; in this configuration the charge current is no
longer a function of the supply voltage (yet the trigger
thresholds still are) and thus the frequen~y beco.mes dependent on the supply voltage. The potential on Pin S may
be swept down from V+ by (% VSUPPLy-2V).

r.7~4~----~I~----~'~2~AM~UDI!

f~

•

I'-~rr-

ICL8038

10

11

Uk

c
~-------------+--------~----~~
0326-22

Figure 8: Sine Wave Output Buffer Amplifiers
tral Pin 8 exceed the voltage at the top of RA and RB by a
few hundred millivolts. The Circuit of Figure 10 achieves this
by using a diode to lower the effective supply voltage on the
ICL803S. The large resistor on pin 5 helps reduce duty cycle
variations with sweep.
The linearity of input sweep voltage versus output frequency can be significantly improved by using an op amp as
shown in Figure 11.

APPLICATIONS
The sine wave output has a relatively high output impedance (1 kO Typ). The circuit of Figure S provides buffering,
gain and amplitude adjustment. A simple op amp follower
could also be used.
With a dual supply voltage the external capacitor on Pin
10 can be shorted to ground to halt the ICLS03S oscillation.
Figure 9 shows a FET switch, diode ANDed with an input
strobe signal to allow the output to always start on the same
slope.
To obtain a 1000:1 Sweep Range on the ICLS03S the
voltage across external resistors RA and Rs must decrease
to nearly zero. This requires that the highest voltage on con-

USE IN PHASE-LOCKED LOOPS
Its high frequency stability makes the ICLS03S an ideal
building block for a phase-locked loop as shown in Figure
12. In this application the remaining functional blocks, the

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

6-27

•

1II0~OIl.

=: ICL8038

o

...

CD

S!

.1OY

1N457
r------4~----------------~---o+IW
CYCLE

ll1e

RB

lk

.11o'F

•

4.7k

Uk

• • 11It

INll.
10

11

lS1c

2

10k
FREQUENCY

INtI.

ICL8038

"'"

!--1>4-"'''''''''STROBE

I.

C

OFF

VON

-IW

~~:: :~;:::

'\I\i

DISTORTION
lOOk

-lOY

0326-23

Figure 9: Strobe-Tone Burst Generator

0326-24

Figure 10: Variable Audio OSCillator,
20Hz to 20kHz

HIGH
FREQUENCY
SYMMETRY

soon

lN753A
(I.2V)

4.7kll

Ukll

lkl!

6

>-......"-A~......--I8

SINE-WAVE
OUTPUT

ICL8038

lk1l

"-

FUNCTION GENERATOR

10

11

12

10k1l

OFFSET
3,9OOpF

'_11
SINE-WAVE,
DISTORTION

~----~----"""----~----------~--------------I~-IW

0326-25

Figure 11: Linear Voltage Controlled OSCillator
phase-detector and the amplifier, can be formed by a number of available IC's (e.g. MC4344, NE562, HA2800,
HA2820)
In order to match these building blocks to each other, two
steps must be taken. First, two different supply voltages are
used and the square wave output is returned to the supply
of the phase detector. This assures that the VCOinput voltage will not exceed the capabilities of the phase detector. If
a smaller VCO signal is required, a simple resistive voltage
divider is connected between pin 9 of the waveform generator and the VCO input of the phase-detector.

Second, the DC output level of the amplifier must be
made compatible to the DC level required at the FM input of
the waveform generator (pin 8, O.8V+). The simplest solution here is to provide a voltage divider to V + (R 1, R2 as
shown) if the amplifier has a lower output level, or to ground
if its level is higher. The divider can be made part of the lowpass filter.
This application not only provides for a free-running frequency with very low temperature drift, but it also has the
unique feature of producing a large reconstituted sinewave
Signal with a frequency identical to that at the input.
For further information, see Intersil Application Note
A013, "Everything You Always Wanted to Know About The
ICl8038."

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but am not tested.

6-28

IIID~DIl.

ICL8038

n
rCD

0

W

v++

CD

R.

v+~----~--

__

~~

TRIANGLE
OUT

FllBiAS

__________•

7

A../v

3

SQUARE
WAVE
OUT •

SINE WAVE

OUT
ICL11G31

'\IV

INPUT
IIN1!WAYE
ADJ.
SINE
WAVE
ADJ.
V-/GNO
0326-26

Figure 12: Waveform Generator Used as Stable veo In a Phase-Locked Loop

R32

RElCTA
4

5.21<
0141

:t---+-;

800
COMPARATOR

10

2.7k

R35
330

m
~::

042

041

R27
33k

R25
33k

~

~

~

~

~

~

R45
33k
~

Rao
33k

-=

R38

1600
R31
33k

R37
330
R38
375

0326-27

Figure 13: Detailed Schematic

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN typical values have been characterizsd but af9 not tsst6d.

6-29

:o ICL8048/ICL8049
3 Logl Antilog Amplifier
()
:::.
Q) GENERAL DESCRIPTION

.
o
Q)

...

g

FEATURES
."'h% Full Scale Accuracy

The 8048 is a monolithic logarithmic amplifier capable of
handling six decades of current input, or three decades of
voltage input. It is fully temperature compensated and is
nominally designed to provide 1 volt of output for each decade change of input. For increased flexibility, the scale factor, reference current and offset voltage are externally adjustable.
The 8049 is the antilogarithmic counterpart of the 8048; it
nominally generates one decade of output voltage for each
1 volt change at the input.

• Temperature Compensated for O'C to + 70'C
Operation
• Scale Factor 1VIDecade, Adjustable
• 120dB Dynamic Current Range (8048)
• 60dB Dynamic Voltage Range (8048 &. 8049)
• Dual JFET-Input Op-Amps

ORDERING INFORMATION
Part Number

Error (25'C)

Temperature Range

Package

ICL8048BCJE
ICL8048CCJE

30mV
60mV

O'Cto +70'C
O'Cto +70'C

16 Pin CERDIP
16 Pin CERDIP

ICL8049BCJE
ICL8049CCJE

10mV
25mV

O'Cto +70'C
O'Cto +70'C

16 Pin CERDIP
16 Pin CERDIP

VREF
A21NPUT

r---~--------~'4~~~

,.

VIN
VIN

Your
10

OND

GAIN
10

VOUT

15

GAIN

A10UTPUT

0313-1

(ICL8048)

0313-2

(ICL8049)
Figure 1: Functional Diagram

GROUND

NO CONNECTION

Al OFFSET NULL
A1 OFFSET NULL

vAl0UTPUT
NO CONNECTION

,

.,
J

AllNPUT 1

..

13 A2 OFFSET NULL

"

•

GROUND

1

A2 OFFSET NULL

9

NO CONNECTION

A2 OFFSET NULL

Al OFFSET NULL 4
Al OFFSET NULL

A2 OFFSET NULL

v-

0

,

1
NO CONNECTION

10

Your

9

NO CONNECTION

A,0UTPUT

1

NO CONNECTION

8

0313-4

0313-3

Figure 2: Pin Configurations (Outline Dwg JE)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

302800-002

NOTE: All typical values have been characterized but are not tested

6-30

IIlD~Do..

ICL8048/ICL8049

n
I'"
CD

ABSOLUTE MAXIMUM RATINGS (ICL8048)
Supply Voltage ................................. ±1BV
liN (Input Current) ................................ 2mA
IREF (Reference Current) ......................... 2mA
Voltage between Offset Null and V+ ............. ±0.5V
Power Dissipation ............................. 750mW

Operating Temperature Range ............ O·C to + 70·C
Output Short Circuit Duration .................. Indefinite
Storage Temperature Range .......... -65·C to + 150·C
Lead Temperature (Soldering, 1Osee) ............. 300·C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress raUngs only and functional
operetion of the device at these or any other condiUons above those indicated In the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (ICL8048)

VS = ± 15V, T A = 25·C, IREF = 1mA, scale factor adjusted

for 1V/ decade unless otherwise specified.
Parameter

8048BC

Test Conditions
Min

Typ

8048CC
Max

Min

Typ

Units
Max

Dynamic Range
liN (1nA - 1mA)
VIN (10mV -10V)

RIN=10kO

Error, % of Full Scale

TA=25·C,IIN= 1nA to 1mA

.20

0.5

.25

1.0

%

Error, % of Full Scale

TA = O·C to + 70·C,
IIN=1nAt01mA

.60

1.25

.BO

2.5

%

Error, Absolute Value

TA=25·C,IIN= 1nA to 1mA

12

30

14

60

mV

Error, Absolute Value

TA=O·C to +70·C
IIN= 1nA to 1mA

36

75

50

150

mV

Temperature Coefficient of Your

IIN= 1nAt01mA

O.B

O.B

mvrc

Power Supply Rejection Ratio

Referred to Output

2.5

2.5

mVIV

120
60

Offset Voltage (A1 & A2)

Before Nulling

Wideband Noise

At Output, for liN = 100",A

Output Voltage Swing

120
60

15

dB
dB

15

25

250

50

mV

250

",V(RMS)

RL =10kO

±12

±14

±12

±14

V

RL =2kO

±10

±13

±10

±13

V

Power Consumption
Supply Current

150

200

150

200

mW

5

6.7

5

6.7

mA

INTERSIL'S SOLE ANO EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, lMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been Characterized but are not tested.

6-31

...oCD

....

n
I;

...oG

. ICL8048/ICL8049
...u
.
ell

o

CO

TYPICAL PERFORMANCE CHARACTERISTICS

:::::.

TRANSFER FUNCTION FOR
VOLTAGE INPUTS

CO

o

CO

'31-~"'lo~·

g

TRANSFER FUNCTION FOR
CURRENT INPUTS

SMALL SIGNAL BANDWIDTH AS A
FUNCTION OF INPUT CURRENT
lOOk
IREF -lmA

++--+-j--H

~

:t:

'2k:-H--t"""~

2
~
z

·'t---f"'jo.;;;::-H---f"","-!-I

....
"
.

--

10k

J

1k

_V
V

-- -

~

z

-I

ill

-2

~

~

po- ~

V

100

~

10
10- 11

INPUT VOLT AGe

0313-5

200

E
w

"~.
0

I I
I I

125

>

'"0

,.~
,.

:>

,..x

;;

8048 CC lite to 700CI

150

100

8048 Be !O"C to 70"CI
'5

8048 CC (25"C)

~

150

~

g

125

'0"
'"ffi,.

100

.

10-8 10-'

I

I

10-6

10-5

10- 4 10-3

INPUT CURRENT (AMPS)

III I"IN -lOki.
~ CC \o·J 10 ':;CI

'\

III I I III
III I I I! I

10-5

50

i

25

o
'OmV

0313-7

1000
434

"

VOLTAGE GAIN- ~ .. logl0e
IRS. 10kOl
6VOUT
VIN

100

.~%

N~

r--

I

"Wa~~t5:ti

01

IV

I

101/

ImV

10mV

100n.V

r-.
IV

IOV

INPUT VOL T AGE

INPUT VOLTAGE

0313-8

-t-

.-

III I I

-

r-.,

8048 CC 12Sn C}

lOOmV

10- 3

SMALL SIGNAL VOLTAGE GAIN AS A
FUNCTION OF INPUT VOLTAGE FOR
RS= 10k!}

10

sWJ Be 'wd 101,~lCI

'5

,.

x

8048 Be 125"CI

25
10-9

!

115

:>

50

o

MAXIMUM ERROR VOLTAGE AT
THE OUTPUT AS A FUNCTION OF
INPUT VOLTAGE
200

I I

115

10- 7

0313-6

MAXIMUM ERROR VOLTAGE AT
THE OUTPUT AS A FUNCTION OF
INPUT CURRENT

:;

10-9

INPUT CURRENT (AMPS)

INPUT CURRENT f AMPS'

0313-9

0313-10

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vall19s have been characterized but are not tested.

6-32

ICL8048/ICL8049
ABSOLUTE MAXIMUM RATINGS (ICL8049)
Supply Voltage ................................. ±18V
VIN (Input Voltage) .............................. ± 15V
IREF (Reference Current) ......................... 2mA
Voltage between Offset Null and V+ ............. ±0.5V
Power Dissipation ............................. 750mW

Operating Temperature Range ............ O'C to + 70'C
Output Short Circuit Duration .................. Indefinite
Storage Temperature Range .......... -65'C to + 150'C
Lead Temperature (Soldering, 1Osee) ............. 300'C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ralings only Bnd functional
operation of the device at these O( any other conditions above those indicated in the operational sections of the specificalions is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (ICL8049)

Vs = ± 15V, T A = 25'C, IREF= 1mA, scale factor adjusted

for 1 decade (out) per volt (in), unless otherwise specified.
Parameter

8049BC

Test Conditions
Min

Typ

8049CC
Max

Min

Typ

Units
Max

60

60

dB

Dynamic Range (VOUT)

VOUT= 10mV to 10V

Error, Absolute Value

TA=25'C,OV:5:VIN:5:2V

3

15

5

25

mV

Error, Absolute Value

TA=O'C to +70'C,
OV:5:VIN:5:3V

20

75

30

150

mV

Temperature CoeffiCient, Referred to VIN

VIN=3V

0.38

0.55

mVI'C

Power Supply Rejection Ratio

Referred to Input, for
VN=OV

2.0

2.0

!'-VIV

Offset Voltage (Al & A2)

Before Nulling

15

Wideband Noise

Referred to Input, for

25

15

26

50

mV

26

!,-V(RMS)

VIN=OV
Output Voltage Swing

RL =10kO

±12

±14

±12

±14

V

RL =2kO

±10

±13

±10

±13

V

Power Consumption
Supply Current

150

200

150

200

mW

5

6.7

5

6.7

mA

TYPICAL PERFORMANCE CHARACTERISTICS
TRANSFER FUNCTION
 -2 f--+-+~~

i:

1-1-t-t-t="'I...+--I

-I L,.--L:-...I.:,....J.~L,-..L.,-..J....J
10- 10 ,0-' 10'" 10-7 10-1 10-1 10-4 10-3
INPUT CURRENT IAMPSI

0313-20

Figure 8
It is important to note that both the ICL8048 and the
ICL8049 require positive values of IREF' and the input
(ICL8048) or output (ICL8049) currents (or voltages) respectively must also be positive. Application of negative liN
to the ICL8048 or negative IREF to either circuit will cause
malfunction, and if maintained for long periods, would lead
to device degradation. Some protection can be provided by
placing a diode between pin 7 and ground.

ERROR DUE TO A (RTO)
-.mV

,

SETTING UP THE REFERENCE
CURRENT

ERROR Due TO 8 IRTOI
·ymV

Figure 7

..

In both the ICL8048 and the ICL8049 the input current
reference pin (lREF) is not a true virtual ground. For the
ICL8048, a fraction of the output voltage is seen on Pin 16
tFigure 3). This does not constitute an appreciable error
provided VREF is much greater than this voltage. A 10V or
15V reference satisfies this condition. For the ICL8049, a
fraction of the input voltage appears on Pin 3 (Figure 4),
placing a similar restraint on the value of VREF.
Alternatively, IREF can be provided from a true current
source. One method of implementing such a current source
is shown in Figure 9.

0313-19

It is very straightforward to estimate the system error at
node (A) by taking the square root of the sum-of-the
squares of the errors of each contributing block.
Total Error = ~x2 + y2 + z2 at (A)
If required, this error can be referred to the system output
through the voltage gain of the antilog circuit, using the voltage gain versus input voltage plot.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED· OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charact9rized but are not tested.

6-37

~

o

ICL8048/ICL8049

a

....«»

.
o

...S:!«»

ERROR, ABSOLUTE VALUE The absolute error is a
measure of the deviation from the theoretical transfer function, after performing the offset and scale factor adjustments as outlined, (ICL8048) or (ICL8049). It is expressed in
mV and referred to the linear axis of the transfer function
plot. Thus, in the case of the ICL8048, it is a measure of the
deviation from the theoretical output voltage for a given input current or voltage. For the ICL8049 it is a measure of
the deviation from the theoretical input voltage required to
generate a specific output voltage.
The absolute error specification is guaranteed over the
dynamic range.
ERROR, % OF FULL SCALE The error as a percentage
of full scale can be obtained from the following relationship:

LOG OF RATIO CIRCUIT, DIVISION

The 8048 may be used to generate the log of a ratio by
modulating the IREF input. The transfer function remains the
same, as defined by equation 9:

liN ]
VOUT= -Klog10 [ IREF

(9)

Clearly it is possible to perform division using just one
ICL8048, followed by an ICL8049. For multiplication, it is
generally necessary to use two log amps, summing their
outputs into an antilog amp.
To avoid the problems caused by the IREF input not being
a true virtual ground (discussed in the previous section), the
circuit of Figure 9 is again recommended if the IREF input is
to be modulated.

VREFI

Error, % of Full Scale

+15V

·'5V

J

100 x Error, absolute value
Full Scale Output Voltage

AI

TEMPERA TURE COEFFICIENT OF VourOR VIN For the
ICL8048 the temperature coefficient refers to the drift with
temperature of VOUT for a constant input current.
For the ICL8049 it is the temperature drift of the input
voltage required to hold a constant value of VOUT.
POWER SUPPL Y REJECTION RA TIO The ratio of the
voltage change .in the linear axis of the transfer function
(VOUT for the ICL8048, VIN for the ICL8049) to the change
in the supply voltage, assuming that the log axis is held
constant.
WIDEBAND NOISE For the ICL8048, this is the noise occurring at the output under the specified conditions. In the
case of the ICL8049, the noise is referred to the input.
SCALE FACTOR For the log amp, the scale factor (K) is
the voltage change at the output for a decade (i. e. 10:1)
change at the input. For the antilog amp, the scale factor is
the voltage change required at the input to cause a one
decade change at the output. See equations 9 and 10.

10-----1
2N221'
10kO

IREF
PIN ,. ON 8048)
( TO
TO PIN 3 ON 8049

0313-21

Figure 9

DEFINITION OF TERMS
In the definitions which follow, it will be noted that the
various error terms are referred to the output of the log
amp, and to the input of the antilog amp. The reason for this
is explained on the previous page.
DYNAMIC RANGE The dynamic range of the ICL8048
refers to the range of input voltages or currents over which
the device is guaranteed to operate. For the ICL8049 the
dynamic range refers to the range of output voltage over
which the device is guaranteed to operate.

APPLICATION NOTES
For further applications assistance, see
A007 "The ICL8048/8049 Monolithic Log-Antilog Amplifi-

ers"

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

6-38

U~UIL2o

ICL8069
Low Voltage Reference

01
G

GENERAL DESCRIPTION

FEATURES

The ICL8069 is a 1.2V temperature compensated voltage
reference. It uses the band-gap principle to achieve excellent stability and low noise at reverse currents down to
50!£A. Applications include analog-to-digital converters, digital-to-analog converters, threshold detectors, and voltage
regulators. Its low power consumption makes it especially
suitable for battery operated equipment.

• Low Bias Current - 50!£A Min
• Low Dynamic Impedance
• Low Reverse Voltage
• Low Cost

ORDERING INFORMATION
Order PIN T()'92

Order PIN TO-52

Temperature Range

Max_ Temp_ Coeff. of VREF

ICL8069CCZR

ICL8069CCSQ

O"C to + 70·C

0.005%I"C

ICL8069CMSQ

- 55·C to + 125·C

0.005%I"C

ICL8069DCSQ

O·Cto +70·C

0.01%I"C

ICL8069DMSQ

- 55·C to + 125·C

0.01%I"C

ICL8089DCZR

-

"Parameter MinIMax Umits guaranteed at 25'C only for DICE orders.

,".
+ 11V'

------~-----~.

--

111r.H

",'DVout

r-----

4.7",.*

••
10ldl

"'Iln
: ICLlOlt ,

2.a.U

, ....

~~

ICLlOlt

.::J

.....: ____.....__....--O...,I·ou,
• ... Notet

0327-1

ICL7107

~~

RIFHI

COMMON

HULO

0327-2

(a) Simple Reference (1.2 volts or less)

(b) Buffered 10V Reference
using a single supply.
Figure 1: Functional Diagrams

0327-3

(c) Double regulated 100mV reference
for ICL7107 one-chip DPM circuit.

0327-4

TO-92

TO-52

0327-5

Figure 2: Pin Configurations

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICUlAR USE.
303120-003
NOTE: All typical values have been characterized but are not 18sfBd.

6-39

::: ICL8069

o

a

ABSOLUTE MAXIMUM RATINGS
Storage Temperature .•...••......... -65'C to + 150'C
Operating Temperature
ICL8069C ............................ O'C to + 70'C
ICL8069M ........................ - 55'C to + 125'C
Lead Temperature (Soldering, 10sec) ............. SOO'C
NOTE: Stresses sbove those !isltld under "Absolute MBximum Rstings" msy CllUS9 permanent damage to the davlce. These aM stress ratings only and functions!
operation of the daviCfJ st th9S6 or any other conditions above those indicaltld in the operations! sactlons of the specifications is not ImplitJd. Exposure to sbsolute
Reverse Voltage ........................... See Note 2
Forward Current ................................ 10mA
Reverse Current ....••..•....•..•••.•••.••.•.••. 10mA
Power Dissipation ...................... Limited by max
forward/reverse current

maximum rating conditions for 9XI9ndad periods msyaffect davictJ rtJIIsbillty.

ELECTRICAL CHARACTERISTICS
CharacteristiCS

(TA= 25'C unless otherwise noted)

Min

Typ

Max

Units

1.20

1.2S

1.25

V

15

20

mV

1
1

2
2

n

0.7

1

V

Test Conditions

Reverse breakdown Voltage

IR=500""A

Reverse breakdown
Voltage change

50""AS:IRS:5mA

Reverse dynamic impedance

IR=50""A
IR=500,..,A

Forward Voltage Drop

IF=500""A
10HzS:fS:10kHz
IR=500""A

RMS Noise Voltage
Long Term Stability

IR=4.75mA
TA=25'C

5

""V

1

ppm/kHR

Breakdown voltage
Temperature coefficient

1"-""""

TA= operating
Temperature range
(NoteS)

ICL8069C
ICL8069D

%I'C
.005
.01

Reverse Current Range

0.050

5

mA

TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE CHANGE AS A
FUNCTION OF REVERSE CURRENT

......

••

....

REVERSE VOLTAGE AS A
FUNCTION OF CURRENT

REVERSE VOLTAGE AS A
FUNCTION OF TEMPERATURE

.
....
. ....
1....

> ••

!

~

I.
~

..~

z

o •

I

~'2$'c.
+12I°C

0:

P

....... ~

·'v1J~':l
V

~
,00,lolA
'rnA
REVII!RIE CURRENT

,.~ .....

u 110 A

//

4

~

1mA

I

-§'Cj

~
~

......

I.'....~A

.2

s

...,.
il

t:::: t:=:

~

".

~Cj

A
..
..
1.0
REVIRSE VOLTAG! (VI

~

'.220
1.211

1.2

1,A

-so

-2$

a

+25 +10 +75 +100 +1as

TEMPERATURE ('CI

0327-7

0327-6

~

03~7-B

Notes: 1) If circu~ strays In excess of 200pF are antiCipated, a 4.71'F shunt cepa~or will ensure stability under all operating conditions.
2) In normal use, the reverse voltage cannot exceed the reference voltage. However when plugging unlta into a powered· up test fixture, an instantaneous
voltage equal to the compliance of the test clrcult will be seen. This should not exceed 20V.
3) For the military part, measurements are made at 25'C. - 55'C, and + 125'C. The un~ is then classified as a funclion of the worst case T.C. from 25'C to
- 55'C, or 25'C to +125'C.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY DSLiGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typIcs/ values havs bB6n ~ but arB not tssted.

6·40

Section 7 -

Operational Amplifiers
ICH8500/ A ............. 7-1
ICL7600 ............•... 7-7
ICL7601 ................ 7-7
ICL7605 ............... 7-19
ICL7606 ............... 7-19
ICL76XX .............. 7-31
ICL7650 ............... 7-46
ICL7650S •............ 7-54
ICL7652 .....•......... 7-64
ICL7652S ............. 7-72
ICL8007 ............... 7-82
ICL8021 ............... 7-86
ICL8023 ............... 7-86
ICL8043 ............... 7-91
ICL8063 ............... 7-99
LM4250 .....•........ 7-108

•

D~DIlI

ICH8500/A
Ultra Low Input-Bias
Operational Amplifier

CII

o

GENERAL DESCRIPTION

FEATURES

The ICH8500 and ICH8500A are hybrid circuits designed
for ultra low input bias current operational amplifier applications. They are ideally suited for analog and electrometer
applications where high input resistance and low input current are of prime importance.
Functionally, they are pin for pin identical to the popular
741 monolithic amplifier. These amplifiers are unconditionally stable and the input offset voltage can be adjusted to
zero with an external 20kO potentiometer. The input bias
current for the inverting and noninverting inputs is 0.1 pA
maximum for the ICH8500, and 0.01pA maximum for the
ICH8500A.
Pin 8 is connected to the case. This permits the deSigner
to operate the case at any desired potential. This is the key
to achieving the ultra low input currents associated with
these two amplifiers. Forcing the case to the same potential
as the inputs eliminates current flow between the case and
the input pins, and leakage currents that may have otherwise existed between any of the other pins and the inputs
are intercepted by the case.

•
•
•
•
•
•

~

Input Diode Protection
Input Bias Current Less Than O.01pA (8500A)
No Frequency Compensation Required
Oftset Voltage Null Capability
Short Circuit Protection
Low Power Consumption

APPLICATIONS
•
•
•
•
•
•
•

Femto Ammeter
Electrometers
Long Time Integrators
Flame Detectors
pH Meters
Proximity Detector
Sample and Hold Circuits

ORDERING INFORMATION
ICH

v'

8500A

TV

L

PACKAGE
TV = TO-99 Metal Can

' - - - - - - - DEVICE TYPE
INTERSIL HYBRID
' - - - - - - - - - - CIRCUIT

CASE

(GUARD)

'K

V·

0303-2

vo

'K

OFFSET
NULL

Figure 2: Pin confl,uration
(Outline dwg V)

12K

0303-1

Figure 1: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typIcs/ VB1ues have beBn chsract6rIzsd but arB not testrJd.

7-1

•

~

o
o

10
CD

~

ICH8500/A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................. ±18V
Internal Power Dissipation (1) ...•....•.•.......• 500mW
Differential Voltage . . . .. .. . .. .. .. .. . . .. .. .. .. ... ± 0.5V
Storage Temperature •...••.•.••••.•• -65°C to + 150"C
Operating Temperature .•...•••.....•• -25°C to +85°C
Lead Temperature (Soldering,10sec) ••.•...•••••• 3WC
Output Short Circuit Duration .........••..••... Indefinite

NOTE: Stresses above thoss /istsd under ''Absolute MsxImum Ratings"
may CSUS9 permsnsnt dsmsgs I<> the dsvlce. These are stress ratings only
and functlonsl operslion of the dsvlce at these or any other conditions
above thoSfJ indicated In the operslionsl SfJCtions of the specificstlons is not
imp/iBd. Exposurs I<> absolute maximum rating conditions for extBndsd periods may afflict dsvIce rellsbUiIy.

Note: 1. Rating applies for ambient temperature 10 + 70"C

ELECTRICAL CHARACTERISTICS
Symbol

IBIAS
VOS

Characteristics
Input Bias Current
(Inverting and Non-Inverting)

(TA= 25°C unless otherwise specified, VSUPPLY= ± 15V)

Test
Conditions

ICH8500
Min

Case at same
potential as inputs

AVO
CMVR

Min

Typ

±75

Input Offset Voltage

Units
Max
±0.Q1

pA

±50

mV

±50

±50

mV

+25to +85°C
-25 to +25°C

±200

±100

mV

Long Term Input Offset
Voltage Stability

At 25°C

±3.0

±3.0

mV

Common Mode Rejection Ratio

±5 volts common
mode voltage

75

75

dB

Output Voltage Swing

RL~10kO

Change in Input Offset
I:.vos/AT
Voltage Over Temperature

CMRR

ICH8500A
Max
±0.1

Offset Voltage Adjustment Range 20kO Potentiometer

AVOS/At

Typ

Common Mode Voltage Range

±11

± 11

V

±10

±10

V
105

-

Case guarded

0.1

0.1

pF

Slew Rate

RL~2kO

0.5

0.5

Vlp-s

CIN

Input CapaCitance

Case guarded

0.7

0.7

pF

CIN

Input CapaCitance

Case grounded

1.5

1.5

pF

AVOL

Large Signal Voltage Gain

Ctb

Feedback Capacitance

SR

VOLTAGE OFFSET NULL CIRCUIT

20,000

105

VOLTAGE FOLLOWER

20,000

LOW LEVEL CURRENT
MEASURING CIRCUIT

"""'"

Yo ~ 1 VOlT/pA
·'012,11N

CASE
GUARD

v-

0303-4
0303-5

0303-3

NOTE: Adjust input offset voltage 10 OV±10"V before measuring leakage.

Figure 3: Circuit Notes

INTERSIL'S SOLE AND EXCLUSIVE WARRAN1Y OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANnES OF
MERCHANTABILITY AND FITNESS FOR A PARnCULAR USE.
NOTE: AN typics/ vaIuss have bfIBIJ chsracterIzBd but IIfS not t88t6d.

7-2

ICH8500/A
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP VOLTAGE GAIN vs.
FREQUENCY

INPUT VOLTAGE RANGE VB. SUPPLY
VOLTAGE

,"
10'

v; ..... I'15v

I'-.

TA· +25"C

w

"-

"-

w

~

100

1k

i

r"-.

>-

"

1

10

~

.."'"
Z

10k

lOOk

~

,,0

'. ,

~

I

10

11

80

~

75

~
13

.o

i

I
(141't

12

.
~

I

+2S o C" TA" +8SoC

85

, ,;;J ;;... I-"

z
o

I

-10

9

9

J.
C~
¢~

I
-. ~/VE

-I' S

1M

COMMON MODE REJECTION RATIO
VB. SUPPLY VOLTAGE

-

14

15

-I-"

70

i-" ~

~
~

65

'"

8'"
16

5 VOLT COMMON
MODE VOLTAGE

60

10

8

SUPPLY VOLTAGE (:tV)

FREQUENCY (Hz)

0303-6

INPUT OFFSET VOLTAGE VB. SUPPLY
VOLTAGE

11

12

VB.
100

4;VSU~PLY""~

~

"

TA ' ,'\;"C

~

w

90

>-

~

~

0

F-

80

~

I;::: r-

'j"'2'

8

11

12

13

14

15

16

8

9

10

11

12

13

;ii:!$

::"
"
0

g
14

15

°87-~-7.'0~1~1~172~173~1~4~15~~'6

16

SUPPLY VOLTAGE ('VI

SUPPL y VOLTAGE (zV)

0303-9

0303-10

± QUIESCENT SUPPLY CURRENT VB.

INPUT REFERRED
NOISE VOLTAGE

SUPPLY VOLTAGE
500

~
~

w

'""
!:;
0

>

300

1\

60

"

~z
0

t
~"

200

~

o

0303-11

POWER CONSUMPTION VB. SUPPLY
VOLTAGE

~s'·' :00'...

400

i5
100
Z

10

SUPPLY VOLTAGE t:tV}

",

~~

"

ro~~~--~~--~~~--~.

10

SUPPLY VOLTAGE ItVl

... \OIf.Q.

~"

'!;

4

10

~

OC

~~

1

Z

"f", s-tSs°c..:::

1\
100

16

0303-8

SUPPLY VOLTAGE

.~

15

OUTPUT VOLTAGE SWING VB.
SUPPLY VOLTAGE

"

>-

14

0303-7

;;
E

>

13

SUPPLY VOLTAGE {'VI

± POWER SUPPLY REJECTION RATIO

IOr--r-;--;--;--;--r-;--,

~"
0

;;..... l-

8

i

N..
1k

!
10k

lOOk

FREQUENCY 1Hz)

40

20

~

10

o

8

?

~

10

~
.,fJ~t. - -

iIff
~

30

'1

.'

,~

12

13

14

15

16

SUPPLYVClTAGE (tV)

0303-13

0303-12

50

0303-14

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but Brs not tested.

7-3

•

~
o
o

.D~DIL

ICH8500/A

10
CD APPLICATIONS

z

2

that may otherwise exist between the ± 15V input terminals
and the inverting input summing junctions. Feedback capacitance" should be kept to a minimum in order to maximize
the response time of the circuit to step function input currents. The time constant of the Circuit is approximately the
product of the feedback capacitance Clb times the feedback resistor Rib. For instance, the time constant of the
circuit in Figure 4 is 1 sec if Clb= 1pF. Thus, it takes approximately 5 sec (5 time constants) for the circuit to stabilize to
within 1% of its final output voltage after a step function of
input current has been applied. Ctb of less than 0.2 to 0.3pF
can be achieved with proper circuit layout. A practical pico
ammeter circuit is illustrated in Figure 5.

The PI co Ammeter
A very sensitive pico ammeter can be constructed with
the ICH8500. The basic circuit (illustrated in Figure 4) employs the amplifier in the inverting or current summing
mode.
Care must be taken to eliminate any stray currents from
flowing into the current summing node. This can be accomplished by forcing all pOints surrounding the input to the
same potential as the input. In this case the potential of the
input is at virtual ground, or OV. Therefore, the case of the
device is grounded to intercept any stray leakage currents

Rfb" lQ12Q

CURRENT

SOURCE

>----......--_

CURRENT/

OUTPUT

Vo" ~ltN Rrb

SUMMING
NODE

"·1 VOlT/pA

0303-15

Figure 4: Basic Pico Ammeter Circuit

.15V

-

R,
,MO

I~UT>---~-~~~--~>-----'-------------~

',.

CR,

~----~----~--------'OV~UT
"'." -'IN I( 10'20
".1 VOl.T/f)A

INTERNAL.

DioDeS

-15V

0303-16

Figure 5: Plco Ammeter Circuit
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANl)ABILlTY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have be8n characterfzed but are not tested.

7-4

ICH8500/A
Rtb CAN BE REDUCED TO 10K
IF CIRCUIT IS EMPLOYED AS
AN INTEGRATOR

RIO

'0.01%
OG""
fft!PUTTERMiNAL

IFCIItCUIT

AS AN

CHARGE

:~~::~~~~~ r~'IM..--t----------..,

STOR"'"
CAPACITOR

VtN-OT01'OV

/
SW,

INPUT ~FE~.~~~~i

IT1700
l00kU

AS . .-::::LL~:~g r-·"··I/'''---t------i
HOLD CIRCUIT

8

V'N-OTO='0V

...

"'SV

.....-- OUTPUT

>-~-

ITI700

,

V't-_'"Skl/'n..----__-1::
SAMI"LE
PULSEOA

1T1700

CAPACITOR
DISCHARGE
PUCS.

15kn

-=

_15V

Figure 6: Sample and Hold Circuit or Integrator Circuit
The internal diodes CR1 and CR2 together with external
resistor R1 protect the input stage of the amplifier from voltage transients. The two diodes contribute no error currents,
since under normal operating conditions there is no voltage
across them.

0303-17

gate of switch SW2 are zero or near zero when the circuit is
in the hold mode. Careful construction will eliminate stray
resistance paths and capacitor resistance can be eliminated
if a quality capacitor is selected. The net result is a low drift
sample and hold circuit.
As an example, suppose the leakage current due to all
sources flowing into the current summing node of the sample and hold circuit is 100pA. The rate of change of the
voltage across the 0.01 fLF storage capacitor is then 1OmV /
sec. In contrast, if an operational amplifier which exhibited
an input bias current of 1nA were employed, the rate of
change of the voltage across CSTO would be O.W /sec. An
error build up such as this could not be tolerated in most
applications.
Waveforms illustrating the operation of the sample and
hold circuit are shown in Figure 7.

*Feedback capacitance is the capacitance between the output and the inverting input terminal of the amplifier.

Sample and Hold Circuit
The basic principle of this circuit (Figure 6) is to rapidly
charge a capacitor CSTO to a voltage equal to an input signal. The input signal is then electrically disconnected from
the capacitor with the charge still remaining on CSTO. Since
CSTO is in the negative feedback loop of the operational
amplifier, the output voltage of the amplifier is equal to the
voltage across the capacitor. Ideally, the voltage across
CSTO should remain constant, causing the output of the amplifier to remain constant as well. However, the voltage
across CSTO will decay at a rate proportional to the current
being injected or taken out of the current summing node of
the amplifier. This current can come from four sources:
leakage resistance of CSTO, leakage current due to the solid state switch SW2, currents due to high resistance paths
on the circuit fixture, and most important, bias current of the
operational amplifier. If the ICH8500A operational amplifier
is employed, this bias current is almost non-existant
«O.01pA). Note that the voltages on the source, drain and

The Gated Integrator
The circuit in Figure 6 can double as an integrator. In this
application the input voltage is applied to the integrator input terminal. The time constant of the circuit is the product
of R1 and CSTO. Because of the low leakage current associated with the ICH8500 and ICH8500A, very large values of
R1 (Up to 1012 ohms) can be employed. This permits the
use of small values of integrating capacitor (CSTO) in applications that require long time delays. Waveforms for the
integrator circuit are illustrated in Figure 8.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are not tested.

7-5

•

ICH8500/A
~

+IV
VIN

.,

••• _ •• _ •.••

~

0.....1

VIN

"5v~TIME­
01

V,

dl

V,
Va

+l&VIL.0"""

TIME_

b)

v,

·10V

-16V

el

~
•••••••••••••
~

+5V

0-,1\

-15v

'I

V,

o~
I

-16V

, .....- -.....,

".V~I
I
I

dl

v,

-15V

-16V

STATE OF
SWI
STATE OF

SW'

II

CLOSED

II

~""'OPEN

OPEN

I

II
II CLOSED

.Ibiit

f-CLOSED--I
~

-

.,

UH

OPEN

~=LEWINDOW

OP.AMP.

0 _ _ _'__ _ _ _

g)

INTE~~:~;

II

II

CLOSED

II

II CLOSED

OPEN

f-CLOSED-i

~OPEN_'II'IL.::e",,,,,__

I

""EN

~=LEWINDOW

0 _ _ _ _ _ _ _ _ _ _ __

INPUT -10V

!oo.
_ _ _ _ _ __

0,,- -----------+lV--

STATE OF
SWI
STATE OF
SW'

.

INPUTTO "ev - - - - - - - - " ' \ .

OUTPUT

hi

II

I

.,5VI'L-'
i

V'N
vo· - ReSTO I" 0,' VOLTISEC.

'--

-1._-_::=-__.- ___ _
0303-18

0303-19

Figure 7: Sample and Hold
Circuit Waveforms

Figure 8: Gated Integrator Waveforms

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATLITORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical VQ/ws havs bHn chsrsctsrIZfId but SfS not IsstfJd.

7-6

D~Dlbe

ICL7600/lCL7601
Com mutating Auto-Zero (CAZ)
Operational Amplifier

ell

~

GENERAL DESCRIPTION

FEATURES

The ICL7600/1CL7601 commutating auto-zero (CAZ) operational amplifiers are designed to replace almost any of
today's hybrid or monolithic ultra-low offset op amps, and
will provide almost three orders of magnitude reduction in
input offset voltage compared with conventional device designs. This is achieved through Intersil's CAZ amp principle,
an entirely new approach to low-frequency operational amplifier design.
The key feature of the CAZ principle is automatic compensation for long-term drift phenomena and temperature
effects. Two internal op amps are connected so that when
one amplifier is processing an input signal the other is maintained in an "auto-zero" mode. The ICL7600llCL7601 contains all of the circuitry required for system operation, including an oscillator, a counter, level translators, analog
switches and operational amplifiers. Only two auto-zero capaCitors are needed for complete operational amplifier function. Control of the oscillator and counter section is provided through the OSC and DR (division ratiO) terminals. Internal biasing of the two on-chip op amps is programmable
through a three-voltage-level terminal deSignated BIAS.
The ICL7600 is internally-compensated and is intended
for applications which require voltage gains from unity
through 20. The uncompensated ICL7601 is intended for
those situations which require voltage gains of greater than
20. Major advantage of the ICL7601 over the ICL7600 at
high gain settings is the reduction in commutation noise and
subsequent greater accuracy.
Minimum periodic adjustments and extremely low offset
voltage and temperature coefficients make the CAZ operational amplifiers very desirable for operation in adverse environments (temperature, humidity, toxic or radioactive)
where equipment service is difficult. Since the device will
auto-zero its internal offset errors, no adjustment is required
other than that of gain, which is established by the external
resistors.

• Exceptionally low Input offset voltag-s p. V
• Low long-term Input offset voltage drlft0.2 P.VIyear
• Low Input offset voltage temperature drlft-D.OO5

C1

DB

C1

N/C

+INPUT

AZ
-INPUT

p'vrc

±2V
• Statio-protected Inputa-no special handling
required
• Fabricated using proprietary MAXCMOSTM
technology
• Compensated (ICL7600) or uncompensated
(lCL7601) versions

ORDERING INFORMATION
Part Number

Temperature Range

ICL7600lJD
ICL7600MJD
ICL76011JD
ICL7601MJD

-

25°C to
55°C to
25°C to
55°C to

+ 85°C
+ 125°C
+ 85°C
+ 125°C

Package
14 Lead CERDIP
14 Lead CERDIP
14 Lead CERDIP
14 Lead CERDIP

OSC

OUTPUT

BIAS

C2

V0105-1

(outline dwg JO, PO)
Figure 1: Pin Configuration

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
302050-001

NOTE: All typ/cBI Vlli1J6s iNJve been _ _ bulsro nottostsd.

ell

...o

• Low DC Input bias current-300 pA
• Low DC Input offset bias current-150 pA
• Wide common mode and differential Input voltage
ranges
• Excellent low supply voltage operation-Down to

or

C2

P
...

7-7

•

...o
...G

ICL 7 600/lCL 7601

~ ABSOLUTE MAXIMUM RATINGS
....

o
o
G

!:i

S:!

Operating Temperature Range
ICL760XI ..........•......•.....•... - 25'C to + 85'C
ICL760XM ........•............•.•. - 55'C to + 125'C
Storage Temperature Range ..........•.. - 55 to + 1500C
Lead Temperature (soldering, 60 seconds) ....... + 3000C

Total Supply Voltage (sum of both positive and
negative supply voltages, V+ and V-) ......... 18 Volts
DRlnputVoltage •.....•..... (V+ +0.3)to(V+ -8) Volts
Input Voltage (Cl C2 + INPUT, -INPUT, BIAS,
OSC(Note1).: .. : ....... (V+ +0.3) to (V- -0.3) Volts
Differential Input Voltage (Note 1) ±(V+ +0.3) to (V- -0.3)
Duration of Output Short Circuit (Note 2) ......... Unlimited
Continuous Total Power Dissipation at or below + 25'C
free air temperature (Note 3)
CERDIP Package ...............•.....•.•.... 500 mW

NOTE: Stresses above Ihose listed undar "Absolute Maximum Ratings"
may cause permanent damage to the davies. These are stress ratings only
and functional operation of the d9vies at these or any other condItIona
above Ihose Indicated In the operational sections of the spaclfications Is not
implied. Exposure to absolute maximum rating conditions for _ p e r i .
ods may affect d9vies reliability.

NOTE 1: An SCR structure is inherent in the CMOS process used in the fabrication of these devicss. If voltages in excess of (V+ +0.3) to (V- -0.3) volts are
connected to e~her Inputs or outputs, destructive latchup can occur. For this reason ~ is recommended that no inputs from sources not on the same
power supply or supplies be applied before the ICL7600/ICL7601 supplies are established. and that if multiple supplies are used the ICL7600/ICL7601
supplies be activated first. No restrictions are placed on the differential input voltages on either the inverting or non·inverting inputs, so long as these
voltages do not exceed the power supply voltages by more than 0.3V.

2: Outputs may be shorted to ground (GND) or to either supply (V+ , V-). Temperature and/or supply vo~ages must be

lim~d

to insure that the dissipetion

rating is not exceeded.

3: For operation above 25'C free-air temperature, derate 4mW/'C from 500mW for CERDIP and 3mWI'C from 375mW for plastiC.
BIAI (CONTROL)
C,

AI

QUTPUT

INPUT

oac

(OSCILLATOR)

0105-2

Figure 2: Functional Diagram
y+
DR (DIVISION RATIO)
OSC

NON-INVERTING
INPUT

+

AUTO-ZERO
INPUT

AZ

OUTPUT

IN'I!lmNG
INPUT

0105-3

Figure 3: Symbol

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNEss FOR A PARTICULAR USE.

NOTE: All typ/c8I . ._

have been charscl9rized but _

not toslBd.

7-8

.D~DI!..

ICL 7600/lCL 7601

n
...
....

GI

o

ELECTRICAL CHARACTERISTICS
Test Conditions: V+ = +5 volts, V- = -5 volts, TA
Test Circuit 1, unless otherwise specified.
Symbol

Vos

Test Conditions

Parameter

Input Offset Voltage

= + 25'C, DR pin connected toV+ (fCOM "'160Hz), C1 = C2 = 1fA-F,

Low Bias Setting
Med Bias Setting
High Bias Setting
Med Bias Setting

Rss 1kO
C1 = C2 = 1fA-F
MIL version over temp.

Long Term Input Offset
VosTime Voltage Stability

Min

Typ

Max

±2
±5
±7

±10
±40

Low or Med Bias Settings

0.2

Units

fA-V
fA-V
fA-V
fA-V

Average Input Offset
Voltage Temperature
Coefficient (Note 4)

Low or Med Bias Settings -55'C > TA > +25'C
+25'C > TA > +85'C
+ 25'C > TA > + 125'C

en

Noise Voltage (RMS)

BandWidth
0.1 to 10Hz
Rss 1kO

Low Bias
Med Bias
High Bias

0.8
0.8
1.0

fA-V
fA-V
fA-V

enp - p

Equivalent Input
Noise Voltage
Peak-to-peak

BandWidth
0.1 to 10Hz
Rss 1kO

Low Bias
Med Bias
High Bias

4.0
4.0
5.0

fA-V
fA-V
fA-V

en10

Spot equivalent
Noise voltage

f

= 10Hz

Band Width 1Hz

700

nV/yHz

in10

Spot equivalent
Noise Current

f

= 10Hz

Band Width 1Hz

0.1

pA/YHz

DIFVIN

Differential Input
Voltage Range

V+ +0.3

V

+4.2
+4.0
+3.5

V
V
V

V- -0.3

to

CMRR

Common Mode
Rejection Ratio

Any Bias Setting

88

dB

PSRR

Power Supply
Rejection Ratio

Any Bias Setting

110

dB

INIB

Non Inverting Input
Bias Current

Any Bias Setting,
(includes charge injection currents)

0.300

3

nA

liB

Inverting Input Bias
Current

Any Bias Setting,
(includes charge injection currents)

0.150

1.5

nA

Av

Voltage Gain

RL

VOUT

Maximum Output Voltage RL
Swing
RL
RL

= 10kO

Low Bias
Med Bias
High Bias

105
105
100

dB
dB
dB

= 1MO

±4.9

= 100kO

±4.8

V
V
V
V
V
V

Positive Swing
Negative Swing

90
90
80

+4.4
-4.5

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have b8en characteJ1z6d but are not testsd.

7-9

....

GI

...

o

fA-VI'C
fA-VI'C
fA-VI'C

Low Bias
Med Bias
High Bias

= 100kO

-4.2
-4.0
-3.5

0.2
0.2
0.2

Common Mode
Input Range

CMVR

n
...

fA-V/year

TCVos

0.005
0.Q1
0.05

o
.....

•

oco ICL 7600IICL 7 601

1Il0~OIl.

........

2

o ELECTRICAL CHARACTERISTICS
=
= ~

........

2

(Continued)
Test Conditions: V +
+ 5 volts, V 5 volts, TA = + 25°C, DR pin connected to V + (fCOM '" 160Hz), Cl
Test Circuit 1, unless otherwise specified .

Symbol
SR

GBW

GBW

Test Conditions

Parameter
Large Signal Slew Rate

Min

Typ

=

C2

Max

=

1p.F,

Units

Unity
Gain
ICL7600

High Bias Setting
Med Bias Setting
Low Bias Setting

1.8
0.5
0.2

V/p.s

ICL7600
Test Circuit 2

High Bias Setting
Med Bias Setting
Low Bias Setting

1.2
0.3
0.12

MHz
MHz
MHz

High Bias Setting
Med Bias Setting
Low Bias Setting

1.8
0.4
0.2

MHz
MHz
MHz

Unity Gain Band Width

V/p.s
V/p.s

Extrapolated Unity
Gain Band Width

ICL7601

ISlAS

BIAS Terminal Input Current

V- -0.3S; VSIAS:;;; V+ +0.3 volt

VSH

BIAS Voltage to Define
Current Modes

Low Bias Setting

V+ -0.3

V+

V+ +0.3

V

Med Bias Setting
High Bias Setting

V- +1.4
V- -0.3

GND
V-

V+ -1.4

V
V

VSM
VSL

±30

IDR

DR (Division Ratio)
Input Current

V+ -8.0V :;;; VDR :;;; V+ +0.3V

VDRH

DR Voltage to define
oscillator division
ratio

Internal oscillator division ratio 32

V+ -0.3

Internal oscillator division ratio 2

V+ -8

feOM

Nominal Commutation
Frequency

Cose = OpF

Is

Supply Current

High Bias Setting
Medium Bias Setting
Low Bias Setting

VDRL

V+ -V- Operating Supply Voltage
Range

V- +0.3

±30

DR Connected to V+
DR Connected to GND

High Bias Setting
Medium or Low Bias Setting

pA

pA
V+ +0.3
V+ -1.4

160
2560
7
1.7
0.6
5
4

V
V
Hz
Hz

15
5
1.5

mA
mA
mA

16
16

V
V

NOTE 4: For design only. not tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values hsvs been characttnizsd but tlf8 not 18Sted.

7-10

ICL 7 600/lCL 7601
oV+

oV+

141---o--'~

13
V1No-.....- - - - - !

12

11
10

OGNO

N/e

13

------------:1-Cosc
v+
I
oV+ -=

V1No-.....- - - - - !

12
11
10

Your

V-

OGNO

N/e

------------l
v+
,ICosc
oV+ -=

OV-~

Your

V-

OV-~

lk

0105-5

Test Circuit 2: Unity Voltage Gain
0105-4

Test Circuit 1: Voltage Gain = 1000
oV+
141----0-13
V1No-.....- - - - - !

12
11

OGNO

N/C

------------:1-

10

v·

ICoSC

Vour oV+

-=

v-

OV-~

18Dk

2Dk

0105-6

Test Circuit 3: Voltage Gain = 10

v·

15Dk 15Dk 15Dk
INPUTQ-JWv.-WW""",..,..po--....
0.1 pF
0.1 pF

VOUT

0105-7

Test Circuit 4: DC to 10Hz Unity Gain Low Pass Filter
Figure 4: Test Circuits

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values haVB besn characterized but arB not tested.

7-11

•

...o
CD

ICL 7600/ICL 7601

....

d
::::.

TYPICAL PERFORMANCE CHARACTERISTICS

o

o

INPUT OFFSET VOLTAGE AS A
FUNCTION OF AMBIENT
TEMPERATURE

CD
....

g

V-· NIGATIVE POWER SUPPLY VOLTAGE·-V

TI~T CIJCUIT I,
C, = c. = '.F
'COM = 110Hz

-7'

./
0

21

-1.5

....

-35

-25

=:.

':.

50

7S

C"C2

= 1.0p.F

~

-1.0

L__

~

=N.2lr,!2,L4A.2~-=
I

+2.5

100 125

+3.5

+4.5

+5.5

1;;;l~",r-l7f-fhlf-i<'t++--l7.5 !

II

=

+1.5

5

l!

+7.5

~

Rna""..rn-I-IoI'I-:;~:!:-:'::!t:-I5.0

l!

2.5

d

°

i

•

10

100

1k

0105-10

0105-9

INPUT OFFSET VOLTAGE AND
PK TO PK NOISE AS A
FUNCTION OF SUPPLY VOLTAGE
(V+ - V-)

INPUT CURRENT AS A
FUNCTION OF COMMUTATION
FREQUENCY

1- 500
! '-450
i E-4OO

-7
TA'" 25"C
Ay ... 1000
AsS; 1kn

f-- -

!-15
~

f--

C!'V~j: !~,~,( i - -

f-- -

tCOM

== 180Hz

r°i.---"1I\

-

!V+}!J:'

id-Loo

-

~-1

>

I

°2

4

•

'i
~E-150

....
•

10

11

14

0105-12

"-

"'" ......

0105-13

SUPPLY CURRENT
AS A FUNCTION
OF SUPPLY VOLTAGE

-

-

/

'"'" INVERTING
INPUT CURRENT
0
10
100
1000
ICOM· COMMUTATION FREQUENCY· HI

MAXIMUM OUTPUT VOLTAGE AS
A FUNCTION OF OUTPUT
LOAD RESISTANCE

Ivl~:12!,~0 V

)I

I..0

IY+·Y-I • SUPPLY YOLTAQI!· V

0105-11

\ I

.!15-100

NOISE V )l.TA E

I

INii NON INVERTING
INPUT CURRENT

260

t-t+!+-+--1~-+++t-I

I
I

I

I III

1=1- 360

7

~~~OLTS

Z--200

./

1011

'COM' COMMUTA.TION FREQUENCY - Hz

v+· POSIT'YE POWER SUPPLY VOLTAGE· V

INPUT OFFSET VOLTAGE AND
PK TO PK NOISE
VOLTAGE AS A FUNCTION OF
COMMUTATION FREQUENCY
(Ct C2 = O.lJLF)

+5

c

,... ~

'"

0-2.0

i

I!

i

1-f+J~*'"-t;;:!;ti--J.-Hq..;:H 12.5 11/

/

0105-8

-I

17.5
15.0

Iv+·v-! ~ 10VOLTS
'COM - 110Hz
OFFaE VOLTAGE

i~ -3.0

T•• AMBIENT TEMPERATURE· ·C

i

-20 r-TT".--;==..-.r-nrTT''"'''I 20.• ':.

Ay = 1000
RS:S: 1kO

~-4.•

II
-to -21

.....

TA - 25"C

J

-4

INPUT OFFSET VOLTAGE AND
PK TO PK NOISE
VOLTAGE AS A FUNCTION OF
COMMUNTATION FREQUENCY
(Ct C2 = 1p.F)

INPUT OFFSET VOLTAGE AND
PK TO PK NOISE
VOLTAGE AS A FUNCTION OF
SUPPLY VOLTAGES

J..- . /
"

.....HIBIA8
fA:O: 25°C
NO LOADNO INPUT

-

-

RL CONNECTED TO GND _

,.... 1'-0.
lk
10k
R, • LOAD RESISTANCE

1

~

...

MED BIA&
LO BIAS
4

lOOk

•

•

10

12

,.

11

Iv+·v-l·suPPLY VOLTAGE· VOLTS
0105-14

0105-15

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE; All typical values havs bgen Characterized but af9 not tested.

7·12

.D~OI!..

ICL 7 600/ICL 7601
OSCILLATOR FREQUENCY AS
A FUNCTION OF EXTERNAL
CAPACITIVE LOADING

SUPPLY CURRENT AS A
FUNCTION OF TEMPERATURE

.....

.iii
II:
II:

-...l
HI,t.U

I III

r---... ~

Y+-V- = 10 VOLTS
NO LOAD
NO INPUT

B4

I

"IV+~n :~~YOLTS=

For Case ...... 0 pF

r--

r- ~

MI!DIlAI

o

-iIO

-n

n

0

50

7S

-

r-In

100

10

1\
10

1

0105-16

TOTAL EQUIVALENT INPUT OFFSET
VOLTAGE AS A FUNCTION OF
SOURCE IMPEDANCE- + INPUT

~'IY+-v",.~ -~ 2SOC
10 YOLTS
'COM ~ 180Hz ~+100
IIII I III
II
~
~

':"':"

3
100

100

0105-18

I

"'-30

t'0
~

~ -3.0 HH-H-fH-+-+-It.i<+--+-f+-I+--I

~

~

.. -1.0 HH-H--I1H-+""'-l+++-+-f+-I+--I

~+1.0

i+ o.

20 304050

~-100

I

~

10

,- fAI!QUI!NCY - Hz

~

/

~+3.0

3 4 I

-300~rr~~~-T~rr~~~

I

Asf i ! jAZ
oRI
+10

2

1000

TOTAL EQUIVALENT INPUT OFFSET
VOLTAGE AS A FUNCTION OF
SOURCE IMPEDANCE--INPUT

au +30

i~

100

0105-17

+300

i_

/
Ik

10k

n
r-

\

Cosc - OSCILLATOA CAPACITANCE - pF

T. - AMBIENT TEMPERATUAE·C

o
~

...o

1\
\
1\

LO BIAII

GI

GI

_~. =lnlJ

'-

....

....

III

,os:, ~15.2lkH'"

.........

5

FREQUENCY RESPONSE
OF THE 10 Hz LOW PASS
FILTER USED TO MEASURE NOISE
(TEST CIRCUIT 4).

P

lOOk

1M

R.,INPUT SERIES RESISTANCE-O

0•3

l00~~~lk~UA~10~k-a~1~00~k~~'M
R•• INPUT SERIES RESISTANCE-O
0105-20

0105-19

DETAILED DESCRIPTION
CAZ Operational Amplifier Operation

voltage equal to the DC offset voltage of that amplifier and
the instantaneous low frequency noise voltage. A short time
later, the analog switches reconnect the on-chip op amps in
the configuration shown in Mode B. In this mode, op amp
if 2 has capaCitor C2 (which was charged to a voltage equal
to its offset and noise voltage) connected in series to its
non-inverting (+) input and nulls out the input offset and
noise voltage of the amplifier. While one of the op amps is
processing the input Signal, the other is placed in the autozero mode and charges its capacitor to a voltage equal to
its equivalent DC and low-frequency error voltage. The internal op amps are reconnected at a rate deSignated as the
commutation frequency, feOM.
The CAZ amp concept offers a number of other advantages to the designer, as compared to standard bipolar or
FET-input op amps:

The CAZ operational amplifier functions on prinCiples
which are very different from those encountered in conventional op amp types. An important advantage of the
ICL7600/lCL7601 devices is the ability to self-compensate
for internal error voltages, whether they are steady-state,
related to temperature or supply voltage, or variable in nature over a long term.
Operation of the ICL7600/lCL7601 CAZ operational amplifier is demonstrated in Figure 5. The basic amplifier configuration represented by the large triangles has one more
input than does a regular op amp-the AZ, or auto-zero input. The voltage at the AZ input is that to which each of the
internal op amps will be auto-zeroed. In Mode A, op amp
if 2 is connected into a unity gain mode through on-chip
analog switches, and charges the external capaCitor C2 to a

INTERSIL'S SOLE AND EXCLUSive WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bsen characterizsd but are not tssted.

7-13

•

i

i...
o
G

...
S:!

ICL 7600/lCL 7601
• Effective input offset voltages can be made between
1000x and 10,OOOx less without trimming.
• Long-term drift phenomena are compensated for and dramatically reduced.
• Temperature effects are compensated for over a wide
range. Reductions can be as high as 100 times or higher.
• Supply voltage sensitivity is reduced.

The on-chip op amps are connected internally to the external input and output terminals via CMOS analog
switches, as shown in Figure 6. The analog switch structure
shown in Figure 6 is arranged so that at any time three
switches are open and three switches are conducting. Each
analog switch includes a P-channel transistor in parallel with
an N-channel transistor.

+INI'UT
AI

~

________~~OU=TPUT

v-~________~~OU:TPU'

-INPUT

0105-21

Figure 5: Diagramatic Representation of the 2 Half Cycles of Operation of the CAZ OP AMP

Cl--+---......- - - I
Cl--+-+'::--"

> ......-{X.J------OUTPUT

+INPUT

Rr
(100 k.n)

AI

-INPUT--------~----JW_----'

~ INPUT

(COt.lt.lUTATION

a:

~REOUENCY)

CL

0105-22

Figure 6: Schematic of Analog Switches Connecting Each Internal
OP AMP to the External Inputs and Output

INTERSlL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SiHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
.
NOTE: AN typ/c8J _

.... been chsrIlc1srIzed but.,. not-'

7-14

IIU~Un.

n
r-

This implies a gain of at least 10 for the CAZ op amp preamplifier.
On the other hand, if the gain of the CAZ op amp is increased too much, its output swing will be limited by the
± 5V supplies. This condition imposes a maximum gain of
200 to produce an output of ± 0.000005 times 4,096 times
200, or ±4,096V, for a 5,."V per count sensitivity. Use of an
ICL7600 is recommended for low gains «20) and the
ICL7601 for gains of more than 20.
The values of the integrating resistor and the reference
voltage must be chosen to suit the overall sensitivity of the
system. For example, in a system requiring a sensitivity of
5 ,."V per count, use a CAZ amp in a gain configuration o~ 50
(with ICL7601). Thus for a full scale count of 4096 (12 bitS),
the input voltage to the ICL7109 would be 5 ,."V times 50
times 4096 or 1.024 volts. Since the ratio of input to reference is 2:1, the value of the reference voltage becomes
0.512 and a 50 kO integrating resistor is recommended. A
system such as that shown in Figure 7 will allow a resolution
of 1°C for low sensitivity platinum/rhodium junctions. For
0.1°C resolution, use high sensitivity thermocouples having
copper I constantan junctions.
The low-pass filter between the output of the CAZ op
amp and the input of the ICL7109 AID converter can be
used to improve the signal-to-noise ratio of the system by
reducing bandwidth. A 10Hz filter will result in an equiva!ent
peak-to-peak noise voltage figure of 4 ".V. If the bandwidth
is reduced to 1.5 Hz, the peak-to-peak noise voltage will be
reduced to about 1.7 ".V, a reduction by a factor of three.
The penalty for this reduction will be ~ I~nger system ~e­
sponse time; however in most cases this Will. not ~e a major
consideration, because of the large thermal Inertia of many
thermocouple probes.

o
o
.....

ICL 7 600/ICL 7601
APPLICATIONS
The ICL7600/lCL7601 CAZ op amp is ideal for use as a
front-end preamplifier for dual-slope AID converters which
require high sensitivity for single-ended input sources such
as thermocouples.
A typical high-sensitivity AID converter system is shown
in Figure 7. The system uses an Intersil ICL7109 12-bit
monolithic AID binary converter, and is intended for direct
interface with microprocessors. Both the ICL7600/lCL7601
and the ICL7109 use power supply voltages of ± 5V, and
the entire system consumes typically 2.5 mA of current.
The input signal is applied through a low-pass filter (150
Hz) to the CAZ op amp, which is connected in. a non-inve~­
ing gain configuration of either 10 or 100. The Internal oscIllator of the CAZ amp is allowed to run free at about 5,200
Hz, resulting in a commutation frequency of 160 Hz, wit~ the
DR terminal connected to V + . The error-storage capacitors
C, and C2 are each 1 ,."F value, and provide a good compromise between the minimum equivalent input offset voltage and the lowest value of low-frequency noise.
The output signal is then passed through a low-pass filter
(1 MO and 0.1 ,."F), with a bandwidth of 1.5 Hz. This results
in an equivalent DC offset voltage of 1 ,."V to 2 ,."V, and a
peak-to-peak noise voltage of 1.7 ,."V, referred to the input
of the CAZ amp. The output from the low-pass filter feeds
directly into the input of the ICL7109.
In a system such as that shown in Figure 7 there is a
degree of flexibility possible in assigning var!ous gains. t?
the ICL7600/lCL7601 pre-amplifier, and to various sensitivIties for the ICL71 09. For optimum performance, the CAZ op
amp must amplify the input signal so that the equivalent,
15 ,."V input noise voltage of the AID converter is masked.

1 GND
2
3
4
5

ICL7600/ICL 7601

INPUT
10k
DIGITAL
110

9BOkIJ (l90klJ)
10k

.".

- -

USE ICL7601 FOR GAIN OF ·20
USE ICL7600 FOR GAIN OF 20

•
••

10
11
12
13
14
15
16

17

:-

18
1•
20

40
39
38
37
38
35

34
ICL7109
31

30
29
28
27

21
25
24
23

22
21

0105-23

Figure 7: AID System with 5)J-V Resolution Using an ICL7600/lCL7601
CAZ AMP Preamplifier and an ICL7109 Dual Slope AID Converter

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR use.

NOTE: All typical values have been characterized but are not tested.

7-15

....G)

n
r....G)

...o

•

o ICL 7600/lCL 7601
...
u SOME HELPFUL HINTS
Ut
~

::::.

Testing the ICL7600/lCL7601 CAZ

Ut

A simple and relatively accurate means of testing the
CAZ op amp is to use a Tektronix Type 577 curve tracer,
with the CAZ op amp inserted in a special 14-lead socket
which plugs into a Tektronix 178, and which contains two
soldered-in auto-zero capacitors of 1 J-tF each. This simple
and convenient tester will provide most of the information
needed for low-frequency parameters. The test setup will
allow resolution of input offset voltages to about 10 J-tV.
For greater accuracy, it is suggested that a breadboard
be built which minimizes thermoelectric effects and which
includes an output low-pass filter of the type shown in Test
Circuit #4. The output from the CAZ amp can be connected
to a dual-slope AID converter as shown in Figure 7. The
low-frequency noise can then be displayed on a storage
scope or on a strip chart recorder.

the recovery edge, as shown in Figure 8. It can be seen that
the effect of the large load capacitor is to produce an area
error in the output waveform, and hence an effective gain
error. The output low pass filter must be a high impedance
type to avoid output voltage area errors. For example, a
1.5 Hz filter should use a 100 kll resistor and a 1.0 J-tF
capacitor, or a 1.0 Mil resistor and an 0.1 J-tF capacitor.
This effect also causes problems with integrator circuits.

o Operational Amplifier
o

...
~

S:!

Oscillator and Digital Considerations
The oscillator has been designed to run free at about
5.2 kHz when the OSC terminal is open-circuited. If the full
divider network is used, this will result in a commutation
frequency of about 160 Hz nominal. The commutation frequency is the frequency at which the on-chip op amps are
switched between the signal processing and the auto-zero
modes. A 160 Hz commutation frequency represents approximately the optimum frequency at which the input offset
voltage is close to minimum, where the low-frequency noise
is acceptable, and where errors derived from noise spikes
will be low. Other commutation frequencies may provide optimization of other parameters, but always to the detriment
of major characteristics.

Bias Control
The on-chip op amps consume over 90% of the power
required for the ICL7600/1CL7601. Three externally-programmable bias levels are provided. These levels are set by
connecting the BIAS terminal to V+, GND or V-, for LOW,
MED of HIGH BIAS levels, respectively. The difference between each bias setting is approximately a factor of three,
which allows a 9: 1 ratio between supply current and the bias
setting. The reason for this current programmability is to
provide the user with a choice of device power dissipation
levels, slew rate values (the higher the slew rate the better
the recovery from commutation spikes), and offset errors
due to chip "voltage drop" and thermoelectric effects (the
higher the power dissipation the higher the input offset error). In most cases, the medium (MED BIAS) setting will be
the best choice.

The oscillator is of a high impedance type, so that a load
of only a few picofarads on the OSC terminal will cause a
significant shift in frequency. It is therefore recommended
that if the desired frequency of the oscillation is 5.2 kHz, the
terminal should be left unattached and open. In other instances, it may be desirable to lock the oscillator to a clock
or to run it at another frequency. The ICL7600/lCL7601 provides two degrees of flexibility. First, the DR (division ratiO)
terminal permits the user to choose between dividing the
oscillator by 32 (DR terminal to V +) or by 2 (DR terminal to
GND), to obtain the commutation frequency. Second, the
oscillator may have its frequency lowered by the addition of
an external capacitor connected between the OSC terminal
and V +, or system ground terminals. For situations which
require the commutation frequency to be locked onto a
master clock, the OSC terminal can be driven from TTL logic (with reSistive pull-up) or from CMOS logiC, provided that
the V + supply (with respect to ground) is + 5V ( ± 10%) and
the logic driver also operates from a similar supply voltage.
This is because the logiC section-including the oscillatoroperates from an internal - 5V supply referenced to V+
generated on-chip, and is not accessible externally.

Output Loading (Resistive)
With a 10 kll load the output swing can cover nearly the
entire supply voltage range, and the device can be used
with loads as low as 2 kll. However, with loads of less than
50 kll, the on-chip op amps become transconductance amplifiers, since their output impedances are about 50 kll
each. Thus the open-loop gain is 20 dB less with a 2 kll
load than it would be with a 20 kn load. For high gain configurations requiring high accuracy, output loads of 100 kll
or more are suggested.

Thermoelectric Effects

Another consideration which must not be overlooked is
the additional power dissipation of the chip which results
from a large output swing into a low value load. This added
variable can affect the initial input offset voltages under certain conditions.

The ultimate limitations to ultra-high-precision DC amplifiers are thermoelectric, Peltier or thermocouple effects in
junctions consisting of various metals, alloys, silicon, etc.
Unless all junctions are at precisely the same temperature,
small thermoelectric voltages will be produced, generally
about 0.1 J-tV;oC. However, these voltages can be several
tens of microvolts per DC for certain thermocouple materials.

Output Loading (Capacitive)
In many applications, it is desirable to include a low-pass
filter at the output to reduce high-frequency noise outside
the signal passband of interest. With conventional op amps,
the obvious solution would be to place a capacitor across
the external feedback resistor to provide the low pass filter.
However, with the CAZ op amp, this is not feasible because of the nature of commutation voltage spikes. The
voltage spikes show a low impedance characteristic in the
direction of the auto-zero voltage, and a high impedance on

In order to realize the extremely low offset voltages which
the CAZ op amp can provide, it is essential to take precautions to avoid temperature gradients. All components
should be enclosed to eliminate air movement across device surfaces. In addition, the supply voltages and power
dissipation should be kept to a minimum. Use the medium
bias mode as well as a high impedance load, and keep well
away from heat dissipated by surrounding equipment.

INTERStL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but 8f9 not test8(/.

7-16

.D~DIL

ICL 7600/ICL 7601

n
I'"

...CII
o

....o
n
I'"

...CII

AA
INPUT

AC

AZ

WAVEFORMS

CAZ
OP At.4P

>-........ OUTPUT

...o

RSOURCE
0105-24

0105-25

Figure 8: Effect of a Load Capacitor on Output Voltage Waveforms
zero mode. Since the input capacitances of the on-Chip op
amps are typically in the 10 pF range, and since it is desirable to reduce the effective input offset voltage about
10,000 times, the offset voltage auto-zero capacitors C1
and C2 must be at least 10,000 x 10 pF, or 0.1 /-tF each.

Component Selection
The two required auto-zero capacitors, C1 and C2, should
each be of 1.0 /-tF value. These are large values for nonelectrolytic capacitors, but since the voltages impressed on
them do not change significantly, problems of dielectric absorption and the like are not important.
Excellent results have been obtained in operation at commercial temperature ranges using several of the smallersize and more economical capacitors, since the absolute
values of the capacitors is not critical. Even polarized electrolytic capacitors rated at 1.0 /-tF/50V, though not recommended, have been used with success.

J~

OUTPUT
VOLTAGE, A
GND

rflVW

3mS - - - I

A .ha

'ftIW .~u

vwiN,"".

!

OJ

1

'vW1"fVw

TIME-

0105-26

Commutating Voltage Transient Effects

Figure 9: Output waveform from Test Circuit 1.

While in most respects the CAZ op amp behaves like a
conventional op amp, its principal applications will be in very
low level, low-frequency preamplifiers limited to DC through
100 Hz. This is because of the finite switching transients
which occur in the input and output terminals due to commutation effects. These transients have a frequency spectrum beginning at the commutation frequency, and include
all of the higher harmonics. If the commutation frequency is
higher than the highest in-band frequency, these transients
can be effectively blanked with a low-pass filter.
The input commutation transients arise when each of the
on-chip op amps experiences a shift in voltage equal to the
input offset voltage(about 5-10 mV) which occurs during
the transition to the signal processing mode from the auto-

The charge which is injected into the op amp when it is
switched into the signal-processing mode produces a rapidly-decaying voltage spike at the input, in addition to an
equivalent DC bias current averaged over a full cycle. This
bias current is directly proportional to the commutation frequency, and in most instances will greatly exceed the inherent leakage currents of the input analog switches, which are
typically about 1.0 pA at ambient temperature of 25'C.
The output waveform of Test Circuit # 1 (with no input) is
shown in Figure 9. Note that the equivalent noise voltage
shown is amplified 1000 times, and that because of the finite slew rate of the on-chip op amps the 7 mV input transients are not amplified by 1000.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIE:S, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE· All typical valuss havs been charscterlzed but are not tested.

7-17

,.

o ICL7600/ICL7601

CO
......

51!
()
o

CO
......

51!

CAZ op amp, the ICL7600 which is compensated for unity
gain and which can be used for gain configurations up to 20,
and the ICL7601, which is uncompensated and recommended for operation in gain configurations greater than 20.
Thus, when a signal is being processed in a high gain configuration, the effective output signal error is greater for the
ICL7600 than it is for the ICL7601.

The output transient voltage effects (as distinct from the
input effects which are propagated through the on-chip op
amps) will occur if there is a difference in the output voltage
of the internal op amps between the auto-zero modes and
the signal-processing modes. The output stage of the onchip op amp must slew from its auto-zero output voltage to
the desired signal-processing output voltage. This is shown
in Figure 10, where the system is auto-zeroed to ground.
The duration of the output transients is greatly affected by
the gain configuration and the bias setting, since these two
parameters have an effect on system slew rate. At low
gains and high bias settings, the output transient durations
are very short. For this reason there are two versions of the

Non-Amplifier Applications
In principle, this is one of the few "chopper-stabilized"
type amplifiers that could be used as a comparator; the
transient effects on the output will normally require careful
synchronism of output strobes with oscillator drive.

VIN ......:F-------~...,..------,:..
INPUT
OUTPUT
VOUT~~--J----~~------~

0105-28

0105-27

Figure 10: Simple CAZ OP AMP Circuit and the Output Voltage Waveform

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but ar9 not tested.

7-18

~DlL.eo

ICL7605/ICL7606

Commutating Auto-Zero (CAZ)
Instrumentation Amplifier

o

....CIt
n

GENERAL DESCRIPTION

FEATURES

The ICL7605/ICL7606 CMOS commutating auto-zero
(CAZ) instrumentation amplifiers are designed to replace
most of today's hybrid or monolithic instrumentation amplifiers. for low frequency applications from DC to 10Hz. This is
made possible by the unique construction of this Intersi! device. which takes an entirely new design approach to low
frequency amplifiers.
Unlike conventional amplifier designs. which employ
three op-amps and require ultra-high accuracy in resistor
tracking and matching. the CAZ instrumentation amplifier
requires no trimming except for gain. The key features of
the CAZ principle involve automatic compensation for longterm drift phenomena and temperature effects. and a flying
capacitor input.
The ICL7605/1CL7606 conSist of two analog sectionsa unity gain differential to single-ended voltage converter
and a CAZ op amp. The first section senses the differential
input and applies it to the CAZ amp section. This section
consists of an operational amplifier circuit which continuously corrects itself for input voltage errors. such as input
offset voltage. temperature effects. and long term drift.
The ICL760511CL7606 is intended for low-frequency operation in applications such as strain gauge amplifiers which
require voltage gains from 1 to 1000 and bandwidths from
DC to 10Hz. Since the CAZ amp automatically corrects itself for internal errors. the only periodic adjustment required
is that of gain. which is established by two external resistors. This. combined with extremely low offset and temperature coefficient figures. makes the CAZ instrumentation amplifier very desirable for operation in severe environments
(temperature. humidity. toxicity. radiation. etc.) where equipment service is difficult.

• Exceptionally Low Input Offset Voltage - 2,..,V
• Low Long Term Input Offset Voltage Drlft-0.2,..,VI
Year
• Low Input Offset Voltage Temperature Coefflclent0.05,..,VI'C
• Wide Common Mode Input Voltage Range - 0.3V
Above Supply Rail
• High Common Mode Rejection Ratio -100 dB
• Operates at Supply Voltages As Low As ± 2V
• Short Circuit Protection On Outputs for ± 5V
Operation
• Static-Protected Inputs - No Special Handling
Required
• Compensated (ICL7605) or Uncompensated
(ICL7606) Versions

9

(outline dwg IN)
0306-1

Figure 1: Pin Configuration

Order parts by the following part numbers:
Part Number

Compensation
INTERNAL
INTERNAL
INTERNAL
EXTERNAL
EXTERNAL
EXTERNAL

Temperature Range

Package

O·Cto +70·C
-25·Cto +85·C
-55·Cto + 125·C
O·Cto +70·C
- 25·C to + 85·C
-55·C to + 125·C

18-PIN CERDIP
18-PIN CERDIP
18-PIN CERDIP
18-PIN CERDIP
18-PIN CERDIP
18-PIN CERDIP

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY ANO FITNESS FOR A PARTICULAR USE.
301681-003

NOTE: All typ;csl values hsvs been characterized but are not tested.

7-19

o

c,

DR
OSC
v+

ORDERING INFORMATION

ICL7605CJN
ICL76051JN
ICL7605MJN
ICL7606CJN
ICL76061JN
ICL7606MJN

o
o

-Dlff IN
+Dlff IN
C3
C3
C,

AZ

-iNPUT

C.
C.
C.
C.
vBIAS
OUTPuT

....

•

8
ICL 7605/ICL 7606
o

...,...

(,)

:::::.
."

o

o,...
...

+OIFFIN

y

-DIFF IN
OUTPUT
AZ
-INPUT

0306-2

Figure 2: Symbol

r'f
+DIFF IN
-OIFF IN

o~

CAZ
OP
AMP
INPUT
AZ ANALOG
SWITCH
SECTION

DIFFERENTIAL
TO SINGLE
ENDED VOLTAGE
CONVERTER
ANALOG
SWITCH
SECTION

AMP

-

RF1

RF2

~

!

AZ

RC
OSCILLATOR

I

CAZ
OP
AMP
OUTPUT
ANALOG
SWITCH
SECTION

---0-0

OUTPUT

A~ 1

-INPUT

I

I

#1

...A

~

--

OSC

1

BIAS

~

+

C'!

+2 OR +32
DIVIDER NETWORK

t
~

rl
Y

~

LEVEL
TRANSLATORS

+2

!

1

LEVEL
,
TRANSLATORS

JR

r

STABILIZED
POWER
SUPPLY

I

(DIVISION RATIO)

L
0306-3

Figure 3: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical va/uss have been characterized but are not tested.

7·20

ICL 7605/ICL 7606
ABSOLUTE MAXIMUM RATINGS
Continuous Total Power Dissipation (Note 4) ..... 500mW
Operating Temperature Range:
ICL7605/1CL7606C ...................... 0 to + 70"C
ICL7605/1CL76061 .................. -25"Cto +S5"C
ICL760S/ICL7606M ............... - 55"C to + 125°C
Storage Temperature Range .......... - 65"C to + 150"C
Lead Temperature (Soldering, 10sec) ............. 300"C

Total Supply Voltage (V+ to V-) ................... 1SV
DRlnputVoltage ............... (V+-S)to(V+ +0.3)V
Input Voltage (C1, C2, C3, C4 + DIFF IN, - DIFF IN,
-INPUT, BIAS, OSC),
(Note 1) ................... (V- -0.3) to (V+ +0.3)V
Differential Input Voltage (+ DIFF IN to - DIFF IN)
(Note 2) ................... (V - - 0.3) to (V + + 0.3)V
Duration of Output Short Circuit (Note 3) ........ Unlimited

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ralings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 1: Due to the SeR structure inherent in all CMOS devices, exceeding these limits may cause destructive latch up. For this reason, it is recommended that no
inputs from sources operating on a separate power supply be applied to the 7605/6 before its own power supply is established, and that when using
multiple supplies. the supply for the 7605/6 should be turned on first.
Note 2: No restrictions are placed on the differential input voltages on either the + DIFF IN or - DIFF IN inputs so long as these voltages do not exceed the power
supply Yoltages by more than 0.3V.
Note 3: The outputs may be shorted to ground (GNO) or to either supply (V+ or V-). Temperatures and/or supply Yoltages must be limited to insure that the
dissipation ratings are not exceeded.
Note 4: For operation above 25"C ambient temperature, derate 4mW/"C from 500mW above 25a C.

ELECTRICAL CHARACTERISTICS
Test Conditions: v+ = +5V, v- = -5V, TA= + 25"C, DR pin connected to v+

(fCOM "" 160Hz, fCOM1 "" SOHz),

C1 = C2= C3=C4 = 1,....F, Test Circuit 1 unless otherwise specified.
Symbol

Value

Test Conditions

Parameter

Min
Vos

Input Offset Voltage

Rss1kO

MIL version over temp.

e.Vos/e.T Average Input Offset
Voltage Temperature
Coefficient (Note 5)

Low or Med Bias Settings

e.Vos/e.t

Long Term Input
Offset Voltage Stability

Low or Med Bias Settings

CMVR

Common Mode Input Range

CMRR

Common Mode
Rejection Ratio

PSRR

Power Supply Rejection Ratio

-ISlAS

-INPUT Bias Current

en(p-p)

Equivalent Input Noise
Voltage peak-to-peak

Low Bias Setting
Med Bias Setting
High Bias Setting
Med Bias Setting

Units

Typ

Max

±2
±2
±7

±5
±30

-S5"C>TA> +25"C
+25°C>TA> +S5"C
+ 25"C> TA> + 125"C

0.01
0.01
0.05

0.2
0.2
0.2

0.5
-5.3

COSc=O, DR connected to V+, C3=C4= 1,....F
COSc= 1,....F, DR connected to GND,
C3=C4=1,....F
COSc= 1,....F, DR connected to GND,
C3=C4=10,....F

Low Bias Mode
Med Bias Mode
High Bias Mode

BandWidth
0.1 to 10Hz

,....VI"C
,....VI"C

,....V/"C
,....VlYear

+5.3

94

V

100

dB
dB

104

dB
dB

110
Any bias setting, fc= 160Hz
(Includes charge injection currents)

,....V
,....V
,....V
,....V

0.15
4.0
4.0
5.0

1.5

nA
,....V
,....V
,....V

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

7-21

•

CD

o

...

ICL 7605/ICL 7606

CD

d

ELECTRICAL CHARACTERISTICS
.::::. Test Conditions: V+ = +5V, v- = -5V, TA= + 25'C, DR pin connected to V+
II)

o

CD
......

!:!

(feoM "" 160Hz, feoM1 "" 80Hz),

C1 = C2 = Cs = C4 = 1",F, Test Circuit 1 unless otherwise specified. (Continued)
Symbol

Parameter

Value

Test Conditions

en

Equivalent Input
Noise voltage

BandWidth
0.1 to 1.0Hz

AVOL

Open Loop Voltage Gain

RL =10kO

±VO

Maximum Output
Voltage Swing

RL=lMO
RL =100kO
RL =10kO

Typ
1.7

",V

90
90
80

105
105
100

dB
dB
dB

±4.9
±4.8

V
V
V
V

All Bias Modes
Low Bias Setting
Med Bias Setting
High Bias Setting

Positive Swing
Negative Swing

GBW

Bandwidth of Input
Voltage Translator

CS=C4=1",F

All Bias Modes

feOM

Nominal Commutation
Frequency

Cose=O

feoM1

Nominal Input Converter
Commutation Frequency

Cose=O

VBH
VBM
VBL

Bias Voltage
required to set
Quiescent Current

Low Bias Setting
Med Bias Setting
High Bias Setting

IBIAS

Bias (Pin 8) Input Current

lOR

Division Ratio Input
Current

V+ -8.0SVORSV+ +0.3 volt

VORH
VORL

DR Voltage required to
set Oscillator division ratio

Internal oscillator division ratio 32
Internal oscillator division ratio 2

RAS

Effective Impedance of
Voltage Translator
Analog Switches

Isupp

Supply Current

High Bias Setting
Med Bias Setting
Low Bias Setting

V+-V-

Operating Supply
Voltage Range

High Bias Setting
Med or Low Bias Setting

Units

Min

Max

+4.4
-4.5
10

Hz

DR Connected to V+
DR Connected to GND

160
2560

Hz
Hz

DR Connected to V+
DR Connected to GND

80
1280

Hz
Hz

V+ -0.3
V-+l.4
V--0.3

V+
GND
V-

V+ +0.3
V+-l.4
V-+0.3

±30

pA

±30

pA

V+ -0.3
V+-8

V+ +0.3
V+ -1.4

7
1.7
0.6

V
V
kO

30

5
4

V
V
V

15
5
1.5

mA
mA
mA

10
10

V
V

Note 5: For Design only. not tested.

INTEAStL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AJI typical values have bsen characterized but are not tested

7-22

ICL 7605/ICL 7606
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE
AS A FUNCTION OF
AMBIENT TEMPERATURE
+1

":.

•

NEGATIVE POWIIIIIUPPLY VOLTAGI
..... ...... ....1 -U -2.1

-,..

TE.lT CII/CUIT 1,

=:.

C, =C2 =1p.F

• +8

tCOM

=110Hz

i+8

..

!s

/

i •
~

J

,.

-4
-50

rf •
i

01'_

~L~a!:)

""

I:LT_

+4.5

+7.5

i

,,,oi

VI~=

'U.
[U ,ui

17.:'
VIAll

\ V
~

~

~ .~

o

17.1.

lIAS

~~'-~~~

/

+I.' +...
• POSITIVI POWIR SUPPLY VOLTAGE
+u

HsS 1kO

y-- .... VOLTI

VOLTAGE

au It

~.l

T,,-II-C
Av-tODD

If-

F= F".21 ~~ a.!!!.-.:: F= • I!

+1.1

-IS
•
lIS 5.
75 100 125
TA • AMBIENT TEMPERATURE· ·C

~

-t.o",

IY+' V'I·'. YOLTI
fcoM -110Hz

O

, -1.0

./

~-2

:.. -II

Rs:S1kU

C" C2

i

+2

=:.

~:~.;:

I .....

~+8

INPUT OFFSET VOLTAGE AND
PK·To-PK NOISE VOLTAGE AS
A FUNCTION OF COMMUTATION
FREQUENCY (C1. C2= 1,.,.F)

INPUT OFFSET VOLTAGE AND
PK·TO·PK NOISE VOLTAGE AS A
FUNCTION OF SUPPLY VOLTAGES

,

7.1!

HIGHBI

III~

F~...J:T

.lJ.UIiI

"'I!
u:i
•

10
tao
1k
10k
'COM - COMMUTATION FRIOLENCY· Hz

0306-6

0306-5

0306-4

INPUT OFFSET VOLTAGE AND
PK·To-PK NOISE VOLTAGE AS A
FUNCTION OF COMMUTATION
FREQUENCY (C1. C2 = 0.1 ,.,.F)

INPUT OFFSET VOLTAGE AND
PK·TO·PK NOISE AS A FUNCTION
OF SUPPLY VOLTAGE (V+·V-)

... -7

~,,~r-~~~~~,

':.

=:.

Si

!,"

r-

iI~. V~T~.~~~~~
0FfS&T

~~~~~~~~~
10
100
1k
11k

-

TA=alc
Av = 1GOO
AsS tlUl

.\

C,. C2= 1.0",
IY+I

i-2
i

IeOM· COMMUTATION FREQUENCY .. Hz

o

=IV-I I--

fcoM·'SO Hz

2

-- -

NOlIE V

TA = +IS~
V'·V'= 'QV
C, =C2 =',uF

ii.~ta

IJ.J-/

V

"7
...

loon = 40Hz

IJ..I.-"'"
....... ~"'='SOH

,
,

IJY

/

/

V

~~"'H'

V

/

/
I

a

"'012141'
SUPPLY VOLTAGE

0306-7

'01

I-- I--

I:

\

i .. F-tt+:I~+H-HtH
..

-

COMMON MODE REJECTION RATIO
AS A FUNCTION OF THE INPUT
DIFFERENTIAL TO SINGLE ENDED
VOLTAGE CONVERTER CAPACITORS

0306-6

800.1

'.0

Co. C. - VOLTAGE CONVERTER

'0.0

CAPACITOR VAWES - .F
0306-9

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AN typIcst _

have bHn cha-.J but"", not tested.

7-23

•

o
o ICL 7605/ICL 7606
o
r0-

d
::::.
II)
o
o

TYPICAL PERFORMANCE CHARACTERISTICS
INPUT CURRENT AS A FUNCTION
OF COMMUTATION FREQUENCY

....ro-

I III

I

I

!:;5+2
00:

>CIi+1

Se
I!:

I
\ i/

-

I-

-HI BIAS

TA =25'C
NO LOAD- I-NO INPUT

-

TA = 25°C
IY+.Y-I = 10V
rR, C NNECTEO TO GNO_

::'~-1

)'

o

0

0

1/

-

~

,,'

WD+3
~z

I
I

INiB NON INVERTING
INPUT CURRENT

.....

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

1/

= 25°C
= 10 VOLTS

TA
IV+~V-I

g

(Continued)

MAXIMUM OUTPUT VOLTAGE
AS A FUNCTION OF
OUTPUT LOAD RESISTANCE

~~-2

~

5~

~INYERTING

>1&1-3

..

I'\.

-

0:

-4

INPUT CURRENT

10
100
1000
'COM - COMMUTATION FREQUENCY· Hz

-

Z-10

::l

~-20

~

"-

IIREF:~r
1

10
100
1,000
I - FREOUENCY - Hz

\

\

\

Q

~-30

"-

~

I ALiASIN

~

,........T~ =12slJ

~

\\

I

0

"

r'i It

§-30
t:
..."'--40
~o

..,

(V··V·) = 5 VOLTS
C, = C2 = C3 = C4 = 11lF

~

III

II

TA - +25°C

"-

III

FREQUENCY RESPONSE OF THE 10Hz
LOW PASS FILTER USED TO MEASURE NOISE
(TEST CIRCUIT 2).

.i' -40

'\

10,000

\
2

0306-15

34 S
.10
20304050
I • FREOUENCY • Hz

100
0306-16

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE" Aft typical values have been characterized but are not tested.

7·24

.o~on..

ICL 7605/ICL 7606

n

r-

...
~

o

....
n
rCII

INPUT:
GND OR VOLTAGE
BETWEEN
(V, +iI.3) AND
(V- -iI.3) VOLT

-1

I~F

-OIFF IN

I

I
I
I

I OUTPUT

0306-19

Figure 6: Simplified Block Diagram

OUTPUT

111
lK

VOLTAGE GAIN

The ICL7605/1CL7606 have approximately constant
equivalent input noise voltage, CMRR, PSRR, input offset
voltage and drift values independent of the gain configuration. By comparison, hybrid-type modules which use the traditional three op amp configuration have relatively poor performance at low gain (1 to 100) with improved performance
above a gain of 100.
The only major limitation of the ICL7605/1CL7606 is its
low-frequency operation (10 to 20Hz maximum). However in
many applications bandwidth is not the most important parameter.

= 1000

0306-17

Figure 4: Test Circuit 1

CAZ Op Amp Section
Your

Operation of the CAZ op-amp section of the ICL76051
ICL7606 is best illustrated by referring to Figure 7. The basic amplifier configuration, represented by the large triangles, has one more input than does a regular op amp - the
AZ, or auto-zero terminal. The voltage on the AZ input is
that level at which each of the internal op amps will be autozeroed. In Mode A, op amp #2 is connected in a unity gain
mode through on-chip analog switches. It charges external
capacitor C2 to a voltage equal to the DC input offset voltage of the amplifier plus the instantaneous low-frequency
noise voltage. A short time later, the analog switches reconnect the on-chip op amps to the configuration shown in
Mode B. In this mode, op amp #2 has capacitor C2 (which
is charged to a voltage equal to the offset and noise voltage
of op amp # 2) connected in series to its non-inverting (+)
input in such a manner as to null out the input offset and
noise voltages of the amplifier. While one of the on-chip op
amps is processing the input signal, the second op amp is in
an auto-zero mode, charging a capacitor to a voltage equal
to its equivalent DC and low frequency error voltage. The
on-chip amplifiers are connected and reconnected at a rate
deSignated as the commutation frequency (feOM), so that at
all times one or the other of the on-chip op amps is processing the input signal, while the voltages on capacitors C, and
C2 are being updated to compensate for variables such as
low frequency noise voltage and input offset voltage changes due to temperature, drift or supply voltages effects.

0306-16

,
Figure 5: Test Circuit 2
DC to 10Hz Unity Gain Low Pass Filter

DETAILED DESCRIPTION
CAZ Instrumentation Amp Overview
The CAZ instrumentation amplifier operates on principles
which are very different from those of the conventional
three op-amp deSigns, which must use ultra-precise
trimmed resistor networks in order to achieve acceptable
accuracy. An important advantage of the ICL7605/1CL7606
CAZ instrumentation amp is the provision for self-compensation of internal error voltages, whether they are derived
from steady-state conditions, such as temperature and supply voltage fluctuations, or are due to long term drift.
The CAZ instrumentation amplifier is constructed with
monolithic CMOS teChnology, and consists of three distinct
sections, two analog and one digital. The two analog sections - a differential to single-ended voltage converter, and
a CAZ op amp - have on-chip analog switches to steer the
input signal. The analog switches are driven from a selfcontained digital section which consists of an RC oscillator,
a programmable divider, and associated voltage translators.
A functional layout of the ICL7605/1CL7606 is shown in Figure 6.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

~~~~~~~~~Jl~;~~~ ~~N~~~L~~~V~ :~~T~~~~~ ~~~~

LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING

NOTE: All typical valUBS have been characterized but sre not tested

7-25

~

o

~

+5V
_vv""'~_

...

TH~

IMPLIED WARRANTIES OF

8 ICL7605/ICL7606

......

CD

()

::::.
II)
o

......
CD

i

~

________~~O~UTPUT

-~~~'~,

__________~O~UTPUT

0306-20

Figure 7: Diagrammatic representation of the 2 half cycles of operation of the CAZ OP AMP.

c,---+---------+---------f

c, --+--+----..

OUTPUT

NPUT

~

INPUT

(COMMUTATION
FREQUENCY)

FROM FIG 4

AZ

RF
(100kll)

~NPUT------------J

C[

Cl
0306-21

Figure 8: Schematic of analog switches connecting each internal OP AMP
to its inputs and output.
Compared to the standard bipolar or FET input op amps,
the CAl amp scheme demonstrates a number of important
advantages:
Effective input offset voltages can be reduced from
1000 to 10,000 times without trimming.
Long-term offset voltage drift phenomena can be
compensated and dramatically reduced.
Thermal effects can be compensated for over a
wide operating temperature range. Reductions can
be as much as 100 times or better.
Supply voltage sensitivity is reduced.
CMOS processing is ideally suited to implement the CAl
amp structure. The digital section is easily fabricated, and
the transmission gates (analog switches) which connect the
on-chip op amps can be constructed for minimum charge

injection and the widest operating voltage range. The analog section, which includes the on-chip op amps, contributes performance figures which are similar to bipolar or FET
input designs. The CMOS structure provides the CAl opamp with open-loop gains of greater than 100dS, typical
input offset voltages of ± 5mV, and ultra-low leakage currents, typically 1pA.
The CMOS transmission gates connect the on-chip op
amps to external input and output terminals, as shown in
Figure 8. Here, one op amp and its associated analog
switches are required to connect each on-chip op amp, so
that at any time three switches are open and three switches
are closed. Each analog switch consists of a P-channel
transistor in parallel with an N-channel transistor.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLlED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOT£' All typical values have been characterized but are not tested.

7-26

IIID~Dn.

ICL7605/ICL7606

p
...
GI

o

en
.....

p
...
GI

o
o

+DIFF IN o---t--~

s,

'----+--- INPUT OF AMPLIFIER
, . . - - -......-

-DIFF IN o---+-i

GND OR REFERENCE VOLTAGE

MODE
8,
S
..
57
A CLOSED OPEN CLOSED OPEN CLOSED OPEN CLOSED
B
OPEN CLOSED
CLOSED OPEN CLOSED OPEN CLOSED

-v

The ' ....
al whiCh _
A .. Bare cvcfed I.
known as ... INPUT COMMUTATION FREQUENCY

0306-22

Figure 9: Schematic of the differential to single ended voltage converter

DIFFERENTIAL-TO-SINGLE-ENDED
UNITY GAIN VOLTAGE CONVERTER
An idealized schematic of the voltage converter block is
shown in Figure 9. The mode of operation is quite simple,
involving two capaCitors and eight switches. The switches
are arranged so that four are open and four are closed. The
four conducting switches connect one of the capacitors
across the differential input, and the other from a ground or
reference voltage to the input of the CAZ instrumentation
amp. The output signal of this configuration is shown in Figure 10, where the voltage steps equal the differential voltage 01A-Vs) at commutation times a, b, c, etc. The output
waveform thus represents a" information contained in the
input signal from DC up to the commutation frequency, including commutation and noise voltages. Sampling theory
states that to preserve the information to be processed, at
least two samples must be taken within a period (1 If) of the
highest frequency being sampled. Consequently this
scheme preserves information up to the commutation frequency. Above the commutation frequency, the input signal
is translated to a lower frequency. This phenomenon is
known as aliasing. Although the output responds to inputs
above the commutation frequency, the frequencies of the
output responses wi" be below the commutation frequency.

INPUT COMMUTATION

PERIOD (1ItCOM1)

0306-23

Figure 10: Input to Output Voltage
waveforms from the differential to single
ended voltage converter. For additional
Information, see frequency characteristics In
Amplitude Response of the Input Differential
to single ended voltage converter graph on
page 5.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIes. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have beBn oharaclfNfz8d but are not I68ted.

7-27

! ICL7605/ICL7606
10

....

d
:::::.
II)

o

OSC140

osc 239

10

....

lOOk

osc 338

g

TEST 37
REF HI 36

y.

REF L03S
C REF 34
C REF 33
COMM32

"
""
"

y.

AZ"

10kJl

Rt

r

"

O.1;,1F

1.5 Hz
LOW PASS
Av

16

v-"

=

Rl +R2

-R,-

FILTER
= 101 TIMES

ICL7106

16
19
20

_

.4 "

SUFF28
.22,u
INT27

15

1M!!

v-

IN HI3l
IN L030

""

23
22

'='

}

20

LCD DISPLAY

0306-24

Figure 11: 3-% Digit Digital Readout Torque Wrench
The voltage converter is fabricated with CMOS analog
switches, which contain a parallel combination of P-channel
and N-channel transistors. The switches have a finite ON
impedances of 30kn, plus parasitic capacitances to the
substrate. Because of the charge injection effects which appear at both the switches and the output of the voltage
converter, the values of capacitors C3 and C4 must be
about 1",F to preserve signal translation accuracies to
0.Q1 %. The 1",F capacitors, coupled with the 30kn equivalent impedance of the switches, produce a low-pass filter
response from the voltage converter which is down approximately 3dB at 10Hz.

the AID. In order to set the full-scale reading, a value of
gain for the ICL7605/1CL7606 instrumentation CAZ amp
must be selected along with an appropriate value for the
reference voltage. The gain should be set so that at full
scale, the output will swing about 0.5V. The reference voltage required is about one-half the maximum output swing,
or approximately 0.25V.
In this type of system, only one adjustment is required.
Either the amplifier gain or the reference voltage must be
varied for full-scale adjustment. Total current consumption
of all circuitry, less the current through the strain gauge
bridge, is typically 2mA. The accuracy is limited only by resistor ratios and the transducer.

APPLICATIONS
Using the ICL760511CL7606 to Build a
Digital Readout Torque Wrench

SOME HELPFUL HINTS
Testing the ICL7605/1CL7606 CAZ
Instrumentation Amplifier

A typical application for the ICL7605/1CL7606 is in a
strain gauge system, such as the digital readout torque
wrench circuit shown in Figure 6. In this application, the
CAZ instrumentation amplifier is used as a preamplifier, taking the differential voltage of the bridge and converting it to
a single-ended voltage referenced to ground. The signal is
then amplified by the CAZ instrumentation amplifier and applied to the input of a 3-% digit dual-slope AID converter
which drives the LCD panel meter display. The AID converter device used in this instance is the Intersil ICL71 06.
In the digital readout torque wrench circuit, the reference
voltage for the ICL7106 is derived from the stimulus applied
to the strain gauge, to utilize the ratiometric capabilities of

Figure 4 and 5 (Test Circuits) provide a convenient means
of measuring most of the important electrical parameters of
the CAZ instrumentation amp. The output signal can be
viewed on an oscilloscope after being fed through a lowpass filter. It is recommended that for most applications, a
low-pass filter of about 1.0 to 1.5Hz be used to reduce the
peak-to-peak noise to about the same level as the input
offset voltage.
The output low-pass filter must be a high-input impedance RC type - not simply a capacitor across the feedback
resistor R2. Resistor and capacitor values of about 100kn
and 1.0",F are necessary so that the output load impedance
on the CAZ op-amp is greater than 100kn.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PROOUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charsctBrized but ere not tested.

7-28

ICL 7605/ICL 7606

-ftfoINPUT
AC

RSOURCE

WAVEFORMS

GND

t

....L..--.----L..-_---\-_-.--~

OUTPUT
VOLTAGE

0306-26

0306-25

Figure 12: Effect of a load capacitor on output voltage waveforms.
tic in the direction of the auto-zero voltage and a high-impedance characteristic on the recovery edge, as shown in
Figure 12. It can be seen that the effect of a large load
capacitor produces an area error in the output waveform,
and hence an effective gain error. The output low-pass filter
must be of a high-impedance type to avoid these area errors. For example, a 1.5Hz filter will require a 100kO resistor
and a 1.0p.F capacitor, or a 1MO resistor and a 0.1 p.F capaCitor.

Bias Control
The on-chip op amps consume over 90% of the power
required by the ICL7605/ICL7606. For this reason, the inter·
nal op amps have externally programmable bias levels.
These levels are set by connecting the BIAS terminal to
either V+ , GND, or V-, for LOW, MED or HIGH BIAS levels, respectively. The difference between each bias setting
is about a factor of 3, allowing a 9: 1 ratio of quiescent supply current versus bias setting. This current programmability
provides the user with a choice of device power dissipation
levels, slew rates (the higher the slew rate, the better the
recovery from commutation spikes), and offset errors due to
"IRn voltage drops and thermoelectric effects (the higher
the power dissipation, the higher the input offset error). In
most cases, the medium bias (MED BIAS) setting will be
found to be the best choice.

Oscillator and Digital Circuitry
Considerations
The oscillator has been designed to run free at about
5.2kHz when the OSC terminal is open circuit. If the full
divider network is used, this will result in a nominal commutation frequency of approximately 160Hz. The commutation
frequency is that frequency at which the on-chip op amps
are switched between the signal processing and the autozero modes. A 160Hz commutation frequency represents
the best compromise between input offset voltage and low
frequency noise. Other commutation frequencies may provide optimization of some parameters, but always at the expense of others.
The oscillator has a very high output impedance, so that a
load of only a few picofarads on the ose terminal will cause
a significant shift in frequency. It is therefore recommended
that if the natural oscillator frequency is desired (5.2kHz)
the terminal remains open circuit. In other instances, it may
be desirable to synchronize the oscillator with an external
clock source, or to run it at another frequency. The
ICL7605/ICL7606 CAZ amp provides two degrees of flexibility in this respect. First, the DR (division ratio) terminal
allows a choice of either dividing the oscillator by 32 (DR
terminal to V+) or by 2 (DR terminal to GND) to obtain the
commutation frequency. Second, the oscillator may have its
frequency lowered by the addition of an external capaCitor
connected between the OSC terminal and the V + or system GND terminals. For situations which require that the
commutation frequency be synchronized with a master
clock, (Figure 13) the OSC terminal may be driven from TTL
logic (with resistive pull-up) or by CMOS logic, provided that
the V+ supply is +5V (±10%) and the logic driver also
operates from a similar voltage supply. The reason for this
requirement is that the logic section (including the oscillator)
operates from an internal -5V supply, referenced to V+
supply, which is not accessible externally.

Output Loading (Resistive)
With a 10kO load, the output voltage swing can vary
across nearly the entire supply voltage range, and the device can be used with loads as low as 2kO.
However, with loads of less than 50kO, the on-chip op
amps will begin to exhibit the characteristics of transconductance amplifiers, since their respective output impedances are nearly 50kO each. Thus the open-loop gain is
20dB less with a 2kO load than it would be with a 20kO
load. Therefore, for high gain configurations requiring high
accuracy, an output load of 100kO or more is suggested.
There is another consideration in applying the CAZ. instrumentation op amps which must not be overlooked. This is
the additional power dissipation of the chip which will result
from a large output voltage swing into a low resistance load.
This added power dissipation can affect the initial input offset voltages under certain conditions.

Output Loading (Capacitive)
In many applications, it is desirable to include a low-pass
filter at the output of the CAZ. instrumentation op amp to
reduce high-frequency noise outside the desired Signal
passband. An obvious solution when using a conventional
op amp would be to place a capaCitor across the external
feedback resistor and thus produce a low-pass filter.
However, with the CAZ op amp concept this is not possible because of the nature of the commutation spikes. These
voltage spikes exhibit a low-impedance characteris-

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE

:~:!.=TYSHA'i!'~ ;N:~L~~~ ~:~T~~~ ~~~N

LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF

NOTE: A/llypical vsluBs hsllf1 bstm charactfIriz6d but artJ not tested.

7-29

•

8 ICL 7605/ICL 7606
....CD

it

:::::.
II)

o

CD

.......
g

Thermoelectric Effects

Commutation Voltage Transient Effects

The ultimate limitations to ultra-high-sensitivity DC amplifiers are due to thermoelectric, Peltier, or thermocouple effects in electrical junctions consisting of various metals (alloys, silicon, etc.) Unless all junctions are at precisely the
same temperature, small thermoelectric voltages will be
produced, generally about 0.1 J.L V
However, these voltages can be several tens of microvolts per 'c for certain
thermocouple materials.

Although in most respects the CAZ instrumentation amplifier resembles a conventional op amp, its principal applications will be in very low level, low-frequency preamplifiers
limited to DC through 10Hz. The is due to the finite switching transients which occur at both the input and output terminals because of commutation effects. These transients
have a frequency spectrum beginning at the commutation
frequency, and including all of the higher harmonics of the
commutation frequency. Assuming that the commutation
frequency is higher than the highest in-band frequency, then
the commutation transients can be filtered out with a lowpass filter.
The input commutation transients arise when each of the
on-chip op amps experiences a shift in voltage which is
equal to the input offset voltages (about S-10mV), usually
occurring during the transition between the signal processing mode and the auto-zero mode. Since the input capacitances of the on-chip op-amps are typically in the 10pF
range, and since it is desirable to reduce the effective input
offset voltage about 10,000 times, the offset voltage autozero capacitors C1 and C2 must have values of at least
10,000 XI OpF, or 0.1 J.LF each.
The charge that is injected into the input of each op amp
when being switched into the Signal processing mode produces a rapidly-decaying voltage spike at the input, plus an
equivalent DC input bias current averaged over a full cycle.
This bias current is directly proportional to the commutation
frequency, and in most instances will greatly exceed the
inherent leakage currents of the input analog switches,
which are typically 1.0pA at an ambient temperature of
2S'C.
The output waveform in Figure 4 (with no input signal) is
shown in Figure 14. Note that the equivalent noise voltage
is amplified 1000 times, and that due to the slew rate of the
on-chip op amps, the input transients of approximately 7mV
are amplified by a factor of less than 1000.

rc.

TTL
OR
CMOS
LOGIC

USE RL - 22kll
FOR TTL LOGIC
(NOT NEEDED FOR CMOS)

0306-27

Figure 13: ICL7605 being clocked from external
logic into the oscillator terminal.
In order to realize the extremely low offset voltages which
the CAZ op amp can produce, it is necessary to take precautions to avoid temperature gradients. All components
should be enclosed to eliminate air movement across device surfaces. In addition, the supply voltages and power
dissipation should be kept to a minimum by use of the MED
BIAS setting. Employ a high impedance load and keep the
ICL760S/ICL7606 away from equipment which dissipates
heat.

Component Selection
The four capacitors (C1 thru C4) should each be about
1.0J.LF. These are relatively large values for non-electrolytic
capacitors, but since the voltages stored on them change
significantly, problems of dielectric absorption, charge
bleed-off and the like are as significant as they would be for
integrating dual-slope AID converter applications. Polypropylene types are the best for C3 and C4, although Mylar
may be adequate for C1 and C2.
Excellent results have been obtained for commercial temperature ranges using several of the less-expensive, smaller-size capacitors, since the absolute values of the capacitors are not critical. Even polarized electrolytic capacitors
rated at 1.0J.LF and SOV have been used successfully at
room temperature, although no recommendations are made
concerning the use of such capacitors.

~6ms

r----

VOLTAGE
OUTPUT

GND

T~

!

----.l
DIFFERENTIAL TO SINGLE ENDED
-I /COVERTER TRANSIENTS

~

III
25rvWIINN"'#I0NIIN.v~, 1Hi1fNN¥l,
f-3mS-J" i~~:E~~:

TIME_
0306-28

Figure 14: Output waveform from Test Circuit 1.

Layout Considerations
Care should be exercised in positioning components on
the PC board particularly the capacitors C1, C2, C3 and C4,
which must all be shielded from the
terminal. Also,
parasitic PC board leakage capacitances associated with
these four capacitors should be kept as low as possible to
minimize charge injection effects.

asc

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE All typical values have b6en characterized but are not tested.

7-30

ICL76XX
ICL76XX Series Low Power
CMOS Operational Amplifiers
GENERAL DESCRIPTION

FEATURES

The ICL761X1762X1763X1764X series is a family of
monolithic CMOS operational amplifiers. These devices provide the designer with high performance operation at low
supply voltages and selectable quiescent currents, and are
an ideal design tool when ultra low input current and low
power dissipation are desired.
The basic amplifier will operate at supply voltages ranging
from ± 1V to ± BV, and may be operated from a single Lithium cell.
A unique quiescent current programming pin allows setting of standby current to 1mA, 100",A, or 1O",A. with no
external components. This results in power consumption as
low as 20",W. Output swings range to within a few millivolts
of the supply voltages.
Of particular significance is the extremely low (1 pAl input
current, input noise current of .01pA/VHz, and 10120 input
impedance. These features optimize performance in very
high source impedance applications.
The inputs are internally protected and require no special
handling procedures. Outputs are fully protected against
short circuits to ground or to either supply.
AC performance is excellent, with a slew rate of 1.6V I "'S,
and unity gain bandwidth of 1MHz at IQ = 1mAo
Because of the low power diSSipation, operating temperatures and drift are quite low. Applications utilizing these features may include stable instruments, extended life designs,
or high density packages.

• Wide Operating Voltage Range
•
•
•
•
•

± 1V to ± 8V

High Input Impedance -10 120
Programmable Power Consumption- Low As 20",W
Input Current Lower Than BIFETs - Typ 1pA
Available As Singles, Duals, Triples, and Quads
Output Voltage Swings to Within Millivolts Of V- and

V+
• Low Power Replacement for Many Standard Op
Amps
• Compensated and Uncompensated Versions
• Input Common Mode Voltage Range Greater Than
Supply Ralls (ICL7612)

APPLICATIONS
•
•
•
•
•
•

Portable Instruments
Telephone Headsets
Hearing Aid/Microphone Amplifiers
Meter Amplifiers
Medical Instruments
High Impedance Buffers

SELECTION GUIDE
SPECIAL FEATURE CODES

DEVICE NOMENCLATURE
ICL76XX

X

X

C

XX

L
L -_ _ _

L -_ _ _ _ _ _

H

L
M

Package Code
TV - TO-99, B pin
PA - Plastic 8 pin Minidip
PD - 14 pin Plastic Dip
PE - 16 pin Plastic Dip
JD - 14 pin CERDIP
JE - 16 pin CERDIP

o
P

V

INTERNALLY COMPENSATED
HIGH QUIESCENT CURRENT (1 mAl
LOW QUIESCENT CURRENT (10",A)
MEDIUM QUIESCENT CURRENT (100",A)
OFFSET NULL CAPABILITY
PROGRAMMABLE QUIESCENT CURRENT
EXTENDED CMVR

Temperature Range
C = O'C to 70'C
M= -55'Cto + 125'C
Vas Selection
A=2mV
B=5mV
C=10mV
D=15mV
E=20mV

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
302060-002
NOTE: All typical values have been chsracterlz9d but are not tested.

7-31

•

= ICL76XX

g... ORDERING INFORMATION
It

Basic
Part
Number

Number of
OP·AMPSin
Package, and
Special Features
(SEE CODES)

ICL7611
ICL7612

SINGLE OP-AMP:
C,O,P
C,O,P,V

ICL7621

DUAL OP-AMP:
C,M

ICL7631

TRIPLE OP-AMP:
C,P

ICL7641
ICL7642

Package Type and Suffix
a·Lead TO·99

a·Pln
MINIDIP

a·Pin
SOIC

Plastic
DIP (1)
O'Cto
+70'C

O'Cto
+70'C

ECPE

ECJE

CCPD
ECPD

CCJD
ECJD

OOCto
+700C

-55'Cto
+ 125'C

O'Cto
+70'C

OOC to
+70'C

ACTV
BCTV

AMTV
BMTV

ACPA
BCPA

DCPA
DCBA

ACTV
BCTV
DCTV

AMTV
BMTV

ACPA
BCPA
DCPA

QUAD OP-AMP:
C,H
C, L

Ceramic DIP (1)
-55'Cto
+ 125'C

CMJD

NOTES: 1. Duals and quads are available in 14 pin DIP package, triples in 16 pin only.
2. Ordering code must consist of basic part number and package suffix, e.g., ICL7611 BCPA.

Device
ICL7611XCPA
iCL7611XCTV
ICL7611 XMTV
iCL7612XCPA
ICL7612XCTV
iCL7612XMTV

Description

Pin Assignments

Internal compensation, plus
offset null capability
and external IQ control

8 PIN DIP (TOP VIEW)
(outline dwg PAl

TO-99 (TOP VIEW)
(outline dwg TV)
'Q SET

0307-1

0307-2

'Pin 7 connected to case.
8 PIN DIP (TOP VIEW)
(outline dwg BA)

v0307-3

Figure 1: Pin Configurations

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicsl values hSV8 been characterized but 8re not tested.

7-32

ICL76XX
Device

Description

ICL7621XCPA
ICL7621XCTV
ICL7621XMTV

Dual op amps with internal
compensation; 10 fixed
at lOOI-'A
Pin compatible with
Texas Inst. TL082
Motorola MC1458
Raytheon RC4558

Pin Assignments
• PIN DIP (TOP VIEW)
(outline dwg PAl

TO-99 (TOP VIEW)
(outline dwg TV)

v+ OUT. -IN. +IN.

v·

OUT. -IN, +IN.
0307-6

v0307-7

'Pin 8 connected to case.
ICL7631XCPE

16 PIN DIP (TOP VIEW)
(outline dwgs JE, PEl

Triple op amps with internal
compensation.
Adjustable 10
Same pin configuration as
ICL8023.

I....

10 •

v·

SET

v-

SET

16

-IN"

+ IN"

OUT.

v+

loc
SET

-INc

+ INc
0307-9

Note: pins 5 and 15 are internally connected.
ICL7641XCPD
ICL7642XCPD

14 PIN DIP (TOP VIEW)
(outline dwg JD, PD)

Quad op amps with internal
compensation.
10 fixed at 1mA (ICL7641)
10 fixed at lOI-'A (ICL7642)
Pin compatible with
Texas Instr. TL084
National LM324
Harris HA4 7 41

-INo

+INo

v-

-IN...

+INA

V+

+INc

-INc

OUTe

-IN.

OUT,

•
OUT"

+IN,

0307-10

Figure 1: Pin Configurations (Cont.)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All Iypicslllslues have be9n characterized but are not festsd.

7-33

•

.D~Dn.

>< ICL76XX
><
U)

....
g...

10
SETTING
STAGE

INPUT
STAGE

OUTPUT
STAGE
I
y+

3K

3K

0

900K

OFFSET 0

OFFSET

6.3Y

lOOK

+INPUT++

'---+---11----+--

Y-

OUTPUT

Cc = 33pF

y+

-INPUT

Y6.3V

Table of Jumper.
ICL·7611
ICL·7612
ICL·7621
ICL·7631
ICL· 7641
ICL·7642

S, F, H
S, F, H
C, E
S, F, H
C, G
A, E

~----~--~------~~~~----~-----+----~--~~Y-

Y+

o--I,,'---

I

100

.J.-


!

1I

-

C!Q-l00p.A

a:

>
~

IC.'

I

i!ia:

~

V+-V-·'0VOLTS
Na LOAD

r- I-- NO SIGNAL

t-'Q-lmA

~

:;
a:
a:

~

-Y

~

INPUT BIAS CURRENT AS A
FUNCTION OF TEMPERATURE
1000

1-10 -10/.1A

ffi

a:

10

10

12

14

-so

16

-25

+2&

+50

/

~
;;

i

+76

1/
./

1.0

o. 1~50

1

j

'1- • ..sVOlTS

100

a

-.....

10

!

Ir ... voiTS

+100 +126

-26

FREE·AIR TEMPERATURE -"C

SUPPLY VOLTAGE -VOLTS

+26

+50

+75

FREE·AIR TEMPERATURe

0307-13

0307-14

0307-12

LARGE SIGNAL DIFFERENTIAL
VOLTAGE GAIN AS A FUNCTION
OF FREE·AIR TEMPERATURE
1000

!

"
~

RI.

100

~

=,j,m l -

RI. ·,00KIl
'Q""OO/lA _

RL;'~ ~

'a=lmA

I--

-

~

rg

I

~

I

Vsupp ~ 10 VOLTS
'lOUT '" 8 VOLTS

1=
f-

. ~ "-

0

1

10

1

1
-75

-SO

-25

0

+25

+50

100

1K

~

90 ~

~

10K

".

~:...

100K

a:

8.

~

80

S
1M

+75 +100 +125

lo-1mA

~r-I--"-

r-....

i~

0307-16

C

r-H-'~"~
r---... r-....

i'" ~

70
-75

FREQUENCY - Hz

FREE·AIR TEMPERATURE -

96

;)

10 " ' , " ' \

0.1

0

r- ~A

S
~

o·

IQ.1ImA

~

PHASE SHIFT\... "'(i Ql'1mA(

1

10

VSUpp·'0V

I 100

2

I\. ~
,

COMMON MODE REJECTION
RATIO AS A FUNCTION OF FREE·AIR
TEMPERATURE
106

TA -+2S'C
Cc "33pF FOR
t1Cl7614/15

/IO"'~A

I

6>

;:

"supp-lev
'0" 10C1;.1A

Z

;;

,

10

I I

!>

LARGE SIGNAL DIFFERENTIAL
VOLTAGE GAIN AND PHASE SHIFT
AS A FUNCTION OF FREQUENCY

-so

o

-25

+26

+75 +100 +126

+60

FREE·AIR TEMPERATURE _·C

0307-15

POWER SUPPLY REJECTION RATIO
AS A FUNCTION OF FREE·AIR
TEMPERATURE

0307-17

",I, mA

r-:;:.A~
5

r-.... r-....

5

r- t-

..........

0
-25

0

+25

+50

+75 .'00 +125

FREE·AIR TEMPERATURE -

2

C

,IV

0
8

•
•

1

iF·ill
. '+-

0
-50

• "su';·

I

!iiitl
!! i: ! r
I'-.

N

,

6

TA"+25C
3V " Vsupp" l8V

j~1'
: I

I :~

65
-75

Ii

\ill
·1

l- f-....

~.'OjOA

0

.!III

Vsupp" 10V

t-- r-

PEAK·TO·PEAK OUTPUT
VOLTAGE AS A FUNCTION
OF FREQUENCY

EQUIVALENT INPUT NOISE
VOLTAGE AS A FUNCTION OF
FREQUENCY

100
IQ

+100 +126

_·c

.
!

i

100

,.

2

l10K

100.

FREOUENCY - Hz

100

- IQ "1mA
--.IQ.10~A

1\

....... '0. ,00 ...

:,

,

'ii """I

v.u.... ,

\

\ i

:

\1

\

i f'-- ""~\I
...~
,.
1..2:»-.........

v,u...

,2V

10K

lOOK

1M

10M

FREOUENCY - Hz

0307-19

0307-18

o

,
~i

,.V

TA • +25"C

-~ """'\

0307-20

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY 08L1GATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE; All typical values have b8M characterized but are not tested.

7·41

•

= ICL76XX
...

~

TYPICAL PERFORMANCE CHARACTERISTICS
MAXIMUM PEAK-T()"PEAK OUTPUT
VOLTAGE AS A FUNCTION OF
FREQUENCY

MAXIMUM PEAK-T()"PEAK OUTPUT
VOLTAGE AS A FUNCTION OF
SUPPLY VOLTAGE

,

>
~

t!
6

i!

~
6

~~. .: f-+-++t4r\~~++--+--+

«

l-++l----j

1,\

TA -+25C,!

•

~

I.;

TA" +25 C

14

..
~
I.;

12
10

j

i

£
-

I

10

12

:

t--

/
00

"

IVI
Vl

/

0.01

V

~

I
il

5~

,

o. 1

i

810121.,8

=

TA

tOY

0

IQ"'mA_

V

=

1.0

i

i

i\:

/OUTPUT!

\

I

>

..
~

-,

12

-8

I

I I'N;~~
-i I :

20

40

TIME

TIME -JlI

!

!

-2

I

10

10

100

LOAD RESISTANCE _ K!!

VSUPP .. tOV
.. lOOKS!
• l00pf

I
I

'o'l"""A

.

\.

i

.,0121416

!6

\.
INPUT

V

/

0307-26

0307-25

"
S
":i"

-

TA '" 25 C

I

I

\

/oUTPUT

0307-23

,

'"

>

i\

I

+75 +100 +125

'o·'mA

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

• 10K!!

+50

v· - v- = 10 VOLTS

0307-24

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

"'00pF
".+25 C

+25

MAXIMUM PEAK-T()"PEAK OUTPUT
VOLTAGE AS A FUNCTION OF LOAD
RESISTANCE

SUPPLY VOLTAGE -VOLTS

VSUJ!p

0

FREE·AIR TEMPERATURE _·C

r-

1.0

SUPPLY VOLTAGE - VOLTS

C,

to VOlTS

~75~· ~;:

IQ;,....~

I

",

i

VSUPP '"

L
f---\ ~ 'Q .. ,o,..A

i

IQ.,mA

~

0307-22

1,

I

I

,.

14

MAXIMUM OUTPUT SINK CURRENT
AS A FUNCTION OF SUPPLY
VOLTAGE

V

/

",'2::

j

~

0307-21

MAXIMUM OUTPUT SOURCE
CURRENT AS A FUNCTION OF
SUPPLY VOLTAGE

I

I j
g~ 10~t:t~t=t!"~'t·~'00;K~!l:t
lr---..

SUPPLY VOLTAGE - VOLTS

FREOUENCY - Hz

I

r-"'T'"-r-,...-..,--r-,...-..,I""

j

~

L

12

RL" lUKU

f--

~"

q.."

::!

10M

MAXIMUM PEAK-TO-PEAK VOLTAGE
AS A FUNCTION OF FREE-AIR
TEMPERATURE

",

--

60

c"

TA

a

+26 C

I

,

2

f\. -lMS!
c" • lOOp'

I

TA "·25C

.!!

\:
\.

/OUTPUT.

I

100

120

0

I
2

i

•

-t-

,

--+\

INPUT

--f-

.

I

i

!

I

i

:

200

400

600

800

[

i
1000 1200

TIME - ....

-III

0307-28

0307-27

•
•

,

;~, .

80

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE
8
Vsu" .. tOY
'0" 10""

0307-29

INlCRSIL'S SOLE AND EXCLUSIVE WARRANTY OBUClATION WIlH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDmON OF SALE.
THE WARRANTY SHALL BE EXCWSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR UBE.
NOTE:AHtyp/cBI _ _ _ _ buttwnot_

7-42

ICL76XX
in a highly linear class A mode. In this mode, crossover
distortion is avoided and the voltage gain is maximized.
However, the output stage can also be operated in Class
AS for higher output currents. (See graphs under Typical
Operating Characteristics). During the transition from Class
A to Class S operation, the output transfer characteristic is
non-linear and the voltage gain decreases.
A special feature of the output stage is that it approximates a transconductance amplifier, and its gain is directly
proportional to load impedance. Approximately the same
open loop gains are obtained at each of the 10 settings if
corresponding loads of 10kO, 100kO, and 1MO are used.

DETAILED DESCRIPTION
Static Protection
All devices are static protected by the use of input diodes.
However, strong static fields should be avoided, as it is possible for the strong fields to cause degraded diode junction
characteristics, which may result in increased input leakage
currents.

Latchup Avoidance
Junction-isolated CMOS circuits employ configurations
which produce a parasitic 4-layer (p-n-p-n) structure. The 4layer structure has characteristics similar to an SCR, and
under certain circumstances may be triggered into a low
impedance state resulting in excessive supply current. To
avoid this condition, no voltage greater than 0.3V beyond
the supply rails may be applied to any pin. In general, the
op-amp supplies must be established simultaneously with,
or before any input signals are applied. If this is not possible, the drive circuits must limit input current flow to 2mA to
prevent latch up.

Input Offset Nulling
For those models provided with OFFSET NULLING pins,
nulling may be achieved by connecting a 25K pot between
the OFFSET terminals with the wiper connected to V+. At
quiescent currents of 1mA and 100",A, the nulling range
provided is adequate for all Vos selections; however with
IO=10",A, nulling may not be possible with higher values of

vos·

Choosing the Proper IQ

Frequency Compensation

Each device in the ICL76XX family has a similar 10 set-up
scheme, which allows the amplifier to be set to nominal
quiescent currents of 10",A, 100",A or 1mA. These current
settings change only very slightly over the entire supply voltage range. The ICL7611/12 and ICL7631 have an external
10 control terminal, permitting user selection of each amplifiers' quiescent current. (The 7621 and 7641/42 have fixed
10 settings - refer to selector guide for details.) To set the
10 of programmable versions, connect the 10 terminal as
follOWS:
10= 10",A -10 pin to V+
la=100",A-la pin to ground. If this is not possible, any
voltage from V+ -0.8 to V- +0.8 can be used.
la=1mA-la pin to VNOTE: The negative output current available is a function of
the quiescent current setting. For maximum pop output voltage swings into low impedance loads, 10 of 1mA should be
selected.

The ICL76XX are internally compensated, and are stable
for closed loop gains as low as unity with capacitive loads
up to 100pF

Extended Common Mode Input Range
The ICL7612 incorporates additional processing which allows the input CMVR to exceed each power supply rail by
0.1 volt for applications where VSUPPL ± 1.5V. For those
applications where Vsupps ± 1.5V, the input CMVR is limited in the positive direction, but may exceed the negative
supply rail by 0.1 volt in the negative direction (eg. for
VSupp= ±1.0V, the input CMVR would be +0.6 volts to
-1.1 volts).

OPERATION AT Vsupp=

± 1.0 VOLTS

Operation at Vsupp= ±1.0V is guaranteed at la=10",A
only. This applies to those devices with selectable 10, and
devices that are set internally to la=10",A (i.e., ICL7611,
7612,7631,7642).
Output swings to within a few millivolts of the supply rails
are achievable for RLL1MO. Guaranteed input CMVR is
±0.6V minimum and typically +0.9V to -0.7V at
Vsupp = ± 1.0V. For applications where greater common
mode range is desirable, refer to the description of ICL7612
above.

Output Stage and Load Driving
Considerations
Each amplifiers' quiescent current flows primarily in the
output stage. This is approximately 70% of the 10 settings.
This allows output swings to almost the supply rails for output loads of 1MO, 100kO, and 10kO, using the output stage

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

7-43

•

= ICL76XX
...
CD

...

~

The user is cautioned that, due to extremely high input
impedances, care must be exercised in layout, construction,
board cleanliness, and supply filtering to avoid hum and
noise pickup.

APPLICATIONS
Note that in no case is 10 shown. The value of 10 must be
chosen by the designer with regard to frequency response
and power dissipation.

v-

v+
DUTYCVCLE
88Ok1l

WAVEFORM GENERATOR

V'N------I."

0307-33
'>--,,?,,--~-----VOUT

Since the output range swings exactly from rail to rail. frequency and
duty cycle afe virtually independent of power supply variations.

Figure 6: Precise Triangle/Square Wave
Generator
0307-30
1M

Figure 3: Simple Follower'
,000F 10k

>-II-'\I'~-.-J\I~---,

V'N
+5

+5

V'N >---+---1

L--f-+-VOL

>----,--- TO CMOS OR
VOUT

1001< ~-r-;!.'"

LPTTL LOGIC

COMMON

1M

0307-34

Figure 7: Averaging AC to DC Converter for A/D
Converters Such as ICL7106, 7107, 7109, 7116,
7117

0307-3'

'By using the ICL76,2 in these applications. the circuits will follow rail
to rail inputs.

Figure 4: Level Detector'
1M

lOOk, 1%

500k.'%

1001<

'pF

+

...

'Nl'UT

>--......---- VOUT

.------+ v+ <>--"\""'-......-1
1001<
100k, 1%

1M

1M,1%

~-4-~~--4~~~-oV-

0307-32
0307-35

*Low leakage currents allow integration times up to several hours.

Note that AVOL = 25; single Ni·cad battery operation. Input current
(from sensors connected to patient) limited to <5p.A under fault condi·

Figure 5: Photocurrent Integrator

tions.

Figure 8: Medical Instrument Preamp

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PROOUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARAANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have beBn characterized but are not tested.

7-44

ICL76XX
O.2.F

II-30k

l&Ok

O.~F

l~

lOOk

680k

1

Slk

~
~

r-- -

r--

360k

INPUT

'"

O.I.F

O.l~F

O.~F

I

•
I
L_-If-=_.J

360k

1M

7

1M

r
[
L_-Ir:_.J

OUTPUT

0307-36

The low bias currents permit high resistance and low capacitance values to be used to achieve low frequency cutoff. fc~ 10Hz, AVCL ~4, Passband
ripple~O.ldB

'Note that small capacitors (25-50pF) may be needed for stability in some cases.

Figure 9: Fifth Order Chebyshev Multiple Feedback Low Pass Filter

16k

•

1601<
1601<
> -......-VOUT

0307-37

Note that 10 on each amplifier may be different. AVCL ~ 10, Q ~ 100, fo ~ 100Hz.

Figure 10: Second Order Biquad Bandpass Filter
+BV

TA .. +12S'C
V,N

>-----VOUT

1.5k

0307-39

0307-38

Figure 12: Vos Null Circuit

NOTE 1. For devices with external compensation. use 33pF.
2. For devices with programmable standby current, connect
10 pin to v- (lo~lmA mode).

Figure 11: Burn-In and Life Test Circuit
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tssted.

7·45

D~DIL

g ICL7650
U)

!:.i Chopper-Stabilized

g Operational Amplifier
GENERAL DESCRIPTION

FEATURES

The ICL7650 chopper-stabilized amplifier is a high-performance device which offers exceptionally low offset voltage and input-bias parameters, combined with excellent
bandwidth and speed characteristics. Intersil's unique
CMOS approach to chopper-stabilized amplifier design
yields a versatile precision component that can replace
more expensive hybrid or monolithic devices.
The chopper amplifier achieves its low offset by comparing the inverting and non-inverting input voltages in a nulling
amplifier, nulled by alternate clock phases. Two external capacitors are required to store the correcting potentials on
the two amplifier nulling inputs; these are the only external
components necessary.
The clock oscillator and all the other control circuitry is
entirely self-contained, however the 14-pin version includes
a provision for the use of an external clock, if required for a
particular application. In addition, the ICL7650 is internally
compensated for unity-gain operation.
An enhanced direct replacement for this part called
ICL7650S will become available shortly and will be more
appropriate for new designs.

• Extremely Low Input Offset Voltage - 2,..,V
• Low Long-Term and Temperature Drifts of Input
Offset Voltage
• Low DC Input Bias Current - 10pA (20pA 7650B)
• Extremely High Gain, CMRR and PSRR - Min 120dB
• High Slew Rate-2.5V/,..,s
• Wide Bandwidth - 2M Hz
• Unity-Gain Compensated
• Very Low Intermodulation Effects (Open Loop Phase
Shift < 10'C @ Chopper Frequency)
• Clamp Circuit to Avoid Overload Recovery Problems
and Allow Comparator Use
• Extremely Low Chopping Spikes at Input and Output

ORDERING INFORMATION
Temperature Range

Package

ICL7650CPA-1

O'Cta +70'C

8-PIN Plastic

ICL7650BCPA-1

O'Cto +70'C

8-PIN Plastic

ICL7650CPD

O'Cto +70'C

14-PIN Plastic

Part

ICL7650BCPD

O'Cto +70'C

14-PIN Plastic

ICL7650CTV-1

O'Cto +70'C

8-PIN TO-99

ICL7650BCTV-1

O'Cto +70'C

8-PIN TO-99

ICL76501JA-1

- 25'C to + 85'C

8-PIN CERDIP

ICL7650BIJA-1

- 25'C to + 85'C

8-PIN CERDIP

ICL7650lJD

- 25'C to + 85'C

14-PIN CERDIP

ICL7650BIJD

- 25'C to + 85'C

14-PIN CERDIP

ICL76501TV-1

-25'C to +85'C

8-PINTO-99

ICL7650BITV-1

- 25'C to + 85'C

8-PIN TO-99

ICL7650MJD

-55'Cto + 125'C

14-PIN CERDIP

ICL7650BMJD

-55'C to + 125'C

14-PIN CERDIP

ICL7650MTV-1

-55'C to + 125'C

8-PINTO-99

ICL7650BMTV-1

- 55'C to + 125'C

8-PINTO-99

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
302061-004

NOTE: All typical vs/uss haYS been charactBrlzsd but lW not t(flsted.

7-46

ICL7650
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V+ to V-) ............... 18 Volts
Input Voltage .............. (V+ +0.3) to (V- -0.3) Volts
Voltage on oscillator control pins .............. V+ to Vexcept EXT CLOCK IN: ..... (V+ +0.3) to (V+ -6.0) Volts
Duration of Output short circuit ................ Indefinite
Current into any pin ............................. 10mA
-while operating (Note 4) ...................... 100l'-A

Cont. Total Power Dissipn (TA = 2S'C)
CERDIP Package ........................... SOOmW
Plastic Package ............................. 37SmW
TO-99 ..................................... 2S0mW
Storage Temp. Range . . . . . . . . . . . . . . . . .. - 6S'C to 1S0'C
Operating Temp. Range .................... See Note 1
Lead Temperature (Soldering, 10sec) ............. 300'C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the devics. These are stress ralings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CEXTB

CEXTA

INT/EXT

CEXTB

EXT ClK IN

CEXTA

V+/CASE

- IN

NC(GUARD)

OUTPUT

+ IN

INT ClK OUT

3

- IN

v+

+ IN

OUTPUT

9

NC(GUARD)

V-

CRETN

a - PIN DIP

14 - PIN DIP
0308-27

0308-26

~EXTCl.KItj

OUTPUT CLAMP

v-

~A"CLKOVT
~,

~.

----f""""l-- '
0308-1

Figure 1: Functional Diagram

v-

a LEAD TO - 99

0308-2

Figure 2: Pin Configuration

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but ar6 not t6stBri.

7-47

•

o

II)

IIO~OIl.

ICL7650

CO

2.... ELECTRICAL CHARACTERISTICS
Test Conditions: V+ = +5V, V- = -5V, TA= + 25°C, (unless otherwise specified)
Symbol

Parameter

Limits 7650

Test Conditions
Min

Vos

Input Offset Voltage

t..Vos
t..T

Average Temp. Coefficient
of Input Offset Voltage

t..Vos
t..t

Change in Input
Offset Voltage
With Time

Min

Max

±2
±5

± 10.0

Max

TA= + 25°C
-25°C~
~
~
!

OUTPUT WITH ZERO INPUT;
GAIN = 1000; BALANCED SOURCE
IMPEDANCE = 10K!)

INPUT OFFSET VOLTAGE
va CHOPPING FREQUENCY

INPUT OFFSET VOLTAGE CHANGE
va. SUPPLY VOLTAGE

-I

-2

r---+---+---+ --+-~--="'1

t--+-~ ---+-~--I

.t +,
~

+1

I

20

o

20

~

ii+4

0

...

~

+2
123456781

10

12

14

"

o~
10

~

100

Tille· IRS

tk

10k

TOTAL SUPPLY VOLTAGE - VOLTS
CH~

0308-11

FREQUENCY (CLOCK.(IU1) liz

0308-9

0308-10

INTERSIL'S SOLE AND EXCLUSIVE WARRANTV OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTV ARTICLE OF THE CONDITION OF SALETHE WARRANTY SHALL BE EXCLUSive AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILlTV AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical vslues have bstJn characterized but are not tested.

7·49

•

~

......

C)

51!

ICL7650
TYPICAL PERFORMANCE CHARACTERISTICS

,.

(Continued)

OPEN LOOP GAIN AND PHASE SHIFT
VB. FREQUENCY

"

OPEN LOOP GAIN AND PHASE SHIFT
VB FREQUENCY

,

,

140

"\

--

1'\

,~

RL. - 10k.n.

ear .~'F
10

,.

70

.

, ,-

'\
1

I" ,.
1ID

II:

I'

CI.01 0.1

"
-•

lOS

1

.Ii:

Ii

,

,/

I•

1

110

1"\ ,

I

'\.

" 1\
"r-

i'--.

~

40 _~L = 10k.n.

1IDE

c:.r ·tO~i
10

CI.01 0.1

1k 10k ,.k

, . 1k

10k 100k

FREQUENCY Hz

FIIEOUENCY Hz

0308-13

0308-12

VOLTAGE FOLLOWER LARGE SIGNAL
PULSE RESPONSE·

I!!

~

+1

IU

!

i'"'

i!;
0

...,.,.,

+2

0

.-'-V

CLOCK OUT
LOW

-1

/}

~

VOLTAGE FOLLOWER LARGE SIGNAL
PULSE RESPONSE·

...

a

,
I

fit

+2

I

>

\

1

CLOCK OUT "H \
HIGH

CLOCK OUT
HIGH

II

-2

o

0.5
1
1.5
TIME .,.11

2

o

2.5

CLOCK OUT
LOW

~
~

1

'" L:1

0.5
1
TIME .,.11

1.5

0308-14

2

0308-15

• THE TWO DIFFERENT RESPONSES CORRESPOND
TO THE TWO PHASES OF THE CLOCK.
P-CHANNEL CLAMP CURRENT vs.
OUTPUT VOLTAGE

NooCHANNEL CI..AMP CURRENT VB.
OUTPUT VOLTAGE

100,.A

~

1.,..

... 1,.,.

100nA

iii! 100nA

1

211:

~B

1GIIA

ZL

1nA

100pA
10pA

1GIIA

:i~

1nA

o

100pA
10pA

1pA
+0.1

+0.1

+0.4

+0.2

1pA

o

OUTPUT VOLTAGE t.V·

-o.a

-0.,

-0.4

-8.2

o

OUTPUT VOLTAGE t.V+
0308-18

0308-17

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDrTlON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITINESS FOR A PARTICULAR USE.
NOTE: AU typ/cB1 values havs bfI6fI chsf8CfBrIzsd but sre not t6sted.

7-50

IIlD~DI!..

ICL7650
Output Clamp

;>~I---.

The OUTPUT CLAMP pin allows reduction of the overload recovery time inherent with chopper-stabilized amplifiers. When tied to the inverting input pin, or summing junction, a current path between this point and the OUTPUT pin
occurs just before the device output saturates. Thus uncontrolled differential input voltages are avoided, together with
the consequent charge build-up on the correction-storage
capacitors. The output swing is slightly reduced.

OUTPUT

n
r....
GI

(II

o

Clock
0.1# Each

The ICl7650 has an internal oscillator giving a chopping
frequency of 200Hz, available at the CLOCK OUT pin on the
14-pin devices. Provision has also been made for the use of
an external clock in these parts. The INT /EXT pin has an
internal pull-up and may be left open for normal operation,
but to utilize an external clock this pin must be tied to V - to
disable the internal clock. The external clock signal may
then be applied to the EXT. CLOCK IN pin. At low frequencies, the duty cycle of the external clock is not critical, since
an internal divide-by-two provides the desired 50% switching duty cycle. However, since the capacitors are charged
only when EXT ClK IN is HIGH, a 50-BO% positive duty
cycle is favored for frequencies above 500Hz to ensure that
any transients have time to settle before the capacitors are
turned OFF. The external clock should swing between V+
and GROUND for power supplies up to ±6V, and between
V+ and V+ -6V for higher supply voltages. Note that a
signal of about 400Hz will be present at the EXT ClK IN pin
with INT /EXT high or open. This is the internal clock signal
before the divider.
In those applications where a strobe signal is available,
an alternate approach to avoid capacitor misbalancing during overload can be used. If a strobe signal is connected to
EXT ClK IN so that it is low during the time that the over- .
load signal is applied to the amplifier, neither capacitor will
be charged. Since the leakage at the capacitor pins is quite
low at room temperature, the typical amplifier will drift less
than 10,,"V/sec, and relatively long measurements can be
made with little change in offset.

0308-18

Figure 3: ICL7650/B Test Circuit

DETAILED DESCRIPTION
Amplifier
The functional diagram shows the major elements of the
ICl7650. There are two amplifiers, the main amplifier, and
the nulling amplifier. Both have offset-null capability. The
main amplifier is connected continuously from the input to
the output, while the nulling amplifier, under the control of
the chopping oscillator and clock circuit, alternately nulls
itself and the main amplifier. The nulling connections, which
are MOSFET gates, are inherently high impedance, and two
external capacitors provide the required storage of the nulling potentials and the necessary nulling-loop time constants. The nulling arrangement operates over the full common-mode and power-supply ranges, and is also independent of the output level, thus giving exceptionally high
CMRR, PSRR, and AVOL.
Careful balancing of the input switches, and the inherent
balance of the input circuit, minimizes chopper frequency
charge injection at the input terminals, and also the feedforward-type injection into the compensation capacitor, which
is the main cause of output spikes in this type of circuit.

Intermodulation
Previous chopper-stabilized amplifiers have suffered from
intermodulatibn effects between the chopper frequency and
input signals. These arise because the finite AC gain of the
amplifier necessitates a small AC signal at the input. This is
seen by the zeroing circuit as an error signal, which is
chopped and fed back, thus injecting sum and difference
frequencies and causing disturbances to the gain and
phase vs. frequency characteristics near the chopping frequency. These effects are substantially reduced in the
ICl7650 by feeding the nulling circuit with a dynamic current, corresponding to the compensation capacitor current,
in such a way as to cancel that portion of the input signal
due to finite AC gain. Since that is the major error contribution to the ICl7650, the intermodulation and gain/phase
disturbances are held to very low values, and can generally
be ignored.

BRIEF APPLICATION NOTES
Component Selection
The two required capacitors, CEXTA and CEXTB, have optimum values depending on the clock or chopping frequency. For the present internal clock, the correct value is
O.lp.F, and to maintain the same relationship between the
chopping frequency and the nulling time constant this value
should be scaled approximately in proportion if an external
clock is used. A high-quality film-type capaCitor such as mylar is preferred, although a ceramic or other lower-grade
capacitor may prove suitable in many applications. For
quickest settling on initial turn-on, low dielectric absorption
capacitors (such as polypropylene) should be used. With
ceramic capacitors, several seconds may be required to
settle to 1,,"V.

Capacitor Connection

Static Protection

The null/storage capacitors should be connected to the
CEXTA and CEXTB pins, with a common connection to the
CRETN pin. This connection should be made directly by either a separate wire or PC trace to avoid injecting load current IR drops into the capacitive circuitry. The outside foil,
where available, should be connected to CRETN.

All device pins are static-protected by the use of input
diodes. However, strong static fields and discharges should
be avoided, as they can cause degraded diode junction
characteristics, which may result in increased input-leakage
currents.

INTERSIL'S SOLE ANO EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values havs been charscterizsd but are not test6d.

7-51

•

~

o

ICL7650

....

..I

~

~
~
""·"~ou"''''
".

~

INPUT

EXTERtiAL
CAPACITORS

OUTPUT::'~70

OUTPUT

•

EXTERNAL

~4~'~
"-(!I

CAPACITORS,
CflETN

v-

~

'F

GUARD

0308-19

INVERTING AMPLIFIER

0308-28

0308-29

FOLLOWER

NON-INVERTING
AMPLIFIER

Figure 4: Connection of Input Guards

BOTTOM VIEW

Board Layout lor Input
Guarding with TO-99 Package

0308-30

Latchup Avoidance

Guarding

Junction-isolated CMOS circuits inherently include a parasitic 4-layer (p-n-p-n) structure which has characteristics
similar to an SCR. Under certain circumstances this junction
may be triggered into a low-impedance state, resulting in
excessive supply current. To avoid this condition, no voltage greater than 0.3V beyond the supply rails should be
applied to any pin. In general, the amplifier supplies must be
established either at the same time or before any input signals are applied. If this is not possible, the drive circuits
must limit input current flow to under 1mA to avoid latchup,
even under fault conditions.

Extra care must be taken in the assembly of printed circuit boards to take full advantage of the low input currents
of the ICL7650. Boards must be thoroughly cleaned with
TCE or alcohol and blown dry with compressed air. After
cleaning, the boards should be coated with epoxy or silicone rubber to prevent contamination.
Even with properly cleaned and coated boards, leakage
currents may cause trouble, particularly since the input pins
are adjacent to pins that are at supply potentials. This leakage can be significantly reduced by using guarding to lower
the voltage difference between the inputs and adjacent
metal runs. Input guarding of the 8-lead TO-99 package is
accomplished by using a 10-lead pin circle, with the leads of
the device formed so that the holes adjacent to the inputs
are empty when it is inserted in the board. The guard, which
is a conductive ring surrounding the inputs, is connected to
a low impedance point that is at approximately the same
voltage as the inputs. Leakage currents from high-voltage
pins are then absorbed by the guard.
The pin configuration of the 14-pin dual in-line package is
designed to facilitate guarding, since the pins adjacent to
the inputs are not used (this is different from the standard
741 and lOlA pin configuration, but corresponds to that of
the LM108).

Output Stage/Load Driving
The output circuit is a high-impedance type (approximately 18kO), and therefore with loads less than this value, the
chopper amplifier behaves in some ways like a transconductance amplifier whose open-loop gain is proportional to
load resistance. For example, the open-loop gain will be
17dB lower with a lkO load than with a 10kO load. If the
amplifier is used strictly for DC, this lower gain is of little
consequence, since the DC gain is typically greater than
120dB even with a 1kO load. However, for wideband applications, the best frequency response will be achieved with a
load resistor of 10kO or higher. This will result in a smooth
6dB/octave response from O.lHz to 2MHz, with phase
shifts of less than 10' in the transition region where the
main amplifier takes over from the null amplifier.

Pin Compatibility
The basic pinout of the 8-pin device corresponds, where
possible, to that of the industry-standard 8-pin devices, the
LM741 , LM10l, etc. The null-storing external capacitors are
connected to pins 1 and 8, usually used for offset null or
compensation capaCitors, or simply not connected. In the
case of the OP-05 and OP-07 devices, the replacement of
the offset-null pot, connected between pins 1 and 8 and
V+, by two capaCitors from those pins to pin 5, will provide
easy compatibility. As for the LM108, replacement of the
compensation capaCitor between pins 1 and 8 by the two
capaCitors to pin 5 is all that is necessary. The same opera.
tion, with the removal of any connection to pin 5, will suffice
for the LM10l, !LA748, and similar parts.
The 14-pin device pinout corresponds most closely to
that of the LM108 device, owing to the provision of "NC"
pins for guarding between the input and all other pins. Since
this device does not use any of the extra pins, and has no
proviSion for offset-nulling, but requires a compensation capacitor, some changes will be required in layout to convert it
to the ICL7650.

Thermo-Electric Effects
The ultimate limitations to ultra-high preciSion DC amplifiers are the thermo-electric or Peltier effects arising in thermocouple junctions of dissimilar metals, alloys, silicon, etc.
Unless all junctions are at the same temperature, thermoelectric voltages typically around O.l!LVrC, but up to tens of
!Lvrc for some materials, will be generated. In order to
realize the extremely low offset voltages that the chopper
amplifier can provide, it is essential to take special precautions to avoid temperature gradients. All components
should be enclosed to eliminate air movement, especially
that caused by power-dissipating elements in the system.
Low thermoelectric-coefficient connections should be used
where possible and power supply voltages and power dissipation should be kept to a minimum. High-impedance loads
are preferable, and good separation from surrounding heatdissipating elements is advisable.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY ANO FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

7-52

.D~DI!.

ICL7650
TYPICAL APPLICATIONS

...
GI
CII

+7.5V

Clearly the applications of the ICL7650 will mirror those of
other op. amps. Anywhere that the performance of a circuit
can be significantly improved by a reduction of input-offset
voltage and bias current, the ICL7650 is the logical choice.
Basic non-inverting and inverting amplifier circuits are
shown in Figures 5 and 6. Both circuits can use the output
clamping circuit to enhance the overload recovery performance. The only limitations on the replacement of other op
amps by the ICL7650 are the supply voltage (±8V max.)
and the output drive capability (10kO load for full swing).
Even these limitations can be overcome using a simple
booster circuit, as shown in Figure 7, to enable the full output capabilities of the LM741 (or any other standard device)
to be combined with the input capabilities of the ICL7650.
The pair form a composite device, so loop gain stability,
when the feedback network is added, should be watched
carefully.

n
r0

...
IN

OUT

,.
0308-22

Figure 7: Using 741 to Boost Output Drive
Capacity

->------f.

."'>------4

>---r--OUTPUT

cJl---_vour

.,

"'·
..,11 .........
FOR PULL CLAMIt EFFECT

0308-23

Figure 8: Low Offset Comparator
0308-20

Figure 5: Non Inverting Amplifier
With (Optional Clamp)

Normal logarithmic amplifiers are limited in dynamic range
in the voltage-input mode by their input-offset voltage. The
built-in temperature compensation and convenience features of the ICL8048 can be extended to a voltage-input
dynamic range of close to 6 decades by using the ICL7650
to offset-null the ICL8048, as shown in Figure 9. The same
concept can also be used with such devices as the HA2500
or HA2600 families of op amps to add very low offset voltage capability to their very high slew rates and bandwidths.
Note that these circuits will also have their DC gains,
CMRR, and PSRR enhanced.

NOTE: R, RalNDICATES THE PARALLEL COMBINATION OF R,
ANDRa

" J1-1----0U1PUT
(R,/IRI);e tOOkfI
FOIII FULL CLAMP 'FFECI'

I.,,.,

8.1....

0308-21

Figure 6: Inverting Amplifier
With (Optional) Clamp
NOTE: R, RalNDICATES THE PARALLEL COMBINATION OF R,
ANDRa

Figure 8 shows the use of the clamp circuit to advantage
in a zero-offset comparator. The usual problems in using a
chopper stabilized amplifier in this application are avoided,
since the clamp circuit forces the inverting input to follow
the input Signal. The threshold input must tolerate the output clamp current:::: VIN/R without disturbing other portions
of the system.

0308-24

Figure 9: ICL8048 Offset Nulled by ICL7650
FOR FURTHER APPLICATIONS ASSISTANCE, SEE A053

AND R017

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPUED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABIUTY AND RTNESS FOR A PARTICULAR USE.

NOTE: All typical - . ha... bsBn _torlzsd but.,. not I6stod.

7-53

•

!
~

2

ICL7650S
Super Chopper-Stabilized
Operational Amplifier
GENERAL DESCRIPTION

FEATURES

The ICL7650S Super Chopper-Stabilized Amplifier offers
exceptionally low input offset voltage and is extremely stable with rllspect to time and temperature. It is a direct replacement for t~\l industry-standard ICL7650 offering
Improved input offset voltage, lower input offset voltage
temperature coefficient, reduced input bias current, wider
common mode voltage range and ESD protection greater
than 2000 volts. All improvements are highlighted in bold
italics in the Electrical Characteristics section. Critical parameters are guaranteed over the entire commercial,
industrial and military temperature ranges.
Intersil's unique CMOS chopper-stabilized amplifier circuitry is user-transparent, virtually eliminating the traditional
chopper amplifier problems of intermodulation effects,
chopping spikes, and @verrange lock-up.
The chopper amplifier achieves its low offset by comparing the inverting and non-inverting input voltages in a nulling
amplifier, nulled by alternate clock phases. Two external capacitors are required to store the correcting potentials on
the two amplifier nulling inputs; these are the only external
components necessary.
The clock oscillator and all the other control circuitry is
entirely self-contained. However the 14-lead version includes a provision for the use of an external clock, if required for a particular application. In addition, the ICL7650S
is internally compensated for unity-gain operation.

• Guaranteed Max Input Offset Voltage for All
Temperature Ranges
• Low Long-Term and Temperature Drifts of Input
Offset Voltage
• Guaranteed Max Input Bias Current-10 pA
• Enhanced ESD Protection > 2000V
• Extremely Wide Common Mode Voltage Range+3.5 to -5V
• Reduced Supply Current-2 mA
• Guaranteed Minimum Output Source/Sink Current
• Extremely High Gain-150 dB
• Extremely High CMRR and PSRR-140 dB
• High Slew Rate-2.5V/ p.s
• Wide Bandwidth-2 MHz
• Unity-gain Compensated
• Clamp Circuit to Avoid Overload Recovery Problems
and Allow Comparator Use
• Extremely Low Chopping Spikes at Input and Output
• Characterized Fully Over All Temperature Ranges
• Improved, Direct Replacement for Industry-Standard
ICL7650 and other Second-Source Parts

ORDERING INFORMATION
Part

Temperature Range

ICL7650SCPA-1

O'Cto +70'C

Package
8-Pin Plastic

ICL7650SCPD

14-Pin Plastic

ICL7650SCTV-1

8-PinTO-99

ICL7650SIJA-1

- 25'C to + 85'C

8-Pin CERDIP

ICL7650SIPA-1

8-Pin Plastic

ICL7650SIPD

14-Pin Plastic

ICL7650SIJD

14-Pin CERDIP

ICL7650SITV-1
ICL7650SMJD

8-PinTO-99
- 55'C to + 125'C

14-Pin CERDIP
8-PinTO-99

ICL7650SMTV-1

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

302161-002

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterlzsd but are not tested

7-54

IIn~ol!..

ICL7650S

n
r....
CI
CII

ABSOLUTE MAXIMUM RATINGS
Storage Temperature Range ....•........ -55·Cto 150·C
Lead Temperature (Soldering, 10 sec) ............ + 300·C
Operating Temperature Range
ICL7650SC ...•..•.••.................. O·C to + 70·C
ICL7650S1 .......................... - 25·C to + 85·C
ICL7650SM ...........•............ -55·C to + 125·C

Total Supply Voltage ry+ to V-I .......•...••....•.. 18V
Input Voltage ................... (V+ +0.3) to ry- -0.3)
Voltage on Oscillator Control Pins .............. V+ to VDuration of Output Short Circuit ................. Indefinite
Current into Any Pin ............................. 10 mA
-while operating (Note 1) ....................... 100 /LA
Continuous Total Power Dissipation (TA = 25·C)
CERDIP Package ............................ 500 mW
Plastic Package ............................. 375 mW
TO-99 ............................•....•.... 250 mW

i

NOTE: Stresses above those lisl9d under "Abso/uts Maximum Ratings"
may cause permafl9nt damage to the device. These are stress ",lings only
and functional opBfBtion of the device at these or any other conditions
above those indlcal9d in the opBfBtional sections of the spacif/cations is not
implied. Exposure to absolute maximum ",ting conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
Test Conditions: ry+ = +5V, V- = -5V, TA = + 25·C, Test Circuit as in Fig. 3 (unless otherwise specified)
Parameter

Symbol

Limits

Test Conditions
Min

Vos

Input Offset Voltage
(Note 2)

aVos/aT

Average Temperature
Coenlclent of Input Offset
Voltage (Note 2)

aVos/at

Change in Input
Offset with Time

IbIBs

Input BIas Current
11(+)1,11(-)1

los

Input Offset Current
Ii(-)-I(+)I

RIN

Input Resistance

A VOL

Large Signal VoUage GaIn
(Note 2)

VOUT

Output Voltage Swing
(Note 3)

TA = +25·C

Units

Typ

Max

±0.7

+5

O·C

S;

TA

S;

+70·C

±1

±8

-25·C

S;

TA

S;

+85·C

±2

±10

±4

±2O

-55·C

S;

TA

S;

+125·C

O·C

S;

TA

S;

+70·C

0.02

-25·C

S;

TA

S;

+ 85·C

0.02

-55·C

S;

TA

S;

+ 125·C

0.03

/LV/·C
0.1

100
TA = 25·C
O·C

S;

TA

S;

+70·C

-25·C

S;

TA

S;

nVNmonth

4

10

5

20

+85·C

20

50

-55·C s; TA s; +85·C

20

50

+85·C

100

500

8

20

S;

TA

S;

+125·C

TA = 25·C
O·C

S;

TA

S;

+70·C

10

40

-25·C

S;

TA

S;

+85·C

20

40

-55·C

S;

TA

S;

+85·C

20

40

+85·C

S;

TA

S;

+125·C

20

50

1012
RL =10 kO,Vo= ±4V,TA=25·C

135

O·C

S;

TA

S;

+70·C

130

-25·C

S;

TA

S;

+85·C

130

-55·C

S;

TA

S;

+125·C

RL = 100 kO

pA

pA

0

150
dB

120
±4.7

RL = 10kO

/LV

±4.85

V

±4.95

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AN typIcsI valutls have bBBn chsrscflHfz8d but II/'tI not fBsltId.

7-55

•

IID~DIL

!10 ICL7650S
...
..I ELECTRICAL CHARACTERISTICS (Continued)

..

1=2 Test Conditions: (V+ = +5V, V- = -5V, TA = + 25·C, Test Circuit as in Fig. 3 (unless otherwise specified)
Symbol

CMVR

CMRR

Common Mode Voltage Range
(Note 2)

Common Mode Re/ectlon RatIo
(Note 2)

Limits

Test Conditions

Parameter

TA = 25·C

Typ

Max

-5

-5.210 +4

+3.5

O·C

S;

TA

S;

+70·C

-5

+3.5

-25·C

S;

TA

S;

+85·C

-5

+3.5

-55·C

S;

TA

S;

+ 125·C

CMVR= -5Vto +3.5V,TA=25·C

-5

120

O·C

S;

TA

+70·C

120

25·C

S;

TA S; + 85·C

115

-55·C

S;

TA

S;

+125·C

110

PSRR

Power Supply Re/ectlon RatIo

V+, V- = ±3Vto ±8V

120

en

Input Noise Voltage

Rs = 1000, f = OCto 10 Hz

in

Input Noise Current

f = 10 Hz

GBW

Gain Bandwidth Product

SR

Slew Rate

tr

dB

140

dB

2

",Vp-p

O.ot

pA/,!Hz
MHz

VI",s

Rise TIme

0.2

",s

Overshoot

20

Isupp

Supply Current

fch

+3.5

140

2.5

Operating Supply Range

10 sink

S;

V

2

V+ toV-

10 source

Units

Min

Output Source Current

Output Sink Current

CL = 50 pF, RL = 10 kO

4.5
2

No Load, TA = 25·C
O·C

S;

TA

S;

+70·C

3.2

S;

TA

S;

+85·C

3.5

-55·C

S;

TA

S;

+125·C

TA = 25·C
O·C

S;

TA

S;

+70·C

2.3

-25·C

S;

TA

~

+85·C

2.2

-55·C

S;

TA';; +125·C

4.5
mA

2
25

O·C

S;

TA

S;

+70·C

20

-25·C

S;

TA

S;

+85·C

19

-55·C

S;

TA';; + 125·C

30
mA

17

Pins 12 & 14 Open

120

250

Clamp ON Current (Note 4)

RL = 100 kO, TA = 25·C

25

70

-4V

S;

Vout

S;

TA

S;

+4V, TA = 25·C

0.001

375

5

10

-25·C';; TA';; +85·C

10

-55·C';; TA

15

S;

S;

+125·C

Hz
",A

+70·C

O·C

mA

4
2.9

TA = 25·C

V

3

-25·C

Internal Chopping Frequency

Clamp OFF Current
, (Note 4)

%

16

nA

NOTE 1: Umlting Input current to 100 p.A Is recommended to avoid latchup problems. Typically 1 mA Is safe, however this Is not guaranteed.
2: These psramefers are guaranteed by design and characterization, but not tested at temperature extremes because thermocouple effects prevent precise
measurement of these voltages In automatic test equipment.
3: OUTPUT CLAMP not connected. See typical characteristic curves for output swing vs. clamp current characteristics.

4: See OUTPUT CLAMP under detailed description.

S: All signHicant Improvements over the Industry-standard ICL7650 are highlighted In bold Itslles.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTe: All typical values hsvtllHHm chsract9rlzed but arB not tested

7-56

ICL7650S

..CUOUT~C
:::~!

:H

II....

... o-..--------i
- IN

o-r-r--------1
i
CLAMP

T

~EXTCL.,N

~ •• CL.OUT
~l

~.

---r-L- C
0089-1

Figure 1: Functional Diagram

CEXTA

CEXTB
CEXTA

CEXTB

+IN

V+/CASE NC(GUARD)
-IN
OUTPUT
+IN

v-

CRETN

-IN

INT/EXT
EXT CLK IN
INT CLK OUT
v+
OUTPUT
OUTPUT CLAWP

NC(GUARD)
V-

8- PIN DIP
(PA-l. JA-l)

CRETN
14-PIN DIP
(PD. JD)

8 LEAD TO 99

(TV-I)

0089-2

Figure 2: Pin Configurations

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AD typical llSiues have beBn charact6rIz6d but sre not fBst6d.

7-57

~ ICL7650S
10
CO

~ TYPICAL PERFORMANCE CHARACTERISTICS

g

Supply Current
vs. Supply Voltage

VS.

v

--

~

1

I

r- r- r-

o

o

4

Maximum Output Current
VS. Supply Voltage

Supply Current
Ambient Temperature

10

12

14

-50 -25

16

0

25

50

75

100 125

AMBIENT TEMPERATURE-<>C

TOTAL SUPPLY VOLTAGE-VOLTS

0089-4

0089-3

TOTAL SUPPLY VOLTAGE - VOLTS

0089-5

Clock Ripple Referred to the
Input VS. Temperature

Common-Mode Input Voltage
Range vs. Supply Voltage

10Hz pop Noise Voltage VS.
Chopping Frequency

/'

,l
~

~

~¢~-

/

/~" t - - -

8ROAD8AND
=_NOISE

L

1\

~$
-<>;t'

~$

--

lAy - 1000)

--

\

===

!

o

o

;

r--.

I

I
I

2345678

so

EACH SUPPLY VOLTAGE (+ ANO-)

0089-6

7S

100

125

150

10

TEMPERATURE - ·C

0089-7

100

lk

10k

CHOPPING FREQUENCY {CLOCK.QUl) Hz
0089-8

Input Offset Voltage Change
vs. Supply Voltage
~

w +2r-~--t-~-+---~~

I +1r-~---+--~--~--+-~

1
~

iI

Input Offset Voltage
Chopping Frequency

VS.

+ar-~---r--~--~--r--'

I

>

Output with Zero Input;
Gain = 1000; Balanced Source
Impedance = 10 kO

+. t-HtltHII-l+1t
~ +. t-HtltHII-l-l-1t
~

w

-1r---+--+--4--~-+~~

iIi

-21--+--t--

o +2 t-HtltHII-l+1t

----~-+----l

t

+4
~~+H*K---l~~~~~~~
12345878'
TIME· ma

-3 .L....-I__--'-__..l.._..L.__.l---J

10

12

1.

1.

tk

10k

0089-11

TOTAL SUPPLY VOlTA.GE - VOLTS

CHOPPING FREQUENCY {CLOCK'()U1) Hz
0089-9

0089-10

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

7-58

ICL7650S
TYPICAL PERFORMANCE CHARACTERISTICS

t.

(Continued)

Open Loop Gain and Phase Shift
vs. Frequency

t40

',.
I
too

!.

1.

"

"\

101
I

1"- I" ..-'- .

"-

I.
40

Open Loop Gain and Phase Shift
vs. Frequency

RI. = 10k.n
C,.Ot·F

0.01 0.,

to

tOO

.~

i

,
~

..

'I'

70~
~
"- I"- .!!;
"i
110 III
i"-t
130 f

l\.

./

•

III

0

t301

40 _RL = 10k.n

1"\

cyr .Io~l

I"
0.01

10k lOOk

lOIS
I

"-

• --

i

1111~

Ik

'00

C

Q

"-

CI

.
8

70S

,.

..•z

t40

10

0.1

100

Ik

"

10k lOOk

FREQUENCY H.

FREQUENCY HI

0089-13

0089-12

Voltage Follower Large Signal
Pulse Response'

~
0

> +1
CI

~
0

....'"'"
>

0

0

~

.....,1...

+2

III

Voltage Follower Large Signal
Pulse Response'

, ;)

CLOCK OUT
LOW

~

II

-2

o

III

VI

+1

~

....'"
'"

CLOCK OUT
HIGH

0

0.5
1.5
TIME· .s

2

0

§!

I

I

)..
~
CLOCK OUT ..K \
!
:

§!
CI

J

-I

I
+2

HIGH

-I

-2

~
I 1\\ 1
"I
L1

o

2.5

CLOCK OUT
LOW

0.5
TIME ·~s

1.5

2

0089-14

0089-15

'THE TWO DIFFERENT RESPONSES CORRESPOND TO THE TWO PHASES OF THE CLOCK.

N-Channel Clamp Current
vs. Output Voltage

P-Channel Clamp Current
vs. Output Voltage

I"'"
!i
lOOnA

=

1"""
I,.A

iilllOOllA

za:
~i3

IOnA

:z: ..

InA

~~

/

lOOpA

CJ

10pA

IOnA

InA
lOOpA - -

IOpA

lpA
+0.8

+0.8

+0.4

+0.2

L

1.

lpA

o

-0.8

OUTPUT VOLTAGE tJ.V-

-0.8

-0.4

-0.2

o

OUTPUT VOLTAGE tJ.y+
0089-16

0089-17

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRES!:'" IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been characterized but are not tested.

7-59

~

.U~OI!..

ICL7650S

II)

...,..

CI)

Output Clamp

S:!

The OUTPUT CLAMP pin allows reduction of the overload recovery time inherent with chopper-stabilized amplifiers. When tied to the inverting input pin, or summing junction, a current path between this point and the OUTPUT pin
occurs just before the device output saturates. Thus uncontrolled input differential inputs are avoided, together with the
consequent charge build-up on the correction-storage capacitors. The output swing is slightly reduced.

OUTPUT

Clock
0089-18

The ICL7650S has an internal oscillator, giving a chopping frequency of 200 Hz, available at the CLOCK OUT pin
on the 14-pin devices. Provision has also been made for the
use of an external clock in these parts. The INT /EXT pin
has an internal pull-up and may be left open for normal operation, but to utilize an external clock this pin must be tied
to Y - to disable the internal clock. The external clock signal
may then be applied to the EXT CLOCK IN pin. An internal
divide-by-two provides the desired 50% input switching duty
cycle. Since the capacitors are charged only when EXT
CLOCK IN is high, a 50%-80% positive duty cycle is recommended, especially for higher frequencies. The external
clock can swing between Y+ and Y-. The logic threshold
will be at about 2.5Y below Y+. Note also that a signal of
about 400 Hz, with a 70% duty cycle, will be present at the
EXT CLOCK IN pin with INT /EXT high or open. This is the
internal clock signal before being fed to the divider.
In those applications where a strobe signal is available,
an alternate approach to avoid capacitor misbalancing during overload can be used. If a strobe signal is connected to
EXT CLK IN so that it is low during the time that the overload signal is applied to the amplifier, neither capacitor will
be charged. Since the leakage at the capacitor pins is quite
low at room temperature, the typical amplifier will drift less
than 10 IJ-Y/ sec, and relatively long measurements can be
made with little change in offset.

Figure 3: ICL7650S Test Circuit

DETAILED DESCRIPTION
Amplifier
The functional diagram shows the major elements of the
ICL7650S. There are two amplifiers, the main amplifier, and
the nulling amplifier. Both have offset-null capability. The
main amplifier is connected continuously from the input to
the output, while the nulling amplifier, under the control of
the chopping oscillator and clock circuit, alternately nulls
itself and the main amplifier. The nulling connections, which
are MOSFET gates, are inherently high impedance, and two
external capacitors provide the required storage of the nulling potentials and the necessary nulling-loop time constants. The nulling arrangement operates over the full common-mode and power-supply ranges, and is also independent of the output level, thus giving exceptionally high
CMRR, PSRR, and AVOL.
Careful balancing Qf the input switches, and the inherent
balance of the input circuit, minimizes chopper frequency
charge injection at the input terminals, and also the feedforward-type injection into the compensation capacitor, which
is the main cause of output spikes in this type of circuit.

Intermodulation

BRIEF APPLICATION NOTES
Component Selection

Previous chopper-stabilized amplifiers have suffered from
intermodulation effects between the chopper frequency and
input signals. These arise because the finite AC gain of the
amplifier necessitates a small AC signal at the input. This is
seen by the zeroing circuit as an error signal, which is
chopped and fed back, thus injecting sum and difference
frequencies and causing disturbances to the gain and
phase vs. frequency characteristics near the chopping frequency. These effects are substantially reduced in the
ICL7650S by feeding the nulling circuit with a dynamic current, corresponding to the compensation capacitor current,
in such a way as to cancel that portion of the input signal
due to finite AC gain. Since that is the major error contribution to the ICL7650S, the intermodulation and gain/phase
disturbances are held to very low values, and can generally
be ignored.

The two required capacitors, CEXTA and CEXTB, have optimum values depending on the clock or chopping frequency. For the preset internal clock, the correct value is 0.1 IJ-F,
and to maintain the same relationship between the chopping frequency and the nulling time constant this value
should be scaled approximately in proportion if an external
clock is used. A high-quality film-type capacitor such as mylar is preferred, although a ceramic or other lower-grade
capacitor may prove suitable in many applications. For
quickest setting on initial turn-on, low dielectric absorption
capacitors (such as polypropylene) should be used. With
ceramic capacitors, several seconds may be required to
settle to 1 IJ-Y.

Capacitor Connection

Static Protection

The null/storage capacitors should be connected to the
CEXTA and CEXTB pins, with a common connection to the
CRETN pin. This connection should be made directly by either a separate wire or PC trace to avoid injecting load current IR drops into the capacitive circuitry. The outside foil,
where available, should be connected to CRETN.

All device pins are static-protected by the use of input
diodes. However, strong static fields and discharges should
be avoided, as they can cause degraded diode junction
characteristics, which may result in increased input-leakage
currents.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

7-60

ICL7650S
R2

Rl
INPUT·JII1,........-

EXTERNAL
CAPACITORS

R2

......W.,....--,

OUTPUT

OUTPUT

OUTPUT

OUTPUT~~70
CRETN ,e5 4

/

~2
~
~ $

#

'V GAURD

Inverting Amplifier

BonOM VIEW

Follower
Non-Inverting Amplifier
Figure 4: Connection of Input Guards

0089-19

realize the extremely low offset voltages that the chopper
amplifier can provide, it is essential to take special precautions to avoid temperature gradients. All components
should be enclosed to eliminate air movement, especially
that caused by power-dissipating elements in the system.
Low thermoelectric-efficient connections should be used
where possible and power supply voltages and power dissipation should be kept to a minimum. High-impedance loads
are preferable, and good separation from surrounding heatdissipating elements is advisable.

Latchup Avoidance
Junction-isolated CMOS circuits inherently include a parasitic 4-layer (p-n-p-n) structure which has characteristics
similar to an SCR. Under certain circumstances this junction
may be triggered into a low-impedance state, resulting in
excessive supply current. To avoid this condition, no voltage greater than 0.3V beyond the supply rails should be
applied to any pin. In general, the amplifier supplies must be
established either at the same time or before any input signals are applied. If this is not possible, the drive circuits
must limit input current flow to under 1 mA to avoid latchup,
even under fault conditions.

Guarding
Extra care must be taken in the assembly of printed circuit boards to take full advantage of the low input currents
of the ICL7650S. Boards must be thoroughly cleaned with
TCE or alcohol and blown dry with compressed air. After
cleaning, the boards should be coated with epoxy or silicone rubber to prevent contamination.
Even with properly cleaned and coated boards, leakage
currents may cause trouble, particularly since the input pins
are adjacent to pins that are at supply potentials. This leakage can be significantly reduced by using guarding to lower
the voltage difference between the inputs and adjacent
metal runs. Input guarding of the 8-lead TO-99 package is
accomplished by using a 10-lead pin circle, with the leads of
the device formed so that the holes adjacent to the inputs
are empty when it is inserted in the board. The guard, which
is a conductive ring surrounding the inputs, is connected to
a low impedance point that is at approximately the same
voltage as the inputs. Leakage currents from high-voltage
pins are then absorbed by the guard.
The pin configuration of the 14-pin dual in-line package is
deSigned to facilitate guarding, since the pins adjacent to
the inputs are not used (this is different from the standard
741 and 101A pin configuration, but corresponds to that of
the LM108).

Output Stage/Load Driving
The output circuit is a high-impedance type (approximately 18 kO), and therefore with loads less than this value, the
chopper amplifier behaves in some ways like a transconductance amplifier whose open-loop gain is proportional to
load resistance. For example, the open-loop gain will be
17 dB lower with a 1 kO load than with a 10 kO load. If the
amplifier is used strictly for DC, this lower gain is of little
consequence, since the DC gain is typically greater than
120 dB even with a 1 kO load. However, for wideband applications, the best frequency response will be achieved with a
load resistor of 10 kO or higher. This will result in a smooth
6 dB/octave response from 0.1 Hz to 2 MHz, with phase
shifts of less than 10' in the transition region where the
main amplifier takes over from the null amplifier.

Thermo-Electric Effects
The ultimate limitations to ultra-high precision DC amplifiers are the thermo-electric or Peltier effects arising in thermocouple junctions of dissimilar metals, alloys, silicon, etc.
Unless all junctions are at the same temperature, thermobut up to tens
electric voltages typically around 0.1
of
for some materials, will be generated. In order to

/J-vrc

BOARD LAYOUT FOR INPUT
GUARDING WITH TO-99
PACKAGE

/J-vrc,

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are not tested

7-61

!

ICL7650S

.......

Pin Compatibility

II)
U)

g

R2

The basic pinout of the 8-pin device corresponds, where
possible, to that of the industry-standard 8-pin devices, the
LM741, LM101, etc. The null-storing external capacitors are
connected to pins 1 and 8, usually used for offset null or
compensation capacitors, or simply not connected. In the
case of the OP-05 and OP-07 devices, the replacement of
the offset-null pot, connected between pins 1 and 8 and
V +, by two capacitors from those pins to pin 5, will provide
easy compatibility. As for the LM108, replacement of the
compensation capacitor between pins 1 and 8 by the two
capacitors to pin 5 is all that is necessary. The same operation, with the removal of any connection to pin 5, will suffice
for the LM101, "A748, and similar parts.
The 14-pin device pinout corresponds most closely to
that of the LM108 device, owing to the provision of "NC"
pins for guarding between the input and all other pins. Since
this device does not use any of the extra pins, and has no
provision for offset-nulling, but requires a compensation capacitor, some changes will be required in layout to convert it
to the ICL7650S.

INPUT >"JII'iN-1

OUTPUT

0089-21

(R,IIR2) ;" 100 kU
FOR FULL CLAMP EFFECT

Figure 6: Inverting Amplifier
With (Optional) Clamp
NOTE: R,/R2 indicates the parallel combination of R, and R2

Figure 8 shows the use of the clamp circuit to advantage
in a zero-offset comparator. The usual problems in using a
chopper stabilized amplifier in this application are avoided,
since the clamp circuit forces the inverting input to follow
the input signal. The threshold input must tolerate the output clamp current Z V,N/R without disturbing other portions
of the system.

TYPICAL APPLICATIONS
Clearly the applications of the ICL7650S will mirror those
of other op amps. Anywhere that the performance of a circuit can be significantly improved by a reduction of input-offset voltage and bias current, the ICL7650S is the logical
choice. Basic non-inverting and inverting amplifier circuits
are shown in Figures 5 and 6. Both circuits can use the
output clamping circuit to enhance the overload recovery
performance. The only limitations on the replacement of
other op amps by the ICL7650S are the supply voltage
(±8V max.) and the butput drive capability (10 kO load for
full swing). Even these limitations can be overcome using a
simple booster circuit, as shown in Figure 7, to enable the
full output capabilities of the LM741 (or any other standard
device) to be combined with the input capabilities of the
ICL7650S. The pair form a composite device, so loop gain
stability, when the feedback network is added, should be
watched carefully.

OUT

0089-22

Figure 7: Using 741 to Boost
Output Drive Capacity

Your

INPUT

VTH
200 kn - 2t.tn

0089-23

Figure 8: Low Offset Comparator
R3 + (R,IIR2) ;" 100 kU
FOR FULL CLAMP EFFECT

Normal logarithmic amplifiers are limited in dynamic range
in the voltage-input mode by their input-offset voltage. The
built-in temperature compensation and convenience features of the ICL8048 can be extended to a voltage-input
dynamic range of close to 6 decades by using the ICL7650S
to offset-null the ICL8048, as shown in Figure 9. The same
concept can also be used with such devices as the HA2500
or HA2600 families of op amps to add very low offset voltage capability to their very high slew rates and bandwidths.
Note that these circuits will also have their DC gains,
CMRR, and PSRR enhanced.

0089-20

Figure 5: Non Inverting Amplifier
With Optional Clamp
NOTE: R,IR2 indicates the parallel combination of R, and R2

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valu9s have been characterized but am not fBsied.

7-62

ICL7650S

:

600k.o.

RO:

. J....w'."••

(LOW T.e.)

10 k.o.

0089-24

Figure 9: ICL8048 Offset Nulled by ICL7650S
FOR FURTHER APPLICATIONS ASSISTANCE, SEE A053 AND R017

•

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OA STATUTORY, INCLUOING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been characterized but are not tested

7-63

D~Dlb

.,= ICL7652

!:i Chopper-Stabilized Low-Noise
g Operational Amplifier
GENERAL DESCRIPTION

FEATURES

The ICL7652 chopper-stabilized amplifier offers exceptionally low input offset voltage and is extremely stable with
respect to time and temperature. It is similar to INTERSIL's
ICL7650 but offers improved noise performance and a wider
common-mode input voltage range. The bandwidth and
slew rate are reduced slightly.
INTERSIL's unique CMOS chopper-stabilized amplifier
circuitry is user-transparent, virtually eliminating the traditional chopper amplifier problems of intermodulation effects, chopping spikes, and overrange lock-up.
The chopper amplifier achieves its low offset by comparing the inverting and non-inverting input voltages in a nulling
amplifier, nulled by alternate clock phases. Two external capacitors are required to store the correcting potentials on
the two amplifier nulling inputs; these are the only external
components necessary.
The clock oscillator and all the other control circuitry is
entirely self-contained, however the 14-pin version includes
a provision for the use of an external clock, if required for a
particular application. In addition, the ICL7652 is internally
compensated for unity-gain operation.
An enhanced direct replacement for this part called
ICL7652S will become available shortly and will be more
appropriate for new designs.

• Extremely Low Input Offset Voltage -10,..v Over
Temperature Range
• Ultra Low Long-Term and Temperature Drifts of
Input Offset Voltage (150nV/Month, 100nVrC)
• Low DC Input Bias Current - 15pA
• Extremely High Gain, CMRR and PSRR - Min 110dB
• Low Input Noise Voltage - 0.2,.. Vp-p (DC - 1Hz)
• Internally Compensated for Unity-Gain Operation
• Very Low Intermodulation Effects (Open-Loop Phase
Shlft<2'@ Chopper Frequency)
• Clamp Circuit to Avoid Overload Recovery Problems
and Allow Comparator Use
• Extremely Low Chopping Spikes at Input and Output

ORD,ERING INFORMATION
Part Number

Temperature Range

Package

ICL7652CPD

O'Cto +70'C

14-pin plastic

ICL76521JD

- 25'C to + 85'C

14-pin CERDIP

ICL7652CTV

O'Cto +70'C

8-pinTO-99

ICL76521TV

- 25'C to + 85'C

8-pinTO-99

INTlm

CorA

EXT CLK II

ICIGUARDI
+INo-~--------------~
-INo-+-~------------~

>---1-t-o OUTPUT

-IN

INT CLKOUT
y.

+IN

OUTPUT

MClGUARDl

OUTPUT CLAMP

y- -..._ _ _ _....r-CII£I.
CLAMP

14 LEAD

(Outline dwg PD, JD)

.....----u-u--

EXTCLKIN

~A=CLKOUT
~A

~B
~C
0309-1

Figure 1: Functional Diagram
TO-99

(Outline dwg TV)

Figure 2: Pin Configuration

0309-2

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
302062-003
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

7-64

ICL7652
ABSOLUTE MAXIMUM RATINGS
TotaISupplyVoltage(V+ toV-) ................... 18V
Input Voltage .................. (V+ +0.3) to (V- -0.3)V
Voltage on Oscillator Control Pins ............. V+ to VDuration of Output Short Circuit ......•......... Indefinite
Current into Any Pin ............................. 10mA
- while operating (Note 4) ...................... 100,..,A

Continuous Total Power Dissipation (TA = 2S'C)
CERDIP Package ...•...•.....•........•.•.. SOOmW
Plastic Package ............................. 37SmW
TO-99 ..................................... 2S0mW
Storage Temperature Range •........... - SS'C to 1S0'C
Operating Temperature Range
ICL76S2C ............................ O'C to + 70'C
ICL76S21 .......................... -2S'Cto +8S'C
Lead Temperature (Soldering, 10sec) ............. 300'C

NOTE: Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the devics. These are stress fstings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections 01 the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
Test Conditions: V+ = +5V, V- = -SV, TA = +2S'C, Test Circuit (unless otherwise specified)
Symbol

Parameter

limits

Test Conditions
Min

VOS

Input Offset Voltage

tJ.VOS
tJ.T
tJ.VOS
tJ.T

Average Temperature Coefficient
of Input Offset Voltage

ISlAS

Input Bias Current
(Doubles every 10'C)

Max

TA= +25'C

±2

±5

Over Operating Temperature
Range (Note 1)

±10

Operating Temperature
Range (Note 1)

Offset Voltage vs Time

(Note 5)
los

Input Offset Current

RIN

Input Resistance

Units

Typ

0.1

fLV/'C

150

nV/month

TA= + 25'C

15

O'C..

~

33
111-1000
--r--i
o L-......L_..I-_.L.-......L_...I
BROADBAND NOISE

26

50
75 100 126
TEMPERATURE ("C)

>..

2

a

4

5

1

7

1

TIME (mol

150

1

2

341171
TlME(mt)

0309-10

0309-11

0309-9

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESI'ECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESB, IMPLIED OR STATUTORY, INCWDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESB FOR A PARTICULAR USE.
NOTE:AH typ/cIIIVBIu8shs.. b6sn _ b u t " , . .

not_

7-66

IIID~OIl.

ICL7652
Voltage Follower Large Signal
Pulse Response'
~

~

~

i

0

a

3 80

_,CLOCK
OUT

-1

f-

-

i:

-2 0

2

I

30

1,J.e I I

80

~ MARGIN-8O'

70

\

I '\.
.... -IOk

20

11

-3

'\.

~

z 100

\\
\ \H~G1

-2

~

.120

!LCJ:K
OUT
, - i\LOW

UI
N

Open-Loop Gain and Phase
Shift vs Frequency
140

....
2

1&1

...
GI

TYPICAL PERFORMANCE CHARACTERISTICS
Voltage Follower Large Signal
Pulse Response'

n
r-

I

o
0.1

4 8 8 10 12 14
TlME(,..)

10

1\\
'\.

110

~.

130
180

r'\.

II
:!I

!
~
JiJ

1 10 100 lk 10k lOOk 1M
FREQUENCY (l1li

0309-12

0309-14
0309-13

'The two different responses correspond to the two phases of the clock.

N-Channel Clamp Current vs
Output Voltage

P-Channel Clamp Current vs
Output Voltage

~

100,.A

8

!l
:5
()
iil

I

1pA

l00nA

l00nA

3
2

IU

10nA

lUnA

iii

1nA

z

iC l00pA
G 10pA
Z

Input Offset Voltage Change vs
SUpply Voltage

~100pA

~
...

lpA
0.8
0.6
U.4
0.2
OUTPUT YOLTAGE (aY·)

~

!

0

~

-1

~

1nA

10pA
lpA
-1.0 -0.8 -0.6 -0.4 -0.2
OUTPUT YOLTAGE «lY')
0309-16

0309-15

'"

~

~~

......

~

~

... -2

o

~
z
-

-3

48810121416
TOTAL SUPPLY VOLTAGE (V)
0309-17

.--~~~

the input to the output. The nulling amplifier, under the control of the chopping frequency oscillator and clock circuit,
alternately nulls itself and the main amplifier. The nulling
connections, which are MOSFET gates, are inherently highimpedance, and two external capacitors provide the required storage of the nulling potentials and the necessary
nulling-loop time constants. The nulling arrangement operates over the full common-mode and power supply ranges,
and is also independent of the output level, thus giving exceptionally high CMRR, PSRR, and AVOL .
Careful balancing of the input switches, together with the
inherent balance of the input circuit, minimizes chopper frequency charge injection at the input terminals. Feedforwardtype injection into the compensation capacitor is also minimized, which is the main cause of output spikes in this type
of circuit.

OUTPUT

Intermodulation

0309-18

Figure 3: Test Circuit

Previous chopper-stabilized amplifiers have suffered from
intermodulation effects between the chopper frequency and
input signals. These arise because the finite AC gain of the
amplifier necessitates a small AC signal at the input. This is
seen by the zeroing circuit as an error Signal, which is
chopped and fed back, thus injecting sum and difference
frequencies and causing disturbances to the gain and

DETAILED DESCRIPTION
The Functional Diagram (Figure 1) shows the major elements of the ICL7652. There are two amplifiers, the main
amplifier, and the nulling amplifier. Both have offset-null capability. The main amplifier is connected continuously from

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but aM not tested

7-67

•

(\I
II)
U)

ICL7652

U_..I

phase vs frequency characteristics near the chopping frequency. These effects are substantially reduced in the
ICL7652 by feeding the nulling circuit with a dynamic current, corresponding to the compensation capacitor current,
in such a way as to cancel that portion of the input signal
due to finite AC gain. Since that is the major error contribution to the ICL7652, the intermodulation and gain/phase
disturbances are held to very low values, and can generally
be ignored.

noise is desired. For limited bandwidth applications where
clock ripple is filtered out, using a 0.1 fLF capacitor results in
slightly lower offset voltage. A high-quality film-type capacitor such as mylar is preferred, although a ceramic or other
lower-grade capaCitor may prove suitable in many applications. For quickest settling on initial turn-on, low dielectric
absorption capaCitors (such as polypropylene) should be
used. With ceramic capaCitors, several seconds may be required to settle to 1fLY.

Capacitor Connection

Static Protection

The null-storage capacitors should be connected to the
CEXTA and CEXTB pins, with a common connection to the
CRETN pin. This connection should be made directly by either a separate wire or PC trace to avoid injecting load current IR drops into the capacitive circuitry. The outside foil,
where available, should be connected to CRETN.

All device pins are static-protected by the use of input
diodes. However, strong static fields and discharges should
be avoided, as they can cause degraded diode junction
characteristics which may result in increased input-leakage
currents.

Output Clamp

Junction-isolated CMOS circuits inherently include a parasitic 4-layer (p-n-p-n) structure which has characteristics
similar to an SCR. Under certain circumstances this junction
may be trigerred into a low-impedance state, resulting in
excessive supply current. To avoid this condition no voltage
greater than 0.3V beyond the supply rails should be applied
to any pin. In general, the amplifier supplies must be established either at the same time or before any input Signals
are applied. If this is not possible, the drive circuits must
limit input current flow to under 1mA to avoid latchup, even
under fault conditions.

...

Latchup Avoidance

The OUTPUT CLAMP pin allows reduction of the overload recovery time inherent with chopper-stabilized amplifiers. When tied to the inverting input pin, or summing junction, a current path between this point and the OUTPUT pin
occurs just before the device output saturates. Thus uncontrolled differential input voltages are avoided, together with
the consequent charge build-up on the correction-storage
capacitors. The output swing is slightly reduced.

Clock
The ICL7652 has an internal oscillator, giving a chopping
frequency of 400Hz, available at the CLOCK OUT pin on the
14-pin devices. Provision has also been made for the use of
an external clock in these parts. The INT /EXT pin has an
internal pull-up and may be left open for normal operation,
but to utilize an external clock this pin must be tied to V - to
disable the internal clock. The external clock signal may
then be applied to the EXT CLOCK IN pin. An internal divide-by-two provides the desired 50% input switching duty
cycle. Since the capacitors are charged only when EXT
CLOCK IN is high, a 50% - 80% positive duty cycle is recommended, especially for higher frequencies. The external
clock can swing between V + and V -. The logic threshold
will be at about 2.5V below V+. Note also that a signal of
about 800Hz, with a 70% duty cycle, will be present at the
EXT CLOCK IN pin with INT/EXT high or open. This is the
internal clock Signal before being fed to the divider.
In those applications where a strobe signal is available,
an alternate approach to avoid capacitor misbalancing during overload can be used. If a strobe signal is connected to
EXT CLK IN so that it is low during the time that the overload signal is applied to the amplifier, neither capacitor will
be charged. Since the leakage at the capacitor pins is quite
low at room temperature, the typical amplifier will drift less
than tOfLV/sec, and relatively long measurements can be
made with little change in offset.

Output Stage/Load Driving
The output circuit is a high-impedance type (approximately 18kfl), and therefore, with loads less than this the chopper amplifier behaves in some ways like a transconductance amplifier whose open-loop gain is proportional to load
resistance. For example, the open-loop gain will be 17dB
lower with a 1kfl load than with a 10kfl load. If the amplifier
is used strictly for DC, this lower gain is of little consequence, since the DC gain is typically greater than 120dB
even with a 1kfl load. However, for wideband applications,
the best frequency response will be achieved with a load
resistor of 10kfl or higher. This will result in a smooth 6dB/
octave response from 0.1 Hz to 2MHz, with phase shifts of
less than 2° in the transition region where the main amplifier
takes over from the null amplifier.

Thermo-Electric Effects
The ultimate limitations to ultra-high precision DC amplifiers are the thermo-electric or Peltier effects arising in thermo-couple junctions of dissimilar metals, alloys, silicon, etc.
Unless all junctions are at the same temperature, thermoelectric voltages typically around 0.1 fL V
but up to tens
of fLvrc for some materials, will be generated. In order to
realize the extremely low offset voltages that the chopper
amplifier can provide, it is essential to take special precautions to avoid temperature gradients. All components
should be enclosed to eliminate air movement, especially
that caused by power-dissipating elements in the system.
Low thermoelectric-coefficient connections should be used
where possible and power supply voltages and power dissipation should be kept to a minimum. High-impedance loads
are preferable, and good separation from surrounding heatdissipating elements is advisable.

rc,

BRIEF APPLICATION NOTES
Component Selection
The required capacitors, CEXTA and CEXTB, are normally
in the range of O.lfLF to 1.0fLF. A 1.0fLF capaCitor should be
used in broad bandwidth circuits if minimum clock ripple

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

7-68

ICL7652
Guarding

PIN COMPATIBILITY

Extra care must be taken in the assembly of printed circuit boards to take full advantage of the low input currents
of the ICL7652. Boards must be thoroughly cleaned with
TCE or alcohol and blown dry with compressed air. After
cleaning, the boards should be coated with epoxy or silicone rubber to prevent contamination.
Even with properly cleaned and coated boards, leakage
currents may cause trouble, particularly since the input pins
are adjacent to pins that are at supply potentials. This leakage can be significantly reduced by' using guarding to lower
the voltage difference between the inputs and adjacent
metal runs. Input guarding of the 8 lead TO-99 package is
accomplished by using a 10 lead pin circle, with the leads of
the device formed so that the holes adjacent to the inputs
are empty when it is inserted in the board. The guard, which
is a conductive ring surrounding the inputs, is connected to
a low-impedance point that is at approximately the same
voltage as the inputs. Leakage currents from high-voltage
pins are then absorbed by the guard.
The pin configuration of the 14-pin dual-in-line package is
designed to facilitate guarding, since the pins adjacent to
the inputs are not used (this is different from the standard
741 and 101 A pin configuration, but corresponds to that of
the LM108).

The basic pinout of the 8-pin device corresponds, where
possible, to that of the industry-standard 8-pin devices, the
LM741, LM 101, etc. The null-storing external capacitors are
connected to pins 1 and 8, which are usually used for offset-null or compensation capaCitors. In the case of the OP05 and OP-07 devices, the replacement of the offset-null
pot, connected between pins 1 and 8 and V+, by two capacitors from those pins to pin 5, will provide easy compatibility. As for the LM108, replacement of the compensation
capacitor between pins 1 and 8 by the two capacitors to pin
5 is all that is necessary. The same operation, with the removal of any connection to pin 5, will suffice for the LM101,
,...A748, and similar parts.
The 14-pin device pinout corresponds most closely to
that .of the LM108 device, owing to the provision of "NC"
pins for guarding between the input and all other pins. Since
this device does not use any of the extra pins, and has no
provision for Offset-nulling, but requires a compensation capacitor, some changes will be required in layout to convert
to the ICL7652.

INPUT

o--"J'I'v-......--....JWI.----....,

OUTPUT

OUTPUT
INPUTo-++~

0309-20

0309-19

Follower

Inverting Amplifier

EXTERNAL
CAPACITORS

v+

~7

OUTPUT .....

()
81

.5~

EXTERNAL . .4 3 ,
CAPACITORS,
......
CRETN v...
GUARD

OUTPUT

~

i'

~

0309-22

Bottom View
Board Layout for Input Guarding
With TO-99 Package

0309-21

Should be low impedance for optimum guarding

Non-Inverting Amplifier

Figure 4: Connection of Input Guards
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AI/typical values haYS been oharacterized but are not tested.

7-69

•

:: ICL7652

,..o

~ TYPICAL APPLICATIONS
+7.5\/

OUT
INPUT
OUTPUT'

O.1pF

10k
0309-25

Figure 7: Using 741 to Boost Output
Drive Capability

R3+(R,IIR21~1001tO

FOR FULL CLAMP EFFECT

Figure 8 shows the use of the clamp circuit to advantage
in a zero-offset comparator. The usual problems in using a
chopper-stabilized amplifier in this application are avoided,
since the clamp circuit forces the inverting input to follow
the input signal. The threshold input must tolerate the output clamp current:::: VIN/R without disturbing other portions
of the system.

0309-23

Figure 5: Non-Inverting Amplifier
with (Optional) Clamp

INPUT

>-.JV'.>I\r-4--!
V,N

OUTPUT

O.1I'F

(R,IIR21.'00kO
FOR FULL CLAMP EFFECT

0309-24

0309-26

Figure 6: Inverting Amplifier
with (Optional) Clamp

Figure 8: Low Offset Comparator
It is possible to use the ICl7652 to offset-null such high
slew ra\e and bandwidth amplifiers as the HA2500 and
HA2600 series, as shown in Figure 9. The same basic idea
can be used with low-noise bipolar devices, such as the OP05, and also with the ICL8048 logarithmic amplifier, to
achieve a voltage-input dynamic range of close to 6 decades. Note that these circuits will also have their DC gains,
CMRR and PSRR enhanced. More details on these and
other ideas are explained in application note A053.
Mixing the ICL7652 with circuits operating at ± 15V supplies requires the provision of a lower voltage. Although this
can be done fairly easily, a highly efficient voltage divider
can be built using the ICl7660 voltage converter circuit
"backwards". A suitable connection is shown in Figure 10.

Clearly the applications of the ICL7652 will mirror those of
other op-amps. Thus, anywhere that the performance of a
circuit can be significantly improved by a reduction of inputoffset voltage and bias current, the ICL7652 is the logical
choice. Basic non-inverting and inverting amplifier circuits
are shown in Figures 5 and 6. Both circuits can use the
output clamping circuit to enhance the overload recovery
performance. The only limitations on the replacement of
other op-amps by the ICL7652 are the supply voltage (± 8V
max) and the output drive capability (10kO load for full
swing). Even these limitations can be overcome using a
simple booster circuit, as shown in Figure 7, to enable the
full output capabilities of the LM741 (or any other standard
device) to be combined with the input capabilities of the
ICL7652. The pair form a composite device, so loop gain
stability, when the feedback network is added, should be
watched carefully.

tNTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PROOUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTe: All typical values have been charactBfized but are not tested.

7-70

ICL7652
TYPICAL APPLICATIONS

(Continued)

OUT

0309-27
HA25001 10/20
HA2600/20
OR SIMILAR DEVICE

Figure 9: HA2500 or HA2600 Offset-Nulled
by ICL7652

t---<+15V
ICL7680

•

r---+-++ 7.5V
10"F

t--+-+ov

0309-28

Figure 10: SpliHing + 15V with ICL7660
at >95% efficiency. Same for -15V

For further applications assistance, see A053 and R017

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN typical valuss have been characterized but 8f9 not test9d.

7·71

=ICL7852S

! Super Chopper-Stabilized Lows!

D~DIL

Noise Operational Amplifier

GENERAL DESCRIPTION

FEATURES

The ICL7652S Super Chopper-Stabilized Low-Noise Amplifier offers exceptionally low input offset voltage and is
extremely stable with respect to time and temperature. It is
a direct replacement for the industry-standard ICL7652 offering ImproVlld input offset voltage, /ower input offset
voltage temperature coefficient, reduCfld input bias current,
wIdtI common mode voltage range, and ESD protection
greater than 2000 volts. All improvements are highlighted in
bold Itsllcs in the Electrical Characteristics Section. CritIcsl psrsmeters are guarsntHd over Mil IInt/", commtll"Clal, Industrlsl, lind military tempersturs rsll(Jfl.
Intersil's unique CMOS chopper-stabilized amplifier circuitry is user-transparent, virtually eliminating the traditional
chopper amplifier problems of intermodulation effects,
chopping spikes, and overrange lock-up.
The chopper amplifier achieves its low offset by comparing the inverting and non-inverting input voltages in a nulling
amplifier, nulled by alternate clock phases. Two external capacitors are required to store the correcting potentials on
the two amplifier nulling inputs; these are the only external
components necessary.
The clock oscillator and all the other control circuitry is
entirely self-contained, however the 14-lead version includes a provision for the use of an external clock, if required for a particular application. In addition, the ICL7652S
is internally compensated for unity-gain operation.

• GuarsntHd Max Input Otfset Voltage for All
Temperature Ranges
• Low Long-Term and Temperature Drifts of Input
Offset Voltage
• Reduced Input Bias Current-3 pA TyPi 30 pA Max
over Temperature
• Enhanced ESD Protection > 2000V
• Extrsmtlly Wide Common Mode Voltage Rang_
+ 3.5 to - 4.3 Volts
• Reduced Supply Current-1.7 mA; 3.5 mA MIIX over
mil Temperature
• GuarsntHd Minimum Output Source/Sink Current
• Extremely High Gain -150 dB
• Low Input Noise Voltag-o.2 ,..Vp-p (DC-1 Hz)
• Unlty-Galn Compensated
• Very Low Intermodulatlon Effects (Open-Loop Phase
Shift < 2",.. @ Chopper Frequency)
• Clamp Circuit to Avoid Overload Recovery Problems
and Allow Comparator Use (14-Lead only)
• Extremely Low Chopping Spikes at Input and Output
• Characterized Fully Over Military Temperature Range
• ImproVlld Direct Replacement for Industry-Standard
IC7652 and other Second-Source Parts

ORDERING INFORMATION
Part

Temperature
Range

ICL7652SCPD

O"Cto +70"C

Package
14-Pin Plastic

ICL7652SCJD

14-Pin CERDIP

ICL7652SCTV

8-PinTO-99

ICL7652SIJD

- 25·C to + 85·C

14-Pin Plastic

ICL7652SIPD
ICL7652SMJD

14-Pin CERDIP
8-PinTO-99

ICL7652SITV

- 55·C to + 125·C

14-Pin CERDIP
8-PinTO-99

ICL7652SMTV

INTERSlL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT BlATED IN THE WARRANTY ARTICLE OF THE CONDmoN OF BALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCWDING THE IMPLIEQ WARRANTIES OF
MERCHANTABILITY AND FlTNESB FOR A PARTICULAR USE.
.
302162-002
NOTE:A6 typ/cBJ1IIJiuBs".",besn _but"",nottsstod.

7-72

.D~OIl.

ICL7652S
ABSOLUTE MAXIMUM RATINGS

P
....
o
en
01

Total SupplyYoltage (Y+ to V-I .................... 18Y
Input Yoltage .................. (V+ + 0.3) to (Y- - 0.3)
Yoltage on Oscillator Control Pins .............. Y+ to YDuration of Output Short Circuit ................. Indefinite
Current into Any Pin ............................. 10 rnA
-While Operating (Note 1) ...................... 100 /LA
Continuous Total Power Dissipation (TA = 25'C)
CERDIP Package ............................ 500 mW
Plastic Package ............................. 375 mW
TO-99 ...................................... 250 mW

Storage Temperature Range ........... - 55'C to + 150'C
lead Temperature (Soldering. 10 sec) ............ + 300'C
Operating Temperature Range
ICl7652SC ............................ O'C to + 70'C
ICl7652S1 .......................... - 25'C to + 85'C
ICl7652SM ........................ -55'C to + 125'C
NOTE:

I\)

Stresses above those listed under "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
Test Conditions: Y+ = +5Y. Y- = -5Y. TA = + 25'C. Test Circuit as in Figure 3 (unless otherwise specified)
Symbol

Parameter

limits

Test Conditions
Min

Vos

Input Offset Voltage

AYos/At

Change in Input Offset
with Time

Iblas

Input BIas Current
11(+)1.11(-)1

±0.7

±5

±2

±7

-25'C"; TA"; +85'C

±3

± 10

± 15

±50

O'C,,; TA"; +70'C

0.01

0.06

-25'C"; TA"; +85'C

0.02

0.07

-55'C,,; TA"; +85'C

0.02

0.07

-85'C';; TA';; +125'C

0.4

1.0

-55'C,,; TA"; +125'C

0.1

0.4

3

TA = 25'C

Input Offset Current
11(-)-1(+)1

Input Resistance

A VOL

Large Signal Voltage Gain
(Note 2)

30

-25'C';; TA ,,; +85'C

30

-55'C"; TA"; +85'C

30
15

Output Yoltage Swing (Note 3)

40

O'C,;; TA"; +70'C

40

-25'C"; TA"; +85'C

40

-55'C,;; TA';; +85'C

40

135

O'C,,; TA"; +70'C

130

-25'C';; TA';; +85'C

130

Rl= 10K!!
Rl = 100K!!

pA

75
10 12

-55'C ,;; TA ,;; + 125'C
YOUT

pA

500

TA = 25'C

Rl = 10 K!!. Yo = ±4Y. TA = 25'C

/LyrC

30

O'C,;; TA';; +70'C

+85'C,;; TA"; +125'C
RIN

/LY

nYNmonth

150

+ 85'C ,,; TA"; +125'C

los

Units
Max

O'C,,; TA"; +70'C

TA = +25'C

-55'C"; TA"; +125'C

AVos/AT Average Temp. Coefficient
of Input Offset Voltage (Note 2)

Typ

!!

150
dB

120
±4.7

±4.85

Y

±4.95

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values hSV9 been chsracterized but (lf9 not teatscl.

7-73

•

=ICL7852S
10

...

CD

~

ELECTRICAL CHARACTERISTICS
Test Conditions: V+ = + 5V, V- = - 5V, TA = + 25"C, Test Circuit (unless otherwise specified)(Continued)

CMRR

Commtlll Mode Rejection R6t1o
(Note 2)

CMVR = -4.3Vto +3.5, TA = 25"C
O"C:s; TA:S; +70"C
-25"C:S; TA:S; +85"C
-55"C:s; TA:S; +125"C

PSRR

Power SUpply Rejection R6t1o
(Note 2)

V+, V- = ±3Vto ±8V
O"C:S; TA:S; +70"C
-25"C:s; TA :s; +85"C
-55"C:s; TA :s; + 125"C

en

Input Noise Voltage

in

Input Noise Current

GBW

GIIIn Bilndwldth

SR

S/eWR6"

Limits

Test Conditions

Parameter

Symbol

Min

Typ

120
110
110
100
120
110
110
100

130

Operating Supply Range

Isupp

SUpply Curnmt

130
dB

0.2

f=OCto10Hz

0.7

f = 10 Hz

0.01

kHz

1.0

VI",s

5.0

1.7

No Load TA = 25"C

< TA < 70"C
< TA < 85"C
-55"C < TA < 125"C

10 sink

ft:h

2.4

4.4

O"C

< TA < 70"C
< TA < 85"C
-55"C < TA < 125"C

2.0
1.9

TA = 25"C

15.0

< TA < 70"C
-25"C < TA < 85"C
-55"C < TA < 125"C

12.0
12.0

Inttlrnlll ChoppIng Freqwncy

Pins 12 & 14 Open (dip)

250

450

CItImp ON Cummt (Note 4)

RL = 100 KO, TA = 25"C

3D

100

CItImp OFF Cummt (Note 4)

-4.0V

< VoUT <

rnA

3.5

TA = 25"C

O"C

V

2.5

3.0
3.0

-25"C
Output Sink Current

%

16

O"C

10 source

pAl~

500

-25"C

Output Source Current

",Vp-p

15

Overshoot
V+ toV-

dB

Rs = 1000, f = OCto 1 Hz

CL = 50 pF, RL = 10 KO

Units
Max

rnA

1.7
20.0

rnA

11.0

+4.0V, TA = 25"C

O"C:S; TA :s; +70"C
-25"C:s; TA:S; +85"C
-55"C:s; TA:S; +125"C

D.001

650

Hz

p.A

10
10
10
10

nA

NOTE 1: Umiting Inpol current to 100 p.A Is recommended to avoid latchup problems. Typically 1 mA is safe. however this Is not guaranteed.
2: Thasa parameters are guaranteed by design and characterization. but not tested at temperatura extremes beceuse thermocouple effects prevent precise
measurement of these voltages In eutometic test equipment.
3: OUTPUT CLAMP not connected. Sse typical characterlslic curves for oulpol swing VB clamp current characteristics.

4: Sse OUTPUT CLAMP under detailed descliption.

5: All significant improvements over the Industry-standard ICL7652 are highlighted in bold ItIIIIta
INTERSlL'S SOLE AND EXcLUSIVE WARRANTY OBLIGATION WITH RESPECT TO TlHIS PRODUCT SHALL BE TlHAT STATED IN TlHE WARRANTY ARTICLE OF THE OONDITION OF SALE.
TlHE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING TlHE IMPUED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.
NOTE: AI1 typIcsI _ _ _ _ buJM8notlNlSd.

7-74

ICL7652S

EXTI:~:::--Cl:: !

CEXTS

CLKOUT~C

CmA

>---iH-o OUTPUT

-INo-+-~------------~

INT ClK OUT

NC(GUARD)

INTER:'~-I

+INo-~---------------i

-IN

Vt

tiN

OUTPUT

NC(GUARD)

OUTPUT CLAIIP

V-

CRETN

CLAMP

14- PIN DIP
(PD,JD)

T
~EXTCLKIN

~A-CLKOUT
~A

~8

8 lEAD TO 99
(TV)

-J""""""l.- C

0087-2

Figure 2: Pin Configuration

0087-1

Figure 1: Functional Diagram

TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Supply Voltage

Supply Current vs Ambient
Temperature

Maximum Output Current vs
Supply Voltage

3

I

1

-

v
./'

-

r-

o

o

-50 -25

4

10

12

14

16

0

25

50

""

--

r--

....... .....

75 100 125

'--

,...-,--.--r-,-.,.....,...."T"'"""'l

- r--

r-- r--

TOTAL SUPPLY VOLTAGE (V)

0087-4

0087-3

8

.-t-- I--

48810121418

AIIBIENT TEMPERATURE (CC)

TOTAL SUPPLY VOLTAGE (V)

Common-Mode Input Voltage
Range vs Supply Voltage

--

......-

0087-5

Input Offset Voltage vs
Chopping Frequency
10

5

It

7 1-1-1-+-+-+--I,--iMI

10 Hz Pop Noise Voltage vs
Chopping Frequency

8I--HH--I----!.
5 I--+-+--+--+
4hHH

1111111

3H-t......,~

80%

21--+--+-+-+-+--+---i---l
11--+--+--+--+-+--+---i---l
OL..-L..-L..-L..-L..-L..-.L....L...J
012345878
EACH SUPPLY VOLTAGE (+AND-)

1111

o

70%

o

80%

10
100
1k
10k
CHOPPINO FREQUENCY (CLOCK OUT)
% parameter Is EXT eLK in duly cycle

10
100
lk
10k
CHOPPINO FREQUENCY (CLOCK OUT)
0087-8

0087-6

0087-7

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUOING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bflen characterized but 8I'B not tested.

7-75

•

=ICL7652S
10
G

...

g TYPICAL PERFORMANCE CHARACTERISTICS

(Continued)

Broadband Noise Balanced
Source Impedance = 1 kO
Gain = 1000 CEXT = 1.0 p.F

Broadband Noise Balanced
Source Impedance = 1 kO
Gain = 1000 CEXT = 0.1 p.F

Clock Ripple Referred to the
Input vs Temperature
1000

s;

CaT" o.l~F-j

~100

i

Y

a: 10

!t

.J'I
CEXT·l~F

BROADBAND NOISE ~

2345178

""-1000

o
25

1234187.

TlME(ms)

50
75 100 125
TEMPERATURE ("C)

150

TlME(mo)
0087-10

0087-11

0087-9

Voltage Follower Large Signal
PulBe Response·

s:

2

2

1

i:i

~

i

0

a

~ .....

Cl.OCK

=1.

~

11

-- ~~K -

I-

Ii

-

8 -2 1
-3
-2 0

I
I

2

2

'"

HIGH

-1

Voltage Follower Large Signal
Pulse Response·

--

0
-1

8 -2
-2 0

!

\.

OUT

~LOW

,

\ l-~LOCK
OUT

\

2

~~IB~
6

~

Ip~Elr
MARGIN-8O'

\

~T

T \.

I- -

R.-1Ok

11
4

I

\.

!JK

-3

4 1 8 10 12 14
TIME",,)

Open-Loop Gain and Phase
Shift vs Frequency

I

o

0.1

8 10 12 14

1

\.

~

~

10 100 lk 10k lOOk 1M
FREQUEHCY (Hz)

TlME(,..)

I.

0087-14

0087-12
0087-13

'THE TWO DIFFERENT RESPONSES CORRESPOND TO THE TWO PHASES OF THE CLOCK.

Ii

100,..\

III

lo,.A

Ii

G
iii

t

5
:i:

~

100,..\

III

CI

~

1~

~l00nA

~100nA

:su

Input Offset Voltage Change vs
Supply Voltage

P-Channel Clamp Current vs
Output Voltage

N-Channel Clamp Current vs
Output Voltage

10nA

~

1nA

iii
z

10nA
lnA

:z:

10pA
1pA

:i
0.8
0.8
U.4
0.2
OUTPUT VOLTAGE (AV-)

~

~

0

Iii

-1

g

~ l00pA

100pA

2

III

10pA
lpA
-1.0 -0.8 -0.6 -0.4 -0.2
OUTPUT VOLTAGE (AV')

~

J:I;

'"'""

~

~

""" ~

1/1

0

0087-16

t:

-2

5

-3

o

~
-

4

8
8 10 12 14 16
TOTAL SUPPLY VOLTAGE (V)
0087-17

INTERSI.·S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT BTATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SAUE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typJcsJ VII/ues hBve bsBn charscterlzed but arB not 18Stsd.

7·76

ICL7652S
Output Clamp
The OUTPUT CLAMP pin allows reduction of the overload recovery time inherent with chopper-stabilized amplifiers. When tied to the inverting input pin, or summing junction, a current path between this point and the OUTPUT pin
occurs just before the device output saturates. Thus uncontrolled differential input voltages are avoided, together with
the consequent charge build-up on the correction-storage
capacitors. The output swing is slightly reduced.

Clock
0087-18

The ICl7652S has an internal oscillator, giving a chopping frequency of 400 Hz, available at the CLOCK OUT pin
on the 14-pin devices. Provision has also been made for the
use of an external clock in these parts. The INT /EXT pin
has an internal pull-up and may be left open for normal operation but to utilize an external clock this pin must be tied
to V - to disable the internal clock. The external clock Signal
may then be applied to the EXT CLOCK IN pin. An internal
divide-by-two provides the desired 50% input switching duty
cycle. Since the capacitors are charged only when EXT
CLOCK IN is high, a 50%-80% positive duty cycle is recommended, especially for higher frequencies. The external
clock can swing between V+ and V-. The logic threshold
will be at about 2.5V below V+. Note also that a Signal of
about 800 Hz, with a 70% duty cycle, will be present at the
EXT CLOCK IN pin with INT /EXT high or open. This is the
internal clock signal before being fed to the divider.
In those applications where a strobe Signal is available,
an alternate approach to avoid capacitor misbalancing during overload can be used. If a strobe signal is connected to
EXT ClK IN so that it is low during the time that the overload signal is applied to the amplifier, neith~r capac!tor ~iII
be charged. Since the leakage at the capacitor pinS IS qUite
low at room temperature, the typical amplifier will drift less
than 10 )J.V/sec, and relatively long measurements can be
made with little change in offset.

Figure 3: Test Circuit

DETAILED DESCRIPTION
The Functional Diagram (Figure 1) shows the major elements of the ICl7652S. There are two amplifiers, the main
amplifier, and the nulling amplifier. Both have offset-null capability. The main amplifier is connected continuously from
the input to the output. The nulling amplifier, under the control of the chopping frequency oscillator and clock circuit,
alternately nulls itself and the main amplifier. The nulling
connections, which are MOSFET gates, are inherently highimpedance, and two external capacitors provide the required storage of the nulling potentials and the necessary
nulling-loop time constants. The nulling arrangement operates over the full common-mode and power supply ranges,
and is also independent of the output level, thus giving exceptionally high CMRR, PSRR, and AVOL.
Careful balancing of the input switches, together with the
inherent balance of the input circuit, minimizes chopper frequency charge injection at the input terminals. Feedforwar~­
type injection into the compensation capaci~or i~ als? minimized, which is the main cause of output spikes In this type
of circuit.

Intermodulation
Previous chopper-stabilized amplifiers have suffered from
intermodulation effects between the chopper frequency and
input signals. These arise because the finite AC gain of the
amplifier necessitates a small AC signal at the input. This !s
seen by the zeroing circuit as an error signal, which IS
chopped and fed back, thus injecting sum and diff~rence
frequencies and causing disturbances to the ga.ln and
phase vs frequency characteristics near the chopping frequency. These effects are substantially reduced in the
ICl7652S by feeding the nulling circuit with a dynamic current, corresponding to the compensation capacitor current,
in such a way as to cancel that portion of the input signal
due to finite AC gain. Since that is the major error contribution to the ICl7652S, the intermodulation and gain/phase
disturbances are held to very low values, and can generally
be ignored.

BRIEF APPLICATION NOTES
Component Selection
The required capacitors, CEXTA and CEXTB, are normally
in the range of 0.1 )J.F to 1.0 )J.F. A 1.0 )J.F capacitor should
be used in broad bandwidth circuits if minimum clock ripple
noise is desired. For limited bandwidth applications where
clock ripple is filtered out, using a 0.1 )J.F capacitor results i~
slightly lower offset voltage. A high-quality film-type capacItor such as mylar is preferred, although a ceramic or other
lower-grade capacitor may prove suitable in many ~pplic~­
tions. For quickest setting on initial turn-on, low dlelectnc
absorption capacitors (such as polypropylene) should be
used. With ceramic capacitors, several seconds may be required to settle to 1 )J.v.

Static Protection

Capacitor Connection

All device pins are static-protected by the use of input
diodes. However, strong static fields and discharges should
be avoided, as they can cause degraded diode junction
characteristics which may result in increased input-leakage
currents.

The null-storage capacitors should be connected to the
CEXTA and CEXTB pins, with a common conn~ction to th~
CRETN pin. This connection should be made directly by either a separate wire or PC trace to avoid injecting I~ad cu~­
rent IR drops into the capacitive circuitry. The outside foil,
where available, should be connected to CRETN.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: Alllypical values have been characterized but are not tesiBd.

7-77

II

=ICL7652S

.D~OI!..

10
CO
....

~

Latchup Avoidance

Guarding

Junction-isolated CMOS circuits inherently include a parasitic 4-layer (p-n-p..n) structure which has characteristics
similar to an SCR. Under certain circumstances this junctidn
may be triggered Into a low-impedance state, resulting in
excessive supply current. To avoid this condition no voltage
greater than 0.3V beyond the supply rails should be applied
to ariy pin. In general, the amplifier supplies must be established either at the same time or before any input signals
are applied. If this is not possible, the drive circuits must
limit input current flow to under 1 mA to avoid latchup, even
under fault conditions.

Extra care must be taken in the assembly of printed circuit boards to take full advantage of the low input currents
of the ICL7652S. Boards must be thoroughly cleaned with
TCE or alcohol and blown dry with compressed air. After
cleaning, the boards should be coated with epoxy or sili·
cone rubber to prevent contamination.
Even with properly cleaned and coated boards, leakage
currents may cause trouble, particularly since the input pins
are adjacent to pins that are at supply potentials. This leak·
age can be significantly reduced by using guarding to lower
the voltage difference between the inputs and adjacent
metal runs. Input guarding of the 8 lead TO-99 package is
accomplished by using a 10 lead pin circle, with the leads of
the device formed so that the holes adjacent to the inputs
are empty when It is inserted in the board. The guard, which
is a conductive ring surrounding the inputs, is connected to
a low-impedance point that is at approximately the same
voltage as the inputs. Leakage currents from high-voltage
pins are then absorbed by the guard.
The pin configuration of the 14-pin dual-in-line package is
designed to facilitate guarding, since the pins adjacent to
the inputs are not used (thiS is different from the standard
741 and 10M pin configuration, but corresponds to that of
the LM108).

Output Stage/Load Driving
The output circuit is a high-Impedance type (approximately 18 kG), and therefore, with loads less than this the chopper amplifier behaves in some ways like a transconductance amplifier whose open-loop gain is proportional to load
resistance. For example, the open-loop gain will be 17 dB
lower with a 1 kG load than with a 10 kG load. If the amplifier is used strictly for DC, this lower gain is of little consequence, since the DC gain is typically greater than 120 dB
even with a 1 kG load. However, for wideband applications,
the best frequency response will be achieved with a load
resistor of 10 kG or higher. This will result in a smooth
6 dB/octave response from 0.1 Hz to 2 MHz, with phase
shifts of less than 2° in the transition region where the main
amplifier takes over from the null amplifier.

PIN COMPATIBILITY
The basic pinout of the 8-pin device corresponds, where
pOSSible, to that of the industry-standard 8-pin devices, the
LM741, LM101, etc. The null-storing external capacitors are
connected to pins 1 and 8, which are usually used for offset-null or compensation capacitors. In the case of the
OP-05 and OP-07 devices, the replacement of the offsetnull pot, connected between pins 1 and 8 and V+, by two
capacitors from those pins to pin 5, will provide easy compatibility. As for the LM10B, replacement of the compensation capacitor between pins 1 and 8 by the two capacitors to
pin 5 is all that is necessary. The same operation, with the
removal of any connection to pin 5, will suffice for the
LM101, p.A 748, and similar parts.
The 14-pin device pinout corresponds most closely to
that of the LM108 device, owing to the provision of "NC"
pins for guarding between the input and all other pins. Since
this device does not use any of the extra pins, and has no
provision for offset-nulling, but requires a compensation capaCitor, some changes will be required in layout to convert
to the ICL7652S.

Thermo-Electric Effects
The ultimate limitations to ultra-high precision DC amplifiers
are the thermo-electric or Peltier effects ariSing in thermocouple junctions of dissimilar metals, alloys, silicon etc. Unless all junctions are at the same temperature, thermo-electric voltages typically around 0.1 p.V/"C, but up to tens of
p.V/"C for some materials, will be generated. In order to
realize the extremely low offset voltages that the chopper
amplifier can provide, it is essential to take special precautions to avoid temperature gradients. All components
should be enclosed to eliminate air movement, especially
that caused by power-dissipating elements in the system.
Low thermoelectrlc-coefficient connections should be used
where possible and power supply voltages and power dissipation should be kept to a minimum. High-Impedance loads
are preferable, and good separation from surrounding heatdiSSipating elements Is advisable.

INTERSIL'S SOlE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHAlL BE EXCLUSIVE AND SHAlL BE IN UEU OF AlL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE:AHIyp/CIJIWlilMhfI.. _ _ buI.,.nct_

7-78

1II0~OI!:.

ICL7652S

P
...

..
ell

=

INPUT o-IIN~~---JV"""-..,
OUTPUT
OUTPUT

INPUT

0087-20

Follower

0087-19

Inverting Amplifier
R2

EXTERNAL
CAPACITORS

..,"~~~O

OUTPUT

CRETN .....

,

0087-21

V-

\~2~
~,s-"
GAURD

I

...
0087-22

Note: Rt R2
Rt +r2

BOTTOM VIEW

Board Layout for Input Guarding
with TO-99 Package

Should be low impedance for optimum guarding

Non-Inverting Amplifier

Figure 4: Connection of Input Guards

•

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical VSlU9S have been characterized but are not tested.

7·79

:I ICL7852S
lit
f&)

....

~

TYPICAL APPLICATIONS

.[

INPUT

OUT

OUTPUT

0087-25

Figure 7: Using 741 to Boost Output
Drive Capability
Figure 8 shows the use of the clamp circuit to advantage
in a zero-offset comparator. The usual problems in using a
chopper-stabilized amplifier in this application are avoided,
since the clamp circuit forces the inverting input to follow
the input signal. The threshold input must tolerate the output clamp current:::: VIN/R without disturbing other portions
of the system.
.

0087-23

R3 + (RlI1R2l ;;, 100 kG
For Full Clamp Effect

Figure 5: Non-Inverting Amplifier
with Optional Clamp
R2
INPUT ~JV\",,",~
OUTPUT

0087-24
0087-26

(RlI1R2l ;;, 100 kG
For Full Clamp Effect

Figure 8: Low Offset Comparator

Figure 6: Inverting Amplifier
with Optional Clamp

It is possible to use the ICL7652S to offset-null such high
slew rate and bandwidth amplifiers as the HA2500 and
HA2600 series, as shown in Figure 9. The same basic idea
can be used with low-noise bipolar devices, such as the OP05, and also with the ICLS048 logarithmic amplifier, to
achieve a voltage-input dynamic range of close to 6 decades. Note that these circuits will also have their DC gains,
CMRR and PSRR enhanced. More details on these and
other ideas are explained in application note A053.
Mixing the ICL7652S with circuits operating at ± 15V supplies requires the provision of a lower voltage. Although this
can be done fairly easily, a highly efficient voltage divider
can be built using the ICL7660S voltage converter circuit
"backwards". A suitable connection is shown in Figure 10.

Clearly the applications of the ICL7652S will mirror those
of other op-amps. Thus, anywhere that the performance of
a circuit can be significantly improved by a reduction of input-offset voltage and bias current, the ICL7652S is the logical choice. Basic non-inverting and inverting amplifier circuits are shown in Figures 5 and 6. Both circuits can use the
output clamping circuit to enhance the overload recovery
performance. The only limitations on the replacement of
other op-amps by the ICL7652S are the supply voltage
(±8V max) and the output drive capability (10 kG load for
full swing). Even these limitations can be overcome using a
simple booster circuit, as shown in Figure 7, to enable the
full output capabilities of the LM741 (or any other standard
device) to be combined with the input capabilities of the
ICL7652S. The pair form a composite device, so loop gain
stability, when the feedback network is added, should be
watched carefully.

.INTERSIL·S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AIItypics/._""volNHJn_butlll8notlllBlBd.

7-80

IfID~DI!..

ICL7652S
TYPICAL APPLICAT!ONS

n
I'"
....

CI
CII

(ContirJed)

N
fit

+15V

8

+7.5V

lOIolF
lOIolF

OV

0087-28

Figure 10: Splitting + 15V with ICL7660S
at > 95% Efficiency. Same for -15V

0087-27

HA2500/10/20
HA2600/20

or Similar Device

Figure 9: HA2500 or HA2600
Offset·Nulled by ICL7652S
FOR FURTHER APPLICATIONS ASSISTANCE, SEE A053
AND R017.

•

INTERSIL'S SOLE AND EXCLUSIVE WARRANTV OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTV ARTICLE OF THE CONDITION OF SALE.
THE WARRANTV SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILlTV AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typk;sl values have besn charact6rIz6d but IW not t6st6d.

7-81

S
o ICL8007
!I JFET Input Operational Amplifier
g

GENERAL DESCRIPTION

FEATURES

The Intersil ICLSOO? is a low input current JFET input
operational amplifier. The ICLSOO?A is selected for 4 pA
max input current.
The devices are designed for use in very high input impedance applications. Because of their high slew rate, high
common mode voltage range and absence of "latch-up",
they are ideal for use as a voltage follower.
The Intersil SOO? and SOO?A are short circuit protected.
They require no external components for frequency compensation because the internal 6 dB/roil-off insures stability
in closed loop applications. A unique bootstrap circuit insures unusually good common mode rejection for a JFET
input op-amp and prevents large input currents as seen in
some amplifiers at high common mode voltage.

•
•
•
•
•
•

Ultra Low Input Current
High Slew Rate - 6V1 /Ls
Wide Input Common Mode Voltage
1MHz Band Width
Excellent Stability
Ideal for Unity Gain Applications

ORDERING INFORMATION
Part
Number

Temperature
Range

ICLSOO?CTY
ICLSOO?ACTV

O'Cto +?O'C

ICLSOO?MTY
ICLSOO?AMTV

-55'Cto +125'C

Package
SLEAD
TO-99
METAL CAN

,-r-----t-----t"--....,-ov·

0310-2
ICLaDD? pin 4 connected to case (TV package)
ICLaD07A pin a connected to case (TV package)

Figure 2: Pin Configuration

0310-1

Figure 1: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values haV8 b88n characl8fizBd but 81'8 not tested.

?-S2

.D~DI!.

ICLa007

n
I'"
C»

ABSOLUTE MAXIMUM RATINGS
Supply Voltage .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 18V
Power Dissipation (Note 1) ..................... 500mW
Differential Input Voltage ........................ ±30V
Input Voltage (Note 2) ......................... .. ± 15V
Storage Temperature Range .......... -65'C to + 150'C

Operating Temperature Range
8007M,8007AM ............. -55'C to + 125'C
8007C, 8007 AC .................. O'C to + 70'C
Lead Temperature (Soldering, 10sec) ............. 300'C
Output Short-Circuit Duration (Note 3) .......... Indefinite

o
o....

NOTES:
1.
2.
3.
4.

Rating applies for case temperatures to 125'C; derate linearly at 6.5 mW I'C for ambient temperatures above + 75'C.
For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
Short circuit may be to ground or either supply. Rating applies to + 125'C case temperature or + 75'C ambient temperature.
For Design only, not 100% tested.

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the davies. These are stress ratings only and functionel
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extendad periods may affect davica reliability.

ELECTRICAL CHARACTERISTICS
Characteristics

(Vs = ± 15V unless otherwise specified)

Test Conditions

8007M
Min

8007AM &
8007AC

8007C

Typ

Max

10

20

Min

Typ

Max

20

50

Min

Units

Typ Max

The following specifications apply for TA = 25'C:
Input Offset Voltage

Rs';;100kO

Input Offset Current

0.5

Input Bias Current (either input)

2.0

Input Resistance

106

Input Capacitance
Large Signal Voltage Gain

15

0.5
3.0

20

50

0.5

106

mV
pA

4.0

106

2.0

2.0
RL:2:2kO, VOUT= ±10V 50,000

30

0.2

pA
MO

2.0

20,000

pF

20,000

VIV

Output Resistance

75

75

75

0

Output Short-Circuit Current

25

25

25

mA

Supply Current

3.4

5.2

3.4

6.0

Power Consumption

102

156

102

180

Slew Rate

6.0

6.0

3.4

6.0

102 180
2.5

mA
mW

6.0

V/",s

1.0

1.0

1.0

MHz

Risetime

CL,;;100pF, RL =2kO

300

300

300

ns

Overshoot

CL';;100pF, RL =2kO

10

10

10

%

Unity Gain Bandwidth

The following specifications apply for O'C,;;TA';; +70'C (8007C and 8007AC), and -55'C';;TA';; + 125'C (8007M and
8007AM):
Input Voltage Range
Common Mode Rejection Ratio

±10

±12

±10

±12

±10

±12

V

70

90

70

90

86

95

dB

Supply Voltage Rejection Ratio

70

Large Signal Voltage Gain
Output Voltage Swing

RL:2:10kO
RL:2:2kO

Input Bias Current (either input)

TA= + 125'C
TA= +70'C

±12
±10

70

300

25,000
±14
±13

±12
±10

15,000
±14
±13

±12
±10

2.0
50

Average Temperature Coefficient
of Input Offset Voltage
(Note 4)

75

70 200 ",VIV

600

15,000

75

VIV
±14
±13

V
V

1.0
30

nA
pA
50 ",VI'C

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical va/uss have been characterized but are not tssted.

7-83

•

~

o

ICL8007

CO

..I

g

r-----------~_1-------.vmrr

0310-3

Figure 3: Transient Response Test Circuit

TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

OPEN LOOP VOLTAGE GAIN

......
Z

~

10'

~SUPP· '15V

r\.
r\.

w 10'
;

g

-

T",-+25°C

"

101

I
I

10

10 100

,.

'\.

I

\

I

'I

INPUT

\

i\..

E40

VOUpp = ±15V _
TA=25'C

I

1\

OUTPUT VOLTAGE SWING AS A
FUNCTION OF FREQUENCY

124

OU~,J,.

!

~

10k lOOk 1M 10M

0123456789
TIME (.0)

FREOUENCY IHzl

0310-4

~~~.,! ='±~~~

TA = +25°C
RL = lOkO

32

i

o

lk

INPUT BIAS CURRENT AS A
FUNCTION OF TEMPERATURE

16

2

12

...

'"

o

1M

10M

0310-6

OUTPUT SWING AS A FUNCTION
OF SUPPLY VOLTAGE
20
T.· 2S"C
RL = 2kO

24
20

lOOk

0310-5

TRANSIENT RESPONSE

;;;

10k

FREOUENCY (Hz)

28

.§

1\

18

gO".

~ 103

I
I

a 10'

I

./

..

~
~

~

15

.

10

...~
...'"

0:

a:

Vs",qSV
T
~ RISE TIME .~25 C
_~~ R, ~2k!l
Cl ::: l00pF
10~.

~
z

L

10

'"

0

V

/

POSITIVE SWING

C>

/

AI"
/V
/'

/"

/ ' NEGATIVE SWING

N

o

1.0

1.5

2.0

2.5

:;

<
~

TIME (~s)

~

./

1

20

10

40

60

80

100

120

140

15

20

SUPPLY V(lTAGE "VI

TEMPERATURE lOCI
0310-9

0310-7
0310-8

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE ANO SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIeD OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been character/zed but are not tested.

7·84

.D~DIL

ICL8007

n
rCD

TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF SUPPLY VOLTAGE

(Continued)

INPUT VOLTAGE RANGE AS A
FUNCTION OF SUPPLY VOLTAGE

QUIESCENT SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

20

T•• 125 ,c

~

to

z
0(
a:

...

".......
0(

1/

15

POsITIVE/

0

V

I-l-I-

N"

10

/

VNEGATIVE

/ V

>

....

2

V

:>
~

0

15

.10

20

INPUT VOLTAGE NOISE AS A
FUNCTION OF FREQUENCY

6

10'

Vs' ,'5V
~

r- l- I'-

a:
a:

a>

--

....

~

...~

..."....
0
...>

10'

0(

-55

-15

25

65

105

20

0310-12

10'

r-.

'"5

100

lk

I
10k

lOOk

FREOUENCY (Hzl

TEMPERATURE ('CI

r:;

i

Rs' son

III
10

WIDEBAND NOISE AS A
FUNCTION OF SOURCE RESISTANCE

ooo

~ 10.0

Rs' 1 Mn

z

o

15

roo - ~C:':J':oo

i%

-

!r...

10

SUPPLY VOLTAGE I'VI

0310-11

0310-10

QUIESCENT SUPPLY CURRENT AS A
FUNCTION OF TEMPERATURE

1

5

sUPPL Y VOL TAGE I.VI

SUPf'LY VOLTAGE I'VI

0310-14

0310-13

i

u
0.1

100

~

kHz

./
~

-'
BANDWIDTH

= 0.1 Hz TO 1kHz

T
lk 10k lOOk 1M 10M 100M
SOURCE RESISTANCE (Il)
0310-15

For additional information, see Application Note A005.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicsl VB/ue$ haV8 been characl8rlzed but are not tested.

7-85

o
o
.....

:o ICL8021/ICL8023

3 Low Power Bipolar Operational

.

g Amplifier
(If

GENERAL DESCRIPTION
o
CC)

....
!:!

FEATURES

The IntersillCL8021 series are low power operational amplifiers specifically designed for applications requiring very
low standby power consumption over a wide range of supply Voltages. The electrical characteristics of the 8021 series can be tailored to a particular application by adjusting
an external resistor, RSET, which controls the quiescent current. This is advantageous because 10 can be made independent of the supply voltages: it can be set to an extremely low value where power is critical, or to a larger value for
high slew rate or wideband applications.
Other features of the 8021 series include low input current that remains constant with temperature, low noise, high
input impedance, internal compensation and pin-for-pin
compatibility with the 741.
The Intersil 8023 consists of three low power operational
amplifiers in a single 16-pin DIP. Each amplifier is identical
to an 8021 low power op amp, and has separate connections for adjusting its electrical characteristics by means of
an external resistor, RSET, which controls the quiescent current of that amplifier.

• Vos=3mV Max (Adjustable to Zero)
• ± 1.5V to ± 18V Power Supply Operation
• Power Consumption - 20",W @ ± 1V
• Input Bias Current - 30nA Max
• Internal Compensation
• Pin-For-Pin Compatible With 741
• Short Circuit Protected

ORDERING INFORMATION
ICL8021

C

TV

1

Package
TV - TQ.99 Metal Can
PA - 8·pin Minidip
JE - 16-pin CERDIP
PE - 16-pin Plastic DIP

8021 only
8023 only

Temperature
C - Commercial - (OOC to +7OOC)
M - Military - (-55OC to +125OC)
Basic Part Number
8021 - Single
8023 - Triple

Part
Number

Temperature
Range

ICL8021CJA
ICL8021CBA
ICL8021 CPA
ICL8021CTY
ICL8021MJA
ICL8021 MTY*

O'Cto 70'C
O'Cto 70'C
O'Cto 70'C
O'Cto 70'C
- 55'C to + 125'C
- 55'C to + 125'C

8
8
8
8
8
8

ICL8023CJE
ICL8023CPE
ICL8023MJE*

O'Ct070'C
O'Ct070'C
- 55'C to + 125'C

16 Lead CERDIP
16 Lead MINIDIP
16 Lead CERDIP

Package
Lead CERDIP
Lead S.O.I.C
Lead MINIDIP
Lead Metal Can
Lead CERDIP
Lead Metal Can

'Add 188313 to Part Number if 8836 processing is required.

0311-20

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE; All typical values have been charact9rized btJt are not tested.

7-86

ICL8021/ICL8023
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................. ± 18V
Differential Input Voltage (Note 1) ................ ± 15V
Common Mode Input Voltage (Note 1) ............ ± 15V
Output Short Circuit Duration .................. Indefinite
Power Dissipation (Note 2) ..................... 300mW

Operating Temperature Range
8021 M/8023M .................... - 55'C to + 125'C
8021 C/8023C ......................... O'C to + 70'C
Storage Temperature Range . . . . . . . . .. - 65'C to + 150'C
Lead Temperature (Soldering, 10sec) ........... +300'C

NOTE 1: For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
NOTE 2: Rating applies for case temperatures to

+ 125'C; derate linearly at 5.6 mW I'C

for ambient temperatures above

+ 95'C.

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress rstings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the speCifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliabt1ify.

R"

25 KO

v'

0311-1

Figure 1: Functional Diagram

10 SET

(outline dwg PAl

v-

(Outline dwg TY)

0311-3
0311-2

(outline dwg JE, PEl

0311-5

Figure 2: Pin Configurations
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

7-87

=
ICL8021/ICL8023
o

a......

y'

&II

o

CD

~

y'

0311-6

Figure 3: Voltage Offset Null Circuit

ELECTRICAL CHARACTERISTICS
Characteristics

(VSUPPLY= ±6V.IQ=301lA. unless otherwise specified.)
8021M

Test Conditions
Min

Typ

8021C
Max

Min

Typ

Units
Max

The following speclflcstlons apply for TA= 25°C:
Input Offset Voltage

RsS:100kO

Input Offset Current
Input Bias Current
Input Resistance
Input Voltage Range

VSUPPLY= ±15V

Common Mode Rejection Ratio

RsS:l0kO

2

3

2

6

0.5

7.5

0.7

10

nA

5

20

7

30

nA

3

10

3

10

±12

±13

±12

±13

V

70

80

70

80

dB

Supply Voltage Rejection Ratio

RsS:l0kO

30

Output Resistance

Open Loop

2

Output Voltage Swing

150

30

MO

150

/J-VIV

2

kO
V

RL~20kO.

VSUPPLY= ±15V

±12

±14

±12

±14

RL~10kO.

VSUPPLY= ±15V

± 11

±13

±11

±13

V

±13

mA

Output Short-Circuit Current
Power Consumption

mV

±13
360

Vour=O

Slew Rate (Unity Gain)
Unity Gain Bandwidth

RL = 20kO. VIN = 20mV

Transient Response (Unity Gain)
Risetime
Overshoot

RL =20kO. VIN=20mV

480

360

600

/J-W

0.16

0.16

V//J-s

270

270

kJiz

1.3
10

1.3
10

/J-s
%

-55°CS:TAS: + 125°C

O"CS:TAS: + 70"C

2.0

5.0

2.0

7.5

mV

Input Offset Current

1.0

11

1.5

15

nA

Input Bias Current

10

32

15

50

nA

Specifications Applicable over Temperature
Input Offset Voltage

Average Temperature
Coefficient of Input
Offset Voltage

RsS:l0kO

RSS:1 OkO

Average Temperature
Coefficient of Input
Offset Current

5

5

/J-VI"C

1.7

0.8

pAI"C

Large Signal Voltage Gain

RL =10kO

50

200

50

200

VlmV

Output Voltage Swing

RL~10kO

±10

±13

±10

±13

V

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY oaUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDiTlON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPUED OR STATUTORY, INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typical valu8s have bsBn charBct6rIztKJ but BfS not testsd.

7·88

.D~On..

ICL8021/ICL8023

n
r-

.
CD

o

QUIESCENT CURRENT ADJUSTMENT

N

QUIESCENT CURRENT SETTING RESISTOR
(PIN8toV-)

....

QUIESCENT CURRENT SETTING RESISTOR
(PIN 8to V-I

p
CD

IQ

Vs

o

100ILA

10ILA

30ILA

±1.5

1.5MO

470kO

150kO

-

±3

3.3MO

1.1MO

330kO

100kO

±6

7.5MO

2.7MO

750kO

220kO

N
Co»

300ILA

±9

13MO

4MO

1.3MO

350kO

±12

18MO

5.6MO

1.5MO

510kO

±15

22MO

7.5MO

2.2MO

620kO

100 k!! u.:I..J4..L...LJ..L.J..J..Ju..Ju...L.ll.J

o

2

4

6

8 10 12 14 16 18

SUPPLY \lOl.TACiE ,"Ill

0311-7

TYPICAL PERFORMANCE CHARACTERISTICS·
(TA = + 25'C, Vs = ± 6V, 10= 30ILA unless otherwise specified.)
INPUT BIAS CURRENT VS
QUIESCENT CURRENT

.ao

i

i.

mlll

a '0

INPUT BIAS CURRENT VS
AMBIENT TEMPERATURE
.00

50

'0

~

DIFFERENTIAL INPUT IMPEDANCE
VS QUIESCENT CURRENT

ii

Ig ·,00,.A

••I.:io.!'
IQ-U:J,.A

S

!

•.0

•-to

30

300
'00
OUIESCENT CURRENT (ItAI

I I I
-20 0 20

60

100

140

TEMPERATURE I CI

0311-8

.~~u...L~~~~~

10

30

100

300

QUIESCENT CURRENT j",AI

0311-9

0311-10

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTV ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bBen characIsriZfId but SNJ not f8st8d.

7-89

(It

""oat

.""

d
::::.
o

IIID~OI!..

ICL8021/ICL8023
TYPICAL PERFORMANCE CHARACTERISTICS*
(TA= +2S·C, Vs= ±6V, la=30",A unless otherwise specified,) (Continued)
SLEW RATE VS
QUIESCENT CURRENT

3

FREQUENCY RESPONSE VS
QUIESCENT CURRENT

PHASE MARGIN VS
QUIESCENT CURRENT
",-20W

S:!

........ 1--

1,....00

L

V
iI'
o
QUIESCENT CURRENT f"AI

10

10

300

100

30

QUIESCENT CuRRENT I,.A)

100
300
30
QUIESCENT CURRENT c..A)

0311-13

0311-11

0311-12

OPEN-LOOP FREQUENCY
RESPONSE

MAXIMUM LOAD VS
QUIESCENT CURRENT

TRANSIENT RESPONSE
Rio.· 'Okn
Ct ·'00pF

;: 20
!

100

w

"~ "
0

>

§

!-!-!-H~H-+--l

40 .......

z

"

10

~

~:>
~=RISE TIME

10

lk

1

12

IOU ..

FREOUENCY IHzl

"
Z

~

EQUIVALENT INPUT NOISE
VOLTAGE VS FREQUENCY

~

Rt

~
0

a

20kU

:==

~

0

'I

!;::::

IQ.'00"A~
10 -30"A0'

10· 10"A"i

/

>

!J

~6

~10

~ .,~~~

r,

I

1111111

1

100

10

Jl

01
500

,.

10

50

100

500

1k

FReaUENCY IHlI

FAEQUENCV CHl!

0311-17

',~O,~~

......... l.!<

"I

1111111
50

SUPPl,.YVOLTAGE lVI

0311-16

EQUIVALENT INPUT NOISE
CURRENT VS FREQUENCY

1111111

./

I I Uffi

10

300

0311-15

0311-14

30

100

30

QUIESCENT CURRENT I",AI

TIME 1/ot1K)

OUTPUT VOLTAGE SWING VS
SUPPLY VOLTAGE
~

10

16

q,V

~f

0

~

j

"

0311-18

0311-19

*ICL8021C guaranteed only for O·C:5:TA:5: +70·C

INTERSIL'S SOLE ANO EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PROOUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicsl values have bsen characterized but sre not tBsted

7-90

D~DIL2o

ICL8043

.

Dual JFET Input Operational
Amplifier

Cot

GENERAL DESCRIPTION

FEATURES

The ICL8043 contains two FET input op amps, each similar in performance to the ICL8007. The inputs and outputs
are fully short circuit protected, and no latch-up problems
exist. Offset nulling is accomplished by using a single pot
(for each amplifier) connected to the positive supply voltage. The devices have excellent common mode rejection.

•
•
•
•
•

Very Low Input Current - 2pA Typical
High Slew Rate-6V/ILs
Internal Frequency Compensation
Low Power DIssipation -135mW Typical
Monolithic Construction

ORDERING INFORMATION
Part Number

Temperature
Range

ICL8043MJE

- 55°C to 125°C

CERAMIC
16 Pin DIP

ICL8043CJE

O"Cto70"C

CERAMIC
16PinDIP

Package

-

INPUT

OI'I'IET NUU.

t-+--oOUTPUT
-IN

(outline dwgs JE. PEl
0312-2

Figure 2: Pin Configuration
16 Pin DIP (Top View)

0312-1

Figure 1: Functional Diagram
(One Side)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE:AHtrPfcBI _ _ bHn_butllJ'9not_

7-91

~
o

ICL8043

!:!

ABSOLUTE MAXIMUM RATINGS

3

Supply Voltage ................................. ± lSV
Internal Power Dissipation (Note 1) .............. 500mW
DifferentiallnputVoltage ........................ ±30V
Input Voltage (Note 2) ........................... ± 15V
Voltage between Offset Null and V+ ............. ± 0.5V
Storage Temperature Range . . . . . . . . .. - 65'C to + 150'C

Operating Temperature Range
S043M ........................... - 55'C to + 125'C
S043C ............................... O'C to + 70'C
Lead Temperature (Soldering, 10sec) ............. 300'C
Output Short·Circuit Duration .................. Indefinite

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these O( any other conditions above those indicated in the operational ssctions of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
NOTES: 1. Rating applies for case temperatures to 125'C; derate linearly at 9mW I'C for ambient temperatures above

+ 95'C.

2. For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.

ELECTRICAL CHARACTERISTICS
Symbol

Characteristic

(VSUPPLY= ± 15V unless otherWise specified)
8043M

Test Conditions
Min

8043C

Typ

Max

10

20

Min

Units

Typ

Max

20

50

The following specifications apply for T A = 25'C:
Vas

Input Offset Voltage

los

Input Offset Current

0.5

liN

Input Current (either input)

2.0
106

RIN

Input Resistance

CIN

Input Capacitance

Av

Large Signal Voltage Gain

Rs<100kO

0.5
20

3.0

pA
50

106

50,000

pA
MO

2.0

2.0
RL>2kO, Vout= ± 10V

mV

pF
VIV

20,000

Ro

Output Resistance

75

75

0

Isc

Output Short·Circuit Current

25

25

mA

ISUPPLY

Supply Current (Total)

4.5

6

4.5

6.S

Po ISS

Power Consumption

135

180

135

204

SR

Slew Rate

6.0

6.0

V/p,s

GBW

Unity Gain Bandwidth

1.0

1.0

MHz

tr

Transient Response (Unity Gain)
Risetime
Overshoot

300
10

300
10

ns
%

CL <100pF, RL =2kO

mA
mW

The following specifications apply for O'C2kO

±10

±13

±10

±13

15

30

2.0

15

75

p,VIV
VIV

RL>10kO

TA=+125'C

600

15,000

TA= +70'C
aVOS lilT

300

25,000

V
V

30

60

50

175

mV
nA

75

pA
p,VI'C

(Note 3)

NOTE: 3. For Design only, not 100% tested.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

7·92

1II0~OI!.. C;
r-

ICL8043

.
CD

o

TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF FREQUENCY
105
105 ~

I'\.

10

OUTPUT VOLTAGE SWING AS A
FUNCTION OF FREQUENCY

vsJPP =l,lY I-TA

~

~;'~N~

=+25°C

~

...

.....g
....i

I\..

r'..

:>

1\
0

I!OUTPUT

1\

-4

fo· - 1-1- I-

0

-8

1\

10k

100 lk 10k lOOk 1M 10M
FREQUENCY (Hz)

lOOk

10M

1M

0123456789

FREQUENCY (Hz)

TIME (ps)
0312-4

0312-3

0312-5

OUTPUT SWING AS A FUNCTION
OF SUPPLY VOLTAGE

INPUT CURRENT AS A FUNCTION
OF TEMPERATURE

TRANSIENT RESPONSE

20

I

l

TA)= 25 C
TL = 2kll

I

~

~ 15

I0'Io

i"

I

.i
.



./

4 rlO'1 f- RISE- - VSUpp = ±15V
....., TIME
TA = HOC
RL = 2k/l
0
CL = l00pF

o

,

~

~

~

1 1YIuPP •• 16V
1 1 T•• 25°C
1 1
INPUT
1

8

TA • +25°C
ft. ·10ka

Co»

VOLTAGE FOLLOWER LARGE·
SIGNAL PULSE RESPONSE

-

V

7

V

- ~
NEjATIVE jWINj- I--

./
40

2.5

SO
SO 100 120
TEMPERATURE (OC)

±S

INPUT VOLTAGE RANGE AS A
FUNCTION OF SUPPLY VOLTAGE

/.~

0312-8

8

i

/. /
1/,1'
- -POSITI,

/1'

~GATIVE- f--

Ii ---

±10

0312-9

~

~~

I-""

2
±S

±1S

±2O

±5

±10

±15

±2O

SUPPLY VOLTAGE

SUPPLY VOLTAGE

SUPPLY VOLTAGE

TAJHOC
5

il

I'
1~0~~~±5~~±~'~0~-_~+1~5~-±20~

±2O

±15

QUIESCENT SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

20

106

±10

SUPPLY VOLTAGE

0312-7

0312-6

OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF SUPPLY VOLTAGE

140

0312-10

0312,11

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

7-93

: ICL8043
o

a

TYPICAL PERFORMANCE CHARACTERISTICS
TOTAL QUIESCENT SUPPLY
CURRENT AS A FUNCTION OF
TEMPERATURE

•

I

I

I.E :
2

-

Ys= :!:lIY

r-.. r-..

--

(Continued)

INPUT NOISE VOLTAGE AS A
FUNCTION OF FREQUENCY

WIDEBAND NOISE AS A FUNCTION
OF SOURCE RESISTANCE

104

,,1000

e

~

... 100

!!!

r-..

~
~ ,o.0

As-.l Mn

I'

o

..

-15
TEMPI!RATURE (OC)

10

..1'

I'

w

100

R,,=50n

it
a::

1.0

1111

i

0.1

lk

10k

BANDWIDTH
• 0.1 Hz r.o I

lOOk

100

lk

FREQUENCY (Hz)

105

,/

~

a:

i

-IS

r- BANDWIDTH
---:
r-" 10Hz TO l00kHZ,TI""r-

10k

lOOk

1M

ktz=_=

10M 100M

SOURCE RESISTANCE 1111

0312-13

0312-14

0312-12

y+

y+

WiF

~c-~
V

1

7

~'OV

1]1
Rc

-

- b-~

10

;/'

16

RMB
VOLTMETER

r~ 1

10

I

~

0312-16

Figure 4: Channel Separation Test Circuit
0312-15

Figure 3: Offset Voltage Null Circuit

110

T

CHANNEL SEPARATION

100

Channel separation or crosstalk is measured using the
circuit of Figure 4. One amplifier is driven so that its output
swings ± 10V; the signal amplitude seen in the other amplifier (referred to the input) is then measured. Typical performance is shown in Figure 5.
Channel Separation = 20 log

iz

~

iIII

(V~~~~~»)

~

10

= lie

,

-;;:F

RL = 10k

10

\

70

10

50

100

~
lk

10k

lOOk

FREQUENCY (Hz)

1M
0312-17

Figure 5: Channel Separation Performance

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OSLiGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AN typIcsJ vsluss have been charactWBd bul ars not testBd.

7-94

1Il0~OIL

ICL8043

,
CD

out. Following this nulling operation, Al is used as a normal
amplifier while the voltage necessary to zero its offset voltage is stored on the integrator comprised of A2 and Gl.
The advantage of this circuit is that it allows chopper amplifier performance to be achieved at one-tenth the cost.
The only limitation is that during the offset nulling mode, Al
is disconnected from the input. However, in most data acquisition systems, many inputs are scanned sequentially. It
is fairly simple to synchronize the offset nulling operation so
that it does not occur when that particular amplifier is being
"looked at". For the component values shown in Figure 3,
and assuming a total leakage of 50pA at the inverting input
of A2, the offset voltage referred to the input of Al will drift
away from zero at only 40,.. V /sec. Thus, the offset nulling
information stored on Gl can be "refreshed" relatively infrequently. The measured offset voltage of Al during the amplification mode was 11,..V; offset voltage drift with temperature was less than 0.1,..VI'G.

APPLICATIONS
Applications for any dual amplifier fall into two categories.
There are those which use the two-in-one package concept
simply to save circuit-board space and cost, but more interesting are those circuits where the two sides of the dual are
used to complement one another in a subsystem application. The circuits which follow have been selected on this
basis.

AUTOMATIC OFFSET SUPPRESSION
CIRCUIT
The circuit shown in Figure 6 uses one amplifier (AI) as a
normal gain stage, while the other (A2) forms part of an
offset voltage zeroing loop. There are two modes of operation which occur sequentially. First, an offset null correction
mode occurs during which the offset voltage of Al is nulled

o

..
Co)

130kll

5

lkll

c;
SWa·
g

I

I

•

lOkIl

I
0312-16

·SW, • SW2. & SWs ARE ALL PART OF A SINGLE IH5043 CMOS ANALOG SWITCH CONNECTED AS SHOWN IN FIGURE SIb)

Figure 6(a): Automatic Offset Null Circuit

+5V

+15V

LOGIC
INPUT

0312-19

Figure 6(b)

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valu9s have been characterized but are not tested.

7-95

•

~
o

ICL8043

CD

ii
tOOkn

;tfttal~'

,01 ...'

ID 100
LOW LEAKAGE

L..-=..,;;j::;"'=...I:==;"I,,;=..;:::...;::t...::::J }(SVlDIVI

DIODE PAIR

HORIZONTAL = SOmS/QIV

0312-20

Figure 7: Staircase Generator Circuit

IH5042

1kn

HORIZONTAL = 200mS/DIV

10100
LOWLEAKAQE

DIODE PAIR

10k!}

Vour VREF

0312-21

Figure 8: Analog Counter Circuit
assure complete discharge. The upper trip point could then
be adjusted independently to determine the pulse count.

STAIRCASE GENERATOR
The circuit shown in Figure 7 is a high input impedance
version of the so-called "diode pump" or staircase generator. Note that charge transfer takes place at the negativegoing edge of the input-signal.
The most common application for staircase generators is
in low cost counters. By resetting the capacitor when the
output reaches a predetermined level, the circuit may be
made to count reliably up to a maximum of about 10. A
straightforward circuit using a LM311 for the level detector,
and a CMOS analog gate to discharge the capacitor, is
shown in Figure 8. An important property of this type of
counter is the ease with which the count can be changed; it
is only necessary to change the voltage at which the comparator trips. A low cost A-D. converter can also be designed using the same principle since the digital cOLint between reset periods is directly proportional to the analog
voltage used as a reference for the comparator.
A considerable amount of hysteresis is used in the comparator shown in Figure 8. This ensures that the capacitor is
completely discharged during the reset period. In a more
sophisticated circuit, a dual comparator "window detector"
could be used, the lower trip point set close to ground to

SAMPLE & HOLD CIRCUIT
Two important properties of the 8043 are used to advantage in this circuit. The low input bias currents give rise to
slow output decay rates ("droop") in the hold mode, while
the high slew rate (6V / fLS) improves the tracking speed and
the response time of the circuit. See Figure 6.
The ability of the circuit to track fast moving inputs is
shown in Figure 10A. The upper waveform is the input
(10V/div), the lower waveform the output (5V/div). The logic input is high.
Actual sample and hold waveforms are shown in Figure
10B. The center waveform is the analog input, a ramp moving at about 67V /ms, the lower waveform is the logic input
to the sample & hold; a logic "1" initiates the sample mode.
The upper waveform is the output, displaced by about 1
scope division (2V) from the input to avoid superimposing
traces. The hold mode, during which the output remains
constant, is clearly visible. At the beginning of a sample
period, the output takes about 8fLs to catch up with the
input, after which it tracks until the next hold period.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

7-96

ICL8043

L

-15V

~~

u~
"~
1/28043

'1' ~~u

ANALOG
INPUT

+15V

1

:

18

.1

...'f-, r1L-

--.!

r!! -15V

n

4

5

...!
..!

~+5V

~~

t1!+15V

5111

I

10
OUTPUT

-15V

10,000 pF
POLYSTYRENE

~

1-,-

10

I
I

8

•

IH5043

+3V = > SAMPLE MODE
OV = > HOLD MODE
0312-22

Figure 9: Sample And Hold Circuit

•

,....,
r--...

A

I

1\

--..

r--.... r':o'!..

--

~ !'!o.
t'- ,.....,
f"""""-

0312-23

TOP: INPUT (10V/DIV)
BOTTOM: OUTPUT (SV/DIV)
HORIZONTAL: 10",s/DIV

ro-..... I""!!o

to0312-24

TOP:2V/DIV
CENTER: 2V/DIV
BOTTOM: 10V/DIV
HORIZONTAL: 10",s/DIV

Figure 10A

Figure 108

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LJEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

7-97

: ICL8043
o

~ INSTRUMENTATION AMPLIFIER
51! A dual JFET-input operational amplifier is an

attractive
component around which to build an instrumentation amplifier because of the high input resistance. The circuit shown
in Figure 11 uses the popular triple op-amp approach. The
output amplifier is a High Speed 741 (741 HS. slew rate
guaranteed:?: O. 7VI ,..s) so that the high slew rate of the
8043 is utilized to the full extent. Input resistance of the
circuit (either input. regardless of gain configuration) is in
excess of 1012 ohms.
For the component values shown. the overall amplifier
.
2R1+R2
gain is 200 (front end gain = ~. back end

---

Common mode rejection is largely determined by the
matching between R4 and Rs. and Rs and R7. In applications where offset nulling is required. a single potentiometer
can be connected as shown in Figure 12.
Another popular circuit is given in Figure 13. In this case
the gain is 1 + R1/R2. and the CMRR determined by the
match between R1 and R4. R2 and R3.
For more information on FET input operational amplifiers.
see Intersil Application Bulletin A005 "The 8007: A High
Performance FET-input Operational Amplifier."

... ..

0312-26

Figure 12: Offset Nulling Both Amplifiers With
One Potentiometer

.

-

.

-..

...

..
.... .
..

0312-27

Figure 13: Modlflec:llnstrumentatlon Amplifier

0312-25

Figure 11: Instrumentation Amplifier

INTERSIL'S SOLE AND EXCWSIVE WARRANTY OBUGA110N WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE OONDI11ON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRAN11ES, EXPRESs, IMPUED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.

NOTE: AD typJcsl va/u6s """" """" _

but.,.

not_
7-98

D~DIL2o

ICL8063

Power Transistor DriverI Amplifier

oCo)

GENERAL DESCRIPTION

FEATURES

The ICL8063 is a unique monolithic power transistor driver and amplifier that allows construction of minimum chip
power amplifier systems. It includes built in safe operating
area circuitry, short circuit protection and voltage regulators,
and is primarily intended for driving complementary output
stages.
Designed to operate with all varieties of operational amplifiers and other functions, two external power transistors,
and 8 to 10 passive components, the ICL8063 is ideal for
use in such applications as linear and rotary actuator drivers, stepper motor drivers, servo motor drivers, power supplies, power DACs and electronically controlled orifices.
The ICL8063 takes the output levels (typically ± 11 V)
from an op amp and boosts them to ± 30V to drive power
transistors, (e.g. 2N3055 (NPN) and 2N3789 (PNP». The
outputs from the ICL8063 supply up to 100mA to the base
leads of the external power transistors.
The amplifier-driver contains internal positive and negative regulators, to power an op amp or other device; thus,
only ± 30V supplies are needed for a complete power amp.

• Converts ± 12V Outputs From Op Amps and Other
Linear Devices to ± 30V Levels
• When Used In Conjunction With General·Purpose Op
Amps and External Complementary Power
Transistors, System Can Deliver> 50 Watts to
External Loads
• Bullt·ln Safe Area Protection and Short·Clrcult
Protection
• Produces 25mA Quiescent Current In Power Output
Stage
• Bullt·ln ± 13V Regulators to Power Op Amps or
Other External Functions
• 500k!} Input Impedance With RBIAS= 1M!}

ORDERING INFORMATION
Part Number

Temperature
Range

Package

ICL8063MJE

- 55·C to + 125·C

CERDIP

ICL8063CJE

O·Cto +70·C

CERDIP

ICL8063CPE

O·Cto +70·C

PLASTIC DIP

•

- VREGOUT ,

-RaIAS
14 T RalAS
13 V +

y-

FREQ. COMPo CAPAC.
PHP BASE DRive OUTPUT

-ASHORTCKT.PROT.
OUTPUT

"
,

---..._-......

GND

11 NPN BASE DRIVE OUTPUT

10 CUARENTCOMP.CAPAC.
• + RSHORT CKT. PROT.

0314-2

Figure 2: Pin Configuration

0314-1

Figure 1: Functional Diagram

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have besn characterized but are not tested.

7-99

: ICL8063
o

3
~

ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................. ± 35V
Power Dissipation ............................. 500mW
Input Voltage (Note 1) ........................... ±30V
Regulator Output Currents ....................... 10mA
Operating Temperature Range
ICL8063MJE ...... .. .. .. .. . .. .. ... - 55'C to + 125'C
ICL8063CPE .......................... O'C to + 70'C
ICL8063CJE .......................... O'C to + 70'C
Storage Temperature Range .......... - 65'C to + 150'C
Lead Temperature (Soldering. 10sec) ............. 300'C

ELECTRICAL CHARACTERISTICS

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only

and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied Exposure to absolute maximum rating conditions for extended PSri~

ods may affect device reliability.

(TA=25'C; VSUPPLY= ±30V)
MinIMax Limits

Symbol

Characteristic

ICL8063M

Test Conditions

ICL8063C

-55'C

+ 25'C

+ 125'C

O'C

+ 25'C

Units
+70'C

Vas

Max. Offset Voltage

See Figure 3

150

50

50

75

mV

10H

Min. Positive Drive
Current

See Figure 4

50

50

50

40

mA

100

Max. Positive Output
Quiescent Current

See Figure 5

500

250

250

300

p,A

10L

Min. Negative Drive
Current

See Figure 4

25

25

25

20

mA

10L

Max. Negative Output
Quiescent Current

See Figure 6

500

250

250

300

p,A

±13.7
±1.2V

±13.7
±1.0V

±13.7
±1.5V

10

10

10

mA

400
(Typ)

400
(Typ)

kO

VREG

Regulator Output Voltages
Range

IREG

Regulator Output Current

(See Note 2)

ZIN

A.C. Input Impedance

See Figure 8

VSUPPLY

Power Supply Range

10

Power Supply
Quiescent Currents

Av

Range of Voltage Gain

VaUT(MIN) Minimum Output Swing
ISlAS

Input Bias Current

±13.7
±1.0V

±13.7
± 1.0V

±5 to ±35V

±13.7
±1.0V

V

V

10

6

6

7

mA

See Figure 9
VIN=8Vp-p

6±2

6±2

6±2

6±2

V/V

See Figure 9; Increase
VIN until VOUT flattens

±27

±27

±27

±27

V

See Figure 10

100

100

100

100

p,A

NOTES: 1. For supply voltages less than ±30V the absolute maximum input voltage is equal to the supply voltage.
2. Care should be taken to ensure that maximum power dissipation is not exceeded.

INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTiCULAR USE.
NOTE: All typical values have been characterized but are not tested

7-100

ICL8063
TEST CIRCUITS
+IOV

0314-3

0314-4

FOR lOUT: VIN IS POSITIVE: INCREASE VIN UNTIL lour LIMITS
FOR lOUT: VIN IS NEGATIVE: INCREASE VIN UNTIL lOUT LIMITS

Figure 3: Offset Voltage Measurement

Figure 4: Output Current Measurement

•
0314-5

0314-7

Figure 5: Positive Output Quiescent Current

Figure 7: On Chip Regulator Measurement

0314-6

0314-8

Figure 6: Negative Output Quiescent Current

Figure 8: A.C. Input Impedance Measurement

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO llilS PRODUCT SHALL BE lliAT STATED IN THE WARRANTY ARTICLE OF lliE CONDITION OF SALE.
lliE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES. EXPRESS. IMPUED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typ/C8I .._

118"" bsIJn ~ but 119 not toBtsd.

7-101

:: ICL8063
o

CO

sf

TEST CIRCUITS

Using the ICL8063 to make a complete
Power Amplifier

(Continued)

As Figure 11 shows, using the ICL8063 allows the circuit
designer to build a power amplifier block capable of delivering ±2 amperes at ±25 volts (50 watts) to any load, with
only three additional discrete devices and 8 passive components. Moreover, the circuit draws only about ± 30 milliamperes of quiescent current from either of the ± 30V power
supplies. A similar design using discrete components would
require anywhere from 50 to 100 components.
Slew rate is about the same as that of a 741 op amp,
approximately 1V/ p.s. Input current, voltage offset, CMRR
and PSRR are also the same. Use of 1,000 picofarad compensation capacitors (three in this configuration) allows
good stability down to unity gain non-inverting (the worst
case). This circuit will drive a 1000pF CL to Gnd, or in other
words, the circuit can drive 30 feet of RG-58 coaxial cable
for line driver applications with no problems.

,--...,..-,,-oVo
Av =.!2.
Y,N

-3OY

0314-9

Figure 9: Gain and Output Voltage
Swing Measurement

-IN

GAn

@SW

0314-10

Figure 10: Input Bias Current Measurement

APPLICATIONS INFORMATION
One problem faced almost every day by circuit designers
is how to interface the low voltage, low current outputs of
linear and digital devices to that of power transistors and
darlingtons.
For example, a low level op amp has a typical output
voltage range of ± 6 to ± 12V, and output current usually on
the order of about 5 milliamperes. A power transistor with a
±35 volt supply, a collector current of 5 amperes, and a
beta, or gain of 100 needs at least 50 milliamperes of drive.
In the past, connecting two transistors with widely dissimilar requirements meant that a rather ornate discrete circuit
had to be built to convert the weak output signals from the
first into levels large enough to drive the second. However,
in addition to converting voltage and current, it was also
necessary to include a number of protection circuits to
guard against damage from shorts, for example, and all this
design work was both tedious and expensive.
The ICL8063 provides a solution to these problems. It's a
monolithic power transistor driver and power transistor amplifier circuit on the same chip, has all the necessary safe
operating area circuitry and short circuit protection, and has
on-chip ± 13V voltage regulators to eliminate the need for
eldra eldemal power supplies.

0314-11

Figure 11: Standard Circuit Diagram

EXTERNAl.
POWER TRANSISTOR

REST OF CIRCUITRY
I. INTeRNAL TO
ICL8M3

TO OTHER SIDE

0314-12

Figure 12: Current Limiting (Safe Area)
Protection Clrcul~ (one side shown)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
'

NOTE: All typical values ""va - . charactBr/zBd but.,. not tostod.

7-102

IIO~OIl. (I)
r-

ICL8063

CD

As Figure 12 indicates, setting up a current limiting (safe
area) protection circuit is straightforward. The 0.4 ohm, 5
watt resistors set the maximum current one can get out of
the output. The equation this SOA circuit follows is: for
VOUT positive,
R2
Vbe=ILR3
-R (VOUT+ILR3- 0.7V)
R1+
2

Often design requirements necessitate an unsymmetrical
output current capability. In that case, instead of the 0.4
ohm resistors protecting the npn and pnp output stages, as
shown in Figure 11, simply substitute any other value. For
example, if up to 3 amps are required when VOUT:0-+-00"'0'"

0270-4

.,,,,

0125

~--+--O\lo

.,

0270-3

0270-5

Circuit Diagrams

Figure 2: Switching Times

TYPICAL PERFORMANCE CHARACTERISTICS
SWITCHING TIMES
VS TEMPERATURE
0123 AND 0125
(SEE NOTES 4 AND 5)

toff(delay) VS IIN(PEAK)
0123
~

1.8

M

1.7

1

Ie

1.6

o

1.5

'"~

<

~

~

1100

I-

/'

1.2

1 IJ
j
I

1. 1
1.0 1

f

/

V

vee' -20V

>-

l000pF

i

II)

300

(1 mAt

--

-so

;; 800

o

25

.........
.........

z

V

:>

600

(delay)

I

75

400
125

-75

-25

25

75

125

TEMPERATURE (OCI

0270-7

0270-6

IOUT·O

.........

z2

TEMPERATURE (OCI

liN (PEAKI (mA)

'"""" r-...

!

I

tOff(4mA~

to,

100

...,.... V
toll

0< lOUT <4mA

TA·25°C

totl

-I"'"

soO -I--

liN -10mA
V. -0
VEE - -20V-

I

COUT - IOpF

C)

V+·10V

I I

VR' 0
VeE" -20V

v+ "" 10V

i=

";:z

VA -0

o < COUT "

900

~ 700

/

1.4

1.3

V

VIN(ON) VS TEMPERATURE
0123
1000

0270-6

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values hsV9 bgen characterized but are not tested..

8-3

..
..

: D123/D125
Q

;;- TYPICAL PERFORMANCE CHARACTERISTICS
N
Q

!

...
...a:z

0.6

I- v. I; 0
VEE

~

::>

l!;

0.5

,........,
125°C

a:

..

-20V

25°C

~

,.....+-~

<

.;

-55°C
0.6

VA "'0
Vu '" -20V

0.2

0.4

0.6

10'

;(
oS

0.3 1--+--+----+----1

.e,

.g

10'

I.

10'

10

1/

1..1

/
o

V... "'4.5V
Vee'" 10V

0.4

0.21--+-

II

/

~ 0.2

0123 AND 0125

r--.,.---.----,---,
I, •• 1 mA (0123)
v, •• 0.5V (0125)

1.4

...u::>

10UT(OFF) VS TEMPERATURE

0123 AND 0125

0123
1.8
;(

(Continued)

VSAT VS TEMPERATURE

iiNVSVIN

oL--~-~-~_~

-75

0.8

-25

25

75

125

V,. - INPUT VOLTAGE (V)

25

45

65

85

125

0270-11

0270-10

0270-9

105

TEMPERATURE (OC)

TEMPERATURE (OC)

APPLICATION TIPS
Interfacing the 0123 and 0125
In order to meet all the specifications on this data sheet,
certain requirements must be met by the drive circuitry.
The D125 can be turned ON easily, but care must be
exercised to insure turn-off. Keeping VL - VIN:O;O.4V is a
must to insure turn-off. To accomplish this, a shunt resistor
must be added to supply the leakage current (ICES) for DTL
devices. Since ICES=50,..A, a 0.4V/O.05mA =8kO or less
resistor should be used. For TTL devices using a 2kO resistor will insure turn-off with up to 200,..A of leakage current.

0270-14

Figure 4: D125 Interface

Using the ENABLE Control
Device pins VA or VL, can be used to enable the D123 or
D125 drivers. For the D123, the enabling driver must sink
IA(ON) X no. of channels used. For the D125, IL(ON) X no. of
channels used must be sourced with a voltage at least + 4V
greater than VIN.

0270-13

Figure 3: D123lnter1ace

INTERSll'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicsl values have been characterized but are not tested.

8-4

D129
4-Channel Decoded JFET
Switch Driver
GENERAL DESCRIPTION

FEATURES

The D129 is a 4-channel driver with binary decode input.
It was designed to provide the DC level-shifting required to
interface low-level logic outputs (0.7 to 2.2V) to field-effect
transistor inputs (up to 50V peak-to-peak). For a 5V input
logic supply, the V- terminal can be set at any voltage between -5Vand -30V. The output transistor is capable of
sinking 10mA and will stand-off up to 50V above V- in the
off-state.
The ON state of the driver is controlled by a logic "1"
(open) on all three input logic lines, while the OFF state of
the driver is achieved by pulling anyone of the three inputs
to a logic "0" (ground).
The 4-channel driver is internally connected such that
each one can be controlled independently or decoded from
a binary counter.

• Quad Three-Input Gates Decode Binary Counter to
Four Lines
• Inputs Compatible With Low Power TTL and DTL,
IF=200",A Max
• Output Current Sinking Capability 10mA
• External Pull-Up Elements Required

ORDERING INFORMATION
0129

L
A

K

PaCkage
K-l4-pin CERDIP
L-l4-pin Flat Package
P-14·pin Ceramic DIP
(Special Order Only)
Temperature Range
A-Military (-55"C to + 125"C)
B-Commercial (-20"C to +85"C)

' - - - - - - - - Device Chip Type
0271-5

v'

,.

36K

2.6K

IN,

13

IN2

INPUTS

12
IN3
IN.
INS

11

IN.

,.
IN,

OUT,

OUT 2

OUTa

OUT 4

(EACH DRIVER)

0271-1

ONO

v0271-2

Figure 1: Functional Diagrams (Outline Dwgs DO, FD-2, JD)

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WAARANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

8-5

~

.U~OIL

D129

is
ABSOLUTE MAXIMUM RATINGS
Yo GND
Y+ YIN -

Y- ........................................ 50Y
- Y- ...................................... 33Y
GND ....................................... 8Y
GND ..................................... ±6V

Note: Dissipation rating assumes device mounted
ambient temperatures.

w~h

Current (any terminal) ........................... 30mA
Storage Temperature ................ - 65·C to + 150·C
Operating Temperature .............. -55·C to + 125·C
Power Dissipation (note) ....................... 750mW
Lead Temperature (Soldering, 10sec) ............• 300·C

all leads welded or soldered to pc board in ambient temperature of 70"C. Derate 1OmW

rc for higher

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the devic6. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sactions of the specifications is not implied. £xposUf'9 to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Test conditions unless otherwise specified V- = -20V, V+ = 5V
Maximum Limit

Symbol

Parameter

Test Conditions

0129M

01291

-SS·C 2S·C

12S·C

-19.3 -19.3

-19

-20·C

2S·C

Units
8S·C

OUT
VOL

Output Voltage, Low

io=10mA

VOL

Output Voltage, Low

lo=1mA

IOH

Output Current, High

Vo= 10V, VIN=0.7V

0.1

0.1

20

0.2

0.2

10

Input Current
Input Voltage High

VIN=5V Input Under Test,
VIN = 0 All Other Inputs

0.25

0.25

5

1

1

5

Input Current
Input Voltage Low

VI~ = 0, V+ = 5.5V

-250

-200

-160

-250

-225

-200

VIN=2.2V, V+ =4.5V

-19.25 -19.25 -19

V

-19.8 -19.8 -19.75
p.A

INPUT
IINH
IINL

.
.

p.A

TIME
Turn-ON Time

Ion
Iolf

See Switching Time Test Circuit

Turn-OFF Time

0.25

0.3

1.0

1.5

-2

-2.25

3

3.3

p.s

SUPPLY
lEE

Negative Supply Current

IL

Logic Supply Current

lEE

Negative Supply Current V+ =5.5V

All VIN=O,

-10

-25

p.A

IL

Logic Supply Current

All Channels "OFF"

0.75

1

mA

One Channel "ON"
V- = -20V

mA

'Per gate Input
.5V

IN

=4

j
tV

I

.,OY
>3.

~

I
I

IN +1+:~=t

If"' lOOns
t, '" lOOns

OV

lpw"'''s
f"looK Hz
OUT

.lOV
OUT

t.n~
_

OV-----2OV

1

~90%

0271-4

0271-3

Figure 2: Switching Time and Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been charactenz8d but ar8 not tested

8-6

DG123/DG125
4 & 5-Channel SPST Driver
With Switch
GENERAL DESCRIPTION

FEATURES

This series includes devices with four and five channel
switching capability. Each channel is composed of a driver
and a MOSFET switch. Two driver versions are supplied for
inverting and noninverting applications. A MOSFET, used as
a current source provides an active pull-up for faster switching.
An external biasing connection is brought out for biasing
the current source, for optimization of speed and power.

• Available With and Without Programmable Constant
Current Pull-up
• Zener Protection on All Gates
• P-Channel Enhancement-Type MOSFET Switches
• Each Switch Summed to One Common Point

ORDERING INFORMATION

TRUTH TABLE

DG123

r[ --A

K

DG123

L - 14-pin Flat Package
P - 14-pin Ceramic DIP

Temperature Range
A - Military (- 55'C to + 125'C)
B - Commercial (- 20'C to + 85'C)

DG125

VIN

VR

VIN

VL

Switch
Condo

L
H
L
H

L
L
H
H

L
L
H
H

L
H
L
H

OFF
ON
OFF
OFF

L=OV, H= +V

L..------Device Chip Type

OG123

OG125

(One Channell

(One Channel)
II\.

y.

'N

y-

Yo

.,,".
.,'

,'

..""

y-

y'

"

y'

"

3.

,,
,,,
,,

,
•

,, ,

,,, ,,,, :, !
, ,, ,,
,
: ,,, ,!
,, ,:,

.

I

___ J

_____ J

,,
,

________ J

0272-2

0272-3

Figure 1: Schematic & Logic Diagrams (Outline Dwgs DD, FD-2)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valU6S have b6en characterized but are not tBStBd.

8-7

: DG123/DG125

i

"C\I
...
Ii
fI)

ABSOLUTE MAXIMUM RATINGS
LogiC to Input (VL - VIN) , • . • . . • • • . . . . • • • • . • . • • . • • .. ± 6V
Input to Emitter (VIN-V-) ......................... 33V
Current (any terminal) ........................... 30mA
Storage Temperature ...••.•.•..•••••• - 65°C to + t 50"C
Operating Temperature ...•........... -55°C to + 125°C
Dissipation (Note) ....•........................ 750mW
Lead Temperature (Soldering,10sec) ............. 300"C

Collector to Emitter (V+ - V-I .....•....•.......... 33V
Collector to Pull-up (V+ -Vp) ...................... 33V
Drain to Emitter (Vo-V-) ......................... 32V
Source to Emitter (Vs-V-) ......••.............•. 32V
Drain to Source (Vo-Vs) .......................... 28V
Source to Drain (Vs-Vo) ...........•.............. 28V
Logic to Emitter (VL - V-I •.............•.......... 33V
Reference to Emitter (VR-V-) .....•...•........•• 31V
Reference to Input (VR-VIN) ....................... 6V

NOTE: Oissipation rating assumes device is mountad with all laads welded
or soldered to printed circuit board in ambient temperature 01 70'C.
Derate 10mW/'C lor higher ambient temperature.

NOTE: Stresses above Ihoss listed under "Absolute Maximum Ratings" may cause permtlnent damage to the davies. Thsss are stress ratings only and functional
operation of the daviC8 at these or any other conditions above Ihoss indicated in the operationsl sections of the specifications is not imp/i6d. Exposura to absolute
maximum rating conditions for extended pariods mayaffact davice re/isbUiIy.

ELECTRICAL CHARACTERISTICS
Test conditions unless specified otherwise are as follows: VL =4.5V, VR=O, V- = -20V. Input ON and OFF test conditions
used for output and power supply specifications.
Device No.

Parameter
(Note)

Max Limits

Test Conditions
-55°C

Units

+ 25°C

+ 125'C

Input
DG123
DG125

IIN(OFF)

VIN=0.4V

1

1

100

VIN(ON)

IIN=1mA

1.3

1.0

0.8

V

IIN(ON)

VIN=0.5V

-0.7

-0.7

-0.7

mA

Vo= 10V,ls= -1mA

100

100

125

(}

Vo=O,IS= -100/LA

200

200

250

(}

Vo= -10V,ls= -100/LA

450

450

600

(}

4

4000

nA

/LA

OUTPUT

rOS(ON)
All
circuits

IO(ON)

Vo=10V,IS(all)=0

IO(OFF)

VS(all) = 10V, Vo= -10V

-4

-4000

nA

IS(OFF)

Vo= 10V, Vs= -10V

-1

-1000

nA

POWER SUPPLY

All
circuits

All
circuits

ICC(ON)

3

mA

IL(ON)

3

mA

One Channel (ON)

IR(ON)

-0.5

rnA

IEE(ON)

-6

mA

ICC(OFF)

10

/LA

IL(OFF)

10

/LA

IR(OFF)

-15

/LA

IEE(OFF)

-20

/LA

0.3

/Ls

1

/Ls

All Channels (OFF)

SWITCHING TIMES
All
circuits

t(ON)

See Switching TImes

t(OFF)

NOTE: (OFF) and (ON) subscript notation refers to the conduction state 01 the MOSFET switch lor the given test condition.

INTERSIL·S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF BALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND RTNESS FOR A PARTICULAR USE.
NOTE: AU typicsJ Wliues have been chtmlct6rizBd but are not tflstsd.

8-8

DG123/DG125
OG 123

v,•
•,01,..s
t,O 1,..s

s,
t--.,--oOUTPUT

JO,.
0272-5
DO 123
OUTPUT

DG125

+4.SV

on
00125
OUTPUT

s,
t--...,.2K

OUTPUT

30 pF

0272-4
0272-6

Figure 2: Switching Times

TYPICAL PERFORMANCE CHARACTERISTICS
SWITCHING TIMES vs
TEMPERATURE

liN vs VIN
DG123
1.8

C

!
....Z

1~:g:N

'"'"

'...."

J

VR' 0
v-· -20V

1.4

_55°C

:>

CJ

..
:>

z

1100

0.6

'~

I

.!

0.2

0.4

I!l
::IE

700

11

~

V
o

]:

.,

)

0.2

C>

'"g

0.8

v,. -'NPUT VOLTAGE IVI

10Fr~

500

300
100

JL

V

IS:i:-1\'iA:
V+-r-1OV:
V-=-20V

i"'>. ~ 1.::.25°

IL
100

f' ~ to- l""- I' K- 55O

-10 ,

~

-so

rDS(ON) vs VD or Vs

12

."

1/
0.6

f

900 V+ lOX
COUT = 30pF

II N
III'}

i'

lK

J
V~20V

VR-O

o

10
25

75

125

-10

10

TEMPERATURE (OC)

0272-7

0272-8

0272-9

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

8-9

•

.

: DG123/DG125

e
..
g
C'?

(II

APPLICATION TIPS
The recommended resistor values for interfacing RTL,
DTL, and TTL Logic are shown in Figures 3 and 4.

'Te

OTL93f.t.tI.
949961.183

TTL $. 7.

TTl9000SfR!£S
SUM!,.

0272-11

Figure 4: DG123 Interface

0272-10

Figure 3: DG125 Interface

Enable Control
The VR and VL terminals can be used as either a Strobe
or an Enable control. The requirements for sinking current
at VR or sourcing current at VL are: IL(ON) x No. of channels
used, for the DG125, and IR(ON)XNo. of channels used for
the DG123 devices. The voltage at VL must be greater than
the voltage at VIN by at least +4V.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PAATICULAR USE.
'

NOTE: All typical values have been characterized but are not tested.

8-10

DG126, DG129, DG133,
DG134, DG140, DG141,
DG151-154
DUALJFET Analog Switch
GENERAL DESCRIPTION

FEATURES

These switching circuits contain two channels in one
package, each channel consisting of a driver circuit controlling a SPST or DPST junction FET switch. The driver interfaces DTL, TIL or RTL logic signals for multiplexing, commutating, and Df A converter applications, which permits
logic design directly with the switch function. Logic "1" at
the input turns the FET switch ON, and logic "0" turns it off.

• Each Channel Complete-Interfaces With Most
Integrated Logic
• Low OFF Power Dissipation, 1mW
• Switches Analog Signals Up to 20 Volts Peak-to-Peak

g

• Low rOS(ON), 10 Ohms Max on DG140/A and
DG1411A
• Switching Times Improved 100%-'A' Versions

....

~

g
....

ORDERING INFORMATION
DG129

A

...
g....

K

$'

Package
K - 14-pin CERDIP
(DGI26, 129, 133, 134, 151, 152, 154)
L - 14-pin Flat Pack
P - 14-pin Ceramic DIP
(00140,141)'

[

.......

g....

Temperature Range
A - Military ( - 55'C to + 125'C)
B - Industrial ( - 20'C to + eo'C)
L -_ _ _ _ _

....enI
....

Device Chip Type

OUALSPST
OG133 (rOS(ON) = 300)
OG134 (rDS(ON)= 800)
OG141 (rOS(ON)= 100)
OG151 (rOS(ON)= 150)
OG152 (rOS(ON) = san)

...en

OUALOPST
OG126 (rOS(ON) = 800)
OG129 (rOS(ON)= 300)
OG140 (rOS(ON)= laO)
OG153 (rOS(ON)= ISO)
OG154 (rOS(ON) = 500)

v11

11

v·
11

~~sw,

~~----------~.~~~,
~L-

~,

____~'~__+-~~~,

sw.
sw.

IN
IN

V" {ENABLEl
V~IENABlEI

10

v.

12

0273-2

0273-3

(ENABLEJ

0273-1
10

v.

(ENABLE)

12

0273-4

Figure 1: Functional Diagrams (Outline Dwgs DD, FD-2, JD)

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but ars not tested

8-11

~ DG126, DG129, DG133, DG134, DG140,
";' DG141, DG151-154

....
g
II)

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS
Analog Signal Voltage (VA -V- or V+ -VA) ......... 30V

~~~~~iI~~~~I~p~;~~~t~~~70-R~;~~it~g~ (V+' ~'v~i':::: ~~~

-;
.. Ref. Voltage to Neg. Supply Voltage (VR-V-) ....... 22V
Power Dissipation (Note) ....................... 750mW
Current(any terminal) ........................... 30mA
($ Storage Temperature ................ -65°C to + 150°C
Operating Temperature .............. - 55°C to + 125°C
:
.11
Lead Temperature (Soldering, 10sec) ............. 300°C

g
is

..;

NOTE: Dissipation rating assumes device is mounted with all leads welded or soldered to printed Circuit board in ambient temperature below 70°C. For higher
temperature, derate at rate of 1OmW

re.

~ ELECTRICAL CHARACTERISTICS (Per Channel)

g
c.)
C')

Applied voltages for ali test: DG126, DG129, DG133, DG134, DG140, DG141 (V+ = + 12V, V- = -18V, VR=O), and DG151,
DG152, DG153, DG154 (V+ = + 15V, V- = -15V, VR=O). Input test condition which guarantees FET switch ON or OFF as
specified is used for output and power supply specifications.
SYMBOL
(NOTE)

CHARACTERISTIC

TYPE

TEST CONDITIONS

ABSOLUTE MAX LIMIT
-55°C

25°C

125°C

UNIT

INPUT
VINfON)

Input Voltage-On

V2=-12V

2.9 min

2.5 min

2.0 min

Volts

VIN(OFF)

Input Voltage-Off

V2= -12V

1.4

1.0

0.6

Volts

IIN(ON)

Input Current

VIN=2.5V

120

60

60

/1- A

IIN~OFF)

Input Leakage Current

VIN=0.8V

0.1

0.1

2

/1- A

80

80

150

.n

30

30

50

.n

10

10

20

.n

15

15

30

.n

Ali Circuits

SWITCH OUTPUT
rOS(ON)

Drain-Source On Resistance

DG126
DG134
DG129
DG133

VIN = (See Note)
Vo=10V,ls=10mA

DG140
DG141
DG151
DG153
DG152
DG154

Vo=7.5V,ls=10mA
50

100

.n

Vo=Vs= -10V

±2

100

nA

Vs=10V, Vo= -10V

±1

100

nA

Vo= 10V, Vs= -10V

±1

100

nA

Vo=Vs= -10V

±2

100

nA

Vs=10V, Vo= -10V

±10

1000

nA

Vo=10V, Vs= -10V

±10

1000

nA

Vo=Vs= -7.5V

±2

500

nA

Vs= 7.5V, Vo= -7.5V

±10

1000

nA

VIN = (See Note)

50

IO(ON)+ IS(ON)

Drive Leakage Current

ISfOFF)

Source Leakage Current

IO(OFF)

Drain Leakage Current

DG126
DG129
DG133
DG134

IOfON) + ISfON)

Drive Leakage Current

DG140

IS1OFF)

Source Leakage Current

IO(OFF)

Drain Leakage Current

IOfON) + ISfON)

Drive Leakage Current

IS(OFF)

Source Leakage Current

IOfOFF)

Drain Leakage Current

Vo=7.5V, Vs= -7.5V

±10

1000

nA

IO(ON) + IS(ON)

Drive Leakage Current

Vo=Vs=-7.5V

±2

500

nA

IS(OFF)

Source Leakage Current

Vs=7.5V, Vo= -7.5V

±2

200

nA

±2

200

nA

DG141
DG151
DG153
DG152

DG154
Drain Leakage Current
Vo=7.5V, Vs= -7.5V
IOfOFFl
..
NOTE: VIN must be a step function with a minimum slew-rate of 1V l/1-s .

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WAARANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typicsl values have been characterized but are not tested.

8-12

IID~DI!..

DG126,DG129,DG133,DG134,DG140,
DG141, DG151-154
ELECTRICAL CHARACTERISTICS (Per Channel)
SYMBOL
(NOTE)

TYPE

CHARACTERISTIC

N

!lJ

(Continued)

TEST CONDITIONS

ABSOLUTE MAX LIMIT

-55'C

25'C

125'C

12(ON)

Negative Power Supply
Drain Current

IR(ON)

Reference Power Supply

11 (OFF)

Drain Current
Positive Power Supply
Leakage Current

-

12(OFF)

Negative Power Supply
Leakage Current

IR(OFF)

Reference Power Supply
Leakage Current

One Driver ON, VIN=2.5V
All Circuits

3

mA

-1.8

mA

-1.4

mA

25

/k A

Both Drivers OFF, VIN = 0.8V

-25

/k A

-25

/k A

tON

Turn-On Time

See Below

DG126, DG129, DG133,
DG134, DG152, DG154

600

ns

tOFF

Turn-Off Time

See Below

DG126, DG129, DG133,
DG134, DG152, DG154

1.6

/ks

tON

Turn-On Time

See Below

DG140, DG141, DG151, DG153

1.0

/ks

!oFF

Turn-On Time

See Below

DG140, DG141, DG151, DG153

2.5

w
!'J

w
1olio

/ks

Both Inputs VIN = 2.5V

175

mW

1

mW

All Circuits

Both Inputs VIN = 1V

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bgen characterized but arB not tested

8-13

olio

CII
I

POWER

ON Driver Power

.
I.
I.
I.
...
I.
..
9

SWITCHING

OFF Driver Power

N

!'

I

Positive Power Supply
Drain Current

POFF

..

I
UNIT

POWER SUPPLY

11(ON)

PON

.

I

CII
olio

•

.... DG126, DG129, DG133, DG134, DG140,
10

...10
I

i

.....
i
.o

DG141, DG151-154

ELECTRICAL CHARACTERISTICS (Continued)
DG151, 152, 153, 154

DG126, 129, 133, 134, 140, 141
N~.

~:~: u:r-------~_
.. <.. t-

Wr-------~

2.1...

.. <0.1.

.. 

...g
..g
.

OG151,152,153,154
ON MOOEL

~

ANALOG INPUT
'OV
3V

)

UI

ovfi -D--f>-LOGIC
INPUT

I

UI

,··h::

~

0273-12

Figure 2: Switching Times (at 25°C) (Continued)

INTERSll'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTieS OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been characterized but are not tested.

8·15

•

:: DG126, DG129, DG133, DG134, DG140,
~ DG141, DG151-154

....
g
..
i
..o
10

TYPICAL PERFORMANCE CHARACTERISTICS

(per channel)

DG151, 152, 153, 154

~

VIN THRESHOLD VB TEMPERATURE

~
CI

~

2

V- = -12V

.J

0

iii
III
c

i

Q

.J

0

...iiic

..

OFF

i!:

2 I-

~~

..
I

I

~

>

-

OFF

%

!;
...!

!;
!

VR-O
V+=+15V
~N V-=-12V

I

-

!

0

-75

-25

25

75

125

o

-75

TEMPERATURE ('C)

25

-25

75

125

TEMPERATURE ('C)

0273-13

0273-14

r!:!S(ON) VB TEMPERATURE
(Normalized to 25'C Value)
2

~

e
...
~
Q

VIN - 2.5V
-VR =0
-V+=+12V
_V-= -18V

.., ,

I

L..,.;I'

i

'"

V

~

DGI52.154

N

~I

I~S(ON) VB TEMPERATURE

-

".

I-

10

DGI51.DGI53

~

~

I

o

-75

-25

25

75

-75

125

-25

75

25

125

TEMPERATURE ('C)

TEMPERATURE ('C)

0273-16

0273-15

ALL CIRCUITS
ON SUPPLY CURRENT VB
TEMPERATURE
2.6

<
!

...z

I2.2 ! -

-

I

~j

'"~

1
~

2

-....,.

0.2

10

.E

I.. ION)

0.6

y

100

-- I"~NI
a
,. 1.0 I - l::;)

=.;

10

I',f:!

1.8
a:
Ia: 1.4 ! J

OFF SUPPLY CURRENT VB
TEMPERATURE

ID(OFF) VB TEMPERATURE
1000

I

0.1

-75 -50 -25 0 25 50 75 100 125

t±:f:jt±j:j:±tlj
25

TEMPERATURE ('C)

45

65

85

105

125

TEMPERATURE ('C)

0273-17

0273-16

45

65

65

105

12~

TEMPERATURE ('C)

0273-19

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESB. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typicalvaluss have - . characterlr«J but.,..

not-.
8·16

.D~DIL!

DG139, DG142-DG146,
DG161-DG164

Cot

!'

DUAL JFET Analog Switch

8...

GENERAL DESCRIPTION

FEATURES

Each package contains a monolithic driver with differential input and 2 or 4 discrete FET switches. The driver may
be treated as a special purpose differential amplifier which
controls the conduction state of the FET switches. The differential output of the driver sets the switches in opposition,
one pair open and the other pair closed. All switches may
be opened by applying a positive control signal to the VR
terminal.

• Each Channel Complete - Interfaces With Most
Integrated Logic
• Low OFF Power Dissipation, 1mW
• Switches Analog Signals Up to 20 Volts Peak-to-Peak
• Low rOS(ON), 10 Ohms Max on DG145 and DG146

r --

ORDERING INFORMATION
DGI39

K-

14-pln CERDIP (DGI39,142,143,144,162,164)

L - 14-pln Flat Package
P-

N
I

l'

...g

1!!0
II'

14·pln Ceramic DIP (DGI45,I46,161,163)

Temperature Range
A - MIlitary (-55"C to +125"C)
B - Commercial (-20"C to +85"C)

~-----

.
8...
.
..

Device Chip Type
0274-21

SPDT

DPDT

DG143 (rDS(ON)=80fl)
DG144 (rOS(ON)=30fl)
DG146 (rOS(ON)= 10fl)
DG161 (rOS(ON) = 15!l)
DG162 (rDS(ON)=50fl)

OG139 (rOS(ON)= 30fl)
DG142 (rDS(ON)=80!l)
DG145 (rDS(ON)= 10!l)
DG163 (rDS(ON)= 15fl)
DG164 (rOS(ON)=50fl)
11

!
.8_'~=========:~==~7
v·

0-

SW 1

~

1
O--I------O~·-+_5 SWl

.....1-------O-+..--~3 SW2
.....I--:-----o~·-+_s...

ARE FOR

v,,.., ..

LOGIC "t ..

0274-3

0274-1
11

0274-2

V·

Figure 1: Functional Diagrams (Outline Dwgs DD, FD-2, JD)

"

0274-4

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not test8(i.

8-17

•

: DG139,DG142-DG146,DG161-DG164
'P

g
I

;

g
'P

.0
...
(;
Q

ABSOLUTE MAXIMUM RATINGS
v+-v- ......................................... 36V
VS-V- ......................................... 30V
V+-VS ......................................... 30V
VS-VO ........................................ ±22V
VR-V- ......................................... 21V
V+-VR·········································17V
V+-VIN1 orVIN2 ................................. 14V
VIN1-VIN2 ...................................... ±6V

VIN1-VR ....................................... ±6V
VIN2-VR ....................................... ±6V
Power Dissipation (Note) ....................... 750mW
Current (any terminal) ........................... 30mA
Storage Temperature ................ - 65'C to + 150'C
Operating Temperature .............. - 55'C to + 125'C
Lead Temperature (Soldering, 10sec) ............. 300'C

(\I

NOTE: Dissipation rating assumes device is mounted with all leads welded or soldered to printed circuit board in ambient temperature below 70o e. For higher
temperature, derate at rate of 1OmW lOCo

,...

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional

~

operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

I

...
C5

=-

ELECTRICAL CHARACTERISTICS

g

Applied voltages for all tests: DG139, DG142, DG143, DG144, DG145, DG146 (V+ = 12V, V- = -18V, VR=O, VIN2=2.5V) and
OG161, DG162, DG163, DG164 (V+ = 15V, V- = -15V, VR=O, VIN2=2.5V). Input test condition that guarantees FET switch
ON or OFF as specified is used for output specifications.

'P

Symbol
(Note)

Parameter

Type

Test Conditions

Absolute Max Limit

Units

-55'C

25'C

125'C

VIN1 =3.0V

120

60

60

/J- A

VIN2=2.0V

120

60

60

/J- A

VIN1 =2.0V

0.1

0.1

2

/J- A

VIN2=3.0V

0.1

0.1

2

/J- A

80

80

150

n

30

30

60

n

10

10

20

n

15

15

30

n

50

50

100

n

Vo=Vs,= -10V

2

100

nA

Vs= 10V, Vo= -10V

1

100

nA

Vo=10V, Vs= -10V

1

100

nA

Vo=Vs= -10V

2

100

nA
nA

INPUT

IIN1(ON)

Input Current
All Circuits

IIN2rON)
IIN1(OFF)

Input Leakage Current

IIN2rOFF)
SWITCH OUTPUT
rOS(ON)

Drain-Source On Resistance

DG142
DG143

Vo= 10V, Is= -10mA

DG139
DG144

VIN (See Note)

DG145
DG146

Vo=10V, Is= -10mA
VIN (See Note)

DG161
DG163
DG162
DG164

Vo=7.5V, Is= -10mA
VIN (See Note)

IO(ON) + IS(ON)

Drive Leakage Current

ISrOFF)

Source Leakage Current

IOrOFF)

Drain Leakage Current

IO(ON) + IS(ON)

Drive Leakage Current

IsrOFF)

Source Leakage Current

Vs= 10V, Vo= -10V

10

1000

IO(OFF)

Drain Leakage Current

Vo= 10V, Vs= -10V

10

1000

nA

lorON) + IsrON)

Drive Leakage Current

Vo=Vs= -7.5V

2

500

nA

I~(OFF)

Source Leakage Current

Vs=7.5V, Vo= -7.5V

10

1000

nA

IO(OFF)

Drain Leakage Current

Vo=7.5V, Vs= -7.5V

10

1000

nA

Vo=Vs= -7.5V

2

500

nA

Vs=7.5V, Vo= -7.5V

2

200

nA

Vo=7.5V, Vs= -7.5V

2

200

nA

IOrON) + IsrON)

Drive Leakage Current

IS(OFF)

Source Leakage Current

lorOFF)

Drain Leakage Current

DG139
DG142
DG143
DG144
DG145
DG146
DG161
DG163
DG162
DG164

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test. VIN must be a step function with a minimum slewMrate
of 1V/f's.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUOING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicsl yalues have bun characterized but are not lest9(/.

8-18

DG139,DG142-DG146,DG161-DG164
ELECTRICAL CHARACTERISTICS
Symbol
(Note)

Parameter

(Continued)

Type

Test Conditions

Absolute Max Limit
-55°C

25°C

Units

~

125°C

N
I

POWER SUPPLY
11 (ON)
12(ON)

Positive Power Supply
Drain Current

VIN1=3V

Negative Power Supply
Drain Current

IR(ON)

Reference Power Supply
Drain Current

11 (OFF)

Positive Power Supply
Leakage Current

12(OFF)

Negative Power Supply
Leakage Current

IR(OFF)

Reference Power Supply
Leakage Current

g...

or

4.2

mA

~

!P
-2.0

mA

-2.2

mA

25

",A

-25

",A

-25

",A

See Switching Times

0.8

",s

See Switching Times

1.6

",s

VIN1=2V
All Circuits

...g
g
...

...
g
...GI
GI
I

VIN1 =VIN2.=0.8V
I

.

SWITCHING
toN

Turn-On Time

DG139. DG142
DG143. DG144
DG162. DG164

toFF

Turn-Off Time

DG139. DG142
DG143. DG144
DG162. DG164

tON

Turn-On Time

DG145. DG146
DG161. DG163

See Switching Times

1.0

",s

tOFF

Turn-Off Time

DG145. DG146
DG161. DG163

See Switching Times

2.5

",s

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test.

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATEO IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but Br9 not testsd.

8-19

.

. DG139,DG142-DG146,DG161-DG164
co

i...
...

DG161, 162, 163, 164

DG139,142,143,144,145,146

I

co

g

'''~''''f'

1,"'- 01 1'&

2S\/

1,"'OI/J.

1,"01 " S '

1, .... 01 lIS

25\/

.

OV

10.,

loti

aWl..
OUTPUT
VA 10V

OV

101'/

90'. SW112
OUTPUT
V. ·10V

ov

10"

SW314

91». SW3se

OUTPUT

OUTPUT

V.

V.lOY O\/

·IOY

Oil'
OV

10'

10"

0274-6

0274-5

0274-8

0274-7

OFF MODEL

OFF MODEL

..'

_. rT~f "'T-'
'I.......

• '000'"

1 OP~

0274-9

0274-10

ON MODEL

ON MODEL

1aU...

~ •••,.

'."y""
0274-12

0274-11

Figure 2: Switching Times Test Circuits

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
'
NOTE: All typIcsI vsluss have bHn chsractsrfz6d but BTf!J not testsd.

8-20

g
...

DG139,DG142-DG146,DG161-DG164

CoO

!'
.... OLUTI VOLT AO.
L.IVILS FOIII'WITCHINQ
WIT"ONIIIDI OPI'" AND

g...

VOL.TAGIAT'IN 13
NlieaSSAIII", TO SWITCH
WHIN ...... AT "N' IS

OTHIIII 'IO'SWITCHIC) AT

...

.2.IVAT 2S"C

'!i°e

N
I

g...

...

!II

g
...

...ell
I

o

g
...

o

5

V 1N (Pin 13)

V. N (Pins 9 or 13)

0274-14

0274-13

...ell

Figure 4

Figure 3

NOTE 1: An example of Absolute Minimum Differential Voltage, IVg-V131, is when Vg~3V and VI3~2.SV, the Vg side of the switch is ON and the V13 side of the
switch is OFF at 2S'C. Conversely, when Vg~2V and V13~2.SV, the Vg side of the switch is OFF and the V13 side of the switch is ON at 2S'C.

TYPICAL PERFORMANCE CHARACTERISTICS

(per channel)

DG139, 142, 144, 145, 146
VIN1 THRESHOLD vs TEMPERATURE

vs TEMPERATURE

ROS(ON)

IO(OFF)

vs TEMPERATURE

1000

100
G142.143

~

~

i

~
z

->

I-

.....

100
DG139.144

lJ-+-

10

DG145. '146

····or
0

10

0

.§

O~------~~~--~

-75 -50 -25

1

25 50

1

75 100 125

-75 -50 -25 0

TEMPERATURE ('C)

25 50 75 100 125

45

TEMPERATURE (CI

0274-15

65

85

105

125

TEMPERATURE tel

0274-17

0274-16

DG161, 162, 163, 164
VIN1 THRESHOLD vs TEMPERATURE

ROS(ON)

IS(OFF) vs
1000

vs TEMPERATURE

100
DG162.164

Jz

E
i

=
z
->

....

..-r-

10

DG161.163

:§

-75 -50 -25 0

25 50

75 100 125

TEMPERATURE ('C)

....

100

9

O~------~~~~~

TEMPERATURE

,;;:

::

1

-75 -50 -25 0

25

50 75 100 125

TEMPERATURE I'C)

~

F

~

10

.A'

9

2

.....

DG162,164

0.1
25

45

65

85

105

125

TEMPERATURE ('C)

0274-19

0274-18

«oS

DG161.163

0274-20

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE ANO SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not test9(/.

8-21

•

. DG180-191
High-Speed Driver With

D~DlL

Gi

~

= JFET Switch

8

GENERAL DESCRIPTION

FEATURES

The DG180 thru DG191 series of analog gates consist of
2 or 4 N-channel junction-type field-effect transistors (JFET)
designed to function as electronic switches. Level-shifting
drivers enable low-level inputs (0.8 to 2V) to control the ONOFF state of each switch. The driver is designed to provide
a turn-off speed which is faster than turn-on speed, so that
break-before-make action is achieved when switching from
one channel to another. In the ON state, each switch conducts current equally well in both directions. In the OFF condition, the switches will block voltages up to 20V peak-topeak. Switch-OFF input-output isolation is 50dB at 10MHz,
due to the low output impedance of the FET-gate driving
circuit.

• Constant ON-Resistance for Signals to ± 10V
(DG182, 185, 188, 191), to ±7_5V (All Devices)
• ± 15V Power Supplies
• <2nA Leakage From Signal Channel In Both ON and
OFF States
• TTL, DTL, RTL Direct Drive Compatibility
• lon, t off<150ns, Break-Before-Make Action
• Cross-talk and Open Switch Isolatlon>50dB at
10MHz (750 Load)
• JAN 38510 Approved
DG

181

ORDERING INFORMATION
Part
Number

Type

rOS(on)
(Max)

DG180
DG181
DG182
DG183
DG184
DG185
DG186
DG187
DG188
DG189
DG190
DG191

DualSPST
DualSPST
DualSPST
Dual DPST
Dual DPST
Dual DPST
SPDT
SPDT
SPDT
DualSPDT
DualSPDT
DualSPDT

10
30
75
10
30
75
10
30
75
10
30
75

X

Y
LpACKAGE
A - 10-PIN METAL CAN
L -14-PIN FLAT PACK
P - CERAMIC DIP
(Special Order Only)
K-CERDIP
TEMPERATURE
A - MILITARY (-55'Cto + 125'C)
B -INDUSTRIAL(-20'Cto +85'C)

' - - - - - DEVICE TYPE
'-------DRIVER

ONE AND TWO CHANNEL SPOT AND
SPST CIRCUIT CONFIGURATION

TWO CHANNEL DPST CIRCUIT CONFIGURATION

Y+

Y+

YL

H--.....=-~s
D

II

I I .........'--_ _4--_+_--'

QNDV-

00186/187/186 SHOWN

GND

0275-1

v-

OG183/184/185 SHOWN
0275-2

Figure 1: Functional Diagram (Typical Channel)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have bgen characterized but are not tested.

8-22

aD~Dn.

DG180-191

.
...

g
CIII

oI

ABSOLUTE MAXIMUM RATINGS
v+-v- ......................................... 36V
v+-vo ......................................... 33V
Vo-V- ......................................... 33V
vo-vs ........................................ ±22V
VL-V- ......................................... 36V
VL-VIN··········································.8V
VL-GND ......................................... 8V
VIN-GND ........................................ 8V

GND-V- ....................................... 27V
GND-VIN ....................................... 20V
Current(S or D) See Note 3 ..................... 200mA
Storage Temperature ................ -65·C to + 150·C
Operating Temperature .............. -55·C to + 125·C
Power Dissipation" ............... 450 (TW), 750 (FLAT),
825(DIP)mW
Lead Temperature (Soldering, 1Osee) ............. 300·C

'Device mounted with all leads welded or soldered to PC board. Derate 6mWI'C (TW); 10mWI'C (FLAT); 11 mW/"C (DIP) above 75"C.

NOTE: Stresses above those listed under "Abso/ute Maximum Ratings" may cause permanent damage to the devics. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

DUAL SPST (DG180, 181, 182)
Flat Package

Metal Can Package

s.
0,

CERDIP'

14

$,

S.

0,

o.

NC

NC

IN,

IN,

YL

0275-3

(OUTLINE DWG TO-100)

NC

NC

IN,

IN,

y+

y-

aND

YL

0275-4

(OUTLINE DWG FO-2)
DUAL DPST (DG183, 184, 185)
Flat Package

0275-5

(OUTLINE DWG JD)
CEROIP'

14

54

5,

D,

D.

D2

D.

5 •.

5,

IN,

IN,

y+

YaND

V,

0275-6
0275-7

(OUTLINE DWG FO-2)

(OUTLINE DWG JE)

Figure 2: Pin Configurations and Switching State Diagram

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOT£: All typical values hilve bSffm characterized but are not tested

8-23

U»

... DG180-191
.
H

.D~Dn..

0

I

0

SPDT (00186, 187, 188)
Flat Package

W

Metal Can Package

CERDlp·

,.

Do

NC

NC

Ne

.,

YL

0275-8

(OUTLINE DWG TO·100)

NC

0,

Do

IN

He

Y+

Y-

52

eND

YL

0275-9

0275-10

(OUTLINE DWG FD·2)

(OUTLINE DWO dO)

DUAL SPDT (D0189, 190, 191)
CERDlp·

Flat Package

,.
IG
NC

o.c:::::r:...... ..,..c:~

D.

y+

112C:::::IJf-+-...J

.,

(SUBSTRATE)

1112

IN,

v+

Y-

02 ___..--

0,

'NC
s,
D,

0,

0275-12

eND

..

0275-11

·Side braze ceramic package available as special order only. Consult factory.
(OUTLINE DWG FD-2)
(OUTLINE DWG dE)
Figure 2: Pin Configurations and Switching State Diagram (Cont.)

ELECTRICAL CHARACTERISTICS
Parameter

Device No.

(V+ = + 15V, v- = -15V, VL = 5V, Unless Noted)

Test Conditions
(Note 1)

BSerle.

ASerles

Units

-S5"C +25"C +12SD C -20"C +25"C +85"C

SWITCH
IS(off)

IO(off)

±1

100

±5

100

±(10)

(1000)

(15)

(300)

DG181, 184, 187, 190 Vs=7.5V, Vo= -7.5V
(DG180, 183, 186, 189) VIN="OFF"
DG182, 185, 188, 191 VS=10V, Vo= -10V
VIN="OFF"
DG181,182,184,185 Vs=10V, Vo= -10V, V+ =10V
187,188,190,191
(DG180, 183, 186, 189) V-= -20V, VIN="OFF"

±1
±(10)

100
(1000)

±5
(15)

100
(300)

nA

±1

100

±5

100

nA

±1

100

±5

100

±(10)

(1000)

(15)

(300)

DG181, 184, 187,190 Vs=7.5V, Vo= -7.5V
(DG 180, 183, 186, 189) VIN="OFF"
DG182,185,188,191 Vs=10V, Vo= -10V
VIN="OFF"

±1
±(10)

100
(1000)

±5
(15)

100
(300)

nA

±1

100

±5

100

nA

DG181,182, 184, 185 Vs=10V, Vo= -10V, V+ =10V
187,188,190,191
(DG180, 183, 186, 189) V-= -20V, VIN="OFF"

nA

nA

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOT1i:AHtypico/_""""bHn_butlUOnot-.

8·24

.U~Ul!..

DG180-191
ELECTRICAL CHARACTERISTICS
Parameter

(V+ = +15V, V- = -15V, VL =5V, Unless Noted) (Continued)

Test Conditions
(Note 1)

Device No.

A Series

BSerles

Units

- 55'C + 25'C + 125'C - 20'C + 25'C + 85'C

SWITCH (Continued)
10(on) + IS(on) DG180, 181,183,184
186,187,189,190

Vo=Vs= -7.5V, VIN= "ON"

DG182, 185,188,191

Vo=Vs= -10V, VIN="ON"

IINL

ALL

VIN=OV

IINH

ALL

VIN=5V

±2

-200

-10

-200

nA

±2

-200

-10

-200

nA

-250

-250

-250

-250

,..A

10

20

10

20

,..A

INPUT
-250

-250

DYNAMIC
Ion

10n Switches

300

30n Switches

150

180

250

300

1on Switches

250

300

30n and 75n Switches

130

75n Switches
toff

See switching time test circuit

DG181, 182, 184, 185, Vs= -5V, 10=0, f=1MHz
187,188,190,191
Vo= +5V, Is=O, f=1MHz
COtoff)
(DG180, 183, 186189)
VO=VS=O, f= 1MHz
COton) + CSton
OFF Isolation
RL = 75n, CL = 3pF

350
ns

150
9 typical (21 typical)

CS(off)

6 typical (17 typical)

pF

14 typical (17 typical)
Typically> 50dS at 1OMHz (See Note 2)

SUPPLY
1+

1-

DG180,181,182,189
190,191

1.5

DG183, 184, 185

0.1

0.1

DG186, 187, 188

0.8

0.8

-5.0

-5.0

-4.0

-4.0

-3.0

-3.0

DG180, 181,182,189
190,191
DG183, 184, 185

VIN=5V

DG186, 187, 188
IL

IGNO
1+

1-

DG180,181,182,183
184,185,189,190,191

4.5

4.5

DG186, 187, 188

3.2

3.2

ALL

-2.0

-2.0

DG180,181,182,189
190,191

1.5

1.5

DG183, 184, 185

3.0

3.0

DG186, 187, 188

0.8

0.8

-5.0

-5.0

-5.5

-5.5

-3.0

-3.0

4.5

4.5

DG180, 181, 182, 189
190,191
DG183, 184, 185

VIN=OV

DG186, 187, 188
IL

DG180, 181, 182, 183
184,185,189,190,191
DG186, 187, 188

IGNO

1.5

ALL

3.2

3.2

-2.0

-2.0

mA

NOTES 1. See Switching State Diagrams for VIN "ON" and VIN "OFF" Test CondHions.
2. Off Isolation typically> 55dB at lMHz for DG180, 183, 186, 189.
3. Saturation Drain Current for DG180, 183, 186, 189 only, typically 300mA (2ms Pulse Duration). Maximum Current on all other devices (any terminal)
30mA.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTe: All typical values have been characterized but are not tested.

8·25

g
...
?CD

...

...
U)

.D~Ou..

;... DG180-191
I

...~

g

ELECTRICAL CHARACTERISTICS
Device
Number

Conditions (Note 1)
V+ = l5V, V- = -l5V, VL =5V

MAXIMUM RESISTANCES (rOS(ON) MAX) (Continued)
Industrial
Temperature

Military Temperature
-55"C

+ 25°C

+ 125°C

-20"C

+25"C

Units
+ 85°C

OG180

Vo=-7.5V

10

10

20

15

15

25

0

OG181

Vo=-7.5V

30

30

60

50

50

75

0

OG182

Vo= -10V

75

75

100

100

100

150

0

OG183

Vo=-7.5V

10

10

20

15

15

25

0

OG184

Vo= -7.5V

30

30

60

50

50

75

0

OG185

Vo=-10V

75

75

150

100

100

150

0

OG186

Vo= -7.5V

10

10

20

15

15

25

0

OG187

Vo= -7.5V

30

30

60

50

50

75

0

OG188

Vo=-10V

75

75

150

100

100

150

0

OG189

Vo=-7.5V

10

10

20

15

15

25

0

OG190

Vo=-7.5V

30

30

60

50

50

50

0

OG191

Vo= -10V

75

75

150

100

100

150

0

18= -lOrnA
VIN="ON"

APPLICATION HINT (for design only): Normally the minimum signal handling capability of the DGleO through DG191 family Is 20V peak.to·peak for the 7S0
switches and ISV peak.to-peak for the 100 and 300 (refer 10 and IS tests above). For other Analog Signals. the following guidelines can be used: proper switch
turn-off requires that V- ,;;VANALOO(peak) - Vpwhere Vp = 7.SVforthe 100 AND 300 switches and Vp = S.OVfor 750 switches e.g., -10V minimum (-peak)
analog signal and a 750 switch (Vp = 5V), requires that V- ,;; -10V -SV = -15V.

Logic Input for "OFF" to "ON" Condition (00180/1811182 Shown)
LOOIC 3V
INPUT
Ir c

,

I~
~:

hal

§~
c~

o~

! .... '
25

': ~

DflAiN VOLTAGE (VOLlSI

0276-8

:0

jz

.:

-~

.,
15
15 10S t25
T - TEMPERATURE (,CI

0

".
,

0,'

..

~::

i,'i

-.- ..... --~
~+-->--.--~

.. .

0.01

; -t-T"'~--"IS

IS

,,,.

T - TEMPERATURE

('c)

".
0276-11

0276-10

APPLICATIONS
Using the VREF Terminal

V+
Supply
(V)

The DG200 has an internal voltage divider setting the
TTL threshold on the input control lines for V + equal to
+ 15V. The schematic shown here with nominal resistor values, gives approximately 2.4V on the VREF pin. As the TTL
input signal goes from +0.8V to +2.4V, 01 and 02 switch
states to turn the switch ON and OFF.
If the power supply voltage is less than + 15V, then a
resistor must be added between V+ and the VREF pin, to
restore + 2.4V at VREF. The table shows the value of this
resistor for various supply voltages, to maintain TTL compatibility. If CMOS logic levels on a + 5V supply are being
used, the threshold shifts are less critical, but a separate
column of suitable values is given in the table. For logic
swings of - 5V to + 5V, no resistor is needed.
In general, the "low" logic level should be <0.8V to prevent 01 and 02 from both being ON together (this will
cause incorrect switch function). With open collector logic,
and a low value of pull-up resistor, the logic "low" level can
be above 0.8V. In this case, INTERSIL can supply parts with
thresholds> 1.5V, allowing the user to define the "low"
as < 1.5V (consult factory). The VREF point should be set at
least 2.6V above this "low" state, or to>4.1V. An external
resistor of 27kO between V + and VREF is required, for a
+ 15V supply.

TTL
Resistor
(kO)

CMOS
Resistor
(kO)

-

+15
+12
+10

-

-

100
51
(34)
(27)
18

+9
+8
+7

-

34
27
18

Y+(+15V)

--l
31kO

01

R.xt

VAEF

II- r-<>6ka

.,...
PROTECTION
INPUT RESISTOR

"n

'f
.t" 02
.,...

0276-12

Figure 6_

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

8-31

•

i DG201

g Quad SPST
CMOS Analog Switch
GENERAL DESCRIPTION

FEATURES

The DG201 solid-state analog switches are designed using an improved, high-voltage CMOS monolithic technology.
They provide performance advantages not previously available from solid-state switches. Destructive latch-up of solidstate analog gates has been eliminated by INTERSIL's
CMOS technology.
The DG201 is completely specification and pin-out compatible with the industry standard device.

• Switches Greater Than 28Vp_p Signals With
Supplies
• Break-Before-Make Switching tOil = 250ns,
ton = Typically 500ns
• TTL, OTL, CMOS, PMOS Compatible
• Non-Latching With Supply Turn-Off
• Complete Monolithic Construction
• Industry Standard (OG201)

± 15V

ORDERING INFORMATION
Industry Standard
Part Number

Temperature
Range

Package

DG201AK

-55·C to + 125·C

16-Pin CERDIP

DG201BK

- 25·C to + 85·C

16-Pin CERDIP

DG201CJ

O·C to +70·C

16-Pin Plastic DIP

s,
v + (SUBSTRATE)

GATE

PROTECTION
RESISTOR

INPUT

0277-2

0277-1

Figure 1: Functional Diagram
(% DG201)
Switch Open For Logic "1" Input

Figure 2: Pin Configuration
(Outline dwgs JE, PEl
DUAL-IN-LiNE PACKAGE

INTERSll'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical values have been characterized but are not tested.

8-32

IIJD~DI!..

DG201

8
...o
II)

ABSOLUTE MAXIMUM RATINGS
v+ to v- .....................................
v+ to Vo ......................................
VotoV- ......................................
Vo to Vs .......................................
VREFtoV- ....................................
VREF to VIN ....................................
VREF to GND ..................................

<3SV
<30V
<30V
<2SV
<33V
<30V
<20V

VIN to GND .................................... <20V
Current (Any Terminal) ........................ <30mA
Storage Temperature ................ -S5'Cto + 150'C
Operating Temperature .............. -55'C to + 125'C
Lead Temperature (Soldering, 10sec) ............. 300'C
Power Dissipation ............................. 450mW
Derate SmW I'C Above 70'C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress raUngs only and functional
opersUon of the device at these or any other conditions above those indicated in the opersUonal sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extBndBd periods may affect device reliability.

DG201 ELECTRICAL CHARACTERISTICS
Per Channel
Symbol

Characteristic

(TA=25'C,V+=+15V,V-=-15V)
MinIMax Limits

Test
Conditions

Military
-55'C

+ 25'C

Commercial
+ 125'C Q'C

+ 25'C

Units

+ 70'CI + 85'C

IIN(ON)

Input Logic Current

VIN = O.SV See Note 1

10

±1

10

±1

±1

10

p.A

IIN(OFF)

Input Logic Current

VIN=2.4V See Note 1

10

±1

10

±1

±1

10

p.A

Is=10mA
VANALOG= ±10V

SO

SO

125

100

100

125

0

ROS(ON) Drain-Source On
Resistance
ROS(ON) Channel to Channel
ROS(ONL Match

25
(typ)

30
(typ)

0

VANALOG Analog Signal
Handling Capability

± 15 (typ)

± 15 (typ)

V

IO(OFF)

Switch OFF Leakage VANALOG= -14Vto + 14V
Current

±1

100

±5

100

nA

IS(OFF)

Switch OFF Leakage VANALOG= -14Vto + 14V
Current

±1

100

±5

100

nA

±2

200

±5

200

nA

Switch ON Leakage Vo=Vs= ±14V
IO(ON)
+IS(ON) Current

ton

toft

Switch "ON" Time
See Note 2

RL = 1kO, VANALOG
=-10Vto +10V
See Figure 3

1.0

1.0

p.s

Switch "OFF" Time
See Note 2

RL = 1kO, VANALOG
= -10V to + 10V
See Figure 3

0.5

0.5

p's

15 (typ)

20 (typ)

mV

54
(typ)

50
(typ)

dB

Q(INJ.)

Charge Injection

See Figure 4

OIRR

Min. Off Isolation
Rejection Ratio

f=1MHz, RL =1000,
CL:S:5pF
See Figure 5

1+0

+ Power Supply
Quiescent Current

VIN=OVto5V

1-0

- Power Supply
Quiescent Current

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

2000

1000

2000

2000

1000

2000

p.A

2000

1000

2000

2000

1000

2000

p.A

One Channel Off
54
(typ)

50
(typ)

dB

NOTE 1: Typical values are for design aid only, not guaranteed and not subject to production testing.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vsluss hsvs been characteriZ9d but are not testsd

S-33

...o
&'II

g

DG201
TEST CIRCUITS

)'h

ANALOG INPUT

3V

9V-O-

ANALOG INPUT

~ haUl

INPUT

r

10 PF

f"2Kr
":"

":"

,vil..~-r~.:'::;~ -~ r

2Vpp @1MHz

LOGIC INPUT

(NO~_

~voo,

i

"'-J

1KO

"::"

~

vo"'

'OOJl

0277-5

0277-4

":"

0277-3
(Note 2)

Figure 4

Figure 3

Figure 5

NOTE 2: All channels are turned off by high "1" logic inputs and all channels are turned on by low "0" inputs; however O.BV to 2.4V describes the min. range for
switching properly. Peak input current required for transition is typically -120,uA. Pull down resistor, if used, S 2Kfl.

TYPICAL PERFORMANCE CHARACTERISTICS

V+=+15V
V-=-15V

100

D

100

.\

II
50

12S'C

po

25' C

po

-SS'C

C

0

5

Y+
Y+
C - Y+
o I- 0 - Y +

do10

A

r- A r- B -

o
-15 -10 - 5

T

50

= +is";, Y- = -ISY
= +12V, Y- = -12Y
= + lOY, Y- = -lOY
= +8V, Y- = -8Y

-15 -10 - 5 0
5 10 15
Vo - DRAIN VOLTAGE (VOLTS)

15

Vo - DRAIN VOLTAGE (VOLTS)

0277-7

0277-6

1 10~.

10

mi
~B

....

Zu:

I~

..~ ~I-"B'B'MI

§~

§

0.1

IL

0.1

Z

o

0.011.....JL.....J.-l..-L.-L...I.-..I-l..-1......J
25 45
85
85 105 125

0.01
25

T - TEMPERATURE ('C)

45

85

85

105

125

T - TEMPERATURE ('C)

0277-8

0277-9

INTERSIL'S SOLE AND eXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been characterized but are not tested.

8-34

DG201
APPLICATIONS
Using the VREF Terminal

Y+
Supply
(Y)

The DG201 has an internal voltage divider that sets the
TTL threshold on the input control lines for V+ = 15V. The
schematic is shown here, with nominal resistor values, giving approximately 2.4V on the VREF pin. As the TTL input
signal goes from + 0.8V to + 2.4V, 01 and 02 switch states
to turn the switch ON and OFF.
If the power supply voltage is less than + 15V, then a
resistor needs to be added between V+ and VREF pin, to
restore + 2.4V at VREF. The table shows the value of this
resistor for various supply voltages, to maintain TTL compatibility. If CMOS logic levels with a + 5V supply are being
used, the threshold shifts are less critical, but a separate
column of suitable values is given in the table. For logiC
swings of -5V to +5V, no resistor is needed.
In general, the "low" logic level should be  1.5V(consult factory). The VREF point should
be set at least 2.6V above this "low" state, or to > 4.1 V. An
external resistor of 27kfi and VREF is required, for a + 15V
supply.

TTL

CMOS

Resistor

Resistor

(kn)

(kfi)

-

-

+15
+12
+10
+9
+8
+7

100
51
(34)
(27)
18

34
27
18

Y· (+15Y)

ObL

~-J Rea'
31kO

VREF

L~'

8ka

":"

'f

-,I:" 02

~"

PROTECTION
INPUT RESISTOR

":"

0277-10

Figure 6

•
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTieS OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but 81'8 not tested.

8-35

g DG201A/DG202

§ Quad Monolithic SPST CMOS
c... Analog Switches
~

g

GENERAL DESCRIPTION

FEATURES

The DG201 A (normally open) and DG202 (normally
closed) quad SPST analog switches are designed using Intersil's new 44V CMOS process. These bidirectional
switches are latch-proof and feature break-before-make
switching. Designed to block signals up to 30V peak-topeak in the OFF state, the DG201A/DG202 offer the advantages of low on resistance (';;;1750), wide input signal
range (± 15V) and provide both TTL and CMOS compatibility.
The DG201A1DG202 are specification and pin-out compatible with the industry standard devices.

• ± 15V Input Signal Range
•
•
•
•

Low ROS(on) (';;; 1750)
TTL, CMOS Compatible
Latch Proof
True Second Source
• 44V Maximum Supply Ratings
• Logic Inputs ~ccept Negative Voltages

ORDERING INFORMATION
Part Number

Temperature Range

DG201AAK

- 55'C to + 125'C

16-Pin CERDIP

DG201ABK

- 25'C to + 85'C

16-Pin CERDIP

DG201ACK

O'Cto +70'C

16-Pin CERDIP

DG201ACJ

O'Cto +70'C

16-Pin Plastic DIP

DG202AK

- 55'C to + 125'C

16-Pin CERDIP

DG202BK

-25'Cto + 85'C

16-Pin CERDIP

DG202CK

O'Cto +70'C

16-Pin CERDIP

DG202CJ

O'Cto +70'C

16-Pin Plastic DIP

DG201A

Package

DG202

"

"

IN,

Dual·ln·Line Package

IN,

"
"

"

"

IN,

IN,

"

"
"

"
IN,

IN,

"
"

"
"

IN,

IN,

0096-3

Top View

"

"

0096-1

Figure 2: Pin Configuration

0096-2

Four SPST Switches Per Package'

Truth Table

Logic "0" os: O.BV
Logic "1" ., 2.4V

Logic

DG201A

DG202

0
1

ON
OFF

OFF
ON

'Switches Shown for Logic "1" Input

Figure 1: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

307010-001

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

8-36

DG201A/DG202
ABSOLUTE MAXIMUM RATINGS
v+ toV- ....................................... 44V
v- to Ground .................................. -25V
Vin to Ground (Note 1) ........... (V- - 2V), (V+ + 2V)
Vs or VD to V+ (Note 1) ................ + 2, (V- - 2V)
Vs or VD to V- (Note 1) ................ -2, (V+ + 2V)
Current, Any Terminal Except S or D .............. 30 mA
Continuous Current, S or D ...................... 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% duty cycle max) ........... 70 mA
Operating Temperature
C Suffix .............................. O'C to + 70'C
B Suffix ........................... - 25'C to + 85'C
A Suffix .......................... - 55'C to + 125'C

Storage Temperature
C Suffix .......................... - 65'C to + 125'C
A & B Suffix ....................... -65'C to + 150'C
Lead Temperature (Soldering, lOs) ............... 300'C
Power Dissipation·
CERDIP Package·· ......................... 900 mW
Plastic Package··· ......................... 470 mW
·Device mounted with all leads
soldered or welded to PC board.
"Derate 12 mW/,C above 75'C
···Derate 6.5 mW/,C above 25'C
NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These afB stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the s~ifications is not

implied. Exposure to absolute maximum rating condHions fOf.' eXtended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

v+

=

15V, v-

=

-15V, GND

= OV, TA =

DG201AA/DG202A
Symbol

Parameter

Test Conditions
Min

.

Typ
Max
(Note 2)

25'C

DG201AB,C/DG202B,C
Min

Typ
(Note 2)

Units
Max

SWITCH
VANALOG Analog Signal
Range

-15
VD = ± 10V, Vin = 0.8V (DG201 A)
Is = 1 mA, Vin = 2.0V (DG202)

RDS(on)

Drain Source
On Resistance

IS(oll)

Source OFF
Vin = 2.4V
Leakage Current (DG201A)
Vin = 0.8V
Drain OFF
(DG202)
Le~~~ge Current

Vs

= 0.8V

VD

ID(off)

ID(on)
(Note 4)

Drain ON

Vin

Lea~age Current (DG201A)

Vs
Vs
Vs

Vin = 2.4V
VD
(DG202)

= 14V, VD = -14V
= -14V, VD = 14V
= -14V, VD = 14V
= 14V, VD = -14V
= Vs = 14V

IINL

115

175

0.01

1.0

-1.0

-0.02

-1.0

-0.02

0.01

0.1

-15

15

V

115

200

n

0.01

5.0

-5.0

-0.02

-5.0

-0.02

1.0

0.01

1.0

0.1

5.0

nA

nA

5.0
p.A

=

Vs

=-

14V

-1.0

-0.15

-1.0

-0.0004

-5.0

-0.15

-1.0

-0.0004

,

INPUT
IINH

15

Input Current with Vin
Voltage High
Vin
Input Current with Vin
Voltage Low

= 2.4V
= 15\1
= OV

0.003
-1.0

-0.0004

1.0

0.003
-1.0

p.A
1.0

-0.0004

p.A

NOTE 1: Signals on Vs, Vo, or Vln exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2: Typical values are for design aid only, not guaranteed and not subject to production testing.
3: The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data sheet.
4: 10(on) is leakage from driver into ON switch.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OaUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHEA WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

8·37

•

o

DG201A/DG202

8

ELECTRICAL CHARACTERISTICS

&II
&II

.

C
o

&II

8

V+ = 15V, v- = -15V, GND = OV, TA = 25°C (Continued)
DG201AA/DG202A

Symbol

Parameter

Test Conditions

Min

Typ
Max
(Note 2)

DG201AB, C/DG202B, C
Min

Typ
(Note 2)

Max

Units

DYNAMIC
ton

Turn-ON Time

toll

Turn-OFF Time

Q

Charge Injection

CL = 1000 pF, Rs = 0, Vs = OV

20

20

pC

CS(OIl)

Source OFF
Capacitance

f = 140 kHz, Yin = 5V,
Vs = OV

5.0

5.0

pF

CO(oll)

Drain OFF
Capacitance

f = 140 kHz, Yin = 5V,
Vo = OV

5.0

5.0

pF

Channel ON
Capacitance

f = 140 kHz, Yin = OV,
Vs.= Vo = OV

16

16

pF

70

70

90

90

COlon)
CSlon)

+

DIRR
CCRR

See Figure 3

OFF Isolation

Yin = 5V, ZL = 750
Crosstalk (Channel Vs = 2.0V, f = 100 kHz
to Channel)

480

600

480

600

370

450

370

450

ns
ns

dB

SUPPLY
1+

Positive Supply
Current

1-

0.9

2

0.9

2

mA

All Channels ON or OFF

Negative Supply
Current

-1

-1

-0.3

-0.3

mA

TA = over operating temperature range
SWITCH
VANALOG Analog Signal
Range

-15

ROS(on)

Drain-Source
ON Resistance

Vo = ± 10V, Yin = 0.8V (DG201A)
Is = 1 mA, Yin = 2.4V (DG202)

IS(oll)

Source OFF
Leakage Current

Yin = 2.4V Vs = 14V, Vo =
(DG201A) Vs = -14V, Vo
Yin = 0.8V
Vs = -14V, Vo
(DG202)
Vs = 14V, Vo =

10(011)

10(on)
(Note 4)

Drain OFF
Leakage Current
Drain ON
Leakage Current

15
250

-14V

100

= 14V -100
= 14V

15

V

250

0

100

nA

-100
100

-14V -100

Yin = 0.8V Vo = Vs = 14V
(DG201A)
Yin = 2.4V Vo = Vs = - 14V
(DG202)

-15

100

nA

-100
200

200
p.A

-200

-200

INPUT
IINH

IINL

Input Current with
Voltage High

Yin = 2.4V

Input Current with
Voltage Low

Yin = OV

-10

Yin = 15V

-10
10

-10

p.A
10

-10

p.A

NOTE 1: Signals on VS. VD. or Vin exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2: Typical values are for design aid only. not guaranteed and not subject to production testing.
3: The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data sheet.
4: ID(on) is leakage from driver into ON switch.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CCNDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

8-38

DG201A/DG202
TEST CIRCUITS
Logic "0"

LOGIC' 3V
INPUT

tr < 20 ns

~

SW ON

50%

t f < 20 ns

SWITCH V
INPUT S
SWITCH
OUTPUT

0

-itl-c-..;;;;;;;;;;;;;;;;;;;;;;;+;;;;;;;;;:-Vo
0.9

Vo

0.9

_-+_..1

torr

0096-4

'Logic Shown for DG201A, Invert for DG202.

Vo ~ Vs=--:R~L_ _
RL

+

ROS(on)

SWITCH
INPUT Sl

SWITCH
OUTPUT

Vs = +2Vo--I------<"r

~-+~~~~~DVO

1

CL
35PF

(REPEAT TEST FOR IN 2 ,IN 3 AND IN 4 )

0096-5

Figure 3: ton and toff Switching Test

ON

',-__OF_F_.JF
0096-6

6. Vo = measured voltage error due to charge injection

The error voltage in coulombs is '

-,.....-o Vo

I\)

"'-I- 50dB at
10MHz (750 Load)

CD

DGM

181

ORDERING INFORMATION
Type

DualSPST

Dual DPST

Dual SPDT

Standard
Part
Number

rDS(on)
Max
at 25'C

DGM181BX
DGM182AX
DGM182BX
DGM184BX
DGM185AX
DGM185BX
DGM190BX
DGM191AX
DGM191BX

50
50
75
50
50
75
50
50
75

!IJ

A

I

A

L

A-1().Pin Metal Can
K-CalBmic DIP
PaCkage
J-Ep<>xyDIP

Temperature Range
A-Mililary (-55"C 10 +125"C)
B-Industrial (-20"C 10 +85"C)

' - - - - - - - Device Type
' - - - - - - - - - - CMOS Analog Driver
0279-14

•

r--~~---~--~----~V+

""d. . t
s
0279-1

NOTE: % of DGM182

Figure 1: Functional Diagram (Typical Channel)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bgen characterized but are not tested.

.......
....
K

8-49

;; DGM18i,-186
)o DGM189-191

..
:.
g
..
CD

DUAL SPST (DGM181, 182)
Metal Can Package

Dual-In-Llne Package

iii
CD
I

CD

i

g

D,
IN,

0279-4

(OUTLINE DWGS JD, PO)

0279-2

(OUTLINE DWG T00100)
SWITCH STATES ARE FOR LOGIC "1" INPUT

DUAL DPST (DGM184, 185)
Dual-In-Llne Package

0279-6

(OUTLINE DWGS JE, PEl
SWITCH STATES ARE FOR LOGIC "1" INPUT

DUAL SPDT (DGM190, 191)
CERClp·

0279-11

(OUTLINE DWGS JE, PEl
SWITCH STATES ARE FOR LOGIC "1" INPUT

Figure 2: Pin Configuration and Switching State Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,

NOTE: AU typical vs/u8s havs been chRrsctBrIz9d but are not tesfBd.

8-50

1Il0~OR.

DGM181-186
DGM189-191

CD
I

v+-v- .........................................
V--Vo .........................................
Vo-V- .........................................
Vo-Vs ..........................................
VL-V- .........................................
VL-VIN .........................................
VL -VGNO .......................................
VIN-VGNO .......................................
GND-V- .......................................

GND-VIN ....................................... 20V
Currenl(Any Terminal) ........................... 30mA
Storage Temperature ................ -65'C to + 150'C
Operating Temperature .............. - 55'C to + 125'C
Lead Temperature (Soldering, 10sec) ............. 300'C
Power Dissipation' ............... 450 (TW), 750 (FLAT),
825(DIP)mW

36V
33V
33V
28V
36V
30V
20V
20V
27V

• Device mounted with all leads welded or soldered to PC board. Derate
SmWI'C (TW); 1OmWI'C (FLAT); 11 mW I'C (DIP) above 7S·C.

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to /he device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V+ = + 15V, v- = -15V, VL =5V, unless noted)

Test Conditions
(Note 1)

Device No.

BSerles

A Series

Units

-55'C +25'C + 125'C -20'C + 25'C + 85'C

SWITCH
DGM181, 184, 190

Vs=7.5V, Vo= -7.5V
VIN="OFF"

±1

100

±2.0

200

nA

DGM182, 185, 191

Vs=10V, Vo= -10V
VIN="OFF"

±1

100

±2

200

nA

DGM181, 184, 190

Vs=7.5V, Vo= -7.5V
VIN="OFF"

±1

100

±2

200

nA

DGM182, 185, 191

Vs=10V, Vo= -10V
VIN="OFF"

±1

100

±2

200

nA

DGM181, 184, 190

Vo=Vs= -7.5V, VIN="ON"

±2

±200

±5

500

nA

DGM182, 185, 191

Vo=Vs= -10V, VIN="ON"

±2

±200

±5

500

nA

IINL

ALL

VIN=OV

±1.0

20

10

20

p.A

IINH

ALL

VIN=5V

±1.0

20

10

20

p.A

ton

DGM181, 184, 190
DGM182, 185, 191

See switching time test circuit

toft

ALL

IS(oft)

lo(off)

lo(on) + IS(on)
INPUT

DYNAMIC

CS(oft)

DGM181, 182, 184, 185, VS= -5V, 10=0, f=1MHz

CO(off)

190,191

Co(on) + CS(on)
OFF Isolation

450

500

250

275

ns

5pF typical

Vo= +5V, Is=O, f=1MHz

6pF typical

Vo=Vs=O, f=1MHz

11 pF typical

pF

Typically>50dB at 10MHz

RL = 750., CL = 3pF

SUPPLY
1+

ALL

1-

ALL

IL
IGNO
1+
1-

ALL

IL

ALL

IGNO

ALL

.....

I:

ABSOLUTE MAXIMUM RATINGS

Parameter

g

10

10

100

100

10

10

100

100

ALL

10

10

100

100

ALL

10

10

100

100

ALL

10

10

100

100

10

10

100

100

10

10

100

100

10

10

100

100

VIN=5V

VIN=OV

p.A

Note: 1. See Switching State Oiagrams for YIN and YIN "OFF" Test Conditions.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHAll BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE AJllypicaJ values have been characterized but are not tested.

8-51

CD

!II

g

..

I:
CD

....
G
I

G

Gi DGM181-186

'i DGM189-191
G)
Ill)

i

g
,,;

ELECTRICAL CHARACTERISTICS
Device
Number

Conditions (Note 1)
V+ = 1SV, V- = -1SV,VL = SV

Ill)

I
'P'
'P'

:Ii

g

DGM181
DGM182
DGM184
DGM185
DGM190
DGM191

Vo= -7.5V
Vo= -10V
Vo= -7.5V
Vo= -10V
Vo=-7.5V
Vo= -10V

Is= -10mA

Industrial
Temperature

Military Temperature
-SS'C

'P'

Ill)

MAXIMUM RESISTANCES rOS(ON)

+2S'C

Units

+ 12S'C

-20'C

+2S'C

+8S'C

50
75
50
75
50
75

50
75
50
75
50
75

75
100
75
100
75
100

-

-

-

50
30
50
30
50

50
30
50
30
50

75
60
75
60
75

0
0
0
0
0
0

APPLICATION COMMENT: The charge injection in these switches is 01 opposite polarity to that of the standard OG180 family. but considerably smalier.

SWITCHING TIME TEST CIRCUIT
output with switch on. Feedthrough via gate capacitance
may result in spikes at leading and trailing edge of output
waveform.

Switch output waveform shown for VS= constant with
logic input waveform as shown. Note that Vs may be + or
- as per switching time test circuit. Vo is the steady state

LOGIC
INPUT
tr< 10ns
tl< 10ns

3V

SWITCH
INPUT

Vs

SWITCH
OUTPUT

0

0.9Vo

O.9Vo
O.tVo
ton

tolf
0279-12

Figure 3: Logic Input for "OFF" to "ON" Condition (DGM181/182 Shown)

V+
15V
SWITCH
INPUT

SWITCH
OUTPUT

S1

A-~-C~,---~~---oVO

VO=VS

RL
RL +rOS(ON)

-=

(REPEAT TEST FOR
ALL CHANNELS)

0279-13

Figure 4: Switching Time Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values havs been characterized but are not tested.

8-52

DGM181-186
DGM189-191
SWITCH STATES
DUAL SPST DGM181/182

DUAL SPDT DGM190/191

Test Conditions

Test Conditions

DGM181/182

VIN "ON" = O.BV
VIN "OFF" = 2.4V

I

DGM190/191

All Channels
All Channels

VIN
VIN
VIN
VIN

DUAL DPST DGM1841185

"ON" = 2.4V
"ON" = O.BV
"OFF" = 2.4V
"OFF" = O.BV

Channels 1 & 2
Channels 3 & 4
Channels 3 & 4
Channels 1 & 2

Test Conditions
DGM184/185

VIN "ON"=2.4V
VIN "OFF"=O.BV

I

All Channels
All Channels

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MEACHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

B-53

:; IH311/IH312

!

High Speed SPST
:: 4-Channel Analog Switch
(I)

!

GENERAL DESCRIPTION

FEATURES
± 15V Analog Signals

• Switches

The IH311 and IH312 are CMOS, monolithic, QUAD,
SPST analog switches for use in high-speed switching applications for communications, instrumentation, process control and computer peripherals. Both devices provide true bidirectional performance in the ON condition and will block
signals to 30V peak-to-peak in the OFF condition. The
IH311 and IH312 differ only in that the digital control logic is
inverted, as shown in the truth table.
The IH311 and IH312 are available in 16-pin Dual-In-Line
packages and are offered in both military and commercial
temperature ranges.

IH311

• TTL Compatibility
• Logic Inputs Accept Negative Voltages
• RONS:175 Ohm

ORDERING INFORMATION
Part Number

Temperature
Range

Package

IH311MJE

- 55·C to + 125·C

16 Pin CERDIP

IH311CJE

O"Cto +70·C

16 Pin CERDIP

IH311CPE

O"Cto +70·C

16 Pin Plastic DIP

IH312MJE

- 55·C to + 125·C

16 Pin CERDIP

IH312CJE

O"Cto +70·C

16 Pin CERDIP

IH312CPE

O·Cto +70·C

16 Pin Plastic DIP

IH312
DUAL·II·LlIE PACKAGE

51

51
INI

INI
01

01

52

52
IN2

IN2

13 V+ ISUBSTRATE}

02

02

53

53
IN3

IN3
03

03

54

S4
IN4

IN4

04

04

TOP VIEW
0282-3

0282-1

0282-2

Four SPST Switches per Package

Figure 2: Pin Configuration
(Outline dwgs JE, PE)

Switches Shown for Logic "1" Input
Truth Table
Logic

IH311

IH312

0
1

ON
OFF

OFF
ON

logic "O"~O.8V
logic "1";':2.4V
Figure 1: functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH REBPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIEB OF
MERCHANTABILITY AND FITNess FOR A PARTICULAR USE.
307040-002
NUrE: AN typ/c8I_ha .. b 6 o n _ b u t _ n o l _

8-54

IH311/IH312
ABSOLUTE MAXIMUM RATINGS
v+ toV- ..................................... ,. 44V
VIN to Ground .........................•...... V+, V+
VL to Ground ............................. -0.3V,25V
VsorVotoV+ .............................. 0, -36V
VsorVotoV- ................................ 0,40V
V + to Ground .............•...................... 25V
V- to Ground ..•...................•...•....... -25V
Current, Any Terminal Except S or 0 .............. 30mA
Continuous Current, S or 0 ....................... 20mA

ELECTRICAL CHARACTERISTICS Symbol

Parameter

Peak Current, S or 0
(Pulsed at 1msec, 10% duty cycle max) ......... 70mA
Storage Temperature ................ -65°C to + 125°C
Operating Temperature .............. - 55°C to + 125°C
Power Dissipation (Package)"
16 Pin Plastic DIP" .......................... 470mW
• Device mounted with all leads soldered or welded to PC board.

•• Derate 6.SmWfOe above 25°C

MILITARY TEMPERATURE RANGE
Test Conditions
Vl= +1SV, V2= -ISV
VL=SV,GND

Limits
-55°C

+2SoC

Units
+ 125°C

SWITCH
VANALOG

Analog Signal Range

V = -15V, VL = +5V

ROS(ON)

Drain-Source On Resistance

Vo= ±10V, VIN=2.4V-IH312
Is=lmA, VIN=0.8V-IH311

IS(oft)

Source OFF Leakage Current

IO(oft)

Drain OFF Leakage Current

VIN=2.4V
IH311
VIN=0.8V
IH312

IO(ON)

Drain ON Leakage Current3

•

±15
150
175

V

150
175

200
250

Vs=14V, Vo= -14V

±1

100

VS= -14V, Vo=14V

±1

100

Vo=14V, Vs= -14V

±1

100

Vo= -14V, Vs=14V

±1

100

±2

200

±2

200

Vs=Vo= -14V, VIN=0.8V, IH311
VIN=2.4V,IH312

°

nA

INPUT
Input Current With Input
Voltage High

VIN=2.4V

10

±1

10

VIN=15V

10

±1

10

IINL
DYNAMIC

Input Current With Input

VIN=OV

10

±1

10

ton

Turn-ON Time

toffl

Turn-OFF Time

See Switching Time Test Circuit
Vs=10V, RL =lkO, CL =35pF

Ioff2
CS(9ff)

Source OFF Capacitance

Vs=OV, VIN=5V, f=IMHz2

5

COloff)

Drain OFF Capacitance

5

CO+Slonl
OIRR

Channel ON Capacitance

Vo=OV, VIN=5V, f= lMHz2
Vo=Vs=OV, VIN=OV, f=IMHz2

CCRR

Crosstalk
(Channel to Channel)

IINH

OFF Isolation4

300
150

ns

pF

16
70

VIN=5V, RL =lkO, CL = 15pF,
Vs= 1VRMS, f= 100kHz 2

dB

90

SUPPLY
1+

Positive Supply Current

10

1

10

1-

Negative Supply Current

10

1

10

IL

Logic Supply Current

10

1

10

VIN = 0 and 2.4V

/-LA

/-LA

NOTES: 1. The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data sheet.
2. For design reference only, not 100% tested.
"ON" switch.

3. 10(on) is leakage from driver into

4. OFF

ISolation~2olog~. Vs~input to OFF switch. VO~output.
Vo

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

8-55

•

= IH311/IH312

z"

...

::::.

!"

ABSOLUTE MAXIMUM RATINGS
V+ to v- ....................................... 44V
VIN to Ground ..............•...........•...•. V+, V+
VL to Ground •••••..•.••........•........• -0.SV,25V
VsorVotoV+ .....................•.•..•••• 0, -S6V
VsorVotoV- ....•...•.....................•. O,40V
V + to Ground .............•.•••.•.•••••.••.••.••. 25V
V- to Ground ..............•.•....•.••••••.•••• -25V
Current, Any Terminal Except S or 0 .............. SOmA
Continuous Current, S or 0 •••••••••.•...•........ 20mA

ELECTRICAL CHARACTERISTICS Symbol

Peak Current, S or 0
(Pulsed at 1msec, 10% duty cycle max) .•...•.•. 70mA
Storage Temperature ................ -65·C to + 125·C
Operating Temperature ..••..•.•.••....•.• O·C to + 700C
Power Dissipation (Package)"
16 Pin Plastic DIP"" .......................... 470mW
• ~evice mounted w~h all leads soldered or welded to PC board.
.. Derate 6.5mWrc above 25'C

COMMERCIAL TEMPERATURE RANGE
Test Conditions
V1 = + 15V, V2= -15V,
VL=5V,GND

Parameter

Umlts
+2SOC

Units

+70"C

SWITCH
VANALOG

Analog Signal Range

V = -15V, VL = +5V

±15

ROS(ON)

Drain-Source On Resistance

Vo= ±10V, VIN=2.4V-IH212
Is=1mA, VIN=0.8V-IH211

175

200

IS(oll)

Source OFF Leakage Current

VIN=2.4V
IHS11
VIN=0.8V
IHS12

Vs= 14V, Vo= -14V

±5

100

Vs= -14V, Vo=14V

±5

100

Vo= 14V, Vs= -14V

±5

100

Vo= -14V, Vs= 14V

±5

100

Vs=Vo= -14V, VIN=0.8V,IH211
VIN=2.4V,IH212

±5

200

±5

200

VIN=2.4V

±1

-10

VIN=15V

±1

10
-10

Drain OFF Leakage Current

10(011)

Drain ON Leakage Current!!

10(ON)

V

.0

nA

INPUT
Input Current With Input Voltage High

IINH
IINL
DYNAMIC

Input Current With Input Voltage Low

VIN=OV

±1

Ion

Turn-ON TIme
Turn-OFF Time

See Switching Time Test Circuit 5
Vs=10V, RL =1k.o, CL =S5pF

500

10111

250

p.A

ns

loff2
CS(oll)

Source OFF Capacitance

Vs=OV, VIN=5V, f=1MHz2

COloff)

Drain OFF CapaCitance

Vo=OV, VIN=5V, f=1MHz22

5
5

Co + S(onl
OIRR

Channel ON CapaCitance
OFF Isolation4

Vo=Vs=OV, VIN=OV, f= 1MHz2

16

Crosstalk
(Channel to Channel)

VIN=5V, RL=1k.o, CL = 15pF,
Vs= WRMS, f= 100kHz2

70

CCRR

VIN = 0 and 2.4V

pF

dB

90

SUPPLY
1+

Positive Supply Current

±1

10

1-

Negative Supply Current

±1

-10

IL

LogiC Supply Current

±1

10

p.A

NOTES: 1. The algebraic convention whereby the most negetive value is a minimum. and the most positive is a maximum, Is used In this data sheel
2. For design reference only, not 100% tested.
3. 10(011) is leakage from driver Into "ON" switch.
4. OFF Isolation = 2010g ~, Vs = Input to OFF
5.

Sw~hlng

s~h, VD = output

times only sampled.

INlERSlL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITlON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AN

_voJues _

been ch8rBcIBrirsd but". not tsotod.

8-56

.D~Dn.

IH311/IH312

..
..
i

61

.....
i61

Switch output waveform shown for Vs=constant with
logic input waveform as shown. Note the Vs may be + or
- as per switching time test circuit. Vo is the steady state
output with switch on. Feedthrough via gate capacitance
may result in spikes at leading and trailing edge of output
waveform.

N

LOGIC"
INPUT (lNll

.,<2One
.,<20ns

~~~;H

60'16

ol'-----..Ji

Vs

--t-"'];:::::==::;=:;to:g
0.9 Vo

SWITCH
OUTPUT (VO)

ton
"LOGIC SHOWN FOR DG211. )NVERT FOR DG212

0282-4

Figure 3: Switching Time Test Circuit
Logic shown for IH311. Invert for IH312.

+16V
SWITCH
OUTPUT

SI

VS'2V~------~r! L-ro-~~-o

(REPEAT TEST FOR IN2. IN3 AND IN4)

OV

Vo • Vs

v-

-15V
RL
RL + 'DS(on)

0282-5

Figure 4: Switching Time Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH REBPECT TO THIS PRODUCT BHALL BE THAT STATED IN THE WARRANlY ARTICLE OF THE CONDITION OF SALE.
THE WARRANlY SHALL BE EXCLUSIVE AND BHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPREBS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIEB OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE:AII/yp/csIVBlu8Bhs.. _ _ butlll8not_

8-57

•

~

C'»

IH311/IH312

.

:z:

:::::.
+15V

C'»

:E

-15V

-16V

+6V

0282-6

Figure 5: IH311 Schematic (% as shown)

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have be9n charsct8rized but are not tested.

8-58

IH401/IH401A
QUAD Varafet Analog Switch
GENERAL DESCRIPTION

FEATURES

The IH401 is made up of 4 monolithically constructed
combinations of a varactor type diode and an N-channel
JFET. The JFET itself is very similar to the popular 2N4391,
and the driver diode is specially designed, such that its capacitance is a strong function of the voltage across it. The
driver diode is electrically in series with the gate of the Nchannel FET and simulates a back-to-back diode structure.
This structure is needed to prevent forward biasing the
source-to-gate or drain-to-gate junctions of the JFET when
used in switching applications.
Previous applications of JFETs required the addition of
diodes, in series with the gate, and then perhaps a gate-tosource referral resistor or a capacitor in parallel with the
diode; therefore, at least 3 components were required to
perform the switch function. The IH401 does this same job
in one component (with a great deal better performance
characteristics).
Like a standard JFET, to practically perform a solid state
switch function a translator should be added to drive the
diode. This translator takes the TTL levels and converts
them to voltages required to drive the diode/FET system
(typically a OV to -15V translation and a 3V to + 15V shift).
With ± 15V power supplies, the IH401 will typically switch
18V
at any frequency from DC to 20MHz, with less than
30.o.~os(on). The IH401A will typically switch 22Vp-p with
less than 50.0. ROS(on)'

• RDS(on) = 25.0. Typical (IH401)
• ID(off) of 10pA Typical
• Switching Times of 25ns for ton and 75ns for toft
(RL =1kn)
• Built-In Overvoltage Protection (± 25V)
• Charge Injection Error of 3mY Typical Into O.01,...F
CapaCitor
• CI.. <1pF Typical
• Can Be Used for Hybrid Construction

ORDERING INFORMATION
Part Number

Package

IH401

CERDIP

IH401A

CERDIP

•
0283-1

Figure 1: Pin Configuration
(Outline Dwg JE)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDmON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTF: AHtypics/ _ _ bssn _ b u l " , . n o t _

8-59

~
o

IH401/IH401 A

....

:z: ABSOLUTE MAXIMUM RATINGS
::::.
... VstoVo ......................................... 35V
o
....

:E

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device, These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VG to Vs, vo ...................................... 35V
Operating Temperature ............... - 55·C to + 125·C
Storage Temperature ................. - 65·C to + 150·C
Lead Temperature (Soldering, 10sec) .............. 300·C

ELECTRICAL CHARACTERISTICS AT 25°C/125°C
Symbol

Characteristic

IH401

Test Conditions
Min

Units

Typ

Max

20

30

n

6

7.5

V

10

±500

pA

Switch "on" Resistance

VORIVE=15V,
VORAIN= -7.5V 10= 10mA

Vp

Pinch-Off Voltage

10=lnA, Vos=10V

10(off)

Switch "off" Current
or "off" Leakage

VORIVE= -15V,
VSOURCE= -7.5V,
VORAIN= +7.5V

Switch "off" Leakage
at 125·C

VORIVE= -15V,
VSOURCE= -7.5V,
VORAIN = + 7.5V

0.25

50

nA

Switch "off" Current

VORIVE= -15V,
VORAIN= -7.5V,
VSOURCE= +7.5V

10

±500

pA

Switch "off" Leakage
at 125·C

VORIVE= -15V,
VSOURCE = -7.5V,
VORAIN= +7.5V

0.3

50

nA

Switch Leakage when Turned "on"

Vo=VS= -7.5V,

0.02

±2

nA

ROS(on)

10(off)

IS(off)

IS(off)

10(on) + IS(on)

3

VORIVE=+15V
Vanalog

AC Input Voltage Range
without Distortion

See Figure 3

Vinject

Charge Injection Error Voltage

See Figure 4

BVdiode

Diode Reverse Breakdown
Voltage. This Correlates to
Overvoltage Protection

Vo=Vs=-V,

Gate to Source or Gate
to Drain Reverse
Breakdown Voltage

18

Vp.p

3

mVp •p

-30

-45

V

VORIVE= -V,
Vo=Vs=OV,
ORIVE=l",A

30

41

V

Maximum Current Switch
can Deliver (Pulsed)

VORIVE=15V,
Vs=OV,
0= +10V

45

70

mA

ton

Switch "on" time (Note 1)

See Figure 2

50

ns

toff

Switch "off" time (Note 1)

See Figure 2

150

ns

BVGSS

loss

10RIVE=1",A,
ORIVE=OV

15

NOTE: 1. Oriving waveform must be > lOOns rise and fall time.

INTERSIL'$ SOLE AND EXCLUStVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

8-60

.D~DIl.

IH401/IH401 A
SIGNAL

-15VIL
STROBE
INPUT

~

ov
-15\1

\.

",.
100_

ton_

0283-2

STROBE INPUT

'5V

"'"'

VOUT

lk"

OV

-

"'"'

""' )'!--

toff

~6V

SIGNAL

-5\1 SIGNAL

/ '''''

-5V

- -

Ioff-

0283-3

Figure 2: Switching Time Test Circuit and Waveforms

V ,N

"5VLi!I

I....

'~:s
"I-

-01-

av~

I.

-15\1

~VaUT

.~ 1
VaUT -

~ C~O,OlJlF

lkH

-=-

0283-5

Figure 4: Charge Injection Test Circuit

0283-4

Figure 3: Analog Input Voltage Range
Test Circuit

ELECTRICAL CHARACTERISTICS AT 25°C/125°C
Symbol

Characteristic

IH401A

Test Conditions
Min

Units

Typ

Max

35

50

n

4

5

V

ROS(on)

Switch "on" Resistance

VORIVE= 15V,
VORAIN= -10V, 10=10mA

Vp

Pinch-Off Voltage

10= 1nA, VOS= 10V

10(off)

Switch "off" Current
or "off" Leakage

VORIVE= -15V,
VSOURCE= -10V,
VORAIN = + 10V

10

±500

pA

Switch "off" Leakage
at 125'C

VORIVE= -15V,
VSOURCE= -10V,
VORAIN= + 10V

0.25

50

nA

Switch "off" Current

VORIVE= -15V,
VORAIN= -10V,
VSOURCE= + 10V

10

±500

pA

Switch "off" Leakage
at 125'C

VORIVE= -15V,
VSOURCE= -10V,
VORAIN= +10V

0.3

50

nA

Switch Leakage when
Turned "on"

Vo=Vs= -10V,
VORIVE= + 15V

0.02

±2

nA

AC Input Voltage Range
without Distortion

See Figure 3

10(011)

IS(Off)

IS(Off)

10(on)

+ IS(on)

Vanalog

2

20

22

Vp_p

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABiLiTY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but ate not tested.

8-61

.

....
i
...
o

"'"'

+15\1

'5V

+15V

...io

,...

:! IH401/IH401 A
o

•z
::.
...o
!•

ELECTRICAL CHARACTERISTICS AT 25°C/125°C
Symbol

Characteristic

(Continued)

IH401A

Test Conditions
Min

VinJect

Charge Injection Amplitude

See Figure 4

BVdiode

Diode Reverse Breakdown
Voltage. This Correlates to
Overvoltage Protection

Vo=Vs=-V,
10RlVE = 1pA,
ORIVE=OV

Gate to Source or Gate
to Drain Reverse
Breakdown Voltage

VORIVE=-V,
Vo=VS=OV,

Maximum Current Switch
can Deliver (Pulsed)

VORIVE=15V, Vs=OV,
0= +10V

lon

Switch "on" time (Note 1)

1011

Switch "off" time (Note 1)

BVGSS

lOSS

Typ

Units
Max

3

mVp-p

-30

-45

V

30

41

V

35

55

mA

See Figure 2

50

ns

See Figure 2

150

ns

ORIVE=1pA

NOTE: Driving waveform must be > lOOns rise and fall time.

APPLICATIONS
IH401 Family

Although this simple PNP circuit represents a minimum of
components, it requires open collector TIL input and 11011) is
limited by the collector load resistor (approximately 1.5,...s
for 10kn). Improved switching speed can be obtained by
increasing the complexity of the translator stage.

In general, the IH401 family can be used in any application formally using a JFET!isolation diode combination
(2N4391 or similar). Like standard FET circuits, the IH401
requires a translator for normal analog switch function. The
translator is used to boost the TIL input signals to the
± 15V analog supply levels which allow the IH401 to handle
±7.5V analog signals (or IH401A to handle ±10V analog
signals). A typical Simple PNP translator is shown in Figure

•

5.

• 1011 time of approx.

A translator which overcomes the problems of the simple
PNPstage is the IntersilIH6201.* This translator driving an
IH401 varafet produces the following typical features:
ton time of approx. 200ns
80ns

}

break before
make switch
+Z.4V

•
·1 V

ANALOG
SIGNALS
IN

•
•
•

,......,

o.4V~

~

10(on) + IS(on) typically 20pA up to ± 10V analog signals
10(011) or IS(oII) typically 20pA
Quiescent current drain of approx. 100nA in either "on"

or "off" case

+15V

,.....,

11V...J

TIL compatible strobing levels of

L..

·The IH6201 Is a dual translator (two independent translators per package) constructed from monolithic CMOS
technology. The schematic of one-half IH6201, driving onefourth of an IH401, is shown in Figure 6 .

tOkO

FROM TTL

OPEN COLLECTOR
LOGIC
• 1SV

0283-6

FigureS

INTERSlL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USIE.
N071::AHtypicsJ_ha .. _ _ butllfllnot_

8-62

lIlO~OI!..

IH401/IH401 A

i

...

o
.......

i
...o
...

•

r----l
2.4V
,....,
mOR
O.4V....I
L... CMOS
INPUT
STROBE

·
1
GND

VL

I

I

I

I
I

I
8

I

I
S
I
L_V~A~_J

+15V

8 - 15V
+15V

+5V

-Vl

..r1-.
I
I
I
I

8

I
I

+15V-LJ-15V

-15V
0283-8

NOTE: Each translator output has a 9 and 8 output. 8 is just the inverse of 9 i.e., (8 output is 1BO· out of phase with respect to 9 output).

Figure 6: IH6201 Driving An IH401

•

-3v
OVSLT21..2

0283-9

NOTE: Either switch is turned on when strobe input goes high.

Figure 7: Dual SPST Analog Switch

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE All typical values have been characterized but are not tested

8-63

~
o

IH401/IH401 A

~

:z:
::::.
o
~
!

..

+3V

ov.SLT 2l1

0283-10

Figure 8: DPDT Analog Switch

0283-11

Figure 9: Dual SPDT Analog Switch
A very useful feature of this system is that one-half of an
IH6201 and one-half of an IH401 can combine to make a
SPOT switch, or an IH6201 plus an IH401 can make a dual
SPOT analog switch. (See Figure 9)

0283-12

Figure 10: Dual DPST Analog Switch

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

8-64

IH5009-IH5024
Virtual Ground
Analog Switch
GENERAL DESCRIPTION

FEATURES

The IH5009 series of analog switches were designed to
fill the need for an easy-to-use, inexpensive switch for both
industrial and military applications. Although low cost is a
primary design objective, performance and versatility have
not been sacrificed.
Each package contains up to four channels of analog gating and is designed to eliminate the need for an external
driver. The odd numbered devices are designed to be driven directly from TTL open collector logic (15 volts) while the
even numbered devices are driven directly from low level
TTL logic (5 volts). Each channel simulates a SPOT switch.
SPST switch action is obtained by leaving the diode cathode unconnected; for SPOT action, the cathode should be
grounded (OV). The parts are intended for high performance
multiplexing and com mutating usage. A logiC "0" turns the
channel ON and a logic "1" turns the channel OFF.

• Switches Analog Signals Up to 20 Volts Peak-to-Peak
• Each Channel Complete - Interfaces With Most
Integrated Logic
• Switching Speeds Less Than O.Sf.LS
• ID(OFF) Less Than SOOpA Typical at 70"C
• Effective rds(ON) - sn to son
• CommerCial and Military Temperature Range
Operation

ORDERING INFORMATION
IH50XX

Channels

Logic
Level

Packages

IH5009

4

+15

JD,DD,PD

IH5010

4

+5

JD,DD,PD

IH5011

4

+15

JE,DE,PE

IH5012

4

+5

JE,DE,PE

IH5013

3

+15

JD,DD,PD

IH5014

3

+5

JD,DD,PD

IH5015

3

+15

IH5016

3

+5

JE,DE,PE

IH5017

2

+15

JD,DD,PA

IH5016

2

+5

JD,DD,PA

IH5019

2

+15

JE,DE,PA

IH5020

2

+5

JE,DE,PA

IH5021

1

+15

JD,DD,PA

IH5022

1

+5

JD,DD,PA

IH5023

1

+15

JE,DE,PA

IH5024

1

+5

JE,DE,PA

Basic
Part Number

.

M

DE
LpaCkage
PA - B-pin PLASTIC DIP
PO - 14-PIN PLASTIC DIP
PE - 16-PIN PLASTIC DIP
DO - 14-PIN CERAMIC DIP
(Special Onder Only)
DE -16-PIN CERAMIC DIP
(Special Order Only)
JD - 14-PIN CERDIP
JE - 16-PIN CERDIP

JE,DE,PE

TEMPERATURE RANGE
M = MILITARY (-55°C to + 125°C)
C = COMMERCIAL (O°C to + 70'C)
' - - - - - - BASIC PART NUMBER

NOTE: MiI·Temperature range (-55'C to +125'C) available In oeramlc
packages only,

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTF:AHtyp/cBI_hIlvobB6n _buttl19no1""'irId.

8-65

•

IID~DIl.

: IH5009-IH5024
o
10

..g

Z ABSOLUTE MAXIMUM RATINGS
'j

Positive Analog Signal Voltage ..................... 30V
Negative Analog Signal Voltage ....•....••....... -15V
Diode Current •.........•...........•..••...•••. 10mA
10 Power Dissipation (Note) ................•...... 500mW
Storage Temperature ......•.•...•.•• - 65·C to + 150·C

Lead Temperature (Soldering, 10see) ............. 300"C
Operating Temperature
5009C Series .....•.•...••...•.....••• O·C to + 70·C
5009~ Series ..................... - 55·C to + 125·C
Lead Temperature (Soldering, 10see) .•.•...•..••• 300"C

:E

NOTE: Dissipation raling assumes device Is mounted wllh all leads welded or soldered 10 printed circuH board in ambienllemperalure below 75"C. For higher
temparature, derate al rate of Sm/W'C.
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may CBUSB ptIJ1TI8nent damage to ths davlce. These 8111 stress ratings only and fUnctionsl
opsrstJon of ths davlce at thsse or any other conditions above those indiCBted in ths opsrstionsl sections of ths spBCificatJons Is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect davlce reliability.

IH5009 (rOSION)S: 1000) IH5010
(rDl(ONLS: 1500) 14 PIN DIP
(OUTLINE DWGS DD, PD, JD)

IH5013 (I'DS(ON)S: 1000) IH5014
(rDS(ON)S: 1500) 14 PIN DIP
(OUTLINE DWGS DD, PE, JE)

IH5011 (rOSION)S:1000) IH5012
(rOSION)S: 1500) 16 PIN DIP
(OUTLINE DWGS DE, PE, JE)

0284-3

0284-2

0284-1

IH5015 (rOS(ON)S: 1000) IH5016
(rOSION)S:1500) 16 PIN DIP
(OUTLINE DWGS DE, PE, JE)

IH5019 (rOSION) s: 1000) IH5020
(r~ON)S:1500) 8 PIN DIP
(OUTLINE DWGS DE, PA, JE)

IH5017 (rDS(ON)S:1000) IH5018
(rOS(ON)S:1500) 8 PIN DIP
(OUTLINE DWGS DD, PA, JD)

31; ,$ E· I:~
I'.

I

0284-5

,

I'.

0284-6

0284-4

IH5021 (rOS{ON1S: 1000) IH5022 (rOSlON)S: 1500)
8 PIN DIP (OUTLINE DWGS DD, PA, JD)

IH5023 (rOSlON)S: 1000) IH5024 (rOSION)S: 1500)
8 PIN DIP (OUTLINE DWGS DE, PA, JE)

0284-8

0284-7

INole: Numbers in brackets refer to CERDIP packages.)

Figure 1: Pin Connections

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typical values have bHn charact6rIzsd but BI'6 not tested.

8·66

IID~Dn.

IH5009-IH5024

i

UI

o
o

IH5009 (rDS(ON) ~ 100.0)
IH5010 (rD8(ON)~ 150.0)
14 PIN DlP

CD

THREE CHANNEL

FOUR CHANNEL

IH5013 (rDS(ON)~ 100.0)
IH5014 (rD8(ON)~ 15O.!l)
14PINDlP

IH5011 (rDS(ON) ~ 100.0)
IH5012 (rD8(ON) ~ 150.0)
16 PIN DlP

•

UI

o

II)
~

.~.

1". 6,
"~.

,R

t2 hl0

0284-11

0284-12

IT

0284-9

i

tT,'

IT
IT.
•

I

IH5015 (rDS(ON) ~ 100.0)
IH5016 (rD8(ON)~ 150.0)
16 PIN DlP

0284-10

TWO CHANNEL
IH5017 (rDS(ON)~ 100.0)
IH5018 (rD8(ON) ~ 15O.!l)
8 PIN DIP

'~.
3

7

I

..

•

SINGLE CHANNEL

IH5019 (fDS(ON)~ 100.0)
IH5020 (rD8(ON)~ 150.0)
8PIN DIP

IH5023 (rDS(ON) ~ 100.0)

IH5022(fD8(ON)~150.o)

IH5024(fD8(ON)~150.o)

8PIN DIP

8 PIN DIP

'~.

"~'

t. b2

3

.~.
0284-13

IH5021 (ros(ON) ~ 100.0)

I

,

0284-15

"TT'
•

2

0284-16

t. 6,
0284-14

Figure 2: Device Schematics and Pin Connections

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED DR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typicsI vaIuss haWl been ch8mcI9riz9d but SI9 not I9SI«J.

8-67

•

: IH5009-IH5024
o

II)

Z

'i
GI
o
o
II)

!

ELECTRICAL CHARACTERISTICS
Symbol
(Note 1)

Characteristic

Type
(Note 4)

(per channel)
TEST
Conditions
(Note 2)

Specification Limit
-SS'C(M)
O'C (C)

25'C

+ 125'C (M)
Units
+70'C(C)

MinIMax Typ MinIMax MinIMax
0.Q1

±0.5

100

/LA

IINeOFF) Input Current-OFF

5V Logic Ckts VIN= +4.5V, VA= ±10V

0.04

±0.5

20

nA

IIN(OFF) Input Current-OFF

15V Logic Ckts VIN= +11V, VA= ±10V

0.04

±0.5

20

nA

VIN(ON) Channel Control Voltage-ON

5V Logic Ckts See Figure 7, Note 3

0.5

0.5

0.5

V

VIN(ON) Channel Control Voltage-ON 15V Logic Ckts See Figure 8, Note 3

1.5

IIN(ON)

Input Current-ON

ALL

VIN=OV,10=2mA

1.5

1.5

V

VIN(OFF) Channel Control Voltage-OFF 5V Logic Ckts See Figure 6, Note 3

4.5

4.5

V

VIN(OFF) Channel Control Voltage-OFF 15V Logic Ckts See Figure 8, Note 3

11.0

11.0

V

20

nA

10(OFF) Leakage Current-OFF

5V Logic Ckts VIN= +4.5V, VA= ±10V

0.02

±0.5

10(OFF) Leakage Current-OFF

15V Logic Ckts VIN= +11V, VA= ±10V

0.02

±0.5

20

nA

0.30

±1.0

1000 (M)
200 (C)

nA

0.10

±0.5

500(M)
100 (C)

nA

10(ON)

Leakage Current-ON

5V Logic Ckts VIN=OV,IS= 1mA

10(ON)

Leakage Current-ON

15V Logic Ckts VIN=OV,ls=1mA

10(ON)

Leakage Current-ON

5V Logic Ckts VIN=OV,ls=2mA

1.0

10

/LA

10eON)

Leakage Current-ON

15V Logic Ckts VIN=OV,ls=2mA

2.0

100

/LA

0
0

rOS(ON) Drain-Source ON-Resistance 5V Logic Ckts 10 = 2mA, VIN = 0.5V
rOS(ON) Drain-Source ON-Resistance 15V Logic Ckts 10=2inA, VIN= 1.5V

150

90

150

385(M)
240 (C)

100

80

100

250(M)
160 (C)

t(on)

Turn-ON Time

All

See Figures 5 & 6

150

500

t(off)

Turn-OFF Time

All

See Figures 5 & 6

300

500

CT

CrossTalk

All

f= 100Hz

120

NOTES:

1. (OFF) and (ON) subscript notation refers to the conduction state of the
2. Refer to Figure 2 for defln~lon of terms.

ns
ns
dB

FET switch for the given test.

3. VIN(ON) and VIN(OFF) are test conditions guaranteed by the tests of rOS(ON) and IO(OFF) respactively.
4. "5V Logic CKTS" applies to even-numbered devices. "15V Legic CKTS" applies to odd-numbered devices,

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: All typical valU68 have been charsctBrized but srs not tsstsd.

8-68

.D~On..

IHS009-IHS024
TYPICAL PERFORMANCE CHARACTERISTICS

~'*~~~ltI~
.
~'OO'III
~ ~
!

'°0.5

!'*
,
l!;
I

!.

!

Is

ROS(ON) VB. TEMPERATURE
(NORMALIZED TO 25'C
VALUE)

•

V

25

,.

TEMPERATURE ( Cl

-'30
-'20

V

-110

~-100

CII

.
o

N

50

,.

'00

TEMPERATURE I' C)

0284-19

CROSSTALK MEASUREMENT CIRCUIT
10 kll

'"

~....,

~

",

25

V

25

'00

0284-18

CROSSTALK AS A
FUNCTION OF FREQUENCY

1/

~-r-

E
F

r~
,....
""··'/"/-r.,,,,,

Fi"

1.0
1.5
2.0
2.5
I, - SOURCE CURRENT (rnA)

0284-17

c--

100

-!I!!!-'E§

I

i

v.

V

I

jD(OFF) VB. TEMPERATURE

IS·'mA
VA" tOV
R .. 10K!~

~

_

(per channel)

_ ID(ON) VB. TEMPERATURE

ID(ON) VB. Is AT 25'C

i
CII
o
o
U)

-80

I'

~ -70

~
50

75

100

5 ....
10

TEMPERATURe I C)

0284-20

,

--P>--

-50
-40
-3D
100

lK

10K

tOOK

1M

FREQUENCY (Hz)

.. SV (5010 ETC)
.15V (5009 ETC)

0284-21

0284-22

DETAILED DESCRIPTION
The signals seen at the drain of a junction FET type analog switch can be arbitrarily divided into two categories;
those which are less than ± 200mV, and those which are
greater than ±200mV. The former category includes all
those circuits where switching is performed at the virtual
ground point of an op-amp, and it is primarily towards these
applications that the IH5009 family of circuits is directed.
By limiting the analog signal at the switching point to
± 200mV, no external driver is required and the need for
additional power supplies is eliminated.
Devices are available with both common drains and with
uncommitted drains.

Those devices which feature common drains have another FET in addition to the channel switches. This FET, which
has gate and source connected such that VGS=O, is intended to compensate for the on-resistance of the switch.
When placed in series with the feedback resistor (Figure 3)
the gain is given by:
GAIN

10k!}

+ rOS(ON)(compensator)
10k!} + rOS(switch)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN ·LlEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typ/cBI values MIlS been chsrBct9rJzed but Ilf8 not tested.

8-69

•

IID~OI!..

IH5009-IH5024

SWITCHING CHARACTERISTICS

VA" -lOV

~
k

+15V

ov.JL

EOUT (CL< 10 pF)

G

VIN

D
'::"

":"

0284-23

Figure 3: Use of Compensation FET

0284-25

Clearly, the gain error caused by the switch is dependent
on the match between the FETs rather than the absolute
value of the FET on-resistance. For the standard product,
all the FETs in a given package are guaranteed to match
within 50n. Selections down to 5n are available however.
Contact factory for details. Since the absolute value of
rDS(ON) is guaranteed only to be less than 100n or 150n, a
substantial improvement in gain accuracy can be obtained
by using the compensating FET.

,.V

ION
PW'" 5~1
',<0.1j.!5
II <0.1j.!'

1.SV

7.SV

'oFF

ov

OUTPUT
V,o."'10V

ov
ov

OUTPUT
VA- -tOV

DEFINITION OF TERMS
0284-26

Figure 5: High Level Logic

.,

VA =

~10V

~
k

.. 5V

ovJL

EOUT (CL ~ 10 pF)

G

VIN

0

0284-24

Figure 4.
VIN

5V

PW = Sp,

NOISE IMMUNITY

t,<0.1j.!1
tf., ·;.v .,
I-~

'''~

°1

S

s,

6"
v-

b"

y.. y"

;~D,

-~:'
ON.

0266-15

0"
v0288-16

DPDTIH5046
(ros

b"
v0266-18

4PSTIH5047
(rDS (ON) < 750)

v,

...
s,

I,

v'

v'

y,.

y.
.- ;-v o,
.... .-V

•
"

.-v

7

0

.....
_.I
lNo1! j1...J'""'P'"

DJ

0,

-v .,

I,

.
..

I,

I

IS

•
S

y"

-

•

~.,

I

t....,

I

~o,

I~

~D,

01

INI~ -f"\..b.J

,-

b"

....b"

112

v-

0266-19

b" 6"
v-

G. .

0266-20

Figure 2: Switching State Diagrams (Cont.)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY BHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTASIUTY AND ATNESS FOR A PARTICULAR USE.

NOTE: AN typical values havB bNn charsctstizBd but lite not_ted.

8-75

i
UI
o

~
o

IH5040-IH5047

II)

z: TYPICAL PERFORMANCE CHARACTERISTICS (Per Channel)
i
o
RDS(on) VS POWER SUPPLY VOLTAGE
~
ROS(on) vs VANALOG SIGNAL
o
160
100
II)

:!:

I

80

§:

+12~'C

60

+25'C

J 40

5S'C

l

-~5

o

120

§:

J

+12~'C

+2S'C

20

=

--....

~ Is ~

20

lmA
5

7.5 ,

~

o
10

I 25~~-+--~~-+--~~~
30

I ..-

+15V

I

e-- r--

35~~-+~--+-1--+~r-i

~

+12V

80
60

40~~~~--~~~~~~

- --

+IOV
100

40

-I @ ± 15V SUPPLIES

-6 -5 -2.5 0 2.5

I
I

140

CHARGE INJECTION vs VANALOG
(SEE FIG. B) CL = 10,OOOpF

J 20r-~-+__r-~-+__~~-1

+1~V

15~~-+__~1--+__r-1--i

-10 -7.5 -5 -2.5 0

2.5

5

7.5

1:t:~;±::t::t:1~I::t:l

10

VANALOG (V)

VANALOG (V)

-10 -7.5 -5 -2.5 0

0286-22

0286-21

2.5 5

7.5

10

VANALOG (V)

0286-23

~"'~-t ~

120

1"- ....
ii'

~

C;;

100

:--.... i'o.

1"-1"-

fI>

co

a::

e

60

>c

40

I

r-

I

I

I

I

I

L-=

I

80

3V

20

o

200mvpp
ceRR ~ 20LOG VOUT (mVpp)

1 10

100 1k 10k 100k 1M

(NIL
SWITCHED
CHANNEL

I

I

~~~_

~
'-- -

-

-

-

Vour

loon

•

f:

5111

-loon

FREQUENCY (Hz)
0286-25

0286-24

-120
-100

ii'
~

-80

ii:'
"- -60
e.

>c

........

"- ~~c

1"-1"-

r-..r-..

OFF STATE

sIn

--

--

-40
100U

-20

o

2OO0mYpp
OIRR • 20LOG VOUT (mYpp)
0286-27

1Hz 10Hz 100Hz 1k 10k 100k 1M

FREQUENCY (Hz)
0286-26

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PROD.UCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bsBn charsct8rized but are not tested.

8-76

IH5040-IH5047
TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
POWER SUPPLY QUIESCENT CURRENT vs LOGIC FREQUENCY RATE

/

/

.g

/

z

/

/

3V

~

~olrl-

I...--r---.I

V

/

0286-29

L/

5

_0

'"

10k

LOGIC FREOUENCV@10'loOUn'CYCLE IHzl

0286-28

TEST CIRCUITS

ANALOG IN'UT

ANALOG INPUT

'OV

3V

ovfi
lOGIC
INPUT

)

o--Q--t>-

h
1";' .

_

'Op'

ovfl~_
~
~:;~~ ~ IL

IMrQ--l>-_
VOUT

10,000pF

0

~vour

'=

1

510

"::""::"

tooo
0286-32

0286-31

0286-30

Figure 3

"\..

LOGIC IN'UT

1-

Your

m
VPO@'MC

Figure 5

Figure 4

NOTE 1: Some channels are turned on by high "1" logic inputs and other channels are turned on by low "0" inputs; however C.SV to 2.4V describes the min. range
tor switching properly. Refer to logic diagrams to see absolute value of logic input required to produce "ON" or "OFF" state.

APPLICATIONS

OUTPUT
ANALOG
INPUT

IHS043

+3V • > SAMPL E MODE
OV • > HOLD Mooe

0286-33

Figure 6: Improved Sample & Hold Using IH5043
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ART1CLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOA A PARTICULAR USE.
NOTE: All typicsl values have been charactBri2ed but are not tested

8·77

•

~

o

IH5040-IH5047

10

:z: APPLICATIONS
i

(Continued)

o
...
o10

:E

T2L
LOGIC
STROBE
EXAMPLE: If - VANALOG ~ -10VDC and
+ VANALOG ~ + 10VDC Ihen Ladder Legs
are swHched between ± IOVDC, depending
upon state of Logic Strobe.

..n..
IH5043
2R

2R

R

R

R

.....-<

ETC. ~.y,Ir-~-""""""""'-"N

T2L
LOGIC
STROBE

ETC.

0286-34

Figure 7: Using the CMOS Switch to Drive an R/2R Ladder Network (2 Legs)

Constant gain, constant Q, variable frequency filter which
provides simultaneous Lowpass, Bandpass, and Highpass
outputs. With the component values shown, center frequency
will be 235Hz and 23.5Hz for high and low logic inputs

respectivelv.

a = 100, and Gain"" 100.
tn

=Center Frequency:: _1_

211RC

STROBE

0286-35

Figure 8: Digitally Tuned Low Power Active Filter

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBUGAnON WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPliED OR STATUTORY, INCLUDING THE IMPliED WARRANTIES OF
MERCHANTABIliTY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charact8lized but are not tested.

8-78

IH5040-IH5047
APPLICATIONS

(Continued)

r - - - - - - - - -, +16V

I

I
I
I
I

I

":"

L~.!'~~T~

I
I
I
I
I

+16V

I

___ -.J

0286-38

Figure 9: Interfacing with TTL Open Collector Logic
(Typ. Example for + 15V Case Shown)

Jl~

~ND
IN

GND

•

15V> y+ >' 5V
;;'-1&V

rsv .. v·

0286-37

Figure 10: Interfacing with CMOS Logic

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE; All typical values have been chafBctBlized but are not tested.

8·79

; IH5040-IH5047

o
:z:
j'

10

APPLICATIONS

(Continued)

o

...o

10

+5V

~

IN

TTL.rL

I
I
I

LOGIC

j

+5V

~++15VOR

I

I
I

+VCC(VI TERMINAL)

1

I
-=L~~L!~~ ___ ..J

100
0266-36

Figure 11: TTL Logic Interface

lNTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

8-80

IH5048-IH5051
Low Charge Injection
CMOS Analog Switches
GENERAL DESCRIPTION

FEATURES

The IH5048 family of analog switches is especially made
for low charge injection and low leakage. Construction includes our CMOS high level driver circuitry combined with
unique "VARAFET" switches.

•
•
•
•

Low Charge Injectlon-1mV (Typ.)
Quiescent Current Less Than 11-'A
TTL, OTL, CMOS, PMOS Compatible
Non-Latching With Supply Turn-Off

• Low rOS(on) - 350 (Typ.)
• Pin-Out Compatible With IH5040 Family
• Low Leakage 100 pA Typical

ORDERING INFORMATION

ORDERING INFORMATION
IH5048

L
M

JE

Package
DE - 14-pin Ceramic DIP
FD-2 - 14-pin Flat Pak
PE - 16-pin Plastic DIP
Temperature Range
M - Military (- 55°C to + 125°C)
C - Commercial (O°C to + 85°C)

Intersll
Part No.

Type

rOS(on)

IH5048 Dual
IH5049 Dual
IH5050
IH5051 Dual

SPST
DPST
SPDT
SPDT

350
350
350
350

NOTE 1. See Switching State diagrams for applicable package equivalency.

' - - - - - - - - Basic Part Number
Switch States are for
Logic "1" Input

Flat Package (FD-2)

DIP (DE) Package

DUAL SPST IHS048
(ros (ON) < 3S!l)

s,

.

1
10

~~

S2

112
~o,

'" " ........
1N2o-a

?',
I

S,

.J

0,

........
',,"1<>:-" ~~

-«)--p--,
~O,

GNO

"

" .q:::w.J

IlIIto-

'

6"

I,

5,

~~n

. 0,

)':' ),"
v-

GND

0287-1

0287-2

Figure 1: Switching State Diagrams

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE' All typical values have been characterized but are not tested.

8-81

•

.. IH5048-IH5051

1Il0~OI!..

II)

0

10

z:

'i
CD

Switch States are
for Logic "1" Input

Flat Package (FD-2)

DIP (DE) Package

~

0

10

!

DUAL DPST IHS049
(ros (ON) < 3S0)

(DG184 EQUIVALENT)
v,

s,
s,

v·

.,

v,

v·

0,
0,

",

s,

",s,

0,

S.

O.

0,
0,

Sj

'N,
'N,

D,

"

aND

"

D.

0287-4
aND

0287-5

SPDTIHSOSO
(rOS (ON) <3S0)

"

v,

v·

v·
"

5,

0,

5,

5,

0,

5,

0,

D,

I

_J

aND
aND

0287-8

0267-7

DUAL SPOT IHSOS1
(rOS (ON)<3S0)

(DG190 EQUIVALENT)

v,

v,

s,
s,

0,

v·

~,

'"

",

..

S,

0,

S,

D,

S,

D,

",

O.

D,

aND

o.
0287-9
aND

0267-10

Figure 1: Switching State Diagrams (Cont.)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have b6en characterized but are not tested.

8-82

[l]D~DIl.

IH5048-IH5051
ABSOLUTE MAXIMUM RATINGS

Current (Any Terminal) ........................ <30mA
Storage Temperature ................ - 65'C to + 150'C
Operating Temperature .............. - 55'C to + 125'C
Lead Temperature (Soldering, 1Osee) ............. 300'C
Power Dissipation ............................. 450mW
(All Leads Soldered to a P.C. Board)
Derate 6mW I'C Above 70'C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permsf19nt damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied Exposure to absolute
maximum rating conditions for extended periods msy affect device reliability.

(@25'C,V+= +15V,V-=-15V,VL= +5V)

Per Channel
Symbol

MiniMax Limits
Test Conditions

Characteristic

CII

...oCD

v+ -v- ....................................... <36V
v+-vo········································<30V
Vo-V- ........................................ <30V
Vo-Vs ...................................... <±22V
VL-V- ........................................ <33V
VL - VIN ........................................ <30V
VL -GND ....................................... <20V
VIN - GND ...................................... <20V

ELECTRICAL CHARACTERISTICS

i

Military

Commercial

-55'C + 25'C + 125'C 0

Units

+ 25'C +70'C

IIN(ON)

Input Logic Current

VIN = 2.4V Note 1

±1

±1

10

±1

±1

10

,...A

IIN(OFF)

Input Logic Current

VIN = 0.8V Note 1

±1

±1

10

±1

±1

10

,...A

rOS(on)

Drain-Source On
Resistance

Is= -10mA
VANALOG= -10V

40

60

45

75

0.

arOS(ON)

Channel to Channel
rOS(ON) Match

15
(Typ)

15
(Typ)

0.

VANALOG

Min. Analog Signal
Handling Capability

±10

±10

V

IO(OFF)liS(OFF) Switch OFF Leakage VANALOG= -10Vto +10V
Current

±1

100

±5

100

nA

±2

200

±10

200

nA

IO(ON)
+IS(ON)

Switch On Leakage
Current

Vo=Vs= -10Vto +10V

Ion

Switch "ON" Time

RL = 1ko., VANALOG= -10V
to + 10V See Fig. 2

500

1000

ns

loff

Switch "OFF" Time

RL = 1ko., VANALOG= -10V
to + 10V See Fig. 2

250

500

ns

1 (Typ)

2 (Typ)

mV

54
(Typ)

50
(Typ)

dB

Q(INJ.)

Charge Injection

See Fig. 3

OIRR

Min. Off Isolation
Rejection Ratio

f= 1MHz, RL = 1000., CL,;;5pF
See Fig. 4, (Note 1)

1+ Q

V + Power Supply
Quiescent Current

1- Q

V - Power Supply
Quiescent Current

1+ LQ

±1

±1

10

10

10

100

,...A

±1

±1

10

10

10

100

,...A

+5VSupply
Quiescent Current

±1

±1

10

10

10

100

,...A

IGNO

GndSupply
Quiescent Current

±1

±1

10

10

10

100

,...A

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

V+ = +15V, V= -15V, VL = +5V

One Channel Off; Any Other
Channel Switches as per
Performance Characteristics (Note 1)

54
(Typ)

50
(Typ)

dB

Note 1: Not tested in production.

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typiCSI values have been characterized but are not tested.

8-83

I

i

CII

o

...
CII

.. IH5048-IH5051
10

o

10

~ TEST CIRCUITS
CD
~

ANALOG INPuT
-+-IOV

o

.fL~..J.h

10

!

INPUT
LOG'C

3K
vn~

Your

lOpF

r

f

LOGIC
INPuT

__ L---

l-~~VOt.:T

Ikn

':'"

)1'-1

ANALOG INPUT

LOGie INPUT

(NO~_

..

........

1--.

ou ,

1'0011

I'Oaoo"

"='

1111

0287-13

0287-12
0287-11

Figure 3

Figure 2

Figure 4

NOTE 1: Some channels are turned on by high "I" logic inputs and other channels are turned on by low "0" inputs; however O.BV to 2.4V describes the min. range
for switching properly. Refer to logic diagrams to see absolute value of logic Input required to produce "ON" or "OFF" state.

TYPICAL PERFORMANCE CHARACTERISTICS
rDS(on)

(Per Channel)

rDS('lZl vs POWER SUPPLY VOLTAGE

vs VANALOG SIGNAL

CHARGE INJECTION vs VANALOG
(SEE FIG, 3) CL = 10,OOOpF
4Or---~~~~~~~~~

'00
120

I 25r-1-·-t~--+-~~--~~
30

80

§

.

§

i

60

i

eo
80

Q

a:

100

40

20

15r-+--t~--+-~~--~;

o

40

+,:zrc

.aoc

00

"T'C

o

-10 -5 -2.5' 0

2.5

20

IS·'.....

5

7.5 -1.5

i"- r--

10

1°t:dd3::!:Ettl

"i

-10 -7.& -5 -2.5

.11SVSUPPLIU

0

2.5

5

7.5 10

• -10 -7.5'-,5 -2.5

VANALOG IVI

VANAL.OG IVI

0287-15

!

.

in

60

:

40

~

r--

80

:i!

~~.~~!

!'-or-

100

r--r-

20

o

1

CCRR _ 2OLOG 2000mVpp
VOUT(mVpp)
10 100 lk 10k lOOk 1M

ov..f"L
SWITCHED
CHANNEL

FREQUENCY (Hz)

r-

I
I

I

I
I

I
I

I
3V

5

7.5 10

0287-16

0287-14

120

0 2.5

VANALOCi (V)

I

looll

:
VOUT

L ....

4-o-t>- I
~----':--t~

.

Sill

0287-17

0287-18

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE exCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRess. IMPliED OR STATUTORY, INCt.UDING THE IMPliED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typIcsl vs/U8s MWJ besn ahsnIDftNIzed but srs not tssted.

8-84

.O~OIL i
CII
o

IH5048-IH5051
TYPICAL PERFORMANCE CHARACTERISTICS

~

(Per Channel) (Continued)

CXI
I

i

-120
-100

!
(
~

CII

o

I'

...
CII

I'~

-80

r-r-r-

-60

OFF STATE
~
OEPENOS ON PART~-

-40

l-----o

Your

1

-20

1000

OIRR = 20LOG 2000mVpp
VOur(m¥iiPi
1Hz 10Hz 100Hz lk 10k lOOk 1M

o

0287-20

FREQUENCY (Hz)

0287-19

POWER SUPPLY QUIESCENT CURRENT
va LOGIC FREQUENCY RATE

''''

~

/

lDO

~

!
!
-~

I

V
3V

~

IV

I..--r---.I

~olrl-

I

10

/

/1
10

0287-22
lDO

1k

1011

lOOk

LOGIC FREQUENCY@ 10% DUTY CYCLE IH~I

0287-21

•

INTERSIL'S SOLE ANO EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PROOUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONOITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tesf9d.

8·85

:: IH5052/IH5053

~ QUAD CMOS Analog Switch

:::::.
(\I
II)

o
II)
~

GENERAL DESCRIPTION

FEATURES

The IH5052/3 analog switches use an improved, high
voltage CMOS technology, which provides performance advantages not previously available from solid state switches.
Early CMOS switches were destroyed when power supplies
were removed with an input signal present. The INTERSIL
CMOS technology has eliminated this serious systems
problem. Key performance advantages are TIL compatibility and ultra low-power operation - the quiescent current
requirement is less than 10pA
The IH5052/3 also guarantees Break-Before-Make
switching. This is accomplished by extending the tON time
(400ns TYP.) such that it exceeds tOFF time (200ns TYP.).
This insures that an ON channel will be turned OFF before
an OFF channel can turn ON, and eliminates the need for
external logic required to avoid channel to channel shorting
during switching. With a logical "0" (O.8V or less) at its control inputs, the IH5052 switches are closed, while the
IH5053 switches are closed with a logical "1" (2.4V or
more) at its control inputs.

• Switches Greater Than 20Vpp Signals With ± 15V
Supplies
• Quiescent Current Less Than 10,..A
• Overvoltage Protection to ± 25V
• Break-Before-Make Switching toff 100ns, ton 250n8
Typical
•
•
•
•

TTL, CMOS Compatible
Non-Latching With Supply Turn-Off
IH5052 4 Normally Closed Switches
IH5053 4 Normally Open Switches

• Low RDS(ON) 500 Typical

ORDERING INFORMATION
IH505X

C

I

JE

~ p"""

JE= 16-Pin CERDIP
DE= 16-Pin Ceramic DIP
(Special Order Only)

Temperature Range
M = Military
C = Commercial
L -_ _ _ _ _ _ _ _

Basic Part Number

OUTLINE DWGS
DE,JE
DUAL-IN-LlNE PACKAGE

1

$,

y'
(SUBSTRATE)

v,

SWITCH STATES ARE

FOR LOGIC "1" INPUT

0288-1
0288-2

Figure 1: Functional Diagram

Figure 2: Pin Configurations

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characteriz9d but are not tested.

8-86

.U~OI!..

IH5052/IH5053

i

UI

o

UI

ABSOLUTE MAXIMUM RATINGS

N

Power Dissipation ............................. 450mW
(All Leads Soldered to a P.C. Board)
Derate 6mW I'C Above 70'C

v+-v- ....................................... <36V
v+-vo ....................................... <30V
Vo-V- ....................................... <30V
vo-vs ...................................... < ±22V
VL-V- ........................................ <33V
VL -VIN ........................................ <30V
VL -GND ...................................... <20V
VlwGND ..................................... <20V
Current (Any Terminal) ........................ <30mA
Storage Temperature ................ -65'C to + 150'C
Operating Temperature .............. - 55'C to + 125'C
Lead Temperature (Soldering, 10sec) ............. 300'C

ELECTRICAL CHARACTERISTICS

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress rstings only
and functional operation of the device at these or any other conditions

i
UI
oUI

Co»

above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

(TA = 25'C, V+ = + 15V, v- = -15V, VL = + 5V)
MinIMax Limits

Per Channel
Military

Test Conditions
Symbol

.......

Characteristic

Commercial

-55'C + 25'C + 125'C 0

Units

+ 25'C +70'C

IIN(ON)

Input Logic Current

VIN = 2.4V (IH5053) = 0.8V (IH5052)

10

±1

10

±10

p.A

IIN(OFF)

Input Logic Current

VIN = 0.8V (lH5053) = 2.4V (IH5052)

10

±1

10

±10

p.A

rOS(ON)

Drain-Source On
Resistance

Is= 10mA, Vanalog= -10Vto + 10V

75

75

100

80

80

100

0

IlrOS(ON) Channel to Channel
rOS(ON) Match

25
(typ)

30
(typ)

0

VANALOG Min. Analog Signal
Handling Capability

±11
(typ)

±10
(typ)

V

IO(OFF) / Switch OFF Leakage VANALOG= -10V to + 10V
Current
IS(OFF)

±1

100

±5

100

nA

±2

200

±10

100

nA

IO(ON)
+IS(ON)

Switch On Leakage
Current

Vo=Vs= -10Vto + 10V

toN

Switch "ON" Time

RL = 1kO, Vanalog= -10Vto + 10V
See Fig. 3

500

1000

ns

tOFF

Switch "OFF" Time

RL = 1kO, Vanalog= -10V to + 10V
See Fig. 3

250

500

ns

Q(INJ.)

Charge Injection

See Fig. 4

15
(typ)

20
(typ)

mV

OIRR

Min. Off Isolation
Rejection Ratio

f= 1MHz, RL = 1000, CL:5:5pF
See Fig. 5

54
(typ)

50
(typ)

dB

1+

+ Power Supply
Quiescent Current

1-

- Power Supply
Quiescent Current

IVL

+5VSupply
Quiescent Current

CCRR

Min. Channel
to Channel
Cross Coupling
Rejection Ratio

V+ = +15V, V- = -15V, VL = +5V
withGND

10

10

100

10

10

100

p.A

10

10

100

10

10

100

p.A

10

10

100

10

10

100

p.A

One Channel Off

54
(typ)

50
(typ)

dB

NOTE 1: Typical values are for design aid only, not guaranteed and not subject to production testing.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been characterized but are not tested.

8-87

•

(II)

10

o

IH5052/IH5053

.m

10

Z TEST CIRCUITS

:::
C\I
10

o

10

:!:

.-0INPUT
LOGIC

-c»l="h

@1MHz

Tn

~o

LOQICINPUT

-=-=
~YOOT

(NO~_

-=

'lOUT

1'000

'.... I-::-'1ill

0288-5

0288-4

0288-3

Figure 3

Figure 5

Figure 4

NOTE 1: The 5053 is turned on by high "1" logic inputs and the 5052 is turned on by low "0" inputs; however O.BV to 2.4V describes the min. range for switching
properly. Refer to logic diagrams to see absolute value of logic input reauired to produce "ON" or "OFF" state.

TYPICAL PERFORMANCE CHARACTERISTICS

(Per Channel)

ros(ON)vs
POWER SUPPLY VOLTAGE

ros(ON) vs V ANALOG SIGNAL

'00

'10

+1J. C _......

10

O

",10

+

:.

soc

~

·cl=

"40

20

--

Is = 1mA
@ ±15V sUPP IES

o
-5 -2.5 0

-10 -7.5

2.5

5

7.5

.
s.
"
.
'40

,

'00

±,
±,

10

±tl

8

......

-

io"""

......
i.-

-10 -7.$ -5

-2.1

0

2.5

5

i

7.5

10

,

I

f!l

II

I'FYOUT
,oon
I

I
I

OUT

TTL LEVEU

100

tk

tOk

tOOk

.IL
SWITCHED
CHANNEL

1M

L-

+o-t>I

CpR = 120~OGI'y_YPP
(mY..)

0

2.$

5

7.5

10

0288-8

~:..- +O-t>--I.!
.........

10

-10 -1.5 -5 -2.5

r------..,

'I'-

1

': t;1;±::t:t:Et:tj
YANAlOG (V)

10

o

j

0288-7

..... r-- .....

20

I

'1ANAlOG (V)

028B-6

....

1-+-++--+-1-1-+--1

.. I-t-++-t-i-I-t--l
30 1--+--+-1'-+--+-1--+--1
• 251--+--+-I--+--+-I--+--l
20 1---+--+-1__+--+-1__+--1

40

CROSS COUPLING REJECTION vs FREQUENCY

'00

'5r-'--r~r-.--r-'--~-'

40

o

10

YANALOG (V)

'20

CHARGE INJECTION vs V ANALOG
(SEE Figure B) CL = 10,OOOpF

-,..,+-~

__~

I

L----~lJ

100n

'REO\IINCY (Hz)

*

2Y..
@lMHz

51n

0288-9
0288-10

Cross Coupling Rejection
Test Circuit

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are not tssted.

8-88

IIJD~OlL

IH5052/IH5053

i

CII

o
TYPICAL PERFORMANCE CHARACTERISTICS

CII

~

(Per Channel) (Continued)

i

OFF ISOLATION vs FREQUENCY
-'20

-'OG
ii

-10

~

-10

"',,-1\

CII
Co)

2Vpp
@1MC

1\1\

~

:

CII

o
510

-

--

...

OFFITATE

-20
OIAR "" 2OLOG VOUT 'MVpp)

_v••

o
1Hz

10HI 100Hz 1k

10k

1_

1M

FREQUENCY (Hz)

0288-'2
0288-11

Off Isolation Teat Circuit

POWER SUPPLY QUIESCENT CURRENT va
LOGIC FREQUENCY RATE
C 1000

V
v
V

.3

~
'":"

.OG

0:

0:

~

~

J

LOGIC IN

,....,

~

L-.

V

0
+

'"'"

,...,

TTL LEVEL

.0

vV'

V

0288-14

Logic Input Waveform

V
1D
100
til
101c
100II
LOGIC 'REQUINCY @ ,"" DUTY CYCLE (Hz)

0288-13

r---------., -IIV
I
I
I
I
I

+1IV

0288-15

Figure 6:

+ 1SV Open Collector TTL Interface to IHSOS2ISOS3

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but 8f'9 not tested.

8-89

=
IH5052/IH5053
o

10

z

=::.

APPLICATIONS
PROGRAMMABLE GAIN NON·INVERTING AMPLIFIER WITH SELECTABLE INPUTS

&\I
10

o

10

!

v... -"'It---oO""! .....i;t.....,d
eM.

--m---_'f

"""-*--->"1

....

ClIo

n

0288-16

Figure 7: Active Low Pase Filter with Digitally Selected Break Frequency
_DalWnCH

DICODEII

IIUlI
lIDUI_ 0-11--""
IlATi

I.

-

QI::t'+-+-::1~~

J H

....

D.

FLOP

VINil

"_,.0
liz

I.

VIN3

D.

v,..
liz

DUAl. J-II pup FLOP
PDSSIIIUTlU

alNl'UT_
_ _IUTIII

c_·CD4Dt7

TTL ·1113_tO
CIIQS"'13C1M013

TTL·_n

EMAllLE o-_ _ _ _ _ _ _J

OUT

0288-17

TRUTH TABLE (IH5052)
Enable

0
1
1
1
1
1

Mux
Sequence
Rate

Sequencer
Output
21
20

0
0
1 pulse
2 pulses
3 pulses
4 pulses

0
0
1

0
1

0
0
0
1
1

Switch States
(-Denotes Off)
SW1

SW2

SW3

SW4

ON
-

-

-

ON

ON

ON
-

0
0
Figure 8: 4-Channel Sequencing MUX

-

INTERSIL'S SOLE AND EXCWSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE:AH_-- _ _ butBlBnot Ios/Sd.

8·90

IH5052/IH5053
A LATCHING DPDT SWITCH
The latch feature insures positive switching action in response to non-repetitive or erratic commands. The A1 and
A2 inputs are normally low. A HIGH input to A2 turns 81 and
82 ON, a HIGH to A1 turns 83 and 84 ON. Desirable for use
with limit detectors, peak detectors, or mechanical contact
closures.

.,.15Y

·5V

-5V

VL
S,

TRUTH TABLE (IH5052)

A,
OUT 1

State of Switches
After Command

Command
A,

53
QUAD 2 INPUT
NANDGAYES

5,

nL -DM7400
OR DM5400
CMOS - CD4011

or OM74COO

A2
0
0

A1
0

1
1

0

1
1

83&84
81 &82
same
same
on
off
off
on
INDETERMINATE

0288-18

Figure 9: A Latching DPDT

•
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bgen characterized but are not fBSted.

8-91

~ IH5140-IH5145
:. High-Level
: CMOS Analog Switch

.
.;n

~ GENERAL DESCRIPTION

FEATURES

j'

•
•
•
•
•
•
•

o

!i

The IH5l40 Family of CMOS switches utilizes Intersil's
latch-free junction isolated processing to build the fastest
switches currently available. These switches can be toggled
at a rate of greater than 1MHz with super fast ton times
(80ns typical) and faster toll times (50ns typical), guaranteeing break before make switching. This family of switches
combines the speed of the hybrid FET DG180 family with
the reliability and low power consumption of a monolithic
CMOS construction.
OFF leakages are guaranteed to be less than 200pA at
25·C. Very low quiescent power is dissipated in either the
ON or the OFF state of the switch. Maximum power supply
current is 1JJ-A from any supply and typical quiescent currents are in the 10nA range which makes these devices
ideal for portable equipment and military applications.
The IH5l40 Family is completely compatible with TTL
(5V) logic, TTL open collector logic and CMOS logic. It is pin
compatible with Intersil's IH5040 family and part of the
DG180/l90 family as shown in the switching state diagrams.

•
•
•
•

Super Fast Break-Before-Make Switching
ton 80ns Typ, toff 50ns Typ (SPST Switches)
Power Supply Currents Less Than 1JJ-A
OFF Leakages Less Than 100pA @ 25'C Typical
Non-latching With Supply Turn-off
Single Monolithic CMOS Chip
Plug-in Replacements for IH5040 Family and Part of
the DG180 Family to Upgrade Speed and Leakage
Greater Than 1MHz Toggle Rate
Switches Greater Than 20Vp-p Signals With ± 15V
Supplies
TTL, CMOS Direct Compatibility
Internal Diode in Series with V+ for Fault Protection

ORDERING INFORMATION
Order
Part Number

Function

v'
Temperature
Range

Package

IH5140 MJE
IH5140 CJE
IH5140 CPE
IH5140 MFD

SPST
SPST
SPST
SPST

16 Pin
16 Pin
16 Pin
14 Pin

CERDIP
CERDIP
Plastic DIP
Flat Pack

-55'C to 125'C
O'Cto 70'C
O'Cto 70'C
- 55'C to 125'C

IH5141
IH5141
IH5141
IH5141

Dual SPST
Dual SPST
DualSPST
DualSPST

16 Pin
16 Pin
16 Pin
14 Pin

CERDIP
CERDIP
Plastic DI P
Flat Pack

- 55'C to 125'C
O'Cto 70'C
O'Cto 70'C
- 55'C to 125'C

IH5142 MJE
IH5142 CJE
IH5142 CPE
IH5142 MFD

SPDT
SPDT
SPDT
SPDT

16 Pin
16 Pin
16 Pin
14 Pin

CERDIP
CERDIP
Plastic DIP
Flat Pack

- 55'C to 125'C
O'Cto 70'C
O'Cto 70'C
- 55'C to 125'C

IH5143 MJE
IH5143 CJE
IH5143 CPE
IH5143 MFD

DualSPDT
DualSPDT
Dual SPDT
dual SPOT

16 Pin
16 Pin
16 Pin
14 Pin

CERDIP
CERDIP
Plastic DIP
Flat Pack

- 55'C to 125'C
O'Cto 70'C
O'Cto 70'C
- 55'C to 125'C

IH5144 MJE
IH5144 CJE
IH5144CPE
IH5144 MFD

DPST
DPST
DPST
DPST

16 Pin
16 Pin
16 Pin
14 Pin

CERDIP
CERDIP
Plastic DIP
Flat Pack

-55'Cto 125'C
O'Cto 70'C
O'Cto 70'C
- 55'C to 125'C

IH5145 MJE
IH5145 CJE
IH5145 CPE
IH5145 MFD

Dual
Dual
Dual
Dual

16 Pin
16 Pin
16 Pin
14 Pin

CERDIP
CERDIP
Plastic 01 P
Flat Pack

- 55'C to 125'C
O'Cto 70'C
O'Cto 70'C
- 55'C to 125'C

MJE
CJE
CPE
MFD

DPST
DPST
DPST
DPST

loon
IJ:tTo-'IfII',-+-ll<-...,

0291-1

Figure 1: Functional Diagram Typical Driver!
Gate - IH5142

Note: 1. Ceramic (side braze) devices also available; consult factory.
2. MIL temp range parts also available with MIL-STD·883 processing.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY AATICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

8-92

IID~OI!:.

IH5140-IH5145 Family
ABSOLUTE MAXIMUM RATINGS
v+ -v- ...................................... <36V
v+ -vo ...................................... <30V
Vo - v- ..............................•....... <30V
Vo-Vs ..................................... <±22V
VL-V- ...........................•..••......• <33V
VL - VIN ............................•.........• <30V
VL ......•................•.......•..•......... <20V
VIN ...................•....................... <20V

Current (Any Terminal) .....•.................. < 30mA
Storage Temperature ................ -65·C to + 150·C
Operating Temperature ..•.•......... - 55·C to + 125·C
Lead Temperature (Soldering 10sec) .............. 300·C
Power Dissipation ............................. 450mW
(All Leads Soldered to a P.C. Board)
Derate 6 mW
Above 70·C

rc

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the davice. These are stress ratings only and functional
operation of the davice at these or any other oondilions above those indic8ted In the operational ssctions of the spscifications is not implied. Exposure to absolute
maximum rating oonditions for extended periods may affect davice reliability.

ELECTRICAL CHARACTERISTICS
Characteristic

I

i

......
CII

CII

l

a

:

(@ 25·C, v+ = + 15V, v- = -15V, VL = + 5V)

Per Channel
Symbol

i

...o...
CII

MinIMax Limits
Test Conditions

Military
-55·C

Commercial

+25"C

+ 125·C

0

+25"C

+700C

Units

LOGIC INPUT
IINH

Input Logic Current

VIN=2.4V Note 1

±1

±1

10

±10

10

fJ-A

IINL

Input Logic Current

VIN = 0.8V Note 1

±1

±1

10

±10

10

fJ-A

rOS(on)

Drain-Source On
Resistance

Is=-10mA
VANALOG= -10Vto +10V

50

50

75

75

100

0.

ArOS(on)

Channel to Channel
rOSlon) Match

25
(typ)

30
(typ)

0.

VANALOG Min. Analog Signal
Handling Capability

± 11
(typ)

±10
(typ)

V

SWITCH
75

10(oft)+
IS(off)

Switch OFF Leakage Vo= +10V, Vs= -10V
Current
Vo= -10V, VS= +10V

±.5
±.5

100
100

±5
±5

100
100

nA

10(on)+
IS(on)

Switch On Leakage
Current

Vo=Vs=-10Vto +10V

±1

200

±2

200

nA

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

One Channel Off; Any Other
Channel Switches
See Performance Characteristics

ton
toft

Switch "ON" Time
Switch "OFF" Time

See switching time specifications and timing diagrams.

Q(INJ.)

Charge Injection

See Performance Characteristics

OIRR

Min. Off Isolation
Rejection Ratio

f=1MHz, RL = 1000., CLS:5pF
See Performance Characteristics

50
(typ)

dB

10
(typ)

15
(typ)

pC

54
(typ)

50
(typ)

dB

54
(typ)

SUPPLY
1+

+ Power Supply
Quiescent Current

1-

- Power Supply
Quiescent Current

V+ = + 15V, V -= -15V,
VL= +5V

IL

+5VSupply
Quiescent Current

See Performance Characteristics

IGNO

Gnd Supply
Quiescent Current

1.0

1.0

10.0

10

10

100

fJ-A

1.0

1.0

10.0

10

10

100

fJ-A

1.0

1.0

10.0

10

10

100

fJ-A

1.0

1.0

10.0

10

10

100

fJ-A

NOTES: 1. Some channels are turned on by high (1) logic Inputs and other channels are turned on by low (0) inputs; howaver O.BV 10 2.4V describes the min.
range for switching properly. Refer to logic diagrams 10 find logical value of logic input required to produce ON or OFF slate.
2. Typical values are for design aid only, not guaranteed and not subject to production teallng.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTAEILITY AND FITNESS FOR A PARTICULAR USE.
NOTE; All typical values haV9 be9n chanlctsrlzed but IIIB not tested.

8-93

III

~

IH5140-IH5145 Family

:.

TYPICAL PERFORMANCE CHARACTERISTICSr-_ _ _ _ _ _ _ _ _ _ _---'\

'i!

..
...

10

90

10

Z

I

so

o

10

~

70

!a
J
~

:

T

'j

....

!, ! I

!i

,

.0

I

i

,

!
50

[

1-+-

!

t--.

40N-

I

2s·c1

I

I

'2

0

i--

30

I,

"

IH~141

I

I

I

I

-'2O~==t:==::::t---r---lr---i
i -.00

DATA

~

-80

>~

--;:- ...
}

[

+12S'C

-20
C-1.,F
SOCKET ON COPPER GROUNO 'LANE JIG

-55'C

20
"0

·s

.. ..

-2

-.

-4

-s

ANALOG SIGNAL VOL lAGE (V)

-.0

FREOU£NCY (HI)

0291-2

rOS(on) vs. Temp., @ ± 15V,
+5VSupplies

"OFF" Isolation vs. Frequency

2.8."-rrnrm--r,..,-rrr'TTl"-...,.......,.....,..,..,,.m
2.• 1------li-------+-....:...-....:.......:....:.:.j

.OOr---r---r---r-~--~--~---,--_.--~--_,

9O~---+t-~*I.,-+.\.!.-1 S+U~PL---t'EsV_-i-I,

2AI-----------4-----------~----------~
2.2~-----__+-

-J--.-j

55Iv ..:.5v
--

2.01\-------+-

801--+--1-'-+.----h"""j.....=~'L.l--+---+-__I
! I : I I I
T
"'25"C
60
i
I
\
1
I ! IH5'41 DATA
I

-+-~
i i --II
iT--T

"

A

rr-j

I

I

e

50

:

f

i

I ' I
I

I

.. ::::j30

-r--~

i

[

:

I

I

I

..rLJ'L.:3V

J.~--+--

~"0V, +5V,SUPPLIES

I-!l

!

t---ij--+---+-i-i---i

"5V. +5v SUPPLIES

P-4OOrI,

i

r

100

~~0--~••~~••~~~L-~.2~~0---~2-·-_4J----~~--1.-~-10
ANALOG SIGNAL VOL TAGE (V)

'"

STROBE INNT

'I

I I

0291-5

T _

PERIOD OF PULSE REPETITION RATE

1000

<.,s)

0291-3

0291-6

rOS(on) vs. Power Supplies

Power Supply Currents vs. Logic Strobe Rate

-120~=::::=t;;;;;;:;~;:::~t==j===j
v""'
10FF CHANNEL}

-100

i

'0

g

'.,-'---r--,')

SCOPEJ..·
-80

i

~

-60\--------'>-

>§ _40
-20
-10

-5

o

+5

+10

ANALOG SIGNAL VOLTAGE (V)

Charge Injection vs. Analog Signal

0291-4

FREQUENCY 1Hz;

0291-7

Channel to Channel Cross
Coupling Rejection vs. Frequency
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RE:SPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been characterized but are not tested.

8-94

IH5140-IH5145 Family
SWITCHING TIME SPECIFICATIONS
(ton. toll are maximum specifications and ton-toll is minimum specifications)
Part Number Symbol

Characteristic

Military

Test Conditions
-55°C

IH51405141

IH51425143

IH51445145

Commercial

+ 25°C + 125°C

0

Units

+ 25°C + 70°C

ton
toll
ton-toll

Switch "ON" time
Switch "OFF" time
Break-before-make

Figure 2'

100
75
10

150
125
5

ns

ton
toll
ton-toll

Switch "ON" time
Switch "OFF" time
Break-before-make

Figure 3

150
125
'10 (typ)

175
150
5

ns

ton
toll
ton-toll

Switch "ON" time
Switch 'OFF" time
Break-before-make

Figure 2"

175
125
10

250
150
5

ns

ton
toll
ton-toll

Switch "ON" time
Switch "OFF" time
Break-before-make

Figure 3

200
125
*10 (typ)

300
150
5

ns

ton
toll
ton-toll

Switch "ON" time
Switch "OFF" time
Break-before-make

Figure 4'

175
125
10

250
150
5

ns

ton
toft
ton-toll

Switch "ON" time
Switch "OFF" time
Break-before-make

Figure 5*

200
125
10

300
150
5

ns

ton
toll
ton-toll

Switch "ON" time
Switch "OFF" time
Break-before-make

Figure 2'

175
125
10

250
150
5

ns

ton
toll
ton-toil

Switch "ON" time
Switch "OFF" time
Break-before-make

Figure 3

200
125
'10

300
150
5

ns

NOTE: SWITCHING TIMES ARE MEASUREO

@

90% PTS.

'" Typical values for design aid only, not guaranteed nor subject to production testing.

NOTE: SWITCHING TIMES ARE MEASURED @ 9O%PTS.
ton

+ 15Y

16 "lOY

toft

r- -p--

=-t

!..riv,","'P

~INPUT
~
:~
I +15V : I
O Y r - I LOGIC INPUT

+15V

)-----'

~

OY!

L

~

lOY F T

II

-11-- --l iton

toff

0291-8

Figure 2.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

8-95

•

i' IH5140-IH5145 Family
~
II)

Irr:-1

.......

VQUTA

II)

z

1

10pF

"j

o

2

lK!2

.......

3

0

-=- -=-

II)

+3V

o
o

~

~
TTL INPUT

10)----'
0!10V

0291-9

Figure 3.

tON

tOFF

I +lOV

!I
I

II
I I

+15V

~
TTL INPUT

+lSV

I

+15V

VOUT A OR B

: 10%
II
i I

T'LINPUT
OV
I
~
I

10pF

o

10V

I

i I

I

I I

I

I I

0291-10

Figure 4.

+3V

OV,iL
TTL INPUT

0291-11

FigureS.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vslues havs been characterized but arB not tsst8d.

8-96

.O~OIl.

IH5140-IH5145 Family
FLATPACK (FD·2)
v,

0

DIP (JE, PEl

I

v,

v'

..i...
..i...
(II

(II
(II

...
\\I

!.

~
GNO

0291-12
0291-13

SPST
IH5140 (roS(on) < 750)
FLATPACK (FD·2)
v,

DIP (JE, PEl

v'

,N,"
,N,

v,

0,

5,

o,

'N,

.

'N,

0,

Do

"
0291-14

0291-15

DUALSPST
IH5141 (rOS(on)<750)
FLATPACK (FD-2)

v,

DIP (JE, PEl

v,

v'

•

v'

"
"

0,

s,

,

.."

0,

_.J

","0

0,

0,

"
0291-17
0291-18

SPDT
IH5142 (roS(on)<75 0)

Figure 6: Switching State Diagrams

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical va//J8S have been charscterlzsd but are not tested.

8-97

~

'E1\1
....

....
....

IH5140-IH5145 Family
FLATPACK (FD-2)

DIP (JE, PEl (DG191 EQUIVALENT)

II)

II)

x

'i
o

_"~~D2D,

S,o':'t----<>"f1'+:-oD'

~

$3

'N,
'N,

II)

!

03

<>-:1----<>"'+:-O D,
D.

0291-20
0291-21

DUALSPDT
IH5143 (rOS(on) < 75!l)

SWITCH STATES ARE FOR LOGIC "1" INPUT
FLATPACK (FD-2)

DIP (JE, PEl

s, <>'-t-----o-r"+-o D,
.. o-'-t-----o-:-,""'i~D'

o:.:.f-{:r-(>- -

s, O-1----ol"+-<>D,

.. o-t----o.....+-c ..

I
J

0291-22
GND

0291-23

DPST
IH5144 (rOs(on) < 75n)
FLATPACK (FD-2)

DIP (JE, PEl (DG185 EQUIVALENT)

S,

0,

53

D3

'N,o-''HJ-i>

0291-25
0291-26

DUAL DPST
IH5145 (rOS(on) < 75!l)

Figure 6: Switching State Diagrams (Continued)

INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

8-98

~O~OIL

IH5140-IH5145 Family
TYPICAL SWITCHING WAVEFORMS

i(II

...
~

oI

SCALE: VERT.=5V/DIV. HORIZ.=100ns/DIV.

i(II

TTL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 8)

...
~

(II

-:

!.

~

0291-27

0291-28

0291-29

TTL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 9)

+125"C
0291-30

0291-31

TTL OPEN COLLECTOR LOGIC DRIVE
(Corresponds to Figure 10)

0291-32

TTL OPEN COLLECTOR LOGIC DRIVE
(Corresponds to Figure 11)

+2S0C
0291-33

0291-34

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

8-99

•

~

IH5140-IH5145 Family

:.

APPLICATION NOTE

.

II)

...

II)

~

o

..
...
II)

:5

IIlD~OI!..

To maximize switching speed on the IH5140 family, TIL
open collector logic (15V with a 1kO or less collector resistor) should be used. This configuration will result in (SPST)
ton and toll times of 80ns and 50ns, for signals between
-10V and + 10V. The SPOT and OPST switches are approximately 30ns slower in both ton and toft with the same
drive configuration. 15V CMOS logic levels can be used (OV
to + 15V), but propagation delays in the CMOS logic will
slow down the switching (typical 50ns -+ 100ns delays).
When driving the IH5140 Family from either +5V TIL or
CMOS logic, switching times run 20ns slower than if they
were driven from + 15V logic levels. Thus ton is about
105ns, and toft 75ns for SPST switches, and 135ns and
105ns (ton, toll) for SPOT or OPST switches. The low level
drive can be made as fast as the high level drive if ± 5V
strobe levels are used instead of the usual OV -+ + 3.0V
drive. Pin 13 is taken to -5V instead of the usual GNO and
strobe input is taken from +5V to -5V levels as shown in
Figure 7.
The typical channel of the IH5140 family consists of both
P and N-channel MOSFETs. The N-channel MOSFET uses
a "Body Puller" FET to drive the body to -15V (± 15V supplies) to get good breakdown voltages when the switch is in
the off state (See Fig. 8). This "Body Puller" FET also allows the N-channel body to electrically float when the
switch is in the on state producing a fairly constant ROS(ON)
with different signal voltages. While this "Body Puller" FET
improves switch performance, it can cause a problem when
analog input signals are present (negative Signals only) and
power supplies are off. This fault condition is shown in Figure 9.
Current will flow from -10V analog voltage through the
drain to body junction of 01, then through the drain to body
junction of 03 to GNO. This means that there is 10V across
two forward-biased silicon diodes and current will go to
whatever value the input signal source is capable of supplying. If the analog input Signal is derived from the same supplies as the switch this fault condition cannot occur. Turning
off the supplies would turn off the analog signal at the same
time.
This fault situation can also be eliminated by placing a
diode in series with the negative supply line (pin 14) as
shown in Figure 10. Now when the power supplies are off
and a negative input signal is present this diode is reverse
biased and no current can flow.

OUTA

ffi

(16
z

~

0
OUT.

ffi

~

ili

;;

~

~

~
~

-0000.1

16 ANALOG IN (CHANNEL A)

r-,

~
ANALOG OUT

ffi

9

CMOS
LLEVEL

INPUT
STROBE

ANALOG IN (CHANNEL B)

0291-35

Figure 7.

t15V FROM
DRIVERS

-15V

0291-36

Figure 8.

GNO WHEN POWER
SUPPLIES ARE OFF

"

0291-37

Figure 9.

1N914
OR EQUIVALENT

INA
T2LAIN

~ +5V
X
~ +15V
10

T2L81N

9

INa

.....
,...

-16V

*
0291-38

Figure 10.

lNTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

8-100

IH5140-IH5145 Family
APPLICATIONS

+15V
+15V

2

6

>--+--o OUTPUT

3
ANALOG
INPUT

51.n
-15V
10,000PF
POLY-=- STYRENE

I

LOGIC INPUT

+3V = > SAMPLE MODE
OV = > HOLD MODE

IH5143

0291-39

Figure 11: Improved Sample and Hold Using IH5143

16

+VANALOG

..rL
-15V
13
12 -::+5V
11
+15V
10

9
2R

2R
R

IH5143

R

+VANALOG

TTL
LOGIC
STROBE

.Jl....
TTL
LOGIC
STROBE

R
ETC.

ETC.

0291-40
EXAMPLE: If -VANALOG= -10YDC and

+ VANALOG = + 10VDC then

Ladder Legs are switched between ±10VDC, depending upon state of Logic Strobe.

Figure 12: Using the CMOS Switch to Drive an R/2R Ladder Network (2 Legs)

INTEASIL'S SOLE AND EXCLUSiVE WARRANTY OBLIGATION WITH AESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE" All typICal values have been characterized but are not tested.

8·101

IH5140-IH5145 Family
APPLICATIONS

(Continued)

lOOk!:!

lOOkS!

BANDPASS

OUTPUT

LO PASS

OUTPUT

68k!!
R

·3V

-ILov
lOGIC

STROBE

0291-41
CONSTANT GAIN, CONSTANT Q, VARIABLE FREQUENCY FILTER WHICH PROVIDES SIMULTANEOUS LOWPASS, BANDPASS, AND HIGHPASS OUTPUTS. WITH THE COMPONENT VALUES SHOWN, CENTER FREQUENCY WILL BE 235Hz AND 23.5Hz FOR HIGH AND LOW LOGIC INPUTS RESPECTIVEL Y, Q ~ 100, AND GAIN ~ 100.

fn=CENTER FREQUENCy=_1271" RC

Figure 13: Digitally Tuned Low Power Active Filter

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATU"TORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

8-102

.n~nll;

IH5148 -IH5151
High-Level CMOS
Analog Switches

~

CO
I

i
~

GENERAL DESCRIPTION

FEATURES

The IH5148 family of solid state analog switches are designed using an improved, high voltage CMOS technology.
Destructive latchup has been eliminated. Early CMOS
switches were destroyed when power supplies were removed with an input signal present; the IH5148 CMOS technology has eliminated this problem.
Key performance advantages of the 5148 series are TTL
compatibility and ultra low-power operation. RDS(on) switch
resistance is typically in the 140 To 180 Area, for signals in
the - 10V to + 10V range. Quiescent current is less than
10pA The 5148 also guarantees Break-Before-Make
switching which is logically accomplished by extending the
tON time (200nsec typ.) such that it exceeds tOFF time
(120nsec typ.). This insures that an ON channel will be
turned OFF before an OFF channel can turn ON. The need
for external logic required to avoid channel to channel
shorting during switching is thus eliminated.
Many of the devices in the 5148 series are pin-far-pin
compatible with other analog switches, and offer improved
electrical characteristics.

• Low Ros(ON) - 2S0
• Switches Greater Than 20Vpp Signals With ± lSV
Supplies
• Quiescent Current Less Than 100p.A
• Break-Before-Make Switching tOFF 120nsec Typ., tON
200nsec Typical

...

• TTL, CMOS Compatible
• Non-Latching With Supply Turn-Off
• Complete Monolithic Construction
• ± SV to ± lSV Supply Range

CMOS ANALOG SWITCH PRODUCT
CONDITIONING
• The Following Processes Are Performed 100"10 In
Accordance With MIL-STD-883
• Precap Visual- Method 2010, Condo B
• Stabilization Bake - Method 1008
• Temperature Cycle - Method 1010
• Centrifuge - Method 2001, Condo E
• Hermeticity - Method 1014, Condo A, C
• (Leak Rate<5xl0- 7 atm cc/s)

ORDERING INFORMATION
Order Part
Number

Function

Package

Temperature Range

Harris
Equivalent

IH5148MJE
IH5148CJE
IH5148CPE
IH5148MFD

Dual
Dual
Dual
Dual

SPST
SPST
SPST
SPST

16 Pin CERDIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack

- 55'C to 125'C
O'C to 70'C
O'C to 70'C
- 50'C to 125'C

HI-5048
HI-5048
HI-5048
HI-5048

IH5149MJE
IH5149CJE
IH5149CPE
IH5149MFD

Dual
Dual
Dual
Dual

DPST
DPST
DPST
DPST

16 Pin CERDIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack

-55'C to 125'C
O'C to 70'C
O'C to 70'C
- 50'C to 125'C

HI-5049
HI-5049
HI-5049
HI-5049

IH5150MJE
IH5150CJE
IH5150CPE
IH5150MFD

SPDT
SPDT
SPDT
SPDT

16 Pin CERDIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack

- 55'C to 125'C
O'C to 70'C
O'C to 70'C
-50'C to 125'C

HI-5050
HI-5050
HI-5050
HI-5050

IH5151 MJE
IH5151CJE
IH5151CPE
IH5151MFD

Dual SPDT
DualSPDT
Dual SPDT
Dual SPDT

16 Pin CERDIP
16 PinCERDIP
16 Pin Plastic DIP
14 Pin Flat Pack

-55'C to 125'C
O'C to 70'C
O'C to 70'C
- 50'C to 125'C

HI-5051
HI-5051
HI-5051
HI-5051

NOTES: 1. Ceramic (side braze) devices also available; consult factory.
2. MIL temp range parts also available with MIL-STD-883 processing.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

304300-003

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

8-103

•

...
...
II)

IH5148-IH5151

II)

~ ABSOLUTE MAXIMUM RATINGS
CD
:
II)

!

V+, v- ....................................... <36V
V+, VD ........................................ <30V
VD, v- ........................................ <30V
VD, Vs ...................................... <±22V
VL, v- ....
<33V
VL, VIN ..
o. <30V
VL .....
o.
o.
<20V
VIN .....
<20V
Current(Any Terminal)
o. < SOmA
Storage Temperature ...........
-6S·C to + 1S0·C
0

0

•

0

•••

0

•••••••••

0

••

••••

0

0

0

0

••••

0

••

0"

••••••

0

0

0.00.

0

0.0

0

0

0

••••••••

0

••••••••••

0

••••

0

0

0

•

0

•

0.0

••••

•••

0

0

•

0

•••

0

0

•

0

0

0

•••

•••

•••

•

0

0

0

•

0

0

0

0"

•••••

0

•••

0

0

0

•

••

•••••

0

0

••

0

••

0

•

•••

0

••••••••

0

•••••

0

•••••

••••

0

0

0

•••

•••

NOTE: Stresses above those listed under ''Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the devica at these or any other conditions
above those indicated in the operational sections of /he specifications is not
implied. Exposure to absolute maximum rating conditions for extended peri·

0

0

•••

0

0

••••••••••••

0

0

Operating Temperature
o. -SS·C to + 12S·C
Lead Temperature (Soldering, 1Osee) ...
300·C
Power Dissipation
4S0mW
(All Leads Soldered to a PoC. Board)
Derate 6mWrC Above 70·C

0

••••

ods may affect device reliability.

+15V (V,)
11

0292-1

Figure 1: Functional Diagram (Typical Switch Schematic -IH5150 in 16 pin DIP PKG.)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE' EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but a(9 not tested.

8·104

IIlD~DIL

IH5148-IH5151
ELECTRICAL CHARACTERISTICS

Test Conditions

MIlitary

I

Commercial

-55'C + 25'C + 125'C

0

Units

+ 25'C +70'C

Input Logic Current

VIN=2.4V (Note 1)

±1

±1

±10

±1

±10

",A

IIN(OFFI Input Logic Current

VIN = 0.8V (Note 1)

±1

±1

±10

±1

±10

",A

RDS(ON) Drain-Source On
Resistance

VD= ±10V, Is= -10mA

25

25

50

30

IIN(ON)

ARDS(ON) Channel to Channel RDS(ON) Match

10
(Typ)

15
(Typ)

VANALOG Min. Analog Signal
Handling Capability

±14
(Typ)

±14
(Typ)

ID(OFF) Switch OFF Leakage Current
IS(OFF)
ID(ON) + Switch On Leakage Current
IS(ON)

VANALOG= -10Vto + 10V
VD=VS= -10Vto +10V

Q(lNJ)

Charge Injection

See Figure 4

OIRR

Min. Off Isolation Rejection Ratio

l=lMHz,RL= 1000,
CL,;:;5pF, See Figure 5

en

i

MinIMax Limits

Characteristic

Symbol

i

CD

(TA@25'C,V+=+15V,V-=-15V,VL=+5V)

Per Channel

....
..
en
en

°
°
V

±1.0

100

t2.0

100

nA

±1.0

100

t2.0

100

nA

(10)
(Typ)

(10)
(Typ)

mV

54
(Typ)

50
(Typ)

dB

~UPPLY
1+

+ Power Supply Quiescent Current

10

10

100

10

",A

1-

- Power Supply Quiescent Current V 1 = +15V, V2= -15V.

10

10

100

10

",A

IL

+ 5V Supply Quiescent Current

10

10

100

10

",A

IGND

Gnd Supply Quiescent Current

10

10

100

10

",A

CCRR

Min. Channel to Channel
Cross Coupling Rejection Ratio

50
(Typ)

dB

NOTE

VL = +5V, VR=O
One Channel Off;
Any Other Channel
Switches as per Figure 8

54
(Typ)

1. Some channels are turned on by high "1" logic inputs and other channels are turned on by low "0" inputs; however O.BV to 2.4V describes the min. range
for switching properly. Refer to logic diagrams to find logical value of logic input required to produce "ON" or "OFF" state.

SWITCHING TIME SPECIFICATION
IH5148 SPST SWITCH
Symbol

Parameter

Max

Units

ton

Switch "on" time

RL = lKO, VANAlOG= -10V

250

ns

toff

Switch "off" time

To + 10V; See Figures 3 and 6

200

ns

Test Conditions

Min

IH5149 OPST SWITCH
Symbol

Parameter

Test Conditions

Max

Units

ton

Switch "on" time

RL =lKO, VANALOG= -10V

Min

350

ns

toff

Switch "off" time

To + 10V; See Figures 3 and 6

250

ns

IH5150 & IH5151 SPOT SWITCH
Symbol

Parameter

Max

Units

ton

Switch "on" time

RL = lKO, VANALOG= -10V

500

ns

toff

Switch "off" time

To + 1OV; See Figures 3 and 6

250

ns

NOTE 2.

Test Conditions

Min

For IH5150 & IH5151 devices, channels which are off for logic input:<2.4V (Pins 3 & 4 on 5150, & Pins 3 & 4,5 & 6 on 5151) have slower Ion time, than
channels on Pins 1, 16, & 8, 9. This is done so switch will maintain break-before-make action when connected in DT configuration, i.e. Pin 1 connected in
Pin 3.

INTERSll'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

8-105

•

...

...
II)

.D~OIL

IH5148-IH5151

II)

:z:

i

CD

...
~

SWITCH STATES ARE
FOR LOGIC "1" INPUT

DIP (DE) PACKAGE

FLAT PACKAGE

DUAL SPST IH5148

II)

"

i

"

"

.,

" "

"

"

II,

"

D,

...

\I

.,

11

II,

"

11,

"

II,

"

D,

"

,-"

..."

0292-2

,-"
0292-3

DUAL DPST IH5149

'I

'I

"

"

"

" ,
" "

D,
D,

"

\I

11

II,

.,
D,

II,

D,
D,

"S,
GlD

II,

11

D,
D,

"
"

,- "

" ,-"

0292-5

GlD

0292-6

SPOT IH5150

"

'I

"
"

"
"

"

.,
"
"

D,

II

"

\I

11

D,
D,

11

"D

,-"

" ,-

0292-7

14

GIG

0292-8

DUAL SPOT IH5151

"

"

"
"

11

.,

"
" "
S, "

II,

D,

II,

11,

"
"

" "
"

\I

D,
D,

.,

D,

...

11,

.,

D,

S,

,-

" ,-"

0292-10

GlD

0292-11

Figure 2: Switching State Diagrams

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOT£;: AI! typical values have been characterized but are not tested

8-106

I!U~DIl

IH5148-IH5151
TEST CIRCUITS

)

MAlO; .Nm

'"

3V

.,n~_

-fr

m
t--

.lIll0G INPUT

ovn
3V

~:;~~

'''IC~''''''-h

INPUT

VOUl

-D--1>-

V
"'.'-

LOGIC INPUT

jll~_

.".

'O.f

i:''';'

VOUT

t

1O,"Op'J

'Op'J ."."0

ooo
0292-14

0292-13

0292-12

Figure 5

Figure 4

Figure 3

TYPICAL PERFORMANCE CHARACTERISTICS
ROS(ON)

@

5'0

(Per Channel)

± 15V, ± 5V SUPPLIES

RDSION)
(}

100
90

80
70

60
50
40
30
20
10

± 5V SUPPLIES ~
~

~r

± ~5V SUPPLIES", ~

o

-12V-l0-8-6-4-20V 2 +4V 6 8+10V+121
RoS ION) vs
ANALOG INPUT VOLTAGE
0292-15

CROSS COUPLING
REJECTION vs FREQUENCY

120

.
~

in

'"a:
CI

!:.
>""

1"' .......

100

~

OFF

............

CHANNEL

i'.

80

~

60

r--. .....

......

40

3V

INP~

20

CCRR

o1

10

20LOG 2000mVpp
Your (mVpp)
100
lk 10k lOOk 1M

SWITCHED
CHANNEL

=

r----lh
o-TD---I>- -1=1
I

I

I
I

r-

I

I

1

I

-=-

I

Your

lOOn

I
L-=I
~L~~
I

~---~

510

1

100n

FREQUENCY (Hz)

0292-17

0292-16

CROSS COUPLING
REJECTION TEST CIRCUIT
INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

8-107

i

...ca,.
CD
I

i

...caca

...

.

; IH5148-IH5151
II)

~ TYPICAL PERFORMANCE CHARACTERISTICS

..

-120

:!:

-100

(Per Channel) (Continued)

OFF ISOLATION vs FREQUENCY

CD

..
II)

=
~

"- ~
......

-80

51!)

~

u::"-

e.

""

>

......

-60

r-. .... ........

OFF STATE
~
DEPENDS ON PART~-

-40
-20

o

OIRR

1

lOOk 1M

10k

VOUT

100 !)

2000mVpp
= 20LOG VOUT
(mVpp)

1Hz 10Hz 100Hz lk

1----o

0292-19

OFF ISOLATION TEST CIRCUIT

FREQUENCY (Hz)
0292-18

POWER SUPPLY QUIESCENT CURRENT vs
LOGIC FREQUENCY RATE

~ 2000

~
::>

""

200

a:::

C>

+
a:::
w
:z::

20

....

!B.
....

..,ffi
~

:5
!:

2
1

Y

/

10

/

V
100

V

V

lk

V

vV

f=

I

T
0292-21

LOGIC INPUT WAVEFORM

10k

lOOk

LOGIC FREOUENCY @ 10% DUTY CYCLE (Hz)
0292-20

Ion

Ion

...... 1 .........'1. .

, 1+10V"

~T
II

i +3V
~CINPUT

ovi:

I,

~-10V~VOUT
-J" ~4- .....!! .....
ton

tofl

0292-22

Figure 6: Switching Time Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARAANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

8·108

mD~DI!..

IH5148-IH5151
Nulling Out Charge Injection:
Charge injection (Oinj. on spec. sheet) is caused by gate
to drain, or gate to source capacitance of the output switch
MOSFET. The gates of these MOSFETs typically swing
from -15V to + 15V as a rapidly changing pulse; thus this
30Vpp pulse is coupled through gate capacitance to output
load capacitance, and the output "step" is a voltage divider
from this combination. For example:

i

......
CII

This configuration will produce a typical charge injection
of Your S 10mVpp into the 1000pF S & H capaCitor shown.

CD

Fault Condition Protection

CII

If your system has analog voltage levels which are independent of the ± 15V (Power Supplies), and these analog
levels can be present when supplies are shut off, you
should add fault protection diodes as shown below:

I

i

...CII
...

Oinject (Vpp) '" Cgate x30V step.
CLoad
i.e.
Cgate= 1.5pF, CLoad= 1000pF, then
1.5pF
Oinject(Vpp) = 1OOOpF x 30V step = 45mVpp

IN914
i - - - - - i )I------15V

Thus if you are using switch in a Sample & Hold application with Csample = 1000pF, a 45mVpp "Sample to Hold error step" will occur.
To null this error step out to zero the following circuit can
be used:

)------.,K 1------+ 15V

IN914

0292-25

Figure 9: Adding Diodes Protects Switch
If the analog input levels are below ± 15V, the pn junctions of 013 & 015 are reversed biased. However if the
± 15V supplies are shut off and analog levels are still present, the configuration becomes:

+3V

JL

TTL STROBE

50K POT

rROM ORIVER

0292-23

Figure 7: Adjustable Charge Injection
Compensation Circuit
ANALOG INPUT

The circuit shown above nulls out charge injection effects
on switch pins 1 and 16; a similar circuit would be required
on switch pins 8 and 9.
Simply adjust the pot until VOUr=OmVpp pulse, with
VANALOG = OV.
If you do not desire to do any adjusting, but wish the least
amount of charge injection possible, then the following circuit should be used:

OUTPUT SWITCH PAIR

16

-15V

'--_ _----;QI3 P ,..--_ _--'

N

N
AFROM DRIVER
0292-26

Figure 10
+3V

JL

TTL STROBE

IOKO

39KO
-15V

0292-24

Figure 8: No-Adjust Charge Injection
Compensation Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

8-109

•

.... IH5148-IH5151
....

1Il0~OI!..

II)
II)

:z::

This structure provides a degree of overvoltage protection when supplies are on normally, and analog input level
exceeds supplies.
This circuit will switch up to about ± 18V ANALOG overvoltages. Beyond this drain(N) to body(P) breakdown VOLTAGE of 013 limits overvoltage protection .

The need for these diodes, in this circumstance, is shown
'j below:

co

....of

II)

:!:

.LQ15

.L

OV WHEN

+ 15V SUPPLY
SHUT OFF
\6 ANALOG INPUT
SAY -10V TO + 10V

OV WHEN
-15V IS
SHUT OFF

+15V

OVERVOLTAGE
ANALOG

-15V

INPUT

0292-27

Figure 11
If ANALOG in is greater than 1V, then the pn junction of
015 is forward biased and excessive current will be drawn.
The addition of IN914 diodes prevents the fault currents
from destroying the switch. A similar event would occur if
ANALOG in was less than or equal to -1V, wherein 013
would become forward biased. The IN914 diodes form a
"back to back" diode arrangement with 013 & 015 bodies.

0292-26

Figure 12

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE ANO SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE' All typical values have been characterized but 8(9 not tested.

8-110

IH5341
Dual SPST CMOS
RF /Video Switch
GENERAL DESCRIPTION

FEATURES

The IH5341 is a dual SPST, CMOS monolithic switch
which uses a "Series/Shunt" ("T" switch) configuration to
obtain high "OFF" isolation while maintaining good frequency response in the "ON" condition.
Construction of remote and portable video equipment
with extended battery life is facilitated by the extremely low
current requirements. Switching speeds are typically
ton = 150ns and toff = 80ns, and "Break-Before-Make"
switching is guaranteed.
Switch "ON" resistance is typically 4011-5011 with ± 15V
power supplies, increasing to typically 17511 for ±5V supplies. The devices are available in TO-100 and 14-pin epoxy
DIP packages.

• ROS(on)<7511
• Switch Attenuation Varies Less Than 3dB From DC
to 100MHz
• "OFF" Isolatlon>70dB Typical @ 10MHz
• Cross Coupling Isolatlon>60dB @ 10MHz
• Compatible With TTL, CMOS Logic
• Wide Operating Power Supply Range
• Power Supply Current,;; 1,..A
• "Break-Before-Make" Switching
• Fast Switching (80n8/150n8 Typ)

ORDERING INFORMATION
Part Number

Temperature
Range

Package

IH5341CPD

oto +70·C

14-pin
PLASTIC DIP

IH53411TW

-20·C to +85·C

1O-pin TO-1 00

IH5341MTW

- 55·C to + 125·C

1O-pin TO-1 00

PD

S\ 0

cY'IIo

v,
00\

~,~
S2 0

rr(o

TO·1DD

•

St

v'
002

OND

I

TOP VIEW

"'~

TOPYIEW

0295-2

Outline dwg: PO

Outline dwg: TW

Figure 2: Pin Configurations

0295-1

Figure 1: Functional Diagram
(Switches are open for a logical "0" control
input, and closed for a logical "1" control input.)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY AATICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARAANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

305528-003

NOTE' All typical values have been characterized but are not tested.

8·111

IfID~DI!..

;f') IH5341
10

aE ABSOLUTE MAXIMUM RATINGS
v+ to Ground
v- to Ground

................................. + 18V
.................................• -18V
VL to Ground ..•....•.•••.••••..••••••.••••. V+ to VLogic Control Voltage ..•..................... V+ to VAnalog Input Voltage ........................ V+ to VCurrent (any Terminal) .........................•• 50mA
Operating Temperature:
(M Version) ....................... -55·C to + 125·C
(IVersion) •.•.•...•••••.•••••••••.• -25·Cto +85·C
(C Version) .......•..•.............•.. O"C to + 70·C

Storage Temperature .......•........ - 65·C to + 150"C
Lead Temperature (Soldering. 10sec) ........•...• 300·C
Power Dissipation •••.•.•••.••••.•..•.•.•..•..• 250mW
Derate above 25·C@ ..................... 7.5mWI"C
NOTE: Stresses above /hose listed undar "Absolute MsxJmum Ratings"
may causa parmanant damage to the davlca. ThasfJ are slr9ss rstlngs only
and functional operation of the davlca at th9sa or any other conditions
above /hose/nd/ca1Bd In the operational sactIons of the speciflcatlona Is not
Irnp/IBd. Exposure to absolute maximum rstlng conditions for ext9ndad pariods may affect davlca reliability.

+1IV

-1IV

......~--+"""OSWITCH

TTL o.:.'....'VOllO\I\r_--1I_,

0295-3

Figure 3: Equivalent Schematic Diagram IH53411TW (VI of actual circuit on chip shown)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTV SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND RTNESS FOR A PARTICULAR USE.
NOTE: All typical values haVB b8sn charscterizsd but IIIlI not testsd.

8-112

IH5341
DC ELECTRICAL CHARACTERISTICS
v+ = + 15V, VL = +5V, v- = -15V, TA = 25°C unless otherwise specified.

I/C Grade Device

M Grade Device
Symbol

Parameter
Supply Voltage
Ranges
Positive Supply
Logic Supply
Negative Supply

V+
VL
V-

Typ

Test Conditions

Switch "ON"

Vo= ±5V

ROS(on)

Resistance
(Note 4)

Is= 10mA, VIN:2:2.4V
Vo= ±10V

ROS(on)

Switch "ON"
Resistance

V+=VL = +5V,
VIN=3V
V- = -5V, Vo= ±3V
Is=10mA
Is=10mA,
Vo= ±5V

-55°C + 25°C + 125°C

O"C

+ 25°C

+851 Units
+70"C

4.5>16
4.5>V+
-4> -16

(Note 3)

.:lROS(on) On Resistance
Match Between
Channels

-251

V
75

100

75

75

75

100

125

125

175

150

150

175

250

250

350

300

300

350

5

>2.4
<0.8

VIH
VIL

Logical "1" Input Voltage
Logical "0" Input Voltage

10(off)
or
IS(Off)

Switch "OFF"
Leakage
(Notes 2 and 4)

VS/O= ±5V
VIN';:0.8V
VS/O= ±14V

±0.5

50

±1.0

100

±0.5

50

±1.0

100

10(on)
+
IS(on)

Switch "ON"
Leakage

VS/O= ±5V
VIN:2:2.4V
VS/O= ±14V

±1

50

±2

100

±1

100

±2

100

liN

Input Logic Current

VIN:2:2.4Vor--

'"

.c: -3.8
~
I -3.9

50
40

I/)

-4.0
0.1

30
0.1

10

100

1

/f

SWITCH
SOURCE C>-----O"'I C
(IN)

L ___ J
I

CONTROL~.
IN~
DRIVER
TRANSLATOR

0-1

10

100

FREQUENCY (MHz)

FREQUENCY (MHz)
0295-12

0295-13

150
+ 15V --'\IIIIr-....- - - - ,

SWITCH
0--0 DRAIN
(OUn

10

vOUT,-----....:::A

ANALOG
INPUT

':'
0295-14

Figure 8: Internal Switch Configuration

DETAILED DESCRIPTION
As can be seen in Figure 8, the switch circuitry is of the
so-called "T" configuration, where a shunt switch is closed
when the switch is open. This provides much better isolation between the input and the output than a single series
switch does, especially at high frequencies. The result is
excellent performance in the Video and RF region compared to conventional Analog Switches.

r---'l- +3V
-I
L-ov
TTL IN (S1ROBE)
0295-15

'Adiust pot for OmVp.p step

@

VOUT with no analog (AC) signal present

Figure g: Charge Injection Compensation

The input level shifting circuit is similar to that of the
IH5140 Series of Analog Switches, giving very high speed
and guaranteed "Break-before-Make" action, with negligible static power consumption and TTL compatibility.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

8-115

•

; IH5341
(II)

10

:5

+sv

YOUT

+ 3V
OV

:rL

TTL
CONTROL IN

0295-16

Figure 10: Alternative Compensation Circuit

APPLICATIONS
Charge Compensation Techniques

1N914

+15V - ;........- - - - . ,

Charge injection results from the signals out of the level
translation circuit being coupled through the gate-channel
and gate-source/drain capacitances to the switch inputs
and outputs. This feedthrough is particularly troublesome in
Sample-and-Hold or Track-and-Hold applications, as it
causes a Sample (Track) to Hold offset. The IHS341 devices have a typical injected charge of 30pC-SOpC (corresponding to 30mV-SOmV in a 1000pF capacitor), at VS/D of
about OV.
This Sample (Track) to Hold offset can be compensated
by bringing in a signal equal in magnitude but of the opposite polarity. The circuit of Figure 9 accomplishes this
charge injection compensation by using one side of the device as a S & H (T & H) switch, and the other side as a
generator of a compensating signal. The 1kO potentiometer
allows the user to adjust the net injected charge to exactly
zero for any analog voltage in the - SV to + 5V range.
Since individual parts are very consistent in their charge
injection, it is possible to replace the potentiometer with a
pair of fixed resistors, and achieve less than SmV error for
all devices without adjustment.
An alternative arrangement, using a standard TIL inverter
to generate the required inversion, is shown in Figure 10.
The capacitor needs to be increased, and becomes the only
method of adjustment. A fixed value of 22pF is good for
analog values referred to ground, while 3SpF is optimum for
AC coupled signals referred to - 5V as shown in the figure.
The choice of - SV is based on the virtual disappearance at
this analog level of the transient component of switching
charge injection. This combination will lead to a virtually
"glitch-free" switch.

25,

t---I~- -ISY

0295-17

Figure 11: Overvoltage Protection Circuit

Overvoltage Spike Protection
If sustained operation with no supplies but with analog
signals applied is possible, it is recommended that diodes
(such as 1N914) be inserted in series with the supply lines
to the IHS341. Such conditions can occur if these signals
come from a separate power supply or another location, for
example. The diodes will be reverse biased under this type
of operation, preventing heavy currents from flowing from
the analog source through the IHS341.
The same method of protection will provide over ± 2SV
overvoltage protection on the analog inputs when the supplies are present. The schematic for this connection is
shown in Figure 11.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSiVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY ANO FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

8-116

IH5352
QUAD SPST CMOS
RFIVideo Switch
GENERAL DESCRIPTION

FEATURES

The IH5352 is a QUAD SPST, CMOS monolithic video
switch which uses a "Series/Shunt" ("T" switch) configuration to obtain high "OFF" isolation while maintaining good
frequency response in the "ON" condition.
Construction of remote and portable video equipment
with extended battery life is facilitated by the extremely low
current requirements. Switching speeds are typically
ton =150ns and toff=80ns, and "Break-Before-Make"
switching is guaranteed.
Switch "ON" resistance is typically 400-500 with ± 15V
power supplies, increasing to typically 1750 for ± 5V supplies.

• ROS(on) < 750
• Switch Attenuation Varies Less Than 3dB From DC
to 100MHz
• "OFF" Isolation>70dB Typical @ 10MHz
• Cross Coupling Isolation >60dB @ 10MHz
• Directly Compatible with TTL, CMOS Logic
• Wide Operating Power Supply Range
• Power Supply Current < 1",A
• "Break-Belore-Make" Switching
• Fast Switching (80ns/150ns Typ)

APPLICATIONS

ORDERING INFORMATION
Temperature
Range

Package

IH5352CPE

O'Cto +70'C

16-PIN PLASTIC DIP

IH53521JE

- 25'C to + 85'C

16-PIN CERDIP

IH5352MJE

-55'C to + 125'C

16-PIN CERDIP

Part
Number

5t

o....--------------a1"o....----o Dz

18

D,

15

V+

D2

"'2

I

I.Z~

52

4

IH5352

GID
D3

1113

53 0

a-lo....----o D3
I

I

113

o--{>---J

s, o>-------a1"o>----o D,

II

V-

10

D,

5,

I

II'~

\\

0296-2

Figure 2: Pin Configurations
Package Outline Drawing: PE, JE

0296-1

Figure 1: Functional Diagram
(Switches are open for a logic "0" control Input,
and closed for a logic "1" control input.)

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

4305529-004

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have b6en characterized but are not tested

8-117

•

ell

IH5352

:E

ABSOLUTE MAXIMUM RATINGS (TA = 25'C Unless Otherwise Noted)
Storage Temperature ................ -65'Cto + 160'C
Y+ to Ground ................................. +18Y
Y- to Ground .................................. -18Y
Lead Temperature
YL to Ground ............................... Y+ to Y(Soldering, 1Osee) ............................ 300'C
Logic Control Yoltage ........................ Y+ to YPower Dissipation:
Analog Input Yoltage ........................ Y+ to YCERDIP ................................... 450mW
Current (any terminal) ......................... < 50mA
derate 4mW /'C above 25'C
Plastic ..................................... 350mW
Operating Temperature:
(M Version) ....................... -55'C to + 125'C
derate 3mW/,C above 25'C
(I Version) ......................... -20'C to +85'C
(C Version) ........................... O'C to + 70'C

II)
f')
II)

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specificstions is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
Y+ = + 15Y, Y- = -15Y, YL = +5Y, TA = 25'C unless otherwise noted.
Maximum Ratings
Symbol

Parameter

Test Conditions

Typ
@25'C

M Grade Device

I/C Grade Device

-55'C + 25'C + 125'C -25/0'C + 25'C

Y+
YL
YROS(on)
ROS(on)

Supply Yoltage
Ranges:
Positive Supply
Logic Supply

Switch "ON"
Resistance

~ROS(on) On Resistance Match

Between Channels

+70'C

5to 15
(Note 3)

5to 15

Y

-5to -15

Negative Supply
Switch "ON"
Resistance (Note 4)

Units

+851

Is=10mAlyo= ±5Y

50

75

75

100

75

75

100

YIN>-2.4ylyo= ±10Y

100

125

125

175

150

150

175

Is= 10mA, Y+ =
YL =+5YY-= -5Y,
Yo= ±3Y, YIN= 3Y

175

250

250

350

300

300

350

Is=10mA, Yo= ±5Y

{1

5

VIH

Logical "1"
Input Voltage

>2.4

VIL

Logical "0"
Input Voltage

<0.8

10(01t)
or
IS(off)

Switch 'OFF'
Leakage
(Note 2 and 4)

YSID= ±5Y
VS/O= ±14Y
YIN:S;0.8Y

10(on)
+
IS(on)

Switch 'ON'
Leakage

VS/O= ±5Y
VS/O= ±14Y
VIN>-2.4Y

liN

Logic Control
Input Current

YIN>-2.4Vor ---_--cY'
(VIDEO INPUn

L___ __-'

DETAILED DESCRIPTION
Figure 3 shows the internal circuit of one channel of the
IH5352. This is identical to the IH5341 "T-Switch" configuration. Here, a shunt switch is closed, and the two series
switches are open when the video switch channel is open or
off. This provides much better isolation between the input
and output terminals than a simple series switch does, especiallyat high frequencies. The result is excellent off-isolation in the Video and RF frequency ranges when compared
to conventional analog switches.
The control input level shifting circuitry is very similar to
that of the IH5140 series of Analog Switches, and gives
very high speed, guaranteed "Break-Before-Make" action,
low static power consumption and TIL compatibility.

SWITCH
0--0 DRAIN
(VIDEO OUTPUn

I
LOGIC~I

CONTROL
INPUT

-

DRIVER
TRANSLATOR
0296-3

NOTE: 1 CHANNEL OF 4 SHOWN

Figure 3: Internal Switch Configuration

•

VOUT1

TTL
INPUT

1000

+3V
OV
+3.3V

VOUT

1000
VANALOG

=+5V

OV
OV

VOUT

loon

VANALOG

=-5V

-3.3V

0296-5

'::"

loon

3V
rI
OV-l
LLOGIC CONTROL SIGNAL

0296-4

Figure 4: Switching Time Test Circuit and Waveforms

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been character/zed but are not tested.

8-119

:: IH5352
C")

II)

:!:
750
IH5352

RG·59 COAX

16

VOUT

RG·59 COAX

2

15

+15V

75Q

14
13
12

6

11

-=

-15V

8
+5V

-=
0296-6
OIRR = 20 LOG VVIN
OUT

VIN=5V pn SINEWAVE @ 10MHz

Figure 5: Off Isolation Test Circuit

IH5352

750

16

+SV

2

15

3

14

4

13

+15V VOUTI

750

5

-=-

750

6

750

7

8

0296-7

CCRR=20LOG~

VOUT

VIN=225mV RMS SINEWAVE@ 10MHz

Figure 6: Cross-Coupling Rejection Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

8-120

IH5352
750

J

+5V

RG-59 COAX

1
2

I(l

3

NC

4
S

....-NC

I~

6
7

NC

8

IH5352

-l>---i

'n.

J

)

VOUT

15
_+15V
14

-I>--i,

RG·59 COAX

16

750

750

13
12

,,

L0-

750

11
_-15V
10

~,

":"

750

9
..:-...... +5V
~

~

0296-8
f-3dB ~ FREQUENCY WHERE DC SWITCH
ATTENUATION IS DOWN 3dB
VIN~225mV

RMS

@

10-100MHz

Figure 7: Switch Attenuation - 3dB Frequency Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valuss have been charact9tized but are not tsst8d

8-121

i

MM450/451/452/455
MM550/551/552/555

=
!! High Voltage Analog Switch
...

I)
I)

GENERAL DESCRIPTION

FEATURES
• Large Analog Input -

~

The MM450, and MM550 series each contain p channel
MOS enhancement mode transistors. These devices are
useful in airborne and ground support systems requiring
multiplexing, analog transmission, and numerous signal
routing applications. The use of low threshold transistors
(VTH = 2 volts) permits operations with large analog input
swings (± 10 volts) at low gate voltages (- 20 volts).
Each gate input is protected from static charge build-up
by the incorporation of zener diode protective devices connected between the gate input and device bulk.

In

ORDERING INFORMATION

()
I)
I)

:I
:I
In
::
....

::

...

.
.

()
In

:I
:I

MM

4

L

± 10V

VBULK= + 10V
VGG=-20V
• Typical ON Resistance - VIN = -10V, 1500.
VIN= + 10V, 750.
• Low Leakage Current - 200pA Typical @ 2SOC
• Low Supply Voltage -

• Input Gate Protection

F

50

Package
F - 14 Pin Flatpak
J -14 Pin Sidebraze
H - 10 Pin Metal Can
Device Type

L -_ _ _ _ _

Temperature Range
4-(-55°Cto + 125°C)
5 - (COC to 7COC)

' - - - - - - - - - - Analog Switch
MM450, MM550 Dual
Differential Switch

MM452, MM552 QUAD
SPSTMOS

MM451, MM551 Four
Channel 4PST Mux

MM455, MM555
ThreeSPST
MOS TranSistor Package

..

.,'

•• '>-------'
..'...
l _ _ _ _ _..J

OUTLINE DWG
TO·l00

OUTLINE OWG

TO-l00
0302-1

OUTLINE DWG TO-tOO

OUTLINE DWGS
JE.FD·2

'0302-2

OUTLINE DWG

TO-l00

OUTLINE DWG TO-tOO
0302-3

OUTLINE DWGS DO, FD-2
Figure 1: Functional Diagram

0302-4

OUTLINE DWG TO-tOO

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITlON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PAATICULAR USE.
NOTE:AH typIcsJvsJusshallflboen _buIsronot/sstod.

8-122

.
........
.
.....

IID~OIL I:
I:

MM450/451/452/455
MM550/551/552/555

CII

~

ABSOLUTE MAXIMUM RATINGS (Note 1)
Gate Voltage (VGG) ................... + 14.5V to -30V
Bulk Voltage (VSUlK) ........................... + 14V
Analog Input (VIN) .••...•••..•.••.•••.•• + 14V to - 20V
Power Dissipation .••..•......................• 200mW

Operating Temperature
MM450, MM451 , MM452, MM455 ... -55·C to + 125·C
MM550, MM551, MM552, MM555 ....•.••• O·C to 70·C
Storage Temperature...............•. - 65·C to + 1500C
Lead Temperature (Soldering,10sec) ............. 3000C
NOTE 1: Dissipation rating assumes device Is mounted w~h all leads welded or soldered to printed circuit board In ambient temperature below nrc. For higher
temperature. derate at rate of 10mW/'C for FD pacI"'i--"1-o VOUT

SeON

-I

35pF

t.n

%

1-

-I topen 1-

0289-6
0289-5

Figure 4: t open (Break-Before-Make) Switching Test Circuit and Waveforms

+15V

3V

VEN

.,<100n&
It < 100ns .;O';.;;8V,-_ _50_0!...J°'1

r-..L--1-~:!..,,==--oVS.

Your
OV

L,....__.,...j-e>=-=t--i......:l VOUT
35pF

VEN

Vs," -sv
0289-8

":'

0289-7

Figure 5: ton and tott Switching Test Circuit and Waveforms

Ion and 10. OF LOGIC
INPUTs10ns

+3V

I

I

Ao,A1.A2

"OV'-_ _......- - 4•• - -..._ _....;S;.;;E;;;.QUENCED
1 1

BREAK.BEFORE
I 1
MAKEDELAV-VV

I:

INPUT
- I '--+10V

¥

:.

=-------T----~-----BREAK·BEFORE
MAKEDELAV-

~

-

10Ka

-

OV

W

INPUT
--10V

0289-10
":'

0289-9

Figure 6: Break-Before-Make Delay Test Circuit and Waveforms

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

9-4

IID~OI!..

IH5108

.
i

CII

o

DETAILED DESCRIPTION

-15V

The IH5108, like all Intersil's multiplexers, contains a set
of CMOS switches that form the channels, and driver and
decoder circuitry to control which channel turns ON, if any.
In addition, the IH5108 contains an internal regulator which
provides a fully TIL compatible ENable input that is identical in operation to the Address inputs. This does away with
the special conditions that many multiplexer enable inputs
require for proper logic swings. The identical circuit conditions of the ENable and Address lines also helps ensure the
extension of break-before-make switching to wider multiplexer systems (see applications section).
Another, and more important difference lies in the switching channel. Previous devices have used parallel n- and pchannel MOSFET switches. While this scheme yields reasonably good ON resistance characteristics and allows the
switching of rail-to-rail input signals, it also has a number of
drawbacks. The sources and drains of the switch transistors
will conduct to the substrate if the input goes outside the
supply rails, and even careful use of diodes cannot avoid
channel-to-output and channel-to-channel coupling in cases
of input overrange. The IH51 08 uses a novel series arrangement of the p- and n-channel switches (Figure 7) combined
with a dielectrically isolated process to eliminate these
problems.

+15V

CD

-15V

SIGNAL
INPUT

COMMON
OUTPUT

1I

-15V FROM +l5V FROM
DRIVER
DRIVER

0289-11

Figure 7: Series Connection of Channel Switches
Within the normal analog signal range, the inherent variation of switch ON resistance will balance out almost as well
as the customary parallel configuration, but as the analog
signal approaches either supply rail, even for an ON channel, either the p- or the n-channel will become a source
follower, disconnecting the channel (Figure 8). Thus protection is provided for any input or output channel against overvoltage, even in the absence of multiplexer supply voltages.
This applies up to the breakdown voltage of the respective
switches. Figure 9 shows a more detailed schematic of the
channel switches, including the back-gate driver devices
which ensure optimum channel ON resistances and breakdown voltage under the various conditions.

-25V
OVERVOLTAGE

O.
G

N·CHANNEL M O S F E T - r / 1D
ISTURNEDON
BECAUSE Vas. + 25V
':"

':"

P·CHANNEL
MOSFET IS OFF

0,
S

G

+25VFORCED
ON COMMON
OUTPUT

~~=~AL

To", CIRCUITRY
.1
N·CHANNEL
":'
MOSFET IS OFF
0289-12

(a) OVERVOLTAGE WITH MUX POWER OFF
-15V

+15V

-15V

+25VFORCED
ON COMMON
OUTPUT
LINE BY

-25V
OVERVOLTAGE

N·CHANNEL MOSFET
IS TURNED ON
BECAUSE Vas = + 10V

/1

t'~''1

EXTERNAL
CIRCUITRY
N.CHANNEL
MOSFET IS OFF
-15V FROM + 15V FROM P.CHANNEL
DRIVERS
DRIVERS MOSFET IS OFF
~

---+-----"''''

..

0289-13

(b) OVERVOLTAGE WITH MUX POWER ON

Figure 8: Overvoltage Protection

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but 8r6 not test6d.

9-5

...~

IH5108

II)

~ DETAILED DESCRIPTION

(Continued)

Under some circumstances, if the logic inputs are present
but the multiplexer supplies are not, the circuit will use the
logic inputs as a sort of phantom supply; this could result in
an output up to that logic level. To prevent this from occurring, simply ensure that the ENable pin is LOW any time the
multiplexer supply voltages are missing (Figure 10).

+15V

100pF

0289-15

Figure 10: Protection Against Logic Input

MAXIMUM SIGNAL HANDLING
CAPABILITY
The IH510B is designed to handle signals in the ± 10V
range, with a typical rDS(on) of 6000; it can successfully
handle signals up to ± 13V, however, rDS(on) will increase to
about 1.BkO. Beyond ± 13V the device approaches an
open circuit, and thus ± 12V is about the practical limit, see
Figure 11.
Figure 12 shows the input! output characteristics of an
ON channel, illustrating the inherent limiting action of the
series switch connection (see Detailed Description), while
Figure 13 gives the ON resistance variation with temperature.

FROM

DECODER

+15V

0289-14

Figure 9: Detailed Channel Switch Schematic

lDS{onl

t
2KO
) "OFP' BEYOND

THIS VOLTAGE

1.5110

1KD

Figure 11: rOS(on) vs Signal Output Voltage

@

TA =

+ 2SoC

0289-16

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPUED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have be9n chsract9fized but are not tested

9-6

IH5108

+YOUT
18
14
12
10

-Y~4--i--+--+--r--r-i--+--+--r--r-i--+-~~r--r-i--+--+--r-~-i~+--+--+-~-++Y~
-24-22-20-18- 8-14-12 -10 -8 -8 -4-2
4

-4
-8
-8
-10
-12
-14
-18
-YOUT

0289-17

Figure 12: MUX Output Voltage vs Input Voltage (Channel 1 Shown; All Channels Similar)

rDS(on)

3000
200fl

Vsupp. :15V
VIN- :10V

1000

25'C

75'C

TEMPERATURE
0289-18

Figure 13: Typical rOS(on) Variation With Temperature

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have be6n characterized but are not tested.

9-7

. IH5108
~

10

:E

USING THE IH5108 WITH SUPPLIES
OTHER THAN ± 15V
The IH5108 will operate successfully with supply voltages
from ± 5V to ± 15V, however rOS(on) increases as supply
voltage decreases, as shown in Figure 14. Leakage currents, on the other hand, decrease with a lowering of supply
voltage, and therefore the error term product of rOS(on) and
leakage current remains reasonably constant. rOS(on) also
decreases as signal levels decrease. For high system accuracy [acceptable levels of rOS(on») the maximum input signal
should be 3V less than the supply VOltages. The logic levels
remain TTL compatible.

2000Il
11000
11000

FOR:2VSIGNAlS

~

14000
12000

1000II
1000

APPLICATION NOTES

+ lOY SIGNAL

1000

Further information may be found in:
A003 "Understanding and Applying the Analog Switch"
A006 "A New CMOS Analog Gate Technology"
A020 "A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing"

-lOY SIGNAL

4000

2000
:OY

:SY

:10Y

:ISY
0289-19

Figure 14: Typical rOS(on) Variation
With Supply Voltages

IH5108 APPLICATIONS INFORMATION

-r

+r
EN

~

r---

r--

1"5108

r--

r--

Ao

A3

J,

J.

A,

....
~LOR

CMOS
INVERTER

-r

+r

Ao

DECODE TRUTH TABLE

-s~.

Al

Ao

0
0
0
0
0

0
0
0
0
1
1
1
1
0

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1

0

0
1
1
1
1
1
1
1
1

-

EN

A2

0
.....-oVoUT

l.

1"5101

A3

J.
0289-20

0
0
0
1
1
1
1

0
1
0
1

On Switch
51
52
53
54
55
56
57
58
59
510
511
512
513
514
515
516

Figure 15: 1 of 16 Channel Multiplexer Using Two IH5108s. Overvoltage Protection Is Maintained Between
All Channels, As Is Break-Before-Make Switching.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values hav8 been Charactsrized but are not tested.

9-8

RlO~DIL

IH5108
IH5108 APPLICATIONS INFORMATION

--t>o-

IH5108
10UTOF8
MUX

A,

-{"

EN

I

[

J

I

ANALOG INPUTS

!8

J"

I!

S,~

E!...
,
,-

IN,

IH5108
10UTOF8
MUX

EN

-

~

n
~

Aa

7,
~

.....

+r

T

Aa

Aa
Ao

...J

Loo-r>i,
S.

-

D.

.~

9 ANALOG INPUTS 16

U

~VOUT

IH5053

Aa

~

IH5108
10UTOF8
MUX

f-?-

~
EN

-J "

I

.I.17

-

r

J.

ANALOG INPUTS 24

n

IH5108
10UrOF8
MUX

s!.-,

,,

IN.

-'N,

4
--4
--4
EN

-D.

...J

ro-t>-;
54 .... -

J.25 ANALOG INPUTS 32J.

~

D,

r-

Jv
0289-21

DECODE TRUTH TABLE
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Al
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Ao
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

DECODE TRUTH TABLE
On Switch

A4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

81
82
83
84
85
86
87
88
89
810
811
812
813
814
815
816

A3

A2

Al

Ao

On Switch

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832

Figure 16: 1 Of 32 Multiplexer Using 41H5108s and An IH5053 As A Submultiplexer.
Note That The IH5053Is Protected Against Overvoltages By The IH5108s.
Submultiplexing Reduces Output Leakage and Capacitance.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valuss have been characterized but are not tested

9·9

UI

CD

(Continued)

TTUCMOS INVERTER

TTUCMOS NOR QATE

i

o

VL

Do-

.

:... IH5116

I

16-Channel Fault Protected
CMOS Analog Multiplexer

GENERAL DESCRIPTION

FEATURES

The IH5116 is a dielectrically isolated CMOS monolithic
analog multiplexer, designed as a plug-in replacement for
the HI506A and similar devices, but adding fault protection
to the standard performance. A unique serial MOSFET
switch ensures that an OFF channel will remain OFF when
the input exceeds the supply rails by up to ± 25V, even with
the supply voltage at zero. Further, an ON channel will be
limited to a throughput of about 1.5V less than the supply
rails, thus affording protection to any following circuitry such
as op amps, DfA converters, etc. Cross talk onto "good"
channels is also prevented.
A binary 2-bit address code together with the ENable input allows selection of any channel pair or none at all.
These 3 inputs are all TTL compatible for easy logic interface. The ENable input also facilitates MUX expansion and
cascading.

• All Channels OFF When Power OFF, tor Analog
Signals Up to ± 25V
• Power Supply Quiescent Current Less Than 1mA
• ± 13V Analog Signal Range
• No SCR Latchup
• Break·Before-Make Switching
• TTL and CMOS Compatible Strobe Control
• Pin Compatible With HI506A
• Any Channel Turns OFF If Input Exceeds Supply
Ralls By Up to ± 25V
• TTL and CMOS Compatible Binary Address and
ENable Inputs

DECODE TRUTH TABLE

ORDERING INFORMATION
Part
Number

Temperature
Range

IH5116MJI

- 55·C to + 125·C

28 pin CERDIP

IH5116CJI

O·Cto +70"C

28 pin CERDIP

IH5116CPI

O·Cto +70"C

Ceramic package
(IH5116MDIICDI)

available

as

Package

28 pin Plastic DIP
special

order

only

A3

Az

A1

Ao

EN

On Switch

X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

NONE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Logic "1"=VAH:<;:2.4V VENH:<;:2.4V
Logic "0"=VAL:S:0.8V

0290-1

Figure 1: Pin Configuration
(Outline dwg JI, PI)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
304500-003
NOTE: All typIcsJ valuss have been chsract6rIz6d but are not test8d.

9-10

IH5116
s.o-----.
s.o---"<
s.o--.
s.o---"<
1.0--.
$.0--.
$,0---"<

s•.,..---:

vau,
D

I.

$'0""---:

$.,""---:
S,,""---:
S,,""---:

::::=::J
S.. ~

TO DECODE LOGN:
COIffROLUIG BOTH
TIERS Of YUK'IIG

4 LIME BINARY ADDRESS .NPUTS
(0001) AIID Ell .. 5V
ABOVE EXAMPlE SNOWS CHAN.ElS 9 TURIED all.

0290-2

Figure 2: Functional Diagram

+ 15V

+3.0V

r .......-l-o~"'"~-o-

VA
2V

+

SWITCH OUTPUT
VOUT 0 f---K,J---"='-+l.J---==
O.9VO

Vo
Vs

~____~~~--~[¢VO~

35pF
0290-4

0290-3

Figure 3: t open (Break-Before-Make) Switching Test

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charactsrized but are not tested

9-11

:... IH5116
II)

:5

ABSOLUTE MAXIMUM RATINGS
Lead Temperature (Soldering, 10sec) ............. 300°C
Power Dissipation' ........................... 1200mW

VIN (A, EN) to Ground ....................... V- to V+
Vs or Vo to V Ground ................... + 25V to -40V
VsorVotoV- ........................ -25Vto +40V
V+ to Ground .................................... 20V
V- to Ground .................................. -20V
V-toV+ ..................................... +25V
Current (Any Terminal) .......................... 20mA
Operating Temperature ................ - 55 to + t 25°C
Storage Temperature .................. - 65 to + 150°C

ELECTRICAL CHARACTERISTICS
Characteristic

• All leads soldered or welded to PC board. Derate 1OmW I'C above 70'C.
NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended peri~
ods may affect device reliability.

(V+ = 15V, v- = -15V, VEN = 2.4V, unless otherwise specified.)
Max Limits

No
Measured Tests
Terminal Per
Temp

Test Conditions

Typ
M Suffix
C Suffix
Units
25°C -55°C
QOC
25°C 125°C
25°C 70°C

SWITCH
ROS(on)

Sto D

16

Vo=10V,
Is=-100/LA

Sequence each
900
switch on

1200

16

Vo=-10V
Is= -100/LA

VAL =0.8V,
VAH= 2.4V

1200

dROS(on)

IS(oft)

10(Oft)

10(on)

AR

S

D

D

- ROS{on}max-ROS{on}min
OS(on) ROS(on)avg.
Vs= ±10V

900

1200 1800 1500 1500 2000

n
1200 1800 1500 1500 2000

%

5

16

Vs=10V,
Vo= -10V

0.02

±0.5

50

±1.0

50

16

Vs= -10V,
Vo=10V

0.02

±0.5

50

±1.0

50

1

Vo=10V,
Vs= -10V

0.05

±1.0

100

±2.0 100

1

Vo= -10V,Vs= 10V

0.05

±1.0

100

±2.0 100

16

VS(AII)=VO= 10V

±2.0

100

±4.0 100

16

VS(AII)=VO= -10V

±2.0

100

±4.0 100

VEN=0.8V

nA
Sequence each
0.1
switch on
VAL =0.8V,
0.1
VAH= 2.4V

FAULT
IS with
Power OFF

S

16

Vsupp=OV, VIN= ±25V,
VEN=VO=OV, Ao, A1, A2=OVor5V

IS(oft) with
Overvoltage

S

16

VIN= ±25V, Vo= ±10V

Ao,A1'
A2,A3
orEN

4

VA =2.4Vor OV

4

VA=15V

1.0

2.0

5.0

1.0

2.0

5.0

0.01

-10

-30

0.01

10

30

/LA

INPUT
IEN(on) IA(on)
or

-10 -30
/LA

IEN(off) IA(ol!)

10

30

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MEACHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been charactenzed but are not tested

9·12

IID~OIL

IH5116
ELECTRICAL CHARACTERISTICS
(v+ = 15V, v- = -15V, VEN= 2.4V, unless otherwise specified.) (Continued)
No
Characteristic Measured Tests
Terminal Per
Temp

Max Limits
Test Conditions

Typ
MSufflx
CSufflx
Units
25'C -55'C 25'C 125'C O'C
25'C 70'C

DYNAMIC
D

0.3

Iopen

D

0.2

Ion(EN)

D

0.6

1.5

0.4

1

tlransilion

toff(EN)

D

ton-toff BreakBefore-Make
Delay Settling
Time

D

"OFF"
Isolation

D

16

VEN= +5V, Ao, Al, A2Strobed
VIN= ±10V.

VEN=O, RL =2000, CL =3pF,
Vs=3VRMS, f=500kHz

Cs(off)

S

Vs=O

CO(off)

D

Vo=O

COS(off)

DtoS

VEN=OV,
f=140kHz
to 1 MHz

Vs=O, Vo=O

1
,""S

25

ns

60

dB

5
25

pF

1

SUPPLY
Supply
Current

I

I

+

1+

1

-

1-

1

AIIVA=OV/5V
VEN=5V

0.5

0.6

1.0

0.02

0.6

1.0

mA

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIeS OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values hSV9 bsen characteriz9d but Bf6 not tesl6d.

9-13

i

......
o
CII

D~DI1.

81H5208

= 4-Channel

Differential
:E Fault Protected
CMOS Analog Multiplexer
GENERAL DESCRIPTION

FEATURES

The IH5208 is a dielectrically isolated CMOS monolithic
analog multiplexer, designed as a plug-in replacement for
the HI509A and similar devices, but adds fault protection to
the standard performance. A unique serial MOSFET switch
ensures that an OFF channel will remain OFF when the
input exceeds the supply rails by up to ± 25V, even with the
supply voltage at zero. Further, an ON channel will be limited to a throughput of about 1.5V less than the supply rails,
thus affording protection to any following circuitry such as
op amps, DJ A converters, etc.
A binary 2-bit address code together with the ENable input allows selection of any channel pair or none at all.
These 3 inputs are all TTL compatible for easy logiC interface; the ENable input also facilitates MUX expansion and
cascading.

• All Channels OFF When Power OFF, for Analog
Signals Up to ± 25V
• Power Supply Quiescent Current Less Than 1,...A
• ± 13V Analog Signal Range
• No SCR Latchup
• Break-Before-Make Switching
• TTL and CMOS Compatible Strobe Control
• Pin Compatible With HI- 509A
• Any Channel Turns OFF If Input Exceeds Supply
Rails by Up to ± 25V
• TTL and CMOS Compatible Binary Address and
ENable Inputs

ORDERING INFORMATION
Temperature
Range

Part Number
IH5208MJE

- 55·C to

IH52081JE

- 20·C to

IH5208CPE

Package

+ 125·C
+ 85·C

O·Cto 70·C

16 pin CERDIP
16 pin CERDIP
16 pin plastiC DIP

.. ~

DECODE TRUTH TABLE

s..~

A1

Ao

EN

On Switch
Pair

s..~

X
0
0
1
1

X
0
1
0
1

0
1
1
1
1

NONE
1a,1b
2a,2b
3a,3b
4a,4b

s..~

Ao, A" EN

s..~

Legic "O"~VAL:S:O.8V

Sao

0--':

s..~

D.

··lf~

logiC "1"~VAH;'2.4V

I

Ao[I~~A1

ADDRESS DECODE
10F4

EN

! ! !

~

~GND

v-I!

~ v+

[!

1!l s,.

S,.

s.. ~

2 LINE BINARY ADDRESS INPUTS
(0 OlANDEN-,
ABOVE EXAMPLE SHOWS CHANNELS ,. AND lb ON

S'"

Su

~s..

tm
~S"
mOo

~

s ..

~

DaE!

0293-1

Figure 1_ Functional Diagram

TOP VIEW

0293-2

Figure 2: Pin Configuration
(Outline dwg JE, PEl

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
304250-003

NOTE; All typical VSIU68 have bBsn characterized but Bf6 not testfJd.

9-14

IIID~OIL

IH5208

CD

Lead Temperature (Soldering, 10sec) ............. 300'C
Power Dissipation (Package)" ................. 1200mW
• All leads soldered or welded to PC board. Derate 1OmW /'C above 70·C.

VIN (A, EN) to Ground .................... -15V, + 15V
VsorVotoV+ ......•.... , ..•.........•. +25V, -40V
VsorVotoV- ....................•..... -25V, +40V
V+ to Ground .................................... 20V
V- to Ground .....•......•..................... -20V
Current (Any Terminal) ...•..••...•..•..•........ 20mA
Operating Temperature .................. -55 to 125'C
Storage Temperature ....•............... -65 to 150'C

ELECTRICAL CHARACTERISTICS

NOTE: Stresses above those listed under ''Absolute Maximum Ratings"
may cause permanent damsge to the devica. These are stress ratings only
and functional operation of the dsvica at these or any other conditions
above those indicated in thfJ operational sections 01 thfJ specifications is not
implisd. Exposure to absolute maximum rating conditions for extended perf.
ods may affect dsvica reliability.

v+ = 15V, v- = -15V, VEN = 2.4V, unless otherwise specified.
Max Limits

Test Conditions

CSutflx
Typ
Units
2S'C -SS'C 2S'C 12S'C -20'CI 2S'C 8S'CI
O'C
70'C
MSufflx

SWITCH
rOS(on)

StoD

8

Vo=10V,
Is=-100",A

Sequence each
900
switch on

1200 1200 1800

1500

1500 2000

8

Vo=-10V
Is= -100",A

VAL =0.8V,
VAH=2.4V

1200 1200 1800

1500

1500 2000

bor

borOS(on)

- rOS!onlmax-rOS!onlmin
OS(on)rOS~n)avg.

900

fi

%

5

VS= ±10
IS(oll)

S

8

VS=10V,
Vo= -10V

0.02

±0.5

50

±1.0

50

8

Vs=-10V,
Vo=10V

0.02

±0.5

50

±1.0

50

0.02

±1.0 100

±2.0 100

0.05

±1.0 100

±2.0 100

±2.0 100

±5.0 100

±2.0 100

±5.0 100

10(011)

D

1

Vo=10V,
Vs=-10V

1

Vo= -10V,Vs=10V

10(on)

D

8

VS(AII)=VO= 10V

8

nA
VEN=0.8V

Sequence each
0.1
switch on
VAL =0.8V,
VS(AII)=VO= -10V
0.1
VAH= 2.4V

FAULT
IS with
Power OFF

S

8

Vsupp=OV, VIN= ±25V,
VEN=VO=OV, Ao, Al, A2=OV

IS(oII) with
Overvoltage

S

8

VIN= ±25V, Vo= ±10V

4

VA=2.4VorOV

0.Q1

4

VA=15VorOV

0.Q1

1.0

2

5

1.0

5

10

",A

INPUT
IEN(on) IA(On) or AO, Al, AA2
orEN
IEN(oft) IA(oft)

UI
N

o

ABSOLUTE MAXIMUM RATINGS

No
Tests
Characteristic Measured
Terminal Per
Temp

i

-10 -30
10

30

-10 -30
10

",A

30

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,

NOTE: AU typical valuss have b6sn characWizsd but artI not testGd.

9·15

CIO

o

IH5208

(II
II)

i5

ELECTRICAL CHARACTERISTICS
V+ = 15V, v- = -15V, VEN = 2.4V, unless otherwise specified. (Continued)

Characteristic

Max Limits

No
Measured Tests
Terminal Per
Temp

Test Conditions

MSuffix

CSufflx
Typ
Units
25'C -55'C 25'C 125'C -20'CI 25'C 85'CI
O'C
70'C

DYNAMIC
ttransition

D

See Figure 3

0.3

topen

D

See Figure 4

0.2

ton(EN)

D

See Figure 5

0.6

1.5

Ioft(EN)

D

0.4

1

lon-toft BreakBefore-Make
Delay Settling
Time

D

"OFF"
Isolation

D

8

VEN= +5V, Ao, Al, A2 Strobed
VIN = ± 10V, Figure 6

VEN=O, RL =2000, CL =3pF,
Vs=3VRMS, f=500kHz

Cs(Off)

S

Vs=O

CO(oft)

D

Vo=O

COS(off)

DtoS

VEN=OV,
f= 140kHz
to 1 MHz

,",S

10

ns

60

dB

5
25

pF

1

Vs=O, Vo=O

SUPPLY
Supply
Current

1+

1+

1

I-

I-

1

All VA, VEN=5V
All VAOO= OV/5V

0.5

0.7

0.6

0.5

1.0

0.02

0.7

0.6

0.5

1.0

mA

Note 1. Readings taken 400ms after the Dvervoltage occurs.

SWITCHING INFORMATION
+15V

aov
lAV
O.8V

-15V

PROBE IMPEDANCE
Rp0TTLICM08

:Do-

_GATE

+11Y
All
A.

IH_

EN

I .:.

-1IV

.........

-

I s!.

s!.~

-

rL-

IH_

EN

r

s!.

..~ ~

..!.~

s...

-fi

+fi

'----

IH_
~~

A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Ao
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

j

-

.'.~

...

s.

I

,,

So

I....

So

I

-...

VOUTa

Da

1
0.

L1IV
+1

,,... Dt
j
I'", . Da

s.
II

tHI043 :
IN.

I
~

.,,

Da v_
.Lr
,
'- U
......
0.

So

I

So

i

L,IY
0293-21

On Switch

On Switch

S1a
S2a
S3a
S4a
S5a
S6a
S7a
S8a
S9a
S10a
S11a
S12a
S13a
S148
S158
S168

I

,

INo

DECODE TRUTH TABLE

A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

IN.

.!.-

EN

I .:-

Da

i

•

.........

-U
-,i'
1-

+yV

-lrV

+'rv

y

Dt Your.

INa

•

+11Y

I

Ie

u

-

~

II

J~ q,

IH_

EN

......

•

S.

.:.~

s!.~, •

+11Y

....

+IY
y

-11Y

S1b
S2b
S3b
S4b
S5b
S6b
S7b
S8b
S9b
S10b
S11b
S12b
S13b
S14b
S15b
S16b

VOUTb

Figure 16: Submultlplexed 2 of 32 System. The Two IH5043s Are Overvolt8ge Protected By The IH5208s.
Submultiplexlng Reduces Output Capacitance and Leakage Currents.
IN'TERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typ/c«1 Vllius8 haYS b6sn chsnlctBrizsd but ~re not testfKI.

9·22

IH5216
8-Channel Differential
Fault Protected
CMOS Analog Multiplexer
GENERAL DESCRIPTION

FEATURES

The IH5216 is a dielectrically isolated CMOS monolithic
analog multiplexer, designed as a plug-in replacement for
the HI507A and similar devices, but adding fault protection
to the standard performance. A unique serial MOSFET
switch ensures that an OFF channel will remain OFF when
the input exceeds the supply rails by up to ± 25V, even with
the supply voltage at zero. Further, an ON channel will be
limited to a throughput of about 1.5V less than the supply
rails, thus affording protection to any following circuitry such
as op amps, Df A converters, etc. Cross talk onto "good"
channels is also prevented.
A binary 2-bit address code together with the ENable input allows selection of any channel pair or none at all.
These 3 inputs are all TTL compatible for easy logic interface. The ENable input also facilitates MUX expansion and
cascading.

• All Channels OFF When Power OFF, for Analog
Signals Up to ± 25V
• Power Supply Quiescent Current Less Than lmA
• ± l3V Analog Signal Range
• No SCR Latchup
• Break-Before-Make Switching
• TTL and CMOS Compatible Strobe Control
• Pin Compatible With HI507A
• Any Channel Turns OFF If Input Exceeds Supply
Ralls By Up to ± 25V
• TTL and CMOS Compatible Binary Address and
ENable Inputs

ORDERING INFORMATION

DECODE TRUTH TABLE

Part
Number

Temperature
Range

IH52l6MJI

-55'C to + l25'C

28 pin CERDIP

IH52l6CJI

O'Cto +70'C

28 pin CERDIP

IH52l6CPI

O'Cto +70'C

28 pin Plastic DIP

Package

A2

A1

Ao

EN

On Switch
Pair

X
0
0
0
0
1
1
1
1

X
0
0
1
1
0
0
1
1

X
0
1
0
1
0
1
0
1

0
1
1
1
1
1
1
1
1

NONE
1
2
3
4
5
6
7
8

Ceramic package available as special order only (lH5216MDI/CDI)

Logic
Logic

"1"~VAH>2.4V

VENH>2.4V

"O"~VAL  v"

r--------~-,~!SI~--------~ v.,

SV

5V

0298-7

-"-------------------------------------- 0298-8

Figure 5: Switching Information
INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIeD WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bgen characterized but BI6 not tested.

9-35

.= IH6116
co

:E

IH6116 APPLICATIONS
+15V

-1SV

r

i

EN

-~

IH111.

r-r--

stl I I I I I I I I I II I 11,

Ao
A,

A2

--"VOUT

::+

-1SV

TTL OR
CMOS
INVERTER

i

+r

--

~

IHI111

EN

'TTL _ , m...t ...........to,
puUup to drl¥tl EN Input.

~IIIIIII

f

II II IlL
0298-9

DECODE TRUTH TABLE
A4

As

A2

A1

Ao

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

DECODE TRUTH TABLE
On Switch
51
52
83
84
85
86
57
88
89
810
811
812
513
514
515
516

A4

A3

A2

A1

Ao

On Switch

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

517
518
819
820
821
822
823
824
825
826
827
828
829
530
831
832

Figure 6: 1 Out of 32 Channel Multiplexer Using 2 IH6116s

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE OONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values hBve been characterized but are not testsd.

9-36

.O~OIl.

IH6116
IH6116 APPLICATIONS

GI

(Continued)

-r

+r
EN

r--

IH6118

r--

r-

st. I I I I II I II I II I IJ

Ao
A,

'*

+r
nLOR~~
CMOS

-

V,
+15V

VL
+5V

I

IH5041

IN,

I
J

IN2

,

D,
~VOUT

~

-15V

j

-

I
5' ....

A2
A:l

INVERTER

D2

52

G

IH8116

':"

EN

V2
-15V

VR

llill 11111 III IlL
A4
-TTL gate must have
pullup reeistor to + 5V to drive EN Inputs

0298-10

DECODE TRUTH TABLE
A4

A3

A2

A,

Ao

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

i

......GI

DECODE TRUTH TABLE

ON SWITCH
81
82
83
84
85
86
87
88
89
510
511
512
813
514
515
516

A4

A3

A2

A,

Ao

ON SWITCH

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

817
818
819
820
821
822
823
824
525
526
527
528
529
530
531
532

Figure 7: 1 Out of 32 Channel Multiplexer Using 2IH6116s; Using An IH5041 for Submultiplexing

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

9-37

.O~IIIL

:... IH6116
co

:E

IH6116 APPLICATIONS

(Continued)

A,
AI
AI

r

I

II

'1 I I I

IJJL~~~I

L:"

IHI"I

AI

I

, OUT 0'"

!lUX

.

IHI"I

"II I 1 I~~~~J.I I I I 1M

D,

I

""

t8=t~

.
I
I

10UT0P'1.
MUX

AI

~

.

~

.,

CIt

......

II

HI I I I 1~~~I~f.ITTTT"

~

I

t8=t~:-

"II I I I~J.OQ\~~' I I 1 ,-

~

EN InPlt"

III,

.'"

I

D.

I

, OUT 0' "
IlUX

AI

I

1 1 1 111

"-

IHI11.

INAllLE

·TT
up ""Itcn tG

II
,...!!!!

I~

I

...Lp""""""'ht*'"

-

IHI"I

1 OUT 01 1.

'"

Ln

r

1

..

..

..

.,v,

,f'"

'"

-,J~'
.v
0298-11

Figure 8: 1 Out of 64 Multiplexer Using 4 1I16s and IH5053 As Submultlplexer

General note on expandability of IH6116

6116 are tied together so that 8 channels are tied to the
VOUT common point. Since only one channel of information
is on at a time, the common output will consist of 7 OFF
channels and 1 ON channel. Thus the output leakage will
correspond to 7 10(offs) and 1 10(on), or about 1.0nA of typical leakage at room temperature. Throughput speed will be
typically 0.8,.,.s for Ion and 0.3,.,.s for Ioff. Throughput channel resistance will be in the 5000 area.
Figure 7 shows the 1 of 32 MUX of Figure 6, with a third
tier of submultiplexing added to further reduce leakage and
output capacitance. The IH5041 has typical ON resistances
of 500 (max. i.s 750) so it only increases thruput channel
resistance from the 500 ohms of Figure 6 to about 550
ohms for Figure 7. Throughput channel speed is a little
slower by about 0.5,.,.s for both ON and OFF time, and output leakage is about 0.2nA.

The IH6116 is a two tier multiplexer, where sixteen input
channels are routed to a common output in blocks of 4.
Each block of 4 input channels is routed to one common
output channel, and thus the submultiplexed system looks
like 4 blocks of 4 inputs routed to 4 different outputs with
the 4 outputs tied together. Thus 20 switches are needed to
handle the 16 chan.nels of information. The advantage of
this is lower output capacitance and leakage than would be
possible with a system using all 16 channels tied to one
common output. Also the expandability into 32, 64, 128,
channels etc. is facilitated. Figures 6, 7, and 8 show how the
IH6116 can be expanded.
Figure 6 shows a 1 of 32 multiplexer, using 2 IH6116s.
Since the 6116 is itself a 2 tier MUX, the system as shown is
basically a 2 tier system. The four output channels of each

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE

:~~~~~:;;:;-TYSH~~ ~~N~L~~~ ~~~~~ ~~~ LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES oF
NOTE:AH typ/cBI_havsbHn

_but.,.,

not_

9-38

BlD~OIl.

IH6116
Figure 8 shows a 1 of 64 MUX using 3 tier MUXing (similar to Figure 7). The Intersil IH5053 is used to get the third
tier of MUXing. The VOUT point will see 3 OFF channels and
1 ON channel at anyone time, so that the typical leakages
will be about 0.4 nA. Throughput channel resistance will be
in the 550 ohm area with throughput switching speeds
about 1.3",s for ON time and 0.8",s for OFF time.

for the low state. When using TTL logic, a pull-up resistor of
1kO or less should be used to pull the output voltage up to
5V. When using CMOS logic, the high state goes to the
power supply so no pull-up is required.
If used on high voltage logic supplies, EN should be at
least 0.7V below V+ at all times. See IH6108 data sheet for
details.

The IH5053 was chosen as the third tier of the MUX because it will switch the same AC Signals as the IH6116 (typically plus and minus 15V) and uses break before make
switching. Also power supply quiescent currents are on the
order of 1-2",A, so that no excessive system power is dissipated. Note that the logic of the 5053 is such that it can be
tied directly to the ENable input (as shown in the figures)
with no extra circuitry being required.

APPLICATION NOTES
Further information may be found in:
A003 "Understanding and Applying the Analog Switch"
A006 "A New CMOS Analog Gate Technology"
A020 "A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing"
R009 "Reduce CMOS Multiplexer Troubles Through Proper Device Selection"
NOTE: This multiplexer does not require external resistors
and/or diodes to eliminate what is commonly known as a
latch up or SCR action. Because of this fact, the rDS(ON) of
the switch is maintained at specified values.

Enable input strobing levels
The enable input (EN) acts as an enabling or disabling pin
for the IH6116 when used as a 16 channel MUX. However,
when expanding the MUX to more than 16 channels, the EN
pin acts as another address input. Figures 6 and 7 show the
EN pin used as theA4 input.
For the system to function properly the EN input (pin 18)
must go to 5V ± 5% for the high state and less than 0.8V

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values hsve b98n charscf9rlzsd but are not tested.

9-39

i

......
ell

ell

. IH6201

U~UlL

o

C\I

!

Dual CMOS
DriverIVoltage Translator
GENERAL DESCRIPTION

FEATURES

The IH6201 is a CMOS, Monolithic, Dual Voltage Translator; it takes low level TTL or CMOS logic signals and converts them to higher levels (i.e. to ± 15V swings). This translator is typically used in making solid state switches, or analog gates.
When used in conjunction with the Intersil IH401 family of
Varafets, the combination makes a complete solid state
switch capable of switching signals up to 22Vpp and up to
20MHz in frequency. This switch is a "break-before-make"
type (Le. toff time< Ion time). The combination has typical
toff "" 80ns and typo ton "" 200ns for signals up to 20Vpp in
amplitude.
A TTL" 1" input strobe will force the (} driver output up to
V+ level; the Ii output will be driven down to the V- level.
When the TIL input goes to "0", the (} output goes to Vand Ii goes to V +; thus (} and Ii are 180' out of phase with
each other. These complementary outputs can be used to
create a wide variety of functions such as SPDT and DPDT
switches, etc.; alternatively the complementary outputs can
be used to drive Nand P channel MOSFETs, to make a
complete CMOS analog gate.
The driver typically uses + 5V and ± 15V power supplies,
however a wide range of V+ and V- is also possible. It is
necessary that V + > 5V for the driver to work properly, however.

• Driven Direct From TTL or CMOS Logic
• Translates Logic Levels Up to 30V Levels
• Switches 20VACPP Signals When Used in
Conjunction With IntersillH401A Varafet (As An
Analog Gate)
• tON S 300ns & tOFF S 200ns for 30V Level Shifts
• Quiescent Supply Currents100,..A for Any State
(D.C.)
• Provides Both Normal & Inverted Outputs

ORDERING INFORMATION
Part Number

Temperature Range

*IH6201CDE

O'Cto 70'C

*IH6201MDE

- 55'C to

+ 125'C

IH6201CJE

0'Ct070'C

IH6201MJE

- 55'C to 125'C

IH6201CPE

O'Cto 70'C

*Special Order Only

V+

DRIVER

DRIYER

OUTPUT

OUTPUT

fl,

4k

II,

0299-1

Figure 1: Functional Diagram

,.

DRIYER
OUTPUT
8

LOGIC

STROBE

';"J'""

81

•

5 TTL INPUT 1

81
82

3

4 y-

IH6201
1
1

OND

DRIYER

+5V
y+

OUTPUT

Ii

TTL INPUT 2

82 8

~

_ _.r--

0299-2

(Outline dwgs DE,JE,PE)
Figure 2: Pin Configuration
0299-3

Figure 3: Schematic Diagram (One Channel)

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

9-40

IH8201
ABSOLUTE MAXIMUM RATINGS
v+ toV- .......•.•.•..••..•.•••.•••.•...••.•••• 35V
v+ ••••.•.•...•.••.••.•.••.•.•.••••..•..•....... 35V
v- .••••..•...•...........•.......••.••.•.•.•.•• 35V
v+ to VIN ........•..•..•.••.......••••.•.••.•••• 40V
Operating Temperature •.••.•.•.•••.• - 55°C to + 125°C
Storage Temperature •.•.•..•.••••... -65°C to + 150"C
Lead Temperature (Soldering,10sec) •...•..•••.•. 300"C

ELECTRICAL SPECIFICATIONS
Item

NOTE: Strsssss above those listed under "AbsoIullJ MBXlmum Rallngs"
may CBU89 psrtTIBnsnt damsge to the davies. These are stress rellngs only
IUId functionBl optHtJlion of IhB davies at thes8 or any 01h8r conditions
above thos8lnd1cBted in the optHtJlionBl S8CIIons of IhB specIfIcalions Is not
/mpI18d. Exposure to tIbBoIuts mBXimum filling conditions for _ndBd ptHI.
ods may sffscl davies rs/1Bblllty.

v+ = + 15V, v- = -15V, VL = + 5V
IH6201CDE

Test Conditions
-25°C

8 or 8 driver output swing

VIN = OV ..rL + 3V Fig. 58

VIN strobe level ("1 ")for
proper translation

8~14V

6~-14V

VIN strobe level ("O")for
proper translation

6~14V

8~

-14V

+ 25°C

IH6201MDE
+ 85°C

-55°C

+25"C

28

Units

+ 125"C

28

Vpp

3.0

3.0

3.0

2.4

Vo.c.

0.4

0.4

0.4

0.8

Vo.c.

±1

±1

10

liN input strobe current draw
(for OV - 5V range)

VIN=OVor +5V

ton time

VIN = OV ..rL CL = 30pF
switching turn-on time fig. 58

400

300

ns

toff time

VIN=OV..rL CL =30pF
switching turn-off time fig. 58

300

200

ns

I + (V +) power supply
quiescent current

VIN=OVor +5V

1- (V-) power supply
quiescent current

VIN=OVor +5V

IL (VtJ power supply
quiescent current

VIN=OVor +5V

±1

±1

10

p.A

100

100

100

100

100

100

p.A

100

100

100

100

100

100

p.A

100

100

100

100

100

100

p.A

APPLICATIONS
Input Drive Capability

You will notice in Figure 4 that a "referral" resistor has
been added from 2N4391 gate to its source. This resistor is
needed to compensate for the inadequate charge area
curve for isoiation diode i.e. if C vs. V plot for diodeS:2 [C
vs. V plot for output JFET] switch won't function; then adding this resistor overcomes this condition. The "referral" resistor is normally in the 100kO to 1MO range and is not too
critical.

The strobe Input lines are designed to be driven from TTL
logic levels; this means 0.8V to 2.4V levels max. and min.
respectively. For those users who require 0.8V to 2.0V operation, a pull-up resistor is recommended from the TTL output to + 5V line. This resistor is not critical and can be in the
1kO to 10kO range.
When using 4000 series CMOS logic, the input strobe is
connected direct to the 4000 series gate output and no pull
up resistors, or any other interface, is necessary.
When the input strobe voltage level goes below Gnd (i.e.
to -15V) the circuit is unaffected as long as V+ to VIN
does not exceed absolute maximum rating.

SIGNAL INPUT

-IV

~
TTLINPUT - - - - f
SWITCH
OUTPUT

Output Drive Capability
HL

The translator output is designed to drive the Intersil
IH401 family of Varafets; these are N-channel JFETS with
built-in driver diodes. Driver diodes are necessary to isolate
the signal source from the driver/translator output; this prevents a forward bias condition between the signal input and
the + Vee supply. The IH6201 will drive any JFET provided
some sort of isolation is added.

0299-4

Figure 4

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCWDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE; AU typ/cBI vaIusB haVfl bstm chIlractBrIzed but IUS not tsst6d.

9-41

•

o IH6201
&\I

CIt

!

Making a Complete Solid State Switch
That Can Handle 20Vpp Signals

IV

~
..,

The limitation on signal handling capability comes from
the output gating device. When a JFET is used, the pinchoff of the JFET acting With the V - supply does the limiting.
In fact max. signal handling capability=2 (Vp + (V-» Vpp
where Vp=pinch-off voltage of JFET chosen. i.e. Vp=7V,
V- = -1SV :. max. Signal handling = 2 (7V + (-1SV»
Vpp = 2(7V -1S)Vpp = 2( -8Vpp) = 16Vpp. Obviously to
get~20Vpp, Vp~SV with V- = -1SV. Another simple way
to get 20Vpp with Vp=7V, is to increase V- to -17V. In
fact using V+=+12V or +1SV and setting V-=-18V
allows one to switch 20Vpp with any member of IH401 family. The advantage of using the Vp=7V pinch-off (along with
unsymmetrical supplies), over the Vp=SV pinch-off (and
± 1SV supplies), is that you will have a much lower ROS(ON)
for the Vp = 7 JFET (i.e. for the 2N4391).

tJ

+1"
v-rL..
I
I

.......

I
I

ii

I
I

+15ViI
-15V

rOS(ON) ::::; 220,
rOS(ON) ::::; 3S0)
Vp=7V
Vp=SV
The IH6201 is a dual translator, each containing 4 CMOS
FET pairs. The schematic of one-half of an IH6201, driving
one-quarter of an IH401, is shown in Figure SA.

,..
~

:!!.....-

,..

-i
V
1\_\

-""'-

+••

\

....
.... r-

~

1

.. - !

-

10"

I-

0299-6

Figure5B

-

NOTE: Each translator output has a 8 and 8 output. 8 is just
the inverse of 6.
A very useful feature of this system is that one-half of an
IH6201 and one-half of an IH401 can combine to make a
SPOT switch, or an IH6201 plus an IH401 can make a dual
SPOT analog switch. (See Figure 8)

'----l
I

I

I

..rL STROBE
~~g:1

I
I

I

INPUT

I

I

8

I

L...!A!!.~_J

UNO

-.,

VL

+5Y

+15V

-1SY

0299-7

TRANSlATOR

Figure. 6: Dual SPST Analog Switch
0299-5

Figure5A

INTERSIL'S SOLE AND EXCLUSIVE WARRANn' OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL. BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPUED OR STATUTORY, INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AD typiQI WIIuss have been chBractsrIzed but tmI not tssttJd.

9-42

IH6201
APPLICATIONS

(Continued)

0299-10

0299-8

Figure 9: Dual DPST

Figure 7: DPDT Analog Switch
NOTE: Either switch is turned on when strobe input goes high.

0299-9

•

Figure 8: Dual SPDT

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical VIIIues haV9 bHn ~ but SI'9 not tsstsd.

9·43

81H6208

= 4-Channel

iE

Differential
CMOS Analog Multiplexer

GENERAL DESCRIPTION

FEATURES

The IH620S Is a 2 of S CMOS multiplexer. The part is a
plug-in replacement for the DG509. Two line binary decodIng is used so that the S channels can be controlled In pairs
by the binary Inputs; additionally a third input is provided to
use as a system enable. When the ENable Input Is high (5V)
the channels are sequenced by the 2 line binary inputs, and
when low (OV) all channels are off. The 2 Address inputs
are controlled by TTL logiC or CMOS logic elements with a
"0" corresponding to any voltage less than O.SV and a "1"
corresponding to any voltage greater than 2.4V. Note that
the ENable input must be taken to 5V to enable the system,
and less than O.SV to disable the system.

• Ultra Low Leakage -1D(off)S; 100pA typical
• rDS(on)<400 Ohm. OYer Full Signal and Temperature
Rang.
• Power Supply QulelCent Current Le•• Than 100I£A
• ±14Y Analog Signal Range
• No SCR Letchup
• Break-Before-Make Switching
• Binary Addre.s Control (2 Address Inputs Control 2
Out of 8 Channels)
• TTL and CMOS Compatible Address Control
• Pin Compatible With HI509, DG509A & AD7509
• Internal Diode In Series With Y+ For Fault
Protection

ORDERING INFORMATION
Part Number
IH620SMJE

Temperature Range
- 55·C to

Package

+ 125·C

16 pin CERDIP

IH620SCJE

OOCt070·C

16 pin CERDIP

IH620SCPE

O·C to 70·C

16 pin Plastic DIP

Ceramic package available as spacial order only (IH6208MDE/CDE)

DECODE TRUTH TABLE

.1.

8211~

A1

Ao

EN

On
Switch
Pair

131~

X

X

841~

0
0
1
1

0
1
0
1

0
1
1
1
1

NONE
1a,1b
2a,2b
3a,3b
4a,4b

IN SWITCH
I
I
I

0,

I
I
I

0,

I
SIb

I
I

Ag,A,
LOGIC "1"=VAHl<2.4V VENHl<4.5V
LOGIC "O"aVALS;O.8V

S2b~

~ab~
S4b~

All
EN

OND

V-

y+

SI.

A,

BIb

S28

B2b

sa.

Bab

S40

S4b
02
0300-2

Figure 2: Pin Configuration
2 LINE BINARY ADDRESS INPUTS
(0 OIANDEN-SV(EN.","FDR +SV.·'O"FORO~I
ABOVE EXAMPLE SHOWS CHANNELS" • 'b ON.

0300-,

Figure 1: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typIcsJ
ha .. bHn _ _ but.,. not IHIBd.
9-44

l1li_

IH6208
ABSOLUTE MAXIMUM RATINGS
Current (Analog Source or Drain) .••••••..•.•.••.• 20mA
Operating Temperature .................. - 55 to 125·C
Storage Temperature ..••.•.•...••.••..•. -65 to 150·C
Lead Temp (Soldering, 10sec) ..•.........•.•.••. 300·C
Power Dissipation (Package)' ..........•....•• 1200mW

VIN (A, EN) to Ground ....................... -15V, Vl
VsorVotoV+ .............................. 0, -36V
VsorVotoV- ..•••...•.•.•....•.•.•.••.•..••• 0,36V
V+ to Ground .•..•.•.•.••.....•.••••.•.•.•...••.• 16V
V- to Ground .................................. -16V
Current(Any Terminal) .......................... 30mA

• All leads soldered or welded to PC board. Oerate 1OmWI·C above 70·C.

NOTE: Stresses above those listed under ''Absolute Maximum Rafjngs" may cause permanent damage to the device. These are stress rafjngs only and functionel

operation of the device at theS9 or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rafjng condmons for extended periods may affect davice reliability.

ELECTRICAL CHARACTERISTICS
v+ = 15V, v- = -15V, VEN= +5V (Note 1), Ground=OV, unless otherwise specified.
Max Limits

No
Characteristic Measured Tests Typ
Terminal Per 2S·C
Temp

MSufflx

Test Conditions

C Suffix

Units

-SS·C 2S·C 12S·C O'C 2S·C 70·C

SWITCH
StoD

rOS(ON)

8
8

180 Vo = -1 OV, Is = -1.0mA Sequence each switch on
150 Vo= -10V, Is= -1.0mA VAL =0.8V, VAH=2.4V

S

ISCOFFl

300

400 350 350 450

300

300

400 350 350 450

- rOS(on)max-rOS(on)min v - ±10V
Il.r
OS(on) 'OS(on)avg.
S-

20

Il.rOS(ON)

300

%

8

0.002 VS=10V, VO= -10V

±.5

50

±1

8

0.002 VS= -10V, VO=10V

±.5

50

±1

50

2

0.03 VO= 10V, VS= -10V

±2

50

±5

100

±2

50

±5

100

VEN=0.8V

0.

50

IOCOFFl

D

2

0.03 VO= -10V, VS=10V

8

0.1

VS(ALL)=Vo=10V

Sequence each switch on

±2

50

±5 100

10(ON)

D

8

0.1

VS(ALL)= -10V

VAL =0.8V, VAH=2.4V

±2

50

±5 100

IA(on)

2

0.01 VA=2.4Vor OV

IACoff)

2

0.01 VA=14VOrOV

Ao,Al

2

VEN=5V

EN

1

VEN=O

nA

INPUT

IA

-10 -30
10
AIIVA=O
(Address Pins)

30

-10 -30
10

30

-10 -30

-10 -30

-10 -30

-10 -30

,...A

DYNAMIC
D

0.3 See Fig. 3

D

0.2 See Fig. 4

EN(on)

D

0.6 See Fig. 5

tEN(off)

D

0.4

"OFF" Isolation

D

60

VEN=O, RL =2000., CL =3pF, Vs=3VRMS,
j=500kHz
Vs=O

transition
~Den

1.5

,...s

1

CsCoff)

S

5

Cd(off)

D

12 Vo=O

CdsCoff)

DtoS

1

1

dB

pF

VEN=OV, j= 140kHz to
1MHz

Vs=O, Vo=O

SUPPLY

+
-

V+

1

40

Current

V-

1

2

Standby

+

V+

1

1

Current

-

V-

1

1

Supply

NOTE 1:

VEN=5V
AIIVA=00r5V
VEN=O

200

1000

100

1000

100

1000

100

1000

,...A

See Section 1 Enable Input Strobing Levels.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been chsr8cteriZed bUt are not tested.

9-45

•

8 IH6208
('I

co

!

SWITCHING INFORMATION
a.ov
IAV
O.IV

f----'i

51.
52,
53.
54.
51b
52b
53b

A,
Al;

VA

'='

54b

IH6208
02 Your

PROBE

.:!: Rp

~*:, Cp

... - ....... -...1

,~,

ttrans

PROBE IMPEDANCE
Rp 2': 1M!!

Cp $ 30pF 0300-4

0300-3

Figure 3: ttrans Switching Test

+15V

A,

r- -.......1-~~--O-2V

Al;

IV
VA

l

_I"'"_ _

.,.J~~1=~I::VOUT
aspF
0300-6

0300-5

Figure 4: t open (Break-Before-Make) Switching Test

+5V

VEN
" . If

$

lOOn.

o.l:~

+O.IV

Z ,: I______

~

+15V

~______~.

I:

-i\.....______
tEN(orr)

r--....I-'""(--t------t--t'l""----

SWITCH OUTPUT
Your

(SEE FlO. 3)

O.9Vo
Vo

-iV
0300-7

Figure 5: ton and toff Switching Test

INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE 'EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values havs be6n charactsJized but are not tsst6d.

9·46

IH6208
IH6208 APPLICATION INFORMATION
ENable Input Strobing Levels
The ENable input on the IH620S requires a minimum of

+ 4.SV to trigger it into the "1" state and a maximum of
+ O.SV to trigger it into the "0" state. If the ENable input is
being driven from TTL logic, a pull-up resistor of 1k to 3kO
is required from the gate output to + 5V supply. (See Figure
6).

14 +5V

1K

OM7404N

TTL LOGIC
+3Y

~

Figure 6: ENable Input Strobing From TTL Logic

0300-9

When the EN input is driven from CMOS logic, no pullup is necessary. (See Fig. 7)
+5V

Figure 7: CMOS Logic Driving ENable Pin

0300-10

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

9-47

~

IH6208

(\II

10

:E IH6208 APPLICATION INFORMATION

(Continued)
The supply voltage of the CD4009 affects the switching
supply voltages decrease, however, the multiplexer error
speed of the IH620B; the same is true for TTL supply voltterm (the product of leakage times rD8(on)) will remain approximately constant since leakage decreases as the supage levels. The chart below shows the effect on ttrans for a
ply voltages are reduced.
supply varying from + 4.5V to + 5.5V.
Caution must be taken to ensure that the enable (EN)
CMOS OR
TYPICAL ttrans
voltage is at least 0.7V below V+ at all times. If this is not
TTL SUPPLY
@ 2S0C
done the Address Input strobing levels will not function
+4.5V
400ns
properly. This may be achieved quite simply by connecting
+4.75V
300ns
EN (pin 2) to V+ (pin 14) via a silicon diode as shown in
250ns
+5.OV
Figure B. A further requirement must be met when using this
type of configuration; the strobe levels at AO and A 1 must
+5.25V
200ns
be within 2.5V of the EN voltage in order to define a binary
175ns
+5.50V
"1" state. For the case shown in Figure B the EN voltage is
11.3V, which means that logic high at AO and A1 is = + B.BV
The throughput rate can therefore be maximized by using
(logic low continues to be = O.BV). In this configuration the
a + 5V to + 5.5V supply for the ENable Strobe Logic.
IH6208 cannot be driven by TTL (+5V) or CMOS (+5V)
logic. It can be driven by TTL open collector logic or CMOS
The examples shown in Figures 6 and 7 deal with ENable
strobing when expansion to more than four differential
logic with + 12V supplies.
channels is required; in these cases the EN terminal acts as
If the logic and the IH620B have common supplies, the
a third address input. If four channel pairs or less are being
EN pin should again be connected to the supply through a
multiplexed, the EN terminal can be directly connected to
silicon diode. In this case, tying EN to the logic supply di+5V to enable the IH620B at all times.
rectly will not work since it violates the 0.7V differential voltage required between V+ and EN (See Figure 9). A 1JAoF
Using the IH6208 with supplies other
capacitor can be placed across the diode to minimize
than 15V
switching glitches.
The IH620B can be used with power supplies ranging
from ± 6V to ± 16V. The switch rD8(on) will increase as the

±

1N914

+12V

,---~~(
A CHANNELS
COMMON DRAIN OUTPUT = D, 1

).~,,~~,~
...._ _ _ _ _...,jI

9 D2 = B CHANNEL DRAIN OUTPUT
(COMMON)
0300-11

Figure 8: IH6208 Connection Diagram for Less Than ± 1SV Supply Operation

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been characterized but are not tested.

9-4B

IH6208
IH6208 APPLICATION INFORMATION

(Continued)

lN914

0300-12

Figure 9: IH6208 Connection Diagram With ENable Input Strobing
for Less Than ± 15V Supply Operation

Peak-to-Peak Signal Handling Capability
The IH6208 can handle input signals up to ± 14V (actually -15V to + 14.3V because of the input protection diode)
when using ± 15V supplies.
The electrical specifications of the IH6208 are guaranteed for ± 1OV signals, but the specifications have very minor changes for ±14V signals. The notable changes are
slightly lower rDS(on) and slightly higher leakages.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicalvslU8S have bs6n charsctsrizsd but 81'8 not tested.

9-49

~
co

~

IH6216

8-Channel Differential
CMOS Analog Multiplexer
GENERAL DESCRIPTION

FEATURES

The IH6216 is a CMOS 2 of 16 multiplexer. The part is a
plug-in replacement for the DGS07. Three line binary decoding is used so that the 16 channels can be controlled in
pairs by the binary inputs; additionally a fourth input is provided to use as a system enable. When the ENable input is
high (SV) the channels are sequenced by the 3 line binary
inputs, and when low (OV), all channels are off. The 3 Address inputs are controlled by TTL logic or CMOS logic elements with a "0" corresponding to any voltage less than
O.BV and a "1" corresponding to any voltage greater than
3.0V. Note that the ENable input must be taken to SV to
enable the system and less than O.BV to disable the system.

• Pin Compatible With HIS07, DGS07A & AD7S07
• ± 11 V Analog Signal Range
• rOS(on) <700 Ohms Over Full Signal and Temperature
Range
• Break-Before-Make Switching
• TTL and CMOS Compatible Address Control
• Binary Address Control (3 Address Inputs Control 2
Out of 16 Channels)
• Two Tier Submultiplexing to Facilitate Expandabllity
• Power Supply Quiescent Current Less Than 100JLA
• No SCR Latchup
• Very Low Leakage IO(OFF):5: 100pA
• Internal Diode In Series With V+ for Fault Protection

ORDERING INFORMATION
Part Number

Temperature Range
-SS·C to

IH6216MJI

+ 12S·C

Package
2B pin CERDIP

IH6216CJI

0·Ct070·C

28 pin CERDIP

IH6216CPI

O·Cto 70·C

28 pin Plastic DIP

Ceramic package available as special order only (IH6216MDI/CDI)

DECODE TRUTH TABLE

•••

:~~'"
.........
~
~

A2

A1

Ao

EN

On
Switch
Pair

X

X

X

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
1
1
1
1
1
1

NONE
1
2
3
4
S
6
7
8

LOGIC
LOGIC

~

"1"~VAH>3V
"O"~VAL

VENH>4.5V

VOUT

G.9VO

35pF

Vo

Vs

0301-7

0301-8

Figure 5: Switching Information

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not t8Sted.

9·52

IH6216
IH6216 APPLICATIONS
+15V

-ISV

1

1

Ao

,..",

I--

IH6216
IN

~ ~lb

~1.

+1i

TTL'JCIIos .II>
INVERTER

-

'l

~
-ISV

1

'--

t---o VOUT1

r--

VOUT2

-

1H6216

----eN

1-------1 1-------1
SIlo

Ito

Sib

'11b

1
0301-9

'TIL gate must have pullup

to drive EN input

Figure 6: 2 Out of 32 Channel Multiplexer Using 2 IH6216s
DECODE TRUTH TABLE

DECODE TRUTH TABLE
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

On Switch

Ao

AI
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

51a
52a
53a
54a
55a
56a
57a
5Sa
59a
510a
511a
512a
513a
514a
515a
516a

A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

VOUT1

A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

l

Ao

,..
A,

IH6211

TTL'/CMOI
INVEIITIIII. I>

~1.

~ ~lb

-ali!

r-

'--

I~

VOUT2

•

+15V

y

~

VOUT1

~J
IH5043

,
I

I

INI

1N2

~

51b
52b
53b
54b
55b
S6b
57b
S6b
59b
510b
511b
512b
513b
514b
515b
516b

.J

-IfV

+lj

'---

As

'l-

On Switch

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

f---

IN

I

Ao

r

-ISV

+jSV

AI
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

1H6211

II;!

~

II;!

f-O-t>-l'......
,

1-

I

~

-+-

YOUT2

IT

-1~
0301-10

'TIL Inverter must have resistor pullup

to drive EN input

Figure 7: 2 One of 32 Multiplexer Using Two IH6216s, and An IH5043 for Submultlplexing
INTERSIL'S SOI.£ AND EXCWSNE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN typics/ vsJues have been chsractstized but 111'6 not fest9d.

9-53

:(\I IH6216
U)

~ General note on expandability of IH6216

Figure 6 shows a 2 of 32 multiplexer, using 2 IH6216s.
Since the 6216 is itself a 2 tier MUX, the system as shown is
basically a 2 tier system. Corresponding output pOints of
each of the 6216 are connected together, and the ENable
input strobe is used as the As input. Since each output (pins
2 and 28) corresponds to an "ON" FET and an "OFF" FET,
the overall system looks like 1 "ON" FET and 3 "OFF"
FETs for each of the Vou!1 and Vout2 outputs. Thus the
output leakage will be 1 ID(On) plus 3 ID(off)S or about O.4nA
at room temperature. Throughput speed will be typically
0.81-'5 for ton and 0.31-'5 for toff, with throughput channel
resistance in the 500n area.

The IH6216 is a two tier multiplexer, where 8 pairs of
input channels are routed to a pair of outputs in blocks of 4.
Each block of 4 input channels is routed to one common
output channel, and thus the submultiplexed system looks
like 4 blocks of 4 inputs routed to 4 different outputs with
the 4 outputs tied in pairs. Thus 20 switches are needed to
handle the 16 channels of information. The advantages of
this are lower output capacitance and leakage than would
be possible using a system with all 8 channels tied to one
common output. Also the expandability into 2 out of 32, 64,
128, etc. is facilitated. Figures 6, 7, and 8 show how the
IH6216 is expanded.

DECODE TRUTH TABLE

DECODE TRUTH TABLE

AO

o
o
o
o
o
o
o
o
1
1
1
1
1
1
1
1

o
o
o
o

o
o

o
1

1
1

o

1
1
1
1

o
o

o

1
1

o

o
o
o
o

o
o

o

1
1
1
1

1
1
1
1

1
1

o

o

o

1
1

o

o

1
1
1

On Switch
Sla
S2a
S3a
S4a
S5a
S6a
S7a
S8a
S9a
S10a
Slla
S12a
S13a
S14a
S15a
S16a

VOUT1

A3

A2

AI

Ao

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

I
1
0
0
1
1
0
0
1
1

On Switch
SIb
S2b
S3b
S4b
S5b
S6b
S7b
S8b
S9b
SlOb
Sllb
S12b
S13b
S14b
S15b
S16b

VOUT2

0301-11

Figure 8: 2 One of 64 Multiplexer Using 4 IH6216s and 2 IH5043s as Sub multiplexers

fNrEASfL'S SOLE ANO EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPAESS, IMPLIED OA STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have b96n characterized but are not tested.

9-54

II]U~OIL

IH6216
Figure 7 shows the 2 of 32 MUX of Figure 6, with a third
tier of submultiplexing added to further reduce leakage and
output capacitance. The IH5043 has typical ON resistance
of 500 (max. is 750) so it only increases throughput channel resistance from the 500 ohms of Figure 6 to about 550
ohms for Figure 7. Throughput channel speed is a little
slower by about 0.5,..s for both ON and OFF time, and output leakage is about 0.2nA.
Figure 8 shows a 2 of 64 MUX using 3 tier MUXing (similar to Figure 7). The Intersil IH5043 is used for the third tier
of MUXing. Each You! point will see 3 OFF channels and 1
ON channel at anytime, so that the typical leakages will be
about 0.4nA. Throughput channel resistance will be in the
5500 area and throughput switching speeds about 1.3,..s
for ON time and 0.8,..s for OFF time.
The IH5043 was chosen as the third tier of the MUX because it will switch the same AC Signals as the IH6216 (typically plus and minus 15V) and uses break before make
switching. Also power supply quiescent currents are typically 1-2,..A so that no excessive system power is generated.
Note that the logic of the 5043 is such that it can be tied
directly to the ENable input (as shown in the figures) with no
extra logic being required.

For the system to function properly the EN input (pin 18)
must go to 5V ± 5% for the high state and less than 0.8V
for the low state. When using TTL logic, a pull-up of 1kO or
less resistor should be used to pull the output voltage up to
5V. When using CMOS logic, the high state goes to the
power supply so no pull-up is required.
If used on high voltage logic supplies, EN should be at
least 0.7V below V+ at all times. See IH6208 data sheet for
details.

APPLICATION NOTES
Further information may be found in:
A003 "Understanding and Applying the Analog Switch"
A006 "A New CMOS Analog Gate Technology"
A020 "A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing"
R009 "Reduce CMOS Multiplexer Troubles Through Proper Device Selection"
NOTE: This multiplexer does not require external resistors
and/or diodes to eliminate what is commonly known as a
latch up or SCR action. Because of this fact, the rOS(ON) of
the switch is maintained at specified values.

Enable input strobing levels
The ENable input acts as an enabling or disabling pin for
the IH6216 when used as a 2 out of 16 channel MUX, however when expanding the MUX to more than 16 channels,
the EN pin acts as another address input. Figures 6 and 7
show the EN pin used as the A3 input.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED.lN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: All typical vs/uss have been characterized but are not tested.

9-55

i

oII.)

...0

...o IH9108
I 8-Channel
CD

High-Voltage
Multiplexer with Latches

GENERAL DESCRIPTION
The IH9108 is an 8-channel multiple
~~s designed for high voltage (± 50V) application~(fl Icroprocessor based instrumentation and process control systems.
The multiplexer features true bi-directional switch action
over the full analog signal range. Interfacing with microprocessors is simplified by on-board data latches and control
pins.
The IH9108 utilizes D/CMOS junction isolation technology providing high breakdown voltage (> 120V). In addition,
the IH9108 features low ON resistance (350 typ) and extremely low leakages (0.5 nA typ). The multiplexer provides
8-channel single-ended multiplexing and demultiplexing. Individual channels are selected by addressing appropriate
data latches with binary coded inputs (Ao, A, and A2)'
Switch state inputs are stored or cleared via write WR and
device reset RS respectively. During system power-up or
reset, switch turn-off is simplified by RS. The IH9108 is
available over the commercial (O'C to 70'C), Industrial
( - 25'C to 85'C) and Military ( - 55'C to 125'C) temperature
range in 18 pin sidebraze package.

• Low Leakage Current

• ± SOV Analog Signal Range
• Low ON Resistance
• Latchable Logic Inputs
• Direct Reset (RS)

APPLICATIONS
•
•
•
•
•

Automatic Test Equipment
Ultrasound Medical Equipment
Microprocessor Controlled Systems
Communications Systems
Data Acquisition

ORDERING INFORMATION
Temperature
Range

Package

IH9108CDN

O'Cto 70'C

Sidebraze 18-pin

IH91081DN

- 25'C to 85'C

Sidebraze 18-pin

IH9108MDN

- 55'C to 125'C

Sidebraze 18-pin

Part
Number

Dual-In-Line Package

v+

WilCl
5,

AoC 2

52

VLC 3
V-C 4

53

o-+-------------~L-'--~~

54

SIC 5
S2 C 6

o

550

S3 C 7
S4 C 8

Ss
57

DC 9

S8

'-/

18 ~:JRS
17PA1
16pA2
IS :::JGND

IH9108

14 :::JV.
13 :::JSs
12 :::JS,
" :::J~
10 :::JS8
007B-3

Outline dwg. ON
Order Number: IH91081DN
Figure 2: Pin Configuration

007B-l

8-Channel Single Ended Multiplexer
Figure 1: Functional Diagram

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
306000-003
NOTE: All typical values have besn characterized but are not tested.

9-56

IIID~OIL.

IH9108

Storage Temperature ...•.•.•.....••.... - 55'C to 125'C
Power Dissipation (Package') .............•...•. 250 mW

ABSOLUTE MAXIMUM RATINGS
v+ ....•.•..................................... +62V
v- ............................................ -62V
Digital Inputs ....................... -0.3V to VL +0.3V
Continuous Current S or D .••..................... 30 mA
Peak Current, S or 0 (Note 1) .•••...•...•.•....•. 100 mA
Operating Temperature
(C Version) ..........................•... O'C to 70'C
(I Version) ....•....•.••.•.•.•......... - 25'C to 85'C
(M Version) ..••••.••.•...•........... - 55°C to 125°C

ELECTRICAL CHARACTERISTICS

Parameter

i
o011

•All leads soldered or welded 10 PC board.
NOTE: Stresses Bbove those listsd under "Absolute MBXimum RBtlngs"
may CBUse psrmsnent demsgs to ths davIce. Thsse Bre stress ratings only
Bnd functionsl operation of the device Bt /hess or Bny 01hBr conditions
above those indicBtsd in ths operatlonsl SBCIions o/the spec//iCBtIons is not
implied. Exposure to absolute mByimum rating conditions for extended per;.
ods may affect devics reliability.

Commercial and Industrial Grade

Test Conditions
(unless otherwise noted)
V+ = SOY, V- = -SOV, GND = VWfi = 0
VL = ViiS = 15V, TA = 25'C

Symbol

...

Limits
Units

Typ
Min

(Note 3)

Max

MULTIPLEXER
Analog Signal Range

Vanalog

Drain-Source ON Resistance

rOS(ON)

Source OFF Leakage Current
Drain OFF Leakage Current
Drain ON Leakage Current

IS(OFF)
IO(OFF)
IO(ON)

-50

+50

V

Vo = -50V, Is = 10 mA
-10V:S: Vo:S: +10V, Is = 10 mA
Vo = +50V, Is = 10 mA

25
35
95

35
50
120

{}

See Fig. 5 Vo = -50V, Vs = +50V
See Fig. 6Vs= -50V,Vo= +50V
See Fig. 7Vs = -50V, Vo = +50V

0.5
5
5

5
25
20

nA

VIN = OV (Note 2)
VIN = 15V (Note 2)

0.1
0.1

2
2

pA

RL = 5K,CL = 10pF See Fig. 3
See Fig. 3
Vs = ±50V
Fig. 8
See Fig. 4

1
0.5
25

2
1

See Fig. 3
See Fig. 3 twA = 500 ns
See Fig. 3
See Fig. 3

100
300
100
300

ns

14
85
110

pF

65

dB

INPUT
Input Currentllnput Low
Input Currentllnput High

IINL
IINH

DYNAMIC
Turn-ON TIme
Turn-OFF Time
Break-Before-Make Interval

toN
toFF
toPEN

Address Access Time
Address Hold TIme
Reset Pulse Width
Write Pulse Width

tA
tH

tFffi

twA

Source OFF CapaCitance
Drain OFF Capacitance
Channel ON CapaCitance

Vs= OV
CS(OFF)
Vo= OV
CO(OFF)
Co + s(ON) Vs= OV

OFF Isolation

OIRR

f=50kHz

VF[S = OV, RL = 2k, CL = 3 pF
Vanalog = 10Vp_p ,f = 100kHz

,..S
,..S
ns

SUPPLY
Positive Supply Current
Negative Supply Current
Logic Supply Current

1+
1-

VIN(all) = 0 or 15V (Note 2)

IL

0.002
0.003
0.002

2
2
2

,..A

NOTE 1: Pulsed all mS, 10% duty cycle.

2: Inputs are digital inputs lAo, AI> A2, AS and WR).
3: For design reference only, noI100% lested.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPUED OR STATUTORY, INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABILITY AND RTNESS FOR A PARTICULAR USE.

NOTE:AH typIcsJ

_have""""

_but/llflnot_/od.

9-57

•

!... IM8108
ca

!

ELECTRICAL CHARACTERISTICS
Parameter

Military Grade

Teat Conditions
(unless otherwise noted)
Y+ = 60Y, Y- = -60Y, GND = VWR = 0
YL = Vg = 15Y, TA = 25°C

Symbol

Umlts
Units

Typ
Min

(Note 3)

Max

MULTIPLEXER
Analog Signal Range

VanaloQ

Drain-Source ON Resistance

rOS(ON)

Source OFF Leakage Current
Drain OFF Leakage Current
Drain ON Leakage Current

IS(OFF)
IO(OFF)
IO(ON)

-50

+50

V

Vo = -50V, Is = 10 rnA
-10V ~ Vo ~ + 10V,Is = 10 rnA
Vo = +50V,ls = 10 mA

25
35
75

35
50
120

{}

SeeFig.5Vo= -50V,VS= +50V
See Fig. 6 Vs = -50V, Vo = +50V
SeeFig.7Vs= -50V,Vo= +50V

0.5
5
5

2
15
15

nA

VIN = OV (Note 2)
VIN = 15V (Note 2)

0.1
0.1

1
1

p.A

RL = 5K,CL = 10pF See Fig. 3
Vs = ±50V
See Fig. 3
Fig. 8
See Fig. 4

1
0.5
25

2
1

See Fig. 3
See Fig. 3 twJ!i = 500 ns
See Fig. 3
See Fig. 3

100
300
100
300

ns

14
85
110

pF

65

dB

INPUT
Input Current/Input Low
Input Current/Input High

IINL
IINH

DYNAMIC
Tum-ONTime
Tum-OFF Time
Break·Before·Make Interval

toN
toFF
toPEN

Address Access Time
Address Hold Time
Reset Pulse Width
Write Pulse Width
Source OFF CapaCitance
Drain OFF Capacitance
Channel ON Capacitance

tA
tH

tAB
twJ!i

Vs = OV
CS(OFF)
Vo= OV
CO(OFF)
Co + s(ON) Vs = OV

OFF Isolation

OIRR

f = 50kHz

VJ=m =

OV, RL = 2k, CL = 3 pF
VanalC)Q = 10 Vp•p, f = 100 kHz

p.S
p.S
ns

SUPPLY
Positive Supply Current
Negative Supply Current
Logic Supply Current

1+
1-

VIN(a1I) = 0 or 15V (Note 2)

IL

0.002
0.003
0.002

1
1
1

p.A

NOTE 1: Pulsed all mS. 10% duty cycle.
2: Inputs are digital inputs (Ao, A1, A2.

AS and WA).

3: Typical values are nollOO% tested, and are for design aid only.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.

NOTE:AHtyplcslvshJ6s". .. bson_butsrenotlo8ltld.

9·58

IH9108
TRUTH TABLE
A2 A, Ao WR
X X X
X X X
X X X
X

X

RS

ON Switch

0

None

1

Maintains previous
switch condition

X

J

J

1

X

L

J J

X

X

X

0

0

0

0

0

0

1

1

Latch Condition

Latches
Address

None

Latches Reset

One of eight
switches

Unlatches Reset
Not Allowed

0

1

1

0

1

2

0

0

1

3
4

1

0

1

1

0

1

1

0

0

0

1

5

1

0

1

0

1

6

1

1

0

0

1

7

1

1

1

0

1

Logic "1": VIN;' 0.7 (VO

8
Logic "0": VIN 0': 1.0V

0078-10

TIMING DIAGRAMS

+VL

~~------~~~~-t2t-~£-t-HjC=

~ ---------------------------------10%
OV

SOV

Vo
OV

+VL

RS

--90~%~-------

tON

---j
~ ~FF-------·i\~90-%--_____________~
__J/~9-0-%-----

5
tRS

---------10""%

90%

OV
0078-4

Figure 3: tON. tOFF Timing

SOV

__________________________to_P~E~~--------------------------

Vo
4SV
0078-5

Figure 4: Break-Before-Make Timing

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

9-59

.. IH9108
~

Gt

~ TEST CIRCUITS
SOY lSY -60Y

SOY lSY -SOY

DI-<1-.....

DI-O--'"

x x x

SEE TRUTH TABLE FOR
PROPER LOGIC

-SOy

. . . .SOY

1:

~

.SOY'"

i-SOY

-+

T
0078-8

0078-6

Figure 7: IO(ON) Test Circuit

Figure 5: IS(OFF) Test Circuit
SOY 15Y-6OV

01-0'-..,

60Y lSY -60Y

D

lSY
SK.Q
OV

GND

x
i-SOY

-

X X
.SOY'"

T

0078-9

0078-7

Figure 8: Break·Before·Make Test Circuit

Figure 6: IO(OFF) Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES QF-'
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical valuBs have besn charaCt6rizBd but are not t9sted.

9·60

2N2607 ............... 10-1
2N2608 ............... 10-1
2N2609 ............... 10-1
2N2609JAN ........... 10-1
2N3684 ............... 10-2
2N3685 ............... 10-2
2N3686 ............... 10-2
2N3687 ............... 10-2
2N3810/A ............. 10-3
2N3811 / A ............. 10-3
2N3821 ............... 10-5
2N3821JAN ........... 10-5
2N3821 JTX ............ 10-5
2N3821JTXV .......... 10-5
2N3822 ............... 10-5
2N3822JAN ........... 10-5
2N3822JTX ............ 10-5
2N3822JTXV .......... 10-5
2N3823 ............... 10-7
2N3823JAN ........... 10-7
2N3823JTX ............ 10-7
2N3823JTXV .......... 10-7
2N3824 ............... 10-8
2N3921 ............... 10-9
2N3922 ............... 10-9
2N3954 .............. 10-11
2N3954A ............. 10-11
2N3955 .............. 10-11
2N3955A ............. 10-11
2N3956 .............. 10-11
2N3957 .............. 10-11
2N3958 .............. 10-11
2N3970 .............. 10-13
2N3971 .............. 10-13
2N3972 .............. 10-13
2N3993 .............. 10-15
2N3994 .............. 10-15
2N4044 .............. 10-16
2N4045 .............. 10-16
2N4100 .............. 10-16
2N4878 .............. 10-16

Section 10

Discretes

2N4879 .............. 10-16
2N4880 .............. 10-16
2N4091 JANTX ........ 10-19
2N4091 .............. 10-19
2N4092JANTX ........ 10-19
2N4092 .............. 10-19
2N4093JANTX ........ 10-19
2N4093 .............. 10-19
ITE4091 .............. 10-19
ITE4092 .............. 10-19
ITE4093 .............. 10-19
2N4117 .............. 10-21
2N4117A ............. 10-21
2N4118 .............. 10-21
2N4118A ............. 10-21
2N4119 .............. 10-21
2N4119A ............. 10-21
2N4220 .............. 10-22
2N4221 .............. 10-22
2N4222 .............. 10-22
2N4223 .............. 10-23
2N4224 .............. 10-23
2N4338 .............. 10-24
2N4339 .............. 10-24
2N4340 .............. 10-24
2N4341 .............. 10-24
2N4351 .............. 10-25
2N4391 .............. 10-26
2N4392 .............. 10-26
2N4393 .............. 10-26
ITE4391 .............. 10-26
ITE4392 .............. 10-26
ITE4393 .............. 10-26
2N4416/ A ............ 10-28
ITE4416 .............. 10-28
2N4856 .............. 10-30
2N4856JAN,JTX,JTXV . 10-30
2N4857 .............. 10-30
2N4857JAN,JTX,JTXV .10-30
2N4858 .............. 10-30
2N4858JAN,JTX,JTXV . 10-30

2N4859 .............. 10-30
2N4859JAN,JTX,JTXV .10-30
2N4860 .............. 10-30
2N4860JAN,JTX,JTXV .10-30
2N4861 .............. 10-30
2N4861JAN,JTX,JTXV.10-30
2N4867 / A ............ 10-32
2N4868/ A ............ 10-32
2N4869/ A ............ 10-32
2N5018 .............. 10-33
2N5019 .............. 10-33
2N5114 .............. 10-35
2N5114JAN,JTX,JTXV.10-35
2N5115 .............. 10-35
2N5115JAN,JTX,JTXV .10-35
2N5116 .............. 10-35
2N5116JAN,JTX,JTXV .10-35
2N5117 .............. 10-37
2N5118 .............. 10-37
2N5119 .............. 10-37
2N5196 .............. 10-39
2N5197 .............. 10-39
2N5198 .............. 10-39
2N5199 .............. 10-39
2N5397 .............. 10-41
2N5398 .............. 10-41
2N5432 .............. 10-43
2N5433 .............. 10-43
2N5434 .............. 10-43
2N5452 .............. 10-45
2N5453 .............. 10-45
2N5454 .............. 10-45
2N5457 .............. 10-47
2N5458 .............. 10-47
2N5459 .............. 10-47
2N5460 .............. 10-48
2N5461 .............. 10-48
2N5462 .............. 10-48
2N5463 .............. 10-48
2N5464 .............. 10-48
2N5465 .............. 10-48

•

Section 10
2N5484 .............. 10-50
2N5485 .............. 10-50
2N5486 .............. 10-50
2N5515 .............. 10-52
2N5516 .............. 10-52
2N5517 .............. 10-52
2N5518 .............. 10-52
2N5519 .............. 10-52
2N5520 .............. 10-52
2N5521 .............. 10-52
2N5522 .............. 10-52
2N5523 .............. 10-52
2N5524 .............. 10-52
2N5638 .............. 10-54
2N5639 .............. 10-54
2N5640 .............. 10-54
2N5902 .............. 10-56
2N5903 .............. 10-56
2N5904 .............. 10-56
2N5905 .............. 10-56
2N5906 .............. 10-56
2N5907 .............. 10-56
2N5908 .............. 10-56
2N5909 .............. 10-56
2N5911 .............. 10-58
2N5912 .............. 10-58
IT5911 ............... 10-58
IT5912 ............... 10-58
ITC5911 ............. 10-58
ITC5912 ............. 10-58
2N6483 .............. 10-60
2N6484 .............. 10-60
2N6485 .............. 10-60
3N161 ............... 10-62
3N163 ............... 10-63
3N164 ............... 10-63
3N165 ............... 10-65
3N166 ............... 10-65
3N170 ............... 10-67
3N171 ............... 10-67
3N172 ............... 10-69
3N173 ............... 10-69
3N188 ............... 10-71

Discretes (Continued)

3N189 ............... 10-71
3N190 ............... 10-71
3N191 ............... 10-71
10100 ................ 10-73
10101 ................ 10-73
IT100 ................ 10-75
IT101 ................ 10-75
IT120 ................ 10-76
IT120A ............... 10-76
IT121 ................ 10-76
IT122 ................ 10-76
IT126 ................ 10-78
IT127 ................ 10-78
IT128 ................ 10-78
IT129 ................ 10-78
IT130 ................ 10-80
IT130A ............... 10-80
IT131 ................ 10-80
IT132 ................ 10-80
IT136 ................ 10-82
IT137 ................ 10-82
IT138 ................ 10-82
IT139 ................ 10-82
IT500 ................ 10-84
IT501 ................ 10-84
IT502 ................ 10-84
IT503 ................ 10-84
IT504 ................ 10-84
IT505 ................ 10-84
IT1700 ............... 10-87
IT1750 ............... 10-88
J105 ................. 10-89
J106 ................. 10-89
J107 ................. 10-89
J108 ................. 10-90
J109 ................. 10-90
J110 ................. 10-90
J111 ................. 10-91
J112 ................. 10-91
J113 ................. 10-91
J174 ................. 10-92
J175 ................. 10-92

J176 ................. 10-92
J177 ................. 10-92
J201 ................. 10-94
J202 ................. 10-94
J203 ................. 10-94
J204 ................. 10-94
J308 ................. 10-95
J309 ................. 10-95
J310 ................. 10-95
LM114/H ............ 10-97
LM114A1 AH .......... 10-97
M116 ................ 10-99
U200 ............... 10-100
U201 ............... 10-100
U202 ............... 10-100
U231 ............... 10-101
U232 ............... 10-101
U233 ............... 10-101
U234 ............... 10-101
U235 ............... 10-101
U257 ............... 10-103
U304 ............... 10-104
U305 ............... 10-104
U306 ............... 10-104
U308 ............... 10-106
U309 ............... 10-106
U310 ............... 10-106
U401 ............... 10-108
U402 ............... 10-108
U403 ............... 10-108
U404 ............... 10-108
U405 ............... 10-108
U406 ............... 10-108
U1897 .............. 10-110
U1898 .............. 10-110
U1899 .............. 10-110
VCR2N ............. 10-112
VCR3P ............. 10-112
VCR4N ............. 10-112
VCR5P ............. 10-112
VCR7N ............. 10-112
VCR118 ............ 10-115

U~U[6io

2N2607-2N2609

P-Channel JFET
General Purpose Amplifier

....oI
N
Z
N

APPLICATIONS

ABSOLUTE MAXIMUM RATINGS

• Low-Level Choppers
• Data Switches

(TA = 25'C unless otherwise noted)
Gate-Source Voltage "', ... , .. ,", ..... , ..... , ... 30V
Gate-Drain Voltage " .. ,.".,", .. " ..... , .. , ..... 30V
Gate Current .. " .... , ... ,., ... , " " " " ' , .. ,.,' 50mA
Storage Temperature Range. , ... , , .. , -65'C to + 200'C
Operating Temperature Range " " " " - 55'C to + 175'C
Lead Temperature (Soldering, 10sec) ..... , ..... + 300'C
Power Dissipation .. , .. , ......... , ..... , .... ,'. 300mW
Derate above 25'C .,", .. " .... ,." ........ 2mW I'C

• Commutators

PIN CONFIGURATION
TO·18

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may CBuse permanent damage to the device. These are stress ratings only
and functional operation of the device sf these or any other conditions
above those indicated in the operational sections of the specifications is not
implied Exposure to absolute maximum rating conditions for extended peri~
ods may affect device reliabl7ity.

ORDERING INFORMATION
TO-1S

o

G,C

2N2607

0200-1

2N2608

5510-2N2607,8
5503-2N2609

2N2609

ELECTRICAL CHARACTERISTICS
Symbol

(TA = 25'C unless otherwise specified)

Test Conditions

Parameter

2N2607
Min

Max

2N2609
Min

Units

Max

3

10

30

nA

VGs=5V, VOs=O, TA=150'C

3

10

30

p.A

Gate Reverse Current

BVGSS

Gate-Source Breakdown
Voltage

lG=lp.A, VOs=O

Vp

Gate-Source Pinch-Off
Voltage

VOs= -5V, 10= -lp.A

loss

Drain Current at Zero Gate
Voltage

VOs= -5V, VGS=O

gls

Small-Signal Common-Source VOs= -5V, VGS=O, f=lkHz
Forward Transconductance

Ciss

Common-Source Input
Capacitance
Noise Figure (Note 1)

2N2608
Min

VGs=30V, VOs=O

IGSS

NF

Max

30

VOs= -5V, VGS= 1V,
f= 1MHz (Note 1)
VOs= -5V,

IRG=10Mfl
I

VGS=O, f= 1kHz RG= lMfl

1

30
4

1

4

-0,30 -1.50 -0.90 -4.50

10

1

4

V

-2

-10

mA
p.S

2500

1000

330

V

30

17

30

3

3

3

pF
dB

NOTE 1: For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

10-1

o
o
G

D~nlL

:; 2N3684-2N3687
z=: N-Channel JFET
...CD~ Low Noise Amplifier
CD

FEATURES

ABSOLUTE MAXIMUM RATINGS

Z

• Low Noise
• High Input Impedance
• Low CapaCitance

(TA = 25'C unless otherwise noted)
Gate-Source or Gate-Drain Voltage ............... -50V
Gate Current ................................... 50mA
Storage Temperature Range .......... -65'C to + 200'C
Operating Temperature Range ........ -55'C to + 175'C
Lead Temperature (Soldering, 10sec) ........... + 300'C
Power Dissipation ............................. 300mW
Derate above 25'C ....................... 2.0mW/'C

'"w

APPLICATIONS
•
•
•
•

Low Level Choppers
Data Switches
Multiplexers
Low Noise Amplifiers

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at /hese or any o/her conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended peri·
ods may affect device reliability.

PIN CONFIGURATION
TO-72

ORDERING INFORMATION
TO·72
2N3684
2N3685
2N3686
2N3687

o
0201-1

5010

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA

25'C unless otherwise noted)

=

Test Conditions

2N3684
Min

BVGSS

Gate to Source Breakdown Voltage

VDS~O,IG~I.0I-'A

-50

Vp

Pinch-Off Voltage

VDs~20V,ID~0.001I-'A

-2.0

IGSS

Gate Leakage Current

VGS~

-30V,

VDS~O

I TA~150'C
IDSS

Saturation Current, Drain-to-Source

IVis I

Forward Transadmittance

Gos

Common Source Output
Conductance

Ciss

Common Source Input
CapaCitance

VGS~O, VDS~20V

VDS~20V, VGS~O
f~lkHz

2N3685

Max

Min

-5.0

-1.0

2N3686

Max

Min

-3.5

-0.6

-50

2N3687

Max

Min

-2.0

-0.3

-50

-50

Units

Max
V
-1.2

-0.1

-0.1

-0.1

-0.1

nA

-0.5

-0.5

-0.5

-0.5

I-'A

0.1

0.5

rnA

500

1500

I-'s

2.5

7.5

2000

3000

1.0

3.0

1500 2500

0.4

1.2

1000 2000

50

25

10

5

I-'s

4.0

4.0

4.0

4.0

pF

1.2

pF

VDS~20V, VGS~O

Crss

Common Source Short Circuit
Reverse Transfer Capacitance

f~

rDS(on)

On Resistance

VDS~O, VGS~O

NF

Noise Figure (Note 1)

f~100Hz, RG~

lMHz (Note 1)

NBW~6Hz,

10M!}
VDs=10V,

1.2

1.2

1.2

600

800

1200

0.5

0.5

0.5

2400 ohms
0.5

dB

VGS~OV

NOTE 1: For design reference only, not 100% tested.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not testsd.

10·2

D~DlLi...

2N3810/A,2N3811/A
Monolithic Dual Matched PNP
General Purpose Amplifier

CD

One Side
500mW
3.3mWrC

Power Dissipation ..
Derate above 25°C
B.

C.

Both Sides
600mW
4.0mWrC

NOTE: StrrIssss abovs thost!J /istsd under "Absoluts MSJdmum Ratings"
msy causa permsnsnt dsmsge to the rJevics. Thss911J'9 strsss ratings only
and functional operstion of the rJevics at _
or any 0_ conditions
llbovs those indicstsd in the operstional sections of the spscIfications Is not
/mp//sd. Exp0sur6 to absoiuts maximum rating conditions for exlsnrJed psriods msyaffBct rJevics f6Iisbility.

0202-1

4501

ORDERING INFORMATION
To-78
2N3810
2N3810A
2N3811
2N3811A

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25°C unless otherwise specified)

2N3810/A

2N3811/A

Min

Min

Unlta

Test Conditions
Max

BVCBO

Collector-Base Breakdown Voltage

Ic= -10p,A, IE=O

-60

-60

BVCEO

Collector-Emitter Breakdown Voltage
(Note 2)

IC= -10mA,IB=O

-60

-60

BVEBO

Emitter-Base Breakdown Voltage

IE= -10,...A.lc=0

-5

-5

lC(off)

Collector Cutoff Current

Vce= -50V,IE=0
TA= + 150"C

IE(off)

Emitter Cutoff Current

hFE

Static Forward Current
Transfer Ratio

VBE=4V,lc=0

VCE=-5V

Max

V

-10

-10

nA

-10

-10

,...A

-20

-20

nA

IC=-10p,A

100

Ic= -100,...A to -1mA

150

225

Ic = 10mA (Note 2)

125

250

Ic=100p,A, TA= -55°C

75

150

450

300

900

INTERSIL'S SOLE AND EXCWSlVE WARRANTY DBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXClUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPREss. IMPLIED OR STATUTORY, INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AN typIuI_ "".. """" _ _ but.,. not,.1«/.

10-3

r:
N

(TA = 25°C unless otherwise noted)
Emitter-Base Voltage (Note 1) .......... .. .. .. .. ... - 5V
Collector-Base or Collector-Emitter Voltsge
(Note 1) ..................................... -60V
Collector Current (Note 1) ....................... 50mA
Storage Temperature Range .......... -65°C to + 175°C
Operating Temperature Range ........ -55°C to + 175°C
Lead Temperature (Soldering, 10sec) ...•....... +300°C

T()'78

E.

~

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

CD
:::

~

...~...

.D~OIL

2N3810/A, 2N3811/A

CD
f')

z

ELECTRICAL CHARACTERISTICS

(Continued) (TA = 25°C I,Inless otherwise specified)

C\I

~...
CD

Symbol

2N3811/A
Units

Test Conditions
Min

Max

Min

Max

Base-Emitter Saturation
Voltage

Ic= -100",A, le= -to",A

-0.7

-0.7

Ic= -1.0",A,le= -tOO",A

-0.8

-0.8

VCE(sat)

Collector-Emitter Saturation
Voltage (Note 2)

IB= -to",A,lc= -tOO",A

-0.2

-0.2

hie

Input Impedance (Note 4)

VCE=-10V

hie

Forward Current Transfer
Ratio (Note 4)

Ic= -lmA

hre

Reverse Voltage Transfer
Ratio (Note 4)

f= 1kHz

hoe

Output Admittance (Note 4)

Ihlel

Magnitude of small signal
current gain (Note 4)

VeE(sat)

f')

Z

C\I

2N3810/A

Parameter

le= -100",A,lc= -lmA

-0.25

-0.25

3

30

10

40

150

600

300

900

0.25

VCE= -5V

5

60

5

60

1

5

1

5

Ic= -500",A,
f=30MHz

1

Output Capacitance (Note 4)

Vce= -5V,IE=O, f=IMHz

4

4

eibo

Input Capacitance (Note 4)

Vce= -0.5V,lc=O, f=IMHz

8

8

hFEl/hFE2

DC Current Gain Ratio

VCE= -5V,lc=100",A

0.9

1.0

0.95

1.0

-2.5

-3

-3

-1.5

-1.5

10

10

5

5

VCE= -10V,lc= -100",A, RG=3k!l,
f= 100Hz, Noise Bandwidth=20Hz

7

4

VCE= -10V,lc= -tOO",A, RG=3K!l
f = 1kHz, Noise Bandwidth = 200kHz

3

1.5

VCE= -10V,lc= -100",A, RG=3k!l

2.5

1.5

3.5

2.5

t.vBEI-VBE2 Base-Emitter Voltage
VCE= -5, Ic= 100",A
aT
Differential Gradient 1A devices

pF

1.0

-2.5
Ic= 100",A

Spot Noise Figure
(Note 4)

1.0

-5

.1 A devices

NF

0.9
0.95

-5

Ic= 10",A to 10mA

"'S

1

Cobo

VCE=-5V
IVBEI-VeE2 I Base-Emitter Voltage
Differential
IA devices

k!l

0.25

Ic= -lmA,
f=100MHz

1A devices

V

mV

",VloC

dB

f = 10kHz, Noise Bandwidth = 2kHz

VCE= -10V,lc= -100",A, RG=3k!l,
Noise Bandwidth = 15. 7kHz (Note 3)
NOTES: I.
2.
3.
4.

Per transistor.
Pulse width:;:300,.s, duty cycle:;:2.0%.
3dB down at 10Hz and 10kHz.
For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tssted.

10-4

2N3821, 2N3822, JAN,
JTX, JTXV
N-Channel JFET
High Frequency Amplifier
FEATURES

ABSOLUTE MAXIMUM RATINGS

• Low Capacitance

(TA = 25'C unless otherwise noted)
Gate-Source Voltage ........................... - 50V ~
Gate-Drain Voltage ............................. -50V ~
Gate Current ................................... 10mA c..
Storage Temperature Range .. . . . . . . .. - 65'C to + 200'C ...
Operating Temperature Range ........ -55'C to + 175'C ~
Lead Temperature (Soldering, 10sec) ........... +300'C
Power Dissipation ............................. 300mW ~
Derate above 25'C ....................... 2.0mWI'C

• Up to 6500",s Transconductance

PIN CONFIGURATION
TO-72

,~
o

5010-2N3821
5010-2N3822

=

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the deviC9. These are stress ratings only

and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect deviC9 reliability.

0203-1

ORDERING INFORMATION
TO-72
2N3821
2N3822

t

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

add JAN. JTX. JTXV to basic part number to specify these devices.

(TA = 25'C unless otherwise specified)
Test Conditions

2N3821
Min

IGSS

Gate Reverse Current

VGS= -30V, VOs=O

BVGSS

Gate-Source Breakdown Voltage

IG= -1 ",A, VOs=O

VGS(off)

Gate-Source Cutoff Voltage

Vos=15V,lo=0.5nA

VGS

Gate-Source Voltage

Vos=15V,lo=50",A

Max
-0.1

I TA= 150'C

-0.1
-50

-4
-0.5

Saturation Drain Current (Note 1)

Vos=15V, VGS=O

0.5

Units

Max
-0.1

nA

-0.1

",A

-50
-6

V

-2

Vos=15V,lo=200",A
loss

2N3822
Min

2.5

-1

-4

2

10

mA

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values havs been characterized but are not testsd.

10-5

~

2N3821, 2N3822, JAN, JTX, JTXV

,~

ELECTRICAL CHARACTERISTICS

Z

Symbol

CIi

9ts

Common-Source Forward
Transconductance (Note 1)

iYfs I

Common-Source Forward
Transadmittance (Note 2)

gos

Common-Source Output
Conductance (Note 1)

Ciss

Common-Source Input
Capacitance (Note 2)

~

CIII

to

'"

Z

ell

Parameter

Crss

Common-Source Reverse Transfer
Capacitance (Note 2)

NF

Noise Figure (Note 2)

en

Equivalent Input Noise Voltage
(Note 2)

(Continued) (TA = 25'C unless otherwise specified)

Test Conditions

VOS= 15V, VGS=O

2N3821

2N3822

Min

Max

Min

Max

f=1kHz

1500

4500

3000

6500

f= 100MHz

1500

f=1kHz

3000

",s

10

20

6

6

f=1MHz

Vos=15V, VGS=O,
Rgen =1meg, BW= 5Hz

Units

pF
3

3

5

5

dB

200

200

~

f=10Hz

VOS= 15V, VGS=O,
BW=5Hz

nV

NOTES: 1. These parameters are measured during a 2ms interval 100ms after DC power is applied.
2. For design reference only, not 100% tested.

tNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but ars not tested.

10-6

2N3823,JAN,JTX,JTXV

N-Channel JFET
High Frequency Amplifier
FEATURES

ABSOLUTE MAXIMUM RATINGS

• Low Noise
• Low Capacitance
• Transductance Up to 6500/LS

(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage ",.,.......... - 30V
Gate Current ................................... 10mA
Storage Temperature Range .......... -65°C to + 200°C
Operating Temperature Range ........ -55°C to + 175°C
Lead Temperature (Soldering, 1Osee) ........... + 300°C
Power Dissipation ............................. 300mW
Derate above 25°C ....................... 2.0mW

PIN CONFIGURATION

rc

TO-72

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functionsl operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING INFORMATION

0204-1

t

5000

ELECTRICAL CHARACTERISTICS
Symbol
IGSS

Parameter
Gate Reverse Current

add JAN, JTX, JTXV to basic part number to specify these devices,

(TA = 25°C unless otherwise specified)
Test Conditions

Min

VGS= -20V, VOs=O
TA= 150°C

BVGSS

Gate-Source Breakdown Voltage

IG= -1/LA, VOs=O

VGS(off)

Gate-Source Cutoff Voltage

Vos=15V,lo=0.5nA

VGS

Gate-Source Voltage

VOS= 15V, lo=4OO/LA
Vos=15V, VGS=O

6,500

3,500

IVlsl

Common-Source Forward
Transadmittance (Note 2)

f=100MHz

3,200

gos

Common-Source Output
Conductance (Note 1)

f= 1kHz

giss

Common-Source Input
Conductance (Note 2)

Common-Source Reverse
Transfer Capacitance (Note 2)

NF

Noise Figure (Note 2)

V

20

f=1kHz

Crss

-8
4

Saturation Drain Current

Common-Source Input
CapaCitance (Note 2)

/LA

-7.5

Common-Source Forward
Transconductance (Note 1)

Ciss

nA

-0.5

-1.0

loss

Common-Source Output
Conductance (Note 2)

Units

-30

gls

goss

Max
-0.5

35

mA

/Ls

800

VOS=15V, VGS=O
f=200MHz

200
6
pF

f=1MHz
2
Vos=15V, VGS=O
RG=1kO

f=100MHz

2.5

dB

NOTES: 1. These parameters are measured during a 2ms interval100ms after DC power is applied.
2. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are not tested.

10-7

Co.

-t

.?<
Co.

=
-t

:; 2N3824

z~ N-Channel JFET
(II

Switch

FEATURES

ABSOLUTE MAXIMUM RATINGS

• rds<250 Ohms

(TA = 25'C unless otherwise noted)
Gate-Source or Gate-Drain Voltage ............... - 50V
Gate Current ................................... 10mA
Storage Temperature Range . . . . . . . . .. - 65'C to + 200'C
Operating Temperature Range ........ - 55'C to + 175'C
Load Temperature (Soldering,10sec) ........... +SOO'C
Power Dissipation ............................. SOOmW
Derate above 25'C ....................... 2.0mWI'C

• IO(Offl < 0.1 nA

PIN CONFIGURATION
TO-72

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions

above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended pen:.
ods may affeot device reliability.

ORDERING INFORMATION
0205-1

5003

ELECTRICAL CHARACTERISTICS

(TA = 25'C unless otherwise specified)
Limits

Symbol

Parameter

Units

Test Conditions
Min

IGSS

Gate Reverse Current

-0.1

nA

-0.1

IJ-A

0.1

nA

TA = 150'C

0.1

IJ-A

f= 1kHz

250

(1

VGS= -SOV, VDS=O
TA = 150'C

BVGSS

Gate-Source Breakdown Voltage

-50

IG= -1IJ-A, VDS=O

ID(eHl

Drain Cutoff Current

VDS= 15V, VGS= -8V

rds(enl

Drain-Source ON Resistance

VGs=OV,ID=O

Ciss

Common-Source Input Capacitance
(Note 1)

VDS=15V, VGS=O

Max

V

6
pF

f=1MHz
Crss

Common-Source Reverse Transfer
Capacitance (Note 1)

VGS= -8V, VDS=O

S

NOTE 1: For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but ere not tested.

10-8

2N3921, 2N3922
Monolithic Dual N-Channel JFET
General Purpose Amplifier
N

Z

FEATURES

ABSOLUTE MAXIMUM RATINGS

• Low Drain Current
• High Output Impedance

(TA = 25'C unless otherwise noted)
Gate-Source or Gate-Drain Voltage (Note 1) .... _.. - 50V
Gate Current (Note 1) ............................ 50mA
Storage Temperature Range ...•.•.... -65'C to + 200'C
Operating Temperature Range ........ - 55'C to + 200'C
Load Temperature (Soldering, 1(lsec) ........... + 300'C
Total Power Dissipation ....... '•..........•..... 300mW
Derate above 25'C ....................... 1.7mW/'C

• Matched VGS. aVGS. and gf.

PIN CONFIGURATION
TO-71

Col

NOTE: Stresses abovs those listed under "Absolute MBXimum Ratings"
may cause pt1IfTIBfI8nt damage /0 /he device. Thess aflJ stress ratings only
and functionsl operation of the device at /hess or any other conditions
above those indiCBt9d in /he operationsl sBCtions of the specifications is not
implied. ExposuflJ /0 absolul8 maximum rating conditions for BXl8nded perfods may affect device reliability.

ORDERING INFORMATION
TO-71
2N3921
2N3922

0208-1

6037

ELECTRICAL CHARACTERISTICS
Symbol
IGSS

(TA = 25'C unless otherwise specified)

Parameter
Gate Reverse Current

Test Conditions

Min

VGS= -30V, VOs=O
TA=100'C

BVOGO

Drain-Gate Breakdown Voltage

10=1IJ.A,ls=0

VGS(off)

Gate-Source Cutoff Voltage

Vos=10V,10=1nA

VGS

Gate-Source Voltage

VOS= 10V, 10= 1OOIJ.A

IG

Gate Operating Current

VOG=10V,10= 7OOIJ.A

loss
gts

Common-Source Forward
Transconductance (Note 2)

gos

Common-Sourbe Output Conductance

Ciss

Common-Source Input Capacitance
(Note 3)

Crss

Common-Source Reverse Transfer
Capacitance (Note 3)

gts

Common-Source Forward Transconductance

goss

Common-Source Output Conductance

NF

Spot Noise Figure
(Note 3)

Units

-1

nA

-1

IJ.A

-3

V

50

-0.2

-2.7
-250

Vos=10V, VGS=O

pA

-25

nA

1

10

mA

1500

7500

TA=100'C
Saturation Drain Current (Note 1)

Max

f=1kHz

IJ.s
35

Vos=10V, VGS=O

18
f=1MHz

VOG=10V,10= 7OOIJ.A

f=1kHz

pF

6
1500

IJ.s
20

Vos=10V, VGS=O

f= 1kHz,
RG=1meg!1

2

dB

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical va/uss have bHn chBracfBrlzsd but 8m not t6sted.

10-9

~

::

2N3921,2N3922

...
(II

M~TCHING

CHARACTERISTICS

Symbol

(TA = 25·C unless otherwise specified)

Parameter

Test Conditions

0)
CO)

Z

(II

2N3921
Min

IVGSI -vGS21

Differential Gate-Source Voltage

AlvGSl -vGS21
AT

Gate-Source Differential Voltage
Change with Temperature

9lsl/gls2

VDG=10V,
ID=700".A

TA=O·C
Ts= 100·C
f=1kHz

Transconductance Ratio

0.95

Max

2N3922
Min

Units

Max

5

5

mV

10

25

".vrc

1.0

0.95

1.0

NOTES: 1. Per transistor.
2. Pulse test duration = 2 ms.
3. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

10-10

2N3954-2N3958
2N3954A/2N3955A

Monolithic Dual N-Channel JFET
General Purpose Amplifier
FEATURES

ABSOLUTE MAXIMUM RATINGS

•
•
•
•
•

(TA= 25'C unless otherwise noted)
Gate-Drain or Gate-Source Voltage ............... - 50V
Gate-to-Gate Voltage ........................... ± 50V
Gate Current ................................... 50mA
Total Device Dissipation 85'C (Each Side) ........ 250mW
Case Temperature
(Both Sides) ....... 500mW
Power Derating (Each Side) ................. 2.86mWI'C
(Both Sides) ................. 4.3mWI'C
Storage Temperature Range .......... - 65'C to + 200'C
Lead Temperature (1/16" from case
for 10 seconds) .............................. 300'C

~

NOTE: Stresses above those listed under "Absolute Maximum Ratings"

..

Low Offset and Drift
Low Capacitance
Low Noise
Superior Tracking Ability
Low Output Conductance

PIN CONFIGURATION
TO-71

msy cause permanent damage to the device. These are stress ratings only

and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied Exposure to absolute maximum rating conditions for extended peri·
ods may affect device reliability.

ORDERING INFORMATION
TO·71
2N3954

0207-1

6037

2N3954A
2N3955
2N3955A
2N3956
2N3957
2N3958

ELECTRICAL CHARACTERISTICS
Symbol
IGSS

Parameter
Gate Reverse
Current

Test Conditions

(T A

2N3954

Min

VGS= -30V,
VOS=O
ITA=150'C

Max

= 25'C unless otherwise specified)

2N3954A

Min

Max

2N3955

Min

Max

2N3955A

Min

Max

2N3956

Min

Max

2N3957

Min

Max

2N3958

Min

Max

-100

-100

-100

-100

-100

-100

-100

pA

-500

-500

-500

-500

-500

-500

--500

nA

BVGSS Gate·Source
Breakdown
Voltage

VOS=O
IG=-1"A

-50

VGS(off) Gate-Source
Cutoff Voltage

Vos=20V,
ID=1nA

-1.0 -4.5 --1.0 -4.5 -1.0 -4.5 -1.0 -4.5 -1.0 -4.5 -1.0 -4.5 -1.0 -4.5

VGS(f)

Gate-Source
VOS=O
Forward Voltage IG=1mA

VGS

Gate-Source
Voltage

IG

Units

-50

--50

-50

-50

-50

-50

V

Vos=20V i'D=50"A

2.0

2.0

2.0

2.0

2.0

2.0

2.0

-4.2

-4.2

-4.2

-4.2

-4.2

-4.2

-4.2

I)D=200"A -0.5 -4.0 -0.5 -4.0 -0.5 -4.0 -0.4 -4.0 -0.5 -4.0 -0.5 -4.0 -0.5 -4.0

Gate Operating Vos=20V,
Current
lo=200"AITA = 125'C

-50

-50

-50

-50

-50

-50

-50

pA

-250

-250

-250

-250

-250

-250

-250

nA

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

10-11

N
Z
Col

~

...
N

Z
Col

CD

g:

cII) 2N3954-2N3958 2N3954A/2N3955A
II)

o

;

•.

ELECTRICAL CHARACTERISTICS

(\I

Symbol

Parameter

loss

Saturation Drain
Current

z(\I

915

Common-Source
Forward
Transconductance

CD

II)

oCO)

z(\I

.

Common-Source
Output
Conductance

90S

Common-Source
Input Capacitance
(Note 2)

iss

I

II)

oCO)

2N3954

2N3954A

2N3955

2N3955A

2N3958

2N3957

2N3958

Units

Min Max Min Max Min Max Min Max Min Max Min Max Min Max

II)

oCO)

Test Conditions

(Continued) (TA = 25'C unless otherwise Specified)

VOS-20V,
VGs=O
f=lkHz
(Note 2)

z

(\I

5.0

0.5

5.0

0.5

5.0

0.5

5.0

0.5

5.0

0.5

5.0

0.5

5.0

rnA

1000 3000 1000 3000 1000 3000 1000 3000 1000 3000 1000 3000 1000 3000

f=200MHz 1000
f=lkHz

1000

1000

1000

1000

1000

1000

pos

35

35

35

35

35

35

35

4.0

4.0

4.0

4.0

4.0

4.0

4.0

1.2

1.2

1.2

1.2

1.2

1.2

1.2

Vos=20V,
VGS=O

Common Source
Reverse Transfer
Capacitance (Note 2)

Crso

0.5

f=IMHz

pF

Cdgo

Drain-Gate
VOG=10V,
Capacitance (Note 2) Is=O

1.5

1.5

1.5

1.5

1.5

1.5

1.5

NF

Common-Source
Spot Noise
Fi9ure (Note 2)

Vos=20V f= 100Hz
VGS=O
RG=10Mn

0.5

0.5

0.5

0.5

0.5

0.5

0.5

dB

IIGI -IG21

Differential Gate
Current

Vos=20V,
T=125'C
10 = 200poA

10

10

10

10

10

10

10

nA

IOSS1110SS2

Drain Saturation
Current Ratio

VOS= 20V
VGS=O

0.95 1.0 0.95 1.0 0.95 1.0 0.95

I VGSI - vGS21 Differential
Gate-Source
Voltage
Gate-Source
Differential
.:I.IVGS1-VGS21 Voltage Change
With Temperature
.:I.T
9151/9102

T=25'C
to -55'C
Vos=20V,
ID=200poA T=25'C
to 125'C

Transconductance
Ratio

f=lkHz

1.0 0.95 1.0 0.90 1.0 0.85 1.0

5.0

5.0

10.0

5.0

15

20

25

0.8

0.4

2.0

1.2

4.0

6.0

8.0

1.0

0.5

2.5

1.5

5.0

7.5

10.0

mV

0.97 1.0 0.97 1.0 0.97 1.0 0.95 1.0 0.95 1.0 0.90 1.0 0.85 1.0

NOTES: 1. Per Transistor.

2. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE; All typical values have been characterized but are not tested.

10-12

2N3970-2N3972

N-Channel JFET Switch

FEATURES

ABSOLUTE MAXIMUM RATINGS

• Low rOS(on)

(TA = 25·C unless otherwise noted)
Gate-Source or Gate-Drain Voltage ____ . _...... _. _ -40V
Gate Current _. _... __ . _. _.. _... __ . _. _. _.. _. _. _. _ 50mA
Storage Temperature Range .. _.. __ ... -65·C to + 200·C
Operating Temperature Range _...... _ - 55·C to + 200·C
Lead Temperature (Soldering, 10sec) . _. _.... _. _ +300·C
Power Dissipation @ 25·C Case Temp_ ... _. ____ ... _ I.BW
Derate above 25·C _. _. _...... __ ... _.. _. _. _ 10mWrC

• IO(OFF)<250pA

• Fast Switching

PIN CONFIGURATION
TO-18

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These BrB stress (stings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING INFORMATION
TO-18
2N3970

o

2N3971

0206-1

5001

2N3972

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25·C unless otherwise specified)
2N3970

Test Conditions

Min
BVGSS

Gate Reverse Breakdown Voltage

IG= -l",A, VOs=O

lOGO

Drain Reverse Current

VOG=20V.ls=0

10(off)

Drain Cutoff Current

VOG=20V, VGS= -12V

Max

-40

2N3971
Min
-40

250
TA=150·C

TA=150·C

Max

2N3972
Min
-40

V

250

250

pA

500

500

500

nA

250

250

250

pA

500

500

500

nA

VGS(Off)

Gate-Source Cutoff Voltage

Vos=20V,10=lnA

-4

-10

-2

-5

-0.5

-3

loss

Saturation Drain Current
(Pulse width 300",s, duty cycleS:3%)

VOS= 20V, VGS=O

50

150

25

75

5

30

VOSlon)

Drain-Source ON Voltage

VGS=O

10= 5mA

Static Drain-Source ON Resistance

VGs=O,lo=lmA

Drain-Source ON Resistance

VGs=O,lo=O

CiSS

Common-Source Input CapaCitance

Vos=20V, VGS=O
(Note 1)

erss

Common-Source Reverse Transfer
Capacitance

VOs=O, VGS= -12V
(Note 1)

10

Turn-On Delay Time (Note 1)

VOo= 10V, VGS(on)=O
10(on)
VGS(off)

tr

Rise Time (Note 1)

toff

Turn-Off Time (Note 1)

2N3970
2N3971
2N3972

20mA
10mA
5mA

1
30

60

100

30

60

100

25

25

25

f=1MHz

6

6

6

RL

10

15

40

4500
8500
1.6KO

10

15

40

30

60

100

f= 1kHz

-10V
- 5V
- 3V

V

1.5

10=20mA

rds(on)

V
mA

2

10=10mA

rOS(on)

Units

Max

0

pF

ns

NOTE 1: For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

10-13

C\I
2N3970-2N3972
....

ell
C')

Z

C\I

ELECTRICAL CHARACTERISTICS

(Continued)

I

....o

VDD

ell
C')

R

Z

C\I

o
VIN

_ VDD"VDs(ON)
L II)(ON)

INPUT PULSE

~VOUT

1-,

<>-___- .......

~

Ro

SAMPLING SCOPE

Rise Time

0.25 ns

Rise Time

0.4 ns

Fall Time

0.75 ns

Input Resistance

10 MO

Pulse Width

200 ns

Input Capacitance

1.5 pF

PulsaRa!e

550 pps

500 ~

~

~
0208-3

Figure 1: Switching Time Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tesl6d.

10·14

2N3993,2N3994
P-Channel JFET
General Purpose AmplifierISwitch
IIJ

FEATURES

ABSOLUTE MAXIMUM RATINGS

Z

• Low rOS(on)
• High Vfs/Clss Ratio (High-Frequency Figure-ot-Merit)

(TA = 25·C unless otherwise noted)
Drain-Gate Voltage ............................. - 25V
Drain-Source Voltage ........................... - 25V
Continuous Forward Gate Current .............. -10mA
Storage Temperature Range .......... - 65·C to + 200·C
Operating Temperature Range ........ - 55·C to + 175·C
Lead Temperature (Soldering, 10sec) ........... + 300·C
Power Dissipation ............................. 300mW
Derate above 25·C ....................... 2.0mWrC

CD
CD
...

PIN CONFIGURATION
TO·72

w

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device st these or sny other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING INFORMATION
0209-1

TO-72

5508

2N3993

APPLICATIONS

2N3994

Used in high-speed commutator and chopper applications. Also ideal for "Virtual Gnd" switching; needs no ext.
translator circuit to switch ±10 VAC. Can be driven direct
from TTL or CMOS logic.

ELECTRICAL CHARACTERISTICS
Symbol

(TA = 25·C unless otherwise specified)
Test Conditions
(Note 3)

Parameter

BVGSS

Gate-Source Breakdown Voltage

IG=1,.A,

VOs=O

lOGO

Drain Reverse Current

VOG=-15V,

Is=O

Voo=-15V,

Is =0,A=150'

loss

Zero-Gate-Voltage Drain Current

Vos=-10V,

VGS=O, (See Note 1)

101off)

Drain Cutoff Current

VOS= -10V,

VGs=6V

VOS= -10V,

VGs=6V, TA=150'C

VOs= -10V,

VGS=10V

Vos=-10V,

VGS=10V, TA=150'C

VGSloff)

Gate-Source Voltage

VOS= -10V,

10=-I,.A

rdslon)

Small-Signal Drain-Source
On·State Resistance

VGS=O,
f=1kHz

10=0,

IYtsl

Small-Signal Common-Source
Forward Transfer Admittance

VOs= -10V,
f=1kHz,

VGS=O,
(See Note 1)

Ciss

Common-Source Short-Circuit
Input CapaCitance (Note 3)

Vos=-10V,
f=1MHz,

VGS=O,
(See Note 2)

Crss

Common-Source Short·Circuit

VOs=O,
f=1MHz

VGs=6V,

Reverse Transfer CapaCitance
(Note 3)

VOs=O,
f=1MHz

VGs=10V,

2N3993
Min

Max

25

2N3994
Min
25

-1.2

4

-1.2
-2

nA
,.A
mA

-1.2

nA

-1

,.A

-1.2

nA

-1

,.A

9.5

1

150
6

V
-1.2

-1.2
-10

Units

Max

12
16

4.5

4

5.5

V

300

n

10

I£S

16

pF

5

pF
pF

NOTES: 1. These parameters must be measured using pulse techniques,lp= lOOms, duty cycle'; 10%.
2. This parameter must be measured with bias voltage applied for less than 5 seconds to avoid overheating.
3. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bssn characterized but are not tested.

10-15

III

I

2N4044, 2N4045, 2N4100,
I 2N4878, 2N4879, 2N4880
; Dielectrically Isolated Monolithic
:0 Dual NPN General Purpose
Amplifier

I

tJi FEATURES

ABSOLUTE MAXIMUM RATINGS

...
z

(TA = 25'C unless otherwise noted)
Coliector·Base or Coliector·Emitter Voltage (Note 1)
2N4044, 2N4878 ............................... 60V
2N4100,2N4879 ...•........................... 55V
2N4045, 2N4880 ............................... 45V
Collector-Collector Voltage ....................... 100V
Emitter Base Voltage (Note 2) ....................... 7V
Collector Current (Note 1) ....................... 10mA
Storage Temperature Range .......... -65'C to + 175'C
Operating Temperature Range ........ -55'C to + 175'C
Lead Temperature (Soldering, 10sec) ........... + 300'C

too • High Gain at Low Current

(0

cot

oo
...

.

•
•
•
•

Low Output Capacitance
Good hFE Match
Tight VBE Tracking
Dielectrically Isolated Matched Pairs for Differential
Amplifiers

= PIN CONFIGURATION

iii'
o

...
...z

TO·71
TO·78

TO-71

cot

..;

...o
...
z

Power Dissipation
Derate above 25'C
(mWI'C)

TO-78

One
Both
One
Both
Side
Sides
Side
Sides
200mW 400mW 250mW 500mW
1.3

2.7

1.7

3.3

NOTE: Stresses above those listed under ''Absolute Maximum Ratings"
may cause permanent damage to the devica. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied Exposure to absolute maximum rating conditions tor extended periods may affect device reliability.

cot

0210-1

4000

ORDERING INFORMATION
TO-78

TO-71

2N4044

2N4878

2N4045

2N4879

2N4100

2N4880

ELECTRICAL CHARACTERISTICS
Symbol

hFE

Parameter
DC Current Gain

(TA = 25'C unless otherwise specified)
Test Conditions

2N4044
2N4878

2N4100
2N4879

Min

Max

Min

Max

Ic=10",A, VCE=5V

200

600

150

600

Ic=1.0mA, VCE=5V

225

Ic=10",A, VCE=5V

I TA= -55'C

VSE(on)

Emitter-Base On Voltage

VCE(sat)

Collector Saturation Voltage

Ic=1.0mA,ls=0.1mA

Icso

Collector Cutoff Current

IE=O, Vcs=45V, 30V

I TA=150'C

Min

Max

80

800

Units

100

175
50

75

2N4045
2N4880

30

0.7

0.7

0.7

0.35

0.35

0.35

V

0.1

0.1

0.1

nA

0.1

0.1

0.1

",A

lEBO

Emitter Cutoff Current

Ic=O, VES=5V

0.1

0.1

0.1

nA

Cobo

Output Capacitance (Note 4)

IE=O, VCS=5V, f=1MHz

0.8

0.8

0.8

pF

INTERSIL'S SOLE ANO EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical vslues hsV6 be6n ohartIcteriz9d but srs not tested.

10-16

II1n~nll

2N4044,2N4045,2N4100,2N4878,
2N4879,2N4880
ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Test Conditions

Ic=O, VEB=0.5V, f= 1MHz

Collector to Collector
Capacitance (Note 4)

VCC=O, 1= 1MHz

IC1' C2

Collector to Collector
Leakage Current

VCC= ±100V

VCEO(sust)

Collector to Emitter
Sustaining Voltage

Ic= 1mA, IB=O

ft

Current Gain Bandwidth
Product (Note 4)

Ic= 1mA, VCE=10V

Current Gain Bandwidth
Product (Note 4)

Ic= 1O""A, VCE= 10V

Narrow Band Noise Figure
(Note 4)

Ic=10""A, VCE=5V
RG = 10kn

BVCBO

Collector Base Breakdown
Voltage

Ic=10""A,IE=0

BVEBO

Emitter Base Breakdown
Voltage (Note 2)

IE= 10""A, Ic=O

ft
NF

MATCHING CHARACTERISTICS

2N4044
2N4878

Min

Max

....Z
o
....

.!"
N

1

pF

0.8

0.8

0.8

pF

5

5

5

pA

N
Z

...CD

Z

........
o

P

....

60

55

45

V

~

200

150

150

MHz

....

15

15

N

Z

...

MHz

l'

dB

Z
....
CD

o

N

2

BW = 200Hz

3

3

60

55

45

V

7

7

7

V

(TA = 25'C unless otherwise specified)

I VBE1 - vBE21

Base Emitter Voltage
Differential

IC= 10""A, VCE=5V

IIS1 -ls21

Base Current
Differential

Ic= 10""A, VCE=5V

I to(IS 1 -ls 2) I I toT

Max

Units

1

I f=1kHz

Ic= 10""A to 1mA,
VCE=5V

Base Emitter
Voltage Differential
Change with
Temperature

Min

2N4045
2N4880

1

20

DC Current Gain Ratio
(Note 3)

II toT

Max

2N4100
2N4879

CD

hFE1/hFE2

I to(VBE1 - VSE2)

~
N

Emitter Transition
Capacitance (Note 4)

CC1,C2

....o

(Continued) (TA = 25'C unless otherwise specified)

Min
Cte

=
....

Ic= 10""A,
VCE=5V
TA= -55'Cto +125'C

Base Current
Differential
Change with
Temperature

0.9

1

0.85

1

0.8

1

3

5

5

mV

5

10

25

nA

3

5

10

""VI'C

0.3

0.5

1

nAI'C

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBlIGAT!ON WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.
NOTE All typical values have been characterized but are not tested.

10-17

CD

o

"It

2N4044,2N4045,2N4100,2N4878,
2N4879,2N4880

(\I

SMALL SIGNAL CHARACTERISTICS

CD
CD

Z

ti
....
CD

"It

Z

Symbol

IIlD~DIl.

(TA = 25°C unless otherwise specified)

Parameter

Test Conditions

Typical
Value

Units

(\I

hlb

Input Resistance

28

!l

ti
....

hrb

Voltage Feedback Ratio

43

x 10-3

CD

hie

Small Signal Current Gain

250

Z

hob

Output Conductance

oo

hie

Input Resistance

"It
(\I

.,..
"It

Z

(\I

.,;
"It

o

Ic= 1mA, Vce=5V (Note 4)

Ic= 1mA, VCE=5V (Note 4)

60

",S

9.6

k!l

hre

Voltage Feedback Ratio

42

x10- 3

hoe

Output Conductance

12

",S

NOTES: 1.
2.
3.
4.

•

Per transistor.
The reverse baseMemitter voltage must never exceed 7.0 volts and the reverse base-emitter current must never exceed 10 v.A .
The lowest 01 two hFE readings is taken as hFEl lor purposes 01 this ratio.
For design reference only, not 100% tested.

"It

Z

(\I

.;
"It

o

"It

Z

(\I

lNTEASll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE' All typiCal values have been characterized but are not tested.

10-18

D~DlLio

2N4091- 2N4093 JAN,
JANTX*, JTXV
ITE4091-ITE4093

..

I&)

I

~

Z

N -Channel JFET Switch

~

o
w

I&)

FEATURES

ABSOLUTE MAXIMUM RATINGS

• Low rOS(on)
• IO(OFF) < 100pA (JAN TX Types)
• Fast Switching

(TA = 25'C unless otherwise noted)
Gate·Source or Gate-Drain Voltage. , . ,. , , ........ -40V
Gate Current ................................... 10mA
Storage Temperature Range .......... -65'C to + 200'C
Operating Temperature Range ........ - 55'C to + 200'C
Lead Temperature (Soldering, 10sec) ........... + 300'C

PIN CONFIGURATIONS
(2N4091-93)

(ITE 4091-93)

TO·92

TO·1S

TO-18
1.BW
10mWI'C

Power Dissipation ..
Derate above 25'C

TO-92
360mW
3.3mWI'C

Plastic
Storage .......................... -55'Cto
Operating ........................ - 55'C to

G,C

o

S

S

0

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only

..

+ 135'C

t

TO-18t

ITE4092

2N4092

ITE4093

2N4093

Symbol

Parameter

(TA = 25'C unless otherwise specified)

Test Conditions

2N/ITE
4091
Min

BVGSS

Gate-Source Breakdown Voltage

lOGO

Drain Reverse Current
(Not JANTX Specified)

VOG=20V,ls=0

Gate Reverse Current

VGS= -20V, VOs=O

IGSS

(JANTX, ITE devices only)

IG= -lILA, VOs=O

I TA=150'C
I TA= 150'C

Max

2N/ITE
4092
Min

Max

Min

Units

Max

-40

-40

-40

2N/ITE
4093

V
200

pA

200

200

400

400

400

nA

-100

-100

-100

pA

-200

-200

-200

nA

INTERSIL'S SCLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valU6s have been characterized but 8f8 not tesf9d.

I

ii
~

o

w

add JANTX to these part numbers if JANTX processing is desired.

ELECTRICAL CHARACTERISTICS

~

o

I&)

I&)

ORDERING INFORMATION
2N4091

.*

_

5001

TO-92

~

::::

iii

0211-1

ITE 4091

;

+ 150'C

and functional operation of the device at these or any other conditions
above those indicated in the operationsl sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended peri·
ods may affect device ",liability.

G

,.;

10-19

CO)

GI

o

...
III

to-

2N4091-2N4093 JAN, JANTX*, JTXV,
ITE4091-ITE4093

...
o
...
III

ELECTRICAL CHARACTERISTICS

>.,~

IO(OFF)

"j

(Continued) (TA = 25'C unless otherwise specified)

GI

Symbol

Parameter

2N/ITE
4091

Test Conditions

.,

Drain Cutoff Current JANTX
JAN, JTXV
JANTX

E
.,
Z

2N/ITE
4093

Units

Min Max Min Max Min Max

!:

II(

2N/ITE
4092

Vos=20V VGS= -12V(4091) TA=25'C
VGS= -8V(4092)
VGS= -6V(4093)
TA=150'C

JAN,JTXV

100

100

100

200

200

200

200

200

200

400

400

400

nA

-7

-5

V

Vp

Gate-Source Pinch-Off Voltage

Vos=20V,10=lnA

-5 -10 -2

loss

Drain Current at Zero Gate
Voltage

Vos=20V, VGS=O,
Pulse Test Duraton = 2ms

30

15

-1
8

pA

mA

II(

VDS(ON) Drain-Source ON Voltage

VGS=O

CO)

...

...
...o
z
~

0.2

10 = 6.6mA

V

0.2

rOS(on)

Static Drain-Source
ON Resistance

VGs=0,10=1mA

rds(on)

Static Drain Source
ON Resistance

VGS=O, 10=0, f=lkHz

C;ss

Common-Source Input
Capacitance

Vos=20V, VGS=O, f=IMHz

I

GI

0.2

lo=4mA

GI

o

z~

10=2.5mA

30

50

80

30

50

80

16

16

16

JANTXOnly

(Note 1)

5

5

5

Common-Source
Reverse Transfer Capacitance

VOs=O, VGS= -20V, f=IMHz
(Note 1)

5

5

5

td(ON)

Turn-ON Delay Time (Note 1)

VDo=3V, VGO(ON)=O

20

tr

Rise Time (Note 1)

toff

Turn-OFF Time (Note 1)

Crss

4091
4092
4093

10(on)

VGS(off)

6.6mA
4mA
2.5mA

-12V
-8V
-6V

15

15

R1

10

20

40

4250.
7000.
11200.

40

60

80

0.

pF

ns

NOTE 1. For design reference only, not 100% tested.

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

10-20

D~DIb~.

2N4117-2N4119,
2N4117A-2N4119A

...
...Z

N-Channel JFET
General Purpose Amplifier

I

I\)

!J

FEATURES

ABSOLUTE MAXIMUM RATINGS

• Low Leakage
• Low Capacitance

(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage ___ .. _......... -40V
Gate Current . _. _..... _.... _.... _....... _....... 50mA
Storage Temperature Range .......... - 65°C to + 200°C
Operating Temperature Range ...... _. -55°C to + 175°C
Lead Temperature (Soldering, 10sec) ..... _..... +300°C
Power Dissipation ............................. 300mW
Derate above 25°C ........... _.......... _ 2.0mW

PIN CONFIGURATION
TO-72

rc

TO-72
0212-1

2N4117

5007

2N4117A
2N4118
2N4118A
2N4119
2N4119A
(TA = 25°C unless otherwise specified)
Test Conditions

2N4117
2N4117A
Min

BVGSS

Gate-Source Breakdown Voltage
Gate Reverse Current

I

Adevices

IG= -lI-'A, VDS=O

Max

-40

VGs= -20V. VDS=O

I TA=+150·C

I A devices

2N4118
2N4118A
Min

Max

2N4119
2N4119A
Min
-40

-40

Units

Max
V

-10

-10

-10

-1

-1

-1

-25

-25

-25

-2.5

-2.5

-2.5

pA

nA

VGS(off)

Gate-Source Pinch-Off Voltage

VDS=10V,ID=lnA

-0.6

-1.8

-1

-3

-2

-6

V

IDSS

Drain Current at Zero Gate
Voltage (Note 1)

VDS=10V
VGS=O

0.02

0.09

0.08

0.24

0.20

0.60

rnA

gts

Common-Source Forward
Transconductance (Note 1)

VDS=10V
f=lkHz

70

210

80

250

100

330

gts

Common-Source Forward
Transconductance (Note 2)

VGs=O, f=30MHz

60

gos

Common-Source Output
Conductance

VDS=10V, VGs=O,
f=lkHz

3

5

10

CiSS

Common-Source Input
Capacitance (Note 2)

VDs=10V, VGS=O,
f=lMHz

3

3

3

erss

Common-Source Reverse
Transfer Capacitance (Note 2)

VDS=10V, VGs=O,
f=lMHz

1.5

1.5

1.5

70

90

I-'s

pF

NOTES: 1. Pulse test: Pulse duration of 2ms used during test.
2. For design reference only, not 100% tested,

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been characterized but are not tested

10-21

...

...

D

IGSS

I

Z

...

ORDERING INFORMATION

Parameter

:..0

I\)

NOTE: Stresses above those listed under "Abso/ute Maximum Ratings"
above those indicated in the operational sections 01 the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Symbol

I\)

Z

may cause permanent damage to the device. These are stress ratings only

and functional operation of the device at these or any other conditions

ELECTRICAL CHARACTERISTICS

..
........
G

II-

D~D[b

2N4220-2N4222
.. General
N-Channel JFET
Purpose AmplifierISwitch
(II
(II
(II

z(II
I

o

(II
(II

FEATURES

ABSOLUTE MAXIMUM RATINGS

:

• Crss <2pF

(II

•

(TA = 25'C unless otherwise noted)
Gate-Source or Gate-Drain Voltage ............•.. - 30V
Gate Current •..•................•....•.•.•....• 10mA
Storage Temperature Range ....•.•.•. -65'C to + 200'C
Operating Temperature Range ......•. -55'C to + 175'C
Lead Temperature (Soldering, 10sec) ...•...•... +300'C
Power Dissipation •................•........... 300mW
Derate above 25'C ....•....•..•.•......•. 2.0mW

Moderately High Forward Transconductance

PIN CONFIGURATION
TO-72

rc

NOTE: Stresses above those listed under ''Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING INFORMATION
0213-1

5010

TO-72
2N4220
2N4221
2N4222

ELECTRICAL CHARACTERISTICS
Symbol

(TA = 25'C unless otherwise specified)
2N4220

Test Conditions

Parameter

Min
Gate Reverse Current

IGSS

VGS- -15V, VOS-O
TA=150'C

BVGSS

Gate-Source Breakdown Voltage

IG= -lO,.A, VOs=O

VGS(off)

Gate·Source Cutoff Voltage

VDS= 15V,ID=0.1nA

VGS

Gate-Source Voltage

VOS= 15V

loss

Saturation Drain Current (Note 1)
Common-Source Forward
Transconductance (Note 1)

1=1kHz

Iyls I

Common-Source Forward
Transadmittance (Note 2)

1=100MHz

gas

Common-Source Output
Conductance (Note 1)

1=1kHz

CiSS

Common-Source Input
Capacitance (Note 2)

Vos= 15V, VGS=O

Vos=15V, VGS=O
1=1MHz

Max

2N4222
Min

Units

Max

-0.1

-0.1

nA

-0.1

-0.1

-0.1

,.A

-30

-30

-6

-4

IID=50,.A (2N4220)
lo=200,.A (2N4221)
10 = 500,.A (2N4222)

Common-Source Reverse
Transler Capacitance (Note 2)

2N4221
Min

-0.1
-30

gf.

Crss

Max

V

-8

-0.5

-2.5

-1

-5

-2

-6

V

0.5

3

2

6

5

15

rnA

1000

4000

2000

5000

2500

6000

750

750

,.S

750

10

20

40

6

6

6

2

2

2

pF

NOTES: 1. Pulse test duration 2ms.
2. For design reference only. not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typics.1 values have been characterized but are not tested.

10-22

n~DIL!

2N4223,2N4224

N-Channel JFET
High Frequency Amplifier

N
N

~

.
N

Z

FEATURES

ABSOLUTE MAXIMUM RATINGS

• NF=3dB Typical at 200MHz

(TA= 25·C unless otherwise noted)
Gate-Source or Gate-Drain Voltage ............... -30V
Gate Current ................................... 10mA
Storage Temperature Range .......... - 65·C to + 200·C
Operating Temperature Range ........ -55·C to + 175·C
Lead Temperature (Soldering, 10sec) ........... +300·C
Power Dissipation ............................. 300mW
Derate above 25·C ....................... 2.0mWrC

• Crss <2pF

PIN CONFIGURATION
To-72

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may caUS6 permanent damage to the davice. These are stress ratings only
and functionel operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum reting conditions for extended periods may affect device reliability.

ORDERING INFORMATION
0214-1

5000

TO-72
2N4223
2N4224

ELECTRICAL CHARACTERISTICS
Symbol

(TA = 25·C unless otherwise specified)

Parameter

2N4223

Test Conditions

Min
IGSS

Gate Reverse Current

VGs= -20V, VOs=O
TA=+150"C

BVGSS

Gate.source Breakdown Voltage

VGS(otn

Gate·Source Cutoff Voltage

VGS

Gate.source Voltage

loss

Saturation Drain Current (Note 1)

Vos=15V, VGs=O

gt.

Common·Source Forward
Transconductance (Note 1)

Vos=15V, VGS=O

Ciss

Common·Source Input
Capacitance (Output Shorted)

VOS=15V, VGS=O

Crss

Common-Source Reverse
Transfer Capacitance

(Note 2)

IYtsl

Common-Source Forward
Transadmittance

9iss

Common-Source Input
Conductance (Output Shorted)

gos.

Common·Source Output
Conductance (Input Shorted)

Gps

Small Signal Power Gain

NF

Noise Figure (Note 2)

10 = 0.25nA (2N4223)
10 = 0.5nA (2N4224)
10 = 0.3mA (2N4223)
10 = 0.2mA (2N4224)

f=lkHz

-0.1

2N4224
Min

-0.5

nA

-0.25

-0.5

p.A

-30
-8

-0.1

-8
V

-1.0

-7.0

-1.0

3

18

2

-7.5
20

rnA

3000

7000

2000

7500

",s

6

6

2

2

pF

f=IMHz

2700

Vos=15V, VGS=O
(Note 2)

Units

Max

-0.25

-30

IG= -10",A, Vos=O

Vos=15V

Max

f=200MHz

1700
800

800

200

200

",S

10
Vos=15V, VGS=O,
Rgen=lkO

5

dB

NOTES: 1. Pulse test. duration 2ms.
2. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typical values havs been characterJzsd but arB not I6st6d.

10-23

N

N
..

...... 2N4338-2N4341
...
z N-Channel JFET

D~DlL

C")

(\I

I

CIO

C")
C")

:
(\I

Low Noise Amplifier

FEATURES

ABSOLUTE MAXIMUM RATINGS

• Exceptionally High Figure of Merit
• Radiation Immunity
• Extremely Low Noise and Capacitance
• High Input Impedance

(TA= 25'C unless otherwise noted)
Gate-Source or Gate-Drain Voltage .............•. -50V
Gate Current ................................... 50mA
Storage Temperature Range .......... - 65'C to + 200'C
Operating Temperature Range ........ - 55'C to + 175'C
Lead Temperature (Soldering, 1Osee) ........... + 300'C
Power Dissipation ............................. 300mW
Derate above 25'C ....................... 2.0mW/,C

APPLICATIONS
• Low-level Choppers
• Data Switches
• Multiplexers and Low Noise Amplifiers

NOTE: Stresses above those listed under ''Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the speCifications is not
implied. Exposure to absolute maximum rating conditions for extended peri.
ods may affect device reliability.

PIN CONFIGURATION
TO·IS

ORDERING INFORMATION
TO-18
2N4338

.m
o

5040

2N4339
2N4340
2N4341
0215-1

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25'C unless otherwise specified)

Test Conditions

2N4338

Min
Gate Reverse Current

IGSS

VGs= -30V, VDS=O

ITA=150'C
BVGSS

Gate-Source Breakdown Voltage

IG= -1/LA, VDS=O

-50

VGS(Off)

Gate·Source Cutoff Voltage

VDS=15V,ID=0.1/LA

-0.3

ID(off)

Drain Cutoff Current

VDS= 15V,

IDSS

Saturation Drain Current (N~te 2)
Common-Source Forward
Transconductance (Note 2)

gos

Common-Source Output
Conductance

rDS(on)

Drain·Source ON Resistance

Ciss

Common-Source Input
Capacitance

Crss

Common·Source Reverse
Transfer Capacitance

NF

Noise Figure (Note 1)

VDS=15V, VGS=O

VDS= 15V, VGS=O

2N4339

Min

Max

2N4340

Min

Max

2N4341

Min

-·0.1

-0.1

-0.1

nA

-0.1

-0.1

-0.1

-0.1

pA

-50
-1

-0.6

-50
-1.8

-1

0.05
(-5)

0.2

0.6

0.5

1.5

600

1800

800

2400

-50
-3

-2

0.05
(-5)
1.2

3.6

1300 3000

V

-6
0.07
(-10)

nA
(V)

3

9

mA

2000

4000

f=1kHz

VDS=O, IDS =0

VDS=15V, VGS=O
(Note 1)

f=1MHz

VDS= 15V, VGS=O
Rgen =1meg,
BW = 200Hz

f=1kHz

Units

Max

-0.1

0.05
(-5)

VGS=()

gfs

Max

/Ls
5

15

30

60

2500

1700

1500

800

7

7

7

7

3

3

3

3

1

1

1

1

ohm

pF

dB

NOTE 1: For design reference only, not 100% tested.
2: Pulse test duration 2 ms (non·JEDEC Condition).

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

10-24

2N4351

N-Channel Enhancement Mode
MOSFET General Purpose
AmplifierISwitch
FEATURES

ABSOLUTE MAXIMUM RATINGS

•
•
•
•
•

(TA= 25'C unless otherwise noted)
Drain-Source Voltage or Drain-Body Voltage .•..•..•. 25V
Peak Gate-Source Voltage (Note 1) .......... . . •. ± 125V
Drain Current ....•....•....................... 100mA
Storage Temperature Range •......... -65'C to + 200'C
Operating Temperature Range ........ -55'C to + 150'C
Lead Temperature (Soldering, 10sec) ........... +300'C
Power Dissipation ............................. 375mW
Derate above 25'C ......................... 3mW I'C

Low ON Resistance
Low Capacitance
High Gain
High Gate Breakdown Voltage
Low Threshold Voltage

PIN CONFIGURATION

NOTE: StressBS above thoss listed under "Absolute Maximum Ratings"
may CBUS6 permsnent dsmage to the dsvics. Thsse are stress ratings only
and functional operstlon of the dsvics at thSSB or any oth9r conditions
above thoss indiested in th9 op9rational ssetlons of the specifications is not
implied. Exposure to absoiulB maximum rating conditions tor sxtsnded periods may affsct dsvics rallability.

T()'72

ORDERING INFORMATION

D

G

S

0216-1

1003

ELECTRICAL CHARACTERISTICS
Symbol

(TA = 25'C unless otherwise specified) Substrate connected to source.
Min

Test Conditions

Parameter

Max

Units
V

25

BVOSS

Drain-Source Breakdown Voltage

lo=10""A, VGS=O

IGSS

Gate Leakage Current

VGS= ±30V, VOs=O

10

pA

loSS

Zero-Gate-Voltage Drain Current

Vos=10V, VGS=O

10

nA

VGS(th)

Gate-Source Threshold Voltage

Vos=10V,lo=10""A

1

10(on)

'ON' Drain Current

VGs=10V, Vos=10V

3

VOS(on)

Drain-Source "ON" Voltage

10=2mA, VGs=10V

rOS(on)

Drain-Source Resistance

VGS= 10V,10=O, f= 1kHz

IYlsl

Forward Transfer Admittance

VOs= 10V, lo=2mA, f= 1kHz

Crss

Reverse Transfer CapaCitance
(Note 2)

VOs=O, VGS=O, f= 1MHz

Ciss

Input CapaCitance (Note 2)

VOS=10V, VGS=O, f=1MHz

5.0

Cd(sub)

Drain-Substrate CapaCitance (Note 2)

VO(SUB)= 10V, f= 1MHz

5.0

Id(on)

Turn-On Delay (Note 2)

t,-

Rise Time (Note 2)

fih
to

Id(off)
tl

Fall Time (Note 2)

V

300

ohms
""s

-

pF

45
65

DUTfC'fOLI1

..TVOI-WI

...

..

1

1.3

1021_

Turn-Off Delay (Note 2)

y..,.

V
mA

1000

Switching Times Test Circuit
y,~

5

..

'~
III

....

,

I0Il

v

MI'!

;~t.1

-

ns
60
100

NOTES: 1. Oevlce must not be tested at ± 125V more than once or longer than 300ms.
2. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typical values hBvs bHn characterlz6d but SI8 not tested.

10-25

III

= 2N4391-2N4393,

: ITE4391-ITE4393

..~ N-Channel JFET Switch

Gt
~ FEATURES
III e rds(on)<300 Ohms (2N439l)

t:
c?
Gt
CO)
~

Z

..

ABSOLUTE MAXIMUM RATINGS
(TA = 25·C unless otherwise noted)
Gate-Source or Gate-Drain Voltage ............... -40V
Gate Current ................................... 10mA
Storage Temperature Range .. . . . . . . .. - 65·C to + 200·C
Operating Temperature Range ........ - 55·C to + 200·C
Lead Temperature (Soldering, 1Osee) ........... + 300·C

eI O(OFF)<100pA

e Switches ± 10VAC With ± l5V Supplies (2N4392,
2N4393)

PIN CONFIGURATION

Power Dissipation ..
Derate above 25·C

TO-18
1.8W
10mwrc

Plastic
Storage
Operating ....... .

- 55·C to
- 55·C to

(\I

I

TO-18
TO-92
(2N439l-93) (ITE439l-93)

Gt

CO)
~

Z

(\I

TO-92
360mW
3.3mwrc

+ 150·C
+ 135·C

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only

and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended peri-

G,C

o

s

S

0

ods may affect device reliability.

G
0217-1

5001

ORDERING INFORMATION*
TO-92

TO-18

ITE4391

2N4391

ITE4392

2N4392

ITE4393

2N4393

ELECTRICAL CHARACTERISTICS

(TA = 25·C unless otherwise specified)

Symbol

Test Conditions

Parameter

4391
Min

IGSS

Gate Reverse Current

VGS= -20V, VDS=O
I TA= 150·C

BVGSS

Gate-Source Breakdown Voltage IG= -1/LA, VDS=O

10(011)

Drain Cutoff Current

Min

Max

Min

Units

Max

-100

-100

-100

pA

-200

-200

-200

nA

-40

VDS=20V VGS= -5V (4393)
VGS= -7V (4392)
VGS= -12V (4391)

4393

4392

Max

-40

-40

V

100

100

100

pA

200

200

200

nA

1

1

1

ITA=150·C
VGS(I)

Gate-Source Forward Voltage

VDS=20V,ID=1nA

-4

-10

-2

-5

-0.5

-3

Saturation Drain Current (Note 1) VDS=20V, VGS=O

50

150

25

75

5

30

VGS(oll) Gate-Source Cutoff Voltage
loss

IG= 1mA, VDS=O

V
mA

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION W1TH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

10-26

2N4391-2N4393, ITE4391-ITE4393
ELECTRICAL CHARACTERISTICS
Symbol

(Continued) (TA = 25'C unless otherwise specified)

Parameter

4391

Test Conditions

4392

4393

Units

Min Max Min Max Min Max
VOS(on)

Drain-Source ON Voltage

VGS=O 10 = 3mA (4393)
10=6mA (4392)
10= 12mA (4391)

rOS(on)

Static Drain-Source ON Resistance

VGs=O,10=1mA

rds(on)

Drain-Source ON Resistance

VGs=O,lo=O

C;ss

Common-Source Input Capacitance
(Note 2)

Vos=20V, VGS=O

Cras

Common-Source Reverse Transfer
Capacitance (Note 2)

VOs=O VGs=-5V

~

Turn-ON Delay Time (Note 2)

Voo=10V, VGS(on)=O

tr

Rise Time (Note 2)

toft

Turn-OFF Delay Time (Note 2)

tf

Fall Time (Note 2)

f=1kHz

VGs=-7V

0.4

0.4

V

.n

30

60

100

30

60

100

14

14

14
3.5

f=1MHz

pF

3.5

VGs=-12V

4391
4392
4393

0.4

3.5
15

15

15

10(on)

VGS(oft)

5

5

5

12mA
6
3

-12V
-7
-5

20

35

50

15

20

30

ns

NOTES: 1. Pulss lesl required, pulse widlh= 300,.s, duty cycle<:3%.
2. For design reference only, not 100% lealed.

Swltchlnll Times Test Circuit

DJ.

PULSE
IN

Yoo

lKO

1 1000PF

sco~~O--

YOUT

510
510

~

510

RL

RL =

(~)-51D
o(ON)

~

~

0217-3

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY A~TICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USIE.

NOTE: AN typ/CaI_ have boon charIIc/wIzsd but.,. not,..1ed.

10-27

•

U~UIL

; 2N4416/A, ITE4416
'II'

~

~
CD
;

N-Channel JFET
High Frequency Amplifier
FEATURES

ABSOLUTE MAXIMUM RATINGS

• Low Noise
Low Feedback Capacitance
• Low Output Capacitance
• High Transconductance
• High Power Gain

(TA = 25'C unless otherwise noted)
Gate-Source or Gate-Drain Voltage
2N4416, ITE4416 ........................ _• " - 30V
2N4416A .................................... -35V
Gate Current ................................... 10mA
Storage Temperature Range
2N4416/2N4416A ........... _..... -65'Cto +200'C
ITE4416 ............................ - 55'C + 150'C
Operating Temperature Range
2N4416/2N4416A ................. - 65'C to + 200'C
ITE4416 .......................... -55'Cto + 135'C
Lead Temperature (Soldering, 10sec) ........... + 300'C
Power Dissipation ............................. 300mW
Derate above 25'C ................................ .
2N4416/2N4416A ........................ 1.7mWrC
ITE4416 ................................. 2.7mWrC

;I; •
ell

PIN CONFIGURATIONS
(2N4416!A)

(ITE4416)

TO-72

TO-92

S

D

NOTE: Stresses above those listed under ''Absolute Maximum Ratings"
may cause permanent damsge to the device. These are stress ratings only
and functional operation of the davice at these or any other conditions
above those indicated in the operational sections of the specifications is not
Implied. Exposure to absolute maximum rating conditions for extendad periods may affect device reliability.

G

5000

0218-1

ORDERING INFORMATION
TO-92

To-72

ITE4416

2N4416

-

2N4416A

ELECTRICAL CHARACTERISTICS
Symbol
IGSS

(TA = 25'C unless otherwise specified)

Parameter

Test Conditions

Gate Reverse Current

Min

VGS= -20V, VOs=O
TA=150'C

BVGSS

Gate-Source Breakdown Voltage

2N441611TE4416

Max

nA

-0.1

,.A

-30

IG= -1,.A, VOs=O

-35

2N4416A
VGS(off)

Gate-Source Cutoff Voltage

2N441611TE4416

VGS(f)

Gate-Source Forward Voltage

IG=lmA, VOs=O

loss

Drain Current at Zero Gate Voltage

Vos=15V, VGS=O

9rs
90.

Common-80urce Forward Transconductance

Units

-0.1

-6

VoS=15V,lo=lnA

2N4416A

f=lkHz

Common-Source Output Conductance
f=IMHz

V

-2.5

-6
1

V

5

15

mA

4500

7500

,.S

50

,.s

0.8

pF

0,..

Common-Source Reverse Transfer CapacHance
(Note 1)

Ciss

Common-Source Input Capacitance (Note 1)

4

Coss

Common-Source Output Capacitance (Note 1)

2

pF

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION wrrH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTV ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORV. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTASILrrv AND FITNESS FOR A PARTICULAR USE.

NOTE:AHtyp/CaI ..Iuu"'vsbBen_butllTOnoI _ _

10-28

2N4416/A, ITE4416
ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25'C unless otherwise specified) (Continued)

Test Conditions

100MHz
Min

Max

400MHz
Min

giss

Common-Source Input Conductance

100

1000

biss

Common-Source Input Susceptance

2500

10,000

goss

Common-Source Output
Conductance

75

100

VOS= 15V, VGS=O (Note 1)

boss

Common-Source Output
Susceptance

gls

Common-Source Forward
Transconductance

Gps

Common-Source Power Gain

VOS = 15V, 10 = 5mA (Note 1)

NF

Noise Figure (Note 1)

Vos=15V, 10=5mA, RG=1kO

Units

Max

",S
1000

4000
4000

18

10
2

dB
4

NOTE 1: For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values havs been characterized but are not tested

10-29

E2N4856-2N4861,

D~Dll

., JAN, JTX, JTXV
~ N-Channel JFET Switch
=- FEATURES

ABSOLUTE MAXIMUM RATINGS

~

(TA = 25'C unless otherwise noted)
Gate-Source or Gate-Drain Voltage
2N4856-58 ................................. -40V
2N4859-61 ................................. -30V
Gate Current ................................... 50mA
Storage Temperature Range .......... - 65'C to + 200'C
Operating Temperature Range ........ - 55'C to + 200'C
Led Temperature (Soldering, 1Osee) ............ + 300'C
Power Dissipation ............................... 1.8W
Derate above 25'C ........................ 10mWrC

(\I

NOTE: Stresses above those listed under "Absolute Maximum Ratings"

:
;;

CD
~

Z

(\I

I

• Low rOS(on)
• 10(Off) < 250pA
• Switches ± 10V Signals With
2N4861)

± 15V Supplies (2N4858,

PIN CONFIGURATION

CD

II)

TO-18

CD

Z

may cause permanent damage to the device. These 8re stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING INFORMATION
TO·18

D

0219-1

2N4856t

5001

2N4857t
2N4858t
2N4859
2N4860
2N4861
tadd JAN. JTX, JTXV, to basic part number to specify these devices.

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25'C unless otherwise specified)

Test Conditions

2N4858

2N4857

Min Max Min Max
12N4856-58 IG= -II£A, Vos=O
BVGSS Gate-Source
Breakdown Voltage12N4859_61
IGSS

IO(off)

Gate Reverse Current

Drain Cutoff Current

2N4858
Min

2N4859

2N4880

Max Min Max Min Max

2N4881
Min

-40

-40

-40

-40

-40

-40

-30

-30

-30

-30

-30

-30

Unltl

Max
V

VGS= -20V, VOs=O

-0.25

-0.25

-0.25

nA

VGS= -20V, VOs=O
TA=150'C

-0.5

-0.5

-0.5

I£A

VGS= -15V, VOs=O

-0.25

-0.25

-0.25 nA

VGS= -15V, VOs=O
TA=150'C

-0.5

-0.5

-0.5

nA

Vos=15V, VGS= -10V
ITA=150'C

~GS(Off)

Gate-Source Cutoff Voltage

VoS=15V, 10 = 0.5nA

Iloss

Saturation Drain Current
(Note 1)

Vos=15V, VGS=O

-4

250

250

250

250

250

250

pA

500

500

500

500

500

500

nA

-10

50

-2

-6

-0.8

-4

-4

20

100

8

80

50

-10

-2

-6

-0.8

-4

V

20

100

8

80

rnA

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical vsJues haV6 b8en charsct9rized but arB not testBci.

10-30

.D~OI!.. N
Z

2N4856-2N4861,JAN,JTX,JTXV
ELECTRICAL CHARACTERISTICS
Symbol

Parameter

...CD
en

(Continued) (TA = 2SoC unless otherwise specified)

GI
I

2N4856 2N4857 2N4858 2N4859 2N486D 2N4861

Test Conditions

Unlta
Min Max Min Max Min Max Min Max Min Max Min Max

VOS(on) Drain-Source ON Voltage

VGs=O,lo=()

rdslan)

Drain-Source ON Resislance

VGs=O,lo=O

f=lkHz

Ci..

Common-Source Inpul
Capacitance

VOs=O, VGS= -10V

f=IMHz

Cros

Common-Source Reverse
Transfer Capacitance

(Note 2)

~

Turn-ON Delay Time (Nota 2)

Ir

Rise Time (Nole 2)

Ioff

Turn-OFF Time (Note 2)

464ll (2N4856,59)
Voo= 10V, RL = 9530 (2N4857,60)
19100 (2N4858,61)
VGS(on)=0
VGS(oII) = -IDV,lo=2O mA (2N4856,9)
VGS(oII) = -6V,lo=10mA (2N4857,60)
VGS(oII) = -4V,lo=5mA (2N4858,61)

0.75
(20)

0.50
(10)

0.50
(5)

0.75
(20)

0.50
(10)

0.50 V
(5) (mA)

25

40

60

25

40

60

ohm

18

18

18

18

18

18

pF

8

8

8

8

8

8

6

6

10

6

6

10

3

4

10

3

4

10

25

50

100

25

50

100

N

...CD
Z

...
GI

w

ns

NOTES: 1. Pulse test required, pulse widlh = l00,..s, duty cycle,;; 10%.
2. For design reference only, not 100% tested.

VDD

INPUT PULSE

?
~ R _ VDo-VDS(ON)

iDlON)

L -

Rise TIme

Fall Time

0.75 ns

Input Resistance

lMO

lOOns

Input Capacitance

2.5pF

Pulse Duty Cycle

0---_-.. -..-.
RO
500

0.25n.

Pulse Width

~ .. ~VOuT

VIN

SAMPLING SCOPE

Rise Time

0.75 ns

< 100%

t-

0219-3

Figure 1: Switching Times Test Circuit

•
INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE Of THE CONDITION OF SALE.
THE WARRANlY SHALL BE EXCWSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical vsIusIJ have bsen chIIrsctsrizBd but IW not t98tsd.

10-31

D~DI1.

~ 2N4867/A-2N4869/A
: N-Channel JFET
I Low Noise Amplifier

""
I

~ •FEATURES
Low Noise Voltage

..

ABSOLUTE MAXIMUM RATINGS

,..

co

• Low Leakage

""

PIN CONFIGURATION

z~

(TA = 25·C unless otherwise noted)
Gate-Source or Gate-Drain Voltage ............... - 40V
Gate Current ..................................• 50mA
Storage Temperature Range •.•.•..•.• -65·C to + 200·C
Operating Temperature Range ........ -55·C to + 200·C
Lead Temperature (Soldering, 10sec) ........... + 300·C
Power Dissipation .....•...................•..• 300mW
Derate above 25·C ....................... 1.7mW'·C

• High Gain

TO-72

NOTE: Stresses above those lis/6d undsr "Absolute Maximum Ratings"
may cause perma.nent damage to the dsvice. These are stress ratings only
and functional operation of the dsvlce at these or any other candltions
above those ind/ca/6d in the operational sections of the specifications is not
Implied. Exposure to absolute maximum rating canditions tor extentisd peri.
ods may affBct dsvice reliability.

ORDERING INFORMATION
TO-72
2N4867

o

2N4867A

0220-1

5005

2N4868
2N4868A
2N4869
2N4869A

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25·C unless otherwise specified)
2N4867
2N4867A

Teat Conditions

Min
IGSS

Gate Reverse Current

VGS= -30V, Vos=O
TA=150·C

BVGSS

Gate-Source Breakdown Voltage

IG= -1,.A, Vos=O

-40

VGSCoff)

Gate-Source Cutoff Voltage

Vos = 20V, 10 = 1,.A

-0.7

loss

Saturation Drain Current (Note 1)

Vos=20V, VGS=O

9fs

Common-Source Forward
Transconductance (Note 1)

Vos=20V, VGS=O

gos

Common-50urce Output
Conductance

Cr.s

Common-Source Reverse
Transfer Capacitance (Note 2)

Cj ..

Common-Source Input
CapaCitance (Note 2)

en

Short Circuit Equivalent Input
Vos=10V,
Noise Voltage
VGS=O
(Nota 2)
A devices

f=lkHz

Spot Noise Figure (Note 2)

Min

Max

2N4869
2N4869A
Min

Units

Max

-0.25

-0.25

-0.25

nA

-0.25

-0.25

-0.25

,.A

-40
-2

-1

-40
-3

-1.8

V
-5

0.4

1.2

1

3

2.5

7.5

700

2000

1000

3000

1300

4000

mA

,.S
1.5

4

10

5

5

5

25

25

25

f=10Hz

20

20

20

f=lkHz

10

10

10

nV

f=10Hz

10

10

10

,1Hz

f=lkHz

5

5

5

f=lkHz

1

1

1

f=IMHz

pF

I

NF

Max

2N4868
2N4868A

VOS= 10V, VGS=O
Rgon = 20K, (2N4867 Series)
Rgon = 5K, (2N4867A Series)

dB

NOTES: 1. Pulse test duratlon=2ms.
2. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

10-32

D~DlLi.

2N5018, 2N5019
P-Channel JFET Switch
FEATURES

APPLICATIONS

• Low Insertion LOBS
• No Offset or Error Voltages Generated By Closed
Switch
• Purely Resistive

• Analog Switches
• Commutators

~
N

Z

CII

g

• Choppers

CD

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(TA = 25·C unless otherwise noted)
Gate-Drain or Gate-Source Vollage .•..•..•.•..•..•• 30V
Gate Current ................................... 50mA
Storage Temperature Range ..•..•...• - 65·C to + 200·C
Operating Temperature Range ........ -55·C to + 2000C
Lead Temperature (Soldering. 10sec) ........... +3000C
Power Dissipation ............................. 500mW
Derate above 25·C ......................... 3mWrC

T0-18

NOTE: Slr9ss9s above those 1/s1Bd under ''Absolute Maximum Ratings"
may cause ptJf'fTIIlnsnt dafTlllfJB to the dBvIc8. These am stress ratings only
and functionsl operation of the dBv1c8 at /hBse or any other conditions
above /hose indlcslBd in the operationsl sections of the specifications Is not
ImpllBd. ExpoSUf'B to absolute maximum rating conditions for sxterrdBd periods may affect dBv1c8 r9llabllity.

ORDERING INFORMATION*

G

0221-1

TO-18

5508

2N5018
2N5019

ELECTRICAL CHARACTERISTICS
Symbol

(TA = 25·C unless otherwise specified)

Parameter

2N5018

Test Conditions

Min
Gate-Source Breakdown
Voltage

IG=1/1oA. VOs=O

IGSS

Gate Reverse Current

VGs=15V. VOs=O

10(011)

Drain Cutoff Current

Vos= -15V'1 VGs= 12V (2N5018)
VGs=7V(2N5019) TA=150.C

lOGO

Drain Reverse Current

BVGSS

TA=150·C
Gate-Source Cutoff
Voltage

VOS= -15V.10= -1/1oA

Saturation Drain Current

VOS= -20V. VGS=O

Drain-Source
ON Voltage

VGs=O.lo= -6mA (2N5018).
10= -3mA (2N5019)

rds(on)

Static Drain-Source
ON Resistance

10= -1mA. VGS=O

rds(on)

Drain-Source
ON Resistance

10=0. VGS=O

f=1kHz

Ciss

Common-Source Input
Capacitance (Note 1)

VOS= -15V. VGS=O

f=1MHz

Crss

Common-Source Reserve
VOs=O. VGs=12V (2N5018).
Transfer Capacitance (Note 1) VGs=7V (2N5019)

Units

Max
V

2

2

-10

-10

-10

-10

/loA

-2

-2

nA

-3

-3

/loA

10

5

V

-10

loss
VOS(on)

2N5019
Min
30

30

VOG= -15V.ls=0

VGS(off)

Max

-5

nA

mA

-0.5

-0.5

75

150

75

150

45

45

10

10

V

n

pF

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FlTNESS FOR A PARTICULAR USE.

NOTE: All typIcsl vslues have bHn characterIzsd but SfB not testtld.

10-33

.., 2N5018, 2N5019
Ii
..
(I

o

ELECTRICAL CHARACTERISTICS

ri
o

Symbol

(Continued)(TA = 25'C unless otherwise specified)

Parameter

2N5018

Test Conditions

Min

10

Z

~

Id(on).

Turn-ON Delay Time (Note 1)

2N5019

Max
15

Voo= -6V, VGS(on) = 0

Min

Units

Max
15

Ir

Rise TIme (Note 1)

VGS(off)

10(on)

RL

20

75

Icttoff)

Turn-off Delay Time (Note 1)

2N5018

12V

-6mA

9100

15

25

If

Fall TIme (Note 1)

2N5019

7V

-3mA

1.8kO

50

100

ns

NOTE:S: 1. For design reference only, not 100% tested.

Voo

VDD
RL

UK

~T~
510

J.

Ro

':'

UK

510

INPUT PULSE
RISE TIME < 1ns
FALL TIME < 1ns
PULSE WIDTH 100ns
REPLETION RATE 1MHz

J-~

SAMPLING
SCOPE

SAMPLING SCOPE
RISE TIME 0.4ns
INPUT RESISTANCE 10MIl
INPUT CAPACITANCE 1.5pF

7.5K

510

0221-3

Figure 1: Switching Time Text Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTO: AU typicaIvsJuss "".. bson characImizod but S/9 not-.

10-34

D~D[bi......
,.,

2N5114-2N5116,
JAN,JTX,JTXV
P-Channel JFET Switch

I
I\)

Z

......

GENERAL DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

01

Ideal for inverting switching or "Virtual Gnd" switching
into inverting input of Op. Amp. No driver is required and
± 10VAC signals can be handled using only + SV logic (TTL
or CMOS).

(TA = 2S·C unless otherwise noted)

!IJ

Gate-Drain or Gate-Source Voltage ................. 30V
Gate Current ................................... SOmA ~z.
Storage Temperature Range .......... -6S·C to + 200·C _
Operating Temperature Range ........ - SS·C to + 200·C
Lead Temperature (Soldering, 10sec) ........... + 300·C ~
Power Dissipation ............................. SOOmW
Derate above 2S·C ......................... 3mWrC

FEATURES

1<

e Low ON Resistance
eI O(off)<500pA
e Switches directly from TTL Logic

NOTE: Stresses a/xJve those listed under '"Absolute Maximum Ratings"

~

may cause permanent damage to the device. These are stress ratings only

<><

and functional operation of the device at these O( any other conditions

PIN CONFIGURATION

above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended peri~
ods may affect device reliability,

ORDERING INFORMATION

TO-18

T018t
2NSl14
2NS11S
2NSl16
tadd JAN, JTX, JTXV to basic part number to spacify these devices.
D

G.t

0222-1

5508

SWITCHING CHARACTERISTICS
Symbol

~

(TA = 2S·C unless otherwise specified)

2N5114

2N5115

2N5116

JANTX
2N5114

JANTX
2N55115

JANTX
2N5116

Max

Max

Max

Max

Max

Max

Turn-ON Delay Time

6

10

12

6

10

2S

Parameter

tr

Rise Time (Note 2)

10

20

30

10

20

3S

toll

Turn-OFF Delay Time (Note 2)

6

8

10

6

8

20

tj

Fall Time (Note 2)

lS

30

SO

lS

30

60

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Test Conditions

2N5114
Max

30

BVGSS

Gate-Source Breakdown Voltage IG=l,...A, VOS=O

IGSS

Gate Reverse Current

VGS=20V, VOS=O

10(011)

Drain Cutoff Current

VOS= -lSV
VGS= 12V (2NS114)
VGs=7V (2NS11S)
VGS=SV (2NS116)

2N5115
Min

VOS= -lSV, 10= -1nA

S

Max

2N5116
Min

SOO

Units

Max

30

30
SOO

I TA=1S0·C

Gate-Source Pinch-Off Voltage

ns

(TA = 2S·C unless otherwise specified)

Min

Vp

Units

V
SOO

pA

1.0

1.0

1.0

,...A

-SOO

-SOO

-SOO

pA

-1.0

-1.0

-1.0

,...A

4

V

10

3

6

1

INTERS1L'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valU6S hsvs besn chsracterlzsd but SJ'8 not testBd.

10-3S

~

2N5114-2N5116, JAN, JTX, JTXV

- ELECTRICAL CHARACTERISTICS

~

Z
~

Symbol

Parameter
Drain Current at Zero Gate Voltage
(Note 1)

loss

II'»

VGSCI)

(\I

VOS(on) Drain-Source ON Voltage

Z

VGS=O
VOS= -18V(2N5114)
VOS= -15V(2N5115)
VOS= -15V (2N5116)

Forward Gate-Source Voltage

2N5115
Min

2N5116

Units

Max Min Max
-5 -25

-1

-1

-1.3

-0.8

-0.6

150

rOS(on)

Static Drain-Source ON Resistance

75

100

rds(on)

Small-Signal Drain-Source ON
VGS=O, 10=0, f=1kHz
Resistance
IJan TX only

75

100

150

75

100

175

Common-Source Input
Capacitance (Note 2)

25

25

25

25

25

27

7

7

pF
7

Ciss

VGS=O, 10= -1mA

VOS= -15 V, VGS=O, f=1mHz
IJan TXonly

Common-Source Reverse
Transfer Capacitance (Note 2)

Crss

mA

-1

IG= -1mA, VOs=O

I

(\I

Max

-30 -90 -15 -60

VGS=O
10= -15 mA (2N5114)
10= -7 mA (2N5115)
10= -3 mA (2N5116)

..........

II'»
Z

2N5114

Test Conditions

Min

,,;

......

(TA = 25°C unless otherwise specified) (Continued)

VOs=O
VGS= 12V (2N5114)
VGs=7V(2N5115)
VGs=5V (2N5116)
f=1mHz

V

0

NOTES: 1. Pulse test; duration ~ 2ms.
2. For design reference only. not 100% tested.
INPUT

Test Conditions
2N5114 2N5115 2N5116
-10V

Voo

-6V

v,.

-6V

~-f

20V

12V

8V

RL

4300

9100

2KO

RG

1000

2200

3900

-7mA

-3mA

-12V

VIN

-7V

<;>

~

t,

90%

10%

<'
<'

(>

~~=

_ 6V 10%

iO(ON) -15mA

9

90%

Vos(ON)

VGG

voo

VGG

0.1_F

"1

f-

510

OUTPUT
0222-3

SAMPLING SCOPE

-5V

RISE TIME 0.4

~

RG

V\r

<'(>
?

7.5K(>

~

1.2K
":"

~ SAMpLING

>

~

ns?

:~~~i ~~~~J~~~~JO'~~F

1.2K

RL

c>---<

>

SCOPE
510

510

>
<

"*"

"::"

0222-4

TYPICAL PERFORMANCE CHARACTERISTICS
'M

V vsrDSON

...L.

10.0

fA

•

&
7A
U
U
OJ

•
•
..,.•

~

Vos '" o.W
Vos'" 0

2.

10

..•
...7.'
.A

7.'
.....•
..

.

~

Yo. - 20V
Vos = 0
(pulHd)

2A

30

100

............,

300

1,000

0222-5

OJ

,

I

I
Vos = 20Y
VOs;o 0
(pulled)

2.'

,..

,

0.'
0.'

OJ

'.7
OJ

...
5.'

....•

,\

7

V vsgl.

10.0

.A

3.

....••
..•.••

Vp vs IDSS

10

toss(mAl

.

...0.'
'.7

10•

0222-6

'....

~

...

10,000

• ..,Yl

"AGO

,......
0222-7

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANlY SHALL eE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values haV6 been characterized but are not tested.

10-36

2N5117 - 2N5119
Dielectrically Isolated Dual PNP
General Purpose Amplifier
FEATURES

ABSOLUTE MAXIMUM RATINGS

•
•
•
•
•

(TA = 25°C unless otherwise noted)
Collector-Base or Collector-Emitter
Voltage (Note 1) .............................. -45V
Emitter-Base Voltage (Notes 1 and 2) .............. -7V
Collector-Collector Voltage ....................... 100V
Collector Current (Note 1) ....................... 1OmA
Storage Temperature Range .......... -65°C to + 200°C
Operating Temperature Range ........ - 55°C to + 175°C
Lead Temperature (Soldering, 10sec) ........... + 300°C

High Gain at Low Current
Low Output Capacitance
Good hFE Match
Tight VBE Tracking
Dielectrically Isolated Matched Pairs for Differential
Amplifiers

PIN CONFIGURATION

Power Dissipation ........
Derate above 25°C .....

ONE SIDE

BOTH SIDES

250mW
1.67mW I'C

500mW
3.33mW I'C

NOTE: Stresses above those listed under ''Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended peri-

TO-7B

ods may affect device reliability.

ORDERING INFORMATION
TO-78
2N5117

0223-1

4503

2N5118
2N5119

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise specified)

Symbol

hFE

ICBO

2N5117
2N5118

Test Conditions

DC Current Gain

Collector Cutoff-Current

2N5119

Min

Max

Min

Ic=10,..A, VCE=5.0V

100

300

50

Ic=500,..A, VCE=5.0V

100

50

Ic=10,..A, VCE=5.0V, TA= -55·C

30

20

IE=O, VCB=30V

I TA=150·C

Units

Max

0.1

0.1

nA

0.1

0.1

,..A
nA

lEBO

Emitter Cutoff Current

Ic=O, VEB=5.0V

0.1

0.1

Ic -C2

Collector-Collector Leakage

VCC=100V

5.0

5.0

GBW

Current Gain Bandwith Product (Note 4)

Ic=500,..A, VCE=10V

Cob

Output CapaCitance (Note 4)

IE=O, Vca=5.0V, f=1MHz

0.8

Ct.

Emitter Transition CapaCitance (Note 4)

Ic=O, VEa=0.5V,1= 1MHz

1.0

1.0

Cc~~

Collector-Collector Capacitance (Note 4)

VCC=O, 1= 1MHz

0.8

0.8

VCEO(sust)

Collector-Emitter Sustaining Voltage

Ic=1.0mA,la=0

NF

Narrow Band Noise Figure (Note 4)

Ic=10,..A,VCE=5.0V
BW=200Hz

BVcao

Collector Base Breakdown Voltage

Ic= 10,..A,IE=0

45

45

V

BVEBO

Emitter Base Breakdown Voltage

IE=10,..A,lc=0

7.0

7.0

V

I f=1kHz,RG=10k!l

0.8

45

45

pA
MHz

100

100

4.0

pF

V
4.0

dB

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have b89n chsractsriz6d but are not fBstsd.

10-37

....,...
G)

2N5117-2N5119

= MATCHING CHARACTERISTICS

(TA = 25°C unless otherwise specified)

I

...10...
t-

Z

~

Symbol

Parameter

2N5117 2N5118 2N5119

Test Conditions

Units

Min Max Min Max Min Max

~FE/hFE2

DC Current Gain Ratio
(Note 3)

~SE1-VSE2

0.9 1.0

Ic= 10p.A to 500p.A, VCE=5V

0.85 1.0 0.8 1.0

Ic= 10p.A, VCE= 5.0V

Base-Emitter Voltage
Differential

3.0

Ic= 10p.A to 500p.A, VCE=5V

5.0

10.0

15

40

nA

p'vrc

Ic= 10p.A, VCE=5.0V
Base Current Differential

181-IS2

mV
5.0

~(VSE1-VSE2)/ a T Base Voltage Differential
Change with Temperature

TA = -55°C to

+ 125°C

3.0

5.0

10

Base-Current Differential
Change with Temperature

TA = -55°C to

+ 125°C

0.3

0.5

1.0 nAloC

a(lSl-IS2)/ a T
NOTES: 1.
2.
3.
4.

Per transistor.
The reverse base-to...mitter voltage must never exceed 7.0 volts and the reverse base-to...mitter current must never exceed 10/'A.
Lower of two hFE readings is defined as hFE1'
For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIIIC WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AHtyp/c8lVBlusshsvobHn_butsro

not_

10-38

D~Dlb5...

2N5196 - 2N5199
Dual N-Channel JFET
General Purpose Amplifier

CD

GI
I

N

Z

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION
TO-71

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions

above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabilily.

0224-1

6037

ORDERING INFORMATION
TO-71
2N5196
2N5197
2N5198
2N5199

ELECTRICAL CHARACTERISTICS
Symbol

IGSS

(TA = 25'C unless otherwise specified)
Test Conditions

Parameter

Gate Reverse Current

Min

VGs= -30V, VDS=O
TA=150°C

Max

Units

-25

pA

-50

nA

V

BVGSS

Gate-Source Breakdown Voltage

IG= -1"A, VDS=O

-50

VGS(Off)

Gate-Source Cutoff Voltage

VDS=20V,ID=1nA

-0.7

-4

VGS

Gate-Source Voltage

VDG=20V,ID=200"A

-0.2

-3.8

IG

Gate Operating Current

-15

nA

0.7

7

mA

1000

4000

700

1600

IDSS

Saturation Drain Current (Note 2)

VDS= 20V, VGS=O

gfs

Common-Source Forward Transconductance (Note 2)

VDS= 20V, VGS=O

gfs

Common-Source Forward Transconductance (Note 2)

VDG=20V,ID=200"A

gos

Common-Source Output Conductance (Note 2)

VDS=20V, VGS=O

SO

gos

Common·Source Output Conductance (Note 2)

VDG=20V,ID=200"A

4

Ciss

Common-Source Input Capacitance (Note 4)

VDs=20V, VGS=O

Crss

Common-Source Reverse Transfer Capacitance
(Note 4)

NF

Spot Noise Figure (Note 4)

en

f=1kHz

f=1MHz

pA

-15

TA=125°C

6

"s

pF

2
f=100Hz,
RG= 10M!}

Equivalent Input Noise Voltage (Note 4)

f=1kHz

O.S
20

dB
nV

,}Hz

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTiCLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are net tested.

10-39

...
CIt

(TA = 25'C unless otherwise noted)
Gate-Source or Gate-Drain Voltage (Note 1) ....... - 50V
Gate Current (Note 1) ........................... 50mA
Storage Temperature Range .......... - 65'C to + 200'C
Operating Temperature Range ........ -55'C to + 150'C
Lead Temperature (Soldering, 10sec) ........... + 300'C
One Side Both Sides
Power Dissipation (TA = 85'C) . . .
250mW
500mW
Derating. . . . . . . . . . . . . . . . . . .. 2.6mW I'C 4.3mW I'C

CD
CD

.8: 2N5196-2N5199
=
.
II)

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise specified) (Continued)

I

CD

GI

Symbol

Parameter

Test Conditions

II)

Z

""

2N5196

2N5197

2N5198

2N5199

IIG1- IG21

Differential Gate Current

VOG=20V,lo=200,.A
TA=125°C

IOSSl/1oSS2

Saturation Drain Current Ratio
(Note 2)

VOS= 20V, VGS=OV

0.95

1

0.95

1

0.95

1

0.95

1

gl81 / gls2

Transconductance Ratio
(Note 2)

f=lkHz

0.97

1

0.97

1

0.95

1

0.95

1

I VGS1-VGS21

Differential Gate-Source Voltage

III VGS1 =vGS21 Gate-Source Differential Voltage VOG=20V, TA=25°C
Change with Temperature
lo=200,.A Ts=125°C
VDO/I>IVGS1- VGS21, (I>VDD ~ 10V)
3. For design reference only, not 100% tested.

INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

10-53

~

Z

en
en

.
~

~ 2N5638-2N5640
:z N-Channel JFET Switch
&II
I
co FEATURES

'"
Z

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise specified)

• Economy Packaging

G
10 • Faat Switching
&II

Drain-Source Voltage ............................. 30V
Drain-Gate Voltage .••••••.•••.•••••••••••••••.•.• 30V
Source-Gate Voltage ............................. 30V
Forward Gate Current ........................... 10mA
Storage Temperature Range •..••.•... -65°C to + 150"C
Operating Temperature Range ••.•.••• - 55°C to + 135°C
Lead Temperature (Soldering, 10see) ••.•.••.•.• + 300"C
Power Dissipation ............................. 310mW
Derate above 25°C ...................... 2.82mW'oC

• Low DralnoSource 'ON' Resistance

PIN CONFIGURATION
TO-92

NOTE: SIr9sstJs above those I/stad undar "Absoluta Maximum Ratings"
may CBUSS psrmsnent damage to the davlca. These are str9sS ratings only
and functlonsl operstion of the davlca at _
or any other conditions
above those Indlcatad In the operstlonsl sections of the spscIfications is not
ImpIIsd. Exposure to IIbso1uta maximum raling conditions for 8X/6ndad perlods may affect davlca rellsbility.

ORDERING INFORMATION
D

•

0

T0-92
0232-1

2N5638

5001

2N5639
2N5640

ELECTRICAL CHARACTERISTICS
Symbol

(TA = 25°C unless otherwise specified)

Parameter

2N5838

Test Conditions

Min
-30

BVGSS

Gate Reverse Breakdown Voltege

IG= -10p.A, Vos=O

IGSS

Gate Reverse Current

VGS= -15V, VOs=O

10(011)

Drain Cutoff Current

Vos=15V, VGS= -12V(2N5638), VGS= -8V(2N5639),
VGS = -8V (2N5840)
TA=I00'C

TA=100'C

loss

Saturation Drain Current

VOS(on) Drain-Source ON Voltege

VGs=O,lo= 12mA (2N5638),
10=6mA (2N5639),lo=3mA(2N5640)

2N584O

Max Min

-30

-30

V

-1.0

-1.0

nA

-1.0

-1.0

-1.0

p.A

1.0

1.0

1.0

nA

1.0

1.0

1.0

p.A

25

5.0

mA

0.5

0.5

0.5

V

30

60

100

60

n

30

100

10

10

10

4.0

4.0

4.0

roS(on)

Stetic Drain-Source ON Resistance 10= lmA, VGS=O

rds(on)

Draln-Source ON Resistance

VGs=O,lo=O

f=lkHz

GJ••

Common-Source Input
Cspacitance (Note 2)

VGS= -12V, Vos=O

1=IMHz

Cras

Common-Scurce Reverse Transfer
Capacitance (Note 2)

leI(on)

Turn-On Delay Time (Note 2)

Voo=10V

10(on) = 12mA (2N5638)

4.0

6.0

8.0

t,.

Rise Time (Note 2)

~~~:on): ~ 10V

10(on) = 6mA (2N5639)

5.0

8.0

10

lei
It

Turn-OFF Delay Time (Note 2)

10(on) = 3mA (2N5640)

5.0

10

15

10

20

30

Fall Time (Note 2)

Units

Max

-1.0

50

Vos=20V, VGS=O (Note 1)

2N5839

Max Min

pF

"Gbn

RG =
(Note 2)

ns

NOTES: 1. Pulse test; PW:l:300p.s, duty cycle:l:3.0%.
2. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
.

NOTE: AU typical v.1wB MIA bHn cMracttItIz«I but.,. not_ted.

10-54

2N5638-2N5640
VDD

=10VDC

. -......---Wl.---<>

RL

0.1,.F

~ TO SO OHM SCOPE.

INPUT
(SCOPE A)

:a

'::N) - (rOS(ON) + SOD)

.r-

~ 10%

~~--C~--~,:::·'"

~
•• %

0.001"F

VOS(onl

--i I- I,

--I

1---0

d(O'f)
I
I
~
"
'90%

OUTPUT
(SCOPE 8)

10%

0232-3

1.0KO

t - - - - + - - - - - - - - - - - - - - O TO SO OHM SCOPE A
SCOPE

son

TEKTRONIX 58fA
OR EQUIVALENT

0232-4

Figure 1: Switching Times Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOT£' All typical values have been characterized but are not teslBd.

10-55

~

O~O[6

2N5902-2N5909

::z Monolithic Dual N-Channel JFET
~ General Purpose Amplifier
N

o FEATURES
GI

II)

Z
N

ABSOLUTE MAXIMUM RATINGS

• Tight Tracking
• Good Matching

(TA = 25'C unless otherwise specified)
Gate-Drain or Gate-Source
Voltage (Note 1) .............................. -40V
Gate Current (Note 1) ........................... 10mA
Storage Temperature Range .......... -65'C to + 200'C
Operating Temperature Range ........ - 55'C to + 150'C
Lead Temperature (Soldering, 10sec) ........... +300'C

PIN CONFIGURATION
TO-99

Power Dissipation ............
Derate above 25'C .........

One Side
367mW
3mWI'C

Both Sides
500mW
4mWI'C

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress retings only
and functional operation of the device at these Or any other conditions

above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

c

G.

0,

ORDERING INFORMATION

$.

0233-1

6015

TO-99
2N5902
2N5903
2N5904
2N5905
2N5906
2N5907
2N5908
2N5909

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25'C unless otherwise specified)
Test Conditions

2N5902-6 2N5903-7 2N5904-8 2N5905-9

Units

Min Max Min Max Min Max Min Max

I IG1- IG2 I
IOSS1
IDSS2
9fs1

Differential Gate Current

Saturation Drain Current Ratio
Transconductance Ratio

VOG=10V, 2N5902-5
lo=30fLA,
TA=125'C 2N5906-9
Vos=10V, VGS=O
f= 1kHz

2.0

2.0

2.0

2.0

0.2

0.2

0.2

0.2

0.95

1

0.95

1

0.95

1

0.95

1

0.97

1

0.97

1

0.95

1

0.95

1

nA

9fs2

IVGS1- VGS21
I

Differential Gate-Source Voltage

A VGS1-VGS21 Gate-Source Voltage Differential VOG=10V, TA=25'C
Drift (Measured at end points
lo=30fLA Ts=125'C
AT
TAandTs)
TA= -55'C
Ts=25'C
19051-90S21

Differential Output Conductance

f=lkHz

5

5

10

15

5

10

20

40

5

10

20

40

0.2

0.2

0.2

0.2

mV

fLY I'C

fLs

lNTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

10-56

.O~OIL N
Z
CII
at

2N5902-2N5909
ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Test Conditions

2N5902-5

Min
IGSS

VGS= -20V, VOs=O

BVGSS

Gate-Source Breakdown Voltage

IG= -1",A, VOS=O

-40

VGS(off)

Gate-Source Cutoff Voltage

Vos=10V,10=1nA

-0.6

VGS

Gate Source Voltage

VOG=10V, 10 = 30",A

IG

Gate Operating Current
TA=125°C
f=1kHz

Saturation Drain Current

gls

Common-Source Forward
Transconductance

gos

Common-Source Output Conductance

Vos=10V, VGS=O

Ciss

Common-Source Input Capacitance

Gras

Common-Source Reverse Transfer
Capacitance

Vos=10V, VGS=O
(Note 1)

9is

Common-Source Forward
Transconductance

gos·

Common-Source Output Conductance
Equivalent Short Circuit Input
Noise Voltage (Note 1)

NF

VOG=10V,10=30",A

f=1kHz

f=100Hz
RG=10MO

-2

pA

-5

nA

-4.5

V

N

Z
CII
at
oat

-40
-4.5

-0.6

-4

-4

-3

-1

-3

-1

nA
",A

500

30

500

70

250

70

250

50

I

Units

Max

30

f=1MHz

Vos=10V, VGS=O

Spot Noise Figure (Note 1)

Min

-10

TA=125°C

loss

Max

N

2N5906-9

-5

Gate Reverse Current

en

o

(Continued) (TA = 25°C unless otherwise specified)

5

5

3

3

1.5

1.5

150

50

150

pA

",S

pF

",S

1

1

0.2

0.1

~

3

1

dB

",V

NOTE 1: For design reference only, no1100% tested.

•
INTERSIL·S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHAll BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typ/C8IvsJuos ha.. bHn _

but BrB not IBsIlod.

10-57

; 2N5911, 2N5912,
~ ITC5911, ITC5912,
:: IT5911, IT5912
: Dual N-Channel JFET
&Ii High Frequency Amplifier

!:

...

o FEATURES

ABSOLUTE MAXIMUM RATINGS

g

(TA = 25·C unless otherwise noted)
Gate-Drain or Gate-Source Voltage ............... - 25V
Gate Current ................................... 50mA
Storage Temperature Range .. . . . . . . .. - 65·C to + 200·C
Operating Temperature Range ........ - 55·C to + 150·C
Lead Temperature (Soldering, 10sec) ........... + 300·C
TO-71
TO-99

10

• Tight Tracking
• Low Insertion Loss
• Good Matching

...o PIN CONFIGURATION
g
...

10

TO-71
(IT5911-12)

TO-99
(2N5911-12)
(ITC5911-12)

One
Side

One
Side

Both
Sides

Power
Dissipation . . .. 200mW 400mW 367mW 500mW
Derate above
25·C ......... 1.6mWrC3.2mWrC3.0mWrC4.0mWrC

......
o
a

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended peri~
ods may affect device reliability.

c S'

0, G,
G, 0, 5,

10

Z

(\I

Both
Sides

0234-1

6011-2N5911-12,ITC5911-12
6022-2N5911-12,ITC5911-12

ORDERING INFORMATION
TO-71

TO-99

Wafer

Dice

IT5911

2N5911

2N5911/W

2N5911/D

IT5912

2N5912

2N5912/W

2N5912/D

ELECTRICAL CHARACTERISTICS
Symbol
IGSS

(TA = 25·C unless otherwise specified)

Parameter

Test Conditions

Gate Reverse Current

Min

VGS= -15V, VOs=O
TA=150·C

Max

Units

-100

pA

-250

nA

V

BVGSS

Gate Reverse Breakdown Voltage

IG= -l,..A, VOs=O

-25

VGS(offl

Gate-Source Cutoff Voltage

Vos=10V,lo=lnA

-1

-5

VGS

Gate-Source Voltage

VOG=10V,lo=5mA

-0.3

-4

IG

Gate Operating Current
TA=150·C

loss

Saturation Drain Current (Pulsewidth 300,..s,
duty cycle,,; 3%)

VOS=10V, VGS=OV

gf.

Common-Source Forward Transconductance

VOG=10V,lo=5mA

-100

pA

-100

nA
mA

7

40

f=lkHz

5000

10,000

5000

10,000

gf.

Common-Source Forward Transconductance (Note 1)

f=100MHz

go.

Common-Source Output Conductance

f=lkHz

100
150

goss

Common-Source Output Conductance (Note 1)

f=100MHz

Cjss

Common-Source Input Capacitance (Note 1)

/=lMHz

Cr••

Common-Source Reverse Transfer Capacitance (Note 1)

en

Equivalent Short Circuit Input Noise Voltage (Note 1)

NF

pF

1.2
/=10kHz

Spot Noise Figure (Note 1)

5

,..s

f=10kHz
RG=100kO.

nV

20

JHz

1

dB

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PROQUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

10-58

2N5911, 2N5912, ITC5911, ITC5912,
IT5911, IT5912
ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(Continued) (TA = 25'C unless otherwise specified)

Test Conditions

IT,2N5911
Min

IiGl-IG21

Differential Gate Current

VOG=10V,lo=5mA

IOSSI

Saturation Drain Current Ratio

Vos=10V, VGS=O
(Pulsewidth 300",s, duty cycles3%)

IOSS2

IVGS1-VGS21

Transconductance Ratio

Min

0.95

1

20
0.95

Z

Units

Max
nA

1

.
~
....
CIt

10

~

CIt

10

10

15

TA=25'C
Ts=125'C

20

40

TA=-55'C
Ts=25'C

20

f= 1kHz

gls2

Max
20

Differential Gate-Source Voltage

al VGS1-VGS21 Gate-Source Voltage Differential
Drift (Measured at end pOints,
aT
VOG=10V,lo=5mA
TA and Ts)

glsl

TA= 125'C

II)

IT,2N5912

mV

",VI'C
40

~CIt

..
10

~
0.95

1

0.95

1

:::'i

..
..
CIt

10

NOTE 1: For deSign relerence only, not 100% tested.

:::'i
CIt

10
II)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values hsvs bun charaotsrlzed but are not tsstsd.

10-59

D~DlL

.., 2N6483-2N6485
In

CD

co

zCOl
I

Dual N-Channel JFET

Low Noise Amplifier

CO)

..,

CD

FEATURES

ABSOLUTE MAXIMUM RATINGS

co • Ultra Low Noise
Z
COl

(TA = 25'C unless otherwise noted)
Gate-Source or Gate-Drain Voltage (Note 1) ....... - 50V
Gate-Gate Voltage ............................. ± 50V
Gate Current (Note 1) ........................... 50mA
Storage Temperature Range .......... -65'C to + 200'C
Operating Temperature Range ........ - 55'C to + 175'C
Lead Temperature (Soldering, 1Osee) ........... + 300'C

• High CMRR
• Low Offset
• Tight Tracking

PIN CONFIGURATION

Power Dissipation ........... .
Derate above 25'C ........ .

TO-71

One Side
250mW

Both Sides
400mW

1.7mWI'C

2.7mWI'C

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only

and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING INFORMATION
TO-71
0235-1

2N6483

6019

2N6484
2N6485

ELECTRICAL CHARACTERISTICS
Symbol
IGSS

(TA = 25'C unless otherwise specified)

Parameter
Gate Reverse Current

Test Conditions

Min

VGS= -30V, Vos=O

I

TA=150'C

BVGSS

Gate-Source Breakdown Voltage

IG= -l/LA, Vos=O

-50

Vp

Gate-Source Pinch Off Voltage

Vos=20V,10=lnA

-0.7

loss

Drain Current at Zero Gate Voltage (Note 2)

Vos= 20V, VGS=O

gls

Common-Source Forward Transconductance (Note 2)

g088

Common-Source Output Conductance

Vos=20V, VGS=O, f= 1kHz
(Note 6)

Ciss

Common-Source Input Capacitance

Crss

Common-Source Reverse Transfer CapaCitance

IG

Gate Current

Units
pA

-200

nA
V

-4.0

0.5

7.5

1000

4000

20

Vos=20V, VGs=O, f=lMHz
(Note 6)

rnA
/Ls

pF

3.5

VGO=20V, 10 = 200/LA (Note 6)

I

Max
-200

TA=150'C

100

pA

100

nA
V

VGS

Gate Source Voltage

VOG=20V,10= 2OO/LA

0.2

3.8

gls

Common-Source Forward Transconductance

VOG=20V, lo=200/LA, f= 1kHz

500

1500

90S

Common-Source Output Conductance

VDG=20V,10=200/LA

1

en

Equivalent Input Noise Voltage (Note 6)

VOS=20V, 10 = 200/LA, f= 10Hz

10

Vos=20V,ID=200p.A, f= 1kHz

5

/Ls

nV/,fHz

NOTES: 1. Per transistor.
2. Pulse test required; pulse width = 2ms.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE; All typical values have been characterized but are not tested.

10-60

1Il0~OIL N
Z

2N6483-2N6485

o

...

MATCHING CHARACTERISTICS
Parameter

Symbol
IOSS1

Test Conditions

IOSS2

Drain Current Ratio at Zero
Gate Voltage

Vos=20V, VGS=O
(Note 4)

IIG1 -IG21

Differential Gate Current

VOG=20V,lo=200"A
TA= +125'C

gl51

Transconductance Ratio

VOG=20V,lo=200"A,
f= 1kHz (Note 4)

1g051 - g052 1

Differential Output
Conductance (Note 6)

VOG=20V,lo=200"A,
f=1kHz

1VGS1 - vGS21

Differential Gate-Source
Voltage

VOG=20V,lo=200"A

~I VGS1 -vGS21

Gate-Source Voltage
Differential Drift

VOG=20V,lo=200"A
TA= -55'Cto +125'C

Common Mode Rejection
Ratio (Note 6)

VOo= 10 to 20V,
lo=200"A (Note 5)

g952

~T

CMRR

NOTES: 3.
4.
5.
6.

CD

(Continued) (TA = 25'C unless otherwise specified)
2N6483

W

2N6485

2N6484

I

Units

Max

Min

Max

Min

Max

o

0.95

1

0.95

1

0.95

1

en

10
0.97

1

10
0.97

10

1

0.95

...

CD

nA

1

0.1

0.1

0.1

"S

5

10

15

mV

5

10

25

"vrc

100

100

dB

90

TYPICAL PERFORMANCE CHARACTERISTICS
en

en vs. FREQUENCY

VB. FREQUENCY
100

YDS = 20V

10=200 ,.A

II

10 =
10

10

~~~S=15V

::;; Vos = 20V

1

10

r,

I 1/ I
100

1
1K

10K

100K

10

l00l~

10 - 2OO,.A
10 = 4OO,.A-

C"~

f-\~
Vrili

100

1K

10K

100K

frequency (Hz)

frequency (Hz)

0235-4

0235-3

GATE CURRENT VB. VDG

TYPICAL CAPACITANCE VS. VDS
15
14
3
2
1

100
SO
SO

1
};

40

I

20

f'If
--

10
8.0
6.0
4.0
2.0
1.0

~

= 200 pA

IGSS

./

~=400,.A/
o

Clss

10

eros

~=12OO,.A
10

15

20

25

o
30

VOG(V)

o2

4 6 8 10 121418 18 20 22 2428 2830
VOs(V)

0235-5

0235-6

INTEASll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

10-61

Z

Min

These ratings are limiting values above which the serviceability of any individual semiconductor device may be impaired.
Pulse duration of 2ms used during test.
CMRR ~ 20Log,0AVOOI A I VGS1·VGS21. (AVoo~ 10V). not included in JEDEC registration.
For design reference only, not 100% tested.

100

N

..

;; 3N161
II Diode Protected P-Channel
Enhancement Mode MOSFET
General Purpose AmplifierISwitch
FEATURES

ABSOLUTE MAXIMUM RATINGS

• Channel Cut Off With Zero Gate Voltage
• Square-Law Transfer Characteristic Reduces
Distortion
• Independent Substrate Connection Provides
Flexibility In Biasing
• Internally Connected Diode Proteeta Gate From
Damage Due to Overvoltage

(TA = 25'C unless otherwise noted)
Drain-Source or Drain-Gate Voltage ...............• 40V
Drain Current ••••.••.•.•••••••••.••.•......•..•• SOmA
Gate Forward Current ......•.•...•.•..•••••.•••• 1011A
Gate Reverse Current ...............•............ 1mA
Storage Temperature •••••.•••••••••• - 65'C to + 2000C
Operating Temperature .••.••••••.••• - 55'C to + 1500C
Lead Temperature (Soldering, 10sec) ..•...•.... + 3000C
Power Dissipation ..•...•......••....•......... 375mW
Derate above 25'C •••••••••••.••••••••••• 3.0mWrC

PIN CONFIGURATION

NOTE: SIrf1sses above those HsItKJ und6r "Absoluts Maximum Ratings"
may CIlUS6 ptHmIlnant damsge to the dsvica. ThastJ IUB stress ratings only
and functional optIfIJlion of the dsvica at these or any oth9r conditions
abova those Indicated In the optIfIJlionaI sactIons of the spscIf/cIllions 18 not
Implied. Exposure to IlbsoIuts msxJmum rating condIIions for sxtendBd fJBIIods may affect d6vica tell8bility.

T0-72

ORDERING INFORMATION

0237-1

15072

ELECTRICAL CHARACTERISTICS
Symbol
IGSSF

(TA = 25"Cand Ves=O unless otherwise specified)
Test Conditions

Parameter
Forward Gate-Terminal Current

Min

VGS= -25V, VOs=O
TA= +100'C

BVGSS

Forward Gate-Source Breakdown Voltage

loss

Zero-Gate-Voltage Drain Current

IG= -0.1mA, Vos=O

Max

Units

-100

pA

-10

nA

-25

V

VOS= -15V, VGS=O

-10

nA

Vos= -25V, VGS=O

-10

p.A

VGS(th)

Gate-Source Threshold Voltage

VOS= -15V,IO= -1011A

-1.5

-5

VGS

Gate-Source Voltage

VOS= -15V, 10= -8mA

-4.5

-8

10(on)

On-State Drain Current (Note 2)

VOS= -15V, VGS= -15V

-40

-120

IYlsl

Small-Signal Common-Source
Forward Transfer Admittance

3500

6500

IYosl

Small-Slgnal Common-Source
Output Admittance

Ciss

Common-Source Short-Circuit
Input Capacitance (Note 1)

Ctss

f= 1kHz

V
mA

p.s
250

VOS= -15V,10= -8mA
10
pF

f=1MHz

Common-Source Short Circuit
Reverse Transfer Capacitance (Note 1)

4

NOTE 1: For dssIgn refaranee only, not 100% tasted.
2: Pulaa test duration 300 ,.a; duty cycle s: 3%

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION Willi RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPUED OR STATUTORY. INCLUDIN(l THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE:AHtypIcIII.-"" .. . " _ b u t . , , , n o t _

10-62

3N163, 3N164
P-Channel Enhancement Mode
MOSFET General Purpose
Amplifier Switch
FEATURES

ABSOLUTE MAXIMUM RATINGS

• Very High Input Impedance

(TA = 2S·C unless otherwise noted)
Drain-Source or Drain-Gate Voltage
3N163 ...................................... -40V
3N164 ...................................... -30V
Static Gate-Source Voltage
3N163 ...................................... ±40V
3N164 ...................................... ±30V
Transient Gate-Source Voltage (Note 2) .......... ± 12SV
Drain Current ................................... SOmA
Storage Temperature ................ - 6S·C to + 200·C
Operating Temperature .............. - SS·C to + 1S0·C
Lead Temperature (Soldering, 10sec) ........... +300·C
Power Dissipation ............................. 37SmW
Derate above + 2S·C ..................... 3.0mW fOC

• High Gate Breakdown
• Fast Switching
• Low Capacitance

PIN CONFIGURATION
TO-72

(Note 1)

NOTES: 1. See handling precautions on 3N170 data sheet.
2. Devices must not be tested at ± 125V more than once, nor for
longer than 300ms.

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the devics. These are stress ratings only
and functional operation of the device at these or any other conditions

0238-1

above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

1503

ORDERING INFORMATION
TO-72

3N163
3N164

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 2S·C and VSS = 0 unless otherwise specified)
Test Conditions

3N163
Min

IGSS

Gate-Body Leakage Current

VGS= -40V, VOS=O (3N163)
VGS= -30V, VOS=O (3N164)

Max

3N164
Min

Units

Max

-10

-10

-2S

-2S

pA

I TA= + 12S·C

BVOSS

Drain-Source Breakdown Voltage

10= -10",A, VGS=O

-40

BVsos

Source-Drain Breakdown Voltage

Is= -10",A, VGo=O, Vso=O

-40

-30
-30
-S.O

VGS(th)

Threshold Voltage

VOs=VGS, 10= -10",A

-2.0

-S.O

-2.0

VGS(th)

Threshold Voltage

VOS= -1SV, 10= -10",A

-2.0

-S.O

-2.0

-S.O

VGS

Gate Source Voltage

VOS= -1SV, 10= -O.SmA

-2.S

-6.S

-2.5

-6.S

loss

Zero Gate Voltage Drain Current

VOS= -1SV, VGS=O

200

400

Isos

Source Drain Current

Vso=1SV, VGS=Vos=O

400

800

rOS(on)

Drain-Source on Resistance

VGS= -20V, 10= -100",A

10(on)

On Drain Current

VOS= -1SV, VGS= -10V

2S0
-S.O

-30.0

-3.0

V

pA

300

ohms

-30.0

mA

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have be9n characterized but are not tested

10-63

..'" 3N163,3N164
CD

Z

CIt

.

err
CD

Z

ELECTRICAL CHARACTERISTICS
Symbol

(Continued) (TA = 25'C and Ves = 0 unless otherwise specified)

Parameter

3N163

Test Conditions

Min

CIt

Vos= -15V, 10= -10mA, f= 1kHz

3N164

Max

Min

2000 4000 1000 4000

91s

Forward Transconductance

90S

Output Admittance

250

250

Giss

Input CapacitancEr-Output Shorted

2.5

2.5

0.7

0.7

3.0

3.0

Grss

Reverse Transfer Capacitance

Goss

Output Capacitance Input Shorted

Units

Max

Vos= -15V, 10= -10mA, f= 1MHz
(Note 1)

,...s

pF

NOTE 1: For design reference only, not 100% tested.

SWITCHING CHARACTERISTICS
Parameter

Symbol

(TA= 25'C and Ves = 0 unless otherwise specified)
3N163

Test Conditions
Min

3N164

Max

Min

Units

Max

Ion

Turn-On Delay Time

12

tr

Voo= -15V
10(on) = -1 OmA (Note 1)

12

Rise Time

24

24

toll

Turn-Off Time

RG=RL =1.4kO

50

50

ns

SWITCHING WAVEFORM

VDD

- . , 10%

1\

Rl
lon_

Vour

R2

10%

Ml

90%

10%

LJ I

I

.~

_loll

0238-4

INPUT PULSE
Rise Time ,;; 2 ns
Pulse Width ;" 200 ns
0238-3

SAMPLING SCOPE
tr';; 0.2 ns
C,N,;;2pF
R,N;" 10 MO

Figure 1. Switching Times Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values havs been characterized but ar8 not 16sted.

10-64

3N165, 3N166
Monolithic Dual P-Channel
Enhancement Mode MOSFET
General Purpose Amplifier
ABSOLUTE MAXIMUM RATINGS (Note 1)
(TA = 25'C unless otherwise specified)
Drain-Source or Drain-Gate Voltage (Note 2)
3N165 ........................................ 40V
3N166 ........................................ 30V
Transient Gate-Source Voltage (Note 3) ........... ± 125
Gate-Gate Voltage ............................. ± SOV
Drain Current (Note 2) ........................... 50mA
Storage Temperature ................ - 65'C to + 200'C
Operating Temperature .............. - 55'C to + 150'C
Lead Temperature (Soldering, 10sec) ........... + 300'C
Power Dissipation
One Side .................................. 300mW
Both Sides ................................. 525mW
Total Derating above 25'C ................. 4.2mW/'C

FEATURES
• Very High Impedance
• High Gate Breakdown
• Low Capacitance

PIN CONFIGURATION
TO-99
BOTTOM VIEW

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only

0239-4

and functionsl operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not

0239-1

2506

implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabJ11ty.

DEVICE SCHEMATIC

ORDERING INFORMATION
TO-99

,-JW'-,
1

7

J

8

3N165

to

3N166

4

0239-2

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25'C and VSS = 0 unless otherwise specified)

Limits

Test Conditions
Min

Units

Max

IGSSR

Gate Reverse Leakage Current

VGs=40V

IGSSF

Gate Forward Leakage Current

VGs=-40V

10

loss

Drain to Source Leakage Current

VOs= -20V

-200

Isos

Source to Drain Leakage Current

Vso= -20, Vos=O

-400

-10

I

TA=

+ 125'C

-25

10(on)

On Drain Current

VOs= -15V, VGS= -10V

-5

-30

VGS(thl

Gate Source Threshold Voltage

VOs= -15V,lo= -1OtJoA

-2

-5

VGS(th)

Gate Source Threshold Voltage

VOS=VGS, 10= - 1OtJoA

-2

-5

rOS(onL

Drain Source ON Resistance

VGS= -20V,10= -1OOtJoA

300

pA

mA
V
ohms

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIeD OR STATUTORY, INCLUDING THE IMPLIED WARRANTlES OF
MERCHANTABlLlTY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

10-65

U)
U)

...

3N165,3N166

z

(')

iii'

...

ELECTRICAL CHARACTERISTICS

(Continued)(TA = 25°C and VBS = 0 unless otherwise specified)

U)

Z

Symbol

Limits

Test Conditions

Parameter

(')

Min

gfs

Forward Transconductance

gos

Output Admittance

Ciss

Input Capacitance

Crss

Reverse Transfer Capacitance

Coss

Output Capacitance

VDS= -15V,ID= -10mA, f= 1kHz

1500 3000

P.s

300
3.0
VDS= -15V,iD= -10mA, f=1MHz
(Note 4)

RE(Yfs) Common Source Forward Transconductance

MATCHING CHARACTERISTICS
Symbol

Units

Max

0.7

pF

3.0

VDS= -15V,ID= -10mA, f= 100MHz (Note 4) 1200

p's

3N165

Parameter

Test Conditions

Limits
Min

Yfsl IYfs2

Forward Transconductance Ratio

VDS= -15V,ID= -500p.A, f=1kHz

VGSl-2

Gate Source Threshold Voltage Differential

VDS= -15V,iD= -500p.A

100

mV

~VGSl-2

Gate Source Threshold Voltage Differential
Change with Temperature

VDS= -15V,IA= -500p.A
TA=-55°Cto = +25°C

100

p-vrc

~T

0.90

Units

Max

1.0

NOTES 1. See handling precautions on 3N170 data sheet.

2. Per transistor.
3. Devices must not be tested at ± 125V more than once, nor for longer than 300ms.
4. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: All typical values have been chsracterized but are not tested.

10-66

D~DIl;....

3N170, 3N171
N-Channel Enhancement
Mode MOSFET Switch

5>

....

FEATURES

HANDLING PRECAUTIONS

• Low Switching Voltages

MaS field-effect transistors have extremely high input resistance and can be damaged by the accumulation of excess static charge. To avoid possible damage to the device
while wiring, testing, or in actual operation, follow the procedures outlined below.
1.
To avoid the build-up of static charge, the leads of
the devices should remain shorted together with a
metal ring except when being tested or used.
2.
Avoid unnecessary handling. Pick up devices by the
case instead of the leads.
3.
Do not insert or remove devices from circuits with
the power on as transient voltages may cause permanent damage to the devices.

• Fast Switching Times
• Low Drain-Source Resistance
• Low Reverse Transfer Capacitance

PIN CONFIGURATION
10·72

ABSOLUTE MAXIMUM RATINGS
(T A = 25·C unless otherwise noted)
Drain-Gate Voltage ............................. ± 35V
Drain-Source Voltage ............................. 25V
Gate-Source Voltage ........................... ±35V
Drain Current ................................... 30mA
Storage Temperature Range .......... - 65·C to + 200·C
Operating Temperature Range ........ -55·C to + 150·C
Lead Temperature (Soldering, 10sec) ........... + 300·C
Power Dissipation ............................. 300mW
Derate above 25·C ....................... 2.4mW

0240-1

1003

ORDERING INFORMATION

rc

TO-72
3N170

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only

3N171

and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied Exposure to absolute maximum rsting conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
Symbol

(25·C unless otherwise noted) Substrate connected to source.
Limits

Test Conditions

Parameter

Min
BVoss

Drain-Source Breakdown Voltage

IGSS

Gate Leakage Current

loss

VGS(th)

Zero-Gate-Voltage Drain Current

Gate-Source
Threshold Voltage

I
I

Units

Max

25

10=10fJ-A, VGS=O

V

VGS= ±35V, VOs=O

±10

VGs=35V, VOs=O, TA= 125·C

100

Vos=10V, VGS=O

I
3N170

TA=125·C

Vos=10V,lo= 10fJ-A

3N171

pA

10

nA

1.0

fJ-A

1.0

2.0

1.5

3.0

10

V
rnA

10(on)

"ON" Drain Current

VGs=10V, Vos=10V

VOS(on)

Drain-Source "ON" Voltage

10=10mA, VGs=10V

2.0

V

rds(on)

Drain-Source ON Resistance

VGS=10V, 10=0, f=1.0kHz

200

0.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NorE: All typical values have been charBCfBrlzed but 8IB not 1Bstsd.

-Col

z

10-67

I:
... 3N170, 3N171
zft

o

...Z
....
ft

ELECTRICAL CHARACTERISTICS

.OIM1/Di)OIl.
(Continued) (TA = 25°C unless otherwise specified) Substrate connected to

source.

Symbol

Teat Condition.

Parameter

Limits
Min

IVIsI

Forward Transfer Admittsnce

Vos= 10V,lo=2.0mA,
f= 1.0kHz

Units

Max

1000

,...S

Cras

Reverse Transfer Capacitance (Note 1)

Vos=O, VGS=O, f= 1.0MHz

1.3

Ciss

Input Cspacitance (Note 1)

Vos= 10V, VGS=O, f= 1.0MHz

5.0

Cd(sub)

Drain-Substrate Cspacitance (Note 1)

VO(SUB)= 10V, f=1.0MHz

5.0

1d(on)

Turn-On Delay Time (Note 1)

Voo=10V,IO(on)=10mA,

3.0

t,-

Rise Time (Note 1)

VGS(on) = 10V, VGS(off) = 0,

10

1d(off)

Turn-Off Delay Time (Note 1)

RG=50n

3.0

tf

Fall Time (Note 1)

pF

ns

15

NOTE 1: For design reference only, not 100% tested.

INTEflSlL'S SOLE AND EXCLUSive WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE OONDiTlON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typqt_ Irs"" """" _ _ _ but". not too/8d.

10-68

D~DlL;....

3N172, 3N173
Diode Protected P-Channel
Enhancement Mode MOSFET
General Purpose AmplifierISwitch

,!I)

.....

61

Z

61

FEATURES

ABSOLUTE MAXIMUM RATINGS

• High Input Impedance

(TA= 25°C unless otherwise noted)
Drain-Source or Drain-Gate Voltage
3N172 ......•.•••••.•.•....................... 40V
3N173 ...............••....................... 30V
Drain Current ....................•.••.•••••••.•• 50mA
Gate Forward Current .••.•.•....•............... 10pA
Gate Reverse Current ..........•...•..•....•....• 1mA
Storage Temperature ................ - 65°C to + 200"C
Operating Temperature •............. - 55°C to + 150"C
Lead Temperature (Soldering,10sec) ..•........ +300"C
Power Dissipation ...............•••••••••..••• 375mW
Derate above 25°C ...................•..• 3.0mW'oC

• Diode Protected Gate

PIN CONFIGURATION
10·72

8_

NOTE: Stresses above those listBd under ''AbsoIuta Maximum Ratings"
may CBUSfJ parmaflfJllt dafT11J(J9 to tha davic9. Thas9 ara
ratings only
and functional operation of tha davic9 at thasa or any othar conditions
above those IndIcatBd In tha operational sections of the specifications is not
impIiad. Exposurs to absolute maximum rating conditions for extendad periods may affact davice rsUability.
0241-1

15032

ORDERING INFORMATION*
To-72

DEVICE SCHEMATIC

3N172
1

3N173

t£:
4

0241-2

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25°C and Ves = 0 unless otherwise specified)

Test Conditions

3N172
Min

IGSS

Gate Reverse Current

VGs=-20V

I TA=+125°C
BVGSS

Gate Breakdown Voltage

10= -10p.A

-40

BVoss

Drain-Source Breakdown Voltage

10= -10pA

-40

Max

3N173
Min

-200

-500

pA

-0.5

-1.0

p.A

-125

-30

-125

-30

BVsos

Source-Drain Breakdown Voltage

Is= -10p.A, Voe=O

-40

VGS(Ih)

Threshold Voltage

VOS=VGS, 10= -10pA

-2.0

-5.0

-2.0

-5.0

VOs= -15V, 10= -10pA

-2.0

-5.0

-2.0

-5.0

VGS

Gate Source Voltage

Vos= -15V,lo= -500pA

-3.0

-6.5

-2.5

-6.5

loss

Zero Gate Voltage Drain Current

VOs= -15V, VGS=O

-0.4

-10

Isos

Zero Gate Voltage Source Current

Vso= -15V, Voe=O, VGo=O

-0.4

-10

rOS(on)

Drain Source On Resistance

VGS= -20V,lo= -100,.A

Io(on)

On Drain Current

Vos= -15V, VGS= -10V

-30

250
-5.0

Units

Max

-30

-5.0

V

nA

350

ohms

-30

mA

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN lypicalva/uBShavsbHn_bulsro

not_

10-69

III

.z 3N172,3N173
CO)

....
CO)

..

N

....

Z

Small-Signal Electrical Characteristics

TA = 25'C and Bulk (substrate) Lead Connected to Source
3N172

Symbol

Parameter

Units

CO)

Magnitude of Small-Signal,
Common-Source, Short-Circuit,
Forward Transadmittance"

Vos= -15V, 10= -10 mA,
f=1 kHz

Magnitude of Small-Signal,
Common-Source, Short-Circuit,
Output Admittance"

Vos= -15V, 10= -10 mA,
f= 1 kHz

Ciss

Small-Signal, Common-Source,
Short-Circuit, Input Capacitance"

Vos= -15V, 10= -10 mA,
f=1 MHz

Crss

Small-Signal, Common-Source,
Short-Circuit, Reverse Transfer
Capacitance"

Vos= -15V, 10= -10 mA,
f= 1 MHz

Small-Signal, Common-Source,
Short-Circuit, Output Capacitance"

Vos= -15V, 10= -10 mA,
f=1 MHz

IYlsl

IYosl

Coss

3N173

Test Conditions
Min

Max

Min

Max

1500

4000

1000

4000

",mhos

250

250

",mhos

3.5

3.5

pF

1.0

1.0

pF

3.0

3.0

pF

Noise Characteristics
Symbol
NF

Parameter

Test Conditions

Typical

Units

Common-Source Spot Noise Figure

Vos= -15V, 10= -1 mA,
f= 1 kHz, RG= 1 M!l

1.0

dB

Switching Characteristics

TA = 25'C Bulk (substrate) Lead Connected to Source
3N172

Symbol

Parameter

Units
Min

td (on)

Turn-On Delay Time"

3N173

Test Conditions
Min

Max

Max

Voo=-15V,
10 (on) = -10 mA

12
24

24

ns

50

50

ns

tr

Rise Time"

RG=RL = 1.4 k!l

toft

Turn-Off Time"

See Test Circuit Below

12

ns

'Registered JEDEC Data

SWitching Time Detail
Measurements on Sampling Oscilloscope with
trise s: 0.2 ns
CinS:2.O pF

Switching Times vs On-State
Drain Current
tODD _ _
SOD

Rin~10M!l

~O~~'~~TK

Voo

Input Pulse

tOO

triseS:2 ns
Pulse Width ~ 200 ns

50

I.ff"
Irl..

to

5.0

d(o.)

t.O
-O.t

-0.5

-1.0

-5.0

-to

ON- STATE DRAtN CURRENT- (to(o.»- mA
0241-4

0241-5

0241-3
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valuss hays been characterized but srs not tested.

10-70

D~DI1.;

3N188-3N191
Dual P-Channel
Enhancement Mode MOSFET
General Purpose Amplifier

C»
C»

..
I

fot

Z
CO

FEATURES

ABSOLUTE MAXIMUM RATINGS

•
•
•
•

(TA = 2S·C unless otherwise noted)
Drain-Source or Drain-Gate Voltage (Note 1)
3N188,3N189 ................................. 40V
3N190,3N191 ................................. 30V
Transient Gate-Source Voltage (Notes 1 and 2) ... ± 12SV
Gate-Gate Voltage ............................. ± 80V
Drain Current (Note 1) ........................... SOmA
Storage Temperature ................ - 6S·C to + 200·C
Operating Temperature .............. - SS·C to + lS0·C
Lead Temperature (Soldering, 10sec) ........... + 300·C
Power Dissipation
One Side .................................. 300mW
Both Sides ................................. S2SmW
Total Derating above 2S·C ................. 4.2mWrC

Very High Input Impedance
High Gate Breakdown 3N190-3N191
Zener Protected Gate 3N188-3N189
Low Capacitance

PIN CONFIGURATION
TO·99

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
C

G.

s.

D.

ORDERING INFORMATION

0242-1

2506

TO-99
3N188
3N189
3N190
3N191

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 2S·C and VBS=O unless otherwise specified)
Test Conditions

3N188
3N189
Min

IGSSR

Gate Reverse Current

VGs=40V

IGSSF

Gate Forward Current

VGS= -40V

Max

3N190
3N191
Min

Units

Max
10

I

TA=12S·C

-200

-10

-200

-2S

BVoss

Drain-Source Breakdown Voltage

10= -lOILA

-40

BVsos

Source-Drain Breakdown Voltage

Is= -lOILA, VBO=O

-40

VGS(th)

Threshold Voltage

Vos= -lSV, 10= -lOILA

-2.0

-S.O

-2.0

-S.O

Vos = VGS, 10= - lOILA

-2.0

-S.O

-2.0

-S.O

-3.0

-6.S

-3.0

-40
-40

Gate Source Voltage

Vos= -lSV,lo= -SOOILA

loss

Zero Gate Voltage Drain Current

Vos= -lSV

-200

-200

Isos

Source Drain Current

VSO= -lSV, VOB=O

-400

-400

ros(on)

Drain-Source on Resistance

Vos= -20V,lo= -lOOILA

10(on)

On Drain Current

Vos= -lSV, VGs= -10V

300
-30.0

-S.O

V

-6.S

VGS

-S.O

pA

pA

300

ohms

-30.0

mA

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

10-71

IIID~Dn..

....c;;z 3N188-3N191
cw:

ELECTRICAL CHARACTERISTICS

(Continued) (TA = 25'C and Ves = 0 unless otherwise specified)

CD
CD

....

Z

Symbol

Parameter

3N188
3N189

Test Conditions

3N190
3N191

Units

f')

Qfs

Forward Transconductance (Note 3)

Yos

Output Admittance

Ciss

Input Capacitance Output Shorted (Note 5)

Crss

Reverse Transfer Capacitance (Note 5)

Coss

Output Capacitance Input Shorted (Note 5)

SWITCHING CHARACTERISTICS
Symbol

f=1kHz

Vos= -15V,
10= -10mA

Min

Max

Min

Max

1500

4000

1500

4000

f=1MHz

300

300

4.5

4.5

1.5

1.0

3.0

3.0

Limits

Test Conditions
Min

Units
Max

td(on)

Turn On Delay Time

Voo= -15V, 10= -10mA

15

tr

Rise Time

RG = RL = 1.4kn (Note 5)

30

toll

Turn Off Time

Symbol

pF

(TA = 25'C and Ves=O unless otherwise specified)

Parameter

MATCHING CHARACTERISTICS

"'S

ns

50
(TA = 25'C and Ves = 0 unless otherwise specified) 3N188 and 3N190

Parameter

Test Conditions

Limits
Min
0.85

Units

Max

Yfs1 /Yfs2

Forward Transconductance Ratio

Vos= -15V, 10= -500",A, f=1kHz

VGS1-2

Gate Source Threshold Voltage Differential

Vos= -15V, 10= -500",A

100

1.0
mV

AVGS1-2
AT

Gate Source Threshold Voltage Differential
Change with Temperature (Note 4)

Vos= -15V, 10= -500",A,
T= -55'C to + 25'C

100

",VI'C

AVGS1-2
AT

Gate Source Threshold Voltage Differential
Change with Temperature (Note 4)

Vos= -15V, 10= -500",A
T= + 25'Cto +125'C

100

",VI'C

NOTES: 1. Per transistor.

2. Approximately doubles for every 10"C increase in TA.
3. Pulse test duration=300"s; duty cycleS:3%.
4. Measured at end points, TA and TB.
5. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values haV9 bun characterized but 8(9 not t8Sf9d.

10-72

ID100, ID101
Dual Low Leakage Diode
GENERAL DESCRIPTION

FEATURES

The 10100 and 10101 are monolithic dual diodes intended
for use In applications requiring extremely low leakage cur·
rents. Applications include interstage coupling with reverse
isolation, signal clipping and clamping and protection of ul·
tra low leakage FET differential dual and operational amplifi·
ers.

elll =0.1pA (Typical)
e BVII>30V
e Crs.=0.75pF (Typical)

ABSOLUTE MAXIMUM RATINGS
(TA= 25°C unless otherwise noted)
Diode Reverse Voltage ............................ 30V
Diode to Diode Voltage .. . .. .. .. .. .. .. .. .. .. . .... ± 50V
Forward Current ................................ 20mA
Reverse Current ............................... 100,...A
Storage Temperature Range .......... - 65°C to + 200"C
Operating Temperature Range ........ - 55°C to + 150"C
Lead Temperature (Soldering, 1Osee) •...•.••.•. +300"C
Power Dissipation ............................. 300mW
Derate above 25°C ....................... 2.4mWI"C

PIN CONFIGURATIONS
T()'71
TO·78

NOTE: SIrtJss9s above those 1ist8d under "Absclute MBXimum Ratings"
may cause permanent damsge to the davicB. Thess are stress ratings only
and funct/onBl opertJl/on of the davicB at these or any other conditions
above those JndicBted In the opertJlIonBl sscl/ons of the specif/cBtions is not
impIisd. ExposurtI to absolul8 mBXimum rating conditions for extBnded periods may affect davicB rsJiBbib'ty.
0243-1

4000

ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS
Symbol

"

Parameter

(@ 25°C unless otherwise noted)

10100,10101

Test Conditions
Min

Typ

VF

Forward Voltage Drop

IF=10mA

0.8

BVR

Reverse Breakdown Voltage

IR=l,...A

30

IR

Reverse Leakage Current

VR=1V

0.1

VR=10V

2.0

I

1.1

Differential Leakage Current

VR = 10V

Cras

Total Reverse Capacitance

VR= 10V, f=lHz (Note 1)

V
V

TA=125°C

IIR1- IR21

Units
Max

0.75

pA
10
10

nA

3

pA

1

pF

NOTE 1: For design reference only, not 100% tested.
2: Pins 3 and 5 should not be connected tog_ nor connected to the elreilft In any way.

INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT BTATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHAll BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR BTATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,

NOTE: AN /yp/C8IvaIuos have bssn ~ but IUO not tostsd.

10·73

•

... ID100, ID101

o
S

oo

9

TYPICAL PERFORMANCE CHARACTERISTICS
FORWARD CURRENT vs. VOLTAGE

CAPACITANCE vs. VOLTAGE

REVERSE CURRENT vs VOLTAGE
12

1.0

11

0.1

10

0.8

'it

0.7

lOOmA

"-

10 ....

r--- t--

r--

~

lmA

0.6

/'"
./

0.3
I

......

0.2

./'

o

"

10

0.'
10 ",A.

...... i-""

o

lOOIJ.A.

0.5

I

hA

0.1

,.

2D

25

30

00

10

15

20

25

30

l00nA

o

0.5

1.4

Vn(VI

0243-3

0243-4

0243-5

INTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANT ABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not t8816li.

10·74

IT100, IT101
P-Channel JFET Switch

3

GENERAL DESCRIPTION

FEATURES

This P-channel JFET has been designed to directly interface with TIL logic, thus eliminating the need for costly drivers, in analog gate circuitry. Bipolar inputs of ± 15V can be
switched. The FET is OFF for hi level inputs (+ 5V or
+ 15V) and ON for low level inputs «0.5 V for
IT1 00, < 1.5V for IT1 01).

• Interfaces Directly w/TTL Logic Elements

...o

• rDS(On)<75n for 5V logic Drive
• lD(off) < 100pA

ABSOLUTE MAXIMUM RATINGS
(TA = 25·C unless otherwise noted)
Gate-Source Voltage ............................. 35V
Gate-Drain Voltage ............................... 35V
Gate Current ................................... 50mA
Storage Temperature Range •..•.•••.• - 65·C to + 200·C
Operating Temperature Range ...•.... - 55·C to + 150·C
Lead Temperature (Soldering, 10sec) ........... +300·C
Power Dissipation ............................. 300mW
Derate above 25·C ....................... 2.4mW'·C

PIN CONFIGURATION
TO-18

NOTE: StresS6S aboVt!J those 1 _ under "Absolute MsxJmum Ratings"
may cause permanent damage to Ihs davies. Th9s9 af9 stress ralfngs only
and functlonsl operation of the davic9 at Ih9ss or any other conditions
aboVt!J those Indicated In Ihs operatlonsl ssctlons of Ih9 spscifiestlons Is not
implied. Exposure to absolute msxJmum rating conditions for 9Xl9nded periods may affect davic9 f9llsbilily.
D G.C

S

0244-1

5514

ORDERING INFORMATION
TO-18
IT100
IT101

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25·C unless otherwise specified)

IT101

IT100

Test Conditions
Min

IGSS

Gate Reverse Current

VGS=20V, VOs=O

BVGSS

Gate-Source Breakdown Voltage

IG=1"A, VOs=O

35

Vp

Pinch Off Voltage

10=1nA. Vos= -15V

2

Max

Min

Units

Max
200

200
35
4.5

4

loss

Drain Current

VGS=O, VOS= -15V

-10

-20

gfs

Transconductance

VGs=O, Vos= -15V

8

8

gos

Output Conductance

10(otl)

Drain (OFF) Leakage

VOS= -10V, VGs=15V

rOS(on)

Drain-Source "ON" Resistance

VGS=O, VOS= -0.1V

Ciss

Input Capacitance

VOG= -20V, VGS=O (Note 1)

Crss

Reverse Transfer Capacitance

VOG= -10V, Is=O (Note 1)

pA
V

10
mA
mS

1

1

-100

-100

pA

75

60

n

35

35

12

12

pF

NOTE 1: For design reference only. not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARnCLE OF THE CONDITION OF BALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANnES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARnCULAR UBE.

NOTE: A1J typ/cB/ ..1ues ha.. bNn charBcIotfzod but ar. not tooled.

10-75

•

~

IT120, IT122

Dual NPN
g General Purpose Amplifier
t:

E FEATURES
•
•
•
•

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Collector-Base Voltage (Note 1) .................... 45V
Collector-Emitter Voltage (Note 1) .................. 45V
Emitter Base Voltage (Notes 1 and 2) ................ 7V
Collector Current (Note 1) ....................... 50mA
Collector-Collector Voltage .•................•..... 60V
Storage Temperature Range .......... -65°C to + 200°C
Operating Temperature Range ........ -55°C to + 150'C
Lead Temperature (Soldering, 10sec) ........... + 300'C

High hFE at Low Current
Low Output Capacitance
Good Matching
Tight VBE Tracking

PIN CONFIGURATION
TO·71
TO·78

TO-7B
One
Side
250mW

TO-71

Both
Sides
500mW

One
Side
200mW

Both
Sides
400mW

Power Dissipation
Derate Above
25'C ......... 1.7mW/,C 3.3mW/,C 1.3mW/,C 2.7mW/,C
NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in /he operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods mayaff9ct device reliability.

0245-1

4003

ORDERING INFORMATION
TO·78

TO·71

IT120

IT120-T071

IT121

IT121·T071

IT122

IT122-T071

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25'C unless otherwise specified)

Test Conditions

IT120A

IT120

IT121

1T122

Units

Min Max Min Max Min Max Min Max
Ic=10",A, VCE=5.0V

200

200

80

80

hFE

DC Current Gain

Ic=1.0mA, VCE=5.0V

225

225

100

100

VBE(ON)

Emitter-Base On Voltage

Ic=10",A,
VCE=5.0V

TA=-55'C

VCE(SAD Collector Saturation Voltage Ic=0.5mA,IB=0.05mA
ICBO

Collector Cutoff Current

IE=O, VCB=45V
TA=

+ 150'C

75

30

75

30

0.7

0.7

0.7

0.7

0.5

0.5

0.5

0.5

1.0

1.0

1.0

1.0

nA

10

10

10

10

",A
nA

lEBO

Emitter Cutoff Current

Ic=O, VEB=5.0V

1.0

1.0

1.0

1.0

Cobo

Output Capacitance

IE=O, VCB=5.0V f=lMHz

2.0

2.0

2.0

2.0

Gte

Emitter Transition
Capacitance

Ic=O,
VEB=0.5V

2.5

2.5

2.5

2.5

CC1,C2

Collector to Collector
Capacitance

VCC=O

4.0

4.0

4.0

4.0

(Note 3)

V

pF

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FiTNESS FOR A PARTICULAR USE.
NOTe: All typical values have been characteriz9d but ars not tested.

10-76

IT120, IT122
ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25'C unless otherwise specified)

Test Conditions

IT120A

IT120

IT121

IT122

Units

Min Max Min Max Min Max Min Max
IC1,C2

Collector to Collector
Leakage Current

VCC= ±60V (Note 3)

VCEO(SUST)

Collector to Emitter
Sustaining Voltage

Ic=1.0mA,ls=0

GBW

Current Gain Bandwidth
Product (Note 3)

Ic=10",A, VCE=5V

10

10

7

7

Ic=1mA, VCE=5V

220

220

180

180

1VSEI - VSE21

Base Emitter Voltage
Differential

Ils 1 -ls2 1

Base Current Differential

Jl(VSEl -VSE2)

Base-Emitter Voltage
Differential Change
with Temperature

aT

IC= 10",A, VCE=5.0V

(Note 3)
TA = -55'C to + 125'C
Ic= 10",A, VCE=5.0V

10
45

10
45

10
45

10
45

nA
V
MHz

1

2

3

5

mV

2.5

5

25

25

nA

3

5

10

20

",VI'C

NOTES: 1. Per transistor.
2. The reverse base-to·emitter voltage must never exceed 7.0 volts and the reverse base·to·emitter current must never exceed 10pA
3. For design reference only, not 100% tested.

III

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATEO IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTV SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bsen chsrscf8tiz6d but 8f9 not tested.

10-77

= IT126-IT129
~ Monolithic Dual NPN
= General Purpose Amplifier
E FEATURES
•
•
•
•
•

ABSOLUTE MAXIMUM RATINGS
(TA= 25°C unless otherwise specified)
Collector·Base Voltage (Note 1)
IT12S,IT127 ................................... SOV
IT128 .................................. " ...... 55V
IT129 ......................................... 45V
Collector·Emitter Voltage (Note 1)
IT12S, IT127 ................................... SOV
IT128 ......................................... 55V
IT129 ...•..................................... 45V
Emitter·Base Voltage (Notes 1 and 2) .•............ 7.0V
Collector Current (Note 1) ...................... 100mA
Collector·Collector Voltage ........................ 70V
Storage Temperature Range ........•. - S5°C to + 175°C
Operating Temperature Range ........ - 55°C to + 175°C
Lead Temperature (Soldering, 1Osee) ........... + 3000C

High Gain at Low Current
Low Output Capacitance
Tight la Match
Tight VaE Tracking
Dlelectrlcally Isolated Matched Pairs for Differential
Amplifiers

PIN CONFIGURATION
T()'71
TO·78

T071

T078

One
Both
One
Both
Power Dissipation
Side Sides Side Sides
Total Dissipation at 25°C 200mW 400mW 250mW 500mW
1.3
2.7
1.7
3.3
Derating Factor ........ mwrc mwrc mwrc mwrc
NOTE: Stresses above those IistBd under "AbsoIul6 Msximum Ratings"
may causa fJBI7TISnBnt damage to the davice. Thasa sra stress ratings only
and functional operation of the dav1c9 at these or any other conditions
above those indicalBd in the operationsl sections of the specifications is not
implied. Exposure to absoIul6 maximum rating conditions for BXl6nded pBfiods may affect dav1c9 tellabHIty.

0247-1

4001

ORDERING INFORMATION
T078

T0-71

IT126

IT126-T071

IT127

IT127-T071

IT128

IT128-T071

IT129

IT129-T071

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25°C unless otherwise specified)

IT126

Test Conditions

Min
hFE

DC Current Gain

IT127

Max

Min

800

200

Max

150

IT128
Min

1T129

Max Min
70

Ic=10p.A, VCE=5V

150

Ic=1.0mA, VCE=5V

200

100

Ic=10mA, VCE=5V

230

230

170

Ic=50mA, VCE=5V

100

100

75

50

IC=1mA, VCE=5V, TA= -55°C

75

75

60

40

800

150

Units

Max

800

100
115

Emitter·Base
On Voltage

Ic=10mA, VCE=5V

0.9

0.9

0.9

Ic=50mA, VCE=5V

1.0

1.0

1.0

1.0

VCE(sat)

Collector Saturation
Voltage

Ic=10mA,le=1mA

0.3

0.3

0.3

0.3

Ic=50mA,le=5mA

1.0

1.0

1.0

1.0

Iceo

Collector Cutoff
Current

IE=O, Vce= 45V,

0.1

0.1

0.1

0.1'

nA

0.1

0.1

0.1

0.1'

p.A

VeE(on)

Vce=30V' (IT129), TA=

+ 1500C

0.9
V

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE:AH typIcalVBiuBsluJllflbHn _ b u t . , . , not tsstod.

10-78

IT126-IT129
ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(Continued) (TA = 25"C unless otherwise specified)

Test Conditions

IT126
Min

IT128

1T127

Max

Min

Max

Min

IT129

Max

Min

Units

Max

IESO

Emitter Cutoff Current

IC=O, VES=5V

0.1

0.1

0.1

0.1

nA

Cobo

Output Capacitance (Note 3)

IE=O, VCs=20V

3

3

3

3

pF

BVC1C2

Collector to Collector Breakdown
Voltage

Ic= ±1,..A

VCEO(sust) Collector to Emitter Sustaining
Voltage

Ic=1mA,ls=0

BVcso

Collector Base Breakdown
Voltage

Ic= 1O,..A, IE=O

BVESO

Emitter Base Breakdown Voltage

IE= 1O,..A, Ic=O

±100

±100

±100

±100

60

60

55

45

60

60

55

45

7

7

7

7

V

MATCHING CHARACTERISTICS
Symbol

Parameter

Test Conditions

IT126

1T127

1T128

1T129

Units

Min Max Min Max Min Max Min Max
1VSE1-VSE21

Base Emitter Voltage Differential

Ic=1mA, VCE=5V

~(IVSE1-VSE21) Base Emitter Voltage Differential
~T

Ils 1-ls 2 1

Ic= 1mA, VCE=5V
Change with Temperature (Note 3) TA= -55"Cto + 125"C
Base Current Differential

1

2

3

5

mV

3

5

10

20 ,..VI"C

Ic=10,..A, VCE=5V

2.5

5

10

20

nA

Ic= 1mA, VCE=5V

0.25

0.5

1.0

2.0

,..A

NOTES: 1. Per transistor.
2. The reverse base~to-emitter voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed lOILA.
3. For design reference only, not 100% tested.

•
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE ANO SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE; All Iyp;cal values have been characterized but are not .ested.

10-79

= IT130-IT132

t Monolithic Dual PNP
I

g General Purpose Amplifier

t

FEATURES

ABSOLUTE MAXIMUM RATINGS

• High hFE at Low Current
• Low Output Capacitance

(TA = 25°C unless otherwise specified)
Collector-Base Voltage (Note 1) .................... 45V
Collector-Emitter Voltage (Note 1) .................. 45V
Emitter Base Voltage (Notes 1 and 2) ................ 7V
Collector Current (Note 1) ....................... 50mA
Collector-Collector Voltage ........................ 60V
Storage Temperature Range .......... - 65°C to + 175°C
Operating Temperature Range ........ - 55°C to + 175°C
Lead Temperature (Soldering, 10sec) ........... + 300°C
TO·71
TO·7S

• Tight IB Match
• Tight VBE Tracking

PIN CONFIGURATIONS
TO·71
TO·78

Both
Sides
400mW

One
Side
200mW

One
Side
250mW

Both
Sides
500mW

Power
Dissipation 1.3mWrC 2.7mWrC 1.7mWrC 3.3mWrC
NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress rstings only
and fUnctional operation of the device at these or any other conditions

above those indicated in the operational sections of the specifications is not
E.

s.

implied Exposure to absolute maximum rating conditions for extended peri~
ods may affect device reliability.

c.

4503

0248-1

ORDERING INFORMATION
TO·78

TO·71

IT130A

IT130A-T071

IT130

IT130-T071

IT131

IT131-T071

11132

IT132-T071

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25°C unless otherwise specified)
Test Conditions

IT130A

1T130

IT131

1T132

Units

Min Max Min Max Min Max Min Max
hFE

DC Current Gain

Ic=10",A, VCE=5.0V

200

200

80

80

Ic=1.0mA, VCE=5.0V

225

225

100

100

Ic=10",A, VCE=5.0V,
TA= -55°C

75

75

30

30

VSE(ON)

Emitter-Base On Voltage

Ic= 10",A, VCE=5.0V

0.7

0.7

0.7

0.7

VCE(SAT)

Collector Saturation Voltage

Ic=0.5mA,ls=0.05mA

0.5

0.5

0.5

0.5

leso

Collector Cutoff Current

IE=O, Vcs=45V,
TA= + 150°C

-1.0

-1.0

-1.0

-1.0

nA

-10

-10

-10

-10

",A
nA

IESO

Emitter Cutoff Current

le=O, VES=5.0V

-1.0

-1.0

-1.0

-1.0

Cob (Note 3)

Output Capacitance

IE=O, Vcs=5.0V

2.0

2.0

2.0

2.0

Gte (Note 3)

Emitter Transition Capacitance Ic=O, VES=0.5V

2.5

2.5

2.5

2.5

4.0

4.0

4.0

4.0

CC1 -C2 (Note 3) Collector to Collector
Capacitance

VCC=O

V

pF

lNTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE COND1T10N OF SALE.
THE WARRANTY SHALL SE EXCLUS1VE AND SHALL BE 1N LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values havs besn characterized but are not test6(/.

10-80

IT130-IT132
ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(Continued) (TA = 25'C unless otherwise specified)
Test Conditions

IT130A

IT130

IT131

IT132

Units

Min Max Min Max Min Max Min Max
IC1-C2

Collector to Collector Leakage
Current

VCC= ±60V

~CEO(SUST)

Collector to Emitter Sustaining
Voltage

Ic=1.0mA,ls=0

~BW

Current Gain
Bandwidth Product (Note 3)

-45

10

10
-45

-45

Ic=10,...A, VCE=5V

5

5

4

4

110

110

90

90

Base Emitter Voltage
Differential

Ic=10,...A, VCE=5.0V

Ils1-ls 2 1

Base Current Differential

IC=10,...A, VCE=5.0V

Differential Change with
Temperature (Note 3)

-45

10

Ic=1mA, VCE=5V

1 VSE1-VSE2 1

~(VSE1-VSE2)/ ~ T Base-Emitter Voltage

10

TA= -55'Cto + 125'C
Ic=10,...A, VCE=5.0V

nA
V

MHz

1

2

3

5

mV

2.5

5

25

25

nA

3

5

10

20 ,...VI'C

NOTES: 1. Per transistor.
2. The reverse base-to-emitter voltage must never exceed 7.0V, and the reverse base-to-emitter current must never exceed 10""A.
3. For design reference only, not 100% tested.

III

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charact8rizeci but are not tested.

10-81

= IT136-IT139
t

D~DIl

Monolithic Dual PNP
General Purpose Amplifier

=
I

t

FEATURES

ABSOLUTE MAXIMUM RATINGS

•
•
•
•
•

(TA = 25°C unless otherwise noted)
Collector-Base Voltage (Nole 1)
IT136,IT137 ., ... ,., ...•. , .... , ... ,., ... ' ..... ' 60V
IT13S •• , .. ,.,', .......... , ....... ,., ........•. 55V
IT139 ..•...• , •..•• , ..•.• ,'".,.' •..........•. , 45V
Collector-Emitter Voltage (Note 1)
IT136,IT137 .. , ... , ........... ,.".,., .... " ... 60V
IT 138 ., .... , ... ', ....... ' .. '., ... ,., ... , ... ,. 55V
IT139 ., .... ,., .... , ..... , .. , ... , .. , ... "., ... , 45V
Emitter Base Vollage (Notes 1 and 2) •.• , ....• , ..... , 7V
Collector Current (Note 1) .... , ....... ,., ....... 100mA
Collector-Collector Voltage •.... ,.,.,., •... , .. ,., •. 70V
Storage Temperature Range. , .. , ....• -65°C to + 175°C
Operating Temperalure Range .. ,.,.,. -55°C 10 + 175°C
Lead Temperature (Soldering, 10sec) •. , ....... , +300"C
To-71
TO·78

High Gain at Low Current
Low Output Capacitance
Tight IB Match
Tight VBE Tracking
Dielectrically Isolated Matched Pairs for Differential
Amplifiers

PIN CONFIGURATION
TO·71
TO·78

Both
Sides

One
Side

E,

Power
Dissipation . .. 200mW 400mW 250mW 500mW
Derate
above 25°C ., 1.3mWI"C 2. 7mWI"C 1.7mWI"C 3.3mWI"C

C.

B.

0249-1

NOTE: Stresses above thoss listed under "AbsoIuf9 Maximum Ratings"
may cause permanent damage to th9 c/9vice. These are stress retings only
and functional opers.tion of the c/9vice at these or any other conditions
above thoss indicated In th9 opers.tionsl sections of th9 specifications is not
/mp//ed. Exposure to absolute maximum rating conditions for extsnc/9d perlods mayaffBct c/9vice rsiiability.

4501

ORDERING INFORMATION
TO-78

To-71

IT136

IT136-T071

IT137

1T137-T071

IT13S

IT13S-T071

IT139

IT139-T071

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25°C unless otherwise specified)
IT136

Test Conditions

Min
hFE

DC Current Gain

Both
Sides

One
Side

Max

IT137
Min

IT138

Max

Min

SOO

100

150

IT139

Max

Min

SOO

70

Ic=10p.A, VCE=5V

150

Ic=1.0mA, VCE=5V

150

Ic=10mA, VCE=5V

125

125

SO

50

Ic=50mA, VCE=5V

65

60

40

25

Ic=1mA, VCE=5V
TA=55°C

75

75

60

40

SOO

150

100

Units

Max

70
SOO

VSE(on)

Emitter-Base On Voltage

Ic=10mA, VCE=5V

.9

.9

.9

.9

Ic=50mA, VCE=5V

1,0

1,0

1,0

1.0

VCE(sat)

Collector Saturation Voltage

Ic=1mA,ls=,1mA

.3

.3

.3

.3

Ic=10mA,ls=1mA

.6

,6

,6

.6

V

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical vsJuss have been characteriz9d but am not tesfBd.

10-S2

IT136-IT139
ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(Continued) (TA = 25'C unless otherwise specified)

Teet Conditione

IT136
Min

Collector Cutoff
Current

ICBO

IE=O, VCB=45V,
Vco=30V· (IT139),
TA= +150'C

lEBO

Emitter Cutoff
Current

Ic=O, VEB=5V

Cobo

Output Capacitance
(Note 3)

IE=O, VCB=20V,
f= 1MHz

BVC1C2

Collector to Collector
Breakdown Voltage

Ic= ±1p,A

VCEO(sust)

ColleC1or to Emitter
Sustaining Voltage

Ic=1mA,IB=0

BVCBO

ColleC1or Base
Breakdown Voltage

Ic=10p,A,IE=0

BVEBO

Emitter Base
Breakdown Voltage

IE= 10p,A, Ic=O

I VBE1-VBE2 I

Base Emitter
Voltage Differential

Ic=1mA, VCE=5V

III (VBE1-VBE2)1 Base Emitter Voltage
Differential Change with
IlT
Temperature (Note 3)
IIB1-IB21

IT137

Max

Min

1T138

Max

Min

IT139

Max

Min

Unite

Max

0.1

0.1

0.1

0.1·

nA

0.1

0.1

0.1

0.1·

p,A

0.1

0.1

0.1

0.1

nA

3

3

3

3

pF

±100

±100

±100

±100

60

60

55

45

60

60

55

45

7

7

7

7

V

Ic=1mA, VCE=5V
TA= -55'Cto
+ 125'C

Base Current Differential Ic=10p,A, VCE=5V
Ic=1mA, VCE=5V

1

2

3

5

mV

3

5

10

20

p,V/'C

2.5

5

10

20

nA

.25

.5

1.0

2.0

p,A

NOTES: 1. Per transistor.

2. The reverse base-to-emitter voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed 10p,A.
3. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tBSI9d.

10-83

~

D~Dll

IT500-IT505

:! Monolithic Dual Cascoded
i'

g N-Channel JFET General

~

Purpose Amplifier
GENERAL DESCRIPTION

FEATURES

A low noise, low leakage FET that employs a cascode
structure to accomplish very low IG at high voltage levels,
while giving high transconductance and very high common,
mode rejection ratio.

• CMRR> 120dB
• IG<5pA @ 50VOG
• C rss < 0.5pF
• 90S> .025",s

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS
(TA = 25'C unless otherwise specified)
Drain-Source and Drain-Gate
Voltages (Note 1) ................................. 60V
Drain Current(Note 1) ........................... 50mA
Gate-Gate Voltage ............................. ±60V
Storage Temperature ................ -65'C to + 200'C
Operating Temperature .............. - 55'C to + 150'C
Lead Temperature (Soldering, 10sec) ........... + 300'C

TO·71
low profile

Power Dissipation (Note 3) ....
Derate above 25'C .........
G.

o.

One Side
250mW
3.8mW/,C

Both Sides
500mW
7.7mW/'C

NOTE 1. Per transistor.
NOTE 2. Due to the non-symmetrical structure of these devices, the drain
and source ARE NOT interchangeable.
NOTE 3. @ 85"C free air temp.

$.

0250-1

6028

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions

SCHEMATIC DIAGRAM

above those indicated in the operational sections of the specifications is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING INFORMATION
TO-71
IT500
IT501

L-......------4_~CAS~

IT502

0250-2

IT503
IT504
IT505

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not testsr/.

10-84

.D~DI!..

ITSOO-ITSOS
ELECTRICAL CHARACTERISTICS
Symbol

I

(TA = 25'C unless otherwise specified)

Characteristics

::;
Lin

Test Conditions
Min

IGSS

Gate Reverse Current

VGS= -20V, VDS=O, TA=125'C

ilfnits

Max

-100

pA

-5

nA

V

Gate-Source Breakdown Voltage

IG= -1",A, VDS=O

-50

VGS(off)

Gate-Source Cutoff Voltage

VDS=20V,ID=1nA

-0.7

-4

VGS

Gate-Source Voltage

-0.2

-3.8

IG

Gate Operating Current

BVGSS

-5

VDG=35V,ID=200",A, TA=125'C

pA

-5

nA

0.7

7

mA

IDSS

Saturation Drain Current (Note 1)

gls

Common-Source Forward Transconductance (Note 1) VDS=20V, VGS=O

1000

4000

gls

Common-Source Forward Transconductance (Note 1) VDG=20V,ID=200",A f= 1kHz

500

1600

gos

Common-Source Output Conductance

VDS=20V, VGS=O

VDS=20V, VGS=O

",s

1
0.025

gos

Common-Source Output Conductance

VDS=20V,ID=200",A

Cg1g2

Gate to Gate Capacitance (Note 4)

VG1=VG2=10V

Ciss

Common-Source Input Capacitance (Note 4)

Crss

Common-Source Reverse Transfer Capacitance
(Note 3, 4)

NF

Spot Noise Figure (Note 4)

f= 100Hz,
RG= 10M!1

0.5

en

Equivalent Input Noise Voltage (Note 4)

f= 10Hz

50

",V

f= 1kHz

15

,/Hz

Symbol

Characteristics

Test Conditions

3.5
f=1MHz

IT501

IT502

pF

7

VDS=20V, VGS=O

IT500

pF

0.5

IT503

IT504

dB

IT505

Units

Min Max Min Max Min Max Min Max Min Max Min Max

IG1- IG2 Differential Gate
Current
IDSS1
IDSS2

Saturation Drain
Current Ratio
(Note 1)

VDG=20V,
ID=200",A, TA=125'C

5

5

5

10

5

15

nA

VDS=20V, VGS=OV

91s1/gls2 Transconductance
Ratio (Note 1)

If=1kHZ

0.95

1

0.95

1

0.95

1

0.95

1

0.9

1

0.85

1

0.97

1

0.97

1

0.95

1

0.95

1

0.90

1

0.85

1

INTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARAANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charactedzed but are not tested

10-85

::;

en
o
o

en
en

o

:g IT500-IT505

~
~

o

~

ELECTRICAL CHARACTERISTICS
Symbol

Characteristics

(Continued) (TA = 25'C unless otherwise specified)

Test Conditions

IT500

IT501

11502

IT503

IT504

IT505

Units

Min Max Min Max Min Max Min Max Min Max Min Max

~GS1-VGS2 Differential Gate-

VOG=20V
lo=200).tA

Source Voltage
.:WGS1-VGS2 Gate-Source Differential Voltage
aT
Change with Temp.
(Note 2,4)
CMRR

(Note 5)

Common Mode
Rejection
Ratio (Note 4)

5

5

10

15

25

50

TA=25'C
Ts=125'C

5

10

20

40

100

200

TA= -55'C
Ts=25'C

5

10

20

40

100

200

mV

).tVI'C

a VOO= 10V,lo=200).tA
120

120

120

120

120

120

dB

pulsewidth~300I's, duty cycle,;3%.
2. Measured at end paints, TA and T B.
3. Wtth case guarded Crss is typically < O.15pF.
4. For design reference only, not 100% tested.
S. CMRR~20 logW\.VDD/a [VgSl-V9S21. aVDD~10/-20V

NOTES: 1. Pulse test required,

TYPICAL PERFORMANCE CHARACTERISTICS
GATE LEAKAGE
if

~ 2.5

10" JOO$.lA

!it •

TA '" 2S'C

~

...
~
"'
.
~

OUTPUT CHARACTERISTICS

5

I

!Z

2.0

j

B

1.5

~

3

2

-V

:; 1

I

.P

10

20

30

40

Vos .Iov

I

!--

"'
:;!

g 1.0

V
50

L

1

60

Vas· -o.sv

Y-

VOS" -D.IV
VOS" -l.OV
Vos" -1.2V
Vas. -1:4V t""VGS· -1.6V

0.5

~

0

o

VDQ-DRAIN·QATE VOLTAGE - VOLTS

r-

VOS" -O.4V

r..

Z

~

VGS" -O.2V

~

10
DRAIN TO SOURCE VOLTAGE

0250-4

OUTPUT CHARACTERISTICS

10

c 2.5
I

8

2.0

\

"i!i

~ 0.5

l

o

1"-.
o

-0.5

1lz

6

~
1l

4

~

l\

1.0

VO~:~:MHz t-

i

1\

1.5

"'
:;!

5

.1 .1

....

E

i

0250-5

TYPICAL CAPACITANCE VS.
GATE·SOURCE VOLTAGE

-1.0

-1.5

o
-2.0

-2.5

e;.

c,~
o

-2

-6

.....

-I

-10

Vas-GATE SOURCE VOLTAGE-VOLTS

Vas-GATE·SOUACE VOLTAGE-VOLTS

0250-7
0250-6

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have besn characterized but are not tested.

U~UIl~o

IT1700
P-Channel
Enhancement Mode MOSFET
General Purpose Amplifier

o

FEATURES

ABSOLUTE MAXIMUM RATINGS

• Low ON-Resistance

(TA = 25'C unless otherwise noted)
Drain-Source and Gate-Source Voltage ___________ -40V
Peak Gate-Source Voltage (Note 1) ______________ ± 125V
Drain Current ___________________________________ 50mA

• High Gain
• Low Noise Voltage
• High Input Impedance

Storage Temperature ________________ -65'C to + 200'C
Operating Temperature Range ________ - 55'C to + 150'C
Lead Temperature (Soldering, 10sec) ___________ + 300'C
Power Dissipation _____________________________ 375mW
Derate above 25'C _____________________ .. _. 3mW I'C

• Low Leakage

PIN CONFIGURATION

NOTE: Stresses above those listed under "Absolute Maximum Ratings"

10-72

may cause permanent damage to the device. These are stress ratings only

and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING INFORMATION

G

o
0252-1

1503

ELECTRICAL CHARACTERISTICS
Symbol

(TA = 25'C and VBS = 0 unless otherwise specified)

Parameter

Limits

Test Conditions
Min

BVoss

Drain to Source Breakdown Voltage

VGs=O,lo= -10,.A

-40

BVSOS

Source to Drain Breakdown Voltage

VGs=O, 10= -1O,.A

-40

IGSS

Gate Leakage Current

loss

Drain to Source Leakage Current

loss (150'C)

Drain to Source Leakage Current

Units
Max
V
V

(See note 2)

VGS=O, VOS= -20V

200

pA

0.4

,.A

Isos

Source to Drain Leakage Current

400

pA

Isos (150'C)

Source to Drain Leakage Current

0.8

,.A

VGs(th)

Gate Threshold Voltage

VGs=Vos, 10= -1O,.A

rOS(on)

Static Drain to Source "on" Resistance

VGS= -10V, VOs=O

-2

los(on)

Drain to Source "on" Current

VGS= -10V, Vos= -15V

2

gf.

Forward Transconductance Common Source

VOs= -15V,lo= -10mA
1=1kHz

2000

GiSS

Small Signal, Short Circuit, Common Source,
Input Capacitance

VOs= -15V, 10= -10mA
1= 1MHz (Note 3)

erss

Small Signal, Short Circuit, Common Source,
Reverse Transler Capacitance

Coss

Small Signal, Short Circuit, Common Source,
Output Capacitance

-5

V

400

ohms
mA

4000

,.s

5

pF

VOG= -15V,lo=O
1= 1MHz (Note 3)

1,2

pF

VOs= -15V,lo= -10mA
1= 1MHz (Note 3)

3_5

pF

NOTES: 1. Device must not be tested at ± 125V more than once nor longer than 300ms.
2. Actual gate current is immeasurable. Package suppliers are required to guarantee a package leakage of < 10pA. External package leakage is the
dominant mode which is sensitive to both transient and storage environment, which cannot be guaranteed.
3. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical vaiues have been characterizlid but are not tested.

10-87

o
..... IT1750
N-Channel
II)

!:

Enhancement Mode MOSFET
General Purpose Amplifier Switch
FEATURES

ABSOLUTE MAXIMUM RATINGS

• Low ON Resistance

(TA = 25'C unless otherwise noted)
Drain·Source and Gate-Source Voltage ............. 25V
Peak Gate-Source Voltage (Note 1) ...•.......... ± 125V
Drain Current ................................. 100mA
Storage Temperature Range .......... -65'C to + 200'C
Operating Temperature Range ........ - 55'C to + 150'C
Lead Temperature (Soldering, 10sec) ........... + 300'C
Power Dissipation ............................. 375mW
Derate above 25'C ......................... 3mWI'C

• Low Cdg
• High Gain
• Low Threshold Voltage

PIN CONFIGURATION
TO·72

NOTE: Stresses abcve those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied Exposure to absolute maximum rsting conditions for extended peri-

ods may affect device reliability.

ORDERING INFORMATION

0253-1

1003

ELECTRICAL CHARACTERISTICS
(TA=25'C, Body connected to Source and VSs=O unless otherwise specified)
Symbol

Parameter

Limits

Test Conditions

VGS(th)

Gate to Source Threshold Voltage

Vos=VGS,10=10J-tA

loss

Drain Leakage Current

VOS= 10V, VGS=O

IGSS

Gate Leakage Current

Units

Min

Max

0.50

3.0

V

10

nA

See note 2.

BVoss

Drain Breakdown Voltage

10=10J-tA, VGS=O

rOS(on)

Drain To Source on Resistance

VGs=20V

10(on)

Drain Current

Vos=VGs=10V

Yls

Forward Transadmittance

Vos=10V,10=10mA,
f=1kHz

Ciss

Total Gate Input CapaCitance

10= 10mA, VOS= 10V,
f=1MHz (Note 3)

6.0

pF

CdsL

Gate to Drain Capacitance

VOG= 10V, f= 1MHz (Note 3)

1.6

pF

25

V
50

ohms

10

mA

3,000

J-ts

NOTES: I. Devices must not be tested at ± 125V more than once nor longer than 300ms.
2. Actual gate current is immeasurable. Package suppliers are required to guarantee a package leakage of100dB

ABSOLUTE MAXIMUM RATINGS
(TA = 25·C unless otherwise noted)
Collector-Base Voltage (1) ......................... 45V
Collector-Emitter Voltage (1) .............•......... 45V
Collector-Collector Voltage ........................ 45V
Emitter-Base Voltage (1) ........................... 6V
Collector Current (1) ............................ 20mA
Storage Temperature Range ... . . . . . .. - 65·C to + 200·C
Operating Temperature Range ........ - 55·C to + 150·C
Lead Temperature (Soldering, 10sec) ........... +300·C
Power Dissipation (TC = 25·C) .................. 800mW
Derate above 25·C ........................ 14mWfOC

PIN CONFIGURATION
TO·71
TO·78

NOTE: Stresses above those listed under "Absolute Msximum Ratings"
may csuse permanent damage to the davics. These af'9 stress ratings only
and functional operation of the davice at these or any other conditions
above those indicsted in the operationsl sections of the specifications is not
implied. Exposuf'9 to absolute msximum rating conditions for sxtendsd periods may affect device reliability.

ORDERING INFORMATION
0259-1

4003

ELECTRICAL CHARACTERISTICS
Symbol

TO-71

TO-78

LM114

LM114H

LM114A

LM114AH

(NOTE 2)

Parameter

Test Conditions

Maximum Umlta
LM114,H

0.5

2.0

mV

10

nA

40

nA

VSE1-2

Offset Voltage

1fJoA:S:lc:S:100fJoA

IS 1-2

Offset Current

Ic= 1OfJoA

2.0

Ic=1fJoA

0.5

Bias Current

t:"vSEIV

Offset Voltage Change

~lslV

Offset Current Change

Units

LM114A,AH

IC= 1OfJoA

20

Ic=1",A

3.0

OV,;;VCS:S:VMAX, Ic= 10fJoA

0.2

1.5

mV

1.0

4.0

nA

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tssted.

10-97

IID~OIL.

z LM114/M, LM114A/AM

i..
!i
....z
•....
!i

.. ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(Continued) (TA = 25°C unless otherwise specified)
Test Conditions

Maximum Limits
LM114A,AH

aVBE/·:n

Offset Voltage Drift

aIBl_2/aT

Offset Current

alB/aT

Bias Current

ICBO

Collector-Base
Leakage Current

VCB= VMAX

ICEO

Collector-Emitter
Leakage Current

VCE=VMAX. VEB=OV

IC1·C2

Collector-Collector
Leakage Current

VCC=VMAX

-55°C:S:TA:S: + 125°C,lc= 10p.A

I

I
I

TA = 125°C (Note 3)

TA = 125°C (Note 3)

TA = 125°C (Note 3)

Units

LM114,H

p'vrc

2.0

10

12

50

60

150

10

50

pA

10

50

nA

50

200

pA

nA

50

200

nA

100

300

pA

100

300

nA

NOTES: 1: Per transistor.
2: These specHications apply for TA= +25'C and OV,;;VCB,;;VMAX. unless otherwise specified: For the LM114 and LM114A. VMAX=30V.

3. For design reference only. not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OSLiGAnON WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANnES OF
MERGHANTABILrrv AND FITNESS FOR A PARTICULAR USE.
NOTE: AHtypIcaI _ _ bHn_butaro not testsd.

10-98

M116
Diode Protected N -Channel
Enhancement Mode MOSFET
General Purpose Amplifier
DEVICE SCHEMATIC

FEATURES
• Low IGSS
• Integrated Zener Clamp for Gate Protection

1

~:

PIN CONFIGURATION
TO·72

4

0260-2

ABSOLUTE MAXIMUM RATINGS
(TA = 25'C unless otherwise noted)
Drain to Source Voltage ........................... 30V
Gate to Drain Voltage ............................. 30V
Drain Current ................................... 50mA
Gate Zener Current ...•....................... ± 0.1 mA
Storage Temperature Range .......... - 65'C to + 200'C
Operating Temperature Range •....... - 55'C to + 125'C
Lead Temperature (Soldering, 1Osee) ........... + 300'C
Power Dissipation ............................. 225mW
Derate above 25'C ....................... 2.2mW/'C

0260-1

1003

ORDERING INFORMATION

~
~

NOTE: Stresses above those listed under ''Absolute Maximum Ratings"
may cause permanent damage to the device. These arB stress ratings only
and functional operation of /he device at these or any other conditions
above those indicated in the operationsl sections of the specifications not
implied. Exposura to absolute maximum rating conditions for extended peri·
ods may affect devioe raliability.

is

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25'C and VSS = 0 unless otherwise specified)

M116

Test Conditions
Min

rOS(on)

Drain Source ON Resistance

Units

Max

VGs=20V,10=100/LA

100

VGS= 10V, 10= 100/LA

200

VGS(th)

Gate Threshold Voltage

VGS= VOS, 10= 10/LA

BVOSS

Drain-Source Breakdown Voltage

10=1/LA, VGS=O

30

1

BVsos

Source-Drain Breakdown Voltage

Is=1/LA, VGO=VSO=O

30
30

n

5
V

60

BVGSS

Gate-Body Breakdown Voltage

IG=10/LA, VSs=VOs=O

10(OFF)

Drain Cutoff Current

Vos=20V, VGS=O

10

IS(OFF)

Source Cutoff Current

Vso=20V, VGO=Vso=O

10

IGSS

Gate-Body Leakage

VGs=20V, VOs=O

100

CgS

Gate-Source (Note 1)
Gate·Drain Capacitance (Note 1)

VGS=VOS=VSS=O, f=1MHz
Body Guarded

2.5

Cgd
Cdb

Drain-Body Capacitance (Note 1)

VGS=O, Vos=10V, f=1MHz

7

Ciss

Input Capacitance (Note 1)

VGS=O, Vos=10V, VSs=O, f= 1MHz

10

nA

pA

2.5
pF

NOTE 1: For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY. INCLUOING THE IMPLlEO WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterlzsd but are not testsd.

10-99

D~DIl

g U200-U202

~I N-Channel JFET Switch
o

~ FEATURES
:::t • Low Insertion Loss

APPLICATIONS
• Analog Switches
• Commutators
• Choppers

• Good OFF Isolation

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS
(TA = 25'C unless otherwise noted)
Gate·Drain or Gate-Source Voltage ............... -30V
Gate Current ................................... 50mA
Storage Temperature Range . . . . . . . . .. - 65'C to + 200'C
Operating Temperature Range ........ - 55'C to + 150'C
Lead Temperature (Soldering, 10sec) ........... +300'C
Total Device Dissipation (Tc=25'C) ............... 1.8W
Derate above 25'C ........................ 1OmW I'C

TO·18

D

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

S

0261-1

5001

ORDERING INFORMATION
TO-18
U200
U201
U202

ELECTRICAL CHARACTERISTICS

(TA = 25'C unless otherwise specified)

Symbol

Test Conditions

Parameter

U200
Min

Gate Reverse Current

IGSS

VGS= -20V, VOs=O
TA=150'C

BVGSS

Gate-Source Breakdown Voltage IG= -1/LA, VOs=O

-30

VGS(oll)

Gate-Source Cutoff Voltage

Vos=20V,lo=10nA

-0.5

10(011)

Drain Cutoff Current

VOS= 10V, VGS= -12V
TA=150'C

loss

Saturation Drain Current (Note 1) Vos=20V, VGS=O

3

rds(on)

Drain-Source ON Resistance

VGS=O, 10=0

Ciss

Common-Source Input
Capacitance (Note 2)

Vos=20V, VGS=O f=1MHz

f=1kHz

Crss

Common-Source Reverse
Transfer Capacitance (Note 2)

VOs=O,
VGs=-12V

U202

U201

Max

Min

Max

Min

Units

Max

-1

-1

-1

nA

-1

-1

-1

/LA

-30
-3

-1.5

-30
-5

-3.5

V
-10
nA

1

1

1

1

1

1

/LA

150

mA
ohm

25

15

75

30

150

75

50

30

30

30

8

8

8

pF

NOTES: 1: Pulse test required, pulsewidth=300"s. duty cycle,;3%.
2. For deSign reference only, not 100% tested.

INTERSIVS SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values havs been characterized but sre not tested.

10-100

.D~DIb:...

U231-U235

Dual N-Channel JFET
General Purpose Amplifier

I

C

I\)

Co»

CII

FEATURES

APPLICATIONS

• Good Matching Characteristics

• Differential Amplifiers
• Low and Medium Frequency Amplifiers

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS
(TA = 25'C unless otherwise noted)
Gate-Source or Gate-Drain Voltage (Note 1) _...... - 50V
Gate Current (Note 1) .•.......................•. 50mA
Storage Temperature Range ... . . . . . .. - 65'C to + 200'C
Operating Temperature Range ........ - 55'C to + 200'C
Lead Temperature (Soldering, 1Osee) ........... + 300'C
Power Dissipation ............................. 300mW
Derate above 25'C ....................... 1.7mWI'C

TO-71

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

s,
0262-1

6037

ORDERING INFORMATION

~
~
ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25'C unless otherwise specified)
Limits

Test Conditions
Min

IGSS

Gate Reverse Current

VGS= -30V, VOS=O
TA= 150'C

Units
Max
-100

pA

-500

nA

V

BVGSS

Gate-Source Breakdown Voltage

IG=lp.A, Vos=O

-50

VGS(off)

Gate-Source Cutoff Voltage

Vos= 20V, 10= lnA

-0.5

-4.5

VGS

Gate-Source Voltage

-0.3

-4.0

IG

Gate Operating Current

-50

VOG=20V,10=200p.A

loss

Saturation Drain Current (Note 2)

Vos=20V, VGS=O

Qts

Common-Source Forward
Transconductance (Note 2)

VOS= 20V, VGS=O

gts

Common-Source Forward
Transconductance (Note 2)

VOG= 20V, 10=200p.A

gos

Common-Source Output Capacitance

VOS= 20V, VGS=O

gos

Common-Source Output Conductance

VOG=20V,10=200p.A

Ciss

Common-Source Input
Capacitance (Note 4)

VOS= 20V, VGS=O

Crss

Common-Source Reverse Transfer
Capacitance (Note 4)

en

Equivalent Short Circuit
Input Noise Voltage

pA

-250

nA

0.5

5.0

mA

f=lkHz

1000

5000

f=100MHz
(Note 4)

1000

TA=125'C

p's

600
f=lkHz

1600
35
10

f=lMHz

6
pF
2

f=100Hz

80

nV

,fFiZ

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

10-101

II1D~OI!..

: U231-U235
~

.

::)
I

ELECTRICAL CHARACTERISTICS

(Continued) (TA = 25°C unless otherwise specified)

CO)
~

::)

Symbol

Matching Characteristics

Test Conditions

U231 U232 U233 U234 U235
Units
Max Max Max Max Max

IIGI -IG21

Differential Gate Current (Note 4) VOG= 20V, 10=200/LA, TA=125°C

10

10

10

10

10

nA

(IOSSI -IOSS2)

Saturation Drain Current
Match (Note 2, 4)

5

5

5

10

15

%

5

10

15

20

25

mV

10

25

50

75

100

10SSI
I VGS1-VGS21

Vos=20V, VGS=O

Differential Gate-Source Voltage

TA=25°C
TA=25°C

.lIVGS1- VGS21 Gate-Source Voltage
Differential Drift (Note 3)
.IT

Ts=125°C

/LvrC
TA= -SSOC
Voo= 20V, 10=2OO/LA Ts=25°C

gI81-g'8~

g'81
I g081-g082I
NOTES: 1.
2.
3.
4.

Transconductance Match
(Notes 2, 4)

f=1kHz

Differential Output Conductance

10

25

50

75

100

3

5

5

10

15

%

5

5

5

5

5

/Ls

Per transistor.
Pulse test required, pulse width = 300I'S, duty cycles: 3%.
Measured at end paints, TA and TB
For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical VS/UBS hayS been chsrscterized but ,rs not t9stBd.

10-102

U257
Dual N-Channel JFET
High Frequency Amplifier
FEATURES

ABSOLUTE MAXIMUM RATINGS

• 91S> 4500,..8 From DC to 100MHz

(TA = 25'C unless otherwise noted)
Gate-Drain or Gate-Source Voltage (Note 1) ....... -25V
Gate Current (Note 1) ........................... 50mA
Storage Temperature Range .......... - 65'C to + 200'C
Operating Temperature Range ........ - 55'C to + 150'C
Lead Temperature (Soldering, 10sec) ........... +300'C

• Matched VGS, 9fs and 90S

PIN CONFIGURATION
TO·gg

Power Dissipation
(TA=85'C) ........
Derate above 25'C

One Side

Both Sides

250mW

500mW

3.8mWI'C

7.7mW/'C

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended peri~
ods may affect device reliability.

ORDERING INFORMATION

0263-1

~
~

6022

ELECTRICAL CHARACTERISTICS
Symbol

(TA = 25'C unless otherwise specified)

Parameter
Gate Reverse Current

iGSS

Test Conditions

Min

VGs=15V, VOs=O
TA= 150·C

Max

Units

-100

pA

-250

nA

BVGSS

Gate·Source Breakdown Voltage

IG= -1f'A, Vos=O

-25

VGS(off)

Gate-Source Cutoff Voltage

Vos=10V,lo=1nA

-1

loss

Saturation Drain Current (Note 2)

Vos=10V, VGS=O

5

40

gts

Common-Source Forward Transconductance

VoS=10V, io=5mA

f=1kHz

4500

10,000

gts

Common-Source Forward Transconductance

VOG=10V,lo=5mA

f= 100MHz (Note 3)

4500

10,000

gos

Common-Source Output Conductance

VOS= 10V, lo=5mA

f=1kHz

200

f=100MHz

200

90ss

Common-Source Output Conductance

Cjss

Common·Source Input CapaCitance

erss

Common-Source Reverse Transfer
CapaCitance

en

Equivalent Input Noise Voltage

IOSS1

Drain Current Ratio at Zero Gate Voltage
(Note 2)

IOSS2
1VGS1-VGS21

Differential Gate-Source Voltage

gts1

Transconductance Ratio

VOG=10V, io=5mA

5

f=1MHz

mA

f's

pF

1.2
(Note 3)

f=10kHz

Vos=10V, VGS=O

30
0.85

Differential Output Conductance

f=1kHz

0.85

nV

,JHz

1
100

VOG=10V, iD=5mA

gts2
1gos 1-gos21

V
-5

mV

1
20

f's

NOTES: 1. Per transistor.
2. Pulse test required, pulse width = 300MS, duty cycle::;; 3%.
3. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

10-103

U~U[b

8 U304-U306
SI P-Channel JFET Switch
g FEATURES

.

APPLICATIONS

::::t • Low ON Resistance
• IO(Off)< SOOpA

• Analog Switches
• Commutators

• Switches directly from TTL Logic (U306)

• Choppers

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS
(TA = 2S·C unless otherwise noted)
Gate-Drain or Gate-Source Voltage (Note 1) ,.,., ... , 30V
GateCurrent ........... , ....... ,' .. , ..... ,.' ... SOmA
Storage Temperature Range, ... , ..... -6S·C to + 200·C
Operating Temperature Range ........ - SS·C to + lS0·C
Lead Temperature (Soldering, 10sec) ...... ,., ..•. 300·C
Power Dissipation .' ........................... 3S0mW
Derate above 2S·C , .. " .... " ...... ,., ... 2,8mW;oC

TO·18

NOTE: Stresses above those listeel under ''Absolute Maximum Ratings"
may cause permanent damage to the device, These are stress retings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
D G,C

implieel. Exposure to absolute maximum rating conditions for extendeel periods may aHect device reliability,

S

0264-1

ORDERING INFORMATION
TO·18
U304
U30S
U306

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 2S·C unless otherwise specified)
U304

Test Conditions

Min
IGSS

Gate Reverse Current

VGs=20V, VOS=O
I TA= lS0·C

BVGSS

Gate-Source Breakdown Voltage

VGS(off) Gate-Source Cutoff Voltage
VOS(on)

Drain-Source ON Voltage

IG=lp.A, VOS=O

30

VOS= -lSV, 10= -lp.A

S

VGS=O, 10= -lSmA (U304),
10= -7mA (U30S),
10 = - 3mA (U306)

loss

Saturation Drain Current (Note 1)

VOS= -lSV, VGS=O

10(Off)

Drain Cutoff Current

VOS= -lSV, VGS= 12V (U304)
VGS = 7V (U30S)
VGs=5V(U306)

Max

U30S
Min

U306
Min

Units

Max

SOO

SOo

SOO

pA

1,0

1.0

1,0

p.A

30

30
10

3

-1,3
-30

Max

-90

6

1

-0,8
-lS

-60

4

V

-0,6
-S

-2S

mA

-SOO

-SOO

-SOO

pA

-1.0

-1,0

-1.0

p.A

rOS(on)

Static Drain-Source ON Resistance VGS=OV, 10= -lmA

8S

110

17S

rds(on)

Drain-Source ON Resistance

8S

110

17S

n
n

ITA=lS0·C

VGs=OV,lo=O

I f= 1kHz

INTERSIL'S SOLE AND EXCLUSIVE WARRANTV OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTV ARTICLE OF THE CONDITION OF SALE,
THE WARRANTV SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILlTV AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but a~ not 18stsd.

10·104

.D~Do..

U304-U306
ELECTRICAL CHARACTERISTICS
Symbol

...
I

(Continued) (TA = 25°C unless otherwise specified)

Parameter

U304

Teat Condltlona

C

U30S

U308

It

Units

Min Max Min Max Min Max
Clss
Cras

f=1MHz

Common-Source Input Capacitance
(Note 2)

Vos= -15V,

Common-Source Reverse Transfer
Capacitance (Note 2)

Vos=O, VGs=12V
(U304)
VGS=7V
(U305),
VGs=5V
(U306)

VGS=O

27

27

7

7

7

25

U306

-10V

-6V

-6V

20

25

t,

Rise Time (Note 2)

VGS(off) 12V

tcI(off)

Turn-OFF Delay Time (Note 2)

RL

tf

Fall Time (Note 2)

VGS(on) 0

5800

7V

5V

15

25

35

7430

18000

10

15

20

0

0

25

40

60

-15mA -7mA

oCII

pF

,

U305

Voo

10(on)

27

U304
Turn-ON Delay Time (Note 2)

tcI(on)

cIt
o

ns

-3mA

NOTES: 1. Pulse test pulsewldth= 300"s, duty cycIes;3%.
2. For design reference only. not 100% tested.

III

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT BTATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR BTATUTORY, INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AD typIcsJ vsIuBs hBvs bSBn charBctsrIzBd but ars not tB8IBd.

10-105

~

D~DIb

U308-U310

~ N-Channel JFET

! High Frequency Amplifier
I')

:::I

FEATURES

ABSOLUTE MAXIMUM RATINGS

•
•
•
•

(TA = 25°C unless otherwise noted)
Gate-Drain or Gate-Source Voltage ............... - 25V
Gate Current ................................... 20mA
Storage Temperature ................ - 65°C to + 200"C
Operating Temperature Range ........ - 55°C to + 150"C
Lead Temperature (Soldering, 10sec) ........... + 300°C
Power Dissipation ............................. 500mW
Derate above 25°C ......................... 4mW

High Power Gain
Low Noise
Dynamic Range Greater Than 100dB
Easily Matched to 750. Input

PIN CONFIGURATIONS

rc

NOTE: Sfrflsses abovs those listed under ''Absolute Maximum RaUngs"
may cause permanent dafTJB{J9 to the device. These are stress ratings only
and functional operation of tha device at these or any othar conditions
abovs those indicated in the operational sections of tha specifications is not
implted. Exposure to absolute maximum rating conditions for extended perlods may affect device rellabilily.

T().52

ORDERING INFORMATION
TO·52
U30S
U309
U310

0265-1

5021

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown
Voltage

(TA = 25°C unless otherwise specified)
U30a

U309

U310

Min Typ Max

Min Typ Max

Min Typ Max

Test Conditions
VGS= -15V
VGS=O

TA=125°C

IG= -1p.A, VOS=O

VGS(off) Gate-Source Cutoff Voltage VOS= 10V, 10= 1nA
loss

Saturation Drain Current
(Note 1)

Vos=10V, VGS=O

VGS(f)

Gate-Source Forward
Voltage

IG=10mA, VOs=O

gig

Common-Gate Forward
Vos=10V,
Transconductance (Note 1) 10=10mA

gogs

Common Gate Output
Conductance

-150

-150

-150

pA

-150

-150

-150

nA

-25

-25

-25

-1.0

-6.0 -1.0

-4.0 -2.5

V

12

60

12

30

Cgd

Drain-Gate Capacitance

CgS

Gate-Source Capacitance

VGs= -10V, f=1MHz
(Note 2)
Vos=10V

en

Equivalent Short Circuit
Input Noise Voltage

Vos=10V,
10=10mA

10

f=100Hz
(Note 2)

10

17

10

-6.0

24

1.0

1.0

f=1kHz

Units

17

10

60

rnA

1.0

V

17

p.s

250

250

250

2.5

2.5

2.5

5.0

5.0

5.0

10

10

I-'s
pF
nV

.,1Hz

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIEs.. EXPRESS, IMPLIeD OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typicsl values have been charscterized but BI'8 not tested.

10-106

.U~O[l

U308-U310

cCot
o
CD

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

U30a

Test Conditions

C

Cot

U310

U309

Units

Min Typ Max Min Typ Max Min Typ Max
gIg

Common-Gate Forward
Transconductance

gogs

Common-Gate Output
Conductance

Gpg

Common-Gate Power Gain

f=100MHz
f=450MHz
Vos=10V, f= 100MHz
lo=10mA
f=450MHz

NF

Noise Figure

(Note 2)

15

15

15

14

14

14

0.18

0.18

0.18

0.32

0.32

",8

0.32

f= 100MHz

14

16

14

16

14

16

f=450MHz

10

11

10

11

10

11

dB

f=100MHz

1.5

2.0

1.5

2.0

1.5

2.0

f=450MHz

2.7

3.5

2.7

3.5

2.7

3.5

NOTES: 1. Pulse test duration ~ 2ms.
2. For design reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bHn characterized but are not tested.

10-107

.
I

(Continued) (TA = 25°C unless otherwise specified)

o

D~DIL

8 U401-U406

~I Dual N-Channel JFET Switch

...

~ FEATURES

~ •
•
•
•

ABSOLUTE MAXIMUM RATINGS

Minimum System Error and Calibration
Low Drift With Temperature
Operates From Low Power Supply Voltages
High Output Impedance

(TA = 25·C unless otherwise noted)
Gate-Drain or Gate-Source Voltage ................. 50V
Gate Current (Note 1) ..•......••.....••.....••.. 10mA
Storage Temperature Range .......... - 65°C to + 200°C
Operating Temperature Range ........ - 55°C to + 1500C
Lead Temperature (Soldering, 10sec) ........... +3000C

PIN CONFIGURATION

Power Dissipation (TA = 85°C)
Derate above 25°C .••.•.•

T()'71

One Side

Both Sides

300mW
2.6mW'oC

500mW
5mW'oC

NOTE: Stresses above those listsd under "Abs0/ut9 Maximum Ratings"
may cause permanent damage to the davic9. These Br9 slrBss ratings only
snd functional operation of the davic9 at these or any other conditions
aboV6 those indicatsd In the operationsl sections of the specifications is not
imp/i6d. Exposure to absolul8 maximum rating conditions for 9XI9nded periods may affect davic9 reliabiHty.

ORDERING INFORMATION

~
~

0266-1
6037

ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(TA = 25°C unless otherwise specified)

Test Conditions

U401
Min

BVGSS

Gate-Source Breakdown
Voltage

Vos=O,IG= -1,.A

IGSS

Gate Reverse Current
(Nots2)

Vos=O, VGS= -30V

VGS(off)

Gate-Source Cutoff Voltage Vos= 15V, 10= 1nA

VGS(on)

Gate-Source Voltage (on)

VOG=15V,10=200,.A

loss

Saturation Drain Current
(Note 3)

Vos=10V, VGS=O

IG

Operating Gate Current
(Note 2)

BVG1-G2 Gate-Gate Breakdown
Voltage

Max

-50

U402
Min

Max

-50
-25

U403
Min

Max

-50
-25

U404
Min

Max

-50
-25

U405
Min

Max

-25

V
-25

-.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5
-2.3

-2.3

-2.3

-2.3

-2.3

Units

Max

-50

-50
-25

U406
Min

pA
V

-2.3
10.0

mA

VDG = 15V, 10 = 200,.A

-15

-15

-15

-15

-15

-15

pA

TA=125°C

-10

-10

-10

-10

-10

-10

nA

Vos=O, VGS=O,
IG= ±1,.A

gfs

Common-Source Forward Vos=10V,
Transconductance (Note 3) VGS=O

90s

Common-80urce Output
Conductance

9fs

Common-Source Forward
Transconductance

gos

Common-Source Output
Conductance

G..

Common-Source Input
Capacitance (Note 6)

Crss

Common-80urce Reverse
Transfer Capacitance
(Note 6)

f=1kHz

0.5

10.0

±50

0.5

±50

f=1kHz

f=1MHz

0.5

10.0

±50

0.5

10.0

±50

0.5

10.0

±50

0.5

±50

V

2000 7000 2000 7000 2000 7000 2000 7000 2000 7000 2000 7000
20

VOG=15V,
10=200,.A

10.0

20

20

20

20

20

,.S

1000 2000 1000 2000 1000 2000 1000 2000 1000 2000 1000 2000
2.0

2.0

2.0

2.0

2.0

2.0

B.O

B.O

B.O

B.O

B.O

B.O
pF

3.0

3.0

3.0

3.0

3.0

3.0

INTERSIL·S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES. EXPRESS. IMPUED OR STATUTORY. INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bsBn chsractertzed but are not tesl6d.

10-108

.D~OIL

U401-U406

I

ELECTRICAL CHARACTERISTRICS (Continued) (TA = 25°C unless otherwise specified)
Symbol

Parameter

U401

Test Conditions

U402

U403

U404

C

U405

U406

Units

Min Max Min Max Min Max Min Max Min Max Min Max
en

Equivalent Short-Circuit
Input Noise Voltage

CMRR

Common-Mode Rejection Voo= 10 to2OV,
Ratio
10 = 200pA (Note 5, 6)

I VGS1- vGS21

Differential Gate-Source
Voltage

Voo=10V,lo=200pA

IAVGS1-VGS21

Gate-Source Voltage
Differential Drift (Note 4)

A=-550 C,
Voo-l0V, T = + 25°C
10=200pA T~=+125.C

.I.T

VOS-15V'lf-l0HZ
VGS=O
(Note 6)

20
95

-f

20
95

20

20
95

20

20

90

95

...
.

c
o
o

at

nV

THZ
dB

5

10

10

15

20

40

mV

10

10

25

25

40

80

"vrc

NOTES: I, Per transistor.
2. Approximately doubles for every 1000C increase in TA.
3. Pulse test duratlon=300"s; duty cycle ':3%.
4. Measured at end points, TA, TB, TC.
AVDD
5. CMRR =20 IOg10 [ A IVGS1-VGS2 I

1, AVoo=10V.

6. For design reference only, not 100% tested.

•
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typ/cB/ vsIuBs hBVtI b8en charsct6Iized but tlfB not tffIBted.

10-109

: U1897-U1899
; N-Channel JFET Switch
I

:; FEATURES

=·
:::» •

APPLICATIONS
• Analog Switches, Choppers

Low Insertion LOll
No Error or Offset Voltage Generated By Closed
Switch

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate·Drain or Gate·Source Voltage ............... -40V
Forward Gate Current ........................... 10mA
Storage Temperature Range .......... -55°C to + 150°C
Operating Temperature Range ........ -55°C to + 135°C
Lead Temperature (Soldering, 1Osee) ........... + 300°C
Power Dissipation ............................. 350mW
Derate above 25°C ....................... 3.2mWrC

PIN CONFIGURATION
TO·92

q

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended peri·
ods may affect device reliability.

D

S

ORDERING INFORMATION

G

0267-1

5001

TO·92

TO·92·18

U1897

U1897·18

U1898

U1898·18

U1899

U1899·18

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise specified)

Symbol

Test Conditions

Parameter

U1897
Min

BVGSS

Gate·Source Breakdown Voltage

IG= -1J.tA, VOs=O

IGSS

Gate Reverse Current

VGS= -20V, VOs=O

lOGO

Drain·Gate Leakage Current

ISGO
10(off)

-40

Max

-40

Min
-40

V
-400

VOG=20V,ls=0

200

200

200

Source·Gate Leakage Current

VSG=20V, 10=0

200

200

200

Drain Cutoff Current

Vos=20V,
VGS= -12V (U1897)

200

200

200

10

10

10

VGS(off) Gate·Source Cutoff Voltage
Saturation Drain Current (Note 1)

VOS(on) Drain·Source ON Voltage

Vos=20V,10=1nA

-5.0

Vos=20V, VGS=O

30

VGs=O,lo=S.SmA (U1897)
10=4.0mA (U1898)
10=2.5mA (U1899)

Static Drain·Source ON Resistance 10=1mA,VGs=0

-10

-2.0 -7.0· -1.0 -5.0
15

Units

Max

-400

I

rDS(on)

Min

U1899

-400

VGS= -8V (U1898~ TA=85°C
VGS= -SV (U1899)

loss

Max

U1898

pA

nA
V
mA

8.0

0.2

0.2

0.2

V

30

50

80

n

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valuss have bgen characterized but are not tested.

10·110

IIID~OIL

U1897-U1899

!i
CD

...

G

ELECTRICAL CHARACTERISTICS
Symbol

(Continued) (TA = 25°C unless otherwise specified)

Parameter

Test Conditions

U1897

I

U1898

U1899

Units

Drain-Gate Capacitance

VOG=20V,ls=0

5

5

Cag

Source-Gate Capacitance

VSG = 20V, 10=0

5

5

5

Cjss

Common-Source Input Capacitance

16

16

1B

Crss

Common-Source Reverse Transfer
Capacitance

3.5

3.5

3.5

15

15

20

10

20

40

td(on)

Turn ON Delay Time (Note 2)

tr

Rise Time (Note 2)

toll

Turn OFF Time (Note 2)

Vos=20V, VGS=O

f=lMHz
(Note 2)

Switching Time Test Conditions
Voo
VGS(on)
VGS(off)
RL
10(on)

U1897 U1898 U1899
3V
3V
3V
0
0
0
-12V
-8V
-BV
4250 7700 11200
B.BmA
4mA 2.5mA

5

pF

ns
40

BO

80

NOTES: 1. Pulse test pulsewidth~300"s; duty cycle<3%.
2. For design reference only. not 100% tested.

ImERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical values have been charscterized but are not tested.

10-111

CD

G
G

Min Max Min Max Min Max
Cda

...C

~ YCR2N/3P/4N/5P/7N'

i
ii;
CIt

~
&\I

a:
~

D~DI1.

Voltage Controlled Resistors

APPLICATIONS

ABSOLUTE MAXIMUM RATINGS

• Small Signal AUenuators

(TA = 25·C unless otherwise noted)
Gate-Drain or Gate-Source Voltage ................. 1SV
Gate Current •...............................•.• 10mA
Storage Temperature Range .......... -6S·C to + 200·C
Operating Temperature Range ........ -SS·C to + 175·C
Lead Temperature (Soldering. 10sec) ........... + 300·C
Power Dissipation ..•.......................... 300mW
Derate above 25·C ......................... 2mW/·C

• Filters
• Amplifier Gain Control
• OSCillator Amplitude Control

ORDERING INFORMATION
T0-18

T0-72

Wafer

Dice

VCR2N

-

VCR2N/W

VCR2N/D
VCR4N/D

VCR4N

-

-

VCR4N/W

VCR3P

VCR3P/W

VCR3P/D

VCR7N

VCR7N/W

VCR7N/D

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to /he device. These are stress ratings only
and fIInctional operation of /he device at these or any other conditions
above those indicated in the operational sactions of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PIN CONFIGURATIONS
TO·72
(P·Channel)
(VCR3P,5P)

T0-18
(VCR2N,7N)

0288-1

TO·72
(N·Channel)
(VCR,7N)

0288-4

0288-3

5001·VCR2N
5010(4N)-VCR4N
5510(5P)·VCR5P

5007·VCR7N
5008·VCR3P

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL 8E EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTe: All typ;csl valuBs have bHn characterized but are not tested.

10-112

VCR2N/3P/4N/5P/7N
ELECTRICAL CHARACTERISTICS

(TA = 25'C unless otherwise specified)

N Channel VCR FETs
Symbol

Parameter

Test Conditions

VCR2N
Min

Max

VCR4N
Min

Max

VCR7N
Min

Units

Max

STATIC
IGSS

Gate Reverse Current

VGs= -15V,
VOs=O

BVGSS

Gate-Source Breakdown Voltage IG= -1/LA,
VOs=O

-15

VGS(off)

Gate-Source Cutoff Voltage

10= 1/LA, VOS= 10V

1.0

3.5

-3.5

-7

-2.5

rds(on)

Drain source ON Resistance

VGS=O, 10=0

f= 1kHz

20

60

200

600

4,000 8,000

f=1MHz

-5

-0.2
-15

-0.1

nA

-15
V
-5
0

DYNAMIC (Note 1)
Cdgo

Drain-Gate Capacitance

VGO= -10V, Is=O

Csgo

Source-Gate Capacitance

VGS= -10V, 10=0

7.5

3

1.5

7.5

3

1.5

I

I

pF

NOTE 1: For design reference only, not 100% tested.

P Channel VCR FETS
VCR3P
Symbol

Parameter

VCR5P

Test Conditions

Units
Min

Max

Min

Max

STATIC
IGSS

Gate Reverse Current

VGs=15V, VOs=O

BVGSS

Gate-Source Breakdown Voltage

IG= 1/LA, VOs=O

15

20

10

nA

VGS(off)

Gate-Source Cutoff Voltage

10= -1/LA, VOS= -10V

1.0

5

3.5

7

rds(on)

Drain-Source ON Resistance

VGS=O, 10=0

f=1kHz

70

200

300

900

0

f=1MHz
(Note 1)

H1

pF

15
V

DYNAMIC (Note 1)
CdgO

Drain-Gate Capacitance

VGo=10V,ls=0

CSgO

Source-Gate Capacitance

VGS=10V, 10=0

NOTE 1: For design reference only, not 100% tested.

6
6

JFETS AS VOLTAGE REGULATORS
The voltage controlled resistor is a junction field effect
transistor whose drain to source ON resistance is controlled
by gate to source voltage.
The gate control terminal is high impedance thereby allowing negligible control current. The gate voltage is zero
for minimum resistance, and increases as the gate voltage
approaches the pinch-off voltage.
This VCR is intended for use on applications using low
level AC signals. Figure 1 shows the output characteristics,
with an enlarged graph of VDS=O for AC signals with no
DC component. Operation is in the first and third quadrants;
the device will operate in the first quadrant only if a constant

current is applied to the drain and the input signal level is
kept low.
Figure 1 also shows that certain combinations of gate
control voltage and signal levels will cause resistance modulation. This distortion may be improved by introducing local
feedback as shown in figure 2 for best frequency response
and impedance levels; eliminating the feedback capacitor
will require the gate control voltage to be double for the
same ON resistance. The resistor values should be equal,
and about 1000.
Best gate control voltage for best linearity is up to about
0.8VPK; ON resistance increases rapidly beyond this point.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN typioBI values have been chsracteriztJd but are not 19Sted.

10-113

;!: VCR2N/3P/4N/5P/7N

~
II)

"z

30

~

Vos

=ov

Vos

=

Vos

= -4'1

~

"'"z

20

-2V

(II

a:

~

10

Vos. -6V

3
//

..

5

vOS= -8V

8

7

8

9

10

VDS·VOLTS

/
//

VI-i-+-=

v //
/

/

/

/

JFET OUTPUT CHARACTERISTICS

/

rnA
JFET OUTPUT CHARACTERISTICS
ENLAROED AROUND Vos - 0
0268-10

Figure 1

R

GATE CONTROL 0--"1/..,.,.....--+1

0268-11

Figure 2

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE All typical values have been characterized but are not tested

10·114

VCR11N
Voltage Controlled Resistors
APPLICATIONS

ABSOLUTE MAXIMUM RATINGS

• Small Signal Attenuators

(TA = 25'C unless otherwise noted)
Gate·Drain or Gate·Source Voltage ................. 25V
Gate Current ................................... 10mA
Total Device Dissipation at T A = 25'C
(Derate at 2.0mW /'C to 175'C) ............... 300mW
Storage Temperature Range .......... - 55'C to + 175'C

• Filters
• Amplifier Gain Control
• Oscillator Amplitude Control

PIN CONFIGURATION

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device, These are stress ratings only

and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TO·71

ORDERING INFORMATION

0269-1

6019

ELECTRICAL CHARACTERISTICS
Symbol

(TA = 25'C unless otherwise specified)

Characteristic

Test Conditions

Min

Max

Units

-0.2

nA

IGSS

Gate Reverse Current

VGS= -15V, VDS=O

BVGSS

Gate·Source Breakdown Voltage

IG= -1fLA, VDS=O

-25

VGS(off)

Gate·Source Cutoff Voltage

10= 1fLA, VOS= 10V

-8

-12

100

200

rds(on)

Drain Source ON Resistance

VGS=O, 10=0

f=1kHz

Cdgo

Drain·Gate CapaCitance (Note 2)

VGO= -10V, Is=O

f=1MHz

CSQO

Source-Gate Capacitance (Note 2)

VGS= -10V, 10=0

rosmin
rOsmax

V

8

0
pF

8

Vos=100mV

rOS1 =2000

.95

1

VGS1=VGS2

rOS1=2kO

.95

1

NOTES: 1. VGS1 + Control Voltage necessary to force ros to 200n or 2kn.
2. For deSign reference only, not 100% tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WAARANTY SHAll BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

10·115

Section 11 -

Data Communications
IM26C91 .............. 11-1
IM4702/4712 ......... 11-19
IM6402 .............. 11-26
IM6403 .............. 11-26
ICL232 ............... 11-36

•

D~DlL!n

IM26C91
Universal Asynchronous Rec
Transmitter (UART)
GENERAL DESCRIPTION

...o

• ",,'u\q,{"

The IM26C91 is a high-performance U
ronous Receiver/Transmitter that provides f
opera8 fixed baud
tion. Operating speed can be selected fr
rates ranging from 50 to 38.4K baud, or from an internal
programmable counter/timer (16 x clock speed), or from
an external 1 x or 16 x clock. The ability to program the
operating speed independently makes the UART particularly well suited for dual-speed channel applications, e.g. clustered terminal systems.
The quadruple buffered receiver minimizes potential receiver overrun and reduces overhead in interrupt driven systems. Handshaking capability disables a remote UART
transmitter when the receiver buffer is full.
The IM26C91 UART is fabricated in 1.5 micron advanced
VLSI CMOS technology which permits monolithic construction and encapsulation in a 0.3" wide 24-pin DIP. The device is TTL compatible and operates from a single + 5V
power supply.

• Programmable Data Format:
-5 to 8 Data Bits Plus Parity
-Odd, Even, no Parity or Force Parity
-1,1.5 or 2 Stop Bits Programmable In y,. Bit
Increments
• Parity, Framing, and Overrun Error Detection
• False Start Bit Detection
• Line Break Detection and Generation
• Programmable Channel Mode
-Normal (Full-Duplex)
-Automatic Echo
-Local Loopback
-Remote Loopback
• Single Interrupt Output with Seven Maskable
Interrupting Conditions
• On-Chip Crystal OSCillator
• 300 mil 24 Pin DIP

ORDER INFORMATION
Vee

~

5V ±10%

Part
Number

Temperature
Range

Package

IM26C91CX24

O'to +70'C

24 Lead Plastic

III
XI/eLK

0104-2

Figure 1: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

11 ~ 1

126091-002
March 1987

.O~OIL

.. IM26C91

§
!"

ABSOLUTE MAXIMUM RATINGS
Voltage from Vee to GND (Note 1) ..•..•.. -0.3 to +6.0V
Voltage from any Pin
to GND (Note 1) ................. -0.3 to Vee ±10% V
Power Dissipation ................................ 0.2W
Operating Temperature Range (Note 2) .•... O'C to + 70'C
Storage Temperature Range ........... -65'Cto + 150'C

RON
RX!)

Vee
WRN

TX1l

DO
DI
D2
D.l
D4

WPO

WA
A2

AI
AD

NOTE: SIr9SSIJS above those listed under "Absolute Max/mum Ratings"
may caus" f)9fmaflBnt defTl8gfl to the devfc9. Th9S9 are stress ratings only
and functionsl operation of the devfc9 at these or any other conditions
above these Indicated In the operational sections of the specificstions Is not
Implied. Exposure to sbsolute maximum rating conditions for 6Xfended perl.
ods may aff"ct deviCB raliability.

D5

X1/Cl!

DB

X2

D7

RESET

CEH

GlID

INTRN

0104-1

Top View
Figure 2: Pin Configuration

ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
Symbol

TA = O'Cto +70'C, Vee = 5.0V ±10% 3,4,5
Limits

Test Conditions

Parameter

Min
VIL

Input low Voltage

VIH

Input High Voltage
Ali Except XI /ClK
Xl/ClK

VOL

Output low Voltage (Note 6)

VOH

Output High Voltage (Note 6)
(Except Open Drain Outputs)

IlL

Input leakage Current

IILL

Data Bus 3·State leakage Current

100

Open Drain Output leakage Current

IX1L

Xl/ClK low Input Current

XI /ClK High Input Current
IX1H
OSCILLATOR IN POWER DOWN MODE:

10L

=

Units

Typ

Max

-0.3

O.S

V

2.0
0.9 Vee

Vee
Vee

V
V

2.4mA

= -400",A
= OtoVee
Vo = 0.4 to Vee
Vo = 0.4 to Vee
VIN = 0, X2 Floated
VIN = Vee, X2 Floated
10H

2.4

VIN

-10

10

",A

-10

10

",A

-10

10

",A

=

IX1H

XI /ClK High Input Current

VIN

IX2L

X2 low Output Current

VOUT

IX2H
Icc

X2 High Output Current
Power Supply Current
Standby

VOUT

V

-100

-30

0.0

",A

0.0

+30

100

",A

Vee, X2 Floated

10

mA

=
=

0, Xl/ClK = Vee

100

",A

Vee, Xl/ClK = OV

100
20
500

",A
mA
",A

NOTES: 1: This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge.
Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maximums.
2: For operating at elevated temperatures. the device must be derated based on

+ 150'C maximum junction temperature.

3: Parameters are valid over specified temperature range.
4: All voltage measurements are referenced to ground (GNO). For testing. all input signals swing bstween 0.4V and 2.4V with a transition time of 20 ns
maximum. For X1/CLK, this swing Is between O.4V and 4.4V. All time measurements are referenced at input voltages of O.BV and 2.0V and output
voHages of O.SV and 2.0V as appropriate.
5: Typical values are at

+ 25'C. typical supply voltages. and typical processing parameters.

6: Tesl condition for outputs: CL

= 150 pF. except Interrupt outputs. Test conditions for Interrupt outputs: CL = 50 pF. RL

= 2.7K II to Vcc.

7: Timing is illustrated and referenced to the WRN and RON inputs. The device may also bs operated with CEN as the 'strobing' input. In this case. all
timing specifications apply referenced to the falling and rising edges of CEN. CEN and RON (also CEN and WRN) are OR'ed Internally. As a
consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle.
8: If CEN is used as the 'slrobing' input. this parameter defines the minimum high time between one CEN and the next. The RON signal must bs negated
for tRWD to guarantee that any status register changes are valid.

9: Consecutive write operations to the same command require at least three edges of the XI clock between writes.
INTERSIL'S SOLE AND EXClUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONomON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLlEO WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTiCULAR USE.
NOTE: All typical vaJuss havs been chsrscterlzsd buisre not tssttH:I.

11-2

.D~On.

IM26C91
AC ELECTRICAL CHARACTERISTICS
Symbol

TA

=

O'Cto +70'C VCC

=

...

Tentative Limits
Min

Typ

N
GI

~

, , ,6
50V ±10% 345

Parameter

i

Units
Max

RESET TIMING (Figure 3)
tRES

RESET Pulse Width

1.0

/,S

BUS TIMING (Figure 4) (Note 7)
tAS

AO-A2 Set-Up Time to RON, WRN Low

10

ns

tAH

AO-A2 Hold Time from RON, WRN High

0

ns

tcs

CEN Set-Up Time to RON, WRN Low

0

ns

tCH

CEN Hold Time from RON, WRN High

0

ns

tRW

WRN, RON Pulse Width

225

ns

too

Data Valid after RON Low

175

ns

tOF

Data Bus Floating after RON High

100

ns

tos

Data Set-Up Time before WRN High

100

ns

tOH

Data Hold Time after WRN High

10

ns

tRWO

Time Between READs and lor WRITEs (Note 9)

200

ns

ns

MPI AND MPO TIMING (Figure 5) (Note 7)
tps

MPllnput Set-Up Time before RON Low

0

tpH

MPllnput Hold Time after RON High

0

tpo

MPO Output Valid after WRN High

ns
370

ns

370
370
370
370
370
270

ns
ns
ns
ns
ns
ns

4.0

MHz

4.0

MHz

2.0
1.0

MHz
MHz

2.0
1.0

MHz
MHz

INTERRUPT TIMING (Figure 6)
tlR

INTRN Negated:
Read RHR (RXRDY IFFULL Interrupt)
Write THR (TXRDY ITXEMT Interrupt)
Reset Command (Break Change Interrupt)
Reset Command (MPI Change Interrupt)
Stop CIT Command (Counter Interrupt)
Write IMR (Clear of Interrupt Mask Bit)

CLOCK TIMING (Figure 7)
tCLK

Xl ICLK High or Low Time

100

fCLK

Xl/CLK Frequency

2.0

tCTC

Counter ITimer Clock High or Low Time

100

fCTC

CounterITimer Clock Frequency

tRX

RXC High or Low Time

fRX

RXC Frequency

tTX

TXC High or Low Time

f-rx

TXC Frequency

0

ns
3.6864

ns

ns

220

(16X)
(lX)

0
0

ns

220

(16X)
(lX)

0
0

TRANSMITTER TIMING (Figure 8)
trxo

TXD Output Delay from TXC Low

tTCS

TXC Output Delay from TXD Output Data

0

350

ns

150

ns

RECEIVER TIMING (Figure 9)
tRXS

RXD Data Set-Up Time to RXC High

240

ns

tRXH

RXD Data Hold Time from RXC High

200

ns

INTERSIL S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typIcs/ values have been characterized but are not tested.

11-3

a

IID~OIL

; IM26C91

V
ft

!

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UARn
PIN DESCRIPTION
Mnemonic

DIP
Pin No.

Type

Name and Function

00·07

22-15

I/O

Data Bus: Active high B·bit bidirectional three· state data bus. Bit 0 is the LSB and bit 7 is
the MSB. Handles all data, command, and status transfers between the CPU and the
UART. Transfer direction is controlled by the WRN and RON inputs when the CEN input
is low. When the CEN input is high, the data bus is in the three-state condition.

CEN

14

I

Chip Enable: Active low input. When low, data transfers between the CPU and the UART
are enabled on 00-07 as controlled by the WRN, RON and AO-A2 inputs. When CEN is
high, the UART is effectively isolated from the data bus and 00-07 are placed in the
three-state condition.

WRN

23

I

Write Strobe: Active low input. A low on this pin while CEN is low, causes the contents
of the data bus to be transferred to the register selected by AO-A2. The transfer occurs
on the trailing (rising) edge of the signal.

RON

1

I

Read Strobe: Active low input. A low input, while CEN is low, causes the contents of the
register selected by AO-A2 to be placed on the data bus. The read cycle begins on the
leading (falling) edge of RON.

AO-A2

B-6

I

Address Inputs: Active high address inputs select the UART registers for read/write
operations.

INTRN

13

0

Interrupt Request: This active low output is asserted by one or more of seven maskable
interrupting conditions. The CPU can read the interrupt status register to determine the
interrupting condition(s).

X1/CLK

9

I

Crystal 1: Crystal or external clock input. When using the crystal oscillator, this pin
serves as the connection for one side of the crystal. If a crystal is not used, an external
clock is supplied at this input. An external clock (or cyrstal) is required even if the internal
baud rate generator is not utilized. This clock is used to drive the internal baud rate
generator, as an optional input to the timer/counter, and to provide other clocking signals
required by the chip.

X2

10

0

Crystal 2: Connection for other side of crystal. If an external source is used instead of a
crystal this connection should be open.

RXO

2

I

Receiver Serial Data Input: The least significant bit is received first. If external receiver
clock is specified, this input is sampled on the rising edge of the clock.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typIcsI values have bssn chsracteriztJd but Sf(J not tested.

11-4

IM26C91
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
PIN DESCRIPTION

(Continued)

DIP
Pin No.

Type

Name and Function

TXD

3

0

Transmitter Serial Data Input: The least significant bit is transmitted first. This output is
held in the marking (high) condition when the transmitter is idle or disabled and when the
UART is operating in localloopback mode. If external transmitter clock is specified, the
data is shifted on the falling edge of the transmitter clock.

MPO

4

0

Multi-Purpose Output: One of the following functions can be selected for this output pin
by programming the auxiliary control register.
RTSN-Request to send active low output. This output is asserted and negated via the
command register. By appropriate programming of the mode registers, RTSN can be
programmed to be automatically reset after the character in the transmitter is completely
shifted or when the receiver FIFO and shift register are full.
CXTo-The counter/timer output.
TXC1X-The 1 x clock for the transmitter.
TXC16X-The 16 x clock for the transmitter.
RXC1X-The 1 x clock for the transmitter.
RXC16X-The 16 x clock for the transmitter.
TXRDY-The transmitter holding register empty Signal. Active low interrupt.
RXRDY/FFULL-The receiver FIFO not empty/full signal. Active low interrupt.

MPI

5

I

Multi-Purpose Input: This pin can be programmed to serve as an input for one of the
following functions:
GPI-General purpose input. The current state of the pin can be determined by reading
the ISA.
CTSN-Glear-to-Send active low input.
CTCLK-Gounter/Timer external clock input.
RTCLK-Receiver and/or transmitter external clock input. This may be a 1 x or 16 x
clock as programmed by CSR [3:0] or CSR [7:4].

Vee

24

I

Power Supply:

GND

12

I

Ground.

Mnemonic

+ 5V supply input.

•
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical va/USB have bHn chBract6rizsd but ars not testlld.

11-5

:;; IM26C91

()
C&)

COl

!

After the stop bit is detected, the receiver will immediately
look for the next start bit. However, if a non-zero character
was received without a stop bit (i.e. framing error) and RXD
remains low for one-half of the bit period after the stop bit
was sampled, then the receiver operates as if a new start bit
transition had been detected at that point. The parity error,
framing error and overrun error (if any) are strobed into the
SR at the received character boundary, before the RXRDY
status bit is set.
If a break condition is detected, (RXD is low for the entire
character including the stop bit) only one character consisting of all zeros will be loaded into the FIFO of the RHR and
the received break bit in the SR is set to 1. The RXD input
must return to a high condition for two successive clock
edges of the 1X clock (internal or external) before a search
for the next start bit begins.
Data entering the RHR is stored in a first-in-first-out
(FIFO) queue with a capacity of three characters. Data is
loaded from the Receive Shift Register into the top-most
empty position of the FIFO.
The RXRDY bit in the Status Register (SR) is set whenever one or more characters are available to be read, and a
FFULL status bit is set if all three queue positions are filled
with data. Either of these bits can be selected to cause an
interrupt. A read of the RHR outputs the data at the top of
the FIFO. After the read cycle, the data FIFO and its associated status bits are 'popped', thus emptying a FIFO position
for new data.
In addition to the data word, three status bits (parity error,
framing error, and received break) are appended to each
data character in the FIFO. Status can be provided in two
ways, as programmed by the error mode control bit in the
mode register. In the character mode, status is provided on
a character-by-character basis: the status applies only to
the character at the top of the FIFO. In the block mode, the
status provided in the SR for these three bits is the logical
OR of the status for all characters coming to the top of the
FIFO since the last reset error command was issued. In
either mode, reading the SR does not affect the FIFO. The
FIFO is 'popped' only when the RHR is read. Therefore, the
SR should be read prior to reading the corresponding data
character.
If the FIFO is full when a new character is received, that
character is held in the Receive Shift Register until a FIFO
position is available. If an additional character is received
while this state exists, the contents of the FIFO are not
affected: the character previously in the shift register is lost
and the overrun error status bit (SR (41) will be set upon
receipt of the start bit of the new (overrunning) character.
Wake Up Mode-In addition to the normal transmitter and
receiver operation described above, the UART incorporates
a special mode which provides automatic wake-up of the
receiver through address frame recognition for multiprocessor communications. This mode is selected by programming bits MR1[4:3) to '11'.
In this mode, a 'master' station transmits an address
character followed by data characters for the addressed
'slave' station. The slave stations, whose receivers are normally disabled, examine the received data stream and
'wake-up' the CPU (by setting RXRDY) only upon receipt of

CIRCUIT DESCRIPTION
The IM26C91 UART is a full duplex asynchronous receiver /transmitter whose operating frequency can be selected
from its internal baud rate generator or counter/timer, or
from an external input.
The functional diagram of the IM26C91 UART is shown in
Figure 1. It consists of the receiver and transmitter, a data
bus buffer, an interrupt control, an operation control and a
timing system. In addition, a multi-purpose input pin can be
programmed to serve as an output for a variety of internal
functions, including a request-to-send output, the counter/
timer output, the output for the 1X or 16X transmitter or
receiver clocks, the TXRDY output or RXRDY /FFULL output (see pin description table).
Registers associated with the communications channel
are the Mode Registers, (MR1 and MR2) ,the Clock Select
Register (CSR), the Command Register (CR), the Status
Register (SR), the Transmit Holding Register (THR), and the
Receiver Holding Register (RHR).

TRANSMITTER
The transmitter accepts parallel data from the CPU and
converts it to a serial bit stream on the Transmit Serial Data
Output pin (TXD). It automatically sends a start bit followed
by the programmed number of data bits, an optional parity
bit, and the programmed number of stop bits. The least significant bit is sent first.
Following the transmission of the stop bits, if a new character is not available in the THR, the TXD output remains
high and a TXEMT bit in the SR will be set to 1.
Transmission resumes and the TXEMT bit is cleared
when the CPU loads a new character into the THR. In the
16X clock mode, this also resynchronizes the internal 1X
transmitter clock so that transmission of the new character
begins with minimum delay.
The transmitter can be forced to send a break (continuous low condition) by issuing a start break command via
the CR. The break is terminated by a stop break command.
If the transmitter is disabled, it continues operating until
the character currently being transmitted and the character
in the THR, if any, are completely sent out. Characters cannot be loaded into the THR while the transmitter is disabled.

RECEIVER
The receiver accepts serial data on the RXD pin, converts
it to parallel format, checks for start bit, stop bit, parity bit (if
any), or break condition, and presents the assembled character to the CPU.
The receiver looks for a high-to-Iow (mark-to-space) transition of the start bit on the RXD input pin. If a transition is
detected, the state of the RXD is sampled again each 16X
clock for 71f:, clocks (16X clock mode) or at the next rising
edge of the bit-time clock (1 X clock mode). If RXD is sampled high, the start bit is invalid and the search for a valid
start bit is resumed. If RXD is still low, a valid start bit is
assumed and the receiver continues to sample the input at
one bit-time intervals until the proper number of data bits
and the parity bit (if any) have been assembled, and one
stop bit has been detected. The data is then transferred to
the RHR and the RXRDY bit in the SR is set to a 1. If the
character length is less than eight bits, the most significant
unused bits in the RHR are set to zero.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bsen characterized but alVJ not tested.

11-6

IM26C91
Mode registers 1 and 2 are accessed via an auxiliary pointer. The pOinter is set to MR1 by RESET or by issuing a reset
pointer command via the command register. Any read or
write of the mode register while the pointer is at MR1
switches the pointer to MR2. The pointer then remains at
MR2 so the subsequent accesses are to MR2, unless the
pOinter is reset to MR1 as described above.

RECEIVER (Continued)
a received address character. The CPU compares the received address to its station address and enables the receiver if it wishes to receive the subsequent data characters. Upon receipt of another address character, the CPU
may disable the receiver to initiate the process again.
A transmitted character consists of a start bit, the programmed number of data bits, an address/data (AID) bit,
and the programmed number of stop bits. The polarity of
the transmitted AID bit is selected by the CPU by programming bit MR1 [2]. A zero transmitted in the AID bit position
identifies the corresponding data bits as data; A one in the
AID bit position identifies the corresponding data bits as an
address. The CPU should program the Mode Register prior
to loading the corresponding data bits into the THA.
While in this mode, the receiver (whether enabled or disabled) continuously looks at the received data stream. If the
receiver is disabled, it sets the RXRDY status bit and loads
the character into the RHR FIFO if the received AID bit is a
one, but discards the received character if the received A/D
bit is a zero. If enabled, all received characters are transferred to the CPU via the RHA. In either case, the data bits
are loaded into the data FIFO while the AID bit is loaded
into the status FI FO position normally used for parity error
(SR[S]). Framing error, overrun error, and break detect operate normally whether or not the receiver is enabled.

A single interrupt output (lNTRN) is provided. It is asserted by any of the following internal events:
-Transmit holding register ready
-Transmit shift register empty
-Receive holding register ready or FIFO full
-Change in break received status
-Counter reached terminal count
-Change in MPI input
-High level at the MPI input
Associated with the interrupt system are the interrupt
mask register (IMR) and the interrupt status register (ISR).
The IMR can be programmed to select only certain of the
above conditions to cause INTRN to be asserted. The ISR
can be read by the CPU to determine all currently active
interrupt conditions. However, the bits of the ISR are not
masked by the IMR.

OPERATION CONTROL

Timing Circuits

Interrupt Control

The timing block consists of a crystal oscillator, a baud
rate generator, a programmable 16-bit counter/timer, and
two clock selectors.
The crystal oscillator operates directly from a 3.6664
MHz crystal connected across the X1/CLK and X2 inputs.
An external clock of the appropriate frequency may be conneted to X1/CLK. If an external clock is used instead of a
crystal, X1/CLK is driven by a configuration similar to the
one in Figure S. However, the input-high voltage must be
capable of attaining 4.4V. The clock serves as the basic
timing reference for the baud rate generator (BRG), the
counter/timer and other intemal circuits. A clock frequency,
within the limits specified in the electrical specifications,
must be supplied even if the internal BRG is not used.
The baud rate generator operates from the oscillator or
external clock input and is capable of generating 18 commonly used data communications baud rates ranging from
SO to 38.4k baud. Thirteen of these are available simultaneously for use by the receiver and transmittar. Eight are
fixed, and one of two sets of five can be selected by programming ACR[7]. The clock outputs from the BRG are at
16X the actual baud rate. The counter/timer can be used as
a timer to produce a 16X clock or any other baud rate by
counting down the crystal clock or an external clock. The
clock selectors allow the independent selection by the receiver and transmitter of any of these baud rates or an external timing signal.
The CounterlTlmer operation is programmed by
ACR[6:4]. One of eight timing sources can be used as the
input to the CIT. The output of the CIT is available to the
clock selectors and can also be programmed by ACR[2:0],
to be output on the MPO pin.

The Operation Control logic receives operation commands from the CPU and generates appropriate signals to
internal sections of the UART to control its operation. It contains address decoding and read and write circuits to permit
communications with the microprocessor via the data bus
buffer. The functions performed by the CPU read and write
operations are shown in Table 1.
Table 1. Register Addressing
READ
WRITE
AO

A2

A1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

(RON

0
1
0
1
0
1
0
1

= 0)

MR1, MR2
SR
Reserved·
RHR
Reserved·
ISR
CTU
(CTL)

(WRN

= 0)

MR1, MR2
CSR
CR
THR
ACR
IMR
CTUR
CTLR

'Reserved registers should never be reed during normal operation since
they are reserved for internal diagnostics.

ACR CR
CSR CTL
CTLRCTU CTUR MR
SR
THR RHR -

Auxiliary control register
Command register
Clock select register
Counter/timer lower
Counter/timer lower register
Counter/timer upper
Counter/timer upper register
Mode Register A
Status register
Transmit holding register
Receiver holding register

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY DBLIGATlON WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCWSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPREss. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN typIcsJ ..fuss Ita"" bssn _

but.", not "",/lid.

11-7

•

:,; IM26C91

(,)

co
&\I

!

OPERATION CONTROL

REGISTERS

(Continued)
In the timer mode, the CIT generates a square wave
whose period is twice the number of clock periods loaded
into the CIT upper and lower registers (CTUR and CTlR).
The counter ready bit in the ISR is set once each cycle of
the square wave. If the value of CTUR or CTlR is changed,
the current half-period will not be affected, but subsequent
half-periods will be affected. In this mode the CIT runs continuously and does not recognize the stop counter command (the command only resets the counter ready bit in
the ISR). Receipt of a start CIT command cause the counter to terminate the current timing cycle and to begin a new
cycle using the values in CTUR and CTlR.
In the counter mode, the CIT counts down the number of
pulses loaded into CTUR and CTlA. Counting beings upon
receipt of a start CIT command. Upon reaching terminal
count, the counter ready bit in the ISR is set. The counter
continues counting past the terminal count until stopped by
the CPU. If MPO is programmed to be the output of the CIT,
the output remains high until terminal count is reached, at
which time it goes low. The output returns to the high state
and the counter ready bit is cleared when the counter is
stopped by a stop counter command. The CPU may
change the values of CTUR and CTlR at any time, but the
new count becomes effective only on the next start counter command following a stop counter command. If new
values have not been loaded, the previous count values are
preserved and used for the next count cycle.
In the counter mode, the current value of the upper and
lower 8 bits of the counter may be read by the CPU. It is
recommended that the counter be stopped when reading to
prevent potential problems which may occur if a carry from
the lower 8 bits to the upper 8 bits occurs between the
times that both halves of the counter are read. However a
subsequent start counter command causes the counter to
begin a new count cycle using the values in CTUR and
CTlA.
Multi-Purpose Input Pin-The MPI can be programmed
as input to one of several UART circuits. The function of the
pin is selected by programming the appropriate control register (MR2[4], ACR[6:4], CSR[7:4], 3:0]). Only one of the
functions may be selected at any given time. If CTS pr GPI
is selected, a change-of-state detector provided with the pin
is activated. A high-to-Iow or low-to-high transition of the
inputs lasting longer than 25-50 JA-sec sets the MPI changeof-state bit in the interrupt status register. The bit is cleared
via a command. The change-of-state can be programmed
to generate an interrupt to the CPU by setting the corresponding bit in the interrupt mask register.
The input pin pulse detection circuitry uses a 38.4 kHz
sampling clock derived from one of the baud rate generator
taps. This produces a sampling period of slightly more than
25 JA-sec (assuming a 3.6864 MHz oscillator input). The detection circuitry, in order to guarantee that a true change in
level has occurred, requires that two successive samples at
the new logic level be observed. Consequently, the minimum duration of the signal change is 25 JA-sec if the transition occurs coincident with the first sample pulse. The
50 JA-sec time refers to the condition where the change-ofstate is just missed and the first change-of-state is not detected until after an additional 25 JA-sec.

The operation of UART is programmed by writing control
words into the appropriate register. Operational feedback is
provided via status registers which can be read by the CPU.
Addressing of the registers is as described in Table 1.
The contents of certain control registers are initialized to
zero on RESET. Changing the contents of a register during
operation may cause operation problems- e.g., changing
the number of bits per character while the transmitter is
active may cause the transmission of an incorrect character. The contents of the MR, the CSR, and the ACR should
only be changed while the receiver(s) and transmitter(s) are
disabled, and certain changes to the ACR should only be
made while the CIT is stopped.
The bit formats of the UART registers are depicted in Table 2 and described below.

MR1-Mode Register 1
MRI is accessed when the MR pOinter points to MRI.
The pOinter is set to MRI by RESET or by a set pOinter
command applied via the CR. After reading or writing MR1,
the pointers are set at MR2.
MR1[7]-Recelver Request-To-Send Control. This bit
controls the deactivation of the RTSN output (MPO) by the
receiver. This output is manually asserted and negated by
commands applied via the Command Register. A "1" in
MRI [7] causes RTSN to be automatically negated upon receipt of a valid start bit if the receiver FIFO is full. RTSN is
reasserted when an empty FIFO position is available. The
feature can be used to prevent overrun in the receiver by
using the RTSN output signal to control the CTS input of the
transmitting device.
MRI [5]-Receiver Interrupt Select. This bit selects either the receiver ready status (RXRDY) or the FIFO full
status (FFUll) to be used for CPU interrupts.
MRI [5]-Error Mode Select. This bit selects the operating mode of the three FIFOed status bits (FE, PE, received
break). In the character mode, status is provided on a character-by-character basis (the status applies only to the character at the top of the FIFO). In the block mode, the status
provided in the SR for these bits is the accumulation (logical
OR) of the status for all characters coming to the top of the
FIFO since the last reset error command was issued.
MRI [4:3]-Parity Mode Select. If "with parity" or "force
parity" is selected, a parity bit is added to the transmitted
character and the receiver performs a parity check on incoming data. If MRI [4:3] = 11, the channel operates in the
special wake-up mode.
MRI [2]-Parity Type Select. This bit selects the parity
type (odd or even) if the "with parity" mode is programmed
by MRI [4:3], and the polarity of the forced parity bit if the
"force parity" mode is programmed. It has no effect if the
"no parity" mode is programmed. In the special wake-up
mode, it selects the polarity of the AID bit.
MR 1[1 :O]-Bits-Per-Character Select. This field selects
the number of data bits per character to be transmitted and
received. The character length does not include the start,
parity, and stop bits.

INTERSIL'S SCLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characf6rlzed but are not tested.

11-8

IM26C91
7. A received break is echoed as received until the next
valid start bit is detected.
When switching in and out of the various modes, the selected mode is activated immediately upon mode selection,
even if this occurs in the middle of a received or transmitted
character. Similarly, if a mode is deselected, the device will
switch out of the mode immediately. An exception to this is
switching out of auto echo or remote loopback modes; if the
deselection occurs just after the receiver has sampled the
stop bit (indicated to be in auto-echo by assertion of
RXRDY), and the transmitter is enabled, the transmitter will
remain in auto echo mode until one full stop bit has been
retransmitted.
MR2[5]-Transmitter Request-to-Send Control. This
bit controls the deactivation of the RTSN output (MPO) by
the transmitter. This output is manually asserted and negated by appropriate commands issued via the command register. If MR2[5] = 1, RTSN is reset automatically one bit
time after the character in the transmit shift register and in
the THR (if any) are completely transmitted; includes the
programmed number of stop bits if the transmitter is not
enabled. This feature can be used to automatically terminate the transmission of a message as follows:
1. Program auto-reset mode (MR2[5] = 1).
2. Enable transmitter.
3. Assert RTSN via command.
4. Send message.
5. Verify the next-to-Iast character of the message is being
sent by waiting until transmitter ready is asserted. Disable transmitter after the last character is loaded into
the THR.
6. The last character will be transmitted and RTSN will be
reset one bit-time after the last stop bit.
MR2[4]-Clear-to-Send Control. The state of this bit
determines if the CTSN input (MPI) controls the operation of
the transmitter. If this bit is 0, CTSN has no effect on the
transmitter. If this bit is a 1, the transmitter checks the state
of CTSN each time it is ready to send a character. If it is
asserted (low), the character is transmitted. If it is negated
(high), the TXD output remains in the marking state and the
transmission is delayed until CTSN goes low. Changes in
CTSN while a character is being transmitted does not affect
the transmission of that character. This feature can be used
to prevent overrun of a remote receiver.
MR2[3:0]-Stop Bit Length Select. This field programs
the length of the stop bit appended to the transmitted character. Stop bit lengths of 9/,. to 1 and 19/,. to 2 bits, in
increments of '/'6 bit, can be programmed for character
lengths of 6, 7, and 8 bits. For a character length of 5 bits,
1'f,. to 2 stop bits can be programmed in increments of 'f,.
bit. In all cases, the receiver only checks for a mark condition at the center of the first stop-bit position (one bit-time
after the last data bit, or after the parity bit if parity is enabled). If an external 1 x clock is used for the transmitter,
MR2[3] = 0 selects one stop bit and MR2[3] = 1 selects
two stop bits to be transmitted.

REGISTERS (Continued)
MR2-Mode Register 2
MR2 is accessed when the channel MR pointer pOints to
MR2, which occurs after any access to MR1. Accesses to
MR2 do not change the pointer.
MR2[7:6]-Mode Select. The UART can operate in one
of four modes: MR2[7:6] = 00 is the normal mode, with the
transmitter and receiver operating independently. MR2[7:6]
= 01 places the channel in the automatic echo mode,
which automatically retransmits the received data. The following conditions are true while in automatic echo mode:
1. Received data is reclocked and retransmitted on the
TXD output.
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but thE! transmitter need
not be enabled.
4. The TXRDY and TXEMT status bits are inactivlil.
5. The received parity is checked, but is not regenerated
for transmission, i.e., transmitted parity bit is as received.
6. Character framing is checked, but the stop bits are retransmitted as received.
7. A received break is echoed as received until the next
valid start bit is detected.
8. CPU to receiver communication continues normally, but
the CPU to transmitter link is disabled.
Two diagnostic modes can also be selected. A local loopback mode is selected if MR2[7:6] = 10. In this mode:
1. The transmitter output is internally connected to the receiver input.
2. The transmit clock is used for the receiver.
3. The TXD output is held high.
4. The RXD input is ignored.
5. The transmitter must be enabled, but the receiver need
not be enabled.
6. CPU to transmitter and receiver communications continue normally.
The second diagnostic mode is the remote loopback
mode, selected by MR2[7:6] = 11. In this mode:
1. Received data is reclocked and retransmitted on the
TXD output.
2. The receive clock is used for the transmitter.
3. Received data is not seot to the local CPU, and the
error status conditions are inactive.
4. The received parity is not checked and is not regenerated for transmission, i.e., the transmitted paritY bit is as
received.
5. The receiver must be enabled, but the transmitter need
not be enabled.
6. Character framing is not checked, and the stop bits are
retransmitted as received.

INTERStL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical vaJU8S have been charsctsriz6d but are not tested.

11-9

l1li

IIlD~DIl..

;; IM26C91

g
(II

Table 2. Register Bit Formats

!

MR1
BIT7

BIT6

BIT5

RXRTS
CONTROL
0= no
1 = yes

R/INT
SELECT
0= RXRDY
1 = FFULL

ERROR
MODE
0= char
1 = blobk

BIT4

BIT3

BIT2

BIT1

PARITY
TYPE
o = even
1 = odd

PARITY MODE
00 = with parity
01 = force parity
10 = no parity
11 = special mode

BITO

BITS PER CHAR
00
01
10
11

=
=
=
=

5
6
7
8

MR2
BIT7

BIT6

CHANNEL MODE
00 = Normal
01 = Auto Echo
10 = Lock Loop
11 = Remote Loop

BIT5

BIT4

TxRTS
CONTROL
o = no
1 = yes

CTS
ENABLETx
0= no
1 = yes

BIT3

BIT2

Bin

BITO

STIP BIT LENGTH"
0=0.563
1 = 0.625
2 = 0.688
3 = 0.750

4
5
6
7

=
=
=
=

0.813
0.875
0.938
1.000

8 = 1.563
9 = 1.625
A = 1.688
B = 1.750

C=
0=
E=
F=

1.813
1.875
1.938
2.000

'Add 0.5 to values shown for 0-7. If channel is programmed for 5 bits/char.

CSR
BIT7

BIT7

BIT6

BIT5

BIT4

BIT3

BIT1

BIT2

RECEIVER CLOCK SELECT

TRANSMITIER CLOCK SELECT

See Text

See Text

BIT6

BIT5

MISCELLANEOUS COMMANDS
See Text

BIT4

BITO

CR
BIT3

BIT2

Bin

BITO

DISABLETx
o = no
1 = Yes

ENABLETx
0= no
1 = yes

DISABLERx
0= no
1 = yes

ENABLERx
0= no
1 = yes

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: All typical values have b6en characterized but are not testsd.

11-10

IM26C91
Table 2. Register Bits Formats (Continued)
SR
BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT1

BITO

RECEIVED
BREAK

FRAMING
ERROR

PARITY
ERROR

OVERRUN
ERROR

TXEMT

TXRDY

FFULL

RXRDY

0= no
1 = yes

0= no
1 = yes

0= no
1 = yes

0= no
1 = yes

0= no
1 = yes

0= no
1 = yes

0= no
1 = yes

0= no
1 = yes

.

.

.

'These status bits are appended to the corresponding data character in the receive FIFO. A read of the status register provides these bits [7:5) from the top of the
FIFO together with bits [4:0). These bits are cleared by a reset error status command. In character mode they are reset when the corresponding data character is
read from the FIFO.

ACR
BIT7

BIT6

BRGSET
SELECT

BITS

BIT4

BIT3

COUNTER/TIMER
MODE AND SOURCE

0= Set 1
1 = Set 2

o = On
1 = off

See Text

BIT1

BIT2

POWER
DOWN
MODE

BITO

MPOPIN
FUNCTION SELECT

000
001
010
011

=
=
=
=

RTSN
C/TO
TXC(1X)
TXC(16X)

100
101
110
111

=
=
=
=

RXC (1X)
RXC(16X)
TXRDY
RXRDY /FFULL

ISR
BIT7

BIT6

MPIPIN
CHANGE

MPIPIN
CURRENT
STATE

0= no
1 = yes

0= low
1 = high

BITS

not
used

BIT4

BIT3

BIT2

BIT1

BITO

COUNTER
READY

DELTA
BREAK

RXRDY/
FFULL

TXEMT

TXRDY

0= no
1 = yes

0= no
1 = yes

0= no
1 = yes

0= no
1 = yes

0= no
1 = yes

IMR
BIT7

BIT6

MPI
CHANGE
INT

MPI
LEVEL
INT

0= off
1 = on

0= off
1 = on

BIT7

BIT6

BIT4

BIT3

Bin

BIT1

BITO

COUNTER
READY
INT

DELTA
BREAK
INT

RXRDY
FFULL
INT

TXEMT
INT

TXRDY
INT

0= off
1 = on

0= off
1 = on

0= off
1 = on

0= off
1 = on

0= off
1 = on

BITS

not
used

CTUR

C1T[15]

I

C/T[14]

BITS

I

C/T[13]

BIT4

I

C1T[12]

BIT3

I

C/T[11]

BIT1

BIT2

I

C1T[10]

I

C/T[2]

I

C1T[9]

I

C1T[1]

BITO

I

CIT[S]

I

CIT[O]

CTLR
BIT7

C1T[7]

BIT6

I

C1T[6]

BITS

I

C1T[5]

BIT4

I

C1T[4]

BIT3

L

C/T[4]

BIT1

Bin

BITO

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE OONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

11·11

•

Cit

()

IM26C91

G

(\II

Table 3. Baud Rate

!

CSR [3:01! [7:4)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

ACR[7) = 0

ACR[7) = 1

50
110
134.5
200
300
600
1,200
1,050
2,400
4,800
7,200
9,600
38.4k
Timer
MPI-16x
MPI-1X

75
110
134.5
150
300
600
1,200
2,000
2,400
4,800
1,800
9,600
19.2k
Timer
MPI-16X
MPI-1X

The receiver clock is always a 16X clock, except for CSR[7:4) = 1111
CSR-Select Register
CSR[7:4)-Receiver Clock Select. When using a 3.6864
MHz crystal or external clock input, this field selects the
baud rate clock for the receiver as shown in Table 3.
CSR[3:0)-Transmitter Clock Select. This field selects
the baud rate clock for the transmitter. The field definition is
as shown in Table 3.
CR-Command Register
CR is used to write commands to the UART. Multiple
commands can be specified in a single write to CR as long
as the commands are non-conflicting, e.g., the enable
transmitter and reset transmitter commands cannot be
specified in a single command word.
CR[7:4)-Miscellaneous Commands. The encoded value of this field may be used to specify a single command as
follows:
0000 No command
0001 Reset MR pointer. Causes the MR pointer to point
to MR1.
0010 Reset receiver. Resets the receiver as if a hardware
reset had been applied. The receiver is disabled
and the FIFO is flushed.
0011 Reset transmitter. Resets the transmitter as if a
hardware reset had been applied.
0100 Reset error status. Clears the received break, parity
error, framing error and overrun error bits in the
status register (SR [7:4». Used in character mode to
clear OE status (although RB, PE, and FE bits will
also be cleared), and in block mode to clear all error
status after a block of data has been received.
0101 Reset break change interrupt. Causes the break detect change bit in the interrupt status register
(SR [31) to be cleared to zero.

0110 Start break. Forces the TXD output low (spacing). If
the transmitter is empty, the start of the break condition will be delayed up to two bit-times. If the
transmitter is active, the break begins when transmission of the character is completed. If a character
is in the THR, the start of break is delayed until that
character (or any others loaded after it) has been
transmitted (TXEMT must be true before break begins). The transmitter must be enabled to start a
break.
0111 Stop break. The TXD line will go high (marking)
within two bit times. TXD will remain high for one bit
time before the next character, if any, is transmitted.
1000 Start CIT. In counter or timer modes, causes the
contents of CTUR/CTLR to be preset into the
counter/timer and starts the counting cycle. In timer
mode, any counting cycle in progress when the
command is issued is terminated. In counter mode,
has no effect unless a stop CIT command was issued previously.
1001 Stop counter. In counter mode, stops operation of
the counter/timer, resets the counter-ready bit in
the ISR, and forces the MPO output high if it is programmed to be the output of the CIT. In timer
mode, resets the counter-ready bit in the ISR but
has no affect on the counter/timer itself or on the
MPO output.
1010 Assert RTSN. Causes the RTSN output to be asserted (low).
1011 Negate RTSN. Causes the RTSN output to be negated (high).
1100 Reset MPI change interrupt. Causes the MPI
change bit in the interrupt status register (SR [71) to
be cleared to zero.
1101 Reserved.
111 x Reserved.

EXCLUSI~

INTERSIL'S SOLE AND
WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but 8m not tested.

11-12

IM26C91
REGISTERS

when the FIFO is full and a character is already in the receive shift register waiting for an empty FIFO position.
When this occurs, the character in the receive shift register
(and its break detect, parity error and framing error status, if
any) is lost.
This bit is cleared by a reset error status command.
SR[3]-Transmitter Empty (TXEMT). This bit will be set
when the transmitter underruns, I.e., both the transmit holding register (THR) and the transmit shift register are empty.
However, this bit is not set until one character has been
transmitted. It is set after transmission of the last stop bit of
a character, if no character is in the THR awaiting transmission. It is reset when the THR is loaded by the CPU, or
when the transmitter is disabled.
SR[2]-Transmitter Ready (TXRDY). This bit, when set,
indicates that the THR is empty and ready to be loaded with
a character. This bit is cleared when the THR is loaded by
the CPU and is set when the character is transferred to the
transmit shift register. TXRDY is reset when the transmitter
is disabled and is set when transmitter is first enabled, e.g.,
characters loaded in the THR while the transmitter is disabled will not be transmitted.
SR[1]-FIFO (FFULL). This bit is set when a character is
transferred from the receive shift register to the receive
FIFO and the transfer causes the FIFO to become full, I.e.,
all three FIFO positions are occupied. It is reset when the
CPU reads the FIFO and there is no character in the receive
shift register. If a character is waiting in the receive shift
register because the FIFO is full, FFULL wil be reset by the
CPU read and then set by the transfer of the character to
the FIFO, which causes all three FIFO positions to be occupied.
SR[O]-Receiver Ready (RXRDY). This bit indicates
that a character has been received and is waiting in the
FIFO to be read by the CPU. It is set when the character is
transferred from the receive shift register to the FIFO and
reset when the CPU reads the RHR, and no more characters are in the FIFO.
ACR-Auxiliary Control Register
ACR[7]-Baud Rate Generator Set. This bit selects one
of two sets of baud rates generated by the BRG.
Set 1: 50,110, 134.5, 200, 300, 600, 1.05K, 1.2K, 2.4K,
4.8K, 7.2K, 9.6K and 38.4K baud.
Set 2: 75, 110, 134.5, 150, 300, 600, 1.2K, 1.8K, 2.0K,
2.4K, 4.8K, 9.6K, and 19.2K baud.
The selected set of rates is available for use by the receiver and transmitter.
ACR[6:4]-Counter/Timer Mode and Clock Source
Select. This field selects the operating mode of the counter/timer and its clock source as follows:

(Continued)
CR[3]-Dlsabled Transmitter. This command terminates transmitter operation and resets the TXRDY and
TXEMT status bits. However, if a character is being transmitted or if a character is in the THR when the transmitter is
disabled, the transmission of the character(s) is completed
before assuming the inactive state.
CR[2]-Enable Transmitter. Enables operation of the
channel A transmitter. The TXRDY status bit will be asserted.
CR[11-Disable Receiver. This command terminates operation of the receiver immediately- a character being received will be lost. The command has no effect on the receiver status bits or any other control registers. If the special wakeup mode is programmed, the receiver operates
even if it is disabled (see Wakeup Mode).
CR[O]- Enable Receiver. Enables operation of the receiver. If not in the special wakeup mode, this also forces
the receiver into the search for start-bit state.

SR-Channel Status Register
SR[7]-Receiver Break. This bit indicates that an all
zero character of the programmed length has been received without a stop bit. Only a single FIFO position is occupied when a break is received; further entries to the FIFO
are inhibited until the RXD line returns to the marking state
for at least one half bit-time (two successive edges of the
internal or external 1X clock).
When this bit is set, the change in break bit in the ISR
(SR [3]) is set. ISR [3] is also set when the end of the break
condition, as defined above, is detected.
The break detect circuitry is capable of detecting breaks
that orginate in the middle of a received character. However, if a break begins in the middle of a character, it must last
until the end of the next character time in order for it to be
detected.
SR[6]-Framing Error (FE). This bit, when set, indicates
that a stop bit was not detected when the corresponding
data character in the FIFO was received. The stop bit check
is made in the middle of the first stop bit position.
SR[5]-Parity Error (PE). This bit is set when the with
parity or force parity mode is programmed and the corresponding character in the FIFO was received with incorrect
parity.
In the special wakeup mode, the parity error bit stores the
received AID bit.
SR[4]-Overrun Error (OE). This bit, when set, indicates
that one or more characters in the received data stream
have been lost. It is set upon receipt of a new character

I'
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical va/uss have b96n characf9flzsd but are not tested.

11-13

III

3 IM26C91
It

;

REGISTERS
ACR[6:4)

ISR-Interrupt Status Register
This register provides the status of all potential interrupt
sources. The contents of this register are masked by the
interrupt mask register (IMR). If a bit in the ISR is a '1' and
the corresponding bit in the IMR is also a '1', the INTRN
?utput is asserted (low). If the corresponding bit in the IMR
IS a zero, the state of the bit in the ISR has no affect on the
INTRN output. Note that the IMR does not mask the reading
of the ISR-the true status is provided regardless of the
contents of the IMA.
ISR[7)-MPI Change of State. This bit is set when a
change of state occurs at the MPI input pin. It is reset by a
reset MPI change interrupt command.
ISR[6)-MPI Current State. This bit provides the current
state of the MPI pin. The information is unlatched and reflects the state of the pin at the time the ISR is read .
. ISR[~)~ounter Ready. In the counter mode of operation, thiS bit IS set when the counter reaches terminal count
and is reset when the counter is stopped by a stop counter
command. It is initialized to '0' when the chip is reset.
In the timer mode, this bit is set once each cycle of the
generated square wave (every other time the CIT reaches
zero count). The bit is reset by a stop counter command.
The command, however, does not stop the CIT.
ISR[3)-Change in Break. This bit, when set, indicates
that the receiver has detected the beginning or the end of a
received break. It is reset when the CPU issues a reset
break change interrupt command.
ISR[2)-Receiver Ready or FIFO Full. The function of
this bit is programmed by MR1 [6). If programmed as receiver ready, it indicates that a character has been received and
is waiting in the FIFO to be read by the CPU. It is set when
the character is transferred from the receive shift register to
the FIFO and reset when the CPU reads the receiver FIFO.
If the FIFO contains more characters, the bit will be set
again after the FIFO is read. If programmed as FIFO full, it is
set when a character is transferred from the receive holding
register to the receive FIFO and the transfer causes the
FIFO to become full, i.e., all three FIFO positions are occupied. It is reset when FIFO is read and there is no character
in the receive shift register. If there is a character waiting in
the receiver shift register because the FIFO is full, the bit is
set again when the waiting character is transferred into the
FIFO.
ISR(1)-Transmitter Empty. This bit is a duplicate of
TXEMT (SR[3)).
ISR[O)-Transmitter Ready. This bit is a duplicate of
TXRDY (SR[2)).
IMR-Interrupt Mask Register
The programming of this register selects which bits in the
ISR cause an interrupt output. If a bit in the ISR is a '1' and
~he corresponding bit in the IMR is a '1', the INTRN output
IS asserted (low). If the corresponding bit in the IMR is a
zero, the state of the bit in the ISR has no effect on the
INTRN output. Note that the IMR does not mask reading of
the ISA.
CTUR and CTLR-Counter/Tlmer Register
The CTUR and CTLR hold the eight MSS's and eight
LSS's respectively, the value to be used by the counter/tim-

(Continued)
Clock Source

Mode

0

0

0

Counter

MPIPin

0

0

1

Counter

MPI pin divided by 16

0

1

0

Counter

TXC-1

0

1

1

Counter

Crystal or external clock
(X 1/CLK) divided by 16

1

0

0

Timer

x clock of the transmitter

MPI Pin

1

0

1

Timer

MPI Pin divided by 16

1

1

0

Timer

Crystal or external
clock (X 1/CLK)

1

1

1

Timer

Crystal or external clock
(X 1ICLK) divided by 16

ACR[3)-Power Down Mode Select. This bit. when set
to zero, selects the power down mode. In this mode, the
oscillator is stopped and all functions requiring this clock
are suspended. The contents of all registers are saved. It is
recommended that the transmitter and receiver be disabled
prior to placing the UART in this mode. This bit must be set
to a logic 1 after power up.
ACR[2:0)-MPO Output Select. This field programs the
MPO output pin to provide one of the following:
000 Request to send active low output (RTSN). This output is asserted and negated via the command register. Mode RTSN can be programmed to be automatically reset after the character in the transmitter is
completely shifted out or when the receiver FIFO and
receiver shift register are full using MR2 [5) and
MR1[71. respectively.
001 The. counter/timer output. In the timer mode, this output IS a square wave with a period of twice the value
(in clock periods) of the contents of the CTUR and
CTLR. In the counter mode, the output remains high
until the terminal count is reached, at which time it
goes low. The output returns to the high state when
the counter is stopped by a stop counter command.
010 The 1 X clock for the transmitter which is the clock
that s~ifts the transmitted data. If data is not being
transmitted, a non-synchronized 1 X clock is output.
011 The 16 X clock for the transmitter. This is the clock
selected by CSR[3:0], and is a 1 X clock if CSR[3:0)
= 1111.
100 The 1 X clock for the receiver, which is the clock that
samples the received data. If data is not being received, a non-synchronized 1 X clock is output.
101 The 16 X clock for the receiver. This is the clock selected by CSR[7:4], and is a 1 X clock if CSR[7.4] =
1111.
110 The transmitter register empty Signal, which is the
complement of SR[2). Active low input.
111 The receiver ready or FIFO full signal (complement of
ISR[2)). Active low output.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE

~~~~~~~~~;~~L~ ~~Ni~~L~~~V~ ;~~T~~~~ ~~~~ LIEU OF ALL OTHER WARRANnes,

NOTE: All typical valuss have been characterized but arB not tested.

11-14

EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES

OF

IID~Dl\.

IM26C91
REGISTERS (Continued)
er in either the counter or timer mO!les of operation. The
minimum value which may be loaded is 000216.
In the Timer (programmable divider) mode, the CIT generates a square wave whose period is twice the value (in
clock periods) of the CTUR and CTLR. If the value in CTUR
or CTLR is changed, the current half-period will not be affected, but subsequent half-periods will be.
The counter ready status bit (SR[41) is set once each
cycle of the square wave. The bit is reset by a stop counter
command. The command, however, does not stop the CIT.
The generated square wave is output on MPO if it is programmed to be the CIT output.
In the counter mode, the CIT counts down the number of
pulses loaded into CTUR and CTLR. Counting begins upon
receipt of a start CIT command. Upon reaching the terminal
count, the counter-ready interrrupt bit (SR[4]) is set. The
counter continues counting past the terminal count until

stopped by the CPU. If MPO is programmed to be the output
of the CIT, the output remains high until the terminal count
is reached, at which time it goes low.
The output returns to the high state and ISR[4) is cleared
when the counter is stopped by a stop counter command.
The CPU may change the values of CTUR and CTLR at any
time, but the new count becomes effective only on the next
start-counter command. If new values have not been loaded, the previous count values are preserved and used for
the next count cycle.

0104-3

Figure 3: Reset Timing

eEN

RDN

......------

00- D7 ......~~... I'''='..... ,.~~"''\.J,.....-(READ) _ _
=:.I' ....--t-+--'~______
FL_OA_T_ __

-+' ....

WRN

~;~----->L VALID

0104-4

Figure 4: Bus Timing

RDN

1

,

. PI=::)( ]Io'-t-ps---~tPHKr_______

WRN

..PO

\_-----~
OLD DATA

_

:: ~:::::::::::::::::
~

NEW DATA

0104-5

Figure 5: 1/0 Timing

INTERSlL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANlY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTASILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AHtyplcal".,..."... _ _ buttwnot_

11-15

i

N

g

...
CD

IM26C91

0104-6
NOTES:
1. INTRN or MPO when used as interrupt outputs.

2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of
the switching signal, VM, to a point 0.5V, above VOL. This point represents a noise margin that assures true switching has occurred. Beyond this level, the

effects of external circuitry and test environment are pronounced and can greatly affect the resultant measurement.

Figure 6: Interrupt Timing

Xl/CLK, CIT CLK,
RxC, TxC

0104-7
DRIVING
PROM EXERNAL SOURCE

~L
UXl
Cl: 10-15 pF
C2: 0-5 pF

+

+

(STRAY

(STRAY

<

<

0104-8

5 pF)

5 pF)

0104-9
CRYSTAL SERIES RESISTANCE SHOULD BE LESS THAN 130n

Figure 7: Clock Timing

1 BIT TIME

Txc---{(l OR 16 CLOCKS)q
(INPUT)
......_ _ _ _ _ __

TxD
TxC
(IX OUTPUT)

\TX~:~\-TCS------X...----/

\.'--_ _ _ _ __
0104-10

Figure 8: Transmit Timing
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typics/ values have bBBn characterized but sre not testsd.

11·16

IM26C91
RxC-----(IX INPUT)
RxD _ _ _---J
0104-11

Figure 9: Receive Timing

TxD
TRANSUImR
ENABLED

TxRDY
(SR2)

WRN
D3

01

D4

START
BREAK

STOP
BREAK

CTSN 1

05 WILL
NOT BE
TRANSMITTED

06

(UPO _ _ _....I

~~CR(H)=1D1D
(MPO)

1-._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

~CR(7:4)=101D
0104-12

NOTES:
1. Timing shown for MR2[4] ~ 1.
2. Timing shown for MR2[5] ~ 1.

Figure 10: Transmitter Timing

•
INTER$IL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR

use.

NOTE: All typical values have been charact9fized but ate not tested.

11-17

IM26C91
R,D

RECEIVER
ENABLE

RxRDY
(SRO) _ _ _ _ _ _...J

FfULL
(SRI)

-----------\0---------....

R,ROY - - -_ _ _ _--,
rrULL
NPO

RON
STATUS DATA

'---'
01

OS WILL
BE LOST

+-__,.;;;;;..J

OVERRUN
(SR4) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

RTS'
NPO

0104-13

NOTES:
1. Timing shown for MR1[7] - 1.
2. Shown for ACR[2:0] - 111 and MR1[6] = O.

Figure 11: Receiver Timing
MASTER STATION

BIT 9

BIT9

I 00: 0I

hD

TRANSNITTER~:
i
i

BIT 9

:

ENABLED

T(~~j

__

~~

jll

~!~----------~,~~~I~AD-~~2~!I~1

----------~§

!

WRN
NRI [4:2]=11
MRI [2]=1

ADDII NR2[2]=D 00

PERIPHERAL STATION
R,D - - - ,

1-1

------;;-~§~~_---Jrl

-

r--..,:-o

r"1. ,

I

NRI [2] =1

BIT 9

ADD#I: 1

00

I
I

RECEIVER
:
ENABLED _ _ _ _ _ _ _ _ _ _ _ _ --....I
1-1

c!

!

BIT 9

I :I

:01:

I

~§--------------ADDI2

:8

BIT 9

BIT 9

s--_______----iS--_.L....a...
__
I I'_~~!°....ll
IAOO#2:q:
~

I

I

I

:

I
I
I
I

I
:
I
I

Clr

L

r--_----.n:-:
---w- ~br:s----_~:~
s-----u--W-

RxRDY
(SRO) _ _ _ _ _ _ _ _ _ __

RDN/WRN

lJ

NRI [4:2] =11

ADD#1

STATUS DATA
'---'
DO

STATUS DATA
'---'
ADD#2

0104-14

Figure 12: Wakeup Mode

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have besn characterized but 819 not tsst9d.

11-18

IM4702/4712
Baud Rate Generator
GENERAL DESCRIPTION

FEATURES

The IM4702/12 Baud Rate Generators provide necessary clock signals for digital data transmission systems,
such as UARTs, using a 2.4576MHz crystal oscillator as an
input. They control up to 8 output channels and can be cascaded for output expansion.
Output rate is controlled by four digital input lines, and
with the specified crystal, is selectable from "zero" through
9600 Baud. In addition, 19200 Baud is possible via hardwiring.
Multi-channel operation is facilitated by making the clock
frequency and the + 8 prescaler outputs available externally. This allows up to eight simultaneous Baud rates to be
generated.
The IM4712 is identical to the IM4702 with the exception
that the IM4712 integrates the oscillator feedback resistor
and two load capacitors on-chip.

• Provides 14 Most Commonly Used BAUD Rates
• On-Chip OSCillator Requires Only One External Part
(IM4712)
• Controls Up to Eight Transmission Channels
• TTL Compatible Outputs Will Sink 1.6mA
• Uses Standard 2.4576MHz Crystal
• Low Power Consumption: S.SmW Guaranteed
Maximum Standby
• Pin and Function Compatible With 4702B and HD4702
• Inputs Feature Active Pull-Ups

PIN DESCRIPTION

ORDERING INFORMATION

Signal

Pin

00- 0 2

1,2,3

Description

ECP

4

CP

5

External Clock Input

Ox

6

Crystal Output
Crystal Input

Prescaler Outputs
External Clock Enable Input

Order
Number

Temperature
Range

Package

IM47021JE

-40'Cto + 85'C

16-pin CERDIP

Ix

7

16-pin PLASTIC

Vss

8

Negative Supply

Co

9

Clock Output
Baud Rate Output

IM47021PE

-40'C to +85'C

IM47121JE

-40'Cto + 85'C

16-pin CERDIP

IM47121PE

-40'Cto + 85'C

16-pin PLASTIC

Z

10

SO-S3

14-11

1M

15

Multiplexed Input

Voo

16

Positive Supply

Baud Rate Select Inputs

,...--------I

410201QLLATOII

:
I

C*ICUft'

I

I

I

~~U

OoC~:::JVDO

I~~r_------~
__
~

a,c

2

Coca

c.~t_------,,......,,,

":::JIM
14:::J ..

! ,.~S,
;~. ~ 12~St

Ecp .....
OxC •

IxC 7
VssC •

11 :::JSa
":::JZ
• :::Jco

----

0373-2

Figure 2: Pin
Configuration
(Outline drawings

JE, PEl

0373-1

Figure 1: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARAANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.

NOTE: All typical va/U68 have b6en characterized but are not f9sted

11-19

•

IID~DIL

:! IM4702/4712

......
.....
o...
...
&\I

ABSOLUTE MAXIMUM RATINGS

!

Supply Voltage (Voo-Vss) ..................... +8.0V
InputorOutputVoltage ........ Vss -0.3VtoVoo+0.3V
Storage Temperature Range .......... - 65·C to + 150·C
Operating Temperature Range ......... -40"C to + 85·C

NOTE: Str9sses above those listed under "Absolute MaxImum Ratings"
may cause permanent damage to th9 davic9. Thss8 are strass ratings only
and functional oparalion of th9 davic9 at th9S9 or any other conditions
above those indicated in th9 oparational sectiona of th9 spscIflcalions Is not
implied. ExposUffJ to absolute maximum rating conditions for extended periods may affect devic9 rsllablHty.

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS Voo= +5V±10% Vss=OV, TA= -40·Cto
Symbol

Parameter

+85·C

Umlts

Test Conditions
Min

VIH

Input Voltage High

VIL

Input Voltage Low

IIH

Input Current
High

Other Inputs

Input Current
Low

Ix 4702

IlL

70%Vcc

Ix 4712

Ix 4712

+1

VIN=VOO
All other pins grounded

+10
-1

Pin under test at ground
All other Inputs at Voo

+10
-15

VOH

Output Voltage High

IOH< -lp.A; Inputs atVss orVoo

VOL

Output Voltage Low

IOL < + 1p.A; Inputs at Vss or Voo

IOH

Output Current
High

Inputs at Vss or Voo
Vo=Voo-·5

-0.1

Vo=+2.5V

-1.0

ISTBY

Output Current
Low

V
30%VCC

Other Inputs

IOL

Units
Max

Ox
All other
Outputs
Ox
All other
Outputs

Quiescent Supply Current

p.A

-100

Voo-·05

V
0.05

-0.3

-0.1
Vo=0.4; Inputs atVss orVoo
Ecp=Voo; CP=Vss
All other Inputs=Vss orVoo,
All outputs open

1.6

mA

1.0

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: AU IypIcsI vsIu6s have been chsractetizBd but 818 not fBst6d.

11-20

IIID~DI!..

IM4702/4712
AC CHARACTERISTICS

voo= +5VVss=OV, TA=25'C

Parameter

Symbol

Limits

Test Conditions
Min

Propagation delay(I), CP to CO

Propagation delay(I), CO to an

CL (except Ox) = 50pF

260

CL(Ox)=7pF

220
(2)

RL =200kO
(2)

tphl
Propagation delay(I), CO to Z

tphl

Input

85

Transition times :£:20ns

75
160

ttlh

Output Transition Time, (1)

Input low = 1.0V

tlhi

(except OX>

Input high=Vcc-1.OV

ts

ttl
twCP(L)

Set UpTime

Hold Time

ns

75

Select to CO

350

1M to CO

350

Select to CO

0

1M to CO

0
120

Clock pulse width(3)

twCP(H)

120

twlx(L)(4702)

160

twlx(H)(4702)

II'

275

tphl

tplh

....

350

\Pu(4712)

tplh

....II'....

275

Propagation delay(I), Ix to CO

tplh(4712)

tplh

.......o

350

tplh(4702)
tphl(4702)

Units
Max

i

160

Ix Pulse Width

twlx(L)(4712)

190

twlx(H)(4712)

190

NOTES: 1. Propagation delays and oulput transition times will vary with output load capacitance.
2. For multichannel operation, propagation delay (CO to an) plus set·up tima (5electto CO) is guaranteed to be less than 367ns for the IM4702/12.
3. The first high level clock pulse after Ecp goes low must be at least 200ns wide to ensure reseting of all counters.
4. For design reference only, not 100% tested.

III

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typlcsl va/USB have beBn characterizsd but are not tested.

11·21

=
.... IM4702/4712

.......
(\I

o

.......

!

CP/IX----1

CO----f'

0373-3

Figure 3: Switching Waveforms
Table 1: Clock Modes and Initialization

FUNCTIONAL DESCRIPTION
Digital data transmission systems employ a wide range of
standardized bit rates, ranging from 50 baud (for electromechanical devices) to 9600 baud (for high speed modems).
Modern electronic systems commonly use Universal Asynchronous Receiver and Transmitter circuits (UARTs) to convert parallel data inputs into a serial bit stream (transmitter)
and to reconvert the serial bit stream into parallel outputs
(receiver). In order to resynchronize the incoming serial
data, the reciever requires a clock rate which is a multiple of
the incoming bit rate. Popular MOSLSI UART circuits use a
clock that is 16 times the transmitted bit rate. The IM47021
12 can generate 14 standard clock rates from one common
high frequency input.
The IM4702/12 contains the following five function subsystems.
OSCillator - For conventional operation generating 16 output clock pulses per bit period, the input clock frequency
must be 2.4576MHz (i.e. 9600 baud x 16 x 16, since the
scan counter and the first flip-flop of the counter chain act
as an internal -;- 16 prescaler). A lower input frequency will
result in a proportionally lower output frequency.
The IM4702/12 can be driven from two alternate clock
sources: (1) When the Ecp (External Clock Enable) inpl!!. is
LOW, the CP input is the clock source. (2) When the Ecp
input is HIGH, a crystal connected between Ix and Ox, or a
signal applied to the Ix input, is the clock source.
Prescaler (Scan Counter) - The clock frequency is made
available on the CO (Clock Output) pin and is applied to the
-;- 8 prescaler with buffered outputs 00, 01, and 02.

Ix

Ecp

CP

Operation

~

H
L
H
L

L

Clocked from Ix
Clocked from CP
Continuous Reset
Reset During First
CP = HIGH Time

X
X
X
H
L
X

..J1..
~

=

~

H

..J1..

HIGH Level

= LOW Level
= Don't Care

= 1st HIGH Level Clock Pulse After Ecp
Goes LOW
= Clock Pulses
0373-8

Counter Network - The prescaler output 02 is a square
wave of 'fa the input frequency, and is used to drive the
frequency counter network generating 13 standardized frequencies. Note that the frequencies are labeled in the block
diagram and described in terms of the transmission bit rate.
In a conventional system using a 2.4576MHz clock input,
the actual output frequencies are 16 times higher.
The output from the first frequency divider flip-flop is thus
labeled 9600, since it is used to transmit or receive 9600
baud (bits per second). The actual frequency at this node is
16 x 9.6kHz = 153.6kHz. Seven more cascaded binaries
generate the appropriate frequencies for bit rates 4800,
2400, 1200, 600, 300, 150, and 75.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values hsVB been charsctsrizsd but are not tested.

11-22

IIID~OI!..

IM4702/4712
The other five bit rates are generated by individual counters:

Table 2: Truth Table for Rate Select Inputs

bit rate 1200 is divided by 6 to generate bit rate 200,
bit rate 200 is divided by 4 to generate bit rate 50,
bit rate 2400 is divided by 18 to generate bit rate 134.5
with a frequency error of -0.87%,
bit rate 2400 is also divided by 22 to generate bit rate
110 with a frequency error of -0.83%, and
bit rate 9600 is divided by 16/3 to generate bit rate
1800.
The 16/3 division is accomplished by alternating the divide
ratio between 5 (twice) and 6 (once). The result is an exact
average output frequency with some frequency modulation.
Taking advantage of the + 16 feature of the UART, the
resulting distortion is less than 0.78% regardless of the
number of elements in a character, and therefore well within
the timing accuracy specified for high speed communications equipment. All signals except 1800, have a 50% duty
cycle.
Output Multiplexer - The outputs of the counter network
are fed to a 16-input multiplexer, which is controlled by the
Rate Select inputs (So - S3). The multiplexer output is then
resynchronized with the incoming clock in order to cancel
all cumulative delays and to present an output signal at the
buffered output (Z) that is synchronous with the prescaler
outputs (00-02)' Table 2 lists the correspondance between select code and output bit rate. Two of the 16 codes
do not select an internally generated frequency, but select
an input into which the user can feed either a different, nonstandardized frequency, or a static level (HIGH or LOW) to
generate "zero baud".
The bit rates most commonly used in modern data terminals (110, 150, 300, 1200, 2400 baud) require that no more
than one input be grounded, easily achieved with a single
pole, 5-position switch. 2400 baud is selected by two different codes, so that the whole spectrum of modern digital
communication rates has a common HIGH on the S3 input.
Initialization (Reset) - The initialization circuit generates a
common master reset signal for all flip-flops in the IM47021
12. This signal is derived from a digital differentiator that
senses the first HIGH level on the CP input after the Ecp
input goes LOW. Upon initialization, all counters are reset
and all outputs will be in the LOW state. When Ecp is HIGH,
selecting the Crystal input, CP must be LOW; a HIGH level
on CP would apply a continuous reset.
All inputs to the 4702/12 except Ix have on-chip pull-up
circuits; the Ix input of the 4712 has a high value resistor
tied to Ox.

S3

S2

SI

So

Output Rate (Z)
Note 1

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

Multiplexed Input (1M)
Multiplexed Input (1M)
50 Baud
75 Baud
134.5 Baud
200 Baud
600 Baud
2400 Baud
9600 Baud
4800 Baud
1800 Baud
1200 Baud
2400 Baud
300 Baud
150 Baud
110 Baud

i

.......
o
.......
....
N

..
N

L~LOW Level
H ~ HIGH Level

Note 1: Actual output frequency is 16 times the indicated output rate, assuming a clock frequency of 2.4576MHz.

Table 3: Crystal Specifications
Parameters

Typical Crystal Spec

Frequency
Series Resistance (Max)
Unwanted Modes
Type of Operation
Load Capacitance

2.4576MHz "AT" Cut
2500
-6dB (Min)
Parallel
32pF±0.5pF

APPLICATIONS
Single Channel Bit Rate Generator
Figure 4 shows the Simplest application of the IM47021
12. This circuit generates one of five possible bit rates as
determined by the setting of a single pole, 5-position switch.
The Bit Rate Output (Z) drives one standard TTL load or
four low power Schottky loads over the full temperature
range. The possible output frequencies correspond to 100,
150, 300, 1200, and 2400 or 3600 Baud. For many low cost
terminals, these five bit rates are adequate.
This mode of operation is commonly chosen for applications using industry standard 1402/6402 UARTs.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

11-23

III

.......

t\I

IM4702/4712

....'Itt\I
o
....
'It

!

OUTPUT I
0373-4

o

E

Switch
Position

Bit Rate

1
2
3
4
5

110 Baud
150 Baud
300 Baud
1200 Baud
2400 Baud

93L34

0373-5

Figure 5: Bit Rate Generator Configuration With
Eight Simultaneous Frequencies

Figure 4: Switch Selectable Bit Rate Generator
Configuration Providing
Five Bit Rates

19200 Baud Operation
A 19200 baud Signal is available on the Q2 output, but is
not internally connected to the multiplexer. This Signal can
be generated on the Z output by connecting the Q2 output
to the 1M input and applying select code. An additional 2-input NOR gate can be used to retain the "Zero Baud" feature on select code 1 for the IM4702/12, (See Figure 6),

Simultaneous Generation of Several Bit
Rates
Figure 5 shows a simple scheme that generates eight bit
rates on eight output lines, using one IM4702/12 and one
93L34 Bit Addressable Latch. This and the following applications take advantage of the built-in scan counter (prescaler) outputs. As shown in the block diagram, these outputs
(Qo to Q2) go through a complete sequence of eight states
for every half-period of the highest output frequency (9600
Baud). Feeding these Scan Counter Outputs back to the
Select inputs of the multiplexer causes the IM4702/12 to
sequentially interrogate the state of eight different frequency signals. The 93L34 Bit Addressable Latch, addressed by
the same Scan Counter Outputs, reconverts the multiplexed
single Output (Z) into eight parallel output frequency signals. In the simple scheme of Figure 5, input S3 is left open
(HIGH) and the following bit rates are generated:

56pF

~I-F--·2''-45-76-M-H~.--I
CRYSTAL

Qo: 110 Baud
Q3: 1800 Baud
Q6: 300 Baud
Q1: 9600 Baud
Q4: 1200 Baud
Q7: 150 Baud
Q2: 4800 Baud
Q5: 2400 Baud
Other bit rate combinations can be generated by changing the Scan Counter to Selector interconnection or by inserting logic gates into this path.

OUTPUT
0373-6

Figure 6: 19200 Baud Operation
" The 4712 may replace the 4702 in the above applications with the

stan~

dard 2.4576MHz crystal. The two external capacitors and one resistor are
not required when using the 4712.

!NTERSIL'S SOLE AND EXCLUS!VE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been character/zed but are not tested.

11-24

.D~DI!..

IM4702/4712

.i...
.....
......
0

N

10

N

.Iw
II
37

as
M

II

as
IMI402

I'

CLII
CLU

PI
CRL

EPE
SIS
SfD

OUTPUT

25
20

TIIO

RRI

0373-7

Figure 7: IM4712 Baud Rate Generator With IM6402 CMOS UART

III

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE' All typical values have been characterized but are not tested

11-25

D~DIl

•/Ig IM6402/IM6403
Universal Asynchronous

:::.
Receiver Transmitter (UART)
(II
o

•
II:»

!

GENERAL DESCRIPTION

FEATURES

The IM6402 and IM6403 are CMOS/LSI UART's for interfacing computers or microprocessors to asynchronous serial data channels. The receiver converts serial start, data,
parity and stop bits to parallel data verifying proper code
transmission, parity, and stop bits. The transmitter converts
parallel data into serial form and automatically adds start,
parity, and stop bits.
The data word length can be 5, 6, 7 or B bits. Parity may
be odd or even, and parity checking and generation can be
inhibited. The stop bits may be one or two (or one and onehalf when transmitting 5 bit code). Serial data format is
shown in Figure B.
The IM6402 and IM6403 can be used in a wide range of
applications including modems, printers, peripherals and remote data acquisition systems. CMOS/LSI technology permits clock frequencies up to 4.0MHz (250K Baud), an improvement of 10 to 1 over previous PMOS UART designs.
Power requirements, by comparison, are reduced from
670mW to 10mW. Status logic increases flexibility and simplifies the user interface.
The IM6402 differs from the IM6403 in the use of five
device pins as indicated in Table 1 and Figure 4.

•
•
•
•
•
•

Low Power - Less Than 10mW Typ. at 2MHz
Operation Up to 4MHz Clock (IM6402A)
Programmable Word Length, Stop Bits and Parity
Automatic Data Formatting and Status Generation
Compatible With Industry Standard UART's (IM6402)
On-Chip OSCillator With External Crystal (IM6403)

• Operating Voltage IM6402-1/03·1: 5V
IM6402A/03A:4-11V
IM6402/03: 5V

ORDERING INFORMATION
ORDER CODE

IM6402·1/03·1

IM6402A103A

IM6402/03

PLASTICPKG

IM6402-1/03-IPL

IM6402/03AIPL

IM6402/031PL

CERAMICPKG

IM6402-1/03-1IJL

IM6402/03AIJL

IM6402/031JL

MILITARY TEMP.

IM6402-1 /03·1 MJL

IM6402/03AMJL

MILITARY TEMP.
WITH /Hi-Rel processing

IM6402-1 /03-1 MJL/HR

IM6402/03AMJL/HR

TRE

* TBRE

------,

TeA1 (LSB)

+_-=-=-:;

~~~~~==~

I

I
I

TRC~~~:

CLSl
CLS2
CRl

CONTROL
REGISTER

TRO
SBS
EPE
PI

MR

RRC

ORR
• OR

0374-1

Figure 1: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONOIT!ON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been chafBcterfz9d but are not tsstBd.

11-26

.D~OI!.

IM6402/IM6403
ABSOLUTE MAXIMUM RATINGS (lM6402/03)
Operating Temperature
IM6402/03 (I) ........................ -40'C to +S5'C
Storage Temperature Range ........... -65'C to 150'C
SupplyVoltage(Voo-Vss) ..................... +S.OV
Voltage On Any Input or Output Pin ......... (Vss -0.3V)
to (Voo + 0.3V)
Lead Temperature (Soldering, 10sec) ............. 300'C

ict

•
0

II)

r--------------------'" :::I:

•ct0

Voo
CLSZ

RRD
RBRS
RBR?
RBRe
RBRS
RBR4
RBR3
RBR2
RBRt
PE
FE
OE
SFD

NOTE: Stresses above those listed under "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only
and functionsl operation of the device at these or any other conditions
above those indicated in /he operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extend6d periods may affect device reliability.

Cot

EPE
CLSt

VIS

SIS
PI
CRL
TBRS
TBR?
TBRS
TBRS
TBR4
TBR3
TBR2
TBRt
TRO
TRE
TBRL
TBRE
MR

ORR
DR
RRI

0374-2

'See Table 1

Figure 2: Pin Configuration

TABLE 1
PIN

IM6402

IM6403 w/XTAL

IM6403 w/EXT TTL CLOCK

IM6402 w/EXT CMOS CLOCK

2
17
19
22
40

N/C

Divide Control
XTAL
Always Active
Always Active
XTAL

Divide Control
External Clock Input
Always Active
Always Active

Divide Control
No Connection
Always Active
Always Active
External Clock Input

RRC
Tri-State
Tri-State
TRC

DC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

Vss

(Voo= 5.0V ± 10% Vss = OV, TA = Operating Temperature Range)
TEST CONDITIONS

MIN

VIH

Input Voltage High

VIL

Input Voltage Low

IlL

Input Leakage [1]

VSS,,;VIN";VOO

-5.0

VOH

Output Voltage High

IOH=-0.2mA

2.4

VOL

Output Voltage Low

IOL =1.6mA

IOLK

Output Leakage

VSS,,;VOUT";VOO

ISTBY

Power Supply Current Standby

VIN=VssorVoo

TYp2

MAX

UNIT
V

Voo-2.0
O.S

V

5.0

p.A
V

-5.0
1.0

le=500kHz

0.45

V

5.0

p.A

SOO

p.A

1.2

mA

100

Power Supply Current IM6402

100

Power Supply Current IM6403

leIVstal = 2.46MHz

3.7

mA

CIN

Input Capacitance [1] [3]

TA=25'C

7.0

S.O

pF

Co

Output Capacitance [1] [3]

TA=25'C

S.O

10.0

pF

NOTE: 1. Except IM6403 XTAL input pins (i.e. pins 17 and 40).
2. VDD~5V. TA~25°C.
3. These parameters are guaranteed but not 100% tested.
INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valUBS hSV9 bHn characterized but arB not tesl9d.

11-27

III

CO)

o

...

IM6402/IM6403

C&)

Ii AC ELECTRICAL CHARACTERISTICS

::::.
CII

...o

(Voo=5.0V ±10% Vss=OV, CL =50pF, TA=Operating

Temperature Range)

C&)

SYMBOL

PARAMETER

TEST CONDITIONS

!

fe

Clock Frequency IM6402

ferystal

Crystal Frequency IM6403

tpw

Pulse Widths CRL, DRR, TBRL

D.C.

tmr

Pulse Width MR

See Timing Diagrams

tds

Input Data Setup Time

(Figures 4,5,6)

tdh

Input Data Hold Time

ten

Output Enable Time

PIN 17
RRC

TRC

r--

\

,I
I

l6X CLOCK
PIN 40

~::~~~TEA REGISTER/

OR

PIN2

NIC

~,,~

XTAL9,"
PIN 40

=

I

NIC

D'
II

,I

DIVlce CONTROL
l ." DIVIDE BY 2048

I

H .. DIVIDE BY 16

I

PIN 19

IM6402

~

.......

\
\

TBRE

PIN 22

TBRE

\

PIN".16

\

SFO

'--

.......

PIN 22

BUFFERS ARE 3·STATE \
WHEN SFO" HIGH
\
\

\

SFO

MHz

600

200

ns

75

20

ns

90

40

ns

RECEIVER REGISTER

C

c

ns
190

.

l6X CLOCK

24 OR211
DIVIDER

~~E

TRANSMITTER REGISTER

l6X CLOCK

CONTROL

OR

\

MHz

2.46

ns

.. I ....
.

UNIT

1.0

50

PIN2

PIN 19

\

~

MAX

225

80

\

RECEIVER REGISTEA

Typ2

MIN

lr
J

BUFFERSAAE
ALWAYS ACTIVE

IM6403

PIN 16

I

'-0374-4

Figure 3: Functional Difference Between IM6402 and IM6403 UART
(IM6403 has On-Chip 4/11 Stage Divider)
The IM6403 differs from the IM6402 on three Inputs
(RRC, TRC, pin 2) as shown in Figure 3. Two outputs
(TBRE, DR) are not three-state as on the IM6402, but are
always active. The on-chip divider and oscillator allow an
inexpensive crystal to be used as a timing source rather
than additional circuitry such as baud rate generators. For
example, a color TV crystal at 3.579545MHz results in a
baud rate of 109.2Hz for an easy teletype interface (Figure
12). A 9600 baud interface may be implemented using a
2.4576MHz crystal with the divider set to divide by 16.

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: All typical values have been characterized but are not tested.

11-28

IIlD~OI!.

IM6402/IM6403
(IM6402AII AM, IM6403AII AM)
ABSOLUTE MAXIMUM RATINGS

i

...o
~

....N
Operating Temperature Range
IM6402AI/03AI .................... -40'Cto + 85'C
IM6402AM/03AM ................. - 55'C to + 125'C
Storage Temperature Range ............ -65'C to 150'C
Lead Temperature (Soldering, 10sec) ............. 300'C

Supply Voltage (Voo-Vss) .................... + 12.0V
Voltage On Any Input or Output Pin .......... (Vss-0.3V)
to (Voo +0.3V)

i~

...o
Co)

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent demage to the device. These are stress ratings only and functional

operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
PARAMETER

SYMBOL

(Voo= 4.0V to 11.0V Vss = OV, TA = Operating Temperature Range)

TEST CONDITIONS

MIN

TYp2

MAX

UNIT
V

VIH

Input Voltage High

VIL

Input Voltage Low

IlL

Input Leakage [1] [3]

VSS,;;VIN';;VOO

VOH

Output Voltage High

IOH=OmA

VOL

Output Voltage Low

IOL =OmA

IOLK

Output leakage

VSS,;;VOUT';;VOO

Icc

Power Supply Current Standby

VIN=VssorVoo

Icc

Power Supply Current IM6402A

Icc

Power Supply Current IM6403A

fcrystal = 3.58MHz

CIN

Input Capacitance [1] [3]

TA=25'C

7.0

Co

Output Capacitance [1] [3]

TA=25'C

8.0

70% Voo

-1.0

10% Voo

V

1.0

/LA
V

Voo-O.Ol

V

Vss+O.Ol
-1.0

1.0
5.0

fcrystal = 4MHz

/LA

500

/LA

9.0

mA

13.0

mA

8.0

pF

10.0

pF

NOTE: 1. Except IM6403 XTAL input pins (i.e. pins 17 and 40).
2. VDD=SV, TA=2S'C.
3. These parameters are guaranteed but not 100% tested.

AC ELECTRICAL CHARACTERISTICS

(Voo = 10.0V

± 5% VSS = OV, CL = 50pF, TA = Operating

Temperature Range)

SYMBOL

PARAMETER

fc

Clock Frequency IM6402A

fcrystal

Crystal Frequency IM6403A

tpw

Pulse Widths CRL, DRR, TBRl

tmr

Pulse Width MR

Ids

Input Data Setup Time

tdh

Input Data Hold Time

ten

Output Enable Time

TEST CONDITIONS

MIN

TYp2

D.C.

MAX

UNIT

4.0

MHz

6.0

MHz

100

40

ns

See Timing Diagrams

400

200

ns

(Figures 4,5,6)

40

0

ns

30

30
40

ns
70

ns

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charscteriz8d but are not tested.

11-29

•

.O~OIL

S IM6402/IM6403

...

C)

:I (IM6402-11/1M, IM6403-1111M)
:::::.
(II
o ABSOLUTE MAXIMUM RATINGS

...
C)

!

Operating Temperature Range
IM6402-1 1103-1 I .•.................. -40'Cto +85'C
IM6402-1M/03-1M ...........•.... -55'Cto + 125'C
Storage Temperature Range .......... -65'C to + 150'C
Lead Temperature (Soldering. 10sec) ............. 300'C

Supply Voltage (Voo-Vss) ..................... +8.0V
Voltage On Any Input or Output Pin ......... (Vss -0.3V)
to (Voo + 0.3V)

NOTE: stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These 8f9 stress rstings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
SYMBOL

(Voo=5.0 ±100/0 Vss=OV. TA=OperatingTemperature Range)

tEST CONOITIONS

PARAMETER

TYp2

MIN

VIH

Input Voltage High

Vil

Input Voltage Low

IlL

Input Leakage [1] [3]

VSS:5:VIN:5:VOO

-1.0

VOH

Output Voltage High

IOH= -0.2mA

2.4

VOL

Output Voltage Low

IOl =2.0mA

IOlK

Output Leakage

VSS:5:VOUT:5:VOO

Icc

Power Supply Current Standby

VIN=VssorVoo

Icc

Power Supply Current IM6402 Dynamic

Icc

Power Supply Current IM6403 Dynamic

MAX

UNIT
V

Voo-2.0
0.8

V

1.0

p.A
V

0.45

V

1.0

p.A

-1.0
1.0

100

p.A

lo=2MHz

1.9

mA

lorystal = 3.58MHz

5.5

mA

CIN

Input Capacitance [1] [3]

TA=25'C

7.0

8.0

pF

Co

Output Capacitance [1] [3]

TA=25'C

8.0

10.0

pF

NOTE: 1. Except IM6403

XTAl input pins (i.e. pins

17 and 40).

2. VDD~5V, TA~25°C.

3. These parameters are guaranteed but not 100% tested.

AC ELECTRICAL CHARACTERISTICS

(Voo=5.0V ±100/0 Vss=OV. Cl =50pF. TA=Operating

Temperature Range)

SYMBOL

10

PARAMETER

TEST CONDITIONS

Clock Frequency IM6402-1

MIN

Typ2

D.C.

lorystal

Crystal Frequency IM6403-1

tpw

Pulse Widths CRL. ORR. TBRL

tmr

Pulse Width MR

See Timing Diagrams

tds

Input Data Setup Time

(Figures 4.5.6)

tdh

Input Data Hold Time

ten

Output Enable Time

MAX

UNIT

2.0

MHz

3.58

MHz

150

50

ns

400

200

ns

50

20

ns

60

40

ns

80

160

ns

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values hSV6 b89n chstacterizBd but are not test6d.

11-30

.O~OI!.

IM6402/IM6403

Table 1: IM6402/3 Pin Description

TIMING DIAGRAMS
PIN

SYMBOL

1

Voo

2

IM6402-N/C
IM6403-Control

Vss

Negative Supply

RRD

A high level on RECEIVER REGISTER DISABLE forces the receiver holding register outputs
RBR1-RBRB to a high impedance
state.

5

RBRB

The contents of the RECEIVER
BUFFER REGISTER appear on
these three-state outputs. Word
formats less than B characters
are right justified to RBR1.

6

RBR7

See Pin 5 - RBRB

7

RBR6

See Pin 5 - RBRB

B

RBR5

See Pin 5 - RBRB

9

RBR4

See Pin 5 - RBRB

10

RBR3

See Pin 5 - RBRB

11

RBR2

See Pin 5 - RBRB

12

RBR1

13

PE

A high level on PARITY ERROR
indicates that the received parity
does not match parity programmed by control bits, The output is active until parity matches
on a succeeding character, When
parity is inhibited, this output is
low.

14

FE

A high level on FRAMING ERROR indicates the first stop bit
was invalid. FE will stay active until the next valid character's stop
bit is received,

15

OE

A high level on OVERRUN ERROR indicates the data received
flag was not cleared before the
last character was transferred to
the receiver buffer register. The
Error is reset at the next character's stop bit if DRR has been performed (i,e" DRR; active low).

CLS1, CLS2, SBS, PI, EPE
Jr""--~

SFDDR RRD

STATUS OR
RBR1· RBR8

VALID
DATA

0374-7

Figure 6: Status Flag Enable Time
or Data Output Enable Time

No Connection
Divide Control
High: 24 (16) Divider
Low: 211 (204B) Divider

4

0374-5

0374-6

Positive Power Supply

3

Figure 4: Data Input Cycle

Figure 5: Control Register Load Cycle

DESCRIPTION

11-31

...oCII
II)

.....

iCII

...o

Col

See Pin 5 - RBRB

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOA A PARTICULAR USE.
NOTE: All typical values havs been charscterized but sre not tested

i

•

i

.-•

Table 1: IM6402/3 Pin Description (Continued)

Table 1: IM6402/3 Pin Description (Continued)

:::::.
C\II

PIN

SYMBOL

.-

16

SFD

o'II'

.D~DIL

IM6402/IM6403

!

DESCRIPTION
. .A high level on STATUS FLAGS
DISABLE forces the outputs PE,
FE, OE, DR", TBRE" to a high impedance state. See Block Diagram and Figure 6.
o IM6402 only.

17

IM6402-RRC
IM6403-XTAL

The
RECEIVER
REGISTER
CLOCK is 16X the receiver data
rate.

18

DRR

A low level on DATA RECEIVED
RESET clears the data received
output (DR), to a low level.

19

DR

A high level on DATA RECEIVED
indicates a character has been received and transferred to the receiver buffer register.

20

21

22

23

24

RRI

MR

TBRE

TBRL

TRE

Serial data on RECEIVER REGISTER INPUT is clocked into the receiver register.
A high level on MASTER RESET
(MR) clears PE, FE, OE, DR, TRE
and sets TBRE, TRO high. Less
than 18 clocks after MR goes low,
TRE returns high. MR does not
clear the receiver buffer register,
and is required after power-up.
A high level on TRANSMITIER
BUFFER REGISTER EMPTY indicates the transmitter buffer register has transferred its data to the
transmitter register and is ready
for new data.
A low level on TRANSMITIER
BUFFER REGISTER LOAD transfers data from inputs TBR1-TBR8
into the transmitter buffer register.
A low to high transition on T8R[
requests data transfer to the
transmitter register. If the transmitter register is busy, transfer is
automatically delayed so that the
two characters are transmitted
end to end. See Figure 4.
A high level on TRANSMITIER
REGISTER EMPTY indicates
completed transmission of a character including stop bits.

PIN

SYMBOL

DESCRIPTION

25

TRO

Character data, start data and
stop bits appear serially at the
TRANSMITIER REGISTER OUTPUT.

26

TBR1

Character data is loaded into the
TRANSMITIER BUFFER REGISTER via inputs TBR1-TBR8. For
character formats less than 8-bits,
the TBR8, 7, and 6 Inputs are ignored corresponding to the programmed word length.

27

TBR2

See Pin 26 - TBR1

28

TBR3

See Pin 26 - TBR1

29

TBR4

See Pin 26 - TBR1

30

TBR5

See Pin 26-TBR1

31

TBR6

See Pin 26 - TBR1

32

TBR7

See Pin 26 - TBR1

33

TBR8

See Pin 26 - TBR1

34

CRL

A high level on CONTROL REGISTER LOAD loads the control
register. See Figure 5.

35

PI·

A high level on PARITY INHIBIT
inhibits parity generation, parity
checking and forces PE output
low.

36

SBS·

A high level on STOP BIT SELECT selects 1.5 stop bits for a 5
character format and 2 stop bits
for other lengths.

37

CLS2*

These inputs program the CHARACTER LENGTH SELECTED.
(CLS1 low CLS2 low 5-bits)(CLS1
high CLS2 low 6-blts)(CLS1 low
CLS2 high 7-bits)(CLS1 high
CLS2 high 8-bits)

38

CLS1*

See Pin 37 - CLS2

39

EPE'

When PI is low, a high level on
EVEN PARITY ENABLE generates and checks even parity. A
low level selects odd parity.

40

IM6402-TRC
IM6403-XTAL

The TRANSMITIER REGISTER
CLOCK is 16X the transmit data
rate.

'See Table 2 (Control Word Function)

INTERBIL'S SOLE AND EXCLUSIVE WARRANTY OSLiGATION WITH RESPECT TO THIS PRQOUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDmoN OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE:AI/ typ/f:8I"-""vobHn_butsrenottos/sd.

11-32

ao~oll.

IM6402/IM6403

i

GI

....

o

Table 2: Control Word Function
CONTROL WORD
CLS2

CLS1

PI

EPE

SBS

L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H

L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H

L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
H
H

L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

X
X
L
L
H
H

X
X
L
L
H
H

X
X
L
L
H
H

X
X

....N

DATA BITS

PARITY BIT

STOP BIT(S)

5
5
5
5
5
5
6
6
6
6
6
6
7
7
7
7
7
7

ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED

1
1.5
1
1.5
1
1.5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2

8
8
8
8
8
8

iGI
....
oto)

x = Don't Care
Output data is clocked by TRClock, which is 16 times the
data rate. A second pulse on TBRLoad loads data into the
transmitter buffer register. Data transfer to the transmitter
register is delayed until transmission of the current character is complete. Data is automatically transferred to the
transmitter register and transmission of that character begins.

TRANSMITTER OPERATION
The transmitter section accepts parallel data, formats it
and transmits it in serial form (Figure 7) on the TROutput
terminal.

5-8 DATA BITS

."TARTS'\

,\

1.11/2 OR 2 STOP BITS

~I::;=:;:::;:~!=:;:::;:::;~~I_tl=~!; j l _
I~l
IMSBhl I!

L

L~;;TV

III

*If ENABLED

0374-8

Figure 7: Serial Data Format
TRE _ _ _

Transmitter timing is shown in Figure 8. Data is loaded
into the transmitter buffer register from the inputs TBR1
through TBR8 by a logic low on the TBRLoad input. Valid
data must be present at least tDS prior to and tDH following
the rising edge of TBRL. If words less than 8 bits are used,
only the least significant bits are used. The character is right
justified into the least significant bit, TBR1. The rising edge
of TBRL clears TBREmpty. 0 to 1 clock cycles later, data is
transferred to the transmitter register, TREmpty is cleared
and transmission starts. TBREmpty is reset to a logic high.

~_~-;t:::::t::::::::::::;h
A

D

\'NDOF
LAST
STOP81T

0374-9

Figure 8: Transmitter Timing (Not to Scale)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAA USE.

NOTE: All typical values have been characterized but are not tested

11-33

.
!
..

S IM6402/IM6403
CD

-! I- 71 a.OCK CYClES

BEGINNING OF RRST STOP BIT"

C\II

o

RRI

CD

DATA

'rl1
I '----

RBRl-8,OE,PE----...;...--------~X"'_ _ _ _ _ __

!

~J
1

L
Ioof--------r-JI
~ _______~----------------~x---------I
-I ~ 1

OR----I

CLOCK CYCLE

A B C

0374-10

Figure 9: Receiver Timing (Not to Scale)

RECEIVER OPERATION

TYPICAL APPLICATION

Data is received In serial form at the RI input. When no
data is being received, RI input must remain high. The data
is clocked by the RRClock, which is 16 times the data rete.
Receiver timing is shown in Figure 9.
A low level on 15Rl=ieset clears the DReady line. During
the first stop bit, data Is trensferred from the receiver register to the RBRegister. If the word is less than 8 bits, the
unused most significant bits will be a logic low. The output
charecter is right justified to the least significant bit RBR1. A
logic high on OError indicates an overrun which occurs
when DReady has not been cleared before the present
character was transferred to the RBRegister. A logic high
on PError indicates a parity error. % clock cycle later,
DReady is set to a logic high and FErrer is evaluated. A
logic high on FError indicates an Invalid stop bit was received. The receiver will not begin searching for the next
start bit until a stop bit is received.

Microprocessor systems, which are inherently parallel in
nature, often require an asynchronous serial interface. This
function can be performed easily with the IM6402/03
UART. Figure 11 shows how the IM6402 can be interfaced
to an IM80C48 microcomputer system.
In this example the characters to be received or trensmitted will be eight bits long (CLS 1 and 2: both HIGH) and
transmitted with no parity (PI:HIGH) and two stop bits
(SBS:HIGH). Since these control bits will not be changed
during operation, Control Register Load (CRL) can be tied
high. Remember, since the IM6402/03 is a CMOS device,
all unused inputs should be tied to either VDD or Vss
The baud rate at which the transmitter and receiver will
operate is determined by the IM4702 Baud Rate Generator.
To ensure consistent and correct operation, the IM64021
03 must be reset after power-up. The Master Reset (MR)
pin is active high, and can be driven reliably from a Schmitt
trigger inverter and R-C delay. In this example, the IM80C48
is reset through still another inverter. The Schmitt trigger
between the processor and RoC network is needed to assure that a slow rising capacitor voltage does not re-trigger
RESET. A long reset pulse after power-up (- 20ms) is required by the processor to assure that the on-board crystal
oscillator has sufficient time to start.
If parity is not inhibited, a parity error will cause the PE pin
to go high until the next valid character is received.
A framing error is generated when an expected stop bit is
not received. FE will stay high after the error until the next
complete character's stop bit is received.
The overrun error flag is set if a received character is
transferred to the RECEIVER BUFFER REGISTER when
the previous character has not been read. The OE J)irLwill
stay high until the next received stop bit after a DFiR is
performed.

START BIT DETECTION
The receiver uses a 16X clock for timing. (See Figure 10.)
The start bit (A) could have occurred as much as one clock
cycle before it was detected, as indicated by the shaded
portion. The center of the start bit is defined as clock count
7%. If the receiver clock is a symmetrical square wave, the
center of the start bit will be located within ± % clock cycle,
±Va2 bit or ±3.125%. The receiver begins searching for
the next start bit at the center of the first stop bil

CLOCK

COUNT1112

DEFINED
CENTER OF
STARTalT

0374-11

Figure 10: Start Bit Timing

INTERSIL'S SOLE AND EXCWSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AD typicM V8/utI$ hav. been ~ but.,. not *"IfId.

11-34

.D~OI!..

IM6402/IM6403

i

o
...
oII)

....
i

~
xrAL

S,

r1

~ ~

Co)

xrAL

Co I--

It

So

~ ~

til i

l

xrAL

-

1St

...oo

+&

j

01 1...1

xrAL

TRC aRC EPI!

PI

eLI, r---+&

....

/

SFD

11

CLIo r-+&

+ 5 - CRL
WI

TiiiL

11

r-

III8OC48
P.,

+5
-~~

220K

rt>-

rL

11

iiEiii

DAR
RRD

2

DII'>7

J
18

1

- ...

•
8

1-

TAD _TRANSMIT
DATA

RRI _RECEIVE

DATA

T8R,..
RBR,..
MR

......

I...

T8RE
DA

0,.1

0374-12

Figure 11: IM80C48 Interface to IM6402

•
INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIeD WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vs/ues hSV8 bHn chsrscterized but are not tested.

11-35

: ICL232
~

!:!

+5

Volt Powered Dual RS-23
TransmitterIReceiver
GENERAL DESCRIPTION
The ICL232 is a dual RS-232 transm
tions. It
face circuit that meets all EIA RS-232C
requires a single + 5V power supply, and features two onboard charge pump voltage converters which generate
+ 10V and -10V supplies from the 5V supply.
The drivers feature true TTL/CMOS input compatibility,
slew-rate-limited output, and 300 ohms power-off source
impedance. The receivers can handle up to ± 30 volts, and
have a 3 to 7 kilohms input impedance. The receivers also
have hysteresis to improve noise rejection.

•
•
•
•
•
•

Meets All RS-232C Specifications
Requires Only Single + 5V Power Supply
On board Voltage Quadrupler
Low Power Consumption
ESD Protection > 2000V
2 Drivers
- ± 9V Output Swing for + 5V Input
-300 Ohms Power-off Source Impedance
-Output Current Limiting
- TTL/CMOS Compatible
-30 VIus Maximum Slew Rate
• 2 Receivers
-±30V Input Voltage Range
-3 to 7 kohms Input Impedance
-o.5V Hysteresis to Improve Noise Rejection
• All Critical Parameters are Guaranteed Over the
Entire CommerCial, Industrial and Military
Temperature Ranges

Typical Applications
Any System Requiring RS-232 Communications Port:
• Computers-Portable and Mainframe
• Peripherals-Printers and Terminals
• Portable Instrumentation
• Modems
• Dataloggers

ORDERING INFORMATION
Temperature
Range

Part
ICL232CPE

O'C to

+ 70'C

ICL232CJE

Package

C1+

16 Pin Plastic DIP

Vee

V+

16 Pin CERDIP

ICL2321PE

- 25'C to

+ 85'C

-55'C to

+ 125'C

ICL2321JE
ICL232MJE

16 Pin Plastic DIP

C1-

16 Pin CERDIP

C2+

16 Pin CERDIP
C2-

C1+

II

V+

IT

[I
C2+ [I

'-../

~GND

!ill

C1-

C2- [ [
V- [ [
T20UT

IT

R21N [ [

V-

~Vee

INTERSIL
ICL232

T20UT

T1 OUT

~R1IN
~R10UT
~T1IN

R21N

iIID T21N

~ R20UT

0100-1

Figure 2: ICL232 Functional Diagram
0100-2

Outline Drawing (PE, JE)
Figure 1: Pin Configuration

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
301600-001

NOTE; All typical values have been characterized but are not tested.

11-36

IID~OIL is

ICL232

r"

N

61

Storage Temperature Range •....•..••. - 55°C to + 150"C N
Lead Temperature (Soldering, 10 sec) .••......... + 300"C
Operating Temperature Range
ICL232C •...•...••••..•••........••...• O"C to + 70"C
ICL2321 .........•.....•.•.......... - 25°C to + 85°C
ICL232M .............•..........•. - 55°C to + 125°C

ABSOLUTE MAXIMUM RATINGS
Vee to ground .......•........•.•..••••••...•. +6 Volts
V+ to ground .••.•.......................... + 12 Volts
V-toground •.••••.••...••.••.............. -12Volts
Input Voltages
Ttin, T2in··· ......•.••.....•..•• -0.3 to (Vee + 0.3V)
R1in, R2in .•••.••.....•....•.................. ±30V
Output Voltages
T10UT' T20uT ....•.•.••.•.• (V+ +0.3) to (V- -0.3V)
R10UT, R20UT .. · ............... -0.3 to (Vee + 0.3V)
Short Circuit Duration
Tt OUT, T20UT .•.......................... Continuous
Continuous Total Power Dissipation (Ta = 25°C)
CERDIP Package •..•..••.•.•••••••.•••..•... 500mW
derate 9.5 mW/oC above 70"C
Plastic Package ....•....•..•.•••.•.••..••••.• 375mW
derate 7.0 mW/oC above 70"C

NOTE:

Str9ssfJs

sbol/fl those IIst9d undBr "AbsoIuIB MBxJmum Ratings"

msy cause (JfJfI1IIInsnt dsmags to the dsvlcs. These IJIfJ stress ratings only
and functional operation of Ihe _
at /hess or any other conditions
abol/fl those IndIcstsd In Ihe operatlonsl ssctIons of Ihe spscificstlons is not
/mpI/sd. Exposure to sb80IuIB maximum rating conditions for sxtsnded periods msyaffect dsvics rsIIsbiIIty.

ELECTRICAL CHARACTERISTICS Test Conditions: Vee = + 5V, Ta = operating temperature range,
Test Circuit as in Figure 3 (unless otherwise specified)
Symbol

Parameter

TOUT

Transmitter Output Voltage Swing

T10UT' T20UT loaded with
3 kO to ground

lee

Power Supply Current

Outputs Unloaded, Ta = 25°C

VIL

Tin, Input Logic Low

VIH

TIn, Input Logic High

Ip

Logic Pullup Current

Yin

RS-232 Input Voltage Range

T1 in, T2in

Typ

Max

±5

±9

±10

V

5

10

mA

0.8

V

200

p.A

+30

V

7.0

kO

= OV

V
15

-30

= ±3V, ±25V
= 5.0V, Ta = 25°C
Vee = 5.0V, Ta = 25°C

Rln

Receiver Input Impedance
Receiver Input Low Threshold

VILH

Receiver Input High Threshold

Vhyst

Receiver Input Hysteresis

VOL

TTL/CMOS Receiver Output Voltage Low

lout

VOH

TTL/CMOS Receiver Output Voltage High

lout

Yin

3.0

5.0

Vee

0.8

1.2

0.2

= 3.2mA
= -1.0mA

tpd

Propagation Delay

RS-232 to TTL or TTL to RS-232

SR

Instantaneous Slew Rate

CL = 10 pF, RL = 3 kO,
Ta = 25°C (Note 1, 2)

SRt

Transition Region Slew Rate

RL = 3 kO, CL = 2500 pF Measured
from +3Vto -3Vor -3Vto +3V

Rout

Output Resistance

Vee

RS-232 Output Short Circuit Current

T1out, T20ut shorted to GND

Iso

Units

Min

2.0

VIHL

NOTE 1:
2:

Umlts

Test Conditions

= V+ = V- = OV, Vout = +2V

3.5

V

1.7

2.4

V

0.5

1.0

V

0.1

0.4

V

4.6

V

0.5

p.s
30

3
300

Vlp.s
Vlp.s
0

±10

mA

Guaranteed by design.
See Figure 5 for deflnHlon.

INTERSIL·S SOLE AND EXCLUSIVE WARRANlY OaUGATION WITH RESPECT TO THIS PRODUCT SHALL aE THAT STATED IN THE WARRANTY ARTICLE OF THE OONomoN OF SALE.
THE WARRANlY SHALL BE EXCLUSIVE AND SHALL aE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE:AHtyplcsl_"" ... bHn _ b u t , . . " not tss1Bd.

11-37

III

= ICL232

1Il0lR!J1J1fiOIL

(\I

2

TYPICAL PERFORMANCE
CHARACTERISTICS
550,----,---,----,
500 FI-."",-",,",+--,--'--+--,-'-~
450
400

- I - . - ' .,.
I

CONDIlIONS:

0) TA=+2S"C

~

S PPLY

'

b) EXT£RNAL SUPPLY ,
LOAD 1 k.Q BETWEEN

+

,

,
""""-'
.,. ..
,

+:

350 f-c- v+ ONO OR .,. GIlD -+__--1
0) TRANSMITTER OUTPU)S
,
300 r- OP£N C1Rcurr ~ GUARANTEED ~
250
• OP£RAllNG. ,

r::=::::tV+~SU~P~PL;;,Y_RA~NIG_E......
-'-:-~:
_~

200 I-

150 '--_ _
3
4

~

...

-

-L..._~__I_~_...J

5

6

INPUT SUPPLY VOLTAGE VCC(VOLTS)
0100-3

0100-5

Figure 3: General Test Circuit

V +. V - Load Impedances vs Vee.

10,--,--"""""",,-,
9~~~~+-+++-+-+-+-~

6~r-r-+-~~~~~~~

5~~~-+-+~~~~~

4

1 2 3 4 5 6 7 8 9 10

IILOAD I (mA)
0100-6

V +. V - Output Voltages vs Load Current.
0100-4

Figure 4: Power-Off Source Resistance
Configuration

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: Alllyplcsi values hsV8 been characterized but 81'9 not tested.

11·38

ICL232
DETAILED DESCRIPTION

Transmitters

The ICL232 is a dual AS-232 transmitter/receiver powered by a single + 5V power supply which meets all EIA AS232C specifications and features low power consumption.
The functional diagram (Figure 2) illustrates the major elements of the ICL232. The circuit is divided into three sections: a voltage quadrupler, dual transmitters, and dual receivers.

The transmitters are TIL/CMOS compatible inverters
which translate the inputs to AS-232 outputs. The input logic threshold is about 26% of Vee, or 1.3V for Vee = 5V. A
logiC 1 at the input results in a voltage of between - 5V and
V - at the output, and a logic 0 results in a voltage between
+5V and (V+ -0.6V). Each transmitter input has an internal 400 kilohm pullup resistor so any unused input can be
left unconnected and its output remains in its low state. The
output voltage swing meets the AS-232C speCification of
± 5V minimum with the worst case conditions of: both transmitters driving 3kohm minimum load impedance,
Vee = 4.5V, and maximum allowable operating temperature. The transmitters have an internally limited output slew
rate which is less than 30V / us. The outputs are short circuit
protected and can be shorted to ground indefinitely. The
powered down output impedance is a minimum of 300
ohms with ±2V applied to the outputs and Vee = OV.

Voltage Converter
The voltage quadrupler contains two charge pumps which
use two phases of an internally generated clock to generate
+ 10V and -10V . During phase one of the clock, capacitor
C1 is charged to Vee. During phase two, the voltage on C1
is added to Vee, producing a signal across C2 equal to twice
Vee. At the same time, C3 is also charged to 2Vee, and then
during phase one, it is inverted with respect to ground to
produce a signal across C4 equal to -2Vee. The voltage
converter accepts input voltages up to 5.5V. The output impedance of the doubler (V+) is approximately 200 ohms,
and the output impedance of the inverter (V -) is approximately 450 ohms. The test circuit (Figure 3) uses 22 uF
capacitors for C1-C4, however, the value is not critical. Increasing the values of C1 and C2 will lower the output impedance of the voltage doubler and inverter, and increasing
the values of the reservoir capacitors, C3 and C4, lowers
the ripple on the V+ and V- supplies.

Receivers
The receiver inputs accept up to ± 30V while presenting
the required 3 to 7 kilohms input impedance even if the
power is off (Vee = OV). The receivers have a typical input
threshold of 1.3V which is within the ± 3V limits, known as
the transition region, of the AS-232 specification. The receiver output is OV to Vee' The output will be low whenever
the input is greater than 2.4V and high whenever the input is
floating or driven between +0.8V and -30V. The receivers
feature 0.5V hysteresis to improve noise rejection.

'",,-T1 OUT' T20UT

]
tf

90%
.;.10..%
..
, _ _ __ rr-VOH
It - I
VOL
r -l

I-

0100-7
0100-8
Instantaneous Slew Rate (SR)

= (0.8) (Voh Ir

VOl) or (0.8) (Vol - Voh)
tf

Average Propagation Delay

Figure 5: Slew Rate Definition

= "'hi ; tplh

Figure 6: Propagation Delay Definition

D

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUOING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been c/Jarsctsrizsd but are not ffl$tfId.

11-39

: ICL232

...
C\I

g

In applications requiring four RS-232 inputs and outputs
(Figure 8). note that each circuit requires two charge pump
capacitors (C1 and C2) but can share common reservoir
capacitors (C3 and C4). The benefit of sharing common reservoir capaCitors is the elimination of two capacitors and the
reduction of the charge pump source impedance which effectively increases the output swing of the transmitters.

APPLICATIONS
The ICL232 may be used for all RS-232 data terminal and
communication links. It is particularly useful in applications
where ± 12V power supplies are not available for conventional RS-232 interface circuits. The applications presented
represent typical interface configurations.
A simple duplex RS-232 port with CTS/RTS handshaking
is illustrated in Figure 7. Fixed output signals such as DTR
(data terminal ready) and DSRS (data signaling rate select)
is generated by driving them through a 3 k!l. resistor connected to V+.

+5V>-----.....- - - - - .

~...........-¥o",,""". DTR (20) DATA

3k.n

T
T
L
/
C
M

o
5

C2 +
22J.LF I
N
P TO
U
T
RTS
S
0
U RD
T
P CTS
U
T
5

3k.n

C4
.![,22J.LF
tl

T1

14
T2

10
12
9

7
13

R2

TERMINAL READY

......W\r-.DSRS (24) DATA

INTERSIL
ICL232

Rl

8

15

SIGNALING RATE SELECT
RS- 232
INPUTS .Ie OUTPUTS

TO (2) TRANSMIT DATA
RTS (4) REQUEST TO SEND
RD (3) RECEIVE DATA
CTS (5) CLEAR TO SEND

SIGNAL GROUND (7)
0100-9

Figure 7: Simple Duplex RS-232 Port with CTS/RTS Handshaking

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values haVB bun chsrscterind but are not tested.

11-40

IIlD~On.

ICL232

n
r~

Col
~

4
Cl +
22}'F _

INTERSIL
ICL232

3

I
N
T P TO
T U
L T
RTS
/ S

11

5

Tl

14
T2

10

13

12

e 0
M U RD
oT
S P CTS
U
T
S

9

7

Rl

R2

8

+C2
- 22}'F

TO (2) TRANSMIT DATA
RTS (4) REQUEST TO SEND
RD (3) RECEIVE DATA
CTS (5) CLEAR TO SEND

15
16
+5V

y

2

C4

...cJ-

v- v+

-= 47}'F

2
16

RS-232
INPUTS &: OUTPUTS

4
Cl +
22}'F _
I
N
T P DTR
T U
L
/
C
M

T DSRS
S
0
U oeD
oT
S P RI
U
T
S

DTR (20) DATA TERMINAL READY
DSRS (24) DATA SIGNAUNG RATE SELECT
12

9

DCD (8) DATA CARRIER DETECT
R2

8

15

RI (22) RING INDICATOR

SIGNAL GROUND (7)
0100-10

Figure 8: Combining 2 ICL232 for 4 Pairs of RS-232 Inputs and Outputs

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPREss, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AIlIypIcsJ values have been chsrscteriz6d but (lI6 not testsd.

11·41

III

Section 12 -

Digital Signal
Processing
IM29C128 ............. 12-1
IM29C510 ............. 12-7
EVK-128 ............. 12-19

U~U[61n

IM29C128

Finite Impulse Response
Filter Controller

...N

CD

GENERAL DESCRIPTION

FEATURES

The 16 bit RR Filter Controller (FFC) provides all the data hislOly,
and programmable filter cycle control logic required to
implement FIR filters of up to 128 filter points. When used in conjunction with an extemal lliter coefficient memory, of up to 128
words by 16 bits, and an indualry standard 16 bit Muhiplier-AccumuIaIor (MAC), the FFC provides the system designer with the ability
10 implement a ~I FIR fiher with onlythrae 1Cs. The FFC pro.
vides all the control signals required to operate the MAC and the
coefficient memory as trI-lllateabie devloes, allowing multiplexed
uaage of theaa resources. The FFC's asynchronous interface
enables easy Integration of the FIR filter In any system environment. It incorporates a 16 bit data 110 path, a 128 word by 16 bit
RAM memory, and programmable filter control logic capable of
handling filter order lengths of up to 128 points.

• FIR Filter Building Block
• Filter Ord... from 1 to 128 Points
• 128 Wolda by 16 BIt Oats Memory

SIorage

• Works with IM29C510 Multlpll.r-Accumulator (MAC) or

EquIvIilent
• lOna Minimum Riter Cycle Period with 25 MHz Master

Clock Input
• Low Power CMOS 'lKhnology
• Full nL Compatibility
• .. Pin PLCC and 84 Pin DIP

ORDERING INFORMATION
PART
NUMBER

IM29CI29CD64
1M29C128MD64
IM29CI28CN68

leI

..~.

.. ....

.,..,
.UOfl..

. _-_.
::1Ir
........ .....,..
...... ..
.~.

IICt
ICe

........
.."..
DwI'.
.."..
.."'"
,."
........
........

DIP
DIP
PLCC

MPQMl

Me'
........

..... " .

O'Cto +70"C
-55"C to +125"C
O'C to +7O"C

••

IC •

...,.."

PACKAGE

:::-

': ;
.......
..... M.

.."..

TEMPERATURE
RANGE

.....
__ I

11_,
- - ,,-,
__ •

...... "
.."..

.."..

.."..

=~::
......

. '"

.,a.u,
..CUIfI

.......

.. CMOI

"ICC

L~"--_"'-_".

~=_r--"1..c'-"'<-

GOUT

....

"lIeU

_""14,
" ""

........._ _oS' . . ..

....

84 Lead DIP

_.. ............... .....
.....
.........55,......
-............
............
..........
imiii iiihulin,.

_'P
_,a

"'IL'::

,

.. .. w

I

,

.'''0

.....

~

--~-f=----I

____oJ

_.

,

a .. .

,

n ...'

• • • • • • • !:

•

~~============~

"1,;111 •••

iiiiiiUmmm
88 Conhlct PLCC

Figure 1: Pin Conflguratlon8

Figure 2: Functional Diagram
0106-1

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORV. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
601100-002
NOTE: AU typicIII VBIuB8 hBve bHn chsrsctstiztId but Me not tsstsd.

12-1

= IM29C128
i ABSOWTE MAXIMUM RATINGS
I

DC Supply Voltage (VDO) ................. -0.5 to +7 Volts
Input/Output Voltage (V,JVOUT) ....•.. -().3 to Voo +().3 Volts
Storage Temperatura (TSTG) ............... -66 to + 150"C

DC ELECTRICAL CHARACTERISTICS
TA - -55"C to + 125"C MIL, TA - -4O"C to +66"C INO, TA • OOC to +70"C INO
PARAMETER
Low Level Input Voltage

MIN

V'L
V'H

~h Level Input Voltage

2

SYMBOL

LKOnIy
Low Level Output \IIII18g8

3

ao

I'L,I'H
IOZ

High l.eliel Output Voltage
Input L8aI<8ge Curren!
3 b__ output Leakage l;UI'l8l1l

100

operating Currem

VOL
VOH

TYP

0.15

MAX

UNIT

0.8

V

CONDITIONS
- 4.5

VOUT
10H Vour
IOH -

0.4

VIN - Vi/M
10 -a
IOL- 4.omA

4.7

-I
-I
40

0
·05
0

+1
+1

!A
!A

50

mA

V'N - OorVOO
VOUT - OorVOO
MCLK - 25MHz

SM " Note,
" Paragraph 5.8.1 T,mlng ReIen!nce Inputs when they SWitCh, either VIL or VIH Outpull 1.5V.

AC CHARACTERISTICS (See Figura 4)
Note: TA - -55'Cto +125'CMiI., V'HM'N'- 2.4\/, VIHMINCLK - 35\/, TA - +40'Cto +85'Clnd .. V'LMAX - 0.4\/, V'LMAXCLK - 0.4\/, TA - O'Cto +70'CCom ..
Vcc - 5'(N ±IO%, Output Load Cap - 50 pF Max.

SYMBOL

DESCRIPT'ION

MIN

Master Clock (MCLI<) Cycle PerIod
MCLK High Period
MCLK Low Pariod
FCLK High from MCLK
FCLK Low from MCLK
STEN Set-Up Time Before Start
STEN Hold Time Aller Start
Start Hold Time
Data Input (DIN) Sat-Up Time Before Start
Data Input Hold Time Aller Start
TO'H
Status High from Start (MCLK High)
TSSH
Status High from MCLK (Start High)
TSMH
Statu. Low from MCLK (End 01 Cycle)
TSHL
TON
0EliI Low to DOUT and CADD Outpull Active (On)
0EliI High to DOUT and CAOD Outpull 011 (Hi.z)
TOFF
I 0EliI Low to Cu<4

X V,S Y,4 V,3 Y,2 Y,1 Y,o YI Va Y7 Va Va
-

_ Ps4
-24 23

Xs

X2

X,

Y..

Va

2-12- 2- 2- 2- 2- 2- 2- 2- 2-1 2-112-1

VI

2'

IGNAL

Y,

Yo SIGNAL

-1 2- 1 2-1 DIGIT VALUE

Pu Pa1 PaD P29 P28 P27 PH Pm PM Pm P22 Pt1 P20 Pta P,e P17 P,e
22

>Co

- 2- 2- 2-1 2-112-1 2-1 2- 1 2-1 DIGIT VALUE

PHS

Pt. P,a

P12 P'1 P,e

20 2-1 - 2- 2-42- 2- 2- 2- 2-92-1 2-112-1 2-1 2-1 2-1 2-1 2-172-18 2-1 2-

PII

Pe

2-212-

MSP

P7

Pe

2-23 2-

Ps

P4

2-26 2-

Ps
2-

P2

P,

2-282-

Po SIGNAL
2-3 DIGIT VALUE

LSP

Fractional Unsigned Magnitude Notation
BINARY POINT

x,.

X,
X
2-12- -

v's Y'4 YUt Y,2 Yn

X

x..

x

X, X,1 X,D Xg Xe
Xe Xs
Xs Xa x, >Co SIGNAL
2- 2- 2- 2-72- 2- 2-1 2-112-1 2-132-1 2-1 2-1 DIGITVAWE

Y,o VII Va Y7 VB

Vs

Y.. Va VI Y, Yo SIGNAL
-112-12-132-12-12- 1 DIGIT VALUE

2-12- 2- 2- 2- 2- 2- 2- 2- 2-1

P34
Pst Pat Pao Pn PH P27 P P PM Pm P22 Pat P20 P,a P'8 P'7 P,a PHi Pt4 Pta P'2 P,t PtO Pi P8 P7 P6 PIj P4 Pa P2 P, Po SIGNAL
22 21 20 2-12- 2- 2- 2- 2- 2- 2- 2- 2-1 2-112-1 2-1 2-1 2-1 2-1 2-17 2-18 2-1 2- 2-212-22 2- 2- 2-2 2- 2- 2-2 2- 2- 2-S1 2-92 DIGIT VALUE

MSP

XTP

LSP

Integer Two's Complement Notation
BINARY POINT

. ,.
,.
,. . ,.
"
"
.,
,. " " ,. " . ,.

X" X" Xl1 X" X.
-2151214 2" 2" 211 2"

Xs

,. ,.

x,

,. ,. "'"

X,

V,

V,

v, v, v, v,

V,

V,

I Ps4IPsa1PuIPa,IP30 P29 P28 P27 PH PH PM P29 P22 P" p" P" P" P17 P" P" P" P" P" Pl1 P" P,
-2341299 232 231 aso _ 228 227 228 2e 224 z2S 222
220 219 2" 217 2" 215 2" 2" 2" 211 2"

P,

P,

p.

X,

x"
v"

V"

X

-2151214

V" Y,2 Y11 V"
2" 2" 211 2"

,.,

XTP

I

I

MOP

2'

2'

Xs

x,

X.

2'
P,

P,

P,

2'

2'

,.
,.

P,
2'

Po SIGNAL
,. 0 IGITVALUE

x, >CoSlGNAl
2'

v,

DIGIT VALUE

Vo SIONAL
DIGIT VALUE

LSP

Integer Unsigned Magnitude Notation
BINARY POINT
X,1i X,4 X,S X,2 X,1 X,0 Xg Xs x, ""
215 214 2" 212 211 210 29
27 28

"

X

... ,.,

Pa4 Pas Pu Pa, Pao PH P28 P27 ft~1 p.lpM Pu P22 P,
234 28S 292 231 230 229 228 227
XTl'

I

'" ...

224 229

MSP

,.

,.x, ",x,,,, x, ,.
"

Xo SIGNAL

.. 2' 2'

,.

DIGITVAWE

. ,.

Y,S Y,4 Y,s Y,2 Y11 Y,0 Ya Y8 Y7 Ya Vs V4 Va Y2 V, Vo SIGNAL
215 214 2" 212 211 2"
2' 2' 2'
2'
2' 20 DIGITVAWE

.,

.. ,.

P, P, P, P, p. P, Po SIGNAL
P20 P'9 Pt8 P'7 P" P" P" P" P" Pl1 P" P, P,
220 219 2'8 2'7 2" 2" 2" 2" 2" 2" 2" 2'
2' 2'
2'
2' 20 DIGITVAWE
I
LSP

"

The RND, TC, ACC, and SUB inputs are registered with
all four bits clocked in at the rising edge of the logical OR of
both ClK X and ClK Y. If normally HIGH clock signals are

,.

used, special attention to the clock signal is required. loading problems of these four control signals can be avoided
by the use of normally lOW clocks.

Table 4
Name

Function

DIP Package

PLCC Package

TSX
TSM
TSl
PREl
RND
TC
ACC
SUB

XTP Three-State Control
MSP Three-State Control
lSP Three-State Control
Preload Control
Round Control Bit
Two's Complement Control
Accumulate Control
Subtract Control

Pin 47
Pin 45
Pin 55
Pin 46
Pin 54
Pin 48
Pin 52
Pin 53

Pin 22
Pin 24
Pin 11
Pin 23
Pin 12
Pin 21
Pin 14
Pin 13

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCWSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED DR STATUTDRV, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.
NOTC: AU typicN valutls htwfI bsBn charIlcttJrIzsd but IIf6 not 1fIBtBd.

12-14

IM29C510

.O~OIl.

i

PLCC Package

8CII
...o

Table 5: Pin Assignments
Pin Name

Function

I

Xe
Xs
X4
X3
X2
X1

Xo
po-Yo

X Input LSB
ProductlY Input LSB

P1-Y1
P2-Y2
P3-Y3
P4-Y4
Ps-Ys
Pe-Ye
PrY7
GND
Ps-Ys
Pg-Yg
P1Q-Y10
P11-Y11
P12-Y12
P13-Y13
P14-Y14
P1S-Y15
P1e
P17
P1S
P19
P20
P21
P22
P23
P24
P25
P26
P27
P2S
P29
P30
P31
P32
P33
P34
CLKP
TSM
PREL
TSX
TC
Voo

Input/Output

ProductlY Input MSB

Product MSB
Clock Product Register
MSP Three-State Control
Preload Control
XTP Three-State Control
Two's Complement Control
Positive Supply Voltage

I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Ground
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
I
I
I
I
Voo

DIP Package
Pin 1
Pin2
Pin 3
Pin4
Pin 5
Pin 6
Pin 7
Pin 8
Pin9
Pin 10
Pin 11
Pin 12
Pin 13
Pin 14
Pin 15
Pin 16
Pin 17
Pin 18
Pin 19
Pin 20
Pin 21
Pin 22
Pin 23
Pin 24
Pin 25
Pin 26
Pin 27
Pin 28
Pin 29
Pin 30
Pin 31
Pin 32
Pin 33
Pin 34
Pin 35
Pin 36
Pin 37
Pin 38
Pin 39
Pin 40
Pin41
Pin 42
Pin 43
Pin 44
Pin 45
Pin 46
Pin 47
Pin 48
Pin 49

Pin 1
Pin 68
Pin 67
Pin 66
Pin 65
Pin 64
Pin 63
Pin 62
Pin 61
Pin 60
Pin 59
Pin 58
Pin 57
Pin 56
Pin 55
Pin 53, 54
Pin 52
Pin 51
Pin 50
Pin 49
Pin 48
Pin 47
Pin 46
Pin 45
Pin 44
Pin 43
Pin 42
Pin41
Pin 40
Pin 39
Pin 38
Pin 37
Pin 36
Pin 35
Pin 34
Pin 33
Pin 32
Pin 31
Pin 30
Pin 29
Pin 28
Pin 27
Pin 26
Pin 25
Pin 24
Pin 23
Pin 22
Pin 21
Pin 17, 18, 19,20

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values havs bsen characl9lized but are not tested.

12-15

N

If)

.. IM29C510

.D~UI!..

0

1ft

Co)

0

Table 5: Pin Assignments (Continued)

(\I

!

Pin Name

Input/Output

Function
Clock Input Data Y
Clock Input Data X
Accumulate Control
Subtract Control
Round Control Bit
LSP Three-State Control
X InputMSB

CLKY
CLKX
ACC
SUB
RND
TSL
X15
X14
X13
X12
X11
X10
Xg
Xa
X7

DIP Package

PLCC Package

Pin 50
Pin 51
Pin 52
Pin 53
Pin 54
Pin 55
Pin 56
Pin 57
Pin 58
Pin 59
Pin 60
Pin 61
Pin 62
Pin 63
Pin 64

Pin 16
Pin 15
Pin 14
Pin 13
Pin 12
Pin 11
Pin 10
Pin 9
Pin 8
Pin 7
Pin 6
Pin 5
Pin4
Pin 3
Pin 2

THREE
STATE
CONTROL
OUTPUT ------~__=.,.,..,==~~=J(
THREE
STATE _ _ _ _- J
0085-4

0085-5

Figure 3: Setup and Hold Time

Figure 4: Three-State Control Timing Diagram

INPUT

INPUT
CLOCK
OUTPUT
CLOCK
PRELOAD
THREE-STATE
CONTROL
OUTPUT

0085-6

Figure 5: Timing Diagram

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF All OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AJf typical values have been characterized but are not tested

12-16

IM29C510
Table 6: Preload Truth Table
PREL
(Note 1)

TSX
(Note 1)

TSM
(Note 1)

TSL
(Note 1)

XTP

MSP

LSP

L
L
L
L
L
L
L
L
H2
H2
H2
H2
H2
H2
H2
H2

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

Register ~ Output Pin
Register ~ Output Pin
Register ~ Output Pin
Register ~ Output Pin
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
Hi Z Preload
Hi Z Preload
Hi Z Preload
Hi Z Preload

Register ~ Output Pin
Register ~ Output Pin
HiZ
HiZ
Register ~ Output Pin
Register ~ Output Pin
HiZ
HiZ
HiZ
HiZ
HiZ Preload
HiZ Preload
HiZ
HiZ
Hi Z Preload
Hi Z Preload

Register ~ Output Pin
HiZ
Register ~ Output Pin
HiZ
Register ~ Output Pin
HiZ
Register ~ Output Pin
HiZ
HiZ
HiZ Preload
HiZ
Hi Z Preload
HiZ
HiZ Preload
HiZ
HiZ Preload

NOTE 1: PREL, TSX, TSM, and TSL are not registered.
2; PREL HIGH inhibits any change of output register for those outputs in which the three-state control is LOW.

AC TEST CONDITIONS
5000

TO

Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDto3.0V
5 ns
1.5V
1.5V
See Figures 6 and 7

OUTPUT~

PIN

'ft_~ 1

1
-LJ~
Vx=O OR 2.6V

Vee

-=
0065-6

Figure 7: Output Three-State Delay Load

TO
OUTPUT
PIN

o--......--f 84 dB

DIGITAL
NOISE
GENERATOR

COEFFICIENT INPUT

BIDIRECTIONAL I-BUS!

DATA IN

DATA

-

PC
BUS
INTERFACE

M 29C510 X
MAC
Y

~

t

29C128
FFC

COEFFICIENT ADDRESS

COEFFICIENT

1
COEFFICIENT
RAMS

I
0109-1

Figure 1: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
601120-002
NOTE: All typical values hsve been characterized but are not tested

12-19

...~

EVK·128

EDETAILED DESCRIPTION

20-pin header and uses 16 bits of parallel data and a nonoverlapping clock scheme to manage data over the bidirectional bus.
The control pattern for the sample/hold, AID, and 0/ A is
downloaded under software control from the PC, as is the
seed value for the Digital Noise Generator (DNG). Since the
DNG shift register is 20 bits long, the resulting sequence will
exhibit a high degree of randomness.

The EVK-128 is designed to be mapped into a 16-byte
block of addresses in the 110 space of the PC. The base
address is set by means of a DIP switch so as not to conflict
with other boards. An expansion decoding scheme is used
to map these 16 addresses into a 1K block. The first 512
locations are used to address the coefficient RAM, and the
rest are available for control, test, and data transfer functions. The address translation from 16 to 1K is handled by
the provided software.
There are two registers which determine the configuration
of the board: the Filter Order Register (FOR), and the Mode
Register (MR). Bits 0 to 6 of the FOR hold the filter order
(number of taps). Bit 7 is used to give a software reset to
the board. Bits 1 to 3 of the MR are used to select between
the AID, digital noise generator, or external digital inputs.
This scheme gives the flexibility to mix analog and digital
110. Bit 0 is used to enable the external digital output, and
bit 4 is used to select between 1 of 2 possible banks of
coefficient RAM memory. Table 1 shows the addresses for
the various control functions.
The analog sample rate is set internally at 32.727 kHz. An
external clock may be provided through the back connectors in lieu of the internal one, as long as the logiC swing is
between 0 to 5 volts. The external digital connection is via a

Table 1: PC Address Map
Relative
Address

Description

000-1 FE
200,201
202,203
204,205
206,207
206,207
208,209
20A,20B
20C, 200
20E
20F

Load Coefficient RAM
Write Data Word to FFC
Write Filter Order Register
Read Data Word from MAC
Read AID into PC
Write PC into 0/ A
Write Mode Register
Load Digital Noise Seed
Read/Write AID Control Pattern
Start all Operations Except FFC
Start all Operations Including FFC

Table 2: Mode Register Bit Map
Bit #

o

4

3

2

FN

ADM

DNGM

DIM

DOM

Filter
Number
A= 0, B=l

AID
Output
Enable
Mask

Digital
Noise
Enable
Mask

Digital
Input
Enable
Mask

Digital
Output
Enable
Mask

0= Disable

1

= Enable

Table 3: Filter Order Register Bit Map
BIT # r-_7...,._--,_5--.,,....4_ _ _...._2--,_--.,,....0_

I

I

+I

I

I

I

I

I

I

I

"""""""",",""""'<"" II/////////////////

SOFT RESET
0= RESET
1 = ACTIVE

FILTER ORDER 0 - 127

0109-2

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

12-20

.O~OI.l m

EVK·128

Sample plot from filter design software. The plot itself is from the program run on a COMPAQ" and plotted on an OKIDA TA
193, but most common dot matrix printers, like the EPSON, are supported

SPECIFICATIONS FOR A BANDPASS
EQUIRIPPLE
FIR FILTER OF LENGTH 125

10
1

1

1

0 - -1- - + - -1--

End of Lower Stopband (Hz) ......................... 19
Beginning of Passband (Hz) .......................... 21
End of Passband (Hz) ............................... 29
Beginning of Upper Stopband (Hz) .................... 31
Maximum Passband Attenuation (dB) ................. 0.6
Minimum Stopband Attenuation (dB) .................. 72
Although the above plot shows the kind of response possible with less than 128 taps, longer filters can be implemented if non-realtime processing is allowed. Data could be
stored on the computer (e.g., floppy or Winchester) and cycled through the filter board, processing up to 128 taps with
each pass. Furthermore, data recorded offline somewhere
else could be loaded and processed easily via the backplane. The board could also function as a powerful development tool, a pedagogical tool, or, more obviously, as a system for actual data conversion and filtering.

CD

...'"c

-10

I

E
:z
~

2

....J

...~
Do.
VI

-20
-30
-40
-50

1
1
1
- -1--+--1-1
1
1
- -1- - + - -1-1
1
1
- -1- - + - -1-1
1
1
- -1--+- -11
1
1
--1--+--11
1
1
--1--+--11

--1--+---1-1
1
1
- -1- - +- - - I - 1
1
1
--1--+---1-1
1
1
-1--+---1-1
1
1
-1--+---1-1
1
1
-1--;---1-1
1
1
-1--+---1--

NORMALIZED fREQUENCY
0109-3

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not test«/.

12-21

...~
I\)

co

Section 13 -

Display Drivers
ICM7211
ICM7212
ICM7218
ICM7228
ICM7231
ICM7232
ICM7233
ICM7243

.............. 13-1
.............. 13-1
............. 13-12
............. 13-23
............. 13-36
............. 13-36
............. 13-36
............. 13-55

II

ICM7211/12

4-Digit LCD/LED
Display Driver

GENERAL DESCRIPTION

ICM7211 (LCD) FEATURES

The ICM7211 (LCD) and ICM7212 (LED) devices constitute a family of non-multiplexed four-digit seven-segment
CMOS display decoder-drivers.
The ICM7211 devices are configured to drive conventional LCD displays by providing a complete RC oscillator, divider chain, backplane driver, and 28 segment outputs.
The ICM7212 devices are configured to drive commonanode LED displays, providing 28 current-controlled, low
leakage, open-drain n-channel outputs. These devices provide a SRighTness input, which may be used at normal logic
levels as a display enable, or with a potentiometer as a
continuous display brightness control.
Soth the LCD and LED devices are available with multiplexed or microprocessor input configurations. The multiplexed versions provide four data inputs and four Digit Select inputs. This configuration is suitable for interfacing with
multiplexed SCD or binary output devices, such as the
ICM7217, ICM7226 and ICL7135. The microprocessor versions provide data input latches and Digit Address latches
under control of high-speed Chip Select inputs. These devices simplify the task of implementing a cost-effective alphanumeric seven-segment display for microprocessor systems, without requiring extensive ROM or CPU time for decoding and display updating.
The standard devices will provide two different decoder
configurations. The basic device will decode the four bit binary inputs into a seven-segment alphanumeric hexadecimal output. The "A" versions will provide the "Code S" output code, i.e., 0-9, dash, E, H, L, P, blank. Either device will
correctly decode true SCD to seven-segment decimal outputs.
Devices in the ICM7211/7212 family are packaged in a
standard 40 pin plastic dual-in-line package and all inputs
are fully protected against static discharge.

• Four Digit Non-Multiplexed 7 Segment LCD Display
Outputs With Backplane Driver
• Complete Onboard RC Oscillator to Generate
Backplane Frequency
• Backplane Input/Output Allows Simple
Synchronization of Slave-Devices to a Master
• ICM7211 Devices Provide Separate Digit Select
Inputs to Accept Multiplexed BCD Input (Pinout and
Functionally Compatible With Siliconix DF411)
• ICM7211M Devices Provide Data and Digit Address
Latches Controlled by Chip Select Inputs to Provide
a Direct High Speed Processor Interface
• ICM7211 Decodes Binary Hexadecimal; ICM7211A
Decodes Binary to Code B (0-9, Dash, E, H, L, P,
Blank)

ICM7212 (LED) FEATURES
• 28 Current-Limited Segment Outputs Provide 4-Digit
Non-Multiplexed Direct LED Drive at> SmA Per
Segment
• Brightness Input Allows Direct Control of LED
Segment Current With a Single Potentiometer or
Digitally as a Display Enable
• ICM7212M and ICM7212A Devices Provide Same
Input Configuration and Output Decoding Options as
the ICM7211

ORDERING INFORMATION
Part Number

Temperature
Range

Package

Part Number

Temperature
Range

Package

ICM7211AMIJL

-40·C to + 85·C 40 Pin CERDIP

ICM7212AIPL

-40·Cto +85·C 40 Pin PLASTIC

ICM7211IPL

-40·Cto +85·C 40 Pin PLASTIC

ICM72121PL

-40·Cto +85·C 40 Pin PLASTIC

ICM7211AIPL

-40·Cto +85·C 40 Pin PLASTIC

ICM7212MIPL

-40·Cto +85·C 40 Pin PLASTIC

ICM7211 AMIPL

-40·Cto + 85·C 40 Pin PLASTIC

ICM7212AMIPL

-40·Cto +85·C 40 Pin PLASTIC

ICM7211 MIPL

-40·Cto + 85·C 40 Pin PLASTIC

ICM7212AEVIKIT

ICM7211 AEV IKIT

-

-

EVALUATION KIT

II

EVALUATION KIT

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

13-1

:! ICM7211/12

"......

...
II
&\I

ICM7211 (A)

2

D3

D2

D1

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

OSCILLATOR

11KHz
FREE-

RUNNING

OSCILLATOR

INl'UT

0364-1

ICM7212 (A)
D4
SEGMENT OUTPUTS

D3
SEGMENT OUTPUTS

D2
SEGMENT OUTPUTS

D1
SEGMENT OUTPUTS

0364-2

Figure 1: Functional Diagrams

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE eXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

13-2

a...

ICM7211/12

......
II)

ICM7211(A)M
_

1MOU'TI'IITS

D1

_0UTPUT8

~
II)

DATA
INPUTS

CHIP SELECT 1

CAlp _Lm 2

OSCIUATOR
111KHz
FREE_
_ NO

+128

OICIUATOR
INPUT

BACKPLANE

DRIVER

ENABLE

0364-3

-1M

ICM7212(A)M

-- -- -DI

D2

D1

--

-

DATA

-....
2....

II
0364-4 .

Figure 1: Functional Diagrams (Cont.)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AD typIcsl VBIu8s have bBen chsrsctsrized but BI9 not f6sIed.

13-3

ICM7211/12
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Note 1) ................. 0.5W@70'C
Supply Voltage (Voo- VSS) ....................... 6.5V
Input Voltage (Any Terminal) (Note 2)
............................. VSS -0.3V to Voo+ 0.3V

Operating Temperature Range ......... - 40'C to + S5'C
Storage Temperature Range .......... - 55'C to + 125'C
Lead Temperature (Soldering. 10sec) ............. 300'C

NOTE 1: This limit refers to that of the package and will not be realized during normal operation.
NOTE 2: Due to the SeR structure inherent in the CMOS process, connecting any terminal to voltages greater than Voo or less than Vss may cause destructive

device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same power supply be applied to the device
before its supply is established. and that in multiple supply systems. the supply to the

ICM7211/1CM7212 be turned

on first.

NOTE: Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

.. .,,.....-v- ." ..

. ,, ,.....-v- " e.

...."" ..,
G.

C2 •

D• •

n,

I)

'314
Cl I~
03 I'

31 03
~ 02
)1 01

....,
D' •

.......
m""".
." ...."
...
e.

1317

~4

G3 "
'3 It

U

1041)

.2 ,
C2 •

n.

-

.. C'

e"•

0",1
s...cl
tl\flut.

..

7211M
7211AM

FaU

83 ,.
C3 15

:~n;

It
23 04

03!*

:!tii

c.

E'

c.

A'

.. ,
§

c••

D• •
U

10

»V

7212
72121.

02 "
F212
Al
83 "
Cl 1$

0 ..... ,..

...

.' ....

03 "

• EO

Cl'

".

22 C4

..
"v..
" ..B
AI

A' •

0>

• :~)
.. "
GO

,,.....-v- .. o.
"n" C•

eAf

~

uCftip1Nc11
n~
2 OIgitAddNu8ft2
" 0ItIt o\dchM iii 1

0) "

0.1.

.. ..

Voo

.. D'

G'

:"ooe~MO'
7211
7211A

CO? n
'212
A)

VDD

.. o.
" c.

VOD I

C, •

..." .."..

"'''
Al'

co

n't

300>

2f

~}:!:':I'

....
EO

'

~ 01
C'

.. ..,

"'
'.T"
c.

)l03 0",1
~ 02 Seleel
101 Iftpuh

0364-6

0364-5

, ~ Ii!

Voo •

D• •

n,

~
u

7212M
7212AM

.

CNII Settel 2

~ CfI.s.t.cll

D;gItAddNuBk 2:

)1 OIgkAddNM" 1

.

"13

•, :~ }O"'I~"
"

FlU

. ..
.......

8' u
CS '$
03 "
1317

os

"

~Al
ill
Vss
»~

EO

II

n

Col

0364-7

0364-8

Figure 2: Pin Configurations (Outline Drawing PL)

ELECTRICAL CHARACTERISTICS
ICM7211 CHARACTERISTICS (LCD)

Voo=5V ±10%. TA=25'C. VSS=OV unless otherwise specilied.

Symbol

Parameter

VSUPPLY

Operating Supply Voltage Range (Voo - VSS)

Test Conditions

Min

Typ

Max

Units

3

5

6

V

Operating Current

Test circuit. Display blank

10

50

IOSCI

Oscillator Input Current

Pin 36

±2

±10

tR. tF

Segment Rise/Fall Time

CL =200pF

0.5

tR. tF

Backplane Rise/Fall Time

CL =5000pF

1.5

losc

Oscillator Frequency

Pin 36 Floating

19

kHz

IBP

Backplane Frequency

Pin 36 Floating

150

Hz

100

,..,A

,..,S

ICM7212 CHARACTERISTICS (COMMON ANODE LED)
Symbol

Parameter

VSUPPLY

Operating Supply Voltage Range (Voo - VSS)

Test Conditions

ISTBY

Operating Current
Display Off

Pin 5 (Brightness).
Pins 27-34-Vss

100

Operating Current

Pin 5 at Voo. DisplayallS's

ISLK

Segment Leakage Current

Segment 011

ISEG

Segment On Current

Segment On, Vo= +3V

Min

Typ

Max

Units

4

5

6

V

10

50

,..,A

200
±0.Q1
5

S

mA
±1

,..,A
mA

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

13-4

ICM7211/12
INPUT CHARACTERISTICS (ICM7211 AND ICM7212)
Symbol

Parameter

Test Conditions

Min

Typ

VIH

Logical "1" input voltage

VIL

Logical "0" input voltage

IILK

Input leakage current

Pins 27-34

±.01

CIN

Input capacitance

Pins 27-34

5

ISPLK

BPI Brightness input leakage

Measured at Pin 5 with Pin 36 at Vss

±.01

CSPI

BP/Brightness input capacitance

All Devices

200

AC CHARACTERISTICS -

Units
V

1
±1

/LA
pF

±1

/LA
pF

MULTIPLEXED INPUT CONFIGURATION

1

tWH

Digit Select Active Pulse Width

tos

Data Setup Time

500

tOH

Data Hold Time

200

tlOS

Inter-Digit Select Time

AC CHARACTERISTICS -

Max

4

Reterto Timing Diagrams

/Ls
ns

2

/Ls

MICROPROCESSOR INTERFACE
other Chip Select either held active, or
both driven together

tWL

Chip Select Active Pulse Width

tos

Data Setup Time

100

tOH

Data Hold Time

10

tiCS

Inter-Chip Select Time

2

+

1I1I

200
ns

0
/Ls

-

n- ----------,
-' ~~t ''''''
}'J
ICM7211(A)(M)

, / ~ 5BP

11I1-

EACH SEGMENT
TO BACKPlANE
WITH 200pF
CAPACITOR

......"

1=
I-

OSC36VSS35DIGIT/CHIP { 3 4 } - - Voo ( MICROPROCESSOR)
SELECT 33
VERSIONS
INPUT 32
DATA
INPUTS

;=OU ,-

{29

~

1=

I-

I1-

1-

j

VSS (MULTIPLEXED)
VERSIONS
VDD

,

I

"" t-U------------ JI
:

20

21

'-

0364-9

Figure 3: Test Circuits

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

13-5

II

...
....

~ ICM7211/12
.....
COl

Ii

2

TYPICAL PERFORMANCE CHARACTERISTICS
ICM7211 OPERATING SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

ICM7211 BACKPLANE FREQUENCY AS A
FUNCTION OF SUPPLY VOLTAGE

30

180

ITA:

V

/

/

I'

i 20OC 't

TA=2S0 CT-

10

120

/V

~/

,

~

~V

80

/ &

~ ~ '\. TA=70 C
o

3

,V

",

/'

V

COSC=O
(PIN 36 OPEN) _

i/
,~

/'

V

,/

IL Vcosc = 22pF

- --

30

,~~ V
2

A"

150

J,

I

20

J/

LbDD~ICJs

-TA=25°C

I

LCD DEVICES. TEST CIRCUIT
25 t- DISPLAY Ill.ANK
PIN 36 DPEN

COSC-220pF

o

4

3

1

4

VSUPP (VOLTS)

Vsupp (VOLTS)

0364-11

0364-10

15

ICM7212 LED SEGMENT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

_pl!SA~V~
TA-25°C
./

-

J.-

r-;supp, BV

,/

i--

-

,/

10

If

/V
III!/
'1/

/

I'
~

VSUPP'IV

-

vsuPP' 4V

,,
!J

3

6

VO(VOLTS)
0364-12

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characteriz6d but are not tested.

13-6

IID~DI!..

ICM7211/12
TYPICAL PERFORMANCE CHARACTERISTICS
12
JGME1NT

TA=2SoC

OLTPU~ AT ~ 3V I

1800

/

10

/

J

r
1500 r

I

L~D De!nC~

I
I
DISPLAY ALL EIGHTS
LED FORWARD VOLTAGE DROP
V.LED-1.7V
PIN SAT VDO

I
1200

I

/

1/

600

/

2

300

/

/

j

/

to)

,

I

TA-2S°C

V

.........

1\
to)

(Continued)

ICM7212 OPERATING POWER (LED DISPLAY) AS A
FUNCTION OF SUPPLY VOLTAGE

ICM7212 LED SEGMENT CURRENT AS A
FUNCTION OF BRIGHTNESS CONTROL VOLTAGE

n

..'

./

V

V

V

V

/
o

o

V
2

3

o

4

VOLTAGE ON BRT PIN 5 (VOLTS)

5
VSupp (VOLTS)

0364-14

0364-13

INPUT DEFINITIONS
In this table, VDD and VSS are considered to be normal operating input logic levels. Actual input low and high levels are
specified under Operating Characteristics. For lowest power consumption, input Signals should swing over the full supply.
Input
BO

Terminal
27

Function

Test Conditions
VDD = Logical One
Vss = Logical Zero

Ones (Least Significant)

28

VDD=LogicalOne
Vss = Logical Zero

Twos

29

VDD = Logical One
Vss = Logical Zero

Fours

B3

30

VDD = Logical One
Vss = Logical Zero

Eights (Most significant)

OSC
(LCD Devices Only)

36

B1
B2

Data Input Bits

Floating or with ex·
ternal capacitor to VDD

Oscillator input

Vss

Disables BP output devices, allowing segments to be
synchronized to an external signal input at the BP terminal (Pin 5)

II
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIeD OR STATUTORY, INCLUDING THE IMPLIED WARRANTies OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values hsV9 been characterized but are not tested.

13-7

ICM7211/12
....=
....

....
~

ICM7211/1CM7212 MULTIPLEXED-BINARY INPUT CONFIGURATION

::I

Input

S:!

Test Conditions

Terminal

D1

31

Voo=Active
VSS = Inactive

Function
D1 Digit Select (Least significant)
D2 Digit Select

D2

32

D3

33

D3 Digit Select

D4

34

D4 Digit Select (Most significant)

ICM7211M/ICM7212M MICROPROCESSOR INTERFACE INPUT CONFIGURATION
Function

Input

Description

Terminal

Test Conditions

DA1

Digit Address
Bit 1 (LSB)

31

Voo = Logical One
Vss = Logical Zero

DA2

Digit Address
Bit2(MSB)

32

DA 1 & DA2 serve as a two bit Digit Address Input
DA2, DA 1 = 00 selects D4
DA2, DA 1 = 01 selects D3
DA2, DA 1 = 10 selects D2
DA2, DA 1 = 11 selects D1

CS1

Chip Select 1

33

CS2

Chip Select 2

34

Voo = Inactive
Vss=Active

When both CS1 and CS2 are taken low, the data at the Data
and Digit Select code inputs are written into the input latches.
On the rising edge of either Chip Select, the data is decoded
and written into the output latches.

DIGIT SELECT
DN•1

DIGIT SELECT
ON

0364-15

Figure 4: Multiplexed Input Timing Diagram

~~----------~;-

CSl
(CS2)

CS2
(CS1)

DATA AND
DIGIT
ADDRESS

_

= DON'T CARE
0364-16

Figure

5: Microprocessor Interface Input Timing Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE' All typ;ca/ values have bsen charllcterized but are not tflSted.

13-8

~U~UI!:.

ICM7211/12

n
I:

....

Tile on board oscillator is designed to free run at approximately ·1 9kHz at microampere power levels. The oscillator
frequency is divided by 128 to provide the backplane frequency, which will be approximately 150Hz with the oscillator free-running; the oscillator frequency may be reduced by
connecting an external capacitor between the OSCillator
terminal and VDD.
The oscillator may also be overdriven if desired, although
care must be taken to ensure that the backplane driver is
not disabled during the negative portion of the overdriving
signal (which could cause a D.C. component to the display).
This can be done by driving the OSCillator input between
the positive supply and a level out of the range where the
backplane disable is sensed (about one fifth of the supply
voltage above Vss). Another technique for overdriving the
oscillator (with a signal swinging the full supply) is to skew
the duty cycle of the overdriving signal such that the negative portion has a duration shorter than about one microsecond. The backplane disable sensing circuit will not respond
to signals of this duration.

DESCRIPTION OF OPERATION
LCD DEVICES
The LCD devices in the family (ICM7211, 7211 A, 7211 M,
7211 AM) provide outputs suitable for driving conventional
four-digit, seven-segment LCD displays. These devices include 28 individual segment drivers, backplane driver, and a
self-contained oscillator and divider chain to generate the
backplane frequency.
The segment and backplane drivers each consist of a
CMOS inverter, with the n- and p-channel devices ratioed to
provide identical on resistances, and thus equal rise and fall
times. This eliminates any DC component, which could arise
from differing rise and fall times, and ensures maximum display life.
The backplane output devices can be disabled by connecting the OSCillator input (pin 36) to Vss. This allows the
28 segment outputs to be synchronized directly to a signal
input at the BP terminal (pin 5). In this manner, several slave
devices may be cascaded to the backplane output of one
master device, or the backplane may be derived from an
external source. This allows the use of displays with characters in multiples of four and a single backplane. A slave
device represents a load of approximately 200pF (comparable to one additional segment). Thus the limitation of the
number of devices that can be slaved to one master device
backplane driver is the additional load represented by the
larger backplane of displays of more than four digits. A good
rule of thumb to observe in order to minimize power consumption is to keep the backplane rise and fall times less
than about 5 microseconds. The backplane output driver
should handle the backplane to a display of 16 one-halfinch characters. It is recommended that if more than four
devices are to be slaved together, that the backplane signal
be derived externally and all the ICM7211 devices be
slaved to it. This external signal should be capable of driving
very large capacitive loads with short (1-2I-'s) rise and fall
times. The maximum frequency for a backplane signal
should be about 150Hz although this may be too fast for
optimum display response at lower display temperatures,
depending on the display used.

~:;~~:~g:
INPUT IOUTPUT

The LED devices in the family (ICM7212, 7212A, 7~12M,
7212AM) provide outputs suitable for directly driving fourdigit, seven-segment common-anode LED displays. These
devices include 28 individual segment drivers, each consisting of a low-leakage, current-controlled, open-drain, n-channel transistor.
The drain current of these transistors can be controlled
by varying the voltage at the BRighTness input (pin 5). The
voltage at this pin is transferred to the gates of the output
devices for "on" segments, and thus directly modulates the
transistor's "on" reSistance. A brightness control can be
easily implemented with a single potentiometer controlling
the voltage at pin 5, connected as in Figure 7. The potentiometer should be a high value (100KO to 1MO) to minimize
power consumption, which can be significant when the display is off.
The BRighTness input may also be operated digitally as a
disolay enable; when high, the display is fully on, and low
fully off. The display brightness may also be controlled by
varying the duty cycle of a signal swinging between the two
voltages at the BRighTness input.
Note that the LED devices have two connections for Vss;
both of these pins should be connected. The double connection is necessary to minimize effects of bond wire resistance with the large total display currents possible.
When operating LED devices at higher temperatures
and/ or higher supply voltages, the device power dissipation
may need to be reduced to prevent excessive chip temperatures. The maximum power dissipation is 1 watt at 25'C,
derated linearly above 35'C to 500mW at 70'C ( -15mW /'C
above 35'C). Power dissipation for the device is given by:

.fIf 1fLilllf 1.fUU" 1llJUlf
I
I
Ll ..

------i'

OFF SEGMENTS

_

CYCLES

1_

64

I\)

I\)

LED DEVICES

_ _ _ _--jr----128 CYCLES---i

BACKPLANE

...
..........

CYCLES-~
L--

ON SEGMENTS

0364-17

Figure 6: Display Waveforms

P = (VSUpp - VFLED)(IsEG)(nSEG)
where VFLED is the LED forward voltage drop, ISEG is segment current, and nSEG is the number of "on" segments. It
is recommended that if the device is to be operated at elevated temperatures the segment current be limited by use
of the BRighTness input to keep power dissipation within
the limits described above.

lNTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bgen characterized but are not tested.

13-9

II

.
...

~

ICM7211/12

CII

I

significant digit at pin 31 ascending to most significant digit
at pin 34), each of which when taken to a positive level
decodes and stores in the output latches of its respective
digit the character corresponding to the data at the input
port, pins 27 through 30.
The
ICM7211M,
ICM7211AM,
ICM7212M,
and
ICM7212AM devices are intended to accept data from a
data bus under processor control.
In these devices, the four data input bits and the two-bit
digit address (DA 1 pin 31, DA2 pin 32) are written into input
buffer latches when both chip select inputs (~ pin 33,
CS2 pin 34) are taken low. On the rising edge of either chip
select input, the content of the data input latches is decoded and stored in the output latches of the digit selected by
the contents of the digit address latches.
An address of 00 writes into D4, DA2 = 0, OA 1 = 1 writes
into 03, DA2 = 1, OA 1 = 0 writes into 02, and 11 writes into
01. The timing relationships for inputting data are shown in
Figure 5, and the chip select pulse widths and data setup
and hold times are specified under Operating Characteristics.

- - -.....- - - V D O (LED ANODES)

?<~_

100IdJ.1U!I<

BRIGHTNESS
PINS

0364-18

Figure 7: Brightness control

INPUT CONFIGURATIONS AND
OUTPUT CODES
The standard devices in the ICM7211/12 family accept a
four-bit true binary (ie, positive level = logical one) input at
pins 27 thru 30, least significant bit at pin 27 ascending to
the most significant bit at pin 30. The ICM7211, ICM7211 M,
ICM7212, and ICM7212M devices decode this binary input
into a seven-segment alphanumeric hexadecimal output,
while the ICM7211A, ICM7211AM, ICM7212A, and
ICM7212AM decode the binary input into the same sevensegment output as in the ICM7218 "Code B", ie 0-9, dash,
E. H, L, P, blank. These codes are shown explicitly in Table
1. Either decoder option will correctly decode true BCD to a
seven-segment decimal output.
TABLE 1: Output Codes
BINARY
B3 B2 B1 BO

a
a
a
a
a
a
a
a

a a a
a a 1
a 1 a
a 1 1
1
a a
1
a 1
1
1
a

1

a a a
a a 1
a 1 a
a 1 1
1
a a
1
a 1

1
1
1
1
I

1

1

1

I

1

1

0,

1

1

1

1

HEXADECIMAL
ICM7211
ICM7211M

CODEB
ICM7211A
ICM7212AM

,j

,j

1..'

'-'I

,
,?
;,
-'
I

'-:

':
,-.J
c·-,
,

,-,
,:;

.:;
-'
.:;

"b

,-

,d

,':,,-

0364-20

Figure 8: Segment Assignment

APPLICATIONS

I

,~

j

,
5
,,:;
L'

01

D7

Of

DiIIM

00

..

D'

LC.D~~~lBBBB!BBBBr
,

-:

BACK~-=li
Il.AVI
•

,,:.

'-'0

-sv

.J

-

E

BCD/BINARY

H

r

DATA

,

I-

:~

DtGlT
SELECTS

(BLANK)

v..
-.==
to LI

-.
.,
.••
.".

1CM721'(A)

J'"

Ole 81-8004 OJ D2 D1 . ,

l

'='

............
_UTP --=h
•

-v.. 1CM721'(A)
Lo.."':.o;.:.

J

Ole UoIO 1M DI DI D1 ...

....:Ii

-1

JJ

:
1M

D'

0364-19

These devices are actually mask-programmable to provide any 16 combinations of the seven segment outputs
decoded from the four input bits. For large quantity orders
custom decoder options can be arranged. Contact the factory for details.
The ICM7211, ICM7211 A, ICM7212, and ICM7212A devices are designed to accept multiplexed binary or BCD input. These devices provide four separate digit lines (least

0364-21

Figure 9: Ganged ICM7211 's Driving
8-Digit LCD Display

INTERSlL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vaIuBs have bsen chsrscteriz9d but If9 not tested.

13-10

ICM7211/12
..DIGIT
LCDDllPLAY

..... :c.:o::.
1.

....•
... ~w

• tA.

» ..

.-...ea

~

....UT

Me

21

rr

--

at

13A01

..,,_

"A1J1

..

_n

11-

M

tlAO)

.. ~w

SO

11AD7

.
21

or

• iiIII

. .7"

toK5W

.e

11 ALI

TO teM7211 INTER'ACE

eEA shOuld go to
8O(C) 35 devices.

+ 5V

.:ISSI.?55
ROMI£PAOM
WITH liD

1355/1715 NOT NIelS"'"

EXPANDER

• •I
.....
':'
7

for

I

Me

Me

0364-22

Figure 10: IM80C48 Microprocessor Interface

II
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

13-11

~ ICM7218
,.. a-Digit LED
~ Multiplexed Display Driver
GENERAL DESCRIPTION

FEATURES

The ICM7218 series of universal LED driver systems provide, in a single package, all the circuitry necessary to interface most common microprocessors or digital systems to
an LED display. Included on chip are an 8-byte static display
memory, 2 types of 7-segment decoders, multiplex scan circuitry, and high current digit and segment drivers for either
common-cathode or common-anode displays.
The ICM7218A and ICM7218B feature 2 control lines
(WRITE and MODE) which write either 4 bits of control information (DATA COMING, SHUTDOWN,DECODE, and
HEXA/CODE B) or 8 bits of display input data. Display data
is automatically sequenced into the 8-byte internal memory
on successive positive going WRITE pulses. Data may be
displayed either directly or decoded in Hexadecimal or
Code B formats.
The ICM7218C and ICM7218D feature 2 control lines
(WRITE and HEXA/CODE B/SHUTDOWN), 4 separate display data input lines, and 3 digit address lines. Display data
is written into the internal memory by setting up a digit address and strobing the WRITE line low. Only Hexadecimal
and Code B formats are available for display outputs.
The ICM7218E provides 4 input lines for control information (WRITE, HEXAICODE B, DECODE and SHUTDOWN),
8 separate display data input lines, and 3 digit address lines.
Display data is written into the internal memory by setting up
a digit address and strobing the WRITE line. Data may be
displayed either directly or decoded in Hexadecimal or
Code B formats.

• Microprocessor Compatible - C, 0, EVersions
• Total Circuit Integration On Chip Includes:
a) Digit and Segment Drivers
b) All Multiplex Scan Circuitry
c) 8 Byte StatiC Display Memory
d) 7 Segment Hexadecimal and Code B Decoders
(Pin Selectable)
• Output Drive Suitable for Large LED Displays
• Common Anode and Common Cathode Versions
• Single 5 Volt Supply Required
• Data Retention to 2 Volts Supply
• Shutdown Feature - Turns Off Display and Puts
Chip Into Low Power Dissipation Mode
• Sequential and Random Access Versions
• Decimal Point Drive On Each Digit

ORDERING INFORMATION
Part
Number

Temperature
Range

Package

ICM7218AIJI

- 40'C to + 85'C

28-PIN CERDIP

ICM7218BIJI

-40'Cto +85'C

28-PIN CERDIP

ICM7218CIJI

-40'Cto +85'C

28-PIN CERDIP

ICM7218DIJI

-40'Cto +85'C

28-PIN CERDIP

ICM7218EIJL

-40'Cto +85'C

40-PIN CERDIP

lNTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

13-12

ICM7218
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage(Voo-Vss) ......................... 6V
Digit Output Current ............................ 300mA
Segment Output Current ......................... SOmA
Input Voltage
(any terminal) ............... Vss -0.3Vto Voo+0.3V
(Note 1)

Power Dissipation (28 Pin CERDIP) ......... 1 W (Note 2)
Power Dissipation (40 Pin CERDIP) ......... 1 W (Note 2)
Operating Temperature Range ......... - 40'C to + 8S'C
Storage Temperature Range .......... - 6S'C to + 1SO'C
Lead Temperature (Soldering. 1Osee) ............. 300'C

NOTE 1: Due to the SCR structure inherent In the CMOS process used to fabricate these devices. ccnnecting any terminal to a voltage greater than Voo or less
than Vss may cause destructive device latchup. For this reason it is recommended that no inputs from sources operating on a different pewer supply be
applied to the device before Hs own supply is established. and when using multiple supply systems the supply to the ICM7218 should be turned on first.
2: These limits refer to the package and will not be obtained during normal operation. Derate above 50'C by 25mW per ·C.
NOTE: Stresses abovs/hoss listsd under "Abso1uf9 Maximum Ratings" may cause permanent damage to the davice. These are streaa ratings only and functional
operation of the davice at these or any other ccnditions abovs/hoss indicatsd in the operationsl sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for 9Xl9ndad petioda may affect davice reliability.

ICM7218A.ICM7218B

ICM7218C. ICM7218D

ICM7218E

--

0365-1

Figure 1: Functional Diagrams

II
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTASILITV AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typ/CBJ values f1ave bsen ChsrscIeriztId but 81'6 not tested.

13-13

ICM7218
ICM7218A*
(OUTLINE DWG JI)

........ ,,

ICM7218B*
(OUTLINE DRAWING JI)

COMMON ANODE

-

." ... .
..... '

c:t.'fIIOD!!

Vas

V88

So9b •

D.P.•
5

IT DIGIT 7
"DIGITI
DIGIT I
"DIGITI

......
........
....
......

2S8egd

.ot (HEXA/~)

105(~.

23 DIGIT 3
22 DIGIT.
21 DIGIT 7
20 DIGIT 4

107 (DATA COMING) 7

WRifE •
MODE t
104 (iHil1'DlSWN)ttO
10111

Voo

•. . . . d

l1",b
1. . . . .

1S D.P,
TOPYIEW

TOP VIEW

0365-2

0365-3

ICM7218C
(OUTLINE DRAWING JI)

ICM7218D
(OUTLINE DRAWING JI)

_c:t._

CDMMDN_

Vas

......
......
IT . . . .

",d

..
..
21
..

Vas

DIGIT.
DIGITI
DIGIT a •
DIGIT 1 •
DAD (DIGIT ADOREII 0)
OA1 (DIGIT ADOREII 1)
107 (INPUT IIJI.)

DIGITI
DIGITI
DIGIT 7
DIGIT.

" DlGIT7
.. DIGIT I
D'GlTI
.. DIGITI

.. ....
....

.....
......
......

ftlT(

17 DIGIT 5

HElWCODE ./iiiRifDOYIii
OAI (DIGIT ADOREII 2)
ID1
IDO

II DIGIT 2

ID2

Voo
1 DIGITI

t

Voo

••

tI

t1

12

",d

"",b

lS D.P.

TOPV.EW

TOPYIEW

0365-5

0365-4

ICM7218E*
(OUTLINE DRAWING DL)
COMMON ANODE

...."'c

GROUND

•

",b •
D.P.
101

107 ~NPUT

105

"He

D.P.) •

.. DECOiiE

WIiiTI

HUAICoDEB

SHUTDOWN
104 11
DA2 (DIGIT ADDRESS 2) •
DAO (DIGIT ADDRESS 0) •
DA1 (DIGIT ADDRESS 1)

DIGIT 3
DIGIT I
DIGIT 7
DIGIT •

Ne
Ne

He
101

He

100

V+

102

DIGIT 8

103 '9

DIGIT 5

DIGIT 1 _20",_ _ _ _- ' - DIGIT 2

TOP VIEW
0365-6

• Note: Pins 5,6,7,10 are under control of Mode pin 9.

Figure 2: Pin Configurations

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF BALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charscterizBd but are not tssted.

13·14

rl)n~nlL

ICM7218
ELECTRICAL CHARACTERISTICS
Symbol
VSUPPLY

N
....

Voo=5V, Vss=OV, TA=25°C, Display Diode drop = 1.7V

CD

Parameter
Supply Voltage Range

Test Conditions

Min

Operating
Power Down Mode

4
2

6

IQ

Quiescent Supply Current

Shutdown (Note 3)

100

Operating Supply Current

Common Anode SEGS On
SEGSOff
Common Cathode SEGS On
SEGSOff
Note 4

Typ

10

Outputs
Open Circuit

IOIG

Digit Drive Current

Common Anode Vout=Voo -2.0V
Common Cathode Vout=Vss + 1.0V

IOLK

Digit Leakage Current

Shutdown Mode
Common Anode V out =2V
Common Cathode Vout= 5V

ISEG

Peak Segment Drive Current

Common Anode Vout=Vss +1.0V
CommonCathodeVout=Voo -2.0V

ISLK

Segment Leakage Current

Shutdown Mode
Common Anode Vout = Voo
Common Cathode Vout = Vss

140
50

Max

Units

6
6

V
V

300

p.A

2.5
500
700
500

mA
p.A
p.A
p.A

200
100

mA
mA
100
100

20
-10

40
-20

p.A
p.A
mA
mA

100
100

p.A
p.A

Display Scan Rate

Per Digit

VIH
VIF
VIL
ZIN

Three Level Input: Pin 91CM7218C/D
Logical "1" Input Voltage
Floating Input
Logical "0" Input Voltage
Three Level Input Impedance

Hexadecimal
CodeS
Shutdown
Note 3

VIH
VIL

Logical "1" Input Voltage
Logical "0" Input Voltage

tWL

Write Pulse Width (Low)

7218A, S

550

400

ns

tWL

Write Pulse Width (Low)

7218C, 0, E

400

250

ns

tMH

Mode Hold Time

7218A, S

150

ns

tMS

Mode Set Up Time

7218A,S

500

ns

tos

Data Set Up Time

500

ns

tOH

Data Hold Time

7218 A,S
7218C,D,E

50
125

ns
ns

tAS
tAH

Digit Address Set Up Time
Digital Address Hold Time

ICM7218C, 0, E
ICM7218C, 0, E

500
0

ns
ns

ZIN

Data Input Impedance

5·10 pF Gate Capacitance

fMUX

a...

250
4.5
2.0

Hz

3.0
0.4
100

3.5
0.8

1010

V
V
V
kO
V
V

Ohms

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: Ali typical valu8s havs been characterized but arB not tested.

13·15

III

= ICM7218

...
(\I

Ii TABLE 1: INPUT DEFINITIONS ICM7218A and B

!i

Input

Terminal

Logic
Level

Function

WRITE

8

High
Low

Input Not Loaded Into Memory
Input Loaded Into Memory

MODE

9

High
Low

Load Control bits on Write Pulse
Load Input Data on Write Pulse

ID4 SHUTDOWN

10

High
Low

Normal Operation
Shutdown (Oscillator, Decoder and Display Disabled)

6

High
Low

No Decode
Decode

5

High
Low

Hexadecimal Qecoding
Code B Decoding

7

High
Low

Data Coming
}
No Data Coming Control Word

ID5 (DECODE)
ID6 (HEXAICODE B)

MODE
High

ID7 (DATA COMING)
MODE
Low

IDO-ID7

11,12,13,14,
5,6,10,7

Display Data Inputs (Notes 4, 5)

TABLE 2: INPUT DEFINITIONS ICM7218C and D
Input
WRITE

HEXAICODE B/SHUTDOWN
DAO -DA2
IDO -ID3
ID (INPUT D.P.)

Terminal

Logic
Level

8

High
Low

9

High
Floating
Low

(Note 3)

Function
Input Not Loaded Into Memory
Input Loaded Into Memory
Hexadecimal Decoding
Code B Decoding
Shutdown (Oscillator, Decoder and Display Disabled)

10,6,5

Digit Address Inputs

14,13,11,12
7

Display Data Inputs
Decimal Point Input

..

NOTE 3. In the ICM7218C and 0 (random access versoons) the HEXA/CODE B/SHUTDOWN Input (Pin 9) has Internal biasing resistors to hold It at VDD/2 when
Pin 9 is open clrcuHed. These resistors consume pcwer and result in a quiscent supply current (10) of typically 5O"A.
The ICM7218A, B, and E devices do not have these biasing resistors and thus are not subject to this condition.
4: 100-103 ~ Don't care when writing control data
104-106 ~ Don't care when writing Hex/Code B data
107 ~ Decimal Point data
(The display blanks on ICM7218A1B versions when writing in data)
5: In the No Decode format, "Ones" represents "on" segments for all inputs except for the Decimal Point, where "Zero" represents an "on" segment, (i.e.
segments are posHive true, decimal point is negative true).
6: Common Anode segment drivers and Common Cathode Digit Drivers have 20kll pullup resistors.

INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION Of SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR use.
NOTE: AN typicsJ values have bssn chsractBrizBd but are not tested.

13-16

ICM7218
TABLE 3: INPUT DEFINITIONS ICM7218E
Input

Logic
Level

Terminal

Function

WRITE

9

High
Low

Input Latches Not Updated
Input Latches Updated

SHUTDOWN

10

High
Low

Normal Operation
Shutdown (OSCillator, Decoder and Displays
Disabled)

DECODE

33

High
Low

No Decode
Decode

HEXA/CODEB

32

High
Low

Code B Decoding
Hexadecimal Decoding

DAO - DA2
Digit Address (0,1 ,2)

13,14,12

IDO -ID6
ID7 (INPUT D.P.)

17,16,18,19,11,7,6
8

OUTPUT

Display Data Inputs (Note 5)
Display Data/Decimal Point Input

r-----r- :E': :~:u.ING

rT ~~E'ET:~NNING
INTERNAL OSC.

Digit Address Inputs

(PER DIGIT)

~ ~...n.......n.......n.......n.......n.......n.......n...._

~'T.LAN'

o.

II

0'

!l

07
EXTERNAL

11

oa

!l

DO

D4

rI

r-

o.
~

0365-7

Figure 3: Multiplex Timing

.

DETAILED DESCRIPTION
DECODE Operation

,1:/·

For the ICM7218A1B/E products, there are 3 input data
formats possible; either direct segment and decimal point
information (8 bits per digit) or two Binary code plus decimal
point information (Hexadecimal/Code B formats with 5 bits
per digit).

fld'

eD.p.

0365-8

Figure 4: Segment Assignments

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OA STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicsl values haV9 been characterized but are not tested.

13-17

II

:2 ICM7218

"...

a

Driving Larger Displays

The 7 segment decoder on chip is disabled when direct
segment information is to be written. In this format, the inputs directly control the outputs as follows:
107 106 105 104 103 102 101 100
Input Data:
Output Segments: 15]5. a b c e
g f
d
Here, "Ones" represent "on" segments for all inputs except the Decimal Point. For the Decimal Point "zero" represents an "on" segment.

If a higher average drive current per digit is required, it is
possible to connect digit drive outputs together. For example, by paralleling pairs of digit drives together to drive a 4
digit display, 5mA average segment drive current can be
obtained.

Power Dissipation Considerations
Assuming common anode drive at Voo=5 volts and all
digits on with an average of 5 segments driven per digit, the
average current would be approximately 200mA. Assuming
a 1.8 volt drop across the LED display, there will be a 3.2
volt drop across the ICM7218. The device power dissipation
will therefore be 640mW, rising to about 900mW, for all
'8' 's displayed. Caution: Position device In system such
that air can flow freely to provide maximum cooling.
The common cathode dissipation Is approximately one
half that of the common anode dissipation.

HEXAdecimal/CODE B Decoding
For all products, a choice of either HEXA or Code B decoding may be made, HEXA decoding provides 7 segment
numeric plus six alpha characters while Code B provides a
negative sign (-), a blank (for leading zero blanking), certain useful alpha characters and all numeric formats.
The four bit binary code is set up on inputs 103-100, and
decimal point data is set up on 107.
Decimal

Sequential Addressing Considerations
(ICM7218A/B)

01 234567891011 12131415

HEXACOOE 0123456789 Abe d E F
COOEB
o 1 2 3 4 5 6 7 8 9 - E HLP (BLANK)

The control instructions are read from the input bus lines
if MODE is high and WRITE low. The instructions occur on 4
lines and are-~/no Decode, type of Decode (if
desired), SHUTDOWN/no Shutdown and DATA COMING/
not Coming. After the control word has been written (with
the Data Coming instruction), display data can be written
into memory with each successive negative going WRITE
pulse. After all 8 digit memory locations have been written
to, additional transitions of the WRITE input are ignored until a new control word is written. It is not possible to change
one individual digit without refreshing the data for all the
other digits.

SHUTDOWN
SHUTDOWN performs several functions: it puts the device into a very low dissipation mode (typically 10p.A at
Voo = 5V), turns off both the digit and segment drivers, and
stops the multiplex scan oscillator (this is the only way the
scan oscillator can be disabled). However, it is still possible
to input data to the memory during shutdown - only the
display output sactions of the device are disabled in this
mode.

Powerdown

Random Access Input Drive
Considerations (ICM7218C/D/E)

In the Shutdown Mode, the supply voltage may be reduced to 2 volts without data in memory being lost. However, data should not be written into memory if the supply
voltage is less than 4 volts.

Control instructions are provided to the ICM7218C/0 by a
single three level input terminal (Pin 9), which operates independently of the WRITE pulse. The ICM7218E control
instructions are also independent but are on three separate
pins (10, 32, 33).
Data can be written into memory on the ICM7218C/0/E
by setting up a 3 bit binary code (one of eight) on the digit
address inputs and applying a low level to the WRITE pin.
For example, it is possible to change only digit 7 without
altering the data for the other digits. (See Figure 7).

Output Drive
The common anode output drive is approximately 200 mA
per digit at a 12% duty cycle. With segment peak drive current of 40mA typically, this results in 5mA average drive.
The common cathode drive capability is approximately one
half that of the common anode drive. If high impedance
LED displays are used, the drive current will be correspondIngly less.

Supply Capacitor

Inter Digit Blanking

A 0.1p.F capacitor is recommended between Voo and
Vss to bypass multiplex noise.

A blanking time of approximately 10p.s occurs between
digit strobes. This ensures that the segment information is
correct before the next digit drive, thereby avoiding display
ghosting.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATIUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
.
NOTE:AHIypIesI_ have besn _ _

but.,.

not_

13-18

ICM7218

0365-9

Figure 5: Timing Diagram for ICM7218A1B

CPNTROL_

/

DON'TCARE

(1)1)

\
CONTROL WOAD
TYPE OF DECODER? 101
DECODE/NO DECODE? 105
SHUTDOWN? 104
DATA NOT COMING 107

TYPE OF DECODER? 101
DECODE/NO DECODE? 101

IHI/TODWN? ID4
DATA COIliNG 107

0365-10

Figure 6: Load Sequence ICM7218A/B

DIGIT
ADDRESS

DAO-DAZ

DATA

~

v_

~

~VAUDDAT~
0365-11

Figure 7: Timing Diagram for ICM7218C/D/E

•
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHEA WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

13-19

: ICM7218
C\I
t-

IE

2

~

~I-

'--

_.coDi"lIIlCII
1CM721'"

DATA COIII_

Dt

,

-:-+

-=-SV

'" \ '" \\\\\=
\

VDD

T

O.1,.F:

VSS

£

I

~ I

£

--

~iIF!IFlIRIRIRIHIHI
D!lPLAV

Figure 8: Test Circuits (# 1)

~=0-

D.P.
0365-12

~~~!I..

'--7
DIGIT ADDIiDS. :

IT

1
107 D.P.

HllWCCDEIli
DIGIT_",

,
I

ICM72110

I

.•

1 "

f \

-:-+

'1 '1

\\ \ \ \ -=:

u

i-

VDD

.....
...=:::
: laiHiHiPiFtip.iHiRI
LI. u. u U. LI. ,_1. '-'"--I

0.1,.,:

,,:,"SY

"T-

..
"
..,.
.
".
.

VSS

0

D.P.

DI 07

DI OS

D3

0' 01

COMMON CATHODE
DllPUV
0365-13

Figure 9: Test Circuits (#2)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE OONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typIcs/ va/u8s have been characterized but 8r9 not testBd.

13·20

ICM7218
TYPICAL PERFORMANCE CHARACTERISTICS
COMMON ANODE SEG. DRIVER
ISEG vs. VOUT AT 25°C

COMMON ANODE SEG. DRIVER
ISEG. vs. VOUT

•

"',..;----,,...:-~__,r:::--~

COMMON ANODE DIGIT DRIVER
IDIG VS. (VDO-VOUT)

r-......;;....,-......;;--,;:::---:~

';';1'

.~---t

ij "1--#-7fL.Ao

i

J

1DO

r-=±--!'II-+---i

1

1

Vour (VOLTS)

2

Voo - Vour (VOLTS)

0365-14

0365-15

0365-16

COMMON CATHODE DIGIT DRIVER
IDIG vs. VOUT AT 25°C

COMMON CATHODE SEG. DRIVER
ISEG vs. (VDO-VOUT)

COMMON CATHODE DIGIT DRIVER
IDIG vs. VOUT

2GO

r=-:c:::..._+:..:....-...- - ,

2OO,----,-----,r-..,..--,

3Or---..,..----r--~

la~--_+-~-+_--~

5Ot-~-t---t--_;

3

1

1

Vour (VOLTS,

a

2

Vour (VOLTI,

Voo - VOUT (VOLTS,

0365-17

•w

0365-19

0365-18

....

• DIGITS

........

,.....,..

-

IMIOCOI

....

I r..
ETC.

NC

• II

{

II T1

tHPUT

II

'T'

....

..
Figure 10: 8 Digit Microprocessor Display

0365-20

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are not tested.

13-21

=
ICM7218
...
&\I

a

play data from the 80481/0 bus (OB7-0BO) is transferred to
both ICM7218's simultaneously.
The display digits from both ICM7218's are interleaved to
allow adjacent pairs of digits to be loaded simultaneously
from a single 8 bit data bus.
Decimal point information is supplied to the ICM7218's
from the processor on port lines P26 and P27.

APPLICATION EXAMPLES

8 DIGIT MICROPROCESSOR DISPLAY
APPLICATION
Figure 10 shows a display interface using the ICM7218A1
B with an 8048 family microcontroller. The 8 bit data bus
(OBO/OB7-100/107) transfers control and data information
to the 7218 display interface on successive WRITE pulses.
The MODE input to the 7218 is connected to one of the I/O
port pins on the microcontroller. When MODE is high a control word is transferred; when MODE is low data is transfered. Sequential locations in the 8-byte static memory are
automatiC~~I~Eded on each successive iiVl'!I'i'E pulse. After eight
pulses have occurred, further pulses are
ignored until a new control word is transferred. (See Figure
6). This also allows writing to other peripheral devices without disturbing the ICM7218A1B.

NO DECODE APPLICATION
The ICM7218 can also be used as a microprocessor
based LED status panel driver. The microprocessor selected control word must include "No Decode" and "Data
Coming". The processor writes "Ones" and "Zeroes" into
the ICM7218 which in turn directly drives appropriate discrete LEOs. LED indicators can be red or green (8 segments x 8 digits = 64 dots + 2 per red or green = 32 channels).

16 DIGIT MICROPROCESSOR DISPLAY
In this application (see Figure 11), both ICM7218's are
addressed simultaneously with a 3 bit word, 0A2-0AO. Ois-

I

0 OT010 08"8'181 1-,I C)1010TCJI8"8I\C)1
O. o.lo.ILI. [J. .1 .IL.IU.lu.IO.ILI.lu.1 .1' .10.1
1

1

D11

D1.

,

D10

DO

DO

III

+sv,
h.
Vee VDD Vas
••

2 XTAL.1

::. $, .....
:: ...

~.u _.;j4 IfIRt
......_ _~7 .4

,--

17"
ETC.

::~

Vas

VDD

i=

D'

GiNO

I.

Vas

VDD

:::". ;:
:::
J:
"7 '-

...., ..
... 1.,

§f

-"-II
=Pt-

DIQI7'~

........... 1---

·=
OAI

'CM721IC1D

DUi=:;-'
D.. ,

GAO

'CM72111C1l1

II~:
r---1!

'"100
t

=

,..-_ _.....<.j7 ~NPUT D.P.)

, (lNPUTD.P.)

P27

DO' 4
DO. ,

fr.====;IJ"

ID1

ID2

ID3

lOS

+IJH=~BI

Viiiffii

+s---' Haoq=~81

Viiiffii

0365 ...21

Figure 11: 16 Digit Display

IN'lERSIL·S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPUED OR STATUTORY. INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.
NOTE: An typical YIIIws hsWl been chsracteriZsd but Bf8 not tssted.

13-22

ICM7228
a-Digit LED Multiplexed
Display Driver
GENERAL DESCRIPTION

FEATURES

The ICM7228 series of universal LED driver systems provide, in a single package, all the circuitry necessary to interface most common microprocessors or digital systems to
an LED display. Included on chip are an 8-byte static display
memory, 2 types of 7-segment decoders, multiplex scan circuitry, and high current digit and segment drivers for either
common-cathode or common-anode displays.
The ICM7228A and ICM7228B feature 2 control lines
(WRITE and MODE) which write either 4 bits of control information (DATA COMING, SHUTDOWN, DECODE, and
HEXA/CODE B) or 8 bits of display input data. Display data
is automatically sequenced into the 8-byte internal memory
on successive positive going WRITE pulses. Data may be
displayed either directly or decoded in Hexadecimal or
Code B formats.
The ICM7228C and ICM7228D feature 2 control lines
(WRITE and HEXAICODE B/SHUTDOWN), 4 separate display data input lines, and 3 digit address lines. Display data
is written into the internal memory by setting up a digit address and strobing the WRITE line low. Only Hexadecimal
and Code B formats are available for display outputs.

• Microprocessor Compatible
• Total Circuit Integration On Chip Includes:
(a) Digit and Segment Drivers
(b) All Multiplex Scan Circuitry
(c) 8 Byte Static Display Memory
(d) 7 Segment Hexadecimal and Code B Decoders
(Pin Selectable)
• Output Drive Suitable for Large LED Displays
• Common Anode and Common Cathode Versions
• Single 5V Supply Required
• Data Retention to 2V Supply
• Shutdown Feature-Turns Off Display and Puts Chip
Into Low Power Dissipation Mode
• Sequential and Random Access Versions
• Decimal Point Drive On Each Digit
• Non-Overlapping Digit Strobe

ORDERING INFORMATION
Part
Number

Temperature
Range

ICM7228AIJI

-40·C to + 85·C

28-Pin CERDIP

ICM7228BIJI

-40·C to + 85·C

28-Pin CERDIP

ICM7228CIJI

-40·Cto + 85·C

28-Pin CERDIP

ICM7228DIJI

-40·C to + 85·C

28-Pin CERDIP

ICM7228AIPI

-40·Cto + 85·C

28-Pin Plastic DIP

ICM7228BIPI

-40·Cto +85·C

28-Pin Plastic DIP

ICM7228CIPI

-40·Cto + 85·C

28-Pin Plastic DIP

ICM7228DIPI

-40·Cto +85·C

28-Pin Plastic DIP

Package

II

INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

202820-001

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typ;cal values have been characterized but are not tested.

13-23

ICM7228
ABSOLUTE MAXIMUM RATINGS

NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may CBuse permanent damage to the device. These are stress ratings only

Supply Voltage (Voo-Vss) .......................... 6V
Digit Output Current ............................ SOO mA

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of the specifications is not
implied. Exposure to sbsolute maximum rsUng conditions for extended peri·

Segment Output Current ........................ 100 mA
Input Voltage
(any terminal) ... (Vss - 0.3V) to (Voo + 0.3V) (Note 1)
Power Dissipation ........................ 1.SW (Note 2)

ods may affect device reliability.

Operating Temperature Range .......... - 40'C to + 8S'C
Storage Temperature Range ........... - 6S'C to + 1S0'C
Lead Temperature (Soldering, 10 sec) .............. 300'C
NOTE 1: Due to the SeR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than Voo or less
than Vss may cause destructive device latchup. For this reason it is recommended that no inputs from sources operating on a different power supply be

applied to the device before its own supply is established, and when using multiple supply systems the supply to the ICM728 should be turned on first.
2: These limits refer to the package and will not be obtained during normal operation. Derate above 50'C by 25 mW per ·C.

ICM7228C, ICM7228D

ICM7228A, ICM7228B

100-103
107
DATA
INPUT

IDO·107
INPUT
DATA

8

WRiTE

OAO-OA2
DIGIT
ADDRESS

3
SHUTDOWN

CONTROL
LOGIC
WRITE
ADDRESS
DECODER

8

8·BYTE
STATIC
RAM

8·BYTE
STATIC
RAM

8
READ

ADDRESS
MULTIPLEXER

4

5

8

INTEROIGIT

,-.I...._ _ _I.rBLANKING

INTERDIGIT
BLANKING

0086-1

Figure 1: Functional Diagrams

tNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
"

NOTE All typical values have been characterized but are not tested

13-24

.D~UIl.

ICM7228

a
....

II)
II)

ICM7228A*

ICM7228B*

Common Anode

Common Cathode

Seg c
Seg.

C»

DIGIT 4
DIGITS
DIGIT 3 3
DIGIT 1 4
ID6 (HEXA/emsE""i)

Seg b
D.P. •
106 (HEXA/CODE 8) 5
ID5(~)6

ID5(~)

107 (DATA COMING) 7
WRITE 8
MODE 9
ID4 (SHUTDOWN) ,.
101 11
10012

107 (DATA COMING) 7
WRITE 8
MODE

0086-2

0086-3

TOP VIEW

TOP VIEW

ICM7228C

ICM7228D

Common Anode

Common Cathode

Seg c
Seg e
Seg b 3
D.P.
DAO (DIGIT ADDRESS 0)
DA1 (DIGIT ADDRESS 1) &
ID7 (INPUT D.P.)
WRITE
HEXA/CODE B/SHUTDOWN •
DA2 (DIGIT ADDRESS 2)
ID1
IDO

DIGIT 4
DIGIT 6
DIGIT 3
DIGIT 1
DAO (DIGIT ADDRESS 0)
DA1 (DIGIT ADDRESS 1)
107 (INPUT D.P.)

3

WJm'!
HEXA/CODE B/SHUTOOWN ,
DA2 (DIGIT ADDRESS 2)
101
100
102
103
0086-4

0086-5

TOP VIEW

TOP VIEW

*NOTE: Pins 5, 6, 7, 10 are under control of Mode pin 9.

Figure 2: Pin Configurations

II
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.
NOTE: All typical values have been characterized but arB not tested.

13-25

: ICM7228

...
N

Ii ELECTRICAL CHARACTERISTICS

g

Symbol

Parameter

VDD = 50V ± 10%. VSS = OV

Min
VSUPPLY

IQ

IDD

IDIG

Supply Voltage Range

Quiescent Supply
Current
Operating Supply
Current

Digit Drive
Current

Operating

4

Power Down Mode

2

ISEG

Digit Leakage
Current

Peak Segment
Drive Current

Segment Leakage
Current

IlL

fMUX

Display Scan Rate

tlOB

Inter-Digit
Blanking Time

VINH

Logical "1" Input
Voltage

6

Min

Typ

6

4

100

1

100

100

2.5

100

Common Anode
Segments = ON
Outputs = OPEN

200

450

200

450

Common Anode
Segments = OFF
Outputs = OPEN

100

450

100

450

Common Cathode
Segments = ON
Outputs = OPEN

250

450

250

450

Common Cathode
Segments = OFF
Outputs = OPEN

175

450

175

450

= VDD - 2.0V

200

175

50

40

mA

Shutdown Mode
Common Anode VOUT = 2.0V

1

100

1

100

Shutdown Mode
Common Cathode VOUT

1

100

1

100

IJ-A

= 5.0V

Common Anode

20

= Vss + 1.0V

Shutdown Mode
Common Anode VOUT

IJ-A

IJ-A

Common Anode

VOUT

V

2
1

VOUT

Units

Max

2.5

20

25

mA
10

= V DD

Shutdown Mode
Common Cathode VOUT
Input Leakage
Current

Max

Shutdown. 7228A. 7228B

Common Cathode
VOUT = VDD - 2.0V
ISLK

Typ

Shutdown. 7228C. 7228D

Common Cathode
VOUT = Vss + 1.0V
IOLK

-40'C ,;;; TA ,;;; +85'C

TA = 25'C

Test Conditions

12

10

1

50

1

50

1

50

1

50

IJ-A

= Vss

All Inputs Except Pin 9
7228C. 7228D VIN = Vss

1

1

All Inputs Except Pin 9
7228C. 7228D VIN = 5.0V

-1

-1

Per Digit

Three Level Input: Pin 9
7228C. 7228D Hexadecimal
VDD = 5V

IJ-A

125

150

80

Hz

2

10

2

IJ-s

4.2

V

4.2

INTERS1L'S SOLE AND EXCLUSIVE WARAANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

13-26

ICM7228
ELECTRICAL CHARACTERISTICS
Symbol

Parameter

VDD

=

TA

Test Conditions
Min

VINF

Floating Input

Three Levellnpul: Pin 9
7228C, 72280 Code B
VDD

ZIN

Three Level Input
Impedance

Vee = 5V
Pin 9 of 7228C & 72280

VIH

Logical "1" Input
Voltage

VIL

Logical "0" Input
Voltage

All Inputs Except
Pin 9 of 7228C, 72280
VDD = 5V

-40'C ,,; TA ,,; +85'C

Max

Min

3.0

2.0

Typ

0.8

50

50

Units

Max
3.0

V

0.8

V

2.0

2.0

kO

V
0.8

AC ELECTRICAL CHARACTERISTICS
Parameter

Typ

2.0

Three Levellnpul: Pin 9
7228C, 72280 Shutdown
VDD = 5V

Symbol

OV (Continued)

= 25'C

= 5V

Logical "0" Input
Voltage

VINL

=

5.0V ± 10%, VSS

VDD

0.8

= 5V ±10%, VIL = O.4V, VIH = 2.4V
-40'C ,,; TA ,,; +85'C

TA = 25'C

Test Conditions

Max

Min

Typ

Units

Min

Typ

Max

200

100

250

ns
ns

tWL

Write Pulsewidth (Low)

tWH

Write Pulsewidth (High)

850

540

1200

tMH

Mode Hold Time

7228A, 7228B

0

-65

0

ns

tMS

Mode Setup Time

7228A,7228B

250

150

250

ns

tDS

Data Setup Time

250

160

250

ns

tDH

Data Hold Time

7228A, 7228B

0

-60

0

ns

7228C, 72280

0

-60

0

ns

250

110

250

ns

0

-60

0

ns

tAS

Digit Address
Setup Time

7228C, 72280

tAH

Digit Address
Hold Time

7228C, 72280

II
!NTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THiS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FiTNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested

13-27

CD

...""""

a

.O~OI!.

ICM7228
TABLE 1: INPUT DEFINITIONS ICM7228A AND B
Input

Terminal

Logic
Level

Function

WRITE

8

High
Low

Input Not Loaded into Memory
Input Loaded into Memory

MODE

9

High
Low

Load Control Bits on Write Pulse
Load Input Data on Write Pulse

ID4 SHUTDOWN

10

High
Low

Normal Operation
Shutdown (Oscillator, Decoder and Display Disabled)

6

High
Low

No Decode
Decode

5

High
Low

Hexadecimal Decoding
Code B Decoding

7

High
Low

Data Coming
No Data Coming

ID5 (DECODE)
ID6 (HEXAICODE B)

MODE
High

ID7 (DATA COMING)
IDO-ID7

MODE
Low

11,12,13,14,
5,6,10,7

}

Control Word

Display Data Inputs (Notes 4, 5)

TABLE 2: INPUT DEFINITIONS ICM7228C AND D
Input

Terminal

Logic
Level

WRITE

8

High
Low

HEXA/CODE B/SHUTDOWN

9

High
Floating
Low

(Note 3)
DAO-DA2
IDO-ID3
ID7 (Input D.P.)

Function
Input Not Loaded into Memory
Input Loaded into Memory
Hexadecimal Decoding
Code B Decoding
Shutdown (Oscillator, Decoder and Display Disabled)

10,6,5

Digit Address Inputs

14, 13, 11, 12
7

Display Data Inputs
Decimal Point Input

NOTE 3. In the ICM7228C and 0 (random access versions) the HEXA/CODE B/SHUTDOWN Input (Pin 9) has Internal biasing resistors to hold It at Voo/2 when
Pin 9 is open circuited. These resistors consume power and result in a quiescent supply current (10) of typically 50 IJ.A.
The ICM7228A, 8 devices do not have these biasing resistors and thus are not subject to this condition.
4: 100-103

~ Don·t care when writing control data
~ Don·t care when writing Hex/Code B data
107 = Decimal point data
(The display blanks on ICM7228A1B versions when writing in data)

104-106

5: In the No Decode format. "Ones" represent "on" segments for a/l inputs except for the Decimal Point where "Zero" represents an "on" segment (Le.,
segments are positive true, decimal point is negative true).

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been charact9lized but are not tested.

13-28

ICM7228

INTERNAL

\ I ;~:: ~~~NING

osc.

r----I ~:~:~~~~ING

(PER DIGIT)

---1L.-JLJLJLJLJLJL~_

OUTPUT

D2

DS

~~------------------------------

------------~~~r-::::!LIT-B-L-AN-.-------------------------------------------------_____________________
_______________________________________
~r__l~

D'

D7

EXTERNAL
DB

D6

___________________________________

~r___l~

__________________________________

_____________________________________

~r___lL_

______________________________________

________________

~r___l~

_______________

__________________________________________________________

_______

r---1~

D4

D3

____________________________________________________________________________

~r----

0086-6

Figure 3: Multiplex Timing
Deci·

'-:-/b
.,-,e

mal

o1

2 3 4 5 6 7 8 9 10 11 12 13 14

15

f

___ eo.p.
d

0086-7

Figure 4: Segment Assignments

DETAILED DESCRIPTION
DECODE Operation

HEXA 0
1 2 3 4 5 6 7 8 9 A
CODE

b

C

d

E

CODE 0
1 2 3 4 5 6 7 8 9
B

E H

L

P (Blank)

-

F

SHUTDOWN
SHUTDOWN performs several functions: it puts the device into a very low dissipation mode (typically 1 ",A at
VDD = 5V), turns off both the digit and segment drivers,
and stops the multiplex scan oscillator (this is the only way
the scan oscillator can be disabled). However, it is still possible to input data to the memory during shutdown - only
the display output sections of the device are disabled in this
mode.

For the ICM7228A1B products, there are 3 input data formats possible; either direct segment and decimal point information (8 bits per digit) or two Binary code plus decimal
point information (Hexadecimal/Code B formats with 5 bits
per digit).
The 7 segment decoder on chip is disabled when direct
segment information is to be written. In this format, the inputs directly control the outputs as follows:
Input Data:
107 ID6 ID5 ID4 103 ID2 ID1 100
Output Segments: D.P. a b c
e
g
f
d
Here, "Ones" represent "on" segments for all inputs except the Decimal Point. For the Decimal Point "Zero" represents an "on" segment.

Powerdown
In the Shutdown Mode, the supply voltage may be reduced to 2 volts without data in memory being lost. However, data should not be written into memory if the supply
voltage is less than 4 volts.

Output Drive
The common anode output drive is approximately 200 mA
per digit at a 12% duty cycle. With segment peak drive current of 40 mA typically, this results in 5 mA average drive.
The common cathode drive capability is approximately one
half that of the common anode drive. If high impedance
LED displays are used, the drive current will be correspondingly less.

HEXAdecimal/CODE B Decoding
For all products, a choice of either HEXA or Code B decoding may be made, HEXA decoding provides 7 segment
numeric plus six alpha characters while Code B provides a
negative sign (~), a blank (for leading zero blanking), certain useful alpha characters and all numeric formats.
The four bit binary code is set up on inputs ID3-IDO, and
decimal point data is set up on ID7.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized btlt are not tested.

13-29

II

= ICM7228
(\f

....
Ii
S:!

Inter Digit Blanking

Sequential Addressing Considerations
(ICM7228A/B)

A blanking time of 2 ,."s minimum, 10 ,."s typical occurs
between digit strobes. This ensures that the segment information is correct before the next digit drive, thereby avoiding display ghosting.

The control instructions are read from the input bus lines
if MODE is high and WRITE low. The instructions occur on 4
lines and are - DECODE/no Decode, type of Decode (if
desired), SHUTDOWN/no Shutdown and DATA COMING/
not Coming. After the control word has been written (with
the Data Coming instruction), display data can be written
into memory with each successive negative going WRITE
pulse. After all 8 digit memory locations have been written
to, additional transitions of the WRITE input are ignored until a new control word is written. It is not possible to change
one individual digit without refreshing the data for all the
other digits.

Driving Larger Displays
If a higher average drive current per digit is required, it is
possible to connect digit drive outputs together. For example, by paralleling pairs of digit drives together to drive a 4
digit display.

Power Dissipation Considerations
Assuming common anode drive at Voo= 5 volts and all
digits on with an average of 5 segments driven per digit, the
average current would be approximately 200 mAo Assuming
a 1.8 volt drop across the LED display, there will be a 3.2
volt drop across the ICM7228. The device power dissipation
will therefore be 640 mW, rising to about 900 mW, for all
"8"s displayed. Caution: Position device in system such that
air can flow freely to provide maximum cooling. The common cathode dissipation is approximately one half that of
the common anode dissipation.

Random Access Input Drive
Considerations (ICM7228C/D)
Control instructions are provided to the ICM7228C/D by a
single three level input terminal (Pin 9), which operates independently of the WRITE pulse.
Data can be written into memory on the ICM7228C/D by
setting up a 3 bit binary code (one of eight) on the digit
address inputs and applying a low level to the WRITE pin.
For example, it is possible to change only digit 7 without
altering the data for the other digits. (See Figure 7.)

Supply Capacitor
A 0.1 ,."F capacitor is recommended between Voo and
Vss to bypass multiplex noise.

0086-8

Figure 5: Timing Diagram for ICM7228A1B

INTERStL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

13-30

ICM7228
MODE

..JI~

_________....rL

WRITE

DON'T CARE

101/
CONTROL WORD
TYPE OF DECODER? 106
DECODE/NO DECODE? 105
SHUTDOWN? 104

108/

\

CONTROL WORD
TVPE OF DECODER? 106
DECODE/NO DECODE? 105
SHUTDOWN? 104
DATA NOT COMING 107

DATA COMING 107

0086-9

Figure 6: Load Sequence ICM7228A/B

DIGrr
ADDRESS
DAO-OAZ

DATA

~VALIDDAT~
0086-10

Figure 7: Timing Diagram for ICM7228C/D

11~~~t-4-----------~
~
t.~~-+----------------------------_,
,,:"!:-+---------------,

L
I06
HEXA_COO E-a-,-iF.:!:l
r -_ _ _ _ _ _ _ _ _ _~~~D~e~C~O~D~~~I=D~51r.~.
DATA COMINGIID7:'j'

"2~3-+-------_,

leM
7228A

r------------~WJIT~~~u.a

~2~'-~-----

r-__________~~~~M~~O~ID~E~'a

fl~~-+---+--+-----.
~

SHUTDOWN/.D. 10
r -_ _ _ _ _ _-7.ID~'~"g

~

~ ~ ~ ~;¥.
t

-:-+

1l2~2-+----,

lij~~~~+_~

\
VDD

-:.- 5V

T-

,J

Vss
D. 07

01 05

04 D3

02 D1

d---

0101010101010101

'-'·I'-I.I'-'·I'-'·IU·IU·IU·IU·I
COMMON ANODE
DISPLAV

:==-

~===:J

b
D,P.

======J
0086-11

Figure 8: Test Circuits (# 1)
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPUED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

13-31

: ICM7228
~
....
:I
!:!

lli1r.v-~
2
3

DIGIT ADDRESS 0 ~
DIGIT ADDRESS 1
ID7eD.p.) ~

7

WRlfE
HEXA/COOE B/SHUTOOWN
DIGIT ADDRESS 2

7

101

l'

27
,.

ICM7228D

•

t

-±-+

\

\

~
19

"

:~
ID3~

\

"
21

iii

~

~
If,\.
~

17

~
IS

-

"1 \

T-

'-.

Voo

",:"SV

'--I
O.1j.1F

08 07

06 05

04 D3

02

01

~ ~ IHIIC~lel,Cl.It='.li=~.\e.lp

- : U.U.U.U.U.U.U.U

VSS

•D.P.

COMMON CATHODE
DISPLAY

0086-16

Figure 9: Test Circuits (# 2)

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

13·32

IID~DIL

ICM7228

(i;8
'j,r

1(1

#=

0

IOIG(WA)

200

j

300

~

'r-i '10--

85"C
25"C
-4O"C

85·C
500

I

I.i

IL

Ii'

~

~

v

o
5
1

o

-

ISEG(MA'

15

20
25
30
35

J.;J

400

fJ.
25"C

i5
15"C

soc

100

,

...

I:
II»
II»
CD

TYPICAL PERFORMANCE CHARACTERISTICS
40"C
"C

n

40
45

t- V

50

55

-40"C1

3.0

4.0

2.0

5.0

1.0

4.0

3.0

1.0

2.0

VOUT (VOLlS)

o

VSEG (VOLTS,

0086-12

0086-13

Common Anode Digit Driver

Common Cathode Segment Driver

10lG VB (VOO-VOUT) @ TA·C

ISEG VB (VOO-VOUT) @ TA·C

100
90

-40

80

!1:1

.!l'

IDIG(MA)

I......

70

25"C
85"C

1/

60

J

50

V

300
-4O"C

V t....II IIV

"
V

40
30
20
10

'"

o II'
o

200

'"
J....: ~ ~

100

I.&i ~

o~

1.0

2.0

25"C
85"C

......

3.0

o

5.D

1.0

2.G

3.0

4,0

5.0

VOUT (VOLTS'

VSEG (VOLlS)

0086-15
0086-14

Common Anode Segment Driver

Common Cathode Digit Driver
10lG VB VOUT @ TA·C

ISEG VB VOUT @ TA ·C

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WrrH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHEI;t WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE:AII/ypk»J_"'vo _ _ bullII8not_

13·33

----------

---------~--

---------

•

= ICM7228

...
2
(\I

i

I

I
,-,
LI ,-,. 0

I.•• ='=

L'.

C'.

I

1

..

2

Yoo

7

-=

NC-!

INPUT

I

0 ,-,

C] L'
Ll. B. '-'. '-'.
,_'.
1

1

j

1

....!!
t~

EA

.

IM80C36
IM80C48
8048
8060
8748
ETC.

1'20

PZ2

I'DIGITS

fK

fIt

-1'21

1'23

1'25
1'27

~::

TO

ICM7228A/B

~

•

I'

121

WI!

r'

IIODE

12
11
13
1.
10

IDO
101
IDZ
103
101
I
IDS
101
1
107

1

I'
DB7 l'

"..! lIlT

• SEGIIENTS

~
~
~

=

Tl

Vss

r;:m:fit-

IllIG 12
DIll
Dtz

r'

T.

Voo
1'10
I'll
1'12
1'13
1'14
1'15
PI.
Pl1

ALE IIRR!'fIOG

1

L

Vss

XTALI

• IID!T

II

I

~.1:

Vee

Ta XTAU

II

I

+5V

C

II

I

WR

lID

r

I'

0086-17

Figure 10: 8 Digit Microprocessor Display

APPLICATION EXAMPLES
8 Digit Microprocessor Display
Application

Display data from the 8048 1/0 bus (087-080) is transferred to both ICM7228's simultaneously.
The display digits from both ICM7228's are interleaved to
allow adjacent pairs of digits to be loaded simultaneously
from a single 8 bit data bus.
Decimal point information is supplied to the ICM7228's
from the processor on port lines P26 and P27.

Figure 10 shows a display interface using the ICM7228A1
8 with an 8048 family microcontroller. The 8 bit data bus
(080/087-100/107) transfers control and data information
to the 7228 display interface on successive WRITE pulses.
The MODE input to the 7228 is connected to one of the 1/0
port pins on the microcontroller. When MODE is high a control word is transferred; when MODE is low data is transferred. Sequential locations in the 8-byte static memory are
automatically loaded on each successive WRITE pulse. After eight WRITE pulses have occurred, further pulses are
ignored until a new control word is transferred (see Figure
6). This also allows writing to other peripheral devices without disturbing the ICM7228A18.

No Decode Application
The ICM7228 can also be used as a microprocessor
based LED status panel driver. The microprocessor selected control word must include "No Decode" and "Data
Coming". The processor writes "Ones" and "Zeroes" into
the ICM7228 which in turn directly drives appropriate discrete LEOs. LED indicators can be red or green (8 segments x 8 digits = 64 dots -;- 2 per red or green = 32
channels).

16 Digit Microprocessor Display
In this application (see Figure 11), both ICM7228's are
addressed simultaneously with a 3 bit word, DA2-DAO.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARAANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHEA WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

13-34

.D~DIl

ICM7228

5
I:
....
II)
II)

I

•

c-'
.'-'. L'. B.IB.1818.IBIBI,9.IB B.l8.18.1
1°D. o.'.IB.IO
,

CD

I

•

DII

OM

......
• •~NDI.•
_It

•

'ee 'Oo'ss

XTAL1

"~
" "f • • TAU

.
."

• 111m
•

~

.

-

IMIOC3I
IMIOC4I
I0IO

8741

ETC.

Ole....!.

D'

.........
....... .
..,
......

I

...
......... t
...
I••

II

OIl

OIl

-"............

-tu;1
r·

Dn

DII

II

t~
.:

.... 2: T1
fill

DII7

ALE NIIf NOU . . -

r'

I' I·

lID

I'

'.

'DO

_

.

, 0..'
DAI

DIGITS

...

t---

1CM722SC/o

1•

'DO

V.

GND

-DIGITI

,0..'

•
t--

-

1C1I722SCID

DAI

,

., (INPUT D.P.)

..

...

rr;:::i

101
DO

• IV..!

I.

II

• IV

t--

•• 101

DII'

TO

,

_I.

·"1,

'-

IV'

DI

DO

H~II

.sv..!

SHUTDOWN

Wiiiii

r

IINPUTD.PJ

'00
10'

101
101

H.Il!YO!!!!LII
SHUTDOWN

WiiiTE

r
0086-18

Figure 11: 16 Digit Display

II
INTERSIL'S SOlE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES. EXPRESS. IMPUED OR STATUTORY. INCLUDING THE IMPLIED WARRANnES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typicM _

ha.. bHn _/eIIzed but.,. not tsstod.

13·35

: ICM7231-ICM7233
&Ii

.... Numeric! Alphanumeric Triplexed
LCD Display Driver

¥
...
C')

....&Ii

:IE

2

GENERAL DESCRIPTION

FEATURES

The ICM7231-7233 family of integrated circuits are designed to generate the voltage levels and switching waveforms required to drive triplexed liquid-crystal displays.
These chips also include input buffer and digit address decoding circuitry allowing six bits of input data to be decoded
into 64 independent combinations of the output segments
of the selected digit.
The family is designed to interface to modern high performance microprocessors and microcomputers and ease
system requirements for ROM space and CPU time needed
to service a display.

• ICM7231: Drives 8 Digits of 7 Segments With Two
Independent Annunciators Per Digit Address and
Data Input In Parallel Format
• ICM7232: Drives 10 Digits of 7 Segments With Two
Independent Annunciators Per Digit Address and
Data Input in Serial Format
• ICM7233: Drives 4 Characters of 18 Segments
Address and Data Input In Parallel Format
• All Signals Required to Drive Rows and Columns of
Triplexed LCD Display Are Provided
• Display Voltage Independent of Power Supply
• On-Chip Oscillator Provides All Display Timing
• Total Power Consumption Typically 200",W,
Maximum 500",W at 5V
• Low-Power Shutdown Mode Retains Data With 5",W
Typical Power Consumption at 5V, 1",W at 2V
• Direct Interface to High-Speed Microprocessors

ORDERING INFORMATION
Part Number

Temperature
Range

ICM7231AFIJL

Temperature
Range

Package

Package

Part Number

- 25'C to + 85'C

40 pin CERDIP

ICM7232CRIJL

- 25'C to + 85'C 40 pin CERDIP

ICM7231AFIPL

- 25'C to + 85'C

40 pin PLASTIC Dip

ICM7232CRIPL

- 25'C to + 85'C 40 pin PLASTIC Dip

ICM7231 BFIJL

- 25'C to + 85'C

40 pin CERDIP

ICM7233AEVIKIT

ICM7231 BFIPL

- 25'C to + 85'C

40 pin PLASTIC Dip

ICM7233AFIJL

- 25'C to + 85'C 40 pin CERDIP

ICM7231CFIJL

-25'C to +85'C

40 pin CERDIP

ICM7233AFIPL

- 25'C to + 85'C 40 pin PLASTIC Dip

ICM7231CFIPL

- 25'C to + 85'C

40 pin PLASTIC Dip

ICM7233BFIPL

- 25'C to + 85'C 40 pin PLASTIC Dip

ICM7232AFIJL

- 25'C to + 85'C

40 pin CERDIP

ICM7233BFIJL

- 25'C to + 85'C 40 pin CERDIP

ICM7232AFIPL

- 25'C to + 85'C

40 pin PLASTIC Dip

ICM7232BFIJL

- 25'C to + 85'C

40 pin CERDIP

ICM7232BFIPL

- 25'C to + 85'C

40 pin PLASTIC Dip

Evaluation Kit.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, eXPRESS, IMPLlEO OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

203299-003

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not testsd.

13-36

ICM7 231-ICM7 233
DO

X y

Z

D7

De

X Y Z

x y z

os

x y z

'04
X y Z

D.

D3
X y Z

X y

Dl
Z

X y

Z

VDD

OUTPUT
LATCHES

VH

~~~!~

VL

VOLTAGE
LEVEL
GENERATOR

OW'DE
Veo...

H+~I--PIN2(1NPUT)

COM 1

COMMON
LINE

COM 2

DRIVER

-"_ _ _ J - COM3

AO Al A2

~

ADDRESS INPUTS

0366-1

Figure 1: ICM7231 Functional Diagram

11.0

DO

x y z

X y Z

DO
X y

Z

D7

De

D8

X y Z

X Y Z

X y Z

04
X y

Z

D3
X y Z

Dl

D2
X Y Z

X

y

Z

Voo
ON CHIP

VH

DISPLAY
VOLTAGE

LEVEL
GENERATOR

OUlPUT
LATCHES

'WIDE

H++=V~O!!!''''-''N 2 (INPUT)

COM.
COMMON

LINE

COM 2

DRIVERS
COM 3

~SHIFT REGISTER/
SHIFTS RIGHT TO LEFT

ON RISING EDGE OF DATA CLOCK

DATA DATA
INPUT CLOCK
I . .ur

WJUft
INPUT

DATA
ACCEPTEO

OUTPUT

0366-2

Figure 2: ICM7232 Functional Diagram
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

13-37

D

ICM7231-ICM7233
CHAR.

UVWXYZ

CHAR 3
UVWXYZ

CHARZ

CHAR.

UVWXVz

UVWXYZ

SEGMENT
LINE
DRIVERS
IWIDE

VDD

OUlfUT
LATCHES
laWIDE

VH

ON CHIP
DISPLAY
VOLTAGE
LEVEl
GENERATOR

II

H+_.V.;.:D:::'SI':.. PIN 2 (INPUT)

II

COM'
COMMON

L.INE

COM 2

DRIVER
COM 3

,CS',CS2,
CHIP $ELECT

INPUTS

0366-3

Figure 3: ICM7233 Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tssted.

13-38

ICM7 231-ICM7 233
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD - Vss) ....................... 6.5V

Power Dissipation[l] ...................... 0.5W @ 70·C
Operating Temperature Range ......... - 25·C to + 85·C
Storage Temperature Range .......... -65·Cto + 1500C
Lead Temperature (Soldering, 10sec) ............. 300·C

Input Voltage [2] .................... Vss-0.3:5:VIN:5:6.5
Display Voltage[2] ................. -0.3 :5:VDISP:5: + 0.3

Noles: 1. This limit refers to that of the package and will not be obtained during normal oparation.
2. Due to the SeR structure inherent in these devices, connecting any display terminal or the display voltage terminal to a voltage outside the power supply
to the chip may cause destructive device latchup. The digital inputs should never be connected to a voltage less than - 0.3 volts below ground, but may
be connected to voltages above Voo but not more than 6.5 volts above Vss.
NOTE: Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. These are stress relings only and functional
operation of the device at these or any other condilions above those Indicated in the operational sections of the specificatJons is not implied. Exposure to absolul8
maximum rsting conditions for extended periods may affect device reliability.

Ci
v",..

,_.

DATA CLOCK

v"

CO•.,

A'

COM.

""v..

COM.

COM'
COM!

VDISf'

os,

DATAINPU'l
OATAACCEPTiD

COMI

A'

OUTNT

COM2

AD

COM3

GND

os

1Z

,OX . .

,v
,x

V·

WIIITI.NPUT

v..

COM'
1Z

ID'
ID'
ID'

1Z

,v
IX

os,

VDO

v",..

A:l

10Y IV

,v

, . . I)(

,X

D3

D4

IX 7%

,W

D2

ANt

••

2V

IV 7V

IV

Dl

A"

2X

IZ 7)(

lU

DO

32

IX 'Z

2.

4U
4V

2.

ODD

2V
2X

3Z

IX

3V

IV

3X

I.

'V
.X

IV IV

2Y

Il IX

2X

ow

zw

4X

4l

7X

4'

7)( 1%

4Y

4V

7V tV

2V

4Y

4X

n
n

4X

7Z tX

2U

4.

5.

IX

I.

I)(

'OZ

3Z

3U

5V

IV

IV

IV 'OV

3Y

3V

5X

IZ

IX

IZ lOX

3X

ow

I

I

""IIF CA

0366-7

0366-5
0366-6

Figure 4: Pin Configuration (Outline dwg PL)

ELECTRICAL CHARACTERISTICS

(V+ = 5V ± 10%, VSS = OV, T A = - 25·C to

+ 85·C unless otherwise

specified)
Symbol

Parameter

Test Conditions/Description

Voo

Power Supply Voltage

Voo

Data Retention Supply Voltage

Guaranteed Retention at 2V

100

Logic Supply Current

Current from VDO to Ground excluding
Display. VOISP = 2V

Is

Shutdown Total Current

VOISP Pin 2 Open

VOISP

Display Voltage Range

VSS,;VOISP,;VDO

IOISP

Display Voltage Setup
Current

VOISP = 2V Current from VDO to
VOISP On-Chip

Display Voltage Setup Resistor Value

One of Three Identical Resistors in String

DC Component of Display Signals

(Sample Test only)

fOISP

Display Frame Rate

See FigureS

VIL

Input Low Level

VIH

Input High Level

ICM7231, ICM7233
Pins 30-35,37-39, 1

IILK

Input Leakage

ROISP

Min

Typ

Max

Units

4.5

>4

5.5

V

2

I.S
100

,..A

10

,..A

30
1
0

Voo

V

30

,..A

'14

1

% (VOO - VOISP)

90

120

Hz

0.8

V

1

,..A

15
40
SO

V

75

kO

2.0

ICM7232,
Pins I, 38, 39 (Note 1)

V
0.1

CIN

Input Capacitance

VOL

Output Low Level

Pin 37, ICM7232, 10L = 1rnA,

VOH

Outpul High Level

Voo=4.5V,loH= -500,..A

4.1

Top

Operating Temperature Range

Industrial Range

-25

5

pF

004

V

+85

'C

V

INTERSIL S SOLE AND EXCLUSIVE WARAANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tssted.

13-39

II

IIJO~On.

: ICM7231-ICM7233

...
~
'i
...
...
Ii
(II

(II)
(II

S!

AC CHARACTERISTICS

(VDD=5V±10% Vss=OV, -20'CsTAS

+ 85'C)

PARALLEL INPUT (ICM7231, ICM7233) See Figure 14
Test Conditions

Min

Typ

les

Chip Select Pulse Width

(Note 1)

500

350

Ids

,Address/Data Setup Time

(Note 1)

200

tdh

Address/Data Hold Time

(Note 1)

0

tics

Inter-Chip Select Time

(Note 1)

3

Symbol

Parameter

Max

Units
ns
ns

-20

ns
Ils

SERIAL INPUT (ICM7232) See Figures 15, 16
Test Conditions

Min

tci

Data Clock Low Time

(Note 1)

350

ns

tcl

Data Clock High Time

(Note 1)

350

ns

tds

Data Setup Time

(Note 1)

200

Idh

Data Hold Time

(Note 1)

0

-20

twp

Write Pulse Width

(Note 1)

500

350

twl!

Write Pulse to Clock at Initialization

(Note 1)

1.5

todl

Data Accepted Low Output Delay

(Note 1)

200

400

ns

todh

Data Accepted High Output Delay

(Note 1)

1.5

3

Ils

lews

Write Delay After Last Clock

(Note 1)

Symbol

Parameter

Typ

Max

Units

ns
ns
ns
Ils

350

ns

NOTE 1: For design reference only, not 100% tested.

TABLE OF FEATURES
Type Number

Output Code

Annunciator
Locations

Input

Output

Parallel Entry
4 bit Data

8 Digits
plus

2 bit Annunciators

16 Annunciators

ICM7231AF

Hexadecimal

ICM7231BF

CodeB

ICM7231CF

CodeB

1 Annunciator COM 1
1 Annunciator COM3

3 bit Address

ICM7232AF

Hexadecimal

Both Annunciators
onCOM3

Serial Entry
4 bit Data

10 Digits
plus

2 bit Annunciators

20 Annunciators

ICM7232B

CodeB

ICM7232CR

CodeB

Both Annunciators
onCOM3

1 Annunciator COM1
1 Annunciator COM3

4 bit Address
Parallel Entry
6 bit (ASCII) Data

ICM7233AF

64 Character
(ASCII)
18 Segment
(Half width numbers)

No Independent
Annunciators

ICM7233BF

64 Character
(ASCII)
18 Segment
(Full width numbers)

No Independent
Annunciators

Four
Characters

2 bit Address
Parallel Entry
6 bit (ASCII) Data

Four
Characters

2 bit Address

INTER$IL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPUED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valuss have been characterized but are not t8Sted

13-40

ICM7 231-ICM7 23 3
TERMINAL DEFINITIONS
ICM7231 PARALLEL INPUT NUMERIC DISPLAY
Terminal

Pin
No.

AN1
AN2

30
31

Annunciator 1 Control Bit
Annunciator 2 Control Bit

High=ON
Low = OFF

BDO
BD1
BD2
BD3

32
33
34
35

Least Significant }
4 Bit Binary
Data Inputs

Input
Data
(See Table 1)

AO
A1
A2

37
38
39

3 Bit Digit
Address Inputs

Input
Address
(See Table 2)

CS

1

Function

Description

Most Significant
Least Significant }
Most Significant

See Table 3

HIGH= Logical One (1)
LOW = Logical Zero (0)

Trailing (Positive going) edge latches data,
causes data input to be decoded and sent
out to addressed digit

Data Input Strobe/Chip Select (Note 3)

NOTE: 3. CS has a special" mid-Ieval" sense circuit that establishes a test mode if it is held near 3V for several msec. Inadvertent triggering of this mode can be
avoided by pulling it high when inactive, or ensuring frequent activity.

ICM7233 PARALLEL INPUT ALPHA DISPLAY
Terminal

Pin
No.

DO
D1
D2
D3
D4
D5

30
31
32
33
34
35

Least Significant }

AO
A1

37
38

Least significant}
Most Significant

CS1
CS2

39
1

Chip Select Inputs
(Note 4)

Description

Function
Input
Data

6 Bit (ASCII)
Data Inputs

HIGH = Logical One (1)
LOW = Logical Zero (0)

See
Table 4

Most Significant
Address Inputs

Input Add.
See Table 5
Both inputs LOW load data into input
latches. Rising edge of either input causes
data to be latched, decoded and sent out
to addressed character.

NOTE 4: CS1 has a special "mid-level" sense circuit that establishes a test mode if it is held near 3V for several msec. Inadvertent triggering of this mode can be
avoided either by pulling it high when inactive, or ensuring frequent activity.

ICM7232 SERIAL DATA AND ADDRESS INPUT
Terminal

Pin
No.

Description

Data Input

38

Data + Address Shift Register Input

HIGH = Logical One (1)
LOW = Logical Zero (0)

WRITE Input

39

Decode, Output, and Reset Strobe

When DATA ACCEPTED Output is LOW, positive
going edge of WRITE causes data in shift register
to be decoded and sent to addressed digit, then
shift register and control logic to be reset. When
DATA ACCEPTED Output is HIGH, positive going
edgw of WRITE triggers reset only.

Data Shift Register and Control
Logic Clock

Positive going edge advances data in shift register.
ICM7232: Eleventh edge resets shift register and
control logic.

Handshake Output

Output LOW when correct number of bits entered
into shift register; ICM7232 8, 9 or 10 bits

Data Clock
Input

1

DATA
ACCEPTED
Output

37

Function

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have been characterized but are not test6d.

13-41

II

= ICM7231-ICM7233

...

.D~DD..

&\I

I..

ALL DEVICES

&\I

Display
Voltage VOISP

I

f')

...

I

Terminal

Pin
No.
2

Common
Line Driver
Outputs

3,4,5

Segment
Line Driver
Outputs

6-29
6-35

Description

Function

Negative end of on-chip resistor
string used to generate intermediate
voltage levels for display. Shutdown Input.

Display voltage control. When open (or less than
1V from VOO chip is shutdown; oscillator stops, all
display pins to Voo.
Drive display commons, or rows.

(On ICM7231/33)
(On ICM7232)

Voo

40

Chip Positive Supply

Vss

36

Chip Negative Supply

Drive display segments, or columns.

ment for the same four combinations of ON/OFF segments
in Figure 6.
The degree of polarization of the liquid crystal material
and thus the contrast of any intersection depends on the
RMS voltage across the intersection capacitance. Note
from Figure 8 that the RMS OFF voltage is always Vp/3 and
that the RMS ON voltage is always 1.92 Vp/3.
For a 1/3 multiplexed LCD, the ratio of RMS ON to OFF
voltages is fixed at 1.92, achieving adequate display contrast with this ratio of applied RMS voltage makes some
demands on the liquid crystal material used.
Figure 9 shows the curve of contrast versus applied RMS
voltage for a liquid crystal material tailored for Vp=3.1V, a
typical value for 1j,-multiplexed displays in calculators. Note
that the RMS OFF voltage Vp/3::< 1V is just below the
"threshold" voltage where contrast begins to increase. This
places the RMS ON voltage at 2.1V, which provides about
85% contrast when viewed straight on.
All members of the ICM723111CM7233 family use an internal resistor string of three equal value resistors to generate the voltages used to drive the display. One end of the
string Is connected on the chip to V00 and the other end
(user input) is available at pin 2 (VOISP) on each chip. This
allows the display voltage input (VOISP) to be optimized for
the particular liquid crystal material used. Remember that
Vp = VOO - VOISP and should be three times the threshold
voltage of the liquid crystal material used. Also it is very
important that pin 2 never be driven below VSS. This can
cause device latchup and destruction of the chip.

ICM7231 FAMILY DESCRIPTION
The ICM7231 drives displays with 8 seven-segment digits
with two independent annunciators per digit, accepting six
data bits and three digit address bits from parallel inputs
controlled by a chip select input. The data bits are subdivided into four binary code bits and two annunciator control
bits.
The ICM7232 drives 10 seven-segment digits with two
independent annunciators per digit. To write into the display, six bits of data and four bits of digit address are
clocked serially into a shift register, then decoded and written to the display.
The ICM7233 has a parallel input structure similar to the
ICM7231, but the decoding and the outputs are organized
to drive four 18-segment alphanumeric characters. The six
data bits represent a 6-bit ASCII code.
Input levels are TTL compatible, and the DATA ACCEPTED output on the serial input devices will drive one LSTTL
load. The intermediate voltage levels necessary to drive the
display properly are generated by an on-chip resistor string,
and the output of a totally self-contained on-chip oscillator
is used to generate all display timing. All devices in this
family have been fabricated using Intersil's MAXCMOS"
process and all inputs are protected against static discharge.

TRIPLEXED (113 MULTIPLEXED)
LIQUID CRYSTAL DISPLAYS
Figure 5 shows the connection diagram for a typical 7segment display font with two annunciators such as would
be used with an ICM7231 or ICM7232 numeric display driver. Figure 6 shows the voltage waveforms of the common
lines and one segment line, chosen for this example to be
the "Y" segment line. This line intersects with COM1 to
form the "a" segment, COM2 to form the "g" segment and
COM3 to form the "d" segment. Figure 6 also shows the
waveform of the "Y" segment line for four different ON/
OFF combinations of the "a", "g" and "d" segments. Each
intersection (segment or annunciator) acts as a capacitance
from segment line to common line, shown schematically in
Figure 7. Figure 8 shows the voltage across the "g" seg-

.

COM 1

-1ECJ.-

::*

RH
SEGMENT LINE CONNECTION

COMMON LINE CONNECTION

03e6-9

Figure 5: Connection Diagrams for
Typical 7 Segment Displays
0

INTERSIL·S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typIcsI VBIues MVS bHn ~ butlU8 not t6sted.

13-42

ICM7231-ICM7233
v,·

. -

-

-

-

-

-

-

-

-

-

-

-

-

-r=u=

r-T - rI.L _LJ_ L..l_

ALL OFF •

-

ONeHIP
RUtSTOR STRING

....

VOOI

-,""II

-

-

-

-

-

-

-

-

-

-

-

_

-

-

-

-

-

-

-

·O~~· -

-

-

-, _____

v+ - VOISP
-COMMON AND
SEGMENT PEAK TO
PEAK VOLTAGE

0

_

-

-

I I I I I I I

- _

+V,

- -

L

• -Vp

- +Vp

0

VRM.·

~

-VAMSOFF

V.
-,""II

J-

bSlGMENT
LINE

ALL OFF

-

____ -

-

_

V,
-

-

_

-

-

-,""II

V~

I I I I I I I

VOl.,

___~- - - --VOO
--- ---~~

a SEGMENT
ON
t"dOFF

I..:.t______ -_- Lv....

I I I I I I I
- --- ------ - ~~
.----~--.VDD

••,ON
dOFF

ptN2

INPUT

TVPICAL
SEGMENT LINE
WAveFORMS
(SEGMENT

LINE ''Y'')

I..:.:..:.t- - - - -~V.,..

ALL ON

I I i I I I I
l-----VOO
-----t-----t
- -- -

-

-----

•
:~
V

VI».

0366-10

0366-12

Figure 6: Display Voltage Waveforms

Figure 8: Voltage Waveforms on
Segment g(Vg)

NOTE: 4>" 4>2, 4>3-COMMON HIGH WITH RESPECT TO SEGMENT.

VOLTAGE CONTRAST RATIO=

4>1',4>2', 4>3,-COMMON LOW WITH RESPECT TO SEGMENT.
COM 1 ACTIVE OURING 4>1 AND 4>1'

VRMSOOFNF=~= 1.92

VRMS

;3

NOTE: 4>" 4>2, 4>3 - COMMON HIGH WITH RESPECT TO SEGMENT.

COM 2 ACTIVE DURING 4>2 AND 4>2'
COM 3 ACTIVE DURING 4>3 AND 4>3'

4>1',4>2', 4>3,-COMMON LOW WITH RESPECT TO SEGMENT.
COM 1 ACTIVE DURING 4>1 AND 4>,'

x

COM 2 ACTIVE DURING 4>2 AND 4>2'

Z_SEGMENT

V

LINES

I

COM 3 ACTIVE DURING 4>3 AND 4>3'

I
I

I
f

I

/.,( a

b

COM 1

I

COM 2

. >~
LH

COM 3

I
I
I
I
I
I
I
I
I
I

9

/- 19 19

,,

J" Z

*

K [ +
L \ /
M ] N 71
0 ~ /

/

L

~

?
0366-28

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDInON OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typ/CtII VIIItiN MWI beM cIwactt1rIad but 6I'B not tssftld.

13-50

ICM7231-ICM7233
TYPICAL APPLICATIONS

-

-

MICROCOMPUTER

IIoof fvcc
2OV• """0 Z7

-'"_.
..

}w_

211

I

ZOSCI

·~O

oJl

~ ~

II
I
I

....:r..

.

IOICZ "7 at

I.

'20 ~~U
M

'RESET

"1"F

'EA

V'.".

....

• TD

INPUTS{=

liNt

PHI
P27 ..
010 12

..,

....

~

CCIWE

27

27

ZNZZZZ

Iloo

""V'

VII

IOGND

110 PORT J

1--

WI

Z

V_

ICM7HIA

WI

Iloo

""V'

VOl

lUND

Z

V_
ICM7233A

00 -----0& AOA.aza;

00------0& AOA'CI2Cii

30 -------.. 31 ~ 31 31 1

30 - - - - - - - 315 37 18 31 1

1I

I
I

I

}-~

I
I

aus

II

EXTERN AL
MEMOR V AND
OTHER PERIPHERALS

I

DB71'

11121101

ALE

.

I ~J. IIRII

1Mn

-PULL-uP RECOMMENDED ON Ci'i. SEE NOTE 3.

"DO
0366-29

Figure 20: 8048/1M80C48 Microcomputer with 8 Character 16 Segment
ASCII Triplex Liquid Crystal Display.
The two bit character address Is merged with the data and written to the display driver
under the control of the WR line. Port lines are used to either select the target driver,
or deselect all of them for other bus operations.

--

I~JTEF~5IL

_RAM
V'

..

27

.J..
T [ _ ~1

-,IC
-J __
=3 =3

27

V'
V'
RI"

V'

'M$l

CIEE NOTE 3)
~--1;---DTMI.1/D

1IIlI

•

II
0366-30

Figure 21: MC6802 Microprocessor with 16 Character 16 Segment
ASCII Liquid Crystal Display.
The peripheral device provides ROM and Timer functions In addition to port line control of the display bank.
Individual character locations are addressed via the address bus. Note that VMA is not decoded on these
lines, which could cause problems with the TST Instruction.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORV, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical valuss haw betm charscterlZ8d but are not tsstfld.

13-51

:; ICM7231-ICM7233
ell

po.

•S!...
I

fIlfllfllfllfllfllfllfll

CI)

ell

po.

a

11

11

I

I

ICM7233

CS2

CSl

ICM7233

Ao Do·05

Al

CS2 .CSl

Al

AO

0 0.05

8

"""

~

r

TO 06 ON
EPROM
lk

6
+5V

~

75OkO

8 xl00kQ

VDD

f- RC

o'l~F*

2
4

ICM7240

f

.......

11-

8
16

+5V- TRIG
RESET
VSS

32

to.

....

MC14049B
OR
C04049B

.......

...
to.

64

1

128
AS
A6
A7

As
"

*

RC
ICM7240

c

I
AS A2 Al

Ao 00·05

IM6S54

08

J

El

I~~
i :~

'-- TB I/O

A4

c

1
2
4

+5V- TRIG
fRESET
Vss

.,..

0366-31

Figure 22: EPROM-Coded Message System.
This circuit cycles through a message coded In the EPROM, pausing at the end of each line,
or whenever coded on Qa.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARnCLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicsI valU8S havs bHn charsctfIrIzed but are not tested.

13·52

ICM7 231-ICM7 23 3
II'EAWO

I

I INTERVAL I

~

I TEST I I FREO. RATIO I

'I

FREQUIENCV

B. B. B. B. B. B. B. B.
ro;;;;-]
~

21

I

~1'~

INPUT A

INPUT 8

J=

.,F

0366-32

Figure 23: 10MHz Frequency/Period Pointer with LCD Display.
The annunciators show function and the decimal pOints indicate the range of the current operation. The
system can be efficiently battery operated.
08

07

DO

D4

D5

OJ

02

01

~ B.. B.. B.. B. ~B..B. ~B..B.

COM •
COM 2
COMJ

•

ICM7231AF/8F
TOP VIEW

0366-33

Figure 24: "Forward" Pin Orientation and Display Connections
INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.

NOTE All typical values have been characterized but are not tested

13-53

IID~OIL

:ICM723'1-ICM7233
('II

i...

0'.

DO

co

DO

DO

DO

DO

DO

0'

B. 8. i B. B. B. ·B. B. B. B.

I

ft

('II

....

I

x v>

xv

xv>

xv

xv

xv>

COM'

COM.
COM.

xv>

'----}-0366-34

Figure 25: "Reverse" Pin Orientation aod Display Connections
CHARACTI!R

4

CHARACTER

CHARACTER
3

2

CHARACTER
1

Y

x

1CM7233AFIBF

W

v
U

z
y

x

LCD

W

v

U

01 E MOUNTS UNDER LCD

Figure 26: "Forward" Ole Pad Orientation and Typical Triplex
Alphanumeric Display Connections

TOP VIEW (BOTH DIE AND LCD)

0366-35

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOT'E:AH typ/MIWIIwo".", _ _ but_no!_

13-54

ICM7243
8-Character LED
J.LP-Compatible Display Driver
GENERAL DESCRIPTION

FEATURES

The ICM7243 is an 8-character alphanumeric display driver and controller which provides all the circuitry required to
interface a microprocessor or digital system to a 14- or 16segment display. It is primarily intended for use in microprocessor systems, where it minimizes hardware and software overhead. Incorporated on-chip are a 64-character
ASCII decoder, 8X6 memory, high power character and
segment drivers, and the multiplex scan circuitry.
Six-bit ASCII data to be displayed is written into the memory directly from the microprocessor data bus. Data location
depends upon the selection of either Serial (MODE = 1) or
Random (MODE=O). In the Serial Access mode the first
entry is stored in the lowest location and displayed in the
"left-most" character position. Each subsequent entry is automatically stored in the next higher location and displayed
to the immediate "right" of the previous entry. A DISPlay
FULL signal is provided after 8 entries; this signal can be
used for cascading. A CLeaR pin is provided to clear the
memory and reset the location counter. The Random Access mode allows the processor to select the memory address and display digit for each input word.
The character multiplex scan runs whenever data is not
being entered. It scans the memory and CHARacter drivers,
and ensures that the decoding from memory to display is
done in the proper sequence. Intercharacter blanking is provided to avoid display ghosting.

• 14- and 16-Segment Fonts With Decimal Point
• Mask Programmable For Other Font-Sets Up to 64
Characters
• Microprocessor Compatible
• Directly Drives Small Common Cathode Displays
• Cascadable Without Additional Hardware
• Standby Feature Turns Display Off; Puts Chip in Low
Power Mode
• Serial Entry or Random Entry of Data Into Display
• Single + 5V Operation
• Character and Segment Drivers, All MUX Scan
Circuitry, 8x6 Static Memory and 64-Character ASCII
Font Generator Included On-Chip

ORDERING INFORMATION
Part
Number

Temperature Range

Package

ICM7243AIJL

- 20"C to + 85"C

CERDIP

ICM724381JL

- 20"C to + 85"C

CERDIP

ICM7243AIPL

- 20"C to + 85"C

PLASTIC

ICM724381PL

-20"C to +85"C

PLASTIC

ICM72438 EV/KIT

II
0368-2

0368-1

Figure 1: Pin Configurations

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPliED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not testBd.

13-55

.
(II)

ICM7243

(II

....
5!

:Ii ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range (I) ....... - 2S'C to + 8S'C
Storage Temperature Range ... . . . . . .. - SS'C to + 125'C
Lead Temperature (Soldering, 10sec) ............. 300'C

Supply Voltage (Voo-Vss) ......................... 6V
CHARacter Output Current ..................... 300mA
SEGment Output Current ........................ 30mA
Input Voltage (Any Terminal) .. (Voo + 0.3V) to (Vss -0.3V)
Power Dissipation ................................. 1W

NOTE: Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functionsl
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

DATA INPUT

SEGMENT OUTPUTS
SEGx

SEGMENT
DRIVERS

0.-.

CHAP.",
CHARACTER OUTPUTS

I

Ao/SEN _ _

11

SEL

SEL

• ICM72<3AHASONLYONECSAND
NO

CS. ICM72<3B HAS 1S SEGMENTS

ADDRESS
MULTIPLEXER
AND
DECODER

AZIOISP FUll +--+

0368-3

Figure 2: Functional Diagram

DC ELECTRICAL CHARACTERISTICS
Symbol

Parameter

(Voo=5V, Vss=OV, TA=25'C unless otherwise stated)
Limits

Test Conditions
Min
4.75

Vsupp

Supply Voltage (Voo-Vss)

100

Operating Supply Current

Vsupp = 5.25V, 10 Segments ON, All 8 Characters
Vsupp=5.25V, OSC/OFFPin<0.5V, CS=Vss

ISTBY

Quiescent Supply Current

V,H

Input High Voltage

V,L

Input Low Voltage

liN

Input Current

Units

Typ

Max

5.0

5.25

30

250

/LA
V

2

-10

V
mA

180

0.8

V

+10

/LA

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values have boon characterized but are not tested.

13-S6

IIID~DIL

ICM7243
DC ELECTRICAL CHARACTERISTICS

I\,)

(Voo=5V, Vss=OV, TA=25'C unless otherwise stated)

...

c.a

(Continued)
Parameter

Symbol

Limits

Test Conditions

ICHAR

CHARacter Drive Current

ICHLK

CHARacter Leakage Current

ISEG

SEGment Drive Current

ISLK

SEGment Leakage Current

VOL

DISPlay FULL Output Low

IOL =1.6mA

VOH

DISPlay FULL Output High

IIH= 1OOIJ-A

Ids

Display Scan Rate

Min

Typ

140

190

Vsupp=5V, VOUT=1V

Units
Max
mA
100

14

VSupp=5V, VOUT=2.5V

IJ-A
mA

19
0.01

10

IJ-A

0.4

V

2.4

V
400

AC ELECTRICAL CHARACTERISTICS

a...

Hz

(Drive levels O.4V and 2.4V, timing measured at O.BV and 2.0V.

Voo= 5V, TA= 25'C unless otherwise stated).
Min

Typ

300

250

Data Hold Time

0

-100

tos

Data Setup Time

250

150

tAH

Address Hold Time

125

tAS

Address Setup Time

40

les

CS, CS Setup Time

0

Symbol

Parameter

Test Conditions

tWPI

WR, CLeaR Pulse Width Low

tWPH

WR, CLeaR Pulse Width High (Note 1)

tOH

Max

Units

250

ns

15
100

tT

Pulse Transition Time

!sEN

SEN Setup Time

0

-25

tWOF

Display Full Delay

700

4BO

CAPACITANCE
Symbol

Test

Min

Typ

Max

Units

CIN

Input Capacitance (Note 2)

5

pF

Co

Output Capacitance (Note 2)

5

pF

NOTES: 1. In Serial mode WR high must be ;"TSEN +TWDF.
2. For deSign referenoa only, not 100% tested.

'Not tested. (Guaranteed)

TYPICAL PERFORMANCE CHARACTERISTICS
SEGment Current vs Output Voltage

CHARacter Current vs Output Voltage

30

,
'--

500
VDD"5.~-:"_

VDD" I.IV

--

.V·+

ov

~4.Sv
~

o

lJ?"
.

#

100
2

SEGment VoItlge (V)

~

o

3

3
CHARacter Voltage (V)

0368-4

II

~v
...~
.... ..sf""':'"

0368-5

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicB/ values have bBBn charafMrized but are not tHfBd.

13·57

.D~DI!..

:: ICM7243

...
:E
(II

!:!

ICM7243A/B DISPLAY FONT AND SEGMENT ASSIGNMENTS
Note: Some display manufacturers use different designations for some of the segments. Check data sheets carefully.

. .

•

'~I'
lit

lIZ

m

k

I

...

o
Do. 0.

0

0

~R BC

C

II,

I1E FG HI JI-< LM NO

DISPLAY

.p OR 5T UV WX yz [ \ ] l'
1 "f g;% ,[,1
0
<> * + / - . /
L ~?
'0 12 3Y ';5 l8 g

•
• D. 0

0. 0 0
Dt 0

Do 0

/

• o•
•o • • •
••
••
•
• , • • •

0

o
o

0

0

o

o •
o
o

0

0

0

0

0

0

0

0

______

~~J

SEGMENT LEO.

0

0

0

~

•••••
••••
•o , •
• • •
0

0

0

0

VIS

0368-6

Figure 3: ICM7243A 16-5egment
Character Font with Decimal Point

0368-8

Figure 5: Segment and Character
Drivers Output Circuit

•
lit

lIZ

m

k

cs _ _--'I

'f1M1'

•

I

C

d

o
Do.o." 0

•
•

0

~R BC I1E

FG HI t..J1-< LM NO

,p OR 5T UV WX YZ (\ ~ 7'
0
' " I:H g; ~Z;, <> *+ - . /
L.- ~?
'0 12 3Y ';5 l8 g
/

o
•••
•o • • • oo o
••
••
• •o • o • •

~ 0

000

iDa

0

0

Dt 0

0

Po

0

o

o

0

0

0

0

0

0

0

0

,

0

/

• • ,• • ,•
• •
• oo • • •
•
•

0

0

0

0368-7

NOTE: Segments a and d appear as 2 segments each, but both halves
are driven together.

Figure 4: ICM7243B 14·Segment
Character Font with Decimal Point

0368-9

Figure 6: Random Access Timing

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR use.

NOTE: All typical values have b6sn charactsrizsd but are not tested.

13~58

ICM7243
WR

SEN

DISPLAY FULL

~~------------------

0368-10

Figure 7: Serial Access Mode Timing (Mode = 1)

TABLE 1: PIN DESCRIPTIONS, ICM7243A(B)
Signal

Pin

Function

Do -Os

10 -15
(8 -13)

Six·Bit ASCII Data input pins (active high).

CS,CS

16
(14-16)

Chip Select for decoding from ,.,.p address bus, etc.

WR

17

WRite pulse input pin (active low). For an active high write pulse,
CS can be used, and WR can be used as CS.

MODE

31

Selects data entry MODE. High selects Serial Access (SA)
mode where first entry is displayed in "leftmost" character and
subsequent entries appear to the "right". Low selects the Random Access (RA) mode where data is displayed on the charac·
ter addressed via Ao-A2 Address pins.

Ao/SEN

30

In RA mode it is the LSB of the character Address. In SA mode it
is used for cascading display driver/controllers for displays of
more than 8 characters (active high enables driver controller).

A1/CLeaR

29

In RA mode this is the second bit of the address. In SA mode, a
low input will CLeaR the Serial Address Counter, the Data Mem·
ory and the display.

A2/DISPlay FULL

28

In RA mode this is the MSB of the Address. In SA mode, the
output goes high after eight entries, indicating DISPlay FULL.

OSC/OFF

27

OSCillator input pin. Adding capacitance to Voo will lower the
internal oscillator frequency. An external oscillator is also applied to this pin. A low puts the display controller/driver into a
quiescent mode, shutting OFF the display and oscillator but reo
taining data stored in memory.

SEGa -SEG m, D.P.

2 -9 (7),
32-40

SEGment driver outputs.

CHARacter 1 - 8

18 -21,
23 -26

CHARacter driver outputs.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANnes OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but S('9 not testBd.

13-59

II

=ICM7243
CII

g"'"

::I

17
SEGMENTS

r----I-~f1j-~m-m-m-flJ-flJ-flJ
CHARI

8 CHARACTERS

I-==c....:.==-+~-':..-

Figure 8: Test Circuit

__ DISPLAY FULL OUTPUT

0368-11

edge of WR (or its equivalent). Subsequent changes on the
Address lines will not affect device operation. This allows
use of a multiplexed 6-bit bus controlling both address and
data, with timing controlled by WR.
Serial Access Mode. If the internal latch is set for Serial
Access (SA), (MODE latched high), the Serial ENable input
on SEN will be latched on the falling edge of WR (or its
equivalent). The CLR input is asynchronous, and will forceclear the Serial Address Counter to address 000 (CHARacter 1), and set all Data Memory contents to 100000 (blank)
at any time. The DISPlay FULL output is always active in SA
mode also, and indicates the overflow status of the Serial
Address Counter. If this output is low, and SEN is (latched
as) high, the contents of the Counter will be used to establish the Data Memory location for the Data input. The Counter is then incremented on the rising edge of WR. If SEN is
low, or DISPlay FULL is high, no action will occur. This allows easy "daisy-chaining" of display drivers for multiple
character displays in a Serial Access mode.

DETAILED DESCRIPTION
WR, CS, CS. These pins are immediately functionally
ANDed, so all actions described as occurring on an edge of
WR, with CS and CS enabled, will occur on the equivalent
(last) enabling or (first) disabling edge of any of these inputs. The delays from CS pins are slightly (about 5ns) greater than from WR or CS due to the additional inverter required on the former.
MODE. The MODE pin input is latched on the falling edge
of WR (or its equivalent, see above). The location in Data
Memory where incoming data will be placed is determined
either from the Address pins or the Serial Address Counter,
under control of this latch, which also controls the function
of Ao/SEN, Al/CLR, and A2/DISPIay FULL.
Random Access Mode. When the internal mode latch is
set for Random Access (RA) (MODE latched low), the Address input on Ao, Al and A2 will be latched by the falling

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tflSted.

13-60

ICM7243
Changing Modes. Care must be exercised in any appli·
cation involving changing from one mode to another. The
change will occur only on a falling edge of WR (or its equiv·
alent). When changing mode from Serial Access to Random Access, note that A2/DISPlay FULL will be an output
until WR has fallen low, and an Address drive here could
cause a conflict. When changing from Random Access to
Serial Access, A1 /CLR should be high to avoid inadvertent
clearing of the Data Memory and Serial Address Counter.
DISPlay FULL will become active immediately after the fall·
ing edge of WR.
Data Entry. The input Data is latched on the rising edge
of WR (or its equivalent) and then stored in the Data Memo·
ry location determined as described above. The six Data
bits can be multiplexed with the Address information on the
same lines in Random Access mode. Timing is controlled
by the WR input.
OSC/OFF. The device includes a one·pin relaxation oscillator with an internal capacitor and a nominal frequency of
200kHz. By adding external capacitance to VDD at the
OSC/OFF pin, this frequency can be reduced as far as desired. Alternatively, an external signal can be injected on
this pin. The oscillator (or external) frequency is pre-divided
by 64, and then further divided by 6 in the Multiplex Counter,
to drive the CHARacter strobe lines (see Display Output).
An intercharacter blanking signal is derived from the pre-divider. An additional comparator on the OSC/OFF input detects a level lower than the relaxation oscillator's range, and

blanks the display, disables the DISPlay FULL output (if ac·
tive), and clears the pre·divider and Mutliplex Counter. This
puts the circuit in a low·power·dissipation mode in which all
outputs are effectively open circuits, except for parasitic diodes to the supply lines. Thus a display connected to the
output may be driven by another circuit (including another
ICM7243) without driver conflicts.
Display Output. The address output of the Multiplex
Counter is multiplexed into the address input of the Data
Memory, except during WR operations (in Serial Access
mode, with SEN high and DISPlay FULL low), to control
display operations. The address decoder also drives the
CHARacter outputs, except during the inter-character blank·
ing interval (nominally about 5",5). Each CHARacter output
lasts nominally about 300",5, and is repeated nominally ev·
ery 2.5ms, i.e., at a 400Hz rate (times are based on internal
oscillator without external capacitor).
The 6 bits read from the Data Memory are decoded in the
ROM to the 17 (15 for ICM7243B) segment signals, which
drive the SEGment outputs. Both CHARacter and SEGment
outputs are disabled during WR operations (with SEN high
and DISPlay FULL Low for Serial Access mode). The out·
puts may also be disabled by pulling OSC/OFF low.
The decode pattern from 6 bits to 17 (15) segments is
done by a ROM pattern according to the ASCII font shown.
Custom decode patterns can be arranged, within these limitations, by consultation with the factory.

APPLICATIONS
8 CHARACTER LED DISPLAY

lILt"

T/\ ITt"RCTI
..LI \J I _
:::l..LI_

TL-It"
11,_

*U:::l_

8 _'_

1

CLR

CLR

CHAR
SEG
DISP FULL

+5V_ SEN
+5V_ MODE

.r

DATA
BUS

ViR
00-.

YDD
CS

L

t--

CLR

CHAR

r---

rOo.

+5

WR

SEG
OfSPFULL
MODE

t+-+5V
VSS~

Voo

Voo

CS

6

6

Viii. Its)
CS. (WR)
FIRST 8 CHARACTERS

CHAR

t---

SEN
+5V_ MODE

+-+ SV

t--

SEG
DISP FULL j - - - - -

L

6

",.

8

r--

V"~

• CHARACTER LED DISPLAY

• CHARACTER LED DISPLAY

SECOND 8 CHARACTERS

-------

CS

.......-+5V

Vss

II

nth 8 CHARACTERS

'1110' 'CM7243A. 15 '0I1CM72438
0368-12

Figure 9: Multicharacter Display using Serial Access Mode

lNTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE- All typical values have been characterized but are not ~sted.

13-61

~

"It
C\I

ICM7243

....

Ii APPLICATIONS

2

(Continued)

~~~~~~m~~~m~~oo~~

ftr-----.:
--+
t:::J

RBRa
RBR7

RRI

DISP
FULL

ETC.

IM6403
UART
RBR,-8
DR

20k

ICL7555
DELAY

ETC.

TH
200pF

0368-13

Figure 10: Driving Two Rows of Characters from a Serial Input.
UART converts data stream to parallel bytes. Bit 7 of each word sets which row data will be entered into.
Bit 8 will blank and reset whole display if low. Each MODE pin should be tied high. ICM7243A can also be
used, with inverter on RBR7 for one row.
Texas Instruments Inc., Dallas, Texas (214) 995-6611
(part # HDSP6508)
A.N.D., Burlingame, California (415) 347-9916 (part
#AND370R)
lEE Inc., Van Nuys, California (213) 787-0311 (part
#LR3784R)

COMPONENT SELECTION
Displays suitable for use with the ICM7243 may be obtained from the following manufacturers; among others:
Hewlett Packard Components, Palo Alto, California (415)
857·6620 (part #HDSP6508, HDSP6300)
General Instruments Inc., Palo Alto, California (415) 4930400 (part # MAN2815)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

13-62

BlO~OIL

ICM7243

n

I:

.....

fI)

WWWWWWWwwwwwwmWWWWWWWWWOOOOOOOOOOOOOOOOOO

I

ICM7243AIB
CS Az A, Ao Ow WR

I

P22

.."
IM8OC35
1M80C48

1'2)

I...:::'"

1

~

CS

ICM7243AIB
A, Ao Ow

Az

I I

--.Jl

r-

rTi?

I

1--=

i

Wii

~

I

CS

I
WI

ICM7243A1B
i
A, Ao Ow WR

Az

l..:~

1

ICM7243A1B
CS Az A, Ao Ow WR

I

t

I"" ?-

DB7

DBe

DBs-o

8-BIT BUS

WR

I
0368-14

Figure 11: Random Access 32-Character Display in IM80C48 system.
One port line controls A2. other two are CS lines. 8-bit data bus drives 6 data and 2 address lines. MODE
should be GrouNDed on each part.

+5V

+5V

+5V

+5V

+5V

'.4 AMP PEAK

'k

10011

10011

1

I

ICM7243

ICM7243

1411 (100mA PEAK)

:30011
I
I

I
I

(100mA PEAK)

--I
':' GND

GND ':'

0368-16
0368-15

(5b.) Common Anode Displays

(5a.) Common Cathode Displays

Figure 12: Driving Large Displays.
The circuits of Figures 12a and 12b can be used to drive 0.5" or larger alphanumeric displays, either common cathode (12a) or common anode (12b).

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

13·63

II

Section 14 - Timers/Clocks/
Counters with Display Drivers
ICM7170 .............. 14-1
ICM7207/A ........... 14-14
ICM7208 ............. 14-19
ICM7209 ............. 14-26
ICM7215 ............. 14-29
ICM7216A ............ 14-36
ICM7216B ............ 14-36
ICM7216C ............ 14-36
ICM7216D ............ 14-36
ICM7217 ............. 14-54
ICM7227 ............. 14-54
ICM7224 ............. 14-72
ICM7225 ............. 14-72
ICM7226A1B ......... 14-80
ICM7236 ............. 14-93
ICM7240 ............. 14-98
ICM7250 ............. 14-98
ICM7242 ............ 14-108
ICM7249 ............ 14-114
ICM7555 ............ 14-123
ICM7556 ............ 14-123

•

.U~UIbS...

ICM7170
J.tP-Compatible
Real-Time Clock

.....

o

GENERAL DESCRIPTION

FEATURES

The ICM7170 real time clock is a microprocessor bus
compatible peripheral, fabricated using Intersil's silicon gate
CMOS LSI process. An 8-bit bidirectional bus is used for the
data I/O circuitry. The clock is set or read by accessing the
8 internal separately addressable and programmable counters from 1/100 seconds to years. The counters are controlled by a pulse train divided down from a crystal oscillator
circuit, and the frequency of the crystal is selectable with
the on-chip command register. An extremely stable oscillator frequency is achieved through the use of an on-chip regulated power supply.
The device access time (tacel of 300ns eliminates the
need for any microprocessor wait states or software overhead. Furthermore, the ALE (Address Latch Enable) input is
provided for interfacing to microprocessors with a multiplexed address/data bus. With these two special features,
the ICM7170 can be easily interfaced to any available microprocessor.
The ICM7170 generates two types of interrupts. The first
type is the periodic interrupt (i.e., 100Hz, 10Hz, etc.) which
can be programmed by the internal interrupt control register
to provide 7 different output signals. The second type is the
alarm interrupt. The alarm time is set by loading an on-chip
51 -bit RAM that activates an interrupt output through a comparator. The alarm interrupt occurs when the real time counter and alarm RAM time are equal. A status register is available to indicate the interrupt source.
An on-chip Power-Down Detector eliminates the need for
external components to support the battery back-up function. When a power-down or power failure occurs, internal
logic switches the on-chip counters to battery back-up operation. Read/write functions become disabled and operation
is limited to time-keeping and interrupt generation, resulting
in low power consumption.
Internal latches prevent clock roll-over during a read cycle. Counter data is latched on the chip by reading the
100th-seconds counter and is held indefinitely until the
counter is read again, assuring a stable and reliable time
value.

• 883B-Rev C Compliant
• 8-Bit ",p Bus Compatible
-Multiplexed or Direct Addressing
• Regulated Oscillator Supply Ensures Frequency
Stability and Low Power
• Time From 1/100 Seconds to 99 Years
• Software Selectable 12/24 Hour Format
• Latched Time Data Ensures No Roll-Over During
Read
• Full Calendar With Automatic Leap Year Correction
• On-Chip Battery Backup Switchover Circuit
• Access Time Less Than 300ns
• 4 Programmable Crystal Oscillator Frequencies over
Industrial Temp Range
• 3 Programmable Crystal Oscillator Frequencies over
Military Temp Range
• On-Chip Alarm Comparator and RAM
• Interrupts from Alarm and 6 Selectable Periodic
Intervals
• Standby Micro-Power Operation: 2",A Typ. at 3_0V
and 32kHz Crystal

APPLICATIONS
• Portable and Personal Computers • Data Logging
• Industrial Control Systems • Point Of Sale

ORDERING INFORMATION
Part
Number
ICM7170IPG
ICM7170lDG

0372-1

Temperature
Range

Package

- 40'C to + 85'C

24-Pin Plastic Dip

-40'Cto + 85'C

AI

A2

AD

A3

OSC OUT

A4

CSC IN

24-Pin Ceramic

INT SOURCE

ICM7170lBG
ICM7170MDG

- 40'C to + 85'C

24-Pin S.O.I.C.
(Surface Mount)

iNT
Vss
VBACKUP

-55'Cto +125'C 24-Pin Ceramic

cs
ALE

Wi!
RD
VDo

00

D7

ICM7170MDG/883C -55'Cto + 125'C 24-Pin Ceramic

01
02

06
05

ICM7170AIPG

-40'Cto + 85'C

24-Pin Plastic Dip

03

04

ICM7170AIBG

-40'Cto +85'C

24-Pin S.O.I.C.

"A" Parts Screened to <4 JJ-A ISTBY

@

191
0372-11

Figure 1: Pin Configurations

32 KHz

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
301680-006

NOTE: All typical VSIU6S have been characterized but are not tested.

14-1

...... ICM7170
~

::I ABSOLUTE MAXIMUM RATINGS

!::!

Supply Voltage .................................... 8V
Power Dissipation (Note 1) ...................... 500mW
Input Voltage (Any Terminal)
(Note2) ..................... Voo +0.3VtoVss -0.3V

Operating Temperature ............... - 40'C to + 85'C
Storage Temperature ................ - 65'C to + 150'C
Lead Temperature (Soldering, 10sec) ............. 300'C

NOTE 1: TA~ 2S'C.
NOTE 2: Due to the SCR structure inherent in the CMOS process. connecting any terminal at voltages greater than Voo or less than Vss may cause destructive
device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same power supply be applied to the device before its
supply is established, and that in multiple supply systems, the supply to the ICM7170 be turned on first.
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress fatings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
OSCILLATOR
CRYSTAL

0372-2

Figure 2: Functional Diagram

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(TA = -40'C to + 85'C, Voo= +5V ± 10%, VBAGKUP=VOO, VSS = OV unless otherwise specified)
Symbol

Parameter

Specification

Test Conditions

Min
Voo

ISTBY(1)

Voo Supply Range

Standby Current

Typ

FOSG = 32kHz

1.9

5.5

FOSG = 1, 2, 4MHz

2.6

5.5

FOSG = 32kHz
Pins 1-8, 15-22 & 24 = Voo
Voo = VSS; VBAGKUP = Voo - 3.0V

Units

Max

7170

2.0

20.0

7170A

2.0

5.0

V

p.A

ISTBY(2)

Standby Current

FOSG = 4MHz
Pins 1-8, 15-22 & 24 = Voo
Voo = VSS; VBAGKUP = Voo - 3.0V

20

150

p.A

100(1)

Operating Supply Current

FOSG = 32kHz
Read/Write Operation at 100Hz

0.3

1.2

mA

100(2)

Operating Supply Current

FOSG = 32kHz
Read/Write Operation at 1MHz

1.0

2.0

mA

VIL

Input low voltage (Except Osc.)

Voo=5.0V

0.8

V

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bsen characterized but are not tested.

14-2

ICM7170
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(TA= -40'C to + 85'C, Voo= +5V ±10%, VSACKUP=VOO, Vss =
Symbol

Parameter

ov unless otherwise specified) (Continued)
Specification

Test Conditions
Min

Typ

VIH

Input high voltage (Except Osc.)

Voo=5.0V

VOL

Output low voltage (Except Osc.)

IOL =1.6mA

VOH

Output high voltage except
INTERRUPT (Except Osc.)

IOH= -400,..A

2.4

IlL

Input leakage current

VIN = Voo or Vss

-10

0.5
0.5

Units

Max

2.4

V
0.4

V

+10

,..A

+10

,..A

V

IOL

Tristate leakage current (Do-D7)

Vo=VooorVss

-10

VSATTERY

Bai::kup Battery Voltage

Fosc= 1, 2, 4MHz

2.6

VDO-1.3

V

VSATTERY

Backup Battery Voltage

Fosc=32kHz

1.9

VDO-1.3

V

IOL

Leakage current INTERRUPT

Vo=Voo

10

,..A

INTSOURCE
connected to Vss

0.5

CliO

CAPACITANCE Do-D7

8

pF

CAOORESS

CAPACITANCE Ao-A4

6

pF

CCONTROL

CAP. RD, WR, CS ALE

6

pF

Total Osc. Input Cap.

3

pF

CINOSC.

AC CHARACTERISTICS (TA= -40'Cto + 85'C, Voo= +5V ±10%, VSACKUP=VOO, Do-D7 Load
Capacitance = 150pF, VIL = O.4V, VIH = 2.8V unless otherwise specified)
Symbol

Parameter

Min

Max

Units

READ CYCLE TIMING
Ird

READ to DATA valid

250

ns

taee

ADDRESS valid to DATA valid

300

ns

!eye

READ cycle time

400

ns

trx

RD high to bus tristate'

tas
t a,

ADDRESS to READ set up time'

50

ns

ADDRESS HOLD time after READ'

0

ns

25'

ns

'Guaranteed Parameter by Design
WRITE CYCLE TIMING
tad

ADDRESS valid to WRITE strobe

50

ns

twa

ADDRESS hold time for WRITE

0

ns

twl

WRITE pulse width, low

100

ns

Iwh

WRITE high time

300

ns

t,h

Read high time

150

ns

Idw

DATA IN to WRITE set up time

100

ns

Iwd

DATA IN hold time after WRITE

30

ns

400

ns

WRITE cycle time
!eve
MULTIPLEXED MODE TIMING
tn

ALE Pulse Width, High

50

ns

tal

ADDRESS to ALE set up time

30

ns

tla

ADDRESS hold time after ALE

30

ns

Capacitance values are maximum values and are sample tested only.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characteriz9d but are not tested.

14-3

•

..... ICM7170
~

:Ii ICM 7170 ELECTRICAL CHARACTERISTICS (TEST SPECIFICATION)
FOR MIL-STD-883 COMPLIANCE

!:!

ABSOLUTE MAXIMUM RATINGS

NOTE:

Supply Voltage .................................... BV
Power Dissipation (Note 1) ...................... 500mW
Input Voltage (Any Terminal)
........................... VDD +0.3V to Vss -0.3V
Operating Temperature .............. -55°C to + 125°C
Storage Temperature ................ -65°C to + 150°C
Lead Temperature (Soldering, 10 sec) ............. 300°C

and functional operation of the device at these or any other conditions

NOTE 1:

TA~

Stresses above those listed under ''Absolute Maximum Ratings"
may cause permanent damage to the devics. These are stress ratings only

above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended peri·
ods may affect device reliability.

25°C.

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (VDD = 5V ± 10%, VBACKUP = VDD, TA =
Symbol

-55°C to + 125°C, unless otherwise specified)
Specification

Test Conditions

Parameter

Min
VDD

VDD Supply Range

Typ

Fosc = 32kHz

1.9

5.5

Fosc = 1, 2MHz

2.6

5.5

ISTBY(l)

Standby Current

FOSC=32 kHz
All chip I/O to VDD
VDD=VSS: VBACKUP=VDD-3.0V

ISTBY(2)

Standby Current

Fosc = 1, 2M Hz
All chip I/O to VDD
7170A
VD -

IDD(l)

Operating Supply Current

Units

Max
V

2.0

40

/LA

30

200

/LA

\ldC:l:~ 3.0V

5.0

\Il\I\,'

Operation at 100 Hz
IDD(2)

Operating Supply Current

osc=32 kHz
Read/Write Operation at 1 MHz

VIL

Input Low Voltage (Except Osc.)

VDD=5.0V

VIH

Input High Voltage (Except Osc.)

VDD=5.0V

VOL

Output Low Voltage (Except Osc.)

IOL =1.6mA

VOH

Output High Voltage Except INTERRUPT
(Except Osc.)

IOH=400/LA

2.5

0.3

1.2

mA

1.0

2.0

mA

O.B

V

0.5

V

2.B

V

IlL

Input Leakage Current

VIN = VDD or Vss

-10

0.5

+10

/LA

IOL

Tristate Leakage Current (00-07)

VIN=VDDorVSS

-10

0.5

+10

/LA

VBATTERY

Backup Battery Voltage

OSG=32 kHz

1.9

VDD-1.5

V

IOL

Leakage Current INTERRUPT

V -V
orV
IINTSOURCE
0- DD
SS connected to Vss

10

/LA

0.5

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

14-4

ICM7170
AC CHARACTERISTICS (TA = -55·Cto + 125·C, voo = 5V ±10%, VBACKUP =
Capacitance = 150 pF, VIL = 0.4V, VIH = 3.20Vunless otherwise specified)
Symbol

Parameter

Min

VOO, 00-07 Load
Max

Units

250

ns

350

ns

READ CYCLE TIMING
trd

READ to DATA Valid

tACO

ADDRESS Valid to DATA Valid

teyC

READ Cycle Time

trx

RD High to Bus Tristate

tas

ADDRESS to READ Set Up Time

tar

ADDRESS HOLD Time after READ

trh

READ High Time

WRITE CYCLE TIMING
tad

ns

450
100
100

~

-.1. ~ ..!'~\\C.
.4

ADDRESS V

'\.'W\-"'''
rott~'"(> C;'"

..."".

ns
ns
ns
ns

~\\

100

ns

twa

ADDRESS H~~~..t4.lJ'WRrTE

50

ns

twl

WRITE Pulse L~Width

125

ns

twh

WRITE Pulse Width High

325

ns

tdw

DATA IN to WRITE Set Up Time

125

ns

twd

DATA IN Hold Time after WRITE

50

ns

tcvc

WRITE Cycle Time

450

ns

MULTIPLEXED MODE TIMING
til

ALE Width

50

ns

tal

ADDRESS to ALE Set Up Time

30

ns

~a

ADDRESS Hold Time after ALE

40

ns

m
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPREss, IMPLIED OR STATUTORY. INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typicsI values havs bHn chsracletfz8d but sre not tBsted.

14·5

..... ICM7170
~

:I

!:!

READ CYCLE TIMING FOR NON-MULTIPLEXED BUS (ALE = VIH. WR = VIH)

ADDRESS VALlD,CS LOW

iii

00-07

~------~------~
0372-3

WRITE CYCLE TIMING FOR NON-MULTIPLEXED BUS (ALE = VIH. RD = VIH)

Ao-A4 ~

ADDRESS VALlD,CS LOW

r

twa

~-------------~~--------------~~

i-----twf------i

_____
00-07

{""'::::::::::::::::-Idw-I-II-P--UT---D:A-T-A:V~A-Ll-D---tW_d3

_______ _

0372-4

Figure 3: Timing Diagrams - Nonmultiplexed Bus

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

14-6

ICM7170
READ CYCLE TIMING FOR MULTIPLEXED BUS (WR = VI H)

AD-A .. DO-D7

9" - - -

1--------'1"
i4----ql----+/

ALE

1-___ 1'1

0372-5

WRITE CYCLE TIMING FOR MULTIPLEXED BUS (RD = VIH)

AD-A.. DD-D7

9" -

- -

II.
1--'-_ _ 111 - - - - I
ALE

/+----1.1

!----------I'd-*I----

0372-6

NOTE: The AO to A4 address inputs may be connecled 10 the DO to D4 data lines when a mulliplexed bus is used.

Figure 4: Timing Diagrams - Multiplexed Bus
Table 1
Signal

Pin

DETAILED DESCRIPTION
Description

WR

1

Write input

ALE

2

Address latch enable input

CS

3

Chip select input

A4-AO
OSCOUT

4-8

Oscillator output

OSCIN

10

Oscillator input

INTSOURCE

11

Interrupt source

INTERRUPT

12

Interrupt output

VSS(GNO)

13

Digital common

VSACKUP

14
15-22

This circuit uses a regulated CMOS Pierce oscillator, for
maximum accuracy, stability, and low-power consumption.
Externally, one crystal and two capacitors are required. One
of the capaCitors is variable and is used to trim or tune the
oscillator output. Typical values for these capaCitors are
CIN = 15pF and COUT = 10- 35pF, or approximately double
the recommended CLOAD for the crystal being used. Both
capacitors must be connected from the respective oscillator
pins to VDD for maximum stability.
The oscillator output is divided down to 4000Hz by one of
four selected ratios, via a variable prescaler. The ICM7170
can use anyone of four different low-cost crystals:
4.194304MHz, 2.097152MHz, 1.048576MHz, or 32.768kHz.
The ICM7170MOG is available with 3 crystal frequency options only. (4.194304 MHz is not avail. with military version.)
The command register must be programmed for the frequency of the crystal chosen, and this in turn will determine
the prescaler's divide ratio.
Command Register frequency selection is written to the
DO and 01 bits at address 11 H and the 12 or 24 hour format
is determined by bit 02, as shown in Table 4.

Address inputs

9

00-07

Oscillator

Battery negative side
Data 1/0

VDD

23

Positive digital supply

RD

24

Read input

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE All typical values haV6 b98n characterized but ars not tested

14-7

..e ICM7170

":I

g

The periodic interrupts can occur concurrently and in addition to alarm interrupts. They are controlled by bits in the
interrupt mask register, and are enabled by setting the appropriate bit to a "1" as shown in Table 5. Bits DO through
D6 in the mask register, in conjunction with bits DO through
D6 of the status register, control the generation of interrupts
according to Figure 5.
The interrupt status register, when read, indicates the cause
of the interrupt and resets itself on the rising edge of the RD
signal. When any of the counters having a corresponding bit
in the status register roll over to zero, that bit is set to a "1"
regardless of whether the corresponding bit in the interrupt
mask register is set or not. This also applies to the alarm
compare bit.
Consequently, when the status register is read it will always
indicate which counters have rolled over to zero and if an
alarm compare occurred, since the last time it was read.
This requires some speCial software considerations. If a
slow interrupt is enabled (i.e. hourly or daily), the program
must always check the slowest interrupt that has been enabled first, because all the other lower order bits in the
status register will be set to "1" as well. Bit D7 is the global
interrupt bit, and when set to a "1", indicates that the 7170
did indeed generate a hardware interrupt. This is useful
when other interrupting devices in addition to the 7170 are
attached to the system microprocessor, and all devices
must be polled to determine which one generated the interrupt.

The 4000Hz signal is divided down further to 100Hz,
which is used as the clock for the counters. Time and calendar information is provided by 8 consecutive addressable,
programmable counters: 100ths of seconds, seconds, minutes, hours, day of week, date, month, and year. The data is
in binary format and is configured into 8 bits per digit. See
Table 4 for address information. Any unused bits are held at
logic "0" during a read and ignored during a write operation.

Alarm Compare RAM
On the chip are 51 bits of Alarm Compare RAM grouped
into words of different lengths. These are used to store the
time, ranging from 100ths of seconds to years, for comparison to the real-time counters. Each counter has a corresponding RAM word. In the Alarm Mode an interrupt is generated when the current time is equal to the alarm time. The
RAM contents are compared to the counters on a word by
word basis. If a comparison to a particular counter is unnecessary, then the appropriate 'M' bit in Compare RAM should
be set to logic "1 ".
The 'M' bit, referring to Mask bit, causes a particular RAM
word to be masked off or ignored during a compare. Table 4
shows addresses and Mask bit information.

Periodic Interrupts
The interrupt output can be programmed for 6 periodic
signals: 100 Hz, 10Hz, once per second, once per minute,
once per hour, or once per day. The 100 Hz and 10Hz
interrupts have instantaneous errors of ± 2.5% and
±0.15% respectively. This is because non-integer divider
circuitry is used to generate these signals from the crystal
frequency, which is a power of 2. The time average of these
errors over a 1 second period, however, is zero. Consequently, the 100 Hz or 10Hz interrupts are not suitable as
an aid in tuning the oscillator; the 1 second interrupt must
be used instead.

Table 2: Command Register Format
COMMAND REGISTER ADDRESS (10001b, 11h) WRITE-ONLY
D7

nla

I

I

D6

nla

I

D5

I

Test

I

I

I

D4

D3

I

Int.

Run

I

I

I

D2
12/24

I

I

Dl

I

Freq

DO
Freq

Table 3: Command Register Bit Assignments
D1

DO

Crystal
Frequency

02

24/12 Hour
Format

03

Run/Stop

04

Interrupt
Enable

05

Test Bit

0

0

32.768kHz

0

12 hour mode

0

Stop

0

Interrupt disabled

0

Normal Mode

0

1

1.048576MHz

1

24 hour mode

1

Run

1

Interrupt enable

1

Test Mode

1

0

2.097152MHz

1

1

4.194304MHz

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE:: All typical values have been characterlz9d but arB not testsd.

14-8

ICM7170
Table 4: Address Codes and Functions
Address
A4

A3

A2

A1

AD

HEX

0
0

0
0

0
0

0
0

0
1

00
01

0
0
0
0
0
0
0
0

0
0
0
0
0
0
1
1

0
0
1
1
1
1
0
0

1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1

02
03
04
05
06
07
08
09

0
0
0
0
0
0

1
1
1
1
1
1

0
0
1
1
1
1

1
1
0
0
1
1

0
1
0
1
0
1

OA
OB
OC
OD
OE

1

0

0

0

0

10

1

0

0

0

1

11

DATA

Function
07
Counter-1 11 00 seconds
Counter-hours
12 Hour Mode
Counter-minutes
Counter-seconds
Counter-month
Counter-date
Counter-year
Counter-day of week
RAM-1 1100 seconds
RAM-hours
12 hour Mode
RAM-minutes
RAM-seconds
RAM-month
RAM-date
RAM-year
RAM-day of week
Interrupt Status
and Mask Register
Command register

OF

06

05

-

-

-

-

-

-

-

-

-

.

-

-

-

-

-

-

-

-

.

M
M

-

M
M
M
M
M
M

-

-

-

-

-

-

-

-

-

-

-

-

03

04

02

Value
01

DO
0-99
0-23
1-12
0-59
0-59
1-12
1-31
0-99
0-6
0-99
0-23
1-12
0-59
0-59
1-12
1-31
0-99
0-6

-

M

-

-

+

-

-

NOTES: Address 10010 to 11111 ( 12h to 1Fh) are unused.
.+' Unused bit for Interrupt Mask Register, MSB bit for Interrupt Status Register.
'-' Indicates unused bits.
'" AM/PM indicator bit in 12 hour format. Logic "0" indicates AM, logic "1" indicates PM.
'M' Alarm compare for particular counter will be enabled if bit is set to logic "0",

Table 5: Interrupt and Status Registers Format
INTERRUPT MASK REGISTER ADDRESS (1 OOOOb. 1Oh) WRITE-ONLY
D7
Not Used

I
I

I

D6
Day

I

D5
Hour

I

I

D4
Min.

I
I

D3
Sec.

I

I

D2
1/10sec.

I

I

D1
1/100 sec.

I
I

DO
Alarm

INTERRUPT STATUS REGISTER ADDRESS (10000b. 10h) READ-ONLY
D7

D6

D5

D4

D3

D2

D1

DO

Global
Interrupt

Day

Hour

Min.

Sec.

1/10 sec.

1/100 sec.

Alarm

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vaJuss have been characteriz9d but sre not tested

14-9

...... ICM7170
~

the battery-backup switchover function, as shown in Figure
6. Whenever the voltage from the Vss pin to the VSACKUP
pin is less than approximately 1.0V (the Vth of the N-channel MOSFET), the data bus I/~ buffers in the 7170 ar~ automatically disabled and the chip cannot be read or written
to. This prevents random data from the microprocess?r being written to the clock registers as the power supply IS going down.
Actual switchover to battery operation occurs when the
voltage on the VSACKUP pin is within ±50 mV of Vss. This
switchover uncertainty is due to the offset voltage of the
CMOS comparator that is used to sense the battery voltage.
During battery backup, devic? operation is limited to t!mekeeping and interrupt generation only, thus achieVing m~cro­
power current drain. If an external battery-backup SWltc~­
over circuit is being used with the 7170, the VSACKUP pin
should be tied to the Voo pin. The same also applies if
standby battery operation is not required.

Ii Interrupt Operation

!:!

The interrupt output N-channel MOSFET is active at all
times when the Interrupt Enable bit is set (bit 4 of the Command Register), and operates in both the standby and battery backup modes.
Since system power is usually applied between Voo and
Vss the user can connect the Interrupt Source (pin #11) to
Vss: This allows the Interrupt Output to turn on only w~ile
system power is applied and will not be pull.ed to Vss dur!ng
standby operation. If interrupts are required only dUring
standby operation, then the interrupt source pin should ~e
connected to the battery's negative side (VSACKUP). In this
configuration, for example, the interrupt could be used to
turn on power for a cold boot.

Power-Down Detector
The ICM7170 contains an on-chip power-down detector
that eliminates the need for external components to support

INTERRUPT MASK
REGISTER ..........,.....-r-""'T.....r"-r-""'T-T""

INTERRUPT STATUS
1+___
REGISTER "'-l~....&_""""""--""''''''''''''

Ri5

or ADD HEX 10 => RESET
INTERRUPT
ENABLE
CR BIT 4
0372-8

Figure 5: Interrupt Output Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF ~ALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, eXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIE OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE; All typical values have been characterized but are not tested.

14-10

IID~Do..

ICM7170
Time Synchronization

by a logical "0" CS as shown in f!gures 3 and 4. The 7170
will also work satisfacto~with CS grounded. This access
also to be controlled by RD and WR only.
With the ALE (Address Latch Enable) input, the ICM7170
can be interfaced directly to microprocessors that use a
multiplexed address/data bus by connecting the address
lines AO-A4 to the data lines 00-04. To address the chip,
the address is placed on the bus and ALE is strobed. On the
falling edge, the address and CS information is read into the
address latch and buffer. RD and WR are used in the same
way as on a non-multiplexed bus. If a non-multiplexed bus is
used, ALE should be connected to Voo.

Time synchronization is achieved through bit 03 of the
Command Register, which is used to enable or disable the
100Hz clock from the counters. A logic "1" allows the counters to function and a logic "0" disables the counters. To
accurately set the time, a logic "0" should be written into 03
and then the desired times entered into the appropriate
counters. The clock is then started at the proper time by
writing a logic "1" into 03 of the Command Register.

Latched Data
To prevent ambiguity while the processor is gathering
data from the registers, the ICM7170 incorporates data
latches and a transparent transition delay circuit.
By accessing the 100ths of seconds counter an internal
store signal is generated and data from all the counters is
stored into a 36-bit latch. A transition delay circuit will delay
a 100Hz transition during a READ cycle. The data stored by
the latches is then available for further processing until the
100ths of seconds counter is read again.

n

•.........
o

Test Mode
The test mode is entered by setting D5 of the Command
Register to a logic "1". This connects the 1OOHz counter to
the oscillator'S output. The peak-to-peak voltage used to
drive osc. out should not be greater than the oscillator's
regulated voltage. The signal must be referenced to Voo.

Oscillator Tuning

Control Lines

Oscillator tuning should not be attempted by direct monitoring of the oscillator pins, unless very specialized equipment is used. Extemal connections to the oscillator pins
cause capacitive loading of the crystal, and shift the oscillator frequency. As a result, the precision setting being at-

The RD, WR, and CS sig~als are active low inputs. Data
is placed on the bus from counters or registers when RD is
a logic "0". Data is transferred to counters or registers
when WR is a logic "0". RD and WR must be accompanied

POSITIVE SUPPLY RAIL

(+5V)

VDD

~------------------------------~~--------+Voo

Pin 23

+
BATTERY ~

L-_ _~ VBACK

t--......- - - - - - - - -.....----.

r-__~--_.--_1--_.V~
INTERNAL GROUND

Pin 14

II

DIGITAL GROUND

0372-9

Figure 6: Simplified 7170 Battery Backup Circuit
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY DBUGATIDN WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE

;:~~~=~~~~~ ~~~L~~V! ~~~~ ~~~~

UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

NOTE: AN typicsJ vs/u6s have ~ _ _ bul818 not tsslBd.

14-11

.......~

:E

ICM7170
tempted is corrupted. One indirect method of determining

PCB DESIGN CONSIDERATION

~ the oscillator frequency is to measure the period between

1) Layout Quartz Crystal traces as short as possible.
2) Keep Crystal traces as far as possible from other
traces.
3) PCB must accept both Saronix and Statek
32.768kHz Crystals.
4) Completely surround crystal traces with VDD trace.
5) Try to keep oscillator traces on one side of the PCB.
6) Trimmer capacitor must be accessible from the top
of the PCB after it is inserted into the appropriate
connector.
7) The fixed and variable oscillator capacitors must be
referenced to VDD' Vss is not an AC ground for the
oscillator.

interrupts on the Interrupt Output pin (# 12). This measurement must be relative to the falling edges of the INTERRUPT pin. The oscillator set-up and tuning can be performed as follows:
1) Select one of 4, readily-available oscillator frequencies and place the crystal between OSC IN (pin
#10) and OSC OUT (pin #9).
2) Connect a fixed capacitor from OSC IN to VDD.
3) Connect a variable capacitor from OSC OUT to
VDD. In cases where the crystal selected is a 32kHz
Statek type (CL = 9pF), the typical value of
CIN=15pF and COUT=5pf-35pF.
4) Place a 4.7K!l resistor from the "IN'"T""'E""R""R"'U""P"'T pin to
VDD, and connect the INT SOURCE pin to VSS.
5) Apply 5V power and insure the clock is not in standby mode.
6) Write all O's to the Interrupt Mask Register, disabling all interrupts.
7) Write to the Command Register with the desired oscillator frequency, Hours mode (12 hour or 24 hour),
Run="1", Interrupt Enable = "1", and Test = "0".
8) Write to the Interrupt Mask Register, enabling onesecond interrupts only.
9) Monitor the INTERRUPT output pin with a precision
period counter and trim the OSC OUT capacitor for
a reading of 1.000000 seconds. The period counter
must be triggered on the falling edge of the interrupt
output for this measurement to be accurate.
10) Read the Interrupt Status Register. This action resets the interrupt output back to a logic "1" level.
11) Repeat steps 9 and 10 with a software loop. A suitable computer should be used.

APPLICATION NOTES
Digital Input Termination During Backup
To ensure low current drain during battery backup operation, none of the digital inputs to the 7170 should be allowed to float. This keeps the input logic gates out of their
transition region, and prevents crossover current from flowing which will shorten battery life. The address, data, CS,
and ALE pins should be pulled to either VDD or Vss, and the
RD and WR inputs should be pulled to VDD. This is necessary whether the internal battery switchover circuit is used
or not.

IBM/PC Evaluation Circuit
Figure 7 shows the schematic of a board that has been
designed to plug into an IBM PC or compatible computer. It
features full buffering of all 7170 address and data lines,
and switch selectable 1/0 block select. A provision for setting the priority level of the 7170 periodic interrupt has also
been added.
Batteries

Crystals

Panasonic
Rayovac

Statek 32kHz CX-IV
SARONIX 32kHz NTF3238

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE- All typical values have been characterized but are not tested

14-12

ICM7170
.sv

.sv

10

A"

Ag

A'3

AS

A,.

A7

A,S

AS

A,S

AS

i-!'lHr----< iOR
!-!=Hf----< iiiW

B,.
B'3

~l l/O

BLOCK
SELECT

'---.--J

4x lOOk SIP
SRI
All

AEN

.sv
GND

A4

A28

A3

US
5 5 74HCT541
A.

A29

A2

4 A3

A30

Al

A31

AO

3 A,
2 AI

..r;---=-4'

0372-10

Figure 7: IBM PC Interface for ICM7170

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTOAY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.
NOTE- All typical values have been characterized but are not test9(/.

14-13

D~DIL

~

ICM7207/A

~

GENERAL DESCRIPTION

FEATURES

The ICM7207 / A consist of a high stability oscillator and
frequency divider providing 4 control outputs suitable for frequency counter timebases. Specifically, when used as a frequency counter timebase in conjunction with the ICM7208
frequency counter, the four outputs provide the gating signals for the ,count window, store function, reset function and
multiplex frequency reference. Additionally, the duration of
the count window may be changed by a factor of 10 to
provide a 2 decade range counting system.
The normal operating voltage of the ICM7207/A is 5
volts. The typical power dissipation is less than 2mW when
using an oscillator frequency of 6.5536MHz with the 7207
and 5.24288MHz with the 7207A.
In the 7207/A the GATING OUTput, ReSeT, and the
MULTIPLEX output provide both pull up and pull down,
eliminating the need for 3 external resistors; although, buffering must be provided if interfacing with TTL is required.

• Stable HF Oscillator
• Low Power Dissipation";2mW With 5 Volt Supply
• Counter Chain Has Outputs at + 212 and + 2n or
+(2nX 10); n= 17 for 7207, and 20 for 7207A
• Low Impedance Output Drivers"; 100 Ohms
• Count Windows of 10/100ms (7207 With 6.5536MHz
Crystal) or 0.111 Sec. (7207A With 5.24288MHz
Crystal)

...= CMOS Timebase Generator

APPLICATIONS
•
•
•
•

System Timebases
Oscilloscope Calibration Generators
Marker Generator Strobes
Frequency counter Controllers

iiii'

NIC

ORDERING INFORMATION

GATING OUT

ordei
Number

Temperature
Range

ICM72071JD
ICM72Q71PD
ICM7207EVlKit

- 25°C.to
- 25°C to

Package

+ 85°C
+ 85°C

14-Pin CERDIP
14-Pin PLASTIC DIP
EV/Kit*

-

ICM7207AIJD
- 25°C to
ICM7207AIPD
- 25°C to
ICM7207AEV /Kit
-

+ 85°C
+ 85°C

oCoN
'i'

0ICOu-r

I

f~

I

+21'

J

NIC

NIC

NIC
0348-1

Figure 1: Pin Configuration
(Outline dwg PO)

l~
":"

4 Vas ~ulllrr.wtets on

-;-

I

I

I

I

I
I

V

....

~

Af.

CONTROL

fCM 'nIJ7A

...

(+1')

~

MULTIPLEX
OUTPUT

Voo

OleiN

14-Pin CERDIP
14-Pin PLASTIC DIP
EV/Kit·

L

MUXOUT
RANGE CONTROL

Ole OUT

'These EV IKlts contain iust the IC and the corresponding crystal. The
ICM7207A is also used in the 4%-Digit Counter/Driver kits, the ICM7224
EVlKit, ICM7225 EVlK~, and ICM7236 EV/Kit, which include severallCs, a
crystal, PC board, and some passive components.

'i'

NIC

Vas

.

l

r-t:l

I

iiiiiT ,

.,,

t-

t

Afl~tSTORE

0348-2

Figure 2: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHAll BE THAT STATED IN THE WARRANTY ARTICLE OF THE DDNDITION OF SALE.
THE WARRANTY SHAll BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED DR STATUTORY. INCLUDING THE IMPLIED WARRANnES OF
MERCHANTABILITY AND FITNESS FOR A PARnCULAR USE.
202200-003
NOTE: AN typIcsJ vsIuBs have been chBracteriz6d but are not testsd.

14-14

ICM7207/A
ABSOLUTE MAXIMUM RATINGS
Output Currents ................................ 25mA
Power Dissipation @ 25'C Note 1 ............... 200mW
Operating Temperature Range ......... - 25'C to + 85'C
Storage Temperature Range . . . . . . . . .. - 65'C to + 125'C
Lead Temperature (Soldering, 10sec) ............. 300'C

Supply Voltage (Voo-Vss) ....................... 6.0V
Input Voltages ................. Vss-0.3VtoVoo+0.3V
Output Voltages:
7207 .................................. Vss to +6V
7207A .................................. VootoVss
NOTE 1: Derate by 2mW/,C above 2S'C.

Absolute maximum ratings refer to values which if exceeded may permanently change or destroy the device.

NOTE: Stresses above those listed under "Abso/ute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliabilify.

ELECTRICAL CHARACTERISTICS
fose= 6.5536MHz(7207), 5.24288MHz(7207A), Voo = 5V, T A = 25'C, VSS = OV, test circuit unless otherwise specified.
Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

Voo

Operating Voltage Range

- 20'C to + 85'C

5.5

V

100

Supply Current

All outputs open circuit

260

1000

,..,A

Rds(on)

Output on Resistances

Output current = 5mA
All outputs

50

120

0.

IOLK

Output Leakage Currents

All outputs (STORE only)

50

,..,A

(ROUT)

(Output Resistance
Terminals 12,13,14)

Output current=50,..,A, 7207A
only

33K

0.

Ipd

Input Pulldown Current

Terminal 11 connected to Voo

Input Noise Immunity

4

50

200

fose

Oscillator Frequency Range

Note 2

fSTAS

Oscillator Stability

CIN=COUT=22pF

rOse

Oscillator Feedback
Resistance

Quartz crystal open circuit
Note 3

2
0.2
3

,..,A

% supply voltage

25
10

MHz

1.0

ppmlV
Mo.

NOTES: 2. DynamiC dividers are used in the initial stages 01 the divider chain. These dividers have a lower frequency of operation determined by transistor sizes,
threshold voltages and leakage currents.
3. The feedback resistor has a non-linear value determined by the oscillator instantaneous input and output voltage voltages and the supply voltage.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AI{ typical values have been characterized but are not tested.

14-15

ICM7207/A

CRYSTAL PARAMETERS
elN - CoUT ..- 22pF

r------------------------.-,

~----~----~----,

L).

ICM7201
f .. 6.5636MHl

Rs -40n
Ct- 15mpF
Co-3.6pF

ICM7201A
f·S.2. . . .Hz
Rs < 7SO
Co '-

..
.....
u
Z

6.0

~

0

a:

/

5.0

A-

4.0

:I

~

:I

;c

3.0

/



/

5

400

300
1.8kHz RC MUX

200
100

2.0
3.0
4.0
5.0
SUPPLY VOLTAGE (V)

Vso~

500

/

>

:)

600

/
V

Jsoc I
=

TA =

osc

,/

1111 I 1111

1.~~~ IEX~EJJ~~.

,/

MUX INPUT Trli

o

6.0

0.001-

0.01

0.1

1.0

~OUNTER INPUT FREQUENCY

0349-6

0349-7

DETAILED DESCRIPTION
Format of Signal to be Counted

TEST PROCEDURES
The ICM7208 is provided with three input terminals 7,23,
27 which may be used to accelerate testing. The least two
significant decade counters may be tested by applying an
input to the 'COUNTER INPUT' terminal 12. 'TEST POINT'
terminal 23 provides an input which bypasses the 2 least
significant decade counters and permits an injection of a
signal into the third decade counter. Similarly terminals 7
and 27 permit rapid counter advancing at two points further
along the string of decade counters.

The noise immunity of the COUNTER INPUT Terminal is
approximately % the supply voltage. Consequently, the input signal should be at least 50% of the supply in peak to
peak amplitude and preferably equal to the supply.
The optimum input signal is a 50% duty cycle square
wave equal in amplitude to the supply. However, as long as
the rate of change of voltage is not less than approximately
10- 4 V/fJ-s, at 50% of the power supply voltage, the input
waveshape can be sinusoidal, triangular, etc.
When driving the input of the ICM7208 from TTL, a 1k 5kO pull-up resistor to the positive supply must be used to
increase peak to peak input signal amplitude.

CONTROL INPUT DEFINITIONS
Input

Terminal

Voltage

1. DISPLAY

9

VDD
Vss

Display On
Display Off

2. STORE

11

VDD

Counter Information
Latched'
Counter Information
Transferring

Vss

Function

3. ENABLE

13

VDD
Vss

Input to Counter
Blocked
Normal Operation

4. RESET

14

VDD
Vss

Normal Operation
Counters Reset

10

"N (MHz)

Display Considerations
Any common cathode multiplexable LED display may be
used. However, if the peak digit current could exceed
150mA for any prolonged time, it is recommended that resistors be included in series with the segment outputs to
limit digit current to 150mA.
The ICM7208 is specified with 500fJ-A of possible digit
leakage current. With certain new LED displays that are extremely efficient at low currents, it may be necessary to include resistors between the cathode outputs and the positive supply to bleed off this leakage current.

Display Multiplex Rate
The ICM7208 has approximately 0.5fJ-s overlap between
output drive signals. Therefore, if the multiplex rate is very
fast, digit ghosting will occur. The ghosting determines the
upper limit for the multiplex frequency. At very low multiplex
rates flicker becomes visible.

COUNTER INPUT DEFINITION
The internal counters of the ICM7208 index on the negative edge of the input signal at terminal #12.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF All OTHER WARRANTIES, eXPRESS, IMPUED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been character/z8d but arB not ts$fed.

14-22

(l]D~OI!..

ICM7208

n
I:

...
to.)

b
-d

"

•

--;:::=-;"
,-G

BBBBBBB
7

5

I

i
,

¥S.ov

2

3

2

l

L

.

•5
I
VOO

DISPLAY

VOO

..::c.
0

~~

lOOk

INPUT
PROCESSiNG
OR
°VOO

N.O.

-

COMMON CATHODE

Voo

27

Vee

ICM720I 23

7

22

I

2'

t

20
It

"
,.

12
13

-:rRESET

2IJ

-

CD

25
2.

10

I
I

.J,.

0-

,

2Ir-

3

T

_I

o

'Ir17r-

'00k

t--

II

'5r--

Figure 4: Schematic Unit Counter

:J

O.OI.F

0349-8

due to the SPDT switch the ICM7208 contains an input
latch on chip.
The unit counter updates the display for each negative
transition of the input signal. The information on the display
will count, after reset, from 00 to 9,999,999 and then reset
to 0000000 and begin to count up again. To blank leading
zeros, actuate reset at the beginning of a count. Leading
zero blanking affects two digits at a time.
For battery operated systems the display may be
switched off to conserve power.

It is recommended that the display multiplex rate be within the range of 50Hz to 200Hz, which corresponds to 400Hz
to 1600Hz for the multiplex frequency input. For stand alone
systems, two inverters are provided so that a simple but
stable RC oscillator may be built using only 2 resistors and a
capacitor.
The multiplex oscillator is eight times the multiplex rate.
The frequency is given using the following formulii:
1
f=-2.2R xCx
Rs should always be ,;; 1MO and Rs = kR x where k is in the
range 2-10.
An external generator may be used to provide the multiplex frequency input. This signal, applied to terminal 19 (terminals 16 and 20 open circuit), should be approximately
equal to the supply voltage, and should be a square wave
for minimum of power dissipation.

Frequency Counter
The ICM7208 may be used as a frequency counter when
used with an external frequency reference and gating logic.
This can be achieved using the ICM7207 Oscillator Controller (Figure 5). The ICM7207 uses a crystal controlled oscillator to provide the store and reset pulses together with the
counting window. Figure 6 shows the recommended input
gating waveforms to the ICM7208. At the end of a counting
period (50% duty cycle) the counter input is inhibited. The
counter information is then transferred and stored in latches, and can be displayed. Immediately after this information
is stored, the counters are cleared and are ready to start a
new count when the counter input is enabled.
Using a 6.5536MHz quartz crystal and the ICM7207 driving the ICM7208, two ranges of counting may be obtained,
using either 0.01 sec or 0.1 sec counter enable windows.
Previous comments on leading zero blanking, etc., apply
as per the unit counter.
The ICM7207 provides the multiplex frequency reference
of 1.6kHz.

Unit Counter
Figure 4 shows the schematic of an extremely simple unit
counter that can be used for remote traffic counting, to
name one application. The power cell stack should consist
of 3 or 4 nickel cadmium rechargeable cells (nominal 3.6 or
4.8 volts). If 4 x 1.5 volt cells are used it is recommended
that a diode be placed in series with the stack to guarantee
that the supply voltage does not exceed 6 volts.
The input switch is shown to be a single pole double
throw switch (SPDT). A single pole single throw switch
(SPST) could also be used (with a pullup resistor), however,
anti-bounce circuitry must be included in series with the
counter input. In order to avoid contact bounce problems

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

14-23

!til ICM7208

...

Ii

g

•

-. fiJ B• B B B B
b

0

r---d

r;::::=t "

"dO

5

7

i

,

ia.ov
,..........
VOOo ~~
DISPLAY -:r

'k

,00k

~

l.:-,--;:;
f--

ICM
7207

8-4Op;

50k

~ J
~

MHz

~

b

0

22toF

OMII

T

50k

VD~-:t:

1~ RESET

r
l

~

i

INPUT
PROCESSING

1-

.

2J
27
2
283
25
4
24
5
8 ICM720S23
22
VDD 0- 7
_ 8
2'
20
9
'0

'9_

r-- "

'8_
17_
'8 _

to.

'2
'3
'4

COMMON CATHODE

VDD

VDD

'5_

47• F
VDD
CRYSTAL PARAMETERS
CL· 12p
CM' '6mpF
AS' 5511
CO' 301'

":"

GATING WiNDOW
~
SELECT

B

~

INPUT

0349-9

Figure 5: Frequency Counter
Note: For a 1 sec count window which allows all 7 digits to be used with a resolution of 1Hz, the ICM7207 can be replaced with the ICM7207A. Circuit details are
given on the 7207A data sheet.

1:1

I

COUNT ENABLE INPUT

,-

I--COUNTER INPUT-t - - - - - - - - O V
ENABLED (COUNTING WINDOW)
i'fOiiilNPUT

I Lr-::CSE"'G::-:M-::E~N=T:-:D:-:A=T:":'A­

lJ

REsET INPUT
COUNTER INPUT

-UPULSE WIDTH NOT
CRITICAL> 50.Sec.

LATCHED

-COUNTER RESET

EXTERNAL FREQUENCY TO BE MEASURED

0349-'0

Figure 6: Frequency Counter Input Waveforms

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vallJ8s have been characterized but are not tested.

14-24

ICM7208
Period Counter
8 shows a block schematic of the input waveform generator. The 1MHz frequency reference is generated by the
ICM7209 Clock Generator using an 8MHz oscillator frequency and internally dividing this frequency by 8. Alternatively, a 1MHz signal could be applied directly to COUNTER
INPUT. Waveforms are shown in Figure 7.

For this application, as opposed to the frequency counter,
the gating and the input signal to be measured are reversed
to the frequency counter. The input period is multiplied by
two to produce a single polarity signal (50% duty cycle)
equal to the input period, which is used to gate into the
counter the frequency reference (1 MHz in this case). Figure

COUNT ENABLE INPUT

~~TERNAL FREQUENCyl

STORE GENERATED BY THE POSITIVE
EDGE OF THE ENAiLi INPUT

STORE INPUT

RESET INI!UT

=U=RESET

COUNTER INPUT

INPUT IS = lMHz

0349-11

Figure 7: Period Counter Input Waveforms

INPUT

----------i

1---.....,------ iNAiLElNPUl

~---- RESET INPUT
L -_ _ _ _ _ _ _ _ _ _- - -

STORE INPUT

1 MHz
~--------- COUNTER INPUT

0349-12

Figure 8: Period Counter Input Generator

II
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

14-25

~

n~nlL

ICM7209

~ Timebase Generator
Ii
g

GENERAL DESCRIPTION

FEATURES

The Intersil ICM7209 is a versatile CMOS clock generator
capable of driving a number of 5 volt systems with a variety
of input requirements. When used to drive up to 5 TTL
gates, the typical rise and fall times are 10ns.
The ICM7209 consists of an oscillator, a buffered output
equal to the oscillator frequency and a second buffered output having an output frequency one-eighth that of the oscillator. The guaranteed maximum oscillator frequency is
10MHz. Connecting the DISABLE terminal to the negative
supply forces the 78 output into the '0' state and the output
1 into the '1' state.

•
•
•
•
•
•
•
•

High Frequency Operation - 10MHz Guaranteed
Requires Only A Quartz Crystal and Two CapaCitors
Bipolar, CMOS Compatibility
High Output Drive Capability - 5 x TTL Fanout With
10ns Rise and Fall Times
Low Power - 50mW at 10MHz
Choice of Two Output Frequencies - Osc., and Osc.
7 8 Frequencies
Disable Control for Both Outputs
Wide Industrial Temperature Range - 20·C to + 85·C

ORDERING INFORMATION
Part
Number

Temperature
Range

ICM72091JA

- 20·C to

ICM72091PA

- 20·C to

+ 85·C
+ 85·C

Package
8pinCERDIP
8 pin PLASTIC

• 4~VDD

afvss
TOP VIEW

1

osc OUT 0 - - - - - - - '

0350-2

5

3

DISABLE

0-------------------.....-1

p.-----o OUT 1
0350-1

Figure 1: Functional Diagram

Figure 2: Pin
Configuration
(Outline dwg PAl
Pin 1 is designated by either a
dot or a notch

'Zener Voltage is Typically 6.3 Volts

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

14-26

.D~DI!..

ICM7209

a....
N

ABSOLUTE MAXIMUM RATINGS
Supply Voltage .................................... 6V
Output Voltages ............... Vss-0.3V to VoO+0.3V
Input Voltages ................. Vss-0.3V to Voo+ 0.3V

Power Dissipation (25°C) ....................... 300mW
Storage Temperature ................ -55°C to + 125°C
Operating Temperature Range ......... - 20°C to + 85°C
Lead Temperature (Soldering, 1Osee) ............. 300°C

oG

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the davice. These are stress ratings only and functionsl
operation of the device at these or any other conditions abovB those indicated in the operationsl sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extendsd periods may affect davics reliability.

ELECTRICAL CHARACTERISTICS
(Voo-Vss=5V, test circuit, fosc= 10MHz, TA=25°C unless otherwise specified.)
Symbol

Parameter

Test Conditions

Typ

Max

Unit

11

20

mA

Either '1' or '0' state

±10

IJ-A

Output Low State

Either OUT 1 or OUT + 8
simulated 5 x TTL loads

0.4

VOH

Output High State

Either OUT 1 or OUT + 8
simulated 5 x TTL loads

tR

Output Rise Time (Note 3)

Either OUT 1 or OUT + 8
simulated 5 x TTL loads

10

tF

Output Fall Time (Note 3)

Either OUT 1 or OUT + 8
simulated 5 x TTL loads

10

100

Supply Current

Co

Disable Input Capacitance

IILK

Disable Input Leakage

VOL

fosc

GM

Min

Note 1
No Load

5

Minimum OSC Frequency
for + 8 Output

Note 2

Output + 8 duty cycle

Any operating frequency
Low state: High state

V

4.9

ns

2
MHz

Oscillator Transconductance

NOTES: 1.

4.0

pF

7:9
80

200

IJ-s

The power dissipation is a function of the oscillator frequency (1st ORDER EFFECT see curve) but is also effected to a small extent by the oscillator
tank components.

2. The

+" 8

circuitry uses a dynamic scheme. As with any dynamic system, information or data is stored on very small nodal capacitances instead of

latches (static systems) and there is a lower cutoff frequency of operation. DYnamic dividers are used in the
frequency performance and to decrease power consumption.
3 Rise and fall times are defined between the output levels of 0.5

ICM7209

to significantly improve high

and 2.4 volts.

CRYSTAL PARAMETERS:
CM-5mpF
RS -15ohm,
CO= 3pF

40012

Cl = IOpF
f- 10 MHz

OUT +8

II
0350-3

Figure 3: Test Circuit

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHAll BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU QF ALL OTHER WARRANTIES, EXPRESS, IMPlieD OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

•

NOTE: All typical value$ have besn characterized but IIf8 not tested.

14-27

g ICM7209

.D~DI!..

(101

....
:E TYPICAL PERFORMANCE CHARACTERISTICS

(Voo-Vss=5V)

S:!

SUPPLY CURRENT AS A FUNCTION
OF OSCILLATOR FREQUENCY

5

IS;--r--r-~--~rT--'

5r---~---rr--r~-'

If
1\
II

4

LQADSxTTL
LOADS
TA·25°C

3

fOSC-

I-

IOMHz

~2

lMHz
IOMHz
FREQUENCY

100MHz

~ 3~---b",--+---7+----4

g
iii

'- 20

4~--~----~---+~--4

t

/
o

w

~ 2~---++---~~-+----~

I
100kHz

SUPPLY VOLTAGE RANGE FOR
CORRECT OPERATION OF + 8
COUNTER AS A FUNCTION OF
OSCILLATOR FREQUENCY.

TYPICAL OUT 1 RISE AND FALL
TIMES

40

60

80

100

TIME Insl
0350-4

oL---~--~--~--~

10KHz 100kHz 1 MHz IOMHZ l00MHz
OSCILLATOR FREQUENCY

0350-5

0350-6

Rise and fall times of OUT .;- 8 are
similar to those of OUT 1.
store voltage levels instead of latches (which are used in
static dividers). The dynamic divider has advantages in high
speed operation and low power but suffers from limited low
frequency operation. This results in a window of operation
for any oscillator frequency (see TYPICAL PERFORMANCE
CHARACTERISTICS).

DETAILED DESCRIPTION
OSCILLATOR CONSIDERATIONS
The oscillator consists of a CMOS inverter with a non-linear resistor connected between the oscillator input and output to provide D.C. biasing. Using commercially obtainable
quartz crystals the oscillator will operate from low frequencies (10kHz) to 10MHz.
The oscillator circuit consumes about 500",A of current
using a 10MHz crystal with a 5 volt supply, and is designed
to operate with a high impedance tank circuit. It is therefore
necessary that the quartz crystal be specified with a load
capaCitance (Cd of 10pF instead of the standard 30pF. To
maximize the stability of the oscillator as a function of supply voltage and temperature, the motional capacitance of
the crystal should be low (5mpF or less). Using a fixed input
capacitor of 18pF and a variable capaCitor of nominal value
of 18pF on the output will result in oscillator stabilities of
typically 1ppm per volt change in supply voltage.

OUTPUT DRIVERS
The output drivers consist of CMOS inverters having active pullups and pulldowns. Thus the outputs can be used to
directly drive TTL gates, other CMOS gates operating with a
5 volt supply, or TTL compatible MOS gates. The guaranteed fanout is 5 TTL loads although typical fanout capability
is at least 10 TTL loads with slightly increased output rise
and fall times.

DEVICE POWER CONSUMPTION
At low frequencies the principal component of the power
consumption is the oscillator. At high oscillator frequencies
the major portion of the power is consumed by the output
drivers, thus by disabling the outputs (activating the DISABLE INPUn the device power consumption can be dramatically reduced.

THE +- 8 OUTPUT
A dynamic divider is used to divide the oscillator frequency by 8. Dynamic dividers use small nodal capaCitances to

INTEASIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

14-28

~DIL!

ICM7215

..

6-Digit LED Display
4-Function Stopwatch

N

ca

GENERAL DESCRIPTION

FEATURES

The ICM7215 is a fully integrated six digit LED stopwatch
circuit fabricated with Intersil's low threshold metal gate
CMOS process. The circuit interfaces directly with a six digit/seven segment common cathode LED display. The low
battery indicator can be connected to the decimal point anode or to a separate LED. The only components required
for a complete stopwatch are the display, three SPST
switches, a 3.2768MHz crystal, a trimming capacitor, three
AA batteries and an ON-OFF switch. For a two function
stopwatch, or to add a display off feature, one additional
slide switch is required. The circuit divides the oscillator frequency by 2'5 to obtain 100Hz, which is fed to the fractional
seconds, seconds and minutes counters, while an intermediate frequency is used to obtain the 1/6 duty cycle 1.07kHz
multiplex waveforms. The blanking logic provides leading
zero blanking for seconds and minutes independently of the
clock. The ICM7215 is packaged in a 24-lead plastic DIP.

• Four Functions: Start/Stop/Reset, Split, Taylor, Time

Out
• Six Digit Display: Ranges Up to 59 Minutes 59.99
Seconc18
• High LED Drive Current: 13mA Peak Per Segment at
16.7% Duty Cycle With 4.0 Volt Supply
• Requires Only Three Low Cost SPST Switches
Without Lo88 of Accuracy: Start/Stop, Reset, Display
Unlock
• Chip Enable Pin Turns Off Both Segment and Digit
Outputa; Can Be Used for Multiple Circuits Driving
One Display
• Low Battery Indicator
• Digit Blanking On Seconds and Minutes
• WIde Operating Range: 2.0 to 5.0 Volts
• 1kHz Multiplex Rate Prevents Flickering Display
• Can Be Used Easily In Four Different Single Function
Stopwatches or Two Two-Function Stopwatches:
Start/Stop/Reset With Time-out, Spilt With Taylor.
The Component Count for A Three- or Fou ....Functlon
Stopwatch Will Be Slightly Greater
• Retrofit to ICM7205 for Split and/or Taylor
Applications

ORDERING INFORMATION
Part Number

Temp. Range

Package

ICM72151PG

O"Cto +70"C

24-Pin PLASTIC DIP

ICM7215lD

-

DICE

6 OUTPUTS
OSCIN

LBIANODE
VDD

MULTIPLEX
GENERATOR

3

liege

LOW
FREQUENCY
DIVIDER

TEST
STARTISTOP
MODE
RESET
DISPLAY

,_.
100..
VSS

CHIP ENABLE

7 OUTPUTS
SI0~~_ _ _...

1 INPUT

Ml0
Ml
0352-2

ILOWL-. 1 OUTPUT

4 INPUTS ) - - - - - 1

~

Figure 2: Pin Configuration
(Outline dwg PG)

0352-1

Figure 1: Functional Diagram

II
INTERSIL'S SOlE AND EXCWSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATIED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN typ/cB/ vsluBs have been chBrscterinJd but IITtI not t8Bted.

14-29

:!CII ICM7215

...

a

ABSOLUTE MAXIMUM RATINGS
Storage Temperature ................ -65·C to + 150·C
Input Voltage ............... (Vss-0.3V) to (Voo+ 0.3V)
Output Voltage ............................ Vss to Voo

Supply Voltage (Voo to VSS) ...................... 5.5V
Power Dissipation (Note 1) ...................... 0.75W
Operating Temperature ................... O·C to + 70·C

NOTE: Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent demage to the device. These are stress ratings only and functional

opstaiion of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS:

(TA = + 25·C, stopwatch circuit, Voo= 4.0V, Vss = OV, unless otherwise

specified.)
Symbol

Parameter

Test Conditions

VSUPPlY

Supply Voltage (Voo - Vss)

-20·CS:TAS: + 70·C

100

Supply Current

Display off

ISEG

Segment Current
Peak
Average

5 segments lit
1.8 Volts across display

Min

Typ

2.0
0.6
9.0

Max

Unit

5.0

V

1.5
mA

13.2
2.2

Switch Actuation Current

All inputs except CHIP ENABLE

20

50

Switch Actuation Current

Chip enable

50

200

IOlK

Digit Leakage Current

VOIG=2.0V

50

ISlK

Segment Leakage Current

VSEG=2.0V

100

VLBI

Low Battery Indicator
Trigger Voltage

Isw

2.2

ILBI

LBI Output Current

fSTAB

Oscillator Stability

Voo = 2.0V to Voo = 5.0V

gm

Oscillator Transconductance

Voo=2.0V

Casel

Oscillator Input CapaCitance

Voo=2.0V, VLBI=1.6V

2.8

".A

V

2.0

mA

6

ppm

120

".S
30

pF

NOTE: 1. The output devices on the ICM7215 have very low impedence characteristics, especially the digit cathode drivers. If these devices are shorted to a low
impedance power supply, the current could be as high as 300mA.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characf8liz8d but 8f6 not I6st6d.

14·30

ICM7215

1:::
~ fila
aII,

7 _d

COMMON CATHODE DISPLAY

II

•5......
•
• • d •C
4 -c
2 D.P.Ml0

t
14

B. B. B. B. B.
Ml

S10

SI

10th.

t
13

t
12

t
11

t
18

VDD
QUARTZ CRYSTA
PARAMETERS

lOath.

t

17
VOO

~

.L

, = 3.2788MHz

RS = son
CM=23mpF
CO = 14pF
CL = llpF

SWITCH TAUTH TABLE
SWITCH MODE
POS.
(21)
MODE
STAAT/STOP/AESET
FLOAT
1
SPLIT
2
vDD
AYLOA
3
Vss
IME-OUT
4
FLOAT

DISPLAY
(19)
FLOAT
UNLOCK
UNLOCK
vss

N.O. NORMALLY OPEN
_ T O DISPLAY
0352-3

Figure 3: Stopwatch Circuit

TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT VS VOLTAGE

C

_0.1 DISPLAY OFF

1
iIII

TA" +25°C

L

0.8

I

B 0.4
~

~ 0.2

V

V

V

SEGMENT CURRENT VS SUPPLY VOLTAGE

.120

V

i 15
III:

V

'-10

i5

3.0

4.0

5.0

SUPPLY VOLTAGE

5

~

0

V
/

V

:I

~

L

VV

§

(,)

0.0
2.0

I
I
I
TA = +25°C
VF(LED) = 1.IV

./

V
2.0

3.0

4.0

5.0

SUPPLY VOLTAGE (V)
0352-4

0352-5

II
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AI/typical vslws have been chsrsct8rized but arB not f9Sted.

14-31

= ICM7215
...
I TYPICAL PERFORMANCE CHARACTERISTICS

.O~OIL

&II

OSC. STABILITY VS SUPPLY VOLTAGE

I

I

TA=+UoC
CaUT =22pF

/
/'

LOW BATTERY INDICATOR (LBI)
TRIGGER VOLTAGE VS TEMPERATURE

...j!'u

g
w
"~

~

/

2.7

"-

e2.5

/'

V

(Continued)

" "-

IIC

IV

2.3

'" "-

!2

~ 2.1

2.0

4.0
3.0
SUPPLY VOLTAGE (VI

!i

5.0

"

-10 0

10
30
TEMPERATURE (OC)

50

0352-6
0352-7

,-,,-,

",.,

G3 L:8

L"_'
RESET

L'L'
RESET

DISPLAY STOPS

CLOCK AND

DISPLAY COUNTING
PRESS

PRESS
START/STOP
ONCE

PRESS

STARONCTISETOP .. 27.65180

.. STARTISTOP
ONCE

0352-8

Figure 4: Start/Stop/Reset Mode

Turning on the stopwatch will bring up the reset state with
the fractional seconds displaying 00 and the other digits
blanked. This display always indicates that the stopwatch is
ready to go.

Each split time is measured from zero in the Taylor mode;
i.e., after stopping the watch, the counters reset momentarily and start counting the next interval. The time displayed is
that elapsed since the last activation of START/STOP. The
display is stationary after the first interval unless the display
unlock is used, by connecting the DISPLAY input to Vss, to
show the running clock. RESET can be used at any time.

The display can be turned off in any mode by connecting
the CHIP ENABLE input to Voo.

SPLIT MODE

DETAILED DESCRIPTION
FUNCTIONAL OPERATION

When the MODE input is connected to Voo the stopwatch is in the Split mode. (Figure 6).
The Split mode differs from the Taylor in that the lap
times are cumulative in the Split mode. The counters do not
reset or stop after the first start until RESET is activated.
Time displayed is the cumulative time elapsed since the first
start after reset. Display unlock can be used, by connecting
the DISPLAY input to Vss, to let the display 'catch up' with
the clock, and RESET can be used at any time.

START/STOP/RESET MODE
When the MODE input is floating and the DISPLAY input
is floating or connected to Voo the circuit is in the Start/
Stop/Reset mode. (Figure 4).
The Start/Stop/Reset mode can be used for single event
timing in a one-button stopwatch; an additional switch can
be used to provide an instant reset. To time another event,
the display must be reset before the start of the event. Seconds will be displayed after one second, minutes after one
minute. The range of the stopwatch is 59 minutes 59.99
seconds, and if an event exceeds one hour, the number of
hours must be remembered by the user. Leading zeroes are
not blanked after one hour.

TIME OUT MODE
When the MODE input is floating and the DISPLAY input
is tied to VSS, the stopwatch is in the Time-out mode. (Figure 7).
In the Time-out mode the clock and display alternately
start and stop with activations of the START/STOP switch.
RESET can be used at any time. The display unlock button
is bypassed in this mode.

TAYLOR OR SEQUENTIAL MODE
When the MODE input is connected to Vss, the stopwatch is in the Taylor or Sequential mode. (Figure 5).

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE ODNDlnoN OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typ/CsJ vaIuoshavobBer/

_but.,. not-'
14-32

ICM7215

,-,,-,

- ,-

IIJ GO
,_,,
_ _'L'

'_'LI
RESET

Ie' =,'J

CLOCK AND
DISPLAY COUNTING

DISPLAY STOPS
CLOCK RESETS
AND STARTS COUNTING

PRESS
START/STOP
ONCE

PRESS
START/STOP
ONCE

DISPLAY STOPS
.CLOCK RESETS
AND STARTS COUNTING
PRESS
DISPLAY
UNLOCK
ONCE

PRESS
START/STOP
ONCE

- - 20.47 MC.---_. - 1 2 . 3 5 M C . - - -___-

_ _ _ 42.78MC.. _ _ __

2'-: :8
CLOCK AND
DISPLAY COUNTING

DISPLAY STOPS
CLOCK RESETS
AND STARTS COUNTING

PRESS
START/STOP
ONCE

RESET

PRESS
RESET

0352-9

Figure 5: Taylor or Sequential Mode

,-, ,-,
RESET

_

Lie

'-'

'0

LAP 1
DISPLAY STOPS
CLOCK CONTINUES COUNTING

PRESS
START/STOP
ONCE

MC._·~.>----

PRESS
DISPLAY
UNLOCK
ONCE

12.35 MC._·~,_---- 42.78MC.----

ICC

""

L',-'

DISPLAY STOPS
CLOCK CONTINUES COUNTING
PRESS
START/STOP
ONCE

DISPLAY STOPS
CLOCK CONTINUES COUNTING

PRESS
START/STOP
ONCE

'-'",, '-' '-'

II]

''-'

CLOCK AND
DISPLAY COUNTING

20.47

-"- '-"-

STOP ' - _ _ _ _ _..J

CLOCK AND
DISPLAY COUNTING

PRESS
START/STOP
ONCE

':;':;OJ

E'L: '-: 7

I/,"i'-;

1/

'-''-'

RESET

PRESS
RESET

0352-10

Figure 6: Split Mode

lNTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical va/uss have been characterized but are not tested

14-33

II

: ICM7215

...

&'II

:Ii

g

,-,,-,

J'-; L/I

il:; 00
,_"
__'L'

ULI
RESET

LL'

CLOCK AND
DISPLAY COUNTING

PRESS
START/STOP
ONCE

I I

DISPLAY STOPS
CLOCK STOPS

PRESS
PRESS
START/STOP
START/STOP
ONCE
ONCE
20.47 - . - - T I M E O U T - - 22.32_.

Il;;

L"_'
CLOCK AND
DISPLAY COUNTING

PRESS
START/STOP
ONCE

DISPLAY STOPS
CLOCK STOPS

.

RESET
PRESS
RESET

0352-11

Figure 7: Time-Out Mode

APPLICATION NOTES
LOW BATTERY INDICATOR
DISPLAY

The on-chip low battery indicator is intended for use with
a small LED or the decimal pOints on a standard LED display. The output is the drain of a p-channel transistor twothirds the size of the segment drivers which will typically
source 2mA of current. The threshold voltage is approximately 2.5 volts at room temperature. Normal AA type batteries will provide many hours of accurate timekeeping after
the indicator comes on, however the wide voltage spread
between the LBI threshold voltage and minimum operating
voltage is required to guarantee low battery indication under
worst case conditions.

TO DISPLAY

TO DISPLAY

ICM7215

1----I--4~2415

L-_ _ _....;.;.......

TAYLOR

VDD

CHIP ENABLE
The CHIP ENABLE input is used to disable both segment
and digit drivers without affecting any of the functions of the
device. When the CHIP ENABLE input is floating or connected to Vss, the display is enabled, and when the tied to
Voo the display is turned off. One example of the many
possible uses of this feature is driving one display from two
ICM7215 devices, one in the split mode and the other in the
Taylor mode. The circuit, Figure 8, shows how the user can
obtain lap and cumulative readings of the same event.

TAYLOR SPLIT
ALL OTHER SWITCHES COMMON TO 80TH DEVICES
0352-12

FigureS

LATCHUP CONSIDERATIONS
Due to the inherent structure of junction isolated CMOS
devices, the circuit can be put in a latchup mode if large
currents are injected into device inputs or outputs. For this
reason special care should be taken in a system with multiple power supplies to prevent voltages being applied to inputs and/or outputs before power is applied to the 7215. If
only inputs are affected, latchup can also be prevented by
limiting the current into the input terminal to less than 1mAo

SWITCH CHARACTERISTICS
The ICM7215 is designed for use with SPST switches
throughout. On the DISPLAY and RESET inputs the characteristics of the switches are unimportant, since the circuit
responds to a logic level held for any length of time however short. Switch bounce on these inputs does not need to
be specified. The START/STOP input, however, responds
to an edge and so requires a switch with less than 15ms of
switch bounce. The bounce protection circuitry has been
specifically designed to let the circuit respond to the first
edge of the signal, so as to preserve the full accuracy of the
system.

OSCILLATOR DESIGN
The oscillator of the ICM7215 includes all components on
chip except the 3.2768MHz crystal and the trimming capacitor. The oscillator input capaCitance has a nominal value of
30pF, and the circuit is designed to work with a crystal with
a load capacitance of approximately 15pF. If ttle crystal has

INTERSIL'$ SOLE AND EXCLUSiVe WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STArED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typ/c81 values have been chsracterizBri but are not test8d.

14-34

ICM7215
ode should be tuned to 1066.667Hz, which is equivalent to
a period of 937.5 microseconds. Note that a frequency
counter cannot be connected directly to the oscillator because of possible loading.

characteristics as shown in the Typical Performance Characteristics, an 8 - 40pF trimming capacitor will be adequate
for a tuning tolerance of ± 30PPM on the crystal. If the crystal's static capacitance is significantly lower, a narrower
trimming range may be selected.
After deciding on a crystal and a nominal load capacitance, take the worst case values of Cin, Cout and Rs and
calculate the gm required by:
Co (Cin + Coutl] 2
gm=w2CinCoutRS [ 1+
Co C
.n out
Co = static capacitance
Rs = series resistance
Cin = input capacitance
Cout = output capacitance
w = 211" x crystal frequency
The resulting gm should be less than half the gm specified
for the device. If it is not, a lower value of crystal series
resistance and/or load capacitance should be specified.

TEST
The TEST input is used for high speed testing of the device. When the input is pulsed low, a latch is set which
speeds up counting by a factor of 32; each pulse on the
TEST input rapidly advances both minutes and seconds in a
parallel mode. To accurately rapid advance the signal applied to the TEST input must be free of switch bounce. The
circuit is taken out of the test mode by using either RESET
or START/STOP.

REPLACING THE ICM7205 WITH THE
ICM7215
The ICM7215 is designed to be compatible with circuits
using the ICM7205. If the 7205 is used only in the Split
mode no changes are required. If the 7205 is used in the
Taylor mode and the Split-Taylor input (pin 21) is left open,
a jumper from pin 21 to VSS must be added when converting to the 7215. A jumper may also be needed if the 7205 is
used with a Split/Taylor switch. Once the jumper has been
added the board can be used with either device.

OSCILLATOR TUNING
Tuning can be accomplished by using the 10th or 100th
seconds with the device reset. The frequency on the cath-

INTERSIL'S SOLE ANO EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

14-35

D~DIb

~ ICM7216A/B/C/D
_ a-Digit Multi-Function
Frequency Counter/Timer

=
...

~ GENERAL DESCRIPTION

FEATURES

Ii
S=!

ALL VERSIONS:

The ICM7216A and B are fully integrated Timer Counters
with LED display drivers. They combine a high frequency
oscillator, a decade timebase counter, an 8-decade data
counter and latches, a 7-segment decoder, digit multiplexers and 8 segment and 8 digit drivers which directly drive
large multiplexed LED displays. The counter inputs have a
maximum frequency of 10MHz in frequency and unit counter modes and 2M Hz in the other modes. Both inputs are
digital inputs. In many applications, amplification and level
shifting will be required to obtain proper digital signals for
these inputs.
The ICM7216A and B can function as a frequency counter, period counter, frequency ratio (fAffe) counter, time interval counter or as a totalizing counter. The counter uses
either a 1OMHz or 1MHz quartz crystal timebase. For period
and time interval, the 1OM Hz timebase gives a 0.1
resolution. In period average and time interval average, the resolution can be in the nanosecond range. In the frequency
mode, the user can select accumulation times of 0.01 sec,
0.1 sec, 1 sec and 10 sec. With a 10 sec accumulation time,
the frequency can be displayed to a resolution of 0.1 Hz in
the least significant digit. There is 0.2 seconds between
measurements in all ranges.
The ICM7216C and 0 function as frequency counters
only, as described above.
All versions of the ICM7216 incorporate leading zero
blanking. Frequency is displayed in kHz. In the ICM7216A
and B, time is displayed in ,..5. The display is multiplexed at
500Hz with a 12.2% duty cycle for each digit. The
ICM7216A and C are designed for common anode display
with typical peak segment currents of 25mA. The ICM7216B
and 0 are deSigned for common cathode displays with typical peak segment currents of 12mA. In the display off
mode, both digit and segment drivers are turned off, enabling the display to be used for other functions.

• Functions as a Frequency Counter (DC to 10MHz)
• Four Internal Gate Times: 0.01 Sec, 0.1 Sec,
1 Sec, 10 Sec in Frequency Counter Mode
• Directly Drives Digits and Segments of Large
Multiplexed LED Displays (Common Anode and
Common Cathode Versions)
• Single Nominal 5V Supply Required
• Highly Stable Oscillator, Uses lMHz or 10MHz
Crystal
• Internally Generated DeCimal POints, Interdlgit
Blanking, Leading Zero Blanking and Overflow
Indication
• Display Off Mode Turns Off Display and Puts Chip
Into Low Power Mode
• Hold and Reset Inputs for Additional Flexibility

,..S

ICM7216A AND ICM7216B
• Functions Also as a Period Counter, Unit Counter,
Frequency Ratio Counter or Time Interval Counter
.1 Cycle, 10 Cycles, 100 Cycles, 1000 Cycles In
Period, Frequency Ratio and Time Interval Modes
• Measures Period From 0.5,..s to 10s

ICM7216C AND ICM7216D
• Decimal Point and Leading Zero Blanking May Be
Externally Selected

ORDERING INFORMATION
Part Number

Temperature Range

+ 85°C
25°C to + 85°C
25°C to + 85°C
25°C to + 85°C
25°C to + 85°C
25°C to + 85°C

Package

ICM7216AIJI

- 25°C to

28 pin CERDIP

ICM7216BIPI

-

28 pin PLASTIC DIP

ICM7216BIJI

-

ICM7216CIJI

-

ICM7216DIPI

-

ICM7216DIJI

-

28 pin CERDIP
28 pin CERDIP
28 pin PLASTIC DIP
28 pin CERDIP

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND BHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
202815-003
NOTE: All typical values have been charsctflrizsd but are not t9sted.

14-36

ICM7216A/B/C/D

r--

EX T

~~

ose

osc

OUl1'UT

3

OSC.
SELECT

INPUT

DECOOER

-

-

-

r---

ose

I.....

I

·,0400.'ao

r'

---

REFERENCE
COUNTER
.. 103

I

fJ..~

I

.~GE ~

CONTROL

~

t

INFOT

I

(8)

r--"'!

LOGIC

I

DIGIT

OU11'UTS

'-----

~ .~GE"LECT

iimT

.h

DIGIT
DRIVERS

STORE AND

RESET LOGIC

RANGE

.MtUT

~

6

-

r---'-

. - - EN

--

MAIN
+101 COUNTER

r--

I-

eL

EXT

CONTROL
LOGIC

INPUT 8
(NOTE 11

D.P.

OVERFLOW

!' t, t, j' f4 t· f4 •

INPUT

INPUT 'A

D.P.

LOGIC

INPUT
( NOTE 2)

r-

-

DATA LATCHES AND
OUTPUTMUX

STORE/--

....
L--.

INPUT
CONTROL

r--Q0

'-----

DECODER
LOGIC

r+-

-

CL

LOGIC

--l-

4

I
r--

CONTROL
cONTROL
LOGIC - 0 INFOT

SEGMENT
DRIVER

,k;SEGMENT
OUl1'UTS
(I)

-

MAIN
FF

~

MEASUREM ENTIN

PliOli'Ii'm OUTPUT

-r--

(HOTE2)

r-FUNCTION
INPUT (NOTE 1I

FN

CONTROL
LOGIC

L

•

HOLD

INPUT

NOTES: 1) fUNCTION INPUT ANO INPUT 8 AVAILABLE ON leM 7216A/BONLY.

---

2) EXT D.P. INPUT AND ME ASUREMENT IN PROGRESS OUTPUT AVAILABLE ON

leM 7218C/O ONLY.

0353-1

Figure 1: Functional Diagram

II
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have be9fI characterized but are not tested.

14-37

.D~DR.

a ICM7216A/B/C/D

~

ABSOLUTE MAXIMUM RATINGS

=

tmd functIonsl opersllon of ths _
at these or any other conditions
sbove /hose _ted In ths operslionsl sections of ths spsc/fIcBtIons is not

i

implied. Exposure to absolute maximum rstlng conditions for axtended pariods may affect davies rslisbility.

;
...

:E

Maximum Supply Voltage (Voo-Vss) ............•.• 6.5V
Maximum Digit Output Current ...•..•............ 400mA
Maximum Segment Output Current ............•..• SOmA
Voltage On Any Input or
Output Terminal[1] ........ (Voo+ 0.3V) to (VSS-0.3V)
Maximum Power Dissipation at
700C .......................... 1.0W (ICM7216A & C)
0.5W (ICM72168 & D)
Operating Temperature Range ..••••••. - 25"C to + 85"C
Storage Temperature Range .....•.•.. -65"C to + 1500C
Lead Temperature (Soldering,10sec) ..•.•.•...•.. 3000C

NOTE: SIrr1sses sbove /hose listed under "Absolute Msximum Ratings"
may CBUSB psrmanent dsrnsge to ths davies. Thsse sre stress rstings only

Note: 1. The ICM7216 may be triggered into a destructive latchup mode Heither Input signals are applied before the power supply Is applied or H input or outputs
are forced to wltages exceeding VDD to Vas by more than 0.3 wits.

CONTROL INPUT

INPUT A

INPUT A

CONTROL IM'IIT

INPUTS

HOLD INPUT

IM'UTB

HOLD INPUT

FUNCTION INPUT

OSCOUTPUT

FUNCTION IM'UT

OSCOUTPUT

DECIMAL POINT OUTPUT

OSC IM'IIT

DIGIT 1 OUTPUT

SEG E OUTPUT
SEGGOUTPUT

EXT OSC INPUT

DIGIT 3 OUTPUT

OSC INPUl
EXT OSC INPUT

SEGAOUTPUT

OIGIT 4 OUTPUT

VA

DIGIT 2 OUTPUT
DIGIT 3 OUTPUT

DECIMAL POINT OUTPUT
SEGGOUTPUT

VA

SEG E OUTPUT

SEGDOUTPUT
SEGBOUTPUT

DIGIT 4 OUTPUT
DIGIT & OUTPUT

DIGIT & OUTPUT
DIGIT 8 OUTPUT

SEGAOUTPUT
SEG 0 OUTPUT

SEG C OUTPUT

VDO

SEOFOUTPUT

DIGIT. OUTPUT

DIGIT 7 OUTPUT
DIGIT 8 OUTPUT

SEGBOUTPUT

linn INPUT
DIGIT 7 OUTPUT
RANGE INPUT """,-_ _..;.r DIGIT. OUTPUT

iimflM'UT

SEGCOUTPUT

RANGE INPUT

SEGFOUTPUT

DIGIT 1 OUTPUT

VDO

0353-3

0353-2

INPUT A

c:ciNTROL INPUT

INPUT A

MEASUREMENT ill PiiiimiDS

HOLD INPUT

MEAIOREMlNf ill PIiiImIm

DECIMAL POINT OUTPUT

OSCOUTPUT

DIGIT 1 OUTPUT

HOLD INPUT
OSCOUTPUT

SEGGOUTPUT

OSCINPUT
EXT OSC INPUT

DIGIT 3 OUTPUT
DIGIT Z OUTPUT

OSCINPUT
EXT OSC INPUT

SEOAOUTPUT

DIGIT 1 OUTPUT

DIOIT 4 OUTPUT

VA

DIGIT Z OUTPUT

VA

SEGDOUTPUT
SEOBOUTPUT

DIGIT 3 OUTPUT
DIGIT 4 OUTPUT

SEGCOUTPUT

DIGIT & OUTPUT

DIOIT & OUTPUT
DIGIT. OUTPUT
DIOIT 7 OUTPUT

SEG E OUTPUT

SEOFOUTPUT

RElIT INPUT
EX. D.P. INPUT
RANGE INPUT

.....

..

_--.;

VDO
DIGIT 8 OUTPUT
DIOIT 7 OUTPUT
'ltOIT 8 OUTPUT

•
9

DECIMAL POINT OUTPUT
SEGGOUTPUT
SEOEOUTPUT
SEG A OUTPUT
SEODOUTPUT

Voo

DIGIT. OUTPUT
IiQlTINPUT

SE090UTPUT

Ell. D.P. INPUT
RANOEIM'UT

SEG C OUTPUT
SEGFOUTPUT

0353-5

0353-4

Figure 2: Pin Configurations

EVALUATION KIT
The ICM7226 Universal Counter System has all of the
features of the ICM7216 plus a number of additional features. The ICM7226 Evaluation Kit consists of the
ICM7226AIJL (Common Anode LED Display), a 10MHz

quartz crystal, eight 7 segment 0.3" LED's, P.C. board, resistors, capacitors, diodes, switches, socket: everything
needed to quickly assemble a functioning ICM7226 Universal Counter System.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLlGAT10N W1TH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ART1CLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANT1ES OF
MERCHANTABILITY AND FITNESS FOR A PARTlCULAR USE.
NOTE: AN /yp/cB/ _
lis"" /)Bon _
but.,. not ...10<1

14-38

ICM7216A/B/C/D
ELECTRICAL CHARACTERISTICS (ICM7216A/B)
(Voo = 5.0V, Vss = 0, T A = 25°C, unless otherwise specified.)

Symbol

Parameter

Test Conditions

MIn

Typ

Max

UnIts

2

5

mA

6.0

V

ICM7216A1B
100

Operating Supply Current

Display Off, Unused Inputs to Vss

Supply Voltage Range (Voo-Vss)

INPUT A,
INPUT B Frequency at f max

VSUPPLY
fA(max)

fB(max)

Maximum Frequency
INPUT A, Pin 28

4.75

Figure 3,
Function = Frequency, Ratio, Unit
Counter
Function = Period, Time Interval

10
2.5

MHz
MHz

Maximum Frequency
INPUT B, Pin 2

Figure 4

2.5

MHz

Minimum Separation
INPUT A to INPUT B
Time Interval Function

Figure 5

250

ns

fosc

Maximum Osc. Freq. and Ext.
Osc. Frequency

fosc

Minimum Ext. Osc. Freq.

gm

Oscillator Transconductance

Voo=4.75V, TA= +85°C

f mux

Multiplex Frequency

fosc= 10MHz

500

Hz

Time Between Measurements

fosc=10MHz

200

ms

VINL
VINH
RIN

10

Input Voltages:
Pins 2,13,25,27,28
Input Low Voltage
Input High Voltage
Input Resistance to Voo
Pins 13,24

MHz
100

2000

!L s

1.0
3.5
VIN=Voo-1.0V

IILK

Input Leakage
Pin 27,28,2

dVIN/dt

Input Range of Change

Supplies Well Bypassed

IOH
IOL

Digit Driver:
Pins 15,16,17,19,20,21,22,23
High Output Current
Low Output Current

VOUT=Voo-2.0V
VOUT= Vss + 1.0V

IOL
IOH

Segment Driver:
Pins 4,5,6,7,9,10,11,12
Low Output Current
High Output Current

VOUT= Vss + 1.5V
VOUT=Voo-2.5V

VINL
VINH
RIN

Multiplex Inputs:
Pins 1,3,14
Input Low Voltage
Input High Voltage
Input Resistance to Vss

100

kHz

V
V
kn

400
20

!LA

15

mV/!Ls

-140

-180
0.3

mA
mA

20

35
-100

mA
!LA

ICM7216A

0.8
VIN=Vss+1.0V

2.0
50

100

V
V
kn

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIeD OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been oharacterized but are not tssted.

14-39

IID~OIL

a ICM7216A/B/C/D

I

ELECTRICAL CHARACTERISTICS (ICM7216A/B)
(Voo= 5.0V, Vss =0, TA = 25°C, unless otherwise specified.) (Continued)

Symbol

Parameter

Test Conditions

Min

Typ

IOL
IOH

Digit Driver:
Pins 4,5,6,7,9,10,11,12
Low Output Current
High Output Current

VOUT= Vss + 1.3V
VOUT=Voo-2.5V

50

75
-100

IOH
ISLK

Segment Driver:
Pins 15,16,17,19,20,21,22,23
High Output Current
Leakage Current

VOUT=Voo-2.0V
VOUT=Voo-2.5V

-10

VINL
VINH
RIN

Multiplex Inputs:
Pins 1,3,14
Input Low Voltage
Input High Voltage
Input Resistance to Voo

Max

Units

ICM7216B

mA
p.A

mA
p.A

10

Voo-2.0
VIN=Voo-2.5V

Voo-0.8
100

360

V
V
kO

ELECTRICAL CHARACTERISTICS (ICM7216C/D)
(Voo= 5.0V, Vss=O, TA= 25°C, unless otherwise specified.)

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

2

5

mA

6.0

V

ICM7216C/D
Operating Supply Current

Display Off, Unused Inputs to VSS

VSUPPLY

Supply Voltage Range (Voo-VSS)

INPUT A
Frequency at Imax

IA(max)

Maximum Frequency
INPUT A, Pin 28

lose

Maximum Osc. Freq. and Ext.
Osc. Frequency

lose

Minimum Ext. Osc. Freq.

9m

Oscillator Transconductance

Voo=4.75V, TA= + 85°C

Imux

Multiplex Frequency

lose=10MHz

500

Hz

Time Between Measurements

lose=10MHz

200

ms

100

VINL
VINH

Input Voltages:
Pins 12,27,28
Input Low Voltage
Input High Voltage

RIN

Input Resistance to Voo
Pins 12,24

IILK

Input Leakage
Pin 27, Pin 28

IOL

Figure 3

4.75
10

MHz
MHz

10
100
2000

kHz
p.s

1.0
3.5
400

V
V

VIN=Voo-1.0V

100

kO

Output Current

VOL =+.4V

0.36

mA

IOH

Pin 2

VOH=Voo-0.8V

265

p.A

dVIN/dt

Input Rate
01 Change

Supplies Well Bypassed

20

15

p.A

mVlp.s

INTERSIL'S SOlE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE OCNDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES. EXPREss. IMPLIED OR STATUTORY. INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABIUTY AND FITNEBS FOR A PARTICULAR USE.
NOTE: AHtypksJVII1ws"".. been chsIocIorIzsdbut.,.nottostod.

14·40

IIID~DIL

ICM7216A/B/C/D

N

ELECTRICAL CHARACTERISTICS (ICM7216C/D)
(Voo = 5.0V ±5%, Vss = 0, TA = 25°C, unless otherwise specified.) (Continued)
Parameter

Test Conditions

Min

Typ

IOH
IOL

Digit Driver:
Pins 15,16,17,19,20,21,22,23
High Output Current
Low Output Current

VOUT=Voo-2.0V
VOUT=Vss+1.0V

-140

-180
0.3

mA
mA

IOL
IOH

Segment Driver:
Pins 3,4,5,8,8,9,10,11
Low Output Current
High Output Current

VOUT=VSS+ 1.5V
VOUT=Voo-2.5V

20

30
-100

mA

VINL
VINH
RIN

Multiplex Inputs:
Pins 1,13,14
Input Low Voltage
Input High Voltage
Input Resistance to Vss

VIN=+1.0V

IOL
IOH

Digit Driver:
Pins 3,4,5,6,8,9,10,11
Low Output Current
High Output Current

VOUT=+1.3V
VOUT=Voo-2.5V

IOH
ISLK

Segment Driver:
Pins 15,16,17,19,20,21,22,23
High Output Current
Leakage Current

VOUT=Voo-2.0V
VOUT=Voo-2.5V

VINL
VINH
RIN

Multiplex Inputs:
Pins 1,13,14
Input Low Voltage
Input High Voltage
Input Resistance to Voo

Symbol

Max

Units

ICM7216C

pA

0.8
100

V
V
kO

50

75
100

mA
p.A

10

15

2.0
50

ICM7216D

10

Voo-2.0
VIN = Voo -1.0V

Voo-0.8
100

360

mA
p.A

V
V
kO

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF BALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPREBS. IMPLIED OR STATLITORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNEBS FOR A PARTICULAR USE.
NOTE: All typIcsI vsJuss hsvs bssn cIJsrsctfIrIzfK but.,. not tfIBtsd.

14-41

a....
.

e

i

e ICM7216A/B/C/D

i

TYPICAL PERFORMANCE CHARACTERISTICS
ICM7216S & 0 TyplcallSEG va. VOO - VOUT.

ICM7216A & C TyplcallOIG va. VOO - VOUT.

4.5'; VOO'; 6.0V

4.5,; VOO'; 6.0V
3OOr-------r------.----~~

~~------~-------r-------n

~~------~-------+~----~

~~------4--------+~~--~

IO~------~---.~--~--------1

IOOr---------r---~~_+--------~

Voo -

Voo -

VOUT (VOLTS)

VOUT(VOLTS)

0353-7

0353-6

ICM7216B & 0 TyplcallOIGIT va. VOUT

ICM7216A & C TypicaiiSEG va. VOUT

~r-------~~--~~--~~~

200
-20 C

~~--~~4--------+------~

VOUT (VOL TSI

(a)
VOUT (VOLTSI

0353-8

200r--------r------~

__- - - - - .

~r--------r-------.------~
-~'C

VOUT (VOL TSI

(b)
0353-10
VOUT (VOLTSI

0353-9
INTERSll'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHAll BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHAll BE IN LIEU OF All OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have bsBn characterized but srs not tsstsd.

14-42

ICM7216A/B/C/D
This can be easily accomplished with the follOwing circuit:
(Figure 5).

COUNTED
/,/TRANSlTlONS

w~d'N

UV
INPUT A
O.5V

so ns MIN

I, -tf" 10nsec

0353-11

Figure 3: Waveform for Guaranteed Minimum
fA(max) Function = Frequency,
Frequency Ratio, Unit Counter.

r--- ~:::::::~INPUT A OR
INPUT B

•.•v--.,
O.5V

0353-13

I--~:S_

t

~~N.-::::t

I, = If" 10nIK

Device

Type

1
2

CD4049B Inverting Buffer
CD4070B Exclusive-OR
Figure 5: Priming Circuit,
Signal ABr.B High or Low.

0353-12

Figure 4: Waveform for Guaranteed Minimum
fB(max) and fA(max) for Function =
Period and Time Interval.

Following the priming procedure (when in single event or
1 cycle range input) the device is ready to measure one
(only) event.
When timing repetitive Signals, it is not necessary to
"prime" the ICM7216A1B as the first alternating Signal
states automatically prime the device. See Figure 5.
During any time interval measurement cycle, the
ICM7216A1B requires 200ms following B going low to update all internal logic. A new measurement cycle will not
take place until completion of this internal update time.

TIME INTERVAL MEASUREMENT
The ICM7216A1B can be used to accurately measure the
time interval between two events. With a 1OM Hz time-base
crystal, the time between the two events can be as long as
ten seconds. Accurate resolution in time interval measurement is 100ns.
The feature operates with Channel A going low at the
start of the event to be measured, followed by Channel B
going low at the end of the event.
When in the time interval mode and measuring a single
event, the ICM7216A1B must first be "primed" prior to measuring the event of interest. This is done by first generating
a negative going edge on Channel A followed by a negative
going edge on Channel B to start the "measurement interval." The inputs are then primed ready for the measurement. Positive going edges on A and B, before or after the
priming, will be needed to restore the original condition.

II
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AIIIyp/cBI vs/uss hBve be8n charsct9fiz9d but 8re not t6sted.

14·43

---_._------

ICM7216A/B/C/D
H-'

intefn.,stor.n!-_...,...
. . ,. __-+
~ t--+-___
eo30 TO 40ms

n!-__:-__-+

I

internll,..t

FUNCTK)N:

TIME INTERVAL

1-+-

- _ - - I _ - - P R I M I N G - -_ _----MEASUREMENT INTEAVAL------oi_'

INPUT A

INPUT 8

I

25OnIMIN.

~ ~~::~~!~ t (FIRST!

- - lI

_

MEASURED
INTERVAL
(LAST)

0353-14

NOTE: IF RANGE IS SET TO 1 EVENT, FIRST AND LAST MEASURED INTERVAL WILL COINCIDE.

Figure 6: Waveforms for Time Interval Measurement
(Others are similar, but without priming phase).

Voo

INPUT A

:;J;IOOpF

21
27
21
25

•

•

ZO
23

FR
TI.

1~~A

U.C.

O.F.
10
11
12

EXT

t---~------------------~~---------------------4-o~
D.
INPUT

22
21
20

D,
D,
D,

It
Ie

Os

17
18

15

..,

TYPICAL CAYST AL SPECS:

F • 10 MHz PARALLEl RESONANCE
CL=~

AS· <35f1

Voo

Os
Os

.01/1
.1/10

10lUl

11100
1011K

LED

OVERFLOW
INDICATOR

tV

BBBBBBBB
D.

0353-15

Figure 7: Test Circuit (7216A shown; others similar)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLlEO WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not Isst9d.

14-44

IIJU~UI!..

ICM7216A/B/C/D

n
iii

...
II)

......
....
06

,

•
"alb

.,-,e
f

d

ell

0

II

....n

2
3

ed.p.

CI

'i

0353-16

,

5
6

Overflow will be indicated on the decimal point output of digit 8.
A separate LED overflow indicator can be connected as follows:

B
9

0353-17

ICM7216A1C
ICM7216B/D

Cathode
DEC. PT.
Da

Anode
Da
DEC. PT.

Figure 8: Segment Identification and Display Font

CONTROL INPUT Functions

DETAILED DESCRIPTION
INPUTS A and B

. I?lsplay. Test - All segments are enabled continuously,
giving a display of all 8's with decimal points. The display
will be blanked if Blank Display is selected at the same time.
Display Off - To disable the drivers, it is necessary to
tie D4 to the CONTROL INPUT and have the HOLD input at
Vee. The chip will remain in this "Display Off" mode until
HOLD is switched back to Vss. While in the "Display Off"
mo~e, the segment and digit driver outputs are open, the
OSCillator continues to run with a typical supply current of
1.5mA with a 10MHz crystal, and no measurements are
made. In addition, inputs to the multiplexed inputs will have
no effect. A new measurement is initiated when the HOLD
input is switched to Vss. Segment and Digit Drive outputs
may thus be bussed to drive a common display (up to 6
circuits).
1MHz Select-The 1MHz select mode allows use of a
1MHz crystal with the same digit multiplex rate and time
between measurements as with a 10MHz crystal. The decimal point is also shifted one digit to the right in Period and
Time Interval, since the least significant digit will be in "'S
increments rather than 0.1
increments.
External OSCillator Enable -In this mode the EXTERNAL OSCILLATOR INPUT is used instead of the on-chip
oscillator for Timebase input and Main Counter input in period and time Interval modes. The on-chip oscillator will
continue to function when the external oscillator is selected.
The external oscillator input frequency must be greater than
100kHz or the chip will reset itself to enable the on-chip
oscillator. OSCillator INPUT (pin 25) must also be connected to EXT.OSC. input when using EXT.OSC. input.
External Decimal Point Enable - When external decimal point is enabled a decimal point will be displayed whenever the digit driver connected to EXTERNAL DECIMAL
POINT input is active. Leading Zero Blanking will be disabled for all digits following the decimal point (7216C/D
only).

INPUTS A and B are digital inputs with a typical switching
threshold of 2.0V at Vee=5.0V. For optimum performance
the peak-to-peak input signal should be at least 50% of the
supply voltage and centered about the switching voltage.
Wh?n these inputs are being driven from TIL logic, it is
desirable to use a pullup resistor. The circuit counts high to
low transitions at both inputs. (INPUT B is available only on
ICM7216A1B).
Note: The amplitude of the input should not exceed the supply, otherwise,
the circuit may be damaged.

Multiplexed Inputs
The FUNCTION, RANGE, CONTROL and EXTERNAL
DECIMAL POINT inputs are time multiplexed to select the
input function desired. This is achieved by connecting the
appropriate Digit driver output to the inputs. The input function, range and control inputs must be stable during the last
half of each digit output, (typically 125",s). The multiplex
inputs are active high for the common anode ICM7216A
and C and active low for the common cathode ICM7216B
and D.
Noise on the multiplex inputs can cause improper operation. This is particularly true when the unit counter mode of
operation is selected, since changes in voltage on the digit
drivers can be capacitively coupled through the LED diodes
to the m~ltiplex inputs. For maximum noise immunity, a
10k!} resistor should be placed in series with the multiplex
inputs as shown in the application circuits.
Table 1 shows the functions selected by each digit for
these inputs.

"'S

INTEASIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE T-HAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE

:~~~~~~~~~~A;~ ~~N~~L~~~V~ ~~~T~~~R ~~~~ LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
NOTE: All typical values hlIve been characteriztld but 818 not tested.

14-45

ICI

~
!!

=
...
&\I

;&
e,)_

1I0~OI!.

ICM7216A/B/C/D

Table 2: 7216A1B Input Routing

RANGE INPUT
The RANGE INPUT selects whether the measurement is
made for 1, 10, 100, 1000 counts of the reference counter.
In all functional modes except unit counter a change in the
RANGE INPUT will stop the measurement in progress without updating the display and then initiate a new measurement. This prevents an erroneous first reading after the
RANGE INPUT is changed.
Table 1: Multiplexed Inpl!t Functions
Function
FUNCTION INPUT
Pin 3
(ICM7216A & B
Only)

Digit

Frequency
Period

Dl
De

Frequency Ratio

D2

Time Interval
Unit Counter
Oscillator
Frequency

D5
D4

RANGE INPUT
Pin 14

.01 seclt Cycle
.1 seclt 0 Cycles
1 seclt 00 Cycles
10 seclt K Cycles

Dl
D2
D3
D4

CONTROL INPUT
Pin 1

Blank Display
Display Test
1 MHz Select
External Oscillator
Enable
External Decimal
Point Enable

D4and Hold
D8
D2
Dl

EXT. D.P. INPUT
Pin 13, ICM7216C
& DOnly

Description

Reference
Counter

Main Counter

Frequency (fAl

Input A

100 Hz (OSCillator
+ 105 or 104)

Period (tA)

Oscillator

Input A

Ratio (fAlte)

Input A

Input B

Time Interval
(A-B)

Osce(Time
Interval FF)

Time Interval FF

Unit Counter
(Count A)

Input A

Not Applicable

Osc. Freq.
(fosel

Oscillator

100 Hz (OSCillator
+ 105 or 104)

EXTernal DECimal Point INput

D3

When the external decimal point is selected this input is
active. Any of the digits, except De, can be connected to
this point. D8 should not be used since it will override the
overflow output and leading zeros will remain unblanked after the decimal point. This input is available on the
ICM7216C and D only.
HOLD Input - Except in the unit counter mode, when
the H0'f Input is at Voo, any measurement in progress
(before TORE goes low) is stopped, the main counter is
reset and the chip is held ready to initiate a new measurement as soon as HOLD goes low. The latches which hold
the main counter data are not updated, so the last complete
measurement is displayed. In unit counter mode when
HOLD input is at Voo, the counter is not stopped or reset,
but the display is frozen at that instantaneous value. When
HOLD goes low the count continues from the new value in
the counter.
RESET Input - The RESET input resets the main counter, stops any measurement in progress, and enables the
main counter latches, resulting in an all zero output. A capacitor to ground will prevent any hang-ups on power-up.

D3

Decimal point is output for same
digit that is connected to
this input

FUNCTION INPUT
The six functions that can be selected are: Frequency,
Period, Time Interval, Unit Counter, Frequency Ratio
and Oscillator Frequency. This input is available on the
ICM7216A and B only.
These functions select which signal is counted into the
Main Counter and which signal is counted by the Reference
Counter, as shown in Table 2. In all cases, only 1 - 0 transitions are counted or timed. In time Interval, a flip-flop is
toggled first by a 1 - 0 transition of INPUT A and then by a
1 - 0 transition of INPUT B. The oscillator is gated into the
Main Counter from the time INPUT A toggles the flip-flop
until INPUT B toggles it. In unit counter mode, the main
counter contents are continuously displayed. A change in
the FUNCTION INPUT will stop the measurement in progress without updating the display and then initiate a new
measurement. This prevents an erroneous first reading after
the FUNCTION INPUT is changed.

DISPLAY CONSIDERATIONS
The display is multiplexed at a 500Hz rate with a digit time
of 244 ""S. An interdigit blanking time of 6 ""S is used to
prevent ghosting between digits. The decimal point and
leading zero blanking assume right hand decimal point displays, and zeros following the decimal point will not be
blanked. Also, the leading zero blanking will be disabled
when the Main Counter overflows. Overflow is indicated by
the decimal point on digit 7 turning on.
The ICM7216A and C are designed to drive common anode LED displays at peak current of 25mA/segment, using
displays with VF=I.8V at 25mA. The average DC current
will be over 3mA under these conditions. The ICM7216B
and D are designed to drive common cathode displays at
peak current of 15mA/segment using displays with
VF = 1.8V at 15mA. Resistors can be added in series with
the segment drivers to limit the display current in very efficient displays, if required. The Typical Performance Characteristics curves show the digit and segment currents as a
function of output voltage.

IN"TERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN typIcs/ vsJuss hsvs b88n charactetizBd but IU8 not tested.

14-46

ICM7216A/B/C/D
To get additional brightness out of the displays, Voo may
be increased up to 6.0V. However, care should be taken to
see that maximum power and current ratings are not exceeded.
The segment and digit outputs in ICM7216's are not directly compatible with either TTL or CMOS logic when driving LEOs. Therefore, level shifting with discrete transistors
may be required to use these outputs as logic signals.

1

ACCURACY
In a Universal Counter crystal drift and quantization effects cause errors. In frequency, period and time Interval
modes, a signal derived from the oscillator is used in either
the Reference Counter or Main Counter. Therefore, in these
modes an error in the oscillator frequency will cause an
identical error in the measurement. For instance, an oscillator temperature coefficient of 20ppml'C will cause a measurement error of 20ppml'C.
In addition, there is a quantization error inherent in any
digital measurement of ± 1 count. Clearly this error is reduced by displaying more digits. In the frequency mode the
maximum accuracy is obtained with high frequency inputs
and in period mode maximum accuracy is obtained with low
frequency inputs. As can be seen in Figure 9, the least accuracy will be obtained at 10kHz. In time interval measurements there can be an error of 1 count per interval. As a
result there is the same inherent accuracy in all ranges as
shown in Figure 10. In frequency ratio measurement can
be more accurately obtained by averaging over more cycles
of INPUT B as shown in Figure 11.

1
"

!"r".

MAXIMUM TIME INTERVAL
FOR 103 IVERi ALS

I

~V

MAXiMUM TIME
INTERVAL FOR

102 I~ERVALS

""
.-/

~~\~~~T~I~~~~:ERVAL _
I

I

10

102

I
103

104

106

TIME INTERVAL (,us)

"

10S

107

lOS

0353-19

Figure 10: Maximum Accuracy of Time Interval
Measurement Due to Limitations of
Quantization Errors

0353-20

Figure 11: Maximum Accuracy for Frequency
Ratio Measurement Due to Limitation of
Quantization Errors

FREQUENCY (Hz)

0353-18

Figure 9: Maximum Accuracy of Frequency and
Period Measurements Due to Limitations of
Quantization Errors

•

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical vs/ues hSV8 been chsracterized but ate not tested.

14-47

.D~DI.L

~ ICM7216A/B/C/D

•...
G

DISPLAY DISPLAY

101e1l

(\I

BLANK

TEST

~
ENABLE

....

Ii

2

FREOUENCY

PERIOD
FREQUENCY RATIO

D.
10kn 03

D,

0-

EXT

2' I-------------------------------~--------------t-~~~UT
23
D.P.
G
.eM 22
101e1l
8 72168 21
20
A
10
D
18
11
Voo
17
'2
13
SEGMENT DRIVERS \
15

" I--+--+-------------------------~==========~--~

I.

I

"

I

DIGIT

DRIVERS

I

I. COMMON CATHOOELED DISPLAY I

BBBBBBBB

D8

~~~RFLOW

L-__~--------~--------~------~~------~--------~------~--------~--------~~~INDICATOR
0353-21

Figure 12: 10MHz Universal Counter

CIRCUIT APPLICATIONS

The ICM7216A or B can be used as a minimum component complete Universal Counter as shown in Figure 12.
This circuit can use input frequencies up to 10MHz at INPUT A and 2MHz at INPUT B. If the signal at INPUT A has a
very low duty cycle it may be necessary to use a 74LS121
monostable multivibrator or similar circuit to stretch the input pulse width to be able to guarantee that it is at least
50ns in duration.

The ICM7216 has been designed for use in a wide range
of Universal and Frequency counters. In many cases, prescalers will be required to reduce the input frequencies to
under 10MHz. Because INPUT A and INPUT B are digital
inputs, additional circuitry is often required for input buffering, amplification, hysterisis, and level shifting to obtain a
good digital signal.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHAll BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typ;cal values have been chsracter/zBd but sre not tested

14-48

ICM7216A/B/C/D

EXT
OSC
EN

OI"LAY OI"LAY
OFF
TEST

'OOpF~
0,
d.

1=::;;::::::::::::::~::~::if~J:~

____________'~~!'~·,~____-!~~
'NPUT

10k!!

COMMON ANOOE LEO O'''LAY

I

BBBBBBBB
D,

0353-22

Figure 13: 40MHz Frequency Counter
there is no external decimal point control with the
ICM7216A/B, the decimal point may be controlled externally with additional drivers as shown in Figure 15. Alternatively, if separate anodes are available for the decimal pOints,
they can be wired up to the adjacent digit anodes. Note that
there can be one zero to the left of the decimal point since
the internal leading zero blanking cannot be changed.. In
Figure 16 additional logic has been added to count the input
directly in period mode for maximum accuracy. In Figures
14 through 16, INPUT A comes from Qc of the prescaler
rather than QD to obtain an input duty cycle of 40%.

To measure frequencies up to 40MHz the circuit of Figure
13 can be used. To obtain the correct measured value, it is
necessary to divide the oscillator frequency by four as well
as the input frequency. In doing this the time between measurements is also lengthened to 800ms and the display mUltiplex rate is decreased to 125Hz.
If the input frequency is prescaled by ten, then the oscillator can remain at 10 or 1MHz, but the decimal point must be
moved one digit to the right. Figure 14 shows a frequency
counter with a + 10 prescaler and an ICM7216C. Since

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PROOUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXFRESS, IMPUED OR STATUTORY, INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABIUTV AND FITNESS FOR A PARTICULAR USE.

NOTE; AD typical values have bssn DharsctetiZsd but IUB not t6stsd.

14-49

II

e.

()

ICM7216A/B/C/D

iD
C
co

......
(II

VDD

:E

EXT,
DECIMAL

PT, ENABLE

!i

EXT.

esc,

BLANK DISPLAY

DISPLAV

TEST

38pF eTVP,)

'----------..
D,

1N91
(,)

10

Z

w
:::>
0
w

...a:

t_,

fa (mucl PERIOD.
TIME INTERVAL MODES

fA

--

T... - 25"C

Voo -

Vss (VOLTS)

0353-26

IA(max), la(max) as a Function 01 VOD

Figure 17: Typical Operating Characteristics

D
INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OA STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

14-53

~

&\I

ICM7217/ICM7227

Iii 4-Digit LED Display Programmable
!i
Up/Down Counter
.....
....
~

....
::Ii
!i

GENERAL DESCRIPTION

FEATURES

The ICM7217 and ICM7227 are four digit, presettable up/
down counters, each with an onboard presettable register
continuously compared to the counter. The ICM7217 versions are intended for use in hardwired applications where
thumbwheel switches are used for loading data, and simple
SPDT switches are used for chip control. The ICM7227 versions are for use in processor-based systems, where presetting and control functions are performed under processor control.
These circuits provide multiplexed 7 segment LED display
outputs, with common anode or common cathode configurations available. Digit and segment drivers are provided to
directly drive displays of up to 0.8" character height (common anode) at a 25% duty cycle. The frequency of the onboard multiplex oscillator may be controlled with a single
capacitor, or the oscillator may be allowed to free run. Leading zeros can be blanked. The data appearing at the 7 segment and BCD outputs is latched; the content of the counter is transferred into the latches under external control by
means of the Store pin.
The ICM721717227 (common anode) and ICM7217A1
7227A (common cathode) versions are decade counters,
providing a maximum count of 9999, while the ICM7217B,
7227B (common anode) and ICM7217C/7227C (common
cathode) are inte.nded for timing purposes, providing a maximum count of 5959.

• Four Decade, Presettable Up-Down Counter With
Parallel Zero Detect
• Settable Register With Contents Continuously
Compared to Counter
• Directly Drives Multiplexed 7 Segment Common
Anode or Common Cathode LED Displays
• On-Board Multiplex Scan Oscillator
• Schmitt Trigger On Count Input
• TTL Compatible BCD I/O Port, Carry/Borrow, Equal,
and Zero Outputs
• Display Blank Control for Lower Power Operation;
Quiescent Power Dissipation  60/LA. A 10kO pull-up resistor
to Voo on the EQUAL or ZERO outputs is recommended for

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typical values hsvs bssn chsnJcterIzsd but Bf8 not IesIBd.

14-60

ICM7217/ICM7227
~L-____
--~~~------~'~
______
---,~r-------~'~____--------~10~.TYP. FREE-RUNNING t---- FR:~~~!!:;'Q---t

SCAN

n

INTERNAL OSC.
OUTPUT
---I

INTERNAL

EXTERNAL

n

a...-..~

[~
D_2~

(BCD AND
SEGMENT
ENABLE)

n

~~

.-----J

_________________________

~~------------------------------------------~

______________________________
r;;~~----------1k-!
:NTERDIGIT BLANK

~~~

(COMMON
ANODE)

DIGiT
STROBES

n

~~ L . . . . . . . - -

~r=

~~------------------------------------------~

L
0354-13

Figure 5: Multiplex Timing

Description

Min Typ Max Unit

UP/DOWN setup time (min)
UP/DOWN hold time (min)
COUNT pulse high (min)
COUNT pulse low (min)
COUNT to CARRY /
BORROW delay
CARRY/BORROW pulse
width
COUNT to EQUAL delay
COUNT to ZERO delay

300
0
100 250
100 250
750

Symbol
tucs
tUCh
tCUh
leUI
tCB
tBw
tCEI
tCZI

ns

100
500
300

0354-14

Figure 6: ICM7217/27 COUNT and Output Timing

Multiplex SCAN Oscillator

viding inter-digit blanking which prevents ghosting. The digits are scanned from MSD (04) to LSD (01). See Figure 4
for the display digit multiplex timing.
Table 1: ICM7217 Multiplexed Rate Control

The on-board multiplex scan oscillator has a nominal
free-running frequency of 2.5kHz, This may be reduced by
the addition of a single capacitor between the SCAN pin
and the positive supply (ICM7217 only). Capacitor values
and corresponding nominal oscillator frequencies, digit repetition rates, and loading times are shown in Table 1 below.
The internal oscillator output has a duty cycle of approximately 25:1, providing a short pulse occurring at the oscillator frequency. This pulse clocks the four-state counter
which provides the four multiplex phases. The short pulse
width is used to delay the digit driver outputs, thereby pro-

Scan
Capacitor

Nominal
Oscillator
Frequency

Digit
Repetition
Rate

Scan Cycle
Time
(4 digits)

None

2.5kHz

625Hz

1.6ms

20pF

1.25kHz

300Hz

3.2ms

90pF

600Hz

150Hz

8ms

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHAll BE EXCLUSIVE AND SHAll BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tesl8d.

14-61

II

= ICM7217/ICM7227

...
.......
...
...
&\I

a
a
&\I

ov
0354-16

Figure 7: Brightness Control Circuits
During load counter and load register operations, the
multiplex oscillator is disconnected from the SCAN input
and is allowed to free-run. In all other conditions, the oscillator may be directly overdriven to about 20kHz, however the
internal oscillator signal will be of the same duly cycle and
phase as the overdriving signal, and the digits are blanked
during the time the external signal is at a positive level. To
insure proper leading zero blanking, the interdigit blanking
time should not be less than about 2,...s. Overdriving the
oscillator at less than 200Hz may cause display flickering.
The display brightness may be altered by varying the duty
cycle. Figure 7 shows several variable-duly-cycle oscillators
suitable for brightness control at the ICM7217 SCAN input
The inverters should be CMOS CD4000 series and the diodes may be any inexpensive device such as IN914.

BCD 1/0 Pins
The BCD 1/0 port provides a means of transferring data
to and from the device. The ICM7217 versions can multiplex
data into the counter or register via thumbwheel switches,
depending on inputs to the LOAD COUNTER or LOAD
REGISTER pins; (see below). When functioning as outputs,
the BCD 1/0 pins will drive one standard TTL load. Common anode versions have internal pull down resistors and
common cathode versions have internal pull up resistors on
the four BCD 1/0 lines when used as inputs.

LOADing the COUNTER and REGISTER
The BCD 1/0 pins, the LOAD COUNTER (LC), and LOAD
REGISTER (LR) pins combine to provide presetting and
compare functions. LC and LR are three-level inputs, being
self-biased at approximately ~'2VDD for normal operation.
With both LC and LR open, the BCD 1/0 pins provide a
multiplexed BCD output of the latch contents, scanned from
MSD to LSD by the display multiplex.
When either the LOAD COUNTER (Pin 12) or LOAD
REGISTER (Pin 11) is taken high, the drivers are turned off
and the BCD pins become high-impedance inputs. When LC
is connected to VDD, the count input is inhibited and the
levels at the BCD pins are multiplexed into the counter.
When LR is connected to VDD, the levels at the BCD pins
are multiplexed into the register without disturbing the counter. When both are connected to VDD, the count is inhibited
and both register and counter will be loaded.
The LOAD COUNTER and LOAD REGISTER inputs are
edge-triggered, and pulsing them high for 500ns at room
temperature will initiate a full sequence of data entry cycle
operations (see Figure 7). When the circuit recognizes that
either or both of the LC or LR pins input is high, the multiplex oscillator and counter are reset (to 04). The internal
oscillator is then disconnected from the SCAN pin and the

Counting Control
As shown in Figure 6, the counter is incremented by the
rising edge of the COUNT INPUT Signal when UPIDOWN is
high. It is decremented when UPIDOWN is low. A Schmitt
trigger on the COUNT INPUT provides hysteresis to prevent
double triggering on slow rising edges and permits operation in noisy environments. The COUNT INPUT is inhibited
during reset and load counter operations.
The STORE pin controls the internal latches and consequently the signals appearing at the 7-segment and BCD
outputs. Bringing the STORE pin low transfers the contents
of the counter into the latches.
The counter is asynchronously reset to 0000 by bringing
the RESET pin low. The circuit performs the reset operation
by forcing the BCD input lines to zero, and "presetting" all
four decades of counter in parallel. This affects register
loading; if LOAD REGISTER is activated when the RESET
in~u~~ low, the register will also be set to zero. The
S O , RESET and UPIDOWN pins are provided with pullup resistors of approximately 75kO.

INlERSlL'S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRAN11ES, EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPUED WARRANnes OF
IAERCHANTABILITY AND FITNESS FOR A PARnCULAR USE.

NOTE: All typ/cBI_ have been chaIacIsIizsd but.,.

not_

14-62

ICM7217/ICM7227
The ZERO output is not valid during a load counter operation.
The RESET input may be susceptible to noise if its input
rise time (coming out of reset) is greater than about 500,",s.
This will present no problems when this input is driven by
active devices (Le., TIL or CMOS logic) but in hardwired
systems adding virtually any capacitance to the RESET input can cause trouble. A simple circuit which provides a
reliable power-up reset and a fast rise time on the RESET
input is shown below.

preset circuitry is enabled. The oscillator starts and runs
with a frequency determined by its internal capacitor, (which
may vary from chip to chip). When the chip finishes a full 4
digit multiplex cycle (loading each digit from D4 to D3 to D2
to D1 in turn), it again samples the LOAD REGISTER and
LOAD COUNTER inputs. If either or both is still high, it repeats the load cycle, if both are floating or low, the oscillator
is reconnected to the SCAN pin and the chip returns to
normal operation. Total load time is digit "on" time multiplied by 4. If the Digit outputs are used to strobe the BCD
data into the BCD I/O inputs, the input will be automatically
synchronized to the appropriate digit (Figure 8). Input data
must be valid at the trailing edge of the digit output.
When LR is connected to GROUND, the oscillator is inhibited, the BCD I/O pins go to the high impedance state,
and the segment and digit drivers are turned off. This allows
the display to be used for other purposes and minimizes
power consumption. In this display off condition, the circuit
will continue to count, and the CARRY/BORROW, EQUAL,
ZERO, UP/DOWN, RESET and STORE functions operate
as normal. When LC is connected to ground, the BCD I/O
pins are forced to the high impedance state without disturbing the counter or register. See "Control Input Definitions"
(Table 2) for a list of the pins that function as three-state
self-biased inputs and their respective operations.
Note that the ICM7217 and 7217B have been designed to
drive common anode displays. The BCD inputs are high
true, as are the BCD outputs.
The ICM7217A and the 7217C are used to drive common
cathode displays, and the BCD inputs are low true. BCD
outputs are high true.

--~

____

~

__

~

________

v~

N.O.'
iiiiii INPUT
ICM7217
IIKn

------------+---------vss
0354-17

Figure 8
When using the circuit as a programmable divider ("'" by n
with equal outputs) a short time delay (about 1,",s) is needed
from the EQUAL output to the RESET input to establish a
pulse of adequate duration. (See Figure 9)

Notes on Thumbwheel Switches &
Multiplexing

...

The thumbwheel switches used with these circuits (both
common anode and common cathode) are TRUE BCD coded; i.e. all switches open corresponds to 0000. Since the
thumbwheel switches are connected in parallel, diodes
must be provided to prevent crosstalk between digits. See
Figure 8. In order to maintain reasonable noise margins,
these diodes should be specified with low forward voltage
drops (IN914). Similarly, if the BCD outputs are to be used,
resistors should be inserted in the Digit lines to avoid loading problems.

r~

1

4
''''

~~~-----------------~.~
0354-16

Figure 9
When the Circuit is configured to reload the counter or
register with a new value from the BCD lines (upon reaching
EQUAL), loading time will be digit "on" time multiplied by
four. If this load time is longer than one period of the input
count, a count can be lost. Since the circuit will retain data
in the register, the register need only be updated when a
new value is to be entered. RESET will not clear the register.

Output and Input Restrictions
The CARRY/BORROW output is not valid during load
counter and reset operations.
The EQUAL output is not valid during load counter or load
register operations.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typioa/1I8lues have bB9n char8ct9fized but are not tested

14-63

~

...
:I

ICM7217/ICM7227

~

()

....

::::
...
~

~VDD

LOAD COUNTER
(OR LOAD REGISTER)

-GND

:I

2

04

03

02

01
INTERNAL
OPERATING
MODE

INPUT

·COUNT INHIBITED IF
LOAO COUNTER

OUTPUT _ _ _ _ _..

BCD 1/0

-r -

- -

-

• " HIGH IMPEDANCE
THREE-STATE W PULLDOWN

0354-19

Figure 10: ICM7217 BCD I/O and Loading Timing

TO D4 STROBE

TO D1 STROBE

TO 04 STROBE

TO D1 STROBe

IN914 OR
EQUIVALENT

,,~8_--'-1___/

I
TO BCD INPUTS OF 7217, 7217B

TO BCD INPUTS OF 7217A, 7217e

0354-20
Note: If the BCD pins are to be used for outputs a 10kO resistor should be placed in series with each digit line to avoid loading problems through the switches.

Figure 11: Thumbwheel Switch/Diode Connections

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

14-64

rIlD~DI!..

ICM7217/ICM7227

g
....

.......

I\)

-tCWi-~'C~

cwo

INPUT

-'

iii'

INPUT

1--'D1W-

r--'SC.-

{~

"-

i-IsCh

ST

•

I

"

....
n

"-

6

REG'STER WRITE CYCLE (SCI, SC2

J'Al'II'l' jm

sc.

=" 1)

(COUNTER WRITE CYCLE IS SIMILAR: SCI, SC2

~ ~.

=1,0)

IIDh

~

I BCD I/O

..

....

SC1, SC2 LATCHES RESET

K1I<\.w, III1W

se1

{

I:

i

mm ~

S~

DATA OUTPUT CYCLE (SCI, SC2

SC2

~ ~

-

J.

BeDIJO
OUTPUT

'TD.~

I--

-

=0, 1)

-

I--'TOI

=DON'T CARE

.: CONTROL WORD INPUTS

0354-21

Figure 12: ICM7227 1/0 Timing (see Table 4)
The sequence of digits will be D4-D3-D2-D1, i.e. when
outputting, the data from D4 will be valid during the first DT
pulse, then D3 will be valid during the second pulse, etc.
When presetting, the data for D4 must be valid at the positive-going transition (trailing edge) of the first DT pulse, the
data for D3 must be valid during the second DT pulse, etc.
At the end of a data transfer operation, on the positive
going transition of the fourth DT pulse, the SC1 and SC2
control latches will automatically reset, terminating the data
transfer and reconnecting the multiplex counter clock to the
oscillator. In the ICM7227 versions, the multiplex oscillator
is always free-running, except during a data transfer operation when it is disabled.
Figure 12 shows the timing of data transfers initiated with
a 11 select code (writing into the register) and a 01 select
code (reading out of the output latches). Typical times during which data must be valid at the control word and BCD
I/O ports are indicated in Table 4.

CONTROL OF ICM7227 VERSIONS
The ICM7227 series has been designed to permit microprocessor control of the inputs. BCD inputs and outputs are
active high.
In these versions, the STORE, UP/DOWN, SC1 and SC2
(Select Code bits 1 and 2) pins form a four-bit control word
input. A negative-going pulse on the CWS (Control Word
Strobe) pin writes the data on these pins into four internal
control latches, and resets the multiplex counter in preparation for sequencing a data transfer operation. The select
code 00 is reserved for changing the state of the Store and/
or Up/Down latches without initiating a data transfer. Writing a one into the Store latch sets the latch and causes the
data in the counter to be transferred into the output latches,
while writing a zero resets the latches causing them to retain data and not be updated. Similarly, writing a one into
the Up/Down latch causes the counter to count up and writing a zero causes the counter to count down. The state of
the Store and Up/Down latches may also be changed with
a non-zero select code.
Writing a nonzero select code initiates a data transfer
operation. Writing select code of 01 (SC1, SC2) indicates
that the data in the output latches will be active and enables
the BCD I/O port to output the data. Writing a select code
of 11 indicates that the register will be preset, and a 10
indicates that the counter will be preset.
When a nonzero select code is read, the clock of the
four-state multiplex counter is switched to the DATA
TRANSFER pin. Negative-going pulses at this pin then sequence a digit-by-digit data transfer, either outputting data
or presetting the counter or register as determined by the
select code. The output drivers of the BCD I/O port will be
enabled only while DT is low during a data transfer initiated
with a 01 select code.

Table 4: ICM7227 1/0 Timing Requirements
Symbol

Description

Control Word Strobe
Width (min)
tiCs Internal Control Set-up (min)
ID'fw DATA TRANSFER pulse
width (min)
t8Cs Control to Strobe setup (min)
tsCh Control to Strobe hold (min)
tlDs Input Data setup (min)
tlDh Input Data Hold (min)
tTDacc Output Data access
tTOt Output Transfer to Data float

tcws

Min Typ Max Units
275
2.5
300
300
300
300
300
300
300

ns
3

",s
ns
ns
ns
ns
ns
ns
ns

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but an!J not tssted

14-65

I\)
I\)

....

.D~OIL

t ICM7217/ICM7227
&'II
too

APPLICATIONS
B
:::. FIXED DECIMAL POINT
...
too

&'II
too

I

VDO

ICU7217JB

(:..ur::

In the common anode versions, a fixed decimal point may
be activated by connecting the D.P. segment lead from the
appropriate digit (with separate digit displays) through a
390 series resistor to Ground. With common cathode devices, the D.P. segment lead should be connected through
a 750 series resistor to Vee.
To force the device to display leading zeroes after a fixed
decimal point, use a bipolar transistor and base resistor in a
configuration like that shown below with the resistor connected to the digit output driving the D.P. for left hand D.P.
displays, and to the next least significant digit output for
right hand D.P. display. See Performance Characteristics for
a similarly operating multi-digit connection.

Ale)
(leM 72Z7 AIC)

;

DIGIT (SEG)

sea (DIGIT)

-I
v..

0354-23

Figure 14: Driving High Current Displays

DI......V

CON'-

Dn~'

DIGIT . . . . . . .

'::L.

••

....IT
LIN!

LCD DISPLAY INTERFACE
The low-power operation of the ICM7217 makes an LCD
interface desirable. The IntersillCM7211 4 digit BCD to LCD
display driver easily interfaces to the ICM7217 as shown in
Figure 15. Total system power consumption is less than
5mW. System timing margins can be improved by using capacitance to ground to slow down the BCD lines. A similar
circuit can be used to drive Vacuum Fluorescent displays,
with the ICM7235.
The 10 - 20kO resistors on the switch BCD lines serve to
isolate the switches during BCD output.

COMMON ANODI
COMMON CATHODe

0354-22

Figure 13: Forcing Leading Zero Display

DRIVING LARGER DISPLAYS
For displays requiring more current than the ICM7217!
7227 can provide, the circuits of Figure 14 can be used.

YDD:: 5V

VOO" IV

,.,.,....
....,.,.,
I
LCD .'IPLAY

L

::t
37

.~

J

.....

0434

.,

ICM7211 D. . .

~

21 SEGMENTS

31

DII3 30
DB2 29

4 8',
5 4',

081 at

~:

DBO .

AND BACKPLANE

Voo
D.C.

ICM7217
IJI
COUNT 8

fiOiiE
•
UP/DN 1D
iESiT14

~~ ~ ~

~~

~'" ~ ~d "'~

y y

~~

~ ~

~ ~

.
3

~

Dl~

D.r,j-

g:~

~ ~

~ "f:j
10-2OK1I

0354-24

Figure 15: LCD Display Interface (with Thumbwheel Switches)
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AD typ/cIIJ vdJB$ INIvtI bBtm clMlwcterlztxl but.,. not Rt«J.

14-66

.D~DI!. C;
I:

ICM7217/ICM7227

In the tape recorder application, the LOAD REGISTER
EQUAL and ZERO outputs are used to control the recorder:
To make the recorder stop at a particular point on the tape,
the register can be set with the stop point and the EQUAL
output used to stop the recorder either on fast forward, play
or rewind.
To make the recorder stop before the tape comes free of
the reel on rewind, a leader should be used. Resetting the
counter at the starting point of the tape, a few feet from the
end of the leader, allows the ZERO output to be used to
stop the recorder on rewind, leaving the leader on the reel.
The 1Mn resistor and .0047",F capacitor on the COUNT
INPUT provide a time constant of about 5ms to debounce
the reel switch. The Schmitt trigger on the COUNT INPUT of
the ICM7217 squares up the signal before applying it to the
counter. This technique may be used to debounce switchclosure inputs in other applications.

UNIT COUNTER WITH BCD OUTPUT
The simplest application of the ICM7217 is a 4 digit unit
counter (Figure 16). All that is required is an ICM7217, a
power supply and a 4 digit display. Add a momentary switch
for reset, an SPOT center-off switch to blank the display or
view leading zeroes, and one more SPOT switch for up!
down control. Using an ICM7217A with a common-cathode
calculator-type display results in the least expensive digital
counter! display system available.

INEXPENSIVE FREQUENCY COUNTER/
TACHOMETER
This circuit uses the low power ICM7555 (CMOS 555) to
generate the gating, STORE and RESET signals as shown
in Figure 17. To provide the gating signal, the timer is configured as an astable multivibrator, using RA, Rs and C to
provide an output that is positive for approximately one second and negative for approximately 300 - 500",s. The positive waveform time is given by twp = 0.693 (RA + Rs)C while
the negative waveform is given by twn = 0.693 RsC. The
system is calibrated by using a 5Mn potentiometer for RA
as a "coarse" control and a 1kn potentiometer for Rs as a
"fine" control. CD401 06B's are used as a monostable multivibrator and reset time delay.

PRECISION ELAPSED TIME/
COUNTDOWN TIMER
The circuit in Figure 19 uses an ICM7213 precision one
minute/one second timebase generator using a 4.1943MHz
crystal for generating pulses counted by an ICM7217B. The
thumbwheel switches allow a starting time to be entered
into the counter for a preset-countdown type timer, and allow the register to be set for compare functions. For instance, to make a 24-hour clock with BCD output the register can be preset with 2400 and the EQUAL output used to
reset the counter. Note the 10k resistor connected between
the LOAD COUNTER terminal and Ground. This resistor
pulls the LOAD COUNTER input low when not loading,
thereby inhibiting the BCD output drivers. This resistor
should be eiiminated and SW4 replaced with an SPOT center·off switch if the BCD outputs are to be used.

TAPE RECORDER POSITION
INDICATOR/CONTROLLER
The circuit in Figure 18 shows an application which uses
the up/down counting feature of the ICM7217 to keep track
of tape position. This circuit is representative of the many
applications of up/down counting in monitoring dimensional
position. For example, an ICM7227 as a peripheral to a
processor can monitor the position of a lathe bed or digitizing head, transfer the data to the processor, drive interrupts
to the processor using the EQUAL or ZERO outputs, and
serve as a numerical display for the processor.

CARRY
ZERO

BCD~
OUTPUT

21-23

1
2

1

25-28"

4
5
6
7

COUNT INPUT 8

7 SEGMENTS
COMMON-CATHODE
LED DISPLAY

leM
7217A

r-_---.....L----....

LJ ':I " ,-,

U U ,-,
_ ,.J

24I-Dc-I..,S~P-LA-Y-+---<>

""S"'T"'0"'R-E--~9

20 CONTROL

191-----..
15-18

0354-25

Figure 16: Unit Counter

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE

~~~~~~~~~~;~~L~ ~~N~~L~;~V~ ~:~~~~~ ~~~~

LIEU OF ALL OTHeR WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES

NOTE: All typical values have bsen charactBrized but are not tested.

14-67

OF

.......
II)

.....
C;
I:

...
...
II)
II)

~

...
::::.
........
:IE

ICM7217/ICM7227

(\I

:IE

U

Voo =5VOLTS

(\I

3K

5M

24
)-__~________________~9 ~OO

g

.047

ICM7555
lk

2 TR
8 TH
Vss

ICM7217

CV

INVERTeRS: CD40108B
NANDS: CD4011B

COUNTINPUT~--------------~

••

r-----~ -----1=::::::~~I~S~E:C::::::::~

GATE

---;!-I-:-__--'
___-;1-+ 50•

()

r-----------~;~,-----

8

'!~------~LJ~------------------~{J

U

~--~'.~'--------~

r-----------~:,~'----0354-25

Figure 17: Inexpensive Frequency Counter

LOGIC TO GENERATE

COMMON-CATHODE

ReCORDER CONTROL

LEO DISPLAY

StONAL,
REEL SWITCH
CLOSED ONCE/REV

~
~ O--l~r---;V;·~·~'O~A:W:AR::D::.::::~~~

0354-27

Figure 18: Tape Recorder Position Indicator

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

14-68

ICM7217/ICM7227

RUNIIINlHC

ITOP
1

1$

.eM 12

aW1

"UN HRS/IltH

7213 It
'0
•

•

Yoo

(4 VOL T8 MAX)

:so,F 4.1843 MHz
':a

CRYSTAL

As < 7$0

Yeo LOAD

lET PT.

DISPLAY OfF

Yoo PRESET

SW5-1....

RESET

0354-28

Figure 19: Precision Timer

COMMON-ANODE
LED D'SPLAYS

II II
-U-'-,.•/
L, U
I

f ,-,

II

"'----U U U '-'
,-,

,-,

,-,

COUNT INPUT

CARRY OUT
BCD OUTPUTS
HIGH ORDER DIGITS
y ... ~OWN

.p

4 4-7 leM 24

7217

0354-29

Figure 20: 8 Digit Up/Down Counter

B
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

14·69

ICM7217/ICM7227
--~----~--------~---;r-------------------~V+=5Y

22pF

10kll
COMMON·ANODE
LED DISPLAY

INPUT

0354-30

Figure 21: Precision Frequency Counter (MHz Maximum)
To implement a four digit tachometer, the ICM7207A with
one second gating should be used. To get the display to
read directly in RPM, the rotational frequency of the object
to be measured must be multiplied by 60. This can be done
electronically using a phase-locked loop, or mechanically by
using a disc rotating with the object with the appropriate
number of holes drilled around its edge to interrupt the light
from an LED to a photo-dector. For faster updating, use 0.1
second gating, and multiply the rotational frequency by 600.
For more "intelligent" instrumentation, the ICM7227 interfaced to a microprocessor may be more convenient (see
Figure 21). For example, an ICM7207A can be used with
two ICM7227's to provide an 8 digit, 2MHz frequency counter. Since the ICM7207A gating output has a 50% duty cycle, there is 1 second for the processor to respond to an
interrupt, generated by the negative going edge of this signal while it inhibits the count. The processor can respond to
the interrupt using ROM based subroutines, to store the
data, reset the counter, and read the data into main memory. To add simultaneous period display, the processor inverts the data and an ICM7218 Universal Display Driver
stores and displays it.

This technique may be used on any 3-level input. The
100kO pullup resistor on the count input is used to ensure
proper logic voltage swing from the ICM7213. For a less
expensive (and less accurate) timebase, an ICM7555 timer
may be used in a configuration like that shown in Figure 17
to generate a 1Hz reference.

8-DIGIT UP/DOWN COUNTER
This circuit (Figure 20) shows how to cascade counters
and retain correct leading zero blanking. The NAND gate
detects whether a digit is active since one of the two segments or b is active on any unblanked number. The flip
flop is clocked by the least significant digit of the high order
counter, and if this digit is not blanked, the Q output of the
flip flop goes high and turns on the NPN transistor, thereby
inhibiting leading zero blanking on the low order counter.
It is possible to use separate thumbwheel switches for
presetting, but since the devices load data with the oscillator free-running, the multiplexing of the two devices is difficult to synchronize. This presents no problems with the
ICM7227 devices, since the two devices are operated as
peripherals to a processor.

a

AUTO-TARE SYSTEM

PRECISION FREQUENCY COUNTER/
TACHOMETER

This circuit uses the count-up and count-down functions
of the ICM7217, controlled via the EQUAL and ZERO outputs, to count in SYNC with an ICL7109 AID Converter as
shown in Figure 22. By RESETing the ICM7217 on a "tare"
value conversion, and STORE-ing the result of a true value
conversion, an automatic tare subtraction occurs in the result.
The ICM7217 stays in step with the ICL7019 by counting
up and down between 0 and 4095, for 8192 total counts,
the same number as the ICL7109 cycle. See A047 for more
details.

The circuit shown in Figure 21 is a simple implementation
of a four digit frequency counter, using an ICM7207A to
provide the one second gating window and the STORE and
RESET signals. In this configuration, the display reads hertz
directly. With Pin 11 of the ICM7027A connected to VDD,
the gating time will be 0.1 second; this will display tens of
hertz as the least significant digit. For shorter gating times,
an ICM7207 may be used (with a 6.5536MHz crystal), giving
a 0.Q1 second gating with Pin 11 connected to VDD, and a
0.1 second gating with Pin 11 open.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN

ueu

OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but ars not tested.

14-70

IIID~OIl..

ICM7217/ICM7227

n
I:

....

.......

I\)

-

.

i&.

FUUICAi..II!
IHI'\IT

-

~C

•

-t-:'

Q~
:"!~

-D

II

.......r--

,-

C

II

R
--;;-

;..l

-

tOND

VDO"
AEF IN~ It
REF CAP· 31
REF CAp· 3'1'

2 STATUS

3'01..
40"
5112
1111
7.,0

...
""
,. .

REF IN+'.

IN HI 35
IN 1..034
COMMON 33

.oa

INTU

""31

1087

ICL7101

I

..

" i:IDil
" iiiEH
~

:::;:'.F

VSS 21

SEND 27
RUN/HOLD 26

BUf

ose OUT 25
OSC SEL 24

.:!I!:

::!I"

1

.."..,.

1..lF- "'F- ..IF-

1

1

a!IIRS

,+
,-

'----

r-.'V

10 UP"oo.;;

"::"

~I'-

ose OUT 23
OSC IN 22
MODE 21 ~+5V

••v-jt-10"F

11 LOAD REG.
12 LOAD CTR.
13 SCAN

~C>-

U

DI"'.

ICM7217

.iTOoi

,.lImf

SV

VDD24

fiCO,

'COUNT

47.

....

1

DUO

SICD ..

"- ,.cO2

....

I\)
I\)

02. -_ I ' ~

"COl

O"/o1'lh
~IO.22jo1'

I:

7

::~

1 CARRY/IOIIROW

.rm:m:

,01<

-

aUF 30
REF OUT 2t

1285

1483
1582
'68'
17 TEST

,..-,.v

Y0 g b

LID
- - liON

·SV

~'~

....
n

0000T~_

_IIIPUY

'IV

eOtn'. 23
022

~~47.F

la,
v....

i,. --=:.-

.11

017
111
C 15

TARE

0354-31

Figure 22: Auto-Tare System for AID Converter

II
INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values ha~ been characterized but are not msted.

14·71

:: ICM7224/ICM7225

LCD/LED
I~ 4%-Digit
Display Counter

•
01
01

...
~

GENERAL DESCRIPTION

FEATURES

The ICM7224 and ICM7225 devices constitute a family of
high-performance CMOS 4 %-dlglt counters, Including decoders, output latches, display drivers, count inhibit, leading
zero blanking, and reset circuitry.
The counter section provides direct static counting, guaranteed from DC to 15 MHz, using a 5V ± 10% supply over
the operating temperature range. At normal ambient temperatures, the devices will typically count up to 25 MHz. The
COUNT Input Is provided with a Schmitt trigger to allow operation In noisy environments and correct counting with
slowly changing inputs. The COUNT INHIBIT, STORE and
RESET inputs allow a direct Interface with the ICM7207I A
to Implement a low cost, low power frequency counter with
a minimum component count.
These devices also incorporate several features intended
to simplify cascading four-digit blocks. The CARRY output
allows the counter to be cascaded, while the Leading Zero
Blanking INput and OUTput allows correct Leading Zero
Blanking between four-decade blocks. The BackPlane driver of the LCD devices may be disabled, allowing the segments to be slaved to another backplane signal, necessary
when using an eight or twelve digit, single backplane display. In common-anode LED systems, the BRighTness input to several ICM7225 devices may be ganged to one potentiometer.
The ICM722411CM7225 family are packaged in a standard 40-pin dual-in-line plastiC or CERDIP package, or In
dice.

• High Frequency Counting - Guaranteed 15MHz,
Typically 25MHz at 5V
• Low Power Operation-Typically Less Than 100p.W
Quiescent
• S'i'ORE and RESET Inputs Permit Operation as
Frequency or Period Counter
• True COUNT INHIBIT Disables Firat Counter Stage
• CARRY Output for cascading Four-Digit Blocks
• SchmIH-Trigger On The COUNT Input Allows
Operation In Noisy Environments or With Slowly
Changing Inputs
• leading Zero Blanking INput and OUTput for Correct
leading Zero Blanking With Cascaded Devices
• LCD Devices Provide Complete Onboard Oscillator
and Divider Chain to Gensrate Backplane Frequency,
or Backplane Driver May Be Disabled Allowing
Segments to be Slaved to A Master Backplane Signal
• LED Devices Provide BRighTness Input Which Can
Function Digitally As A Display Enable or As A
Continuous Display Brlghtneaa Control With A Single
Potentiometer

ORDERING INFORMATION
Part Number

Display Typs

ICM72241PL

LCD

19999

ICM72251PL

LED

19999

Count Option

Evaluation Kits, order ICM7224 EVlKlt or ICM7225 EVIKit

0355-1

Figure 1: Pin Configuration
(Outline dwg PL)

INTERSIL'S SOLE AND EXClUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIes, EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AD typIcsJ _

lis.. bHn _

but IUS not /oslod.

14-72

ICM7224/ICM7225
ICM7224(A)

MSD

LSD
DIGIT 1
SEGMENT OUTPUTS

DIGIT 2
SEGMENT OUTPUTS

DIGIT 3
SEGMENT OUTPUTS

DIGIT 4
SEGMENT OUTPUTS

1/2-DIGIT
OUTPUT

STORE----+I
LEADING

LEADING

BLAN~~~+-----f

1+-----t-~c:~KING

OUTPUT

L--"'T"'TTT...J

INPUT

~~~~~----+I
COUNT
INPUT
RESU--__---~----~---6---~-_t-~---~--~~--~--1t:::~-~~RRY

OSCIL~~~~ ___....._ ;
+124

BACKPLANE
DRIVER

OUTPUT
BACKPLANE
t-<_-----------------INPUT/
OUTPUT

0355-2

ICM7225(A)

LSD
DIGIT 1
SEGMENT OUTPUTS

t.1SD
DIGIT 2
SEGMENT OUTPUTS

DIGIT 3
SEGMENT OUTPUTS

DIGIT 4
SEGMENT OUTPUTS

1/2- DIGIT
OUTPUT

STORE - - - - + I

LEADING

LEADING

BLANZ~~g +-----f

I+-----t-~~~KING

OUTPUT

INPUT

COUNT
INHIBIT----+I
COUNT
INPUT
R~IT----~---~--~_--~--+-4_--_4~--4_--_4~-t_~
L--_ _ _... CARRY

OUTPUT
L--------------------BRIGHTN~S

0355-3

Figure 2: Functional Diagrams

INTERStL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but ar9 not t9St8d.

14-73

II

=ICM7224/ICM7225
...
C\I

2 ABSOLUTE MAXIMUM RATINGS

.

U

:::.
C\I
C\I

...
:I

!:!

Operating Temperature Range .•...•..• - 25·C to + 85·C
Storage Temperature Range ..... . . • .• - 65·C to + 150·C
Lead Temperature (Soldering, 10sec) ............. 300·C

Supply Voltage (Voo-Vss) ....................... 6.5V
Input Voltage (Any
Terminal) (Note 2) ••....... (Voo+ 0.3V) to (Vss-0.3V)
Power Dissipation (Note 1) ................ 0.5W @ 70"C

NOTE 1: This limit refers to that of the package and will not be obtained during normal operation.
2:

Oue to the SCR structure inherent in the CMOS process, oonnecting any terminal to voltages graater than VDD or less than VSS may cause destructive
device latch up. For this reason. It is reoommended that no inputs from sources operating on a different power supply be applied to the device befora its
supply Is established, and that In multiple supply systems, the supply to the ICM7224/ICM7225 be turned on first.

NOTE: Stresses above those listed under "Absolu/9 Maximum Ratings" may cause permanent damage to the davies. These artJ stress ratings only and functional
operation of the davies at thase or any other conditions abo"" those indicated in the operational sactiona of the specifications is not imp/ied. Expos/Jr9 to sbs0/u/9
maximum rating conditions for exf9ndad psriods mayaff9ct davies rs/lablHty.

ELECTRICAL CHARACTERISTICS

(Voo= 5V, Vss= OV, TA= 25·C, unless otherwise indicated)

ICM7224 CHARACTERISTICS
SYMBOL
100
VSUPPLY
10SCI
tR, tF
tR, tF
fosc
fBP

TEST CONDITIONS
Test circuit, Display blank

PARAMETER
Operating current
Operating supply voltage range (Voo- Vss)

MIN

TYP
10

3

OSCILLATOR input current

Pin 36

±2

Segment rise/fall time
BackPlane rise/fall time

Cload = 200pF

0.5

Cload = 5000pF
Pin 36 Floating
Pin 36 Floating

1.5

Oscillator frequency
Backplane frequency

MAX
50
6
±10

UNIT
pA
V
p.A
p.s

19
150

kHz
Hz

ICM7225 CHARACTERISTICS
SYMBOL

TEST CONDITIONS

PARAMETER

MIN

Pin 5 (BRighTness) at Vss
Pins 29, 31-34 at Voo

ISTBY

Operating current display off

VSUPP
100

Operating supply voltage range (Voo - Vss)
Operating current

TYP

MAX

UNIT

10

50

p.A

4

6
200
±0,O1

Pin 5 at Voo, Display 18888

ISLK

Segment leakage current

ISEG
IH

Segment on current

Segment Off
Segment On, Vout= +3V

5

8

Half-digit on current

Half-digit on, Vout= +3V

10

16

V
mA

±1

p.A
mA

FAMILY CHARACTERISTICS
SYMBOL
Ip
VIH

PARAMETER

Pins 29, 31, 33, 34
Vout=Voo-3V
Pins 29, 31, 33, 34

Input Low Voltage

Pins 29, 31, 33, 34

VIL
VCT

COUNT Input Threshold

VCH

COUNT Input Hysteresis

10H

Output High Current

10L

Output Low Current

fCOUNT
tS,tR

TEST CONDITIONS

Input
Pullup Currents
Input High Voltage

Count Frequency

MIN

TYP

MAX

10

UNIT
p.A

3

1

V

2
0.5
CARRY Pin 28
Leading Zero Blanking OUT Pin 30
Vout=Voo-3V
CARRY Pin 28
Leading Zero Blanking Out Pin 30
Vout= +3V
4.5V<

<

~

~

,/

~I/ ~

.I

"
·c
"i.--' ~ -- arc

,/

V

.....TA -7 C

10-' ~

~
1

I

,....,.WAYE-.T

~

o•

~ ...

MAXIMUM COUNT FREQUENCY (TYPICAL) AS A
FUNCTION OF SUPPLY VOLTAGE

1/

I:

y

I

0355-7

/

•

II

Case (pF)

/

•

I

1.( VSUPPLY= 5V

hSUPPLy=3V

1

7225 LED SEGMENT CURRENT AS A
FUNCTION OF BRIGHTNESS CONTROL VOLTAGE

I

~

VSUPPLy=4V

~

•

VSUPPLY = 6V

~~
)"",~

'"

"

..

0355-5

LCtl DEVICES

~'ALL""'"

V

'2

loY

7224 BACKPLANE FREQUENCY AS A
FUNCTION OF OSCILLATOR CAPACITOR Case

wl.~

~

I-

o

7225 OPERATING POWER (LED DISPLAY) AS A
FUNCTION OF SUPPLY VOLTAGE

..

VSUPPLY ·IV

1/

o

0355-4

CII

I

IJ ,/ ysu""'......"v·
• '(j

•

SUPPLY VOLTAGI! IVI

II)
II)

'- W

1/

I

~

V

V'iY,IV '- l -

~

,

...

1""'1-'-

i-""

I
i"

.. ,'..... II'/I

n
I:

TA-we

I

TA-"

.:e.

7225 LED SEGMENT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

.. .J.IA~ vo!.

7224 OPERATING SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE
:...~. . . doIculr.

I

:I

4

•

I

BRIGHTNESS CONTROL VOLTAGE

0355-9

•

SUPPLY VOLTAGE IVI

•
0355-10

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typic8I MIIu6s MWI b68n charsctetized but are not teslsd.

14·75

...

I:
II)
II)

TYPICAL PERFORMANCE CHARACTERISTICS

.
. -.-

n

: ICM7224/ICM7225

...

C\I

:Ii! TYPICAL PERFORMANCE CHARACTERISTICS

g,'It

(Continued)

SUPPLY CURRENT AS A
FUNCTION OF COUNT FREQUENCY

C\I
C\I

0

...

W

or-sv
TA -u·c

:Ii!

1

2

i
~
>~

1

I

It

0.1

~

r--

01

"""

10t1Hr

100kHz

1MHz

1011Hz

l00MHz

jCOUNT
0355-11

TABLE I- Control Input Definitions
INPUT

TERMINAL

Leading Zero Blanking
INput

29

COUNT INHIBIT

31

RESET

33

STORE

34

VOLTAGE

FUNCTION

VDD or Floating
Vss
VDD or Floating
Vss
VOD or Floating
Vss
VOO or Floating
Vss

Leading Zero Blanking Enabled
Leading Zeroes Displayed
Counter Enabled
Counter Disabled
Inactive
Counter Reset to 0000
Output Latches not Updated
Output Latches Updated

source. This allows the use of displays with characters In
multiples of four and a single backplane. A slave device will
represent a load of approximately 200pF (comparable to
one additional segment). The limitation on the number of
devices that can be slaved to one master device backplane
driver is the additional load represented by the larger backplane of displays of more than four digits, and the effect of
that load on the backplane rise and fall times. A good rule of
thumb to observe in order to minimize power consumption,
is to keep the rise and fall times less than about 5 microseconds. The backplane driver devices of one device should
handle the backplane to a display of 16 one-half-inch characters without the rise and fall times exceeding 5!,-s (ie, 3
slave devices and the display backplane driven by a fourth
master device). It is recommended that if more than four
devices are to be slaved together, that the backplane signal
be derived externally and all the ICM7224 devices be
slaved to it.
This external backplane signal should be capable of driving very large capacitive loads with short (1-2!,-s) rise and
fall times. The maximum frequency for a backplane signal
should be about 150Hz, although this may be too fast for
optimum display response at lower display temperatures,
depending on the display used.
The onboard oscillator is designed to free run at approximately 19kHz, at microampere power levels. The oscillator
frequency is divided by 128 to provide the backplane frequency, which will be approximately 150Hz with the oscilla-

CONTROL INPUT DEFINITIONS
In Table I, Voo and Vss are considered to be normal
operating input logic levels. Actual input low and high levels
are specified in the Operating Characteristics. For lowest
power consumption, input Signals should swing over the full
supply.

DETAILED DESCRIPTION
LCD Devices
The LCD devices in the family (lCM7224 and ICM7224A)
provide outputs suitable for driving conventional 4 %-digit by
seven segment LCD displays. They include 29 individual
segment drivers, a backplane driver, and a self-contained
oscillator and divider chain to generate the backplane frequency.
The segment and backplane drivers each consist of a
CMOS inverter, with the n- and p-channel devices ratioed to
provide identical on resistances, and thus equal rise and fall
times. This eliminates any D.C. component which could
arise from differing rise and fall times, and ensures maximum display life.
The backplane output devices can be disabled by connecting the OSCILLATOR input (pin 36) to Vss· This synchronizes the 29 segment outputs directly with a signal input at the BP terminal (pin 5) and allows cascading of several slave devices to the backplane out~ut of one master device. The backplane may also be derrved from an external

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE All typical values have been characterized but are not tested.

14-76

ICM7224/ICM7225
tor free-running. The oscillator frequency may be reduced
by connecting an external capacitor between the OSCillator
terminal (pin 36) and Voo; see the plot of oscillator/backplane frequency in "Typical Characteristics" for detailed information.
The oscillator may also be overdriven if desired, although
care must be taken to insure that the backplane driver is not
disabled during the negative portion of the overdriving signal (which could cause a D.C. component to the display).
This can be done by driving the OSCILLATOR input between the positive supply and a level out of the range where
the backplane disable is sensed, about one fifth of the supply voltage above the negative supply. Another technique
for overdriving the oscillator (with a signal swinging the full
supply) is to skew the duty cycle of the overdriving signal
such that the negative portion has a duration shorter than
about one microsecond. The backplane disable sensing circuit will not respond to signals of this duration.

0355-12

Figure 3: Brightness Control

COUNTER SECTION
The devices in the ICM7224/ICM7225 family implement a
four-digit ripple carry resettable counter, including a Sch~itt
trigger on the COUNT input and a CARRY output. Also Included is an extra D-type flip-flop, clocked by the CARRY
Signal which controls the half-digit segment driver. This output driver can be used as either a true half-digit or as an
overflow indicator. The counter will increment on the negative-going edge of the signal at ~he C<>-ri

BUFFERED
osc OUT
oseOUTpuT

qm

~~~==~U~~~~~~t=8d~~~~~kj~E~~~~~~~~===

'NPUTO--1T~:~;-ITr=====:;:=~:±=;;;~1~RJ

EXT

RANGE INPUT
CONTROL

INPUT

1---------.... ~~:u~
INPUT A

p

O----r+-l

INPUT • o--~++-I

SEGMENT

OuTPUTStt.

='

L _ _ _ _ _ ~ __ BCD

-,----v~

MlAS LNPROG
OUTPUT

"OLD INPUT

v

'---------t

0---.......<:.--_____+-_-'
0-----=--_____-'

L.._ _ _ _ _ _ _ _ _- ;

0

,i

-:

:

:::::TS '"

OUTPUT

0356-3

Figure 2: Functional Diagram

II
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE· All typical values have been characterized but are not tested.

14-81

SleM7226A/B

.OIMUlfiOIL

co
:: ELECTRICAL CHARACTERISTICS

i

Symbol
100

VSUPPLY

fA(max)

Parameter

(Voo=5.0V, TA=25°C, unless otherwise specified.)

Test Conditions

Operating Supply
Current

Display Off
Unused inputs to Vss

Supply Voltage Range Voo - Vss

-25°C lilLJ
30 TO 40ml

~ 80JM

.... T _ _-:-_ _ _

~n~-+--~

fUNCTtON:
TIME INTERVAL

1-+MEASUREMEfit
iIil'Iil!Il1!n!

INPUT A

INf'UT 8

t
--4

250nsMIN.
MEASURED

INTERVAL
(FIRS!)

I
I--

I

-of

t--

MEASURED
INTERVAL
(LAST)

0356-9
NOTE: IF RANGE IS SET TO 1 EVENT, FIRST AND LAST MEASURED INTERVAL WILL COINCIDE.

Figure 7: Waveforms for Time Interval Measurement
(Others are similar, without priming phase)
Noise on the multiplex inputs can cause improper operation. This is particularly true when the unit counter mode of
operation is selected, since changes in voltage on the digit
drivers can be capacitively coupled through the LED diodes
to the multiplex inputs. For maximum noise immunity, a
10k!} resistor should be placed in series with the multiplex
inputs as shown in the application notes.
Table 1 shows the functions selected by each digit for
these inputs.

This can be easily accomplished with the following circuit:
(Figure,B).
SiGNAL A

.1D - - - - INPUT A
SIGNAL. 8

r---ID----INPUTB
VDO

VDO

NJ ~ [fi!iMij
too!.

......
'OOk

VOO

...

,
LII

t-l,

1~' r''''''-

Vss

,~ T

Table 1: Multiple Input Control

'OOk

t-l,

O.l~F

1000pF

Function

......

vss

Frequency
Period
Frequency Ratio
Time Interval
Unit Counter
Oscillator Frequency

D1
D8
D2
Ds
D4
D3

RANGE INPUT
PIN 21

0.01 Sec/1 Cycle
0.1 Sec/1 0 cycles
1 Sec/1 00 Cycles
10 Sec/1 k Cycles
Enable External Range
Input

D1
D2
D3
D4

0356-10

Figure 8: Priming Circuit, Signal A&B
High or Low
Device

Type

1
2

CD4049B Inverting Buffer
CD4070B Exclusive-OR
PIN31

MULTIPLEXED INPUTS

CONTROL INPUT
PIN 1

The FUNCTION, RANGE, CONTROL and EXTERNAL
DECIMAL POINT inputs are time multiplexed to select the
input function desired. This is achieved by connecting the
appropriate digit driver output to the inputs. The input function, range and control inputs must be stable during the last
half of each digit output, (typically 125,."s). The multiplex
inputs are active high for the common anode ICM7226A,
and active low for the common cathode ICM7226B.

Digit

FUNCTION INPUT
Pin 4

Ds

D4 & Hold
Display Off
Display Test
D8
1MHz Select
D2
External Oscillator Enable
D1
External Decimal Point
D3
Enable

EXTERNAL DECIMAL Decimal Point is Output for Same
POINT INPUT, PIN 20 Digit That is Connected to This Input

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOA A PARTICULAR USE.
NOTE: All typical values have been characterized but arB not tested.

14-85

II

ICM7226A/B

=
...
CIt
CIt

II

2

in progress without updating the display and then initiate a
new measurement. This prevents an erroneous first reading
after the FUNCTION input is changed. If the main counter
overflows, an overflow indication is output on the Decimal
Point Output during Os.

CONTROL INPUTS

Display Test - All segments are enabled continuously,
giving a display of all 8's with decimal points. The display
will be blanked if display off is selected at the same time.
Display Off - To enable the display off mode it is necessary to tie 04 to the CONTROL input and have the HOLD
input at Voo. The chip will remain in this mode until HOLD is
switched low. While in the display off mode, the segment
and digit driver outputs are open and the oscillator continues to run (with a typical supply current of 1.5mA with a
10MHz crystal) but no measurements are made. In addition,
signals applied to the multiplexed inputs have no effect. A
new measurement is initiated after the HOLD input goes
low. (This mode does not operate when functioning as a
unit counter.)
1MHz Select- The 1MHz select mode allows use of a
1MHz crystal with the same digit multiplex rate and time
between measurements as a 10MHz crystal. The internal
decimal point is also shifted one digit to the right in period
and time interval, since the least significant digit will be in
11's increments rather than 0.1I's.
External Oscillator Enable - In this mode, the EXTernal OSCillator INput is used, rather than the on-Chip oscillator, for the Timebase and Main Counter inputs in period
and time interval modes. The on-chip oscillator will continue to function when the external oscillator is selected, but
have no effect on circuit operation. The external oscillator
input frequency must be greater than 100kHz or the chip will
reset itself and enable the on-Chip oscillator. Connect external oscillator to both OSC IN (pin 35) and EXT OSC IN (pin
33), or provide crystal for "default" oscillation, to avoid
hang-up problems if an external OSC or TXCO will always
be used, AC couple to OSC IN.
External DeCimal Point Enable - When external decimal point is enabled, a decimal point will be displayed
whenever the digit driver connected to the EXTERNAL
DECIMAL POINT pin is active. Leading Zero Blanking will
be disabled for all digits following the decimal point.

Table 2: Input Routing
Description

Main Counter

Reference
Counter

Frequency (fA)

Input A

100 Hz (OSCillator
+ 105 or 104 )
Input A

Period (tAl

Oscillator

Ratio (fA/fs)

Input A

Input B

Time Interval
(A --+ B)

OscON
Gate

OscOFF
Gate

Unit Counter
(Count A)

Input A

Not Applicable

Osc. Freq.
(foscl

Oscillator

100 Hz (OSCillator
+ 105 or 104 )

EXTERNAL DECIMAL POINT INPUT
When the external decimal point is selected, this input
is active. Any of the digits. except Os, can be connected to
this point. Os should not be used since it will override the
overflow output and leading zeros will remain unblanked after the decimal point.
HOLD Input - Except in the unit counter mode, when
the HOLD input is at VOO, any measurement in progress
(before STORE: goes low) is stopped, the main counter is
reset and the chip is held ready to initiate a new measurement as soon as HOLD goes low. The latches which hold
the main counter data are not updated, so the last complete
measurement is displayed. In unit counter mode when
HOLD input is at Voo. the counter is not stopped or reset,
but the display is frozen at that instantaneous value. When
HOLD goes low the count continues from the new value in
the counter.
RESET Input - The RESET Input resets the main counter, stops any measurement in progress, and enables the
main counter latches, resulting in an all zero output. A capacitor to ground will prevent any hang-ups on power-up.
EXTernal RANGE Input- The EXTernal RANGE Input
is used to select other ranges than those provided on the
chip. Figure 9 shows the relationship between MEASurement IN PROGRESS and EXTernal RANGE Input.

RANGE INPUT
The range input selects whether the measurement is
made for 1, 10, 100 or 1000 counts of the reference counter, or if the EXTernal RANGE INput determines the measurement time. In all functional modes except unit counter,
a change in the RANGE input will stop the measurement in
progress, without updating the display, and initiate a new
measurement. This prevents an erroneous first reading after
the RANGE input is changed.

FUNCTION INPUT
Six functions can be selected. They are: Frequency, Period, Time Interval, Unit Counter, Frequency Ratio and
OSCillator Frequency.
These functions select which signal is counted into the
main counter and which signal is counted by the reference
counter, as shown in Table 2. In time interval a flip flop is
set first by a 1 --+ 0 transition at INPUT A and then reset by
a 1 --+ 0 transition at INPUT B. The oscillator is gated into
the Main Counter during the time the flip flop is set. A
change in the FUNCTION input will stop the measurement

REFERENCE
COUNTER

CLOCK

eXT RANGE

INPUT

0356-11

Figure 9: External Range Input to End of
MEASUREMENT IN PROGRESS.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.

~~~~~~~~~~T~~~~ ~~N~~~L~~~~ ::T~~~~LR ~~~~ LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
NOTE: All typical values have been characterized but are not tesl9d.

14·86

ICM7226A/B
Main Counter overflows. The internal decimal pOint control
displays frequency in kHz and time in ,..,S.
The ICM7226A is designed to drive common anode lED
displays at a peak current of 25mAlsegment. using displays
with VF ~ 1.8V at 25mA. The average DC current will be
greater than 3mA under these conditions. The ICM7226B is
designed to drive common cathode displays at a peak current of 15mAI segment, using displays with VF ~ 1.8V at
15mA. Resistors can be added in series with the segment
drivers to limit the display current. if required. Figures 11.
12. 13 and 14 show the digit and segment currents as a
function of output voltage for common anode and common
cathode drivers.

MEASUREMENT IN PROGRESS, STORE AND RESET
Outputs - These Outputs are provided to facilitate external interfacing. Figure 10 shows the relationship between
these signals during the time between measurements. All
three outputs can drive a low power Schottky TTL load. The
MEASUREMENT IN PROGRESS output can directly drive
one ECl load. if the ECl device is powered from the same
power supply as the ICM7226.

1-"
Ml'Ail/MMLNT
IN PROGRESS

,-190 TO

2ooms----1

I 1--+40m.
---~I

IU
r-1-

n

30 TO 40ms+-1

I

RESET OUT

I'-----60m8

-40-m-.----

i.. -------I-I-,

0356-12

Figure 10: RESET OUT, STORE, and
MEASUREMENT IN PROGRESS Outputs
Between Measurements.

100

BCD Outputs - The BCD representation of each digit
output is available at the BCD outputs; see Table 3 for Truth
Table. The positive going (ICM7226A-Common Anode) or
negative going (ICM7226B - Common Cathode) digit drivers lag the BCD data by 2 to 6 microseconds; the leading
edge of the digit drive signal should be used to externally
latch the BCD data. Each BCD output will drive one low
power Schottky TTL load. The display is multiplexed from
MSD to LSD. leading zero blanking has no effect on the
BCD outputs.
Table 3: Truth Table BCD Outputs
Number

BCD8
Pin7

BCD 4
Pin 6

BCD2
Pin 17

BCD 1
Pin 18

0
1
2
3
4
5
6
7
8
9

0
0
0
0
0
0
0
0
1
1

0
0
0
0
1
1
1
1
0
0

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

1---+----,,,,,-+-----1

1

2

vDD - Yo (VOLTa)

0356-13

Figure 11: ICM7226A TypicallOIG VS. VOO-VO
4.SS:VooS:6.0V

..

V' -MY

,.'v

80

y.~ ~'

C

i

40

20

~

.lL
•

JI''' \

c

!.

~

y. = Uy

1
2

1

Vo(VOLTS)
(.)

-2.~

•• r--40

20

3

•

/
,~

."'C

...... r

~.

~~~~C
v,,,,

~'

V, =15.OV

J

1

2

3

Va (VOLTS)

(b)

0356-14

Figure 12: ICM7226A TypicallSEG VS. Vo

BUFFered OSCillator OUTput - The BUFFered OSCillator OUTput has been provided to enable use of the on
chip oscillator signal without loading the oscillator itself.
This output will drive one low power Schottky TTL load.
Care should be taken to minimize capacitive loading on this
pin.

150 t-----t-'V:~~~

150

so 1--I'-;-----j-----1

so

DISPLAY CONSIDERATIONS
The display is multiplexed at a 500Hz rate with a digit time
of 244,..,s. and an interdigit blanking time of 6,..,s to prevent
ghosting between digits. The decimal point and leading zero
blanking have been implemented for right hand decimal
point displays; zeros following the decimal point will not be
blanked. leading zero blanking will also be disabled if the

1

Yo (VOLTI)

0356-15

Figure 13: ICM7226B TypicailOIG VS. Vo

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PROOUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested

14·87

ID

3
C\I
C\I

....

.D~DI!.

ICM7226A/B
30

Ii

,----,---...-----'71

2Or---+------''i-,;~__I

1

2

IE

3

IE
::>
IE

5

i
10r---+--~~+--__I

1/ ,,~
10 CYCLES
1",1'\1'\ "' 1/Y
1"'\1"'
"' / 1/
I,
/"

)

: ['\ l'\ ['\ ['\.

...

2

~

MEASUREMENT
lose • 10MHz

103 CYCLES

4

l/

..
)
"
"'

;}If.

;}If.

,~

1/1/V
I'\.
, / / / V 1"'\ I'\.
1,\
• /V/l/

IE

PERIOD

102 CYCLES

6

.1

1

0.1 SEC
1 SEC

FREQUENCY
MEASUREMENT

10 SEC

10 100 103 104 105 106 107

VDD· Your (VOL T5)

FREOUENCY (Hz)

0356-16

0356-17

Figure 14: ICM7226B TypicallSEG vs. (VOO-VO)

Figure 15: Maximum Accuracy of Frequency and
Period Measurements Due to Limitations of
Quantization Errors.

4.5V~VOO~6.0V

To increase the light output from the displays, Voo may
be increased to 6.0V, however care should be taken to see
that maximum power and current ratings are not exceeded.
The SEGment and Digit outputs in both the 7226A and B
are not directly compatible with either TTL or CMOS logic.
Therefore, level shifting with discrete transistors may be required to use these outputs as logic signals. External latching should be done on the leading edge of the digit signal.

0
.. 1

ffi§
010

2

~i

3

!~

5

'\

z ..
IE" 4
::>il:

ACCURACY
In a Universal Counter, crystal drift and quantization errors cause errors. In frequency, period and time Interval
modes, a signal derived from the oscillator is used either in
the Reference Counter or Main Counter, and in these
modes, an error in the oscillator frequency will cause an
identical error in the measurement. For instance, an oscillator temperature coefficient of 20ppml'C will cause a measurement error of 20ppml'C.
In addition, there is a quantization error inherent in any
digital measurement of ± 1 count. Clearly this error is reduced by displaying more digits. In the frequency mode,
maximum accuracy is obtained with high frequency inputs,
and in period mode maximum accuracy is obtained with low
frequency inputs. As can be seen in Figure 15, the least
accuracy will be obtained at 10kHz. In time interval measurements there is a maximum error of 1 count per interval.
As a result there is the same inherent accuracy in all
ranges, as shown in Figure 16. In frequency ratio measurement more accuracy can be obtained by averaging over
more cycles of INPUT B as shown in Figure 17.

;~

'\

V MAXIMUM TIME INTERVAL
FOR 103 INTERVALS

i",\

./

1'\ L

MAXIMUM TIME INTERVAL

./

"' "- '\
/

6

0

FOR 100 INTERVALS

V

MAXIMUM TIME INTERVAL
FOR 10 INTEf:lVALS

/'

7

•1

10 100 103 104 105 10S 107 lOS
TIME INTERVAL (/.ISfC)

0356-18

Figure 16: Maximum Accuracy of Time Interval
Measurement Due to Limitations of Quantization
Errors.

0
.. 1

...
=~
IE ...

2
3
::>z
z ..
IE" 4
::>il:

!~
;~

5

6

v"~·l

'\

1 CYCLE

"-

V
'\
V
"'\ "'\ '\
./
V
~ :"\ ."'\ .'\
V
'\. "'\ ,"'\ ~
V
'\. "'\ l\. p.;

0

7

•1

100 CYCLES

RANGE

(CYCLES OF 8)

103 CYCLES

'\ 1'\1'\ ~
I'; ~ 1'\1,\

10 102 103 11)4 105 106 107

10B

tAlfs

0356-19

Figure 17: Maximum Accuracy for Frequency
Ratio Measurement Due to Limitations of
Quantization Errors.

INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

14-88

ICM7226A/B
For input frequencies up to 40MHz, the circuit shown in
figure 14 can be used to implement a frequency and period counter. To obtain the correct value when measuring
frequency and period, it is necessary to divide the 10MHz
oscillator frequency down to 2.5MHz. In dOing this the time
between measurements is lengthened to 800ms and the
display multiplex rate is decreased to 125Hz.
If the input frequency is prescaled by ten, the oscillator
frequency can remain at either 10MHz or 1MHz, but the
decimal point must be moved. Figure 20 shows use of a +
10 prescaler in frequency counter mode. Additional logic
has been added to enable the 7226 to count the input directly in period mode for maximum accuracy. Note that A
IN comes from Qc rather than QD, to obtain an input duty
cycle of 40%. If an output with a duty cycle not near 50%
must be used then it may be necessary to use a 74lS121
monostable multivibrator or similar circuit to stretch the input pulse to guarantee a 50ns minimum pulse width.

CIRCUIT APPLICATIONS
The ICM7226 has been designed as a complete stand
alone Universal Counter, or used with prescalers and other
circuitry in a variety of applications. Since A IN and B IN are
digital inputs, additional circuitry will be required in many
applications, for input buffering, amplification, hysteresis,
and level shifting to obtain the required digital voltages. For
many applications an FET source follower can be used for
input buffering, and an ECl 10116 line receiver can be used
for amplification and hysteresis to obtain high impedance
input, sensitivity and bandwidth. However, cost and complexity of this circuitry can vary widely, depending upon the
sensitivity and bandwidth required. When TTL prescalers or
input buffers are used, pull up resistors to VDD should be
used to obtain optimal voltage swing at A IN and BIN.
If prescalers aren't required, the ICM7226 can be used to
implement a minimum component Universal counter as
shown in Figure 18.

EXT

....

eUNK

l--oVDD

AIH

ose

DISPLAY DISPLAY

lOkI}

TES'

ENABLE

VDD
DIODES: 1"'14

~====rl[i~ lOMHZ CRYSTAL

TYPICAL
CRYSTAL PARAMETERS

3tpF TYP.

CL

UpF

Rs" . 35n
' - - - - - _ EXT

ose IN

0356-20

Figure 18: 10MHz Universal Counter

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE

~~~~~:'~~~;~~L~ ~~N~~~L~~~V; ::~TI~~~ ~~~~

LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES

NOTE: All typical values have been charact9rized but are not tested.

14-89

OF

S ICM7226A/B
CD

(\I
(\I

....

VDD

II

!::!

.,,

...
0356-21

Noles: 1) If a 2.5MHz crystal is used, diode Dl and I.G.'s 1 and 2 can be eliminated.

Figure 19: 40MHz Frequency, Period Counter

,,.
INPUT

DIODES: 'N91C

'---::-----<1 EXT osc

INPUT

10k!!

OVERF~OW

,...

0356-22

Figure 20: 100MHz Multi Function Counter
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE; All typIcsl values have been characterlz9d but are not tested.

14-90

·o~on.

ICM7226A/B

a....
S
N
N

DISp\'AY DISP\.AY
OFF
TEST

IG11n

VDD'-~--~~~~------------------r---T--'
'Ok!!

INPUT

FUNCTION
SWITCH
OPENo FRED
CLOSED PERIOD

l_

0,

D.

0358-23

Figure 21: 100MHz Frequency, Period Counter
Figure 21 shows the use of a CD4016 analog multiplexer
to multiplex the digital outputs back to the FUNCTION Input.
Since the CD4016 is a digitally controlled analog transmis·
sion gate, no level shifting of the digit output is required.
CD4051's or CD4052's could also be used to select the
proper inputs for the multiplexed input on the ICM7226 from
2 or 3 bit digital inputs. These analog multiplexers may also
be used in systems in which the mode of operation is con·
trolled by a microprocessor rather than directly from front
panel switches. TIL multiplexers such as the 74LS153 or
74LS251 may also be used, but some additional circuitry will
be required to convert the digit output to TIL compatible
logic levels.
The circuit shown in Figure 22 can be used in any of the
circuit applications shown to implement a single measure·
ment mode of operation. This circuit uses the SiORE out·
put to put the ICM7226 into a hold mode. The HOLD input
can also be used to reduce the time between measurements. The circuit shown in Figure 23 puts a short pulse into
the HOLD input a short time after STORE goes low. A new
measurement will be initiated at the end of the pulse on the
HOLD Input. This circuit reduces the time between mea·
surements to less than 40ms from 200ms; use of the circuit
shown in Figure 23 on the circuit shown in Figure 19 will
reduce the time between measurements from 1600ms to
800ms.

CI._

11
12

_'II*GUIIEAI _ _LBD
-INITIATE _
. .A l I _

a

CLOIIID • HOLD INPUT

I
0356-24

Switch

Function

S1
52
53

OPEN·SINGLE MEAS MODE ENABLED
CLOSED·INITIATE NEW MEASUREMENT
CLOSED·HOLD INPUT

Figure 22: Single Measurement CircUit
for Use With ICM7226

INTERSlL'S SOLE AND EXCLUSIVE WARRANTY OSUGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS. IMPUEO OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.
NOTE: AD typical vsluss hllve bssn ch8Iactsriz8d but IUB not

_ted.
14-91

•

!!
ICM7226A/B
II(
It
ell
ell

The required gm should not exceed 50% of the gm specified for the ICM7226 to insure reliable startup. The oscillator
input and output pins each contribute about 4pF to CIN and
COUT. For maximum frequency stability, CIN and COUT
should be approximately twice the specified crystal load capaCitance.
In cases where nondecade prescalers are used, it may be
desirable to use a crystal which is neither 10MHz nor 1MHz.
In this case both the multiplex rate and the time between
measurements will be different. The multiplex rate is
fose
fose
fmux = 2 x 104 for 1OMHz mode and fmux = 2 x 103 for the

....

:IIi!

!:!
HOLOINPUT

~ON.O.
NOLO

SWITCH~
0356-25

.
. 2X1~.
1MHz mode. The time between measurements IS - - - I n
fose

Figure 23: Circuit for Reducing Time
Between Measurements

2Xl0 5
the 10MHz mode and - - in the lMHz mode. The bufffose
ered oscillator output should be used as an oscillator test
point or to drive additional logic; this output will drive one
low power Schottky TTL load. When the buffered oscillator
output is used to drive CMOS or the external oscillator input,
a 10k!} resistor should be added from the buffered oscillator output to V DO.
The crystal and oscillator components should be located
as close to the chip as practical to minimize pickup from
other Signals. In particular, coupling from the BUFFfered
OSCillator OUTput and EXTernal OSCillator INput to the
OSCillator OUTput or OSCillator INput can cause undesirable shifts in oscillator frequency. To minimize this coupling,
pins 34 and 37 should be connected to Voo or Vss and
these two signals should be kept away from the oscillator
circuit.

.5.
V·(VOI.TS)

1AMAx, - . AS FUHCTION 01' Voo
0356-26

Figure 24: Typical Operating Characteristics
Figure 25 shows the ICM7226 being interfaced to LCD
displays, by using its BCD outputs and 8 digit lines to drive
two ICM7211 display drivers. The ICM7226 EVIKit may easily be interfaced to 21CM7211 EV I Kits in this way. A similar
arrangement can be used for driving vacuum fluorescent
displays with the ICM7235.

TYPICAL L.CD DISPLAY

OSCILLATOR CONSIDERATIONS

+1:

The oscillator is a high gain complementary FET inverter.
An external resistor of 10M!} or 22M!} should be connected
between the oscillator input and output to provide biasing.
The oscillator is designed to work with a parallel resonant
1OM Hz quartz crystal with a load capacitance of 22pF and a
series resistance of less than 35!t Among suitable crystals
is the 10MHz CTS KNIGHTS ISI-002.

I

~5

where

CL
Co
Rs
Cin
Cout

w

0

I

~~)2

=Ug!SUo!SUgil

rtr

'--~lr
LINES

ICM7211
31 32 33

~

22 2324 26

For a specific crystal and load capacitance, the required
gm can be calculated as follows:

gm=w2 CIN COUT Rs ( 1 +

affo~ ~ae SofE e

=¥(] =

~

Os • • Os

ITI

5

5

0

gil

0

lr~-'~
ICM7211

"1''1' 1'"

28n

1,1.1,,1'8

+sv

.l!

LINES

3132 3334

~s

2728 2930
04 • • 0,

ICM1226A

0356-27

Figure 25: 10MHz Universal Counter System with
LCD Display

( CINCOUT )
CIN+COUT
Crystal static capacitance
Crystal Series Resistance
Input Capacitance
Output Capacitance
2'ITf

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUS!VE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not tested.

14-92

ICM7236
4%-Digit Counter/Vacuum
Fluorescent Display Driver
GENERAL DESCRIPTION

FEATURES

The ICM7236 and ICM7236A devices are high-performance CMOS 41jz-digit counters. They include 7-segment decoders, output latches, count inhibit, reset, and leading zero
blanking circuitry, as well as twenty-nine high-voltage open
drain P-channel transistor outputs suitable for driving nonmultiplexed (static) vacuum fluorescent displays.
The ICM7236 is a decade counter, providing a maximum
count of 19999, while the ICM7236A is intended for timing
purposes, and provides a maximum count of 15959.
The counter section of the two devices in the ICM7236
family provides direct static counting from DC to 15MHz
guaranteed (with a 5V ± 10% supply) over the operating
temperature range. At normal room temperatures, the device will typically count up to 25MHz. The COUNT input is
provided with a Schmitt trigger for operation in noisy environments and allows correct counting with slowly changing
inputs. These devices also provide count inhibit, store and
reset circuitry which allow a direct interface to the ICM7207
devices. This results in a low cost, low power frequency
counter with minimum component count.
These devices also incorporate features intended to simplify cascading in four-digit blocks. The CARRY output allows the counter to be cascaded, while the Leading Zero
Blanking INput and OUTput allow correct leading zero
blanking between four-decade blocks.
The ICM7236 and ICM7236A are packaged in a standard
40-pin dual-in-line plastic and CERDIP packages.

• High Frequency Counting - Guaranteed 1SMHz,
Typically 2SMHz at T A - 2S·C
• Low Power Operation - Less Than 100p.W
Quiescent
• Direct 4YrDlgit Seven-Segment Display Drive for
Non-Multiplexed Vacuum Fluorescent Displays
• srmiE and RESET Inputs Permit Operation As
Frequency or Period Counter
• True COUNT INHIBIT Disables First Counter Stage
• CARRY Output for Cascading Four-Digit Blocks
• Schmitt-Trigger On COUNT Input Allows Operation In
Noisy Environments or With Slowly Changing Inputs
• Leading Zero Blanking INput and OUTput for Correct
leading Zero Blanking With Cascaded Devices

ORDERING INFORMATION
ORDER PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

ICM72361JL

-40·C to + 85·C 40-PIN CERDIP

ICM7236AIJL

-40·C to + 85·C 40-PIN CERDIP

ICM72361PL

-40·C to + 85·C 4Q-PIN PLASTIC DIP

ICM7236AIPL

- 40·C to + 85·C 40-PIN PLASTIC DIP

34 STORE
33 iiESEi'
32 COUNT

ICM7236/D

- 40·C to + 85·C DICE

30 LZSOUT

ICM7236A1D

-40·Cto+85·C DICE

ICM7236EVIKIT

EVALUATION KIT

31 COUNT INHIBIT
29 LZBIN

CAiiiiY
1/2·DIGrr
F4

G4

E4
D4
C4
84
0357-1

Figure 1: Pin Configuration

INTERSIL'S SOlE AND EXCLUSIVE WARRANTY DBUGATION WITH REBPECT TO THIS PRODUCT BHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CDNDmDN OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND BHALL BE IN LIEU OF ALL DTHER WARRANTIes. EXPRESS. IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
-002
NOTE: AN typ/cIII vsJuss lis"" bssn _
but 818
14-93

not_

G

&II)
(II

ICM7236

P-

I! ABSOLUTE MAXIMUM RATINGS

2

Power Dissipation (Note 1) .•.•..•..•.••• O.SW @ + 70'C
Operating Temperature Range •••.•.... -40'C to + 8S'C
Supply Voltage (Voo-Vss) ....................... 6.SV
Storage Temperature Range .•.....••. -6S'C to + 1S0'C
Display Voltage (Note 3) .................... Voo - 3SV
Lead Temperature (Soldering, 10sec) ••••.•.•....• 300'C
Input Voltage .•.••.•.•.••.•. (Vss-0.3V) to (Voo+0.3V)
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operationsl sections of the specifications is not imp/ied. Exposure to absolute
maximum rating conditions for extended periods may affect devica reHsbiHty.
DIGIT.
SEGMENT OUTPUTS

DIGIT a
SEGUENT OUTPUTS

DIGIT.
SEGMENT OUTPUTS

DKJIT4
SEGMENT OUTPUTS

112DIQIT
OUTPUT

1---------t------lZ8IN

~800T __------------~

~--------------~
COUNT IN

~------------------~----~----~----~---t--~----~------~----~--~--~
~------------aoow
L-______________________________________

>-,~~~:

0357-2

Figure 2: Functional Diagram

ELECTRICAL CHARACTERISTICS

(Voo = SV, Vss = OV, TA = 2S'C, unless otherwise indicated).

SYMBOL

PARAMETER

VSUPPLY

Operating Supply Voltage Range (Voo-Vss)

100

VOISP
IOLK

TEST CONDITIONS

TYP

MAX

3

S

6

V

Test circuit, Display blank

10

SO

",A

Display Output Leakage

Output OFF, VOISP = Voo - 30V

0.1

Operating Current
Display Voltage
Input Pull up Currents

Pins 29, 31, 33, 34 VIN=Voo-3V

VIH

Input High Voltage

Pins 29, 31, 33, 34

VIL

Input Low Voltage

Pins 29, 31, 33, 34

Ip

UNIT

MIN

30

V

10

",A

10

",A

3

V
2

V

VCT

COUNT Input Threshold

2

V

VCH

COUNT Input Hysteresis

O.S

V

IOH

Output High Current

CARRY (Pin 28), LZB OUT (Pin 30)
VOUT=Voo-3V.

3S0

SOO

",A

IOL

Output Low Current

CARRY (Pin 28), LZB OUT (Pin 30)
VOUT= +3V.

3S0

SOO

",A

fcount

Count Frequency

4.SV-

'A

i-

IZL

I- 1-'/1/
Vj
1/

,,,.""

ICM7238

VDD~I5V ,~*H:m*mR~~

SINE WAVi INPUT
SWINGING FULL SUPPLY

II,

Supply Current as a Function of
Count Frequency

l ..... ZSOC
TESTC:IRCUIT

,

~TA=20'C

v

f'

,

.
,
.

V

~~=26·C

~

f'

...... r-

V

V ~

tL

V

,

0357-4

--

T... -70·C

'-H+tt-+-+++t-t-HWt-tttt-+-+++H

/'

~' V

.

.

SUPPLY VOLTAGE

.

'COUNT

0357-6

VOD - Vss

0357-5

DESCRIPTION OF OPERATION

,_,"

Both devices in the ICM7236 family provide twenty-nine
outputs suitable for directly driving the anode terminals of
4 % digit seven-segment non-multiplexed (statiC) vacuumfluorescent displays. Each display output is the drain of a
high-voltage low-leakage P-channel transistor, capable of
withstanding typically greater than - 35 volts with respect to
Voo. The output characteristics are shown graphically under "Typical Characteristics."
These chips also provide a display ON/OFF input which
may be used to disable all the segment outputs and thus
blank the display. This input may also be used to control the
display brightness by varying the duty cycle of a signal at
the input swinging between Voo and Vss.
Note that these circuits have two terminals for Voo; both
of these pins should be connected to the power supply positive terminal. The double connection is necessary to minimize effects of bond wire resistance with the large total display currents possible.
These chips may also be used to directly drive non-multiplexed common-cathode LED displays, where each segment of the display is driven by one ICM7236 output, and
the common cathode is connected to ground. With a 5V
power supply and a 1.7V LED diode forward voltage drop,
the current in an "ON" segment will be typically 3mA. This
should provide sufficient brightness in displays up to about
0.3" character height.

I

I

,?
_,:::;

'-:
,-'5

(j

-,I
'.J
,_,
Cl

-'

(BLANK)
0357-8

Figure 5: Display Font

COUNTER SECTION
The devices in the ICM7236 family implement a four-digit
ripple-carry resettable counter, including a Schmitt trigger
COUNT input and a CARRY output. Also included is an extra D-type flip-flop, clocked by the carry signal, which controls the half-digit segment driver. This can be used as either a true half-digit or as an overflow indicator. The counter
will increment on the negative-going edge of the signal at
the COUNT input, and the CARRY output will provide a negative-going edge following the count which increments the
counter from 9999 (or 5959) to 10000. Once half-digit flipflop has been clocked, it can only be reset (with the rest of
the counter) by a negative level at the RESET terminal, pin
33. However, the four decades will continue to count in a
normal fashion after the half-digit is set, and subsequent
CARRY outputs will not be affected.

0357-7

Figure 4: Segment Assignment

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are not tested.

14-96

ICM7236
A negative level at the COUNT INHIBIT disables the first
divide-by-two flip-flop in the counter chain without affecting
its clock. This provides a true count inhibit which is not
sensitive to the state of the COUNT input, and prevents
false counts which can result from a normal logic gate forcing the state of the clock to prevent counting.
Each decade is fed directly into a four-to-seven line decoder which generates the seven-segment output code.
Each decoder output corresponds to one-segment terminal
of the device. The output data is latched at the driver. When
the STORE pin is at a negative level, the latches are updated, and when the pin is left open or at a positive level, the
latches hold their contents.
The decoders also include zero detect and blanking logic
to provide leading zero blanking. When the Leading Zero
Blanking INput is floating, or at a positive level, this circuitry
is enabled and the device will blank leading zeroes. When
the Leading Zero Blanking INput is at a negative level, or
the half-digit is set, leading zero blanking is inhibited, and
zeroes in the four digits will be displayed. The Leading Zero
Blanking OUTput is provided to allow cascaded devices to
blank leading zeroes correctly. This output will assume a
positive level only when all four digits are blanked, and can

only occur when the Leading Zero Blanking INput is at a
positive level and the half-digit is not set.
For example, on an eight-decade counter with overflow
using two ICM7236 devices, the Leading Zero Blanking
OUTput of the high-order digit device would be connected
to the Leading Zero Blanking INput of the low-order digit
device. This will assure correct leading zero blanking for all
eight digits.
The STORE, RESET, COUNT INHIBIT, and Leading Zero
Blanking INputs are provided with internal pullup devices,
so that they may be left open when a positive level is desired. The CARRY and Leading Zero OUTputs are suitable
for interfacing to CMOS logic in general, and are specifically
designed to allow cascading of ICM7236 devices in fourdigit blocks.

CONTROL INPUT DEFINITIONS
In this table, Voo
operating input logic
are specified under
power consumption,
supply.

and Vss are considered to be normal
levels. Actual input low and high levels
Operating Characteristics. For lowest
input signals should swing over the full

OPEN·DRAIN HIGH·VOLTAGE P·CHANNEl TRANSISTOR OUTPUTS

\

10·30V

DEP~~ING
ON

.

.-------If'1\~~lm
T

:k:

4·6V

,1
~

Voo

as

DISPLAY

ICM7236

'---

Vso

36

r

IG •

I

bed

•

f

9

L
,->,

PHOSPHOR·COATED

ANODES
GRID

l/' / DIRECT·HEATED
_~ _________ '=-_'=- __ ~t~~:=!~::~~:E

IF-

F-

J11
+1

_

1.S-2.SV TVP

DEPENDING ON DISPLAY

0357-9

Figure 6: Typical DC Vacuum Fluorescent Display Connection
VACUUM FLUORESCENT DISPLAYS (4Y.-DIGIT):
N.E.C. Electronics, Inc.
Model FIP5F8S

II
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been chsrscterized but are not tested.

14-97

~ ICM7240/ICM7250
• Programmable Timer
(II

()

....

::::.
o

(II

:IE

g

GENERAL DESCRIPTION

FEATURES

The ICM7240/50 is a family of CMOS Timer/Counter circuits intended to replace Intersil's ICM8240/50 and the
2240 in most applications. Together with the ICM7555/56
(CMOS versions of the SE/NE 555/6), they provide a complete line of RC oscillators/timers/counters offering lower
supply currents, wider supply voltage ranges, higher operating frequencies, lower component counts and a wider range
of timing components. They are intended to simplify the selection of various time delays or frequency outputs from a
fixed RC oscillator circuit.
Each device consists of a counter section, control circuitry, and an RC oscillator requiring an external resistor and
capacitor. For counter/divider applications, the oscillator
may be inhibited and an input clock applied to the TB terminal. The ICM7240 is intended for straight binary counting or
timing, whereas the ICM7250 is optimized for decimal
counting or timing. Both devices use open drain output transistors, thereby allowing wire AND-ing. Manual programming is easily accomplished by the use of standard thumbwheel switches or hardwired connections. The ICM7240/50
are packaged in 16 pin CERDIP packages.
Applications include programmable timing, long delay
generation, cascadeable counters, programmable counters,
low frequency oscillators, and sequence timing.

•
•
•
•
•

•
•
•
•

Replaces 8240/50, 2240 in Most Applications
Timing From Microseconds to Days
May Be Used As Fixed or Programmable Counter
Programmable With Standard Thumbwheel Switches
Select Output Count From
1RC to 255RC (ICM7240)
1RC to 99RC (ICM7250)
Monostable or Astable Operation
Low Supply Current: 115",A @ 5 Volts
Wide Supply Voltage Range: 2 - 16 Volts
Cascadeable

ORDERING INFORMATION
Part
Number

Temperature
Range

ICM7240lJE

- 25'C to

ICM72501JE

- 25'C to

+ 85'C
+ 85'C

Package
16 Lead CERDIP
16 Lead CERDIP

y.
/N/C(7240)
'CARRY OUT(7250)
181/0

MOD 1"-'- - - - - - - ,

RC
~OD

,c,~,---~--1

32

TRIGGER

64

RESET

0358-22

ICM7240

1--------8

15

0358-1

Figure 1: Functional Diagram
ICM7240/S0

y.

{
10'S[:~

40

/N/C(7240)
'CARRY OUT(7250)
TSI/O
RC
~OD

5

TRIGGER
RESET

80
0358-23

ICM7250
Figure 2: Pin Configurations

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

203403-003

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valuss have be9n charactBflzed but are not testBd.

14-98

ICM7240/lCM7250
ABSOLUTE MAXIMUM RATINGS
Power Dissipation[21 ........................... 200mW
Supply Voltage (Voo-Vss) ........................ 1BV
Operating Temperature Range ......... - 25·C to + B5·C
Input Voltage[11
Storage Temperature Range .......... -65·C to + 150·C
Terminals 10,11,12,13,14 ...... VSS -0.3VtoVoo+0.3V
Lead Temperature (Soldering, 10sec) ............. 30Q·C
Maximum continuous output
current(each output) .......................... 50mA
NOTES: 1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than VDD or less than Vss may cause destructive
device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same supply be applied to the device

2.

before its supply is established. and that in multiple supply systems, the supply to the ICM7240/50 be turned on first.
Derate at - 2mWrc above 25°C.

NOTE: Stresses above those listed under "Absolute Maximum RatIngs" may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating condifjons for extended periods may affect device raliability.

ELECTRICAL CHARACTERISTICS
+ 25·C, R= 10k!!., C=0.1/LF, unless otherwise specilied.)

(Voo=5V, VSs=OV, TA=
Symbol

Test Conditions

Parameter

VSUPPlY

Guaranteed Supply Voltage
(Voo-Vss)

100

Supply Current

Min

Typ

2
125
300
120
125

Reset
Operating, R = 10k!!., C = 0.1 /LF
Operating, R = 1M!!., C = 0.1 /LF
TB Inhibited, RC Connected to GND

Max

Units

16

V

5

/LA
/LA
/LA
/LA
%

(Exclusive 01 RC Drift)

250

ppmrC

ISOURCE= 100/LA
ISINK=1.0mA

3.50
0.40

V

Timing Accuracy

BOO
600

t:..f/t:..T

RC Oscillator Frequency
Temperature Drift

VOTB

Time Base Output Voltage

ITBlK

Time Base Output
Leakage Current

VMOO

Mod Voltage Level

Voo=5V
Voo=15V

3.5
11.0

VTRIG

Trigger Input Voltage

Voo=5V
Voo=15V

1.6
3.5

2.0
4.5

V
V

VRST

Reset Input Voltage

Voo=5V
Voo=15V

1.3
2.7

2.0
4.0

V
V

It

Max Count Toggle Rate
7240

Voo=2V
Counter/Divider Mode
Voo=5V
Voo=15V
50% Duty Cycle Input with Peak to
Peak Voltages Equal to Voo and VSS

Max Counter Toggle Rate
7250

Voo=5V
(Counter/Divider Mode)

It

}

It

Max Count Toggle Rate

Programmed Timer - Divider Mode

VSAT

Output Saturation Voltage

All Outputs except TB Output
Voo=5V,IOUT=3.2 mA
Voo = 5V, per Output

IOlK

Output Leakage Current

Ct

MIN Timing CapaCitor (Note 1)

Rt

Timing Resistor Range (Note 1)

25

RC=Ground

V
V

2

1
6
13

MHz
MHz
MHz

2

5

MHz

0.22

100

kHz

0.4

V

1

/LA
pF

12M
12M

!!.
!!.

10
1K
1K

Voo';;5.5V
Voo,;;16V

/LA

NOTE; 1. For Design only, not tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have be6n characterized but are not tested.

14-99

0

ICM7240/lCM7250

10

...
&\I

:I

@

.....

Yoo

YOD
10K

0

10K

&\I

10K

:I

10K

S!

10K
10K
10K
10K

2

Ne/CARRY

ouf'

3

S1·A=RCRUN
S2·A=INACTIVE S3·A=INACTIVE
B=T.B.INPUT RUN B=TRIGGER
B=RESET
NOTE: SI·B INHIBITS THE TIMEBASE SECTION, ALLOWING
TERMINAL 14 TO BECOME THE COUNTER INPUT.

4

.. TERMINAL 15 IS CARRY OUTPUT FOR 7250 DEVICES.

1100

5
6

7
8

GNO

0358-3

Figure 3: Test Circuit

TYPICAL PERFORMANCE CHARACTERISTICS
RECOMMENDED RANGE OF TIMING COMPONENT
VALUES FOR ACCURATE TIMING

SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE
2~J

I

i

1--'~-'--'-~r-'

-r-;---l---+
220 f·-+--T--+--J.-....c.,.--..,..~7'f---j
200 ;i---+---4
. l----r!---;,::......I"""'==!---I-7'I
240f-

::;

T.I••2O'C

1~~~~~~~~~~~

I lMr--;~~~~~~~~~~~~

:; 180 ~-t-+.·.,c.+---!---f-"...j""'--j

1~ L-.-+1 --+-:A--+::~~":l::=+--1

i I~l--J~~~~~~~~~~~~

1~r-~--~-t.,c.+-~~4-~~~

i1i
~ 1~r--;~~~~~~~~~~~~

z

~I--"'~--+
20

i

~

Ikr-~~~~~~~~~~~~~

16
SUPPL Y VOLTAGE IV)

0358-4
TIMING CAPACITOR. C ("F)
0358-5

TIMEBASE FREE RUNNING FREQUENCY
AS A FUNCTION OF RAND C

MINIMUM TRIGGER PULSE WIDTH AS A
FUNCTION OF TRIGGER AMPLITUDE
1500
1400
1300
.. 1200
~ 1100

A = +25'C

r:

800
700
600
VOD
500
400
S! 300
a:
200
100 Voo = 2V .,..

w
~
a.
a:
w

:::>

"
...
I~Fr-~---+--4-~~~~~~-H--~

o

I~Fr--+--~--t-~~~-+~~+--1
IpF.~~

.1

-- \-~rSI'
I

I

r

,
= 16V

"""-

,

012345678910

__~__~__~__L-~-L-U~~

TRIGGER AMPLITUDE (VOLTS)

lOOK
0358-7

TIME BASE FREQUENCY (Hz)
0358-6

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typical values have been characIsrIzed but 81'8 not tested.

14·100

ICM7240/lCM7250
TYPICAL PERFORMANCE CHARACTERISTICS

(Continued)
NORMALIZED FREQUENCY STABILITY IN THE
ASTABLE MODE AS A FUNCTION OFitEMPERATURE

MINIMUM RESET PULSE WIDTH AS A
FUNCTION OF RESET AMPLITUDE

SUPPL V VOLTAGE (VI

9
R~SET

10
0358-9

AMPLITUDE (VOL TS)

0358-8

MAXIMUM DIVIDER FREQUENCY vs. SUPPLY VOLTAGE'

NORMALIZED FREQUENCY STABILITY IN THE ASTABLE
MODE AS A FUNCTION OF SUPPLY VOLTAGE
+5

I

+4

I

+2

i

1

-1

-2

-3

I

I

+3

I
I

--

-- .......--r

I

,I

I

I

I
I

-4

-5.1
-25

+25

'OOM

I
TA" +25°C
RC CONNECTED ::
rOGROUNO
_

R=loJn+
C=O.I"!;..'" _

...,

=
::::

•

R=lkn:--

c = O'~J.lF

i
I

F=
~

'OK

5V'; VOO'; 15V

o

I
+50

•

== .~~R~~~~:/~~~;g~:~;L~_

-

2

NO PROGRAMMING CONNECTIONS

4

6

8

10

12 14

,. 18

~

SUPPLY VOLTAGE IV)

+75

0358-11

0358-10

OUTPUT SATURATION CURRENT AS A FUNCTION OF
OUTPUT SATURATION VOLTAGE

DISCHARGE OUTPUT CURRENT AS A FUNCTION OF
DISCHARGE OUTPUT VOLTAGE

0.1

O.10:.1:-"L..-'--'"'-"O"'.1-:----~...!..,--'---~.l.;..:Jl0

10

DISCHARGE SATURATION VOLTAGE IV)

OUTPUT SATURATION VOLTAGE IV)

0358-12

0358-13

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE,
NOTE: All typical values have been characterized but are not tested

14-101

•

o ICM7240/lCM7250

;I

...

:I CIRCUIT DESCRIPTION

Vss (PIN 9)

@
Q

~

...
:I
&\I

!:!

This is the return or most negative supply pin. It should
have a very low impedance as the capaCitor discharge and
other switched currents could create transients.

The timing cycle is initiated by applying a positive-going
trigger pulse to pin 11. This pulse enables the counter section, sets all counter ou1puts to the LOW or ON state, and
starts the time base OSCillator. Then, external C is charged
through external R from 20% to 70% of Voo-Vss, generating a timing waveform with period t, equal to 1RC. A short
negative clock or time base pulse occurs during the capacitor discharge portion Of the waveform. These clock pulses
are counted by the binary counter. of the 7240 or by two
cascaded Binary Coded Decimal (BCD) Counters in the
7250. The timing cycle terminates when a positive level Is
applied to RESET. When the circuit is at reset, both the time
base and the counter sections are disabled and all the
counter outputs are at a HIGH or OFF state. The carry-out
is also HIGH. Both devices u1ilize an identical timebase,
control flip-flops, and basic counters, with the outputs consisting of open drain n-channel transistors. Only the
ICM7250 has CARRY outputs.
In most timing applications, one or more of the counter
outputs are connected back to RESET, the circuit will start
timing when a TRIGGER is applied and will automatically
reset itself to complete the timing cycle when a programmed count is completed. If none of the counter outputs
are connectl'ld back to the RESET (switch S1 open), the
circuit operates in its astabie, or free-running mode, after
initial triggering.

RESET AND TRIGGER INPUTS (PINS 10 AND
11)
The circuits are reset or triggered by a positive level applied to pins 10 and 11, and once triggered they ignore additional trigger inputs until either the timing cycle is completed
or a reset signal is applied. If both reset and trigger are
applied simultaneously trigger overrides reset. Minimum inpu1 pulse widths are shown in the typical performance characteristics. Note that all devices feature power ON reset.

MODULATION AND SYNC INPUT (PIN 12)
The period, t, of the time base oscillator can be modulated by applying a,DC voltage to this terminal. The time base
oscillator can be synchronized to an external clock by applying a sync pulse to pin 12. .

TIMEBASE INPUT/OUTPUT PIN (PIN 14)
While this pin can be used as either a time base input or
ou1put terminal, it should only be used as an inpu1 if the RC
pin is connected to Vss.
If the counter is to be externally driven, care should be
taken to ensure that fall times are fast (see Operating Limits
section).
Under no conditions is a 300pF capaCitor on this terminal
useful and should be removed if a 7240/50 is used to replace an 8240/50 or 2240.

DESCRIPTION OF PIN FUNCTIONS
COUNTER OUTPUTS (PINS 1 THROUGH 8)

CARRY OUTPUT (PIN 15, ICM7250 ONLY)

Each binary counter outpu1 is a buffered "open-drain"
type. At reset condition, all the counter outputs are at a
high, or non-conducting state. After a trigger input or when
using the intemal timebase, the outputs change state (see
timing diagram, Figure 4). If an external clock input is used,
the trigger input must overlap at least the first falling edge of
the clock. The counter outputs can be used individually, or
can be connected together in a wired-AND configuration, as
described in the Programming section.

Jl

...._ _ _ _ _ _ _ _ _

-

This pin will go HI for the last 10 counts of a 59 or 99
count, and can be used to drive another 7250 counter stage
while still using all the counter ou1puts of the first. Thus, by
cascading several 7250's a large BCD countdown can be
achieved.
The basic timing diagrams for the ICM7240/50 are shown
in Figure 4. Assuming that the device is in the RESET
mode, which occurs on powerup or after a positive level on
the RESET terminal (if TRIGGER is low), a positive level on
the trigger input signal will initiate normal operation. The
discharge transistor turns on, discharging the timing capacitor C, and all the flip-flops in the counter chain change
states.
Note that for straight binary counting the outputs are symmetrical; that is, a 50% duty cycle HI-La. This is not the
case when using BCD counting. (See Figure 6.)

TRIGGER
INPUT
I. .RMINAL111

~1""1"11""'11-Y1""1-11""'11r-r1~1""1"Ir-- r~:=~:u-r
-

+2 OUTPUT (TERMINAL 1)

-1 .. 1--

PROGRAMMING CAPABILITY

.. 4 OUTPUT (TERMINAL 2)

I--.. ---J
1
I

.

I

1---.. ---1

,.

t=;.!::j.-----4

r
~

The counter outputs, pins 1 through 8, are open-drain Nchannel FETs, and can be shorted together to a common
pull-up resistor to form a "wired-AND" connection. The
combined output will be LOW as long as anyone of the
outpu1s is low. Each output is capable cif sinking;:::: 5mA. In
this manner, the time delays associated with each counter
outpu1 can be summed by simply shorting them together to
a common output. For example, if only pin 6 is connected to
the output and the rest left open, the total duration of the
timing cycle (monostable mode) Ie would be 32t for a 7240
and 20t for a 7250. Similarly, if pins, 1, 5, and 6 were

.1 OUTPUT (TERMINAL 31

+2fi80UTPUT

ITERMINALI;724IIONLVI

0358-14

Figure 4: Tlmlng'Dlagram for ICM7240/50

INTERSIL'S ·SOLE AND EXCLlJSIVE WARRANTY CSLIGATI0i4 WITH RESPECT TO THIS PRODUCT SHALL BE THAT sTATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS, IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AU typ/cIII VBIues ""VB b68n _

but.,. not _ _

14-102

ICM7240/lCM7250
For a single ICM7250 two such switches would select a
time of 1RC to 99RC. Cascading two ICM7250's (using the
carry out gate) would expand selection to 9999RC.

shorted to the output bus, the total time delay would be
to=(l + 16 + 32)tfor the 7240 or (1 + 10+20)t for the 7250.
Thus, by selecting the number of counter terminals connected to the output bus, the timing cycle can be programmed from:
1t,;;to:5:255t (7240)
1t:5:to:5:99t (7250)
Note that for the 7250, invalid count states (BCD
values;;;: 10) will not be recognized and the counter will not
stop.
The 7240/50 can be configured to initiate a controlled
timing cycle upon power up, and also reset internally; see
Figure 5. Applications for this could include lawn watering
sprinkler timing, pump operation, etc.

NOTES ON THE COUNTER SECTION
Used as a straight binary counter (ICM7240), or as a

+ 100 (ICM7250), both devices are significantly faster than
their bipolar equivalents. However, when using these devices as programmable counters the maximum frequency of
operation is reduced by more than an order of magnitude.
For any division ratio other than 256 (ICM7240), or 100
(ICM7250), the maximum input frequency must be limited to
approximately 100kHz or less (with Voo equal to + 5 volts).
The reason for this is two-fold:
a.
Since Ripple counters are used, there is a propagation delay between each individual + 2 counter (8
counters for the ICM7240/50). Outputs from the individual + 2 counters are AND'ed together to provide the output signal and the RESET ITRIGGER
signal.
b.
There must be a delay of the positive going output
to RESET, (pin 10) and TRIGGER (pin 11). The RESET signal must therefore be generated first, and
from this Signal another signal is obtained through a
delay network. The TRIGGER overrides RESET.
The delay between TRIGGER and RESET is generated
by the signal RC network consisting of the 56kO resistor
and the 330pF capacitor.
The delay caused by the counter ripple delays can be as
long as 2,...s (5 volt supply), and the delay between RESET
and TRIGGER should be at least 2,...s. The sum of these
two delays cannot be greater than one-half of the input
clock period for reliable operation. See Figure 7 and 8.

BINARY OR DECIMAL PATTERN
GENERATION
In astable operation, as shown in Figure 5, the output of
the 7240/50 appears as a complex pulse pattern. The
waveform of the output pulse train can be determined directly from the timing diagram of Figure 4, which shows the
phase relations between the counter outputs. Figure 6
shows some of these complex pulse patterns. The pulse
pattern repeats itself at a rate equal to the period of the
highest counter bit connected to the common output bus.
The minimum pulse width contained in the pulse train is
determined by the lowest counter bit connected to the output.

THUMBWHEEL SWITCHES
While the ICM7240 is frequently hard wired for a particular function, the ICM7250 can easily be programmed using
thumbwheel switches. Standard BCD thumbwheel switches
have one common and four inputs (1,2,4 and 8) which are
connected according to the binary equivalent to the digits 0
through 9.
VDD

(7240)

(7250)

10K

r---H 1----00 VDD

OUTPUT
VDD., rVss-L..I

lo~

1-.1

51
PROGRAMMING BY SOLDER CONNECTIONS
OR THUMBWHEEL SWITCHES

*

FOR POWER UP TRIGGERING(lw = 185mB) USE CIRCUIT SHOWN
AND OMIT EXTERNAL PULSE.
0358-15

Figure 5: Generalized Circuit for Timing Applications
(Switch SI open for astable operation, closed for monostable operation)
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typIcsi vs/uBs have been chsracter/ztJd but are not tssted.

14-103

IIlD~OIl.

ICM7240/lCM7250
A

2 PIN PATTERNS

.JLfi.JLJlJl.~
.~ ~ ~8·-L7.--J

.-1 ~ 3. L

PINS 1 81 2 SHORTED t .. RC
B

PINS 1 & 4 SHORTED

3 PIN PATTERNS

1------21.------1
PINS " 3, & 5 SHORTED

C

4PIN PATTERNS

~' Jft~"!l~~
PINS 1, 3, 5, & 7 SHORTED

0358-16

Figure 6: Pulse Patterns Obtained by Shorting Various Counter Outputs

CLOSE
TO INHIBIT
INTERNAL
TIMEBASE

10KO

'--------------+----OUTPUT

0358-17

Figure 7: Programming the Counter Section of the ICM7240/50

TBSIGNAL

OFF
PIN 1

ON

Il

PIN 2 - - - - ,1.._ _ _ _..1

,

' - - - - - - '

I

OFF

ON

I

PIN3 - - - - ,

!-,----------....I

-..ll

I

OUTPUT (RESET)

r

L . ,- - - - - - '

I

OFF

n____________

1.,- - - - - - -

ON

I

,~--------------------------....II..,
I

I

f\..

TRIGGER - - - "

~L-

--ij.O:

RESET TO TRIGGER
RCDELAV

RESET TO TRIGGER
RC DELAY

0358-18

Figure 8: Waveforms for Programming the Counter Section for a Division Ratio of 7 (S1. S2. S3 Closed)
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE,
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typIcsJ valuss haYS been chsracterizsd but are not tested.

14-104

ICM7240/lCM7250
APPLICATIONS
GENERAL CONSIDERATIONS
Shorting the RC terminal or output terminals to VDD may
exceed dissipation ratings and/or maximum DC current limits (especially at high supply voltages).
There is a limit of 50pF maximum loading on the TB I/O
terminal if the timebase is being used to drive the counter
section. If higher value loading is used, the counter sections
may miscount.
For greatest accuracy, use timing component values
shown in the graph under Typical Performance Characteristics. For highest frequency operation it will be desirable to
use very low values for the capacitor; accuracy will decrease for oscillator frequencies in excess of 200kHz.
When driving the counter section from an external clock,
the optimum drive waveform is a square wave with an amplitude equal to supply voltage. If the clock is a very slow
ramp triangular, sine wave, etc., it will be necessary to
"square up" the waveform (rise/fall time';; 1/Ls); this can be
done by using two CMOS inverters in series, operating from
the same supply voltage as the ICM 7240/50.
By cascading devices, use of low cost CMOS AND/OR
gates and appropriate RC delays between stages, numerous sequential control variations can be obtained. Typical
applications include injection molding machine controllers,
phonograph record production machines, automatic sequencers (no metal contacts or moving parts), milling machine controllers, process timers, automatic lubrication systems, etc.
By selection of Rand C, a wide variety of sequence timing can be realized. A typical flow chart for a machine tool
controller could be as follows:

ICM7240

ICM7240

• TRIGGERING CAN BE
OBTAINED FROM A
PREVIOUS STAGE, A

LIMIT SWITCH. OPERATOR SWITCH. ETC.
ICM7240

ICM7240

ICM1240

S!!!TJ

t
WAIT
6 SEC.

It~

I
ENABLE
10 SEC.

WAIT
5 SEC.

COUNT

ENABLE

TO 185

5 SEC.

0358-19

Figure 9

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valU9S have been characterized but are not testsd

14-105

~

ICM7240/lCM7250

~

....

Ii

U

VOo-Vss = + 5 VOLTS DC

::::.

...
o

QUARTZ XTAL

Voo

= 32,788 Hz

18

8

-

11

~

....
Ii
g

14

Voo
330KD

C04080B

10

C04024B

RESET

27pF

12

VSSo-+-_.J

1PULSEIMIN

START

·~~S'2~~____~;;~____- ,

VOOo--o 0'4C04001B

$OK

15K

Voo
S4

S5

10K

l=OFF
O=COUNTING

S~
2 DECADE BCD
THUMBWHEEL SWITCHES

_VOO
BUZZER RESET

$OK

0356-20

Figure 10
The circuit operates as follows:
The time base is first selected with S1 (seconds or minutes), then units 0 - 99 are selected on the two thumbwheel
switches S4 and S5. Finally, switch S2 is depressed to start
the timer. Simultaneously the quartz crystal controlled divider circuits are reset, the ICM7250 is triggered and counting
begins. The ICM7250 counts until the pre-programmed value is reached, whereupon it is reset, pin 10 of the CD4082B
is enabled and the buzzer is turned on. Pressing S3 turns
the buzzer off.

CMOS PRECISION PROGRAMMABLE
0-99 SECONDS/MINUTES
LABORATORY TIMER
The ICM7250 is well suited as a laboratory timer to alert
personnel of the expiration of a preselected interval of time.
When connected as shown in Figure 10, the timer can
accurately measure preselected time intervals of 0 - 99 seconds or 0 - 99 minutes. A 5 volt buzzer alerts the operator
when the preselected time interval is over.

INTERSIL·S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typk;sf values haYS been oharactBlizBd but 81'6 not tested.

14-106

ICM7240/lCM7250
~

Voo

1 MEG
VOO
INTERRUPT
ONE-SHOT

RESET

10..

15K

J1...
..A
"ELAPSED TIME OVER"I
INTERRUPT TO
MICROPROCESSOR

ICM7240IPE
CMOS PROGRAMMABLE BINARY TIMER

VOO

11

TRIGGER
10K

•

.001

~~

~

~ CD4001B

9.1 MEG

13

10

7

•

5

211 314 .1.

11

C04016B
OUAOSWITCH

2

,!!.......o VOO

0.1

~

1

4

3

2 ,

~ I. 11J11

J

• 1.

C04016B
QUAD SWITCH

13

5

6

12

13

5

6

12

5

7

•

11

17

19

21

23

TRIGGER

1,13

RESET

STROBE 2,14

ER
RESET

15K

CD40178

WR FROM MICROPROCESSOR

....
....
~C040001B

3,15

l'

I

3

6

8

10 16 18 20 22

2 417

II,•

C04017B
DECADE COUNTER RESET

,r .b'13
a

VOO

4

DISABLE

~

C04506B
8 BIT LATCH

~OO1

MSB

LSB

J

":"

8 BIT MICROPROCESSOR BUS

0358-21

Figure 11
latch, the third triggers the ICM7240 to begin its timing cycle
and the fourth resets the decade counter.
The ICM7240 then counts the interval of time determined
by the R-C value on pin 13, and the programmed binary
count on pins 1 through 8. At the end of the programmed
time interval, the interrupt one-shot is triggered, informing
the microprocessor that the programmed time interval is
over.
With a resistor of approximately 10Mfi and capacitor of
0.1I-'F, the time base of the ICM7240 is one second. Thus, a
time of 1 - 255 seconds can be programmed by the microprocessor, and by varying R or C, longer or shorter time
bases can be selected.

LOW POWER MICROPROCESSOR
PROGRAMMABLE INTERVAL TIMER
The ICM7240 CMOS programmable binary timer can be
configured as a low cost microprocessor controlled interval
timer with the addition of a few inexpensive CD4000 series
devices.
With the devices connected as shown in Figure 11, the
sequence of operation is as follows:
The microprocessor sends out an 8 bit binary code on its
8 bit I/O bus (the binary value needed to program the
ICM7240), followed by four WRITE pulses into the
CD4017B decade counter. The first pulse resets the 8 bit
latch, the second strobes the binary value into the 8 bit

INTER$IL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT 5T AlEC IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICUlAR USE.
NOTE: All typical values havs been charact9lized but are not tested.

14-107

II

~

C\I

D~DlL

ICM7242

... Long-Range
~ Fixed Timer
GENERAL DESCRIPTION

FEATURES

The ICM7242 is a CMOS timer/counter circuit consisting
of an RC oscillator followed by an 8-bit binary counter. It will
replace the 2242 in most applications, with a significant reduction in the number of external components.
Three outputs are provided. They are the oscillator output, and buffered outputs from the fi: st and eighth counters.

• Replaces The 2242 in Most Applications
• Timing From Microseconds to Days
•
•
•
•

Cascadeable
Monostable or Astable Operation
Wide Supply Voltage Range: 2 -16 Yolts
Low Supply Current: 115,..A @ 5 Yolts

ORDERING INFORMATION
Part Number

Temperature Range

+ 85°C
25°C to + 85°C

- 25°C to

8 pin MINI-DIP

ICM72421JA

-

8 pin CERDIP

ICM7242CBA

O°Cto

+ 70°C

VDD~--~~-----1

VDD08

Package

ICM72421PA

+ 2 OUTPUT

7

+ 128/256 OUTPUT

3

6

TRIGGER

Vss

4

5

RESET

0360-1

8 pin S.O.I.C.

________ ______
~

TBIIO
RC

2

Figure 1: Pin Configuration
(Outline Drawing JA, PAl

~

&OK

18K

RC

0----+-+-1
L---------------f::>O---'" +

2 OUTPUT

2

&OK

L-_______________________-----o

TB 110

8

v~

~

__

~~

______________

~

______

~

0360-2

Figure 2: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterizsd but are not tested.

14-108

IID~Dn..

ICM7242
ABSOLUTE MAXIMUM RATINGS

NOTE: Strsssss above those Hsled under ''Abso/JJts MaxImum Ratings"
may csuse psrmsnenl tismsg6 /0 the device. Thsso Bf9 stress ratings only
and functions/ operation of the devles at these or any other conditions
above those IndIcsIed In the operationsJ sections of the specifications Is not
imp/iBd. Exposure /0 sbsoIuts maximum rating conditions for extended periods may affect devIc8 ra/isbiHty.

SupplyVoltage(VootoVss) ....................... 18V
Input Voltage [1)
Terminals (Pins 5,6,7,8) •.. (VSS -0.3V) to (Voo +0.3V)
Maximum continuous output current
(each output) ................................. 50mA
Power Dissipation(2) ........................... 200mW
Operating Temperature Range
!CM72421 .......................... -25'Cto +85'C
ICM7242C ............................ O'C to + 70"C
Storage Temperature Range .•.....•.. -65'C to + 150'C
Lead Temperature (Soldering, 10sec) ••.•••••...•. 300'C
NOTES: 1. Due to the SCR structure inherent in the CMOS process. connecting any terminal to voltages greeter then VDD or less than Vss may cause destructive

a...
N

..

N

device latchup. For this reesen. It Is reccmmended that no inputs from external seurcas not operating on the same supply be applied to the device
before Its supply Is established and. that in multiple supply systems, the supply to the ICM7242 be turned on first
2. Derate at - 2mWrc above 25'C.

ELECTRICAL CHARACTERISTICS
(Voo=5V, TA= + 25'C, R=10kO, C=0.1p.F, Vss=OV unless otherwise specified.)
Symbol

Teat Conditions

Parameter

Voo

Guaranteed Supply Voltage

100

Supply Current

Min

Typ

2
125
340
220
225

Reset
Operating, R=10kO, C=0.1p.F
Operating, R=1MO, C=0.1p.F
TB Inhibited, RC Connected to Vss

800
600

250

ppm/'C

ISOURCE= 100p.A
ISINK=1.0mA

3.5
0.40

V
V

VOTB

Time Base Output Voltage

ITBlK

Time Base Output
Leakage Current

VTRIG

Trigger Input Voltage

Voo=5V
Voo=15V

VRST

Reset Input Voltage

Voo=5V
Voo=15V

ITRIG,
IRST

Trigger/Reset Input Current

ft

Max Count Toggle Rate

25

p.A

1.6
3.5

2.0
4.5

V
V

1.3
2.7

2.0
4.0

V
V

RC=Ground

}

Voo=2V
Counter/Divider Mode
Voo=5V
Voo=15V
50% Duty Cycle Input with Peak to
Peak Voltages Equal to Voo and Vss

2

10

p.A

1
6
13

MHz
MHz
MHz

VSAT

Output Saturation Voltage

All Outputs except TB Output
Voo=5V,loUT=3.2mA

0.22

ISOURCE

Output Sourcing
Current 7242

Voo=5V
Terminals2&3, VOUT=1V

300

MIN Timing Capacitor (Note 1)

V
p.A
p.A
p.A
p.A

Independent of RC Components

t:.f/t:.T

Timing Resistor Range (Note 1)

16

%

RC Oscillator Frequency
Temperature Drift

Rt

Units

5

Timing Accuracy

Ct

Max

0.4

p.A

10
Voo=2-16V

1K

V

pF
22M

0

NOTE: 1. For Dsslgn only, not tested.
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN typJcsI vaIufts hat18 btIen charBctsrlzsd but are not tssted.

14·109

•

: ICM7242
....~
:Ii
S:!

VDD

L __d-;-""""r--;]b-__-<> TIMEBASE INPUT/OUTPUT
21 (RC 2) OUTPUT

<>----{J

28 (RC 256) OUTPUT

o----C)

ICM
7242

VDD

Jl

1l

• TIMEBASE PERIOD = 1.0RC;
1 SEC. = 1MO x 1~F

0360-3
NOTE: OUTPUTS +2' AND +28 ARE INVERTERS AND HAVE ACTIVE PULLUPS.

Figure 3: Test Circuit

TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

100M

260

I

240

~

80
60
40

J

20

o

o

l-r-

/

a: 140

a:
a
120

~

/

./

160

100

V

I ....l-""'"

180

~

I

TA "-lO°C

220
200

1

RECOMMENDED RANGE OF TIMING COMPONENT
VALUES FOR ACCURATE TIMING

.L

II'
1// V
VI/
IV

."".. TA" +2S"C

l..,j.--".-

TA - +75°C

I
I

I
I

RESET MODE
1

1

10

12

14

16

SUPPLY VOLTAGE (V)

TIMING CAPACITOR, C

0360-4

(~F)

DIMENSIONS IN INCHES ANO MILLIMETERS

0360-5

TIMEBASE FREE RUNNING FREQUENCY
AS A FUNCTION OF RAND C

MINIMUM TRIGGER PULSE WIDTH AS A
FUNCTION OF TRIGGER AMPLITUDE
1500
1400
1300
.. 1200
S. 1100
1000

A

= +25"C

i!:

iw

.

900
800

~ 700

::>

600

VDO = 16V

a: 500
w

co
52

...a:
100pF f--t-,.--r---"'k-'r-'h+-+lrl

400

-

\tr

300
SV
,"
200
I'..
100 VOD = 2V ,...,
0
I
0
2345678910

I T

10pFr--+-~-~-+4-~~~-Hr-4

'P~,~~-~-~-~~L-~-L-UL-,~OM

TRIGGER AMPLITUDE (VOLTS)

0360-7

TIME BASE FREQUENCY (Hz)

0360-6

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE· All typical values have been characterized but are not tested.

14-110

ICM7242
TYPICAL PERFORMANCE CHARACTERISTICS
MINIMUM RESET PULSE WIDTH AS A
FUNCTION OF RESET AMPLITUDE
1500
1400
1300

!

'"....Q

i

w
w

500

...,....

::>

a:

TA

400
300
200
100

i!
~

-26'C

VDD -5V

VD~ -2~

/'

,
!

r-::

V

\.

o

I
I

"

!

9

I

+1

1

-2

-3

--

~-I

C'O}~F

--

l00kn .01 F - -

"-

~,

-6.•

~"

-8.•

-I •.•
2

8

100M

~

~

~

---

ff:

10

12

14

"-

r~

"

~

18

,.

s:

I

I

5V~ VDD'; 15V

+50

1M

I

20

---rI

.-

~

,

TA '+2SOC

--+-

f- --

I
I

!

I

r- - -

~ lOOK

f-

,.K
•

-t-

-I-

'

i

1

1

I
-

i

._6

8

¥

1-

RC CONNECTED'

TO GROUND

l!j

I

I

10M

a:

::E

+25

....I"'o-~~ ~ ,...
.....
"" " ~ ::;,"~':::

MAXIMUM DIVIDER FREQUENCY VS. SUPPLY VOLTAGE

is

1

o

-2.•

I

I

i

~

0360-9

I~-

-4

-5
-25

."

+2.

0360-8

I
I

I

,,,,F-----

lOkn ,OOl~F--- ....
lMU
lkU
.111F
100kSl .001IlF---IOkU .011lF -_ .. --.

10

i
I R"at.ln~
C·O.I~F ~

I

2

_R_ _ _
C_

SUPPLY VOLTAGE IV)

NORMALIZED FREQUENCY STABILITY IN THE ASTABLE
MODE AS A FUNCTION OF TEMPERATURE
+5

!

o :~~

>

I

I

RESET AMPLITUDE (VOLTS)

+3

+4.

ff
S
N

I

VDD -16V

I

.......

o

+4

+8.

~

~

I

/

TA - +2S°C

•
•

+8.

!C
Q

900

800
700
600

•

+'0.

1200
1100
1000

.,w-'

(Continued)

NORMALIZED FREQUENCY STABILITY IN THE ASTABLE
MODE AS A FUNCTION OF SUPPLY VOLTAGE

~--+-

-i

10

12

I
14

16

18

20

SUPPLY VOLTAGE (V)

0360-11

+75

TEMPERATURE ('C)

0380-10

DISCHARGE OUTPUT CURRENT AS A
FUNCTION OF DISCHARGE OUTPUT VOLTAGE

OUTPUT SATURATION CURRENT AS A
FUNCTION OF OUTPUT SATURATION VOLTAGE

i

...!Za:

az

"
...
"«a:
1;1
'"

Cii

is

0.1

10
OUTPUT SATURATION VOLTAGE (V)

OISCHARGE SATURATION VOLTAGE (V)

0380-13

0360-12

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSive AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typics/ values hBV9 N9n chsrsct9liz9d but 8.f'9 not t98tfHt.

14-111

~

1Il0~OI!..

ICM7242

(\I

....

~

OPERATING CONSIDERATIONS

- :a:
". J1I11l: - s

Shorting the RC terminal or output terminals to Voo may
exceed dissipation ratings and/or maximum DC current limits (especially at high supply voltages).
There is a limitation of 50pF maximum loading on the TB
I/O terminal if the timebase is being used to drive the counter section. If higher value loading is used, the counter sections may miscount.
For greatest accuracy, use timing component values
shown in the graph under typical performance characteristics. For highest frequency operation it will be desirable to
use very low values for the capacitor; accuracy will decrease for oscillator frequencies in excess of 200KHz.
When driving the counter section from an external clock,
the optimum drive waveform is a square wave with an amplitude equal to supply voltage. If the clock is a very slow
ramp triangular, sine wave, etc., it will be necessary to
"square up" the waveform; this can be done by using two
CMOS inverters in series, operating from the same supply
voltage as the ICM7242.
The ICM7242 is a non-programmable timer whose principal applications will be very low frequency oscillators and
long range timers; it makes a much better low frequency
oscillator/timer than a 555 or ICM7555, because of the onchip 8-bit counter. Also, devices can be cascaded to produce extremely low frequency signals.
Because outputs will not be AND'd, output inverters are
used instead of open drain N-channel transistors, and the
external resistors used for the 2242 will not be required for
the ICM7242. The ICM7242 will, however, plug into a socket
for the 2242 having these resistors.
The timing diagram for the ICM7242 is shown in Figure 4.
Assuming that the device is in the RESET mode, which occurs on powerup or after a positive Signal on the RESET
terminal (if TRIGGER is low), a positive edge on the trigger
input signal will initiate normal operation. The discharge
transistor turns on, discharging the timing capacitor C, and
all the flip-flops in the counter chain change states. Thus,
the outputs on terminals 2 and 3 change from high to low
states. After 128 negative timebase edges, the + 28 output
returns to the high state.
To use the 8-bit counter without the timebase, terminal 7
(RG) should be connected to ground and the outputs taken
from terminals 2 and 3.

n

~ "'""-,---------

TrT' I I I I II I I I

-u-L~

l.-.~~
1--128RO--l--128R0---1

_

3A(V+)
14(V+)

0360-15

Figure 5: Using the ICM7242 as a
Ripple Counter (Divider)
The ICM7242 may be used for a very low frequency
square wave reference. For this application the timing components are more convenient than those that would be required by a 555 timer. For very low frequenCies, devices
may be cascaded (see Figure 6).

0360-16

Figure 6: Low Frequency Reference (OSCillator)
For monostable operation the + 28 output is connected
to the RESET terminal. A positive edge on TRIGGER initiates the cycle (NOTE: TRIGGER overrides RESET).
The ICM7242 is superior in all respects to the 2242 except for initial accuracy and oscillator stability. This is primarily due to the fact that high value p - resistors have been
used on the ICM7242 to provide the comparator timing
points.

OUTPUT

-.----1=1

TRIGGER INPUT
(TERM'NAL 6)
TlMEBASE OUTPUT

(TERMINAL 8)

_ ..

TRIGGER

2 OUTPUT (TERMINAL 2)

+ 128/256 OUTPUT
(TERMINAL 3) (ASTABLE
OR "FREE RUH" MODE)

TB OUTPUT

.... '281256 OUTPUT

OUTPUT

(TERMINAL 3) (MONOSlASLE
OR "ONE SHOT" MODE)

-.
111111111TJ='.

---.fl. . ___-:::=

'--P'

TERMINAL 6

TERMINAL 8

TERMINAL 3

0360-17

Figure 7: Monostable Operation

0360-14

Figure 4: Timing Diagrams of
Output Waveforms for the ICM7242_
(Compare with Figure 8)
INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

14-112

ICM7242
By selection of Rand C, a wide variety of sequence timing can be realized. A typical flow chart for a machine tool
controller could be as follows:

COMPARING THE ICM7242 WITH THE
2242
ICM7242

2242
leM 7242

.eM 7242

2-16V
4-15V
a. Operating Voltage
b. Operating Temp.
- 25'C to + 85'C O'C to + 70'C
Range
c. Supply Current
7mAMax.
O.7mAMax.
Voo=5V
d. Pullup Resistors
TB Output
No
Yes
+2 Output
No
Yes
+256 Output
No
Yes
3.0MHz
O.5MHz
e. Toggle Rate
f. Resistor to Inhibit
No
Yes
Oscillator
g. Resistor in Series
with Reset for
Monostable Operation
No
Yes
h. Capacitor TB
Terminal for
No
Sometimes
HF Operation

ICM7~2

~

I t I
WAIT

ENABLE

WAIT

5 SEC.

10 SEC.

5 SEC.

COUNT
TO 185

ENABLE
5BEC.

0360-18

Figure 8
By cascading devices, use of low cost CMOS AND/OR
gates and appropriate RC delays between stages, numerous sequential control variations can be obtained. Typical
applications include injection molding machine controllers,
phonograph record production machines, automatic sequencers (no metal contacts or moving parts), milling machine controllers, process timers, automatic lubrication systems, etc.

SEQUENCE TIMING
eproce.. Control
eMachlne Automation

eElectro-Pneumatlc Drive,.
eMultl-Operellon (Serial or Parallel Controlling)

-..

~E!fl...

VDO

10K

PUSH", TO START SEQUENCe:

-i I---

MUST BE SHORTER THAN «ON It....,,"

1'---_______________________•

r1
TRIGGER --1

DESIRED ''ON time"

-

FOR EACH ICII72G

SELECT He VALUES TO

OUTPUTA_l~·"·C----li

OUTPUTI- ____~----------__,~.H~~~---------------I
I
I
OUTPUTC--+I--+I------iLJi - - - . . C~I
OUTPUT.- __~-------+--------~.~-_,~
I
I
I
I-....C-I

.

D

1

I--ON .....

I

ON -.--J.oN .moc-j--ON ..... --j

0360-19

Figure 9: Sequence Timer

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHEA WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical valuss havs been charscterized but are not tested.

14-113

: ICM7249
(\I

.... 5% Digit LCD ,u-Power
~ Event/Hour Meter
GENERAL DESCRIPTION

FEATURES

The ICM7249 Timer/Counter is intended for long-term
battery-supported industrial applications. The ICM7249 typically draws 1/LA during active timing or counting, due to
Intersil's special low-power design techniques. This allows
more than 10 years of continuous operation without battery
replacement. The chip offers four timing modes, eight
counting modes and four test modes.
The ICM7249 is a 48-lead device, powered by a single DC
voltage source and controlled by a 32.768kHz quartz crystal. No other external components are required. Inputs to
the chip are TTL-compatible and outputs drive standard
LCD segments. The chip is available in dice and in ceramic
side-brazed packages.

• Hour Meter Requires Only 4 Parts Total
• Mlcropower Operation: < 1/LA at 2.8V Typical
• 10 Year Operation On One Lithium Cell
2% Year Battery Life With Display Connected
• Directly drives 5% Digit LCD
• 14 Programmable Modes of Operation
• Times Hrs., 0.1 Hrs., .01 Hrs., .1 Mins.
• Counts 1's, 10's, 100's, 1000's
• Dual Funtion Input Circuit:
-Selectable Debounce for Counter
-High-Pass Filter for Timer
• Direct AC Line Triggering With Input Resistor
• Winking "Timer Active" Display Output
• Display Test Feature

BoIC.

DT

F.

SIS (START/STOP)

G.

C, (CONTROL INPUT)
C, (tONTROL INPUT)
C, (CONTROL INPUT)
Co ICONTROL INPUT)
GND
OSC OUTPUT
DSC INPUT

E.
D.
C.

B.
A.
F.
G.
E.
D.
C.
B.
A.
F,
G,
E,
D,
C,

B,
A,

C,

f,

D,
E,

AC or DC Hour Meters
AC or DC Totalizers
Portable Battery Powered Equipment
Long Range Service Meters

ORDERING INFORMATION

VDD

BP (BACKPLANE)
W(WINK)
A,
B,
C,
D,
E,
G,
F,
A,
B,

G,

APPLICATIONS
•
•
•
•

Temperature Range
-40°C to

+ 85'C

Package
48-Pin Ceramic

0362-1

Figure 1: Pin Configuration

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTiES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
203500-004

NOTE: All typical values have been characterized but are not tested,

14-114

ICM7249
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ......•........•....•............... 6V
Input Voltage
Pins 43-48 (Note 1) ......•.. (Vss -O.3V) to (Voo +O.3V)
Power Dissipation (Note 2) ..................... 200mW
Operating Temperature Range ........... -40"C to 85°C
Storage Temperature Range ............ - 65°C to 150"C
Lead Temperature (Soldering, 10sec) .••.......... 300"C

NOTE: Stress9s .sboV9 thoss Usted umkJr "Absolut9 MaxImum Ratings"
may CBUSiI p6fmBnsnt damage to /he device• .Thsse are stress ralfngs only
and fUnctional operallon of /he device at thBsB or any other conditions
sboV9 thoss Indicated In /he operatlonsJ SBCtions of the spec/flcallons Is not
Implied. Exposure to absolute rnsxJmum rating conditions for BXI8ndtJd pariods may aff8ct device raIiabiJity.

0362-2

Figure 2: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typIcsI values havs been charactfJriZfId but III'fI not tested.

14·115

GI
'It

ICM7249

(If

....

ELECTRICAL CHARACTERISTICS Temperature = -40'Cto + 85'C, VDD = 2.5V to 5.5V, Vss=OV, unless
B_ otherwise
noted. Typical specifications measured at temperature = 25'C and VDD = 2.8V unless otherwise noted.
Symbol

Limits

Test Conditions

Parameter

Min
2.5

VDD

Operating Voltage

Note 3

IDD

Operating Current

Note 4, All inputs = VDD or GND
VDD=2.8V
VDD=5.5V

Input Current:
CO-C3,

liN
ISS
IDT

All Inputs VDD or GND
VDD=2.8V
Note 5

SIS
DT
Input Voltage:
CO-C3, DT, SIS

VIL
VIH
VOL
VOH

Segment Output Voltage

VOL
VOH

Backplane Output Voltage

IOL = 1p.A
IOH=1p.A
IOL =1O",A
IOH=10",A

•

0.0
0.5
40.0

Units
Max
5.5

V

1.0
4.0

10.0
20.0

p.A
p.A

1.5

1
3.0
110

p.A
p.A
p.A

0.3VDD

V
V

0.8

V

0.8

V

0.7VDD
VDD - 0.8
VDD - 0.8

Oscillator Stability:
Temp. = 25'C, VDD = 2.5V to 5.5V
Temp. = -40'Cto + 85'C,
VDD = 2.5V to 5.5V

-

Typ

0.1

ppm

5

ppm

SIS Pulse Width:
High-pass Filter (Modes 0-3)
Debounce (Modes 4, 6, 8, 10)
w/o Debounce (Modes 5, 7, 9, 11)

THP
TDE
TDE

5
10,000
5

10,000

",s

"'",5S

NOTES: 1. Due to the seR structure inherent in junction-isolated CMOS devices, the circuit can be put in a latchup mode if large currents are injected into device
inputs or outputs. For this reason special care should be taken in a system with multiple power supplies to prevent voltages being applied to inputs or
outputs before power is applied. If only inputs are affected, latchup also can be prevented by limiting the current into the input terminal to less than
2.
3.
4.
5.

1~

I

This limit refers to that of the package and
I not occur during normal operation.
Internal reset to 00000 requires a maximum VDO rise time of 1J.Ls. Longer rise times at power~up may cause improper reset.
Operating current is measured with the LCD disconnected, and input current Iss and lor supplied externally.
Inputs CO~C3 are latched internally and draw no DC current after switching. During switching, a 90j.tA peak current may be drawn for 10 nanoseconds.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FDA A PARTICULAR USE.
NOTE: All typ/csJ values havs been charactBrized but are not t9sted.

14-116

ICM7249
Table 1. Pin Assignment and Function
Pin

Table 1. Pin Assignment and Function (Continued)

Name

Description

1

Bs/Cs

Half-digit LCD segment output.

2

F5

38

BP

Backplane for LCD reference.

v+
ascI
asco

Positive supply voltage.
Quartz Crystal
connections
Chip GRouND.

3

Name

Pin
37

Description
Wink-segment output.

W

G5

39

4

E5

40

5

D5

41

6

C5

42

GND

7

B5

43

Co

8

A5

44

C1

9

F4

45

C2

10

G4

46

C3

11

E4

Seven-segment

47

SIS

Start I Stop

D4

LCD outputs.

48

DT

Display Test

12
13

C4

14

B4

15

A4

16

F3

17

G3

Table 2. Mode Select Table
Mode

Control Pin Inputs
C2

C1

Co

0

0

0

0

0

1 hour interval timer

0

0

0

1

0.1 hour interval timer

1

0

0.01 hour interval timer
0.1 minute interval timer

18

E3

19

D3

2

0

0

20

C3
B3

Function

C3

1

21

Mode-select
control inputs.

3

0

0

1

1

4

0

1

0

0

l's counter with debounce

0

1

0

1

l's counter

1

1

0

10's counter with debounce

22

A3

5

23
24

F2
G2

6

0

7

0

1

1

1

1O's counter

25

E2

8

1

0

0

0

1OO's counter with debounce

26

D2

9

1

0

0

1

1OO's counter

27

C2

10

1

0

1

0

1000's counter with debounce

28

B2

11

1

0

1

1

1000's counter

29

A2

12

1

1

0

0

Test display digits

30

F1

13

1

1

0

1

Internal test

31

G1

14

1

1

1

0

Internal test

32

E1

15

1

1

1

1

Reset

33

D1

34

C1

35

B1

36

A1

INTERS1L'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE- All typical values have been characterized but are not I9sl9d.

14-117

1I0~OIl

~

ICM7249

~

DETAILED DESCRIPTION

...""

frequency between 40Hz and 50Hz has an indeterminate
effect on the timing.
The timing intervals are different for each mode. For example, in Mode 0 the display is incremented every hour,
while in Mode 3 the display is incremented every tenth of a
minute.
While timing is active, the wink-segment output W will
flash, as seen in Figure 1. On the upward transistion of SIS,
the wink output turns off. It remains off for 16 backplane
cycles and turns back on for another 16 cycles. If timing is
still active, the wink segment repeats this process, giving it
a flash rate of 1Hz: otherwise the wink output remains on
until timing begins again. In counting modes 4-11, the count
is registered and latched on each positive transition of SIS.
The display is keyed to the specific counting mode. In the
1's counter mode, the display is incremented for each
count; in the 10's counter mode, the display is incremented
after every tenth count.

After power is applied, the ICM7249 requires a rise time
of tR to become active and for oscillation to begin, as seen
in Figure 3. Initially the backplane output BP is a logic '1'
level, but then changes after every 512 crystal oscillation
cycles, giving BP a square-wave frequency of 32Hz. Segments are turned off when the voltage levels of the segment drive pins are the same as and in phase with BP.
Segments are turned on by having the drive pin voltages out
of phase with BP.
The 16 modes are selected by placing the binary equivalent of the mode number on inputs CO-C3 (Table 2). In the
four timer modes, timing is controlled by the StartlStop input SIS. Because of internal high-pass filtering, timing is
active when either SIS is held high for more than 25ms, or
the input signal has a frequency of at least 50Hz and less
than 120kHz as shown in Figure 4. Driving SIS with an input

((

jJ

~
I
fo 14

OSCo ----r-...J

OlE % BACKPLAIE CYCLE
32.788KHz

511 512

BP

~~~"~----------------~I
WPM
~ faP

ss----r

I

- 32Hz

I

SEG~~m%\\~

fSEG

= 32Hz

S~

SEG::m 11////;)I

0362-3

Figure 3: Power On/Reset Waveforms

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE' All typ;cs/ values have been charactetiz8d but are not tested.

14-118

ICM7249
SIS

~TIMING ACTIVE DURING INTERVAj'

VALID

.-------------

_ t > 25ms ---'l~

~
TlMING

INDETERMINATE DURING INTERVAL

.....1

SIS
INVALID

-------1

~Thp

40Hz

< f < 50Hz

------

I.- TIMING ACTIVE DURING INTERVAL

-+-I J.- Thp
SIS
VALID - - - - - - - . . . . . ,
0362-4

Figure 4: Start/Stop Input Hlgh·Pass Filtering In Timing Modes

_________

~~,~---~----------~---------~-(~J~T-IM-I-N-G-~_T_W_E:::::::::::::::::~~1.------

SIS

BP

w

ON
SEGMENTS

OFF
SEGMENTS
0362-5

Figure 5: Wink Waveforms In Timing Modes

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE OONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typicalllsJuss havs been charact8fized but are not test6d.

14-119

: ICM7249

...
(III

~

During counting, the display will wink off at each count
input regardless of whether the display is incremented.
When a count occurs, the wink segment output turns off at
the end of the 16th BP cycle and turns back on at the end of
the 32nd BP cycle, creating a half-second wink, as shown in
Figure 6. If counting occurs more frequently than once a
second, the wink output will default to a constant 1Hz flash
rate.
In counter modes 4,6,8 and 10, the count pulse is subject to debounce filtering. Figure 7 shows that only pulses
with a frequency of less than 40Hz are valid. Pulses with a
frequency between 50Hz and 120kHz are ignored,· while
those with a frequency between 40Hz and 50Hz have an
indeterminate effect on the count.

SiS

The display may be tested at any time without disturbing
operation by pulsing DT high, as seen in Figure 8. On the
next positive transition of BP, all the segments turn on and
remain on until the end of the 16th BP cycle. This takes a
half-second or less. All the segments then tum off for an.
additional 48 BP cycles (the end of the 64th cycle), after
whicl) valid data returns to the display. As long as DT is held
high, the segments will remain on.
Additional display testing is provided by using mode 12. In
this mode each displayed decade is incremented on each
positive transition of SIS. Modes 13 and 14 are for manufacturer testing only.
Mode 15 resets all the decades and internal counters to
zero, essentially bringing everything back to power-up
status.

--f'

BP

w
0362-6

Figure 6: Wink Waveforms In Counting Modes

COUll WITH OR WITHOUT OEIOUIC:I
----{

SIS
VAllO

~-------------COUll WITHOUT OEBOUICE

t> 26_

UIIKIIOWII RESULTS WITH DEBOUIiCE

SIS - - - - - - - . . ,
IIIVALID

40Hz

<

f.

< 50Hz
COUIIT WITHOUT DEIOUIICE
110 COUll WITH DEIOUIICE

SIS _ _ _ _ _ _ _,.UIUUIU
50Hz ~ f. < 120Hz

VALID

0382-7

Figure 7: Start/Stop Input Debounce Filtering In Counting Modes

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHAll BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPUED WARRANnES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE:AII/yp/cB/_ho""bssn_bulllfBnottostsd.

14-120

ICM7249

BP

I

OT

ALL

n,

I~

__________

I ALL SEGMENTS ON
~~G::NO~~ "::\\\~\\\\\~~"~"\
\'"\\\\'"\\'1~~
~\ffi\ \~\~\~ Ir-\.' - - 'I

t

~I

____________-LI
I ___________

I ALL SEGMENTS OFF
I

\

I DISPLAY RESTORED

fIII.I///I///II//I/I////1/4

r-\.
",)-J'
,

0362-8

Figure 8: Display Testing
The .3V !ithiu~ battery ca~ be. replaced without disturbing
If a SUitable capacitor IS connected in parallel with
It. The display should be disconnected, if possible, during
the procedure to minimize current drain. The capacitor
should be large enough to store charge for the amount of
time needed to physically replace the battery (at = a VCII).
A 100"F capaCitor initially charged to 3V will supply a current of 1..0"A. for 50 s~~onds before its voltage drops to
2.5V, which IS the minimum operating voltage for the
ICM7249.
Before the battery is removed, the capacitor should be
placed in parallel, across the VDD and GND terminals. After
the battery is replaced, the capacitor can be removed and
the display reconnected.

APPLICATION NOTES

?peratlo~

A typical use of the ICM7249 is seen in Figure 9, the
Motor Hour Meter. In this application the ICM7249 is configured as a~ hours-in-use meter and shows how many whole
hours of line voltage have been applied. The 20M!) resistor
and high-pass filtering allow AC line activation of the SIS
input. This configuration, which is powered by a 3V lithium
cell, will operate continuously for 2% years. Without the display,. which only needs to be connected when a reading is
reqUired, the span of operation is extended to 1 years.
When the ICM7249 is configured as an attendance counter, as shown in Figure 10, the display shows each increm~nt. ~y using mode 2, external debouncing of the gate
SWitch IS unnecessary, provided the switch bounce is less
than 35ms.

°

LCD

/8:88:88
W

BP

At -

B./C.
OSC t

32.76BkHz
CRYSTAL

D

ICM7249

oseo
DT

+3V Li

L----4--------~~

DISPLAY
TEST
0362-9

Figure 9: Motor Hour Meter

~i~~~;~~T~~~:r~~~fs~~~ri~::~~~r~~% ~:~~ ~~S:~~TO~~;~I~=~~~~~:H;;;:E~~~~~p~~:;EgR'Ns;~;U~~~~~~'6L~~~~L~~: 1~~~,~N~~~~~~:rE~~F
NOTE: All typical values have been characterized but are not tested.

14-121

: ICM7249
&\I
....

a

LCD

18888
+3VTO +24V DC

",

20KO

GATE

f'

W

BP

V

A, -

'38
32.7881cHz

Be/C.

SIS

OSC,

ICM7249
OSe..

¥DD

Vss

Co C, C. C.

CRYSTAl

a
T

OT

j

H:!v

li
-"-

~

DISPLAY
TEST

0362-10

Figure 10: Attendance Counter

INTeRSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TID THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE Of THE CONDITION Of SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AU typ/cOIvsJuss l1li .. _

chIIrac_ but.,. not tostsd.

14-122

ICM7555/ICM7556
General Purpose Timer
GENERAL DESCRIPTION

FEATURES

The ICM7555/6 are CMOS RC timers providing significantly improved performance over the standard
SE/NE555/6 and 355 timers, while at the same time being
direct replacements for those devices in most applications.
Improved parameters include low supply current, wide ;erating~ voltage range, low THRESHOLO, TRIG ER
and F1ESEi' currents, no crowbarring of the supply current
during output transitions, higher frequency performance and
no requirement to decouple CONTROL VOLTAGE for stable operation.
Specifically, the ICM7555/6 are stable controllers capable of producing accurate time delays or frequencies. The
ICM7556 is a dual ICM7555, with the two timers operating
independently of each other, sharing only V+ and GNO. In
the one shot mode, the pulse width of each circuit is precisely controlled by one external resistor and capacitor. For
astable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled by two
external resistors and one capacitor. Unlike the regular bipolar 555/6 devices, the CONTROL VOLTAGE terminal
need not be decoupled with a capacitor. The circuits are
triggered and reset on falling (negative) waveforms, and the
output inverter can source or sink currents large enough to
drive TTL loads, or provide minimal offsets to drive CMOS
loads.

• Exact Equivalent In Most Cases for SEINE555/556 or
TLC555/556
• Low Supply Current - 60,...A Typ. (ICM7555)
120,...A Typ. (ICM7556)
• Extremely Low Trigger, Threshold and Reset
Currents - 20pA Typical
• High Speed Operation -1MHz Typical
• Wide Operation Supply Voltage Range Guaranteed 2
to 18 Volts
• Normal Reset Function - No Crowbarrlng of Supply
During Output Transition
• Can Be Used With Higher Impedance Timing
Elements Than Regular 555/6 for Longer RC Time
Constants
• Timing From Microseconds Through Hours
• Operates In Both Astable and Monostable Modes
• Adjustable Duty Cycle
• High Output SourcelSlnk Driver Can Drive TTLI
CMOS
• Typical Temperature Stability of 0.005% Per °C at
25°C
• Outputs Have Very Low Offsets, HI and LO

APPLICATIONS

ORDERING INFORMATION
Part
Number
ICM7555CBA
ICM75551PA
ICM75551TV
ICM7555MTV*
ICM75561PO
ICM7556MJO*

Temperature
Range

•
•
•
•
•
•
•

Package

O°Cto +70°C
8 LeadSOIC
- 25°C to + 85°C
8 Lead MiniOip
- 25°C to + 85°C
TO-99 Can
- 55°C to + 125°C TO-99 Can
- 25°C to + 85°C
14 Lead Plastic OIP
- 55°C to + 125°C 14 Lead CEROIP

Precision Timing
Pulse Generation
Sequential Timing
Time Delay Generation
Pulse Width Modulation
Pulse Position Modulation
Missing Pulse Detector

• Add 18838 to part number if 8838 processing is desired.

v· •
OUTPUT
.........MOLD

:;CONT;';OO;L=tr
VOLTAGI

'iiiGoii

'0---+-11".....
COMPMATQfII

•

0363-1
This Functional Diagram reduces the circuitry down to its simplest equivalent components. Tie down unused inputs. R ~ 100kll, ± 20% typo

Figure 1: Functional Diagram

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHAll BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIeS. EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical vsluss have been characterized but ars not test6d.

14-123

II

CD

10
10

...

ICM7 SSS/ICM7 556

::I ABSOLUTE MAXIMUM RATINGS

()

::::
10
10
10

...
::I

g

NOTE:

Supply Voltage ............................. + 18 Volts
Input Voltage: Trigger.
Control Voltage. Threshold •...... v+ +O.3V to v- -O.3V
Reset
Output Current ................................ 100mA
Power Dissipation[21 lCM7556 .................. 300mW
ICM7555 ................................... 200mW
Storage Temperature ................ -65'C to + 150'C
Lead Temperature (Soldering. 1Osee) ........... + 300'C
Operating Temperature Range[21
ICM7555XC ........................... O'C to + 70'C
ICM7555XI ........................ - 25'C to + 85'C
ICM7555XM ...................... - 55'C to + 125'C

Stresses above those listed under "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not
implied. Exposuf9 to absolute maximum rating conditions for extended peri-

ods may affect device reliability.

v+ AND CASE

v+
(OUTLINE DRAWING TV)
OUTPUT
GND

iiiiiiiR

2

RESET

DISCHARGE

OUTPUT

THRESHOLD
CONTROL
VOLTAGE

THRESHOLD
CONTROL

iiiiii

0363-3

VOLTAGE

(OUTLINE DRAWING BA)

(OUTLINE DRAWING PAl

DISCHARGE
THRESHOLD
CONTROL

2

DISCHARGE

THRESHOLD

V0!.IA!!l.
RESET
OUTPUT

iiiiiiiR •

11

10
•

....... •

~8~i:g~
iiiiiT
OUTPUT

TiiiiGiii

'--~
(OUTLINE DRAWING JD, PDI

0363-2

Figure 2: Pin Configuration
(Top View)

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characteriz9(i but are not test9d.

14-124

ICM7 555/ICM7 556
ICM7555
ELECTRICAL CHARACTERISTICS
ICM7555C,I,M
Symbol

Parameter

Test Conditions

TA=25'C
Min Typ Max

1+

ICM7555M

-55'CS;TAS;
Min

Typ

+ 125'C

Units

Max

Static Supply
Current

Voo=5V
Voo=15V

40
60

Monostable Timing
Accuracy

RA=10k, C=0.1",F, Voo=5V

2

Drift with Temp'

Voo=5V
Voo=10V
Voo=15V

150
200
250

150
200
250

ppm/'C
ppm/'C
ppml'C

Drift with Supply'

Voo=5 to 15V

0.5

0.5

%/V

200
300

",A
",A

1161

"'S

%
858

Astable Timing Accuracy RA=RB=10k,C=0.1",F, Voo=5V

300
300

2
1717

2323

%
",s

Drift with Temp'

Voo=5V
Voo=10V
Voo=15V

150
200
250

150
200
250

ppml'C
ppml'C
ppml'C

0.5

0.5

%IV

Drift with Supply'

VOO=5V to 15V

VTH

Threshold Voltage

Voo=15V

62

67

71

61

72

O/OVoo

VTRIG

Trigger Voltage

Voo=15V

28

32

36

27

37

%Voo

ITRIG

Trigger Current

Voo=15V

10

50

nA

ITH

Threshold Current

Voo=15V

10

50

nA

Vcv

Control Voltage

Voo=15V

62

O/OVoo

VRST

Reset Voltage

Voo=2to 15V

0.4

IRST

Reset Current

Voo=15V

lOIS

Discharge Leakage

Voo=15V

VOL

Output Voltage
Drop

Voo=15V,l sink=20mA
VOO = 5V, Isink = 3.2mA

VOH

Output Voltage
Drop

Voo= 15V, Isource=0.8mA
Voo=5V,lsource=0.8mA

VDlS

Discharge Output
Voltage Drop

Voo=5V,ISINK=15mA
Voo=15V,l sink=15mA

67

71

61

72

1.0

0.2

1.2

V

50

nA

10

50

nA

1.0
0.4

1.25
0.5

V
V

10

0.4
0.2
14.3 14.6
4.0 4.3
0.2

14.2
3.8

V
V

0.4

V+

Supply Voltage'

Functional Oper.

tR

Output Rise Time'

RL= 10M, CL= 10pF, Voo=5V

75

75

tF

Output Fall Time'

RL= 10M, CL= 10pF, Voo=5V

75

75

fMAX

Oscillator Frequency'

Voo=5V, RA=470n,
RB=270n C=200pF

2.0

18.0

1

2.0

1

0.6
0.4

V
V

18.0

V
ns
ns
MHz

*These parameters are based upon characterization data and are not tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIeD WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE' All typical values have been characterized but are not fest8(/.

14·125

II

= ICM7 555/ICM7 556
...

1ft

~ ICM7556
Mi ELECTRICAL CHARACTERISTICS

TA = 25°C, unless otherwise specified.

1ft
1ft

...
:I

Symbol

Parameter

Test Conditions

S:!

ICM75561,M

ICM7556M

TA=25"C

-55"C';;:TA';;: + 125"C

Min Typ Max
1+

Min

Typ

80 400
120 600

Units

Max
600
600

/l-A
/l-A

1161

/l-s

Static Supply
Current

Voo=5V
Voo=15V

Monostable Timing
Accuracy

RA= 10k, C=0.1/l-F, Voo=5V

Drift with Temp·

Voo=5V
Voo=10V
Voo=15V

150
200
250

150
200
250

ppmrc
ppmrc
ppmrc

0.5

0.5

O/ON

0/0

2
858

Drift with Supply'

Voo=5Vto 15V

Astable Timing
Accuracy

RA=RB=10k, C=0.1/l-F, Voo=5V

Drift with Temp·

Voo=5V
Voo=10V
Voo=15V

150
200
250

150
200
250

ppmrc
ppmrc
ppmrc

Drift with Supply·

Voo=5Vto15V

0.5

0.5

0/0 V

VTH

Threshold Voltage

Voo=15V

62

67

71

61

72

0/0 Voo

VTRIG

Trigger Voltage

Voo=15V

28

32

36

27

37

0/0 Voo

ITRIG

Trigger Current

Voo=15V

10

50

nA

ITH

Threshold Current

Voo=15V

10

50

nA

Vcv

Control Voltage

Voo=15V

62

0/0 Voo

VRST

Reset Voltage

Voo=2Vto 15V

0.4

IRST

Reset Current

Voo=15V

lOIS

Discharge Leakage

Voo=15V

VOL

Output Voltage
Drop

Voo=15V,l sink=20mA
Voo=5V,l sink=3.2mA

VOH

Output Voltage
Drop

Voo= 15V,lsource=0.8mA
Voo=5V,lsource=0.8mA

VOIS

Discharge Output
Voltage Drop

Voo=5V,l sink=15mA
Voo=5V,l sink=15mA

V+

Supply Voltage·

Functional Oper.

tR

Output Rise Time·

RL=10M, CL=10pF, Voo=5V

75

75

ns

tF

Output Fall Time·

RL= 10M, CL= 10pF, Voo=5V

75

75

ns

fMAX

Oscillator Frequency· Voo=5V, RA=4700,
RB=2700, C=200pF

1

1

MHz

0/0

2
2323

1717

67

0.4
0.2

71

61

72

1.0

0.2

1.2

V

10

50

nA

10

50

nA

1.0
0.4

1.25
0.5

V
V

14.3 14.6
4.0 4.3
0.2
2.0

/l-s

V
V

14.2
3.8
0.4
18.0

2.0

0.6
0.4

V
V

18.0

V

'These parameters are based upon characterization data and are not tested.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBUGATION WITH RESPECT TO THIS PRODUCT SHAll. BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SAUE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF All. OTHER WARRANTIES. EXPRESS. IMPUED OR STATUTORY. INCLUDING THE IMPUED WARRANTIES OF
MERCHANTABIUTY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values havs be8n chsrscterized but are not tBStsd.

14-126

.D~OIL

ICM7555/ICM7556
TYPICAL PERFORMANCE CHARACTERISTICS

,-.

MINIMUM PULSE WIDTH REQUIRED
FOR TRIGGERING

"

T.

i''''
i'"

2S·C

r,

....
~

I
'/I

Ii ...... I - -::r...- ~ ~.
V'

...

V·

IV

2¥

..

...-,,::

..

10

20

TA

30

.Yl

LOWIIT VOLTAGE LEYt:L OF TRIGGER PULSE ("loY')

2

-01

I

/./

•.•••1"""

C-

....01

~

....
E

..

4

•

•

10 12 14 "

~

V

~
'I' '1''1

....

1. 20

0363-6
0363-5

OUTPUT SINK CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

i§
... 10.0

II
I

T.

·-a c-

••'e!..-+-.

¥

I't

~

-to .../

~

1/

V' -1'1;

f-

.oo

I

ff-

2V-

-

/
1.0

0.G1

0.1

....

1.0

OUTPUT LOW VOLTAGE VOL

II

2~"C

I!

v'· ..

u

! '.. /
i
"

V/
V

... /

0.01

0.1

1.0

..

l •
~

~

4

II • I~

'

"'='e,.....,.""17.....rT1.

c,

R.

Re

~.
Re

V' .

fOMIi

:OOp,

I

y' "18V

~

I ...

..... -

/'/

1.0

f-

c-

/
'/

0.01

0.1
1.0
OUTPUT LOW VOLTAGE VOL

10.0

0363-9

PROPAGATION DELAY AS A
FUNCTION OF VOLTAGE LEVEL OF
TRIGGER PULSE

1.0
10.0
SUPPLY VOLTAGE (VOLTIl

100.0

S ...
...
~

y' =2Y

~

\

lsoo

iii

~ '.' r-V>"t-Jolft-r---rl-tt-t-!-t-I+--i

'Okll

lI_+J-I IW'
II

~

10.0

sv

,.
1-+t12'4:A-J.I-F-+-+I+l-l
-

Ii

I

RA

...

DISCHARGE OUTPUT CURRENT AS A
FUNCTION OF DISCHARGE OUTPUT
VOLTAGE

i

111\

If • I-

i

i

.... ~

r- IJ.-\,

... r":T:T."T.

I

51

r·
i!

0363-6

T.

i2 :

10.0

T • .. 7G 6 C

i

OUTPUT LOW VOLTAGE VOL

0363-7

NORMALIZED FREQUENCY
STABILITY IN THE ASTABLE MODE
AS A FUNCTION OF SUPPLY
VOLTAGE

.oo

...
.... - Ht-y·/ t/ ~JI ovII!
""
-r §
z

OUTPUT SINK CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

J..rTl

!

to
0

'.'

T.

c

to

~

V"

OUTPUT SINK CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

0.'o.~
••;--'-.J..J."-.;.!:.• -L..J..I......,.:':.•,--'-'-~,0.0
DISCHARGE LOW VOLTAGE VOL

0363-11

0363-10

.1.
rA'" ..7rc

Z

TA" .. H~C
TA --20"

/'

~

:I'"
~

f

.oo
o

10

JO

LOWEST VOLTAGE LEVEL OF

3D

40

iiiiiiii ",LU (If. V')
0363-12

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCWSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN typIcsI VBIuss have bHn chsrscItItIz8d but tUB not 16s19d.

14-127

n
I:

...en
en

V' -5'1

t-:

en
.....

CI

SUPPLY VOLTAGE (Yot.TS)

0363-4

...

0.'

/

~

'2S"C

I
I

J

40

IS·C

r

10

'10

I,t,..--

'IV

240g

...
.... .....
!u
-~·t·e .. i
TA

,

C-' '--

... •=

, / T.·· ·..·C

.... 1--"

,..V-

-

I

a

'0

HOi

f-

II

...
... I - -

OUTPUT SOURCE CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE
OUTPUT VOLTAOII! REFERINCED TO V'

"'c

/,

Iii'"
i ,..
~

...

...

f,

...en
en

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

r.

I

:g ICM7 555/ICM7 556
II)

....

Ii TYPICAL PERFORMANCE CHARACTERISTICS

....S!
II)
II)
II)

....
Ii
S!

NORMALIZED FREQUENCY
STABILITY IN THE ASTABLE MODE
AS A FUNCTION OF TEMPERATURE

(Continued)

FREE RUNNING FREQUENCY AS A
FUNCTION OF RA , RB and C
1.0F
T

TIME DELAY IN THE MONOSTABLE
MODE AS A FUNCTION OF RA AND C
1.OF

,. 25"C

100mF

~ '0.'

~

'0.'

~
li

-0.7

~

'0.5

~

;

-0.6

~

l!

f--'t\-''bot--i

100pF

~",
,,

z

""'::::"........
\

1

10

100

lk

10k

~

10/.1F

:

'",F
l00nF

C1

10nF

5
I'\.

........

1,\ 1,,\ "\

10pF

tpF
0.1

w 10o,..F

"""........ """,".~""
,'$} . . . . ,

"........ "

TA"21°C

"OmF

~ ,,(k + ~RJ
100",,"
i""-..
~ 10"F
........ ,,~
;!
t,r

1\--"-+-"-+-+--1-+-+-+--1
I-';-+-r-~+-T-t-t-+--H
1\-\-"'---"-+_+-+_+-.+_+--1

-

a

100mF

10mF

tnF

"i l

tOOk

1M

R,

l00pF
10pF
10M

tpF

100
M

V
1/ V
/ V
. /V
IJ / V
1

10

....

"'.

FREQUENCY (Hz)

V~\"("

V~~

V IA
V V
V

tOO
10"

,

r

10

........

nUEDELAV

0363-14

0363-13

~

"L

100

1

,...

••

10

0363-15

POWER SUPPLY CONSIDERATIONS

APPLICATION NOTES
GENERAL
The ICM7555/6 devices are, in most instances, direct replacements for the NE/SE 555/6 devices. However, it is
possible to effect economies in the external component
count using the ICM7555/6. Because the bipolar 555/6 devices produce large crowbar currents in the output driver, it
is necessary to decouple the power supply lines with a good
capacitor close to the device. The 7555/6 devices produce
no such transients. See Figure 3.

...
...

,
VV
V V V
.....~ V V;'
1/'%\ V V

Although the supply current consumed by the ICM7555/6
devices is very low, the total system supply can be high
unless the timing components are high impedance. Therefore, use high values for R and low values for C in Figures 4
and 5.

OUTPUT DRIVE CAPABILITY
The output driver consists of a CMOS inverter capable of
driving most logic families including CMOS and TTL. As
such, if driving CMOS, the output swing at all supply voltages will equal the supply voltage. At a supply voltage of 4.5
volts or more the ICM7555/6 will drive at least 2 standard
TTL loads .

ASTABLE OPERATION

TA '" HOC

The circuit can be connected to trigger itself and free run
as a multivibrator, see Figure 4. The output swings from rail
to rail, and is a true 50% duty cycle square wave. (Trip
points and output swings are symmetrical). Less than a 1%
frequency variation is observed, over a voltage range of + 5
to +15V.
1
f = 1.4 RC

~
VSE/NES5.

\

. )\CM7555/5Il

200

...

TIME·

n.

600

The timer can also be connected as shown in Figure 4b. In
this circuit, the frequency is:
f = 1.44/(RA + 2RB)C
The duty cycle is controlled by the values of RA and RB, by
the equation:
D = (RA + RB)/(RA + 2RB)

600

0363-16

MONOSTABLE OPERATION

Figure 3: Supply Current Transient
Compared with a Standard Bipolar 555
During an Output Transition

In this mode of operation, the timer functions as a oneshot. Initially the external capacitor (C) is held discharged by
a transistor inside the timer. Upon application of a negative
TRIGGER pulse to pin 2, the internal flip flop is set which
releases the short circuit across the external capacitor and
drives the OUTPUT high. The voltage across the capacitor
now increases exponentially with a time constant t=RAC,
When the voltage across the capacitor equals % V+, the
comparator resets the flip flop, which in turn discharges the
capacitor rapidly and also drives the OUTPUT to its low
state. TRIGGER must return to a high state before the OUTPUT can return to a low state.

The ICM7555/6 produces supply current spikes of only
2 - 3mA instead of 300 - 400mA and supply decoupling is
normally not necessary. Secondly, in most instances, the
CONTROL VOLTAGE decoupling capacitors are not required since the input impedance of the CMOS comparators
on chip are very high. Thus, for many applications 2 capacitors can be saved using an ICM7555, and 3 capacitors with
an ICM7556.

toutput = -In (Ys) RAC = 1.1 RAC
INTERSIL'$ SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical values have been characterized but are not test8d.

14-128

ICM7 555/ICM7 556
CONTROL VOLTAGE
The CONTROL VOLTAGE terminal permits the two trip
voltages for the THRESHOLD and TRIGGER internal comparators to be controlled. This provides the possibility of
oscillation frequency modulation in the astable mode or
even inhibition of oscillation. depending on the applied voltage. In the monostable mode. delay times can be changed
by varying the applied voltage to the CONTROL VOLTAGE
pin.

v.

'OK
OUTPUT 0.,---1---1

RESET
The RESET terminal is designed to have essentially the
same trip voltage as the standard bipolar 555/6. i.e. 0.6 to
0.7 volts. At all supply voltages it represents an extremely
high input impedance. The mode of operation of the RESET
function is. however. much improved over the standard bipolar 555/6 in that it controls only the internal flip flop.
which in turn controls simultaneously the state of the OUTPUT and DISCHARGE pins. This avoids the multiple threshold problems sometimes encountered with slow falling edges in the bipolar devices.

0363-17

Figure 4a: Astable Operation

v+

v+

•

t =

'.'RC

ICM7555
..JLOUTPUT
RB

t-RESET

v+ .. 'BV
0363-18

Figure 5: Monostable Operation
0363-22

Figure 4b:

THRESHOLD

•

CONTROL
VOLTAGE

OUTPUT

"NO

0363-19

Figure 6: Equivalent Circuit

lNTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typ;caJ values have been characterized but are not testsd.

14-129

CD

II)
II)

...

.D~DI!..

ICM7SSS/ICM7SS6

:I TRUTH TABLE
(,)

:::::
II)
I/)
I/)

...

:I

51!

Threshold
Voltage

Trigger
Voltage

DON'TeARE

DON'TeARE

>%(V+)

>%(V+)

<%(V+)

>%(V+)

DON'TeARE

<%(V+)

Output

Discharge
Switch

LOW

LOW

ON

HIGH

LOW

ON

HIGH

STABLE

STABLE

HIGH

HIGH

OFF

RESET

NOTE: RESET will dominate all other inputs: TRIGGER will dominate over THRESHOLD.

INTERSIL'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE CONDITION OF SALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: All typical va/u9s havs been charact8lized but are not tested.

14-130

Section 15 - High Reliability

D~DlL

HIGH-RELIABILITYIMILITARY
PRODUCTS

38510
Per MIL-M-38510
Slash Sheet

100% INTEGRATED CIRCUIT PROCESSING
Intersil is committed to build and process integrated circuits for the Military/High-Rei market segments in conformance with MIL-STD-883 and MIL-M-38510. Any customer
drawing which specifies testing as set forth in these documents will be automatically processed to the latest revisions
of MIL-STD-883 and MIL-M-38510, unless specific requests
are made to the contrary.

u.s. BUILO AND ASSEIIBLY

I

I

TRACEABILITY TO WATER. INSPECTION LOTS

I

I

INTERNAL VISUAL - METHOD 2010, COHO. B

I

L

HI-REL PROCESS OFFERINGS

I

38510 PRODUCTS

STABILlZAllON BAKE - METHOO 1008. CONDo C
24 HRS. 0 .,SOOC OR EQUIVALENT

Intersil holds QPL 1 status on a number of JAN MIL-M38510 products. As required by JAN specifications, these
products are fabricated, assembled, and 100% processed
within the United States and are fully compliant with all the
requirements, procedures, and methods as given in MIL-M38510 and MIL-STD-883.

TEllPERATURE CYCLE - METHOD 1010.
COHO.C 10 CYClES. -65°C TO +15()OC

CONSTANT ACCELERAllON
METHOD 2001, CONDo E, 30 Kg

MILITARY DRAWING PRODUCTS
Intersil offers a large and growing number of Military
Drawing Products (previously referred to as Desc Drawings). These are processed in full compliance with MILSTD-883 Rev C and carry electrical specifications standardized and controlled by Desc.

I

I

HERMET1C1TY - FINE & GROSS. METHOO 1014

INITlAL(PRE-BURN-IN) ELECTRICAL PARAMETER PER
APPUCABLE DEVICE SPEClFICAllON

883 CLASS B PRODUCTS

I

I

The 883 Class B flow diagram represents product processed in accordance with Method 5004 and Method 5005
of MIL-STD-883 Rev. C, Class B. Many products herein are
available as compliant to paragraph 1.2 of MIL-STD-883
Rev. C while others are available only as non-compliant at
this time. Check with Intersil Customer Service as to the
compliant status of individual product offerings at any point
in time.

I

BURN-IN TEST - METHOD 1015

I
INTERIUM (POST BURN-IN) ELECTRICAL PARAYmRS
PER APPLICABLE DEVICE SPECIFlCAnON
5% DEFECTIVE ALLOWABLE (PDA) UNLESS
OTHERWISE SPECIFIED

I
FINAL ELECTRICAL PER APPLICABLE DEVICE
SPECIfICATION
STATIC. DYNAMIC, FUNCTIONAL, & SWITCHING

HR PRODUCTS

• 25°C

The HR flow diagram, newly offered by Intersil, represents high reliability hermetic product utilizing many, but not
necessarily all, of the test methods and requirements of
MIL-STD-883 Rev. C, to be used in high reliability applications where some deviations from Rev. C may be justified
and economic advantages realized. Such product may not
be branded /883B but may be branded /HR or a special
brand as required by purchase order.

STATIC 0 MAX. OPERATING TEIIPERATURE
STATIC 0 MIN. OPERAllNG TEMPERATURE

L
QUALITY CONFORMANCE INSPECTION PER METHOD 5005
GROUP A: TABLE I. EACH LOT PER APPUCABLE DEVICE
SPECIFICATION
SUBGRP
-

BR PRODUCTS
The BR flow diagram, newly offered by Intersil, represents hermetic or plastic encapsulated product intended for
application in the computer, industrial, or hi-rei commercial
marketplace. In addition to 100% burn-in, many other reliability processing steps are included to enhance quality levels on shipped parts and to improve long term reliability
characteristics. Such product may be branded /BR or as
required by purchase order.
Contact Product Marketing for availability and pricing on
883B, HR and BR products.

1
2
3
4

-5
-6

-7
- 8

-9
-10
-11

TEST
STAnc

TEIIP
25°C
MAX.
MIN.

STAne

STATIC
DYNAMIC
DYNAMIC
DYNAMIC
FUNe.
FUNC.
SWITCH
SWITCH
SWITCH

25°c
MAX.
MIN.

25°C
MIN./MAX.
25°C
MAX.
MIN.

GROUP B: TABLE liB, EACH INSPECTION LOT
GROUP C: TABLE III, 3 MO. PERIODIC
GROUP 0: TABLE IV. 6 MO. PERIODIC

EXTERNAL VISUAL - METHOD 2009

100% DISCRETE DEVICE PROCESSING

J

DEVICE MARKING - INTERS~ LOGO
JM 38510/XXX xx XXX DATA CODE

Intersil also offers several QPL-approved discrete products carrying the JAN, JTX, and JTXV deSignation, which
are screened and qualified to the latest revisions of MILSTD-750 and MIL-S-19500.

0422-1

15-1

HR (1, 2, 4)
In-House HI Rei Processing
Flows Per10rmed 100% Unless
Otherwise Noted Applies to
IC's and Hybrids

883 Class B (1, 2, 4)

Per MIL-STD-883 Rev. C
Screening per Method 5004

I

1RACEA8IUIY 10 WAtER a IHSI'£CIION LOTS

I

I

IN1ERIW. VISUAl. - MEIHOO 2010. COND. B

I

I

INTERNAl. VISUAL - MElHOD 2010. CONo. B

I

I

STAlllUZA1ION BAKE
1l£III00 10011. COND.C OR EQUIVAI.EII1'

STABlUZAOON BAJC[ - METHOD 1008. COND.C
24HRS. 0 '15O"C OR EQUIVALENT

I

J

1EMP£RATIJR[ CYCI.£ - 1l£III00 1010.
CONo.C 10 CYClES, -65"C 10 'IWC

TEMPERATlJRE CYCLE - ME1IHOD 1010.
CONDo C 10 CYCLES. -65·C TO '15OOC

I
CONSTANT ACCELERATIOII
MEIHOO 2001. COND. E. 30 Kg

CONSTANT ACCELERAOON
UE1IHOD 2001. CONDo E. 30 Kg

I

I

HERMETlCIlY - nNE.t GROSS. METHOD 1014

I

I

I

INIllAL(PRE-BURN-IN) ELECTRICAL PARAMETER PER
APPLICABLE DEVICE SPEClFlCA~ON

I

BURN-IN TEST - METHOD 1015

BURN-IN TEST
160 HRS. MIN.. TA='12SOC OR EQUIVALENT

INlERIUM (POST BURN-IN) ELECIRICAL PARAMEtERS
PER APPUCAII.E DEVICE SPECIFICATION
5X DEFECIIY[ ALLOWABU: (PDA) UNLESS
OTHERWISE SPECFIED

I
INTERIUM (POST BURN-IN) ELECTRICAL PARAMETERS
PER APPLICABLE DEVICE SPEanCAOON
5" DEFECTIVE ALLOWABLE (POA) UNLESS
OTHEHWISESPEClnED

nNAL ElECI1ItCAL PElt APPLICABLE DE'IICE
SPECIFICATION
STAtIC, DYNAMIC, FUNCTIONAL, a SWIItHING
OZSOC
STAlIC 0 MAX. OPERA~NG 1IlIPERAlURE
STAlIC 0 liN. OPERA_ lEMPERAlURE

J
nHAL ELECTTlICAL PER APPLICABLE DEVICE
SPECInCAOOH (3)
FUNCOONAI. " DC 0 25·C
DC 0 MAX. ·C
DC 0 MIN.·C
At 0 2S·C

QUALITY CONFORMANCE INSPECTION PER METHOD 5005
GROUP A, TABlE I. EACH La! PER APPLICABLE DEVICE
SPECFlCAOON

SUBGRP
-I
- 2
- 3
-4

-5
- 6
- 7

-8
- 9

-10
-II

TEST
STAlIC
STAlIC
STAlIC
DYNAMIC
DYNAMIC
DYNAMIC
FUHC.
FUHc.
SWIICH
SWIICH
SWIICH

HERMETKm' - FlNE.t GROSS. MElHOD 1014

I

INIlW.(PRE-BURN-IN) ELECIRICAL PARAMEtER PER
APPI.ICAIILE DEVICE SPECIFICATION

TEMP
ZSOC
MAX.
MIN.

QA ACCEPTANCE SAMPLE PER APPLICABLE DEVICE

SPEClnCATION (3)
DC 0 2S·C
DC 0 UAX"C
MINOC
FUMC. 0 25·C
FUMC•• MIN / MAXOC
At 0 25·C

zsoc

DC'

MAX.
MIN.

zsoc

MIN./MAX.
ZSOC
MAX.
MIN.

LTPO
LTPO
LTPD
LTPD
LTPD
LTPD

=
=
=
=
=
=

5
7
7
5
10.
S

EXTERNAL VISUAL

GROUP B, TABU: E. EACH INSPECTION La!
GROUP

c: TABLE ., 3 YO. PERIODIC

GROUP 0, TABU: IV. 6 MO. PERIODIC

I

EXTERNAL VISUAL - METHOD 2009

GENERIC DATA
GROUP B = 6 WEEKS
GROUP C = 12 MONTHS
GROUP D = 12 MONTHS

I

DEVICE MARKING - IHlERSlL LOGO
PROOUCT COOE/883B DATA CODE

DEVICE MARK1NG - INTERSIL LOGO
PRODUCT CODE /HR DATA CODE

0422-2

0422-3

FOOTNOTES:
(1) Governing Document, Order of Precedence
A. Purchase Order Contract
B. DetaIl Specification
C. This Flow
(2) Where _ methods are indicated. the _ will be performed to MILSTD-833.
(3) With exception of parameters guaranteed by basic design. no! tested.

15-2

BR (1, 2)
Performed 100% Unless Otherwise Noted
APPLIES TO IC'S AND HYBRIDS

B1 (1,2)
Performed 100% Unless Otherwise Noted
APPLIES TO IC'S ANY HYBRIDS AND
TRANSISTORS

INTERNAL VISUAL - METHOD 2010, CONDo B
INTERNAL VISUAL - PER INTERSIL SPECIFICATION

1

I

STABILIZATION BAKE(6) - METHOD 1008, COND.C

STABILIZATION BAKE(6) - METHOD 1008, COND.C

I
TEMPERATURE CYCLE
5 CYCLES, -65°C TO +150o C

TEMPERATURE CYCLE (7)
METHOD 1010, COND.C

I

I

CONSTANT ACCELERATION (4, 7)
METHOD 2001, CONDo E

CONSTANT ACCELERATION (4, 7)
METHOD 2001, CONDo E

I

I

HERMETICITY
FINE I!c GROSS LEAK(4), METHOD 1014

HERMETICITY(4,7)
FINE I!c GROSS LEAK, METHOD 1014

I

I

ELECTRICAL TEST PER DATA SHEET(3)
DC @ TA = 25°C

ELECTRICAL TEST PER DATA SHEET(3)
DC @ TA = 25°C

I

I

BURN-IN TEST
96 HRS. MIN., TA =+1250 C OR EQUIVALENT

BURN-IN TEST
96 HRS. MIN., TA =+1250 C OR EQUIVALENT

I

I

ELECTRICAL TEST PER DATA SHEET (3)
TA = 25°C

ELECTRICAL TEST PER DATA SHEET (3)
TA = 25°C

I

I

QA ACCEPTANCE SAMPLE PER DATA SHEET(3)
DC @ 25°C
LTPD = 5
FUNC. @ 25°C
LTPD = 5
AC @ 25°C
LTPD = 5

QA ACCEPTANCE SAMPLE PER DATA SHEET(3)
DC @ 250C
LTPD = 5
FUNC. @ 25°C
LTPD = 5
AC @ 25°C
LTPD = 5

I

I

EXTERNAL VISUAL - PER INTERSIL SPECIFIED

QC EXTERNAL VISUAL - 0.1 % AQL

I

I

PRESSURE POT - PLASTICS ONLY 72I!cHRS.(5.7)

PRESSURE POT - PLASTICS ONLY 72I!cHRS. (5.7)

I

I

DEVICE MARKING - INTERSIL LOGO
PRODUCT CODE /BR DATA CODE

DEVICE MARKING - INTERSIL LOGO
PRODUCT CODE /BI DATA CODE
0422-4
0422-5

FOOTNOTES:
(1) Governing Document, Order of Precedence
A. Purchase Order Contract
B. Detail Specification
C. This Flow

(2) Where test methods are indicated, the test will be performed to MIL·STD-883.
(3) With exception of parameters guaranteed by basic deSign, not tested.
(4) Does not apply to plastic packages.
(5) May be performed any time after encapsulation.
(6) For Plastic Packages, stabilization bake is accomplished during the encapsulation curing cycle.
(7) Weekly Reliability Monitor.

15-3

Standard Product (1, 2)
Performed 100% Unless Otherwise Noted
APPLIES TO IC'S AND HYBRIDS AND TRANSISTORS
INTERNAL VISUAL - PER INTERSIL SPECIFICAnON

I
STABILIZATION BAKE(6) - METHOD 1008, COND.C

I
TEMPERATURE CYCLE (4, 6)
METHOD 1010, COND.C

1
CONSTANT ACCELERATION (4, 7)
METHOD 2001, CONDo E

I
HERMETICITY (4, 7)
FINE &< GROSS LEAK, METHOD 1014

I
ELECTRICAL TEST PER DATA SHEET(3)
DC @ TA = 25°C

I
BURN-IN TEST
96 HRS. MIN., TA =+1250 C OR EQUIVALENT

I
ELECTRICAL TEST PER DATA SHEET (3)
TA = 25°C

I
QA ACCEPTANCE PER DATA SHEET(3)
DC @ 25° C
AQL = 0.065%
FUNC. @ 25° C
AQL = 0.065%
AC @ 25°C
AQL = 0.065%

I
QC EXTERNAL VISUAL - 0.1% AQL

I
PRESSURE POT - PLASTICS ONLY 72 &< HRS.(5.7)

I
DEVICE MARKING - INTERSIL LOGO
PRODUCT CODE DATA CODE
0422-6

FOOTNOTES:

(1) Governing Document, Order of Precedence
A. Purchase Order Contract
B. Detail Specification
C. This Flow
(2) Where test methods are indicated, the test will be performed to MIL·STD-883.
(3) Wrth exception of parameters guaranteed by basic deSign, not tested.
(4) Does not apply to plastic packages.
(5) May be performed any time after encapsulation.
(6) For Plastic Packages, stabilization beke is accomplished during the encapsulation curing cycle.
(7) Weekly Reliability Monitor.

15-4

.O~OI!..

High-ReliabilityIMilitary Products
Discrete Products JAN, JANTX and JANTXV
Per MIL-S-19500 and MIL-STD-750
Performed 100% unless otherwise noted
JANlXV

JANTX

0422-7

JAN

0422-8

0422-9

Intersil also offers specials to Customer Source Control Drawings, SCD's. Specials are available with any of the above
processing plus SEM, PIND, etc.

15-5

IJlO~OIL
HIGH RELIABILITY PROCESSING
PROCESS FLOW SELECTION GUIDE
-STANDARD IC PROCESS FLOWSHERMETIC PLASTIC HERMETIC PLASTIC HERMETIC PLASTIC
38510 883B
STANDARD STANDARD NOTES
BI
BI
JAN REV.C.HR
BR
BR

ON·SHORE BUILD
WAFER LOT
TRACEABILITY
PRE-CAP VISUAL M201 OB
STABILIZATION BAKE
TEMPERATURE CYCLE
CENTRIFUGE
HERMETICITY
ELECTRICAL TEST
BURN-IN
ELECTRICAL TEST
POST BURN-IN PDA
D.C. ELECT. @ 3 TEMPS.
A.C. ELECT. @ 25'C
GROUP A SAMPLE
INSPECTION
GROUP B EAC INSP. LOT
STRICT DOCUMENTATION
GROUP C & D INSPECTION

X
2

X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X

X
X
X

X
X
X

X

S

S

G

X
X
X

X
X
X
X
X
X
X
X

X
X
X

S

X

X

X

S
S
S

S

S
S
S

X
3

X
X
X
X

X
X
X

X
X
X

X
X
X

X

X

X

X

X

X

X

X

X
X

3

S
G

3

HIGH RELIABILITY PROCESSING
PROCESS FLOW SELECTION GUIDE
- STANDARD TRANSISTOR PROCESS FLOWS-

ON-SHORE BUILD
INSPECTION LOT TRACEABILITY
PRE-CAP VISUAL
STABILIZATION BAKE
TEMPERATURE CYCLE
CENTRIFUGE
HERMETICITY
ELECTRICAL TEST
BURN-IN
ELECTRICAL TEST
POST BURN-IN PDA
D.C. ELECT. @ 25'C
A.C. ELECT. @ 25'C
GROUPA
GROUP B EACH INSP. LOT
STRICT DOCUMENTATION
GROUP C INSPECTION

JANTXV

JANTX

JAN

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X

S

S

S

HERMETIC
BI

PLASTIC
BI

HERMETIC
STANDARD

PLASTIC
STANDARD

NOTES

2

X
X
X
S

X

X

X

S
S
S

S

S
S
S

X
X

X
X

X
X
X

X
X
X

X
X
X

X
3

X
X
X
3

X

NOTE 1. ONLY MAJOR TRANSISTOR PROCESSING DIFFERENCES ARE SHOWN HERE. SEE DETAIL FLOWS ON FOLLOWING PAGES FOR MORE SPECIF·
IC DATA. CHART IS FOR HERMETIC PACKAGES. ONLY MINIMUM REQUIREMENTS ARE SHOWN.
2. WAFER LOT TRACEABILITY MAINTAINED AND AVAILABLE AT EXTRA CHARGE FOR OTHER PRODUCTS.
3. S ~ SAMPLE TEST ON REGULAR BASIS.
X~PERFORMED 100%.
G~GENERIC DATA.
4. INTERSIL ALSO OFFERS "SPECIALS" TO SPECIFIC CUSTOMER SCD'S. SPECIALS ARE AVAILABLE WITH ANY OF THE ABOVE PROCESSING
PLUS SEM, PIND, ETC.

15-6

MIL·STD·883 REV. C, CLASS B
METHOD 5005
GROUP A
ELECTRICAL ltSTS

I
I

I

I

I

I

I

I

SUBGROUP 1

SUBGROUP 3

SUBGROUP"

SUBGROUP 6

SUBGROUP 7

SUBGROUP 9

SUBGROUP 11

STA11C(DC)
1tSTS 0
25°C

STA11C(DC)
1tSTS 0
IIIN. 1£IIP.

DYNAIlIC
ltSTSO
25°C

DYNAIlIC

1tSTS 0

FUNCTIONAL
1tSTS 0
25°C

SWITCHING
1tSTS 0
250C

SWITCHING
1tSTS 0
IIIN. TEIIP.

IIIN. TEIIP.

SUBGROUP 2

SUBGROUP 5

SUBGROUP 8

SUBGROUP 10

STATIC (DC)
TESTS 0
IIAX. TEIIP.

DYNAIIIC

FUNCTIONAL
1tSTS 0
IIAX. TEIIP.

SWITCHING
1tSTS 0
IIAX. TEIIP.

1tSTS 0
IIAX. TEIIP.

0422-10

TABLE lib
GROUP B

I

I

I

I

SUBGROUP 1
METHOD 2016
PHYSICAL
DIMENSIONS

SUBGROUP 3
IIETHOD 2003
SOLDERABILITY

SUBGROUP 5
IIETHOD 2011
BOND
STRENGTH

SUBGROUP 7
IIETHOO 1014
nNE AND
GROSS LEAK

SUBGROUP 2
METHOD 2015
RESISTANCE
TO SOLVENTS

SUBGROUP"
METHOD 2014
INTERNAL VISUAL
AND
MECHANICAL

SUBGROUP 6
METHOD 1016
INTERNAL WATER
VAPOR CONTENT
(NOTE 1)
0422-11

Note 1: Required only npackage oontains a desiccant

•
15-7

TABLE III

I

I

GROUP C

I

I

SUBGROUP 1
METHOD 2005
STEADY STATE
LIFE TEST

SUBGROUP 2
METHOD 2010
TEMPERATURE
CYCLING
METHOD 2001
CONSTANT
ACCELERATION
METHOD 2014
SEAL
0422-12

TABLE IV

I

GROUP D

I

I

I

I

SUBGROUP 1
METHOD 2016
PHYSICAL
DIMENSIONS

SUBGROUP 3
METHOD 2011
THERMAL SHOCK
METHOD 1010
TEMPERATURE
CYCLING
METHOD 1004
MOISTURE
RESISTANT
METHOD 1014
SEAL

SUBGROUP 5
METHOD 2009
SALT
ATMOSPHERE
METHOD 1014
SEAL

SUBGROUP 7
METHOD 1025
ADHESION OF
LEAD FINISH

SUBGROUP 2
METHOD 2004
LEAD INTEGRITY
METHOD 1014
SEAL

SUBGROUP 4
METHOD 2002
MECHANICAL
SHOCK
METHOD 1007
VARIABLE
FREQUENCY
VIBRATION
METHOD 2001
CONSTANT
ACCELERATION
METHOD 1014
SEAL

SUBGROUP 6
METHOD 1018
INTERNAL WATER
VAPOR CONTENT

SUBGROUP 8
METHOD 2024
LID TORQUE
(NOTE t)
0422-13

Note 1: Applies if package has a Fril-Seal.

15-8

lI1D~OIl.
INTERSIL QPL/Hi·REL DEVICES
Data Acquisition Products
JM38510
AD7520UD
12702BEA
12703BVA
AD7521UD
AD7541TD
12704BVC
12704BVA
AD7541TD
Analog Switch Products
JM38510
IH5040MDE
10501BEA
IH5040MDE
10501BEC
10502BEA
IH5041MDE
IH5041MDE
10502BEC
IH5042MDE
10503BEA
10503BEC
IH5042MDE
IH5043MDE
10504BEA
10504BEC
IH5043MDE
DG181AL
11101BAC
11101BCC
DG181AP
DG181AA
11101BIA
DG181AA
11101BIC
DG181AP
11101BCA
DG182AA
11102BIA
DG182AL
11102BAC
DG182AP
11102BCC
11102BIC
DG182AA
11102BCA
DG182AP
11103BAC
DG184AL
DG184AP
11103BEC
DG184AP
11103BEA
11104BAC
DG185AL
DG185AP
11104BEC
11104BEA
DG185AP
11105BAC
DG187AL
DG187AP
11105BCC
11105BIA
DG187AA
DG187AA
11105BIC
11105BCA
DG187AP
DG188AL
11106BAC
11106BCC
DG188AP
11106BIA
DG188AA
11106BIC
DG188AA
11106BCA
DG188AP
11107BAC
DG190AL
11107BEC
DG190AP
11107BEA
DG190AP
11107BAC
DG191AL

Data Aqulsltlon Products
JM38510 (Continued)
DG191AP
11108BEC
11108BEA
DG191AP
DG300AAP
11601BCC
11601BCA
DG300AAP
DG301AAP
11602BCC
DG301AAP
11602BCA
DG302AAP
11603BCC
11603BCA
DG302AAP
DG303AAP
11604BCC
11604BCA
DG303AAP
DG201AP
12302BEA
DG201AP
12302BEC
Analog Switch Products
Military DWG. NO.
7705201EA
IH6108MJE
7705201EC
IH6108MDE
IH6108MDE
7705201EA
7705301EA
DG201AK
DG201AP
7705301EC
7705301EA
DG201AP
7801401CA
DG129AK
DG129AP
7801401CC
7801401CA
DG129AP
81 00601 AC
IH5040MFD
IH5040MDE
8100601EC
8100601EA
IH5040MDE
8100602AC
IH5041MFD
8100602EC
IH5041MDE
8100602EA
IH5041MDE
81006021A
IH5041MTW
IH5041MTW
81006021C
81006021B
IH5041MTW
8100603AC
IH5042MFD
8100603EC
IH5042MDE
8100603EA
IH5042MDE
81006031A
IH5042MTW
81006031C
IH5042MTW
IH5042MTW
81006031B
8100604AC
IH5043MFD
8100604EA
IH5043MJE
8100604EC
IH5043MDE
IH5043MDE
8100604EA
8100605AC
IH5044MFD
IH5044MJE
8100605EA

15·9

Analog Switch Products
Military DWG. NO. (Continued)
8100605EC
IH5044MDE
IH5044MDE
8100605EA
81006051A
IH5044MTW
IH5044MTW
81006051C
81006051B
IH5044MTW
IH5045MFD
8100606AC
8100606EA
IH5045MJE
IH5045MDE
8100606EC
8100606EA
IH5045MDE
IH5045MTW
81006061A
81006061C
IH5045MTW
IH5045MTW
81006061B
IH5116MJI
5962·8513104XA
IH5116MDI
5962·8513104XA
IH5116MDI
5962·8513104XC
5962·8513105XA
IH5216MJI
IH5216MDI
5962·8513105XA
5962-8513105XC
IH5216MDI
IH5208MJE
5962·8513106EA
IH5208MDE
5962·8513106EA
5962·8513106EC
IH5208MDE
MIL-8-19500 Transistors
2N4858JAN
2N3821 JAN
2N4858JTX
2N3821JTX
2N3821JTXV
2N4858JTXV
2N4859JAN
2N3823JAN
2N3823JTX
2N4859JTX
2N4859JTXV
2N3823JTXV
2N4860JAN
2N4091JAN
2N4860JTX
2N4091JTX
2N4860JTXV
2N4091JTXV
2N4861 JAN
2N4092JAN
2N4861JTX
2N4092JTX
2N4861JTXV
2N4092JTXV
2N5114JAN
2N4093JAN
2N5114JTX
2N4093JTX
2N5114JTXV
2N4093JTXV
2N5115JAN
2N4856JAN
2N5115JTX
2N4856JTX
2N5115JTXV
2N4856JTXV
2N5116JAN
2N4857JAN
2N4857JTX
2N5116JTX
2N5116JTXV
2N4857JTXV

INTERSIL MIL-8TD-883B REV. C COMPLIANT DEVICES
Data Acquisition
Producta
883BReYC.
AD7520SD/883B
AD7520TD/883B
AD7520UD/883B
AD7521 SD/883B
AD7521TD/883B
AD7521 UD/883B
AD7533SD/883B
AD7533TD/883B
AD7533UD/883B
AD7541SD/883B
AD7541TD/883B
ICL7134UJMJ1/883B
ICL7134UKMJI/883B
ICL7134ULMJII883B
ICL7134BJMJI/883B
ICL7134BKMJI/883B
ICL7134BLMJI/883B
Special Analog
Function.
883BReYC.
ICL7660MTV1883B
ICL7662MTV1883B
ICL7667MJAl883B
ICL7667MTV1883B
ICL8038AMJD/883B
ICL8038BMJD/883B
ICL8069CMSQ/883B
ICL8069DMSQ/883B
ICL8211 MTY1883B
ICL8212MTY1883B
nmer/Counter
Clrculta
883BRevC.
ICM7555MTV1883B
ICM7556MJD/883B
AmplifiersOperaUOnal
883BReYC.
ICL8021 MTIt/883B
ICL8023MJE/883B
Analog Switch
Producta
883BReYC.
D123AK/8SSB
D123AL/883B
D125AK/883B
D125ALl883B
D129AK/883B
D129AL/883B
DG126AK/883B

Analog SwHch
Producta
883B Rey C. (Continued)
oo186AP/883B
DG187AA/883B
00187AK/883B
oo187AL/883B
oo188AA/883B
oo188AK/883B
oo188AL/883B
DG189AP/883B
oo190AK/883B
oo190AL/883B
00191 AK/883B
oo191AL/883B
DG200AA/883B
oo200AK/883B
oo201AK/883B
DG201 AAK/883B
DG202AK/883B
DG300AAK/883B
DG301AAA/883B
DG301 AAK/883B
DG302AAK/883B
DG303AAK/883B
DGM181AA/883B
DGM181AK/883B
DGM182AA/883B
DGM182AK/883B
DGM184AK/883B
DGM185AK/883B
DGM190AK/883B
DGM191 AK/883B
IH5009MJD/883B
IH5010MJD/883B
IH5011 MJE/883B
IH5012MJE/883B
IH5013MJD/883B
IH5014MJD/883B
IH5015MJE/883B
IH5016MJE/883B
IH5017MJD/883B
IH5018MJD/883B
IH5019MJE/883B
IH5020MJE/883B
IH5021 MJD/883B
IH5022MJD/883B
IH5023MJE/883B
IH5024MJE/883B
IH5040MFD/883B
IH5040MJE/883B
iH5041 MFD/883B
IH5041MJE/883B
IH5042MFD/883B
IH5042MJE/883B
IH5043MFD/883B
IH5043MJE/883B
IH5044MFD/883B
IH5044MJE/883B

Analog Switch
Producta
883B Rey C. (Continued)
DG126AL/883B
DG129AK/883B
DG129AL/883B
DG133AK/883B
DG133ALl883B
DG134AK/883B
DG134ALl883B
oo139AK/883B
oo139ALl883B
oo140ALl883B
oo140AP/883B
oo141AL/883B
DG141AP/883B
oo142AK/883B
oo142ALl883B
oo143AK/883B
oo143AL/883B
00 144AK/883B
DG144AL/883B
DG145ALl883B
DG145AP/883B
DG146AL/883B
DG146AP/883B
DG151AK/883B
DG151ALl883B
DG152AK/883B
DG152ALl883B
DG153AL/883B
DG153AP/883B
DG154AK/883B
DG154AL/883B
DG161ALl883B
00161 AP/883B
DG162AK/883B
DG162AL/883B
DG163AL/883B
DG163AP/883B
DG164AK/883B
DG164ALl883B
oo180AA/883B
oo180AK/883B
DG180ALl883B
DG181AA/883B
oo181AK/883B
oo181ALl883B
oo182AA/883B
oo182AK/883B
oo182ALl883B
DG183ALl883B
DG183AP/883B
DG184AK/883B
DG184AL/883B
DG185AK/883B
DG185ALl883B
DG166AA/883B
oo186ALl883B

15-10

Analog SwItch
Producta
883B Rey C. (Continued)
IH5045MFD/883B
IH5045MJE/883B
IH5046MFD/883B
IH5046MJE/883B
IH5047MFD/883B
IH5047MJE/883B
IH5052MJE/883B
IH5053MJE/883B
IH5108MJE/883B
IH5116MJI/883B
IH5140MFD/883B
IH5140MJE/883B
IH5141MFD/883B
IH5141MJE/883B
IH5142MFD/883B
IH5142MJE/883B
IH5143MFD/883B
IH5143MJE/883B
IH5144MFD/883B
IH5144MJE/883B
IH5145MFD/883B
IH5145MJE/883B
IH5148MFD/883B
IH5148MJE/883B
IH5149MFD/883B
IH5149MJE/883B
IH5150MFD/883B
IH5150MJE/883B
IH5151 MFD/883B
IH5151MJE/883B
IH5208MJE/883B
IH5216MJI/883B
IH5341 MlW1883B
IH5352MJE/883B
IH6108MJE/883B
IH6116MJI/883B
IH6201 MJE/883B
IH6208MJE/883B
IH6216MJI/883B
Mlcrocontroller.,
Mlcroperlpheral..
Memory
883BReYC.
ICM7170MDG/883B
IM6402-1 MJLl883B
IM6402AIJL/883B
IM6402AMJL/883B
IM6402IJLl883B
IM6653AMJG/883B
IM6653MJG/883B
IM6654-1IJG/883B
IM6654AMJG/883B
IM6654MJG/883B
IM6654IJG/883B

High Reliability Processing
GLOSSARY OF MILITARY/AEROSPACE
HI·REL DEFINITIONS/TERMINOLOGY
ACCELERATED BURN-IN - Same as "Bum-In", except
that testing is carried out at an increased temperature (nominally 150'C) for reduced dwell time. Accelerated testing is
not permissible for Class S devices.
ATTRIBUTES DATA - Go-Na-Go data. Strictly pass/fail
and number of rejects recorded. A typical requirement for
post bum-in electrical tests on Class B devices.
BASELINE - Technique used to define manufacturing and
test processes at time of order placement. Baselining usually involves development of a Program Plan and an Acceptance Test Plan which include flow charts, specification identification/revision letters, QA procedures, and actual specimens of certain important specifications. During subsequent
manufacture and testing of parts, it is not permissible to
make revisions or changes to any of the identified specifications, unless prior notification and possible customer approval occurs.
BURN-IN - A screening operation. Devices are subjected
to high temperature (typically 125'C) and normal power/operation for 160 hours (Class B devices) or 240 hours (Class
S devices).
CLASS SAND B INTEGRATED CIRCUITS -These
classes set forth the screening, sampling and document
control requirements for IC testing. Terminology is defined
in MIL-M-38510 and in Test Methods 5004 and 5005 of
MIL-STD-883. Classes, Sand B are sometimes referred to
as "Levels S and B." The Classes cover:
CLASS S - For space and satellite programs. Includes
Condition A Precap, SEM, 240 hour bum-in, PIND test and
elaborate qualification and quality conformance testing.
Normally requires extensive data, documentation, and program planning. Formerly referred to as Class A. Class S
devices are quite expensive.
CLASS B - For manned flight, and includes most frequently-procured military integrated circuits. Used for all but highest reliability requirements. Class B uses bum-in, pre-cap
visual, etc.
CORRECTIVE ACTION - Those actions which a given
supplier (or user) agrees to perform so that a detected problem does not reoccur.
DESC - Defense Electronic Supply Center, located in Dayton, Ohio.
DESC LINE CERTIFICATION - The document which approves a supplier'S facilities as an appropriate site to manufacture JAN parts.
DPA - Destructive Physical Analysis. Finished products
are opened and analyzed, in accordance with customer or
MIL Spec criteria.
GENERIC DATA - Data pertaining to a device family; not
necessariiy the specific part number ordered by the customer, but representative of parts in the family. Group B, C and
D generic data is frequently requested in lieu of the performance of special qual tests on a given order.
GROUP A - Sample electrical test which are performed on
each lot. Group A is defined in Test Method 5005 for integrated circuits and in MIL-S-19500 for diodes and transistors.

15-11

GROUP B - For Integrated Circuits, Package-Related Environmental Tests are performed for Class B Products per
MIL-STD-883, Method 5005 (For Revision Products) or per
the "HR" program. For Class S, Group B includes Additional Processing, including steady state life test.
For Diodes and TranSistors, both enviromental and life test
are performed per MIL-S-19500.
GROUP C - For Class B or "HR" program I.Co's, Die-Related Tests are performed. Not required for Class S I.Co's.
Group C includes life testing temperature cycling and constant acceleration per MIL-M-38510. For diodes transistors,
Group C includes both environmental and life tests per MILS-19500.
GROUP D - Additional Package-Related Environmental
Test for I.Co's for Class B or Class S products or per the
"HR" program.
JAN - "Joint Army Navy", a registered trademark of the
U.S. Government. The JAN marking denotes a device which
is in full compliance to MIL-M-38510 or MIL-S-19500.
JAN TX - A JAN-qualified diode or transistor which has
been subjected to additional screening and bum-in tests.
MIL-S-19500 only.
JAN TXV - A JAN-qualified diode or transistor which, in
additional to bum-in testing, has been subjected to additional screening including pre-cap visual inspection, as witnessed by a government source inspector. Equivalent to
Class B screening for integrated circuits. MIL-S-19500 only.
LTPD-Lot Tolerance Percent Defective is a sampling plan
measurement criteria.
MIL-M-38510 - The general military specification for integrated circuits.
M38510/XXX - Detail specifications (or "slash sheets")
for integrated circuits. For example, the 101 specification
covers Operational Amplifiers, with electrical requirements
for the 741, LM10l, 108, 747 types, etc.
MIL-8-19500 - The general military specifications for diodes and transistors.
MIL-8-19500/XXX - Detail specifications (or "slash
sheets" for diodes and transistors.
MIL-sTD-750 - Specifies Test Methods for diodes and
transistors, such as bum-in, pre-cap, temperature CYCling,
etc.
MIL-sTD-883 - Specifies Test Methods for integrated circuits, such as pre-cap, bum-in, hermeticity, storage life, etc.
NPFC;... Naval Publications and Forms Center, Philadelphia Printing and distribution source for military specifications.
NON-sTANDARD PARTS -In govemment terminology,
refers to non-JAN devices. Non-standard parts are typically
covered by user Source Control Drawings (SCD).
NON-STANDARD PARTS APPROVAL-Approval by the
government (frequently RADC) of non-JAN parts, typically
on source control drawings, for use in a military system or
program. This approval is essentially a waiver which permits
non-JAN 38510 parts in a system which otherwise mandatOrially requires JAN parts only.

11:1

HIGH RELIABILITY PROCESSING
OPERATING LIFE TEST - Same conditions as burn-in,
but duration is usually 1000 hours. This is a sample test
(Qualification and Quality Conformance).
PCA - Parts Configuration Analysis. A new term which has
much the same meaning as "Baseline".
PDA - Percent Defective Allowable. Criteria sometimes
applied to burn-in screening. MIL-STO-883 and MIL-M38510 typically require either a 5% or 10% PDA. A 10%
PDA means that if more than 10% of that lot fails as a result
of burn-in (as determined by pre- and post-burn-in electrical
tests) the entire lot is considered to have failed.
PDS - Parameter Drift Screening. Measures the changes
(as) in electrical parameters through burn-in. Common for
Class S devices.
PIND - Particle Impact Noise Detection. This is an audio
screening test to locate and eliminate those parts which
have loose internal particles. The test can isolate a high
percentage of defectives, even in otherwise good lots. Repeatability of the tests is questionable. This test is one of
the screening items for Class S integrated circuits.
PREPARING ACTIVITY - The organizational element of
the government which writes specifications, frequently
RADC.
PRESEAL VISUAL - A screening inspection which involves observation of a die through a microscope.
PROCURING ACTIVITY - Per MIL-M-38510, this is the organizational element in the government which contracts for
articles or services. The Procuring Activity can be a subcontractor (OEM), providing that the government delegates this
responsibility. In such a case, the subcontractor does not
have the power to grant waivers, unless this authority has
been approved by the government.
PRODUCT RELIABILITY - Pertains to the level of quality
of a product over a period of time. Reliability is usually measured or expressed in terms of Failure Rate (such as
"0.002% per 1000 hours) or MTBF (mean time between
failure in hours). MTBF is the reciprocal of Failure Rate.
QPL - Qualified Products List. In the case of JAN products, QPLs are identified as QPL-38510 for integrated circuits and QPL-19500 for diodes and transistors. QPL-38510
revisions occur approximately quarterly and QPL-19500 revisions occur approximately annually. In the interim, the
government will notify suppliers via letter of any new device
qualifications which may have been granted. Two types of
QPLs exist for MIL-M-38510:

QUALIFYING ACTIVITY - Per MIL-M-38510, the organizational element in the government which deSignates certification (i.e., DESC).
QUALIFICATION TESTING -Initial one-time sample tests
which are performed to determine whether device types
and processes are good. For integrated circuits, this usually
means testing to Groups A, B, C and D per MIL-STD-883.
For diodes and transistors, this usually means testing to
Groups A, Band C per MIL-STD-750.
QUALITY CONFORMANCE TESTING - These are sample tests which must be performed at prescribed intervals
per MIL-M-38510 or MIL-S-19500, assuring that processes
remain in control and that individual lots are passed.
RADC - Rome Air Development Command, Griffiss AFB,
New York. This is the government organization which created semiconductor specifications; MIL-M-38510 and MILSTD-883 were developed at RADC. This Air Force unit develops specifications for all U.S. military services. RADC is
frequently involved in granting waivers for non-standard
parts for Air Force systems.
READ AND RECORD DATA - Same as variable data.
REWORK PROVISION - For semiconductor devices, permissible rework of parts is usually limited to re-testing
(screening), re-marking, and cleaning.
SCREENING - Operations which are performed on devices on a 100% basis (not sampling). Examples include precap visual, burn-in hermeticity, 100% electrical test, etc.
SEM INSPECTION - Inspection by Scanning Electron Microscope. Die samples are examined at very high magnification for metallization defects.
SERIALIZATION - The marking of a unique part number
on each part, with assigned numbers marked sequentiallyl
consecutively.
SCD. - Source Control Drawings. Typically user-generated drawings which require development of internal IC vendor sheets. Although each drawing may be slightly different,
all will be modelled around MIL-M-38510, MIL-S-19500,
MIL-STD-883, or MIL-STD-750.
SOURCE INSPECTION - Can be either Customer Source
Inspection (CSI) or Government Source Inspection (GSI).
Source Inspection is initiated via purchase order, and can
typically occur at one or more points:
• Pre-cap Visual. Expensive and adds to throughput time.

PART II QPL - This is an interim or temporary QPL which
is granted on the basis of having obtained line certification
and approval of an Application to Conduct Qualification
Testing. A PART II QPL is automatically voided after 90
days whenever anyone supplier is granted a PART I QPL.
PART I QPL - A "permanent" QPL, granted after all qualification testing is completed and test data is approved by
the government.

15-12

• Final Inspection.
TRACEABILITY - A production and manufacturing control
system which includes:
• Wafer run identification number.
• Date pre-cap visual inspection was performed, identity of
inspector, and specification number and revision.
• Lot number and inspection history.
• QA Group A electrical results.
VARIABLE DATA - Read and recorded electrical measurements (parametric values). Usually required for pre- and
post-burn-in electrical tests. Also common for Group C and
D testing.

Section 16 -

Ordering and Marking
Information

ORDERING INFORMATION
Device Family Prefixes

Package Type DesIgnators

AD

A
B
C
0
E
F
H

-Analog Devices Alternate Source
-Driver/Level Translator IC
DG
-Siliconix Analog Switch Alternate Source
DGM -Monolithic DG Analog Switch Replacement
ICL
-Linear IC
ICM
-Microperipheral IC
ICH
-Hybrid IC
1M
-Microcontroller IC
LH
-National Semiconductor Hybrid Alternate Source
LM
-National Semiconductor Alternate Source
MM
-High Voltage Analog Switch
NE
-Signetics Alternate Source
SE
-Signetics Alternate Source
2N
-Industry Standard Discrete Transistor
3N
-Industry Standard Discrete Transistor
IT
-Discrete Transistor
ITE
-Discrete Transistor
J
-Discrete Transistor
M
-Discrete Transistor
NF
-Discrete Transistor
P
-Discrete Transistor
PN
-Discrete Transistor
-Discrete Transistor
U
VCR -Discrete Transistor
10
-Low Leakage Diodes
G
-Siliconix Analog Gate Alternate Source
IH
-Analog Switch Family
ADC -National Semiconductor AID Alternate Source
p.a
-Fairchild Linear Alternate Source
Temperature Range Designators

o

J
K
L
P
S
T
U

V
Z

EXCEPTIONS TO PACKAGE TYPE
DESIGNATORS
DG & DGM Series
A
L
P
K

M

-10 Pin Metal can
-14 Pin Flatpack
-Ceramic DIP (Special Order Only)
-CERDIP

AD Serlel
H

C

-TO-237
-Small Outline IC (SOIC)
-TO-220
-Ceramic Dual-In-Line
-Small TO-8
-Ceramic Flat Pack
-TO-66
-16 Pin (0.6 x 0.7 Pin Spacing)
Hermetic Hybrid Dip
-CERDIP Dual-In-Line
-TO-3
-Leadless, Ceramic
-Plastic Dual-In-Line
-TO-52
-T0-5Type
(Also TO-78, TO-99, TO-100)
-TO-72 Type
(Also TO-18, TO-71)
-TO-39
-T0-92

-Commercial: O"C to + 70°C
-Industrial: Either -25°C to + 85°C or -40"C to
+ 85°C (Specified on Datasheet)
-Military: - 55°C to + 125°C

o
N
R

-TO-52
-CERDIP Ceramic DIP
-Epoxy DIP
-TO-92

III
INTERSlL'S SOLE AND EXCLUSIVE WARRANlY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARnCLE OF THE CONDlnoN OF BALE.
THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANnES. EXPRESS. IMPLIED OR STATUTORY. INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

NOTE: AN typ/cBI V8Iu6s have btHJn characIstiz6d but IU6 not tssted.

16-1

ORDERING INFORMATION
Pin Count Designator

A

8

P

B

10

Q

2

C

12

R

3

D

14

S

4

E

16

T

6

20

F

22

U

7

G

24

V

8 (0.200· pin circle, isolated case)

H

42

W

10 (0.230· pin circle, Isolated case)

J

32

Y

8 (0.200· pin circle, case to pin 4)

Z

10 (0.230· pin circle, case to pin 5)

28
K

35

L

40

M

48

N

18

EXCEPTIONS TO PIN COUNT DESIGNATORS
DG • DGII! Series
A
L
P
K

-10 Pin Metal Can
-14 Pin Flatpack
-Ceramic DIP (Special Order Only)
-CERDIP

ADSeriea
D
H
N

-20, 18, 16 or 14

-3 Pin
-20, 18, 16 or 14

HIGH RELIABILITY DESIGNATOR
1883B
IHR
IBR
IBI

-MIL-STD-883B Screened Device
-High-Reliability Device
-Cost Effective High-Reliability Device
-Bum-in Only Process Flow

16-2

ORDERING INFORMATION
Part Numbering System
All Intersi! Part Numbers consist of a Device Family Prefix, a Basic Numeric Part Number, and an Option Suffix, as follows:

1, 2 OR 3
DIGIT
PREFIX

3, 4, OR 5 DIGIT
3 OR 4
UNIQUE DEVICE DIGIT OPTION
NUMBER
SUFFIX

XXX

XXXXX

HIGH
RELIABILITY
DESIGNATOR

XXXX

/XXXX

-r-

PIN COUNT DESIGNATOR
PACKAGE TYPE DESIGNATOR
TEMPERATURE RANGE DESIGNATOR
ELECTRICAL OPTION DESIGNATOR ONLY.
USED IF MORE THAN ONE ELECTRICAL
OPTION IS AVAILABLE.
VARIATION OF BASIC DEVICE TYPE DESIGNATOR.
ONLY USED IF MORE THAN ONE
BASIC DEVICE IS AVAILABLE.
3 OR 4 DIGIT BASIC DEVICE TYPE
PART NUMBER
DEVICE FAMILY PREFIX

0424-1

Part Number Systems Examples
ICL 7129CPL

ICt.f7170 I DG

U!l]l::L

U!1!l::L

40 PINS ON PACKAGE
PLASTIC DUAL-IN-LINE PACKAGE
OOC TO 700C TEMP. RANGE
BASIC PART NUMBER: 7129 A/D CONVERTER
LINEAR IC FAMILY DEVICE

24 PINS ON PACKAGE
CERAMIC DUAL-IN-LiNE PACKAGE
-40OC TO +85OC TEMP. RANGE
BASIC PART NUMBER: 7170 REAL TIME CLOCK
MICROPERIPHERAL IC FAMILY DEVICE

0424-2

0424-3

Example 1

Example 2

IH 5043 BMFD

IH 5009 MJ D/883B

~~l::L

m~l:::[L_STD_883B

14 PINS ON PACKAGE
CERAMIC FLAT-PACK-PACKAGE
-55OC TO +1250 C TEMP. RANGE
B TYPE ELECTRICAL OPTION
BASIC PART NUMBER: 5043 ANALOG SWITCH
' - - - - - HYBRID IC FAMILY DEVICE

SCREENED DEVICE
14 PINS ON PACKAGE
CERDIP DUAL-IN-LiNE-PACKAGE
-55OC TO +125 0 C TEMP. RANGE
BASIC PART NUMBER: 5009 ANALOG SWITCH
' - - - - - HYBRID IC FAMILY DEVICE

0424-4

0424-5

Example 3

Example 4

1[11
16-3

ORDERING INFORMATION
Part Number Systems Examples

~~~11107B~iL ,~.
[

L -_ _ _ _

(Continued)
ITS XXXX

e"..

A- HOT SOLDER DIP
B- nN PLATE
C- GOLD PLATE

L

FOUR OR FIVE DIGIT NUMBER
FIRST DIGIT INDICATOR PRODUCT FAMILY I. •.•
1 OR 3-DISCRETE
7- ANALOG
6- LINEAR
8- DATA ACQUISITION
9- LOW POWER
' - - - - - INTERSIL SPECIAL-NORMALLY SELECTED TO AN SCD
r

CASE OUTLINE
DEVICE CLASS
DETAIL SPECIFICATION AND DEVICE TYPE
MILITARY DESIGNATOR

0424-7

0424-6

Example 6

Example 5

~Fl':

65SXXX

1T :"" .'"'""~.

INTERSIL DIGITAL SPECIAL-NORMALLY
SELECTED TO AN SCD

. . ,.

,0., ""

L-14 PIN FLAT PACK
P- CERAMIC DIP (SPECIAL ORDER ONLY)
K- CERDIP
A-MILITARY
TEMPERATURE RANGE B-INDUSTRIAL

PACKAGE

0424-8

Example 7

DEVICE TYPE
' - - - - - . ANALOG SWITCH
0424-9

Example 8
AD 7541 T D

L.::
~Tl18

PIN CERDIP
MIL TEMP RANGE
DEVICE TYPE
ANALOG DEVICES
ALTERNATE SOURCE

Example 9

Intersil Code and FSCM Number Information
CDPR - Letter Code for Intersil Assigned by the U.S. Government
32293- Intersil FSCM Number Assigned by the U.S. Government

16-4

0424-10

EVALUATION KITS
Product Description
Power Amplifier Kits

Part Number

Contents

ICH851 OIEVIKIT
ICH8520lEVIKIT

ICH851 Oi + Socket+ Heat Sink
ICH8520i + Socket + Heat Sink

3% Digit LCD Panel Meter Kit

ICL71 06EVIKIT

ICL7106+ PC Card + All Passive Components

3% Digit LED Panel Meter Kit

ICL7107EV/KIT

ICL7107+ PC Card + All Passive Components

3% Digit Low Power
LCD Panel Meter Kit

ICL7126EVIKIT

ICL7126 + PC Card + All Passive Components

4% Digit AID Converter Kit

ICL7129EVIKIT

ICL7129 + 4% Digit LCD Display + ICL8069 + PC Card + Active,
Passive Components

4% Digit LCD Display Driver Kit

ICM7211EVlKIT

ICM7211 +4% Digit LCD Display + PC Card + Active,
Passive Components

8 Character Multiplexed LCD
Display Driver Kit

ICM7233AEVIKIT

2 of ICM7233A + PC Card + 8 Character Triplexed LCD Display

8 Character Multiplexed LED
Display Driver Kit

ICM7243BEVIKIT

ICM7243B + PC Card + 8 Character LED

4% Digit LCD Display Counter Kit

ICL7224EVIKIT

ICM7224 + ICM7207A + 5.24288MHz Crystal + 4% Digit
LCD Display + PC Card + Passive Components

4% Digit LED Display Counter Kit

ICM7225EVIKIT

ICM7225+ ICM7207A + 5.2428BMHz Crystal + 4 % Digit
LED Display + PC Card + Passive Components

ICM7206EVIKIT
ICM7206AEVIKIT

ICM7206 + 3.579545MHz Crystal
ICM7206A + 3.579545MHz Crystal

ICM7206BEV/KIT

ICM7206B + 3.579545MHz Crystal

ICM7226AEV/KIT

ICM7226A + 1OMHz Crystal + PC Card + LEDs + All
Passive Components

Touch Tone Encoder
One contact per key
Two contacts per key, common
to positive supply
Common to negative supply,
oscillator enabled when key
depressed

8 Digit Frequency/Perlod Counter
5 Function

IIII
16-5

A020

APPLICATION NOTE SUMMARY
The following are brief descriptions of current Intersil Application notes.
A003

A004

A005

A007

A011

A013

A015

A016

A017

A018

A019

UNDERSTANDING AND APPLYING THE ANALOG
SWITCH
Introduces analog switches and compares them to
relays. Describes CMOS, hybrid (FET + driver), JFET "virtual ground" and J-FET "positive signal"
types. Application information included.
IH5009 LOW COST ANALOG SWITCH SERIES
Compares the members of the IH5009 "virtual
ground" analog switches and provides suggested
applications.
THE 8007 - A HIGH PERFORMANCE FET INPUT
OPAMP
Compares the 8007 with the 741, which is pin compatible and suggests applications such as logantilog
amplifier, sample and hold circuit, photometer, peak
detector, etc.
USING THE 8048/8049 MONOLITHIC LOG-ANTILOG AMPLIFIER
Describes in detail the operation of the 8048 logarithmetic amplifier, and its counterpart, the 8049 antilog amp.
A PRECISION FOUR QUADRANT MULTIPLlERTHE 8013
Describes, in detail, the operation of the 8013 analog multiplier. Included are multiplication, division,
and square root applications.
EVERYTHING YOU ALWAYS WANTED TO KNOW
ABOUT THE 8038
This note includes 17 of the most asked questions
regarding the use of the 8038.
DESIGN FOR A BATTERY OPERATED FREQUENCY COUNTER
Describes a low cost battery operated frequency /
period counter using the 7207 A and 7208. Includes
specifications, schematics, PC layout, etc.
SELECTING A/D CONVERTERS
Describes the differences between integrating converters and successive approximation converters.
Includes a checklist for decision making, and a note
on multiplexed data systems.
THE INTEGRATING AID CONVERTER
Provides an explanation of integrating AID converters, together with a detailed error analysis.
DO'S AND DONT'S OF APPLYING AID CONVERTERS
An analysis of proper design techniques using 0/ A
converters.
4% DIGIT PANEL METER DEMONSTRATION/INSTRUMENTATION BOARDS
Describes two typical PC board layouts using the
8052A17103A 4 % digit AID pair. Includes schematics, parts layout, list of materials, etc. Also see
A028.

A021

A022

A023

A026

A027

A028

A029

A030

A031

A032

16-6

A COOKBOOK APPROACH TO HIGH SPEED
DATA ACQUISITION AND MICROPROCESSOR INTERFACING
Uses the building block approach to design a complete 12 volt system. Explains the significance of
each component and demonstrates methods for microprocessor interfacing, including the use of control signals.
POWER D/A CONVERTERS USING THE ICH 8510
Detailed analysis of the 8510. Included are a section describing the linearity of the device and application notes for driving servo motors, linear and rotary actuators, etc. Also see A026.
A NEW J-FET STRUCTURE - THE VARAFET
Describes in detail the operation of the varafet, a
standard J-FET with the analog gate interfacing
components monolithically built-in.
LOW COST DIGITAL PANEL METER DESIGNS
Provides a detailed explanation of the 7106 and
7107 3% digit panel meter IC's, and describes two
of the evaluation kits available from Intersil.
DC SERVO MOTOR SYSTEMS USING THE
ICH8510
This companion note to A021 explains the design
techniques utilized in using the ICH8510 family to
drive closed loop servo motor systems.
POWER SUPPLY DESIGN USING THE ICL8211
AND ICL8212
Explains the operation of the ICL8211/12 and describes various power supply configurations. Included are positive and negative voltage regulators,
constant current source, programmable current
source, current limiting, voltage crowbarring, power
supply window detector, etc.
BUILDING AN AUTO RANGING DMM WITH THE
ICL7103A18052A CONVERTER PAIR
This companion app note to A019 explains the use
of the 8052A/7103A converter pair to build a ±4%
digit auto ranging digital multimeter. Included are
schematics, circuit descriptions, tips and hints, etc.
POWER OP AMP HEAT SINK KIT
Describes the heat sinks for the ICH8510 family.
These heat sinks may be ordered from the factory.
THE ICL71 04: A BINARY OUTPUT AID CONVERTER FOR MICROPROCESSORS
Describes in detail the operation of the 7104. Includes in digital interfacing, handshake mode, buffer
gain, auto-zero and external zero. Appendix includes detailed discussion of auto-zero loop residual errors in dual slope AID conversion.
COIL DRIVE ALARM DESIGN CONSIDERATIONS
Explains the procedure used when using watch circuits to drive piezoelectric transducers.
UNDERSTANDING THE AUTO-ZERO AND COMMON MODE PERFORMANCE OF THE ICL7106/
7107/7109 FAMILY
Explains in detail the operation of the ICL71 06/7/9
family of AID Converters.

1Il0~OI!..
A046

A047

AOSO

AOS1

BUILDING A BATTERY OPERATED AUTO RANGING DVM WITH THE ICL7106
Explains principles of auto ranging, problems and
solutions. Includes clock circuits, power supply requirements, design hints, schematics, etc.
GAMES PEOPLE PLAY WITH AID CONVERTERS
Describes 25 different integrating AID converter applications. Input circuits, conversion modifications,
display and microprocessor interfaces are shown in
detail.
USING THE IT500 FAMILY TO IMPROVE THE INPUT BIAS CURRENT OF BIFET OP AMPS
A brief description of a preamplifier for BIFET OP
AMPS.
PRINCIPLES AND APPLICATIONS OF THE
ICL7660 CMOS VOLTAGE CONVERTER
Describes internal operation of the ICL7660. Includes a wide range of possible applications.

AOS2

AOS3

AOS4

16-7

TIPS FOR USING SINGLE CHIP 3% DIGIT AID
CONVERTERS
Answers frequently asked questions regarding the
operation of 3% digit single chip AID converters.
Included are sections on power supplies, displays,
timing and component selection.
THE ICL7650 A NEW ERA IN GLITCH-FREE
CHOPPER STABILIZER AMPLIFIERS
A brief discussion of the internal operation of the
ICL7650, followed by an extensive applications section including amplifiers, comparators, log-amps,
pre-amps, etc.
DISPLAY DRIVER FAMILY COMBINES CONVENIENCE OF USE WITH MICROPROCESSOR INTERFACEABILITY
Compares and describes the various display drivers.
Includes design examples for 7 segment, Alpha-numeric. and bargraph systems.

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

'_1-

0.209-0.219
(5.309 5.563)
0.188-0.210

0.178-0.191

0.208-0.219
(5.309-5.583)
0.178-0.191 ~ I 0.142-0.150
(4.521-4.851) : I
I I (3.807-3.810)

I

I+--,
y_~

.1

SEATING PLANEr

t=L 0

0.030
(0.782)

IL

MAX
0.018-0.019 ....
(0.0408 0.483)

0.01:~~.019

U U

(0.406-0.463) ....

0.500
(12.70)
MIN

1

0a0

0.030

(0.762)

II II

II1--

0.500
(12.70)

0•100
-1
. - (2.540)

0.050
1
(1.270)-

I-I

TO-52 (SQ' , SR)

R

0.209-0.219
(5.309 5.583)
0.178-0.191
(4.521-4.851)

_

I

0.208-0.219
-(5.309-5.563)

0.178-0.191 , _ 0.142-0.159
(4.521-4.851)
1 (3.807,-4.039)

0.188-0.210

I (4.775~5.334)

'·. . ·llO?

SEATING

o.~ ~~r\1

(0.762)
MAX
0.016-0.019 .....
(0.406-0.463)

III 0111w __
MAX
II (12.70)
0.500
0.018-0.019 .... __
0.j30
(0.782)

(0.408-0.483)

PLANED_~

U W __

1_

0.500

(12.70)
MIN

0.050 ...
(1.270)

MIN

0.050 ....
(1.270)

SQ'" denotes a two lead package; center lead missing.

16·8

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).
0.209-0.219

'"

(5.309-5.5831

0.178-0.191 1 _
(4.521-4.881 1 , 1

0.188-0.210
(4.775, 5.3341

1

" "(:::::~:~:I
"1
I DIA "I

~

0.165-0.1 5
(4.191-4.8991

'~n"~TqJ
(~:~:I

MAX
0.018-0.019 _
(0.408-0.4931

a
II_

DIA

I

+

+ --

-

t

0.500 0.040
(12.701 (1.0181 ~ ~
MIN
MAX

001

0.315-0.335
(8.001-8.5091

t

SEATING
PLANE

~ ~~I

~ 0.016-0.019

0.500

(~i~OI

-

(0.406 0.4931

0.050_
(1.270)

TO-78(TT)
~

.095 (2.4131

: 1::1

DIA (31

~

019 (4631

.095

f====l=+===~r==:p~16/406) DI_Ar(3_1---+_.045~(_1.1_43,,,.IT',_(2_.41t3_1t
C:::J

t=+=========p d
~=tt======:::::P' d
I
'1~::~A~INJU
I!::l

r :: 1§'
SEATING

.500 (12.700) MIN

I

-4-3
f -~-2-

-~-1

----'-

~i""i"""'"~-+
~~:.

PLANE

TO-92

16-9

•

PACKAGE OUTLINES

~

.210 (5.334)
.119 (4.318)

All dimensions given in inches and (millimeters).

J

J

.100 ' .100'
(2.540) (2.54G)
MIN
MAX

.310
(7.874)
MAX

.170 '4.318'
=

.135 (3.429)

.197
(5.004)
MAX

TO-92 with ICO Mil Leads Spacings Add (-2) to Standard Part Number

1.

.100
(2.540)
MIIN

~

r-

SEATING PLANE

305 MAX
(7.747)

.120
(3.848)
MIN

---~J{

1-1

l

.280 (7.112)
.220 (5.588)

.019

(A83)

.016 (AII6)
DIA
.100
(2.54G) REF

~REF
(2.54G)

TO-92 Lead Form to TO-5 Pin Circle Add (-5) Suffix to Standard Part Number

.100
(2.540)

1

C~ L

~MIN SEATINGiPLANE(3.048)
.120

.305
(7.747) MAX

I I q===J-L
l~

J

.175 (4.445)
DIA

MIN

' 1 \ I-:I
1-~r,1-

L.019 (.483) DIA
.016

(.406~

.220 (6.588)

(1.270)

REF

jJ-1

L

(1.270) REF

.050
(1.270) REF

TO-92 TO-92 Lead Form to TO-18 Pin Circle Add (-18) Suffix to Standard Part Number

16-10

TO-92 TAPING SPECIFICATIONS AND WINDING STYLES
Extraction Force
Mln300gf

(EIA STD RS468)
P
Po
P,
P2
P3
W
Wo
W,
W2
W3
H

~II--

12.7 ± 0.5
12.7 ± 0.2
3.85 ± 0.5
6.35 ± 0.5
6.35
10
8+-Q5

6±1
9 ± 0.5
Max. 0.5
Min. 4.5
19.5 ± 0.5

16 ± 0.5
0.8
5+-02

Ho
F
F, - F2
Do

±0.3
4 ± 0.2
0.7 ± 0.2
o± 1
0.050,gg:dia.

t
dh
d

R

0.8
4S"C-60"C
Max. 11
o ± 0.5

"L
de

All Dimensions in Millimeter

!1!!l&.e
STYLE A IS PREFERRED

~
FEED~

0

0

a

0

ROUNDED SIDE

STYLE E IS A PREFERRED STYLE

AOUNDEDSIDE

~

ADHESIVE TAPE
CARRIER STRIP

0

FEED~

00

~

FLATSIDE

ADHESIYE TAPE

~~~;.;~~~~

CARRIER STRIP

ADHESIVE TAPE
CARRIER STRIP

coo

ROUNDED SIDE OF TRAN~STOR ANO ADHESIVE TAPE VISIBLE
FLAT SlOE OF TRANSISTOR AND ADHESIVE TAPE VISIBLE

~

~

ROUND£DSIDE

F\.ATSID£

o

ADHESIVE TAPE ON
REVERSE SlOE

FEED~

CARRIER STAtP

ceo

00

FUT SlOE OF TRANSISTOR AND CARAfEA STRIP YISIBLE
(ADHESiVE TAPE ON REVERSE SIDE)

FEEO-~

/ ADHESIVE TAPE ON
/
; REVERSE SiDe
CARRIER STRIP

D

0

Q

0

ROUNDED SlOE OF TRANSISTOR AND ADHESIVE TAPE VISIBlE
STYLE P IS EQUIVALENT TO STYLES A, a, C, D OF REEL
PACK DePENDING ON WHICH BOX.FLAP IS OPENED AND
WHICH END OF THE BOX THE DEVICES ARE FED FROM.

D

ROUNDED SIDE OF TRANSISTOR AND CARRIER STRIP VISIBLE
(ADHESIVE TAPE ON REVERSE SlOE)
FLAT SIDE

/

o
~
C

Q

0

0

a

ROUNDED SIDE

8"

~ADHE"VET'PE

CARAIERSTAIP

ADHESIVE TAPE

CARRIER STRIP

FEED

"~'lY

~F~EE~D~~~~~y

ADHESIVE TAPE
CARRIER STRIP

FLAT SIDE

FUO~
ROUNDED SIDE OF TRANSISTOR
AND ADHESIVE TAPE VISI8LE

G' ,,

ADHESIVE TAPE ON
REVERSE SIDE

~CARRIERSTRIP
FEED-

'l';y

FlAT SIDE OF TRANSISTOR AND ADHESiVE TAPE VISiBlE

ADHESIvE TAPE
ON REvERSE SIDE

FEED~CARRIERSTRIP
c o o ..
ROUNDED SIDE
Q

F1.AT SiDe OF TRANSISTOA AND ADHESivE TAPE VISIBLE
STYLE M AMMO PACK IS EQUIVALENT TO STYLES e, F, G, H
OF REEL PACK DEPENDING ON WHICH BOX·FLAP IS OPENED
AND WHICH END OF THE BOx THE DEVICES ARE FED FROM.

FLATSIDE

o
ROUNDED SIDE OF TRANSISTOR AND CARRIER STRIP VISIBLE
(ADHESIVE TAPE ON REvERSE stDE)

FLAT SIDE OF TRANSISTOR AND CARRIER STRIP VISIBLE
(ADHESIVE TAPe ON REVERSE SIDE)

0424-11

16-11

Typical Quantities

ORDERING INFORMATION

1800 Units Per Reel
3000 Units Per Ammo Box

TO-92 Standard Lead Forms
Lead Form
Suffix
TO-18 Pin Circle
T0-5 Pin Circle
100-Mil Leads Spacing

-18
-5
-Z

TO-92 Taping Specifications and Winding Styles
Style
A
B
C
D
E
F
G
H
P
M

Packaging

Suffix

Reel
Reel
Reel
Reel
Reel
Reel
Reel
Reel
Ammo Box
Ammo Box

-TA
-TB
-TC
-TD
-TE
-TF
-TG
-TH
-TP
-TM

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

0.335-0.315
(8.508-8.001)

0.315-0.335
(8.001-8.508)
0.185-0.185
(4.191-4.689)

+

_+_

~

0.500

.040

(12.70)
MIN

(1.0181
MAX

+

-.1

DIA

DIA

L

~~ ~ ~~

.LEADS

0.019-0.018

0.200
(5.0811)

0.034-0.028
(0.884-0.7111

16-12

0.185-0.185

+(4.689-4.1811

0.500
(12.7)

~~ ~ ~~~MIN

-I L
(O.483-CI.408I -II·

0.018-0.019
(0.408-0.4831

1

==;:-r

I

(.254-1.0161

--II ..

•

PLANE - . -

.010-0.040

::::-~!::I
DlA

0.040

(1.0161
MAX
SEATING

___ INSULATOR
l

A

.010-0.040
(.254 1.0181

PACKAGE OUTLINES

All dimensions given in inches and (millimeters) .
•370-.335
(!.398-8.509)

~

.335-.305 I
I"(8.509
7.747)"

'040_1'018~
~

T/"
.019-.016 DIA
(.483 .408)

.185-.185

---,tr-

_(4_.8~r_-_4_.19_1_)

L
~~

~

on

UU U UU

.010-.041.500
(.254-1.016)
(12.700) MIN

*

[[]
_

0.430 (10.922) _

MAX
0.115 (2.921)

0.310 (7.674)
0.260 (7.1121 ..

0.070 (1.778)

- t' rmr+r_~_'!0::-:::(::-5'08-;:-::)=--1..-----.
t

0.060 (1.524)
0.025 (0.635)

1

~

J. J.

t-

4=0.=200=(=5.=08=)=:::=- 1i--'0.rr,-::5=>=11-

I

0.110 (2.794) - 0.090 (2.286)

I II

if.125 (3.175)

--

~:~~: :~:::: _ _

(0.361)

I

__

0.320 (8.128)
0.290 (7.366)

8 LEAD CERAMIC (DA)

16-13

0.008
(0.203)

i"

"I'

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

-- --

D --

0.271
0.245

--

0.320
0.290

--g:~~:-

!
t

~!~I ~
1

0.060

ftff' J5t.-,/
~~o
-I

1065
h_
-_
0.045
0.011
0.009

I

I

't-O-'.
16'c::
5- - 0.125

11_

1__

-I i-

0 .020
0.016

I

I

I

I-

0.015
0.009

I

0.375
NOM. -

I

8 LEAD CERDIP (JA)

-L
0.250 ± 0 . 0 1 0 0
6.36 ± .254

___

t

0.065
J(1.6511

-

-

'r

L

! 0.390 MAX J

0.310 ± 0.010
(7.87 ± .25)

~ ~ ""'1"''R
",,:t
.L." =i
J:Illllll~
tlt

.090 (2.2861

I

0.130 ± 0.005

.014 (.356)

(3.1751

.Q70 {t.7781
.030 (.7621

8 LEAD PLASTIC (PA)
0.770
(19.561
0.344-0.364 ~
(8.74-9.251

I

0.480-0.500
(12.19-12.71

I

lr~~SEATING
T
~

PLANE

0.085-0.100
(2.16-2.54)

!!_

(1.021 TYP ....

1.182-1.192

0.500

(12.70) R 1(!0.02
±.010
(.254) I"

+

30.2~1

...

I

j,......,:-!-+

0.153-0.159
0"0..0
(3.88-4.031 " ' ....... I
(2) HOLES '
40' TYP.
(7) PLCS

"-......1

~;.::=~:!~~ RAD.

0.495-0.505
(12.057 12.082)
LEAD CIRCLE

8 LEAD TO-3 METAL CAN (KA)

16-14

rn

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

-I

r

~
7
-+==-t__

-I-i'+---I----

~1.27) TYP

L

.016±.001 TYP
.154±.002 ~
(.406±.025)
(3.91±.051) 450±10
.015±.002
TYP
, 0 ° 10 10°
(.381±.051)
~ TYP ALL LEADS
_

.005~.O10

R (.127~.254) ~4 PLS

'fr-------·rr-----..,

i~JL---;t-I-./-;I~.

7°±1° TYP

~~' i~

==='=180=±='004=*1::::;1

.Q36± 002
(.914±:051)

008
-'
(.203)

I

I

r

(4.57±.102)

..

II
IL

.236±.004 --;_+-__
(5.99±.102)

.1

.029±.DOl REF
.028±.OOl
(.737±.025)
(.711±.025) REF

.006±.OO2
(.152±.051)

0° 10 6°
TYP ALL LEADS

~ MIN

LENGTH OF
(.356) FLAT AREA
TYP ALL LEAOS

8 LEAD S.O.I.C. (SA)

L
L

r

- 1 - 0.240 (6.096)
1

1

0.040 (1.016)
0.020 (0.508)

0.220 (5.566)

=<:=~~=====~
0.006 (0.152)
0.004 (0.102)

0.070 (1.778)
0.040 (1.016)

~

10 LEAD FLATPACK (FS)

16-15

.193±.Q02
(4.90±.051)

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

[OJ

0.310 (7.874)

0.710118.034) MAX-

_

0.280 ( 7 , 1 1 2 ) [
0.115 (2.921)
0.060 (1.524)

0.070 (1.778)_

if.li3ii fD.762i

~
..--

I~J-{}-{

l
~I ~I

I

HI

0.110 (2.794) _
0.090 (2.286)

r

_

I

~

H f-

0.060 (1.5241

~I

il.025 (0.635 ]
0.200 (5.08)

I

_

0 .200 (5.08)
MAX

t

0.015

(g::r
(0.203) I

I

ii:i25 (3.'i75)

_ _ _ 0.023 (0.584)
0.014 (0.356)

0.320 (8.128)1'
0.290 (7.366) •

I'

..

14 LEAD CERAMIC (DO)

[~~~~~] ~:~:~:

1

~

0.080 (1.524)
0.015 (0.381)

0.780 (19.812) MAX

~

0.240 (6.096)
~

'200--'('-5'08-)-+-J--'--~
MAX

r

t

~!

~~

!

11

ff!!3r.,,,

\~ (5'08):J~ lH~!: :r1~'L-15.

--

0.110 (2.794)
0.090 (2.286)

0.180 (4.572)
0.140 (3.556)

0.070 (1.778)
0.030 (0.762)

0.200
0.125 (3.175)

g:= l~~~~:

0.023 (0.584)
0.D15 (0.381)

14 LEAD CERDIP (JD)

n

0.265 (0.673)
0.250 (0.635)

1--0.550 REF-0.017

±

0.002

TYP

:d

I
'OTYP
•05O

+t

1.

0.385

r

0.055 (0.139)
0.045 (0.114)

lili::~TT

01
:',

.i i i

L

I

r==l

[0.007 (0.177)
0.004 (0.101)

t

LO.078 (0.198)
0.065 (0.165)

14 LEAD FLATPACK (FD-2)

14 LEAD FLATPACK (FD-1)

16-16

Lo.018 (0.457)
0.010 (0.254)

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

(.¢;J~::::~::]

r

- t 1-

.770 (19.558) MAX

l-.1

--

~0.310 ±

0.130 ± 0.005

",clJ L""~,, ~~~I .:::61

.090 (2.286)

.045 (1.143)

_

.015 (.3810)

~~~'~

14 LEAD PLASTIC (PD)

II:::]]
0.115 (2.921)
0.060 (1.524)

I

I.

0.310 (7.874)
0.280 (7.112)

0.810 (20.574) MAX-0.070 (1.778)_110.030 (0.762)
1I

r

0.200 (5.08)
MAX

~~~__

•

-r- Ur~, H ,'W H

H

~

)-\

I

0.060 (1.524)
0.025 (0.635) "] _
0.200 (5.08)
0.125 (3.175)

_

_

0.010

(7.874 ± 0.264)

I~

0.023 (0.584)
0.014 (0.356)

16 LEAD CERAMIC (DE)

16-17

~

t

(8.128)
0.290 (7.366)

J
r--r-r-"

.J., I

0.Q15
(0.381)

!I" (~'.~)!.1

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

[~~~~]
~.,~ -~ L

j

'"''''

.2-00-'-(s-.O-SI--I--mmm1
MAX
•

t

t

g:~~ :~:~~~: I
~

~

~ ~ J~
-=====r~1 :~:~~~:
~:~~~

L
1

0.180 (4.572)
0.140 (3.556)

QJ.!.Q. (2.794)
0.090 (2.286)

J' j'

O~i~~O(~:i~~)

0.070 (1.778)
0.030 (0.7621

0.023 (0.584)
if.015 (0.381)

1\ (
y'-lS.

0.400 (10.16)
0330 (8382) . ..

-

16 LEAD CERDIP (JE)

4

0.050

TYP
I

1

1.045-------<01'1

I

I

j T='i

0.016
,0.002

I

i•

lr

~ ~"~too
W~

,___-1..

I

I
I
,

:..

I,

·i

i

!

I

L
,~

I i
0.063

MAX. ----+j

0.370 , 0.003

16 LEAD FLATPACK (FE-2)

16·18

,0.001
0.005

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

R

·OOOMAX

(25.4)

0.380 (9.662)
D.3OO (7.62) - ,

I

0.290

I-~A~)

•

0.019 (0.483)

Jo:o15(G.381)
-

t

I

+

t

0.400 MAX
(10.16)

t

*

0.056 (1.::971
- [ - 0 . 2 8 0 (7.112) 0.045 (1.1430 .040 (1.016)

L ========~1§0§.2§46§(6§.2~23=)~==!r
1

L

0.006 (0.152)
0.003 (0.076)

0.080 (2.0321
0.040 (1.016)

0.020 (0.508)

~

16 LEAD FLATPACK (FE-1)

I

~,::j:[~::~::]
FO.770MAX~

t

19.668

.060 (1.524)

0.130

%

3.302

%

,

I

0.006
0.127

.015L~r--------i------r-!-B-

1!!
I

I!
I- ~
I

r-+i

:~ Gl

:=

L ~I

.1601064)
.100 (2.540)

I--

l!:~~l :g~~ l:~l

16 LEAD PLASTIC (PE)

16-19

.015(.:JI1l
.008 (.2031

l
-15.

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

r-0.910

(:.~4) MAX~

[[
JJ
"~,,~,
It
l J

~

=
= (1.778)
0.070

0.110
0.090 (2.286)

L-

g. ;~~ l~·.~~~)

r=MAjX

0.030 (0.762)

~T~==~j!
¥¥¥¥ ¥¥¥1 I ..,,~.~~

0.115 (2.921)
0.060 (1.524)

0.060 (1.524) 0.008 (0.203)
0.025 (0.635):

-t-

0.200 (5.08)
0.125 (3.175)

I

~

0.023 (0.584)
0.014 (0.356)

:

I

I

0.320 (8.128) _
0.290 (7.366)

18 LEAD CERAMIC (DN)

-

[~~~~~]
I---

MAX
*
.~~'"

mNmW
U
1

0.060 (1.524)
0.015 (0.381),

--

0.900 (22.860) MAX--.I

-!

,

t-

~

0.110 (2.794) 0.070 (1.778)
0.090 (2.286) 0.030 (0.762)

-i

1_
I

0.200 (5.08)
0 .125 [3.'i'i5j I

0.023 (0.584)
0.015 (0.381)

18 LEAD CERDIP (IN)

16-20

I-

0.310
0.260
(7.874)
(6.604)

,1t "'"''''''
0.140 (3.556f

+ ---.--

0.320
0.290
(8.128)
(7.366)

~

I

0.015 ... 11--

0.008
(0.381)
(0.203)

II
'!

~"-15.

_ _ 0.400 (10.16) _
0.330 (8.382)

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

PIN ONE INDICATOR

f

.."'t' ' :

~~~=::n::::!!!~~~.-f

0.050 TVP
0.315 (8.001) \+---+\
(1.2701
0.950 • 0.050
0.005 ± 0.002
- ( 2 4 . 1 3 0 ' 1.271
(0.127 • 0.0501)

J

,., ,. , ,
0.026 REF
(0.6351

=~=E~~~::;f

=+=t

18 LEAD FLATPACK (FN)

.1

.~~=
.

.

L

•060'.005

067 +.006
-.007}

:L"

f 1:.00&+.002
-.001

-.£.010

i

S"~-:.r

U

•
.230

t

M~.

;r

019

.019
••002

18 LEAD FLATPACK (FN-2)

16-21

•

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

11B

,.000

PIN NUMBER I ~

(2.64)

~

+-(~·~)l

I ~~.

0.017

D

~0.400
::r(1·r
~
(0.127)

L~~::iiiF.::i~~!-~==4

rL

0.005
(0.0127)

0.063
(0.160)

J

lO.020
(0.051)

18 LEAD FLATPACK (FN-3)

~~:~.[~:

~:

:-=-=-=-:
: :

fl

•

0.310 ± 0.010
7.874 ± 0.264

.920 MAX
23.388

]

•

I

.130 ± .006

J:==3.30~2r'27~D

t
0.110 (2.794) 0.070 (1.7181
0.090 (2.286) 0.030 (0.762)

0.022 (0.5591
0.018 (0.457)

.160 (4.064)
.100 (2.540)

d

r+-l

:~: tf'~~:

1f-15'

18 LEAD PLASTIC (PN)

16-22

IIID~OI!..
PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

-

[~~~~~~]
1-----1.025 (26.035)
.200 (5.08)

•

t

0.060 (1.524)

~

0.310
0.260
(7.874)
(6.6041

MAx-I

~ tf .-J.l.LMAX
(4.46)

MAX

0.015 (0.381)

1

II
II
---+

"

----I ~ ~ ~
0.110 (2.794) 0.070 (1.778)
0.090 (2.286) 0.030 (0.762)

r
-0.320
0.290
(8.128)
(7.366)

0.200 (5.OB) I
0.125 (3.175) II

~I

4--

0.023 (0.584)
Q015 (0.381Y

_

0.015 ... 1
O.OOB
II

1-

~':0'-15°
(0.203)
(0.381)

g:~g :~~~~:

_

20 LEAD CERDIP (JP)

0.310 : 0.010

---LC--::J

.260 : .010
6.36: .264

-rIo

--

1-7 .874 :0.264

•

~.~40MAX

26.416

_I

.130 : .006
3.302: .127

B-

~:~~Pml::~)
--~
1
L
__
==~_

oj

~

t

0.0;\~9) :::It~:! :~ri:!:L~1) ~

(2::) 0.070!1ml
0.090 (2.286) 0.030 (0.762) 0.018 (0.467)

0"-15"

20 LEAD PLASTIC (PP)

16-23

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

I'

(25.654)MAX~

~

I
nJ
r -~ H H 1-\)l.t11-1 1-1 1-1 1-1

0.200 MAX

I

I

---1.

(5.08i)

I

0.200 (5.080)

f

O.110(2.794~......

..

Jl

0.090 (2.286)
0.070 (1.778)
0.030 (0.762)

0.060(1.524)

0.060 (1.524)

~0.008(0.203)

I 0.320 (8.128)
-- 0.290(7.366)

0.023(0.584)
0.014 (0.356)

20 LEAD SIDE BRAZED (GP)

r

1.100 (27.940) MAX~

[[
"]]'~~I
I
I~MA1X J~ (1~::i_

=0.070
= 1'.7781....

I

- -

-Ltm--m---'
T
-JI

0.110 (2.794)
0.090 (2.286)

I

ii.1i3O 0.762

X+:::;::==!:t==lt~l~
II

-t-

Q...!l9. (3.302!
0.070 (1.778

t 0.060 (1.624)
t

0.025 (0.635)
0.200 (5.08)

-

~ (0.584)

If.125 (3.176)

0.014 10.356}

22 LEAD CERAMIC (OF)

16·24

-

Q&l2!0.3gM· ...0.008 0.2

i
i
I0.420 (10.6BB)) ~
I

I

'li:39O (9.906

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

l

I--~
L
~

,- - --

r--

g:~~

0.200 (5.08)
0.125 (3.175)

11 g:~~g I~:~~:I

~,

1•260 (32.004) MAX

---j

0.180

(4.~ II

Jl

I L lI
I I
I

~

I

0.110 (2.794)
0.090 (2.286)

0.070 (1.778)
0.030 (0.762)

r

r

0.420(10.668)
0.390(9.906)

I

0.008 I
(0:203)

'

0.510(12.954)J
0.440(11.176)

0.023 (0.584)
0.015 (0.381)

22 LEAD CERDIP (JF)

~1.290 (32:~)

[

MAX-i

--]

~__

~

1_

0.0;0-!.!.:lli1

1J

_ , .....,
0.225 (5.713)

-

0.570 (14.478)-

--II- Mt

g:~gtli~~:'mf=o.7~)I~~-+-~t+---t--Ir----l--l----'I
0.115 (2.921)
0.060 (1.524)

_11_
0.023 (0.584)
0.014 (0.356)

0.015 (0.381) _ II-0.008 (0.203)
- II -

i

0.2:Js.08)
0.125 (3.175)
0.060 (1.524) 0.025 (0.635)

I

24 LEAD CERAMIC (DG)

16-25

Ii

0.620 (15.748)
0.590 (14.986)-

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

0.620 (15.75)
0.590 (14.966)... 0.550 (13.970) ...
0.510 (12.954)

-

-

1.290 (32.766) M A X -

.175
(4.45)
MAX

g:g~~(~:52~)m-- -m~
t

.200 (5.06)

MAX

~

o.koo

!

(5.08)
0.125 (3.175) ~I

"

--

"

.-

~

0.015 (0.361) -II....·
0.008 (0.203)
"

!~0'-15.

II!I

j

I

·

~ '~=:t:t=:::f\\

--

n- I I

~

....- --+ ...--,

0.110 (2.794) 0.070 (1.718)
0.090 (2.286) 0.030 (0.762)

0.023 (0.584)
0.015 (0.381) _

0.700 (17.780)_
0.630 (16.002)

24 LEAD CERDIP (JG)

0.620 (15.75)
-0.590 (14.966)0.550 (13.970) ...
... 0.510 (12.954)
- 1 . 2 9 0 (32.766) M A X _ ~

M!..rrO~m!:=~mri~~3
'!

g:~~ (~~i~~)J

J- ____\ . .,

0.110 (2.794) 0.070 (1.778)
0.090 (2.286) 0.030 (0.762)

0.015 (0.381) _
0.008 (0.203)

~!\

!I

0.023 (0.584)
0.015 (0.381) _

0.700 (17.780)~
0.630 (16.002)

24 LEAD CERDIP WITH WINDOW (JG/W)

16-26

.-

r

0'-15·

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

0.055 (l.397)j

[:006 (0.162)
Q.Oii3 (0.076)

0.090 (2.286)J

if.046 (1.143)

LO.04O

(1.016)
0.010 (0.264)

24 LEAD FLATPACK (FG)

-.-L[==]

0.&35 ± 0.016
13.588 ,. 0.381

T

0.810 ± 0.010
15.484 ,. 0.254

__

--

Fu.-~",

jft~~m+f--~
I L
I!!

r--'

.110g.~!

.0ii0 • 6

.
JL~~~
~-J\
'iOO (2.540)

-00-15"

.000P.524)
.046 1.143)

.023~
.016 r.3IftO)

24 LEAD PLASTIC (PG)

16-27

•

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

I'

-r-I

0.200 MAX

(5.OsOj
0.125

(r

(25:6s4)t.tAX:---I

U

I

~

0.060 (1.524)

H

nil

I

H H H H t-I t-I t-I

I

75 )

0.110(2.794)
0.090 (2.286) -+

--.-1.
0025(0635)

I

JL

I-

.

0.015(0.381)
0.008 (0.203)

•

0.023(0.584)
0.014 (0.356)

-

I

I

0.320(8.128)
0.290(7.366)

I--

0.070 (1.778)
0.030 (0.762)

20 LEAD SIDE BRAZED (GI)

D (
F ,-, M"--lc,oo,:: ~~
--~·I

.~,

1;:%','0'1:.

~__

M"

1

"D~mrr;~trmn=: ~

~~J!

h i

0.100
(2.54

,Jl:t L: ': ~:~ :

I

0.610 ± 0.010j
(15.49 ± 0.25)

±
±

0.005
0.13)

0.018
(0.46

±
±

0.002 TYP
0.05)

0.050 TYP
(1.27)

28 LEAD CERAMIC (01)

16-28

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

0.620 (15.75)

I-- 0.570 l14.47Il-

!

0.060 11.5241
0.3811

ii.iii5

.2---'--C:1x5.08)--'--1--'-1

f

~

-

-~

-m
J

-

-- -

1.475 (37.4651 MAX

0.175
(4.4461

r=(~~:~7°l

MAX

~-

l

II

h

P=
J L ~ J~--' =,W-+~:~~
jy~15.
1;:::1

0.110 (2.7941
0.090 (2.286)

0.060 (1.5241

li]45 [f."i;m

0.023 (0.58421
0.015 (0.38101

L

0.680 (17.2721
G:61li (15.494)

28 LEAD CERDIP (JI)

-.-L[==]
F ±

~0.61O:t 0.010--

o.l53II:t 0.015
13.e8. ,. 0.381

1

16.48 ,. 0.26

__

--

l.470MAX

37.34

• ,166,. ,010

3.94,. .25

.oeo~

B~J::~r,.-----.:=r----.,.
A

J L ~ J~w

.110 ~7941
.090 2.2861

.060 !1.6241
.046 (1.1431

.m !1sBfoI
.
.023

28 LEAD PLASTIC (PI)

16·29

5~ l.-r~

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

-i-----f----+----t----;--

'j

1.430
1 - - - - - - (36.322)MAX

0.200 MAX
(5.080)

t

0.610(15.494)

---!I

0.570(14.478) _

0.115 (2.921)
0.060 (1.524) ~

t
0.060 (1.524)J
0.025 (0.635)

0.125 (3.175)

JLO~84)

0.110(2.794)
0.090 (2.286)

0.014 (0.356)

0.070 (1.778)
0.030 (0.762)

L

0.015(0.381)
0.008 (0.203)
0.620(15.748)=:J
0.590 (14.986)

28 LEAD SIDE BRAZE (GI)

-1-----+--+---+---;--

~

0=-.::-:11':"5(~2.-::92::-1);--0.060(1.524) ~

r'-----

'j

2.020
(51.3'iiii)MAX

0.200 MAX
(5.080)

t

---!I

0.620(15.748)
0.590(14.986) _

t
0.060 (1.524)J
0.025 (0.635)

JL

0.110(2.794)
0.090 (2.286)

0.125 (3.175)

~

0.023(0.584)
0.014 (0.356)

0.070 (1.778)
0.030 (0.762)

40 LEAD SIDE BRAZED (GL)

16-30

L

0.015(0.381)
0.008 (0.203)
0.620(15.748)=:J
0.590 (14.986)

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

~

2.0~~.308) _______

_1 _
I

!!J.g!!(2.5401

~nD~
'"="--r=-= = = = 1--....
0.520 _
(13.208)
SQUARE

_11_

0.020 (5.080)
0.050 (1.270)

0.166
0.050 (4.191)
(1.270) MAX.
TYP.

I

+~:-~m~F~~

J~ -I~

0.06011.§701
• 0.010 O. 64

0.018 (0.457)
• 0.002 (0.061)

.,L

(3.175)

II
I

I

0600
I
1--(1Ii.24O) _ I
I
REF.
I

1

MIN .

40 LEAD CERAMIC DUAL-IN-LINE (DL)

.225

(5.71~·015 (0.381)

"j

UlJ1J1J1 .fU=iJ1J1lM

II--M

P=lTI¥-~-p
L-I ~~:(W.2~iJ)+
JI
'V

0.160(4.064)
0.100 (2.540)

r-l

I

0.110 (2.794)
0.090 (2.286)

I--

0.090 (1.524)
0.045 (1.143)

L

j

~'

I

0.023 (0.5842)
0.015 (0.3610)

(1

0 ....15·

7)

~::,'~ (1~:!e!)

40 LEAD CERDIP (JL)

DI
16·31

PACKAGE OUTLINES

All rlimensions given in inches and (millimeters).

I

III

TOP

VIEW

~40 --t~-J"
---,

PIN NO.1

--

20

I

---'

INDEX

18

PlATING
TI£ lARS

I
BACK

1

VIEW

tI.812
(0.1041 R TYP

IJI40
(1.D1e) TYP
~PINNo.l

INDEX

;....:r0.1011
(2.&40) REF

IIJI2S
(I1.1III141" REF

NOTE 1: Finish: Gold plated 60 micro Inch.. minimum thlckn... over nickel plated.
2: Pin number 1 connected to die attach pad ground.

40 PIN LEADLESS CHIP CARRIER (LL)

16-32

.D~Dl!.
PACKAGE OUTLINES

-.-L[_ ]

All dimensions given in inches and (millimeters).

0.53. " 0.01.
13.69

:!:

0.610 ± 0.010

•

15.49::t:: 0.26

.38
.156

-t
0.025

F2.~~AX~ 3"9:~025
62,58

t=-m~r1W+t~~~
L~L~'

J

0.060 (1.5241
±0.020 (.511

h'

0.018 ~ TYP.
0.020 (0.5081

0.160
(4.0641
MIN.

0.012 (0.3051 TYP.
0.001 (0.0251

0.100
(2.5401

40 LEAD PLASTIC (PL)
.543:~~:
1 _ - - - - ( 1 3.• ~)Z PLCS - - - - - 1
.....--- .394±.D08 2 PLeS - - - - +
11.0.0.21

mutM. DlA
(1.1'0.1)

"

- - ' .014>.004 TYP

Fi'="'---. (0.35'0.1)

1S°:t3'

TYP

~m,I

A!!UI!yyp
(0.36".1)

(~:l!:':~1 R yyp

f

~

(O.hO.1)

~

I- I .04U.OIZ TYP

NOTE 1: PART MUST COMPLY TO SPECIFICATION.
2: DIMENSIONS IN PARENTHESIS ARE IN MILLIMETERS.
3: PART IS SYMMETRICAL ABOUT THE CENTER LINES
(CLlSHOWN.

~

(0.I6±0.061 TYP

11."0.31

44 LEAD PLASTIC FLATPACK (M44)

16-33

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

I

Il~ .,~:.

................,.......

.....",.-

0.050 , 0.010
(1.27' 0.25)

r-

I

I

2 400 0 024
0.085 , 0.009
(tiO.96" 0.61) ~~(2.16 ± 0.23)

4=mo: :=rmmn=: I
~~.j~ JL J[ LO;:.::~~~~J
!

h!

0.610' 0.010
(15.49 , 0.25)

~;.: ! ~:~

~~: : g:~f

~i~~) TYP

TYP

48 LEAD CERAMIC (048)

-+---t--- + - - - - t - - - - t - -

0.115(2.92"
0.060(1.524)

----r-=*

0.225
(5.715)MAX

t

r'-----

'I

2.430
(s1.722)MAX

0.200 MAX
(5.080)

t

0.610(15.494)
0.570 (14.478)

j

+

~

0.060 (1.524) ]
0.025(0.635)

I

JL

0.110(2.794)
0.090 (2.286)

---r

0.125 (3.175)

0.023(0.584)
0.014 (0.356)

0.070 (1.778)
0.030 (0.762)

48 LEAD SIDE BRAZED (GM)

16·34

L

0.015 (0.381)
0.008 (0.203)

0.620(15.748)~

0.590 (14.986)

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

J15 (2.921)
.060 (1.524)

I

I--.910 (23.114)
I
.870 (22.098)

(82.0421
MAX

j

~ '::W=r
~ .•
= TI' :~~
--11_ --I
t

(~:~~l

.110 (2.794) _

.090 (2.286)

.023 (.584)
.014 (.3561

.200 (5.080)
.125 (3.175)

_
.070 (lorn)
.030 (.762)

64 LEAD SIDE BRAZED (GX)

I

TtilS METALLIZED AREA IS
CONNECTED TO DIE AnACH

.840 so ±

.085 ± .009

.ooe
THIS METALLIZED SURFACE TO BE
FUlT WITHIN .002 Tift

PAD.
34 33

0

.. ..

li! ~

•

~:l ~:l CHAMFER

31 32
0

.oso TYP

0

Iii

li!

~~ ~~YENDOR'SOPTION

~
DETAIL..\

' - - - - - - - - - U O O ± .010 TOL NON A C C U M I - - - - - - - - - - i

64 LEAD DIP

III
16·35

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).
DATUM PlANE

...mL.

(2.14)

~

2PLCS

B

~2PLCS

i1~)2PLCSl

1 Ar-

1
-"IlL
(25.15 I

~

1

lnnnnn~-

··t

'PlCS

~3)

-~

-Lh
T

....Il1..

(3.221 t: 0.1

(23.18)

1

~
~
~

A

(0.38)

~

2SlDES

~

2PlCS

I

~Typt

(0.81210.861)

'Uwuuuu,

J
SEATING PLANE

----

(0.101)

68 LEAD CONTACT (PLCC)

16-36



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