1987_Microcomputer_Products_Vol_1 1987 Microcomputer Products Vol 1
User Manual: 1987_Microcomputer_Products_Vol_1
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NEe
NEe Electronics Inc.
VOL 1 OF2
MICROCOMPUTER
PRODUCTS
1987
DATA BOOK
SINGLE-CHIP PRODUCTS
;
. ,
.
NEe
NEe Electronics Inc.
1987
MICROCOMPUTER
DATA BOOK
SINGLE-CHIP PRODUCTS
VOL 1 OF2
August 1986
NECEL-000175
Stock No. 500100
©1986 NEC Electronics Inc./Printed in U.S.A.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Electronics Inc. The information in this document is subject to change without notice. Devices sold by NEC
Electronics Inc. are covered by the warranty and patent indemnification provisions appearing in NEC Electronics Inc.
Terms and Conditions of Sale only. NEC Electronics Inc. makes no warranty, express, statutory, implied, or by
description, regarding the information set forth herein or regarding the freedom of the described devices from patent
infringement. NEC Electronics Inc. makes no warranty of merchantability orfitness for any purpose. NEG Electronics
Inc. assumes no responsibility for any errors that may appear in this document. NEC Electronics Inc. makes no
commitment to update or to keep current the information contained in this document.
NEe
ii
NEe
I
E
GENERAL INFORMATION
QUALITY AND RELIABILITY
I
I
I
I
4-BIT. SINGLE-CHIP MICROCOMPUTERS
8-BIT. SINGLE-CHIP MICROCOMPUTERS
i6-BIT. SINGLE-CHIP MICROCOMPUTERS
LCD PERIPHERALS
~
DEVELOPMENT TOOLS
E
PACKAGING INFORMATION
iii
t-{EC
iv
ttiEC
TABLE OF CONTENTS
Section 1 - General Information
Page
Introduction ....................' ....................................... r' ••••••••••••••••••••••••• 1-3
Ordering Information ............................................................................. 1-3
Part Numbering System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-3
4-Bit, Single-Chip Microcomputer Selection Guide .................................................. 1-4
8-Bit, Single-Chip Microcomputer Selection Guide .................................................. 1-7
16-Bit, Single-Chip Microcomputer Selection Guide ................................................. 1-9
CMOS LCD Peripheral Selection Guide ............................................................ 1-9
,uPD7500 Series Hardware Development Tool Selection Guide ...................................... 1-10
,uPD75000 Series Hardware Development Tool Selection Gu ide ..................................... 1-10
,uPD7800 Series Hardware Development Tool Selection Guide ...................................... 1-11
,uPD78000 Series Hardware Development Tool Selection Guide ..................................... 1-11
,uPD70320/322 Hardware Development Tool Selection Guide ....................................... 1-11
,uPD8048 Series Hardware Development Tool Selection Guide ...................................... 1-11
MD-086 Series Microcomputer Development System Selection Guide ............................... 1-12
MD-910TM Character Display Terminal Development System Selection Guide ....................... 1-12
PG1000 PROM Programmer Selection Guide ...................................................... 1-12
Ordering Procedure for ROM-Based Microcomputer Products ...................................... 1-13
ROM Code Submission (Form No. NEC-0000071) .................................................. 1-14
Section 2 - Quality and Reliability
Introduction ...................................................................................... 2-3
Technology Description ......................................... ;................................. 2-3
Reliability Testing ................................................................................. 2-3
Failure Rate Calculation and Prediction ............................................................ 2-6
Reliability Test Results ............................................................................ 2-7
NEC's Goals on Failure Rates ...................................................................... 2..;7
Infant Mortality Failure Screening .................................................................. 2-8
Life Tests ........................................................................ . . . . . . . . . . . . . . . .. 2-8
Built-in Quality and Reliability .................................................................... 2-10
Approaches to Total Quality Control .............................................................. 2-10
Summary and Conclusion ........................................................................ 2-12
Section 3 - 4-Bit, Single-Chip Microcomputers
,uPD7500 Series
,uPD7500H/H-E
,uPD7501
,uPD7502/03
,uPD7506
,uPD7507/08
,uPD7507H/08H
,uPD7507S
,uPD7508A
,uPD7514
,uPD7516H
,uPD7519/19H
,uPD7527 A/28A
,uPD7533
,uPD7537 A/38A
pPD7554/64
,uPD7556/66
,uPD75104/106/108
pPD75P108
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Microcomputers .................................................... 3-3
Microcomputers for ,uPD7500-Series Evaluation ...................... 3-31
Microcomputer with LCD Controller/Driver .......................... 3-45
Microcomputers with LCD Controller/Driver ......................... 3-59
Microcomputer .................................................... 3-75
Microcomputers ................................................... 3-89
Microcomputers .................................................. 3-109
Microcomputer ................................................... 3-123
Microcomputer with FIP® Driver ................................... 3-141
Microcomputer with LCD Controller/Driver ......................... 3-155
Microcomputer with FIP® Controller/Driver ......................... 3-175
Microcomputers with FIP® Controller/Driver ........................ 3-199
Microcomputers with FIP® Driver .................................. 3-229
Microcomputer with A/D Converter ................................ 3-243
Microcomputers with FIP® Driver .................................. 3-263
Microcomputers with Serial I/O .................................... 3-277
Microcomputers with Comparator .................................. 3-295
Microcomputers .................................................. 3-313
Microcomputer with On-Chip EPROM .............................. 3-325
FIP is the registered trademark for NEC's fluorescent indicator panel (vacuum fluorescent display).
v
TABLE OF CONTENTS
NEe
Section 4 - a-Bit, Single-Chip Microcomputers
pPD78C05A/06A
pPD7807/08/09
pPD78P09
pPD7810/11
pPD78C10/C11/
C14
pPD7810H/11 H
pPD78PG11
pPD78310/312
pPD8035HL/48H
pPD80C35/C48,
pPD48
pPD8039HLl49H,
IlPD8749H
IlPD80C39H/49H,
Il PD4 9H
IlPD80C40H/50H,
IlPD50H
IlPD8041 AH,
IlPD8741A
IlPD80C42
IlPD8748H
Page
High-End CMOS Microcomputers ............................................... 4-3
High-End NMOS Microcomputers with Comparator and 8K ROM ................. 4-23
High-End NMOS Microcomputer with Comparator and 8K EPROM ................ 4-51
NMOS Microcomputers with A/D Converter ..................................... 4-75
CMOS Microcomputers with A/D Converter .................................... 4-101
NMOS Microcomputers with A/D Converter ....................................
High-End NMOS Microcomputer with Piggyback EPROM .......................
CMOS Microcomputers, Real-Time Control Oriented ............................
High-Speed HMOS Microcomputers ...........................................
CMOS Microcomputers ........................................................
4-129
4-155
4-175
4-201
4-213
High-Speed HMOS Microcomputers ........................................ ~ .. 4-235
High-Speed CMOS Microcomputers ........................................... 4-249
High-Speed CMOS Microcomputers ............ ; .............................. 4-271
NMOS Microcomputers with Universal PPI ..................................... 4-293
CMOS Microcomputer with Universal PPI ...................................... 4-307
High-Speed NMOS Microcomputer with UV EPROM ............................ 4-325
Section 5 - ie-Bit, Single-Chip Microcomputers
IlPD70320/322
CMOS Microcomputers (V25™)
5-3
V25 is a trademark of NEC Corporation.
Section e - LCD Peripherals
IlPD6307
IlPD6308
IlPD7225
IlPD7227
IlPD7228
IlPD72030
LCD Row Driver ................................................................ 6-3
LCD Column Driver ........................................................ ; .... 6-7
CMOS, Intelligent, Alphanumeric LCD Controller/Driver ......................... 6-11
CMOS, Intelligent, Dot-Matrix LCD Controller/Driver ............................. 6-21
CMOS, Intelligent, Dot-Matrix LCD Controller/Driver ............................. 6-29
CMOS, Intelligent, LCD Controller .............................................. 6-39
Section 7 - Development Tools
IlPD7500 Series Hardware Development Tools ...................................................... 7-3
IlPD7500 Series Hardware Development Tool Selection Guide ..................................... 7-3
EVAKIT-7500B .................................................................................. 7-4
pPD75000 Series Hardware Development Tools ..................................................... 7-7
EVAKIT-75X .................................................................................... 7-7
IlPD7800 Series Hardware Development Tools ...................................................... 7-9
IlPD7800 Series Hardware Development Tool Selection Guide ...............................•..... 7-9
EVAKIT-87AD .................................................................................. 7-9
EVAKIT-87LC ................................................................................. 7-10
IE-7809-M ..................................................................................... 7-11
IE-87AD-M .................................................................................... 7-11
IE-7811H-M .................................................................................... 7-12
IE-78C11-M .................................................................................... 7-12
IlPD78000 Series Hardware Development Tools .................................................... 7-15
IE-78310-R .................................................................................... 7-15
pPD70320/322 Hardware Development Tools ...................................................... 7-17
IE-70322 ...................................................................................... 7-17
vi
NEe
TABLE OF CONTENTS
Section 7 - Development Tools (cont)
JlPD8048 Series Hardware Development Tools .....................................................
EVAKIT-84C-1 .................................................................................
EVAKIT-80C42 ................................................................................
EV-9001/EV-9002 ..............................................................................
SE-80C50H System Evaluation Board ...........................................................
V-Series Hardware Development Tools ............................................................
IE-70108/70116 .................................................................................
JlPD7500 Series Software Absolute Assembler Development Tools ..................................
ASM75 ........................................................................................
JlPD75000 Series Software Relocatable Assembler Development Tools ..... , .........................
RA75X ........................................................................................
JlPD7800 Series Software Absolute Assembler Development Tools ..................................
ASM87 ........................................................................................
JlPD7800 Series Software Relocatable Assembler Development Tools ................................
RA87 ..........................................................................................
JlPD78000 Series Software Relocatable Assembler Development Tools ...............................
RA310 .........................................................................................
JlPD70320/322 Software Relocatable Assembler Development Tools .................................
Evakit Communication Program ..................................................................
MD-086 Series Microcomputer Development Systems ..............................................
MD-086 Floppy and Hard Disk Drive System .....................................................
MD-910TM Character Display Terminal Development Tool ..........................................
PG1000 PROM Programmer ......................................................................
Page
7-19
7-19
7-19
7-20
7-20
7-21
7-21
7-23
7-23
7-25
7-25
7-27
7-27
7-29
7-29
7-31
7-31
7-33
7-35
7-37
7-37
7-43
7-45
Section 8 - Packaging Information
Package/Device Cross Reference .................................................................. 8.. 3
20-Pin Plastic Shrink DIP (300 mil) ................................................................. 8-5
20-Pin Plastic SO (Small Outline) (300 mil) ......................................................... 8-5
24-Pin Plastic Shrink DIP (300 mil) ................................................................. 8-6
24-Pin Plastic SO (Small Outline) (300 mil) ......................................................... 8-6
28-Pin Plastic DIP (600 mil) ........................................................................ 8-7
28-Pin Plastic Shrink DIP (400 mil) ................................................................. 8-7
40-Pin Plastic DIP (600 mil) ........................................................................ 8-8
40-Pin Plastic Shrink DIP (600 mil) ................................................................. 8-8
40-Pin Ceramic Piggyback DIP (600 mil) ........................................................... 8-9
40-Pin Cerdip with Window (600 mil) ............................................................... 8-9
42-Pin Plastic DIP (600 mil) ....................................................................... 8-10
42-Pin Plastic Shrink DIP (600 mil) ................................................................ 8-10
42-Pin Ceramic Piggyback DIP ................................................................... 8-11
44-Pin Plastic Miniflat ............................................................................ 8-11
52-Pin Plastic Miniflat ............................................................................ 8-12
54-Pin Plastic Miniflat ............................................................................ 8-12
54-Pin Plastic Miniflat (Inverted leads) ............................................................. 8-13
64-Pin Plastic Shrink DIP (750 mil) ................................................................ 8-13
64-Pin Plastic Miniflat ............................................................................ 8-14
64-Pin Plastic QUiP .............................................................................. 8-14
64-Pin Shrink Cerdip with Window ................................................................ 8-15
64-Pin Ceramic QUIP with Window ............................................................... 8-15
64-Pin Ceramic Piggyback QUiP .................................................................. 8-16
68-Pin Plastic Leaded Chip Carrier (PLCC) ........................................................ 8-16
80-Pin Plastic Miniflat ............................................................................ 8-17
84-Pin Plastic Leaded Chip Carrier (PLCC) ........................................................ 8-17
vii
NEe
TABLE OF CONTENTS
Numerical Index
Device
Page
JlPD49~
............................................. 4-249
JlPD50H ............................................. 4-271
JlPD6307 ............................................... 6-3
JlPD6308 ............................................... 6-7
JlPD7225 .............................................. 6-11
JlPD7227 .............................................. 6-21
JlPD7228 .............................................. 6-29
JlPD7500 Series ....................................... 3-3
JlPD7500H ............................................ 3-31
JlPD7500H-E ......................................... 3-31
JlPD7501 .............................................. 3-45
JlPD7502 .............................................. 3-59
JlPD7503 .............................................. 3-59
JlPD7506 .............................................. 3-75
JlPD7507 .............................................. 3-89
JlPD7507H ........................................... 3-109
JlPD7507S ........................................... 3-123
JlPD7508 .............................................. 3-89
JlPD7508A ........................................... 3-141
JlPD7508H ........................................... 3-109
JlPD75CG08 .......................................... 3-89
JlPD75CG08H ....................................... 3-109
JlPD7514 ............................................. 3-155
JlPD7516H ........................................... 3-175
JlPD75CG16H ....................................... 3-175
JlPD7519 ............................................. 3-199
JlPD7519H ........................................... 3-199
JlPD75CG19 ......................................... 3-199
JlPD75CG19H ....................................... 3-199
JlPD7527 A .......................................... 3-229
JlPD7528A .......................................... 3-229
JlPD75CG28 ........................................ 3-229
JlPD7533 ............................................ 3-243
JlPD75CG33 ........................................ 3-243
JlPD7537 A .......................................... 3-263
JlPD7538A .......................................... 3-263
JlPD75CG38 ... .'.................................... 3-263
JlPD7554 ............................................ 3-277
JlPD7556 ............................................ 3-295
JlPD7564 ............................................ 3-277
JlPD7566 ............................................ 3-295
viii
~~~
P~e
JlPD78C05A ........................................... 4-3
JlPD78C06A ........................................... 4-3
JlPD7807 .............................................. 4-23
JlPD7808 .............................................. 4-23
JlPD7809 .............................................. 4-23
JlPD78P09 ............................................ 4-51
JlPD7810 .............................................. 4-75
JlPD7810H ........................................... 4-129
JlPD78C10 ........................................... 4-101
JlPD7811 .............................................. 4-75
JlPD7811 H ........................................... 4-129
JlPD78C11 ........................................... 4-101
JlPD78C14 ........................................... 4-101
JlPD78PG11 ......................................... 4-155
JlPD8035HL ........................................ 4-201
JlPD80C35 ........................................... 4-213
JlPD8039HL ........................................ 4-235
JlPD80C39H ........................................ 4-249
JlPD80C40H ........................................ 4-271
JlPD8041 AH ........................................ 4-307
JlPD80C42 .......................................... 4-321
JlPD8048H .......................................... 4-201
JlPD80C48 ........................................... 4-213
JlPD8049H .......................................... 4-235
JlPD80C49H ........................................ 4-249
JlPD80C50H ........................................ 4-271
JlPD8741A .......................................... 4-307
JlPD8748H .......................................... 4-339
JlPD8749H .......................................... 4-235
JlPD70320 ............................................. 5-3
JlPD70322 ............................................. 5-3
JlPD72030 ............................................ 6-39
JlPD75104 ............................................
JlPD75106 ............................................
JlPD75108 ............................................
JlPD75P108 .........................................
3-313
3-313
3-313
3-325
JlPD78310 ............................................ 4-175
JlPD78312 ............................................ 4-175
NEe
GENERAL INFORMATION
1-1
II
GENERAL INFORMATION
Section 1 - General Information
NEe
Page
Introduction ................................................................. 1-3
Ordering Information ......................................................... 1-3
Part Numbering System ...................................................... 1-3
4-Bit, Single-Chip Microcomputer Selection Guide ............................. 1-4
8-Bit, Single-Chip Microcomputer Selection Guide ............................. 1-7
16-Bit, Single-Chip Microcomputer Selection Guide ............................ 1-9
CMOS LCD Peripheral Selection Guide ........................................ 1-9
pPD7500 Series Hardware Development Tool Selection Guide .................. 1-10
pPD75000 Series Hardware Development Tool Selection Guide ................. 1-10
pPD7800 Series Hardware Development Tool Selection Guide .................. 1-11
pPD78000 Series Hardware Development Tool Selection Guide ................. 1-11
pPD70320/322 Hardware Development Tool Selection Guide ................... 1-11
pPD8048 Series Hardware Development Tool Selection Guide .................. 1-11
MD-086 Series Microcomputer Development System Selection Guide ........... 1-12
MD-910TM Character Display Terminal Development System Selection Guide .. 1-12
PG1000 PROM Programmer Selection Guide .................................. 1-12
Ordering Procedure for ROM-Based Microcomputer Products .................. 1-13
ROM Code Submission (Form No. NEC-0000071) ............................. 1-14
1-2
t-{EC
GENERAL INFORMATION
Introduction
Ordering Information
The NEC microcomputer data book is issued in two
volumes.
Part numbers for ordering microcomputer products
are listed on the first page of each data sheet. NEC's
part numbers consist of four elements as shown in the
example that follows.
• Volume 1: Single-Chip Products
• Volume 2: Microprocessors, Peripherals, and DSP
Products
NEC offers a wide variety of single-chip microcomputer
products for you to choose from. Volume 1 covers
4-bit, 8-bit, and 16-bit microcomputers plus LCD peripheral products, both NMOS and CMOS, in an assortment of packages. This extraordinary selection provides greater design alternatives with products that
truly fit your needs in data processing, communications, instrumentation, industrial, and consumer applications.
Part Numbering System
f.1P
0
7810H
CW
~ Package type
Plastic DIP = C
Plastic shrink DIP = CS,
CT, CU, CW
Cerdip = 0
Shrink cerdip = OW
Plastic SO = G
Plasticminiflat=G-OO, G-12,
G-22, G-R, G-F, G-1 B
Plastic QUIP = G-36
Volume 1 is divided into the following sections.
1. General Information. This section includes ordering
information, product selection guides, and ROM Code
submission procedures.
2. Quality and Reliability. The NEC concepts of designed-in quality and total quality control as a company-wide activity are discussed here.
L..-_ _
1 . -_ _ _
L..-_ _
Device identifier (alphanumeric)
Device type: 0 = Digital MOS
NEC monolithic silicon integrated circuit
3. Four-Bit Single-Chip Microcomputers. This section
covers the 7500 Series, the 75000 Series, and the
cost-effective, low-end mini-microcomputers known
as 755x/756x.
4. Eight-Bit Single-Chip Microcomputers. The 8-bit
products include the popular 80xx/87xx and 80Cxx
Series together with the high-end 7800 and 78000
Series.
5. Sixteen-Bit Single-Chip Microcomputers. The 16bit microcomputers are CMOS products, type 703201
70322.
6. LCD Peripherals. Peripherals include LCD controller-driver products for alphanumeric, dot-addressable,
and large-area displays.
7. Development Tools. A comprehensive line of development hardware and software products support NEC's
single-chip microcomputer families.
8. Packaging. This section provides dimensioned
package drawings and a cross-reference from package
type to device numbers.
1-3
II
NEe
GENERAL INFORMATION
4-Bit, Single-Chip CMOS Microcomputer Selection Guide
Clock
(MHz)
Supply
Voltage
ROM
(V)
(X8)
RAM
IX4)
liD
Package
46
Plastic QUIP
64
Device
Description
JlPD7500HG-36
Microcomputer
0.7
4.5 to 5.5
External
256
JlPD7500H-EG-36
Microcomputer
0.2
4.5 to 5.5
External
256
46
Plastic QUIP
64
JlPD7501G-12
Microcomputer with
LCD Controller/Driver
0.4
2.5 to 6.0
1K
96
24
Plastic Miniflat
64
JlPD7502G-12
Microcomputer with
LCD Controller/Driver
0.4
2.7 to 6.0
2K
128
23
Plastic Miniflat
64
JlPD7503G-12
Microcomputer with
LCD Controller/Driver
0.4
2.7 to 6.0
4K
224
23
Plastic Miniflat
64
JlPD7506C
Microcomputer
0.4
2.5 to 6.0
1K
64
22
Plastic DIP
28
JlPD7506CT
Microcomputer
0.4
2.5 to 6.0
1K
64
22
Plastic Shrink DIP
28
JlPD7506G-00
Microcomputer
0.4
2.5 to 6.0
1K
64
22
Plastic Miniflat
52
JlPD7507C
Microcomputer
0.4
2.5 to 6.0
2K
128
32
Plastic DIP
40
JlPD7507CU
Microcomputer
0.4
2.5 to 6.0
2K
128
32
Plastic Shrink DIP
40
JlPD7507G-00
Microcomputer
0.4
2.5 to 6.0
2K
128
32
Plastic Miniflat
52
JlPD7507HC
Microcomputer
4.19
2.7 to 6.0
2K
128
32
Plastic DIP
40
JlPD7507HCU
Microcomputer
4.19
2.7 to 6.0
2K
128
32
Plastic Shrink DIP
40
JlPD7507HG-22
Microcomputer
4.19
2.7 to 6.0
2K
128
32
Plastic Miniflat
44
JlPD7507SC
Microcomputer
0.4
2.2 to 6.0
2K
128
20
Plastic DIP
28
JlPD7507SCT
Microcomputer
0.4
2.2 to 6.0
2K
128
20
Plastic Shrink DIP
28
JlPD7508C
Microcomputer
0.4
2.5 to 6.0
224
32
Plastic DIP
40
JlPD7508CU
Microcomputer
0.4
2.5 to 6.0
4K
4K
224
32
Platic Shrink DIP
40
JlPD7508G-00
Microcomputer
0.4
2.5 to 6.0
4K
224
32
Plastic Miniflat
52
JlPD75CG08E
Piggyback EPROM
Microcomputer
0.4
4.5 to 5.5
4K
224
32
Ceramic DIP
40
JlPD7508HC
Microcomputer
4.19
2.7 to 6.0
4K
224
32
Plastic DIP
40
JlPD7508HCU
Microcomputer
4.19
2.7 to 6.0
4K
224
32
Plastic Shrink DIP
40
JlPD7508HG-22
Microcomputer
4.19
2.7 to 6.0
4K
224
32
Plastic Miniflat
44
JlPD75CG08HE
Piggyback EPROM
Microcomputer
4.19
4.5 to 5.5
4K
224
32
Ceramic DIP
40
JlPD7508AC
Microcomputer with
FIP Driver
0.4
2.7 to 5.5
4K
208
32
Plastic DIP
40
JlPD7514G-12
Microcomputer with
LCD Controllier IDriver
0.5
2.7 to 6.0
4K
256
31
Plastic Miniflat
80
JlPD7516HG-12
Microcomputer with
FIP Controller/Driver
6.55
2.5 to 6.0
6K
256
53
Plastic Miniflat
64
JlPD7516HG-36
Microcomputer with
FIP Controller/Driver
6.55
2.5 to 6.0
6K
256
53
Plastic QUIP
64
JlPD7516HCW
Microcomputer with
FIP Controller/Driver
6.55
2.5 to 6.0
6K
256
53
Plastic Shrink DIP
64
JlPD75CG16HE
Piggyback EPROM
Microcomputer with
FIP Controller/Driver
6.55
4.5 to 5.5
6K
256
53
Ceramic QUIP
64
1-4
Pins
NEe
GENERAL INFORMATION
4-Bit, Single-Chip CMOS Microcomputer Selection Guide (cont)
Device
Description
(MHzl
Supply
Voltage
(VI
(X41
liD
jlPD7519G-12
Microcomputer with
FIP Controller / Driver
4.19
2.5 to 6.0
4K
256
53
Plastic Miniflat
64
jlPD7519G-36
Microcomputer with
FIP Controller/Driver
4.19
2.5 to 6.0
4K
256
53
Plastic QUIP
64
jlPD7519CW
Microcomputer with
FIP Controller/Driver
4.19
2.5 to 6.0
4K
256
53
Plastic Shrink DIP
64
jlPD75CG19E
Piggyback EPROM
Microcomputer with
FIP Controller/Driver
4.19
4.5 to 5.5
4K
256
53
Ceramic DIP
64
jlPD7519HG-12
Microcomputer with
FIP Controller /Driver
6.55
2.5 to 6.0
4K
256
53
Plasti Miniflat
64
jlPD7519HG-36
Microcomputer with
FIP Controller/Driver
6.55
2.5 to 6.0
4K
256
53
Plastic QUIP
64
jlPD7519HCW
Microcomputer with
FIP Controller / Driver
6.55
2.5 to 6.0
4K
256
53
Plastic Shrink DIP
64
jlPD75CG19HE
Piggyback EPROM
Microcomputer with
FIP Controller/Driver
6.55
4.5 to 5.5
4K
256
53
Ceramic DIP
64
jlPD7527AC
Microcomputer with
FIP Display
0.6
2.7 to 6.0
2K
128
35
Plastic DIP
42
jlPD7527 ACU
Microcomputer with
FIP Display
0.6
2.7 to 6.0
2K
128
35
Plastic Shrink DIP
42
jlPD7528AC
Microcomputer with
FIP Display
0.6
2.7 to 6.0
4K
160
35
Plastic DIP
42
jlPD7528ACU
Microcomputer with
FIP Display
0.6
2.7 to 6.0
4K
160
35
Plastic Shrink DIP
42
jlPD75CG28E
Piggyback EPROM
Microcomputer with
FIP Display
0.5
4.5 to 5.5
4K
160
35
Ceramic DIP
42
jlPD7533C
Microcomputer with
A/D Converter
0.5
2.7 to 6.0
4K
160
34
Plastic DIP
42
jlPD7533CU
Microcomputer with
A/D Converter
0.5
2.7 to 6.0
4K
160
34
Plastic Shrink DIP
42
jlPD7533G-22
Microcomputer with
A/D Converter
0.5
2.7 to 6.0
4K
160
34
Plastic Minflat
44
jlPD75CG33E
Piggyback EPROM
Microcomputer with
A/D Converter
0.5
4.5 to 5.5
4K
160
34
Ceramic DIP
42
jlPD7537AC
Microcomputer with
FIP Driver
0.6
2.7 to 6.0
2K
128
35
Plastic DIP
42
jlPD7537ACU
Microcomputer with
FIP Driver
0.6
2.7 to 6.0
2K
128
35
Plastic Shrink DIP
42
jlPD7538AC
Microcomputer with
FIP Driver
0.6
2.7 to 6.0
4K
160
35
Plastic DIP
42
jlPD7538ACU
Microcomputer with
FIP Driver
0.6
2.7 to 6.0
4K
160
35
Plastic Shrink DIP
42
Clock
ROM
RAM
(X81
Package
Pins
11
1-5
NEe
GENERAL INFORMATION
4-Bit, Single-Chip CMOS Microcomputer Selection Guide (cont)
ROM
RAM
(MHzl
Supply
Voltage
(VI
(X81
Clock
Device
Description
(X41
lID
Package
pPD75CG38E
Piggyback EPROM
Microcomputer with
FIP Driver
0.5
4.5 to 5.5
4K
160
35
Ceramic DIP
42
pPD7554CS
Microcomputer with
Serial 110
0.7
2.5 to 6.0
1K
64
16
Plastic Shrink DIP
20
pPD7554G
Microcomputer with
Serial 110
0.7
2.5 to 6.0
1K
64
16
Plastic SO
20
pPD7556CS
Microcomputer with
Comparator
0.7
2.5 to 6.0
1K
64
20
Plastic Shrink DIP
24
pPD7556G
Microcomputer with
Comparator
0.7
2.5 to 6.0
1K
64
20
Plastic SO
24
pPD7564CS
Microcomputer with
Serial 110
0.7
2.7 to 6.0
1K
64
15
Plastic Shrink DIP
20
pPD7564G
Microcomputer with
Serial 110
0.7
2.7 to 6.0
1K
64
15
Plastic SO
20
pPD7566CS
Microcomputer with
Comparator
0.7
2.7 to 6.0
1K
64
19
Plastic Shrink DIP
24
pPD7566G
Microcomputer with
Comparator
0.7
2.7 to 6.0
1K
64
19
Plastic SO
24
pPD75104CW
Microcomputer
4.19
2.5 to 6.0
4K
320
58
Platic Shrink DIP
64
pPD75104G-18
Microcomputer
4.19
2.5 to 6.0
4K
320
58
Plastic Miniflat
64
pPD75106CW
Microcomputer
4.19
2.5 to 6.0
(6016)
320
58
Plastic Shrink DIP
64
pPD75106G-18
Microcomputer
4.19
2.5 to 6.0
(6016)
320
58
Plastic Miniflat
64
pPD75108CW
Microcomputer
4.19
2.5 to 6.0
8K
512
58
Plastic Shrink DIP
64
Pins
pPD75108G-18
Microcomputer
4.19
2.5 to 6.0
8K
512
58
Plastic Miniflat
64
pPD75P108CW
Microcomputer with
On-Chip OTPROM
4.19
2.5 to 6.0
8K
512
58
Plastic Shrink DIP
64
pPD75P108DW
Microcomputer with
On-Chip EPROM
4.19
2.5 to 6.0
8K
512
58
Plastic Shrink DIP
64
pPD75P1 08G-1 8
Microcomputer with
On-Chip OTPROM
4.19
2.5 to 6.0
8K
512
58
Plastic Miniflat
64
1-6
NEe
GENERAL INFORMATION
a-Bit, Single-Chip Microcomputer Selection Guide
Device
Description
Clock
(MHz)
JlPD78C05AG-36
CMOS Microcomputer
JlPD78C06AG-12
Supply
Voltage
(V)
ROM
IX8)
RAM
IX8)
110
Package
6.25
2.6 to 6.0
External
128
46
Plastic QUIP
64
CMOS Microcomputer
6.25
2.5 to 6.0
4K
128
46
Plastic Miniflat
64
JlPD7807CW
NMOS Microcomputer
with Comparator
12
4.5 to 5.5
External
256
28
Plastic Shrink DIP
64
JlPD7807G-36
NMOS Microcomputer
with Comparator
12
4.5 to 5.5
External
256
28
Plastic QUIP
64
JlPD7808CW
NMOS Microcomputer
with Comparator
12
4.5 to 5.5
4K
256
40
Plastic Shrink DIP
64
JlPD7808G-36
NMOS Microcomputer
with Comparator
12
4.5 to 5.5
4K
256
40
Plastic QUIP
64
JlPDl809CW
NMOS Microcomputer
with Comparator
12
4.5 to 5.5
8K
256
40
Plastic Shrink DIP
64
JlPD7809G-36
NMOS Microcomputer
with Comparator
12
4.5 to 5.5
8K
256
40
Plastic QUIP
64
JlPD78P09R
NMOS Microcomputer
with Comparator
12
4.5 to 5.5
EPROM
8K
256
40
Ceramic QUIP
with Window
64
JlPD7810CW
NMOS Microcomputer
with AID Converter
12
4.5 to 5.5
External
256
32
Plastic Shrink DIP
64
JlPD7810G-36
NMOS Microcomputer
with AID Converter
12
4.5 to 5.5
External
256
32
Plastic QUIP
64
JlPD78C10CW
CMOS Microcomputer
with AID Converter
12
4.5 to 5.5
External
256
32
Plastic Shrink DIP
64
JlPD78C 1OG-1 B
CMOS Microcomputer
with AID Converter
12
4.5 to 5.5
External
256
32
Plastic Miniflat
64
JlPD78C10G-36
CMOS Microcomputer
with AID Converter
12
4.5 to 5.5
External
256
32
Plastic QUIP
64
JlPD78C10L
CMOS Microcomputer
with AID Converter
12
4.5 to 5.5
External
256
32
PLCC
68
JlPD7810HCW
NMOS Microcomputer
with AID Converter
15
4.5 to 5.5
External
256
32
Plastic Shrink DIP
64
JlPD7810HG-36
NMOS Microcomputer
with AID Converter
15
4.5 to 5.5
External
256
32
Plastic QUIP
64
JlPFD7811 CW
NMOS Microcomputer
with AID Converter
12
4.5 to 5.5
4K
256
44
Plastic Shrink DIP
64
JlPD7811 G-36
NMOS Microcomputer
with AID Converter
12
4.5 to 5.5
4K
256
44
Plastic QUIP
64
JlPD78C11 CW
CMOS Microcomputer
with AID Converter
12
4.5 to 5.5
4K
256
44
Plastic Shrink DIP
64
JlPD78C11G-1 B
CMOS Microcomputer
with AID Converter
12
4.5 to 5.5
4K
256
44
Plastic Miniflat
64
JlPD78C11G-36
CMOS Microcomputer
with AID Converter
12
4.5 to 5.5
4K
256
44
Plastic QUIP
64
JlPD78C11L
CMOS Microcomputer
with AID Converter
12
4.5 to 5.5
4K
256
44
PLCC
68
Pins
1-7
11
NEe
GENERAL INFORMATION
a-Bit, Single-Chip Microcomputer Selection Guide (cont)
Clock
(MHz)
Supply
Voltage
ROM
RAM
(V)
(XS)
Device
Description
(XS)
I/O
Package
IlPD7811 HG-36
NMOS Microcomputer
with AID Converter
15
4.5 to 5.5
4K
256
44
Plastic QUIP
64
Piggy Back EPROM
NMOS Microcomputer
with AID Converter
12
4.5 to 5.5
4K
256
44
Ceramic QUIP
64
CMOS Microcomputer
with AID Converter
12
4.5 to 5.5
16K
256
44
Plastic Shrink DIP
64
IlPD78C14G-1 B
CMOS Microcomputer
with AID Converter
12
4.5 to 5.5
External
256
44
Plastic Miniflat
64
IlPD78C14G-36
CMOS Microcomputer
with AID Converter
12
4.5 to 5.5
External
256
44
Plastic QUIP
64
CMOS Microcomputer
with AID Converter
12
4.5 to 5.5
External
256
44
PLCC
68
Pins
CMOS Microcomputer
12
4.5 to 5.5
External
256
28
Plastic Shrink DIP
64
IlPD7831 OG-1 B
CMOS Microcomputer
12
4.5 to 5.5
External
256
28
Plastic Miniflat
64
IlPD78310G-36
CMOS Microcomputer
12
4.5 to 5.5
External
256
28
Plastic QUIP
64
CMOS Microcomputer
12
4.5 to 5.5
External
256
28
PLCC
68
CMOS Microcomputer
12
4.5 to 5.5
8K
256
40
Plastic Shrink DIP
64
IlPD78312G-1 B
CMOS Microcomputer
12
4.5 to 5.5
8K
256
40
Plastic Miniflat
64
IlPD78312G-36
CMOS Microcomputer
12
4.5 to 5.5
8K
256
40
Plastic QUIP
64
CMOS Microcomputer
12
4.5 to 5.5
8K
256
40
PLCC
68
EPROM Microcomputer
12
4.5 to 5.5
8K
256
40
Plastic QUIP
64
HMOS Microcomputer
6
4.5 to 5.5
External
64
27
Plastic DIP
40
CMOS Microcomputer
6
4.5 to 5.5
External
64
27
Plastic DIP
40
HMOS Microcomputer
11
4.5 to 5.5
External
128
27
Plastic DIP
40
CMOS Microcomputer
12
2.5 to 6
External
128
27
Plastic DIP
40
CMOS Microcomputer
12
2.5 to 6
External
256
27
Plastic DIP
40
NMOS Microcomputer
with Universal PPI
11
4.5 to 5.5
1K
64
18
Plastic DIP
40
CMOS Microcomputer
with Universal PPI
12
4.5 to 5.5
2K
128
18
Plastic DIP
40
CMOS Microcomputer
with Universal PPI
12
4.5 to 5.5
2K
128
18
Plastic Miniflat
44
IlPD78P312G-36
IlPD80C48G-00
IlPD80C49G-00
1-8
HMOS Microcomputer
6
4.5 to 5.5
1K
64
27
Plastic DIP
40
CMOS Microcomputer
6
2.5 to 6.0
1K
64
27
Plastic DIP
40
CMOS Microcomputer
6
2.5 to 6.0
1K
64
27
Plastic Miniflat
52
CMOS Microcomputer
6
2.5 to 6.0
1K
64
27
Plastic Miniflat
44
HMOS Microcomputer
11
4.5 to 5.5
2K
128
27
Plastic DIP
40
CMOS Microcomputer
12
2.5 to 6.0
2K
128
27
Plastic DIP
40
CMOS Microcomputer
12
2.5 to 6.0
2K
128
27
Plastic Miniflat
52
CMOS Microcomputer
12
2.5 to 6.0
2K
128
27
Plastic Miniflat
44
NEe
GENERAL INFORMATION
B-Bit, Single-Chip Microcomputer Selection Guide (cont)
Clock
(MHz)
Supply
Voltage
(V)
ROM
RAM
(X8)
Device
Description
(X8)
liD
JlPD80C50HC
CMOS Microcomputer
12
2.5 to 6.0
4K
256
27
Plastic DIP
Package
JlPD50HG-22
CMOS Microcomputer
12
2.5 to 6.0
4K
256
27
Plastic Miniflat
44
JlPD8741AD
NMOS Microcomputer
with Universal PPI
6
4.5 to 5.5
1K
64
18
Cerdip with
Window
40
JlPD8748HC
NMOS Microcomputer
with UV EPROM
11
4.5 to 5.5
1K
64
27
Plastic DIP
40
JlPD8748HD
NMOS Microcomputer
with UV EPROM
11
4.5 to 5.5
1K
64
27
Cerdip with
Window
40
JlPD8749HC
HMOS Microcomputer
11
4.5 to 5.5
2K
128
27
Plastic DIP
40
JlPD8749HD
HMOS Microcomputer
11
4.5 to 5.5
2K
128
27
Cerdip with
Window
40
Pins
40
11
i6-Bit, Single-Chip Microcomputer Selection Guide
Device
Description
JlPD70320G-12
CMOS Microcomputer
Clock
(MHz)
Supply
Voltage
(V)
ROM
RAM
(X8)
(X8)
liD
10
4.5 to 5.5 V
16K
256
32
Package
Pins
Plastic Miniflat
80
JlPD70320L
CMOS Microcomputer
10
4.5 to 5.5 V
16K
256
32
PLCC
84
JlPD70322G-12
CMOS Microcomputer
10
4.5 to 5.5 V
16K
256
32
Plastic Miniflat
80
JlPD70322L
CMOS Microcomputer
10
4.5 to 5.5 V
16K
256
32
PLCC
84
Clock
(MHz)
Supply
Voltage
(V)
Active
(rnA)
CMOS LCD Peripheral Selection Guide
No. of
Rows
No. of
Column
Power Dissipation
Standby
(rnA)
Package
Pins
Device
Description
JlPD6307G-F
LCD Row Driver
32
2.5
4.5 to 5.5
Plastic Miniflat
54
JlPD6307G-R
LCD Row Driver
32
2.5
4.5 to 5.5
Plastic Miniflat
Reverse leads
54
JlPD6308G-F
LCD Column Driver
40
2
4.5 to 5.5
1.2
Plastic Miniflat
54
JlPD6308G-R
LCD Column Driver
40
4.5 to 5.5
1.2
Plastic Miniflat
Reverse leads
54
JlPD7225G-00
LCD Controlier/Driver
2.7 to 5.5
0.1
Plastic Miniflat
52
JlPD7227G-12
LCD Controller 1Driver
+5
0.2
Plastic Miniflat
64
JlPD7228G-12
LCD Controller 1Driver
+5
0.2
0.02
Plastic Miniflat
80
JlPD72030G-12
LCD Display Controller
+5
5
0.001
Plastic Miniflat
64
4
32
0.2
40
8/16
42/50
1.1
1-9
NEe
GENERAL INFORMATION
pPD7500 Series Hardware Development Tool Selection Guide
Part
Number
Emulator
Add·On Board
IRequired)
System
Evaluation Board
IlPD7501
EVAKIT·7500B
EV7514
SE·7514A
IlPD7502
EVAKIT·7500B
EV7514
SE·7514A
IlPD7503
EVAKIT·7500B
EV7514
SE·7514A
IlPD7506
EVAKIT·7500B
IlPD7507
EVAKIT·7500B
IlPD7507H
EVAKIT·7500B
IlPD7507S
EVAKIT·7500B
EPROM
Device
SE·7508
IlPD75CG08E
EV7508H
IlPD75CG08HE
SE·7508
IlPD7508
EVAKIT·7500B
IlPD7508A
EVAKIT·7500B
IlPD7508H
EVAKIT·7500B
EV7508H
IlPD7514
EVAKIT·7500B
EV7514
IlPD75CG08E
SE·7508
IlPD75CG08HE
SE·7514A
IlllPD7516H
EVAKIT·7500B
EV7500FIP
IlPD75CG16HE
IlPD7519
EVAKIT·7500B
EV7500FIP
IlPD75CG19E
IlPD7519H
EVAKIT·7500B
EV7500FIP
IlPD75CG19HE
IlPD7527
EVAKIT·7500B
EV7528
IlPD75CG28E
IlPD7528
EVAKIT·7500B
EV7528
IlPD75CG28E
IlPD7533
EVAKIT·7500B
EV7533
IlPD75CG33E
IlPD7537
EVAKIT·7500B
EV7528
IlPD75CG38E
IlPD7538
EVAKIT·7500B
EV7528
IlPD7554
EVAKIT·7500B
EV7554A
SE·7554A
IlPD7556
EVAKIT·7500B
EV7554A
SE·7554A
IlPD7564
EVAKIT·7500B
EV7554A
SE·7554A
IlPD7566
EVAKIT·7500B
EV7554A
SE·7554A
pPD75000 Series Hardware
Development Tool Selection Guide
Device
Description
EV75108
Add·on board
EV75208
Add·on board
1-10
IlPD75CG38E
NEe
GENERAL INFORMATION
pPD7800 Series Hardware Development Tool Selection Guide
Part
Number
Emulator
Real-time
Trace
Board
jlPD7BC05A
EVAKIT-B7LC [Note 1]
jlPD7BC06A
EVAKIT-B7LC
jlPD7B07
IE-7B09-M
jlPD7BP09R
jlPD7BOB
IE-7B09-M
jlPD7BP09R
jlPD7B09
IE-7B09-M
jlPD7B10
EVAKIT-B7AD [Note 1]
IE-B7AD-M
IE-7B11H
jlPD7BC10
IE-7BC11-M
jlPD7B11
EVAKIT-B7AD [Note 1]
IE-B7AD-M
jlPD7B11H
IE-7B11H
IE-7BC11-M
jlPD7BC14
IE-7BC11-M
System
Evaluation
Board
EVB7LCRTT
EV7BC06A
SE-7BC06
EVB7LCRTT
EV7BC06A
SE-7BC06
EPROM
Device
jlPD7BP09R
jlPD7B10H
jlPD7BC11
Add-on
Board
I
EVB7ADRTT
jlPD7BPG11E
jlPD7BPG11E
EVB7ADRTT
jlPD7BPG11 E [Note 2]
Notes:
(1) Addresses O-OFFFH access memory on the Evakit only.
(2) Special selected parts.
pPD78000 Series Hardware
Development Tool Selection Guide
pPD8048 Series Hardware
Development Tool Selection Guide
System
Evaluation
Board
Description
Device
IE-310-R
Stand-alone in-circuit emulator
pPD70320/322 Hardware Development
Tool Selection Guide
Device
Description
IE-70322
Portable stand-alone in-circuit emulator
Part
Number
Emulator
jlPDB035H
EVAKIT-B4C-1
jlPDB04BH
EVAKIT-B4C-1
jlPDB039H
EVAKIT-B4C-1
jlPDB049H
EVAKIT-B4C-1
jlPDBOC39H
EVAKIT-B4C-1
jlPDBOC4B
EVAKIT-B4C-1
jlPDBOC35
EVAKIT-B4C-1
jlPDBOC49H
EVAKIT-B4C-1
jlPDBOC40H
EVAKIT-B4C-1
jlPDBOC50H
EVAKIT-B4C-1
jlPDBOC42
EVAKIT-BOC42
EPROM
Device
jlPDB74BH*
jlPDB749H*
SE-BOC50H
SE-BOC50H
SE-BOC50H
jlPDB741A
*jlPD8748H and jlPD8749H are both available in erasable windowed
packages or in the economical one time programmable plastic
package.
Conversion Board
Function
EV-9001-64
64-pin QUIP to 64-pin shrink DIP
EV-9002-42
42-pin standard DIP to 42-pin shrink DIP
EV-9002-40
40-pin standard DIP to 40-pin shrink DIP
EV-9002-2B
2B-pin standard DIP to 2B-pin shrink DIP
1-11
GENERAL INFORMATION
MD·086 Series Microcomputer
Development System Selection Guide
Device
Description
MD-086FD-10
MD-086 series, floppy-disk based system
MD-086HD-10
MD-086 series, floppy-hard-disk based system
MD-086DK
Hard-disk upgrade for MD-086FD-10
MD-910TM
Character display terminal
MD·910TM Character Display Terminal
Development System Selection Guide
Device
Description
MD-910TM
Character display terminal
PG 1000 PROM Programmer
Selection Guide
Device
Description
PG1003
Plug-in personality module
PG1005
Plug-in personality module
1-12
t-{EC
ttiEC
GENERAL INFORMATION
Ordering Procedure for
ROM-Based Microcomputer Products
The devices listed below are ROM-based microcomputer products.
pPD70322
pPD7501
pPD7502
pPD7503
pPD7533
pPD7537A
pPD7538A
pPD7554
pPD78C11
pPD78C14
pPD78312
pPD8041AH
pPD7506
pPD7507
pPD7507H
pPD7507S
pPD7556
pPD7564
pPD7566
pPD75104
pPD80C42
pPD8048H
pPD80C48
pPD8049H
pPD7508
pPD7508H
pPD7514
pPD7516H
pPD75106
pPD75108
pPD75206
pPD75208
pPD80C49H
pPD80C50H
pPD8355
pPD7519
pPD7519H
pPD7527A
pPD7528A
pPD78C06A
pPD7809
pPD7811
pPD7811H
Please use the following ordering guidelines. Contact
your local sales representative for assistance and to
obtain the necessary forms.
A complete order must include:
o
o
o
o
o
o
Two copies of ROM code information contained in
either the equivalent memory EPROMs or EPROMbased microcomputers.
ROM code submission form (provided by your
local sales representative); see next three pages.
Your engineering specifications, if applicable.
Please ignore this item if NEC has already reviewed
your specification.
Mask charge payment.
Liability agreement for ROM-based work-in-progress. The NEC form, "ROM-Based Microprocessors
Agreement," can be obtained from your local sales
representative.
Your purchase order.
NEC Electronics Inc. will return the ROM code patterns
in the EPROM media together with a code listing and a
ROM-code verification form to you. Please return the
verification form to verify the code in the EPROM
provided by NEC. NEC guarantees that the final
product will contain the same code you verified.
Summary:
Step 1
0 Customer submits a complete order, including the items listed above.
Step 2
0 NEC returns ROM pattern to customer
together with a ROM-code verification form
and a code listing.
Step 3
0 Customer verifies code received from N EC
and returns verification form.
Step 4
0 NEC acknowledges customer order and
begins production.
1-13
I
NEe
GENERAL INFORMATION
NEe
NEe Electronics Inc.
ROM CODE
SUBMISSION
Date _ _ _ _ _ _ _ _ __
To: NEC Electronics Inc.
Corporate Headquarters
401 Ellis Street, P.O. Box 7241
Mountain View, CA 94039
Attn:
ROM Code Administrator
We are ready to place a purchase order for our
Customer Part Number
'
your
NEC Part Number
'
and are
submitting two copies of the ROM code on the following medium/media. (Please check all applicable boxes.)
o pPD2764
o pPD27128
0
0
pPD70P322
pPD75P108
0
0
0
0
0
pPD78P09
pPD78P312
o pPD77P20
pPD8741A
pPD8748H
pPD8749H
o pPD8755A
This device should be manufactured as follows: (Please check all applicable boxes.)
To our engineering specification # _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
With special marking: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
o
o
o With the I/O port loading options (available only on the devices listed on this form).
o
Lead type (if applicable) Bent
Straight _ _ _ _ _ __
Application _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
o
NEC Electronics Inc.
Please return the processed ROM code to the following individual for our verification.
Name
Company
Division
Shipping Address (not a P.O. Box. please)
City
State
ZIP
Telephone Number
Customer
Please send this form and the items listed below in a package clearly marked "ROM CODE Enclosed" to the address
above.
•
•
•
•
•
Two copies of ROM code
Engineering specification, if applicable. Not required if NEC has already reviewed the specification.
Mask charge payment.
Signed "ROM-Based Microprocessors Agreement"
Purchase order
Form No. NEC-0000071 Rev. B 7/86
1-14
&1986 NEC Electronics Inc
NEe
GENERAL INFORMATION
NEe
pPD7519, pPD7519H, pPD7516H
Pin
lID Port Loading Option
50
51
52
53
Open drain
0
0
0
0
Pull-down
resistor to
VLOAD
0
0
0
0
54
55
56
57
0
0
0
0
0
0
0
0
Ta /5 a
T9 /5 9
T10 /5 10
T11 /S 11
0
0
0
0
0
0
0
0
T12 /S 12
T13 /S 13
T14 /5 14
T15 /S 15
0
0
0
0
.0
0
0
0
To
T1
T2
T3
0
0
0
0
0
0
0
0
T4
T5
T6
T7
0
0
0
0
0
0
0
0
pPD7527A, pPD7528A, pPD7537A, pPD7538A
Pin
POolINTO
lID Port Loading Option
o Direct connection (no
o Zero-crossing
zero-crossing detector)
Open drain
0
0
0
0
Pull-down
resistor to
VLOAD
0
0
0
0
P83
0
0
0
0
0
0
0
0
P90
P91
~
P93
0
0
0
0
0
0
0
0
P100
P101
P102
P103
0
0
0
0
0
0
0
0
P110
P111
P112
P113
0
0
0
0
0
0
0
0
P23-P21
P33-P30
P43-P40
P53-PSo
Plio
P81
P~
detector
I
pPD7554, pPD7564
Pin
I/O Port Loading Option
No Internal
resistor
0
0
0
0
POo
P01
P02
P03
Pull-up
resistor
0
0
0
0
Pull-down
resistor
0
0
0
0
Plio
P81
P82
P83*
N-chann'l.
open drain
0
0
0
0
CMOS. pushpull output
0
0
0
0
P100
P101
P102
P103
0
0
0
0
0
0
0
P110
P111
P112
P113
0
0
0
0
0
0
0
0
Oscillator
RESET
OR-oscillator
o No internal resistor
N-channel.
open-drain.
and pull-up
0
0
0
0
0
0
0
0
o External clock (7554 only)
o Pull-down resistor
• If P83 is used for CL2. the N-channel open-drain option should be
selected. In this case. P83 cannot function as a port.
Form No. NEC-0000071 Rev. 8 7/86
@1986 NEG Electronics Inc.
1-15
NEe
GENERAL INFORMATION'
t\fEC
pPD7556, pPD7566
Pin
pPD75104, pPD75106
I/O Port Loading Option
POo
P01
P02
P03
Pull-up
resistor
0
0
0
0
PUll-down
resistor
0
'0
0
0
No intarnal
resistor
0
0
0
0
P10
P11
P12
P13
0
0
0
0
0
0
0
0
0
0
0
0
N-channel.
open-drain
0
0
0
CMOS. pushpull output
0
0
0
PBo
PB1
PB2
PB3*
0
0
P90
P91
0
0
0
0
P100
P101
P102
P103
0
0
0
0
0
0
0
0
N-channel.
open-drain.
and pull-up
0
0
0
0
P110
P111
P112
P113
0
0
0
0
0
0
0
0
0
0
0
0
Pin
VREF
0
Comparator
input
0
0
0
0
DR-oscillator
Oscillator
o External clock (7556 only)
RESET
o No internal resistor
o Pull-down resistor
o No internal bias
o Internal bias
VREF
* If P83 is used for CL2. the N-channel open-drain option should be
selected. In this case. P83 cannot function as a port.
P120
P121
P122
P123
Open drain
0
0
0
0
Pull-up
resistor
0
0
0
0
P130
P131
P132
P133
0
0
0
0
0
0
0
0
P140
P141
P142
P143
0
0
0
0
0
0
0
0
Power-on reset flag
Power-on reset generator
1-16
DYes
o Yes*
o No
o No
* If power-on reset generator is selected. power-on reset flag must
be selected also.
pPDBOC4B
Pin
lID Port Loading Option
P1o-P17
P2o-P23
P24-P27
CMOS
(-5pA)
0
0
0
TTL-compatible
(-50pA)
0
0
0
pPDBOC49H,pPDBOC50H
lID Port Loading Option
Pin
POO-P07
P1o-P17
P24-P27
Form NO.NEC-0000071 Rev. B 7/86
lID Port Loading Option
CMOS
(-5pA)
0
0
0
No pull-up
resistor
0
0
0
TTL-compatible
(-50pA)
0
0
0
©1986 NEC Electronics Inc.
t-IEC
I
QUALITY AND RELIABILITY
2-1
QUALITY AND RELIABILITY
NEe
Section 2 - Quality and Reliability
Introduction ................................................................. 2-3
Technology Description ..............................................•....... 2-3
Reliability Testing ............................................................ 2-3
Failure Rate Calculation and Prediction ........................................ 2-6
Reliability Test Results ........................................................ 2-7
NEC's Goals on Failure Rates ................................................. 2-7
Infant Mortality Failure Screening ............................................. 2-8
Life Tests.................. , . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-8
Built-in Quality and Reliability.'; .............................................. 2-10
Approaches to Total Quality Control .......................................... 2-10
Summary and Conclusion ................................................... 2-12
2-2
NEe
QUALITY AND RELIABILITY
Introduction
Reliability Testing
As large-scale integration reaches a higher level of
density, reliability of devices imposes a profound
impact on system reliability. And as device reliability
becomes a major factor, test methods to assure acceptable reliability become more complicated. Simply
performing a reliability test according to a conventional method can not satisfy the demand i ng req u i rements for higher reliability. At these new, higher levels
of LSI density, it is increasingly difficult to activate all
the elements in the internal circuits. A different philosophy and methodology is needed for reliability assurance. Moreover, as integration density increases,
the degradation of internal elements in an LSI device is
seldom detected by measuring characteristics across
external terminals.
Reliability is defined as the characteristics of an item
expressed by the probability that it will perform a
required function under stated conditions for a stated
period of time. This involves the concept of probability,
definition of required function(s). and the critical
time used in defining the reliability.
In order to improve and guarantee a certain level of
reliability for large-scale integrated circuits, it is essential to build quality and reliability into the product.
Then, the conventional reliability tests are followed to
ensure that the product demonstrates an acceptable
level of reliability.
NEG has introduced the concept of total quality control
(TOG) across its entire semiconductor product line.
By adopting TOG, NEG can build quality into the
product and thus assure higher reliability. The concept
and methodology of total quality control are companywide activities involving workers, engineers, quality
control staffs, and all levels of management.
NEG has also introduced a prescreening method into
the production line that helps eliminate potentially
defective units. The combination of building quality in
and screening projected early failures out has resulted
in superior quality and excellent reliability.
Definition of a required function, by implication, treats
the definition of a failure. Failure is defined as the
termination of the ability of a device to perform its
required function. Furthermore, a device is said to
have failed if it shows inability to perform within
quaranteed parameters as given in an electrical
specification.
Discussion of reliability and failure can be approached
in two ways: with respect to systems or to individual
devices. The accumulation of normal device failure
rates constitutes the expected failure rate of the system
hardware. Important considerations here are the constant failure period, the early failure (infant mortality)
period, and overall reliability level. With regard to
individual devices, areas of prime interest include
specific failure mechanisms, failures in accelerated
tests, and screening tests.
Some of these failure considerations pertain to both
systems and devices. The probability of no failures in a
system is the product of the probability of no failure in
each of its components. The failure rate of system
hardware is then the sum of the failure rates of the
components used to construct the system.
Figure 1.
Reliability Life (Bathtub) Curve
Technology Description
Most large-scale integrated circuits utilize high-density,
MOS technology. State-of-the-art high performance
has been achieved by introducing fine-line generation
techniques. By reducing physical parameters, circuit
density and performance increase while active circuit
power dissipation decreases. The data presented here
shows that this advanced technology yields products
as reliable as those from previous technologies.
. . ____--____------__~ ::~:u~
Random Failure Period
~
Time_
83-003939A
2-3
IE
NEe
QUALITY AND RELIABILITY
Life Distribution
The fundamental principles of reliability engineering
predict that the failure rate of a group of devices will
follow the well-known bathtub curve in figure 1. The
curve is divided into three regions: infant mortality,
random failures, and wearout failures.
Infant mortality, as the name implies, represents the
early-life failures of devices. These failures are usually
associated with one or more manufacturing defects.
After some period of time, the failure rate reaches a low
value. This is the random failure portion of the curve,
representing the useful portion of the life of a device.
During this random failure period, there is a decline in
the failure rate due to the depletion of potential random
failures from the general population.
The wearout failures occur at the end of the device's
useful life. They are characterized by a rapidly rising
failure rate overtime as devices wear out both physically and electrically.
Thus, for devices that have very-long life expectancies
compared to those of systems, the areas of concern
will be the infant mortality and the random failure
portions of the population.
The system failure rates are related to the collective
device failure rates. In a given system, afterelimination
of the early failures, the system will be left to the failure
rate of its components. In order to make proper
projections of the failure rate in the operating environment, time-to-failure must be accelerated in tests in a
predictable way.
Failure Distribution at NEe
Integrated circuits returned to NEC from the field
underwent extensive failure analysis at NEC's Integrated Circuit Division.
Temperature, humidity, and bias tests are used for
testing the moisture resistance of plastic encapsulated
integrated circuits. NEG developed a special process
to improve the plastic encapsulation material. As a
result, moisture-related~thus packaging-related-failures have been drastically reduced.
As a preventive measure, NEC has introduced a special
screening procedure embedded in the production line.
A burn-in at an elevated temperature is performed for
100 percent of the lots. This burn-in effectively removes
the potentially defective units. In addition, improvement
of the plastic encapsulation material has lowered the
failures in a high-temperature and high-humidity
environment.
Figure 2.
Failure Distribution of MOS Integrated
Circuits
Percent Failures
20
40
60
80
100
Oxide
Deslroyed
Si02 Pattern
Defects
Bond·Wire
Peel or Cut
Metalization
Defects
Percent
Cumulative
Failures
Moisture
Penetration
Parameter
Degradation
Scratch
Chip/Peel/
Crack
Metalization
Corrosion
Other
First, approximately 50 percent of the field returns
were found to be damaged either from improper
handling or misuse of the devices. These units were
eliminated from the analysis. The remaining failed
units were classified by their failure mechanisms as
depicted in figure 2. These failures were then related to
the major integrated circuit failure mechanisms and to
their origins in a particular manufacturing step.
As shown in figure 2, the first four failure mechanisms
accounted for more than 90 percent of total failures. As
a result, NEC improved processes and material to
reduce these failures. Additionally, NEC introduced
screening procedures to detect and eliminate defective
devices.
2-4
63·Q03940A
NEe
QUALITY AND RELIABILITY
Accelerated Reliability Testing
As an example, assume that an electronic system
contains 1000 integrated circuits and can tolerate 1
percent system failures per month. The failure rate per
component is:
0.01 Failures
13.888 x 10-9 Failures/Hour
or 13.8888 FITs
720K Device Hours
where FIT
R = Ro exp(-Ea/kT)
where
Ro
A most common time-to-failure relationship involves
the effect of temperature, which accelerates many
physiochemical reactions leading to device failure.
Other environmental conditions are voltage, current,
humidity, vibration, or some combination of these.
Table 1 lists the reliability assurance tests performed at
NEC for integrated circuits.
Monthly NEe Reliability Tests
Test
life Test
High-temperature,
operating
High-temperature,
storage
MIL·STO-883
Method
Test Conditions
1005A, D
TA = 100 to 125°C
for 1000 hours
1008C
TA = 150°C for 1000 hours
High-temperature,
high-humidity test
TA = 85°C at 85% RH
for 1000 hours
Pressure cooker test
TA = 125°C at 2.3 atm
for 168 hours
Environmental Test
Soldering heat test
2031
(MIL-STD-750)
T = 260°C for 10 s
without flux
Temperature cycle
1010C
T = -65 to +150°C for
10 cycles
Thermal shock
1011A
T = 0 to 100°C for
15. cycles
Lead fatigue
2004B2
at 250 gm: 3 leads, 3 bends
Solderability
2003
T = 230°C for 5 s with flux
= Constant
Ea
k
= Activation energy in eV
T
= Absolute temperature in kelvin
= Failure units per 109 device hours
To demonstrate this failure rate, note that 13.8888 FITs
corresponds to one failure in about 7000 devices
during an operating test of 10,000 hours. It is quickly
apparent that a test condition is required to accelerate
the time-to-failure in a predictable and understandable
way. The implicit requirement for the accelerated
stress test is that the relationship between the accelerated stress testing condition and the condition of
actual use be known.
Table 1.
Temperature Effect. The effect of temperature that
concerns us is that which responds to the Arrhenius
relationship. This relates the reaction rate to temperature.
= Boltzmann's constant
= 8.617 x 10-5 eV/K
(K)
The significance of this relationship is that the failure
mechanisms of semiconductor devices are directly
applicable to it. A linear relationship between failure
mechanism and time is assumed.
Activation Energy. Associated with each failure mechanism is an activation energy value. Table 2 lists some
of the more common failure mechanisms and the
associated activation energy of each.
Table 2.
Activation Energy and Detection of Failure
Mechanisms
Failure Mechanism
Activation
Energy
Oxide defect
0.3 eV
Silicon defect
0.3 eV
Ionic contamination
1.0-1.35 eV
Electromigration
0.4-0.8 eV
Charge injection
1.3 eV
Gold-aluminum
interface
0.8 eV
Metal corrosion
0.7 eV
Detection
High-temperature operating
life test
High-humidity operating
life test
High-Temperature Operating Life Test. This test is
used to accelerate failure mechanisms by operating
the devices at an elevated temperatu re of 125 cC. The
data obtained is translated to a lower temperature by
using the Arrhenius relationship.
High-Temperature and High-Humidity Test. Semiconductor integrated circuits are highly sensitive to
the general accelerating effect of humidity in causing
electrolytic corrosion between biased lines. The hightemperature and high-humidity test is performed to
detect failure mechanisms that are accelerated by
these conditions. This test is effective in accelerating
leakage-related failures and drifts in device parameters
due to process instability.
2-5
NEe
QUALITY AND RELIABILITY
High-Temperature Storage Test. Another common test
is the high-temperature storage test in which devices
are sUbjected to elevated temperatures with no applied
bias. This test is used to detect mechanical problems
and process instability.
Environmental Test. Other environmental tests are
performed to detect problems related to the package,
material, susceptibility to extremes in environment,
and problems related to usage of the devices.
Acceleration Factor
The acceleration factor is the factor by which the
failure rate can be accelerated by increased temperature. This factor is derived from the Arrhenius
failure rate expression, resulting in the following form.
A = F1/F2
where
Failure Rate Calculation and Prediction
= exp[(Ea/k) x (1/T1
-1/T2)]
A = Acceleration factor
F2 = Failure rate at T 2
F1 = Failure rate at T1
Analysis of integrated circuit failure rates can serve
many useful purposes. For example, the early-life
failure rate helps establish a warranty period, while the
mature-life failure rate aids in estimating repair costs,
spare parts stock requirements, or product downtime.
Accurate prediction of failure rates can also be used for
process control.
In calculating the field reliability of an integrated
circuit, it is necessary to calculate the junction temperature. In general, the junction temperature will
depend on the ambient temperature, cooling, package
type, operating cycle time, and power dissipation of
the circuit itself. In these terms, the junction temperature (TJ) is expressed as:
The following sections describe the failure rate calculation and prediction methods used by NEC's
Integrated Circuit Division.
where
T J = TA + Pd Af 8JA
The Arrhenius Model
Most integrated circuit failure mechanisms depend to
some degree on temperature. This relationship can be
represented by the Arrhenius model, which includes
the effects of temperature and activation energy of the
failure mechanisms.
As applied to accelerated life testing of integrated
circuits, the Arrhenius model assumes that degradation
of a performance parameter is linear with time. Temperature dependence is taken to be the exponential
function that defines the probability of occurrence.
The relationship of failure rate to temperature is
expressed as:
F1
Where: F2
F1
Ea
k
T
= F2 exp[(Ea/k) x (1/T1 - 1fT2)]
= Failure rate at T2
= Failure rate at T1
= Activation energy in eV
= Boltzmann's constant
= Operating junction temperature in
kelvin (K)
The equation explains the thermal dependence of
integrated circuit failure rates and is used for derating
the resulting failure rate to a more realistic temperature.
2-6
TJ = Junction temperature
TA = Ambient temperature
Pd = Power dissipation
At = Air flow factor
8JA = Package thermal resistance
Table 3 lists derating factors of various failure mechanisms. This table is generated assuming that an accelerated test is performed at ajunction temperature of
125°C. The result is then derated to 55°C junction
temperature. The acceleration factor may then be
obtained by taking the inverse of the derating factor.
Table 3.
Derating Factors of Failure Mechanisms
Failure Mechanisms
Activation
Energy, eV
Derating Factor
Oxide defect
0.3
0.1546
Silicon defect
0.3
0.1546
Ionic contamination
1.0
0.001984
Electromigration
0.4
0.08307
Charge injection
1.3
0.0003067
Metal corrosion
0.7
0.01315
Gold-aluminum interface
0.8
0.006886
The acceleration of failure mechanisms in a highhumidity and high-temperature environment must be
expressed as a function not only of temperature but
also of humidity.
NEe
According to the reliability test statistics, the acceleration factor in such an environment can best be
approximated with Peck's model as follows.
A
where
= exp[(Ea/k) x (1/T1 -1/T2)] X (H2/H1)4.5
Ea = Activation energy
k = Boltzmann's constant
T
H
= Junction temperature
= Relative humidity
For example, the acceleration factor for high-humidity
and high-temperature or pressure cooker tests ranges
from 100 to 1000 times that of the normal operating
envi ron ment.
Failure Rate Calculation
As an example, suppose that product samples are
submitted to a 1000-hour life test at 125°C junction
temperature and two failures are encountered: one
oxide and one metalization defect. The sample size is
885 units.
Thus, the oxide failure rate is 0.11 percent per 1000
hours and the metalization failure rate is 0.11 percent
per 1000 hours. Therefore, the total failure rate at
125°C sumsto 0.22 percent per 1000 hours at 1K hours.
Failure Rate Prediction
To derate these failure rates to a normal operating
environment, use the derating factors listed in table 3.
Oxide failures = 0.11 x 0.1546 = 0.01701% per 1K hrs
Metal failures = 0.11 x 0.01315 = 0.00145%
per 1K hrs
Total failures = 0.01846% per 1K hrs
Note that the example above is a snapshot of the hightemperature life test performed on a particular lot. It is
not accumulated data that can be used to represent
overall reliability. This conservative illustration, however, shows that the failure rate in a normal operating
environment is approximately one-twelfth the failure
rate in a higher-temperature environment.
The failure rate prediction takes different activation
energies into account whenever the causes of failures
are known through performing failure analysis. In
some cases, however, an activation energy is assumed
in order to accomplish a quick first-order approximation. To yield a conservative estimate offailure rates,
NEC assumes an average activation energy of 0.7 eV
whenever the exact failure mechanism is not known.
QUALITY AND RELIABILITY
Reliability Test Results
Before introducing new technologies or products,
NEC's internal reliability goals must be attained. Several
categories of testing are used in the internal qualification program to assure that product reliability
meets NEC's reliability goals. Once the product is
qualified, its reliability level is regularly monitored in a
monthly reliability test.
NEe's Goals on Failure Rates
NEG's approach to achieving high reliability is to build
quality into the product, as opposed to merely screening out defective units. The use of distributed control
methods embedded in the production line, in conjunction with conventional screening methods, results
in the highest reliability at the lowest cost.
NEC's maximum failure rate goals for infant mortality
and long-term device operation are listed in table 4.
Table 4.
Infant Mortality and Long-Term Failure Rates
Type
Failure Rate
Percent/tODD Hours
Infant mortality
0.10 max
Long-term
1.2M device hours average
3.0M device hours average
0.02 max
0.01 max
Infant Mortality Failure Rate
The infant mortality goal for each product group is set
at 0.10 percent maximum. When a failure rate exceeds
this level, there is prompt remedial action.
Long-Term Failure Rate
The long-term failure rate goal is based on the
following conditions:
• A minimum of 1.2 million device hours at 125°C is
accumulated to resolve 0.02 percent per 1000 hours
at 55°C with a 60-percent confidence level.
• A minimum of 3 million device hours at 125°C is
accumulated to resolveO.01 percent per 1000 hours
at 55°C with a 60-percent confidence level.
2-7
IE
...
NEe
QUALITY AND RELIABILITY
Infant Mortality Failure Screening
Life Tests
It is logical to assume the integrated circuit that fails at
one tem peratu re wou Id also fai I at another tem peratu re,
except it would fail sooner at a higher temperature. As
can be expected, the failure rate is a function of
activation energy. Establishing infant mortality screening, therefore, requires knowledge of the likely failure
mechanisms and their associated activation energy.
The most significant difference between NEG's products and those of other integrated circuit manufacturers
is that NEG's have been prescreened for their infant
mortality defects. The products delivered to customers
are operating at the beginning of the random failure
region of the life curve. The life test data also reflects
this fact, as will be shown.
The most likely mechanisms associated with infant
mortality failures are generally manufacturing defects
and process anomalies. These generally consist of
contamination, cracked chips, wire bond shorts, or bad
wire bonds. Since these describe a number of possible
mechanisms, anyone of which might predominate at a
given time, the activation energy for infant mortality
might be expected to vary considerably.
The failure mechanism distribution from field failures,
as previously shown in figure 2, also contains a very
low percentage due to infant mortality. The majority of
failures are long-term life failures, and these can be
eliminated by stringent process control. Usually, these
failure mechanisms have low activation energy associated with them.
The effectiveness of a screening condition, preferably
at some stress level in order to shorten the time, varies
greatly with the failure mechanism being screened for.
Another factor is the economics of the screening
process introduced into the production line. Optimal
conditions and duration of a screening process will be
a compromise of these two factors.
For example, failures due to ionic contamination have
an activation energy of approximately 1.0 eV. Therefore, a 15-hour stress at 125°G junction temperature
would be the equivalent of approximately 90 days of
operation at a junction temperature of 55°G. On the
other hand, failures due to oxide defects have an
activation energy of approximately 0.3 eV, and a 15hour stress at 125°G junction temperature would be
the equivalent of approximately one week's operation
at 55°G junction temperature. As indicated by this, the
condition and duration of infant mortality screening
wou Id be a strong function of the allowable component
failures, hence the system failure, in the field.
Empirical data, gathered over more than a year at NEG,
indicates that early failure does occur after less than 4
hours of stress at 125°G ambient temperature. This
fact is supported by the life test of the same lot, where
the failure rate shows random distribution, as opposed
to a decreasing failure rate that then runs into the
random failure region.
NEG has adopted the initial infant mortality burn-in at
125°C as a standard production screening procedure.
As a result, the field reliability of NEG devices is an
order of magnitude higher than the goals set for NEG's
integrated circuit products.
2-8
Another significant improvement devised by NEG is
plastiC encapsulation and passivation. As a result, NEG
products show excellent reliability in both highhumidity and high-temperature environments. Following is life test data accumulated over more than a year
for large-scale integrated circuits.
High-Temperature Operating Life Test
This test is used to accelerate failure mechanisms by
operating the devices at an elevated temperature. For
large-scale integrated circuits, the failure rate is 0.242
percent per 1000 hours at 125°G. This is equivalent to
0.0071 percent per 1000 hours in an operating environment of 55°G (table 5).
Table 5.
Number of
Samples
3317
High- Temperature Operating Life Test
Number of Failures at
48 hrs 96 hrs 168 hrs 500 hrs 1K hrs
1
4
3
Total number of failures at 1K hrs
= 8
Failure rate at 1K hrs at 125°C
= 0.242% per 1K hrs
Projected failure rate at 1K hrs at 55°C = 0.007% per 1K hrs
High-Temperature and High-Humidity Life Test
This test is used to accelerate failure mechanisms by
operating the devices at high temperature and high
humidity. Leakage-related failures and device parameter drift are accelerated by this test. For these
large-scale integrated circuits, the failure rate is 0.091
percent per 1000 hours. This is equivalent to 0.0027
percent per 1000 hours in an operating environment of
55°G. The test conditions are TA = 85°G and relative
humidity (RH) = 80% (table 6).
NEe
Table 6.
QUALITY AND RELIABILITY
High- Temperature and High-Humidity Life
Test
Table 9.
Life Test Data
Total
Number of Failures at
Number of
Number of
Samples 96 hrs 168 hrs 500 hrs lK hrs Failures
Number of Failures at
Number of
Samples
48 hrs 96 hrs 168 hrs 500 hrs 1K hrs
Test Time
High-temperature
life test
3317
0
1
4
3
8
= 2
= 0.091% per 1K hrs
High-humidity
life test
2190
0
0
0
2
2
= 0.003% per 1K hrs
High-temperature
storage life test
2410
0
0
4
5
High-Temperature Storage Life Test
Pressure
cooker test
1718
4
5
This test is effective in accelerating the failure
mechanisms related to mechanical reliability problems
and process instability. For these LSI devices, the
failure rate is 0.207 percent per 1000 hours at 125°C.
This is equivalent to 0.0061 percent per 1000 hours in
an operating environment of 55°C (table 7).
Total
9635
4
6
2190
0
Total number of failures at 1K hrs
Failure rate at 1K hrs at 85°C/80% RH
Projected failure rate at 1K hrs at
55°C/60% RH
Table 7.
0
2
Number of Failures at
48 hrs 96 hrs 168 hrs 500 hrs 1K hrs
o
2410
Total number of failures at 1K hrs
Failure rate at 1K hrs at 125°C
Projected failure rate at 1K hrs
at 55°C
0
0
1
4
=5
= 0.207% per 1K hrs
= 0.006% per 1K hrs
Pressure Cooker Test
This test is effective in accelerating failure mechanisms related to metalization corrosion due to moisture.
The failure rate is 0.52 percent per 1000 hours at T A =
125°C and 2.3 atm at 100 percent humidity. This is
equivalent to 0.0013 percent per 1000 hours at 55°C
and an environment of 60 percent humidity (table 8).
Table 8.
Number of
Samples
1718
5
9
24
9
The projected failure rate in the normal operating
environment is calculated assuming that the average
activation energy is 0.7 eV.
Figure 3 shows the life distribution of NEC integrated
circuits as a form of the bathtub curve.
High- Temperature Storage Life Test
Number of
Samples
No test
performed
Pressure Cooker Test
This life test data shows improvements of approximately an order of magnitude better than NEC's goal.
The hours of operation are equivalent to the normal
operating environment. Wear-out failures, which had
been the main target for reliability improvement, have
also been significantly reduced. This result comes
mainly from process improvements and stringent manufacturing process control.
NEC's main goal has been to improve reliability with
respect to infant mortality and long-term life failures.
This can be achieved by introducing an effective
screening method for infant mortality and building
quality into the product.
Figure 3.
0.10
Plot of Life Test Results
+-------
Infant Mortality Failure Rate Goal
0,10 percent per 1000 hours maximum
+-+------
Long-Term Life Failure Rate Goal
0.02 percent per 1000 hours maximum
Number of Failures at
48 hrs 96 hrs 168 hrs 500 hrs
0
Total number of failures at 168 hrs
Failure rate at 125°C
Projected failure rate at 55°C
4
5
1K hrs
No test performed
0.05
= 9
=
0.54% per 1K hrs
= 0.001% per 1K hrs
0.01
Life Test Data Summary
Table 9 summarizes the life test results and projected
failure rates in the normal operating environment. The
failure rate shows random distribution as opposed to a
decreasing failure rate. This is a result of infant
mortality screening.
0.005
O.SK
lK
2K
3K
4K
SK
10K
20K
30K
40K
Hours_
83-003941 A
2-9
~
KI::I
NEe
QUALITY AND RELIABILITY
Thermal Stress Tests
Approaches to Total Quality Control
Temperature cycling and thermal shock test the thermal
compatibility of material and metal used to make
integrated circuits. Table 10 lists the reliability test
results of thermal stress tests.
First, the quality control function is embedded into
each process. This method enables early detection of
possible causes of failure and immediate feedback.
Table 10.
Thermal Stress Tests
Number of
Samples
Number of
Failures
Soldering heat test
TA = 260°C for 10 seconds
1891
o
Temperature cycle
TA = -65 to +150 °C, 10 cycles
1891
Thermal shock test
TA = 0 to +100°C, 15 cycles
1891
Teslltem
o
Mechanical Stress Tests
Second, the reliability and quality assurance policy is
an integral part of the entire organization. This enables
a companywide quality control activity. At NEG, everyone in the company is involved with the concept and
methodology of total quality control.
Third, there is an ongoing research and development
effort to set even higher standards of device quality and
reliability.
Fourth, extensive failure analysis is performed periodically and corrective actions are taken as preventive
measures. Process control is based on statistical data
gathered from this analysis.
In addition to the device life test, NEG performs
mechanical stress tests to detect reliability problems
related to the package, material, and device susceptibility to an extreme environment. Table 11 lists
mechanical stress test results.
The goal is to maintain the superior product quality
and reliability that has become synonymous with the
NEG name. The new standard is continuously upgraded
and the iterative process continues.
Table 11.
Building quality into a product requires early detection
of possible causes of failure at each process step.
Then, immediate feedback to remove the causes is a
must. A fixed station quality inspection is often lacking
in immediate feedback. It is, therefore, necessary to
distribute quality control functions to each process
step, including the conceptual stage. NEG has implemented a distributed quality control function at each
step of the process. Following is a breakdown of the
significant steps:
Mechanical Stress Tests
Teslltem
Number of
Samples
Number of
Failures
Mechanical shock test
at 15 kg, 3 axis
315
Vibration test
at 100 Hz to 2 kHz, 20 g
315
0
Constant acceleration
at 20 kg, 3 axis
315
0
Lead fatigue test
at 240 grams
538
0
Solderability test
at 230°C for 5 seconds
638
0
Built-In Quality and Reliability
As large-scale integration reaches even higher levels
of density, simple quality inspections cannot assure
adequate levels of product quality and reliability. In
order to ensure the reliability of state-of-the-art VLSI,
NEG has adopted another approach. Highest reliability
and superior quality of a device can only be achieved
by building these characteristics into the product at
each process step. NEG, therefore, has introduced the
notion of total quality control (TQG) into its entire
semiconductor production line. Quality control is distributed into each process step and then summed to
form a consolidated system.
2-10
Implementation of Distributed Quality Control
•
•
•
•
•
Product development phase
Wafer processing
Chip mounting and packaging
Electrical testing and thermal aging
Incoming material inspection
Product Development Phase. The product development
phase includes conception of a product, review of the
device proposal, organization and physical element
design, engineering evaluation, and finally, transfer of
the product to manufacturing. Quality and reliability
are considered at every step. More significantly, at the
design review stage and prior to product transfer, the
quality and reliability requirements have to be examined
and determined to be satisfactory. This often adds 2 to
3 months to the product development cycle. Building
in high reliability, however, cannot be sacrificed.
NEe
QUALITY AND RELIABILITY
Wafer Processing Stage Inspection. The in-process
quality inspections that occur at the wafer fabrication
stage are listed in table 12.
Figure 4.
Electrical Testing and Screening
DC Parameters
Table 12.
Wafer Processing Inspection
Process
Inspection Item
Wafer
Resistivity, dimension, and appearance,
(lot sampling inspection)
Mask
Photolithography
Alignment and etching (100% inspection)
DC Parameters,
AC Functional
Cleaning
Diffusion and oxidation
Oxide thickness, sheet resistivity (lot
sampling inspection)
IE
Metalization and passivation Thickness, Vth, C-V characteristics (lot
sampling)
Wafer sort and scribe
Dc parameters (100% inspection)
Die sort
100% visual inspection
Electrical,
Appearance, and
Dimensions
Chip Mounting and Packaging. The in-process quality
inspections done at the chip mounting and packaging
stage are listed in table 13.
Table 13.
Chip Mounting and Packaging Inspection
Process
Inspection Item
Die
Incoming material Inspection
83-003942A
Die attach
Appearance (lot sampling inspection)
Wire bonding
Bond strength, appearance (lot sampling)
Packaging
100% appearance inspection
Incoming Material Inspection. Prior to warehouse
storage, lots are subjected to an incoming inspection
according to the following sampling plan.
Fine leak*
Lot sampling
• Electrical test:
Gross leak*
100% inspection
*For ceramic package devices only.
Electrical Testing and Screening. Electrical testing and
infant mortality screening are performed at this stage.
A flowchart of the process is depicted in figure 4.
At the first electrical test, dc parameters are tested
according to the electrical specifications on 100% of
each lot. This is a prescreening prior to the infant
mortality test. At the second electrical test, ac functional tests as well as dc parameter tests are performed on
100% of the subjected lot. If the percentage of defective
units exceeds the limit, the lot is subjected to an
additional burn-in. During this time, the defective units
are undergoing a failure analysis, the results of which
are then fed back into the process for corrective action.
Dc parameters
Functional test
• Appearance
LTPD
LTPD
3%
3%
LTPD
3%
Reliability Assurance Test
Samples are continually taken from the warehouse and
subjected to monthly reliability tests as discussed
previously. They are taken from similar process groups
so that it can be assumed that any device is representative of the reliability of the group.
2-11
NEe
QUALITY AND RELIABILITY
In-Process Screening
Summary and Conclusion
Perhaps the most significant preventive measure that
NEC has implemented is the introduction of 100%
burn-in as an integral part of the standard production
process. Most of the potential infant failures are effectively screened from every lot, thereby improving
reliability. Assuming average activation energy of 0.7
eV, burn-in at T A = 125 °G for 4 hours is equivalent to a
week's operation in a normal operating environment.
This appears to be ample time for accelerating the
time-to-failure mechanisms for early failures.
As has been discussed, building quality and reliability
into products is the most efficient way to ensure
product reliability. NEC's approach of distributing
quality control functions to process steps, then forming
a consolidated quality control system, has produced
superior quality and excellent reliability.
Process automation, as previously mentioned, has also
contributed a great deal toward improving reliability.
Since its introduction, assembly related failure mechanisms have been substantially reduced. And, in
combination with in-process screening and materials
improvement, it has helped establish quality and
reliability above NEG's initial goals.
Prescreening, introduced as an integral part of largescale integrated circuit protection, has been a major
factor in improving reliability. The most recent year's
production clearly demonstrates continuation of NEG's
high reliability and the effectiveness of this method.
Reliability assurance tests (RATs), performed monthly,
have ensured high outgoing quality levels. The combination of building quality into products, effective
prescreening of potential failures, and the reliability
assurance test has established a singularly high standard of quality and reliability for NEG's large-scale
integrated circuits.
With a companywide quality control program, NEG is
committed to building superior quality and highest
reliability into all its products. Through continuous
research and development activities, extensive failure
analysis, and process improvements, a higher standard
of quality and reliability will continuously be set and
maintained.
2-12
NEe
4-BIT, SINGLE-CHIP MICROCOMPUTERS
3-1
4-BIT, SINGLE-CHIP MICROCOMPUTE~S
t-IEC
Section 3 - 4-Bit, Single-Chip Microcomputers
pPD7500 Series
pPD7500H/H-E
pPD7501
pPD7502/03
pPD7506
pPD7507/08
pPD7507H/08H
pPD7507S
pPD7508A
pPD7514
pPD7516H
pPD7519/19H
pPD7527 A/28A
pPD7533
pPD7537 A/38A
pPD7554/64
pPD7556/66
pPD75104/106/108
pPD75P108
CMOS Microcomputers .................................. 3-3
CMOS Microcomputers for pPD7500-Series Evaluation .... 3-31
CMOS Microcomputer with LCD Controller/Driver ........ 3-45
CMOS Microcomputers with LCD Controller/Driver ....... 3-59
CMOS Microcomputer .................................. 3-75
CMOS Microcomputers ................................. 3-89
CMOS Microcomputers ...... ; ......................... 3-109
CMOS Microcomputer ................................. 3-123
CMOS Microcomputer with FIP® Driver ................. 3-141
CMOS Microcomputer with LCD Controller/Driver ....... 3-155
CMOS Microcomputer with FIP® Controller/Driver ....... 3-175
CMOS Microcomputers with Flp® Controller/Driver ...... 3-199
CMOS Microcomputers with FI p® Driver ................ 3-229
CMOS Microcomputer with A/D Converter .............. 3-243
CMOS Microcomputers with FI p® Driver ................ 3-263
CMOS Microcomputers with Serial I/O .................. 3-277
CMOS Microcomputers with Comparator ................ 3-295
CMOS Microcomputers ................................ 3-313
CMOS Microcomputer with On-Chip EPROM ............ 3-325
FIP is the registered trademark for NEe's fluorescent indicator panel (vacuum fluorescent display).
3-2
NEe
NEe Electronics Inc.
Description
The J.lPD7500 series of 4-bit, single-chip CMOS microcomputers is a broad product line of devices designed
for a variety of applications; for example, electronic
games, home electronic products such as the VCR,
and electronic automotive devices. To this end, more
than 25 products based on the J.lPD7500 evaluation
chip have been designed with various combinations of
memory size, number of I/O ports, output drive capability, type of display driver/ controller (LCD or FIP®),
oscillators, package type (DIP, shrink DIP for ease of
handling, flat for high-density installations, QUIP), and
more. Because the J.lPD7500 series products have
hardware and software in common, systems are easily
upgraded.
The J.lPD7500 series uses a low-power CMOS design.
As an example, the current consumption of the
J.lPD7508C operating at 5 V is typically 300J.lA (at 10J.ls,
200 kHz). In standby mode at3 V, current consumption
is reduced to 0.3 J.lA (typ). This feature is most suitable
for systems requiring battery backup or for batterypowered devices that must operate for long periods.
pPD7500 SERIES
4-BIT, SINGLE-CHIP
CMOS MICROCOMPUTERS
The many kinds of peripheral hardware (such as
display controllers/drivers) that are built into the
members of the series can significantly reduce the cost
of a system. One common hardware feature is an 8-bit
timer, which easily provides a clock function. With the
exception of the J.lPD7506/7556/7566, all products of
the series incorporate an 8-bit serial 110, so that
developing multiprocessorsystemsorconnecting peripheral devices is easier. The J.lPD7533 offers a 4channel, 8-bit A/D converter.
Piggyback products, such as the J.lPD75CG08, are
available and can be used as a final check of functions
during system development, preproduction, and small
volume production.
The same support tools can be used for the entire
series, thus helping to reduce system development
cost.
Table 2 lists the package types applicable to each chip
in the J.lPD7500 series.
FIP is the registered trademark for NEG's fluorescent indicator panel
(vacuum fluorescent display).
The wide operating voltage range of the series allows
systems to be configured with normal operation at
5 V ±10% and battery backup operation at 3 V. In
particular, the J.lPD7507S can run at 2.2 V, and systems
using this device need only a single lithium battery,
thus reducing the overall system cost
Although the normal operating temperature range is
-10 to +70°C, products in the J.lPD7500 series can
operate from -40 to +85°C and -40 to +110°C in
accordance with the user's request. This is useful in
automotive and outdoor applications.
Table 1 lists the J.lPD7500 series products and features,
and figure 1 shows the different development directions
of the series. Within each of these directions, the
memory sizes have been serialized. For example, in the
product group with built-in LCD controllers, the
J.lPD7501 has a 1K-byteROM, the J.lPD7502 has a
2K-byte ROM, and the J.lPD7503 has a 4K-byte ROM.
(Note also that the J.lPD7502 and J.lPD7503 are pin
compatible; software developed on the J.lPD7502 can
be used without modification on the J.lPD7503. Except
LAMT instruction for J.lPD7502 only and LAMTL instruction for J.lPD7503 only.)
3-3
E
NEe
fJ;PD7500
Table 1.
pPD 7500 Series Product List
Product (PPD)
Features
Clock Osc
ROM Ix8)
RAM Ix4)
liD
Power Supply
7500H
EVACHIP, high speed (2.86/Js)
RC
8K (External)
256
46
5 V ±10%
7500H-E
EVACHIP
RC
8K (External)
256
46
5 V ±10%
7501
LCD controller/driver, 24-segment
RC
1K
96
24
2.5 to 6.0 V
7502
LCD controller/driver, 24-segment
RC
2K
128
23
2.5 to 6.0 V
7503
LCD controller/driver, 24-segment
RC
4K
224
23
2.5 to 6.0 V
7514
LCD controller/driver, 32-segment
RC
4K
256
31
2.7 to 6.0 V
7507S
General purpose, low voltage
RC
2K
128
20
2.2 to 6.0 V
7507
General purpose
RC
2K
128
32
2.5 to 6.0 V
7508
General purpose
RC
4K
224
32
2.5 to 6.0 V
7507H
General purpose, high speed (2.86/Js)
Xtal/Cer
2K
128
32
2.7 to 6.0 V
7508H
General purpose, high speed (2.86/Js)
Xtal/Cer
4K
224
32
2.7 to 6.0 V
7506
General purpose
R
1K
64
22
2.5 to 6.0 V
7554
LED direct drive, mask option ports, serial I/O
R
1K
64
16
2.5 to 6.0 V
7564
LED direct drive, mask option ports, serial I/O
Ceramic
1K
64
15
2.5 to 6.0 V
7556
LED direct drive, mask option ports,
4-channel comparator
R
1K
64
20
2.5 to 6.0 V
7566
LED direct drive, mask option ports,
4-channel comparator
Ceramic
1K
64
19
2.5 to 6.0 V
7527A
P-ch, high-voltage output ports for FIP driver;
high speed (3.3 p.s)
RC
2K
128
35
2.7 to 6.0 V
7537A
P-ch, high-voltage output ports for FIP driver;
high speed (3.3 p.s)
Ceramic
2K
128
35
2.7 to 6.0 V
7528A
P-ch, high-voltage output ports for FIP driver;
high speed (3.3 p.s)
RC
4K
160
35
2.7 to 6.0 V
7538A
P-ch, high-voltage output ports for FIP driver;
high speed (3.3 p.s)
Ceramic
4K
160
35
2.7 to 6.0 V
7508A
P-ch, high-voltage output ports for FIP driver
RC
4K
208
32
2.7 to 5.5 V
7519
FIP controller/driver
Xtal
4K
256
53
2.5 to 6.0 V
7519H
FIP controller/driver; high speed (2.44 p.s)
Xtal
4K
256
53
2.5 to 6.0 V
7516H
FIP controller/driver; high speed (2.44 p.s)
Xtal
6K
256
53
2.5 to 6.0 V
7533
LED driver; 4-channel A/D converter
Ceramic
4K
160
30
3.0 to 6.0 V
75CG08
Piggyback; for 7507/08
RC
4K
224
32
5 V ±10%
75CG08H
Piggyback; for 7507H/08H
Xtal/Cer
4K
224
32
5 V ±10%
75CG19
Piggyback; for 7519
Xtal
4K
256
53
5 V ±10%
75CG19H
Piggyback; for 7519H
Xtal
4K
256
53
5 V ±10%
75CG16H
Piggyback; for 7516H
Xtal
6K
256
53
5 V ±10%
75CG28
Piggyback; for 7527A/28A
RC
4K
160
35
5 V ±10%
75CG38
Piggyback; for 7537A138A
Ceramic
4K
160
35
5 V ±10%
75CG33
Piggyback; for 7533
Ceramic
4K
160
30
5V±10%
3-4
NEe
Figure 1.
fJPD7500
pPD7500 Series Product Classification
:> I~'~""~O I
L -_ _ _ _ _ _ _ _ _ _
0~CD
U
Minimicrocomputer
[Piggyback]
General
purpose
>
I
7500H
L------,)
AID
D:~~:~Oltage
533
D
Table 2.
"---->
Applicability of Packages
Product IJ,tPDI
Package
Product IJ,tPDI
Package
7500H, 7500H-E
64 QUIP
7527 A, 7528A
42 DIP or SDiP
7501
64 miniflat
75CG28
42 ceramic piggyback DIP
7502,7503
64 miniflat
7533
42 DIP, SDlP, or 44 miniflat
42 ceramic piggyback DIP
7506
28 DIP or SDIP; 52 miniflat
75CG33
7507,7508
40 DIP or SDlP; 52 miniflat
7537 A, 7538A
42 DIP or SDiP
75CG08
40 ceramic piggyback DIP
75CG38
42 ceramic piggyback DIP
7507H,7508H
40 DIP or SDIP; 44 miniflat
7554,7564
20 SDlP or SO package
75CG08H
40 ceramic piggyback DIP
7556,7566
24 SDiP or SO package
7507S
28 DIP or SDiP
Note:
7508A
40 DIP
7514
80 miniflat
(1) For ordering information, including package codes, refer to the
applicable data sheet.
7516H
64 miniflat, QUIP, or SDiP
75CG16H
64 ceramic piggyback QUIP
7519,7519H
64 miniflat, QUIP, or SDIP
75CG19, 75CG19H
64 ceramic piggyback QUIP
(2) Packages are plastic unless otherwise specified.
3-5
NEe
J..lPD7500
Applications
7500 series products with a built-in LCD controller:
• Electronic game
• Automotive device (dashboard display)
• Phone
• VCR (timer)
• Camera
• Calculator
• Electronic musical instrument
• Measuring equipment
• Medical device (blood pressure gauge)
• Water, gas, or electric meter
• Pager
• PPC
• Data terminal
7500 series products with built-in high-voltage outputs:
•
•
•
•
•
•
VCR
ECR
Microwave oven
Electronic game
Scanner
Trip computer
7500 series products with a built-in LED controller/driver:
• Electronic game
• Deck controller
• Refrigerator
• Cooking appliance
• Washing machine
7500 series general-purpose products:
• VCR
• Phone
• Automobile
• ECR
• Record player
• Transceiver
• PPC
• Cassette
Block Diagram
Common Processor Portion
I
Peripheral
PC
• Timer/Counter
I
• Serial Interface
SP
~
I
I
• Interrupt Circuit
A
• Standby Circuit
ALU
• System Clock Circuit
• General I/O Port
• Display Control Driver
ROM
[J
I
H
I
D
I I
I I
L
E
I
I
49-001252B
3-6
ttfEC
J,1PD7500
Functional Description
Program Counter [PC]
A jlPD7500 series microcomputer consists of the following:
• Program counter (PC)
• Accumulator (A)
• Program status word (PSW)
• Arithmetic logic unit (ALU)
• General-purpose registers (H, L, D, E)
• Program memory (ROM)
• Data memory (RAM)
The program counter (figure 2) is a binary counter that
generates a 12-bit address. The bit length of the PC will
vary depending on the ROM size for the particular
device. ThejlPD7516H andjlPD7500H/H-E, which contain more than 4K-bytes of memory, access upper
memory by setting bit 1 of the program status word
(BNK flag) to 1.
The peripheral hardware includes the following:
• Timer/counter
• Serial interface
• Interrupt circuit
• Standby circuit
• System clock oscillation circuit
• General-purpose I/O
• Display controller/driver
Figure 2.
Program Counter Structure
When an instruction executes, the PC increments by
the number of bytes in the instruction.
When a jump instruction (JMP, JCP, JAM) executes,
either immediate data or the contents of the accumulator and data memory, which show a jump
destination, are loaded into some or all bits of the PC.
While a call instruction is executing (CALL, CAL T) or
at an interrupt occurrence, the contents of the PC (the
return address already incremented to designate the
next instruction) are stored in stack memory. A proper
address is then loaded into the PC.
While a return instruction is executing (RT, RTS,
RTPSW), the contents of stack memory are loaded into
the PC.
The RESET instruction clears the PC to O.
3-7
3
~EC
JiPD7500
Figure 3.
Stack Pointer [SP]
The stack area for the pPD7500 series resides in data
memory. The stack depth can be as large as the
maximum size of RAM, since the stack pointer is user
programmable.
Data Movement at Execution of TAMSP
and TSPAM
The stack pointer is an 8-bit register (SPy-SPa) that
stores the stack's top address for the area in data
memory used as an LIFO stack. The SP decrements
when a call (CALL, CAL T) or push (PSHDE, PSHHL)
instruction executes and at an interrupt generation. It
increments when a return (RT, RTS, RTPSW) or pop
(POPDE, POPHL) instruction executes.
To determine the stack area, the SP must be initialized
by the TAMSP instruction. However, when TAMSP
executes, 0 (zero) is unconditionally loaded into SPa.
Because the SP decrements before a stack instruction
executes, the top of the stack will always begin at an
odd memory location. Thus the initial value of the SP
should be set to the top of the stack (odd) plus one (set
to an even value). To.setthe most significant address of
the stack area to FFH, the initial value of the SP should
be OOH.
Although TSPAM may read the SP at any time, it
cannot read the contents of SPa; 0 is unconditionally
stored in bit 0 of data memory. See figure 2 and table 3.
Table 3.
Process
Order
Stack Memory Push/Pop Operation
RT, RTS
RTPSW
PSHDE,
PSHHL
CALL, CALT
Interrupt
2
(SP-1) (SP-2) -
PCM
PCl
PCH - (SP)
PCl - (SP+2)
PCH - (SP)
PSW - (SP+ 1)
(SP-1) (SP -2) -
3
(SP-3) -
PSW
PCM -
PCl -
(SP+2)
SP -
4
(SP -4) -
PCH
SP- SP+4
PCM -
(SP+3)
5
SP -
Note:
(1) PCH = PC1rPCa
PCM = PCrPC4
PCl = PC3-PCa
3-8
SP-4
(SP+3)
SP- SP+4
D/H
Ell
SP-2
POPDE,
POPHL
Ell - (SP)
D/H -
SP -
(SP+ 1)
SP+2
NEe
f.l P D7500
Program Memory [ROM]
General-Purpose Registers
Program memory is a mask-programmable ROM of
6144 words x 8 bits (maximum). It stores programs and
table data, and is addressed by the PC. (See figure 4.)
ROM address locations are from OOOH to 17FFH.
The four 4-bit general-purpose registers D, E, H, and L
either operate in units of 4 bits, or can form the 8-bit
pair registers DE, DL, and HL (D or H is the upper-order
4 bits, and E or L is the lower-order 4 bits) to be used as
data pointers.
Specific fixed address locations are allocated to
RESET and interrupt start addresses and the table
areas of the LHL T and CAL T instructions. Consideration of these locations in program memory should be
taken in preparing a program.
Figure 4.
Program Memory Map
When pair register HL operates as a data pointer, it can
perform automatic increment and decrement for the L
register only. (See figure 5.) The L register is also used
to specify I/O ports and mode registers when the I/O
instruction (OPL, IPL) is executed.
The pPD7501 /06/27/28/33/37/38/54/64/56/66 do not
contain DE registers.
Figure 5.
General-Purpose Register Configurations
o
~3
r---:-------'j=---:;:::f
________~O
r----
Subroutine
Entry
Addresses
-----:,~
49·001229A
J9·001228A
3-9
NEe
J.lPD7500
Data Memory [RAM]
Accumulator [A]
Data memory is a static RAM of 256 words x 4 bits
(maximum). It is used to store processing data and
display data. It also operates with the accumulator to
process data in 8-bit units.
The accumulator is a 4-bit register that performs
various arithmetic/logical operations. Operating with
data memory addressed by pair register HL, data
processing may be done in 8-bit units (higher-order
bits in the accumulator and lower-order bits in data
memory). See figure 8.
There are three types of data memory addressing:
• Direct, performed by the second byte of the
instruction
Figure 8. Accumulator Configuration
• Register indirect, performed indirectly by the contents of the pair register designated by an instruction
• Stack indirect, performed by the contents of the SP
Locations 00 to 3FH are used for display memory
devicespPD7516H/19H, so these locations cannot be
used for stack area. Locations 00 to 17H (1 FH for the
pPD7514) are used for display memory devices
pPD7501/02/03/14, so these locations cannot be used
for stack area. See figure 6.
Valid stack area is used during execution of the
instructions CALL, CALT, RT, RTS, RTPSW, PSHDE,
PSHHL, POPDE, and POPHL. At the execution of a call
instruction or an interrupt occurrence, the contents of
the PC and PSW are stored in the stack area. At the
execution of a push instruction, the contents of DE or
HL are stored in the stack. See figure 7.
Arithmetic Logic Unit [ALU]
The ALU is a 4-bit arithmetic logic circuit that performs
such processes as binary addition, arithmetic/logical
operation, comparison, and rotation.
Program Status Word [PSW]
The 4-bit PSW consists of two skip flags (SK1, SKO)
and a carry flag (C), as shown in figure 9.
Figure 9.
Structure of Program Status Word
3
SKl
Figure 6.
Data Memory Map
Data memory
(0) DOH
32 x 4
(31) lFH
,.PD7519116 (32) 20H
Display Area
PPGArea
28 x 4
3BH
(63) 3FH 3CH
(64) 40H
4x4
256 x4
(256)
Figure 7.
192x 4
FFH
49-001230A
Stack Contents After Call, Interrupt, or
Push
SP-4
Call Instruction,
Interrupt
Push Instruction
Stack
Stack
PCl1-PCa
SP-3
PSW
SP-2
PC3-PCO
SP-2
E orL
SP-l
PCrPC4
SP-l
DorH
49-001231A
3-10
0
C
The contents of the PSW are automatically stored in
the stack area at an execution of a call instruction
(CALL, CALT) or at an interrupt occurrence, and are
restored by an RTPSW instruction. The BNK flag is
used in the pPD7500H/H-E and 7516H to access high
memory.
At RESET, SK1 and SKO are cleared to 0, and C is
undefined.
Stack Area
"r
1
SKO BNK
49-001256A
,.PD751f Display
Data Area
Direct/Register
Indirect Address
Area
2
I I I I Ipsw
NEe
Skip Flags [SK1, SKO]. The skip flag is used to hold the
following skip states:
• String effect of an LAI instruction
• String effect of an LHLI or LHLT instruction
• Skip condition accomplished by instructions other
than string effect
The skip flag is automatically set and reset when an
instruction is executed.
Carry Flag [C]. This flag can be generated only by the
addition instruction (ACSC). If a carry is generated
from bit 3 of the ALU, the carry flag is set to 1. If a carry
is not generated, the carry flag is reset to O.
The carry flag is set to 1 by the SC instruction and reset
to 0 by the RC instruction. Its contents are tested by
the SKC instruction. The carry bit is rotated into the
high bit of the accumulator by the rotation instruction
(RAR).
J,1PD7500
System Clock Generator
The system clock (CL) is generated by one of the five
types of oscillators listed in table 4. The CPU clock (~)
is derived from CL by frequency division.
Table 4. IlPD7500 Series System Clock (CL) and CPU
C/ock(~)
~/CL
Oscillator
Type
Stop Mode
Released by
7500H,7500H-E 1/2
7501
7502
7503
7514
7507,7507S
7508,7508A
7527A
7528A
RC
Interrupt or RESET
7506
7554
7564
7556
7566
1/2
R
Interrupt or RESET
7507H
7508H
1/12
Crystal/ceramic
1.0 to 4.2 MHz
RESET (Note 1)
7519
7519H
7516H
1/32 or 1/64
1/16 or 1/64
1/16 or 1/64
Crystal
RESET
4.19 to 6.55 MHz
(75194.19 MHz max)
7537A
7538A
1/2
Ceramic
Product (PPD)
Frequency
Ratio
RESET
7533
Note:
(1) RESET pulse width provides time for oscillation stabilization.
3-11
E
ttiEC
JlPD7500
RC Oscillator
The system clock generator (figure 10) consists of an
RC oscillator and a half-frequency divider. The RC
oscillator is controlled by an external resistor (R) and
capacitor (C) connected to CL 1 and CL2.
Notshown in figure 10, the RC oscillator output (CL) is
sent to a clock control circuit, and then frequency
divided to become a count pulse (CP) for the timer/
event counter.
An external clock can be input to the CL 1 pin without
using an RC circuit. Pin CL2 should be left open. In this
case, the RC oscillator merely operates as an inverting
buffer.
If an external clock is used, the CL 1 input clock
becomes CL via an inverting buffer, so the supply of CL
does not stop even in stop mode. Thus, both stop mode
and halt mode stop only the half-frequency divider. In
both modes, only the output of cp is stopped.
The frequency of CL is the RC oscillation frequency of
the CL 1 input clock frequency. The RC oscillator
output is frequency divided by 2 to become the CPU
clock (CP), which is sent to the CPU and the serial
interface.
Using the standby circuit, the RC oscillator and the
half-frequency divider are stopped in the stop mode,
thereby stopping the output of CL and cp.ln halt mode,
only the half-frequency divider is stopped, so that cp
stops but CL continues to be supplied.
Figure 10.
System Clock Generator; RC Oscillator
StopF/F
~"I---_STOP'
~------~Q
S~--------------~
HaltF/F
R
Disable
Clock
frl
Q
S
P
'
"
I--+---- HALT"
RESET (High)
R
cu
RC
Oscillator
CL2
STANDBY RELEASE
11---------+--,-1----- RESET ( 1.. )
~---_(toCPU)
~----------------. . . CL(SystemClock)
Note: • Indicates instruction execution.
49·0012338
3-12
NEe
J.lPD7500
R Oscillator
In this circuit, the resistor is external and the capacitor
is internal. See figure 11.
Figure 11.
System Clock Generator; R Oscillator
Stop F/F
r------~Q
,--,..----1,.-- STOp·
S~----------------~
HaltF/F
R
Disable
Clock
Q
S
1--+--- HALT"
RESET (High)
R
CL1
E
RC
Oscillator
CL2
STANDBY RELEASE
........~----- RESET (
L )
t--------.. c!> (to CPU)
L -____________________________
CL (System Clock)
Note: • Indicates instruction execution.
49·0012346
3-13
NEe
J..l.PD7500
Crystal/Ceramic Oscillator
The standby mode control circuit is mainly composed
of a stop flip-flop and a halt flip-flop. See figures 12 and
13.
This clock generator provides stable high-speed operation. The circuit (figure 12) consists mainly of a
crystal oscillator circuit, several frequency dividers,
and a control circuit for standby (halt/stop) modes.
The STOP instruction sets the stop flip-flop to the stop
mode, in which crystal oscillation and all clock supplies
are stopped. A high input to RESET resets the stop
flip-flop, and crystal oscillation starts again. When
RESET goes low, the supply for each clock restarts.
The crystal oscillator operates at the fundamental
crystal frequency, typically 4.19 MHz. Or, a ceramic
resonator (typically 4.0 MHz) may be connected
between the CL 1 and CL2 pins. Or, an external clock
may be input at CL 1, in which case the crystal oscillator
operates as an inverting buffer.
Figure 13.
The frequency divider generates several ki nds of clocks
by dividing the crystal/ceramic oscillation frequency
(fee) orthe external clock frequency (fe), where fee or
fe = 4.19 MHz, as follows:
Stop Mode Timing
r
HALT
(----STOP
Mode----~Mod:.;;,i.je
Operating
Mode
r o a t a ~:~ntion
-~-il,~
VOO
t
VOOOR
STOP Instruction
Execution
• System clock (CL): fee/6 or fe/6 (698 kHz)
RESET
• CPU clock (cp) and output clock (CPOUT): fee/12 or
fc/12 (349 kHz):
49·0012368
• Timer/event counter clock: fee/8 or fe/8 (524 kHz)
System clock CL is supplied to the timer/event counter,
the clock synchronizing the gate of the INT1 interrupt
input, etc.
Figure 12.
System Clock Generator; Crystal/Ceramic Oscillator
OUT
(349kHz)
,...
-
V2
CLR
~
To Timer/Event Counter
(524kHz)
V.
CLR
CL
(698kHz)
0-----Crystal!
Ceramic
Oscillator
~
fc
V2
CLR
0--
i -.......
V3
~~
V2
(to CPU)
I-- t--- (349kHz)
CLR
CLR
L-.
Disable
Clock
HALTF/F
'--Q
(~
-
---
RK (
HALT
RELEASE
RESET(""l)
s~r-
HALT'
S
STOP'
R
RESET
-J
STOPF/F
Q
Note: • Indicates instruction execution.
49·001235E
3-14
NEe
J.l,PD7500
The HALT instruction sets the halt flip-flop to halt
mode. In this mode, input from the half-frequency
divider that generates the CPU clock is inhibited and
the CPU clock is stopped. The halt flip-flop is reset
either by the RELEASE signal, which becomes active
when the interrupt request flag is set, or at the falling
edge of the RESET signal. The supply to the CPU clock
restarts.
The frequency divider divides the output of the crystal
oscillator (fxx for crystal oscillation, and fx for the
external clock) to the following values:
• 1/2 for pulse generator clock ¢PPG
• 1/8 for system clock ClH (pPD7519H/16H)
• 1/16 for system clock ClH (pPD7519)
• 1/32 for system clock Cll and FI P controller clock
¢FIP
Crystal Oscillator
This clock generator (figure 14), applicable to 7516H,
7519, and 7519H, consists of a crystal oscillator, a
frequency divider, and a standby (halt/stop) mode
control circuit. The crystal (for example, 6.55 MHz is
4.19 MHz) is connected to pinsX1, X2. (ThepPD7519 is
4.19 MHz only).
• 1/128 for the timer/event counter clock.
It is also possible to operate with an external clock
input at X1. In this case, the crystal oscillator acts
merely as an inverting buffer.
Figure 14.
System Clock Generator; Crystal Oscillator
r - - - - - - - - - - - - - . - - R E SET
I - - - - -__+-- STOP [Note 1]
f~" ,
STOPF/F
Frequency Divider
1/8 [Note 21
11128
L-----J
4.19 MHz
'-
EM2 -.-1----.
_ - - - HALT [Note 1]
,,-""'J-----HALT RELEASE
IRESET(""L)
1 - - - - - - - - - ; . --_________-. CL(System Clock)
L -_ _
' - - - - - - - - - - , - - - - - - . to Timer/Event Counter
' - - - - - - - - - - - - - - - _ PPG(toPulseGenerator)
[1] Indicates instruction execution.
[2] IlPD7519 uses 1/16.IlPD7519H/16H uses 1/8.
49-0012576
3-15
NEe
J,tPD7500
The 1/8 and 1/32 frequency-divided outputs are available as system clock sources. If expansion mode
register bit 2 (EM2) is 1,1/8 is selected; if it is 0,1/32 is
selected. (Note: For pPD7519, the divisor is 1/16
instead of 1/8.) In systems where high-speed processing is not required, or in part of a program that does
not require high-speed processing, power consumption
can be held to a minimum with the 1/32 frequencydivided low-speed clock. It is necessary to use the
low-speed clock when using a supply voltage that is
too low to allow operation with a high-speed clock.
System clock selection via EM2 does not apply to FIP
(FIP controller clock) or PPG (pulse generator clock).
The FIP clock is always 1/32 times the input frequency;
the PPG clock is always half the input frequency.
The system clock is half-frequency divided to be a CPU
clock, . Also, the system clock becomes an input of
the clock control circuit, which generates a count
pulse (CP) of the timer/event counter.
The standby mode control circuit consists mainly of
the stop and halt flip-flops. The STOP instruction sets
the stop flip-flop, which stops crystal oscillation and
clears the frequency divider circuit. All output from the
frequency divider circuit stops; the system is in stop
mode. A RESET input clears the stop flip-flop and
starts crystal oscillation and the frequency dividing
operation.
The HALT instruction sets the halt flip-flop. This
inhibits the input of the half-frequency divider from
generating a CPU clock , thereby causing the CPU
clock to be halted (halt mode). The halt flip-flop is also
set when the STOP instruction executes and when
RESET is input, so that the flip-flop performs the same
operation as that in halt mode. The flip-flop is reset at
the falling edge of either the RELEASE signal (which
becomes active when anyone interrupt flag is set) or
the internal reset (IRESET) signal (which is released
after a certain waiting time following the release of the
RESET input), thereby starting the supply of . See
figure 15.
Figure 15.
Release of Stop Mode
Operating
Mode
Operating
Mode
-4..-I-----Stop Mode---_-I-Data Retention
VDDR
Wait (- 62.5 msl
4.19 MHz)
RESET
49-001237A
3-16
Ceramic Oscillator
This circuitry (figure 16) consists of a ceramic oscillator, half-frequency divider, control circuit for standby
(halt) mode, etc. The oscillator frequency is set by a
ceramic resonator connected to pins CL 1 and CL2. Or,
an external clock may be input at CL 1. In this case, the
oscillator operates as an inverting buffer. Output from
the oscillator is used as the system clock (CL), which is
divided into a CPU clock (1/2 CL).
The standby mode control circuit consists mainly of
the halt flip-flop. When this flip-flop is set, input of the
half-frequency divider is inhibited from generating the
CPU clock , thereby causing the CPU clock to be
halted (halt mode). This flip-flop is reset either by the
RELEASE signal, which becomes active when one
interrupt request flag is set, or by the falling edge of the
RESET input. The supply of the clock then begins.
The halt flip-flop is also set when the RESET input is
active. At power-on reset, RESET goes high and then
the ceramic oscillator is driven. After a short time, the
oscillation output becomes stable. So that an unstable
clock does not cause the CPU to misoperate, the halt
flip-flop inhibits the CPU clock as long as RESET is
high level. Thus, the high-level pulse width for the
RESET input should be wide enough to cover the
required time for oscillator stabilization.
Count Clock Generator Circuit
This crystal oscillator (figure 17) is fed either by the
crystal connected to pins X1 and X2, or by an external
clock connected to X1 (in which case it operates as an
inverting buffer). The output X is sent to the clock
control circuit, either directly or after being frequency
divided, in order to become a count pulse (CP) for the
timer/event counter. The frequency of X is equivalent
to the crystal oscillation frequency or the X1 external
clock frequency. This circuit is not affected by standby
(halt/stop) mode.
The count clock oscillator generates frequencies
between 25 and 50 kHz. Figures 18 and 19 illustrate the
frequency error (ppm) vs. temperature and capacitance.
NEe
Figure 16.
JlPD7500
System Clock Generator; Ceramic Oscillator
StopF/F
, . . . , . - _ - - STOp·
S~---------------~
~_r_,
__
r---------~Q
HaltF/F
R
Disable
Clock
I----+--HALT'
Q
RESET (High)
r~CL1
R
Ceramic
Oscillator
~~CL2
STANDBY RELEASE
...........k----RESET (
L )
L-+-------------------------RESET(Jr)
v,
1-------__
L--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
(to CPU)
CL (System Clock)
Note: • Indicates instruction execution.
49·0012388
Figure 17.
Figure 18.
Count Clock Generator
,------
Crystal Oscillation
1~:C
~ ~r
Temperature Dependence of Count Clock
Frequency
I
I
R
X1
I
I
Crystal
Oscillator
r- ~~~~~;~o~~n~rol
X2
330kH
-20~------~~----_T--------r_~-----r------~
Circuit)
-40~--~--~-------L--------r_----~-r------~
I
X2
L ______
32.768
kHz
-60
1-External
Clock
I
I
I
IL
20 P F
-80
X1
Crystal
Oscillator
I
I
Open
----
X2
(Inverted
Buffer)
Count Clock
r- (toCircuit)
Clock Control
X
330 kO
o
External Clock
30 pF
~
f
-20
20
40
60
80
TA [CC]
Capacitance (C1) Dependence of Count
Clock Frequency
Figure 19.
_______
49·001239A
-2
-4
C1
f
*
C2 = 30 pF
"
---I____________________~ §
~---------~---------~~
10
20
Capacitance, C1 [pF]
3-17
NEe
J.lPD7500
1/0 Ports
Port
OOH/OOHE
06
POo
A
B
F
P02
E
P03
B
E
P60·P63
Port
00H/OOHE/07/07H/08/08H/14
E
P70·P73
OOH/OOHE
06
07/078/07H/08/08HI
01/14/19/19H/16H
INTO
B
B
INT1
B
B
INT2
B
F
RESET
E
E
Port
B
B
02103
F
A
OOH/OOHE/01 102/03/06/07/07HI
08/08H/14/1 911 9H/16H
Port
Port
Table 5. pPD7500 Series 110 Buffer Configurations
P01
pPD7500 Series 110 Buffer Configurations
(cont)
Table 5.
Input and output buffers (figure 20) are classified as
types A through I. Table 5 shows the applicability of
each type to the 7500 series. For example, on the
pPD7506, port POo is a type B input buffer and P03 is a
type A input buffer; P01 and P02 are not used. (Part
numbers in table 5 are abbreviated; thus, pPD7506
becomes "06".)
B
01/02/03/07/078/07HI
08/08H/14/1 911 9H/16H
B
B
B
B
07H/08
19/19HI16H
EVENT
B
B
If>OUT
C
Port
01
02/03
00H/OOHE/06/07/07H/081
08H/14/1 9/1 9H/16H
P10
B
B
E
PPO
o
P11
A
A
E
Port
01/02103/14
P12
A
A
E
COMO·COM3
P13
A
A
E
Port
P20·P23
Port
P3O·P3
Port
P40·P43
Port
P5O·P3
3-18
00H/OOHE/06/07/078/07HI
08/08H/14/1 911 9H/16H
0
OOH/OOHE/OI 102/03/07/0781
07H/08/08HI1411 9/1 9H/16H
Port
19/19H/16H
G
H
Port
14
Port
19/19H/16H
H
SO·S7
0
OOH/OOHE/OI 102/03/06/071
078/07H/08/08H/14/1 9/1 9HI16H
TO·T7
Port
E
BUSS, BUSg
OOH/OOHE/OI 102/03/06/07/0781
08/08HI1411 911 9HI16H
BUSO·BUS7
E
OOH/OOHE
C
E
E
DOUT
C
ALE
C
PSEN
C
LCDCL
C
CSOUT
C
STB
C
TEST
A
NEe
Figure 20.
JlPD7500
Interface at Input/Output Ports
Type F
Type A
Voo
Data
Type 0
InlOut
Output
Disable
~"P"
Type G
Vss
P·ch
Type B
~'"P"
..1..
T
Type C
P·ch
N·ch
Output
Voo
~---o
Output
T
N·ch
Vss
Type 0
Voo
P·ch
Data~
Output
outPut~
Type I
Disable
------~----------~--oVDD
Vss
Type E
Display Output
Data
Type 0
InlOut
Output
Disable
~------------- - - - - - - - - - I
~~---<~-+--~
P02/S0 0 - - - - - + - - - - - - - 1 - - 1 - - < 1 - - - - - - - - - - - - - - 4 - - - - - - - - - - - - l
LJ:>--+--
TOUT
POo 0 - - - - - - - - - - - 1
• Command Execution
tf> System Clock
R~-~--_
INTS
RS F/F
"""'--
,....--....., Q
S 1 - - - - - - 'SIO
83-0034686
3-36
NEe
Figure 5.
pPD7500H/H-E
Interrupt Control
INT1o------------~
INTT--------------I
INTS------I--f
INTOID-----4---I-,
I
INT2D-----+------~
S I O · - - -.....
'Command Signal
~
Standby
Release
83-0034086
3-37
NEe
pPD7500H/H-E
Figure 6.
Clock Control
Inlernal Bus
~----------------,
r-------------------------------~----~
CL-----I
LCDCL
~~=====r~~-----CP
[To the Timer/Event Counter]
INT2
-_---1---1.-....
83-0034098
3-38
NEe
Figure 7.
pPD7500H/H-E
Interface at Input/Output Ports
Type A
TEST,POO
Type 0
P30-P33, P20/PSTB, P21/PTOUT, P22, P23
Voo
Voo
P·ch
~I"P"
oataJb:
Output
Output
Disable
Vss
Vss
Type B
INTO, INT1, INT2, RESET, P03/S1
I
Type E
BUSO-BUS7, BUS10-BUS13, P40-P43, P50-P53,
P60-P63, P70-P73, P02/S0, P10-P13
Data
TypeD
Output
InlOut
Disable
TypeC
BUSS, BUSg OOUT, ALE, PSEN, LCD CL, CSOUT, STB
Type F
P01/SCK
Voo
Data
TypeD
Output
In/Out
Disable
t---~
Output
Vss
83·003410C
3-39
NEe
jlPD7500H/H-E
Absolute Maximum Ratings
TA
= 25°C
Operating temperature, TOPT
/JPD7500H
/JPD7500H-E
oto +40°C
-10 to +70°C
Storage temperature, TSTG
-65 to +150°C
Power supply voltage, VDD
-0.3 to +7.0 V
All input and output voltages
-0.3 to VDD + 0.3 V
Output current (total, all output ports)
IOH
IOL
-20 mA
50 mA
Comment: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC Characteristics
/JPD7500H: T A = 0 to +40°C, Voo == 5 V ±5%
/JPD7500H-E: T A = -10 to HO°C, Voo = 5 V ±10%
Limits
pPD7500H·E
/JPD7500H
Parameter
Symbol
Input high voltage
VIH1
0.7 VDD
VIH2
VIL1
VIL2
Input low voltage
Input leakage current, high
Typ
Min
Max
Min
VDD
0.7 VDD
VDD - 0.5
VDD
0
0.3 VDD
0
IUH1
Typ
Max
Unit
VDD
V
All inputs other than CL 1, X1
Test Conditions
VDD - 0.5
VDD
V
CL1, X1
0
0.3 VDD
V
All inputs other than CL 1, X1
0.5
0.5
V
3
3
pA
CL1, X1
All inputs other than CL 1, X1
IUH2
10
10
pA
CL1, X1
Input leakage current, low
IUL1
-3
-3
/JA
All inputs other than CL 1, X1
-10
VOH
/JA
V
CL1, X1
Output voltage, high
Output voltage, low
VOL
0.4
V
Output leakage current, high
ILOH
3
3
/JA
Vo = VDD
Output leakage current, low
ILOL
-3
-3
VO=O V
Supply current
IDD1
4
3
/JA
mA
20
/JA
-10
IUL2
IDD2
VDD -1.0
VDD -1.0
0.4
2
20
2
IOH = 1.0 mA
Normal operation, all output pins
open, no BUS conflicts
Stop mode, X1
=0 V
Capacitance
TA
= 25°C, Voo =0 V, f = 1 MHz
Limits
pPD7500H
Parameter
Symbol
Input capacitance
Output capacitance
1/0 capacitance
3-40
Co
Min
Typ
pPD7500H·E
Max
Min
Max
Unit
Test Conditions
15
Typ
15
pF
Unmeasured pins returned to Vss
15
15
pF
15
15
pF
t-lEC
pPD7500H/H-E
AC Characteristics
pPD7500H: TA = 0 to 40°C, VDD = 5 V ±5%
pPD7500H-E: TA = -10 to +70°C, VDD = 5 V ±10%
Limits
pPD7500H
pPD7500H·E
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
System clock oscillation frequency
f¢
300
400
500
160
200
250
kHz C = 33 pF ±5%;
pPD7500H: R= 33 kn ±2%;
pPD7500H·E: R= 62 kn ±2%
700
10
410
kHz CL 1 = external clock
CL 1 input rise time
tCR
0.2
0.2
ps
CL 1 input fall time
tCF
0.2
0.2
ps
CL 1 input clock width (high)
tCH
0.7
1.2
CL 1 input clock width (low)
tCl
0.7
1.2
Count clock oscillation frequency (X1, X2)
fxx
25
Parameter
Test Conditions
Clock Operation
10
32
50
25
0
ps
ps
32
50
kHz Crystal oscillation
Count clock input frequency (X1)
fx
700
410
kHz
X1 input rise time
fXR
0.2
0.2
ps
X1 input fall time
fXF
0.2
0.2
ps
X1 input clock width (high)
tXH
0.7
1.2
ps
X1 input clock width (low)
tXl
0.7
1.2
ps
ALE pulse width (high)
tlH
400
600
ns
Address setup time to ALE!
tAL
100
200
ns
Address hold time to ALE!
tlA
80
80
ns
tO~~
200
200
ns
Output data hold time after DOUT f
tooo
80
80
ns
DOUT pulse width (low)
tOOL
400
600
ALE -
tLDV
600
700
tAOV
700
900
Bus 1/0 Operation
Output data setup time to DOUT
t
data input valid time
Address -
data input valid time
PSEN pulse width (low)
tpSl
PSEN -
data input valid time
tpsov
PSEN -
data float
tpsoF
700
ns
1000
300
ns
ns
600
0
ns
ns
ns
3-41
NEe
pPD7500H/H-E
AC Characteristics (cont)
Limits
IIPD7500H
Parameter
Symbol
Min
Typ
IIPD7500H-E
Max
Min
Typ
Max
Unit
Test Conditions
Port 110 Operation
Port 1 output setup time to STB t
tpST
200
200
ns
Port 1 output hold time after STB f
tSTP
80
80
ns
STB pulse width (low)
tSTL1
400
600
ns
Output data setup time to STB t
tOST
300
300
ns
Output data hold time after STB t
tSTO
80
80
ns
STB!- input data valid time
tSTDV
STB!- input data float time
tSTOF
Control setup time to STBl
tCST
200
200
ns
Control hold time after STBl
tSTC
80
80
ns
8S0
8S0
Port output mode
I/O expander mode
ns
ns
STB pulse width (low)
tSTL2
700
1000
ns
CSOUT setup time to STBl
tCSST
200
200
ns
CSOUT hold time after STBl
tSTCS
80
80
ns
2.S
3.0
liS
Input
2.86
4.9
liS
Output
1.1
1.3
liS
Input
1.3
2.2
liS
Output
1.1
1.3
liS
Input
1.3
2.2
liS
Output
Serial Interface Operation
SCK cycle time
SCK pulse width, high
SCK pulse width, low
tKCY
tKH
tKL
SI setup time to SCKt
tSIK
300
300
ns
SI hold time after SCKt
tKSI
4S0
4S0
ns
SO output delay after SCKt
tSKO
SOO
8S0
ns
Other Operations
INTO pulse width, high
tlOH
10
10
INTO pulse width, low
tlOL
10
10
JlS
INT1 pulse width, high
tl1H
2/f¢
2/f¢
liS
INT1 pulse width, low
tl1L
2/f¢
2/f¢
JlS
INT2 pulse width, high
tl2H
2/f¢
2/f¢
JlS
INT2 pulse width, low
tl2L
2/f¢
2/f¢
JlS
RESET pulse width, high
tRSH
10
10
JlS
RESET pulse width, low
tRSL
10
10
JlS
3-42
liS
NEe
J.lPD7500H/H-E
Timing Waveforms
Strobe Output TIming
AC Test Input
~O.7VDD
O.7VDD~
~~O~.3~V~D~D________________O_.3_V~D~D~
83·003411A
Clock Timing
Clllnpul
f:"T'~lh
tCR
Xllnpul
1=
83-003414A
tCF
txL4l/f~txH~1
_ _
tXR
tXF
83·003412A
Bus I/O Timing
\ ___------J/
Cll
\_----/
!---tLH-
ALE
J
!---tALf.tLA·
BUSO-BUS7,
BUS10-BUS13
BUSS,
BUSs
/
Address
\.
~
K
~
Data Out
K
I--tODO-- I'tooo'
i+---tLOV-
\
tAOV
II
t------tOOL - -
\
1/
tPSLI-tpsOV"
BUSO-BUS7,
BUS10-BUS13
l'tPSOF'
Data In
83-0034138
3-43
NEe
pPD7500H/H-E
Timing Waveforms (cont)
Port 1 I/O Expander Port Timing
Expander
Port Output
~
Port Control
Output Data
STO
J ,t
-
tOST
Expander
Port Input
Input Data
Port Control
I---tSTOF-
tSTOV
~tSTC'"
tCST
STB
tSTL2
I
~
_tcssT~_,1
CSOUT-it--,---'
II
I-tSTCS
_ _ _} _
83-0034159
Serial Interface Timing
Interrupt Input Timing
'NTO
[Rising Edge Triggered]
51 - - ! - - - - - - {
'Nn
[Rising Edge Triggered]
50
Output Data
83-003416A
'Nn
[Failing Edge Triggered]
----I"~~ ~"~=i
1---- ---*T
i'--
----I""~
1---- ---*T~'''"=1i'-~'''"=i~''''~ r
---'1"
11-- --¥
RESET Input Timing
'Nn
[Rising Edge Triggered]
83-003318A
3-44
c="ait=''"=iI\1----
____
~
83-003417A
t¥EC
pPD7501
4-BIT, SINGLE-CHIP
CMOS MICROCOMPUTER
WITH LCD CONTROLLER/DRIVER
NEe Electronics Inc.
Description
Pin Configuration
The jlPD7501 4-bit, single-chip CMOS microcomputer
has advanced fourth-generation architecture with the
functional blocks necessary for a single-chip controller,
including an 8-bit timer/event counter, an 8-bit serial
I/O, and an LCD display controller/driver.
NC
P32
The jlPD7501 contains two 4-bit general-purpose
registers outside of RAM. The jlPD7501 executes a
su bset of the jlPD7500 series B instruction set with a
10-jls instruction cycle time.
P31
P30
4
P03/S1
P02/S0
Maximum power consumption is 900 jlA at 5 V and
300jlA at3 V. The HALT and STOP instructions further
reduc.e power consumption.
P63
P62
P61
P60
P53
Features
o
o
o
o
o
o
o
o
o
o
o
o
o
1024 x 8-bit program ROM
96 x 4-bit data RAM
Interrupts
-External: INTO, INT1
-Internal: INTT (timer/event counter), INTS
(serial interface)
a-bit timer/event counter
-Based on crystal oscillation
-External event counter (prescale option by 64)
Serial interface
LCD controller/driver
-Programmable multiplexing mode: triplex or
quadruplex
-4 common lines (COMo-COM3)
-24 segment lines (SO-S23)
Standby modes: stop, halt
Data retention mode
I/O ports
-3 input ports
-1 output port
-3 I/O ports
RC oscillation clock
Crystal oscillation clock
2.5 to 6.0 V operating voltages
CMOS technology
Ordering Information
Part No.
IIPD7501 G-12
Package Type
Max Frequency
of Operation
64-pin plastic miniflat
410 kHz
83-00330SA
Pin Identification
No.
Symbol
NC
Function
No connection
2-4,64
P33-P30
Output port 3
5-7,55
P03/S1
Input port 0, serial I/O interface,
external interrupt
P02/~
P01/SCK
POoIINT1
8-11
P63-P60
I/O port 6
12-15
P53-P50
I/O port 5
16-19
P43-P40
I/O port 4
20,21
X2, X1
Crystal clock/external event input
22
Vss
Ground
23-25
VLC03- VLC01
LCD bias voltage inputs
26,58
VOO
Positive power supply
27-30
COMo-COM3
LCD backplane driver outputs
31-54
S23- S0
LCD segment driver outputs
56
RESET
Reset input
57,59
CL1, CL2
System clock input
60-63
P13-P11
P1ollNTO
Input port 1, external interrupt
3-45
NEe
'pPD7501
:; Pin Functions
COM3-COMO [LCD Backplane Driver Outputs]
, P03-POO [Input Port 0]; 51, SO, SCK [Serial
, I/O Interface]; and INT1 [External Interrupt]
Leave unused pins open.
This port Gan be configured as a 4-bit parallel input
port or a~the 8-bit serial I/O interface under control of
-. the serial· mode select register. The ser .1 input SI,
seriaLoutput SO, and the se.rial clock SCK (active low)
usedfo{.~wrtchronizing data transfer make up the 8-bit
serialllO interface. Line POo is always shared with
external'interrupt INT1. If POo/1 NT1 is unused, it should
be connected to Vss. If P01/SCK, P0 2/SO, or P03/S1 are
unused, connect them to Vss or Voo.
, P13-P10 [Input Port 1] and INTO
[External Interrupt]
Four-bit input port. Line P10 is shared with external
interrupt INTO, a rising edge-triggered interrupt. If
P1o/INTO is unused, connect it to Vss. If P13-P11 are
unused, connect them to Vss or Voo.
P33-P30 [Output Port 3]
i
Four-bit latched three-state output port 3. Leave unused
pins open.
P43-P40 [I/O Port 4]
. Four-bit input/latched three-state output port. This
port also performs 8-bit parallel I/O with port 5. In
input mode, connect unused pins to Vss or Voo. In
output mode, leave unused pins open.
P53-P50 [I/O Port 5]
Four-bit input/latched three-state output port. This
port also performs 8-bit parallel I/O with port 4. In
input mode, connect unused pins to Vss or Voo. In
output mode, leave unused pins opel').
P63-P60 [I/O Port 6]
Four-bit input/latched three-state output port. The
port 6 mode select register configures individual lines
as inputs or outputs. In input mode, connect unused
pins to Vss or Voo. In output mode, leave unused pins
open.
3-46
S23-S0 [LCD Segment Driver Outputs]
Leave unused pins open.
VLC03-VLC01 [LCD Bias Voltage Inputs]
LCD bias voltage supply to the LCD voltage controller.
Apply appropriate voltages from a voltage ladder
connected across Voo. Leave unused pins open.
X2, X1 [Crystal Clock/External Event Input]
For crystal clock operation, connect a crystal oscillator
circuit to input X1 and output X2. For external event
counting, input event pulses to X1 and leave X2 open. If
X1 is not used, leave it open. If X2 is not used, connect it
to Vss.
CL 1, CL2 [System Clock Input]
Connect an 82-kO resistor across CL 1 and CL2, and
connect a 33-pF capacitor from CL 1 to Vss. Alternatively, connect an external clock source to CL 1 and
leave CL2 open.
RESET [Reset Input]
A high-level input to the RESET pin initializes the
pPD7501 after power-up.
VOO [Positive Power Supply]
Apply a single voltage in the range +2.7 to +6.0 volts
for proper operation.
NEe
pPD7501
Block Diagram
SCK/P01
X1
INTO/P10 INT1/POO
X2
Program Memory
1024 x 8 Bits
SI/P03
SO/ P02
Instruction
Decoder
Data Memory
96 x 4 Bits
LCDCL
System
Clock
Generator
CL1
CL2
LCD Controller/Driver
Standby
Control
i
VDD
i
Vss
i
RESET
COMO·COM3
VLCD1, VLCD2,
VLCD3
83-0033136
Details of some blocks on the diagram are illustrated
in figures 1 through 6 as listed below.
Figure
1
2
3
4
5
6
Title
Interface at Input/Output Ports
Clock Control
Timer/Event Counter
Test Control
Serial Interface
LCD Controller/Driver
3-47
NEe
JlPD7501
Figure 1.
Interlace at Input/Output Ports
Type E
P02/S0, P4o·P43, P50·P53, P60·P63
Type A
P11, P12, P13
Voo
Voo
Datalb:
Disable
Inputl
Output
Output
N·ch
Vss
Voo
Vss
Type B
POO/INT1, P03/SI, P10IlNTO, RESET
Vss
Type F
P01/SCK
Type D
P30·P33
Voo
Voo
P·ch
P·ch
Datalb:
Disable
Output
Datalb:
Disable
Inputl
Output
Output
Output
Vss
Vss
83-003320C
3-48
NEe
Figure 2.
J.lPD7501
Clock Control
Internal Bus
Clock Mode Register
Prescaler 1
(1/4)
CL
Prescaler 2
(1/64)
J---._-_+_
~~~ ~~ntrolierlDriVer)
Clock Mode Register
CM1
CMO
Count Pulse
CL x
2~6
xx
-i4
LCD Clock
CL x
2~6
x x-&CL x
~
____________________________-+ CP
(Timer/Event Counter)
2~6
83-0033218
Figure 3.
Timer/Event Counter
Internal Bus
~--~-----------------,
r-----------------------J
'TCNTAM
-------------_--------------+1
1---.----- :~oTinterruPt Circuit)
CP----_I
Count Hold
Circuit
1---1-_ _ _ _ _ _ _ TOUT
(To Serial Interface)
'Command Execution
'Timer
RESET
83-0033228
3-49
NEe
pPD7501
Figure 4.
Test Control
Test RQF
,Control
Q
Nonsync
Edge
Detect
INTT
INTT
RQF
TIMER'
SM3
INTS
Standby
Release
Q
Nonsync
Edge
Detect
INTO/S
RQF
INTO
CL
SIO'
INTI
RQF
Sync
Edge
Detect
INTI
Q
• Instruction Execution
83·0033238
Figure 5.
Serial Interface
PO~Slo-------------~~>-~4-~--~
P02/S0 o---------_----------~---<:
t-------------------t----------------------'
'----.J:l-+--- TOUT
t----¢
RS F/F
POO/INTI <>-------------~ : > - - - - - - 4 - -...
R
• Command Execution
¢ System Clock
1+---------- ~oT~nterruPt Circuit)
S .....- - - - - - - 'SIO
83·0033248
3-50
NEe
Figure 6.
pPD7501
LCD Controller/Driver
OP, OPL (Command Execution)
Data
Memory
LCD CL
~~~~~~~~~~
Multiplexer
So
VLC03
VLC02
VLCD1
COM3 COM2 COM1 COMO
Multiplexer
COMO-COM3 Outputs (Type G)
1-
P.ch
...L
T
P.ch
N·ch
OUT
LCD Voltage Ladder Connections
VOO
T
R
C
N·ch
H-
VLCD1
R
VLC02
50·523 Outputs (Type H)
f,
II
R
C
VLC03
II
R~ Y"
...L
P.ch
~------,
_~OUT
T
N·ch
VSS
r.
83-003325C
3-51
NEe
pPD7501
DC Characteristics
= 2.7 to 6.0 Volts
For VDD
T A = -10 to +70,oC
Limits
Parameter
Symbol
Input voltage, high
Input voltage, low
Min
Typ
Max
VIH1
0.7 VOO
VOO
V
Except CL 1, X1
VIH2
VOO - 0.5
VOO
V
CL1, X1
VIHOR
0. 9VOOOR
VOOOR + 0.2
V
RESET, data retention mode
0
0.3 Voo
V
Except CL 1, X1
0.5
V
CL1, X1
V
IOH = -1.0 mA; VOO = 4.5 to 6.0 V
V
10L = -100 IlA
VIL1
VIL2
0
Output voltage, high
VOH
VOO -1.0
Output voltage, low
VOL
VOO - 0.5
Input leakage current, high
Input leakage current, low
Test
Conditions
Unit
0.4
V
IOL = 1.6 mA; VOO = 4.5 to 6.0 V
0.5
V
10L = 400llA
IUH1
3
IlA
Except CL 1, X1; VI = VOO
IUH2
10
CL 1, X1; VI = VOO
IUL1
-3
IlA
IlA
IUL2
-10
IlA
CL1,X1;VI=OV
Except CL 1, X1; VI = 0 V
Output leakage current, high
ILOH
3
IlA
Vo = Voo
Output leakage current, low
ILOL
-3
IlA
Vo=OV
Output impedance (Note 1)
ReOM
3
5
kn
COMo-COM3; VOO = 4.5 to 6.0 V
5
15
kn
COMo-COM3
15
20
kn
SO-S23; VOO = 4.5 to 6.0 V
20
60
kn
SO-S23
6.0
V
300
900
IlA
Normal operation, VOO = 5 V ±10%;
R = 82 kn ±2%, C = 33 pF ±5%
70
300
IlA
Normal operation, VOO = 3 V ±10%;
R = 160 kn ±2%, C = 33 pF ±5%
Rs
Supply voltage
VOOOR
Supply current
1001
1002
1000R
Note:
(1)
VLCD
= 2.7 V to
V LCD1
VLCD2
VLCD3
3-52
= VDD = VDD = VDD -
V DD
(1/3) VLCD
(2/3) VLCD
VLCD
2.0
Data retention mode
= 0 V; VOO = 5 V ±10%
= 0 V; VOO = 3 V ±10%
Data retention mode, VOOOR = 2.0 V
1.0
20
IlA
Stop mode, X1
0.3
10
IlA
Stop mode, X1
0.2
10
IlA
NEe
JlPD7501
DC Characteristics (cont)
For VDD = 2.5 to 3.3 Volts
TA = -10 to +70°c
Limits
Typ
Min
Test
Conditions
Max
Unit
VOO
V
Except CL 1, X1
VOO
V
CL1, X1
VOOOR + 0.2
V
RESET, data retention mode
V
Except CL 1, X1
Parameter
Symbol
Input voltage, high
VIH1
O.B VOO
VIH2
VOO - 0.3
VIHOR
0. 9VOOOR
0
0.2 VOO
0.3
V
CL1, X1
V
IOH = -BOJ.lA
IOL = 350J.lA
Input voltage, low
VIL1
VIL2
Output voltage, high
VOH
Output voltage, low
VOO - 0.5
VOL
0.5
V
Output leakage current, high
ILOH
3
J.lA
Vo = Voo
Output leakage current, low
ILOL
-3
J.lA
Vo =OV
Supply voltage
VOOOR
Supply current
1001
1002
IOOOR
V
2.0
50
250
J.lA
Normal operation, VOO = 3 V ±10%;
R = 240 kn ±2%, C = 33 pF ±5%
35
230
J.lA
Normal operation, VOO = 2.5 V;
R = 240 kn ±2%, C = 33 pF ±5%
Storage temperature, TSTG
Power supply voltage, Voo
All input and output voltages
Output current high, IOH
Per pin
Total, output ports
Output current low, IOL
Per pin
Total, output ports
11
0.3
10
J.lA
Stop mode, X1 = 0 V; VOO = 3 V ±10%
0.2
10
J.lA
Stop mode, X1 = 0 V; VOO = 2.5 V
0.2
10
J.lA
Data retention mode, VOOOR = 2.0 V
Absolute Maximum Ratings
Operating temperature, TOPT
Data retention mode
Capacitance
-10 to +70°C
TA = 25°C, Voo=OV
Limits
-65 to +150°C
-0.3 to +7.0 V
-0.3 V to VOO + 0.3 V
-17mA
-20mA
Parameter
Symbol
Typ
Max
Input capacitance
CI
15
Output capacitance
Co
15
1/0 capacitance
CIQ
15
Test
Unit
Conditions
pF f=1 MHz;
unmeasured pins
pF
returned to Vss
pF
17mA
55 mA
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
3-53
NEe
pPD7501
AC Characteristics
For Voo = 2.7 to 6.0 Volts
T A = -10 to +70°C
Limits
Parameter
Symbol
Min
System clock frequency
fcc
fc
System clock rise and fall
time
tCR, tCF
System clock pulse width
tCH, tCl
Counter clock frequency
tKCY
SI hold time after SCK
t
SO delay time after SCK ~
240
kHz
VOO = 5 V ±10%; R = 82 kO ±2% (Note 1)
100
120
kHz
Voo = 3 V ±10%; R= 160 kO ±2% (Note 1)
75
135
kHz
R = 160 kO ±2% (Note 1)
10
410
kHz
CL 1, external clock, 50% duty; Voo = 4.5 to
6.0 V
10
125
kHz
CL 1, external clock, 50% duty; Voo = 2.7 V
0.2
ps
CL 1, external clock
1.2
50
ps
CL 1, external clock; Voo = 4.5 to 6.0 V
4.0
50
ps
CL 1, external clock; Voo = 2.7 V
50
kHz
X1, X2, crystal oscillator
410
kHz
X1, external pulse input, 50% duty;
Voo = 4.5 to 6.0 V
125
kHz
X1, external pulse input, 50% duty;
VDO = 2.7 V
0.2
ps
X1, external pulse input
32
1.2
ps
X1, external pulse input; Voo = 4.5 to 6.0 V
4.0
ps
X1, external pulse input; Voo = 2.7 V
3.0
ps
SCK as input; Voo = 4.5 to 6.0 V
8.0
ps
SCK as input
4.9
ps
SCK as output; Voo = 4.5 to 6.0 V
16.0
ps
SCK as output
1.3
ps
SCK as input; Voo = 4.5 to 6.0 V
4.0
ps
SCK as input
2.2
ps
SCK as output; Voo = 4.5 to 6.0 V
8.0
ps
SCK as output
tSIK
300
ns
tKSI
450
tKH, tKl
t
200
75
0
tXH, tXl
SI setup time to SCK
150
fx
Counter clock pulse width
SCK pulse width
Unit
25
tXR, tXF
SCK cycle time
Max
fxx
Counter clock rise and fall
time
tKSO
ns
850
ns
1200
ns
INTO pulse width
tIOH, tlOl
10
ps
INT1 pulse width
t11H, tl1l
2/f¢
ps
RESET pulse width
tRSH, tRSl
10
ps
RESET setup time
tSRS
0
ns
RESET hold time
tHRS
0
ns
Note:
(1) RC network at CL 1 and CL2; C = 33 pF ±5%,I~c/ocl~ 60 ppm.
3-54
Test
Conditions
Typ
Voo = 4.5 V to 6.0 V
t-IEC
pPD7501
AC Characteristics (cont)
For VDD
= 2.5 to 3.3 Volts
TA = -10 to +70°C
Limits
Parameter
Symbol
Min
System clock frequency
fcc
50
50
fC
System clock rise and fall
time
System clock pulse width
tCH, tCl
fxx
Counter clock rise and fall
time
Counter clock pulse width
tXH, tXl
SCK cycle time
tKCY
SCK pulse width
SI setup time to SCK
t
Unit
80
kHz
64
77
kHz
Voo = 2.5 V; R = 240 kn ±2% (Note 1)
80
kHz
CL 1, external clock, 50% duty
0.2
IlS
CL 1, external clock
10
6.25
50
IlS
CL 1, external clock
kHz
X1, X2, crystal oscillator
fx
80
kHz
X1, external pulse input, 50% duty
tXR, tXF
0.2
IlS
X1, external pulse input
6.25
IlS
X1, external pulse input
12.5
IlS
SCK as input
25.0
IlS
SCK as output
25
32
6.25
IlS
SCK as input
11.5
IlS
SCK as output
tSIK
t
SO delay time after SCK
IlS
tKSI
!
Voo = 5 V ±10%; R = 240 kn ±2% (Note 1)
50
tKH, tKl
SI hold time after SCK
Max
tCR, tCF
Counter clock frequency
Test
Conditions
Typ
IlS
2
tKSO
IlS
INTO pulse width
tlOH, tlOL
30
IlS
INT1 pulse width
t11H, tl1l
2/f¢
IlS
30
IlS
RESET pulse width
tRSH, tRSl
RESET setup time
tSRS
ns
RESET hold time
tHRS
ns
Note:
(1) RC network at CL 1 and CL2; C = 33 pF ±5%,I..6.C/ocl::; 60 ppm.
Recommended Rand C Values for System
Clock Oscillation Circuit
TA = -10 to +70°C
Supply Voltage Range
Recommended
Values (Note 1)
Frequency Range
4.5 to 6.0 V
R = 82 kn ±2%
150 to 240 kHz,
200 kHz typical
2.7 to 3.3 V
R =160 kn ±2%
75 to 120 kHz,
100 kHz typical
2.7 to 6.0 V
R =160 kn ± 2%
75 to 135 kHz
2.5 to 3.3 V
R = 240 kn ±2%
50 to 80 kHz
2.5 V
R = 240 kn ±2 %
50 to 77 kHz
Note:
(1) C = 33 pF ±5%,I..6.C/ocl::; 60 ppm.
3-55
t-{EC
pPD7501
Timing Waveforms
External Interrupts
A C Test Points
Voo
==X
007VOO
~Oo~3~V~o~o
= 2.7 to 6.0 V
Oo7V00X==
Test Points
_________________O~o3~V~o~o
Voo
,,,,~"O'=V="O"~
'N"~''''=V='""~
= 2.5 to 2.7 V
=X
008VOO
Oo8V00X=
Test Points
~O~o2~V~O~O_________________O~o2~V~oo
83-003317A
83-003314A
Reset
Clocks
83-003318A
CL1
Data Retention
X1
Data Retention Mode
VOO
RESET
Seriallntertace
SI
so
VIHOR
83-003319A
---!-------{
Valid Output Data
)(
~------'
83-003316A
3-56
VOOOR
NEe
JlPD7501
Operating Characteristics
fe vs Vee
1000
~1
r-
400
~
~
>.
u
[TA = 25°C]
t2
-I 1---1
CL1~
c:
"'"
..
~
r-
>.
u
"'"
tl
2t2
.
Q.
Defined
Operating Voltage
2tl
0
10
'"
"0
c:
til
()
1
1
o
o
Supply Voltage VOO [V]
Supply Voltage Voo [V]
fCC vs Vee
lee vs Vee
500
1000
~
l"
500
c
E
100
33
50
[TA
.---::::
~
pF
I
10
>.
:: I
~
lJ'q'~
0
kHz
til
0.5
0.1
E 22
pF
o
--kO
33
1
l"
pF
r' ---
I
-
N
~
400
~ 300
~:~i [~:~ ~gl-
>.
u
-
I---
200
I---
---
..g
I--"'"
'"
c:
~
150
~
l"
I---
I"
+ Xtal Oscillation
33pF
.~
.-
100
0
!
--
til
50
---- _.
I
-
c:
!
c:
~
100
'u
..0
u
0
r
[TA
33pF
20
c:
"'"
voo~~
!
c:
~
'u
""'-'-
..
200
r-l"
0
is
~
100
R CL2
u
'"
Resistance R [kO]
100
0
Voo=2.5V~
'"'"
50
~Ll
150
0
:-..
R
1I
--------------1-----
>.
u
I I
!
R = 82 kO
~
r'--,
r---
til
Voo = 5 V,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ f- _
__ _
N
25 o
~ 200~----~----~--------------r-------~--9F~~~~~
(3
20
1 cl-
(J
2~
l"
E
R=240kO-
250r----------r----------r---------~--------~
......
~
50
I
- voo = 51 '"'
200
"'"
.-
160kO
fCC vs TA
1 .1.
>.
u
ro-
R
Supply Voltage Voo [V]
fCC vs R
(J
.-
2
500
~
f - - - - - R = 82 kO
f--
---- f-'----
Supply Voltage Voo [V]
~
---
R
I---
0
STOP [Xl = 0 V]
[t=25 0 C ] -
I
(J
250
STOP
X2
[82 kO]
[160 kO]
[240 kO]
HALT [82kO]
c:
,
I
Xl
()
-
25°C]
R
c:
~
v
u
(3
10
!
~
~
r
tl>t2:fx=~
tlt2:fC= ~
2t2
100 I-
fX vs Vee
1000
I
500
(3
E
50
i
til
Voo=3V,
--r-----,....---------------------------R = 160 kO
C
_ _ _ _ _ _ _ _ ..... _ _ _ _ _ _ .
.....
I.....
-·Voo=2.5V,- '"
OL-________L -________L -________L -______
-25
~
R=240kO
C = 33 pF
r"C/OC 560 ppm
25
50
~~
75
Operating Temperature T A [OC]
3-57
NEe
pPD7501
Operating Characteristics (cont)
1001 VS
fcc
1001 vs TA
500
500
;c
.5!.
Q 400
0
"'"
~
~
l
....
E
300
33pF
c
!
C
E
~
"'"
R
I
0
200 f - -
c
c
~
ii
300 f - -
c
~
0 200
a,.,
400
~
100
~g
§'
0
1il
0
50
100
150
200
250
100
5 V, R
82 kO
R
Voo
= 3 V, R = 160 kO
1
-25
300
25
50
Operating Temperature TA [OC]
IOL
IOH vs VOH
VS
VOL
20
-6
[TA
= 25°C]
;c
-5
!.
....
:J:
E
5}
~
0
c
~
0
15
_ _- - , Voo=3V
-;
...
:I
-;
Voo
0
'ii -2
= 3V
~
0
___+---
Voo = 2.5 V
l!
~
~
~
.2'
:r
High-Level Output Voltage VOH [V]
3-58
I
o
System Clock Oscillation Frequency fCC [kHz]
;c
~
l
33pF
,.,
~til
-= r =
voo
0
til
!.
-
Low-Level Output Voltage VOL [V]
75
NEe
NEe Electronics Inc.
Description
The pPD7502 and pPD7503 4-bit, single-chip CMOS
microcomputers have advanced fourth-generation architecture with the functional blocks necessary for a
single-chip controller, including an 8-bit timer/event
counter, an 8-bit serial liD, and an LCD controller/
driver.
The instruction set includes the following types of
instructions: addressing, table look-up, bit manipulation, vectored dump, auto increment or decrement
data pointer, and conditional skip. These instructions
maximize use of fixed program memory space.
pPD7502/03
4-BIT, SINGLE-CHIP
CMOS MICROCOMPUTERS
WITH LCD CONTROLLER/DRIVER
o RC oscillation clock
o Crystal oscillation clock
o 2.7 to 6.0 V operating voltage
o CMOS technology
Ordering Information
Package Type
Part No.
Max Frequency
of Operation
pPD7502G-12
64-pin plastic miniflat
410 kHz
pPD7503G-12
64-pin plastic miniflat
410 kHz
Pin Configuration
Both devices are manufactured with the CMOS process
and have a maximum power consumption of 900 pA at
5 V and 300 pA at 3 V. Halt and stop modes further
reduce power consumption.
These devices are ideal for a wide range of solar- and
battery-powered applications.
Features
o 92 powerful instructions
o Program ROM
o
o
o
o
o
o
o
o
- pPD7502: 2048 x 8-bit
- pPD7503: 4096 x 8-bit
Data RAM
- pPD7502: 128 x 4-bit
- pPD5703: 224 x 4-bit
Interrupts
- External: INTO, INT1
- Internal: INTT (timer/event counter)
INTS (serial interface)
8-bit timer/event counter
- Based on crystal oscillation
- External event counter (prescale option by 64)
Serial interface
LCD controller/driver
- Programmable multiplexing mode: triplex or
quadruplex
- 4 common lines (COMo-COM 3)
- 24 segment lines (SO-S23)
Standby modes: stop, halt
Data retention mode
I/O ports
- 3-bit input port
- 4-bit input port
- 4-bit output port
- Two 4-bit I/O ports with 8-bit capability
- 4-bit I/O port with each bit configurable as an
input or output
NC
1
P3,
3
P30
4
P03fSI
5
P02/S0
6
0
PO,/SCK
P63
P62
9
P6,
10
P60
11
P53
12
P52
13
P5,
14
P50
15
P43
16
P42
17
P4,
18
P40
19
83-003429A
3-59
NEe
pPD7502/03
Status of Unused Pins
Pi n Identification
Symbol
Name
Pin Connection
NC
No connection
CL2
Open
2-4.64
P33-P30
4-bit output port 3
X1
Vss
5-7
P03/S1
3-bit input port O. or
serial I/O interface
X2
Open
VSS or VDD
Vss
No.
P02/~
function
8-11
P63-P60
4-bit I/O port 6
P01/SCK
PO:!/SO
P03/S1
12-15
P53-P50
4-bit I/O port 5
P1o/INTO
16-19
P43-P40
4-bit I/O port 4
P11-P13
VSS or VDD
20.21
X2. X1
Crystal clock/external event
input port X
P30-P33
Open
22
Vss
Ground
Input mode: Vss or VDD
Output mode: Open
23-25
P40-P43
P50-P53
P60-P63
P01/SCK
VLCD3- VLCD1
LCD bias supply inputs
26.58
VDD
Positive power supply
27-30
COM3-COMo
LCD backplane driver outputs
31-54
S23- S0
LCD segment driver outputs
55
INT1
External interrupt
56
RESET
RESET input
57.59
CL1. CL2
System clock input
60-63
P13-P11.
P10llNTO
4-bit input port 1. or
external interrupt INTO
3-60
INT1
Vss
SO-S23
COMo-COM3
VLCD1- VLCD3
Open
NEe
pPD7502/03
Pin Functions
P03/SI, P02/S0, P01/SCK [Port 0 or Serial
Interface]
This port can be configured as a 4-bit parallel input
port 0 or as the 8-bit serial I/O interface under control
of the serial mode select register. The serial interface
consists of the serial input (SI), the serial output (SO),
and the serial clock (SCK), which synchronizes data
transfer.
P13-P11, P1011NTO [Port 1 or Interrupt]
INT1 [Interrupt]
This external interrupt is a rising edge-triggered
interrupt.
RESET
A high-level input to this pin initializes the pPD7502/
7503.
X2, X1 [Crystal Clock/External Event Input Port X]
4-bit input port 1. Line P10 is shared with external
interrupt INTO, which is a rising edge-triggered interrupt.
For crystal clock operation, connect a crystal oscillator
circuit to input X1 and output X2. For external event
counting, input external event pulses to X1 and leave
X2 open.
P33-P30 [Port 3]
CL 1, CL2 [System Clock Input]
4-bit, latched three-state output port 3.
P43-P40 [Port 4]
Connect an 82-kO resistor across CL 1 and CL2, and a
33-pF capacitor from CL 1 to Vss. Or, connect an
external clock source to CL 1 and leave CL2 open.
4-bit input or latched three-state output port 4. Can
perform 8-bit I/O in conjunction with port 5.
VLC03-VLC01 [LCD Bias Voltage Inputs]
P53-P50 [Port 5]
4-bit input or latched three-state output port 5. Can
perform 8-bit I/O in conjunction with port 4.
LCD bias voltage supply inputs to the LCD voltage
controller. Apply appropriate voltages from a voltage
ladder connected across VDD.
VOO
P63-P60 [Port 6]
4-bit input or latched three-state output port 6. The port
6 mode select register configures individual lines as
inputs or outputs.
COM3-COMO [LCD Backplane Driver Outputs]
Positive power supply. For proper operation, apply a
single voltage from 2.7 to 6.0 V.
Vss
Ground.
LCD backplane driver outputs.
S23-S0 [LCD Segment Driver Outputs]
LCD segment driver outputs.
3-61
3
NEe
pPD7502/03
Block Diagram
SCK/P01
INT1 INTO/POO
X2
X1
SI/P03
SO/P02
H [4]
Program Memory
2048 x 8 Bits [7502]
4046 x 8 Bits [7503]
Instruction
Decoder
Data Memory
128 x 4 Bits [7502]
224 x 4 Bits [7503]
LCDCL
System
Clock
Generator
CL1
CL2
LCD Controlier/Drlver
Standby
Control
r
VDD
r
VSS
r
RESET
COMO·COM3
VLCD1. VLCD2.
VLCD3
83-0034308
See figures 1 through 8 for additional block diagram
details.
Figure
1
2
3
4
5
6
7
8
3-62
Title
Data Memory Map
Program Memory Map
Interface at Input/Output Ports
Clock Control
Timer/Event Counter
Interrupt Control
Serial Interface
LCD Controller/Driver
NEe
Figure 1.
pPD7502/03
Figure 2.
Data Memory Map
Address
[DeCima~
Address
Program Memory Map
Address
[Decimal]
MSB
r-----------. ~~~xJ
LCD Segment Data
Storage Area
Address
[Hex]
LSB
OOOH
RESET Pulse Vectors Program
Execution to Address DOH
16
010H
INTT [Internal TimerlEvent
Counter Interrupt] Vectors
Execution to 010H
32
020H
INTOIS [External Interrupt or
Serial Interface Interrupt]
Vectors Execution to 020H
48
030H
INT1 [External Interrupt 1]
Vectors Execution to 030H
0
716151413121110
~! I--------~ ~~~
~
...'" ...":c
...":c 0~
I'PD7502
0
It)
~
Q
11-
192
OCOH
207
208
OCFH
ODOH
255
OFFH
1023
1024
3FFH
400H
_,-2047
2048
7FFH
800H
I - '-----4095
FFFH
~
0
I'PD7503
~
223
L.-_ _ _ _ _ _ _......
Q
11-
LHL T Instruction
Reference Table
CALT Instruction
Reference Table
Last Address for
CALL Instruction
Entry (lJPD7503]
DFH
83-003432 A
83-003431 A
3-63
~EC
pPD7502/03
Figure 3.
Interlace at Input/Output Ports
Type A
P11, P12, P13
Type E
P02/S0, P40·P43, P50·P53, P60·P63
Voo
Voo
P·ch
Datalb:
Disable
Inputl
Output
Output
Voo
Vss
Vss
Type B
INT1, P03/SI, P10/INTO, RESET
Vss
Typ~
Type D
P3o·P33
P01/SCK
Voo
Voo
P·ch
P·ch
Datalb:
Disable
Output
Datalb:
Disable
Inputl
Output
Output
Output
Vss
Vss
83-003859C
3-64
NEe
Figure 4.
pPD7502/03
Clock Control
Internal Bus
Clock Mode Register
Prescaler 1
CL
(1/4)
Prescaler 2
(1/64)
LCD CL
l - -___- - . (LCD Controller/Driver)
Clock Mode Register
CM1
CMO
Count Pulse
CL x
LCD Clock
2k-
CL x
2~6
> - - - - - - - - - - - - - - - - ~~mer/Event Counter)
CL x
x
2!6-
x-&83-003321B
Figure 5.
Timer/Event Counter
Internal Bus
L -__~______________- ,
r-------------------~
'TCNTAM - - - - - - - _ - - - - - - - . - \
~----- ~oT~nterruPt Circuit)
CP------;~
Count Hold
Circuit
J...--I----_
~~u;erial Interface)
'Command Execution
'Timer
RESET
83-0033228
3-65
NEe
pPD7502/03
Figure 6.
Interrupt Control
INT1 ( r - - i - - = - = , - - - - - - - - f
INTS
P10/lNTO o - - t - - f
SIO·
INTT----------I
Standby
Release
·Command Execution
83-0034336
Figure 7.
Ser/allnterlace
"IP
"IPL
PO~Slo---------~=>--+-+-r--~
P02/S0 0 - - - - - - - - ' - - - - - - - - - - - + - - - < 1---------------1I-------------~
'---IO-+-- TOUT
-=----r/J
RS F/F
--+---- ~oT~nterruPt Circuit)
R .....
"Command Execution
r/J System Clock
S .....- - - - - "SIO
83-0038056
3-66
NEe
Figure 8.
pPD7502/03
LCD Controller/Driver
OP, OPL (Command Execution)
Data
Memory
LCD CL
~~~~~~~~~~
Multiplexer
So
VLCD3
VLCD2
VLCD1
COM3 COM2 COM1 COMo
COMO-COM3 Outputs (Type G)
Multiplexer
J.-
P-ch
..L
T
P-ch
N-ch
OUT
LCD Voltage Ladder Connections
T
VDD
R
C
a--
VLCD1
R
C
~L
VLCD2
II
R
VLCD3
r.
N-ch
50-523 Outputs (Type H)
...L
~_P_-C_h____________- .
_~OUT
T
N-ch
II
R~ V"
Vss
d.,
83-003325C
3-67
tt{EC
pPD7502/03
Absolute Maximum Ratings
Capacitance
TA=25°C
TA=25°C;VDD=OV
-0.3 to +7.0 V
Power supply voltage, Voo
All input and output voltages
-0.3 V to Voo + 0.3 V
Output current high, IOH
Per pin
Total, output ports
-:17 rnA
-20 rnA
Output current low, IOL
Per pin
Total, output ports
17 rnA
55 rnA
Limits
Parameter
Symbol
Min
Typ
Max
Unit
Input
capacitance
CI
15
pF
Output
capacitance
Co
15
pF
1/0
capacitance
CIO
15
pF
Test
Conditions
fc = 1 MHz
Unmeasured
pins returned to
Vss
-10 to +70°C
Operating temperature, TOPT
-65 to +150°C
Storage temperature, TSTG
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
For VDD
= 2.5 to 3.3 Volts
TA = -10 to +70°C
Limits
Parameter
Symbol
Input voltage, high
VIH1
VIH2
VIHOR
Input voltage, low
VIL1
Typ
Test
Conditions
Max
Unit
O.B Voo
Voo
V
Except CL1, X1
Voo - 0.3
Voo
V
CL1, X1
0.9 VOOOR
VOOOR + 0.2
V
RESET, data retention mode
0
0.2 VOO
V
Except CL 1, X1
0.3
V
CL1, X1
V
10H = -BOpA
IOL = 350pA
Min
VIL2
0
Output voltage, high
VOH
Voo - 0.5
Output voltage, low
VOL
0.5
V
Input leakage current, high
IUH1
3
pA
Except CL 1, X1; VIN = Voo
IUH2
10
pA
CL1, X1; VIN = Voo
Input leakage current, low
Output leakage current, high
Output leakage current, low
Supply voltage
Supply current
IUL1
-3
f.JA
Except CL1, X1; VIN = 0 V
IUL2
-10
pA
CL 1, X1; VIN = 0 V
ILDH
3
pA
Vo = Voo
ILOL
-3
pA
Vo =OV
VOOOR
1001
1002
1000R
3-68
V
2.0
Data retention mode
50
250
pA
Normal operation, VOO = 3 V ± 10%; R
= 240 kO ±2%, C= 33 pF ±5%
35
230
pA
Normal operation, VOO = 2.5 V; R = 240
kO ±2%, C = 33 pF ±5%
0.3
10
pA
Stop mode, X1 = 0 V; Voo = 3 V ±10%
0.2
10
f.JA
Stop mode, X1 = 0 V; Voo = 2.5 V
0.2
10
pA
Data retention mode, VOOOR = 2.0 V
NEe
pPD7502/03
DC Characteristics (cont)
==:::: 2.7
TA = -10 to +70°C
For VDD
to 6.0 Volts
Limits
Parameter
Symbol
Input voltage, high
VIH1
VIH2
VIHOR
0.9 VOOOR
VOOOR + 0.2
0
0.3 VOO
0.5
Input voltage, low
VIL1
Min
Typ
Unit
0.7 VOO
VOO
V
Except CL 1, X1
VOO - 0.5
VOO
V
CL1, X1
V
Except CL 1, X1
VIL2
0
Output voltage, high
VOH
VOO -1.0
Output voltage, low
VOL
Voo - 0.5
Input leakage current, high
Input leakage current, low
Test
Conditions
Max
RESET, data retention mode
V
CL1, X1
V
IOH = -1.0 rnA, VOO = 4.5 to 6.0 V
V
IOL = - 1OO f.J A
0.4
V
IOL = 1.6 rnA, VOO = 4.5 to 6.0 V
0.5
V
IOL = 400f.JA
IUH1
3
f.JA
IUH2
10
f.JA
CL1, X1
IUL1
-3
f.JA
Except CL 1, X1; VI =0 V
Except CL 1, X1; VI = Voo
IUL2
-10
f.JA
CL1, X1
Output leakage current, high
ILOH
3
f.JA
Vo = Voo
Output leakage current, low
ILOL
-3
f.JA
Vo=O V
3
5
kn
COMo-COM3; VOO = 4.5 to 6.0 V
5
15
kn
COMo-COM3
15
20
kn
SO-S23; VOO = 4.5 to 6.0 V
20
60
kn
SO-S23
6.0
V
300
900
f.J A
Normal operation, VOO =5 V ± 10%;
R= 82 kn ± 2%, C= 33 pF ± 5%
70
300
f.JA
Normal operation, VOO =3 V ± 10%;
R = 160 kn ± 2%, C = 33 pF ± 5%
Output impedance (1)
ReOM
Rs
Supply voltage
Supply current
VOOOR
1001
1002
1000R
2.0
Data retention mode
1.0
20
f.JA
Stop mode, X1 = 0 V; Voo
= 5 V ± 10%
0.3
10
f.JA
Stop mode, X1 = 0 V; Voo
= 3 V ± 10%
0.2
10
f.JA
Data retention mode, VOOOR = 2.0 V
Note:
(1)
VLCD = 2.7 V to VDD
V L CD1
VDD - (1/3) VLCD
VLCD2 = VDD - (2/3) VLCD
VLCD3
VDD - VLCD
=
=
3-69
NEe
pPD7!i02103
AC Characteristics
For VDD
TA
= 2.7 to 6.0 Volts
= -10 to +70°C
Limits
Test
Conditions
Parameter
Symbol
Min
Typ
Max
Unit
System clock frequency
fcc
150
200
240
kHz
Voo:= 5 V ±10%; R:= 82 kn ±2% (Note 1)
75
100
120
kHz
Voo := 3 V ±10%; R:= 160 kn ±2% (Note 1)
75
135
kHz
R:= 160 kn ±2% (Note 1)
10
410
kHz
CL 1, external clock. 50% duty; Voo := 4.5 to
6.0 V
10
125
kHz
CL 1. external clock. 50% duty; Voo := 2.7 V
0.2
jJS
CL 1. external clock
1.2
50
jJS
CL 1. external clock; Voo := 4.5 to 6.0 V
4.0
50
jJS
CL 1. external clock; Voo := 2.7 V
50
kHz
X1. X2. crystal oscillator
fc
System clock rise and fall
time
tCR. tCF
System clock pulse width
tCH. tCl
Counter clock frequency
fxx
25
fx
0
410
kHz
X1. external pulse input. 50% duty;
VDD := 4.5 to 6.0 V
0
125
kHz
X1. external pulse input. 50% duty;
Voo:= 2.7 V
0.2
jJS
X1. external pulse input
Counter clock rise and fall
time
tXR. tXF
Counter clock pulse width
tXH. tXl
SCK cycle time
tKCY
SCK pulse width
SI setup time to SCK
tKH. tKl
t
SI hold time after SCK
t
SO delay time after SCK
l
32
1.2
jJS
X1. external pulse input; Voo := 4.5 to 6.0 V
4.0
jJS
X1. external pulse input; Voo := 2.7 V
3.0
jJS
SCK as input; Voo := 4.5 to 6.0 V
8.0
jJS
SCK as input
4.9
jJS
SCK as output; Voo := 4.5 to 6.0 V
16.0
jJS
SCK as output
1.3
jJS
SCK as input; Voo := 4.5 to 6.0 V
4.0
jJs
SCK as input
2.2
jJS
SCK as output; Voo := 4.5 to 6.0 V
8.0
jJs
SCK as output
tSIK
300
ns
tKSI
450
ns
tKso
850
ns
1200
ns
INTO pulse width
tlOH. tlOL
10
jJs
INT1 pulse width
t11H. tl1l
2/frp
jJS
RESET pulse width
tRSH. tRSl
10
jJS
RESET setup time
tSRS
0
ns
RESET hold time
tHRS
0
ns
Note:
(1) RC network at CL 1 and CL2; C := 33 pF ±5%.lllC/oCI~ 60 ppni.
3-70
Voo := 4.5 V to 6.0 V
NEe
pPD7502/03
AC Characteristics (cont)
For VDD = 2.7 to 5.5 Volts
TA=-10to+70°C
Limits
Parameter
Symbol
System clock frequency
fcc
Min
50
50
fc
System clock rise and fall
time
Typ
64
10
tCR, tCF
Max
Unit
Test
Conditions
80
kHz
Voo = 5 V ±10%; R= 240 kn ±2% (Note 1)
77
kHz
Voo = 2.5 V; R= 240 kn ±2% (Note 1)
80
kHz
CL 1, external clock, 50% duty
0.2
J1S
CL 1, external clock
50
J1S
CL 1, external clock
50
kHz
X1, X2, crystal oscillator
fx
80
kHz
X1, external pulse input, 50% duty
tXR, tXF
0.2
J1S
X1, external pulse input
System clock pulse width
tCH, tCl
Counter clock frequency
fxx
Counter clock rise and fall
time
Counter clock pulse width
6.25
25
32
tXH, tXl
6.25
J1S
X1, external pulse input
SCK cycle time
tKCY
12.5
J1S
SCK as input
25
J1S
SCK as output
SCK pulse width
tKH, tKL
6.25
J1S
SCK as input
11.5
J1s
SCK as output
SI setup time to SCK
t
SI hold time after SCK
tSIK
t
SO delay time after SCK
INTO pulse width
tKSI
!
2
tKSO
tlOH, tlOL
30
INT1 pulse width
tl1H, tl1l
2/fr/J
RESET pulse width
tRSH, tRSl
30
Note:
(1) RC network at CL 1 and CL2; C = 33 pF ±5%,I~C/°Cl:::; 60 ppm.
Recommended Rand C Values for System
Clock Oscillation Circuit
TA = -10 to +70°C
Supply Voltage Range
Recommended
Values (Note 1)
Frequency Range
4.5 to 6.0 V
R =82 kn ±2%
150 to 250 kHz,
200 kHz typical
2.7 to 3.3 V
R =160 kn ±2%
75 to 120 kHz,
100 kHz typical
2.7 to 6.0 V
R =160 kn± 2%
75 to 135 kHz
2.5 to 3.3 V
R = 240 kn ±2%
50 to 80 kHz
2.5 to 6.0 V
R = 240 kn ±2 %
50 to 85 kHz
Note:
(1) C = 33 pF ±5%,I~C/°Ci:::; 60 ppm.
3-71
NEe
pPD7502/03
Timing Waveforms
Timing Measurement Points
Voo
=X
External Interrupts
= 2.7 to 6.0 V
0.7VDDX="
Test Points
~0.~3~V~DD~_______________0_.3~V~D~D
---yo
0.7VDD
Voo
0.8 VDD
INro ~"o'=r="OH~
INn~""=r="'~
= 2.5 to 2.7 V
0.8 VDD
V
83-003317A
~~0_.2_V~D~D______
Th_st_p_o_ln_ts______
0._2_VD
__
Df~
83-003314A
Reset
Clocks
83-003318A
CL1
Data Retention Mode
Data Retention Mode
X1
VDD
RESET
Seria/lnterlace
SI
so
VIHDR
83-003319A
---+---------{
Valid Output Data
83-003316A
3-72
VDDDR
NEe
pPD7502/03
Operating Characteristics
25°C
TA =
fCC vs Voo
fC vs VOO
500
N
~
1000
400
E
>-
"c
""
I
400
200 I---
~
33pF
J;
---
R
.-
+---
.-
- .-
U)
50
~
(
R-82kO
100 f-
[TA = 25'C]
t2
....1 1---1
CL1~
tl>t2:fC= ~
212
~
g
(3
160 kO
10
!
U)
R = 240 kO-
1
o
Supply Voltage VOO [V]
Supply 'Voltage Voo [V]
fCC vs R
N
~
E
~
.l<
g
I I
I 5_J
cl-
[TAl 25 o
£
100
J;
R
100 ~
.t
"
..............
E
"0
(3
I I
i
[
20
-
+_
~
12: fX = _~
212
"c
U)
"
Xl~
~
.l<
VOO=2.5V~
50 f---
>c
[TA = 25°C]
12
....11--1
211
C
;:00...
I
11<12:fx=~
Q.
(3
20
11
400 ~
>-
"c
""...
..............
33pF
I
~
l'
...""
~
VO
1000
f-
>u 200
c
.tc
fX vs VOO
r i""'1'
voo~
t=~
t=
~
()
V
.l<
R
2
500
V
Defined
Operating Voltage
11<12:fC= ~
211
.t
t-
---I--
E
i
1-----
---- +------
.-
100
t-
~
150 I---
'u
.l<
N
~
300 f--250 I---
c
0
"0
(3
il
[t=25 0 C ] -
I
()
I
~
75
&l
0.1
0
Supply Voltage VOO [V]
'l_7'l
t-{EC
pPD7502/03
Operating Characteristics (cont)
1001 vs
fcc
IOH vs VOH
-6
500~----~------~------r-----~------'-----~
[TA = 25°C)
~
~
1
o 400
E
~
~
Io
33 pF
300
R
:«.§.
l:
5}
c
0
...
::0
200~-----+-------h~----~-----+------4-----~
___~__------~VOO=3V
0
100~-7~-+------4-------~-----+------+-----~<
~
-3
::0
~
~
-4
§
----!-----""""7'''f'------+-----
C
o
-5
~
!
J:
-2
-1
§
o
OL-----~----~------L-----~----~----~~
o
50
100
150
300
250
200
System Clock Oscillation Frequency
fcc [kHz)
High-Level Output Voltage VOH [V)
IOL vs VOL
1001 vs TA
500
20
:«,3;
[TA= 25°C)
0 400
E
...
III
0
::E
c
'"
!
x.
0
c
300
r-
200 I------
~
0
>-
Q.
-
--
~
1
33pF
-
~
~
_ _---, Voo = 3 V
10
__-+---
Voo = 2.5 V
!
R
100
Voo
i
= v. R = 160 kCl
<
~
•
.3
§
~
25
Operating Temperature TA [OC)
3-74
15
~
0
0
g.
o
..J
5}
c:
....
Voo = 5 V. R = 82 kCl
tJ)
-25
:«.§.
50
75
Low-Level Output Voltage VOL [V)
NEe
NEe Electronics Inc.
pPD7506
4-BIT, SINGLE-CHIP
CMOS MICROCOMPUTER
Description
Pin Configurations
The J.lPD7506 CMOS 4-bit single chip microcomputer
has the J.lPD7500 series architecture. Twenty-two I/O
lines are organized into the 2-bit input port 0, the 4-bit
output port 2, and the 4-bit I/O ports 1, 4, 5, and 6. The
device executes 58 of the J.lPD7500 Set B instructions,
and has a 5-J.ls instruction cycle time. The subroutine
stack is implemented in RAM for greater nesting depth
and flexibility.
28-Pin Plastic DIPs
Vss
P42
P41
P03/Xl
P40
POo/INTO
P21/PTOUT
P53
P22
P52
Due to the CMOS process, the device has a maximum
power consumption of 600J.lA at 5 V, and this is further
reduced in halt and stop modes.
P51
P50
P63
Features
D 1024 x 8-bit program ROM
64 x 4,.bit data RAM
D 8-bit timer/event counter
o Two 4-bit general-purpose registers
o Two testable interrupts
D 5-l1s instruction cycle/400 kHz external clock
o 600 pA max current consumption
D 2 standby modes
0221/0 lines
P13
P62
CL1
Pl1
Cl2
Plo
Voo
83-003461 A
o
52-Pin Plastic Mlnlflat
52 51 50 49 48 47 46 45 44 43 42 41 40
Ordering Information
Part No.
Package Type
NC
39
NC
Max Frequency
of Operation
Cll
NC
NC
0
NC
37
NC
36
X2
pPD7506C
28-pin plastic DIP
410 kHz
Cl2
35
NC
pPD7506CT
28-pin plastic shrink DIP
410 kHz
NC
34
P43
pPD7506G-00
52-pin plastic miniflat
410 kHz
Voo
/lPD7506
RESET
33
Voo
32
NC
31
Vss
Pl1
10
30
P42
P12
11
29
P41
NC
12
28
NC
NC
13
27
NC
Pl0
14 15 16 17 18 19 20 21 22 23 24 25 26
CJ
z
CJ
z
CO>
:if
Ii: A.
:f lzl
CJ
Z
~
CO>
~
f lzl
CJ
Z
83-003462A
3-75
NEe
J.tPD7506
Pin Functions
Pi n Identification
POo/INTO, P03/X1 [Port 0]
28-Pln Plastic DIPs
No.
Symbol
Function
4-bit 110 port 4
2-bit input port O. Line POo is shared with external
interrupt INTO. Line P03 is shared with crystal clockl
external event input X1. Ground any unused pins.
1, 25-27
P43-P40
2
X2
External event input
3
P03/X1
Input port O/Clock input
P1o-P13 [Port 1]
4
P2o/PSTB
Output port 2/0utput strobe
5
P21/PTOUT
Output port 2lTimer out F/F signal
6-7
P22-P23
Output port 2
4-bit input port or three-state output port. Output is
strobed in synchronization with the PSTB pulse. Connect unused pins to Vss or Voo.
8-11
P6o-P63
4-bit I/O port 6
12, 13
CL1, CL2
System clock input
14
VDD
Positive power supply
15
RESET
RESET input
16-19
P1o-P14
4-bit I/O port 1
20-23
P50-P53
4-bit I/O port 5
24
POOIINTO
Input port O/Externallnterrupt
28
VSS
Ground
52-Pin Plastic Miniflat
P20/PSTB, P21/PTOUT, P22, P23 [Port 2, Strobe,
Timer F/F Output]
4-bit latched, three-state output port. Line P20 is
shared with the port 1 output strobe pulse PSTB. Line
P21 is shared with the timer out flip flop signal PTOUT.
Leave unused pins open.
P43-P40 [Port 4]
4-bit input or latched three-state output port. Can
perform 8-bit parallel 1/0 in conjunction with port 5. In
input mode, connect unused pins to Voo or Vss. In
output mode, leave unused pins open.
No.
Symbol
3, 5
CL1, CL2
System clock input
7, 33
VDD
Positive power supply
8
RESET
RESET input
9-11, 16
P1o-P14
4-bit I/O port 1
16-18, 21
P50-P53
4-bit I/O port 5
23
POo/INTO
Input port O/External interrupt
24, 29, 30,
34
P4o-P43
4-bit I/O port 4
31
VSS
Ground
36
X2
External event input
41
P03/X1
Input port O/Clock input
42
P2o/PSTB
Output port 2/0utput strobe
43
P21/PTOUT
Output port 2lTimer out F/F signal
CL 1, CL2 [System Clock Input]
44, 45
P22-P23
Output port 2
47-50
P6o-P63
4-bit I/O port 6
1, 2, 4, 6,
12-15,19,
20,25-28,
32,35,37-40,
46, 51, 52
NC
No connection
Connect a 120-kO resistor across CL 1 and CL2, and a
33-pF capacitor from CL 1 to Vss. Or, connect an
external clock source to CL 1 and leave CL2 open.
Function
P53-P50 [Port 5]
4-bit input or latched three-state output port. Can
perform 8-bit parallel 1/0 in conjunction with port 4.ln
input mode, connect unused pins to Vss or Voo. In
output mode, leave unused pins open.
P63-P60 [Port 6]
4-bit input or latched three-state output port. The port
6 mode select register (MSR) configures individual
lines as inputs or outputs. In input mode, connect
unused pins to Vss or Voo. In output mode, leave
unused pins open.
X2, X1 [Crystal Clock/External Event Input]
For crystal clock operation, connect a crystal oscillator
circuit to input X1 and output X2. For external event
counting, connect external event pulses to input X1
and leave X2 open. If X1 is not used, connect it to Vss. If
X2 is not used, leave it open.
RESET
A high level input to this pin initializes the pPD7506.
3-76
t-IEC
J..tPD7506
Voo
Positive power supply. For proper operation, apply a
single voltage from 2.7 to 6.0 V.
Vss
Ground.
Block Diagram
P03/X1
POO/INTO
X2
Program Memory
1024 x 8 Bits
Instruction
Decoder
Data Memory
64 x 4 Bits
System
Clock
Generator
CL1
CL2
Standby
Control
t
Voo
t
VSS
t
RESET
83-003463C
3-77
NEe
J.tPD7506
Clock Control Circuit
Table 1.
This circuit consists of a 4-bit clock mode register
(CMR), prescalers 1 and 2, and a multiplexer, as shown
in figure 1. The circuit selects the clock source, accepts
output from the system clock oscillator (CL) and count
clock generator circuit (X), divides the signal according
to the setting in the CMR, and outputs the count pulse
(CP) to the timer/event counter.
The OP or OPL instruction sets the CMR as defined by
table 1. Before loading the CMR, it is necessary to clear
bit 2 of the accumulator (A2) to zero.
Selecting the Count Pulse Frequency
o
o
CMo
Frequency Selected
o
CLl256
X/64
x
o
x
CM3
TOUT Signal
o
Disabled
Enabled
Figure 1.
Clock Control Circuit
Internal Bus
Clock Mode Register
Prescaler 2
(1/64)
)--------------
~~mer/Event Counter)
x
Crystal Clock Oscillator/
Event Counter Input
83-0039228
3-78
NEe
JAPD7506
Timer/Event Counter
The timer/event counter consists of an 8-bit count
register, an 8-bit modulo register, an 8-bit comparator,
and a timer out flip flop, as shown in figure 2.
The count register is a binary up-counter that increments each time a count pulse is input. The TIMER
instruction, a RESET signal, or an INTT coincidence
signal clears it to OOH. When an overflow occurs the
counter is reset from FFH to OOH.
'
Figure 2.
The modulo register determines the number in the
count register. The TAMMOD instruction sets the
contents of the modulo register. On reset, its contents
are FFH.
The comparator compares the contents of the count
register and the modulo register; when equal, the
comparator outputs INTT.
Timer/Event Counter
TAMMOD
Instruction Execution
'--_____
IE
....
~-----J-
- - - - - I N T T [Coincidence]
Counter Pulse
[from Clock Control Circuit]
TIMER
Instruction
Execution or
RESET Pulse _ _ _ _ _ _ _ _ _ _ _----.J
PTOUT
[to P21/PTOUT Pin]
83-0034648
3-79
NEe
~PD7506
Interrupts
Table 2.
ThepPD7506 has two interrupts, INTT and INTO.INTT
is internally generated by the timer/event counter.
INTO is externally generated. See figure 3.
Mode
CL
160 kCl
(J
500
'-
1--'
-
u
S!
,..
.
u
c
:>
~
0
~
100
~
r
til
R=240kO-
, "'-
50
fCC vs R
fX vs VOO
'
25 o
~
1I
til
20
50
400 -
,..u
..
voo=~
"
100 -
I
;:-...
..............
0
'"
100 -
0
1
500
o
100 vs VOO
1000
g
~
i
.,~
C-
.::!.
c
Voo = 3V,
R = 160 kCl
50
C
~
,..
__ ------ ----- _.
-------------------
C = 33 pF
I1CI'C '-:;60 ppm
10
(J
~
-- ------ ------ -----
STOP [Xl = 0 V)
Ul
'"
~
R = 240 kCl
0.5
1?
O~---------L--------~~--------~--------~~
-25
---k~4;;~~;;:::~~~:~i f~:~ :gj
100
E
50 1 - - - - - - - - - + - - ' - - - - - 1 " - - - - - - - - 1 - -'voo = 2.5 V, -
til
[82kO)
-+---+----=:::;;ot[160 kCl)
[240 kCl)
__
_ _--,HALT [82 kO)
500
CL2
J
Defined
Operaling Vollage
Supply Voltage Voo [V)
~Ll
C
~
~
~
200
R
C
..!...
r'
§
100
--------1----------__ ------1------ -----
~
212
(J
Voo= 5 V,
R = 82 kCl
5=
,,!_
10
fCC vs TA
150
11> 12: fx =
"'u0"
Voo=2.5V~
250r----------r--------~----------,_--------~
~
[TA = 25'C)
~
211
Resislance R [kCl)
(
I
11 <12:fX=
"
~
I:
12
-11-1
X1SLJL
C
r-..
I I
E
I
11
N
-
i
20
1000
l cl-
~
.......
R
0
o
Supply Voltage Voo [V)
[TA
=~
J
= 3 3 PF
0
"'u0"
"-
200
12:fC= ~
212
E
- .-
til
..
100 I-
[TA = 25°C)
I
_lll~
.!!
___ -I-'
E
i
u
R = 82 kCl
---- 1-'---- R
-
S!
,..
I
CL1SLJL
~
R
.- -
100
i
[TA=25°C)-
I
S!
,..
1000
25
Operaling Temperalure TA [0C]
50
75
0.1
0
Supply Vollage Voo [V]
3-87
NEe
JJPD7506
Operating Characteristics (cont)
1001 vs
fcc
IOH vs VOH
-6
500
Cl
.:;
Q
E
~
0
~
'"..
;( -5
~
I
400
300
33pF
I:
E.
:I:
E
~
CJ
R
..
"a.
a.
0
"
200
-3
__. l - - - - - - ! Voo = 3 V
0
I:
~
CJ
t
-4
I:
100
I
Ul
I
i
-2
-1
~
0
0
50
100
150
250
200
300
High-Level Output Voltage VOH [V]
System Clock Oscillation Frequency ICC [kHz]
IOL vs VOL
1001 vs TA
20
500
;(
.:;
C
E
.
400
."
0
~
'"
300 t----
I:
l'!!
~
0
200 t----
I:
~
;(
-
------
t---
~
I
33pF
E.
..J
E
I:
~
Voo = 5 V, R = 82 kO
R
~"
0
a;
CJ
>- 100
~
I
Voo = 3 V, R = 160 kG
Ul
I
o
-25
25
Operating Temperature TA ['C]
3-88
50
_ _- - - , Voo
CJ
'"
__--1--- Voo = 2.5 V
~
~
.3
is
~
75
Low-Level Output Voltage VOL [V]
=3 V
NEe
NEe Electronics Inc.
pPD7507/08
4-BIT, SINGLE-CHIP
CMOS MICROCOMPUTERS
Description
Features
The JlPD7507 and JlPD7508 4-bit, single-chip CMOS
microcomputers have theJlPD7500 series architecture.
The subroutine stack is implemented in RAM for
greater nesting depth and flexibility.
o
o
Thirty-two I/O lines are organized into eight 4-bit
ports: input port/serial interface port 0, output ports 2
and 3, and I/O ports 1,4, 5, 6, and 7.
The JlPD7507 and JlPD7508 execute 92 instructions of
the JlPD7500 series A instruction set with a 5-Jls
instruction cycle time.
Maximum power consumption is 900 JlA at 5 V, less in
the HALT and STOP low-power modes.
The JlPD75CG08 is a piggyback EPROM prototyping
ch ip that is pi n-compatible with JlPD7507 and JlPD7508.
A 2716 inserted into the top of the JlPD75CG08 emulates
the JlPD750Ts ROM. A 2732 emulates the JlPD7508's
ROM. When emulating the JlPD7507, the user must
take care to use only the first 128 RAM locations.
Although the JlPD7507 and JlPD7508 can operate over
a range of 2.5 to 5.5 V, JlPD75CG08 operation is limited
to 5 V ±10%.
Single chip microcomputer
Program ROM
- JlPD7507: 2048 x 8-bit
- JlPD7508: 4096 x 8-bit
- JlPD75CG08: piggyback EPROM
o Data RAM
- JlPD7507: 128 x 4-bit
- JlPD7508: 224 x 4-bit
- JlPD75CG08: 224 x 4-bit
D 8-bit timer/event counter
o Four 4-bit general purpose registers
o Four vectored, prioritized interrupts
o Executes 92 instructions of pPD7500 series A
instruction set
o 5 JlS instruction cycle/400 kHz external clock
o Two standby modes
o 32 I/O lines
o Low-power HALT and STOP modes
Ordering Information
*Part Number
Package Type
Max Frequency
of Operation
pPD7507C
40-pin plastic DIP
410 kHz
Table 1 summarizes the differences among JlPD7507,
JlPD7508 and JlPD75CG08.
pPD7507CU
40-pin plastic shrink DIP
410 kHz
pPD7507G-00
52-pin plastic miniflat
410 kHz
Table 1.
pPD7508C
40-pin plastic DIP
410 kHz
pPD7508CU
40-pin plastic shrink DIP
410 kHz
pPD7508G-00
52-pin plastic miniflat
410 kHz
pPD75CG08E
40-pin ceramic piggyback DIP
410 kHz
Features Comparison
pPD75CGD8
Program memory
2K x 8 EPROM (2716)
4K x 8 EPROM (2732)
x4
pPD7507n508
x 8 masked ROM (7507)
x 8 masked ROM (7508)
128 x 4 (7507)
2K
4K
Data memory
224
Data retention
mode
No
Yes
Power supply
5 V ±10%
2.7 to 6.0 V
Package types
40-pin ceramic
piggyback DIP
40-pin plastic DIP
40-pin plastic shrink DIP
52-pin plastic miniflat
224 x 4 (7508)
* A 3-digit mask identification code is added to the part number by
NEC at the time of code verification.
3-89
NEe
J,tPD7507/08
Pin Configurations
40-Pln Plastic DIP and Plastic Shrink DIP
X2
52-Pin Plastic Miniflat
Xl
P20/PSTB
Vss
P2l/PTOUT
P 43
P22
P42
NC
P23
P4l
P73
Plo
P4 0
RESET
Pl l
P53
NC
P12
P52
Cll
P23
P22
P2l/PTOUT
P20/PSTB
NC
P13
P5l
NC
P30
P50
VDD
P3l
P63
NC
P32
P62
Cl2
Vss
P33
P6l
INn
P43
P70
P60
POo/INTO
NC
P7l
P03/S1
P01/SCK
P42
P7 2
P02/S0
NC
NC
P73
P01/SCK
RESET
POolINTO
Cll
INT1
VDD
Cl2
X2
VDD
Xl
83-003454A
Pin Identification
40-Pln Ceramic Piggyback DIP
X2
83-003455A
40-Pin DIP, Shrink DIP and Piggyback DIP
Xl
Vss
No.
P43
Function
1,40
X2, X1
Crystal clock/external event input port
P4l
2-5
P2o/PSTB,
P21/PTOUT,
P22, P23
Output port 2/output strobe pulse,
timer out F/F signal
P40
Pll
P53
P12
P52
P13
P5l
6-9
P1o-P13
I/O port 1
P30
P50
10-13
P30-P33
Output port 3
14-17
P7o-P73
I/O port 7
18
RESET
RESET input
System clock inputs
P3l
P63
P32
P62
P33
P6l
P70
P60
P7l
P03/S1
19,21
CL1, CL2
P72
P02/S0
P73
P01/SCK
20
Voo
Positive power supply
RESET
POoflNTO
22
INT1
External interrupt
Cll
INT1
VDD~________________~,
Cl2
23-26
POoIINTO,
P01/SCK,
P02/SQ,
P03/S1
Input port O/external interrupt, serial
I/O interface
83-003779A
3-90
Symbol
P42
27-30
P6o-P63
I/O port 6
31-34
P50-P53
I/O port 5
35-38
P43-P40
I/O port 4
39
Vss
Ground
NEe
f.,lPD7507/08
Pin Identification (cont)
Pin Functions
28-Pin EPROM Socket on Piggyback DIP
POo/INTO, P01/SCK, P02/S0, P03/S1 [Port 0/
External Interrupt, Serial Interface]
No.
Symbol
1,2
NC
Not connected
Function
3-10
ArAo
Address bits 7-0
11-13
10- 12
Data bits 0-2
14,22
VSS
Ground
15-19
13- 17
Data bits 3-7
20
CE
Chip Enable
21,23
A10- A11
Address bits 10, 11
24,25
Ag, As
Address bits 9, 8
26,28
VDD
Positive power supply
27
MSEL
Memory select
52-Pin Miniflat
No.
Symbol
1,4,6,13,
14,27,29,
35,40,45
NC
Not connected
2,50-52
P70-P73
110 port 7
Function
3
RESET
RESET input
5,9
CL 1, CL2
System clock inputs
7
VDD
Positive power supply
10
INT1
External interrupt
11,12,
15,16
POoIINTO,
P01/SCK,
P02/S0,
P03/S1
Input port Olexternal
interrupt, serial 110
interface
17-20
P60-P63
110 port 6
21-24
P50-P53
110 port 5
25,26
28,30
P43-P40
110 port 4
31
VSS
Ground
32,34
X1, X2
Crystal clock I external
event input
33
VDD
Positive power supply
36-39
P20/PSTB,
P21/PTOUT,
Ph P23
4-bit output port 2/0utput
strobe pulse, timer out
F/F signal
41-44
P10-P13
110 port 1
46-49
P30-P33
Output port 3
4-bit input port/serial I/O interface. This port can be
configured as a 4-bit parallel input port or as the 8-bit
serial I/O interface under control of the serial mode
select register. The serial input SI, serial output SO
(active low), and the serial clock SCK (active low), used
for synchronizing data transfer, make up the 8-bit
serial I/O interface. Line POQ is always shared with
external interrupt INTO, a rising edge-triggered interrupt. If POQ/INTO is unused, it should be connected to
Vss. If P01/SCK, P02/S0, or P03/S1 are unused, connect
them to Vss or Voo.
P10-P13 [Port 1]
4-bit input/three-state output port. Data output to port 1
is strobed in synchronization with a P2Q/PSTB pulse.
Connect unused pins to Vss or Voo.
P20/PSTB, P21/PTOUT, P22, P23 [Port 2]
4-bit latched three-state output port. Line P2Q is shared
with PSTB, the port 1 output strobe pulse. Line P21 is
shared with PTOUT, the timer out F/F signal. Leave
unused pins open.
P30-P33 [Port 3]
4-bit latched three-state output port. Leave unused pins
open.
P40-P43 [Port 4]
4-bit latched three-state output port. Can also perform
8-bit parallel I/O with port 5. In input mode, connect
unused pins to Voo or GND. In output mode, leave
unused pins open.
P53-P50 [Port 5]
4-bit input/latched three-state output port. This port
also performs 8-bit parallel I/O with port 4. In input
mode, connect unused pins to Vss or VDD. In output
mode, leave unused pins open.
P63-P60 [Port 6]
4-bit input/latched three-state output port. The port 6
mode select register configures individual lines as
inputs or outputs. In input mode, connect unused pins
to Vss orVoo.ln output mode, leave unused pins open.
3-91
NEe
JlPD7507/08
P70·P73 [Port 7]
RESET [Reset]
4-bit input/latched three state output port. In input
mode, connect unused pins to Vss or Voo. In output
mode, leave unused pins open.
A high level input to this pin initializes the pPD7507 /08
after power up.
.
INT1 [Interrupt 1]
X2, X1 [Crystal Clock/External Event Input]
For crystal clock operation, connect a crystal oscillator
circuit to input X1 and output X2. For external event
counting, input external event pulses to input X1 while
leaving output X2 open. If X1 is not used, leave it open.
If X2 is not used, connect it to ground.
CL 1, CL2 [System Clock Input]
External rising edge-triggered interrupt. Connect to
Vss if unused.
Voo [Power Supply]
Positive power supply. Apply a single voltage in the
range 2.7 to 6.0 V for proper operation.
Vss [Ground]
Connect a 120 kO resistor across CL 1 and CL2, and
connect a 33 pF capacitor from CL 1 to Vss. Alternatively, connect an external clock source to CL 1 and
leave CL2 open. If CL 1 is unused, connect it to Vss.
Ground.
Block Diagram
General Registers
Program Memory
2048 x 8-Bit ROM [pPD7507]
4096 x 8-Bit ROM [pPD7508]
CL
CL1
Instruction
Decoder
0[4]
E [4]
H [4J
L [4J
Stack Pointer [8J
Data Memory
128 x 4-Bit ROM [pPD7507]
224 x 4-Bit ROM [pPD7508]
¢
CL2
III
RESET
Voo
Vss
83-003470C
3-92
t-lEC
JlPD7507/08
Memory Map
Clock Control Circuit
Figure 1 shows the ROM memory map of the
The clock control circuit consists of a 4-bit clock mode
register (bits CM1 and CM2), prescalers 1,2, and 3, and
a multiplexer. It takes the output of the system clock
generator (Cl) and count clock generator circuit (I). It
also selects the clock source and divides the signal
according to the setting in the clock mode register. It
outputs the count pulse (CP) to the timer/event counter.
Figure 2 shows the clock control circuit.
pPD7507/08.
Figure 1.
ROM Map
Address
[Decimal]
MSB
0
to.
Address
[Hex]
LSB
716151413121110
OOOH
16
010H
32
020H
48
030H
C>
~
Q
a.
::..
a.
:E
~
RESET Pulse Vector. Program
Execution to Address OOH
INTT [Internal Timer/Event
Counter Interrupt] Vectors
Execution to 010H
INTO/S [External Interrupt 0/
Serial Interface Interrupt]
Vectors Execution to 020H
INT1 [External Interrupt 1]
Vectors Execution to 030H
I!!
Q
a.
::..
a.
:E
~
0
Table 2 lists the codes set in the clock mode register by
the OP or OPl instruction to specify the count pulse
frequency. Be sure to clear the high-order bits of the
accumulator (A3, A2) to zero before loading the clock
mode register.
Table 2.
192
OCOH} LHLT Instruction
Reference Table
OCFH
207
208
ODOH} CALT Instruction
OFFH
Reference Table
0
255
1023
1024
3FFH
400H
<-2047
2048
7FFH
800H
Last address for
CALL Instruction
entry for pPD7507
L--4095
FFFH
Last address for
CALL Instruction
entry for pP 07508
Selecting the Count Pulse Frequency
CM2
CM!
o
0
o
o
o
0
o
o
CMo
Frequency Selected
0
CLl256
o
x
x
o
CLl32
o
Not used
X/64
X/8
Not used
83-003456A
CM3
TOUT Signal
o
Disabled
Enabled
Figure 2.
Clock Control Circuit
XI
>-------------------------_.CP
(Timer/Event Counter)
Crystal Clock Oscillator/
Event Counter Input
83-003457B
3-93
ttiEC
J.1PD7507/08
Timer/Event Counter
The timer/event counter consists of an 8-bit counter,
an 8-bit modulo register, an 8-bit comparator, and a
timer out flip-flop as shown in figure 3.
The 8-bit count register is a binary 8-bit up-counter
which is incremented each time a count pulse is input.
The TIMER instruction, a RESET signal, or an INTT
coincidence signal clears it to OOH.
The 8-bit modulo register determines the number of
counts the count register holds. The TAMMOD instruction loads the contents of the modulo register.
RESET sets the, modulo register to FFH.
The 8-bit comparator compares the contents of the
count register and the modulo register and outputs an
I NTT when they are equal.
Figure 3.
Timer/Event Counter
Internal Bus
~--~--------------~
r--------------------J
~CN~M--------------------------~
1---------..
INTT
[Coincidence]
CP------------------------------~
I---t--t---l~u;erial Interface)
'Command Execution
Clock
MSR
~imer
RESET
Bit·3
PTOUT
[to P21/
PTOUTpin]
Pulse
83-003458B
3-94
NEe
JlPD7507/08
Serial Interface
The 8-bit serial interface allows the pPD7507/08 to
communicate with peripheral devices such as the
pPD7001 A/D converter, the pPD7227 dot matrix LCD
controller/driver, and other microprocessors or microcomputers. Figure 4 shows the serial interface.
The serial interface consists of an 8-bit shift register, a
3-bit SCK pulse counter, the SI input port, the SO
output port, the SCK serial clock I/O port, and a 4-bit
serial mode select register (MSR). The MSR selects
serial I/O or port 0 operation.
Figure 4.
Serial Interface
P03lS1 0 - - - - - - - - - - - 1
P02/S0
Il
~>---_++'H_-H
o - - - -........-----+-~~ 1--_ _ _ _ _ _ _-+-________--1
_.J>--+-- TOUT
POO/INTO 0 - - - - - - - - - 1
RS F/F
I+-----<~-_ INTS
(To Interrupt CircuIt)
• Command Execution
¢ System Clock
1 - - - - - - ·SIO
83-0030146
t-IEC
JlPD7507108
Interrupts
The tJPD7507/08 has four vectored, prioritized interrupts. Two of these interrupts, INTT and INTS, are
internally generated from the timer/event counter and
serial interface, respectively. INTO and INT1 are
externally generated. Table 3 is a summary of the four
interrupts. Figure 5 is the block diagram.
Table 3.
tJPD750710Blnterrupts
Location
Priority
INTT
Source
Coincidence in timer/event counter
Internal
1
10H
INTS
Transfer complete signal from serial interface
Internal
2
20H
INTO
INTO pin
External
2
20H
INT1
INT1 pin
External
3
30H
Figure 5.
Function
ROM Vector Address
Interrupt Block Diagram
INTT--------+---------4--4-+=~-fS'Ii;n:-,Hr_t~--_t__t___t
INTS---------+---r
ROM
INTO---------+--I
SIO·-----------f
INT1----------------~----~'Ii~_,
~~~------~~
Timer· _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
·Command Execution
>----_ Standby Release
83-003459B
NEe
J.lPD7507/08
System Clock and Timing Circuitry
Figure 6.
RC Circuit Connection
Timing for the pPD7507/08 is internally generated
except for a frequency reference, which can be an RC
circuit or an external clock source. Connect the
frequency reference to the on-Chip oscillator for the
feedback phase shift required for oscillation. Figure 6
shows the connection for an RC circuit. Figure 7 shows
the connection for an external clock source.
-CL2
83-002994A
The internal oscillator generates a frequency in the
range 60 kHz to 300 kHz depending on the frequency
reference. For example, at Voo = 5 V, an 83-kO resistor
and a 33-pF capacitor generate a frequency of 200 kHz.
The oscillation frequency is fed to the clock control
circuit. It is divided by two and the resulting signal is
fed to the CPU and serial interface as shown in figure 8.
Figure 7.
External Clock Source Connection
L
External
Source
CL2
Table 4 shows the operating status of the various logic
blocks under the three power down-modes.
Figure 8.
L1
System Clock Circuitry
83-002995A
X1
X2
INTT
CL1
INTS
Syslem Clock
Oscillator
CL2
'------+--------------0 STOP
~---<>
\-----<>
~:~~~~:~~n
Siandby Release
Reset
83-0034606
3-97
NEe
JlPD7507/08
Table 4.
Power-Down Operating Status
Power-Down Mode
logic Block
HALT
STOP
Data Retention Mode
System clock
(Note 1)
Disabled
Disabled
X2
Normal
Normal
Disabled
CPU
Disabled
Disabled
Disabled
RAM
Data retained
Data retained
Data retained
Internal registers
Data retained
Data retained
Data retained
Timer I event counter
Normal
(Note 3)
Disabled
Serial interface
(Note 2)
(Note 2)
Disabled
INTO
Normal
Normal
Disabled
INT1
Normal
Disabled
Disabled
RESET
Normal
Normal
(Note 4)
Note:
(1) Supplied to timer/event counter but not to CPU or serial interface.
(2) Can function normally if the serial MSR is set to get the SCK signal externally or from the TOUT signal.
(3) Can function normally if the clock MSR is set to use X1 as the source for the count pulse.
(4) To enter the data retention mode, raise RESET while Voo is lowered. To end the data retention mode, raise RESET when Voo is raised, then
lower it. INTT, INTO, INTS or RESET releases the STOP mode. RESET or any interrupt releases the HALT mode.
3-98
NEe
JlPD7507/08
I/O Port Interfaces
Figure 9 shows the internal circuit configurations at the
I/O ports.
Figure 9.
Interface at Input/Output Ports
Type E
Type A
P02/S0, P40-P43, PSO-PS3, P60-P63, P10·P13, P70-P73
Voo
Voo
P·ch
oatalb:
~"'"
Inputl
Output
Output
Disable
.
Vss
Voo
Vss
Type B
POo/INTO, P03/SI, RESET, INT1
Vss
Type F
Type 0
P01/SCK
P30-P33, P20/PSTB, P21/PTOUT, P22-P23
Voo
Voo
P·ch
P·ch
oatalb:
oatalb:
Inpull
Output
Output
Output
Output
Disable
Disable
Vss
Vss
83·003860C
3-99
NEe
f.1PD7507108
Absolute ,Maximum Ratings
TA
Capacitance
=25°C
TA
= 25°C, Voo =,0 V
Operating temperature, TOPT
limits
Storage temperature, TSTG
-65 to +150°C
-0.3 to +7.0 V
Power supply voltage, VOO
All input and output voltages
-0.3 to Voo + 0.3 V
Output current high, IOH
One pin
All pins, total
-17 rnA
-30 rnA
Output current low, IOL
One pin
Ports 1,2,3,7
Ports 4, 5, 6
Parameter
Symbol
Typ
Max
Unit
Input capacitance
CI
15
Output capacitance
Co
15
pF
1/0 capacitance
CIO
15
pF
Test
Conditions
pF f= 1 MHz;
unmeasured pins
returned to Vss
17 rnA
25 rnA
25 rnA
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
For Voo
TA
= 2.5 to 3.3 V (7507, 7508 only)
=-10 to +70°C
Limits
Parameter
Input voltage, high
Symbol
Min
Typ
Max
Unit
Test
Conditions
VIH1
O.B VOO
VOO
V
Except CL 1, X1
VIH2
VOO - 0.3
Voo
V
CL1, X1
VIHoR
RESET, data retention mode
0.9VOOOR
VOoOR + 0.2
V
VIL1
0
0.2 VOO
V
Except CL 1, X1
VIL2
0
0.3
V
CL1, X1
Output voltage, high
VOH
Voo - 0.5
V
IOH = -BOpA
Output voltage, low
VOL
0.5
V
IOL = 350pA
Input voltage, low
Input leakage current, high
Input leakage current, low
Output leakage current, high
IUH1
3
pA
VUH2
10
pA
CL1, X1
IUL1
-3
JlA
Except CL1, X1; VI = 0 V
VUL2
-10
pA
CL1, X1
ILOH
3
JlA
Vo = Voo
-3
JlA
Vo =OV
Output leakage current, low
ILOL
Supply voltage
VOoOR
Supply current
1001
1002
1000R
3-100
2.0
V
Except CL1, X1; VI = Voo
Data retention mode
50
250
pA
Normal operation, VOO = 3 V ±10%;
R = 240 kQ ±2%, C= 33 pF ±5%
35
230
pA
Normal operation, Voo = 2.5 V;
R = 240 kQ ±2%, C = 33 pF ±5%
0.3
10
JlA
Stop mode, X1 = 0 V; Voo = 3 V ±10%
0.2
10
pA
Stop mode, X1 = 0 V; VOO = 2.5 V
0.2
10
pA
Data retention mode, VOoOR = 2.0 V
NEe
fJPD7507/08
DC Characteristics {cont}
For VDD = 2.7 to 6.0 V (75CG08. 5 V ±10%)
TA = -10 to +70°C
limits
Parameter
Symbol
Input voltage, high
V,H1
Input voltage, low
Output voltage, high
Output voltage, low
Input current, high
Min
Typ
0.7 VDD
Unit
VDD
V
Except CL 1, X1
CL1, X1
V,H2
VDD - 0.5
VDD
V
V,HDR
0.9VDDDR
VDDDR + 0.2
V
RESET, data retention mode
0
0.3 VDD
V
Except CL 1, X1
V,L2
0
0.5
V
CL 1, X1
VOH
VDD -1.0
V
10H = -1.0 mA; VDD = 4.5 to 6.0 V, 7507/08 only
V,L1
VDD - 0.5
V
10H = -100 fJA, 7507/08 only
VOH1
VDD -1.0
V
10H = -1.0 mA, 75CG08 only
VOH2
VDD - 0.75
V
10H = -5.0 mA, 75CG08 only
0.4
V
10L = 1.6 mA; VDD = 4.5 to 6.0 V, 7507/08 only
0.5
V
IOL = 400 fJA, 7507/08 only
0.4
V
10L = 1.6 mA, 75CG08 only
300
fJA
fJA
fJA
fJA
fJA
fJA
fJA
fJA
VOL
Input current, low
I'H
I,L
Input leakage current, high
IUH1
3
IUH2
10
Input leakage current, low
Test
Conditions
Max
-200
IUL1
-3
IUL2
-10
Output leakage current, high
'LOH
3
Output leakage current, low
ILOL
-3
Supply voltage
VDDDR
Supply current
IDD1
'D02
'DDDR
2.0
75CG08 only, V, = VDD, MSEL
75CG08 only, V, = 0 V, 10-17
Except CL1, X1; V, = VDD
CL1, X1
Except CL1, X1; V, = 0 V
CL1, X1
Vo = VDD
Vo=OV
V
Data retention mode, 7507/08 only
300
900
fJA
Normal operation, VDD = 5 V ±10%;
R= 82 kO ±2%, C = 33 pF ±5%
70
300
fJA
Normal operation, VDD = 3 V ±10%;
R = 160 ko ±2%, C= 33 pF ±5%, 7507/08 only
fJA
fJA
fJA
fJA
1.0
20
0.3
10
2
20
0.2
10
Stop mode, X1 = 0 V; VDD = 5 V ±10%
Stop mode, X1 = 0 V; VDD = 3 V ±10%, 7507/08 only
Stop mode, X1 = 0 V; VDD = 5 V ±10%, 75CG08 only
Data retention mode VDDDR = 2.0 V, 7507/08 only
NEe
f..lPD7507108
AC Characteristics
For Voo
= 2.7 to 6.0 V (75CGOB,
5 V ±10%)
TA = -10 to +70°C
Limits
Test
Conditions
Parameter
Symbol
Min
Typ
Max
System clock frequency
fcc
150
200
240
kHz
Voo
75
100
120
kHz
Voo = 3.0 ±10%; R = 160 kn ±2% (Note 1), 7507/08 only
75
135
kHz
VOO
10
410
kHz
CL 1, external clock, 50% duty;
Voo = 4.5 to 6.0 V, 7507/08 only, Voo = 5 V ±5%, 75CG08 only
10
125
kHz
CL 1, external clock, 50% duty; Voo = 2.7 V, 7507/08 only
10
300
kHz
CL 1, external clock, 50% duty; 75CG08 only
0.2
JiS
CL 1, external clock
CL 1, external clock; Voo = 4.5 to 6.0 V, 7507/08 only
fc
System clock rise and fall
times
tCR, tCF
System clock pulse width
tCH, tCl
Counter clock frequency
fxx
tXR, tXF
Counter clock pulse width
tXH, tXl
SCK cycle time
SCK pulse width
tKCY
tKH, tKl
= 3.0 ±10%; R= 160 kn ±2% (Note 1), 7507/08 only
1.2
50
JiS
50
JiS
CL 1, external clock; Voo = 2.7 V, 7507/08 only
1.5
50
JiS
CL 1, external clock, 75CG08 only
1.2
50
JiS
CL 1, external clock; Voo
50
kHz
X1, X2, crystal oscillator
410
kHz
X1, external pulse input; 50% duty;
Voo = 4.5 to 6.0 V, 7507/08 only
0
125
kHz
X1, external pulse input, 50% duty;
VOO = 2.7 V, 7507/08 only
0
300
kHz
X1, external pulse input; 50% duty, 75CG08 only
410
kHz
X1, external pulse input; 50% duty;
Voo = 5 V, 75CG08 only
0.2
JiS
X1, external pulse input
X1, external pulse input; Voo = 4.5 to 6.0 V, 7507/08 only
25
32
= 5 V ±5%, 75CG08 only
1.2
JiS
4.0
JiS
X1, external pulse input; Voo = 2.7 V, 7507/08 only
1.5
JiS
X1, external pulse input, 75CG08 only
1.2
JiS
X1, external pulse input; Voo = 5 V ±5%, 75CG08 only
3.0
JiS
SCK as input; Voo = 4.5 to 6.0 V, 7507/08 only
5 V ±5%, 75CG08 only
8.0
JiS
SCK as input, 7507/08 only
4.9
JiS
SCK as output; Voo = 4.5 to 6.0 V, 7507/08 only
5V ±5%, 75CG08 only
16.0
JiS
SCK as output, 7507/08 only
4.0
JiS
SCK as input, 75CG08 only
6.7
JiS
SCK as output, 75CG08 only
1.3
JiS
SCK as input; Voo = 4.5 to 6.0 V, 7507/08 only
5V ±5%, 75CG08 only
4.0
JiS
SCK as input
Note:
(1) RC network at CL 1 and CL2; C = 33 pF ±5%,It..c/ocl::; 60 ppm.
~-102
= 5.0 V ±10%; R= 82 kn ±2% (Note 1)
4.0
fx
Counter clock rise and fall
times
Unit
NEe
JJ,PD7507/08
AC Characteristics (cont)
For VDD = 2.7 to 6.0 V (75CG08, 5 V ±10%)
TA = -10 to +70°C
limits
Parameter
Symbol
SCK pulse width
SI setup time to SCK
t
SI hold time after SCK
tSIK
t
Min
Typ
Max
2.2
/.IS
SCK as output, Voo = 4.5 to 6.0 V, 7507 lOB only
5 V ±10% 75CGOB only
B.O
/.IS
SCK as output, 7507 lOB only
3.0
/.IS
SCK as output, 75CGOB only
300
ns
450
SO delay time after SCK ~
ns
850
1200
Port 1 output setup time to PSTB
t
tpST
Port 1 output setup time to PSTB
t
tSTP
Test
Conditions
Unit
ns
Voo = 4.5 to 6.0 V, 7507 lOB only
5 V ±10% 75CGOB only
ns
7507 lOB only
1I (2fcC - BOO)
ns
Voo = 4.5 to 6.0 V, 7507 lOB only
5 V ±10% 75CGOB only
1I (2fCC - 2.0)
ns
7507 lOB only
100
ns
Voo = 4.5 to 6.0 V, 7507/0B only
5 V ±10% 75CGOB only
100
ns
7507 lOB only
1I (2fcC - BOO)
ns
Voo = 4.5 to 6.0 V, 7507 lOB only
5 V ±10% 75CGOB only
7507 lOB only
PSTB pulse width
tSTL
1I (2fcc - 2.0)
ns
INTO pulse width
tlOH, tlOL
10
/.IS
INn pulse width
t11H, tl1L
2/fcc
/.IS
RESET pulse width
tRSH, tRSL
10
/.IS
RESET setup time
tSRS
0
ns
RESET hold time
tHRS
0
ns
II
3-103
t-{EC
~PD7507/08
AC Characteristics (cont)
For VDD = 2.5 to 3.3 V (7507, 7508 only)
TA == -10 to +70°C
Limits
Parameter
Symbol
Min
System clock frequency
fcc
50
50
fc
System clock rise and fall
time
Max
80
kHz
R = 240 kn ±2% (Note 1)
64
77
kHz
VDD = 2.5 V; R = 240 kn ±2% (Note 1)
80
kHz
CL 1, external clock, 50% duty
0.2
/1S
CL 1, external clock
50
/1S
CL 1, external clock
50
kHz
X1, X2, crystal oscillator
80
kHz
X1, external pulse input, 50% duty
0.2
/1S
X1, external pulse input
10
tCR, tCF
System clock pulse width
tCH, tCl
Counter clock frequency
fxx
25
fx
0
Counter clock rise and fall
time
6.25
tXR, tXF
Test
Conditions
Typ
32
Unit
Counter clock pulse width
tm tXl
6.25
/1S
X1, external pulse input
SCK cycle time
tKCY
12.5
/1S
SCK as input
25.0
/1s
SCK as output
6.25
/1s
SCK as input
11.5
/1S
SCK as output
SCK pulse width
SI setup time to SCK
tKH, tKl
t
SI hold time after SCK
tSIK
t
Port 1 output setup time to PSTB
/1s
tKSI
SO delay time after SCK ~
2
tKSO
t
Port 1 output hold time after PSTB
PSTB pulse width
/1s
t
/1S
tpST
1/(2fcc - 2.0)
ns
tSTP
100
ns
tSTl
1/(2fcC - 2.0)
ns
/1s
INTO pulse width
tIOH, tlOl
30
INT1 pulse width
tl1H, tl1l
2IfCC
/1s
RESET pulse width
tRSH, tRSl
30
/1s
RESET setup time
tSRS
0
ns
RESET hold time
tHRS
Note:
(1) RC network at CL 1 and CL2; C = 33 pF ±5%,lllC/ocl::::: 60 ppm.
~-104
ns
NEe
J,tPD7507/08
Timing Waveforms
External Interrupts
Timing Measurement Points
Voo
==X
0.7VDD
~O~.3~V~D~D
Oo7VDDX=
Test Points
_________________O~o3~V~D~D
Voo
==X
0.aVDD
~O~.2~V~D~D
= 2.7 to 6.0 V
'Hm ~"O'J="O"~
'"T<~'"'J="'"~
= 2.5 to 2.7 V
o.aVDDX=
Test Points
_________________
O~.2~VD~D
83-003314A
83-003317A
RESET
Clocks
83-003318A
CL1
Data Retention Mode
Data Retention Mode
X1
VDD
VDDDR
RESET
Serial Interface
SI
83-003319A
--i-------{
so
Valid Output Data
>C
'-------
83-003316A
Output Strobe
83-003414A
3-105
NEe
J,1PD7507108
Operating Characteristics
TA =25°C
fcC vs R
fccvs Voo
500 ,----r----.I-,---I~--r..,,-----r---,Ic---Jr---1
500
~
400
(,)
i!
!
250 I---200 I----
c
0
:;
150 I----
j
100
~
33pF
J;
~
1-----=-~---I--
__ - - f-
~
:;
2
1-----t-,
--- -
50
[
R=82kCl
~
~----
R
-- -------
U
1 - - - + - -+----11----+-+-I-I--+---+-[TA = 25°C]1
1----1- VOl = 51 "dr-...--j~-+-+-+-----+----+---+-----1
~
(,)
~
300 I----
N
It=25 0 C]-
I
(,)
c
0
~
R
~...
g
160 kCl
«
200~--4--+--+-~~~~~~----+---4--4-~
".~ ~ VDD~,~
~33PFT
.-m
R
-1--1--+-1---
0
i i
R=240kO- ~
II)
50
100
fCC vs TA
1000
Voo= 5V.
--I...-----I------I-.!!..':.!~
! '" 'f~i
~
!
I
C=33 pF
AC/oC S60 ppm
OL-________
~
__________L -_________L_ _ _ _ _ _ _ _
25
50
L
11>12:fC= ~
212
100 f.-.-
Defined
Operaling Vollage
11 <12:fC= ~
211
lAo
U
~
10
E
~
!
~
~
1
75
a
Supply Vollage Voo [V]
Operaling Temperalure TA 1°C]
loovs VOO
fX vs VOO
1000
I
11
N
!
400 f-
~
!
!
1000
I
[TA= 25°C]
12
--11-1
X1J"LR
r;
100 f-
.."
11>12:fX=~
212
11<12:fX=~
211
c
r"
V
500 I-
V
~
c
Defined
Operating Voltage
100
.~
50 I- 33
E
~
~
"
0
1
F-PF
l"
I
0.1
o
Supply Vollage Voo [V]
3-106
F 22
o
-
~:~~ g:~ ~gl-
STOP + Xlal Oscillalion
~
,17r~~
0
kHz
0.5
•
(J
I-:';::;;;;
~
~
[82kO]
[160kO]
[240 kO]
HALT [82kCl]
~
X2
XI
II)
-
I
I
U
10
25°C]
-,.
I
10
[TA
R
PF,l
,.,
~
g
i)
V
V
g
R=240kO
-25
[TA = 25°C]
CL1J"LR
2!
--~-----~-----I----~
~
~ Voo=2.5V.-
50
__1'll~
IT
VDD''',
R = 160kCl
I-J; C --~-----~-----~---__ ~----_ 1- _ _ _ _ _ ~---
g
U
N
!
~
I
I
400 I-
--1...-----1------1-----
~ 100
SOD
fcvs VOO
250r-------r---------r---------~--------~
o
200
Resislance R [kO]
Supply Vollage VOO IV]
I
...............
VOO = 2.5 V----"'"
~
......
N----+--i
50 f - -
~
kO
1
~
33
pF
l....o'"
r--'::/
4
Supply Voltage Voo [V]
STOP [XI
= a V]
NEe
IlPD7507/08
Operating Characteristics (cont)
TA
= 25°C
1001 VS
fcc
1001 VS TA
500r-----~------,-------r-----_r------~----~
~
C
E
~
J
400
~
0
:::I! 300
33 pF
E
I!
A
500
1
c 400
E
..o
."
i
----+---~'I"'___----+----f
~
0
~
o
200
c
~
,.,
200 f - -
c
~
0
~
300 I--
I!
100
0
~
~----~------~------~----~------~----~~
0
50
100
150
200
250
,., 100
!
-5
-25
300
X
75
15
E
c
~
i
50
IOL vs VOL
...
5
0
-3
~
i
25
Operating Temperature T A [OC]
<'
g
-4
__~--------~VOO=3V
0
I
20
:r:
:l
A
Voo = 3 V, A = 160 kO
o
IOH vs VOH
0
Voo = 5 V, A = 82 kO
Ul
-6
c
~
J
33pF
System Clock Oscillation Frequency ICC [kHz]
E
----
U
Ul
<'
g
- -
-2
~
0
____- - - , VOO = 3 V
10
___-+----
Voo= 2.5 V
~
~
.3
-1
High-Level Output Voltage VOH [V]
Low-Level Output Voltage VOL [V]
3-107
~PD7507/08
3-108
NEe
NEe
NEe Electronics Inc.
Description
The pPD7507H and pPD7508H are pin-compatible,
high-speed (4.19 MHz), 4-bit, single-chip CMOS microcomputers with the pPD7500 series architecture. The
subroutine stack is implemented in RAM for greater
nesting depth and flexibility.
Thirty-two I/O lines are organized into eight 4-bit
ports: input port/serial interface port 0, output ports 2
and 3, and I/O ports 1,4,5,6, and 7.
The pPD7507H and pPD7508H execute 92 instructions
of the pPD7500 series A instruction set with a 2.86-ps
instruction cycle time.
Maximum power consumption is 800 pA at 5 V and less
in the HALT and STOP low-power modes.
The 75CG08H is a piggyback EPROM prototyping chip
that is pin-compatible with 7507H and 7508H. A 2716
plugged into the top of the 75CG08H emulates the
ROM of a 7507H. A 2732 emulates the ROM of 7508H.
When emulating the 7507H, the user must take care to
use only the first 128 RAM locations. Although 7507H
and 7508H can operate over a range of 2.5 to 6.0 V,
75CG08H is limited to 5 V ±10%. Table 1 summarizes
the differences among 7507H, 7508H, and 75CG08H
pPD7507H/08H
4.BIT, SINGLE·CHIP
CMOS MICROCOMPUTERS
Ordering Information
Part No.
Package Type
Max Frequency
of Operation
tLPD7507HC
40-pin plastic DIP
4.19 MHz
tLPD7507HCU
40-pin plastic shrink DIP
4.19 MHz
tLPD7507HG-22
44-pin plastic miniflat
4.19 MHz
tLPD7508HC
40-pin plastic DIP
4.19 MHz
tLPD7508HCU
40-pin plastic shrink DIP
4.19 MHz
tLPD7508HG-22
44-pin plastic miniflat
4.19 MHz
tLPD75CG08HE
40-pin ceramic piggyback DIP
4.19 MHz
Pin Configurations
40-Pin Plastic DIP and Plastic Shrink DIP
OUT
1
EVENT
P20/PSTB
2
Vss
P21/PTOUT
3
P43
NC
P23
Voo
NC
P41
P10
P40
As
P11
Ag
P12
P13
P30
P31
P32
P33
A4
A11
A3
Vss
A2
A10
A1
CE
Ao
17
11
Is
12
14
Vss
13
Is
P70
P71
P72
P73
P4 2
RESET
P51
P62
P03/S1
P02/S0
P01/SCK
POo/INTO
Cl1
INT1
Voo
Cl2
83-003761 A
44-Pin Plastic Miniflat
Function
27-30
P60-P6J
110 port 6
31-34
P50-P53
110 port 5
35-38
P4o-P43
110 port 4
39
Vss
Ground
40
EVENT
External event input port
44-Pln Miniflat
83-003762A
No.
Symbol
1.4
P1o-P13
I/O port 1
5-8
P30-P33
Port 3 output
9.10.
13.14
P70-P73
110 port 7
11-12
NC
Not connected
15
RESET
RESET input
16.18
CL1. CL2
System clock inputs
17
VOO
Positive power supply
19
INn
External interrupt 1
20
POoflNTO
Port 0 inputflnterrupt 0
21
P01/SCK
Port 0 input/Serial clock 110
22
P02/S0
Port 0 input/Serial output
23
NC
Not connected
24
P03/S1
Port 0 input/Serial output
25-28
P60-P6J
I/O port 6
29-32
P5Q- P53
I/O port 5
P40-P43
110 port 4
33-36
3-110
Function
NEe
pPD7507H/08H
Pin Identification (cont)
P20/PSTB, P21/PTOUT, P22, P23 [Port 2]
44-Pin Miniflat (cant)
No.
Symbol
37
Vss
Function
Ground
4-bit latched three-state output port. Line P2a is shared
with PSTB, the port 1 output strobe pulse. Line P21 is
shared with PTOUT, the timer out F/F signal. Leave
unused pins open.
38
EVENT
External event input
39
The clock control circuit consists of a 4-bit clock mode
register (bits CMo-CM3), prescalers 1,2, and 3, and a
multiplexer. It takes the output of the system clock
generator (CL) and external EVENT input. It also
selects the clock source and divides the signal
according to the setting in the clock mode register. It
outputs the count pulse (CP) to the timer/event
counter. Figure 3 shows the clock control circuit.
CM1
CMo
Frequency Selected
0
0
fce/1536 (CLl256)
0
1
fce/512 (fee/8 x 1/64)
1
0
EVENT input
1
Not used
0
fcc/192 (CLl32)
0
Cll
Frequency Range
VOO
IIPD74HCOO
4.5 to 6.0 V
0.1 to 4.2 MHz
2.7 to 6.0 V
0.1 to 1.8 MHz
0
0
~Cl2
0
0
83·003763A
fcc/64 (fcc/8 x 1/8)
0
Memory Map
Not used
Not used
Figure 2 shows the ROM program map of the
7507H17508H.
Figure 2.
ROM Map
Address
[Decimal)
MSB
0
:I:
:I:
~
Q
~
Address
[Hex)
LSB
716151413121110
OOOH
RESET Pulse Vectors Program
Execution to Address OOOH
INTT [Internal Timer/Event
Counter Interrupt) Vectors
Execution to 010H
INTO/S [External Interrupt 0/
Serial Interface Interrupt)
Vectors Execution to 020H
16
010H
32
020H
48
030H
INTl [External Interrupt 1)
Vectors Execution to 030H
192
OCOH}
207
OCFH
LHLT Instruction
Reference Table
Q
II.
"'-
1
II.
:c
II.
"'II.
:c 0~
~
0
~.
ODOH}
CAL T Instruction
Reference Table
255
OFFH
. 1023
1024
3FFH
400H
2047
2048
7FFH
800H
Last Address for CALL Instruction Entry
IIPD7507H
<----4095
FFFH
Last Address for CALL Instruction Entry
IIPD7508H
83·0034368
3-113
1m
NEe
pPD7507H/08H
Figure 3.
Clock Control Circuit
Internal Bus
To Timer/
Event Counter
1/8 fcc----------1~_+_r~
CL----t
[1/6 feel
EVENT-----I
>----_CP
Count Pulse to
Timer/Event Counter
'Instruction execution
83-003469B
Timer/Event Counter
Serial Interface
The timer/event counter consists of an 8-bit counter,
an 8-bit modulo register, an 8-bit comparator, and a
timer out flip flop as shown in figure 4.
The 8-bit serial interface allows the pPD7507H/08H to
communicate with peripheral devices such as the
pPD7001 A/D converter, the pPD7227 dot matrix LCD
controller/driver, and other microprocessors or
microcomputers.
The 8-bit count register is a binary 8-bit up counter,
which is incremented each time a count pulse is input.
The TIMER instruction, a RESET signal, or an INTT
coincidence signal clears it to OOH.
The 8-bit modulo register determines the number of
counts the count register holds. The TAMMOD instruction loads the contents of the modulo register.
RESET sets the modulo register to FFH.
The 8-bit comparator compares the contents of the
count register and the modulo register and outputs an
I NTT one clock pulse after they are equal.
Table 3.
The serial interface consists of an 8-bit shift register, a
3-bit SCK pulse counter, the SI input port, the SO
output port, the SCK serial clock I/O port, and a 4-bit
serial mode select register (MSR). The MSR selects
serial I/O or port 0 operation.
Interrupts
ThepPD7507H/08H has four vectored, prioritized interrupts. Two of these interrupts, INTT and INTS, are
internally generated from the timer/event counter and
serial interface, respectively. INTO and INT1 are
externally generated. Table 3 is a summary of the four
interrupts.
pPD7507HIOBH Interrupts
Source
Function
Location
Priority
INTT
Coincidence in timer/event counter
Internal
1
10H
INTS
Transfer complete signal from serial interface
Internal
2
20H
INTO
INTO pin
External
2
20H
INT1
INT1 pin
External
3
30H
3-114
ROM Vector Address
NEe
Figure 4.
pPD7507H/08H
Timer/Event Counter
r-----------------------J
Internal Bus
L -_ _~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
~CNTAM------------------------------~
1------- INTT
[Coincidence]
CP----------------------------------~~
.--+------1---- ~u;erlallnterfaCe)
·Command Execution
Clock
MSR
Bit 3
·Timer
RESET
PTOUT
[to P21/
PTOUTpln]
83-0034378
Figure 5.
System Clock Circuitry
I-+-__________________.. ~;:~~~ Timer/Event Counter
~
__________________-.CL
[698 kHz]
CL1
~
[349 kHz]
CL2
~---"'---'--
Halt Release
~--z--..--
Reset ['-.]
~-,...-t---
Hall
*
14----+-- Stop*
t+--------+--- Reset
·Command Instruction
83-0034388
3-115
~EC
pPD7507H/08H
System Clock and Timing Circuitry
Table 4. pPD7507H/OBH Time Bases
There are four time bases available for the
pPD7507H/08H. Table 4 shows these bases and the
frequencies generated.
Base
The CPU clock is used by the CPU and serial interface.
The system clock is used by the timer/event counter
and the INT1 signal.
External clock
Symbol
Frequency
CL
1/6 fcc (698 kHz/4.19 MHz)
System clock
CPU clock
1/12 fcc (349 kHz/4.19 MHz)
1/12 fCC (349 kHz/4.19 MHz)
¢OUT
Timerlevent
counter clock
1/8 fcc (524 kHz/4.19 MHz)
1/0 Port Interfaces
Figure 6 shows the internal circuit configurations at the
I/O ports.
Figure 6.
Interlace at Input/Output Ports
Type B
Type E
POoIINTO, INn, P03/SI, RESET, EVENT
P10-P13, P02/S0, P40-P43, P50-P53, P60-P63, P70-P73
Voo
p·ch
Datalb:
Inpull
Output
Type C
Output
Disable
¢OUT
Voo
Voo
--t
Vss
Output
Vss
Vss
Type D
P20/PSTB, P21/PTOUT, P22, P23, P30-P33
Voo
Type F
P01/SCK
Voo
Dat8Jb:
Output
Output
Disable
P·ch
D8ta1h:
I"pull
Output
N·eh
Vss
Output
Disable
Note: Upon RESET, both transistors are turned off.
Vss
83-003439C
3-116
NEe
pPD7507H/08H
Absolute Maximum Ratings
Capacitance
TA = 25°C, Voo = 0 v
TA=25°C
Limits
Operating temperature, TOPT
Storage temperature, TSTG
Power supply voltage, Voo
All input and output voltages
-0.3 to +7.0 V
--0.3 to Voo + 0.3 V
Output current, high, IOH
One pin
All pins, total
-5mA
-20mA
Output current, low, IOL
One pin
Ports 6, 7
Total ports
17 mA
20 mA
200 mA
Parameter
Symbol
Input capacitance
CI
Typ
Max
15
Unit
Test
Conditions
pF f = 1 MHz;
........:...-........:...-----~------..:..P-F unmeasured pins
Output capacitance
15
Co
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ returned to Vss
I/O capacitance
CIQ
15
pF
Comment: Exposing the. device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
3-117
t-IEC
pPD7507H/08H
DC Characteristics
T A = -10 to +70°C; VDO = 2.7 to 6.0 V (5 V ±10% for 75CG08H)
Limits
Parameter
Symbol
Input voltage, high
VIH1
Input voltage, low
Output voltage, high
Output voltage, low
Input leakage current, high
Input leakage current, low
Min
Typ
0.7 Voo
Test
Conditions
Max
Unit
Voo
V
CL1, CL2
Except CL 1, CL2
VIH2
Voo - 0.5
Voo
V
VIHOR
0. 9VOOOR
VOOOR + 0.2
V
RESET, data retention mode
0
0.3 Voo
V
Except CL 1, CL2
VIL2
0
0.5
V
CL1, CL2
VOH
Voo -1.0
V
IOH = -1.0 mA; Voo = 4.5 to 6.0 V; except
A11/VPP
VIL1
VOO - 0.5
V
IOL = -100 /.lA
Voo - 0.75
V
A11 /Vpp; IOH = -5 mA (j.tPD75CG08H only)
0.5
VOL
1.5
V
IOL = 12 mA; VOO = 4.5 to 6.0 V; Ports 2-5
0.4
V
IOL = 1.6 mA; VOO = 4.5 to 6.0 V; Ports 6-7
0.5
V
3
/.lA
Except CL 1, CL2; VI = Voo
IUH2
20
/.lA
CL 1, CL2; VI = Voo
IUL1
-3
/.lA
Except CL 1, CL2; VI = 0 V
IUL2
-20
/.lA
CL 1, CL2; VI = 0 V
IUH1
IOL = 400/.lA
Output leakage current, high
ILOH
3
/.lA
Vo = Voo
Output leakage current, low
ILOL
-3
/.lA
Vo =OV
Supply voltage
VOOOR
6.0
V
Supply current
1001
900 (1)
1000 (2)
3000 (1)
3000 (2)
/.lA
/.lA
Normal operation, Voo = 4.5 to 6.0 V;
f = 4.19 MHz
150 (2)
700 (2)
/.lA
Normal operation, VOO = 2.7 to 3.3 V;
f= 1 MHz
350 (1)
500 (2)
800 (1)
1100 (2)
/.lA
/.lA
HALT mode, X1 = 0 V; VOO = 4.5 to 6.0 V;
f = 4.19 MHz
70 (2)
180 (2)
/.lA
HALT mode, X1 = 0 V; VOO = 2.7 to 3.3 V;
f= 1 MHz
0.1
10
/.lA
STOP mode
1002
1003
Note:
(1) Crystal oscillation; C1 = C2 = 10 pF.
(2) Ceramic oscillation; C1 = C2 = 30 pF.
3-118
2.0
Data retention mode
NEe
pPD7507H/08H
AC Characteristics
TA = -10 to HO°C; VDD = 2.7 to 6.0 V (5 V ±10% for 75CG08H)
Limits
Parameter
Symbol
Min
System clock frequency
fCY
EVENT input frequency
fE
Typ
Max
Unit
2.86
120
kHz
6.7
120
kHz
0
700
kHz
0
250
kHz
Test
Conditions
Voo = 4.5 to 5.5 V
Voo = 4.5 to 6.0 V
EVENT input high
tEH
0.7
ps
EVENT input low
tEL
3.3
ps
SCK cycle time
tKCY
2.5
ps
SCK as input; Voo = 4.5 to 6.0 V
10
ps
SCK as input
2.86
ps
SCK as output; Voo
11
ps
SCK as output
SCK pulse width
SI setup time to SCK
tKH. tKL
t
SI hold time after SCK
t
SO delay time after SCK
l
ps
SCK as input; Voo = 4.5 to 6.0 V
ps
SCK as input
ps
SCK as output; Voo
ps
SCK as output
tSIK
300
ns
tKSI
450
tKSO
ns
1200
ns
ns
(Note 2)
ns
tSTP
80
ns
tSWL
(Note 1)
ns
(Note 2)
ns
10
ps
PSTB pulse width
tIOH. tlOL
tI1WH. tl1WL
(Note 3)
ps
10
ps
RESET pulse width
tRSH. tRSL
RESET setup time
tSRS
0
ns
tos
25
ms
Clock stabilization time
=4.5 to 6.0 V
ns
850
(Note 1)
Port 1 output hold time after
PSTB t
INT1 pulse width
1.1
1.3
tpST
=4.5 to 6.0 V
4.5
5.0
Port 1 output setup time to
PSTB t
INTO pulse width
Voo = 4.5 to 6.0 V
Voo = 4.5 to 6.0 V
Voo = 4.5 to 6.0 V
Voo = 4.5 to 6.0 V
Voo =4.5 V
Note:
(1) (3 -:- fcc or fc) - 350.
(2) (3 -:- fcc or fc) - 1000.
(3) tCY = 12 -:- fcC or fC·
3-119
NEe
pPD7507H/08H
Timing Waveforms
External Interrupts
Clocks
.Nro --C="O'=:J="O"~
'Nn --C='"'=:J='"~
Timing Measurement Points
83-003317A
~O.7.VOO
O.7V00V--~~O~.3_V~o~o________________O_.3_V~O~O~
Reset
83·003411 A
Serial Interface
83-003318A
STOP Mode
I~STOPMode
SI
~~
---+------00{
VOO
so
-----Valid Output Data
Data Retention
VOOOR
)(
RESET
83-003316A
83-003442A
EVENT Input
83-003441 A
3-120
NEe
pPD7507H/08H
Operating Characteristics (cont)
TA
= 25°C
Oscillator Frequency vs Supply Voltage
Oscillator Frequency vs Supply Voltage
10
10
== MC'~c,~,,,,
N
J:
::
~
~
0
i
0
-_
o
0.5
0.4
0.3
C1;};
--~
J;C2
.~
0
0.2
0.1 '--_---''--_----'_ _--'-_ _........J.._ _- - ' -_ _- ' -_ _- ' - - - - '
o
o
Supply Voltage, VOO [V]
Clock Frequency vs Supply Voltage
100
f=1
~
J:
~
:
1.1 MHz_L--J
Supply Voltage, VOO [V]
N
I
_2.5MHz
C1J;
~
==
0.2
0.1
0
£c
--
;};C2
--f-4.2MHZ
=
i
CL1
CL2 C2 < 20
~C,
""pF
£c
°
_
~
Jl
J:!
~.~
N
J:
J:!
r ~~~
10
I
t:,
Event Frequency vs Supply Voltage
CLaj
CL1
IlPD74HCOO
c
o
co
.~
--
o
'"
u°"
.,
.,>c
0.1
0.01 I----I------t----t--+---+---+---+--_+_-----I
w
c
o"
(J
0.01
0.001 '--_ _'--_----'_---'--'-_ _--'-_ _--'-_ _.....L.._ _- ' - - - - '
o
o
Supply Voltage, Voo [V]
Supply Voltage, VOO [V]
Supply Current vs Supply Voltage
104
=R --
=
<"
~
103
==
E
c
~
102
CL2
0
~
==
C
CL1
];,C1
C1
];,C2
= =
C2
30 pF
I
,.
I
t3:t~:r.::J:
fCC
1
_I, ~
100
r-
1 MHz
fCC 4.19 MHzfCC = 1 MHz
HALT Mode
I
10'
1400
Operating Mode
(J
~
en
Oscillator Frequency vs Supply Voltage
1200
<"
~
1000
c
800
(J
...
600
~
en
400
c
E
i
~ht
0
rr-
=T
C
I
o
o
Supply Voltage, Voo [V]
J ; C,
, L'
V
-- ----
o
TA= 25°C
Voo=5V-
Voperatin g Mode
J;C2
C, = C2 = 30 pF
200
TA
j
~ fHALTMode
Oscillation Frequency, fCC [MHz]
3-121
NEe
pPD7507H/08H
Operating Characteristics (cont)
TA
= 25°C
Clock Frequency vs Supply Voltage
VOL vs. IOL [Ports 2-7]
20
TA = 25°C
1400
TA= 25°C
Voo = 5 V
1200
~
c
.,/
/
V
1000
E
.:
E.
./
800
~
15
:c
~
' / p e r a l i n g Mode
0
>.
SOO
Q.
g.
400
III
V
o
o
i
~
0
HALT Mode _ _
./
200
~~
I-
~
2
Output Voltage - V
Counter Clock Frequency, Ie [MHz]
VOH vs.IOH
-7
TA = 25°C
-6
:c
E.
-5
voo=s'j
I:
-4
0
-3
0
-2
Vvo~
/1 0-0=4~
i
///
1///
i
-1
~
---
Voo=3V
o
o
Output Voltage - V
3-122
Voo =3 V
10
U
,NEe
pPD7507S
4-BIT, SINGLE-CHIP
CMOS MICROCOMPUTER
NEe Electronics Inc.
Description
Pin Configuration
The jJPD7507S 4-bit, single-chip CMOS microcomputer has advanced fourth-generation architecture. It is a reduced version of the jJPD7507, with fewer
I/O lines. The device can be operated as low as VD D =
2.2 V to minimize power consumption.
P20
4
P21/PTOUT
P22
P23
Features
P30
D Single-chip microcomputer
D Can operate on a single lithium battery
D Executes 91 instructions of jJPD7500 instruction
setA
D 2048 x 8-bit program ROM
D 128 x 4-bit data RAM
D Interrupt capabilities
- Two external interrupts: INTO, INT1
- Two internal interrupts: INTT, INTS
D 8-bit timer/event counter
D 8-bit serial interface
D Two standby modes
D Data retention mode
D 20 I/O lines
D Internal RC oscillation circuitry
D Crystal oscillation circuitry for count clock
D Low power consumption
o Single 2.2 to 6.0 V operating voltage
o CMOS technology
Ordering Information
Part No.
Package Type
Max Frequency
of Operation
J.lPD7507SC
28-pin plastic DIP
410 kHz
J.lPD7507SCT
28-pin plastic shrink DIP
410 kHz
P03/S1
P02/S0
P01/SCK
POolINTO
INT1
83-003418A
Pin Identification
No.
Symbol
1,25-27
Function
I/O port 4
2,3
X2, X1
Crystal clock/external event input
4-7
P2o, P21/PTOUT,
P22, P23
Output port 2/timer out F/F signal
8-11
Output port 3
12
RESET
RESET input
13,15
CL1, CL2
System clock input
Positive power supply
14
Voo
16
INT1
External interrupt
17-20
POO/INTO
P01/SCK
P02/S0
P03/S1
Input port O/external interrupt,
serial I/O interface
21-24
I/O port 5
28
Vss
Ground
3-123
NEe
/APD7507$
Pin Functions
POo/INTO, P01/SCK, [Port O/Externallnterrupt
Serial Interface] P02/S0, P03/S1
'
4-bit input port/serial I/O interface. This port can be
configured as a 4-bit parallel input port or as the 8-bit
serial I/O interface under control of the serial mode
select register. The serial input SI, serial output SO,
and the serial clock SCK (active low) used for
synchronizing data transfer make up the 8-bit serial I/O
interface. Line POa is always shared with external
interrupt INTO, a rising-edge triggered interrupt. If
POa/INTO is unused, it should be connected to ground.
If P01/SCK, P02/S0, or P0 3/SI are unused, connect
them to ground or Voo.
P20, P21/PTOUT, P22, P23 [Port 2]
4-bit latched three-state output port. Line P21 is shared
with PTOUT, the timer out F/F signal. If any pins are
unused, leave them open.
P33-P30 [Port 3]
4-bit latched three-state output port. Leave unused pins
open.
P43-P40 [Port 4]
4-bit input/latched three-state output port. This port,
with port 5, also performs 8-bit parallel I/O. In input
mode, connect unused pins to ground or Voo. In
output mode, leave unused pins open.
3-124
P53-P50 [Port 5]
4-.bit input/latched three-state output port. This port,
with port 4, also performs 8-bit parallel I!0~ In input
mode, connect unused pins to ground· or VDO. In
output mode, leave unused pins open.
X2, X1 [Crystal Clock/External Event Input]
Connect a crystal oscillator circuit to input X1 and
output X2 for crystal clock operation. Alternatively,
connect external event pulses to input X1 and leave
output X2 open for external event counting. If X1 is not
used, connect it to ground. If X2 is not used, leave it
open.
CL 1, CL2 [System Clock Input]
Connect an 82-kO resistor across CL 1 and CL2 and
connecta 33-pF capacitor from CL 1 to GND (200 kHz).
Alternatively, connect an external clock source to CL 1
and leave CL2 open.
INT1 [External Interrupt]
This is a rising edge-triggered interrupt.
Voo [Power Supply]
Positive power supply. Apply a single voltage in the
range 2.2 to 6.0 V for proper operation.
Vss [Ground]
Ground.
NEe
JAPD7507S
Block Diagram
Xl
INTl INTO/POO
X2
SCKlP01
SI/P03
SO/P02
POO·P03
Program Memory
2048 x 8 Bits
Cl
H [4]
Instruction
Decoder
¢
Data Memory
l28x4 Bits
Cll
Cl2
r
Voo
t
VSS
t
RESET
83'()03419B
3-125
NEe
IlPD7507S
Memory Map
Figure 1 shows the program memory map of the
pPD7507S.
Figure 1.
Program Memory Map
Address
[decimal]
MSB
71 61 5 I 41 3 I 2.11
Address
[Hex]
LSB
I0
OOOH
RESET pulse vectors program execution
to addre.s OOOH.
161========1 010H
INTT [internailimer/event counter Interrupt]
vectors program execution to addre•• 010H.
321========1 020H
INTO/S [External Interrupt O/lnternal serial
Interface Interrupt] vectors program
execution to address 020H.
461========1 030H
INT1 [Extemallnterrupt1] vectors execution
to address 030H.
192 t - - - - - - ' - - - - I OCOH
~g~ t - - - - - - - - I g~~~
255 t - - - - - - - - I OFFH
2047 ...._ _ _ _ _ _", 7FFH
I LHLT Instrucllon reference table.
I CALT Instruction reference table.
Last address for CALL Instruction entry.
83-0034216
3-126
t\'EC
J.lPD7507S
Clock Control Circuit
The clock control circuit consists of a 4-bit clock mode
register (bits CMo-CM3), prescalers 1,2, and 3, and a
multiplexer. It takes the output of the system clock
generator (CL) and the count clock generator circuit
(I). It also selects the clock source and divides the
signal according to the setting in the clock mode
register. It supplies the timer/event counter with the
count pulse. Figure 2 shows the clock control circuit.
Table 1 lists the codes set in the clock mode register by
the OP 12 and OPL instruction to specify the count
pulse frequency. CM3 controls the timer out flip flop.
When CM3 is 0, the timer out F/F is disabled; when CM3
is 1, it is output. When you set the clock mode register
with the OPL instruction, clear the high-order two bits
of the accumulator.
Table 1.
o
o
o
o
Selecting the Count Pulse Frequency
CM1
CMu
0
0
ClI256
0
1
X/64
0
X
1
Frequency Selected
X
0
0
ClI32
0
1
X/8
0
Not used
Not used
CM3
Timer F/F Output
o
Disabled
Output
Figure 2.
Clock Control Circuit
x--------------~~+-+-~~
>---------cp
·Instructlon execution
83·0034208
3-127
NEe
J.lPD 7 50"7S
Timer/Event Counter
The timer/event counter consists of an 8-bit counter,
an 8-bit modulo register, an 8-bit comparator, and a
timer-out flip-flop as shown in figure 3.
The 8-bit counter is a binary up-counter which is
incremented each time a count pulse is input. The
TIMER instruction, an INTT coincidence signal, or a
RESET signal clears it to OOH.The 8-bit modulo register
determines the number of counts the count register
holds. The TAMMOD instruction loads the modulo
register. RESET sets the modulo register to FFH.
The 8-bit comparator compares the contents of the
count register to the modulo register and outputs a
coincidence signal when these are equal.
Figure 3.
Timer/Event Counter
~_~
_______Internal Bus
~
~-----------J
*TCNTAM - - - - - -__- - - - - - + 1
1------- INTT
[Coincidence]
c p - -__
~
Count Hold
Circuit
[Initialized during TCNTAM]
t--+--t---
·Command Execution
CM3
~~U:erlal Interface)
PTOUT
Timer
RESET
83-003422B
3~128
NEe
J.lPD7507S
Serial Interface
The 8-bit serial interface allows the pPD7507S to
communicate with peripheral devices such as the
pPD7001 AID convertor, the pPD7227 dot matrix LCD
controller/driver, and other microprocessors or microcomputers. Figure 4 shows the serial interface.
The serial interface consists of an 8-bit shift register, a
3-bit SCK pulse counter, the SI input port, the SO
output port, the SCK serial clock I/O port, and a 4-bit
serial mode select register (MSR). The MSR selects
serial I/O or port 0 operation.
Figure 4.
Serial Interface
P03/SI 0 - - - - - - - 1
>--*+t+--+I
P02/S0o----........-----+t---c~ ...- - - - - - - - I _ - - - - - - - - - - - . J
'-..s>--t-- TOUT
POollNTO - - - - - - - - - - 1
• Command execution
I/J System Clock
RS F/F
t--+----.:T~nt8rruPt Circuit)
S
1+------ ·SIO
83-0034238
3-129
NEe
J.lPD7507S
Interrupts
System Clock and Timing Circuitry
The pPD7507S has four vectored, prioritized interrupts. Two of these interrupts, INTT and INTS, are
internally generated from the timer/event counter and
serial interface, respectively. INTO and INT1 are
externally generated. Table 2 is a summary of the four
interrupts. Figure 5 is the block diagram.
Timing generation for the pPD7507S is internally
generated except for a frequency reference, which can
be an RC circuit or an external clock source. Connect
the frequency reference to the on-chip oscillator for
the feedback and phase shift required for oscillation.
Figures 6 to 9 show the connections for count clocks
and system clocks.
Table 3 shows the operating status of the various logic
blocks under the three power-down mod.es.
Table 2.
pPD7507S Interrupts
Function
Source
Location
Priority
INTT
Coincidence in timer/event counter
Internal
1
10H
INTS
Transfer complete signal from serial interface
Internal
2
20H
INTO
INTO pin
External
2
20H
INT1
INT1 pin
External
3
30H
Figure 5.
ROM Vector Address
Interrupt Block Diagram
INT1o---+---:'l==~--~
INTS
Plio/INTO o---+-IJ
SIO·
INTT------,---,----f
L.-:=::.....I
·Command Instruction
Standby
Release
83-o03424B
3-130
NEe
Figure 6.
J..lPD7507S
Count Clock. Crystal Oscillator
Figure 8.
System Clock. RC Oscillation
r:--
C
~
Xl
System Clock ¢
[To CPU and Serial Interface]
Count Clock X
[To Count Clock]
Crystal
Oscillation
c~~~~~~~X_2______~
L..:: _ _ _
HALT Mode
' - - - - - _ C L [To Clock Circuitry]
83-003425A
83-003427A
Figure 7.
Count Clock. External Source
Figure 9.
System Clock. External Source
1:--External
Clock
I
IL
Xl
Count Clock X
[To Count Clock]
Buffer
X2
External
Clock
System Clock ¢
[To CPU and Serial Interface]
___
CL2
HALT Mode
L - - - - - _ C L [To Clock Circuitry]
83-003426A
83-Q03428A
Table 3.
Power-Down Operating Status
Power Down Mode
Logic Block
HALT
STOP
Data Retention
System clock
(1)
Disabled
Disabled
X2
Normal
Normal
Disabled
CPU
Disabled
Disabled
Disabled
RAM
Data retained
Data retained
Data retained
Internal registers
Data retained
Data retained
Data retained
Timer/event counter
Normal
(3)
Disabled
Serial interface
(2)
(2)
Disabled
INTO
Normal
Normal
Disabled
INT1
Normal
Disabled
Disabled
RESET
Normal
Normal
(4)
Note:
(1) Supplied to timer/event counter but not to CPU or serial interface.
(2) Can function normally if the MSR is set to get the SCK signal externally or from the TOUT signal.
(3) Can function normally if the clock MSR is set to use X1 as the source for the count pulse.
(4) To enter the data retention mode, raise RESET while Voo is lowered. To end the data retention mode, raise RESET when Voo is raised,
then lower it. INTT, INTO, INTS or RESET releases the STOP mode. RESET or any interrupt releases the HALT mode.
3-131
I
NEe
IAPD7507S
1/0 Port Interfaces
Figure 10 shows the configurations at the I/O ports.
Figure 10.
Input/Output Port Interfaces
Type A
Type E
P02/S0, P40·P43, PSO·PS3
Vee
Vee
[Type 0 output]
P·ch
Data~
Inpull
Output
Output
Disable
Vee
Vss
Vss
Type B
POO/INTO, P03/SI, INT1, RESET
[Type A input]
~'"'"
Vss
Type D
Typ~
P30·P03, P20, P21/PTOUT, P22, P23
P01/SCK
Vee
Voo
[Type 0 output]
Data~
P·ch
Data~
Inpull
Output
Output
Output
Disable
Output
Disable
Vss
.
.
Vss
[Type B Input]
Note: Upon RESET, both transistors are turned off.
83-003861C
3-132
NEe
J.tPD7507S
Capacitance
Absolute Maximum Ratings
-10 to +70°C
Operating temperature. TOPT
TA
= 25°C,
VD D =
0v
Limits
-6.5 to +150°C
Storage temperature, TSTG
-0.3 to +7.0 V
Power supply voltage, VDD
Input voltage, VI
-0.3 to VDD + 0.3 V
Output voltage. Vo
-0.3 to VDD + 0.3 V
Symbol
Parameter
Typ Max
Input capacitance
CI
15
pF
Output capacitance
Co
15
pF
15
pF
1/0 capacitance
Output current high, 10H
One pin
Total. all pins
Test
Conditions
Unit
f = 1 MHz;
unmeasured pins
returned to Vss
-17mA
-34mA
Output current low. 10l
One pin
Total, all pins
Ports P2. P3. and P43
Ports P5 and P40-P42
17mA
25 mA
25 mA
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
For VDD = 2.7 to 6.0 V
TA = -10 to +70°C
Limits
Parameter
Input voltage, high
Input voltage, low
Symbol
Min
Typ
Max
VIH1
0.7 VDD
VDD
V
Except CL 1, X1
VIH2
VDD - 0.5
VDD
V
CL1, X1
VIHDR
0.9VDDDR
VDDDR + 0.2
V
RESET, data retention mode
0
0.3 VDD
V
Except CL 1, X1
0.5
V
CL1, X1
V
10H = 1.0 mA; VDD = 4.5 to 6.0 V
VIl1
VIl2
0
Output voltage, high
VOH
VDD -1.0
Output voltage, low
VOL
V
10l = -100pA
0.4
V
10l = 1.6 mA; VDD = 4.5 to 6.0 V
0.5
V
10l = 400 pA
IUH1
3
IUH2
10
IUL1
-3
pA
pA
pA
pA
pA
pA
VDD - 0.5
Input leakage current, high
Input leakage current. low
Test
Conditions
Unit
IUl2
-10
Output leakage current, high
ILDH
3
Output leakage current. low
IlOl
-3
Supply voltage
VDDOR
Supply current
ID01
2.0
V
CL 1, X1; VI = VDD
Except CL 1, X1; VI = 0 V
CL 1. X1; VI = 0 V
Vo = VDD
Vo =OV
Data retention mode
300
900
pA
Normal operation, VDD = 5 V ±10%; R = 82
kn ±2%. C = 33 pF ±5%
70
300
pA
Normal operation. VDD = 3 V ±10%; R = 160
kn ±2%, C = 33 pF ±5%
20
pA
pA
pA
Stop mode, X1 = 0 V; VDD = 5 V ±10%
IDD2
IDDDR
Except CL1, X1; VI = VDD
0.3
10
0.2
10
Stop mode, X1 = 0 V
Data retention mode VODDR = 2.0 V
3-133
NEe
IlPD7507S
DC Characteristics (cont)
VDD
= 2.2 103.3 V
TA = -10 to +70°C
Limits
Parameter
Symbol
Input voltage, high
VIH1
VIH2
VIHOR
Unit
0.7 VOO
VOO
V
VOO - 0.1
VOO
V
CL1, X1
0.9VOOOR
VOOOR + 0.2
V
RESET, data retention mode
VIL1
0
0.2 VOO
V
Except CL 1, X1
VIL2
0
0.2
V
CL1, X1
Output voltage, high
VOH
VOO - 0.5
Output voltage, low
VOL
Input leakage current, high
Input leakage current, low
Typ
Test
Conditions
Max
Input voltage, low
Min
Except CL 1, X1
V
IOH = -BOJlA
0.5
V
IOL = 350pA
IUH1
3
JlA
Except CL 1, X1; VI = VOO
IUH2
10
JlA
CL1, X1; VI = VOO
IUL1
-3
JlA
Except CL 1, X1; VI = 0 V
IUL2
-10
JlA
CL1,X1;VI=OV
Output leakage current, high
ILOH
3
JlA
Va = VOO
Output leakage current, low
ILOL
-3
JlA
Va =OV
Supply voltage
VOOOR
Supply current
1001
1002
1000R
3-134
2.0
V
Data retention mode
50
200
JlA
Normal operation, R = 270 ko ±2%,
C =33 pF ±5%
30
100
JlA
Normal operation, VOO = 2.2 V;
R= 270 kO ±2%, C = 33 pF ±5%
0.3
10
JlA
Stop mode, X1
0.2
10
JlA
Stop mode, X1 = 0 V; VOO = 2.2 V
0.2
10
JlA
Data retention mode, VOOOR = 2.0 V
=0V
NEe
J.lPD7507S
AC Characteristics
=
For VDD 2.7 to
T A = -10 to +70°C
6.0 Volts
Limits
Test
Conditions
Parameter
Symbol
Min
Typ
Max
Unit
System clock frequency
fcc
150
200
240
kHz
Voo
75
100
120
kHz
Voo
fc
System clock rise and fall
time
tCR, tCF
System clock pulse width
tCH, tCl
Counter clock frequency
!
10
125
kHz
CL 1, external clock, 50% duty; Voo = 2.7 V
0.2
ps
CL 1, external clock
1.2
50
ps
CL 1, external clock; Voo = 4.5 to 6.0 V
4.0
50
ps
CL 1, external clock; Voo
50
kHz
X1, X2, crystal oscillator
32
= 4.5 to
= 2.7 V
kHz
X1, external pulse input, 50% duty;
Voo = 4.5 to 6.0 V
0
125
kHz
X1, external pulse input, 50% duty;
Voo = 2.7 V
0.2
ps
X1, external pulse input
X1, external pulse input; Voo = 4.5 to 6.0 V
tKH, tKl
t
CL 1, external clock, 50% duty; Voo
6.0 V
410
tKCY
SO delay time after SCK
R = 160 kn ±2% (Note 1)
kHz
0
tXH, tXl
SI hold time after SCK
kHz
410
fxx
Counter clock pulse width
SI setup time to SCK f
135
10
fx
tXR, tXF
SCK pulse width
75
20
Counter clock rise and fall
time
SCK cycle time
= 5 V ±10%; R =82 kn ±2% (Note 1)
= 3 V ±10%; R =160 kn ±2% (Note 1)
1.2
ps
4.0
ps
X1, external pulse input; Voo
3.0
ps
SCK as input; Voo = 4.5 to 6.0 V
4.9
ps
SCK as output; Voo
8.0
ps
SCK as input
16.0
ps
SCK as output
1.3
ps
SCK as input; Voo = 4.5 to 6.0 V
2.2
ps
SCK as output; Voo
4.0
ps
SCK as input
SCK as output
8.0
ps
tSIK
300
ns
tKSI
450
tKSO
I
= 2.7 V
=4.5 to 6.0 V
=4.5 to 6.0 V
ns
850
ns
1200
ns
INTO pulse width
tlOH, tlOl
10
ps
INT1 pulse width
t11H, tl1l
2/f
ps
RESET pulse width
tRSH, tRSl
10
ps
RESET setup time
tSRS
0
ns
RESET hold time
tHRS
0
ns
Voo
= 4.5 V to 6.0 V
Note:
(1) RC network at CL 1 and CL2; C = 33 pF ±5%,I~C/Ocl~ 60 ppm.
3-135
NEe
IJPD7507S
AC Characteristics (cont)
For Voo
= 2.2 to 3.3 V
TA = -10to +70°C
Limits
Test
Conditions
Parameter
Symbol
Min
Typ
Max
System clock frequency
fcc
40
60
70
kHz
R= 240 kn ±2% (Note 1)
43
55
65
kHz
Voo = 2.2 V; R = 240 kn ±2% (Note 1)
80
kHz
CL 1, external clock, 50% duty
0.2
J1S
CL 1, external clock
fc
System clock rise and fall
time
10
tCR, tCF
System clock pulse width
tCH, tCl
6.1
Counter clock frequency
fxx
20
fx
0
Counter clock rise and fall
time
tXR, tXF
32
Unit
50
J1S
CL 1, external clock
50
kHz
X1, X2, crystal oscillator
80
kHz
X1, external pulse input, 50% duty
0.2
J1S
X1, external pulse input
Counter clock pulse width
tXH, tXl
6.1
J1S
X1, external pulse input
SCK cycle time
tKCY
12.5
J1S
SCK as input
25
J1s
SCK as output
SCK pulse width
tKH, tKl
6.5
J1S
SCK as input
11.5
J1S
SCK as output
1
J1S
SI setup time to SCK
t
tSIK
SI hold time after SCKt
SO delay time after SCK
INTO pulse width
tKSI
!
J1S
tKSO
J1s
tlOH, tlOl
30
J1S
INT1 pulse width
t11H, tl1l
2/f
J1S
RESET pulse width
tRSH, tRSl
30
J1s
RESET setup time
tSRS
0
ns
RESET hold time
tHRS
0
ns
Note:
(1) RC network at CL 1 and CL2; C = 33 pF ±5%,I.6.C/ocl::::: 60 ppm.
Recommended Rand C Values for System
Clock Oscillation Circuit
TA
= -10 to +70°C
Supply
Voltage Range
Recommended
Values (Note 1)
Frequency Range
4.5 to 6.0 V
R=82kn±2%
150 to 250 kHz,
200 kHz typical
2.7 to 3.3 V
R =160 kn ±2%
75 to 120 kHz,
100 kHz typical
2.7 to 6.0 V
R =160 kn± 2%
75 to 135 kHz
2.2 to 3.3 V
R ='= 270 kn ±2%
40 to 70 kHz
2.2V
R = 270 kn ±2 %
43 to 65 kHz
Note:
(1) C = 33 pF ±5%,I.6.C/ocl::::: 60 ppm.
3-136
NEe
JJPD7507S
Timing Waveforms
External Interrupts
Timing Test Points
Voo
=X
= 2.7 to 6.0 V
0.7VOO
O.7V00X=
Test Points
~O~.3~V~o~o~______________~O.~3~V~oO
Voo
= 2.5 to 2.7 V
,,,,~,,o'=r='~"~
'Nft
~O.8VOO
O.8VooV
~~O~.2~V~o~o______Th_s_t_p_oi_nt_s_____O~.2~VO~of~
83-003314A
~'"'=r'""~
83-003317A
RESET
Clocks
83-003318A
I:
CL1
Data Retention Mode
Data Retention Mode
X1
Voo
RESET
Serial Interface
VOOOR
VIHOR
83-003319A
SI ----I--------.......f
so
Valid Output Data
)(
'-----83-003316A
3-137
NEe
/JPD7507S
Operating
Ch aracteristics
TA = 250C
Ie vs VOD
S
4
4
5
Supply Voltage Voo [V]
upply Voltage Voo [V]
1000
4
Resistance R [kO]
25
Operating Tem perature TA [Oe]
3-138
Supply Voltage Voo [V]
75
4
5
Supply Voltage Voo [V]
NEe
JAPD7507S
Operating Characteristics (cont)
TA
= 25°C
1001 vs
fcc
IOH vs VOH
-6
500
<'
.:;,
C
"8"
:::E
r
<'
E.
~
J
400
E
300
33pF
E -4
c:
~
R
U
!!
&.
S
0
U
~
-3
::I
0 200
c:
~
,.,
-5
:I:
100
'~"
g
rJ)
!
__~--------~VDD=3V
-2
l: -1
9
0
g
0
100
50
150
200
300
250
High-Level Output Voltage VOH [V]
System Clock Oscillation Frequency fCC [kHz]
1001 vs TA
IOL vs VOL
20
500
<'
.:;,
C
..."
°
:::E
g'
!
x.
0
<:
<'
E.
....
E
400
E
300
200
r-r--
§
33pF
u,..
-
~
J
...
::I
::I
0
___- - - - , VDD = 3 V
10
___- t - - - VDD = 2.5 V
S
R
~
g.
VDD = 3 V, R = 160 kCl
rJ)
o
§
U
VDD = 5 V. R = 82 kCl
'a 100
-25
15
c:
'::}"
J
25
Operating Temperature T A [OC]
50
!l
g
9
g
75
Low-Level Output Voltage VOL [V]
3-139
J-lPD7507S
-3-140
NEe
pPD7508A
4-BIT, SINGLE-CHIP
CMOS MICROCOMPUTE'R
WITH Flp® DRIVER
t-IEC
NEe Electronics Inc.
Description
Pin Configuration
The tlPD7508A 4-bit, single-chip CMOS microcomputer has advanced fourth-generation architecture. It is identical to the tlPD7508 except for a smaller
RAM and 16 lines of vacuum fluorescent display FIP
drive capability. It contains a 4096 x 8-bit ROM and a
208 x 4-bit RAM.
vss
P43
P42
P41
P40
P53
The tlPD7508A contains four 4-bit general purpose
registers outside RAM. The subroutine stack is implemented in RAM for greater nesting depth and flexibility.
The tlPD7508A executes 92 instructions of the tlPD7500
series instruction set A with a 10-tls cycle time.
The tlPD7508A has two external and two internal edgetriggered hardware vectored interrupts. It also contains
an 8-bit timer/event counter and an 8-bit serial interface
to reduce software requirements. Ports 3-6 can be
pulled to -35 V to drive vacuum fluorescent displays.
CMOS technology allows the use of a single 2.7 V to 6.0
V power supply with a maximum current consumption
of 900 tlA. This is even lower in the HALT and STOP
standby modes.
P63
P62
P61
P60
PO31'S I
paz/so
P01/SCK
POoIlNTO
CL1
voo
83-OO2989A
Pin Identification
Symbol
No.
Features
o Single-chip microcomputer
o Executes 92 instructions of tlPD7500 instruction set A
o Instruction cycle:
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
- 10 tls/200 kHz (5 V internal)
- 5 tls/400 kHz (5 V external)
4096 x 8-bit program ROM
208 x 4-bit data RAM
Interrupt capabilities
- Two external interrupts: INTO, INT1
- Two internal interrupts: INTT, INTS
8-bit timer/event counter
8-bit serial interface
Two standby modes
Data retention mode
32 I/O lines
Four high-voltage (40 V) ports
Two high-current (8 rnA) ports
Internal RC oscillation circuitry
Crystal oscillation circuitry for count clock
Low power consumption
Single 2.7 to 6.0 V operating voltage
CMOS technology
-....---~
Function
1,40
X2, X1
Crystal clock/external event input port
2-5
P2o/PSTB
P21/PTOUT,
P22, P23
Output port 2/output strobe pulse,
timer out F/F signal
6-9
P1o-P13
I/O port 1
10-13
P30-P33
Output port 3
14-17
P7o-P73
I/O port 7
18 '
RESET
RESET input
19,21
CL1, CL2
System clock inputs
20
Voo
Positive power supply
22
INT1
External interrupt
23-26
POo/INTO,
P01/SCK,
P02/S0
P03/S1
Input port 0/
external interrupt,
serial I/O interface
27-30
P6o-P63
I/O port 6
31-34
P50-P53
I/O port 5
35-38
P43-P40
110 port 4
39
VSS
Ground
FIP is the registered trademark for NEC's fluorescent indicator panel
(vacuum fluorescent display).
Ordering Information
Part No.
pPD7508AC
Package Type
Max Frequency
of Operation
40-pin plastic DIP
400 kHz
3-141
NEe
pPD7508A
Pin Functions
POO/INTO, P01/SCK, [Port O/External Interrupt,
Serial Interface] P02/S0, P03/S1
4-bit input port/serial 110 interface. This port can be
configured as a 4-bit parallel input port or as the 8-bit
serial I/O interface under control of the serial-mode
select register. The serial input SI, serial output SO
(active low), and the serial clock SCK (active low) used
for synchronizing data transfer make Lip the 8-bit serial·
I/O interface. Line POo is always shared with external
interrupt I NTO, a rising edge-triggered interrupt. If
POo/INTO is unused, it should be connected to Vss. If
P01/SCK, P02/S0, or P03/S1 are unused, connect them
to Vss or Voo·
P10·P13 [Port 1]
4-bit input/three-state output port. Data output to port 1
is strobed in synchronization with a P2o/PSTB pulse.
Connect unused pins to Vss or Voo.
P20/PSTB, P21/PTOUT, P22, P23 [Port 2]
4-bit latched three-state output port. Line P20 is shared
with PSTB, the port 1 output strobe pulse. Line P21 is
shared with PTOUT, the timer out F/F signal. Leave
unused pins open.
P30·P33 [Port 3]
4-bit latched three-state output port. Leave unused pins
open.
P40-P43 [Port 4]
4-bit latched three-state output port. Can also perform
8-bit parallel I/O with port 5. In input mode, connect
unused pins to Voo or GND. In output mode, leave
unused pins open.
P63-P60 [Port 6]
4-bit input/latched three-state output port. The port 6
mode select register configures individual lines as
inputs or outputs. In input mode, connect unused pins
to Vss orVoo.ln output mode,leave unused pins open.
P70-P73 [Port 7]
4-bit input/latched three-state output ·port. In input
mode, connect unused pins to Vss or Voo. In output
mode, leave unused pins open.
X2, X1 [Crystal Clock/External Event Input]
For crystal clock operation, connect a crystal oscillator
circuit to input X1 and output X2. For external event
counting, input external event pulses to input X1 while
leaving output X2 open. If X1 is not used, leave it open.
If X2 is not used, connect it to ground.
CL 1, CL2 [System Clock Input]
Connect an 82 kO resistor across CL1 and CL2, and
connect a 33 pF capacitor from CL1 to Vss (200 kHz).
Alternatively, connect an external clock source to CL 1
and leave CL2 open. If CL 1 is not used, connect it to
Vss·
RESET [Reset]
A high level input to this pin initializes the pPD7508A
after power up.
INT1 [Interrupt 1]
External rising edge-triggered interrupt. Connect to
Vss if unused.
Voo [Power Supply]
Positive power supply. Apply a single voltage in the
range 2.7 to 6.0 V for proper operation.
P53-P50 [Port 5]
4-bit input/latched three-state output port. This port
also performs 8-bit parallel I/O with port 4. In input
mode, connect unused pins to Vss or VOD. In output
mode, leave unused pins open.
3-142
Vss [Ground]
Ground.
NEe
pPD7508A
Block Diagram
P03/SI
P02/S0
P01/SCK
General Registers
Program Memory
4096 x 8-Blt ROM
CL
Instruction
Decoder
o [4J
E [4J
H [4J
L [4J
Stack Pointer
Data Memory
208 x 4-BII RAM
t/>
) ) )
CL1
CL2
RESET
VOO
VSS
83-002990C
Functional Description
Program Memory
Figure 1.
Program Memory Map
Address
[DeclmalJ
Figure 1 is a map of the 4096 x a-bit program ROM_
Address
[HEXJ
MSB
LSB
OOOH
RESET Pulse vectors program
execution to address ~OH.
16
010H
INTT [Internal Timer/Event
Counter InterruptJ vectors
program execullon to address
010H.
32
020H
INTS or INTO vectors program
execution to address 020H.
48
030H
INT1 [External Interrupt 1J
veclors program execution
to address D30H.
o
716151413121110
~
192
207
208
255
OCOH} LHLT Instruction
Reference Table
OCFH
ODOH } CALT Instruction
Reference Table
OFFH
,~,II==========II"'"
4095T
Lasl address for
CALL instruction
entry of the
pPD7508A
TFFFH
83·0029918
3-143
NEe
pPD7508A
Clock Control Circuit
The clock control circuit (figure 2) consists of a 4-bit
clock mode register (bits CM1 and CM2), prescalers 1,
2, and 3, and a multiplexer. It takes the output of the
system clock generator (CL) and count clock generator
circuit (I). It also selects the clock source and divides
the signal according to the setting in the clock mode
register. It outputs the count pulse (CP) to the
timer/event counter.
Table 1 lists the codes set in the clock mode register by
the OP or OPL instruction to specify the count pulse
frequency. Bit CM3 controls the timer out F/F; it is
disabled when the bit is 0 and output when the bit is 1.
When you set the clock mode register with the OP or
OPL instruction, clear the high-order two bits of the
accumulator.
Table 1.
Selecting the Count Pulse Frequency
CMZ
CMl
CMo
0
0
0
0
0
CLl256
X/64
0
0
Frequency Selected
0
X
0
CLl32
1
X
0
X/8
0
0
Not used
Not used
CM3
Timer F/F Signal
o
Enabled
Disabled
Figure 2.
Clock Control Circuit
>-----CP
Crystal Clock Oscillatorl
Event Counter Input
·Command Execution
83-oo2992B
3-144
NEe
pPD7508A
Timer/Event Counter
The timer/event counter consists of an a-bit counter,
an a-bit modulo register, an a-bit comparator, and a
timer out flip flop, as shown in figure 3.
The a-bit count register is a binary a-bit up counter
which is incremented each time a count pulse is input.
The TIMER instruction, a RESET signal, or an INTT
coincidence signal clears it to OOH.
The a-bit modulo register determines the number of
counts the count register holds. The TAMMOD
instruction loads the contents of the modulo register.
RESET sets the modulo register to FFH.
The a-bit comparator compares the contents of the
count register and those of the modulo register and
outputs an INTT when they are equal.
Figure 3.
Timer/Event Counter
Internal Bus
~-~-------,
·TCNTAM
,---------~
-------------+\
1-------- :~T:.erruPt Circuit
1--+---- ~~u;erlal
·Command Execution
Clock
MSR
·Timer
Bit-3
Interface)
PTOUT
to pin 3
RESET
83-0030138
3-145
NEe
pPD7508A
Serial Interface
The 8-bit serial interface allows the pPD7508A to
communicate with peripheral devices such as the
pPD7001 A/D converter, the pPD7227 dot matrix LCD
controller/driver, and other microprocessors or microcomputers. Figure 4 shows the serial interface.
The serial interface consists of an 8-bit shift register, a
3-bit SCK pulse counter, the SI input port, the SO
output port, the SCK serial clock I/O port, and a 4-bit
serial mode select register (MSR). The MSR selects
serial I/O or port 0 operation.
Figure 4.
Serial Interface
P03lSI ~------I :>-~H--~
P02/S0
o - - - -........-----t-r-.-c:: 1 - - - - - - - - - - 1 1 - - - - - - - - - - - - - '
'---....JC>--f-- TOUT
POollNTO 0 - - - - - - - - - - 1
RS F/F
R
• Command Execution
System Clock
q,
t--.---. ~oT~nterruPt Circuit)
5 1 - - - - - - ·510
83-oo3014B
3-146
NEe
Interrupts
Table 2.
The pPD7508A has four vectored, prioritized interrupts.
Two of these interrupts, INTT and INTS, are internally
generated from the timer/event counter and serial
interface, respectively. INTO and INT1 are externally
generated. Table 2 is a summary of the four interrupts.
Figure 5 is a block diagram of the interrupts.
Figure 5.
pPD7508A
pPD 7508A .Interrupts
Function
Location
INTT
Coincidence in
timer / event counter
Internal
INTS
Transfer complete
signal from serial
interface
Internal
Source
Priority
ROM Vector
Address
10H
2
20H
INTO
INTO pin
External
2
20H
INT1
INT1 pin
External
3
30H
Interrupt Block Diagram
INTlo---I---.==::-:-:-----I
INTS
POO/INTO o---If--L~
SIO'
INTT--------~
'Command Instruction
Standby
Release
83·0034246
3-147
,NEe
pPD7508A
System Clock and Timing Circuitry
Figure 6.
TimingforthepPD7508A is internally generated except
for a frequency reference, which can be an RC circuit
or an external clock source. Connect the frequency
reference to the on-Chip oscillator for the feedback
phase shift required for oscillation. Figure 6 shows the
connection for an RC circuit. Figures 6 and 7 show the
connection for the frequency reference.
RC Circuit Frequency Reference
Vss()-H-~ CL1
'---- CL2
83-002994A
The internal oscillator 'generates a frequency in the
range 60 kHz to 300 kHz depending on the frequency
reference. For example, at Voo = 5 V, an 83 kO resistor
and a 33 pF capacitor generate a frequency of 200 kHz.
The oscillation frequency is fed to the clock control
circuit. It is divided by two and the resulting signal is
fed to the CPU and serial interface as shown in figure 8.
Figure 7.
External Clock Frequency Reference
E
xternal=LL1
Source
Table 3 shows the operating status of the various logiC
blocks under the three 'power down modes.
Open
CL2
83-002995A
Figure 8.
Sy,tem Clock Circuitry
X1
INTl
'X2
CL1
INTS
CL2
Standby Release
___~---vRESET
83-0029969
3-148
NEe
Table 3.
pPD7508A
Absolute Maximum Ratings
Power Down Operating Status
TA = 25°C
Power Down Mode
Logic Block
HALT
STOP
Data Retention
Operating temperature, TOPT
System clock
(1)
Disabled
Disabled
Storage temperature, TSTG
-65 to 150°C
X2
Normal
Normal
Disabled
Power supply voltage, VDD
-0.3 to +7.0 V
CPU
Disabled
Disabled
Disabled
RAM
Data retained
Data retained
Data retained
Input voltage, VI
Except ports 4-6
Ports 4-6
-0.3 to VDD + 0.3 V
VDD - 40 to VDD + 0.3 V
Internal registers
Data retained
Data retained
Data retained
Ti mer I event
counter
Normal
(3)
Disabled
Output voltage, Vo
Except ports 3-6
Ports 3-6
-0.3 to VDD + 0.3 V
VDD - 40 to VDD + 0.3 V
Serial interface
(2)
(2)
Disabled
INTO
Normal
Normal
Disabled
INT1
Normal
Disabled
Disabled
RESET
Normal
Normal
(4)
Note:
(1) Supplied to timer/event counter but not to CPU or serial
interface.
(2) Can function normally if the serial MSR is set to get the SCK
signal externally or from the TOUT signal.
(3) Can function normally if the clock MSR is set to use X1 as the
source for the count pulse.
(4) You must raise RESET while VDD is lowered to enter data
retention mode. Raise RESET when VDD is raised, then lower it to
end the data retention mode. INTT, INTO, INTS or RESET
releases STOP mode. RESET or any interrupt releases HALT
mode.
Output current, high, IOH
Single port, one pin except ports 3-6
Single port, one pin ports 3-6
All port pins
-17 mA
-30mA
-150 mA
Output current, low, IOL
One pin
All port pins
17 mA
50 mA
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Capacitance
TA=25°C,VDD=OV
Limits
Parameter
Symbol
Min
Typ
Max
Unit
pF
Test
Conditions
Input capacitance
CI
15
Output capacitance
Co
15
pF Except port 3
Co
35
pF Port 3
CIO
15
pF Except ports
4-6
CIO
35
pF Ports 4-6
1/0 capacitance
3-149
Il
NEe
pPD7508A
DC Characteristics
TA =-10 to +70°C,
voo = 2.7 to 5.5 V
limits
Parameter
Input voltage, high
Input voltage, low
Output voltage, high
Symbol
Min
Typ
Max
Unit
Test
Conditions
VIH1
0.7 Voo
Voo
V
Except CL 1, X1, ports 4-6
VIH2
Voo - 0.5
Voo
V
CL1, X1
VIH3
0.7 Voo
Voo
V
Ports 4-6; Voo = 4.5 to 5.5 V
VIH3
Voo - 0.5
Voo
V
Ports 4-6; Voo = 3 to 4.5 V
VIH3
2.5
Voo
V
Ports 4-6; Voo = 2.7 to 3 V
VIHOR
0.9 VOOOR
VOOOR +0.2
V
RESET, data retention mode
0
0.3 Voo
V
Except CL 1, X1, ports 4-6
VIL1
VIL2
0
0.5
V
CL1, X1
VIL3
Voo - 35
0.3 Voo
V
Ports 4-6
VOH
Voo -1.0
V
Except ports 3,6; 10H = 1.0 mA,
Voo = 4.5 to 5.5 V
VOH
Voo - 2.0
V
Ports 3, 6; 10H = -8.0 mA;
Voo = 4.5 to 5.5 V
VOH
Voo - 0.5
V
10H = -100 pA;
Voo = 2.7 to 5.5 V
VOL
0.4
V
Except ports 3, 6; 10L =1.6 mA,
Voo = 4.5 to 5.5 V
VOL
0.5
V
Except ports 3, 6; 10L = 400 pA;
Voo = 2.7 to 5.5 V
ILlH1
3
pA
Except CL 1, X1, ports 4-6;
VI = Voo
ILlH2
10
pA
CL 1, X1; VI = Voo
ILlH3
60
pA
Ports 4-6; VI = Voo
ILlL1
-3
pA
Except CL 1, X1, ports 4-6;
VI =OV
ILlL2
-10
pA
CL1,X1;VI=OV
ILlL3
-30
pA
Ports 4-6; VI = Voo - 35 V
ILOH1
3
pA
Vo == Voo
Except ports 4-6
ILOH2
30
pA
Ports 4-6; Vo = Voo
Output leakage current,
low
ILOL1
-3
pA
Vo =OV
-30
pA
Ports 3-6; Vo = Voo - 35 V
Supply voltage
VOOOR
Supply current
1001
300
900
pA
Normal operation, Voo =
5 V ±10%; R = 82 kn ±2%,
C= 33 pF ±5%
1001
70
300
pA
Normal operation, Voo =
3 V ±10%; R = 160 kn ±2%,
C=33 pF ±5%
Output voltage, low
Input leakage current,
high
Input leakage current,
low
Output leakage current,
high
ILOL2
2.0
V
20
pA
Stop mode, Voo = 5 V ±10% (1)
1002
0.3
10
pA
Stop mode, Voo = 3 V ±10% (1)
1000R
0.3
10
pA
Data retention mode
VOOOR = 2.0 V
1002
Note:
(1) X1 = 0 V; ports 4-6 output disabled or low level input.
3-150
Data retention mode
t-IEC
pPD7508A
AC Characteristics
= -10 to 70°C, Voo = 2.7 to 5.5 V
TA
Limits
Test
Conditions
Parameter
Symbol
Min
Typ
Max
Unit
System clock frequency
fcc
150
200
240
kHz
CL 1, CL2, RC clock, R = 82 kn ±2%;
C = 33 pF ±5% Voo = 5 V ±10%,
I t.C/ °C I :s: 60 ppm
fcc
75
100
120
kHz
CL 1, CL2, RC clock, R = 160 kn ±2%; C =
33 pF ± 5% Voo = 3 V ±10%,1 t.C/ °C I :s:
60 ppm
fcC
75
135
kHz
CL 1, CL2, RC clock, R = 160 kn ±2%;
C = 33 pF ±5% I t.C/ °C I :s: 60 ppm
fC
10
410
kHz
CL 1, external clock, 50% duty,
Voo = 4.5 to 5.5 V
fC
10
125
kHz
CL1, external clock, 50% duty,
Voo = 2.7 V
0.2
/.IS
CL 1, external clock
System clock rise and
fall times
tCR, tCF
System clock pulse width
tCH, tCl
1.1
50
/.IS
CL 1, external clock, Voo
tCH, tCl
3.5
50
/.IS
CL 1, external clock, Voo
fxx
25
50
kHz
X1, X2, crystal oscillator
fx
0
410
kHz
X1, external pulse input
50% duty, Voo = 4.5 to 6.0 V
fx
135
kHz
X1, external pulse input
50% duty, Voo = 2.7 V
Counter clock rise and
fall times
tXR, tXF
0.2
/.IS
X1, external pulse input
Counter clock pulse width
tXH, tXl
1.1
/.IS
X1, external pulse input, Voo = 4.5 to 5.5 V
tXH, tXl
3.5
/.IS
X1, external pulse input, Voo = 2.7 V
Port 1 output setup
time to PSTB t
tpST
(1)
/.IS
Voo = 4.5 to 5.5 V
tpST
(2)
/.IS
Port 1 output hold
time from PSTB high
tSTP
0.1
/.IS
tSTP
0.1
/.IS
PSTB low pulse width
tSTL
(1)
/.IS
tSTl
(2)
/.IS
tKCY
3.0
/.IS
SCK as input, Voo = 4.5 to 5.5 V
tKCY
5.0
/.IS
SCK as output, Von
tKCY
7.0
/.IS
SCK as input
Counter clock
frequency
SCK cycle time
SCK pulse width
32
Voo
= 4.5 to 5.5 V
Voo
= 4.5 to 5.5 V
= 4.5 to 5.5 V
= 2.7 V
= 4.5 to 5.5 V
tKCY
14.0
/.IS
SCK as output
tKH, tKl
1.3
/.IS
SCK as input, Voo = 4.5 to 5.5 V
tKH, tKl
2.2
/.IS
SCK as output, Von
tKH, tKl
3.3
/.IS
SCK as input
tKH, tKL
6.5
/.IS
SCK as output
= 4.5 to 5.5 V
3-151
I]
NEe
pPD7508A
AC Characteristics (cont)
Limits
Parameter
Symbol
Sisetup time to SCK high
tSIK
0.3
tKSI
0.45
SI hold time'idter SCK high
Min
Typ
Max
Unit
JiS
JiS
tSKO
0.85
JiS
tSKO
1.2
JiS
SO delay time after
SCKlow
INTO pulse width
tlOH
10
JiS
tlDL
10
Jis
tl1H
(3)
JiS
tl1L
(3)
JiS
tRSH
10
JiS
tRSL
10
JiS
INT1 pulse width
RESET pulse width
RESET high set up time
,tSRS
RESET high hold time
tHRS
Note:
(1) fCC/2 - 0.8 or fC/2 - 0.8
(2) fCC/2 - 0.3 or fC/2 - 0.2
(3) 2/fCC or 2/fC
3-152
ns
0
Test
Conditions
ns
VDD = 4.5 to 6.0 V
NEe
pPD7508A
Timing Waveforms
Timing Test Points
External Interrupts
O.7VDD~
---V-0.7VDD
~~O~.3~V~D~D________________O~.3~VD~O~
"w
83-003411A
Clocks
CL11nput
i='' =j[=,e'=i
tCR
X11nput
i=
--c"o'=r="o,~
"" --C"'=V="'"~
83-003317A
RESET
tCF
tXL~11f~tXH~%
83-003318A
._ _
tXR
tXF
Data Retention Mode
83-003412A
Data Retention Mode
Serial Interface
VOO
RESET
VDOOR
VIHOR
83-003319A
51
----+--------.f
so
Valid Output Data
83-003316A
Output Strobe
83·003414A
3-153
NEe
JlPDT508A
Operating Characteristics
f vs R
100 VS VOO [HALT Mode]
500
200
N
2~
c
E
i
~
!
§
100
50
~
~C
0
c
S
0
~
i0
100
~
200
50
~
Q,
§'
1/1
20
1= 33pF
C=33 PF
«
8
1
ot....0
50
200
100
10
~
500
~
Resistance, R [kO]
Supply Voltage, Voo [V]
fCC vs VOO
250
Ii 20
2-
I
or,
()
~
100 vs VOO [STOP Mode]
I
30
IC=33 PF
..
R=82kO
20
~
2
c
r;
150
.§
100
I
i
E
i
10
§
R= 160kO
0
>ii.
.....
R1
§'
i
o
1/1
;!i
~
50
gj
2
Supply Voltage, VOO [V]
3-154
Porls4-6
Output
1
R1 = 330 kO
C1 =20pF
C2 = 30 pF
C1 ;,;
Xtal = 32.768 kHz
2
Supply Current, VOO [V]
;,;C2
~
i
NEe
NEe Electronics Inc.
Description
The JIPD7514 is a 4-bit single-chip microcomputer with a
4-bit ALU, a 4K x B-bit program memory (ROM), a
256 x 4-bit data memory (RAM), an B-bit serial interface,
a programmable B-bit timer/event counter, an LCD
controller/driver, and 31 general purpose 110 lines.
The LCD controller/ driver supervises all of the timing required by 32 segment drivers and 4 common drivers, for
biplexedltriplexed LCD (1/2 bias method) or triplexed/
quadriplexed LCD (113 bias method).
The instruction set includes transfer and increment!
decrement instructions to directly address memory,
memory bit manipulation instructions, test instructions
for bit test and data comparison, memory reference instructions with automatic register increment!
decrement functions, table look-up instructions, load
instructions with a string effect, and multi-branch instructions.
The /iPD7514 allows the organization of any system with
the least additional circuitry. It is suited for the following applications:
•
•
•
•
•
•
J.(PD7514
4.BIT, SINGLE·CHIP
CMOS MICROCOMPUTER WITH
LCD CONTROLLER/DRIVER
o
110 ports
- 4-bit input port (POOIINTO, P01/SCK, P02/S0,
P03/SI)
- Strobed 4-bit 110 port (P10-P13)
- 3-bit output port (P20/PSTB, P21/PTOUT, P22)
- 4-bit output port (P3o-P33)
- 4-bit 110 ports (P40-P43, P50-P53, P60-P63,
P70-P73)
DOn-chip RC oscillator for system clock
o Crystal oscillator input pins
o CMOS technology
o low power consumption
o Single power supply (2.7V to 6.0Y)
Ordering Information
Part No.
pPD7514G-12
Package Type
Max Frequency
of Operation
aD-pin plastic miniflat
500 kHz
Pin Configuration
'Telephones
Personal radio equipment
Automobile equipment (electric)
High-grade electronic calculators
Electron ic games
VCRs
Features
o
o
o
92 powerful instructions
Instruction cycle 5/is at 400 kHz, 5 V
Interrupts
- 2 external: INTO, INn
- 2 internal: INIT (timer/event counter)
INTS (serial interface)
o Programmable B-bit timer/event counter
- Time base count operation
- External event count operation
DB-bit serial interface (three serial clocks)
o LCD controller/driver
- Static method
- Biplexed/triplexed LCD (1/2 bias method)
- Triplexed/quadriplexed LCD (113 bias method)
- Common outputs (strobe): 4 lines (COMo-COM3)
- Segment outputs (data): 32 lines (SO-S31)
o Standby operation
- Stop and halt modes
83,OO2914A
3-155
NEe
JAPD7514.
Pin Functions
Pin Identification
No.
Symbol
1,2,79,80
P40-P43
I/O port 4
3,4
X1, X2
Crystal clock
5-7
VLC1-VLC3
LCD bias voltage input
8-11
COMo-COM3
LCD common output
12-22, 24-32, SO-S31
34-41, 43-46
Function
LCD segment output
33
Voo
Power supply positive
47
INT1
External interrupt input
48
RESET
Reset input
49,50
CL1, CL2
System clock
51-54
P70-P73
I/O port 7.
55
56
57
P22
P21/PTOUT
P20/PSTB
3-bit output port 2. PTOUT is the timer
F/ Foutput. PSTB is the strobe output.
58-61
P10-P13
I/O port 1
62,63,65,66 P30-P33
I/O port 3
64
VSS
Ground
67
68
69
70
P03/S1
4-bit input port O. Serial input. Serial
output. Serial clock I/O. Interrupt
request input.
71-74
P60-P63
I/O port 6
75-78
P50,..P53
I/O port 5
P02/~
P01/SCK
POolINTO
Status of Unused Pins
Name
Pin Connection
POO-P03 (Port 0)
This is the 4·bit input port O. The pins also operate as the
interrupt input (INTO/POO), serial clock I/O (SCK/P01),
and serial data output (SO/P02) and input (SI/P03).
P10- P13 (Port 1)
This is the 4·bit I/O port 1. Data on these lines is loaded
into the accumulator. by execution of a port input in·
struction (IP, IP1, IPL). The contents of the accumulator
are output by the execution of a port output instruction
(OP, OPL). Port 1 does 'not have an output latch. When a
port output instruction is executed, the strobe signal,
which·is used for latching output data externally, is au·
tomatically output from PSTB. ThePSTB signal is suit·
able for data output to memory or peripheral circuits
requiring write strobe signals. Port 1 is usually held high
impedance, and is driven for output with a port output
instruction.
P20-P22 (Port 2)
. This is the three"state 3·bit latched output port 2. Follow·
ing RESET, these pins become high impedance.
When port 1 is outputting data, P20 operates as the write
strobe output (P20/ PSTB). P21 is the output (P21/ PTOUT)
for the timer flip·flop signal (TOUT) ..
P30-P33 (Port 3)
This is the 4·bit latched output port 3. On RESET, the
contents of the output latches become undefined and
the output goes high impedance.
CL2
Open
X1
Vss
X2
Open
P40-P43 (Port 4), P50-P53 (Port 5)
INT1
POolINTO
Vss
P01/SCK
P02/S0
P03/S1
P10-P13
Vss orVoo
Ports 4 and 5 are both 4·bit latched I ports. Ports 5 and
4 can be treated as a pair, and can input or output 8·bit
data (by an IP54 or OP54 instruction) between the accu·
mulator and memory (addressed by the HL register).
P20/PSTB
P21/PTOUT
P22
P30-P33
Open
P40-P43
P50-P53
P6o-P63
P70-P73
Input mode: Vss or Voo
Output mode: Open
SO-S31
COMo-COM3
VLC1-VLC3
Open
3-156
to
A RESET or input instruction will place these ports in
input mode (high impedance). On RESET, the output
latch contents become undefined.
If data is input to an I/O port just after changing it from
output to input mode, data on the line at the execution
of the first input instruction may be unstable. Accord·
ingly, the first input data just after the modification
should be ignored. Executing the input instruction
again will insure the data is stable.
NEe
JAPD7514
P60-P63 (Port 6)
SO-S31 (Segment)
This is the 4-bit latched 110 port 6. Each line can be set
as an input or output using the port 6 mode register
(PM3-PMO). Port 6 performs data 110 to and from the accumulator in 4-bit units. An output instruction will
cause the output latches to latch the contents of the accumulator. Then the contents of the output latch at the
bit position that the PM R designates as being in the output mode are output from the pins via the output
buffers. The other pins are high impedance (input).
These segment signal outputs directly drive the LCD
segment lines. They are used for biplexed/triplexed
LCD (1/2 bias method) and triplexed/quadriplexed LCD
(1/3 bias method).
P70-P73 (Port 7)
This is the 4-bit latched 110 port 7. An input instruction
reads port data into the accumulator. An output instruction latches and outputs the accumulator contents. A
RESET or input instruction will place port 7 in input
mode (high impedance).
INTO (Interrupt 0)
This input is the rising-edge-triggered external interrupt.
It has a Schmidt-trigger input in order to decrease noise.
Setting bit 3 of the shift mode register (SM3) low level
selects INTS; setting it high selects INTO. INTO can be
used in both stop and halt modes.
INT1 (Interrupt 1)
INT1 is the rising-edge-triggered external interrupt input.
X1, X2 (Crystal Clock)
X1 and X2 are the crystal connection pins for the count
clock generator. An external clock may be input to X1 directly, in which case X2 must be open.
COMO-COM3 (Common)
These outputs directly drive common (backplane) LCD
lines via the following strobe signals:
• 1/2 bias method: biplexed (COMo, COM1), triplexed
(COMo-COM~
• 1/3 bias method: triplexed (COMo-COM2), quadriplexed (COMo-COM3)
VLC1, VLC2, VLC3 (LCD Power Supply)
These pins are the LCD bias voltage supply. Based on
applied voltages to these pins, the on-chip LCD
controller/driver generates segment and common signals to the LCD. The bias voltage configuration for the
1/2 bias method is different from that for the 1/3 bias
method.
RESET
A high level input to this pin resets the /JPD7514.
VDD
Positive power supply.
VSS
Ground.
CL1, CL2 (System Clock)
CL1 and CL2 are the resistor and capacitor connection
pins for the system clock generator. An external clock
may be input to CL1 directly, in which case CL2 must be
open.
3-157
NEe
JAPD7514
Block Diagram
~
~POo-P03
~P1P1
~O-3
P2Q-P22
PSTBIP2Q
PTOUTIP21
P50-P53
Instruction
Decoder
P60-P63
Cl
P70-P73
Cll
Cl2
RESET
VOO Vss
VLC1-VLC3 COMO-COM3
50-531
83.()Q3589C
3-158
NEe
JiPD7514
Absolute Maximum Ratings
DC Characteristics (cont)
TA= -10 0Cto +70 0C, Voo=2.7Vt06V
TA=25°C
Limits
-0.3Vto +7V
Supply voltage, Voo
Symbol
Max
Unit
Test
Conditions
- 0.3 V to Voo +0.3 V
Parameter
Output voltage, Vo
-0.3VtoVoo +0.3V
Common output ReOM
impedance
3
5
15
kQ
Segment output RS
impedance
15
20
kQ
20
60
kQ
Supply current
600
1800
/AA
Operating mode
Voo=5V ±10%;
R=39kQ ±2%;
C=33pF ±5%
70
210
~
Operating mode
Voo=3V ±10%;
R=160kQ ±2%;
C=33pF ±5%
300
900
~
Halt mode
X1=OV;
Voo=5V ±10%;
R=39kQ ±2%;
C=33pF ±5%
35
100
~
Halt mode
X1=OV;
Voo=3V ±10%;
R=160kQ ±2%;
C=33pF ±5%
1.0
20
/AA
Stop mode
X1=OV;
Voo=5V ±10%
0.3
10
~
Stop mode
X1=OV;
Voo=3V ±10%
Max
Unit
Test
Conditions
Output current high, IOH
Per pin
Min
Typ
Input voltage, VI
-5mA
Total, all output ports
-50mA
Output current low, IOL
Per pin
15mA
40mA
Total, Ports 0, 4, 5, 6, P30, P31
1001
40mA
Total, Ports 1,2,7, P32, P33
Operating temperature, TOPT
-10°C to +70°C
- 65°C to + 150°C
Storage temperature, TSTG
Comment: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits described in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
1002
DC Characteristics
TA = -100Cto +70 oC, Voo=2.7Vt06V
Limits
Parameter
Input voltage
high
Input voltage
low
Output voltage
high
Symbol
Min
VIHl
Typ
Test
Conditions
Max
Unit
0. 7V oo
Voo
V
Except X1, CL1,
RES, INTO, INT1,
SI, SCK
VIH2
0. 8V oo
Voo
V
RES, INTO, INT1,
SI, SCK
VIH3
VOO-O.5
Voo
V
X1, CL1
VILl
0
0.3 Voo
V
Except X1, CL1,
RES, INTO, INT1,
SI, SCK
VIL2
0
0. 2V oo
V
RES, INTO, INT1,
SI, SCK
VIL3
0
0.5
V
X1, CL1
Voo-1.0
V
Voo=4.5 to 6.0V;
IOH= -1.0mA
Voo-0.5
V
0.4
V
0.5
V
IOL =400~
3
~
VI=VOO exceptX1,
CL1
VOH
Output voltage
low
VOL
Input leakage
current high
IUHl
kQ
1003
Voo=4.5 to 6.0V
Voo=4.5t06.0V
Capacitance
TA=25°C;Voo=ov
Limits
Parameter
Symbol
Min
Typ
Input
capacitance
CI
15
pF
(Note 1)
IOH= -100/AA
Output
capacitance
Co
15
pF
(Note 1)
Voo=4.5 to 6.0 V;
IOL=1.6mA
I/O capacitance CIO
15
pF
(Note 1)
IUH2
10
/AA
VI=VOO; X1, CL1
Input leakage
current low
IUL1
-3
/AA
VI = 0 V except X1,
CL1
IUL2
-10
~
X1, CL1
Output leakage
current high /
low
ILOH
3
/AA
Vo=Voo
ILOL
-3
/AA
Vo=OV
Note:
(1) fc = 1 MHz. Return unmeasured pins to 0 V.
3-159
E
NEe
IJPD7514
AC Characteristics
TA= -10°C to +70 oc,Voo=3Vto6V
Limits
Parameter
Symbol
System clock
fcc
oscillation (CL1,
CL2)
Min
Typ
Max
Unit
300
400
500
kHz
75
System clock
fc
input frequency
(CL1)
CL1 input rise
time
CL1input fall
time
100
flO(
Count clock
fx
input frequency
(X1)
tSTl
(2)
ns
(3)
JAs
C=33pF ±5%,
lAC / °CI~60 ppm
R=160kQ ±2%,
Voo=3V ±10%
SCK cycle time
tKCY
3.0
/As
Input Voo=4.5 V
t06.0V
Output
150
kHz
Duty=50%
0.2
/AS
/As
50
/As
3.2
50
/AS
0.9
50
0.9
25
32
/AS
50
/As
50
kHz
0
500
kHz
0
150
kHz
tXR
0.2
X1 input fall time tXF
0.2
X1 input rise
time
PSTBpuise
width low
10
3.2
Count clock
oscillation
frequency (X1,
X2)
C=33pF ±5%,
lAC / °CI~60 ppm
R=39kQ ±2%,
Voo=5V ±10%
Voo=4.5Vto
6.0V, Duty=50%
Voo-4.5 V to
6.0V
SCK pulse width tKH
high
SCK pulse width tKl
low
Voo=4.5 V to
6.0V
C1=20pF
C2=30 pF
R=220 kQ
(Note 1)
Voo=4.5 to 6.0V,
Duty =50%
Max
Unit
4.0
/As
/As
Input
13.0
/As
Output
1.3
JAs
Input Voo=4.5 V
to 6.0V
Output
1.8
JAs
3.8
/As
Input
6.3
/As
Output
1.3
/As
Input Voo=4.5 V
to 6.0V
Output
1.8
/As
3.8
JAs
Input
6.3
/As
Output
SI set-up time
(to SCKt)
tSIK
300
ns
SI hold time
(after SCKt)
tKSI
450
ns
850
SO output delay tKSO
time (after
SCK.I-)
/As
INTO pulse
width high
JAS
INTO pulse
width low
1200
ns
ns
tlOH
10
/As
tlOL
10
JAs
/As
Voo=4.5 V to
6.0V
INT1 pulse width tl1H
high
(4)
/AS
3.2
/AS
Voo=2.7V
/As
/AS
Voo=4.5Vto
6.0V
INT1 pulse width tl1l
low
(4)
0.9
10
JAs
/As
Voo=2.7V
RESET pulse
width high
tRSH
3.2
Port 1output set- tpST
up time to
PSTBt
(2)
JAs
Voo=4.5Vto
6.0V
RESET pulse
width low
tRSl
10
/As
(3)
/As
Port10utp~
0.1
JAs
0.1
JAs
tXH
X1 input pulse
width low
tXL
tSTP
hold after PSTB t
Note:
VOO=4.5Vto
6.0V
(1) See recommended clock circuit on next page.
(2) 1/2 fcc - 0.8 or 1/2 fc - 0.8
(3) 1/2 fcc - 2.0 or 1/2 fc - 2.0
(4) 2/fcc or 2/fc
3-160
Voo=4.5V to
6.0V
8.0
0.9
X1 input pulse
width high
Test
Conditions
Min
kHz
0.2
Typ
Symbol
510
tCF
CL1input pulse tCl
width low
kHz
Limits
Parameter
10
tCR
CL1 input pulse tCH
width high
120
Test
Conditions
Voo=4.5Vto
6.0V
t-{EC
J.tPD7514
Timing Waveforms
Recommended Clock Circuit
Data Retention Mode Timing
I'PD7514
X1
X2
VDD-+---4.
R
0
Xtal
C2
J
C1.J
83-002915A
Note:
In data retention mode, all inputs (except RESEll should be made lower level than VDDDR.
83-002918A
AC Timing Test Points
Clock Timing
L
==X0.7VDD> Test ___ 0.7VDD
0.3 VDD
Points - - - 0.3 VDD
1-----1Ifc----~
83-002916C
CL
Input
Data Retention Characteristics
TA = -100Cto +70°C
Limits
Typ
Symbol
Min
Data retention
supply voltage
VDDDR
2.0
Data retention
supply current
IDDDR
Data retention
RESET input
voltage high
VIHDR
RESET set-up
time
tSRS
0
ns
RESET hold time tHRS
o
ns
Parameter
Unit
Test
Conditions
XL
Input
v
0.3
0.9 x
VDDDR
Max
83·002917A
10
VDDDR
+0.2
v
Serial Transfer Timing
SI---01--..(1
SO
Output Data
83-D02919A
3-161
NEe
J-LPD7514
Timing Waveforms (cont)
Program Memory (ROM)
This 4,096·word x a·bit mask-programmable ROM
stores programs and table data and is addressed by the
PC. ROM address locations are from OOOH to FFFH.
Fixed locations are allocated to the RESET and inter·
rupt start addresses, and table areas· of the LH LT and
CALT instructions. See figure 2.
Strobe OutputTiming
P10- P1 3 ---~
PSTB----.
Figure 2. Program Memory Map
83-OO2920A
Interrupt Input Timing
OOOH
RESET Start Address
010H
INTT Start Address
020H
INTO/S Start Address
030H
INTl Start Address
INTO
Subroutine
Entry
~~11--------I1J
Look.up Table of
LHLT Instruction
INT1
Look·up Table of CALT
Instruction (Call Address Table)
~4
RESET Input Timing
FFFH
r
l...______....l
83-003591A
RESET
General Purpose Registers
Program Counter (PC)
Registers D, E, H, and Loperate in units of 4 bits, orthey
form the a·bit pair registers DE, DL, and HL for use as a
data pointer (D or H is the upper·order 4 bits). See
figure 3.
This 12·bit binary counter, shown in figure 1, holds the
address of the current instruction in program memory.
When an instruction executes, the PC increments by the
number of bytes in the instruction. RESET clears the
PC to 0.
Pair register HL can perform the functions of automatic
increment ( +1) and automatic decrement ( -1) for the L
register only. The L register is also used to specify I/O
ports and mode registers when the I/O instruction (OPL,
IPL) is executed.
Figure 1. Program Counter Structure
Figure 3. General·Purpose Register Configuration
Functional Description
0
D
83-OO3590A
Stack Pointer (SP)
This a-bit register (SPrSPo) stores the top address of
the data memory area used as a LIFO stack. The SP decrements when a call (CALL, CALT) or a push (PSHDE,
PSHHL) instruction executes, and at an interrupt generation. It increments when a return (RT, RTS, RTPSW) or
POP (POPDE, POPHL) instruction executes.
3-162
{
H
3
'::==;;::'
1
83-003592A
NEe
J-lPD7514
Data Memory (RAM)
Accumulator (A)
This 256-word x 4-bit static RAM stores processing
data and display data. It also operates with the accumulator to process data in 8-bit units. There are three types
of data memory addressing:
• Direct addressing is made by the second byte of the
instruction.
• Register indirect addressing is made indirectly by the
contents of the register pair designated by an instruction.
• Stack indirect addressing is made by the contents of
the SP.
The accumulator is a 4-bit register. (See figure 6.) Various arithmetic/logical operations are done mainly by
the accumulator. Operating with the data memory addressed by the pair register HL, data processing may be
done in 8-bit units (higher-order bits in the accumulator
and lower-order bits in the data memory).
RAM resides at addresses OOH-FFH. Thirty-two of
these locations (00H-1 FH) are allocated for the LCD display data area. When display data is written to 00H-1 FH,
the LCD controller/driver reads it and generates an LCD
drive signal. Address locations 00H-1FH cannot be
used as stack area. See figure 4.
Data Memory
Direct/Register
Indirect Address
Area
Arithmetic Logic Unit (ALU)
The ALU is a 4-bit arithmetic logic circuit that performs
such processes as binary addition, arithmeticllogical
operation, comparison, and rotation.
Program Status Word (PSW)
Figure 4. Data Memory Map
t
Display Data Area
Figure 6. Accumulator Configuration
(0)
DOH
(31)
lFH
(32)
20H
32x4
256x4
The program status word consists of two skip flags
(SK1, SKo) and a carry flag (C). (See figure 7.) These are
stored in the stack area upon execution of a call instruction (CALL, CALT) or at an interrupt occurrence; they are
restored by an RTPSW instruction. At RESET, SK1 and
SKo are cleared to 0, and C is undefined.
224x4
Figure 7. Structure of Program Status Word
~______~____(~22~~__
FF_H~____~~
83-003593A
Addresses 20H-FFH in data memory can be used as a
stack area at execution of a call or return instruction
(CALL, CALT, RT, RTS, RTPSW), a push/pop instruction
(PSHDE, PSHHL, POPDE, POPHL), or at an interrupt occurrence.
At the execution of a call instruction or an interrupt occurrence, the contents of the PC and PSW are stored in
the stack. At the execution of a push instruction, the
contents of DE or HL are stored in the stack. The data is
stored in the stack as shown in figure 5.
Figure 5. Stack Contents after Call, Interrupt, or Push
Call Instruction,
Interrupt
Push Instruction
Stack
Stack
SP4
PC11-PCa
SP3
PSW
SP2
PC3-PCO
SP2
Eorl
SP1
PC7-PC4
SP1
DorH
83-003594A
3
2
83-003598A
System Clock Generator Circuit
This circuit consists of an RC oscillator circuit and a
half-frequency divider circuit, as shown in figure 8. The
RC oscillator circuit is controlled by an external resistor
(R) and capacitor (C) connected to CL1 and CL2.
An external clock can be input to CL1 without using an
RC circuit. CL2 should be left open, in which case the
RC oscillator circuit merely operates as an inverted
buffer.
In stop mode, the RC oscillator circuit and the halffrequency divider circuit stop, thereby stopping the output of CL and ~, respectively. In halt mode, the
half-frequency divider circuit stops (~), but CL continues
to be supplied.
With an external clock, when the device is in standby
mode, the CL1 input clock becomes CL via an inverted
buffer; CL continues to be supplied. In this case, both
standby modes stop only the half-frequency divider (~).
3-163
NEe
""PD7514
Figure 8. System Clock Generator Circuits
Figure 9. Count Clock Generator Circuits
RC Oscillation
Crystal Oscillation
I'PD7514
I'PD7514
r-------------
r--------
I
III-------<4+1--1
SM3
P02/SO -4------++---<
1----------+--------------'
~_~~---+----~--TOUT
POoIINTO ----I>---4-~_+ INTO
Note:
1. Indicates the Intemal clock signal (System clock).
2. TOUT isthetlmer-out F/Fslgnal.
3. -Indicates the execution of instruction.
4. 5M3 Is to the Interrupt controller.
R
RSF/F
\-------IQ
INTS
S-SIO'
83'()()3602B
3-166
NEe
J.lPD7514
LCD Controller/Driver
Table 2. Maximum Segment Number
This controller/driver directly drives an LCD with static,
1/2 bias voltage (biplexed, triplexed) and 1/3 bias voltage
(triplexed, quadriplexed) configurations. Thirty-two segment lines (SO-S31) and 4 common lines (COMo-COM3)
serve as the LCD driver outputs. See tables 2 and 3, and
figure 14.
Bla,
Multiplexing
COMUne,
Mallmum Segment Number
1/2
biplexed
COMO. 1
64 (32 Segmentsx2 Commons)
1/2
triplexed
COMO. 1. 2
96 (32 Segments x 3 Commons)
1/3
triplexed
COMO. 1. 2
96 (32 Segmentsx3 Commons)
1/3
quadriplexed
COMO. 1. 2. 3 128 (32 Segmentsx4 Commons)
Note:
To supply the proper voltage to the segment and common lines, supply the voltages listed in table 4 to pins
VLC1, VLC2, and VLC3. See also figure 15.
In the following cases, LCD driving waveform stops operation and
DC potential is applied between LCD electrodes. This will considerably reduce the I ife span of the LCD.
LCD Clock Source
Primary Cau..,
CL Channel
o(System Clock)
1. STOP instruction is executed.
2. External clock is stopped.
X Channel
(Count Clock)
1. External clock is stopped.
Table 3. Display Mode Register
CMO=O
DM2
DM3
DMo
Multiplexing
0
Quadriplexed
0
Bias
Voltage
LCDCL
1/3
CL/256
Biplexed
1/2
CL/512
Triplexed
1/3
CLl512
1/2
CL/1024
CLl1536
Triplexed
CLl3072
DM1
DI,play output control
DM1
DI,play output control
0
TO deselect all segments Signal
1
To enable display outs
X192
X256
X/128
X384
X512
X/128
X584
X1512
CL12048
Biplexed
0
CL/1536
Frame
Frequency
X256
X/164
CLl2048
Quadriplexed
0
CL1768
CLl1024
Triplexed
0
LCDCL
CL/1024
Triplexed
0
MCO=1
Frame
Frequency
X/256
X768
Table 4. LCD Supply Voltage
Pin Name
lI21la,
113 Bias
VLC1
Voo-(112) VLCO
Voo-(113) VLCO
VLC2
Voo-(112) VLCO
Voo-(2I3) VLCO
VLC3
VOO-VLCO
VOO-VLCO
~_1~7
NEe
JAPD7514
Figure 14. LCD ControllerlDriverBlock Diagram
On-chip Bus
Data Memory
Multiplexer
LCD Drive·Voltage Controller
532
so
S30
VLC3
VLC2
VLC1
Common Driver
COM3 COM2
COM1
COMO
Note: 'indicates instruction execution
Multiplexer
83-OO3604C
3-168
NEe
f..'PD7514
Figure 15. Configuration of LCD Power Supply by Voltage
Dividing Method
(a) '/3 Bias Method
!,PD7514
Positive
VOD
(b) '12 Bias Method
1--..........- - - - 1....... Power
Supply
!,PD7514
Rl
Positive
1---..--..-+ Power
Supply
Interrupt Enable Register (IE2-IEo). This register permits or inhibits individual interrupt requests of INn;
INTO/S and INT1; it allows the interrupt if the respective
bit of each interrupt is set to 1, and inhibits the interrupt
if o. See figure 17.
R2
Rl
Output
Port
Output
Port
Vss 1 - - - - - - . GND
Interrupt Function
There are two external (INTO, INT1) and two internal
(INn; INTS) interrupts. Interrupt INTO and pin POo share
one line; figure 12 shows how to select between these.
When INTO is selected, either INTO or INTS may be specified. The interrupt process (interrupt address and priority) for INTO and INTS is the same. See table 5 and
figure 16.
Vss 1 - - - - - - + GND
The value~ ~f R, R2, and C depend on the particular LCD panel
charactensllcs. TYPical values are:
VLCD = VOO-VLC3
2.7 V"VLCD"VDD
(KR2-'>2R, typically
R,=I00K
R2=200K
C=O.OO1"F
VLCD = 1 +
~:Rl
83-003603A
Figure 16. Interrupt Controller Block Diagram
CL
INTI 0 - + - - - - - - - - - 4
INTS
PQoIINTO
510"----.._#
Notes:
1. "Indicates execution of instruction.
2. 5M3 is bit 3 of the shift mode register. (Selection of INTO or INTS)
Standby Release
6121 83-0036058
3-169
NEe
J.(PD7514
Standby Function
Table 5. Source of Interrupts
Interrupt
Intlllt
Priority
Interrupt Address
INTI
(coincidence signal
from timer / event counter)
Int
1
10H (16)
INTO
(interrupt signal
from POo pin)
Ext
20H (32)
INTS
(transfer end signal
from serial interface)
Int
20H (32)
INT1
(interrupt signal
from INT1 pin)
Ext
30H (48)
Figure 17. Format of Interrupt Enable Register
EI
1
E2IE1IEo
~
Interrupt Enable Register
To pennlt or Inhibit INTT
To penn It or Inhibit INTO/S
To pennlt or Inhibit INT1
83-003606A
Interrupt Master Enable F/F (1M E). This F/F permits or
inhibits the acceptance of all interrupts (INTI, INTO,
INTS, and INT1); after accepting an interrupt, it is reset
to inhibit subsequent interrupts. The F I F is set by the EI
o instruction to permit all interrupts not individually dis·
abled, or it is reset by the 01 0 instruction to inhibit all
interrupts. In either case, the interrupt enable register is
unaffected.
Typical Interrupts. Figure 18 is an example of the interrupt process for the INT1 interrupt.
Figure 18. Typical Interrupt Process Flow
-t--
RESET
Address: 30H
Master Enable FIF = 0
Enable Register = 000
EI
EI
1
PSHDE
PSHHL
t
T
I
I
Enable Register = 100
Master Enable F/F=1
(INT1 Enable)
-.t
T
Master Enable FIF = 0
(All Interrupts Disabled)
~
-.t INT1
01
I
1
Master Enable FIF = 0
(All Interrupts Disabled)
POPHL
POPDE
EIO
PTPSW
83.(J()3607A
3-170
Two standby modes, stop and halt, are provided to reduce power consumption during a program standby
state. The STOP and HALT instructions select these
modes.
In standby mode, program execution ceases and the
contents of data memory and all internal registers are
held. The shift register and timer! event counter still operate.
A RESET or interrupt generation releases standby
mode; if an interrupt request flag is set, stop/halt mode
cannot be set in spite of the STOP I HALT instruction execution. Consequently, when setting standby mode
when there is a possibility of a request flag being set, it
is necessary to have the interrupt request flag reset either by processing the interrupt in advance or by executing a SKI instruction.
Differences between stop and halt modes are shown in
table 6. The main difference lies in that RC oscillation
output (CL) either stops (stop mode), or does not stop
(halt mode), when the system clock is being supplied by
RC oscillation.
Table 6. Comparing Stop and Halt Modes
Mode Instruction
CL
0
X
Interrupt used
CPU 510 eNT for rele...
Stop
STOP
X
X
0
X
*
Halt
HALT
0
X
0
X
0 INTI, INTO/S,
INT1
Note:
o Operation possible
• Operation possible with a mode selected
X Operation disabled
INTI,INTO/S
NEe
J-tPD7514
Reset Function
A high level RESET input initializes the J.lPD7514. The sequence of events is as follows:
(1)
The PC is cleared to O.
(2)
PSW flags SK1 and SKo are cleared to O.
(3)
The timer/event counter as reset as follows:
Count register = OOH
Modulo register = FFH
Timer out F/F=O
(4)
The clock control circuit is reset as follows:
Clock mode register (CM3-CMO) is cleared to 0
CP = LCD Clf = Cl X 1/256
TOUT is disabled.
Prescalers 1, 2, 3
0
After RESET, program execution starts from address
OOH. The contents of each register must be initialized as
needed.
=
Shift mode register (SM3-SMO) is cleared to O.
Serial interface shift operation stops.
Port 0 is placed in input mode (high impedance).
INTS is selected for the interrupt source of INTO/S.
(6)
Display mode register (DM3-DMO) is cleared to O.
1/3 bias, quadriplexed
Frame frequency = CLl1024, LCD drive deselected
(8)
All output buffers of ports 0-7 are turned off, and
become high impedance, I/O ports are set to input
mode.
(10) The contents of data memory and the following
registers are undefined:
Stack pointer (SP)
Accumulator (A)
Carry flag (C)
General-purpose registers (D, E, H, l)
Output latch of each port
Shift register
(5)
(7)
(9)
Power·On·Reset Circuit. The simplest example is shown
in figure 19.
Figure 19. Power· On-Reset Circuit
----
+5V
I'P07514
+
-w.
Interrupt control circuit becomes as follows:
Interrupt request flags 0
Interrupt master enable F / F = 0
Interrupt enable register = 0
All pending interrupts cancelled.
All interrupts disabled.
=
~
RESET
83-003608A 16121
Port 6 mode register (PM3-PMO) is cleared to O.
Operating Characteristics
fccvs R
fccvs Voo
1000
(TA
I--
§~
I-I--
I
-=
33PF
=
R=39kQ- t--
R
I-I--
2S 0 C)
--
--
- 1--- -- I---
--
-
r-l--t-
1---
f-~160-tQ-
I---
(TA
'N'
J:
~500
1
J
--4- 1--+ 1---
I
1
.~
-
-1--1---
-~
-
-- -
j - - 1--
1 - - 1--
-
-1--
-1--
Supply Voltage, Voo (V)
-- -- -
1---
1--
1--- 1--
~
()
I
II
:"~OI=ISV
--+- t-+ 1--- -- ~~
!
...o
i'
I
""g
I
100
-
2S 0 C)
50
~ -I-
10
10
~d~
I
~~
I-I--
--t- --t--
-ti
Voo=3V--
R
-+- I-j~- I-r- 1--- -l-:
33PF
i
50
100
Resistance, R (kQ)
500
3-171
NEe
JlPD7514
Operating Characteristics (cont)
Rvs VOO
fccvs TA
~ (TA
l
Voo =5V
R=39kQ
-- - -
- - -- -
-
r---- - - -
f---
--
-
-- -
-- --t-
'-
-r----
--
f---
-:-:--+-
'-
-
Voo=3V
R 160kQ
W
*'
a60pp':;;/°C)-
10
-25
1000
i
100
50
c3
-
50
25
AmblentTemperalure, TA (OC)
1010 +70°C)
75
=w
=1
=
Cll
Cl2
10 t=
R
~
I
== I
:-- -
33PF
~-I
~
I
Supply Vollage, Voo (VI
fcvs Voo
fxvs vOO
1+11+1412
;: 1000
g
(TA
JLJL
'N
12:fx=
1000
500
I
I
I
I I I
1
o
W
O
Cll
1 ....
-~
50
E
~
*,33 PF
c3
~
a.
---
i""'"
3
V
HALT (39 kHz)
HAL; (1601HZ)
STOP+Xlal=
~
I
0.1
o
-=-
I
-=-
500
0
.a:- 100
li
~
g'
30PF
r
......... STOP (Xl = 0 V)
!
«
--Supply Vollage, Voo (VI
3-172
1000
E
I I I I
§
. / i-""""
ljp~~~
20PF
<"
~
i
X2J
lXl
I
Supply Vollage, VOD (V)
..".,
10
I
IOO1VS TA
_ " ....... kH
R Cl2
L
J I I
loovs VOO
~ (TA 25°C) ~ Operaling Mode (39 kHz)
100
~
Defined
Oparallng
Area
~
Supply Vollage, Voo (VI
i
1010 +70°C)
1
11<12:fx= 211
11 >12:fc= 2112
I I I
c
I
I........
II
~
<"
.,3.
(TA-
500
J"8
I
Defined
Operallng
Area
I
.........
~
~
!.
0
50
I I I I
'w
Cl1
10
VOO 5V~
R 39kQ
E
VOO-3V!~
R 160kQ_r-----
CL2.
R
*,33 PF
-25
25
50
Amblenl Temparalure, TA (OC)
75
NEe
J,lPD7514
Operating Characteristics (cont)
VOHVS IOH
VOlVS IOl
-10
20
0
(TA=2S C)
(TA=2S 0 C)
I
I.
Voo=SV
~:z:
/
I
V voo=~
/
S}
.c
.1iP
Voo=sv
= -s
AOO=4~
~
u
/v
i
Iv
.",
o
/
o~
./
~
I
Voo=3V
--r
o
S
i
VOO-VOH(V)
V
... V
V
.
.
.
11 . . V
o~
. . . /1
-
--
Voo=3V
I
1
o
Output Voltage
Low, VOL (V)
I
Differences Between the JJPD7514, JJPD7508, and
JJPD7503
The J.tPD7514 integrates the features of the J.tPD7508 and
the strengthened LCD controller I driver of the J.tPD7503.
Differences are shown in table 7.
Table 7. Difference Between J.tPD7514, J.tPD7508, and
J.tPD7503
IlPD7514
jlPD7508C/G
On-chip RAM
256x4
226x4
224x4
Input ports
Port 0 (POO-P03)
Port 0 (P01-P03)
Port 1(P1rP13)
PortO
(P01-P03)
Port 1
(P11-P1 3)
Output ports
Port 2 (P20-P22)
Port 2 (P20-P23)
110 ports
Port 1(P10-P13)
Port 7 (P70-P73)
Port 1(P10-P13)
Port 7 (P70-P73)
Number of ports
31
32
LCD controller I
driver
Multiplexing
Biplexed
Triplexed
Quadriplexed
Triplexed
Quadriplexed
LCD controller I
driver
Segments
32
24
Package
SO-pin flat
40-pin DIP/
52-pin flat
IlPD7503G
23
64-pin flat
3-173
J.tPD7514
3-174
NEe
NEe
NEe Electronics Inc.
J,lPD7516H
4.BIT, SINGLE·CHIP
CMOS MICROCOMPUTER
WITH FlpID CONTROLLER/DRIVER
Description
D Vectored, prioritized interrupts
- Two external: INTO, INT1
- Two internal: timer (I NIT) and
serial (INTS)
D Four 4-bit general purpose registers
D 107 instructions; subset of J,lP07500 series instruction set A
- Look-up-table capability
- Indirect indexed addressing
The J,lP07516H and 75CG16H are 4-bit, single-chip
CMOS microcomputers with the J,lP07500 series architecture and a FIP controller/driver. On-board peripheral
functions include an 8-bit timer/event counter, an 8-bit
serial interface, a 14-bit programmable pulse generator,
and a display controller/driver that supervises all of the
timing requirements by the 24-port S segment drivers either for a 16-character, 7-segment FIP, or an 8-character,
14-segment FIP. The J,lP07516H is functionally equivalent to the J.lP07519H except for ROM size.
Twenty-eight I/O lines are organized into seven 4-bit
ports: the input/serial interface port 0, output ports 2
and 3, and I/O ports 1,4,5, and 6.
The subroutine stack is implemented in RAM for greater
nesting depth and flexibility, providing such operations
as the pushing and popping of register values.
The J,lP07516H /75CG16H has a 2.44 J,ls instruction cycle
time at fxx = 6.55 MHz.
For the J,lP07516H, current consumption is less than
6mA for normal operation (Voo=5V ±10%, fxx
= 6.55 MHz, high speed mode).
The J,lP075CG16H, a piggyback EPROM version, is available for prototyping and program development. It is pincompatible and functionally equivalent to the masked
version.
Features
D 6144 x 8-bit program memory (ROM)
D 256 x 4-bit data memory (RAM)
D 281/0 lines
D Programmable FIP controller/driver
- 24 high-voltage output lines
D 8-bit serial interface
D 8-bit timer/event counter
D Programmable pulse generator (PPG)
- Variable duty port (0/ A converter)
- Signal generator port
- 1-bit output port
@
D Instruction cycle
- J,lP07516H low speed mode: 15.26J,ls/4.19 MHz
- J,lP07516H low speed mode: 9.77 J,ls/6.55 MHz
- J,lP07516H high speed mode: 3.81J,ls/4.19 MHz
- J,lP07516H high speed mode: 2.44J,ls/6.55 MHz
D Two power-down modes
D Single power supply (2.5 V to 6 V)
Applications
The J,lP07516H has a variety of flexible powerful functions and is best suited for the following applications:
• Video tape recorders
• Plain paper copiers
• .Electronic cash registers
• Telephone sets
• Electronic scales
• Automobiles
Figures 1-4 show how to apply the device to a digital
tuning system, a telephone, an ECR, and automotive
equipment.
Ordering Information
Part
Number
Package Type
Max Frequency
of Operation
J.lPD7516HG-12
64-pin plastic miniflat
6.55 MHz
J.lPD7516HG-36
64-pin plastic QUIP
6.55 MHz
J.lPD7516HCW
64-pin plastiC shrink DIP
6.55 MHz
J.lPD75CG16HE
64-pin ceramic piggyback
QUIP
6.55 MHz
FIP is the registered trademark for NEC's fluorescent indicator panel (vacuum fluorescent display).
3-175
NEe
fAPD7516H
Pin Configurations
64·Pin Plastic Mlnlflat
64·Pin Plastic QUIP, and Shrink DIP
I-
~
m
Q.
Q.
...I 0
IU I- 1II)
Iii
P20/P5TB
~
w
P21/PTOUT
64 63 62 61 60 59 58 57 56 55 54 53 52
P23
RESET
0Q.
Q.
NC
POollNTO
Q.
rfiR~~~ gt-~~~~ g:
« Q. Q. Q. Q. > ~ Q. Q. Q. Q. >
0
P01/5CK
P02/S0
P03l51
P60
P61
P62
P63
51
50
VLOAO
To
49
Tl
48
47
46
45
44
T2
T3
T4
T5
43
42
PPO
NC
POolINTO
P01/SCK
T6
T7
VOO
INn
P33
P32
P31
P30
VPRE
VLOAO
To
P02/S0
Tl
P03iSI
T2
P60
P61
P62
T3
T4
Ts
P63
P50
T6
T7
P51
10
11
P52
12
40
Ta/Sa
T9/S9
Tl0/S l0
P53
P10
13
14
39
T11/S11
P51
P52
Ta/5a
Tg/Sg
38
T12 /S 12
P53
TlO/ S10
Pl1
15
16
17
37
36
35
34
Tl31S 13
Plo
T11/511
Tl4iS14
Tls/S 1S
So
P11
P12
T12/S12
Tl3i513
P13
Tl4i 5 14
33
51
NC
Tls/51S
P40
P41
50
Sl
P50
P12
P1 3
P40
P41
I'PD7518H
41
18
19
20 21 22 23 24 25 26 27 28 29 30 31 32
iiffi~x~~$clI'clfW'~~
>
w
83-002979A
P42
52
P43
S3
~~T
~
X2
55
56
Xl
Pin Identification
VSS'""1,.;~_ _...;.;;.... 57
83-002980A
Plastic Miniflat, QUIP, and Shrink DIP
Flat
QUIP(1)
S,mbol
7,24
NC
No connection
Function
Flat
QUIP(1)
S,mbol
Function
2
8
POOIINTO
51
57
VLOAD
3
9
POj/SCK
High voltage option resistor
supply negative. This pin is not
used (NC) in the /APD75CG16H.
4
10
.P02/S0
Port 0, or external interrupt
INTO and the serial I 10
interface
5
11
P03/S1
52
58
VPRE
High voltage predriver supply
negative
6-9
12-15
P60-P63
Port 6
53-56
59-62
P30-P33
Port 3
10-13
16-19
P50-P53
Port 5
57
63
INT1
External interrupt
14-17
20-23
P10-P13
Port 1
59
P20/PSTB
18-21
25-:28
P40-P43
Port 4
60
Port 2, or port 1STB signal,
timer FI F output, internal CL
output, and general purpose
output
2
P21/PTOUT
22
29
EVENT
Timer I event counter input
61
3
P22/PCL
23,24
30,31
X2, X1
Crystal clock input
62
4
P23
25
32
Vss
Ground
63
5
RESET
RESET input
26,58
64
VDD
Power supply positive
64
6
PPO
PPG output
27-34
33-40
SO-S7
Segment outputs
Note:
35-42
41-48
Ta/SaT15 /S 15
Timing I segment outputs
(1) This QUIP pin identification is al50 true for the shrink DIP and piggyback packages.
43-50
49-56
To-T7
Timing outputs
3-176
NEe
J.(PD7516H
Pin Configurations (cont)
Pin Functions
64-Pin Ceramic Piggyback QUIP
(Except EPROM)
POOl INTO, P~/SCK, P02/SO, P03/S1 (Port 0)
P20/P5TB 1
64
Vee
P2,/PTOUT
2
63
INT1
P22/PCl
3
4
P23
~PD75CG16H
62
P33
61
P32
RESET
5
60
P3,
PPO
6
59
P30
NC
7
58
VPRE
POo/INTO
8
57
NC
PO,/5CK
9
56
To
P02/50 10
P03/51 11
Vee
Vee
55
T,
Vee
54
T2
Vee
53
T3
52
T4
51
T5
P60
12
A'2
A7
P6,
13
A6
Aa
P62
14
A5
A9
P63
15
P50
16
50
T6
A3
49
T7
P5, 17
P52 18
A2
48
Ta/5 a
47
T9/59
P53 19
P10 20
Ao
17
46
T,0/5,0
10
16
45
T"/5,,
P1,
21
15
44
T'2/5,2
P12
22
14
43
T'3/5,3
13
42
T'4/5,4
P13
23
NC
24
41
T'5/5,5
P40
25
40
So
P4,
26
39
5,
P42
27
38
52
-.. ..
..r-
P43
28
37
53
EVENT
29
36
54
X2
30
35
55
X1
31
34
56
Vss 32
33
57
This port can be configured as the 4-bit, parallel input
port 0, or as the 8-bitseriall/ 0 interface under control of
the serial mode select register. The 8-bit serial 110 interface consists of the serial input (SI), the serial output
(SO), and a serial clock (SCK) used for synchronizing
data transfer. Line POo is shared with external interrupt
INTO, which is a rising edge-triggered interrupt.
P10-P13 (Port 1)
Individual lines can be configured as a 4-bit input or as a
latched, three-state output under control of the port 1
mode select register.
P20/PSTB, P21/PTOUT, P22/PCL, P23
P20-P23 are the 4-bit latched output port 2. PSTB is the
port 1 output strobe pulse. PTOUT is the timer-out F/F
signal. PCl is the internal system clock output. P23 is a
general purpose output.
P30-P33 (Port 3)
4-bit, latched three-state output port 3.
P40-P43 (Port 4)
83-00298'A
P50-P53 (Port 5)
Pin Identification (cont)
4-bit latched three-state I/O port. Can perform 8-bit parallell/O in conjunction with port 4.
I-lPD75CG16H, Piggyback EPROM
No.
Symbol
Voo
2-10,21,
23-25
Ao-A12
4-bit latched three-state 110 port. Can perform 8-bit parallell/O in conjunction with port 5.
Function
Unused
Program counter output
P60-P63 (Port 6)
Individual lines can be configured as a 4-bitinput or as a
latched, three-state output under control of the port 6
mode select register.
11-13,15-19
10- 17
Data input from the 2764
14
Vss
Same as bottom pin 32; connected to
2764 GND pin
EVENT
20
CE
Chip enable output
1-bit external event input for the timer/event counter.
Vss
Same as bottom pin 32; supplies OE
signal to the 2764
SO-S7,T8/S8-T15/~5,TO-T7
26
Voo
Same as bottom pin 64; supplies Vee
to the 2764
27,28
Voo
Unused
22
High voltage outputs. SO-57 are segment driver outputs, and To-T7 are digit driver outputs. Ta/Sa-T15/ S15
can be configured as either segment or digit driver outputs under control of the display mode select register.
3-177
IE
NEe
I-tPD7516H
INT1
External, rising edge triggered interrupt.
EPROM Pin Functions
Piggyback EPROM
PPO
Ao-A12 (Address)
1-bit programmable pulse generator output. PPO can
operate as the pulse width modulation output, signal
generator port, or 1-bit output port, as dictated by the
PPG mode select register.
Output the 13 bits of the program counter (PCO-PC11),
which are the address signals of EPROM 2764.
RESET
RESET input. RIC circuit or pulse initializes J.lPD7516H
and also releases stop or halt mode.
X1,X2
Crystal clock connection. A crystal oscillator circuit is
connected to X1 and X2 for system clock operation, or
an external clock may be connected to X1 and an inverted clock to X2.
VPRE
High voltage predriver supply. Apply single voltage from
Voo -12V to Voo for proper display operation.
V LOA 0
10-17 (Data Input)
Input data from the 2764.
CE (Chip Enable)
Outputs the chip enable signal to the 2764.
Voo(Pin 1)
Electrically equivalent to Voo of the bottom pins. Provided for future devices. Use in the open condition.
VOO(Pin 26)
Electrically equivalent to Voo of the bottom pins. Supplies Vee to 2764.
VOO(Pins 27, 28)
Electrically equivalent to Voo of the bottom pins. Do not
use these pins.
High voltage option resistor supply negative. Apply single voltage from Voo - 40 V to Voo for proper display
operation. This pin is not used (NC) in the J.lPD75CG16H.
VSS(Pin 22)
Voo
Electrically equivalent to VSS of the bottom pins. Supplies OE signal to the 2764.
Power supply positive. Apply single voltage ranging
from 2.5 V to 6.0 V for proper operation.
VSS(Pin 14)
Vss
Electrically equivalent to Vss of the bottom pins. Connected to 2764 GND pin.
Ground.
3-178
NEe
J.lPD7516H
Block Diagrams
IAPD7516H
INT1
EVENT
INTO/POo
SCK/POI
SO/P0 2
SI/P03
POO·P03
P10·P1a
P20·P23
PSTB/P20
PTOUT/P21
PCLlP22
P30·P33
ROM
Program Memory
6144 x 8 Bits v.PD7516H)
Instruction
Decoder
P40·P43
CL
Standby
Control
P50·P53
Ix/ 128
Clock
Generator
X1
X2
P60·P63
PPO
T7·lo
TIs/SIS
Ts/Sa
57·50
VPRE VLOAD
83-0029826
3-179
tt¥EC
iJPD7516H
Block Diagrams (cont)
jAPD75CG16H
EVENT
INTl
INTO/POo
SCK/P01
SO/P02
SI/P03
POO·P03
Plo·P13
P20·P23
PSTB/P20
PTOUT/P21
PCLlP22
P30·P33
P40·P43
10.17
CE
P50·P53
P60·P63
Xl
X2
PPO
T7·TO
T1s1515
Ta/Sa
57·50 VPRE
83-0029838
3-180
NEe
J.lPD7516H
Absolute Maximum Ratings
Consumption:
(1) CPU
5.5V x 2.0mA=11mW
TA=25°C
Supply voltages
Voo
VLOAO (IlPD7516H)
-0.3Vto +7V
Voo -40 V to +Voo +0.3 V
Voo -12 V to +Voo +0.3 V
Input voltage, VI
-0.3 V to Voo +0.3 V
Output voltage, Va
Display outputs, Va
Voo -40 V to Voo +0.3 V
Other outputs, Voo
- 0.3 V to Voo +0.3 V
Output current high, 10H
Per pin, other than display outputs
Per pin, SO-S7
-15mA
-15mA
-30mA
(2) Output pins
Segment pins: (5/7 x 2V) x 5mA x 9=64mW
Timing pins: 2 V x 15 mA = 30 mW
LED output pins: (10/15 x 2V) x 10mA x 4=53mW
(3) Pull-down resistors
(30 + 5.5 V)2/80 kQ x 10 = 158 mW
Therefore, PT = (1)
+ (2) + (3)
= 316 mW
DC Characteristics
j.lPD7516H: TA = -10°C to + 70°C, VOO = 2.5 V to 6 V
j.lPD75CG16H:TA= -100Cto +70 oC,VDO=5V ± 10%
Total, display outputs, IlPD7516H
-120mA
display outputs, IlPD75CG16H
-90mA
Parameter
Total, other than display outputs
-20mA
Input voltage
high
VIH1
0. 7V oo
Voo
V
Other than X1, X2
VIH2
Voo-0.4
Voo
V
X1, X2 (Note 1)
Input voltage
low
VIL1
0
0. 3V OD
V
Other than X1, X2
VIL2
0
0.4
V
X1, X2 (Note 1)
Output voltage
high
VOH
Voo-1.0
V
Voo=5V±10%,
10H= -1mA
Voo-0.5
V
IlPD7516H only,
10H= -100~
0.4
V
Voo=5 V ±10%,
IOL=1.6mA
0.5
V
IlPD7516H only,
10L =400~
3
~
VI = Voo; other
than X1, X2
Output current low, 10L
Per pin
Total, all output ports
Total power consumption (Note 1), PT
Plastic flat package (IlPD7516H)
Plastic QUIP, (IlPD7516H)
17mA
60mA
400mW
Umlta
Symbol
600mW
Min
Typ
Max
Unit
Operating temperature, TOPT
Storage temperature, TSTG
Comment: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits described in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
Output voltage
low
Input leakage
current high
Note:
(1) Calculation of PT: there are three kinds of power consumption, the
total of which should be less than the total power consumption (PT)
in this specification. Use of less than 80% of PT is recommended.
The three different power consumptions are as follows:
1. CPU power consumption. Voo(max) x I001(max)
2. Power consumption of output pins. This includes both normal
output and display output. Calculate the total consumption of
each output pin to which the maximum current flows.
3. Power consumption of on-chip pull-down resistors (mask option).
Example
Configuration:
9 segments x 11 digits, 4 LED outPUtS
VOO = 5 V ±10%, 4.19 MHz oscillation
Segment pin = 5 mA (max)
Timing pin = 15 mA (max)
LED output pin = 10 mA (max)
Vacuum fluorescent display (V LOA D) = - 30 V
Input leakage
current low
VOL
IUH1
Test
Conditions
IUH2
20
~
VI=VOO; X1, X2
IUL1
-3
~
VI = 0 V; other than
X1, X2
IUL2
-20
~
VI=OV; X1, X2
Input leakage
current
IlL
-200
~
IlPD75CG16H only;
VI=OV, 10-17
Output leakage
current high
ILOH
3
~
VO=Voo
Output leakage
current low
ILOL1
-3
Il A
Vo=OV: other
than display
outputs
ILOL2
-10
~
VO=VLOAO=
Voo-35 V: display
outputs
3-181
I
ttiEC
JIPD7516H
DC Characteristics (cont)
j.lPD7516H: TA = -10°C to + 70°C, Voo = 2.5 V to 6 V
j.lPD75CG16H: TA = -10°C to + 70°C, VDO = 5 V ± 10%
Limits
Parameter
Display output
current
On-chip
pull-down
resistance
Symbol
100
RL
Typ
Max
Unit
Tast
Conditions
-7
mA
SO-S7;
(Notes 2 & 3)
-4
mA
j.lPD75CG16H;
(Notes 2 & 3)
-15
mA
To-T15
(Notes 2 & 3)
-10
mA
j.lPD75CG16H;
(Notes 2 & 3)
-3
mA
So-S]; (Note 4)
-2
mA
j.lPD75CG16H;
(Note 4)
-7
mA
To-T15 (Note 4)
-5
mA
j.lPD75CG16H;
(Note 4)
kQ
VOO- VLOAO=35 V
40
70
120
Limits
Paramatar
Symbol
Min
Supply current, 10D1
j.lPD75CG16H
1002
Tast
Conditions
Typ
Max
Unit
1.2
3.6
mA
High speed
Voo=4.75 V to
5.5 V; (Note 5)
1.0
3.0
mA
High speed; (Note
6)
350
1000
j.tA
Halt mode
Voo=5V±10%;
(Note 6)
20
j.tA
Stop mode; (Note
6)
1003
Note:
(1) The circuits in figures 19 and 20 are recommended.
(2) The external circuit in figure 21 is recommended.
(3) VPRE=VOo-9V±1V, Vo o =4Vto6V, Voo=Voo-2V
(4) VPRE=OV, VOO=VDD-2V
(5) 6.55 MHz crystal, C1 = C2 = 10 pF
(6) 4.19 MHz crystal, C1 = C2 = 10 pF
Supply current, 1001
j.lPD7516H
1002
1001
1002
1003
3-182
Min
3.0
0.6
9.0
1.9
mA
mA
High speed
Voo=5V±10%;
(Note 5)
Low speed
halt mode
Voo=5V±10%;
(Note 5)
2.0
6.0
mA
High speed
Voo=5V±10%;
(Note 6)
400
1200
j.tA
Voo=3V±1O%;
(Note 6)
450
1500
j.tA
Halt mode
Voo=5 V ±10%;
(Note 6)
150
400
j.tA
Halt mode
Voo=3V ±10%;
(Note 6)
0.1
20
j.lA
Stop mode
Voo=5 V ±10%;
(Note 6)
0.1
10
j.tA
Stop mode
Voo=3V ±10%;
(Note 6)
Capacitance
TA=25°C;Voo=OV
Limits
Paramatar
Symbol
Input
capacitance
CI
Output
capacitance,
Display
outputs
Co
Other
outputs
I/
acapacitance
Cia
Min
Typ
Max
Unit
Tast
Conditions
15
pF
(Note 1)
35
pF
(Note 1)
15
pF
(Note 1)
15
pF
(Note 1)
Note:
(1) fc = 1MHz, Unmeasured pins are connected to OV.
t-IEC
J.lPD7516H
AC Characteristics
Clock Operation
Port 1110 Operation (cant)
IlPD7516H:TA= -10°C to +70°C, Voo=2.5Vt06V
IlPD75GC16H:TA = -10°Cto +70 oC, Voo =5V±10%
Parameter
Limits
Parameter
System clock
oscillation
Symbol
fxx
System clock
fx
input frequency
X1, X2 input
pulse width
high, low
Min
Typ
Max
Unit
Limits
Test
Conditions
Symbol
3.5
4.19
4.2
MHz (Notes 1, 2 & 3)
6.55
6.6
MHz Voo=4.5 V to
6.0V;
(Notes 1, 2 & 3)
Input data
floating time
(after PS'i'B t)
0.1
4.2
MHz (Notes 1& 4)
4.2
6.6
MHz Voo=4.5Vto
6.0V;
(Notes 1& 4)
Control set-up tesT
time (to PSTB +)
100
tXL
75
ns
(Notes 1 & 4)
Voo=4.5Vto
6.0V;
(Notes 1 & 4)
EVENT input
frequency
fE
410
EVENT input
pulse width
high, low
tEL
1.2
!-Is
Voo=4.0Vto
6.0V
tEH
6.25
j.ls
j.lPD7516H only
80
kHz
Voo=4.0Vto
6.0V
kHz !-IPD7516H only
Note:
(1) The circuits in figures 19 and 20 are recommended.
(2) Refer to the Operating Supply Voltage table.
Unit
Test
Conditions
700
ns
(Note 2)
0
ns
(Note 2)
100
ns
(Note 2)
100
ns
(Note 2)
ns
(Note 2)
ns
(Note 2)
tSTDF
Control hold time tSTe
Output
command
Input
command
PSTB pulse
width low
tSTL2
750
Note:
(1) Port output mode.
(2) 1/0 expander mode Voo = 4 V to 6 V.
Port 1110 Operation
j.lPD7516H:TA= -100Cto +70 oC, VoO=4.5Vt06.0V
IlPD75CG16H:TA= -10 0Cto +70 oC, Voo=4.75Vt05.5V
4.2MHz~ fx, fxx~ 6.6 MHz
Low Speed Mode(1) (EM2 = 0)
Limits
(4) External clock.
Parameter
Port 1110 Operation
IlPD7516H: TA = -10°C to + 70°C, Voo = 2.5 V to 6 V
IlPD75CG16H: TA = -10°Cto +70°C, Voo=5V±10%
0.1 MHz ~ fx, fxx ~ 4.2 MHz
Limits
Symbol
80
0
(3) Crystal oscillation.
Parameter
Typ
Input data valid tSTDV
time (after
PSTB +)
4.2
tXH
Max
Min
Min
Typ
Max
Unit
Test
Conditions
ns
(Note 1)
Symbol
Unit
Test
Conditions
ns
(Note 2)
Port 1output
tSTP
hold time (after
PSTB t)
100
ns
(Note 2)
PSTB pulse
width low
tSTL1
600
ns
(Note 2)
Output data set- tOST
uptime (to
PSTB t)
400
ns
(Note 3)
Output data hold tSTO
time (after
PSTB t)
100
ns
(Note 3)
ns
(Note 3)
ns
(Note 3)
ns
(Note 3)
Port 1output
hold time (after
PSTB t)
tSTP
100
PSTB pulse
width low
tSTL1
450
ns
(Note 1)
Output data set- tOST
uptime (to
PSTB t)
200
ns
(Note 2)
Input data valid tSTOV
time (after
PSTB +)
Output data hold tSTD
time (after
PSTB t)
100
(Note 2)
Input data
floating time
(after PSTB t)
ns
Max
400
250
(Note 1)
Typ
Port 1 output set- tpST
uptime (to
PSi'B t)
Port 1 output set- tpST
uptime (to
PSTB t)
ns
Min
850
tSTDF
Control set-up teST
time (to PSTB +)
400
3-183
NEe
JJPD7516H
AC Characteristics (cont)
Port 1110 Operation (cont)
Other Operations
Limits
Parameter
Symbol
Control hold time tSTC
Output
command
Input
command
PSTB pulse
width low
Min
Typ
Unit
ns
{Note 3)
Parameter
ns
{Note 3)
INTO pulse
tIOH,
width high, low tlOL
10
",s
ns
{Note 3)
INT1 pulse width tl1H
high, low
t11L'
(1)
",s
RESET pulse
tRSH,
width high, low tRSL
10
",s
Limits
100
80
0
tSTL2
Max
",PD7516H:TA = -10°C to +70 oC, Voo=4.5Vt06.0V
",PD75CG16H: TA = -10°C to + 70°C, Voo = 4.75 V to 5.5 V
Test
Conditions
1200
Note:
(1) The ",PD82C43/8243H, etc, cannot interface with the ",PD7516H in
high speed mode (EM 2 = 1).
(2) Port output mode.
Symbol
Min
Typ
Max
Unit
Test
Conditions
Note:
(1) 26/f x or 26/f xx
(3) 1/0 expander mode Voo = 4 V to 6 V.
",PD75CG16H EPROM Characteristics
TA= -10°C to +70°C;Voo=5V±10%
Serial Interface Operation
Limits
",PD7516H: TA = -10°C to + 70°C, Voo = 2.5 V to 6 V
",PD75CG16H:TA= -10OCto + 70°C, Voo=5V±10%
Limits
Parameter
Typ
Test
Conditions
Access time
tACC
tKCY
2.1
",s
Voo=4Vt06V;
Input
12.5
",s
",PD7516H only;
Input
(1)
",s
Voo=4Vt06V;
Output
(2)
",s
",PD7516H only;
Output
TA = -10°C to + 70°C
SCK pulse width tKH
high, low
0.7
",s
Voo=4 V to 6V;
Input
Parameter
tKL
6.5
",s
",PD7516H only;
Input
(3)
",s
Voo=4Vt06V;
Output
(4)
",s
",PD7516H only;
Output
300
ns
Voo=4Vto 6V
1000
ns
",PD7516H only
450
ns
VDO=4Vto 6V
SI hold time
(after SCK t)
tSIK
tKSI
1000
SO output delay tKSO
time (after
SCK ~)
Note:
(1) High speed mode: 16/f x or 16/f xx
Low speed mode: 64/f x or 64/f xx
(2) 64/f xx or 64/f xx
(3) High speed mode: 8/f x or 8/f xx
Low speed mode: 32/f x or 32/f xx
(4) 32/f xx - 2.01'5, or 32/f xx - 2.01'5
3-184
ns
",PD7516H only
500
ns
Voo=4 V to 6 V for
7516H
2000
ns
",PD7516H only
Min
Typ
CE low set-up
tCE
time to data valid
Min
SI set-up time
(to SCK t)
Unit
Symbol
Symbol
SCK cycle time
Max
Parameter
Max
Unit
700
ns
700
ns
Test
Conditions
ns
Data valid hold tlH
time to CE rising
edge
Operating Supply Voltages
Limits
CPU (Note 1)
Symbol
Typ
Test
Conditions
Max
Unit
4.5
6.0
V
fx, fxx =4.2MHzto
6.6 MHz, (Note 3)
4.0
6.0
V
fx=0.1 MHzto
4.2MHz,
fxx =3.5 MHz to
4.2 MHz, (Note 3)
4.5
6.0
V
fx, fxx =4.2 MHz to
6.6 MHz, (Note 4)
2.5
6.0
V
fx=0.1MHzto
4.2 MHz,
fxx=3.5 MHz to
4.2 MHz, (Note 4)
Min
tt1EC
J.lPD7516H
AC Characteristics (cont)
Timing Waveforms
Operating Supply Voltages (cont)
Data Retention Timing
Limits
Parameter
Symbol
Crystal
oscillation
circuit
(Note 2)
Typ
Min
4.5
Max
Unit
6.0
V
Te,t
Conditions
6.6MHz,
C1=10pF, C2~
10 pF, (Note 5)
2.7
6.0
V
h
I
fxx =4.2 MHz to
C1=10pF, C2~
10pF,
fxx =3.5MHzto
4.2 MHz, (Note 5)
2.85
6.0
V
C1=10pF, C2~
22pF,
fxx =3.5 MHz to
4.2 MHz, (Note 5)
External clock
2.5
6.0
V
Display controller
4.0
6.0
V
PPG
4.0
6.0
V
Port 1
2.5
6.0
V
Port output mode
4.0
6.0
V
1/0 expander
mode
(---STOP Mode
rData Retention MOde,
t '\
Voo
VOOOR
Execution of
STOP Instruction
/;..-----
=-..!
I
RESET
83·002959A
Clock Timing
X1 input
I
EVENT Timing
Note:
(1) Except the crystal oscillation circuit, display controller, PPG, and
portt
(2) The circuits in figure 19 and 20 are recommended.
83·002961A
(3) High speed mode, EM2=1.
(4) Low speed mode, EM2 = o.
EPROM Timing
(5) Crystal Oscillator.
AC Waveform Measurement Points (Except X1, X2)
0.7 Voo
0.3 VOO
>
Test
Points
<
0.7 Voo
0.3 Voo
CE
83·002909A
10·17
----------<1
83'()02962A
Strobe Output Timing
Plo·P13
PSTB
83·002963A
3-185
NEe
f..tPD7516H
Timing Waveforms (cont)
Interrupt Input Timing
Port I/O Expander I/O Timing
Expander
Port
Output
INTO
Expander
Port
Input
INT1
(Rising
Edge)
INT1
(Falling
Edge)
83-002966A
Serial Transfer Timing
RESET Input Timing
SCK
RESET
83-002967A
SI---+--..(J
SO
Output. _
Data
V_
I'--.
83-002965A
3-186
NEe
JiPD7516H
Figure 1. Digital Tuning System Application
Tuning Signal - - - - - - - - - - - - - - - - - - - - - - - - ,
Electronic Tuner
(Analog Output)
....-------------1
PPO
LPF
Keyboard
I'PD7516H
System
Control
Voo
Vss
83-0029858
Figure 2. Telephone Application
Buzzer
Figure 3. ECR Application
Keyboard
DO
Telephone Line
(Dial Pulse)
Keyboard
Buzzer
Melody
DO
I
X1
I
83-OO2986A
Power Fail
PPO
X2
Voo
Vss
I
83-002987A
3-187
NEe
J,tPD7516H
Data Memory (RAM), 256 Words x 4 Bits
Figure 4. Automotive Equipment Application
This static RAM used to store display and operation
data. It may also function with the accumulator (A) for 8bit data processing.
Analog Input
• Fuel
• Temperature
• Battery
ct1 Buzzer
Il..Jmelod Y
83-002988B
Functional Description
Program Memory (ROM), 6144 Words x 8 Bits
This mask-programmable memory is addressed by the
bank flag (BNK) and the program counter (PC), and is
used to store programs and table data. See figure 5.
Figure 5.
OOOOH
Program Memory Map
r-------,~----O-OO-OH
RESET vector
3,84ox8
INTT vector
0020H
INTO/S vector
0030H
INTI vector
D
Data memory addresses are from OOH to OFFH. The first
64 locations are pre-assigned as display data for the FIP
display (OOH to 03BH) and the programmable pulse generator (PPG) modulo section (03CH to 03FH). When display data is written in OOH-03BH, the FIP
controller/driver automatically reads it and generates
drive signals for the FIP. See figure 6.
Addresses OOH-03FH cannot be accessed by stack operations. RAM locations 40H-OFFH can be used as a
stack area addressed by the SP. This data memory area
is used when executing call or return instructions
(CALL, CALT, AT, RTS, RTSPW), push/pop instructions
(PSHDE, PSHHL, POPDE, POPHL), and when answering an interrupt.
When executing a call instruction or interrupt occurence with interrupts enabled, the contents of the PC
and program status word (PSW) are stored in the stack
area. A push instruction stores the contents of DE or H L
in the stack area. See figure 7.
256 x 8
0010H
There are three types of data memory addressing:
• Direct. Address designation is made on the second
byte of the instruction.
• Register indirect. Address designation is made by the
contents of a register pair designated by the instruction .
• Stack. Indirect address designation is made by the
contents of the stack pOinter (SP).
Figure 6.
~
Data MemoryMap
Data Memory
~
(0) DOH
lFFFH
OOCFH
OODOH
Reference table (16 x 8)
for LHLT Instruction
Reference table (48 x 8)
for CALT instruction
83·002938A
General Purpose Registers
Four 4-bit general purpose registers (D, E, H, L) may be
paired as follows for 8-bit operations: DE, HL, and DL.
These 8-bit register pairs are commonly used as
pointers to memory locations. When using the HL register pair as a data pointer, auto-increment and autodecrement of the L register may be specified.
3-188
60 x 4
Display iata Area
J
OOCOH
(59) 3BH
(60) 3CH
4 x 4
PPG Modulo Section
Dire ctllndirect
Ad dress Area
J
(63) 3FH
(64) 40H
256 x 4
..,,!,..
192 x 4
(255) FFH
83·002939A
NEe
Figure 7.
#-,PD7516H
Push, Call, Interrupt
•
1/32
(system clock, Cll; and FOP controller clock,
FIP)
Push Instruction
Call Instruction/Interrupt
Stack
Stack
SP·4
•
PCll' PCS
SP-3
PSW
SP·2
E or L
SP·2
PC3'PCO
SP· 1
D or H
SP· 1
PC7,PC4
83-002940A
Clock Generator
The system clock generator consists of a crystal oscillator, a frequency divider, and a standby (stop/halt)
mode control circuit, as shown in figure 8. When an external crystal is connected to X1 and X2, the crystal oscillator generates the f xx . (The notation 'fxx' is used
when referring to crystal oscillation; 'fx' is used when an
external clock is input.) It is also possible to obtain a
clock by inputting an external clock into X1 and an inverted clock to X2.
The frequency divider divides the output of the crystal
oscillator into four frequencies, as follows:
• 1/2 (pulse generator clock, PPG)
• 1/8 (system clock, ClH)
Figure 8.
1/128
(timer/event counter clock)
The system clock (Cl) may be 1/8 or 1/32 frequencydivided, depending on the state of expansion mode register bit 2 (EM:V. EM2 = 1 selects 1/8 , and EM2 = 0 selects
1/32. Cl is supplied to all circuits except the FIP controller and PPG, which use the fxx x 1/32 and fxx x 1/2, respectively. Cl is 1/2 frequency divided to supply the CPU
(,) clock. Cl is an input to the clock control circuitry
used to generate the count pulse (CP) used by the timer /
event counter.
The standby mode control circuit consists mainly of the
stop and halt flip-flops. The stop flip-flop, when set,
stops the crystal oscillator. There is no input to the frequency divider, so no clocks are output to the ",PD7516H
circuitry. The STOP instruction sets the stop flip-flop;
RESET clears it. The halt flip-flop, when set, inhibits the
input to the 1/2 frequency divider that generates "
thereby stopping ,. A HALT or STOP sets this flip-flop; it
is reset by the RELEASE Signal (generated when an interrupt flag is set) or at the falling edge of the internal
reset (IRESET) signal. (IRESET is released after a waiting time following the release of the external RESET
input.)
Clock Generator Circuit
...----------~r__--RESET
~----+-+----STOP
[Note 1]
STOP F/F
Frequency Divider
112
11128
........... r - - - - - J : i A L T [Note 1]
EM2--+---'
I - - - - - - H A L T RELEASE
l...-_ _ _
I RESET (
~
)
~----_, (to CPU)
L -_ _-+---1~--------------
__ CL (System Clock)
L -_ _ _ _ _ _ _ _ _ _ _ _ _ to Timerlevent counter
l...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ 'FIP
(to FIP controller)
Note:
[1]
Instruction execution.
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 'PPG (to pulse generator)
83-0029418
3-189
3
t\'EC
f..'PD7516H
Figure 9.
Clock Control Circuit
_nt~ernalrBU-S--------------------------------------------~
L -_ _ _ _ _ _ _ _ _
to
Tim~~~~~~:
_------------
1xx ___________________-1-__1--__1---1
128
Prescaler 2
(1/8)
Event 0 - - -
~------------ CP
(to Timer/Event
Counter)
Note:
(1) Instruction execution.
83·002942B
Clock Control Circuit
This circuit consists of a 4-bit clock mode register
(CMo-CM3), three prescalers, and a multiplexer, as
shown in figure 9. The circuit generates the clock pulse
(CP) input to the timer 1event counter from the following
inputs:
• System clock (Cl)
• 1/128 divided clock from the crystal oscillator (fxx/128)
• External EVENT pulse
Bit CMo-CM2 determine the clock input selection and
divide ratio. CM3 gates the output of a timer out signal
from the PTOUT (P21) pin. When CM3 = 1, output from
the timer out flop-flop (TOUT) is output to P21. Executing
an OP or OPl instruction loads the clock mode register.
The format of the clOck mode register is shown in
figure 10.
Timer/Event Counter
This counter consists of an 8-bit counter register, an 8bit modulo register, an 8-bit comparator, and a timer-out
flip-flop, as shown in figure 11.
The 8-bit count increments at every rising edge of the
clock pulse (CP). It is cleared to 0 when executing the
TIMER instruction, a RESET input, or a coincidence signal from the comparator.
3-190
Figure 10.
Clock Mode Register
Clock Mode Register
ICM3T CM21cM11cMol
L -l--l
CM2 CM1
0
0
CMO
0
CL x~
256
Ixx~
orlxx x~
8192
0
0
1
0
0
1
1
0
1
EVENT input
CL x-.!...
32
1
0
0
1
0
1
1
1
1
0
1
1
CM3
o
I 1
8192
Ixx~ orlxx x~
1024
1024
Inhibit
Designation 01 Timer Out F/F Output
I
I
Stop
Output
I
I
I
83·002943A
The modulo register determines the INTI signal interval. The contents of this register are set via the TAMMOD instruction. RESET sets the contents to OFFH.
The timer-out flip-flop inverts with every INTI signal output from the comparator. Its output, TOUT, can by sent
to the PTOUT pin when bit 3 (CM3) of the clock mode register is set. TOUT may also be used as a serial clock
source to the serial interface.
NEe
Figure 11.
J-lPD7516H
Serial Interface
Structure of the Timer/Event Counter
The serial interface is used for serial data I/O. It consists of an a·bit shift register, a 4·bit shift mode register,
and a 3·bit counter, as shown in figure 12. Figure 13
shows the serial shift timing.
TCNTAM - t - - . - !
[Note 1]
The serial clock (SCK) controls the serial data communication rate. An a·bit byte clocks into the serial input (SI)
port or out of the serial output (SO) port starting with the
MSB. Data transmission occurs synchronously with the
falling edge of SCK. Data reception occurs synchronously with the rising edge of SCK.
CP
Note:
[1] Instruction execution.
PTOUT
The 3·bit counter counts the number of serial clock
pulses. When a byte of serial data is transferred, an internal interrupt signal (INTS) is generated. Selecting
INTS (setting SM3 of the shift mode register to 0) sets
the interrupt request flag, INTO/S RQF.
83·002944A
The end of transfer of each byte can also be verified by
testing INTS RQF with the SKI instruction instead of interrupt processing.
Figure 12.
Serial Interface Block Diagram
POJiSI O - - - - i .>-----4-+-1-+--+I
SM3
[Note 2]
P02/SO 0----"------++-<
"-_ Jo-----1i-----+--TOUT
Notes:
[1] Indicates instruction execution.
[2] SM3 to the interrupt controller.
I------<>--.INTS
POOIINTOo------t . > - - - - - -...
RS
"""""----~---,Q
F/F
SI+----SIO
[Note 1]
83-0029458
CPU Clock (~)
When the SIO instruction executes, eight CPU clock
pulses (~) are supplied to the serial interface for the serial clock and output from SCK. After the eighth clock,
SCK is fixed high level, automatically stopping serial
data 110 after one byte has transferred.
Table 1. SCK Frequencies
Low Speed Mode
High Speed Mode
6.55 MHz
102.4 kHz
409.6 kHz
4.19MHz
65.5 kHz
262 kHz
SCK does not have to be software controlled. Its transfer rate is determined by the frequency of ~. See table 1.
3-191
11
ttlEC
JAPD7516H
Figure 13.
Serial Shift Timing
INTS
generating
timing
reenabling the master interrupt flip-flop or until their interrupt request flags are reset by executing a SKI instruction.
Figure 14 is a block diagram of the interrupt control
circuit.
FIP Controllerl Driver
83·002946A
Interrupt Function
There are two external and two internal interrupts, with
the specifications listed in table 2. The external interrupt INTO uses the POO port pin as the interrupt signal
input, and has the same interrupt process as the internal serial interrupt INTS. Selection of the interrupt is
programmable and depends on the application.
Table 2. Interrupt Specifications
Vector
Inti
Source
Ext
PriorIty
Address
INTI (coincidence signal from timer / event
counter)
int
1
10H(16)
INTO (interrupt signal from POO terminal)
ext
20H(32)
INTS (end of transfer signal from serial
interface)
int
20H(32)
INT1 (interrupt signal from INT1 terminal)
ext
3
30H(48)
Interrupt Sequence
When an interrupt goes active, the following occur:
• A corresponding interrupt request flag is set.
• The interrupt master enable flip-flop is reset.
• The contents of the PC and PSW are saved in the
stack.
• An interrupt start address is generated and jumped
to.
• The interrupt request flag set by the interrupt is reset.
Two machine cycles are required for interrupt execution,
one for saving the return address and one for jumping to
the interrupt start address. If several interrupts occur simultaneously, all respective request flags are set, and
the interrupt with the highest priority is processed. The
remaining interrupts are pending until serviced by
3-192
The FIP controller/driver consists of 60 4-bit nibbles of
display memory (000-03BH of data RAM), a 4-bit display
mode register (DM3-DMo), a 4-bit timing mode register
(TM3-TMo), a 4-bit blanking mode register (BM3-BMo),
an output selector, and a high voltage output driver. See
figure 15.
The FI P controller / d river has 24 outputs for directly d riving a high voltage vacuum fluorescent display:
• 8 segment signal outputs (So-S7)
• 8 timing signal (grid) outputs (To-T7)
• 8 timing or segment outputs (Ta/Sa-T15/S15)
The contents of the display mode register determines
which of the five display modes is available to the user.
The modes are as follows:
• Static mode
- 24 static output
• Dynamic mode
- 8 segment mode
- 12 segment mod~ I
- 12 segment mode II
- 16 segment mode
The contents of the timing mode register determine the
number of display digits (1-16) and control the number
of timing signals (To-T15) output. Timing signals drive
the grids of vacuum fluorescent display tubes. The
voltage on the grid will determine the brightness of a
digit (made up of one or more segments) or if the digit
will be turned on or off.
The width of the timing signal pulse can be adjusted at
eight independent steps by the value loaded into the
blanking mode register. This function is useful for dimming control and for preventing display cross-talk of adjacent digits.
The active level of the timing signal can be designated
high or low by bit DM 3 .
NEe
Figure 14.
J..lPD7516H
Interrupt Control Circuit Block Diagram
[Note 1]
SM3
[Note 2]
INT1
INT1
ROF
CLINTS
POolINTO
Nonsync
Edge
Detect
INTO/S
ROF
Nonsync
Edge
Detect
INIT
ROF
Vector
Address
Gen
[Note 1]
SID
INIT
Note:
[1] Indicates instruction execution.
[Note 1] Timer
[2] SM3 is bit 3 of the shift mode register
(selection of INTO or INTS).
HALT Release
83-0029478
Figure 15.
FIP Controller/Driver Block Diagram
On·chip Bus
Display Data Memory
(60 )( 4 bits max)
Segment Data Latch (16 bits)
TO·T7
83-0029848
~_1Q~
ttiEC
J.(PD7516H
Display Mode Register (OM)
Figure 16.
This 4-bit write-only register (OM3-0MO) determines the
display mode (dynamic, static, and off) of the FIP
controller/driver. It also determines the active level of
the display timing signals. This is shown in figure 16.
Display Mode Register Format
IDM~DM21DM1 DMOJ
L- ~
The DM register has an output address of aBH and is
accessed by the output instructions OP and OPL when
bit EM3 of the expansion mode register is set. The OM
register is cleared by a RESET.
0
0
0
Display OFF
0
0
1
Use Inhibited
f--0
1
0
1
0
1
1
0
0
Static display (24 segment output)
8 segment mode (up to 16 digits)
f---
Figure 17 showns a display example in 12-segment
model.
1
0
1
1
1
1
r---1 1 0
r----
o
12 segment mode I (up to 15 digits)
Dynamic
Display
12 segment mode II (up to 11 digits)
16 segment mode (up to 11 digits)
I
I
Timing signal Tn: active
hi9~
1 Timing signal Tn: active low
I
83-002949A
Figure 17.
Display Example in 12-Segment Mode I
Display Data Memory
{OM = [x[101]
TM = [1010]
1 EH
T1S T14 T13 T12
I
k
i
i
h
g
f
e
d
c
b Ja
0
0
0
b3
0
0
0
b2
0
0
0
0
b1
0
0
0
0
bO
0
0
0
0
0
b3
0
0
1
1
1
b2
0
0
0
0
1
b1
0
0
0
0
1
1
bO
1
0
0
1
1
0
b3
1
0
1
1
0
1
b2
0
0
1
1
0
0
b1
0
1
0
0
1
0
0
bO
II
II
II
II
:
I
I
I
I
I
I
I
:
I
I
II
I
Ts
Ts
T4
T3
T2
Tl
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
1
1
0
0
0
I
I
I
I
I
I
I
I
I
I
I
Tg/Sg
Ta/Sa
1FH
1DH
1CH
03H
01H
OOH
27H
25H
24H
I
I
I
1BH
19H
18H
17H
15H
14H
OFH
ODH
OCH
OBH
09H
08H
0
0
0
0
0
1
13H
11H
10H
~ • • • • • • • • •
I
I
~ S14 ~ ~ S7 S6 S5 S4 S3 S2 S1 SO
23H
21H
20H
07H
05H
04H
2BH
29H
28H
Tll /S 11 Tl0/Sl0
1
T7
I
I
I
+
4n + 3
4n + 1
4n
I
I
I
•
To
I I I I I I I I I I I
SUN
AMa
p";b
0
-
MON
-
I I I I
~E1 WED
leil
-
FRI
SAT
THU
I-I I- I I- I I- I I 1 I- I
a
ffglb
[10 [10 I~I
C10 [10 [10 [10 [10 1]0 el~~
-0
i 10 h
1
2
3
4
7
9
5
6
8
83-0029508
NEe
Standby Function
Two standby modes, stop and halt, hold device power
consumption to a minimum. Stop mode is entered via
the STOP instruction, and halt mode is entered via the
HALT instruction. In stop mode, all clocks are stopped.
In halt mode, only the CPU clock (~) is stopped.
Stop mode can only be released by a RESET. Halt mode
may be released either by a RESET or by the setting of
an interrupt request flag.
Stop Mode
In stop mode, the contents of memory are retained, and
all other functions are stopped. RESET releases stop
mode.
In stop mode, the X1 input is internally shorted to Vss in
order to hold the crystal oscillator leakage to a minimum. A system using stop mode cannot use an external
clock.
Halt Mode
When no interrupt flags are set, the HALT instruction
causes the device to enter halt mode. In this mode, only
~ stops; all other clocks continue to operate. The following functions continue to operate:
• Clock oscillation
• Frequency division and output of clocks other than ~
• Event input
• Timer/event counter
• Serial interface (except when ~ is used as SCK)
• FIP controller/driver
• PPG
• Interrupts (INTO, INTS, INIT, INn)
• RESET
Since a set interrupt flag releases the device from halt
mode, this mode cannot be entered if an interrupt request flag is set. It is therefore necessary to reset the
request flag(s) either by answering the interrupt(s) (setting the interrupt master enable F/F and process interrupt) or by executing the SKI instruction.
J.LPD7516H
Low Supply Voltage Data Retention (J.tP D7516H
only)
Data retention is possible with VOD as low as 2 V. VOO
should be lowered after the device is put in stop mode
and while RESET is inactive. Stop mode cannot be released in low voltage data retention mode; VOO should
first be raised to normal operation.
Release of Stop Mode
RESET releases stop mode. On RESET's rising edge,
the device mode changes to halt mode, starting clock
oscillation. At the falling edge of RESET, a waiting time
(about 62.5 ms/4.19 MHz, 40 ms/6.55 MHz) elapses, allowing for stabilization of crystal operation; following
this the halt mode is released. After normal RESET operation, the CPU begins program execution from address
OOOOH.
C3
In the release operation, the contents of data memory
are retained while the contents of other registers become undefined.
Power-on Reset Circuit
An example of the simplest power-on reset circuit using
a resistor and capacitor is shown in figure 18.
Figure 18.
Power-on Reset Circuit
+5V
~RESET
83-002951B
Figure 19.
In halt mode, CPU power consumption is eliminated. To
hold power consumption to a minimum, all unnecessary circuits should be inactive and the steps below
should be taken:
• Set the system clock (CL) to low speed
• Set the FIP controller/driver to the off mode
• Set the PPG for static operation
• Stop SCK input
Crystal
X1
X2
r---m~
C1 = 10 pF
C2 os; 22 pF
e'1
r
83-002956A
'l_10k
NEe
""PD7516H
Figure 20.
External Clock
Figure 21.
External Circuit
VOOr---~------~-----------o-5V
+
_=~ 3.3,..F
Xl
2~ RD9.1EL
VpREr---+--------+
~
68 kO
High·Speed CMOS Inverters
VLOAO r------------+--------------
l
II)
<"
.3
High Speed Halt Mode
500
X1
X2
o
10
10 PF
I
1
I
J
500
f-
2.0
&:::
f-
~
We
-t-- t---
~
100
(J
>-
X1
50
g-
Il)
110 PF
1
~
M
~,,~ ~""
V
<"
~
IJ
~5ob-
High spee1d
2.0
i/
. / Mjde
~eel
= 5 V - I--
V
..... 17
V
1-1-1
......
17
)?' l - I.--- ....
"-- l- Low Speed Mode Vee
--
~ f=:
~
r==
&AI =
V
_I-- I--'"
::
I
./
1.0
I
100 Vs. fx
High Speed Mode Vee = 5 V
II)
o
~
-
Supply Voltage, Vee (V)
High Speed Hall Mode Vee = 5 V
o
I
I I
o
./
>-
I
I
I
10 pF
I
-
~
~ i==
=t~- t~
-
10 pFI6.55 MHz
10
4.19 MHz ~
X2::
D
ii
hi A I1= ~5obI I
t-
(J
k::::
Low Speed Hal~ Mo~e
&:::
100 Vs. fxx
~
6.55 MHz)::
l---
High Speed Halt Mode
Low Speed Mode
1000
Q
Q
Supply Voltage, Vee (V)
<"
= 25°C,lxx
~i9h, Spe~d Mode
High Speed Mode J....-- I--- +--
1000
c(
(TA
4..19 MHz)=
25°C,lxx
= 3V
... Low Speed Halt Mode Veo = 3 V
Clock Oscillation Frequency, Ixx (MHz)
o
-::....
"-
V
-
.J,.....--P'
__ V
HiJh
~pee~
J.....- Halt Mode Vee = 5 V-
_+- Low Speed Mode
j...
Low Speed Halt Mode
o
Clock Input Frequency, Ix (MHz)
3-197
f..'PD7516H
3-198
NEe
NEe
NEe Electronics Inc.
J..tPD7519/19H
4-BIT, SINGLE-CHIP
CMOS MICROCOMPUTERS
WITH Flp® CONTROLLER/DRIVER
Description
Features
The J.LPD7519, 7519H, 75CG19, and 75CG19H are CMOS
4-bit, single-chip microcomputers with the J.LPD7500
series architecture and a FIP controller/driver. Onboard peripheral functions include and 8-bit
timer/event counter, an 8-bit serial interface, a 14-bit
programmable pulse generator, and a display controller/driver that supervises all of the timing requirements of the 24 port S segment drivers either for
a 16-character, 7-segment Flp, or an 8-character,
14-segment FIP.
o 4096 x 8-bit program memory (ROM)
o 256 x 4-bit data memory (RAM)
o 28 I/O lines
o Programmable FIP controller/driver
Twenty-eight 110 lines are organized into seven 4-bit
ports: the input serial interface port 0, output ports
2 and 3, and I/O ports 1, 4, 5, and 6.
o
The subroutine stack is implemented in RAM for
greater nesting depth and flexibility, providing such
operations as the pushing and popping of register
values.
o
o
The J.LPD7519 has a 7.63 J.Ls instruction cycle time at
fxx = 4.19 MHz. The J.LPD7519H/75CG19H has a
2.44 J.Ls instruction cycle time at fxx = 6.55 MHz.
o
Current consumption for the J.LPD7519 is less than 2
rnA in normal operation (Voo
5 V ± 10%, fxx
4.19
MHz, high speed mode) and is further reduced in the
halt and stop power-down modes. For the J.LPD7519H,
current consumption is less than 6 rnA for normal
operation (Voo
5 V ± 10%, fxx
6.55 MHz, high
speed mode).
=
=
o
o
o
=
=
The J.LPD75CG19/75CG19H piggyback EPROM version,
is available for prototyping and program development.
It is pin-compatible and functionally equivalent to the
masked version.
Note: FIP is the registered trademark for NEG's fluorescent indio
cator panel (vacuum fluorescent display).
o
o
- 24 high-voltage output lines
8-bit serial interface
8-bit timer/event counter
Programmable pulse generator (PPG)
- Variable duty port (D/A converter)
- Signal generator port
- 1-bit output port
Vectored, prioritized interrupts
- Two external: INTO, INT1
- Two internal: timer (INTT) and serial (INTS)
Four 4-bit general purpose registers
106 instructions; subset of J.LPD7500 series
instructions set A
- Look-up-table capability
- Indirect indexed addressing
Instruction cycle
- J.LPD7519 low speed mode: 15.26 J.Ls/4.19 MHz
- J.LPD7519 high speed mode: 7.63 J.Ls/4.19 MHz
- J.LPD7519H low speed mode: 15.26 J.Ls/4.19 MHz
- J.LPD7519H low speed mode: 9.77 J.Ls/6.55 MHz
- /APD7519H high speed mode: 3.81 /As/4.19 MHz
- /APD7519H high speed mode: 2.44 /As/6.55 MHz
Two power-down modes
Single power supply (2.5 V to 6.0 V)
Ordering Information
Part Number
Package Type
Max Frequency
of Operation
tJPD7519G-12
64-pin plastic miniflat
4.19 MHz
tJPD7519G-36
64-pin plastic QUIP
4.19 MHz
4.19 MHz
tJPD7519CW
64-pin plastic shrink DIP
tJPD75CG19E
64-pin ceramic piggyback QUIP
4.19 MHz
tJPD7519HG-12
64-pin plastic miniflat
6.55 MHz
tJPD7519HG-36
64-pin plastic QUIP
6.55 MHz
tJPD7519HCW
64-pin plastic shrink DIP
6.55 MHz
tJPD75CG19HE
64-pin ceramic piggyback QUIP
6.55 MHz
3-199
3
~EC
/-lPD7519119H
Pin Configurations
64-Pln Plastic Mlnlflat
64-Pin Plastic QUIP and Shrink DIP
P20IPSTB
P21/PTOUT
NC
VLOAD
POo/lNTO
P22/PCL
P33
P23
RESET
P32
P31
PPO
P30
50
To
NC
49
T1
PDa/INTO
VLOAD
48
T2
P01/SCK
To
P03/SI
47
T3
P02/S0
T1
P80
46
T4
P03i51
T2
P61
45
T5
P60
T3
P62
44
T6
P61
T4
P63
43
T7
P62
T5
42
Te/S6
TglSg
P63
T6
P50
T7
0
P01/SCK
P02/S0
VPRE
P50
10
P51
11
41
P52
12
40
T101S10
P51
P53
13
39
T11 /S 11
P52
Te/5a
Tg/59
I'PD751917519H
P10
14
38
T12 /S 12
P53
T10/510
P11
15
37
T13iS13
P10
T11 /5 11
P12
16
36
T14iS14
P11
T12/512
P13
17
T1s1S15
P12
T13i5 13
So
P13
T14i514
S1
NC
T1s1515
P40
18
P41
19
20 21 22 23 24 25 26 27 28 29 30 31 32
~.:ti~
Do
Do
w
~
x
~8Jj~Jf.3Jl~
> >
83·002933A
P40
50
P41
51
P42
52
P43
S3
EVENT
54
X2
55
X1
Sa
Vss
57
83·002934A
3-200
NEe
/-lPD7519/19H
Pin Configurations (cont)
Pin Identification
64·Pin Ceramic Piggyback QUIP
Flatpack, Shrink DIP, and QUIP Packages
Flat
P20/PSTB
VDD
P21/PTOUT
INTl
P22/PCL
P33
P23
P32
RESET
P31
PPO
P30
NC
7, 24
VPRE
POoliNTO
NC
P01/SCK
To
P02/S0
Tl
P03/S1
T2
P60
T3
P61
T4
P62
QUlP(I)
Name
Function
NC
No connection
8
POo/INTO
9
P01/SCK
Port 0 or external interrupt INTO
and the serial I/O interface
4
10
P02/S0
5
11
P03/S1
6-9
12-15
P60-P63
10-13
16-19
P50-P53
Port 6
Port 5
14-17
20-23
P10-P13
Port 1
18-21
25-28
P40-P43
Port 4
29
EVENT
Timer/event counter input
30-31
Ts
22
P63
T6
23-24
X2, X1
Crystal clock input
P 50
T7
25
32
Vss
Ground
VDD
Power supply positive
P51
Ta/Sa
P52
Tg/Sg
26, 58
64
P53
Tl0/S l0
27-34
33-40
SO-S7
Segment outputs
35-42
41-48
T8/ S8T15/ S15
Timing/segment outputs
Pl 0
Tll/S11
Pl1
T12/S12
P12
T13/S 13
P13
T14/S14
43-50
49-56
To-T7
Timing outputs
NC
T1S/S 1S
51
57
P 40
So
VLOAD
P 41
Sl
High voltage option resistor supply negative. This pin is not used
(NC) in the J..lPD75CG19175CG19H.
P42
S2
52
58
VPRE
High voltage predriver supply
negative
P43
S3
EVENT
S4
X2
Ss
Xl
S6
Vss
S7
53-56
P30-P33
Port 3
INT1
External interrupt
59
P20/PSTB
60
P21/PTOUT
Port 2, or port 1 STB signal,
timer F/F output, internal CL output, and general purpose output
57
83·002935A
59-62
63
61
P22/PCL
62
4
P23
63
5
RESET
RESET input
64
6
PPO
PPG output
Note:
(1) This QUIP pin identification is also true for the shrink DIP and
piggyback packages.
t-IEC
/JPD7519/19H
Pin Identification (cont)
P60·P63 (Port 6)
EPROM Socket on Piggyback QUIP
Individual lines can be configured as a 4-bit input or
as a latched, three-state output under control of the
port 6 mode select register.
No.
Symbol
Function
VDD
MSEL
Unused
Unused
EVENT
3-10,21,
23-25
Ao-A11
Program counter output
1-bit external event input for the timerlevent counter.
11-13,
15-19
10- 17
Data input from the 2732
50.57, T8/S8·T 15/515, To.:r 7
14
Vss
Same as bottom pin 32; connected to
2732 GND pin
20
CE
Chip enable output
22
Vss
Same as bottom pin 32; supplies OE
signal to the 2732
26
VDD
Same as bottom pin 64; supplies Vee
to the 2732
INTI
VDD
Unused
External, rising edge triggered interrupt.
27, 28
Pin Functions
POo/INTO, P01/SCK, P02/S0, P03/S1 (Port 0)
This port can be configured as the 4-bit, parallel input port 0, or as the 8-bit serial 1/0 interface under control of the serial mode select register. The serial interface consists of the serial input (SI), serial output
(SO), and serial clock (SCK) used for synchronizing
data transfer. Line POo is shared with external interrupt INTO, which is a rising edge-triggered interrupt.
P1o·P13 (Port 1)
High voltage outputs. SO-S7 are segment driver outputs, and To.:r7 are digit driver outputs. Ts/Ss.:r 15/S15
can be configured as either segment or digit driver
outputs under control of the display mode select
register.
PPO
1-bit programmable pulse generator output. PPO can
operate as the pulse width modulation output, the
signal generator port, or as a 1-bit output port, as dictated by the PPG mode select register.
RESET
RESET input. RIC circuit or pulse initializes
JAPD7519/7519H and also releases stop or halt mode.
X2, X1
Individual lines can be configured as a 4-bit input or
as a latched, three-state output under control of the
port 1 mode select register.
Crystal clock connection. A crystal oscillator circuit
is connected to X1 and X2 for system clock operation.
Or, an external clock may be connected to X1 and an
inverted clock to X2.
P20/PSTB, P21/PTOUT, P22/PCL, P23 (Port 2)
VPRE
P20-P23 are the 4-bit latched output port 2. PSTB is
the port 1 output strobe pulse. PTOUT is the timer-out
F/F signal. PCl is the internal system clock output.
P23 is a general purpose output.
High voltage predriver supply. Apply single voltage
from Voo-12 V to Voo for proper display operation.
P30·P33 (Port 3)
4-bit, latched three-state output port 3.
P40·P43 (Port 4)
4-bit latched three-state 1/0 port. Can perform 8-bit
parallel 1/0 in conjunction with port 5.
VLOAD
High voltage option resistor supply negative. Apply
single voltage from Voo-40 V to Voo for proper
display operation. This pin is not used (NC) in the
JAPD75CG19/75CG19H.
VDD
Power supply positive. Apply single voltage ranging
from 2.5 V to 6.0 V for proper operation.
P50·P53 (Port 5)
4-bit latched three-state 1/0 port. Can perform 8-bit
parallel 1/0 in conjunction with port 4.
Vss
Ground.
NEe
J,lPD7519/19H
Pin Functions, EPROM Socket
Voo (Pins 27, 28)
Ao-A11 (Address)
Electrically equivalent to VDD of the bottom pins. Do
not use these pins.
Output the 12 bits of the program counter (PCa-PC11),
which are the address signals of EPROM 2732.
Vss (Pin 22)
Electrically equivalent to Vss of the bottom pins. Supplies OE signal to the 2732.
10-17 (Data Input)
Input data from the 2732.
Vss (Pin 14)
CE (Chip Enable)
Outputs the chip enable signal to the 2732.
Electrically equivalent to Vss of the bottom pins. Connected to 2732 GND pin.
Voo (Pin 1)
MSEL
Electrically equivalent to VDD of the bottom pins. Provided for future devices. Use in the open condition.
Provided for future devices. Use in the open condition.
Voo (Pin 26)
Electrically equivalent to VDD of the bottom pins. Supplies Vee to the 2732.
Block Diagram, J.tPD7519/7519H
INT1
EVENT
INTO/POo
SCK/P01
SO/P02
SI/P03
P20·P23
PSTB/P20
PTOUT/P21
PCL/P22
ROM
Program Memory
4096 x 8 Bits {jJPD7519/7519H)
CL
Standby
Control
1,/128
Clock
Generator
X1
X2
PPO
TrTo
T1S/S1S
Ts/Sa
S7·S0
VPRE VLOAD
83·0029368
NEe
JAPD7519119H
Block Diagram, IlPD75CG19/75CG19H
EVENT
INn
INTO/POo
..!L
128
P10·P13
P20·P23
P5TB/P20
PTOUT/P21
PC L/P22
P 40· P4 3
lo·h
ce-----,
X1
X2
PPO
T7·To
T1s1515
Ta /5 a
57·50
VPRE
83·0029378
NEe
J..lPD7519/19H
Functional Description
Program Memory (ROM), 4096 Words x 8 Bits
This mask programmable memory is addressed by the
program counter (PC), and is used to store programs
and table data. See figure 1.
General Purpose Registers
Four 4-bit general purpose registers (0, E, H, L) may
be paired as follows for B-bit operations: DE, HL, and
DL. These B-bit register pairs are commonly used as
pointers to memory locations. When using the HL
register pair as a data pointer, auto-increment and
-decrement of the L register may be specified.
Data Memory (RAM), 256 Words x 4 Bits
This static RAM is used to store display and operation data. It may also function with the accumulator
(A) for B-bit data processing.
There are three types of data memory addressing:
• Direct. Address designation is made on the second
byte of the instruction.
• Register indirect. Address designation is made by
the contents of a register pair designated by the
instruction.
• Stack. Indirect address designation is made by the
contents of the stack pointer (SP).
Figure 1.
Data memory addresses are from OOH to OFFH. The
first 64 locations are pre-assigned as display data for
the FIP display (OOH to 03BH) and the programmable
pulse generator (PPG) modulo section (03CH to 03FH).
When display data is written in 00H-03BH, the FIP controller/driver automatically reads it and generates
drive signals for the FIP. See figure 2.
Addresses 00H-03FH cannot be accessed by stack
operations. RAM locations 40H-OFFH can be used as
a stack area addressed by the SP. This data memory
area is used when executing call or return instructions
(CALL, CALT, RT, RTS, RTSPW), push/pop instructions
(PSHDE, PSHHL, POPDE, POPHL), and when answering an interrupt.
When executing a call instruction or interrupt occurrence with interrupts enabled, the contents of the PC
and program status word (PSW) are stored in the stack
area. A push instruction stores the contents of DE or
HL in the stack area. See figure 3.
Figure 2.
Data Memory
(0) OOH
OOOOH
RESET vector
0010H
INIT vector
0020H
INTO/S vector
(59) 3BH
(60) 3CH
PPG MOdto Section
0030H
INT1 vector
4 x 4
(63) 3FH
(64) 40H
Dire ct/lndirect
Ad dress Area
256 x 4
' 'r'
256 x 8
Figure 3.
192 x 4
(255) FFH
83-002939A
Push, Call, Interrupt
Push Instruction
3.84ox8
60 x 4
Display iata Area
Program Memory Map
OOOOH
Data Memory Map
Call Instruction/Interrupt
Stack
Stack
D
SP-4
~
SP-3
PSW
SP-2
E or L
SP-2
pe3- PCO
SP-1
o or H
SP·1
PC7,PC4
!
1FFFH
PCll-PCS
OOCOH
OOCFH
OODOH
Reference table (16 x 8)
for LHL T instruction
83-002940A
Reference table (48 x 8)
for CAL T instruction
83-002938A
3-205
NEe
IlPD7519/19H
Clock Generator
The system clock generator consists of a crystal
oscillator, a frequency divider, and a standby
(stop/halt) mode control circuit, as shown in figure 4.
When an external crystal is connected to X1 and X2,
the crystal oscillator generates the f xx . (The notation
'f xx ' is used when referring to crystal oscillation; 'f x'
is used when an external clock is input.) It is also
possible to obtain a clock by inputting an external
clock into X1 and an inverted clock to X2.
The frequency divider divides the output of the crystal
oscillator into four frequencies, as follows:
1/2 (pulse generator clock, PPG)
1/8 (system clock, ClH) ~PD7519H only
1/16 (system clock, ClH) ~PD7519 only
1/32 (system clock, Cll; and FIP controller clock,
FIP)
• 1/128 (timer/event counter clock)
•
•
•
•
the FIP controller and PPG, which use the fxx x 1/32
and fxx x 1/2, respectively. Cl is 1/2 frequency divided to supply the CPU (cp) clock. Cl is an input to the
clock control circuitry used to generate the clock
pulse (CP) used by the timer/event counter.
The standby mode control circuit consists mainly of
the stop and halt flip-flops. The stop flip-flop, when
set, stops the crystal oscillator. There is no input to
the frequency divider, so no clocks are output to the
~PD7519/7519H circuitry. The STOP instruction sets
the stop flip-flop, and RESET clears it. The halt flipflop, when set, inhibits the input to the 1/2 frequency
divider that generates cp, thereby stopping cp, A HALT
or STOP sets this flip-flop; it is reset by the RELEASE
signal (generated when an interrupt flag is set) or at
the falling edge of the internal reset (I RESET) signal.
(IRESET is released after a waiting time following the
release of the external RESET input.)
The system clock (Cl) may be 1/8 (~PD7519H), 1/16
~PD7519) or 1/32 frequency-divided, depending on the
state of expansion mode register bit 2 (EM2)' EM2 =
1 selects 1/8 ~PD7519H) and 1/16 ~PD7519), and EM2
= 0 selects 1/32. Cl is supplied to all circuits except
Figure 4.
Clock Generator Circuit
r---------------.~--RESET
~---..._t__--STOP
[Note 1]
"""'---~----HALT
[Note 1]
STOP F/F
Frequency Divider
1/2
11128
1 - - - - - - HALT RELEASE
' - -_ _ _ I RESET ( """"--
)
t-------- ~ (to CPU)
' - - - - - + - - - 1 - - _ - - - - - - - - - _ CL (System Clock)
' - - - - - - - - - - - - -_ _ 10 Timerlevent counler
Note:
[1]
Instruction execution.
l...--------------_~FIP
' - - - - - - - - - - - - - - - - - - - - - -___
(10 FIP conlroller)
~PPG
(10 pulse generalor)
83·0029418
3-206
NEe
J-lPD7519/19H
Figure 6.
Clock Control Circuit
This circuit consists of a 4-bit clock mode register
(CMo-CM3), three prescalers, and a multiplexer, as
shown in figure 5. The circuit generates the clock
pulse (CP) input to the timer/event counter from the
following inputs:
Clock Mode Register
Clock Mode Register
I CM31 CM21cM11 CMO I
CM2 CM1
• System clock (CL)
• 1/128 divided clock from the crystal oscillator
(fxx/128)
• External EVENT pulse
Bits CMo-CM2 determine the clock input selection
and divide ratio. CM3 gates the output of a timer out
signal from the PTOUT (P21) pin. When CM3 = 1, output from the timer out flip-flop (TOUT) is output to P21.
Executing an OP or OPL instruction loads the clock
mode register.
CL x~
256
0
0
0
0
0
1
0
a
1
1
0
1
EVENT input
1
a
0
CL x 1
32
1
0
1
1
1
1
1
0
1
CM3
0
I
CMO
1
fxx~
8192
orfxx )(~
8192
fxx~ orfxx )(~1024
1024
Inhibit
Designation of Timer Out F/F Output
I
Stop
Output
I
83-002943A
The format of the clock mode register is shown in
figure 6.
Figure 5.
Il
Clock Control Circuit
Internal Bus
to
Tim~~~~~:~ _ - - - - - - - - - - - l
~--------------~-~-~~
128
Event 0 - - Note:
(1) Instruction execution.
Prescaler 2
(1/8)
II
:><>----1==t=t===l:J
Prescaler 3
(1/8)
~-------CP
(to Timer/Event
Counter)
83-002942B
3-207
NEe
",PD7519/19H
Timer/Event Counter
Serial Interface
This counter consists of an 8-bit count register, an
8-bit modulo register, an 8-bit comparator, and a timerout flip-flop, as shown in figure 7.
The serial interface, used for serial data 1/0, consists
of an 8-bit shift register, a 4-bit shift mode register,
and a 3-bit counter, as shown in figure 8. Figure 9
shows the serial shift timing.
The 8-bit count increments at every rising edge of the
clock pulse (CP). Executing the TIMER instruction, a
RESET input, or a coincidence signal from the comparator clears it to O.
The modulo register determines the INTT signal interval. The contents of this register are set via the
TAMMOD instruction. RESET sets the contents to
OFFH.
The timer-out flip-flop inverts with every INTT signal
output from the comparator. Its output, TOUT, can be
sent to the PTOUT pin when bit 3 (CM3) of the clock
mode register is set. TOUT may also be used as a
serial clock source to the serial interface.
Figure 7.
Structure of the Timer/Event Counter
TCNTAM -.....----+1
[Note 1]
CP
Note:
[1] Instruction execution.
PTOUT
83-002944A
3-208
The serial clock (SCK) controls the serial data communication rate. An 8-bit byte clocks into the serial
input (SI) port or out of the serial output (SO) port starting with the MSB. Data transmission occurs synchronously with the falling edge of SCK. Data reception
occurs synchronously with the rising edge of SCK.
The 3-bit counter counts the number of serial clock
pulses. When a byte of serial data is transferred, an
internal interrupt signal (INTS) is generated. Selecting
INTS (setting SM3 of the shift mode register to 0) sets
the interrupt request flag, INTO/S ROF.
The end of transfer of each byte can also be verified
by testing INTS ROF with the SKI instruction instead
of interrupt processing.
NEe
Figure 8.
J..tPD7519/19H
Serial Interface Block Diagram
POa/510------I
JI----4-+-t+-t
5M3
[Note 2]
P02/50o---+-----+-+-<
to--+------f-TOUT
RI----<>---.. INT5
POo/INToo------I
> - - - - -..
R5
............r-----, Q
F/F
514----510
[Note 1]
Note:
[1) Indicates instruction execution.
[2) SM3 to the interrupt controller.
83·0029458
Figure 9.
Serial Shift Timing
INT5
generating
timing
51
the internal serial interrupt INTS. Selection of the interrupt is programmable and depends on the
application.
Table 1.
fxx
50
83·002946A
Low Speed Mode
High Speed Mode
6.55 MHz
102.4 kHz
409.6 kHz (",PD7519H)
4.19 MHz
65.5 kHz
262 kHz (",PD7519H)
4.19 MHz
65.6 kHz
131 kHz (",PD7519)
CPU Clock (cj»
Table 2.
When the SIO instruction executes, eight CPU clock
pulses (~) are supplied to the serial interface for the
serial clock and output from SCK. After the eighth
clock, SCK is fixed high level, automatically stopping
serial data 110 after one byte has transferred.
Source
SCK does not have to be software controlled. Its
transfer rate is determined by the frequency of ~. See
table 1.
SCK Frequencies
Interrupt Specifications
Int/Ext
Priority
Vector Address
INTT (coincidence signal
from timer/event counter)
int
10H(16)
INTO (interrupt signal from
POo terminal)
ext
20H(32)
INTS (end of transfer
signal from serial interface)
int
20H(32)
INT1 (interrupt signal from
INT1 terminal)
ext
30H(48)
Interrupt Function
There are two external and two internal interrupts,
with the specifications listed in table 2. The external
interrupt INTO uses the POo port pin as the interrupt
signal input, and has the same interrupt process as
3-209
NEe
tJPD7519119H
Interrupt Sequence
When an interrupt goes active, the following occur:
• A corresponding interrupt request flag is set.
• The interrupt master enable flip-flop is reset.
• The contents of the PC and PSW are saved in the
stack.
• An interrupt start address is generated and jumped
to.
• The interrupt request flag set by the interrupt is
reset.
Figure 10.
Two machine cycles are required for interrupt execution, one for saving the return address and one for
jumping to the interrupt start address. If several interrupts occur simultaneously, all respective request
flags are set, and the interrupt with the highest priority is processed. The remaining interrupts are pending
until serviced by reenabling the master interrupt flipflop or until their interrupt request flags are reset by
executing a SKI instruction.
Figure 10 is a block diagram of the interrupt control
circuit.
Interrupt Control Circuit Block Diagram
[Note 1)
SM3
[Note 2)
INT1
CL-
R
INT1
ROF
INTS
POolINTO
Nonsync
Edge
Detect
S
R
INTO/S
ROF
Vector
Address
Gen
[Note 1)
SIO
INTT
Note:
[1] Indicates Instruction execution.
[2] SM3 is bit 3 01 the shift mode register
(selection of INTO or INTS).
Nonsync
Edge
Detect
S
R
INTT
ROF
[Note 1) Timer
HALT Release
83·0029476
3-210
NEe
J..tPD7519/19H
FIP Controller/Driver
The FIP controller/driver consists of 60 4-bit nibbles
of display memory (000-03BH of data RAM), a 4-bit
display mode register (DM3-DMo), a 4-bit timing mode
register (TM3.:rMo), a 4-bit blanking mode register
(BM3-BMo), an output selector, and a high voltage output driver. See figure 11.
The FIP controller/driver has 24 outputs for directly
driving a high voltage vacuum fluorescent display:
• 8 segment signal outputs (SO-S7)
• 8 timing signal (grid) outputs (To.:r7)
• 8 timing or segment outputs (Ta/Sa.:r15/S15
The content of the display mode register determines
which of five display modes is available to the user.
The modes are as follows:
The content of the timing mode register determines
the number of display digits (1-16), and controls the
number of timing signals (To-T15) output. Timing
signals drive the grids of vacuum fluorescent display
tubes. The voltage on the grid will determine the
brightness of a digit (made up of one or more
segments) or if the digit will be turned on or off.
The width of the timing signal pulse can be adjusted
at eight independent steps by the value loaded into
the blanking mode register. This function is useful for
dimming control and for preventing display cross-talk
of adjacent digits.
The active level of the timing signal can be designated
high or low by bit DM3.
• Static mode
- 24 static output
• Dynamic mode
- 8 segment mode
- 12 segment mode I
- 12 segment mode II
- 16 segment mode
Figure 11.
FIP Controller/Driver Block Diagram
On-chip Bus
Display Data Memory
(60 x 4 bits max)
Segment Data Latch (16 bits)
SO-57
83-002948B
3-211
NEe
IlPD7519119H
Display Mode Register (OM)
This 4-bit write-only register (OM3-0MO) determines
the display mode (dynamic, static, and off) of the FIP
controller/driver. It also determines the active level of
the display timing signals. This is shown in figure 12.
Figure 12_
The OM register has an output address of aBH and
is accessed by the output instructions OP and OPL
when bit EM3 of the expansion mode register is set.
The OM register is cleared by a RESET.
Figure 13 shows a display example in 12 segment
mode I.
Display Mode Register Format
lOM31DM21DMl DMOJ
L-~
0
0
0
Display OFF
0
0
1
Use Inhibited
I---0
1
0
0
1
1
1
0
0
Static display (24 segment output)
8 segment mode (up to 16 digits)
I---1
0
1
1
1
1
r---1 1 0
r----
o
Dynamic
Display
12 segment mode I (up to 15 digits)
12 segment mode II (up to 11 digits)
16 segment mode (up to 11 digits)
I
Timing signal Tn: active high
I
1 Timing signal Tn: active low
I
I
83-002949A
Figure 13.
Display Example in 12 Segment Mode I
Display Data Memory
2BH
29H
28H
{OM = [x(101)
TM = (1010)
1 EH
I ~
TIS T14 T13 T12
515 514
57 56 55 54 53 52 51 SO
S13 s,;
I
k
j
i
h
g
,
e
d
c
b
Ja
23H
21H
20H
lFH
lDH
lCH
lBH
19H
18H
17H
15H
14H
13H
llH
10H
OFH
ODH
OCH
OBH
09H
08H
07H
05H
04H
03H
01H
OOH
b3
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
b2
0
0
0
1
0
0
0
0
0
0
0
bl
0
0
0
0
0
0
1
0
0
0
0
bO
0
0
0
0
0
0
0
0
0
0
0
b3
0
0
0
0
1
1
0
0
1
1
1
b2
0
0
0
0
1
1
0
0
0
0
1
bl
0
0
0
0
0
0
0
0
0
1
1
bO
0
0
0
0
0
1
0
0
1
1
0
b3
0
1
1
0
1
1
0
1
1
0
1
b2
0
1
1
0
1
0
0
1
1
0
0
bl
bO
1
0
0
0
0
1
0
0
1
0
0
iI
iI
iI
iI
iI
:
iI
iI
II
:
II
I
I
I
+
Tll/Sll Tl0/Sl0
1
27H
25H
24H
I
AMa
PMb
0
I
I
I
I
I
I
I
+
+
Tg/Sg
Ta/Sa
SUN
MON
~1
WED
1
2
3
4
I
I
I
I
I
I
I
I
I
I
I
I
4n + 1
4n
I
I
+
+
+
+
+
+
+
+
T7
Ts
Ts
T4
T3
T2
Tl
To
THU
FRI
SAT
5
6
7
I I I I
4n + 3
a
I I I I I·d I I I-I I I I-I I-I I I ,fglb
I=10 I=10 1~lo 1]0 [10 I]0 [10 [10 Clo e(~~
-
-
8
9
i 10 h
83-0029508
3-212
NEe
J..lPD7519/19H
Standby Function
Two standby modes, stop and halt, hold device power
consumption to a minimum. Stop mode is entered via
the STOP instruction, and halt mode is entered via the
HALT instruction. In stop mode, all clocks are
stopped. In halt mode, only the CPU clock (+) is
stopped.
Stop mode can only be released by a RESET. Halt
mode may be released either by a RESET or by the
setting of an interrupt request flag.
Stop Mode
In stop mode, the contents of memory are retained,
and all other functions are stopped. RESET releases
stop mode.
In stop mode, the X1 input is internally shorted to Vss
in order to hold the crystal oscillator leakage to a
minimum. A system using stop mode cannot use an
external clock.
Halt Mode
When no interrupt flags are set, the HALT instruction
causes the device to enter halt mode. In this mode,
only stops; all other clocks continue to operate. The
following functions continue to operate:
+
• Clock oscillation
• Frequency division and output of clocks other
than
• Event input
• Timer/event counter
• Serial interface (except when is used as SCK)
• FIP controller/driver
• PPG
• Interrupts (INTO, INTS, INTT, INT1)
• RESET
Since a set interrupt flag releases the device from halt
mode, this mode cannot be entered if an interrupt request flag is set. It is therefore necessary to reset the
request flag(s) either by answering the interrupt(s)
(setting the interrupt master enable F/F and process
interrupt) or by executing the SKI instruction.
+
+
In halt mode, CPU power consumption is eliminated.
To hold power consumption to a minimum, all unnecessary circuits should be inactive and the steps
below should be taken:
•
•
•
•
Set the system clock (CL) to low speed
Set the FIP controller/driver to the off mode
Set the PPG for static operation
Stop SCK input
Low Supply Voltage Data Retention
(J,tPD7519/7519H only)
Data retention is possible with VDD as low as 2 V. VDD
should be lowered after the device is put in stop
mode, and while RESET is inactive. Stop mode cannot be released in low voltage data retention mode;
VDD should first be raised to normal operation.
Release of Stop Mode
RESET releases stop mode. On RESET's rising edge,
the device mode changes to halt mode, starting clock
oscillation. At the falling edge of RESET, a waiting
time (about 62.5 ms/4.19 MHz, 40 ms/6.55 MHz)
elapses, allowing for stabilization of crystal operation,
following which halt mode is released. After normal
RESET operation, the CPU begins program execution
from address OOOOH.
In the release operation, the contents of data memory
are retained while the contents of other registers
become undefined.
Power-on Reset Circuit
An example of the simplest power-on reset circuit
using a resistor and capacitor is show in figure 14.
Figure 14.
Power-on Reset Circuit
+5V
_______ RESET
83·0029518
3-213
NEe
JAPD7519/19H
Application
The ",PD7519/7519H has a variety of flexible powerful
functions and is best suited for the following
applications:
•
•
•
•
•
•
Video tape recorders
Plain paper copiers
Electronic cash registers
Telephone sets
Electronic scales
Automobiles
Figures 15·18 show how to apply the device to a
digital tuning system, a telephone, an ECR, and
automotive equipment.
Figure 15.
Digital Tuning System Application
Tuning Signal - - - - - - - - - - - - - - - - - - - - ,
Electronic Tuner
(Analog Output)
....- - - - - - - - - 1
LPF
PPO
Keyboard
I'PD7519/7519H
System
Control
P 10· P1 3
Voo
Vss
83·0029528
3-214
NEe
Figure 16.
J..lPD7519/19H
Telephone Application
Figure 18.
Automotive Equipment Application
Hook Switch, etc.
Line Control
Telephone Line
(Dial Pulse)
Analog Input
• Fuel
• Temperature
• Battery
Keyboard
cf'1 Buzzer
1'"
melody
83·0029558
83·002953A
Figure 17.
ECR Application
Keyboard
Buzzer
Melody
DCJ
J
PPO
I
I
83·002954A
3-215
NEe
~PD7519/19H
Absolute Maximum Ratings
TA
= 25°C
-0.3Vto +7V
Supply voltages, Voo
VLOAO (",PD751917519H)
(V DO - 40) to (Voo + 0.3)
(V DO - 12) to (Voo + 0.3)
Input voltage, VI
-0.3 V to (Voo + 0.3)
Output voltage, Display outputs, Vo
(V DO - 40) to (Voo + 0.3)
Other outputs, Voo
-0.3 V to (Voo + 0.3)
Output current high, IOH
Per pin, other than display outputs
-15 mA
Per pin, SO-S7
-15 mA
-30 mA
Total, display outputs, ",PD751917519H
-120 mA
Display outputs, /-lPD75CG19175CG19H
-90 mA
Total, other than display outputs
-20 mA
17 mA
____T_ot_al_,_al_lo_u~tp_u_t~po_rt_s_______________________ 60mA
Total power consumption (1), PT
Plastic flat package (/-lPD751917519H)
Plastic QUIP, (/-lPD751917519H)
400 mW
ExamRle
Configuration:
9 segments x 11 digits, 4 LED outputs
Voo
5 V ± 10%,4.19 MHz oscillation
Segment pin
5 mA (max)
=
Timing pin;;; 15 mA (max)
LED output pin
10 mA (max)
Vacuum fluorescent display (VLOAO)
=
- 30 V
Consumption:
600 mW
Operating temperature, TOPT
Storage temperature, TSTG
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
3-216
1. CPU power consumption. Voo(max) x I001(max)
2. Power consumption of output pins. This includes both
normal output and display output. Calculate the total
consumption of each output pin to which the maximum
current flows.
3. Power consumption of on-chip pull-down resistors (mask
option).
=
Output current low, IOL
Per pin
Note:
(1) Calculation ofPT: There are three kinds of power consumption,
the total of which shou Id be less than the total power consumption (PT) in this specification. Use of less than 80% of PT is
recommended. The three different power consumptions are as
follows:
(1) CPU
5.5 V x 2.0 mA = 11 mW
(2) Output pins
Segment pins: (5/7 x 2 V) x 5 mA x 9
Timing pins: 2 V x 15 mA = 30 mW
LED output pins: (10/15 x 2 V) x 10 mA
(3) Pull-down resistors
(30 + 5.5 V)2/80 kO x 10
158 mW
= 64 mW
x 4 = 53 mW
=
Therefore, PT
= (1)
+ (2)
+
(3)
= 316 mW
NEe
J..lPD7519/19H
Capacitance
Operating Supply Voltages
TA
TA = -10°C to
= 25°C; Voo = 0 v
Limits
Parameter
Symbol
Input capacitance
CI
Output capacitance,
Display outputs
Other outputs
Co
liD capacitance
Cia
Min
Typ
Max Unit
15
pF
35
pF
15
pf
15
pF
Test
Conditions
fC = 1 MHz
Unmeasured
pins are connected to 0 V
+ 70°C
limits
Parameter
Min Max Unit
CPU (1)
/oIPD75191
75CG19
4.0 6.0
V
2.5 6.0
V
Test
Conditions
fx = 0.4 MHz to 4.2 MHz High speed
mode,
fxx = 3.5 MHz to
4.2 MHz
EM2=1
Low speed
mode,
EM2=0
4.0 6.0
High speed
V fx, fxx = 4.2 MHz to
mode,
V 6.6 MHz
fx = 0.1 MHz to 4.2 MHz EM2=1
fxx = 3.5 MHz to 4.2 MHz
4.5 6.0
V
2.5 6.0
V
Crystal oscilla- 2.7 6.0
tion circuit (2)
/oIPD75191
2.85 6.0
75CG19
V
C1 = 10 pF
C2 :s 10 pF
V
C1 = 10 pF
C2 :s 22 pF
CPU (1)
/oIPD7519HI
75CG19H
4.5 6.0
Low speed
mode,
fx = 0.1 MHz to 4.2 MHz EM2=0
fxx = 3.5 MHz to 4.2 MHz
fx, fxx = 4.2 MHz to 6.6
MHz
Crystal
Oscillator
External
clock
2.5 6.0
V
Crystal oscilla- 4.5 6.0
tion circuit (2)
/oIPD7519HI
2.7 6.0
75CG19H
V
fxx = 4.2 MHz to 6.6 MHz Crystal
C1 = 10 pF, C2 :s 10 pF Oscillator
V
C1 = 10 pF, C2 :s 10 pF
fxx = 3.5 MHz to 4.2 MHz
2.85 6.0
V
C1 = 10 pF, C2 :s 22 pF
fxx = 3.5 MHz to 4.2 MHz
2.6 6.0
V
Display
controller
4.0 6.0
V
PPG
4.0 6.0
V
Port 1
2.5 6.0
V
Port output mode
4.0 6.0
V
liD expander mode
External
clock
Note:
(1) Except the crystal oscillation circuit, display controller, PPG,
and port 1.
(2) The circuits in figures 19 and 20 are recommended.
3-217
I
NEe
J-LPD7519/19H
DC Characteristics
=
TA
-10°C to + 70°C
",PD7519/7519H: Voo
2.5 Vto 6 V; ",PD75CG19/75CG19H: Voo
=
=5 V
± 10%
Limits
Parameter
Input voltage high
Input voltage low
Output voltage high
Output voltage low
Input leakage current high
Symbol
Min
Typ
Max
Unit
Test
Conditions
VIH1
0.7 VDD
VDD
V
VIH2
VDD -0.4
VDD
V
X1, X2 (1)
VIL1
0
0.3 VDD
V
Other than X1, X2
VIL2
0
0.4
V
X1, X2 (1)
VOH
VDD -1.0
V
VDD -0.5
V
= -1 rnA
= -100!-IA
VDD = 5 V ± 10%, IOL = 1.6 rnA;
",PD7519/19H only, IOL = 400!-IA
VI = VDD; other than X1, X2
VI = VDD; X1, X2
VI = 0 V; other than X1, X2
VI = 0 V; X1, X2
",PD75CG19H only VI = 0 V, 10 - 17
Vo = VDD
Vo = 0 V; other than display outputs
Vo = VLOAD = VDD-35 V; display outputs
VPRE = VDD-9 V ±
SO-S7
",PD75CG 19/75CG 19H VOD = VDD-2 V
VDD = 4 V to 6 V
VOL
0.4
0.5
V
V
!-IA
Other than X1, X2
VDD
= 5V ±
10%,IOH
",PD7519/19H only, IOH
ILlH1
3
ILlH2
20
/AA
Input leakage current low
ILlL1
-3
!-IA
ILlL2
-20
!-IA
Input leakage current
IlL
-200
!-IA
Output leakage current high
ILOH
3
!-IA
Output leakage current low
ILOL1
-3
!-IA
ILOL2
-10
-7
!-IA
rnA
-4
rnA
-15
rnA
To-T15
-10
rnA
",PD75CG 19175CG 19H
-3
rnA
SO-S7 VPRE
-2
rnA
/APD75CG 19175CG 19H VOD
VDD = 4 V to 6 V
-7
rnA
To-T15
-5
rnA
/APD75CG19/75CG19H
Display output current
10D
=0V
On-chip pull-down resistance,
",PD7519
RL
80
140
220
kO
VOD - VLOAD
= 35 V
On-chip pull-down resistance,
/APD7519H
RL
40
70
120
kO
VOD - VLOAD
=
3-218
35 V
= VDD
-2 V
1 V(2)
NEe
f..tPD7519/19H
DC Characteristics (cont)
=
TA
-10°C to + 70°C
/JPD7519/7519H: Voo
2.5 V to 6 V; /JPD75CG19/75CG19H: Voo
=
=5V
± 10%
Limits
Parameter
Supply current, /JPD7519 (3)
Symbol
Min
Max
Unit
600
2000
/JA
High speed Voo = 5 V ± 10% 4.19 MHz crystal
C1 = C2 = 10 pF
200
700
800
120
400
iJA
iJA
iJA
Low speed Voo
260
1003
0.1
10
/JA
Stop mode
1001
1002
700
2000
800
iJA
iJA
High speed 4.19 MHz crystal C1
350
1001
1002
2.0
6.0
mA
High speed 6.55 MHz crystal
0.6
1.9
mA
Halt mode C1
1001
1.3
4.0
mA
High speed 4.19 MHz crystal Voo
C1 = C2 = 10 pF
250
800
/JA
Low speed Voo
1002
450
1500
150
400
0.1
20
0.1
10
iJA
iJA
iJA
iJA
Low speed halt mode Voo = 5 V ± 10%
1.2
3.6
mA
High speed Voo = 5 V ± 10%
6.55 MHz crystal C1 = C2 = 10 pF
1.0
3.0
mA
High speed halt mode Voo = 4.75 to 5.5 V 4.19
MHz crystal C1 = C2 = 10 pF
350
1000
iJA
Low speed halt mode Voo = 5 V ± 10%
4.19 MHz crystal C1 = C2 = 10 pF
20
iJA
1001
1002
Supply current, /JPD75CG19 (3)
Supply current, /JPD7519H (3)
1003
Supply current, /JPD75CG19H (3)
Test
Conditions
Typ
1001
1002
1003
=3V±
10%
=5V±
=3V±
Low speed halt mode Voo
Low speed halt mode Voo
10%
10%
= C2 = 10
= 5 V ± 10%
Low speed halt mode Voo
pF
= C2 = 10 pF Voo = 5 V ± 10
= 5 V ± 10%
=3V±
II
10%
Low speed halt mode Voo = 3 V ± 10%
Voo = 5 V ± 10% Stop mode
Voo
= 3V ±
10%
Voo
=5V±
10% Stop mode
Note:
(1) The circuits in figures 19 and 20 are recommended.
(2) The external circuit in figure 21 is recommended.
(3) The display controller and PPG are not operated.
3-219
NEe
I-lPD7519/19H
Figure 19.
AC Characteristics
Crystal
TA
= -10°C to
+ 70°C
Clock Operation, jiP07519/75CG19
=
J.lPD7519: voo
2.5 V to 6 V
J.lPD75CG19: voo
5 V ± 10%
X2
X1
=
limits
HDI--
Figure 20.
r
e'I
C1 = 10 pF
C2 :s 22 pF
83·002956A
External Clock
Min
Typ
Max
Unit
System clock
oscillation
frequency
fxx
3.5
4.19
4.2
MHz Crystal
oscillation (1),
(2)
System clock
input frequency
fx
0.1
X1, X2 input
pulse width high
and low
tXH
100
ns
tXL
100
ns
MHz External clock
(1)
EVENT input
frequency
kHz
80
X1
EVENT input
pulse width high,
low
~
Test
Conditions
Symbol
Parameter
tEH
External clock
(1)
Voo = 4.0 V to
6.0 V
kHz J.lPD7519 only
6.25
J.ls
Voo = 4.0 V to
6.0 V
J.ls
J.lPD7519 only
Note:
High·Speed CMOS Inverters
(1) The circuits in figures 19 and 20 are recommended.
External Clock
(2) Refer to the Operating Supply Voltages tables.
83·002957A
Clock Operation, jiP07519H/75CG19H
Figure 21.
=
J.lPD7519H: voo
2.5 V to 6 V
J.lPD75CG19H: voo
5 V ± 10%
External Circuit
=
limits
VDD~~~----~-----------o -5
3.31'F
V
Parameter
RD9.1EL
68 k!l
-30
VLOAD
Vss
-=
v
Note:
RD9.1EL: Zener Diode (NEC)
Zener Voltage = 8.29 V to 9.30 V
83·002958A
Symbol
System clock
oscillation
frequency
fxx
System clock
input
frequency
fx
Test
Conditions
Min
Typ
Max
Unit
3.5
4.19
4.2
Crystal
MHz oscillation (1), (2)
4.2
6.55
6.6
0.1
4.2
4.2
6.6
X1, X2 input
pulse width
high, low
tXH
100
tXL
75
EVENT input
frequency
fE
EVENT Input
pulse width
high, low
tEL
6.25
MHz VOO =
4.5 V to 6.0 V
External
MHz clock (1)
MHz VOO =
4.5 V to 6.0 V
ns
External
clock (1)
ns
Voo = 4.5 V to 6.0 V
410
kHz Voo = 4.0 V to 6.0 V
80
kHz J.lPD7519H only
J.ls
Voo = 4.0 V to 6.0 V
J.lPD7519H only
Note:
(1) The circuits in figures 19 and 20 are recommended.
(2) Refer to the Operating Supply Voltages table.
3-220
NEe
J.tPD7519/19H
AC Characteristics (cont)
TA
= -10°C to
AC Characteristics (cont)
+ 70°C
TA
= -10°C to
+ 70°C
Port 11/0 Operation, pPD7519175CG19
Port 1 I/O Operation, pPD7519HI75CG19H
",PD7519: voo
2.5 V to 6 V
",PD75CG19: voo
5 V ± 10%
0.1 MHz ~ fx, fxx ~ 4.2 MHz
",PD7519H: voo
4.5 V to 6 V
",PD75CG19H: Voo
4.75 V to 5.5 V
4.2 MHz ~ fx, fxx ~ 6.6 MHz, Low Speed Mode(1) (EM2
=
=
=
Limits
Unit
Test
Conditions
400
ns
Port output mode
100
ns
Symbol
Min
Port 1 output setup
time (to PSTBt)
tpST
Port 1 output hold
time (after PSTBt)
tSTP
Parameter
Max
PSTB pulse width low
tSTL1
600
ns
Output data set-up
time (to PSTBt)
tOST
400
ns
Output data hold time
(after PSTBt)
tSTD
100
ns
Input data valid time
(after PSTB+)
tSTDV
Input data floating
time (after PSTBt)
tSTDF
Con~et-up
time
tesT
Control hold time
Output command
Input command
tSTe
PSTB pulse width low
tSTL2
=
Limits
Unit·
Test
Conditions
400
ns
Port output mode
100
ns
Symbol
Min
Port 1 output setup
time (to PSTBt)
tpST
Port 1 outp!!!.Jlpld
time (after PSTBt)
tSTP
Parameter
Max
PSTB pulse width low
tSTL1
600
ns
Output data set-up
time (to PSTBt)
tOST
400
ns
Output data hold time
(after PSTBt)
tSTD
100
ns
ns
Input data valid time
(after PSTBt)
tSTDV
a
ns
Input data floating
time (after PSTBt)
tSTDF
a
ns
400
ns
Control set-up time
(to PSTB+)
tesT
400
ns
ns
ns
Control hold time
Output command
Input command
tSTe
100
ns
PSTB pulse width low
tSTL2
850
1/0 expander
mode VOO =
4 V to 6 V
(to PSTB+)
a
80
1200
= 0)
850
100
a
1200
80
1/0 expander
mode VOO =
4 V to 6 V
IE
ns
ns
ns
ns
Note:
Port 1 liD Operation, pPD7519HI75CG19H
=
(1) The ",PD82C43/8243H, etc, cannot interface with the ",PD7519H
in high speed mode (EM2
1).
=
",PD7519H: Voo
2.5 V to 6 V
",PD75CG19H: Voo
5 V ± 10%
0.1 MHz ~ fx, fxx ~ 4.2 MHz
=
Limits
Unit
Test
Conditions
250
ns
Port output mode
tSTP
100
ns
Symbol
Min
Port 1 output setup
time (to PSTBt)
tpST
Port 1 output hold
time (after PSTBt)
PSTB pulse width low
Parameter
Max
tSTL1
450
ns
Output data set-up
time (to PSTBt)
tOST
200
ns
Output data hold time
(after PSTBt)
tSTO
100
ns
Input data valid time
(after PSTBt)
tSTOV
Input data floating
time (after PSTBt)
tSTOF
Control set-up time
(to PSTB+)
tesT
Control hold time
Output command
Input command
tSTe
PSTB pulse width low
tSTL2
700
1/0 expander
mode VOO =
4 V to 6 V
ns
ns
100
ns
100
a
750
80
ns
ns
ns
3-221
NEe
J.lPD7519/19H
AC Characteristics (cont)
AC Characteristics (cont)
TA
TA
= -10°C to
+70°C
= -10°C to
+70 O C
Serial Interface Operation, pPD7519/75CG19
Serial Interface Operation, pPD7519H/75CG19H
",PD7519: voo
2.5 V to 6 V
",PD75CG19: voo
5 V ± 10%
",PD7519: voo
2.5 V to 6 V
",PD75CG19: Voo
5 V ± 10%
=
Limits
Parameter
SCK cycle time
SCK pulse width
high, low
Symbol
SI set-up time
(to SCKt)
time (after
Max
Unit
",5
Input Voo =
4 V to 6 V
12.5
",5
",PD7519 only
4.9
",5
Output Voo
4 V to 6 V
10
",5
",PD7519 only
1.3
",5
Input Voo =
4 V to 6 V
65
",5
",PD7519 only
2.2
",5
Output Voo
4 V to 6 V
4.5
",5
",PD7519 only
300
ns
Voo = 4 V
to 6 V
1000
ns
",PD7519 only
450
ns
Voo = 4 V
to 6 V
1000
ns
",PD7519 only
850
ns
Voo = 4 V
to 6 V
2000
ns
",PD7519 only
tSIK
tKSI
tKSO
Test
Conditions
3.0
tKH
SCKt)
SO ou~ delay time
(after SCK~)
Min
tKCY
tKL
~old
=
=
=
Limits
Symbol
Parameter
SCK cycle time
Min
Max
Unit
2.1
",5
Input Voo =
4 V to 6 V
12.5
",5
",PD7519H only
(1)
",5
Output Voo
4 V to 6 V
tKCY
=
(2)
SCK pulse width
high, low
'"
Input Voo =
4 V to 6 V
6.5
",5
",PD7519H only
(3)
",5
Output Voo
4 V to 6 V
(4)
",5
",PD7519H only
300
ns
Voo = 4 V
to 6 V
1000
ns
",PD7519H only
450
ns
Voo = 4 V
to 6 V
1000
ns
",PD7519H only
500
hs
Voo = 4 V
to 6 V
2000
ns
",PD7519H only
tSIK
m.J!old time (after
SCKt)
tKSI
SO ou~ delay time
(after SCK~)
tKSO
",PD7519H only
",5
=
SI set-up time
(to SCKt)
Note:
(1) High speed mode: 16/f x or 16/f xx
Low speed mode: 64/f x or 64/f xx
(2) 64/f x or 64/f xx
(3) High speed mode: 8/f x - O.B ",5, or B/fxx - O.B ",5
Low speed mode: 32/f x - O.B ",5, or 32/f xx - O.B ",5
(4) 32/f x - 2.0
3-222
",5,
=
0.7
tKH
tKL
Test
Conditions
or 32/fxx - 2.0
",5
=
NEe
f.,tPD7519/19H
Timing Waveforms
AC Characteristics (cont)
TA
= -10°C to
+70 0 C
AC Waveform Measurement Points (Except X1, X2)
Other Operations
/iPD7519/7519H: voo = 4.5 V to 6.0 V
/iPD75CG19/75CG19H: voo
4.75 V to 5.5 V
0.7 Voo
0.3 Voo
=
Test
Points
<
0.7 Voo
0.3 Voo
83-002909A
Limits
Parameter
>
Symbol
Min
INTO pulse width
high. low
tIOH. tlOL
10
/is
INT1 pulse width
high. low
t11H. tm
(1)
/is
RESET pulse width
high. low
tRSH. tRSL
Max
Test
Conditions
Unit
10
Data Retention Timing
H~STOPMode
I
/is
1\
Voo
VOOOR
Execution of
STOP Instruction
Note:
"
rData Retention MOde1
/"-----
=-.i
It
SRS
RESET
(1) 26/f x or 26/f xx
83-002959A
j.LPD75CG19/75CG19H EPROM Characteristics
TA
= -10°C to
+ 70°C; Voo
=5 V ±
10%
Clock Timing
Limits
Parameter
Symbol
Min
Typ
Max
Unit
Access time
tACC
700
ns
CE low set-up
time to data valid
tCE
700
ns
Data valid hold
time to CE rising
edge
tlH
Test
Conditions
X1 input
ns
0
EVENT Timing
Stop Mode Low Voltage Data
Retention Characteristics, j.LPD7519/7519H
TA
= -10°C to
+70 0 C
Limits
Parameter
Symbol
Min
Data retention
supply voltage
VOOOR
2.0
Data retention
supply current
IOOOR
RESET set-up
time
tSRS
Typ
0.1
Max
Unit
6.0
V
10
/i A
Test
Conditions
83-002961 A
EPROM Timing
VOOOR = 2 V
/is
CE
10·17
-----------(J
83-002962A
3-223
NEe
I-'PD7519/19H
Timing Waveforms (cont)
Strobe Output Timing
Interrupt Input Timing
INTO
INT1
83·002963A
Port 1 I/O Expander I/O Timing
(Rising
Edge)
INT1
(Falling
Edge)
Expander
Port
Output
83·002966A
RESET Input Timing
Expander
Port
Input
RESET
83·002967A
83·002964A
Serial Transfer Timing
SCK
SI---+---C
Output Data.
83·002965A
NEe
J..lPD7519/19H
Operating Characteristics, pPD7519/7519H
= 25°C
TA
100 vs (Voo - Voo) (V DO = 4 V to 6 V)
15.0
/
1/
Voo -
;;(
.sc
VPRE - 9 VI
I
/
/
c
~
U
I I
VVoo -
c.
:>
0
1//
5.0
c
)!I/
Ir//
~
/
V
;;(
.s
=5V
VPRE I
'"
4V
1
.-)...-. / I-"'"
VOoffi,
V
41----------IL--I--_~-+_----+_---___i
.2
I
I
Voo
Voo -
Voo
SO,S7
-
//i'
o
~ I-""
~ Voo - VPRE
Ih
en
=7V
1
...--r
I V ./
IJ
:>
VPRE
/
/'
10H vs (Voo - VOH)
1
V
I
.2 10.0
/
"
-100
Voo - VPRE
VPRE
o
Voo -
Voo (V)
Voo -
100 vs (Voo - Voo) (Voo = 4 to 6 V)
30
I
Voo -
VPRE - 9 V)V
Voo -
.sc
/
20
§
I /
/
/
,/
/
-
-~
Voo -
.s
I
-
VplRE
= 4 V-
~
c
~:J'
_
Voo To·T7
Voo
-100
VPRE ~ Voo -
Voo (V)
15
.2
-
T8/S8·T1S/S1S
"
;;(
=5V
1
Vo~
o I¥'
o
VPRE
/'
./
--,'"
II
/ / /'
11//
HJ/
=7V
Voo -
10L vs VOL
20
I
J
-t--1
./
I
II /
U
VPRE
/
I
;;(
~
/
VOH (V)
Voo
-
Voo = 3 V
10
~
Voo·= 2.5 V
u
:>
c.
:>
0
5
«
VPRE
~
~
Output Voltage Low, VOL (V)
3-225
NEe
iJPD7519/19H
Operating Characteristics, JlPD7 519H only
TA
= 25°C
100 vs Voo (fxx = 4.19 MHz)
100 vs fxx
1000
I---
~
..;!.
s~eed
c
~
g-
i::====-I----
I
50
..;!.
0
0
c
en
1-----+---+---+--__1"
10~_~
2.0
x21
X1
pFr,~flo
_ __ L_ _J __ _L__ _
3.0
4.0
J_1_~1
___
5.0
=
=
L_1_~~
6.0
100 vs fx
600
~
4"
.:i
Ext~SP
Clock
•• d
I~:'~:r
500 i - - - - - _ j _
i: 400
~
~ 3001-----~---~-~~~4_~~~~~~-__I
I
en
200r----lr~~~~~~~::~::~;;~~~~~
Clock Input Frequency
3-226
Ix (MHz)
~
500
Voo
0
>- 300 I-
~
en
=5V
400
200
P' : <
Supply Voltage, Voo (V)
700
a_
,/
~
100
0
>1i
-I____ I-_
Haiti MOde"::::,C::::-
..k-:::--:I-'
__ I----- Low Speed Haiti Mode
0
0
§
High
Low Speed M~I--'"'"
700 f- a - High Speed Halt MoJe
b - Low Speed Halt Mode
c - Low Speed Mode
600
I---"
High Speed Me!!!-
500
100
o
~
''''J S!P'J
I
...--
i--'b
I:::::::
I--b
a_
VDD = 3 V { -
c-
I _I - b
I
o
Clock Oscillation Frequency,
Ixx (MHz)
NEe
J..lPD7519/19H
Operating Characteristics, pPD7519 only
TA = 25°C
100 vs fxx
100 vs Voo
25°C,lxx = 4.19 MHz)=
(TA
I
<"
~
i
()
High Speed Mode
1000
r---ti
100
50
-Lo~ Speed Mod!-
V
~
1
Low Speed Halt Mode
o
10
f--
~
~
~,,~ tOO'
f--
High Speed Mode Voo
>-
/'
High Speed Halt Mode Voo = 5 V
(J)
I
<"
~
500
l 1 0 PF
j.,--- t---. Low Speed Mode Voo = 3 V
o
ro-+- Low Speed Halt Mode Voo
I
.~
Clock Oscillation Frequency, Ixx (MHz)
100 vs fx
25°C,lxx
S.55 MHz)
j
I
100
()
50
>-
~
r----
~-
--
F F=.-:
High spee1d
/
E
F= F=
~c
o
= f==
X1
r---
1
==
X2
~
'==
-
1 I
Supply Voltage, Voo (V)
~5ob-
k::::::
10 pF IS.55 MHz
10
ITAI=
>--
---
~
- 3V
o
Low spee~ Hal~ Mo~e
c:
(J)
I
High Speed Halt Mode
-Low Speed Mode
1000
.L-I-1
r--:r-
100 vs VOO
(TA
IV"
1.0
Supply Voltage, Voo (V)
High Speed Mode
=5V
V
...... V
()
~
illl
4.19 MHz :'
10 PF
1
2.0
c:
~
1
>-
f--
<"
~
~5ob-
iTA 1=
r- ~
500
~
(J)
~
High Speed Halt Mode
c:
~
I
10
I
-
P~
, - r---
~= ~ §
c:
V
~
V
Mide ~ool
= 5 V_ t-
,£'i"'"
()
>-
~ 1.0
V
(J)
/'
~~
-
V
o
o
IV"
~
l..--'
-I-'
.I. -'
I
High Speed
Ha:t Mode Voo
= 5 V-
1-' ....... -~
,...,~Low Speed
---...-
Mode
.... Low Speed Halt Mode
Clock Input Frequency, Ix (MHz)
3-227
J.lPD7519/19H
3-228
NEe
NEe
NEe Electronics Inc.
Description
The I-LPD7527A, I-LPD7528A, and I-LPD75CG28 are 4-bit,
single-chip CMOS microcomputers with the I-LPD7500
architecture and FIP direct-drive capability.
Note: This data sheet pertains to j.lPD7527A, j.lPD7528A,
and j.lPD75CG28. For simplification, the revision
letter (A) usually is omitted from the part numbers
within the data sheet.
The I-LPD7527 contains a 2048 x 8-bit ROM and a
128 x 4-bit RAM. The I-LPD7528 contains a 4096 x 8-bit
ROM and a 160 x 4-bit RAM.
The I-LPD7527/28 contains two 4-bit general purpose registers located outside RAM. The subroutine stack is implemented in RAM for greater depth and flexibility. The
I-LPD7527/28 typically executes 67 instructions with a
5I-Ls instruction cycle time.
The I-LPD7527/28 has one external and two internal
edge-triggered hardware-vectored interrupts. It also
contains an 8-bit timer/event counter and an 8-bit serial
interface to help reduce software requirements.
Thirty-one high-voltage lines are organized into the 3-bit '
output port 2, the 4-bit output ports 3, 8, and 9, and the 4bit I/O ports 4, 5, 10, and 11.
The low power consumption CMOS process allows the
use of a power supply between 2.7 and 6.0V. Current
consumption is less than 3.0 mA maximum, and can be
further reduced in the halt and stop power-down modes.
The I-LPD75CG28 is a piggyback EPROM version of the
I-LPD7527/28. Pin-compatible and function-compatible
with the final, masked versions of the I-LPD7527/28, the
I-LPD75CG28 is used for prototyping and for aiding in program development.
pPD7527A/28A
4-BIT, SI,NGLE-CHIP
CMOS MICROCOMPUTERS
WITH Flp® DRIVER
D Vectored interrupts: one external, two internal
D 8-bit timer/event counter
o 8-bit serial interface
o Standby function (HALT, STOP)
o Data retention mode
o Zero-cross detector on POolINTO input (mask
optional)
o System clock (JAPD7527/7528175CG28): on-chip RC
oscillator
o CMOS technology
o Low power consumption
D Single power supply
-I-LPD7527/7528: 2.7 to 6.0 V
-I-LPD75CG28: 5.0 V
Ordering Information
Part
Number
J.tPD7527AC / 28AC
MalFrequency
of Operation
Package Type
• 42-pin plastic DI P
610 kHz
J.tPD7527ACU /28ACU
42-pin plastic shrink DIP
610 kHz
J.tPD75CG28E
42-pin ceramic piggyback DIP
500 kHz
Pin Configurations
I-LPD7527/28, 42-Pin Plastic DIP or Shrink DIP
RESET
eL1
CL2
VpRE
V LOAD
P53
P52
P51
P50
P33
P40
Features
o
o
o
o
o
o
o
o
67 instructions
Instruction cycle:
-Internal clock: 51-Ls/400 kHz, 5 V
- External clock: 41-Ls/500 kHz, 5 V
Upwardly compatible with the I-LPD7500 series
product family
4,096 x 8-bit ROM (JAPD7528/75CG28)
2,048 x 8-bit ROM (JAPD7527)
160 x 4-bit RAM (JAPD7528/75CG28)
128 x 4-bit RAM (JAPD7527)
351/0 lines
31 high-voltage output lines that can directly drive a
vacuum fluorescent display (FIP)
Can select either a pull-down resistor or open-drain
output per 31 high-voltage outputs (mask optional)
FIP is the registered trademark for NEC's fluorescent indicator panel (vacuum
fluorescent display),
49·001078A
3-229
I
NEe
fAPD7527A/28A
Pin Configurations (cont)
/-LPD75CG28 EPROM
No.
/-LPD75CG28, 42·Pin Ceramic Piggyback DIP
Symbol
VDD
RESET
VLOAD
NCO 2 270MSEL
A791-:f6~Voo
A60 425 0 As
I
I
P52
P51
A505240 Ag
P50
I
I
A406 230All
P23
I
I
A30 7 220Vss
P22
I
I
A208210Al0
P21/PTOUT
A1 0 9200CE
I
I
Ao010 19017
P103
P102
I
I
10011 18016
PllJj
11012170 15
P1Do
I
I
12013 16014
Pl13
vSSy:.s9
13
P111
P110
EPROM address output
P03/S1
11-13,15-19
10-17
Data read input from the EPROM
P30
14
Vss
Connection to EPROM GND pin
20
CE
Chip enable output
22
P02/S0
vooO 1 280VoO
P53
Pl12
No connection
AO-A10
P01/SCK
CL2
VpRE
NC
3-10,21,
24,25
Vss
POo/INTO
CL1
P31
P32
Vss
Supplies EPROM OE signal
23
A11
Program counter MSB output
P42
26
VDD
Supplies Vee to the EPROM
P43
27
MSEL
Mode select input
VDD
Supplies high-level signal to MSEL
P33
P40
P41
POo
28
POl
P02
Note:
(1) Output drivers on ports 2-5 and 8-11 are mask-optional. Accordingly,
either an open-drain output or a pull-down resistor can be selected.
VLOAD is suitable for an output driver with a pull-down resistor.
P03
P90
P91
EPROM: 2732
P92
(2) Ports 2-5 are suitable as FIP segment signal outputs, and ports 8-11
are suitable for FIP digit signal outputs.
P93
Voo
Function
Connection to pin 21 of j.lPD75CG28
49-001079A
(3) Ports 8'-11 have high-current drive capability and can drive an LED
directly.
Pin Identification
Pin Functions, I-lPD7527 128 and
I-lPD75CG28
/-LPD7527/28 and /-LPD75CG28
No.
Symbol
Function
RESET
Reset input
2,3
CL1, CL2
Clock pins
4
VPRE
High-voltage predriver supply
5
VLOAD
High-voltage option resistor supply
6-9
P50-P53
High-voltage I 10 port 5
10,12
P23, P22
P21/PTOUT
High-voltage output port 2, and output
port from timer I event counter (PTOUT)
13-16
P100-P103
High-current, high-voltage I 10 port 10
17-20
P110-P113
High-voltage, high-current I 10 port 11
RESET
System reset (input).
CL1, CL2
Connection to the RC oscillator. CL1 is the external
clock input.
VPRE
Negative power supply for high-voltage output predrivers (for ports 2-5, 8-11).
21
VDD
Positive power supply
22-25
P90-P93
High-voltage, high-current output port 9
VLOAD
26-29
P8o-P83
High-voltage, high-current output port 8
30-33
P4o-P43
High-voltage I 10 port 4
34-37
P30-P33
High-voltage output port 3
Negative power supply for optional load resistors (pulldown resistors) of high-voltage output drivers (for ports
2-5,8-11). This pin is only on the /-LPD7527/28.
38
39
40
41
P03/S1
P02/.§2...
P01/SCK
POOl INTO
4-bit input of port 0; or serial data input
(SI), serial data output (SO), serial clock
I 10 (SCK), and external interrupt input
(INTO) or zero-cross detect input (POo).
4-bit, high-voltage 1/0 port 5.
42
Vss
Ground
P53-P50
P21-P23
3-bit, high-voltage output port 2.
3-230
ttfEC
JAPD7527A/28A
PTOUT
Pin Functions, I-lPD75CG28 EPROM
Output port from the timer/event counter.
MSEL
P103-P100
Changes the addressing area of the external EPROM
and the on-chip RAM (with a pull-down resistor). Connecting a jumper between socket pins 27 (MSEL) and 28
(voo) selects ",P07527 mode (2-Kbyte EPROM, 128 x 4bit RAM). Leaving MSEL open selects ",P07528 mode (4Kbyte EPROM, 160 x 4-bit RAM).
4-bit, high-voltage, high-current I/O port 10. Capable of
bit set/reset by SPBLlRPBL instructions.
P113-P110
4-bit, high-voltage, high-current 110 port 11. Capable of
bit set/reset by SPBLlRPBL instructions.
Ao-A10
Voo
Output the low-order 11 bits of the program counter
(PCO-PC10). Used as EPROM address signals.
Positive power supply.
A11
P93-P90
4-bit, high-voltage, high-current output port 9. Capable
of bit set/reset by SPBLlRPBL instructions.
When MSEL is high level, A11 outputs high-level signals.
When MSEL is open, A11 outputs the MSB of the PC,
which is used as the most significant address signal of
the 4-Kbyte EPROM 2732.
P83-P80
10- 17
4-bit, high-voltage, high-current output port 8. Capable
of bit set/reset by SPBLlRPBL instructions.
Input data read from the EPROM.
P43-P40
CE
4-bit, high-voltage I/O port 4.
Outputs the chip enable signal to the EPROM.
P33-P30
Voo
4-bit, high-voltage output port 3.
Pin 26 is electrically equivalent to the bottom Voo pin
and is used to supply Vee to the EPROM. Pin 28 is electrically equivalent to the bottom VOO pin and is used to
supply the high level signal to MSEL. Pin 1 connects to
pin 21 of ",P075CG28.
POO-P03
4-bit input port O. POO is also used as the zero-cross detection input.
SI
Serial data input.
so
Vss
Pin 14 is electrically equivalent to the bottom VSS pin in
voltage, and is connected to the EPROM GNO pin. Pin
22 is electrically equivalent to the bottom VSS pin and is
used to supply the OE signal to the EPROM.
Serial data output.
Instruction Set
I/O serial clock.
Refer to the User's Manual. The instruction set appears
also as subset A4 in the data sheet for the ",P07500 series of single-chip microcomputers.
INTO
External interrupt input.
Vss
Ground.
3-231
m
~
fttfEC
J.tPD7527A/28A
Block Diagram, ",PD7527/28
POo/INTO
H(4)
Program Memory
2048 x 8 Bits (I-'-PD7527/)
4096 x 8 Bits (I-'-PD7528/)
CL
Instruction
Decoder
,I>
Data Memory
128 x 4 Bits (I-'-PD7527)
160 x 4 Bits (I-'-PD7528)
P100-P103
CL1
CL2
I i i
Voo
Vss
P110-P113
RESET
49-0010678
3-232
NEe
J-LPD7527A/28A
Block Diagram, f.tPD75CG28
POO/INTO
P21-P23
PTOUT/ P21
~DP7C
I
L.-_ _ _ _ _....
Instruction
Buffer
Instruction
Decoder
CL
Data Memory
160x4 Bits
CL1
CL2
hh
t
voo Vee vss vss RESET
49-0010688
Absolute Maximum Ratings
TA=25°C
Power supply voltage, Voo
-0.3to +7V
Output current high, ports 3, 4, 8, 9 total, IOH
-55mA
Power supply voltage, VLOAO (flPD7527 / 28)
VOO-40VtoVoO +0.3V
Output current high, ports 2, 5, 10, 11 total, IOH
-55mA
Power supply voltage, VPRE
VOO-12 V to Voo +0.3 V
Output current low, per pin, IOL
15mA
Output current low, all ports total, IOL
15mA
Input voltage, except ports 4,5, 10, 11, VIN
Input voltage, ports 4, 5, 10, 11, VIN
Output voltage, except ports 2-5,8-11, Vo
Output voltage, ports 2-5,8-11, Vo
-0.3VtoVoO +0.3V
VOO-40 V to Voo +0.3 V
-0.3VtoVoo +0.3V
Voo-40 V to Voo +0.3 V
Output current high, per pin: POj, P02; IOH
-15 mA
Output current high, per pin: ports 2-5,8-11; IOH
-30 mA
Operating temperature, TOPT
Storage temperature, TSTG
Comment: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits described in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
3-233
t\'EC
JAPD7527AI28A
DC Characteristics
",PD7527/28
TA = -10°C to +70 oC, Voo = +2.7VtoS.OV
Limits
Parameter
Input voltage,
low
Input voltage,
high
Symbol
Min
Typ
Mal(
Test
Conditions
Unit
VIL1
0
0. 3V oo
V
Port 0, RESET
VIL2
0
0.5
V
CL1
VIL3
Voo-35
0.3 Voo
V
Ports 4, 5, 10, 11
VIH1
0. 7Voo
Voo
V
Port 0, RESET
VIH2
Voo-0.5
Voo
V
CL1
VIH3
0. 7V oo
Voo
V
Ports 4, 5, 10, 11;
4.5V~Voo~
6.0V
Voo-0.5
Voo
V
Ports 4, 5, 10, 11;
Limits
Parameter
Output leakage
current, low
Output leakage
current, high
Typ
Unit
ILOL1
-3
~
Vo=OV; P01, P02
ILOL2
-10
~
Vo=Voo-35V;
ports 2-5, 8-11
ILOH1
3
~
Vo=Voo; except
ports 4, 5, 10, 11
ILOH2
80
~
Vo=Voo; ports 4,
5,10,11
1.0
3.0
mA
Voo=5V±10%,
R=39kQ
0.4
1.0
mA
Voo=3V,
R=82kQ
200
600
JAA
Voo=5V±10%,
R=39kQ (Note 4)
60
200
~
Voo=3V,
R=82kQ (Note 4)
Min
Supply current, 1001
normal operation
2.7V~Voo~
4.5V
Output voltage,
low
0.4
VOL
V
P01, P02;
4.5V~
Voo~6.0V;
IOL=1.6mA
0.5
Output voltage,
high
VOH
Voo-2.0
VOO-0.5
3-234
210
640
~
Ports 2-:5,
10H= -4mA
(Note 1)
Voo=5V±10%,
R=39kQ (Note 5)
67
230
~
Voo=3V,
R=82kQ (Note 5)
0.1
10
~
Voo=3 V (Note 4)
10
40
~
Voo=5V±10%
(Note 5)
7
30
140
220
~
kQ
V
VOO-1.0
Input leakage
current, high
IOL=400~
V
V
VOO-2.0
Input leakage
current, low
P01, P02;
V
Voo-2.0
Supply current, 1002
HALT mode
(Note 6)
V
V
Voo-2.0
Test
Conditions
Mal(
Symbol
Ports 8-11,
10H= -10mA
(Note 1)
Ports 2-5,
10H= -2mA
(Note 2)
Ports 8-11,
IOH=-5mA
(Note 2)
P01, P02;
IOH=-1mA
(Note 3)
V
P01, P02;
10H= -100~
IUL1
-3
~
VIN=OV; POa-P03
IUL2
-40
~
VIN=OV; POa
(Note 5)
IUL3
-10
~
VIN=OV; CL1
IUL4
-10
~
VIN=Voo-35V;
ports 4, 5, 10, 11
IUH1
3
~
VIN=VOO;
POa-P03 (Note 4)
IUH2
40
~
VIN = Voo; POa
(Note 5)
IUH3
10
~
VIN = Voo; CL1
IUH4
80
~
VIN=VOO; ports 4,
5,10,11
Supply current, 1003
STOP mode
(Note 6)
On-chip pullRL
down resistance
80
Voo=3V (Note 5)
Voo- VLOAO = 35 V
Note:
(1) VPRE = Voo-9V +1V. The circuit in figure 5 is recommended.
(2) VPRE=OV. Vo o =4.5Vto6.0V.
(3) Voo = 4.5 V to 6.0 V.
(4) Without zero-cross detector.
(5) With zero-cross detector.
(6) Ports 4, 5, 10, 11 are low level output or low level input.
t-IEC
""PD7527A/28A
DC Characteristics (cont)
I-lPD75CG28
TA= -10°C to +70°C, Voo= +5V±10%
Limits
Parameter
Limits
Parameter
Input voltage,
high
Output voltage,
low
Test
Conditions
Input leakage
current, low
IUL1
-3
~
VIN=OV; POO-P03
VIN=OV; POo
Typ
Unit
0.3 Voo
V
Port 0, RESET
IUL2
-40
~
0.5
V
CL1
IUL3
-10
~
VIN=OV; CL1
VIL3
Voo-35
0. 3V oo
V
Ports 4, 5, 10, 11
IUL4
-10
~
VIH1
0. 7V oo
Voo
V
Port 0, RESET
VIN=Voo-35V;
ports 4, 5, 10, 11
VIH2
Voo-0.5
Voo
V
CL1
IUH1
3
~
VIN=VOO;
POO-P03
VIH3
O.7Voo
Voo
V
Ports 4, 5, 10, 11
IUH2
40
V
~
VIN=VOO; POo
0.4
P01, P02;
IOL=1.6mA
IUH3
10
/AA
VIN = Voo; CL1
IUH4
80
/AA
VIN=VOO; ports 4,
5,10,11
Min
0
VIL1
VIL2
VOL
0.5
Output voltage,
high
Test
Conditions
Unit
Min
Max
Symbol
Input voltage,
low
Typ
Max
Symbol
VOH
Voo-2.0
Input leakage
current, high
V
P01, P02;
10L =400~
V
Ports 2-5,
10H= -4mA (1)
Voo-2.0
V
Ports 8-11,
10H = -10 mA(1)
Voo-2.0
V
Ports 2-5,
10H = - 2 mA(2)
Voo-2.0
V
Ports 8-11,
10H = - 5 mA(2)
Voo-1.0
V
P01, P02;
10H= -1mA
Input current,
low (10-17)
IlL
-200
~
VIN=OV
Input current,
high (MSEL)
IIH
300
~
VIN=VOO
Output leakage
current, low
Output leakage
current, high
ILOL1
-3
~
Vo=OV; P01, P02
ILOL2
-10
~
Vo=Voo-35V;
ports 2-5,8-11
ILOH1
3
~
Vo=Voo; except
ports 4, 5, 10, 11
ILOH2
80
~
Vo=Voo; ports 4,
5,10,11
Supply current, 1001
normal operation
1.0
3.0
mA
R=39kQ
Supply current, 1002
HALT mode(3)
210
630
/AA
R=39kQ
Supply current, 1003
STOP mode(3)
10
50
~
Note:
(1) VpRE = VDD- 9V +1\1. The circuit in figure 6 is recommended.
(2) VpRE=OV
(3) Ports 4, 5, 10, 11 are output off or low input.
Figure 1.
Recommended Circuit, I-lPD752717528
Recommended Circuit, J.lPD75CG28
+5V
Voo
Voo
):~.3 ~F ~ ~RD9.1EL
~PD7527
Figure 2.
+5V
~L7
~PD75CG28
VPRE
VPRE
17528
:.68 kl!
68kl!
30V
VLOAO
Vss
~~ RD9.1EL
3.3~F
_-30V
Vss
1
49·001052A
1
49·001054A
3-235
E
NEe
I-lPD7527A/28A
Zero-Cross Detection Characteristics
AC Characteristics
liPD7527/28:TA= -10OCto +70°C, Voo=4.5Vto6.0V
liPD75CG28:TA= -10°Cto +70°C,Voo= +5V±10%
",PD7527/28
Limits
Parameter
Symbol
Min
Zero-cross
detection input
voltage
Vzx{P-P) 1
Zero-cross
accuracy
VAZX
Zero-cross
detection input
frequency
fzx
Typ
Max
3
Unit
Vp_p AC coupled,
C=0.1!-1F
±100
1000
45
Test
Conditions
mV
50 Hz to 60 Hz sine
wave
Hz
Zero-Cross Detection Waveform
TA= -100Cto +70 oC,Voo= +2.7V to 6.0V
Limits
Parameter
Cycle time
(Note 1)
Symbol
tCY
POo event input fpo
frequency
Min
Typ
Max
Unit
3.3
200
lis
6.9
200
!-Is
0
610
kHz
0
290
kHz
POo input rise
time
tpOR
0.1
lis
POo input fall
time
tpOF
0.1
!-Is
Test
Conditions
Voo=4.5Vto
6.0V
Voo=4.5Vto
6.0V
POo input pulse tpOL
width, low
1.63
!-Is
POo input pulse tpOH
width, high
0.72
lis
Voo=4.5Vto
6.0V
SCK cycle time
3.0
!-Is
Input: Voo=4.5 V
to 6.0V
3.3
lis
Output:
Voo=4.5Vto
6.0V
Signal
8.0
lis
Input
Note: In the above waveforms, both o-t0-1 and 1-to-O transitions of the zero-cross
detection signal delay from the low-to-high and hlgh-to-Iow transitions of the AC
Input signal, respectively. However, it Is possible that the zero-cross detection
leads low-to-high and/or hlgh-to-Iow transltlon(s) of the AC input signal.
6.9
liS
Output
AClnput
II
II
I,
II
tKCY
I
'I
I
I
zerocros~
Detection
SCK pulse
width, low
tKL
SCK pulse
width, high
tKH
49'OO1055A
Capacitance
TA = 25°C, Voo=ov, f=1.0MHz, Unmeasured pins returned to GND
Limits
Parameter
Symbol
Input
capacitance
CI
Output
capacitance
Co
I/O
capacitance
CIO
3-236
Min
Typ
Test
Conditions
3.9
!-IS
Input
3.35
liS
Output
1.4
!-Is
Input: Voo=4.5V
t06.0V
1.55
!-Is
Output:
Voo=4.5Vto
6.0V
Max
Unit
300
ns
pF
POo, P03
SI set-up time
(to riSing-edge
ofSCK)
tSIK
15
SI hold time
tKSI
450
ns
15
pF
Port 2
35
pF
Ports 3,8,9
15
pF
P01, P02
35
pF
Ports 4,5, 10, 11
(afterri~
edge of SCK)
SO output delay tKSO
time (after
falling-edge of
SCK)
850
ns
1200
ns
INTO pulse
tIOH,
width, high, low tlOL
10
liS
RESET pulse
tRSH,
width, high, low tRSL
10
liS
Voo=4.5Vto
6.0V
NEe
jiPD7527A/28A
AC Characteristics (cont)
Oscillation Characteristics
J.lPD75CG28
J.lPD7527/28
TA = -10°Clo +70 0 C, Voo= +5V±10%
TA= -10°C 10 + 70°C, Voo=2.7Vl06.0V
Limits
Parameter
Symbol
Min
Typ
Max
Unit
tCY
4.0
200
J.ls
POQ event input fpo
frequency
0
500
kHz
Cycle time
(Note 1)
Test
Conditions
LlmHs
Parameter
Symbol
System clock
oscillation
frequency
(Note 1)
fcc
fc
Typ
Max
Unit
300
400
500
kHz
R=39kQ±2%;
Voo=4.5Vto
6.0V
110
150
190
kHz
R=110kQ±2%
10
500
kHz
Voo=4.5Vto
6.0V
10
210
kHz
POQ input rise
time
tpOR
0.2
J.ls
POQ input fall
time
tpDF
0.2
J.ls
System clock
CL1 input
frequency
(Note 2)
CL1input rise
time (Note 2)
tCR
0.2
J.ls
CL1input fall
time (Note 2)
tCF
0.2
J.ls
POQ input pulse tpOH,
width, high, low tpOl
0.8
J.ls
SCK cycle time
tKCY
3.0
J.ls
Input
4.0
J.ls
Output
SCK pulse
width, low
tKl
1.8
J.ls
Output
SCK pulse
width, high
tKH
1.3
J.ls
Input
SI set-up time
(to rising-edge
of SCK)
tSIK
300
ns
SI hold time
(after risingedge of SCK)
tKSI
450
ns
CL1input pulse tCl
width, low
(Note 2)
2.0
50
J.ls
CL1 input pulse tCH
width, high
(Note 2)
0.8
50
J.ls
Voo=4.5Vto
6.0V
J.lPD75CG28
TA= -10°C 10 +70 oC,Voo=5V±10%
LlmHs
SO output delay tKSD
time (after
falling-edge of
SCK)
850
Parameter
ns
INTO pulse
tlOH,
width, high, low llOL
10
J.ls
RESET pulse
tRSH,
width, high, low tRSl
10
J.ls
Symbol
UnH
300
400
500
kHz
R=39kQ±2%
110
150
190
kHz
R=110kQ±2%
500
kHz
fc
CL1input rise
time (Note 2)
tCR
0.2
"'S
tCF
0.2
"'S
50
/As
Data input delay tCE
time from CE
700
ns
CL1 input fall
time (Note 2)
ns
CL1input pulse tCH,
width, high, low tCl
a
Max
System clock
CL1 input
frequency
(Note 2)
ns
tlH
Typ
fcc
700
Test
CondHlons
Min
System clock
oscillation
frequency
(Note 1)
Data input delay tACC
time from
address
Input hold time
after address
Test
Conditions
Min
10
0.8
Note:
(1) R, C (see figure 3)
Note:
(1) tCY = 2/fcc or 2/fc
(2) External clock (see figure 4)
AC Waveform Measurement Points (Except CL 1)
~0.7VOO>
_ 0.3 VOO
Test
Points
<: 0.7VOoX=
0.3 VOO ~
49·001056A
3-237
NEe
",PD7527A128A
Figure 3.
Recommended RC Oscillator Circuit
Figure 4.
Recommended External Clock Circuit
~
e~
e
= 33pF ±S%
49-001060A
l.lel '" 60 ppm/'e
49-001059A
Data Retention Mode Timing
Stop Mode Low Voltage Data Retention
Characteristics
IlPD7527/28
TA
VOO-+-----\
= -1o oe to + 70 e
0
Limits
Symbol
Min
Data retention
supply voltage
VOOOR
2.0
Data retention
supply current
IOOOR
Paramet.r
Typ
T.st
Conditions
Max
Unit
6.0
V
0.3
10
~
VOOOR=2V
(Note 1)
7
30
~
VOOOR=2V
(Note 2)
VOOOR
+0.2
V
Data retention
RESET input
voltage high
VIHOR 0. 9V OOOR
RESET set-up
time
tSRS
0
/As
RESET hold time tHRS
0
/As
RESET
TA= -10 0 eto +70 oe
Limits
Typ
Symbol
Min
Data retention
supply voltage
VOOOR
2.0
Data retention
supply current
IOOOR
Data retention
RESET input
voltage high
VIHOR 0.9 VOOOR
RESET set-up
time
tSRS
0
/As
RESET hold time tHRS
0
/As
7
Note:
(1) Without zero-cross detector
(2) With zero-cross detector
3-238
® VIH1
® VIHOR
0
VIL1
49-001077A
J.lPD75CG28 EPROM Interface
IlPD75CG28
Paramet.r
CD VOOOR
Note: In data retention mode, all inputs should be made lower level than VOOOR.
Max
Unit
5.5
V
30
/AA
VOOOR
+0.2
V
T.st
Conditions
VOOOR=2V
A 4-Kbyte EPROM (2732) plugs into socket pins on top of
the IlPD75CG28. A high input to MSEL selects IlPD7527
mode and fixes the A11 output high level in order to access the upper 2-Kbytes of the 4-Kbyte EPROM. When
MSEL is open, IlPD7528 mode is selected. All EPROM
addresses can be accessed because A11 functions as
the MSB of the address. Figure 5 shows the address
control unit. Figures 6 and 7 show the IlPD75CG28 connected with the 2732.
Figure 8 shows the EPROM read timing. Data is read
into the instruction buffer at the end of the T4 state. The
chip enable (CE) signal is made active during 2 states
(T3, T4) in order to decrease the power consumption of
the EPROM.
NEe
Figure 5.
J-tPD7527A/28A
Address Control Unit
VOO(28)
MSEL
to Address Decoder
of Data Memory
SW
On-chip
pull-down
resistor
Vss
SWan : ~PD7527 Mode
SW off : ~P07528 Mode
49-0010B9A
Figure 6.
Connection with the 2732 (JAPD7527 Mode)
Figure 7.
~PD75CG28
2732
~PD75CG28
VOO(26)
Connection with the 2732 (JAPD7528 Mode)
2732
Vee
VOO(26)
Voo(28)
MSEL
0
Vee
Voo(28) -(open)
All (high)
All
MSEL -(open)
"'\
/
"
"-
Ao-A1O
)
Ao- A l0
AO-All
v
Ao-All
CE
CE
CE
CE
VSS(22)
OE
VSS(22)
OE
A
10-17
Oo-Or
GND
VSS(14)
GND
VSS(14)
K..
10-17
°o-Or
49·001070A
Figure 8.
49-001071A
EPROM Read Timing
1 Machine Cycle
T4
T1
\
CLl \ \.. _ _ _ _-..1/
(External)
AO-A"
CE
____________
J)(~
- - - -/
I
T2
I
T3
I
T4
/
\
/
_______________________Ad_d_~_SS
'I
______________________
\
_J)(~______
\~-----_/
.J}-- - - - - - - - - - - -<~__________
___J>- - - - -
10- 17 _______________
Re_a_d_Da_ta________
49·001072A
3-239
ttiEC
J.lPD7527A/28A
Timing Waveforms
EPROM (jAPD75CG28 only)
Serial Interface
SCK
tlH
10 -17
SI
-----------<1
49-001075A
so
Clock
Output Data
>C
49-001074A
Interrupt Input
CL11nput
tCF
RESET
49-001169A
Reset Input
PDQ Input
49-001073A
INTO
49-00116SA
3-240
NEe
J.lPD7527A/28A
Operating Characteristics
fpovs VOO
100 vs Voo (Typical)
1000
10,000
500
e
./
E
./
Guaranteed Area
~
c
§
u
:::J
Co
c
»
50
100
50
Q.
g-
8
III
0..
~~
~
Cll
10 E::::::::
~
r--
o
o
2.7 3
.-l-':_ ~
R=39kQ
R=110kQ
R -39kQ
R=110kQ
H~Mode I
CL2
R
E
10
--
500
Q
E
--
100
\~
TA 125 oC
1000
~
..::l.
./
1:.'
~
Operating Mode
./
N
:I:
33PF
I
j"
~
o
Supply Voltage, (V)
Supply Voltage, Voo(V)
fCC vs VOO (lYpical)
fC vs VOO
1000
1000
N
N
:I:
~
500
~
.><
g
(3
E
~
Guaranteed Area
c
.
0
100
~
50
g
2.7 3
500
I'....
"" r-.
I!!
u..
(3
E
!
o
I33PF
f
I
VOH vs IOH (Ports 2-5) (l'ypical)
25°C
....
~
g
r---
-~r-------r-------,-------,-------,-------,
TA
N
~
R
Supply Voltage, Voo (V)
fCC vs R (lYpical)
[
i
_
10
o
~~
-
!
1000
u
50
E
Supply Voltage, Voo (V)
~
100
(3
10
R=39kQ
R 110kQ
u..
!
:I:
I----
g:
./
c:r
:::J
2SoC
g
./
f
500 t - - - TA
~
,/
~
J:
0
./
~
100
~-
~~=
~
50 I - - f-.f - . - f-f - . - f--
I - - - I-
I--- f--
CL1
I:::
-20r------r------~------i_-----_+---~
Voo=SV
~ ~.
I--
Voo-3V
CL2
.....
-10f----------f--------~f---~~-~-----_+------__4
R
I33PF
-=
10
10
50
100
Resistance, R (kQ)
500
1000
VOO-VOH(V)
3-241
NEe
~PD7527A/28A
Operating Characteristics (cont)
Difference. Among the tJPD75271281CG28
jlPD7527
jlPD7528
Program memory 4 Kbyte EPROM
(2732)
connectable
on top
On-chip 2 Kbyte
ROM
On-chip 4 Kbyte
ROM
Data memory
(RAM)
160x4
128x4
160x4
High-voltage
output lines
All open-drain
outputs
On-chip load capacitor or open drain
output (bit by bit, mask optional)
f.lPD75C028
VOH vs IOH (Ports 8-11) (TypIcal)
0
TA=2S C
-10~----~----~~----~------~----~
~
~
VLOAD pin
No
Zero-cross
detection
Yes
Package
42-pin ceramic
piggyback DIP
bottom pin
compatible with
",PD7527 128
Power supply
5V
VDD-VOH(V)
3-242
Mask optional
42-pin plastic DIP
42-pin plastic
shrink DIP
2.7Vto6.0V
NEe
NEe Electronics Inc.
pPD7533
4-BIT, SINGLE-CHIP
CMOS MICROCOMPUTER
WITH A/D CONVERTER
PRELIMINARY INFORMATION
Description
The pPD7533 is a 4-bit, single-chip CMOS microcomputer with a 4-channel, 8-bit A/D converter, 8-bit
timer/event counter, and an 8-bit serial interface. The
pPD7533 has 30 I/O lines, 8 of which can be used to
directly drive LEDs. The pPD7533 executes 67 instructions of the pPD7500 series "A" instruction set.
The A/D converter has various temperature monitoring
applications that can be used with household electrical
appliances, such as air conditioners and electric
ovens. Other applications include health monitoring
equipment and cameras.
The pPD75CG33 consists of a 28-pin socket "piggybacked" on the lower 42-pin ceramic DIP. This socket
is configured to hold either a 2732A or 2764 EPROM.
For engineering purposes, programs can be tried and
debugged before ROM code submission.
Features
o 4-bit single chip microcomputer
o 67 instructions (subset of pPD7500 series set A)
o Instruction cycle
o
o
o
o
o
o
o
o
o
o
o
- 5 ps at 5 V, 400-kHz clock at ceramic oscillation,
DIVSEL = high
- 10 ps at 5 V, 400-kHz clock at ceramic
oscillation, DIVSEL = low
Program memory (ROM): 4096 words x 8 bits
- External in the pPD75CG33
Data memory (RAM): 160 words x 4 bits
8 high current output lines for LED direct drive
Input/output ports
- Two 4-bit input ports
- One 2-bit output port
- One 4-bit output port
- Three 4-bit input/output ports (two of which can
function in 8-bit units)
- One 4-bit input/output port usable at bit level
Interrupts: two internal and one external
8-bit serial interface
Standby operation
-STOP mode
- HALT mode
On-chip system clock oscillator
- Ceramic resonator
- Full or 1/2 oscillation frequency
CMOS technology
Low power consumption
Single power supply
Ordering Information
Maximum
Frequency
of Operation
Package
Type
Part
Number
pPD7533C
42-pin plastic DIP
pPD7533CU
42-pin plastic shrink DIP
500 kHz
500 kHz
pPD7533G-22
44-pin plastic minifiat
500 kHz
pPD75CG33E
42-pin ceramic piggyback DIP
500 kHz
Pin Configurations
42-Pin Plastic DIP or Plastic Shrink DIP
Vss
P50
P22
P21/PTOUT
P73
P72
83-002631 A
3-243
NEe
pPD7533
Pin Configurations (cont)
Pin Identification
42-P/n Ceramic Piggyback DIP
42-Pln DIP, Shrink DIP, and PIggyback DIP
P43
Vss
P42
P50
IlP075CG33
P41
P51
P40
P52
P22
P21/PTOUT
5
6
Voo
Vss
P53
2
Cl2
P73
Cl1
P72
No.
Symbol
1-4
P43-P40
I/O port 4
5,6
P22, P21/PTOUT
Port 2 output
7-10
P73-P70
I/O port 7
11-14
P33-P30
Port 3 output
16-19
Avss
AN3-ANO
AID converter ground
20
VAREF
AID reference voltage input
21
15
OIVSEl
P7 1
P70
10
P3a
11
A4
P32
12
P3l
13
Al
A9
RESET
A1l
POo/INTO/EVENT
Vss
P01/SCi<
P02/S0
P03/SI
P30
14
Ao
17
P10
AVss
15
10
Is
P11
AN3
16
11
15
P12
AN2
17
12
14
P13
AN1
18 Vss
13
P60
ANO
19
P61
VAREF
20
P62
Voo
21
P63
Voo
Positive power supply
P63-P60
I/O port 6
26-29
P13-P10
Port 1 input
P03/S1
Port 0 input/Serial input
31
P~/SO
Port 0 input/Serial output
32
P01/SCK
Port 0 input/(I/O) Serial clock
33
POo/INTO/EVENT
Port 0 input/Interrupt O/Event
input
34
RESET
RESET input
35
DIVSEL
System clock selection input
36,37
CL1, CL2
External clock input/System
clock terminal
38-41
P53-PSo
I/O port 5
42
Vss
Ground
83-002633A
P21/PTOUT
NC
P73
Cl1
P72
OIVSEl
P71
P 33
RESET
POo/INTO/
EVENT
P01/SCK
P32
P02/S0
P31
P03/SI
P30
P10
P 70
AVss
P11
AN3
P12
83-002632A
3-244
Analog input
22-25
30
44-Pin Plastic Minlflat
Function
NEe
pPD7533
Pin Functions
Pin Identification (cont)
POO-P03 [Port 0]
44-Pin Miniflat
No.
Symbol
Function
1,44
P21/PTOUT, P22
2-5
P73-P70
lID port 7
6-9
P33-P30
Port 3 output
Port 2 output
10
AVSS
AID converter ground
11-14
AN3-ANO
Analog input
15
VAREF
AID reference voltage input
17
Voo
Positive power supply
18-21
P63-P60
1/0 port 6
21-25
P13-P10
Port 1 input
26
P03/S1
Port 0 input/Serial input
POO-P03 function as port O. POo also functions as a
count pulse input pin for the timer/event counter
(EVENT) or as interrupt 0 (INTO). P0 1 also functions as
a serial clock input/output pin (SCK) for the serial
interface. P02 functions as a serial data output pin (SO)
and pins P03 as a serial data input pin (SI). The P0 1/SCK
and P0 2/SO pins are three-state input/output.
The shift mode register (SM o-SM3) determines the
operation mode of the port 0 input/output pins; how-:ever, the data on POO-P03 can be loaded into the
accumulator at any time by executing a port input
instruction (IP/IPL). This is possible even when POr
P03 are functioning as the serial interface.
After a RESET, POO-P03 become input ports (high
impedance).
27
P02/S0
Port 0 input/Serial output
28
P0 1/SCK
Port 0 input/(l/O) Serial clock
29
POol INTO/ EVENT
Port 0 input/Interrupt O/Event
input
P10-P13 [Port 1]
30
RESET
RESET input
31
DIVSEL
System clock selection input
32,34
CL1, CL2
External clock inputlSystem
clock
P1o-P13 function as port 1. Execution of an IP or IPL
instruction reads data present on P1o-P13 into the
accumulator. Tie any unused lines of P1o-P13 to VDD or
Vss·
35-38
P53-P50
lID port 5
P21-P22 [Port 2]
39
VSS
Ground
40-43
P43-P40
lID port 4
P2rP22 function as port 2 with an output latch. When
an output instruction (OP/OPL) to port 2 is executed,
the middle 2 bits (A1 and A2) of the accumulator are
latched by the output latch and, at the same time,
output to P2rP22.
28-Pin EPROM Socket on 42-pin Piggyback DIP
No.
1,26-28
Symbol
Function
Voo
Positive power supply
2,14,22
VSS
Ground
20
CE
Chip enable output
3-10,21,
23-25
Ao-A11
Address bus
11-13,
15-19
10-17
Data bus
After being written once, the output latch contents
remain until they are rewritten by an output instruction
or a reset. The status of the corresponding output
signal also remains. After a reset, the output latch
contents become undefined, all output signals are
disabled, and the output drivers are turned off.
P21 is also used as an output pin (PTOUT) for the
timer-out F/F signal (PTOUT). Bit 3 (eM3) of the clock
mode register controls the PTOUT output. When eM3
is 1, TOUT is ORed with the P21 output latch contents
and sent to the output driver. Therefore, to output the
P21 output latch contents, reset eM3 to 0 to inhibit the
TOUT signal.
Note that soon after the RESET signal is asserted, CM3
is reset and TOUT is inhibited. However, since the
output latch contents are undefined after a reset, to
output the TOUT signal, first write 0 in the P21 output
latch and then set CM3 to 1 to output TOUT.
III
t\'EC
pPD7533
P30·P33 [Port 3]
P60·P63 [Port 6]
P30-P33 function as port 3 with an output latch. When
an output instruction to port 3 is executed, the accumulator contents are latched and output.
P6o-P63 function as the 4-bit input latched, three-state
output port. The individual lines can be programmed
as either inputs or outputs.
Once data is written in the output latch, the data is held
until the next outputinstruction to port 3 is executed or
RESET is asserted. After a reset, the output latch
contents become undefined and the output driver is
turned off.
In input mode, data present at this portis read into the
accumulator by the execution of an IP or IPL instruction. Accumulator data written to this port by the
execution of an OP, OPL, ANP, or ORP instruction is
statically latched, and remains unchanged until rewritten. This data, however, is not output since the
output buffer is disabled and placed in the high
impedance state.
P40·P43 [Port 4]
P50·P53 [Port 5]
P4o-P43 function as port 4 and P50-P53 function as port
5. When an input instruction is executed, the data on
these pins is read into the accumulator. When an
output instruction is executed, the accumulator
contents are latched and output. After the data is
written into the latch, it is held until the next output
instruction to ports 4 or 5 is executed, or RESET is
asserted.
Ports 4 and 5 can work as a pair enabling data (input
with the IP54 instruction and output with the OP54
instruction) in a-bit units. The high four bits of data are
from the accumulator and the low four bits are from
memory (addressed by HL).
Ports 4 and 5 automatically set in the input mode (high
impedance output) after a reset or when· the input
instructions to these ports are executed. After a reset,
the output latch contents become undefined. Both
ports 4 and 5 can drive LEOs directly.
In output mode, accumulator data written to the
specified port line by the execution of the OP, OPL,
ANP, or ORP instruction is statically latched and
output to the P6 n pin. Data present at P6 n is read into
the accumulator by the execution of the IP or IPL
instruction, making it possible to read the contents of
the P6 n output latch.
All lines of port 6 are initialized to the high impedance
state at Reset. Leave any unused lines open (if outputs)
or tied to VDD or Vss (if inputs).
The port 6 mode select register (MSR) controls the
function of the individual port 6 lines. The execution of
the OP or OPL instruction loads the port 6 MSR with
the accumulator contents. The 4-bit immediate data
operand or the contents·of the L register must be set to
OEH. Figure 1 shows the format of the port 6 MSR.
Figure 1.
Port 6 MSR Format
Note that after the port changes from output mode to
input mode, the data on the line is unstable when the
input instruction that changes the mode is first executed. It is strongly recommended that you re-execute
the input instruction considering the input/output
mode switching time. This will insure reading stable
data.
The bit manipulation instruction affects the specified
bit only. So when the output latch contents are undefined, (immediately after a reset), initialize the output
latch contents with an output instruction before the bit
manipulation instruction is executed.
3-246
P60
L------P61
' - - - - - - - - - - P62
L--_ _ _ _ _ _ _ _ _ P63
PM n
Port 6 Selection
0
P6 n input [output buffer high-impedance]
1
P6n output [output buller on]
83-002634A
t-iEC
pPD7533
P70-P73 [Port 7]
Pin Functions, pPD75CG33 EPROM
Port 7 is a 4-bit input or latched three-state output port.
The execution of an IP or IPL instruction execution
reads data present at this port into the accumulator.
Accumulator data written to this port by the execution
of an OP, OPL, ANP, or ORP instruction is statically
latched and remains unchanged until rewritten.
Ao-A11 [EPROM Address]
Upon reset, all lines are initialized to the highimpedance state. Leave any unused lines open (if
outputs) or tied to Voo or Vss (if inputs).
ANO-AN3 [AID Input Terminal]
ANO-AN3 are the 4-channel AID converter input terminals. The AID converter uses a successive approximation method.
VAREF [AID Converter Positive Reference]
The voltage on VAREF determines the full scale analog
voltage.
Ao-A11 output the contents of the EPROM program
address counter. A reset leaves Ao-A11 undefined.
10-17 [Data Bus]
10-17 input the contents of the EPROM data bus.
CE [Chip Enable]
CE outputs the EPROM chip enable signal. (Active
low.)
Voo [Power Supply], VSS [Ground]
Voo is the positive power supply pin with the same
voltage as the lower portion pin 21. Vss is the ground
pin with the same voltage as the lower portion pin 42.
The following voltages are supplied to the 2764 or
2732A pins from Voo or Vss.
AVSS [AID Converter Ground]
Avss is the ground for the AID circuit.
CL 1, CL2 [Clock]
CL 1 and CL2 connect external oscillator elements to
the system clock. Connect a ceramic resonator to
these pins. If an exte'rnal clock is used, place a buffer
between the clock source and the CL 1 and CL2 pins.
Pin Number
2764
2732A
Symbol
Voltage
20
Vpp
VDD pin 21 = +5 V
28
24
Vee
VDD pin 21 = +5 V
22
20
DE
VSS pin 42 = 0 V
2
14
12
A12
VDD pin 21 = +5 V
Vss
Vss pin 42 = 0 V
When connecting the oscillation parts to the CL 1 and
CL2 pins, use the shortest wiring possible. Ground the
capacitor as close to the Vss pin as possible.
DIVSEL [System Clock Divider Selection Input]
DIVSEL selects whether the system clock runs at
ceramic oscillation frequency, or at one-half the ceramic
oscillation frequency. If a logic 0 (Vss) is connected to
DIVSEL, the system clock is one-fourth the ceramic
oscillation. If DIVSEL is high, then the system clock will
be one-half of the ceramic oscillation.
RESET [Reset]
A high on RESET activates this input.
Voo [Power Supply]
Voo is the positive power supply pin.
Vss [Ground]
Vss is the ground pin.
3-247
NEe
pPD7533
Block Diagram
INTO/EVENT/POo
EVENT
Clock
Conlrol
CL
P10-P103
P21/PTOUT,
P22
P30-P33
P40-P43
Program Memory
4096 x 8 Bits
Instruction
Decorder
P50-P53
CL
I/J
P60-P63
Cll CL2
111
Voo
Vss
RESET
P70-P73
AN o-AN3
VAREF
Avss
83-00263~
Absolute Maximum Ratings
Capacitance
TA
TA
=25°C
Power supply voltage, Voo
== 25°C, Voo == 0 v
Limits
-0.3 to +7.0 V
Input voltage, VI
-0.3 V to Voo + 0.3 V
Parameter
Output voltage, Vo
-0.3 V to Voo + 0.3 V
Input
capacitance
-20 rnA (all output ports)
10 rnA (1 pin)
High level output current, IOH
Low level output current, IOL
-10 rnA (1 pin)
45 rnA ports 2,3,4,7 (total pins)
45 rnA ports 0,5,6
Operating temperature, TOPT
-10 to +70 o G
Storage temperature, TSTG
-65 to +150°C
AID Vss, Avss
-0.3 to +0.3 V
AID reference, VAREF
-0.3 V to Voo
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
3-248
Symbol
Min
Max
Unit
GIN
15
pF
Output
capacitance
GOUT
15
pF
110
capacitance
GIO
15
pF
Test
Conditions
f =1 MHz
Unmeasured
pins are 0 V
NEe
pPD7533
DC Characteristics
A C Characteristics
TA = -10 to +70°C. Voo = 3.0 to 6.0 V. DlVSEL
Limits
Parameter
High level
input voltage
(other than
CL1. CL2)
Symbol
VIH1
High level
input voltage
(CL 1. CL2)
VIH2
Low level
input voltage
(other than
CL1. CL2)
VIL1
Low level
input voltage
(CL1. CL2)
VIL2
High level
output voltage
VOH
Min
Max
Unit
0.7 Voo
Voo
V
Voo - 0.5
0
0
Voo
0.3 Voo
0.5
0.5 (typ)
Test
Conditions
Conditions
specified by
oscillation
characteristics
V
Limits
Parameter
Symbol
Min
Max
Cycle time
tCY
4.0
200
ps
9.5
200
ps
0
500
kHz
0
210
kHz
Voo = 4.5-6.0 V
IOH=-1mA
fE
EVENT input
high duration
tEH
0.8
ps
EVENT input
low duration
tEL
2.3
ps
SCK cycle
time
tKCY
3.0
fJS
V
IOH = -100pA
V
Voo = 4.5-6.0 V
IOL = 10 mA
0.4
V
IOL = 1.6 mA
IOL = 400pA
0.5
V
High level
IUH1
input leakage
current (other
than CL 1. CL2)
3
pA
High level
input leakage
current (CL 1.
CL2)
IUH2
20
Low level
input leakage
current (other
than CL 1. CL2)
IUL1
-3
pA
Low level
input leakage
current (CL1.
CL2)
IUL2
-20
pA
High level
'LDH
output leakage
current
3
pA
VOUT = Voo
Low level
'LDL
output leakage
current
-3
pA
VOUT = 0 V
pA
VIN = Voo
VIN = Voo
VIN = 0 V
Supply current 10D1
1.0 (typ)
3.0
rnA
Operating
mode: Voo =
4.5-6.0 V;
fcc = 400 Hz
1002
450 (typ)
1200
pA
HALT mode:
Voo = 4.5-6.0 V;
fcc = 400 HZ
1003
0.1 (typ)
10
pA
STOP mode
SCK high.
low level
duration
tKH.
tKL
Test
Conditions
Unit
EVENT input
frequency
V
2.0
Voo - 0.5
Low level
VOL
output voltage
TA = -10 to +70°C. Voo = 3.0 to 6.0 V
V
V
Voo -1.0
=1
. Voo = 4.5-6.0 V
Voo = 4.5-6.0 V
Voo = 4.5-6.0V
Input
Voo = 4.5-6.0 V
4.0
ps
Output
8.0
pS
Input
9.5
pS
Output
1.3
pS
Input
Voo = 4.5-6.0 V
1.8
pS
Output
4.0
pS
Input
Output
4.7
pS
SI setillL
time (SCK high)
tSIK
300
ns
SI hold
time (SCK high)
tKSI
450
ns
SCK low
to SO
output delay
time
tKSO
INTO high.
low level
duration
tIOH.
tlOL
10
ps
RESET high.
low level
duration
tRSH.
tRSL
10
ps
850
ns
Voo = 4.5-6.0 V
1200
3-249
11
NEe
pPD7533
Data Memory, STOP Mode Data Retention
Characteristics
TA = -10 to +70 G
O
limits
Typ
Parameter
Symbol
Min
Max
Unit
Data
retention
supply voltage
VDDDR
2.0
6.0
V
Data retention
supply current
IDDDR
RESET setup
time
tSRS
0
ps
Oscillation
stabilizing
time
tos
20
ms
0.1
10
Symbol
Min
Resolution
I
STOP Mode
J
~
I
---t--I)\
flA
VDDDR
ms
Data Retention Timing
RESET
limits
Parameter
Typ
·'1
Data
tCONV
Sampling
time
tSAMP
Ceramic
resonator:
when VDD
greater than
4.5 V
Analog input
voltage
VIAM
Analog input
impedance
RAN
Crystal:
when VDD
greater than
45V
VAREF current
IAREF
* tCYC
Unit
Test
Conditions
Bits
0.6
±1/2 LSB
Conversion
time
·19
HALT
= 2.0 V
Max
8
Absolute
accuracy
25
VOO
Test
Conditions
AID Converter Characteristics
TA = -10 to +70 0 G, Voo = +5.0 V ±5%,
Vss = Avss = 0 V, VAREF = Voo - 0.5 V to Voo
9
tCyc*
tCYC*
0
VAREF
Mn
1000
0.4
V
2
rnA
2
= fcc (DIVSEL = 1)
roperating
Mode
Mode
l1r--:-----
Rete::o: :ode_
o
STOP
Instruction
Execution
tSRS
=-.j
83-002636A
Osci Ilator Characteristics
TA = -10 to HOOG, Voo = 3.0 to 6.0 V, DIVSEL =
1
limits
Test
Conditions
Oscillation
Configuration
Parameter
Min
Typ
Max
Unit
Ceramic
See figure 3
Oscillation frequency (fcc)
390
400
410
kHz
VDD == 4.5 to 6.0 V
Stabilization time
20
ms
VDD greater than 4.5 V
CL 1 input frequency
10
410
kHz
VDD =- 4.5 to 6.0 V
10
210
kHz
1.0
50
ps
50
pS
External clock
See figure 3
CL 1 input high, low level duration (tcH,tcLl
2.0
3-250
VDD = 4.5 to 6.0 V
NEe
pPD7533
Timing Waveforms
AC Timing Measuring POints (Except CL 1)
0.7 Voo _ _ Measuring Points
0.3 VOO - - - -
<:
Serial Transfer Timing
0.7 VOO
0.3 VOO
Clock Timing
SI
----1----<1
t------l/fC-----..!
so
Output Data
\/
~--"-
83-002640A
Cll
Interrupt Input Timing
EVENT Timing
INTO
EVENT
RESET Input Timing
83-002639A
RESET
3-251
NEe
pPD7533
Functional Description
Standby Control
System Clock Generator
The HALT F/F and the STOP F/F comprise the control
circuitry for standby mode (figure 2). The STOP F/F is
set by the STOP instruction. When the STOP F/F is set,
the ceramic oscillator stops. The rising edge of the
RESET input resets the STOP F/F.
The ceramic oscillator circuit generates the system
clock for the pPD7533. Fig u re 2 shows that the osci Ilator
circuit for the pPD7533 includes a ceramic oscillator,
two divide-by-two circuits, the DIVSEL input, and
control circuitry for the standby modes, HALT and
STOP.
Figure 3 shows that the ceramic oscillator requires that
a ceramic resonator be connected to the CL 1 and CL2
pins. An external clock can also be inputat CL 1. In this
case, the oscillator operates as an inverted buffer.
Figure 2 shows that the output .frequency from the
ceramic oscillator connects either directly to the clock
selector or via a divide-by-two circuit. The selector is
controlled by the DIVSEL line. If DIVSEL is low the
divide-by-two frequency is selected. This opti~n is
used during a low power operating mode. If DIVSEL is
high, then the direct frequency is chosen. The output
of the selector is used as system clock (CL), and is also
divided by two to supply the CPU cloc,k (¢).
Table 1 shows how DIVSEL selects the system and
CPU clocks, and machine cycle timing.
The HALT instruction sets the HALT F/F and inhibits
the input of the half-frequency divider which generates
the CPU clock. As a result, only the CPU clock is
stopped in HALT mode. The RELEASE signal resets
~he HALT F/F. RELEASE becomes active when any
mterrupt request flag is set, or at the falling edge of the
RESET input.
While RESET is active, the HALT F/F is set, and the
chip goes into the HALT mode. At a power-on Reset,
the ceramic oscillation is driven when the RESET input
signal becomes high.
Figure 3.
Clock Driver Configuration
30 pF
.-----i i l - - _ -... CL 1
External
Clock --I
>0---...-.... CL1
Ceramic c:::J
CMOS
Inverter
Resonator
30 pF
Table 1.
DlVSEl
Clock Selection
System Clock
(ClI
CL2
CPU Clock
(4)1
Machine Cycle
low
200 kHz
100 kHz
10 tiS
High
400 kHz
200 kHz
5 tiS
Figure 2.
83-002644A
System Clock Generator
STOPF/F
. - - _ - - STOP Instruction
r------,--~Q
HALTF/F
l - - - - I - - - HALT Instruction
L-...j--RESET
- , . . . . - _ - - Standby Release
,,--~---RESET " '--t-----------RESET
J
CL1
Ceramic
Oscillator
CL2
r---+CPU
' - - - - - - - - - - - _ C L To Timer/Event Counter
DIVSEL o-----------~
83-002643B
3-252
t\'EC
pPD7533
It takes a short period of time for the oscillator output to
become stable. To prevent errors due to an unstable
clock, the HALT F/F is set to inhibit the CPU clock
while the RESET input is high. Therefore, the highlevel pulse width for the RESET input should be wide
enough to cover the required time for the ceramic
resonator oscillation to stabilize.
Format of Clock Mode Register
Figure 5.
I
CM3
I
C M2
I
CM1
I
-
The OP 12 or OPL (L = 12) instruction sets codes in the
clock mode register. CM3 designates the output of the
timer-out signals. If CM3 = 1, the output of the timerout F/F (TOUT) is available at the PTOUT (P21) pin.
CMo
I
Clock Control
Figure 4 shows that the clock controller contains a
4-bit clock mode register (CMO-CM3), prescalers 1-3,
and multiplexers. The clock controller selects the
clock sources and prescalers, and supplies the count
pulses (CP) to the timer/event counter. The clock
sources are the system clock generator output (CL) or
the EVENT pulse.
I
CM2
C M1
CMo
0
0
0
CL x
0
0
1
EVENT x
2~6
~
0
1
0
EVENT
0
1
1
EVENT
1
0
0
CLX~
1
0
1
EVENTxt
1
1
0
CLX~
1
1
1
EVENT
CM3
Figure 5 shows the format of the clock mode register.
CP Count Pulse
Timer-out F/F
0
PTOUT inhibited
1
PTOUT output enabled
83-002646A
Figure 4.
Clock Controller Block Diagram
Internal Bus
- O P , OPL Instruclion Execulion
Timer/Event Counter - - - - '
Mux
CL
EVENT [POo/INTO]
O------jj..;..r::r:--4-tj::t::t=~C)
~~~g=>-
I
____
Timer/Event Counter
CP
83-0026458
3-253
t-IEC
pPD7533
Timer/Event Counter
Event Counter Operation
Figure 6 shows the timer/event counter has an 8-bit
count register, 8-bit modulo register, an 8-bit comparator, and a timer-out flip fiop.
To use the timer/event counter as an event counter,
input the external event pulse into the POo pin, and
select POo' as the count pulse (CP) for the clock
controller. The count register counts the external event
pulses input at the POo pin, either as they are, or
frequency divided.
Timer Operation
Afterthe TAMMOD instruction sets a count value in the
modulo register and the TIMER instruction clears the
contents of the count reg ister, the timer starts counti ng
count pulses (CP). If an external clock is used, the
count pulses are synchronized with the rising edge of
CL 1 or the POo input.
When the value of the modulo register equals the value
of the count register, the comparator generates a
coincidence signal (INTT) to set an interrupt request
flag. Then it clears the count register to repeat the
counting. In this manner, the timer functions as an
interval timer whose interval is set by the modulo
register.
As a result, the timer/event counter operates as an
event counter that generates interrupts after observing
the number of counts (events) specified by the modulo
register. The TCNTAM instruction can read the current
count at any time.
Set the modulo register with the number of count
pulses minus one. If set to 0, no counting will occur
because the counter register is held at 0 (both the
detection of coincidence and zero-clearing are simultaneously made).
Regardless of any instructions, the count pulses are
always input into the count register, updating the
count value. If the contents of the count register are
equal tothose of the modulo register, the INTT request
flag is then set. For this reason, inhibit INTT interrupts
when not using the timer.
Figure 6.
Block Diagram of Timer/Event Counter
1 - - - - - - - ;r:s~:~~n Execution
TCNTAM
Instruction
Execution
-----.----+1
. - - - -....... INTT
CP -
Count Hold
Circuit for
TCNTAM Execution
TOUT
Serial Interface
and Port 2
Timer Reset
Instruction Execution
83-002647B
3-254
NEe
pPD7533
Serial Interface
As figure 7 shows, the serial interface includes an 8-bit
shift register, a 4-bit shift mode register, and a 3-bit
counter.
The serial clock controls serial data I/O. At the falling
edge of the serial clock (SCK), the SO line outputs the
most significant bit (7) of the shift register. The
contents of the shift register are shifted by one bit at the
rising edge of the next serial clock (n -0 n+1). At the
same time, the data on the SI line is loaded into the
least significant bit (0) of the shift register.
The 3-bit counter (octal counter) counts up the serial
clocks and generates an internal interrupt signallNTS
at every count of 8 clocks (at the end of a 1-byte serial
data transfer). It then sets the interrupt request flag
(INTO/S RQF). The TAMSIO instruction sets data in
the shift register during the transmission of serial data,
then starts transmission. At the end of the transmission
of each byte (8 bits) an internal interrupt (INTS) is
generated.
The SIO instruction also starts the reception of serial
data. The received data is taken from the shift register
by executing the TSIOAM instruction after an interrupt
(INTS) is generated by the reception of one byte of
data.
Figure 7.
The end of a 1-byte transfer can be confi rmed by
testing the INTS RQF with the SKI instruction instead
of interrupt processing.
The following three types of serial clock sources are
available: system clock ¢, external clock (SCK input),
and timer-out F/F output signal (TOUT). Bits SM2-SMO
of the shift mode register select the clock source.
If the system clock ¢ is chosen, execute the SIO
instruction to supply the clock to the serial interface,
controlling the input/output of serial data while ¢ is
output from the SCK pin.
After eight ¢ pulses, the clock is automatically discontinued by holding the SCK output at a high level.
Therefore, the input/output of serial data automatically
stops after each byte has been transferred. Consequently, the software does not need to control the
serial clock and the transfer rate is determined by the
system clock frequency.
In this mode, after six machine cycles from the execution of the SIO, the TSIOAM instruction can read out
the received data from the shift register or can write in
the next transmit data.
Figure 8 shows the shift mode register format.
Serial Interface Block Diagram
-OP,OPL·
P02/SI
SM3
0---+------+--+--< 1--_ _ _ _ _-+_ _ _ _ _ _ _-1
~~~----~-----~------TOUT
~------+------+------¢
POO/INTO/EVENT
1--+------
INTS
RS F/F
'-.lr---~ Q
S 1 - - - - - - - SIO·
"Instruction Execution
83-267488
3-255
NEe
pPD7533
Figure 8.
Format of'Shlft Mode Register
SM 2
SM I
SMo
P03/81
P02/80
0
0
0
Port input
Port input
0
1
1
0
0
Outputs TOUT continuously
SI input
SO output
0
Bit SM3 selects the interrupt source in the following
manner:
SM3
Interrupt Source
o
INTS
INTO
1
If the external clock (SCK input) is selected, the serial
clocks are input from SCK. When the eighth external
serial clock is input, an internal interrupt (INTS) is
generated, signalling the end of a 1-byte data transfer.
Since the serial clocks are not internally inhibited, the
external clock must hold the signal high after eight
clocks. The external serial clock determines the transfer
rate. The serial interface can be operated from DC to
the maximum rate in the electrical specifications.
If TOUT is selected, the half-frequency divided coincidence signal of the timer/event counter is the serial
clock. This serial clock controls the input/output of the
serial data and is output from the SCK pin.
3-256
Serial Operation
Stops
Outputs t/J continuously
0
0
POI /8CK
Port input
SCK input
Operates with external clock
SCK output (----......:....----- :~~~=::
"Instruction Execution
83-002653B
Standby Function
The jJPD7533 has two types of standby modes (STOP
and HALT) to minimize power consumption during a
program standby state_ STOP mode is set by the STOP
instruction and HALT mode by the HALT instruction_
When standby mode is set, program execution is
stopped, and the contents of all internal registers and
data memory are held_ However, it is possible to
operate the shift register and the timer/event counterAn interrupt or reset releases standby mode_ Since an
interrupt releases standby mode, neither STOP nor
HALT modes can be set if an interrupt request flag is
set Therefore, when setting standby mode when there
is a possibility of a request flag being set, first reset the
interrupt request flag by processing the interrupt in
advance or by executing the SKI instruction.
The major difference in the two modes is that crystal
oscillation (CL) stops in STOP mode but does not stop
in HALT mode.
In STOP mode, it is possible to go into data retention
mode by lowering the power supply voltage_ During
data retention mode, all operation stops and only the
data RAM stays intact
Table 2 shows the differences between STOP and
HALT modes_
Table 2.
Differences Between STOP and HAL T Modes
Mode
Operation
Ceramic Oscillation
STOP Mode
HALT Mode
X(1)
0(2)
112 Ceramic Oscillation
X
X
CPU
X
X
Serial 1/0
(3)
Timer IEvent Counter
X
AID Converter
X
0
RESET
INTOIS ROF
NTT ROF
RESET Input
Release of Standby
Mode
0
Note:
(1) Not possible
(2) Possible
(3) Possible depending on clock source selected
3-259
NEe
pPD7533
STOP Mode
In STOP mode, ceramic oscillation and the halffrequency divider stop. The CPU stops and the operations requiring the system clock (CL, 0) stop.
Release from STOP mode is with the RESET input
only. All other functions cease to operate.
In order to minimize power consumption, the current
flowing through the resistor ladder of the A/D converter
must be minimized. To minimize power consumption,
turn off the power to the VAREF pin.
Note that ceramic oscillation stops and disables the
system clock during STOP mode by bringing CL2 to
ground. Therefore, if the external clock is connected to
CL 1 and a STOP instruction is executed, the CPU will
enter HALT mode instead.
HALT Mode
In HALT mode, only the half-frequency divider circuit
stops in the clock generator circuit (CL operates, ¢
stops). Therefore, the CPU and the operation of the
serial interface (when using ¢ as a serial clock) stop.
However, since the clock control circuit is still in
operation, it can select the CL signal from the clock
generator or the EVENT input and supply the count
pulse (CP) to the timer/event counter.
Conseq uently, the ti mer/event cou nter can be operated
in HALT mode. The serial interface operates if a serial
clock other than ¢ (such as the external clock, TOUT
signal) is selected. The HALT mode is released by the
RESET input or an interrupt, even if the interrupt is
disabled.
If the interrupt master enable F/F is disabled, the
instruction following the STOP/HALT instruction is
executed regardless of the state of the interrupt enable
register (interrupt routine is not initiated). In this case,
the interrupt request flag is left set. If necessary, it can
be reset by the SKI instruction.
After any release, operation resumes with the same
register contents as before standby mode.
Release From Standby Mode with RESET
Both STOP and HALT modes are released unconditionally by the RESET input. Figure 14 shows the
release timing.
If the device is reset during STOP mode, the low to high
transition of the RESET pin will take the processor
from STOP mode to HALT mode. When RESET goes
high to low, the HALT mode is abandoned, and after a
normal reset operation, the PC is initialized to O. Only
the data memory will stay intact during the HALT
mode, but all registers become undefined.
If the device is reset during HALT mode, the high to low
transition of RESET will release the device from standby
mode. After a normal reset operation, the PC is
initialized to o. Only the data memory will stay intact
during the STOP mode, but all registers become
undefined.
Figure 15 shows the release from HALT mode by
RESET.
Figure 14.
Release from STOP mode by RESET
~
~-I-_----.J
Release from Standby Mode by Interrupt
RESET _ _
The standby mode is released when the interrupt
request flag is set by an interrupt source, whether
interrupts are disabled or enabled. However, the operations after release differ in each case.
~
Input
_ . HALT Mode
STOP
Mode
.1
•
Reset Operation
PC=O
Clock Oscillation
Begins
83-002654A
If the interrupt master enable F/F is enabled, and if the
interrupt is enabled, the corresponding interrupt routine
is initiated after execution of one instruction after the
STOP/HALT instruction. Then, the result flag is reset.
If the corresponding bit of the interrupt enable register
has been reset, execution of instructions starts after
the STOP/HALT instruction, and the interrupt routine
is not initiated. In this case, the request flag for release
remains set. If necessary, reset the request flag with the
SKI instruction.
3-260
Figure 15.
Release from HAL T Mode by RESET
RESET~
- - - HALT Mode
.1
•
Reset Operation
PC=O
83-002655A
t\'EC
pPD7533
Reset Function
Power-on Reset Circuit
The J.lPD7533 is reset and initialized by the input of the
RESET signal (active high).
Figure 16 shows an example of the simplest power-on
reset circuit using a resistor and a capacitor.
A RESET causes the CPU to initialize in the following
manner:
Figure 16.
• Program counter (PC) is cleared to 0
• Skip flags (SK1, SKO) and program status word
(PSW) are reset to 0
• Timer/event counter:
- Count register = OOH
- Modulo register = FFH
- Timer-out F/F = 0
• Clock control circuitry:
- Clock mode register (CM3-CMO) = 0
CL
- CP = 256
•
•
•
•
•
Power-on Reset Circuit
+5V
pPD7533
~
..---tRESET
r.7
83-002656A
- Timer-out FF signal not output to PTOUT
- Prescalers 1-3 = 0
Shift Mode Register (SM3-SMa) is cleared to O.
- Shift operation stops
- Port 0 is in input mode (high impedance)
- INTS is selected interrupt source of INTO/S
AID converter circuit:
- ADM register is set to 0
- ANO is selected
- SA register is set to 7FH
- EOC flag is set to logic 1
Interrupt control circuit:
- Interrupt request flags = 0
- Interrupt master enable F/F = 0
- Interrupt enable register = 0
- All pending interrupts are cancelled
- All interrupts are disabled
All Port 2-7 output buffers are turned off
Contents of data memory and the following registers
are undefined:
- Stack pointer (SP)
- Accumulator (A)
- Carry flag (C)
- General purpose registers (H,L)
- All port output latches
- Shift register
3-261
pPD7533
3-262
NEe
NEe
NEe Electronics Inc.
Description
The /JPD7537 A, /JPD7538A, and /JPD75CG38 are 4-bit,
single-chip CMOS microcomputers with the /JPD7500
architecture and FIP direct-drive capability.
Note: This data sheet pertains to ",PD7537A, ",PD7538A,
and ",PD75CG38. For simplification, the revision
letter (A) usually is omitted from the part numbers
within the data sheet.
The /JPD7537 contains a 2048 x 8-bit ROM and a
128 x 4-bit RAM. The /JPD7538 contains a 4096 x 8-bit
ROM and a 160 x 4-bit RAM.
The /JPD7537/38 contains two 4-bit general purpose registers located outside RAM. The subroutine stack is implemented in RAM for greater depth and flexibility. The
/JPD7537/38 typically executes 67 instructions with a
5/Js instruction cycle time.
The /JPD7537/38 has one external and two internal
edge-triggered hardware-vectored interrupts. An 8-bit
timer/event counter and an 8-bit serial interface help to
reduce software requirements.
Thirty-one high-voltage lines are organized into the 3-bit
output port 2, the 4-bit output ports 3, 8, and 9, and the 4bit I/O ports 4, 5, 10, and 11.
The low power consumption CMOS process allows the
use of a power supply between 2.7 V and 6.0 V. Current
consumption is less than 3.0 mA maximum, and can be
further reduced in the halt and stop power-down modes.
The /JPD75CG38 is a piggyback EPROM version of the
/JPD7537/38. Pin-compatible and function-compatible
with the final, masked versions of the /JPD7537/38, the
/JPD75CG38 is used for prototyping and for aiding in program development.
pPD7537A/38A
4-BIT, SINGLE-CHIP
CMOS MICROCOMPUTERS
WITH Flp® DRIVER
D Can select either a pull-down resistor or open-drain
output per 31 high-voltage outputs (mask optional)
D Vectored interrupts: one external, two internal
D 8-bit timer/event counter
o 8-bit serial interface
o Standby function (HALT, STOP)
o Data retention mode
o Zero-cross detector on POOIINTO input (mask
optional)
o System clock (lJPD753717538/75CG38): on-chip
ceramic oscillator
o CMOS technology
o Low power consumption
o Single power supply
- /JPD7537/7538: 2.7 V to 6.0 V
-/JPD75CG38: 5.0V ±10%
Ordering Information
Max Frequency
Part
Package Type
Number
of Operation
",PD7537 AC / 38AC
42-pin plastic DIP
610 kHz
/APD7537ACU /38ACU
42-pin plastic shrink DIP
610 kHz
/APD75CG38E
42-pin ceramic piggyback DIP
500 kHz
Pin Configurations
/JPD7537/3842·Pin Plastic DIP or Shrink DIP
RESET
Cll
Cl2
VpRE
41
POo"NTO
PO,/SCK
P02/S0
VlOAD
P53
P52
P5,
P50
Features
D 67 instructions
D Instruction cycle:
- I nternal clock: 5 /Js /400 kHz, 5 V
- External clock: 4/Js/500 kHz, 5 V
D Upwardly compatible with the /JPD7500 series
product family
D 4,096 x 8-bit ROM (lJPD7538/75CG38)
2,048 x 8-bit ROM (lJPD7537)
D 160 x 4-bit RAM (lJPD7538/75CG38)
128 x 4-bit RAM (lJPD7537)
D 351/0 lines
D 31 high-voltage output lines that can directly drive a
vacuum fluorescent diplay (FIP)
49-001170A
FIP is the registered trademark for. NEC's fluorescent indicator panel (vacuum
fluorescent display).
3-263
NEe
IAPD7537A/38A
!-,PD75CG38 EPROM
Pin Configurations (cont)
No.
Symbol
!-,PD75G38 42·Pin Ceramic Piggyback DIP
RESET
CL1
Vss
POo/INTO
CL2
P01/SCK
VpRE
Voo 0 1 280 Voo
VLOAO
NC 0 2 270 MSEL
P53
A76'H6~Voo
P52
P113
Supplies EPROM OE signal
Program counter MSB output
26
Voo
Supplies Vee to the EPROM
1-
P42
27
MSEL
Mode select input
1
P43
28
Voo
Supplies high-level signal to MSEL
1
(~)12
I
17 ~)ls
1
12013 16014
Vss<2,1415913
7-
P111
P110
Chip enable output
P41
1
10011 18016
17
CE
A11
1
Pl12
20
23
AoOl0 19017
P100
Connection to EPROM GND pin
P30
P33
1
1
11
Vss
Vss
1
P1CJ,
14
P02/S0
22
Al0 9200CE
P102
Data read input from the EPROM
P03/S1
P32
1
P103
10-17
P31
A30 7220Vss
1
1
A20 8 210 Al0
P21/PTOUT
EPROM: 2732
P40
P80
P81
Note:
(1) Output drivers on ports 2-5 and 8-'11 are m~sk-optional. Accordingly,
either an open-drain output or a pull-down resistor can be selected.
VLOAD is suitable for an output driver with a pull-down resistor.
P82
P83
P90
P91
(2) Ports 2-5 are suitable as FIP segment signal outputs, and ports 8-11
P92
are suitable for FIP digit signal outputs.
P93
Voo
49-001171A
Pin Identification
Symbol
Function
RESET
Reset input
2,3
CL1, CL2
Clock pins
4
VPRE
High-voltage output predriver supply
5
VLOAD
High-voltage output option resistor
supply
6-9
P50-P53
High-voltage I/O port 5
10,12
P23, P22
P21/PTOUT
High-voltage output port 2, and output
port from timer / event counter (PTOUT)
13-16
P100-P103
High-current, high-voltage I/O port 10
17-20
P110-P113
High-voltage, high-current I/O port 11
21
Voo
Positive power supply
22-25
P90-P93
High-voltage, high-current output port 9
26-29
P80-P83
High-voltage, high-current output port 8
High-voltage I/O port 4
30-33
P40-P43
34-37
P30-P33
High-voltage output port 3
38
39
40
41
P03/S1
P01/SCK
POo/INTO
4-bit input of port 0; or serial data input
(SI), serial data output (SO), serial clock
I/O (SCK), and external interrupt input
(INTO) or zero-cross detect input (POO).
42
VSS
Ground
3-264
P02/~
(3) Ports 8-11 have high-current drive capability and can drive an LED
directly.
Pin Functions, ",PD7S37' 38 and
",PD7SCG38
!-,PD7537138 and !-,PD75CG38
No.
EPROM address output
11-13,15-19
1
1
P23
No connection
1
A40 6 230All
P22
NC
3-10, 21, 24, 25 Ao-A10
1
As 05 240Ag
P50
Connection to pin 21 of flPD75CG38
1
A60 4250 Aa
P51
Function
Voo
RESET
System reset (input).
CL1, CL2
Connection to the ceramic oscillator. CL1 is the external
clock input.
VPRE
Negative power supply for high-voltage output pre·
drivers (for ports 2-5, 8-11).
VLOAD
Negative power supply for optional load resistors (pulldown resistors) of high-voltage output drivers (for ports
2-5, 8-11). This pin is only on the !-,PD7537 138.
P53-P50
4-bit, high-voltage I/O port 5.
P21-P23
3-bit, high-voltage output port 2.
NEe
/JPD7537A/38A
PTOUT
Pin Functions, J-lPD75CG38 EPROM
Output port for the timer/event counter.
MSEL
P103-P100
4-bit, high-voltage, high-current I/O port 10. Capable of
bit set/reset by SPBLlRPBL instructions.
P113-P110
4-bit, high-voltage, high-current I/O port 11. Capable of
bit set/reset by SPBLlRPBL instructions.
Voo
Positive power supply.
P93- P90
4-bit, high-voltage, high-current output port 9. Capable
of bit set/reset by SPBLlRPBL instructions.
P83-P80
4-bit, high-voltage, high-current output port 8. Capable
of bit set/reset by SPBLlRPBL instructions.
P43-P40
4-bit, high-voltage I/O port 4.
P33-P30
4-bit, high-voltage output port 3.
POO-P03
4-bit input port O. POo is also used as the zero-cross detection input.
SI
Serial data input.
so
Changes the addressing area of the external EPROM
and the on-chip RAM (with a pull-down resistor). Connecting a jumper between socket pins 27 (MSEL) and 28
(Voo) selects /JPD7537 mode (2-Kbyte EPROM, 128 x 4bit RAM). Leaving MSEL open selects /JPD7538 mode (4Kbyte EPROM, 160 x 4-bit RAM).
AO-A10
Output the low-order 11 bits of the program counter
(PCO-PC10). Used as EPROM address signals.
A11
When MSEL is high level, A11 outputs high-level signals.
When MSEL is open, A11 outputs the MSB of the PC,
which is used as the most significant address signal of
the 4-Kbyte EPROM 2732.
10- 17
Input data read from the EPROM.
CE
Outputs the chip enable signal to the EPROM.
Voo
Pin 26 is electrically equivalent to the bottom Voo pin
and is used to supply Vee to the EPROM. Pin 28 is electrically equivalent to the bottom Voo pin and is used to
supply the high level signal to MSEL. Pin 1 connects to
pin 21 of /JPD75CG38.
Vss
Pin 14 is electrically equivalent to the bottom Vss pin in
voltage, and is connected to the EPROM GND pin. Pin
22 is electrically equivalent to the bottom Vss pin and is
used to supply the OE signal to the EPROM.
Serial data output.
Instruction Set
SCK
Refer to the User's Manual. The instruction set appears
also as subset A4 in the data sheet for the /JPD7500 series of single-chip microcomputers.
Serial I/O clock.
INTO
External interrupt input.
Vss
Ground.
3-265
NEe
",PD7537A/38A
Block Diagram, IAPD7537/38
POO"NTO
4
POO-P03
P21-P23
PTOUT/P21
P30-P33
P40-P43
H(4)
Program Memory
2048 x 8 Bits !/lPD7537)
4096 x 8 Bits !/lPD7538)
Instruction
Decoder
Cl
Data Memory
128 x 4 Bits (I-'PD7537)
160 x 4 Bits (I-'PD7538)
Cll
Cl2
I
Voo
f
Vss
I
P90-P93
Pll0-P113
RESET
49-0010678
3-266
NEe
J.(PD7537A138A
Block Diagram, J.lPD75CG38
POO/INTO
P2,-P23
PTOUT/P2,
L.-_ _ _ _
--'~DP7C
Instruction
Buffer
Cl
Instruction
Decoder
Points
Symbol
500
kHz
tCR
0.2
j.ls
tCF
0.2
j.ls
50
j.ls
49-001056A
After Voo reaches
4.5V
...
CL1input pulse tCH.
width high. low tCl
0.7V00X==
<:: 0.3
VOO
ms
Test
Conditions
0.8
Note:
(1) Ceramic resonator: CSB400P (MURATA) is recommended; C = 300 pF
(see figure 3).
(2) External clock (see figure 4).
3-271
NEe
J..lPD7537A/38A
Figure 3.
Recommended Circuit, /-LPD753717538
Data Retention Mode Timing
HAl.T Operating
Mode
Mode
r5---sTOP Mode'----.J---+I
I
_
r
Data Retention Mode
---.Jf~----\.
Voo
t
Execution of
STOP Instruction
49-Q01057A
RESET
Figure 4.
Recommended Circuit, /-LPD75CG38
49-001076A
tJPD75CG38 EPROM Interface
49-001058A
Stop Mode Low Voltage Data Retention
Characteristics
/-LPD7537/38
TA= -10°C to +70 oc, Voo=2.7Vto6.0V
Limits
Parameter
Symbol
Min
Data retention
supply voltage
VDDDR
2.0
Data retention
supply current
IDDDR
RESET set-up
time
Typ
Unit
6.0
V
0.1
10
JAA
VDDDR=2V
(Note 1)
7
30
JAA
VDDDR=2V
(Note 2)
tSRS
Oscillation stable tos
time
Test
Conditions
Max
A 4-Kbyte EPROM (2732) plugs into socket pins on top of
the /-LPD75CG38. A high input to MSEL selects the
/-LPD7537 mode and fixes the A11 output high level in order to access the upper 2-Kbytes of the 4-Kbyte EPROM.
When MSEL is open, /-LPD7538 mode is selected. All
EPROM addresses can be accessed because A11 functions as the MSB of the address. Figure 5 shows the address control unit. Figures 6 and 7 show the /-LPD75CG38
connected with the 2732.
Figure 8 shows the EPROM read timing. Data is read
into the instruction buffer at the end of the T4 state. The
chip enable (CE) signal is made active during 2 states
(T3, T4) in order to decrease the power consumption of
the EPROM.
Figure 5.
Address Control Unit
MSBOf_'--_ _~
Address Buffer
lAS
20
ms
VOO(28)
After VDD reaches
4.5V
MSEL
to Address Decoder
of Data Memory
SW
On-chip
pull-down
resistor
/-LPD75CG38
TA= -10°C to +70 oc, Voo=5V±100/0
Vss
Limits
Parameter
Symbol
Min
Data retention
supply voltage
VDDDR
2.0
Data retention
supply current
IDDDR
RESET set-up
time
tSRS
Oscillation stable tos
time
7
Max
Unit
5.5
V
30
0
20
Note:
(1) Without zero-cross detector.
(2) With zero-cross detector.
3-272
Typ
Test
Conditions
ms
After VDD reaches
4.5V
SW on : flPD7537 Mode
SW off : flPD7538 Mode
49-001174A
NEe
Figure 6.
J.tPD7537 AI38A
Connection with the 2732 (JlPD7537 Mode)
)J.PD75CG38
Figure 7.
Connection with the 2732 (JlPD7538 Mode)
2732
)J.PD75CG38
2732
Vee
VOO(26)
VOO(26)
Voo(28)
MSEL
:J
Vee
Voo(28) r--(open)
All (high)
All
MSEL r--(open)
...
...
"a-Al0
)
"a- Al0
Ao-All
)
"
CE
VSS(22)
"'-
CE
CE
CE
OE
VSS(22)
OE
Oo-Or
lo-Ior
10-17
GND
Co-Or
...
"
Vss(14)
"a-All
0'
GND
Vss(14)
49-001173A
FigureS.
49-001071A
EPROM Read Timing
1 Machine Cycle
T1
T4
T2
I
\
/
CLl \
(External;
I
/
T3
T4
I
..,XI..__________
AO-Al1 _ _ _ _ _
CE
\
/
\
-JXI.._____
A_dd_re_ss_ _ _ _ _ _ _ _ _
\~ ____--J/
- - - - "/
...J}- - - - - - - - - - - - -<'-_____
10- 17 _ _ _ _ _ _ _
Re_ad_O_at_a_ _ _ _..,}- -
-
-
-l9-0010i2A
NEe,
",PD7537A/38A
Timing Waveforms
EPROM(/iPD75CG38 only)
10- 17
Serial Interface
SI
--------"-------<1
---'--+---(1
49·001075A
so
Clock
Output Data
V--------I\..49-001074A
Interrupt Input
CL11nput
INTO
49-001168A
Reset Input
POo Input
49-001073A
RESET
49-001169A
3-274
NEe
J.lPD7537A/38A
Operating Characteristics
fCC (Ceramic Oscillation) vs. Voo
1000
I
N
J:
Oscillation
....
............. ....
()
J:!
[
I!!
u.
I:
0
~.~
TA-
Guaranteed Ar~~.~ ••••
~
100
""0
(3
~
~
~
~
I---10
o
10~+70°C
SOO
C
I
/"
~
Guaranteed
Area
11.
r
I
0 ceo
c"
/'
N
~Operation
=w.
~
0
u
fpovs. VOO
1000
L
Guaranteed Area
100
::l
Q.
I:
SO
~
C
I
T I
10
o
Supply Voltage, Voo (V)
2.7 3
Supply Voltage, (V)
I
fcvs. VOO
100 VS. Voo (Typical)
1000
~ TA-2S o C
Operating Mode
<"
..;!.
c
E
soo
E
§
u,.,
8:
~
1000
100
SO
cil
10
!I
-
~
~
I--
o
V
-
=
N
J:
500
~
J:!
.....
[
Halt Mode-
£
::l
./
""
./
Guaranteed Area
100
Q.
I:
CL1
CL21
""g
0
~!~'
(3
E
CSB400P
!
I330PF I330PF
-=-1
-=-
SO
1
10
o
o
Supply Voltage, Voo (V)
2.7 3
Supply Voltage, VOO (V)
VOH vs. IOH (Ports 2-5) (Typical)
VOH vs. IOH (Ports 8-11) (Typical)
-30
TA=2S oC
TA=2S o C
-20
<"
<"
.s
.s
.9
.9
:I:
:I:
-10
-10
§
~
VOO-VOH (V)
VOO-VOH(V)
3-275
ttiEC
IAPD7537A/38A
Differences Among the ",PD7537/38/CG38
JdlD75CQ38
,d'D7537
,d'D7538
Program memory
4 Kbyte EPROM
(2732)
connectable
on top
On-chip 2 Kbyte
ROM
On-chip 4 Kbyte
ROM
Data memory
(RAM)
160x4
128x4
160x4
High-voltage
output lines
All open-drain
outputs
On-chip load capacitor or open drain
output (bit by bit. mask optional)
VLOAD pin
No
Yes
Zero-cross
detection
Yes
Mask optional
Package
42-pin ceramic
piggyback DI P
bottom pin
compatible with
~PD7537 /38
Power supply
5V
3-276
42-pin plastic DIP
42-pin plastic
shrink DIP
2.7Vto 6.0V
NEe
NEe Electronics Inc.
pPD7554/64
4-BIT, SINGLE-CHIP
CMOS MICROCOMPUTES
WITH SERIAL I/O
PRELIMINARY INFORMATION
Description
Pin Configuration
The ",PD7554 and ",PD7564 are low-end versions of
",PD7500 series products. These microcomputers incorporate a serial interface and are useful as slave
CPUs to high-end ",PD7500 series or a-bit ",COM-87
series products.
P01/SCK
P02/S0
POalSI
P80
P8l
The ",PD7554/7564 has output ports that can directly
drive triacs and LEDs. Also, various mask-optional I/O
circuits can be configured for a wide selection of outputs allowing a reduction of external circuitry in your
design.
The ",PD7554 and ",PD7564 differ only in their clock
circuitry. The ",PD7554 uses an external resistor with
an internal capacitor for an RC oscillator clock, where
the ",PD7564 uses an external ceramic oscillator as
a clock. These microcomputers are ideally suited to
control devices such as plain paper copiers (PPCs),
printers, VCRs, and audio equipment.
Features
o
o
o
o
o
o
o
o
o
o
o
47 instructions (subset of ",PD7500 set 8)
Instruction cycle:
External clock:
2.86 ",s/700 kHz, 5 V
RC oscillator ~PD7554):
4 ",s/500 kHz, 5 V
Ceramic oscillator ~PD7564): 3 ",s/660 kHz, 5 V
Program memory (ROM) of 1024 x 8-bits
Data memory (RAM) of 64 x 4-bits
8-bit timer/event counter
8-bit serial interface
16 I/O lines
Data memory retention at low supply voltage
CMOS technology
Low power consumption
Single power supply (2.5 V to 6.0 V) ",PD7554
(2.7 V to 6.0 V) J,LPD7564
Ordering Information
Part Number
Package Type
pPD7554CS
20-pin plastic shrink DIP
pPD7564CS
20-pin plastic 3hrink DIP
pPD7554G
20-pin plastic SO
pPD7564G
20-pin plastic SO
GND
POO/INTO
P82
Cl2(P83)
Cl1
83-0026l4A
Pin Identification
No.
Symbol
Function
1-4
POo/INTO
P01/SCK
P02/S0
P03/S1
4-bit input port O/count clock input/serial
interface
5-8
P8o-P82
P83/CL2
4-bit output port 8
Connection for ceramic resonator or RC.
CL1
Connection for ceramic resonator or RC
10
11
Voo
RESET
Reset input pin
12-15
P101-P103
4-bit I/O port 10
16-19
P11o-P113
4-bit I/O port 11
20
GND
Ground
+5 V power supply
Pin Functions
POo/INTO, P01/SCK
P02/S0, POa/SI
(Port O/count clock input/serial interface)
4-bit input port O/count clock input/serial I/O interface.
This port can be configured as a 4-bit parallel input
port or as the 8-bit serial I/O interface, under control
of the serial mode select register. The serial input SI
(active high), serial output SO (active low), and the
serial clock SCK (active low-synchronizes data
transfer) comprise the 8-bit serial I/O interface. If
POo/INTO is unused, connect it to ground. If any of
P01-P03 are unused, connect them to ground or VDD.
The port is in the input state at reset.
3-277
11
NEe
pPD7554/64
P80·P82
P8s1CL2
(Port 8/clock input 2)
4-bit output port 8. This port can sink 15 mA and interface 12 V. On the ~PD7554, the port function of
P83/CL2 is specified by mask option. P83 is a normal
output port on the ~PD7564. On the ~PD7554, CL2 is
one of the pins to which a resistor for RC oscillation
is connected. On the ~PD7564, CL2 is one of the pins
to which a ceramic resonator is connected. If any of
P8o-P82 pins are unused, leave them open. The port
is in the high impedance state at reset.
CL 1 (Clock input 1)
On the ~PD7554, CL1 is one of the two pins to which
a resistor for RC oscillation is connected. On the
~PD7564, CL 1 is one of the two pins to which a
ceramic resonator is connected.
P110·P113 (Port 11)
4-bit I/O port. This port can sink 10 mA and interface
12 V. If any of these pins are unused, connect them
to ground or VDD in the input state, or leave open in
the output state. The port is in the high impedance
or high-level output state at reset.
GND (Ground)
Ground.
Pin Mask Options
Table 1 shows the mask options for all the port pins
and the RESET pin. You may select these options in
bit units.
Table 1.
Pin
Pin Mask Options
Options
1 No connection to internal resistor
2 Connected to internal pull-up resistor
3 Connected to internal pull-down resistor
Voo (Power supply)
Positive power supply.
CMOS (push-pull) output
N-channel open-drain output
RESET (Reset)
Use as P83
Use as CL2
System reset input pin (active high). This pin can be
internally connected to a pull-down resistor if
specified by mask option.
P1 Oo-P1 03 (Port 10)
4-bit 1/0 port. This port can sink 10 mA and interface
12 V. If any of these pins are unused, connect them
to ground or VDD in the input state, or leave open in
the output state. The port is in the high impedance
or high-level output state at reset.
3-278
CMOS (push-pull) output
N-channel open-drain output
P100-P103
P110-P113
Used as P83
1 N-channel open-drain input/output
2 CMOS (push-pull) input/output
3 N-channel open-drain input/output with internal
pull-up resistor.
RESET
*: !-,PD7554 only
Connected to internal pull-down resistor
Not connected to internal pull-down resistor
NEe
pPD7554/64
ILPD7554 Block Diagram
POollNTO
Program Memory
1024x8 Bits
Instruction
Decoder
CL
Q
CL 1 CL2(P831
1 r
VDD
GND
1
RESET
83-0026158
3..279
pPD7554/64
",PD7564 Block Diagram
3-280
NEe
NEe
J.LPD7554/64
Functional Description
1/0 Ports
Figure 1 shows the internal circuits at 1/0 ports PO,
P8, PIO, and P11
Figure 1.
Interface at lID Ports
Type F. Type D Output with Type B
Schmitt·Triggered input
P01/SCK
Type.A. CMOS Input Cell
(Part of Type E)
Voo
Data
Output Disable - - - - iL -_ _....
InlOut
~'"P"'
Type O.
Vss
Type B. Schmitt-Triggered Input
POO/INTO, P03/SI
Mid·Level Voltage, High·Current
P8o/P82, P83/CL2
D a l a - - -......-I
Out
Type D. Push·Pull Output (part of types E and F)
High impedance on RESET (output disabled); both
p. and N·channel transistors are turned off.
Voo
Type P.
P·ch
Data~
Mid·level Voltage Input Buffer
P100·P103, P110·P113
Output
Output
Disable
..
Data--__.-4
Vss
,..--+----0 In/Out
Type E.
Type D Output 1I"ith Type A
Input Buffer
P02/S0
Output _
Disable
........_--1
(Middle-Level Voltage.
Middle·Level Current)
Data
Output Disable
InlOut
Mlddle·Level Voltage Input Buffer
83-003557C
3-281
NEe
pPD7554/64
Program Memory
Data Memory
The ",PD7554/7564 has a mask-programmable ROM
with a capacity of 1024 words by 8 bits for program
storage. It is addressed by the program counter. The
reset start address is OOOH. Figure 2 shows the program memory map.
The data memory is static RAM with a capacity of 64
words by 4 bits. Part of this memory is used as the
stack area. The data memory is also used in8-bit data
processing when paired with the accumulator. Figure
4 shows the data memory map.
Figure 4.
General Purpose Registers
Two registers, H (2-bit) and L (4-bit) are provided as
general purpose registers. Each register can be individually manipulated. The two registers also form
pair register HL; H being the high register and L being the low one. The HL register is a data pointer to
address data memory. Figure 3 shows the configuration of the general purpose registers.
Data Memory Map
(0) OOH
64 words x 4 bits
(63) 3FH L...-_ _ _....I
83-002594A
The L register also specifies an 1/0 port or mode
register when an 1/0 instruction (IPL or OPL) is executed. It also specifies the bits of a port when the
SPBL or RPBL instruction is executed.
Figure 2.
Program Memory Map
You may use any area of the data memory as the
stack. The boundary of the stack is determined by
how the TAMSP instruction initializes the stack
pointer. Once the boundary is set, a call or return instruction automatically accesses the stack.
~O»"f~
' ' ' 3FFHU
Figure 3.
83-002592A
Configuration of General
Purpose Registers
o
1
0
3
Data memory can be addressed directly, with the immediate data from an instruction; indirectly, with the
contents of HL (including autoincrement and
autodecrement); and indirectly by the contents of the
stack pointer.
When a call instruction is executed, the contents of
the program counter and the program status word
(PSW) are stored to the stack in the sequence shown
in figure 5;
Figure 5.
Call Instruction Storage to Stack
0
"::""'1--;"1
Stack Area
3
SP·4
83-002593A
0\
0
0
\ PCg\ PCa
SP·3
psw'
SP·2
PC3'PCO
SP·1
PCr,PC4
'Bit 101 PSW
is always O.
83-002595A
3-282
NEe
When a return instruction is executed, the contents
of the program counter are automatically restored,
but the PSW is not. The contents of data memory can
be retained with a low supply voltage during STOP
mode.
Accumulator
The accumulator is a 4-bit register used in arithmetic
operations. The accumulator can process 8-bit data
with paired data addressed by HL. Figure 6 shows the
configuration of the accumulator..
Figure 6.
Configuration of the Accumulator
pPD7554/64
Program Status Word
The program status word (PSW) consists of two skip
flags (SKO and SK1), a carry flag (C), and bit 1, which
is always zero. Figure 7 shows the configuration of
the PSW.
Figure 7.
Configuration of the Program
Status Word
3
2
°
I~S_K...J1l_s_K0..J..I_o--,-_c...I1 psw
83-002597A
The contents of the PSW are stored to the stack when
a call instruction is executed, but are not restored
from the stack by the return instruction.
Arithmetic Logic Unit
The arithmetic logic unit (ALU) is a 4-bit arithmetic circuit that performs operations such as binary addition,
logical operation, increment, decrement, comparison,
and bit processing.
The skip flags retain the following skip conditions:
string effect byLAI or LHLI instruction, and skip condition satisfied by an instruction other than a stringeffect instruction. The skip flag is set or reset in accordance with the instruction executed.
The carry flag is set to 1 if an addition instruction
(ACSC) generates a carry from bit 3 of the ALU. If no
carry is generated, the flag is reset to zero. The SC
instruction sets the carry flag and the RC instruction
resets it.
When a RESET is input, the SK1 and SKO flags are
cleared to zero and the contents of the carry flag are
undefined.
E
t'tIEC
pPD7554/64
oscillator. The STOP flip-flop is reset by the standby
release signalthat becomes active when one of the
test requests flags is set or at the falling edge of the
RESET signal. When the STOPflip-flop'is reset, the
RC oscillator resumes operation and supplies the
system clock.
System Clock Generator
The system clock generator consists of a ceramic
oscillator, a 112 frequency divider, standby modes
(STOP/HAL and control circuit. Figure 8 is a circuit
diagram of the system clock generator.
n,
In the f.tPD7554, the RC oscillator operates with a
single external resistor connected across CL 1 and
CL2 (the capacitor C is incorporated). When the RC
oscillator is not used, external clock pulses can be
input via the CL 1 pin. In this case, the RC oscillator
functions as an inverting buffer. The output from the
RC oscillator serves as the system clock (CL) which
is then divided by two and used as the CPU clock (~).
The HALT & STOP instruction & RESET HIGH sets the
HALT flip-flop which disables signals from going to
the 1/2 frequency divider that generates the CPU
clock. Only the CPU clock stops in HALT mode. The
HALT flip-flop is reset by the same conditions as the
STOP flip-flop.
Figure 9 shows the system clock generator circuit for
the f.tPD7564.
The standby mode control circuit is made up of a
STOP flip-flop and a HALT flip-flop. The STOP instruction sets the STOP flip-flop and stops the system
clock supply. This flip-flop also stops the RC
Figure 8_
System Clock Generator' for JiPD7554
STOP F/F
1---------......,.- STOp·
HALT F/F
S
Q
HALT·
RESET (High)
Standby Release
CL2
RESET (-"L)
; (to CPU)
L-_ _ _ _ _ _ _ _ _ _ _ CL (System Clock)
• Execution of Instruction
83-0025986
Figure 9_
System Clock Generator for JiPD7564
STOP F/F
1---1----- STOp·
HALT F/F
Q
CL1
S
I=---+- HALT·
RESET (High)
Ceramic
Oscillator
Standby Release
CL2
\ - - - - RESET 'L.
L--1--_ _ _ _ _ _ _ _ _ RESET
~
(To CPU)
L-_ _ _ _ _ _ _ _ _ _ _ _ CL (System Clock)
·Executlon of Instruction
83-0025996
3-284
NEe
pPD7554/64
On the J.lPD7564, the ceramic oscillator operates with
a ceramic resonator connected across CL 1 and CL2.
The output from the ceramic oscillator is used as the
system clock (CL); it is divided by two to produce the
CPU clock (~).
The standby mode control circuit is made up of a
STOP flip-flop and a HALT flip-flop. The STOP instruction sets the STOP flip-flop and stops the ceramic
oscillation, thus stopping the supply for all clocks.
The STOP flip-flop is reset by the RESET signal (high
level) and restarts ceramic oscillation. The supply of
each clock resumes when RESET goes low.
The HALT instruction sets the HALT flip-fiop which
disables signals from going to the 1/2 frequency
divider that generates the CPU clock. Only the CPU
clock stops in HALT mode. The HALT flip-flop is reset
by the HALT RELEASE signal (activated by setting at
least one test request flag) or the falling edge of
RESET, resuming supply of the CPU clock.
The HALT flip-flop is also set when RESET is active
(high level). At power on reset operation, the rising
edge of RESET starts ceramic oscillation; however,
some time is required to achieve stable oscillation.
To prevent the unstable clock from operating the CPU,
the HALT flip-flop is set and the CPU clock is stopped while RESET is high. Accordingly, the high-level
width of RESET must be more than the required stable
time for the ceramic resonator.
Figure 10.
Clock Control Circuit
Clock Control Circuit
The clock control circuit consists of a 2-bit clock
mode register (bits CM1 and CM2), prescalers 1, 2, and
3, and a multiplexer. It takes the output of the system
clock generator (CL) and event pulses (POo). It also
selects the clock source and prescaler according to
the setting in the clock mode register and supplies
the timer/event counter with count pulses. Figure 10
shows the clock control circuit.
Table 2 lists the codes set in the clock mode register
by the OPL instruction to specify the count pulse
frequency.
When you set the clock mode register with the OPL
instruction, clear bit 0 of the accumulator (correspon~
ding to bit CMO Of the EVAKIT-7500 or J.lPD7500H during emulation).
Timer/Event Counter
The timer/event counter is a binary 8-bit up-counter
which is incremented each time a count pulse is input. The TIMER instruction or a RESET signal clears
it to OOH. When an overflow occurs, the counter Is
reset from FFH to OOH. Figure 11 shows the inputs
and outputs of the counter.
Table 2.
Selecting the Count Pulse Frequency
CM2
CM1
o
o
o
CLl256
o
CLl32
CLl4
Frequency Selected
POQ
Figure 11.
Timer/Event Counter
CL
CP
'Instruction Execution
CP
83-002601A
'Instruction
Execution
83-002600A
3-285
t'tfEC
pPD7554/64
Serial Interface
The serial interface consists of an 8-bit shift register,
a 3-bit shift mode register, and a 3-bit counter. This
interface inputs and outputs serial data. Figure 12is
a block diagram of the interface.
Test Control Circuit
The ~PD7564 has three test sources, as shown in table
3.
The test control circuit consists of two test request
flags (INT T RQF and INTO/S RQF) set by the three test
sources, and a test request flag control circuit that
checks the contents of each test request flag byexecuting an SKI instruction and resetting the flags.
Test sources INTO and INTS share the request flag
INTO/S RQF. Bit 3 of the shift mode register (SM3)
determines which source is selected. A zero in SM3
selects INTS and a one selects INTO.
The request flag INTT RQF is set when a timer
overflow occurs in the timer event counter. The SKI
or TIMER instruction resets it
When'SM3 is zero, request flag INTO/S RQF is set
when the INTS signal is generated, indicating the end
of an 8-bit serial data transfer. The SKI or SIO instruction resets the flag.
When SM3 is one, request flag INTO/S RQF is set at
the rising edge of the signal input to the POollNTO pin.
The SKI instruction resets the flag.
The logical sum of the outputs from the test request
flags releases standby mode (STOP* or HALT mode).
The mode is released when one or both flags are set.
Both flags and SM3 are reset when the RESET Signal
is input. After reset, source INTS is selected and
signal input to the INTO pin is inhibited as the initial
condition.
Figure 13 is a block diagram of the test control circuit
*only jJPD7554
Table 3.
JiPD7564 Test Sources
Source
Function
Location
Request Flag
INTT
Overflow in timer/event
counter
internal
INTT ROF
INTO
Test request signal from
POo pin
external
INTO/S ROF
INTS
Transfer complete signal
from serial interface
internal
INTO/S ROF
Figure 12.
Serial Interlace Block Diagram
Note:'
(1)
+Is the Internal clock signal (I.e., system clock).
(2) • Instruction execution
(3) SM3 and INTO are Input to the test control circuit.
83-oo2622B
3-286
NEe
Figure 13.
pPD7554/64
Test Control Circuit Block Diagram
Internal Bus
INTT - 1 - - - - - - - - - 1
Standby
Release
INTO ----.----...__
II
'SIO
Note:
(1) SM3 is bit 3 of the shill mode register.
(2) • Instruction execution
83·0026238
Standby Modes
Table 4.
STOP and HAL T Modes
The J.lPD7554/64 has two standby modes to reduce
power consumption while the program is in the wait
state. The STOP and HALT instructions set these
modes.
Mode
CL
+
STOP
x
x
x
When the program enters a standby mode, program
execution stops and the contents of all registers and
data memory immediately before the program entered
standby mode are retained. The timer and serial interface can operate.
The RESET signal and STANDBY Release Signal *1
releases STOP mode. HALT mode is released when
one or both of the test request flags are set, or when
the RESET signal is input. The program cannot enter
a standby mode when a test request is being set, even
if the STOP or HALT command is executed.
If there is some uncertainty as to the state of the test
request flags, execute the SKI instruction to reset
them so the program can enter standby mode.
Table 4 compares STOP and HALT modes. The main
difference is that STOP mode stops the system clock
and HALT does not. Ceramic oscillation stops during
STOP mode. The power consumed by the ceramic
oscillator is the difference between the two modes.
In STOP mode, data memory can be retained with a
lower supply voltage.
HALT
POD
CPU
Timer
Released by
x
RESET input
x
INTT RQF
INTO/S RQF
RESET input
Note:
(1) 0: operates x: stops l>: will operate depending on clock source
j.lPD7554, if external clock is used STOP instruction will not STOP
CL. In this case STOP mode acts as HALT mode.
Power-on Reset Circuit
Figure 14 shows a circuit example of the power-on
reset circuit using a resistor and a capacitor. This is
the simplest reset control circuit. Figure 21 shows the
circuit with a pull-down resistor internally connected
to RESET as a mask option.
,.,PD7554/7564 Applications
Figures 16 and 17 show examples of application circuits for the I-IPD7554/7564.
Table 5 compares the features of products in this part
of the 7500 series devices.
*1 standby release signal only for j.lPD7554
3-287
t-lEC
pPD7554/64
Figure 14.
Power·on Reset Circuit
Product Comparison
Table 5.
",P07554
Item
Voo
I'PD7564
Instruction
cyclelsystem
clock (5 V)
:!: z:~
~
RC
",P07564
",P07556
4 ",sl
500 kHz
4 ",sl
500 kHz
External 2.S6 ",sl
700 kHz
2.S6 ",sl
700 kHz
RESET
Ceramic
3 ",sl
3 ",sl
660 kHz
ri7
83-002624A
Figure 15.
Power·on Reset Circuit with Pull·down
Resistor
47
47
45
ROM
1024xS
1024xS
1024xS
1024xS
RAM
64x4
64x4
64x4
64x4
1/0 port total
16 (max)
15
20 (max) 19
Port 0
POO-P03
POO-P03
POO-P01
POO-P01
P10-P13
P01-P03
Port 1
PSO-PS2
P90-P91
P90-P91
Port 10
P100P103
P100P103
P100P103
P100P103
Port 11
P110P113
P110P113
P110P113
P110P113
Timer IEvent
counter
S-bit
S-bit
S-bit
S-bit
Serial interface
S-bit
S-bit
Process
CMOS
CMOS
CMOS
CMOS
Package
20-pin
plastic
shrink
DIP
20-pin
plastic
shrink
DIP
24-pin
plastic
shrink
DIP
24"pin
plastic
shrink
DIP
Port 9
RESET
Vss
83-002625A
Figure 16.
45
PSO-PS2
PS2/CL2
I'PD7564
:!:z:~
660 kHz
Instruction set
Port S
Voo
",P07566
PSO-PS2 PSO-PS2
PS3/CL2
4-channel 4-channel
Comparator
Tape Counter Circuit
Master
Microcomputer
y
Microcomputer
for Tape Counter
RESET
~OUT
POo/INTO
I-----ICLI
SCK
SCK
P113
Count Pulse
Up/Down Signal
I'PD7554
SO
I'PD7507H SI
I'PD7508H
1-----1 SI
r----I
SO
7·segment LEDs
83-002626B
3-288
NEe
Figure 17.
pPD7554/64
Remote·controlled Data Reception, Key Input and LED Display.
Master
Microcomputer
r
I'PD7564
0
SCK I - - SCK
SO I-- SI
(11
(1) P11l
P11 2
S
I
Driver !!,PA80C)
SI I - - SO
I'PD7508H I - - P113 (2)
I'PD7519H
etc.
I-- RESET
LEDC
~C DC ~G ~
1--1--
P'
I:'-.
f-'
;/
1--1--
I:'-.
/.~(i
P'
f-'
1--1--
~G~
I--~
P80 I----<
P8l
(3)
Remote
Controlled
Signal
AmPlifier
I'PC1473
r
P82
P83
POo
P100
P10l
(4)
P102
P103
Note:
(1) CMOS output
(2) Chip select or transfer request
(3) Open·drain output
(4) Input with internal pull·up resistor
Key Input (4 x 4)
83-0026278
Absolute Maximum Ratings
TA
= 25°C
Operating temperature, TOPT
Storage temperature, TSTG
-0.3 V to +7.0 V
Power supply voltage, VDD
Input Voltage VI
Output Voltage Va
Except Port 10 & 11
-0.3 V to VDD + 0.3 V
-------------------------------Port 10 & 11
-'(___
1)____
-_0._3_tO---.::VD=D_+__
0_.3_V
(2)
-0.3 to + 13 V
Except Port 8, 10 & 11
-0.3 to VDD + 0.3 V
Ports 8, 10, 11
(___1)'---___
- _0._3_to_V...:;Dc.::..D_+__
O._3_V
(2)
Output current high, one port IOH
all output ports, total IOH
-5 mA
-15 mA
5 mA
Ports 9, 10, 11
15 mA
Ports 8,
Power dissipation, PD
Capacitance
=
=
=
Symbol
Min
TA
25°C, VDD
GND
0 V; f
Unmeasured pins returned to GND
- 0.3 to +13 V
Output current low
POi, P02
All ports, total
Comment: Stresses above those listed in "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.
(1) CMOS I/O or N-channel open drain + internal pull up resistor
(2) N-channel open drain I/O
30 mA
100 mA
480 mW (TA = 70°C)
= 1 MHz,
limits
Parameter
Typ
Max
Unit
Test
Conditions
Input capacitance
C,
15
pF
POo. P03
Output capacitance
Co
35
pF
Port 8
1/0 capacitance
1/0 capacitance
Cia
Cia
35
15
pF
pF
Ports 10, 11.
POi, P02
NEe
pPD7554/64
DC Characteristics
=
",PD7554 only: TA
-10°C to +700 C, Voo = 2.5 V to 3.3 V, GND = 0 V
",PD7554/64: TA = -10°C to +70°C, VOO= 2.7 V to 6.0 V, GND = 0 V
(Voo
= 2.5-3.3) 7554 only
(Voo
= 2.7 to 6.0 V) 7554/64
Limits
Limits
Symbol
Min
Input high voltage except CL1
VIH1
Input high voltage CL1 (2)
VIH2
Input high voltage ports 10, 11
VIH3
0.8 Voo
Parameter
Max
Min
0.8 Voo
Voo
Voo-0.3
Voo
12 (1)
~p
Unit
0.7 Voo
Voo
V
Voo-0.5
Voo
12 (1)
V
Data retention mode
Includes CLI for 7564
0.7 Voo
V
VIHOR
0.9 VOOOR
VOOOR
+0.2
0.9 VOOOR
VOOOR
+0.2
V
Input low voltage except CL1
VIl1
0
0.2 VOO
0
0.3 VOO
V
Input low voltage CL1 (2)
VIl2
0
0.3
0
0.5
V
Input leakage current
except CL1
IU1
IU1
-3
3
-3
3
/AA
Input leakage current CL1 (2)
IU2
-10
10
-10
Input leakage current
ports 10, 11
IU3
Output voltage high P01, P02,
ports 8-11
VOH
Output voltage high P01, P02,
ports 8-11
VOH
Output voltage high P01, P02,
ports 8-11
VOH
Output voltage low P01, P02,
ports 10, 11
VOL
Output voltage low P01, P02
VOL
Output voltage low P01, P02
Output voltage low
ports 10, 11
Output voltage low
ports 10, 11
Input high voltage RESET
Test
Conditions
Max
~p
oV ~
VI ~ VOO
Includes CLI for 7564
10
/AA
oV ~
10 (1)
IJA
VI
V
IOH
Voo-2.0
V
VOO = 4.5 V to
6.0 V, IOH = 1 rnA
VOo-1.0
V
VOO
IOH
V
IOl
0.4
V
VOL
0.5
V
VOO = 4.5 V to
6.0 V, IOl = 1.6 rnA
IOl = 400/AA
VOL
0.4
V
VOO = 4.5 V to
6.0 V, IOl = 1.6 rnA
VOL
2.0
V
VOO = 4.5 V to
6.0 V, IOl = 10 rnA
Output voltage low
ports 10, 11
VOL
0.5
V
VOO = 2.7 V,
IOl = 400 IJA
Output voltage low port 8
VOL
V
IOl
Output voltage low
port 8
VOL
2.0
V
VOO = 4.5 V to
6.0 V, 10l = 15 rnA
Output voltage low
port 8
VOL
0.5
V
VOO = 2.7 V
IOl = 600 IJA
3
IJA
IJA
Output leakage current
IL01
Output leakage current
ports 8-11
IlO2
Supply voltage,
data retention mode
VOOOR
10 (1)
VOo-1.0
0.5
0.5
-3
3
-3
10 (1)
10 (1)
=
-80 ",A
= 2.7 V
= -100 ",A
= 350 IJA
= 500 IJA
oV ~
VO ~ VOO
Vo = 12 V
V
2.0
2.0
VI ~ VOO
= 12 V
Supply current,
normal operation
1001
55
180
IJA
VOO = 3 V ± 0.3 V
R = 150 kO ± 2%
R oscillation
1001
40
150
IJA
VOO = 2.5 V
R = 150 kO ± 2%
Supply current, normal
operation, ceramic oscillation
1001
650
2200
/AA
VOO = 5 V + 0.5 V
fcc = 700 kHz
Supply current, normal
operation, ceramic oscillation
1001
120
360
IJA
VOO = 3 V ± 10%
fcc = 300 kHz
~
tlnn
NEe
pPD7554/64
DC Characteristics (cont)
=
=
=
=
",PD7554 only: TA
-10°C to +70°C, Voo
2.5 V to 3.3 V, GND
0V
",PD7554/64: TA
-10°C to + 70°C, Voo 2.7 V to 6.0 V, GND = 0 V
=
(Voo
= 2.5-3.3) 7554 only
(Voo
Limits
Parameter
Symbol
Min
~p
= 2.7 to &.0
V) 7554/&4
Limits
Max
Min
~p
Max
UnH
Test
CondHlons
Supply current, normal
operation, R oscillation
1001
270
900
,.,A
VOO = 5 V ± 0.5 V
R = 56 kO = 2%
Supply current, normal
operation, R oscillation
1001
80
240
,.,A
VOO = 3 V ± 10%
R = 100 kO ± 2%
Supply current,
HALT mode, R osc.
1002
25
180
,.,A
VOO = 3 V ± 0.3 V
R = 150 kO ± 2%
1002
18
60
,.,A
VOO = 2.5 V
R = 150 kO ± 2%
Supply current, HALT mode,
ceramic osc.
1002
450
1500
,.,A
VOO = 5 V ± 0.5 V
fcc = 700 kHz
Supply current, HALT mode,
ceramic osc.
1002
65
200
,.,A
VOO = 3.0 V ± 10%
fcc = 300 kHz
Supply current,
HALT mode, R osc.
1002
120
400
,.,A
VOO = 5 V ± 0.5 V
R = 56 kO ± 2%
Supply current,
HALT mode, R osc.
1002
35
110
,.,A
VOO = 3 V ± 10%
R = 100 kO ± 2%
10
Supply current, STOP mode
1003
Supply current, STOP mode
1003
0.1
5
0.1
,.,A
VOO
Supply current, STOP mode
1003
0.1
p.A
VOO = 3 V ± 10%
Supply current, data
retention mode
1000R
0.1
,.,A
VOOOR
0.1
5
,.,A
Pull-up/down resistance,
Port 0, RESET
RP1
23.5
47
70.5
23.5
47
70.5
kO
Pull-up resistance
Ports 8-11
RP2
7.5
15
22.5
7.5
15
22.5
kO
=5V ±
= 2.0
0.5 V
V
Note:
(1) N-channel open drain I/O ports.
(2) JAPD7554 only
AC Characteristics
=
=
IlPD7554 only: TA = -10°C to +70 0 C, Voo
2.5 V to 3.3 V, GND
0V
IlPD7554/64: TA
-10°C to + 70°C, Voo= 2.7 V to 6.0 V, GND
0V
=
(Voo
=
= 2.5 - 3.3) 7554 only
(Voo
Limits
limits
Symbol
Min
~p
Max
System clock osc. frequency (1)
fcc
140
180
220
System clock osc. frequency (1)
Parameter
= 2.7 to 6.0 V) 7554/64
Test
Conditions
Min
~p
Max
kHz
R = 150 kO ± 2%
fcc
400
500
600
kHz
System clock osc. frequency (1)
fcc
200
350
300
kHz
Voo = 4.5 V to
6.0 V; R = 56
kO ± 2%
Voo = 3 V ± 10%; R
= 100 kO ± 2%
System clock osc. frequency,
CL1, CL2
fcc
140
External clock frequency, CL1
fc
10
External clock frequency, CL1
fc
10
710
kHz
Voo = 4.5 V to 6.0 V;
50% duty
External clock frequency, CL 1
fC
10
350
kHz
Voo
duty
175
Unit
kHz
240
250
Voo = 2.5 V R = 150
kO ± 2%; 50% duty
kHz
= 2.7 V;
50%
3-291
I]
NEe
pPD7554/84
AC Characteristics (cont)
j.lPD7554 only: TA = -10°C to +700 C, Voo = 2.5 V to 3.3 V, GND = 0 V
j.lPD7554/64: TA = -10°C to +700 C, VOO= 2.7 V to 6.0 V, GND = 0 V
(You
= 2.5-3.3) 7554 only
(VDO
LImItS
Parametar
System clock osc.
frequency (2)
= 2.7 to 6.0 V) 755"64
LImItS
1W
Max
fcc
290
700
710
kHz
Voo
290
500
510
kHz
Voo
tos
System clock rise time, CL1
1W
Max
Test
Conditions
Min
Oscillation stabilization
time (2)
Min'
Unit
Symbol
290
400
410
kHz
Voo
290
300
310
kHz
Voo
j.lS
Voo
20
tCR
200
200
System clock fall time, CL1
tCF
200
200
System clock pulse width
tCH
System clock pulse width
tCH
System clock pulse width
tCl
2
50
2
50
0
250
= 4.5 to 6.0 V
= 4.0 to 6.0 V
= 3.5 to 6.0 V
= 2.7 to 6.0 V
= 2.7 to 6.0 V
ns
ns
j.lS
0.7
50
1.45
50
j.lS
j.ls
Voo = 2.7 V
50% duty
System clock pulse width, CL1
tCl
External clock frequency (POo)
fpoo
External clock frequency (POo)
fpoo
0
710
kHz
Voo = 4.5 V to 6.0 V;
50% duty
External clock frequency (POo)
fpoo
0
350
kHz
Voo
duty
= 2.7 V 50%
ns
Voo
= 4.5 V to 6.0 V
Voo
= 2.7 V
kHz
POo rise time
tCRPOO
200
200
POo fall time
tCFPO
200
200
POo pulse width
tpOOH
POo pulse width
tpOOH
POo pulse width
tpOOl
POa pulse width
tpOOl
INTO high time
tlOH
30
INTO low time
tlOl
RESET high time
tRSH
RESET low time
tRSl
RESET setup time
tSRS
RESET hold time
tHRS
SCK cycle time
tKCY
8.0
/AS
Input
SCK cycle time
tKCY
10.0
/AS
Output
SCK cycle time
tKCY
2.0
/AS
Input; Voo
to 6.0 V
SCK cycle time
tKCY
2.5
/AS
Output; Voo = 4.5 V
to 6.0 V
2
ns
/AS
0.7
2
/As
/As
1.45
/AS
10
/As
30
10
/As
30
10
/AS
30
10
/As
0
0
/As
'0
0
/As
= 4.5 V
= 2.7 V
SCK cycle time
tKCY
5.0
SCK cycle time
tKCY
5.7
/AS
j.ls
Output; Voo = 2.7 V
SCK pulse width
tKH
/As
Input
SCK pulse width
tKH
1.0
"'S
Input; Voo = 4.5 V
to 6.0 V
SCK pulse width
tKH
1.25
"'s
Output; Voo
to 6.0 V
/AS
Output
/As
Input; Voo = 2.7 V
SCK pulse width
tKl
SCK pulse width
tKl
3-292
4.0
5.0
2.5
Input; Voo
= 4.5 V
NEe
pPD7554/64
AC Characteristics (cont)
=
=
=
",PD7554 only: TA
-1O o e to +70o e, Voo
2.5 V to 3.3 V, GND
0V
",PD7554/64: TA
-1O o e to + 70 o e, VDD
2.7 V to 6.0 V, G N D = 0 V
=
=
(Voo
= 2.5-3.3) 7554 only
(Voo
limits
Parameter
Symbol
Min
~p
= 2.7 to &.0 V) 7554/&4
limits
Max
Min
~p
Max
Unit
SCK pulse width
tKL
2.85
",s
SI setup time to SCKt
tSIK
0.3
0.1
!AS
SI hold time after SCKt
tKSI
0.3
0.1
!AS
SO output delay time
after SCKt
tKSO
SO output delay time
after SCKt
tKSO
SO output delay time
after SCKt
' tKSO
2.0
Test
Conditions
Output; VOO = 2.7 V
!-,S
GOUT = 100 pF max.
0.85
!-,S
Voo = 4.5 V to 6.0 V;
GOUT = 100 pF max.
1.2
",s
Voo = 2.7 V;
GOUT = 100 pF max.
(1) ",PD7554 only
(2) ",PD7564 only
3-293
NEe
pPD7554/64
Timing Waveforms
Clocks
Data Retention Mode f.lPD7554 .
1-----1Ifc-----'-~
flPD7554 ~I'-----STOP Mode.-----~
Operating
Mode
Voo :-..----l
CL1----"'\.
t
POO _ _ _ _ _
1/POO
:l-=
tPOOL~FtPOOH
~::
(1) VIHI
(2) VODDR
(3) VIHOR
(4) VIU
RESET
tSRS
83-002612A
tpooR::::fLtPOOF
83-002609A
Data Retention Mode f.lPD7564
External Interrupt
HALT Mode
Operating
flPD7564\1+.----STOP M o d e - - - -...
·l---+{ -Mode
Voo
83-002610A
Reset
RESET-----------------J
RESET
----t=·~'T·""~:: ~:~
83-002611 A
Serial Interface
1----tKCy----+t
SCK----""\
SI-----+---~
SO
Data
_Output
_
_VA83-002628A
83-002613A
NEe
NEe Electronics Inc.
J,tPD7556/66
4-BIT, SINGLE-CHIP
CMOS MICROCOMPUTERS
WITH COMPARATOR
Description
Pin Configuration
The J,lP07556 and J,lP07566 are low-end versions of
J,lP07500 series products. These microcomputers incorporate a 4-bit comparator input and are useful as slave
CPUs to high-end J,lP07500 series or B-bit J,lCOM-B7
series products.
The J,lP07556/66 has output ports that can directly drive
triacs and LEOs. Also, various mask-optional 1/0 circuits can be configured for a wide selection of outputs
allowing a reduction of external circuitry in your design.
There are two testable interrupts.
The J,lP07556 and J,lP07566 differ only in their clock circuitry. The J,lP07556 uses an external resistor with an in~
ternal capacitor for an RC oscillator clock, where the
J,lP07566 uses a ceramic oscillator as a clock. These microcomputers are ideally suited to control devices such
as air conditioners, microwave ovens, refrigerators, rice
cookers, and audio equipment.
83-001994A
Pin Identification
Symbol
1, 2
POo I INT0
P01/VREF
2-bit input port 0I testable input pin I
comparator reference voltage input pin
3-6
P1o/CINo
PV CIN 1
P12/CIN2
P13/CIN3
4-bit input port 1I 4-bit comparator
inputs
7-9,
10
P80-P82,
P83/CL2
3-bit output port 8 (7566),
3- .(4-) bit output port 81 connection for
RC oscillator (7556) I Ceramic resonator
(7566)
11
CL1
Connection for ceramic resonator I RC
oscillator
Features
o
o
45 instructions (subset of J,lP07500 set 8)
Instruction cycle:
- External clock:
2.B6J.ls/700 kHz, 5 V
- RC osci Ilator (J,.tP07556):
4 J.ls 1500 kHz, 5 V
- Ceramic oscillator (J,.tP07566): 3J.ls/660 kHz, 5 V
o Program memory (ROM) of 1024 x B bits
o Data memory (RAM) of 64 x 4 bits
DB-bit timerlevent counter
o 1/0 lines:
- J,lPD7556: 20
- J,lPD7566: 19
o Data memory retention at low supply voltage
o Standby (STOP I HALD functions
o CMOS technology
o Low power consumption
o Single power supply (2.5 V to 6.0 V J.lPD7556)
(2.7V to 6.0V J,lPD7566)
Function
No.
12
VDD
+5 V power supply
13
RESET
Reset input pin
14-17
P10rP103
4-bit I 10 port 10
18-21
P11o-P113
4-bit I 10 port 11
22-23
P90-P91
2-bit output port 9
24
GND
Ground
Ordering Information
Part Number
Package Type
J.lPD7556CS
24-pin plastic shrink DIP
J.lPD7566CS
24-pin plastic shrink DIP
J.lPD7556G
24-pin plastic SO
J.lPD7566G
24-pin plastic SO
3-295
NEe
J,lPD7556/66
Pin Functions
POOIINTO, PD1/VREF
(Port O/count clock input/comparator reference
voltage input)
2-bit input port O/count clock input/comparator reference voltage input. INTO is an edge-sensitive testable
input pin that detects a signal at the rising edge. VREF is
the comparator reference voltage input pin. A mask option specifies whether this pin is used as P01 or VREF.
POa/INTO is unused; connect it to ground. If PD1 /VREF is
unused, connect it to ground or Voo. The port is in the
input state at reset.
P10/CINO-P13/CIN3 (Port 1/comparator inputs)
4-bit input port 1/comparator inputs. A mask option
specifies whether these pins are used as digital inputs
(Port 1) or as comparator inputs (CINo-CIN3). If any of
P1a-P13 pins are unused, connect them to ground or
Voo. The port is in the input state at reset.
PSo-P82, P83/CL2 (Port 8/clock input 2)
4-bit output port 8. This port sinks 15 rnA and can interface to 12V. On the /APD7556, the port function of P83/
CL2 is specified by mask option. PBs is a normal output
port on the /APD7556. On the /APD7556, CL2 is one of the
pins to which a resistor for RC oscillation is connected.
On the /AP07566, CL2 is one of the pins to which a ceramic resonator is connected. If any of P80-P82 pins are
unused, leave them open. The port is in the high impedance state at reset.
CL1 (Clock input 1)
On the /APD7556, CL1 is one of the two pins to which a
resistor for RC oscillation is connected. On the
/APD7566, CL1 is one of the two pins to which a ceramic
resonator i.s connected.
Vee (Power supply)
Positive power supply.
RESET (Reset)
System reset input pin (active high). This pin can be internally connected to a pull-down resistor if specified by
mask option.
P100-P103 (Port 10)
4-bit I/O port. This port sinks 10 rnA and can interface to
12V. If any of these pins are unused, connect them to
ground or Voo in the input state, or leave open in the
output state. The port is in the high impedance or highlevel output state at reset.
P110-P113 (Port 11)
4-bit I/O port. This port sinks 10 rnA and can interface to
12V. If any of these pins are unused, connect them to
ground or Voo in the input state, or leave open in the
output state. The port is in the high impedance or highlevel output state at reset.
P90-P9-, (Port 9)
2-bit output port. This port sinks 15 rnA and can interface to 12 V. If either of these pins is unused, leave it
open. The port is in the high impedance state at reset.
GND (Ground)
Ground.
3-296
NEe
JJPD7556/66
Block Diagram
INTO/POe
r-;.;;;;--1---- POe/INTO
P10/CINO-P13/CIN3
Program Memory
1024x8Blts
P90-P91
Instruction
Decoder
P10e-P103
Data Memory
64x 4 Bits
P110-P113
CL1
CL2
t t t
VDD GND RESET
83-0019958
Absolute Maximum Ratings
TA=25OC
Power supply voltage, Voo
-0.3Vto +7V
Input voltage, ports other than 10 & 11, VI
-0.3 V to Voo +0.3 V
Input voltage, ports 10,11, V, (1)
- 0.3 V to Voo +0.3 V
Input voltage, ports 10,11, V, (2)
-0.3VtoVoo +13 V
Output voltage, ports other than 8, 10 & 11, Vo
- 0.3 V to Voo +0.3 V
Output voltage, ports 8, 10, 11, Vo (1)
- 0.3 V to Voo +0.3 V
Output voltage, ports 8, 10, 11, Vo (2)
-0.3VtoVoo +13 V
Output current high, one pin, IOH
Output current high, aU output ports total, IOH
-5mA
-15mA
Output current low, ports 10, 11, IOL
15mA
Output current low, ports 8, 9, IOL
30mA
Output current low, aU ports total, IOL
Operating temperature, TOPT
100mA
Comment: Exposing the device to stresses above those listed in Abso-
lute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits dascribed in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
Note:
(1) CMOS push pull or N-channel open drain + pull up resistor 110
(2) N-channel open drain 1/0
Capacitance
TA = 25°C, Voo=GND=OV, f=1.0MHz, Unmeasured pins returned to
GND
Umlta
Parameter
Symbol
Min
Typ
Max
Unit
pF
POO-P01;
P10-P13,
GINO-GIN3
35
pF
Ports 8,9
35
pF
Ports 10, 11
Input
capacitance
Storage temperature, TSTG
Power dissipation, Po
Output
capaCitance
liD
capacitance
GOUT
Test
Conditions
3-297
NEe
IJPD7550/66
DC Characteristics
",PD7556:TA= -10°C to +70 oc, Voo= +2.5V to 3.3 V, GND=OV
",PD7556/",PD7566:TA = -10OCto +70OC, Voo= +2.7V to 6.0 V, GND=OV
Umlts
TA =10 0 Cto HOoC,
YDD= +2.5Yto3.3Y
j.lPD7558
Parameter
Input voltage low
Input voltage, high
Output voltage low
Symbol
Min
VIL1
VIL2
TA = 10°C to + 70°C,
YDD= +2.7Yt08.0Y
j.lPD75881j.1PD7558
Typ
Max
Min
0
0. 2V OO
0
0. 3VOO
V
Except CL1
0
0.3
0
0.5
V
CL1
VIH1
0. 8V OO
VOO
0. 7V OO
VOO
V
Except CL1
VIH2
Voo-0.3
CL1
0.5 VOO
0. 7V OO
VOD
12(1)
V
VIH3
VOO
12(1)
Voo-0.5
V
Ports 10,11
VIHDR
0.7VDDOR
VOODR+0.2
0.9VDDDR
VDDDR+0.2
V
RESET; data retention
V
Ports 10,11;
IOL=350j.iA
0.4
V
Ports 10,11;
VDD=4.5 V to 6.0V,
IOL=t6mA
2.0
V
Ports 10,11;
VOD=4.5Vto 6.0V,
IOL =10mA
0.5
V
Ports 10,11;
VOD=2.7V,
IOL =400j.iA
V
Ports 8,9;
10L =500j.iA
2.0
V
Ports 8,9; VOD=4.5 V
t06.0V,IOL=15mA
0.5
V
Ports 8,9;
Voo=2.7V,
IOL = 600 j.iA
V
Ports 8-11;
IOH= -80j.iA
Voo-2.0
V
VOD-tO
V
Ports 8-11;
VDO=4.5 V to 6.0V,
IOH=1mA
Ports 8-11;
VDO=2.7V,
IOH=100j.iA
2.0
V
0.5
VOL
0.5
Output voltage high
VOH
VDD-tO
Supply voltage,
data retention mode
VDDOR
2.0
Input leakage current
IU1
-3
IU2
-10
IL01
IL02
3-298
3
-3
3
j.iA
Except CL1;
OV~VI~VDD
10
-10
10(1)
IU3
Output leakage current
T.st
Conditions
Unit
Max
Typ
-3
3
10(1)
-3
OV~VI~VDD
10
j.iA
CL1;
10(1)
j.iA
Ports 10,11; VO=12V
3
j.iA
OV~VO~VDO
10(1)
j.iA
Ports 8-11; Vo = 12 V
~EC
JlPD7556/66
DC Characteristics (cont)
IlPD7556:TA= -10°C to +70 o c, Voo= +2.5Vto3.3V,GND=OV
IlPD7556/IlPD7566: TA = -10°cto +70°c, Voo = +2.7Vto6.0V, GND=OV
Limits
TA = 10°C to HOoC,
VDD = +2.5 V to 3.3 V
J.lPD7556
Parameter
Supply current, normal
operation
Supply current, HALT mode
Supply current, STOP mode
Supply current,
data retention mode
Symbol
Min
IOD1
1002
Max
55
180
~
Roscillation;
Voo=3V±0.3V,
R=150k2±2%
40
150
~
Roscillation;
Voo=2.5V,
R=150k2±2%
IOOOR
Min
Typ
Test
Conditions
Typ
Max
Unit
650
2200
~
Ceramic oscillation;
Voo=5 V ±0.5 V,
fcc= 700 kHz
120
360
~
Ceramic oscillation;
Voo=3V±10%,
fcc=300 kHz
270
900
p.A
Roscillation;
Voo=5V±0.5V,
R=56k2±2%
80
240
p.A
Roscillation;
Voo=3V±10%,
R=100k2±2%
25
80
p.A
Roscillation;
Voo=3V±0.3V,
R=150k2±2%
18
60
p.A
Roscillation;
Voo=2.5V,
R=150k2±2%
0.1
1003
TA = 10°C to HOoC,
VDD= +2.7Vt06.0V
J.lPD75661J.1PD7556
450
1500
p.A
Ceramic oscillation;
Voo=5 V ±0.5 V,
fCC = 700kHz
65
200
p.A
Ceramic oscillation;
Voo=3V ±10%,
fcc=300 kHz
120
400
p.A
Roscillation;
Voo=5V±0.5V,
R=56k2±2%
35
110
p.A
R oscillation;
Voo=3V±10%,
R=100k2±2%
0.1
10
0.1
5
5
0.1
5
0.1
!lA
!lA
!lA
!lA
Voo=5V±0.5V
Voo=3V±10%
VOOOR=2.0V
Pull·up / down resistance
RP1
23.5
47
70.5
23.5
47
70.5
k2
Port 0, RESET, Port 1
Pull·up resistance
RP2
7.5
15
22.5
7.5
15
22.5
k2
Ports 8-11
Note:
(1) N-channel open-clrain 1/0 ports.
3-299
11
NEe
IJPD7556166
Comparator
TA= -10 0 eto +7o oe, Voo=3.0Vto6.0V,GND=OV
Limits
jAPD7556
Parameter
Symbol
Typ
Min
jAPD7566
Max
Min
Voo
0
Typ
Max
Unit
Voo
V
Test
Conditions
Input voltage range
VCIN/
VREF
Response time
TCOMP
4
4
Input voltage resolution
AVCIN
100
100
mV
All comparators
50
mV
All comparators;
Voo=5V±0.5V
~
All comparators
10
Input leakage current
ICIN/
IREF
10
50
-3
-3
All comparators
MC(1) All comparators
VREF bias resistance (R1, R2)
BIAS
100
100
kQ
(R1 = R2) typically
Comparator circuit current
IOOCMP
50
50
~
Comparator;
Voo=5V±0.5V
Note:
(1) Machine cycle.
AC Characteristics
,",PD7556:TA = -10 0 eto + 70 oe, voo = +2.5Vto3.3V, GND=OV
,",PD7556',",PD7566:TA = -10 0 eto +70 oe, voo= +2.7V to 6.0 V, GND =OV
Limits
=
=
=
TA 10°C to +70 oC,
Voo +2.5 Vto 3.3 V
jAPD7556
Parameter
System clock oscillator
frequency
Symbol
Min
Typ
Max
fcc
140
180
220
140
External clock frequency
System clock rise time
System clock fall time
TA 10°C to +70 oC,
Voo= +2.7Vto6.0V
jAPD75661jAPD7556
fc
175
10
Typ
Max
kHz
R=150kQ±2%
400
500
600
kHz
Voo=4.5 Vto 6.0V;
R=56kQ±2%
200
250
300
kHz
Voo=3V ±10%,
R=100kQ±2%
kHz
CL1, CL2;
Voo=2.5V;
R=150kQ±2%
210
Unit
kHz
CL1; 50% duty
10
710
kHz
CL1; Voo=4.5 V to
6.0V; 50% duty
10
350
kHz
CL1; Voo=2.7V;
50% duty
250
tCR
200
200
ns
CL1
200
ns
CL1
tCF
200
System clock pulse width,
low
tCl
50
System clock pulse width,
high
tCH
50
,",S
1.45
50
/As
CL1; Voo=2.7V
/As
0.7
fcC
3-300
Test
Conditions
Min
50
/As
CL1; Voo=4.5 V to
6.0V
290
700
710
kHz
Voo=4.5t06.0V
290
500
510
kHz
Voo=4.0to 6.0V
290
400
410
kHz
Voo = 3.5 to 6.0 V
290
300
310
kHz
Voo=2.7 to 6.0V
NEe
J,lPD7556/66
AC Characteristics (cont)
JAPD7556:TA = -10 0 cto + 70°C, Voo = +2.5Vto3.3V, GND=OV
JAPD75561JAPD7566: TA = -10 0 cto +70 oc, Voo = +2.7V to 6.0 V, GND=OV
Limits
TA=100Cto HOoC,
VDD= +2.7Vt08.0V
/lPD75881j1PD7558
TA = 10°C to HOoC,
VDD= +2.5Vt03.3V
jlPD7558
Symbol
Min
Oscillator setup
tos
20
External clock frequency
(POo)
fpOO
o
Parameter
Max
Typ
Min
Typ
Max
JAS
250
kHz
50% duty
710
kHz
Voo=4.5Vto6.0V;
50% duty
0
350
kHz
Voo=2.7V; 50% duty
POo rise time
tCRPO
200
200
ns
tCFPO
200
200
ns
POo pulse width, low
tpOOL
/AS
1.45
/AS
0.7
JAS
INTO low time
tlOL
30
10
INTO high time
tlOH
30
10
10
tRSL
30
RESET high time
tRSH
30
10
RESET setup time
tSRS
0
0
tHRS
0
0
RESET hold time
Voo=2.7V
JAS
tpOOH
RESET low time
Oscillator stabilization
time after Voo=4.5 V
0
POofall time
POo pulse width, high
Test
Conditions
Unit
Voo=4.5 V to 6.0 V
Timing Waveforms
Clocks
CL1
External Interrupt
--,-F'''jF''"~1
=~~
:i-=
INTO----C'~'T''''=_t_=~::
83-002610A
btCR:dl-tCF--li=-
t
POo _ _ _ _
1/POo
tPOOL~ FPOOH
~:~
Reset
tpooRdLtPOOF
83-002609A
Data Retention Mode - JAPD7566
83-002611A
HALT Mode
I'PD7564I
Operating
Mode
Data Retention Mode - JAPD7556
Voo
Operating
I'PD7554I'
Mode
Voo:----ool
(1) V,HI
(2) VOODR
(3) V,HOR
(4) V,L,
RESET _ _ _ _ _ _ _ _ _ _.....J
RESET
83-002613A
tSRS
IHRS
83-002612A
3-301
NEe
JiPD7556166
Pin Mask Options
Figure 2.
Table 1 shows the mask options for all the port pins and
the RESET pin. You may select these options in bit
units.
Type 2 Schmitt· triggered Input:
P10-P13/C/No-C/N3
VDD
--vvv--,
oMask Option
o
Table 1.
Pin Mask Options
Pin
Options
POO
1
2
3
No connection to internal resistor
Connected to Internal pull-up resistor
Connected to internal pull-down resistor
P01/VREF
1
2
3
4
No connection to internal resistor
Connected to internal pull-up resistor
Connected to internal pull-down resistor
Used as VREF pin
A bias of Voo 12 internally applied to VREF pin
Bias not applied
P1o/CINoP13/CIN3
1
2
3
4
No connection to internal resistor
Connected to internal pull-up resistor
Connected to internal pull-down resistor
Used as comparator input pins
P8o-P82
P90-P91
1
2
CMOS (push-pull) output
N-channel open-drain output
P83-CL2 (7556)
option one
1
2
Used as P83
Used as CL2
P83-CL2 (7556)
option two
1
2
CMOS push-pull
N-channel open-drain
P10o-P103
P11o-P113
1
2
3
N-channel open-drain input/output
CMOS (push-pull) input/output
N-channel open-drain input/output with internal
pull-up resistor
RESET
1
2
Connected to internal pull-down resistor
Not connected to internal pull-down resistor
83-OO1997A
Figure 3.
Type 3 Input Cell: PO,IVREF
VDD~
Mask OptionO
~O~'"
Reference
Voltage
83-001998A
Figure 4.
Type 4 Output Cell: PBo-PB3J
P90-P9,
110 Pin Configurations
Oata---.__--4
Figure 1.
Type 1 Input Cell (part of Type 2)
VDD~
Out
Mask Option
o
~-"""----1I----o In
83-001999A
83-001996A
3-302
NEe
Figure 5.
fJPD7556/66
Type 5//0 Cell: P10o-P103,
P11o-P113
Figure 7.
Program Memory Map
OO'OO"n
Voo
08t8--_...---,.
~t. ,""'.,
q-----oln/Out
Figure 8.
Configuration of General Purpose
Registers
MIddle-level Voltage Input Buffer
1
Figure 6.
0
3
0
01r--""";"1
83-002590A
Type 6 Schmitt· triggered Input:
POollNTO
Data Memory
1
The data memory is static RAM with a capacity of 64
words by 4 bits. Part of this memory is used as the stack
area. The data memory is also used in a-bit data
processing when paired with the accumulator. Figure 9
shows the data memory map.
Program Memory
Data memory can be addressed directly, with the
immediate data from an instruction; indirectly, with the
contents of HL (including autoincrement and
autodecrement); and indirectly by the contents of the
stack pointer.
The ~PD7556/66 has a mask-programmable ROM with a
capacity of 1024 words by8 bits for program storage or
table data. It is addressed by the program counter. The
reset start address is OOOH. Figure 7 shows the program
memory map.
You may use any area of the data memory as the stack.
The boundary of the stack is determined by how the
TAMSP instruction initializes the stack pointer. Once
the boundary is set, a call or return instruction
automatically accesses the stack.
General Purpose Registers
When a call instruction is executed, the contents of the
program counter and the program status word (PSW)
are stored to the stack in the sequence shown in figure
10.
83·002591A
Two registers, H (2-bit) and L (4-bit), are provided as
general purpose registers. Each register can be
individually manipulated. The two registers also form
pair register HL; H being the high register and L being
the low one. The H L register is a data pointer to address
data memory. Figure a shows the configuration of the
general purpose registers.
The L register also specifies an 1/0 port or mode
register when an 1/0 instruction (IPL or OPL) is
executed. It also specifies the bits of a port when the
SPBL or RPBL instruction is executed.
When a return instruction is executed, the contents of
the program counter are automatically restored, but the
PSW is not. The contents of data memory can be
retained with a low supply voltage during STOP mode.
Accumulator
The accumulator is a 4-bit register used in arithmetic
operations. The accumulator can process a-bit data
when paired with the data memory addressed by HL.
Figure 11 shows the configuration of the accumulator.
3-303
t-IEC
fJPD7556166
Figure 9.
When a RESET is input, the SK1 and SKO flags are
cleared to zero and the contents of the carry flag are
undefined.
Data Memory Map
(0) OOH
Figure 12.
Configuration of the Program Status Word
64 words x 4 bits
3
2
SK1
SKo
0
I I I I c Ipsw
(63) 3FH "'--_ _ _.....
0
83-002597A
83-002594A
System Clock Generator
Figure 10.
Call Instruction Storage to Stack
The system clock generator consists of a RC oscillator
(7556) a ceramic resonator (7566), a 1/2 frequency divider,
standby modes (STOP/HALn, and control circuit. Figure 13 is a circuit diagram of the system clock generator
for the ",PD7556.
Stack Area
3
0
SP·3
ololpcslpcs
psw·
SP·2
PC3·PCO
SP·1
PC7·PC4
SP·4
*Blt 1 of PSW
is always o.
83-002595A
Figure 11.
Configuration of the Accumulator
Arithmetic Logic Unit
The arithmetic logic unit (ALU) is a 4-bit arithmetic
circuit that performs operations such as binary
addition, logical operation, increment, decrement,
comparison, and bit processing.
Program Status Word
The program status word (PSW) consists of two skip
flags (SKO and SK1), a carry flag (C), and bit 1, which is
always zero. Figure 12 shows the configuration of the
PSw.
The contents of the PSW are stored to the stack when a
call instruction is executed, but are not restored from
the stack by the return instruction.
The skip flags retain the following skip conditions:
string effect by LAlor LHLI instruction, and skip
condition satisfied by an instruction other than a
string-effect instruction. The skip flag is set or reset in
accordance with the instruction executed.
The carry flag is set to 1 if an addition instruction (ACSC)
generates a carry from bit 3 of the ALU. If no carry is
generated, the flag is reset to zero. The SC instruction
sets the carry flag and the RC instruction resets it.
3-304
In the J..tPD7556, the RC oscillator operates with a single
external resistor connected across CL1 and CL2 (the
capacitor C is incorporated). When the RC oscillator is
not used, external clock pulses can be input via the CL1
pin. In this case, the RC oscillator functions as an
inverting buffer. The output from the RC oscillator
serves as the system clock (CL) which is then divided by
two and used as the CPU clock (+).
The standby mode control circuit is made up of a STOP
flip-flop and a HALT flip-flop. The STOP instruction sets
the STOP flip-flop and stops the system clock supply.
This flip-flop also stops the RC oscillator. The STOP
flip-flop is reset by the standby release signal that
becomes active when one of the test request flags is set
or at the falling edge of the RESET signal. When the
STOP flip-flop is reset, the RC oscillator resumes
operation and supplies the system clock.
The HALT instruction sets the HALT flip-flop which
disables signals from going to the 1/2 frequency divider
that generates the CPU clock. Only the CPU clock stops
in HALT mode. The HALT flip-flop is set or reset by the
same conditions as the STOP flip-flop.
Figure 14 shows the system clock generator circuit for
the J..tPD7566.
On the J..tPD7566, the ceramic oscillator operates with a
ceramic resonator connected across CL1 and CL2. The
output from the ceramic oscillator is used as the system
clock (CL); it is divided by two to produce the CPU clock
(+).
The standby mode control circuit is made up of a STOP
flip-flop and a HALT flip-flop. The STOP instruction sets
the STOP flip-flop and stops the ceramic oscillation,
thus stopping the supply for all clocks. The STOP
flip-flop is reset by the RESET signal (high level) and
restarts ceramic oscillation. The supply of each clock
resumes when RESET goes low.
NEe
Figure 13.
J..lPD7556 166
System Clock Generator for JAPD7556
STOP F/F
S ~--------,-- STOp·
Q
HALT F/F
R
S
Q
HALT·
RESET (High)
R
Standby Release
CL2
"'-_"--
- RESET (~)
~
(to CPU)
L -_ _ _ _ _ _ _ _ _ _ _ CL (System Clock)
·Execution of Instruction
83-0025988
Figure 14.
11
System Clock Generator for JAPD7566
STOP F/F
Q
S J-.-------1
R
STOp·
HALT F/F
HALT*
CL1
RESET (High)
Ceramic
Oscillator
Standby Release
CL2
RESET ' - RESET
~
(To CPU)
CL (System Clock)
• Execution of Instruction
83-0025998
The HALT instruction sets the HALT flip-flop which
disables signals from going to the 1/2 frequency divider
that generates the CPU clock. Only the CPU clock stops
in HALT mode. The HALT flip-flop is reset by the HALT
RELEASE signal (activated by setting at least one test
request flag) or the falling edge of RESET, resuming
supply of the CPU clock.
The HALT flip-flop is also set when RESET is active (high
level). At power-on reset operation, the rising edg~ of
RESET starts ceramic oscillation; however, some time
is required to achieve stable oscillation. To prevent the
unstable clock from operating the CPU, the HALT
flip-flop is set and the CPU clock is stopped while
RESET is high. Accordingly, the high-level width. of
RESET must be more than the required stable time for
the ceram ic resonator.
Clock Control Circuit
The clock control circuit consists of a 2-bit clock mode
register (bits CM1 and CM2), prescalers 1, 2, and 3, and a
multiplexer. It takes the output of the system clock
generator (CL) and event pulses (POo).1t also selects the
clock source and prescaler according to the setting in
the clock mode register and supplies the timer/event
counter with count pulses. Figure 15 shows the clock
control circuit.
Table 2 lists the codes set in the clock mode register by
the OPL instruction to specify the count pulse
frequency.
3-305
NEe
J-lPD7556/66
Figure 15.
Test Control Circuit
Clock Control Circuit
The /-tPD7556/66 has two test sources, as shown in
table 3.
Table 3.
CL
/-tPD7556/66 Test Sources
Source
Function
Location
Request Flag
INTT
Overflow in timer I event counter
Internal
INTT ROF
INTO
Test request signal from POo pin
External
INTO ROF
The test control circuit consists of two test request
flags (INTT RQF and INTO RQF) set by the two test
sources, the SM3 flag which determines whether INTO
is enabled, and a test request flag control circuit that
checks the contents of each test request flag by
executing an SKI instruction and resetting the flags.
The OPL instruction (L = FH, corresponding to A3) sets
the SM3 flag. INTO is enabled when SM3 =1.
"Instruction
Execution
83-002600A
Table 2.
Selecting the Count Pulse Frequency
CM2
CM1
Frequency Selected
o
o
o
CL/256
o
CL/32
POo
CL/4
When you set the clock mode register with the OPL
instruction, clear bit 0 of the accumulator
(corresponding to bit CMO of the EVAKIT-7500 or
/-tPD7500H during emulation).
Timer/Event Counter
The timer/event counter is a binary 8-bit up-counter
which is incremented each time a count pulse is input.
The TIMER instruction or a RESET signal clears it to
OOH. When an overflow occurs, the counter is reset from
FFH to OOH. Figure 16 shows the inputs and outputs of
the counter.
Figure 16.
Timer/Event Counter
Request flag INTO RQF is set at the rising edge of the
signal input to the INTO/POa pin and the SKI instruction
resets it.
The logical sum of the outputs from the test request
flags release HALT mode. The mode is released when
one or both flags are set. Both flags and SM3 are reset
when the RESET signal is input. After reset, signal input
to the INTO pin is inhibited as the initial condition.
Figure 17 is a block diagram of the test control circuit.
Standby Modes
The /-tPD7556/66 has two standby modes to reduce
power consumption while the program is in the wait
state. The STOP and HALT instructions set these
modes.
When the program enters a standby mode, program
execution stops and the contents of all registers and
data memory immediately before the program entered
standby mode are retained. The timer can operate even
in HALT mode.
The RESET signal or standby release signal (7556 only)
releases STOP mode. HALT mode is released when one
or both of the test request flags are set, or when the
RESET signal is input. The program cannot enter a
standby mode when a test request is being set, even if
the STOP or HALT command is executed.
CP
If there is some uncertainty as to the state of the test
request flags, execute the SKI instruction to reset them
so the program can enter standby mode.
"Instruction Execution
83-002601 A
3-306
The request flag INTI RQF is set when a timer overflow
occurs in the timer event counter. The SKI or TIMER
instruction resets it.
NEe
Figure 17.
J-lPD7556/66
Test Control Circuit Block Diagram
OPL(Note1)
INTT--+----I
HALT
Release
INTOv---...
Note (1)
~
Instruction execution
83-0026028
Table 4 compares STOP and HALT modes. The main
difference is that STOP mode stops the system clock
and HALT does not. Oscillation stops during STOP
mode. The power consumeq by the oscillator is the
difference between the two modes. In STOP mode, data
memory can be retained with a lower supply voltage.
Figure 18.
Power·on Reset Circuit
VDD
~
Table 4.
Mode
CL
STOP
x
HALT
"PD7564
RESET
STOP and HALT Modes
POo
x
CPU
x
o
x
Timer
Released by
RESET input
INTIRQF,
INTO RQF
(7556 only)
INTIRQF
INTO RQF
RESET input
Note:
83-002603A
Figure 19.
Power·on Reset Circuit with Pull· down
Resistor
VDD
"PD7564
o=operales
x = stops
~= operational depending on clock source
RESET
Power·on Reset Circuit
Figure 18 shows a circuit example of the power-on reset
circuit using a resistor and a capacitor. This is the
simplest reset control circuit. Figure 19 shows the
circuit with a pull-down resistor internally connected to
RESET as a mask option.
GND
B3-OO2604A
Figures 20 to 23 show examples of application circuits
for the /iPD7556/66.
3-307
NEe
JAPD7556166
Figure 20.
Refrigerator or Air Conditioner Circuitry
LEDx4
12VMax
RES
PBo
PB1 '
P82
CIN1
CIN2
P90
P91
P113
CMOS
Output
CINo
Comparator
Input
CIN3
~PD7566
VREF
I
P100
P101
P102
CMOS
Output
INTO
With Pull-Up
Resistor
P103
-:-
CL1
CL2
J
Note:
J
With
Pull-Down
Resistor
I~
P111
P112
~,,~L
1
Over-Current
Compressor
Detection
Motor
Incase 01 air conditioner, Heater is changed to Fan Motor.
83·002605B
3-308
NEe
Figure 21.
JJPD7556/66
Rice Cooker Circuitry
2SA733
"-' AC
100 V
RD
10E
lEDx4
'--+---1-----'
RES
Plio
CINO
Comparator
Input
P90
Open Drain
Output
P91
lplll
Heater
for
Keeping
Warm
Heater
for
Cooking
-I P110
L - -_ _ _
~PD7566
~----IVREF
....--"w"......t------'VI/\r---1 P11l1 CMOS
P112
CMOS
Output
.-J'W..........~-------'V->Ar-_i P102 Output
.....-J\N.,.....,6----------..JVo,.I\r--! P103
.----------1 Cll
Input With P11
Pull· Down
Resistor P12
1 - - - - - - - 1 Cl2
83·002606B
3-309
~EC
JiPD7556/66
Figure 22.
Washing Machine Circuitry
2SA733
RES
P10:!
Open Drain
Input
P90
PB1
~
Pl00
Washing
Motor
Output
Plo,
CMOS
Output P110
Water
Water
Supply Drain
Magnet Magnet
Pl13
Piezo
?"
P10a
CMOS
Output
3-310
r~
PSt
pe2
POO jlnput With
Pull·Up
Resistor
Cl2
~
Open Drain
Output
po,
Cll
~
~PD7566
P10
Input With
Pull·Up
Resistor
P11
P12
P13
Key Input x 12
NEe
Figure 23.
fJPD7556/66
Tape Deck Controller Circuitry
P91
Motor
Planger
Driver
P100
P11l-t
P1l0-P1l2
Record
Pl13
Mute
P102
Music Select
P103
P80
~PD7566
Tape·End Detect
INTO
Open
Drain
Output
PIl-t
Voltage Detect
PB1
P82
P90
P13
Cll
Cl2
With
Pull· Up
Resistor
I~
P11
P12
Key x12
~
~
83·0026088
3-311
NEe
JAPD1556/66
Table 5 compares the features of products in this part of
the 7500 series devices.
Table 5.
Product Comparison
Item
Instruction
cycle / system
clock (5 V)
JJPD7554
RC
4 /As / 500 kHz
External
2.86 /As 1700 kHz
JJPD7564
f1PD7556
2.86 /As 1700 kHz
3/As I 660 kHz
Ceramic
f1PD7566
4/As/500kHz
3/As/660 kHz
Instruction set
47
47
45
45
1024x8
ROM
1024x8
1024x8
1024x8
RAM
64x4
64x4
64x4
64x4
I 10 port total
16 (max)
15
20 (max)
19
Port 0
POO-P01
POO-P01
Port 1
P1o-P13
P1o-P13
Port 8
P80-P82
P83/CL2
P80-P82
Port 9
P90-P91
P90-P91
Port 10
P10o-P103
P10o-P103
Port 11
P11o-P113
P11o-P113
8-bit
8-bit
Comparator
4-channel
4-channel
Process
CMOS
CMOS
CMOS
CMOS
Package
20-pin
plastic
shrink DIP
20-pin
plastic
shrink DIP
24-pin
plastic
shrink DIP
24-pin
plastic
shrink DIP
Timer I event counter
8-bit
8-bit
Serial interface
8-bit
8-bit
3-312
t-iEC
pPD75104/106/108
4-BIT, SINGLE-CHIP
CMOS MICROCOMPUTERS
NEe Electronics Inc.
Description
The pPD75104, pPD75106, and pPD75108 are highperformance single-chip CMOS microcomputers that
incorporate a CPU, ROM, RAM, I/O ports, vector
interrupt functions, serial interface, and timer/event
counters.
The devices can manipulate data in 1-,4-, or 8-bit units.
A variety of bit manipulation instructions enhance I/O
data control. The devices are especially suitable for
controlling VCRs, audio sets, touch-tone telephones, and
printers.
Features
o 46 instructions
o
o
o
o
o
o
- Bit manipulation instructions
- 8-bit data transfer, comparison, and increment!
decrement instructions
- 1-byte relative branch instructions
- GETI instruction that realizes 2- or 3-byte
instructions in 1-byte units
I nstruction cycles
- High-speed cycle: 0.95 ps/4.19 MHz, VDD = 5 V
- Low-voltage cycle: 1.91 ps/4.19 MHz, 15.3 ps/
4.19 MHz
Program memory (ROM)
- pPD75104: 4096 x 8 bits
- pPD75106: 6016 x 8 bits
- pPD75108: 8064 x 8 bits
Data memory (RAM)
- pPD75104: 320 x 4 bits
- pPD75106: 320 x 4 bits
- pPD75108: 512 x 4 bits
Bit manipulation memory (bit-sequential buffer):
16 bits
Four banks of 8 x 4-bit general purpose registers
Accumulators
- Bit accumulator (CY)
- 4-bit accumulator (A)
- 8-bit accumulator (XA)
058 I/O lines
- High-current output ports that can directly drive
LEDs (total of 200 rnA for 32 pins)
- 12 N-channel, open-drain outputs with 12 V
maximum
- Four programmable threshold comparator
inputs
- Two external event inputs
o Vectored interrupt function capable of multiple
interrupts
- Three external vectored interrupts
- Two external test inputs
- Four internal vectored interrupts
o Two 8-bit timer/event counters
o 8-bit serial interface
- Data transfer can start with LSB or MSB
- Two transfer modes (transmit/receive and
receive-on Iy)
- Mask option power-on reset circuit
- Crystal or ceramic oscillator
- Standby modes (STOP/HALT)
- CMOS technology
- Low power consumption
Ordering Information
Part Number
ROM (Bytes)
pPD75104CW
4096
Package Type
64-pin plastic shrink DIP
pPD75106CW
6016
64-pin plastic shrink DIP
pPD75108CW
8064
64-pin plastic shrink DIP
pPD75104G-1B
4096
64-pin plastic miniflat
pPD75106G-1 B
6016
64-pin plastic miniflat
pPD75108G-1 B
8064
64-pin plastic miniflat
3-313
NEe
pPD75104/106/108
Pin Configurations
64-Pln Shrink DIP
64-Pln Minif/at
... ...
P13/INT3
vss
P12/INT2
P90
P11/INT1
P91
P1o/INTO
P92
P41
PTH03
P93
P40
PTH02
P80
PS3
N
'"
0.
0.
o
~M~~gO :!
Z 0.
0.
...
0.
0.
0.
10
U>
,.... ('II ('II) 0
~ ~ ~ ~
>
0.
co
:ll
'"
0.
0.
0.
N
'"
0
51
P131
P 132
P133
PTH01
P81
PS2
PTHOO
P82
PS1
TlO
P 121
P83
PSo
P122
TI1
P70
RESET
X2
48
45
P120
P123
P23
P71
P22/PCL
P72
X1
P21/PT01
P73
P63
P2o/PTOO
P60
P62
P03/SI
P03/S 1
P61
P61
P2o/PTOO
P02/S0
P62
P60
39
P21/PT01
P73
P22/PCL
P72
36
P 23
TI1
P01/SCK
P63
POo/INT4
X1
P123
X2
P71
P122
RESET
P70
P121
PSo
P83
P120
PS1
P82
P133
PS2
P132
PS3
P131
P 40
P130
P41
P143
P42
P142
P43
P141
P30
P140
P31
NC
P32
voo
P33
POo/INT4
P01/SCi<
42
Il P D5104/106/108
13
16
P02/S0
TIO
PTHOO
19
0
N
,....
00
0.
:E:
'"
N
0
co
0.
(I')
0)
0.
('II
CD
0.
en
,....
en
0.
0
CD
0.
U)
UJ
>
N
PTH01
~
~ ~ ~ S S
Z Z Z z :z: :z:
I0.
~~?~t:
0. 0. 0. 0.
C')
I-
83-003930B
83-002742B
Pin Identification
Symbol
Function
P13/1NT3
P12/1NT2
P11/1NT1
P10/lNTO
4-bit input port 1/ Edge-triggered vectored
interrupts
PTH03PTHOO
Programmable threshold comparator analog
input port
Symbol
P143-P140
Function
4-bit I/O port 14
NC
No connection
VDD
Positive power supply
P33-P30
Programmable 4-bit I/O por.t 3
P43-P40
4-bit I/O port 4
P53-P50
4-bit I/O port 5
RESET
Reset input
X2, X1
Ceramic or crystal system clock oscillator
TlO, TI1
External event input for timer/event counter
P23, P22/PCL
P21/PT01,
P20/PTOO
4-bit I/O port 2/Clock output terminallTimer / .
event counter output pins
P03/S1
4-bit input port O/Serial interface/Edge-triggered
vectored interrupt
P63-P60
Programmable 4-bit I/O port 6
P73-P70
4-bit I/O port 7
P83-P80
4-bit I/O port 8
P123-P120
4-bit I/O port 12
P93-P90
4-bit I/O port 9
P133-P130
4-bit I/O port 13
Vss
Ground
P02/~
P01/SCK
POo/INT4
3-314
I
II
NEe
pPD75104/106/108
Pin Functions
P83-P80 [Port 8]
P0 3/SI, P02/S0, P01/SCK, POo/INT4 [Port 0, Serial
4-bit I/O port for directly driving LEOs. The port is in
the input state at reset and has a-bit lID capability
when paired with port 9.
110, Interrupt 4]
Port 0 can be configured as a 4-bit parallel input
port or as the serial lID interface under control of the
serial mode select register. The serial input SI (active
high). serial output SO (active low). and the serial clock
SCK (active low synchronizes data transfer) make-up
the serial I/O interface. INT4 is an edge-triggered
vectored interrupt triggered by a rising or falling edge.
The port is in the input state at reset.
P13-P1o/INT3-INTO [Port 1, Interrupts 3-0]
Port 1 is a 4-bit input port. INTO and INT1 are edgetriggered vectored interrupts selected by a rising or
falling edge. INT2 and INT3 are triggered by a rising
edge only. The port and the interrupts are in the input
state at reset.
P93-P90 [Port 9]
4-bit I/O port for directly driving lEDs. The port is in
the input state at reset and has a-bit lID capability
when paired with port 8.
P123-P120 [Port 12]
4-bit I/O port. N-channel open-drain. 12 V max. An
internal pull-up resistor is a mask option. The port is in
the high-impedance state at reset when open-drain is
selected or in the high-level state when a pull-up
resistor is selected. Port 12 has 8-bit 1/0 capability
when paired with port 13.
P133-P130 [Port 13]
P23, P22/PCL, P21/PT01, P2o/PTOO [Port 2, Clock
Output, Timer/Event Counter Output]
Port 2 is a 4-bit I/O port for directly driving LEOs. PT01
and PTOO are the timerlevent counter output pins. PCl
is the clock output pin. These pins are in the input state
at reset.
4-bit lID port. N-channel open-drain. 12 V max. An
internal pull-up resistor is a mask option. The port is in
the high-impedance state at reset when open-drain is
selected or in the high-level state when a pull-up
resistor is selected. Port 13 has a-bit I/O capability
when paired with port 12.
P33-P30 [Port 3]
P143-P140 [Port 14]
Programmable 4-bit lID port for directly driving LEOs
with bit-level 110 selection. The port is in the input state
at reset.
4-bit lID port. N-channel open-drain 12 V max. An
internal pull-up resistor is a mask option. The port is in
the high-impedance state at reset when open-drain is
selected or in the high-level state when a pull-up
resistor is selected.
P43-P40 [Port 4]
4-bit 1/0 port for directly driving LEOs. The port is in
the input state at reset and has 8-bit I/O capability
when paired with port 5.
PTH03-PTHOO [Threshold Detector Analog Input
Port]
Threshold detector analog input port.
P53-P50 [Port 5]
4-bit 1/0 port for directly driving lEDs. The port is in
the input state at reset and has 8-bit lID capability
when paired with port 4.
TIO, TI1 [Timer/Event Counter Input]
External event input for the timerlevent counter. These
two pins are also an edge-triggered vectored interrupt
and a 1-bit input port.
P63-P60 [Port 6]
Programmable 4-bit lID port for directly driving LEOs
with bit-level I/O selection. The port is in the input state
at reset and has 8-bit lID capability when paired with
port 7.
P73-P70 [Port 7]
4-bit lID port for directly driving LEOs. The port is in
the input state at reset and has 8-bit lID capability
when paired with port 6.
RESET [Reset]
System reset input pin (active low).
X2, X1 [System Clock I/O]
These pins are the system clock I/O. The clock may be
from an external source or from an internal oscillator
controlled by a crystal or ceramic resonator connected
to pins X2 and X1. See figure 1.
3-315
NEe
pPD75104/106/108
Figure 1.
Voo [Power Supply]
System Clock Configurations
Positive power supply.
A. Ceramic Oscillator
Vss [Ground]
System ground.
X1
X2
pPD7500 Series
Table 1 compares the features of similar products in
the pPD75000 series.
30 PF
l 3 0 PF
J
1/0 Port Interfaces
Figure 2 shows the internal circuit configurations at the
I/O ports.
B. Crystal Oscillator
X1
IOPF
X2
lS20 PF
l
C. External Clock
pPD74HCOO
Clock
83-002753A
Table 1.
Product Comparison
Item
pPD75Pl08
pPD75104
pPD75106
pPD75108
Program memory
EPROM
0000-1FFFH
Mask ROM
OOOO-OFFFH
Mask ROM
0000-177FH
Mask ROM
0000-1FFFH
Data memory
512 x 4-bit
Bank 0: 256
Bank 1: 256
320 x 4-bit
Bank 0: 256
Bank 1: 64
320 x 4-bit
Bank 0: 256
Bank 1: 64
512 x 4-bit
Bank 0: 256
Bank 1: 256
Instruction set
Set P108
Set P108 minus
BR!addr (3-byte instr.)
Set P108
Set P108
Ports 12-14 pull-up
resistor
Not offered
Mask option
Mask option
Mask option
Power-on reset
Integrated
Mask option
Mask option
Mask option
Power-on flag
Integrated
Mask option
Mask option
Mask option
Operating voltage
5 V±10%
2.5 to 6.0 V
2.5 to 6.0 V
2.5 to 6.0 V
Pin 31
Vpp
NC
NC
NC
Packaging
64-pin ceramic
shrink DIP
64-pin plastic
miniflat or shrink DIP
64-pin plastic
miniflat or shrink DIP
64-pin plastic
miniflat or shrink DIP
3-316
NEe
Figure 2.
pPD75104/106/108
Interface at Input/Output Ports
Type F
P01/SCK
Type A
Voo
Voo
Data~
~'"'"'
Inpull
Output
Output
Disable
Vss
Vss
Type B
P13-P10/INT3·INTO, TlO, T11, POO/INT4, P03/SI, RESET
Type M
P123-P120, P133-P130, P143-P140
~'"'"'
V?D
<
Pull up Resistor
[Mask Option] ~
~-~-o ~n.!:~~t
Data~
Type D
outputJ
Disable
-
I
Voo
P·ch
oata~
Inpul Buffer
Output
outPut~
Type N
PTH03-PTH09
Disable
Vss
Comparator
Type E
P23, P22/PCL, P21 IPT01, P20/PTOO. P02/S0, P33-P30,
P43-P40, P53-P50, P60, P73-P70, P83-P80, P93-P90
Voo
'"~
VREF [Threshold Vollage]
Data~
Inpull
Output
Output
Disable
N.ch
Voo
l
Vss
Vss
3-317
NEe
pPD75104/106/108.
Figure 3.
Cycle Time
Supply Voltage
VB
I
\
1\
\
1
0.5
o
1\
3
VOO IV]
Block Diagram
POO-P03
P10-P13
P20-P23
PTOO/P20
P30-P33
TI1
PT01/P21
SI/P03
SO/P02
SCK/P01
P40-P43
ROM
Program
Memory
Decode
and
Control
IlPD75104: 4096 x B
IlPD75106: 6016 x B
P50-P53
RAM
Data Memory
P60-P63
IlPD75104/106: 320
x4
IlPD7510B: 512 x 4
PPD7510B: 8064 x B
P70-P73
INTO/P1 0
INT1/P11
INT2/P12
INT3/P13
INT4/POo
PBO-PB3
P90-P93
CPU Clock
PTHOO-PTH03 4
'"
PCL/P22
Xl
X2
1 1 1
Voo
Vss
RESET
83·0027438
3-318
t-lEC
pPD75104/106/108
Absolute Maximum Ratings
Capacitance
(Preliminary Specifications)
TA = 25°C, Voo = GND = 0 V, f = 1 MHz
TA = 25°C
Limits
Operating temperature, TOPT
Parameter
Symbol
Min Typ Max
Unit
Test
Conditions
Storage temperature, TSTG
-65 to +150°C
Input capacitance
CI
15
Power supply voltage, Voo
-0.3 to +7.0 V
Output capacitance
Co
15
pF Unmeasured pins
returned to GND
pF
I/O capacitance
Cia
15
pF
Input voltage
Ports 12, 13, 14 (1), VI2
Other ports VI1
-0.3 to +13 V
-0.3 to Voo + 0.3 V
Output voltage, Va
-0.3 to Voo + 0.3 V
Output current, high
One pin
All output pins, total
Output current, low
Single pin (peak value)
Ports 0, 2-4, 12-14, total (peak value)
Ports 5-9, total (peak value)
Power dissipation, Po (TA = 70°C)
-15mA
-30 rnA
30 rnA
(2) 15 rnA
100 rnA
(2) 60 rnA
100 rnA
(2) 60 rnA
480 mW
Note:
(1) No internal pull-up resistor (mask option). If internal pull up
resistor is used, then voltages are same as V11'
(2) The calculation method is: value = peak value x duty.
Comment: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
3-319
NEe
pPD75104/106/108
DC Characteristics
= -40 to +85°C, Voo = 2.7 to 6.0 V, GND = 0 V
TA
Limits
Parameter
Symbol
Input high voltage except
Xl, X2, TIO, T11, ports 0,1,12-14,
and RESET
VIH1
Input high voltage, ports
0,1, TIO, T11, and RESET
Min
Typ
Test
Conditions
Max
Unit
0.7 Voo
Voo
V
VIH2
0.8 Voo
Voo
V
Input high voltage, ports
12-14
VIH3
0.7 Voo
12
V
Input high voltage X1, X2
VIH4
Voo - 0.5
Voo
V
Input low voltage except
Xl, X2, TlO, T11, ports 0,1,
and RESET
VIL1
0
0.3 Voo
V
Input low voltage ports
0,1, TIO, Tl1, and REm
VIL2
0
0.2
V
Input low voltage X1, X2
VIL3
0
0.4
V
Input leakage current high,
except X1, X2
IUH1
3
J.lA
VI = Voo
Input leakage current high,
X1,X2
IUH2
20
J.lA
VI = Voo
Input leakage current low,
except X1, X2
IUL1
-3
J.lA
VI =OV
Input leakage current low,
X1,X2
IUL2
-20
J.lA
VI =OV
Output voltage, high
VOH
V
10H = -100J.lA
Output voltage, low
Ports 0,2-9
Ports 12-14
VOL
2.0
V
Voo = 4.5 to 6.0 V
10L = 15 mA
10L = 10 mA
Output voltage, low
VOL
0.4
V
Voo = 4.5 to 6.0 V;
10L = -1.6 mA
Output leakage current, high
ILOH
V
Voo -1.0
Voo - 0.5
0.5
V
3
J.lA
-3
(Note 1)
Voo = 4.5 to 6.0 V;
10H = -1 mA
10H = 400J.lA
Vo = VOO
Output leakage current, low
ILOL
J.lA
VO=OV
Supply current
1001
3.5
mA
Voo = 5 V + 10% (Note 2,3,4)
0.9
mA
Voo = 3 V + 10% (Note 2, 3, 5)
Supply current HALT mode
1002
600
J.lA
VOO = 5 V + 10% (Note 2, 3, 5)
150
J.lA
Voo = 3 V + 10% (Note 2, 3, 5)
(Note 2)
Supply current, STOP mode
1003
Pull-up resistance, ports 12-14
RL
15
0.1
10
J.lA
35
55
kn
Notes:
(1) No internal pull-up resistor. If an internal pullr·up resistor is used, then same as V11. If an input voltage greater than 10V is supplied to port
12,13, or 14, the pull-up resistor must be> 50 kO.
(2) Does not account for current drawn through the mask option pull-up resistor, the mask option power-on reset circuit, or the comparator
circuit.
(3) 4.19-MHz crystal oscillation; C1 = C2 = 10 pF.
(4) Set PCC to 00118 for high-speed operation.
(5) Set PCC to 00008 for low-!;oeed ooeration.
3-320
NEe
pPD75104/106/108
Crystal Characteristics
TA = -40 to +85°C; Voo = 2.7 to 6.0 V
limits
Type
Parameter
Ceramic Frequency (fXX)
oscillator
Oscillation
2.0
Stabilization (1)
Crystal
Frequency (fXX)
oscillator
Oscillation
Input frequency
5.0 MHz
4
ms
20
ms
Voo = 4.5 to 6.0 V
2.0 4.19 5.0 MHz
Stabilization (1)
External
clock
Test
Conditions
Min Typ Max Unit
2.0
Highllow level
100
duration (txH. txL)
5
ms
25
ms
Voo = 4.5 to 6.0 V
5.0 MHz
250
ns
Note:
(1) Time required for oscillator to stabilize after power-on or release
of STOP mode.
II
AC Characteristics
= 2.7 to 6.0 V. GND = 0 v
TA = -40 to +85°C. Voo
Limits
Parameter
Symbol
Cycle time (Note 1)
tCY
TI input frequency
fTI
Min
Typ
Max
Unit
0.95
32
jJS
3.85
32
jJS
0
1
MHz
0
550
kHz
TI high time
tTIH
0.48
jJS
Tllow time
tTIL
1.8
jJS
SCK cycle time
tKCY
SCK pulse width
SI setup time to SCK high
tSIK
SI hold time from SCK high
INTO pulse width
Voo = 4.5 to 6.0 V
Voo = 4.5 to 6.0 V
Input; Voo = 4.5 to 6.0 V
0.8
jJS
jJS
Output; Voo = 4.5 to 6.0 V
3.2
jJS
Input
3.8
jJS
Output
0.4
jJS
Input; Voo = 4.5 to 6.0 V
(tKCy/2) - 50
ns
Output; Voo = 4.5 to 6.0 V
1.6
jJS
Input
(tKCY 12) - 50
ns
Output
100
ns
ns
500
tINTH. tlNTL
Voo = 4.5 to 6.0 V
0.95
SCK low to SO valid delay time
RESET pulse width
Test
Conditions
300
ns
1000
ns
5
jJS
5
jJS
Voo = 4.5 to 6.0 V
Note:
(1) Cycle time depends on the supply voltage as shown in figure 3.
3-321
NEe
pPD75104/106/108
Power-On Reset Characteristics (Mask
Option)
Data Memory STOP Mode Low Supply
Voltage Data Retention Characteristics
TA
TA
= -40 to +85°C
limits
Parameter
Symbol
Min Typ Max
Unit
0.5
Power-on reset circuit
operation voltage
Power-on reset circuit
operation voltage rise
time
10
Power-on reset circuit
consumption current
30
100
Test
Conditions
= -40 to +85°C
Limits
Parameter
Symbol
Min
V
Data retention
supply voltage
VOOOR
2.0
ps
Data retention
supply current
IOOOR
Release signal
set time
tSREL
pA
Oscillation
tWAIT
stable wait time
Typ
0.1
Max
Unit
6.0
V
10
pA
0
= -40 to +85°C, Voo = 4.5 to 6.0 V
limits
Parameter
Symbol
Min Typ Max
Unit
±100
mV
V
Comparision accuracy VACOMP
Threshold voltage
VTH
0
VOO
PTH input voltage
0
VOO
VIPTH
Comparator
consumption current
Test
Conditions
V
rnA Set PTHM7
to 1
Table 2.
Oscillation Stable Walt Times
BTM3
BTM2
BTMI
BTMO
o
o
0
0
WaltTlme "xx = 4.19 MHzJ
220 /fxx (approx 250 ms)
217/fXX (approx 31.3 ms)
o
215 /fXX (approx 7.82 ms)
213 /fXX (approx 1.95 ms)
3-322
VDOOR = 2.0 V
ps
217 /fX
ms
When released
by RESET
(Note 1)
See table 2.
ms
When released
by interrupt
request
Comparator Characteristics
TA
Test
Conditions
Note:
(1)
During oscillation stable wait time, CPU operation must be
stopped to avoid unstable operation upon oscillation start.
NEe
pPD75104/106/108
Timing Waveforms
Clock Timing
Timing Measurement POints
(Except Ports 0, 1, TI1, X1, X2, RESET)
O.7VDD~
--V0.7VDD
~~O_.3_V~D~D_________________O_.3~VD~D~
XI Input
83-oo3411A
83-oo2756A
TI Timing
Serial Interface Timing
83-oo2757A
Interrupt Input Timing
SI
---i---------(]
Output Data
SC
INTO-INT4
83-oo275&A
83-oo2759A
Reset Input Timing
Data Retention Timing
(STOP Mode is Released by RESET)
("~J
RESET
HALT Mode
0.2 VOO
Internal Reset Operation
~SToPMode
Operation
Mode
83-oo276oA
~~Data Retention Mode
t
VOO
STOP
Instruction
Execution
Data Retention Timing
(STOP Mode is Released by Interrupt Request)
VOODR
J - - - - - - S T O P MOde _ _ _ _-+J.ot---3-_-I+--~~~~ation
Data Retention Mode
83-002761 A
VOD
VOOOR
Standby Release Signal
[Interrupt Request]
83-oo2762A
3-323
pPD75104/106/108
3-324
NEe
NEe
NEe Electronics Inc.
pPD75P108
4-BIT, SINGLE.CHIP
CMOS MICROCOMPUTER
WITH ON-CHIP EPROM
PRELIMINARY INFORMATION
Description
The jJPD75P108 is a high-performance, single-chip
CMOS microcomputer that incorporates a CPU, ROM,
RAM, I/O ports, vector interrupt functions, serial interface, and timer/event counters.
The device is functionally equivalent and pin-compatible with the jJPD75104/pPD75106/jJPD75108. The
EPROM in thejJPD75P108 allows you to evaluate your
program before placing the mask order. An OTP ROM
version is available for small production runs.
Features
o
o
o
o
o
o
o
o
46 instructions
- Bit manipulation instructions
'~ 8-bit data transfer,comparison, and increment/
decrement instructions
- 1-byte relative branch instructions
- GETI instruction that realizes 2-or 3-byte
instructions in 1-byte units
Instruction cycles
- High-speed cycle: 0.95 jJs/4.19 MHz, VDD = 5 V
- Low-voltage cycle: 1.91 jJs/4.19 MHz, 15.3 jJs/4.19
MHz
'
Program memory (EPROM): 8192 x 8 bits
Data memory (RAM): 512 x 4 bits
Bit manipulation memory (bit-sequential buffer):
16 bits
Four banks of 8 x 4-:-bit general-purpose registers
Accumulators
- Bit accumulator (CY)
- 4-Bit accumulator (A)
- 8-Bit accumulator (XA)
58 I/O lines
- High-current output ports that can directly
drive LEOs (total of 200 mAfor 32 pins)
- 12 N-channelopen-drain outputs with 12 V
maximum
- Four programmable comparator threshold inputs
- Two external event inputs
o Vectored
o
o
interrupt function capable of multiple
interrupts
- Three external vectored interrupts
- Two external test inputs
- Four internal vectored interrupts
Two 8-bit timer/event counters
8-bit serial interface
- Data transfer can start with LSB or MSB
- Two transfer modes (transmit/receive and
receive-only)
o
o
o
o
o
Power-on reset circuit
Crystal or ceramic oscillator
Standby modes (STOP/HALT)
CMOS technology
Low power consumption
Ordering Information
Part Number
Package Type
ROM (8K x 81
pPD75P108DW
64-pin shrink cerdip
with window
pPD75P108CW
64-pin plastic shrink DIP
OTP ROM
pPD75P108G-1 B
64-pin plastic miniflat
OTP ROM
EPROM
Pin Configurations
64-Pin Ceramic Shrink DIP or
Shrink Cerdip with Window
P13/1NT3
Vss
P12/1NT2
P90
P11IINT1
P9l
Plo/lNTO
P92
PTH03
P93
PTH02
P80
PTHOl
P8l
PTHOO
P82
TIO
P83
TI1
P70
P 23
P7l
P22/PCL
P72
P2l/PTOl
P73
P2o/PTOO
P03/S1
P6l
P02/S0
P62
P01/SCK
P63
POolINT4
P1 23
X2
P122
RESET
P12l
P50
P1 20
P5l
P1 33
P132
P13l
P40
P1 30
P4l
P1 43
P42
P142
P43
P14l
P30/MDO
P1 40
P3l/MDl
Vpp
P32/MD2
Voo
P33/MD3
83·0027639
3-325
NEe
pPD75P108
Pin Configurations (cont)
Symbol
64-Pln Plastic Min/fiat
Q
Q
.,..
Q
('\rI
Q
M
Q
~~~~~~g8:~i;£'~
> >
~
~
~
~
P40
~
~
~
;;;
~
~
'"III
~.
~
~
.P5l
P53-PSo
4-bit 1/0 port 5
RESET
Reset input
X2,X1
Ceramic or crystal system clock oscillator
P63-P60
Programmable 4-bit 110 port 6
4-bit 1/0 port 7
P133
P83-P80
4-bit 1/0 port 8
P120
P93-P90
4-bit 1/0 port 9
VSS
Ground
P132
0
P53
4-bit 1/0 port 4
PlJ- P7o
~
III
III
P12l
P122
P50
Function
P43-P40
P123
POoIINT4
X2
Xl
P01/SCK
IJPD75P108
P02/S0
P62
P03/S1
P6l
P20/PTOO
P73
P22/PCL
P72
P 23
Til
P 70
TID
PTHOO
P83
PTHOl
'"N
0
N
~
~
=
0
M
~
N
~.
en
'"
~
0
~
0
0
'"
N
N
~
N
M
~
N
~
.,..
~
~~~~~>~~~
~
~
'"
...
J:
I~
POo/lNT4, P01/SCK, P02/SO, P03/S1 [Port 0,
Interrupt, Serial Clock, Serial Interface]
This port can be configured as a 4-bit parallel input
port or as the serial liD interface under control of the
serial mode select register. The serial input 81, serial
output SO, and the serial clock SCK make up the
serial 110 interface. INT4 isan edge-triggered vectored
interrupt triggered by a rising or falling edge. The port
is in the input state at reset.
0N
J:
I-
~
~
83-003931A
Pin Identification
Symbol
Pin Functions
Function
P13/1NT3, P12/1NT2, P11/1NT1, P1o/iNTO [Port 1,
Edge-Triggered Interrupts]
4-bit input port 1/interrupts. INTO and INT1 are edgetriggered vectored interrupts selected by a rising or
falling edge. INT2 and INT3 are triggered by a rising
edge only. The port and the interrupts are in the input
state at reset.
P1311NT3
P1211NT2
P1111NT1
P10llNTO
4-bit input port 1lEdge-triggered vectored
interrupts
PTH03-PTHOO
Programmable threshold comparator analog input
port
TIO, TI1
External event input for timerlevent counter
P23, P22/PCL
P21/PT01
P20/PTOO
4-bit 1/0 port 2/Clock output terminal/Timerl
event counter output pins
P03/S1
4-bit input port O/Serial interface/Edgetriggered vectored interrupt
P33/M03, P32/MD2, P31/MD1, P30/MOO [Port 3,
EPROM Function Mode Inputs]
4-bit 110 port 12
Programmable 4-bit liD port for directly driving LEOs
with bit-level 110 selection. MOO-M03 selectthe EPROM
operating mode. The port is in the input state at reset.
P02/§!L
P01/SCK
POoII NT4
4-bit 1/0 port 13
P14J- P14o
4-bit 1/0 port 14
Vpp
EPROM programming power supply
Voo
Positive power supply
P33/MD3
P32/MD2
P31/MD1
P30/MDO
Programmable 4-bit 1/0 port 3/EPROM function
mode selection inputs
3-326
P23, P22/PCL, P21/PT01, P2o/PTOO [Port 2, Clock
Output, Timer/Event Counter Output]
Port 2 is a 4-bit liD port for directly driving LEOs. PT01
and PTOO are the timerlevent counter output pins. PCl
is the clock output pin. These pins are in the input state
at reset.
P43-P40 [Port 4]
4-bit liD port for directly driving LEOs. The port is in
the input state at reset and has 8-bit liD capability
when paired with port 5.
NEe
JlPD75P108
Pin Functions (cont)
RESET [Reset]
P53-P50 [Port 5]
System reset input pin (active low).
4-bit 110 port for directly driving LEOs. The port is in
the input state at reset and has 8-bit I/O capability
when paired with port 4.
P63-P60 [Port 6]
X2, X1 [System Clock 1/0]
These pins are the system clock I/O. The clock may be
ceramic or crystal.
Voo [Power Supply]
Programmable 4-bit 110 port for directly driving LEOs
with bit-level I/O selection. The port is in the input state
at reset and has 8-bit I/O capability when paired with
port 7.
Vpp [EPROM Programming Power Supply]
P7 3-P70 [Port 7]
Ouring normal operation, connect to VDD . Connect to
+21 V for EPROM programming.
4-bit 110 port for directly driving LEOs. The port is in
the input state at reset and has 8-bit 110 capability
when paired with port 6.
Vss [Ground]
Positive power supply.
System ground.
P83-P80 [Port 8]
4-bit 110 port for directly driving LEOs. The port is in
the input state at reset and has 8-bit I/O capability
when paired with port 9.
P93-P90 [Port 9]
4-bit 110 port for directly driving LEOs. The port is in
the input state at reset and has 8-bit 110 capability
when paired with port 8.
P123-P120 [Port 12]
4-bit I/O port, N-channel, open-drain (12 V max). The
port is in the high-impedance state at reset and has
8-bit I/O capability when paired with port 13.
P133-P130 [Port 13]
4-bit 110 port, N-channel, open-drain (12 V max). The
port is in the high-impedance state at reset and has
8-bit 110 capability when paired with port 12.
P143-P140 [Port 14]
4-bit 110 port, N-channel, open-drain (12 V max). The
port is in the high-impedance state at reset.
PTH03-PTHOO [Threshold Detector Analog Input
Port]
Threshold detector analog input port.
TIO, TI1 [Timer/Event Counter Input]
External event input for the timer/event counter. These
two pins are also an edge-triggered vectored interrupt
and a 1-bit input port.
3-327
NEe
pPD75P108
Block Diagram
POO-P03
Pl0-P13
P20-P23
TIO
PTOO/P20
P30-P33
Til
P40-P43
PT01/P2l
EPROM
Program
Memory
8192 x 8
SI/P03
SO/P0 2
SCK/POl
Decode
and
Control
RAM
Data Memory
512 x 4
P60-P63
P70-P73
INTO/P10
INT1/Pll
INT2/P1 2
INT3/P13
INT4/POo
P80-P83
P90-P93
P120-P123
CPU Clock
P130-P133
'"
Xl
PCL/P22
X2
1 1 1
Voo
Vss
P140-P143
RESET
83-002764C
pPD75000 Series
Table 1 compares the features of similar products in
the pPD75000 series.
Table 1.
Product Comparison
Item
pPD75Pl08
pPD75104
pPD75106
pPD75108
Program memory
EPROM
0000-1FFFH
Mask ROM
OOOO-OFFFH
Mask ROM
0000-177FH
Mask ROM
0000-1FFFH
Data memory
512 x 4-bit
Bank 0: 256
Bank 1: 256
320 x 4-bit
Bank 0: 256
Bank 1: 64
320 x 4-bit
Bank 0: 256
Bank 1: 64
512 x 4-bit
Bank 0: 256
Bank 1: 256
Instruction set
Set P108
Set P108 minus
BR!addr (3-byte instr.)
Set P108
Set P108
Ports 12-14 pull-up
resistor
Not offered
Mask option
Mask option
Mask option
Mask option
Power-on reset
Integrated
Mask option
Mask option
Power-on flag
Integrated
Mask option
Mask option
Mask option
Operating voltage
5 V ±10%
2.5 to 6.0 V
2.5 to 6.0 V
2.5 to 6.0V
Pin 31
Vpp
NC
NC
NC
Packaging
64-pin ceramic
shrink DIP or
plastic miniflat
64-pin plastic
miniflat Oi shrink DIP
64-pin plastic
miniflat or shrink D!P
64-pin plastic
minif!at or shrink D!P
3-328
NEe
pPD75P108
Figure 1.
EPROM Programming
EPROM Programming Flowchart
The internal 8K-byte EPROM is programmed via the
pins and functions listed in table 2. Refer to the
flowchart, figure 1.
The Vpp and Voo pins must be held at 5 V for at least 10
ps upon power-up and before the programming voltages
of 21 V to Vpp and 6 V to Voo are applied.
Mode pins MDo-MD3 control the programming stepsas
shown in table 3. Address inputs are not used during
programming. The program memory address is first
cleared via the mode pins, then incremented by applying
four clock pulses to the X1 input.
Table 2.
EPROM Access
Pin
Function
Vpp
Programming voltage. Connect to 21 V when programming
EPROM.
X1, X2
Address increment clock input. X2 inputs the inverse of
X1.
MDO-MD3
Mode selection
P40-P43
8-bit data bus connection, low
P50-P53
8-bit data bus connection, high
VDD
Connect to 6 V during programming.
Table 3.
IE
No
EPROM Mode Selection
vpp = 21 V, VD D = 6.0 V
MOO
MOl
H
M02
M03
Operating Mode
Program memory address
clear
H
H
H
H
Program memory write
L
L
H
H
Program verify
H
X
H
H
Program inhibit
I/O Port I nlerfaces
Figure 2 shows the internal circuit configurations at the
1/0 ports.
3-329
NEe
pPD75P108
Figure 2.
Interface at Input/Output Ports
TypeB
P13/INT3, P10/INTO,
TIO, T11, POO/INT4, P03/SI, RESET
TypeE
P23, P22/PCL, P21/PT01, P20/PTOO, P02/S0,
P33/M D3-P30/M DO, P43-P40, PS3-PSO, P63-P60,
P73-P70, P83-P80, P93-P90
Voo
Data~
Inputl
Output
Output
Disable
Noch
Voo
Vss
Vss
Voo
Data~
Inputl
Output
Output
Olsable
TypeM
P123-P120, P133-P130, P143-P140
V?D
Pull-up Resistor ~
[Mask Option] ~
InlOut
oata~ffN_Ch
outputJ
Disable
-
I
./1
~_I
Input Buller
3-330
~I
NEe
a-BIT, SINGLE-CHIP MICROCOMPUTERS
4-1
E
a-BIT, SINGLE-CHIP MICROCOMPUTERS
NEe
Section 4 - a-Bit, Single-Chip Microcomputers
JlPD7SC05A/06A
JlPD7S07/0S/09
JlPD7SP09
JlPD7S10/11
JlPD7SC10/C11/C14
JlPD7S10H/11 H
JlPD7SPG11
JlPD7S310/312
JlPDS035HLl4SH
JlPDSOC35/C4S,
JlPD4S
JlPDS039HL/49H,
JlPDS749H
JlPDSOC39H/49H,
·JlPD49H
JlPDSOC40H/50H,
JlPD50H
JlPDS041AH,
JlPDS741A
JlPDSOC42
JlPDS74SH
4-2
High-End CMOS Microcomputers ...................... 4-3
High-End NMOS Microcomputers with
Comparator and SK ROM ........................... 4-23
High-End NMOS Microcomputer with
Comparator and SK EPROM ........................ 4-51
NMOS Microcomputers with AID Converter ............ 4-75
CMOS Microcomputers with AID Converter ........... 4-101
NMOS Microcomputers with AID Converter ........... 4-129
High-End NMOS Microcomputer with Piggyback
EPROM .......................................... 4-155
CMOS Microcomputers, Real-Time Control Oriented .. 4-175
High-Speed HMOS Microcomputers .................. 4-201
CMOS Microcomputers .............................. 4-213
High-Speed HMOS Microcomputers .................. 4-235
High-Speed CMOS Microcomputers .................. 4-249
High-Speed CMOS Microcomputers .................. 4-271
NMOS Microcomputers with Universal PPI ............ 4-293
CMOS Microcomputer with Universal PPI ............. 4-307
High-Speed NMOS Microcomputer with UV EPROM ... 4-325
NEe
NEe Electronics Inc.
Description
The pPD78COSA and pPD78C06A are advanced
CMOS 8-bit general purpose, single-chip microcomputers intended for applications requiring 8-bit
microprocessor control and extremely low power
consumption. They are ideally suited for portable,
battery-powered/backed-up products. Subsets of the
pPD7801, the pPD78COSA/06A integrate an 8-bit ALU,
4K-byte ROM, 128-byte RAM, 46 I/O lines, an 8-bit
timer, and a serial I/O port on a single die. Expanded
system operation can easily be implemented using
industry standard peripheral and memory components. Total memory space can be increased to 64K
bytes.
The pPD78COSA/06A lend themselves well to lowpower, portable applications by featuring two powerdown modes to further conserve power when the
processor is not active. ThepPD78C06A is packaged in
a 64-pin plastic miniflat package. ThepPD78COSA is a
ROM-less version, packaged in a 64-pin QUIP, and
designed for prototype development and small volume
production.
Features
o CMOS silicon gate technology; +S V supply
o
o
o
o
o
o
o
o
o
o
o
o
Complete single-chip microcomputer
-8-bit ALU
-4K-byte ROM
-128-byte RAM
6.2S MHz
Low power consumption
46 I/O lines
Expansion capabilities
-60K-byte external memory address range
-8080A bus compatible
Serial I/O port
101 instructions with multiple address modes
Power-down modes
-Halt mode
-Stop mode
8-bit timer
Prioritized interrupt structure
-Two external
-One internal
On-Chip clock generator
ROM-less version available (78COSA)
pPD7SC05A/06A
HIGH-END, S-BIT, SINGLE-CHIP
CMOS MICROCOMPUTERS
Ordering Information
ParI Number
Package Type
pPD78C05AG-36
64-pin plastic QUIP
pPD78C06AG-12
54-pin plastic miniflat
Pin Configurations
64-Pin Plastic QUIP
AB1S
Vee
"'OUT
DB7
AB14
AB13
DB6
AB12
DBs
AB11
DB4
AB10
DB3
ABs
DB2
ABa
DB1
AB7
DBo
AB6
Ne
ABs
INT1
AB4
INTo
AB3
WAIT
AB2
M1
AB1
ViR
ABo
RD
PB7
PCs
PBs
PC4
PBs
PC3
PB4
PC2
PB3
PC1
PB2
PCo
PB1
REL
PBo
TO
PA7
SCK
PAs
SI
PAs
SO
PA4
RESET
PA3
X2
PA2
PA1
X1
Vss
I:
32
33
PAo
83-002770A
4-3
NEe
pPD78C05A/06A
Pin Configurations (cont)
Plastic QUIP (cont.)
No.
64-Pln Plastic Mlnlflat
Reset input
30,31
X2, X1
PE7
32
VSS
Ground potential
DB2
PEs
33-40
DBl
PEs
PAo-PA7
I/O port A, bits 0-7
DBO
PE4
41-48
PBO-PB7
I/O port B, bits 0-7
INTl
PE3
49-63
INTo
PE2
PEo-PE14 (78C06A)
ABo-AB14 (78C05A)
Address bus/output port E, bits 0-14
Address bus, bits 0-14
WAIT
PEl
WR
RD
PEo
64
Vee
Power supply
PCs
PBs
PB7
PC4
PBs
PC3
PB4
PC2
PB3
PCl
P B2
PCo
PB l
REL
PBo
TO
PA7
19
Plastic Mlnlflat
No.
No.
PAa
Function
Not connected
2-5
DB3-DBo
Bidirectional data bus, bits 3-0
6,7
INh INTo
Interrupt inputs 1 and 0
8
WAIT
Wait request input
9
WR
Write strobe output
10
RD
Read strobe output
11-16
PCs-PCo
Input port C
17
REL
STOP release input
18
TO
Timer output
19
SCK
Serial clock input/output
20
SI
Serial data input
Function
21
SO
Serial data output
Address bus/output port E, bit 15
Address bus, bit 15
22
RESET
Reset input
23,24
X2, X1
Crystal connections
25
Vss
IC (Vecl
Ground potential
26
27-34
Symbol
PE1S (78C06A)
AB1S(78C05A)
Symbol
NC
Plastic QUIP
14
Serial data output
RESET
PEa
Pi n Identification
12,13
SO
29
NC
83-002771 A
11
28
DB3
SCK
3-10
Function
Serial data input
Crystal connections
52
64
2
Symbol
SI
27
¢OUT
Clock output
DB7-DBo
Bidirectional data bus
NC
Not connected
INT1, INTo
Interrupt inputs 1 and 0
WAIT
Wait request input
Internally conected to Vee
PAo-PA7
I/O port A, bits 0-7
35-42
PBO-PB7
I/O port B, bits 0-7
43-57
PEo-PE14
Address bus/output port E,
bits 0-14
Vee
Power supply
15
M1
Machine cycle 1 output
16
WR
Write strobe output
58
17
RD
Read strobe output
59
PE1S
Address bus/output port E, bit 15
18-23
PCs-PCo
Input port C
60-63
DBr DB 4
Bidirectional data bus, bits 7-4
24
REL
STOP release input
64
¢OUT
Clock output
25
TO
Timer output
26
SCK
Serial clock input/output
4-4
NEe
pPD78C05A/06A
Pin Functions
SCK [Serial Clock]
DBo·DB7 [Data Bus]
The control clock for the serial data port is userprogrammable as an input or output.
The 8-bit bidirectional data bus transfers data between
the accumulator and external memory or memorymapped I/O.
INTo, INT1 [Interrupts 0 and 1]
INTo is a rising-edge-triggered external interrupt input.
INT1 is an active-high external interrupt input. Both
inputs must be held high for a least 2flS to be recognized
as valid.
SI [Serial Data Input]
The SI input loads into the serial register on the rising
edge of SCK.
SO [Serial Data Output]
On the falling edge of SCK, the serial register outputs
data to SO, most significant bit first.
WAIT [Wait Request]
RESET [Reset]
The WAIT input is used to interface with slow memories
or peripherals. WAIT is sampled at the end of machine
cycle T 2. If it is low, then the processor goes into a wait
state until WAIT returns high.
A low level on RESET input of more than 8 fls resets
the processor.
M1 [Machine Cycle 1]
(78C05A only) The M1 output is high during machine
cycles T1 through T3 of the first opcode fetch of an
instruction.
WR [Write Strobe]
When the WR output is low, valid output data is available
on the data bus.
RD [Read Strobe]
The processor loads data from the data bus into the
accumulator on the rising edge of the RD output.
X1, X2 [Crystal Connections]
These pins connect to the internal clock generator
circuit. If an external clock generator is used, then it is
connected to X1.
I:
Vss [Ground]
This is the power supply ground potential input.
IC [Vee]
(78C06A only) This is the internal connection to
Vee
through a high impedance. It should be left open.
PAO·PA7 [Port A]
The 6-bit input port has internal pull-up resistors.
When contents of the port buffer are transferred to the
accumulator, they fill the least significant six bits.
Port A is an 8-bit latched output port. Data can be
readily transferred between the accumulator and the
output latch buffers. The contents of the output latches
can be modified using arithmetic and logic instructions.
Data remains latched at port A unless it is acted on by
another port A instruction or a RESET is issued.
REL [STOP Release]
PBo·PB7 [Port B]
The STOP release input has an internal pull-down
resistor. High level on REL releases the processor from
stop mode, allowing the clock generator to restart.
Port B is an 8-bit I/O port. Data is latched at port B in
both the input and output modes. Each bit of port B can
be independently set to either input or output mode.
The mode B register programs the individual lines of
port B to be either an input (mode Bn = 1) or an output
(mode Bn = 0).
PCo·PCs [Port C]
TO [Timer Output]
Frequency of square wave output at TO is determined
by the timer register contents. TO outputs a low level
after reset.
4-5
pPD78C05A/06A
PEo-PE15 [Port E]
(78C06A only) Port E is a 16-bit address bus/output
port. It can be set to one of two operating modes using
the PER or PEX instruction.
• 16-bit address bus: the PER instructfon sets this
mode for use with external I/O or memory expansion
(up to 60K bytes, externally).
• 16-bit output port: the PEX instruction sets port E to
a 16-bit output port. The contents of Band C
registers appear· on PE8-PE15 and PEo-PE7,
respectively.
ABo-AB15 [Address Bus]
These lines are the 16-bit address bus to the main
memory. The 78C05A, having no internal ROM, must
address the area from 0 to 4096 as external ROM.
The 78C05A AB lines are unlike the 78C06A PE lines in
that they have no internal latches. When the Port E
output instruction PEX is executed in a 78C05A, the
register pair BC is output to the AB lines for only one
clock cycle during the third machine cycle. This is
provided to allow external hardware to emulate the
Port E operation of the 78C06A.
Vee [Power Supply]
This pin is the power supply input, 3.5 to 6.0 V during
normal operation.
cp OUT [Clock Output]
The system clock frequency, which is 1/4 or 1/8 of the
crystal frequency, is output on this pin. ¢ OUT is active
in halt mode but is held high in stop mode.
Block Diagram
OSC
Xl
16
latch
REl
INC/DEC
PC
Data
SP
B
Progl'llm
Memory
(4K-byte)
Memory
(128-Byte)
A
C
7BC06A
o
INTI
H
TO
SI
PCs-PC.
WR
M,
(fLPD78C05A)
4-6
WAIT
RESET
~Out
1 1
VCC
VSS
ttiEC
pPD78C05A/06A
Absolute Maximum Ratings
-0.3 to +7.0 V
Supply voltage, VCC
Input voltage, VI
-0.3 V to VCC + 0.3 V
Output voltage, Vo
-0.3 V to VCC + 0.3 V
Output high current, 10H (device total)
-5mA
Output low current, 10L (device total)
43.5 mA
Operating temperature, TOPR
-65 to +150 °C
Storage temperature, TSTG
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Capacitance
TA = +25°C; Vee = GND = 0 V
Limits
Parameter
Symbol
Min
Typ
Max
Unit
Input
capacitance
C,
15
pF
Output
capacitance
Co
15
pF
I/O
capacitance
CliO
15
pF
Test
Conditions
fc = 1 MHz;
unmeasured
pins returned
to 0 V
Low-Power Data Memory Retention in
Stop Mode
TA = -40 to + 85°C
Limits
Parameter
Data retention
voltage
Symbol
Min
VCCDR
2.0
Data retention ICCDR
supply current
TYP
Test
Max
Unit
Conditions
V
0.8
20
J1A
VCCDR =
2.0 V, (X1
=OV,X2=
open)
Data retention
input low
RESET voltage
VILDR
Data retention
input high
RESET voltage
VIHDR
REL input
delay time
to
500
J1S
REL Input
high time
tREL
10
J1S
0
0.2
VCCOR
0.8
VCCOR
V
VCCDR
Note:
(1) In data retention mode, input voltages to WAIT and PCO-PC5 pins
(with pull-up resistors) should be maintained the same as VeeDR
level; other input voltages should be kept less than VeeDR level.
4-7
4
NEe
pPD78C05A/06A
DC Characteristics
AC Characteristics
TA = -40 to +85°C; Vcc = +5 V ±10%
Limits
Parameter
Symbol
Min
Input high
voltage
VIH1
0.7 Vee
VIH2
0.75 Vee
VIH3
Vee - 2.0
VIH4
VIL1
Typ
Max
Unit
Vee
V
Test
Conditions
INTO,INT1,
WAIT, PBOPB7, PCO-PC5
Read/Write Operation
78C05A, tCY¢ = 660 ns; 78C06A, tCY¢ = 1320 ns
Limits
Parameter
Symbol
Min
Typ
Max
1070
+660
Unit
RD low time
tRR
ns
RD LE to
WAIT LE .
tRWT
460
ns
Address (PEo-
tAWTI
790
ns
V
RESET, SCK,
REL, SI
Vee
V
DBo-DB7
Vee - 0.5
Vee
V
X1
0
0.3 Vee
V
INTo-INT1'
WAIT, PBoPB7, PCO-PC5
VIL2
0
0.25 Vee
V
RESET, SCK,
REL, SI
VIL3
0
0.8
V
DBo-DB7
VIL4
0
0.5
V
X1
VOH1
2.4
V
10H =
-100tJA
M1 to RD LE (1) tMR
108
ns
RD TE to M1 (1) tRM
130
ns
V
10H =
-50 tJA
¢O!J.l.LE
to WR LE
tw
0.45
V
IOL = 1.8 mA
tA
420
ns
100
tJA
VIN = Vee
(REL)
Address (PEoPE15) to ¢OUT
TE
90
ns
tJA
VIN = Vee
(X1)
Address (PEoPE15) to ¢OUT
TE (1)
tA-
45
-100
tJA
VIN = 0 V
(WAIT, PCoPC5)
Address (PEoPE15) to data
output
tA02
510
ns
IIL2
-45
tJA
VIN = 0 V
(X1)
Data output
to WR TE
tow
740
+ 660N
ns
Input high
leakage
current
IUH
3.2
tJA
VIN = Vee
(except REL,
X1)
WR TE to data
stable time
two
130
ns
Address
tAW
460
ns
Input low
leakage
current
IUL1
-3.2
tJA
VIN =OV
(except WAIT,
PCO-PC5, X1)
(P~E15)
180
ns
-3.2
tJA
VIN =0 V
(Stop mode,
X1)
WRTE to
address
stable time
tWA
IUL2
WR low time
tww
ILOH
3.2
tJA
VOUT = Vee
690
+900N
ns
Output high
leakage
current
WR LE to
WAIT LE
tWWT
Output low
leakage
current
ILOL
Vee supply
current
lee1
4
7.5
mA
Operation
mode
lee2
1.2
2.7
mA
Halt mode
20
tJA
Stop mode
(X1 = 0 V, X2
= Open)
Input low
voltage
Output high
voltage
VOH2
Output low
voltage
VOL
Input high
current
IIH1
Vee- 0.5
7
IIH2
Input low
current
11L1
-3.2
tJA
VOUT = 0 V
WAIT LE
WAIT set-up
time to ¢OUT
LEo
tWTS
370
ns
WAIT hold
time after
¢OUT LE
tWTH
0
ns
175
ns
to WR LE
110
ns
Note:
(1) Applies only to 78C05A.
lee3
4-8
-7
~to
(2) N is number of WAIT states (TWAIT).
In the 78C06A, two WAIT state!> are automatically
inserted when accessing internal ROM.
(3) LE is leading edge and TE is trailing edge.
Test
Conditions
NEe
pPD78C05A/06A
AC Characteristics (cont)
Bus Timing Depending
on tCY4J
Serial Operation
TA = -40 to +85°C
Symbol
Formula
78C05A, tCY4J
= 660 ns; 78C06A, tC Y4J = 1320 ns
Limits
MiniMax
Unit
tR4J
(1/2)T -150
Min
ns
Parameter
Symbol
Min
TYP
Test
Conditions
Max
Unit
80,000
ns
ns
SCK input
SCK output
tA01
(3/2 + N)T - 200
Max
ns
SCK cycle
time
tCYK
1270
1280
tRA(T3)
(1/2)T -150
Min
ns
SCK low time
tKKL
tRA(T4)
(3/2)T -150
Min
ns
515
520
ns
ns
SCK input
SCK output
tRO
(1 + N)T - 200
Max
ns
SCK high
time
tKKH
515
520
ns
ns
SCK input
SCK output
tRR
(2 + N)T -250
Min
ns
200
ns
T -200
Max
ns
SI set-up time
to SCK TE
tSIS
tRWT
tAwTI
(3/2)T - 200
Max
ns
250
ns
tWTS
Min
SI hold time
after SCK TE
tSIH
(1/3)T + 150
ns
(3/8)T -140
Min
ns
SCK LE to
SO delay time
tKO
tMR (1)
tRM (1)
(1/2)T - 200
Min
ns
Note:
tA4J (1)
(1/2)T - 240
Min
ns
(1)
tA4J
T -240
Min
ns
(2)
tA02
T -150
Min
ns
Input timings are measured at VIH min and VIL max.
Output timings are measured at VOH= 2.4 V, VOL = 0.45 V, and
load = one TTL + 200 pF.
tow
(3/2 + N)T - 250
Min
ns
(3)
LE is leading edge and TE is trailing edge.
two
(1/2)T - 200
Min
ns
Clock Timing
tAW
T -200
Min
ns
TA
tWA
(1/2)T -150
Min
ns
300
ns
E
= -40 to +85°C voo = +5 V ±10%
Limits
(3/2 + N)T - 300
Min
ns
tWWT
(1/2)T - 220
Max
ns
X1 input
cycle time
tCYX
160
X1 input
low time
tXXL
75
ns
X1 input
high time
tXXH
75
ns
OUT
cycle time (2)
tCY4J
1,280
OUT low
time (2)
t4J4JL
515
ns
OUT high
time (2)
t4J4JH
515
ns
OUT
cycle time (1)
tCY4J
640
OUT
Low time (1)
t4J4JL
195
ns
OUT
high time (1)
t4J4JH
195
ns
OUT rise/
fall time
tR, tF
tCYK
2T
Min
ns
tKKL
T -120
Min
ns
tKKH
T -120
Min
ns
Note:
(1) For 78C05A only
(2) N = Number of TWAIT states
In the 78C06A, two wait states are automatically inserted
when accessing internal ROM.
T = tCY4J for 78005A
T = 2tCY 4J for 78C06A
tCY assumes 50% duty cycle on X1'
Symbol
Min
TYP
tww
Parameter
Max
Unit
10,000
ns
80,000
40,000
120
Test
Conditions
ns
ns
ns
Note:
(1 ) Applies only to 78C05A. (tCY4J
(2) Applies only to 78C06A. (tCY4J
= 4/fosc)
= 8IfosC>
4-9
NEe
pPD78C05A/06A
Timing Waveforms
Write Operation
! - - - T , - - - t - - -T2 - - - t - - -TWAIT---i·I---T3 - - - {
ILPD78C06A: OUT
PEo-PE,5 ____
,~------~------------------~--------__----------~--------------------~,---
DBO-DB7----~------+_----_\__________~__------~----~~~~~~~--------------------
ILPD78C05A: M,
4-10
NEe
pPD78C05A/06A
Timing Waveforms (cont)
Countup operation is initiated upon execution of the
STM instruction. When the contents of the upcounter
are incremented and a coincidence with the Timer Reg.
occurs, an internal interrupt (INTT) is generated. The
duration of the time-out may be altered by loading new
contents into the timer register.
Serial Operation
The timer flip-flop is set by the STM instruction and
reset on a countup operation. Its output (TO) is
available externally and may be used for general
external synchronization.
Serial Port Operation
83-003075A
Clock Timing
"'OUT
83-003076A
The on-ch ip serial port (figure 3) provides basic synchronous serial communication functions allowing the
pPD78C05A/06A to serially interface with external
devices.
Serial transfers are synchronized with either the internal
clock or an external clock input (SCK). The transfer
rate is fixed at fasc/8 if the internal clock is used or is
variable between dc and fasc/8 when an external clock
is used. The clock source select is determined by the
serial mode register. Data on the 81 (serial input) line is
latched into the serial register on each rising edge of
the serial clock (SCK). Concurrently, data is transferred
out of the serial register onto the 80 (serial output) line
with each falling edge of SCK. At this time, receive and
transmit operations th rough the SI/SO port are enabled.
Receive and transmit operations are performed MSB
first.
Functional Description
Interrupt Structure
Memory Map
The pPD78C05A/06A provide a maskable interrupt
structure capable of handling vectored prioritized
interrupts. Interrupts can be generated from three
different sources: two external interrupts and a timer
interrupt. When activated, each interrupt branches to a
designated memory vector location for that interrupt.
See table 1.
The pPD78C06A can directly address up to 64K bytes
of memory. Except for the on-chip ROM (0-4,095) and
RAM (65,408-65,535), any memory location can be
used as either ROM or RAM. Figure 1 defines the 064K-byte memory space for the pPD78C06A showing
that the reset start address, interrupt start address, call
tables, etc, are located in the internal ROM area.
Timer Operation
A programmable 8-bit timer (figure 2) is provided onchip for measuring time intervals, generating pulses,
and general time-related control functions. It is capable
of measuring time intervals from 5 j1S to 21 ms in
duration. The timer consists of a prescaler that decrements an 8-bitcounter at a fixed 5-ps or 82-ps rate.
Table 1.
Interrupt Structure
INT
Vectored Memory
Location
Priority
INTT
8
2
Internal, timer overflow
Type
INTo
4
1
External, level sensitive
INT1
16
3
External, rising-edge
sensitive
..:1-11
II
...
NEe
pPD78C05A/06A
Figure 1.
Memory Map
0
Reset/Stop Release
Internal ROM
4,096 x 8
4
INTo
8
INTT
4,095
4,096
[
INT,
External
Memory
61,312 x 8
"I
-
65,279
65,280
------------------ -
128
Low Address
129
High Address
130
Low Address
131
High Address
Call Table
Working
I- Register
65.407
65.40 8
Internal RAM
128 x 8
254
Low Address
255
High Address
-
65,535
User's Area
<---------------------------
-PEX Instruction - - - - - - - - - - - - - - - - - - - - - - - - - - -
>
\ ----\---- \ ---- \---- \ ---- \---- \ ----I ---- \---- \ ----I -.:.--\ -.:.-- \
T,
M,
T2
T3
T.
T,
T2
T3
T.
T,
T2
T3
J - - - - - - - - - - - - - - \'-_______________________________________________
AB)(_________I_st_B~y_te_F_et_ch________~X~________
2n_d_B~y~te_F_et~ch________~X~
___B_C~_JX~______________
NEe
Figure 2.
pPD78C05A/06A
Timer Block Diagram
Instruction-_------------+-----_---------+------------,
Prescaler 1
System
Clock
(3)
System Clock = Oscillation Frequency x 1/4
Figure 3.
Serial Port Diagram
Internal Bus
~----------------~
WRs
RDs
SI
SO
Octal Counter
T.(INTS)
Internal SCK
S
Start SilO
R
T.
4-1~
NEe
pPD78C05A/06A
Reset
Table 2.
An active-low signal on the RESET input for more than
4 ps forces the pPD78C05A/06A into a reset condition,
which affects the following internal functions:
Function
Halt Mode
Stop Mode
Oscillator
Run
Stop
Internal system clock
Stop
• The interrupt enable flags are reset, and interrupts
are inhibited.
• The interrupt request flag is reset.
• The halt flip-flop is reset, and the halt state is
released.
• The contents of the mode B register are set to FFH,
and port B becomes an input port.
• All flags are reset to O.
• The internal count register for timer operation is set
to FFH and the timer F/F is reset.
• The contents of the program counter are set to
OOOOH.
• Data bus (DBo-DB7), RD, and WR go to a highimpedance state.
Once the RESET input goes high, the program is
started at location OOOOH.
Halt and Stop Modes
Timer
Run
Timer register
Hold
Upcounter, prescaler 0, 1
Run
Cleared
Serial interface
Run
Run (1)
Serial clock
Hold
Hold
Interrupt control circuit
Run
Stop
Interrupt enable flag
Hold
Reset
INTo, INT 1 input
Active
Inactive
Hold
Set
REL input
Inactive
Active
Set
INTT
T8 (lNTFS)
Mask register
Pending interrupts (INTFX)
Reset
RESET input
Active
Stop and Halt Modes
On-chip RAM
Hold
The JlPD78C05A/06A have a stop and a halt mode. The
effects of stop and halt on various functions are shown
in table 2.
Output latch in ports A, B, E
Hold
Program counter (PC)
Cleared
Stack pOinter (SP)
Unknown
General registers (A, B, C, 0, E, F, L)
Registers
The JlPD78C05A/06A contain seven 8-bit registers and
two 16-bit registers. See figure 4.
Program status word (PSW)
Reset
Mode B register
Hold
Standby control register (SCO-SC3)
General Purpose Registers
Standby control register (SC4)
Set
The general purpose registers B, C, D, E, H,· L can
function as auxiliary registers to the accumulator or in
pairs as data pOinters (BC, DE, HL). Automatic
increment and decrement addressing mode capabilities
extend the uses for the DE and HL register pairs.
Timer mode register (TMMo-TMM1)
Hold
Timer mode register (TMM1)
Set
Serial mode register (SM)
Hold
Figure 4.
Registers
Data bus (DBo-DB7)
High-Z
High-Z
RD, WR output
High
High
Note:
15
(1) Serial clock counter is running and T 8 is generated; however,
there are no effects from it.
PC
SP
A
c
Main
o
H
83-003077A
4-14
NEe
jlPD78C05A/06A
Accumulator [A]
Automatic Decrement Addressing
All data transfers between the jlPD78C05AI 06A and
external memory or 1/0 are done through the accumulator.
~~----------~~----~~_l------loperandl
rp
Memory
Program Counter [PC]
The PC is a 16-bit register containing the address of the
next instruction to be fetched. Under normal program
flow, the PC is automatically incremented. However, in
the case of a branch instruction, the PC contents are
from another register or an instruction's immediate
data. A reset sets the PC to OOOOH.
Stack Pointer [SP]
The stack pointer is a 16-bit register used to maintain
the top of the stack area (Iast-in/first-out). The contents
of the SP are decremented during a Call or Push
instruction or if an interrupt occurs. The SP is incremented during a Return or POP instruction.
Working-Register Addressing
The contents of the register are linked with the byte
following the opcode to form a memory address that
contains the operand. The V register is used to indicate
the memory page. This address mode is useful as a
short-offset address mode when working with operands
in a common memory page where only one additional
byte is required for the address. Mnemonics with a W
suffix indicate this address mode. In the jlPD78C05AI
06A, the V register is always FFH.
"r
PC
PC + 1
I
Address Modes
Register Addressing
The instruction opcode specifies a register that
contains the operand.
r
~~-------------------------------.~
The instruction opcode specifies a register pair that
contains the memory address of the operand. Mnemonics with an X suffix indicate this address mode.
rp
Memory
Operand
I
t
I
Il
Direct Addressing
The two bytes following the opcodespecify an address
of a location containing the operand.
Opcode
PC
Register Indirect Addressing
FFHex
Memory
I
PC + 1
PC
+
Low Address
f--------I
2 High Address
Operand
I
1 Byte
Immediate Addressing
PC
PC+ 1
Automatic Increment Addressing
The opcode specifies a register pair that contains the
memory address of the operand. The contents of the
register pair are automatically incremented to point to
a new operand. This mode provides automatic sequential stepping when working with a table of
operands.
rp
Immediate Extended Addressing
PC
PC+ 1
PC+2
Opcode
Low Operand
High Operand
Memory
~~----------~'~~-----~~----__'Ioperandi
B
L...-....-_
4-15
NEe
pPD78C05~/06A
Clock Driver Circuit
Instructions
The 6.25-MHz master timing signal is from an external
oscillator connected to pin X1 or from an internal
oscillator controlled by an external 6.25-MHz crystal
connected to pins X1 and X2 (figure 5). Dividing fosc
by four creates the internal CPU clock (f4> = 1.5625
MHz).
A system clock is available for external use at the ¢OUT
pin. Its frequency is 1.5625 MHz (6.25/4) or 0.78125
MHz (6.2S/8) for 78C05A and 78C06A, respectively.
Figure 5.
External 6.25-MHz Crystal
X1
16.25
ric>
T
1
pPD7BC05A106A
MHz
C2
X2
Crystal speclflcallons
AT cut
lose = 6.25 MHz
R=50n
CL = 16 ±0.2 pF
P = 1.0 ±0.2 mW
Instruction Set Definitions
Description
Operand
A, B,C, D, E,H,L
r1
B, C, D, E, H, L
r2
A, B, C
sr
PA, PB, PC, MK, MB, TMO, TM1, S, SM, SC
sr1
PA, PB, PC, MK, S, TMO, TM1, SC
sr2
PA, PB, PC, MK
rp
SP, B,D,H
rp1
rpa
B,D,H
wa
a-bit immediate data used to access working register area
B, D, H, D+, H+, D-, H-
word
16-bit immediate data
byte
8-bit immediate data
bit
1-bit immediate data
if
FO, F1, FT, FS
F
CY,Z
fa
10-bit immediate data used to access fixed area in
locations 0-2047
ta
5-bit immediate data used to access table in locations
128-191
Capacitor specifications
C1, C2 = 5to 20 pF [Including stray capacitance]
IC1-C21 :510pF
Number of bytes in an instruction
83-002772A
Note:
(1) When special register operands sr, sr1, sr2 are used, PA = port A,
PB = port B, PC = port C, MK = mask register, MB = mode B
register, SM = serial mode register, SC = standby control
register, TMo = timer register 0, TM1 = timer register 1,
S = serial register.
(2)
When register pair operands rp, rp1 are used, SP = stack pointer,
B = BC, D = DE, H = HL.
(3)
Operands rpa, rp1, wa are used in indirect addressing and
auto-incrementlauto-decrement addressing modes. B = (BC),
D=(DE), H=(HL), D+=(DE)+, H+=(HL)+, D-=(DE)-,and
H-= (HL)-.
(4)
When the interrupt operand "if" is used, FO = INTFO, F1 = INTF1,
FT = INTFT, FS = INTFS.
(5)
When the operand F is used, CY = Carry and Z = Zero.
(6) The V register is always FFH.
4-16
NEe
jlPD78C05A/06A
Instruction Set
Mnemonic
Operand
Bytes
*Clocks
Skip
Condition
Operation
Flags
CY
Z
8·8it Data Transfer
MOV
r1,A
4/6
(r1) +- (A)
MOV
A,r1
4/6
(A) +- (r1)
MOV
sr,A
2
10114
(sr) +- (A)
MOV
A,sr1
2
10/14
(A) +- (sr1)
MOV
r,word
4
17/25
(r) +- (word)
MOV
word,r
4
17125
(word) +- (r)
2
MV1
r,byte
7/11
(r) +- (byte)
STAW
wa
10/14
(FFH,wa) +- (A)
LDAW
wa
10/14
STAX
rpa
7/9
((rpa))+- (A)
LDAX
rpa
7/9
(A) +- ((rpa))
(A) +- (FFH,wa)
16·8it Data Transfer
SBeD
word
20/28
(word)
+-
(e), (word + 1)
SDED
word
20/28
(word)
+-
(E), (word + 1) +- (D)
SHLD
word
20/28
(word)
+-
(L), (word + 1) +- (H)
SSPD
word
20/28
(word) -- (SPLl,
((word) + 1) - (SPH)
LBeD
word
20/28
(e) +- (word), (B) -
+-
(B)
II
(word + 1)
LDED
word
20/28
(E) +- (word), (D) +- (word + 1)
LHLD
word
20/28
(L) +- (word), (H) -
LSPD
word
20/28
(SP1) +- (word)
POP
rp1
14/18
(rp1L) +- ((SP))
(rp1H) +- ((SP) + 1),
(SP) +- (SP) + 2
LXI
rp,word
10/16
(rp) -
8/12
(A)-(A)+(r)
(word + 1)
word
Arithmetic
ADD
A,r
ADDX
rpa
ADe
A,r
ADeX
SUB
2
11/15
(A) -
(A) + ((rpa))
2
8/12
(A) -
(A) + (r) + (ey)
rpa
2
11/15
(A) -
(A) + ((rpa)) + (ey)
A,r
2
8/12
(A)-(A)-(r)
SUBX
rpa
2
11/15
(A) -
(A) - ((rpa))
SBB
A,r
2
8/12
(A) -
(A) - (r) - (ey)
SBBX
rpa
2
11/15
(A) -
(A) - ((rpa)) - (ey)
ADDNe
A,r
2
8/12
(A)-(A)-(r)
No carry
ADDNeX
rpa
2
11/15
(A) -
No carry
SUBNB
A,r
2
8/12
(A)-(A)-(r)
No borrow
SUBNBX
rpa
2
11/15
(A) -
No borrow
(A) - ((rpa))
(A) - (rpa)
4-17
NEe
pPD78COSA/06A
Instruction Set (cont)
Mnemonic
Operand
Bytes
Operation
*Clocks
Skip
Condition
Logical
(A)--(A)A(r)
ANA
A,r
2
8/12
ANAX
rpa
2
11/15
(A) -- (A) A ((rpa))
ORA
A,r
2
8/12
(A)--(A)V(r)
(A) -- (A) V ((rpa))
ORAX
rpa
2
11/15
XRA
A,r
2
8/12
(A) -- fA) V (r)
XRAX
rpa
2
12/15
(A) -- (A) V ((rpa))
GTA
A,r
2
8/12
(A)-(r)-l
No borrow
GTAX
rpa
2
11/15
(A) - ((rpa))-l
No borrow
LTA
A,r
2
8/12
(A)- (r)
LTAX
rpa
2
11/15
(A) -((rpa))
Borrow
ONAX
rpa
2
8/12
(A) A ((rpa))
No zero
OFFAX
rpa
2
11/15
(A) A ((rpa))
NEA
A,r
2
8/12
(A)-(r)
No zero
No zero
Borrow
Zero
NEAX
rpa
2
11/15
(A) - ((rpa))
EQA
A,r
2
8/12
(A)-(r)
Zero
EQAX
rpa
2
11/15
(A) - ((rpa))
Zero
7/11
(A) -- (A) V byte
7/11
(A)
Immediate Data Transfer (Accumulator)
XRI
A,byte
ADINe -
A,byte
2
SUINB
A,byte
2
7/11
(A) -- (A) - byte
ADI
A,byte
2
7/11
(A) -- (A)
ACI
A,byte
7/11
(A) -- (A)
SUI
A, byte
7/11
(A) -- (A) - byte
SBI
A,byte
ANI
A,byte
ORI
2
+-'-
(A) - byte
No carry
No borrow
+ byte
+ byte+ (CY)
7/11
(A) -- (A) - byte -(CY)
2
7/11
(A) -- (A) A byte
A,byte
2
7/11
(A) -- (A) V byte
GTI
A,byte
2
7/11
(A) - byte-l
No borrow
LTI
A,byte
2
7/11
(A) - byte
Borrow
ONI
A,byte
2
7/11
(A) A byte
No zero
OFFI
A,byte
2
7/11
(A) A byte
Zero
NEI
A,byte
2
7/11
(A) - byte
No zero
EQI
A,byte
2
7/11
(A) - byte
Zero
Immediate Data Transfer (Special Register)
ANI
sr2,byte
3
17/23
(sr2) -- (sr2) A byte
ORI
sr2,byte
3
17/23
(sr2) -- (sr2) V byte
OFFI
sr2,byte
3
14/20
(sr2) A byte
Zero
ONI
sr2,byte
3
14/20
(sr2) A byte
No zero
4-18
Flags
CY
Z
NEe
pPD78C05A/06A
Instruction Set (cont)
Mnemonic
Skip
Condition
Operand
Bytes
*Clocks
Operation
ANIW
wa,byte
3
16/22
(FFH, wa) +- (FFH, wa) A byte
ORIW
wa,byte
3
16/22
(FFH, wa) +- (FFH, wa) V byte
GTIW
wa,byte
3
13/19
(FFH, wa) - byte - 1
No borrow
LTIW
wa,byte
3
13/19
(FFH, wa) - byte
Borrow
ONIW
wa,byte
3
13/19
(FFH, wa) A byte
No zero
OFFIW
wa,byte
3
13/19
(FFH, wa) A byte
Zero
NEIW
wa,byte
3
13/19
(FFH, wa) - byte
No zero
EQIW
wa,byte
3
13/19
(FFH, wa) - byte
Zero
Flags
CY
Z
Working Register
Increment/Decrement
(r2) +- (r2)
+1
INR
r2
4/6
INRW
wa
13/17
DCR
DCRW
r2
wa
4/6
13/17
INX
rp
7/9
(rp)+-(rp)
DCX
rp
7/9
(rp)+-(rp) - 1
DAA
4/6
Decimal adjust accumulator
STC
8/12
(CY) +-1
1
CLC
8/12
(CY) +- 0
0
RLD
17/21
Rotate left digit
RRD
17/21
Rotate right digit
RAL
8/12
(A m+1) +- (Am), (AO) +- (CY),
(CY) +- (A7)
RAR
8/12
(A m-1) +- (Am), (A7) +- (CY),
(CY) +- (Ao)
(FFH, wa) +- (FFH, wa)
(r2) +- (r2) - 1
Carry
+1
(FFH, wa) +- (FFH, wa)-1
Carry
Borrow
Borrow
+1
E
Miscellaneous
Rotate and Shift
Jump
JMP
word
10/16
JB
4/6
JR
word
JRE
word
2
(PC) +- word
(PCH) +- (B), (PCl) +- (C)
10/12
(PC) +- (PC)
13/17
(PC) +- (PC)
+ 1 + jdisp1
+ 2 + jdisp
4-19
NEe
J.IPD78C05A/06A
Instruction Set
Mnemonic
Operand
Bytes
*Clocks
3
16/22
((SP) - 1) -- ((PC) + 3)H,
((SP) ~ 2) -- ((PC) + 3)l,
(PC) -- word
Skip
Condition
Operation
Call
CALL
word
CALF
word
13/17
((SP) - 1) - ((PC) + 2)H,
((SP) - 2) - ((PC) + 2)l,
(PC1S-PC11) - 00001,
(PC lO -PCO) -fa
CALT
word
19/21
((SP) -1) - ((PC) + 1)H,
((SP) - 2) - ((PC) + 1lL,
(PCl) - (128 + 2ta),
(PCH) - (129 + 2ta)
10/12
(PCl) - ((SP)),
(PCH) - ((SP) +1),
(SP) - (SP) + 2
RETS
10+n/12+n
(PCLl ~ ((SP)),
(PCH) - ((SP) +1),
(SP) - (SP) +2,
(PC) - (PC) +n
RETI
13/15
(PCLl - ((SP)),
(PCH) - ((SP) +1),
(PSW) -- ((SP) +2),
(SP) - (SP) +3
Return
RET
Skip
SKNC
SKNZ
2
2
8/12
8/12
Skip if no carry
Skip if co zero
Cy= 0
Z=O
SKNIT
2
8/12
Skip if no INT X otherwise
reset INT X
f=O
NOP
1
4/6
No operation
EI
2
8/12
Enable interrupt
DI
2
8/12
Disable interrupt
4/6
4/6
Start (trigger) serial 1/0
start timer
CPU Control
Serial Port Control
SIO
STM
Port EControl
PEX
2
11/15
(PE1S-PES) - (B),
(PE7-PEO) - (C)
PER
2
8/12
Port E AB mode
4-20
Flags
CY
Z
NEe
pPD78C05A/06A
Program Status Word (PSW) Operation
Operation
Reg. Memory
Immediate
Skip
ADD
ADC
SUB
SBB
ADDX
ADCX
SUBX
SBBX
AD!
ACI
SUI
SBI
ANA
ORA
XRA
ANAX
ORAX
XRAX
ANI
ORI
XRI
ADDNC
SUBNB
GTA
LTA
ADDNCX
SUBNBX
GTAX
LTAX
ADINC
SUINB
GTI
LTI
GTlW
LTIW
ONAX
OFFAX
ONI
OFFI
ONIW
OFFIW
NEA
EQA
NEAX
EQAX
NEI
EQI
NEIW
EQIW
INR
DCR
INRW
DCRW
06
°5
Z
SK
°4
HC
0
ANIW
ORIW
0
D3
L1
°2
LO
00
CY
0
•
•
0
•
0
0
0
DAA
•
•
RLL,RLR
RLD-RRD
•
•
STC
CLC
MVI A, byte
MVI L, byte
LXI H, word
SKNC
SKNZ
SKNIT
RETS
All other
instructions
•
•
•
•
•
•
0
0
0
0
0
0
0
1
0
•
•
•
•
•
•
•
•
•
•
0
0
•
0
0
0
0
•
0
•
•
0
0
•
•
Flag Symbols:
t
1
0
•
Flag
Flag
Flag
Flag
affected according to result of operation.
set
reset
not affected.
4-21
I]
J.lPD78C05A/06A
4-22
NEe
NEe
NEe Electronics Inc.
pPD7S07/0S/09
HIGH-END, S-BIT, SINGLE-CHIP
NMOS MICROCOMPUTERS
WITH COMPARATOR AND SK ROM
PRELIMINARY INFORMATION
Description
Pin Configuration
The pPD7807/pPD7808/j1PD7809 single chip microcomputer augments the high-end NEG family of 8-bit
microcomputers with on-chip peripheral functions.
Like the j1PD7811, the device has a fast internal 16-bit
ALU and data paths, 256 bytes of RAM, a multifunctional
16-bit timer/event counter, two 8-bit timers, a USART,
and two zero-cross detect inputs.
Other features are 8K ROM (4K ROM for the j1PD7808),
a programmable threshold comparator (8 inputs), a
programmable WAIT function, a watchdog timer, hold
and hold acknowledge for DMA interfaces, and bit
test/write instructions for both RAM and I/O.
The pPD7809 and pPD7808 are mask-ROM versions
with your program on chip. The j1PD7807 is the ROMless version for prototyping and small volume
applications.
Features
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
NMOS silicon gate technology requiring +5 V power
supply
Complete single-chip microcomputer
-16-bit ALU
-8K ROM (4K ROM for the j1PD7808)
-256-byte RAM
Large I/O capability
-40 I/O port lines (J1PD7809 and j1PD7808)
-28 110 port lines (j1PD7807)
-8 input lines
Two zero-cross detect inputs
Expansion capabilities (64K memory access total)
-8085A bus compatible
-56K-byte external memory address range
(60K for the j1PD7808)
Programmable threshold comparator
-8 inputs, 1 of 16 software selectable levels
Full duplex USART
-Synchronous and asynchronous
165 instructions
-16-bit arithmetic, multiply and divide
1 j1S instruction cycle time
Prioritized interrupt structure
-3 external
-8 internal
Hold, hold acknowledge for DMA interface
Programmable WAIT function
Watchdog timer
Standby function
On-chip clock generator
64-pin plastic straight or bent lead QUIP or plastic
shrink DIP
IJ
HLDA
NMI
INT1
MODEl
RESET
MODEO
49-000477A
Ordering Information
Part
Number
Package Type
Max Freq.
of Operation
JlPD7807G-36
JlPD7808G-36
JlPD7809G-36
64-Pin plastic QUIP
12 MHz
JlPD7807CW
JlPD7808CW
JlPD7809CW
64-Pin plastic shrink DIP
12 MHz
4-23
NEe
pPD7807/08/09
Pin Identification
No.
Symbol
PCO·PC7 [Port C]
Function
1-8
PAo-PA7
PortA I/O
9-16
PBO-PB7
Port B I/O
17
PCO/TxO
Port C I/O line O/Transmit data output
18
PC1/RxO
Port C I/O line 1/Receive data input
19
PC2/SCK
Port C I/O line 2/Serial clock I/O
20
~TI/
NT2
Port C I/O line 3/Timer input/Interrupt
request 2 input
21
PC4/TO
Port C I/O line 4/Timer output
22
PCs/CI
Port C I/O line 5/Counter input
23,24
PC6, PC7/
COo' C01
Port C I/O lines 6, 7/Counter outputs 0,1
25
NMI
Nonmaskable interrupt input
26
INT1
Interrupt request 1 input
. Mode 1 input/memory cycle 1 output
27
MOOE1/M1
28
RESET
Reset input
29
MOOEO/
iO/M
Mode 0 input/I/O/memory output
30,31
Port C is an 8-bit three-state port. Each bit is independently programmable as either input or output.
Alternatively, the lines of port C can be used as control
lines for the USART and timer. Reset puts all lines of
port C in port mode; input.
TxD [Transmit Data]. Serial data output terminal.
RxD [Receive Data]. Serial data input terminal.
SCK [Serial Clock]. Output for the serial clock when
internal clock is used. Input for serial clock when
external clock is used.
TI [Timer Input]. Timer input terminal.
INT2 [Interrupt Request 2]. Falling-edge-triggered.
maskable interrupt input terminal and AC-input. zerocross detection terminal.
TO [Timer Output]. The output of TO is a square wave
with a frequency determined by the timer.
CI [Counter Input]. External pulse input to timer/event
counter.
COo, C01 [Counter Outputs 0, 1]. Programmable
rectangular wave outputs based on timer/event
counter.
X2, X1
Crystal connections 1, 2
32
Vss
Ground
33
VRTH
Port T threshold voltage input
34-41
PTo-PT7
Port T variable threshold input port
PDO·P07 [Port 0]
42
HOLD
Hold request input
43
HLDA
Hold acknowledge output
Port 0 is an 8-bit three-state port. It can be programmed
as either 8 bits of input or 8 bits of output. When
external expansion memory is used, port 0 acts as the
multiplexed address/data bus.
44
AD
Read strobe output
45
WR
Write strobe output
46
ALE
Address latch enable output
47-54
PFO-PF7
Port F I/O
55-62
POO-P07
Port 0 110
63
VDD
RAM backup power supply
64
Vee
5 V power supply
Pin Functions
PAo·PA7 [Port A]
Port A is an 8-bit three-state port. Each bit is independently programmable as either input or output.
Reset makes all lines of port A inputs.
PBo·PB7 [Port B]
Port B is an 8-bit three-state port. Each bit is independently programmable as either input or output.
Reset makes all lines of port B inputs.
4-24
PFo·PF7 [Port F]
Port F is an a-bit three-state port. Each bit is
independently programmable as an input or output.
When external expansion memory is used, port F
outputs the high-order address bits.
PTo·PT7 [Port T]
Port T is made up of a variable threshold inputs. The
input of each line is compared to a threshold voltage.
VRTH [Variable Threshold Reference Voltage]
VRTH is the reference voltage that the port T threshold
voltage is derived from.
NMI [Nonmaskable Interrupt]
Falling-edge-triggered nonmaskable interrupt input.
t-IEC
pPD7S07/0S/09
INT1 [Interrupt Request 1]
Voo [Backup Power]
INT1 is a rising-edge-triggered, maskable interrupt
input. It is also an AC-input, zero-cross detection
terminal.
Backup power for on-chip RAM.
RESET [Reset]
When the RESET input is brought low, it initializes the
PD7807/08/09.
MODE1, MODEO [Mode 1, 0]
The MODE1 and MODEO inputs select the memory
expansion mode. MODE1 also outputs the M1 signal
during each opcode fetch. MODEO outputs the 101M
signal.
HOLD [Hold Request]
When the HOLD input is high, the CPU is put in a hold
state until HOLD is brought low.
HLDA [Hold Acknowledge]
The CPU brings the HLDA output high when it is in the
hold state, and low when the hold is released.
RD [Read Strobe]
The RD output goes low to gate data from external
devices onto the data bus. RD goes high during reset.
Three-state.
WR [Write Strobe]
The WR output goes low to indicate that the data bus
holds valid data. It is a strobe signal for external
memory or I/O write operations. WR goes high during
reset. Three-state.
ALE [Address Latch Enable]
Vee [Power Supply]
+5 V power supply.
Input/Output
ThepPD7S07/0S/09 has S comparator input lines (port
T) and 40 digital I/O lines; five S-bit ports (port A, port
B, port C, port D, port F).
Comparator Input Lines. PTo-PT7 are configured as
variable threshold comparator input lines.
Port A, Port B, Port C, Port F. Each line of these ports
can be individually programmed as an input or output.
When used as I/O ports, all have latched outputs and
high-impedance inputs.
Port D. Port D can be programmed as a byte input or a
byte output.
Control Lines. Under software control, each line of port
C can be configured individually to provide control
lines for the serial interface, timer, and timer/counter.
Memory Expansion. In addition to the single-chip
operation mode, the pPD7S09 has four memory expansion modes. Under software control, port 0 can provide
a multiplexed low-order address and data bus; port F
can provide a high-order address bus. Table 1 shows
the relation between memory expansion modes and
the pin configurations of port 0 and port F.
Table 1.
Memory Expansion Modes and Port
Configurations
Memory
Expansion
Port Configuration
None
The ALE output latches the address signal to the
output of PDo-PD7.
Port D
Port F
I/O port
110 port
256 Bytes
Port D
Port F
Multiplexed addressldata bus
110 port
X1, X2 [Crystal Connections 1,2]
4K Bytes
Port D
Port Fo-F3
Port F4-F7
Multiplexed addressldata bus
Address bus
110 port
16K Bytes
Port D
Port Fo-Fs
Port Fs-F7
Multiplexed addressldata bus
Address bus
110 port
56K Bytes
Port D
Port F
Multiplexed addressldata bus
Address bus
X1 and X2 are the system clock crystal oscillator
terminals. X1 is the input for an external clock.
Vss [Ground]
Ground potential.
4-25
NEe
pPD7807/08/09
Block Diagram
Xl=EJ
Osc.
X2
PF7 -PF o
(AB'5- AB .)
PCo/TxD
Inc./Dec.
PC,/RxD
PC
SF
EA
PC,tSCK
13
V
A
B
C
0
16
Main
G.R.
H
INT1
EA'
V'
B'
PD7 -PDo
(AD7 -AD o)
Program
Memory
A'
C'
Alt.
G.R.
",PD7809
BK-bytes
Data
Memory
(256-byte)
E'
PC 7 -PC o
PC 3 /TI/INT2
PCs/CI
PCs/COO
PB 7 -PB o
PC,/COl
PT 7 -PT o
PA7 -PA o
VRTH
Notes: The pPD7B07 has no on chip ROM.
HOLD
HLDA
ALE
MODE 1
J
I
MODE 0
L
Voo
RESET
II
49'000554C
Timers
Timer/Event Counter
The timers consist of two 8-bit timers: The timers may
be programmed independently or may be cascaded
and used as a 16-bit timer. The timer can be software
set to increment at intervals of four machine cycles
(1 /1S at 12 MHz operation) or 128 machine cycles (32/1s
at 12 MHz), or to increment on receipt of a pulse at TI.
Figure 1 shows the block diagram for the timer.
The 16-bit multifunctional timer/event counter (figure
2) can be used for the following operations:
• Interval timer
• External event counter
• Frequency measurement
• Pulse width measurement
• Programmable square-wave output
4-26
ttfEC
Figure 1.
pPD7S07/0S/09
Timer Block Diagram
,------
Timer 0
,---------,
Timer 1
PC 3 iT1
I
I
I
I
---,
Timer/Event
Counter
I
I
Watchdog Timer
Serial Interface
Clear
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
L
__ _
_
INTTa
INTT,
I
_ _ ...J
Internal Bus
Notes: 1 CL = 311 (250n5: 12MHz operation).
I: System clock lrequency (MHz).
49·0005906
Interrupt Structure
Table 2.
There are 11 interrupt sources. Three are external
interrupts and eight are internal. The following, table 2,
shows 11 interrupt sources divided into six priority
levels. See figure 3.
Interrupt
Request
IRQO
IRQ1
Interrupt Sources
Interrupt
Address
4
8
Standby Function
The standby function saves the top 32 bytes of RAM with
backup power (Voo) if the main power (Vee) fails. On
power up, you can check the standby flag to determine
whether recovery was made from standby mode or from
a cold start.
Type of Interrupt
Internal/
External
NMI (Nonmaskable interrupt)
Ext
INTWD (Watchdog timer)
Int
INTTO (Coincidence signal from
timer 0)
Int
INTT1 (Coincidence signal from
timer 1)
IRQ2
16
INT1 (Maskable interrupt)
Ext
INT2 (Maskable interrupt)
IRQ3
24
INTEO (Coincidence signal from
timer/event counter)
Int
INTE1 (Coincidence signal from
timer/event counter)
IRQ4
32
IRQ5
40
INTEIN (Falling signal of CI and
TO counter)
Int/Ext
INTSR (Serial receive interrupt)
Int
INST (Serial send interrupt)
4-27
NEe
pPD7807/08/09
Figure 2.
Timer/Event Counter Block Diagram
CPO
CP1--t---I
Output
Control
EIN
PC.,IC01
INT1
4CL
PCs/CI
----+--+------1
o--_~-1-----+____f
TO
CPO
INTEO
Interrupt
Control
INTE1
INTEIN
t-----------------+------Notes: 1 CL = 3/1 [250 ns: 12 MHz operation}.
f: System clock frequency [MHz}.
Figure 3.
NMI
INTTO
INm
INTI
INT2
INTEO
INTE1
INTEIN
INTWD
INTSR
INTST
Interrupt Structure Block Diagram
EIN
49·000553C
Figure 4.
Universal Ser/a/lnterface B/ock Diagram
PC,/RxD
OV
ER
S8
SK2 SK1
PCo/TxD
49·000591 A
4-28
NEe
Universal Serial Interface
The serial interface can operate in one of three modes:
synchronous, asynchronous, and I/O interface. The
I/O interface mode transfers data MSB first, for easy
interfacing to certain NEG peripheral devices.
Synchronous and asynchronous modes transfer data
LSB first. Synchronous operation offers two modes of
data reception: search and nonsearch. In the search
mode, data is transferred one bit at a time from the
serial register to the receive buffer. This allows a
software search for a sync character. In the nonsearch
mode, data transfer from the serial register to the
transmit buffer occurs eight bits at a time. In asynchronous mode, the serial interface can act as a fullduplex USART with data transfer rates up to 125K bps.
Figure 4 shows the universal serial interface block
diagram.
Zero-Crossing Detector
The INT1 and INT2 terminals (used common to TI and
PC3) can detect the zero-crossing point of lowfrequency AC signals. When driven directly, these pins
respond as a normal digital input. Figure 5 shows the
zero-crossing detection circuitry.
The zero-crossing detection capability allows you to
make the 50-60 Hz power signal the basis for system
timing and to control voltage phase sensitive devices.
To use the zero-cross detection mode, an AC signal of
approximately 1-3 V AC (peak-to-peak) and a maximum
frequency of 1 kHz is coupled through an external
capacitor to the INT1 and INT2 pins.
jlPD7S07/0S/09
Figure 5.
Zero-Crossing Detection Circuitry
IINT1
C
IINT2 (PC3)
----l f------<)---'--_--~
>0------1>0--
83-00383SA
Figure 6.
Threshold Variable Input Port
PToo--------~
PT,o--------+--n...
PT2 o--------+--n...
PT3 o--------+--n-...
II
PT. C>--------+--Qo,.
PTsC>--------+--n-...
PT6 C>--------+-O-"
PT7o--------+~
For the INT1 pin, the internal digital state is sensed as a
the rising edge crosses the average DC level,
when it becomes a 1 and INT1 interrupt is generated.
o until
For the INT2 pin, the state is sensed as a 1 until the
falling edge crosses the average DC level, when it
becomes a 0 and INT2 interrupt is generated.
49-000594A
Variable Threshold Input Port [Port T]
Port T has the following features:
• 8 input lines
• 16 threshold levels from 1/16 to 16/16 of reference
voltage (VRTH)
• Level selected by writing to mode T register
(figure 7)
• Output of comparator reads 0 until voltage at pin
exceeds selected level
• Comparison execution time: 12 flS
Figure 6 shows the block diagram for the threshold
variable input port. Figure 7 shows the mode T register
format.
4-29
NEe
pPD7807/08/09
Figure 7.
7
6
Watchdog Timer
Mode T Register Format
5
4
3
r-I-T -1-1 MT31 MT2 MT,I MTal
Specification of 16 Threshold Levels
0
0
0
0
0
0
0
1
VTHX
0
0
1
0
VTHX'!-\.
0
0
1
1
VTH X
0
1
0
0
V TH X'Y1.
0
1
0
1
VTH X
0
1
1
0
VTH X
0
1
1
1
VTH XY16
1
0
0
0
V TH Xo/,.
1
0
0
1
V TH X 'Yi.
1
0
1
0
VTH X'cv,6
1
0
1
1
VTH x'Y,6
1
1
0
0
VTH X
1
1
0
1
VTH X':Y'6
1
1
1
0
V TH X
'0/1.
1
1
1
1
VTHX
'0/,6
VTHx'o/i.
Use the watchdog timer for software or overall performance safety checks. If the watchdog is enabled, it must
be cleared at regular intervals in program execution to
avoid watchdog interrupts. Intervals are software selectable via the WDM register. Figure a shows the block
diagram for the watchdog timer.
Y16
Bit Address Instructions
¥,.
The following bits may be addressed directly with
certain instructions:
'¥,.
0/,.
• Any bit in the first 16 bytes of memory addressed by
the V register
• Any bit in the five a-bit I/O ports (A, B, C, D, F)
• Any bit in the comparator port
• Any bit in the following special registers: interrupt
mask, serial mode high, timer mode, timer/event
counter output control.
'0/,.
An addressed bit may be tested, set, cleared, orcomplemented. It also may be moved to or from the carry flag.
An addressed bit may be ANDed, ORed, and XORed
with the carry flag.
49-ooo595A
Figure 8.
Watchdog Timer Block Diagram
INTWD
Interval
Control
WDS --+---+-----fS
Q~------------------------------------~
RESET-----~---fR
Notes: 1 CL = 311 [250 ns: 12 MHz operation].
f: System clock frequency [MHz].
49-0005938
4-30
NEe
pPD7S07/0S/09
Absolute Maximum Ratings
DC Characteristics
-----------------------------
TA = -1Q°Cto +70°C; Vee = +5.0V ±10%; Vss=OV; Vee -O.B v'S.
Voo 'S. Vee; TA = -40°C to +B5°C (J,tPD7BOB)
Voo
-0.5 V to +7.0 V
AVee
-0.5 V to +7.0 V
Parameter
Symbol
Input low
voltage
V,L
0
O.B
V
Input high
voltage
V,H1
2.0
Vee
V
V,H2
O.B Vee
Vee
V SCK,X1
V,H3
O.B VOO
Vee
V
RESET
0.45
V
IOL = 2.0 mA
V
IOH = -200pA
Power supply voltages, Vee
-0.5 V to +7.0 V
Input voltage, V,
-0.5 V to +7.0 V
Output voltage, Vo
-0.5 V to +7.0 V
Reference input threshold voltage, VRTH
-0.5 V to Vee +0.1V
Operating temperature, TOPR
10 MHz'S. fXTAL 'S.12 MHz
Limits
fXTAL'S. 10 MHz (fJPD7B07/09)
-40°C to +B5°C
fXTAL'S. 10 MHz (fJPD7B08 only)
Storage temperature, TSTG (fJPD7B07/09)
-40°C to +125 °C
Storage temperature, (fJPD7BOB only)
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Operating Conditions
Oscillating Frequency
Vee. AVec
Output low
voltage
VOL
Output high
voltage
VOH
Typ
Min
Max Unit
2.4
I nput current
Test
Conditions
All except SCK,
RESET, and X1
±200 pA INT1, TI(PC3);
+ 0.45 V 'S. V,N
'S. Vee
III
±10
pA All except
INT1, TI(PC3)
oV 'S.V,N 'S. Vee
Output leakage ILO
current
±10
pA +0.45 V 'S. Vo
'S. Vee
Input leakage
current
VRTH input
current
IRTH
0.2(1)
0.6
mA VRTH = Vee
+5.0 V ± 10%
Voo supply
current
100
1.5(1)
3.5
mA
+5.0 V ± 10%
Vee supply
current
lee
150(1) 220
mA
10 MHz'S. fXTAL 'S. 12 MHz
+5.0 V ±5%
fXTAL'S. 10 MHz
(fJPD7B07/09)
fXTAL'S. 10 MHz
(fJPD7BOB)
Note:
Capacitance
(1) TA = 25°C: Vee = Voo = +5.0 V
Limits
Parameter
Symbol Min
Typ
Max
Unit
Test
Conditions
Capacitance
C,
10
Output
capacitance
Co
20
pF Afe = 1 MHz.
pF Unmeasured
I/O capacitance
CIQ
20
pin returned
pF to 0 V.
Hold Operation
TA =-1Q°C to +70°C; Vee = +5.0V ±10%; Vss= 0 v; Vee -O.B v'S.
Voo 'S. Vee; TA = -40°C to +B5°C (J,tPD7B08)
Limits
Parameter
Symbol
Min
HOLD t setup
time to ALE t
tSHOL
2T +
150
ALE t to
HLDA t delay
tOLHA
HLDA t to bus
floating
tFBHA
HOLD! to
HLDA ! delay
tHOOA
HLDA ! to bus
enable time
tEHAB
Bus setup time tBL
to ALE
Typ
Max Unit
Test
Conditions
ns
T+
150
ns
ns
T - 50
4T +
150
ns
ns
2T 100
ns
4-31
E
NEe
pPD7807/08/09
Comparator Characterisctics
Data Retention Characteristics
TA = -10°C to +70°C; Vee = +5.0 V±10%; Vss =OV; Vee '-:O.S VS
Voo S Vee; TA = -40°C to +S5°C (pPD7S0S)
TA = -10°C to +70°C: Vee = 0 v, VOO = VOOOR: TA = -40°C to
Limits
Parameter
Symbol
Comparison
accuracy
VACOMP
Threshold
voltage
Comparison time
Min
VTH
0
tCOMP
144
VIPT
0
PT input voltage
Typ
+S5°C (pPD7S0S)
Limits
Test
Max Unit Conditions
Parameter
Symbol
Min
±100 mV
Data retention
voltage
VOOOR
3.2
V
Data retention
supply current
IOOOR
VCC
Typ
1.3
Max Unit
Test
Conditions
5.5
V
RESET = VIL
3.0
rnA
RESET = VIL
VOOOR = 3.2 V
145 tCYC
VCC
V
External Clock
TA =-10°Cto +70°C; Vee = +5.0 V±10%; Vss=OV; Vee -O.S VS
VOD:S Vee: TA = -40°C to +S5°C (pPD7S0S)
Limits
Parameter
Symbol
Min
Typ
Test
Max Unit Conditions
High level width
t<1>H
30
250
Low level width
t<1>L
30
250
ns
Rising time
tr
0
30
ns
Falling time
tl
0
30
ns
ns
AC Characteristics
= 0 v, Vee -o.s V S VOO S Vee; See Operating Conditions table
Vss
Limits
'XTAL == 10 MHz
Parameter
Symbol
Min
Max
'XTAL = 12 MHz
Min
Max
Unit
Test
Conditions (1)
Read/Write Operation
RESET pulse width
tRP
6.0
5.0
Interrupt pulse width
tiP
3.6
3.0
Counter input
pulse width
tCI
600
500
tCI
4.8
4.0
Timer input pulse width
tTl
600
500
X1 Input cycle time
tCYC
100
tAL
100
Address set-up to ALE
l
Address hold after ALE
Address to RD
RD
l
l
delay time
l to address floating
Address to data input
Note:
(1) Load capacitance: CL = 150 pF.
4-32
250
83
I-lS
ns
Event counter mode
Pulse width measurement mode
ns
250
65
ns
ns
tLA
70
50
ns
tAR
200
150
ns
tAFR
20
20
ns
tAO
480
360
ns
NEe
j1PD7S07/0S/09
AC Characteristics (cont)
Vss = 0 v, Vee -0.8 V :5 VDD :5 Vee; See Operating Conditions table
Limits
Parameter
Symbol
'XTAl = 10 MHz
'XTAl = 12 MHz
Min
Min
Max
Max
Unit
Test
Conditions (1)
Read/Write Operation
ALE ~ to data input
tLDR
300
215
ns
RD ~ to data input
tRO
250
180
ns
ALE ~ to RD ~ delay time
tLR
50
35
ns
tROH
0
0
ns
Data hold time to RD
RD
t
t to ALE t delay time
RD width low
tRL
150
115
ns
tRR
350
280
ns
Data read
650
530
ns
Opcode fetch
ALE width high
tLL
160
125
ns
M1 setup time to ALE ~
tML
100
65
ns
M1 hold time from ALE ~
tLM
70
50
ns
101M setup time to ALE ~
tiL
100
65
ns
101M hold time from ALE ~
tLi
70
50
ns
Address to WR ~ delay
tAW
200
150
ns
ALE ~ to data output
tLOW
210
195
WR ~ to data output
two
100
100
ALE ~ to WR ~ delay
tLW
50
35
tow
300
230
ns
tWOH
130
95
ns
Data set-up time to WR
Data hold time to WR
WR
t
t
t to ALE t delay time
WR width low
E
ns
ns
ns
tWL
150
115
ns
tww
350
280
ns
Note:
(1) Load capacitance: CL = 150 pF.
4-33
NEe
pPD7S07/0S/09
Serial Operation
See Operating Conditions table
Limits
Parameter
Symbol
SCK cycle time
fXTAL = 10 MHz
fXTAL = 12 MHz
Min
Min
Max
500
SCK width low
SCK width high
SCK input (4)
ns
SCK input (5)
2.4
2
ps
SCK output
500(6)
400(7)
ns
SCK input(4)
200
200
ns
SCK input (5)
1100
900
ns
SCK output
500(6)
400(7)
ns
SCK input (4)
200
200
ns
SCK input (5)
1100
900
ns
SCK output
80
80
ns
(4)
ns
(4)
ns
(4)
t
RxD hold time after SCK t
RxD set-up time to SCK
SCK
ps
500
1.2
tCYK
Test
Conditions
Unit
Max
80
80
l TxD delay time
210
210
Note:
(4) 1x Baud rate in Asynchronous, Synchronous, or I/O Interface mode.
(5) 16x Baud rate or 64x Baud rate in Asynchronous mode.
(6) 505 ns min for pPD7808 only.
(7) 420 ns min for pPD7808 only.
Zero-Cross Characteristics
Limits
Parameter
Symbol
Min
Typ
Max
Zero-cross detection input
Vzx
3(8)
Zero-cross accuracy
AZX
±135
Zero-cross detection input frequency
fZX
Note:
(8) 1.8 VAC p _p max for pPD7808 only.
4-34
0.05
Unit
Test Conditions
mV
60 Hz sine wave
AC coupled
kHz
NEe
pPD7S07/0S/09
Bus Timing Depending on tCYC (cont)
Bus Timing Depending on tCYC
Symbol
Calculating Expression
MinIMax
Calculating Expression
Symbol
MinIMax
tAW
3T -100
Min
Min
tLOW
T + 110
Max
Min
tLW
T - 50
Min
48T
Min
tow
4T -100(4)
Min
tIP
36T
Min
tWOH
2T -70
Min
tAL
2T -100
Min
tWL
2T -50
Min
tLA
T -30
Min
tww
4T - 50(4)
Min
tAR
3T -100
Min
tCYK
tAO
7T - 220(4)
Max
tRP
60T
Min
tTl
6T
tCI(2)
6T
tCI(3)
tLOR
5T - 200(4)
Max
tRO
4T -150(4)
Max
tLR
T -50
Min
tRL
2T -50
Min
4T - 50 (Data Read)(4)
Min
tRR
-.. -......... _----- .. __ . __ ._----_.--- ... _----------------
2T -40
Min
tML
2T -100
Min
tLM
T -30
Min
tiL
2T -100
Min
tLi
T -30
Min
Min
tKKL
6T -100 (SCK input)(1)(5)
----------._-------------------------------12T - 100 (SCK output)
Min
tKKH
6T - 100 (SCK input)(1)(5)
--------.----------- --------_ ... _-_._-----------.-._12T - 100 (SCK output)
Min
Note:
(1) 1x Baud rate in asynchronous, synchronous, or I/O interface
mode.
7T - 50 (Opcode Fetch)(4)
tLL
12T (SCK input)(1)
--------.--------------- -------------------------24T (SCK output)
(2)
(3)
(4)
(5)
T=tCyc= _1_
fXTAL
The items not included in this list are independent of oscillator
frequency (fXTAd.
Event counter mode.
Pulse width measurement mode.
Add 3Twhen using external program memory with programmable
WAIT function.
5T+5 (SCK input)(1) min for JlPD7808 only.
Timing Waveforms
Read Operation
Xl
-
. J.
}
-
K X
ADDRa-ADDRF
,
lAD
.J(IIf/).
ADORa ADDR7
~ILA-
I--- f--I LL -
-
ALE
Dala-in
1_ _
""I:
I-
tLDR
I-tRL
II-IAFR
I----I AL -
~tROH
J
-
V
IRD
RD
I-ILR
Ill.
IRR
IAR
MODEO [iO/M]
[Nolet]
~
I'L-
~IL~-I
Noles: [1] iO/M signal is oulpullo Ihe MODEO pin during a read or wrile of special
regisler[s] Sr-Sr2, if MODEO is pulled up 10 Vee'
49-0005438
4-35
NEe
pPD7S07/0S/09
Timing Waveforms (cont)
Write Operation
T,
T2
T3
Xl
AB,s-AB.~~--~--------------------------~~~~~----------------------------"--"-------
(PF7 -P,F.) ~,'-__,1I=__________-:-_________~----A-D-DR...;.;..--A-DD-R..;.F--------------------------.1 '\__.1'\_______
Data-out
I------tow------~
ALE
~-----------tww-----------~
MODED [iO/M)
[Note 1)
Noles: [1) iO/M signal Is output to the MODED pin during a read or write ofspeclal
reglster[s) Sr-Sr2,11 MODED Is pulled up to Vee.
49·0005448
Opcode Fetch Operation
Xl
AB,s-AB.
(PF 7 -PF.)
-J
).
[(
ALE
~
~
I ROH
Opcode
ADDR.- ADDR 7
I--tLA -
I--tLR
"-
tAR
A
! - - - - tML -
4-36
~tL:.J
M1 81gnalls output to the MODEl pin during opcode letch II MODEl pin
is pulled up to Vee.
-------
I----tRL
~tRo-
RD
MOOEl [M'l)
[Note 1)
---l
t LOR -
_tLL
- IAL-
Notes: (1)
-
ADDR.-ADDRF
tAO
tRR
--
'I
X
NEe
pPD7807/08/09
Timing Waveforms (coni)
Serial Operation Transmit/Rec/eve Timing
TxD
RxD
----~---'1~-----------J~-------------
-------J1~~--------~t'---------------49·0005468
Hold Operation
X1
J
I
ALE
~."')-
IE
\
A
HOLD
t SHDL - -
r-
HLDA
)
~
PF 7 -PF D
PD 7 -PDD
AD, iNA
t FBHA -
-
XTAL Oscillation Circuit
-
- tHDDA -
tEHAB
49·0005498
External Clock Timing
~:B~~~l-t"H-l
O.BV
c
tr
tF
t,bL
tCYC
49·000550A
c
AC Timing Test Points
C
= 10 pF
2.0V
49·0005528
2.4V
0.4SV
=::X:>
O.BV
2.0V
Test Points
384
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
L
I
INTTa
INTT,
I
I
__ _
_
I
_ _ ..J
Internal Bus
Notes: 4'3 =
(1)12
fXTAL X '13
fXTAL X V2
==
4'384 == tXTAL X V384
f XT AL = System Clock
Frequency (MHz)
49-0012178
4-55
t\'EC
pPD78P09
Figure 2.
Timer/Event Counter Block Diagram
INTlo----------I
PC,/CI o--+-+----I~
TO
INTEO
INTEl
INTEIN
49-001226C
Table 3.
Interrupt
Request
IROO
IR01
Interrupt Structure
Interrupt Sources
Interrupt
Address
4
8
Type of Interrupt
Internal/
External
NMI (Nonmaskable interrupt)
Ext
INTWD (Watchdog timer)
Int
INTTO (Coincidence signal from
timer 0)
Int
INTT1 (Coincidence signal from
timer 1)
IR02
16
INT1 (Maskable interrupt)
Ext
INT2 (Maskable interrupt)
IR03
24
INTEO (Coincidence signal from
timer/event counter)
Int
32
IR05
40
INTEIN (Falling signal of CI and
TO counter)
Int/Ext
INTSR (Serial receive interrupt)
Int
INST (Serial send interrupt)
4-56
Standby Function
The standby function saves the top 32 bytes of RAM with
backup power (Voo) if the main power (Vee) fails. On
power up, you can check the standby flag to determine
whether recovery was made from standby mode or from
a cold start.
Universal Serial Interface
INTE1 (Coincidence signal from
timer/event counter)
IR04
There are 11 interrupt sources. Three are external
interrupts and eight are internal. Table 3 shows 11
interrupt sources divided into six priority levels. See
figure 3.
The serial interface can operate in one of three modes:
synchronous, asynchronous, and I/O interface. The
1/0 interface mode transfer~ data MSB first, for easy
interfacing to certain NEG peripheral devices.
Synchronous and asynchronous modes transfer data
LSB first. Synchronous operation offers two modes of
data reception: search and nonsearch. In the search
mode, data is transferred one bit at a time from the
NEe
serial register to the receive buffer. This allows a
software search for a sync character. In the nonsearch
mode, data transfer from the serial register to the
transmit buffer occurs eight bits at a time. In asynchronous mode, the serial interface can act as a fullduplex USART with data transfer rates up to 125 kb/s.
Figure 4 shows the universal serial interface block
diagram.
Zero-Crossing Detector
The INT1 and INT2 terminals (used common to TI and
PC3) can detect the zero-crossing point of lowfrequency AC signals. When driven directly, these pins
respond as a normal digital input. Figure 5 shows the
zero-crossing detection circuitry.
The zero-crossing detection capability allows you to
make the 50-60 Hz power signal the basis for system
timing and to control voltage phase sensitive devices.
pPD78P09
Figure 3.
Interrupt
NMI
INTWD
INTTO
INm
INT1
INT2
INTEO
INTE1
INTEIN
INTSR
INTST
OV
ER
S6
Universal Serial Interface Block Diagram
Figure 4.
To use the zero-cross detection mode, an AC signal of
approximately 1-3 V AC (peak-to-peak) and a maximum
frequency of 1 kHz is coupled through an external
capacitor to the INT1 and INT2 pins.
Forthe INT1 pin, the internal digital state is sensed as a
o until the rising edge crosses the average DC level,
when it becomes a 1 and INT1 interrupt is generated.
Pc,/RxD
For the INT2 pin, the state is sensed as a 1 until the
falling edge crosses the average DC level, when it
becomes a 0 and INT2 interrupt is generated.
PC 2 /SCKo--+--< I--t--
Variable Threshold Input Port [Port T]
PCo/TxDo-----.cn-----------------'
Port T has the following features:
• 8 input lines
• 16 threshold levels from 1/16 to 16/16 of reference
voltage (VRTH)
• Level selected by writing to mode T register
(figure 7)
• Output of comparator port bit reads 0 until voltage at
pin exceeds selected level
• Comparison execution time: 12 /1S
SK 2 • SK,
Noles:
(1)24
= fXTAL X V24
fXTAL X %84
= Crystal Frequency (MHz)
H
30
250
ns
Low level width
tcl>L
30
250
ns
Rising time
tr
0
30
ns
Falling time
tf
0
30
ns
Test
Conditions
Symbol
Min
Data retention
voltage
VOOOR
3.2
Data retention
supply current
IOOOR
Typ
1.3
Max Unit
5.5
V
3.0
mA
t to ALE t delay time
WR width low
ns
tow
230
ns
tWOH
95
ns
tWL
115
ns
tww
280
ns
(1) Load capacitance: CL = 150 pF; fXTAL = 12 MHz (figure 10).
Figure 10.
Data Retention Characteristics
Parameter
WR
tLW
35
Note:
External Crystal Connections
10pF
TA = -10 to +50°C; Vee = 0 V, VDD = VDDDR
limits
ns
Test
Conditions
RESET = VIL
RESET = VIL
VOOOR = 3.2 V
~~+
X1
X2
83-003938A
NEe
pPD78P09
DC Programming Characteristics
Serial Operation
TA =25 ±5°C, Vee = 5 V ±10%, Vpp =21 V±0.5 V, Vss =0 V, Vee
- 0.8 V ~ VDD ~ Vee
Symbol
Input voltage low
Input voltage high
VIL
VIH1
Min
Min
teYK
1.66
ps
SCK input (1)
V
500
ns
SCK input (2)
V
2
ps
SCK output
750
ns
SCK input (1)
SCK, X1
200
ns
SCK input (2)
OV~VI
2.0V
Test Points
0.8 V
<::C
0.8 V
49-000551A
.,-----+_---------:.1.,.....-
PD 7 -PD o
7T - 50 (Opcode Fetch) (4)
tLL
2T -40
tML
2T -100
Min
tLM
T -30
Min
tiL
2T -100
Min
tu
T -30
Min
tAW
3T -100
Min
tLOW
T + 110
Max
tLw
T- 50
Min
Instruction Set
tow
4T -100 (4)
Min
tWOH
2T -70
Min
In addition to the basic 7800 family instruction set, the
pPD78P09 executes the following types of instructions:
tWL
2T -50
Min
tww
4T - 50 (4)
Min
20T (SCK input) (1)
Min
tCYK
-- .. _-_.- ... _-- ... __ ... __ .. -.-. __ ......... _--_ ........... _--
Min
24T (SCK output)
tKKL
10T - 80 (SCK input) (1)
Min
__ • ___ • ______ • • • _ • • __ • • • • __ • • • ____ • • • __ • • • _____ • • • ___ • • - __ 0 .
12T - 100 (SCK output)
tKKH
10T - 80 (SCK input) (1)
Min
---1-2T-~-100-(SCK-~~t-p~i)-----------------
Note:
(1) 1x baud rate in asynchronous, synchronous, or 110 interface
mode_
T = tCYC = 1 fXTALThe items not inciuded in this ii~t are Ifid6p6iident of csc!!!atcr
frequency (fXTAd(2) Event counter mode.
(3) Pulse width measurement mode.
(4) Add 3T when using external program memory with programmable
WAIT function.
4-62
--Programming mode--t----Verify m o d e - -
Note
(1) MODE 0, MODE 1 = low level, PC 7
(2) External Clock Input = 1 MHz
= high level
49'001221A
• 16-bit data transfers between memory, registers,
and extended accumulator
• 16-bit addition and subtraction
• 16-bit comparison and skip
• 16-bit AND, OR, XOR operation
• 16-bit data shift and rotation
• Multiply; 8-bit by 8-bit, 16-bit product (less than 8ps
execution)
• Divide; 16-bit by 8-bit, 16-bit quotient, 8-bit remainder
(less than 15 ps execution)
• Working register instruction for efficient RAM
addressing, testing, and manipulating
• Direct bit addressing for code-efficient addressing,
testing, and manipulating bits in RAM, port lines,
and mode registers.
NEe
pPD78P09
Operand Format/Description
Remarks
Format
1. sr-sr5 (special register)
Description
r
r1
r2
V,A,B,C,D,E,H,L
EAH,EAL,B,C, D, E,H, L
A, B, C
sr
sr2
sr3
sr4
sr5
PA, PB, PC, PD, PF, MKH, MKL, SMH, SML, EOM, ETMM,
TMM, MM, MCC, MA, MB, MC,
MF, TxB, TMo, TM1, WDM, MT
PA, PB, PC, PD, PF, MKH, MKL, SMH, EOM, TMM, RxB,
PT, WDM
PA, PB, PC, PD, PF, MKH, MKL, SMH, EOM, TMM
ETMo, ETM1
ECNT, ECPTO, ECPT1
PA, PB, PC, PD, PF, MKH, MKL, SMH, EOM, TMM, PT
rp
rp1
rp2
rp3
SP, B, D, H
V, B, D, H, EA
SP, B, D, H, EA
B, D, H
rpa
rpa1
rpa2
B, D, H, D +, H +, D -, H B, 0, H
B, D, H, D +, H + , D -, H -, D+ byte, H + A, H + B,
H + EA, H + byte
D, H, D + +, H + +, D + byte, H + A, H + B, H + EA,
H + byte
sr1
rpa3
wa
8-Bit immediate data
word
byte
bit
16-Bit immediate data
8-Bit immediate data
8-Bit address of bit location
NMI, FTO, FT1, F1, F2, FEO, FE1, FEIN, FSR, FST, ER, OV,
IFE2, SB
Instruction Set Symbol Definitions
Symbol
ECNT = Timer/Event
Counter Upcounter
ECPTO = Timer/Event
Counter Capture 0
ECPT1 = Timer/Event
Counter Capture 1
ETMM = Timer/Event
Counter Mode
EOM = Timer/Event
Counter Output Mode
WDM = Watchdog Timer Mode
TxB = Tx Buffer
RxB = Rx Buffer
SMH = Serial Mode High
SML = Serial Mode Low
MKH = Mask High
MKL = Mask Low
2. rp-rp3 (register pair)
SP = Stack Pointer
B = BC
D = DE
H = HL
V=VA
EA = Extended Accumulator
Il
3. rpa-rpa3 (rp addressing)
CY, HC, Z
irf
PA = Port A
PB = Port B
PC = Port C
PD = Port D
PF = Port F
PT = Port T
MA = Mode A
MB = Mode B
MC = Mode C
MCC = Mode Control C
MF = Mode F
MT = Mode T
MM = Memory Mapping
TMo = Timer Register 0
TM1 = Timer Register 1
TMM = Timer Mode
ETMo = Timer/Event
Counter Register 0
ETM1 = Timer/Event Counter
Register 1
B = (BC)
D = (DE)
H = (HL)
D + = (DE) + 1
H + = (HL) + 1
D -= (DE)-1
H - = (HL)-1
D+ + = (DE) + 2
H + + = (HL) + 2
D + byte = (DE) + byte
H +A = (HL) + (A)
H + B = (HL) + (B)
H + EA = (HL) + (EA)
H + byte = (HL) + byte
4. f (flag)
Description
CY = Carry
Transfer direction, result
5. irf (interrupt flag)
A
Logical product (logical AND)
V
Logical sum (logical OR)
.Jf
Exclusive OR
NMI = NMI input
FTO = INTFTO
FT1 = INTFT1
F1 = INTF1
F2 = INTF2
FEO = INTFEO
FE1 = INTFE1
Complement
Concatenation
HC = Half Carry
Z = Zero
FEIN = INTFEIN
FSR = INTFSR
FST = INTFST
ER = Error
OV = Overflow
IE2 = Interrupt Enable F/F2
SB = Standby
4-63
.J:o.
I
0>
.J:o.
Instruction Se~t
81
82
-
Mnemonic
MVI
Operation
Operand
B-Bit Data Transfer
MOV
rl,A
A, r1
6
5
0
0
0
0
0
0
1
0
(A) -
(r1)
(sr)-(A)
(A)-(sr1)
(r)-(word)
0
0
0
word,r
(word) -
0
(r)
(r) -byte
set L1 if r = A
set LO if r = L
sr2,byte (sr2) - byte
*r,byte
*wa, bytE' ((V)e(wa)) -
MVIX
STAW
LDAW
STAX
LDAX
EXX
*rpa1,bytl~
EXA
EXH
EXR
1
2
0
T2 T1 To
T2 T1 TO
7
6
5
B4
4 3
2
1
0
State,l )
Bytes
Skip
Condition
0
(r1)-(A)
MVIW
byte
(rpa1) - byte
((V)e(wa)) - A
(A) - ((V)e(wa))
(rpa2) - (A)
(A) - ((rpa2))
(B) .... (B'),(C) .... (C').(D) .... (D')
(E) - (E'),(H) .... (H'),(L) .... (L')
(V) .... (V'),(A) .... (A'),(EA) .... (EA')
(H) - (H'),(L) .... (L')
(V) .... (V'),(A) - (A'),(B) - (B');
(C) - (C') (D) - (D') (E) .... (E'),(H)
.... (H'),(L) - (L'),(EA) - (EA')
16-Bit Data Transfer
BLOCK
D+
DMOV
7
B3
4 3
*sr,A
*A,sr1
r,word
*wa
*wa
*rpa2
rpa2
,.a
,.CiI
1:::
Operation Code
((DE)) - ((HL)),(DE) - (DE) + 1,
(HL) - (HL) + 1, (C) - (C)-1
End if borrow
D((DE)) - ((HL)),(DE) - (DE) + 1,
(HL) - (HL) -1, (C) - (C)-1
End if borrow
rp3, EA (rp3d - (EAL),(rp3H) - (EAH)
EA,rp3 (EAL) - (rp3d,(EAH) - (rp3H)
III
0
0
0
1
1
0 1
1 1 0 0
0 0 0 0
Lowaddr
1 0 0 0 0
Lowaddr
0 1 R2 R1 Ro
0
0
0
0
0
0 0 0
Data
0 1 o A1 Ao
0 0 0 1 1
0 0 0 0
1
A2 A1 Ao
0
A2 A1 Ao
0
0 0 0
1
1
0
0
1
0
A3 0
A3 0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S5 S4 S3
S5 S4 S3
1 0 1
High addr
1 1 1
High addr
Data
1
0
0
S3
0
0
0
0
0
1
0
0
0
0
S2 S1 So
S2 S1 So
R2 R1 Ro
10
10
17
2
2
4
R2 R1 Ro
17
4
7
2
14
3
13
3
10
10
10
7/13(3)
7/13(3)
8
2
2
2
2
2
2
8
8
8
2
2
2
0 o S2 S1 So
Data
Offset
Data
Offset
Offset
Data (2)
Data (2)
0
1
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
13 x
(C+1)
0
0
0
1
0
0
0
1
13 x
(C+ 1)
1
0
0
0
0
P1 Po
P1 Po
G
4
4
4
4
L1 = 1 and r = A
LO = 1 and r = L
;(
~
Instruction Set (cont)
Operation Code
Bl
B2
-
Operation
7
16-Bit Data Transfer (cont)
DMOV
sr3, EA (sr3) - (EA)
EA,sr4 (EA) - (sr4)
SBCD
word (word) - (C), (word + 1) -
(B)
0
0
0
SDED
(D)
0
Mnemonic
Operand
word
(word) -
(E), (word + 1) -
SHLD
word
(word) -
(L), (word + 1) -
SSPD
word
(word) -
(SPd,(word + 1) -
STEAX
rpa3
((rpa3)) -
LBCD
word
(C) -
(H)
(word),(B)
+-
(EAH)
(word + 1)
0
(E)
+-
(word),(D)
+-
(word + 1)
0
LHLD
word
(L)
+-
(word),(H)
+-
(word + 1)
0
LSPD
word
(SPL)
+-
(word),(SPH)
+-
LDEAX
rpa3
(EAL)
PUSH
rp1
((SP) -1) - (rp1H) ((SP) - 2) (SP) +- (SP) - 2
POP
rp1
LXI
+-
((rpa3)),(EAH)
((word) + 1)
(rp1d - ((SP)),(rp1H)
(SP) - (SP) + 2
*rp2,word (rp2) +- (word)
set LO if rp2 = H
+-
+-
((rpa3) + 1)
0
((SP) + 1)
(C) +- ((PC)+3+(A)),B +- ((PC)+3+(A)+ 1)
TABLE
8-Bit Arithmetic (Register)
A,r
(A)-(A)+(r)
ADD
(r)-(r)+(A)
r,A
(A) +- (A) + (r) + (CY)
ADC
A,r
r,A
(r) +- (r) + (A) + (CY)
0
1
0
7
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Lowaddr
1 0 0
Lowaddr
1 0 0
Lowaddr
1 0 0
Lowaddr
0 0 1 0
Data(4)
0
(rp1d
0
1
1 0 0
Lowaddr
0 0 1 0
Data(4)
0 0
0
word
0
0
6
2
Lowaddr
1 0 0
Lowaddr
0
LDED
5
0 0
Lowaddr
1 0 0
0
(SPH)
(EAL),((rpa3)) + 1 -
6
B3
4 3
0
5
B4
4 3
0 1
0 0
0
High
1 0
High
1 1
High
0 0
High
0 1
0
0
2
1
0
Bytes
Uo
0 V1 Vo
1 0
14
2
14
20
2
4
0
20
4
0
20
4
0
20
4
14/20(3)
3
20
4
20
4
20
4
20
4
14/20(3)
3
0
addr
1
addr
1
addr
1
addr
C3 C2 C1 Co
0
0
0
0
0
0
0
0
0
0
0
0
0
High addr
1 0 1
High addr
1 1 1
High addr
0 0 1
0
High addr
0 0 C3 C2 C1 Co
0
State(l)
0
1
0 02 01 00
13
0
0
0 02 01 00
10
0 P2 P1 Po 0
High byte
0
0 0 1 0
0
0
0
0
0
0
0
0
0
0
0
0
Low byte
0
0
0
0
10
3
17
2
8
8
8
8
2
Skip
Condition
~~
LO = 1 and
rp2= H
1:::
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
~
I
0
0 R2 R1 RO
0 R2 R1 Ro
0 R2 R1 Ro
0 R2 R1 RO'
2
2
2
"at
"
D
0
G
(J)
0'1
I!I
~
en
1:::
Instruction Set (cont)
0)
"a
Operation Code
Mnemonic
Operand
Operation
8-Bit Arithmetic [Register] (cont)
ADDNC·
A,r
(A) - (A) + (r)
r,A
(r)-(r)+(A)
SUB
A,r
(A) - (A) - (r)
r,A
(r)-(r)-(A)
SBB
A,r
(A) - (A) - (r) - (CY)
r,A
(r) - (r) ~ (A) - (CY)
SUBNB
A,r
(A) - (A) - (r)
r,A
(r)-(r)-(A)
ANA
A,r
(A) - (A) 1\ (r)
r,A
(r) - (r) 1\ (A)
ORA
A,r
(A) - (A) V (r)
r,A
(r)-(r)V(A)
XRA
A,r
(A) - (A) -'o'-(r)
r,A
(r) - (r)-'o'-(A)
GTA
A,r
(A) - (r) - 1
r,A
(r)-(A)-1
LTA
A,r
(A) - (r)
r,A
(r)- (A)
NEA
A,r
(A) - (r)
r,A
(r)-(A)
EQA
A,r
(A) - (r)
r,A
(r)-(A)
ONA
A,r
(A) 1\ (r)
OFFA
A,r
(A) 1\ (r)
8-Bit Arithmetic (Memory)
ADDX
rpa
(A) - (A) + ((rpa))
ADCX
rpa
(A) - (A) + ((rpa)) + (CY)
ADDNCX
rpa
(A) - (A) + ((rpa))
SUBX
rpa
(A) - (A) - ((rpa))
SBBX
rpa
(A) - (A) - ((rpa)) - (CY)
SUBNBX
rpa
(A) - (A) - ((rpa))
ANAX
rpa
(A) - (A) 1\ ((rpa))
ORAX
rpa
(A) - (A) V ((rpa))
iii
7
654
01
o 1
o
o
o
o
o
o
o
1
1
1
1
1
1
1
B1
B2
~
B4
3
2
0
7
6
5
4
3
2
00000
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0
0 0
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
R2
R2
R2
R2
R1
R1
R1
R1
Ro
Ro
Ro
Ro
8
8
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
8
0
0
o
1
0
1
00000
o 1 1 0 0 0 0
o 1 1 0 0 0 0
o
o
o
o
o
o
o
o
o
o
o
o
o
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
o
o
0
0
o
0
0
o
o
1
o
0
0
0
0
0
0
o
o
1
o
0
0
0
o
o
1
1
1
1
1
0
o
000
1
o
o
o
o
0
0
0
01110000
01110000
01110000
01110000
01110000
o 1 1 1 0 0 0
1 0 0 0
01110000
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1 ~ ~
1 R2 R1
1 R2 R1
1 R2 R1
1 R2 R1
o
o
0
0
1
1
1
1
0
0
1
1
1 ~ ~ ~
State(l)
8
8
8
8
8
8
8
8
8
8
8
8
~
8
Ro
Ro
Ro
Ro
8
0
1
1 R2 R1 Ro
1R2 R1 Ro
8
8
0
1
0
0
1
1
0
1
0
0
0
0
0
0
1
1
A2
A2
A2
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
A1
A1
A1
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
8
8
8
Bytes
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
11
2
11
2
11
11
11
11
11
11
2
2
2
2
2
Skip
Condition
No carry
No carry
CD
--o
"
CD
No borrow
No borrow
No borrow
No borrow
Borrow
Borrow
No zero
No zero
Zero
Zero
No zero
Zero
No carry
No borrow
~
~
Instruction Set (cont)
Operation Code
-
Mnemonic
Operand
Operation
8-Bit Arithmetic (Memory) (cont)
(A) ;,- (A)..IJ-((rpa))
XRAX
rpa
GTAX
rpa
LTAX
rpa
NEAX
rpa
EQAX
rpa
ON AX
rpa
OFFAX
rpa
Immediate Data
ADI
*A,byte
r,byte
(A) - ((rpa))-1
(A)- ((rpa))
(A)- ((rpa))
(A) - ((rpa))
(A) /\ ((rpa))
(A) /\ ((rpa))
0
0
0
0
0
0
0
(A) - (A) + byte
(r) - (r) + byte
0
sr2, byte (sr2) ACI
SBI
+ byte
(sr2) + byte + (CY)
*A,byte (A) - (A) + byte
r,byte (r) - (r) + byte
sr2,byte (sr2) -
SUI
(sr2)
*A,byte (A) - (A) + byte + (CY)
r,byte (r) - (r) + byte + (CY)
sr2,byte (sr2) -
ADINC
7
(sr2) + byte
sr2,byte (sr2) -
0
*A,byte (A) - (A) - byte - (CY)
r;byte (r) - (r) - byte - (CY)
0
sr2,byte (sr2) -
0
B2
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Data
0 0
Data
0 0
1 0
Data
0 0
Data
0 0
0
Data
0 0
Data
1 0
1 0
Data
0 0
Data
B4
4 3
State(1)
Bytes
Skip
Condition
2
1
0
A2
A2
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
A1
A1
Ao
Ao
Ao
Ao
Ao
Ao
Ao
11
11
11
11
11
11
11
Data
0 0 R2 R1 Ro
7
2
0
11
3
S3
0
0
0 S2 S1 So
20
3
0
Data
1 0 R2 R1 Ro
7
0
11
2
3
0
S3
0
0 S2 S1 So
20
3
1
0
2
0
Data
0 0 R2 R1 Ro
7
0
11
3
No carry
No carry
0
S3
0
0 S2 S1 So
20
3
No carry
Data
0 R2 R1 Ro
11
3
3
0
7
6
5
0
0
0
0
0
0
o
0
1
0
1
0
0
0
1
0
0
0
0
0
Data
0 0
Data
1 0
0
0
0
0
(sr2) - byte - (CY)
0
0
0
0
5
B3
4 3
0
0
0
0
0
0
0
0
*A,byte (A) - (A) - byte
r,byte (r) - (r) - byte
(sr2) - byte
6
B1
0
0
0
2
2
2
2
2
~~
No borrow
Borrow
No zero
Zero
No zero
Zero
7
0
S3
0 S2 S1 So
20
2
0
Data
1 0 R2 R1 Ro
7
0
11
3
0
S3
0 S2 S1 So
20
3
1:::
"D~
"
~
0
CD
I
0>
-../
II
~
I
0>
Instruction Set (cont)
"t:
(X)
Operation Code
12
11
n
7
6
Immediate Data (cont)
SUINB
*A,byte (A) +- (A) - byte
r,byte (r) +- (r) - byte
o
o
0
1
sr2,byte (sr2)
o
Mnemonic
ANI
ORI
Operand
6TI
LTI
NEI
+-
(sr2) - byte
*A,byte (A) +- (A) A byte
r,byte (r) +- (r) A byte
o
o
sr2,byte (sr2)
o
+-
(sr2) A byte
*A,byte (A) +- (A) V byte
r,byte (r) +- (r) V byte
sr2,byte (sr2)
XRI
Operation
+-
(sr2) V byte
o
o
o
o
sr2,byte (sr2)
o
(sr2)-\l-byte
*A,byte (A) - byte-1
r,byte (r) - byte-1
o
o
srS,byte (srS) - byte - 1
o
4
3
0
0
Data
o
0
1
0
1
o
0
0
1
1
0
B4
076543210
2
0
o
o
0
S3 0
0
1
3
No borrow
2
o
S3 0
0
0
20
3
o
0
0
Data
1 1 R2 R1
7
o
S3 0
0
S2 S1 So
Ro
11
2
3
0
S2 S1 So
20
3
Data
1 0 R2 R1 Ro
7
11
2
3
S2 S1 So
20
3
1
0
o
0
o
0
0
o
0
S3 0
0
1
o
1
0
o
0
o
Data
1 R2 R1 Ro
7
11
2
3
No borrow
No borrow
S2 S1 So
14
3
No borrow
1 R2 R1 Ro
7
11
2
3
Borrow
Borrow
S2 S1 So
14
3
Borrow
1 R2 R1 Ro
7
11
2
3
No zero
No zero
o
1
0
o
1
Data
0
Data
o
0
S3 0
o
20
3
1
o
o
S2 S1 So
7
o
*A,byte (A) - byte
r,byte (r) - byte
o
11
1 0
o
No borrow
No borrow
Data
0 1 R2 R1 Ro
o
o
2
3
0
S3 0
srS,byte (srS) - byte
7
0
o
Skip
Condition
11
o
0
o
o
Bytes
o
o
0
State(l)
0 R2 R1 Ro
Data
o
Data
1 0
*A,byte (A) - byte
r,byte (r) - byte
III
0
Data
1 0
1 0
Data
o 0
Data
o 0
1 0
Data
o
0
0
Data
000
1 1 0
Data
o 0
Data
0 1 0
1 1 0
Data
o
*A,byte (A) +- (A)-\l-byte
r,byte (r) +- (r)-\l-byte
+-
5
0
1
1
1 0
Data
o
0
Data
0
Data
o
1
o
"~a
"o
C)
~
,~
Instruction Set (cont)
Operation Code
-
Mnemonic
Operand
Operation
Immediate Data (cont)
NEI
sr5,byte (sr5) - byte
7
6
5
0
B1
B3
4
3
0
0
B2
B4
2
1
0
7
6
5
4
3
2
1
0
State(l)
Bytes
Skip
Condition
S2 S1 So
14
3
No zero
7
11
2
3
Zero
1 R2 R1 Ro
S2 S1 So
14
3
Zero
1 R2 R1 Ro
7
11
2
3
No zero
0
0
S2 S1 So
14
3
No zero
1 R2 R1 Ro
7
11
2
3
Zero
Zero
S2 S1 So
14
3
Zero
0
0
0
0
14
3
0
0
0
0
14
3
0
0
0
0
14
3
0
0
0
0
14
3
0
0
0
0
14
3
0
0
0
0
14
3
0
0
0
14
3
0
S3
0
0
0
1
0
S3
1
0
0
0
S3
~~
Data
EOI
*A,byte (A) - byte
r,byte
0
0
(r) - byte
1
1
0
0
Data
Zero
Data
sr5,byte (sr5) - byte
0
0
0
Data
ONI
*A,byte (A) A byte
r,byte
0
0
(r) A byte
0
0
0
0
1
Data
0
No zero
Data
sr5,byte (sr5) A byte
0
0
0
Data
OFFI
*A,byte (A) A byte
r,byte
0
0
(r) A byte
0
1
1
0
0
Data
0
0
S3
0
1
Data
sr5,byte (sr5) A byte
0
0
0
0
Data
Working Register
ADDW
wa
(A)
+-
(A)
+ ((V)e(wa))
0
1
0
0
0
0
0
0
Offset
ADCW
wa
(A)
+-
(A)
+ ((V)e(wa)) + (CY)
0
1
0
Offset
ADDNCW
wa
(A)
+-
(A)
+ ((V)e(wa))
0
1
0
0
0
0
0
0
No carry
Offset
SUBW
wa
(A)
+-
(A) - ((V)e(wa))
0
1
0
Offset
SBBW
wa
(A)
+-
(A) - ((V)e(wa)) - (CY)
0
1
0
0
Offset
SUBNBW
wa
(A)
+-
(A) - ((V)e(wa))
0
1
0
0
0
0
Offset
ANAW
wa
(A)
+-
(A) A ((V)e(wa))
0
1
0
0
0
Offset
0
0
No borrow
1:::
"ata
"
~
0
I
en
CD
<0
II
~
~
Instruction Set (cont)
1:::
0
Operation Code
81
Mnemonic
Operand
Operation
7
Working Register (contI
ORAW
wa
(A) -
(A) V ((V)e(wa))
0
XRAW
wa
(A) -
(A)-'f((V)e(wa))
0
GTAW
wa
(A) - ((V)e(wa)) - 1
0
LTAW
wa
(A) - ((V)e(wa))
0
NEAW
wa
(A) - ((V)e(wa))
0
EQAW
wa
(A) - ((V)e(wa))
0
ONAW
wa
(A) A ((V)e(wa))
0
OFFAW
wa
(A) A ((V)e(wa))
0
ANIW
*wa,byte ((V)e(wa)) -
((V)e(wa)) A byte
ORIW
*wa,byte ((V)e(wa))
GTIW
*wa,byte ((V)e(wa)) - byte - 1
+-
((V)e(wa)) V byte
0
6
5
B3
4 3
0
Offset
1 0
Offset
1 0
Offset
1 0
Offset
1 0
Offset
1 0
Offset
1 0
Offset
1 0
Offset
0
0
0
0
Data
1 0
Data
0
82
2
6
5
B4
4 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
7
0
0
0
0
0
0
0
0
0
0
0
0
State(1)
Bytes
Skip
Condition
2
1
0
0
0
14
3
0
14
3
14
3
No borrow
0
0
0
14
3
Borrow
0
0
0
0
14
3
No zero
0
0
0
0
14
3
Zero
0
0
0
0
14
3
No zero
0
0
0
0
14
3
Zero
Offset
19
3
Offset
19
3
0
0
0
0
0
0
0
0
Offset
13
3
No borrow
0
Data
1 0
Data
0
Offset
13
3
Borrow
LTIW
*wa,byte ((V)e(wa)) - byte
0
NEIW
*wa,byte ((V)e(wa)) - byte
0
0
0
0
Offset
13
3
No zero
0
Offset
13
3
Zero
EQIW
*wa,byte ((V)e(wa)) - byte
0
Data
1 0
Data
ONIW
*wa,byte ((V)e(wa)) A byte
0
0
0
0
Offset
13
3
No zero
0
Data
1 0
Data
0
Offset
13
3
Zero
OFFIW
*wa,byte ((V)e(wa)) A byte
III
"
0
CD
0
0
"a1a
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operand
16-Bit Arithmetic
EADD
EA,r2
DADD
EA,rp3
DADC
EA,rp3
DADDNC
EA,rp3
ESUB
EA,r2
DSUB
EA,rp3
DSBB
EA,rp3
DSUBNB
EA,rp3
DAN
EA,rp3
DOR
EA,rp3
DXR
EA,rp3
DGT
EA,rp3
DLT
EA,rp3
DNE
EA,rp3
DEQ
EA,rp3
DON
EA,rp3
DOFF
EA,rp3
Multiply/Divide
MUL
r2
DIV
r2
Increment/Decrement
INR
r2
INRW
·wa
INX
rp
EA
DCR
r2
DCRW
wa
DCX
rp
EA
Others
f"
:i
765
Operation
(EA) -
(EA)
+ (r2)
(EA) -
(EA)
+ (rp3)
(EA) -
(EA)
+ (rp3) + (CY)
+ (rp3)
(EA)
(EA) - (r2)
(EA) -
(EA) - (rp3)
(EA) -
(EA) - (rp3) - (CY)
(EA) -
(EA) - (rp3)
(EA) -
(EA) A (rp3)
(EA) -
(EA) V (rp3)
o
o
o
o
1
000
o 1 0
01 0
o 1 0
000
o 1 0
0 1 0
(EA) - (rp3)
(EA) - (rp3)
(EA) - (rp3)
(EA) A (rp3)
o
o
o
o
1
(r2) -
(r2)
+1
((V)e(wa)) (rp) (EA) (r2) -
(rp)
((V)e(wa))
+1
+1
(EA)
+1
(r2) - 1
((V)e(wa)) -- ((V)e(wa)) -1
(rp) -
(rp) - 1
(EA) -
(EA) - 1
DAA
Decimal Adjust Accumulator
STC
(CY)-1
CLC
(CY)-O
CMC
(CY) -- (CY)
4
320
o
0
0
0 R1 Ro
o
0
1 P1
1
0
0
0
1 P1 Po
1 P1 Po
0 R1 Ro
0
1 P1 Po
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
o
0
0
0
o
o
o
1
o
o
o
o
o
o
o
1 0 0 0
0 1 0 0
0 P1 Po 0
0 1 0 1
1 0 1 0
0 1 1 0
0 P1 Po 0
0 1 0 1
0 R1 Ro
0 0 0
0 1 0
0 0 0
0 R1 Ro
0 0 0
0 1
0 0
o
o
o
o
1
1
1
1
0
5
o
0
0
0
1
0
0
0
1
o
Remainder
0
0
0
6
o
000
0 0 0
1
1
o
(EA) -;- (r2), (r2) -
o
7
0
0
0
1
1
1
x (r2)
(A)
(EA) -
0
o
o
o
1
1
1
(EA) A (rp3)
(EA) -
2
o
o
o
o
o
o
o
o
o
o
o
o
o
o
(EA) - (EA) V (rp3)
(EA) - (rp3) - 1
B4
3
o
(EA) -
B2
~
4
o
(EA) -
B1
0
0
0
0
0
0
0
1 0 000
001 000
001 0 0
001 000
1
1
0
0
0
1
1
1
1
0
1
1
0
1
o
o
o
o
o
0
0
1
0
1
Po
State(l)
11
11
2
11
2
11
11
11
2
2
P1
Po
11
P1
Po
P1
Po
P1
Po
P1
Po
P1 Po
11
11
11
11
11
P1
Po
11
P1
Po
11
P1
Po
11
P1
Po
P1 Po
11
11
R1 Ro
32
1 R1 Ro
59
o
4
16
7
7
4
16
7
7
Offset
Offset
Bytes
o
I!!I
0
1
8
0
o
No carry
2
2
2
2
No borrow
2
2
2
2
2
2
2
2
No borrow
Borrow
No zero
Zero
No zero
Zero ~
2
2
Carry
2
Carry
1
Borrow
2
Borrow
1:::
"
D
~
0
1
1
~
~
2
4
o
o
o
Skip
Condition
2
2
,.o
CD
U)
.;..
I
......
,.a
1::
Instruction Set (cont)
N
Operation Code
Mnemonic
Operand
Others (contI
NEGA
Rotate and Shift
RLO
RRO
RLL
r2
RLR
r2
SLL
SLR
SLLC
SLRC
ORLL
r2
r2
r2
r2
EA
ORLR
EA
OSLL
EA
OSLR
EA
Jump
JMP
7
4
3
2
0
7
654
3
2
o
o
o
o
0
0
0
0
000
000
000
o
o
0
0
1
0
001
o
001
000
o
0
0
1 001 000
01001000
1 001 000
o 1 001 000
01001000
o
o
o
o
o
1
001
000
101
o
1
001
o
1
001
o
1
0
o
0
Rotate left digit
Rotate right digit
(r2m + 1) +- (r2 m), (r2o) - (CY),
(CY) - (r27)
(r2m -1) +- (r2m),(r27) - (CY),
(CY) +- (r2o)
(r2m+ 1) - (r2m),(r20) +- 0, (CY) +- (r27)
(r2m - 1) +- (r2m),(r27) +- 0, (CY) +- (r20)
(r2m + 1) +- (r2 m),(r20) +- 0, (CY) +- (r27)
(r2m - 1) - (r2m),(r27) -- 0, (CY) +- (r2o)
(EAn + 1) +- (EAn),(EAO) +- (CY),
(CY) +- (EA1S)
(EAn - 1) +- (EA n),(EA1S) +- (CY),
(CY) +- (EAO)
(EAn + 1) +- (EAn),(EAO) +- 0,
(CY) +- (EA1S)
(EAn - 1) +- (EA n),(EA1S) +- 0,
(CY) +- (EAO)
o
o
o
*word
(PC)
word
*word
(PCH) +- (B),(PCLl- (C)
(PC) +- (PC) + 1 + jdisp 1
(PC) +- (PC) + 2 + jdisp
(PC) +-(EA)
word
5
000
o
+-
6
82
B4
o
(A) +- (A) + 1
JB
JR
JRE
JEA
Operation
81
n
o
o
o
o
1
2
1 R1 Ro
17
17
8
2
2
2
0 R1 Ro
8
2
0 1 0 0 1 R1 Ro
0 1 0 0 0 R1 Ro
0 0 0 0 1 R1 Ro
0 0 0 0 0 R1 RO
0110100
8
8
8
8
8
2
2
2
2
2
0
8
2
000
10100100
8
2
000
101
8
2
Lowaddr
10
3
jdisp
00101000
10
10
8
2
2
Lowaddr
16
3
00101001
17
2
fa
13
2
o
1
1
Bytes
8
o
o
o
State(l)
1 0 1 0 0
High addr
1 00 0 0 1
jdisp1
0 0 1 1 1
001 000
000
1
1
1
0
0
0
0
0
0
0
0
1
0
Skip
Condition
""-II
CD
,.o
CD
Carry
Carry
4
Call
CALL
*word
CALB
CALF
*word
«SP) -1) +- «PC) + 3)H,
«SP) - 2) +- «PC) + 3)l
(PC) +- word, (SP) +- (SP) - 2
01000000
High addr
«SP) -1) +- «PC) + 2)H,
«SP) - 2) +- «PC) + 2) l
(PCH) + - (B),(PCLl+- (C),
(SP) +- (SP) - 2
o
1
001
«SP) - 1) +- «PC) + 2)H,
"«SP) - 2) +- «PC) + 2)l
(PC1S-11) +- 00001,
(PC1O-0) +- fa, (SP) +- (SP) - 2
o
1
1
III
1
000
1 +-
~
~
Instruction Set (cont)
Operation Code
BI
Mnemonic
Operand
Operation
7
6
5
B2
B3
4 3
2
I
0
7
6
5
B4
4 3
2
I
0
Statell)
Bytes
Skip
Condition
Calileont)
CALT
word
SOFT!
((SP) - 1) - ((PC) + 1)H,
((SP) - 2) - ((PC) + 1) L
(PCLl - (128 + 2ta),(PCH) (129 + 2ta),(SP) - (SP) - 2
((SP) -1) - (PSW),((SP) - 2) ((PC) + 1)H,((SP) - 3) - ((PC) + 1)L,
(PC) - 0060H,(SP) - (SP) - 3
ta
0
0
1
1
1
0
1
1
0
16
0
1
0
16
0
0
0
10
0
0
~
~
Return
(PCLl- ((SP)),(PCH) - ((SP) + 1)
(SP) - (SP) + 2
(PCLl- ((SP)),(PCH) - ((SP) + 1)
(SP) - (SP) + 2,(PC) - (PC) + n
(PCLl - ((SP)),(PCH) - ((SP) + 1)
(PSW) - ((SP) + 2), (SP) - (SP) + 3
RET
RETS
RETI
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
1
10
Unconditional
Skip
13
0
Bit Manipulation
MOV
AND
OR
XOR
SETB
*CY, bit (CY) - (bit)
*bit CY (bit)-(CY)
*CY,bit (CY) - (CY) A (bit)
SK
*CY, bit
*CY, bit
*bit
*bit
*bit
*bit
SKN
*bit
CLR
NOT
(CY) - (CY) V bit
(CY) - (CY)Jf(bit)
(bit)-1
(bit)-O
(bit)-(bit)
Skip if (bit) = 1
Skip if (bit) = 0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
Bit Addr
Bit Addr
Bit Addr
Bit Addr
Bit Addr
Bit Addr
10
13
10
Bit Addr
BitAddr
BitAddr
Bit Addr
13
13
10
10
10
13
10
2
2
2
2
2
2
2
2
2
2
(bit) = 1
(bit) =0
1::::
".....D
"o
CD
~
I
......
CD
U)
~
.j::.
I
--...I
Instruction Set (cont)
1:::
.j::.
Operation Code
B1
Mnemonic
Operand
Operation
7
Skip iff= 1
Skip if f = 0
Skip if irf = 1, then reset irf
Skip if irf = 0
Reset irf if irf = 1
No operation
Enable interrupt
msable interrupt
Halt
0
0
0
0
6
5
B3
4 3
0
0
0
0
-
2
0
7
6
5
0
0
0
0
0
0
0
0
0
B4
4 3
2
0
0
F2 F1
FO
F2 F1
FO
10
10
State(1)
Bytes
Skip
Condition
CPU Control
SK
SKN
SKIT
SKNIT
NOP
EI
DI
HLT
"m
D
B2
""-I
"
0
irf
irf
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
14
13
12
11
14
13
12
11
0
0
8
8
8
8
2
2
2
2
4
4
4
11
1
2
f= 1
f=O
irf=1
irf=O
CD
Note:
(1) In the case of skip condition, the idle states are as follows:
1-byte instruction: 4 states
2-byte instruction (with *): 7 states
2-byte instruction: 8 states
3-byte instruction (with *): 10 states
3-byte instruction: 11 states
4-byte instruction: 14 states
(2) 82 (Data): rpa2 = D + byte, H
+ byte.
(3) Right side of slash (/) in states indicates case rpa2, rpa3 = D
H + EA, H + byte.
(4) 83 (Data): rpa3 = D + byte, H
+ byte, H + A, H + 8,
+ byte
~
~
Ii I
NEe
NEe Electronics Inc.
Description
pPD7810/11
8-BIT, SINGLE-CHIP
NMOS MICROCOMPUTERS
WITH AID CONVERTER
Pin Configuration
The IlPD7810 and IlPD7811 single-chip microcomputers integrate sophisticated on-chip peripheral
functionality normally provided by external components. The device's internal 16-bit ALU and data paths,
combined with a powerful instruction set and addressing, make the IlPD7810/11 appropriate in data
processing as well as control applications. The devices
integrate a 16-bit ALU, 4K-ROM, 256-byte RAM with an
8-channel AID converter, a multifunction 16-bit timerl
event counter, two 8-bit timers, a USART, and two
zero-cross detect inputs on a single die, allowing their
use in fast, high end processing applications. This
involves analog signal interface and processing.
PAo
Vee
PA,
Voo
PA.
P0 7
PA 3
PD.
PA.
PO s
PAs
PD.
PAs
P0 3
PA7
PD.
PB o
PO,
POo
PF7
PB 3
PF.
PF s
PBs
The IlPD7811 is the mask-ROM high volume production device embedded with custom customer
program. The IlPD7810 is a ROM-less version for
prototypi ng and small volume production. The
IlPD78PG 11 E is a piggy-back EPROM version for
design development.
PB 7
PF.
PF,
PF o
ALE
Features
PC 3
WR
PC.
AD
PC s
AVee
PC.
V AREF
PC 7
NMI
D NMOS silicon gate technology requiring +5 V power
supply
o Complete single-chip microcomputer
- 16-bit ALU
- 4K x 8 ROM
- 256-byte RAM
o 44 I/O lines
o Two zero-cross detect inputs
D Two 8-bit timers
D Expansion capabilities
- 8085A bus-compatible
- 60K-byte external memory address range
o 8-channel, 8-bit AID converter
- Autoscan mode
- Channel select mode
D Full duplex USART
- Synchronous and asynchronous
o 153 instructions
- 16-bit arithmetic, multiply and divide
D 11ls instruction cycle time (12 MHz operation)
D Prioritized interrupt structure
- 3 external
- 8 internal
D Standby function
o On-chip clock generator
o 64-pin plastic QUIP or shrink DIP
INT1
ANs
MOOE1
AN.
RESET
AN3
MOOED
AN.
AN,
ANo
Vss
AVss
49-000601 A
Ordering Information
Part Number
Package Type
Max Frequency
of Operation
jlPD7810G-36
jlPD7811 G-36
64-pin plastic QUIP
12 MHz
jlPD7810CW
jlPD7811CW
64-pin plastic shrink DIP
12 MHz
4-75
NEe
pPD7810/11
Pin Identification
No.
1-8
Symbol
PAo-PA7
PCO·PC7 [Port C]
function
Port A 1/0
9-16
PBO-PB7
Port B 1/0
17
PCO/TxD
Port CliO line OlTransmit data output
Port C is an 8-bit three-state port. Each bit is independently programmable as either input or output.
Alternatively, the lines of port C can be used as control
lines for the USART and timer. Reset puts all lines of
port C in port mode, input.
18
PC1/RxD
Port CliO line 1/Receive data input
19
PC2/SCK
Port CliO line 2/Serial clock 1/0
20
~TII
INT2
Port CliO line 3/Timer inputllnterrupt
request 2 input
21
PC4/TO
Port CliO line 4ITimer output
22
PC5/CI
Port CliO line 5/Counter input
SCK [Serial Clock]. Output for the serial clock when
internal clock is used. Input for serial clock when
external clock is used.
23,24
PCs, PC71
COO, C01
Port CliO lines 6, 7/Counter outputs 0,1
TI [Timer Input]. Timer input terminal.
25
NMI
Nonmaskable interrupt input
26
INT1
Interrupt request 1 input
27
MODE1/Ml
Mode 1 input/Memory cycle 1 output
28
RESET
Reset input
29
MODEOI
iO/M
Mode 0 inputlllO/Memory output
30, 31
X2, X1
Crystal connections 1, 2
32
Vss
Ground
TxD [Transmit Data]. Serial data output terminal.
RxD [Receive Data]. Serial data input terminal.
INT2 [Interrupt Request 2]. Falling-edge-triggered,
maskable interrupt input terminal and AC-input, zerocross detection terminal.
TO [Timer Output]. The output of TO is a square wave
with a frequency determined by the timer/counter.
CI [Counter Input]. External pulse input to timer/event
counter.
COo, C01 [Counter Outputs 0, 1]. Programmable
rectangular wave outputs based on timer/event
counter.
33
AVss
Port T threshold voltage input
34-41
ANo-AN7
AID converter analog inputs 0-7
42
VAREF
AI D converter reference voltage
PDo·PD7 [Port 0]
43
AVee
AID converter power supply
44
RD
Read strobe output
45
WR
Write strobe output
46
ALE
Address latch enable output
Port D is an 8-bit three-state port. It can be programmed
as either 8 bits of input or 8 bits of output. When
external expansion memory is used, port D acts as the
multiplexed address/data bus.
47-54
PFO-PF7
Port F 1/0/Expansiom memory address bus
(bits 8-15)
55-62
PDo-PD7
Port D 1/0/Expansion memory addressl
data bus
63
Voo
RAM backup power supply
64
Vee
5 V power supply
PFo·PF7 [Port F]
Port F is an 8-bit three-state port. Each bit is
independently programmable as an input or output.
When external expansion memory is used, port F
outputs the high-order address bits.
ANo·AN7
Pin Functions
PAo·PA7 [Port A]
Port A is an 8-bit three-state port. Each bit is independently programmable as either input or output.
Reset makes all lines of port A inputs.
PBo·PB7 [Port B]
Port B is an 8-bit three-state port. Each bit is independently programmable as either input or output.
Reset makes all lines of port B inputs.
4-76
These are the eight analog inputs to the A/D converter.
AN4-AN7 can also be used as a digital input for falling
edge detection.
AVss [AID Converter Power Ground]
AVss is the ground potential for the A/D converter
power supply.
NMI [Nonmaskable Interrupt]
Falling-edge-triggered nonmaskable interrupt input.
NEe
pPD7810/11
INT1 [Interrupt Request 1]
WR [Write Strobe]
INT1 is a rising-edge-triggered, maskable interrupt
input. It is also an AC-input, zero-cross detection
terminal.
The WR output goes low to indicate that the data bus
holds valid data. It is a strobe signal for external
memory or 1/0 write operations. WR goes high during
reset.
RESET [Reset]
When the RESET input is brought low, it initializes the
ALE [Address Latch Enable]
pPD781D/11.
The ALE output latches the address signal to the
output of PDo,..PD7'
MODE1, MODEO [Mode 1, 0]
The MODE1 and MOOED inputs select the memory
expansion mode. MODE1 also outputs the M1 signal
during each opcode fetch. MODED outputs the jQ/M
signal.
VAREF [AID Converter Reference]
X1, X2 [Crystal Connections 1, 2]
X1 and X2 are the system clock crystal oscillator
terminals. X1 is the input for an external clock.
Vss [Ground]
Ground potential.
VAREF set the upper limit for the AID converter's
conversion range.
Voo [Backup Power]
AVee [AID Converter Power]
Backup power for on-chip RAM.
This is the power supply voltage for the AID converter.
Vee [Power Supply]
RD [Read Strobe]
+5 V power supply.
The RD output goes low to gate data from external
devices onto the data bus. RD goes high during reset.
4-77
NEe
pPD7810/11
Block Diagram
x'=EJ
X2
.
Osc.·
PF 7 -PFo
(AB,s-AB.)
PC,/TxD
PC,/RxD
PC,tSCi<
PD7 -PD o
(AD 7 -AD o)
NMI
INTl
PC 7 -PC o
PC 31T1/INT2
PCs/CI
PC 6 /CO O
PB 7 -PB o
PC 7 /CO,
AN 7 -AN o
VAREF
AVee
AVss
PA 7 -PA o
RD
WR
ALE MODEl MODEO
RESET
Voo
11
Vce
Vss
49·000600C
4-78
NEe
Functional Description
Memory Map
The JlPD7811 can directly address up to 64K bytes of
memory. Exceptfortheon-chip ROM (0-4095) and RAM
(65280-65535), any memory location can be used as
ROM or RAM. The memory map, figure 1, defines the 0
to 64K byte memory space for the JlPD7811.
pPD7810/11
Table 1.
Memory
Expansion
Analog Input Lines. ANa-AN? are configured as
analog input lines for on-chip A/D converter.
Port A, Port B, Port C, Port F. Each line of these ports
can be individually programmed as an input or output.
When used as I/O ports, all have latched outputs and
high-impedance inputs.
Port D. Port D can be programmed as a byte input or a
byte output.
AN4-AN7' The high order analog input lines, AN4-AN?,
can be used as digital input lines for falling edge
detection.
Control Lines. Under software control, each line of port
C can be configured individually to provide control
lines for the serial interface, timer, and timer/counter.
Memory Expansion. In addition to the single-chip
operation mode, theJlPD7811 has four memoryexpansion modes. Under software control, port D can provide
a multiplexed low-order address and data bus; port F
can provide a high-order address bus. Table 1 shows
the relation between memory expansion modes and
the pin configurations of port D and port F.
Port Configuration
None
Port D
Port F
I/O port
I/O port
256 Bytes
Port D
Port F
Multiplexed address/data bus
I/O port
4K Bytes
Port D
Port Fo-F3
Port F4-F7
Multiplexed address/data bus
Address bus
I/O port
16K Bytes
Port D
Port Fo-F5
Port F6-F7
Multiplexed address/data bus
Address bus
I/O port
60K Bytes
Port D
Port F
Multiplexed address/data bus
Address bus
Input/Output
The JlPD7810/11 has 8 analog input lines (ANa-AN?),
44 digital I/O lines, five 8-bit ports (port A, port B, port
C, port D, port F), and 4 input lines (AN4-AN?).
Memory Expansion Modes and Port
Configurations
Timers
There are two 8-bit timers. The timers may be programmed independently or may be cascaded and used as an
8-bit timer with 8-bit prescaler. The timer can be
software setto increment at intervals of four machine
cycles (1 JlS at 12 MHz operation) or 128 machine
cycles (32Jls at 12 MHz), orto increment on receipt of a
pulse at TI. Figure 2 shows the block diagram for the
timer.
Timer/Event Counter
The 16-bit multifunctional timer/event counter (figure
3) can be used for the following operations:
• Interval timer
• External event counter
• Frequency measurement
• Pulse width measurement
• Programmable square-wave output
4-79
.
~
NEe
pPD7810/11
Figure 1.
Memory Map
0
,
".
IntemalROM
4,096 Bytes x 8
,,~
0
Re8etlStandby Release
4
IRQO
8
IRQ1
10H
IRQ2
18H
IRQ3
20H
IRQ4
28H
IRQ5
OFFFH
1000H
:~
Extemal
Memory
61,184 Bytes x 8
:~
FEFF,H
FFOOH
IntemalRAM
256 Bytes x8
FFFFH
"l"
....
CIIllllIbIe-
-1
SoftINT
t"
SOH
LowADDR
81H
HlghADDR
82H
LowADDR
83H
HlghADDR
~
BEH
LowADDR
BFH
L,.COH
HlghADDR
: ...
Uaer'8Area
I
.
.~
OFFFH
49-000602C
4-80
NEe
Figure 2.
pPD7810/11
Timer Block Diagram
Timer 0
,---------,
Timer 1
r---- - ---,
PC 3 1T1
I
I
I
I
Timer/Event
Counter
Serial Intertace
Clear
I
4 CL----I-f-----I
128CL
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IL _ _ _
_
INTI.
INTI,
I
_ _ ...I
Internal Bus
Notes: 1 CL = 31f (250ns: 12MHz operation~
f: System clock frequency (MHz).
49'()()()S90B
4-81
t¥EC
pPD7810/11
Figure 3.
Block Diagram for Timer/Event Counter
4CL--------,
PCs/CI
(}----1r----------f---f
TO
INTEO
INTE1
INTEIN
Notes: 1 CL = 31f (25Ons: 12MHz operation~
f: System clock frequency (MHz~
49-000599C
8-Bit A/D Converter
Analog/Digital Converter
• 8 input channels
• 4 conversion result registers
• 2 powerful operation modes
- Autoscan mode
- Channel select mode
• Successive approximation technique
• Absolute accuracy: ±1.5 LSB (±O.6%)
• Conversion range: 0 to 5 V
• Conversion time: 48 JlS
• Interrupt generation
The JlPD7810/11 features an 8-bit, high speed, high
accuracy AID converter. The AID converter is made up
of a 256-resistor ladder and a successive approximation
register (SAR). There are four conversion result
registers (CRo-CR3). The 8-channel analog input may
be operated in either of two modes. In the select mode,
the conversion value of one analog input is sequentially
stored in CRo-CR3. In the scan mode, the upper four
channels or the lower four channels may be specified.
Then those fou r channels wi II be consecutively selected
and the conversion results stored sequentially in the
four conversion result registers. Figure 4 shows the
block diagram for the AID converter.
4-82
NEe
pPD7810/11
Interrupt Structure
Universal Serial Interface
There are 11 interrupt sources. Three are external
interrupts and eight are internal. The following, table 2,
shows 11 interrupt sources divided into six priority
levels. See figure 5.
The serial interface can operate in one of three modes:
synchronous, asynchronous, and I/O interface. The
I/O interface mode transfers data MSB first, for easy
interfacing to certain NEG peripheral devices. Synchronous and asynchronous modes transfer data LSB
first. Synchronous operation offers two modes of data
reception: search and nonsearch. In the search mode,
data is transferred one bit at a time from the serial
register to the receive buffer. This allows a software
search for a sync character. In the nonsearch mode,
data transfer from the serial register to the transmit
buffer occurs eight bits at a time. Figure 6 shows the
universal serial interface block diagram.
Standby Function
The standby function saves the top 32 bytes of RAM with
backup power (Voo) if the main power (Vee) fails. On
power-up, you can check the standby flag (SB) to
determine whether recovery was made from standby
mode or from a cold start.
Table 2.
Interrupt Sources
Interrupt
Request
Interrupt
Address
Type of Interrupt
Internal!
External
IRQO
NMI (Nonmaskable interrupt)
Ext
IRQ1
INTTO (Coincidence signal from
timer 0)
Int
INTT1 (Coincidence signal from
timer 1)
IRQ2
16
INT1 (Maskable interrupt)
Ext
INT2 (Maskable interrupt)
IRQ3
24
INTEO (Coincidence signal from
timer / event counter)
Int
INTE1 (Coincidence signal from
timer/event counter)
IRQ4
32
IRQ5
40
INTEIN (Falling signal of CI and
TO counter)
Figure 5.
Interrupt Structure Block Diagram
NMI
INITO
INITl
INTl
INT2
INTEO
INTEl
INTEIN
INTAD
INTSR
INTST
I
OV
ER
SB
Int/Ext
INTAD (AID converter interrupt)
INTSR (Serial receive interrupt)
Int
INST (Serial send interrupt)
49-000603A
Figure 4.
AID Converter Block Diagram
Figure 6.
Universal Signal Interface Block Diagram
AVec
AVss
VAREF
AND
AN,
AN2
AN3
AN.
AN.
AN.
AN7
~
~
PC,'RxD
:=;;
Edge
Detect
49-000B04A
49-000591A
4-83
NEe
pPD7810/11
Zero-Crossing Detector
Absolute Maximum Ratings
The INT1 and INT2 terminals (used common to TI and
PC3) can detect the zero-crossing point of lowfrequency AC signals. When driven directly, these pins
respond as a normal digital input. Figure 7 shows the
zero-crossing detection circuitry.
Power supply voltages, Vee
-0.5 V to +7.0 V
Voo
-0.5 V to +7.0 V
AVee
-0.5 V to +7.0 V
The zero-crossing detection capability allows you to
make the 50-60 Hz power signal the basis for system
timing and to control voltage phase-sensitive devices.
To use the zero-cross detection mode, an AC signal of
approximately 1-3 V AC (peak-lo-peak) and a maximum
frequency of 1 kHz is coupled through an external
capacitor to the INT1 and INT2 pins.
For the I NT1 pin, the internal digital state is sensed as a
the rising edge crosses the average DC level,
when it becomes a 1 and INT1 interrupt is generated.
o until
For the INT2 pin, the state is sensed as a 1 until the
falling edge crosses the average DC level, when it
becomes a 0 and INT2 interrupt is generated.
Figure 7.
AVss
-0.5 V to +0.5 V
Input voltage, VI
-0.5 V to +7.0 V
Output voltage, Vo
-0.5 Vto +7.0 V
Reference input voltage, VAREF
-0.5 V to Vee
Operating temperature, TOPR
10 MHz $ fXTAL $ 12 MHz
fXTAL $ 10 MHz
Storage temperature, TSTG
Comment: Exposing the device to stresses above those listed in
absolute maximum ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Operating Conditions
Oscillating Frequency
Zero-Crossing Detection Circuit
c
~~-----------------------
INT1
INT2(PC 3 )
fXTAL $ 10 MHz
Vee, AVec
+5.0 V ±10%
10 MHz $ fXTAL $12 MHz
+5.0 V ±5%
Capacitance
TA =25°C; Vcc = Voo = Vss = 0 V
Limits
Parameter
Symbol Min
TYP
. Max
Capacitance
CI
10
Output
capacitance
Co
20
1/0 capacitance
CIO
20
Unit
Test
Conditions
pF Afe = 1 MHz.
Unmeasured
pF pins returned
to 0 V.
pF
Recommended XTAL Oscillation Circuit
49·000592A
c=
10 pF
83·003282A
4-84
NEe
pPD7810/11
DC Characteristics
Serial Operation
TA == -10°C to +70°C; Vee == +5.0 V ±5%; Vss == 0 V; VDD == Vee
- 0.8 V to Vee
Limits
Parameter
Symbol
Input low
voltage
VIL
Input high
voltage
VIH1
Min
Typ
Max Unit
Test
Conditions
O.B
V
Vee
V All except SCK,
RESET, X1 and
X2
VIH3
2.0
O.B Vee
Vee
O.B VDD
Vee
V RESET
0.45
V IOL == 2.0 mA
VOL
Output high
voltage
VOH
2.4
V IOH == -200 pA
Data
retention
voltage
VDDDR
3.2
V Vee = 0 V;
RESET = VIL
I nput current
±200 pA INT1, TI(PC3); +
0.45 V::; VI <
Vee
±10 pA All except
INT, TI(PC3)
oV::; VI ::;Vee
III
Vee supply
current
Max
ps
Alec
6
12
mA
IDD
1.5
3.5
mA TA = -40 to
+B5°C
3.2
mA Vee = VDD =
5VTA=-10to
+70°C
Icc
tKKL
SCK width high
tKKH
RxD set-up time to SCK
t
150
220
SCK input (1)
ns (2)
500
SCK width low
Test
Conditions
Unit
teYK
ps
SCK output
750
ns SCK input(1)
200
ns SCK input (2)
900
ns SCK output
750
ns SCK input (1)
200
ns SCK input (2)
900
ns SCK output
BO
ns (1)
tRXK
RxD hold time after
SCK t
tKRX
BO
ns (1)
SCK ~ TxD delay time
tKTX
210
ns (1)
Note:
(1) 1x baud rate in asynchronous, synchronous, or I/O interface
mode.
E
(2) 16x baud rate or 64x baud rate in asynchronous mode.
Zero-Cross Characteristics
±10 pA +0.45 V::; Vo
::; Vee
Output leakage ILO
current
VDD supply
current
SCK cycle time
Min
V SCK, X1, X2
Output low
voltage
AVec supply
current
Symbol
2
VIH2
Input leakage
current
Limits
Parameter
Limits
Parameter
Symbol
Min
Max
Unit
Test
Conditions
Zero-cross detection
input
Vzx
3
V ac, p-p
Ac coupled
Zero-cross accuracy
Azx
±135
mV
60-Hz sine
wave
Zero-cross detection
input frequency
fzx
0.05
kHz
mA TA = -40 to
+B5°C; Vee =
VDD = 5 V
4-85
NEe
pPD7810/11
AC Characteristics
Read/Write Operation
vss = 0 v, vee - 0.8 v::::; VDO::::; Vee
Limits
fXTAL = 10 MHz
Parameter
Symbol
RESET pulse width
Min
Max
fXTAl = 12 MHz
Min
Max
Test
Conditions (11
Unit
tRP
6.0
5.0
/1S
Interrupt pulse width
tiP
3.6
3.0
/1S
Counter input pulse width
tel
600
500
ns
Event counter mode
4.8
4.0
/1S
Pulse width measurement mode
500
ns
tel
Timer input pulse width
tTl
600
X1 Input cycle time
teye
100
Address set-up to ALE!
tAL
100
65
ns
Address hold after ALE!
tLA
70
50
ns
Address to RD ! delay time
tAR
200
RD ! to address floating
tAFR
20
20
Address to data input
tAD
480
360
ns
ALE! to data input
tLDR
300
215
ns
RD ! to data input
tRD
180
ns
ALE! to RD ! delay time
tLR
50
35
ns
tRDH
0
0
ns
tRL
150
115
ns
tRR
350
280
ns
Data read
650
530
ns
Opcode fetch
Data hold time to RD
RD
t
t to ALE t delay time
RD width low
250
83
250
ns
150
250
ns
ns
ALE width high
tLL
160
125
ns
M1 setup time to ALE!
tML
100
65
ns
M1 hold time after ALE!
tLM
70
50
ns
101M setup time to ALE!
tiL
100
65
ns
101M hold time after ALE!
tLi
70
50
ns
Address to WR ! delay
tAW
200
150
l to data output
WR l to data output
tLDW
210
195
ns
tWD
100
100
ns
ALE
ALE! to WR ! delay
Data set-up time to WR
Data hold time to WR
WR
tLW
50
35
ns
tDW
300
230
ns
tWDH
130
95
ns
tWL
150
115
ns
tww
350
280
ns
t
t
t to ALE t delay time
WR width low
Note:
(1) Load capacitance: CL
4-86
ns
= 150 pF.
NEe
pPD7810/11
AID Converter Characteristics
TA = -10°C to +70°C; Vee = AVec = 5,0 V ±5%; Vss = AVss = 0 V;
VAREF = AVec - 0,5 V to AVec,
Limits
Parameter
Symbol
Resolution
Min
Typ
Max
Unit
Bits
8
Absolute
accuracy
0.4% LSB
± 1/2
TA = -10°C to
+50°C
0,6%
TA = -10°C to
+70°C (Note 1)
LSB
±1/2
Conversion
time
Sampling
time
tCONV
tSAMP
576
tCYC
83 ns::; tCyc::;
110 ns
432
tCYC
110 ns::; tCyc::;
170 ns
96
tCYC
83 ns::; tCyc::;
110 ns
72
Analog
input voltage
VIA
Analog
resistance
RAN
Analog
reference
current
IAREF
Test
Conditions
tCYC
0
VAREF
1000
0,2
0,5
1.5
110 ns::; tCYc::;
170 ns
Symbol
MiniMax
Min
tTl
6T
Min
tCI(2)
6T
Min
tCI(3)
48T
Min
tiP
36T
Min
tAL
2T -100
Min
tLA
T -30
Min
tAR
3T -100
Min
tAD
7T - 220
Max
tLDR
5T - 200
Max
tRD
4T -150
Max
tLR
T -50
Min
tRL
2T - 50
Min
Mn
tLL
= -40°C to +85°C,
Calculating Expression
60T
tRR
mA
tCYC
tRP
V
Note:
(1) In case of fXTAL::; 10 MHz, TA
Bus Timing Depending on
4T - 50 (Data Read)
----------------._-------------------_.7T - 50 (Opcode Fetch)
2T -40
Min
Min
tAW
3T -100
Min
tLDW
T+ 110
Max
tLW
T -50
Min
tDW
4T -100
Min
tWDH
2T -70
Min
tWL
2T -50
Min
tww
4T -50
Min
tCYK
20T (SCK input)(1)
---.-------_.----._.----._-_.-- ... --------_.-----.--24T (SCK output)
Min
tKKL
10T - 80 (SCK input)(1)
-.---"---.--------------------- .. _------------.------.
12T - 100 (SCK output)
Min
tKKH
10T - 80 (SCK input)(1)
.--.---.---------------".---------------------.------.
12T - 100 (SCK output)
Min
IE]
Note:
(1) 1x Baud rate in asynchronous, synchronous, or I/O interface
mode,
T = teye = 1/fXTAL'
The items not included in this list are independent of oscillator
frequency (fXTAd,
(2) Event counter mode,
(3) Pulse width measurement mode,
4-87
NEe
pPD7810/11
Timing Waveforms
Read Operation
x,
AB,.-AB. X l
(PF7 -PF.)
--
--.JIUa
t::1 t ROH
tAD
1
ADoR.-AooR7
I-- - t L L _
-
ALE
- tAL -
)
Data-In
1-~
t LOR
I - tLA -
-X
'i:
AooR.-ADoR'5
_ t RL _ "
I-tAFR
t Ro
Ro
-tLR
~
tRR
tAR
MOoEO [101M]
[Note 1]
I
7''!
! - = = = i ' L - . tL
Note: [1] iO/M signal Is output to the MOoEO pin during a read orwrlteofspeclal
reglster[s] Sr-Sr2, if MOoEO Is pulled up to Vee.
49-0005438
Write Operation
x,
AB'5-AB.~'~--~~~------------------------------------------------------------~J~~'~----(PF7 -PF.) _r'-__,.-p;__________-:-________~----A-0-0-R;.8--A-0-oR-,;;.5----------------------_J''-_r'-____
0 7 -0.
(P07 -Po.) .....r
'"_,.p;_____.....;~_t_....;..--_'l~'--J,,...-----------------O-ata-o---ut--_:__:__---------~,--,, ,______
I------tow------i
ALE
~-----------tww------------~
MOoEO [101M]
[Note 1]
Note: [1] iO/M signal is output to the MOoEO pin duringareadorwrlteolspeclal
reglster[s] Sr-Sr2, If MOoEO is,pulled up to Vee.
49·0006396
4-88
NEe
pPD7810/11
Timing Waveforms (cont)
Opcode Fetch Operation
X,
,5
AB -AB.
(PF 7 -PF.)
J--.J
l(
ADDR.-ADDR ,5
tAD
AD 7 -AD.
(PD 7 -PD.)
ALE
-
)
tRDH
Opcode
ADDR.- ADDR 7
1-----1
'}--------
t LDR -
I::::::: _tLL
j4--tLA_
-tRL
~
If
f - - t RD -
- tALRD
- tLR
IK:"'
tRR
tAR
MODE1 [M1]
[Note 1]
! - - - tML -
J
:+/
. tL
Note:
[1] M1 signal Is output to the MODE1 pin during Opcode Fetch If MODE1 pin Is
pulled up to VCC.
49-0005458
I
Serial Operation Transmit/Receive Timing
TXD ____
~----~~--------------~------------------
RXD ________~~4+------------~--------------------
49-0005468
4-89
NEe
pPD7810/11
Operand Format/Description
Remarks
Format
1. sr-sr4 [special register)
Description
r
r1
r2
V,A,B,C, D,E, H,L
EAH,EAL, B,C,D,E, H,L
A, B,C
sr
sr2
sr3
sr4
PA, PB, PC, PO, PF, MKH, MKL, ANM, SMH, SML, EOM,
ETMM, TMM, MM, MCC, MA, MB, MC,
MF, TxB, TMo, TM1
PA,PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB,
CRO,CR1,CR2,CR3
PA, PB, PC, PD, PF, MKH, ANM, MKL; SMH, EOM, TMM
ETMO, ETM1
.
ECNT, ECPT
rp
rp1
rp2
rp3
SP,B,D,H
V, B,D,H, EA
SP,B,D,H,EA
B, D,H
rpa
rpa1
rpa2
B, D, H, D+ , H + , 0 -, H B, D,H
B, D, H, 0 +, H + , D -, H -, D+ byte, H + A, H + B,
H + EA, H + byte
D, H, D + +, H + +, D + byte, H + A, H + B, H + EA,
H + byte
sr1
rpa3
wa
a-Bit il)1mediate data
word
byte
bit
16-Bit immediate data
a-Bit immediate data
3-Bit immediate data
f
CY,HC,Z
irf
FNMI, FTO, FT1, F1, F2, FEO, FE1, FEIN, FAD, FSR, FST, ER,
OV, AN4, ANs, AN6, AN?, SB
ETMM = Timer/Event
Counter Mode
EOM = Timer/Event
Counter Output Mode
MM = Memory Mapping
TMo = Timer Register 0
TM1 = Timer Register 1
TMM = Timer Mode
ETMo = Timer/Event
Counter Register 0
ETM1= Timer/Event Counter
Register 1
TxB = TX Buffer
RxB = RX Buffer
SMH = Serial Mode High
SML = Serial Mode Low
MKH = Mask High
MKL = Mask Low
ANM = A/D Channel Mode
CRo = A/D Conversion Result 0-3
to CR3
2. rp·rp3 [register pair)
H = HL
V=VA
EA = Extended Accumulator
SP = Stack Pointer
B=BC
D= DE
Description
B = (BC)
D = (DE)
H = (HL)
D+=(DE) +
H - = (HL) +
D-= (DE)H- = (HL)'CY = Carry
5. irf [interrupt flag)
A
Logical product (logical AND)
NMI = NMI* Input
v
Logical sum (logical OR)
Exclusive OR
Complement
Concatenation
D + += (DE) ++
H + +=(HL) ++
D + byte = (DE) + byte
H + A = (HL) + (A)
H + B = (HL) + (B)
H + EA = (HL) + (EA)
H + byte = (HL) + byte
4. f [flag)
Transfer direction, result
4-90
ECNT = Timer/Event
Counter Upcounter
ECPT = Timer/Event
Counter Capture
3. rpa·rpa3 [rp addressing)
Instruction Set Symbol Definitions
Symbol
PA = Port A
PB = Port B
PC = Port C
PD = Port D
PF = Port F
MA = Mode A
MB = Mode B
MC = Mode C·
MCC = Mode Control C
MF = Mode F
FTO = INTFTO
FT1 = INTFT1
F1 = INTF1
F2 = INTF2
FEO = INTFEO
FE1 = INTFE1
HC = Half Carry
Z = Zero
FEIN = INTFEIN
FAD = INTFAD
FSR = INTFSR
FST = INTFST
ER = Error
OV = Overflow
AN4 to AN? = Analog Input 4-7
SB = Standby
Instruction Set
Operation Code
Mnemonic
Operand
Operation
7
6
5
0
0
0
B1
B3
4 3
B2
2
1
0
7
6
5
B4
4 3
2
1
0
State(l)
Bytes
Skip
Condition
8·Bit Data Transfer
MOV
MVI
r1,A
A, r1
(r1)-(A)
(A)-(r1)
0
0
*sr,A
*A,sr1
r,word
(sr)-(A)
(A)-(sr1)
(r)-(word)
0
0
word,r
(word)-(r)
0
*r,byte
(r) -byte
setL1 if r = A
set LOif r = L
sr2,byte (sr2) - byte
0
MVIW
*wa, byte ((V).(wa)) -
0
MVIX
STAW
LDAW
STAX
LDAX
*rpa1,byte
*wa
*wa
*rpa2
*rpa2
EXX
EXA
EXH
16·Bit Data Transfer
BLOCK
D
DMOV
rp3, EA
EA,rp3
byte
(rpa1) - byte
((V).(wa)) +- A
0
0
0
1
0
0
(rpa2) - (A)
(A) - ((rpa2))
(B) - (B'),(C) - (C'),(D) - (D')
(E) .... (E'),(H) .... (H'),(L) .... (L')
(V) ++ (V'),(A) .... (A'),(EA) ++ (EA')
(H) .... (H'),(L) .... (L')
A3
0
((DE)) - ((HL)),(DE) - (DE + 1),
(HL) - (HL) + 1, (C) - (C)-1
End if borrow
0
((V).(wa))
(rp3L) - (EAL),(rp3H) - (EAH)
(EAL) - (rp3d,(EAH) - (rp3H)
A3 0
0 0
0
0
0
0
0
(A) -
0 1
0 1
1 0 0
Lowaddr
1 0 0
0
0
0
1
0
0
0 0
Lowaddr
0 1 R2 R1 Ro
1
0
0
0
0
0
0
Data
1 0
Data
0 1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
S5 S4 S3 S2 S1 So
S5 S4 S3 S2 S1 So
1 0 1 R2 R1 Ro
High addr
10
10
17
2
2
4
1 1 R2 R1 RO
High addr
17
4
7
2
14
3
Offset
13
3
Data
10
2
Offset
Offset
Data (2)
Data (2)
10
10
7/13(3)
2
2
2
2
1
0
Data
S3
o A1 Ao
0 0 1 1
0 0 0
1 A2 A1 Ao
1 A2 A1 AO
0 0 0 1
0
0
1
1
1
0
0
0
4
4
T2 T1 TO
1 T2 T1 To
0
P1 Po
P1 Po
0
0
0
o
S2 S1 So
7/13(3)
4
~
t'l
L1 = 1 and r = A
LO = 1 and r = L
4
4
13 x
(C+1)
4
4
,.
1:::
g
--a
...0CD
...~
.j::a..
I
~
I!II
~
I
<.D
1:::
Instruction Set (cont)
I\)
Operation Code
82
81
Mnemonic
Operand
7
Operation
16-Blt Data Transfer (cont)
OMOV
sr3, EA (sr3) +- (EA)
EA,sr4 (EA) +- (sr4)
S8CO
word (word) +- (C), (word + 1) +- (8)
o
o
o
SOEO
. word
(word)
+-
(E), (word + 1) -
(D)
o
SHLO
word
(word)
+-
(L), (word + 1) - (H)
o
SSPO
word
(word) -
(SPd,(word + 1) +- (SPH)
o
STEAX
rpa3
((rpa3)) -
L8CO
word
(C) -
(EAL),((rpa3) + 1 +- (EAH)
(word),(8) - (word + 1)
o
o
0
0
o
1
(E) - (word),(O) -
(word + 1)
o
LHLO
word
(L) - (word),(H) -
(word + 1)
o
LSPO
word
(SPd -'(word),(SPH) - ((word) + 1)
o
LOEAX
rpa3
(EAL) - ((rpa3)),(EAH) - ((rpa3) + 1)
o
PUSH
rp1
((SP) - 1) - (rp1H) ((SP) - 2) (SP) +- (SP) - 2
POP
rp1
TABLE
(C) 8-Bit Arithmetic [Register)
ADD
A,r
(A) r,A
(r) AOC
A,r
(A) r,A
(r) -
4
o
word
LXI
5
o
LOEO
(rp1d- ((SP)),(rp1H) (SP) - (SP) + 2
*rp2,word (rp2) - (word)
set LO if rp2 = H
&
U
o
o
((SP) + 1)
2
I
0
o
000
000
0 0 0
Lowaddr
10000
Lowaddr
1 0 0 0 0
Lowaddr
1 0 0 0 0
Lowaddr
0 1 0 0 0
Oata(4)
1 0 0 0 0
Lowaddr
1 0 0 0 0
Lowaddr
1 0 0 0 0
Lowaddr
1 0 0 0 0
Lowaddr
0 1 0 0 0
Oata(4)
o
(rp1d
3
o
2
I
0
01001UO
1 1 0 0 0 0 V1 Vo
000 1
1 0
High addr
o 0 1 0 1 1
High addr
o 0 1 1 1
o
High addr
1 0
o 0 001
High addr
o
0
1 C3 C2 C1 Co
000
o
0
o
0
o
0
o
High addr
1 0 1 1
High addr
1 1 1 1
High addr
0 0 1 1
High addr
0 C3 C2 C1 Co
0
Statefl)
Bytes
14
14
20
2
20
4
20
4
20
4
14/20(3)
3
20
4
20
4
20
4
20
4
14/20(3)
3
0 02 01 00
10
0
((PC)+3+(A)),B - ((PC)+3+(A)+ 1)
0
0
0
(A) + (r)
(r) + (A)
(A) + (r) + (CY)
(r) + (A) + (CY)
o
o
o
o
III
5
13
0
0
&
002 01 00
0 P2 P1 Po 0 1
High byte
1
7
B4
4 3
0
1
0
o
o
o
o
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Low byte
o
o
1
o
10
3
0
1
000
17
2
o
o
o
o
0
0
0
0
~ ~ ~
8
8
2
2
~
1
0 ~ ~ ~
8
2
1
0 ~ ~ ~
8
2
"
"....
...
2
4
1
~ ~
Skip
Condition
a
....
...oCD
LO = 1 and
rp2=H
~
t)
Instruction Set (cont)
Operation Code
B2
B1
U
Mnemonic
Operand
Operation
7
6
5
4
3
2
1
0
7
6
1
0
o
0
5
B4
4 3
2
1
0
State(l)
Bytes
Skip
Condition
8-Bit Arithmetic [Registerl(cont!
ADDNC
SUB
SBB
SUBNB
ANA
ORA
XRA
GTA
LTA
NEA
EQA
ONA
OFFA
(A) + (r)
(r) + (A)
(A) - (r)
(r) - (A)
(A) - (r) - (CY)
(r) - (A) - (CY)
(A) - (r)
(r) - (A)
(A) A (r)
(r) A (A)
(A) V (r)
(r) V (A)
(A).If(r)
(r) ¥ (A)
(r) - 1
(A) - 1
(r)
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A,r
r,A
A;r
r,A
A,r
(A) (r) (A) (r) (A) (r) (A) (r) (A) (r) (A) (r) (A) (r) (A) (r) (A) -
r,A
(r)
A,r
r,A
A,r
r,A
A,r
A,r
(A) - (r)
(r)-(A)
(A) - (r)
(r) - (A)
(A) A (r)
(A) A (r)
~
(A)
o
o
or
0 000 0
0 0 0 0 0
00000
01
00000
00000 0
o 1
0 0 0 0 0
o
100 000
o 1 100 000
o
0 000 0
o 1
0 0 0 0
o
0 0 0 0 0
o
0 0 0 0 0
o
0 0 0 0 0
o
1 0 0 0 0 0
o
0 0 0 0 0
o
0 0 0 0 0
o
0 000 0
o 1
0 0 0 0 0
o
0 0 0 0 0
o 1 1 0 0 0 0 0
01
00000
01
00000
o 1 1 0 0 0 0 0
o 1 1 0 0 0 0 0
o
o
o
o
0 ~ ~ ~
0 ~ ~ ~
8
8
0 R~
0 R2 R1 Ro
1
o R2 R1 Ro
o 1
o R2 R1 Ro
1 0
o R2 R1 Ro
o 0
o R2 R1 Ro
1 000
~ R1 Ro
o 0 0 0
R2 R1 Ro
1 0 0
~ R1 Ro
000
R2 R1 Ro
100
o R2 R1 Ro
000
R1 Ro
1 0
o
~ R1 Ro
o
o 0
R2 R1 Ro
1 0 1 1
R2 R1 Ro
o 0 1 1
R2 R1 Ro
o 1 ~ R1 Ro
o
o
R2 R1 ~
~ R1 Ro
1 1
o
R2 Rl Ro
o 0
R2 Rl Ro
o
1 R2 R1 Ro
8
8
8
8
o
0R2
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2
2
2
2
2
2
2
2
2
2
2
2
No carry
No carry
~
~
No borrow
No borrow
2
2
2
2
2
2
2
2
2
2
2
2
No borrow
No borrow
Borrow
Borrow
No zero
No zero
Zero
Zero
No zero
Zero
8-Bit Arithmetic (Memory!
ADDX
ADCX
ADDNCX
SUBX
SBBX
SUBNBX
ANAX
ORAX
rpa
rpa
rpa
rpa
rpa
rpa
rpa
rpa
(A) (A) (A) (A) (A) (A) (A) (A) -
(A) + ((rpa))
(A) + ((rpa)) + (CY)
(A) + ((rpa))
(A) - ((rpa))
(A) - ((rpa)) - (CY)
(A) - ((rpa))
(A) A ((rpa))
(A) V ((rpa))
o
o
o
o
o
o
o
o
1
000 0
o 0 0 0
o 000
o 0 0 0
000 0
000 0
o
0
0
0
1 0 0 0 0
1
o
o
0
0
1
1
0
o
1
1
01
0
o 0
o
1
1
0
1
0 A2
0 A2
0 A2
0 A2
0 A2
0 A2
1 A2
1 A2
Al Ao
A1 Ao
A1 Ao
A1
Al
Al
Al
Al
Ao
Ao
Ao
Ao
Ao
11
11
11
11
11
11
11
11
2
2
2
2
2
2
2
2
No carry
No borrow
1::
"a
....CD--o
~
~
....
I
co
(J.)
I!II
~
I
<0
,.
1::::
Instruction Set (cont)
~
Operation Code
Bl
Mnemonic
Operand
Operation
7
~
B2
a
B4
& 5 432
0
7
& 543
2
1
0
State(l)
Bytes
Skip
Condition
8-Bit Arithmetic IMemory)lcont)
XRAX
rpa
(A)
GTAX
rpa
(A) - ((rpa» -1
LTAX
NEAX
rpa
rpa
(A) - ((rpa»
(A) - ((rpa))
o
o
o
o
EQAX
rpa
(A) - ((rpa))
o
ONAX
OFFAX
rpa
rpa
(A) A ((rpa))
(A) A ((rpa»
o
+-
(A)-\f((rpa»
o
o
o
o
o
o
o
o
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o
o
o
0
0
0
0
0
0
0
11
11
1
1 A2 A1 Ao
11
o
1 A2 A1 Ao
11
1
1
1 A2 A1 Ao
11
o
o
0
1 A2 A1 Ao
1
1 A2 A1 -Ao
11
11
2
2
2
2
2
2
2
0
1
1
0
1
0 A2 A1 Ao
1 A2 A1 Ao
.....
m
o
~
No borrow
Borrow
No zero
Zero
No zero
Zero
Immediate Data
ADI
*A,byte (A)
r,byte
(r)
++-
+ byte
+ byte
(A)
(r)
o
o
o
o
o
o
0
o
o
0
o
o
0
0 R2 R1 Ro
7
11
3
o
0
S3
o
0
0 S2 S1 So
20
3
1
0 R2 R1 Ro
7
11
3
o
S2 S1 So
20
3
Data
2
Data
sr2, byte (sr2)
(sr2)
+-
+ byte
0
Data
ACI
*A,byte (A)
r,byte
(r)
++-
sr2,byte (sr2)
+ byte + (CY)
+ byte + (CY)
(A)
(r)
(sr2)
+-
+ byte + (CY)
o
o
010
1
0
1
o
0
o
o
o
o
o
0
S3
o
0
1
2
o
0
0
7
1 0
o
0
o
0 R2 R1 Ro
11
3
No carry
No carry
o
0
S3 0
o
0 S2 S1 So
20
3
No carry
0
Data
0
Data
2
Data
ADINC
*A,byte (A)
r,byte
(r)
++-
+ byte
+ byte
(A)
(r)
o
o
0
o
Data
Data
sr2,byte (sr2) +- (sr2)
+ byte
o
o
0
Data
SUI
*A,byte (A)
r,byte
(r)
++-
(A) - byte
(r) - byte
o
o
o
o
o
1
0
0
1
0
o
0
o
o
0 R2 R1 Ro
7
11
3
o
0
S3
o
0 S2 S1 So
20
3
1
Data
2
Data
sr2,byte (sr2)
+-
(sr2) - byte
0
Data
SBI
*A,byte (A)
r,byte
(r)
+-
+-
(A)..,.. byte - (CY)
(r) - byte - (CY)
o
o
1 0
o
o
1
o
0
7
2
0 R2 R1 Ro
11
3
o
20
3
Data
o
0
o
o
0
S3
Data
sr2,byte (sr2)
+-
(sr2) - byte - (CY)
0
Data
III
S2 S1 So
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operand
Operation
7
6
0
0
0
5
B1
B3
4
3
B2
B4
2
1
0
0
1
0
0
Data
0
7
6
0
0
0
0
S3
5
4
3
2
1
0
Statell)
Bytes
Skip
Condition
Immediate Data (contI
SUINB
*A,byte (A)
r,byte
(r)
++-
sr2,byte (sr2)
(A) - byte
(r) - byte
+-
(sr2) - byte
0
0
0
7
2
R2 R1 Ro
11
3
No borrow
No borrow
0 S2 S1 So
20
3
No borrow
1 R2 R1 Ro
11
3
S2 S1 So
20
3
7
2
1 R2 R1 Ro
11
3
S2 S1 So
20
3
7
2
0 R2 R1 Ro
11
3
0 S2 S1 So
20
3
Data
1 R2 R1 Ro
2
No borrow
11
3
No borrow
S2 S1 So
14
3
No borrow
7
2
Borrow
1 R2 R1 Ro
11
3
Borrow
S2 S1 So
14
3
Borrow
Data
0 1 R2 R1 Ro
7
Data
0
~
~
Data
ANI
ORI
*A,byte (A) - (A) /\ byte
r,byte (r) - (r) /\ byte
0
sr2,byte (sr2) -
0
*A,byte (A) r,byte
(r) -
(sr2) /\ byte
(A) V byte
(r) V byte
0
0
0
0
0
0
0
0
1
1
0
Data
0
0
0
0
Data
0
0
S3
0
0
1
0
0
1
1
0
0
Data
0
0
0
0
0
0
0
0
2
Data
1
Data
sr2,byte (sr2) XRI
*A,byte (A)
r,byte
+-
(sr2) V byte
0
(A)-\fbyte
0
0
0
0
Data
0
1
0
0
(r) -(r)-Ifbyte
sr2,byte (sr2) -
(sr2) V byte
0
Data
0
0
0
S3
Data
1
0
0
0
S3
0
0
Data
GTI
* A,byte
(A) - byte - 1
0
r,byte
(r) - byte-1
0
sr2,byte (sr2) - byte - 1
LTI
NEI
0
0
0
0
0
0
Data
0
0
0
Data
0
S3
0
0
0
0
0
1
0
S3
*A,byte (A) - byte
r,byte (r) - byte
0
sr2,byte (sr2) - byte
0
0
0
Data
* A,byte
(A) - byte
0
0
0
r,byte
(r) - byte
0
1
0
0
Data
1
Data
0
11
No zero
3
No zero
1:::
"--aD
...
:::.:
...
CX)
0
Data
~
I
(0
0'1
~
~
I
<0
1:::
Instruction Set (cont)
0)
Operation Code
Bl
B2
-
-
B3
Mnemonic
Operand
Operation
Immediate Data (cont)
NEI
sr2,byte (sr2) - byte
EQI
ONI
OFFI
7
6
5
4
0
0 0
Data
1 0
1 0
Data
0 0
Data
0 0
1 0
Data
0 0
Data
1 0
1 0
Data
0
*A,byte (A) - byte
r,byte (r) - byte
0
0
sr2,byte (sr2) - byte
0
*A,byte (A) A byte
r,byte (r) A byte
0
0
sr2,byte (sr2) A byte
0
*A,byte (A) A byte
r,byte (r) A byte
0
0
sr2,byte (sr2) A byte
0
0
3
0
0
2
B4
4 3
2
S2 S1 So
14
1 R2 R1 Ro
S2 S1 So
14
1
0
7
0
0
S3
0
0
0
1
6
5
1
0
1
0
Data
0
S3
State(l)
Bytes
Skip
Condition
3
No zero
7
2
11
3
Zero
Zero
3
Zero
1
0
2
0
0
Data
0 1 R2 R1 Ro
7
0
11
3
No zero
No zero
0
0
S3
0
0
S2 S1 So
14
3
No zero
1
0
1
0
7
2
0
0
1
1 R2 R1 Ro
11
3
Zero
Zero
0
0
S3
0
S2 S1 So
14
3
Zero
0
0
0
0
0
0
0
14
3
0
0
0
0
0
0
0
14
3
0
0
0
0
14
3
0
0
0
0
0
14
3
1
0
0
0
0
14
3
0
0
0
0
14
3
0
0
0
14
3
Data
"ma
...0--...~
Data
Working Register
ADDW
wa
(A) -
(A) + ((V)e(wa))
0
1
0
0
Offset
ADCW
wa
(A) -
(A) + ((V)e(wa)) + (CY)
0
1
0
Offset
ADDNCW
wa
(A) -
(A) + ((V)e(wa))
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
SUBW
wa
(A) -
(A) - ((V)e(wa))
0
Offset
1 0
Offset
SBBW
wa
(A) -
(A) - ((V)e(wa)) - (CY)
0
1
0
0
1
No carry
Offset
SUBNBW
ANAW
wa
wa
(A) (A) -
(A) - ((V)e(wa))
(A) A ((V)e(wa))
,II
0
1
0
Offset
1 0
Offset
0
0
No borrow
~
(1
Instruction Set (cont)
Operation Code
Bl
Mnemonic
Operand
Working Register (cont)
ORAW
wa
Operation
(A)
+-
(A) V ((V)e(wa))
7
6
5
B3
4 3
0
B2
2
0
6
5
B4
4 3
2
1
0
0
0
0
0
0
0
0
14
3
0
0
0
0
0
0
0
0
14
3
0
0
0
0
0
0
14
3
No borrow
0
0
0
0
0
0
14
3
Borrow
0
0
0
0
0
14
3
No zero
0
0
0
14
3
Zero
0
0
0
14
3
No zero
0
0
0
14
3
Zero
I
0
0
7
State(l)
Bytes
Skip
Condition
~
~
Offset
XRAW
wa
(A)
GTAW
wa
(A) - ((V)e(wa))-1
0
LTAW
wa
(A) - ((V)e(wa))
0
NEAW
wa
(A) - ((V)e(wa))
0
EQAW
wa
(A) - ((V)e(wa))
0
+-
(A).lf((V)e(wa))
0
1 0
Offset
1 0
Offset
1 0
Offset
1 0
Offset
1 0
0
0
Offset
ONAW
wa
(A) A ((V)e(wa))
0
1 0
Offset
0
0
OFFAW
wa
(A) A ((V)e(wa))
0
1 0
Offset
0
0
0
0
0
0
Offset
19
3
0
Data
1 0
0
Offset
19
3
ANIW
ORIW
*wa,byte ((V)e(wa))
*wa,byte ((V)e(wa))
+-
+-
((V)e(wa)) A byte
((V)e(wa)) V byte
0
0
0
0
0
0
Data
GTIW
*wa,byte ((V)e(wa)) - byte - 1
0
0
0
0
0
Offset
13
3
No borrow
0
Data
1 0
Data
0
Offset
13
3
Borrow
LTIW
*wa,byte ((V)e(wa)) - byte
0
NEIW
*wa,byte ((V)e(wa))- byte
0
0
0
0
Offset
13
3
No zero
0
Data
1 0
0
Offset
13
3
Zero
0
Offset
13
3
No zero
EQIW
*wa,byte ((V)e(wa)) - byte
1
Data
ONIW
OFFIW
*wa,byte ((V).(wa)) A byte
*wa,byte ((V)e(wa)) A byte-' '
0
0-Q 0
0
Data
1 0
0
1
,.
1:::
D
Offset
0
Data
13
3
Zero
IIIiiI
CD
~
~
~
~
~
I
(0
"'"
II
4:>-
cb
1::
Instruction Set (cont)
(X)
~
Operation Code
Mnemonic
Operand
Operation
7
654
o
o
o
o
o
o
r
B1
~
~
~
3
2
0
7
o
6
5
4
3
2
0
o
o
o
o
0
R1 Ro
1 P1 Po
11
0
0
11
11
11
11
11
State(1)
Bytes
Skip
Condition
16-Bit Arithmetic
EADD
EA,r2
(EA) -
(EA) + (r2)
DADO
EA,rp3
(EA) -
(EA) + (rp3)
DADC
EA,rp3
(EAr ~ (EA) + (rp3) + (CY)
DADDNC
EA,rp3
(EA) -
(EA) + (rp3)
ESUB
EA,r2
(EA) -
(EA) - (r2)
DSUB
EA,rp3
(EA) -
(EA) - (rp3)
DSBB
EA,rp3
(EAr -
(EA) - (rp3) - (CY)
DSUBNB
EA,rp3
(EA) -
(EA) - (rp3)
DAN
EA,rp3
(EA) -
(EA) /\ (rp3)
(EA) V (rp3)
DOR
EA,rp3
(EA) -
DXR
EA,rp3
(EA) -(EA)-\f-(rp3)
DGT
EA,rp3
(EA) - (rp3) - 1
DLT
EA,rp3
(EA) - (rp3)
ONE
EA,rp3
(EA) - (rp3)
DEQ
EA,rp3
(EA) - (rp3)
DON
EA,rp3
(EA) /\ (rp3)
DOFF
EA,rp3
(EA) /\ (rp3)
Multiply /Divide
MUL
r2
DIV
r2
Increment/Decrement
INR
r2
INRW
*wa
INX
OCR
DCRW
DCX
rp
(EA) -
(A) x (r2)
(EA) -
(EA) + (r2), (r2) -
Remainder
(r2)-(r2)+1
((V)e(wa)) (rp) -
EA
(EA) -
r2
(r2) -
*wa
o
o
o
o
o
o
o
o
o
o
((V)e(wa)) + 1
(EA) + 1 .
((V)e(wa)) -
((V)e(wa)) -1
1
(J
0
0
0
o
o
o
o
o
o
o
1
1
1
0
0
0
0
0
0
1
0
0
0
o
1
1
1
0
0
0
0
0
0
1
0
1
0
1
0
1
1
o
o
1
0
0
1
0
11
2
1 P1
Po
11
1 P1
Po
11
2
2
2
100
1
0
1
000
o
1
R1 Ro
P1 Po
P1
Po
0
P1
Po
1
Pt Po
2
2
2
P1 Po
11
2
001
0
P1
010
o
o
1
P1 Po
11
11
11
11
11
11
11
2
2
No borrow
2
Borrow
0
1
0
0
o
1
0
0
1
0
P1 Po
1
0
P1 Po
010
1
0
1
0
1
1
0
1
0
(J
o
0
0
o
o
0
P1
Po
P1
Po
P1
Po
1
1
0
0
0
0
o
o
1
0
0
0
0
R1 Ro
0
1
0
0
0
0
0
0
P1
Po
0
1
0
7
0
7
001
o
1
0
1
0
1
0
0
0
1
0
1
0
0
R1 Ro
0
0
1
1
0
0
0
0
0
0
1
2
No zero
2
Zero
2
2
Zero
R1 Ro
32
2
R1 Ro
59
2
4
Offset
16
16
(rp) - 1
0
0
P1 Po
0
0
1
1
7
EA
(EA) -
(EA) - 1
1
0
1
0
1
0
0
1
7
o
o
o
o
o
0
0
0
1
1
0
0
Decimal Adjust Accumulator
CLC
(CY)-O
Iii
1
1
0
0
4
0
00101
0
000
00101
0
8
o
8
Carry
Borrow
2
Others
(CY) -1
No zero
Carry
2
4
Offset
(rp) -
DAA
No borrow
2
001
rp
STC
No carry
0
Po
"
2
010
o
o
(rp) + 1
(r2) - 1
1
1
...,
Q)
....
o
~
....
2
2
Borrow
~
~
Instruction Set (cont)
Operation Code
B1
B2
B3
Mnemonic
Operand
7
Operation
Others [conti
NEGA
Rotate and Shift
RLD
RRD
RLL
r2
(r2m + 1) - (r2 m), (r2o) (CY) - (r27)
RLR
r2
(r2m - 1) - (r2m),(r27) (CY) - (r2o)
SLL
SLR
r2
r2
(r2m + 1) - (r2m),(r20) - 0, (CY)
(r2m - 1) +- (r2m),(r27) +- 0, (CY)
SLLC
SLRC
r2
r2
(r2m + 1) +- (r2m),(r20)
(r2m - 1) +- (r2m),(r27)
DRLL
EA
(EAn + 1) +- (EAn},{EAO)
(CY) +- (EA1S)
DRLR
EA
(EAn -1) +- (EA n},{EA1S)
(CY) +- (EAo)
DSLL
EA
(EAn + 1) +- (EAn),(EAo)
(CY) + - (EA1S)
DSLR
EA
(EAn - 1) +- (EA n},{EA1S)
(CY) +- (EAo)
6
5
4
0
0
3
2
1
0
7
6
0
0
0
5
B4
4 3
2
1
1
1
0
1
1
0
0
(A)-(A)+1
0
Rotate left digit
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
Rotate right digit
0
1
1
1
0
0
1
(CY),
0
1
0
1
0
0
0
0
0
1
1
0
(CY),
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
+-
+-
0, (CY)
0, (CY)
+-
(CY),
+-
+-
(CY),
0,
+-
0,
++++-
2
17
2
17
2
1 R1 Ro
8
2
o
R1 Ro
8
2
0
1 R1 Ro
0
0
R1 Ro
0 0
8
8
8
8
8
2
2
2
0
8
2
8
2
8
2
Lowaddr
10
3
0
4
1
1
jdisp
10
10
2
0
0
0
8
2
0 0 0
High addr
0
0
16
3
0
17
2
13
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1 0 1
High addr
0
0
0
(r27)
(r2o)
0
1
1
Bytes
8
0
0
(r27)
(r20)
State(l)
1
1
0
0
0
0
0
0
R1 Ro
R1 Ro
0
0
0
Skip
Condition
~
n
2
Carry
Carry
2
Jump
JMP
*word
word
*word
JEA
Call
CAll
*word
CALB
CALF
~
cO
co
+-
(PCH)
JB
JR
JRE
(PC)
*word
(PC)
(PC)
(PC)
word
+-
+++-
(B),(PCl)
+-
(C)
(PC) + 1 + jdisp 1
(PC) + 2 + jdisp
(EA)
0
0
0
0
0
0
0
0
0
0 0
jdisp1
1
((SP) -1) + - ((PC) + 3)H,
((SP) - 2) + - ((PC) + 3)l
(PC) - word, (SP) +- (SP) - 2
0
1
0
((SP) -1) +- ((PC) +2)H,
((SP) - 2) - ((PC) + 2)l
(PCH) +- (B), (PCl) - (C),
(SP) +- (SP) - 2
0
1
0
0
1
((SP) - 1) + - ((PC) + 2)H,
((SP) - 2) - ((PC) + 2)l
(PC1S-11) - 00001,
WC10-0) +- fa, (SP) +- (SP) - 2
0
1
1
1
1-
0
0
0
0
1
0
0
Lowaddr
1
1:::
0
0
1
0
fa
~
1
0
0
1
"C--..
...
~
...
CD
0
~
I
"
1::::
Instruction Set (cont)
Operation Code
0
B1
B2
-
B3
Mnemonic
Operand
Operation
7
6
5
0
0
4
2
3
1
0
7
6
5
B4
4 3
2
1
0
State(1)
Bytes
Skip
Condition
Call (conti
CALT
word
SOFTI
((SP) -1) - ((PC) + 1)H,
((SP) - 2) - ((PC) + 1)L
(PGLl - (128 + 2ta),(PCH) (129 + 2ta),(SP) - (SP) :..- 2
((SP) - 1) - (PSW),((SP) - 2) ((PC) + 1)H,((SP) - 3) - ((PC) + 1)L,
(PC) - 0060H,(SP) - (SP) - 3
•
Return
0
ta
1
0
16
0
1
0
16
0
10
RET
(PCLl - ((SP)) , (PCH) (SP) - (SP) + 2
+ 1)
0
0
0
RETS
(PCLl- ((SP)),(PCH) - ((SP) + 1)
(SP) - (SP) + 2,(PC) -{PC) + n
0
0
0
RET!
(PCtl- ((SP)),(PCH) - ((SP) + 1)
(PSW) - ((SP) + 2), (SP) - (SP) + 3
0
bit, wa
0
((SP)
0
0
0
......
CD
...~...
Unconditional
Skip
10
0
"a
...
13
Skip
Bit
0 1 1 B2
Offset
So
B1
10
2
Bit Test
CPU Control
SK
Skip if f = 1
Skip iff =0
SKN
SKIT
irf
Skip if irf = 1, then reset irf
SKNIT
irf
NOP
Skip if irf = 0
Reset irf if irf = 1
No operation
EI
Enable interrupt
01
Disable interrupt
Halt
HLT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F2 F1 Fo
F2 F1 Fo
0
0
1
0
0
0
0
0
0
1
f =1
f=O
irf = 1
2
irf =0
13
12
11
10
14
13
12
11
10
8
0
0
2
2
2
14
0
0
8
8
8
0
1
4
4
4
1
11
2
Notes:
(1) In the case of skip condition,the idle states are as follows:
1-byte instruction: 4 states
2-byte instruction (with *): 7 states
3-byte instruction (with *): 10 states
2-byte instruction: 8 states
3-byte instruction: 11 states
4-byte instruction: 14 states
(2) B2 (Data): rpa2
(4) B3 (Data): rpa3
III
= D + byte, H + byte.
(3) Right side of slash (I) in states indicates case rpa2,
rpa3 = D + byte, H + A, H + B, H + EA, H + byte.
= D + byte, H + byte
~
~
NEe
NEe Electronics Inc.
Description
ThepPD78C10,pPD78C11, andpPD78C14 single-chip
microcomputers integrate sophisticated on-chip peripheral functionality normally provided by external
components. The devices' internal 16-bit ALU and data
paths, combined with a powerful instruction set and
addressing, make them appropriate in data processing
as well as control applications. The devices integrate a
16-bit ALU, 4K-byte ROM, 256-byte RAM with an 8channel AID converter, a multifunction 16-bit timerl
event counter, two 8-bit timers, a USART, and two
zero-cross detect inputs on a single die, allowing their
use in fast, high end processing applications. This
involves analog signal interface and processing.
The pPD78C11 is a 4K-byte mask ROM high-volume
production device embedded with custom customer
program. The pPD78C14 is a 16K-byte mask ROM
device. The pPD78C10 is a ROM-less version for
prototyping and small volume production.
pPD78C10/C11/C14
a-BIT, SINGLE-CHIP
CMOS MICROCOMPUTERS
WITH A/D CONVERTER
Ordering Information
Part Number
J,lPD78C10G-36
J,lPD78C11G-36
J,lPD78C14G-36
64-pin plastic OUIP
12 MHz
J,lPD78C10CW
J,lPD78C11CW
J,lPD78C14CW
64-pin plastic shrink DIP
12 MHz
J,lPD78C10G-1 B
J,lPD78C11 G-1 B
J,lPD78C 14G-1 B
64-pin plastic miniflat
12 MHz
J,lPD78C10L
J,lPD78C11L
J,lPD78C14L
68-pin PLCC
(available 3086)
12 MHz
Pin Configurations
64-Pin QUIP or Shrink DIP
III
Voo
Features
D CMOS technology
- 2.5 to 6.0 V operating range
- 30 mA operating current
D Complete single-chip microcomputer
-16-bit ALU
- 4K x 8 ROM (78C11)
- 16K x 8 ROM (78C14)
- 256-byte RAM
D 441/0 lines
D Two zero-cross detect inputs
D Two 8-bit timers
D Expansion capabilities
- 8085A bus-compatible
- 60K-byteexternal memory address range
D 8-channel, 8-bit AID converter
- Autoscan mode
- Channel select mode
D Full duplex USART
- Synchronous and asynchronous
D 154 instructions
- 16-bit arithmetic, multiply and divide
- HALT and STOP instructions
D 1 ps instruction cycle time (12 MHz operation)
D Prioritized interrupt structure
- 3 external
- 8 internal
D Standby function
D On-chip clock generator
D 64-pin plastic QUIP, shrink DIP, or flatpack
Max Frequency
of Operation
Package Type
STOP
PA4
PDs
PAs
PD4
PA6
PF7
PF6
PB6
PB7
PC3/TI/INT2
PCs/COo
23
PC7/COl
NMI
INT1
ANs
MODEl
RESET
ANo
AVss
83-003817A
4-101
NEe
pPD78C10/C11/C14
Pin Configurations (cont)
Pin Identification (cont)
AVss
A/D converterpower supply ground
A/D converter analog inputs 0-7
S4
VAREF
A/D converter reference voltage
PD1
AVoo
AID converter power supply voltage
PDo
RD
Read strobe output
WR
Write strobe output
ALE
Address latch enable output
PFO-PF7
Port F I/O/Expansion memory address bus
(bits 8-15)
PDo-PD7
Port 0 I/O/Expansion memory address/
data bus
STOP
Stop mode control input
Voo
5 V power supply
......
IDU')~M
S2
1
PA7
0
PBo
PB1
48
P F7
PB2
PFs
PB3
PFs
7
4S
PF4
PBs
PF3
PBs
PF2
PB7
IlPD78C10/C11/C14
10
42
PF1
PCo/TxD
PFo
PC1/RxD
ALE
PC2/SCK
13
39
ViR
R5
PC3/T1/INT2
PC4/TO
PCs/CI
AVoo
1S
PCs/COo
AN7
PC7/C01
ANs
NMI
Ground
ANo-AN7
I~
PB4
Vss
~ '"
~ ~ '"
~ ~ "
~ ,C
> I~- C
~ C
~ C
~C
~C
~
Lf)oo:tMN,...OQO
PAs
Function
Symbol
64-Pin Miniflat
19
33
20
23
Pin Functions
PAo-PA7 [Port A]
ANs
32
Port A is an 8-bit three-state port. Each bit is independently programmable as either input or output.
Reset makes all lines of port A inputs;
83·003818A
PBo-PB7 [Port B]
Pin Identification
Symbol
Function
PortA I/O
Port B I/O
PColTxD
Port C I/O line O/Transmit data output
Port C I/O line 1/Receive data input
Port C I/O line 2/Serial clock I/O
Port C I/O line 3/Timer input/Interrupt
request 2 input
Port B is an 8-bit three-state port. Each bit is independently programmable as either input or output.
Reset makes all lines of port B inputs.
PCO-PC7 [Port C]
Port C is an 8-bit three-state port. Each bit is independently programmable as either input or output.
Alternatively, the lines of port C can be used as control
lines for the USART and timer. Reset puts all lines of
port C in port mode, input.
Port C I/O line 4/Timer output
PCS/CI
Port C I/O line 5/Counter input
Port C I/O lines 6, 7/Counter outputs 0,1
NMI
Nonmaskable interrupt input
INT1
Interrupt request 1 input
MODE1
Mode 1 input/Memory cycle 1 output
RESET
TxD [Transmit Data]. Serial data output terminal.
RxD [Receive Data]. Serial data input terminal.
Reset input
SCK [Serial Clock]. Output for the serial clock when
internal clock is used. Input for serial clock when
external clock is used.
MODEO
Mode 0 input/I/O/Memory output
TI [Timer Input]. Timer input terminal.
X1, X2
Crystal connections 1, 2
4-102
NEe
INT2 [Interrupt Request 2]. Falling-edge-triggered,
maskableinterrupt input terminal and AC-input, zerocross detection terminal.
TO [Timer Output]. The output of TO is a square wave
with a frequency determined by the timer/counter.
CI [Counter Input]. External pulse input to timer/event
counter.
COo, C01 [Counter Outputs 0, 1]. Programmable
rectangular wave outputs based on timer/event counter.
pPD78C10/C11/C14
MODE1, MODEO [Mode 1, 0]
The MODE1 and MODEO inputs select the memory
expansion mode. MODE1 also outputs the M1 Signal
during each opcode fetch. MODEO outputs the 10/M
signal.
VAREF [AID Converter Reference]
VAREF sets the upper limit for the A/D conversion
range.
AVoo [AID Converter Power]
PDo-PD7 [Port D]
This is the power supply voltage for the A/D converter.
Port 0 is an a-bit three-state port. It can be programmed
as either a bits of input or a bits of output. When
external expansion memory is used, port 0 acts as the
multiplexed address/data bus.
RD [Read Strobe]
PFo-PF7 [Port F]
Port F is an a-bit three-state port. Each bit is
independently programmable as an input or output.
When external expansion memory is used, port F
outputs the high-order address bits.
ANo-AN7
The RD output goes low to gate data from external
devices onto the data bus. RD goes high during reset.
Th ree-state.
WR [Write Strobe]
The WR output goes low to indicate that the data bus
holds valid data. It is a strobe signal for external
memory or I/O write operations. WR goes high during
reset. Three-state.
ALE [Address Latch Enable]
These are the eight analog inputs to the A/D converter.
AN 4 -AN 7 can also be used as a digital input for falling
edge detection.
The ALE output latches the address signal to the
output of PDQ-PO?
AVss [AID Converter Power Ground]
X1, X2 [Crystal Connections 1,2]
AVss is the ground potential for the A/D converter
power supply.
X1 and X2 are the system clock crystal oscillator
terminals. X1 is the input for an external clock.
NMI [Nonmaskable Interrupt]
Vss [Ground]
Falling-edge-triggered nonmaskable interrupt input.
Ground potential.
INT1 [Interrupt Request 1]
STOP [Stop Mode Control Input]
INT1 is a rising-edge-triggered, maskable interrupt
input. It is also an AC-input, zero-cross detection
terminal.
A low-level input on STOP stops the system clock
oscillator.
RESET [Reset]
+5 V power supply.
Voo [Power Supply]
When the RESET input is brought low, it initializes the
device.
4-103
III
~
NEe
pPD78C10/C11/C14
Block Diagram
X'=EJ
X2
Osc ..
PF 7 -PF o
(AB,s-AB.)
PC./TxD
Inc.lDec.
PC
SP
EA
PC,/RxD
PC,tSCK
V
NMI
12
A
C
Main
G.R.
0
H
INTl
A'
C'
PD 7 -PD o
(AD 7- ADo)
Program
Memory
[NotelJ
Data
Memory
(2S6-byte)
All.
G.R.
PC 3 /TI/INT2
PCs/CI
PCs/COo
PC 7 /CO,
VAAEF
AVoo
AVss
Note:
[lJ On-Chip ROM:
78Cl0: 0
78Cll: 4096 Bytes
78C14: 16,384 Bytes
AD WR
ALE MODEl MODEO
RESET
STOP
11
Voo
Vss
49-000634C
4-104
NEe
Functional Description
Memory Map
The pPD78C11 can directly address up to 64K bytes of
memory. Exceptforthe on-chip ROM (0-4095) and RAM
(65,280-65,335), any memory location can be used as
ROM or RAM. The memory map, figure 1, defines the 0
to 64K byte memory space for the pPD78C11. On-chip
ROM is located from 0-16,383 in the pPD78C14.
pPD78C10/C11/C14
Table 1.
Memory
Expansion
Analog Input Lines. ANa-AN? are configured as analog
input lines for on-chip A/D converter.
Port A, Port B, Port C, Port F. Each line of these ports
can be individually programmed as an input or output.
When used as I/O ports, a" have latched outputs and
high-impedance inputs.
Port D. Port D can be programmed as a byte input or a
byte output.
AN4-AN7. The high-order analog input lines, AN4-AN?,
can be used as digital input lines for falling-edge
detection.
Control Lines. Under software control, each line of port
C can be configured individually to provide control
lines for the serial interface, timer, and timer/counter.
Memory Expansion. In addition to the single-chip
operation mode, the pPD78C11 has four memory
expansion modes. Under software control, port D can
provide a multiplexed low-order address and data bus;
port F can provide a high-order address bus. Table 1
shows the relation between memory expansion modes
and the pin configurations of port D and port F.
Port Configuration
None
Port D
Port F
I/O port
I/O port
256 Bytes
Port D
Port F
Multiplexed address/data bus
I/O port
4K Bytes
Port D
Port Fo-F3
Port F4-F7
Multiplexed address/data bus
Address bus
I/O port
16K Bytes
Port D
Port Fo-F5
Port FS-F7
Multiplexed address/data bus
Address bus
I/O port
6DK Bytes
Port D
Port F
Multiplexed address/data bus
Address bus
Input/Output
The pPD78C10/C11/C14 has 8 analog input lines
(ANa-AN?), 44 digital I/O lines, five 8-bit ports (port A,
port B, port C, port D, port F), and 4 input lines
(AN 4-AN?).
Memory Expansion Modes and Port
Configurations
Timers
There are two 8-bit timers. The timers may be programmed independently or may be cascaded and used as a
16-bit timer. The timer can be software set to increment
at intervals of four machine cycles (1 ps at 12 MHz
operation) or 128 machine cycles (32ps at 12 MHz), or
to increment on receipt of a pulse at TI. Figure 2 is the
block diagram for the timer.
Timer/Event Counter
The 16-bit multifunctional timer/event counter (figure
3) can be used for the following operations:
•
•
•
•
•
Interval timer
External event counter
Frequency measurement
Pulse width measurement
Programmable square-wave output
4-105
11
~
NEe
pPD78C10/C11/C14
Figure 1.
Memory Map
Reset/Standby Release
Internal ROM
4,096 Bytes: 78C11
16,384 Bytes: 78C14
IROO
IR01
External
Memory
61,184 Bytes: 78C11
49,152 Bytes: 78C14
10H
IR02
18H
IR03
20H
IR04
28H
IR05
FEFFH
FFOOH
Internal RAM
256 Bytes x 8
FFFFH
001
SoftlNT
....
80H
LowADDR
81H
HighADDR
82H
LowADDR
83H
High ADDR
I
.
l"
BEH
LowADDR
BFH
COH
HighADDR
l"
User's Area
49-000635C
4-106
NEe
Figure 2.
JlPD78C10/C11/C14
Timer Block Diagram
PC.,TO
Timer 0
,---------,
Timer 1
r-----I
I
PC 3 1T1
I
I
I
----,
Timer/Event
Counter
I
I
Clear
Serial
Interlace
I
I
I
I
I
I
INTTo
INTT,
I
I
I
_ _ _ ...J
Internal Bus
Notes: 1 CL = 3/f (250ns: 12MHz operation).
f: System clock frequency (MHz).
49·000645B
4-107
NEe
pPD78C10/C11/C14
Figure 3.
Block Diagram for Timer/Event Counter
4CL-------,
PC.IClo-----,-------I---I
TO--+--.
PC 71CO,
INTEO
INTEl
INTEIN
Notes: 1 CL = 31f (25Ons: 12MHz operation).
f: System clock frequency (MHz).
49·000633C
8-Bit AID Converter
Analog/Digital Converter
• 8 input channels
• 4 conversion result registers
• 2 powerful operation modes
- Autoscan mode
- Channel select mode
• Successive approximation technique
• Absolute accuracy: 0.6% ±1/2 LSB
• Conversion range: 0 to 5 V
• Conversion time: 42 ps
• Interrupt generation
ThepPD78C10/C11/C14featuresan 8-bit, high-speed,
high-accuracy AID converter. The AID converter is
made up of a 256-resistor ladder and a successive
approximation register (SAR). There are four conversion result registers (CRo-CR3)' The 8-channel
analog input may be operated in either of two modes.
In the select mode, the conversion value of one analog
input is sequentially stored in CRo-CR3' In the scan
mode, the upper four channels or the lower four
channels may be specified. Then those four channels
will be consecutively selected and the conversion
results stored sequentially in the four conversion result
registers. Figure 4 shows the block diagram for the AID
converter. To prevent operation of the AID converter
and thus reduce power consumption, set VAREF = 0 V.
4-108
NEe
pPD78C10/C11/C14
Interrupt Structure
There are 11 interrupt sources. Three are external
interrupts and eight are internal. Table 2 shows 11
interrupt sources divided into six priority levels. See
figure 5.
Standby Function
ThepPD78C10/C11/C14 has two standby modes: HALT
and STOP. The HALT mode reduces power consumption to less than 50% of normal operating requirements, while maintaining the contents of on-chip
registers, RAM, and control status. The system clock
and on-board peripherals continue to operate, but the
CPU stops executing instructions. The HALT mode is
initiated by executing the HL T instruction. The HALT
mode can be released by any nonmasked interrupt or
by RESET.
Type B is initiated by inputting a low level on the STOP
input. Only RAM contents are saved, not the CPU
register contents. The OSCillator is stopped. The STOP
mode is released by raising STOP to a high level. The
oscillator stabilization time is fixed at 65 ms; 65 ms after
STOP is raised, instruction execution will begin at
location O. You can increase the stabilization time by
holding RESET low for the required time period.
AID Converter Block Diagram
Figure 4.
AVec
AVss
VAREF
AN,
AN,
AN,
AN,
AN,
AN,
AN,
AN,
i
i
The STOP mode reduces power consumption to less
than 0.1 % of normal operating requirements. There are
two STOP modes: type A and type B.
Type A is initiated by executing a STOP instruction. If
Vee is maintained within the operating range (2.5 to 6.0
V), on-board RAM and CPU register contents are
saved. If Vee is held above 2.0 V (but less than 2.5 V),
only on-board RAM is saved. The oscillator is stopped.
The STOP mode can be released by an input on NMI or
RESET. The user can program oscillator stabilization
time via timer 1. By checking the standby flag (SB), the
user can determine whether the processor has been in
the standby mode.
Table 2.
Interrupt
Request
Interrupt Sources
Interrupt
Address
Type of Interrupt
IROO
4
NMI (Nonmaskable interrupt)
Ext
8
INTTO (Coincidence signal from
timer 0)
Int
INTT1 (Coincidence signal from
timer 1)
IR02
16
Figure 5.
Interrupt Structure Block Diagram
Wi
INTTO
INTT1
INT1
INT2
INTEO
INTEl
INTEIN
INTAD
INTSR
INTST
ov
Internal/
External
IR01
INT1 (Maskable interrupt)
49-000632A
ER
S8
49-000642A
Ext
INT2 (Maskable interrupt)
IR03
24
INTEO (Coincidence signal from
timer I event counter)
Int
INTE1 (Coincidence signal from
timer levent counter)
IR04
32
IROS
40
INTEIN (Falling signal of CI and
TO counter)
Int/Ext
INTAD (AID converter interrupt)
INTSR (Serial receive interrupt)
Int
INST (Serial send interrupt)
4-109
NEe
pPD78C10/C11/C14
Universal Serial Interface
Zero-Crossing Detector
The serial interface can operate in one of three modes:
synchronous, asynchronous, and liD interface. The
liD interface mode transfers data MSB first, for easy
interfacing to certain NEC peripheral devices. Synchronous and asynchronous modes transfer data LSB
first. Synchronous operation offers two modes of data
reception: search and nonsearch. In the search mode,
data is transferred one bit at a time from the serial
register to the receive buffer. This allows a software
search for a sync character. In the nonsearch mode,
data transfer from the serial register to the transmit
buffer occurs eight bits at a time. Figure 6 shows the
universal serial interface block diagram.
The INT1 and INT2 terminals (used common to TI and
PC3) can detect the zero-crossing point of lowfrequency AC signals. When driven directly, these pins
respond as a normal digital input. Figure 7 shows the
zero-crossing detection circuitry.
Figure 6.
Universal Serial Interface Block Diagram
The zero-crossing detection capability allows you to
make the 50-60 Hz power Signal the basis for system
timing and to control voltage phase-sensitive devices.
To use the zero-cross detection mode, an AC signal of
approximately 1-3 V AC (peak-to-peak) and a maximum
frequency of 1 kHz is coupled through an external
capacitor to the INT1 and INT2 pins.
For the I NT1 pin, the internal digital state is sensed as a
the rising edge crosses the average DC level,
when it becomes a 1 and INT1 interrupt is generated.
o until
For the INT2 pin, the state is sensed as a 1 until the
falling edge crosses the average DC level, when it
becomes a 0 and INT2 interrupt is generated.
Figure 7.
PC,/RxD
Zero-Crossing Detection Circuit
IINT1
C
I iNT2 (PC3)
~r---~--~~---1~--~I~r--
49-000646A
83-003835A
4-110
NEe
pPD78C10/C11/C14
Absolute Maximum Ratings
Power supply voltages, Voo
Operating Conditions
-0.5 V to +7.0 V
----------------------------AVoo
AVss to Voo + 0.5 V
AVss
Input voltage, VI
Output voltage, Vo
Output current low, IOL
Output current low,
total for all pins
-40°C to +85°C
fXTAL::; 12 MHz
+5.0 V ±10%
-0.5 V to +0.5 V
-0.5 V to +7.0 V
-0.5 V to Voo+ 0.5 V
Capacitance
TA =25°C; Voo = Vss = 0 v
Limits
4.0 rnA
100 rnA
Parameter
Input capacitance
Output current high, IOH
-2.0 rnA
Output current high,
total for all pins
-SOmA
Reference input voltage, VAREF
Oscillating Frequency
Symbol
Min
Typ
Max
CI
10
Output
capacitance
Co
20
liD capacitance
CIO
20
Unit
Test
Conditions
pF Afe = 1 MHz.
Unmeasured
pF pins returned
to 0 V.
pF
-0.5 V to AVoo + 0.3 V
Operating temperature, TOPR
fXTAL::; 12 MHz
Recommended XTAL Oscillation Circuit
Storage temperature, TSTG
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
c = 10 pF
83-003282A
4-111
NEe
pPD78C10/C11/C14
Serial Operation
DC Characteristics
TA = -1Q°C to HOaC; Voo = +5.0 V ±50/0; Vss = 0 v
Limits
Parameter
Symbol
Input low
voltage
VIL1
Input high
voltage
Min
Typ
0
0.2
VOO
V Note 1 inputs.
VIH1
2.2
VOO
V All except X1,
X2, and Note
1 inputs.
Output low
voltage
VOL
Output high
voltage
VOH
Data
retention
voltage
VOOOR
0.8 Voo
Voo
0.45
V X1, X2, and
Note 1 inputs.
Max
Unit
ns (2)
IlS SCK output
2
tKKL
SCK width high
tKKH
t
420
ns SCK input (1)
200
ns SCK input (2)
900
ns SCK output
420
ns SCK input (1)
200
ns SCK input (2)
900
ns SCK output
tRxK
80
ns (1)
tKRX
80
ns (1)
V 10H = - 1OO IlA
RxD hold time after
SCK t
V STOP mode
SCK l TxD delay time
tKTX
VOO - 0.5
Test
Conditions
/lS SCK input (1)
tCYK
500
RxD set-up time to SCK
210
ns (1)
Note:
±200 /lA INT1, TI(PC3);
oV:S= VI:S= VOO
±10 IlA All except
INT, TI(PC3)
ov:s= VI :S=VOO
III
Output leakage ILO
current
±10 /lA
oV:s= Vo
:s= VOO
AVoo supply
current
Aloo
0.3
1.0
mA
VOO supply
current
1001
15
30
mA Operation mode
f = 12 MHz
1002
10
20
mA HALT mode
f = 12 MHz
15
IlA VOOOR = 2.5 V
10
50
/lA VOOOR=5V
±10%
1000R
Note:
(1) Inputs RESET, STOP, NMI, SCK, INT1, TI, and AN4-AN7.
4-112
Min
V 10L = 2.0 mA
V IOH= -1.0 mA
I nput current
Data retention
current
SCK cycle time
SCK width low
VOO -1.0
2.5
Symbol
Parameter
V All except Note
1 inputs.
VIL2
VIH2
Input leakage
current
Max Unit
0.8
0
Limits
. Test
Conditions
(1) 1x baud rate in asynchronous, synchronous, or I/O interface
mode.
(2) 16x baud rate or 64x baud rate in asynchronous mode.
Zero-Cross Characteristics
LImits
Parameter
Symbol
Min
Max
Unit
Zero-cross detection
input
VZX
1
1.8
VAC p_p
Zero-cross accuracy
Azx
Zero-cross detection
input frequency
fzx
0.05
±135
mV
1
kHz
Test
Conditions
Ac coupled
60-Hz sine
wave
NEe
pPD78C10/C11/C14
AC Characteristics
Read/Write Operation
TA = -40°C to +85°C; Voo = +5.0 V ± 10%; Vss = 0 v
limits
fXTAl = 12 MHz
Parameter
Symbol
Min
Max
Unit
RESET pulse width
tRP
10
J1S
Interrupt pulse width (iNT1, INT2)
tiP
3.0
J1S
10
J1S
NMI pulse width
Counter input pulse width
Test
Conditions (1)
500
ns
Event counter mode
4.0
J1S
Pulse width measurement mode
tTl
500
ns
X1 Input cycle time
tCYC
83
Address set-up to ALE!
tAL
65
ns
Address hold after ALE!
tLA
50
ns
Address to RD ! delay time
tAR
150
RD ! to address floating
tAFR
20
ns
Address to data input
tAD
360
ns
ALE! to data input
tLDR
215
ns
RD ! to data input
tRD
180
ALE! to RD ! delay time
tLR
35
ns
tRDH
0
ns
tRL
115
ns
tRR
280
ns
Data read
530
ns
Opcode fetch
Timer input pulse width
Data hold time to RD
RD
t
t to ALE t delay time
RD width low
tCI
250
ns
ns
ALE width high
tLL
125
ns
M1 Setup time to ALE!
tML
65
ns
M1 Hold time after ALE!
tLM
50
ns
101M Setup time to ALE!
tiL
65
ns
101M Hold time after ALE!
tLi
50
ns
tAW
150
ns
Address to WR
! Delay
ALE ! to data output
tLOW
195
WR ! to data output
tWD
100
ALE! to WR ! delay
Data set-up time to WR
Data hold time to WR
WR
t
t
t to ALE t delay time
WR width low
II
ns
ns
ns
tLW
35
ns
tDW
230
ns
tWDH
95
ns
tWL
115
ns
tww
280
ns
Note:
(1) Load capacitance: CL = 150 pF.
4-113
NEe
JlPD78C10/C111Cf~4
AI D Converter Characteristics
=
= AVss = 0 V; AVDD -0.5 V :::;VAREF:::;
TA -40°C to +85°C; Vss
AVDD; VDD - 0.5:::; AVDD
Symbol
Resolution
Min
Typ
Conversion
time
Sampling
time
tCONV
tSAMP
VIA
Analog
RAN
input impedance
VAREF current
IAREF
MinIMax
Min
tTl
6T
Min
tCI (2)
6T
Min
0.4% LSB TA = -10°C to
±1/2
+50°C
tCI (3)
48T
Min
tIP
36T
Min
0.6%
± 1/2 LSB
tAL
2T -100
Min
tLA
T -30
Min
tAR
3T -100
Min
7T - 220
Max
Max
Unit
Test
Conditions
Bits
567
tCYC 83 ns :::; tCYC :::;
110 ns
432
tCYC 110 ns :::; tCYC :::;
170 ns
tAD
tLOR
5T - 200
Max
96
tCYC 83 ns :::; tCYC :::;
110 ns
tRO
4T -150
Max
tLR
T -50
Min
tRL
2T -50
Min
72
Analog
input voltage
Calculating Expression
60T
8
Absolute
accuracy
Symbol
tRP
Limits
Parameter
Bus Timing Depending ontCYC
tCYC 110 ns:::; tCYc:::;
170 ns
0
VAREF
1000
1.5
3.0
4T - 50 (Data Read)
........... -------.--------.----7T - 50 (Opcode Fetch)
Min
V
tRR
Mn
tLL
2T -40
tML
2T -100
Min
tLM
T -30
Min
tiL
2T -100
Min
tLi
T -30
Min
tAW
3T -100
Min
tLOW
T+110
Max
tLW
T -50
Min
tow
4T -100
Min
tWOH
2T -70
Min
tWL
2T -50
Min
tww
4T -50
Min
rnA
tCYK
tKKL
Min
12T (SCK input) (1)
----------.----------------------------24T (SCK output)
Min
5T + 5 (SCK input) (1)
Min
···1·2·T·~·1·00·(SCK··~~t·p~t)
tKKH
51 + 5 (SCK input) (1)
Min
···12T·~·100·(SCK·output)
Note:
(1) 1x baud rate in asynchronous, synchronous, or I/O interface
mode.
T = tCYC = 1/fxTAL ·
The items not included in this list are independent of oscillator
frequency (fXTALl.
(2) Event counter mode.
(3) Pulse width measurement mode.
4-114
NEe
pPD78C10/C11/C14
Timing Waveforms
Read Operation
x,
-~
-JIIIIA
-- X
i(
ADDR.-ADDR'5
tAD
HtRDH
)
ADDRO ADDR7
l+- f-- t LL ______
--
~tAL--
RD
t lOR
I--tLA---oo
ALE
,.....,
1-
Data-in
I-tRL
l~tAFR
-If
tRD
tRR
j-tLR
tAR
MODEO [iO/M)
[Note 1)
~tIL _ _
r
I+tL~-I
Note:
[1) iO/M signal is output to the MODEO pin during a read or write of special
register[s) Sr-Sr2, if MOOEO is pulled up to VDD.
49-oo0543B
Write Operation
x,
, -... , - - - .....''\.,.....,'-_ __
AB'5-AB.-~"-'~~-------------------------------'"\
r'-_''''___--'__-:-_~___~---A..:D..:D..:R::..--A..:.D,;;.DR..:.,:;:,5-------------
(PF 7-PF o) .....
Data-out
t-------tDw------l
ALE
~------tww--------~
WR
MOOEO [161M]
[Note 1)
Note:
[1) jQ/M signal is outputto the MODEO pin during a read or write of special
register[sj Sr-Sr2, if MODEO is pulled up to Voo.
49-0oo639B
4-115
NEe
pPD78C10/C11/C14
Timing Waveforms (cont)
Opcode Fetch Operation
x,
AB'5- AB •
(PF7 -PFol
--
...ft_J
X
ADDR.-ADDR'5
lAD
AD7-ADo
(PD7 -PDol
ALE
r
-)
ADDRo-ADDR7
IROHI--l
"'
Opcode
.---jILDRI--ILA
_ILL
"J-------j+---IRL
-
-<
I - - - IRo -
- IAL-
RD
- ILR
~
IRR
IAR
MODE11M1)
[Note1J
~ILA"
! - - - IML -
Nole:
[1J M1 signal is oulpullo Ihe MODEl pin during Opcode Felch if MODE1 pin is
pulled up 10 Voo.
49·0005458
Serial Operation Transmit/Receive Timing
TXD ____~-----'l~--------------J,------------------
RxD
________J~__~----------~.~------------------
49-0005468
4-116
~EC
pPD78C10/C11/C14
Operand Format/Description
Format
Remarks
Description
r
r1
r2
~A,B,C,D,E,H,
sr
sr2
sr3
sr4
PA, PB, PC, PO, PF, MKH, MKL, ANM, SMH, SML, EOM,
ETMM, TMM, MM, MCC, MA, MB, MC,
MF, TxB, TMO, TM1, ZCM
PA, PB, PC, PO, PF, MKH, MKL, ANM, SMH, EOM, TMM, RxB,
CRO, CR1, CR2, CR3
PA, PB, PC, PO, PF, MKH, ANM, MKL, SMH, EOM, TMM
HMo, ETM1
ECNT, ECPT
rp
rp1
rp2
rp3
SP, B, 0, H
V,B,D,H,EA
SP, B, 0, H, EA
B, 0, H
rpa
rpa1
rpa2
B, 0, H, 0+ , H + , 0 -, H B, 0, H
B, 0, H, 0 +, H + , 0 -, H -, 0 + byte, H + A, H + B,
H + EA, H + byte
0, H, 0 + +, H + +, 0 + byte, H + A, H + B, H + EA,
H + byte
L
EAH,EAL,B,C,D,E,H,L
A, B, C
sr1
rpa3
wa
8-Bit immediate data
word
byte
bit
16-Bit immediate data
8-Bit immediate data
3-Bit immediate data
FNMI, FTO, FT1, F1, F2, FEO, FE1, FEIN, FAD, FSR, FST, ER,
OV, AN4, AN5, ANs, AN?, SB
v
SP = Stack Pointer
B= BC
0= DE
TxB = Tx Buffer
RxB = Rx Buffer
SMH = Serial Mode High
SML = Serial Mode Low
MKH = Mask High
MKL = Mask Low
ANM = A/D Channel Mode
CRo = A/D Conversion Result 0-3
to CR3
TxB = Tx Buffer
RxB = Rx Buffer
SMH = Serial Mode High
SML = Serial Mode Low
MKH = Mask High High
MKL = Mask Low
H=HL
V=VA
EA = Extended Accumulator
3. rpa-rpa3 (rp addressing)
Logical product (logical AND)
Logical sum (logical OR)
4. f (flag)
Description
Transfer direction, result
A
HMM = Timer/Event
Counter Mode
EOM = Timer/Event
Counter Output Mode
MM = Memory Mapping
TMo = Timer Register 0
TM1 = Timer Register 1
TMM = Timer Mode
HMo = Timer /Event
Counter Register 0
HM1 = Timer/Event Counter
Register 1
ZCM = Zero-Cross Mode
Control Register
B = (BC)
0= (DE)
H = (HL)
0+ = (DE) +
H -=(HL) +
D-=(DE) H -=(HL)-
Instruction Set Symbol Definitions
Symbol
ECNT = Timer/Event
Counter Upcounter
ECPT = Timer/Event
Counter Capture
2. rp-rp3 (register pair)
CY, HC, Z
irf
1. sr-sr4(special register)
PA = Port A
PB = Port B
PC = Port C
PO = Port 0
PF = Port F
MA = Mode A
MB = Mode B
MC = Mode C
MCC = Mode Control C
MF = Mode F
Exclusive OR
CY = Carry
Complement
5. irf (Interrupt flag)
Concatenation
NMI = NMI* Input
FTO = INTFTO
FT1 = INTFT1
F1 = INTF1
F2 = INTF2
FEO = INTFEO
FE1 = INTFE1
D++=(DE) ++
H++=(HL)++
o+ byte = (DE) + byte
H + A = (HL) + (A)
H + B = (HL) +(B)
H + EA = (HL) + (EA)
H + byte = (HL) + byte
HC = Half Carry
Z = Zero
FEIN = INTFEIN
FAD =INTFAD
FSR =INTFSR
FST = INTFST
ER = Error
OV = Overflow
AN4 to AN? = Analog Input 4-7
SB = Standby
4-117
E
!
1:::
Instruction Set
"a
Operation Code
....L
ex>
B1
Mnemonic
2
1
0
6
(r1)-(A)
(A)-(r1)
0
0
0
0
0
*sr,A
(sr)-(A)
*A,sr1
r,word
(A)-(sr1)
(r)-(word)
0
0
0
1
0
0
1
word,r
(word)-(r)
0
1
*r,byte
(r) - byte
set L1 if r = A
set LO if r = L
0
1 1
0
0 0
0
Lowaddr
1 1 0 0 0 0
Lowaddr
0 1 R2 R1 Ro
0
1
sr2,byte (sr2) -
byte
MVIW
*wa, byte ((V)e(wa)) -
MVIX
STAW
LDAW
STAX
LDAX
EXX
*rpa1,byte
*wa
*wa
*rpa2
*rpa2
EXA
EXH
16·Bit Data Transfer
BLOCK
D
DMOV
5
B2
7
8·Bit Data Transfer
r1,A
MOV
A, r1
MVI
Operation
Operand
B3
4 3
byte
0
0
0
(rpa2) -- (A)
(A) - ((rpa2))
(B) ++ (B'),(C) ++ (C'),(D) ++ (D')
(E) ++ (E'),(H) ++ (H'),(L) ++ (L~)
(V) ++ (V'),(A) ++ (A'),(EA) ++ (EA')
++
(H'),(L)
++
1
0
(rpa1) -- byte
((V)e(wa)) - A
(A) - ((V)e(wa))
(H)
0
(L')
((DE)) - ((HL)),(DE) -- (DE + 1),
(HL) - (HL) + 1, (C) - (C)-1
End if borrow
rp3, EA (rp3Ll -- (EAL),(rp3H) - (EAH)
EA,rp3 (EAL) - (rp3L),(EAH) - (rp3H)
0
1
0
A3 0
A3 0
0 0
0
0
0
1
0
0
0
0
0
0
0
0
Data
1 0
Data
0 1
0
0
0
1
0
6
5
2
1
0
0
0
0
o A1 Ao
0 0 1
0 0 0
1 A2 A1 Ao
1 A2 A1 Ao
0 0 0 1
0
0
0
0
0
0
0
0
0
0
0
0
0
P1 Po
1 P1 Po
Bytes
10
10
17
2
2
4
17
4
7
2
14
3
Offset
13
3
Data
10
10
10
7/13(3)
7113(3)
2
2
2
2
2
S5 S4 S3 S2 S1 So
S5 S4 S3 S2 S1 So
1 0 1 R2 R1 Ro
High addr
1 1 1 R2 R1 Ro
1
0
0
High addr
Data
S3
0
0
0
o
Offset
Offset
Data (2)
Data (2)
S2 S1 So
~
m
n
....
~
..n
..n
4
1
0
State(l)
Skip
Condition
4
T2 T1 To
1 T2 T1 To
0
0
0
1
7
B4
4 3
"~
L1 = 1 and r = A
LO = 1 and r = L
4
4
4
13 x
(C+1)
4
4
~
~
Instruction Set (cont)
Operation Code
B1
Mnemonic
Operand
Operation
7
16-Bit Data Transfer [contI
DMOV
sr3, EA (sr3) - (EA)
EA,sr4 (EA) - (sr4)
SBCD
word (word) - (C), (word + 1) -
0
0
0
SDED
word
(word) -
(E), (word + 1) -
(D)
0
SHLD
word
(word) -
(L), (word + 1) -
(H)
0
SSPD
word
(word) -
(SPL),(word + 1) -
STEAX
rpa3
((rpa3)) -
LBCD
word
(C)
LDED
word
+-
(E) -
(SPH)
(EAL),((rpa3) + 1 -
(word),(B) (word),(D) -
(EAH)
0
LSPD
word
(SPd+- (word),(SPH) +- ((word) + 1)
0
LDEAX
rpa3
(EAL) +- ((rpa3)),(EAH) +- ((rpa3) + 1)
0
PUSH
rp1
LXI
((SP) - 1) +- (rp1H) ((SP) - 2) +- (rp1d
(SP) +- (SP) - 2
(rp1d+- ((SP)),(rp1H) +- ((SP) + 1)
rp1
(SP) - (SP) + 2
*rp2,word (rp2) +- (word)
set LO if rp2 = H
TABLE
(C) +- ((PC)+3+(A)),B -
8-Bit Arithmetic [Register)
(A)-(A)+(r)
ADD
A,r
(r) +-(r) + (A)
r,A
ADC
A,r
r,A
(A) +- (A) + (r) + (CY)
(r) +- (r) + (A) + (CY)
((PC)+3+(A)+ 1)
1
0 0
Lowaddr
1 0 0
0
(L) +- (word),(H) +- (word + 1)
B4
2
1 0 0
Lowaddr
0 0 1 0
Data(4)
0
word
B2
0 0
Lowaddr
1 0 0
Lowaddr
1 0 0
Lowaddr
(word + 1)
(word + 1)
5
0
0
0
LHLD
POP
!.....
(B)
6
B3
4
3
Lowaddr
1 0 0
Lowaddr
1 0 0
Lowaddr
0 0 1 0
Data(4)
0
State(l)
Bytes
14
14
2
2
20
4
0
20
4
20
4
20
4
0
1 1 1
High addr
0
0 0 1
High addr
0 1 C3 C2 C1 Co
14/20(3)
3
0
0
20
4
20
4
20
4
20
4
14/20(3)
3
1
0
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
0
1
o
0
0
0
0
0
Uo
V1 Vo
1 0
High addr
1 0 1
High addr
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
High addr
1 0 1
High addr
1 1 1
High addr
0
0
0
0
0
0
0 0 1
High addr
0
0
0 C3 C2 C1 Co
0 02 01 00
13
o
10
Skip
Condition
~
~
1:::
0
0
02 01 00
0 P2 P1 Po 0
High byte
0
0 0 1 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Low byte
0
0
1
0
0
0
1
0
0
0
0
0
10
3
0
17
2
0 R2 R1 Ro
0 R2 R1 RO
0 R2 R1 Ro
0 R2 R1 RO
8
8
8
0
0
2
2
2
2
LO = 1 and
rp2 = H
"a
~
CD
n...
~......
...~
~
CD
I!!I
~
~
,.a
Instruction Set (cont)
l::
I\)
Operation Code
o
~
Mnemonic
Operand
Operation
8·Bit Arithmetic [Register~ Icont)
ADDNC
A,r
(A) -- (A) + (r)
r,A
(r) -- (r) + (A)
SUB
A,r
(A) -- (A) - (r)
r,A
(r) -- (r) - (A)
SBB
A,r
(A) -- (A) - (r) -:- (CY)
r,A
(r) -- (r) - (A) - (CY)
SUBNB
A,r
(A) -- (A) - (r)
r,A
(r) -- (r) - (A)
ANA
A,r
(A) -- (A) A (r)
r,A
(r) -- (r) A (A)
ORA
A,r
(A) -- (A) V (r)
r,A
(r) -- (r) V (A)
XRA
A,r
(A) -- (A) V (r)
r,A
(r) -- (r) V (A)
GTA
A,r
(A) - (r) -:- 1
r,A
(r) - (A) - 1
LTA
A,r
(A) - (r)
r,A
(r)- (A)
NEA
A,r
(A) ~ (r)
r,A
(r)-(A)
EQA
A,r
(A) - (r)
r,A
(r)-(A)
ONA
A,r
(A) A (r)
OFFA
A,r
(A) A (r)
8·Bit Arithmetic (Memory)
ADDX
rpa
(A) -- (A) + ((rpa»
ADCX
rpa
(A) -- (A) + ((rpa» + (CY)
ADDNCX
rpa
(A) -- (A) + ((rpa»
SUBX
rpa
(A) -- (A) - ((rpa»
SBBX
rpa
(A) -- (A) - ((rpa» - (CY)
SUBNBX
rpa
(A) -- (A) - ((rpa»
ANAX
rpa
(A) -- (A) A ((rpa»
ORAX
rpa
(A) -- (A) V ((rpa»
7
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
654
o
B2
B4
321
0
1
1
0 0 0 0 0
0 0 000
0 0 0 0 0
0 0 000
000 0 0
0 0 0 0 0
0 0 0 0 0
0 0 000
000 0 0
0 0 0 0 0
000 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 000
100 0 0 0
000 0 0
0 0 0 0 0
1 0 0 0 0 0
1 0 0 0 0 0
1
1
1
1
1
011
1 1
011
011
011
1 1
011
o
a
o 0 0 0
100 0 0
1 0 0 0 0
100 0 0
1 0 0 0 0
1 0 0 0 0
1 0 0 0 0
1 0 000
7
o
1
o
654
3
2
o
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
0 0
1 0
0 0
00
1 0
1 0
0 1
1 1
A2
A2
A2
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
A1
A1
A1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
o
1
o
1
o
1
o
1
o
1
o
1
o
1
o
1
o
1
1
o
o
o
1 1
1 1
10
1 0
1 0
1
1
1
1
0
0
0
1
0
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ro
Ao
Ao
Ao
Ao
Ao
Ao
Ao
Ao
State(l)
Bytes
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
11
11
11
11
11
11
11
11
2
2
2
2
2
2
2
2
Skip
Condition
No carry
No carry
....
..n
~..
....
CD
~
No borrow
No borrow
No borrow
No borrow
Borrow
Borrow
No zero
No zero
Zero
Zero
No zero
Zero
No carry
No borrow
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operand
Operation
8-Blt Arithmetic (Memory) (cont)
XRAX
rpa
(A) GTAX
rpa
(A) LTAX
rpa
(A) NEAX
rpa
(A) EQAX
rpa
(A) ONAX
rpa
(A) A
OFFAX
rpa
(A) A
Immediate Data
ADI
*A,byte (A) r,byte (r) -
(A) V ((rpa))
((rpa)) - 1
((rpa))
((rpa))
((rpa))
((rpa))
((rpa))
+ byte
+ byte
(A)
(r)
7
6
5
4
o
o
o
o
o
o
o
~
B2
U
B4
3
2
o
o
o
o
o
o
o
0
0
o
o
000
o
o
0
0
0
7
0
0
000
0
0
0
0
0
0
0
0
654
3
o
o
o
Statell)
1
0 A2 A1 Ao
11
1
1
0
1
A2 A1 AO
11
A2 A1 Ao
1
0
1
1
1
1
1
A2 A1 AO
11
11
11
A2 A1 AO
11
1
1 A2 A1 Ao
1
o
o
o
o
0
0
o
0
0
0
0
2
A2 A1 Ao
Bytes
Skip
Condition
2
2
No borrow
2
Borrow
No zero
11
2
2
2
2
Zero
No zero
Zero
2
o
0
o
o
0
0 R2 R1 Ro
7
11
3
o
0
S3
o
0
0 S2 S1 So
20
3
1
0
o
0
o
o
1
S3
o
Data
~~
Data
sr2, byte (sr2) -
(sr2)
+ byte
0
Data
ACI
+ byte + (CY)
+ byte + (CY)
*A,byte
(A) -
(A)
r,byte
(r) -
(r)
o
o
010
1 0
7
2
0 R2 R1 Ro
11
3
o
S2 S1 So
20
3
Data
Data
sr2,byte (sr2) -
(sr2)
+ byte + (CY)
o
o
o
0
Data
ADINC
+ byte
+ byte
*A,byte
(A) -
(A)
r,byte
(r) -
(r)
o
o
0
o
0
1
1
0
o
0
0
No carry
0
o
0 R2 R1 Ro
7
11
2
o
3
No carry
S3
0
o
0 S2 S1 So
20
3
No carry
7
2
o
1
1
0
0
R2 R1 Ro
11
3
S3
1
1
0
0 S2 S1 So
20
3
7
2
Data
Data
sr2,byte (sr2) -
(sr2)
+ byte
o
o
o
0
Data
SUI
*A,byte
(A) -
(A) - byte
r,byte
(r) -
(r) - byte
o 1
01
1
0 0 1 1 0
10100
Data
Data
sr2,byte (sr2) -
(sr2) - byte
00000
D~
SBI
* A,byte
(A) -
(A) - byte - (CY)
r,byte
(r) -
(r) - byte - (CY)
o
o
1
1
1
1
1
1
0
0
1
1
1
0
0
001
0
0
Data
o
1
1
1
0 R2 R1 Ro
11
3
S3
1
1
1
0 S2 S1 So
20
3
Data
sr2,byte (sr2) -
(sr2) - byte - (CY)
o
1
D~
~
~
~
~
'l::::
"ma.....
..n
..n
....
~
~
~
.!...
1::
Instruction Set (cont)
I\)
I\)
Operation Code
Bl
Mnemonic
Operation
Operand
Immediate Data Icont)
SUINB
*A,byte (A) -- (A) - byte
r,byte (r) -- (r) - byte
ANI
ORI
XRI
0
*A,byte (A) -- (A) /\ byte
r,byte (r) -- (r) /\ byte
0
0
sr2,byte (sr2) -- (sr2) /\ byte
0
*A,byte (A) -- (A) V byte
r,byte (r) -- (r) V byte
0
0
sr2,byte (sr2) -- (sr2) V byte
0
*A,byte (A) -- (A) V byte
0
0
sr2,byte (sr2) -- (sr2) V byte
0
*A,byte
0
0
r,byte
LTI
(r) -- (r) V byte
(A) - byte - 1
(r) - byte-1
6
5
B3
3
4
sr2,byte (sr2) - byte - 1
0
*A,byte (A) - byte
r,byte (r) - byte
0
0
2
1
0
0
Data
0 0
0
Data
0
0
0
Data
1 0
1 0
Data
0 0
Data
1 0
0
7
0
0
0
0 0
1 0
Data
0 0
Data
1 0
1 0
5
B4
4 3
2
1
0
0 R2 R1 Ro
State(l )
Bytes
7
2
11
3
Skip
Condition
No borrow
No borrow
"a--a
CD
n
"""
~
n
~
~
0
0
S3
0
0 S2 S1 So
20
3
Data
0 1 R2 R1 Ro
7
2
11
3
0
S2 S1 So
20
3
0
Data
1 1 R2 R1 Ro
11
3
3
No borrow
'"n
~
1
0
0
0
0
S3
0
0
0
0
~
7
S3
0
0
S2 S1 So
20
0
0
0
Data
1 0 R2 R1 Ro
11
3
~O
0
0 S2 S1 So
20
3
0
1 0
Data
0 0
Data
0
6
Data
0
0
Data
0
0
sr2,byte (sr2) -- (sr2) - byte
r,byte
GTI
7
B2
7
1
0
2
0
0
Data
0 1 R2 R1 Ro
7
0
11
3
No borrow
No borrow
0
0
S3
0
0
S2 S1 So
14
3
No borrow
2
0
0
0
Data
1 1 R2 R1 RO
7
0
11
3
Borrow
Borrow
3
Borrow
No zero
No zero
1
Data
sr2,byte (sr2) - byte
NEI
*A,byte (A) - byte
r,byte (r) - byte
0
0
0
0
Data
0
0
S3
0
S2 S1 So
14
0
0
1
0
1
0
2
1
Data
0 1 R2 R1 Ro
7
0
11
3
Data
,II
~
~
Instruction Set (cont)
Operation Code
B1
Mnemonic
Operand
Operation
7
6
5
B3
4 3
B2
2
1
0
7
6
5
B4
4 3
2
0
S2 S1 So
14
7
2
Zero
1 R2 R1 Ro
11
3
Zero
S2 S1 So
14
3
Zero
1
0
State(l )
Bytes
Skip
Condition
Immediate Data (cont)
NEI
sr2,byte (sr2) - byte
0
0
0
S3
3
No zero
~
~
Data
EQI
*A,byte
(A) - byte
0
0
1
Data
r,byte
(r) - byte
0
0
Data
0
0
1
0
0
0
sr2,byte (sr2) - byte
0
S3
Data
ONI
*A,byte
r,byte
(A) /\ byte
(r) /\ byte
0
0
0
1
7
0
0
0
Data
0 1 R2 R1 Ro
11
3
No zero
No zero
0
S3
0
S2 S1 So
14
3
No zero
2
Zero
1 R2 R1 Ro
11
3
Zero
S2 S1 So
14
3
Zero
0
0
14
3
0
0
14
3
0
0
14
3
14
3
14
3
14
3
14
3
Data
sr2,byte (sr2) /\ byte
0
0
0
Data
OFFI
*A,byte (A)/\byte
r,byte (r) /\ byte
1
0
1
1
0
0
0
Data
0
1
Data
(sr2) /\ byte
0
0
0
Data
0
0
S3
Working Register
ADDW
wa
(A) -
(A)
+ ((V)e(wa))
0
0
0
0
0
0
Offset
ADCW
wa
(A) -
(A)
+ ((V)e(wa)) + (CY)
0
1
0
0
0
0
0
Offset
ADDNCW
wa
(A) -
(A)
+ ((V)e(wa))
0
1
0
0
0
No carry
l::
Offset
SUBW
wa
(A) -
(A) - ((V)e(wa))
SBBW
wa
(A) -
(A) - ((V)e(wa)) - (CY)
1
0
0
Offset
1 0 1
0
0
0
0
0
0
0
0
"--a
C
CD
Offset
SUBNBW
wa
(A) -
(A) - ((V)e(wa))
1
0
0
Offset
ANAW
wa
(A) -
(A) /\ ((V)e(wa))
0
1
0
0
0
Offset
~
I
-I.
0
0
0
0
No borrow
n
...
0
""......n
Ci...
~
I\:)
c.v
~
~
~
Instruction Set (cont)
I\:)
~
Operation Code
Bl
B2
B3
Mnemonic
Operand
Working Register (contI
ORAW
wa
XRAW
wa
Operation
(A) (A) -
(A) V ((V)e(wa))
(A) V ((V)e(wa))
7
(A) - ((V)e(wa)) - 1
0
LTAW
wa
(A) - ((V)e(wa))
0
NEAW
wa
(A) - ((V)e(wa))
0
EQAW
wa
(A) - ((V)e(wa))
0
ONAW
wa
(A) /\ ((V)e(wa))
0
OFFAW
wa
(A) /\ ((V)e(wa))
0
((V)e(wa)) /\ byte
ORIW
*wa,byte ((V)e(wa)) -
((V)e(wa)) V byte
GTIW
*wa,byte ((V)e(wa)) - byte - 1
4
0
3
0
Offset
1 0
0
wa
*wa,byte ((V)e(wa)) -
5
0
GTAW
ANIW
6
Offset
1 0
Offset
0
0
0
0
0
0
0
14
3
0
0
0
0
0
0
0
14
3
~
n...
'-n
0
0
7
0
0
0
0
0
0
0
0
0
0
0
0
1 0
Offset
0
0
0
0
0
0
0
0
Data
1 0
Data
2
1
0
Statell)
Bytes
0
0
0
14
3
No borrow
0
0
0
14
3
Borrow
0
0
0
0
14
3
No zero
0
0
0
0
14
3
Zero
0
0
0
0
14
3
No zero
0
0
14
3
Zero
Offset
19
3
0
Offset
19
3
0
0
n
...
...
~
0
0
0
0
0
0
0
Offset
13
3
No borrow
0
Data
1 0
Data
0
Offset
13
3
Borrow
*wa,byte ((V)e(wa)) - byte
0
NEIW
*wa,byte ((V)e(wa)) - byte
0
0
0
0
Offset
13
3
No zero
0
Data
1 0
0
Offset
13
3
Zero
0
Offset
13
3
No zero
0
Offset
13
3
Zero
*wa,byte ((V)e(wa)) - byte
CD
5
0
Skip
Condition
LTIW
EQIW
"...
6
1
0
1 0
Offset
1 0
Offset
1 0
Offset
1 0
Offset
0
2
a
-.a
B4
4 3
Data
ONIW
*wa,byte ((V)e(wa)) /\ byte
0
0
0
0
Data
OFFIW
*wa,byte ((V)e(wa)) /\ byte·
III
0
0
1 0
Data
~
~
Instruction Set (cont)
Operation Code
B1
B2
U
Mnemonic
Operand
16-Bit Arithmetic
EADD
EA,r2
DADD
EA,rp3
DADC
EA,rp3
DADDNC
EA,rp3
ESUB
EA,r2
DSUB
EA,rp3
DSBB
EA,rp3
DSUBNB
EA,rp3
DAN
EA,rp3
DOR
EA,rp3
DXR
EA,rp3
DGT
EA,rp3
DLT
EA,rp3
DNE
EA,rp3
DED
EA,rp3
DON
EA,rp3
DOFF
EA,rp3
Multiply /Divide
MUL
r2
DIV
r2
Increment/Decrement
INR
r2
INRW
*wa
INX
DCR
DCRW
DCX
!
Others
DAA
STC
CLC
Operation
(EA) -
(EA) + (r2)
(EA) (EA) -
(EA)
(EA)
(EA)
(EA)
(EA)
(EA)
(EA)
-
(EA) + (rp3)
(EA) - (r2)
(EA) - (rp3)
(EA) - (rp3) - (CY)
(EA) - (rp3)
(EA)
(EA)
(EA)
(EA)
(EA)
-'-
+ (rp3)
+ (rp3) + (CY)
(EA) II (rp3)
(EA) V (rp3)
(EA) V (rp3)
(rp3) - 1
(rp3)
(EA) - (rp3)
(EA) - (rp3)
(EA) II (rp3)
(EA) II (rp3)
x (r2)
+ (r2), (r2) - Remainder
(EA) -
(A)
(EA) -
(EA)
(r2) - (r2) + 1
((V)e(wa)) - ((V)e(wa))
B4
7654320
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
1
o
o
1
0
0
1
0
0
o
o
1
0 0 0
1 0 0
1 0 0
1 0 0
000
1 0 0
1 0 0
2
o
o
o
0
0
0 R1 RO
0
0
0
1
1
1
0
0
Po
Po
Po
1
0
0
0
0
0
1 P1
1 P1
1 P1
0 R1
1
0
P1
P1
P1
P1
P1
P1
P1
P1
Po
Po
Po
Po
Po
Po
Po
Po
1
o
1
0
1
o
0
0
o
0
0
0
0
0
0
1
1
0
0
000
o 0
001
010
0
0
o
1
0
0
1
1
1
0
0
0
0
0
0
000
000
0
0
0
1
0
0 R1 Ro
0 0 0
0 1 0
0 0 0
0 R1 Ro
rp
EA
r2
*wa
(rp) - (rp) + 1
(EA) - (EA) + 1
(r2) - (r2) - 1
((V)e(wa)) - ((V)e(wa)) -1
0
1
0
0
0
1
0
0
0
0
rp
EA
(rp) - (rp) - 1
(EA) - (EA) - 1
0
1
0 P1 Po
0 1 0
0
1
0
0
1
0
1
1
Decimal Adjust Accumulator
(CY)-1
(CY)-O
o
o
o
1
1
1
1 0 0
001
001
3
1
1
1 0 0
0 1 0
0 P1 Po
0 1 0
1 0 1
+1
654
1
0
o
o
o
o
o
7
0 0
000
000
o
0
1
o
o
0
0
0
1
o
1
RO
1
P1 Po
1 P1 Po
P1 Po
1 P1 Po
1
1
1 R1 Ro
1 R1 Ro
1
o
o
0
State(1)
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
32
59
4
16
7
7
4
Offset
Offset
16
Bytes
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
I\)
CJ1
II
8
8
No carry
No borrow
No borrow
Borrow
No zero
Zero
No zero
Zero
Carry
2
Carry
,.
'l:::
2
4
0
0
~
~
2
2
7
7
00101
00101
Skip
Condition
2
2
Borrow
Borrow
a
--a
..
~..
....
CD
n
~
!
,.o
Instruction Set (cont)
1:::
N
0>
Operation Code
Mnemonic
765
4
(A)-(A)+1
o
Rotate left digit
Operation
Operand
Others (cont)
NEGA
Rotate and Shift
RLD
RRD
B1
B2
~
B4
0
7
654
0
000
o
0
1
1
1
001
001
000
000
o
0
1
001
1
001
000
o
0
o
3
2
320
o
2
0
17
100
17
r2
(r2m + 1) - (r2m), (r2o) (CY) - (r27)
(CY),
RLR
r2
(r2 m-1) - (r2m),(r27) (CY) - (r2o)
(CY),
o
1
0
0
o
0
o
0
SLL
r2
(r2 m+ 1) -
(r2m),(r20) -
0, (CY) -
(r27)
0
0, (CY) -
(r2o)
0
1
0
0
SLLC
r2
SLRC
DRLL
r2
EA
(r2 m+ 1) - (r2m),(r20) - 0, (CY) (r2m - 1) - (r2m),(r27) - 0, (CY) (EAn + 1) - (EAn),(EAO) - (CY),
(CY) - (EA15)
(r2ol
o
o
o
o
0
(r2m),(r27) -
0
0
1
(r2m -1) -
10
1 0
0
r2
o
o
o
o
o
000
SLR
DRLR
EA
DSLL
EA
(EAn - 1) - (EAn),(EA15) - (CY),
(CY) - (EAo)
(EAn + 1) +- (EAn),(EAO) - 0,
(CY) - (EA15)
DSLR
EA
(EAn - 1) - (EAn),(EA15) (CY) - (EAo)
Jump
JMP
·word
(PC) -
0,
word
(r27)
1
1
0
1 R1 Ro
8
2
2
2
o
0 R1 Ro
8
2
1 R1 Ro
8
0 R1 Ro
8
2
2
2
2
2
1
1
0
0
0
0
1 R1 Ro
8
0
0
1
0
0
0 R1 Ro
1 0 .0
8
o
0
1
000
o
1
1
0
0
0
8
2
0
000
o
1
001
0
8
2
0
000
o
1
0
0
8
2
10
3
1
0
0
1
0
0
1
001
000
000
o
o
0
o
o
o
o
o
o
1
0
1
0
0 0
jdisp1
0
.....
CD
...on
"-
RLL
000
000
Bytes
8
o
o
o
Rotate right digit
State(1)
Skip
Condition
0
0
0
Lowaddr
0
n
..."-...
....
n
Carry
Carry
High addr
JB
JR
JRE
JEA
(PCH) - (B),(PCLl -- (C)
(PC) - (PC) + 1 + jdisp 1
o
word
·word
(PC) -
(PC) + 2 + jdisp
(PC) -
(EA)
o
o
3)H,
3)l
(SP) - 2
2) H,
2)l
(C),
((SP) -1) - ((PC) + 2)H,
((SP) - 2) - ((PC) + 2)l
(PC15-11) - 00001,
(PC1O-0) - fa, (SP) - (SP) - 2
o
0
1
+--
1
1
0
0
o
1
0
o
1
001
o
1
1
0
0
1
4
10
8
2
2
Lowaddr
16
3
00101001
17
2
fa
13
jdisp
1
1
o
0
0 0 0
High addr
0
0
o
0
1
0
10
1
000
Call
CALL
·word
CALB
CALF
·word
((SP) - 1) '- ((PC) +
((SP) - 2) - ((PC) +
(PC) - word, (SP) ((SP) - 1) - ((PC) +
((SP) - 2)- ((PC) +
(PCH) - (B), (PCl) (SP) - (SP) - 2
dl
1
000
1 -
~
~
Instruction Set (cont)
Operation Code
B2
81
Mnemonic
7
Operation
Operand
6
5
0
0
B4
B3
4 3
2
1
0
7
6
5
4
3
2
1
0
State(l)
Bytes
Skip
Condition
Call (conti
CALT
word
((SP) - 1) - ((PC) + 1)H,
((SP) - 2) - ((PC) + 1) l
(PCd + - (128 + 2ta),(PCH) (129 + 2ta),(SP) - (SP) - 2
((SP) - 1) - (PSW),((SP) - 2) ((PC) + 1)H,((SP) - 3) - ((PC) + 1)l,
(PC) + - 0060H,(SP) - (SP) - 3
SOFTI
ta
0
0
16
0
1
0
16
0
0
0
10
~~
Return
RET
(PCd- (SP)),(PCH) (SP) - (SP) + 2
+ 1)
0
RETS
(PCl) - ((SP)),(PCH) - ((SP) + 1)
(SP) - (SP) + 2,(PC) - (PC) + n
0
RETI
(PCl) -- ((SP)),(PCH) - ((SP) + 1)
(PSW) - «(SP) + 2), (SP) - (SP) + 3
0
bit, wa
0
((SP)
10
0
0
0
Unconditional
Skip
13
0
Skip
Bit
1 1 B2
B1
Offset
Bo
Bit Test
10
CPU Control
SK
Skip iff= 1
0
0
0
0
0
0
0
0
SKN
Skip if f = 0
0
0
0
0
0
0
0
0
0
SKIT
irf
Skip if irf = 1, then reset irf
0
0
0
0
0
0
0
SKNIT
irf
Skip if irf = 0
Reset irf if irf = 1
0
0
0
0
0
0
0
NOP
No operation
0
0
0
0
0
0
EI
Enable interrupt
01
HLT
STOP
Disable interrupt
0
1
0
1
Halt CPU operation
0
1
0
Stop system clock
0
0
0
0
1
0
0
0
F2 F1
Fo
8
2
f=1
F2 F1
FO
8
2
f=O
14
13
12
11
10
8
2
irf=1
14
13
12
11
10
8
2
irf=O
4
4
4
0
1
0
0
0
0
0
0
0
0
0
0
"a
12
0
0
't::
0
12
--I
2
Q)
Notes:
(1) In the case of skip condition, the idle states are as follows:
2-byte instruction (with *): 7 states
1-byte instruction: 4 states
3-byte instruction (with *): 10 states
2-byte instruction: 8 states
4-byte instruction: 14 states
3-byte instruction: 11 states
(2) B2 (Data): rpa2 = D + byte, H + byte.
(3) Right side of slash (/) in states indicates case rpa2, rpa3 = D + byte, H
H + B, H + EA, H + byte.
(4) B3 (Data): rpa3 = D + byte, H + byte
~
~
I\)
~
m
+ A,
n....
0
"....n....
"n....
~
pPD78C10/C11/C14
4-128
NEe
NEe
NEe Electronics Inc.
Description
pPD7810H/11H
8-BIT, SINGLE-CHIP
NMOS MICROCOMPUTERS
WITH A/D CONVERTER
Pin Configuration
The pPD7810H and pPD7811 H single-chip microcomputers integrate sophisticated on-chip peripheral
functionality normally provided by external components. The devices' internal 16-bit ALU and data paths,
combined with a powerful instruction set and addressing, make thepPD7810H/11 H appropriate in data
processing as well as control applications. The devices
integrate a 16-bit ALU, 4K-ROM, 256-byte RAM with an
8-channel AID converter, a multifunction 16-bit timerl
event counter, two 8-bit timers, a USART, and two
zero-cross detect inputs on a single die, allowing their
use in fast, high-end processing applications. This
involves analog signal interface and processing.
The pPD781 OH/11 H are high-speed versions of the
pPD7810/11. The pPD7811 H is the mask-ROM high
PC.
pc,
pc.
pc.
pc.
volume production device embedded with custom
customer program. The pPD7810H is a ROM-less
version for prototyping and small volume production.
D NMOS silicon gate technology requiring +5 V power
supply
o Complete single-chip microcomputer
-16-bit ALU
-4Kx8 ROM
-256-byte RAM
D 44 1/0 lines
D Two zero-cross detect inputs
D Two 8-bit timers
D Expansion capabilities
-8085A bus compatible
-60K-byte external memory address range
o 8-channel, 8-bit AID converter
-Autoscan mode
-Channel select mode
D Full duplex USART
-Synchronous and asynchronous
o 153 instructions
-16-bit arithmetic, multiply and divide
o 1 ps instruction cycle time
o Prioritized interrupt structure
-3 external
-8 internal
o Standby function
D On-chip clock generator
D 64-pin plastic QUIP, shrink DIP
E
pC s
Features
pc.
PC 7
NMI
INT1
MODEl
MODEO
Vss ____________
49-oQl334A
Ordering Information
Part Number
Package Type
Max Frequency
of Operation
pPD7810HG-36
pPD7811 HG-36
64-pin plastic QUIP
15 MHz
pPD7810HCW
pPD7811HCW
64-pin plastic shrink DIP
15 MHz
4-129
t-lEC
f..lPD781 OH/11 H
Pin Identification
No.
1-8
Symbol
PCO-PC7 [Port C]
Function
PAo-PA7
Port A I/O
9-16
PBo-PH7
Port B I/O
17
PCo/TxO
Port C I/O line O/Transmit data output
18
PC1/RxO
Port C I/O line 1/Receive data input
19
PC2/SCK
Port C 110 line 2/Serial clock I/O
20
PC31T1/
INT2
Port C I/O line 3/Timer input/Interrupt
request 2 input
Port C is an 8-bit three-state port. Each bit is independently programmable as either input or output.
Alternatively, the lines of port C can be used as control
lines for the USART and timer. Reset puts all lines of
port C in port mode, input.
TxD [Transmit Data]. Serial data output terminal.
RxD [Receive Data]. Serial data input terminal.
21
PC4/TO
Port C I/O line 4/Timer output
22
PCs/CI
Port C I/O line 5/Counter input
SCK [Serial Clock]. Output for the serial clock when
internal clock is used. Input for serial clock when
external clock is used.
23,24
PC6, PC7/
COo' C01
Port ClIO lines 6, 7/Counter outputs 0,1
TI [Timer Input]. Timer input terminal.
25
NMI
Nonmaskable interrupt input
26
INT1
Interrupt request 1 input
INT2 [Interrupt Request 2]. Falling-edge-triggered,
maskable interrupt input terminal and AC-input, zerocross detection terminal.
27
MOOE1/M1
Mode 1 input/Memory cycle 1 output
28
RESET
Reset input
29
MOOEO/
IO/M
Mode 0 inputll/O/Memory output
30, 31
X2, X1
Crystal connections 1,.2
32
VSS
Ground
33
AVss
Port T threshold voltage input
34-41
ANo-AN7
AID converter analog inputs 0-7
42
VAREF
A/D converter reference voltage
PDo-PD7 [Port D]
43
AVee
AID converter power supply
44
RO
Read strobe output
45
WR
Write strobe output
Port D is an 8-bit three-state port. It can be programmed
as either 8 bits of input or 8 bits of output. When
external expansion memory is used, port D acts as the
multiplexed address/data bus.
46
ALE
Address latch enable output
47-54
PFo-PF7
Port F I/O/Expansion memory address bus
bits 8-15
55-62
POO-P07
Port 0 I/O/Expansion memory address/
data bus
63
Voo
RAM backup power supply
Vee
5 V power supply
64
TO [Timer Output]. The output of TO is a square wave
with a frequency determined by the timer/counter.
CI [Counter Input]. External pulse input to timer/event
counter.
COo, C01 [Counter Outputs 0, 1]. Programmable
rectangular wave outputs based on timer/event
counter.
PFo-PF7 [Port F]
Port F is an 8-bit three-state port. Each bit is
independently programmable as an input or output.
When external expansion memory is used, port F
outputs the high-order address bits.
ANo-AN7
Pin Functions
PAo-PA7 [Port A]
These are the eight analog inputs to the A/D converter.
AN 4 -AN 7 can alsobe used as a digital input for falling
edge detection.
Port A is an 8-bit three-state port. Each bit is independently programmable as either input or output.
Reset makes all lines of port A inputs.
AVss [AID Converter Power Ground]
PBo-PBj7 [Port B]
Port B is an 8-bit three-state port. Each bit is independently programmable as either input or output.
Reset makes all lines of port B inputs.
4-130
AVss is the ground potential for the A/D converter
power supply.
NMI [Nonmaskable Interrupt]
Falling-edge-triggered nonmaskable interrupt input.
NEe
JlPD781 OHI11 H
INT1 [Interrupt Request 1]
WR [Write Strobe]
INT1 is a rising-edge-triggered, maskable interrupt
input. It is also an AC-:-input, zero-cross detection
terminal.
The WR output goes low to indicate that the data bus
holds valid data. It is a strobe signal for external
memory or I/O write operations. WR goes high during
reset.
RESET [Reset]
When the RESET input is brought low, it initializes the
pPD781 DH/11 H.
ALE [Address Latch Enable]
The ALE output latches the address signal to the
output of PDo-PD7.
MODE1, MODEO [Mode 1,0]
The MODE1 and MODED inputs select the memory
expansion mode. MODE1 also outputs the M1 signal
during each opcode fetch. MODED outputs the 101M
signal.
X1, X2 [Crystal Connections 1, 2]
X1 and X2are the system clock crystal oscillator
terminals. X1 is the input for an external clock.
Vss [Ground]
VAREF [AID Converter Reference]
VAREF set the upper limit for the AID converter's
conversion range.
AVee [AID Converter Power]
Ground potential.
Voo [Backup Power]
Backup power for on-chip RAM.
This is the power supply voltage for the AID converter.
Vee [Power Supply]
RD [Read Strobe]
+5 V power supply.
The RD output goes low to gate data from external
devices onto the data bus. RD goes high during reset.
4-131
NEe
J.lPD781 OHI11 H
Block Diagram
x'o--:=EJ·
Osc.
X.
PF7 -PF.
(AB'5- AB.1
PC,lTxD
IncJDec.
PC
SP
EA
PC,/RxD
PC",SCK
V
B
NMI
12
A
C
E
0
H
Main
G.R.
EA'
INTl
V'
B'
A'
C'
E'
0'
Alt.
G.R.
PD7 -PD.
(ADrAD.1
Program
Memory
4K-bytes
ROM
Data
Memory
(256-bytel
PC 7 -PC.
PC"ITIIINT2
PCJTO
PCs/CI
PC",CO.
PC.,ICO,
PB 7 -PB.
AN 7 -AN.
V AREF
AVcc
AVss
PA7 -PA.
AD
WR
ALE MODEl MOOED RESET
Voo
11
Vee
Vss
49·001330C
::::
4-132
NEe
Functional Description
Memory Map
The pPD7811 H can directly address up to 64K bytes of
memory. Except for the on-chip ROM {O-4095} and
RAM {65280-65535}, any memory location can be used
as ROM or RAM. The memory map, figure 1, defines
the O-to 64K-byte memory space for the pPD7811 H.
J..lPD7810H/11H
Table 1.
Memory
Expansion
Port 0
Port F
I/O port
I/O port
256 Bytes
Port 0
Port F
Multiplexed address/data bus
I/O port
4K Bytes
Port 0
Port Fo-F3
Port F4-F7
Multiplexed address/data bus
Address bus
I/O port
16K Bytes
Port 0
Port Fo-Fs
Port F6-F7
Multiplexed address/data bus
Address bus
I/O port
60K Bytes
Port D
Port F
Multiplexed address/data bus
Address bus
Analog Input Lines. ANa-AN7 are configured as
analog input lines for on-chip A/D converter.
Port A, Port e, Port C, Port F. Each line of these ports
can be individually programmed as an input or output.
When used as I/O ports, all have latched outputs and
high-impedance inputs.
Port D. Port 0 can be programmed as a byte input or a
byte output.
AN4-AN7' The high order analog input lines, AN4-AN7,
can be used as digital input lines for falling edge
detection.
Control Lines. Under software control, each line of port
C can be configured individually to provide control
lines for the serial interface, timer, and timer/counter.
Memory Expansion. In addition to the single-chip
operation mode, thejlPD7811H hasfourmemoryexpansion modes. Under software control, port 0 can provide
a multiplexed low-order address and data bus; port F
can provide a high-order address bus. Table 1 shows
the relation between memory expansion modes and
the pin configurations of port 0 and port F.
Port Configuration
None
Input/Output
The pPD7810H/11 H has 8 analog input lines
{ANa-AN7}, 44 digital I/O lines, five 8-bit ports {port A,
port S, port C, port 0, port F}, and 4 input lines
{AN 4-AN 7}·
Memory Expansion Modes and Port
Configurations
Timers
There are two 8-bit timers. The timers may be programmed independently or may be cascaded and used as an
8-bit timer with 8-bit prescaler. The timer can be
software set to increment at intervals of four machine
cycles {1 ps at 12 MHz operation} or 128 machine
cycles {32ps at 12 MHz}, orto increment on receipt of a
pulse at TI. Figure 2 shows the block diagram for the
timer.
Timer/Event Counter
The 16-bit multifunctional timer/event counter {figure
3} can be used for the following operations:
• Interval timer
• External event counter
• Frequency measurement
• Pulse width measurement
• Programmable square-wave output
4-133
I:
~
NEe
JJPD781 OH/11 H
Figure 1.
Memory Map
Reset/Standby Release
IRQO
Internal ROM
4,096 Bytes x 8
IRQ1
~~~~~ ...--------------1
10H
External
Memory
61,184 Bytes x 8
IRQ2
~--------------------~
18H
20H
IRQ3
IRQ4
r---------------------~
~~~~~----------~
Internal RAM
256 Bytesx8
28H
IRQ5
FFFFH " -_ _ _ _ _ _ _ _ _ _- - '
~I
SoftlNT
I
LowADDR
HighADDR
}t=o
LowADDR
HighADDR
}t=l
LowADDR
HighADDR
}t=31
User's Area
49-001326C
4-134
NEe
Figure 2.
fJPD781 OH/11 H
Timer Block Diagram
,--------...,
Timer 0
PC,/TI
Timer 1
,------
I
I
I
I
Timer/Event
Counter
--I
Seriallntertace
Clear
I
4 CL----Ih--l
128CL
I
I
I
I
I
I
I
I
INTTo
INTT,
I
I
_ _ _ oJ
IntemalBus
Notes: 1 CL = 311 (250 ns: 12 MHz operation).
f: System clock frequency (MHz).
49-00'331B
4-135
NEe
IlPD781 OH/11 H
Figure 3.
Block Diagram for Timer/Event Counter
4CL------,
PCslClo---,-------t---i
TO---+--,
PC,ICO,
INTEO
INTEl
INTEIN
Not••: 1 CL = 31f(25O.ns: 12 MHzoperatlon~
f: System clock frequency (MHz~
49·0013326
8-Bit AID Converter
Analog/Digital Converter
• 8 input channels
• 4 conversion result registers
• 2 powerful operation modes
-Autoscan mode
-Channel select mode
• Successive approximation technique
• Absolute accuracy: ±1.5 LSB (±O.6%)
• Conversion range: 0 to 5 V
• Conversion time: 40 ps
• Interrupt generation
ThepPD7810H/11 H features an 8-bit, high speed, high
accuracy AID converter. The AID converter is made up
of a 256-resistor ladder and a successive approximation
register (SAR). There are four conversion result
registers (CRo-CR3)' The 8-channel analog input may
be operated in either of two modes. In the select mode,
the conversion value of one analog input is sequentially
stored in CRo-CR3' In the scan mode, the upper four
channels or the lower four channels may be specified.
Then those four channels will be consecutively selected
and the conversion results stored sequentially in the
four conversion result registers. Figure 4 shows the
block diagram for the AID converter
4-136
NEe
JAPD781 OH/11 H
Interrupt Structure
Universal Serial Interface
There are 11 interrupt sources. Three are external
interrupts and eight are internal. The following, table 2,
shows 11 interrupt sources divided into six priority
levels. See figure 5.
The serial interface can operate in one of three modes:
synchronous, asynchronous, and I/O interface. The
I/O interface mode transfers data MSB first, for easy
interfacing to certain NEG peripheral devices. Synchronous and asynchronous modes transfer data LSB
first. Synchronous operation offers two modes of data
reception: search and nonsearch. In the search mode,
data is transferred one bit at a time from the serial
register to the receive buffer. This allows a software
search for a sync character. In the nonsearch mode,
data transfer from the serial register to the transmit
buffer occurs eight bits at a time. Figure 6 shows the
universal serial interface block diagram.
Standby Function
The standby function saves the top 32 bytes of RAM
with backup power (Voo) if the main power (Vee) fails.
On power up you can check the standby flag (S8) to
determine whether recovery was made from standby
mode or from a cold start.
Table 2.
Interrupt
Request
Interrupt Sources
Interrupt
Address
Type of Interrupt
Internall
External
IRQO
4
NMI (Nonmaskable interrupt)
Ext
IRQ1
8
INTTO (Coincidence signal from
timer 0)
Int
INTT1 (Coincidence signal from
timer 1)
IRQ2
16
IRQ3
24
INn (Maskable interrupt)
Ext
INT2 (Maskable interrupt)
INTEO (Coincidence signal from
timer / event counter)
Figure 5.
NMI
INTTO
INTTl
INn
INT2
INTEO
INTEl
INTEIN
INTAO
INTSR
INTST
Interrupt Structure Block Diagram
:J:I
.z
~
I
Int
INTE1 (Coincidence signal from
timer/event counter)
IRQ4
32
IRQ5
40
EI
INTEIN (Falling signal of CI and
TO counter)
INTAD (A/D converter interrupt)
Int/Ext
INTSR (Serial receive interrupt)
Int
01
INST (Serial send interrupt)
49-OO1333A
Figure 4.
AID Converter Block Diagram
Figure 6.
Universal Signal Interface Block Diagram
AVcco-------------------~
AVsso-----------------~
VAREF o---------~
ANo 0--------1
AN, 0--------1
AN. 0 - - - - - - - 1
AN3 0-------1
AN4 0-------....-1
AN. 0------1P"-+-I
ANa 0---.....-11-+-1
AN, 0--...+-11-+-1
PC,fRxD
Internal Bus
SK •• SK,
PC.fTxO
49-00'327A
49-001329A
4-137
NEe
/JPD7810H/11H
Zero-Crossing Detector
Absolute Maximum Ratings
The INT1 and INT2 terminals (used common to TI and
PC3) can detect the zero-crossing point of lowfrequency AC signals. When driven directly, these pins
respond as a normal digital input. Figure 7 shows the
zero-crossing detection circuitry.
Power supply voltages, _V-"-cc"--_ _ _ _ _ _ _ _-_0_.5_V_to_+_7_.0_V
The zero-crossing detection capability allows you to
make the 50-60 Hz power signal the basis for system
timing and to control voltage phase sensitive devices.
To use the zero-cross detection mode, an AC signal of
approximately 1-3 V AC (peak-to-peak) and a maximum
frequency of 1 kHz is coupled through an external
capacitor to the I NT1 and I NT2 pins.
For the INT1 pin, the internal digital state is sensed as a
o until the rising edge crosses the average DC level,
when it becomes a 1 and INT1 interrupt is generated.
For the I NT2 pi n, the state is sensed as a 1 u nti I the
falling edge crosses the average DC level, when it
becomes a 0 and INT2 interrupt is generated.
Figure 7.
Zero-Crossing Detection Circuit
VDD
-0.5 V to +7.0 V
AVcc
-0.5 V to +7.0 V
AVss
-0.5 V to +0.5 V
Input voltage, VI
-0.5 V to +7,0 V
Output voltage, Vo
-0.5 V to +7.0 V
Reference input voltage, VAREF
-0.5 V to Vcc V
Output current low, 10L
All outputs
Total, all outputs
4.0 rnA
100 rnA
Output current high, 10H
All outputs
Total, all outputs
-0.5 rnA
-20 rnA
Operating temperature, TOPR
fXTAL :s. 15 MHz
Storage temperature, TSTG
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Operating Conditions
Oscillating Frequency
Vee. AVec
+5.0 V ± 10%
fXTAL:S 15 MHz
Capacitance
TA =25°C; Vcc = Voo = Vss =0 V
Limits
Parameter
Symbol
Min
Typ
Max
Capacitance
CI
10
Output
capacitance
Co
20
1/0 capacitance
CIO
20
Unit
Test'
Conditions
pF fc = 1 MHz.
Unmeasured
pF pins returned
to 0 V.
pF
49·001328A
Recommended XTAL Oscillation Circuit
c=
10 pF
83·003282A
4-138
NEe
JAPD781 OH/11 H
DC Characteristics
= +5.0 V ±10%; Vss = 0 V; Vee -0.8 V:S
AC Characteristics
TA = -10°C to +70°C; Vee
Voo:S Vee
Read/Write Operation
Limits
Parameter
Symbol
Input low
voltage
VIL
Input high
voltage
Typ
Min
Max Unit
0.8
Test
Conditions
Vee - 0.8 V ~ Voo ~ Vee
Limits
V
Parameter
X1 input cycle time
Symbol
Min
Max
Unit
teye
66
250
ns
Conditions
20
ns Load capacitance:
CL = 150 pF
VIH1
2.0
Vee
V All except SCK,
RESET, and X1
VIH2
0.8 Vee
Vee
V SCK, X1(1)
VIH3
0.8 Voo
Vee
V RESET
Data hold after RD t
0.45
V 10L = 2.0 mA
WR to data output
two
Address setup to
ALE!
tAL
30
ns fXTAL = 15 MHz
Address hold after
ALE!
tLA
35
ns
Address to RD delay
time
tAR
100
ns
±200 fJA INT1, TI(PC3); +
0.45 V:S VI <
Vee
Address to data input
tAD
250
ns
tLOR
135
ns
±10 fJA All except
INT1, TI(PC3)
oV:S VI:S Vee
RDl to data input
tRO
120
ns
ALE to RD delay
time
±10 fJA +0.45 V:S Vo
:S Vee
Output low
voltage
VOL
Output high
voltage
VOH
2.4
V IOH
Data
retention
voltage
Vooo
3.2
V Vec=OV;
RESET = VIL
Input current
Input leakage
current
TA = -1Q°C to +70°C, Vee = +5.0 V ±10%, Vss = -0 V,
III
Output leakage ILO
current
= -200 fJA
1
RD to address
floating
1
1
ALEl to data input
I
I
tAFR
tROH
ns
0
100
ns
tLR
15
ns
ALE to WR delay
time
tLW
15
ns
IJ
AVee supply
current
Alee
6
12
mA
Data setup time to
WRt
tow
165
ns
VOO supply
current
100
1.5
3.2
mA TA = +25°C;
Vee = Voo =
5V
Data hold time after
WRt
tWOH
60
ns
Vee supply
current
lee
150
200
mA TA = +25°C;
Vee = VOO =
5V
WR t to ALEt delay
time
tWL
80
ns
WR width low
tww
215
ns
RD t to ALE t delay
time
tRL
80
ns
RD width low
tRR
215
ns
415
ns OP code fetch,
fXTAL = 15 MHz;
CL = 150 pF
ns fXTAL = 15 MHz
Load capacitance
ns
= 150 pF
Note:
(1) For XTAL oscillation, see the recommended circuit.
External Clock Timing
TA = -10°C to +70°C; Vee = +5.0 V ±10%; vss = 0 V;
Vee --0.8 V :S Voo:S Vee
Limits
Typ
Test
Max Unit Conditions
Parameter
Symbol
Min
X1 input width high
t4>H
20
250
ns
X1 input width low
t4>L
20
250
X1 input rise time
tr
0
20
X1 input fall time
tf
0
20
ALE width high
tLL
90
tAW
100
ns
Address to WRl
delay
ns
ALE! to data output
tLOW
ns
M1 setup time to
ALE!
tML
30
ns
M110ld time after
ALE
tLM
35
ns
10/~ setup
time to
tiL
30
ns
time after
tLi
35
ns
180
Data read,
fXTAL = 15 MHz;
CL = 150 pF
ns
ALE
10/~ hold
ALE
4-139
NEe
I-tPD781 OH/11 H
Serial Operation
Zero-Cross Characteristics
Limits
Parameter
SCK cycle time
Symbol
Min
tCYK
800
Max
Unit
tKKL
SCK width high
tKKH
RxD set-up time to
SCi( t
RxD hold time after
SCK t
SCK
l TxD delay time
tRXK
tKRX
ns SCK input (2)
1.6
ps SCi( output
335
ns SCK input (1)
200
ns SCK input (2)
700
ns SCK output
335
ns SCK input (1)
200
ns SCK input (2)
700
ns SCK output
80
ns (1)
ns (1)
210
Parameter
Max
Unit
Test Conditions
Zero-cross detection
input
VZX
1.8
VACp_p
AC coupled
Zero~cross accuracy
Azx
±135
mV
60 Hz
sine wave
Zero-cross detection
input frequency
fzx
Symbol
Min
0.05
kHz
Bus Timing Depending on tCYC
Symbol
ns (1)
80
tKTX
Limits
ns SCK input (1)
500
SCK width low
Conditions
TA =-10to+70°C, Vee=+5.0V± 10%, VSS=OV, Vee-8V::;Voo
<:5:V ee
Calculating Expression
MinIMax
tAL
2T -100
Min
tLA
T -30
Min
Min
tAR
3T -:-100
Note:
tAD
7T - 220
Max
(1) 1x clock rate in asynchronous, synchronous, or I/O interface
mode.
tLDR
5T - 200
Max
tRD
4T -150
Max
tLR
T -50
Min
tRL
2T - 50
Min
(2) 16x, 64x clock rate in asynchronous mode.
AID Converter Characteristics
TA = 0 to +70°C; Vee = AVec = +5.0 V ± 10%; Vss = AVss = 0 V;
AVec - 0.5 V::; VAREF::; AVec
tRR
Symbol
tLL
2T -40
Min
tML
2T -100
Min
tLM
T -30
Min
tiL
2T -100
Min
tCYC 66 ns::; tCYc::;
110 ns
tLi
T -30
Min
tAW
3T -100
Min
432
tCYC 110 ns::; tCYc::;
170 ns
tLDW
T + 110
Max
96
tCYC 66 ns::; tCYc::;
110 ns
tLW
T -50
Min
tDW
4T -100
Min
tWDH
2T -70
Min
tWL
2T -50
Min
tww
4T -50
Min
tCYK
12T (SCK input)(1)
-------_. __ .----------------_ ... ----------._.-.-.------24T (SCK output)
Min
tKKL
5T + 5 (SCK input)(1)
.--------------_.---.------------------ .. --------------12T - 100 (SCK output)
Min
tKKH
5T + 5 (SCK input)(1)
------------" .. ------------------_.--------------_.---12T - 100 (SCK output)
Min
Min
Typ
Sampling time
Unit
Conditions
bits
0.8% LSB TA=-10to
± 1/2
+150°C, 66 ns
::; tCYC::; 170 ns
Absolute
accuracy
Conversion
time
Max
8
Resolution
tCONV
tSAMP
576
72
Analog .input
voltage
VIA
Analog
resistance
RAN
Analog
reference
current
IAREF
Min
~-.------------
Limits
Parameter
4T - 50 (Data Read)
..
... -.---------------- .. -------------------7T - 50 (Opcode Fetch)
tCYC 110 ns::; tCYc::;
170 ns
0
VAREF
1000
0.2
0.5
V
Mel
1.5
rnA
Note:
(1) 1x clock rate in asynchronous, synchronous, or I/O interface
mode.
(2) T = teye = 1/fxTAL.
4-140
(3) The items not included in this list are independent of oscillator
frequency (fXTALl.
NEe
J.lPD7810H/11 H,
Other Operations
T A = -10 to +70°C, Vee = +5.0 V ± 10%, Vss = 0 V, Vee - 0.8 V::§;;
VOD::§;; Vee
Limits
Parameter
Symbol
TI width high, low
CI width high, low
Max
Test
Conditions
Unit
tCI1H, tCl1L
6
6
tCYC
Event count
mode
tCI2H, tCI2L
48
tCYC
Pulse width
measurement
mode
36
36
36
60
tCYC
tTlH, tTIL
NMI width high, low tNIH, tNIL
INT1 width high, low t11H, tl1L
INT2 width high, low t12H, tl2L
RESET width high,
low
Min
tRSH, tRSL
tCYC
tCYC
tCYC
tCYC
Timing Waveforms
Read Operation
X1
High Address
PDa-P D7
Low Address
ALE
RD
----+-----+If---t
1+-----tRD-----~
1+-------tRR----.:.----Ir--------------
,,,~.I .,
"f~:~lf~dL,.L~,
MODEO(IO/M)
[Note 2)
-------------------------
Note:
(1) M1 is output to the MODE1 pin at the first opcode fetch cycle if the MODE 1 pin is pulled up.
(2) 101M is output to the MODEO pin at the sr to sr2 register read cycle If the MODEO pin Is pulled up.
83·003;2848
4-141
NEe
IAPD781 OH/11 H
Timing Waveforms (cont)
Write Operation
Xl
High Address
PFo-PF7
Write Data
POO-P07
1+------tDw-----~
ALE
I+------------tww--------~
WR
tAw-------+I
.OOEO~" --C,,,-J L,,~
,...-----------------------------J
[Note 1)
\_
Note:
(1) 101M Is output to the MOOED pin at the srto sr2 register write cycle if the MOOED pin is pulled up.
83·0032858
Serial Operation
!-------tCYK-------------.j
SCK
TxO
RxO
tRXK
j4-----tKRX------~
83·0032868
4-142
NEe
J,tPD781 OH/11 H
Timing Waveforms (cont)
RESET Input Timing
Timer Input Timing
_ YO.8V tRSHI.tRSlJ...---
RESET
DO
_
0.8 V
83-003287A
83·003291A
External Clock Timing
Timer/Event Counter Input Timing:
Event Counter Mode
83-003288A
83·003292A
Timer/Event Counter Input Timing:
Pulse Width Measurement Mode
AC Timing Test Points
2.4
V~
0.45 V
2.0 V ;: Test pOints:::' 2.0 V
0.8 V
0.8 V
x:=
83-003283A
83-003289A
Interrupt Input Timing
'M'
J"'"=(~"}.---
~fi ----L''''J=''"~'--
"u
J~"=("aJ...--83-003290A
4-143
t-IEC
pPD7810H/11 H
Instruction Set
Operand Format/Description
Remarks
Description
Format
V,A, B,C,D,E,H,L
EAH,EAL,B,C, D,E,H, L
A, B,C
sr2
sr3
sr4
PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH,SML, EOM,
ETMM, TMM, MM, MCC, MA, MB, MC,
MF, TxB, TMo, TM1
PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB,
CRO, CR1, CR2, CR3
PA, PB, PC, PD, PF, MKH, ANM, MKL, SMH, EOM, TMM
HMo, ETM1
ECNT, ECPT
rp
rp1
rp2
rp3
SP,B,D,H
V, B, D, H, EA
SP,B,D,H,EA
B, D,H
rpa
rpa1
rpa2
B, D, H, D+ , H + , D-, H B,D,H
B, D, H, D+, H + , D-, H -, D + byte, H + A, H + B,
H + EA, H + byte
D, H, D+ +, H + +, D+ byte, H + A, H + B, H + EA,
H + byte
sr
sr1
rpa3
wa
a-Bit immediate data
word
byte
bit
16-Bit immediate data
a-Bit immediate data
3-Bit immediate data
FNMI, flO, Fl1, F1, F2, FEO, FE1, FEIN, FAD, FSR, FST, ER,
OV, AN4, ANs, AN6, AN?, SB
Instruction Set Symbol Definitions
Symbol
Description
Transfer direction, result
A
Logical product (logical AND)
V
Logical sum (logical OR)
.Jf
Exclusive OR
Complement
Concatenation
4-144
ECNT = Timer/Event
Counter Upcounter
ECPT = Timer/Event
Counter Capture
PA = Port A
PB = Port B
PC = Port C
PD = Port D
PF = Port F
MA = Mode A
MB = Mode B
MC = Mode C
MCC = Mode Control C
MF= Mode F
ETMM = Timer/Event
Counter Mode
EOM'= Timer/Event
Counter Output Mode
MM = Memory Mapping
TMo = Timer Register 0
TM1 = Timer Register 1
TMM = Timer Mode
ETMo = Timer/Event
Counter Register 0
ETM1 = Timer/Event Counter
Register 1
TxB = TX Buffer
RxB = RX Buffer
SMH = Serial Mode High
SML = Serial Mode Low
MKH = Mask High
MKL = Mask Low
ANM = A/D Channel Mode
CRo = AID Conversion Result 0-3
to CR3
2. rp-rp3 (register pair)
SP = Stack Pointer
B = BC
D= DE
H= HL
V=VA
EA = Extended Accumulator
3. rpa-rpa3 (rp addressing)
CY, HC, Z
irf
1. sr-sr4 (special register)
B= (BC)
D= (DE)
H = (HL)
D+= (DE) +
H -=(HL) +
D-=(DE) H-=(HL) -
D+ += (DE) ++
H + += (HL) ++
D+ byte = (DE) + byte
H + A = (HL) + (A)
H + B = (HL) + (B)
H + EA = (HL) + (EA)
H + byte = (HL) + byte
4. f (flag)
CY = Carry
HC = Half Carry
Z = Zero
5. irf (interrupt flag)
NMI = NMI* Input
FTO = INTFTO
FT1 = INTFT1
F1 = INTF1
F2 = INTF2
FEO = INTFEO
FE1 = INTFE1
FEIN = INTFEIN
FAD = INTFAD
FSR = INTFSR
FST = INTFST
ER = Error
OV= Overflow
AN4 to AN? = Analog Input 4-7
SB = Standby
Instruction Set
Operation Code
B1
Mnemonic
7
6
5
(r1)-(A)
(A)-(r1)
0
0
0
0
0
0
1
0
T2 T1 To
T2 T1 To
*sr,A
*A,sr1
r,word
(sr)-(A)
0
0
0
0
0
0
(A) -(sr1)
(r)-(word)
0
0
0
0
word,r
(word)-(r)
0
Operand
a-Bit Data Transfer
MOV
r1,A
A, r1
MVI
Operation
*r,byte
0
1
0
0
0
MVIW
*wa, byte ((V)e(wa)) -
0
MVIX
STAW
LDAW
STAX
lDAX
EXX
*rpa1,byte
*wa
*wa
*rpa2
*rpa2
1 0
Data
0 1
EXA
EXH
16-Bit Data Transfer
DMOV
byte
(rpa1) - byte
((V)e(wa)) - A
(A) - ((V)e(wa))
(rpa2) - (A)
(A) - ((rpa2))
(B) ++ (B'),(C) ++ (C'),(D) ++ (D')
(E) ++ (F),(H) ++ (H'),(l) ++ (l')
(V) ++ (V'),(A) ++ (A'),(EA) ++ (EA')
(H) ++ (H'),(l) ++ (l')
D
((DE)) - ((Hl)),(DE) - (DE + 1),
(Hl) - (Hl) + 1, (C) - (C) -1
End if borrow
rp3, EA (rp3d- (EAl),(rp3H) - (EAH)
EA,rp3 .(EAl) -
(rp3Ll,(EAH) -
(rp3H)
0
0
0
1
1
0
0
0
A3
A3
0
0
0
0
0
0
0
0
2
0
1
0
0
Data
0
0
1
0
0
0
0
0
o
A1 Ao
1 1
0 1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
5
B4
4 3
2
1
0
State(l)
Bytes
0
0
S5 S4 S3
S5 S4 S3
1 1 0 1
High addr
1 1 1
High addr
Data
S2 S1 So
S2 S1 So
R2 R1 Ro
10
10
17
2
R2 R1 Ro
17
4
7
2
o
S2 S1 So
14
3
13
3
0
0
0
Offset
A2 A1 Ao
1 A2 A1 Ao
0 0 0 1
0
6
Skip
Condition
4
4
S3
0
0
0
7
1
0
0
lowaddr
1 0 0 0 0
lowaddr
0 1 R2 R1 Ro
(r)-byte
set l1 if r = A
setLO if r = l
sr2,byte (sr2) - byte
BLOCK
B2
B3
4 3
Data
Offset
Offset
Data (2)
Data (2)
~
~
2
4
10
2
10
10
7/13(3)
7/13(3)
4
2
2
2
2
l1 = 1 and r = A
lO = 1 and r = l
4
0
4
13 x
(C+1)
P1 Po
P1 Po
4
4
'l:::
"......a
CD
...
0
::z:
...::z:~
t'
~
01
~
~
.!..
,.a
1:::
Instruction Set (cont)
.j::>.
Operation Code
0)
Mnemonic
Operand
7
Operation
16-Bit Data Transfer Icont)
OMOV
sr3, EA (sr3) - (EA)
EA,sr4 (EA) - (sr4)
SBCD
word (word) - (C), (word + 1) -
(B)
o
o
o
SDEO
(0)
o
word
(word) -
(E), (word + 1) -
SHLD
word
(word) -
(L), (word + 1) -
SSPD
word
(word) -
(SPLl,(word + 1) -
STEAX
rpa3
((rpa3)) -
LBCD
word
(C) -
(word),(B) -
o
o
(SPH)
(EAH)
(word + 1)
B4
2
1
0
000
0 0
000
Lowaddr
1 0 0 0 0
Lowaddr
1 1 0 0 0
Lowaddr
1 0 0 0 0
Lowaddr
00100
Data(4)
o
(H)
(EAL),((rpa3) + 1 -
6
o
o
o
0
0
1
0
0
0
word
(E) -
(word),(O) -
(word + 1)
LHLD
word
(L) -
LSPD
word
(SPLl -
(word),(SPH) -
LDEAX
rpa3
(EAL) -
((rpa3)),(EAH) -
PUSH
rp1
POP
LXI
(word),(H) -
(word + 1)
((word) + 1)
((rpa3) + 1)
((SP) - 1) - (rp1H) ((SP) - 2) - (rp1Ll
(SP) - (SP) - 2
rp1
(rp1Ll - ((SP)),(rp1H) - ((SP) + 1)
(SP) - (SP) + 2
*rp2,word (rp2) - (word)
set LO if rp2 == H
TABLE
(C) - ((PC)+3+(A)),B 8-Bit Arithmetic [Register)
ADO
A,r
(A) - (A) + (r)
r,A
(r)-(r) + (A)
ADC
A,r
(A) .- (A) + (r) + (CY)
r,A
(r) - (r) + (A) + (CY)
((PC)+3+(A)+ 1)
o
1
0
0
o
o
o
0
o
o
2
0
Bytes
01001UO
1 0 0 0 0 V1 Vo
000 1
1 0
High addr
14
14
20
2
2
4
o
o
20
4
1
0
20
4
1
0
20
4
14/20(3)
3
20
4
20
4
20
4
20
4
14/20(3)
3
0
o
0
o
0
o
1
0
1
High addr
1 1 1
High addr
001
High addr
0
1 C3 C2 C1 Co
0
o
0
0 C3 C2 C1 Co
0 02 01 00
10
0
0
o
o
o
o
3
13
0
0
4
02 01 00
0 P2 P1 Po 0 1
High byte
1
5
0 1 1 1 1
High addr
0010111
High addr
o 0 1 1 1
High addr
o 0 0 0
High addr
Lowaddr
1 000
Lowaddr
1 000
Lowaddr
00100
Oata(4)
o
1
0
6
State(1)
o
Lowaddr
LDED
7
0
Low byte
o
0
1
0
o
o
o
o
0
0
0
0
0
0
0
0
o
0
0
0
0
0
0
0
0
o
1
..
.....
B2
B1
B3
543
1
000
10
3
17
2
2
2
2
2
1
0
o
0 0
o
o
o
0
0 ~ ~ ~
8
8
1
1
0 R2 R1 Ro
0 R2 R1 Ro
8
~ ~
~
8
Skip
Condition
CD
o
:z
..
~
:z
LO == 1 and
rp2 == H
~
~
Instruction Set (cont)
Operation Code
BI
B2
B4
U
Mnemonic
.j::o.
I
~
......
Operand
Operation
a-Bit Arithmetic [Registerl(contl
AOONC
A,r
(A) +- (A) + (r)
r,A
(r) +- (r) + (A)
SUB
A,r
(A) +- (A) - (r)
r,A
(r) +- (r) - (A)
SBB
A,r
(A) +- (A) :- (r) - (CY)
r,A
(r) +- (r) - (A) - (CY)
SUBNB
A,r
(A) +- (A) - (r)
r,A
(r) +- (r) - (A)
ANA
A,r
(A) +- (A) A (r)
r,A
(r) +- (r) A (A)
ORA
A,r
(A) +- (A) V (r)
r,A
(r) +- (r) V (A)
XRA
A,r
(A) +- (A) V (r)
r,A
(r) +- (r) V (A)
GTA
A,r
(A) - (r) - 1
r,A
(r) - (A) - 1
LTA
A,r
(A) - (r)
r,A
(r) - (A)
NEA
A,r
(A) - (r)
r,A
(r) - (A)
EQA
A,r
(A) - (r)
r,A
(r) - (A)
ONA
A,r
(A) A (r)
OFFA
A,r
(A) A (r)
8-Bil Arithmetic (Memory)
AOOX
rpa
(A) +- (A) + ((rpa))
AOCX
rpa
(A) +-(A) + ((rpa)) + (CY)
AOONCX
rpa
(A) +- (A) + ((rpa))
SUBX
rpa' (A) +- (A) - ((rpa))
SBBX
rpa
(A) +- (A) - ((rpa)) - (CY)
SUBNBX
rpa
(A) +- (A) - ((rpa))
ANAX
rpa
(A) +- (A) A ((rpa))
ORAX
rpa
(A) +- (A) V ((rpa))
7
6
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
5
1
1
1
4
3
2
0
6
4
3
2
0
Statell)
0
0
0
1
0
0
0
R2 R1 Ro
8
0
0
0
0
o
0
0
0
R2 R1 RO
8
0
0
0
0
1
1
1
0
0
R2 R1 Ro
8
0
0
o
1
1
0
0
R2 R1 Ro
8
1
1
0
R2 R1 RO
8
8
0
0
0
000
0
000
0
o
1
1
1
0
R2 R1 Ro
o
0
0
0
1
0
1
1
0
R2 R1 Ro
8
0
0
0
0
o
0
1
1
0
R2 R1 RO
8
000
0
0
1
0
0
1 R2 R1 Ro
8
0
0
0
0
0
o
0
0
1 R2 R1 Ro
8
0
0
0
0
1
0
0
1
1 R2 R1 RO
8
000
0
0
o
0
0
1
1 R2 R1 Ro
0
0
0
0
0
1
0
0
1
0
R2 R1 RO
8
8
0
0
0
0
R2 R1 Ro
8
0
0
o
0
0
1
0
0
1
0
1
0
1 R2 R1 RO
o
0
1
0
1 R2 R1 RO
8
o
1
1
1 R2 R1 Ro
8
000
0
0
0
0
0
0
000
0
0
o
0
1
1
1 R2 R1 Ro
8
0
0
0
0
1
1
1
0
1 R2 R1 RO
8
000
0
0
o
1
1
0
1 R2 R1 RO
8
000
0
0
1
1
1
1
1 R2 R1 Ro
8
o
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
00
o 0
o
0
0
0
0
1
1
1 R2 R1 Ro
o
o
0
1 R2 R1 Ro
8
8
1
1 R2 R1 Ro
8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
o
0
0 A2 A1 Ao
11
2
0
1
0 A2 A1 AO
11
2
o
1
0
0 A2 A1 Ao
11
2
2
2
2
2
2
01110000
1
0
0 A2 A1 Ao
11
1
1
1
000
0
1
1
1
0 A2 A1 Ao
11
1
1
1
0
0
0
0
1
1
0 A2 A1 Ao
11
1
1
100
0
0
o
o
0
0
1 A2 A1 Ao
11
1
1
1
000
0
0
0
1
1 A2 A1 Ao
11
1
Bytes
1
01110000
o
o
o
o
o
5
0
000
1
7
Skip
Condition
No carry
~
~
No carry
No borrow
No borrow
No borrow
No borrow
Borrow
Borrow
No zero
No zero
Zero
Zero
No zero
Zero
1:::
No carry
"a
--I
...o
:z
"......
co
No borrow
:z
.j::o.
!...
Instruction Set (cont)
l:::
.j::o.
(»
Operation Code
Mnemonic
Operand
Operation
8·Bit Arithmetic (Memory) (cont)
XRAX
rpa
(A) - (A) V ((rpa))
GTAX
rpa
(A) - ((rpa)) - 1
LTAX
rpa
(A) -((rpa))
NEAX
rpa
(A) - ((rpa))
EaAX
rpa
(A) - ((rpa))
ONAX
rpa
(A) A ((rpa))
OFFAX
rpa
(A) A ((rpa))
Immediate Data
ADI
*A,byte (A) - (A)+ byte
r,byte (r) - (r) + byte
7
6
5
4
B1
H
B3
M
3
2
0
o
o
o
000
o 0 0
o 0 0
000
o 0 0
o 0 0
0
0
0
0
0
0
o
o
0
o
o
000
o
00
o
o
Data
010
1 0
Data
o
o
o
o
o
o
0
0
7
6
5
o
0
4
aytes
Skip
Condition
11
2
2
2
2
2
2
2
No borrow
Borrow
No zero
Zero
No zero
Zero
0 R2 R1 Ro
7
11
2
3
o
S2 S1 So
20
3
3
2
1
0
o
A2
A2
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
A1
A1
Ao
Ao
Ao
Ao
Ao
Ao
Ao
010
o
o
o
Data
1
0
o
0
o
o
o
0
S3
o
0
State(1)
11
11
11
11
11
11
"a.....
..
..
CD
o
z
~
Z
Data
sr2, byte (sr2) ACI
(sr2) + byte
*A,byte (A) - (A) + byte + (CY)
r,byte (r) - (r) + byte + (CY)
sr2,byte (sr2) -
(sr2) + byte + (CY)
0
7
2
0
R2 R1
Ro
11
3
o
S2 S1 So
20
3
Data
1
0
o
0
o
o
o
0
S3
o
1
Data
ADINC
*A,byte (A) - (A) + byte
r,byte (r) - (r) + byte
o
o
0
o
0
1
0
1
0
o
0
o
0
o
0 R2 R1 Ro
7
11
2
3
No carry
'No carry
o
0
S3 0
o
0 S2 S1 So
20
3
No carry
Data
Data
sr2,byte (sr2) -
(sr2) + byte
o
o
0
Data
SUI
SBI
*A,byte (A) - (A) - byte
r,byte (r) - (r) :- byte
o
o
1 100
7
2
0
Data
o
0
o
o
0 'R2 R1 Ro
11
3
sr2,byte (sr2) -
o
100
o
0
S3
o
0 S2 S1 So
20
3
*A,byte (A) - (A) - byte - (CY)
r,byte (r) - (r) - byte - (CY)
o
o
Data
1 0
1 0
Data
7
sr2,byte (sr2) -
o
(sr2) - byte
(sr2) - byte - (CY)
1
1
1
1
o
0
Data
o
Data
1
0
o
0
o
1 1 1 0 R2 R1 Ro
11
2
3
o
0
S3
1
20
3
Data
1
1
0 S2 S1 So
~
~
Instruction Set (cont)
Operation Code
BI
Mnemonic
Operand
Operation
Immediate Data (contI
SUINB
'A,byte (A) - (A) - byte
r,byte (r) - (r) - byte
sr2,byte (sr2) ANI
ORI
GTI
NEI
~
0
0
0
sr2,byte (sr2) -
0
(sr2) A byte
'A, byte (A) - (A) V byte
r,byte (r) - (r) V byte
5
0
0
0
Data
0 0
Data
0 0
0
0
0
0
0
0
0
Data
0
0
0
(sr2) V byte
'A,byte (A) - (A) V byte
r,byte (r) - (r) V byte
0
0
sr2,byte (sr2) -
0
(sr2) V byte
*A,byte (A) - byte - 1
r,byte
LTI
6
'A,byte (A) - (A) A byte
r,byte (r) - (r) A byte
sr2,byte (sr2) XRI
(sr2) - byte
7
B3
4 3
(r) - byte-1
0
0
sr2,byte (sr2) - byte - 1 ~
0
'A,byte (A) - byte
r,byte (r) - byte
0
0
sr2,byte (sr2) - byte
0
'A,byte (A) - byte
r,byte (r) - byte
0
0
0
0
0
0
Data
1 0
0
Data
0 0
Data
0
0
Data
0 0
Data
2
I
0
7
6
0
0
0
0
0
0
0
0
0
Data
0
0
Data
S3
1
0
0
Data
0
0
Data
2
I
0
State(l)
Bytes
Skip
Condition
Data
1 0 R2 R1 Ro
7
2
11
3
No borrow
No borrow
0 S2 S1 So
20
3
No borrow
2
0
0
Data
0 1 R2 R1 Ro
7
0
11
3
0
0
S3
0
0
S2 S1 So
20
3
2
0
0
Data
1 1 R2 R1 Ro
7
0
11
3
3
0
0
S3
0
0
S2 S1 So
20
0
0
2
0
0
0
Data
1 0 R2 R1 Ro
7
0
11
3
0
0
S3
0 S2 S1 So
20
3
1
1
0
0
0
0
Data
0 1 R2 R1 Ro
11
3
No borrow
No borrow
0
0
S3
0
S2 S1 So
14
3
No borrow
0
0
0
Data
1 1 R2 R1 Ro
7
0
11
2
3
Borrow
Borrow
0
0
S3
0
S2 S1 So
14
3
Borrow
1
0
B4
4 3
0
1
0
0
0
1
1
Data
0 1 R2 R1 Ro
2
7
2
11
3
No zero
No zero
~
~
1:::
"a
--.I
CD
0
....
:z:
....~
I
~
co
5
0
1
0 0
Data
0
B2
m
:z:
f."
~
l:::
Instruction Set (cont)
C1I
Operation Code
0
B2
B1
Mnemonic
Operand
Operation
7
6
5
B3
3
4
2
1
0
7
0
S3
6
5
B4
4 3
2
1
0
State(l)
Bytes
Skip
Condition
Immediate Data (cont)
NEI
sr2,byte (sr2) - byte
0
0
0
0
• A,byte (A) - byte
r,byte
(r) - byte
0
0
1
1
0
0
1
0
0
0
~
0
:I:
-
14
3
No zero
::.:
2
Zero
1 R2 R1 Ro
7
11
3
Zero
:I:
S2 S1 So
14
3
Zero
7
11
2
No zero
1 R2 R1 Ro
3
No zero
S2 S1 So
14
3
No zero
7
11
2
Zero
R2 R1 Ro
3
Zero
S2 S1 So
14
3
Zero
0
14
3
Data
1
Q)
S2 S1 So
Data
EQI
".....a
Data
sr2,byte (sr2) - byte
0
0
S3
1
0
0
0
0
S3
0
0
0
~
0
Data
ONI
0
• A,byte (A) A byte
r,byte (r) A byte
0
0
1
0
0
Data
0
Data
sr2,byte (sr2) A byte
0
0
0
Data
OFFI
·A,byte (A) A byte
r,byte
0
0
(r) A byte
0
1
o .1
1
1
0
0
Data
1
1
Data
sr2,byte (sr2) A byte
0
0
0
0
0
Data
Working Register
ADDW
wa
(A) +- (A)
+ ((V)e(wa))
0
1
0
0
0
0
0
0
0
0
0
0
14
3
0
0
0
0
14
3
0
0
14
3
0
0
0
0
14
3
0
0
0
0
14
3
0
0
14
3
Offset
ADCW
wa
(A) +- (A)
+ ((V)e(wa)) + (CY)
0
1
0
Offset
ADDNCW
wa
(A) ..- (A)
+ ((V)e(wa))
0
1
0
0
0
No carry
Offset
SUBW
wa
(A) ..- (A) - ((V)e(wa))
0
1
0
0
Offset
SBBW
wa
(A) ..- (A) - ((V)e(wa)) - (CY)
0
1
0
0
1
Offset
SUBNBW
wa
(A) +-(A) - ((V)e(wa))
0
1
0
0
0
0
0
Offset
ANAW
wa
(A) +- (A) A ((V)e(wa))
0
1
0
Offset
II
0
0
No borrow
~
I:)
Instruction Set (cont)
Operation Code
B1
B2
B3
Mnemonic
Operand
Working Register Icont)
wa
ORAW
XRAW
wa
Operation
(A) (A) -
(A) V ((V).(wa))
7
6
5
4
3
0
0
2
1
0
0
0
6
5
B4
4 3
2
1
0
0
0
0
State(l )
Bytes
Skip
Condition
14
3
14
3
14
3
No borrow
14
3
Borrow
14
3
No zero
14
3
Zero
0
14
3
No zero
0
14
3
Zero
Offset
19
3
0
Offset
19
3
0
Offset
13
3
No borrow
0
Offset
13
3
Borrow
Offset
13
3
No zero
0
Offset
13
3
Zero
0
Offset
13
3
No zero
Offset
1 0
(A) V ((V).(wa))
7
0
0
0
0
~~
Offset
GTAW
LTAW
NEAW
EOAW
ONAW
wa
wa
wa
wa
wa
(A) - ((V).(wa)) - 1
1
0
0
(A) - ((V).(wa))
Offset
1 0
(A) - ((V).(wa))
Offset
1 0
0
(A) - ((V).(wa))
Offset
1 0
(A) 1\ ((V).(wa))
Offset
1 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Offset
OFFAW
wa
(A) 1\ ((V).(wa))
1
0
0
0
Offset
ANIW
'wa,byte ((V).(wa)) -
0
((V).(wa)) 1\ byte
0
Data
ORIW
*wa,byte ((V).(wa)) -
((V).(wa)) V byte
0
0
0
1
Data
GTlW
LTIW
0
*wa,byte ((V).(wa)) - byte - 1
0
0
Data
*wa,byte ((V).(wa)) - byte
0
0
0
1
Data
NEIW
*wa,byte ((V).(wa)) - byte
0
0
0
Data
EOIW
*wa,byte ((V).(wa)),- byte
1
0
Data
ONIW
*wa,byte ((V).(wa)) 1\ byte
0
0
0
Data
OFFIW
*wa,byte ((V).(wa)) 1\ byte
0
1 0
Data
Offset
3
Zero
"a
~
CD
0
....
Z
~
.!....
~
13
"t:::
m
"....Z....
~
~
U'I
Instruction Set (cont)
't:
"a
Operation Code
I\)
Mnemonic
Operand
16-Bit Arithmetic
EADD
EA,r2
DADO
EA,rp3
DADC
EA,rp3
DADDNC
EA,rp3
ESUB
EA,r2
DSUB
EA,rp3
DSBB
EA,rp3
DSUBNB
EA,rp3
DAN
EA,rp3
DOR
EA,rp3
DXR
EA,rp3
DGT
EA,rp3
DLT
EA,rp3
ONE
EA,rp3
DEQ
EA,rp3
DON
EA,rp3
DOFF
EA,rp3
Multiply /Divide
MUL
r2
DIV
r2
Increment/Decrement
INR
r2
INRW
*wa
INX
rp
EA
OCR
r2
DCRW
*wa
DCX
rp
EA
Others
DAA
STC
CLC
7
Operation
(A) x (r2)
(EA) + (r2), (r2) -
4
o
o
o
o
o
o
o
o
o
o
o
o
Remainder
Decimal Adjust Accumulator
(CY)-1
(CY)-O
o
o
B2
U
B4
3
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
(r2) - (r2) + 1
((V)e(wa)) - ((V)e(wa)) + 1
(rp) - (rp) + 1
(EA) - (EA)+ 1
(r2) - (r2) - 1
((V)e(wa)) - ((V)e(wa)) - 1
(rp) - (rp) - 1
(EA) - (EA) - 1
II
5
o
o
(EA) - (EA) + (r2)
(EA) - (EA) + (rp3)
(EA) - (EA) + (rp3) + (CY)
(EA) - (EA) + (rp3)
(EA) - (EA) - (r2)
(EA) - (EA) - (rp3)
(EA) - (EA) - (rp3) - (CY)
(EA) - (EA) - (rp3)
(EA) - (EA) 1\ (rp3)
(EA) - (EA) V (rp3)
(EA) - (EA) V (rp3)
(EA) - (rp3) - 1
(EA) - (rp3)
(EA) - (rp3)
(EA) - (rp3)
(EA) 1\ (rp3)
(EA) 1\ (rp3)
(EA) (EA) -
6
B1
1
1
1
0
7
654
o
o
o
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o
0
1
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
P1 Po
1 0
0 1
1 1
0
1
0
0
R1 Ro
0 0
1 0
0 0
R1 Ro
0 0
o
0
P1 Po
0
0
1
o
o
o
0
0
2
000
1
0
1
0
1
o
1
1
0
0
1
0
0
o
320
0
0
0
0
0
0
o
o
o
000
001
001
0
010
o
1
1
o
o
o
1
1
1
o
o
0
1
1
1
0
0
R1 Ro
~ Po
~ Po
P1 Po
R1 Ro
P1 Po
1 P1 Po
1 P1 Po
P1 Po
P1 Po
P1 Po
P1 Po
1 P1 Po
State(l)
0
11
1
1
1
0
1
11
P1
P1
1 P1
1 P1
1
o
Po
Po
Po
Po
R1 Ro
R1 Ro
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
32
59
16
2
2
2
2
2
2
2
2
2
2
2
~
...
CD
o
:z
~
...
No carry
z
No borrow
No borrow
Borrow
No zero
Zero
No zero
Zero
2
2
2
Carry
Carry
2
Borrow
Borrow
7
7
4
Offset
16
1
7
7
0
2
2
2
2
2
4
Offset
0101001
000
Bytes
Skip
Condition
1
1
1
001
000
1
001
0
1
001
000
001
0
o
o
o
4
8
8
2
2
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operand
Operation
Bl
B2
B3
7
&
5
4
3
2
1
0
1
0
0
1
0
0
1
0
7
&
5
B4
4 3
2
1
0
0
0
1
1
0
1
0
8
2
0
0
0
0
0
2
2
R1 Ro
17
17
8
State(l)
Bytes
Skip
Condition
Others (cont)
+1
NEGA
Rotate and Shift
RLD
(A) -
Rotate left digit
0
0
0
RRD
RLL
Rotate right digit
0
r2
(r2m + 1) - (r2 m), (r2o) (CY) - (r27)
(CY),
0
0
0
0
RLR
r2
(r2m -1) - (r2m),(r27) (CY) - (r2o)
(CY),
0
0
0
0
SLL
SLR
SLLC
SLRC
r2
r2
r2
r2
(r2m + 1) (r2m _ 1) -
0, (CY) 0, (CY) -
(r27)
(r2o)
(r27)
(r2o)
0
0
0
0
0
0
0
0
EA
0
0
0
0
0
0
0
0
0
0
0
DRLL
0
0
DRLR
EA
(r2m + 1) - (r2m),(r20) - 0, (CY) (r2m -1) - (r2m),(r27) - 0, (CY) (EAn + 1) - (EAn),(EAO) - (CY),
(CY) - (EA1S)
(EAn - 1) - (EA n),(EA1S) - (CY),
(CY) - (EAO)
0
0
0
0
0
0
0
0
1
0
0
DSLL
EA
1
0
DSLR
EA
Jump
JMP
*word
JB
JR
JRE
word
*word
JEA
(A)
(r2m),(r20) (r2 m),(r27) -
1
0
((SP) -1) - ((PC) + 2)H,
((SP) - 2) - ((PC) + 2) L
(PCH) - (B), (PCLl- (C),
(SP) - (SP) - 2
0
((SP) -1) - ((PC) + 2)H,
((SP) - 2) - ((PC) + 2)L
(PC1S-11) - 00001,
(PC10-0) - fa, (SP) - (SP) - 2
0
8
2
0
0
0
0
0
0
0
0
0
0
o
R1 Ro
R1 Ro
2
2
2
2
2
0
0
1 0 1
High addr
0
0
0
1
0
0
R1 Ro
0
0
((SP) - 1) - ((PC) + 3)H,
((SP) - 2) - ((PC) + 3)L
(PC) - word, (SP) - (SP) - 2
o
0
(PC) -
1
0
0
0
0
0
0
0
0
0
0
0
0
1
(PC) + 2 + jdisp
(EA)
0
0
0
(PC) (PC) -
0
0
0
0
0
0
0
R1 Ro
R1 Ro
1 0 0
0
0
1
0
0
0
o
1
(PCH) - (B),(PCL) - (C)
(PC) - (PC) + 1 + jdisp 1
0
0
0
0
0
0
0
0
0
0
8
8
8
8
8
(EAn + 1) - (EAnHEAO) - 0,
(CY) - (EA1S)
(EAn - 1) - (EA n),( EA 1S) - 0,
(CY) - (EAo)
word
0
0
1
0 0
jdisp1
0 1 1
0 1 0
0
0
0
0
0
0
1
0
0
0
1
0
2
0
0
8
2
0
0
8
2
0
0
8
2
Lowaddr
10
3
jdisp
10
10
1
0
0
*word
CALB
CALF
.J:o.
I
Ir-;.r-----J1\-~~
_ _ _ _ _ _ _ _ _ _ _ _ _-':':::::::::;.!::-=::.:!:F_ _ _ _ _ _ _ _ _ _ _ _-1"_...A.____
--===t==~~~§~=~---------~-IRR-------Ilr-----------49-000182A
Transmit/Receive Timing
TXD _ _4-__~H+_______J~________________
RXD _ _ _ _ _~~~--------~----------~----49-000179A
4-161
NEe
MPD78PG11
Remarks
1. sr-sr4 (special register)
PA
PB
PC
PO
PF
MA
MB
MC
MCC
MF
MM
TMD
TMI
TMM
HMo
HMI
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
5. irf (interrupt flag)
Port A
Port B
Port C
Port 0
Port F
Mode A
Mode B
Mode C
Mode Control C
Mode F
Memory Mapping
Timer Register 0
Timer Register 1
Timer Mode
Timer Event
Counter Register 0
Timer Event
Counter Register 1
ECNT
ECPT
ETMM
Timer IEvent
Counter Upcounter
Timer IEvent
Counter Capture
TimerIEvent
Counter Mode
Timer IEvent
Counter Output Mode
AID Channel Mode
=
=
=
EOM
=
ANM
=
foRo
CR3
TxB
RxB
SMH
SMl
MKH
MKl
=
AID Conversion
Results 0-3
=
TxBuffer
RxBuffer
Serial Mode High
Serial Mode low
Mask High
Mask low
=
=
=
=
=
FNMI
FTO
FT1
F1
F2
FEO
FE1
FEIN
FAD
=
=
=
=
=
=
=
=
=
INTFNMI
INTFTO
INTH1
INTF1
INTF2
INTFEO
INTFE1
INTFEIN
INTFAD
FSR
FST
ER
OV
AN 4
to
AN4
SB
=
=
=
=
=
=
=
INTFSR
INTFST
Error
Overflow
Analog Input 4-7
= Standby
Instruction Set Symbol Definitions
Symbol
Description
Transfer direction. result
logical product (logical AND)
,\
v
logical sum (logical OR)
2. rp-rp3 (register pair)
SP
B
0
=
Exclusive OR
Stack POinter
BC
DE
H
V
EA
=
0++
H++
D+byte
H+A
H+ B
H+ EA
H+ byte
=
=
=
=
=
'=
Hl
VA
Extended Accumulator
Complement
Concatenation
3. rpa-rpa3 (rp addressing)
B
=
=
=
o
H
0+
H+
DH-
=
=
=
=
(BCj
(DE)
(Hlj
(DEj+
(Hl)+
(DE)(Hl)-
=
=
=
(DE)++
IHl)++
(DE+ byte)
(Hl+A)
(Hl+B)
(Hl+EA)
(Hl+byte)
4. (flag)
CY
=
HC
Carry
=
Half Carry
Z
=
Zero
Instruction Groups
8-bit Data Transfer
Dpcode
Mnemonic
Operand
B1
B2
B4
0001lT2T1TD
4
(r1j-(A)
OOOOlT 2TIT D
4
(Aj-(r1)
sr. A
01001101
r1. A
-_.-------_."._-------------.-
----_.-._.--------- .. -.--------------_.------------_.".----_._-_ .. ------------_.--------._-
-----._.---------.---------- ----------.-----_._. ----_.-------_.-----------
110S4S3S2S ISO
---------_ .. _------._---------._._-_._--------------- .. --.--------_.-----------_.-.-----._-_ .. ------._-- -------------------_.----------_
Skip
Condition
Operation
State 1
A. r1
.......... ---------------
MOV
B3
10
(srJ-(A)
-----_._.--. __ ._ .. ---------_.---
.-------------------- ---_._-_.,,-_ .. _----
A. sr1
01001100
l1S5S4S3S2S1S0
10
(Aj-(sr1)
... __ ._----- .... _-----_ ...... .. _-------- .. _--_._----_._ .. _._----,_ .. - ... _---,_.- .. _._--,_ ......... _--_ ..... .. _----, ... _._._---_._._-,--_ ..... _-_ .... _._-_ ....... ...... _,--_._ .... _--_ ...... _._.,-----, ..... _----"-_ ..... _---- .... _-_._ ..... _..
_
_
_
r. ......
word
01110000
01101R2R1Ro
low Addr High Addr
17
(rj-(wordj
---_.,
__ ._._,-_ ....... _.. -... _.... _--_ .. _---_ .... __ ._. __ .. __ .... _--_.-_ .... _-_. __ ... __ .. _---- .. _..•. __ ..... _.... _._ ....... _-_._ ... _--_.- ... ............. _. __ ._._ .. _--_ ...... ,--_ ..... _.... _-_ ..... _.... .. _.... __ ........ _--_ ..
_
MVI
word. r
01110000
r. byte
01101R2R1RO
High Addr
17
01100100
MVIW
wa. byte
MVIX
rpa1. byte
STAW
wa
_
(wordj-(r)
(rJ-byte
String skip. when r
Data
--_ ..... _._--_ ...... _._._--_ .......... __ .. _--_ ..... _.... _._, .... _-_._ ...... __ .. _._ ... _... __ ._. __ ....... _._"--
sr2. byte
4-162
low Addr
..... __ ... -... _.- ..... -....
14
(sr2j-byte
S;P000S2S1S0
Data
01110001
Offset
Data
13
((V). (wa)J-byte
01 001 OA lAo
Data
10
(rpal)-byte
01100011
Offset
10
((V)(wall-A
=
A or l
NEe
pPD78PG11
Instruction Groups (cont)
8-Bit Data Transfer (cont)
Opcode
Mnemonic
Operand
B1
B2
B3
B4
State 1
LDAW
wa
00000001
Offset
STAX
rpa2
A3 0111 A2A lAo
Data 2
10
7113 3
LDAX
rpa2
A30101 A2A lAo
Data 2
7113 3
Skip
Condition
Operation
IA)-((V). Iwall
Irpa2)-IA)
IAI-lIrpa211
EXX
00010001
B
IB)-IB'). IC)-IC'). ID)-ID')
IE)-IE'). IH)-IH'). IL)-IL')
EXA
00010000
8
IV)-IV'). IA)-IA'I. IEA)-IEA')
EXH
01010000
8
IH)-IH'). IL)-IL')
16-bit Data Transfer
BLOCK
00110001
rp3. EA
. __
13
IIDEII-IIHLII. IDE)-IDE 1+ ),
1) IHL)-IHL) + 1. IC)-IC) - 1
End if borrow
Irp3d-IEAL). Irp3 H)-lEAH)
c+
101101P1 PO
4
EA. rp3
101001P1PO
4
sr3. EA
01001000
.... _--- .. _-----------
DMOV
I
------_ .... _----.- .. _---------
._----_ .... _---.-_.---_ .... _--------_ .. _-_._-- ..... -_._._.--
.- ... _._--_ ....
------._---------_. ------------_ .... -.. _-------------------_ .. _--
1101D01U o
···EA:··~·~4········ ··········l····················i·iiiiiiiiiv;·ii~···········
01110000
00011110
..............................................
Low Addr
IEALI-Irp3d.IEAHI-Irp3H)
----.- ..
------------_ ... _------ ... _-----_._._---------_._. --.--------_ .. _--_ .. _----
Isr3)-IEA)
···i4········"iE"Ai=·i~·~4i············
................................
SBCD
word
20
Iword)-IC). ((word) + 1) -IB)
SDED
word
00101110
20
Iword)-IE). ((word) + 1) -ID)
SHLD
word
00111110
20
Iwordl-IL). ((wordl + II -IHI
SSPD
word
,
20
Iword)-ISPd.llword + 1) ISPH)
STEAX
rpa3
01001000
01110000
00001110
High Addr
14
If
14120 3 IIrpa311-IEAL). IIrpa3) + 1)lEAH)
Data 4
LBCD
word
20
ICI-Iword). IBJ-lIwordl + I)
LBCD
word
00101111
20
IE)-Iword). ID)-((wordJ + 1)
LHLD
word
00111111
20
IL)-Iword). IH)-((word) + 11
LSPD
word
00001111
20
ISPd-lword). ISPH)-((word)
+ 1)
LDEAX
rpa3
01001000
PUSH
rpl
10110020100
13
((SPJ - lJ-lrplHIIISP) - 2J Irpl ~ISPJ-ISPJ - 2
POP
rpl
10100020100
10
Irpl d-((SPII. Irpl HJ-IISP) + 1)
ISP)-ISP) + 2)
LXI
rp2. word
OP2P1Po0100
10
Irp2)-lwordl
String skip when rp2
17
(C)-((PC) + 3 + IAII
B-((PC) + 3 + IA) + 1)
00011111
Low Addr
High Addr
If
1000C3C2C1CO
14120 3 IEALI-((rpa3)). IEAHI-lIrpa3J + 1)
Data 4
Low Byte
High Byte
=
H
8-bit Aritmetic (Register)
TABLE
01001000
A. r
ADD
r. A
11000R R1R0
2
-------------------.-._------_._-------.. _-----------. ._-------------_.-------
r. A
A. r
ADC
01100000
10101000
01000R 2R 1Ro
-------------- --------------
11010R2R1Ro
----------------------------01010R 2R1Ro
-.. _--- ---------
8
8
IAI-IA) + Ir)
----------------------------------------------Ir)-Ir) + IA)
8
IA)·-IA) + Ir) + ICY)
.--~
-------------------------
--------------------
-------------_ .. _---
Ir)-Ir) + IA) + ICY)
4-163
NEe
pPD78PG11
Instruction Groups (cont)
8-Bit Arithmetic (Register) (cont)
Ope ode
Mnemonic
AOONC
Operand
A. r
B1
B2
B4
B3
01100000
10100R2R)RO
.... -_ .. _-_ ............... __ ... _-------_ .................. __ .. _-_ ...... -.......... -
........ __ .......... __ ... _-_._- ... __
r. A
State 1
Skip
Condition
Operation
8
(A)-(A) +(r)
No Carry
8
(r)-(r) + (A)
No Carry
........... -......................... -- .................... _-_ ................................. -........ -_ ..... .
00100R2R) Ro
SUB
A. r
11100R2R)Ro
8
(A)-(A) - (r)
..... __ ..... __ ................ _.. _.. _................... --0 __ .... _--_ .... ·... _--_ ............................ __ ................... _......... _............. _........... _...... __ ......... ___ ................... _..... __ ... _._. __ ......... .
SBB
8
(A)-(A) - (r) - (CY)
-_ ....... ........... __ ... _-_ ...... _-_ ... _-_ ................................................................... ... ...... _. __ ............ -........................... -........ ...................... -.. ... _.
r. A
SUBNB
ANA
XRA
GTA
LTA
NEA
_
,
_
_
r. A
8
_
__
............... _-_. __ ... .
(r)-(r) - (A) - (CY)
A. r
10110R2R)RO
8
(A)-(A) - (r)
No Borrow
r. A
00110R 2R) Ro
8
(r)-(r) - (A)
No Borrow
A. r
10001R2R)Ro
8
(A)-(A) .\ (r)
._ ................................ _................ _................................ _._ ............ _............ _ ... -.... -............................... _ ... _............... -- ....... _.... .
···~·:i··························~ ·····················ooool·ii~R·;i~·············
01100000
··············································8· ·······i~i·:i~i··:\··iAi"······························ ...........................
10011R2R)Ro
8
(A)-(A)V(rlJ
r. A
00011 R2R )Ro
8
(r)-(r)V(A)
A. r
10010R2R)Ro
8
(A)-(AJV(rlJ
A. r
10101 R2R )RO
........... __ ....... -................................................... _........... _......... -................... _........... _.............. _ ........ __ ................. -.... -.................... _.. - _........ _.. -._ .............. _ ..
................. _.... _....... _._ ........ _................... _ ...................... _........ _...... _........... __ ..................... _._ .......... _....... -..... ' - ' - " - " ' - " - " ' .
. ..................... _ ........ .
8
(A) - (r) - 1
No Borrow
8
(r) - (A) - 1
No Borrow
...... _......................... _................. _............. _........... _....... _.... -...... _.................... _ .. _.... -._ ............. _ .......... -.......... __ ... _...... _.- .... __ ......... -._ ................. _ .......... _ ....... .
r. A
....~: ..~.................................................~~.1.~.~.~~~.~~.~.....................................................,.........~..........!~! ~ ~~!
r. A
00111R2R)Ro
8
(r) - (A)
. . .............................................~~~.~~~ .........
Borrow
A. r
11101R2R)Ro
8
(A) - (r)
............. .. -._ ............. _._ .................................... -..................... _._ ................. ....................................... _._ ......... .....
_
_
r. A
01101R2R)Ro
A. r
EQA
(r)-(r) - (A)
11110R2R)RO
A. r
ORA
8
01100R2R)Ro
A. r
_
No Zero
_
.............................................. _...... " ' -
8
(r) - (A)
No Zero
8
(A) - (r)
Zero
r. A
01111R2R)Ro
8
(r) - (A)
Zero
ONA
A. r
11001 R2R )RO
8
(A).\(r)
No Zero
OFFA
A. r
11011R2R)Ro
8
(A).\(r)
Zero
01100000
8-bit Arithmetic (Memory)
ADDX
rpa
11000A2A)Ao
11
(A)-(A) + IIrpalJ
ADCX
rpa
11 01 OAzA )A 0
11
(A)-(A) + IIrpalJ + (CY)
ADDNCX
rpa
10100AzA)A 0
11
(A)-(A) + IIrpalJ
SUBX
rpa
11100AzA )A 0
11
(A)-(A) - IIrpalJ
SBBX
rpa
11110AzA)Ao
11
(A)-'-(A) - IIrpalJ - (CY)
SUBNBX
rpa
10110AzA )Ao
11
(A)-(A) - IIrpalJ
ANAX
rpa
10001A2A)AO
11
(A)-(A) - IIrpalJ
ORAX
rpa
10011AzA )AO
11
(A)-(A)VllrpalJ
XRAX
rpa
10010A2A)Ao
11
(A)-(A)V((rpalJ
GTAX
rpa
10101A 2A)A 0
11
(A) - IIrpalJ - 1
No Borrow
LTAX
rpa
10111A2A )Ao
11
(A) - IIrpalJ
Borrow
NEAX
rpa
11101A2A)AO
11
(A) - IIrpalJ
No Zero
EQAX
rpa
11111A2A)Ao
11
(A) - IIrpalJ
Zero
ONAX
rpa
11001AzA)Ao
11
(A)-lIrpalJ
No Zero
OFFAX
rpa
11011A2A)Ao
11
(A)-lIrpalJ
Zero
4-164
01110000
,
No Carry
No Borrow
NEe
pPD78PG11
Instruction Groups (cont)
Immediate Data
Opcode
Mnemonic
*
ADI
ACI
ADINC
8UI
B2
A. byte
01000110
-Data-
r. byte
01110100
01ODOR2R1Ro
sr2. byte
0110 I
8310008~180
A. byte
01010110
-Data-
r. byte
01110100
01010R2Rl RO
B3
B4
.-._-----.-----.-.----------------------_.--._--- --------._----_.-----.-.--------------_.-
sr2. byte
0110 I
8310108~180
A. byte
00100110
-Data-
r. byte
01110100
00100R2R1RO
sr2. byte
0110 I
8aOl00828180
A. byte
01100110
-Data-
r. byte
01110100
01100R R1R0
sr2. byte
0110 I
State 1
Skip
Condition
Operation
(A)-(A) + byte
Data
.------- .. -------.------ .. ----._------._-----.-.--- ---------------._-----.-------.-._----.---------------".----------------
---- -------
11
(r)-(r) + byte
20
(sr2)-(sr2) + byte
11
(r)-(r) + byte + (CY)
20
(sr2)-(sr2) + byte + (CY)
-------.---------._------_._-------._ .. _----------------.----------- .---------------._----
(A)-(A) + byte + (CY)
Data
(A)-(A) + byte
No Carry
(sr2)-(sr2) + byte
No Carry
----------_.-----._.-- ------------------------- -.----------------------------------- .. _----------.--- -._.-_ .. --------._-------- .. -Data
11
(r)-(r) + byte
No Carry
.----------------------------------._-----.-------.------ .. ---------_._- .. _.-------_. ---_ .. _---_ ... _---_ .. _----_._.------_.------------------------------------------_._---------_._------------------- -------------------------------
2
-------------------- ------------------------------------------------_._---._---------------A. byte
8BI
Bl
Operand
01110110
-Data-
r. byte
01110100
01110R R R
sr2. byte
0110
8311108~180
20
(A)-(A) - byte
Data
11
(r)-(r) - byte
20
(sr2)-(sr2) - byte
(A)-(A) - byte - (CY)
Data
11
(r)-(r) - byte - (CY)
20
(sr2)-(sr2) - byte - (CY)
2 1 o ---_.-----_._._---------------- ----_._---------------_._---------------_._------_._---------------------_._-------------------------------------------------------_._---- --------------------------- ------------_._-------_._---j
*
A. byte
00110110
-Data(A)-(A) - byte
No Borrow
...........................................................................................................................................................................................................................................
8UINB
ANI
ORI
XRI
r. byte
01110100
00110R2R1RO
sr2. byte
0110 I
8aOll08~180
A. byte
00000111
-Data-
-----------_. __ ._-----_._--------------------------------_._-----_._---_._------_._-----_.
_..
_---- .. _------_._._--_ .. _. __ ._-
sr2. byte
01100100
830001828180
-Data-
A. byte
00010111
r. byte
01110100
sr2. byte
0110 I
8300118~180
A. byte
00010110
-Data-
00011 R2R lRO
-_ .. __ ._-_. __ .. _- .. -.. _-_._---- ... _._- .. __ .---._-_ ... .. __ ... .. _--_ .. _-- .. _-----_. __ ._
r. byte
01110100
_.-._---_.-_.-.- ... _--- ..... _- .... _--- .. _._----_.A. byte
0110 I
(r)-(r) - byte
No Borrow
(sr2)-(sr2) - byte
No Borrow
. __ ._---. __ .. __ ._--- .. __ .. _-._-_ .. _- .. __ ._--._-_.-._---_._--_._. -. __ ._-----_ .... _-._-_.-
~.~
~~~.=~r.) . ~~~!.~................................
............... .........
20
(sr2)-(sr2);\byte
11
(r)-(r)Vbyte
20
(sr2)-(sr2)Vbyte
(A)-(A)Vbyte
Data
_
00010R2R1RO
... .. .. _.. _. __ ._ .. _- ... _._--_.-_._-----_
11
20
(A)-(A).\byte
. . r. . ~.~~~...............~1.~.1.~1~.~................~~~~l."-tl.!.~.~........... ......n.~.~~....................
sr2. byte
(A)-(A)Vbyte
Data
11
(r)-(r)Vbyte
-- .. -_ .. _-- .. _._---_ ... __ .. _-_ .... __ .. _-._-_.----_ .... --- .. _.... .. __ .
_
_
8a00108 28 180
20
_
.. _._ .. __ ._._- .. __ .. _- ... __ .. -- .. _._ .. -
(sr2)-(sr2)Vbyte
00100111
- Data-
r. byte
01110100
00101 R2R 1R0
sr2. byte
0110 I
8a0101 8~ 180
14
(sr5) - byte - 1
A. byte
00110111
-Data-
7
(A) - byte
Borrow
r. byte
01110100
00111 R2R lRO
11
(r) - byte
Borrow
sr2. byte
0110 I
8301118~180
14
(sr5) - byte
A. byte
01100111
-Data-
7
(A) - byte
r. byte
01110100
01101 RzR lRO
sr2. byte
0110 I
8311018~180
A. byte
01110111
-Data-
----------._-_. __ .--_ .. -.. -_.
GTI
Data
.._-_ .. _-- .. __ ._.- .. _--_.-
-... _-- .. _-_._ ... _-- . __ .. _-- .. _--_ ....... _-_._._- .. -._----_. __ .. _- .. _...
-_ .. _._--_. __ ._- .... _---_ .... -..... -- .. _ .. _--. __ .. _-.--- -.-_._--- ... _._--.--_._----_..
Data
.._ ... _- .. __ ._._-----_ .. _- ... _-_ .. -
7
(A) - byte - 1
No Borrow
11
(r) - byte - 1
No Borrow
._-_ .. _._----_._-- .. __ .. _----_ .. _._- .. __ .. _--- .. __ ._- ... ---._---_. __ ._-- -.. _ ... _-._-_ ... -..... --
------_._- .. __ .. _--. __ .. _-- ....... .. _-_
._-_._--._._ ... --_. __ ._-
No Borrow
.__ .. __ ._-_._-----_.- .. ------._.--- ... _... -._-_.- .. _--._-_._--_ .... __ ._-_._-_._-.----_. __ ... _ .. _- ... _ ....... ---_ .... __ .... -... _--_ .... _--_ .. -- ... __ .. -._._--_._-.-.-_ ... --. __ .... _-_ .. __ .- .. __ .. -.. __ .. -._-_._-_._-_ ..... __ .--
LTI
NEI
EOI
-_"""-"".---.---.
--_._----_ ... -._-_ .. _- .. __ .. -.. _--- .. _----- ...
_
... -.--_ .. _- .. _ ... -... -
Data
Data
-.--_ .. _- .. _--_ .. -.---_ .... _--_ ... _----_ ... _--_ .. _--- ...
.-._--- .. --_ .. -.. -----._-_ ..... _--_.- .. _-_.- .. __ ._.- .. ------ .... _._----_ .. _-._ .. __ .- .. _--_ .. -._--_ .. --._----._-_._-_.
.. _---. __ ... _. __ ... _-. __ .--. __ .. --- .. _ ..
11
(r) - byte
-- .. __ ._--.--_ .... __ ... _-_._- ... _--_ ..
14
Data
_
(sr5) - byte
Borrow
No Zero
No Zero
No Zero
(A) - byte
Zero
11
(r) - byte
Zero
14
(sr5) - byte
Zero
4-1RR
4
NEe
J-LPD78PG11
Instruction Groups (cont)
Immediate Data (cont)
Opcode
Mnemonic
Operand
82
81
A. byte
01000111
-Data-
r. byte
01110100
01001 R2R IRo
sr2. byte
0110 I
A. byte
01010111
-Data-
r. byte
01110100
01011R~IRo
sr2. byte
0110 I
ADDW
wa
01110100
ADCW
wa
1101
ADDNCW
wa
SUBW
83
84
State 1
Operation
Skip
Condition
(A).\byte
No Zero
11
(r).\byte
No Zero
14
(sr5).\byte
No Zero
7
(A).\byte
Zero
11
(r).\byte
Zero
14
Isr5).\byte
Zero
14
(A)-IA) + ((V)o(wall
14
(A)-(A) + ((V) -(wall + (CY)
1010
14
(A)-IA) + ((V)o(wall
wa
1110
14
IA)-IA) -((V)-(wall
SBBW
wa
1111
14
IA)-IAI - ((V)o(wall - (CYI
SUBNBW
wa
1011
14
IA)-(A) - ((VI-(wall
ANAW
wa
10001000
14
(A)-IA)A((V) - (wall
ORAW
wa
XRAW
wa
GTAW
wa
LTAW
wa
NEAW
EQAW
ONAW
wa
OFFAW
wa
ONI
Data
---------.------------------------._----------------------------------------------------_."-._----------------------._------------_ .. _-------.------------_.---------------_.-------------------------- .. _-------------.----.-----------.-
OFFI
-------------------------.--------.---------_.
Data
------_ ... _---_._---------.--------.-.----------------------_.------.-----------------------._------.--------.-------. -----_.------- .. ------------------_.--------
Working Register
ANIW
1
11000000
Offset
1001 I
No Carry
No Borrow
14
IA)-(A)V((V) -(wall
14
(A)-IAIvt(V)o(wall
10101000
14
IA) - ((V)-(wall - 1
No Borrow
1011
14
IA) - ((V) - (wall
Borrow
wa
1110
14
IA) - ((V) - (wall
No Zero
wa
1111
14
(A) - ((V) - (wall
Zero
1100
14
IAI.\((VI- Iwall
No Zero
1101
14
IA).\((V)o(wall
Zero
01110100
,
10010000
Offset
wa. byte
00000101
19
((V) -Iwall-((V)o(wall.\byte
ORIW
*
wa. byte
0001
19
((V) -(wall-((V) -IwallVbyte
GTIW
*
wa. byte
0010
13
((V)o(wall - byte - 1
No Borrow
LTIW
*
wa. byte
0011
13
((VI- Iwall - byte
Borrow
NEIW
*
wa. byte
0110
13
((V) -Iwall - byte
No Zero
EQIW
*
wa. byte
0111
13
((V)- Iwall -byte
Zero
ONIW
*
wa. byte
0100
13
((V) -Iwall .\byte
No Zero
OFFIW
*
wa. byte
0101
13
((V)o(wall·\byte
Zero
11
IEA)-IEA) + (r2)
11
(EA)-IEA) + Irp3)
IEA)-IEA) + Irp31 + ICY)
-Offset-
Data
1
16-bit Arithmetic
EADD
EA. r2
DADD
EA. rp3
DADC
EA. rp3
11
DADDNC
EA. rp3
11
lEAl-lEA) + Irp3)
ESUB
EA. r2
0000
011000RIR o
11
IEA)-IEA) - Ir2)
DSUB
EA. rp3
01110100
111001 PIPO
11
IEA)-IEA) - (rp3)
DSBB
EA. rp3
11
IEA)-IEA) - Irp3) - ICY)
DSUBNB
EA. rp3
1011
DAN
EA. rp3
100011P IPO
4-166
01110000
010000RI Ro
0100
1111
I
t
11
IEA)-IEA) - Irp3)
11
lEAl-lEAl - Irp31
No Carry
No Borrow
NEe
pPD78PG11
Instruction Groups (cont)
16-Bit Arithmetic (cont)
Opcode
Operand
DOR
EA. rp3
11
(EA)-(EA)V(rp3)
DXR
EA. rp3
100101 PIP O
11
(EA)-(EA)V(rp3)
DGT
EA. rp3
101011 PIP O
11
(EA) - (rp3) - I
No Borrow
DLT
EA. rp3
lOll
11
(EA) - (rp3)
Borrow
Bl
B2
B3
B4
01110100
State 1
Operation
Skip
Condition
Mnemonic
ONE
EA. rp3
1110
11
(EA) - (rp3)
No Zero
DEQ
EA. rp3
1111
11
(EA) - (rp3)
Zero
DON
EA. rp3
1100
11
(EA).\(rp3)
No Zero
DOFF
EA. rp3
1101
11
(EA). \[rp3)
Zero
MUL
r2
32
(EA)-(A)
59
(EAI-(EAI + (r2).
(r2)-Remainder
4
(r2) - (r2) + I
Carry
16
((V). (wall-((V). (wall + I
Carry
if
MultiplyIDivide
01001000
DIV
r2
INR
r2
010000R I Ro
INRW
wa
00100000
rp
00P I Po0010
001011 RIRo
0011 1
x
(r2)
Increment/Decrement
INX
.. _--.
EA
10101000
OCR
r2
010100RI Ro
DCRW
wa
00110000
DCX
-Offset-
(rp)-(rp) + I
--------------_.-- .. _---------
rp
OOPIPoOOII
EA
10101001
(EAI-(EA) + I
4
-Offset-
16
(r2)-(r2) - I
Borrow
((V). (wall-((V). (wall - I
Borrow
(rp)-(rp) - I
--- ---- --- --_._-------------------.
(EA)-(EA) - I
Others
DAA
01100001
STC
01001000
4
Decimal Adjust Accumulator
00101011
8
(CY)-I
CLC
00101010
8
(CY)-O
NEGA
00111010
8
(A)-(A) + I
Rotate and Shift
RLD
01001000
RRD
00111000
17
Rotate Left Digit
1 1001
17
Rotate Right Digit
001101 RIRo
(r2 M+ 1)-(r2 M). (r2 0)-(CY).
(CY)-(r2 7)
r2
1 OOR IRo
(r2M + 1)-(r2M).(r2 7)-(CY).
(CY)-(r2 0)
SLL
r2
001001 RI Ro
(r2M + JI-(r2M).(r2 0)-0.
(CY)-(r27)
SLR
r2
OORIRo
(r2 M _11-(r2 MI. (r2 71--0.
(CY)-(r2 0)
SLLC
r2
OOOOOIRIRo
(r2M + 1)-(r2 M). (r201-0.
(CY)-(r2 7)
Carry
SLRC
r2
100RI RO
(r2 M _ II' (r2 MI. (r2 71-0.
(CY)-(r2 0)
Carry
RLl
r2
RLR
01001000
j
A.-1R7
Il
NEe
",PD78PG11
Instruction Groups (cont)
Rotate and Shift (cont)
Ope ode
Mnemonic
Operand
oRLL
EA
oRLR
EA
oSLL
EA
oSLR
EA
B1
01001000
B3
B2
B4
Operation
State 1
(EAN + I)-(EA N). (EAo)-(CV).
(CV)-(EA I5)
10110100
8
0000
8
10100100
8
(EAN _1)-(EA N).(EAI5)-(CV),
(CV)-(EA o)
(EA N+ I)-(EAN). (EAo)-O.
(CV)-(EA 15)
8
(EA N-I)-(EA N). (EAI5)-0
10
(PC)-word
j
j
0000
Skip
Condition
Jump
JMP
word
01010100
-Low Addr-
High Addr
00100001
JB
JR
word
ll-jdisp 1-
JRE
word
0100111-
jdisp-
01001000
00101000
JEA
4
(PCH)-(8). (PCd-(C)
10
(PC)-(PC) + 1 + jdisp 1
10
(PC)-(PC) + 2 + jdisp
8
(PC)-EA
16
liSP) - l)-IIPC) + 3)H.
liSP) - 2)-IIPC) + 31L.
(PC)-word. (SP)-(SP) - 2
Call
CALL
word
CALB
01000000
-Low Addr-
01001000
00101001
17
liSP) - l)-IIPC) + 2)H.
liSP) - 2)-((PC) + 2)L.
(PCH)-(B). (SP)-(SP) - 2
la-
13
liSP) - l)-((PC) + 2)H.
liSP) - 2)-I\PC) + 2)L.
(PC 15_11)-00001.
(PCIO-oI-la. (SP)-(SP) - 2
High Addr
CALF
word
01111-
CALT
word
100-ta-
16
liSP) - 1)-((PC) + I)H.
liSP) - 2)-I\PC) + III
(PCt.\-(128 + 2ta). (P~) (129 + 2ta). (SP)-(SP) - 2
01110010
16
liSP) - l)-(PSW). liSP) - 2)IIPC) + l)H. liSP) - 3)-IIPC)
+ l)L. (PC)-0060H. (SP)(SP) - 3
10111000
10
(PC)-IISP)). (PC ~-ItSP) + 1)
(SP)-(SP) + 2
1001
10
(PCt.\-IISP)). (PCH)-IISP) + 1)
(SP)-(SP) + 2. (PC)-(PC) + n
01100010
13
(PCJ-IISP)), (PCHI-I\SP) + 1)
(PSW)-IISP) + 2). (SP)-(SP)
+ 3
Unconditional Skip
10
Bit Test
ltV). (wall
bit = 1
SOFT!
Return
RET
RETS
j
RETI
Skip
BIT
bit. wa
01011B2BIBo
-Onset-
01001000
0001F2Fl f o
8
Skip if 1= 1
1= 1
0001
8
8
Skip if 1= 0
Skip il irl = 1. then reset Irl
1=0
irf = 1
CPU Control
SK
SKN
SKIT
4-168
irf
•
j
01 01 41312111 0
NEe
pPD78PG11
Instruction Groups (cont)
CPU Control (cont)
Ope ode
Mnemonic
Operand
SKNIT
irf
Bl
01001000
B2
B3
B4
State 1
8
01114131211 10
Operation
Skip if irf = 0
Reset irf, if irf = 1
NOP
00000000
4
No Operation
EI
10101010
4
Enable Interrupt
4
Disable Interrupt
11
Halt
DI
10111010
HLT
01001000
Notes:
*
*
*
*
00111011
Skip
Condition
irf = 1
1 :In the case of skip condition, the idle states are as follows:
1-byte instruction: 4 states 2-byte instruction (with *): 7 states
2-byte instruction: 8 states 3-byte instruction (with *): 10 states
3-byte instruction: 11 states 4-byte instruction (with *): 14 states
2: B2 (Data):rpa2 = D + byte. H + byte.
3: Right side of slash (I) in states indicate case rpa2, rpa3 = D + byte, H + A, H + B, H + EA, H + byte.
4: B3 (Data): rpa3 = D + byte, H + byte.
Emulating the JlPD7811
To emulate thetJPD7811: tie MODEO to ground and pull
up MODE1 through a 10-kO resistor; insert a 2732A or
2764 into the upper terminals of the tJPD78PG11. If a
2732 is used it should be inserted so that pin 1 of the
2732A goes into terminal 3 (see pin configuration). If a
2764 is used, address line A12 will be held low so that
only memory locations O-OFFFH (the lower 4K bytes)
of the 2764 will be accessed. This simulates accessing
4K bytes of masked-ROM in the tJPD7811. In other
respects tJPD78PG11 is functionally equivalent to
tJPD7811.
3. Control Lines
Under software control, each line of Port C can be
configured individually to provide control lines for
serial interface, timer, and timerlevent counter.
Input/Output
4. Memory Expansion
In addition to the single-chip operation mode,
tJPD78PG11 has 4 memory expansion modes. Under
software control, Port D can provide multiplexed
low-order address and data bus and Port F can
provide high-order address bus. The relation
between memory expansion modes and the pin
configurations of Port D and Port F is shown in the
table that follows.
8 Analog Input Lines
44 Digital 110 Lines: five 8-bit ports (Port A, Port S, Port
C, Port D, Port F) and 4 input lines (AN4-AN7)
Memory
Expansion
1. Analog Input Lines
ANa-AN7 are configured as analog input lines for
on-chip AID converter.
2. Port Operation
-Port A, Port S, Port C, Port F
Each lineof these ports can be individually programmed as an input or as an output. When used
as 1/0 ports, all have latched outputs, high-impedance inputs.
-Port D
Port 0 can be programmed as a byte input or a
byte output.
- AN 4- AN 7
The high-order analog input lines, AN4-AN7 can
be used as digital input lines for falling edge
detection.
None
256 Bytes
4K Bytes
16K Bytes
60K Bytes
Port Configuration
Port D
I/O Port
Port F
I/O Port
Port D
Multiplexed Address/Data Bus
Port F
I/O Port
Port D
Multiplexed Address/Data Bus
Port Fo-Fa
Address Bus
Port F4 - F7
I/O Port
Port D
Multiplexed Address/Data Bus
Port Fo- F5
Address Bus
Port Fo- F7
I/O Port
Port D
Multiplexed Address/Data Bus
Port F
Address Bus
4-169
NEe
J,LPD78PG11
Memory Map
The J.lPD78PG11 can directly address up to 64K bytes
of memory. Except for the EPROM (0-4,095) and RAM
(65,280-65,535), any memory location can be used as
ROM or RAM. The following memory map defines the
0-64K-byte memory space for the J.lPD78PG11.
Memory Map
Reset/Standby Relsase
IRQO
Internal ROM
4,096 Bytes x B
IRQ1
OFFFH
1000H
External
Memory
61,184 Bytes x 8
10H
IRQ 2
1BH
IRQ3
20H
IRQ 4
28H
IRQS
FEFFH
FFOOH
IntemalRAM
256BytesxB
FFFFH
~1
SoftlNT
BOH
LowADDR
81H
HighADDR
82H
LowADDR
B3H
HlghADDR
I
}t=o
}t=1
LowADDR
HighADDR
}t=31
User's Area
49-0001728
4-170
NEe
pPD78PG11
Timers
Timer /EventCounter
The timer/event counter consists of two 8-bit timers.
The timers may be programmed independently or may
be cascaded and used as a 16-bit timer. The timer can
be set in software to increment at intervals of 4 machine
cycles (1,us at 12MHz operation) or 128 machine cycles
(32,us at 12MHz), or to increment on receipt of a pulse
at T1.
The 16-bit multifunctional timer/event counter can be
used for the following operations:
o Interval timer
o External event timer
o Frequency measurement
o Pulse width measurement
o Programmable square-wave output
Timer Block Diagram
,-----Timer 0
Timer 1
r - - - - - - --1
Timer/Event
Counter
Serial
Interface
49-0001738
.:1.-171
NEe
jLPD78PG11
Block Diagram for Timer IEvent Counter
4CL
PCsfCI
CP,
TO
pc./co.
CPo
Output
Control
EIN
pC.tco,
CPo
CP,
INTEO
Interrupt
Control
INTEl
EIN
INTEIN
Note:
=
CL 311 [250 ns; 12 MHz operation].
f: System clock frequency [MHz].
49-oo0174B
8-Bit AID Converter
o8
o
o
o
o
o
o
o
input channels
4 conversion result registers
2 powerful operation modes
-Autoscan mode
-Channel select mode
Successive approximation technique
Absolute accuracy: ±1.S LSB (±O.6%)
Conversion range: OV to SV
Conversion time: SOILS
I nterrupt generation
AnaloglDigital Converter
The JlPD78PG11 features an 8-bit, high-speed, highaccuracy AID converter. The AID converter consists of
a 256-resistor ladder and a successive approximation
reg!ster (SAR). There are four conversion result registers (CRo-CR3). The 8-channel analog input may be
operated in either of two modes. I n the select mode, the
conversion value of one analog input is sequentially
stored in CRo-CR3. In the scan mode, the upper four
4-172
channels or the lower four channels may be specified.
Then those four channels will be consecutively selected
and the conversion results stored sequentially in the
four conversion result registers.
AID Converter Block Diagram
~cc~-----------------,
AVs.o--------------,
VAREF 0------------------,
AN. 0--------1
AN,o-----t
AN. 0--------1
AN 3 0 - - - - - t
AN. 0-----.-1
AN. 0---+-+-1
AN. o-----..+-+-t
AN, o--~+-+-t
Internal Bus
49-000175A
NEe
pPD78PG11
Interrupt Structure
Universal Serial Interface
There are 11 interrupt sources. Three are external
interrupts and 8 are internal. These 11 interrupt sources
are divided into 6 priority levels as shown in the table
below.
The serial interface can operate in any of three modes:
synchronous, asynchronous, and I/O interface. The
I/O interface mode transfers data MSB first for ease of
communication with certain peripheral devices. Synchronous and asynchronous modes transfer data LSB
first. Synchronous operation offers two modes of data
reception. In the search mode, data is transferred one
bit at a time from serial register to receive buffer. This
allows a software search for a sync character. In the
nonsearch mode, data transfer from serial register to
transmit buffer occurs 8 bits at a time.
Interrupt Interrupt
Request
Type of Interrupt
InlExt
4
NMI
(Nonmaskable interrupt)
External
IRQ I
8
INTTO (Coincidence signal from
timer 0)
INTTI (Coincidence signal from
timer I)
Internal
IRQ2
16
INTI
INT2
External
IRQ3
24
INTEO (Coincidence
ti mer / event
INTEl (Coincidence
timer/event
IRQ4
32
INTEIN (Falling signal of Cl and
TO counter)
INTAD (A/D converter interrupt)
In/External
IRQ5
40
INTSR (Serial receive interrupt)
INST (Serial send interrupt)
Internal
IRQO
(Maskable interrupt)
(Maskable interrupt)
signal from
counter)
signal from
counter)
Universal Serial Interface Block Diagram
Internal
PC,IRxD
Il
PC,.ISCKo--~<
Interrupt Structure Block Diagram
NMI
INTTO
SK.. SK,
PCoITxD
49-000177A
INTTI
INTI
1NT2
INTEO
INTE1
INTEIN
INTAD
INTSR
INTST
ov
ER
SB
AN 7 -AN.
Zero-crossi ng Detector
The INT1 and INT2 terminals (used common to TI and
PC3) can be used to detect the zero-crossing point of
slow moving AC signals. When driven directly, these
pins respond as a normal digital input.
To utilize the zero-cross detection mode, an AC signal
of approximately 1-3V AC peak-to-peak magnitude
and a maximum frequency of 1kHz is coupled through
an external capacitor to these pins.
Standby Function
The pPD78PG11 offers a standby function that allows
the user to save up to 32 bytes of RAM with backup
power (VOD) if the main power (Vee) fails. On powerup
the pPD78PG11 checks whether recovery was made
from standby mode or from cold start.
For the INT1 pin, the internal digital state is sensed as
a zero until the rising edge crosses the DC average
level, when it becomes a one and INT1 interrupt is
generated.
For the INT2 pin, the state is sensed as a one until the
falling edge crosses the DC average level, when it
becomes a zero and INT2 interrupt is generated.
The zero-cross detection capability allows the user to
make the 50-60Hz power signal the basis for system
timing and to control voltage phase sensitive devices.
4-173
NEe
jlPD78PG11
Operand Format/Description
Zero-Crossing Detection Circuit
IINT1
C
IINT2 (PC31
~~--~--~~--,~~--~~~--
Format
Description
r
rl
r2
V. A. B. C. D. E. H. L
sr
sr2
sr3
sr4
PA. PB. PC. PD. PF. MKH. MKL. ANM. 8MH. SML. EOM. ElMM.
TMM. MM. Mee. MA.MB. MC MF. TxB. TMo. TMI
PA. PB. PC. PD. PF. MKH. MKL. ANM. SMH. EOM. TMM. RxB.
eRo; CR I. CR2; CR3
PA. PB. PC. PD. PF. MKH. MKL. ANM. SMH. EOM. TMM
ElMo. ElMI
ECNT. ECPT
rp
rpl
rp2
rp3
SP. B. D. H
V. B. D. H. EA
SP. B. D. H. EA
B. D. H
rpa
rpal
rpa2
rpa3
B.
B.
B.
D.
srl
83-003835A
EAH. EAL. B. C. D. E. H. L
A. B. C
D. H. D+. H+. D-. HD. H
0. H. D+. H+. D-. H-. D+ byte. H+ A • H+ B. H+ EA. H+ byte
H. D+. H+ +. D+ byte. H+ A. H+ B. H+ EA. H+ byte
wa
8-bit immediate· data
word
byte
bit
l6-bit immediate data
B-bit immediate data
3-bit immediate data
CV. He.
irf
4-174
z
FNMI. flO. FTl. Fl. F2. FEO. FE1. FEIN. FAD. FSR. FST. ER. OV.
AN4• AN 5• AN 6• AN 7• SB
NEe
NEe Electronics Inc.
Description
The tJPD78310 and tJPD78312 microcomputers are
designed for use in process control. They perform all
the usual process control functions and are particularly
well-suited for driving dc motors in servo loops and
stepping motors. The processor includes on-chip
memory, timers, input/output registers, and a powerful
interrupt handling facility. The tJPD78310/312 is
constructed of high-speed CMOS circuitry and
operates from a +5 V power supply.
The input frequency (maximum 12 MHz) is derived
from an external crystal or an external oscillator. The
internal processor clock is two-phase, and thus
machine states are executed at a rate of 6 MHz. The
shortest instructions require three states, making the
minimum time 500 ns. The CPU contains a three-byte
instruction prefetch queue which allows a subsequent
instruction to be fetched during execution of an
instruction that does not reference memory.
pPD78310/312
8-BIT, SINGLE-CHIP
CMOS MICROCOMPUTERS,
REAL-TIME CONTROL ORIENTED
D Macro service facility for interrupts
- Gives the effect of 8 DMA channels
o Bidirectional serial port
- Either UART or interface mode
- Dedicated baud rate generator
o Watchdog timer
D Refresh output for pseudostatic RAM
o Programmable HALT and STOP modes
D One-byte call instruction
o On-chip clock generator
D CMOS silicon gate technology
o +5 V power supply
Pin Configurations
64-Pin DIP and QUIP
VDD
P47/AD7
P4s/ADs
Program memory is 8K bytes of mask-programmable
ROM (tJPD78312 only), and data memory is 256 bytes
of static RAM. ThetJPD78310 is the ROM-less version.
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P4o/ADo
Note: pPD78P312, available in 3086, is a prototyping chip for
pPD78312. It has an on-chip 8K EPROM instead of a
mask ROM.
ALE
VIR
Features
D Complete single-chip microcomputer
- 16-bit ALU
- 8K ROM (tJPD78312 only)
- 256 bytes RAM
- 1-bit and 8-bit logic
D Instruction prefetch queue
D 16-bit unsigned multiply and divide
D String instructions
D Memory expansion
D - 808SA bus-compatible
- Total64K address space
D Large I/O capacity
- Up to 32 I/O port lines
D Extensive timer/counter system
- Two 16-bit up/down counters
- Two 16-bit timers
- Free running counter with two 16-bit capture
registers
- Pulse-width modulated outputs
- Timebase counter
D Four-channel 8-bit A/D converter
D Two 4-bit real-time output ports
D Two nonmaskable interrupts
D Eight hardware priority interrupt levels
P1s
PS7/A1S
P17
PSs/A14
P20INMI
PSs/A13
PS4/A12
P22/INTE1
PS3/A11
P23/INTE2
PS2/A10
PS1/Ag
P2S/RxD
PSo/As
P26/SCK
P37/CLR1/T01
P27/CTS
P3S/PWM1
P30/CIO
P31/CTRLO
P34/PWMO
AVss
AVREF
P33/CTRL1
AN3
X1
AN2
AN1
Vss _ _ _ _ _ _-r- ANo
83-003822A
4-175
NEe
pPD78310/312
Pin Identification (cont)
Pin Configurations (cont)
Symbol
54-Pin Mlnltlat
I/O port 2/Clear to send input
co
U'>
U'>
51
Up/down counter 1 input
P41/AD1
P40/ADo
Up/down counter 1 control input
ALE
ViR
48
EA
X1
External crystal/External clock input
X2
External crystal
Vss
P57/A1S
P1S
42
pPD78310/312
10
P54/A12
P53/A11
P21/1NTEO
13
39
16
36
PSO/AS
P24/TxD
P36/CLRO/TOO
P3s/PWM1
P34/PWMO
33
N
45
P2s/RxD
Refresh output
P30/C10
N
RO
P22/1NTE1
RFSH
Up/down counter 0 control input
'"
o
P17
Function
P37/CLR1/T01
I/O port 3/Counter 1 clear input/Timer 1 output
P50-P57/ As-A15
I/O port 5/High address byte output
EA
External access control input
RESET
External reset input
RD
Read strobe output
WR
Write strobe output
ALE
Address latch enable output
P40-P47/ ADo-AD7
I/O port 4/External address/Data bus
Voo
Power supply
pPD78310CW
pPD78312CW
54-pin plastic shrink DIP
12MHz
Pin Functions
pPD78310G-36
pPD78312G-36
pPD78P312G-36
54-pin plastic QUIP
12 MHz
POO-P07 [Port 0]
pPD7831 OG-1 B
pPD78312G-1B
54-pin plastic miniflat
12 MHz
Port 0 consists of 8 bits, individually programmable for
input/output or two 4-bit real-time (timer controlled)
output ports.
pPD78310L
pPD78312L
68-pin PLCC
12 MHz
P10-P17 [Port 1]
Port 1 consists of 8 bits, individually programmable for
input/output.
Pin Identification
Symbol
POO-PO?
Function
I/O port 0
P10-P1?
I/O port 1
P20/NMI
Nonmaskable interrupt input
P20/NMI
Port P20 is dedicated to NMI, the nonmaskable external
interrupt request.
P21-P23/1 NTEO-I NTE2
1.1 ....... 1,,.. .... 1.... ;n+ ........ lln+ innlltt"
IVIQ.;:)r\QUIt;i I l l l \ l I I U P " IIIPUh,1
I/O port 2/Serial transmit output
P25/RxD
I/O port 2/Serial transmit output
I/O port 2/Serial clock output
4-176
Ports P21-P23 are dedicated to INTEU, IN I t::l, and
INTE2, the maskable external interrupt requests.
NEe
pPD78310/312
P24/TxD
ANo-AN3
P24 is an I/O port bit or the transmitted serial data
output.
ANo-AN3 are the four program selectable input
channels for the A/D converter.
P2s/RxD
AVREF
P2s is an I/O port bit or the received serial data input.
AVREF is the reference voltage input for the A/D
converter.
P2s1SCK
P26 is an I/O port bit or the serial shift clock output.
AVss
AVss is the analog ground pin.
P27/CTS
P27 is an I/O port bit or clear-to-send input (external
serial transmission control) in the asynchronous
communication mode. In theseriall/O interface mode,
it becomes the serial receive clock I/O pin.1
P34/PWMO
P34 is an I/O port bit or the pulse-width modulated
output O.
P3s/PWM1
RFSH
RFSH is the refresh pulse output to be used for external
pseudostatic DRAM.
P3s is an I/O port bit or the pulse-width modulated
output 1.
P36/CLRO/TOO
P30/CIO
Port P30 is dedicated to Cia, the external count input
for up/down counter o.
P36 is an I/O port bit, or the clear input for up/down
counter 0, or the timer a flip-flop output.
P37/CLR1/T01
P31/CTRLO
Port P31 is dedicated to CTRLO, the external control
input for up/down counter O.
P37 is an I/O port bit, or the clear input for up/down
counter 1, or the timer 1 flip-flop output.
PSo-PS7/As-A15 [Port 5]
P32/CI1
Port P32 is dedicated to C11, the external count input
for up/down counter 1.
P33/CTRL1
Port P33 is dedicated to CTRL 1, the external control
input for up/down counter 1.
X1
X1 is the external oscillator input or one of the
connections for an external crystal. It is used to
generate the system clock. The system clock frequency
is half the input frequency.
X2
X2 is the second connection for an external crystal.
Vss
Vss is the power supply return, normally ground.
Port 5 consists of 8 bits, individually programmable for
input or output, or the high-order address bits for
external memory. Under control of the memory mask
register, bits P50-P53 are used for 4K memory expansion, bits P50-P5s are used for 16K memory expansion, or bits P50-P57 are used for 56K memory
expansion.
EA [External Access]
On IIPD78312, a Iowan EA enables use of external
memory in place of on-chip ROM. The EA pin must be
Iowan IIPD7831 O.
This pin is used for the external reset input. A low level
sets all registers to their specified reset values.
RD
RD is the read strobe output. It is to be used by external
memory (or data registers) to place data on the I/O bus
during a read operation.
4-177
.,
IIIi.i
t\fEC
pPD78310/312
WR
P40·P47/ADo·AD7 [Port 4]
WR is the write strobe output. It is to be used by
external memory (or data registers) to latch data from
the I/O bus during a write operation.
Port 4 consists of 8 bits, programmable as a unit for
input or output, or as the multiplexed address/data bus
if external memory or external interface circuitry is
used. The port is controlled by the memory mapping
register.
ALE
ALE is the address latch enable. It is to be used by
external circuitry to latch the low-order 8 address bits
during the first part of a read or write cycle.
Voo
VDD
is the positive power supply input.
Block Diagram
16
P20INMI
P21/1NTEO
P22/1NTE1
ALE
P23/1NTE2
AD
WR
P24/TxD
RFSH
P2S/RxD
EA
P2s/SCK
P27/CTS
P30/CIO
P31/CTRLO
P32/CI1
P33/CTRL1
P3s/CLRO/TOO
X1
P37/CLR1/T01
X2
RESET
P21/1NTEO
Voo
Vss
P3S/PWM1
AVREF
ANo-AN3
AVss
P3S/CLRO/TOO P37 /CLR1/T01
49-001302C
4-178
NEe
pPD78310/312
Functional Description
General Registers
On-chip features designed to facilitate process control
include two 16-bit timers, two 16-bit up/down counters,
two pulse-width modulated outputs, a free-running
counter with two capture registers, two 4-bit real-time
(timer controlled) output ports, an 8-bit A/D converter
with 4 input channels, a timebase counter to generate
widely spaced interrupts, and a watchdog timer to
guard against infinite program loops.
The CPU has 16 8-bit registers (figure 2) that can also
be used in pairs to function as 16-bit registers. A
complete set of 16 general registers is mapped into
each of 8 program-selectable register banks, stored in
RAM. Three bits in the PSW specify which of the
register banks is active at any given time. Each register
bank has two program-selectable accumulators.
In addition there is a serial 110 port which can be used
in either an interface mode or an asynchronous
communication mode. HALT and STOP modes are
provided to conserve power at times when the action of
the CPU is not required.
Figure 1.
Memory Map
FFFFH
-
FEOOH I- - -
-
-
-
-
- FFFFH7T"""-----,
- - f- """'
Special Function
Registers
,
"
,
,
All I/O, timer, and control registers are defined as
special function registers and assigned addresses in
the top 256 bytes of memory. The special function
registers may be operated on directly by many of the
arithmetic, logic, and move instructions of the CPU.
Table 2 at the end of the Functional Description
describes the registers.
FFOOHr- _ _ T _ _ _
Register I
Storage I Internal
,
Awiiiib"ie' RAM
'~~H Storage:
FE80H
External
Memory
Area
IOFFF::":'Hr-------,
/
/
/
The pPD78310/312 features 1-byte addressing of the
special function registers and 1-byte addressing ofthe
internal RAM. There are nine modes of addressing
main memory, including autoincrement, autodecrement, indexing, and double indexing. There are 8- and
16-bit immediate operands.
Fixed Area
/
Addressing
I
/
0800H
______ _
/
I
lFFFH - - - - - Internal
/
ROM
I
/
--t-.J
OFFFH - - - -
007FH
- - --- --Cali
0040H _ _
_Table
_ _Area
_ _
OOOOH ' - -_ _- L _ _ _ _ _ _ _ _OOOOH
Vector Table Area
49·001304A
External Memory
External memory (figure 1) is supported by 110 port 4,
an 8-bit multiplexed address/data bus. The memory
mapping register controls the size of external memory
as well as the number of additional wait states. Highorder address bits are taken from I/O port 5 as
required. No bits are required for 256 bytes of external
memory; bits P50-P53 are used for 4K bytes, P50-P55
for 16K bytes, and P50-P57 for 56K bytes. Any remaining
port 5 bits are available for I/O.
Figure 2.
Register Designation and Storage
RSS=1
FE80H
Register Bank
;'
7
I
r-_-~-~_-.J.."""I_-~-O_""
/
/
I
I
I
I
I
I
/
.------jl
I
I
=0
AX [RPOI
RPO
I
I
I
I
I
I
Refresh
The pPD7831 0/312 has a refresh signal for use with the
pseudostatic RAM. The refresh cycle can be set to one
of four intervals ranging from 2.67 to 21.3 ps. The
refresh is timed to follow a read or write operation so
that the CPU does not have to wait.
I
RSS
__A_[~~_..L_~~~_
BC [RP1]
RPI
~_[~~..L~l~~]
AX [RP2]
__ ~: __ ..L __~ __
RP2
R7
RS
I _____ _
_ _ _ _ _ _ ...L..
~il~?ll~lR!l
BC [RP3]
RP3
VPH [Rgi ..L
I _
VPL
______
_ _[RBI
__ _
VP [RP4]
UPH [Rll)
I
UPL [RIO)
-------'------UP [RPS)
_~l~:U__ ~~~~
DE [RPS)
H [R1S]
FEFFH
I
L [R14)
------'------HL [RP7)
83-003824A
4-179
NEe
pPD78310/312
Program Status Word
Figure 3.
Pulse-Width Modulated Output
r------------------------------,
Following is the program status word format.
I
15
8
o I RB2 I RB1 I RBo I
0
o
IE
7
S
I
I
I
o
0
z
RB2- RB o
IE
S
Z
RSS
AC
UF
P/V
SUB
Cy
I RSS I AC
UF
P/V
ISUB I Cy
Active register bank number
Interrupt enable
Sign (1 if last result was negative)
Zero (1 if last result was zero)
Register set select
Auxiliary carry (carry out of 3 bit)
User flag
Parity or arithmetic overflow
Subtract (1 if last operation was
subtract)
Carry
Input/Output
All ports may be used for either latched output or highimpedance input. All ports except port 4 are bitprogrammable for input or output. Port 0 is used for
real-time or normal I/O. Port 1 is used for normal I/O.
The low nibble of ports 2 and 3 is always used for
control and the high nibble for control or normal 110.
Port 4 is used for the external address/data bus or
byte-programmable I/O. Port 5 is used for the high bits
of the external address or for normal I/O.
Real-Time Output Port
The real-time output port shares pins with 110 port O.
The high and low nibbles are treated separately or
together. Data is transferred from a buffer to the port
latches on either a timer or software command.
Serial Port
The serial port can operate in UART or interface mode
with the baud rate and byte format under program
control. The serial port also includes a dedicated baud
rate generator.
Pulse-Width Modulated Outputs
The two independent pulse-width modulated outputs
are controlled by two 16-bit modulus registers and
counters. There are four programmable repetition
rates ranging from 91.6 Hz to 23.4 kHz. Figure 3 shows
one of these outputs.
4-180
I
49·001303A
Timers
The JlPD7831 0/312 has two 16'-bit ti mers. The inputs to
these timers may be the. internal clock divided by 6 or
by 128. Each timer has an associated modulus register
to store the timer count. The timer counts down to zero,
sets a flag, reloads from the modulus register, and then
counts down again. The timer flags can be used under
program control to generate interrupt requests and/or
a square-wave output. TMO also functions optionally
as two one-shot timers.
Figure 4 is a diagram of the interval timers.
There is a free-running counterthat counts the internal
clock divided by 4 or by 16. The counter has two 16-bit
capture registers. Capture is triggerd by an external
interrupt request or by the up/down counter clock.
The timebase counter generates a signal at one of four
intervals ranging from 170 JlS to 175 ms. The signal can
be used to generate an interrupt request and/or an
up/down counter capture.
.
Up/Down Counters
The JlPD78310/312 has two 16-bit up/down counters,
each of which has two capture/compare registers.
There are three modes of operation: compare and
interrupt, capture on external command, and capture
on timebase counter command. There are five sources
of counts: the internal clock divided by 3, the external
clock, external independent up and down inputs,
external clock with direction control, and external clock
with automatic up/down discrimination. Figure 5 shows
an up/down counter.
NEe
Figure 4.
pPD78310/312
Timer Block Diagram
,-----------------------------,
SCLK/6
I
I
I
I
I
SCLK/128
I
I
I
I
I
I
I
I
I
I
I
I
I
I
j
I
I
I
I
MOO (16)
I
I
I
I
~
:::
3-
SCLK/128
L ________ - -
6
I
I
~
output:
-n------------
>00
----~
Internal Bus
q
49-001305C
Standby Modes
Watchdog Timer
HALT and STOP modes conserve power when CPU
action is not required. In HALT mode, the CPU stops
and the clock continues to run. Maskable interrupts
can restart the CPU.
The watchdog timer protects agains inadvertent
program loops. A nonmaskable interrupt occurs if the
timer is not reset before a timeout occurs. There are
four program-selectable intervals ranging from -5.5
ms to 349.3 ms. The watchdog timer can be disabled by
software. The watchdog timer mode register controls
the watchdog timer and is a protected location written
to by a special instruction.
In STOP mode, the CPU and clock are both stopped. A
RESET pulse or the nonmaskable external interrupt is
required to restart them.
There is also the option of slowing the system clock by
a factor of four. The standby control register controls
the standby modes and is a protected location written
to only by a special instruction.
AID Converter
The AID converter has four input channels and can
operate in either scan or select mode. The AID
converter performs 8-bit successive approximation
conversions, has a 30-Jls conversion time, and is
triggered either internally or externally. The AID
converter includes an on-Chip sample and hold amplifier.
4-181
NEe
JlPD78310/312
Figure 5.
Up/Down Counter Block Diagram
~f-~-----------------------l
~~9
~O
r - - - - -7ro;- - - - - - - - - ---,- - - -
I
I
I
I
~=
I
I
--1
I
I
Interrupt
Request
I
I
I
I
CIO
I
I
CTRLO
I
I
I
I
Interrupt
Request
CLRO
I
I
I
L _______ _
I
I
I
I
I
I
------Dn-------~
&
Internal Bus
V
49-0013066
Interrupts
Macro Service
There are two nonmaskable interrupt sources: the
external nonmaskable interrupt and the watchdog
timer. Their relative priorities are software selectable.
The macro service controller can be programmed to
perform word or byte transfers. It can transfer data
from a special function register to memory or from
memory to a special function register. Transfer events
are triggered by interrupt requests and take place
without software intervention.
There are eight hardware priority interrupt levels, level
ohaving the highest priority and level 7 the lowest. The
fifteen maskable interrupt sources (table 1) are divided
into five groups, and each group can, under program
control, be assigned to anyone of the priority levels.
I nterrupts may be serviced by routines entered either
by vectoring or by context switching. Context switching
automatically saves a" the general registers, the
program status word, and the program counter. Figure
6 illustrates the mechanism of context switching.
Fina"y, there is an optional macro service function
that transfers data between anyone special function
register and memory without program intervention.
4-182
There are eight macro service channels; channel
control information is stored in RAM. This information
(figure 7) consists of a 16-bit memory address
(optiona"y incremented at each transfer), an 8-bit
special function register designator, and an 8-bit
transfer counter (decremented at each transfer.) When
the count equals 0, a context switch or vectored
interrupt occurs.
NEe
Table 1.
pPD78310/312
Interrupt Sources and Vector Addresses
Default Priority
Source
Nonmaskable interrupts
Maskable interrupts
Macro Service
No
No
No
003EH
0002H
OOOAH
0
1
2
3
CRFOO
CRF01
CRF10
CRF11
Up/down counter
Up/down counter
Up/down counter
Up/down counter
Yes
No
Yes
No
001AH
001CH
001EH
0020H
4
6
EXIFO
EXIF1
EXIF2
External interrupt 0
External interrupt 1
External interrupt 2
Yes
Yes
Yes
0004H
0006H
0008H
7
8
9
TIMFO
TIMF1
TlMF2
Timer flag 0
Timer flag 1
Timer flag 2
Yes
Yes
Yes
OOOEH
0010H
0012H
10
11
12
SEF
SRF
STF
Serial port error
Serial port receive buffer
Serial port transmit buffer
No
Yes
Yes
0022H
0024H
0026H
13
14
ADF
TBF
A/D converter doneftag
Timebase counter flag
Yes
No
0028H
OOOCH
RESET
External reset line
Figure 7.
Hardware Context Switching
OOOOH
pPD78312 Macro Service Pointer Addresses
New Active
Register Bank
Current Active
Register Bank
15
8/7
FEEOH
MSP4
AX
AX
BC
FEE3H
SFRP4
FEE7H
SFRP5
FEEBH
SFRP6
FEEFH
SFRP7
FEF3H
SFRPO
FEF7H
SFRP1
FEFBH
SFRP2
FEFFH
SFRP3
BC
Ssve
RP2
~
RP3
VP
UP
UP
I
I
I
MSC4
FEE2H
MSC5
FEE6H
MSC6
FEEAH
FEE4H
MSP5
PC
SsveArea
PSW
SsveArea
VP
Register
Bank 1
DE
DE
HL
HL
I
FEECH
Channel 7
MSC7
Register
Bank 0
Load
Program
L
Status Word I
I
FEF4H
FEF6H
MSC2
FEFAH
MSC3
FEFEH
FEF8H
FEFCH
MSP3
49-001307A
I
Channel 0
FEF2H
MSC1
MSP2
I
FEEEH
FEFOH
MSCO
MSP1
I
Channel 5
Channel 6
MSPO
I
Channel 4
FEE8H
MSP6
MSP7
Program
Counter
Vector
Break instruction
External nonmaskable interrupt
Watchdog timer
5
Figure 6.
Interrupt Service
BRK
NMI
WDT
Channel 1
Channel 2
Channel 3
Note:
[11 The macrO service pointers share storage with register banks 0 and 1_
[21 MSP = Memory address pointer
SFRP ~ Special function register pointer
MSC -, Transfer counter
4-183
NEe
pPD78310/312
Table 2.
Special Function Registers
Function
Address
Mnemonic
Read/
Write
16-Bit
Transfer
Reset
State
FFOOH
I/O port 0
PO
R/W
No
Undefined
FF01H
I/O port 1
P1
R/W
No
Undefined
FF02H
I/O
2
P2
R/W
No (Note 1)
Undefined
FF03H
I/O port 3
P3
R/W
No (Note 1)
Undefined
FF04H
I/O port 4
P4
R/W
No
Undefined
FF05H
I/O port 5
P5
R/W
No
Undefined
FF08H
FF09H
Capture/compare register 00
CROOl
CROOH
R/W
Yes
Undefined
FFOAH
FFOBH
Capture/compare register 01
CR01l
CR01H
R/W
Yes
Undefined
FFOCH
FFODH
Capture/compare register 10
CR10l
CR10H
R/W
Yes
Undefined
FFOEH
FFOFH
Capture/compare register 11
CR11l
CR11H
R/W
Yes
Undefined
FF10H
FF11H
Capture register 0 (from FRC)
CPTOl
CPTOH
R/W
Yes
Undefined
FF12H
FF13H
Capture register 1 (from FRC)
CPT1l
CPT1H
R/W
Yes
Undefined
FF14H
FF15H
PWM register 0 (duration)
PWMOl
PWMOH
R/W
Yes
Undefined
FF16H
FF17H
PWM register 1 (duration)
PWM1l
PWM1H
R/W
Yes
Undefined
FF1CH
FF1DH
Presettable up/down counter 0
UDCOl
UDCOH
R/W
Yes
Undefined
FF1EH
FF1FH
Presettable up/down counter 1
UDC1l
UDC1H
R/W
Yes
Undefined
FFH
p~rt
FF20H
Port 0 mode register
PMO
R/W
No
FF21H
Port 1 mode register
PM1
R/W
No
FFH
FF22H
Port 2 mode register
PM2
R/W
No
FFH
FF23H
Port 3 mode register
PM3
R/W
No
FFH
FF25H
Port 5 mode register
PM5
R/W
No
FFH
FF32H
Port 2 mode control register
PMC2
R/W
No
OFH
Port 3 mode control register
PMC3
R/W
No
OFH
Real-time output port control register
RTPC
R/W
No
08H
FF33H
FF38H
4-184
NEe
Table 2.
pPD78310/312
Special Function Registers (cont)
Address
Function
Mnemonic
Read/
Write
16-Bit
Transfer
Reset
State
R/W
R/W
No
No
Undefined
Undefined
30H
FF3AH
FF3BH
Port 0 buffer register (Note 2)
FF40H
Memory mapping register
MM
R/W
No
FF41H
Refresh mode register
RFM
R/W
No
10H
FF42H
Watchdog timer mode register
WDM
R/W
No
OOH
FF44H
Standby control register
STBC
R/W
No
2nH (Note 3)
FF46H
Timebase mode register
TMB
R/W
No
OOH
FF48H
Interrupt mode register
INTM
R/W
No
OOH
POL
POH
FF4AH
In-service priority register
ISPR
R/W
No
OOH
FF4EH
CPU control word
CCW
R/W
No
OOH
FF50H
Serial communication mode register
SCM
R/W
No
OOH
FF52H
Serial communication control register
SCC
R/W
No
OOH
FF53H
Baud rate generator
BRG
R/W
No
OOH
FF56H
Serial communication receive buffer
RXB
R
No
Undefined
FF57H
Serial communication transmit buffer
TXB
W
No
Undefined
FF60H
Free-running counter control register
FRCC
R/W
No
OOH
FF64H
Capture mode register
CPTM
R/W
No
OOH
FF66H
PWM mode register
PWMM
R/W
No
OOH
FF68H
AID converter mode register
ADM
R/W
No
OOH
FF6AH
AID converter result register
ADCR
R
No
Undefined
FF70H
Count unit input mode register
CUlM
R/W
No
OOH
I:
FF72H
Up/down counter control register 0
UDCCO
R/W
No
OOH
FF74H
Capture/ compare control register
CRC
R/W
No
OOH
FF80H
Timer 0 control register
TMCO
R/W
No
OOH
FF82H
Timer 1 control register
TMC1
R/W
No
OOH
FF88H
FF89H
Timer 0
TMOL
TMOH
R/W
Yes
Undefined
FF8AH
FF8BH
Modulus/timer register 0
MDOL
MDOH
R/W
Yes
Undefined
FF8CH
FF8DH
Timer 1
TM1L
TM1H
R/W
Yes
Undefined
FF8EH
FF8FH
Modulus register 1
MD1L
MD1H
R/W
Yes
Undefined
FFBOHFFBFH
External area (Note 4)
4-185
NEe
pPD78310/312
Table 2. Special Function Registers (cont)
Address
Mnemonic
Function
Read/
Write
16·Blt
Transfer
Reset
State
47H
FFCOH
Interrupt controlOO
Up/down counter
CRICOO
R/W
No
FFC1H
Macro service control 00
Up/down counter
CRMSOO
R/W
No
Undefined
FFC2H
Interrupt control 01
Up/down counter
CRIC01
R/W
No
47H
FFC4H
Interrupt control 10
Up/down counter
CRIC10
R/W
No
47H
FFC5H
Macro service control 10
Up/down counter
CRMS10
R/W
No
Undefined
FFC6H
Interrupt control 11
Up/down counter
CRIC11
R/W
No
47H
47H
FFC8H
EXIFO interrupt control
External interrupt
EXICO
R/W
No
FFC9H
EXIFO macro service control
External interrupt
EXMSO
R/W
No
Undefined
FFCAH
EXIF1 interrupt control
External interrupt
EXIC1
R/W
No
47H
FFCBH
EXIF1 macro service control
External interrupt
EXMS1
R/W
No
Undefined
FFCCH
EXIF2 interrupt control
External interrupt
EXIC2
R/W
No
47H
FFCDH
EXIF2 macro service control
External interrupt
EXMS2
R/W
No
Undefined
FFCEH
TMFO interrupt control
Timer flag
TMICO
R/W
No
47H
FFCFH
TMFO macro service control
Timer flag
TMMSO
R/W
No
Undefined
FFDOH
TMF1 interrupt control
Timer flag
TMIC1
R/W
No
47H
FFD1H
TMF1 macro service control
Timer flag
TMMS1
R/W
No
Undefined
FFD2H
TMF2 interrupt control
Timer flag
TMIC2
R/W
No
47H
FFD3H
TMF2 macro service control
Timer flag
TMMS2
R/W
No
Undefined
FFDAH
Error interrupt control
Serial port
SEIC
R/W
No
47H
FFDCH
Receive interrupt control
Serial port
SRIC
R/W
No
47H
FFDDH
Receive macro service control
Serial port
SRMS
R/W
No
Undefined
FFDEH
Transmit interrupt control
Serial port
STIC
R/W
No
47H
FFDFH
Transmit macro service control
Serial port
STMS
R/W
No
Undefined
FFEOH
A/D converter interrupt control
ADIC
R/W
No
47H
FFE1H
A/D converter macro service control
ADMS
R/W
No
Undefined
FFE2H
Timebase counter interrupt control
TBIC
R/W
No
47H
FFFCH
FFFDH
Stack pointer (Note 5)
SPL
SPH
R/W
Yes
Undefined
FFFEH
FFFFH
Program status word (Note 5)
PSWL
PSWH
R/W
Yes
OOH
Note:
(1) Bits 0-3 of port 2 and port 3 are read-only.
(2) POH and POL are 4-bit buffer registers used to store data to be loaded into the high and low nibbles of the real-time output (PO).
(3) Bit 3 of the STBCis not affected by RESET (n = 0 or 8).
(4) External registers interfaced with these addresses can be accessed by special function register addressing.
(5) SP and PSW do not have real SFR addresses and can be accessed only by special instructions.
4~186
NEe
pPD78310/312
Instruction Set
Symbols in the Operand and Operation Columns
The instruction set for the pPD7831 0/312 has 8- and
16-bit arithmetic instructions including a 16 x 16-bit
unsigned multiply with a 32-bit product and a 32 by
16-bit unsigned divide with a 32-bit quotient and a
16-bit remainder. The instruction set also excutes an
8-bit and a 16-bit shift and rotate by count, 1- and 8-bit
logic, and 1-, 2-, and 3-byte call instructions. String
manipulation instructions are also included.
Symbol
There are four addressing modes for unconditional
branching. Branch instructions exist to test single bits
in the program status word, the 16-bit accumulator, the
special function registers, and internal RAM. The
instruction set also includes multiple register PUSH
and POP instructions.
Following are several tables explaining symbols,
designations, and codes in the Instruction Set. Machine
codes are omitted from the instructions but they are in
the User's Manual.
Meaning
RO-R15
r1
RO-R7
r2
C,B
rp
RPO-RP7*
rp1
RPO-RP7*
rp2
DE, HL, VP, UP
sfr
Special function register, 8 bits
sfrp
Special function register, 16 bits
post
RPO, RP1, RP2, RP3, RP4, RP5/PSW, RP6, RP7
Bits set to 1 indicate register pairs to be pushed/popped
to/from the stack
RP5 pushed/popped by PUSH/POP:
SP is stack pointer
PSW pushed/popped by PUSHU/POPU:
RP5 is stack pointer
mem
(DE), (HL), (DH), (HL+), (DE-), (HL-), (VP), (UP); register
indirect
(DE + A), (HL + A), (DE + B), (HL + B), (VP + DE),
(VP + HL); baselindex mode
(DE + byte), (HL + byte), (VP + byte), (UP + byte),
(SP + byte); base mode
Word (A), word (B), word (DE), word (HL); index mode
saddr
FF20H-FF1 FH: immediate byte addresses one byte in RAM,
or label
saddrp
FE20H-FF1 FH: immediate byte (bit 0 = 0) addresses one
word in RAM
word
16 bits of immediate data
byte
8 bits of immediate data
jdisp
8-bit two's complement displacement (immediate data)
bit
3 bits of immediate data (bit position in byte), or label
3 bits of immediate data
addr16
OOOOH-FEFFH: 16-bit immediate address (up to FFFFH in
MOV instruction)
!addr16
OOOOH-FEFFH: 16-bit absolute branch address (immediate
data)
$addr16 Relative branch address ((PC)+jdisp»
addr11
0800H-OFFFH: 0800H+ (11-bit immediate address), or label
addr5
0040H-007EH: 0040H + 2 x (5-bit immediate address), or
label
4-187
NEe
pPD78310/312
Symbols In the Operand and Operation Columns (cont)
Symbol
Meaning
Flag Indicators
Symbol
Meaning
A
A register (8-bit accumulator)
(blank)
x
X register
0
Cleared to 0
B
B register
1
Set to 1
C
C register
X
Set or cleared according to result
D
D register
P
Parity of result
E
E register
V
Arithmetic overflow
H
H register
U
Undefined
L
L register
R
Restored from saved PSW
RO-R15
Register 0-15
AX
Register pair AX (16-bit accumulator)
BC
Register pair BC
DE
Register pair DE
HL
Register pair HL
RPO-RP7
Register pair 0-7
PC
Program counter
SP
Stack pointer
UP
User stack pointer (RP5)
No change
Execution Times of Memory Reference Instructions:
Number of Processor States
Memory Reference Mode
XCH
AC
Auxiliary carry flag
Z
Zero flag
CMP
Subtract flag
TPF
Table position flag
RBS
Register bank select flag
RSS
Register set select flag
IE
Interrupt enable flag
EOS
End of software interrupt flag
STBC
Standby control register
WDM
Watchdog timer mode register
( )
Contents of the location whose address is within ( ); (+)
and (-) indicate that the address is incremented after or
decremented before it is used.
(( ))
Contents of the memory location defined by the contents
of the location defined by the quantity within the (( )).
XXH
Hexadecimal number
XH,XL
High-order 8 bits and low-order 8 bits of X
rp and rp1 describe the same registers, but generate different
machine code.
4-188
6
7
8
8
8
A,mem
6
7
7
7
mem,A
7
8
8
8
A,mem
--mem, A
6
7
7
7
A,mem
ADD, ADDC,
SUB, SUBC,
AND,OR,XOR
SUB
6
mem,A
Program status word
Parity I overflow flag
Index
6
mem,A
Carry flag
Sign flag
Base
5
A,mem
MOV
PSW
P/V
Base
Index
Instruction
CY
S
Register
Indirect
Memory Addressing Modes
mod 1 0110
1 0111
mem
Register
Indirect
Base
Index
0 0 0
(DE+)*
(DE+A)
0 0
0
0
0 0110
Base
(DE + byte)
(HL+)*
(HL+A)
(SP + byte)
word (A)
(DE+ B)
(HL + byte)
word (HL)
word (B)
(HL-)*
(HL+B)
(UP + byte)
(DE)*
(VP+ DE)
(VP + byte)
0 1
(HL)*
(VP + HL)
0
Index
word (DE)
(DE-)*
0 0
0 1
0 1010
(VP)
(UP)
*1-byte instructions: defined by special opcode and mem only.
NEe
pPD78310/312
General Register Designations
r, r1
R3
R2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
r2
C
reg
0
1
C
B
Rl
RO
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RO
R1
R2
R3
R4
R5
R6
R7
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
R8
R9
R10
R11
R12
R13
R14
R15
rp
reg
I
rl
~
P2
PI
PO
reg-pair
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RPO
RP1
RP2
RP3
RP4
RP5
RP6
RP7
02
01
00
reg-pair
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RPO
RP4
RP1
RP5
RP2
RP6
RP3
RP7
rp1
rp2
81
80
reg-pair
0
0
1
1
0
1
0
1
VP
UP
E
DE
HL
4-189
t-{EC
pPD78310/312
Instruction Set
Flags
Mnemonic
Operand
Operation
MOV
r1, #byte
r1 -
saddr, #byte
(saddr) -
sfr**, #byte
sfr -
r, r1
r-r1
3
2
A, r1
A-r1
3
1
A,saddr
A-
3
2
saddr, A
3
2
XCH
byte
byte
byte
(saddr)
States
Bytes
3
2
3
3
3
3
(saddr) -
A
saddr, saddr
(saddr) -
(saddr)
4
3
A, sfr
A-sfr
3
2
sfr, A
sfr-A
3
2
A,mem*
A-(mem)
5
A,mem
A-(mem)
5-6
mem,A*
(mem) -A
5
1
mem,A
(mem)-A
5-6
2-4
5
2
4
2
4
4
A, (saddrp)
A-
(saddrp), A
((saddrp)) -
A, addr16
A-
addr16, A
(addr16) -
PSWL, #byte
((saddrp))
A
(addr16)
3
4
PSWL -
byte
3
3
PSWH, #byte
PSWH -
byte
3
3
PSWL, A
PSWL -A
3
2
PSWH, A
PSWH -A
3
2
A, PSWL
A- PSWL
3
2
A, PSWH
A-PSWH
3
2
A,r1
A+-. r1
4
r,r1
r-r1
A,mem
A+-. (mem)
A, saddr
A +-. (saddr)
4
2
A,sfr
A-sfr
7
3
A, (saddrp)
A+-. ((saddrp))
6
2
saddr, saddr
(saddr) - - (saddr)
8
3
* One-byte move instruction.
4-190
Z
AC
P/V
SUB
CY
X
X
X
X
X
X
X
X
X
X
X
X
2-4
A
4
2
7-8
2-4
** A special instruction is used to write to STBC and WDM (see below).
S
NEe
pPD78310/312
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
MOVW
rp1, #word
rp1 -
XCHW
ADD
AD DC
word
saddrp, #word
(saddrp) -
sfrp, #word
sfrp -
word
word
States
Bytes
3
3
4
4
3
4
rp, rp1
rp -
AX, saddrp
AX -
saddrp, AX
(saddrp) -
AX
3
2
saddrp, saddrp
(saddrp) -
(saddrp)
4
3
rp1
(saddrp)
3
2
3
2
AX, sfrp
AX -
sfrp
3
2
sfrp, AX
sfrp -
AX
3
2
AX, saddrp
AX -
AX, sfrp
AX-sfrp
saddrp, saddrp
(saddrp) -
rp rp1
rp-rp1
A, #byte
A, CY -
saddr, #byte
(saddr), CY -
(saddrp)
(saddrp)
4
2
7
3
8
3
(saddr) + byte
sfr, #byte
sfr, CY -
r, r1
r,CY-r+r1
A, saddr
A, CY -
A + (saddr)
A, sfr
A, CY -
A + sfr
sfr + byte
(saddr), CY -
A,mem
A, CY -
P/V
SUB
CY
2
2
X
X
X
V
0
X
3
X
X
X
V
0
X
7
4
X
X
X
V
0
X
3
2
X
X
X
V
0
X
X
X
X
V
0
X
3
X
X
X
V
0
X
A + byte
saddr, saddr
AC
S
(saddr) + (saddr)
A + (mem)
4
6
6
3
X
X
X
V
0
X
6-7
2-4
X
X
X
V
0
X
7-8
2-4
X
X
X
V
0
X
3
2
X
X
X
V
0
X
3
X
X
X
V
0
X
mem,A
(mem), CY -
A, #byte
A, CY -
saddr, #byte
(saddr), CY (saddr) + byte + CY
4
sfr, #byte
sfr, CY -
7
4
X
X
X
V
0
X
r,r1
r, CY -
r + r1 + CY
3
2
X
X
X
V
0
X
A, saddr
A, CY -
A + (saddr) + CY
3
2
X
X
X
V
0
X
A, sfr
A, CY -
A + sfr + CY
3
X
X
X
V
0
X
saddr, saddr
(saddr), CY (saddr) + (saddr) + CY
3
X
X
X
V
0
X
A,mem
A, CY -
6-7
2-4
X
X
X
V
0
X
mem,A
(mem), CY -
7-8
2-4
X
X
X
V
0
X
(mem) + A
A + byte + CY
sfr + byte + CY
A + (mem) + CY
(mem) + A + CY
4-191
IJ
NEe
pPD78310/312
Instruction Set (cont)
Flags
States
Bytes
A, CY +- A - byte
3
2
s
x
saddr, #byte
(saddr), CY +- (saddr) - byte
4
3
x
sfr, #byte
sfr, CY +- sfr - byte
7
4
r, r1
r, CY +- r - r1
3
2
A,saddr
A, CY +- A - (saddr)
3
2
A,sfr
A, CY +- A - sfr
6
3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Mnemonic
Operand
Operation
SUB
A, #byte
SUBC
AND
OR
saddr, saddr
(saddr), CY +- (saddr) - (saddr)
6
3
A,mem
A, CY +- A - (mem)
6-7
2-4
mem,A
(mem), CY +- (mem) - A
7-8
2-4
A, #byte
A, CY +- A - byte - CY
3
2
saddr, #byte
(saddr), CY +(saddr) - byte - CY
4
3
sfr, #byte
sfr, CY +- sfr - byte - CY
7
4
r, r1
r, CY +- r - r1 - CY
3
A,saddr
A, CY +- A - (saddr) - CY
3
2
A,sfr
A, CY +- A - sfr - CY
6
3
saddr, saddr
(saddr), CY +(saddr) - (saddr) - CY
6
3
A,mem
A, CY +- A - (mem) - CY
6-7
2-4
mem,A
(mem), CY +- (mem) - A - CY
7-8
2-4
A, #byte
A +- A A byte
3
2
saddr, #byte
(saddr) +- (saddr) A byte
4
3
sfr, #byte
sfr +- sfr A byte
7
4
r, r1
r +- 'r A r1
3
2
A,saddr
A +- A A (saddr)
3
2
A,sfr
A-
6
3
saddr, saddr
(saddr) +- (saddr) A (saddr)
6
3
A,mem
A+- AA (mem)
6-7
2-4
mem,A
(mem) +- (mem) A A
7-8
2-4
A, #byte
A +- A V byte
3
2
saddr, #byte
(saddr) +- (saddr) V byte
4
3
sfr, #byte
sfr +- sfr V byte
7
4
r, r1
r +- r V r1
3
2
A,saddr
A +- A V (saddr)
3
2
A,sfr
A +- A V sfr
saddr, saddr
(saddr) +- (saddr) V (saddr)
A,mem
A +- A V (mem)
mem,A
4-192
AAsfr
(mem) +- (mem) V A
6
3
6
3
6-7
2-4
7-8
2-4
x
x
x
x
x
x
x
x
x
x
AC
P/V
x
x
x
V
x
x
x
SUB
CY
V
x
x
V
x
V
x
V
V
x
x
x
x
x
x
x
V
x
V
x
V
x
x
x
x
x
x
x
x
x
x
x
x
x
V
x
V
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
V
U
p
u
p
u
u
u
u
u
u
u
p
V
V
V
x
V
x
x
V
V
p
p
p
p
p
p
U
p
u
p
U
p
U
p
U
p
U
p
U
p
U
p
u
p
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
x
x
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
NEe
pPD78310/312
Instruction Set (cont)
Flags
States
Bytes
s
z
AC
P/V
SUB
CV
A --V- byte
3
2
x
4
3
x
sfr, #byte
sfr -
7
4
x
o
o
o
0
(saddr) -
x
x
x
u
u
u
u
u
u
u
u
u
P
saddr, #byte
x
x
x
Mnemonic
Operand
Operation
XOR
A, #byte
CMP
ADDW
SUBW
sfr-V- byte
r,r1
r-
r-V- r1
3
2
A, saddr
A-
A-V- (saddr)
3
2
A-V- sfr
6
3
6
3
x
x
x
x
6-7
2-4
x
7-8
2-4
x
x
x
x
A, sfr
A-
saddr, saddr
(saddr) -
A,mem
A-
mem, A
(mem) -
A, #byte
A - byte
3
2
x
x
saddr, #byte
(saddr) - byte
4
3
x
x
(saddr)-V- (saddr)
A-V- (mem)
(mem)-V- A
x
x
x
x
x
x
x
x
x
sfr, #byte
sfr - byte
7
4
r, r1
r - r1
3
2
A, saddr
A - (saddr)
3
2
A, sfr
A - sfr
6
3
x
x
x
x
x
saddr, saddr
(saddr) - (saddr)
6
3
x
x
A, mem
A - (mem)
6-7
2-4
x
6-7
2-4
x
x
x
4
3
X
X
5
4
X
X
u
u
mem,A
(mem) - A
AX, #word
AX, CY -
saddrp, #word
(saddrp), CY -
sfrp, #word
sfrp, CY -
rp, rp1
rp, CY -
AX, saddrp
AX + word
(saddrp)
+ word
x
x
x
sfrp + word
8
5
X
X
U
4
2
X
X
U
AX, CY -
+ rp1
AX + (saddrp)
4
2
X
X
U
AX, sfrp
AX, CY -
AX + sfrp
7
3
X
X
U
saddrp, saddrp
(saddrp), CY (saddrp) + (saddrp)
6
3
X
X
u
AX, #word
AX, CY -
4
3
X
X
U
5
4
X
X
saddrp, #word
CMPW
(saddr)-V- byte
rp
AX - word
(saddrp), CY -
(saddrp) - word
P
P
P
P
P
P
P
P
o
o
o
o
o
o
x
x
v
v
v
x
x
x
v
v
v
v
v
v
v
v
v
v
v
v
v
o
o
o
o
o
o
o
o
x
x
x
x
o
o
o
o
o
o
o
X
X
X
X
X
X
X
X
U
v
v
U
v
X
U
X
X
sfrp, #word
sfrp, CY -
8
5
X
X
rp, rp1
rp, CY -
rp - rp1
4
2
X
X
AX, saddrp
AX, CY -
AX - (saddrp)
4
2
X
X
U
v
v
AX, sfrp
AX, CY -
AX - sfrp
7
3
X
x
U
v
x
saddrp, saddrp
(saddrp), CY (saddrp) - (saddrp)
6
3
X
X
U
v
X
X
sfrp - word
AX, #word
AX - word
4
3
X
X
U
v
saddrp, #word
(saddrp) - word
5
4
X
X
U
sfrp, #word
sfrp - word
8
5
X
X
U
v
v
v
v
v
v
rp, rp1
rp - rp1
4
2
X
X
U
AX, saddrp
AX - (saddrp)
4
2
X
X
U
AX, sfrp
AX - sfrp
7
3
X
X
saddrp, saddrp
(saddrp) - (saddrp)
6
3
X
X
u
u
X
X
x
X
X
X
X
4-193
tttlEC
pPD78310/312
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
States
Bytes
MULU
r1
AX-Ax r1
18
DlVU
2
r1
AX (Quotient). r1 (Remainder)
-AX+r1
18
2
MULUW
rp1
AX (High Order 16 Bits).
rp1 (Low Order 16 Bits).
-AX x rp1
27
2
DlVUX
rp1
AXDE (Quotient). rp1 (Remainder)
-AXDE+ rp1
50
2
INC
DEC
INCW
S
Z
AC
P/V
SUB
r1
r1-r1 +1
3
1
X
X
X
V
0
saddr
(saddr) -
4
2
X
X
X
V
0
r1
r1-r1-1
3
1
X
X
X
V
saddr
(saddr) -
4
2
X
X
X
V
X
X
0
P
0
X
X
X
0
P
0
X
X
X
0
P
0
X
X
X
0
P
0
X
X
X
0
P
0
X
X
X
0
P
0
X
0
X
X
rp2
rp2 -
saddrp
(saddrp) -
(saddr) + 1
(saddr) - 1
rp2 + 1
(saddrp) + 1
3
1
6
3
rp2
rp2- rp2-1
saddrp
(saddrp) -
6
3
ROR
r1. n
(CY. r17 - r10;
r1 m- 1 - r1 m) x n
4+3n
2
ROL
r1. n
(CY. r10 - r17;
r1 m+ 1 - r1 m) x n
4+3n
RORC
r1. n
(CY - r10;
r17-CY;
r1 m- 1 - r1 m) x n
4+3n
ROLC
r1. n
(CY - r17;
r10-CY;
r1 m+1- r1m) x n
4+3n
SHR
r1. n
(CY- r1 0;
r17-0;
r1 m- 1 - r1 m) x n
4+3n
SHL
r1. n
(CY- r1 7;
r10-O;
r1m + 1 - r1m) x n
4+3n
SHRW
rp1. n
(CY - rpO;
rP15- 0;
rPm - 1 - rPm) x n
4 +3n
2
X
X
0
SHLW
rp1. n
(CY +- rp15;
rpO-O;
rPm + 1 -- rPm) x n
4 + 3n
2
X
X
0
P
0
ROR4
(rp1)
A3-0 - (rp 1h-0;
(rp1)7-4 - A3-0;
(rp1) 3-0 - (rp1}]-4
8
2
X
X
0
P
0
ROL4
(rp1)
A3-0 - (rp1}]-4;
(rp1b-0 -- A3-0;
(rp1}]-4 - (rp1)3-0
8
2
X
X
0
P
0
Decimal Adjust Accumulator
3
X
X
X
V
0
DECW
ADJ4
4-194
CY
(saddrp) - 1
3
2
2
X
t\'EC
pPD78310/312
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
MOV1
CY, saddr.bit
CY -
CY, sfr.bit
AND1
OR1
States
Bytes
(saddr.bit)
6
3
X
CY -
sfr.bit
6
3
X
CY, A.bit
CY -
A.bit
6
2
X
CY, X.bit
CY -
X.bit
6
2
X
CY, PSWH, bit
CY -
PSWH.bit
6
2
X
CY, PSWL, bit
CY -
PSWL.bit
6
2
X
saddr.bit, CY
(saddr.bit) -
S
Z
AC
P/V
SUB
CY
3
CY
7
3
sfr.bit, CY
sfr.bit -
A.bit, CY
A.bit -
CY
8
2
X.bit, CY
X.bit- CY
8
2
PSWH.bit, CY
PSWH.bit -
CY
8
2
PSWL.bit, CY
PSWL.bit -
CY
8
2
CY, saddr.bit
CY -
CY A (saddr.bit)
6
3
CY,/saddr.bit
CY -
CY A (saddr.bit)
6
3
X
CY, sfr.bit
CY -
CY A sfr.bit
6
3
X
CY'/sfr.bit
CY -
CY A sfr.bit
6
3
X
CY, A.bit
CY -
CY A A.bit
6
2
X
CY,/A.bit
CY
CY A A.bit
6
2
X
CY, X.bit
CY -
CY A X.bit
6
2
X
CY,/X.bit
CY
CY A X.bit
6
2
X
CY, PSWH.bit
CY -
CY A PSWH.bit
6
2
X
CY,/PSWH.bit
CY -
CY A PSWH.bit
6
2
X
CY, PSWL.bit
CY -
CY A PSWL.bit
6
2
X
CY,/PSWL.bit
CY -
CY A PSWL.bit
6
2
X
CY, saddr.bit
CY -
CY V (saddr.bit)
6
3
X
CY,/saddr.bit
CY -
CY V (saddr.bit)
6
3
X
CY, sfr.bit
CY -
CY V sfr.bit
6
3
X
CY'/sfr.bit
CY -
CY V sfr.bit
6
3
X
2
X
+-
+-
CY
X
CY, A.bit
CY -
CY V A.bit
6
CY,/A.bit
CY -
CY V A.bit
6
2
X
CY, X.bit
CY -
CY V X.bit
6
2
X
CY,/X.bit
CY -
CY V X.bit
6
2
X
CY, PSWH.bit
CY -
CY V PSWH.bit
6
2
X
CY,/PSWH.bit
CY -
CY V PSWH.bit
6
2
X
CY, PSWL.bit
CY -
CY V PSWL.bit
6
2
X
CY, / PSWL. bit
CY -
CY V PSWL.bit
6
2
X
4-195
E
NEe
pPD78310/312
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
XOR1
CY, saddr.bit
CY -
CY, sfr.bit
SET1
CLR1
NOT1
States
Bytes
CY.Jf (saddr.bit)
6
3
X
CY -
CY.Jf sfr.bit
6
3
X
CY, A.bit
CY -
CY.Jf A.bit
6
2
X
CY, X.bit
CY -
CY.Jf X.bit
6
2
X
CY, PSWH.bit
CY -
CY.Jf PSWH.bit
6
2
X
CY, PSWL.bit
CY -
CY.Jf PSWL.bit
6
2
X
saddr.bit
(saddr.bit) -
5
2
sfr.bit
sfr.bit-1
6
3
A.bit
A.bit-1
7
2
X.bit
X.bit-1
7
2
PSWH.bit
PSWH·bit-1
7
2
PSWL.bit
PSWL.bit -1
7
2
saddr.bit
(saddr.bit) -
sfr.bit
1
5
2
sfr.bit - 0
6
3
2
0
A.bit
A.bit-O
7
X.bit
X.bit-O
7
2
PSWH.bit
PSWH·bit-O
7
2
PSWL.bit
PSWL.bit - 0
saddr.bit
(saddr.bit) -
(saddr.bit)
7
2
6
3
sfr.bit
sfr.bit -sfr.bit
6
3
A.bit
A.bit - A.bit
7
2
X.bit
X.bit -
7
2
PSWH.bit
PSWH.bit -
PSWH.bit
7
2
PSWL.bit
PSWL.bit -
PSWL.bit
7
2
SET1
CY
CY-1
3
CLR1
CY
CY-O
3
X.bit
Z
AC
P/V
SUB
CY
1
1
0
X
NOT1
CY
CY-CY
3
1
CALL
!addr16
(SP - 1) - (PC + 3)H;
(SP - 2) - (PC + 3)L;
PC - addr16;
SP- SP-2
8
3
CALLF
!addr11
(SP - 1) - (PC + 2)H;
(SP - 2) - (PC + 2k;
PC - addr11;
SP- SP-2
8
2
CALLT
(addr5)
(SP - 1) - (PC + 1)H;
(SP - 2) - (PC + 1k;
PCH - (TPFX8000H + addr5 + 1);
PCH - (TPFX8000H + addr5);
SP-SP-2
10
4-196
S
NEe
pPD78310/312
Instruction Set (cont)
Flags
States
Bytes
(SP - 1) +- (PC + 2)H;
(SP - 2) +- (PC + 2)l;
PCH +- rp1H;
PCl +- rp1l;
SP +- SP - 2
13
2
(SP - 1) +- (PC + 2)H;
(SP - 2) +- (PC + 2)l;
PCH +- (rp1)H;
PCl +- (rp1)l;
SP +- SP-2
11
2
BRK
(SP - 1) +- PSWH;
(SP - 2) +- PSWl;
(SP - 3) +- (PC + 1)H;
(SP - 4) +- (PC + 1)l;
PCl +- (OO3EH);
PCH +- (OO3FH);
SP +- SP-4
16
RET
PCl +- (SP);
PCH +- (SP + 1);
SP +- SP +2
RET!
PCl +- (SP);
PCH +- (SP + 1);
PSWl +- (SP + 2);
PSWH +- (SP + 3);
SP +- SP+4;
EOS +- 0
14
post
((SP - 1) +- postH;
(SP - 2) +- postl;
SP +- SP - 2) x n.
7+8n
PSW
(SP - 1) +- PSWH;
(SP - 2) +- PSWl;
SP +- SP-2
5
PUSHU
post
((UP - 1) +- postH;
(UP - 2) +- postl;
UP +- UP - 2) x n.
8+8n
2
POP
post
(postl +- (SP);
(postH +- (SP + 1);
SP +- SP + 2) x n.
7+8n
2
PSW
PSWl +- (SP);
PSWH +- (SP + 1);
SP +- SP + 2
5
post
(postl +- (UP);
postH +- (UP + 1);
UP +- UP + 2) x n.
8+8n
SP, #word
SP +- word
3
4
SP,AX
SP +- AX
3
2
Mnemonic
Operand
Operation
CALL
rp1
(rp1)
PUSH
POPU
MOVW
SP
Z
R
R
AC
P/V
SUB
CV
R
R
R
E
2
R
R
R
R
R
R
2
AX,SP
AX
3
2
INCW
SP
SP +- SP + 1
6
2
DECW
SP
SP +- SP-1
6
2
+-
S
LI._1Q7
t\'EC
pPD78310/312
Instruction Set (cont)
Flags
Mnemonic
Operand
Operation
States
Bytes
BR
!addr16
PC -- addr16
4
3
rp1
PCH -- rp1H;
PCl -- rp 1l;
6
2
(rp1)
PCH -- (rp1)H;
PCl -- (rp1)l;
9
2
7 .
2
$addr16
PC -- addr16
BC
BL
$addr16
PC -- addr16 if CY = 1
7(3)
BNC
BNL
$addr16
PC -- addr16 if CY = 0
7(3)
BZ
BE
$addr16
PC -- addr16 if Z = 1
7(3)
BNZ
BNE
$addr16
PC -- addr16 if Z = 0
7(3)
BV
BPE
$addr16
PC -- addr16 if PIV = 1
7(3)
BNV
BPO
$addr16
PC -- addr16 if PIV = 0
7(3)
BN
$addr16
PC -- addr16 if S = 1
7(3)
BP
$addr16
PC +- addr16 if S = 0
7(3)
2
BGT
$addr16
PC -- addr16 if (PIV.J.f S) V Z = 0
9(5)
3
2
BGE
$addr16
PC
+-
addr16 if P/V.J.f S = 0
9(5)
3
BLT
$addr16
PC
+-
addr16 if PIV.J.f S = 1
9(5)
3
BLE
$addr16
PC
+-
addr16 if (PIV.J.f S) V Z = 1
9(5)
3
BH
$addr16
9(5)
3
BNH
$addr16
9(5)
3
BT
saddr.bit, $addr16
9(7)
3
10(7)
4
10(7)
3
PSWH.bit, $addr16
=0
PC -- addr16 if Z + CY = 1
PC -- addr16 if (saddr.bit) = 1
PC +- addr16 if (sfr.bit) = 1
PC -- addr16 if A.bit = 1
PC -- addr16 if X.bit = 1
PC +- addr16 if PSWH.bit = 1
PSWL.bit, $addr16
PC
+-
addr16 if PSWl.bit = 1
saddr.bit, $addr16
PC
+-
addr16 if (saddr.bit)
sfr.bit, $addr16
PC -- addr16 if (sfr.bit)
A.bit, $addr16
PC -- addr16 if A.bit = 0
10(7)
3
X.bit, $addr16
PC -- addr16 if X.bit = 0
10(7)
3
PSWH.bit, $addr16
PC -- addr16 if PSWH.bit = 0
10(7)
3
PSWL.bit, $addr16
PC
addr16 if PSWl.bit = 0
10(7)
3
saddr.bit, $addr16
PC +- addr16 if (saddr.bit)
then reset (saddr.bit)
12(7)
4
sfr.bit, $addr16
PC +- addr16 if (sfr.bit)
then reset (sfr.bit)
12(7)
4
A.bit, $addr16
PC +- addr16 if A.bit = 1
then reset A.bit
11(7)
3
sfr.bit, $addr16
A.bit, $addr16
X.bit, $addr16
BF
BTCLR
A_1QR
PC +- addr16 if Z + CY
+-
=0
=0
=1
=1
10(7)
3
10(7)
3
10(7)
3
10(7)
4
10(7)
4
S
Z
AC
P/V
SUB
CY
NEe
pPD78310/312
Instruction Set (cant)
Flags
Mnemonic
Operand
Operation
States
Bytes
BTCLR
(cont)
X.bit, $addr16
PC +- addr16 if X.bit = 1
then reset X.bit
11(7)
3
PSWH.bit, $addr16
PC - addr16 if PSWH.bit = 1
then reset PSWH.bit
12(7)
3
PSWL.bit, $addr16
PC - addr16 if PSWl.bit = 1
then reset PSWl.bit
12(7)
3
saddr.bit, $addr16
PC - addr16 if (saddr.bit)
then set (saddr.bit)
12(7)
4
sfr.bit, $addr16
PC - addr16 if (sfr.bit)
then set (sfr.bit)
12(7)
4
A.bit, $addr16
PC - addr16 if A.bit = 0
then set A.bit
11(7)
4
X.bit, $addr16
PC - addr16 if X.bit = 0
then set X.bit
11(7)
3
PSWH.bit, $addr16
PC - addr16 if PSWH.bit = 0
then set PSWH.bit
12(7)
3
PSWL.bit, $addr16
PC - addr16 if PSWl.bit = 0
then set PSWl.bit
12(7)
3
r2, $addr16
r2-r2-1;
then PC - addr16 if r2 "" 0
8(5)
2
saddr, $addr 16
(saddr) - (saddr) - 1;
then PC - addr16 if saddr "" 0
7(6)
3
BRKCS
RBn
PCH-R5;
PCl -R4;
R7-PSWH;
R6-PSWl;
RBS2-0 -- n;
RSS -0;
IE-O
13
2
RETCS
!addr16
PCH - R5;
PCl - R4;
R4, R5 - (addr16);
PSWH - R7;
PSWl - R6;
EOS-O
6
3
MOVM
(DE+),A
(DE+) -A;
C - C - 1, End if C = 0
2+ 7n
(DE-), A
(DE-)-A;
C - C - 1, End if C = 0
2+ 7n
2
(DE+), (HL +)
(DE+) - (HL +);
C - C - 1, End if C = 0
2 + 10n
2
(DE-), (HL-)
(DE-) - (HL -);
C - C - 1, End if C = 0
2 + 10n
2
(DE+), A
(DH)-A;
C - C - 1, End if C = 0
2 + 12n
2
(DE-), A
(DE-)-A;
C - C -1, End if C = 0
2 + 12n
2
BFSET
DBNZ
MOVBK
XCHM
=0
=0
S
Z
AC
P/V
SUB
CY
Il
4-199
NEe
pPD78310/312
Instruction Set (cont)
Flags
S
Z
AC
P/V
2
X
X
X
V
X
2+8n
2
X
X
X
V
X
(OE+) - (HL+);
C - C - 1, End if C = 0 or Z = 0
2+ 11n
2
X
X
X
V
X
(OE-), (HL-)
(OE-) - (HL-);
C - C - 1, End if C = 0 or Z = 0
2 + 11n
2
X
X
X
V
X
(OE+), A
(OE+) - A;
C - C -1, End if C = 0 or Z = 1
2+8n
2
X
X
X
V
X
(OE-), A
(OE-) -A;
C - C - 1, End if C = 0 or Z = 1
2+8n
2
X
X
X
V
X
(OE+), (HL+)
(OE+) - (HL+);
C - C - 1, End if C = 0 or Z = 1
2 + 11n
2
X
X
X
V
X
(OE-), (HL-)
(OE-) - (HL-);
C +- C - 1, End if C= 0 or Z = 1
2 + 11n
2
X
X
X
V
X
(OE+), A
(OE+) -A;
C - C - 1, End if C = 0 or CY = 0
2+8n
2
X
X
X
V
X
(OE-), A
(OE-) -A;
C - C - 1, End if C = 0 or CY = 0
2+8n
2
X
X
X
V
X
(OE+), (HL+)
(OE+) - (HL+);
2 + 11n
C - C - 1, End if C = 0 or CY = 0
2
X
X
X
V
X
(OE-), (HL-)
(OE-) - (HL-);
2 + 11n
C - C - 1, End if C = 0 or CY = 0
2
X
X
X
V
X
(OE+), A
(OE+) -A;
C - C -1, End if C = 0 or CY = 1
2+8n
2
X
X
X
V
X
(OE-), A
(OE-) - A;
C - C - 1, End if C = 0 or CY
2+8n
2
X
X
X
V
X
(OE+), (HL+)
(OE+) - (HL+);
2 + 11n
C - C - 1, End if C = 0 or CY = 1
2
X
X
X
V
X
(OE-), (HL-)
(OE-) - (HL-);
C - C - 1, End if C = 0 or CY
2 + 11n
2
X
X
X
V
X
States
Bytes
(OE+) (HL+);
C +- C - 1, End if C = 0
2+ 15n
2
(OE-), (HL-)
(OE-)-(HL-);
C - C - 1, End if C = 0
2 + 15n
2
(OE+),A
(OE+) -A;
C - C -1, End if C = 0 or Z = 0
2+ 8n
(OE-), A
(OE-) - A;
C - C - 1, End if C = 0 or Z = 0
(OE+), (HL+)
Mnemonic
Operand
Operation
XCHBK
(OE+), (HL+)
CMPME
CMPBKE
CMPMNE
CMPBKNE
CMPMC
CMPBKC
CMPMNC
CMPBKNC
MOV
=1
STBC, #byte
STBC +- byte
5
4
WOM, #byte
WOM- byte
5
4
RSS -
RSS
3
1
RBn
RSS -0;
RBS2-0 - n
3
RBn, ALT
RSS-1;
RBS2-0 - n
3
SWRS
SEL
=1
NOP
No Operation
3
EI
IE - 1 (Enable Interrupt)
3
01
IE - 0 (Disable Interrupt
3
4-200
2
SUB
CY
NEe
NEe Electronics Inc.
pPD8035HL/48H
HIGH·SPEED, 8·BIT, SINGLE·CHIP
HMOS MICROCOMPUTERS
Description
Ordering Information
The I-IPD8035HL and the I-IPD8048H make up the
I-IPD8048H family of single-chip 8-bit microcomputers.
The processors in this family differ only in their internal
program memory options: the I-IPD8048H with 1K x 8
bytes of mask ROM and the J,lPD8035HL with external
memory.
Part
Number
Package Type
pPD8035HLC
40-pin plastic DIP
6 MHz
pPD8048HC
40-pin plastic DIP
6 MHz
Max Frequency
of Operation
Pin Configuration
The NEC I-IPD8035HL and I-IPD8048H are single
component, 8-bit, parallel microprocessors using
n-channel silicon gate MOS technology. The I-IPD8048H
family of components functions efficiently in control as
well as in arithmetic applications. Standard logic
function implementation is facilitated by the large
variety of branch and table look-up instructions.·
TO
XTAL1
XTAL2
3
RESET
ss
P2s
P~
The JlPD8035HL/48H instruction set comprises 1
and 2 byte instructions with. over 70% of them
single-byte. Execution requires only 1 or 2 cycles per
instruction and over 50% are single-cycle instructions.
P14
P13
The functions of the I-IPD8048H series of microprocessors can easily be expanded Lising standard
8080A/8085A peripherals and memories.
Il
P10
P23
The J,lPD8048H contains the following functions usually
found in external peripheral devices: 1024 x 8 bits of
ROM program memory; 64 x 8 bits of RAM data
memory; 27 I/O lines; an 8-bit interval timer/event
counter; oscillator and clock circuitry.
The I-IPD8035HL is intended for applications using
external program memory only. It contains all the
features of the I-IPD8048H except the 1024 x 8-bit
internal ROM. The external program memory can be
implemented using standard 8080A/8085A memory
products.
83-002890A
Pin Identification
No.
TO
4
Features
D Fully compatible with industry standard
.
8048/8748/8035
D 2.51-1s cycle time: all instructions 1 or 2 bytes
D Interval timer/event counter
D 64 x 8-byte RAM data memory
D External and timer interrupts
D 96 instructions: 70% single byte
D 271/0 lines
D Internal clock generator
D 8 level stack
D Compatible with 8080A/8085A peripherals
D HMOS silicon gate technology
D Single +5 V power supply
Symbol
6
9
Function
Test 0 input/output
XTAL1
Crystal 1input
XTAL2
Crystal 2 input
RESET
Reset input
SS
Single step input
INT
Interrupt input
EA
External access input
RD
Read output
PSEN
Program store enable output
10
WR
Write output
11
ALE
Address latch enable output
12-19
DBa-DB?
Bidirectional data bus
20
Vss
Ground
21-24. 35-38
P2a-P2?
Quasi-bidirectional Port 2
25
PROG
Program output
NEe
J-tPD8035HL148H
Pin Identification (cont)
No.
Symbol
26
VDD
RD(Read)
Function
RAM power supply
27-34
P10-P17
Quasi-bidirectional Port 1
39
T1
Test 1input
40
Vee
Primary power supply
Pin Functions
XTAL 1(Crystal 1)
XTAL1 is one side of the crystal, LC, or external frequency source (non-TTL-compatible VIH).
XTAL 2 (Crystal 2)
XTAL2 is the other side of the crystal or frequency
source.
TO (Test 0)
TO is the testable input using conditional transfer functions JTO and JNTO. The internal state clock (CLK) is
available to TO using the ENTO CLK instruction. TO can
also be used during programming as a testable flag.
T1 (Test 1)
T1 is the testable input using conditional transfer functions JT1 and JNT1. T1 can be made the counterltimer
input using the STRT CNT instruction.
RESET (Reset)
An active low on RESET initializes the processor. RESET is also used for PROM programming verification
and power-down (non-TTL compatible VIH).
SS (Single Step)
An active low on SS, together with ALE, causes the
processor to execute the program one step at a time.
I NT (Interrupt)
An active low on INT starts an interrupt if interrupts are
enabled. A reset disables an interrupt.INT can be tested
with the JNI instruction and, depending on the results, a
jump to the specified address can occur.
EA (External Access)
An active high on EA disables internal program memory
and fetches and accesses external program memory.
EA is used for system testing and debugging.
RD will pulse low when the processor performs a bus
read. An active low on RD enables data onto the processor bus from a peripheral device and functions as a read
strobe for external data memory.
WR(Write)
WR will pulse low when the processor performs a bus
write. WR can also function as awrite strobe for external data memory.
PSEN (Program Store Enable)
\
PSEN becomes active only during a~ external memory
fetch. (Active low).
ALE (Address Latch Enable)
ALE occurs at each cycle. ALE can also be used as a
clock output. The falling edge of ALE addresses external data memory or external program memory.
DBO-DB7 (Data Bus)
DBo-DB7 is a bidirectional port. Synchronous reads and
writes can be performed on this port using RD and WR
strobes. The contents of the DBo-DB7 bus can be
latched in a: static mode.
During an external memory fetch, DBo-DB7 output the
low-order eight bits of the memory address. PSEN
fetches the instruction. DBo-DB7 also output the address of an external data memory fetch. The addressed
data is controlled by ALE, RD, and WR
P10-P17 (Port 1)
P10-P17 is an 8-bit quasi-bidirectional port.
P2Q-P27 (Port 2)
P20-P27 is an 8-bit quasi-bidirectional port. P20-P23
output the high-order four bits of the address during an
external program memory fetch. P20-P23 also function
as a 4-bit 110 bus for the ",PD82C43 110 port expander.
PROG (Program Pulse)
PROG is used as an output pulse during a fetch when
interfacing with the ",PD82C43 1/0 port expander.
Vee (Primary Power Supply)
Vee is the primary power supply. Vee is +5V during
normal operation.
NEe
JJPD8035HL/48H
Vee (RAM Power Supply)
Voo must be set to +5 V for normal operation. Voo supplies power to the internal RAM during standby mode.
Vss (Ground)
Vss is ground potential.
Block Diagram
Expansion to Additional
Extemal Memory and 110
Oscillator
Frequency
Bus Latch
Low Program
Counter's Temp
Register
Bus
Buffer
and
Latch
Port 1
Timer and
Event Counter
:J
8
......
B
_
Arlthtmetic
Logic Unit
(ALU)
TestO
Multiplexer
Register 0
_Test1
-00
Conditional
Branch
Logic
(8)
--+- Vee Program Supply
Power
Supply
{
-
-
Register 1
Flag 0
Register 2
_Flag1
_
Register 4
"8~r-------------4
Register 5
_ACC
VDD +5 V (Low Power Standby)
_
--+- VSS Ground
Register 3
Timer Flag
-Carry
ACC Bit Test
~
r-------------4
Register 6
Register 7
8·Level Stack
(Variable Word Length)
EA
Interrupt
Initialize
PROMI
Expander
Strobe
Control and Timing
XTAL XTAL
1
2
ALE
External
Memory
Access
tt
Oscillatorl
Crystal
RD
WR
Optional Second
Register Bank
Data Store
Address
Latch
Strobel
Cycle
Clock
Program
Memory
Enable
Single
Step
Read/Write
Strobes
Resident Data MemoryRAM (64 x 8)
Note: !,PD8035H does not include ROM.
83-002891C
NEe
/JPD8035HL148H
Logic Symbol
DC Characteristics (cont)
TA=OOCto + 70°C, Vcc=Voo= +5V±10%, Vss=OV
Umlts
Port 1
Parameter
Port 2
Output low
VOL3
voltage (all other
outputS)
Read
::E:
ic
Port Expander
Strobe
Bus
83-002892A
Absolute Maximum Ratings
TA = 25°C
Operating temperature, TOPT
O°C to +70°C
Storage temperature, TSTG
- 65°C to +150°C
-0.5Vto +7V (Note 1)
Voltage on any pin, VI / 0
Power dissipation, Po
1.5W
Note:
(1) With respect to ground.
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the limits
described in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
DC Characteristics
TA=OOCto +70OC, Vcc=Voo= +5V±10%, Vss=OV
Umlts
Input low
voltage (All
except XTAL1,
XTAL2)
VIL
Min
-0.5
Input high
VIH
voltage (All
except XTAL1,
XTAL2, RESET)
2.0
Input high
VIH1
voltage (XTAL1,
XTAL2, RESET)
3.8
VOL
Output low
volta~,
WR, PSEN,
ALE)
VOL1
Output low
voltage (PROG)
VOL2
4-?O4
0.45
V
10L =2.0mA
2.4
V
10H = - 400 JAA
Output high
VOH1
voltage (RD,
WR, PSEN, ALE)
2.4
V
10H = - 400 JAA
Output high
VOH2
voltage (all other
outputs)
Input leakage
IlL
current (T1, INT)
2.4
V
10H= -40JAA
±10
JAA
Vss ~ VIN ~ Vcc
-500
JAA
Mal
Unit
0.8
V
Test
Conditions
VOH
0.8
VCC
VCC
VCC~VIN~
Input leakage
current
(P1 0- P1 7,
~-P27' EA,
SS)
11L1
Output leakage
current (bus,
TO, high
impedance
state)
10L
Power down
supply current
100
4
8
mA
TA=25°C
Total supply
current
100+
Icc
50
80
mA
TA=25°C
RAM standby
voltage
Voo
5.5
V
Vss+0.45V
±10
JAA
VCC~VIN~
VSS+0.45V
2.2
Standby mode.
Reset~ 0.6V
AC Characteristics
TA=OOCto +70 oC, Vcc=Voo = +5V±10%, Vss=OV
Limits
-0.5
Test
Conditions
Unit
Parameter
Input low
VIL1
voltage (RESET,
X1, X2)
Output low
voltage (bus)
Typ
Typ
Max
Output high
voltage (bus)
~~~~mStore
Address Latch
Enable
Symbol
Min
Write
~
Parameter
Symbol
V
V
V
Symbol
Min
Typ
Max
Unit
Test
Conditions
ALE pulse width tLL
410
ns
(Note 1)
Address setup
to ALE
tAL
220
ns
(Note 1)
Address hold
from ALE
tLA
120
ns
(Note 1)
Control pulse
tCC1
width (RD,WR)
1050
ns
(Note 1)
Contro~
tCC2
800
ns
(Note 1)
tow
880
ns
(Note 1)
ns
(Note 2)
220
ns
(Note 1)
width (PSEN)
0.45
0.45
0.45
V
V
V
IOL=2.0mA
10L =2.0mA
10L =2.0mA
Data setup WR
Data hold after
WR
two
110
Data hold (RD,
PSEN)
tOR
0
RDto data in
tR01
800
ns
(Note 1)
PSEN to data in tR02
550
ns
(Note 1)
NEe
J..tPD8035HL/48H
AC Characteristics (cont)
Timing Waveforms
TA =O°C to +70°C, vcc=voo= +5V±10%, Vss=OV
Limits
Parameter
Symbol
Min
Typ
Max
Unit
rest
Conditions
ns
(Note 1)
Address setup
toWR
tAW
Address setup
to data (RD)
tA01
1570
ns
(Note 1)
Address setup
to data (PSEN)
tA02
1090
ns
(Note 1)
680
Instruction Fetch from External Memory
ALE
Address float to tAFC1
RD. WR
290
ns
(Note 1)
Address float to tAFC2
PSEN
40
ns
(Note 1)
ALE to control
(RD.WR)
tLAFC1
420
ns
(Note 1)
ALE to control
(PSEN)
tLAFC2
170
ns
(Note 1)
~trolto~
tCA1
120
ns
(Note 1)
tCA2
620
ns
(Note 1)
tcp
210
ns
(Note 1)
PSEN
Bus
-tAD283-002864A
Read from External Data Memory
tCY
(RD. WR. PROG)
Control to ALE
(PSEN)
Port control
setup to PROG
ALE
I- tLL -j-tLAFC1-!-tCC1-!-tCA1-!
Port control hold tpc
to PROG
460
ns
(Note 1)
PROG to P2
input valid
tpR
1300
ns
(Note 1)
Input data hold
from PROG
tpF
250
ns
(Note 1)
Output data
setup
top
850
ns
(Note 1)
Output data hold tpD
200
ns
(Note 1)
PROG pulse
width
tpp
1500
ns
(Note 1)
Port 2 I /0 data tpL
setup to ALE
460
ns
(Note 1)
Port 2 I /0 data tLP
hold to ALE
150
Floating
tAD83-D02883A
Write to External Memory
ALE
l-tLAFC1-!-tCC1-!-tCA1-1
WR
Port output from tpv
ALE
ns
(Note 1)
850
ns
(Note 1)
15
JAs
(Note 1)
ns
(Note 1)
11
LJ
AD
LJ
Floating
83-Q02864A
Cycle time
tCY
2.5
TO rep rate
tOPRR
500
Note:
(1) Control outputs: CL = 80 pF, bus outputs: CL
(2) Bus high impedance, load
=150 pF
=20 pF
4-20fi
NEe
",PD8035HL/48H
Timing Waveforms (cont)
Port 2 Timing
Bus Timing Requirements
Symbol
Timing Formula
MinIMax
Unit
tLL
(7/30) tCY -170
Min
ns
tAL
(2I15)tCy-110
Min
ns
(1/15)tCy-40
Min
ns
ns
ALE
Expander
Port
Output
Expander
Port
Input
(1/2) tCy-200
Min
tCC2
(2/5) tCy-200
Min
ns
tow
(13/30) tCY - 200
Min
ns
ns
two
(1/15)tCy-50
Min
tOR
(1/10)tCy-30
Max
ns
tR01
(215) tCY- 200
Max
ns
tR02
(3/10) tCY - 200
Max
ns
tAW
(1/3)tCy-150
Min
ns
tA01
(11/15) tCY- 250
Max
ns
tA02
(8/15) tCy-250
Max
ns
tAFC1
(2115) tCy-40
Min
ns
tAFC2
(1/30)tCy-40
Min
ns
tLAFC1
(1/5) tCy-75
Min
ns
tLAFC2
(1/10)tCy-75
Min
ns
tCA1
(1/15)tCy-40
Min
ns
tCA2
(4/15) tCy-40
Min
ns
tcp
(1/10) tCy-40
Min
ns
tpc
(4/15) tCY- 200
Min
ns
tpR
(17/30) tCy-120
Max
ns
ns
PROG
4-206
tpF
(1/10) tCY
Max
top
(2/5) tCy-150
Min
ns
tpo
(1/10)tCy-50
Min
ns
tpp
(7/10) tCY - 250
Min
ns
tpL
(4/15) tCY - 200
Min
ns
tLP
(1/10) tCY -100
Min
ns
tpv
(3/10) tCy-100
Max
ns
tOPRR
(3/15) tCY
Min
ns
tCY
6MHz
/-Is
Instruction Set
Operation Code
Mnemonic
Function
Description
D7
De
Ds
D4
D3
D2
D1
Do
ADDA, # data
(A) -
Add immediate the specified data to the accumulator.
0
d7
0
d6
0
d5
0
d4
0
d3
0
d2
1
dl
1
do
ADDA, Rr
(A) - (A) + (Rr)
r = 0-7
Add contents of designated register to the accumulator.
0
1
1
0
1
ADDA, @Rr
(A) - (A) + ((Rr»
r.= 0-1
Add indirect the contents of the data memory location to the
accumulator.
0
0
0
0
0
ADDC A, # data
(A) -
Add immediate with carry the specified data to the
accumulator.
0
d7
0
d6
1
d4
0
d3
0
d2
1
dl
ADDCA, Rr
(A) - (A) + (C) + (Rr)
for r = 0-7
Add with carry the contents of the designated register to the
accumulator.
0
1
1
1
ADDCA,@Rr
(A) - (A) + (C) + ((Rr»
forr = 0-1
Add indirect with carry the contents of data memory location to
the accumulator.
0
ANL A, # data
(A) -
Logical AND specified immediate data with accumulator.
0
d7
1
d6
0
d5
ANLA, Rr
(A) - (A) AND (Rr)
r = 0-7
Logical AND contents of designated register with accumulator.
0
1
0
1
ANLA, @Rr
(A) - (A) AND ((Rr))
r = 0-1
Logical AND indirect the contents of data memory with
accumulator.
0
0
0
CPLA
(A) -NOT (A)
Complement the contents of the accumulator.
0
a
1
0
CLRA
(A)-O
Clear the contents of the accumulator.
0
0
0
0
Decimal adjust the contents of the accumulator.
0
Decrement by 1the accumulator's contents.
0
0
Cycles
Bytes
C
Accumulator
(A) + data
(A) + (C) + data
(A) AND data
DAA
DECA
(A)-(A)-1
oJ
1
d4
0
0
0
d3
0
d2
1
dl
0
0
0
0
0
0
INCA
(A)-(A)+1
Increment by 1the accumulator's contents.
0
0
0
(A) -
Logical OR specified immediate data with accumulator.
0
d7
1
d6
0
d5
0
d4
0
d3
ORL A, Rr
(A) - (A) OR (Rr) for
r = 0-7
Logical OR contents of designated register with accumulator.
0
1
0
0
1
ORLA, @Rr
(A) - (A) OR ((Rr)) for
r = 0-1
Logical OR indirect the contents of data memory location with
accumulator.
RLA
(AN + 1) - (AN); N = 0-6
(Ao) -(A7)
Rotate accumulator left by 1 bit without carry.
0
RLC A
(AN + 1) - (AN); N = 0-6
(Ao)-(C)
(C)-(A7)
Rotate accumulator left by 1 bit through carry.
0
(AN) - (AN + 1); N = 0-6
(A7) - (Ao)
Rotate accumulator right by 1 bit without carry.
(A) OR data
0
0
F1
~
~
•
1
do
•
•
0
ORL A, # data
RRA
~
0
d5
•
Flags
AC FO
•
1
do
•
0
d2
1
dl
0
0
1
do
,.a
1:
CD
0
W
01
Z
0
.,.....rCD
)
Z
.J
I!I
~
I
\)
,.
1::
Instruction Set (cont)
::>
:xl
Mnemonic
Function
Description
D7
De
Operation Code
Ds D4 D3 D2
D1
DO
Cycle.
Byte.
C
Rotate accumulator right by 1 bit through carry.
0
SWAP A
(AN) - (AN + 1); N = 0-6
(A7)-(C)
(C)-(Ao)
(A4-A7) -'" (Ao-A3)
Swap the two 4-bit nibbles in the accumulator.
0
XRLA. # data
(A) -
Logical XOR specified immediate data with accumulator.
1
d7
1
d6
0
d5
1
d4
0
d3
XRLA. Rr
(A) - (A) XOR (Rr) for
r = 0-7
Logical XOR contents of designated register with accumulator.
1
1
0
1
1
XRLA. @Rr
(A) - (A) XOR ((Rr)) for
r = 0-1
Logical XOR indirect the contents of data memory location with
accumulator.
(Rr) - (Rr) - 1; r = 0-7
If (Rr) = 0;
(PCO-PC7) - addr
Decrement the specified register and test contents.
(PCO-PC7) -- addr if Bb = 1
(PC) -- (PC) + 2 if Bb = 0
Jump to specified address if accumulator bit is set.
(PCO-PC7) -- addr if C = 1
(PC) -- (PC) + 2 if C = 0
Jump to specified address if carry flag is set.
(PCO-PC7) -- addr if FO = 1
(PC) -- (PC) + 2 if FO = 0
Jump to specified address if flag FO is set.
(PCO-PC7) - addr if F1 = 1
(PC) -- (PC) + 2·if F1 = 0
Jump to specified address if flag F1 is set.
(PCS-PC10) - (addrs-addr10)
(PCO-PC7) -- (addro-addr7)
(PC11) - DBF
Direct jump to specified address within the 2K address block.
JMPP@A
(PCO-PC7) -- ((A))
Jump indirect to specified address with address page.
JNCaddr
(PCO-PC7) - addr if C = 0
(PC) -- (PC) + 2 if C = 1
Jump to specified address if carry flag is low.
(PCO:-PC7) -- addr if I = 0
(PC) - (PC) + 2 if I = 1
Jump to specified address if interrupt is low.
(PCO-PC7) - addr if Ta = 0
(PC) - (PC) + 2 ifTa 1
Jump to specified address if test 0 is low.
(PCO-PC7) -- addr ifT1 = 0
(PC) - (PC) + 2 ifT1 1
Jump to specified address if test 1 is low.
(PCO-PC7) -- addr if A = a
(PC) - (PC) + 2 if A = 1
Jump to specified address if accumulator is non-zero.
(PCO-PC7) - addr ifTF = 1
(PC) -- (PC) + 2 ifTF = a
Jump to specified address if timer flag is set to 1.
Branch
DJNZ Rr. addr
JBb addr
JC addr
JFO addr
JF1 addr
JMP addr
JNI addr
JNTO addr
JNT1 addr
JNZ addr
JTF addr
F1
CJ
CO
0
Accumulator (cont)
RRCA
Flags
AC FO
(A) XOR data
=
=
II
•
0
W
en
,........
Z
0
0
0
0
d2
1
d1
0
0
0
1
do
a7
as
a5
~
a3
r
a2
r
a1
r
ao
b2
a7
b1
a6
bo
a5
a4
0
a3
0
a2
a1
0
ao
1
a7
1
a6
1
a5
a4
0
a3
1
a2
1
a1
0
ao
0
a7
as
1
a5
~
0
a3
1
a2
1
a1
0
ao
0
a7
a6
1
a5
a4
0
a3
1
a2
1
a1
0
ao
a10
a7
ag
a6
as
a5
0
a4
0
a3
1
a2
a1
0
ao
1
0
0
0
0
a3
a2
a1
0
ao
0
a3
a2
a1
a
ao
1
0
0
1
a7
a6
0
0
0
a7
as
~
~
a
a7
a
a6
a5
~
a
a3
a2
a1
a
ao
a
a7
a6
a
a5
a
a4
a
a3
a2
a1
a
ao
a7
a
a6
a
a5
a4
0
a3
a2
a1
a
ao
a
a7
a6
a
a5
a4
a
a3
1
a2
a1
0
ao
a5
~
a
2
2
C»
Z
2
2
2
2
2
2
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Function
Description
JTO addr
(PCO-PC l ) - addr if TO = 1
(PC) - (PC) + 2 if TO = 0
Jump to specified address if test 0 is a 1.
JT1 addr
(PCO-PCl) - addr if T1 = 1
(PC) - (PC) + 2 ifT1 = 0
Jump to specified address if test 1is a 1.
(PCo-P.C?) - addr if A = 0
(PC) - (PC) + 2 if A = 1
Jump to specified address if accumulator is O.
D7
De
Ds
D4
Da
0
0
as
a4
0
a3
as
0
al
1
a?
as
1
as
0
as
0
as
a4
0
a4
0
a3
0
a3
0
0
0
D2
D1
Do
a2
a1
0
ao
a2
1
a2
1
a1
1
a1
0
ao
0
aO
Cycles
Bytes
Branch (cont)
JZ addr
al
C
Flags
AC FO
F1
~
~
2
Control
EN I
Enable the external interrupt input.
0
DIS I
Disable the external interrupt input.
0
Enable the clock output pin TO.
0
ENTO CLK
SEL MBO
~
(DBF) -0
Select bank 0 (locations 0-2047) of program memory.
SEL MB1
(DBF)-1
Select bank 1(locations 2048-4095) of program memory.
SEL RBO
(BS)-O
Select bank 0 (locations 0-7) of data memory.
SEL RB1
(BS)-1
Select bank 1 (locations 24-31) of data memory.
(A)-data
Move immediate the specified data into the accumulator.
MOVA, Rr
(A) -
(Rr); r = 0-7
Move the contents of the designated registers into the
accumulator.
MOVA,@Rr
(A) -
((Rr)); r = 0-1
Move indirect the contents of data memory location into the
accumulator.
MOVA, PSW
(A)-(PSW)
Move contents of the program status word into the
accumulator.
MOV Rr, # data
(Rr) -
Move immediate the specified data into the deSignated
register.
d?
0
1
0
0
0
0
0
0
0
1
0
0
d?
0
ds
1
ds
0
d4
0
d3
0
d2
1
1
1
0
0
0
0
0
0
ds
1
ds
1
d4
1
d3
1
MOV Rr, A
(Rr) -
Move accumulator contents into the designated register.
1
0
MOV@Rr,A
((Rr)) -
(A); r = 0-1
Move indirect accumulator contents into data memory location.
1
0
MOV@Rr,
# data
((Rr)) -
data; r = 0-1
Move immediate the specified data into data memory.
1
d?
0
ds
1
d5
1
0
(A); r = 0-7
0
0
0
Data Moves
MOVA, # data
data; r = 0-7
0
MOVPSW, A
(PSW)-(A)
Move contents of accumulator into the program status word.
MOVPA,@A
(PCo-PC?) - (A)
(A)-((PC))
Move data in the current page into the accumulator.
MOVP3A,@A
(PCo-PC?) - (A)
(PCa-PCm) - 011
(A)-((PC))
Move program data in page 3 into the accumulator.
1
0
0
1
d1
1
do
r
d2
r
d1
r
do
0
1
0
0
0
0
1
d4
0
d3
0
d2
0
d1
1
0
0
0
0
2
2
1::
do
"
D
CD
0
0
W
UI
...-..Z
.
m
I
I\)
Z
0
<0
II
~
I
1::
Instruction Set (cont)
I\)
(5
Mnemonic
Description
Function
D7
De
Ds
Operation Code
D4 D3 D2
Flags
D1
Do
Cycles
Bytes
C
AC
FO
F1
MOVXA, @R
(A) -
((Rr»; r = 0-1
Move indirect the contents of external data memory into the
accumulator.
0
0
MOVX@R,A
((Rr)) -- (A); r = 0-1
Move indirect the contents Of the accumulator into external
data memory.
0
0
XCH A, Rr
XCHA,@Rr
(A) ++ (Rr); r = 0-7
(A) ++ ((Rr)); r = 0-1
Exchange the accumulator and designated register's contents.
Exchange indirect contents of accumulator and location in data
memory.
XCHDA,@Rr
(Ao-A3)
r = 0-1
Exchange indirect 4-bit contents of accumulator and data
memory.
0
++
((Rr))o-((Rr))3;
0
0
0
0
Flags
CPLC
(C) -NOT(C)
Complement contents of carry bit.
0
CPL FO
(FO) -
NOT (FO)
Complement contents of flag FO.
0
NOT (F1)
0
0
0
0
0
0
r
0
0
0
0
CD
:z
•
0
Complement contents of flag Ft
0
1
0
Clear contents of carry bit to O.
0
0
0
CLR FO
(FO)-O
Clear contents of flag 0 to O.
CLR F1
(F1)-0
Clear contents of flag 1to O.
Input / Output
ANL BUS,
# data
(bus) -
0
0
0
0
•
•
•
0
Logical AND immediate specified data with contents of bus.
1
d7
0
d6
0
d5
1
d4
1
d3
0
d2
0
d1
0
do
(Pp) -- (Pp) AND data
p = 1-2
Logical AND immediate specified data with designated
port (1 or 2).
1
d7
0
d6
0
d5
1
d4
1
d3
0
d2
P
d1
P
do
ANLD Pp, A
(Pp) - (Pp) AND (Ao-A3);
p= 4-7
Logical AND contents of accumulator with designated port
(4-7).
1
0
0
1
1
1
IN A, Pp
(A) -
(Pp); p = 1-2
Input data from designated port (1-2) into accumulator.
0
0
0
0
0
INSA, BUS
(A) -
(bus)
Input strobed bus data into accumulator.
0
0
0
0
0
MOVDA, Pp
(Ao-A3) - (Pp); p = 4-7
(A4-A7) -- 0
Move contents of designated port (4-7) into accumulator.
0
0
0
0
MOVD Pp, A
(Pp) -(Ao-A3); p = 4-7
Move contents of accumulator to designated port (4-7).
0
0
ORL BUS,
# data'
(bus) -- (bus) OR data
Logical OR immediate specified data with contents of bus.
1
d7
0
d6
0
0
d5
ORLD Pp, A
(Pp) - (Ppl OR (Ao-A3);
P = 4-7
Logical OR contents of accumulator with designated port
(4-7).
1
0
ORL Pp,
(Pp) - (Pp) OR data
p = 1-2
Logical OR immediate specified data with designated port
(1-2).
d7
OUTL BUS, A
(bus) --:- (A)
Output contents of accumulator onto bus.
0
OUTL Pp,A
(Pp) -
Output contents of accumulator to designated port (1-2).
0
# data
(A); P = 1-2
II
....
.,..
0
(F1) -
(bus) AND data
:z
r-.
2
r
0
(C)-O
0
W
01
0
1
0
CPL F1
0
0
0
CLRC
ANL Pp,
CD
0
Data Moves (cont)
# data
"e
P
0
1
2
0
0
0
d4
1
d3
d2
d1
do
0
0
1
1
P
P
0
d6
0
d5
0
d4
1
d3
0
d2
P
d1
P
do
0
0
0
0
0
1
0
0
2
2
~
~
Instruction Set (cont)
Flags
Operation Code
Mnemonic
Description
Function
D7
Do
Ds
D4
0
0
D3
D2
Increment by 1 contents of designated register.
0
0
0
1
Increment indirect by 1 the contents of data memory location.
0
0
0
0
0
a10
a7
ag
a6
aa
a5
a4
a3
a2
Return from subroutine without restoring program status word.
0
0
0
0
0
Return from subroutine restoring program status word.
0
0
D1
Do
Subroutine
Registers
= 0-7
= 0-7
DEC Rr (Rr)
(Rr) -
(Rr) - 1; r
INC Rr
(Rr) -
(Rr) + 1; r
INC@Rr
((Rr)) r = 0-1
CALLaddr
((SP)) - (PC),
(PSW4-PSW7),
(SP) - (SP) + 1
(PCa-PC1Q) - (addra-addr10)
(PCO-PC7) - (addro-addr7)
(PC11) - DBF
((Rr)) + 1;
(SP) = 1
((SP))
RET
(SP) (PC) -
RETR
(SP) - (SP) = 1
(PC) -((SP))
(PSW4-PSW7) - ((SP))
Decrement by 1 contents of designated register.
Call designated subroutine.
Timer / Counter
EN TCNTI
Enable internal interrupt flag for timer / counter output.
0
0
DIS TCNTI
Disable internal interrupt flag for timer / counter output.
0
0
MOVA, T
(A)-(T)
Move contents of timer / counter into accumulator.
0
MOVT, A
(T)-(A)
Move contents of accumulator into timer / counter.
0
0
0
a1
aO
Bytes
C
AC
FO
F1
~
~
0
0
0
1
0
STOP TCNT
Stop count for event counter.
0
STRT CNT
Start count for event counter.
0
0
STRTT
Start count for timer.
0
0
Miscellaneous
NOP
No operation performed.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note:
(1) Operation code designations rand p form the binary representation of the registers and ports involved.
(2) The dot under the appropriate flag bit indicates that its content is subject to change by the instruction it appears in.
(3)
Cycles
References to the address and data are specified in bytes 2 and/or 1 of the instruction.
0
l:::
"
~
CO
(4) Numerical subscripts appearing in the function column reference the specific bits affected.
0
(5) When the bus is written to, with an OUTl instruction, the bus remains an output port until either device is reset or a MOVX instruction is excecuted.
CIt
c.»
...:z:....
.
f"
CD
~
:z:
I!I
ttiEC
I-lPD8035HLI48H
Instruction Set Symbol Definitions
Symbol
A
AC
addr
Operating Characteristics
Description
Accumulator
Bu~ Output High Voltage YS. Source Current
Auxiliary carry flag
\TYP
Program memory address (12 bits)
Bb
Bit designator (b = 0-7)
BS
Bank switch
BUS
Bus port
C
Carry flag
3mA
:I:
ClK
Clock signal
CNT
Event counter
\
\
2mA
9
1mA
Nibble designator (4 bits)
data
Number of expression (8 bits)
DBF
Memory bank flip-flop
FO, F1
Vec=4.5V
OV
2V
~
I
4V
6V
VOH
Flags 0,1
Interrupt
Pp
PSW
"In-page" operation designator
Port designator (p=1, 2 or 4-7)
Rr
Register designator (r=O, 1or 0-7)
SP
Stack pointer
T
Timer
TF
Timer flag
TO, T1
Testable flags 0, 1
X
External RAM
#
Prefix for immediate data
@
Prefix for indirect address
$
Program counter's current value
(x)
Contents of external RAM location
((x))
Port P1 & P2 Output High Voltage YS. Source Current
Program status word
Vee=4.5V
~~
.
:I:
9
\
OV
~
I
4V
2V
6V
VOH2
Contents of memory location addressed by the
contents of external RAM location
Replaced by
AND
Logical product (logical AND}
OR
Logical sum (logical OR)
XOR
Exclusive-OR
Bus Output Low Voltage Ys. Sink Current
Typ
Vee = 4.5 V
..J
9
~----------------~----------------~I
OV
4-212
1V
VOL
2V
NEe
NEe Electronics Inc.
Description
The IIPD80C35, IIPD80C48, and IIPD48 are true standalone 8-bit microcomputers fabricated using CMOS
technology. All of the functional blocks necessary for
an integrated microcomputer are incorporated, including a 1 K-byte ROM (J.tPD80C48 only), a 64-byte RAM,
27 I/O lines, an 8-bit timer/event counter, and a clock
generator. This integrated capability permits use in
stand-alone applications. For deSigns requiring extra
capability, the1lPD80C35/IIPD80C48 can be expanded
using peripherals and is memory compatible with
industry-standard 8080A/8085A processors.
pPD80C35/C48,pPD48
8-BIT, SINGLE-CHIP
CMOS MICROCOMPUTERS
Pin Configurations
40·Pin Plastic DIP
TO
XTAL1
XTAL2
RESET
4
iNf
EA
Providing compatibility with industry-standard 8048,
8748, and 8035 processors, the IIPD80C35/IIPD80C48
features significant savings in power consumption. In
addition to the power savings gained through CMOS
technology, the IIPD80C35/IIPD80C48 offers two
standby modes (Halt and Stop modes) to further
minimize power drain.
DB7
Vss
Features
D 8-Bit CPU with memory and 110 on a single-chip
D Hardware/software-compatible with industryD
D
D
D
D
D
D
D
D
D
D
D
D
standard 8048, 8748, and 8035 processors
1K x 8 ROM (J.tPD80C48 only)
64 x 8 RAM
27 I/O lines
2.5-IIS cycle time (6-MHz crystal)
All instructions executable in 1 or 2 cycles
97 instructions: 70 percent are single-byte
instructions
Internal timer/event counter
Two interrupts (external and timer)
Easily expandable memory and I/O
Bus compatible with 8080A/8085A peripherals
Power-efficient CMOS technology requiring a
single +2.5 to +6.0 V power supply
Halt mode
Stop mode
83·002861A
52· Pin Plastic Mlniflat
NC
NC
P 25
PROG
NC
P23
P2&
P22
P27
P21
T1
P20
vce
Vec
NC
Vss
TO
DB7
XTAL1
DB6
XTAL2
DB5
RESET
NC
DB4
NC
83·002882A
4-213
NEe
pPD80C35/C48,pPD48
Pin Configurations (cont)
Pin Identification
Symbol
44-Pin Plastic Miniflat
Cl
()
z
VDD
g: .., '"
0
N
£I.
N
£I.
en
C\I
£I.
IN
£I.
f'-.
CD
II)
III III III
>'" Q
Q Q
""
Test 0 input/clock output
XTAL1
Crystal 1 input
XTAL2
Crystal 2 input
III
Q
DB3
0
P10
RESET
Reset input
SS
Software stop. input
INT
Interrupt input·
EA
External access input
DB2
P 11
Function
TO
31
DB1
P12
DBo
RD
Read output
P 13
ALE
PSEN
Program store enable output
WR
Write output
ALE
Address latch enable output
Vss
Ground
P20-P27
Quasi-bidirectional port 2
P 14
28
IlP D48
WR
P1s
PSEN
NC
AD
P1s
P17
25
EA
iNT
55
10
P24
Bidirectional data bus
PROG
Program output
VDD
Oscillator control voltage
T1
Test 1 input
Quasi-bidirectional port 1
83-003962A
Ordering Information
Part
Number
Package
Type
Max Frequency
of Operation
ROM
JlPD80C35C
40-pin plastic DIP
6 MHz
None
JlPD80C48C
40-pin plastic DIP
6 MHz
1K x 8
JlPD80C48G-00
52-pin plastic
miniflat
6 MHz
1K x 8
JlPD48G-22
44-pin plastic
miniflat
6 MHz
1K x 8
Note:
JlPD80C48C, JlPD80C48G-00, and JlPD48G-22 have two optional
port types: type 0, 10H = -5 JlA; type 1, 10H = -50 JlA. Type 0 or 1 can
be selected independently for P1o-P17, P2o-P23, and P24-P27.
Vee
Primary power supply
NC
No connection
Pin Functions
XTAL 1, XTAL2 [Crystals 1, 2]
XTAl1 and XTAl2 are the crystal inputs for the internal
clock oscillator. XTAl1 is also used as an input for
external clock signals.
TO [Test 0]
The JTO and JNTO instructions test the level of TO and,
if it is high, the program address jumps to the specified
address. TO becomes a clock output when the ENTO
ClK instruction is executed.
T1 [Test 1]
The JT1 and JNT1 instructions test the level of T1 and,
if it is high, the program address jumps to the specified
address. T1 becomes an internal counter input when
the STRT CNT instruction is executed.
RESET [Reset]
RESET initializes the processor and is also used to
verify the internal ROM. RESET determines the oscillation stabilizing time during the release of STOP mode.
The RESET pulse width requires at least 5 machine
cycles when the supply voltage is within specifications
and the oscillation frequency is stable.
4-214
NEe
pPD80C35/C48, pPD48
SS [Single Step]
P10-P17 [Port 1]
SS causes the processor to execute the program one
step at a time.
P1 O-P17 is an 8-bit quasi-bidirectional port.
P20-P27 [Port 2]
INT [Interrupt]
I NT starts an interrupt if interrupts are enabled. A reset
disables an interrupt. INT can be tested with the JNI
instruction and, depending on the results, a jump to
the specified address can occur.
EA [External Access]
EA disables internal program memory and fetches and
accesses external program memory. EA is used for
system testing and debugging.
P2o-P27 is an 8-bit quasi-bidirectional port. P2o-P23
output the high-order four bits of the address during an
external program memory fetch. P2o-P23 also function
as a 4-bit 1/0 bus for the pPD82C43 I/O port expander.
PROG [Program Pulse]
PROG is used as an output pulse during a fetch when
interfacing with the pPD82C43 1/0 port expander.
V DO [Oscillator Control Voltage]
RD enables a data read from external memory.
VDD stops and starts the oscillator in STOP mode.
STOP mode is enabled by forcing VDD low during a
rest.
WR [Write]
Vee [Primary Power Supply]
WR enables a data write to external memory.
Vee is the primary power supply. Vee must be between
+2.5 V and +6.0 V for normal operation. In STOP mode,
Vee must be at least +2.0 V to ensure data retention.
RD [Read]
PSEN [Program Store Enable]
PSEN fetches instructions only from external program
memory.
ALE [Address Latch Enable]
ALE occurs at each cycle. The falling edge of ALE
addresses external data memory or external program
memory. ALE can also be used as a clock output.
Vss [Ground]
Vss is ground potential.
NC [No Connection]
NC is no connection.
DBO-DB7 [Data Bus]
DBo-DB7 is a bidirectional port, which reads and writes
data using RD and WR for latching. During an external
program memory fetch, DBo-DB7 output the low-order
eight bits of the memory address. PSEN fetches the
instruction. DBo-DB7 also output the address of an
external data memory fetch. The addressed data is
read and written by RD and WR.
4-215
III
NEe
pPD80C35/C48,pPD48
Block Diagram
Expansion to Additional
External Memory and 110
A
Oscillator
Frequency
R
iT
Timer and
Event Counter
_
Conditional
Branch
logic
vcc
. _
Power
Supply
{
+2.5VtO. +6.0V
~
TestO
Register 0
-iNT
Register 1
_
Flag 0
Flag 1
Register 2
_
TimerFlag
_Carry
Ground
Multiplexer
_Test1
_ACC
-
ACC Bit Test
Voo Standby Power Control
Register 3
i
Register 4
g i_st_er_5_ _ _- l
\-R_e_
Register 6
Register 7
8·Level Stack
(Variable Word Length)
RESET
Voo
PROG
EA
Control and Timing
XTAL XTAL
1
2
ALE
Optional Second
Register Bank
Data Store
Low
Power
Standby
Control
Interrupt
Initialize
110
CPU/
Expander Memory
Strobe
Separate
Oscillator/
Crystal
Address
Latch
Strobe/
Cycle
Clock
Program
Memory
Enable
Single
Step
Read/Write
Strobes
Resident Data Memory
-RAM (64 x 8)
Note:
"PDSOC35 does not Include ROM.
83·002863C
Absolute Maximum Ratings
TA
=25°C
Power supply voltage, Vee
Vss - 0.3 to +10 V
Input voltage, VIN
Vss -0.3toVee +0.3V
Output voltage, Vo
Vss - 0.3 to Vee +0.3 V
Operating temperature, TOPT
Storage temperature, TSTG
-40°C to +85°C
-65°Cto +150°C
Comment: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits described in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
4-216
NEe
pPD80C35/C48,pPD48
DC Characteristics
Standard Voltage Range
Extended Voltage Range
TA= -40°C to +85°C, Vee = +5V±10%, Vss=OV
TA= -40°C to +85°C, Vee = +2.5Vto +6.0 V, Vss=OV
Limit,
Parameter
Symbol
Min
Typ
Max
Unit
Te,t
Condition,
Input voltage
low
VIL
-0.3
+0.8
V
Input voltage
high
VIH
Vcc- 2
Vcc
V
Except XTAL1,
XTAL2, RESET
VIH1
Vcc- 1
Vcc
V
RESET, XTAL1,
XTAL2
Output voltage
low
VOL
Output voltage
high
VOH
VOH1(1)
VOH2
Input current
V
10L =2.0mA
2.4
V
Bus, RD, WR,
PSEN, ALE, PROG,
TO; 10H= -100J,iA
2.4
V
10H= -5J,iA (type
0) port 1, port 2
2.4
V
10H= -50J,iA
(type 1) port 1,
port 2
V
All outputs,
10H= -0.2J,iA
+0.45
Vcc- 0.5
-15
IILP(1)
IILC
-40
J,iA
Port 1, port 2;
VIN~VIL (type 0)
-500
J,iA
Port 1, port 2;
VIN~VIL (type 1)
-40
/AA
Limit,
Parameter
Output leakage
current
±1
IU1
VIL
-0.3
Input voltage
high
VIH
0. 7Vcc
VIH1
0. 8Vcc
Max
Unit
+0.18Vcc V
Vec
V
Except XTAL1,
XTAL2
Vec
V
XTAL1, XTAL2
+0.45
V
10L =1.0 mA
VOL
Output voltage
high
VOH
0. 75Vcc
V
Bus, RD, WR,
PSEN, ALE, PROG,
TO; 10H= -100 J,iA
VOH1
O.7Vcc
V
All other outputs;
10H= -1 J,iA (type
0) port 1, port 2
O.7Vcc
V
All other outputs;
10H = -10 J,iA (type
1) port 1, port 2
Input current
IILP
-15
-40
J,iA
J,iA
EA; VSS~VIN~
Vcc
ILO
±1
J,iA
VSs~VO~VCC
High impedance,
bus, TO
0.4
4
Icc
VCCOR
2.0
0.8
mA
Halt mode
tCy=2.5/As
20
J,iA
Stop mode
(Note 2)
8
mA
tCy=2.5/As
V
Port 1, port 2;
VIN~VIL (type
0)
-500
J,iA
Port 1, port 2;
VIN~VIL (type 1)
IlL
-40
J,iA
IU1
±1
J,iA
SS, RESET; VIN~
VIL
T1, INT, Vss
C2
IC1-C21 ~ 20pF
For example, C1 = 30 pF, and C2 = 10 pF.
Values of C1 and C2 do not include stray capacitance.
C'= C+3Cpp
2
83-OO2876A
Note:
Cpp = 5 -10pF. Pin to pin capacitance should be approximately 20pF,
Including stray capacitance.
83·002875A
4-222
As the crystal frequency is lowered, there is an equivalent reduction in series resistance (R). As the
temperature of the crystal is lowered, R is increased.
Due to this relationship, it becomes difficult to stabilize
oscillation when there is low power supply voltage.
When Vee is less than 2.7 V and the oscillator frequency
is 3 M Hz or less, TA (ambient temperature) should not be
less than -10°C.
t'tIEC
Figure 8.
pPD80C35/C48,pPD48
External Clock Frequency Reference Circuit
Figure 9.
Major Input and Output Signals
Vee
Port 1
XTAL{=
~
2
---,...,-1
.....
>0--..-_-=-1[
~
XTALl
iij
0
!i!
c
'S.
Open
---2.(
Port 2
Read
Write
~~~lbl~m Store
Address Latch
Enable
XTAL2
Port Expander
Strobe
Bus
Note:
A minimum voltage of Vee -1 is required for XTAL1 to go HIGH.
83-002878A
83-002877A
Instruction Set
Instruction Set Symbol Definitions
Symbol
Description
A
Accumulator
AC
addr
Stack pOinter
Auxiliary carry flag
T
Timer
Program or data memory address (ao-a?) or
(aO-a10)
TF
Timer flag
BS
Bank switch
BUS
Bus
ClK
Clock
Counter
DBF
FO, F1
INT
8-bit binary data (do-d?)
Pp
PSW
Rr
#
@
Flag 0, flag 1
Interrupt pin
Test 0, test 1pin
, Prefix for immediate data
Prefix for indirect address
Indicates the hex number corresponding to the
accumulator bit or page number specified in the
operand
(x)
((x))
Contents of RAM
Contents of memory location addressed by (x)
Transfer direction, result
Memory bank flip-flop
Indicates the hex number of the specified register
or port
PC
TO, T1
Carry flag
CNT
data
Description
SP
Accumulator bit (b=0-7)
C
Symbol
AND
OR
EXOR
logical product (logical AND)
logical sum (logical OR)
Exclusive-DR
Complement
Program counter
Port 1, port 2, or ports 4-7 (p=1, 2 or 4-7)
Program status word
Register (r=0-7)
4-223
~
I
I\)
I\)
Instruction Set (cont)
1:::
~
Mnemonic
Function
Description
ADDA, # data
(A) -
Adds immediate data do-d7 to the accumulator. Sets or clears both
carry flags. (Note 2)
ADDA, Rr
(A) - (A) + (Rr)
r = 0-7
Adds the contents of register Rr to the accumulator. Sets or clears
both carry flags. (Note 2)
ADDA,@Rr
(A) - (A) + ((Rr))
r = 0-1
Hex
Code
Operation Code
D7
De
Ds
D4
D3
D2
D1
Do
03
0
d7
0
d6
0
d5
0
d4
0
d3
0
d2
1
dl
1
do
6n(4)
0
1
1
0
Adds the contents of the internal data memory location specified by 6n( 4)
bits 0-5 of register Rr to the accumulator. Sets or clears both carry
flags. (Note 2)
0
0
0
0
Adds, with carry, immediate data do-d7 to the accumulator. Sets
or clears both carry flags. (Note 2)
13
0
d7
0
d6
0
d5
1
1
Cycles
Bytes
0
Accumulator
(A) + data
0
ADDCA, Rr
(A) - (A) + (C) + (Rr)
r = 0-7
Adds, with carry, the contents of register Rr to the accumulator.
Sets or clears both carry flags. (Note 2)
7n(4)
0
ADDCA,@Rr
(A) - (A) + (C) + ((Rr))
r = 0-1
Adds, with carry, the contents of the internal data memory location
specified by bits 0-5 of register Rr, to the accumulator. Sets or
clears both carry flags. (Note 2)
7n(4)
0
ANLA, # data
(A) -
Takes the logical product (logical AND) of immediate data do-d7
and the contents of the accumulator, and stores the result in the
accumulator.
53
0
d7
ANLA, Rr
(A) - (A) AND (Rr)
r = 0-7
Takes the logical product (logical AND) of the contents of register
Rr and the accumulator, and stores the result in the accumulator.
5n(4)
0
0
ANLA, @Rr
(A) - (A) AND ((Rr))
r = 0-1
Takes the logical product (logical AND) of the contents of the
internal data memory location specified by bits 0-5 of register Rr,
and the accumulator, and stores the result in the accumulator.
5n(4)
0
0
CPLA
(A)-(A)
Takes the complement of the contents of the accumulator.
37
0
0
CLRA
(A)-O
Clears the contents of the accumulator.
27
0
0
Converts the contents of the accumulator to BCD. Sets or clears
the carry flags. When the lower 4 bits (Ao-A3) are greater than 9,
or if the auxiliary carry flag has been set, adds 6 to (Ao-A3). When
the upper 4 bits (A4-A7) are greater than 9 or if the carry flag (C)
has been set, adds 6 to (A4-A7). If an overflow occurs at this
point, Cis set. (Note 2)
57
0
DAA
1
d6
DECA
(A)-(A) -1
Decrements the contents of the accumulator by 1.
07
0
0
(A)-(A)+1
Increments the contents of the accumulator by 1.
17
0
ORLA, # data
(A) -
Takes the logical sum (logical OR) of immediate data do-d7 and the
contents of the accumulator, and stores the result in the
accumulator.
43
0
d7
0
1
d6
ORLA, Rr
(A) -
(A) OR (Rr) r
i I
= 0-7
Takes the logical sum (logical OR) of register Rr and the contents of 4n(4)
the accumulator, and stores the result in the accumulator.
0
0
d5
1
d4
W
ell
..tl
.."a
CD
0
d3
0
d2
1
dl
1
do
1
1
d4
CD
0
0
0
0
d3
0
d2
1
dl
1
do
2
1
2
0
0
0
1
0
0
INCA
(A) OR data_
n
w
(A) -
(A) AND data
2
1:::
ADDC A, # data
(A) + (C) + data
"a
CD
0
0
0
0
0
1
0
1
1
1
0
d5
0
d4
0
d3
0
d2
1
dl
1
0
0
do
~
~
Instruction Set (cont)
Mnemonic
Operation Code
Hex
Code
D7
4n(4)
0
Function
Description
ORLA, @Rr
(A) - (A) OR ((Rr))
r = 0-1
Takes the logical sum (logical OR) of the contents of the internal
data memory location specified by bits 0-5 in register Rr, and the
contents of the accumulator, and stores the result in the
accumulator.
RLA
(AN + 1) - (AN)
(AD) - (A7) N = 0-6
Rotates the contents of the accumulator one bit to the left. The
MSB is rotated into the LSB.
E7
RLCA
(AN + 1) - (AN); N = 0-6
(Ao)-(C)
(C)-(A7)
Rotates the contents of the accumulator one bit to the left through
carry.
F7
RRA
(AN) - (AN + 1); N = 0-6
(A7) -(AD)
Rotates the contents of the accumulator one bit to the right. The
LSB is rotated into the MSB.
77
RRCA
(AN) - (AN + 1); N = 0-6
(A7)-(C)
(C)-(Ao)
Rotates the contents of the accumulator one bit to the right through
carry.
67
SWAP A
(A4-A7)- (Ao-A3)
Exchanges the contents of the lower 4 bits of the accumulator with
the upper 4 bits of the accumulator.
47
0
XRLA, # data
(A) -
Takes the exclusive OR of immediate data do-d7 and the contents
of the accumulator, and stores the result in the accumulator.
D3
1
d7
XRLA, Rr
(A) - (A) XOR (Rr)
r = 0-7
Takes the exclusive OR of the contents of register Rr and the
accumulator, and stores the result in the accumulator.
Dn(4)
XRLA,@Rr
(A) - (A) XOR ((Rr))
r = 0-1
Takes the exclusive OR of the contents of the location in data
memory specified by bits 0-5 in register Rr, and the accumulator,
and stores the result in the accumulator.
Dn(4)
(Rr) - (Rr) - 1; r = 0-7
If(Rr)i-O;
(PCa-PC7) - addr
Decrements the contents of register Rr by 1, and if the result is not
equal to 0, jumps to the address indicated by aa-a7'
En
(PCa-PC7) - addr if b = 1
(PC) = (PC) + 2 if b = 0
Jumps to the address specified by aO-a7 if the bit in the
accumulator specified by bo-b2 is set.
D6
Ds
D4
D1
Do
0
d2
1
d1
1
da
0
0
0
r
a1
r
aa
a1
aD
D3
D2
Accumulator (cont)
(A) XOR data
0
0
0
JBb addr
Bytes
~
~
0
0
0
0
0
0
1
d6
0
ds
1
d4
0
d3
1
0
1
1
0
Branch
DJNZ Rr, addr
Cycles
1::
x2(6)
a7
a6
as
a4
a3
r
a2
b2
a7
b1
a6
ba
a5
a4
0
a3
0
a2
"a
CD
0
n
W
CII
Ci,.
..1::
CD
",.a
~
J\)
J\)
CD
CJ1
II1II
~
I
I\)
I\)
Instruction Set (cont)
Mnemonic
Hex
Code
Operation Code
Function
Description
(PCo-PC?) - addr if C = 1
(PC) - (PC) + 2 if C = 0
Jumps to the address specified by ao-a? if the carry flag is set.
JFO addr
(PCo-PC?) - addr if FO = 1
(PC) - (PC) + 2 if FO = 0
Jumps to the address specified by aO-a? if FO is set.
B6
JF1 addr
(PCo-PC?) - addr if F1 = 1
(PC) - (PC) + 2 if F1 = 0
Jumps to theaddress specified by aO-a? if F1 is set.
76
0
a?
a6
JMP addr
(PCS-PC10) - (addrs-addr10) Jumps directly to the address specified by aO-a10 and the DBF.
(PCo-PC?) - (addro-addr?)
(PC11) - DBF
x4(6)
a10
a?
ag
a6
D7
De
Ds
D4
D3
D2
D1
Do
a?
a6
a5
a4
0
a3
a2
a1
ao
a?
0
a6
a4
a3
1
a2
a1
0
ao
a5
a4
0
a3
1
a2
a1
0
ao
as
a5
0
a4
0
a3
a2
0
a1
0
ao
Branch (cont)
JC addr
JMPP@A
(PCo-PC?) -
JNCaddr
F6
Replaces the lower 8 bits of the program counter with the contents
of program memory specified by the contents of the accumulator,
producing a jump to the specified address within the current page.
B3
(PCo-PC?) - addr if C = 0
(PC) - (PC) + 2 if C = 1
Jumps to the address specified by aO-a? if the carry flag is not set.
E6
(PCo-PC?) - addr if I = 0
(PC) - (PC) + 2 if I = 1
Jumps to the address specified by aO-a? if the interrupt flag is not
set.
86
(PCo-PC?) - addr if TO = 0
(PC) - (PC) + 2 if TO = 1
Jumps to the address specified by aO-a? if test 0 is low.
26
(PCo-PC?) - addr if T1 = 0
(PC) - (PC) + 2 ifT1 = 1
Jumps to the address specified by aO-a? if test 1 is low.
JNZaddr
(PCo-PC?) - addr if A 0
(PC) - (PC) + 2 if A = 0
Jumps to the address specified by aO-a? if the contents of the
accumulator are not equal to O.
96
JTF addr
(PCo-PC?) - addr if TF == 1
(PC) - (PC) + 2 ifTF = 0
Jumps to the address specified by aO-a? if the timer flag is set.
The timer flag is cleared after the instruction is executed.
16
(PCo-PC?) - addr if TO = 1
(PC) - (PC) + 2 if TO = 0
Jumps to the address specified by aO-a? if test 0 is high.
36
(PCo-PC?) - addr if T1 = 1
(PC) - (PC) + 2 ifT1 = 0
Jumps to the address specified byao-a? if test 1 is high.
(PCo-PC?) - addr if A = 0
(PC) - (PC) + 2 if A = 1
Jump to the address specified byao-a? if the contents of the
accumulator are equal to O.
JNI addr
JNTO addr
JNT1 addr
JTO addr
JT1 addr
JZ
,.a
1:::
0'>
((A))
'*
0
0
a6
a5
0
a4
0
a3
a2
a1
0
ao
a?
0
a6
a5
a4
a3
a2
a1
0
ao
0
a?
a6
1
a5
0
a4
0
a3
a2
a1
0
ao
a?
a6
0
a5
a4
0
a3
a2
a1
0
ao
a?
a6
a5
a4
a3
a2
a1
ao
a?
0
a6
0
a5
1
a4
0
a3
1
a2
1
a1
0
ao
0
a?
0
a6
a5
a4
a3
a2
a1
0
ao
0
a?
a6
0
a5
a4
a3
a2
a1
ao
a6
0
a5
a4
0
a3
a2
a1
0
ao
C6
a?
Bytes
CD
0
nW
en
~
!'J
,.
,.a
,.
1:::
CD
a?
46
56
a5
Cycles
~
0
Instruction Set (cont)
Mnemonic
Function
Hex
Code
Description
Operation Code
D7
De
Ds
D4
D3
D2
D1
0
0
0
0
0
Do
Control
EN I
Enables external interrupts. When external interrupts are enabled,
a low-level input to the INT pin causes the processor to vector to
the interrupt service routine.
05
0
0
DIS I
Disables external interrupts. When external interrupts are
disabled, low-level inputs to the INT pin have no effect on program
execution.
15
0
0
Enables clock output to pin TO.
75
SEL MBO
ENTO CLK
(DBF) -0
Clears the memory bank flip-flop, selecting program memory bank
o(program memory addresses 0-2047(10)). Clears PC11 after the
next JMP or CALL instruction.
E5
SEL MB1
(DBF)-1
Sets the memory bank flip-flop, selecting program memory bank 1
(program memory addresses 2048-4095(10) ). Sets PC11 after the
next JMP or CALL instruction.
F5
SEL RBO
(BS)-O
Selects data memory bank 0 by clearing bit 4 (bank switch) of the
PSW. Specifies data memory addresses 0-7(10) as registers 0-7 of
data memory bank O.
C5
SEL RB1
(BS)-1
Selects data memory bank 1 by setting bit 4 (bank switch) of the
PSW. Specifies data memory 24-31(10) as registers 0-7 of data
memory bank 1.
D5
Initiates halt mode.
01
0
23
0
d7
0
d6
1
d5
0
d4
0
d3
1
1
1
1
1
HALT
Bytes
~
~
0
0
0
0
Cycles
0
0
0
0
0
0
0
0
0
Data Moves
MOV A, # data
(A) -data
Moves immediate data do-d7 into the accumulator.
MOV A, Rr
(A) -
(Rr); r = 0-7
Moves the contents of register Rr into the accumulator.
Fn(4)
MOVA,@Rr
(A) -
((Rr)); r
Moves the contents of internal data memory specified by bits 0-5
in register Rr, into the accumulator.
Fn(4)
MOVA, PSW
(A)-(PSW)
MOV Rr, # data
(Rr) -
= 0-1
Moves the contents of the program status word into the
accumulator.
data; r
= 0-7
0
C7
0
d7
MOV Rr, A
(Rr) -
MOV@Rr,A
((Rr)) -
MOV @ Rr, # data ((Rr)) -
(A); r
= 0-7
(A); r = 0-1
data; r
= 0-1
0
r
d1
0
1
0
0
0
0
d3
0
d2
0
d1
0
Moves immediate data do-d7 into the data memory location
specified by bits 0-5 in register Rr.
Bn(4)
0
d6
1
d5
1
d4
d3
r
d2
1
0
An(4)
D
CD
0
d4
An(4)
"
0
d5
Moves the contents of the accumulator into the data memory
location specified by bits 0-5 in register Rr.
1
do
'l:::
d6
Moves the contents of the accumulator into register Rr.
1
d7
1
d1
0
Bn(4)
Moves immediate data do-d7 into register Rr.
0
d2
r
do
nW
UI
(:)
~
..'l:::
CD
r
do
"
D
~
~
N
'"
CD
-.J
~
~
I
I\)
I\)
1::
Instruction Set (cont)
e»
Mnemonic
Hex
Code
Operation Code
Function
D!tscrlptlon
MOV PSW, A
(PSW)-(A)
Moves the contents of the accumulator into the program status
word.
07
MOVPA,@A
(PCO-PCl) - (A)
(A)-((PC))
Moves the contents of the program memory location specified by
PCS-PC11 concatenated with the contents of the accumulator, into
the accumulator.
A3
MOVP3A,@A
(PCO-PCl) - (A)
(PCS-PC11) - 001
(A)-((PC))
Moves the contents of the program memory location specified by
0011 (PCS-PC11, page 3 of program memory bank 0) and the
contents of the accumulator, into the accumulator.
E3
MOVXA,@R
(A) -
Moves the contents of the external data memory location specified
by register Rr, into the accumulator.
8n(4)
0
0
MOVX@R,A
((Rr)) -
Moves the contents of the accumulator into the external data
memory location specified by register Rr.
9n(4)
0
0
XCH A, Rr
(A)- (Rr); r = 0-7
Exchanges the contents of the accumulator and register Rr.
2n(4)
XCH A, @Rr
(A)- ((Rr)); r
Exchanges the contents of the accumulator and the contents of the
data memory location specified by bits 0-5 in register Rr.
2n(4)
XCHOA,@Rr
(Ao-A3)- ((Rr))o-((Rr)13;
r = 0-1
Exchanges the contents of the lower 4 bits of the accumulator with 3n(4)
the contents of the lower 4 bits of the internal data memory location
specified by bits 0-5 in register Rr.
CPLC
(C)-(C)
Takes the complement of the carry bit.
A7
0
1
CPL FO
(FO)-(FO)
Takes the complement of flag O.
95
0
0
CPL F1
(F1)-(F1)
Takes the complement of flag 1.
85
0
CLR C
(C)-O
Clears the carry bit.
97
0
0
1
0
1
CLR FO
(FO)-O
Clears flag O.
85
0
0
0
0
0
CLR F1
(F1)-0
Clears flag 1.
A5
0
0
0
0
D7
De
Ds
D4
D3
D2
D1
Do
Cycles
Bytes
"ma
0
Data Moves (cont)
((Rr)); r = 0-1
(A); r
= 0-1
= 0-1
0
0
0
nW
0
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
en
...
t;
CD
1::
.."
a
CD
Flags
0
0
1
0
0
0
0
~
~
Instruction Set (cont)
Mnemonic
Function
Hex
Code
Description
Operation Code
D7
De
98
1
d7
0
d6
Ds
D4
D3
D2
D1
Do
0
d2
0
d1
0
do
P
d1
P
do
Input! Output
ANlBUS,
# data
(bus) -
d5
d4
1
d3
ANl Pp,
# data
(Pp) - (Pp) AND data;
p = 1-2
Takes the logical AND of the contents of designated port Pp and
immediate data do-d7, and sends the result to port Pp for output.
9n(5)
1
d7
0
d6
0
d5
1
d4
1
d3
0
d2
ANlD Pp, A
(Pp) - (Pp) AND (Ao-A3);
P = 4-7
Takes the logical AND of the contents of designated port Pp and the 9n(5)
lower 4 bits of the accumulator, and sends the result to port Pp for
output.
1
0
0
1
1
1
IN A, Pp
(A) -
(Pp); p = 1-2
loads the accumulator with the contents of designated port Pp.
On(5)
0
0
0
0
0
P
INSA, BUS
(A) -
(bus)
loads the contents of the bus into the accumulator on the rising
edge of RD.
08
0
0
0
0
0
MOVDA, Pp
(Ao-A3) (A4-A7) -
Moves the contents of designated port Pp to the lower 4 bits of the
accumulator, and clears the upper 4 bits.
On(5)
0
MOVD Pp, A
(Pp) -
Moves the lower 4 bits of the accumulator to designated port Pp.
The upper 4 bits of the accumulator are not changed.
3n(5)
ORl BUS,
# data
(bus) -
ORlD Pp, A
(bus) AND data
(Pp); p = 4-7
0
(Ao-A3); P = 4-7
Takes the logical AND of the contents of the bus and immediate
data do-d7, and sends the result to the bus.
Takes the logical OR of the contents of the bus and immediate data
do-d7, and sends the result to the bus.
88
(Pp) - (Pp) OR (Ao-A3);
P = 4-7
Takes the logical OR of the contents of designated port Pp and the
lower 4 bits of the accumulator, and sends the result to port Pp for
output.
8n(5)
ORl Pp,
# data
(Pp) - (Pp) OR data;
p = 1-2
Takes the logical OR of the contents of designated port Pp and
immediate data do-d7, and sends the result to port Pp for output.
9n(5)
OUTl BUS, A
(bus) -
latches the contents of the accumulator onto the bus on the rising
edgeofWR.
Note: Never use the OUTl BUS instruction when using external
program memory, as this will permanently latch the bus.
02
OUTl Pp,A
(Pp) -
(bus) OR data
(A)
(A); P = 1-2
0
0
Bytes
~
~
0
p
0
1
d7
Cycles
p
0
d6
0
d5
0
d4
1
d3
0
d2
0
d1
0
do
0
0
0
1
1
P
P
1
d7
0
d6
0
d5
0
d4
1
d3
0
d2
P
d1
P
do
0
0
0
0
0
0
1
0
1:::
latches the contents of the accumulator into designated port Pp for 3n(5)
output.
0
0
0
p
"am
0
n
Registers
= 0-7
= 0-7
DEC Rr
(Rr) -
(Rr) -1; r
INC Rr
(Rr) -
(Rr) + 1; r
INC@Rr
((Rr))-((Rr)) +1;
r = 0-1
Decrements the contents of register Rr by 1.
Cn(4)
Increments the contents of register Rr by 1.
1n(4)
0
0
0
Increments by 1the contents of the data memory location specified
by bits 0-5 in register Rr.
1n(4)
0
0
0
W
0
CII
0
0
ti,..
..1:::m
"a,..m
~
I
f\)
f\)
<0
~
.j:>..
I
a
Mnemonic
""'Function
Description
He.
Code
Operation Code
D7
D6
D5
D4
D3
D2
D1
DO
am
a7
ag
a6
as
a5
a4
0
a3
a2
0
a1
0
aO
Subroutine
CALL addr
RET
RETR
((SP)) - (PC), (PSW4-PSW7)
(SP) - (SP) + 1
(PC8-PC10) - (addrs-addr10)
(PCO-PC7) - (addro-addr7)
(PC11) -DBF
Stores the contents of the program counter and the upper 4 bits of
the PSW in the address indicated by the stack pOinter, and
increments the contents of the stack pOinter, calling the subroutine
specified by address ao-am and the DBF.
x4(6)
(SP) (PC) -
Decrements the contents of the stack pOinter by 1and stores, in
the program counter, the contents of the location specified by the
stack pOinter, executing a return from subroutine without restoring
the PSW.
83
Decrements the contents of the stack pointer by 1and stores, in
the program counter, the contents of the upper 4 bits of the PSW
and the contents of the location specified by the stack pOinter,
executing a return from subroutine with restoration of the PSW.
93
Enables internal interrupt of timer I event counter. If an overflow
condition occurs, then an interrupt will be generated.
25
0
Disables internal interrupt of timer I event counter.
35
a
(SP) - 1
((SP))
(SP) - (SP) - 1
(PC) -((SP))
(PSW4-PSW7) - ((SP))
,.D
1::
Instruction Set (cont)
I\)
w
Cycles
Bytes
CD
0
nw
(II
ts
.,..
0
0
0
0
0
...CD
,.
1:::
0
0
D
0
~
CD
Timer I Counter
EN TCNTI
DIS TCNTI
0
0
a
0
MOVA, T
(A)-(T)
Moves the contents of the timer I counter into the accumulator.
MOVT, A
(T)-(A)
Moves the contents of the accumulator into the timer I counter.
62
0
STOP TCNT
Stops the operation of the timer I event counter.
65
0
0
0
STRTCNT
Starts the event counter operation of the timer I counter when T1
changes from a low-level input to a high-level input.
45
0
0
0
STRTT
Starts the timer operation of the timer I counter. The timer is
incremented every 32 machine cycles.
55
0
0
Uses one machine cycle without performing any operation.
00
42
0
0
0
0
0
0
0
Miscellaneous
NOP
0
0
0
0
0
0
~
~
Instruction Set (cont)
Note:
(1) Binary operation code designations rand p represent encoded values or the lowest-order bit value of specified registers and ports, respectively.
(2) Execution of the ADD, ADDC, and DA instructions affect the carry flags, which are not shown in the respective function equations. These instructions set the carry flags when there is an
overflow in the accumulator (the auxiliary carry flag is set when there is an overflow of bit 3 of the accumulator) and clear the carry flags when there is no overflow. Flags that are specifically
addressed by flag instructions are shown in the function equations for those instructions.
(3) References to addresses and data are specified in byte 1 and/or 2 in the opcode of the corresponding instruction.
(4) The hex value of n for specific
a) Direct addressing
RO: n
8
R2: n
A
R3: n = B
Rt n = 9
b) Indirect addressing
@ RO: n
0
@ Rt n
=
=
=
~
~
registers is as follows:
=
R4: n
C
RS: n = D
=
R6: n
E
R7: n = F
=1
(S) The hex value of n for specific ports is as follows:
P1: n
9
P4: n
C
P6: n
E
P2:n = A
PS: n = D
P7: n = F
=
=
=
(6) The hex value of x for specific accumulator or address bits is as follows:
a) JBb instruction
Bo: x = 1
B2: x = S
B4 :x = 9
B6:X = D
B7:x = F
Bf x = 3
B3: x = 7
B5: x = B
b) JMP instruction
Page 4: x = 8
Page 6: x = C
Page 2: x = 4
Page 0: x = 0
Page 3: x = 6
PageS: x = A
Paget x = 2
Page 7: x = E
c) CALL instruction
Page 2: x = S
Page 0: x = 1
Page 4: x = 9
Page 6: x = D
Page 1: x = 3
PageS: x = B
Page 7: x = F
Page 3: x = 7
't::
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C
Q)
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III
NEe
pPD80C35/C48,pPD48
Operating Characteristics
Port Control Hold After PROG, tpc Max (J.lPD80C48),
and Address to Output Delay,
tACC Min ~PD82C43), VS. Supply Voltage
Supply Current VS. Oscillation Frequency
I.,
1
i
\
. . . . . . . . . . . . ::::~:. ~--l--~
~
0.1
l
0.05
1-----+--:-:-:...
..........
..........................
0.03
VCC=3V
~
........... "-
~
................... ~
...........
0.2
tpcMax
ICC1......,......- - - ! - - - I
t----+--..,.,.,..
.......... ,......:...."-..-.._..+-_ _ _-+-_ _ _ _+-_-1
0.1
~PD82C43:
~Mln
~PD~
u ::::::::::::::::.. ...........-............ ·................fo;-a-=x......- - - ! - - - I
d
-a
IC~
t----+--____+----,;"1' ...:.4Max _ _ _l-_~
I
~~
u.
0.5
1
Oscillation Frequency, I (MHz), (I = 15 tCY)
4
5
Supply Voltage, Vcc (V)
Current Consumption as a Function of Temperature Normal Operating Mode
Cycle Time VS. Supply Voltage
200
-
100
10
50
'iii'
1=6MHz
Vcc=5.5V
~ r-
Operation Guarantee
Area
,3.
>
~ 20
t
j::
!
10
...........
~
,....
ICC1
'""" ~
Halt Mode
~~
"
Supply Voltage, Vcc (V)
25
Temperature, TA(OC)
Supply Current VS. Oscillation Frequency
Current Consumption as a Function of Operating
Frequency - Normal Operating Mode
-40
......J...........
I
ICC
~
ICC~
Max
<"
g
1i
..............
:B
j
i
0.5 ••••••••••••••• ••••••••
J!
•................
...... • ••••••
10
8
k'"
........-4lYP
1
./
1
..---ICC--V
Typ--~--II--~
t..-
..-
--0-....
0.11---•••-••-+.
VCC=,5.5V
I
&l
0.2
0.5
Oscillation Frequency, I(MHz),(I = 151tCY)
V
Max.,...-
/
,J.
.. . .~
...:...:. .-...-1.f.....-•••-••-..-••-•••+.....----+-----I---+----1
..............
0.05
0.1
VCC=5.5V
V
V,..:.:...-..-...-...+·-···-···=··~.q.---Ic-f-~I---fv--+-----I
...............
0.2
•••••
..........
85
1/
0.2
V
j..ool.-
V
j..ool.-
V
/'
K
V
i ....
0.5
OSCillator Frequency (MHz)
Note: External oscillation Is lor lrequency less than 1 MHz.
Internal oscillation requires more power.
4-232
t\'EC
pPD80C35/C48, pPD48
Operating Characteristics (cont)
Output High Current VS. Output High Voltage
Output High Current VS. Output High Voltage
-15.-------,-------,-------,--------,-------,
Vee=4.5V
1:z:
9-10~------+_------+_~~--~------_+------~
i'
§
u
.c
Cl
:t:
[
:;
-5~------+_------+_~~--~--~--_+------_1
o
2
Output High Voltage, VOH (V)
Output High Voltage, VOH1 (V)
Output High Current VS. Supply Voltage
c
~
:z:
9 -100 -10
- 0.4 . - - - - - - - , - - - - - - - - , - - - - - - -......------:V::-O-H~2-=:-:-Ve-e---::O-::.5-:-:-1V
c
~
:z:
9
V
/
I
u
.c
9
:z:
I-
Output High Current VS. Supply Voltage
v
-150 -15
-SO-5
o
co
JJ
'i
~
3
g
-0.2 ~------+_------+_-------t---r---+------~
:z:
[
:;
o
VOH1=2.4V
6
I
L_~'~--L-------L-----~------~~----~
Supply Voltage, Vee (V)
I
Supply Voltage, Vee (V)
Output Low Current VS. Output Low Voltage
Output Low Current VS. Supply Voltage
3
V
2
c:
~
u
~
[
1
/
V
V
/"
...J
9
~
82~--------------~~~------------------~
~
l-
:;
o
c
.s
.................
e
t I~
VOL = 0.45 V
Supply Voltage, Vee (V)
~__________________~_____________V_e~e_=_4_.5~V
0.5
Output Low Voltage, VOL (V)
1",,<,>
1.0
4-233
t-{EC
pPD80C35/C48,pPD48
Operating Characteristics (cont)
Current Consumption as a Function
of Temperature - Stop Mode
~r-----r-----+---r-------~~--~
VCC=5.5V
-40
4':'234
25
Temperature, TA (OC)
85
I
NEe
NEe Electronics Inc.
Description
The NEC /JPD8039HL, /JPD8049H and the /JPD8749H are
high performance, single component, 8-bit parallel
microcomputers using n-channel silicon gate MOS
technology. The processors differ only in their internal
program memory options: the /JPD8049H has 2K x 8
bytes of mask ROM, the /JPD8749H has 2K x 8 of UV
erasable EPROM and the /JPD8039H L has external
program memory.
The /JPD8049H family functions efficiently in control as
well as arithmetic applications. The powerful
instruction set eases bit handling applications and
provides facilities for binary and BCD arithmetic.
Standard logic functions implementation is facilitated
by the large variety of branch and table look-up
instructions. The instruction set is comprised of 1 and 2
byte instructions, most of which are single-byte. The
instruction set requires only 1 or 2 cycles per instruction
with over 50 percent of the instructions single-cycle.
The /JPD8049H family of microprocessors will function
as stand-alone microcomputers. Their functions can
easily be expanded using standard 8080A/8085A
peripherals and memories. The /JPD8039HL is intended
for applications using external program memory only. It
contains all the features of the /JPD8049H except for the
internal ROM. The external program memory can be
implemented using standard 8080A/8085A memory
products. The /JPD8049H contains the following
functions usually found in external peripheral devices:
2048 x 8 bits of mask ROM program memory; 128 x 8
bits of RAM data memory; 271/0 lines; an 8-bit interval
timer/event counter; and oscillator and clock circuitry.
The /JPD8749H differs from the /JPD8049H in its
2048 x 8-bit UV erasable EPROM program memory
instead of the mask ROM memory. It is useful in
preproduction or prototype applications where the
software design has not yet been finalized or in system
designs whose quantities do not require a maskROM.
~PDa039HL/49H,~PDa749H
HIGH·SPEED, a·BIT, SINGLE·CHIP
HMOS MICROCOMPUTERS
o
o
o
o
o
o
o
External and internal interrupts
96 instructions: 70 percent single byte
271/0 lines
Internal clock generator
Expandable with 8080A/8085A peripherals
HMOS silicon gate technology
Single +5 V ± 10 percent power supply
Ordering Information
Part
Number
Package Type
Max Frequency
of Operation
JJPD8039HLC
40-pin plastic DIP
11 MHz
JJPD8049HC
40-pin plastic DIP
11 MHz
JJPD8749HC
40-pin plastic DIP
11 MHz
JJPD8749HD
40-pin cerdip (Note 1)
11 MHz
Note:
(1) With quartz window.
Pin Configuration
Vee
T1
P27
\VA
ALE
DBo
DBl
DB2
DB3
Voo
DB4
PROG
P23
P22
83·002879A
Features
o
o
o
o
o
o
High performance 11 MHz operation
Fully compatible with industry standard
8039/8049/8749
Pin compatible with the /JPD8048/8748
1.36/Js cycle time. All instructions 1 or 2 bytes
Programmable interval timer/event counter
2K x 8 bytes of ROM, 128 x 8 bytes of RAM
4-235
NEe
~PD8039HL/49H,~PD8749H
SS (Single Step)
Pin Identification
Function
No.
Symbol
1
TO
Test 0 input/output
2
XTAL1
Crystal 1input
3
XTAL2
Crystal 2 input
4
RESET
Reset input
5
SS
Single step input
6
INT
Interrupt input
7
EA
External access input
8
RD
Read output
9
PSEN
Program store enable output
10
WR
Write output
Address latch enable output
An active low on SS, together with ALE, causes the
processor to execute the program one step at a time.
INT (Interrupt)
An active low on INT starts an interrupt if interrupts are
enabled. A reset disables an interrupt.INT can be tested
with the JNI instruction and, depending on the resuits a
jump to the specified address can occur.
'
EA (External Access)
An active high on EA disables internal program memory
and. fetches and accesses external program memory.
EA IS used for system testing and debugging.
11
ALE
12-19
DBO-DB?
Bidirectional data bus
RD(Read)
20
Vss
Ground
21-24
P20-P2?
Quasi-bidirectional Port 2
25,35-38
PRaG
Program output
26
Voo
RAM power supply
RD will pulse low wh~the processor performs a bus
read. An active low on RD enables data onto the processor bus from a peripheral device and functions as a read
strobe for external data memory.
27-34
P10-P1?
Quasi-bidirectional Port 1
39
T1
Test 1input
40
Vee
Primary power supply
WR(Write)
WR will pulse low when the processor performs a bus
write. WR can also function as a write,strobe for external data memory.
Pin Functions
XTAL 1(Crystal 1)
XTAL1 is one side of the crystal, LC, or external frequency source (non-TTL-compatible VIH).
XTAL 2 (Crystal 2)
XTAL2 is the other side of the crystal or frequency
source. For external sources, XTAL2 must be driven with
the logical complement of the XTAL1 input.
TO (Test 0)
TO is the testable input using conditional transfer function.s JTO and IN!O. The internal state clock (CLK) is
available to TO uSing the ENTO CLK instruction. TO can
also be used during programming as a testable flag.
T1 (Test 1)
T1 is the testable input using conditional transfer functions JT1 and JNT1. T1 can be made the counterltimer
input using the STRT CNT instruction.
RESET (Reset)
An active low on RESET initializes the processor. RESET is also used for PROM programming verification
and power-down (non-TTL compatible VIH).
4-236
PSEN (Program Store Enable)
PSEN becomes active only during an external memory
fetch. (Active low).
.
ALE (Address Latch Enable)
ALE occurs at each cycle. ALE can also be used as a
clock output. The falling edge of ALE addresses external data memory or external program memory.
DBO-DB7 (Data Bus)
DBo-DB7 is a bidirectional port. Synchronous reads and
writes can be performed on this port using RD and WR
strobes. The contents of the DBa-DB7 bus can be
latched in a static mode.
During an external memory fetch, DBo-DB7 output the
low order eight bits of the memory address. PSEN
fetches the instruction. DBa-DB7 also output the address of an external data memory fetch. The addressed
data is controlled by ALE, RD, and WR.
P10-P17 (Port 1)
P10-P17 is an 8-bit quasi-bidirectional port.
NEe
tJPD8039HL149H, tJPD8749H
P20- P27 (Port 2)
Vee (RAM Power Supply)
P2o-P27 is an 8-bit quasi-bidirectional port. P2o-P23
output the high order four bits of the address during an
external program memory fetch. P20-P23 also function
as a 4-bit I/O bus for the ~PD82C43 110 port expander.
Voo provides +5 V to the 128 x 8-bit RAM section. During normal operation, Vee must also be +5 V to provide
power to the other functions in the device. During
standby operation, Voo must remain at +5 V while Vee
is at ground potential.
PROG (Program Pulse)
PROG is used as an output pulse during a fetch when
interfacing with the ~PD82C431/0 port expander. When
the ~PD8049H is used ina stand-alone mode, PROG can
be allowed to float.
Vss (Ground)
Vss is ground potential.
Vee (Primary Power Supply)
Vee is the primary power supply. Vee is +5 V during
normal operation.
Block Diagram
Expansion to Additional
External Memory and I/O
Oscillator
Frequency
Bj
E
T'j'
Bus
Buller
and
Timer and
Event Counter
Conditional
Branch
(8)
Logic
Power
Supply
{
_
8
Latch
Port 1
_
TestO
_
Test1
- - iNT
Register 1
_
Flag 0
Flag 1
Register 2
_
Timer Flag
_Carry
VCC Program Supply
Multiplexer
Register 0
- - Voo +s V (Low Power Standby)
_ACC
-VssGround
_
ACCBitTest
Register 3
i
Register 4
I-R_eg_is_te_r_s- - - - 4
Register 6
Register 7
B-Level Stack
(Variable Word Length)
EA
Control and Timing
XTAL XTAL
1
2
ALE
Optional Second
Register Bank
Data Store
Interrupt
Initialize
PROM I
Expander
Strobe
External
Memory
Access
Oscillator I
Crystal
Address
Latch
Strobel
Cycle
Clock
Program
Memory
Enable
Single
Step
ReadlWrite
Strobes
Resident Data MemoryRAM (128 x 8)
Note: "PD8039HL does not Include ROM.
83OO288OC
4-237
~PD8039HL/49H,
NEe
f-lPD8749H
Logic Symbol
Limits
Parameter
...!.- Por:t1
XTAL{=
Read
J:
ic
Write
~
~~~bl~m Store
Address Lateh
Enable
Por:t Expander
Strobe
Bus
83-002892A
Absolute Maximum Ratings
TA = 25°C
Operating temperature. TOPT
O°C to +70°C
Storage temperature. TSTG
- 65°C to +150°C
Voltage on any pin
-0.5Vto +7.0V(Notel)
Power dissipation. Po
1.5W
Note:
(1) With respect to ground.
Min
Typ
Mal(
Test
Conditions
Unit
2.4
V
10H= -400 ",A
Output high
VOHl
voltage (RD.
WR. PSEN. ALE)
2.4
V
10H= -400 ",A
Output high
VOH2
voltage (all other
outputS)
2.4
V
10H= -40",A
±10
~
VSS ~ VIN ~ Vee
Output high
voltage (... )
Por:t2
Symbol
VOH
Input leakage
IlL
current (Tl. EA.
INT)
Input leakage
current
(Pl 0- P1 7.
P20-P27. EA.
SS)
11L1
-500
",A
Vss+ 0.45 V
~ VIN ~ Vee
Output leakage
current (BUS.
TO. high
impedance
state)
ILO
±10
~
Vee ~ VIN ~ VSS+
0.45V
10
rnA
TA=25°C
rnA
TA=25°C
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the limits
described in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliabi lity.
Power down
supply current
100
Total supply
current
100+
lee
DC Characteristics
TA=25°C±5°C, Vee = +5V±5%, Voo= +21V±O.5V
8749H only
5
80
110
85
110
8749H only
DC Programming Characteristics
TA=OOCto +70 0 C, Vee=Voo=
+5V±10%~
Vss=OV
Limits
Limits
Test
Conditions
Mal(
Unit
20.5
21.5
V
VOD program
VOOL
voltage low level
4.75
5.25
V
PROG program
voltage high
level
VPH
17.5
18.5
V
PROG voltage
low level
VPL
4.0
Vee
V
VEAH
17.5
18.5
V
~tage(~
EA program/
verify voltage
high level
RD. WR. PSEN.
ALE)
VOO high voltage 100
supply current
20.0
mA
PROG high
voltage supply
current
1.0
rnA
1.0
rnA
Parameter
Input low
voltage (All
except XTAL1.
XTAL2)
Symbol
VIL
Min
-0.5
Input high
VIH
voltage (All
except XTAL1.
XTAL2. RESET)
2.0
Input high
VIHl
voltage (XTAL1.
XTAL2. RESET)
3.8
Output low
VOL
Typ
Mal(
Unit
0.8
V
Vee
V
Vee
V
0.45
V
10L =2.0mA
Output low
voltage (All
others except
PROG)
VOL1
0.45
V
10L =2.0mA
Output low
voltage (PROG)
VOL2
0.45
V
10L =2.0mA
4-238
Parameter
VOO program
voltage high
level
Symbol
Min
VOOH
IpROG
EA high voltage lEA
supply current
Typ
Test
Conditions
NEe
~PD8039HL/49H,~PD8749H
AC Characteristics
TA=OOCto +70°C, vee=voo= +5V±10%, vss=ov
Umlt.
Parameter
Symbol
Min
TyP
Max
Unit
Test
Condition.
Limits
Parameter
Symbol
Min
Typ
Max
Unit
ALE pulse width tLL
150
ns
Address setup
to ALE
tAL
70
ns
tLA
50
ns
Control pulse
tCC1
width (RD, WR)
480
ns
Control pulse
width (PSEN)
tCC2
350
ns
I/O rep rate
Data setup
beforeWR
tow
390
ns
Note:
(1) Control outputs: CL= 60 pF, bus outputs: CL = 150 pF
Data hold after
WR
two
40
ns
Data hold (RD,
PSEN)
tOR
0
RD to data in
PSEN to data in
Address hold
from ALE
Port 2 I / 0 data tpL
setup to ALE
160
ns
Port 2 I / 0 data tLP
hold to ALE
40
ns
Port output from tpv
ALE
Cycle time
tCY
1.36
tOPRR
270
510
ns
15
J.ls
Te.t
Conditions
ns
(2) Bus high impedance, load = 20 pF
(Note 2)
(3) Calculated values will be equal to or better than published 8049
values.
110
ns
tR01
350
ns
tR02
210
ns
Address setup
toWR
tAW
Address setup
to data (RD)
tA01
AC Programming Characteristics
300
ns
750
480
Address setup to tA02
data (PSEN)
ns
ns
TA=25°C±5°C, Vee = +5V±5%, Voo= +21V±O.5V
Limits
Parameter
Symbol
Min
Address setup tAW
time to RESETt
4tCY
Address hold
time after
RESETt
tWA
4tCY
Address float to tAFC1
RD,WR
140
ns
Data in setup
time to PROG t
tow
4tCY
Address float to tAFC2
PSEN
10
ns
Data in hold time two
after PROG+
4tCY
4tCY
ALE to control
(RD, WR)
tLAFC1
200
ns
RESET hold time tpH
to verify
ALE to control
(PSEN)
tLAFC2
60
ns
Voo
tVOOW
Voo hold time
after PROG+
tVOOH
PROG pulse
width
tpw
Control to ALE tCA1
(RD. WR. PROG)
50
ns
Control to ALE
(PSEN)
tCA2
320
ns
Port control
setup to PROG
tcp
100
ns
Port control hold tpc
to PROG
160
ns
PROG to P2
input valid
tpR
Input data hold
from PROG
tpF
0
Output data
setup
top
400
ns
Output data hold tpo
90
ns
PROG pulse
width
700
ns
tpp
650
ns
140
ns
0
50
TESTO setup
tTW
time for program
mode
4tCY
TESTO hold time twr
after program
mode
4tCY
TESTO to data
out delay(1)
too
RESET pulse
width to latch
address
tww
4tCY
Vooand PROG
rise and fall
times
tr.tf
0.5
Typ
Max
Unit
1.0
ms
1.0
ms
60
ms
Test
Conditions
4tCY
100
J.ls
4-239
E
NEe
J.lPD8039HL/49H, IJPD8749H
AC Programming Characteristics (cont)
Timing Waveforms
TA = 25°C±5°C, Vee = +5V±5%, Voo= +21V±O.5V
Limits
Parameter
CPU operation
cycle time
Symbol
Min
tCY
4.0
RESET setup
tRE
time before EA t
4tCY
TyP
Max
Unit
15
",5
Test
Conditions
Instruction Fetch from ExternafMemory
Note:
(1) Control outputs: CL = 60 pF, bus outputs: CL = 150 pF
(2) Bus high impedance, load = 20 pF
(3) Calculated values will be equal to or better than published 8049
values.
Bus Timing Requirements
-tAD283·002864A
Symbol
Timing Formula
MinIMax
Unit
tLL
(7/30) tCY -170
Min
ns
tAL
(2/15) tCy-110
Min
ns
tLA
(1/15) tCy-40
Min
ns
tCC1
. (1/2)tCy-200
Min
ns
tCC2
(2/ 5) tCY- 200
Min
ns
tow
(13/30) tCY - 200
Min
ns
two
(1/15) tCY- 50
Min
ns
tOR
(1/10) tCy-30
Max
ns
tR01
(2/5)tCy-200
Max
ns
tR02
(3/10) tCY- 200
Max
ns
tAW
(1/3) tCy-150
Min
ns
tA01
(11/15) tCY- 250
Max
ns
tA02
,8/15) tCY- 250
Max
ns
tAFC1
(2/15)tCy-40
Min
ns
tAFC2
(1/30) tCY- 40
Min
ns
tLAFC1
(1/5) tCy-75
Min
ns
tLAFC2
(1/10) tCY- 75
Min
ns
tCA1
(1/15)tCy-40
Min
ns
tCA2
(41.15)tCy-40
Min
ns
tcp
(2/15) tCY- 80
Min
ns
tpc
(4/15) tCY- 200
Min
ns
tpR
(17/30) tCY -120
Max
ns
tpF
(1/10) ICY
Max
ns
lop
(2/5) ICy-150
Min
ns
lpo
(1/10) ICY- 50
Min
ns
lpp
(7/10) tCY - 250
Min
ns
tpL
(4/15) tCY- 200
Min
ns
I-------tcv-----ALE
Floating
i---tAD83·002865A
ILP
(1/10) tCY -100
Min
ns
tpv
(3/10) tCy-100
Max
ns
IOPRR
(3/15) tCY
Min
ICY
11MHz
4-240
Read from External Data Memory
ns
",5
Write to External Memory
NEe
~PD8039HL/49H,~PD8749H
Timing Waveforms (cont)
Port 2 Timing
ALE
Expander
Port
Output
Expander
Port
Input
PROG
Waveforms for Programming the /APD8749H
1_-------program-------~-Verify-,I-------Programl-------+
TO
RESET
DBO-DB7
J---
PROG
'"-_N_ex_t_M_d_re_s_s-J
...
Valid
"
Mdress (8-9) Valid
P20-P21
VOD
X\.______________
Data To Be
Programmed Valid
~:::V-------!"'~jl
Next Mdress
r"",,"-VOOH _ _ _ _
~\.._---t-o-wtn--+~, I,.------------~\\..-----------83·002885A
Program/Verify Timing (ROM/EPROM)
TO
RESET
DBO-DB7
P20-P21
\
)----<
Mdress (0-7) Valid
X
X
Data Out
Valid
\
/
\
/
>----<
X
Next Mdress
X
Next Data
Out Valid
r-------83·002888A
4-241
~
I
I\)
1::
Instruction Set
~
Mnemonic
Funciton
Description
D7
DO
Operation Code
D5 D4 D3 D2
Accumulator
ADDA, # data
(A) -
Add immediate the specified data to the accumulator.
0
d7
0
d6
0
d5
I\)
(A) + data
0
d4
0
d3
(A) - (A) + (Rr)
r = 0-7
Add contents of designated register to the accumulator.
0
ADDA,@Rr
(A) - (A) + ((Rr))
r = 0-1
Add indirect the contents of the data memory location to the
accumulator.
0
ADDC A, # data
(A) -
Add immediate with carry the specified data to the
accumulator.
0
d7
0
d6
0
d5
1
d4
0
d3
ADDCA, Rr
(A) - (A) + (C) + (Rr)
r = 0-7
Add with carry the contents of the designated register to the
accumulator.
0
1
1
1
1
ADDCA,@Rr
(A) - (A) + (C) + ((Rr))
r = 0-1
Add indirect with carry the contents of data memory location to
the accumulator.
0
ANLA, # data
(A) -
Logical AND specified immediate data with accumulator.
0
d7
1
d6
0
d5
1
d4
0
d3
ANLA, Rr
(A) - (A) AND (Rr)
r = 0-7
Logical AND contents of designated register with accumulator.
0
1
0
1
1
ANLA, @Rr
(A) - (A) AND ((Rr))
r = 0-1
Logical AND indirect the contents of data memory with
accumulator.
0
CPLA
(A) -NOT(A)
Complement the contents of the accumulator.
0
0
CLRA
(A)-O
Clear the contents of the accumulator.
0
0
Decimal adjust the contents of the accumulator.
0
(A) AND data
DAA
1
d1
1
do
0
1
0
0
C
•
•
0
0
d2
1
d1
1
do
•
•
'11
F1
0
CD
0
W
CO
...:E:....
...
CO
:E:
1::
'11
0
CD
0
0
•
0
~
U)
0
0
0
0
1
0
0
0
(A)-(A)-1
Decrement by 1the accumulator's contents.
0
0
0
1
d1
0
0
1
do
:E:
0
INCA
(A)-(A) +1
Increment by 1the accumulator's contents.
0
0
0
1
0
ORLA, # data
(A) -
Logical OR specified immediate data with accumulator.
0
d7
1
d6
0
d5
0
d4
0
d3
ORLA, Rr
(A) - (A) OR (Rr)
r = 0-7
Logical OR contents of designated register with accumulator.
0
1
0
0
1
ORLA, @Rr
(A) - (A) OR ((Rr))
r = 0-1
Logical OR indirect the contents of data memory location with
accumulator.
0
0
0
0
RLA
(AN + 1) - (AN); N = 0-6
(Ao) -(A7)
Rotate accumulator left by 1bit without carry.
0
0
RLCA
(AN + 1) - (AN); N = 0-6
(Ao)-(C)
(C)-(A7)
Rotate accumulator left by 1 bit through carry.
RRA
(AN) - (AN + 1); N = 0-6
(A7) - (Ao)
Rotate accumulator right by 1bit without carry.
0
0
0
d2
0
1
DEC A
(A) OR data
Do
Brte.
•
ADDA, Rr
(A) + (C) + data
0
d2
D1
Crcle.
Flags
AC FO
0
•
0
d2
1
d1
0
0
1
do
•
;(
~
Instruction Set (cont)
Operation Code
Mnemonic
Function
Description
D7
D6
Ds
D4
D3
0
0
D2
D1
Do
0
d2
1
d1
1
do
Accumulator (cont)
RRCA
(AN) - (AN + 1); N = 0-6
(A7)-(C)
(C)-(Ao)
Rotate accumulator right by 1 bit through carry.
0
SWAP A
(A4-A7) -
Swap the 2 4-bit nibbles in the accumulator.
0
XRLA, # data
(A) -
XRLA, Rr
XRLA, @Rr
(Ao-A3)
Logical XOR specified immediate data with accumulator.
(A) - (A) XOR (Rr)
r = 0-7
Logical XOR contents of designated register with accumulator.
(A) - (A) XOR ((Rr))
r = 0-1
Logical XOR indirect the contents of data memory location with
accumulator.
(Rr) - (Rr) - 1; r = 0-7
If (Rr) '" 0;
(PCO-PC7) - addr
Decrement the specified register and test contents.
(PCO-PC7) -- addr if Bb = 1
(PC) - (PC) + 2 if Bb = 0
Jump to specified address if accumulator bit is set.
(PCO-PC7) - addr if C = 1
(PC) - (PC) + 2 if C = 0
Jump to specified address if carry flag is set.
JFOaddr
(PCO-PC7) - addr if FO = 1
(PC) - (PC) + 2 if FO = 0
JF1 addr
(A) XOR data
0
0
0
1
d7
1
d6
0
d5
1
d4
0
d3
1
1
0
1
1
0
0
0
Cycles
Bytes
C
Flags
AC FO
F1
~~
Branch
DJNZ Rr, addr
a7
a6
a5
0
a4
a3
r
a2
r
a1
r
ao
b2
a7
b1
a6
bo
a5
a4
0
a3
0
a2
a1
0
ao
1
a7
1
a6
a5
a4
0
a3
1
a2
a1
ao
Jump to specified address if flag FO is set.
1
a7
0
a6
1
a5
1
a4
0
a3
1
a2
1
a1
0
ao
(PCO-PC7) - addr if F1 = 1
(PC) - (PC) + 2 if F1 = 0
Jump to specified address if flag F1 is set.
0
a7
a6
a5
a4
0
a3
a2
a1
0
ao
(PCa-PC1O) - (addra-addr1O)
(PCO-PC7) - (addro-addr7)
(PC11) - DBF
Direct jump to speciffed address within the 2K address block.
a10
a7
ag
a6
aa
a5
0
a4
0
a3
a2
a1
ao
JMPP@A
(PCO-PC7) -- ((A))
Jump indirect to specified address with address page.
0
1
0
1
JNC addr
(PCO-PC7) -- addr if C = 0
(PC) - (PC) + 2 if C = 1
Jump to specified address if carry flag is low.
a6
a5
0
a4
0
a3
JNI addr
(PCO-PC7) - addr if I = 0
(PC) -- (PC) + 2 if I = 1
Jump to specified address if interrupt is low.
a7
a6
0
a5
a4
0
a3
JNTO addr
(PCO-PC7) -addr if TO = 0
(PC) - (PC) + 2 if TO = 1
Jump to specified address if test 0 is low.
0
a7
0
a6
1
a5
0
a4
0
a3
a2
JNT1 addr
(PCO-PC7) - addr ifT1 = 0
(PC) - (PC) + 2 ifT1 = 1
Jump to specified address if test 1 is low.
0
a7
1
a6
0
a5
a4
0
a3
1
a2
JNZaddr
(PCO-PC7) - addr if A", 0
(PC) - (PC) + 2 if A = 1
Jump to specified address if accumulator is non-zero.
1
a7
0
a6
0
a5
a4
a3
(PCO-PC7) -- addr ifTF = 1
(PC) - (PC) + 2 ifTF = 0
Jump to specified address if timer flag is set to 1.
0
a7
0
a6
a5
a4
0
a3
JBb addr
JC addr
JMP addr
~
I
I\)
-'=>-
JTF addr
a7
(.0.)
I!I!I
a2
a1
0
aO
a2
1
a1
ao
a1
0
ao
a1
0
aO
a2
a1
aO
a2
a1
0
ao
"l:
"
D
CD
0
W
CD
.......
%
~
CD
..%
"l:
"
D
CD
~
CD
%
f"
J\)
Instruction Set (cont)
Mnemonic
Description
Function
D7
D6
Operation Code
Ds D4 D3 D2
D1
Do
Branch (cant)
JTO addr
JT1 addr
JZ addr
,.a
1::
~
~
Cycles
Bytes
C
Flags
AC FO
F1
CD
0
(PCO-PC7) - addr ifTO = 1
(PC) - (PC) + 2 if TO = 0
Jump to specified address if test 0 is a 1.
(PCO-PC7) - addr if T1 = 1
(PC) - (PC) + 2 ifT1 = 0
Jump to specified address if test 1is a 1.
(PCO-PC7) - addr if A = 0
(PC) -(PC) + 2ifA = 1
Jump to specified address if accumulator is O.
a7
0
as
a5
a4
0
a3
a2
a1
0
aO
0
a7
1
a7
1
as
1
as
0
a5
0
a5
a4
0
a4
0
a3
0
a3
a2
1
a2
a1
1
a1
aO
0
ao
0
0
Control
EN I
Enable the external interrupt input.
0
0
DIS I
Disable the external interrupt input.
0
0
Enable the clock output pin TO.
0
ENTO ClK
0
1
0
0
0
0
(DBF) -0
Select bank 0 (locations 0-2047) of program memory.
SEl MB1
(DBF)-1
Select bank 1(locations 2048-4095) of program memory.
1
SEl RBO
(BS)-O
Select bank 0 (locations 0-7) of data memory.
0
SEl RB1
(BS)-1
Select bank 1(locations 24-31) of data memory.
0
MOV A, # data
(A) -data
Move immediate the specified data into the accumulator.
0
d7
0
ds
1
d5
0
d4
0
d3
MOVA, Rr
(A) -
(Rr); r = 0-7
Move the contents of the designated registers into the
accumulator.
1
1
1
1
1
MOVA,@Rr
(A) -
«Rr)); r = 0-1
Move indirect the contents of data memory location into the
accumulator.
MOVA, PSW
(A) -(PSW)
Move contents of the program status word into the
accumulator.
MOV Rr, # data
(Rr) -
data; r = 0-7
Move immediate the specified data into the designated
register.
1
d7
(A); r = 0-7
Move accumulator contents into the designated register.
1
.
CD
~
,.
aCD
~
CD
0
0
:z:
r.....
1::
0
0
SEL MBO
W
CD
:z:
0
0
Data Moves
MOV Rr, A
(Rr) -
MOV@Rr,A
«Rr)) -
(A); r = 0-1
Move indirect accumulator contents into data memory location.
MOV@Rr,
# data
«Rr)) -
data; r = 0-1
Move immediate the specified data into data memory.
MOV PSW, A
0
1
d7
0
0
0
0
ds
1
d5
1
d4
1
d3
1
d1
1
do
r
d2
r
d1
r
do
0
d2
0
0
1
0
1
0
1
0
0
0
0
0
ds
1
d5
1
d4
0
d3
0
d2
0
d1
1
do
0
1
0
1
1
1
0
0
0
0
0
0
(PSW)-(A)
Move contents of accumulator into the program status word.
1
MOVPA,@A
(PCO-PC7) - (A)
(A)-«PC))
Move data in the current page into the accumulator.
0
MOVP3A,@A
(PCO-PC7) - (A)
(PCa-PC10) - 011
(A)-«PC))
Move program data in page 3 into the accumulator.
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Function
Description
MOVXA,@R
(A) -
((Rr)); r = 0-1
MOVX@R,A
((Rr)) -
(A); r = 0-1
XCH A, Rr
(A) -
(Rr); r = 0-7
Exchange the accumulator and deSignated register's contents.
0
0
0
1
XCH A, @Rr
(A) -
((Rr)); r = 0-1
Exchange indirect contents of accumulator and location in data
memory.
0
0
0
0
XCHDA,@Rr
(Ao-A3) r = 0-1
Exchange indirect 4-bit contents of accumulator and data
memory.
0
0
De
Ds
D4
D3
D2
D1
Move indirect the contents of external data memory into the
accumulator.
0
0
0
0
0
0
Move indirect the contents of the accumulator into external
data memory.
0
0
0
0
0
0
0
0
D7
Do
Cycles
Bytes
C
Flags
AC FO
F1
Data Moves (cont)
Flags
CPL C
(C) -
CPL FO
(FO) -
CPL F1
(F1) -
CLR C
((Rr))o-((Rr))s;
Complement contents of carry bit.
0
1
0
1
NOT (FO)
Complement contents of flag FO.
0
0
0
0
NOT (F1)
Complement contents of flag F1.
0
1
0
0
(C)-O
Clear contents of carry bit to O.
0
0
0
1
CLR FO
CLR F1
(FO)-O
Clear contents of flag 0 to O.
0
0
(F1)-0
Clear contents of flag 1to O.
Input! Output
ANL BUS,
# data
(bus) -
NOT (C)
0
1
0
0
0
0
0
0
•
•
•
•
•
Logical AND immediate specified data with contents of bus.
1
d7
0
d6
0
d5
1
d4
1
d3
0
d2
0
d1
0
do
(Pp) - (Pp) AND data
p = 1-2
Logical AND immediate specified data with designated
port (1 or 2).
1
d7
0
d6
0
d5
1
d4
1
d3
0
d2
P
d1
P
do
ANLD Pp, A
(Pp) - (Pp) AND (Ao-A3);
P = 4-7
Logical AND contents of accumulator with designated port
(4-7).
1
0
0
1
1
1
ANL Pp,
# data
(bus) AND data
"
IN A, Pp
(A) -
Input data from designated port (1-2) into accumulator.
0
0
0
0
0
p
P
2
(A) -(bus)
Input strobed bus data into accumulator.
0
0
0
0
0
0
0
2
MOVDA, Pp
(Ao-A3) (A4-A7) -
Move contents of designated port (4-7) into accumulator.
0
0
0
0
Move contents of accumulator to deSignated port (4-7).
0
0
Logical OR immediate specified data with contents of bus.
1
d7
0
0
0
0
0
d5
d4
1
d3
0
d6
d2
d1
do
(Pp); P = 4-7
0
MOVD Pp, A
(Pp) (bus) -
ORLD Pp, A
(Pp) - (Pp) OR (Ao-As);
p = 4-7
Logical OR contents of accumulator with deSignated port
(4-7).
1
0
0
0
1
1
P
P
ORL Pp,
# data
(Pp) - (Pp) OR data
p = 1-2
Logical OR immediate specified data with designated port
(1-2).
1
d7
0
d6
0
d5
0
d4
1
d3
0
d2
P
d1
P
do
~
OUTL BUS, A
(bus) -(A)
Output contents of accumulator onto bus.
0
0
0
0
0
0
1
0
01
OUTL Pp, A
(Pp) -
Output contents of accumulator to designated port (1-2).
0
0
(Ao-A3); p = 4-7
(bus) OR data
(A); P = 1-2
m
0
C
CO
0
W
CO
2:
......r-
p
ORL BUS,
# data
I\.)
~
~
INS A, BUS
(Pp); p = 1-2
~
~
CO
~
~
"
C
CO
~
CO
2:
~
I
N
1:
Instruction Set (cont)
~
(J)
Operation Code
Mnemonic
Function
Description
D7
De
D5
1
a
a
a
D4
D3
D2
D1
Do
Registers
DEC Rr (Rr)
= a-7
+ 1; r = a-7
Decrement by 1 contents of designated register.
(Rr) -
(Rr) - 1; r
INC Rr
(Rr) -
(Rr)
INC@Rr
((Rr))-((Rr)) +1;
r = a-1
Increment indirect by 1 the contents of data memory location.
((SP)) - (PC),
(PSW4-PSW7),
(SP) - (SP) + 1
(PCS-PC10) - (addrs- addr10)
(PCo-PC?) - (addro-addr7)
(PC11) - DBF
Call designated subroutine.
(SP) - (SP) = 1
(PC) -((SP))
Return from subroutine without restoring program status word.
(SP) - (SP) = 1
(PC) - ((SP))
(PSW4-PSW?) - ((SP))
Return from subroutine restoring program status word.
a
Increment by 1 contents of designated register.
a
RET
RETR
a10
a7
ag
a6
as
a5
Bytes
C
F1
"a
C»
0
~
CD
:z
1
a
a
a
a
a
a2
a1
ao
Subroutine
CALL addr
Cycles
Flags
AC FO
a
a4
a3
...,.rCD
..:z
1:
"a
CD
a
a
a
a
~
a
CD
:z
a
Timer / Counter
EN TCNTI
Enable internal interrupt flag for timer / counter output.
DIS TCNTI
Disable internal interrupt flag for timer / counter output.
MOVA, T
(A)-(T)
MOVT, A
(T)-(A)
Move contents of timer / counter into accumulator.
a
a
a
a
a
a
1
1
a
a
Move contents of accumulator into timer / counter.
STOP TCNT
Stop count for event counter.
1
STRT CNT
Start count for event counter.
STRTT
Start count for timer.
a
a
a
No operation performed.
a
a
a
a
a
a
a
a
a
a
1
a
a
a
a
a
Miscellaneous
NOP
a
a
a
a
a
a
Note:
(1) Operation code designations rand p form the binary representation of the registers and ports involved.
(2) The dot under the appropriate flag bit indicates that its contents are subject to change by the instruction it appears in.
(3) References to the address and data are specified in bytes 2 and/or 1 of the instruction.
(4) Numerical subscripts appearing in the function column
r~ference
the specific bits affected.
(5) When the bus is written to with an OUTL instruction, the bus remains an output port until either the device is reset or a MOVX instruction is executed.
~
~
NEe
~PD8039HL/49H,~PD8749H
Instruction Set Symbol Definitions
A
Accumulator
AC
Auxiliary carry flag
addr
Bb
Bit designator (b = 0-7)
Bank switch
BUS
Bus port
C
Carry flag
ClK
Clock signal
CNT
Event counter
\TYP
3mA
J:
Number of expression (8 bits)
DBF
Memory bank flip-flop
Vee=4.5V
\
2mA
\
9
1mA
(
Nibble designator (4 bits)
data
FO, F1
Bus Output High Voltage vs. Source Current
Program memory address (12 bits)
BS
D
Operating Characteristics
Description
Symbol
OV
2V
4V
6V
VOH
Flags 0,1
Interrupt
"In-page" operation designator
Pp
PSW
Program status word
Rr
Register designator (r= 0, 1or 0-7)
SP
Stack pointer
T
Timer
TF
Timer flag
TO, T1
Testable flags 0, 1
X
External RAM
#
Prefix for immediate data
@
Prefix for indirect address
$
Program counter's current value
(x)
((x))
Port P1 & P2 Output High Voltage vs. Source Current
Port desig nator (p = 1, 2 or 4-7)
II
Vee=4.5V
Typ
'"J:
9
OV
~\
2V
~
4V
VOH2
Contents of external RAM location
Contents of memory location addressed by the
contents of external RAM location
Replaced by
AND
OR
EXOR
Bus Output Low Voltage vs. Sink Current
logical product (logical AND)
logical sum (logical OR)
Typ
Exclusive-OR
vee = 4.5 V
..J
9
10mA~----~~---------+----------------~
I
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
~2
OV
2V
VOL
4-247
~PD8039HL/49H,~PD8749H
4-248
NEe
NEe
NEe Electronics Inc.
~PDaOC39H/49H,~PD49H
HIGH-SPEED, a-BIT, SINGLE-CHIP
CMOS MICROCOMPUTERS
Description
Pin Configurations
The JAPD80C39H, JAPD80C49H, and JAPD49H are singlechip, 8-bit microcomputers containing an 8-bit CPU,
ROM (80C49H and 49H), RAM, I/O ports, and control circuitry. Through CMOS technology, the devices can retain data with low power consumption. In addition, the
processor uses two standby modes (HALT and STOP) to
further minimize power drain.
40-Pin Plastic DIP
TO
Vee
1
T1
XTAL1
P27
Features
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
98 instructions
1.25JAs instruction cycle time (12 MHz crystal)
Addition, logic, and decimal adjust functions
2K x 8-bit ROM (JJPD80C49H and JAPD49H)
256 x 8-bit RAM
Standby function
8-level stack
Two sets of working registers
Interrupt capability
Two test inputs
Internal timer/event counter
Input/output ports (8 bits x 2)
- Data bus alternative to I/O ports (8 bits x 1)
Expandable memory and I/O ports
Single-step function
Internal clock generator
CMOS technology
Single power supply of +2.5 to +6.0 V
Intel 8049H, 8039H pin compatible
Item
IIPD80C49H
IIPD80C49
Instructions
98 (STOP instruction
added)
97
Instruction Cycle
1.2S/As (12 MHz
crystal)
1.87S/As (8 MHz
crystal)
Standby Modes
3 (HALT, hardware
STOP, software STOP)
2 (STOP and HALT)
Standby Functions
All standby modes stop
at the same timing.
The control signal
(ALE) stops in the
inactive state whether
or not internal or
external ROM is
accessed.
HALT and STOP modes
stop at different
timing.
Type 0: IOH = - S/AA;
Voo=SV±10%
Type 1: IOH= -50~;
Voo=5V±10%
Type 2: no pullup
resistor
Type 0: IOH = -5~;
Voo=5V±10%
Type 1: IOH=-50~;
Voo=5V±10%
Port Options
ViR
ALE
DBo
DB1
DB2
Vss
83-002789A
44-Pin Plastic Miniflat
~ ~
> Q
STOP
lQ
~
Q
JQ
DB3
0
P10
DB2
P11
31
DB1
P12
DBo
P13
ALE
pPD49H
P14
28
ViR
PSEiii
25
EA
P1s
NC
Ri5
P16
P17
P24
10
iNi'
58
83-002790A
4-249
11
NEe
~PD80C39H/49H,~PD49H
Pin Configurations (cont)
Pin Identification
Function
Symbol
52· Pin Plastic Miniflat
(.)
(.)
z
Z
~
NC
;r
D.
fl f f. f f
...
...
en
CD
(.)
f. f
Z
...
c
c
>
...
M
C>
NC
TO
Test 0 input / clock output
XTAL1
Crystal 1input
XTAL2
Crystal 2 input
RESET
Reset input
SS
Single step input
INT
Interrupt input
P2s
PROG
NC
P23
P2s
P22
EA
External access input
P27
P21
RD
Read output
T1
P20
Vee
IC*
PSEN
Program store enable output
NC
Vss
WR
Write output
DB7
ALE
Address latch enable output
DBa-DB7
Bidirectional data bus
TO
XTAL1
DB6
10
XTAL2
DBs
RESET
DB4
Vss
Ground
NC
P2a-P27
Quasi-bidirectional port 2
NC
13
(.)
z
Il:! I~ iti
I~
I~ I~
..,
(.)
~ ~ z
~ Q~ IE
Q
Q
c(
*Internally connected
topln7
83·003899A
Ordering Information
Part
.Number
Package Type
I1PD80C39HC
40-pin plastic DIP
I1PD80C49HG-00 52-pin plastic
miniflat
Mal Frequency
of Operation
ROM
12 MHz
None
12 MHz
2K x 8 bits
I1PD80C49HC
40-pin plastic DIP
12 MHz
2K x 8 bits
I1PD49HG-22
44-pin plastic
miniflat
12 MHz
2K x 8 bits
4-250
PROG
Program output
STOP
Stop input
P1a-P17
Quasi-bidirectional port 1
T1
Test 1input
VDD
Power supply
NC
Not connected
IC
Internal connection
NEe
~PD80C39H/49H,~PD49H
Pin Functions
XTAL1, XTAL2 (Crystals 1, 2)
WR(Write)
XTAl1 and XTAl2 are the crystal inputs for the internal
clock oscillator. XTAl1 is also used as an input for external clock signals.
WR enables a data write to external memory.
TO (Test 0)
The JTO and J NTO instructions test the level of TO and, if
it is high, the program address jumps to the specified
address. TO becomes a clock output when the ENTO
ClK instruction is executed.
T1 (Test 1)
The JT1 and J NT1 instructions test the level of T1 and, if
it is high, the program address jumps to the specified
address. T1 becomes an internal counter input when the
STRT CNT instruction is executed.
RESET (Reset)
RESET initializes the processor and is also used to verify the internal ROM. RESET determines the oscillation
stabilizing time during the release of STOP mode. The
RESET pulse width requires at least 5 machine cycles
when the supply voltage is within specifications and
the oscillation frequency is stable. (Active low).
SS (Single Step)
SS causes the processor to execute the program one
step at a time. SS also determines the oscillation stabilizing time during the release of the software STOP
mode.
INT (Interrupt)
INT starts an interrupt if interrupts are enabled. A reset
disables an interrupt. INT can be tested with the JNI instruction and, depending on the results, a jump to the
specified address can occur.
EA (External Access)
PSEN (Program Store Enable)
PSEN fetches instructions only from external program
memory. (Active low).
ALE (Address Latch Enable)
ALE occurs at each cycle. The falling edge of ALE addresses external data memory or external program
memory. ALE can also be used as a clock output.
DBO-DB7 (Data Bus)
DBa-DB? is a bidirectional port. DBa-DB? reads and
writes data using RD and WR for latching. During an external program memory fetch, DBa-DB? output the loworder eight bits of the memory address. PSEN fetches
the instruction. DBa-DB? also output the address of an
external data memory fetch. The addressed data is read
and written by RD and WR.
P10- P17 (Port 1)
P1a-P1? is an 8-bit quasi-bidirectional port.
P20-P27 (Port 2)
P2a-P2? is an 8-bit quasi-bidirectional port. P2a-P23
output the high-order four bits of the address during an
external program memory fetch. P2a-P23 also function
as a 4-bit 110 bus for the J-lPD82C43 110 port expander.
PROG (Program Pulse)
PROG is used as an output pulse during a fetch when
interfacing with the J-lPD82C43110 port expander.
STOP (Stop)
STOP controls the hardware STOP mode. STOP stops
the oscillator when active low.
EA disables internal program memory and fetches and
accesses external program memory. EA is used for system testing and debugging. (Active high).
Voo (Power Supply)
RD (Read)
Vss (Ground)
RD enables a data read from external memory. (Active
low).
Vss is ground potential.
VDD is the positive power supply (+2.5 V to +6.0 V).
4-251
NEe
~PD80C39H/49H,~PD49H
Block Diagram
DalaMemory
128x8RAM
Regis1er0-7
B Level Stack
(Variable Leng1h)
Op1lonai Second
Register Bank
Data Store
P1o-P17
P20- P27
Program
Memory
SlOP
T1
Power
Supply
Voo -
+2.5-+6.0V
V
GND
ss
_
TO
T1
Test
49-0005578
Absolute Maximum Ratings
DC Characteristics
TA=25°c
Standard Voltage Range
Power supply voltage, Voo
Vss -0.3Vto +7V
Input voliage, VI
Vss -0.3VtoVoo +0.3V
Output voltage, Vo
Vss -0.3VtoVoo +O.3V
Operating temperature, TOPT
Storage temperature, TSTG
-40°C to +85°C
- 65°C to + 150°C
Comment: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits de,
scribed in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
TA= -40°C to +85°c,Voo= +5V±10%,Vss=OV
Limits
Parameter
Symbol
Min
TyP
Max
Unit
Test
Conditions
Input voltage
low
VIL
-0.3
+0.8
V
Input voltage
high
VIH
Voo-2
Voo
V
Except XTAL1, _
XTAL2, RESET, SS
VIH1
VOO-1
VOO
V
RESET, XTAL1,
XTAL2, SS
+0.45
V
IOL=2.0mA
Output voltage
low
VOL
Output voltage
high
VOH
2.4
V
Bus, RD, WR,
PSEN, ALE, PROG,
TO; IOH= -400jAA
VOH1(1)
2.4
V
IOH = - 5 fAA (type
0) port 1, port 2
2.4
V.
IOH= -50jAA
(type 1) port 1,
port 2
V
All outputs,
IOH= -0.2fAA
-40
jAA
Port 1, port 2;
VIL (type 0)
VI~
-500
fAA
Port 1, port 2;
VIL (type 1)
VI~
-40
fAA
SS, RESET;
VOH2
Input current
IILP(1)
IILC
Voo-0.5
-15
VI~VIL
4-252
NEe
~PD80C39H/49H,~PD49H
DC Characteristics (cont)
Extended Voltage Range (cant)
Standard Voltage Range (cant)
TA= -400Cto +85°C,Voo= +2.5Vto +6.0V,Vss=ov
Limits
TA= -40°C to +85°C, Voo= +5V±10%, Vss=OV
Limits
Parameter
Input leakage
current
Output leakage
current
Symbol
Typ
Min
ILl1
Max
Unit
±1
JAA
Test
Conditions
Parameter
Symbol
Min
Standby current 1001(4)
1L12
±3
JAA
EA; VSS~VI~VOO
ILO
±1
JAA
VSs~Vo~VOO
High impedance,
bus, TO(3)
1.5
3.0
mA
tCy=1.25JAs
1002(5)
20
JAA
(2)
Supply current
(total)
100
18
mA
tCy=1.25JAs
Data retention
voltage
VOOOR
Standby current 1001(4)
V
2.0
Max
Unit
0.3
0.6
mA
Voo=3V;
tCy=5JAs
2.0
4.0
mA
Voo=6 V
tCy=1.25JAs
T1, INT, STOP;
VSS~VI~VOO
20
JAA
(2); Voo=3 V
50
JAA
Voo=6 V
2.0
4.0
mA
Voo=3V;
tCy=5JAs
10
20
mA
Voo=6V;
tCy=1.25JAs
1002(5)
Supply current
100
Test
Conditions
Typ
Note:
At hardware STOP
mode (STOP,
RESET~0.4 V) or
RESET
(RESET~O.4 V)
(1) Types 0, 1, and 2 options can be specified for j.lPD80C49H.
Type 0 for j.lPD80C39H only.
(2) Input pin voltage is VI':S;; VILor VI ~ VIH'
(3) Includes port 1and port 2 pins optionally specified with type 2.
(4) HALT mode.
(5) STOP mode.
Extended Voltage Range
TA= -40°Cto +85°C, Vss=OV
Limits
Parameter
Symbol
Input voltage
low
VIL
Input voltage
high
VIH
VIH1
Output voltage
low
VOL
Output voltage
high
VOH
Input current
Input leakage
current
Output leakage
current
Min
Typ
-0.3
Max
Unit
Test
Conditions
Limits
VDD=
t5V±10"lo
+0.18Voo V
O.7VOO
VOO
0. 8V OO
II
AC Characteristics
TA = - 40°C to +85°C, Voo = +2.5 V to +6.0 V, Vss = 0 V
VOO
+0.45
0. 75V oo
V
V
Except XTAL1, _
XTAL2, RESET, SS
RESET, XTAL1,
XTAL2, SS
V
IOL=1.0mA
V
Bus, RD, WR,
PSEN, ALE, PROG,
TO; 10H = -100 JAA
Parameter
Symbol
Min
Max
Cycle time
150
VDD=
2.5Vto&.OV
Min
Max
150
Test
Unit Conditions
tCY
1.25
ALE pulse width tLL
125
995
ns
(1)
Address setup
before ALE
tAL
140
890
ns
(1)
Address hold
from ALE
tLA
45
295
ns
(1)
Control pulse
width (fill, WR)
tCC1
425
2300
ns
(1)
JAs
VOH1(1) 0. 7V oo
V
10H = -1 JAA (type
0) port 1, port 2
Control pulse
width (PSEN)
tCC2
300
1400
ns
(1)
0. 7V OO
V
10H = -10 JAA (type
1) port 1, port 2
Data setup
before WR
tow
340
1965
ns
(1)
Data hold after
WR
two
45
295
ns
(2)
Data hold after
RD, PSEN
tOR
95
470
ns
(1)
RD to data in
tR01
300
1800
ns
(1)
1300
ns
(1)
ns
(1)
-40
JAA
Port 1, port 2;
VIL (type 0)
VI~
-500
JAA
Port 1, port 2;
VIL (type 1)
VI~
IILC
-40
JAA
SS, RESET;
VIL
ILl1
±1
JAA
T1 , INT, STOP;
PSEN to data in
tR02
VSS~VI~VOO
Address setup
before WR
tAW
Address setup
before data in
tA01
IILP(1)
-15
VI~
1L12
±5
JAA
EA; VSS~VI~VOO
ILO
±1
JAA
VSs~Vo~VOO
High impedance,
bus, TO (3)
175
1850
350
700
3585
(1)
(im)
4-253
NEe
~PD80C39H/49H,~PD49H
AC Characteristics (cont)
AC Timing Test Points (Except RESET, XTAL1, XTAL2, 55)
TA= -40°Cto +85°C, Vss=OV
(a)Voo= +5.OV±10%
Limits
Parameter
Symbol
Address setup
before data in
(PSEN)
tA02
Address float to
RD, WR
tAFC1
Address float to
PSEN
tAFC2
Voo -2
Voo=
+5Vj:10%
Voo=
2.5Vt08.0V
Min
Min
Max
Max
2750
500
==:>C::::>-
Test
Unit Conditions
ns
(1)
Voo -2
Test Points
0.8
0.8
(b)Voo= +2.5 to S.OV
O·7V oo
O·7V oo
===x~
Test Points
0.18Voo
105
600
ns
(1)
125
ns
(1)
ALE to control
tLAFC1
signal (RD, WR)
175
925
ns
(1)
ALE to control
signal (PSEN)
50
425
ns
(1)
Control signal
tCA1
(RD, WR, PROG)
to ALE
35
285
ns
(1)
Control signal
(PSEN) to ALE
tCA2
280
1285
ns
(1)
Port control
setup before
falling edge of
PROG
tcp
85
460
ns
(3)
tLAFC2
-=:::::x=:
~x==
0. 18Voo
4~70A
Timing Waveforms
Instruction Fetch (External Program Memory)
ALE
PSEN
Port control hold tpC1
0
Port control hold tpC2
after falling edge
of PROG
135
PROG to time P2 tpR
input must be
valid
ns
(3,4)
ns
(3,5)
2715
ns
(3)
500
ns
(3)
200
80
1135
585
Read (External Data Memory)
ALE
AD
Input data hold
time
tpF
0
125
0
Output data
setup time
top
350
1850
ns
(3)
Output data hold tpo
time
75
450
ns
(3)
PROG pulse
width
tpp
625
3250
ns
(3)
Port 21/0 data
setup time
tpL
135
1135
ns
(3)
Port 21/0 data
hold time
tLP
125
ns
(3)
ALEta port
output
tpv
ns
(3)
TO clock period
tOPRR
ns
(3)
Write (External Data Memory)
ALE
1600
475
250
1000
WR
Bus Floating
Floating
Note:
(1) Control output: CL = 80 pF, bus output: CL = 150 pF
(2) CL=20pF
(3) Control output: CL =.80 pF
(4) At execution of MOVO A, Pp instruction
(5) At execution of MOVO Pp, A; ANlO Pp, A; ORlO Pp, A instructions
4-254
49-OOO571B
NEe
J.lPD80C39H/49H, J.lPD49H
Timing Waveforms (cont)
Bus Timing Requirements
Symbol
Timing Formula
MiniMax
Unit
(7/30) tCY -170
Min
ns
(1/5)tCy-110
Min
ns
(1/15) tCy-40
Min
ns
(1/2) tCY - 200
Min
ns
(2/5) tCY- 200
Min
ns
tow
(13/30) tCY - 200
Min
ns
two
(1/15) tCy-40
Min
ns
tOR
(1/10)tCy-30
Max
ns
(2/5) tCY- 200
Max
ns
(3/10) tCy-200
Max
ns
(2/5) tCy-150
Min
ns
(23/30)tCy-250
Max
ns
(315) tCy-250
Max
ns
(2/15)tCy-65
Min
ns
(1/30)tCy-40
Min
ns
(1/5) tCy-75
Min
ns
(1/10) tCy-75
Min
ns
tCA1
(1/15) tCY- 50
Min
ns
tCA2
(4/15) tCY- 50
Min
ns
tcp
(1/10)tCy-40
Min
ns
(4/15) tCY- 200
Min
ns
(17/30) tCY -120
Max
ns
(1/10) tCY
Max
ns
top
(2/5) tCy-150
Min
ns
tpo
(1/10) tCy-50
Min
ns
Port 2 Expansion Timing
ALE
Expander
Port
Output
Expander
Port
Input
PROG
I/O Port Timing
2nd Cycle
ALE
P20-P23
Output
Port 20-Port 23 Data
New P20-P23 Data
PC H
P 2 4 - P 2 7 - - - - - - - - - - - " " ' " " ' I r -_ _ _ __
P1~-;;-;:~r
__
Po_rt_24;...-P_o_rt.....;.27_D_ata_,_Po_rt....;10;...-P_ort_1..:...
7 _Da_ta-J 1,,-_N_ew_po_rt_Da_ta_
49-000572A
(7/10) tCY - 250
Min
ns
(4/15) tCY- 200
Min
ns
(1/30)tCy-40
Min
ns
tpv
(3/10) tCY +100
Max
ns
tOPRR
(1/5) tCY
Min
tCY
(11 fXTALl x 15
tpp
ns
lAS
4-255
NEe
~PD80C39HI49H,~PD49H
Operating Characteristics
IOH VSVOH
IOHVS VOH
-15 r - - - - r - - - - , - - - - , - - - - - - , - - - . . , . - - ,
-150
-~r--------,,---~---.---------r----~--'
TA = 25°C
Voo = 4.5 V
TA = 25·C
VOO=4.5V
c
~
i
:z:
.9
:i
x
I
-100
-10
I-----I----_f-~._____--+----+-----l
.9
..c
JP
x
-400
C
§
U
U -50
I
-51-----+-----1-~.___f-~._____-l----____1
io
....
~
o
~
~~O----L---~---~---~~~~
Output Voltage High VOH1 [V]
Output Voltage High VOH [V]
IOHVSVOO
-200
IOH vs VOO
~20
TA=25·C
VOH1 =2.4V
~
-150
-15
:z:
.9
..c
JP
X
I
-100
-10
U
io
-50
-5
/
o
/
/
V
TA = 25°C
VOH2 = Voo -0.5 V
~
:z:
.9
..c
JP
:z:
~
-0.2
::I
U
1
:;
0
0(
~
t
~
-0.4
gj
o
0
"
2
Supply Voltage Voo [V]
Supply Voltage Voo [V]
IOL vs VOL
IOL vs VOO
TA = 25°C
VOL = 0.45 V
C
C
!.
...
!.
...
.9
....~
.9
•
.3
2
~
U
!u
::I
2
/"
i
:;
~
//
"
"
0
0
0(
~
:I
§
ij
gj
1
2
4-256
4
Supply Voltage VOO [V]
::s
0
0
0.5
Output Voltage Low VOL [V]
1.0
NEe
~PD80C39H/49H,~PD49H
Operating Characteristics (cont)
100/1001 vs f
100/1001 vs f
20
TA=25°C
Voo = 5.5 V
IO~ j..-l--
;,.
...
10
1
Q
--
5
Q
~
E
I
.~
u
.... ....
::::: ~
....
..... 1~
---
100 Typ ....
."-~--
10'"
IO~1-
~ .... 1-
I-
>-
is.
Do
Jl
0.5
_
-I-
0.2 ~ ___ - - - 0.11......._ _ _-'----_--L_-'---L--L--L..L.L.l..._ _ _--'-_ _.L..-.......J
0.1
0.5
0.2
0.2
0.1
0.2
0.5
10
15
Supply Voltage VOO [V]
Oscillation Frequency I [MHz] [I = 15 tCY]
Curves below 1 MHz show characteristics lor external oscillation
Curves below 1 MHz show characteristics 'or external oscillation.
IPC1 Max [80C49H] and IACC Min [82C43] vs VOO
ICyvs VOO
200
! ..c
100
J}
It
tJPOSOC49H
tPC1 Max
j::
20
CJ
CJ
~
j:: 150
X Q
i
u
10
~
U
~ 'iii;'
It
E
It
E
j::
~
~
i
Operation
Secured Area
0
""'-.
TA = -40 10 +S5°C
'I:
~
0
A-
X
. . . . t---..
Supply Voltage Voo [V]
.-
TA= 25°C
\
.5
:& 200
:&
==
50
!>
250
~
i
,.
~
100
tJPOS2C43
~CMln
~
~ r---...
..........
0
!Q
g
~
50
o
1
,("
Supply Voltage VOO [V]
Note: Curves without "operation secured area" show relerence data.
4-257
III
~EC
JjPD8'OC39H 149H, JjPD49H
Functional Description
The ",PD80C39H I ",PD80C49H has the following functional blocks:
Instruction Decoder
The instruction decoder stores the operation code of
each instruction and converts it into outputs that control the functions of each block. These outputs control
the functions executed by the ALU, data source, and
specified registers.
Arithmetic Logic Unit (ALU)
The ALU receives 8-bit data from the 'accumulator or
temporary register and computes an 8-bit result under
control of the instruction decoder.
The ALU executes the following functions:
• Add with carry or add without carry
• Logical AND, OR, XOR
• Increment and decrement
• Bit complement
• Rotate left and right
• Swap nibbles
• BCD decimal correction
When a carry results from ALU overflows, the carry bit of
the program word is set.
counter exceed the built-in ROM area, the external program memory will be automatically accessed by
DBo-DB7, P20-P23, and PSEN.
Data Memory
The ",PD80C39H I ",PD80C49H has 128 words x 8 bits of
data memory that can be externally expanded 256
words maximum when needed.
RAM Address Register
The RAM address register specifies the next address to
be accessed in data memory.
Program Status Word
The PSW (figure 1) is an 8-bit status word containing the
information shown in table 1.
Figure 1.
Program Status Word
5
2
I I I I I I I I I
CY
AC
FO
BS
I
!
1
I
Stack save possible
52
I
51
SO
I
I
CYCarry
AC Auxiliary Carry
FO Flag 0
BS Register Bank Select
Stack Pointer
49-000561 A
Table 1.
Bits 0-2
Accumulator
PSW Bit Functions
Stack pOinter bits (SO-S2)
A RESET clears the stack pOinter to 0,
The accumulator is an 8-bit register that stores ALU input data and arithmetic results. It can also be used for
transferring data between 1/0 ports and memory.
Bit 3
Not used (1),
Bit 4
Working register bank switch bit (B8)
0= Bank 0
1=Bank 1
Temporary Register
Bit 5
The temporary register is an 8-bit register used for the
internal proceSSing necessary with arithmetic operations. The contents of the temporary register are input
to the ALU.
Flag bit (FO),
User-controlled bit that can be complemented, cleared, or
tested by conditional jump instruction JFO,
Bit 6
Auxiliary Carry (AC) ,
Generated by an auxiliary carry, ADD instruction, Can by used
by decimal adjust instruction DA A,
Bit 7
Carry flag (CY)
Indicates that an accumulator overflow has taken place with
the previously executed instruction,
Program Counter
The program counter is a 12-bit register that addresses
on-chip program memory. The program counter specifies the address of the next instruction to be executed.
Program Memory
The ",PD80C49H contains a mask-programmable ROM
of 2048 x 8 bits that can be addressed by a program
counter. The ",PD80C39H has no internal ROM, so it
uses external program memory. You can expand internal
program memory to 4096 bytes by connecting external
program memory. When the contents of the program
4-258
Conditional Branch logic
The conditional branch logic is used to test processor
conditions. Use a conditional jump instruction to test
the conditions shown in table 2.
Control Logic
The control logic generates or receives the signals that
control various functions including memory reads and
writes, interrupts, software STOP mode, resets, and external memory fetches.
NEe
Table 2.
~PD80C39H/49H,~PD49H
Branching Conditions
Test Device
Conditional Jump
Accumulator
All 0
Not all 0
Accumulator bit
Carry flag
Event Counter. When the T1 pin and counter input are
connected by the execution of a STRT CNT instruction,
the counter starts counting as an event counter. A
change in T1 from high to low causes a count signal
which increments the counter by +1. The maximum
speed of a count increment is one count per 3 machine
cycles. When a 12 MHz crystal is used, the maximum
speed is 1 count per 3.75 !As. There is no mimimum
speed. After a count signal the T1 input must be held low
at least 250 ns (at 12 MHz).
User flags (FO, F1)
Timer overflow flag
Test inputs (TO, T1)
Interrupt input (INT)
o
Reset Functions
A reset performs the following functions:
• Clears the program counter and the stack pointer
toO
• Selects register bank and memory bank 0
• Sets the data bus in a high impedance state
(except when EA is high)
• Sets ports 1, 2 in input mode
• Disables interrupts (timer and external)
• Stops the timer
• Clears the timer flag, FO, and F1
• Disables the clock output from TO
• Releases HALT and STOP modes
Timer/Event Counter
The timer / event counter can count external events in order to generate a precise time delay. The counter operation is the same in both modes, the only difference is
the input source.
The counter is an 8-bit binary up counter (figure 2) that
can be reset. It is possible to transfer the contents of the
timer to the accumulator and vice-versa by using the
MOV A, T and MOV T, A instructions, respectively. The
contents of the counter can be independently initialized
by the MOV T, A instruction. Use the STRT T instruction
to use the counter as a timer and the STRT CNT instruction to use the counter as an event counter.
Figure 2.
Once the counter starts, it continues counting until the
program executes a STOP TCNT instruction or RESET
becomes active. The counter is incremented up to the
maximum count (FFH) and overflows when the count
goes from FFH to OOH.
Timer/Event Counter
Timer. When an internal clock is connected with the
counter input by the execution of the STRT T instruction, the counter starts counting as a timer. When used
as a machine cycle clock, ALE is passed through a prescaler which generates an internal clock that increments the timer every 32 machine cycles. The prescaler
is reset during the execution of a STRT T instruction.
With a 12 M Hz crystal, the counter is incremented by +1
at each 25 kHz clock every 40 !As.
You can obtain a delay from 40 !As to 10 ms (256 counts)
by presetting the counter and detecting the overflow. To
obtain time" through software control, in excess of
10 ms, count overflows in a separate register. To count in
steps of 40 !As or less, an external clock can be supplied
to the T1 input which causes the counter to operate in
the event counter mode. Use the ALE frequency divided
by 3 or more for the external clock. Use a software delay
loop for fine adjustment of an extremely small or large
delay.
Ports 1 and 2 Latch and Buffer
Ports 1 and 2 are 8-bit input/output ports.The data written to the port by an output instruction is latched and
output and the data is maintained unless a new output
instruction is executed. Input data is not latched, so it is
necessary to stabilize input data when reading data by
an input instruction.
Several port-loading options are available. At the time
you order a mask ROM, {JAPD80C49H), you can designate the pullup resistors for port lines P10-P17, P20-P23,
and P24-P27.
XTAL+1S
Three types of pullup resistors are available:
49-OOO563A
Type 0
(IOH= -5f..1A: Voo= +5 V +10%)
Type 1
(lOH= -50 f..IA: Voo= +5 V +10%)
Type 2
No pullup resistor
4-259
t\'EC
~PD80C39HJ49H,~PD49H
Only type 0 pullup resistors are available with the
",PD80C39H.
Timing Logic
The oscillator generates a clock signal that controls all
system timing operations. Oscillation is generated by
either an external self-oscillating element or external
clock input. The oscillator acts as an internal high-gain
amplifier for serial resonance. To obtain the oscillation
frequency, an external LC network or a crystal or ceramic external resonator may be connected.
As the crystal frequency is lowered, there is an equivalent reduction in series resistance (R). As the
temperature of the crystal is lowered, R is increased.
Due to this relationship, it becomes difficult to stabilize
oscillation where there is low power supply voltage.
When Vee is less 'than 2.7 V and the oscillator frequency is 3 MHz or less, TA (ambient temperature)
should not be less than -10°C.
Standby Control
The standby control cirquitry allows .Iow power consumption operation. The standby function operates in 2
'
modes: HALT and STOP.
HALT Mode
In HALT mode, the oscillation circuit continues to operate but the internal clock stops. The CPU holds all the
status of the internal circuits just prior to execution of
the HALT instruction. In HALT mode, power consumption is much less than normal.
Setting HALT Mode. HALT mode is set by execution
of the HALT instruction and released by 'either INT or
RESET. If interrupts are disabled and INT becomes low
at a machine cycle right before the HALT instruction
and remains low during 2 machine cycles, the HALT instruction byte will be fetched and decoded, but the
HALT mode will not be set. Program operation resumes
from the instruction following the HALT instruction.
If interrupts are enabled under the same conditions as
above, the HALT instruction byte will be fetched and decoded but the HALT mode will not be set and the program will jump to the interrupt start address, After
returning from the interrupt routine, the program will
continue from the instruction following the HALT instruction.
Releasing HALT Mode. Release HALT mode by activating INT or RESET. When using INT to release HALT
mode, a low level is present at the INT pin and the internal clock is restarted. If interrupts are enabled, the interrupt is executed after the first instruction following the
HALT instruction.
4-260
In the interrupt enable state, hold the INT pin low until
the interrupt procedure is started to ensure the interrupt.
When using RESET to release HALT mode, a low level is
present at the RESET pin and the HALT mode is reset
and a normal reset operation is executed. When RESET
goes to a high level, the program starts from address O.
STOP Mode
In STOP mode, the oscillator stops and only the contents of RAM are maintained. Power consumption is
lower than that of the HALT mode. You can set the STOP
mode with hardware, by controlling the RESET and
STOP pins; and by software, by executing the corresponding instruction.
Hardware STOP Mode
In hardware STOP mode, the contents of RAM can be
held at a voltage as low as +2.0 V.
To set hardware STOP mode, set the RESET pin to a low
level to protect the contents of RAM. Set the STOP pin to
a low level to stop operation of the oscillation circuit.
To release hardware STOP mode, apply the normal operating level ( +2.5 V to +6.0 V) to the power supply at the
VDD pin. As figure 3 shows, set the STOP pin to a high
level while holding the RESET pin at a low level. This will
restart the oscillation circuit. When RESET is set high
after oscillation circuit operation is stabilized, the program is started from address OOOH. Because the STOP
pin controls oscillator operation, be careful to protect
the STOP pin from noise.
When power is turned on, or when STOP mode is
released, the oscillation circuit restarts. Because the
crystal or ceramic resonator utilizes mechanical vibration, a certain time is required for the oscillation to stabilize. The "t" represents the oscillation stabilizing wait
time in the timing waveform.
During this wait time, it is necessary to stop instruction
execution in order to prevent CPU errors, Therefore, "t"
must be longer than the oscillator's stabilizing time.
Figure 3.
Oscillator Stop and Start
Oscillation Start
4-r
'---------'t 'r
R'''~
STOP
4iH)()()566A
NEe
~PD80C39H'49H,~PD49H
Oscillation stabilizing time differs somewhat by the
type of oscillator used. With a 6 MHz oscillation frequency, a crystal resonator needs several milliseconds
to stabilize, while a ceramic resonator needs several
hundred microseconds. Figure 4 shows how to easily
control the hardware STOP mode by externally connecting a capacitor to the RESET pin. This allows control of
the oscillation stabilizing time.
Figure 4.
Hardware STOP Mode Control Circuit
+ External
- Capacitor
-----~---<><
I - - - - - ¢ STOP
49-000567A
Software STOP Mode
In software STOP mode, the oscillation circuits stop,
but the CPU maintains all status of internal circuits and
data existing just before the STOP instruction. Software
STOP mode is the same as when the oscillation circuit
stops in HALT mode.
causes SS to go to a high level. Then, program execution restarts. The time it takes for SS to reach the threshold of a logic 1 determines the oscillation stabilizing
wait time.
After software STOP mode is released, if interrupts are
disabled as in the HALT mode, program execution is resumed from the instruction following the STOP instruction. If interrupts are enabled, the interrupt procedure is
initiated (address 003H) after the execution of 1 instruction following the STOP instruction. To assure the interrupt, hold INT at a low level until the interrupt procedure
is initiated. Even with short low level timing, the interrupt procedure will be assured if you place a 1-machine
cycle instruction afterthe STOP instruction. However, it
is recommended that you hold INT low for at least 2 machine cycles.
When using the RESET input, a low level at the RESET
pin resets the software STOP flip-flop. The oscillator
starts and the SS pin goes to a high level as Css is
charged. The program starts from address OOOH when
RESET goes high. Also, since..!!!,e oscillation stabilizing
wait time is generated when SS is low, the RESET pin
should be held low longer than the SS pin. When the oscillation stabilizing wait time is obtained by the externally connected capacitor, the value of the capacitor
(CRST) connected to the RESET pin (figure 4) should be
set at least 3 times larger than that of capacitor CSS
connected to the SS pin. For example, if Css is set to
O.33/-lF, CRST should be 1/-lF.
When no capacitor is connected to the SS pin, the low
level time of the RESET pin should be set to a value
larger than the oscillation stabilizing time and SS
should be open or pulled up with a 1 k or more resistor.
In software STOP mode, if a capacitor (Css) is connected to the SS pin as shown in figure 5, you can obtain
the oscillation stabilizing wait time when releasing
STOP mode.
Setting Software STOP Mode. To set software STOP
mode, execute the STOP instruction. This sets the internal software STOP mode flip-flop which stops the oscillator and turns transistors A and B off and on,
respectively. Capacitor Css discharges through transistor B causing the SS pin to go low.
Releasing Software STOP Mode. To release software
STOP mode, apply an INT or RESET input.
When using the INT input (figure 6), a low at the INT pin
resets the software STOP flip-flop and turns transistors
A and B on and off, respectively. Then the oscillator restarts, but since SS is still low, program execution remains stopped. With transistor A on, Css charges and
4-261
II
~
NEe
~PD80C39HI49H,~PD49H
Figure 5.
Software STOP Mode Control Circuit
Figure 6.
Software STOP Mode Timing
55---""
Software
STOPF/F
ffiff------~------_f!~----~
r---+----------
Execution of STOP
Instruction
Oscillation
Stabilizing
Wait Time
49-000569A
"Execution of instruction
4-262
49-OOO568A
Instruction Set
Mnemonic
Operation
Description
ADD A, # data
(A) -
Add immediate the specified data to the accumulator. (2)
ADDA, Rr
(A) - (A) + (Rr) for
r = 0-7
ADDA, @Rr
Hex
Code
Operation Code
D7
De
Ds
D4
D3
D2
D1
Do
03
0
dl
0
d6
0
d5
0
d4
0
d3
0
d2
1
d1
1
do
Add contents of designated register to the accumulator.(2)
6n(4)
0
1
1
0
1
(A) - (A) + ((Rr)) for
r = 0-1
Add indirect the contents the data memory location to the
accumulator.(2)
6n(4)
0
0
0
0
0
ADDC A, # data
(A) -
Add immediate with carry the specified data to the accumulator. (2)
13
0
dl
0
d5
1
d4
0
d3
0
d2
1
d1
ADDC A, Rr
(A) - (A) + (C) + (Rr)
for r = 0-7
Add with carry the contents of the designated register to the
accumulator.(2)
7n(4)
0
1
1
1
ADDCA,@Rr
(A) - (A) + (C) + ((Rr))
for r = 0-1
Add indirect with carry the contents of data memory location to the
accumulator. (2)
7n(4)
0
0
0
0
ANLA, # data
(A) -
Logical AND specified immediate data with accumulator.
53
0
dl
1
d6
0
d5
1
d4
0
d3
0
d2
1
d1
ANLA, Rr
(A) - (A) AND (Rr) for
r = 0-7
Logical AND contents of designated register with accumulator.
5n(4)
0
1
0
1
1
ANLA, @Rr
(A) - (A) AND ((Rr))
forr = 0-1
Logical AND indirect the contents of data memory with
accumulator.
5n(4)
Accumulator
(A) + data
(A) + (C) + data
(A) AND data
CPLA
(A) -NOT(A)
Complement the contents of the accumulator.
37
0
0
(A)-O
Clear the contents of the accumulator.
27
0
0
1
Decimal adjust the contents of the accumulator. (2)
57
0
1
0
DECA
(A)-(A)-1
Decrement by 1the accumulator's contents.
07
0
0
0
0
1
0
0
0
1
do
0
,.a
1=
(A)-(A)+1
Increment by 1the accumulator's contents.
17
0
0
0
1
0
1
(A) -
(A) OR data
Logical OR specified immediate data with accumulator.
43
0
dl
1
d6
0
d5
0
d4
0
d3
0
d2
1
d1
ORLA, Rr
(A) -
(A) OR (Rr) for r
Logical OR contents of designated register with accumulator.
4n(4)
0
1
0
0
1
ORLA, @Rr
(A) - (A) OR ((Rr)) for
r = 0-1
Logical OR indirect the contents of data memory location with
accumulator.
4n(4)
0
0
0
0
0
0
RLA
(AN +1) - (AN)
(Ao) - (Al) for N = 0-6
Rotate accumulator left by 1 bit without carry.
E7
0
0
RLCA
(AN + 1) - (AN); N = 0-6
(Ao)-(C)
(C)-(Al)
Rotate accumulator left by 1 bit through carry.
F7
(AN) - (AN + 1); N = 0-6
(Al) -(Ao)
Rotate accumulator right by 1 bit without carry.
0
~
~
1
do
0
INCA
= 0-7
Bytes
0
ORLA, # data
RRA
I
I\)
0
CLRA
DAA
~
0
d6
Cycles
1
1
do
CD
0
n
W
CD
....:z
~
CD
..:z
,.a
1=
77
0
0
~
CD
:z
(J)
(,.)
I!I
~
I\J
Instruction Set (cont)
1:
(J)
~
Operation Code
Hex
Code
D7
67
0
Operation
Description
(AN) - (AN + 1); N = 0-6
(A7)-(C)
(C)-(Aa)
Rotate accumulator right by 1 bit through carry.
SWAP A
(A4-A7)-- (Aa-A3)
Swap the 2 4-bit nibbles in the accumulator.
47
0
XRL A, # data
(A) -
Logical XOR specified immediate data with accumulator.
D3
1
d7
XRLA, Rr
(A) - (A) XOR (Rr) for
r = 0-7
Logical XOR contents of deSignated register with accumulator.
Dn(4)
1
XRLA, @Rr
(A) - (A) XOR ((Rr)) for
r = 0-1
Logical XOR indirect the contents of data memory location with
accumulator.
Dn(4)
(Rr) - (Rr) - 1; r = 0-7
If (Rr) "'0;
(PCa-PC7) - addr
Decrement the specified register and test contents.
(PCa-PC7) - addr if Bb = 1
(PC) - (PC) + 2 if Bb = 0
Jump to specified address if accumulator bit is set.
(PCa-PC7) - addr if C = 1
(PC) - (PC) + 2 if C = 0
Jump to specified address if carry flag is set.
(PCa-PC7) - addr if FO = 1
(PC) - (PC) + 2 if FO = 0
Jump to specified address if flag FO is set.
(PCa-PC7) - addr if F1 = 1
(PC) - (PC) + 2 if F1 = 0
Jump to specified address ifflag F1 is set.
Mnemonic
De
D5
D4
D3
0
0
D2
D1
Do
Cycles
Bytes
Accumulator (cont)
RRCA
(A) XOR data
JBb addr
JC addr
JFO addr
JF1 addr
JMP addr
W
CG
0
0
0
1
d6'
0
d5
1
d4
0
d3
1
0
1
1
0
...
."
....Z
0
d2
1
d1
1
da
CG
Z
1:
0
0
0
a3
r
a2
r
a1
r
aa
0
CG
(PCs-PC1a) - (addrs-addr1a) Direct jump to specified address within the 2K address block.
(PCa-PC7) - (addra-addr7)
(PC11) -DBF
JMPP@A
(PCa-PC7) -
JNC addr
(PCa-PC7) - addr if C = 0
(PC) - (PC) + 2 if C = 1
JNI addr
JNT1 addr
JNZ addr
((A))
- addr if I = 0
(PC) + 2 if I = 1
(PCa~PC7)
(PC) JNTO addr
0
CD
0
n
Branch
DJNZ Rr, addr
"
En
x2(6)
76
x4(6)
B3
E6
Jump to specified address if test 0 is low.
(PCa-PC7)- addr ifT1 = 0
(PC) - (PC) + 2 ifT1 = 1
Jump to specified address if test 1 is low.
(PCa-PC7) - addr if A '" 0
(PC) - (PC) + 2 if A = 0
Jump to specified address if accumulator is non-zero.
a5
b2
a7
b1
a6
ba
a5
a4
0
a3
0
a2
a1
0
aa
a7
a6
a5
a4
0
a3
a2
a1
0
aa
a7
0
a6
a5
1
a4
0
a3
1
a2
a1
0
aa
0
a7
a6
1
a5
a4
0
a3
a2
a1
0
aa
a1Q
a7
ag
a6
as
a5
0
a4
0
a3
a2
0
a1
0
aa
0
0
0
a3
a2
a1
0
aa
B6
Jump to specified address if carry flag is low.
(PCa-PC7) - addr if TO = 0
(PC) - (PC) + 2 if TO = 1
a6
F6
Jump indirect to specified address with address page.
Jump to specified address if interrupt is low.
a7
0
a4
0
a7
a6
a5
0
a4
a7
0
a6
0
a5
0
a4
0
a3
a2
a1
0
aa
0
a7
0
a6
a5
0
a4
0
a3
1
a2
a1
0
aa
0
a7
a6
0
a5
0
a4
0
a3
a2
a1
0
aa
a7
0
a6
0
a5
1
a4 '
0
a3
1
a2
a1
0
aa
86
26
46
96
Z
2
2·
~
~
Instruction Set (cont)
Hex
Code
Operation
Description
JTF addr
(PCa-PC7) - addr if TF = 1
(PC) - (PC) + 2 ifTF = 0
Jump to specified address if timer flag is set to 1.
16
JTO addr
(PCa-PC7) - addr if TO = 1
(PC) - (PC) + 2 if TO = 0
Jump to specified address if test 0 is a 1.
36
(PCa-PC7) - addr ifT1 = 1
(PC) - (PC) + 2 ifT1 = 0
Jump to specified address if test 1 is a 1.
(PCa-PC7) - addr if A = a
(PC) - (PC) + 2 if A = 1
Jump to specified address if accumulator is O.
Mnemonic
Operation Code
D7
De
Ds
D4
Da
D2
D1
Do
0
a7
0
a5
a4
0
a3
a6
0
a7
a2
a1
aO
0
a6
a5
1
a4
0
a3
1
a2
a1
ao
0
a7
a6
0
a5
a4
0
a3
a2
a1
ao
a7
1
a6
a5
0
a4
0
a3
a2
a1
ao
0
0
0
a
0
0
0
0
a
0
0
Branch (cont)
JT1 addr
JZ addr
56
C6
a
Cycles
Bytes
~~
Control
EN I
Enable the external interrput input.
05
DIS I
Disable the external interrupt input.
15
0
ENTO ClK
Enable the clock output pin TO.
75
0
SEl MBO
(DBF) -0
Select bank 0 (locations 0-2047) of program memory.
E5
SEl MB1
(DBF)-1
Select bank 1(locations 2048-4095) of program memory.
F5
SEl RBO
(BS)-O
Select bank 0 (locations 0-7) of data memory.
C5
SEl RB1
(BS)-1
0
Select bank 1 (locations 24-31) of data memory.
D5
HALT
Initiates halt mode.
01
0
STOP
Sets CPU to software stop mode.
82
0
Move immediate the specified data into the accumulator.
23
1
0
0
0
a
a
0
0
0
0
0
0
a
0
0
d3
0
d2
0
0
0
Data Moves
MOV A, # data
MOV A, Rr
(A) -data
(A) -
.j:>.
= 0-7
MOVA,@Rr
(A) -
MOVA, PSW
(A)-(PSW)
MOV Rr, # data
(Rr) -
data; r
MOV Rr, A
(Rr) -
(A); r
MOV@Rr,A
((Rr)) -
MOV @ Rr, # data ((Rr)) -
I
I\)
(Rr); r
MOV PSW, A
((Rr)); r
= 0-1
= 0-7
= 0-7
(A); r = 0-1
data; r = 0-1
(PSW)-(A)
Move the contents of the designated registers into the
accumulator.
Fn(4)
Move indirect the contents of data memory location into the
accumulator.
Fn(4)
0
d7
0
d6
1
d5
0
d4
1
1
1
1
1
d1
1
da
1::
'11
D
CD
0
0
Move contents of the program status word into the accumulator.
C7
Move immediate the specified data into the designated register.
Bn(4)
1
d7
Move accumulator contents into the designated register.
An(4)
1
Move indirect accumulator contents into data memory location.
An(4)
Move immediate the specified data into data memory.
Bn(4)
Move contents of accumulator into the program status word.
D7
0
0
0
0
d6
1
d5
1
d4
1
d3
0
1
0
1
0
0
0
n
0
W
CD
r
d2
r
d1
0
0
0
a
1
d7
0
d6
1
d5
1
d4
0
d3
0
d2
d1
1
1
0
1
0
1
1
r
do
:z
....
~
CD
..:z
r
do
1::
'11
D
~
CD
:z
0>
(]I
I!I
.J:>.
I
Instruction Set (cont)
1::
N
0>
0>
Mnemonic
Operation
Description
Hex
Code
Operation Code
D7
De
Ds
D4
D3
D2
D1
Do
MOVPA, @A
(PCO-PC7) - (A)
(A)-((PC))
Move data in the current page into the accumulator.
A3
MOVP3A,@A
(PCO-PC7) - (A)
(PCa-PC11) - 0011
(A)-((PC))
Move program data in page 3 into the accumulator.
E3
MOVXA, @R
(A) -
MOVX@R,A
((Rr)) -
XCH A, Rr
(A)- (Rr): r
XCHDA,@Rr
Bytes
"C
Q)
0
Data Moves (cont)
XCH A,@Rr
Cycles
0
((Rr)): r
= 0-1
Move indirect the contents of external data memory into the
accumulator.
8n(4)
0
(A): r
= 0-1
Move indirect the contents of the accumulator into external data
memory.
9n(4)
0
= 0-7
(A)- ((Rr)): r = 0-1
Exchange the accumulator and designated register's contents.
2n(4)
Exchange indirect contents of accumulator and location in data
memory.
2n(4)
(Ao-A3)- ((Rr))o-((Rr)l3:
r = 0-1
Exchange indirect 4-bit contents of accumulator and data memory.
3n(4)
0
0
0
n
0
0
0
0
Q
0
0
0
0
0
0
0
0
W
CD
:I:
.....
,.
1::
,."
C
0
0
1
0
0
0
0
0
0
0
0
0
CD
..:I:
CD
:I:
Flags
CPLC
(C) -NOT(C)
Complement contents of carry bit.
A7
0
CPL FO
(FO) -
NOT (FO)
Complement contents of flag FO.
95
0
CPL F1
(F1) -
NOT (F1)
Complement contents of flag F1.
85
0
0
0
0
1
0
0
0
0
CLR C
(C)-O
Clear contents of carry bit to O.
97
0
0
0
1
CLR FO
(FO)-O
Clear contents of flag 0 to O.
85
0
0
0
0
CLR F1
(F1)-0
Clear contents of flag 1to O.
A5
0
0
0
0
Logical AND immediate specified data with contents of bus.
98
Input! Output
(bus) AND data
d7
0
d6
0
d5
d4
1
d3
0
d2
0
d1
do
9n(5)
1
d7
0
d6
0
d5
1
d4
1
d3
0
d2
P
d1
P
do
Logical AND contents of accumulator with deSignated port (4-7).
9n(5)
1
0
0
1
1
1
P
P
Input data from designated port (1-2) into accumulator.
On(5)
0
0
0
0
0
08
0
0
0
0
0
0
0
On(5)
0
0
0
0
ANL BUS,
# data
(bus) -
ANL Pp,
# data
(Pp) - (Pp) AND data
p = 1-2
Logical AND immediate specified data with designated
port (1 or 2).
ANLD Pp, A
(Pp) .,- (Pp) AND (Ao-A3):
P = 4-7
(Pp): p = 1-2
IN A, Pp
(A) -
INS A, BUS
(A) -(bus)
MOVD A, Pp
(Ao-A3) (A4-A7) -
(Pp): p = 4-7
0
Input strobed bus data into accumulator.
Move contents of designated port (4-7) into accumulator.
~
n
Instruction Set (cont)
Mnemonic
Operation
Description
Hex
Code
Move contents of accumulator to designated port (4-7).
3n(5)
Operation Code
D7
D6
Ds
D4
D3
D2
D1
Do
0
d1
0
do
Inputl Output (cont)
MOVD Pp, A
(Pp) -
ORl BUS,
(bus) -
(AO-A3); p = 4-7
(bus) OR data
logical OR immediate specified data with contents of bus.
0
88
1
d7
0
d6
0
d5
0
d4
1
d3
0
d2
# data
ORlD Pp, A
(Pp) - (Pp) OR (Ao-A3);
P = 4-7
logical OR contents of accumulator with designated port (4-7).
8n(5)
1
0
0
0
1
1
ORl Pp,
(Pp) - (Pp) OR data
p = 1-2
logical OR immediate specified data with designated port (1-2).
9n(5)
# data
1
d7
0
d6
0
d5
0
d4
1
d3
0
d2
P
d1
P
do
OUTl BUS, A
(bus) -(A)
Output contents of accumulator onto bus.
0
0
0
0
1
0
1
0
0
a1
ao
(Pp) -
(A); P = 1-2
DEC Rr
(Rr) -
(Rr) - 1; r
INC Rr
(Rr) -
(Rr) + 1; r
INC@Rr
((Rr))-((Rr)) +1;
r = 0-1
OUTl Pp,A
02
0
0
Output contents of accumulator to designated port (1-2).
3n(5)
0
0
Decrement by 1 contents of designated register.
Cn(4)
Increment by 1 contents of designated register.
1n(4)
0
0
Increment indirect by 1the contents of data memory location.
1n(4)
Cycles
Bytes
~
~
P
Registers
= 0-7
= 0-7
1
0
0
0
ag
a6
a8
a5
0
Subroutine
CAlladdr
x4(6)
((SP)) - (PC), (PSW4-PSW7) Call designated subroutine.
(SP) - (SP) + 1
(PC8-PC10) - (addr8-addr10)
(PCO-PC7) - (addro-addr7)
(PC11) - DBF
RET
(SP) - (SP) - 1
(PC) -((SP))
Return from subroutine without restoring program status word.
83
RETR
(SP) - (SP) - 1
(PC) - ((SP))
(PSW4-PSW7) - ((SP))
Return from subroutine restoring program status word.
93
a10
a7
a4
0
a3
0
a2
0
1:
"a
0
Q)
0
n
Timer I Counter
W
EN TCNTI
Enable internal interrupt flag for timer I counter output.
25
DIS TCNTI
Disable internal interrupt flag for timer / counter output.
35
0
0
0
0
0
0
1
MOVA, T
(A)-(T)
Move contents of timer I counter into accumulator.
42
0
0
0
0
0
MOVT, A
(T)-(A)
Move contents of accumulator into timer / counter.
62
0
1
0
0
0
STOP TCNT
Stop count for event counter.
65
0
0
0
STRTCNT
Start count for event counter.
45
0
STRTT
Start count for timer.
55
0
~
0
0
0
0
CD
....:z:
~
CD
0
..:z:
1:
"a
~
CD
I
I\)
:z:
en
.......
I!
~
N
0>
1::
Instruction Set (cont)
00
Mnemonic
Operation
Description
Operation Code
Hex
Code
D7
D6
D5
00
0
0
0
D4
D3
D2
D1
Do
0
0
0
0
Cycles
Bytes
Misce"aneous
NOP
No operation performed.
"oI:»
C»
n
w
U)
Note:
(1) Binary instruction code designations rand p represent encoded values or the lowest-order bit value of specified registers and ports, respectively.
(2) Execution of the ADD, ADDC, and DA instructions affect the carry flags, which are not shown in the respective function equations. These instructions set the carry flags when there is an
overflow in the accumulator (the auxiliary carry flag is set when there is an overflow of bit 3 of the accumulator) and clear the carry flags when there is no overflow. Flags that are specifically
addressed by flag instructions are shown in the function equations for those instructions.
(3) References to addresses and data are specified in byte 1 and/or 2 in the opcode of the corresponding instruction.
....:z:....
CD
..:z:
1::
"....I:»
(4) The hex value of n for specific registers is as follows:
a) Direct addressing
R4:n = C
R6:n = E
RO: n = 8
R2: n = A
R1: n = 9
R3: n = B
R5: n = D
R7: n = F
b) Indirect addressing
@ RO: n = 0
@ R1: n = 1
CD
:z:
(5) The hex value of n for specific ports is as follows:
Pt n = 9
P4: n = C
P6: n = E
P2: n = A
P5: n = D
P7: n = E
(6) The hex value of x for specific accumulator or address bits is as follows:
a) JBb instruction
B4 :x = 9
Bo: x = 1
B2: x = 5
D
B6:X
B7 :x = F
B1: x = 3
B3: x = 7
B5:x = B
b)JMP instruction
Page 4: x = 8
Page 0: x = 0
Page 2: x = 4
Page 6: x
C
Page 3: x = 6
Page 1: x = 2
Page7:x = E
Page 5: x = A
c) CALL instruction
Page 0: x = 1
Page 2: x = 5
Page 4: x = 9
Page 6: x = D
Page t x = 3
Page 3: x = 7
Page 5: x = B
Page 7: x = F
=
=
~
~
NEe
~PD80C39HI49H,~PD49H
Symbol Definitions
Symbol
Description
Symbol
Description
A
Accumulator
SP
AC
Auxiliary carry flag
T
Timer
Program memory address (ao-a?) or (aO-a10)
TF
Timer flag
addr
Accumulator bit (b=0-7)
BS
TO, T1
Stack pOinter
Testable flags 0, 1
Bank switch
#
Prefix for immediate data
BUS
Bus port
@
Prefix for indirect address
C
Carry flag
ClK
Clock signal
CNT
Event counter
data
Number or expression (8 bits)
DBF
Memory bank flip-flop
Indicates the hex number corresponding to the
accumulator bit or page number specified in the
operand
(x)
Contents of external RAM location
((x))
Contents of memory location addressed by the
contents of external RAM location
FO, F1
Flags 0,1
INT
Interrupt
AND
logical product (logical AND)
Indicates the hex number of the specified register
or port
OR
logical sum (logical OR)
PC
Program counter
Pp
Port designator (p = 1, 2 or 4-7)
PSW
Rr
Replaced by
XOR
Exclusive-OR
Complement
Program status word
Register designator (r = 0-7)
4-269
~PD80C39H/49H,~PD49H
4-270
NEe
NEe
NEe Electronics Inc.
pPD80C40H/50H,pPD50H
HIGH-SPEED, 8-BIT, SINGLE-CHIP
CMOS MICROCOMPUTERS
Pin Configurations
Description
The J.lPD80C40H, J.lPD80C50H, and J.lPD50H are singlechip, CMOS 8-bit microcomputers containing an 8-bit
CPU, ROM (J.lPD80C50H only), RAM, I/O ports, and control circuitry. Through CMOS technology, the devices
can retain data with low power consumption. In addition, the processor uses two standby modes (HALT and
STOP) to further minimize power drain.
40-Pin Plastic DIP
TO
XTAL1
XTAl2
RESET
55
Features
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
EA
AD
98 instructions
1.25 J.ls instruction cycle time (12 M Hz crystal)
Addition, logic, and decimal adjust functions
2K x 8-bit ROM (J.lPD80C50H)
256 x 8-bit RAM
Standby function
8-1 eve I stack
Two sets of working registers
Interrupt capability
Two test inputs
Internal timer/event counter
Input/output ports (8 bits x 2)
- Data bus alternative to I/O ports (8 bits x 1)
Expandable memory and I/O ports
Single-step function
Internal clock generator
CMOS technology
Single power supply of +2.5 V to +6.0V
Inte18050H,8040H pin compatible
PSEN
49-00047BA
44-Pin Plastic Miniflat
STOP
Ordering Information
Part
Number
Package Type
DB2
P11
ROM
pPD80C40HC
40-pin plastic DIP
12 MHz
None
pPD80C50HC
40-pin plastic DIP
12 MHz
2K x 8 bits
pPD50HG-22
44-pin plastic
12 MHz
2K x 8 bits
miniflat
DB3
0
P10
Max Frequency
of Operation
P1s
DB1
P12
DBo
P13
ALE
P1s
ViR
i>SEN
NC
RD
P14
pPD50HG
P16
EA
P17
iNT
55
P24
13
0
z
19
16
~ '"
~
... «...'"
«
~
~
>< ><
22
0
Z
Ii
83-002790A
4-271
NEe
pPD80C40H/50H,pPD50H
Pin Functions
Pin Identification
Symbol
Function
TO
Test 0 input / clock output
XTAL1
Crystal 1input
XTAL2
Crystal 2 input
RESET
Reset input
SS
Single step input
INT
Interrupt input
EA
External access input
RD
Read output
PSEN
Program store enable output
WR
Write output
ALE
Address latch enable output
DBO-DB?
Bidirectional data bus
Vss
Ground
P20-P2?
Quasi-bidirectional port 2
XTAL1, XTAL2 (Crystals 1, 2)
XTAl1 and XTAl2 are the crystal inputs for the internal
clock oscillator. XTAl1 is also used as an input for external clock signals.
TO (Test 0)
The JTO and JNTO instructions test the levelof TO and,
as a result, the program address jumps to the specified
address. TO becomes a clock output when the ENTO
ClK instruction is executed.
T1 (Test 1)
The JT1 and J NT1 instructions test the level of T1 and, as
a result, the program address jumps to the specified address. T1 becomes an internal counter input when the
STRT CNT instruction is executed.
PROG
Program output
RESET (Reset)
STOP
Stop input
P10-P1?
Quasi-bidirectional port 1
T1
Test 1input
Voo
Power supply
RESET initializes the processor and is also used to verify the internal ROM. RESET determines the oscillation
stabilizing time during the release of STOP mode. The
RESET pulse width requires at least 5 machine cycles
when the supply voltage is within specifications and
the oscillation frequency is stable. (Active low).
4-272
NEe
pPD80C40H/50H,pPD50H
SS (Single Step)
DBO-DB7 (Data Bus)
SS causes the processor to execute the program one
step at a time. SS also determines the oscillation stabilizing time during the release of the software STOP
mode.
DBa-DB? is a bidirectional port. DBa-DB? reads and
writes data using RD and WR for latching. During an external program memory fetch, DBa-DB? output the loworder eight bits of the memory address. PSEN fetches
the instruction. DBa-DB? also output the address of an
external data memory fetch. The addressed data is read
and written by RD and WR.
INT (Interrupt)
INT starts an interrupt if interrupts are enabled. A reset
disables an interrupt. INT can be tested with the JNI instruction and, depending on the results, a jump to the
specified address can occur.
P10-P17 (Port 1)
P10-P1? is an 8-bit quasi-bidirectional port.
EA (External Access)
P20-P27 (Port 2)
EA disables internal program memory and fetches and
accesses external program memory. EA is used for system testing and debugging. (Active high).
P20-P2? is an 8-bit quasi-bidirectional port. P20-P23
output the high-order four bits of the address during an
external program memory fetch. P20-P23 also function
as a 4-bit 110 bus for the f.tPD82C43 110 port expander.
RD(Read)
RD enables a data read from external memory. (Active
low).
PROG (Program Pulse)
PROG is used as an output pulse during a fetch when
interfacing with the J.lPD82C43 1/0 port expander.
WR(Write)
WR enables a data write to external memory.
PSEN (Program Store Enable)
PSEN fetches instructions only from external program
memory. (Active low).
STOP (Stop)
STOP controls the hardware STOP mode. STOP stops
the oscillator when active low.
Voo (Power Supply)
VDD is the positive power supply ( +2.5 V to +6.0 V).
ALE (Address Latch Enable)
ALE occurs at each cycle. The falling edge of ALE addresses external data memory or external program
memory. ALE can also be used as a clock output.
Vss (Ground)
Vss is ground potential.
4-273
NEe
pPD80C40H/50H,pPD50H
Block Diagram
Data Memory
256 x 8 RAM
XTALI
Register 0-7
8 - Level Stack
(Variable Length)
XTAL2
Optional Second
Register Bank
Data Store
ALE
EA
PROG
1-----T1
Power
Supply
{
Vee -
+2.5-+6.0V
Vss -
GND
49·0004796
Absolute Maximum Ratings
DC Characteristics
TA=25°C
Power supply voltage, lJoo
Vss -0.3Vto +7V
Input voltage, VI
Vss -0.3VtoVoo +0.3V
Output voltage, Vo
Vss - 0.3 V to Voo +0.3 V
Operating temperature, TOPT
Storage temperature, TSTG
Comment: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits. described in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
4-274
Standard Voltage Range
TA= -400Cto +85°C, VOD= +5V±10%, VSS=OV
Limits
Parameter
Symbol
Min
Typ
Max
Unit
Test
Conditions
Input voltage
low
VIL
-0.3
+0.8
V
Input voltage
high
VIH
Voo-2
Voo
V
Except XTAL1,
XTAL2, RESET, SS
VIH1
Voo-1
Voo
V
RESET, XTAL1,
XTAL2, SS
+0.45
V
10L =2.0 mA
Output voltage
low
VOL
Output voltage
high
VOH
2.4
V
Bus, RD, WR,
PSEN, ALE, PROG,
TO; 10H= -400/AA
VOH1(1)
2.4
V
10H = - 5 /AA (type
0) port 1, port 2
2.4
V
10H= -50/AA
(type 1) port 1, port
2
NEe
pPD80C40H/SOH,pPD50H
DC Characteristics (cont)
Extended Voltage Range (cant)
TA= -40°cto +85°c,Voo= +2.5Vto +6.0V,Vss=ov
Standard Voltage Range (cant)
Limits
TA= -40°cto +85°c, Voo= +5V±10%, Vss=OV
Parameter
Limits
Parameter
Input current
Symbol
Min
IILP(1)
Typ
Max
Unit
-15
-40
/1 A
IILC
-500
J.lA
-40
/1 A
Test
Conditions
Port 1, port 2;
VIL (type 0)
VI~
Port 1, port 2;
VIL (type 1)
VI~
SS, RESET;
Output leakage
current
±1
IU1
±3
J.lA
EA; VSS~VI~VOO
ILO
±1
J.lA
VSs~Vo~VOO
High impedance,
bus, TO(3)
Unit
IU1
±1
J.lA
1U2
±5
J.lA
EA; VSS~VI~VOO
ILO
±1
J.lA
VSs~Vo~VOO
1.5
6
100
VOOOR
3.0
mA
tCy=1.25J.ls
20
J.lA
(2)
18
mA
tCy=1.25/1s
2.0
V
T1, INT, STOP;
VSS~VI~VOO
High impedance,
bus, TO (3)
0.3
0.6
mA
Voo=3V;
tCY= 5 J.ls
2.0
4.0
mA
Voo=6V
tCy=1.25J.ls
20
J.lA
(2);Voo=3V
50
J.lA
Voo=6V
2.0
5.0
mA
Voo=3V;
tCY= 5/1s
10
20
mA
Voo=6V;
tCy=1.25J.ls
1002(5)
Supply current
Test
Conditions
Max
T1, INT, STOP;
1U2
1002(5)
Data retention
voltage
Typ
VSS~VI~VOO
Standby current 1001(4)
Supply current
(total)
J.lA
Output leakage
current
Min
Standby current 1001(4)
VI~VIL
Input leakage
current
Input leakage
current
Symbol
100
Note:
At hardware STOP
mode (STOP,
RESET ~ 0.4 V) or
RESET
(RESET~O.4 V)
(1) Types 0, 1, and 2 options can be specified for IJPD80C50H.
Type 0 for IJPD80C40H only.
E
(2) Input pin voltage is VI~VIL orVI~VIH'
(3) Includes port 1and port 2 pins optionally specified with type 2.
(4) HALT mode.
(5) STOP mode.
Extended Voltage Range
AC Characteristics
TA = -400cto +85°c, Voo = +2.5Vto +6.0 V, Vss=OV
Limits
Parameter
Symbol
Input voltage
low
VIL
Input voltage
high
VIH
VIH1
Output voltage
low
VOL
Output voltage
high
VOH
Input current
Min
Typ
-0.3
Max
Unit
TA= -40°C to +85°c, Vss=OV
Limits
Test
Conditions
+0.18Voo V
0. 7V OO
VOO
0. 8V OO
V
VOO
V
+0.45
V
0. 75V oo
V
Except XTAL1,
XTAL2, RESET, SS
RESET, XTAL1,
XTAL2, SS
IOL=1.0mA
Bus, RD, WR,
PSEN, ALE, PROG,
TO; 10H= -100J.lA
VDD=
t5V±100f0
VDD=
2.5Vto&.OV
Min
Parameter
Symbol
Min
Max
Cycle time
150
Max
Test
Unit Conditions
tCY
1.25
ALE pulse width tLL
125
995
J.ls
(1)
Address setup
before ALE
tAL
140
890
ns
(1)
Address hold
from ALE
tLA
45
295
ns
(1)
Control pulse
width (RD, WR)
tCC1
425
2300
ns
(1)
150
J.ls
VOH1(1) O.7VOO
V
10H = -1 J.lA (type
0) port 1, port 2
Control pulse
width (PSEN)
tCC2
300
1800
ns
(1)
0. 7V OO
V
10H = -10 J.lA (type
1) port 1, port 2
Data setup
beforeWR
tow
340
1965
ns
(1)
-40
J.lA
Port 1, port 2;
VIL (type 0)
VI~
Data hold after
WR
two
45
295
ns
(2)
-500
J.lA
Port 1, port 2;
VIL (type 1)
VI~
Data hold after
RD, PSEN
tOR
95
470
ns
(1)
-40
/1 A
SS, RESET;
RD to data in
tR01
300
1800
ns
(1)
IILP(1)
IILC
-15
VI~ VIL
4-275
t\'EC
pPD80C40H/SOH, pPDSOH
AC Characteristics (cont)
Note:
TA = - 40°C to +85°C, VSS =OV
Limits
VDD=
+5V:!:10%
Parameter
Symbol
PSEN to data in
tRD2
Address setup
beforeWR
tAW
Address setup
before data in
(RD)
tAD1
Address setup
before data in
(PSEN)
tAD2
Address float to
RD, WR
tAFC1
Address float to
PSEN
tAFC2
Min
Max
VDD=
2.5Vto6.0V
Min
175
Max
1300
1850
350
Test
Unit Conditions
ns
(1)
ns
(1)
(1)
(2)
(3)
(4)
(5)
Control output: CL = 80 pF, bus output: CL = 150 pF
CL=20pF
Control output: CL = 80 pF
At execution of MOVD A, Ppinstruction
At execution of MOVO Pp, A; ANlO Pp, A; ORlO Pp, A instructions
AC Timing Test Points (Except RESET, XTAL 1, XTAL2, SS)
(a) Voo= +S,OV±10%
==x:::::=V oo -2
700
(1)
3585
0,8
2750
500
ns
(1)
600
ns
O,7V oo
Test Points
O,18V oo
(1)
-c:::::::X==
O,18V oo
49,OOO492A
125
ns
(1)
Timing Waveforms
175
925
ns
(1)
ALE to control
signal (PSEN)
50
425
ns
(1)
Control signal
tCA1
(RD, WR, PROG)
toALE
35
285
ns
(1)
ALE
Control signal
(PSEN) to ALE
tCA2
280
1285
ns
(1)
PSEN
Port control
setup before
falling edge of
PROG
tcp
85
460
ns
(3)
ns
(3,4)
ns
(3,5)
ns
(3)
tLAFC2
0,8
O,7V oo
===x: ::::::=105
~x==
(b) voo= +2,Sto6,OV
ALE to control
tLAFC1
signal (RD, WR)
Port control hold tpC1
0
Port control hold tpC2
after falling edge
of PROG
135
80
0
200
1135
PROG to time P2 tpR
input mustbe
valid
585
Input data hold
time
tpF
125
Output data
setup time
tDP
350
Output data hold tpD
time
PROG pulse
width
2715
Instruction Fetch (External Program Memory)
Read (External Data Memory)
ALE
ns
(3)
1850
ns
(3)
75
450
ns
(3)
tpp
625
3250
ns
(3)
Port 2 I /0 data
setup time
tpL
135
1135
ns
(3)
Port 2 I / 0 data
hold time
tLP
125
ns
(3)
ALE to port
output
tpv
ns
(3)
TO clock period
tOPRR
ns
(3)
4-276
Voo -2
Test Points
500
AD
tOR
475
250
1600
1000
Bus Floating
NEe
pPD80C40H/50H,pPD50H
Bus Timing Requirements
Timing Waveforms (cont)
Symbol
Write (External Data Memory)
Timing Formula
MiniMax
Unit
(7/30) tCY -170
Min
ns
(1/5) tCy-110
Min
ns
(1/15) tCy-40
Min
ns
(1/2) tCY- 200
Min
ns
(2/5) tCY- 200
Min
ns
(13/30) tCY - 200
Min
ns
(1/15)tCy-40
Min
ns
ALE
tow
two
(1/10)tCy-30
Max
ns
(2/5)tCy-200
Max
ns
(3/10) tCy-200
Max
ns
(2/5)tCy-150
Min
ns
(23/30) tCY - 250
Max
ns
(3/5) tCy-250
Max
ns
(2/15) tCy-55
Min
ns
(1/30)tCy-40
Min
ns
tLAFC1
(1/5) tCy-75
Min
ns
tLAFC2
(1/10) tCy-75
Min
ns
tCA1
(1/15) tCY- 50
Min
ns
tCA2
(4/15) tCY- 50
Min
ns
tcp
(1/10) tCy-40
Min
ns
(4/15) tCY- 200
Min
ns
(17/30) tCy-120
Max
ns
(1/10) tCY
Max
ns
(2/ 5) tCy-150
Min
ns
tpo
(1/10)tCy-50
Min
ns
tpp
(7/10) tCY - 250
Min
ns
(4/15) tCY- 200
Min
ns
(1/30)tCy-40
Min
ns
(3/10) tCy+100
Max
ns
tOPRR
(1/5) tCY
Min
ns
tCY
(11 fXTAL) x 15
tOR
49-000493A
Port 2 Expansion Timing
ALE
Expander
Port
Output
Expander
Port
Input
PROG
I/O Port Timing
2nd Cycle
P24- P27-------------..I,...._____
P1g;rt~l
Port 24-Port 27 Data, Port 10-Port 17 Data
NewPort Data
JAS
49-000494A
4-277
NEe
pPD80C40H/SOH, pPDSOH
Operating Characteristics
IOH vs VOH
IOHVS VOH
-150
-800
-15,...----,------,-----,-----,...----,
TA= 25°C
Voo = 4.5V
TA = 25°C
Voo =4.5V
~
;c
i
l:
~
.=
JP
:z:
- 1 0 1 - - - - - 1 - - - - - - 1 - -....-------1-----+----1
-50
-51-----1------1--"'00.,.---1----'\.-------+----1
JP
:z:
-400
~
-100
~
.=
~
:::I
0
o
1
:;
1
:;
0
o
C>
~
~~o---~---~---~---~~L-~
Output Voltage High VOH1 IV]
Output Voltage High VOH IV]
IOH VS VOO
-200
IOH vs VOO
-20
/
TA=25°C
VOHI =2.4V
~
-150
-15
l:
~
'i
X
-
~
-100
-10
o
1
:;
o
-50
-5
/
/
V
-0.4
TA = 25°C
VOH2 = Voo -0.5 V
~
l:
~
.=
01
X
C -0.2
~
0
!
5
0
2
Supply Voltage Voo IV]
Supply Voltage Voo IV]
IOL vs VOL
IOL vs Voo
TA = 25°C
VOL = 0.45 V
;C
;C
!.
...
!.
...
~
~
!
~
.3
2
c
~
2
§
,;"
,;"
0
:::I
",
:;
0
I
//
~
./
0
0
..
~
~
0
1
0
2
Supply Voltage Voo IV]
4-278
0.5
Output Voltage Low VOL IV]
1.0
NEe
pPD80C40H/50H,pPD50H
Operating Characteristics (cont)
IDD/IDD1 vs f
20
c
TA=25°C
Voo =5.5V
IO~~
!.
--
Q 5
c
'2.
E
...
'""""
o
15.
Co
IOOTyp ...
.-- ----
1---- ---
....
IO~ ... 1--
1- ....
1
.-.-:::: ::::: ~ 1- -
I...
ci!
j.. """
10
0.5 t-
IOO1Typ
~I--
j..i-
0.2~
0.1 L-_ _ _...l-_--l._...l...---l.--L--L..l...-LL_ _ _--l._ _L---....J
0.5
0.1
0.2
0.2
0.1
0.2
0.5
10
____--;;; __
15
Oscillation Frequency I [MHz] [I = 15tCY]
Supply Voltage Voo [V]
Curves below 1 MHz show characteristics for external oscillation.
Curves below 1 MHz show charecterlstlcs for external oscillation
tPC1 Max [80C49H] and tACC Min [82C43] vs VDD
tCY vs VDD
200
.. !
.
250
c
100
U
50
~
>-
..
.
~
J:}
Operation
Secured Area
20
E
i=
10
E
"::t:o
g
"il
0
Co
......
""
Supply Voltage Voo [V]
.
~
i= i= 150
1:
"""~
TA = -40 10 +85°C
200
!- $
Ii
0
0
0
0
t;c
'[
100
~
~CMln
IlPD.80C49H
tPC1 Max
~
IlPD82C43
~ r----....
..........
"S
0
!
i ...c:s
~
TA= 25°C
\
c
i i
Q
~
50
!CI
o
1
"
Supply Voltage Voo [V]
Note: Curves without "operation secured area" show reference data.
4-279
IE
NEe
pPD80C40H/SOH,pPDSOH
Functional Description
Data Memory
The ~PD80C40Hh1P080C50H has the following functional blocks:
The ~P080C40H I ~P080C50H has 256 words x 8 bits of
internal RAM for data memory. Data memory can be externally expanded 256 words maximum when needed.
Instruction Decoder
The instruction decoder stores the operation code of
each instruction and converts it into outputs that control the functions of each blo.ck. These outputs control
the functions executed by the ALU, data source, and
specified registe"rs".
RAM Address Register
The RAM address register specifies the next address to
be accessed in data memory.
'
Program Status Word
Arithmetic Logic Unit (ALU) .
The PSW (figure 1) is an 8-bit status word containing the
information shown in table 1.
The ALU receives 8-bit data from the accumulator or
temporary register and computes an 8-bit result under
control of the instruction decoder.
Figure 1.
7654
The ALU executes the following functions:
•
•
•
•
•
•
•
Add with carry or add without carry
Logical AND, OR, XOR
Increment and decrement
Bit complement
Rotate left and right
Swap nibbles
BCD decimal correction
When a carry resu Its from ALU overflows, the carry bit of
the program word is set.
Accumulator
The accumulator is an 8-bit register that stores ALU input data and arithmetic results. It can also be used for
transferring data between I/O ports and memory.
Temporary Register
The temporary register is an 8-bit register used for the
internal processing necessary with operations such as
multiply or divide. The contents of the temporary register are input to the ALU.
Program Status Word
210
I~I~I~I~I
I
I
I
Stack save possible
CYCarry
AC Auxiliary Carry
FO Flag 0
BS Register Bank Select
1
I~I~I~I
1
I
I
Stack Pointer
49-000483A
Table 1.
Bits 0-2
PSW Bit Functions
Stack pointer bits (SO-S2)
A RESET clears th~ stack pointer to O.
Bit3
Not used (1).
Bit4
Working register bank switch bit (BS)
0= Bank 0
1=Bank 1
Bit5
Flag bit (FO).
User-controlled bit that can be complemented, cleared, or
tested by conditional jump instruction JFO.
Bit6
Auxiliary Carry (AC)
Generated by an auxiliary carry, ADD instruction. Can by used
by decimal adjust instruction DA A.
Bit 7
Carry flag (CY)
Indicates that an accumulator overflow has taken place with
the previously executed instruction.
Program Counter
The program counter is a 12-bit register that addresses
on-chip program memory by specifying the address of
the next instruction to be executed.
Program Memory
The ~PD80C50H contains a mask-programmable ROM
of 4096 x 8 bits. Program memory can be addressed by
a program counter. The ~PD80C40H has no internal
ROM, so it uses external program memory. External program memory is accessed by OBo-OB7, P20-P23, and
PSEN.
4-280
Conditional Branch Logic
The conditional branch logic is used to test processor
conditions. Use a conditional jump instruction to test
the conditions shown in table 2.
NEe
Table 2.
pPD80C40H/50H,pPD50H
Branching Conditions
Test Device
Accumulator
Figure 2.
Timer/Event Counter
Conditional Jump
All a
Not all a
XTAL-c15
Accumulator bit
Carry flag
User flags (Fa, F1)
Timer overflow flag
Test inputs (TO, T1)
a
Interrupt input (INT)
a
Control Logic
The control logic generates or receives the signals that
control various functions including memory reads and
writes, interrupts, software STOP mode, resets, and external memory fetches.
Reset Functions
A reset performs the following functions:
• Clears the program counter and the stack pointer
toO
• Selects register bank and memory bank 0
• Sets the data bus in a high impedance state
(except when EA is high)
• Sets ports 1, 2 in input mode
• Disables interrupts (timer and external)
• Stops the timer
• Clears the timer flag, FO, and F1
• Disables the clock output from TO
• Releases HALT and STOP modes
Timer I Event Counter
The timer/event counter can count external events in order to generate a precise time delay. The counter operation is the same in both modes, the only difference is
the input source.
The counter is an 8-bit binary up counter (figure 2) that
can be reset. It is possible to transfer the contents of the
timer to the accumulator and vice-versa by using the
MOV A, T and MOV T, A instructions, respectively. The
contents of the counter can be independently initialized
by the MOV T, A instruction. Use the STRT T instruction
to use the counter as a timer and the STRT CNT instruction to use the counter as an event counter.
Once the counter starts, it continues counting until the
program executes a STOP TCNT instruction or RESET
becomes active. The counter is incremented up to the
maximum count (FFH) and overflows when the count
goes from FFH to OOH.
Event" Counter. When the T1 pin and counter input are
connected by the execution of a STRT CNT instruction,
the counter starts counting as an event counter. A
change in T1 from high to low causes a count signal
which increments the counter by +1. The maximum
speed of a count increment is one count per 3 machine
cycles. When a 12 MHz crystal is used, the maximum
speed is 1 count per 3.75/As. There is no mimimum
speed. After a count signal the T1 input must be held low
at least 250 ns (at 12 MHz).
Timer. When an internal clock is connected with the
counter input by the execution of the STRT T instruction, the counter starts counting as a timer. When used
as a machine cycle clock, ALE is passed through a prescaler which generates an internal clock that increments the timer every 32 machine cycles. The prescaler
is reset during the execution of a STRT T instruction.
With a 12 MHz crystal, the counter is incremented by +1
at each 25 kHz clock every 40 /As.
You can obtain a delay from 40/As to 10 ms (256 counts)
by presetting the counter and detecting the overflow. To
obtain time, through software control, in excess of
10 ms, count overflows in a separate register. To count in
steps of 40/As or less, an external clock can be supplied
to the T1 input which causes the counter to operate in
the event counter mode. Use the ALE frequency divided
by 3 or more for the external clock. Use a software delay
loop for fine adjustment of an extremely small or large
delay.
Ports 1 and 2 Latch and Buffer
Ports 1 and 2 are 8"bit input/output ports. The data written to the port by an output instruction is latched and
output and the data is maintained unless a new output
instruction is executed. Input data is not latched, so it is
necessary to stabilize input data when reading data by
an input instruction.
Several port-loading options are available. At the time
you order a mask ROM, (JAPD80C50H), you can designate the pullup resistors for port lines P10-P17, P20-P23,
and P24-P27.
4-281
I
:.4
ttiEC
pPD80C40H/50H, pPD50H
Three types of pullup resistors are available:
Type 0
(IOH= -5J.1A: VDD= +5V +10%)
Type 1
Type 2
Nopullup resistor
Only type 0 pullup resistors are available with the
J.lPD80C40H.
Timing Logic
The oscillator generates a clock signal that controls all
system timing operations. Oscillation is generated by
either an external self-oscillating element or external
clock input. The oscillator acts as an internal high-gain
amplifier for serial resonance. To obtain the oscillation
frequency, an external LC network or a crystal or ceramic external resonator may be connected.
As the crystal frequency is lowered, there is an equivalent reduction in series resistance (R). As the
temperature of the crystal is lowered, R is increased.
Due to this relationship, it becomes difficult to stabilize
oscillation where there is low power supply voltage.
When Vee is less than 2.7 V and the oscillator frequency is 3 MHz or less, TA (ambient temperature)
should not be less than -10°C.
Standby Control
The standby control circuitry allows low power consumption operation. The standby function operates in 2
modes: HALT and STOP.
HALT Mode
In HALT mode, the oscillation circuit continues to operate but the internal clock stops. The CPU holds all the
status of the internal circuits just prior to execution of
the HALT instruction. In HALT mode, power consumption is much less than normal.
Setting HALT Mode. HALT mode is set by execution
of the HALT instruction and released by either INT or
RESET. If interrupts are disabled and INT becomes low
at a machine cycle right before the HALT instruction
and remains low during 2 machine cycles, the HALT instruction byte will be fetched. and decoded, but the
HALT mode will not be set. Program operation resumes
from the instruction following the HALT instruction.
If interrupts are enabled under the same conditions as
above, the HALT instruction byte will be fetched and decoded but the HALT mode will not be set and the program will jump to the interrupt start address. After
returning from the interrupt routine, the program will
continue from the instruction following the HALT instruction.
4-282
Releasing HALT Mode. Release HALT mode by activating INT or RESET. When using INT to release HALT
mode, a low level is present at the INT pin and the internal clock is restarted. If interrupts are enabled, the interrupt is executed after the first instruction following the
HALT instruction.
In the interrupt enable state, hold the INT pin low until
the interrupt procedure is started to ensure the interrupt.
When using RESET to release HALT mode, a low level is
present at the RESET pin and the HALT mode is reset
and a normal reset operation is executed. When RESET
goes to a high level, the program starts from address O.
STOP Mode
In STOP mode, the oscillator stops and only the contents of RAM are maintained. Power consumption is
lower than that of the HALT mode. You can set the STOP
mode with hardware, by controlling the RESET and
STOP pins; and by software, by executing the corresponding instruction.
Hardware STOP Mode
In hardware STOP mode, the contents of RAM can be
held at a voltage as low as +2.0 V.
To set hardware STOP mode, set the RESET pin to alow
level to protect the contents of RAM. Set the STOP pin to
a low level to stop operation of the oscillation circuit.
To release hardware STOP mode, apply the normal operating level ( +2.5 V to +6.0 V) to the power supply at the
VDD pin. As figure 3 shows, set the STOP pin to a high
level while holding the RESET pin at a low level. This will
restart the oscillation circuit. When RESET is set high
after oscillation circuit operation is stabilized, the program is started from addressOOOH. Because the STOP
pin controls oscillator operation, be careful to protect
the STOP pin from noise.
When power is turned on, or when STOP mode is
released, the oscillation circuit restarts. Because the
crystal or ceramic resonator utilizes mechanical vibration, a certain time is reqUired for the oscillation to stabilize. The "t" represents the oscillation stabilizing wait
time in the timing waveform.
During this wait time, it is necessary to stop instruction
execution in order to prevent CPU errors, Therefore, "t"
must be longer than the oscillator's stabilizing time.
Oscillation stabilizing time differs somewhat by the
type of oscillator used. With a 6 MHz oscillation frequency, a crystal resonator needs several milliseconds
to stabilize, while a ceramic resonator needs several
hundred microseconds. Figure 4 shows how to easily
NEe
Figure 3.
pPD80C40H/SOH,pPD5QH
Oscillator Stop and Start
A and B on and off, respectively. Then the oscillator restarts, but since SS is still low, program execution remains stopped. With transistor A on, Css charges and
causes SS to go to a high level. Then, program execution restarts. The time it takes for SS to reach the threshold of a logic 1 determines the oscillation stabilizing
wait time.
Oscillation Start
""';~--------~,r
tr
STOP
49-000488A
Figure 4.
Hardware STOP Mode Control Circuit
+ External
- Capacitor
_ - -_ _---4_~
~------Q
STOP
49-000489A
control the hardware STOP mode by externally connecting a capacitor to the RESET pin. This allows control of
the oscillation stabilizing time.
Software STOP Mode
After software STOP mode is released, if interrupts are
disabled as in the HALT mode, program execution is resumed from the instruction following the STOP instruction. If interrupts are enabled, the interrupt procedure is
initiated (address 003H) after the execution of 1 instruction following the STOP instruction. To assure the interrupt, hold INT at a low level until the interrupt procedure
is initiated. Even with short low level timing, the interrupt procedure will be assured if you place a 1-machine
cycle instruction after the STOP instruction. However, it
is recommended that you hold INT low for at least 2 machine cycles.
When using the RESET input, a low level at the RESET
pin resets the software STOP flip-flop. The oscillator
starts and the SS pin goes to a high level as Css is
charged. The program starts from address OOOH when
RESET goes high. Also, since the oscillation stabilizing
wait time is generated when SS is low, the RESET pin
should be held low longer than the SS pin. When the oscillation stabilizing wait time is obtained by the externally connected capacitor, the value of the capacitor
(CRST) connected to the RESET pin (figure 4) should be
set at least 3 times larger than that of capacitor Css
connected to the SS pin. For example, if Css is set to
0.33 J.AF, CRST should be 1J.AF.
In software STOP mode, the oscillation circuits stop,
but the CPU maintains all status of internal circuits and
data existing just before the STOP instruction. Software
STOP mode is the same as when the oscillation circuit
stops in HALT mode.
In software STOP mode, if a capacitor (Css) is connected to the SS pin as shown in figure 5, you can obtain
the oscillation stabilizing wait time when releasing
STOP mode.
Setting Software STOP Mode. To set software STOP
mode, execute the STOP instruction. This sets the internal software STOP mode flip-flop which stops the oscillator and turns transistors A and B off and on,
respectively. Capacitor Css discharges through transistor B causing the SS pin to go low.
Releasing Software STOP Mode. To release software
STOP mode, apply an INT or RESET input.
When using the INT input (figure 6), a low at the INT pin
resets the software STOP flip-flop and turns transistors
4-283
IE
~
NEe
pPD80C40H/50H, pPD50H
Figure 5.
Software STOP Mode Control Circuit
Figure 6.
Software STOP Mode Timing
~~
Software
STOPF/F
RESET
INT
.. ~~----~ ~---+---------
Execution of STOP
Instruction
Oscillation
Stabilizing
Wait Time
49-000491 A
'Execution of Instruction
49-000490A
4-284
Instruction Set
Operation
Description
ADDA, # data
(A) -
Add immediate the specified data to the accumulator. (2)
ADDA, Rr
(A) - (A) + (Rr) for
r = 0-7
ADDA,@Rr
Mnemonic
Hex
Code
Operation Code
D7
D6
Ds
D4
D3
D2
D1
Do
03
0
d7
0
d6
0
d5
0
d4
0
d3
0
d2
1
d1
1
do
Add contents of designated register to the accumulator.(2)
6n(4)
0
1
1
0
1
(A) - (A) + ((Rr)) for
r = 0-1
Add indirect the contents the data memory location to the
accumulator. (2)
6n(4)
0
0
0
0
0
ADDC A, # data
(A) -
Add immediate with carry the specified data to the accumulator. (2)
13
0
d7
0
d6
0
d5
1
d4
0
d3
0
d2
1
d1
ADDC A, Rr
(A) -- (A) + (C) + (Rr)
forr = 0-7
Add with carry the contents of the designated register to the
accumulator.(2)
7n(4)
0
1
1
1
1
ADDCA,@Rr
(A) -- (A) + (C) + ((Rr))
forr = 0-1
Add indirect with carry the contents of data memory location to the
accumulator. (2)
7n(4)
0
0
0
0
ANLA, # data
(A) -
Logical AND specified immediate data with accumulator.
53
0
d7
1
d6
0
d5
1
d4
0
d3
0
d2
1
d1
ANLA, Rr
(A) - (A) AND (Rr) for
r = 0-7
Logical AND contents of designated register with accumulator.
5n(4)
0
1
0
1
1
ANLA, @Rr
(A) - (A) AND ((Rr))
forr = 0-1
Logical AND indirect the contents of data memory with
accumulator.
5n(4)
0
0
0
CPLA
(A) -NOT(A)
Complement the contents of the accumulator.
37
0
0
CLRA
(A)-O
Clear the contents of the accumulator.
27
0
0
Accumulator
(A) + data
(A) + (C) + data
(A) AND data
~
I
(»
c.n
0
~
t)
1
do
1
do
Decimal adjust the contents of the accumulator. (2)
57
0
1
0
1
0
Decrement by 1the accumulator's contents.
07
0
0
0
0
0
1:::
INCA
(A)-(A)+1
Increment by 1the accumulator's contents.
17
0
0
1
0
1
ORLA, # data
(A) -
(A) OR data
Logical OR specified immediate data with accumulator.
43
0
d7
1
d6
0
d5
0
d4
0
d3
0
d2
ORLA, Rr
(A) -
(A) OR (Rr) for r = 0-7 Logical OR contents of designated register with accumulator.
4n(4)
0
1
0
0
1
ORLA, @Rr
(A) - (A) OR ((Rr)) for
r = 0-1
Logical OR indirect the contents of data memory location with
accumulator.
4n(4)
0
1
0
RLA
(AN +1) - (AN)
(Ao) - (A7) for N = 0-6
Rotate accumulator left by 1bit without carry.
E7
RLCA
(AN + 1) - (AN); N = 0-6
(Ao)-(C)
(C)-(A7)
Rotate accumulator left by 1bit through carry.
F7
RRA
(AN) -- (AN + 1); N = 0-6
(A7) -(Ao)
Rotate accumulator right by 1bit without carry.
77
0
0
,.a
0
(A)-(A)-1
0
Bytes
0
0
DECA
DAA
I\,)
0
Cycles
0
CD
1
d1
1
do
0
n
...
0
0
0
:z:
"0
ell
0
..:z:
0
(II
,.a
1:::
0
:z:
~
I
I\J
Instruction Set (cont)
1:::
00
0>
Mnemonic
Operation
Description
Hex
Code
Operation Code
D7
De
Ds
D4
D3
D2
D1
Do
Cycles
Bytes
(AN) - (AN + 1); N = 0-6
(A?)-(C)
(C)-(Ao)
Rotate accumulator right by 1bit through carry.
SWAP A
(A4-A? ) - (Ao-A3)
Swap the 2 4-bit nibbles in the accumulator.
47
0
XRLA. # data
(A) -
Logical XOR specified immediate data with accumulator.
D3
1
d?
XRLA. Rr
(A) - (A) XOR (Rr) for
r = 0-7
Logical XOR contents of designated register with accumulator.
Dn(4)
0
XRLA. @Rr
(A) - (A) XOR ({Rr)) for
r = 0-1
Logical XOR indirect the contents of data memory location with
accumulator.
Dn(4)
0
(Rr) - (Rr) - 1; r = 0-7
If{Rr)'"0;
(PCo-PC?) - addr
Decrement the specified register and test contents.
(PCo-PC?) -: addr if 6b = 1
(PC) - (PC) + 2 if 6b = 0
Jump to specified address if accumulator bit is set.
(peo-pc?) - addr if C = 1
(PC) - (PC) + 2 if C = 0
Jump to specified address if carry flag is set.
(PCo-PC?) - addr if FO = 1
(PC) - (PC) + 2 if FO = 0
Jump to specified address if flag FO is set.
(PCo-PC?) - addr if F1 = 1
(PC) - (PC) + 2 if F1 = 0
Jump to specified address if flag F1 is set.
(A) XOR data
67
0
0
0
J6baddr
JC addr
JFOaddr
JF1 addr
JMP addr
1
d6
:z:
0
0
0
1
0
d5
1
d4
0
d3
0
d2
1
d1
0
0
0
a3
r
a2
r
a1
r
aO
0
a3
0
a2
a1
0
ao
"en
1
do
0
..:z:
1:::
"en"
0
(PCS-PC10) - (addrs-addr10) Direct jump to specified address within the 2K address block.
(PCo-PC?) - (addro-addr?)
(PCl1) -D6F
En
x2(6)
66
76
x4(6)
(PCo-PC?) -
Jump indirect to specified address with address page.
63
JNC addr
(PCo-PC?) - addr if C = 0
(PC) - (PC) + 2 if C = 1
Jump to specified address if carry flag is low.
E6
(PCo-PC?) - addr if I = 0
(PC) - (PC) + 2 if I = 1
Jump to specified address if interrupt is low.
(PCo:"PC?) - addr if TO = 0
(PC) - (PC) + 2 if TO = 1
Jump to specified address if test 0 is low.
(PCo-PC?) - addrifT1 = 0
(PC) - (PC) + 2 ifT1 = 1
Jump to specified address if test 1is low.
(PCo-'PC?) - addr if A '" 0
(PC) - (PC) + 2 if A = 0
Jump to specified address if accumulator is non-zero.
JNTOaddr
JNT1 addr
JNZaddr
({A))
a?
a6
a5
0
a4
b2
a?
b1
a6
bo
a5
a4
a?
a6
a5
~
0
a3
a2
a1
0
ao
1
a?
0
a6
a5
a4
0
a3
1
a2
1
a1
0
ao
0
a?
1
as
a5
a4
0
a3
1
a2
a1
0
ao
a10
a?
ag
a6
as
a5
~
0
a3
a2
0
a1
0
aO
0
1
0
0
a?
a6
a5
0
a4
0
a3
a2
a1
0
ao
a?
0
a6
0
a5
0
a4
0
a3
a2
a1
0
ao
0
a?
0
a6
0
a5
~
0
a3
1
a2
a1
0
ao
0
a?
1
a6
0
a5
0
a4
0
a3
a2
a1
0
ao
a?
0
a6
0
a5
a4
0
a3
a2
a1
0
ao
F6
JMPP@A
JNI addr
..
0
Branch
DJNZ Rr. addr
CD
0
Accumulator (cont)
RRCA
""n
1
86
26
46
96
0
:z:
2
2
2
~
~
Instruction Set (cont)
Mnemonic
Hex
Code
Operation
Description
JTF addr
(PCO-PC7) - addr if TF = 1
(PC) - (PC) + 2 if TF = 0
Jump to specified address if timer flag is set to 1.
16
JTO addr
(PCO-PC7) - addr if TO = 1
(PC) - (PC) + 2 if TO = 0
Jump to specified address if test 0 is a 1.
36
JT1 addr
(PCO-PC7) - addr ifT1 = 1
(PC) - (PC) + 2 ifT1 = 0
Jump to specified address if test 1 is a 1.
56
JZaddr
(PCO-PC7) - addr if A = 0
(PC) - (PC) + 2 if A = 1
Jump to specified address if accumulator is O.
C6
Operation Code
D7
D6
Ds
D4
D3
D2
D1
Do
a7
0
a6
0
a5
a4
0
a3
0
a7
0
a6
a2
a1
ao
a4
0
a3
a5
a7
1
a6
0
a5
a2
a1
ao
a4
0
a3
1
a2
1
a7
1
a6
0
a5
a1
ao
0
a4
0
a3
1
a2
a1
0
ao
0
Branch (cont)
Cycles
Bytes
~
~
Control
EN I
Enable the external interrput input.
05
0
0
0
DIS I
Disable the external interrupt input.
15
0
0
0
ENTO ClK
Enable the clock output pin TO.
75
0
0
0
0
0
0
0
0
SEl MBO
(DBF) -0
Select bank 0 (locations 0-2047) of program memory.
E5
0
0
SEl MB1
(DBF)-1
Select bank 1(locations 2048-4095) of program memory.
F5
1
0
SEl RBO
(BS)-O
Select bank 0 (locations 0-7) of data memory.
C5
SEl RB1
(BS)-1
Select bank 1(locations 24-31) of data memory.
D5
HALT
Initiates halt mode.
01
STOP
Sets CPU to software stop mode.
82
Move immediate the specified data into the accumulator.
23
Move the contents of the designated registers into the
accumulator.
Fn(4)
Move indirect the contents of data memory location into the
accumulator.
Fn(4)
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
d7
0
d6
1
d5
0
d4
0
d3
0
d2
1
1
1
1
1
0
0
1
0
0
0
Data Moves
~
I
I\.)
-
Test
Points
-<
2.0VC
0.8V
83·002896A
4-297
NEe
~PD8041AH,~PD8741A
Timing Waveforms
Read Operation (DBBOUT Register)
Write Operation (DBBtH Register)
(System's
Address Bus)
CSorAo
(System's
Address Bus)
CSorAo
(Read Control)
(Write Control)
Data Bus
Data
Data
e_
(Input) _ _
M_aY;..C_h_an..;9;..e--, ~----"1 ,-_M_ay_C_h_an..;9_
~~~t:~~ ---1----<
,....----~
83-002898A
83-OO2897A
DMA
PORT 2
Expander
Port
SYNC
Output
Expander
Port
Input
~rtCRQ
PROG
ORO
83-002899A
PORT(EA=1)
SYNC
Port t::ontrol
v-;;;-v-;:;:;A...______
~
P10-P17 - ; ; ; ; - - ' \ /
P20- P21 ~
83-002900A
4-298
~
~r
tCRQ
'--83-002901A
t-{EC
~PD8041AH,~PD8741A
Functional Description
Two data bus buffers, an 8-bit status register, the RD and
WR inputs, and expandable I/O lines enhance the
J..IPD8041AH /8741A. These features enable easier
master/slave interface and increased functionality.
Data Bus Buffers
Figure 1 shows how the input and output data bus
buffers enable a smooth data flow to and from the master processors.
Figure 1. Data Bus Buffers
Port 24-Port 27
P24 and P2S can be used as either port lines or buffer
status flag lines. This allows you to make OBF and IBF
status available externally to interrupt the master processor. Upon execution of the EN FLAGS instruction
(F5H), P24 becomes the OBF pin. When a 1 is written to
P24, the OBF pin is enabled and the status of OBF is
output. Ao to P24 disables the OBF pinAND the pin remains low. This pin indicates valid data is available from
the J..IPD8041AH/8741A.
An EN FLAGS instruction execution also enables P2s to
indicate that the J..IPD8041AH/8741A is ready to accept
data. A1 written to P2s enables the IBF pin and the status of IBF is available on P2S. Ao written to P2s disables
the IBF pin. If OBF is not true, the data at the data bus is
invalid.
83.(JQ2902A
Status Register
The 8-bit status register includes four user-definable
bits, ST4-ST7. Use the MOV STS, A instruction (90H) to
define bits ST4-ST7 by moving accumulator bits 4-7 to
bits 4-7 of the status register. Bits STO-ST3 are not
affected.
Figure 2 shows the format of the status register.
P26 and P27 can be used as either port lines or DMA
handshake lines to allow DMA interface. The EN DMA
instruction (E5H) enables P26 and P27 to be used as
DRO (DMA request) and DACK (DMA acknowledge),
respectively.
When a 1 is written to P26, DRO is activated and a DMA
request is issued. The EN DMA instruction deactivates
DRO. You can also deactivate DRO by adding DACK
with RD or WR. Execution of the EN DMA instruction enables P27 (DACK) to function as a chip select input for
the data bus buffer registers during DMA transfers.
Figure 2. Status Register Format
DO
IBF
OBF
RDandWR
The RD and WR inputs are edge-sensitive. Figure 3
shows that status bits IBF, OBF, F1, and FO are affected
on the trailing edge at RD orWR.
Figure 3. RD and WR Inputs
Flags Aflected~
RD,WR
Jl...J
\ ' -_ _ _ _ _
83.(JQ2903A
4-299
IJ
~
I
W
0
0
1::..
Instruction Set
Operation Code
Mnemonic
Operand
Operation
D7
De
D5
D4
Da
D2
D1
Do
ADD
A, # data
(A) -
0
d6
0
0
d5' d4
0
d3
0
d2
1
d1
1
do
ADD
A, Rr
(A) - (A) + (Rr)
r = 0-7
0
d7
0
1
1
1
Cycle.
Iytes
C
Accumulator
(A) + data
0
•
!
AC
FO
Flags
F1 IIF
OIF
514-51 7
"
tJ
.
Q)
0
...
~
:z
w'
0
0
0
0
1
d4
0
d3
0
d2
1
d1
1
1
ADD
A,@Rr
(A) - (A) + ((Rr))
r = 0-1
0
ADDC
A, # data
(A) -
(A) + (C) + data
0
d7
0
d6
ADDC
A, Rr
(A) - (A) + (C) + (Rr)
r = 0-7
0
1
ADDC
A,@Rr
(A) - (A) + (C) + ((Rr))
r = 0-1
0
ANL
A, # data
(A) -
(A) AND data
0
d7
1
d6
0
d5
1
d4
0
d3
ANL
A, Rr
(A) - (A) AND (Rr)
r = 0-7
0
1
0
1
1
ANL
A,@Rr
(A) - (A) AND ((Rr))
r = 0-1
0
CPL
A
(A) -NOT(A)
0
0
1
0
CLR
A
(A)-O
0
0
0
0
DA
A
DEC
A
0
d5
0
•
1
do
•
•
0
0
0
d2
1
d1
0
0
•
1::
"
0
Q)
...~
~
1
do
•
0
(A)-(A)-1
0
0
0
0
1
INC
A
(A)-(A)+1
0
0
0
1
ORL
A, # data
(A) -
(A) OR data
0
d7
1
d6
0
d5
0
d4
0
d3
ORL
A, Rr
(A) -4,-- (A) OR (Rr)
r = 0-7
0
1
0
0
1
ORL
A,@Rr
(A) - (A) OR ((Rr))
r = 0-1
0
0
0
0
RL
A
(AN + 1) - (AN); N = 0-6
(Ao) -(A7)
0
0
0
d2
1
d1
0
0
1
do
~
~
Instruction Set (cont)
Operation Code
Operand
Operation
RLC
A
(AN + 1) - (AN); N = 0-6
(Ao)-(C)
(C)-(A7)
RR
A
(AN) - (AN + 1); N = 0-6
(A7)-(Ao)
0
RRC
A
(AN) - (AN + 1); N = 0-6
(A7)-(C)
(C)-(Ao)
0
Mnemonic
D7
Da
Ds
D4
D3
D2
D1
Do
Cycles
Bytes
C
Accumulator (cont)
SWAP
A
(A4-A7) ++ (Ao-A3)
XRL
A, # data
(A) -
XRL
A, Rr
(A) - (A) XOR (Rr)
r = 0-7
XRL
A,@Rr
(A) - (A) XOR ((Rr))
r = 0-1
(A) XOR data
•
0
AC
FO
Flags
F1 IBF
OBF
ST4-ST7
~~
0
0
0
•
1
0
0
0
1
1
1
0
1
0
0
1
1
d7
d6
d5
d4
d3
d2
d1
do
1
1
0
1
1
0
0
0
0
,.a
'l:
Q)
......
o
J;.
..:z
,.a
'l:
Q)
....
~
~
I
VJ
~
~
~
I
U)
Instruction Set (cont)
Operation Code
N
Mnemonic
Operand
Operation
D7
De
D5
D4
Branch
DJNZ
Rr, addr
(Rr) - (Rr) - 1; r = 0-7
If (Rr) =F 0;
(PCO-PC7) - addr
a7
a6
a5
(PCO-PC7) - addr if Bb = 1
(PC) - (PC) + 2 if Bb = 0
b2
a7
b1
a6
bo
a5
1
JBb
addr
Da
D2
D1
Do
'4
a3
r
a2
r
a1
r
ao
a4
0
a3
0
a2
a1
0
ao
1
a2
0
JC
addr
(PCO-PC7) - addr if C = 1
(PC) - (PC) + 2 if C = 0
a7
as
1
a5
'4
0
a3
JFO
addr
(PCO-PC7) - addr if FO = 1
(PC) - (PC) + 2 if FO = 0
a7
0
a6
1
a5
a4
0
a3
(PCO-PC7) - addr if F1 = 1
(PC) - (PC) + 2 if F1 = 0
0
a7
1
a6
a5
a4
a10
a7
a9
a6
aa
a5
JF1
addr
1
0
a1
ao
a2
a1
0
ao
0
a3
a2
a1
0
ao
0
a4
0
a3
1
a2
0
a1
0
ao
0
1
0
0
0
a3
a2
a1
0
ao
JMP
addr
(PCa-PC10) - (addra-addr10)
(PCO-PC7) - (addro-addr7)
(PC11)-DBF
JMPP
@A
(PCO-PC7) -
JNC
addr
(PCO-PC7) - addr if C = 0
(PC) - (PC) + 2 if C = 1
a7
a6
a5
0
a4
(PCO-PC7) - addr if IBF = 0
(PC) - (PC) + 2 if IBF = 1
1
a7
a6
0
a5
a4
0
a3
1
a2
a1
0
ao
(PCo-PC]) - addr if OBF = 1
(PC) - (PC) + 2 if OBF = 0
1
a7
0
a6
0
a5
0
a4
0
a3
a2
a1
0
ao
(PCO-PC7) - addr if TO = 0
(PC) - (PC) + 2 if TO = 1
0
a7
0
a6
0
a5
'4
0
a3
a2
a1
0
ao
(PCO-PC7) - addr ifT1 = 0
(PC) - (PC) + 2 ifT1 = 1
0
a7
1
a6
0
a5
'4
0
a3
1
a2
1
a1
0
ao
(PCO-PC7) - addr if A = 0
(PC) - (PC) + 2 if A = 1
1
a7
0
a6
0
a5
'4
0
a3
a2
a1
0
ao
(PCO-PC7) - addr if TF = 1
(PC) - (PC) + 2 ifTF = 0
0
a7
0
a6
a5
'4
0
a3
a2
a1
0
ao
(PCO-PC7) - addr ifTO = 1
(PC) - (PC) + 2 if TO = 0
0
a7
0
a6
a5
a4
a3
a2
a1
0
ao
(PCO-PC7) - addr ifT1 = 1
(PC) - (PC) + 2 ifT1 = 0
0
a7
1
a6
0
a5
a4
a3
a2
a1
0
ao
(PCO-:PC7) - addr if A = 0
(PC) - (PC) + 2 if A = 1
1
a7
a6
0
a5
0
a4
0
a3
a2
a1
0
ao
JNIBF
addr
JOBF
JNTO
JNT1
JNZ
JTF
JTO
JT1
JZ
addr
addr
addr
addr
addr
addr
addr
,.a
1:
0
((A))
0
1
1
Cycl••
Iytes
C
AC
FO
Flags
F1 .IF OIF
ST4-ST7
CD
0
......
~
..Z
,.a
1:
2
CD
2
...~
~
2
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operand
Operation
D7
De
Ds
D4
0
D3
D2
D1
Do
Control
EN I
Enable the external
interrupt input
0
0
0
DIS I
Disable the external
interrupt input
0
0
0
SEL RBO
(BS)-O
0
SELRB
(BS)-1
0
EN DMA
Enable DMA handshake
EN FLAGS
Enable interrupt to master
device
0
0
Cycles
Bytes
C
AC
FO
Flags
F1 IBF
OBF
ST4-ST7
~
~
0
0
0
1
0
0
0
0
0
0
d3
Data Moves
MOV
A, # data
(A) -data
= 0-7
= 0-1
MOV
A, Rr
(A) -
(Rr); r
MOV
A,@Rr
(A) -
((Rr)); r
MOV
A, PSW
(A)-(PSW)
MOV
Rr, # data
(Rr) -
data; r
MOV
Rr, A
(Rr) -
(A); r
MOV
@Rr,A
((Rr)) -
MOV
@Rr,#data
((Rr)) -
MOV
PSW, A
(PSW)-(A)
MOVP
A,@A
(PCo-PC?) - (A)
(A)-((PC))
MOVP3
A,@A
(PCo-PC?) - (A)
(PCa-PC1o) - 011
(A)-((PC))
XCH
A, Rr
(A) -
XCH
A,@Rr
(A) -
XCHD
A,@Rr
(Ao-A3) r = 0-1
0
d?
0
d6
1
ds
0
d4
1
1
1
1
= 0-7
= 0-7
(A); r = 0-1
data; r = 0-1
= 0-7
((Rr)); r = 0-1
(Rr); r
((Rr))o-((Rr)}J;
0
0
0
1
d?
0
d6
1
ds
1
d4
1
d3
1
0
1
0
1
0
1
d?
0
d6
1
ds
1
1
0
1
0
1
d1
0
0
r
d2
r
d1
1
do
1
0
1
0
d2
r
do
0
0
0
0
1
d4
0
d3
0
d2
0
d1
r
do
1
1
1
0
1
0
0
0
1:
0
0
0
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
,.
.CD
0
..•Z
,.
1:
D
CD
~
~
I
W
0
w
I!I
•
,J:O..
I
W
~
Instruction Set (cont)
0
.flo.
Operation Code
IInemonlc
Flags
CPlC
Operand
Operation
D7
D8
D5
D4
Da
(C)-NOT(C)
0
1
0
0
1
CPlFO
(FO) -: NOT (FO)
0
0
0
0
CPlF1
(F1) -
0
0
0
NOT (F1)
Dz
D1
Do
0
1
0
1
0
0
0
0
0
ClR F1
(F1)-0
0
0
0
1
0
MOVSTS, A
ST4-ST'l -
cccc
STOP
P10
Pl,
P12
P13
P14
P1s
NC
P16
P17
Ordering Information
P24/0BF
Part Number
Package Type
Max Frequency
of Operation
JlPD80C42C
40-pin plastic DIP
8 MHz
44-pin plastic miniflat
8 MHz
JlPD80C42G-22
49-001145A
4-307
NEe
J.lPD80C42
Pin Identification
Plastic DIP
No.
Plastic Mlnlflat
Symbol
Function
No.
Symbol
Function
TESTO
Test 0 input
18
TESTO
Test 0 input
2,3
XTAL1, XTAL2
Crystal input
19,20
XTAL1, XTAL2
Crystal input
4
RESET
Reset input
22
RESET
Reset input
5
SS
Single-step input
23
SS
Single-step input
6
CS
Chip select input
24
CS
Chip select input
EA
External access input
25
EA
External access input
RO
Read input
26
RO
Read input
9
Ao
Address input
27
Ao
Address input
10
WR
Write input
28
WR
Write input
11
SYNC
Synchronize output
29
SYNC
Synchronize output
12-19
00- 07
Bidirectional port
30-37
00- 07
Bidirectional port
20
Vss
Ground
38
Vss
Ground
21-24
P20-P23
Quasi-bidirectional port 2
39-42
P20-P23
Quasi-bidirectional port 2
35-38
P24/0BF,
P25/IBF,
P26/0RQ,
P27/0ACK
Output buffer full, input buffer full, OMA
request, OMA acknowledge
11,13-15
P24/0BF,
P25/IBF,
Output buffer full, input buffer full, OMA
request, OMA acknowledge
P26/~
P27/0ACK
25
PROG
PROG output strobe
26
STOP
STOP input
43
PROG
PROG output strobe
STOP
STOP input
27-34
P10-P17
Quasi-bidirectional port 1
2-7,9-10
P10-P17
Quasi-bidirectional port 1
39
TEST1
Test 1input
16
TEST1
Test 1input
40
VDD
Positive power supply
17
VDD
Positive power supply
NC
No connection
8,12,21,44
NC
No connection
Pin Functions
SS (Single·Step)
XTAL1, XTAL2 (Crystal)
SS is an input used with SYNC to step the program
through each instruction.
XTAL1 and XTAL2 are the inputs forthe crystal oscillator
for the LC circuit generating internal clock signals. Use
XTAL1 as the external clock input.
TESTO (Test 0)
TESTO is a testable input using conditional jump instructions JTO and J NTO. TESTO also resets the HALT
mode.
TEST1 (Test 1)
TEST1is a testable input using conditional jump instructions JTO and JNTO. TEST1 is also an input to the
event counter.
CS (Chip Select)
CS inputs the chip select signal. An active low enables
the data bus.
EA (External Access)
EA is an input that inhibits internal program memory
fetches. Use EA to check the ROM contents when debugging programs.
WR(Write)
WR is an input used by the master CPU to write data and
commands into the data bus buffer in (DBBIN) register.
RESET (Reset)
RESET inputs a system reset, resets the HALT mode,
and controls the STOP mode.
4-308
RD(Read)
RD is the input used by the master CPU to read data or
NEe
/JPD80C42
status words from the data bus buffer out (DBBOUl) or
status registers.
Ao (Address 0)
Ao is an address input that the master CPU uses to determine the bus operation as follows:
Ao
Cycle
Operation
Read
00- 07 (Port)
DO-D7 is a bidirectional port that transfers data between the data bus buffer (DBBOUT, DBBIN) registers
and the 8-bit master CPU data bus.
P10-P17 (Port 1)
P10-P17 is a quasi-bidirectional, 8-bit port.
Data
Status
o
Write
Data
Command
SYNC (Synchronization)
SYNC is an output that occurs once per instruction cycle. SYNC is used as a strobe for external circuitry or to
synchronize the single-step operation.
PROG (PROG output)
P20-P27 (Port 2)
P20-P27 is a quasi-bidirectional, programmable 8-bit
port. P24-P27 (high-order bits) are alternative pins for
the following interrupt request and DMA handshaking
functions:
P24 = OBF (Output buffer full)
P2s IBF (Input buffer full)
P26 = DRQ (DMA request)
P27 DACK (DMA acknowledge)
=
=
VOO (Power Supply)
When using the I/O expansion port (J,tPD82C43), PROG
outputs a strobe that outputs data/ addresses P20-P23.
Voo is the positive power supply (+2.5 V to +6.0 V)
VSS (Ground)
STOP (Stop)
The STOP input controls the hardware STOP mode.
Vss is the ground potential.
Block Diagram
128x8RAM
OataMemory
~
~
00- 0 7
Reg Bank 1
Stack
96x8
8x8
16x8
8x8
Master
System
Interface
cs
Ao
EA
Control
Logic
SYNC
55
PROG
RESET
I.C.or
Clock
C,,","
Peripheral
Interface
f""
XTAL2
VOO_+2.5V-+6.0V
Power
{
VSS_Ground
49·0011468
NEe
J.(PD80C42
Absolute Maximum Ratings
Extended Voltage Range
TA =:= 25°C
TA= -40°C to +85°C, Voo= +2.5Vto +6.0 V, Vss=OV
Limits
-0.3Vto +7V
Power supply voltage, Voo
Input voltage, VI
- 0.3 V to Voo +0.3V
Parameter
Output voltage, Vo
-0.3 Vto Voo +0.3 V
Input voltage
low
Comment: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits de·
scribed in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
DC Characteristics
Standard Voltage Range.
Input voltage
high
Min
Typ
Test
Conditions
Max
Unit
Input voltage
low
VIL
-0.3
+0.8
V
Input voltage
high
VIH
2.2
Voo
V
Except RESET,
XTAL1, XTAL2
VIH1
Voo-1
Voo
V
RESET, XTAL1,
XTAL2
+0.45
V
10L =2.0 mA
Output voltage
low
VOL
Output voltage
high
VOH
2.4
V
00-07, SYNC,
PROG;
10H= -400 fAA
VOH1
2.4
V
Port 1, port 2;
10H= -50fAA
V
All outputs;
10H= -0.2fAA
Port 1, port 2; VI'"
VIL
SS, RESET;
VI",VIL
VOH2
Input current
Input leakage
current
Output leakage
current
Voo-0.5
IILP
-500
fAA
IILC
-40
fAA
±1
IU1
fAA
EA; VSS",VI"'VOO
ILO
±1
fAA
VSS'" Vo'" Voo
High impedance,
00-07, port
3.0
mA
HALT mode;
tCy=1. 25 fAs
20
fAA
STOP mode (1)
20
mA
tCy=1. 25 fA s
1.5
10
100
VOOOR
+0.6
V
2.5 V'" Voo'"
4.5V
-0.3
+0.8
V
4.5 V'" Voo'"
6.0V
VIH
0. 7V oo
Voo
V
Except RESET,
XTAL1, XTAL2
VIH1
0. 8V oo
VOO
V
RESET, XTAL1,
XTAL2
+0.45
V
10L =1.0 mA
VOL
Output voltage
high
VOH
0. 75V oo
V
00-07, SYNC,
PROG;
10H= -100 fAA
VOH1
0. 7V oo
V
Port1, port 2;
10H= -10fAA
2.0
V
Note: (1) The input voltage pin is VI';; VIL or VI;?; VIH.
Input current
Input leakage
current
Output leakage
current
IILP
-500
fAA
Port 1, port 2; VI'"
VIL
IILC
-40
fAA
SS, RESET; VI'"
VIL
IU1
±1
fAA
TO, T1, STOP, CS,
Ao, RD, WR; VSS'"
VI"'VOO
1L12
±5
fAA
EA; VSS",VI"'VOO
ILO
±1
fAA
VSS'" VO'" Voo
High impedance,
00-07, port
300
600
fAA
HALT mode;
Voo=3V;
tCy=5fAs
2.0
4.0
mA
Voo=6V
tCy=1. 25 fA s
20
fAA
STOP mode (1) ;
Voo=3V
Standby current 1001
1002
Supply current
100
TO, T1, STOP, CS,
Ao, RD, WR; VSS'"
VI"'VOO
±3
1002
Data retention
voltage
fAA
IU2
Standby current 1001
Supply current
-0.3
VIL
Output voltage
low
TA= -40°Cto +85°C, Voo= +5V±10%, Vss=OV
Limits
STOP mode (STOP,
RESET"'0.4 V) or
RESET
(RESET",O.4 V)
Test
Conditions
Unit
Min
- 65°C to + 150°C
Storage temperature, TSTG
Symbol
Typ
Max
-40°C to. +85°C
Operating temperature, TOPT
Parameter
Symbol
Data retention
voltage
VOOOR
2
50
mA
Voo=6V
2.0
5.5
mA
Voo=3V;
tCy=5fAs
16
30
mA
Voo=6V;
tCy=1. 25 fA s
2.0
Note:
(1) The input voltage pin is VI';;VIL OrVI;?;VIH'
V
STOP mode (STOP,
RESET", 0.4 V) or
RESET
(RESET"'0.4 V)
NEe
J.lPD80C42
AC Characteristics
Standard Voltage Range - DBB Read
Extended Voltage Range - DBB Write
TA= -O°Cto +70°C, voo= +5V±10%, vss=ov
TA = - O°C to + 70°C, Voo = +2.5 Vto 6.0 V, Vss = 0 V
Limits
Parameter
Symbol
Min
Typ
Max
~,
AD setup to tAR
RD low
CS, AD hold
from RTI high
tRA
0
200
Unit
Test
Conditions
Min
Typ
Max
Unit
CS, Ao setup to tAW
WRlow
300
ns
ns
CS, ~old
from WR high
tWA
200
ns
WR pulse width tww
data setup to
tow
WR high
2000
ns
1500
ns
Data hold from
WR high
200
ns
RD pulse width
tRR
tAO
150
ns
CL =100 pF
RD low to data
output delay
tRO
140
ns
CL =100 pF
RD high to data
float delay
tOF
85
ns
15
J.l.s
tCY
Symbol
ns
CS, AD to data
output delay
Cycle time
Limits
Parameter
ns
two
Standard Voltage Range - Port 2
1.25
Voo= +5V±10%
Limits
Standard Voltage Range - DBB Write
Parameter
TA= -OOCto +70°C, Voo= +5V±10%, VSS=OV
Port control
setup to PROG
low
Limits
Parameter
Symbol
Min
Typ
Max
Unit
CS, AD setup to tAW
WRlow
ns
CS, ~old
from WR high
ns
tWA
WR pulse width tww
data setup to
tow
WR high
Data hold from
WR high
Test
Conditions
ns
ns
Input data setup tpR
to PROG low
ns
Input data hold tpF
from PROG high
Limits
Min
Typ
Max
Unit
AD setup to tAR
RDlow
300
ns
CS, A..Q..hold
from RD high
tRA
200
ns
RD pulse width
tRR
2000
RD low to data
output delay
tRO
1500
ns
RD high to data
float delay
tOF
400
ns
Cycle time
tCY
15
J.l.s
Typ
Unit
Test
Conditions
ns
CL=80pF
ns
CL=20pF
ns
CL =20 pF
650
ns
CL=80pF
150
ns
CL=20pF
Max
100
80
135
0
top
200
ns
CL =80 pF
Output data hold tpo
from PROG high
60
ns
CL =20 pF
PROG pulse
width
700
ns
Output data
setup to PROG
high
Test
Conditions
Min
Input port
tpC1
control hold from
PROG low
130
TA= -O°Cto +70°C, voo= +2.5Vto +6.0 V, Vss=OV
Symbol
tcp
Output port
tpC2
control hold from
PROG low
Extended Voltage Range - DBB Read
Parameter
Symbol
200
two
~,
Test
Conditions
tpp
ns
CL =100 pF
4-311
E
NEe
",PD80C42
AC Characteristics (cont)
Extended Voltage Range- Port 2
Extended Voltage Range-DMA
voo= +2.5Vto +6.0V
voo= +2.5Vto +6.0V
Limits
Parameter
Port control
setup to PROG
low
Symbol
tcp
Min
Typ
460
Input port
tpC1
control hold from
PROG low
0
Output port
tpC2
control hold from
PROG low
1135
200
Input data setup tpR
to PROG low
Input data hold tpF
from PROG high
Output data
setup to PROG
high
Max
Unit
Test
Conditions
ns
CL =80 pF
ns
CL =20 pF
ns
CL =20 pF
2715
ns
CL =80 pF
500
ns
CL =20 pF
Limits
Typ
Symbol
Min
tACC
200
ns
DACK hold from tCAC
Ri),WR
200
ns
Parameter
Q8CK1etup to
RD, WR
Max
Unit
DACK to data
output delay
tACO
1500
ns
RD, WRto DRQ
clear delay
tCRQ
700
ns
CL =150 pF
Unit
Test
Conditions
Standby Flag Retention Conditions
0
Limits
Parameter
Symbol
Min
Typ
Max
top
1850
ns
CL =80 pF
Preservation of tf
standby flag
voltage fall time
100
/As
Output data hold tpo
from PROG high
450
ns
CL =20 pF
100
/As
PROG pulse
width
3250
ns
Preservation of tr
standby flag
voltage rise time
Standby flag
VSTF
retention voltage
2.0
V
tpp
Test
Conditions
Standard Voltage Range - DMA
Voo= +5V±10%
Input Waveforms for AC Test
Limits
Parameter
~C~etupto
Symbol
Min
Typ
Max
Unit
Test
Conditions
A) Voo= +5.0V±10%
ns
tACC
2.4V~2.2V_
RD, WR
0.45 v
DACK hold from tCAC
Ro, WR
0.8 V
ns
0
DACK to data
output delay
tACO
140
ns
RD, WRto DRQ
clear delay
tCRQ
130
ns
4-312
T,:st _ 2 . 2 V X = =
0.8 V -POints -
B) voo= +2.5 V +6.0 V
0. 8V oo
CL =150 pF
0.45 V
_ _ Test _ _
0. 7V oo
0. 7V oo
0.6 or 0.8 V _ _ Points 0.6 or 0.8 V
49·0011S2A
NEe
J.lPD80C42
Standby Flag Retention Timing
Bus Timing Requirements
Voo
SysGND
49-001151A
Symbol
Timing Formula
MiniMax
Unit
tcp
(1/10) tCy-40
Min
ns
tpC2
(4/15) tCy-200
Min
ns
tpR
(17/30) tCy-120
Max
ns
tpF
(1/10) tCY
Max
ns
top
(2/5)tCy-150
Min
ns
tpo
(1/10) tCy-50
Min
ns
tpp
(7/10) tCy-250
Min
ns
tCY
(11 fXTALl x 15
/-Is
Timing Waveforms
Read Operation (DBBOUT Register)
System Address Bus
CSorAo
1----tRR---+J
Read Control
~J
49-0011536
Write Operation (DBBIN Register)
CSor Ao
=x:_____________ " '-___________
~
system Address Bus
!.-tAW
Write Control
Data Bus Input
Data May Change
Data May Change
49-0011546
NEe
,iPD80C42
Timing Waveforms (cont)
PORT2
SYNC
J r---\\ _ _ _
/
~
Expander Port
Output
P20-P23
Expander Port
Input
P20-P23 Data
PROG
PORT(EA =1)
SYNC
/
_---J
\--------'/
P10-P17 - - - - - - - - , .
Port Data
Port Control
P20-P22-------------J , __________________________J
Port Data
\~-Port Control
49-0011568
DMA
Data Bus
-------t--{I
ORO
49-0011578
ttrEC
J.lPD80C42
Functional Description
Data Bus Buffer In (DBBIN) and Data Bus Buffer
Out (DB BOUT) Registers
As figure 1 shows, the DBBIN and DBBOUT registers
transfer data to and from the master processors by way
of the 8-bit external data bus (Do-D7) and the 8-bit internal data bus.
Figure 1.
You can make STo (OBF) and ST1 (IBF) externally available in order to interrupt the master processor by executing the EN FLAGS instruction. When the EN FLAGS
instruction is executed, P24 becomes the OBF pin. A 1
written to P24 enables OBF and outputs its status. A 0
written to P24 disables OBF by holding it low. Use OBF
to indicate that valid data is available from the output
data bus buffer register.
You can also use the EN FLAGS instruction to use P25
as theN pin. A 1 written to P25 enables TBF to output
the inverse of the IBF status bit. A 0 written to P25 disables IBF by holding it low, making data at the data bus
invalid.
I-lPDBOC42 Data Flow
Input Data
Bus Buffer
(8)
The EN FLAGS instruction is coded as follows:
11110101
OutpulData
Bus Buffer
(8)
49-001147A
Data Bus Buffer (DBB) Status Register
The I-lPD80C42 has an 8-bit status register (STo-ST7)
that contains information about the current status of
the master or slave processor. The MOV STS, A instruction makes status bits ST4-ST7 user-definable by moving accumulator bits 4-1 to bits ST4-ST7 of the status
register (STo-ST3 are not affected). Bits STo-ST3 give
the status of the Output Buffer Full (OBF) and Input
Buffer Full (IBF) bits, and flag bits (FO, F1). Figure 2
shows the status register format.
Figure 2.
ST7
Status Register Format
ST6
ST5
ST4
ST3
ST2
F5H
P26 and P27 are port pins or DMA handshake pins that
allow a DMA interface. Use the EN DMA instruction to
enable P26 and P27 as DRO (DMA Request) and DACK
(DMA Acknowledge), respectively. A 1 written to P26 activates DRO, thus issuing a DMA request. Deactivate
DRO with the EN DMA instruction, DACK ANDed with
RD, or DACK ANDed with WR. When EN DMA is executed, P27 (DACK) functions as a chip select input for
the data bus buffer registers during DMA transfers.
The EN DMA instruction is coded as follows:
1 1 1 0
0
1 0
1
E5H
HALT Mode
The HALT mode allows the I-lPD80C42 to conserve
power during periods of inactivity. In the HALT mode,
the oscillator remains active but the internal system
clock stops. The HALT instruction allows the processor
to enter the HALT mode.
STO
STOP Mode
IBF
OBF
The MOV STS, A instruction is coded as follows:
1 0
0
1 0
0
0
0
90H
Figure 3 shows how STo-ST3 change internally on the
trailing-edge of RD or WR (RD and WR are edgesensitive).
Figure 3.
AD orWR
RD or WR Inputs
The STOP mode disables the oscillator but maintains
the contents of RAM. STOP mode conserves even more
power than HALT mode. Enter STOP mode through software with the STOP instruction or through hardware
with the STOP pin. In hardware STOP mode, the power
supply voltage can drop as low as 2.0 V. In software
STOP mode, it can drop as low as 2.5 V while still maintaining the RAM contents.
Control the STOP mode with hardware, with the RESET
and STOP pins, as follows:
f
~'--~ _ _ _ _ _- - J
Flags Affected
49-00114BA
• Bring RESET low for at least six machine cycles, then
bring STOP low. This assures proper termination of
CPU operations. Figure 4 shows the timing for controlling STOP mode with hardware.
NEe
/JPD80C42
Figure 4.
STOP Mode Control Timing
Oscillator starts operation.
Oscillation stabilizing time
OSC
State count clock
CPU
AORSOOOH
49-0011498
• Release hardware STOP mode by returning Vee to
+5V±10%. After STOP goes high, hold RESET low
long enough to allow the oscillator to stabilize. Figure
5 shows how to control oscillator settling time with
the STOP pin by adding an external capacitor to the
RESET line.
• Release the software STOP modes by applying a low
level to the RESET pin to initiate oscillator operation.
After sufficient oscillator stabilization time has
passed, return RESET to a high level. Program execution will then begin at address O.
Figure 5.
STOP Mode Control Circuit
Voo
4-316
The following table shows the states of the output pins
during both hardware and software STOP mode.
Table 1.
Output Pins During STOP Mode
State
Output Pin
STOPZ Instruction STOPH Instruction Hardware STOP
High level
High level
Do-D7
P10-P17, P20-P27 High-Z
High-Z
High-Z
High-Z
PROG
High level
High .Ievel
High level
SYNC
Low level
Low level
Low level
Instruction Set
Operation Code
Mnemonic
Operation
Description
D7
D6
Ds
D4
D3
D2
D1
Do
ADD A, # data
(A), (C) -- (A) + data
Add immediate the specified data to the accumulator. (2)
0
dl
0
d6
0
d5
0
d4
0
d3
0
d2
1
d1
1
do
ADDA, Rr
(A), (C) r = 0-7
(A) + (Rr)
Add contents of designated register to the accumulator.(2)
0
1
1
0
1
r2
r1
ro
ADDA,@Rr
(A), (C) r = 0-1
(A) + ((Rr))
Add indirect the contents the data memory location to the
accumulator. (2)
0
0
ro
AD DC A, # data
(A), (C) -
(A) + (C) + data
Add immediate with carry the specified data to the accumulator. (2)
0
dl
0
d6
0
d5
1
d4
0
d3
0
d2
1
d1
1
do
ADDC A, Rr
(A), (C) r = 0-7
(A) + (C) + (Rr)
Add with carry the contents of the designated register to the
accumulator.(2)
0
1
1
1
1
r2
r1
rO
ADDCA,@Rr
(A), (C) r = 0-1
(A) + (C) + ((Rr))
Add indirect with carry the contents of data memory location to the
accumulator.(2)
0
0
0
ro
ANLA, # data
(A) -
ANLA, Rr
Accumulator
0
Logical AND specified immediate data with accumulator.
0
dl
1
d6
0
d5
1
d4
0
d3
0
d2
1
d1
1
do
(A) - (A) AND (Rr)
r = 0-7
Logical AND contents of deSignated register with accumulator.
0
1
0
1
1
r2
r1
ro
ANLA, @Rr
(A) - (A) AND ((Rr))
r = 0-1
Logical AND indirect the contents of data memory with accumulator.
0
0
0
ro
CPLA
(A) -
Complement the contents of the accumulator.
0
0
CLRA
(A)-O
Clear the contents of the accumulator.
0
0
Decimal adjust the contents of the accumulator. (2)
0
(A) AND data
NOT (A)
DAA
0
Bytes
~~
0
0
DECA
(A)-(A)-1
Decrement by 1the accumulator's contents.
0
0
INCA
(A)-(A)+1
Increment by 1the accumulator's contents.
0
0
ORLA, # data
(A) -
(A) OR data
Logical OR specified immediate data with accumulator.
0
dl
1
d6
0
d5
0
d4
0
d3
0
d2
1
d1
1
do
ORLA, Rr
(A) -
(A) OR (Rr); r = 0-7
Logical OR contents of designated register with accumulator.
0
0
0
1
r2
r1
ro
ORLA, @Rr
(A) - (A) OR ((Rr))
r = 0-1
Logical OR indirect the contents of data memory location with
accumulator.
0
RLA
(An + 1) - (An),
(Ao) - (Al) n = 0-6
Rotate accumulator left by 1 bit without carry.
RLC A
(An + 1) - (An),
(Ao)-(C)
(C) - (Al) n = 0-6
Rotate accumulator left by 1 bit through carry.
RRA
(An) (Al) -
Rotate accumulator right by 1 bit without carry.
(An + 1),
(AO) n = 0-6
Cycles
0
0
0
0
0
0
ro
,.a
1:
CD
0
0
...
n
N
III
~
I
~
1::
Instruction Set (cont)
Operation Code
:x>
Mnemonic
Operation
Description
D7
D6
Ds
D4
D3
D2
D1
Do
(An) - (An + 1),
(A7)-(C)
(C) - (AO) n = 0-6
Rotate accumulator right by 1 bit through carry.
0
"a
C»
.
0
N
SWAP A
(Ar A4 ) - (A3-AO)
Swap the 2 4-bit nibbles in the accumulator.
XRL A, # data
(A) -
Logical XOR specified immediate data with accumulator.
1
d7
XRLA, Rr
(A) - (A) XOR (Rr)
r = 0-7
Logical XOR contents of designated register with accumulator.
1
XRLA, @Rr
(A) - (A) XOR((Rr))
r = 0-1
Logical XOR indirect the contents of data memory location with
accumulator.
(Rr)-(Rr)-1;
IfRr* 0;
(PCrPCo) - arao
r = 0-7
Decrement the specified register and test contents.
(PCrPCo) - arao if Bb = 1
(PC) - (PC) + 2 if Bb = 0
Jump to specified address if accumulator bit is set.
(PCrPCo) - arao if C = 1
(PC) - (PC) + 2 if C = 0
Jump to specified address if carry flag is set.
(PCrPCo) - arao if FO = 1
(PC) - (PC) + 2 if FO = 0
Jump to specified address if flag FOis set.
(PCrPCo) - arao if F1 = 1
(PC) - (PC) + 2 if F1 = 0
Jump to specified address if flag F1 is set.
(A) XOR data
Bytes
n
Accumulator (cont)
RRCA
CYGles
0
1
d6
0
d5
1
d4
0
d3
0
d2
1
d1
1
do
0
1
1
r2
r1
ro
0
ro
Branch
DJNZ Rr, addr
JBb addr
JC addr
JFO addr
JF1 addr
JMP addr
(PC 10-PC S) -
(arao)
Direct jump to specified address within the 2K address block.
JMPP@A
(PCrPCo) -
JNC addr
(PCrPCo) - arao if C = 0
(PC) - (PC) + 2 if C = 1
Jump to specified address if carry flag is low.
(PCrPCo) - arao if IBF = 0
(PC) - (PC) + 2 if IBF = 1
Jump to specified address if interrupt is low.
JNTO addr
(PCrPCo) - arao if TO = 0
(PC) - (PC) + 2 if TO = 1
Jump to specified address if test 0 is low.
JNT1 addr
(PCrPCo) - arao if T1 = 0
(PC) -(PC) + 2 if T1 = 1
Jump to specified address if test 1 is low.
(PCrPCo) - arao if A * 0
(PC) - (PC) + 2 if A = 0
Jump to specified address if accumulator is non-zero.
JNIBF addr
JNZ addr
((A))
a7
a6
a5
a4
a3
r2
a2
r1
a1
ro
ao
b2
a7
b1
a6
bo
a5
a4
a3
0
a2
a1
ao
a7
a6
a5
a4
a3
a2
a1
0
ao
a7
a6
1
a5
a4
0
a3
a2
1
a1
ao
a2
a1
0
ao
a2
a1
0
ao
a7
a6
a5
a4
0
a3
a10
a7
ag
a6
as
a5
a4
a3
0
a3
a2
a1
0
ao
Jump indirect to specified address with address page.
0
0
a7
a6
a5
0
a4
a7
a6
0
a5
a4
a3
a2
a1
aO
a7
0
a6
a5
a4
0
a3
1
a2
a1
ao
a6
0
a5
0
a4
0
a3
1
a2
1
a1
0
ao
a6
0
a5
a1
0
ao
0
a7
a7
a4
a3
a2
.~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operation
Description
D7
D6
Ds
D4
D3
D2
D1
Do
a7
a6
a5
0
a4
a3
a2
a1
ao
a7
a6
a5
a4
a3
a2
a1
0
ao
0
a7
a6
a5
a4
a3
a2
a1
ao
a7
a6
0
a5
a4
a3
a2
a1
ao
a7
a6
a5
a4
a3
a2
a1
aO
Branch (cont)
JOBF addr
(PCrPCo) + - arao if OBF = 1 Jump to specified address if output is low.
(PC) + - (PC) + 2 if OBF = 0
(PCrPCo) + - arao if TF = 1
then reset TF
(PC) + - (PC) + 2 if TF = 0
Jump to specified address if timer flag is set to 1.
JTO addr
(PCrPCo) + - arao if TO = 1
(PC) + - (PC) + 2 if TO = 0
Jump to specified address if test 0 is a 1.
JT1 addr
(PCrPCo) + - arao if T1 = 1
(PC) + - (PC) + 2 ifT1 = 0
Jump to specified address if test 1 is a 1.
JZ addr
(PCrPCo) + - arao if A = 0
(PC) - (PC) + 2 if A = 1
Jump to specified address if accumulator is O.
JTF addr
Cycles
Bytes
~
~
Control
EN I
Enable the interrupt.
DIS I
Disable the external interrupt input.
1
EN DMA
Enables DMA handshake lines.
0
EN Flags
Enables master interrupts.
SEL RBO
(BS)-O
Select bank 0 (locations 0-7) of data memory.
SEL RB1
(BS)-1
Select bank 1 (locations 24-31) of data memory.
0
0
1
1
0
0
0
0
HALT
Initiates halt mode.
STOPZ
Sets CPU to software stop mode. (Port output high impedance)
0
0
STOP H
Sets CPU to software stop mode. (Port output high level)
0
0
0
Data Moves
MOV A, # data
.j::Io.
~
co
(A) -data
Move immediate the specified data into the accumulator.
= 0-7
= 0-1
MOV A, Rr
(A) -
(Rr); r
MOVA,@Rr
(A) -
((Rr)); r
(PSW)
MOVA, PSW
(A) -
MOV Rr, # data
(Rr) -
data;r
MOV Rr, A
(Rr) -
(A); r "" 0-7
MOV@Rr,A
((Rr)) -
(A); r
MOV @ Rr, # data
((Rr)) -
data; r
MOV PSW, A
(PSW)-(A)
Move the contents of the deSignated registers into the accumulator.
0
0
d7
d6
1
d5
0
d4
0
d3
0
d2
1
d1
1
do
1
1
1
1
1
r2
r1
ro
0
ro
Move indirect the contents of data memory location into the
accumulator.
Move contents of the program status word into the accumulator.
= 0-7
= 0-1
= 0-1
Move immediate the specified data into the deSignated register.
0
1
d7
Move accumulator contents into the designated register.
0
d6
1
d5
0
Move indirect accumulator contents into data memory location.
1
d3
r2
d2
r1
d1
ro
dO
0
1
r2
r1
rO
0
0
0
rO
1
d4
0
d3
0
d2
0
d1
ro
do
n
1
0
1
1
1
N
0
Move immediate the specified data into data memory.
1
d7
d6
1
d5
Move contents of accumulator into the program status word.
1
1
0
~
1
d4
0
,.a
1::
CD
0
~
~
I
U)
Operation Code
Mnemonic
Description
Operation
D7
D6
D5
D4
D3
D2
D1
Do
Move data in the current page into the accumulator.
0
0
0
Move program data in page 3 into the accumulator.
0
0
0
MOVPA,@A
A-
MOVP3A, @A
(A)-((011,A))
XCH A, Rr
(A)"""'--' (Rr); r
Exchange the accumulator and designated register's contents.
0
0
0
XCH A, @Rr
(A)"""'--' ((Rr)); r = 0-1
Exchange indirect contents of accumulator and location in data
memory.
0
0
0
XCHDA, @Rr
(A3-AO)"""'--' ((Rr}J-(Rr)o);
r = 0-1
Exchange indirect 4-bit contents of accumulator and data memory.
0
0
CPLC
(C) -
Complement contents of carry bit.
CPL FO
(FO) -
NOT (FO)
Complement contents of flag FO.
0
CPL F1
(F1) -- NOT (F1)
Complement contents of flag F1.
0
CLRC
(C)-O
Clear contents of carry bit to O.
0
CLR FO
(FO)--O
Clear contents of flag 0 to O.
0
CLR F1
(F1)--0
Clear contents of flag 1to O.
0
ANL Pp,
# data
(Pp) -- (Pp) AND data
p = 1-2
Logical AND immediate specified data with designated
port (1 or 2).
1
d7
0
d6
0
d5
1
d4
1
d3
0
d2
P1
d1
PO
do
ANLD Pp, A
(Pp) - (Pp) AND (ATAO);
p = 4-7
Logical AND contents of accumulator with designated port (4-7).
1
0
0
1
1
1
P1
Po
IN A, DBB
(A) -- (DBBIN); IBF -- 0
0
0
0
0
0
IN A, Pp
(A) -- (Pp); p = 1-2
Input data from designated port (1-2) into accumulator.
0
MOVDA, Pp
(A3-AO) -+'- (Pp);
(ArA4) - 0 P = 4-7
Move contents of designated port (4-7) into accumulator.
0
= 0-7
r2
0
Cycles
Bytes
CD
0
...n
Data Moves (cont)
((PC10-PCS), (A))
,.a
1::
Instruction Set (cont)
I\)
e
N
r1
rO
0
ro
0
ro
Flags
NOT (C)
0
0
0
0
0
0
0
0
0
Input I Output
0
0
0
0
0
0
MOVD Pp, A
(Pp) -- (ATAO); P = 4-7
Move contents of accumulator to designated port (4-7).
0
MOV STS, A
(STrST 4) -- (ArA4)
Move contents of accumulator to designated port (4-7).
0
0
0
0
0
P1
P2
P1
Po
P1
Po
0
0
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operation
Description
ORLD Pp, A
(Pp) - (Pp) OR (ATAO):
P = 4-7
Logical OR contents of accumulator with designated port (4-7).
ORL Pp,
(Pp) - (Pp) OR data
p = 1-2
Logical OR immediate specified data with designated port (1-2).
# data
OUT DBB, A
(DBBOUT) -
OUTL Pp, A
(Pp) -
D6
D5
D4
0
0
0
1
d7
0
d6
0
ds
0
d4
1
d3
0
0
0
0
0
D7
D3
D1
Do
P1
Po
0
d2
P1
d1
Po
do
0
1
0
0
P1
Po
D2
Input! Output (cont)
(A), OBF -1
(A); P = 1-2
Output contents of accumulator to designated port (1-2).
0
Cycles
Bytes
~
~
Registers
= a-7
= 0-7
a
DEC Rr
(Rr) -- (Rr) - 1; r
INC Rr
(Rr) -
INC@Rr
((Rr))-((Rr)) +1;
r = 0-1
Increment indirect by 1the contents of data memory location.
((SP)) - (PC), (PSWrPSW4)
(SP) - (SP) + 1
(PC10-PCO) -- a10-aO
Call designated subroutine.
RET
(SP) (PC) -
Return from subroutine without restoring program status word.
RETR
(SP) - (SP) - 1
(PC) - ((SP))
(PSWrPSW4) -- ((SP))
(Rr) + 1; r
Decrement by 1 contents of designated register.
0
Increment by 1contents of designated register.
r2
r1
ro
1
r2
r1
ro
a
a
a
0
a
a1Q
a7
ag
a6
as
as
a4
a3
a2
a
a
a
a
ro
Subroutine
CALLaddr
(SP) - 1
((SP))
a
Return from subroutine restoring program status word.
a
a1
aO
a
Timer I Counter
EN TCNTI
Enable internal interrupt flag for timer / counter output.
a
0
0
a
DIS TCNTI
Disable internal interrupt flag for timer / counter output.
a
a
1
0
1
Move contents of timer / counter into accumulator.
a
a
0
a
0
MOVA, T
(A)-(T)
MOVT, A
(T)-(A)
Move contents of accumulator into timer I counter.
a
0
STOP TCNT
Stop count for event counter.
a
a
STRTCNT
Start count for event counter.
a
0
0
STRTT
Start count for timer.
0
a
a
No operation performed.
a
a
a
1::
Miscellaneous
NOP
a
a
0
a
a
"a
CD
.
0
n
~
I
(,.)
N
~
I!!I
t¥EC
J..lPD80C42
Symbol Definitions
Symbol
Description
A
Accumulator
AC
addr
Symbol
Description
SP
Stack pointer
Auxiliary carry flag
T
Timer
Program memory address
TF
Timer flag
Accumulator bit (b = 0-7)
TO, T1
TESTO, TEST1 pin
C
Carry flag
#
Immediate data
CNT
Counter
@
Indirect address
data
8-bit data
(x)
Contents of register X
DBB
Data bus buffer
FO, F1
((x))
Flags 0, 1(C /0 flag)
Contents of memory addressed by X
Transfer direction, result
Interrupt
AND
Logical product (logical AND)
IBF
Input buffer full flag
OR
Logical sum (logical OR)
OBF
Output buffer full flag
XOR
Exclusive OR
PC
Program counter
Pp
Port (p=1-20r4-7)
PSW
Program status word
Rr
Complement
Register (r=0-1 or r=O-7)
Operating Characteristics
VOH1 vsI OH
-150 .--------,-------,--------,,--------,--------,
VOHVS IOH
-800r---~~~----~--~r-~------~-------'
l
:I:
9
-100
~------~------I--.....----I----------1I__----__t
~
<3
.::
.2'
J:
1
-50~------1__------1__~~--1__~--~~----__t
'S
o
O~----~~----~------~------~--~--~
o
Output High Voltage VOH (V)
4-322
0~----~------~----~------~-3--~1
o
Output High Voltage VOHl (V)
NEe
JlPD80C42
Operating Characteristics (cont)
IOH vs VOO (VOH1 = 2.4 V)
-100
/
/
~
J:
::I
~
-50
0
o
J:
9
8~
-0.2 I-----+-----I---::;~~-+------l
.c
.2'
J:
::I
Co
'S
o
OL-________
_ _ _ _ _ _L __ _ _ _ _ _
Supply Voltage Voo (V)
IOL vs VOO (VOL = 0.45 V)
IOL vsVoo{Voo=4.5V)
e-
I]
e-
§.
§.
...J
9
u
...J
9
C
§
2
2
U
~
i
.9
!
......................
!
0
0
0
1
2
0.5
0
IOO/lOD1 vs f{VOO = 5.5 V)
20
--
IOO/IOD1 vs f{VOO = 3 V)
10
1-1--1-
H1-
10
§.
---
5
E
"0
E
f==Voo
VOOJ5.5V
L----F-r
~
.1
I
~
~
f
I--~ I-~
1
10D1Typ.
i..----
I
E
,I
100 Max. _
.----r
§.
5
I
.1
3V
e-
100TY~
~
~
1001 Max.
1----+--.---
~
Jl
10
1
Oscillation Frequency, f (MHz)
(f=1S/tCY)
-
u 0.5
I--
0.2
0.5
1.0
Output Low Voltage VOL (V)
Supply Voltage Voo (V)
e-
I
2
2
Supply Voltage Voo (V)
I
________
~
~
U
l
~
9
/
V
~
-150
J:
.--------..,---------r-------r--------,
_
e-
.ilo
IOH vs VOO (VOH2 = VOO - 0.5 V)
-0.4
L
-200
15
0.1
0.5
r---
1001 Max •
..i.--10D1Typ.
I
I
Oscillation Frequency, f (MHz)
(f=1S/tCY)
4-323
NEe
J.lPD80C42
Operating Characteristics (cont)
tpCI Max {j.IPD80C42)1
tACC Min (,lPD82C42) vs Voo
tCyvsVOO
2~r-------~---------r--------.---------'
20
Operating Range
200
10
~
~
100 I - - - - - - t - - - - - + - - - - - - "......=--+---=__o----I
"",
~~------~--------~--------~------~
2
1
2
Supply Voltage, Voo (V)
4-324
t--~T--+------+-----I------I
Supply Voltage
Voo (V)
NEe
NEe Electronics Inc.
pPD8748H
HIGH-SPEED, a-BIT, SINGLE-CHIP
NMOS MICROCOMPUTER
WITH UV EPROM
Description
Pin Configuration
The J..tPD8748H is one of the J..tPD8048 family of singlechip 8-bit microcomputers. It is a high-speed NMOS
processor that functions efficiently in control and
arithmetic applications. The flexible instruction set
allows you to directly set and reset individual data bits
within the accumulator and the I/O ports. The variety of
branch and table look-up instructions simplifies the
implementation of standard logic functions.
TO
XTAL2
o
o
o
o
o
o
o
o
o
o
o
o
o
o
Low programming voltage
Fully compatible with 8048/8748/8035
NMOS silicon gate technology
Single +5V supply
2.5J..ts cycle time
96 instructions; 70% single byte
Internal timer/event counter
64 x 8 byte RAM data memory
Single interrupt level
271/0 lines
Internal clock generator
8-level stack
Compatible with 8080A/8085A peripherals
Available in one-time-programmable plastic
package
Ordering Information
Part
Number
Package Type
pPD8748HC
40-Pin plastic DIP
11 MHz
pPD8748HD
40-Pin cerdip with quartz window
11 MHz
P2s
EA
P17
Ro
P1s
PSEN
P1s
ALE
P13
DBo
P12
DB1
P11
DB2
P10
DB3
VDO
DB4
PROG'
DBs
P2a
DBs
P22
DB7
Vss -,.;;.~_ _.....,49·000468A
Pin Identification
No.
Symbol
Function
1,39
TO, T1
Testable inputs 0 and 1
2,3
XTAL1, XTAL2
Crystal inputs
4
RESET
System reset input
5
SS
Single step input
7
8
INT
Interrupt input
EA
External access input
RD
Read strobe output
PSEN
Program store enable
output
10
WR
Write strobe output
11
ALE
Address latch enable
output
12-19
Do-D7
8-bit bidirectional port
Vss
Ground
P20-P27
8-bit quasi bidirectional
port 2
25
PROG
Program pulse input
26
Voo
Programming power
supply
P10-P17
8-bit quasibidirectional
port 1
Vee
Primary power supply
20
21-24, 35-38
27-34
Max Freq.
of Operation
P2s
55
WR
The J..tPD8748H functions as a stand-alone microcomputer. You can expand its functions with standard
8080A/8085A peripherals and memories. It contains
1024 x 8 bits of ROM program memory, 64 x 8 bits of
RAM data memory, 27 I/O lines, an 8-bit internal
timer/event counter, oscillator, and clock circuitry.
Features
P27
RESET
P24
The instruction set is made up of one- and two-byte
instructions. Over 70% are single-byte instructions that
require only one or two cycles. Over 50% require a
single cycle.
The J..tPD8748H differs from the J..tPD8048 in that it has 1K
of on-board EPROM. This is useful in preproduction or
prototype applications where the software is not
complete or in system designs in quantities that do not
require a mask ROM. See the J..tPD8048H/8035HL data
sheet for more information.
Vcc(+S)
XTAL1
40
4-325
NEe
JlPD8748H
Pin Functions
WR
TO, T1
Acitve low write strobe output. WR pulses low when the
processor performs a bus write. WR also functions as a
write strobe for external data memory.
(Testable inputs 0 and 1)
TO uses the conditional transfer ·functionsJTO and
JNTO; T1 uses JT1 and JNTt The ENTO CLK instruction
allows TO to use the internal state clock (CLK). Use the
STRT CNT instruction to use T1 as the timer/counter.
During programming, you can use TO as a testable flag.
XTAL1, XTAL2
(Crystal inputs)
XTAL1 and XTAL2 are two sides of the crystal input for
an external oscillator or frequency (non-TTL compatible
VIH)·
RESET
(Reset)
Active low input for processor initialization. RESET is
also used for PROM programming verification and
power down (non-TTL compatible VIH).
SS
(Single step)
Active low single step input. SS and ALE allow the
processor to single step through each instruction in
program memory.
INT
(Interrupt)
Active low interrupt input. INT starts an interrupt if an
enable interrupt instruction has been executed. RESET
disables the interrupt. You can test INT with a
conditional jump instruction.
EA
(External access)
A logic 1 at the EA input tells the processor to perform
all program memory fetches from external memory.
RO
(Read strobe)
Active low read strobe output. RO pulses low when the
processor performs a bus read. RO also enables data
onto the processor bus from a peripheral device and
functions as a read strobe for external data memory.
PSEN
(Program store enable)
Active low program store enable output. PSEN
becomes active only during external memory fetches.
(Write strobe)
ALE
(Address latch enable)
Once each cycle, the falling edge of ALE latches the
address for external memory or peripherals. You can
also use ALE as a clock output.
00-07
(a-bit bidirectional bus)
The RO and WR strobes allow you to perform
synchronous reads and writes on this port. The
contents of 00-07 can be latched in static mode. During
an external memory fetch, 00-07 holds the LSBs of the
program counter. PSEN controls the incoming
addressed instruction. 00-07 also holds address and
data information for external RAM data store
instruction (controlled by ALE, RO, and WR).
Vss
(Ground)
Ground.
P20-P27
(Port 2)
Port 2 is one of two 8-bit quasibidirectional ports.
P20-P23 hold the four MSBs of the program counter for
external data memory fetches; P24-P27 hold data.
P20-P23 are also used as a 4-bit I/O bus for the /APD8243
I/O expander.
PROG
(Program pulse)
Apply a + 18 V pulse to the PROG input to program the
/AP08748H. You can also use PROG as an output strobe
for the /AP08243.
Voo
(Programming power supply)
VDD must be +21 V to program the /AP08748H or +5 V
for the ROM and PROM versions for normal operation.
P10-P17
(Port 1)
Port 1 is one of two 8-bit quasibidirectional ports used
for external data memory fetches.
Vee
(Power supply)
Vee must be +5 V to program and operate the
/APD8748H.
4-326
NEe
JAPD8748H
Block Diagram
Power Supply
I
I
t
!
V DD
Program
Supply
I
t
Vee
Vss
+5V
Ground
(Low Power
Standby)
Resident Program Memory
ROM EPROM
1024x8
Register 2
Register 3
Register 4
RegisterS
Register 6
Register 7
8-Level Stack
(variable word length)
IJ
Optional Second
Register Bank
Data Store
Resident Data Memory RAM
(64x8)
PROM/Expander
Strobe
49-()()()469B
Absolute Maximum Ratings
DC Characteristics
TA=25°C
TA=OOCto +70°C, VCC=VDD= +5V±10%, VSS=OV
Limits
Operating temperature, Top
Parameter
Storage temperature, TST
Output voltage, Vo
-0.5Vto +7.0V
-0.5Vto +7.0V
Input voltage, VI
Power supply voltages, Vee,
voo
-0.5Vto +7.0V
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the limits
described in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
Symbol
Min
Typ
Max
Unit
Test
Conditions
Input low voltage VIL
(except XTAL1,
XTAL2, RESET)
-0.5
0.8
V
Inputlow voltage VIL1
(XTAL1, XTAL2,
RESET)
-0.5
0.6
V
Input high voltage VIH
(except XTAL1,
XTAL2, RESET)
2.0
Vee
V
Input high voltage VIH1
(XTAL1, XTAL2,
RESET)
3.8
Vee
V
VOL
0.45
V
IOL =2.0mA
Output low
VOL1
voltage (RD, WR,
PSEN, ALE)
0.45
V
IOL =1.8mA
Output low
voltage (Bus)
4-327
NEe
J.lPD8748H
DC Characteristics (cont)
AC Characteristics
TA=OOCto +70 0 C, vec=voo= +5V±10%, vss=ov
TA=OOCto +70°C, vce=Voo=+5V±10%, vss=ov
Umlts
Parameter
Symbol
Typ
Test
Conditions
Limits
Parameter
Symbol
Unit
Test
Conditions
150
ns
(1,3)
70
ns
(1,3)
Min
Max
Unit
VOl2
0.45
V
10l =1.0mA
Read, Write, and Instruction FetchExternal Data and Program Memory
Output low
VOL3
voltage (all other
outputs)
0.45
V
10L =1.6 mA
ALE pulse width
tll
Address setup
before ALE
tAL
Output low
voltage (PROG)
Output high
voltage (Bus)
Min
l'yp
Max
2.4
V
10H= -400/AA
Address hold
after ALE
tLA
50
ns
(1,3)
Output hl9!! _
VOHl
voltage (RD, WR,
PSEN, ALE)
2.4
V
10H= -100MA
Control pulse
width (RD, WR)
tCC1
480
ns
(1,3)
Output high
VOH2
voltage (all other
outputs)
2.4
V
10H= -40MA
Control pulse
width (PSEN)
tCC2
350
ns
(1,3)
Data setup before tow
WR
390
ns
(1,3)
Data hold after
WR
two
40
ns
(1,2,3)
Cycle time
tCY
1.36
15.0
lAS
Data hold after
RD, PSEN
tOR
0
110
ns
VOH
Input leakage
III
current (T1, INT)
±10
Input leakage
ILil
current (P10-P17,
P20-P27, EA, 88)
-500
Output leakage
IlO
current (Bus, TO,
high impedance)
±10
Supply current
(VOO)
100
Total supply
current
100+
ICC
MA Vss~ VI ~ VCC
MA Vss+ 0.45 V
~VI~VCC
MA Vss+ 0.45 V
~VI~VCC
mA
85
110
mA
Programming DC Characteristics
TA = 25°C ±5°C, Vee = +5 V ±5%, Voo = +21 V ±O.5 V
Limits
Te.t
Conditions
(1,3)
RD to data in
tROl
330
ns
(1,3)
PSEN to data in
tR02
190
ns
(1,3)
Address setup
beforeWR
tAW
ns
(1,3)
Address setup
before data in
(RD)
tAOl
730
ns
(1,3)
Address setup
before data in
(PSEN)
tA02
460
ns
(1,3)
300
Max
Unit
140
ns
(1,3)
21.5
V
Address float to
RD, WR
tAFCl
20.5
10
ns
(1,3)
4.75
5.25
V
Address float to
PSEN
tAFC2
VOOl
200
ns
(1,3)
VPH
17.5
18.5
V
ALE to RD, WR
delay time
tLAFCl
PROG voltage
high level
60
ns
(1,3)
VPl
4.0
VCC
V
ALE to PSEN
delay time
tLAFC2
PROG voltage
low level
ns
(1,3)
VEAH
17.5
18.5
V
RD, WR, PROG to tCAl
ALE delay time
50
EA program/
verify voltage
high level
PSEN to ALE
delay time
320
ns
(1,3)
Parameter
Symbol
Min
VOO voltage
high level
VOOH
VOO voltage
low level
l'yp
VOO high voltage 100
supply current
20.0
mA
PROG high
voltage supply
current
IpROG
1.0
mA
EA high voltage
supply current
lEA
1.0
mA
4-328
tCA2
Note:
(1) Control Output: CL = 80 pF, Bus Output: CL = 150 pF
(2) Bus high impedance, load = 20 pF
(3) Clock oscillation frequency, fosc = 11 MHz
NEe
""PD8748H
AC Characteristics {cont}
Programming AC Characteristics {cont}
TA=OOCto +70°C,Vcc=Voo= +5V±10%,Vss=OV
TA = 25°C ± 5°, Voo = +21 V ± 0.5 V
Parameter
Symbol
Min
Limits
Typ
Max
Unit
Test
Conditions
Port 2 Timing
Limits
Parameter
Symbol
Min
Typ
Max
Unit
Port control setup tcp
before PROG
100
ns
(1,3)
TESTO to data
output delay(1)
tDO
160
ns
RESET pulse
width to latch
address
4tCY
tpc
(1,3)
tww
Port control hold
after PROG
Input data setup
before PROG
tpR
650
ns
(1,3)
VDD and PROG
tr,tf
rise and fall times
0.5
100
/is
Input data hold
after PROG
tpF
140
ns
(1,3)
CPU cycle time
tCY
4.0
15
/is
tRE
4tCY
4tCY
Output data setup tDP
before PROG
400
ns
(1,3)
RESET setup
before EA t
Output data hold
after PROG
tpD
90
ns
(1,3)
Note:
(1) If TESTO is high, too is triggered by RESETt.
PROG pulse width tpp
700
ns
(1,3)
Port 2 I 1 0 data tpL
setup before ALE
160
ns
(1,3)
Port 2 I 1 0 data
setup after ALE
15
tLP
510
ALE to port output tpv
time
TO output cycle
time
tOPRR
270
ns
(1,3)
ns
(1,3)
ns
(1,3)
Note:
(1) Control output: CL = 80 pF, bus output: CL = 150 pF
(2) Bus high impedance, load = 20 pF
(3) Clock oscillation frequency, fosc = 11 MHz
Programming AC Characteristics
TA = 25°C
± 5°, Voo = +21 V ± 0.5 V
Limits
Parameter
Address setup
before RESETt
Symbol
tAW
Min
Typ
Max
Unit
4tCY
Test
Conditions
Test
Conditions
4.0 /is 1 3.7 MHz
Bus Timing Requirements
Unit
Symbol
Timing Formula
MinIMax
tLL
(7/30) tCY -170
Min
ns
tAL
(2115) tCy-110
Min
ns
tLA
(1/15) tCy-40
Min
ns
tCC1
(1/2) tCY- 200
Min
ns
tCC2
(2/5) tCY- 200
Min
ns
tDW
(13/30) tCY - 200
Min
ns
tWD
(1/15) tCY- 50
Min
ns
tDR
(1/10)tCy-30
Max
ns
tRD1
(11113) tCy-170
Max
ns
tRD2
(4/15)tCy-170
Max
ns
tAW
(1/3)tCy-150
Min
ns
tAD1
(7/10) tCY- 220
Max
ns
tAD2
(1/2)tCy-220
Max
ns
tAFC1
(2115) tCy-40
Min
ns
tAFC2
(1/30) tCy-40
Min
ns
tLAFC1
(1/5)tCy-75
Min
ns
tLAFC2
(1/10)tCy-75
Min
ns
Address hold
after RESETt
tWA
Data Input setup
before PROG-I-
tDW
4tCY
tCA1
(1/15)tCy-40
Min
ns
tCA2
(4/15) tCY- 40
Min
ns
Data input hold
after PROG-I-
tWD
4tCY
tcp
(2115) tCy-BO
Min
ns
tpc
(4/15) tCY- 200
Min
ns
tpR
(17/30) tCY -120
Max
ns
tpF
(1/10) tCY
Max
ns
tDP
(2/5) tCy-150
Min
ns
tpD
(1/10)tCy-50
Min
ns
tpp
(7/10) tCY- 250
Min
ns
tpL
(4/ 15)tCY- 200
Min
ns
tLP
(11 30)tCY- 30
Min
ns
tpv
(3/10) tCy+100
Max
ns
tOPRR
(1/5)tCY
Min
tCY
(11 fosc) x 15
RESET hold after tpH
verify
4tCY
4tCY
VDD setup before tVDDW
PROGt
1.0
VDD hold after
PROG')'
1.0
tVDDH
PROG pulse width tpw
TESTO setup
before program
mode
tTW
TESTO hold after tWT
program mode
50
4tCY
4tCY
60
ms
ms
ms
ns
/is
4-'329
Il
NEe
J.lPD8748H
Timing Waveforms
Read (External Data Memory)
Instruction Fetch (External Program Memory)
49-000470A
Write (External Data Memory)
AC Test I/O Waveform
£. 2.0
2_0 ~
2.4V
0.45V
----"")(>
0.8
Test Points
i'
:::::::::x---'\ 0.8
49-000473A
49-000472A
Port 11Port 2
2nd Cycle
1st Cycle
ALE
PSEN
P2Q-P23
Output
P24-P27
P1O-P17
Output
Port ,2 Data (0-3)
Port 2 (4-7), Port 0 (0-7) Data
Expander
Port
Output
Expander
Port
Input
PROG
49·0004748
4-330
NEe
J.lPD8748H
Timing Waveforms (coni)
Program/Verify
EA
VEAH
Vee
To
Vll1
Vee
RESET
VIl1
Next Address
P2Q-P21
49-0004756
Verify
Next Data
Out Valid
TO, RESET
Address (8-9) Valid
X________N_~_t_A_dd_re_s_s_~_n_~
_______
Note:
1. When EA Is "low" or TO = 5 V, PROG should be In floating condlton [".18 V].
2. tCY 41-15 can be achieved using 3.7 MHz frequency at the XAL 1 and XTAL2.
49-0004769
4-331
~
I
C".)
C".)
,.
Instruction Set
1:
Operation Code
I\)
Mnemonic
Operation
Description
D7
De
Ds
D4
D3
D2
D1
Do
Accumulator
ADD A, # data
(A) -
Add immediate the specified data to the accumulator.
0
d7
0
d6
0
d4
0
d3
0
d2
1
d1
1
do
1
0
d5
1
0
1
0
0
0
0
d2
(A) + data
ADDA, Rr
(A) - (A) + (Rr) for
r = 0-7
Add contents of designated register to the accumulator.
0
ADDA,@Rr
(A) - (A) + ((Rr)) for
r = 0-1
Add indirect the contents of the data memory location to the
accumulator.
0
ADDC A, # data
(A) -
Add immediate with carry the specified data to the
accumulator.
0
d7
0
d6
0
d5
1
d4
0
d3
ADDC A, Rr
(A) - (A) + (C) + (Rr)
for r = 0-7
Add with carry the contents of the designated register to the
accumulator.
0
1
1
1
1
ADDCA, @Rr
(A) - (A) + (C) + ((Rr))
forr = 0-1
Add indirect with carry the contents of data memory location to
the accumulator.
0
ANLA, # data
(A) -
Logical AND specified immediate data with accumulator.
ANLA, Rr
(A) - (A) AND (Rr) for
r = 0-7
Logical AND contents of designated register with accumulator.
0
d7
0
ANLA, @Rr
(A) - (A) AND ((Rr)) for
r = 0-1
Logical AND indirect the contents of data memory with
accumulator.
0
CPLA
(A) -NOT (A)
Complement the contents of the accumulator.
0
0
CLRA
(A)-O
Clear the contents of the accumulator.
0
0
1
0
0
Decimal adjust the contents of the accumulator.
0
1
0
1
0
0
0
(A) + (C) + data
(A) AND data
DAA
1
d6
0
d5
0
0
1
d4
0
d3
0
d2
1
1
0
C
•
F1
0
CD
~
CD
:z:
•
1
d1
1
do
•
•
1
d1
1
do
0
0
DECA
(A)-(A)-1
Decrement by 1the accumulator's contents.
0
0
0
INCA
(A)-(A)+1
Increment by 1the accumulator's contents.
0
0
0
1
0
ORLA, # data
(A) -
Logical OR specified immediate data with accumulator.
0
d7
1
d6
0
d5
0
d4
0
d3
ORLA, Rr
(A) - (A) OR (Rr) for
r = 0-7
Logical OR contents of designated register with accumulator.
0
1
0
0
1
ORLA, @Rr
(A) - (A) OR ((Rr)) for
r = 0-1
Logical OR indirect the contents of data memory location with
accumulator.
0
0
0
0
RLA
(AN + 1) - (AN); N = 0-6
(Ao) -(A7)
Rotate accumulator left by 1 bit without carry.
0
0
RLCA
(AN + 1) - (AN); N = 0-6
(Ao)-(C)
(C)-(Al)
Rotate accumulator left by 1bit through carry.
RRA
(AN) - (AN + 1); N = 0-6
(Al) -(Ao)
Rotate accumulator right by 1bit without carry.
0
RRCA
(AN) - (AN + 1); N = 0-6
(Al)-(C)
(C)-(Ao)
Rotate accumulator right by 1bit through carry.
0
(A) OR data
Byte.
•
0
0
Cycl••
Flag.
AC FO
0
•
1
0
d2
1
d1
1
do
0
•
0
0
0
•
~
~
Instruction Set (cont)
Operation Code
Mnemonic
Operation
Description
D7
Swap the 2 4-bit nibbles in the accumulator.
0
Logical XOR specified immediate data with accumulator.
1
d7
1
Ds
D4
D3
D2
D1
Do
0
0
0
1
1
1
1
d6
0
d5
1
d4
0
d3
0
d2
1
d1
1
do
1
0
1
0
0
a3
r
a2
r
a1
r
aO
a2
1
a2
a1
1
a1
0
a3
0
a3
1
a2
1
a2
1
a2
1
a1
1
a1
0
0
De
Accumulator (cont)
SWAP A
(A4-A7)
XRLA, # data
(A) -
XRLA, Rr
(A) - (A) XOR (Rr) for
r = 0-7
Logical XOR contents of designated register with accumulator.
XRLA,@Rr
(A) - (A) XOR ((Rr)) for
r = 0-1
Logical XOR Indirect the contents of data memory location with
accumulator.
(Rr) - (Rr) - 1; r = 0-7
If (Rr) "* 0;
(PCO-PC7) - addr
Decrement the specified register and test contents.
(PCO-PC7) - addr if Bb = 1
(PC) - (PC) + 2 if Bb = 0
Jump to specified address if accumulator bit is set.
JC addr
(PCO-PC7) - addr if C = 1
(PC) - (PC) + 2 if C = 0
Jump to specified address if carry flag is set.
JFO addr
(PCO-PC7) - addr if FO = 1
(PC) - (PC) + 2 if FO = 0
Jump to specified address if flag FO is set.
JF1 addr
(PCO-PC7) - addr if F1 = 1
(PC) - (PC) + 2 if F1 = 0
JMP addr
++
(Ao-A3)
(A) XOR data
Cycles
Bytes
C
Flags
AC FO
F1
~~
Branch
DJNZ Rr, addr
a6
a5
b2
a7
bO
a5
1
a7
b1
a6
1
a6
1
a5
a4
1
a4
a7
0
a6
Jump to specified address if flag F1 is set.
0
a7
1
a6
1
a5
1
a5
1
a4
1
a4
(PCS-PC10) - (addrs-addr10)
(PCO-PC7) - (addro-addr7)
(PC11) -DBF
Direct jump to specified address within the 2K address block.
a10
a7
ag
a6
as
a5
0
a4
JMPP@A
(PCO-PC7) -
Jump indirect to specified address with address page.
JNC addr
(PCO-PC7) - addr if C = 0
(PC) - (PC) + 2 if C = 1
Jump to specified address if carry flag is low.
0
a3
JNI addr
(PCO-PC7) - addr if I = 0
(PC) - (PC) + 2 if I = 1
JNTO addr
JBbaddr
~
I
w
w
w
0
a4
a7
((A))
0
a3
0
a3
0
a3
a7
a6
a5
0
a4
Jump to specified address if interrupt is low.
1
a7
0
a6
0
a5
0
a4
0
a3
(PCO-PC7) - addr if TO = 0
(PC) - (PC) + 2 if TO = 1
Jump to specified address if test 0 is low.
0
a7
0
a6
1
a5
0
a4
0
a3
JNT1 addr
(PCO-PC?) - addr ifT1 = 0
(PC) - (PC) + 2 ifT1 = 1
Jump to specified address if test 1is low.
(PCO-PC7) - addr if A = 0
(PC) - (PC) + 2 if A = 1
Jump to specified address if accumulator is non-zero.
1
a6
0
a6
0
as
JNZaddr
0
a7
1
a?
0
a5
0
a4
1
a4
0
a3
0
a3
JTF addr
(PCO-PC7) - addr if TF = 1
(PC) - (PC) + 2 if TF = 0
Jump to specified address if timer flag is set to 1.
0
a?
0
a6
0
a5
1
a4
0
a3
JTO addr
(PCo-PC?) - addr if TO = 1
(PC) - (PC) + 2 if TO = 0
Jump to specified address if test 0 is a 1.
0
a7
0
a6
1
a5
1
~
0
a3
(PCo-PC?) - addr ifT1 = 1
(PC) - (PC) + 2 ifT1 = 0
Jump to specified address if test 1 is a 1.
0
a7
1
a6
0
a5
~
JT1 addr
II
1
0
a3
0
a1
0
ao
0
ao
0
ao
0
ao
0
ao
0
aO
a2
1
a2
1
a2
a1
1
a1
1
a1
0
aO
1
a2
1
a2
1
a2
1
a1
1
a1
0
ao
0
ao
1
a1
0
ao
1
a2
1
a2
1
a1
0
ao
1
a1
0
ao
0
aO
1::
11
D
CD
~
CD
:.::
.J:>.
I
(.)
(.)
1:
Instruction Set (cont)
Operation Code
.J:>.
Mnemonic
Operation
Description
(PCO-PC7) - addr if A = 0
(PC) - (PC) + 2 if A = 1
Jump to specified address if accumulator is O.
D7
De
Ds
D4
D3
D2
D1
Do
a7
a6
0
a5
0
a4
0
a3
a2
a1
0
aO
0
0
Cycles
Bytes
Branch (cont)
JZ addr
EN I
Enable the external interrupt input.
0
Disable the external interrupt input.
0
ENTO ClK
Enable the clock output pin TO.
0
SEl MBO
0
0
F1
"a
CD
;:
CD
Z
Control
DIS I
C
Flags
AC FO
0
0
(DBF) -0
Select bank 0 (locations 0-2047) of program memory.
SEl MB1
(DBF)-1
Select bank 1(locations 2048-4095) of program memory.
SELRBO
(BS)-O
Select bank 0 (locations 0-7) of data memory.
SEl RB1
(BS)-1
Select bank 1(locations 24-31) of data memory.
0
MOV A,.# data
(A) -data
Move immediate the specified data into the accumulator.
MOVA, Rr
(A) -
(Rr); r = 0-7
Move the contents of the designated registers into the
accumulator.
MOVA,@Rr
(A) -
((Rr)); r = 0-1
Move indirect the contents of data memory location into the
accumulator.
MOVA, PSW
(A)-(PSW)
Move contents of the program status word into the
accumulator.
MOV Rr, # data
(Rr) -
data; r = 0-7
Move immediate the specified data into the deSignated
register.
1
d7
0
d6
MOV Rr, A
(Rr) -
(A); r = 0-7
Move accumulator contents into the deSignated register.
1
0
MOV@Rr,A
({Rr)) -
(A); r = 0-1
Move indirect accumulator contents into data memory location.
MOV@Rr,
# data
({Rr)) -
data; r = 0-1
Move immediate the specified data into data memory.
0
0
1
1
0
0
0
0
0
0
11
0
Data Moves
0
d7
1
0
d6
1
1
d5
1
0
d3
1
1
0
1
d7
0
0
0
1
d5
1
1
d4
1
d3
r
d2
0
1
0
0
1
d4
1
0
d3
0
d2
0
1
0
0
0
0
0
0
0
0
0
0
0
(PSW)-{A)
Move contents of accumulator into the program status word.
MOVPA,@A
(PCO-PC7) - (A)
(A)-{{PC))
Move data in the current page into the accumulator.
0
MOVP3A,@A
(PCO-PC7) - (A)
(PCS-PC10) - 011
(A)-((PC))
Move program data in page 3 into the accumulator.
MOVXA,@R
(A) -
({Rr)); r = 0-1
Move indirect the contents of external data memory into the
accumulator.
0
0
MOVX@R,A
({Rr)) -
(A); r = 0-1
Move indirect the contents of the accumulator into external
data memory.
0
0
XCH A, Rr
(A) ++ (Rr); r = 0-7
0
d5
0
0
1
d1
1
do
r
d1
r
do
0
d1
1
1
do
0
0
MOVPSW, A
0
0
d2
0
0
d6
1
Exchange the accumulator and deSignated register's contents.
0
d4
~
0
Instruction Set (cont)
Operation Code
Mnemonic
Operation
Data Moves (cont)
XCHA, @Rr
(A)
XCHDA,@Rr
++
Description
((Rr)); r
(Ao-A3)
r = 0-1
++
= 0-1
((Rr))o-((Rr))s;
D7
D6
Exchange indirect contents of accumulator and location in data
memory.
Exchange indirect 4-bit contents of accumulator and data
memory.
Ds
0
0
D4
D3
D2
0
0
0
0
Dl
DO
Cycles
Bytes
C
Flags
AC FO
F1
0
~
~
Flags
CPLC
(C) -NOT(C)
Complement contents of carry bit.
CPL FO
(FO) -
NOT (FO)
Complement contents of flag Fa.
CPL F1
(F1) -
NOT (F1)
Complement contents of flag F1.
CLRC
(C)-O
Clear contents of carry bit to O.
0
1
0
CLR Fa
(FO)-a
Clear contents of flag 0 to O.
0
0
0
CLR F1
(F1)-0
Clear contents of flag 1to O.
0
0
Input I Output
ANL BUS,
# data
(bus) -
I
0
•
•
1
d7
a
d6
0
d5
1
d4
1
d3
0
d2
a
dl
0
do
(Pp) - (Pp) AND data
p = 1-2
logical AND immediate specified data with designated
port (1 or 2).
1
d7
0
d6
0
d5
1
d4
1
d3
0
d2
P
dl
P
do
ANLD Pp, A
(Pp) - (Pp) AND (Ao-A3);
p = 4-7
logical AND contents of accumulator with designated port
(4-7).
1
a
0
1
1
P
P
INA, Pp
(A) -
Input data from designated port (1-2) into accumulator.
0
0
0
0
0
INS A, BUS
(A) -(bus)
Input strobed bus data into accumulator.
a
0
0
0
MOVDA, Pp
(Ao-A3) - (Pp); P = 4-7
(A4-A7) - 0
Move contents of designated port (4-7) into accumulator.
0
0
0
ANL Pp,
~
0
Logical AND immediate specified data with contents of bus.
# data
MOVD Pp, A
(Pp) -
ORLBUS,
# data
(bus) -
ORlD Pp, A
ORL Pp,
(bus) AND data
•
0
0
(Pp); p = 1-2
(Ao-A3); P = 4-7
Move contents of accumulator to designated port (4-7).
0
1
1
1
1
Logical OR immediate specified data with contents of bus.
1
d7
0
d6
0
d5
0
d4
1
d3
0
d2
(Pp) - (Pp) OR (Ao-A3);
P = 4-7
logical OR contents of accumulator with designated port
(4-7).
1
0
0
a
1
# data
(Pp) - (Pp) OR data
p = 1-2
Logical OR immediate specified data with designated port
(1-2).
1
d7
0
d6
0
d5
a
d4
1
d3
0
d2
OUTL BUS, A
(bus) -(A)
Output contents of accumulator onto bus.
0
0
0
0
0
0
OUTL Pp,A
(Pp) -
Output contents of accumulator to designated port (1-2).
a
0
1
1
1
0
(bus) OR data
(A); P = 1-2
0
0
dl
0
do
p
P
P
dl
P
do
0
1::
Registers
DEC Rr (Rr)
(Rr) -
(Rr) + 1; r
INC Rr
(Rr) -
(Rr)
INC@Rr
((Rr))-((Rr))
r = 0-1
=
= 0-7
= 0-7
Decrement by 1contents of designated register.
1
1
0
Increment by 1 contents of designated register.
0
0
0
1
1;
Increment indirect by 1the contents of data memory location.
0
0
0
0
1; r
=
"a
0
CD
0
~
CD
VJ
VJ
::z:
01
II
~
I
(J.)
(J.)
0)
1::
Instruction Set (cont)
Operation Code
Mnemonic
Operation
Description
Dr
De
Ds
D4
D3
((SP)) -- (PC)
(PSW4-PSW7),
(SP) -- (SP) + 1
(PCs-PC1Q) -- (addrS-addr1Q)
(PCO-PC7) -- (addro-addr7)
(PC11) -- DBF
Call designated subroutine.
a10
a7
a9
a6
as
a5
a4
RET
(SP) -- (SP) = 1
(PC) -- ((SP))
Return from subroutine without restoring program status word.
a
a
a
RETR
(SP) -- (SP) = 1
(PC) -- ((SP))
(PSW4-PSW7) -- ((SP))
Return from subroutine restoring program status word.
a
D2
D1
Do
a3
a2
a1
aO
a
a
a
a
Bytes
C
F1
"a
CD
~
Subroutine
CALLaddr
Cycles
Flags
AC FO
a
CD
:z
Timer I Counter
EN TCNTI
Enable internal interrupt flag for timer I counter output.
DIS TCNTI
Disable internal interrupt flag for timer I counter output.
a
Move contents of timer I counter into accumulator.
0
MOVA, T
(A)--(T)
MOVT, A
(T)-(A)
a
a
a
1
1
a
1
1
0
0
0
0
0
0
0
0
Move contents of accumulator into timer I counter.
0
STOP TCNT
Stop count for event counter.
0
1
a
STRT CNT
Start count for event counter.
0
0
0
STRTT
Start count for timer.
0
0
0
No operation performed.
0
0
Miscellaneous
NOP
0
0
0
0
0
0
0
Note:
(1) Instruction code designations rand p form the binary representation of the registers and ports involved.
(2) The dot under the appropriate flag bit indicates that its content is subject to change by the instruction it appears in.
(3) References to the address and data are specified in bytes 2 and/or 1 of the instruction.
(4) Numerical subscripts appearing in the function column reference the specific bits affected.
~
~
NEe
J.lPD8748H
Instruction Set Symbol Definitions
Symbol
Description
A
Accumulator
AC
Auxiliary carry flag
Symbol
Pp
PSW
Description
Port designator (p=1, 2 or 4-7)
Program status word
Program memory address (12 bits)
Rr
Bb
Bit designator (b = 0-7)
SP
Stack pointer
BS
Bank switch
T
Timer
Timer flag
addr
BUS
Bus port
TF
C
Carry flag
TO, T1
Register designator (r=O, 1or 0-7)
Testable flags 0, 1
ClK
Clock signal
x
External RAM
CNT
Event counter
#
Prefix for immediate data
Nibble designator (4 bits)
@
Prefix for indirect address
data
Number or expression (8 bits)
$
Program counter's current value
DBF
Memory bank flip-flop
(x)
Contents of external RAM location
0
FO, F1
Flags 0, 1
I
Interrupt
"I n-page" operation designator
((x))
Contents of memory location addressed by the
contents of external RAM location
Replaced by
4-337
J.lPD8748H
4-338
NEe
NEe
16.BIT, SINGLE·CHIP MICROCOMPUTERS
5-1
D
16-BIT, SINGLE-CHIP MICROCOMPUTERS
NEe
Section 5 - is-Bit, Single-Chip Microcomputers
pPD70320/322
CMOS Microcomputers (V25™) .... . . . . . . . . . . . . . . . . • . . . . . . . .. 5-3
V25 is a trademark of NEC Corporation.
5-2
NEe
NEe Electronics Inc.
pPD70320/322 (V25™)
16·BIT,SINGLE·CHIP
CMOS MICROCOMPUTERS
PRELIMINARY INFORMATION
Description
The pPD70320 and pPD70322 (V25™) are high-performance, 16-bit, single-chip microcomputers with an
8-bit external data bus. They combine the instruction
set of the pPD70108 (V20TM) with many of the on-chip
peripherals in NEC's 78000 series.
The pPD70320/322 processor has software compatibility with the V20 (and subsequently the 8086/8088),
faster memory accessing, superior interrupt processing
ability, and enhanced control of internal peripherals.
A variety of on-chip components, including 16K bytes
of mask programmable ROM (pPD70322 only), 256
bytes of RAM, serial and parallel I/O, comparator port
lines, timers, and a DMA controller make the pPD70320/
322 a sophisticated microsystem.
Eight banks of registers are mapped into internal RAM
below an additional 256-byte special function register
(SFR) area that is used to control on-chip peripherals.
I nternal RAM and the SFR area are together relocatable
to anywhere in the 1M-byte address space. This
maintains compatibility with existing system memory
maps.
D DRAM refresh pulse output
D Two standby modes
-HALT
-STOP
D I nternal clock generator
- 5-MHz maximum frequency (O.4-ps instruction
cycle time) (target specification: 8 MHz)
D Programmable wait state generation
D Separate address/data bus interface
D CMOS technology
Ordering Information
Part Number
Package Type
pPD70320G-12
80-pin plastic miniflat
pPD70322G-12
80-pin plastic miniflat
pPD70320L
84-pin PLCC (plastic lead led chip carrier)
pPD70322L
B4-pin PLCC (plastic lead led chip carrier)
Pin Configurations
80-Pin Plastic Minlflat
The pPD70322 is the mask ROM version and the
pPD70320 is the ROM-less version.
Features
D Complete single-chip microcomputer
-16-bit ALU
- 16K bytes of ROM (pPD70322)
- 256 bytes of RAM
D Four-byte instruction prefetch queue
D 24 parallel 1/0 lines
D Eight analog comparator inputs with programmable
threshold level
D Two independent DMA channels
D Two 16-bit timers
D Programmable time base counter
D Two full-duplex UARTs
D Programmable interrupt controller
- Eight priority levels
- Five external, 12 internal sources
- Register bank (eight) context switching
- Eight macro service function channels
POs
PO,fCLKOUT
PT2
P17/REAOY
P14/1NT/POLL
P13/1NTP2/1NTAK
P1,/iN"FPO
AS
P10/NMI
AS
P26/ HI:"i5AK
AS
P2s/TC1
Ag
P23/DMARQl
V20 and V25 are trademarks of NEC Corporation.
83-003943A
5-3
NEe
pPD70320/322 (V25)
Pin Configurations (cont)
Pin Identification
Symbol
B4-Pin PLCC
P07/ClKOUT
Address bus outputs
00- 07
Bidirectional data bus
X1, X2
Crystal connection terminals
RESET
Reset input
VDD
Positive power supply voltage
Vss
Ground
VTH
Threshold voltage input
P16/ SCKO
PTO-PT7
.Comparator port input lines.
P14 /INT/POLl.
EA
External access
P17/REAOY
P13/1NTP2/1NTAK
P23/0 MAR01
:::::::II~~I~~~IIY!II~Y
MREQ
Memory request output
POO-P07
I/O port 0
CLKOUT
System clock output
NMI
Nonmaskable interrupt input
P11-P1~
Parallel input port lines/
External interrupt input lines
P1311NTP211NTAK
Parallel input port line/
External interrupt input line/
Interrupt acknowledge output
P14"NT/POLL
I/O port 111nterrupt request input!
I/O poll input
P151T0UT
I/O port 1 bit/Timer out
P16/SCKO
I/O port 1 bit/Serial clock out
P17/REAOY
I/O port 1 bit/Ready input
P20/OMARQO
I/O port 2 bit/OMA request 0
P21/DMAARO
I/O port 2 bit/DMA acknowledge 0
P22ITCO
I/O port 2 bitlDMA terminal count 0
P23/DMARQ1
I/O port 2/DMA request 1
P24IDMAAK1
I/O port 2/DMA acknowledge 1
P25/TC1
I/O port2IDMAterminai count 1
iNml-1
ceQ.
~
f
83-003960A
5-4
Function
Ao-A19
P26/HLDAK
I/O port 2/Hold acknowledge output
P27/HLDRQ
I/O port 2/Hold request input
10STB
I/O strobe output
MSTB
Memory strobe output
R/W
Read/Write output
REFRQ
Refresh pulse output
RxDO
Serial receive data 0 input
CTSO
Clear to send 0 input
TxDO
Serial transmit data 0 output
RxD1
Serial receive data 1 input
CTS1
Clear to send 1 input
Tx01
Serial transmit data 1 output
NEe
pPD70320/322 (V25)
Pin Functions
P10-P17 [Port 1 ]
Ao-A19 [Address Bus]
P1 rP13 are the input only lines of parallel port 1. P10
and P14-P17 are the remaining lines of parallel port 1,
each line individually programmable as either an input
or output.
Ao-A19 is the 20-bit address bus used to access all
external devices.
00-07 [Data Bus]
0 0-0 7 is the a-bit external data bus.
RESET [Reset]
A low on RESET resets the CPU and all on-chip
peripherals. RESET can also release the standby
modes. After RESET returns high, program execution
begins from address FFFFOH.
X1, X2 [Crystal Connections]
The internal clock generator requires an external
crystal across these terminals.
P20-P27 [Port 2]
P20-P27 are the lines of port 2, an a-bit bidirectional 1/0
port. The lines can also be used as control signals for
theon-chip OMA controller.
CLKOUT [System Clock]
This is the internal system clock. It can be used to
synchronize external devices to the CPU.
NMI [Nonmaskable Interrupt]
Two positive power supply pins (VDD) reduce internal
noise.
NMI cannot be masked through software and is typically
used for emergency processing. Upon execution, the
interrupt starting address is obtained from interrupt .
vector number 2. NMI can release the standby modes
and can be programmed to be either rising or falling
edge triggered.
Vss [Ground]
INTPO-INTP2 [External Interrupt]
Two ground connections (Vss) reduce internal noise.
INTPO-INTP2 allow external devices to generate 1/0
requests (interrupts). Each can be programmed to be
rising or falling edge triggered.
Voo [Power Supply]
VTH [Threshold Voltage]
The comparator port uses this pin to determine the
analog reference point. The actual threshold to each
comparator line can be VTH or VTH x n/16, where n = 1
to 15.
INTAK [Interrupt Acknowledge]
After INT is asserted, the CPU will respond with
INTAK (active low) to inform external devices thatthe interrupt
request has been granted.
EA [External Access]
If this pin is low on reset, the pP070322 will execute
program code from external memory instead of from
internal ROM.
INT [Interrupt Request]
INT is a maskable, active-low, vectored interrupt
request input. After assertion, external hardware must
provide the interrupt vector number.
MREQ [Memory Request]
MREQ (active low) informs external memory that the
current bus cycle is a memory access bus cycle.
PTO-PT7 [Comparator Port]
PTO-PT7 are inputs to the analog comparator port.
POO·P07 [Port 0]
POO-P07 are the lines of port 0, an a-bit bidirectional
parallel 1/0 port.
POLL [Poll]
Upon execution of the POLL intruction, the CPU
checks the status of this pin and, if low, program
execution continues. If high, the CPU will check the
level of the line every five clock cycles until it is low.
POLL can be used to synchronize program execution
to external conditions.
TOUT [Timer Out]
TOUT is the square-wave output signal from the
internal timer.
D
NEe
pPD70320/322 (V25)
SCKO, TxOn, CTSn, RxDn [Serial Clock
Out, Serial Transmit Data, Clear to Send,
Serial R.ceive Data]
An HLOAK output (active low) informs external devices
that the CPU has released the system bus.
The two on-chip serial ports use these lines for data
transmission, receiving, and handshaking.
10STB [I/O Strobe]
READY [Ready]
10STB is asserted during read and write operations to
external 1/0.
After READY is asserted (active low), the CPU will
synchronize and insert at least two wait states into a
read or write cycle to memory or 1/0. This allows the
processor to accommodate devices whose access
times are longer than normal' execution allows.
OMARan, OMAAKn, TCn [OMA Request, DMA
Acknowledge, Terminal Count]
These are the control signals to and from the on-chip
DMA controller.
HLDRQ [Hold Request] .
The HLDRQ input (active low) is used by external
devices to request the CPU to release the system bus to
an external bus master. The following lines go into a
high-impedance state ~ternal 4.7-kO pull-up
resistors: Ao-A19, 00-07, MREQ; R/W, and MSTB.
HLDAK [Hold Acknowledge]
MSTB [Memory Strobe]
MSTB (active low) is asserted during read and write
operations to external memory.
R/W [Read/Write]
An R/W output allows external hardware to determine
if the current operation is a read or write cycle. It can
also control the direction of bidirectional buffers.
REFRQ [Refresh]
This active-low output pulse can refresh nonstatic
RAM. It can be programmed to meet system specifications and is internally synchronized so that refresh
cycles do not interfere with normal CPU operation.
NEe
pPD70320/322 (V25)
Block Diagram
.---,,---.../1
P20/DMARQO
Staging Staging
Latch Latch
Ao-AI9
P2,/!mAAirn
P2:Vm
P2a1DMARQI
P24/DMAAKI
p2siTC1
TxDO
RxDO
CTSO
TxD'
RxDl
RESET
HLDAK/P26
PloiNMI
HLDRQ/P27
Pl,/INTPO
READY/PI7
P12/1NTPI
MSTB
PlaiINTP2/1NTAK
P14/1NT/POLI
Instruction Decoder
Micro Sequencer
Xl-
Micro ROM
POLLIINT/P1 4
Clock
Generator
X2 -
00-07
TOUT/PIS
iiEFRO
CLKOUTIP07
~-7
NEe
pPD70320/322 (V25)
Fu nctiona. Description
AW
Word multiplication/division, word I/O, data
conversion
AL
Byte multiplication/division, byte I/O, BCD
rotation, data conversion, translation
AH
Byte multiplication/division
BW
Translation
Architectural Enhancements
The following features enable the pPD70320/322 to
perform high-speed execution of instructions:
• Dual data bus
• 16-/32-bit temporary registers/shifters (TA, TB,
TA +TB)
• 16-bit loop counter (LC)
• Program counter (PC) and prefetch pointer (PFP)
Dual Data Bus. The pPD70320/322 has two internal
16-bit data buses: the main data bus and a subdata bus.
This reduces the processing time required for addition/
subtraction, and logical comparison instructions by
one third over single bus systems. The dual data bus
method allows two operands to be fetched simultaneously from the general purpose registers and
transferred to the ALU.
16-/32-Bit Temporary Registers/Shifters. The 16-bit
temporary registers/shifters (TA, TB) allow high-speed
execution of multiplication/ division and shift/rotation
instructions. By using the temporary registers/shifters,
the pPD70320/322 can execute multiplication/division
instructions about four times faster than with the
microprogramming method.
Loop Counter [LC]. The dedicated hardware loop counter
counts the number of loops for string operations and the number of shifts performed for multiple
bit shift/rotation instructions. The loop counter works
with internal dedicated shifters to speed the processing
of multiplication/division instructions.
Program Counter and Prefetch Pointer [PC and PFP].
The hardware PC addresses the memory location of
the instruction to be executed next. The hardware PFP
addresses the program memory location to be accessed
next. Several clocks are saved for branch, call, return,
and break instructions compared with processors
having only one instruction pointer.
Register Set
Figure 1 shows the pPD70320/322 has eight banks of
registers functionally mapped into internal RAM. Each
bank contains general purpose registers, pOinter and
index registers, segment registers, and save areas.
General Purpose Registers [AW, BW, CW, OW]. There
are four 16-bit general purpose registers that can each
serve as individual 16-bit registers or two independent
8-bit registers (AH, AL, BH, BL, CH, CL, DH, DL). The
following instructions usethegeneral purpose registers
for default:
CW
Loop control branch, repeat prefix
CL
Shift instructions, rotation instructions, BCD
operations
OW
Word multiplication/division, indirect addressing I/O
Pointers [SP, BP] and Index Registers [IX, IV]. These
registers are used as 16-bit base pointers or index
registers in based addressing, indexed addressing,
and based indexed addressing. The registers are used
as default registers under the following conditions:
SP
Stack operations
IX
Block transfer (source), BCD string operations
IY
Block transfer (destination), BCD string
operations
Segment Registers. The segment registers divide the
1M-byte address space into 64K-byte blocks. Each
segment register functions as a base address to a
block; the effective address is an offset from that base.
Physical addresses are generated by shifting the associatedsegment register left four binary digits and then
adding the effective address. The segment registers
are:
Segment Register
Defau It Offset
PS (Program segment)
SS (Stack segment)
DSO (Data segment-O)
DS1 (Data segment-1)
PC
SP, Effective address
IX, Effective address
IY, Effective address
Save Registers. SAVE PC and SAVE PSW are used as
save areas during register bank context switching. The
VECTOR PC save location contains the effective
address of the interrupt service routine when register
bank switching is used to ~ervice interrupts.
Program Counter [PC]. The PC is a 16-bit binary
counter that contains the offset address from the
program segment ofthe next instruction to be executed.
It is incremented every time an instruction is received
from the queue. It is loaded with a new location
whenever a branch, call, return, break, or interrupt is
executed.
NEe
pPD70320/322 (V25)
Processor Status Word [PSW]. The PSW contains the
following status and control flags.
15
PSW
I
1
I RB2 I RB1
RBO
s
I
AC
I
8
I DIR
V
7
I
I
z
F1
Status Flags
V
Overflow bit
S
Sign
Z
Zero
AC Auxiliary carry
P
Parity
CY
Carry
FO
P
IE
BRK
I BRKI I
CY
I
o
I
Control Flags
DIR
Direction of string
processing
IE
Interrupt enable
BRK
Break (after every
instruction)
RBn
Register bank select
BRKI
I/O trap enable (see
software interrupts)
FO, F1 General-purpose
user flags (accessed
through the flag
special function
register)
Memory Map
The pPD70320/322 has a 20-bit address bus that can
directly access 1M bytes of memory. Figure 2 shows that
the 16K bytes of internal ROM (pPD70322
only) are located at the top of the address space from
FCOOOH to FFFFFH.
Figure 1.
Internal Data Area. Figure 2 shows the internal data
area (IDA) is a 256-byte internal RAM area followed
consecutively by a 256-byte special function register
(SFR) area. All the data and control registers for onchip peripherals and 110 are mapped into the SFR area
and accessed as RAM. The IDA is dynamically relocatable in 4K-byte increments by changing the value in
the internal data base (lOB) register. Whatever value is
in this register will be assigned as the uppermost eight
bits of the IDA address.
On reset, the internal data base register is set to FFH
which maps the IDA into the internal ROM space.
However, since the pPD70322 has a separate bus to
internal ROM, this does not present a problem. When
these address spaces overlap, program code cannot be
executed from the IDA and internal ROM locations
cannot be accessed as data. You can select any of the
eight possible register banks which occupy the entire
internal RAM space. Multiple register bank selection
allows faster interrupt processing and facilitates mUltitasking.
In larger-scale systems where internal RAM is not
required for data memory, the internal RAM can be
removed completely from the address space and
dedicated entirely to registers and. control functions
such as macro service and DMA channels. Clearing the
RAMEN bit in the processor control register achieves
this. When the RAMEN bit iscleared, internal RAM can
only be accessed by register addressing or internal
control processes.
Register Banks in Internal RAM
AW
XXEFEH
XXFOOH
Bank 7
CW
CH
32 bytes
ow
Data Register
AH
XXEEOH
BW
XXEF8H
Bank 6
SP
6H
BP
XXECOH
Index Register
4H
IX
2H
IV
XXEFOH
DS1
~
EH
PS
Segment Register
CH
SS
XXE40H
AH
DSO
Bank1
XXEE8H
Save PC
6H
XXE20H
SavePSW
4H
BankO
XXEOOH
Vector PC
2H
XXEEOH
Reserved
Internal RAM
49-0013428
5-9
5
NEe
JiPD70320/322 (V25)
Figure 2.
Memory Map
FFFFFH
FFFFFH
Internal
ROM
XXFFFH -
FCOOOH
/
------,
XXEOOH
XXDFFH
Moves a string from
port
PREPARE
Allocates an area for a stack frame and
copies previous frame pointers
DISPOSE
Frees the current stack frame on a
procedure exit
/"
Special Function
Registers
(256 Bytes)
Internal RAM
(256 Bytes)
1--;
m~mory
OUTM
"
to an I/O
-;
1//
External
Area
Unique Instructions
The pPD70320/322 has the following unique
instructions.
Instruction Function
OOOOOH
OOOOOH
1 Mbyte Memory Space
49-001343A
Instruction Set
The pPD70320/322 instruction set is fully compatible
with the V20 native mode instruction set. The V20
instruction set is a superset of the pPDBOB6/BOBB
instruction set with different execution times and
mnemonics.
The pPD70320/322 does not support the V20 BOBO
emulation mode. All of the instructions pertaining to
this have been deleted from the pPD70320/322 instruction set.
INS
I nserts bit field
EXT
Extracts bit field
ADD4S
Performs packed BCD string addition
SUB4S
Performs packed BCD string subtraction
CMP4S
Performs packed BCD string
comparison
ROL4
Rotates BCD digit left
ROR4
Rotates BCD digit right
TEST1
Tests bit
SET1
Sets bit
CLR1
Clears bit
Enhanced Instructions
NOT1
Complements bit
In addition to the pPDBOB6/BB instructions, the
pPD70320/322 has the following enhanced instructions.
BTCLR
Tests bit; if true, clear and branch
REPC
Repeat while carry set
REPNC
Repeat while carry cleared
Instruction
Function
PUSH imm
Pushes immediate data onto stack
PUSH R
Pushes eight general registers onto
stack
POPR
Pops eight general registers from stack
MUL imm
Executes 16-bit multiply of register or
memory contents by immediate data
Shifts/rotates register or memory by
SHL immB
SHR immB
immediate value
SHRA immB
ROL immB
ROR immB
ROLC immB
RORC immB
CHKIND
Checks array index against designated
boundaries
INM
Moves a string from an I/O port to
memory
5-10
Variable Length Bit Field Operation Instructions
Bit fields are a variable length data structure that can
range in length from 1 to 16 bits. The pPD70320/322
supports two separate operations on bit fields: insertion
(INS) and extraction (EXT). There are no restrictions
on the position of the bit field in memory. Separate
segment, byte offset, and bit offset registers are used
for insertion and extraction. Following the execution of
these instructions, both the byte offset and bit offset
are left pointing to the start of the next bit field, ready
for the next operation. Bit field operation instructions
are powerful and flexible and are therefore highly
effective for graphics, high level languages, and packing/
unpacking applications.
Insert bit field copies the bit field of specified length
from the AW register to the bit field addressed by
DS1 :IY:regB (B-bit general purpose register). The bit
field length can be located in any byte register or
ttiEC
pPD70320/322 (V25)
supplied as immediate data. Following execution, both
the IY and reg8 are updated to point to the start of the
next bit field.
rotation instructions perform rotation of a single BCD
digit in the lower half of the AL register through the
register or the memory operand.
Bit field extraction copies· the bit field of specified
length from the bit field addressed by DSO:IX:reg8 to
the AW register. If the length of the bit field is less than
16 bits, the bit field is right justified with a zero fill. The
bit field length can be located in any byte register or
supplied as immediate data. Following execution; both
IX and reg8 are updated to point to the start of the next
bit field.
Figures 3 and 4 show bit field insertion and bit field
extraction.
Repeat Prefixes
Packed BCD
Two new repeat prefixes (REPC, REPNC) allow conditional block transfer instructions to use the state of
the CY flag as the termination condition. This allows
inequalities to be used when working on ordered data,
thus increasing performance when searching and
sorting algorithms.
Packed BCD instructions process packed BCD data
either as strings (ADD4S, SUB4S, CMP4S) or byte
format operands (ROR4, ROL4). Packed BCD strings
may be one to 254 digits in length. The two BCD
Figure 3.
Bit Manipulation Instructions
The J.lPD70320/322 has five unique bit manipulation
instructions. The ability to test, set, clear, or complement a single bit in a register or memory operand
increases code readability as well as performance over
the logical operations traditionally used to manipulate
bit data. This feature further enhances control over
on-chip peripherals.
Bit Field Insertion
Bit length
15
o
AW
Bit offset
Memory
Byte boundary
Segment base (OS1)
83-000106B
Figure 4.
Bit Field Extraction
Bit length
Bit offset
Byte boundary
Segment base (OSO)
83-000107B
ii-11
tttfEC
pPD70320/322 (V25)
Besides the V20 instruction set; the pPD70320/322
has the 'four additional instructions described in
table 1.
Table 1.
Additionallnstructlons
Instruction
Function
BTCLR Var,imm3,
short label
Bit test and if true, clear
and branch; otherwise, no operation
STOP (no operand)
Power down instruction, stops oscillator
RETRBI (no operand)
Return from register bank context switch
interrupt
FINT (no operand)
Finished interrupt. After completion of a
hardware interrupt or I/O request, this
instruction must be used to reset the current
priority bit in the in-service priority register
(ISPR).
The ISPR is an 8-bit register; each·of its bits, PRo-PR7,
correspond to each of the eight possible 110 request
priorities, respectively. The ISPR keeps track of the
priority of the interrupt currently being serviced by
setting the appropriate bit. The ISPR format is shown
below.
When executing software written for another system, it
is better to implementliO with on-chip peripherals to
reduce external hardware requirements. However, since
pPD70320/322 internal peripherals are memory mapped, software conversion could be difficult. The I/O
trap feature 'allows easy conversion from external
peripheralsto on-chip peripherals.
Interrupt Vector Table. Table 3 shows the starting
addresses of interrupt processing routines. The table
begins at physical address OH, which is outside the
internal ROM space. Therefore, if utilizing an interrupt
processing routine within the interrupt vector table,
external memory will be required. By servicing interrupts via the macro service function or context
switching, you can avoid the addition of external
memory.
Each interrupt vector is four bytes. Upon execution of a
vectored interrupt, the lower addressed word is transferred to the PC, and the upper word to the PS.
However, the byte order within each word is reversed
so that the low-order bytes of the vector address
become the most significant bytes in the PC and PS.
Hardware Interrupt Configuration. There are two types
of hardware interrupt requests: standard vectored
interrupts and I/O requests.
Interrupt Structure
The pPD70320/322 can service interrupts generated
through hardware and software. Table 2 shows the
various software interrupts.
Table 2.
Software Interrupts
Interrupt
Description
Divide error
The CPU will trap if a divide error occurs as the
result of a DlV or DlVU instruction,
Single step
The interrupt is generated after every instruction
if the BRK bit in the PSW is set.
Overflow
By using the BRKV instruction, an interrupt can be
generated as the result of an overflow.
Interrupt
instructions
The BRK 3 and BRK imm8 instructions can
generate interrupts.
Array bounds
The CHKIND instruction will generate an interrupt
if specified array bounds have been exceeded.
Escape trap
The CPU will trap on an FP01,2 instruction to
allow software to emulate the floating point
processor.
1/0 trap
5-12
If the 1/0 trap bit in the PSW is set, a trap will be
generated on every IN or OUT instruction.
Software can then provide an updated peripheral
address. This feature allows software
interchangeabilty between different systems.
After a vectored interrupt, the PC and PSW are saved
, on the stack and the program transfers to the location
indicated by the interrupt vector contents. When an
interrupt is triggered by NMI, the CPU automatically
traps to vector number two. When an interrupt is
triggered by INTR, external devices must provide the
interrupt vector number.
I/O requests are a group of interrupts, generated
externally or from on-chip peripherals. The internal
interrupt controller controls I/O requests. I/O requests
can be serviced (by the macro service function) without
transferring program control to an interrupt routine.
The following are the 14 possible I/O requests.
Group
Source
External interrupt
request
INTPO, INTP1, INTP2
DMA controller
INTDO,INTD1
Timer
INTTUO, INTTU1, INTTU2
Serial interface
INTSERO,INTSRO,
INTSTO,INTSER1,
INTSR1,INTST1
NEe
Table 3.
Address (HexJ
00
pPD70320/322 (V25)
Interrupt Vectors
Vector No.
0
Assigned Use
Divide error 04 1 Break flag
04
Break flag
08
NMI
BRK3 instruction
OC
3
10
4
BRKV instruction
14
5
CHKIND instruction
18
6
General purpose
1C
7
Escape trap
General purpose
20
24-3C
9-15
Reserved
40-4C
15-19
General purpose
50
20
110 trap
54-5C
21-23
General purpose
60
24
Reserved
64-6C
25-27
General purpose
70
28
INTSERO
74
29
INTSRO
78
30
INTSTO
7C
31
General purpose
80
32
INTSER1
84
33
INTSR1
88
34
INTST1
General purpose
8C
35
90
36
INTDO
94
37
INTD1
98-9C
38,39
General purpose
AO
40
INTPO
A4
41
INTP1
A8
42
INTP2
AC
43
General purpose
BO
44
INTTUO
B4
45
INTTU1
B8
46
INTTU2
BC
47
INTTB
OCO-3FF
48-255
General purpose
Arbitration of I/O requests is resolved internally by the
interrupt controller. The priority of each I/O request is
individually programmable from 0 to 7 (0 is the highest
priority). You can process these interrupts in one of
three modes: standard vectored interrupt, register
bank context switching, or macro service function.
When standard vectored interrupt mode is selected,
I/O requests are serviced as previously described
vectored interrupts. The CPU automatically traps to
the vector location shown in the interrupt vector table.
Register bank context switching allows I/O requests to
be processed rapidly by switching register banks. After
an interrupt, the new register bank selected is that
which has the same register banknumber (0-7) as the
priority of the interrupt to be serviced. The PC and PSW
are automatically stored in the save areas of the new
register bank and the address of the interrupt routine is
loaded from the vector PC storage location in the new
register bank. After interrupt processing, execution of
the RETRBI (return from register bank interrupt) returns
control to the former register bank and restores the
former PC and PSW. Figures 5 and 6 show register
bank context switching and registerbank return.
The macro service function (MSF) acts as an internal
DMA controller between on-chip peripherals (special
function registers) and memory. The MSF greatly
reduces the software overhead and CPU time that
other processors would require for register save
processing, register returns, and other handling
associated with interrupt processing.
If the MSF is selected for a particular I/O request, each
time the request is received, a byte or word of data will
be transferred between the SFR and memory without
interrupting the CPU. Each time a request occurs, the
macro service counter is decremented. When the
counter reaches zero, an interrupt is generated. The
MSF also has a character search option. When selected,
every byte transferred will be compared to an 8-bit
search character and an interrupt will be generated
if a match occu rs or if the macro service cou nter cou nts
out.
There are eight eight-byte macro service channels
mapped into internal RAM from XXEOOH to XXE3FH.
Figure 7 shows the components of each channel.
I)
ttlEC
pPD70320/322 (V25)
Figure 5.
Register Sank Context Switching
RB
Figure 7.
Macro Service Channels
RB'
AW
AW
CW
CW
ow
DW
BW
BW
SP
SP
c>
BP
f
Upto3FH
XXE08H
MSS
M.S_ Channel 0
MSP
BP
IIIII
SCHR
IV
OS1
DS1
SFRP
MSC
PS
P5
IX
IV
IX
SS
SS
OSO
OSO
r-
Save PC
SaveP
~~
Lr
MSS = Macro service segment
MSP = Macro service pointer
SCHR = Search character
5avePC
SFRP = Special function,register pointer
5avePSW
Vector PC
Vector PC
Reserved
Reserved
XXEOOH
MSC '" Macro service counter
r-
49-001345A
On-Chip Peripherals
PC
Timer Unit
PSW
49-001344A
Figure 6.
Register Sank Return
RB
RB'
AW
AW.
, CW
CW
ow
ow
BW
BW
SP
5P
BP
BP
V
IX
IV
IY
DS1
P5
PS
5S
55
DSO
D50
-'ruSave PC
Vector PC
.--
Save PC
f--
5avePSW
.
Reserved
4
L..L
Interval Timer Mode. In this mode, TMO/TM1 are
decremented. by the selected input clock and, after
counting out, the registers are automatically reloaded
from the modulus registers and counting continues.
Each time TM1 counts out, 1/0 requests are generated
through TF1 and TF2 (Timer Flags 1,2). When TMO
counts out, an 1/0 request is generated through TFO.
The timer out signal can be used as a square wave
output whose half-cycle is equal to the count time.
There are two selectable input clocks (SCLK: system
clock = fosc/2, fosc = 10 MHz).
IX
OS1
Vector PC
Reserved
PC
PSW
49-001346A
5-14
The jlP070320/322 (figure 8) has two programmable
16-bit interval timers (TMO, TM1) with variable input
clock frequencies on-chip. Each of the two 16-bit timer
registers has an associated 16-bit modulus register
(MOO, M01). The timer operates in interval timer mode
or one-shot mode.
Clock
Timer Resolution
Full Count
SCLK/6
SCLK/128
1.2 jlS
25.6 jlS
78.643 ms
1.678 s
One-Shot Mode. In the one-shot mode, TMO and MOO
operate as independent one-shot timers. Starting with
a preset value, each is decremented to zero. At zero,
counting ceases and an 1/0 request is generated by
TFO orTF1. One-shot mode allows two selectable input
clocks (fosc = 10 MHz).
Clock
Timer Resolution
Full Count
SCLK/12
SCLK/128
2.4 jlS
25.6 jlS
157.283 ms
1.678 s
t-IEC
pPD70320/322 (V25)
Time Base Counter
The pPD70320/70322 has a free-running long base
cou nter that can be used to generate period ic interrupts
at lengthy intervals. The counter has three selectable
input clocks: SCLK, SCLK/2, and SCLK/4. You can
select one of the following four taps (outputs) from the
counter as an interrupt source: i/1024, i/8192, i/64K, or
i/1 M ("i" is the selected input clock).
The TBC interrupt is unlike the other on-chip peripheral
I/O requests in that it is preset as a level seven vectored
interrupt. Macro service and register bank switching
cannot be used to service this interrupt. Figure 9
is the time base counter block diagram.
modes. Refresh cycles are automatically timed to
REFRQ following read/write cycles to minimize the
effect on system throughput.
The following shows the REFRQ pin level in relation
to bits 4 (RFEN) and 7 (RELV) of the refresh mode
register.
--
--
RELV
REFRQ Level
0
0
1
1
RFEN
0
1
0
1
0
1
0
Refresh pulse output
Figure 9.
Time Base Counter Block Diagram
Refresh Controller
The pPD70320/322 has an on-chip refresh controller
for dynamic and pseudostatic RAM mass storage
memories; The refresh controller generates refresh
addresses and refresh pulses. It inserts refresh cycles
between the normal CPU bus cycles according to
refresh specifications.
i i i
1024
8192
64K
i
1M
49-00134BA
The refresh controller outputs a 9-bit refresh address
on address bits Ao-As during the refresh bus cycle.
Address bits As-A19 are all 1'so The 9-:bit refresh
address is automatically incremented at every refresh
timing for 512 row addresses. The 8-bit refresh mode
(RFM) register specifies the refresh operation and
allows refresh during both CPU HALT and HOLD
Figure 8.
Timer Unit Block Diagram
,---------------------
"I
I
I
I
I
I
lose/ 6
fose/ 128
I
I
I
fose/ 12
fose/ 128
I
I
lose/ 6
fose/ 12
fose/ 128
L
-- -- -
o
Output
Control
-
r---~TO
TI ------------ __
Internal Bus
I
-.J
~
49-0013478
ttiEC
pPD70320/322 (V25)
Serial Interface
ThepPD70320/322 has two full-duplex UARTs, channel
o and channel 1. Each serial port channel has a
transmit line (TxDn), a receive line (RxDn), and a clear
to send (CTSn). input line for handshaking. Communication is synchronized by a start bit, and you can
program the ports for even, odd, or no parity, character
lengths of seven or eight bits, and one or two stop bits.
The pPD70320/322 has dedicated baud rate generators
for each serial channel. This eliminates the need to
obligate the on-chip timers. The baud rate generator
allows a wide range of data transfer rates (up to 1
Mbps). This includes all of the standard baud rates
without being restricted by the value of the particular
external crystal. Each baud rate generator has an 8-bit
baud rate generator (BRGn) data register which functions as a prescaler to a programmable input clock
selected by the serial communication control (SCCn)
register. Together these must be set to generate a
frequency that is equivalent to the desired baud rate.
In addition to the asynchronous mode, channel 0 has a
synchronous I/O interface mode. In this mode, each bit
of data transferred is synchronized to a serial clock
(SCKO). This is the same as the NEG pCOM75 and
pCOM87 series, and allows easy interfacing to these
devices. Figure 10 shows the serial interface block
diagram.
DMA Controller
The pPD70320/322 has a two-channel, on-chip DMA
controller. This allows rapid data transfer between
memory and auxiliary storage devices. The DMA controller supports four modes of operation, two for
memory-to-memory transfers and two for transfers
between I/O and memory.
Memory-to-Memory Transfers. In single-step mode,
the falling edge of DMARQ causes DMA transfer cycles
and CPU bus cycles to alternate as long as DMARQ is
low or until the prescribed number of DMA transfers
has occurred. Interrupts can be accepted while in this
mode. In burst mode, DMA transfer cycles continue
until the DMA terminal counter decrements to zero.
Software can also initiate memory-to-memory transfers.
Transfers Between I/O and Memory. In single-transfer
mode, one DMA transfer occurs after each falling edge
of DMARQ. After the transfer, the bus is returned to the
CPU. In demand release mode, the falling edge of
i5fViARQ enables DMA cycles, which continue as long
as DMARQ is low.
5-16
In all modes, the TC (terminal count) output pin will
pulse low and a DMA completion I/O request will be
generated after the predetermined number of DMA
cycles has been completed. Figure 11 shows the DMA
channel area in memory.
The bottom of internal RAM contains all of the necessary address information for the designated DMA
channels. The DMA channel mnemonics are as follows:
TC
SAR.
SARH
DAR
DARH
Terminal counter
Source address register
Source address register high
Destination address register
Destination address register high
The DMA controller generates physical source addresses by offsetting SARH 12 bits to the left and then
adding the SAR The same procedure is also used to
generate physical destination addresses. You can program the controller to increment or decrement source
and/or destination addresses independently during
DMA transfers.
Parallel Ports
The pPD70320/322 has three 8-bit parallel I/O ports:
PO, P1, and P2. SFR locations·can access these ports.
The port lines are individually programmable as inputs
or outputs. Many of the port lines have dual functions
as port or control lines.
The analog comparator port (PT) compares each input
line to a reference voltage. The reference voltage is
programmable to be the VREF input or VREF x n/16,
where n 1 to 15.
=
Programmable Wait State Generation
You can generate wait states internally to further
reduce the necessity for external hardware. Insertion
of these wait states allows direct interface to devices
whose access times cannot meet the CPU read/write
timing requirements.
When using this function, the entire 1M-byte memory
address space is divided into 128K-blocks. Each block,
with the exception of the uppermost block, can be
programmed for zero, one, or two wait states, or for
external control (READY signal). The appropriate bits
in the wait control word (WTC) control wait state
generation. Programming the bits corresponding to
the top 128K-byte block of memory, will actually set the
wait state conditions for the entire I/O address space.
Figure 12 shows the memory map for programmable
wait state generation.
NEe
Figure 10.
pPD70320/322 (V25)
Serial Interface Block Diagram
CHO
TxDO
Baud Rate
Generator
RxDO
SCKO
CTSO
CH1
TxD1
Baud Rate
Generator
RxD1
CTS1
49-0013498
Figure 11.
Figure 12.
DMA Channels
TC1
SARH1
I
DARH1
Programmable Wait State Generation
FFFFFH
Cannot set
EOOOOH
128K
DAR1
COOOOH
SARHO
SAR1
Channel 1
TCO
Channel 0
I
l..
I"
40000H~
DARHO
20000H
128K
OH
128K
DARO
SARO
XXEOOH
1--16 B i t S - l
49-001351A
49-001350A
5-17
NEe
pPD70320/322 (V25 )
Low-Power Standby
Special Function Registers
There are two low-power standby modes: HALT and
STOP. Software causes the processor to enter either
mode.
Table 4 shows the special function register mnemonic,
type, address, reset value, and function. Figures 13
through 32 show the register formats.
HALT Mode. In the HALT mode, the processor is
inactive and the chip consumes much less power than
when operational. The external oscillator remains
functional and all peripherals are active. Internal status
and output port line conditions are maintained. Any
unmasked interrupt or 1/0 request can release this
mode. In the EI state, I/O requests subsequently will be
processed as vectored interrupts. In the DI state,
program execution is restarted with the instruction
following the HALT instruction.
STOP Mode. The STOP mode allows the largest power
reduction while maintaining RAM. The oscillator is
stopped, halting all internal peripherals. All internal
status is maintained. Only a reset or NMI can release
this mode.
A standby flag in the SFR area is set by rises in the
supply voltage. The flag is reset when its status is read.
Its status is maintained during normal operation and
standby. Use the standby flag to determine whether
program execution is returning from standby orfrom a
cold start.
5-18
Table 4.
Special Function Registers
Name
Byte/
Word Address
PO
B
xxFOOH
PMO
B
xxF01H
FFH
Port mode 0
PMCO
B
xxF02H
OOH
Port mode control 0
P1
B
xx F08H
PM1
B
xxF09H
FFH
Port mode 1
PMC1
B
xxFOAH
OOH
Port mode control 1
P2
B
xxF10H
PM2
B
xxF11H
FFH
PMC2
B
xxF12H
OOH
PT
B
xxF38H
PMT
Reset
Value
Function
Port 0
Port 1
Port 2
Port mode 2
Port mode control 2
Port T
B
xxF3BH
OOH
Port mode T
INTM
B
xxF40H
OOH
Interrupt mode
EMSO
B
xxF44H
External interrupt macro
service 0
EMS1
B
xxF45H
External interrupt macro
service 1
EMS2
B
xxF46H
External interrupt macro
service 2
EXICO
B
xxF4CH
47H
External 110 request
control 0
EXIC1
B
xxF4DH
47H
External 1/0 request
control 1
EXIC2
B
xxF4EH
47H
External 1/0 request
control 2
NEe
Table 4.
Special Function Registers (cont)
Function
Name
Byte/
Word
Address
xxF60H
Receive buffer 0
MDOL
B
xxF82H
Modulo register 0 low
B
xxF62H
Transfer buffer 0
MDOH
B
xxF83H
Modulo register 0 high
B
xxF65H
Serial receive macro
service 0
TM1
W
xxF88H
Timer register 1
TM1L
B
xxF88H
Timer register 1 low
Serial transmit macro
service 1
TM1H
B
xxF89H
Timer register 1 high
MD1
W
xxF8AH
Modulo register 1
MD1L
B
xxF8AH
Modulo register 1 low
MD1H
B
xxF8BH
TMCO
B
xxF90H
OOH
OOH
Name
Byte/
Word
Mdress
RXBO
B
TXBO
SRMSO
STMS1
pPD70320/322 (V25)
B
Reset
Value
xxF66H
SCMO
B
xxF68H
OOH
Serial communication
mode 0
SCCO
B
xxF69H
OOH
Serial communication
control 0
Reset
Value
Function
Modulo register 1 high
Timer control 0
BRGO
B
xxF6AH
OOH
Baud rate generator 0
TMC1
B
xxF91H
SCEO
B
xxF6BH
OOH
Serial communication
error 0
TMMSO
B
xxF94H
Timer macro service 0
SEICO
B
xxF6CH
47H
Serial error 1/0 request
control 0
TMMS1
B
xxF95H
Timer macro service 1
TMMS2
B
xxF96H
SRICO
B
xxF6DH
47H
Serial receive 110 request
control 0
TMICO
B
xxF9CH
47H
Timer 110 request control 0
TMIC1
B
xxF9DH
47H
Timer 1/0 request control 1
STICO
B
xxF6EH
47H
Serial transmit 110 request
control 0
TMIC2
B
xxF9EH
47H
Timer 1/0 request control 2
DMACO
B
xxFAOH
DMAMO B
xxFA1H
OOH
DMA mode 0
OMAC1
B
xxFA2H
OMAM1
B
xxFA3H
OOH
OMA mode 1
RXB1
B
xxF70H
Receive buffer 1
Timer control 1
Timer macro service 2
DMA control 0
TXB1
B
xxF72H
Transmit buffer 1
SRMS1
B
xxF75H
Serial receive macro
service 1
STMS1
B
xxF76H
Serial transmit macro
service 1
DlCO
B
xxFACH
47H
DMA 110 request control 0
SCM1
B
xxF78H
OOH
Serial communication
mode 1
DlCI
B
xxFADH
47H
OMA 110 request control 1
RFM
B
xxFE1H
10H
Refresh mode
SCC1
B
xxF79H
OOH
Serial communication
control 1
TBIC
B
xxFECH
47H
Time base 1/0 request
control
BRG1
B
xxF7AH
OOH
Baud rate generator
register 1
WTC
W
xxFE8H
FFH
Wait control
WTCL
B
xxFE8H
FFH
Wait control low
WTCH
B
xxFE9H
FFH
Wait control high
Flag register
DMA control 1
SCE1
B
xxF7BH
OOH
Serial communication
error 0
SEIC1
B
xxF7CH
47H
Serial error 1/0 request
control 1
PSWL
B
xxFEAH
OOH
PRC
B
xxFEBH
4EH
SB
B
xxFEOH
IDB
B
FFFFFH
SRIC1
B
xxF70H
47H
Serial receive 110 request
control 1
STlC1
B
xxF7EH
47H
Serial transmit 110 request
control 1
TMO
W
xxF80H
Timer register 0
TMOL
B
xxF80H
Timer register 0 low
TMOH
B
xxF81H
Timer register 0 high
MOO
W
xxF82H
Modulo register 0
Processor control
Standby control
FFH
Internal data area base
5-19
IJ
NEe
pPD70320/322 (V25)
Figure 13.
Port Mode Registers 0, 1, and 2.
Output Port Mode
Input ,Port Mode
49·0013778
Figure 14.
Port Mode Control 0 Register
Port Mode
c!>Out
49·0013788
Figure 15.
Port Mode Control 1 Register
I
CP17
1
CP16
I
CP1s
1
CP14
I
CP13
I
CP12
I
CP11
I
CP10
L
X
NMllnput
X
INTEO/P11 Input
X
INTElIP12 Input
0
INTE2/P13 Input
1
INTA
Port/Control Bit Selection
0
P141/0/Polllnput
1
INTRlnpU1
0
P1sl/O
1
TO Output
0
P161/O
1
SCKOOutput
0
P17110
1
Ready InpU1
49·0013798
5-20
NEe
Figure 16.
pPD70320/322 (V25)
Port Mode Control 2 Register
I
CP27
I
CP26
I
CP2s
I
CP24
1
CP23
1
CP22
1
CP21
I
CP20
I
Port/Control Bit Selection
0
110 Port
1
DRQOlnput
0
1/0 Port
1
DACKO Output
0
1/0 Port
1
TCOOutput
0
1/0 Port
1
DRQllnput
0
1/0 Port
1
DACKl Output
0
1/0 Port
1
TCOOutput
0
1/0 Port
1
Hold Input
0
1/0 Port
1
HLDAOutput
49-0013808
Figure 17.
Port Mode T Register
I
0
I
0
I
0
I
0
1
MPT3
I
1
MPT2
1
MPTl
1
MPTo
I
Comparator Port Threshold Selection
'0/,.
0
0
0
0
VTHX
0
0
0
1
VTHxV,.
VTHxo/,.
0
0
1
0
0
0
1
1
VTHX'lI,.
0
1
0
0
VTHXo/,.
VTHXo/'.
0
1
0
1
0
1
1
0
VTHX'V'.
0
1
1
1
VTH X 7/,.
1
0
0
0
VTHX'V'.
1
0
0
1
VTHlIo/'·
1
0
1
0
VTH X '0/,.
1
0
1
1
VTH X
1
1
0
0
VTHX''II,.
1
1
0
1
VTHX ''Y,.
1
1
1
0
VTHx'o/,.
1
1
1
1
VTHx''1,.
'V,.
49-0013818
5-21
NEe
pPD70320/322 (V25)
Figure 18.
Interrupt Mode Register
INTM:
I I I I I I I 1
0
0
ES2
0
ESl
ES
NMI
0
ESO
I
Trigger Mode
0
Failing Edge
1
Rising Edge
0
Failing Edge
1
Rising or Falling Edge
0
Falling Edge
1
Rising or Falling Edge
0
Falling Edge
1
Rising Edge
49·00'3828
Figure 19.
I/O Request Control Registers
I I I I I I I I
MSI
xxlCn:
FLAG
iNT
MASK
0
ENCS
PR2
PRl
PRo
PR
2 1 0
Priority
o 0 0
Highest
111
Lowest
ENCS
Context Switch
0
Disable
1
Enable
MS/INT
Macro Service or Interrupt
Interrupt
0
1
Macro Service
xxMKn
Interrupt Mask
0
Mask Open: Interrupts Enabled
1
Mask Closed: Interrupts Disabled
xxFn
Interrupt Request Flag
0
No Request
1
Interrupt Requested
49·00'3838
Figure 20.
Macro Service Control Registers
xxMSn:
I
MSM2
I
MSMl
I
MSMO
I
DIR
I
0
I
CH2
I
CHl
I
CHo
2 1 0
Macro Service Channel
o
0
0
Channel 0
1 1
1
Channel 7
Transfer Direction
0
From Memory to SFR
1
From SFR to Memory
Transfer Mode
0 0 0
0 0 1
1 00[1]
8·bit Transfer
16·bit Transfer
8-blt Transfer with Character Search
Note: (1] All other combinations are reserved
49·00'3848
5-22
NEe
Figure 21.
pPD70320/322 (V25)
Serial Communication Mode Register
SCM:
I
I
TxRDY
RxE
I
PEN
EP
L-,..---I
I
I
CL
I
SL
I
MOl
MOO
L·~·oo
Mode
o
o
0
1
Asynchronous
1
X
Reserved
1
1 Stop Bit
2
2 Stop Bits
0
7 Bits
1
BBlts
1/0 Interface
Stop Bit Control
Character Length
PEN EP
Parity Control
0
X
1
0
Even Parity
1
1
Odd Parity
0
Disable
1
Enable
0
Disable
1
Enable
Disable Parity
Receiver Control
Transmitter Control
Figure 22.
Serial Communication Error Registers
l
RXD
I
0
I
0
I
0
I
0
I
ERP
I
ERF
I
ERO
L
Overrun Error Flag
1 1 Overrun has occurred
o1
Overrun has not occurred
Framing Error
1 1 Framing error has occurred
o1
Framing error has not occurred
Parity Error
1
I
o1
Parity error has occurred
No parity error has occurred
RxD Line Status
11 RxDLine=l
o1
RxDLine = 0
49-001386A
5-23
NEe
pPD70320/322 (V25)
Figure 23.
I
Timer Control 0 Register
TSO
I
TCKLO
I
MSO
1 MCCK 1
ENTO
I
ALV
I
MOD1
I
MODO
L·:~
MODO
1
Timer Mode
0
Interval Timer Mode
1
One-shot Timer Mode
X
Reserved
Active Level of TOUT
0
1
TOUT inltiallellel
I
TOUT Initial level
=0
=1
Enable Timer Out
1
I
I
0
I
SCLK/12
1
f
SCLK/128
0
Disable Timer Out
Enable Timer Out
One-shot Mode Modulus Register Clock
Modulus Start (One-shot Mode)
Stop Modulus Register Count
0
1
I
Start Modulus Register Count
TM Register Clock Select
MOD1
MODO
TCLK
0
0
0
SCLK/61ntervai Timer Mode
0
0
1
SCLK/128
0
1
0
SCLK/12 One-shot Mode
0
1
1
SCLK/128
Timer Start Bit
0
1
I
StopTimer
Start Timer
49-0013878
Figure 24.
Serial Communication Control Register
SCC:
1
0
J
0
J
0
1
0
.1
PRS3
1 PRS2
PRS1
I
PRSo
PRS
321 0
Note: [1] All other combinations after 1000 are illegal
Input clock for baud
rate generator
0000
SCLK
0001
SCLK/2
0010
SCLK/4
001 1
SCLK/8
01 00
SCLK/16
0101
SCLK/32
01 1 0
SCLK/64
01 1 1
SCLK/128
1 000
SCLK/256[1]
49-0013888
5-24
NEe
Figure 25.
pPD70320/322 (V25)
Timer Control 1 Register
I
TSI
I
TCLKI
I
I
0
I
0
I
0
I
0
I
0
0
1
TMI Clock Select
oI
SCLK/6
1
SCLK/128
I
Timer Start Bit
oI
Stop TMI counting
I
Start TMI counting
1
49-001389B
Figure 26.
I
DMA Mode Registers
MD2
I
I
MOl
I
MOo
I
I
W
lEOMA
I
TDMA
I
I
0
0
I
TriggerDMA
oI
1
No Effect
I Trigger DMA
EnabieDMA
oI
Disable DMA
1
I Enable DMA
X
I
Word/byte
No Effect
DMAMode
MD2
MOl
MOo
0
0
0
Single Step (Mem to Mem)
0
0'
1
Demand Release (I/O to Mem)
0
1
0
Demand Release (Mem to I/O)
0
1
1
Reserved
1
0
0
Burst Mode (Mem to Mem)
1
0
1
Single Transfer (I/O to Mem)
1
1
0
Single Transfer (Mem to I/O)
1
1
1
Reserved
49-001390B
Figure 27.
DMA Control Register
I
0
I
0
I
POI
PDO
L,-J
I
0
I
0
I
PSI
I
L
PSO
PSI
"'"=""""~,,,~,,""".,_'Co""'"
PSO
0
0
Source Address not
Incremented/Decremented
0
1
Increment Source Address ( + 1)
1
0
Decrement Source Address ( -1)
1
1
Source Address not
Incremented/Decremented
!
i
i
I
Destination Address Increment/Decrement Control
POI
PD~
0
0
Destination Address not
Incremented/Decremented
0
1
Increment Destination
Address ( + 1)
1
0
Decrement Destination
Address (-1)
1
1
Destination Address not
Incremented/Decremented
49-0013918
5-25
NEe
pPD70320/322 (V25)
Figure 28.
Refresh Mode Register
I
RELV
I
HLDRF
I
HLTRF
L
RFEN
J
RWl
RWO
L-r--1
I
RFTl
RFTO
Refresh Cycle Speed
RFTl
RFTO
Refresh
0
0
16/SCLK
~
0
1
32/SCLK
1
0
64/SCLK
1
128/SCLK
1
Refresh Cycle Wait States
RWl
RWO
0
0
Number Of Walt States
0
0
1
1
1
0
2
1
1
2
Refresh Enable
--
0
Refresh Pin - RFLV
1
Refresh Enabled
Halt Refresh Enable
0
1
1 No Effect
.1 Refresh During CPU HALT
Hold Refresh Enable
1 Hold Refresh Disabled
1 Refresh During Hold
0
1
Refresh level output
to RFSH pin when RFEN = 0
49-001392B
Figure 29.
Time Base 110 Request Control Register
I
TBF
1
TBMK
J
0
I
1
0
1
0
1
1
I
1
I
1
Time Base Interrupt Mask Bit
o 1 Unmasked
1
1 Masked
Time Base Interrupt Flag
o 1 No Interrupt Generated
1
I
Interrupt Generated
49-001393B
Figure 30.
Walt Control Register
Walt Control low
100
101
BLK61
I
4
BLK60
I
BLK51
BLK50
BLK40
BLK41
Wait Control High
I
BlK31
I
BlK30
1
BLK21
I
BlK20
I
I
BlKll
1
BLK10
1
BlKOl
.I
BlKOO
BlKnl
BlKnO
0
0
Mode
0
1
1 Wait
1
0
2 Wait
1
1
External Ready Control
No Walts
49-001394B
5-26
NEe
Figure 31.
pPD70320/322 (V25)
Processor Control Register
I
0
I
RAMEN
I
0
I
0
I
TB1
TBO
L-....--J
I
PLK1
I
PLKO
L--
System Clock Select
PLK1
PLKO
0
0
losc
0
1
losc/2
1
0
losc/4
1
1
Reserved
Time Base Interrupt Period
TB1
TBO
0
0
SCLK/2'O
0
1
SCLK/2"
1
0
SCLK/2 '6
1
1
SCLK/2 20
Internal RAM Enable
0
Disabled
1
Enabled
49-0013958
Figure 32.
Standby Register
Standby Flag
No changes in supply voltage (standby)
Rising edge on supply voltage (cold start)
49-0013968
5-27
t-IEC
pPD70320/322 (V25)
Timing Waveforms
Memory Read Cycle
Memory Write Cycle
RD/iNA
RD/WR
00- 0 7 -~~--+---+---+---~-
Do-Dr
--44-49-001353A
49-001352A
5-28
NEe
LCD PERIPHERALS
6-1
E
NEe
LCD PERIPHERALS
Section 6 - LCD Peripherals
J,lPD6307
J,lPD6308
J,lPD7225
J,lPD7227
J,lPD7228
J,lPD72030
6-2
LCD Row Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
LCD Column Driver ........................................ 6-7
CMOS, Intelligent, Alphanumeric LCD Controller/Driver ..... 6-11
CMOS, Intelligent, Dot-Matrix LCD Controller/Driver ........ 6-21
CMOS, Intelligent, Dot-Matrix LCD Controller/Driver ........ 6-29
CMOS, Intelligent, LCD Controller ......................... 6-39
NEe
NEe Electronics Inc.
",PD6307
LCD ROW DRIVER
Description
Pin Configuration
The I-lPD6307 can directly drive any multiplexed LCD
organized with up to 32 rows. It is easily cascaded to
128 rows.
Features
D High voltage output 21 V maximum
D Directly controllable by the I-lPD72030
D CMOS technology
D Single 5 V ± 10% power supply
Ordering Information
Part Number
Package Type
pPD6307G-F
54-pin plastic miniflat
pPD6307G-R
54-pin plastic miniflat (inverted leads)
('1').
titE
U')U)"'"OOQc:nO
....
NM
....
U')
rirEri«~ri,;~2rr~cr
83·003161A
Pin Identification
No.
Symbol
Function
1-19,
21-23
Ro-R31
Row drive output
20
Vcc
SBY
Positive power supply
34
35
FRM
Frame input
36
STB
Strobe input
37
RST
Reset input
38
EDT
End of transfer input
39
lOW
lID write input
Standby input
40, 41
RSo, RS1
Row select input
42-44
VLC1, VLC4, VLC5
LCD drive supply
45
Vss
Ground
46
VCC (= VLCO)
Positive power supply and
LCD drive supply
47-54
CSrCSo
Chip select output
I
6-3
NEe
J.lPD6307
Pin Functions
lOW (1/0 Write)
Ro·R31 (Row Drive Output)
This input increments the CScounter signal following 10 low level lOW pulses.
LCD row drive output.
EOT (End of Transfer)
CSO·CS7 (Chip Select)
Column driver chip select. These outputs are
generated by the CS counter and RSo-RS1.
This input clears the CS counter when it goes active
low.
RST (Reset)
VLC1, VLC4, VLC5 (LCD Drive Supply)
This is the row driver reset input. A low input clears
the internal counter and row outputs Ro-R31, and sets
the CSO-CS7 outputs to a high level.
Reference voltages used to drive Ro-R31.
RSO, RS1 (Row Select)
This input selects the row driver cascade connection.
It enables expansion to 128 row drive outputs and 32
CS outputs, as shown in table 1.
FRM (Frame)
A high level input to this pin displays a positive frame
and a low level input displays a negative frame. At the
falling or rising edge of the signal, the row counter
is cleared and the row driver is started· from Ro.
STB (Strobe)
Row drive strobe input. One STB pulse input at the
timing interval causes the display of the next row.
SBY (Standby)
This is the standby input. A low level input to this pin
sets the row outputs Ro-R31 to VLCO. Before entering
standby mode, set all column driver display data to
high level.
VCC (= VLCO) (Power Supply and LCD Drive
Supply)
Connect the 5 V power supply between Vcc and Vss
for logic circuit operation. This pin is also used for
the row drive voltage output.
Vss (Ground)
Ground.
Block Diagram
VCC(=VLCO)
VI"
v,,,
,-V_LC_5_ _- . Voltage Control and
Output Driver
To Logic
Circuit
Row Clear
+ /-
83-003162B
6-4
NEe
J.tPD6307
Table 1. RSo and RS1 Row Cascading
Functional Description
RSo
HSl
How Signal
Chip Select
0
0
Ro-R31
CSO-CS7
This circuit controls the timing for each internal block.
FRM, RSo, RS 1, RST, and SBY are sampled at the
leading edge of STB, and then supplied to other internal circuits.
0
1
R32- R63
R64- R95
CSa-CS15
R96- R127
CS24-CS31
Row Counter Decoder/Select Circuit
Table 2. Row Select Logic
Timing Control Circuit
As shown in figure 1, this circuit consists of a 7-bit
counter, a comparator, and a 5 to 32 decoder. The 7-bit
counter can accommodate 128 rows. The comparator
acts to clear Ro-R31 if the upper two bits of the
counter do not match RSo and RS1. If they match, one
of Ro-R31, indicated by the lower five bits of the row
counter, is selected and the rest are cleared. RSo and
RS1 allow for cascading as shown in table 1. Table 2
shows the row select logic.
Figure 1.
Row Counter Decoder/Select Circuit
To Voltage Control, Driver Circuit
0
EN
0
C
0
0
0
0
0
B
CS16-CS23
Selected
Row Signal
A
0
Ro
0
R1
+
Rn
R30
1
X
X
X
1
1
X
X
R31
None
Voltage Control Driver Circuit
This circuit generates the row signals for AC drive of
the LCD panel. A low level RST clears the output. A
low level SBY sets the output VLCO. Table 2 shows the
Ro-R31 output levels.
Table 2. Ro·R31 Outputs Levels
Function
+ (FRM = 1)
- (FRM
= 0)
Select
RST--------,r~+-~--~
Clear
Chip Select Counter/Decoder Circuit
Row Counter Count·Up-------t>·
Row Counter Clear-------J
RSo' . - - - - - - - - - - - - - - - - - - - - - - - - '
RS1' . - - - - - - - - - - - - - - - - - - - - - - - - - '
• RSo', RS1', and RST are obtained by synchronizing RSo, RSh RST with STB.
83-003163A
This circuit, shown in figure 2, generates the column
driver CS signal. This circuit has a 5-bit counter to
generate up to 32 CS signals. The 5-bit counter is incremented once for every 10 lOW (active low) pulses.
If the upper two bits of the chip select counter do not
match RSo and RS1, all the CSO-CS7 outputs are set
to high level. If they match, one of CSO-CS7 (indicated
by the lower three bits of the chip select counter) goes
low. If RST is low, CSO-CS7 become high level. Table
3 shows the chip select logic.
6-5
NEe
~PD6307
Figure 2.
Chip Select Counter/Decoder Circuit
Table 3. Chip Select Logic
EN
c
b
8
Chip Select
0
0
0
0
0
0
0
1
0
1
CSa
CS1
CS2
CS3
CS4
CS5
CSs
CS7
X
Disabled
0
0
0
RST'
0
lOW'
EOT'
RSo'
RS1'
83·003164A
6-6
X
X
0
NEe
NEe Electronics Inc.
J.lPD6308
LCD COLUMN DRIVER
PRELIMINARY INFORMATION
Description
Pin Configuration
The J,lPD6308 can directly drive any multiplexed dotmatrix LCD organized with up to 40 columns. It is
easily cascaded to fit the user's system.
54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
Features
o
o
o
o
C3B
o
High voltage output 21 V maximum
Directly controllable by the J,lPD72030
CMOS technology
Single 5 V ± 10% power supply
I'PD6308
Ordering Information
Part Number
Package Type
J.lPD6308G-F
54-pin plastic miniflat
J.lPD6308G-R
54-pin plastic miniflat (inverted leads)
83·003165A
Pin Identification
Symbol
Function
1-19.
21-41
CO-C39
Column drive output
No.
20
Vcc
Positive power supply
42-44
VLC2. VLC3.
VLC5
LCD drive supply
45
Vss
Ground
46
Positive power supply and
LCD drive supply
47
VCC
(=VLCO
CS
Chip select output
48
STB
Strobe input
49
FRM
Frame input
50
lOW
1/0 write input
51-54
D3- DO
Data input
~
6-7
NEe
J.lPD6308
Pin Functions
CO·C39 (Column Drive Output)
LCD column drive output.
VLC2, VLC3, VLC5 (LCD Drive Supply)
Reference voltages used to drive CO-C39'
00.03 (Data Input)
This is the display data bus. Data in the 40-bit input
latch is written via this bus four bits at a time, a total
of 10 times.
Block Diagram
Vcc
= (VLCO)
Vss
VLc2
VLC5
40
I
Voltage Control and
Output Driver
FRM (Frame)
A high level input to this pin displays the positive
frame and a low level input displays the negative
frame.
STB (Strobe)
This is the column driver strobe input. At the leading
edge of the STS input, the 40-bit display data in the
input latch is transferred to the output latch to appear
in the column drive output.
83·0031668
lOW (I/O Write)
Functional Deacription
This is the data write input. If CS is active and lOW
goes low, data on 00-03 is written to the input latch.
Timing Control Circuit
CS (Chip Select)
This circuit controls the timing that operates each
IlPD6308 internal block.
This input pin is connected to the chip select output
of the row driver as the lOW enable. CS is active low.
Voltage Control Driver Circuit
VCC (= VLCO) (Power Supply and LCD
Drive Supply)
This circuit generates the column signals for AC drive
of the LCD panel. Table 1 lists CO-C39 output levels.
FRM' is obtained by internally synchronizing the FRM
signal with the leading edge of the STS signal.
Connect the 5 V power supply between Vee and Vss.
Vee is also used for the column drive voltage.
Table 1. Co' C39 Output Levels
Vss (Ground)
Function
Ground.
Select (Data = 1)
+ (FRM'
= 1)
- (FRM' =0)
Clears (Data = 0)
Column Data Counter/Decoder Circuit
The column data counter/decoder circuit is shown in
figure 1. This decimal circuit generates latch enable
pulses to the input latches, which latch 40 bits of data
(four bits at a time, a total of 10 times). The number
of decoder outputs can be increased by cascading
IlPD6308s under the control of CS. The counter value
increments at the leading edge of lOW, and clears
when CS goes high.
6-8
NEe
Figure 1.
J..tPD6308
Internal Block Diagram
C4
Cs
Cs
C7
•
•
•
•
•
•
C3S C37 C3B C39
STB
'---+--+--+-+----4>-- '-------+--+-~--- '--------+~---- '-----+--+--+-~--
-
-
- - - - - - - - -
4--
Output Latch
4--
Input Latch
-+--1.--11--+---4---- Do
-+--I.--1I--~--D1
-+--1----<>----- 02
-+----4-----03
To
To
To
Latch 3 Latch 5 Latch 7
cs - __-+-----'-'-'-"'--+1
lOW
-------+1
_
Column Data Decoder
_
Column Data Counter
83·0031678
Input Latch Circuit
Output Latch Circuit
The input latch circuit is shown in figure 1. The input
latches display data four bits at a time until 40 bits
are latched and displayed. When CS is active low,
each lOW active low pulse input to the decimal
counter causes 1 of 10 latch enable signals to be
generated from the column data decoder. Latches 0
to 9 are enabled consecutively to load data 00-03 until 40 bits are latched.
The output latch circuit is shown in figure 1. The 40
bits output from the input latch circuit are transferred
to the output latch circuit at the leading edge of the
STB signal and appear on the column drive outputs.
Note that Do is output to C3, D1 to C2, 02, to C1, and
D3 to Co.
6-9
",PD8308
6-10
NEe
NEe
NEe Electronics Inc.
pPD7225
CMOS, INTELLIGENT, ALPHANUMERIC
LCD CONTROLLER/DRIVER
Description
Pin Configuration
The !-,PD7225 is an intelligent peripheral device designed to interface most microprocessors with a wide
variety of alphanumeric LCDs. It can directly drive any
static or multiplexed LCD containing up to 4 backplanes
and up to 32 segments and is easily cascaded for larger
LCD applications. The !-,PD7225 communicates with a
host microprocessor through an 8-bit serial interface. It
includes a 7-segment numeric and a 14-segmentalphanumeric segment decoder to reduce system software
requirements. The !-,PD7225 is manufactured with a low
power consumption CMOS process allowing use of a
single power supply between 2.7 V and 5.5 V. Itis available in a space-saving 52-pin plastic flat package.
Features
o
o
o
o
o
o
o
o
o
o
o
Single chip LCD controller with direct LCD drive
Low cost serial interface to most microprocessors
Compatible with
- 7-segment numeric LCD configurations
up to 16 digits
- 14-segment alphanumeric LCD configurations
up to 8 characters
Selectable LCD drive configuration:
- Static, biplexed, triplexed, or quadruplexed
32-segment drivers
Cascadable for larger LCD applications
Selectable LCD bias voltage configuration:
- Static, 1/2 or 1/3
Hardware logic blocks reduce system software
requirements
- 8-bit serial interface
- Two 32 x 4-bit static RAMs for display data and
blinking data storage
- Programmable segment decoding capability:
-16-character, 7-segment numeric decoder
- 64-character, 14-segment USASCII
alphanumeric decoder
- Programmable segment blinking capability
- Automatic synchronization of segment drivers
with sequentially multiplexed backplane
drivers
Single power supply, variable from 2.7 V to 5.5 V
Low power consumption CMOS technology
Extended - 40°C to +85°C temperature range
available
83·002798A
Pin Identification
No.
Symbol
Function
1
CL2
System clock output
2
SYNC
Synchronization port
3-5
VLCD1VLCD3
LCD bias voltage supply inputs
Vss
Ground
7,33
VDD
Power
8
SCK
Serial clock input
9
SI
Serial input
10
CS
Chip select
11
BUSY
Busy output
12
C/O
Command or data select input
13
RESET
Reset input
14
NC
No connection
15-18
COMo-COM3
LCD backplane driver outputs
19-32, 34-51
SO-S31
LCD segment driver outputs
52
CL1
System clock input
Ordering Information
Part Number
Package Type
Max Frequency
of Operation
pP07225G-00
52-pin plastic miniflat
1 MHz
6-11
NEe
J..tPD7225
Pin Functions
CS
COMO-COM3
Chip select input. Enables the JAPD7225 for data input
from the microprocessor. When CS is deselected, the
display can be updated.
.
LCD backplane driver outputs.
SO-S31
SYNC
LCD segment driver outputs.
Synchronization port. For multichip operation, tie all
SYNC lines together.
VLCD1- V LCD3
LCD bias voltage supply inputs to the LCD voltage controller. Apply appropriate voltages from a voltage ladder
connected across Voo.
CL1
SI
CL2
Serial input from the microprocessor.
System clock output. Connect CL2 to CL1 with a 180 kQ
resistor, or leave open.
SCK
Serial clock input. Synchronizes 8-bit serial data transfer from the microprocessor to the JAPD7225.
BUSY
Handshake output indicates the JAPD7225 is ready to receive the next data byte.
c/o
Command/data select input. Distinguishes serially input data byte as a command or as display data.
6-12
System cJock input. Connect CL1 either to CL2 with a
180 kQ resistor, or to an e.xternal clock source.
RESET
Reset input. R/C circuit or pulse initializes theJAPD7225
after power-up.
VDD
Power supply positive. Apply single voltage ranging
from 2.7 to 5.5 V for proper operation.
Vss
Ground.
NEe
J-lPD7225
Block Diagram
COMo-COM3
LCD Driver
32
Display Latch
32
VDD
VLCD1
VLCD2
VLCD3
LCD
Voltage
Controller
32x4Bit
Display RAM
Segment
Decoder
Data
Pointer
32x4Bit
Blinking RAM
VSS
CL1
CL2
~L - - _
Clock
Oscillator
RESET
Buffer
Interface
Controller
Command
Decoder
Serial Interface
SI
SCK
83-003379B
6-13
NEe
J.lPD7225
DC Characteristics (cont)
Absolute Maximum Ratings
TA = - ooe to + 7o oe, Voo = +2.7V to 5:5 V
TA=25°e
Limits
-0.3Vto +7V
Power supply voltage, Voo
Input voltage, VI
-0.3VtoVoo +0.3V
Parameter
Output voltage, Vo
-0.3VtoVoo +0.3V
Input voltage
low
-10°C to +70°C
Operating temperature, TOPT
- 65°6 to +150°C
Storage temperature, TSTG
Comment: Exposing the device to stresses above those listed in Abso·
lute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits de·
scribed in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
gevice reliability.
DC Characteristics
TA= -10 0 eto +70 0 e,Voo= +5V±10%
Limits
Parameter
Symbol
Input voltage
low
VIL
Input voltage
high
VIH
Output voltage
low
Typ
0
0.7 Voo
Max
Unit
0. 3V oo
V
Voo
Test
Conditions
V
VOL1
0.5
V
BUSY, 10L =100J.lA
VOL2
1.0
V
10L =900J.lA,
Output voltage
high
VOH
Input leakage
current low
ILiL
Input leakage
current high
ILiH
Output leakage
current
ILOL
Output short
circuit current
los
Backplane
driver output
impedance
ReOM
Segment
driver output
impedance
RSEG
Supply current
Min
~
Voo
-0.5
-2
-2
ILOH
-300
V
BUSY, SYNC,
10H= -1OJ.lA
J.lA
VIL =OV
J.lA
VIH=VOO
J.lA
VOL =OV
J.lA
VOH=VOO
J.lA
SYNC, VOs=1.0V
kQ
COMO-COM3,
Voo~VLeo
(Note 1)
14
kQ
SO-S31,
Voo~VLeo
(Note 1)
100
100
250
J.lA
CL1external clock,
f+=200kHz
Note:
(1) Applies to static-, 1/2-, and 1/3-LCO bias voltage schemes.
Input voltage
high
Symbol
Min
Typ
Unit
Test
Conditions
VIL1
0
0. 3V oo
V
Except SCK
VIL2
0
0. 2V oo
V
SCK
VIH1
O.7Voo
Voo
V
Except SCK
VIH2
0. 8V oo
Voo
V
SCK
BUSY, 10L =100J.lA
Output voltage
low
VOL1
0.5
V
VOL2
0.5
.V
10L =400 ptA,
SYNC
Output voltage
high
VOH
V
BUSY, SYNC,
10H= -7J.1A
Input leakage
current low
ILiL
J.lA
VIL =OV
Input leakage
current high
ILiH
J.lA
VIH=VOO
Output leakage
current
ILOL
J.lA
VOL=OV
J.lA
VOH=VOO
Output short
circuit current
los
J.lA
SYNC, Vos=0.5V
Backplane
driver output
impedance
ReOM
Segment
driver output
impedance
RSEG
Supply current
100
Voo
-0.75
-2
-2
ILOH
-200
kQ
COMo-COM3,
Voo~VLeo
(Note 1)
kQ
12
SO-S31,
Voo~VLeo
(Note 1)
30
100
~
CL1external clock,
Voo=3.0V ±10%,
fcp=140 kHz
Note:
(1) Applies to static·, 1/2-, and 1/3-LCO bias voltage schemes.
Capacitance
TA=25°C, f,=1MHz
Limits
Parameter
Symbol
Min
Typ
Max
Unit
Test
Conditions(1)
Input
capacitance
CI
10
pF
Output
capacitance
C01
20
pF
CO2
15
pF
BUSY
1/0
capacitance
CIO
15
pF
SYNC
Clock
capacitance
Ccp
30
pF
CL1 input
Note:
(1) All unmeasured pins returned to 0 V.
6-14
Max
Except BUSY
NEe
J..tPD7225
AC Characteristics
TA= -100Cto +70°C,VDD= +5V±10%
Limits
Symbol
Parameter
Clock Irequency I.
lose
Min
Typ
50
85
130
rest
Conditions
Mal
Unit
200
kHz
175
kHz
R=180kQ+5%
16
J.ls
CU, external clock
Clock pulse
width low
t'Wl
Clock pulse
width high·
t'WH
SCK cycle
teYK
900
ns
SCK pulse width tKWl
low
400
ns
SCK pulse width tKWH
high
400
ns
BUSY tto SCK t tBHK
hold time
0
ns
51 setup time to tlSK
100
ns
200
ns
16
J.lS
tlHK
8th SCK t to
BUSY.J. delay
time
tKOB
3
1.5
CS -I-to BUSY.J. teoB
delay time
C/Ds~time
tOSK
9
J.lS
J.ls
CU, external clock
CL =50pF
CL =50 pF
J.ls
tOHK
J.ls
CS hold time
after 8th SCK
teHK
J.lS
t
CS pulse width
low
tewL
CS pulse width
high
tewH
8/1.
8/f.
Min
Typ
50
lose
50
Clock pulse
width low
t+Wl
3
Clock pulse
width high
t'WH
SCK cycle
100
rest
Conditions
Max
Unit
140
kHz
140
kHz
R=180 kQ+5%,
Voo=3.0V ±10%
16
J.lS
CU, external clock
16
J.ls
CL1, external clock
teYK
4
J.ls
SCK pulse width tKWL
low
1.8
J.ls
SCK pulse width tKWH
high
1.8
J.lS
BUSY tto SCK.J. tBHK
hold time
0
ns
SI setup time to tlSK
SCK t
J.lS
SI hold time
after SCK t
tlHK
J.ls
8th SCK t to
BUSY .J. delay
time
tKOB
5
J.ls
Cl=50pF
CS .J. to BUSY .J. teoB
delay time
5
J.ls
CL =50 pF
C/Ds~time
to 8th SCK t
C/i) hold time
after 8th SCK t
Symbol
Clock Irequency I!
SCK t
SI hold time
after SCK t
Limits
Parameter
tOSK
18
J.ls
to 8th SCK t
J.ls
J.ls
C/ D hold time . tOHK
after 8th SCK t
J.ls
CS hold time
after 8th SCK t
teHK
J.ls
CS pulse width
low
tewL
8/f.
J.ls
CS pulse width
high
tewH
8/f.
J.ls
SYNC load
capacitance
Cl
50
pF
I
f.=200kHz
AC Timing Characteristics
All Inputs
All Outputs
\-__________ # ____________
----------
~IH
------------~
"\=======:.===t-=.=-..:::--=-------=--=--=--=--=---~~~L
83-0027998
6-15
NEe
Timing Waveforms
Clock
Cll-----------------------
~
1
11f¢
toWl
~~
t,WH
83-OO2800B
Serial Interface
~--------~~--~-----------tCWL--------------------------~~
tCHK
tCDB
1-+------------------------------------- --------~------~
~--------------------------- - -----J
,- - --,
,---- -'-
~'B", ~I~
,- --,
,_ -
-
-'-----.II
tlHK
Sl----~---------------+_(
I
I
1"""·~-----------tDSK-------------. . .~---tDHK~
c/o
---------..;..,--------....:«"'______________________
----------
>....--_____
83-OO2801B
6-16
NEe
f..lPD7225
Instruction Set (Note 1)
Command
Description
Mode Set
Initialize the J.lPD7225, including selection of:
1) LCD drive configuration
2) LCD bias voltage configuration
3) LCD frame frequency
Operation Code
Hex
Code
D7
D6
Ds
D4
D3
D2
DI
Do
40-5F
a
1
a
d4
d3
d2
d1
do
a
a
a
a
d4
d3
d2
d1
a
a
a
a
a
d3
d2
d1
do
Unsynchronous Data Transfer
Synchronize display RAM data transfer to display latch with CS
30
Synchronous Data Transfer
Synchronize display RAM data transfer to display latch with LCD
drive cycle
31
a
Interrupt Data Transfer
Interrupt display RAM data transfer to display latch
Load Data Pointer
Load data pointer with 5 bits of immediate data
EO-FF
38
Clear Display RAM
Clear the display RAM and reset the data painter
20
a
Write Display RAM
Write 4 bits of immediate data to the display RAM location
addressed by the data pointer; increment data pointer
DO-OF
1
AND Display RAM
Perform a logical AND between the display RAM data addressed by 90-9F
the data pointer and 4 bits of immediate data; write result to same
display RAM location. Increment data pointer
d3
d2
d1
do
OR Display RAM
Perform a logical OR between the display RAM data addressed by
the data pointer and 4 bits of immediate data; write result to same
display RAM location; increment data painter
BO-BF
d3
d2
d1
do
Enable Segment Decoder
Start use of the segment decoder
15
Disable Segment Decoder
Stop use of the segment decoder
14
Enable Display
Turn on the LCD
11
a
a
a
a
a
Disable Display
Turn off the LCD
10
Clear Blinking RAM
Clear the blinking RAM and reset the data painter
00
Write Blinking RAM
Write 4 bits of immediate data to the blinking RAM location
addressed by the data pointer; increment data pointer
CO-CF
AND Blinking RAM
Perform a logical AND between blinking RAM data addressed by
the data painter and 4 bits of immediate data; write result to same
blinking location; increment data pointer
80-8F
OR Blinking RAM
Perform a logical OR between blinking RAM data addressed by the
data pointer and 4 bits of immediate data; write result to same
blinking location; increment data painter
AO-AF
Enable Blinking
Start segment blinking at the frequency specified by 1 bit of
immediate data
1A-1B
Disable Blinking
Stop segment blinking
a
a
a
a
a
a
a
do
a
a
a
a
a
a
a
d3
d2
d1
do
a
d3
d2
d1
do
d3
d2
d1
do
do
18
Note:
(1) Details of operation and application examples can be found in the IJPD7225 Intelligent Alphanumeric LCD ControlierlDriver Technical Manual.
6-17
If
NEe
f..lPD7225
Operating Characteristics
TA =25°C
External Resistance vs Oscillation Frequency
Supply Voltage vs Oscillation Frequency
+-~~-------+----------I~I
~200
CL2R
____._
•••
••••
I-
140
R=l
C
CLL11
..:
f
I~
~
o
50
't..tl----+-----+----~::-------po...,...-...-.---j
100
200
I
500
External Resistance R (kQ)
Supply Voltage vs Supply Current
100
j
c
E
I
/
/'
100
501------1------------~~~------+_--------~
U
ici!
~~~~------~------~----~I
Supply Voltage VOO (V)
6-18
80
V"
~
V
Y
R
~
I
Supply Voltage Voo (V)
I
I
NEe
JAPD7225
7·Segment Numeric Data Decoder Character Set
Decoded Display RAM Data
Display
Byte
(HEX)
00
01
02
03
Character
a
05
Ii
06
a
07
H
08
a
09
Ii
OC
00
n+1
n
n+1
n
0
a
a
B
8
a
OB
Quadruplexed
Display RAM Address
B
04
OA
n+2
Triplexed
Display RAM Address
A
B
a
a
B
a
B
B
Sa
OE
8,
OF
B
~
3
0
a
a
a
A
a
6-19
Cf>
14·Segment Alphanumeric Data Decoder Character Set
o
Display
Byte
(HEX) Char.
f\)
AO
Display RAM
Address
n+3
10
n+2
n+1
n
0
0
0
Display
Byte
(HEX) Char.
BO
A1
Invalid
B1
A2
Invalid
B2
A3
Invalid
B3
A4
Invalid
B4
A5
Invalid
B5
A6
Invalid
B6
A7
A8
A9
AA
AB
~
~o
10
10
Ie
I
0
0
A
0
B7
A
B8
0
B9
0
Invalid
10
AE
AF
0
IJ
[f4[t
n+3
n+2
4
7
0
6
0
0
C1
3
C
4
C2
7
8
4
C3
4
C4
4
C5
4
C6
0
C7
4
C8
4
C9
10
10
10
10
10
rm
lmIo
n+1
CO
6
A
5
0
7
0
10
10
n
A
BA
Invalid
CA
BB
Invalid
CB
0
Invalid
10
BC
4
BO
BE
BF
10
~
[Do
4
0
0
It
Invalid
,.a
1::
Display
Byte
(HEX) Char.
v(.;
AC
AD
0
00
Display RAM
Address
10
10
10
10
10
10
10
10
10
10
10
10
~
CC
lEL
~c
8
4
CO
8
8
CE
CF
Display-RAM
Address
n+3
A
8
n+2
n+1
n
C
0
DO
6
D1
8
D2
D3
0
8
Display
Byte
(HEX) Char.
8
6
0
6
D4
4
05
4
06
4
07
4
08
09
8
8
0
C
0
OA
6
A
DB
0
DC
0
I,
I,
Display RAM
Address
n+3
0
10
10
m
lmL
10
11
10
10
10
10
n+2
n+1
n
3
6
4
7
3
8
C
8
4
4
0
4
6
6
8
5
0
0
A
0
0
0
4
Invalid
10
8
0
6
8
DE
Invalid
E
0
OF
Invalid
I,
6
6
lm
0
8
0
6
mt
01
0
g
00
N
--N
[OOJ
WO
Invalid
~
~
N'EC
pPD7227
CMOS, INTELLIGENT, DOT-MATRIX
LCD CONTROLLER/DRIVER
NEe Electronics Inc.
Descri ption
Pin Configuration
The IlPD7227 intelligent dot-matrix LCD controllerl
driver is a peripheral device designed to interface
most microprocessors with a wide variety of dot
matrix LCDs. It can directly drive any multiplexed LCD
organized as 8 rows by 40 columns, and is easily cascaded up to 16 rows and 280 columns. The IlPD7227
is equipped with several hardware logic blocks, such
as an 8-bit serial interface,ASCII character generator,
40 x 16 static RAM with full read/write capability, and
an LCD timing controller; all of which reduce microprocessor system software requirements. The
IlPD7227 is manufactured with a single 5 V CMOS process, and is available in a space-saving 64-pin plastic
flat package.
C4
C3
C2
Cl
o
o
o
Ordering Information
Part Number
Package Type
Max Frequency
of Operation
pPD7227G-12
64-pin plastic miniflat
1000 kHz
C2l
R7 /R 15
RslR14
RslR13
C23
R4f R12
C25
10
C26
11
C27
12
Rl/ R9
C2S
13
Ro/Rs
C29
14
VLCDl
C30
15
VLCD2
C32
17
VLCD4
C34
19
cs
R3iRll
VLCD3
o Single-chip LCD controller with direct LCD drive
o Compatible with most microprocessors
o Eight row drives
o
Co
C22
Features
- Designed for dot-matrix LCD configurations up
to 280 dots
- Designed for 5 x 7 dot-matrix character LCD configuration up to 8 characters
- Cascadable to 16 row drives
40 column drives
- Cascadable to 280 column drives
Hardware logic blocks reduce system software
requirements
- 8-bit serial interface for communication
- ASCII 5 x 7 dot-matrix character generator with
64-character vocabulary
- 40 x 16-bit static RAM for data storage, retrieval,
and complete back-up memory capability.
- Voltage controller generates LCD bias voltages
- Timing controller synchronizes column drives
with sequentially-multiplexed row drives
Single + 5 V power supply
CMOS technology
C20
SYNC
Pin Identification
Symbol
Function
NC
No connection
2-24,
47-57,
59-64
CO-C39
LCD column driver outputs
25
Vss
Ground
26, 58
VDD
Power
27
CLOCK
System clock input
No.
28
RESET
Reset input
29
SI
Serial input
30
C/O
Command or data select input
31
SO/BUSY
Serial output or busy output
32
SCK
Serial clock input
33
CS
Chip select input
34
SYNC
Synchronization port
35-38
VLCD1- VLCD4
LCD bias voltage supply inputs
39-46
Ro/Ra- R7/ R15
LCD row driver outputs
6-21
NEe
IlPD7.227
Pin Functions
c/o
CO·C39
Command/data select input. Distinguishes serially input data byte as a command or as display data.
LCD column driver outputs.
CS
RO/8·R7/15
LCD row driver outputs.
Chip select input Enables th~ j.lPD7227 for communication with the microprocessor.
VLCD1· VLCD4
SYNC
LCD bias voltage supply inputs to the LCD voltage .
controller. Apply appropriate voltages from a voltage
ladder connected across VDD.
Synchronization port. For multichip operation, tie all
SYNC lines together and configure with the MODE
SET command.
SI
CLOCK
Serial input from the microprocessor.
System clock input. Connect to external clock source.
SO/BUSY
RESET
Serial output from the j.lPD7227 to the microprocessor
when in read mode and C/D is low. When BUSY (active low), handshake output indicates the j.lPD7227 is
ready to receive/send the next data byte.
Reset input. RC circuit or pulse initializes the j.lPD7227
after power-up.
VDD
Power supply positive. Apply single voltage 5 V±10%
for proper operation.
SCK
Serial clock input. Synchronizes 8-bit serial data
transfer between the microprocessor and j.lPD7227.
Vss
Ground.
Block Diagram
Ro-R7
OR
Rs-R15
SYNC
Voo
Vss
RESET-
Clock
cs
C/O
SO/BUSY
SCK 51
83-0037958
6-22
NEe
J.tPD7227
Absolute Maximum Ratings
DC Characteristics
TA ::: 25°e
T A ::: -10 o e to + 70 o e, Voo ::: +5.0V ± 10%
- 0.3 V to + 7.0 V
Power supply, VDD
All inputs and outputs with respect to Vee
-0.3 V to VDD +0.3 V
Limits
Parameter
Symbol
Min
l'yp
Test
Max Unit Conditions
V
Storage temperature, TSTG
Input voltage, high
VIH
0.7 VDD
Operating temperature, TOPT
Input voltage, low
Vil
0
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Input leakage
current, high
ILiH
+10 /lAVIH
= VDD
Input leakage
current, low
ILil
-10 /lAVIH
= OV
Output voltage, high
Capacitance
TA :::
VDD
0.3 VDD V
VOH1 VDD-0.5
V SO/BUSY,
IOH = -400 /lA
VOH2 VDD-0.5
V SYNC,
IOH = -100 /lA
25°e, Voo ::: OV
Output voltage, low
Limits
Parameter
Symbol
Input capacitance
CI
Output capaCitance Co
Input/output
CIO
capacitance
Min
Max
Unit
10
pF
25
15
0.45
V SO/BUSY,
IOl = +1.7 mA
0.45
V SYNC,
IOl = +100!lA
f+ = 1 MHz
Unmeasured pins
returned to
pF
SYNC ground.
pF
VOL1
Test
Conditions
Output leakage
current, high
IlOH
+10 !lAVOH
= VDD
Output leakage
current, low
IlOl
-10 /lAVOl
= OV
LCD operating voltage
VlCD
3.0
VDD
V 16-row
multiplexed
LCD drive
configuration
VDD
Row drive
output impedance
RROW
Column drive
output impedance
RCOLUMN
IDD
Supply current
V 8-row
multiplexed
LCD drive
configuration
8
kO
10
15
kO
200
400
/lAfO
= 400
KHz
6-23
m
~EC
JAPD7227
AC Characteristics
TA
= -1O o e to
+ 70 o e, Voo
= +5.0V
± 10%
limits
Symbol
Min
Max
Unit
Clock frequency
f+
100
1000
KHz
Clock pulse
width high
t+WH
400
ns
Clock pulse
width low
t+WL
400
ns
SCK cycle
tCYK
0.9
/As
SCK pulse
width high
tKWH
400
ns
SCK pulse
width low
tKWL
400
ns
SCK hold time
after BUSyt
tKHB
0
ns
SI setup time
to SCKt
tlSK
100
ns
SI hold time
after SCKt
tlHK
250
ns
SO delay time
after SCK~
tOOK
SO delay time
after C/D~
tO~~
SCK hold time
after C/D~
tKHO
BUSY delay
time after 8th
SCKt
tBOK
BUSY delay
time after Clot
tBOO
BUSY delay
time after CS~
tBOC
C/O setup time
to 8th SCKt
tOSK
lis
C/O hold time
after 8th SCKt
tOHK
/As
CS hold time
after 8th SCKt
tCHK
/As
CS pulse width
high
tCWH
Parameter
320
CLOAOS
BUSY low
level width
tWLB
CLOAO =
50 pF
/As
2
/As
3
/As
CLOAO =
50 pF
/As
2
2/f+
/As
/As
CSt delay time
tCOB
to BUSY floating
SYNC load
capacitance
ns
Test
Conditions
/As
18
100
pF
64
1/f+
CLOAO =
50 pF
CLOAO =
50 pF
NEe
J.tPD7227
Timing Waveforms
Clock Waveform
1+-----------111,1'-----------.1
Clock
83-003837B
Serial Interface
~
___- - - - - - - - - - - - - - - - - - - - - - - ___ ----+-_-1
C/O
(SO)
--a--++------------------ - -- -------++_~
8th
SI
========================~========
83-0038388
NEe
IAPDl227
Command Summary
Instruction Code
Binary
Description
D7
D6
D5
Initialize the jAPD7227,
including selection of
1. LCD drive configuration
2. Row driver port function
3. RAM bank
4. SYNC port function
0
0
0
Frame
Frequency
Set
Set LCD frame frequency
0
0
Load Data
Pointer
Load data pOinter with 7 bits
of immediate data
Write Mode
Write display byte in serial
register to RAM location addressed by data pointer;
modify data pointer
Read Mode
Command
D_
D3
D2
D1
Do
HEX
D2
D1
Do
18-1F
0
D2
D1
Do
10-14
D4
D3
D2
D1
Do
80-E7
0
0
0
D1
Do
64-67
Load RAM contents addressed by data pointer into serial
register for output; modify
data pointer
0
0
0
D1
Do
60-63
AND Mode
Perform a logical AND between the display byte in the
serial register and the RAM
contents addressed by data
pointer; write result to same
RAM location; modify data
pOinter
0
0
D1
Do
6C-6F
OR Mode
Perform a logical OR between the display byte in the
serial register and the RAM
contents addressed by data
pointer; write result to same
RAM location; modify data
pOinter
0
0
D1
Do
68-6B
Character Mode
Decode display byte in serial
register into 5 x 7 character
with character generator;
write character to RAM location addressed by data
pointer; increment data
pointer by 5
0
0
72
Set Bit
Set single bit of RAM location addressed by data
pointer; modify data pointer
0
Reset Bit
0
0
Enable Display
Reset single bit of RAM location addressed by data
pointer; modify data pointer
Turn on the LCD
0
0
0
0
Disable Display
Turn off the ICD
0
0
0
0
0
Mode Set
D6
D5
0
0
0
D4
D3
D2
D1
Do
40-5F
D4
D3
D2
01
Do
20-3F
0
1
09
0
0
08
Further details of operation can be found in the IlPD7227 intelligent dot-matrix LCD controller/driver technical manual.
NEe
JiPD7227
5)( 7 Character Set as Generated in ",PD7227
Display Byte
Display Byte
° °
° °
ro;- -,,;- -,;;-/0.---0---10 lo-d""-o-o.;.-0-+_-+-0--+----1 ro;- --- -o~-I-o~3
-2""-
06
03
I 02 I 0 1 I Do
° °
° °
° °
( ~ 0 • -:; 0 • • • 0 • 0 0 D • • 0 0 0 .
( ' . , " . 0 0 0 • • 000 • • 0 0 0 e
o
o
o
o
o
o
e c-",:e000 • • 000eoeoeo
•
•
e-,
•
o
o
o
o
0.0.00 ••• 0
o
o.
0 ••• 0 ••••• 00.00
• ~, " ') • • ') 0
0.0.0
.')0,) • • ,00 • • 000 •
, 0 • • • oeoOO • • 000e
o
•••• 0
oeoeoeooo • • ooo.
oeo.ooooo • • ooo.
o
o
mnmgmg
0.0.0
•••••
o
0 ••• 0
oeo.ooooeoeooo.
o
o
1
m:~Hm:~m
oeo.oeooo.eooo.
oeo.oo ••• oo ••• o
o
u".ooooo.o ••• oo •••••
0 ••••
o
o
0
mnmHmHHm
HmHmHmHm
~m~ gm gm m~;
• • 000
ooooooooeoeooooooooo
00 • • 0 . 0 0 . 0 0 0 . 0 0
oooooooeooeooooeoooo
o
0
• • • • • • • • • • • 000.
ooooooooooeoooeo ••• o
• • 00 • • 0 0 0 0 . 0 0 0 0 . 0 0 0 .
o
o
1
IHHHmHwnm
OOOOOQOOOO • • O • • OOO.O
o
1
HHHHH HHHHH
O • • OODO • • O · • • • • • O O " .
o
o
o
.oo.oeooo • • ooooo.o.o
o •• oeo ••• o·oooooo.oo
000000 ••• 00 ••• 000000
0 0 0 0 • • 000 • • 0 0 0 . 0 0 0 0 0
000.00000 • • 000.00000
00.00000.0.000.00000
0.00000.00.000.00000
.000000000.000.00000
0000000.000 ••• 0 •••••
6-27
JlPD7227
6-28
NEe
NEe
NEe Electronics Inc.
pPD7228
CMOS, INTELLIGENT, DOT-MATRIX
LCD CONTROLLER/DRIVER
Description
Ordering Information
The I-/PD7228 intelligent dot-matrix LCD controllerl
driver is a peripheral device designed to interface most
microprocessors with a wide variety of dot-matrix LCDs.
It can directly drive any multiplexed LCD organized as 8
rows by 50 columns or 16 rows by 42 columns. The
I-/PD7228 has a standby function to conserve power. It is
equipped with several logic blocks, such as an 8-bit serial interface, a 4-bit parallel interface, an ASCII upperl
lower case, a Kana character generator, a 50 x 16 static
RAM with full read/write capability, and an LCD timing
controller, all of which reduce microprocessor system
software requirements.
Part
Number
Package Type
jlPD7228G-12
80-pin plastic miniflat
Pin Configuration
The pPD7228 is manufactured with a single 5 V CMOS
process, and is available in an 80-pin space saving
miniflat plastic package.
Features
o
o
LCD direct drive
8- or 16-line multiplexing drive possible with singlechip
- 8-line multiplexing: 400 (50 x 8) dots
- 16-line multiplexing: 672 (42 x 16) dots
8-line or 16-line multiplexing drive with n chip
configuration
- 8-line multiplexing: n x 400 (n x 50 x 8) dots
-16-line multiplexing: n x 800 (n x 50 x 16) dots
DRAM: 2 x 50 x 8 bits for display data storage
o Programmer designated dot (graphics) display
o 5 x 7 dot-matrix display by on-chip character generator ASCII characters (alphanumerics, others): 64
characters; J IS characters (Kana and others): 96
characters
o Cursor operating command
o 8-bit serial interface compatible with I-/PD7500,
I-/COM-43N,I-/COM-87/87LC
o 4-bit parallel interface compatible with I-/PD7500,
I-/COM-84/84C
o Standby function
o CMOS technology
o Single +5 V power supply
o Extended - 40°C to +85°C temperature range.
available'
o
83-002904A
6-29
NEe
""PD7228
Pin Identification
SO Serial Data·Out (Output Common to D3)
No.
Symbol
Function
1-4,43-80
CO-C41
LCD column drive outputs
5-12
C42 I R15C49 /R a
LCD row I column drive outputs
13-20
RO I Ra-R7 I R15
LCD row drive outputs
In serial interface mode, SO is an output pin for serial
data. The contents of the serial I parallel register are output to the SO pin, beginning with the most significant
bit, on the falling edge of SCK.
PIS ParaliellSerial Select (Input Common to D1)
21, 22, 24-26 VLC1-VLC5
23,42
NC
No connection
27
Do/SI
Data bus 0I serial input
28
D1(P/S)
Data bus 1(parallel I serial select)
29
D2(CAE)
Data bus 2 (chip address enable)
30
D3 /SO
Data bus 31 serial output
CAE Chip Address Enable (Input Common to D2>
31
SYNC
Synchronization signal input loutput
32
BUSY
Busy signal output
33
Voo
Power supply
Ground
This pin is only used during serial interface mode, that
is, when PIS is low at the falling edge of RESET. To enable chip addressing, the CAE line must be high at the
falling edge of RESET. In parallel interface mode (when
PIS is high at the falling edge of RESET), the chip addressing function is enabled regardless of the logic
state of CAE at the falling edge of RESET. The Schmitttrigger input prevents noise errors.
LCD power supply
34
Vss
35
STB/SCK
Strobe I serial clock input
36
C/D
Command I data select input
37,38
CAo, CA1
Chip address select inputs
39
CS
Chip select input
40
RESET
Reset signal input
41
CLOCK
System clock input
Pin Functions
DO- D3 (Data Bus)
In parallel interface mode, 00-03 are inputloutput pins
for 4-bit parallel data. Data on these lines is read at the
rising edge of STB. The four bits read on the first STB are
loaded into the highest four bits of the serial/parallel
register. The four bits read on the second STB are
loaded into the lowest four bits of the register.
The contents of the serial/parallel register are output to
these pins on the falling edge of STB. As in the above
case, the high-order four bits correspond to the first
STB, and the low-order four bits to the second STB.
In serial interface mode, Do is a serial data input pin and
03 is a serial data output pin. 01 selects serial or parallel
interface mode (PIS), and 02 is the chip address enable
pin (CAE).
SI Serial Data·ln (Input Common to DO)
In serial interface mode, SI inputs serial data. Data on SI
is loaded into the serial/parallel register at the rising
edge of SCK. The first data loaded is the most
significant bit. To eliminate noise errors, SI uses the
Schmitt-trigger input.
6-30
This pin sets parallel interface mode if it is high at the
hilling edge of RESET (at reset release). If it is low at the
falling edge of RESET, it selects serial interface mode.
The Schmitt-trigger prevents noise errors.
CAO-CA1 (Chip Address)
These input pins allow you to address the ",PD7228 in a
multi-chip configuration used for driving logic displays.
During parallel interface mode, CAo and CA1 are compared to chip address data sent from the CPU regardless of CAE status during a reset.
However, during serial interface mode, CAo and CA1 are
compared with chip address data from the CPU only
when CAE enables chip addressing.
In multi-chip configurations, the device is selected if
CS 0 and CAo and CA1 match the chip address generated by the CPU. This address is the low two bits of the
first 8-bit data input after CS O.
=
=
In serial interface mode, if chip address selection is not
used, connect CAo and CA1 to ground.
CS (Chip Select)
CS is an active-low chip select input pin. When you are
not using the chip address selection function, the STBI
SCK and C/D inputs are enabled if a low input is sent to
CS.
When you are using the chip address select function, if
CS is brought low and the chip address data matches
CAo-CA1, then STB/SCK and C/O are enabled.
When CS is made high, 03-00 and BUSY are placed in a
high impedance state. The Schmitt-trigger input prevents noise errors.
NEe
J.lPD7228
STB/SCK (Strobe/Serial Clock)
In parallel interface mode, this is the strobe signal input
pin (STB) for 4-bit parallel input and output data. In serial
interface mode, this is the serial clock input pin (SCK)
for serial input and output data.
C/O (Command/Data)
This pin specifies whetherthe parallel or serial input is a
command or data. Bring C/O high to input a command,
and low to input data.
In parallel interface mode, the contents of C/O are
latched at the rising edge of the second STB. Perform
any changes to the C/O input before the falling edge of
the first STB. When outputting data, hold C/O low,
whether serial or parallel.
In serial interface mode, the contents of C/O are
latched at the rising edge of the eighth SCK.
The Schmitt-trigger input prevents noise errors.
BUSY (Busy)
This pin outputs a busy signal to the CPU to warn that
the IJPD7228 is internally busy. When this signal is low,
the CPU cannot read/write the IJPD7228.
=
If a chip is deselected (CS high or chip address data
does not match), the busy output is placed in the high
impedance state.
SYNC (Synchronous)
In a multichip configuration, the SYNC signal synchronizes the phases of the LCD drive AC signals (row/
column signals) among all the f,lPD7228's within the
frame period. It uses the row drive signal as a common
signal.
If one chip is designated master, its SYNC pin is in output mode and the remaining chips are made slaves.
Their SYNC pins are put in input mode. The SMM command selects input or output mode. The master chip
outputs a SYNC pulse in the last cycle of each frame.
The slave chip reads the SYNC pulse from its own SYNC
input for synchronization with the master chip.
In a single chip configuration, set the SYNC pin in the
input or output mode. If you choose input mode, connect the SYNC pin to VSS; conversely, if you choose output mode, the SYNC pin must be open.
Figures 1 and 2 show the output timing for the SYNC
pulse in 8- and 16-line multiplexing.
In the parallel interface mode, BUSY is forced low at the
rising edge of the second STB. In the serial interface
mode, BUSY is forced low at the rising edge of the
eighth SCK.
Figure 1.
SYNC Signal in B-line Multiplexing
1+1·---------1frame---------I
Row 0
~~ ~ _ _ _ __..__In_____
83-0029058
6-31
NEe
J.(PD7228
Figure 2.
SYNC Signal in 16-line Multiplexing
1----------1Irame-----------t.,
Row 0
83-OO2906B
CO-C41 (Columns)
RESET (Reset)
These pins output the column drive signal for the LCD.
This is the active-high reset signal input pin. It has priority over all operations. You can also use it to release
standby mode and begin low power data retention.
Ral C49-R151 C42 (Row I Column)
These pins are row drive outputs (RS-R1S) or column
drive outputs (C49-C42), depending on the SMM command.
This is apositive power supply pin.
RO/RS-R7/R15 (Rows)
Vss (Ground)
These pins are row drive outputs for rows Ro-R7 or rows
Rs-R15, depending on the SMM command.
This is ground (GND).
Voo (Power Supply)
Commands for ",PD7228
VLC1-VLC5 (LCD Drive Voltage Supply)
These are reference voltage input pins for determining
the voltage level of the LCD row I column drive signals.
CLOCK (Clock)
This is the external clock input pin.
6-32
The ",PD7228 is provided with sixteen types of commands, each command consisting of one byte (8 bits).
Figure 3 shows the character codes and display
patterns.
NEe
Figure 3.
J-tPD7228
Character Codes and Display Patterns
7
4
3
0
I I I I
0
0
0
0
0
0
0
0
0
0
0
o
o
o
o
0
1
0
0
0
0
0
0
0
0
0
..
0
0
0
0
0
0
0
0
0
0
0
..
..
0
0
0
0
.....
..
..
:
..
....
: ..
..
0 1 1
.. ... :
..
:
: :
· . ... .....
..
.
...
.... .. ... ..... ....... ...... ..... .. .. .... .... .. .........
..... ...
·....
.. ..
........
. ..................
... · . . .. ...' ......
.......
..... ..
......
..
...
.
.
.
.
.
o 0 ...
...
..
..
..
.
....
....
... .... . ....
.... ....
... ......
... ......
.......
.. .... .
....
..
..
..
..
· ... ..
........
.....
.
. ....... .. .
..
.. ... .
......
..
.. ..
.... ..
o 1 ···.... ......
.... ..
.. .
...
..
.......
. .......'
.
.....
....... .
.
.
.
.
.
...
...
...
....
..
.
··· .
...
..
. ...
....
1 0
..
..... ......
.... .. ..........
.
.... ....
......
.
···· .......
.
......
.. ...... .
··
.. ..........
.
..
...
. ..
.... ........ .....
. ......................
o
..
...... ......
.. ......
o
.. . ......
. ..
..
. ..... ...........
..
..
.. .....
..... .... ..... ..... ........
........... .
o 1 1 ..... .: ... ':. .: .: .: ..
.': : : .. : ... ' : ' :
: : : , , : .. ' : .' '. :
. ......
... . .
. . ... . .. ...
.
.........
.... ... ...
..... .... .
1 0 0 .... : .. :" : : : ":"
. .. ..
..
.
· ..
...... . .. ....
...·· .....
..
·
...........
.
. ..
.
. ...
..
.. .....
o 1
.. .. .. ..
· ............
. .. ... .....
.........
... ... .
. .. ..
:
••
••
e..
•••
•
•
•
••
"'
• ••••••••
eo
••••••
"
'
'
. 83-0029138
6-33
NEe
",PD7228
Block Diagram
c·s
R-S
R·NS
C·NS
Clock
1
t:i
1/1
w
I~
~
~
10
0
a:
I~
I~
~
~
8
riI
I~
8
6-
~
iii
8
83-0029076
Absolute Maximum Ratings
Capacitance
TA=25°C
TA=25°C; Voo=OV
Supply voltage, Voo
-0.3Vto +7V
10
pF
(Note 1)
Co
25
pF
(Note 1)
I / 0 capacitance CIO
15
pF
(Note 1)
Parameter
Output voltage, Vo
-0.3VtoVoo +0.3V
Input
capacitance
CI
Storage temperature, TSTG
Output
capacitance
Comment: exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is
not meant to be operated under conditions outside the limits described in the operational sections of the specification. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
6-34
Te,t
Condition,
- 0.3 V to Voo +0.3 V
Operating temperature, TOPT
Umltl
Typ
Mal
Unit
Symbol
Input voltage, VI
Min
Note:
(1) f 1 MHz. Return unmeasured pins to 0 v.
=
NEe
j-tPD7228
DC Characteristics
TA= -10 0 Cto +70 o C, voo= +5V±10%
Common Operation (cont)
Umlts
Parameter
Symbol
Typ
Min
Max
Unit
Test
Conditions
Umlts
Parameter
Symbol
Input voltage
high
VIH1
0. 7VOO
VOO
V
Except SCK
VIH2
0. 8VOO
VOO
V
SCK
Input voltage
low
VIL
0
0. 3VOO
V
Output voltage
high
VOH1
Voo-0.5
V
BUSY, 00-03,
10H= -400~
CS high level
time
tWHCS
VOH2
Voo-0.5
V
SYNC,
10H= -100,..A
SYNC load
capacitance
CLSY
Output voltage
low
Min
Typ
BUSYJ!elay time tOCSB
from CS +
CS~aytime
4
tOCSBF
Unit
Test
Conditions
}AS
CL =50 pF
}As
CL =50 pF
to BUSY floating
VOL1
0.45
V
BUSY, 00-03,
10L =1.7mA
Data set-up time tSOR
to RESET +
SYNC, 10L =100~
Data hold time
from RESET +
4
}As
100
4
J.ls
VOL2
0.45
V
IUH
10
~
VI=VOO
Input leakage
current low
IUL
-10
~
VI=OV
Serial Interface Operation
Output leakage
current high
ILDH
10
~
VO=VOO
Parameter
Symbol
Output leakage
current low
-10
~
VI=OV
SCK cycle
ILDL
tHRO
pF
}As
Input leakage
current high
Limits
LCD operating
voltage
VLCO
Row output
impedance
RROW
Row/column
output
impedance
RROW/
COL
Column output
impedance
RCOL
Supply current
1001
3.0
4
VOO
V
8
kQ
0.9
J.ls
ns
SCK pulse width tWLK
low
400
ns
SCK hold time
from BUSY t
tHBK
0
ns
tSIK
100
ns
250
ns
10
15
kQ
SI hold time
from SCK t
tHKI
200
400
~
Operating mode
fc=400 kHz
SOd~time
from SCK +
tOKO
20
~
Stop mode
CLK=OV
BUSY delay time tOKB
from eighth
SCK t
Max
Unit
1100
kHz
Clock frequency fC
100
Clock pulse
width high
tWHC
350
ns
Clock pulse
width low
tWLC
350
ns
RESET pulse
width high
tHRS
J.lS
Test
Conditions
320
tWLB
18
C/5 s~ time tSOK
to firstSCK +
0
BUSY low-level
time
Common Operation
Typ
Unit
Test
Conditions
SCK t
TA= -10°C to +70°C, Voo= +5V±10%
Min
Max
400
~et-up time to
AC Characteristics
Symbol
Typ
tCYK
kQ
Limits
Min
SCK pulse width tWHK
high
10
1002
Parameter
Max
64
ns
CL =50 pF
J.ls
CL =50 pF
1/fc
CL=50pF
J.ls
C/5 hold time
from eighth
SCK t
tHKO
J.ls
CS holdfime
from eighth
SCK t
tHKCS
J.lS
D
NEe
fAPD7228
AC Characteristics (cont)
TA= -10°C to + 70°C, Voo= +5V±10%
Parallellntertace Operation
Parallel Interface Operation (cont)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test
Conditions
Limits
Parameter
Symbol
Input command tA
set-up time to
STB +
100
ns
CL =80 pF
BUSY delay time tOSB
from second
STB t
Input command tB
hold time from
STB +
90
ns
CL =20 pF
C/ Dset-up time tsos
to first STB +
Input data setup time to STB
tc
230
ns
CL=80pF
Input data~d to
time from STB t
50
ns
CL =20 pF
Output data
delay time
90
650
ns
150
ns
Output data hold tH
time
700
STB pulse width tSL
low
0
Typ
Max
Unit
3
jAs
tHSO
Ils
tHSCS
jAs
CL =80pF
CS hold time
from second
STB t
CL =20 pF
AC Timing Test Points
ns
J O . 7 V D D > Test ___ O. 7VO D L
O.3VDO
Points - - - O.3VOO
jAs
STB high level
time
tSH
STB hold time
from BUSY t
tHBS
0
Test
Conditions
Ils
C/ D hold time
froms econd
STB t
t
tACC
Min
83-002909A
jAs
Timing Waveforms
Seriallntertace
c/o
BUSV--------------
83-0029086
NEe
/JPD7228
Timing Waveforms (cont)
Clock Waveform
Interface
RESET
~.~
.
t.,nD~
=3E~"3-----
CL
83-002910A
83-002912A
Parallel Interface
C/O
BUSy----(I
&B--------------~
00-03
00-D3------------------------~
83-0029118
Reset Signal
F '"~\'------
RESET______- - J
83·003856A
NEe
/JPD7228
Command Summary
Command Summary
1. Set frame frequency
2. Set multiplexing mode
0
0
0
0
0
0
F2
F1
FO
M2 M1 MO
0
Mnemonic
Operation
4. Display on
5. Set read mode
0
0
0
0
0
0
0
0
0
0
0
11
10
6. Set write mode
0
0
11
10
7. Set AND mode
0
0
11
10
8. Set OR mode
0
0
11
10
9. Set character mode with
right entry
0
0
0
0
10. ·Set character mode with
left entry
0
11. Bitset
0
12. Bit reset
0
13. ·Write cursor
0
0
14. ·Clear cursor
0
0
0
DO
15. Load immediate to data
pointer
16. ·Set stop mode
0
0
0
0
0
0
B2
B1
BO
J1
JO
B2
B1
BO
J1
JO
06
D5 D4 D3
D2
D1
0
0
0
0
0
Note:
• Newly added (compared to ",PD7227).
0
o
0
0
b
0
0
Set frame frequency
0
0
0
SMM
Set multiplexing mode
0
0
0
0
0
D2 D1 Do 10-14
D2 D1 Do 18-1F
0
0
0
0
0
08
DlSPON
Display on
0
LDPI
Load data pOinter with
immediate
.
D6 D5 D4 D3 D2 D1 Do 80-B1,
CO-F1
SRM
Set read mode
0
1 0
0
SWM
Set write mode
0
0
0
SORM
Set OR mode
0
0
SANDM
Set AND mode
0
0
SCML
Set character mode with
left entry
0
0
0
SCMR
Set character mode with
right entry
0
0
0
BSET
Bit set
0
1 0 D4 D3 D2 D1 Do 40-5F
BRESET
Bit reset
0
0
D4 D3 D2 D1 Do 20-3F
1
1
1 0
1
70
1
1
1 0
0
7C
0
0
0
0
0
0
0
1
SFF
DlSPOFF Display off
3. Display off
Instruction Code
Binary
D7 De Ds D4 D3 D2 D1 Do HEX
1
WRCURS Write cursor
0
CLCURS
Clear cursor
0
1
STOP
Set stop mode
0
0
0
09
0 D1 Do 60-63
01 Do 64-67
0 D1 Do 68-6B
1 1 D1 Do 6C-6F
71
0
0
0
72
01
NEe
NEe Electronics Inc.
pPD72030
CMOS, INTELLIGENT
LCD CONTROLLER
Pin Configuration
Description
The ",PD72030 intelligent LCD controller manipulates
dot-matrix characters and graphics by host CPU commands that are provided through an 8085-compatible
bus interface. This frees the host to perform other
tasks, and so increases overall system efficiency. The
",PD72030 utilizes an 8-bit parallel bus that connects,
without an additional interface, to such generalpurpose microcomputers as the ",PD8085AH or
",PD8086. This bus permits high-speed data transfer
to the LCD driver. A font character generator of up to
16 x 16 dots can be externally attached, permitting
the generation of Kanji (Sino-Japanese) and other
characters. A 5 x 7 dot character generator for
alphanumeric characters and symbols totalling 64
characters is internally supported.
NC
LAS
SPLT
LA7
DRAM
CKOUT
LA6
LAs
LA4
LA3
LA2
LA1
LAo
LD7
LD6
LDS
LD4
LD3
LD2
Features
LD1
D Display duty: 1/32 to 1/128
D Display control
- Cursor manipulation
- Vertical and horizontal movement
- Direct addressing
- Shift to home position
- Editing
- Scrolling
- Attribute functions
- Reverse display
- Underline
- Blinking display
D Directly connectable to LCD driver
MEMR
MEMW
LDO
49-000979A
",PD6307/6308
D CMOS technology
D Single +5 V power supply
Ordering Information
Part Number
J.lPD72030G-12
Package Type
Max Frequency
of Operation
64-pin plastic miniflat
6 MHz
6-39
NEe
I-'Pl),.72030
Pin Identification
Pin Functions
No.
Symbol
1-6,8-11,
56-64
LAo-LA18
Local address bus output
7,39
VDD
Power supply input
12
INT
Interrupt request output
13
CGEN
Character generator enable output
14
NC
No connection
Function
Data Bus [00.07]
This 1/0 data bus interfaces with the host CPU. Writing
of commands, parameters, and data, or reading of
status and data are performed through this bus.
Address 0 [AO]
When input AO is low, the data bus contains data or
a parameter. When AO is high, the data bus contains
a command or status. AO connects to the host CPU
address bus.
15
SPLT
Split screen select output
16
DRAM
DRAM reset enable output
17
CKOUT
Clock output
18
EOT
End of transfer output
19
DREQ
DMA request output
Chip Select [eS]
20
DACK
DMA acknowledge input
21
TC
Terminal count input
A low input to this pin enables the host CPU to read
from or write to the data bus. CS connects to the host
CPU address decode signal.
22-29
Do-D7
Data bus liD
30
WR
Write strobe input
31
RD
Read strobe input
32
CS
Chip select input
33
AO
Address 0; command and signal
input for data .bus function
34
TEST
Sets test mode input
35
RESET
Reset input
36,37
X2,X1
Clock pins
38
VSS
Ground
40
STB
Strobe output
41
FRM
Frame; AC converted signal output
. that drives the LCD
42
RST
LCD driver reset output
43
SBY
LCD standby mode output
44,45
IOW2,IOW1
LCD driver write strobe output
46
MEMW
Local memory write output
47
MEMR
Local memory read output
48-55
LDo-LD7
Data bus input to local memory
Read Strobe [RO]
A low input to this pin while CS is active enables the
JlPD72030 to send status or data to the data bus. RD
connects to the host CPU read strobe.
Write Strobe [WR]
A low input to this pin while CS is active enables the
JlPD72030 to receive a command or parameter. WR
connects to the host CPU write strobe.
OMA Request [OREQ]
This pin outputs a DMA service request for data block
transfer. When a data block transfer is required
between host CPU memory and JlPD72030 local
memory, if the transfer is possible, DREQ will be set
high to request DMA service. DREQ connects to the
service request input of the DMA controller. If the
block transfer function is not used, this pin should
be left open.
OMA Acknowledge [OACK]
A low input to this pin acknowledges a DMA service
request and internally sets CS and AO low. DACK
connects to the service acknowledge output of the
DMA controller. If the block transfer function is not
used, this pin should be pulled high.
Terminal Count [TC]
A low input to this pin indicates data block transfer
has terminated. TC connects to the DMA transfer
termination output of the DMA controller. If the block
transfer function is not used, TC should be pulled
high.
6-40
NEe
J,lPD72030
Local Data Bus [LDo-LD7]
Strobe [STB]
This data bus input provides communication between
the J.lPD72030 and local memory, which consists of
display memory and the character generator.
This is the row driver strobe. One STB pulse output
at the timing interval causes the display of one row.
The number of STB outputs during each frame interval determines the display duty.
Local Address Bus [LAo-LA1S]
This address bus output accesses local memory.
LAo-LA15 address display memory. LA16-LA18 address
the external character generator.
Character Generator Enable [CG EN]
This output enables the external character generator.
When CGEN is high, the character address and scan
address are output on LAO-LA18. When CGEN = 0, the
address to display memory is output on LAo-LA15;
LA16-LA18 become don't care. When the external
generator is not used, CGEN should be left open.
Frame [FRM]
This output is an AC-converted signal that drives the
LCD. A high-level output displays a positive frame (one
screenful) and a low-level output displays a negative
frame.
End of Transfer [EOT]
When low, this output indicates one row of display
data has transferred. EOT is a clear signal for the CS
Signal generator counter of the row driver.
LCD Driver Reset [RST]
Split Screen Select [SPLT]
When the partitioned matrix display is used, this output pin selects which of two refresh memories will be
available for access. When SPLT is low, refresh
memory for the upper portion of the screen is accessed. When SPLT is high, refresh memory for the
low portion of the screen is accessed.
DRAM Reset Enable [DRAM]
When dynamiC RAM (DRAM) is connected to local
memory, the logical AND of this output signal and the
J.lPD72030 RST signal is input to the RST pin of the
column driver. This prevents a loss of display memory
contents while the display is off, without refreshing
DRAM.
Local Memory Read [M EM R]
This is the read strobe output to local memory. When
MEMR goes low, the J.lPD72030 reads the contents of
local memory. If IOW1 and IOW2 are also low level,
the contents of display memory are directly written
to the LCD driver.
This output goes low when the LCD driver is being
reset For normal display, RST is high level.
LCD Standby [SBy]
This output goes low when the LCD display stops and
the LCD driver enters standby mode. For normal
display, set SBY high level.
Clock Out [CKOUT]
This pin outputs a clock whose frequency is 1/15 that
of the original oscillator.
XTAL1, XTAL2 [X1, X2]
These pins are used to connect an external crystal.
Because the J.lPD72030 has a built-in high-gain
amplifier, a functional clock can be generated by connecting a crystal or ceramic resonator and two
capacitors to X1 and X2.
When an external clock is used, X1 inputs the clock
and X2 is left open.
Reset [RESET]
Local Memory Write [MEMW]
This is the write strobe output to local memory. When
MEMW goes low, data is written to local memory.
LCD Driver Write Strobe [lOW1, IOW2]
These are the data write strobe outputs to the column
driver. For each MEMR pulse, IOW1 generates one
pulse and IOW2 generates two pulses. IOW1 and
IOW2 are selected according to how the column driver
is used.
A low-level input to this pin initializes the J.lPD72030.
Interrupt Request [INT]
This pin outputs an interrupt service request to the
host CPU. If INT = 1, a command is being processed.
If INT = 0, a command process is complete and the
J.lPD72030 is ready to request a new command from
the host Cpu.
6-41
NEe
""PD72030
Test [TEST]
Functional Description
A high-level input to this pin sets the ",PD72030 to test
An LCD display system can be configured by connecting a row and column driver (a ",PD6307 and ",PD6308)
and a general-purpose RAM as display memory to the
",PD72030. An external character generator may be
connected.
mode. For normal use, the input to the TEST pin should
be fixed low by connecting TEST directly to Vss.
Vss
Ground.
Voo
Positive power supply.
Block Diagram
iNf
SPLT
AD
cs
CGEN
AD
WR
Local Memory
Access
Controller
DO-07
LAD-LA18
LDO-L07
OREQ
OACK
MEMR
fC
The ",PD72030 performs both the display and command process. In the display process, the ",PD72030
drives an LCD panel by sending display memory data
to the column driver, and timing signals to the row
and column drivers. At fixed intervals generated by
the ",PD72030, the display memory contents are
transferred directly to the column driver via the I()cal
bus. When two or more' column drivers are connected
to the system, the row driver CS signal determines the
column driver to which the data is to be written~ After
display data is stored in each column driver, the STB
signal is output. One line of display data is then output to the LCD panel. The row signals are scanned,
and the above sequence is repeated to drive the LCD
panel using this time-division method.
MEMW
RESET
TEST
RST
SBV
ORAM
LCOTlming
Generator
IOWl
IOW2
EOT
STB
FRM
CKOUT
Clock
Generator
Xl
X2
V
__
oo
Vss _ _ Power Supply
49-000963A
6-42
In the command process, the ",PD72030 manipulates
the contents of display memory with host CPU commands. In order for the ",PD72030 to process a command, the host CPU must read and check the status
of the ",PD72030.1f the ",PD72030 is processing a command, the host continues to read and check status
until the ",PD72030 is in the command wait state (no
command is executing). When the ",PD72030 is in the
command wait state, the host sends a command to
the ",PD72030. (An interrupt may also be used.) The
",PD72030 interprets the given command and executes
it.
NEe
J.(PD72030
Absolute Maximum Ratings
DC Characteristics
TA
TA
TA
= 25°C
Supply voltage, Voo
Vss - 0.3 to + 7 V
Input voltage, VI
VSS - 0.3 V to Voo + 0.3 V
Output voltage, Va
Vss - 0.3 V to Voo + 0.3 V
Operating temperature, TOPT
-10 to +70°C
Storage temperature, TSTG
-65 to +125°C
Comment: Exposing the device to stresses above those listed in
Absolute Maximum Ratings could cause permanent damage. The
device is not meant to be operated under conditions outside the
limits described in the operational sections of this specification.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Recommended Operating Conditions
Limits
Parameter
Symbol
Supply voltage
VOO1
Operating
frequency
fOPT1
Supply voltage
VOO2
Operating
frequency
fOPT2
Min
Typ Max Unit
4.75 5.0 5.25
6
4.5
5.0
5.5
V
6
MHz
+70 o C, Voo
+50 o C, Voo
TA= -10 to + 70°C
=5V
=5V
±5%
±10%
Limits
Symbol
Min
Input voltage low
VIL
Input voltage
high
VIH1
VIH2
Parameter
lYP
Test
Conditions
Max
Unit
-0.3
0.7
V
2.2
Voo
+ 0.3
V
Voo
- 1
VOO
+ 0.3
V
0.45
V
(1)
V
(2)
Output voltage
low
VOL
0
Output voltage
high
VOH
4.0
Input current
111
-25
112
Test
Conditions
V
MHz
= -10 to
= -10 to
Other than
RESET, Xl
RESET, Xl
-3
!JA.
RESET VI:sVIL
7.5
JAA
Xl: VI>VIH
-7.5
JAA
X1: VI
o
V
Test <2.2VC
Points
0.7 V
49·001311A
1+----tOACK-----+I
AC Output Test Points
WR,RD
49·001312A
Clock Timing
1
too
DREQ/r---~
49-001314A
49·001313A
Read Timing
49-00131SA
Write Timing
DACK,
(;S,AO
00- 0 7
-------(1
49-001316A
6-46
NEe
",PD72030
Timing Waveforms (cont)
Local Bus Timing
Display Timing
SPLT,CGEN,
LAo-LA18
MEMW------------~----~------------~----------+_---
LDO-LD7
------------------+--<
CKOUT
49-0013178
Display Timing
STB
FRM -------------'"'\.
RST
SBY - - - - - - - - '
.J.:--------------11=--------49-001318A
6-47
ttiEC
JAPD72030
Commands
Timing Waveforms (cont)
Paragraphs that follow explain the four initialization
commands, nine function specifying commands, 21
display control commands, and 20 display data
manipulation commands.
Local Bus Timing (cant)
Read Timing
SPLT,CGEN,
Initialization Commands
LAo-LA18
SYNC
I I
o
MEMW--~~~----------~------
Parameters
IOW1--~~~----------~------
• Column direction (bytes)
(L)
(H)
• Time division
• 0 0 0 0 0
it STB cycle
49-001319A
Write Timing
SPLT,CGEN,
LAO-LA18
MEMR
--t--------------------t--
0
B1
BO
Function. This command specifies the LCD panel size
and the timing to generate control signals (FRM and
STB) to the LCD driver. The total number of pixels in
a row can be up to twice the number of time divisions.
BO specifies whether the connection for expansion is
used.
BO = 0 Single matrix
1 Partitioned matrix
B1
o DRAM not used
1 DRAM used
DSPDEF
IOW1
--t---~~----rr----------
I I
0
o
o
Parameters
IOW2 ~~~--------~----------
49-001320A
6-48
•
•
•
•
•
•
•
Characters/line
Character rows/screen
Font size in column direction
Font size in row direction
Cell size in column direction
Cell size in row direction
0 0 0 0 B3 B2 B1 BO
t-iEC
J,tPD72030
Function. Font and cell size are specified by a number
of pixels. Cell size equals the character font size plus
the size of the gap between each character, with the
following limitations:
Cell column = 5 to 10, 12, or 16 pixels
Cell row = 7 to 17 pixels
B3 specifies the use of character code for the scan
address. When B3 = 0, SA4 of the character code is
used for the scan address. When B3 = 1, SA4 of the
character code is used for the CS of the external
character generator, in which case the following fonts
are allowed:
Column Size
Row Size
1 to 8
9 to 16
1 to 16
1 to 8
B2 and B1 specify whether the external character
generator is used. BO specifies whether 2-byte codes
are used.
B2
B1
o
0
1
0
o
1
Function
Internal character generator is used
External character generator is used
Internal and external character
generators are used; if a code is given
corresponding to characters in both,
the internal character generator has
priority.
BO = 0 2-byte codes not used
= 1 2-byte codes used
MEMSIZ
I
I
o
o
o
Parameters
• Character code memory (lines)
• Character code memory (bytes)
(L)
(H)
• Character attribute memory (bytes)
(L)
(H)
• Graphics memory (bytes)
(L)
(H)
Function. This command specifies the size of each
display memory. If a memory is not required, set O.
To determine the required memory size for 1-byte
codes, use the following formula:
MR
MB/R
=
where
MR is the number of character code memory rows
MB is the number of character code memory bytes
R is the number of characters per row.
For 2-byte codes, multiply the right side of the equation by 2.
MEMADR
I
I
o
o
Parameters
• Refresh memory starting address
(L)
(H)
• Character code memory starting address
(L)
(H)
• Character attribute memory starting address
(L)
(H)
• Graphics memory starting address
(L)
(H)
Function. This command specifies the start address
of each display memory. If a memory is not required,
set FFFFH.
6-49
NEe
IJPD72030
Function Specification Commands
START
DISPLY4
This command releases the STOP mode when the
display is OFF, interrupts command input, and clears
the data bus.
This command modifies the fixed row of refresh
memory according to the contents of display memory.
The fixed row is specified by the DIVIDU, DIVIDD, and
DIVIDB commands. If DIVIDN is executed or the
fixed row is modified to a different portion of display
memory, DISPLY4 cannot be used. (Use DISPLY1.)
STOP
This command turns the ",PD72030 oscillator off.
While the oscillator is off, data is retained with low
power consumption. When a DRAM is used, STOP will
destroy data in display memory.
The START command releases the STOP state. Once
released, the oscillator requires an oscillation stabilizing time that has the same length as the blinking
interval.
.
BLANK
This command stops display operation and turns the
display off.
DISPL
o
STOP2
This command functions like the STOP command except that the external clock is input.
DISPLY1
I
1
I
0
I
0
I
0
I
0
I
0
I
0
If the display is OFF, this command modifies refresh
memory according to the contents of display memory
and turns the display ON. If the display is ON, refresh
memory is modified without turning the display off.
DISPLY2
Use this command after execution of BLANK, STOp,
or STOP2 to return the display screen to the condition
that existed before BLANK, STOp, or STOP2 was executed. DISPLY2 modifies refresh memory according
to the contents of display memory and starts the
display function.
DISPLY3
This command displays the contents of display
memory unchanged.
6-50
I
0
This command updates the row where the cursor exists and moves the cursor to the leftmost position of
the next row. If in graphics mode, the internal cursor
position is moved.
NEe
I-lPD72030
Display Control Commands
CURSOR
MODEC,MODEG,MODEM
I
These commands specify the display mode, as
follows:
Command Mode _D_i_sp_l_a_y_M_o_d_e_ _ _ _ _ __
MODEC
01
Character display mode (default)
MODEG
10 Graphics display mode
MODEM
11
Mixed (character/graphics) mode
If the display is ON, the display screen is changed to
the specified mode. If MODEC is selected, refresh
memory is cleared to 0 before refresh memory is updated. When the display mode is specified and display
memory has not been specified, the contents of the
addresses starting from FFFFH are displayed. (This
proceeds from address FFFFH, to address 0, address
1, ...)
BLlNKO·3
TS1
TSO
These commands specify four different blinking intervals, as follows:
Command
BUNKO
BLlNK1
BLlNK2
BLlNK3
TS1
-
0
0
1
1
TSO Interval Time
0 218 X 15/fosc (default)
1 217 X 15/fosc
0 216 X 15/fosc
1 215 X 15/fosc
DSPPOS
I
1
I
1
I
I
0
I
0
0
I
0
I
I
0
I
0
Parameter
I
0
I
0
I
0
I
P
0
B
I
Function. This command specifies the cursor type
and whether blinking is to be used. These are
specified as follows:
P= 0
= 1
B
0
= 1
=
Underline cursor
Block cursor
Blinking off
Blinking on
The default is the underline cursor with blinking off.
This cursor is one pixel thick, immediately below the
character or space, its length that of the character
plus the gap between the characters. The block cursor is the size of the character plus the gap. When the
block cursor overlaps a character, the light and dark
areas of the character are reversed.
CURON
o
I
1
I
0
I
0
I
0
I
0
This command sets the mode for cursor display on
the screen. In display-ON character mode or displayON mixed mode, CURON displays the cursor by
writing to refresh memory. The default setting is for
the cursor to be displayed.
CUROFF
I
0
I
0
I
0
I
0
Parameter
Display start position (row)
Function. This command specifies the row in
character code memory where the display starts. The
default is O.
o
o
I
0
I
0
This command sets the mode for no display of the cursor. In display-ON character mode or display-ON
mixed mode, CUROFF turns the cursor off by modifying refresh memory.
6-51
NEe
J.(PD72030
CURHM
CURUp, CURDN, CURRT, CURLT
I I I I I I
0
0
B1
0
BO
This command shifts the cursor up, down, left, or
right. The commands and their respective shift direc·
tions are as follows:
Command
-
B1
Direction
BO
-Up
0
0
0
CURUP
CURDN
CURRT
CURLT
Down
Right
Left
1
0
1
1
1
o
o
o
o
This command moves the cursor to leftmost edge.
LF
I
0
o
o
I
o
0
When the cursor is displayed, this command moves
the cursor to the home position (upper left corner of
the screen). If the fixed ro':N is set, the cursor will be
at the upper left corner in the manipulating region,
not on the fixed row. When the cursor is not displayed,
it will be moved and displayed in the next display
mode.
o
I
1
I
0
o
0
'1
o
Parameters
• Column position (X)
• Row position (Y)
Function. When the cursor is displayed, this com·
mand moves the cursor to a specified location (col·
umn X in row V). When the cursor is not displayed, it
will be moved and displayed in the next display mode.
CR
0
o
0
CURDR
When the cursor is displayed, these commands shift
the cursor as specified. When the cursor is not
displayed, it will be shifted and displayed in the next
display mode. Table 1 describes what happens when
the cursor is at the screen edge and one of these com·
mands instructs the cursor to move outward.
I
I I
,...... '
o
When parameters exceeding the number of rows or
columns are input, the address will be calculated
assuming the specified location exists. The cursor will
then be moved.
The default is home position (0, 0).
This command moves the cursor down one line.
DIVIDU, DIVIDD
BS
I
0
o
o
o
o
o
0
o
0
B1
BO
Parameters
This command moves the cursor left one character.
Table 1.
I I I
Cursor Movement at Screen Edge
Instruction
Function
CURUP at the highest row
Cursor does not move.
CURDN/LF at the lowest row
Screen scrolls and cursor moves
down one row, remaining in the
same column.
CURRT at rightmost edge in the
highest row
Cursor moves to the leftmost
edge in the next lower row.
CURRT at rightmost edge in the
lowest line
Screen scrolls and cursor shifts
to the leftmost edge of the next
row.
CURLT/BS at the leftmost edge
Cursor moves to the rightmost
edge in the preceding row.
CURLT/BS at leftmost edge in the
highest row
Cursor does not move.
• Character code memory fixed row
(L)
(H)
• Character attribute memory fixed row
(L)
(H)
Function. These commands specify the fixed row,
which is a portion of refresh memory the user can
allocate in order to modify parts of refresh memory
without the whole display being updated. A fixed row
corresponds to one line on the display screen.
B1 and BO are specified as follows:
Command
B1
BO
DIVIDU
0
1
DIVIDD
o
Function
Use upper fixed row (see
DIVIDB)
Use lower fixed row
If character attribute memory is not used, set FFFFH
for the character attribute fixed row (L, H).
6-52
t\'EC
!-,PD72030
Display Data Manipulation Commands
DIVIDe
o
o
o
CHRDSP
Parameters
Parameter
• Character code'
• Character code memory upper fixed row
(L)
(H)
(L)
• Character code (when in 2-byte code mode)
• Character code memory lower fixed row
(H)
(L)
(H)
Function. This command simultaneously displays a
character (at the cursor location) and stores its display
code in memory. The character code is input as a command, thus AO = 1.
• Character attribute memory upper fixed row
(L)
(H)
• Character attribute memory lower fixed row
(L)
(H)
Function. This command is used when both upper and
lower fixed rows are used, for the purpose of partitioning the screen. If character attribute memory is not
used, set FFFFH for the character attribute memory
upper and lower fixed rows (L, H).
The default is that upper and lower fixed rows are not
set.
DIVIDN
I I
o
o
o
o
This command invalidates t.he upper and lower fixed
rows.
In 2-byte code mode, AO must be 1 so that the lower
byte of the character code will be sent to the command buffer and AO = 0, when the higher byte of the
character code is sent to the data buffer.
In display-ON graphics mode or display-OFF mode,
only the code will be written to character code
memory. When in display-ON character mode or mixed mode, the cursor will shift one character to the
right when the display and writing are done. When the
cursor is at the rightmost edge of a row, it will move
to the leftmost edge of the next row. If the cursor is
at the rightmost edge in the lowest row, the screen
will scroll.
ESC
o
o
This command selects whether the input to the command buffer will be the command code or the external character generator code. The default is the command code, and the code selected toggles each time
ESC is executed. Codes 1B, 08, OA and 00 will not be
accepted as character codes.
6-53
NEe
J..'PD72030
ATTR
I
1
BLKTOT
I
0
0
I
0
0
I
1
Parameters
Parameter
I
S
C
U
R
B
I s I c
0
0
I
0
I
u
R
I
B
I
Space (when the character does not exist)
Carriage return (logical row end)
Underline
Reverse
Blink
• Display memory address
(L)
(H)
Function. This command performs data block transfer
from display memory to the data bus buffer. The address will increment each time a byte transfers. The
DMA controller is used.
Function. When a display character appears at the
cursor location, ATTR specifies an attribute for the
character and writes the attribute to attribute memory.
Once specified, the attribute will apply to every subsequent character that is input, until another attribute
is specified, or the ATTROF command is executed.
The ",PD72030 enters the command wait state after
the block transfer finishes.
Any attribute can be specified by setting its bit to 1.
Two or more attributes can be specified
simultaneously.
Parameters
I
0
o
o
I
1
I
0
o
This command releases any attributes specified for
the character at the cursor location.
BLKTIN
o
o
Parameter
• Display memory address
(L)
(H)
Function. This command performs data block transfer
from the data bus buffer to display memory. The address will increment each time a byte transfers. The
DMA controller is used.
If the display is ON, executing BLKTIN to other than
refresh memory causes no change in the display. To
display the written contents of display memory, execute DISPLY1.
The ",PD72030 does not enter the command wait state
after the block transfer finishes.
6-54
• Display memory address
• Number of transfer bytes
ATTROF
1
o
(L)
(H)
The default is that all attributes are off.
I
READ
Function. This commands reads data from display
memory and transfers the specified number of bytes
via the data FIFO to the data bus buffer. The address
increments each time a byte transfers.
If the host CPU does not accept all transfer data
bytes, the ",PD72030 cannot enter the command wait
state.
NEe
JAPD72030
WRITE
CLRCHR
o
o
o
Parameters
Parameters
• Display memory address
• Data
• Data (for 2-byte code mode only)
(L)
(H)
Function. This command replaces character code
memory with the specified data. If character attribute
memory exists it is simultaneously cleared by O.
• Number of transfer bytes
• Write data
• Write data
•
•
•
In display-ON character mode or mixed mode, the
display turns off, refresh memory is modified, and the
display turns on again. The character display start
position is initialized.
• Write data (max 256)
Function. This command writes data for the number
of transfer bytes from the data bus buffer to display
memory. The address increments each time a byte
transfers. If 0 is input c;lS the number of transfer bytes,
256 is assumed.
If the display is ON, executing WRITE to other than
refresh memory causes no change in the display. Execute DISPLY1 to display the written contents.
In display-ON graphics or display-OFF modes, only
character code memory is altered. The boundaries of
character code memory are initialized.
If character code memory is cleared by 20H or 2121H
and attribute memory exists, attribute memory will be
cleared by 40H (the space attribute is attached). The
cursor will move to home position.
If character code memory is not specified, CLRCHR
will not execute and the WARNING bit will be set.
If during WRITE execution the host CPU does not
send the full number of transfer data bytes, the
IiPD72030 cannot enter the command wait state.
CLRGRP
SELCTO, SELCT1
I
I I I
o
0
o
BO
When using a partitioned matrix, two refresh
memories are required. When refresh memory is to be
accessed, these commands specify refresh memory
oor 1. The default is refresh memory O. Once a refresh
memory is specified, it remains valid until the next
specification.
Command
BO
SELCTO
SELCT1
0
1
o
Selects
1
I
o
Parameter
• Data
Function. This command replaces graphics memory
with the specified data.
In display-ON graphics mode or mixed mode, the
display turns off, refresh memory is modified, and the
display turns on. In character display-ON and -OFF
modes, only graphics memory is modified.
If graphics memory is not specified, CLRGRP will not
execute and the WARNING bit will be set.
Refresh memory 0
Refresh memory 1
SELCTCG
I
0
I
Parameters
I
0
0
LA18
LA17
LA16
Function. This command will permit access to the external character generator memory. When a READ,
WRITE, BLKTIN, or BLKTOT is executed, CGEN output goes high and the upper 3-bit address specified
by the parameter is used.
6-55
NEe
I-lPD'7203·0
TRANS
CLRLN
o
o
o
Parameters
Number of transfer characters
Function. This command sends the character code of
each of the specified number of characters to the data
bus buffer, beginning with the character at the cursor location. For each character, the character code
and then' the attribute code, ifit exists, is sent. For
2-byte codes, the charactercode is sent from the lower
to the higher bits. The number of characters to be
transferred is specified as follows:
otransfers up to the logical row end (up to the location wh,ere the CR attribute is set); 0 cannot be
specified if attribute memory has not been
specified
o
o
o
o
This command clears character code memory from
the cursor position to the right edge of the row. When
character attribute memory exists, attribute memory
will be cleared by 40H. The cursor does not move.
When 1-byte code is used, character code memory will
be cleared by 20H. For 2-byte code, character code
memory will be cleared by 2121H. Attribute memory
should be set to the space attribute state (cleared by
40H).
In display-ON graphics and display-OFF mode, only
character code memory is cleared depending on the
cursor position and character code display start position stored in the controller.
FFH transfers up to the physical row end (up to the
right edge of the screen.)
When character code memory is omitted, the calculation of the character code memory address will be
made assuming character code memory starts from
address FFFFH.
1 to FEH transfers up to the specified number of
characters.
CLRFRM'
In display-ON graphics or character display-OFF
mode, the character code is transferred to the data
bus buffer with an address that is calculated based
on the cursor location and the character code start
position stored in the controller.
If character code memory has not been specified,
TRANS will not execute and the WARNING bit will be
set.
o
o
o
This command clears character code memory from
the cursor location to the right edge of the last row.
In display-ON mode, refresh memory is also cleared.
If character attribute memory exists, it is cleared by
40H. The cursor does not move.
When 1-byte code is used, character code memory is
cleared by 20H. For 2-byte code, character code
memory is cleared by 2121H. Attribute memory should
be set to the space attribute state, cleared by 40H.
In display-ON graphics and display-OFF mode, only
character code memory is cleared, depending on the
cursor position and character code display startposition stored in the controller.
If character code memory has not been specified,
character code memory will be cleared beginning
from address FFFFH.
6-56
NEe
J-lPD72030
COMP
DRESET, DSET
I
o
0
I
80
0
Parameter
Parameters
• Pixel position in column direction
• Pixel position in column direction
o
(L)
(H)
(L)
(H)
• Pixel position in row direction
• Pixel position in row direction
(L)
(H)
(L)
(H)
Function. These commands reset or set a pixel at a
specified coordinate on the screen. These commands
manipulate only graphics memory.
Command
80
DRESET
DSET
0
1
Operation
Reset
Set
The coordinate location is specified according to the
number of pixels in the column and row positions. If
the specified location is outside the screen, data in
an unexpected location will be reset or set. DISPLY1
will display the updated contents of graphics memory.
Function. This command reverses a pixel at a
specified coordinate on the screen. COMP manipulates only graphics memory. If the specified location
is outside the screen, data in an unexpected location
will be reversed. DISPLY1 will display the updated contents of graphics memory.
If graphics memory has not been specified, COMP will
execute assuming graphics memory starts from address FFFFH.
If graphics memory has not been specified, DRESET
or DSET will execute assuming graphics memory
starts from address FFFFH.
GET
o
o
Parameters
• Pixel position in column direction
(L)
(H)
• Pixel position in row direction
(L)
(H)
Function. This command sends data that tells
whether the pixel at the specified coordinate on the
screen is set or reset in graphics memory. If the pixel
is set, FFH is sent to the data bus buffer. If reset, 0
is sent to the data bus buffer.
If graphics memory has not been specified, GET will
execute assuming graphics memory starts from address FFFFH.
6-57
",PD72030
6-58
NEe
NEe
DEVELOPMENT TOOLS
7-1
IE
DEVELOPMENT TOOLS
NEe
Section 7 - Development Tools
pPD7500 Series Hardware Development Tools .................................. 7-3
pPD7500 Series Hardware Development Tool Selection Guide ................. 7-3
EVAKIT-7500B ............................................................. 7-4
pPD75000 Series Hardware Development Tools ................................. 7-7
EVAKIT-75X ............................................................... 7-7
pPD7800 Series Hardware Development Tools .................................. 7-9
pPD7800 Series Hardware Development Tool Selection Guide ................. 7-9
EVAKIT-87AD .............................................................. 7-9
EVAKIT-87LC ............................................................. 7-10
IE-7809-M ................................................................ 7-11
IE-87AD-M ................................................................ 7-11
IE-7811H-M ............................................................... 7-12
IE-78C11-M ............................................................... 7-12
pPD78000 Series Hardware Development Tools ..... '" '" ..................... 7-15
IE-78310-R ................................................................ 7-15
pPD70320/322 Hardware Development Tools .................................. 7-17
IE-70322 .................................................................. 7-17
pPD8048 Series Hardware Development Tools ....................... '" ., .... , 7-19
EVAKIT-84C-1 ............................................................ 7-19
EVAKIT-80C42 ............................................................ 7-19
EV-9001/EV-9002 .......................................................... 7-20
SE-80C50H System Evaluation Board. '" ................. , ................. 7-20
V-Series Hardware Development Tools ...................................... ,. 7-21
IE-70108/70116 ............................................................. 7-21
pPD7500 Series Software Absolute Assembler Development Tools .............. 7-23
ASM75 ................................................................... 7-23
pPD75000 Series Software Relocatable Assembler Development Tools .......... 7-25
RA75X .................................................................... 7-25
pPD7800 Series Software Absolute Assembler Development Tools .............. 7-27
ASM87 ................................................................... 7-27
pPD7800Series Software Relocatable Assembler Development Tools ........... 7-29
RA87 ..................................................................... 7-29
pPD78000 Series Software Relocatable Assembler Development Tools .......... 7-31
RA310 .................................................................... 7-31
pPD70320/322 Software Relocatable Assembler Development Tools ............ 7-33
Evakit Communication Program ......... " ........... , .... , .... " ... , .... , ... 7-35
MD-086 Series Microcomputer Development Systems ......................... 7-37
MD-086 Floppy and Hard Disk Drive System ................................ 7-37
MD-910TM Character Display Terminal Development Tool ...................... 7-43
PG1000 PROM Programmer ............. " ............................. , ..... 7-45
7-2
NEe
NEe Electronics Inc.
pPD7500 SERIES
HARDWARE
DEVELOPMENT TOOLS
Introduction
NEC has a comprehensive line of development hardware and software supporting our many families of
single-chip microcomputers. NEC's software operates
under CPM-86™ or MS-DOSTM, and will run on a variety
of hardware including IBM-PCTM, NEC-APC, and the
NEC MD-086 multiuser development system. Generally, an NEC cross-assembler will assemble all members
of a series.
NEC hardware is divided into two types: Evakits and IE
boards. Evakits are mother boards. They accept plugin daughter boards that emulate speci.fic microcomputers. IE boards are in-circuit emulators. They
generally have more memory and more functionality
than the specific device they emulate. Both types of
hardware come with up/down load software that allows
communication with the host computer over a serial
line.
Following is an example of configuring a system for
developing the pPD7533 single-chip microcomputer.
The selection guide below shows that the pPD7533
requires a mother board, the EVAKIT-7500B, and a
daughter board, the EV7533, which personalizes the
mother board for the pPD7533.
For software development, you first select the host
computer and operating system. USing the most popular module, the IBM-PC type running under MS-DOS,
as an example, you would need ASM75:-D52. This assembler works for all 7500 series members, and
includes up/down loading software.
In addition to these development tools, you would
need somepPD75CG33E piggyback prototyping chips.
And voila, you have a low-cost development system
that can be configured by adding daughter boards for
other members of the family as new applications
emerge.
pPD7500 Series Hardware Development Tool Selection Guide
Part
Number
Emulator
Add-On Board
(Required)
System
Evaluation Board
JlPD7501
JlPD7502
EVAKIT-7500B
EV7514
SE-7514A
EVAKIT-7500B
EV7514
SE-7514A
JlPD7503
EVAKIT-7500B
EV7514
JlPD7506
EVAKIT-7500B
JlPD7507
EVAKIT-7500B
JlPD7507H
EVAKIT -7500B
JlPD7507S
EVAKIT-7500B
JlPD7508
EVAKIT-7500B
JlPD7508A
EVAKIT-7500B
JlPD7508H
EVAKIT-7500B
EV7508H
JlPD7514
EVAKIT-7500B
EV7514
EPROM
Device
SE-7514A
SE-7508
JlPD75CG08E
EV7508H
JlPD75CG08HE
SE-7508
JlPD75CG08E
SE-7508
JlPD75CG08H E
SE-7514A
JlPD7516H
EVAKIT-7500B
EV7500FIP
JlPD75CG16HE
JlPD7519
EVAKIT-7500B
EV7500FIP
JlPD75CG19E
JlPD7519H
EVAKIT-7500B
EV7500FIP
JlPD75CG19HE
JlPD7527
EVAKIT-7500B
EV7528
JlPD75CG28E
JlPD7528
EVAKIT-7500B
EV7528
JlPD75CG28E
JlPD7533
EVAKIT-7500B
EV7533
JlPD75CG33E
JlPD7537
EVAKIT-7500B
EV7528
JlPD75CG38E
JlPD7538
EVAKIT-7500B
EV7528
JlPD7554
EVAKIT-7500B
EV7554A
SE-7554A
JlPD7556
EVAKIT-7500B
EV7554A
SE-7554A
JlPD7564
EVAKIT-7500B
EV7554A
SE-7554A
JlPD7566
EVAKIT-7500B
EV7554A
CP/M-86 is
a trademark of Digital Research Corporation.
JlPD75CG38E
SE-7554A
MS-DOS is a trademark of Microsoft Corporation.
IBM-PC is a trademark of International Business Machines Corporation.
7-3
E
ttfEC
pPD7500 SERIES
EVAKIT-7500B
o
Supports three operating modes
- On-board hexadecimal keypad controlled
- External terminal controlled
- Host computer system controlled
o Serial interface: RS-232C or TTL
D EPROM programming capability (2764 and 27128)
EV7500 Add-On Boards
EV7500FIP
Description
The EVAKIT-7500B is a stand-alone Evakit for NEC's
pPD7500 series of 4-bit, single-chip microcomputers.
The EVAKIT-7500B provides complete hardware emulation and software debug capabilities for the
pPD7506, pPD750717507S and the pPD750817508A
microcomputers. With the addition of device specific
add-on boards, the EVAKIT -7500B is easily tailored to
support the remaining members of the family.
Real-time and single-step emulation capability, coupled
with a powerful on-board system monitor and real-time
trace capability create a powerful debug environment.
The EVAKIT-7500B is controlled either from an onboard keypad or over a serial line from a terminal or
host computer. User programs are downloaded through
a serial line or read from a PROM. Existing programs
may be modified or small programs may be created
using the on-board hexadecimal keypad.
The EV7500FIP is an add-on board for the EVAKIT7500B which is required for emulating the pPD7516H
and the pPD751917519H microcomputers. This board
is mounted under the EVAKIT-7500B, adding vacuum
fluorescent display control and high voltage driver
capability to the Evakit.
EV7508H
Features
D Real-time and single-step emulation capability
o 8K bytes of user program memory
D Powerful system monitor
- Display/modify/move program memory
- Display/modify data memory
- Load/verify/display PROM
- Examine/modify internal registers
- Full disassembler
o User-specified breakpoint conditions
- Program counter and number of passes
- Stack pOinter
- Data address and value
D Real-time trace capability
- 2048 instruction cycle trace
- External trace probes
7-4
The EV7508H is an add-on board for the EVAKIT7500B which is required for emulating the pPD7507H
and the pPD7508H microcomputers. This board plugs
directly into the pPD7500 socket on the EVAKIT7500B, allowing the system to support these high
speed versions of the pPD7500 series.
NEe
EV7514
pPD7500 SERIES
EV7554A
The EV7554A is an add-on board for the EVAKIT7500B which is required for emulating the pPD7554,
pPD7556, pPD7564, and pPD7566 microcomputers.
This board mounts on top of EVAKIT-7500B, allowing
the Evakit to emulate the additional features of these
parts: optional pull-up/pull-down resistors for ports 0,
1,10, and 11; comparator/CMOS inputs for port 1; high
current/CMOS outputs for ports 8, 9, 10, and 11.
pPD7500 Series System Evaluation
Boards
The EV7514 is an add-on board for the EVAKIT -7500B
which is required for emulating thepPD7501 ,pPD7502,
pPD7503, and pPD7514 microcomputers. This board is
mounted under the EVAKIT-7500B, adding LCD controller/driver capability to the Evakit.
EV7528
SE-7S08
The SE-7508 is the system evaluation board for the
pPD7506, pPD7507S, and pPD7508A microcomputers.
The SE-7508 is functionally equivalent to the ROMbased microcomputers. With the user's program
residing in either a pPD2716 or pPD2732 on board, the
SE-7508 can be connected to the user's prototype
allowing total system performance to be evaluated.
SE-7514A
The EV7528 is an add-on board forthe EVAKIT-7500B
which isrequired for emulating thepPD7527,pPD7528,
pPD7537, andpPD7538 microcomputers. This board is
mounted under the EVAKIT-7500B, allowing the Evakit
to support the additional features of these parts: I/O
ports with high dielectric strength, optional pull-down
resistors, and zero voltage detection circuits.
EV7533
The EV7533 is an add-on board for the EVAKIT-7500B
which is required for emulating the pPD7533 microcomputer. This board plugs directly into the pPD7500
socket, allowing the Evakit to emulate the pPD7533's
four analog inputs and its 8-bit A/D converter.
The SE-7514A is the system evaluation board for the
pPD7500 series microcomputers with LCD direct drive
capabilities: pPD7501, pPD7502, pPD7503 and
pPD7514. The SE-7514A is functionally equivalent to
the ROM-based microcomputers. With the user's program residing in either an on-board pPD2764 or
pPD27128, you can connect the SE-7514A to your
prototype and evaluate total system performance.
SE-7554A
The SE-7554A is the system evaluation board for the
pPD7500 series mini/microcomputers: pPD7554,
pPD7556, pPD7564, and pPD7566. The SE-7554A is
functionally equivalent to the ROM-based mini/microcomputer. With your program residing in the lower 4K
bytes of an on-board pPD2764, you can connect the
SE-7554A to your prototype and evaluate total system
performance.
7-5
E
pPD7500
7-6
NEe
NEe
NEe Electronics Inc.
pPD75000 SERIES
HARDWARE
DEVELOPMENT TOOLS
EVAKIT·75X
EVAKIT-75X Add-On Boards
Description
EV75108
The EVAKIT-75X is a stand-alone Evakit for NEC's
pPD75000 series of 4-bit, single-chip microcomputers.
With the addition of a device specific add-on board, the
EVAKIT-75X is easily tailored to provide complete
hardware emulation and software debug capabilities
for the individual members of the family. Real-time and
single step emulation capability, coupled with an onboard system monitor, create a powerful debug
envi ron ment.
The EV75108 is an add-on board for the EVAKIT-75X
required for emulating the pPD75104, pPD75106, and
pPD75108 microcomputers. This board mounts on top
of the EVAKIT-75X, allowing the Evakit to support the
features specific to these parts. This includes switch
selectable pull-up resistors on ports 12,13, and 14.
The EVAKIT-75X is controlled over a serial line from
either a terminal or host computer. User programs can
be downloaded through this serial line or read from
PROM. The NEC PG1000 series PROM programmer
with the PG1005 personality module can be connected
for easy programming of the pPD75P105.
Features
o Real-time, real-time step, and Single step emulation
o 16K bytes of program memory (72 hour backup)
o Powerful on-board system monitor
-
o
o
\
o
o
o
o
o
o
Display/modify/move/exchange/search/verify
program memory
- Display/modify/move/exchange/verify data
memory
- Display/modify general and special registers
- Upload/download data
- Line-assembler and full disassembler
- Load/verify/display PROM
User-specified breakpoints
- Logical OR of up to four break conditions
- Break loop counter
- Delayed break by machine cycle or instruction
count
Real-time trace capability
- 512 machine cycle or2048 instruction cycle trace
- User-specified trace range
- Trace data search function
Automatic command string execution
Eight external sense probes
Controlled from external terminal or host computer
Two RS-232C serial ports
On-board EPROM programmer (2764 and 27128)
Upload/download program for PG1 000/PG1 005
PROM programmer
EV75208
The EV75208 is an add-on board for the EVAKIT-75X
which is required for emulating the pPD75204,
pPD75206, andpPD75208 microcomputers. This board
mounts on top of the EVAKIT-75X, allowing the Evakit
to support the features specific to these parts including
the FIP Controller/Driver.
PG1000 Personality Module
PG1005
The PG1005 is a plug-in personality module for the
PG1000 PROM Programmer. This module is required
to program thepPD75P108, the EPROM version forthe
pPD75104, pPD75106, and pPD75108 4-bit, single-chip
microcomputers. Interchangeable socket adapters are
provided with the PG1005 to allow programming both
shrink dip and flat packages.
7-7
pPD75000
7-8
NEe
t-{EC
pPD7800 SERIES
HARDWARE
DEVELOPMENT TOOLS
NEe Electronics Inc.
pPD7800 Series Hardware Development Tool Selection Guide
Part
Number
Emulator
Real-time
Trace
Board
Add-on
Board
System
Evaluation
Board
EPROM
Device
IlPD78C05A
EVAKIT-87LC [Note 1]
EV87LCRTT
EV78C06A
SE-78C06
IlPD78C06A
EVAKIT-87LC
EV87LCRTT
EV78C06A
SE-78C06
IlPD7807
IE-7809-M
IlPD78P09R
IlPD7808
IE-7809-M
IlPD78P09R
IlPD7809
IE-7809-M
IlPD7810
EVAKIT-87AD [Note 1]
IE-87AD-M
IlPD7810H
IE-7811H
IlPD78C10
IE-78C11-M
IlPD7811
EVAKIT-87AD [Note 1]
IE-87AD-M
IlPD7811H
IE-7811H
IlPD78C11
IE-78C11-M
IlPD78 C14
IE-78C11-M
IlPD78P09R
EV87ADRTT
EV87ADRTT
IlPD78PG11E
IlPD78PG11E
IlPD78PG11E [Note 2]
Notes:
(1) Addresses O-OFFFH access memory on the Evakit only.
(2) Special selected parts.
EVAKIT·87AD
Description
The EVAKIT-87 AD is one of the stand-alone Evakits for
NEC's pPD7800 series of 8-bit, single-chip microcomputers. The EVAKIT-87AD provides complete
hardware emulation and software debug capabilities
forthepPD7811 microcomputer. Real-time and singlestep emulation capability, coupled with an on-board
system monitor, creates a powerful debug environment. An optional real-time trace board is also available
to greatly increase your debugging capabilities.
An auxiliary hexadecimal keypad or a serial line from a
terminal or host computer controls the EVAKIT-87AD.
User programs are downloaded through a serial line or
read from a PROM. Use the keyboard to modify
existing programs or create small programs. An onboard programmer for 2716, 2732, 2732A, or 2764
EPROMs provides an easy means for submitting your
final code for production.
Features
D Real-time and single-step emulation capability
o 8K bytes of on-board user program memory
-
Expandable to 64K bytes using IEEE-796 bus
o Powerful system monitor
-
Display/modify/move/search/verify/test
Memory
- Display/modify internal registers
- Display input ports; write to output ports
- Load/verify/display PROM
- Full disassembler
D User-specified breakpoint
- One serial (logical AND of up to 4 conditions) or
- One parallel (logical OR of up to 15 conditions)
- Break delay and loop counter
- Break on: address and data values and CPU
controls
o Supports three operating modes
- Auxiliary hexadecimal keypad controlled
- External terminal controlled
- Host computer system controlled
D Serial interface: RS-232C, TTL, or 20 rnA current
loop
o EPROM programming capability (2716, 2732,
2732A, 2764)
7-9
7
NEe
pPD7800 SERIES
EVAKIT·87AD Add·On Board
Features
EV87ADRTT
D Real-time and single-step emulation capability
o 4K bytes of on-board user program memory
- Expandable to 64K bytes using the IEEE-796 bus
o Powerful system monitor
- Display/modify/move/exchange/search/verify/
test memory
- Display/modify internal registers
- Display input ports; write to output ports
- Load/verify/display PROM
- Full disassembler
D User-specified breakpoint
- One serial (logical AND of up to 4 conditions) or
- One parallel (logical OR of up to 15 conditions)
- Break delay and loop counter
- Break on: address, memory read/write, opcode
fetch
o Three modes of operation
- Auxiliary hexadecimal keypad controlled
- External terminal controlled
- Host computer system controlled
D Serial interface: RS-232C, TTL, or 20 mA current
loop
o EPROM programming capability (2716, 2732)
The EV87ADRTT is the real-time trace board for use
with NEC's EVAKIT-87AD stand-alone Evakit. The
EV87ADRTT communicates with the EVAKIT-87AD
via the IEEE-796 bus, adding real-time trace and
additional breakpoint capabilities to the Evakit. A 1K X
62-bit trace RAM is available for storing the status of
the address bus, the data bus, the control signals, and
the I/O ports as your program is executed in real-time.
The trace data may be displayed in either the machine
cycles or the instruction mode with the user control Iing
the content of the display. The addition of another
address breakpoint, a timer breakpoint, and a trace
step breakpoint greatly increase the power of the
EVAKIT -87 AD.
EVAKIT·87LC
Description
The EVAKIT-87LC is one of the stand-alone Evakits for
NEC's J.lPD7800 series of 8-bit, single-chip microcomputers. The EVAKIT -87LC provides complete
hardware emulation'and software debug capabilities
for theJ.lPD78C06 microcomputer. With the addition of
the EV78C06A add-on board, the EVAKIT -87LC supports the J.lPD78C06A. Real-time and single-step
emulation capability, coupled with an on-board system
monitor, create a powerful debug environment.
An auxiliary hexadecimal keypad or a serial line from a
terminal or host computer controls the EVAKIT -87LC.
User programs are downloaded through a serial line or
read from a PROM. Existing programs may be modified
or small programs may be created using the keypad.
An on-board programmer for 2716 or 2732 EPROMs
provides an easy means for submitting the user's final
code for production. An optional real-time trace board
is available to greatly increase your debugging capabilities.
EVAKIT·87LC Add·On Boards
EV87LCRTT
The EV87LCRTT is the real-time trace board for use
with NEC's EVAKIT-87LC stand-alone Evakit. The
EV87LCRTT communicates with the EVAKIT-87LC via
the I EEE-796 bus, adding real-time trace and additional
breakpoint capabilities to the Evakit. A 1K X 59 bit trace
RAM is available for storing the status of the address
bus, data bus, control signals, I/O ports and ten
external sense lines, as the user's program is executed
in real-time. The trace data may be displayed in
machine cycles or instruction mode with the user
controlling the content of the display. The addition of
another address breakpoint, a timer breakpoint, and a
trace step breakpoint greatly increases the power of
the EVAKIT-87LC.
EV78C06A
The EV78C06A is an add-on board for the EVAKIT87LC which is required for emulating the J.lPD78C06A
microcomputer. This board is connected between the
Evakit and the target system, dividing the clock output
of the Evakit by two. An emulation probe with a 64-pin
QUIP header for plugging directly into the microcomputer socket of the target system is included with
the EV76C06A.
7-10
NEC
IE-7809-M
pPD7800 SERIES
o MD-086
series development system bus-coupled
config u ration
- Symbolic debugging
- Macro command file capability
- Multiple IE-7809 operation
- Improved upload/download times
IE-87AD-M
Description
The IE-7809-M is one of the in-circuit emulators for
NEC's pPD7800 series of 8-bit, single-chip microcomputers. The IE-7809-M provides complete hardware emulation and software debug capabilities for the
pPD7807, pPD7808, and pPD7809 single-chip microcomputers. Real-time and single-step emulation capability, coupled with sophisticated memory mapping
features, breakpoints and trace capabilities, create a
powerful debug environment. A single-line assembler
and disassembler, full register and memory control,
and complete upload/download capabilities further
simplify the task of debugging your hardware and
software.
The IE-7809 can operate in two modes: as a standalone in-:-circuit emulator, controlled from either a user
terminal orfrom a wide variety of host systems; or as an
integral part of the MD-086 series microcomputer
development system.
Description
The IE-87AD-M is one of the in-circuit emulators for
NEC's pPD7800 series of 8-bit, single-chip microcomputers. The I E-87 AD-M provides complete hardware emulation and software debug capabilities forthe
pPD7810, and pPD7811 single-chip microcomputers.
Real-time and single-step emulation capability, coupled
with sophisticated memory mapping features, breakpoints, and trace capabilities create a powerful debug
environment. A single-line assembler and disassembler,
full register and memory control, and complete upload/
download capabilities further simplify the task of
debugging your hardware and software.
The I E-87AD-M can operate in two modes: as a standalone in-circuit emulator, controlled from either a user
terminal or from a wide variety of host systems; or as an
integral part of the MD-086 series microcomputer
development system.
Features
o
Real-time and single-step emulation
o User-designated breakpoints
o Sophisticated trace capabilities
- 1024 X 56-bit trace buffer
- Trace conditioning registers
- Instruction or machine cycle display
D Powerful memory mapping capability
- 64K bytes of RAM mappable in 256-byte blocks
o Line assembler/disassembler
o Eight external sense probes
D Self-diagnostic command
o Stand-alone configuration
- User terminal controlled
- Host computer system controlled
7-11
NEe
pPD7800 SER'IES
Features
o
o
o
o
o
o
o
o
o
Real-time and single-step emulation
User-designated breakpoints
Sophisticated trace capabilities
- 1024 X 56-bit trace buffer
- Trace conditioning registers
- Instruction or machine cycle display
Powerful memory mapping capability
- 64K bytes of RAM mappable in 256 byte blocks
Line assembler/disassembler
Eight external sense probes
Self-diagnostic command
Stand-alone configuration
- User terminal controlled
- Host computer system controlled
MD-086 series development system bus-coupled
configuration
- Symbolic debugging
- Macro command file capability
- Multiple IE-87AD,.M Operation
- Improved upload/download times
IE-7811H-M
De~eriptiC)n
The IE,.7811 H-M is one of the in-circuit emulators for
NEG's pPD7800 series of 8-bit, single-chip microcomputers. The I E-7811 H-M provides complete hardware emulation and software debug capabilities for the
pPD7810H andpPD7811 H single-chip microcomputers.
Real-time and single-:-step emulation capability, coupled
with sophisticated memory mapping features, breakpoints, and trace capabilities create a powerful debug
environment. A single-line assembler, disassembler,
full register, memory control, and complete upload/
download capabilities further simplify the task of
debugging your hardware and software.
o Self-diagnostic command
o Stand-alone configuration
o
IE-78C11-M
Descri ption
The IE-78C11-M is one of the in-circuit emulators for
NEG's pPD7800 series of 8-bit, single':'chip microcomputers. The IE-78G11-M provides complete hardware emulation and software debug capabilities forthe
pPD78C10, pPD78C11 and pPD78C14 single-chip
microcomputers. Real-time and single-step emulation
capability, coupled with sophisticated memory mapping features, breakpoints and trace capabilities create
apowerful debug environment. A single-line assembler,
disassembler, full register, memory control, and complete upload/download capabilities further simplify the
task of debugging your hardware and software.
The IE-78C11-M can operate in two modes: asa standalone in-circuit emulator, controlled from either a user
term inal or from a wide variety of host systems; or as an
integral part of the MD-086 series microcomputer
development system.
Features
o
o
o
The I E-7811 H-M can operate in two modes: as a standalone in-circuit emulator, controlled from either a user
terminal or from a wide variety of host systems; or as an
integral part of the MD-086 series microcomputer
development system.
o
Features
o
o Real-time and single-step emulation
o
o
o
o
o
User-designated breakpoints
Sophisticated trace capabilities
- 1024 X 56-bit trace buffer
- Trace conditioning registers
- Instruction or machine cycle display
Powerful memory mapping capability
- 64K bytes of RAM mappable in 256-byte blocks
Line assembler/disassembler
Eight external sense probes
7-12
- User terminal controlled
- Host computer system controlled
MD-086 series development system bus-coupled
configuration
- Symbolic debugging
- Macro command file capability
- Multiple IE-87AD-M operation
- Improved upload/download times
o
o
o
o
Real-time and single-step emulation
User-designated breakpoints
Sophisticated trace capabilities
- 1024 X 56-bit trace buffer
- Trace conditioning registers
- Instruction or machine cycle display
Powerful memory mapping capability
- 64K bytes of RAM mappable in 256 byte blocks
Line assembler/disassembler
Eight external sense probes
Self-diagnostic command
Stand-alone configuration
- User terminal controlled
- Host computer system controlled
MD-086 series development system bus-coupled
configuration
- Symbolic debugging
- Macro command file capability
- Multiple IE-78C11-M operation
- Improved upload/download times
NEe
pPD7800 SERIES
pPD7 800 Series System Evaluation Board
PG1000 Personality Module
SE-78C06
PG1003
The SE-78C06 is the system evaluation board for the
pPD78C06 microcomputer. The SE-78C06 is functionally· equivalent to the ROM-based microcomputer.
With the user's program residing in a pPD2732 onboard, you can connect the SE-78C06 to your prototype, allowing total system performance evaluation.
The PG1003 is a plug-in personality module for the
PG1000 PROM Programmer. This module is required
to program thepPD78P09R, the EPROM version forthe
pPD7808 and pPD7809 8-bit, single-chip microcomputers. The PG1003 supports two programming modes:
high-speed writing mode and normal writing mode.
7-13
.,;..:0
pPD7800·· .
7-14
NEe
NEe
NEe Electronics Inc.
pPD78000 SERIES
HARDWARE
DEVELOPMENT TOOLS
IE·78310·R
Description
The IE-78310-R is the stand-alone in-circuit emulator
for NEC's pPD78000 series of 8-bit, single-chip microcomputers. The IE-78310-R provides complete hardware emulation and software debug capabilities forthe
pPD78310 and pPD78312 single-chip microcomputers.
Real-time and single-step emulation capability, coupled
with sophisticated memory mapping features, breakpoints, and trace capabilities create a powerful debug
environment.
A serial line from either a terminal or a host computer
system controls the IE-78310-R. User programs can be
uploaded or downloaded from the host system or from
a PROM programmer connected to a second serial
line.
Features
o
o
o
Real-time and single-step emulation
- Up to 12 MHz external clock
- Software selectable internal or external clock
Emulation memory
- 16K bytes of high-speed emulation memory for
on-chip ROM
- 64K bytes of emulation memory for external
memory mappable in 256-byte blocks
Powerful system monitor
- Display/modify/move/exchange/search/verify/
test memory
- Display/modify internal registers
- Upload/download capability
- Symbolic line assembler and disassembler
o User-specified breakpoints
-
o
o
o
o
Logical OR of up to 4 conditions
Logical AND of address, data, CPU status, loop
count
- 8-bit external sense probe (bit-maskable)
- Emulation timer - 1 to 65,535 ms
- Program fetch count - 1 to 65,535 steps
Real-time trace capability
- 2048 X 44-bit trace memory
- Traces: address, data, CPU status, ports 0-5,
instruction queue status, macro service status,
external sense probes
- User-specified trace qualifiers: address, data,
CPU status, external sense probes
- Instruction/macro service/frame mode display
Eight external sense probes for tracing user system
signals
Two RS-232C serial ports
On-board self diagnostics
pPQ7800Q
NEe
NEe
NEe Electronics Inc.
pPD70320/322
HARDWARE
DEVELOPMENT TOOLS
PRELIMINARY INFORMATION
IE·70322
o
Description
The IE-70322 is a portable stand-alone in-circuit
emulator providing both hardware emulation and software debug capabilities for the NEC V25 (pPD703201
70322) 16-bit single-chip microcomputers. The standard IE-700K chassis integrates a 9.5 inch CRT display,
two 5-1/4 inch 640 kilobyte floppy disk drives and an
ASCII keyboard. Real-time and single-step emulation
capability, coupled with sophisticated memory mapping features, breakpoints, and trace capabilities create
a powerful debug environment. User programs can be
uploaded and downloaded from a variety of host
systems.
o
o
o
Powerful communication software supporting:
- Digital Equipment Corporation VAX™ computers
- I ntel Series 111111 Development Systems
- IBM Personal Computers
- NEC MD-086 Series Development Systems
Macro command file capability
Full on-line help facility and screen editor
EPROM programmer - 2732, 2764, 27128, 27256,
27512
VAX is a trademark of Digital Equipment Corporation.
Features
o
o
o
o
o
o
o
o
Portable stand-alone in-circuit emulator
- Integrated CRT, floppy disks, keyboard
- Can be upgraded to support V20IV30, V35,
V40IV50, V60
Precise real-time and single-step emulation
- Up to 8 MHz external clock
User-specified mask ROM area of 0 KB, 8 KB, 16 KB
or 32 KB
124 KB of high-speed emulation memory (expandable to 636 KB)
- Mappable in 4K blocks as user, internal or
inhibited
Seven user-specified breakpoints
- Selectable as execution or bus access cycle break
- Break loop counter
Sophisticated real-time trace capability
- 2K trace buffer (sampling every machine cycle)
- Traces: IROM/memory address and data, CPU
status, 16 external sense probes
- User-specified trace qualifiers
Full symbolic debug capabilities
Symbolic line assembler and disassembler
7-17
pPD70320/322
7-18
NEe
t-rEC
pPD8048 SERIES
HARDWARE
NEe Electronics Inc.
EVAKIT-84C-1
DEVELOPMENT TOOLS
EVAKIT-80C42
Description
The EVAKIT-84C-1 is a stand-alone Evakit forNEC's
pPD8048 series of 8-bit, single-chip microcomputers.
The EVAKIT-84C-1 provides complete hardware emulation and software debug capabilities for the
pPD8048H,pPD8049H,pPD80C48,pPD80C49H, and
pPD80C50H microcomputers. Real-time and singlestep emulation capability, coupled with a powerful onboard system monitor, and real-time trace capability
create a powerful debug environment.
An on-board hexadecimal keypad or a serial line from a
terminal or host computer controls the EVAKIT-84C-1.
User programs are downloaded through the serial line
or read from a PROM. Use the keypad to modify
existing programs or create small programs. An onboard programmer for pPD2716, pPD8748, and
pPD8749H EPROM devices provides an easy means for
submitting your final code for production.
Description
Features
o
Real-time and single-step emulation capability
o 4K bytes on-board user program memory
o Powerful on-board system monitor
o
o
o
o
o
Display/modify program memory
Display/modify data memory
Display/modify internal registers
Display input ports; write to output ports
Load/verify PROM
Full disassembler
Real-time trace capability - 256 steps
- Program counter; port 1, 2, or address/data on
data bus
User-specified breakpoints
- One serial (logical AND of up to 15 sequential
addresses)
- Breakpoint loop counter: up to 16 counts
Supports three operating modes
- On-board hexadecimal keypad controlled
- External terminal controlled
- Host computer system controlled
Serial interface: RS-232C, TTL, 20 rnA current loop
EPROM programming capability (2716, 8748, 8749H)
The EVAKIT -80C42 is a stand-alone Evakit for NEC's
pPD80C42 8-bit single-chip microcomputer that provides both complete hardware emulation and software
debug capabilities. Real-time and single-step emulation
capability, coupled with an on-board monitor create a
powerful debug environment.
An auxi'liary hexadecimal keypad or a serial line from a
terminal or host computer controls the EVAKIT-80C42.
User programs are downloaded through the serial line
or read from a PROM. Use the keyboard to modify
existing programs or create small programs. An onboard programmer for the pPD8741A EPROM device
provides an easy means for submitting your final code
for production.
Features
o Real-time and single-step emulation capability
o 2K bytes on-board user program memory
o Powerful on-board system monitor
-
Display/modify/move/search/verify program
memory
Display/modify/move/search/verify data memory
Display/modify internal registers
Read/write to data bus buffer
Display input ports; write to output ports
Load/verify/display PROM
Full disassembler
7-1Q
7
ttiEC
pPD8Q48 SERIES
o
o
o
o
o
Real-time trace capability - 256 steps
- Program counter; DBBIN, DBBOUT, and DBB
status; OBF pin status
User-specified breakpoints
- One serial (logical AND of up to 4 sequential
addresses)
- One parallel (logical OR of up to B addresses)
- Breakpoint loop counter: up to 256 counts
Supports three operating modes
- Auxiliary hexadecimal keypad controlled
- External terminal controlled
- Host computer system controlled
Serial interface: RS-232C and TTL
EPROM programming capability (pPDB741A)
pPD8048 Series Development Tool
Selection Guide
Part
Number
Emulator
pPDB035H
EVAKIT-B4C-1
pPDB04BH
EVAKIT-B4C-1
pPDB039H
EVAKIT-B4C-1
pPDB049H
EVAKIT-B4C-1
pPDBOC39H
EVAKIT-B4C-1
pPDBOC4B
EVAKIT-B4C-1
pPDBOC35
EVAKIT-B4C-1
pPDBOC49H
EVAKIT-S4C-1
pPDBOC40H
EVAKIT-B4C-1
pPDSOC50H
EVAKIT-B4C-1
pPDBOC42
EVAKIT-BOC42
System
Evaluation
Board
EPROM
Device
pPDB74BH*
pPDB749H*
SE-BOC50H
SE-SOC50H
SE-BOC50H
pPDB741A
*pPD8748H and pPD8749H are both available in erasable windowed
packages or in the economical one time programmable plastiC
package.
EV-9001/EV-9002
Description
The EV-9001 and EV-9002 shrink DIP conversion
boards allow the standard in-circuit emulator and
Evakit emulation cables to connect to shrink DIP
sockets. The EV-9001:-64 converts the emulation probe
from a 64-pin QUIP to a 64-pin shrink DIP. The EV9002-42/40/2B convert the emulation cables from 42/40-/2B-pin standard DIP to 42-/40-/2B-pin shrink DIP
respectively.
7-20
Ordering Information
Conversion Board
Function
EV-9001-64
64-pin QUIP to 64-pin shrink DIP
EV-9002-42
42-pin standard DIP to 42-pin shrink DIP
EV-9002-40
40-pin standard DIP to 40-pin shrink DIP
EV-9002-2B
2B-pin standard DIP to 2S-pin shrink DIP
SE-80C50H System Evaluation
Board
The SE-BOC50H isthe system evaluation board for the
following CMOS members of the J.lPDB04B series:
J.lPDBOC4BH,J.lPDBOC49H, and theJ.lPDBOC50H. The
SE-BOC50H is functionally equivalent to the ROMbased microcomputers. You can connect the SEBOC50H to your prototype with up to 4K of your
program residing in an on-board J.lPD2716, J.lPD2732,
J.lPD2732A, J.lPD2764, or a J.lPD27C64. Th is allows total
system performance evaluation.
NEe
NEe Electronics Inc.
V-SERIES
HARDWARE
DEVELOPMENT TOOLS
PRELIMINARY INFORMATION
IE-7010S/70116
Ordering Information
Part Number
Description
IE-70108-S
In-circuit emulator for pPD70108 (with V20 pod)
IE-70116-S
In-circuit emulator for pPD70ll6 (with V30 pod)
IE-70l08-00l
Optional pod unit for jlPD70l08 emulation
IE-70ll6-00l
Optional pod unit for jlPD70ll6 emulation
IE-70ll6-l508
Converts IE-70208/2l6-S008 to IE-70l08/70ll6-S
®CP/M-86 is a registered trademark for Digital Research Corporation.
V25/35 Series Selection Guide
Description
The IE-70108 and IE-70116 are stand-alone in-circuit
emulators that provide both hardware emulation and
software debug capabilities for the NEC jlPD70108
(V20) and jlPD70116 (V30) respectively. Each system
consists of a standard I E-70K chassis with interchangeable emulator pods for either the V20 or V30 microprocessor. The IE-70108170116 provides real-time and
single-step emulation in both native and 8080 emulation
mode. User programs can be uploaded and downloaded from a variety of host systems via a serial link, or
loaded directly from a CP/M-86® format 8" disk.
Part Number
Emulator
jlPD70l08 (V20)
IE-70l08-S
jlPD70ll6 (V30)
IE-70ll6-S
jlPD70208 (V40)
IE-70208-S
jlPD702l6 (V50)
IE-702l6-S
jlPD70320 (V25)
IE-70322
jlPD70322 (V25)
IE-70322
EPROM Device
jlPD70P322
Features
D Stand-alone in-circuit emulator
- Interchangeable emulator pods for V20/V30
- Conversion kit avai lable for I E-70208/70216-S008
Precise real-time and single-step emulation
- 5/8 MHz internal clock
- Up to 8 MHz external clock
D Sophisticated memory mapping in 1K blocks of:
- 64K bytes of no wait state internal RAM
- 127K bytes of one wait state internal RAM
(expandable to 610K bytes)
- Up to 1M byte of user system memory
D User programmable breakpoints and trace control
D 1K trace buffer - mnemonic and cyclic display
o Full symbolic debug capabilities
- 128K memory disk for rapid symbol search
o Symbolic line assembler and disassembler
o Full on-line help facility
o Macro command file capability
o External probes for tracing user system signals
o 1M byte 8" floppy disk drive
o
7-?1
V-SERIES
7-22
NEe
NEe
NEe Electronics Inc.
ASM75
Description
The 7500 series absolute assembler (ASM75) converts
symbolic source code for the entire 7500 series microcomputer family into executable absolute address
object code. The assembler verifies that each instruction assembled is valid for the target microcomputer specified at assembly time. An object code
file is produced in ASCII hexadecimal format and may
be downloaded to a PROM programmer or hardware
debugger.
pPD7500 SERIES
SOFTWARE
ABSOLUTE ASSEMBLER
DEVELOPMENT TOOLS
Ordering Information
ParI Number
ASM75-C81
Description
CP/M-80, 8" single-density floppy diskette
ASM75-D52
MS-DOS, 5-1/4" double-density floppy diskette
ASM75-181
ISIS-/l, 8" single-density floppy diskette
ASM75-182
ISIS-/l, 8" double-density floppy diskette
ASM75-M52
CP / M-86, 5-1/4" double-density floppy diskette
ASM75-M81
CP/M-86, 8" single-density floppy diskette
ASM75-F9T1
Fortran IV ANSI X3.9-1966 source program
9-track 1600 BPI magnetic tape
The NEC ASM75 is available for use on all NEC
development systems and many other manufacturers'
microcomputer development systems, personal computers, minicomputers, and mainframes.
Features
D
D
D
D
o
o
Absolute address object code output
Macro definition capability
Generic jump with optimization capability
Conditional assembly options
- Up to eight levels of nesting
User-selectable and directable output files
Runs under a variety of operating systems
- CP/M-80®
-
o
CP/M-86®
- MS-DOS®
- ISIS-II
Fortran IV ANSI X3.9-1966 source program available
CP/M-80 and CP/M-86 are registered trademarks of Digital Research
Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
7-?~
pPD7500
7-24
NEe
NEe
NEe Electronics Inc.
pPD75000 SERIES
SOFTWARE
RELOCATABLE ASSEMBLER
DEVELOPMENT TOOLS
RA75X
Features
Description
o Absolute address object code output
o User-selectable and directable output files
o Extensive error reporting
o Jump optimization
o Runs under a variety of operating systems
The RA75X relocatable assembler package converts
symbolic source codeforthepPD75104,pPD75106, and
pPD75108 4-bit, single-chip microcomputers into an
executable absolute address object code. This package
consists of three separate programs: a relocatable
assembler (RA75X), a linker (LK75X), and an object
code converter (OC75X).
The RA75X translates a symbolic source module into a
relocatable object module. The assembler verifies that
each instruction assembled is valid for the target
microcomputer specified at assembly time. LK75X
combines multiple relocatable object modules into one
absolute object module. OC75X produces an ASCII
hexadecimal format object file.
-
CP/M-86®
MS-DOS®
CP/M-86 is a registered trademark of Digital Research Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
Ordering Information
Part Number
Description
RA75X-D52
MS-DOS, 5-1/4" double-density floppy diskette
RA75X-M52
CP/M-86, 5-1/4" double-density floppy diskette
RA75X-M81
CP/M-86, 8" single-density floppy diskette
The RA75X relocatable assembler package is available
for use on all NEC development systems and many
other manufacturers' development systems and
personal computers.
IJ
pPD75000
"7
I)~
t-iEC
pPD7800 SERIES
SOFTWARE
ABSOLUTE ASSEMBLER
NEe
NEe Electronics Inc.
DEVELOPMENT TOOLS
ASM87
Ordering Information
Description
Part Number
The 7800 series absolute assembler (ASM87) converts
symbolic source code for the J.lPD7800, J.lPD7801,
J.lPD7802, J.lPD78C05, J.lPD78C06, J.lPD7810, J.lPD7811,
and J.lPD7816 microcomputers into executable absolute
address object code. The assembler verifies that each
instruction assembled is valid for the target microcomputer specified at assembly time. An object code
file is produced in ASCII hexadecimal format and may
be downloaded to a PROM programmer or hardware
debugger.
ASM87-C81
Description
CP/M-80, 8" single-density floppy diskette
ASM87-D52
MS-DOS, 5-1/4" double-density floppy diskette
ASM87-181
ISIS-II, 8" single-density floppy diskette
ASM87-182
ISIS-II, 8" double-density floppy diskette
ASM87-M52
CP/M-86, 5-1/4" double-density floppy diskette
ASM87-M81
CP/M-86, 8" single-density floppy diskette
ASM87-F9T1
Fortran IV ANSI X3.9-1966 source program
9-track 1600 BPI magnetic tape
The NEC ASM87 is available for use on all NEC
development systems and many other manufacturers'
microcomputer development systems, personal computers, minicomputers and mainframes.
Features
D Absolute address object code output
D Macro definition capability
o Generic jump with optimization capability
o Conditional assembly options
- Up to eight levels of nesting
o User-selectable and directable output files
o Runs under a variety of operating systems
- CP/M-80®
- CP/M-86®
- MS-DOS®
- ISIS-II
o Fortran IV ANSI X3.9-1966 source program available
CP/M-80 and CP/M-86 are registered trademarks of Digital Research
Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
7-27
pPD7800
7-28
N'EC
NEe
NEe Electronics Inc.
pPD7800 SERIES
SOFTWARE
RELOCATABLE ASSEMBLER
DEVELOPMENT TOOLS
RA87
Ordering Information
Description
Part Number
The RA87 relocatable assembler package converts
symbolic source code for the entire 7800 family of
8-bit, single-chip microcomputers into executable
absolute address object code. This package consists
of three separate programs: a relocatable assembler
(RA87), ,,~inker (LK87), and an object converter
(OC87).
Description
RA87-D52
MS-DOS, 5-1/4" double-density floppy diskette
RA87-M52
CP/M-86, 5-1/4" double-density floppy diskette
RA87-M81
CP/M-86, 8" single-density floppy diskette
The RA87 translates a symbolic source module into a
relocatable object module. The assembler verifies that
each instruction assembled is valid for the specified
target microcomputer. LK87 combines multiple relocatable object modules into one absolute object module.
OC87 produces an ASCII hexadecimal format object
file.
The RA87 relocatable assembler package is available
for use on all NEC development systems and many
other manufacturers' microcomputer development
systems and personal computers.
Features
o Absolute address object code output
o User-selectable and directable output files
o Extensive error reporting
o JMP/JRE optimization
o Runs under a variety of operating systems
-
CP/M-86®
MS-DOS®
CP/M-86 is a registered trademark of Digital Research Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
7-29
pPD7800
7-30
NEe
pPD78000 SERIES
SOFTWARE
RELOCATABLE ASSEMBLER
DEVELOPMENT TOOLS
NEe
NEe Electronics Inc.
RA310
Features
Description
o Macro definition capability
The RA310 relocatable assembler package converts
symbolic source code for the pPD78310 and pPD78312
8-bit, single-chip microcomputers into executable
absolute address object code. This package consists
of four separate programs: a relocatable assembler
(RA310), a linker (LK310), a locator (LC310), and a
librarian (LB310).
RA310 translates a symbolic source module into a
relocatable object module. The assembler verifies that
each instruction assembled is valid for the target
microcomputer specified at assembly time. LK310
combines multiple relocatable object modules into one
relocatable object module. LC310 assigns addresses
to the relocatable object module and produces both an
ASCII hexadecimal format object file and a symbol file
for use by the 78000 series hardware emulators. LB310
creates and maintains files containing relocatable
object modules. When the library file is included in the
input to LK310, the linker only extracts those modules
required to resolve external references and links them
into the relocatable object module.
o
o
o
Conditional assembly options
Jump optimization
Runs under a variety of operating systems
- CP/M-86®
- MS-DOS®
- VAXIVMS® and VAX/UNIX®
CP/M-86 is a registered trademark of Digital Research
Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
VAX and VMS are registered trademarks of Digital Equipment
Corporation.
UNIX is a trademark of AT&T.
Ordering Information
Part Number
Description
RA310-D52
MS-DOS, 5-1/4" double-density floppy diskette
RA310-M52
CP / M-86, 5-1/4" double-density floppy diskette
RA310-M81
CP/M-86, 8" single-density floppy diskette
RA310-VVT1
VAXIVMS, 9-track 1600 BPI magnetic tape
RA310-VXT1
VAX/UNIX, 9-track 1600 BPI magnetic tape
The RA310 relocatable assembler package is available
for use on all NEC development systems and many
other manufacturers' development systems, personal
computers and minicomputers.
7-31
pPD78000
7-32
NEe
NEe
NEe Electronics Inc.
Description
The RA70320 Relocatable Assembler Package converts
symbolic source code for the V25 (pPD703201
pPD70322) single-chip microcomputers into executable absolute address object code. The package consists of fou r separate prog rams: a relocatable assembler
(RA70320), a linker (LK70320), a hexadecimal format
object code converter (OC70320), and a librarian
(LB70320).
RA70320 translates a symbolic source module into a
relocatable object module. LK70320 combines relocatable object modules and absolute load modules and
converts them into an absolute load module. OC70320
produces an ASCII hexadecimal format object fi Ie from
either an absolute load or object module. LB70320
creates and maintains files containing relocatable
object modules. When the library file is included as
input to the LK70320, only those modules required to
resolve external references are extracted from the
library, relocated and linked into the absolute load
module.
pPD70320/322
SOFTWARE
RELOCATABLE ASSEMBLER
DEVELOPMENT TOOLS
Ordering Information
Part Number
Description
RA70320-D52
MS-DOS, 5-1/4" double-density floppy diskette
RA70320-181
ISIS-Ii, 8" single-density floppy diskette
RA70320-182
ISIS-Ii, 8" double-density floppy diskette
RA70320-M52
CP/M-86, 5-1/4" double-density floppy diskette
RA70320-M81
CP/M-86, 8" single-density floppy diskette
RA 70320-VVT1
VAXIVMS, 9 track 1600 BPI magnetic tape
RA 70320-VXT1
VAX/UNIX, 9 track 1600 BPI magnetic tape
CP/M-86 is a trademark of Digital Research Corporation.
MS-DOS is a trademark of Microsoft Corporation.
VAX and VMS are trademarks of Digital Equipment Corporation.
UNIX is a trademark of AT&T.
Features
D
D
D
D
D
Absolute address object code output
User-selectable and directable output files
Extensive error reporting
Powerful librarian
Runs under a variety of operating systems
- CP/M-86®
- MS-DOS®
- ISIS/UDI
- VAX/VMS® and VAX/UNIX®
7-33
pPD70320/322
7-34
t\'EC
NEe
NEe Electronics Inc.
Descri plion
The Evakit communication program (EVA) allows a
variety of microcomputer development systems and
personal computers to control NEC's Evakits and incircuit emulators directly from the console of the host
system. Once a particular emulator is selected from the
EVA program's menu, EVA recognizes all legal commands for that emulator. In addition to the emulator
standard commands, the EVA program provides commands to upload, download, and display disk files and
directories, to save debug session on disk, to display
command help files, and to exit from the program to the
operating system.
You can download to the emulator object code program
files produced by a cross assembler on the host system
and upload patched copies of the program from the
emulatorto the disk for use in later debugging sessions.
The disk display commands allow you to examine
directories and files on the screen without having to
exit the EVA program. This is extremely useful for
checking a file before it is downloaded to the emulator
or erased during an upload. The help command displays a complete list of all legal commands for the
chosen emulator with their proper syntax. There is a
command to exit from the EVA program and to return to
the operating system. The emulator is not affected, and
emulation can be continued by invoking the EVA
program again.
EVAKIT
COMMUNICATION
PROGRAM
The EVA program is supplied in executable format and
is included with each NEC assembler. Executable
versions are available for the following host systems:
Intel MDS-220/330 under ISIS-II
NEC APC under CP/M-86®
IBM PC or PC/XT® under CP/M-86 or PC-DOS®
IBM PC/AT® under PC-DOS
Source code is available and may be modified to
support other CP/M-80®, CP/M-86, MS-DOS®, and
ISIS-II based systems.
The EVA program supports all current Evakits and incircuit emulators and is periodically updated as new
emulators are introduced.
CP/M-80 and CP/M-86 are registered trademarks of Digital Research
Corporation.
PC/XT, PC-DOS, and PC/AT are registered trademarks of
International Business Machines Corporation.
MS-DOS is a trademark of Microsoft Corporation.
7-35
EVA KIT COMMUNICATION PROGRAM
7-36
tt¥EC
NEe
NEe Electronics Inc.
MD·086 SERIES
MICROCOMPUTER
DEVELOPMENT SYSTEMS
MD-086 FLOPPY AND HARD DISK DRIVE SYSTEM
Description
The MD-086 series microcomputer development
systems are a series of disk based, multi-user, multitasking systems supporting the development of
products using NEG's microcomputers and microprocessors. Available in either a floppy disk-based or
floppy/hard disk-based configuration, the MD-086 may
be coupled with NEG's stand-alone evaluation kits
(Evakits) or in-circuit emulators (IEs) to provide a
complete integrated software and hardware development system.
Based on NEG'stJPD808616-bit microprocessor, running Digital Research's MP/M-86® operating system,
the MD-086 gives you access to all NEG's assemblers,
simulators, high level language compilers, and all other
GP/M-86® application software.
The MD-086FD-10 (floppy disk-based) consists of two
units: the system chassis (housing all the electronics)
and the system console (an ANSI standard X3.64
terminal.) The MD-086HD-10 (floppy/hard disk based)
consists of three units: the system chassis, the hard
disk chassis and the system console, and an ANSI
standard terminal. Additional terminals may be added
to the system as required, thereby lowering the system
cost per user.
MP/M-86 and CP/M-86 are registered trademarks of Digital Research
Corporation.
7-37
NEe
MD-086 SERIES
Features
D MP/M-86 multi-user/multi-tasking operating system
- Supports up to three users
- Supports multi-tasking at each user terminal
D 512K bytes of system memory
- Optional expansion to 1M byte total
D Two 1M byte 8" double-sided floppy disk drives
D Optional 35M byte hard disk
D 64K byte memory disk
D Two parallel printer ports
D IEEE-796 bus-based with 5 vacant slots for future
expansion
D Separate ANSI standard X3.64 system console
Ordering Information
Part Number
Description
MD-086FD-10
MD-086 series, floppy disk-based system
MD-086HD-10
MD-086 series, floppy/hard disk-based system
MD-086DK
Har~disk
MD-910TM
Character display terminal
upgrade for MD-086FD-10
Hardware Description
System Chassis
The system chassis of the MD-086 series houses a
multiprocessor system, two 8" doubled-sided floppy
disk drives, an IEEE:-796 cardcage, power supply, and
fans. Utilizing the industry standard IEEE-796 bus as
its internal system bus, NEC's MD-086 series with
severa.l vacant slots, can easily be expanded to meet
tommorrow's technological advances.
The multiprocessor architecture of the MD-086 series
permits the master CPU to offload the time consuming
tasks of data storage/retrieval and system I/O processing to its intelligent peripheral boards, significantly
increasing the multi-user/ multi-tasking capabilities of
the operating system. This multiprocessor system is
composed of a pPD8086 master CPU board, a 512Kbyte memory board, apPD780-based intelligent floppy
disk controller (FDC) board, a pPD8088-based intelligent system controller board (SCB), and an optional
pPD780-based intelligent hard disk controller (HDC)
board.
System Boards
The master CPU board is the heart of the system.
Utilizing apPD8086 microprocessor running at 5 MHz,
it controls the operation of the multi-user/multi-pro-
7-38
gramming operating system. The CPU board also
contains the bootstrap loader PROM and the system
work RAM, interrupt controller, and timer.
A single 512K-byte memory board provides the system
memory and is accessed by either the master CPU
board, the floppy disk controller board, or the optional
hard disk controller board. System memory can be
expanded to 1M byte by adding additional IEEE-796
bus memory boards.
The FDC board is an intelligent floppy disk controller
board using NEC's pPD765A floppy disk controller
chip to control up to four 8" double-sided floppy disk
drives in either single or double-density format. Containing an NEC pPD780-1 microprocessor with 8K of
PROM, 64K of RAM, and a DMA controller, the FDC
board controls the transfer of data between the system
memory and the floppy disk.
The HDC board is an intelligent hard disk controller
board using N EC's pPD7261 A hard disk controller ch ip
to control up to two SMD interface hard disk drives.
Containing an NEC j.lPD780-1 microprocessor with
8K PROM, 18K of RAM, and a DMA controller, the HDC
board controls the transfer of data between the system
memory and the hard disk.
The SCB isan intelligent I/O controller board using an
NEC pPD8088 microprocessor with up to 16K bytes of
PROM and 64K bytes of RAM to control the system
console, the serial communication channels, the printer
ports, and the paper tape interfaces.
The master CPU writes commands into· the dualported memories on the FDC, HDC, and SCB boards.
Each board executes its command with no further
intervention by the master CPU. This increases the
system performance of the MD-086 series.
The two 8" doubled-sided floppy disk drives provide
approximately 2M bytes of data storage capacity.
Single-sided diskettes are recorded in single-density
to provide compatibility with other CP/M-86 and
MP/M-86 systems. Double-sided diskettes are recorded
in double-density providing a maximum storage capacity of 972K bytes per diskette.
Hard Disk Chassis
The optional hard disk chassis houses one 8" SMD
interface hard disk drive capable of storing 32M bytes
of formatted data, the power supply, and fans. A ready
indicator, along with a write protect switch/indicator,
and a fault switch/indicator are also provided.
NEe
System Console
MD·086 SERIES
D Display and modify user registers.
o Read and write to the floppy disks and paper tape.
D Set breakpoints and execute user's program.
D Single-step and trace executing user's program.
The MD-91 OTM, an ANSI standard X3.64 CRT terminal,
is provided as the system console for the MD-086
series microcomputer development systems. To take
advantage of the mUlti-user features of the MD-086
series, additional ANSI standard terminals may be
purchased separately from NEC Electronics Inc. or
other manufacturers.
MD-086 Series Utilities
Software Description
The following utility programs are supplied with the
M D-086 series:
The MD-086 series incorporates Digital Research's
MP/M-86 operating system providing you a compact
multi-user, multitasking operating system. Each user
has complete access to all of the MP/M-86 facilities and
may execute multiple programs simultaneously.
ABORT
ASM86
ATTACH
BACKUP
The powerful MP/M-86 file system manages all files
and file directories, dynamically allocating, and releasing disk space as required. Designed for the multiuser environment, it enhances file integrity by permitting files to be opened in one of three modes: locked,
unlocked, and read only modes. In locked mode, only
one user may open a specific file at a given time, while
in unlocked mode multiple users/programs may open
the same file. Read only mode, permits a file to be
opened by more than one process but it cannot be
changed.
Optional password protection is available at both the
file and disk level, providing protection for a particular
user's files. MP/M-86's extended directories allow files
to be dated and time stamped. Each file may have up to
two date and time stamps: one reflects the date and
ti me of the last update and the other the date of the last
access or file creation.
All files generated on CP/M® 8" diskette systems may
be read under M P/M-86, allowi ng you to easily transport
existing software routines to the MD-086 series. Hardware-independent CP/M-86 application programs can
be ru n, g ivi ng you access to a wide variety of th i rd party
software.
A 64K-byte memory disk residing in system memory is
available for high speed file processing, significantly
improving the overall performance of the MD-086
series microcomputer development systems.
The MD-086 series contains a PROM-resident monitor
program which may be used for pPD8086 program
development/debugging. This monitor program is
entered automatically if there is no MP/M-86 system
disk in drive A when the reset switch is pressed. Some
of the main features of the MD-086 monitor are:
D Display, fill, substitute, compare, transmit, ortestthe
contents of memory.
Note:
CP/M is a registered trademark of Digital Research Corporation.
CLEAR
CONSOLE
DDT86
DIR
DSKRESET
ED
ERA
ERAQ
FORMAT
GENCMD
GENSYS
HDBACKUP
HDDUMP
HDFORMAT
MPMSTAT
PHFORMAT
PIP
PRINTER
REN
SDIR
SET
SHOW
SPOOL
STAT
STOPSPLR
SUBMIT
SYSCPY
TOD
TYPE
USER
YEAR
Stops the specified process
Absolute assembler for pPD8086/8088
Attaches program to its console
Makes a complete backup copy of a
disk
Clears the system console screen
Displays console number
Dynamic debugging tool for
pP D8086/8088
Displays disk directory of filenames
Resets drives
Line-oriented editor
Erases a file
Erases <;l file only after confirmation
Formats floppy disks
Converts H86 file to CMD file
Generates MP/M-86 operating system
Makes backup of hard disk logical
drive
Displays and changes contents of
hard disk
Initializes hard disk logical drives
Displays MP/M-86 internal status
Physically formats hard disk
Copies fi les
Displays and sets the printer number
Renames files
Displays disk directory with options
Sets disk and file protection levels,
file attributes, and file time stamping
Displays disk status and protection
levels
Spools files to the list device
Displays, set files, and disk status
Stops the spooler
Executes batch processing
Copies system loader and MPM.SYS
Displays and sets time of day
Displays ASCII file contents at
console
Displays and sets user number
Sets the year
7-39
ID
NEe
MD·086 SERIES
Five of these utilities have been incorporated into the
operating system as resident system processes (RSPs)
and reside in system memory. They can be executed
without disk accesses, increasing the performance of
the system. The RSPs in the MD-086 series include:
ABORT, DSKRESET, MPMSTAT, PRINTER, and USER.
MD·086 Series Development Environment
The MD-086 series microcomputer development
systems have been designed to provide a integrated
software and hardware development environment for
all NEC proprietary microcomputers, microprocessors,
and digital signal and image processing components.
For software development, a complete family of
absolute and relocatable assemblers, high level languagecompilers, and digital signal and image processor
simulators are available for the MD-086 Series. For
software and hardware debug, N EC in-circuit emulators
and Evakits can be controlled directly from the MD-086
series consoles.
Evakit communication programs are available for controlling all stand-alone Evakits via a serial link directly
from any console of the development system. These
programs provide program upload and download capability plus a full line assembler and disassembler.
Up tothree in-circuit emulators can be plugged directly
in the IEEE-796 backplane of the MD-086 series and
controlled by the appropriate IE control program. In
this bus-coupled configuration, your program debugging capabilities are greatly enhanced with the addition
of symbolic debug, macro command file capability, and
improved file upload/download times.
With the MD-086 series microcomputer development
systems, you will always have access to development
tools for NEC's newest components at the earliest
possible time.
Documentation
The following documentation is supplied with the
system. Additional copies may be obtained from NEC
Electronics Inc.
•
•
•
•
•
•
MD-086FD-10 Installation Manual
MD-086FD-10 MP/M-86 Implementation Manual
MD-910TM Terminal User Manual
MP/M-86 Multi-Process Monitor User's Guide*
MP/M-86 Operating System Guide*
MP/M-86 Multi-Process Monitor Programmer's
Guide*
'Additional copies may be obtained from Digital Research.
Equipment
The following equipment is supplied with the system:
MD-086FD-10
•
•
•
•
•
•
•
•
•
1
2
1
1
1
2
2
1
2
• 1
• 1
System chassis
RS-232C serial cables
Centronics printer cable
Line cord and ground adapter
Spare fuse
On-off keys
Male DB-25 solder type connectors/shells
Set of disk drive labels
8" floppy diskettes
MP/M-86 system disk
MP/M-86 gensys disk
MD-910TM system console
1 RS-232C cable
1 TTL level cable
1 Line cord and ground adapter
Set of documentation
MD-086HD-10
• 1 MD-086FD-10 system
• 1 MD-086DK
MD-086DK hard disk upgrade
•
•
•
•
1 Hard disk chassis
1 HDC board
1 Set of interconnecting cables
1 Line cord and ground adapter
Specifications
Processors
Main
Slave
pPD8086C, 5 MHz, CPU Board
pPD780C-1, 4 MHz, FDC Board
pPD8088C-2, 6.5536 MHz, SCB Board
pPD780C-1, 4 MHz, HDC Board
System Memory
512K-bytes of dynamic RAM (1 M byte total- optional)
Operating system area
Memory Disk
User's Area
64K bytes
64K bytes
384K byte
(896K bytes optional)
External Memory
Two double-sided 8" floppy disk drives
- 2M-byte maximum capacity
Optional SMD Interface 8" hard disk drive
- 32M-byte formatted capacity
7-40
NEe
MD·086 SERIES
Bus Structure
Environmental Specifications
IEEE-796 Bus
- 5 spare slots in MO-086FO-10
- 4 spare slots in MO-086HO-10
Temperature:
Humidity:
Serial Interfaces
System console
Serial interfaces
RS-232C/TTL
RS-232C
RS-232C/TTL
1 channel
1 channel
4 channel
-20 to +40°C, non-operating
+10 to +40°C, operating
10 to 90% relative humidity,
non-operati ng
30 to 80% relative humidity, operating
(without condensation)
Electrical Characteristics
FCC: Class A
Parallel Interfaces
AC Requirements:
Centronics printer interface
2 channel
Operating System
System chassis: 90-132 V, 50/60 Hz ±2%, SA
System console: 90-132 V, 50/60 Hz ±2%, 2A
MP/M-86, version 2.0 with NEC proprietary enhancements.
Physical Characteristics
System Console
Width
System Chassis
CRT
Keyboard
16.75 in (425 mm)
14.25 in (362 mm)
18.5 in (470 mm)
Height
11.77 in (299 mm)
14.29 in (363 mm)
1.50 in (38 mm)
Depth
24.21 in (615 mm)
13.46 in (342 mm)
7.44 in (189 mm)
Weight
59.40 Ib (27 kg)
19.95 Ib (9 kg)
4.41 Ib (2 kg)
7-41
MD·086 SERIES
7-42
NEe
NEe
NEe Electronics Inc.
Description
The MD-910TM character display terminal is an ANSI
standard CRT terminal used as the system console of
the MD-086 series microcomputer development system.
The MD-910TM can also be used as an additional
console for this system, or as an external terminal for
any stand-alone Evakit or in-circuit emulator.
Features
o
o
o
o
o
o
o
o
o
o
o
o
o
o
Multiple emulation modes
- ANSI standard X3.64 (VT100 compatible)
- VT52 (Digital Equipment Corporation)
Amber 12" nonglare screen
Tilt/swivel display
Detached low-profile keyboard conforming to DIN
standard
- ASCII keys, numeric keypad, four function keys
Total software set-up feature
Smooth, jump, or partial scrolling
80/132 columns by 24-line display
Standard, double width, or double height/width
characters
Blinking block, blinking underline, or invisible cursor
Display attributes
- Normal, bold, blinking, reverse, underscore,
overline, and vertical line
Display status LEDs on keyboard
Software selectable serial interface
- RS-232C, TTL, 20 mA current loop
- 7- or 8-bit character with odd, even, or no parity
- Full or half-duplex operation
- Transfer rate: 50 to 19200 BPS
Power-on, self-diagnostic function and data analyzer
mode
Centronics printer port
MD-910TM CHARACTER
DISPLAY TERMINAL
DEVELOPMENT TOOL
Physical Characteristics
Dimension
Width
Display
Keyboard
14.25 in (362 mm)
18.05 in (470 mm)
Height
14.49 in (363 mm)
1.50 in (38 mm)
Depth
13.46 in (342 mm)
7.44 in (189 mm)
Weight
19.951b (9 Kg)
4.41 Ib (2 Kg)
Environmental Specifications
Temperature: 0 to 40°C
Relative Humidity: 30 to 80% , non-condensing
Electrical Characteristics
FCC: Class A
Power: 90-132 V AC, 50/60 Hz ±2%, 2A
Ordering Information
Part Number
Description
MD-910TM
Character display terminal
Equipment
The following equipment is supplied with the
MD-910TM terminal:
•
•
•
•
•
•
•
1 Display terminal
1 Keyboard with attached cable
1 RS-232C serial interface cable
1 TTL serial interface cable
1 AC power cord and ground adapter
1 Spare fuse
1 MD-910TM user's manual
7-43
MD·910TM.
7-44
NEe
NEe
NEe Electronics Inc.
PG1000PROM
PROGRAMMER
Description
PG 1 000 Personality Modules
The PG1000 is NEC's PROM Programmer for use with
the MD-086 Series Development Systems and certain
NEC Emulators. With the use of interchangeable personality modules, the user can tailor the PG1000 to
support various NEC single-chip microcomputers. The
user controls the PG1000 via the serial interface from
either a host computer or an external terminal, or
directly from the on-board keypad in stand-alone
mode.
The PG1003 is a plug-in personality module for the
PG1000 PROM Programmer. This module is required
to program theJ,lPD78P09R, the EPROM version forthe
J,lPD7808 and J,lPD7809 8-bit, single-chip microcomputers. The PG1003 supports two programming modes:
high-speed writing mode and normal writing mode.
Features
o
o
o
o
o
o
o
Interchangeable personality modules
16K of data RAM
Address/data display and mode specification LEDs
Flexible membrane keypad
Three modes of operation
- Host computer controlled
- External terminal controlled
- Stand-alone operation
Serial interface: RS-232C, TTL, or 20-mA current
loop
Parallel interface: TTL (two-wire handshake)
PG1003
PG1005
The PG1005 is a plug-in personality module for the
PG1000 PROM Programmer. This module is required
to program theJ,lPD75P108, the EPROM version forthe
J,I~D75104, J,lPD75106, and J,lPD75108 4-bit, single-chip
mIcrocomputers. Interchangeable socket adapters are
provided with the PG1005 to allow programming both
shrink dip and flat packages.
7-45
PG1000
7-46
NEe
NEe
PACKAGING INFORMATION
8-1
E
PACKAGING INFORMATION
NEe
Section 8 - Packaging Information
Package/Device Cross Reference ............................................. 8-3
20-Pin Plastic Shrink DIP (300 mil) ............................................ 8-5
20-Pin Plastic SO (Small Outline) (300 mil) ..................................... 8-5
24-Pin Plastic Shrink DIP (300 mil) ............................................ 8-6
24-Pin Plastic SO (Small Outline) (300 mil) ..................................... 8-6
28-Pin Plastic DIP (600 mil) ................................................... 8-7
28-Pin Plastic Shrink DIP (400 mil) ............................................ 8-7
40-Pin Plastic DIP (600 mil) ................................................... 8-8
40-Pin Plastic Shrink DIP (600 mil) ............................................ 8-8
40-Pin Ceramic Piggyback DIP (600 mil) ....................................... 8-9
40-Pin Cerdip with Window (600 mil) .......................................... 8-9
42-Pin Plastic DIP (600 mil) .................................................. 8-10
42-Pin Plastic Shrink DIP (600 mil) ........................................... 8-10
42-Pin Ceramic Piggyback DIP ............................................... 8-11
44-Pin Plastic Miniflat ....................................................... 8-11
52-Pin Plastic Miniflat ....................................................... 8-12
54-Pin Plastic Miniflat ....................................................... 8-12
54-Pin Plastic Miniflat (Inverted leads) ........................................ 8-13
64-Pin Plastic Shrink DIP (750 mil) ........................................... 8-13
64-Pin Plastic Miniflat ....................................................... 8-14
64-Pin Plastic QUIP ......................................................... 8-14
64-Pin Shrink Cerdip with Window ........................................... 8-15
64-Pin Ceramic QUIP with Window ........................................... 8-15
64-Pin Ceramic Piggyback QUIP ............................................. 8-16
68-Pin Plastic Leaded Chip Carrier (PLCC) ................................... 8-16
80-Pin Plastic Miniflat ....................................................... 8-17
84-Pin Plastic Leaded Chip Carrier (PLCC) ................................... 8-17
8-2
NEe
PACKAGING INFORMATION·
Package/Device Cross Reference
Device
Package
Device
Package
20-Pin Plastic Shrink DIP (300 mil)
pPD7554CS
pPD7564CS
20-Pin Plastic SO (Small Outline)
(300 mil)
pPD7554G
pPD7564G
42-Pin Plastic Shrink DIP (600 mil) pPD7527ACU
pPD7528ACU
pPD7533CU
pPD7537ACU
pPD7538ACU
24-Pin Plastic Shrink DIP (300 mil)
pPD7556CS
pPD7566CS
24-Pin Plastic SO (Small Outline)
(300mil)
pPD7556G
pPD7566G
28-Pin Plastic DIP (600 mil)
pPD7506C
pPD7507SC
28-Pin Plastic Shrink DIP (400 mil)
pPD7506CT
pPD7507SCT
40-Pin Plastic DIP (600 mil)
pPD7507C
pPD7507HC
pPD7508C
pPD7508HC
pPD7508AC
pPD8035HLC
pPD80C35C
pPD8039HLC
pPD80C39HC
pPD80C40HC
pPD8041AHC
pPD80C42C
pPD8048HC
pPD8QC48C
pPD8049HC
pPD80C49HC
pPD80C50HC
pPD8748HC
pPD8749HC
40-Pin Plastic Shrink DIP (600 mil)
pPD7507CU
pPD7507HCU
pPD7508CU
pPD7508HCU
40-Pin Ceramic Piggyback DIP
(600 mil)
pPD75CG08E
pPD75CG08HE
40-Pin Cerdip with Window (600 mil) pPD8741AD
pPD8748HD
pPD8749HD
42-Pin Plastic DIP (600 mil)
pPD7527AC
pPD7528AC
pPD7533C
pPD7537AC
pPD7538AC
42-Pin Ceramic Piggyback DIP
pPD75CG28E
pPD75CG33E
pPD75CG38E
44-Pin Plastic Miniflat
pPD48G-22
pPD49HG-22
pPD50HG-22
pPD7507HG-22
pPD7508HG-22
pPD7533G-22
pPD80C42G-22
52-Pin Plastic Miniflat
pPD7225G-00
pPD7506G-00
pPD7507G-00
pPD7508G-00
pPD80C48G-00
pPD80C49HG-00
54-Pin Plastic Miniflat
pPD6307G-F
pPD6308G-F
54-Pin Plastic Miniflat
(inverted leads)
pPD6307G-R
pPD6308G-R
64-Pin Plastic Shrink DIP
(750 mil)
pPD7516HCW
pPD7519CW
pPD7519HCW
pPD7807CW
pPD7808CW
pPD7809CW
pPD7810CW
pPD78C10CW
pPD7810HCW
pPD7811CW
I]
pPD78C11CW
pPD7811HCW
pPD78C14CW
pPD75104CW
pPD75106CW
pPD75108CW
pPD75P108CW
pPD78310CW
pPD78312CW
8-3
NEe
PACKAGING INFORMATION
PackagelDevice Cross Reference
Package
Device
Package
Device
64-Pin Plastic Miniflat
64-Pin Plastic QUIP (cont)
pPD78C10G-36
pPD7810HG-36
pPD7811 G-36
pPD78C11 G-36
pPD7811 HG-36
pPD7227G-12
pPD7501 G-12
pPD7502G-12
pPD7503G-12
pPD7516HG-12
pPD7519G-12
pPD7519H G-12
pPD78C06AG-12
pPD78C10G-1 B .
pPD78C 11 G-1 B
64-Pin Plastic QUIP
64-Pin Shrink Cerdip with Window pPD75P108DW
pPD78C14G-1 B
pPD72030G-12
pPD75104G-1 B
pPD75106G-1 B
pPD75108G-1 B
64-Pin Ceramic Piggyback QUIP
pPD75P108G-1 B
pPD78310G-1 B
pPD78312G-1 B
pPD75CG16HE
pPD78PG11 E
pPD75CG19E
pPD75CG19HE
68-Pin Plastic Leaded Chip
Carrier (PLCC)
pPD78C10L
pPD78C11 L
pPD78C14L
pPD78310L
pPD78312L
80-Pin Plastic.Miniflat
pPD7228G-12
pPD7514G-12
pPD70320G-12
pPD70322G-12
84-Pin Plastic Leaded Chip
Carrier (PLCC)
pPD70320L
pPD70322L
pPD7500HG-36
pPD7500HG-E-36
pPD7516HG-36
pPD7519G-36
pPD7519HG-36
pPD78C05AG-36
pPD7807G-36
pPD7808G-36
. pPD7809G-36
pPD7810G-36
8-4
pPD78C14G-36
pPD78310G-36
pPD78312G-36
pPD78P312G-36
64-Pin Ceramic QUIP with Window pPD78P09R
ttiEC
PACKAGING INFORMATION
20-Pln Plastic Shrink DIP (300 mil)
20
MIllimeters
Inches
A
19.57 max
.771 max
B
1.78 max
.070 max
C
1.778 [TPJ
.070 [TPJ
Item
0
.50±.10
.020
16.0
.630
~:~~:
.85 min
.033 min
G
3.2±.3
.126 ±.012
H
.51 min
.020 min
4.31 max
.170 max
5.08 max
.200 max
7.62 [TPJ
.300 [TPJ
K
6.5
M
.25
11
.256
~:~~
.010
~:~~~
Note:
[1 J Each lead centerline is located within
.17 mm [.007 inchJ of its true
position [TPJ at maximum material
condition.
M
[2J Item uK" to center of leads when
formed parallel.
0-15°
83-0036098
20-Pln Plastic SO (Small Outline) (300 mil)
20
Millimeters
Inches
A
13.00 max
.512 max
B
.78 max
.031 max
C
1.27 [TPJ
.050 [TPJ
0
.40
Item
~:~~
.016
~:~~~
.1 ±.1
.004 ±.004
1.8 max
.071 max
G
1.55
.061
H
7.7±.3
.303 ±.012
5.6
.220
.043
1.1
K
.20
~:~~
.6 ±.2
11
.008
~:~~~
.024
~:~~:
Note:
[1 JEach lead centerline is located wilhin
.12 mm [.005 inchJ of its true
position [TPJ at maximum material
condition.
I. '
A
" .1
H
t~1RJ-.l
fK
83-0038478
8-5
0
t-rEC
PACKAGING INFORMATION
24-Pln Plastic Shrink DIP (300 mil)
24
Item
MIllimeters
Inches
A
23.12 max
.911 max
1.78 max
.070 max
c
1.178 [TP)
.070 [TP)
.50 ±.10
.020 :::~~:
19.558
.170
.85 min
.033 min
G
3.2 ±.3
.126 ±.012
H
.51 min
.020 min
4.31 max
.170 max
5.08 max
.200 max
7.62 [TP)
.300 [TP)
6.5
.256
.25 :::~~
.010 :::~~:
M
13
I. '
".I
A
Note:
(1) Each lead centerline Is located within
.17 mm [.007 Inch) of Its true
position [TP) at maximum material
condition.
(2) Item UK" to center of leads when
formed parallel.
c
B
-IIM
\-0-15 0
83-0037838
24-Pln Plastic SO (Small Outline) (300 mil)
24
Item
Millimeters
Inches
A
15.54 max
.612 max
B
.78 max
.031 max
C
1.27 [TP)
.050 [TP)
.40:::~~
.016 :::~~:
D
.1±.1
.004 ±.004
1.8 max
.071 max
G
1.55
.061
H
7.7±.3
.303±.012
K
5.6
.220
1.1
.043
.20 :::~~
.008 :::~~:
.6±.2
.024 :::~~:
13
" .1
Note:
(1) Each lead centerline Is located within
.12 mm [.005 Inch) of Its true
position [TP) at maximum material
condition.
83-0038578
8-6
NEe
PACKAGING INFORMATION
28-Pln Plastic DIP (600 mil)
15
28
Item
A
Millimeters
1nches
38.1 max
1.5 max
---------~-~-----
a
2.54 max
.10 max
C
2.54 [TP)
.10 [TP)
0
.5 ± .10
.02
+ .004
- .005
-----------~-------.--
33.02
G
H
K
M
Notes:
1.3
1.2 min
.047 min
3.6 ±.3
.142 ± .012
.51 min
.02 min
4.31 max
.17 max
5.72 max
.226 max
15,.24 [TP)
.60 [TP)
13.2
.52
.25
+.10
-.05
.01
" .1
A
K
+.004
- .003
1. Each lead centerline Is located
within .25 mm [.01 Inch) of Its true
position [TP) at maximum material condition.
2. Item "K" to center of leads when
formed parallel.
-~
0-15'
E
83·0014078
28-Pln Plastic Shrink DIP (400 mil)
15
28
Item
Millimeters
Inches
A
28.46 max
1.121 max
.106 max
a
2.67 max
C
1.778 [TP)
.070 [TP)
0
.50±.10
.02
23.114
.91
F
.9 min
.035 min
G
3.2±0.3
.126 ±.012
H
.51 min
.020 min
4.31 max
.170 max
5.08 max
.200 max
10.16 [TP)
.400 [TP)
K
8.6
M
.25
+ .004
- .005
.339
+.10
- .05
.01
+ .004
- .003
Notes:
1. Each lead centerline Is located within
.17 mm [.007 Inch) of Its true position [TP)
at maximum material condition.
2. Item "K" to center of leads when formed
parallel.
E
83-0015198
8-7
NEe
PACKAGING INFORMATION
40-Pln Plastic DIP (600 mil)
40
Item
Mlilimetera
Inches
A
53.34 mex
2.100 max
B
2.54 max
.100 max
C
2.54 [TP]
.100 [TP]
D
.50±.10
.020
48.26
1.900
~:~~:
F
1.2 min
.047 min
G
3.6±.3
.142 ± .012
H
.51 min
.020 min
4.31 max
.170 max
K
5.72 max
.226 max
15.24 [TP]
.600 [TP]
13.2
M
.25
21
.520
~:~~
.010
~:~~~
Notes:
[1] Each lead centerline Is located within .25
mm [.010 Inch] of Its true position [TP] at
maximum material condition.
[2] Item "K" to center of leads when formed
parallel.
83-0013998
40-Pln Plastic Shrink DIP (600 mil)
40
Item
Millimeters
Inches
A
39.13 max
1.541 max
B
2.67 max
.106 max
C
1.778 [TP]
.070 [TP]
D
.50 ± .10
.020 ± .004
33.78
1.330
F
.9 min
.035 min
G
3.2±.3
.126 ± .012
H
K
M
.51 min
.020 min
4.31 max
.170 max
5.08 max
.200 max
15.24 [TP]
.600 [TP]
13.2
.520
.25
~:~~
.010
21
~:~~~
Note:
[1] Each lead centerline is located within
.17 mm [.007 Inch] of Its true position
[TP] at maximum material condition.
[2] Item "K" to center of leads when formed
parallel.
83-0037658
8-8
NEe
PACKAGING INFORMATION
40-Pln Ceramic Piggyback DIP (600 mil)
A
Item
Millimeters
Inches
A
53.34 max
2.1 max
.8
B
20.32
C
2.54 ± .25
.1 ±.01
D
0.46 ± .05
.018 ± .002
E
48.26
1.9
1.02
.04
G
3.2 min
.126 min
H
1.02 min
.04 min
3.0 max
.118 max
K
4.32 max
.17 max
15.24
.6
15.24
.6
M
.25 ± .05
.01 ± .002
N
33.02
1.3
0
2.54 ± .25
.1 ±.01
'I
00000000000000
~
D
00000000000000
N
M
83·0039218
40-Pin Cerdlp with Window (600 mil)
Item
Millimeters
Inches
A
53.34 max
2.100 max
B
2.54 max
.100 max
C
2.54 [TPJ
.100 [TPJ
D
.50 ±.10
.020
E
48.26
1.900
1.2 min
.047 min
G
3.5±.3
.138 ±.012
H
.51 min
.020 min
K
1:~~:
3.80
.150
5.08 max
.200 max
15.24 [TPJ
.600 [TPJ
13.21
.520
~:~~~
M
.25 ±.05
.010
N
r/J 7.62
r/J .300
Note:
[1 J Each lead centerline is located within
.25 mm [.01 inchJ of its true
position [TPJ at maximum material
condition.
[2J Item "K" to center of leads when
formed parallel.
83-0037858
8-9
NEe
PACKAGING INFORMATION
42-Pln Plastic DIP (600 mil)
42
Item
MIllimeters
Inches
A
55.88 max
2.200 max
2.54 max
.100 max
C
2.54 [TP]
.100 [TP]
0
.5±.1
.020
50.8
2.000
1.2 min
.047 min
=:~~:
G
3.6± .3
.142 ± .012
H
.51 min
.020 min
4.31 max
.170 max
5.72 max
.226 max
K
15.24 [TP]
.600 [TP]·
1;1.2
.520
M
.25
=:~~
.010
22
=:~g:
Note:
[1] Each lead centerline Is located within .25
mm [.01 Inch] 01 Its true position [TP] at
maximum material condition.
[2] Item "K" to center 01 leads when formed
parallel.
83-0035726
42-Pln Plastic Shrink DIP (600 mil)
42
Item
MIllimeters
Inches
A
39.13 max
1.541 max
B
1.78 max
.070 max
C
1.778 [TP]
.070 [TP]
0
.50±.10
.020
E
35.57
1.400
=:~~:
F
.9 min
.035 min
G
3.2±.3
.126 ± .012
H
.51 min
.020 min
4.31 max
.170 max
5.08 max
.200 max
15.24 [TP]
.600 [TP)
L
13.2
.520
M
.25
K
=:~~
.10
22
=:gg:
Note:
[1] Each lead centerline Is located within .17
mm [.007 Inch] 01 Its true position [TP] at
maximum material condition.
[2]lIem "K" to center 01 leads when lormed
parallel.
J
M
0·15°
83-0035736
8-10
NEe
PACKAGING INFORMATION
42-Pln Ceramic Piggyback DIP
A
Item
Millimeters
A
55.88 max
2.200 max
B
20.32
.800
C
2.5 ± .25
.100 ± .010
0
0.46± .05
.018 ± .002
5D.80
2.000
1.02
.040
G
3.2 min
.126 min
H
1.02 min
.040 min
3.0 max
.118 max
Inches
4.32 max
.170 max
K
15.24
.600
15.24
.600
M
.25 ± .05
.001 ± .010
N
33.02
1.300
0
2.54± .25
.100 ± .010
l
00000000000000
r
00000000000000
21
83-0035746
44-Pln Plastic Mlnlflat
A
Item
A
Millimeters
Inches
13.6 ±.4
.535 ~:~~!
~:~~:
10 ±.2
.394
c
10±.2
.394 ~:~~:
0
13.6 ±.4
.535 ~:~~~
F
G
H
M
8.0
.315
1.0
1.0
.039
.039
.35
~:~~
B
.014 ~:~~:
.8 [TPJ
Note 1
.031 [TPJ
1.8 ±.2
.071
1.0 ±.2
.039 ~:~~:
E
C
0
~:~~:
.15~:~~
.006 ~:~~~
.15
.006
Note 2
o
---~----
N
1.45±.1
.057 ~:~~:
0
0.0±.1
1.65 max
0.000 ±.004
.065 max
G
H
Note:
[1 J Each lead centerline is located within
.15 mm [.006 inchJ of its true
position [TPJ at maximum material
condition.
[2J Flat within .15 mm [.006 inchJ total.
83-0012328
8-11
~EC
PACKAGING INFORMATION
52-Pin Plastic Mlnillat
A
B
Item
Millimeters
Inches
A
21.0±.4
.B27±.016
B
14±.2
.551
c
1.0 [TP]
Note 1
.039 [TP]
o
~:~~:
~:~~:
.40±.10
.016
1.0
.039
3.5±.2
.13B ~:~~:
A
~:~~:
G
2.2±.2
.OB7
H
.15~:~~
.006 ~:~~:
.15
Note 2
.006
K
2.6~:~~
.102
.1±.1
.004 ±.004
~:~~:
Note:
E
[1] Each lead centerline Is located within
.20 mm [.OOBlnch] of Its true
position [TP] at maximum material
condition.
[2] Flat within .15 mm [.006 Inch] total.
o
c
83-0009328
54-Pin Plastic Mlnlflat
Item
Millimeters
Inches
A
13.5±.4
.531
B
9.5±.2
.374 ±.OOB
C
9.5±.2
.374 ±.OOB
0
13.5±.4
.531
E
B.45
.333
~:~~
~:~~~
.5
.020
G
.B5
.033
H
.30±.10
.012
.65 [TP]
Note 1
.026 [TP]
2.0±.2
.079
K
M
A
-+I
:'::~~:
~:~~:
1.2±.2
.047~:~~
.15~:~~
.006 ~:~~:
.15
Note 2
.006
N
1.5±.1
.059 ±.004
0
0.1 ±.1
0.004 ±.004
P
0.1 ±.1
0.004±.OO4
Q
1.Bmax
.071 max
F
J
E
C
0
lQ}S ~=}
0
G
H
Note:
[1] Each lead centerline Is located within
.15 mm [.006 Inch] of Its true
position [TP] at maximum material
condition.
[2] Flat within .15 mm [.006 Inch] total.
83-0038548
8-12
NEe
PACKAGING INFORMATION
54-Pin Plastic Mlnlflat (inverted leads)
1~'~
A
Millimeters
Inches'
A
13.9±.4
547
B
9.5±.2
c
9.5±.2
.374 ±.008
o
13.9±.4
.547 ±.016
Item
.
1
.374~?b8
8.45
.333
.5
.020
G
.85
.033
H
.30±.10
.012
.65 [TP]
Note 1
.026 [TP]
K
B
6
~:~~:
2.2±.2
.079
~:~~:
.9 ±.2
.047
~:~~:
.15~:~~
.006
~:~~:
M
.15
Note 2
.006
N
1.5±.1
.059 ±.004
o
0.1 ±.1
0.004 ±.004
P
0.1 ±.1
0.004 ±.004
Q
1.8 max
.071 max
Note:
[1] Each lead centerline Is located within
.15 mm [.006 inch] of its true
position [TP] at maximum material
condition.
[2] Flat within .15 mm [.006 inch] total.
E
C
o
0
P
lA-Or
J
H
G
'~
INi==~
J
83-003855B
64-Pin Plastic Shrink DIP (750 mil)
Item
Millimeters
Inches
A
58.68 max
2.311 max
B
1.78 max
.07 max
C
1.778 [TP]
.07 [TP]
0
.5 ±.10
.02
2.17
.9 min
.035 min
G
3.2±.3
.126 ±.012
H
.51 min
.02 min
4.31 max
.17 max
5.08 max
.2 max
19.05 [TP]
.75 [TP]
17
M
.25
33
+ .004
- .005
55.12
K
64
S
.669
+.10
- .05
.01
+ .004
- .003
Notes:
1. Each lead centerline is located within .17
mm [.0007 inch] of its true position [TP] at
max!mum material condition.
2. Item "K" to center of leads when formed
parallel.
~:It
F O e
M
0-15'
E
83-001494B
8-13
NEe
PACKAGING INFORMATION
64-Pln Plastic M'n"'at
Item
MIllimeters
Inches
A
24.7 ±.4
.972 ::~~~
B
20±.2
.795 ::~~:
c
14±.2
.551
o
1B.7±.4
0.736±.016
12.0
.472
1.0
.039
G
1.0
.039
H
.40±.10
1.0 [TP]
Note 1
K
::~~:
.016 ::~~:
.039 [TP]
.093 ::~~:
1.2±.2
.047 ::~~:
::~:
-+I
2.35 ±.2
.15
A
0
1J
.006 ::~~:
Note 2
2.05 ::~
.OB1
o
0.1 ±.1
0.004 ±.004
::~~:
Note:
[1] Each lead centerline Is located within
.20 mm [.OOB Inch] of Its true
position [TP] at maximum material
condition.
[2] Flat within .15 mm [.006 Inch] total.
0
I
19 20
------------------M
.15
.006
N
c
!
o
G
H
~+
K
63·0009338
64-Pln Plastic QUIP
Item
Millimeters
Inches
A
41.B max
1.65 max
C
2.54
.100
0
.5±.1
.020±.004
E
39.37
1.55
F
1.27 min
.050 min
G
3.6
.142
H
3.2 min
.126 min
24.13 ±1.05
.950 ±.041
19.05 ±1.05
.750 ±.041
K
16.5
N
.25
.650
::~:
tri-----------;'ll"
,. II' I·I-------t
..
K
-----------~~-
.010 ::~~~
~~
F O e
p:
~B
11
!}I+--.
N _ _---+I
M
.1.1
63-0015068
8-14
NEe
PACKAGING INFORMATION
64-Pln Shrink Cerdlp with Window
Item
Millimeters
Inches
A
58.68 max
2.311 max
B
1.78 max
.070 max
C
1.778 [TP]
.070 [TP]
0
.46 ±.05
.018 ±.002
E
55.11
2.17
F
.08 min
.003 min
G
3.5 ±.3
.138 ±.012
H
1.0 min
.093 min
I
3.0
.118
J
5.08 max
.200 max
K
19.05 [TP]
.750 [TP]
L
18.8
.740
M
.25 ±.05
.010 ±.002
7.62 dla
N
~::::::::::i;I::::::::::J
A
K
L
~+
.300 dla
Note:
[1] Each lead centerline Is located within
.25 mm [.01 Inch] of Its true
position [TP] at maximum material
condition.
[2] Item uK" to center of leads when formed
parallel.
I
E
I
I
~~
83-0039338
64-Pln Ceramic QUIP with Window
I'
Item
A
Millimeters
Inches
42.0 max
1.65 max
B
26.67
1.05
C
2.54±.25
.1 ±.01
0
.46 ±.05
.018 ±.002
E
38.10
1.5
.04
F
1.02
G
1.27 ±.25
.05±.01
H
1.02 min
.04 min
.194 max
I
4.95 max
J
3.2 min
.126 min
K
24.13
.95
L
19.05
.75
M
.25 ±.05
.01 ±.002
N
8.89 dla
.350 dla
D
A
-I,-
~
B
H
l~~~~~~~~~r§J,
E
I
r
I
...,1...,
:rJ
I
I
~~M
I
L
K
83-0039298
8-15
NEe
PACKAGING INFORMATION
64-Pln Ceramic Piggyback QUIP
A
Item
Millimeters
Inches
A
42.0 max
1.65 max
B
26.67
1.050
C
2.54 ±.25
.100 ±.010
0
.46 ±.05
.018 ±.002
38.10
1.500
F
1.02
.040
G
1.27±.25
.050 ±.010
H
1.02 min
.040 min
3.9 max
.154 max
4.45 max
.175 max
3.2 min
.126 min
33.02
1.300
M
2.54 ±.25
.100±.010
N
.25 ±.05
.010 ±.002
0
15.24
.600
P
19.05
.750
Q
24.13
.950
K
00000000000000
D
D
B
00000000000000
o
83-0038448
68-Pln Plastic Leaded Chip Carrier (PL CCJ
Item
Millimeters
Inches
25.2 ±.2
.992 ±.008
24.20
.953
C
24.20
.953
0
25.2 ±.2
.992 ±.008
A
B
60
61
44
43
~:~~~
1.94±.15
_076
.6
.024
G
4.4±.2
.173 ~:~~:
H
2.8±.2
.110 ~:~~:
.7mln
.028 min
3.6
.142
1.27 [TP]
Note 1
.050 [TP]
.7
.028
M
.40±.10
.016 ~:~~:
N
23_12 ±.20
.910 ~:~~:
0
.15
Note 2
.006
P
1.0
.040
K
A
Q
R .8
R .031
R
.20 ~:~~
.008 ~:~~~
Note:
[1] Each lead centerline is located within
.12 mm [.005 Inch] of its true
position [TP] at maximum material
condition.
[2] Flat within .15 mm [.006 inch] total.
68
-B-++-+-----+--------f:1-
C
0
F
GIH4~j_
L--:--oU--L--~:+·Q
I..
K
M
L
P
.,
I
N
83-0037928
8-16
NEe
PACKAGING INFORMATION
80-Pin Plastic Mlnlflat
Item
A
Millimeters
Inches
A
24.7 ±.4
.972 ~:~~~
B
B
20±.3
.795 ~:~~:
C
14 ±.2
.551
o
18.7±.4
.736 ±.016
12
.472
~:~~:
I
1.0
.039
G
.8
.031
H
.35 ±.1
.014
.8 [TPJ
Note 1
.031 [TPJ
~-+-~
~:~~~
2.35 ±.3
.093 ~:~~:
1.2±.2
.047 ~:~~:
o
E
C
0
I
.006 ~:~~~
M
.15
Note 2
.006
~:~
N
2.05
o
.1±.1
G
H
.004 ±.004
EF
Note:
[1J Each lead centerline is located within
.15 mm [.006 inchJ 01 its true
position [TPJ at maximum material
condition.
[2J Flat within .15 mm [.006 inchJ total.
'
o
83·0012308
84-Pin Plastic Leaded Chip Carrier (PLCC)
A
Item
Millimeters
Inches
1.197 ±.008
1.154
A
30.4 ±.2
B
C
29.30
29.30
0
30.4 ±.2
1.197 ±.008
1.95±.15
.077 ~:~~~
.6
.024
G
4.4±.2
.173 ~:~~:
H
2.5±.2
.098 ~:~~:
1.154
.6 min
.024 min
3.7
.146
1.27 [TPJ
Note 1
.050 [TPJ
.7
.028
M
.40±.10
.016 ~:~~:
N
28.51 ±.20
0
.15
Note 2
.006
P
1.0
R .8
.040
R .031
.20 ~:~~~
.008 ~:~~:
K
Q
R
1.122 ~:~~:
Note:
[1 J Each lead centerline is located within
.12 mm [.005InchJ 01 Its true
position [TPJ at maximum material
condition.
[2] Flat within .15 mm [.006InchJ total.
Q
8-17
NEe
Notes:
t-IEC
Notes:
NEe
Notes:
Source Exif Data:
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