1987_Mostek_Communications_Products 1987 Mostek Communications Products
User Manual: 1987_Mostek_Communications_Products
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- - - - - - TABLE OF CONTENTS - - - - - GENERAL INFORMATION
Page
Alphanumerical Index ................................................. iv
OrderiFig Information (What #'s Mean & How To) ............................ v
List of Sales Offices .................................................. vii
List of Reps ........................................................ viii
List of Distributors .................................................... ix
CHAPTER 1 - DATA COMMUNICATIONS
PACKET SWITCHING
MK5025 CCITT X.25 Link Level Controller ............................... 1-1
MK5025 Technical Manual ........................................... 1-19
ETHERNET
MK68590 - LANCE, IEEE 802.3 Ethernet Controller ....................... 1-75
MK68590 - LANCE Technical Manual .................................. 1-91
MK68590 - Application Note: Interfacing LANCE to MK68000 .............. 1-153
MK68591/2 - IEEE 802.3 Ethernet Serial Interface Adaptor ................. 1-247
STARLAN
MK5030 - 1M Bit/Sec Starlan Hub .................................... 1-261
MK5032 - Starlan Controller (1 - 10 Mbps) .............................. 1-277
MK5033 - Generic Manchester Encoder/Decoder ........................ 1-293
MK5035 - Starlan Station (Use with MK68590, 82586 at 6 & 8 MHz) ........ 1-309
MK50351 - Starlan Station (Use with MK5032, 82588 at 8 & 10 MHz) ....... 1-323
CHAPTER 2 - MODEM ICs
SINGLE CHIP
TSG7515 - Bell 212A MODEM - 1200, 600 BPS DPSK; 300 BPS FSK
(Bell 212A, Bell 103, & V.22A1B) .............. 2-1
Application Note - TSG7515 ........................................... 2-17
LINE INTERFACE
TEA7868 - MODEM to Telephone Line Direct Interface ................... 2-103
DSP BASED MODEMS - See DIGITAL SIGNAL PROCESSORS & PERIPHERALS
MODEM Standards Coverage ........................................ 2-117
- V.32 Echo Cancelling Software Application Note
(Contact factory direct 214/466-6316)
TS7524 - 2400 bps Chip Set - (V.22 Bis, V.22, Bell 2121V.23, V.21, Bell 103) ... 2-119
CHAPTER 3 - DIGITAL SIGNAL PROCESSORS & PERIPHERALS
DIGITAL SIGNAL PROCESSORS
TS68930 - High Performance, 25 MHz ..•............................... 3-1
TS68931 - ROM-less version of TS68930 ......................•......... 3-1
DEVELOPMENT TOOLS
SOFTWARE:
PSI MAC - Macro Assembler for VAX & IBM Hosts ...................... 3-53
PSIMUL - Simulator for VAX Host ................................... 3-55
PSILIB - DSP Library for VAX & IBM Hosts ............................ 3-57
HARDWARE:
EVAPSI - Real.:rime Emulation Board ................................ 3-59
HDSPSI - Hardware Development System ............................. 3-61
EVMMAFE - Evaluation Board for MODEM Analog Front End ............. 3-63
PSI REP ROM - TS68931 Module with External Coefficient and
Program Memory ............................................... 3-65
- - - - - - - THOMSON COMPONENTS MOSTEK - - - - - - -
- - - - - - - TABLE OF CONTENTS - - - - - - CHAPTER 3 (cant'd)
Page
ANALOG FRONT END
TS68950 - Analog Front End Transmitter ................................ 3-67
TS68951 - Analog Front End Receiver .................................. 3-81
TS68952 - Analog Front End Clock Generator .......................... 3-105
CHAPTER 4 - SUBSCRIBER LINE CARD COMPONENTS
SUBSCRIBER BOARD ICs
CODEC II G (CODEC, FILTERS, & TIME SLOT ASSIGNMENT)
TS5070 - Two port assignments and 6 interface latches ..................... 4-1
TS5071 - One port assignment and 5 interface latches ..................... 4-1
CODEC W/FILTER (COMBINATION)
ETC5054 - wLaw, Single Channel ..................................... 4-25
ETC5064 - wLaw, Single Channel with Power Amplifiers ................... 4-39
ETC5057 - A-Law, Single Channel ..................................... 4-25
ETC5067 - A-Law, Single Channel with Power Amplifiers ................... 4-39
CODEC's
MK5116 - wLaw, Serial Output ....................................... .4-53
MK5151 - wLaw, Serial Output with AB signalling ........................ 4-63
MK5156 - A-Law, Serial Output ........................................ 4-75
- App. Note "Integrated PCM CODEC Technology Update ................. 4-89
FILTERS
ETC5040 - CMOS Single channel PCM filter ............................ 4-95
SUBSCRIBER LINE INTERFACE CIRCUIT (SLlC)
TDB7711 - Low Voltage Interface ...................................... 4-105
TDBm2 - High Voltage Interface ..................................... 4-105
TRUNKICs
EFB73321 - PCM Clock Recovery ..................................... 4-113
Application Note: EF73321 & EF7333 .................................. 4-125
CHAPTER 5 - TELEPHONE SET ICs
DIALERS
REPERTORY TONEPULSE™ DIALERS
Comparison of TCMC TonePulse'" Dialers ................................ 5-1
MK5375 - Ten Memory TonePulse'" switchable dialer ....................... 5-3
MK5376 - Same as MK5375 with added options .......................... 5-15
MK53761 - Ten Memory TonePulse Dialer with Continuous Tone ............ 5-25
MK53762 - Same as MK53761, with Single Key Redial of the Ten Memories ... 5-37
MK53763 - 13 Memory Repertory World Dialer'" with Single Key Autodialing ... 5-49
- Applications Note: MK53761 ......................................... 5-51
- Applications Note: MK53762 ........................................ 5-53
- Applications Note: "MK5375 Typical Applications: No Battery
Back-Up & Continuous Tone" ....................... 5-55
- - - - - - - THOMSON COMPONENTS MOSTEK - - - - - - ii
- - - - - - TABLE OF CONTENTS - - - - - CHAPTER 5 (cont'd)
Page
TONEPULSE™ DIALERS
MK5370 • Low cost TonePulse™ Dialer for Low End Apps ................... 5·61
MK5371 • TonePulse™ with Redial ..................................... 5·73
MK53721 • TonePulse™ World Dialer'" with Redial ........................ 5·89
MK53731 • TonePulse™ with 28 Digit Redial and Continuous Tone ........... 5·91
TONE DIALERS
MK5380 • Industry Standard DTMF Generator ........................... 5·103
SINGLE CHIP TELEPHONES
TEA3046 • 2 to 4 Wire Conversion and DTMF Generator .................. 5·111
LOUD SPEAKER AMPLIFIERS
TEA7531 • Loudspeaker Amplifier .................................... 5·125
CHAPTER 6 • HIGH SPEED DATA CONVERSION
FLASH CONVERTERS
TS8306 • 6·Bit Flash ADC, 20 MHz ..................................... 6·1
TS8308 • 8·Bit Flash ADC, 20 MHz ..................................... 6·7
TS8328 • 8·Bit Flash ADC (min. version of TS8308) ....................... 6·19
CHAPTER 7 • INTEGRATED CIRCUITS SHORT FORM CATALOG
- - - - - - - THOMSON COMPONENTS MOSTEK - - - - - - iii
- - - - - ALPHANUMERICAL INDEX - - - - - - - Device
EFB73321
ETC5040
ETC5054
ETC5057
ETC5064
ETC5067
EVAPSI
EVMMAFE
HDSPSI
MK5025
MK5030
MK5032
MK5033
MK5035
MK50351
MK5116
MK5151
Page
4-113
4-95
4-25
4-25
4-39
4-39
3-59
3-63
3-61
1-1
1-261
1-277
1-293
1-309
1-323
4-53
4-63
Device
MK5156
MK5370
MK5371
MK53721
MK53731
MK5375
MK5376
MK53761
MK53762
MK53763
MK5380
MK68590
MK68591
MK68592
PSI MAC
PSIMUL
PSILIB
Page
Device
Page
4-75
5-61
5-73
5-89
5-91
5-3
5-15
5-25
5-37
5-49
5-103
1-75
1-247
1-247
3-53
3-55
3-57
PSIREPROM
TDB7711
TDBm2
TEA3046
TEA7531
TEA7868
TS5070
TS5071
TS68930
TS68931
TS68950
TS68951
TS68952
TSG7515
3-65
4-105
4-105
5-111
5-125
2-103
4-1
4-1
3-1
3-1
3-67
3-81
3-105
2-1
- - - - - - - THOMSON COMPONENTS MOSTEK - - - - - - - - - - . ; .
iv
ET C, 2716 ,Q, _ I 55 ,M, BIB
I
lHOMSONSC
prefix
Ir[l
I
Ir fl
~rn ~
Quality level
s-"'
I
.mperature ,.nge
C : Ceramic Oil
'-' , NMOS
C , CMOS
J : Cerdip 01 L
N : PI.tic OIL
Q : UV ~ndow cerdp
L : Lowpower
TS
: Standard
: MIL-STD-8838 class B
Operlting
Packogo
Tochnology
~
W
BIB
'-'
O"C,+ 70°C
E : -2SoC,+ 70°C
V ; -40o C,+ 85°C
M : -55°C,+ 12SoC
71191B ,M,J BIB
r,r- n
Quality level
'-'
BIB
Opontinl
• "",'Itu .. , . . .
'-' , NMOS
·C ,CMOS
L
: Lowpower
C
O"C,+ 70°C
I
- 25°C. + 8SoC
M
V
-5SoC,+ 125°C
-400C, + 85°C
V
: Standard
: MIL-STD·883B class B
I
Pack...
C : Ce ramie 01 L
E : Cer."ic Lee
FN : P'.ticc:hip-carrter
Cordip OIL
J
PI.tic OIL
P
Q
UV windowoerc:ip
Pin Grid ArrlN
II
I MK
.
I
68901
I
P I 00
I
L
f-
2 I 3 LETTER PREFIX
MK
One or two numerical characters
defining specific device performance characteristics and operating temperature range.
= Standard Products
DEVICE
MKJ = Military Hi-Rei
fully compliant to
MIL-M-38510
NUMBER
MKB = Military Hi-Rei
.
screening to MILSTD-883 Class B
for extended temperature
range
operation.
PACKAGE
'--
p
- Gold size-brazed ceramic DIP
J
- CER-DIP
N - Epoxy DIP (Plastic)
MKX = Military Hi-Rei
screening to customers SCD
MKI
DASH NUMBER
K - Tin-side-brazed ceramic DIP
T
= Industrial
Hi-Rei
screening for
-40"C to +85°C
operation.
- Ceramic DIP with trans parent lid
E - Ceramic leadless chip carrier
0 - Dual density RAM-PAC
F
EF
68AOO
I r r'
I
11
- Flat pack
e,M , BIB
II
lr
Qualtty level
I
I
......
BIB
BIC
: Standard
: MIL·STO·8B3B cia•• B
: MIL·STD·BB3C cla.s B
I
P.. iuorIt
T....noI_
A
B
G
X
NMOS'
CMOS I Bulk
CMOS lSi g...
Pr~totype
C
Ceramic OIL
E
CLCC
Cerdip OIL
PLCC
PI.tic OIL
Pin GridArNrt/
J
FN
P
R
Opwa1ing
tempetature ,.-t..
OOC, + 7o"C
L- :
V : -40oC.+ 85°C
M : -55"C.+ 125°C
.
Mey be omitted.
vi
THOMSON - MOSTEK
TECHNICAL SUPPORT, PRODUCT MARKETING
FOR INTEGRATED CIRCUITS: (Corporate Headquarters)
FOR DISCRETE DEVICES AND RF & MICROWAVE TRANSISTORS:
16 Commerce Drive
1310 Electronics
Carrollton, TX 75006
2141466-6000
TWX 910-860-5437
Montgomeryville, PA 18936-1002
215/362-8500
FAX 2151362-1293
U.S. AND CANADIAN SALES OFFICES:
WESTERN AREA:
CENTRAL AREA:
EASTERN AREA:
Thomson Components - Mostek Corporation
Thomson Components - Mostek Corporation
Thomson Components - Mostek Corporation
2540 Mission College Blvd.
Suite 104
Santa Clara, CA 95054
4081970-8585
FAX 408-970-8737
1310 Electronics
MSI137
Carrollton, TX 75006
83 Cambridge Street
Suite 2A
Burlington, MA 01803
2141466-6844
617/273-3310
FAX 617/272-2467
TWX 910-860-5437
Thomson Components - Mostek Corporation
Thomson Components - Mostek Corporation
18004 Skypark Circle
Suite 140
Irvine, CA 92714
7141250-0455
FAX 7141261-1505
600 N. Meacham
Suite 304
Schaumburg, IL 60196
Thomson Components - Mostek Corporation
The Pavilions at Greentree
Route #73, Suite 101
Marlton, NJ 08053
312/490-1890
FAX 3121490-1899
609/596-9200
FAX 609/424-7437
Thomson Components - Mostek COrporation
Thomson Components - Mostek Corporation
Thomson Components - Mostek Corporation
6203 Variel Ave.
Unit A, PO. Box 4051
Woodland Hills, CA 91367
8181887-1010
FAX 818/702-0725
3215 Steck Ave.
Suite 202
Austin, TX 78758
4414 Evangel Cr. #C
Huntsville, AL 35816
2051830·9036
FAX 2051830-9038
512/451-4061
TWX 910-674-2007
Thomson Components - Mostek Corporation
Thomson Components - Mostek Corporation
601 South Bowen SI.
Longmont, CO 80501
303/449-9000
FAX 303/651-7976
Thomson Components - Mostek Corporation
1000 E. Bell
Phoenix, AZ 85222
6021867-6340
FAX 6021867-6102
387 Hooker Avenue
Office No.2
Poughkeepsie, NY 12603
9141454-8813
FAX 9141454-1320
CANADA
Thomson Components - Mostek Corporation
16 Davenrich Court
Brampton, Ontario L6Z lW6
4161846-5008
FAX 4161454-4328
Thomson Components - Mostek Corporation
5890 Sawmill Rd.
Suite 204
Dublin, Ohio 43017
6141761-0676
FAX 6141761-2305
Thomson Components - Mostek COrporation
7155 SW varns SI.
Tigard, OR 97223-6057
5031620-5517
FAX 503/639-3591
Western Canada
Thomson Components - Mostek Corporation
Call 503/620-5517
6045 Atlantic Blvd.
Suite 104
Norcross, GA 30071
4041662-1588
FAX 404/662-1561
FOR ALL OTHER COUNTRIES
Thomson Semiconducteurs
43, Avenue de L:Europe
78140 Velizy-Viliacoublay/France
Tel: (1) 39 46 97 19rrelex: 204 780 F
or contact Corporate Headquarters
vii
u.s.
AND CANADIAN REPRESENTATIVES
ALABAMA
Rep, Inc.
11535 Gilleland Rd.
Huntsville, AL 35803
(205) 881-9270
FAX (205) 882-6692
CONNECTICUT
Scientific Components
315 Highland Ave., Suite 101
Cheshire, CT 06410
(203) 272-2963
FAX (203) 271-3048
FLORIDA
Lawrence Associates
5021 N. Dixie Hwy.
Boca Raton, FL 33431
(305) 368-7373
Sales Engineering Concepts, Inc.
926 Great Pond Dr.
Suite 2002
Altamonte Springs, FL 32714
(305) 682-4800
FAX (305) 682-6491
Sales Engineering Concepts, Inc.
1000 S. Federal Hwy.
Suite 204
Deerfield Beach, FL 33441
(305) 426-4601
TWX 510-600-7740
GEORGIA
Rep, Inc.
1944 Northlake Parkway
Tucker, GA 30084
(404) 938-4358
FAX (404) 938-0194
ILLINOIS
Eagle Technical Sales, Inc.*
1805 B. Hicks Rd.
Rolling Meadows, IL 60008
(312) 991-0700
INDIANA
J & 8 Engineering Sales Co."
2420 COliseum Blvd.
FI. Wayne, IN 46805
MIS Sales Associates, Inc.
7319 W. Jefferson Blvd.
Ft. Wayne, IN 46804
(219) 436-3023
FAX (219) 436-3026
IOWA
Rep Associates"
980 Arica Ave.
Marion, fA 52302
(319) 373-0152
KANSAS
Rush & West Associates
107 N. Chester Street
Olalhe, KS 66061
(913) 764-2700
TWX 910-380-8110
MARYLAND
Tri·Mark Inc.
1410 Crain Hwy. NW
Glen Burnie, MD 21061
(301) 761-6000
FAX (301) 761-6006
MASSACHUSETTS
AID Nova Sales, Inc'83 Cambridge St.
Suite 20
Burlington, MA 01803
(617) 270-9600
FAX (617) 272-2467
Conti·Younger Assoc.
12 Blanchard Rd.
Burlington, MA 01803
(617) 273-1583
FAX (617) 270-0301
MICHIGAN
Electronic Sources, Inc.
8014 W. Grand River
Suite 6
Brighton, MI 48116
(313) 227-3598
FAX (313) 227-5655
Centech, Inc'10312 E. 63rd Terrace
Ray1own, MI 64133
(816) 358-8100
MINNESOTA
Horizon
8053 East Bloomington Freeway
Bloomington, MN 55420
(612) 884-6515
FAX (612) 888-3073
MISSOURI
Rush & West Associates
2170 Mason Rd.
St. Louis, MO 63131
(314) 965-3322
TWX 910-752-653
TELEX 752 653
NEW JERSEY
Tritek Sales, Inc.
21 E. Euclid Ave.
Haddonfield, NJ 08033
(609) 429-1551
FAX (609) 429-4915
NE Components
189·191 Godwin Ave.
Wyckoff, NJ 07481
(201) 848-1100
NEW YORK
Empire Technical Assoc.
33 West State St.
Suite 211B
Binghamton, NY 13901
(607) m-0651
Empire Technical Assoc.
1551 E. Genesse St.
Skaneateles, NY 13152
(315) 685-5703
GT Sales
34 Grand Blvd.
Brentwood, NY 11717
(516) 231-0270
FAX (516) 273-1247
NORTH CAROLINA
Rep, Inc.
6407 Idlewild Rd.
Suite 425
Charlotte, NC 28212
(704) 563-5554
FAX (704) 563-7507
Rep, Inc.
2500 Gateway Centre Blvd.
Suite 400
Morrisville, NC 27560
(919) 469-9474
FAX (919) 481-3877
MIS Sales Associates, Inc.
1425 E. 86th St., Suite 3
Indianapolis, IN 46240
(317) 257-8916
.. RF & Microwave Transistors Only
viii
OHIO
Five Star Electronics
6200 S.O.M. Center Road
Suite B 21
Solon, OH 44139
(216) 349-1611
Tom Mulligan Co.·
166 N.W. Professional Plaza
Columbus, OH 43220
(614) 457-2242
PENNSYLVANIA
M. Lader Company
456 Germantown Pike
Lafayette Hill, PA 19444
(215) 825-3177
TENNESSEE
Rep, Inc.
113 S. Branner St.
Jefferson City, TN 37760
(615) 475-9012
FAX (615) 475-6340
WISCONSIN
Heartland Technical Marketing
3846 Wisconsin Ave.
Milwaukee, WI 53208
(414) 931-0606
CANADA
Solution Electronic Sales
8557 Government St.
Suite 103
Burnaby, B.C.
Canada V3N 459
(604) 421-9111
FAX (604) 421-2373
u.s.
AND CANADIAN DISTRIBUTORS
ALABAMA
Marshall Industries
3313 S. Memorial Pkwy.
Huntsville, AL 35801
(205) 881-9235
Quality Components, S.E.
4900 University Square #207
Huntsville, AL 35817
(205) 830-1881
Pioneer Technologies Group
4825 University Square
Huntsville, AL 35805
(205) 837-9300
Schweber Electronics
4930 A Corporate Drive
Huntsville, AL 35805
(205) 895-0480
M
ARIZONA
Kierulff Electronics
4134 E. Wood Street
Phoenix, AZ 85040
(602) 437-0750
Marshall Industries
835 West 22nd St.
Tempe, AZ 85282
(602) 968-6181
Schwaber Electronics
11049 North 23rd Drive
Suite 100
Phoenix, AZ 85029
(802) 997-4874
ARKANSAS
See Oklahoma
CALIFORNIA
Integrated Electronics Corp.
7000 Franklin Blvd., Suite 625
Sacramento, CA 95823
(916) 424-5297
Integrated Electronics Corp.
2170 Paragorr1)rive
San Jose, CA 95131
(408) 435-1000
ITAL Sales
15405 Proctor Avenue
City of Industry, CA 91745
(818) 966-8515
Kierulff Electronics
9800 Variel Avenue
Chatsworth, CA 91311
(818) 407-2500
Kierulff Electronics
5650 Jillson St.
Los Angeles, CA 90040
(213) 725-0325
Kierulff Electronics
f!il97 Balboa Avenue
San Diego, CA 92123
(819) 278-2112
Kierulff Electronics
1180 Murphy Avenue
San Jose, CA 95131
(408) 971-2800
Marshall Industries
One Morgan
Irvine, CA 92715
(714) 458-5395
Marshall Industries
9710 DeSoto Avenue
Chatsworth, CA 91311
(818) 407-0101
Marshall Industries
3039 Kilgore Ave., #140
Rancho Cordova, CA 95670
(916) 635-9700
Marshall Industries
10105 Carroll Canyon Rd.
San Diego, CA 92131
(619) 578-9600
Marshall Industries
336 Los Coches St.
Milpitas, CA 95035
(408) 943-4600
Schweber Electronics
21139 Victory Blvd.
Conoga Park, CA 91303
(818) 999-4702
Schwaber Electronics
1225 West 190th Street
Suite 360
Gardena, CA 90248
(213) 327-8409
Schweber Electronics
17822 Gillette Avenue
Irvine, CA 92714
(714) 863-0264
FAX (714) 863-0200 (X500)
Schweber Electronics
1m Tribute Rd. Suite B
Sacramento, CA 95815
(916) 929-9732
FAX (916) 929-5608
COLORADO
Integrated Electronics Corp.
5750 N. Logan Street
Denver, CO 80216
(303) 292-6121
Schwaber Electronics
215 North Lake Blvd.
Altamonte Springs, FL 32701
(305) 331-7555
TWX 510-954-0304
Kierulff Electronics
7060 South Tuscan Way
Englewood, CO 80112
(303) 790-4444
Schwaber Electronics
3665 Park Central Blvd. N.
Pompano Beach, FL 33064
(305) 977-7511
TWX 510-954-0304
Marshall Industries
7000 North Broadway
Denver, CO 80221
(303) 427-1818
Schweber Electronics
8955 E. Nicholas, Bldg. 2
Englewood, CO 80221
(303) 799-0258
CONNECTICUT
Greene-Shaw
1475 Whalley Avenue
New Haven, CT 06525
(203) 397-0710
TWX 92-2498
Marshall Industries
20 Sterling Drive
Barnes Industrial Park, N.
P.O. Box 200
06492-0200
Wallingford,
(203) 265-3822
cr
Pioneer-Standard
112 Main Street
Norwalk, CT 06851
(203) 853-1515
TWX 710-468-3373
FAX (203) 838-9901
Schwaber Electronics
Commercial Industrial Park
Finance Drive
Danbury, CT 06810
(203) 748-7080
TWX 710-456-9405
Schweber Electronics
6750 Nancy Ridge Drive
San Diego, CA 92121
(619) 450-0454
TWX 910-335-1155
DELAWARE
See New Jersey
Pennsylvania
Schwaber Electronics
90 E. Tasman Drive
San Jose, CA 95131
(408) 946-7171
FLORIDA
All American Semiconductor
16251 N.W. 54th Avenue
Miami, FL 33014
(305) 621-8282
800-327-6237
Zeus Components
1130 Hawk Circle
Anaheim, CA 92807
(714) 632-6880
TWX 910-591-1696
FAX (714) 630-8770
Zeus Components
1580 Old Oakland Road
Suite C205lC206
San Jose, CA 95131
(408) 998-5121
TWX 408-628-98083
FAX (408) 998-0285
Marshall Industries
4205 34th St., S.w.
Orlando, FL 32811
(305) 841-1878
(305) 841-1878
Pioneer Technologies Group
337 S. North Lake, #1000
Altamonte Springs, FL 32701
(305) 834-9090
TWX 810 853-0284
w
Pioneer Technologies Group
674 S. Military Trail
Deerfield Beach, FL 33441
(305) 428-8877
TWX 510-955-9653
Kierulff Electronics
14101 Franklin Avenue
Tustin, CA 92680
(714) 731-5711
ix
Zeus Components
1750 West Broadway
Suite 114
Oviedo, FL 32765
(305) 365-3000
TWX 910-380-7430
FAX (305) 365-2356
GEORGIA
Dixie Electronics
1234 Gordon Park Road
Augusta, GA 30901
(404) 722-2055
Pioneer Technologies Group
3100 F. Northwoods Place
Norcross, GA 30071
(404) 448-1711
TWX 810-766-4515
Quality Components
6145 N. Belt Parkway #B
Norcross, GA 30071
(404) 449-9508
TWX 510-601-5297
629-32421
Schwaber Electronics
303 Research Drive
Suite 210
Norcross, GA 30092
(404) 449-9170
TWX 810-765-1592
ILLINOIS
Advent Electronics
7110-16 N. Lyndon St.
Rosemont, IL 60018
(312) 297-6200
Kierulff Electronics
1140 W. Thorndale Ave.
Itasca, IL 60143
(312) 250-0500
Marshall Industries
1261 Wiley Road
#F
Schaumburg, IL 60195
(312) 490-0155
Pioneer-Standard
1551 Carmen Drive
Elk Grove Village, IL 60007
(312) 437-9680
Schweber Electronics
904 Cambridge Drive
Elk Grove Village, IL 60007
(312) 364-3750
TWX 910-222-3453
u.s.
AND CANADIAN DISTRIBUTORS
Kierulff Electronics
13 Fortune Drive
MISSOURI
PioneerMStandard
Advent Electronics
Kierulff Electronics
8446 Moller Road
Indianapolis, IN 46268
Billerica, MA 01821
(617) 667-8331
11804 Borman Drive
St. Louis, MO 63146
(314) 997-4956
TWX 910-762-0721
840 fairport Park
Fairport. NY 14450
(716) 381-7070
TWX 510-253-7001
FAX (716) 381-5955
INDIANA
(317) 872-4910
TWX 810-341-3228
Lionex Corporation
Marshall Industries
6990 Corporate Dr.
Indianapolis, IN 46278
Wilmington, MA 01887
(617) 657-5110
FAX (617) 657-6008
36 Jonspin Road
(317) 297-0483
Pioneer-Standard
6408 Castleplace Drive
Indianapolis, IN 46250
Marshall Industries
One WIlshire Road
Burlington, MA 01803
(617) 272-8200
Schweber Electronics
502 Earth City Expressway
Suite 203
Earth City, MO 63045
(314) 739-0526
TWX 43-4065
MONTANA
(317) 849-7300
TWX 810-260-1794
Pioneer-Standard
44 Hartwell Ave.
Lexington, MA 02173
NEBRASKA
IOWA
Advent ElectroniCS
682 58th Avenue, Ct. SW
Cedar Rapids, IA 52404
Schwaber Electronics
25 Wiggins Avenue
NEW HAMPSHIRE
(319) 363-0221
TWX 910·525·1337
Schwaber Electronics
5270 North Park Place, NE
Cedar Rapids, IA 52402
(319) 373-1417
KANSAS
Marshall Industries
8321 Melrose Dr.
Lenexa, KS 66214
(913) 492-3121
See California
Bedford, MA 01730
(617) 275-5100
TWX 710-326-0268
See Iowa
Schwaber Electronics
Bedford Farms Bldg. #2
Manchester, NH 03102
(603) 625-2250
TWX 710-220-7572
FAX (603) 625-5710
Pioneer-Standard
1806 Vestal Pkwy. East
Vestal, NY 13850
(607) 748-8211
TWX 510-252-0893
Pioneer-Standard
Crossways Park West
Woodbury, NY 11797
(516) 921-8700
TWX 510-221-2184
FAX (516) 921-2143
Schwaber Electronics
3 Townline Circle
Rochester, NY 14623
(716) 424-2222
TWX 710-541-0601
Zeus Components
429 Marrett Road
Lexington, MA 02173
NEW JERSEY
(617) 863-8800
TWX 710-326-7604
FAX (617) 863-8807
Kierulff Electronics
37 Kulick Road
Fairfield, NJ 01006
(516) 334-7474
TWX 510-220-1365
(201) 575-6750
Zeus Components
100 Midland Avenue
Port Chester, NY 10573
MICHIGAN
Schwaber Electronics
Jericho Turnpike
Westbury, NY 11590
Advent Electronics
24713 Crestview Ct.
Farmington Hills, MI 48018
Marshall Industries
101 Fairfield Rd.
Fairfield, NJ 07006
(313) 477-1650
(201) 882-0320
Pioneer-Standard
4505 Broadmoor Avenue SE
Grand Rapids, MI 49508
Pioneer·Standard
45 Route 46
Pine Brook, NJ 07058
NORTH CAROLINA
(616) 696-1800
TWX 510-600-8456
(201) 575-3510
TWX 710-734-4382
Charlotte, NC 28234
(704) 377-4348
Pioneer-Standard
13485 Stamford
Livonia, MI 48150
Schwaber Electronics
18 Madison Road
Fairfield, NJ 07006
Winston-Salem, NC 27102
See Massachusetts
(313) 525-1800
TWX 810-242-3271
(201) 227-7880
TWX 710-734-4305
MARYLAND
Schwaber Electronics
Marshall Industries
8445 Helgerman Court
Gaithersburg, MD 20m
12060 Hubbard Avo. CN3306
Solid State
46 Farrand Street
Bloomfield, NJ 07003
Schweber Electronics
10300 West 103rd Street
Suite 200
Overland Park, KS 66214
(913) 492-2922
KENTUCKY
See Indiana
LOUISIANA
See Texas
MAINE
(301) 840-9450
Livonia, MI 48150
(313) 525-8100
TWX 810-242-2983
Pioneer Technologies Group
9100 Gaither Road
Gaithersburg, MD 20m
MINNESOTA
(301) 921-0660
Edina, MN 55435
Kierulff Electronics
NEW YORK
7867 Cahill Road
Add Electronics
7 Adler Drive
E. Syracuse, NY 13057
TWX 710-828-0545
(612) 941-7500
Schwaber Electronics
9330 Gaither Road
Gaithersburg, MD 20877
Marshall Industries
3800 Annapolis Lane
Plymouth, MN 55441
(301) 840-5900
TWX 710-829-9749
Zeus Components
8930·A Route 108
Columbia, MD 21045
(301) 997-1118
TWX 910-380-3554
FAX (301) 964-9784
MASSACHUSETTS
Greene-Shaw
70 Bridge Street
Newlon, MA 02195
(617) 969-8900
TWX 92 2498
(201) 429-8700
TWX 710-994-4780
FAX (201) 429-8883
(914) 937-7400
TWX 710-567-1248
FAX (914) 937-2553
Dixie Electronics
2220 5. Tryon Street
Dixie Electronics
1021 R. Burke 51.
(919) 724-5961
Hammond Electronics
2923 Pacific Avenue
Greensboro, NC 27406
(919) 275-6391
TWX 628-94645
Pioneer Technologies Group
9801 A Southern Pine Blvd.
Charlotte, NC 28210
(704) 527-8188
TWX 810-621-0366
(315) 437-0300
Quality Components, S.E.
2940-15 Trawick Road
Raleigh, NC 27604
(919) 876-7767
(612) 559-2211
Add ElectroniCS
7315 Pittsford-Victor Rd.
Victor, NY 14564
Pioneer Standard
10203 Bren Road East
Minnetonka, MN 55343
Marshall Industries
129 Brown St.
Johnson City, NY 13790
Schwaber Electronics
(612) 935-5444
TWX 910-576-2738
5285 North Blvd.
Raleigh, NC 27604
(919) 876-0000
TWX 510-928-0531
Schwaber Electronics
Marshall Industries
1280 Scottsville Rd.
Rochester, NY 14624
7424 W. 7B1h 51reet
Edina, MN 55435
(612) 941-5280
TWX 910-576-3167
Nu-Horizons Electronics
6000 New Horizons Blvd.
N. Amityville, NY 11701
OHIO
(516) 226-6000
Day1on, OH 45459
(513) 439-0045
MISSISSIPPI
See Texas
X
NORTH DAKOTA
See Minnesota
Kierulff Electronics
476 Windsor Park Drive
u.s.
AND CANADIAN DISTRIBUTORS
OHIO (cont.)
Marshall Industries
6212 Executive Blvd.
Dayton, OH 45424
(513) 236-6086
Pioneer-Standard
259 Kappa Drive
Plnoburgh, PA 15238
(412) 762·2300
TWX no- 795-3122
Pioneer-Standard
13710 Omega Road
001100, TX 75234
(214) 386-7300
TWX 910-86Qo5563
Marshall Industries
59058 Harper Road
Pioneer Technologies Group
261 Gibraltar Road
Horsham, PA 19044
(215) 674-4000
TWX 510-665-6776
Pioneer-Standard
9901 Burnet Road
Austin, TX 79758
(512) 635-4000
TWX 910-674-1323
Schweber Electronics
900 Business Center Or.
Horsham, PA 19044
(215) 441·0800
TWX 510-665-6540
Pioneer-Standard
5863 Point West Drive
Houston, TX no36
(713) 986-5555
TWX 910-881·1608
Schweber Electronics
1000 R.I.D.C. Plaza
Suite 203
Plnsburgh, PA 15238
(412) 762·1800
TWX 810·427·9441
Quality Components
4257 Kellway Circle
Addison, TX 75001
(214) 733-4300
TWX 910-86Qo5459
Solon, OH 44139
(216) 248·1768
Pioneer·Standard
4800 East 131st Stroot
Cleveland, OH 44105
(216) 567·3800
TWX 810-421·0011
VIRGINIA
See Maryland
WASHINGTON
Almac Electronics Corp_
14380 S.E. Eastgate W""
Bellevue, WA 98007
(206) 643-9992
TWX 910-444-2067
FAX (206) 746-7425
Almae Electronics Corp_
East 10905 Montgomery
Spokane, WA 99206
(509) 924-9500
TWX 510-773-1855
FAX (509) 928-8096
Pioneer-Standard
4433 Interpoint Blvd.
Dayton, OH 45424
(513) 236-9900
TWX 810·459·1622
Schweber Electronics
23880 Commerce Park Rd.
Beachwood, OH 44122
(216) 464-2970
TWX 810-427·9441
Schwaber Electronics
7865 Paragon Road
Suite 210
RHODE ISLAND
See Massachusetts
Naw York
SOUTH CAROLINA
Dixie Electronics
1900 Barnwell Street
se 29202
Dayton, OH 45459
Columbia.
(513) 439-1800
(803) 779-5332
TLX 910-866-2820
FAX (803) 765-9276
Zeus (Televoxj2593 Lance Drive
Dayton, OH 45409
(513) 294-4499
TWX 75-9251
FAX (513) 294-6620
OKLAHOMA
Quality Components
9934 East 21st South
Thlsa, OK 74129
(918) 664-8812
TWX 910-880·5459
629-28599
Schweber Electronics
4815 SOuth Sheridan
Fountain Plaza. Suite 109
Tulsa, OK 74145
(918) 822·8000
OREGON
Almac Electronics Corp.
1885 N.W. 169th Place
Beaverton, OR 98006
(503) 629-8090
FAX (503) 645-0811
TWX 910-467·8743
Klerulff ElectroniCS
14273 N.W. Science Park Drive
Portland. OR 97229
(503) 641·9150
Marshall Industries
8333 S.W. Cirrus Dr.
Beaverton. OR 97005
(503) 644-5050
PENNSYLVANIA
Almo Electronics, Inc.
9815 Roosevelt Blvd.
Philadelphia, PA 19114
(215) 696-4063
TLX 476-1218
FAX (215) 969·6788
Dixie Electronics
4909 Palham Rd.
Greenville, se 29806
(803) 297·1435
Dixie Electronics
#6 Papperhlll Square
7525 Brandywine Road
N. Charleston, SC 29410
(803) 552·2671
SOUTH DAKOTA
See Minnesota
TENNESSEE
Dixie Electronics
Box 8215 Suncrest Drive
Gray, TN 37615
(615) 477·3838
Dixie Electronics
6408 Clinton Highway
Knoxville, TN 27912
(615) 938-4131
TEXAS
Kierulff Electronics
3007 Longhorn Blvd.
Austin. TX 79759
Kierulff Electronics
9610 Skillman Ave.
Dallas, TX 75243
(214) 343-2400
Marshall Industries
2045 Chenault SI.
Carrollton, TX 75006
(214) 233-5200
FAX (214) 770·0675
Kierulff Electronics
19450 88th Ave.
South Kent. WA 98032
(206) 575-4420
Marshall Industries
Quality Components
1005 Industrial Blvd.
Sugarland. TX n478
(713) 24Qo2255
TWX 829 27026
14102 N.E. 21st St.
Bellevue, WA 98007
(208) 747·9100
WASHINGTON D.c.
See Maryland
Quality Components
2120 M. Braker Lane
Austin, TX 79758
(512) 835-0220
TWX 324930
WEST VIRGINIA
See Ohio
Pennsylvania
Maryland
Schwaber Electronics
4202 Beltway Drive
Dallas. TX 75234
(214) 881·5010
TWX 910-86Qo5493
WISCONSIN
Kierulff Electronics
2238-E West Bluemound Road
Waukesha, WI 53186
(414) 764-8180
Schwaber Electronics
6300 La Calma Drive
Suite 240
Austin, TX 79752
(512) 458-8253
TWX 910-874-2045
Marshall Industries
235 North Executive Dr.
#305
Brookfield, WI 53005
(414) 797·8400
Schwaber Electronics
10825 Richmond, Suite 100
Houston. TX 77042
(713) 764-3800
TWX 910-881-4638
Zeus Components
1800 North Glenville
Suite 120
Richardson. TX 75081
(214) 763-7010
TWX 910-867·9422
FAX (214) 234-4385
UTAH
Integrated Electronics Corp.
101 N. 700 West
N. Salt Lake City. UT 84054
(801) 296-1889
Klerulff Electronics
1846 Parkway Blvd.
Salt Lake City, UT 84119
(801) 973-6913
Marshall Industries
3501 South Main SI.
Salt Lake City, UT 84115
(801) 261·0901
VERMONT
See New York
xi
Schwaber Electronics
3050 South Calhoun Rd.
Naw Berlin, WI 53151
(414) 764-9020
WYOMING
See Oregon
Washington
CANADA
R.A.E. Industrial
3455 Gardner Court
Burnaby, B.C.
(804) 291·8866
TWX 810-929-3065
R.A.E. Industrial
11880 l70th Street
Edmonton, Alberta
T5S lJ7
(403) 451·4001
TWX 037·2653
Zentronics
8 Tilbury Court
Brampton, Ontario
L6T 3T4
(418) 451·9800
TWX 06-97678
FAX (416) 451·8320
u.s.
AND CANADIAN DISTRIBUTORS
CANADA (cont.)
Zantronics
330().14 love.• NE Bay #1
Calgary. Alberta
T2A 6.14
(403) 272·1021
Zentronies
155 Colonnade. S. #17118
Napean, Ontario
K2E 7K1
(613) 226-8840
TWX 06-87688
Zentronics
11400 Bridgeport Rd. #108
Richmond, B.C.
vex 1T2
(804) 273-5575
TWX 04-355844
Zentronics
817 McCaffrey Street
St. Laurent, Quebec
H4T 1N3
(514) 737-9700
TWX 05-824826
Zentronics
590 Berry Street
Winnipeg, Manitoba
R3H OS1
(204) 775-8661
TWX 06-97878
Future Electronics
3220 5th Avenue, N.E.
Calgary. Alberta
T2A 5N1
(403) 235-5325
Future Electronics
82 St. Regis Crescent N.
Downsview, Ontario
M3J1Z3
(416) 636-4771
TWX 610-491-1470
FAX (416) 638-2936
Future Electronics
.5312 Calgary Trail South
Edmonton, Alberta
TSH 4J8
(403) 438-2856
Future Electronics
Hymus Blvd.
Pointe Claire
Montreal, Quebec
H9R 507
(514) 694-7710
TWX 610-421-3251 or
610-421-3500
FAX (514) 695-3707 or
(514) 694-0062
Future Electronics
Baxter Center
1050 Baxter Road
Ottawa, Ontario
K2C 3P2
(613) 820-8313
TWX 610-563-1697
FAX (613) 620-3271
Zentronles
564 Weber Street. N. #10
Waterloo. Ontario
N21 506
(519) 884-5700
TWX 06-97878
xii
Future Electronics
1695 Boundary Road
Vancouver, B.C.
B5K 4X7
(804) 294-1166
TLX 04354744
FAX (604) 294-1206
Future Electronics
444 Sharon Bay
Winnipeg. Manitoba
R2G OH7
(804) 294-1166 (Vancouver)
CHAPTER 1 - DATA COMMUNICATIONS
---
MI{5025
-----------
.-~~-
PRELIMINARY
COMMUNICATIONS PRODUCTS
FEATURES
VSS·GND
DAL07
DAL06
DAL05
DAL04
DAL03
DAL02
DALOI
DALOO
READ
INTR
DALI
DALO
OAS
BMO. 8YTE. BUSREL
BMI. BUSAKO
HOLD. BUSHO
ALE. As
HLDA
D CMOS
D Fully compatible with both 8 or 16 bit systems.
D System clock rate to 10 MHz.
D Data rate up to 7 MBPS with 64 byte FIFOs in each
direction.
D Complete Data Link Layer Implementation.
D Compatible with X.25 LAPB, ISDN LAPD, X.32, and
X.75 Link Level Protocols.
D 48-pin DIP nearly pin-for-pin compatible with the
Mostek LANCE chip (MK68590).
D Buffer Management includes:
- Initialization Block
- Separate Receive and Transmit Rings
- Variable Descriptor Ring and Window Size.
cs
AOR
HEADY
RESET
VSS·GND
D On chip DMA control and programmable burst
length.
D Selectable Single or extended control field.
D Programmable 1 or 2 byte address field and Global
Address.
3
6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
3D
29
28
27
26
25
vee 1+5VI
DAL08
DAL09
DAL10
DALlI
DAL12
DALI3
DAL14
DAL15
AI6
A17
A18
A19
A20
A21
A22
A23
RO
DSH. CTS
TO
SYSCLK
RCLK
DTR. RTS
TCLK
Figure 1. Pin Connection
D Handles all HDLC (ADCCP) frame formatting:
- Zero bit insert and delete
- FCS generation and detection
- Frame delimiting with flags.
D All inputs and outputs are TTL compatible.
D Programmable for Full or Half Duplex operation.
D Handles all error recovery, sequencing, and Sand
U frame control.
D Programmable minimum frame spacing on transmit
(flags between frames).
D Transparent mode with or without address filtering
allows disabling X.25 processing for customized applications.
DESCRIPTION
The Thomson Components - Mostek X.25 Link Level
Controller (MK5025) is a VLSI semiconductor device
which provides a complete link level data communication control conforming to the 1984 CCITT version of
X.25. This includes frame formatting, transparency (socalled "bit-stuffing"), error recovery by retransmission,
sequence number control, U (unnumbered) frame control, and S (supervisory) frame control. The MK5025
also supports X.32 (XI D), X.75, and ISDN LAPD. The
MK5025 may be used with any of several popular 16
and 8 bit microprocessors, such as 68000, 6800,
Z8000, Z80, LSI-11, 8086, 8088, 8080, etc.
D Selectable FCS of 16 or 32 bits.
D Data Link Services:
- Compatible with ISO Data Link Services
- Compatible with LAPD Data Link Services.
D Testing Facilities:
- Internal Loopback
- Silent Loopback
- Optional Internal Data Clock Generation
- Self Test.
1-1
PIN DESCRIPTION
LEGEND:
I
o
10
Input only
Output only
InputlOutput
3S
OD
3-State
Open Drain (no internal pull-up)
Active low (i.e. inverted)
SIGNAL NAME
PIN(S)
TYPE
DESCRIPTION
DAL<07:00>
2-9
10/3S
The time multiplexed Data/Address bus. During the address portion of the
memory transfer, DAL<07:00> contains the lower 8 bits of the memory
address. During the data portion of a memory transfer, DAL < 07:00 > contains the read or write data, depending on the type of transfer.
READ
10
10/3S
READ indicates the type of operation that the bus controller is performing
during a bus transaction. READ is driven by the MK5025 only while it is
the BUS MASTER. READ is valid during the entire bus transaction and is
tristated by the MK5025 at all other times.
MK5025 as a Bus Slave
READ = HIGH - Data is placed on the DAL lines by the MK5025.
READ = LOW - Data is taken from the DAL lines by the MK5025.
MK5025 as a Bus Master
READ = HIGH - Data is taken from the DAL lines by the MK5025.
READ = LOW - Data is placed on the DAL lines by the MK5025.
INTR
11
OIOD
INTERRUPT is an attention interrupt line that indicates that one or more
of the following CSRO status flags is set: MISS, MERR, ROR, TUR, RINT,
TINT or PINT. INTERRUPT is enabled by CSRO<09>, INEA=1.
DALI
12
0/3S
DAL IN is an external bus transceiver control line. DALI is driven by the
MK5025 only while it is the BUS MASTER. DALI is active when it reads from
the DAL lines during the data portion of a READ transfer. DALI is inactive during a WRITE transfer.
DALO
13
0/3S
DAL OUT is an external bus transceiver control line. DALO is driven by
MK5025 only while it is the BUS MASTER. DALO is asserted by MK5025
when the MK5025 drives the DAL lines during the address portion of a READ
transfer or for the duration of a WRITE transfer.
DAS
14
10/3S
DATA STROBE defines the data portion of a bus transaction. By definition
data is stable and valid at the low to high transition of DAS. This signal is
driven by the MK5025 while it is the BUS MASTER. At all other times the
signal is tristated.
BMO
BYTE
BUSREL
15
10/3S
110 pins 15 and 16 are programmable through CSR4. If bit 06 of CSR4 is
set to a one, pin 15 becomes input BUSREL and is used by the host to Signal
the MK5025 to terminate a DMA Burst after the current bus transfer has
completed. If bit 06 is set to a zero, pin 15 is an output and behaves as
described below for pin 16.
BM1
BUSAKO
16
0/3S
Pins 15 and 16 are programmable through bit 00 of CSR4 (BCON).
If CRS4<00> BCON = 0,
110 PIN 15 = BMO (0/3S)
110 PIN 16 = BM1 (0/3S)
BYTE MASK < 1:0> Indicates the byte(s) on the DAL to be read or written
1-2
SIGNAL NAME
PIN(S)
TYPE
DESCRIPTION
during this bus transaction. MK5025 drives these lines only as a Bus Master.
MK5025 ignores the BM lines when it is a Bus Slave.
Byte selection is done as outlined in the following table.
BMl
BMO
LOW
LOW
LOW
HIGH
HIGH
LOW
HIGH
HIGH
ENTIRE WORD
UPPER BYTE
(DAL<15:08»
LOWER BYTE
(DAL < 07:00 »
ILLEGAL CONDITION
If CSR4<00> BCON = 1,
1/0 PIN 15 = BYTE (0/3S)
1/0 PIN 16 = BUSAKO (0)
Byte selection is done using the BYTE line and DAL latched during
the address portion of the bus transaction. MK5025 drives BYTE only as
a Bus Master and ignores it when a Bus Slave. Byte selection is done as
outlined in the following table.
BYTE
DAL
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
ENTIRE WORD
ILLEGAL CONDITION
LOWER BYTE
UPPER BYTE
BUSAKO is a bus request daisy chain output. If MK5025 is not requesting
the bus and it receives HLDA, BUSAKO will be driven low. If MK5025 is
requesting the bus when it receives HLDA, BUSAKO will remain high.
17
1010D
Pin 17 is programmable through bit 00 of CSR4.
IF CSR4<00> BCON = 0,
1/0 PIN 17 = HOLD
HOLD request is asserted by the MK5025 when it requires a DMA cycle
regardless of the previous state of the HOLD pin. HOLD is held low for the
--entire ensuing bus transaction.
IF CSR4<00> BCON = 1,
1/0 PIN 17 = BUSRQ
BUSRQ is asserted by the MK5025 when it requires a DMA cycle if the prior
state of the BUSRQ pin was high. BUSRQ is held low for the entire ensuing bus transaction.
ALE
AS
18
0/3S
The active level of ADDRESS STROBE is programmable through bit 01 of
CSR4. The address portion of a bus transfer occurs while this signal is at
its asserted level. This signal is driven by the MK5025 while it is the BUS
MASTER. At all other times, the signal is tristated.
IF CSR4<01 > ACON
1/0 PIN 18 = ALE
=
0,
ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define the address portion of the transfer. As ALE, the signal transitions from
high to low during the address portion of the transfer and remains low during the data portion.
1-3
SIGNAL NAME
PIN(S)
TYPE
DESCRIPTION
IF CSR4<01 > ACON = 1,
1/0 PIN 18 = AS
As AS, the signal pulses low during the address portion of the bus transfer.
The low to high transition of AS can be used by a slave device to strobe
the address into a register.
HLDA
19
HOLD ACKNOWLEDGE, is the response to HOLD. When HLDA is low
in response to MK5025's assertion of HOLD, the MK5025 is the Bus Master.
HLDA should be disasserted ONLY after HOLD has been released by
MK5025.
CS
20
CHIP SELECT indicates, when low, that the MK5025 is the slave device for
the data transfer. CS must be valid throughout the entire transaction.
ADR
21
ADDRESS selects the Register Address Port or the Register Data Port. It
must be valid throughout the data portion of the transfer and is only used
by the chip when CS is low.
READY
22
10/00
ADR
PORT
LOW
HIGH
REGISTER DATA PORT
REGISTER ADDRESS PORT
When the MK5025 is a Bus Master, READY is an asynchronous acknowledgement from the bus memory that memory will accept data in a WRITE
cycle or that memory has put data on the DAL lines in a READ cycle.
As a Bus Slave, the MK5025 asserts READY when it has put data on the DAl
lines during a READ cycle or is about from take data off the DAL lines during a WRITE cycle. READY is a response to DAS and it will be negated
after DAS is negated.
RESET
23
RESET is the Bus signal that will cause MK5025 to cease operation, clear
its internal logic and enter an idle state.
TCLK
25
TRANSMIT CLOCK. A 1X clock input for transmitter timing. TO changes
on the falling edge of TCLK. The frequency of TCLK may be up to 7 Mbps.
DTR
RTS
26
RCLK
27
RECEIVE CLOCK. A 1X clock input for receiver timing. RD is sampled on
the rising edge of RCLK. The frequency of RCLK may be up to 7 MHz.
SYSCLK
28
SYSTEM CLOCK. System clock used for internal timing of MK5025.
SYSCLK should be a square wave, and be greater than 500 KHz and less
than 10 MHz.
TO
29
0
TRANSMIT DATA. Transmit serial data output.
DSR
CTS
30
10
DATA SET READY, CLEAR TO SEND. Modem Control Pin. Pin 30 is configurable through CSR5. This pin can be programmed to behave as input
CTS or as a programmable 10 pin DSR. If configured as CTS, the MK5025
will transmit all 1's while CTS is high.
10
DATA TERMINAL READY, REQUEST TO SEND. Modem Control Pin. Pin
26 is configurable through CSR5. This pin can be programmed to behave
as output RTS or as a programmable 10 pin DTR. If configured as RTS, the
MK5025 will assert this pin if it has data to send and throughout transmission of a frame.
1·4
SIGNAL NAME
PIN(S)
TYPE
DESCRIPTION
RD
31
A<23:16>
32·39
0/35
Address bits <23:16> used in conjunction with DAL< 15:00> to produce
a 24 bit address. MK5025 drives these lines only as a Bus Master.
DAL<15:08>
40·48
10/3S
The time multiplexed Data/Address bus. For 16·bit operations,
DAL < 15:08> behaves similar to DAL < 07:00 > above for the high byte
of data or the middle byte of the 24 bit address. For 8·bit operations,
DAL< 15:08> behaves similar to A <23:16> for the middle byte of the
24·bit address only.
VSS·GND
1,24
Ground • 0 VDC
VCC
48
Power Supply Pin.
+5.0 VDC ±5%
RECEIVE DATA. Received serial data input.
HOST PROCESSOR
(68000, 8088, zeooo, ETC)
16·BIT DATA BUS INCWDING
24 BIT ADDRESS AND BUS CONTROL
MEMORY
(MULTIPLE
DATA BLOCKS)
,...------+
LAYER 3
1/0 PROCESSOR
"OPTIONAL"
t
I
I
I
I
I
I
I
I
MK5025
I~
~
I~
r£
!l
I
la
" I~
0::
I
"
I
l-
f
LINE DRIVERS
AND RECEIVERS
"OPTIONAL"
LINE DRIVERS
AND RECEIVERS
ELECTRICAL 1/0
(SUCH AS RS·232C, RS-423, RS·422)
t
I
..
,DATA COMM. CONNECTOR
(SUCH AS RS·449, RS·232C)
Figure 2. Possible System Configuration for the MK5025
1·5
...........
I~
Ii I~
1:1
I~ ~ Ii II
Irl
iiEADY
a:
~
READ
I~
Ie
~ Iic
Ii
~1
A
i
v
C
-'\
I
FIRMWARE
ROM
DMA
CONTROLLER
'---lI
CSllO-5
I
MICRO
CONTROLLER
I
TIMERS
TI·TP
I
SYSCLK
I
A
~
INTERNAL BUS
~
'l
r
i
RECEIVER
FIFO
TRANSMITTER
FIFO
RECEIVER
TAANSMmER
..
..
vee
VSs-GND
..
RESET
TCLK
IICLK
TO
AD
-1
LOOPBACK TEST
l--
Figure 3. MKIi025 SlmplHlecl Block Diagram
1-8
ways: either as bus master or as a bus peripheral. The
MK5025 contains a dual channel DMA on chip to handle data transfers to and from the host memory. All access to the initialization block and descriptor rings is
handled in this way. The address bus is 24 bits wide
and does not use any segmentation or paging methods.
Data transfers can optionally be 8 and 16 bit operations,
this allows easy interfacing with both 8 and 16 bit
processors. DMA transfers can be up to 1, 8 or an unlimited number of words per transfer under program
control. In bus slave mode the MK5025 allows access
to its 6 controllstatus registers which are used to monitor and control the chip. These registers are used to controllink procedures, configure interface options, control
and monitor interrupt status, and more. Bus slave mode
also allows both 8 and 16 bit accesses.
OPERATIONAL DESCRIPTION
The Mostek X.25 Link Controller (MK5025) device is a
VLSI product intended for data communication applications requiring X.25 link level control (LAPB). The
MK5025 will perform all frame formatting, such as frame
delimiting with flags, FCS generation and detection, as
well as zero-bit insertion and deletion for transparency. The MK5025 also includes a buffer management
mechanism that allows the user to transmit and/or
receive multiple packets. Contained in the buffer
management is an on-Chip dual channel DMA: one
channel for receive and one channel for transmit. The
MK5025 handles all supervisory (S) and unnumbered
(U) frames. (See Table I.)
The MK5025 is intended to be used with any popular
16 or 8 bit microprocessor. A possible system configuration for the MK5025 is shown in figure 2.
BUFFER MANAGEMENT
The MK5025 will move multiple blocks of receive and
transmit data directly into and out of memory through
the Host's bus. An 110 acceleration processor can be
used to off-load Network Level software from the Host.
The 110 acceleration processor in figure 2 is recommended, but not required.
The basic organization of the buffer management is a
circular queue of tasks in memory called descriptor
rings. There are separate rings to describe the transmit and receive operations. Up to 128 buffers may be
queued-up on a descriptor ring awaiting execution by
the MK5025. The descriptor ring has a segment assigned to each buffer. Each segment holds a pointer
for the starting address of the buffer, and holds a value
for the length of the buffer in words (16 bits).
All signal pins on the MK5025 are TIL compatible. This
has the advantage of making the MK5025 independent
of the physical interface. As shown in Fig. 2, line drivers
and receivers are used for electrical connection to the
physical layer.
Each segment also contains two control bits called
OWNA and OWNB, which denote whether the MK5025,
the HOST, or the 110 ACCELERATION Processor (if
present) "owns" the buffer. For transmit, when the
MK5025 owns the buffer, the MK5025 is allowed and
commanded to transmit the buffer. When the MK5025
does not own the buffer, it will not transmit that buffer.
For receive, when the MK5025 owns a buffer, it may
place received data into that buffer. Conversely, when
the MK5025 does not own a receive buffer, it will not
place received data in that buffer.
SERIAL INTERFACE
The MK5025 provides two seperate serial channels;
one for received data and one for transmitted data.
These serial channels are completely seperate and may
be run at different clock frequencies up to 7 MHz. The
receiver is responsible for recognizing frame boundaries, removal of inserted zeroes (for transparency), and
checking the incoming FCS. Frames with incorrect FCS
values are discarded. The receiver also parallelizes the
incoming data which is placed into the receive data
buffers within the receive descriptor ring. The receiver
also recognizes link idle and frame abort sequences.
The transmitter is responsible for framing and serializing the data frames placed in the transmit descriptor
ring. The transmitter calculates the FCS of the outgoing data and appends it to the data. The transmitter
generates flag sequences for interframe fill, at least two
flags are transmitted between adjacent frames. The
FCS calculations for both directions of serial data optionally follow either the 16-bit CRC-CCITI or the 32-bit
CRC-32 algorithms. FCS generation and checking can
also be optionally disabled if defined.
The MK5025 buffer management mechanism will handle frames which are longer than the length of an individual buffer. This is done by a chaining method which
utilizes multiple buffers. The MK5025 tests the next segment in the descriptor ring in a "look ahead" manner.
If the packet is too long for one buffer, the next buffer
will be used after filling the first buffer; that is, "chained".
The MK5025 will then "look ahead" to the next buffer,
and chain that buffer if necessary, and so on.
The operational parameters for the buffer management
are defined by the user in the initialization block. The
parameters defined include the basic mode of operation, the number of entries for the transmitter and
receiver descriptor rings, frame Address field, and etc.
MICROPROCESSOR INTERFACE
The MK5025 can interface with the host bus in two
1-7
PROTOCOL
ing and UI frames are optionally available for use in
ISDN LAPD applications. XID and TEST frames are
available for use in X.32. The interface between the
MK5025 and the host Qayer 3) conforms to both the ISO
data link services standard and the ISDN LAPD data
link services standard.
The MK5025 contains a full implementation of the 1984
CCITT X.25 data link layer. It allows both basic and extended control fields, variable window sizes, and userdefined counter and timer values. Extended address-
V,-0
RECEIVE BUFFERS
CSRl. CSR3
~
POINTER TO INIT·
, IALIZATION BLOCK
J
RECEIVER DESCRIPTOR RINGS
..
0
DESC:~~= :rATUS
-IiUFFEAAOORBS---------- -
BUFFER
BUFFER SIZE
/ '
B~F;
cOUNT -
MSG
DESCRIPTOR 1
1
•
•
'----'
•
•
•
INITIALIZATION BLOCK
~
•
MODE
DESCRIPTOR M
FRAME ADDRESS
FIELDS
BUFFER
M
TIMER VAWES
RECEIVE DESCRIPTOR
RING SET·UP
TRANSMIT DESCRIPTOR
RING SET·UP
XIDITEST TRANSMIT
DESCRIPTOR
XIDITEST RECEIVE
DESCRIPTOR
TRANSMIT DESCRIPTOR RINGS
r--
Lf-+- _.
I- _
~
STATUS BUFFER
ADDRESS
-"~F~ ,!I'A~~
__
L-----""
BUFFER
0
BUFFER ADDRESS
f - -BUFFER
-----SIZE
1:--------BUFFER MSG COUNT
ERROR COUNTERS
DESCRIPTOR 1
XIDITEST RECEIVE
BUFFER
TRANSMIT BUFFER
r-
•
•
•
DESCRIPTOR N
XIDITEST TRANSMIT
BUFFER
Figure 4. MK5025 Buffer Management
1-8
~
BUFFER
1
•
•
•
r---.6
THE COMMAND/RESPONSE REPERTOIRE
Name
Definition
The command/response repertoire of the MK5025 is
shown in Tables 1a and lb. This set conforms to ISDN
LAPD and X.32, which are super-sets of X.25 Link Level. The MK5025 will process the Sand U frames shown
in Table I, and will handle the A and C fields for all I
and UI frames.
I
UI
RR
DISC
RNR
UA
REJ
FRMR
SABM
Information frame
Unnumbered Information
Receiver Ready
Disconnect
Receiver Not Ready
Unnumbered Acknowledge
Reject
Frame Reject
Set Asynchronous Balance Mode
Disconnect Mode
Exchange Identification
Link Test frame
The definitions for the symbols for the frame types are:
OM
XID
TEST
1-9
Table la. MK5025 Command/Response Repertoire.
Modulo 8 Operation
Format
Command
Information Transfer
I
Supervisory
RR
RNR
REJ
Unnumbered
Resp
RR
RNR
REJ
SABM
·XID
·UI
DISC
·TEST
DM
·XID
·UI
UA
FRMR
·TEST
Encoding
5
6
7
P
-
N(R)
-
1
P/F
P/F
P/F
-
N(R) N(R) N(R) -
1
1
1
0
0
0
0
0
P
F
P/F
P/F
P
F
F
P/F
1
0
1
0
0
1
0
1
1
2
0
-
1
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
4
N(S)-
1
0
0
0
1
0
0
0
0
0
1
1
0
1
8
-
0
0
1
0
0
0
1
1
Table lb. MK5025 Command/Response Repertoire.
Modulo 128 Operation.
Format
Resp
Command
Encoding
1
Information Transfer
I
Supervisory
RR
RNR
REJ
Unnumbered
·TEST
3
4
1
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
RR
RNR
REJ
SABME
·XID
·UI
DISC
2
DM
·XID
·UI
UA
FRMR
·TEST
* XID and UI Frames can be individually enabled for compatibility with X.32
and LAPD respectively_ TEST frames are enabled with XID frames.
1-10
1
1
6
7
8
0
0
0
0
0
0
0
0
0
0
P
F
P/F
P/F
P
F
F
P/F
1
0
1
0
0
0
0
0
5
N(S)
1
0
0
0
0
1
0
1
0
0
0
0
1
1
1
1
1
1
I
9
10-16
P
N(R)
P/F N(R)
P/F N(R)
P/F N(R)
MK5025 ELECTRICAL SPECIFICATION
ABSOWTE MAXIMUM RATINGS
Temperature Under Bias ....................................................... -25°C to +100°C
Storage Temperature .......................................................... -65°C to +150°C
Voltage on Any Pin with Respect to Ground .................................... -0.5 V to Vcc +0.5 V
Power Dissipation ...................................................................... 0.50 W
Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
TA=O°C to 70°C, VCC = +5 V ±5 percent unless otherwise specified.
SYMBOL CONDITIONS
MIN
MAX
UNITS
VIL
-0.5
+0.8
V
+2.0
Vcc +0.5
V
+0.5
V
VIH
VOL
@ IOL = 3.2 rnA
VOH
@ IOH = -0.4 rnA
IlL
@ Yin = 0.4 to VCC
Icc
TSCT = 100 ns
TYP
V
+2.4
~
±10
mA
50
CAPACITANCE
Frequency = 1 MHz
MAX
UNITS
CIN
10
pF
COUT
10
pF
CIO
20
pF
SYMBOL CONDITIONS
MIN
AC TIMING SPECIFICATIONS
TA = O°C to 70°C, Vcc = +5 V ±5 percent, unless otherwise specified.
NO. SIGNAL
SYMBOL
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
ns
ns
ns
1
SYSCLK TSCT
SYSCLK period
100
2
SYSCLK TSCL
SYSCLK low time
45
3
SYSCLK TSCH
SYSCLK high time
45
4
SYSCLK TSCR
Rise time of SYSCLK
0
8
5
SYSCLK TSCF
Fall time of SYSCLK
0
8
6
TCLK
TTCT
TCLK period
140
7
TCLK
TTCL
TCLK low time
63
8
TCLK
TTCH
TCLK high time
63
9
TCLK
TTCR
Rise time of TCLK
0
8
10
TCLK
TTCF
Fall time of TCLK
0
8
11
TD
TTDP
TD data propagation delay after the
falling edge of TCLK
CL = 50 pF
12
TD
TTDH
TD data hold time after the falling edge
of TCLK
C L = 50 pF
1-11
40
5
AC TIMING SPECIFICATIONS
TA =
to 70°C, V CC = +5 V ±5 percent, unless otherwise specified.
oae
NO. SIGNAL
SYMBOL
PARAMETER
TEST
CONDITIONS
MIN
ns
TYP
ns
MAX
ns
13
RCLK
T RCT
RCLK period
14
RCLK
TRCH
RCLK high time
63
15
RCLK
T RCL
RCLK low time
63
16
RCLK
T RCR
Rise time of RCLK
0
8
17
RCLK
TRCF
Fall time of RCLK
0
8
18
RD
TROR
RD data rise time
0
8
19
RD
T ROF
RD data fall time
0
8
20
RD
TROH
RD hold time after rising edge of RCLK
5
30
140
21
RD
T ROS
RD setup time prior to rising edge of RCLK
22
AlDAL
TOOFF
Bus Master driver disable after rising edge
of HOLD
23
AlDAL
TOON
Bus Master driver enable after falling edge
of HLDA
24
HLDA
THHA
Delay to falling edge of HLDA from
falling edge of HOLD (Bus Master)
25
RESET
TRW
RESET pulse width
26
AlDAL
TevCLE
Readlwrite, address/data cycle time
27
A
T XAS
Address setup time to falling edge of ALE
100
28
A
TXAH
Address hold time after the rising edge of
DAS
50
29
DAL
TAS
Address setup time to the falling edge of
ALE
75
30
DAL
TAH
Address hold time after the falling edge
of ALE
20
31
DAL
T ROAS
Data setup time to the rising edge of DAS
(Bus master read)
55
32
DAL
T ROAH
Data hold time after the rising edge of DAS
(Bus master read)
0
33
DAL
T OOAS
Data setup time to the falling edge of DAS
(Bus master write)
0
34
DAL
Twos
Data setup time to the rising edge of DAS
(Bus master write)
250
35
DAL
TWOH
Data hold time after the rising edge of
DAS (Bus master write)
36
DAL
TSROH
Data hold time after the rising edge of DAS TSCT
(Bus slave read)
37
DAL
TSWOH
Data hold time after the rising edge of DAS
(Bus slave write)
0
38
DAL
Tswos
Data setup time to the falling edge of DAS
(Bus slave write)
0
39
ALE
TALEW
ALE width high
TSCT
= 100 nS
0
50
0
200
0
30
TSCT
= 100 nS
600
35
= 100 nS
0
110
1-12
35
AC TIMING SPECIFICATIONS
TA =
oce to 70°C, Vee
= +5 V ±5 percent, unless otherwise specified.
TEST
CONDITIONS
NO. SIGNAL
SYMBOL PARAMETER
40
ALE
TOALE
Delay from rising edge of DAS to the
rising edge of ALE
MIN
TYP
MAX
ns
ns
ns
70
41
DAS
Tosw
DAS width low
200
42
DAS
T AOAS
Delay from the falling edge of ALE to the
falling edge of DAS
80
43
DAS
T RIOF
Delay from the rising edge of DALO to
the falling edge of DAS (Bus master read)
35
44
DAS
T ROYS
Delay from the falling edge of READY to
the rising edge of DAS
45
DALI
T ROIF
Delay from the rising edge of DALO to
the falling edge of DALI (Bus master read)
70
46
DALI
T RIS
DALI setup time to the rising edge of
DAS (Bus master read)
150
47
DALI
TRIH
DALI hold time after the rising edge of
DAS (Bus master read)
0
48
DALI
T RIOF
Delay from the rising edge of DALI to
the falling edge of DALO (Bus master read)
70
49
DALO
Tos
DALO setup time to the falling edge of
ALE (Bus master read)
110
50
DALO
T ROH
DALO hold time after the falling edge of
ALE (Bus master read)
35
51
DALO
TWOSI
Delay from the rising edge of DAS to
the rising edge of DALO (Bus master write)
50
52
CS
TeSH
CS hold time after the rising edge of
DAS (Bus slave)
0
53
CS
Tess
CS setup time to the falling edge of
DAS (Bus slave)
0
54
ADR
TSAH
ADR hold time after the rising edge of
DAS (Bus slave)
0
55
ADR
TSAS
ADR setup time to the falling edge of
DAS (Bus slave)
0
56
READY
T ARyO
Delay from the falling edge of ALE to the TSCT = 100 nS
falling edge of READY to insure a minimum bus cycle time (600 nS)
57
READY
T SROS
Data setup time to the falling edge of
READY (Bus slave read)
75
58
READY
TRDYH
READY hold time after the rising edge
of DAS (Bus master)
0
59
READY
TSRYH
READY hold time after the rising edge of
DAS (Bus slave)
60
READ
TSRH
READ hold time after the rising edge of
DAS (Bus slave)
0
61
READ
TSRS
READ setup time to the falling edge of
DAS (Bus slave)
0
62
READY
T RDYO
Delay from falli~e of DAS to
falling edge of READY (Bus slave read)
1-13
TARYO =300 nS
TSCT = 100 nS
TSCT = 100 nS
TSCT = 100 nS
120
200
150
35
0
200
TEST
POINT
R1
=1.2K
CR 1·CR4
=:
1N914 OR EQUIVALENT
CL
O.4mA
I
Figure 5. Output Load Diagram
RD
TO
TIMING MEASUREMENTS ARE MADE AT THE FOLLOWING VOLTAGES.
UNLESS OTHERWISE SPECIFIED:
OUTPUT
INPUT
FLOAT
"1"
"0"
2,0 V
2,0 V
0.8 V
0.8 V
90% V OH
10% VOL
Figure 6. MK5025 Serial Link Timing Diagram
1-14
""
50pF MAX @ 1 MHz
100
200
300
400
500
600
I
I
I
I
I
I
A 16·23
ALE
DAlO·15
(WRITE)
i5Alo
(WRITE)
DAU
(WRITE)
READ
(WRITE)
DALO·15
----<1/
IREADI
OALO
IREADI
DATI
IREADI
READ
IREADI
SMO,1
NOTE: The Bus Master cycle time will Increase from
a minimum of 600 ns In 100 ns steps until
the slave device returns READY.
Figure 7. MK5025 Bus Master Timing Diagram
1-15
1t
a--1- 1
ADR
~"F
~Mt;
~____________~~mffi
~----------~----------~
57
81
READ
(READI
DALO-15
}READI
READ
}WRITEI
zZa
8
DALO 15
(WRITEI
DATA IN
________________________________---:~
II
Figure 8. MK5025 Bus Slave Timing Diagram
1-16
1-4--------62------1
--j
57
61
REAO
(READ)
OAlO·15
(READI
READ
(WRITE)
8
DALO 15
(WRITE)
~
DATA IN
_ _ _ _ _ _ _ _ _ _ _ _ _ _~-------~
II
Figure 8. MK5025 Bus Slave Timing Diagram
1-17
PACKAGE DESCRIPTION
(
~~
)~~~~~=a~~~~_?i-.~~
I-----o,--~.I
23 EO SPCS @ .100
= 2.300
-jel
~J=-::!:::1II~
~
Bl~-L
B-H-
INCHES
DIM.
MIN.
A
-
Al
.020
MAX.
NOTES
.175
1
-
1
A2
.080
.110
B
.015
.021
Bl
.038
.057
C
.008
.012
0
2.370
2.430
01
.035
.065
E
.595
.625
El
.580
.610
el
.090
.110
eA
.590
.665
L
.125
-
0
.005
-
2
NOTES
1. Package standoff to be measured per JEDEC requirements.
2. The maximum limit shall be increased by .003 in. when solder lead finish
is specified.
3. Measured from top of ceramic to nearest metallization .
2
3
1-18
h:(·M~i·UI
COMPONENTS
COMMUNICATIONS PRODUCTS
-::::::'-l~---------
--------------------MOSTEK
TECHNICAL
MANUAL
MOSTEK X.25
LINK LEVEL CONTROLLER
(MK5025)
1·19
1-20
TABLE OF CONTENTS
Paragraph
Number
Page
Number
Title
Section 1
Introduction
Introduction ................................................................ 1-1
Section 2
Features
Features ................................................................... 2-1
Section 3
Operational Description
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.3
Functional Blocks ........................................................... 3-1
Microcontroller .......................................................... 3-1
Receiver ............................................................... 3-4
Transmitter ............................................................. 3-4
Frame Check Sequence .................................................. 3-4
Receive FIFO ........................................................... 3-5
Transmit FIFO .......................................................... 3-5
DMA Controller ......................................................... 3-5
Bus Slave Circuitry ...................................................... 3-5
Buffer Management Overview ................................................. 3-6
The Initialization Block ................................................... 3-6
The Circular Queue ...................................................... 3-6
Frame Format ........................................................... 3-8
The Command/Response Repertoire ........................................ 3-8
Pin Description ............................................................ 3-10
Section 4
Programming Specification
4.1
4.1.1
4.1.1.1
4.1.1.2
4.1.2
4.1.2.1
4.1.2.2
4.1.2.3
4.1.2.4
4.1.2.5
4.1.2.6
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
Control and Status Registers .................................................. 4-1
Accessing the Control and Status Registers .................................. 4-1
Register Address Port (RAP) ........................................... 4-1
Register Data Port (RDP) .............................................. 4-2
Control and Status Register Definition ....................................... 4-2
Control and Status Register 0 (CSRO) ................................... 4-2
Control and Status Register 1 (CSR1) .................................... 4-4
Control and Status Register 2 (CSR2) ................................... 4-6
Control and Status Register 3 (CSR3) ................................... .4-7
Contr~: and Status Register 4 (CSR4) ................................... 4-8
Control and Status Register 5 (CSR5) .................................. .4-9
Initialization Block .......................................................... 4-10
Mode Register ......................................................... 4-11
Station Addresses
.4-13
Timers ................................................................ 4-13
Receive Descriptor Ring Pointer ........................................... 4-14
Transmit Descriptor Ring Pointer ........................................... 4-15
XIDITEST Descriptors ................................................... 4-16
Status Buffer Address ................................................... 4-16
1-21
Paragraph
Number
4.2.8
4.3
4.3.1
4.3.1.1
4.3.1.2
4.3.1.3
4.3.1.4
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.2.4
4.3.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.5.10
4.5.11
4.5.12
4.5.13
4.5.14
Page
Number
Title
Error Counters ........................................................ .4-17
Receive and Transmit Descriptor Rings ........................................ .4-17
Receive Message Descriptor Entry ........................................ .4-17
Receive Message Descriptor 0 (RMDO) .................................. 4-17
Receive Message Descriptor 1 (RMD1) .................................. 4-18
Receive Message Descriptor 2 (RMD2) .................................. 4-18
Receive Message Descriptor 3 (RMD3) .................................. 4-19
Transmit Message Descriptor Entry ......................................... 4-19
Transmit Message Descriptor 0 (TMDO) .................................. 4-19
Transmit Message Descriptor 1 (TMD1) ................................. 4-20
Transmit Message Descriptor 2 (TMD2) ................................. 4-20
Transmit Message Descriptor 3 (TMD3) ................................. 4-20
Status Buffer ......................................................... .4-21
Data Link Services ......................................................... 4-22
Detailed Programming Procedures ............................................ 4-24
Initialization ........................................................... 4-24
Active Link Setup ....................................................... 4-24
Passive Link Setup ..................................................... 4-24
Refusing Link Setup .................................................... 4-25
Sending Data .......................................................... 4-25
Receiving Data ......................................................... 4-25
Link Disconnection ..................................................... 4-25
Link Reset .........................' .................................. .4-25
Receiving Link Reset. ................................................... 4-25
Receiving FRMR frame .................................................. 4-26
Exchanging identification ................................................. 4-26
Receiving an identification request. ........................................ 4-26
Disabling the MK5025 ................................................... 4-26
Re-enabling the MK5025 ................................................. 4-27
Section 5
Electrical Specifications
Electrical Specifications ...................................................... 5-1
Section 6
Reference Documents
Reference Documents ........................................................ 6-1
1-22
SECTION 1
INTRODUCTION
The Mostek X.25 Link Level Controller (MK5025) is a VLSI semiconductor device which provides a complete link
level data communication control conforming to the 1984 CCITT version of X.25. This includes frame formatting,
transparency (so-called "bit-stuffing"), error recovery by retransmission, sequence number control, U (unnumbered)
frame control, and S (supervisory) frame control. The 1984 specification includes several enhancements to the
1980 version of X.25. It includes extended control fields and a 16 or 32 bit FCS. The MK5025 also supports X.32
(XID) and X.75.
The chip also supports single channel LAPD for ISDN with its UI frames and extended addressing capabilities.
However, LAPD is still being defined as of the writing of this speCification and is subject to change. No guarantees
are made regarding future compatibility.
A transparent mode provides an HDLC transport mechanism without link layer support. Extended addressing and
control are optionally supported within transparent mode. Address filtering is also optional in transport mode.
One of the outstanding features of the MK5025 is its buffer management which includes on-chip DMA. This feature
allows users to handle multiple frames of receive and transmit data at a time. (A conventional data link control
chip plus a separate DMA chip would handle data for only a single block at a time.)
The MK5025 may be used with several popular microprocessors, such as 68020,68000,6800, Z80OC, zao, LSI-11,
8086, 8088, 80aO, etc.
1-23
1-1
SECTION 2
FEATURES
• CMOS
• Fully compatible with both 8 or 16 bit systems.
• System clock rate to 10 MHz.
• Data rate up to 7 MBPS, with a 64-byte FIFO in each direction.
• Complete Level 2 Implementation.
• Compatible with X.25 LAPB, ISDN LAPD, X.32, and X.75 Link Level Protocols.
• 48-pin DIP pin-for-pin compatible with the Mostek SS7 Controller (MK5027) and nearly pin-for-pin compatible
with the Mostek LANCE chip (MK68590).
• Buffer Management includes:
Initialization Block
Separate Receive and Transmit Rings
Variable Descriptor Ring and Window Size.
• On chip DMA control with programmable burst length.
• Selectable single
c:o extended control field.
• Programmable 1 or 2 byte address field and Global Address.
• Transparent modll with or without addressing filtering for customized protocols using HDLC framing and DMA
buffering.
• Handles all HDLC (ADCCP) frame formatting:
Zero bit insert and delete
FCS generation and detection
Frame delimiters by flags
• Five programmable timer counters:
T1, T3, TP, N1, N2.
• Handles all error recovery, sequencing, and Sand U frame control
• Selectable FCS of 16 or 32 bits.
• Data Link Services:
Compatible with ISO Data Link Services
Compatible with LAPD Data Link Services.
• Testing Facilities:
Internal Loopback
Silent Loopback
Optional Internal Data Clock Generation
Self Test.
• All inputs and outputs are TTL compatible.
• Programmable for full or half duplex operation.
• Programmable minimum frame spacing (number of flags between frames).
2-1
1-24
SECTION 3
OPERATIONAL DESCRIPTION
The Thomson Components - Mostek X.25 Link Controller (MK5025) is a VLSI semiconductor device intended for
data communication applications requiring X.25 link level control. The MK5025 will perform all frame formatting,
such as: frame delimiting with flags, FCS generation and detection. The MK5025 also includes a buffer management mechanism that allows the user to transmit and/or receive multiple frames. Contained in the buffer management is an on-chip dual channel DMA: one channel for receive and one channel for transmit. The MK5025 handles
all supervisory (S) and unnumbered (U) frames. (See Table I.)
The MK5025 is intended to be used with any popular 16 or 8 bit microprocessor. A possible system configuration
for the MK5025 is shown in figure 1. This document assumes that the processor has a by1e addressable address bus.
The MK5025 will move multiple blocks of receive and transmit data directly into and out of memory through the
Host's bus. An I/O acceleration processor, such as the MK68HC200 Single Chip Micro-Computer, could be used
to off-load Network Level software from the Host. The I/O acceleration processor in figure 1 is recommended, but
not required.
The MK5025 may be operated in either full or half duplex mode. In half duplex mode, the RTS and CTS modem
control pins are provided. In full duplex mode, these pins become user programmable I/O pins.
.
All signal pins on the MK5025 are TTL compatible. This has the advantage of making the MK5025 independent
of the physical interface. As shown in Fig. 1, line drivers and receivers are used for electrical connection to the
physical layer.
3.1 Functional Blocks
The MK5025 is made up of 8 functional blocks. These are shown in Figure 2.
3.1.1 Microcontroller
The microcontroller is the brain of the MK5025. It controls all of the other blocks and contains most of the protocol
processing. All frame content processing as well as Sand U frame processing and generation is performed by
the microcontroller. All primitive processing and generation is also done here. The microcode ROM contains the
control program for the microcontroller.
1-25
3-1
HOST PROCESSOR
(68000, 8086, Z8000, ETC)
16-BIT DATA BUS INCLUDING
24 BIT ADDRESS AND BUS CONTROL
MEMORY
(MULTIPLE
DATA BLOCKS)
LAYER 3
1/0 PROCESSOR
"OPTIONAL"
I
MK5025
I~
Itl
Ii
f/)
b
Ii
e
,
ja
e
a:
l:g!l
e
t-
•
LINE DRIVERS
AND RECEIVERS
"OPTIONAL"
LINE DRIVERS
AND RECEIVERS
ELECTRICAL I/O
(SUCH AS RS-232C, RS-423, RS-422)
t
I
+
DATA COMM. CONNECTOR
(SUCH AS RS-449, RS-232C)
Figure 1. Possible System Configuration for the MK5025
3-2
1-26
I:2!; I~ I~ I~
~/'-.
1!Il
~
I~ Iii
READY
l!'l
READ
II:
c
'"
I~ I~ I~
r<
r< .,
I:i
C
~l
~
~
V
'" --\
OMA
L-.y'
~
ROM
CSRO-5
CONTROLLER
I
MICRO
CONTROLLER
I
TIMERS
TI-TP
I
SYSCLK
-
1
A
~
INTERNAL BUS
~
~
RECEIVER
FIFO
r
i
..
vce
-----VSS··GND
TRANSMITTER
FIFO
RESET
TCLK
RCLK
RECEIVER
TRANSMITTER
RO-_ _
~ LOOPBACK TEST
--
TO
r-
Figure 2. MK5025 Simplified Block Diagram
1·27
3·3
3.1.2 Receiver
Serial receive data comes into the Receiver (Figure 2). The Receiver is responsible for:
1. Leading and trailing flag detection.
2. Deletion of zeroes inserted for transparency.
3. Detection of idle and abort sequences.
4. Detection of good and bad FCS (Frame Check Sequence).
5. Monitoring Receiver FIFO status.
6. Detection of Receiver-Over-Run.
7. Odd byte detection.
NOTE: If frames are received that have an odd number of bytes in the information field, the last byte of the
frame is said to be an odd byte.
8. Detection of non-octet aligned frames, such frames are treated as invalid frames (see reference #5, section
2.3.5.3).
3.1.3 Transmitter
The Transmitter is responsible for:
1. Serialization of outgoing data.
2. Generating and appending the FCS.
3. Generation of interframe time-fill as either flags or idle.
4. Zero bit insertion for transparency.
5. Transmitter-Under-Run detection.
6. Transmission of
odd byte.
7. RTS/CTS Control
3.1A Frame Check Sequence
The FCS on the transmitter or receiver may be either 16 bit or 32 bit, and is user selectable. For full duplex operation, both the receiver and transmitter have individual FCS computation circuits. The characteristics of the FeS are:
Transmitted Polarity:
Inverted
Transmitted Order:
High Order Bit First
Pre-set Value:
AII1's
Polynominal 16 bit:
><16 + ><12 + )(5
+
1
Remainder 16 bit (if received correctly):
high order bit- > 0001 1101 0000 1111
1·28
Polynominal 32 bit:
><32 + ){26 + )(23
+
)(22
+
X16
+
X12
+
><11
+
Xl0
+
XB
+ Xl +
X-5
+
X4
+
X-2
+
X
+
1
Remainder 32 bit (if received correctly):
high order bit--> 1100 0111 00000100
1101 1101 0111 1011
3.1.5 Receive FIFO
The Receive FIFO buffers the data received by the receiver. This performs two major functions. First, it resynchronizes
the data from the receive clock to the system clock. Second, it allows the microcontroller time to finish whatever
it may be doing before it has to process the received data.
The receive FIFO holds the data from the receiver without interrupting the microconroller until it contains enough
data to reach the watermark level. This watermark level can be programmed in CSR4 to occur when the FIFO
contains at least 2 bytes; 18 or more bytes; 34 or more bytes; or 50 or more bytes. This programmability, along
with the programmable burst length of the DMA controller, enables the user to define how often and for how long
the MK5025 must use the host bus. For more information, see Control/Status Register 4.
For example, if the watermark level is set at 34 bytes and the burst length is limited to 8 word transfers at a time,
the MK5025 will request control of the host bus as soon as 34 bytes are received and again after every 16 subsequent bytes.
3.1.6 Transmit FIFO
The Transmit FIFO buffers the data to be transmitted by the MK5025. This also performs two major functions. First,
it resynchronizes the data from the system clock to the transmit clock. Second, it allows the microcontroller and
DMA controller to read data from the host's memory buffers in bursts; making both the MK5025 and the host bus
more efficient.
The transmit FIFO has a watermark scheme similar to the one described for the receive FIFO above. The transmit
FIFO will not interrupt the microcontroller for service until it empties enough to reach the watermark level. The
watermark can be programmed in CSR4 as: any space available, 1a bytes of space available, 34 bytes of space
available, or 50 bytes of space available.
3.1.7 DMA Controller
The MK5025 has an on-chip DMA Controller circuit. This allows it to access memory without requiring host software intervention. Whenever the MK5025 requires access to the host memory it will negotiate for mastership of
the bus. Upon gaining control of the bus the MK5025 will begin transferring data to or from memory. The MK5025
will perform memory transfers until either it has nothing more to transfer, it has reached its DMA burst limit (user
programmable), or the BUSREL pin is driven low. In any case it will complete all bus transfers before releasing
bus mastership back to the host. If, during a memory transfer, the memory does not respond within 256 SCLK
cycles, the MK5025 will release ownership of the bus immediately and the MERR bit will be set in CSRO.
The DMA burst limit can be programmed by the user through CSR4. In 16 bit mode the limit can be set to 1 word,
a words, or unlimited word transfers. In a bit mode, it can be set to 2 bytes, 16 bytes, or unlimited byte transfers.
For high speed data lines (i.e. > 1 Mbps) a burst limit of a words, 16 bytes or unlimited is suggested to allow maximum throughput.
The byte ordering of the DMA transfers can be programmed to account for differences in processor architectures
or host programming languages. Byte ordering can be programmed seperately for data and control information.
Data information is defined as all contents of data buffers; control information is defined as anything else in the
shared memory space (I.e. initialization block, descriptors, etc). For more information see section 4.1.2.5 on control
status register 4.
3.1.8 Bus Slave Circuitry
The MK5025 contains a bank of internal control/status registers (CSRO-5) which can be accessed by the host as
a peripheral. The host can read or write to these registers like any other bus slave. The contents of these registers
and the bus signal timing is listed below.
1-29
3·5
3.2 Buffer Management Overview
Refer to Fig. 3.
3.2.1 The Initialization Block
Chip initialization information is located in a block of memory called the Initialization Block. The Initialization Block
consists of 44 contiguous words of memory starting on a word boundary. This memory is assembled by the HOST
or 1/0 acceleration processor, and is accessed by MK5025 during initialization. The Initialization Block is comprised of:
A. Mode of Operation.
B. Frame Address Values.
C. Timer Preset Values.
D. Location and size of Receive and Transmit Descriptor Rings.
E. Location and size of XIDITEST Buffers.
F. Location of status buffer.
G. Error Counters.
3.2.2 The Circular Queue
The basic organization of the buffer management is a circular queue of tasks in memory called descriptor rings.
There are separate rings to describe the transmit and receive operations. Up to 128 buffers may be queued-up
on a descriptor ring awaiting execution by the MK5025. The descriptor ring has a segment assigned to each buffer.
Each segment holds a pointer for the starting address of the buffer, and holds a value for the length of the buffer
in bytes.
Each segment also contains two control bits called OWNA and OWNB, which denote whether the MK5025, the
HOST, or the 1/0 ACCELERATION PROCESSOR (if present) "owns" the buffer. For transmit, when the MK5025
owns the buffer, the MK5025 is allowed and commanded to transmit the buffer. When the MK5025 does not own
the buffer, it will not transmit that buffer. For receive, when the MK5025 owns a buffer, it may place received data
into that buffer. Conversely, when the MK5025 does not own a receive buffer, it will not place received data in that
buffer.
3-6
1-30
RECEIVE BUFFERS
CSR2 , CSR3
r1
POINTER TO INITIALIZATION BLOCK
---,. v B
I
BUFFER
RECEIVER DESCRIPTOR RINGS
~ I- _ ~U~E~STATU~
0
__
",,,,,,,,
1 - -"m,
------I- -
,,"""
~;-F~ MsGCOON-:;:-
-
BUFFER
~'
DESCRIPTOR 1
•
•
•
•
•
•
INITIALIZATION BLOCK
~
MODE
~
DESCRIPTOR M
FRAME ADDRESS
FIELDS
BUFFER
M
TIMER VAWES
RECEIVE DESCRIPTOR
RING SET·UP
TRANSMIT DESCRIPTOR RINGS
TRANSMIT DESCRIPTOR
RING SET·UP
XIDITEST TRANSMIT
DESCRIPTOR
XID/TESt RECEIVE
DESCRIPTOR
t--I--
LI-+-
I-
,,_,Pro,'
_...,!'~F.=!I EA~~
__
f-o---- -
0
-
--
BUFFER SIZE
~-------BUFFER MSG COUNT
ERROR COUNTERS
DESCRIPTOR 1
XIDITEST TRANSMIT
BUFFER
~I
BUFFER ADDRESS
STATUS BUFFER
ADDRESS
XID/TEST RECEIVE
BUFFER
0
TRANSMIT BUFFE R
•
•
•
~
r-
DESCRIPTOR N
~
BUFFER
1
•
•
•
!--I"~~' I
Figure 3. MK5025 Buffer Management
1·31
3·7
The MK5025 buffer management mechanism will handle frames which are longer than the length of an individual
buffer. This is done by a chaining method which utilizes multiple buffers. The MK5025 tests the next segment in
the descriptor ring in a "look ahead" manner. If the frames are too long for one buffer, the next buffer will be used
after filling (or transmitting) the first buffer; that is, "chained". The MK5025 will then "look ahead" to the next buffer,
and chain that buffer if necessary, and so on.
The operational parameters for the buffer management are defined by the user in the initialization block. The
parameters defined include the basic mode of operation, the number of entries for the transmitter and receiver
descriptor rings, frame Address field, and etc. The starting address for the Initialization, IADR, is defined in the
CSR2 and CSR3 registers inside the MK5025.
3.2.3 Frame Format
The frame format used by the MK5025 is shown below. Each frame consists of a programmable number of leading
flag patterns (01111110), an address field, a control field, an information field (not in all frames), an FCS of either
16 or 32 bits, and a trailing flag pattern. The number of leading flags is programmable through the Mode Register
in the Initialization Block. Received frames may have only one flag between adjacent frames.
F
000
S bits
F
A
C
S
S/16
SI16
SOn
FCS
F
16/32
S
Transmitted First
3.2.4 The Command/Response Repertoire
The command/response repertoire of the MK5025 is shown in Tables la and lb. This set conforms to the ISDN
LAPD, which is a super-set of X.25 Link Level. The MK5025 will process the Sand U frames shown in Table I,
and will handle the A and C fields for all I and UI frames.
The definitions for the symbols for the frame types are:
Name
Definition
I
Information frame
Unnumbered Information
Receiver Ready
Disconnect
Receiver Not Ready
Unnumbered Acknowledge
Reject
Frame Reject
Set Asynchronous Balance Mode
Disconnect Mode
Exchange Identification
Link Test frame
UI
RR
DISC
RNR
UA
REJ
FRMR
SABM
DM
XID
TEST
3·8
1-32
Table la. MK5025 Command/Response Repertoire.
Modulo 8 Operation
Format
Information Transfer
I
Supervisory
RR
RNR
REJ
Unnumbered
Resp
Command
RR
RNR
REJ
SABM
'XID
'UI
DISC
'TEST
DM
'XID
'U!
UA
FRMR
'TEST
Encoding
1
2
3
0
+-
N(S)
1
1
1
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
5
6
7
P
+-
N(R)
->
0
0
1
P/F
P/F
P/F
+-
->
+-
N(R)
N(R)
N(R)
1
1
1
0
0
0
0
0
P
F
P/F
P/F
P
F
F
P/F
1
0
1
0
0
1
0
1
0
0
0
0
1
1
0
1
4
->
+-
8
->
->
0
0
1
0
0
0
1
1
Table lb. MK5025 Command/Response Repertoire.
Modulo 128 Operation.
Format
Command
Resp
Encoding
2
3
4
1
1
1
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
1
Information Transfer
I
Supervisory
RR
RNR
REJ
Unnumbered
SABME
'XID
'UI
DISC
'TEST
DM
'XID
'UI
UA
FRMR
'TEST
6
7
8
0
0
0
0
0
0
0
0
0
0
0
0
P
F
P/F
P/F
P
F
F
P/F
1
0
1
0
0
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
0
0
1
1
N(S)
0
RR
RNR
REJ
5
9
10·16
P
N(R)
P/F N(R)
P/F N(R)
P/F N(R)
.. XID and UI Frames can be individually enabled for compatibility with X.32
and LAPD respectively. TEST frames are enabled with XID frames.
1-33
3-9
3.3 Pin Description
VSS·GND
1
48
VCC (+5V)
DAL07
2
47
DAL08
DAL06
3
46
DAL09
DAL05
4
45
DALlo
DAL04
5
44
DAL11
DAL03
6
43
DAL12
DAL02
7
42
DAL13
DALol
8
41
DAL14
DALoo
9
40
DAL15
READ
10
39
A16
INTR
11
38
A17
DALI
12
37
A18
DALO
13
36
A19
DAS
14
35
A20
BMo, BYTE, BUSREL
15
34
A21
BM1, BUSAKO
16
33
A22
17
32
A23
18
31
RD
HLDA
19
3D
DSR, CTS
CS
20
29
TO
--HOLD, BUSRO
ALE, AS
3·10
MK5025
ADR
21
28
SYSCLK
READY
22
27
RCLK
RESET
23
26
DTR, RTS
VSS·GND
24
25
TCLK
1-34
PIN DESCRIPTION
LEGEND:
Input only
I
Output only
0
Input/Output
10
3S
OD
SIGNAL
3-State
Open Drain (no internal pull-up)
Active low signal, i.e., inverted
SIGNAL NAME
PINeS)
TYPE
DESCRIPTION
DAL<7:00>
2-9
10/3S
The time multiplexed Data/Address bus. During the address portion of the
memory transfer, DAL < 7:00 > contains the lower 8 bits of the memory address. During the data portion of a memory transfer, DAL < 7:00 > contains
the read or write data, depending on the type of transfer.
READ
10
10/3S
READ indicates the type of operation that the bus controller is performing
during a bus transaction. READ is driven by the MK5025 only while it is
the BUS MASTER. READ is valid during the entire bus transaction and is
tristated by the MK5025 at all other times.
MK5025 as a Bus Slave
READ = HIGH - Data is placed on the DAL lines by the chip.
READ = LOW - Data is taken off the DAL lines by the chip.
MK5025 as a Bus Master
READ = HIGH - Data is taken off the DAL lines by the chip.
READ = LOW - Data is placed on the DAL lines by the chip.
INTR
11
OIOD
INTERRUPT is an attention interrupt line that indicates that one or more
of the following CSRO status flags is set: MISS, MERR, RINT, TINT or PINT.
INTERRUPT is enabled by CSRO<09>, INEA=1.
DALI
12
0/3S
DAL IN is an external bus transceiver control line. DALI is driven by the
MK5025 only while it is the BUS MASTER. DALI is asserted by MK5025
when it reads from the DAL lines during the data portion of a READ transfer. DALI is not asserted during a WRITE transfer.
DALO
13
0/3S
DAL OUT is an external bus transceiver control line. DALO is driven by
the MK5025 only while it is the BUS MASTER. DALO is asserted by MK5025
when it drives the DAL lines during the address portion of a READ transfer
or for the duration of a WRITE transfer.
DAS
14
10/3S
DATA STROBE defines the data portion of a bus transaction. By definition
data is stable and valid at the low to high transition of DAS. This Signal is
driven by the MK5025 while it is the BUS MASTER. During Bus Slave operations, this pin is used as an input. At all other times the signal is tristated.
BMO
BYTE
BUSREL
15
10/3S
I/O pins 15 and 16 are programmable through CSR4. If bit 06 of CRS4 is
set to a one, pin 15 becomes input BUSREL and is used by the host to signal the MK5025 to terminate a DMA burst after the current bus transfer has
completed. If bit 06 is clear then pin 15 is an output and behaves as
described below for pin 16.
BM1
BUSAKO
16
0/3S
Pins 15 and 16 are programmable through bit 00 of CSR4 (BCON).
= 0,
I/O PIN 15 = BMO (0/3S)
I/O PIN 16 = BM1 (0/3S)
If CSR4<00> BCON
1-35
3·11
SIGNAL NAME
PINeS)
TYPE
DESCRIPTION
BYTE MASK<1:0> Indicates the byte(s) on the DAL to be read or written
during this bus transition. MK5025 drives these lines only as a Bus Master.
MK5025 ignores the BM lines when it is a Bus Slave.
Byte selection is done as outlined in the following table.
BM1
BMO
LOW
LOW
LOW
HIGH
HIGH
LOW
HIGH
HIGH
ENTIRE WORD
UPPER BYTE
(DAL<15:08»
LOWER BYTE
(DAL < 07:00 > )
NONE
If CSR4<00> BCON = 1,
1/0 PIN 15 = BYTE (0/3S)
1/0 PIN 16 = BUSAKO (0)
Byte selection is done using the BYTE line and DAL <00 > latched during
the address portion of the bus transaction. MK5025 drives BYTE only as
a Bus Master and ignores it when a Bus Slave. Byte selection is done as
outlined in the following table.
BYTE
DAL
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
ENTIRE WORD
ILLEGAL CONDITION
LOWER BYTE
UPPER BYTE
BUSAKO is a bus request daisy chain output. If MK5025 is not requesting
the bus and it receives HLDA, BUSAKO will be driven low. If MK5025 is
requesting the bus when it receives HLDA, BUSAKO will remain high.
HOLD
BUSRQ
17
1010D
Pin 17 is configured through bit 0 of CSR4.
If CSR4 BCON = 0
1/0 PIN 17 = HOLD
HOLD request is asserted by MK5025 when it requires a DMA cycle regardless of the previous state of the HOLD pin. HOLD is held low for the entire
ensuring bus transaction.
If CSR4 BCON = 1
1/0 PIN 17 = BUSRQ
BUSRQ is asserted by the MK5025 when it requires a DMA cycle if the prior
state of the BUSRQ pin was high. BUSRQ is held low for the entire ensuing bus transaction.
ALE
AS
18
0/3S
The active level of ADDRESS STROBE is programmable through CSR4.
The address portion of a bus transfer occurs while this signal is at its asserted level. This signal is driven by the MK5025 while it is the BUS
MASTER. At all other times, the signal is tristated.
If CSR4<01 > ACON
1/0 PIN 18 = ALE
=
0
ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define the address portion of the transfer. As ALE, the signal transitions from
high to low during the address portion of the transfer and remains low during the data portion.
3-12
1·36
SIGNAL NAME
PIN(S)
TYPE
DESCRIPTION
If CSR4<01 > ACON = 1,
1/0 PIN 18 = AS
As AS, the signal pulses low during the address portion of the bus transfer.
The low to high transition of AS can be used by a slave device to strobe
the address into a register.
HLDA
19
HOLD ACKNOWLEDGE is the response to HOLD. When HLDA is low in
response to MK5025's assertion of HOLD, the MK5025 is the Bus Master.
HLDA should be disasserted ONLY after HOLD has been released by
MK5025; otherwise the MK5025 will interpret the raising of HLDA as a
memory error (see CSRO).
CS
20
CHIP SELECT indicates, when low, that the MK5025 is the slave device for
the data transfer. CS must be valid throughout the entire transaction.
ADR
21
ADDRESS selects the Register Address Port or the Register Data Port. It
must be valid throughout the data portion of the transfer and is only used
by the chip when CS is low.
READY
22
1010D
ADR
PORT
LOW
HIGH
REGISTER DATA PORT
REGISTER ADDRESS PORT
When the MK5025 is a Bus Master, READY is an asynchronous acknowledgement from the bus memory that memory will accept data in a WRITE
cycle or that memory has put data on the DAL lines in a READ cycle.
As a Bus Slave, the MK5025 asserts READY when it has put data on the DAL
lines during a READ cycle or is about to take data from the DAL lines during a WRITE cycle. READY is a response to DAS and it will be negated after
DAS is negated.
RESET
23
RESET is the Bus signal that will cause MK5025 to cease operation, clear
its internal logic and enter an idle state with the STOP bit of CSRO set.
TCLK
25
TRANSMIT CLOCK. A 1X clock input for transmitter timing. TD changes
on the falling edge of TCLK. The frequency of TCLK may be up to 7 Mbps.
DTR
RTS
26
RCLK
27
RECEIVE CLOCK. A 1X clock input for receiver timing. RD is sampled on
the rising edge of RCLK. The frequency of RCLK may be up to 7 MHz.
SYSCLK
28
SYSTEM CLOCK. SYSTEM CLOCK. System clock used for internal timing
of MK5025. SYSCLK should be a square wave, and be greater than 500
KHz and less than 10 MHz.
TD
29
a
TRANSMIT DATA. Transmit serial data output.
DSR
CTS
30
10
DATA SET READY, CLEAR TO SEND. Modem Control Pin. Pin 30 is configurable through CSR5. This pin can be programmed to behave as input
CTS or as programmable 10 pin DSR. If configured as CTS, the MK5025
will transmit all 1's while CTSis high.
10
DATA TERMINAL READY, REQUEST TO SEND. Modem Control Pin. Pin
26 is configurable through CSR5. This pin can be programmed to behave
as output RTS or as programmable 10 pin DTR. If configured as RTS, the
MK5025 will assert this pin if it has data to send and throughout transmission of a frame.
1-37
3-13
SIGNAL NAME
PINeS)
RD
31
A<23:16>
32-39
0/3S
Address bits <23:16> used in conjunction with DAL<15:00> to produce
a 24 bit address. MK5025 drives these lines only as a Bus Master.
DAL<15:08>
40-48
10/3S
The time multiplexed Data/Address bus. For 16-bit operations, DAL <15:08>
behaves similar to DAL < 07:00 > above for the high byte of data or the middle byte of the 24 bit address. For 8-bit operations, DAL < 15:08 > behaves
similar to a < 23:16 > for the middle byte of the 24-bit address only.
VCC-GND
1,24
VCC
48
3-14
TYPE
DESCRIPTION
RECEIVE DATA. Received serial data input.
Power Supply Pin.
+5.0 VDC ±5%
1-38
SECTION 4
PROGRAMMING SPECIFICATION
This section defines the Control and Status Registers and the memory data structures required to program the
MK5025.
4.1 Control and Status Registers
There are six Control and Status Registers (eSR's) resident within MK5025. The eSR's are accessed through two
bus addressable ports, an address port (RAP), and a data port (RDP). Thus the MK5025 needs only two address
locations in the system memory or 10 map.
4.1.1 Accessing the Control and Status Registers
The eSR's are read (or written) in a two step operation. The address of the eSR is written into the address port
(RAP) during a bus slave transaction. During a subsequent bus slave transaction, the data being read from (or
written into) the data port (RDP) is read from (or written into) the eSR selected in the RAP. Once written, the address in RAP remains unchanged until rewritten. A control 1/0 pin (ADR) is provided to distinguish the address
port from the data port.
ADR
Port
L
H
Register Data Port (RDP)
Register Address Port (RAP)
4.1.1.1 Register Address Port (RAP)
1
1
1
1
5
4
3
2
1 0 0
098
0
7
0
6
0
5
0
4
0
3
000
2 1 0
I
0
0
0
0
0
0
0
0
B
M
8
0
0
0
I
eSR
<2:0>
I I
H
B
Y
T
E
BIT
NAME
DESCRIPTION
15:08
RESERVED
Must be written as zeroes.
07
BM8
When set, places chip into 8 bit mode. eSR's, Init Block, and data transfers are all
8 bit transfers; this provides compatibility with 8 bit microprocessors. When clear, all
transfers are 16 bit transfers. This bit must be set to the same value each time it is
written, changing this bit during normal operation will achieve unexpected results. BM8
is READIWRITE and cleared on Bus RESET.
06-04
RESERVED
Must be written as zeroes.
03:01
eSR<2:0>
eSR address select bits. READIWRITE. Selects the eSR to be accessed through the
RDP. RAP is cleared by Bus RESET.
eSR<2:0>
0
1
2
3
4
5
eSR Selected
eSRO
eSR1
eSR2
eSR3
eSR4
eSR5
1-39
4-1
00
Determines which byte is addressed for a bit operation. If set, the high byte of the
register referred to by CSR < 2:0 > is addressed, otherwise the low byte is addressed.
This bit is only meaningful for a bit operation and must be written as zero if BMa =
o. HBYTE is READIWRITE and cleared on Bus Reset.
HBYTE
4.1.1.2 Register Data Port (RDP)
111110000000000
5 4 3 2
0 9 a 7 6 5 432 1 0
I: : : : : :
~~:~: : : : : :
i
BIT
NAME
DESCRIPTION
15:00
CSR DATA
Writing data to the RDP loads data into the CSR selected by RAP. Reading the data
from RDP reads the data from the CSR selected in RAP.
4.1.2 Control and Status Register Definition
4.1.2.1 Control and Status Register 0 (CSRO)
RAP<3:1> = 0
1
5
1 1 1
432
T S
D T
M 0
D P
D
T
X
1
o
D T R
R X X
X 0 0
N N
0
9
000
a 7 6
0
5
I
N
E
A
I M M R
N E I 0
T R S R
R R S
0
4
0 000
321 0
T
P
I
N
T
U
R
T
I
N
T
R
I
N
T
0
BIT
NAME
DESCRIPTION
15
TDMD
TRANSMIT DEMAND, when set, causes MK5025 to access the Transmit Descriptor
Ring without waiting for the transmit politi me interval to elapse. TDMD need not be
set to transmit a frame, it merely hastens MK5025's response to a Transmit Descriptor
Ring entry insertion by the host. TDMD is WRITE WITH ONE ONLY and cleared by
the MK5025 after it is used. It may read as a "1" for a short time after it is written
because the MK5025 may have been busy when TDMD was set. It is also cleared
by Bus RESET. Writing a "0" in this bit has no effect.
14
SlOP
SlOp, when set, indicates that MK5025 is operating in the SlOPPED phase of operation. All external activity is disabled and internal logic is reset. MK5025 remains inactive except for primitive processing until a START primitive is issued. SlOP IS READ
ONLY and set by Bus RESET or a SlOP primitive. Writing to this bit has no effect.
13
DTX
Transmitter Ring Disable prevents the MK5025 from further access to the Transmitter
Descriptor Ring. No transmissions are attempted after finishing transmission of any
frame in transmission at the time of DTX being set. DTX is READIWRITE. TXON acknowledges changes to DTX, see below.
12
DRX
Receiver Ring Disable prevents the MK5025 from further accesss to the Receiver
4.·2
1-40
Descriptor Ring. No received frames are accepted after finishing reception of any frame
in reception at the time of DRX being set. If DRX is set while a data link is established
the MK5025 will go into the local busy condition and will send a RNR response frame
to the remote station. DRX is READIWRITE. RXON acknowledges changes to DRX,
see below.
11
TXON
TRANSMITTER ON indicates that the transmitter ring access is enabled. TXON is set
as the START primitive is issued if the DTX bit is "0" or afterward as DTX is cleared.
TXON is cleared upon recognition of DTX being set, by issuing a STOP primitive in
CSR1, or by a Bus RESET. If TXON is clear, the host may modify the Transmit Descriptor Ring entries regardless of the state of the OWNA bits. TXON is READ ONLY; writing this bit has no effect.
10
RXON
RECEIVER ON indicates that the receiver ring access is enabled. RXON is set as the
START primitive is issued if the DRX bit is "0" or afterward as DRX is cleared. RXON
is cleared upon recognition of DRX being set, by sending a STOP primitive in CSR1,
or by a Bus RESET. If RXON is clear, the host may modify the Receive Descriptor Ring
entries regardless of the state of the OWNA bits. RXON is READ ONLY; writing this
bit has no effect.
09
INEA
INTERRUPT ENABLE allows the INTR I/O pin to be driven low when the Interrupt
Flag is set. If INEA = 1 the INTR I/O pin will be low if CSRO < 08 > INTR is set. If
INEA = 0 the INTR I/O pin will be high, regardless of the state of the Interrupt Flag.
INEA is READIWRITE, set by writing a "1" into this bit and is cleared by writing a "0"
into this bit or by Bus RESET or by issuing a STOP primitive.
on
INTR
INTERRUPT FLAG indicates that one or more of the following interrupt causing conditions has occurred; MISS, MERR, RINT, TINT, PINT, TUR or ROR. If INEA = 1 and
INTR = 1 the INTR I/O pin will be low. INTR is READ ONLY, writing t/;'.;, bit has no
effect. INTR is cleared as the specific interrupting condition bits are cleared. INTR is
also cleared by Bus RESET or by issuing a STOP primitive.
07
MERR
MEMORY ERROR sets when MK5025 is the Bus Master and has not received READY
'''Iithin 256 SYSCLKs (25.6 usec @ 10 MHz) after asserting the address on the DAL
lines. A memory error is also caused by the deassertion of HLDA during a bus transaction. When a Memory Error is detected, the receiver and transmitter are turned off
and an interrupt is generated if INEA = 1. MERR is READ/CLEAR ONLY and is set
by the chip and cleared by writing a "1" into the bit. Writing a "0" has no effect. It
is cleared by Bus RESET or by issuing a STOP primitive.
06
MISS
MISSED PACKET is set when the receiver loses a packet because it does not own
a receive buffer and the fifo has overflowed, indicating loss of a frame. When MISS
is set, an interrupt will be generated if INEA = 1. MISS is READ/CLEAR ONLY and
is set by MK5025 and cleared by writing a "1" into the bit. Writing a "0" has no effect.
It is also cleared by Bus RESET or by issuing a STOP primitive.
05
ROR
RECEIVER OVERRUN indicates that the Receiver FIFO was full when the receiver
was ready to input data to the Receiver FIFO, The frame being received is lost but
is recoverable according to the Link Level protocol. When ROR is set, an interrupt is
generated if INEA = 1. ROR is READ/CLEAR ONLY and is set by MK5025 and cleared
by writing a "1" into the bit. Writing a "0" has no effect. It is also cleared by Bus RESET
or by issuing a STOP primitive.
04
TUR
TRANSMITTER OVERRUN indicates that the MK5025 has aborted a frame since data
was late from memory. This condition is reached when the transmitter and transmitter
FIFO both become empty while transmitting a frame. When TUR is set, an interrupt
is generated if INEA = 1. TUR is READ/CLEAR ONLY and is set by MK5025 and cleared
by writing a "1" into the bit. Writing a "0" has no effect. It is also cleared by Bus RESET
or by issuing a STOP primitive.
1-41
4-3
03
PINT
PRIMITIVE INTERRUPT is set after the chip updates the. primitive register either to
issue a provider primitive or to accept a user primitive. When PINT is set, an interrupt
is generated if INEA = 1. PINT is READ/CLEAR ONLY and is set by MK5025 and
cleared by writing a "1" into the bit. Writing a "0" has no effect. It is also cleared by
Bus RESET or by issuing a STOP primitive.
02
TINT
TRANSMITTER INTERRUPT is set after the chip updates an entry in the Transmit
Descriptor Ring. This occurs when a transmitted frame has been acknowledged by
the remote station. When TINT is set, an interrupt is generated if INEA = 1. TINT is
READ/CLEAR ONLY and is set by MK5025 and cleared by writing a "1" into the bit. Writing a "0" has no effect. It is also cleared by Bus RESET or by issuing a STOP primitive.
01
RINT
RECEIVER INTERRUPT is set after MK5025 updates an entry in the Receive Descriptor
Ring. This occurs when the MK5025 has received a correct frame from the remote
station. When RINT is set, an interrupt is generated if INEA = 1. RINT is READ/CLEAR
ONLY and is set by MK5025 and cleared by writing a "1" into the bit. Writing a "0"
has no effect. It is cleared by Bus RESET or by issuing a STOP primitive.
00
o
This bit is READ ONLY and read always as a zero.
4.1.2.2 Cont.rel and Status Register 1 (CSR1)
RAP<3:1> = 1
1
1
1
1
5
4
3
2
1
o
000
0
0
9
7
6
5
P
L
P
A
V
pi
8
T I I
0
0
UPRIM
<3:0>
I
I
0
I
S
T
0 0 000
432
0
P 1
A
R 0
MI
TTl
PPRIM
<3:0>
I
I
I
BIT
NAME
DESCRIPTION
15
UERR
USER PRIMITIVE ERROR is set by the MK5025 when a primitive issued by the user
is in conflict with the current status of the link. UERR is READ/CLEAR ONLY and is
set by MK5025 and cleared by writing a "1" into the bit. Writing a "0" in this bit has
no effect. It is also cleared by Bus RESET.
14
UAV
USER PRIMITIVE AVAILABLE is set by the user after a primitive has been placed in
UPRIM. It is cleared by the MK5025 after the primitive has been processed. This bit
is also cleared by a Bus RESET.
13:12
o
Reserved, must be written as zeroes.
11:08
UPRIM
USER PRIMITIVE is written by the user to control the MK5025 link procedures. The
following values are valid:
o
Stop - Instructs MK5025 to go into STOPPED Mode. All link activity is terminated
and the STOP bit is set. Transmitter outputs all "l"s. All DMA activity ceases.
Start - Instructs MK5025 to exit STOPPED Mode and enter the Disconnected Phase.
Descriptor Rings are reset. Transmitter begins outputting flags. Valid only In
STOPPED Mode.
2
4·4
Init Request - Instructs MK5025 to read the initialization block. Valid only in
STOPPED Mode and Disconnected Phase. This should be performed prior to the
start primitive after a bus reset or powerup.
1-42
3
Trans -Instructs MK5025 to enter the Transparent phase of operation. Data frames
are transmitted and received out of the descriptor rings but no protocol processing
is done. Address and Control Fields are not prepended to the frames, but FCS
processing works normally. If the PROM bit is set in CSR2 then no address filtering is performed on received frames. Transparent Mode may be eXited only with
a stop primitive or by bus reset.
4
Status Request - Instructs MK5025 to write the current link status into the STATUS
buffer. Valid only if INIT primitive has previously been issued.
6
Connect request - Instructs MK5025 to attempt to establish a logical link with the
remote site. Valid only in Disconnected Phase.
7
Connect Response - Indicates willingness to establish a logical link with the remote site. Valid only in Disconnected Phase after receiving a Connect Indication
primitive.
8
Reset Request - Instructs MK5025 to attempt to reset the current logical link with
the remote site. Invalid in STOPPED Mode and Disconnected Phase.
9
Reset Response - Indicates willingness to reset current logical link with remote
site. Valid only after receiving a Reset Indication primitive.
10 XID Request - Requests MK5025 to send an XID command to the remote site. Data
in the XlDrrEST Transmit buffer is used for the Data Field. Invalid in STOPPED
Mode.
11 XID Response - Requests MK5025 to send an XID response to the remote site.
Data in the XIDrrEST Transmit Buffer is used for the Data Field. Valid only after
receiving an XID Indication primitive.
12 TEST Request - Requests MK5025 to send a TEST command to the remote site.
Data in the XIDrrEST Transmit Buffer is used for the Data Field. Invalid in STOPPED
Mode.
13 TEST Response - Requests MK5025 to send a TEST response to the remote site.
Data in the XIDrrEST transmit buffer is used for the data field. Valid only after receiving a TEST indication primitive.
14 Disconnect Request - Requests MK5025 to disconnect the currer' logical link. Invalid in STOPPED Mode. A DM response with the F bit clear will be sent if the
link is currently disconnected.
07
PLOST
PROVIDER PRIMITIVE LOST is set by MK5025 when a provider primitive cannot be
issued because the PAV bit is still set from the previous provider primitive. PLOST is
cleared when PAV is cleared and by a Bus RESET. Writing to this bit has no effect.
06
PAV
PROVIDER PRIMITIVE AVAILABLE is set by the MK5025 when a new provider primitive has been placed in PPRIM. PPRIM is READ/CLEAR ONLY and is set by the chip
and cleared by writing a "1" to the bit or by Bus RESET.
1·43
4-5
05:04
PPARM
PROVIDER PARAMETER provides additional information about the reason for the
receipt of a disconnect, reset or error indication primitive. This field is undefined for
other provider primitives. Parameters are as follows:
PPARM
0
Disconnect
Indication
Reset
Indication
Remotely
Initiated
Remotely
Initiated
Timer Rec
Timeout
SABM
Timeout
03:00
PPRIM
Error
Indication
2
FRMR Sent and
DISC or DM Received
3
T3 Timeout
FRMR Sent and
SABM/E Recvd
FRMR
Received
Unsolicited UA or
F bit Received
PROVIDER PRIMITIVE is written by MK5025 to inform the user of link control conditions. Valid Provider Primitives are as follows:
2
Init Confirmation - Indicates that the initialization has completed.
4
Error Indication - Indicates an error condition has occurred during the Information
Transfer phase of operation that requires instruction by the Host for recovery. See
PPARM for specific error conditions. Either a Reset Request or Disconnect Request primitive should be issued in UPRIM after receiving an Error Indication
primitive.
6
Connect Indication - Indicates an attempt by the remote site to establish a logical
link. Appropriate user responses are Connect Response and Disconnect Request.
7
Connect Confirmation - Indicates the success of a previous Connect Request by
the user. A logical link is now established.
8
Reset Indication - Indicates an attempt by the remote site to reset the current logical link. Appropriate user responses are Reset Response and Disconnect Request.
9
Reset Confirmation - Indicates the success of a previous Reset Request by the
user. The current logical link has now been reset.
10 XID Indication - Indicates the receipt of an XID command. The Data Field of the
XID command is located in the XIDITEST Receive Buffer.
11 XID Confirmation - Indicates the receipt of an XID response. The Data field of the
XID response is located in the XIDITEST Receive Buffer.
12 TEST Indication - Indicates the receipt of a TEST command. The Data Field of the
TEST command is located in the XIDITEST Receive buffer.
13 TEST Confirmation - Indicates the receipt of a TEST response. The Data field of
the TEST response is located in the XIDITEST Receive Buffer.
14 Disconnect Indication - Indicates a request by the remote site to disconnect the
current logical link or the refusal of a previous Connect or Reset Request. The chip
is now in the Disconnected Phase.
4-6
1-44
4.1.2.3 Control and Status Register 2 (CSR2)
RAP<3:1> = 2
1 1 1
543
1
2
x
o
0
0
0
1
0
9
0 0 0
876
P
R
U
I
E
X
I
D
E
o
7
5
E
0
M
0
5
I I
0 0 0
432
I
I
I
0
1
I
0
0
I
IADR<23:16>
1 I I I I I I
BIT
NAME
DESCRIPTION
15:12
0
Reserved, must be written as zeroes.
n
X75E
X.75 mode is enabled if this bit is set to 1; otherwise X.75 mode is enabled. This bit
is READIWRITE and cleared on Bus Reset.
10
PROM
Address filtering is disabled for transparent mode, if this bit is set. All uncorrupted incoming frames are placed in the Receive Descriptor Ring. This bit is READIWRITE
and cleared on bus reset.
09
UIE
UI frames are recognized only if this bit is set. If UIE = 0 all received UI frames will
not be recognized. This bit is READIWRITE and cleared on Bus Reset.
08
XI DE
XID frames are recognized only if this bit is set. If XIDE = 0 all received XID frames
will not be recognized. This bit is READIWRITE and cleared on Bus Reset.
07:00
IADR
The high order 8 bits of the address of the first word (lowest address) in the Initialization Block. IADR must be written by the Host prior to issuing an INIT primitive.
4.1.2.4 Control and Status Register 3 (CSR3)
RAP<3:1> = 3
1
5
1 1 1
432
1
o
0
9
0
8
0
7
0
6
0
5
0 0 0
432
0
1
0
0
BIT
NAME
DESCRIPTION
15:00
IADR
The low order 16 bits of the address of the first word (lowest address) in the Initialization Block. Must be written by the Host prior to issuing an INIT primitive. The Initialization Block must be on an even byte boundary.
1-45
4·7
4.1.2.5 Control and Status Register 4 (CRS4)
CSR4 allows redefinition of the bus master interface.
RAP<3:1> = 4
1 1 1
543
1
2
1
o
0
9
0 0 0
876
0
FWM
<1:0>
1
0
0
0
0
0
0
I
000
543
B B BI
U S U 1
S W R :
R P S 0
C TI
000
2 1 0
B A
S C
W 0
P N
D
B
C
0
N
BIT
NAME
DESCRIPTION
15:10
o
Reserved, must be written as zeroes.
09:08
FWM
These bits define the FIFO watermarks. FIFO watermarks prevent the MK5025 from
performing DMA transfers to/from the data buffers until the FIFOs contain a minimum
amount of data or space for data. For receive data, data will only be transferred to the
data buffers after the FIFO has at least N 16-bit words or an end of frame has been
reached. Conversely, for transmit data, data will only be transferred from the data buffers
when the transmit FIFO has room for at least N words of data. N is defined as follows:
N
1 word
9 words
17 words
25 words
FWM<1:0>
00
01
10
11
o
Reserved, must be written as zeroes.
06
BUSR
If this bit is set, pin 15 becomes input BUSREL. If this bit is clear pin 15 is either
BMO or BYTE depending on bit 00. For more information see the description for pin 15
earlier in this document.
05
BSWPC
This bit determines the byte ordering of all "non-data" DMA transfers. "Non-data" DMA
transfers refers to any DMA transfers that access memory other than the data buffers
themselves. This includes the Initialization Block, Descriptors, and Status Buffer. It has
no effect on data DMA transfers. BSWPC allows MK5025 to operate with memory organizations that have bits <07:00> at even addresses with bits <15:08> at odd addresses or vice versa.
With BSWPC = 1:
XXO
o
1".1
XX1
7
8
1"'115
This memory organization is used with the LSI 11 microprocessor and the 8086
microprocessor.
1·46
With BYTE SWAP = 0:
XXO
1".1151
8
XX1
o
1".1
7
I
This memory organization is used with the 68000 and Z8000 microprocessors. BSWP
is ReadlWrite and cleared by BUS RESET.
04:03
This field determines the maximum number of data transfers performed each time control of the host bus is obtained.
BURST
BURST<1:0>
8 bit Mode
16 bit Mode
00
10
01
2 bytes
16 bytes
unlimited
1 word
8 words
unlimited
BURST is READIWRITE and cleared on Bus RESET.
02
BSWPD
This bit determines the byte ordering of all data DMA transfers. Data transfers are those
to or from a data buffer. BSWPD has no effect on non-data transfers. The effect of
BSWPD on data transfers is the same as that of BSWPC on non-data transfers (see
above).
01
ACON
ALE CONTROL defines the assertive state of Pin 18 when MK5025 is a Bus Master.
ACON is READIWRITE and cleared by Bus RESET.
ACON
00
o
ALE
1
AS
High
Low
BYTE CONTROL redefines the Byte Mask and Hold 1/0 pins. BCON is READIWRITE
and cleared by Bus RESET.
BCON
BCON
PIN 16
PIN 15
o
BM 1
BUSAKO
BM 0
BYTE
1
PIN 17
4.1.2.6 Control and Status Register 5 (CSR5)
CSR5 facilitates control and monitoring of modem controls.
RAP<3:1> = 4
1 1 1
543
0
0
0
1
2
0
1
o
0
0
0
0
0
0
0
0
0
000
9
8
7
6
5
4
3
2
1
0
0
R
T
S
E
N
D
T
R
D
D
S
R
D
D
T
R
D
S
R
0
0
0
1·47
0
4-9
BIT
NAME
DESCRIPTION
15:05
o
Reserved, must be written as zeroes.
4
RTSEN
RTS/CTS ENABLE is a READIWRITE bit used to configure pins 26 and 30. If this bit
is set pin 26 becomes RTS and pin 30 becomes DSA. RTS is driven low whenever
the MK5025 has data to transmit and kept low during transmission. RTS will be driven
high after the closing flag of a frame transmitted if either no other frames are in the
FIFO or if the minimum frame spacing is higher than 2 (see Mode Register). The
MK5025 will not begin transmission and TD will remain HIGH if CTS is high.
3
DTRD
DTR DIRECTION is a READ/WRITE bit used to control the direction of the DTR pin.
If DTRD = 0, the DTR pin becomes an input pin and the DTR bit reflects the current
value of the pin; if DTRD = 1, the DTR pin is an output pin controlled by the DTR bit
below.
2
DSRD
DSR DIRECTION is a READIWRITE bit used to control the direction of the DSR pin.
If DSRD = 0, the DSR pin becomes an input pin and the DSR bit reflects the current
value of the pin; if DSRD = 1, the DSR pin is an output pin controlled by the DSR
bit below.
DTR
DATA TERMINAL READY is used to control or observe the DTo 1/0 pin depending
on the value of DTRD. If DTRD = 0, this bit becomes READ ONL'Y and always equals
the current value of the DTR pin. If DTRD = 1, this bit becomes READ/WRITE and
any value written to this bit appears on the DTR pin.
DSR
DATA SET READY is used to control or observe the DSR 110 pin depending on the
value of DSRD. If DSRD = 0, this bit becomes READ ONLY and always equals the
current value of the DSR pin. If DSRD = 1, this bit becomes READ/WRITE and any
value written to this bit appears on the DSR pin.
o
4.2 Initialization Block
MK5025 initialization includes the reading of the initialization block in memory to obtain the operating parameters.
The Initialization Block is defined on the next page..
The Initialization Block is read by MK5025 when receiving an INIT primitive. During normal initialization the INIT
should be sent prior to sending a START primitive. The user may re-issue the INIT primitive after a START, but
received frames may be lost if care is not taken. An INIT cannot be issued while a link is connected; MK5025
will reject such an attempt.
Except for the Error Counters and XIDITEST Descriptor OWNA bits, the MK5025 will not write into the Initialization
Block.
4·10
1-48
BASE ADDRESS
MODE
IADR+OO
LOCAL STATION ADDRESS
IADR+02
REMOTE STATION ADDRESS
IADR+04
N1
IADR+06
N2 + SCALER
IADR+08
T1 TIMER
IADR+10
T3 TIMER
IADR+12
TP TIMER
IADR+14
RLEN-RDRA <23:16>
IADR+16
RDRA <15:00>
IADR+18
TLEN:rDRA <23:16>
IADR+20
TDRA <15:00>
IADR+22
XIDITEST TRANSMIT
DESCRIPTOR
IADR+24
XIDITEST RECEIVE
DESCRIPTOR
IADR+32
STATUS BUFFER ADDRESS
IADR+40
SIX ERROR COUNTERS
IADR+44
thru
IADR+55
HIGHER ADDR
Figure 4. Initialization Block
4.2.1 Mode Register
The Mode Register allows alteration of the MK5025's operating parameters.
1
1
543
1
1
2
I
I
I
1
I
MFS<4:0>
I I I I
15:11
0
o
9
E
X
T
C
F
E
X
T
A
F
0 0 0
876
0
5
000
432
D
A
C
E
D
R
F
C
S
D
T
F
C
S
E
X
T
C
E
X
T
A
F
C
S
S
0
I
0
0
I
LBACK
<2:0>
I l
NAME
DESCRIPTION
MFS<4:0>
Minimum Frame Spacing defines the minimum number of flag sequences transmitted
between adjacent frames transmitted by the MK5025. This only affects frames transmitted by the MK5025 and does not restrict the spacing of frames received by the
MK5025. When using RTS/CTS control this field defines the number of flags transmitted at the beginning of the frame after CTS is driven low (minus one for the trailing
flag). See following table for encoding of this field.
1-49
4-11
NUMBER OF FLAGS
MFS<4:0>
NUMBER OF FLAGS
MFS<4:0>
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
0
2
4
9
18
5
11
22
12
25
19
7
15
31
30
28
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
24
17
3
6
13
27
23
14
29
26
21
10
20
8
16
10
EXTCF
Extended Control Force is useful only in transparent mode operation. If set along with
EXTC, the receiver will assume the control field to be two bytes long regardless of the
first two bits of the control field. See EXTC below.
09
EXTAF
Extended Address Force is useful only in transparent mode operation. If set along with
EXTA, the receiver will assume the address field to be two bytes long regardless of
the first bit of the address. See EXTA below.
08
DACE
Address and control field extraction are disabled when DACE is set. Address and control fields are treated as normal data. DACE must be written as "0" for normal operation in non-transparent mode.
07
EXTC
Extended Control Field is enabled when EXTC = 1. The control fields of all Sand
I frames become two octets in length, instead of one. The numbering for I frames becomes modulo 128, instead of modulo 8. The control field of U frames remains one
byte in length.
06
EXTA
Extended address is enabled when EXTA is a one. The address field of all frames becomes 2 octets in length.
05
DRFCS
Disable Receiver FCS. When DRFCS = 0, the receiver will extract and check the FCS
field at the end of each frame. When DRFCS = 1, the receiver continues to extract
the last 16 or 32 bits of each frame, depending on FCSS, but no check is performed
to determine whether the FCS is correct.
04
DTFCS
Disable Transmitter FCS. When DTFCS = 0, the transmitter will generate and append
the FCS to each frame. When DTFCS = 1, the FCS logic is disabled, and no FCS
is generated with transmitted frames.
Setting DTFCS = 1 is useful in loopback testing for checking the ability of the receiver
to detect an incorrect FCS.
03
4-12
FCSS
FCS Select. When FCSS = 0, a 16 bit FCS is selected otherwise a 32-bit FCS is used.
1-50
02:00
LBACK
Loopback Control puts the MK5025 into one of several loopback configurations.
LBACK
Description
o
Normal operation, No loopback,
Simple loopback, Receive data and clock are driven internally by transmit
data and clock,
Clockless loopback, Receive data is driven internally by transmit data,
Transmit and receive clocks are driven by SYSCLK divided by 8.
Silent loopback, Same as simple loop back with TO pin forced to all ones,
Silent Clockless loopback, Combination of Silent and Clockless loopbacks,
Receive data is driven internally by transmit data, transmit and receive
clocks are driven by SYSCLK divided by 8, TD pin is forced to all ones,
4
5
6
7
4.2.2 Station Addresses
The Local and Remote station addresses may be either one or two octets according to the EXTA control bit described
in the MODE register, If extended address mode is selected bit 0 should be set to a zero for adherence to
ADCCP/HDLC, If extended address mode is not selected, the command and response frame addresses should
be located in the lower order byte of their respective fields,
4,2,3 Timers
There are ten independent counter-timers, The lower 8 bits of IADR+08 are used as a scaler for T1, T3, and TP.
The scaler is driven by a clock which is 1/32 of SYSCLK, N1 is a 16 bit counter and is used to count the number
of bytes in an I-frame, N2 is an 8 bit counter,
The Host will write the period of N1, N2, T1, T2, T3, and TP into the Initialization Block,
1
5
1
4
1
3
1
2
10000
o
IADR + 06
IADR + 08
9
8
7
6
o
0
5
4
o o o o
3 2 1 o
COUNTER N1
COUNTER N2
SCALER
IADR + 10
TIMER T1
IADR + 12
TIMER T3
IADR + 14
TIMER TP
1-51
4·13
DESCRIPTION
N1
MAXIMUM FRAME LENGTH. This field must contain the two's complement of the maximum allowable frame length, in bytes. Any frame received that exceeds this count
will be discarded.
N2
MAXIMUM RETRANSMISSION COUNT. This field must contain the two's complement
of the maximum number of retransmissions that will be made following the expiration
ofn
SCALER
TIMER PRESCALER. Timers n, T3, and TP are scaled by this number. The prescaler
incremented once every 32 system clock pulses. When it reaches zero the timers are
incremented and the prescaler is reset. This field is interpreted as the two's complement of the prescaler period. Note: a prescale value of one gives the smallest amount
of scaling to the timers (64 clock pulses), zero gives the largest (8192 clock pulses).
T1
RETRANSMISSION TIMER. Link control frames will be retransmitted upon the expiration of the n timer if the appropriate response is not received. These frames will
be retransmitted up to N2 (see above) times, at which time the link will be disconnected or reset by MKS025. according to the X.2S protocol. This field must contain the two's
complement of the period of timer T1. The scaled (see SCALER) value of T1 should
be made large enough to allow the remote station to receive the control frame and
send its response.
T3
LINK IDLE TIMER. The link idle timer determines the amount of link idle time necessary to consider the link disconnected. This field must contain the two's complement
of the period of timer T3. T3 is disabled if CSRS RTSEN = 1 or if the MKS02S is in
transparent mode.
TP
TRANSMIT POLLING TIMER. This scaled timer determines the length of time between
transmit frame checks. Unless TDMD (see CSRO) is set or a frame is received on the
link, no attempt to transmit a frame in the transmit descriptor ring is made until TP
expires. At TP expiration all transmit frames in the transmit descriptor ring will be sent.
4.2.4 Receive Descriptor Ring Pointer
IADR
+
IADR
+ 18
4-14
16
1
S
1 1 1
432
o
RLEN
1
o
o
0
0
9
000
876
0
0
RDRA<1S:00>
1-52
0
0
0
000
S
4
3
2
1
0
RDRA<23:16>
o
BIT
NAME
DESCRIPTION
15
0
Reserved, must be written as a zero.
14:12
RLEN
RECEIVE RING LENGTH is the number of entries in the Receive Ring expressed as
a power of two.
RLEN
NUMBER OF
ENTRIES
0
1
2
3
4
5
6
1
2
4
8
16
32
64
128
7
11:08
0
Reserved, must be written as zeroes.
(17:001
15:00
RDRA
RECEIVE DESCRIPTOR RING ADDRESS is the base address of (lowest address) of
the Receive Descriptor Ring. The Receive Ring must be aligned on a word boundary.
4.2.5 Transmit Descriptor Ring Pointer
IADR
+
20
IADR
+
22
1
1
1
1
5
4
3
2
o
TLEN
1
o
o
0
9
0
8
0
0
7 6
TWD
000 000
5 432 1 0
TDRA<23:16>
TDRA<15:00>
o
BIT
NAME
DESCRIPTION
15
o
Reserved, must be writte-n as a zero.
14:12
TLEN
TRANSIT RING LENGTH is the number of entires in the Transmit Ring expressed as
a power of two.
11
o
Reserved, must be written as a zero.
10:08
TWD
TRANSMIT WINDOW is the window size of the Transmitter expressed as a power of
two less one. TWD must be less than TLEN. TWD is the maximum number of I frames
which may be transmitted without an acknowledgement. TWD is not allowed to be greater than 127.
1-53
4-15
07:00/
15:00
TLEN
NUMBER OF
ENTRIES
TWD
0
1
2
3
4
5
6
7
1
2
4
8
16
32
64
128
0
1
2
3
4
5
6
7
WINDOW SIZE
EXTC = 0
EXTC = 1
NA
1
2
3
4
5
6
7
1
3
7
15
31
63
127
127
TRANSMIT DESCRIPTOR RING ADDRESS is the base address of (lowest address)
of the Transmit Descriptor Ring. The Transmit Ring must be aligned on a word boundary.
TDRA
4.2.6 XID/TEST Descriptors
The XIDITEST Descriptors contain pOinters to the buffers used to receive and transmit XID and TEST frames, as
well as the buffer lengths. The exact format of these descriptors can be seen below under Receive and Transmit
Message Descriptor Entry descriptions. They are used the same as other descriptors except that no data chaining
takes place and only the OWNA bit is significant in RMDO and TMDO.
4.2.7 Status Buffer Address
1
5
1
1 1 1
432
o
000
0
0
0
0
0
0
9
6
5
4
3
2
1
8
7
I
IADR
IADR
+
40
0
0
0
0
0
0
0
+ 42
I
0
I
I
I
I
0
0
I
SBA<23:16>
I
I
L
I
I
I
J
I
I
I
I
I
I
I
0
SBA<15:00>
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
BIT
NAME
DESCRIPTION
15:08
o
Reserved, must be written as zeroes.
07:00
15:00
SBA
STATUS BUFFER ADDRESS pOints to a 3 word buffer into which link status information is placed upon the issuance of the STAT primitive by the HOST. The contents of
the Status Buffer are described later in this document. The Status Buffer must begin
on a word boundary.
4-16
1-54
4.2.8 Error Counters
Six locations in the initialization buffer are reserved for use as error counters which the MK5025 will increment.
These are intended for use of the Host CPU for statistical analysis. The MK5025 will only increment the counters;
it is up to the user to clear and preset these counters. The error counters are:
ERROR COUNTER
MEMORY ADDRESS
IADR
+ 44
Bad frames received
- Bad FCS
- Non-Octet Aligned
IADR
+ 46
Number of FRMR frames received
IADR
+ 48
Number of T1 timeouts
IADR
+ 50
Number of REJ frames received
IADR
+ 52
Number of REJ frames transmitted
IADR
+
Frames shorter than minimum length received
54
4.3 Receive and Transmit Descriptor Rings
Each descriptor ring in memory is a 4 word entry. The following is the format of the receive and transmit descriptors.
4.3.1 Receive Message Descriptor Entry
4.3.1.1 Receive Message Descriptor 0 (RMDO)
1 1 1
543
1
2
0
E
L
F
0
W W
N N
A B
S
L
F
U
I
R
1
0
0
0
0
0
0
0
0
0
o
9
8
7
6
5
4
3
2
1
F
R
M
R
R
I
0
0
I
I
I
I
I
0
0
I
RBADR<23:16>
I I I I J I L
NAME
DESCRIPTION
15
OWNA
When this bit is a zero either the HOST or the 1/0 ACCELERATION PROCESSOR
owns this descriptor. When this bit is a one the MK5025 owns this descriptor. The chip
clears the OWNA bit after filling the buffer pointed to by the descriptor entry provided
the received frame had a good FCS, N(r), and N(s). The Host sets the OWNA bit after
emptying the buffer. Once the MK5025, Host, or 1/0 acceleration processor has relinquished ownership of a buffer, it may not change any field in the four words that comprise the descriptor entry.
14
OWNB
This bit determines whether the HOST or the SLAVE PROCESSOR owns the buffer
when OWNA is a zero. The MK5025 never uses this bit. This bit is provided to facilitate use of an 1/0 acceleration processor.
1-55
4-17
13
SLF
Start of Long Frame indicates that this is the first buffer used by MK5025 for this frame.
It is used for data chaining buffers. SLF is set by the chip.
NOTE: A "Long Frame" is any frame which needs data chaining. Usually this will be
an I frame, but it could also be a UI or FRMR frame.
12
ELF
End of Long Frame indicates that this the last buffer used by MK5025 for this frame.
It is used for data chaining buffers. If both SLF and ELF were set the frame would
fit into one buffer and no data chaining would be required. ELF is set by the MK5025.
11
UIR
UI Frame Received indicates that a UI frame has been received and is stored in this
buffer.
10
FRMRR
FRMR Received indicates that the I-field of a FRMR is stored in the buffer referenced
by this Message Descriptor.
09:08
o
Reserved, must be written as zeroes.
07:00
RBADR
The High Order 8 address bits of the buffer pOinted to by this descriptor. This field
is written by the Host and unchanged by MK5025.
4.3.1.2 Receive Message Descriptor 1 (RMD1)
1
5
1 1 1
432
1
o
0
0
9
8
0
7
0
6
000
543
000
2 1 0
BIT
NAME
DESCRIPTION
15:00
RBADR
The low order 16 address bits of the receive buffer pOinted to by this descriptor. RBADR
is written by the Host CPU and unchanged by MK5025. The receive buffers must be
word aligned.
4.3.1.3 Receive Message Descriptor 2 (RMD2)
1 1 1
543
1
2
o
o
0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
IBCNT
: <15:00>
I I I ::
I
::
I
I I I
II
0 I
I
BIT
NAME
DESCRIPTION
15:00
BCNT
Buffer Byte Count is the length of the buffer pOinted to by this descriptor expressed
in two's complement. This field is written to by the Host and unchanged by MK5025_
Buffer size must be even_
4-18
1-56
4.3.1.4 Receive Message Descriptor 3 (RMD3)
1 1 1
543
15:00
1
2
10000
09876
0
5
0
4
0
3
0
2
0
0
0
NAME
DESCRIPTION
MCNT
Message Byte Count is the length, in bytes, of the contents of the buffer expressed
in two's complement. If ELF = 0, MCNT will equal the two's complement of BCNT
since the MK5025 will fill a buffer before chaining to the next descriptor.
4.3.2 Transmit Message Descriptor Entry
4.3.2.1 li"ansmit Message Descriptor 0 (TMDO)
1 1 1
543
1
2
0
E
L
F
w
0
W
N N
A B
S
L
F
100
098
T
U
I
0 0 0
765
0 0 0
432
0
1
0
0
I I I I I I I
0
0
0
TBADR<23:16>
I I I I I I I
BIT
NAME
DESCRIPTION
15
OWNA
14
OWNB
When this bit is a zero either the HOST or the SLAVE PROCESSOR owns this descrip·
tor. When this bit is a one the MK5025 owns this descriptor. The host should set the
OWNA bit after filling the buffer pOinted to by the descriptor entry. The MK5025 releases
the descriptor after transmitting the buffer and receiving the proper acknowledgement
from the remote station. After the MK5025, Host, or 1/0 acceleration processor has
relinquished ownership of a buffer, it may not change any field in the four words that
comprise the descriptor entry.
This bit determines whether the HOST or the 1/0 ACCELERATION PROCESSOR owns
the buffer when OWNA is a zero. The MK5025 never uses this bit. This bit is provided
to facilitate use of an 1/0 acceleration processor.
13
SLF
Start of Long Frame indicates that this is the first buffer used by MK5025 for this frame.
It is used for data chaining buffers. SLF is set by the Host.
NOTE: A "Long Frame" is any frame which needs data chaining. Usually this will be
an I frame, but it could also be a UI frame or others.
12
ELF
End of Long Frame indicates that this the last buffer used by MK5027 for this frame.
It is used for data chaining buffers. If both SLF and ELF were set the frame would
fit into one buffer and no data chaining would be required. ELF is set by the Host.
11
TUI
Transmit a UI frame indicates that a UI frame is to be transmitted from the transmit
buffer instead of a normal I frame. This bit must also be set for anything transmitted
while the MK5025 is in Transparent Mode.
10:08
o
Reserved, must be written as zeroes.
07:00
TBADR
The High Order 8 address bits of the buffer pOinted to by this descriptor. This field
is written by the Host and unchanged by MK5025.
1-57
4-19
4.3.2.2 Transmit Message Descriptor 1 (TMD1)
1
5
1
4
1
3
1
2
0
0
0
0
0
0
000
098
1
0
7
6
5
4
3
2
1
0
BIT
NAME
DESCRIPTION
15:00
TBADR
The Low Order 16 address bits of the buffer pointed to by this descriptor. TBADR is
written by the Host and unchanged by MK5025. The least significant bit is zero since
the descriptor must be word aligned.
4.3.2.3 Transmit Message Descriptor 2 (TMD2)
1
5
1
4
1
3
1
2
1
o
000 0
9 876
0
5
0
4
000
3 2 1
0
0
BIT
NAME
DESCRIPTION
15:00
BCNT
Buffer Byte Count is the usable length, in bytes, of the buffer pointed to by this descriptor
in two's complement. This field is not used by the MK5025.
4.3.2.4 Transmit Message Descriptor 3 (TMD3)
111110000000000
5
432
I : : : : :
0
9
8
7
6
5
432
1
0
~C~T~15:0>: : : : : :
I
BIT
NAME
DESCRIPTION
15:00
MCNT
Message byte count is the length, in bytes, of the contents of the buffer associated
with this descriptor expressed as a two's complement.
4-20
1·58
4.3.3 Status Buffer
1
1
5
432
1
1
o
0
0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
SBA
+ 00
V(r)
V(s)
SBA
+ 02
Local State
Remote State
SBA
+ 04
Phase
V(A)
SBA
+
06
Unused
CURRD<23:16>
SBA
+
08
SBA
+
10
SBA
+
12
CURRD<15:00>
Unused
CURXD <23:16 >
CURXD < 15:00 >
FIELD
DESCRIPTION
V(r)
Current value of the Receive Count Variable. 0 < = V(r) <
trol; 0 < = V(r) < = 127 for extended control.
V(s)
Current value of the Transmit Count Variable. 0 < = V(s) < = 7 for non-extended control; 0 < = V(s) < = 127 for extended control.
Local State
Current state of local station.
Value
Description
o
Normal Data Transfer state
Local Busy state
1
2
REJ sent state
3
DISC sent state
4
Normal Disconnected state
5
SABM/E sent for link connection
6
FRMR sent state
SABM/E sent for link reset
7
1-59
=
7 for non-extended con-
4-21
Remote State
Current state of remote station.
Value
Description
o
Normal Data Transfer state
1
Remote Busy state
Phase
Current phase of operation.
Value
Description
-1
Stopped Mode
o
Information Transfer phase
1
Disconnected phase
2
Resetting phase
3
Transparent Data Transfer phase
VeAl
Current value of Transmit Acknowledge Count.. This field contains the value of the
N(r) of the most recently received S or I frame. The modulo difference between VeAl
and V(s) determines the number of outstanding I frames that have not been acknowledged by the remote station.
CURRD<23:00>
Current Receive Descriptor. This pOinter indicates the position of the descriptor for the
next receive buffer to be filled.
CURRXD<23:00>
Current Transmit Descriptor. This pointer indicates the position of the descriptor for
the next transmit buffer to be transmitted.
4.4 Data Link Services
The MK5025 is consistent with the ISO Data Link Service Definition in providing services to the HOST. The following section is a brief description of this interface.
All link oriented services are provided through the exchange of Data Link Service Primitives. These primitives provide both confirmed and unconfirmed services to the HOST. Each primitive falls into one of the following categories:
1.
Link Establishment (Connection)
2.
Link Resetting
3.
Link Disconnection
4.
Data Transfer
A primitive is also one of the following types:
1.
Request
2.
Response
3.
Indication
4.
Confirmation
4-22
1-60
REMOTE STATION
r -DATA
- LINK
-- T -HIGHER
- -LAYER
-LAYER
I
I
I
I
I
~~1!
I~
I
I
I
I
I
I
~
I
I
I
DISCONNEcT
~
I
I
•
•
I
I
•
I
I
I
I
I
I
I
I
I
_ _ _ ...1 _ _ _ _ _
I
-.J
Example of Confirmed and Unconfirmed Data Link Services
Requests and Responses are issued by the HOST and Indications and Confirmations are issued by the MK5025.
Responses and Confirmations are not used for unconfirmed exchanges. Only the link disconnection service is
unconfirmed.
A Request will be issued by the HOST when a service is required. An Indication will be issued by the MK5025
when the remote system is attempting to change the data link status. A Response is issued by the HOST when
receiving an indication for a confirmed service. A confirmation is issued by the MK5025 when the remote system
has responded to a previously requested service.
In the MK5025, primitives are exchanged two ways: through the CSR1 and through the OWN bits in the descriptor
rings. Connection, disconnection, and link reset primitives are exchanged through CSR1. Data primitives are handled transparently by the OWN bit handshaking in the Descriptor Rings.
Eight additional primitives have been included in the MK5025 to handle services not mentioned in the ISO Data
Link Service definition. These primitives include:
1.
STOP - Disables the MK5025 from link operation.
1-61
4-23
2.
INIT - Instructs the MK5025 to read the initialization block.
3.
START - Enables the MK5025 for link operation.
4.
TRANS - Enables the MK5025 for transparent operation.
5.
ERROR - Indicates the occurence of a link error requiring higher level action.
6.
STAT - Instructs the MK5025 to write chip status in the status buffer.
7.
XID - Confirmed exchange of identification (X.32 mode only).
8.
TEST - Provides a full remote loop back test facility.
For examples of the use of primitives, see the section on detailed programming procedures below.
4.5 Detailed Programming Procedures
4.5.1 Initialization
The following procedures should be followed to initialize the MK5025:
1.
Setup bus control information in CSR4.
2.
Setup Initialization Block and Descriptor Rings and load the address of the initialization block in CSR's 2 and 3.
3.
Issue the INIT primitive through CSR1 instructing the MK5025 to read the initialization block information.
4.
Wait for INIT Confirmation primitive from the MK5025.
5.
Issue the START Primitive through CSR1 to enable the MK5025 for link operation.
6.
Enable interrupts in CSRO if desired.
4.5.2 Active Link Setup
1.
Issue the Connect Request primitive through CSR1. The MK5025 will attempt to establish a logical link.
2.
Wait for a Connect Confirm primitive from the MK5025.
3.
If a Connect Confirm primitive is received, a link has been established.
4.
If a Disconnect Indication primitive is received, the MK5025 has been unable to establish a link. The reason
will be in the PPARM field of CSR1.
4.5.3 Passive Link Setup
The following procedures should be followed to passively establish a link:
1.
Issue a Disconnect Request primitive. A DM frame with F bit clear will be sent to the remote station requesting link setup. This step is optional.
2.
Wait for a Connect Indication primitive from the MK5025.
3.
If a Connect Indication primitive is received, issue a Connect Response primitive to indicate willingness to
establish the link. The link is now established.
4.
If no Connect Indication primitive is received, the remote site is not trying to actively setup a link.
4·24
1·62
4.5.4 Refusing Link Setup
The following procedure should be followed when refusing link establshment:
1.
A Connect Indication will be received indicating a request by the remote station to establish a link.
2.
Issue a Disconnect Request to refuse the link establishment request.
4.5.5 Sending Data
The following procedure should be followed to send a data frame:
1.
Wait for OWNA bit of current transmit descriptor to be cleared, if not already.
2.
Fill buffer associated with current transmit descriptor with data to be sent.
3.
Repeat steps 1 and 2 for next buffer if chaining is necessary. setting SLF and ELF appropriately.
4.
Set the OWNA bit for each descriptor used.
5.
Go on to next descriptor. these OWNA bits will be cleared when the data has been sucessfully sent and
acknowledged.
4.5.6 Receiving Data
The following procedure should be followed when receiving a data frame:
1.
Make sure that the OWNA bit of the current receive descriptor is clear.
2.
Read data out of buffer associated with current receive descriptor.
3.
Set the OWNA bit of current descriptor.
4.
If ELF bit of current descriptor is clear, go on to next descriptor and repeat above steps appending data
from each buffer until a descriptor with the ELF bit set is reached.
4.5.7 Link Disconnection
The following procedure should be followed to disconnect an established link:
1.
Issue the Disconnect Request primitive to the MK5025. The MK5025 will disconnect the link.
4.5.8 Link Reset
The following procedure should be followed to reset an established link:
1.
Issue a Reset Request primitive to the MK5025.
2.
Wait for a Reset Confirm primitive from the MK5025.
3.
If a Reset Confirm primitive is received, the link has been reset.
4.
If a Disconnect Indication is received, the MK5025 was unable to reset and has disconnected. The reason
for failure is in the PPARM field of CSR1. Link connection procedures must now be performed to re-establish
the link.
4.5.9 Receiving Link Reset
The following procedure should be followed when receiving a request for link reset:
1.
A Reset Indication will be received from the MK5025 indicating the remote station has requested a link
resetting.
1-63
4-25
2.
At this time the host may wish to remove any unacknowledged frames in the Transmit Descriptor Ring to
avoid possible duplication at reset.
3.
If able to reset, issue a reset response to indicate willingness to reset the link.
4.
If unable to reset, issue a Disconnect Request to disconnect the link.
4.5.10 Receiving FRMR frame
The following procedure should be followed when receiving a FRMR:
1.
An Error Indication will be received from MK5025 indicating an error condition. PPARM will indicate a FRMR
frame has been received. The I-field of the FRMR has been placed in the next Receive Descriptor.
2.
If able to reset, issue a Reset Request to MK5025 and wait for either a Reset Indication or a Disconnect
Indication as described above for Link Reset.
3.
If unable to reset, issue a Disconnect Request to disconnect the current link. Link setup procedures should
now be performed to re-establish a link.
4.5.11 Exchanging Identification
The following procedure should be followed to exchange identification with the remote:
1.
XIDE in CSR3 must be set prior to any identification exchange.
2.
Place identification information in the XIDITEST Transmit Buffer.
3.
Issue an XID Request primitive.
4.
If an XID Confirm primitive is received, the identication exchange has been performed and the remote response
is located in the XIDITEST receive buffer.
4.
If a Disconnect Indication is received, the identification exchange was unsuccessful.
4.5.12 Receiving an identification request
The following procedure should be performed when receiving a request for identification:
1.
An XID Indication primitive will be received from the MK5025 to indicate the request for identification. The
remote identification information will be located in the XIDITEST receive buffer.
2.
To respond, place identification information in the XIDITEST send buffer and issue an XID Response primitive.
3.
To refuse, issue a Disconnect Request primitive.
Note: An XID Indication will only be issued of the XI DE bit in CSR3 has been set. Otherwise, all identification requests
will automatically be refused and XID frames will not be recognized.
4.5.13 Disabling the MK5025
The following procedure should be followed to disable the MK5025:
1.
4·26
Issue the STOP primitive. This will disable the MK5025 from receiving or transmitting. The TD pin will be
held high while the MK5025 is in stopped mode. The STOP bit in CSRO will be set and interrupts disabled.
If a link is currently established, data may be lost.
1-64
4.5.14 Re-enabling the MK5025
The same procedure should be followed for re-enabling the MK5025 as was used to initialize upon power-up. If
the Initialization Block and the hardware configuration have not changed then steps 1 thru 3 may be omitted.
1-65
4·27
SECTION 5
MK5025 ELECTRICAL SPECIFICATION
ABSOWTE MAXIMUM RATINGS
Temperature Under Bias ....................................................... -25°C to +100°C
Storage Temperature .......................................................... -65°C to +150°C
Voltage on Any Pin with Respect to Ground .................................... -0.5 V to Vcc +0.5 V
Power Dissipation ...................................................................... 0.50 W
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
TA=O°C to 70°C, VCC = +5 V ±5 percent unless otherwise specified.
SYMBOL CONDITIONS
VIL
V IH
MAX
UNITS
-0.5
+0.8
V
+2.0
Vcc +0.5
V
+0.5
V
±10
pA
MIN
VOL
@ IOL = 3.2 mA
VOH
@ IOH = -0.4 mA
IlL
@ Yin = 0.4 to VCC
Icc
T SCT =100ns
TYP
V
+2.4
50
mA
CAPACITANCE
Frequency = 1 MHz
MAX
UNITS
CIN
10
pf
COUT
10
pf
C IO
20
pf
SYMBOL CONDITIONS
MIN
AC TIMING SPECIFICATIONS
TA = O°C to 70°C, VCC = +5 V ±5 percent, unless otherwise specified.
NO. SIGNAL
SYMBOL
TEST
CONDITIONS
PARAMETER
MIN
ns
1
SYSCLK TSCT
SYSCLK period
100
2
SYSCLK TSCL
SYSCLK low time
45
3
SYSCLK TSCH
SYSCLK high time
45
TYP
ns
MAX
ns
4
SYSCLK TSCR
Rise time of SYSCLK
0
8
5
SYSCLK TSCF
Fall time of SYSCLK
0
8
6
TCLK
TTCT
TCLK period
140
7
TCLK
TTCL
TCLK low time
63
TTCH
TCLK high time
63
0
8
0
8
8
TCLK
9
TCLK
TTCR
Rise time of TCLK
10
TCLK
TTCF
Fall time of TCLK
11
TO
TTDP
TO data propagation delay after the
falling edge of TCLK
C L = 50 pF
12
TO
TTDH
TO data hold time after the falling edge
of TCLK
C L = 50 pF
1-66
40
5
5-1
AC TIMING SPECIFICATIONS
TA = O°C to 70°C, VCC = +5 V ±5 percent, unless otherwise specified.
NO. SIGNAL
SYMBOL
PARAMETER
TEST
CONDITIONS
MIN
ns
13
RCLK
T RCT
RCLK period
140
14
RCLK
T RCH
RCLK high time
63
15
RCLK
T RCL
RCLK low time
63
TYP
ns
MAX
ns
16
RCLK
T RCR
Rise time of RCLK
0
8
17
RCLK
T RCF
Fall time of RCLK
0
8
18
RD
TRDR
RD data rise time
0
8
19
RD
TRDF
RD data fall time
0
8
20
RD
TRDH
RD hold time after rising edge of RCLK
5
21
RD
T RDS
RD setup time prior to rising edge of RCLK
30
22
AlDAL
T DOFF
Bus Master driver disable after rising edge
of HOLD
0
50
23
AlDAL
T DON
Bus Master driver enable after falling edge
of HLDA
0
200
24
HLDA
THHA
Delay to falling edge of HLDA from
falling edge of HOLD (Bus Master)
25
RESET
TRW
RESET pulse width
26
AlDAL
TCYCLE
Read/write, address/data cycle time
27
A
T XAS
Address setup time to falling edge of ALE
100
28
A
TXAH
Address hold time after the rising edge of
DAS
50
29
DAL
TAS
Address setup time to the falling edge of
ALE
75
30
DAL
TAH
Address hold time after the falling edge
of ALE
20
31
DAL
T RDAS
Data setup time to the rising edge of DAS
(Bus master read)
55
32
DAL
TRDAH
Data hold time after the rising edge of DAS
(Bus master read)
0
33
DAL
T DDAS
Data setup time to the falling edge of DAS
(Bus master write)
0
34
DAL
T WDS
Data setup time to the rising edge of DAS
(Bus master write)
250
35
DAL
TWDH
Data hold time after the rising edge of
DAS (Bus master write)
36
DAL
TSRDH
Data hold time after the rising edge of DAS TSCT
(Bus slave read)
37
DAL
TSWDH
Data hold time after the rising edge of DAS
(Bus slave write)
0
38
DAL
T SWDS
Data setup time to the falling edge of DAS
(Bus slave write)
0
39
ALE
TALEW
ALE width high
5-2
TSCT
=
100 nS
0
30
TSCT = 100 nS
600
35
=
100 nS
0
110
1-67
35
AC TIMING SPECIFICATIONS
TA = OOC to 7OOC, Vee = +5 V ±5 percent, unless otherwise specified.
TEST
CONDITIONS
MIN
ns
NO. SIGNAL
SYMBOL
PARAMETER
40
ALE
TOALE
Delay from rising edge of DAS to the
rising edge of ALE
41
DAS
Tosw
DAS width low
200
42
DAS
TAOAS
Delay from the falling edge of ALE to the
falling edge of DAS
80
43
DAS
T RIOF
Delay from the rising edge of DALO to
the falling edge of DAS (Bus master read)
35
44
DAS
T ROYS
Delay from the falling edge of READY to
the rising edge of DAS
45
DALI
T ROIF
Delay from the rising edge of DALO to
the falling edge of DALI (Bus master read)
70
46
DALI
T RIS
DALI setup time to the rising edge of
DAS (Bus master read)
150
47
DALI
TRIH
DALI hold time after the rising edge of
DI\S (Bus master read)
0
48
DALI
T RIOF
Delay from the rising edge of DALI to
the falling edge of DALO (Bus master read)
70
49
DALO
Tos
DALO setup time to the falling edge of
ALE (Bus master read)
110
50
DALO
T ROH
DALO hold time after the falling edge of
ALE (Bus master read)
35
51
DALO
TWOSI
Delay from the rising edge of DAS to
the rising edge of DALO (Bus master write)
50
52
CS
TesH
CS hold time after the rising edge of
DAS (Bus slave)
0
53
CS
Tess
CS setup time to the falling edge of
DAS (Bus slave)
0
54
ADR
TSAH
ADR hold time after the rising edge of
DAS (Bus slave)
0
55
ADR
TSAS
ADR setup time to the falling edge of
DAS (Bus slave)
0
56
READY
TARyO
Delay from the falling edge of ALE to the TSCT = 100 nS
falling edge READY to insure a minimum bus cycle time (600 nS)
57
READY· TSROS
58
READY
59
MAX
ns
70
TARYO =300 nS
TSCT=100 nS
120
75
T ROYH
READY hold time after the rising edge
of DAS (Bus master)
0
READY
T SRYH
READY hold time after the rising edge of
DAS (Bus slave)
60
READ
TSRH
READ hold time after the rising edge of
DAS (Bus slave)
0
61
READ
T SRS
READ setup time to the falling edge of
DAS (Bus slave)
0
62
READY
TROYO
Del~y from falling edge of DAS to
falling edge of READY
(Bus slave read)
TSCT = 100 nS
TSCT = 100 nS
200
150
Data setup time to the falling edge of
READY (Bus slave read)
1-68
TYP
ns
0
39
200
5-3
TEST
POINT
R, ;: 1,2K
CR,.CR,
0
CL
1N914 OR EQUIVALENT
=
Figure 5. Output Load Diagram
___I
TO
TIMING MEASUREMENTS ARE MADE AT THE FOLLOWING VOLTAGES,
UNLESS OTHERWISE SPECIFIED:
"1"
OUTPUT
INPUT
FLOAT
2.0 V
2.0 V
10% V OH
"0"
0.8 V
0.8 V
90% VOL
Figure 6. MK5025 Serial Link Timing Diagram
5·4
1-69
50pF min @ 1 MHz
o
100
200
300
400
500
600
I
I
I
I
I
I
I
24
HlDA
A 16·23
ALE
DAl 0·15
-----:::: BUFFEAOBYTECOUNT
~~
~
f---------_
~
PA~KET
----.
•
•
__ r-;;;r;PACKET
N
N
~~------N~------~
NUMBER OF RECEIVE ENTRIES
POINTER TO TRANSMIT RINGS
TRANSMIT DESCRIPTOR RINGS
NUMBER OF TRANSMIT ENTRIES
TRANSMIT BUFFE
v.~
V
~~
PACKET 0
V~
ADORESS OF TRANSMIT BUFFERS 0
~
BUFFER 0 STATUS
~
BUFFER 0 BYTE COUNT
~
::::-::::
~
@§
:
~
--
'
•
••
,
PACKET
.
~A-----N----~_
:
_--j-l---_.......Jr---
v
/:::::::..t.-=--=--:::...~;;-_-_-_-_~
..........
/7
N
N
1·6
1-102
-
OATA
PACKET
N
mabie polarity on the Address Strobe signal eliminates the need for external logic. The LANCE
interfaces with both multiplexed and demultiplexed data buses and features control signals for
address/data bus transceivers.
Interrupts to the microprocessor are generated by the LANCE upon completion of its initialization routine, the reception of a packet, the transmission of a packet, transmitter timeout error,
a missed packet, or a memory error.
The cause of the interrupt is ascertained by reading the control status register (CSRO). Bit (06)
of CSRO, INEA, enables or disables interrupts to the microprocessor. In a polling mode, BIT
(07) of CSRO is sampled to determine when an interrupt causing condition occurred.
LANCE PIN ASSIGNMENT
Figure 7
v•• -
1
48 -
vee
DAL07- 2
47-DAL08
DAL08- 3
48-DAL09
DALOS- 4
45-DAL 10
DAL04- 5
44-DAL 11
DAL03- 8
4 3 - DAL12
DAL02- 7
4Z-DAL 13
DAL01- 8
41-DAL 14
DALOO- 9
40-DAL 15
READ-10
39 - A 18
iiii'i'lf-11
38 - A 17
DALiDA'CO _
12
13
37 - A 18
DAS_14
'Biili/BYTE _
15
35 -A20
iiii1/iiiiSAK6 HOLD/BUSRQ _
38 - A 19
34 -A21
18 -A22
33
17
32 -A23
ALE/AS_ 18
HiJ5i
_19
Cs
_20
31_ RX
30_ RENA
29 _
TX
ADR _21
28_ CLSN
READY_22
2 7 - RCLK
28 _
TENA
RESET _23
Vas -
25_ TCLK
24
1-103
1-7
1.3.5
PIN DESCRIPTION
DALOO-DAL15
(Data/Address Bus)
Input/Output Tri-State. Pins 2-9 and 40-47. The time multiplexed Address/Data bus. During the
address portion of a memory transfer, DAL < 15:00> contains the lower 16 bits of the memory
address. The upper 8 bits of address are contained in A < 23:16 >. During the data portion of
a memory transfer, DAL < 15:00 > contains the read or write data, depending on the type of
transfer. The LANCE drives these lines both as a Bus Master and as a Bus Slave.
READ
Input/Output Tri-State. Pin 10. Read indicates the type of operation the bus controller is performing during a bus transaction. When it is a Bus Master, LANCE drives READ. Read is valid during the entire bus transaction and is tri-stated at all other times.
LANCE as Bus Slave:
High - The chip places data on the DAL lines.
Low - The chip takes data off the DAL lines.
LANCE as Bus Master:
High - The chip takes data off the DAL lines.
Low - The chip places data on the DAL lines.
INTR
(Interrupt)
Output Open Drain. Pin 11. INTERRUPT is an attention interrupt line that indicates that one
or more of the following CSRO status flags is set: BABL, MISS, MERR, RINT, TINT OR IDON.
Interrupt is enabled by CSRO < 6 >, INEA = 1.
i5A[j
(Data/Address Line In)
Output Tri-State. Pin 12. DAL IN is an external bus transceiver control line. LANCE drives 5A[j
only while it is the Bus Master. When LANCE reads the DAL lines during the data portion of
a READ transfer, DALI is asserted. i5AiJ is not asserted during a WRITE transfer.
i5ACO
(Data/Address Line Out)
Output Tri-Staie. Pin 13. DAL OUT is an external bus transceiver control line. LANCE drives 5A[(5
only when it is a Bus Master. When LANCE drives the DAL lines during the address portion
of a READ transfer or for the duration of a WRITE transfer, i5ALO is asserted.
DAS
(Data/Strobe)
Input/Output Tri-State. Pin 14. Data Strobe defines the data portion of the bus transaction. By
definition, data is stable and valid at the low to high transition of iSAS. When it is the Bus Master,
LANCE drives this signal. At all other times, the signal is tri-stated.
BMO, BM1 or BYTE, BUSAKO
(Byte Mask)
Output' Tri-State. Pins 15 and 16 are programmable through CSR3.
CSR3<00> BCON = 0
PIN 15 = BMO (Output Tri-State)
PIN 16 = BM1 (Output Tri-State)
Byte Mask < 1:0> Indicates the byte(s) on the DAL to be read or written during this bus
transaction. LANCE drives these lines only as a Bus Master. LANCE ignores the BM lines when
it is a Bus Slave and assumes word transfers. Byte selection follows:
BM1
LOW
LOW
HIGH
HIGH
1-8
Whole Word
Byte < DAL 15:08 >
Byte < DAL 07:00 >
None
LOW
HIGH
LOW
HIGH
1-104
CSR3<00> BCON = 1
PIN 15 = BYTE (Output Tri-State)
PIN 16 = BUSAKO (Output)
Byte selection occurs by using the BYTE line and DAL <00> latched during the address portion of the bus transaction. LANCE drives BYTE only as a Bus Master and ignores it when
operating as a Bus Slave. Byte selection occurs as follows:
BYTE
DAL
(During Address Portion)
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
WHOLE WORD
ILLEGAL CONDITION
LOWER BYTE
UPPER BYTE
BUSAKO is a bus request daisy chain output. If LANCE is not requesting the bus and it receives
HLDA, BUSAKO is driven low. If LANCE is requesting the bus when it receives HLDA, BUSAKO
remains high.
HOLD/BUSRQ
(Bus Hold Request)
Input/Output Open Drain. Pin 17. This pin is programmable through CSR3.
CSR3<00> BCON = 0
PIN 17 = HOLD
LANCE asserts the HOLD request when it requires a DMA cycle regardless of the HOLD pin
state. HOLD is held LOW for the entire bus transaction.
CSR3<00> BCON = 1
PIN 17 = BUSRQ
LANCE asserts BUSRQ when it requires a DMA cycle if the prior state of the BUSRQ pin
was high. BUSRQ is held low for the entire bus transaction.
ALE/AS
(Address Latch Enable)
Output Tri-State. Pin 18. The active level of Address Strobe is programmable through CSR3.
The address portion of a bus transfer occurs while this signal is at its asserted level. LANCE
drives this signal while it is the Bus Master. At all other times, the signal is tri-stated.
CSR3<01> ACON = 0
PIN 18 = ALE
Address Latch Enable is used to demultiplex the DAL lines and define the address portion of
the transfer. As ALE, the signal transitions from high to low during the address portion of the
transfer and remains low during the data portion. A slave device can use ALE to control a latch
on the bus address lines. When ALE is high, the latch should be open and when ALE goes
low, the latch should be closed.
CSR3<01> ACON = 1
PIN 18 = AS
As AS, the signal pulses low during the address portion of the bus transfer. The low to high
transition of AS can be used by a slave device to strobe the address into a register.
HLDA
(Hold Acknowledge)
Input. Pin 19. Hold Acknowledge is the response to HOLD. When HLDA is low in response to
LANCE's assertion of HOLD, the LANCE is the Bus Master. HLDA should be deasserted after
LANCE releases HOLD.
1-105
1-9
CS
(Chip Select)
Input. Pin 20. When low, CS indicates LANCE is the slave device for the data transfer. CS must
be valid throughout the data portion of the transaction.
ADR
(Register Address Port Select)
Input. Pin 21. Address selects the Register Address Port or the Register Data Port. It must be
valid throughout the data portion of the transfer and the chip only uses it when CS is low.
ADR
PORT
LOW
HIGH
Register Data Port
Register Address Port
READY
Input/Output Open Drain. Pin 22. When LANCE is a Bus Master, READY is an asynchronous
acknowledgement from the bus memory that memory will accept data in a WRITE cycle or that
memory has put data on the DAL lines in a READ cycle. As a Bus Slave, LANCE asserts READY
when it has put data on the DAL lines during a READ cycle or is about to take data off the DAL
lines during a WRITE cycle. READY is a response to DAS and is negated after DAS is negated.
CS and DAS must remain asserted until READY is asserted or READY will not be asserted.
RESET
(Bus Reset Signal.)
Input. Pin 23. Causes LANCE to cease operation, clear its internal logic and enter an idle state
with the STOP bit of CSRO set.
TLCK
(Transmit Clock)
Input. Pin 25. A crystal-controlled 10 MHz clock. This clock is the primary LANCE clock as well
as the Transmit clock. (A 0.01 % clock as specified in the Ethernet Specification.)
TENA
(Transmit Enable)
Output. Pin 26. A high level signal asserted w:th the transmit output serial bit stream, TX, to
enable the external transmit logic.
RCLK
(Receive Clock)
Input. Pin 27. The 10 MHz clock that is synchronous with the received data and is used for transferring the received data into the LANCE.
CLSN
Collision)
Input. Pin 28. A logical input that indicates, when high, that a collision is occurring on the channel.
TX
(Transmit)
Output. Pin 29. Transmit Output Bit Stream.
RENA
(Receive Enable)
Input. Pin 30. A logical input that indicates, when high, the presence of data on the channeL
RX
(Receive)
Input. Pin 31. The input for the serial receive data. The data is synchronous with the receive clock.
1-10
1-106
A16-A23
(High-Order Address Bus)
Output, Three State pins 32 thru 39. Address bits <23:16> used in conjunction with DAL
< 15:00 > to produce a 24-bit address. LANCE drives these lines only as a Bus Master.
Vcc
Power supply pin 48. +5 VDC ±5%. It is recommended that a power supply filter be used between Vee (Pin 48) and Vss (Pins 1 and 24). This filter should consist of two capacitors in parallel
having the values of 1O",F and .047",F respectively.
Vss
Ground pins 1 and 24. 0 VDC
1.3.6
LANCE INTERFACE DESCRIPTION--BUS MASTER MODE
All data transfers from the LANCE in the Bus Master mode are timed by ALE, DAS, and READY.
The automatic adjustment of the LANCE cycle by the READY Signal allows synchronization with
variable cycle time memory due either to memory refresh or to dual port access. Bus cycles
are a minimum of 600 nsec in length and can be increased in 100 nsec increments. Figure 8
and Figure 9 show generalized interfaces to both multiplexed and demultiplexed bus
microprocessors, and Figure 10, the Bus Master Timing modes.
MULTIPLEXED BUS INTERFACE
Figure 8
A <23:16>
TO
SIA
~----------~~ADR
LANCE
A16· A23
DATA AND ADDRESS CONTROL
ADDRESS BITS 16·23 SIGNALS
BITS 0·15
---,v,-----'
MICROPROCESSOR BUS
1-107
1-11
DEMULT!!l'tEXED BUS INTERFACE
Figure 9
DATA BITS CONTROL ADDRESS BITS
0-15
SIGNALS
0-23
""
~
'"
;::..
./':,.
'--
I---
~
I---
"\
1
r-~
A O. 15
L
A
T
C
'I
~
DAL <15:00>
'I
H
ALE
'---
A
A <23:16>
A'6_23
SIA
BUS
.1
\
"
TO
SIA
V
'I
AO
AOR
r.J\
A O_23
LANCE
0
E
C
CS
0
V
0
E
T
5AS
....
?
...
7
------~v~------~
MICROPROCESSOR BUS
1.3.6.1
READ SEQUENCE
At the beginning of a read cycle, valid addresses are placed on DAL < 15:00 > and
A < 23:16 >. The BYTE Mask signals (BMO and i3"M1) become valid at the beginning
of this cycle as does READ, indicating the type of cycle. The trailing edge of ALE
or AS is used to strobe in the addresses A < 15:00> into the external latches. Approximately a hundred nanoseconds later, DAL < 15:00> go into a tristate mode. There
is a fifty nanosecond delay to allow for transceiver turnaround, then BAS falls low
to signal the beginning of the data portion of the cycle. At this point in the cycle, the
LANCE waits for the memory device to assert READY. Upon assertion of READY,
DAS makes a transition from a zero to a one, latching memory data. (DAS) is low
for a minimum of 200 nsec).
The bus transceiver controls, DALI and DALO, are used to control the bus transceivers.
The DALI signal is used to strobe data toward the LANCE and the DALO signal is
used to strobe data or addresses away from the LANCE. During a read cycle, DALO
goes inactive before DALI goes active to avoid the "spiking" of the bus transceivers.
1-12
1-108
BUS MASTER TIMING
Figure 10
..
I
A16-A21 READ
iiMD, BM1
TCYCLE
50
I
'00
I
'50
I
200
I
250
I
300
I
350
I
400
I
450
I
500
I
550
I
600
I
X__________________________x
DAL <15:00>
(READ)
ADDRESS
DAL <15:00>
(WRITE)
ADDRESS
- - - - --- - - ________
J
DATA TO MEMORY
---"'"
ALE
(DOTTED)
AS
DAS
REAi:iY
DALO (READ)
DAD
DAi:O
(READ)
(WRITE)
"'"
i5ALi (WRITE)
'---___--J/
"
,,~-------/
"~------------------------~/
1,3.6.2
WRITE SEQUENCE
The write cycle begins exactly like a read cycle with the READ line remaining inactive. After ALE or AS pulse, the DAL < 15:00> change from addresses to data. DAS
goes active when the DAL < 15:00> lines are stable. This data will remain valid on
the bus until the memory device asserts READY. At this pOint, DAS goes inactive
latching data into the memory device. Data is held for 75 nanoseconds after the
deassertion of DAS.
1.3.7
LANCE INTERFACE DESCRIPTION··BUS SLAVE MODE
The LANCE enters the Bus Slave Mode whenever CS becomes active. This mode must be
entered whenever writing or reading the four status control registers (CSRO, CSR1, CSR2, and
CSR3) and the register address painter (RAP). RAP and CSRO may be read or written to at
any time, but the LANCE must be stopped for CSR1, CSR2, and CSR3 to be written to or read.
1.3.7.1
READ SEQUENCE
CS, READ, and DAS are asserted at the beginning of a read cycle. ADR also must
be valid at this time. (If ADR is a "1", the contents of RAP are placed on the DAL
lines. Otherwise the contents of the CSR register addressed by RAP are placed on
the DAL line~fter the data on the DAL lines become valid, LANCE asserts READY.
CS, READ, DAS, and ADR must remain stable throughout the read cycle. Refer to
Figure l1.
1·109
1-13
BUS SLAVE READ TIMING FOR CSRO, RAP, AND CSR3
Figure 11
.....f - - - - - - - - T C Y C L E - - - - - - - - - - - - - i..
~
I
DAS
50
~~
I
100
I
150
I
200
I
250
I
300
I
350
I
400
I
450
I
500
I
_______________'
~ ~~----------------------~
READ
---.J
DAL _______~F~LO~AT~_~(================)--~~~
\1.-_---1
AD"
==x~
_____________
--...J ' - -_ _ __
Timing for CSR1 and CSR2 8,.. similar but the DELAY to
becomes 1260 Instead of 360 ~.
1.3.7.2
fiEAi5Y
WRITE SEQUENCE
This cycle is similar to the read cycle, except that during this cycle, READ is not
asserted. The DAL buffers are tristated which configures these lines as inputs. The
assertion of REAi5Y by LANCE indicates to the memory device that the data on the
DAL lines has been stored by LANCE in its appropriate CSR register. CS, READ, DAS,
ADR, and DAL < 15:00 > must remain stable throughout the write cycle. Refer to
Figure 12.
BUS SLAVE WRITE TIMING FOR CSRO, RAP, AND CSR3
Figure 12
.....f - - - - - - - - T C y C L E _ _ _ _ _ _ _ _ _ _ _ _
..
I
50
I
100
I
160
I
200
I
260
I
300
I
350
I
400
I
450
I
600
I
1
DAs~
READ ~'-________________________--'I
AD"
==x___________ ____
~x
DAL ---.!
------'-___________________J ..) - FLOAT
---
\1.-_---11
Timing tor CSR1 and CSR 2 are similar but the DELAY to iiEA6Y
become. 1250 instead of 360 1-'1.
1-14
1·110
1.3.7.3
REFERENCE DOCUMENTS
The following documents provide a good overview and background for Ethernet. They
can be requested from:
Ethernet
Xerox Office Systems Division
Dept. A
3333 Coyote Hills Rd.
Palo Alto, CA 94304
1. The Ethernet, a Local Area Network, Data Link Layer and Physical Layer
Specifications··Version 2.0, November 1982.
2. John F. Shoch, An Annotated Bibliography on Local Computer Networks,
October 1979.
3. The Ethernet Local Network: Three Reports, February 1980.
4. Internet Transport Protocols, Xerox System Integration Standard, December 1981.
5. Courier: The Remote Procedure Call Protocol, Xerox System Integration Standard,
December 1981.
1·111
1·15
1-16
1-112
CHAPTER 2
PROGRAMMING SPECIFICATIONS
2.0
INTRODUCTION
2.1
PROGRAMMING SPECIFICATIONS
This section defines the Control and Status Registers and the memory data structures required to program the LANCE Ethernet Protocol Controller.
2.2
PROGRAMMING THE LANCE
The LANCE is designed to operate in an environment that includes close coupling with a local memory
and a microprocessor (HOST). The LANCE is programmed by a combination of registers and data structures resident within the LANCE and in memory. There are four Control and Status Registers (CSR's)
within the LANCE which are programmed by the HOST device. Once enabled, the LANCE has the ability to access external buffer memory locations to acquire additional operating parameters. LANCE has
the ability to do independent buffer management as well as transfer data packets to and from an Ethernet.
There are three memory structures accessed by LANCE, as follows:
1. Initialization Block - 12 words in contiguous memory starting on a word boundary. The initialization
block is assembled by the HOST, and is accessed r. LANCE. The initialization block contains the
operating parameters necessary for device operation. I ne initialization block is comprised of:
1.
2.
3.
4.
5.
Mode of Operation (1 Word)
Physical Address (3 Words)
Logical Address Mask (4 Words)
Location of Receive and Transmit Descriptor Rings (2 Words)
Number of Entries in Receive and Transmit Descriptor Rings (2 Words)
2. Receive and Transmit Descriptor Rings - Two ring structures, one each for incoming and outgoing
packets. Each entry in the rings is 4 words long. Each entry must start on a quadword boundary. The
Descriptor Rings are comprised of:
1. The address of a data buffer.
2. The length of that buffer.
3. Status information associated with the buffer.
3. Data Buffers - Contiguous portions of memory reserved for packet buffering. Data buffers may begin
on arbitrary byte boundaries.
In general, the programming sequence of LANCE may be summarized as:
1. Programming the LANCE CSR's by a HOST device to locate an initialization block in memory.
2. LANCE loading itself with the information contained within the initialization block.
3. LANCE accessing the Descriptor Rings for packet handling.
2.3
CONTROL AND STATUS REGISTERS
There are four Control and Status Registers (CSR's) resident within LANCE. The CSR's are accessed
through two bus addressable ports, an address port (RAP), and a data port (RDP).
2.3.1
ACCESSING THE CONTROL AND STATUS REGISTERS
The CSR's are read (or written) in a two step operation. The address of the CSR is written into
1-113
.
2·1
the address port (RAP) during a bus slave transaction. During a subsequent bus slave transaction, the data being read from (or written into) the data port (RDP) is read from (or written into)
the CSR selected in the RAP. Once written, the address in RAP remains unchanged until rewritten. A discrete control input pin (ADR) is provided to distinguish the address port from the data
port.
Pin
ADR
Port
L
REGISTER DATA PORT (RDP)
REGISTER ADDRESS PORT (RAP)
H
2.3.1.1
REGISTER DATA PORT (RDP)
1111
5 4 3 2
10000000000
0 9 8 7 6 5 432 1 0
I:::::
~~R ~~T~
: : : : :
I
CSR DATA
Bits 15:00
Writing data to the RDP loads data into the CSR selected by RAP. Reading the data
from RDP reads the data from the CSR selected by RAP. CSR1, CSR2 and CSR3
are accessible only when the STOP bit of CSRO is set. If an attempt to access CSR1,
CSR2, or CSR3 is made without the STOP bit being set, LANCE does not respond
to the bus transfer. LANCE will assert READY, but no data will be transferred either into or out of these registers.
2.3.1.2
REGISTER ADDRESS PORT (RAP)
111 1 1 1 000 0 0 000 0 0
5 432 1 0 9 8 7 6 5 432 1 0
RES
Bits 15:02
Reserved and read as zeros.
CSR
Bits 01:00
CSR address select bits. READ/WRITE. Selects the CSR to be accessed through
the RDP. RAP is cleared by Bus RESET.
CSR<1:0>
CSR
o
CSRO
CSR1
CSR2
CSR3
1
2
3
2·2
1-114
2.3.2
CONTROL AND STATUS REGISTER DEFINITION
2.3.2.1
CONTROL AND STATUS REGISTER 0 (CSRO)
RAP = 0
1
10000000000
5 4 3 2
0 9 8 7 6 5 432 1 0
1
E B CM
R A E I
R B R S
l R S
MR
E I
R N
R T
T I
10
NO
T N
I
N
T
R
I R T T S S I
N XX o T TN
E 00 MO R I
AN NO PTT
ERR
Bit 15
(Error Summary) Error Summary is set by the 'OR' of BABl, CERR, MISS and MERR.
ERR remains set as long as any of the error flags are true. ERR is read only, writing
it has no effect. It is cleared by RESET or by setting the stop bit.
BABl
Bit 14
(Babble) BABl is a transmitter timeout error. It indicates that the transmitter has been
on longer than the time required to send the maximum length packet. BABl will be
set if the number of bytes transmitted exceeds 1518. When BABl is set, an interrupt
will be generated if INEA = 1. BABl is READ/CLEAR ONLY and is set by lANCE
and cleared by writing a "1" into the bit. Writing a "0" has no effect. RESET or set·
ti ng the STOP bit clears it.
CERR
Bit 13
(Collision Error)
Collision Error indicates that the collision input to the chip failed to activate within
2 usec after a chip-initiated transmission was completed. Collision after transmission
is a transceiver test feature. CERR is READ/CLEAR ONLY. The chip sets it and clears
it by writing a "1" into the bit. Writing a "0" has no effect. 'RES'ET or setting the STOP
bit clears it.
MISS
Bit 12
(Missed Packet) Missed Packet is set whenever a packet arrives and passes address
recognition, but is lost because the receiver does not own a receive buffer. When
MISS is set, an interrupt will be generated if INEA = 1. MISS is READ/CLEAR ONLY
and is set by lANCE and cleared by writing a "1" into the bit. Writing a "0" has no
effect. RESET or setting the STOP bit clears it.
MERR
Bit 11
(Memory Error) Memory Error sets when lANCE is the Bus Master and has not
received READY within 25.6 !,sec after asserting the address on the DAl lines. When
a Memory Error is detected, the receiver and transmitter are turned off and an interrupt
is generated if INEA = 1. MERR is READ/CLEAR ONLY and is set by the chip and
cleared by writing a "1" into the bit. Writing a "0" has no effect. RESET or setting
the STOP bit clears it.
1-115
2·3
RINT
Bit 10
(Receiver Interrupt) Receiver Interrupt is set after LANCE updates the last entry in
the Receive Descriptor Ring for the completed packet. When RINT is set, an interrupt is generated if INEA = 1. RINT is READ/CLEAR ONLY and is set by LANCE
and cleared by writing a "1" into the bit. Writing a "0" has no effect. RESET or setting the STOP bit clears it.
TINT
Bit 09
(Transmitter Interrupt) Transmitter Interrupt is set after LANCE updates the last entry
in the Transmit Descriptor Ring for that completed packet. When TINT is set, an interrupt is generated if INEA = 1. TINT is READ/CLEAR ONLY and is set by LANCE
and cleared by writing a "1" into the bit. Writing a "0" has no effect. RESET or setting the STOP bit clears it.
lOON
Bit 08
(Initialization Done) Initialization Done indicates that LANCE has completed the initialization procedure started by setting the INIT bit. When IDON is set, the chip has
read the Initialization Block from memory and stored the new parameters. When IDON
is set, an interrupt is generated if INEA = 1. IDON is READ/CLEAR ONLY and is
set by LANCE and cleared by writing a "1" into the bit. Writing a "0" has no effect.
RESET or setting the STOP bit clears it.
INTR
Bit 07
(Interrupt Flag) Interrupt Flag indicates that one or more of the following interrupt causing conditions has occurred: BABL, MISS, MERR, RINT, TINT, IDON. If INEA = 1
and INTR = 1 the INTR output pin will be low. INTR is READ ONLY, writing this bit
has no effect. INTR is cleared by RESET or by setting the STOP bit.
INEA
Bit 06
(Interrupt Enable) Interrupt Enable allows the INTR Output pin to be driven low when
the Interrupt Flag is set. If INEA = 1 and INTR = 1 the INTR pin will be low. If
INEA = 1 and INTR = 1 the INTR pin will be low. If INEA = 0 the INTR pin will be
high, regardless of the state of the Interrupt Flag. INEA is READIWRITE set by writing
a "1" into this bit and is cleared by writing a "0" into this bit or by RESEi' or by setting the STOP bit.
RXON
Bit 05
(Receiver On) Receiver On indicates that the receiver is enabled. RXON and IDON
are set at the same time, if the DRX bit in the Mode Register is a "0". RXON is cleared
by MERR or STOP being set or by RESET. RXON is READ ONLY, writing this bit has
no effect. RXON is gated by the STRT bit; thus it will always be read as a "0" until
STRT is set.
TXON
Bit 04
(Transmitter On) Transmitter On indicates that the transmitter is enabled. TXON and
IDON are set at the same time, if the DTX bit in the Mode Register is "0". TXON
is cleared by MERR, or STOP being set, a TRANSMIT UNDERFLOW, or by RESET.
TXON is READ ONLY; writing this bit has no effect. TXON is gated by the STRT bit;
thus it will always be read as a "0" until STRT is set.
TDMD
Bit 03
(Transmit Demand) When set, Transmit Demand causes LANCE to access the Transmit
2-4
1-116
Descriptor Ring without waiting for the polltime interval to elapse. (about 1.6 ms). TDMD
need not be set to transmit a packet, it merely hastens LANCE's response to a Transmit
Descriptor Ring entry insertion by the host. TDMD is WRITE WITH ONE ONLY l!nd
microcode clears it after it is used. It may read as a "1" for a short time after it is
written because the LANCE microcode may have been busy when TDMD was set.
It is also cleared by RESET or by setting the STOP bit. Writing a "0" in this bit has
no effect.
STOP
Bit 02
(Stop) STOP disables LANCE from all external activity when set and clears the internal logic. Setting STOP is the equivalent of asserting Bus RESET. LANCE remains
inactive and STOP remains set until the STRT or INIT bit is set. If STRT, INIT and
STOP are all set together, STOP will override the other bits and only SlOP will be
set. STOP IS READIWRITE WITH ONE ONLY and set by ~ Writing a "0" to
this bit has no effect.
STRT
Bit 01
(Start) Start enables LANCE to send and receive packets, perform direct memory
access and do buffer management. If STRT and INIT are set together, the INIT function will be executed first. STRT is READIWRITE WITH ONE ONLY. Writing a "0"
into this bit has no effect. STRT is cleared by RESET or by setting the STOP bit.
INIT
Bit 00
(Initialize) When set, Initialize causes LANCE to begin the initialization procedure and
access the Initialization Block. If STRT and INIT are set together, the INIT function
is executed first. INIT is READIWRITE WITH "1" ONLY. Writing a "0" into this bit
has no effect. INIT is cleared by RESET or by setting the STOP bit.
2.3.2.2
CONTROL AND STATUS REGISTER 1 (CSR1)
RAP
=1
READIWRITE: Accessible only when the STOP bit of CSRO is a ONE. Access at any
other time will not be responded to by LANCE. READY will be asserted
but no data will be transferred. CSR1 is unaffected by RESET.
1 1 1 1 1 1 0 0 0 000 0 0 0 0
5 4 3 2 1 098 765 4 3 2 1 0
IADR
Bits 15:01
The low order 16 bits of the address of the first word (lowest address) in the Initialization Block. Bit 00 must be zero.
2.3.2.3
CONTROL AND STATUS REGISTER 2 (CSR2)
RAP = 2
READIWRITE: Accessible only when the STOP bit of CSRO is a ONE. Access at any
other time will not be responded to by LANCE. READY will be asserted
but no data will be transferred. CSR2 is unaffected by RESET.
1-117
2-5
111110000000000
5 4 3 2
0 9 876 5 4 3 2 1 0
RES
Bits 15:08
Reserved.
IADR
Bits 07:00
The high order 8 bits of the address of the first word (lowest address in the Initialization Block.
2.3.2.4
CONTROL AND STATUS REGISTER 3 (CSR3)
CSR3 allows redefinition of the Bus Master interface.
RAP = 3
READIWRITE: Accessible only when the STOP bit of CSRO is a ONE. Access at any
other time will not be responded to by LANCE. READY will be asserted
but no data will be transferred. CSR3 is cleared by RESET or by setting the STOP bit in CSRO.
1 1 111 1 0 0 0 0 0 0 0 000
5 4 3 2 1 0 9 8 7 6 5 432 1 0
B A B
SCC
WOO
P N N
RES
Bits 15:03
Reserved/read as "0".
BSWP
Bit 02
(Byte Swap) Byte Swap allows LANCE to operate with memory organizations that
have bits < 07:00 > at even addresses with bits < 15:08 > at odd addresses or vice
versa.
With Byte Swap = 0:
Address
XXI
Address
1L--15.L...1_ _----'1---'81
This memory organization is used with the LSI 11 microprocessor and the 8086
microprocessor.
2-6
1·118
With Byte Swap
=
1:
Address
Address
XXO
L-115-,----1_ _
---'I-----'SI
,-----I
7-,---1_ _-----'1'--'0I
XX1
This memory organization is used with the MK6S000, MK6S200, and ZSOOO
microprocessors. Only data from SILO transfers are swapped. Initialization Block Data
and Ring Descriptor entries are not swapped. BSWP is READIWRITE and cleared
by RESET or by setting the STOP bit in CSRO.
ACON
Bit 01
(ALE Control) ALE Control defines the assertive state of ALEIAS when LANCE is
a Bus Master. ACON is READIWRITE and cleared by RESET or by setting the STOP
bit in CSRO.
ACON
o
1
ALEIAS
ASSERTED HIGH (ALE)
ASSERTED LOW ()is)
BCON
Bit 00
(Byte Control) Byte Control redefines the Byte Mask and Hold 1/0 Pins. BCON is
READIWRITE and cleared by RESET or by setting the STOP bit in CSRO.
1/0 PIN 16
1/0 PIN 15
1/0 PIN 17
o
BiVi1
1
BUSAKO
BMO
BYTE
HOLD
BUSRQ
BCON
2.4 INITIALIZATION
2.4.1
INITIALIZATION BLOCK
LANCE initialization includes the reading of the initialization block in memory to obtain the
operating parameters. The following is a definition of the Initialization Block. The Initialization
Block is read by LANCE when the INIT bit in CSRO is set. The INIT bit should be set before
or concurrent with the STRT bit to ensure proper parameter initialization and LANCE operation. After LANCE has read the Initialization Block, IDON is set in CSRO and an interrupt is
generated if INEA = 1.
1-119
2-7
HIGHER ADDRESSES
TLEN - TDRA <23:16>
IADR <23:00> +16
TDRA <15:00>
IADR <23:00> +14
RLEN - RDRA <23:16>
IADR <23:00> +12
RDRA < 15:00 >
IADR <23:00> +10
LADRF < 63:48 >
IADR <23:00> +E
LADRF <47:32>
IADR <23:00> +C
LADRF <31:16>
IADR <23:00> +A
LADRF < 15:00 >
IADR <23:00> +8
PADR <47:32>
IADR <23:00> +06
PADR <31:16>
IADR <23:00> +04
PADR <15:00>
IADR <23:00> +02
MODE
IADR <23:00> +00
BASE ADDRESS
OF BLOCK
2.4.1.1
MODE
The Mode Register allows alteration of LANCE's operating parameters. Normal operation is with the Mode Register clear.
1111
5 4 3 2
P
R
a
M
IADR <23:00> +00
10000000000
0 9 8 7 6 5 4 321 0
I I I I I I I
RES
I I I I I I I
I
N
T
L
D
R
T
Y
CD
aT
L C
L R
L D D
OTR
OXX
P
PROM
Bit 15
(Promiscuous Mode) When PROM = 1, all incoming addresses are accepted. This.
bit must be set in internal loopback if a physical address is not used.
RES
Bits 14:07
(Reserved)
2-8
1-120
INTL
Bit 06
(Internal Loopback) Internal loopback is used with the lOOP bit to determine where
the loopback is to be done. Internal loopback allows lANCE to receive its own
transmitted packet. Since this represents full duplex operation, the packet size would
be limited by the SilO size, which is 48 bytes. However, a SilO full flag is generated
after 32 bytes are loaded into the SILO. This limits the transmit buffer size to 32 bytes
in internal or extended loop back. With transmit CRC enabled, the LANCE generates
the 4-byte CRC code and appends it to the data. Thus, the receive buffer is filled
with 36 bytes and the host CPU checks the CRC result. With transmit CRC disabled,
the host CPU provides 4 bytes of CRC as part of the 32 bytes in the transmit buffer.
The LANCE checks the CRG on reception and transfers only 28 bytes of "data" to
the receive buffer. After each Internal loopback packet, lANCE should be
reinitialized.
INTl is only valid if lOOP = 1, otherwise it is ignored.
lOOP
INTL
o
X
o
1
lOOPBACK
NO lOOPBACK, NORMAL OPERATION
EXTERNAL
INTERNAL
ORTY
Bit 05
(Disable Retry) When DRTY = 1, LANGE attempts only one packet transmission
If there is a collision on the first transmission attempt, a Retry Error (RTRY) is reported
in Transmit Message Descriptor 3 (TMD3).
COLL
Bit 04
(Force Collision) This bit allows the collision logic to be tested. lANCE must be in
internalloopback mode for COLl to be valid. If COll = 1, a collision will be forced
during the subsequent transmission attempt. This will result in 1 or 16 total transmission attempts with a retry error reported in TMD3. The number of attempts depends
upon the state of DRTY (Bit (05).
OTCR
Bit 03
(Disable Transmit CRG) When DTCR = 0, the transmitter generates and appends
a CRC to the transmitted packet. When DTCR = 1, the CRC logic is allocated to the
receiver and no CRC is generated and sent with the transmitted packet. During loopback, DTCR = 0 causes a CRC to be generated on the transmitted packet but the
receiver will not perform a CRC check since the CRC logic is shared and cannot
generate and check CRG at the same time. The generated CRC is written into memory
with the data and can be checked by the host software. If DTCR = 1 during loopback
the host software must append a CRC value to the transmit data. The receiver checks
the CRG on the received data and reports any errors.
LOOP
Bit 02
(loopback) loopback allows LANCE to operate in full duplex mode for test purposes.
The maximum packet size is limited to 36 bytes as described above for the INTl bit.
During loopback, the runt packet filter is disabled because the maximum packet is
forced to be smaller than the minimum size Ethernet packet (64 bytes). lOOP = 1
allows simultaneous transmission and reception for a message constrained to fit within
the SILO. The chip waits until the entire message is in the SilO before serial transmission begins. The incoming data stream fills th" SILO from behind as it is being emptied. Moving the received message out of the SilO to memory does not begin until
reception has ceased. In loopback mode, transmit data chaining is not possible.
Receive data chaining is allowed regardless of the receive buffer length. In normal
operation, the receive buffers must be 64 bytes long, to allow time for buffer lookahead.
1-121
2-9
DTX
Bit 01
(Disable the Transmitter) Disable the Transmitter causes LANCE not to access the
Transmit Descriptor Ring and therefore no transmissions are attempted. DTX disables
TXON from being set when initialization is complete.
DRX
Bit 00
(Disable the Receiver) Disable the Receiver causes LANCE to reject all incoming
packets and not access the Receive Descriptor Ring. DRX disables RXON from being set when initialization is complete.
2.4.1.2
PHYSICAL ADDRESS
1
1 1
5 4 3 2
1 000 0 0 0 0 000
098 765 4 321 0
IADR <23:00> +06
IADR <23:00> +04
IADR <23:00> +02
PADR
Bits 47:00
(Physical Address) Physical Address is the unique 48-bit physical address assigned
to LANCE. PADR < 0 > must be zero.
2.4.1.3
LOGICAL ADDRESS FILTER
The Logical Address Filter is a 64 bit mask composed of four sixteen bit registers
LADRF < 63:00 > in the initialization block that is used to accept incoming Logical
Addresses. This is an imperfect filter that requires the host processor to do the final
filtering. The first bit of the incoming address must be a "1" for either the Logical
Address Filter or the Broadcast Address decode to be enabled. Otherwise the incoming address is a physical address and is compared against the contents of PADR
<47:00> that was loaded through the Initialization Block.
All incoming data goes through the CRC Generator. In the case of a logical address,
the six most significant bits of the CRC Generator are strobed into the Hash Register
after the 48th bit of the logical address has gone through this circuitry. This 6-bit address then selects one of the 64 bits in the Logical Address Filter. If the mask bit
selected is a "1 ", the address is accepted and the packet will be put into the current
receive buffer space. The task of mapping a logical address to one of 64 bit positions
is a tedious one that requires a simple computer program to generate the CRC codes
for the addresses desired. The Ethernet CRC Polynomial is CRC-32, which is:
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + XB + X7 + XS + X4 + X2 +
X + 1. Figure 13 shows one such mapping. (This is one of 226 possible mappings).
Hash Address 00 will select bit 0 and Hash Address 63 will select bit 63.
2·10
1-122
o
63
1011 etc.
LOGICAL ADDRESS
FILTER
64 to 1 MUX
CRC31-26
(MUX CONTROL)
31
o
CRC GENERATOR
* If MATCH = 1, the packet is accepted.
If MATCH
=
0, the packet is rejected.
The Broadcast address, which is all ones, is decoded independent of the Logical Address Filter (Broadcast Address will also map to bit 47 of the Logical Address Filter).
If the Logical Address Filter is loaded with all zeroes, all incoming logical addresses
except Broadcast will be rejected.
1 1 1 1 1 1 0 0 0 0 0 0 0 000
54321 0 9 8 7 6 5 4 3 2 1 0
IADR <23:00> +E
IADR <23:00>C
IADR <23:00> +A
IADR <23:00> +8
LADRF
Bits 63:00
The 64-bit mask used by LANCE to accept logical addresses.
1-123
2-11
MAPPING OF LOGICAL ADDRESS TO FILTER MASK
Figure 13
LAF
REG
BITS
SET
0
L
A
F
0
15
0
L
A
F
1
15
LAF
LOC,
DESTINATION
ADDRESS ACCEPTED
DEC,
(HEX)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FF FF FF FF FF 65
FF FF FF FF FF 55
FF FF FF FF FF 15
FF FF FF FF FF 35
FF FF FF FF FF B5
FF FF FF FF FF 95
FF FF FF FF FF D5
FF FF FF FF FF F5
FF FF FF FF FF DB
FF FF FF FF FF FB
FF FF FF FF FF BB
FF FF FF FF FF 8B
FF FF FF FF FF OB
FF FF FF FF FF 3B
FF FF FF FF FF 7B
FF FF FF FF FF 5B
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
2.4.1.4
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF 27
FF 07
FF 57
FF 77
FF F7
FF C7
FF 97
FF A7
FF 99
FF B9
FF F9
FF C9
FF 59
FF 79
FF 29
FF 19
LAF
REG,
BITS
SET
0
L
A
F
2
15
O·
L
A
F
3
15
LAF
LOC,
DESTINATION
ADDRESS ACCEPTED
DEC,
(HEX)
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
FF FF FF FF FF D1
FF FF FF FF FF F1
FF FF FF FF FF B 1
FF FF FF FF FF 91
FF FF FF FF FF 11
FF FF FF FF FF 31
FF FF FF FF FF 71
FF FF FF FF FF 51
FF FF FF FF FF 7F
FF FF FF FF FF 4F
FF FF FF FF FF 1F
FF FF FF FF FF 3F
FF FF FF FF FF BF
FF FF FF FF FF 9F
FF FF FF FF FF DF
FF FF FF FF FF EF
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
FF FF FF FF FF 93
FF FF FF FF FF B3
FF FF FF FF FF F3
FF FF FF FF FF D3
FF FF FF FF FF 53
FF FF FF FF FF 73
FF FF FF FF FF 23
FF FF FF FF FF 13
FF FF FF FF FF 3D
FF FF FF FF FF OD
FF FF FF FF FF 5D
FF FF FF FF FF 7D
FF FF FF FF FF FD
FF FF FF FF FF DD
FF FF FF FF FF 9D
FF FF FF FF FF BD
RECEIVE DESCRIPTOR RING POINTER
1111
10000000000
5 4 3 2 1 098 765 432 1 0
IADR <23:00> +12
IADR <23:00> +10
2-12
1-124
RLEN
Bits 15:13
(Receive Ring Length) Receive Ring Length is the number of entries in the Receive
Ring expressed as a power of two.
RLEN
NUMBER OF ENTRIES
o
1
2
4
8
16
32
64
128
1
2
3
4
5
6
7
RES
Bits 12:08
(Reserved)
RDRA
Bits 07:00 and 15:03
(Receive Descriptor Ring Address) Receive Descriptor Ring Address is the base address (lowest address) of the Receive Descriptor Ring.
RDRA
Bits 02:00
(Must Be Zeros) These bits are RDRA <02:00> and must be zeroes because the
Receive Rings are aligned on quadword boundaries.
2.4.1.5
TRANSMIT DESCRIPTOR RING POINTER
1111
10000000000
5 4 3 2
0 9 8 7 6 5 4 3 2 1 0
IADR <23:00> +16
IADR <23:00>+14
TLEN
Bits 15:13
(Transmit Ring Length) Transmit Ring Length is the number of entries in the Transmit
Ring expressed as a power of two.
TLEN
NUMBER OF ENTRIES
o
1
1
2
3
2
4
8
16
32
64
128
4
5
6
7
1-125
2·13
RES
Bits 12:08
(Reserved)
TDRA
Bits 07:00 and 15:03
(Transmit Descriptor Ring Address) This address is the base address (lowest address)
of the Transmit Descriptor Ring.
Bits 02:00
(Must Be Zeros) These bits must be zeroes because the Transmit Rings are aligned
on quadword boundaries.
2.5 BUFFER MANAGEMENT
Buffer Management is accomplished through message descriptors organized in ring structures in
memory. Each message descriptor entry is four words long. There are two rings allocated for the LANCE:a
Receive ring and a Transmit ring. The LANCE is capable of polling each ring for buffers either to empty
or fill with packets to or from the channel. The LANCE is also capable of entering status information
in the descriptor entry. When polling, LANCE is limited to looking one ahead of the descriptor entry
with which it is currently working. The speed of the data stream restricts the receiver buffer size to
a minimum of 64 bytes to avoid an overflow when chaining receive buffers. The location of the descriptor rings and their length are found in the initialization block, accessed during the initialization procedure
by LANCE. Writing a "ONE" into the STRT bit of CSRO will cause LANCE to start accessing the descriptor
rings and enable it to send and receive packets. The LANCE communicates with a HOST device (probablya microprocessor) through the ring structures in memory. Each entry in the ring is either "owned"
by LANCE or the HOST. There is an ownership bit (OWN) in the message descriptor entry. Mutual exclusion is accomplished by a protocol which states that each device can only relinquish ownership of
the descriptor entry to the other device; it can never take ownership, and each device cannot change
the state of any field in an entry after it has relinquished ownership. When chaining buffers, the minimum
transmit buffer size is restricted to 100 bytes (to avoid mutual exclusion violations, which could occur
following a collision). Otherwise, LANCE would access a buffer to which it had relinquished ownership
(to reinitialize a transmission interrupted by a collision).
2.5.1
DESCRIPTOR RINGS
Each descriptor in a ring in memory is a 4 word entry. The following is the format of the receive
and the transmit descriptors.
2.5.1.1
RECEIVE MESSAGE DESCRIPTOR ENTRY
2.5.1.1.1
RECEIVE MESSAGE DESCRIPTOR 0 (RMDO)
MEMORY ADDRESS: XXXXXXXO
1111
10000000000
5 4 3 2
0 9 8 7 6 5 4 3 2 1 0
LADR
Bits 15:00
The Low Order 16 address bits of the buffer pOinted to by this descriptor.
LADR is written by the Host and unchanged by LANCE.
2.5.1.1.2 RECEIVE MESSAGE DESCRIPTOR 1 (RMD1)
2·14
1-126
MEMORY ADDRESS: XXXXXXX2
1111
5 4 3 2
10000000000
098 765 432 1 0
OE FO C B S E
WR R F R U TN
N R A L C F P P
MO
F
I I I I I I I
HADR
I I I I I I I
OWN
Bit 15
This bit indicates that either the Host owns the descriptor entry (OWN =
0) or LANCE owns it (OWN = 1). The chip clears the OWN bit after filling
the buffer pOinted to by the descriptor entry. The Host sets the OWN bit
after emptying the buffer. Once the LANCE or Host relinquishes ownership of a buffer, it may not change any field in the four words that comprise the descriptor entry.
ERR
Bit 14
(Error Summary) Error Summary is the "OR" of FRAM, OFLO, CRC or
BUFF. ERR is set by LANCE when it releases the buffer and is cleared
by the Host.
FRAM
Bit 13
(Framing Error) Framing Error indicates that the incoming packet contained
both a non-integer multiple of eight (8) bits and a CRC error. In internal
loopback, whenever a CRC error occurs, FRAM will always be set. FRAM
is set by LANCE when it releases the buffer and is cleared by the Host.
OFLO
Bit 12
(Overflow) Overflow error indicates that the receiver has lost all or part
of the incoming packet due to an inability to store the packet in a memory
buffer before the internal SILO overflowed. OFLO is set by LANCE when
it releases the buffer and is cleared by the Host.
CRC
Bit 11
CRC indicates that the receiver has detected a CRC error on the incoming packet. CRC is set by LANCE when it releases the buffer and is cleared
by the Host.
BUFF
Bit 10
(Buffer Error) Buffer Error is set either when LANCE has utilized all its
allocated buffers or if the next status is not acquired in time while data
chaining a received packet. BUFF is set by LANCE when it releases the
buffer and is cleared by the Host. If a Buffer Error occurs, an Overflow
Error also occurs because LANCE tries to acquire the next buffer until
the SILO overflows.
STP
Bit 09
(Start of Packet) Start of Packet indicates that this is the first buffer used
by LANCE for this packet. It is used for data chaining buffers. STP is set
by LANCE when it releases the buffer and is cleared by the Host.
1.127
2·15
ENP
Bit 08
(End of Packet) End of Packet indicates that this is the last buffer used
by LANCE for this packet. It is used for data chaining buffers. If both STP
and ENP were set, the packet would fit into one buffer and there was no
data chaining. ENP is set by LANCE when it releases the buffer and is
cleared by the Host.
HADR
Bits 07:00
The High Order 8 address bits of the buffer pOinted to by this descriptor.
This field is written by the Host and unchanged by LANCE.
2.5.1.1.3 RECEIVE MESSAGE DESCRIPTOR 2 (RMD2)
MEMORY ADDRESS: XXXXXXX4
11111 1 0 0 0 0 0 0 0 0 0 0
54321 0 9 8 7 6 5 4 321 0
Bits 15:12
(Must Be Ones) This field is written by the Host and unchanged by LANCE.
BCNT
Bits 11:00
(Buffer Byte Count) Buffer Byte Count is the length of the buffer pOinted
to by this descriptor expressed as a two's complement number. This field
is written by the Host and unchanged by LANCE. The minimum buffer
size is 64 bytes.
2.5.1.1.4
RECEIVE MESSAGE DESCRIPTOR 3 (RMD3)
MEMORY ADDRESS: XXXXXXX6
1 1 1 1 1 1 000 0 0 0 0 0 0 0
5 4 321 098 7 6 5 4 321 0 .
RES
Bits 15:12
(Reserved) Read as zeroes.
2-16
MCNT
Bits 11:00
(Message Byte Count) Message Byte Count is the length in bytes of the
received message. MCNT is valid only when ERR is clear and ENP is set.
MCNT is written by LANCE and is cleared by the Host. In data chaining,
RMD3 is only written to after the last buffer status is updated. Only the
status word is updated for intermediate buffers in the data chain.
1-128
2.5.1.2
TRANSMIT MESSAGE DESCRIPTOR ENTRY
2.5.1.2.1
TRANSMIT MESSAGE DESCRIPTOR 0 (TMDO)
MEMORY ADDRESS: XXXXXXXO
1 111 1 1 0 0 0 0 0 0 0 0 0 0
5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
I::::::
~~:::::: I
lADR
Bits 15:00
The Low Order 16 address bits of the buffer pOinted to by this descriptor.
LADR is written by the Host and unchanged by LANCE.
2.5.1.2.2 TRANSMIT MESSAGE DESCRIPTOR 1 (TMD1)
MEMORY ADDRESS: XXXXXXX2
111 1 1 1 0 0 0 0 0 0 0 0 0 0
5 4 3 2 1 0 9 8 7 6 5 432 1 0
OE RM 00 S E
WR EO N E TN
N R S R E F P P
E
I I I I I I I
HADR
I I I I I I I
OWN
Bit 15
This bit indicates that either the Host owns the descriptor entry (OWN =
0) or LANCE owns it (OWN = 1). The host sets the OWN bit after filling
the buffer pointed to by the descriptor. LANCE clears the OWN bit after
transmitting the contents of the buffer. Both the Host and LANCE must
not alter a descriptor entry after it has relinquished ownerShip.
ERR
Bit 14
(Error Summary) Error Summary is the "OR" of LCOL, LCAR, UFLO or
RTRY. ERR is set by LANCE when it releases the buffer and is cleared
by the Host.
RES
Bit 13
(Reserved) LANCE will write this bit with a "0".
MORE
Bit 12
MORE indicates that more than one retry was needed to transmit a packet.
MORE is set by LANCE when it releases the buffer and is cleared by the
Host.
ONE
Bit 11
ONE indicates that exactly one retry was needed to transmit a packet. ONE
is set by LANCE when it releases the buffer and is cleared by the Host.
ONE is not valid if LCOl in TMD3 is set.
1-129
2·17
DEF
Bit 10
(Deferred) Deferred indicates that LANCE had to defer while trying to
transmit a packet. This condition occurs when the channel is busy when
LANCE is ready to transmit. DEFER is set by LANCE when it releases
the buffer and is cleared by the Host.
STP
Bit 09
(Start of Packet) Start of Packet indicates that this is the first buffer to be
used by LANCE for this packet. It is used for data chaining buffers. STP
is set by the Host and is unchanged by LANCE.
ENP
Bit 08
(End of Packet) End of Packet indicates that this is the last buffer to be
used by LANCE for this packet. It is used for data chaining buffers. If both
STP and ENP are set. the packet fits into one buffer and there is no data
chaining. ENP is set by the Host and is unchanged by LANCE.
HADR
Bits 07:00
The High Order 8 address bits of the buffer pOinted to by this descriptor.
This field is written by the Host and is unchanged by LANCE.
2.5.1.2.3 TRANSMIT MESSAGE DESCRIPTOR 2 (TMD2)
MEMORY ADDRESS: XXXXXXX4
111 1 1 1 0 0 0 0 0 000 0 0
5432109 8 765 432 1 0
ONES
Bits 15:12
(Must Be Ones) This field is set by the Host and unchanged by LANCE.
BCNT
Bits 11:00
(Buffer Byte Count) Buffer Byte Count is the usable length in bytes of the
buffer pOinted to by this descriptor expressed as a two's complement
negative number. This is the number of bytes from this buffer that will be
transmitted by LANCE. This field is written by the Host and unchanged
by LANCE. The minimum buffer size is 100 bytes when chaining or 64
bytes when not chaining.
2.5.1.2.4 TRANSMIT MESSAGE DESCRIPTOR 3 (TMD3)
TMD3 is valid only if the ERR bit of TMD1 has been set by LANCE.
MEMORY ADDRESS: XXXXXXX6
2·18
1-130
1 1 1 1
5 4 3 2
1 0 0 0 0 0 0 0 0 0 0
098 7 6 5 4 3 2 1 0
BURLLR
U F E C C T
F L S 0 A R
F 0
L R Y
BUFF
Bit 15
(Buffer Error) Buffer Error is set by LANCE during transmission when
LANCE does not find the ENP flag in the current buffer and does not own
the next buffer. BUFF is set by LANCE and cleared by the Host. If a Buffer
Error occurs, an Underflow Error will also occur because LANCE tries to
read memory data until the SILO is empty. Buffer Error is valid only if UFLO
is set.
UFLO
Bit 14
(Underflow Error) Underflow Error indicates that the transmitter has truncated a message due to data late from memory. UFLO indicates that owing to a lack of data from memory, the SILO has emptied before the end
of the packet was reached. UFLO is set by LANCE and is cleared by the
Host.
RES
Bit 13
Reserved bit. LANCE writes this bit with a "0".
lCOl
Bit 12
(Late Collision) late Collision indicates that a collision has occurred after
the slot time of the channel has elapsed. lANCE does not retry on late
collisions. LCOL is set by LANCE and is cleared by the Host.
lCAR
Bit 11
(loss of Carrier) loss of Carrier is set when the carrier presence (RENA)
input to lANCE goes false during a LANCE-initiated transmission. LANCE
does not retry upon Loss of Carrier. LCAR is set by lANCE and is cleared
by the Host.
RTRY
Bit 10
(Retry Error) Retry Error indicates that the transmitter has failed in 16 attempts to successfully transmit a message due to repeated collisions on
the medium. If DRTY = 1 in the MODE register, RTRY sets after 1 failed
transmission attempt. RTRY is set by LANCE and is cleared by the Host.
TOR
Bits 09:00
(Time Domain Relectometry) Time Domain Reflectometry is an internal
counter that counts system clocks from the start of a transmission to the
occurrence of a collision. This value is useful in determining the approximate distance to a cable fault. The TDR value is written by LANCE and
is valid only if RTRY is set.
1-131
2-19
DESCRIPTOR RINGS IN MEMORY
HIGHER ADDRESSES
15
°
TMD(127)
TRANSMIT RING
TMD(1)
TMD(O)
BASE ADDRESS OF
TRANSMIT RING
HIGHER ADDRESSES
,..15_ _ _ _ _ _ _ _ _ _ _ _0...,
RMD(127)
RECEIVE RING
RMD(1)
RMD(O)
BASE ADDRESS OF
RECEIVE RING
2-20
1-132
CHAPTER 3
FUNCTIONAL SPECIFICATIONS
3.0
INTRODUCTION
3.1
FUNCTIONAL DESCRIPTION
This section describes the logical elements used to implement the LANCE Ethernet Controller.
3.2 LOGIC
3.2.1
CLOCK
The LANCE has its clocks derived from a basic free running 10 MHz clock presented to the
input pin TCLK. Refer to Section 4 for the clock specification. The microcycle is 200 nanoseconds
long, or two basic clock ticks. The microcycle is the basic unit of time in the microsequencer
and the control data path. Clock suppression is the act of selectively stretching the microcycle
to allow a memory transfer to complete when the Chip is operating as a bus master. Clock suppression can only occur in those microcycles that contain an asserted USUPPRESS bit in the
microword register.
3.2.2
MICROSEQUENCER
LANCE is controlled by an internal microprogram. Chained sequencing is used to advance the
program address. Each microword contains the address of the next instruction plus any microbranch and trap information required in the program being executed. The microsequencer
operates as a one level deep pipeline. As one micro-instruction is being executed, the next is
being accessed. The basic microcycle is 200 nanoseconds long, but may be extended on 200
nanosecond boundaries to allow memory transfers to complete. During each microcycle, an address is formed to access the program store which is clocked into the microword register at
the end of each cycle.
3.2.3
CONTROL DATA PATH
The Control Data Path contains the hardware necessary to bUild,control, and store the information required to do buffer management and to control the block transfers of data to and from
the silo. The major components in this section of logic are a 24-bit adder, a data shuffler, a constant selector, and a static memory. In this memo.ry resides twelve 24-bit Address Registers and
ten 16 bit Statusl Byte Count Registers.
3.2.4
MESSAGE BYTE COUNT
The message byte count is contained in a 12-bit counter. The message byte count keeps track
of the number of bytes entering or leaving the Silo under microprogram control for each transmission or reception. The value contained in the message byte count is written into memory through
the MDR as part of the reception process. It is also used for the detection of runt packets on
reception, and for the detection of babbling transmissions.
3.2.5
RING END FINDERS
The ring end finders, one each for the receive and transmit rings, determine whether the ring
address pointers in the CDP RAM are at the end of the rings, and provide a microbranchable
signal, which, when true, informs the microprogram to restore the pOinters with the beginning
address of the rings. The ring end finders are simply a pair of programmable modulo counters,
the value of which is loaded at initialization time. The counters are independently incremented
under microprogram control.
1-133
3-1
3.3
BUS CONTROL
3.3.1
BUS ADDRESS REGISTER
The Bus Address register (BA) is 27 bits wide. It is loaded directly from the Data Shuffler under
control of a bit in the microword, ENA BA CLK, at the end of the microcycle. At the same time,
the bus address is clocked, byte mask and readlwrite information, associated with the transfer
is clocked into a three bit extension of the BA. Clocking of the BA initiates the bus transfer. The
upper 8 bits of the BA drive A <23:16> directly. The lower sixteen bits of the BA are multi·
plexed onto DAL < 15:00> during the address portion of the bus cycle when LANCE is the
Bus Master. This is an internal register and is not directly addressable by the user.
3.3.2
MEMORY DATA REGISTER
The Memory Data register (MDR) buffers data transfers to and from the 1/0 bus. The MD is clocked
at the end of the microcycle. It is enabled from the ENA MD CLK bit of the microword register.
1/0 bus data is synchronized to LANCE prior to loading the MDR.
3.3.3
BUS MASTER CONTROL
LANCE becomes a Bus Master for the purposes of acquiring data from the initialization block,
buffer management, and the block move of data during the transmission or reception process.
The Bus Master Control works in partnership with the microprogram. :rhe microprogram is responsible for loading the BA and MDR for a write transaction, and loading the BA and unloading
the MDR for a read transaction. Clocking the BA initiates the transfer. The microprogram also
provides a clock suppress enable to stall selectively a microcycle until a memory transaction
completes, thus providing synchronization between the microprogram and the Bus Master Control. During block transfer (DMA) of data, memory references overlap. LANCE performs up to
8 data transfers before relinquishing HOLD. Refer to Chapter 4 for timing specifications.
3.3.4
MEMORY TIMEOUT
As a Bus Master, LANCE detects and recovers from non-existent memory errors. LANCE waits
for a maximum of 25 microseconds for the assertion of READY after it asserts ALE. If LANCE
does not receive READY within that time, it sets the MERR bit of CSRO, negates the RXON
and TXON bits, and takes no further action unless either the RESET signal is asserted or the
STOP bit of CSRO is asserted.
3.3.5
BUS SLAVE CONTROL
The Bus Slave control is invoked when a memory transaction occurs and the CS pin is asserted.
When this happens, it indicates that one of the four LANCE CSR's is being accessed. CSRO
provides visibility into LANCE and is accessed independently of the microprogram. CSR1 and
CSR2 hold the address of the initialization block and are resident within the CDP RAM. Accessing CSR1 and CSR2 causes a microtrap for access. The microprogram issues the READY signal
for CSR1 and CSR2. The Bus Slave Control independently returns READY for CSRO and CSR3.
CSR 3 allows the I/O pins to be programmed. CSR1, CSR2, and CSR3 are accessible only when
the STOP bit of CSRO is set. Refer to Chapter <1/ for timing specifications.
3.3.6
DISCRETE USER APPARENT REGISTERS
Of the register ports and control and status registers, CSRO, CSR3, and RAP are read and written asynchronously from the parallel I/O bus. Refer to Section 2.3 for definitions of the register
ports and control and status registers.
3.4
TRANSCEIVER DATA PATH
3.4.1
SERIAL DATA OUTPUT
Serial output data is presented at the TX Output pin by LANCE. The presence of the output
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data stream is indicated by the assertion of the TENA level at the Output pin. TX and TENA
are synchronous to the internal clock TCLK.
3.4.2
SERIAL DATA INPUT
Serial input data is presented to LANCE at the RX Input pin. The serial input data clock is
presented at the RCLK Input pin. The presence of the input data stream is indicated by the
assertion of the RENA at its Input pin. RX, RCLK, and RENA are asynchronous to the internal
clock TCLK. RCLK is used by LANCE to clock in the input data stream. After the assertion of
RENA, LANCE waits 800 nanoseconds before searching for the start bit. If LANCE detects a
double ZERO prior to detecting a START bit, LANCE rejects the rest of the packet. Once the
Start bit has been detected, LANCE frames the remaining bit stream into byte boundaries, synchronizes the bytes to the internal clock, and loads the Silo if not otherwise disabled.
3.4.3
SILO
The SILO provides buffer storage for the data being transferred between the parallel bus 1/0
pins and serial bus 1/0 pins. The capacity of the SILO is 48 bytes. The fall-through time of the
SILO is 200 nanoseconds maximum. The SILO has the following capabilities:
1. SILO OPERATION - TRANSMISSION. Data is loaded into the SILO under
microprogram control from the MDR. Data from the SILO goes to the serial output
shift register.
2. SILO OPERATION - UNDERFLOW. Underflow occurs during Transmission when
the output serial shift register requires data to continue an unbroken bit stream
output, but data is not available at the output of the SILO, and the last data byte
in the frame has been shifted out. Once the SILO has underflowed, the SILO locks
out further reads and writes until cleared by the microprogram.
3. SILO OPERATION - RECEPTION. Data is loaded into the SILO from the serial
input shift register during Reception. Data leaves the SILO under microprogram
control. The destination is the MDR. Preamble is not loaded into the SILO.
4. SILO OPERATION - OVERFLOW. Overflow occurs during Reception when the SILO
is filled and data needs to be transferred from the input serial shift register. Once
the SILO has overflowed, the SILO locks out further reads and writes until cleared
by the microprogram.
5. SILO OPERATION - RESTORE. During Reception, restoring the SILO refers to
the action of discarding the 6 bytes of the destination address that have accumulated in the SILO after an address match has been tested and an address
match has not occurred. The same action occurs if less than 6 bytes are received
before the packet ends. Note that this is different from clearing the SILO since there
may be residual data in the SILO from a previous reception which cannot be lost.
During the Transmission process, restoring the SILO refers the action of discarding the accumulated Transmit bytes when bit stream transmission has not yet
begun and the receiver becomes active.
6. SILO OPERATION -INDEXING. The SILO is capable of holding residual data from
a received packet, and accepting data from a second packet. The SILO is able
to mark the end of one packet and the beginning of another.
7. SILO OPERATION - CLEARING. The SILO is cleared as part of the recovery for
overflow, underflow, and collision. SILO clearing is the action of flushing all data
from the SILO unconditionally by clearing the address counters. The SILO is cleared
by a discrete microprogram operation.
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3-3
3.4.4
SILO - MEMORY BYTE ALIGNMENT
Memory buffers may begin and end on arbitrary byte boundaries. Parallel data is byte aligned
between the SILO and the MDR. Byte alignment can be reversed by setting the Byte Swap
(BSWP) bit in CSR3.
TRANSMISSION - WORD READ FROM EVEN MEMORY ADDRESS
BWSP = 0:
SILO BYTE n
gets MDR <07:00>
SILO BYTE n + 1 gets MDR < 15:08 >
BWSP = 1:
SILO BYTE n
gets MDR <15:08>
SILO BYTE n + 1 gets MDR <07:00>
TRANSMISSION - BYTE READ FROM EVEN MEMORY ADDRESS
BSWP = 0:
SILO BYTE n
gets MDR <07:00>
BSWP = 1:
SILO BYTE n
gets MDR < 15:08 >
TRANSMISSION - BYTE READ FROM ODD MEMORY ADDRESS
BWSP = 0:
SILO BYTE n
gets MDR <15:08>
BWSP = 1:
SILO BYTE n
gets MDR <07:00>
RECEPTION - WORD WRITE TO EVEN MEMORY ADDRESS
BSWP = 0:
BSWP
=
1:
MDR <07:00> gets SILO BYTE n
MDR <15:08> gets SILO BYTE n
+
1
MDR < 15:08> gets SILO BYTE n
MDR <07:00> gets SILO BYTE n
+
1
RECEPTION - BYTE WRITE TO EVEN MEMORY ADDRESS
BSWP = 0:
MDR <07:00> gets SILO BYTE n
MDR < 15:08 > - don't care
BSWP = 1:
MDR <15:08> gets SILO BYTE n
MDR <07:00> - don't care
RECEPTION - BYTE WRITE TO ODD MEMORY ADDRESS
3.4.5
BSWP = 0:
MDR <07:00> - don't care
MDR < 15:08> gets SILO BYTE n
BSWP = 1:
MDR < 15:08> - don't care
MDR <07:00> gets SILO BYTE n
CYCLIC REDUNDANCY CHECK
LANCE utilizes the 32-bit CRC function used in the Autodin-II network. Refer to the Ethernet
Specification (section 6.2.4 Frame Check Sequence Field and Appendix C; CRC Implementation) for more detail. LANCE requirements for the CRC logic are the following:
1. TRANSMISSION - MODE <02> LOOP = 0, MODE <03> DTCRC = O. LANCE calculates
the CRC from the first bit following the Start bit to the last bit of the data field. The CRC value
is inverted and appended onto the transmission in one unbroken bit stream.
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2. RECEPTION - MODE < 02 > LOOP = O. LANCE performs a check on the input bit stream
from the first bit following the Start bit to the last bit in the frame. LANCE continually samples
the state of the CRC check on framed byte boundaries, and, when the incoming bit stream
stops, the last sample determines the state of the CRC error. Framing error (FRAM) is not
reported if there is no CRC error.
3. LOOPBACK - MODE < 02 > LOOP = 1, MODE < 03 > DTRC = O. LANCE generates and
appends the CRC value to the outgoing bit stream as in Transmission but does not check
the incoming bit stream.
4. LOOPBACK - MODE < 02 > LOOP = 1 MODE < 03 > DTRC = 1. LANCE performs the CRC
check on the incoming bit stream as in Reception, but does not generate or append the CRC
value to the outgoing bit stream.
3.5
TRANSMISSION
Serial transmission consists of sending an unbroken bit stream from the TX pin consisting of:
1. Preamble I Start bit: 64 alternating ONES and ZEROS terminating in two ONEs. The last
ONE is the Start bit.
2. Data: The serialized byte stream from the Silo. Shifted out LSB first.
3. CRC: The inverted 32 bit polynomial calculated from the Data field. CRC is not transmitted if:
1. Transmission of the Data field is truncated for any reason.
2. CLSN becomes asserted any time during transmission.
3. LANCE is in Loopback mode and CRC transmission is disabled (MODE <03>
1 and MODE <02> = 1).
4. Mode <03> DTCRC = 1 in a normal transmission mode.
Transmission is indicated at the I/O pin by the assertion of TENA with the first bit of the preamble and
the negation of TENA after the last transmitted bit. LANCE starts transmitting the preamble when the
following are satisfied.
1. There is at least one byte of data to be transmitted in the Silo.
2. The inter-packet delay has elapsed.
3. The backoff interval has elapsed, if a retransmission.
3.5.1
INTERPACKET DELAY
The interpacket delay is 9.6 to 10.6 microseconds including synchronization. The interpacket
delay interval begins after the negation of the RENA signal, LANCE continuously monitors the
RENA input pin to monitor or generate an interpacket delay. If LANCE is about to transmit (about
to assert the TENA output pin) and RENA is asserted, the chip will not assert TENA until RENA
has negated and the interpacket delay has elapsed. Whenever LANCE is about to transmit and
is waiting for the interpacket delay to elapse, it will begin transmission immediately after the
interpacket delay interval, independent of the state of RENA.
3.5.2
COLLISION DETECTION AND COLLISION JAM
Collisions are detected by monitoring the CLSN input pin. If CLSN becomes asserted during
a Frame Transmission, TENA will remain asserted for at least 32 (but not more than 48) additional bit times (including CLSN synchronization). This additional transmission after collision
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3-5
is referred to as COLLISION JAM. The bit pattern present at the TX output pin is unspecified
during COLLISION JAM, but it may not be the 32 bit CRC value corresponding to the (partial)
packet transmitted prior to the COLLISION JAM.
If CLSN becomes asserted during the reception of a packet, this reception is immediately ter·
minated. Depending on the timing of collision detection, the following will occur. A collision that
occurs within 6 byte times (4.8 microseconds) will result in the packet being rejected because
of an address mismatch with the silo write pointer being reset. A collision that occurs within
64 byte times (51.2 microseconds) will result in the packet being rejected since it is a runt packet.
A collision that occurs after 64 byte times will result in a truncated packet being written to the
memory buffer with the CRC error bit being set in the Status Word of the Receive Ring.
3.5.3
COLLISION BACKOFF
When a transmission attempt has been terminated due to the assertion of CLSN, it is retried
by LANCE up to 15 times until successful, or something else aborts the process (memory timeout).
The scheduling of the retransmissions is determined by a controlled randomized process called
"truncated binary exponential backoff." Upon the negation of the COLLISION JAM interval,
LANCE calculates a delay before retransmitting. The delay is an integral multiple of the SLOT
TIME. The SLOT TIME is 512 bit times. The number of SLOT TIMEs to delay before the nth
retransmission attempt is chosen as a uniformly distributed random integer in the range:
where k = min (n,10)
If all 16 attempts fail, LANCE sets the RTRY bit in the current Transmit Message Descriptor 3
in memory, and steps over the current transmit buffer.
3.5.4
COLLISION· MICROCODE INTERACTION
The microprogram uses the time provided by COLLISION JAM, INTERPACKET DELAY, and
the backoff interval to restore the address and byte counts and start loading the Silo in anticipa·
tion of retransmission. It is important that LANCE be ready to transmit when the backoff interval
elapses in order to utilize the channel properly.
3.5.5
TIME DOMAIN REFLECTOMETRY
LANCE contains a time domain reflectometry counter. The TDR counter is ten bits wide. It counts
at a 10 MHz rate. It is cleared by the microprogram and counts upon the assertion of RENA
during transmission. Counting ceases if CLSN becomes true. The counter does not wrap around,
once all ONEs are reached in the counter, that value is held until cleared. The value in the TDR
is written into memory by the microprogram through the MDR. TDR is used to determine the
location of suspected cable faults. Transfer from TDR counter into MDR register occurs only
if RTRY is set. Normally, when RTRY is not set, the value of TDR will be all zeros.
3.5.6
HEARTBEAT
During the INTERPACKET DELAY following the negation of TENA, the CLSN input is asserted
by some Version 1 and all Version 2 transceivers as a self·test. If two microseconds of the IN·
TERPACKET DELAY elapse without CLSN having been asserted, LANCE will set the CERR
bit in CSRO (bit < 13 ». This function is gated off in the internal loopback mode.
3.6
RECEPTION
Serial reception consists of receiving an unbroken bit stream on the RX I/O pin consisting of:
1. Preamble I Start bit: Two ONES occurring a minimum of 8 bit times after the assertion of RENA.
The last ONE is the Start bit.
2. Destination Address: The 48 bits (6 bytes) following the Start bit.
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1·138
3. Data: The serialized byte stream following the Destination Address. The last four complete
bytes of data are the CRC. The Destination Address and the Data are framed into bytes and
enter the Silo.
Reception is indicated at the I/O pin by the assertion of RENA and the presence of clock on RCLK while
TENA is deasserted.
3.6.1
STATION ADDRESS DETECTION
The station address detect logic checks the destination address of the incoming packet to determine if the packet is addressed to this node. A packet will be accepted if at least one of the
following is true:
1. Physical address match: The destination address of the packet exactly matches the
physical address of the node.
2. Logical address match: The destination address of the packet is hashed using the
CRC. The hash function is used to determine a logical address match.
3. Promiscuous mode: The node accepts all packets regardless of the destination
address.
4. Broadcast Detection: The destination address of the packet is the Broadcast Address;
all ones.
3.6.1-1
PHYSICAL ADDRESS REGISTER
The physical address register is 48 bits wide and contains the physical address of
LANCE. The microprogram loads the physical address from the initialization block
through three sequential memory transactions. If the first bit following the Start bit
is a ZERO, LANCE will perform a physical address compare. The following 47 bits
are compared, bit for bit, for an exact match. If they do not match, LANCE will reject
the packet. Bit < 00 > of the physical address register corresponds to the first bit
of the destination address field, and bit < 47 > of the physical address register corresponds to the last bit of the destination address field.
3.6.1.2
LOGICAL ADDRESS FILTER REGISTER
The logical address filter register is 64 bits wide. The microprogram loads the logical
address filter from the initialization block through four sequential memory transactions. If the first bit following the Start bit is a ONE, LANCE will perform a logical
address compare. After the last bit of the destination address is clocked into the CRC
check logic, the value of CRC 31:26 is used as an index into the logical address filter
register. If the bit selected in the register is not a ONE, the chip will reject the packet.
3.6.1.3
PROMISCUOUS MODE
If MODE < 15 > PROM = 1, LANCE will accept all packets, regardless of the destination address.
3.6.1.4
BROADCAST ADDRESS DETECTION
LANCE will always accept all packets sent to the Broadcast Address of all ones.
3.6.2
RUNT PACKET FILTRATION
If, after loading a buffer, the message byte count is less than 64 bytes, LANCE does not update
the ring descriptor entry that pointed to the buffer. Instead LANCE retains the buffer information
for use with the next incoming packet. An incoming message must be greater than 64 bytes
to be considered a valid packet.
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3-7
3.7
LOOPBACK
normal operation of LANCE is as a half duplex device. However, to provide an on-line operational
test of LANCE, a pseudo-full duplex mode is provided. In this mode, simultaneous transmission and
reception of a loopback packet are enabled with the following constraints:
1. The packet length must be no longer than 32 bytes, exclusive of the CRC.
2. Serial transmission does not begin until the Silo contains the entire output packet.
3. Moving the input packet from the Silo to the memory does not begin until the serial
input bit stream terminates.
4. CRC may be generated and appended to the output serial bit stream or may be
checked on the input serial bit stream, but not both in the same transaction.
Loopback is controlled by bits < 06,03:02 > INTL, DTCR, and LOOP of the MODE register. Refer to Section 2.4.1.1 for detailed operation of this register.
3.8
MICROPROGRAM OVERVIEW
3.8.1
SWITCH ROUTINE
Upon power-up, the microprogram finds itself in a routine to evaluate the INIT, STRT, and STOP
bits of CSRO. INIT and STRT are cleared and STOP is set by the hardware by RESET. Setting
either INIT or STRT through an 1/0 transfer to CSRO clears STOP. Setting STOP through an
1/0 transfer clears INIT and STRT. After seeing STOP cleared, the microprogram tests the state
of INIT. If set, it branches to the initialization routine, returns, and tests the state of STRT. If INIT
is clear and STAT is set, the microprogram goes on to the Polling routine without going to the
Initialization routine. If, while the STOP bit is set, an 1/0 transfer to CSR1 or CSR2 occurs, the
microprogram traps to the CSR service 10titine.
3.8.2
INITIALIZATION ROUTINE
This routine is entered only from the switch routine upon the setting of the INIT bit. Its function
is to load LANCE with the data from the initialization block in memory. The routine accesses
the initialization block through the address loaded into the COP RAM by a trap to CSR1 and
CSR2 that should have occurred prior to the INIT bit being set. This routine simply sequentially
reads the initialization block and stores the information away in the appropriate elements of
LANCE. When done, the microcode returns to the switch routine.
3.8.3
POLLING ROUTINE
This routine is entered from:
1. The switch routine upon the setting of the STRT bit.
2. The receive routine after a packet has been received.
3. The transmit routine after a packet has been transmitted.
4. The transmit routine after a Transmission Abort occurs.
5. The memory error trap routine after the trap is serviced.
The routine begins by testing to see if the receiver is disabled, and, if not, tests the current
receiver buffer ownership bit to see if it owns a buffer. If LANCE had not acquired a buffer previously, the microprogram goes to the receiver polling routine to acquire one. When the microprogram
returns from the receive polling routine, or if LANCE had acquired a buffer previously, it tests
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1-140
to see if the transmitter is disabled, and, if not, goes to the transmit polling routine to test if
there is a buffer to be transmitted. When the microprogram returns from the transmit polling
routine, the microprogram enters a timing loop; and repeats the routine upon timeout (above
1.6 ms). Setting the TDMD bit in CSRO overrides the timing loop. This forces the microprogram
to fall through the wait loop. The TDMD bit is cleared immediately after leaving the wait loop.
Therefore, to be effective, TDMD should be set after a buffer has been inserted on the transmit
ring.
During this routine, should the receiver become active, the microprogram traps to the receive
routine.
3.8.4
RECEIVE POLLING ROUTINE
This routine is entered if the receiver is enabled, and LANCE needs a free buffer. The routine
begins by the microprogram performing a memory transaction to get a buffer status word from
the receive descriptor ring. After acquiring the word, it tests to see if it owns the buffer. If not,
the microprogram returns to the polling routine. If it does, the microprogram proceeds to acquire two additional words to obtain the rest of the buffer address and byte count. It then returns
to the polling routine with the three words stored in the CDP RAM. The trap to the receive routine
is enabled in this routine.
3.8.5
RECEIVE ROUTINE
The receive routine is entered when the receiver is enabled and an incoming packet address
has been detected as a match. The routine is divided into three sections of code, an initialization section, a buffer lookahead section, and a descriptor update section. In the initialization
section, the microprogram first tests to see if it has acquired a free buffer. If not, it makes one
attempt to get the status, address, and byte count from memory. LANCE backs up the address
and byte count in the CDP RAM for runt packet recovery, and proceeds to the lookahead section. In the lookahead section, the microprogram tries to acquire an additional buffer by memory
transactions with the ring buffer descriptors. If it acquires one, it stores it in the CDP RAM, and
waits for byte count overflow or the frame to terminate. In this section the receive DMA trap
is enabled. The descriptor update section is entered when byte count overflow has occurred
or the message has ended. The code section begins with a test to determine if the message
has completed, if data chaining needs to be done, or if a runt packet has been encountered.
If a runt packet has been encountered, the microprogram restores the address and byte count
and goes to the polling routine. If the incoming message has terminated, the microprogram writes
the message length into the ring descriptor entry, writes the status information into the ring
descriptor entry, puts the next buffer status information it acquired in the lookahead code in
the current buffer status area of the CDP RAM, advances the ring pOinter, and goes to polling.
If the byte count has overflowed, but the message has not ended, chaining is required. The
microprogram releases the buffer by writing the status information into the ring descriptor entry,
puts the next buffer status information it acquired in the lookahead code in the current buffer
status area of the CDP RAM, advances the ring pointer, and returns to the lookahead code section.
3.8.6
RECEIVE DMA ROUTINE
The Receive DMA routine is entered whenever there are 16 or more bytes of data in the SILO
for transfer to memory during receive. The routine is also entered when there are less than 16
bytes in the SILO and the receiver has gone inactive. This is to allow the SILO to empty at the
end of reception. Once entered, the Receive DMA routine transfers 16 bytes of data to memory
by doing 8 word transfers. These transfers are done on a single memory bus acquisition. This
means that LANCE will arbitrate through the HOLD-HOLD ACKNOWLEDGE sequence and then
keep HOLD asserted for the duration of 8 transfers. The READY signal from the bus slave device
controls the individual word transfers.
If the memory buffer starts on an odd address boundary, the first transfer is 1 byte rather than
1 word (2 bytes). This routine is also used to transfer less than 16 bytes at the end of a reception
depending upon the packet size, buffer addresses and data chaining.
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3-9
NOTE:
DMA (direct memory access) is performed each time LANCE initiates a memory transfer. However,
in this document, DMA refers only to those transfers between the SILO and Bus memory.
This routine is entered through a microtrap in the lookahead section of the receive routine. The
function of the routine is to move data out of the SILO to local memory. The trap is active when
there are 16 or more bytes of data in the SILO and SILO overflow has not occurred or when
the incoming message has terminated with data in the SILO. The routine pipelines the data
through the Memory Data register while the address and byte counts are incremented in the
control data path. A memory timeout will cause a trap. The routine is exited through the URETURN
register to the code section that originally trapped to this routine.
3.8.7
TRANSMIT POLLING ROUTINE
The transmit polling routine is entered from the polling routine to determine if a message has
been scheduled on the transmit descriptor ring. The routine begins by testing the status word
of the ring descriptor entry. The routine tests the ownership of the ring buffer by reading the
status word in the ring descriptor. If LANCE does not own the buffer, the microprogram returns
to the polling routine. If it does own the buffer, this indicates that a message is to be transmitted,
and the microprogram performs memory transactions to acquire and store the address and byte
count of the buffer in the CDP RAM. It then goes to the transmit routine to allow transmission
of the buffer. The receive active trap is enabled during this routine to allow for processing of
an incoming packet and termination of the transmit process.
3.8.8
TRANSMIT ROUTINE
The transmit routine is entered from the transmit polling routine when the microcode finds a
buffer that it owns, indicating that a message is scheduled to be transmitted. The routine is
divided into three sections of code: an initialization section, a buffer lookahead section, and
a descriptor update section. Upon entering the initialization section, the first thing the
microprogram does is back up the buffer address and byte count in the event of a retry. It then
enables the DMA engine to start filling the SILO and send the preamble. It then enters a wait
loop until the transmitter is actually sending the bit stream. It then proceeds to the lookahead
section. In the lookahead section, the microprogram tests to determine if the current buffer it
is transmitting has been marked with the end of packet flag. If so, data chaining is not required.
The microprogram enters a wait loop for byte count overflow. If the end of packet flag is not
set, the microprogram attempts to obtain the next buffer descriptor status, address, and byte
count before entering the wait loop. When byte count overflow does occur, the microprogram
enters the descriptor update section. In the descriptor update section, the microprogram first
determines if an error has occurred or, simply, if data chaining must be performed. If an error
needs to be reported, an error status word is written into the ring descriptor prior to writing the
status word containing the "OWN" bit which releases the buffer. If no error is to be reported,
the single word containing the "OWN" bit is written. The microprogram returns to the polling
section if the "ENP" flag is found. Otherwise the microprogram returns to the lookahead section.
3.8.9
TRANSMIT DMA ROUTINE
This routine is entered through a microtrap in the lookahead section of the transmit routine.
The function of the routine is to move data out of local memory into the SILO. The trap is active
when there are 16 or more free locations in the SILO and SILO underflow has not occurred.
The routine pipelines the data through the Memory Data register while the address and byte
counts are incremented in the Control Data Path. A memory timeout will cause a trap. After a
maximum of eight (8) words have been transferred into the SILO, the routine is exited through
the URETURN register to the code section that originally trapped to this routine.
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3.8.10
COLLISION TRAP ROUTINE
This routine is entered when a collision has been detected while the transmitter is active. The
buffer address and byte counts are restored and the microprogram proceeds to the transmit
routine to reschedule the transmission. This is the rule if less than 15 retransmissions have occurred. If 15 retransmissions have occurred, the microprogram goes instead to the error reporting code in the descriptor update section.
3.8.11
CSR TRAP ROUTINE
The CSR trap routine is entered only during the switch routine when the STOP bit of CSRO is
set. The function of the routine is to allow the access of CSR1 and CSR2 through an 1/0
transaction. The routine determines which CSR is being accessed, read or written, moves the
data between the MDR and the CDP RAM, and generates a READY signal. The routine is exited through the URETURN register.
3.8.12
MEMORY TIMEOUT TRAP ROUTINE
This trap is invoked whenever a memory transfer times out. The routine sets the STOP bit of
CSRO and returns the microprogram to the start of the switch routine.
3.8.13
RETRY TRAP ROUTINE
This routine is entered when a collision has been detected. The buffer address pointer is restored
and the SILO is cleared to restore the READ and WRITE pointers. If there was a TX error, it
indicates that 15 retransmissions have occurred (16 total attempts) or that the Disable Retry bit
(DRTY) is set in the Mode register. The microprogram then writes the status into the transmit
descriptor ring.
If there was no TX error, the byte count is restored and the microprogram returns to the start
of the transmit routine to attempt another transmission.
3.8.14
DATA CHAIN
If Byte Count Equal 0 becomes true, it indicates that the receive buffer is full and the packet
is not yet finished, which is the data chain case. The microprogram updates the receive status
in the descriptor ring. It then checks the next OWN bit. If next OWN is false, which would be
the case if there was only one buffer or if there was more than one buffer but the chip did not
own the next one, the microprogram waits for RX Active to go false. This indicates that no more
data is arriving from the Ethernet. When RX Active goes false, the current RX OWN bit is cleared
because the ring entry has just been used for the updated receive status. The SILO is then
cleared to restore the READ and WRITE pOinters, RX Clear is issued and the microprogram
returns to the Polling routine.
If LANCE owned the next buffer, the current receive buffer parameters in the CDP Ram are
updated from the next receive buffer parameters that had previously been loaded into the CDP
Ram. The microprogram then checks for the end of the ring and updates the address pointers
accordingly. The microprogram then goes through the receive buffer lookahead microprogram
once to try to acquire another receive buffer if one is available. The microprogram finally returns
to the wait loop until either RX Done, SILO overflow or receive buffer overflow becomes true.
When RX Done or SILO Overflow occurs, the microcode sets the RINT bit in CSRO. The flow
from this pOint is the same as described elsewhere.
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CHAPTER 4
ELECTRICAL SPECIFICATIONS
4.0
ELECTRICAL SPECIFICATIONS
This chapter provides tabular presentations for Absolute Maximum Ratings, DC Characteristics, Capacitance,
and AC Timing Specifications. In addition, illustrations are provided for an Output Load Diagram and for Serial
Link, Bus Master, and LANCE Bus Slave Timing Diagrams.
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias .................................................... -25OC to +100OC
Storage Temperature ....................................................... -65°C to +150OC
Voltage on Any Pin with Respect to Ground ....................................... -.7 V to +7 V
Power Dissipation ................................................................... 2.0 W
Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
TA=OOC to 7Q°C, Vee = +5 V ± 5% unless otherwise specified.
SYMBOL PARAMETER
MIN
MAX
UNITS
V
V IL
-0.5
+0.8
V IH
+2.0
Vee +0.5
V
+0.5
V
±10
pA
VOL
@ IOL = 3.2 mA
V OH
@ IOH = -0.4 mA
IlL
@ V in = 0.4 to Vee
+2.4
V
CAPACITANCE
F=1 MHz
SYMBOL PARAMETER
MIN
MAX
UNITS
C IN
10
pf
C OUT
10
pf
CIO
20
pf
AC TIMING SPECIFICATIONS
TA = O°C to 70OC, Vee = +5 V± 5% unless otherwise specified.
TEST
CONDITIOS
NO. SIGNAL SYMBOL PARAMETER
MIN
(ns)
TYP
(ns)
MAX
(ns)
1
TCLK
TTCT
TCLK period
99
101
2
TCLK
TTCL
TCLK low time
45
55
3
TCLK
TTCH
TCLK high time
45
55
4
TCLK
TTCR
Rise time of TCLK
0
8
5
TCLK
TTCF
Fall time of TCLK
0
8
6
TENA
TTEP
TENA propagation delay after the
rising edge of TCLK
CL=50pf
7
TENA
TTEH
TENA hold time after the rising edge
of TCLK
CL=50pf
1-145
75
5
4·1
AC TIMING SPECIFICATIONS (CONTINUED)
TA = O°C to 70°C, VCC = +5 V± 5% unless otherwise specified.
TEST
CONDITIONS
NO. SIGNAL SYMBOL PARAMETER
TYP
(ns)
MAX
(ns)
75
8
TX
TTDP
TX data propagation delay after the
rising edge of TCLK
CL=50 pf
9
TX
TTDH
TX data hold time after the rising
edge of TCLK
CL=50 pf
10
RCLK
T RCT
RCLK period
85
5
118
11
RCLK
T RCH
RCLK high time
38
12
RCLK
T RCL
RCLK low time
38
13
RCLK
T RCR
Rise time of RCLK
0
8
14
RCLK
ReF
Fall time of RCLK
0
8
15
RX
TROR
RX data rise time
0
8
16
RX
T ROF
RX data fall time
0
8
17
RX
TRDH
RX data hold time (RCLK to RX
data change)
5
18
RX
T ROS
(See note)
RX data setup time (RX data stable to
the rising edge of RCLK)
See
Note
19
RENA
TOPL
RENA low time
120
20
RENA
TRENH
RENA Hold time after rising
edge of RCLK
40
21
CLSN
TCPH
CLSN high time
80
22 AlDAL
TOOFF
Bus master driver disable after rising
edge of HOLD
0
50
23 AlDAL
TOON
Bus master driver enable after falling
edge of HLDA
0
150
24
HLDA
THHA
25
RESET TRW
Delay to falling edge of HLDA from
ing edge of HOLD (Bus master)
fall·
0
RESET pulse width low
200
600
26 AlDAL
TCYCLE
Read/write, address/data cycle time
27 A
TXAS
Address setup time to the falling edge of
ALE
75
28 A
TXAH
Address hold time after the rising
edge of DAS
35
29
DAL
T AS
Address setup time to the falling edge of
ALE
75
30
DAL
TAH
Address hold time after the falling edge
of ALE
35
31
DAL
T ROAS
Data setup time to the rising edge of
DAS (Bus master read)
50
NOTE: TADS (min) ~ TACT -25ns i.e. TACT ~ 1oons, then TADS (min) ~ 75 ns.
4-2
MIN
(ns)
1·146
AC TIMING SPECIFICATIONS (CONTINUED)
TA = ooe to
70 oe, Vee
= +5 V± 5% unless otherwise specified.
TEST
CONDITIONS
NO. SIGNAL SYMBOL PARAMETER
MIN
TYP
MAX
(ns)
(ns)
(ns)
32 DAL
T ROAH
Data hold time after the rising edge of
DAS (Bus master read)
0
33 DAL
TOOAS
Data setup time to the falling edge of
DAS (Bus master write)
0
34 DAL
Twos
Data setup time to the rising edge of DAS
(Bus master write)
200
35 DAL
TWOH
Data hold time after the rising edge of
DAS (Bus slave read)
35
36 DAL
TSD01
Data driver delay after the falling edge of
DAS (Bus slave read)
(eSR
0,3, RAP)
400
'37 DAL
TSOO2
Data driver delay after the falling edge of
DAS (Bus slave read)
(eSR
1,2)
1200
38 DAL
T SROH
Data hold time after the rising edge of
DAS (Bus slave read)
0
39 DAL
TSWOH
~
setup time to the falling edge of
DAS (Bus slave write)
0
40 DAL
Tswos
Data setup time to the falling edge of
DAS (Bus slave write)
0
41 ALE
TALEW
ALE width high
120
42 ALE
TOALE
Delay from rising edge of DAS to the
rising edge of ALE
70
43 DAS
Tosw
DAS width low
200
44
DAS
TAOAS
Delay from the.!2!!J!lg edge of ALE to the
falling edge of DAS
80
45 DAS
T RIOF
Delay from the rising edge of DALO to
the falling edge of DAS (BUS master read)
15
46 DAS
T ROYS
Delay from the falling edge of READY
to the rising edge of DAS
47 DALI
T ROIF
Delay from the ris~dge of DALO to
the falling edge of DALI (Bus master read)
15
48 DALI
T RIS
~ setup time to the rising edge of
DAS(Bus master read)
135
49 DALI
TRIH
~I hold time after the rising edge of
DAS (Bus master read)
50 DALI
T RIOF
Delay from the rising edge of DALI to the
falling edge of DALO (Bus master read)
55
51 DALO
Tos
DALO setup time to the falling edge of
ALE (Bus master read)
110
52 DALO
T ROH
DALO hold time after the falling edge of
ALE (Bus master read)
35
53 DALO
TWOSI
Delay from the rising edge of DAS to the
rising edge of DALO (Bus master write)
35
1·147
Taryd=
300 ns
75
35
150
130
250
0
4·3
AC TIMING SPECIFICATIONS (CONTINUED)
TA = O°C to 7Q°C, Vee = +5 V± 5% unless otherwise specified.
TEST
CONDITIONS
NO. SIGNAL SYMBOL PARAMETER
54
4-4
CS
TeSH
CS hold time after the rising edge of DAS
(Bus slave)
55 CS
Tess
CS setup time
(Bus slave)
to
MIN
(ns)
TYP I MAX
(ns)
(ns)
0
the falling edge of DAS
0
56
ADR
TSAH
ADR hold time after the rising edge of
DAS (Bus slave)
0
57
ADR
TSAS
ADR setup time to the falling edge of
DAS (Bus slave)
0
58
READY
TARYD
Delay from the falling edge of ALE
to the falling edge of READY to insure a
minimum bus cycle time (600 ns)
59
READY
T SRDS
Data setup time to the falling edge of
READY (Bus slave read)
75
60
READY
TRDYH
READY hold time after the riSing edge of
DAS (Bus master)
0
61
READY
T SR01
READY driver turn on after the falling
edge of DAS (Bus slave)
(CSR 0,3, RAP)
600
62
READY
T SR02
READY driver turn on after the falling
edge of DAS (Bus slave)
(CSR 1,2)
1400
80
63 READY TSRYH
READY hold time after the rising edge of
DAS (Bus slave)
0
64 READ
TSRH
READ hold time after the rising edge of
DAS (Bus slave)
0
65 READ
T SRS
READ setup time
DAS (Bus slave)
to
the falling edge of
1-148
0
35
OUTPUT LOAD DIAGRAM
Figure 14
TEST
POINT
v""
R, = 1.2K
CR, -CR.
IN914 OR EQUIVALENT
CL = 100 pF MINIMUM AT 1 MHz
CR,
0.4 rnA
I
B
S_ERIAL LINK TIMING DIAGRAM - SIA I N T E R
SIGNALS
FA?CE
Figure 15
'2
_______
_1=='8 aff'6 '3
!l////JI!IJ!/II//////~
'7
15
,.
XL~/;~7/~I!/~M~I2~72~7/~7
jj,~//~!
I-lO~
~I+---. '9-----.1{
RENA~
CLSN
"
I\.
RCLK
RX
O
-t=.,=l'-
TCLK
TX
lENA
Timing measurements are made at t"'e following voltages, unless otherwise specified:
1-149
OUTPUT
INPUT
FLOAT
"1"
"0"
2,0 V
Q.SV
O.SV
O.SV
2.0V
V
4-5
BUS MASTER TIMING DIAGRAM
Figure 16
100
200
300
400
500
600
I
I
I
I
I
I
ALE
DALO-15
(WRITE)
DALO
(WRITE)
OALI
(WAITE)
READ
(WRITE)
CAL 0-15
(READ)
DALO
(READ)
DAU
(READ)
READ
(READ)
BMO.1
NOTE:
The Bus Master cycle time will increase from a minimum of 600 ns in 100 ns steps
until the slave device returns REAnV.
4-6
1-150
LANCE BUS SLAVE TIMING DIAGRAM
Figure 17
-1 55 ~
-rlr
B~~!_ _ _ _ _ _ _ _ _ _ _ _
-.21'· ~
ADA
-1, .. t __
~5ft:
wa
, ~rTT7/!;"TTT1/!;"TTrm
1 - - - - - 81 ,62 - - - - I
-59
READ
(READI
OAlO·15
lREADI
DATA OUT
--16'~
~'I
(WAIT"~
READ
DALQ.'5
(WRITE)
~
I
DATA IN
+J=r----~rI
II
1-151
4-7
1·152
il:['hj&i']~1
COMPONENTS
COMMUNICATIONS PRODUCTS
~-~~---------
-----~--------------------------------MOSTEK
APPLICATION
NOTE
MK68590 (LANCETM)
INTERFACE TO MK68000
1-153
1·154
TABLE OF CONTENTS
PARAGRAPH
TITLE
PAGE
1.0
Introduction .................................................................................................................................. 1-1
2.0
Ethernet Primer ........... ................. ....... ........................... ....................................... .......... ... ......... 2-1
3.0
Definition of Terms ...................................................................................................................... 3-1
4.0
LANCE Chip Description ............................................................................................................. 4-1
5.0
5.1
5.2
5.2.1
5.2.2
5.3
5.4
5.5
5.6
Ethernet Node Overview .............................................................................................................. 5-1
Introduction ......... ... .................................................. ........................ .... .................... ........ ........... 5-1
Operational Description ............................................................................................................... 5-1
Typical Ethernet Node ................................................................................................................. 5-1
Application-Note Ethernet Node ................................................................................................... 5-1
Hardware Requirements .............................................................................................................. 5-2
Software Requirements ............................................................................................................... 5-3
System Memory Map .................................................................................................................. 5-4
Utility Area Definition ................................................................................................................... 5-7
6.0
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Hardware Description ...................................................................................................................
Introduction .................................................................................................................................
Chip Select Decode Circuit .........................................................................................................
DTACK Circuit .............................................................................................................................
Address/Data Bus Interface .........................................................................................................
Interrupt Circuit ...........................................................................................................................
Autovectoring Circuit .................................... ..................... ..........................................................
Bus Arbitration Circuit .................................................................................................................
SIA-LANCE Interconnect .............................................................................................................
7.0
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.6.1
7.2.6.2
7.2.7
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.4.1
7.3.4.2
7.3.5
7.4
Software Description .................................................................................................................... 7-1
Introduction .................................................................................................................................. 7-1
Initialization and Diagnostics Software Module ............................................................................ 7-2
Introduction ................................................................................................................................. 7-2
Clear Submodule ......................................................................................................................... 7-3
Block-Move Submodule ............................................................................................................... 7-4
Receive Ring Initialization Submodule ......................................................................................... 7-6
Transmit Ring Initialization Submodule ........................................................................................ 7-8
Diagnostics Software Module ...................................................................................................... 7-10
CRC Code Software Generation ................................................................................................. 7-13
Code Status Register Initialization Subroutine ............................................................................ 7-13
Normal Operation Initialization .................................................................................................... 7-15
LANCE Interrupt Exception Software Module .............................................................................. 7-17
Introduction ................................................................................................................................. 7-17
Interrupt Error Determination Submodule .................................................................................... 7-18
Transmit Interrupt Handling Submodule ....................................................................................... 7-20
Receive Interrupt Handling Submodule ....................................................................................... 7-22
Loopback Handling Routine ........................................................................................................ 7-26
Receive Interrupt Normal Operation ............................................................................................ 7-26
Initialization Done Interrupt Handling Submodule ........................................................................ 7-28
Message Interrupt Software Module ............................................................................................ 7-29
8.0
8.1
8.2
8.3
Appendices
Appendix A,
Appendix B,
Appendix C,
6-1
6-1
6-1
6-3
6-4
6-6
6-6
6-7
6-8
................................................................................................................................. 8-1
Initialization Assembly Code .................................................................................... 8-1
LANCE Interrupt Assembly Code ............................................................................ 8-15
Message Interrupt Assembly Code .......................................................................... 8-27
1-155
LIST OF ILLUSTRATIONS
FIGURE
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
PAGE
TITLE
OSI Network Model ........................................................................................................................ 2-2
Ethernet and LANCE Packet Format ............................................................................................... 4-1
Ethernet and Packet Bit Transmission Sequence ............................................................................ 4-1
LANCE Memory Management '" ..................................................................................................... 4-2
68000/68590 Block Diagram .......................................................................................................... 5-2
Program Software Overview Flowgraph .......................................................................................... 5-3
System Memory Map ..................................................................................................................... 5-5
Utility Area Memory Map ................................................................................................................ 5-6
Ring Management Area Memory Map ............................................................................................ 5-8
Chip Select Decode & DTACK Circuit ............................................................................................. 6-1
Chip Select Decode Description ..................................................................................................... 6-2
Chip Select Decode PROM Firmware ............................................................................................ 6-3
MK68000 - Memory Interface Circuit .............................................................................................. 6-4
Address/Data Bus Interface Circuit ................................................................................................. 6-5
Interrupt and Autovector Circuit ...................................................................................................... 6-6
Bus Arbitration Circuit .................................................................................................................... 6-7
Bus Arbitration Timing .................................................................................................................... 6-7
SIA Filter Values ............................................................................................................................ 6-8
Software Memory Map .................................................................................................................... 7-1
Initialization Software Module ......................................................................................................... 7-2
Clear Submodule ............................................................................................................................ 7-3
Block-Move Submodule .................................................................................................................. 7-4
Buffer Displacement Diagram ......................................................................................................... 7-5
Receive Ring Initialization Submodule ............................................................................................ 7-7
Transmit Ring Initialization Submodule ........................................................................................... 7-9
Diagnostics Subroutine .................................................................................................................. 7-10
Loopback Diagnostics Test Routine ................................................................................................ 7-11
Cycle Redundancy Check Generation Subroutine .......................................................................... 7-13
Control & Status Register Initialization Subroutine ......................................................................... 7-14
Normal Operation Initialization Submodule .................................................................................... 7-16
LANCE Exception Processing Module ............................................................................................ 7-17
Interrupt Error Determination Submodule ....................................................................................... 7-19
Transmit Interrupt Handling Submodule ......................................................................................... 7-21
Receive Interrupt Handling Submodule .......................................................................................... 7-23
Loopback Service Routine ..................................................................................,.......................... 7-25
Packet Status Discrepancy Check Routine .................................................................................... 7-27
Initialization Done Interrupt Handling Submodule .......................................................................... 7-28
Message Interrupt Software Module .............................................................................................. 7-30
Transmit Ring Update Submodule ................................................................................................. 7-32
1-156
1.0 INTRODUCTION
The LANCEm Application Note describes the basic hardware and software needed to interface the.MK68590, Local
Area Network Controller for Ethernet (LANCE), to the MK68000, Mostek's 16/32 microprocessor. It can be used
as a "cookbook" for designing the basic hardware and software needed for a LANCE-68000 interface, but is actually more useful as a design guide.
This publication contains seven sections in addition to this introduction. Section two is the Ethernet Primer, which
contains background material and basic concepts involved in Ethernet communication. Section three defines terms
used throughout the Application Note. Section four is an overview of the Local Area Network Controller for Ethernet (LANCE) chip. Section five is the Ethernet Node overview, listing design requirements for an intelligent Ethernet node. It deals with the block level concepts of both hardware and software. Section six is the Hardware
Description. It deals with the basic hardware requirements and includes both block diagrams and schematics. Section
seven describes the software used in the LANCE-MK68000 interface. This section includes flowcharts, assembly
code, and a step-by-step explanation of the software. The eighth and final section is a Assembly Code listing of
the software needed for an intelligent Ethernet node.
The LANCE-MK68000 hardware and software were designed as simply as possible. The design incorporates a
minimum number of interface logic gates and no time multiplexing of devices. Structured assembly code with few
subroutines and loops is used, making it easy to change and understand. The schematics and assembly code
are presented in a format that easily lends itself to a self-tutorial on an existing Ethernet interface design for users.
The design is intended to give users ideas on how to design or how to improve present designs. But, if so desired,
users can apply the information directly to quickly generate a basic working interface.
This Application Note refers to many technical aspects of the LANCE but they are not fully explained. For this
reason, users should also study the MK68590 LANCE Technical Manual, published by United Technologies Mostek.
LANCE is a trademark of Mostek Corporation.
1-157
1-1
1-158
2.0 ETHERNET PRIMER
Much debate and questioning as to the nature of celestial bodies existed in the early days of science. These questions included: What type of material exists between the heavenly bodies? If it is not a vacuum, how does light
move across it? The conclusion agreed upon was that an Ether existed between the planets and it was the medium
light used to travel from the sun to the Earth.
Xerox borrowed this terminology in their early stages of defining a local area network. Ether was the medium information would use to travel from one station to the next throughout the network specification. They called this network "Ethernet."
Ethernet was designed as a system for local communication between computing stations. A series of tapped coaxial cables between computing stations comprise a network that connects up to 1024 different stations per network.
In addition, a gateway interface may be used to connect each network to other networks. The computing stations
may consist of personal computers, CAD workstations, file storage devices, magnetic tape backup stations, large
central computers, printers, plotters or any device that conforms to the Ethernet standard.
The objective of Ethernet was to provide a communication system that can grow with users' needs and accommodate several buildings in a local area. One of its purposes is to eliminate bottlenecks and reliability problems
associated with a central controller.
Ethernet provides for one, and only one, connection between any two pOints on the network. Since the Ether, or
the common broadcast communication channel, is passive when an active node fails, only its operation is affected
- not the entire system.
Ethernet employs Carrier Sense Multiple Access with Collision Detect (CSMAlCD). The principle behind this operation
is similar to human conversation. If several people are conversing while standing in a circle (assuming it is a noncontroversial discussion between polite adults), only one person speaks at a time. When the first person finishes,
someone else begins to speak and continues until he or she is also finished. If no one has anything else to say,
silence falls over the group.
The same is true for Ethernet. Each node listens until the network becomes silent. Then, if a message needs to
be transmitted the node broadcasts onto the Ether and the remaining nodes listen.
The more people in the circle, and the more they have to say, the greater the chance that two or more people
will begin speaking simultaneously. If this happens in normal conversation, all the participants who have started
speaking will stop and whoever begins to speak first will be able to say what he has to say. Two or more people
may occaSionally begin speaking again at the same time, in which case, they will again stop talking and, hopefully,
the more gracious member of the group will wait. When a person starts talking, no one else begins until that person finishes. Delays and collisions occur in Ethernet just as they do in normal conversation. Due to the propagation delays encountered in the medium, a station may not sense network activity and begin transmitting. Once
it begins, it keeps listening to the network; if it detects a collision, it aborts the transmission and waits a certain
amount of time determined by a random number generator.
In any given group of people, some are naturally talkers while others are listeners. If the conversation does not
concern them, the listeners are less likely to pay attention. The same is true with Ethernet stations. Some stations,
such as personal computers, transmit much information and others, such as printers, do much of the receiving.
A particular station's Ethernet interface connects bit-serially through an interface to a transceiver that taps into
the passive Ether. The Ethernet station, or node, broadcasts its message into the passive Ether, enabling all nodes
on the network to hear it. All stations receive the message and determine if they are the desired destination. If
the transmitting node's destination address matches that of the receiving node, the packet is accepted and the
station digests the data. If the address does not match, the receiving node rejects the packet.
A station may use two addressing schemes when broadcasting. The first is the physical addreSSing scheme, whereby
the transmitting station addresses one, and only one unique destination station. As long as all stations on the network are not in the promiscuous mode, only one station accepts the message.
The second adddressing scheme uses a logical address. In this operation, stations receiving the message must
1-159
2-1
determine if they are one, of possibly many, intended recipients. An example of logical addressing is one in which
all printers have the same logical address. If people want to send memos via the printers, they simply set the destination as the logical address - "printers." All printers on the network then see themselves as the destination and
all accept the message. In addition, a station may set itself up in a promiscuous mode. In this mode, the station
accepts all incoming messages, no matter what destination address the message has.
When Xerox defined Ethernet, their intent was to define a standard that all manufacturers who wanted access to
the Ether, could use. They wanted to define a rigorous standard from the onset to avoid incompatability. Universal
acceptance of a standard is the very key to practical applications of local area networking. The International Standards Organization (ISO) has approved a layered protocol standard that specifies functions, as well as minimal
rules for accessing these functions and for information exchange between devices on the network. This sevenlayer architecture logically groups functions and provides conventions for connecting functions between layers.
The model, shown in Figure 1, is called the Open Systems Interconnection (OSI) network model.
INTERFACES
WITH HOST
OPERATING
SYStEM
HIGHER
LEVEL
PROTOCOLS
(RESPONSIBILITY
OF HOST SYSTEM)
LOWER LEVEL
{
PROTOCOLS
(RESPONSIBILITY
OF NETWORKS)
Figure 1. OSI Network Model
2·2
1-160
The bottom three layers of the OSI model include the physical, data-link control, and network layers. Hardwartj
is based on the actual definition of the two lower layers. Specifications in these layers include the transmission
medium (Ether) and how the node must interface to the Ether. The physical and data-link control layers also specify
how information should be formatted for error-free transmission and reception. Each layer supports another in hierarchial fashion. In other words, layer 1 serves layer 2, layer 2 serves layer 3 and so forth. The three bottom layers
differ according to network architecture. The top three layers - session, presentation, and application - are the
same for all networks. The transport layer is the interfacing layer between the top three and bottom three layers.
The functions of each layer of the OSI model follow.
Physical Layer:
• Handle cables, connectors, and components
• Handle collision detection for CSMAlCD
• Handle voltages and electrical pulses
Data Link Control Layer:
• Make sure data is not mistaken for flags
• Add error checking algorithms
• Insert flags to indicate beginning and end of messages
• Provide access methods for local area networks
Network Layer:
• Internetworking
• Send control messages to peer layers about own status
• Set up routes for packets to travel (virtual circuit)
• May disassemble transport messages into packets and reassemble them at their destination
• Flow control
• Recognize message priorities and send messages in proper priority order
• Address network machines on the route through which the packets travel
Transport Layer:
• Multiplex end-user addresses onto network
• Monitor quality of service
• End-to-end error detection and recovery
• Address end user machines without concern for route of message or address machines in route between end
user machines
• Possible disassemble and reassemble session messages
• Map address to names
Session Layer:
• Send information from one task to another
• Coordination and cooperation between end users tasks
• Start and stop tasks
• Dialog control
• Recovery from communication problems during a session without losing data
Presentation Layer:
• Encoding and decoding
• Data compaction
• Syntax transformation for character sets, text string, data display formats, graphics, file organization, data types
Application Layer:
• Log in
• Password checks
• Color control
• Graphics procedures
• Downline loading
• Creation of charts and displays
• File requests and file transfers
1-161
2-3
•
•
•
•
•
•
Remote job entry
Computer based message systems
Job minipulation
Virtual terminal service
Data-based queries, insertions, and deletions
User specific applications (e.g. editing, word processing, electronic funds transfer, airline reservation, and transaction processing)
The LANCE, together with the SIA, Transceiver, and Coaxial cable satisfy the specifications in the bottom two layers
of the ISO model. By adding the software shown in this Application Note, layers 1, 2, and 3a can be satisfied.
2-4
1-162
3.0 DEFINITION OF TERMS
DMA Capability: The ability to directly access memory or memory-mapped I/O. This includes reading, writing,
and control signal generation.
Peripheral: A processing unit attached to the system bus which handles part of the processing load.
Bus Master: A CPU or DMA device that has gained control of the system bus. It can initiate data transfers on
the bus by issuing an address and by driving the read/write, address strobe, and data strobe control Signals.
Bus Slave: A device that decodes the address, read/write, address strobe, and data strobe control signals and
responds ac'oordingly for a read or write operation.
Bus Arbitration: In a system with more than one device capable of being the Bus Master, a bus arbitration convention must be employed to determine which device may take control of the system bus at anyone time. Normally
one of the Bus Master type devices is responsible for receiving and granting requests for access to the system bus.
Front End Processor: A processor microsystem, usually consisting of a microprocessor, or single-chip microcomputer, along with memory and control logic. This microsystem alleviates some of the burden placed on the main
host processor. The front end processor acts as an intermediate stage of processing between the host processor
and an I/O device.
Intelligent Ethernet Node: An Ethernet node that acts as a front end processor to the host processor. An intelligent
Ethernet node would basically consist of microprocessor or microcomputer, memory, an Ethernet protocol device
(LANCE), transceiver interface device (SIA), and the associated firmware required to implement the lower layers
of the Ethernet protocol.
1-163
3-1
1·164
4.0 LANCE CHIP DESCRIPTION
The MK68590 LANCE (Local Area Network Controlier for Ethernet) is a 48-pin VLSI device that simplifies interfacing a microcomputer or minicomputer to an Ethernet Local Area Network (LAN). This chip operates in a local environment that includes a closely coupled memory and microprocessor. The LANCE uses scaled N-channel MOS
technology and is compatible with several popular microprocessors. It interfaces to a microprocessor bus characterized by time-multiplexed address and data lines. Typically, data transfers are 16 bits wide, but byte transfers occur
if the buffer memory address boundaries are odd. The address bus is 24 bits wide.
The Ethernet packet format consists of a 64-bit preamble, a 48·bit destination address, a 48-bit source address,
a 16-bit type field, and a 46- to 1500-byte data field terminated with a 32-bit CRC (cyclic redundancy check) as
shown in Figures 2 and 3. The packet's variable widths accommodate both short status, command and terminal
traffic packets, and long data packets to printers and disks (1024 byte disk sectors, for example). Packets are spaced a minimum of 9.6 usec apart to allow one node time enough to receive back-to-back packets.
~14~--------------PACKET--------------~·~1
I - - - C R C COVERS THESE FIELDS----.I
-.../
I.-
MINIMUM PACKET SPACING (96 BIT TIMES)
"LAST BYTE IS START OF FRAME SYNCHRONIZATION BYTE··10101011
Figure 2. Ethernet and LANCE Packet Format
r - - 1 BYTE----!
PHYSICAL/MULTICAST BIT-+
6 BYTES
""'
DESTINATION
6 BYTES
SOURCE
2 BYTES
TYPE
46·1500 BYTES
DATA
4 BYTES
LSBI
OCTETS WITHIN
FRAME TRANSMITTED
TOp·TO·BOTTOM
FRAME CHECK
SEQUENCE
I I I I I I I
IMSB
LOCT:t:R~~~~~TTED - +
LEFT·TO·RIGHT
Figure 3. Ethernet and Packet Bit 1l'ansmlsslon Sequence
1-165
4·1
The LANCE operates in a minimal configuration that requires close coupling between local memory and a processor. The local memory provides packet buffering and is a communication link between the chip and processor.
During initialization, the control processor loads the starting address of the initialization block plus the operation
mode into the LANCE via two control registers. The host processor talks directly to the LANCE only during this
initialization as a Bus Slave peripheral. The LANCE's DMA machine, under microword control, handles all further
communications.
The LANCE on-chip DMA channel provides flexibility and speed by communicating with the host, or dedicated
microprocessor, through common memory locations. Buffer management is organized by a circular queue of tasks
in memory called "descriptor rings" (see Figure 4). Separate descriptor rings describe transmit and receive operations. Up to 128 tasks may be queued on a descriptor ring for future execution. Each entry in a descriptor ring
holds a pOinter to a data memory buffer and an entry for the data buffer length. Data buffers can be chained or
cascaded to handle a long packet in multiple data buffer areas. The LANCE searches the descriptor rings in a
"look-ahead manner" to determine the next empty buffer for chaining buffers together or handling back-to-back
packets. As each buffer is filled, an "own" bit is reset, signaling the host processor to empty this buffer.
LANCE CSR REGISTERS
rliOINTER TO INITIALIZATION
BLOCK
RECEIVE BUFFER
I
RECEIVE DESCRIPTOR RINGS
~
~f"':
~t:::
[:::f"':
4-
•••
•
r;:v
LOGICAL ADDRESS FILTER
~
VA
POINTER TO RECEIVE RINGS
NUMBER OF RECEIVE ENTRIES
POINTER TO TRANSMIT RINGS
~"""
0
----
_ _ _ _ r--oAi=A
,
l;::v
~~
PHYSICAL ADDRESS
BUFFER 0 BYTE COUNT
',
vb::
MODE OF OPERATION
BUFFER 0 STATUS
V
~v
INITIALIZATION
BLOCK
ADDRESS OF RECEIVE BUFFER 0
PACKET
N
PAC,KET
'----;-
··
r-
N
'--TRANSMIT DESCRIPTOR RINGS
~
f§
~
§§
~
~
TRANSMIT BUF FER
_ _ _ _ r--oAi=A
~p
::?""
~
~
PACKET
N
N
t---
NUMBER OF TRANSMIT ENTRIES
-~
ADDRESS OF TRANSMIT BUFFERS 0
PAC:ET
BUFFER 0 STATUS
BUFFER 0 BYTE COUNT
,,
,
••
••
N
N
N
'---
'!iATA"
,
- - PACKET
~
·
·
----r-;i;;PACKET
N
---Figure 4. LANCE Memory Management
4-2
1-166
5.0 ETHERNET NODE OVERVIEW
5.1 INTRODUCTION
The LANCE has two basic types of micro·interfaces. The first is when the LANCE acts as a peripheral to a host
processor and the second is when the LANCE and a dedicated microprocessor or microcontroller work together
to form an intelligent node. In the second type, all processing between the processor and the LANCE occurs on
a local bus, while the entire node interfaces to the main system bus as an intelligent subsystem.
The LANCE parallel interface is designed to be an easy or "friendly" interface to several popular 16-bit microprocessors. This Application Note addresses MK68000 interface requirements, but the concepts can be applied to other
microprocessors.
5.2 OPERATIONAL DESCRIPTION
The following two sections are operational descriptions of a typical intelligent Ethernet node controller design, and
the Ethernet node controller design used to generate this Application Note.
5.2.1 TYPICAL ETHERNET NODE
An intelligent Ethernet node's primary function is to unburden the host processor from many networking tasks and,
at the same time, reduce system bus congestion by eliminating the need for the LANCE to ever access the system
bus.
A typical intelligent node performs node initialization and self tests, as well as transmitting and receiving messages. It also retains statistical records of error-causing conditions and generates time-out interrupts. These timeout
interrupts are used for both memory refresh and upper-level protocol requirements.
The software of the intelligent node isolates the higher level user software from node details, such as memory
refresh and the LANCE interface.
In a typical system, an intelligent Ethernet controller may be designed and placed on a separate system board.
The LANCE chip permits placement of the entire Ethernet controller on a single system board because it reduces
the chip count. This board would interface to a particular bus structure, i.e., the VME, Versabus m , Multibus'", etc.
The system host procesor may interface to the node processor via a dual-ported memory with the use of semiphores.
5.2.2 APPLICATION-NOTE ETHERNET NODE
The Ethernet node controller design discussed in this Application Note does not have the characteristics of a typical intelligent Ethernet controller. It was designed more as a demonstration and teaching tool. The only software
written for the node is the lower level software included in the Appendix.
This design uses a total of 8K bytes of memory. A greater quantity of memory would be present in a typical intelligent Ethernet node design. This design has no memory refresh requirements since static RAMs are used instead
of dynamic RAMs.
This design includes a "message send request" button that users depress to send data messages to any desired
node. The push button simulates a message request that the system host processor would normally generate.
The button idea is only used on the breadboard for controlled message transfer for debug and demonstration
purposes.
Depressing the button interrupts the local processor and calls a message routine. This message routine generates
a pseudo message and updates the transmit descriptor so proper transmission can occur. Immediately after pushing the button, users can examine the memory to verify message transmission and proper hardware and software
operation. The pushbutton was felt to be the best way to demonstrate message generation.
Aside from these few differences, the Ethernet node design used in this publication is functionally the same as
a typical design used in industry.
Versabus is a trademark of Motorola, Inc.
Multibus is a trademark of INTEL Corp.
1-167
5·1
5.3 HARDWARE REQUIREMENTS
As the Bus Master, the LANCE has a wide 24-bit linear address space it can access directly via OMA. This 24-bit
address bus interfaces directly to the MK68000's 24-bit bus. The only provision is that latches must be placed
on the multiplexed address/data bus to latch up the address at the start of a read or write cycle when the LANCE
is the Bus Master. Only the lower 15 bits must be latched up; the upper eight bits can be interfaced directly. When
interfacing to the MK68000, BM1 and BMO correspond to upper data strobe (UOS) and lower data strobe (LOS).
Address bit AO is not used in the basic MK68000 interface.
The basic blocks of this design include the LANCE, MK68000, memory, bus arbitration circuitry, chip select circuitry, and OTACK circuitry. Figure 5 is a block diagram of this interface.
'.
RESET
MK68000
RESET
MK68590
RESET
RESET
CONTROL
IPLO
-MESSAGE INTR.
INTERRUPTI
IPL1
IPL2
DTACK
DTACK
GEN
BG.
READY
HOLD
BUS
ARBITRATION
BR
BGACK
__
TENA
HLDA
RCLK
_CLSN
BMO TX
BM1RENA
CS
ADR
I
I
R/W
LOS
~
CS
DECODE
rv'
AS
A(1-23)
2
f--
READ
~DDRESSBUS
DATA BUS
cs
ADD
A
(16-23)
t
LL
I
A
0(0-15)
NC- DALO
I
t
r-
ADD
LATCH
lJ---
11
mJ.I
RJW
MEMORY
o
Figure 5. 68000/68590 Block Diagram
5-2
TCLK
ALE
SEL 2
1-168
----'\
---...
RX ' + -
NC- DAL1
UDS
-------
DAL
(0-15)
TO
SIA
The memory includes 8K bytes of random access memory (RAM) and 4K bytes of erasable programmable read
only memory (EPROM). The EPROM contains the Ethernet node program, while the RAM is used for receive and
transmit rings as well as stack area.
Section 6 -
Hardware Description gives a detailed hardware description.
5.4 SOFTWARE REQUIREMENTS
The software program has three functions:
1. Initialize the LANCE
2. Perform message ring management
3. Keep track of the error- and flag-causing conditions.
The software acts as an intermediate stage between the higher-level software protocol of the system host processor
and the lower-level protocol implemented by the LANCE. Figure 6 shows the main flow of the software.
LANCE
INTERRUPT
SERVICE
MESSAGE
INTeRRUPT
SERVICE
STATISTICAL
KEEPING
SUBROUTINES
Figure 6; Program Software Overvi_ Flowgraph
1-169
The initialization and diagnostics are implemented upon powerup. Users may set up the diagnostics submodule
to be implemented any time they desire an operational check. The two service modules - LANCE Interrupt and
Message Interrupt - are both interrupt-driven.
The LANCE Interrupt service routine is called when the LANCE interrupts the local processor. The LANCE interrupts the processor when a message is received or transmitted, initialization is complete, or an error has occurred.
The error- or flag-causing condition is determined by reading the Control and Status Registers zero (CSRD). The
processor then either services the flag-raising condition or calls one of the statistical-keeping subroutines. It then
simply reports the condition to the system processor.
It is not necessary for the LANCE to operate on an interrupt-driven basis. The processor may be programmed
to periodically poll the Control and Status Registers zero (CSRD) for flag-causing conditions. This Application Note
performs the function on an interrupt basis to eliminate the need for a timer.
The message interrupt service routine is called when users depress the "message request" button. The routine
generates a pseudo message depending on what parameters users give it. It then writes the message into a transmit message buffer and updates the transmit message descriptor.
As stated before, the "Push-button" operation is not included in a typical Ethernet node processor, but appears
here to give the reader possible suggestions on how to write required software for servicing an actual systemgenerated message.
5.5 SYSTEM MEMORY MAP
All software activities take place in the low end of memory. The entire program uses less than 2K bytes of memory.
Figure 7 is a memory map of the space this program uses.
5·4
1-170
$0000
VECTOR SPACE
$0400
INITIALIZATION
MODULE
EXCEPTION
MODULE
PROGRAM
SPACE
PROM
SELECT
MESSAGE
MODULE
ERROR HANDLING
SUBROUTINES
L-
$2000
MESSAGE
MANAGEMENT
AREA
'""
INITIALIZATION
BLOCK
RECEIVE
MESSAGE
DESCRIPTORS
TRANSMIT
MESSAGE
DESCRIPTORS
RAM
SELECT
RECEIVE
BUFFERS
TRANSMIT
BUFFERS
UTILITV{
AREA
$4000 ~-------I
}
LANCE
SELECT
Figure 7. System Memory Map
1-171
5·5
Memory area from hex address $0000 to $03FF is reserved for vectors. The program resides in the memory space
bounded by addresses $0400 and $1FFF. Message management memory space is between $2000 and $3878.
This area contains the initialization block and the receive and transmit message descriptors, along with the receive
and transmit ouffers. The memory space between addresses $387C and $3FFF is the utility area. The program
stack, ring management, and error flags reside here. Figure 8 gives a detailed map of the utility area.
$2000 r---::T=R":'A~NS~M~I=T~"""
AND RECEIVE
RING AREA
$387C
68 BYTES
SYSTEM STACK
64 BYTES
RING MANAGEMENT
ERR~~R"; ~~:TUS
FLAG AREA
RECEIVE
MESSAGE
OUTPUT
AREA
TRANSMIT
MESSAGE
WAITING
AREA
-
$3FFF
Figure 8. Utility Area Memory Map
5·6
1·172
Memory location $4000 is the address of the LANCE's register data port (RDP). Memory location $4002 is the
address of the LANCE's register address port (RAP).
The receive and transmit ring length, as well as their buffer sizes, are all variable. These variables may be altered
by changing an equate statement at the beginning of the program. This Application Note uses eight receive descriptors and four transmit buffers. The size for both transmit and receive buffers is 256 bytes. There are twice as many
receive buffers as transmit buffers because it is undesirable for the node to miss an incoming packet due to a
lack of receive buffers.
5.6 UTILITY AREA DEFINITION
The utility area is composed of the following:
1. 68 bytes of system stack
2. 64 bytes of ring management variables
3. 32 bytes of error and status flag area
4. 620 bytes for message area.
The message storage area is to be used for receive message output and transmit message waiting area. A ring
management stack or status area is set aside in memory to record all transmit and receive descriptor ring activity.
Figure 9 gives the address location and describes the information in that memory location.
The addressing mode to access all ring management locations is "Address Register Indirect with Displacement".
Base address $38CO is placed in register A4 upon initialization. The displacements are all defined in the equate
statements at the beginning of module number one (see Software listing in the Appendix).
The ring management area has several pOinters. Some point to the top and bottom of the descriptor rings. Others
point to the next-descriptor to be used and the last-descriptor used. The complicated task of message management is controlled by using these pOinters and other status information in the ring management area.
1-173
5·7
ADDRESS
DESCRIPTION OF CONTENTS
38CO
38C2
38C4
38C8
38CC
38DO
RECEIVE RING LENGTH Number of entries in the receive ring
TRANSMIT RING LENGTH Number of entries in the transmit ring
RECEIVE RING BASE ADDRESS POINTER This paints to the firsi receive message descriptor
TRANSMIT RING BASE ADDRESS POINTER This paints to the first transmit message descriptor
RECEIVE RING BOTlOM ADDRESS POINTER This points to the last receive message descriptor
TRANSMIT RING BOTlOM ADDRESS POINTER This points to the last transmit message
descriptor
LAST RECEIVE DESCRIPTOR USED POINTER This paints to the last receive descriptor to be
used. When the LANCE interrupts the host because of a received message, this painter will indicate which ring corresponds to the message. If more. than one buffer was required for the incoming
message, than one buffer was required for the incoming message, this painter will point to the first
descriptor used.
LAST TRANSMIT DESCRIPTOR USED POINTER This points to the last transmit descriptor turned
over to the host by LANCE. When LANCE interrupts the host because it has just transmitted a message, this pointer will indicate the descriptor just used.
NEXT TRANSMIT DESCRIPTOR TO BE USED POINTER This points to the next transmit message descriptor available for use. The "number of rings available" must be checked before the next
ring is accessed. If there are "0" rings available the Next Transmit Pointer will be pointing to a ring
which has not been serviced by LANCE.
LOOPBACK MESSAGE COUNT This contains the number of bytes contained in the loopback message. This is not used in diagnostics
TRANSMIT DESCRIPTOR COUNT number of descriptors that are available
RING MANAGEMENT STATUS
BIT #1
"1" indicates that LANCE is in LOOPBACK Mode
BIT #2
"1" indicates that the START OF PACKET bit was set before
BIT #3
"1" indicates that the END OF PACKET bit was set before
BIT #4
"1" indicates that the program is in DIAGNOSTIC Mode
BIT #5
"1" indicates that this portion of the TEST IS COMPLETE
BIT #6
NOT USED
BIT If7
NOT USED
LOOPBACK TRANSMIT BUFFER ADDRESS POINTER
MORE COUNTER keeps count of the number of times more than one retry was needed to transmit
a packet
ONE COUNTER keeps count of the number of times exactly one retry was needed to transmit a
packet
MESSAGE WORD used for testing and debugging
38D4
38D8
38DC
38EO
38E2
38E4
38E8
38EC
38EE
38FO
Figu~
5-8
9. Ring Management Area Description
1-174
6.0 HARDWARE DESCRIPTION
6.1 INTRODUCTION
The circuit described in this Application Note has a minimal amount of logic for interfacing the MK6800D to the
LANCE. Figure 5 is a block diagram of the circuit.
The basic interface blocks consist of the following:
1. Chip select decode and DTACK (Data Transfer Acknowledge) generation
2. Address/Data bus interface
3. Interrupt - autovector
4. Bus arbitration blocks.
Detailed schematics of these blocks are given in Figures 10 through 16.
6.2 CHIP SELECT DECODE CIRCUITRY
The Chip Select Decode circuit consists of five logic gates and a Bipolar Programmable Read Only Memory (PROM)
as shown in Figure 10. The circuit output enables both the RAM and EPROM, as well as enabling the LANCE.
When the LANCE is the Bus Slave and the MK68000 needs to access one of its control-status registers, the LANCE
is enabled. As Bus Masters, either the MK68000 or the LANCE can access memory. The DTACK circuitry uses
the output signals, RAM SELECT and ROM SELECT. They generate the needed DTACK and READY signals for
the MK68000 and the LANCE, respectively.
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14t--------50 tLh
5100
680 pF
I
I
I
I
I
I
I
I
'ct'
'ct'
•
Vee
6·8
'tr;'
•
•
TRANSMIT +
48
21
SIA
MK68581
LANCE
Vee
22
7.0. SOFTWARE DESCRIPTION
7.1 INTRODUCTION
The software needed to generate a basic interface between the LANCE and the MK68000 is described in three
different formats: a written description of the step-by-step process, flow charts of the individual submodules, and
a printout of the actual assembly code. The assembly code appears in Appendices A, B, and C.
Users should read the software description along with studying the flow charts and assembly code. This triple
reinforcement should make it easier to comprehend software requirements.
The software has four basic modules, as shown in the memory map of Figure 19. They include: Initialization &
Diagnostics, LANCE Interrupt, Message Interrupt, and Status Module.
HEX ADD
$0000
~
VECTOR
SPACE
~
$0400
INITIALIZATION
MODULE
AND
DIAGNOSTICS
$0800
LANCE
INTERRUPT
HANDLING
MODULE
$0800
$OCOO
IVIESSAGE
GENERATION
MODULE
STATUS
HANDLING
~UTIN;:""
Figure 19. Software Memory Map
1-183
7-1
7.2 INITIALIZATION & DIAGNOSTICS SOFTWARE MODULE
7.2.1 INTRODUCTION
The Initialization & Diagnostics Module, as shown in Figure 20, contains six submodules:
1. Clear
2. Block-Move
3. Receive Ring Initialization
4. Transmit Ring Initialize
5. Diagnostics
6. Normal Initialize.
The diagnostics portion is actually a subroutine. Diagnostics may be performed at any time by simpling calling
this subroutine.
.
In addition to these six submodules are two subroutines: Control and status Register Initialization Subroutine, and
the Cyclic Redundancy Check Subroutine.
MOVE INITIALIZATION
BLOCK FROM PROGRAM
MEMORY INTO LANCE'S
INITIALIZATION BLOCK
[INITIAL. BLK MOVE)
INITIALIZE THE RECEIVE
MESSAGE DESCRIPTOR
RINGS
[INITIAL. R RING INIT)
INITIALIZE THE TRANSMIT
MESSAGE DESCRIPTOR
RINGS
[INITIAL. T RING INIT)
Figure 20. Initialization Software ModUle [LANCE. INITIAL)
7-2
1-184
7.2.2 CLEAR SUBMODULE
Upon powerup, the MK68000 (also referred to as the local host, or host) addresses the reset vector location $0000
that holds the address of the start of the program. The starting address of the Clear Submodule, shown in Figure
21, is at location $400.
DEFINE MESSAGE
READY INTERRUPT
VECTOR
LOCATION
PUT ADDRESS OF
RING MANAGEMENT
STACK IN TO
REGA4
Figure 21. Clear Submodule [LANCE. INITIAL. CLEAR]
1-185
7·3
The program's first action is to reset the LANCE and other peripherals on the local system bus. Next, it clears
out the address and data registers, sets the interrupt mask, loads the interrupt autovectors and both system and
ring-management stack locations. The ring management area starting address is stored in Address Register A4.
Following this action, the host clears all data held in the ring status register.
7.2.3 BLOCK-MOVE SUBMODULE
Once the registers have all been cleared, the processor's next task is to move the LANCE's initialization block
into memory where the LANCE can access it. Information also must be extracted from the initialization block which
allows the software to determine the base addresses of the transmit and receive descriptor rings and their respective lengths. These operations take place in the "Block-Move" submodule described by the flowchart in Figure 22.
(
START
)
I
1
GET STARTING ADDRESS OF PROGRAM
INITIALIZATION BLOCK & STARTING ADDRESS
OF LANCE·S INITIALIZATION BLOCK
l
MOVE MODE INFORMATION FROM PROGRAM
BLOCK INTO LANCE'S BLOCK. STRIP
OFF INFORMATION PRIOR TO MOVE & STORE
IT IN RING MANAGEMENT AREA
l
MOVE PHYSICAL ADDRESS FROM PROGRAM
BLOCK INTO LANCE'S BLOCK
l
MOVE LOGICAL ADDRESS FROM PROGRAM
BLOCK INTO LANCE'S BLOCK
l
MOVE RECEIVE DESCRIPTOR RING ADDRESS
INTO LANCE INIT. BLOCK. SAVE A COpy
OF THE ADDRESS IN RING MANAGEMENT AREA
l
MOVE RECEIVE RING LENGTH (RLEN) INTO
LANCE'S INIT. BLOCK. USE RLEN TO CALCULATE
THE "NO. OF RINGS", STORE # OF DESCRIPTORS IN
RING MANAGEMENT AREA
1
MOVE TRANSMIT DESCRIPTOR RING ADDRESS
INTO LANCE'S IN IT BLOCK. SAVE A COPY
OF THE ADDRESS IN THE RING MANAGEMENT AREA
1
MOVE TRANSMIT RING LENGTH (TLEN) INTO
LANCE'S INIT BLOCK. USE TLEN TO CALCULATE
THE # OF TRANSMIT DESCRIPTORS, THEN STORE THE
# OF XMIT RINGS IN THE DESCRIPTORS MANAGEMENT AREA
(
1
END
)
Figure 22. Block-Move Submodule [LANCE, INITIAL. BLKMOVEI
1-186
The LANCE buffer management information is set up as equates. Equates define the following information:
1. Starting address of the initialization block
2. Displacement needed between the initialization block's starting address to the receiver and transmit descriptors' starting address
3. Number of transmit and receive buffers desired
4. Desired buffer size.
By altering one or more equate statements, any of these buffer management areas may be relocated in memory.
This software routine makes all calculations needed to initialize the receive and transmit descriptors. The only
limitation is that all receive descriptors must be in a contiguous block of memory. The same holds true for transmit
descriptors. The buffers for the receive and transmit operation may be placed anywhere throughout the memory
by specifying a buffer displacement from the descriptor's starting address (see Figure 23).
CONTIGUOUS {
MEMORY
INITIALIZATION
L-_...::::BLO=C::;:K:...-_....1
CONTIGUOUS {
MEMORY
r---R-EC-E-IV-E---'
DESCRIPTORS
CONTIGUOUS {
MEMORY
TRANSMIT
L..-_
DESCRIPTOR
_ _ _- '
~
-r
RBUFDISP
RECEIVE
BUFFER
DISPLACEMENT
TBUFDISP
TRANSMIT
BUFFER
L------....I~T'
RECEIVE
BUFFERS
TRANSMIT
BUFFERS
Figure 23. Buffer Displacement Diagrem
1·187
7-5
This design was chosen to give the program more flexibility. The same piece of software can be used, independent
of buffer number, size, and location.
Information is stripped by the block-move submodule from the initialization block source and transferred to the
LANCE shared memory. If the source is EPROM, the initialization block is identical upon each powerup. If the
source is downloaded from the main host, the initialization block may vary from one powerup sequence to the
next. The software in this Application Note was written so the initialization block, receive and transmit descriptors,
and the receive and transmit buffers are all in contiguous memory.
The "Block-Move" submodule also strips the receive and transmit ring lengths as it moves the initialization block
into memory. It stores the values to be used in memory allocation calculations in the receive and transmit ring
initialization routines. It also extracts mode information and sets the corresponding bits in the ring management
status register. In addition, it also copies, reformats for MK68000 compatability, and stores the receive and transmit
ring base address for later use.
In this software design, the receive and transmit descriptor base addresses are predetermined and the program
generates the buffer addresses from ring length information. The software also could have been structured to give
only ring length information. The program would then determine ring and buffer locations. Another structure may
have all address information pre-calculated without any calculations necessary upon initialization, although this
structure would not allow flexible ring management. The structure depends on the application desired.
7.2.4 RECEIVE RING INITIALIZATION SUBMODULE
Once the entire initialization block is moved into the share memory, the "Block-Move" submodule is complete and
the "Receive Ring Initialization" submodule begins. This submodule initializes all receive ring descriptors by
generating Receive Descriptors 0 through 3 (RMDO, RMD1, RMD2, & RMD3), as shown in Figure 24. It generates
each descriptor's respective buffer address by displacing it with the buffer length and displacement.
For example, if 256-byte buffers are required and the receive descriptor has a starting address of hex $5000 and
a buffer displacement of hex $1000, users would first add the buffer displacement to the starting address of the
descriptors. This would give a receive buffer starting address of hex $6000. Therefore, the buffer address of receive
buffer number 1 would be $6000. Receive buffer number 2 would have a starting address of $6100, Receive number
3 would have a starting address of $6200 and so on, each displaced 256 bytes, or one buffer length from the previous
buffer. Once the descriptor is initialized, ownership of it is given to the LANCE to be used when an incoming message
is received.
7-6
1-188
GET A WORKING COPY OF RECEIVER
RING BASE
ADDRESS
STORED FROM PREVIOUS PROCESS
GENERATE RECEIVE MESSAGE
DESCRIPTOR 0·1 (RMDO, RMD1) BY
ADDING RECEIVE BUFFER DISPLACE·
MENT TO THE RING DESCRIPTOR
ADDRESS
GENERATE LONG WORD BY USING
RMD2 FOR LOWER WORD"
ZERO'S FOR HIGH WORD. REFOR·
MATE FOR 68000 COMPATABlllTY
MOVE THIS LONGWORD TO RECEIVE
DESCRIPTOR ADDRESS, POINTED TO BY
RECEIVE DESCRIPTOR ADDRESS
COUNT.
SET "OWN" BIT RELINQUISHING
OWNERSHIP TO LANCE ONCE IT IS
INITIALIZED. SET MSB OF LONG WORD.
REFORMAT FOR 68000 COMPAT·
ABiliTY" MOVE RMDO " RMD1 OUT
TO MEMORY LOCATION DEFINED BY
RECEIVE DESCRIPTOR RING ADDRESS
INCREMENT THE RECEIVE DESCRIPTOR RING ADDRESS SO THAT IT
POINTS TO THE NEXT RING.
DECREMENT THE NUMBER OF
REMAINING DESCRIPTORS
TO BE INITIALIZED (RECEIVE
DESCRIPTOR COUNT)
INCREMENT RECEIVE BUFFER
ADDRESS BY 4 BYTES SO IT
WILL POINT TO ADDRESS DESIG·
NATED FOR RMD2 " RMD3
(MORE DESCRIPTORS
TOINIT.)
NO
GENERATE RMD2 BY GETTING
PRE·DEFINED BUFFER lENGTH.
TAKE 2'S COMPLEMENT OF IT,
AND FORCE 4 HIGHEST BITS
OF WORD TO ONE'S. THIS WILL
GIVE BUFFER BYTE COUNT.
Figure 24. Receive Ring Initialization Submodule [LANCE. INITIAL. RRINGINIT]
1·189
7.2.5 TRANSMIT RING INITIALIZATION SUBMODULE
When all receive ring descriptors are initialized, the program proceeds into the "Transmit Ring Initialization" submodule shown in Figure 25. This submodule initializes the transmit descriptors in much the same way it initializes
the receive descriptors, with the exception that the host retains ownership of the transmit descriptors. They are
used during message transmission. This submodule also generates the 2's complement of the byte count (BeNT)
and places it in the address specified for TMD2.
7-8
1-190
-
GET A WORKING COPY OF XMIT
DESCRIPTOR BASE ADDRESS
STORED FROM PREVIOUS PROCESS
GENERATE TMDO & TMD1, WHICH
CONTAIN XMIT BUFFER FOR THAT
RING, BY ADDING BUFFER DISPLACEMENT TO RING ADDRESS
SWAP WORDS OF TMD2-TMD3
LONG WORD. THIS WILL FORCE
THE LOWER WORD TO ALL ZEROS
AND PUT LONG WORD IN CORRECT
FORMAT FOR TRANSFER TO
MEMORY. MOVE LONG WORD
TO MEMORY LOCATION SPECIFIED
BY XMIT DESCRIPTOR ADDRESS
SWAP INDIVIDUAL WORDS OF
GENERATED LONG WORD SO THAT
IT IS COMPATIBLE WITH LANCE
FORMAT. MOVE LONG WORD INTO
MEMORY DESIGNATED FOR TMDO
AND TMD1. ADDRESS IS GIVEN
BY XMIT RING ADDRESS.
INCREMENT THE XMIT DESCRlp·
TOR ADDRESS BY 4.
DECREMENT THE XMIT RING
LENGTH REGISTER
INCREMENT XMIT DESCRIPTOR ADDRESS
BY 4 BYTES. IT WILL NOW
POINT TO ADDRESS DESIGNATED
FOR TMD2 & TMD3.
NO
GENERATE TMD2 BY GETTING
PREDEFINED BUFFER LENGTH AND
TAKING 2'S COMPLEMENT OF IT.
FORCE HIGHEST 4 BITS TO ONE'S
THIS WILL GIVE BUFFER BYTE
COUNT
---
(NO MORE DESCRIPTORS)
.....
Figure 25. Transmit Ring Initialization Submodule [LANCE. INITIAL. TRINGINITJ
1·191
7-9
7.2.6 DIAGNOSTIC SUBROUTINE
At this point in the program, the initialization block is in memory, which the LANCE can access. The receive and
transmit rings are initialized. A diagnostic routine now needs to be run to determine if the LANCE and associated
hardware are operating properly. (See Figures 26 and 27.) This is done by placing the LANCE in four different
loopback modes:
1. Internal loopback with transmit CRC enabled
2. Internal loopback with transmit CRC disabled
3. Internal loopback with transmit CRC enabled and the collision force bit set.
4. External loopback.
GET INITIALIZATION BLOCK
STARTING ADDRESS
SET THE: DIAGNOSTIC BIT, THE
LOOPBACK BIT, & INTERNAL
LOOPBACK BIT IN THE
RING MANAGEMENT REG
GET TRANSMIT DESCRIPTOR
BASE ADDRESS
GET TRANSMIT BUFFER
ADDRESS FROM DESCRIPTOR
GENERATE TEST MESSAGE
CRC GENERATION
Figure 26. Diagnostics' Subroutine [LANCE. INITIAL. DIAGJ
7·10
1-192
SET TRANSMIT MESSAGE
BYTE COUNT (MBCNT) TO
CORRECT MESSAGE SIZE
{
TEST
TEST
TEST
TEST
#1, MBCNT = 28 BYTES
#2, MBCNT = 32 BYTES
#3, MBCNT = 28 BYTES
#4, MBCNT = 28 BYTES
SET OWNERSHIP BIT IN
TRANSMIT DESCRIPTOR, GIVING
OWNERSHIP TO LANCE
SET UP INITIALIZATION BLOCK
MODE TO CORRESPOND TO
THE PARTICULAR TEST
{
TEST
TEST
TEST
TEST
#1,
#2,
#3,
#4,
INTERNAL LOOP, DTCR = 0
INTERNAL LOOP, DTCR = 1
INTERNAL LOOP, DTCR = 0
EXTERNAL LOOP, DTCR = 0
CONTROL & STATUS REG.
INITIALIZATION
SUBROUTINE
CHECK "TEST DONE" BIT
NO
TURN OFF LANCE
Figure 27, Loopback Diagnostic Test Routine
1-193
7·"
To test the LANCE, a test message must be generated and placed in the first transmit buffer. In addition, the first
transmit descriptor must be initialized.
The test data message created in this program is 28 bytes long. The test message is all hex /l\s, which is alternating binary l's and O's. The maximum amount of data that can be transmitted in loopback mode, whether external or internal, is 32 bytes. With transmit CRC enabled, a 28-byte message is transmitted but, the actual message
size is 32 bytes because the LANCE tags four bytes of hardware CRC upon transmission. The transmit length
constraint is due to the size limitation of the LANCE's SILO.
In this Application Note, the loopback date size is 28 bytes for all four tests.
After the message is generated, a CRC is generated by calling the software CRC subroutine described in Section
7.2.6.1. In all but the second loopback test, the LANCE's transmit CRC is enabled (bit 3 of the mode is set for
transmit CRC disable). When the transmit CRC is disabled, a software CRC is generated and transmitted with
the message. For the remaining loop back tests, the LANCE generates the CRC code in hardware and tags it on
the end of the transmitted message. This hardware-generated CRC is then compared to the software CRC to assure
proper operation of the LANCE.
The CRC generation is followed by initialization of the transmit descriptor. The buffer byte count (BCNT) of 28 is
written into transmit message descriptor 2 (TMD2). The start and end of packet bits, as well as the own bit are
set in transmit message descriptor 1 (TMD1). Following this descriptor initialization, the mode is set to: promiscuous,
internal loop back, with the "disable transmit CRC" bit set to "0".
As described before, with transmit CRC enabled, a CRC is generated for the outgoing message, but is not checked
for the incoming message. This is because the LANCE has only one CRC device. The device can generate the
CRC or check the CRC, but not concurrently. Verification of proper CRC occurs in the Receive Interrupt submodule,
described later.
The final step in each loopback test is an initialization of the LANCE's control and status registers (CSRINIT subroutine
call). The CSRINIT subroutine initializes the control and status registers which effectively starts the LANCE. These
subroutine steps are summarized in Section 7.2.6.2.
Once the CSRINIT subroutine has executed, the LANCE initializes itself. The program stays in a loop, waiting for
completion of this part of the loopback test. This is indicated when a test-complete bit is set in the ring management status register. Once one portion of the loopback test has completed, the next portion begins.
The steps taken after the CSR initialization subroutine is called include:
1. The LANCE is initialized by calling [CSRINIT].
2. The LANCE requests the bus and makes DMA cycles. It reads the entire initialization block.
3. The LANCE polls the receive and transmit rings to check for ownership (see MK68590 LANCE Technical Manual
for a more detailed description of polling routines.)
4. Finding that it owns the transmit ring, it enters its transmit DMA routine.
5. Once it has completed its transmission, it immediately starts to DMA the message it concurrently received
into the receive buffer.
6. The LANCE then interrupts the MK68000 to notify it that a transmission and reception has occurred.
7. The program vectors off to service the interrupt routine. During the exception processing routine, the applicationdependent status subroutines are called if an error flag is found.
8. Once all exception processing is complete, the test done bit is set and a return from the exception processing
occurs.
9. The "test-done" bit is constantly checked. Once set, the program continues normal execution, turning off the
LANCE and proceeding to the next portion of the diagnostics.
When loopback test number one is complete, the second loopback test proceeds in a similar manner as the first.
The only difference between loopback tests is the mode. For clarity, this test is repeated four times in the software
rather than tightening the code by inserting four loops.
If the diagnostics detects problems with the LANCE, the status subroutines report the errors by setting a status
bit in memory. This Application Note does not deal with error handling, since it is application-dependent and out
7·12
1-194
of the real of this document.
After all four loopback tests have completed, the LANCE is initialized for normal operation.
7.2.6.1 CRC CODE SOFTWARE GENERATION
Before the descriptor initialization, a CRC subroutine, is called to generate a 32-bit cycle redundancy check code
(CRC) toJt!e added at the end of the message (see Figure 28).
Since all hex fJ(s is the predetermined data in the message, the CRC can also be predetermined. If the test message
differed for each test, an actual rigorus software CRC subroutine would have to be designed. But, in this case,
the CRC subroutine simply writes $B1109280 out to the message buffer. This data is the CRC code for the 28-byte
test message.
SAVE CONTENT OF REGISTER
BY PLACING THEM ON STACK
GET ADDRESS OF CRC LOCATION
Figure 28. Cycle Redundancy Check Generation Subroutine ICRCGEN]
7.2.6.2 CONTROL AND STATUS REGISTER INITIALIZATION SUBROUTINE
The Control and Status register initialization subroutine is shown in Figure 29. The first step is to move the initialization starting address into the LANCE's Control and Status registers. The low order bits <00:15> are placed
in CSR1, and the high order bits < 16:23> are placed in CSR2. Next, the LANCE is made compatible to the hardware interface by setting BSWP = 1, ACON = 1, and BCON = 0 in CSR3. Finally, a $0043 is written into CSRO,
which sets the Interrupt Enable, the Start and Initialize bits. Immediately following this last write, the LANCE starts
its initialization procedure by requesting the bus and completing 12 DMA cycles. Each DMA cycle corresponds
by moving one word of the initialization block into its internal registers.
1·195
7·13
Figure 29. Control and Status Register Initialization Subroutine [CSRINIT]
7·14
1·196
Once the DMA cycles are complete, th!l LANCE interrupts to notify the host of completed initialization. If the Interrupt Enable bit in CSRO is not set, the LANCE does not interrupt the host, but rather, waits for the host to poll
its Control and Status register.
Next, a polling routine is begun to determine which receive and transmit descriptors are owned by LANCE. When
a LANCE-owned receive ring is found, that result is stored and polling continues to locate a relinquished transmit
ring. The CSR initialization submodule is complete when the final CSRO takes place. The program then returns
from this subroutine.
7.2.7 NORMAL-OPERATION INITIALIZATION
After the diagnostics are complete, the normal-operation initialization occurs. This submodule is shown in Figure
30. The predefined mode in the program initialization block is moved into the LANCE's initialization block. The
mode information is checked to determine if the desired mode is a loopback mode. If it is, the ring management
status register is set up accordingly. The LANCE is then restarted by calling the control and status register initialization subroutine, CSRINIT.
1-197
7·15
GET STARTING ADDRESS OF PROGRAM INITIALIZATION BLOCK
(CONTAINS NORMAL OPERATION MODE
INFORMATION
SET LOOP STATUS BIT IN RING
MANAGEMENT STATUS REGISTER
MOVE NORMAL-OPERATION MODE
INFORMATION INTO LANCE'S
INITIALIZATION BLOCK
NO
CLEAR OUT RING MANAGEMENT
STATUS REGISTER
SET INTERNAL LOOP BIT IN RING
MANAGEMENT STATUS REGISTER
CHECK MODE BIT TO DETERMINE
MODE OF OPERATION
CONTROL & STATUS INITIALIZATION
SUBROUTINE
YES
WAIT FOR INTERRUPT
Figure 30. Normal Operation Initialization Submodule [LANCE. INITIAL. NORM)
7-16
1-198
After the Normal-Operation Initialization, the initialization software module is complete and stays in a wait loop.
The program is completely interrupt-driven from this point on and only moves out of the wait loop when an interrupt
occurs.
7.3 LANCE INTERRUPT EXCEPTION SOFTWARE MODULE
7.3.1 INTRODUCTION
The
1.
2.
3.
4.
LANCE Interrupt Exception Module has basically four submodules. They are:
Interrupt Error Determination Submodule
Transmit Interrupt Handling Submodule
Receive Interrupt Handling Submodule
Initialization Done Interrupt Handling Submodule
Figure 31 depicts the flow of the Exception Software Module. The LANCE Interrupt Exception Software Module,
also referred to as the LANCE Interrupt Routine, is called when the LANCE interrupts the host processor. The
LANCE interrupts the host if a message has been transmitted or received, the LANCE has finished its initialization
routine, or an error has occurred.
RECEIVE
INTERRUPT
SUBMODULE
[LEXCEPT. RVCR]
ERROR
DETERMINATION
SUBMODULE
[LEXCEPT. ERROR)
INITIALIZATION
DONE
SUBMODULE
[LEXCEPT. lOON)
TRANSMIT
INTERRUPT
SUBMODULE
[LEXCEPT. XMIT]
Figure 31. LANCE Exception Processing Module ILEXCEPT]
1-199
7.17,
The LANCE interrupt is hardware set at level 6; the second highest priority. The only higher priority is level seven,
that of the nonmaskable interrupt. When the LANCE interrupts the MK68000, it autovectors to memory location $800.
The first action the MK68000 takes is to get the LANCE's status from CSRO. This status helps determine what
caused the interrupt. The error bit is the first bit checked. If this bit is not set, the Transmit Interrupt bit is checked
to see if a transmitted message caused the interrupt. If an error did cause the interrupt, the software determines
the type of error and the routine proceeds to the transmit interrupt check. Once the transmit bit is checked, the
receive bit is checked in the same manner. Finally the Initialization Done bit is checked and the program returns
to the waiting loop.
All flag-causing conditions are serviced and the error-causing conditions call application-dependent service
subroutines. For the purposes of this Application Note, these error service routines simply set certain bits in memory
that correspond to the error. The programmer may then examine memory for errors.
7.3.2 INTERRUPT ERROR DETERMINATION SUBMODULE
The first task in this submodule, as shown in Figure 32, is to save the registers. Information in the data and address
registers is placed on the stack to be retrieved after exception processing. Next, status information in the Control
and Status Register zero (CSRO) is moved into one of the MK68000's registers. Following this, all flags set in CSRO
and the Interrupt Enable bit are cleared. This occurs by clearing bit 6 (Interrupt Enable bit) in the register containing a copy of CSRO, and writing this copy back into CSRO. Since the flags are all cleared by writing a "1" in their
bit location, all flags set in CSRO are cleared. The Error bit in CSRO clears itself after all the individual error flags
are cleared. The interrupt enable bit is cleared by writing a "0" in its bit location. The LANCE's interrupt capabilities
are disabled because it is not desirable to have another interrupt occur while the present interrupt from the LANCE
is being serviced.
7·18
1-200
SAVE CONTENTS OF REGISTER
ON STACK
GET STATUS INFORMATION OUT OF
CONTROL-STATUS REGISTER ZERO
CSRO
CLEAR "INTERRUPT ENABLE" BIT
(lNEA) IN CSRO AND CLEAR OUT
REMAINING FLAGS THAT WERE SET
IN CSRO
CERR SUB
SERVICE
COLLISION ERROR
BABL SUB
SERVICE BABBLE
ERROR
MISSUB
SERVICE MISSED
PACKET ERROR
MERRSUB
SERVICE MEMORY
ERROR
NO
Figure 32_ Interrupt Error Determination Submodule [LANCE. LEXCEPT. ERROR)
1-201
7-19
The Error Summary bit is the first status bit to be checked. If this bit is not set, no error-causing conditions are
present and the individual error bits need not be checked. The Transmit Interrupt bit is checked next to see if it is set.
If the Error Summary bit is set, each individual error bit is checked. If any are set, an error-handling subroutine
is called to report or service the error. Again, as stated before, these are application-dependent subroutines. The
user can implement error handling routines to suit system requirements.
When it is determined whether an error caused the interrupt, the Transmit Interrupt bit is checked. Since more
than one condition can cause the interrupt, all bits must be checked. The interrupt pin is simply an OR of the
interrupt-causing conditions. If another interrupt occurs after the interrupt pin is asserted, another transition on
the interrupt pin will not occur.
7.3.3 TRANSMIT INTERRUPT HANDLING SUBMODULE
If the Transmit Interrupt bit is set, the Transmit Interrupt Handling Submodule is executed (see Figure 33). First,
the address pointer to the last transmit descriptor ring is retrieved from the ring management area. This address
is incremented by two bytes so it points to the transmit status (TMD1). Next, the transmit status is moved into a
MK68000 register. The "More" bit is checked to see if more than one transmission attempts were required. If so,
the More counter in the ring management area is updated. The "One" bit is then checked to see if it took exactly
one attempt to transmit the message. If so, the One counter is updated in a similar manner.
7·20
1-202
Figure 33. Transmit Interrupt Handling Submodule [LANCE. LEXCEPT. XMITI
1-203
7·21
Next, the Transmit Error bit is tested to see if a transmission error occurred. As with the Interrupt Error bit in CSRO,
if this bit i~' not set, it is not necessary to check each individual error bit, but if this Error Summary bit is set, the
program del'ls cbeck each individual error bit. It checks the errors in the following order: retry error, loss of carrier
error, late collision error, underflow error, and finally the buffer error. If any of these errors have occurred, the error
handling subroutines are called to report and/or service the error-causing conditions.
If the transmission error summary bit is not set, the program checks to see if the LANCE is in the loopback mode.
If this is true, a copy of the starting address of the transmit buffer is saved so the data in this buffer can be compared against data in the loopbacked message just received. This comparison indicates loopback mode status.
If the LANCE is in the loopback mode, the pointer to the last transmit descriptor is not incremented. This is because
the descriptor buffer must not be available for additional messages until data in the transmit buffer is compared
to that in the receive message buffer. This comparison occurs in the Receive Interrupt Handling Submodule of
the module that is presently executing. At this time, the Last Transmit Descriptor pointer is updated.
In all other cases, before this submodule is complete, the last descriptor address pointer is updated to pOint to
the next available descriptor. When the last descriptor address is updated, the present address pointed to must
be compared with the bottom of the ring.
If the pointer is pOinting to the bottom of the ring, it must not be simply incremented but, the address of the top
of the ring must be placed in the pOinter register. Once the Transmit Interrupt Handling Submodule is complete,
the Receive Interrupt bit is checked in the CSRO status.
7.3.4 RECEIVE INTERRUPT HANDLING SUBMODULE
The Receive Interrupt Handling Subrnodule, shown in Figure 34, is the most complicated piece of software in this
program because it must handle loopback messages differently from a normal received message.
Two loopback situations can occur: One can occur during the diagnostic routine, and the other is the normal condition loopback. The latter loopback happens when the programmer desires to have external or internal loopback
as a normal operating mode. This would most likely be the (;ClSe during debut and system integration.
7·22
1-204
Figure 34. Receive Intllrrupt Handling Submodule [LANCE. LEXCEPT. RVCR]
1-205
7·23
If during CSRO status checking the Receive Interrupt bit is set, the Receive Interrupt Handling Submodule is executed. The first step is to check the status of the receive message descriptor that the LANCE has turned over
to the host by retrieving the Receive Descriptor pOinter from the ring management area. Next, receive message
descriptor number one (RMD1) is moved into one of the 68000's registers and the Receive Error Summary bit is
checked. If this bit is set, the individual error bits are checked to see which error, or combination of errors, caused
the error summary bit to be set. Error bits are checked in the following order: frame error, CRC error, overflow
error, and buffer error.
If the Error Summary bit is not set, and LANCE is in the loop back mode, the loopback routine is executed (see
Figure 35). The loopback routine is still part of the receive interrupt routine, but is listed separately for clarity.
7-24
1-206
SIZEERR
SUBROUTINE
LPACKERR
SUBROUTINE
LMESSBAD
SUBROUTINE
Figure 35. Loopback Service Routine [LANCE. LEXCEPT. RVCR. LOOPBACK]
1-207
7·25
7.3.4.1 LOOPBACK HANDLING ROUTINE
The first step in this routine is to check the received message length, which must be equal to the message sent,
plus four bytes if transmit CRC is enabled. This is done by checking MCNT against the transmit message word
(MLENGTH). The transmit message word length is in the ring management area (see Ring Management). The
size of the transmit message is moved into MLENGTH when loopback occurs during the diagnostics.
In normal operation with the application breadboard, an arbitrary message size can be written into DLENGTH,
followed by pushing the message interrupt button, and a message of that data size is transmitted.
If the message sizes do not match, an error subroutine is called. Next the packet check is made. In loopback mode,
transmit data chaining cannot occur and the maximum received message size is 36 bytes. The receive buffers
are larger than 36 bytes and since there must be only one packet per message, the start- and end-ol-packet bits
must be set. If both are not set, an error routine is called.
After the packet check, the receive and transmit buffer starting addresses are retrieved. The receive buffer address is taken from the receive descriptor, while the transmit buffer address is taken out of LOOPXADD from the
Ring Management Area. LOOPXADD is moved into the Ring Management Area during the transmit interrupt routine.
By using these addresses, the transmit and receive message data can be compared to verify proper transmission
and reception. If any part of the message has been altered, an error subroutine is called.
When the entire message has been compared, the program checks if it is in the diagnostic mod"t As stated previously,
a software CRC is generated for the test message, and is compared to LANCE's hardware GI1C. If any of the two
do not match, an error subroutine is called. This comparison is only performed during diagnostics. If the program
is in loopback, but not in diagnostics, this part of the routine is omitted.
After all comparisons are made, the transmit descriptor pOinter is updated. The transmit descriptor pOinter is not
updated in the transmit interrupt routine because the descriptor pOints to the transmit buffer needed for the loopback data comparison. If the transmit buffer is made available before the data comparison, the buffer might be
written over, thus invalidating the comparison.
7.3.4.2 RECEIVE INTERRUPT NORMAL OPERATION
If no errors are detected, and the LANCE is not in loopback, the receive interrupt routine proceeds normally. A
packet check then searches for any errors with the start-of-packet and end-of-packet bits (see Figure 36). The ring
management status register contains information on the status of these bits. A receive message coming in with
the start-of-packet bit set and the end-of-packet bit not set indicates that more than one buffer contains the message.
In this situation, the start·of-packet bit is set in the ring management status register. If the following descriptor contains another start-of-packet bit, an error flag is set since an end-of-packet has not been detected between the
two start-of-packets. If the end-of-packet bit is set in the descriptor, the whole packet is received and the status
register is set accordingly. The same holds true for two end-of-packets detected sequentially. If two end-of-packets
are detected, without a start-of-packet in between them, an error flag is raised. These error flags call applicationdependent subroutines to service the error.
7-26
1-208
TEST AND CLEAR RING
START BIT CONTAINED IN
THE RING MANAGEMENT
STATUS REGISTER
PACKERR
PACKET ERROR
HANDLING
SUBROUTINE
PACKERR
YES
YES
PACKET ERROR
HANDLING
SUBROUTINE
SET START OF PACKET
BIT IN RING MANAGEMENT
STATUS REGISTER
YES
SET THE START OF PACKET BIT
IN RING MANAGEMENT STATUS
REGISTER
Figure 36. Packet Status Discrepancy Check Routine [LANCE. LEXCEPT. RCVR. PACKCHECK]
1-209
7-27
Once the packet check is complete, the received message is moved to an output device or to another memory
location. Once moved, this layer of software no longer handles the message, instead the upper level software takes
over. The upper level reformats the message and combines messages by sequence number as well as routing
them to their final destination.
In this Application Note, the message is simply moved to another memory block. This can be accomplished effectively by changing the receive buffer starting address in the receive message descriptor to the address of an empty
memory block. Then the used buffer address can be passed on to the next software layer. The same holds for
transmitted messages. If the number of messages exceeds the number of available buffers, the host either rejects
the last message and waits for a free buffer or moves the message into an empty memory block. When a descriptor is free, the host then changes the transmit buffer address in the descriptor.
The message is moved from the message buffer into the output memory a word at a time. Each time a word is
moved, a count of the message length is decremented and checked to see if any messages still need to be transferred. Once the entire message is out of the buffer, the ring management area is updated by moving the last receive
descriptor pointer to the next descriptor to be used by the LANCE. The LANCE again owns the buffer.
The start bit in the ring management area undergoes a final check. A set bit indicates that this receive buffer was
only one of several buffers needed for the full message. If more buffers are associated with this message, a jump
back to the beginning of the receive interrupt routine is made and the routine is executed again until the entire
message is processed. If the start bit is not set, this was the only buffer needed for the message, thus, the routine
is completed.
7.3.5 INITIALIZATION DONE INl ERRUPT HANDLING SUBMODULE
The final submodule of the LANCE interrupt processing routine, shown in Figure 37, is the Initialization Done Interrupt Handling Submodule. This submodule determines if the host was interrupted because the LANCE had just
completed initialization. CSRO is checked to see if the lOON bit is set. If so, a flag-raising routine is called.
IDONSUB
YES
SERVICE
INTERRUPT ENABLE
THE LANCE
NO
RETRIEVE CONTENTS
OF OLD REGISTERS
SET TEST FINISHED BIT
Figure :g. Initialization Done Interrupt Handling Submodule [LANCE. LEXCEPT. lOON)
7·28
1-210
The diagnostic bit in the ring management register is then checked, If the LANCE is in the diagnostic routine,
the test done bit is set. The test done bit indicates a message has been loopbacked and checked and the next
portion of the diagnostics may begin, This bit is checked after both a completed interrupt service routine and a
Return From Exception,
At this point, all of the LANCE's interrupting conditions have been checked and serviced, During the exception
processing, the LANCE's interrupting capabilities are disabled because another interrupt from the LANCE should
not be performed while the first one is being serviced, Since servicing is complete the Interrupt Enable bit can
again be set again in CSRO,
The module is concluded by moving the contents of the old registers off the stack and back into the register locations, A Return From Exception is then executed,
7,4 MESSAGE INTERRUPT SOFTWARE MODULE
The Message Interrupt Software Module, shown in Figure 38, is the routine that services the "push-button" message
generator used in Aplication Note's hypothetical design, This push button is used for demonstration and debugging, The software description is included in this Application Note because the service routine is general enough
to be adapted to any type of interrupt. The source of the interrupt may be anything, such as another processor
controlling a terminal, a file server, or, as in this case, a push-button switch,
1-211
7-29
NO RINGS
ERROR HANDLING
SUBROUTINE
Figure 38. Message Interrupt Software Module (LANCE. MESSAGE]
7·30
1-212
There is, however, one major difference between this module and one used in real life. In addition to servicing
the transmit message, this module also generates the message.
This module's basic function is to fill up as many transmit buffers as needed for the outgoing message, and to
set the status information in the message descriptor accordingly.
The message interrupt is hardware set at interrupt level 5. Upon interrupt, the processor autovectors to memory
location $OBOO, the location of this module.
The software first saves the contents of the old registers and then clears the registers for use. Next, the message
data length is retrieved from DLENGTH in the Ring Management Area. This message data length is manually written into before the message button is depressed.
Next, the Descriptor Count is Checked for available transmit buffers. If none are available, an error subroutine is
called, which sets an error bit in the status area, and the routine is over. If a buffer is available, the descriptor
count is decremented and the Next Descriptor Ring address is moved into a register from the Ring Management
Area. The Next Transmit Descriptor points to the descriptor of the next transmit buffer. The transmit buffer address
is then moved in from the descriptor and reformatted for MK68000 compatability.
A message data word is then generated. The message consists of byte values ranging from zero to the hex value
specified by DLENGTH. In other words, if the value $20 is written into DLENGTH and a message is generated,
it consists of 32 bytes. The value of the first byte is $00, the second, $01, the third, $03, the 32nd, $1F, and so forth.
Each time a data word is generated, the transmit buffer address is incremented along with the buffer and message
counts. The buffer count records how many bytes have been moved into the present transmit buffer. If the transmit
message length exceeds the buffer size, more then one transmit buffer is used. The message count keeps track
of the number of generated message words. If this amount equals DLENGTH, the message generation part of
this module is complete.
If the transmit buffer is full, and more data words need to be generated, the transmit descriptor for that buffer is
updated, and the rest of the message is placed in the next available transmit message buffer. In this case, the
first transmit descriptor has the start-of-packet bit set, but the end-of-packet bit is not set. Figure 39 shows a flow
chart of the transmit descriptor update submodule.
Once the entire message has been moved into the message buffer, or buffers, the last transmit descriptor is updated with the status information, along with a 2's complement of the number of bytes placed in its buffer. Finally,
the old registers are retrieved, and a Return From Exception is executed.
1·213
7·31
SET START OF PACKET
BIT IN TMD1
OET ADDRESS OF TMD2
CLEAR OUT TMD3
OET 2'S COMPLEMENT
OF WORD COUNT
GET ADDRESS OF TMD1
PUT 2'S COMPLEMENT WORD
COUNT INTO TMD2
CLEAR OUT HIGH BYTE
AND SET OWN BIT GIVING
OWNERSHIP BACK TO LANCE
OET ADDRESS OF TMD3
DECREMENT "DESCRIPTORS
AVAILABLE" COUNTER
Figure 39. lI'anamlt Ring Update Submodule [MESSAGE. XMIT RING UPDATE]
7-32
1-214
8.0 APPENDICES
Appendix A (paragraph 8.1) presents the initialization assembly code. Appendix B (paragraph 8.2) provides the
LANCE interrupt assembly code. Appendix C (paragraph 8.3) addresses the message interrupt assembly code.
8.1 APPENDIX A, INITIALIZATION ASSEMBLY CODE
The following pages provide a listing of the initialization assembly code.
1-215
8-1
~
UNITED TECHNOLOGIES MOSTEK 68000 Assembler Vl.4
Site 99994 MOSTEK
INITIAL. A68
Line S Location
Value
Source
1 0
2 0
3 0
4 0
5 0
******************************************************************+
*+****************:k**********************************************+*
6 0
7 0
8 0
~
en
9
10
11
12
13
14
15
16
17
18
19
20
21
22
**
**
0
0
0
0
0
0
**
0
**
**
**
0
0
0
0
MODULE NAME:
AUTHOR:
**
**
**
INITIAL.
JIM FONTAINE
PROGRAM: LANCE
LATEST REVISION DATE:
**
**
JANUARY 20,1984
*******************************************************************
**
**
**
**
**
0
0
**
**
23 0
24 0
**
**
**
**
25 0
26 0
27 0
**
28 0
29 0
**
**
**
30 0
31 0
32 0
DESCRIPTION:
TIllS MODULE WILL INITIALIZE TIlE ETHERNET NODE
AND MAKE IT OPERATIONAL.
THIS MODULE IS COMPOSED OF SIX
SUBMODULES.
THEY ARE: CLEAR, BLKMOVE, RRINGINIT, TRINGINIT,
DrAG, AND NORM.
THE CLEAR SUBMODULE CLEARS OUT THE WORKING REGISTERS. RESETS
TIlE SYSTEM, DEFINES TIlE INTERRUPT VECTORS AND STACK
LOCATIONS. THE BLKMOVE SUBMODULE MOVES THE INITIALIZATION
BLOCK FROM PROGRAM MEMORY INTO THE MEMORY SPACE ALLOCATED FOR
LANCE I S INITIALIZATION BLOCK. RRINGINIT SUBMODULE INITIALIZES
TIlE RECEIVE MESSAGE DESCRIPTOR RINGS. TIlE TRINGINIT SUBMODULE
INITIALIZES THE TRANSMIT MESSAGE DESCRIPTOR RINGS. THE
DIAGNOSTIC SUBMODULE RUNS THROUGH A INTERNAL AND EXTERNAL
LOOP BACK ROUTINE TO TEST THE PROPER OPERATION OF THE LANCE
AND ADDITIONAL HARDWARE. FINALLY, TIlE NORMAL SUBMODULE
INITIALIZES THE LANCE IN A NORMAL MODE OF OPERATION.
M
33 0
34 0
35 0
36 0
**
**
**
**
**
**
**
**
**
**
**
**
M
*****************************************************************+*
******************************************************************+
37 0
38 0
39 0
*************************************************
40 0
EQUATE TABLE
41 0
42 0
43
*************************************************
44
45 0
XREF
XREF
DATINTR
LANINTR
46 0
47 0
DESCRIPTOR RING STACK ALLOCATION
48 0
49 0
50 0
51 0
00000000
00000002
RLEN
TLEN
EQU
EQU
$00
$02
; 38CO
; 38C2
RECEIVER RING LENGTH
TRANSMIT RING LENGTH
UNITED TECHNOLOGIES mSTEK 68000 Assembler VI. 4
Site 99994 MOSTEK
INITIAL .A68
Line
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
S Location Value
00000004
0
00000008
0
0
OOOOOOOC
0
00000010
0
00000014
00000018
000000IC
00000020
0
00000022
0
00000024
0
00000028
0
0000002C
0
0000002E
0
00000034
0
00000038
0
0
00000100
0
00000060
69
00001020
70 0
Source
RRNGBASE
TRNGBASE
RRNGBOT
TRNGBOT
LASTRRNG
LASTTRNG
NEXTTRNG
LOOPMCNT
TRINGCNT
RINGSTAT
LOOPXADD
MORE
ONE
DLENGTH
MLENGTH
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$04
$08
SOC
$10
$14
$18
$1 C
$20
$ 22
$24
$ 28
$2C
$2E
$34
$ 38
BUFLEN
RBUFDIS
TBUFDIS
EQU
EQU
EQU
$0100
$0060
$1020
; 38C4
; 38C8
; 38CC
; 38DO
;38D4
; 38D8
;38DC
; 38EO
;3EE2
; 38E4
;38E8
RECEIVER RING BASE ADDRESS
TRANSMIT RING BASE ADDRESS
RECEIVER RING BOTTOM ADDRESS
TRANSMIT RING BOTTOM ADDRESS
ADDRESS OF LAST RECEIVE RING USED
ADDRESS OF LAST TRANSMIT RING USED
ADDRESS OF NEXT AVAILABLE TRANSMIT RING
MESSAGE COUNT OF LOOP MESSAGE
NUMBER OF TRANSMIT RINGS AVAILABLE TO USE
RING STATUS
ADDRESS OF LOOPBACK BUFFER
;38EC
RUNING COUNT OF "MORE" FLAGS
;38EE
;38FO
; 38F4
RUNNING COUNT OF "ONE" FLAGS
DESIRED MESSAGE DATA SIZE
TOTAL LENGTH OF TRANSMITTED MESSAGE
TRANSMIT & RECEIVE BUFFER LENGTH
RECEIVER BUFFER DISPLACEMENT FROM DESCRIPT. RING
XMIT BUFFER DISPLACEMENT FROM THE DESCRIPT RING
71 0
720
~
.....
73
74
75
76
0
0
MEMORY MAP LOCATIONS
0
0
77 0
78 0
79 0
800
81 0
82 0
83 0
84 0
85 0
86 0
87 0
88 0
89 0
90 0
91 0
920
93 0
94 0
95 0
LANCES INITIALIZATION BLOCK BASE ADDRESS
STACK BASE ADDRESS
XMIT & RVCR USERS STACK BASE ADDRESS
00002000
0000387C
000038CO
IADR
STACK
RINGSTK
EQU
EQU
EQU
$2000
$387C
$38CO
00000044
00000004
00000000
00000000
00000008
00000000
00000000
00000000
00002018
00006000
00002058
00004000
MODE
PADRI
PADR2
PADR3
LADRI
LADR2
LADR3
LADR4
RDRAI
RDRA2
TORAI
TORA2
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$0044
$0004
$0000
$0000
$0008
$0000
$0000
$0000
$2018
$6000
$2058
$4000
; ETHERNET MODE
;PHYSICAL ADDRESS <00: 15>
;PHYSICAL ADDRESS <16 :31>
;PHYSICAL ADDRESS 02:47>
;LOGICAL ADDRESS <00: 15>
; LOGICAL ADDRESS <16: 31>
;LOGICAL ADDRESS <32:47>
; LOGICAL ADDRESS <48: 63>
;RECEIVE DESCRIPTOR ADDRESS <00: 15>
; RECEIVE DESCRIPTOR ADDRESS <16: 23>
;TRANSMIT DESCRIPTOR ADDRESS <00: 15>
; TRANSMIT DESCRIPTOR ADDRESS <16: 23>
00004002
00004000
RAP
RDP
EQU
EQU
$4002
$4000
; LANCE , S REGISTER ADDRESS PORT ADDRESS
;LANCE'S REGISTER DATA PORT ADDRESS
96 0
97 0
KEYWORD VALUE EQUATES
98 0
99 0
~
100 0
101 0
102 0
00000000
00000001
CSRO
CSRI
EQU
EQU
$00
$01
;ADDRESS OF CONTROL-STATUS REGISTER 0
;ADDRESS OF CONTROL-STATUS REGISTER 1
~
UNITED TECHNOLOGIES MOSTEK 68000 Assembler V1.4
Site 99994 MOSTEK
INITIAL.A68
Line S Location
...
N
CO
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
0
0
0
Value
00000002
00000003
Source
CSR2
CSR3
EQU
EQU
$02
$03
;ADDRESS OF CONTROL-STATUS REGISTER 2
;ADDRESS OF CONTROL-STATUS REGISTER 3
WORD VALUE DEFINITION
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000400
XDEF
XDEF
RAP
RDP
XDEF
XDEF
XDEF
XDEF
CSRO
CSRI
CSR2
CSR3
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
XDEP
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
RLEN
TLEN
RRNGBASE
TRNGBASE
RRNGBOT
TRNGBOT
LASTRRNG
LASTTRNG
NEXTTRNG
LOOPMCNT
TRINGCNT
RINGSTAT
MORE
ONE
LOOPXADD
DLENGTH
TBUFLEN
MLENGTH
XDEF
DIAG
ORG
$400
****************
MAIN PROGRAM
**********************
****************************************************
*
INITIAL. CLEAR
INITIALIZE 11K68000 AND CLEAR REGISTERS
*
****************************************************
00000400 46FC2700
00000404 4E70
CLEAR
MOVE.W
RESET
11$2700, SR
SET UP STATUS REGISTER
RESET THE 68000
UNITED TECHNOLOGIES MOSTEK 68000 Assembler V1.4
Site 99994 MOSTEK
INITIAL .A68
...
~
CD
~
Line S Location Value
154
155
156
157
00000406 4280
158
00000408 4281
159
0000040A 4282
0000040C 4283
160
161
0000040E 4284
00000410 4285
162
00000412 4286
163
00000414 4287
164
165
166
167
168
00000416 2040
00000418 2240
169
170
0000041A 2440
171
0000041C 2640
172
0000041E 2840
173
174
175
176
177
00000420 207 C00000078
178
00000426 20BCFFFFFFFF
179
0000042C 207C00000074
180
00000432 20BCFFFFFFFF
181
00000438 287C000038CO
182
0000043E 207C0000387C
183
00000444 4E60
184
00000446 46FCA400
185
0000044A 29400028
186
0000044E 19400024
187
00000452 3940002E
188
00000456 3940002C
189
0000045A 39400020
190
191
192
193
194
195
196
197
198
199
0000045E 207COOOO071C
00000464 227COOOO2000
200
201
0000046A 2290
202
20'j
0000046C OC04000F
00000470 6EOOOOOA
204
Source
*'*
CLEAR
ALL
CLR.L
CLR.L
CLR.L
CLR.L
CLR.L
CLR.L
CLR.L
CLR.L
***
CLEAR
ADDRESS
MOVE.L
MOVE.L
MOVE.L
MOVE .L
MOVE.L
***
DATA
REGISTERS
DO
Dl
D2
D3
D4
D5
D6
D7
***
CLEAR
CLEAR
CLEAR
CLEAR
CLEAR
CLEAR
CLEAR
CLEAR
REGISTERS
DO ,AD
DO,Al
DO,A2
DO,A3
DO,A4
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
REG
REG
REG
REG
REG
REG
REG
REG
DO
Dl
D2
D3
D4
D5
D6
D7
AO AND A4
CLEAR
CLEAR
CLEAR
CLEAR
CLEAR
ADDRESS
ADDRESS
ADDRESS
ADDRESS
ADDRESS
REG
REG
REG
REG
REG
AO
Al
A2
A3
A4
DEFINE STACK AND INTERRUPT VECTOR LOCATIONS
MOVE.L
MOVE.L
MOVE.L
MOVE.L
MOVE-L
MOVE-L
MOVE.L
MOVE.W
MOVE.L
MOVE.B
HOVE.W
MOVE.W
MOVE.W
11$78,AO
IILANINTR, (AO)
11$74,AO
IIDATINTR, (AO)
ilRINGSTK,A4
II STACK ,AO
AD,USP
iI$A400, SR
DO,LOOPXADD(A4)
DO, RINGSTAT(A4)
DO,ONE(A4)
DO ,MORE(A4)
DO, LOOPMCNT( A4 )
DEFINE VECTOR FOR "LANCE" INTERRUPT
MOVE VECTOR LOCATION TO LOCATION 978
DEFINE VECTOR FOR "DATA FOR XMIT" INTERRUPT
MOVE VECTOR LOCATION TO LOCATION $74
MOVE RING STACK LOCATION TO REGISTER A4
MOVE STACK LOCATION TO AO
MOVE STACK LOCATION TO USER STACK POINTER
SET UP MASK IN STATUS REGISTER
CLEAR OUT LOOP ADDRES S ON STACK
CLEAR OUT RING STATUS
CLEAR OUT THE ONE'S COUNTER
CLEAR OUT THE MORE' S COUNTER
CLEAR OUT THE MESSAGE COUNT
*******************************************************
INITIAL .BLKMOVE
MOVE INITIALIZATION BLOCK
*******************.,.***********************************
MOVE.L
IlpROGIADR,AO
IIIADR,Al
GET STARTING ADDRESS OF PROGRAM INIT. BLOCK
GET STARTING ADDRESS OF LANCE IN IT • BLOCK
MOVE.L
CMPI.B
BGT
(AO) ,(Al)
1115,D4
COUNTl6
MOVE LONG WORD OF PROG BLOCK INTO LANCE BLOCK
SEE IF WE ARE UP TO ADDRESS IADR (23: 00>+20 (OCT)
IF SO BRANCH TO COUNT = 16
MOVE.L
RETURN
:l:
UNITED TECHNOLOGIES MOSTEK 68000 Assembler Vl.4
SHe 99994 MOSTEK
INITIAL. A68
Line S Location
205
206
207
208
209
210
211
....
N
I\)
<:>
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
Value
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
ADD
ADD
ADD
BRA
CMPI.B
BNE
1104,AO
1104 ,AI
1104,D4
RETURN
1116,D4
COUNT20
5848
5849
5844
60EE
OC040010
66000030
00000484
00000486
00000488
0000048A
0000048E
00000490
00000494
00000496
0000049A
2010
E758
1200
02010007
7 A01
04010001
6D06
CAFC0002
60F4
MOVE.L
ROL.W
MOVE.B
ANDI.B
MOVEQ
NXTPOWER SUB I .B
BLT.S
MOLU
BRA.S
(AO) ,DO
113 ,DO
DO,D1
11$07,D1
1101,D5
1101,D1
CALCDONE
112,D5
NXTPOWER
MOVE RECEIVE RING ADDRESS AND LENGTH TO DO
MOVE RECEIVE LENGTH TO LOWER BYTE OF LONG WORD
SAVE A COPY OF CODED RECEIVER RING LENGTH IN REG D1
CLEAR OUT EVERYTHING EXCEPT FOR THE LENGTH
LOAD REG D1 WITH 1 FOR CALC. RING LENGTH
DECREMENT LENGTH COUNT
IF COUNTER IS LESS THAT "0" CALCULATION IS FINISHED
MULTIPLY BY 2 TO CALCULATE POWER
CALCULATE NEXT POWER OF 2
0000049C
0000049E
000004AO
000004A4
000004A6
000004AA
000004AE
000004BO
3885
E658
024000FF
4840
29400004
29400014
2A40
60C2
CALCDONE MOVE. W
ROR.W
ANDI.W
SWAP
MOVB.L
MOVE.L
MOVE.L
BRA
D5,RLEN(A4)
113 ,DO
II$OOFF ,DO
DO
DO,RRNGBASE(A4)
DO ,LASTRRNG(A4)
DO,AS
INCREM
MOVE RECEIVER LENGTH OUT ONTO THE RING STACK
MOVE THE WORD BACK INTO ORIGINAL POSISION
CLEAR OUT THE STATUS FOR THE ADDRESS WORD
REFORMAT THE WORDS FOR 68000 COMP ATAB ILITY
PUT RECEIVE DESCRIPTOR BASE ADDRESS ON RING STACK
PUT RVCR DESCRIPTOR BASE ADDRESS IN LAST RVCR RING SPOT
SAVE A COPY OF THE RVCR RING BASE ADD. IN REG AS
GO INCREMENT THE REGISTERS
000004B2
000004 B4
000004B6
000004B8
2010
E 7 58
1200
02010007
COUNT20
000004BC
000004BE
000004C2
000004C4
000004C8
7C01
04010001
6D06
CCFC0002
60F4
000004CA
000004CE
000004D2
000004D4
000004D8
000004DA
000004DE
000004E2
000004E6
39460002
39460022
E658
024000FF
4840
29400008
2940001C
29400018
2C40
COUNT 16
***
232
233
234
235
236
Source
INCREM
00000474
00000476
00000478
0000047 A
0000047C
00000480
***
RECEIVE RING LENGTH CALCULATION
INCREMENT THE PROGRAM IN IT BLOCK ADDRESS BY 4
INCREMENT THE LANCE INIT BLOCK ADDRESS IN Al BY 4
INCREMENT COUNTER BY 4
GO BACK AND LOAD THE NEXT LONG WORD
SEE IF THE COUNT IS EQUAL TO 16
IF NOT BRANCH TO COUNT ~ 20
*.*
TRANSMIT RING LENGTH CALCULATION
NXPOWER
CALCDNE
MOVE. L
ROL.W
MOVE.B
ANDI.B
(AO) ,DO
113 ,DO
DO,D1
11$07,D1
MOVE TRANSMIT RING ADDRESS AND LENGTH TO DO
MOVE XMIT LENGTH TO LOWER BYTE OF LONG WORD
MAKE A COPY OF CODED XMIT RING LENGTH IN REG D1
CLEAR OUT EVERYTHING EXCEPT FOR THE LENGTH
MOVEQ
SUB I • B
BLT.S
MULU
BRA.S
1/01,D6
1101,D1
CALCDNE
112,D6
NXPOWER
LOAD REG D1 WITH 1 FOR CALC. RING LENGTH
DECREMENT LENGTH COUNT
IF COUNTER IS LESS THAT "0" CALCULATION IS FINISHED
MULTIPLY BY 2 TO CALCULATE POWER
CALCULATE NEXT POWER OF 2
MOVE. W
MOVE .vt
ROR.W
ANaI.W
SWAP
MOVE .L
MOVE.L
MOVE.L
MOVE.L
D6, TLEN(A4)
D6, TRINGCNT(A4)
113 ,DO
II$OOFF ,DO
DO
DO, TRNGBASE(A4)
DO, NEXTTRNG( A4)
DO,LASTTRNG(A4)
DO,A6
MOVE XMIT LENGTH OUT ONTO THE RING STACK
MOVE XMIT RING COUNT OUT TO "COUNTER STACK LOCATION
MOVE THE WORD BACK INTO ORIGINAL POSITION
CLEAR THE STATUS OUT OF THE ADDRESS WORD
REFORMAT THE WORDS FOR 68000 COMPATABILITY
PUT XMIT DESCRIPTOR BASE ADDRESS ON RING STACK
PUT XMIT DESCRIPTOR BASE ADD IN NEXT RING SPOT
PUT A COPY OF XMIT DESCR. ADD. IN LAST RING SPOT
SAVE A COPY OF THE BASE ADDRESS IN REG A6
UNITED TECHNOLOGIES MOSTEK 68000 Assembler V1.4
Site 99994 MOSTEK
INITIAL.A68
Line S Location Value
256
257
258
259
260
261
262
263
264
265
000004E8 220D
266
267
000004EA 068100000060
000004FO 2401
268
000004F2 600A
269
270
000004F4 588D
271
000004F6 068200000100
272
000004FC 2202
273
000004FE 008180000000
274
00000504 4841
275
276
00000506 2A8l
~
~
*
*
*
*
*
INITIAL. RRINGINIT
INITIALIZE THE RECEIVE MESSAGE DESCRIPTOR RINGS
*
*
*********************************************************
*** GENERATE RMDO, AND RMDl
MOVE.L
ADD.L
MOVE.L
BRA.S
NEXTRRNG ADDQ. L
ADDl.L
MOVE.L
FIRSTRCV ORL L
SIIAP
MOVE.L
GET COPY OF RVCR RING BASE ADD. AND PUT IT IN Dl
GENERATE RECEIVE BUFFER ADDRESS BY ADDING DISPLACEMENT
CQPY
GO INITIALIZE FIRST RECEIVE RING
AS,Dl
#RllUFDIS ,Dl
Dl,D2
FIRSTRCV
GENERATE NEXT ADDRESS OF MESSAGE DESCRIPTOR
INCREMENT THE BUFFER DISPLACEMENT IIITH BUFFER LENGTH
#$04 ,AS
IIBUFLEN ,D2
D2,D1
#$80000000,01
Dl
Dl,(A5)
SET OlIN BIT IN DESCRIPTOR WORD
MAKE WORDS COMPATABILITY WITH 68000 FORMAT
MOVE LONG WORD INTO DESCRIPTOR RING ADDRESS
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
'".:..
Source
*********************************************************
293
294
295
296
297
298
299
300
301
302
303
304
305
306
***
00000508
0000050A
00000510
00000514
00000518
0000051A
588D
203COOOOOI00
OA40FFFF
06400001
4840
2A80
0000051C
00000520
00000522
00000524
04050001
66D2
598D
294DOOOC
GENERATE RMD2
ADDQ.L
MOVE.L
EORLII
ADDLII
SIIAP
MOVE.L
J
AND RMD3
GENERATE NEXT ADDRESS OF DESCRIPTOR WORD
GET RING BUFFER LENGTH
GET 2'S COMPLEMENT BY EXCLUSIVE ORING AND,
ADDING 1 TO THE RESULT. THIS GIVES BYTE COUNT
tw(E WORDS CAMFATABILITY WITH 68000 FORMAT
MOVE LONG WORD TO MESSAGE DESCRIPTOR 2 AND 3
11$04,A5
IIBUFLEN ,DO
#$FFFF ,DO
11$01 ,DO
DO
DO,(A5)
GENERATE NEXT RECEIVE DESCRIPTOR RING
SUBl.B
BNE.S
SUBQ.L
MOVE.L
11$01,D5
NEXTRRNG
#$04 ,AS
AS,RRNGBOT(A4)
***
DECREMENT THE RECEIVER RING COUNT
IF THERE IS STILL ANOTHER RING LEFT, GO INIT. IT
OR, POINT BACK TO THE BEGINING OF THE ADDRESS
MOVE IT OUT ONTO THE RING STACK
*********************************************************
*
INITIAL. TRINGINIT
INITIALIZE THE TRANSMIT MESSAGE DESCRIPTOR RINGS
*********************************************************
***
00000528
0000052A
00000530
00000532
220E
068100001020
2401
600A
GENERATE TMDO, AND TMDl
MOVE.L
ADD.L
MOVE.L
A6,Dl
#TBUFDIS,Dl
Dl,D2
BRA. S
FIRSTXM
***
GET XMIT RING BASE ADDRESS AND PUT IT IN Dl
GENERATE XMIT BUFFER ADDRESS BY ADDING DISPLACEMENT
COPY IT
GO GENERATE FIRST TRANSMIT RING
~
N
N
N
UNITED TECHNOLOGIES MOSTEK 68000 Assembler V1.4
Site 99994 MOSTEK
INITIAL. A68
Line
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
Location
00000534
00000536
0000053C
0000053E
00000540
Value
588E
068200000100
2202
4841
2C81
Source
NXTTRNG
FIRSTXM
****
00000542
00000544
0000054A
0000054E
00000552
00000554
588E
203C00000100
OA40FFFF
06400001
4840
2C80
04060001
66D8
598E
294E0010
**
GENERATE NEXT ADDRESS OF MESSAGE DESCRIPTOR
MOVE LONG WORD INTO DESCRIPTOR RING ADDRESS
1/$04,A6
IIBUFLEN ,DO
II$FFFF ,DO
1/$01,00
DO
DO,(A6)
GENERATE NEXT ADDRESS OF DESCRIPTOR WORD
GET RING BUFFER LENGTH
GET 2' S COMFLEMENT BY EXCLUSIVE ORING AND,
ADDING 1 TO THE RESULT. THIS GIVES BYTE COUNT
REFORMAT FOR 68000 COMFATABILITY
MOVE LONG WORD TO MESSAGE DESCRIPTOR 2 AND 3
GENERATE NEXT TRANSMIT DESCRIPTOR RING
SUBLB
BNE.S
SUBQ.L
MOVE.L
00000562 4EB90000059A
11$04,A6
IIBUFLEN, D2
D2,D1
D1
D1,(A6)
GENERATE TMD2, AND TMD3
ADDQ. L
MOVE.L
EORLW
ADDLW
SWAP
MOVE.L
***
00000556
0000055A
0000055C
0000055E
ADDQ.L
ADDLL
MOVE.L
SWAP
MOVE.L
11$01,D6
NXTTRNG
11$04,A6
A6, TRNGBOT(A4)
***
DECREMENT THE MESSAGE RING COUNT
IF THERE IS STILL ANOTHER RING LEFT, GO INIT. IT
POINT BACK TO THE BEGINNING OF THE ADDRESS
GO MOVE IT OUT ONTO THE STACK
CALL DIAGNOSTICS ROUTINE
JSR
DIAG
CALL DIAGNOSTICS SUBROUTINE
*******************************************************
*
INITIAL • NORM
INITIALIZES FOR NORMAL OPERATION
*******************************************************
***
00000568 207C0000071C
0000056E 2290
00000570
00000576
00000578
0000057C
0000057E
00000584
00000588
0000058A
00000590
397C00000024
3010
08000002
6712
08EC00010024
08000006
6706
08EC00000024
4EB9000006CC
SET UP FOR NORMAL OPERATION
MOVE.L
MOVE.L
IlpROGIADR,AO
(AO),(A1)
LOOPBACK CHECKING
MOVE.W
IIO,RINGSTAT(A4)
MOVE.W
(AO) ,DO
BTST
1102 ,DO
BEQ. S
GOINIT
BSET.B
1/01,RINGSTAT(A4)
BTST
1106 ,DO
BEQ. S
GOINIT
BSET.B
1100 ,RINGSTAT(A4)
GOINIT
JSR
CSRINIT
GET STARTING ADDRESS OF PROCRAM INIT. BLOCK
MOVE MODE INFORMATION INTO INIT BLOCK
CLEAR OUTRING STATUS REGISTER
GET MODE INFORMATION AND PUT IN REG DO
SEE IF WE ARE IN LOOPBACK MODE
IF NOT GO INITIALIZE THE CSR REGISTERS
IF SO, SET THE LOOP STATUS BIT
SEE IF WE ARE IN INTERNAL LOOP BACK
IF NOT, GO INITIALIZE THE CSR REGISTERS
IF SO, SET THE INTERNAL LOOP STATUS BIT
GO START UP THE LANCE
UNITED TECHNOLOGIES MOSTEK 68000 Assembler V1.4
Site 99994 MOSTEK
INITIAL .A68
Line S Location
N
II)
Co)
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
~
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
Value
00000596 4E71
00000598 60FC
Source
WAIT
NOP
BRA
WAIT
WAIT HERE UNTIL AN INTERRUPT OCCURS
WAIT SOME MORE
*******************************************************
INITIAL. DIAG
LANCE DIAGNOSTIC ROUTINE
*******************************************************
***
0000059A
0000059C
0000059E
000005A4
4281
4282
227 CO0002000
08EC00040024
DIAGNOSTIC MESSAGE GENERATION
***
CLR.L
CLR.L
MOVE.L
BSET.B
Dl
D2
IIIADR,A1
1104,RINGSTAT(A4)
CLEAR OUT REGISTER
CLEAR OUT REGISTER
GET INITIALIZATION
SET DIAGNOSTIC BIT
000005AA 08EC00010024
000005BO 08EC00000024
BSET .B
BSET .B
1101 ,RINGSTAT(A4)
1/00, RINGSTAT(A4)
SET 'TIlE LOOP STATUS BIT
SET THE INTERNAL LOOP STATUS BIT
000005B6
000005BA
000005BC
000005CO
000005 C2
000005C4
000005C6
000005CC
000005CE
000005DO
000005D4
000005D6
000005DC
MOVE.L
MOVE.L
ANDLW
MOVE.L
SWAP
MOVE.L
MOVE.L
ADDQ.W
ADDQ.W
CMP.W
BLT.S
JSR
MOVE.W
NEXTTRNG (A4 ) , AO
(AO),D3
II$OOFF ,D3
D3,D5
D3
D3,AJ
11$ AAAAAAAA, (A3)
1104,D1
1104,A3
II$lC,D1
MESS
CRCGEN
11$20 ,MLENGTH(A4)
MOVE.I;
II$lC,DLENGTH(A4 )
GET XMIT RING BASE ADDRESS
GET XMIT BUFFER BASE ADDRESS
CLEAR STATUS OUT OF WORD
MAKE A COPY OF IT
MOVE WORDS FOR 68000 COMPATABILITY
MOVE XMIT BUFFER ADDRESS INTO ADD REG
MOVE TEST MESSAGE WORD INTO BUFFER ADDRESS
INCREMENT MESSAGE COUNTER BY 4 (BYTES)
INCREMENT THE BUFFER ADDRESS
CHECK TO SEE IF TIlE MESSAGE IS 28 BYTES LONG
IF SO, GO ADD MORE TO TIlE MESSAGE
JUMP TO SOFTWARE CRC GENERATOR
MOVE A MESSAGE LENGTH OF 32 BYTES OUT TO
RING MANG. AREA FOR LATER COMPARISON
MOVE DATA SIZE OUT FOR LATER COMPARISON
206C001C
2610
024300FF
2A03
4843
2643
26BCAAAAAAAA
5841
584B
OC41001C
6DFO
4EB900000706
397 C00200038
DIAG
MESS
000005E2 397C001C0034
***
TEST INTERNAL LOOPBACK WITH TRANSMIT CRC ENABLED
000005E8
000005EC
000005EE
000005FO
00458300
2085
5888
20BCFFE40000
ORI.W
MOVE.L
ADDQ.L
MOVE.L
11$8300,D5
D5,(AO)
1104,AO
II$FFE40000, (AD)
000005F6
000005F8
000005FC
00000602
00000608
5588
32BC8044
4EB9000006CC
08ACOO050024
67F8
SUBQ.L
MOVE.W
JSR
BCLR.B
BEQ
1102,AO
11$8044,(A1)
CSRINIT
1105 ,RINGSTAT(A4)
CHECK1
CHECKl
D1
D2
STARTING ADDRESS
IN STATUS REG
***
SET OWNERSHIP BIT IN XMIT RING
MOVE TMD1 TO RING LOCATION
GENERATE ADDRESS OF TMD2
MOVE BYTE COUNT(28 BYTES) TO TMD2 ON DESCRIPTOR
RING AND CLEAR OUT TMD3
POINT TO TMD1
SET UP INIT BLOCK TO INTERNAL LOOPBACK
GO START UP THE LANCE
SEE IF THIS PORTION OF THE TEST IS COMPLETE
CHECK AGAIN
'!:o
~
....
I\)
UNITED TECHNOLOGIES MOSTEK 68000 Assembler Vl.4
Site 99994 MOSTEK
INITIAL .A68
Line S Location
409
410
411
0000060A
412
00000610
413
00000614
414
0000061A
415
416
417
418
0000061E
419
00000622
420
00000624
421
00000626
422
423
0000062C
424
0000062E
425
00000632
426
00000638
427
0000063E
428
429
430
00000640
431
00000646
432
0000064A
433
00000650
434
435
436
437
00000654
00000658
438
0000065A
439
0000065C
440
441
00000662
442
443
00000664
444
00000668
445
0000066E
446
447
00000674
448
449
00000676
450
0000067 C
451
00000680
452
00000686
453
454
455
456
0000068A
457
00000690
458
00000694
459
Value
Source
***
247C00004002
34BCOOOO
267C00004000
36BCOOFF
***
TURN OFF THE LANCE
***
MOVE.L
IIRAP ,A2
MOVE.W
IICSRO,(A2)
MOVE.L
IIRDP ,A3
MOVE.W
II$OOFF,(A3)
SELECT LANCE' S REGISTER ADDRESS PORT TO WRITE TO
LOAD REGISTER ADDRESS PORT OF LANCE WITH CSRO
SELECT LANCE' S REGISTER DATA PORT TO WRITE TO
TURN OFF THE LANCE
TEST INTERNAL LOOPBACK :WITH TRANSMIT eRe DISABLED
00458300
3085
5488
20BCFFEOOOOO
ORLW
MOVE.W
ADDQ.L
MOVE.L
#$8300,D5
D5,(AO)
#02,AO
#$FFEOOOoo,(AO)
5588
32BC804C
4EB9000006CC
08AC00050024
67F8
SUBQ.L
MOVE.W
::rSR
BCLR.B
BEQ
1I02,AO
#$804C,(A1)
CSRINIT
1105 ,RINGSTAT(A4)
CHECK2
CHECK2
*••
247C00004002
34BCOOOO
267C00004000
36BCOOFF
TURN OFF THE LANCE
MOVE.L
IIRAP,A2
IICSRO, (A2)
MOVE.W
MOVE.L
IIRDP,A3
MOVE.W
II$OOFF, (A3)
SET OWNERSHIP BIT IN XMIT RING
MOVE TMDl TO RING LOCATION
GENERATE ADDRESS OF TMD2
MOVE BYTE COUNT( 32 BYTES) TO TMD2 ON DESCRIPTOR
RING AND CLEAR OUT TMD3
POINT TO TMD1
SET UP INIT BLOCK TO INTERNAL LooPBACK
GO START UP THE LANCE
SEE IF THIS PORTION OF THE TEST IS COMPLETE
CHECK AGAIN
SELECT LANCE' S REGISTER ADDRESS PORT TO WRITE TO
LOAD REGISTER ADDRESS PORT OF LANCE WITH CSRO
SELECT LANCE'S REGISTER DATA PORT TO WRITE TO
TURN OFF THE LANCE
TEST INTERNAL LOOPBACK WITH XMIT CRC ENABLED AND COLLISION FORCE ON
00458300
3085
5488
20BCFFE40000
5588
SUBQ.L
1I02,AO
32BC8054
4EB9000006CC
08AC00050024
67F8
MOVE.W
JSR
BCLR.B
BEQ
#$8054, (Ai)
CSRINIT
1105,RINGSTAT(A4)
CHECK)
SET UP INIT BLOCK TO INTERNAL LOOPBACK
GO START UP THE LANCE
SEE IF THIS PORTION OF THE TEST IS COMPLETE
CHECK AGAIN
247C00004002
34 BCOOOO
267 C00004000
36BCOOFF
08AC00000024
00458300
3085
CHECK)
11$8300,D5
D5, (AO)
#02,AO
II$FFE40000, (AO)
.**
SET OWNERSHIP BIT IN XMIT RING
MOVE TMDl TO RING LOCATION
GENERATE ADDRESS OF TMD2
MOVE BYTE COUNT(28 BYTES) TO TMD2 ON DESCRIPTOR
RING AND CLEAR OUT TMD3
POINT TO TMDl
ORLW
MOVE.W
ADDQ.L
MOVE.L
.**
TURN OFF THE LANCE
***
MOVE.L
#RAP,A2
MOVE.W
#CSRO,(A2)
MOVE.L
IIRDP ,A3
~IOVE. W
II$OOFF, (A3)
**.
TEST EXTERNAL LOOPBACK
BCLR.B
ORI.W
MOVE.W
SELECT LANCE'S REGISTER ADDRESS PORT TO WRITE TO
LOAD REGISTER ADDRESS PORT OF LANCE WITH CSRO
SELECT LANCE'S REGISTER DATA PORT TO WRITE TO
TURN OFF THE LANCE
***
1100,RINGSTAT(A4)
#$8300,D5
D5,(AO)
CLEAR THE INTERNAL LOOP STATUS BIT
SET OliNERSHIP B IT IN XMIT RING
MOVE TMDl TO RING LOCATION
UNITED TECHNOLOGIES MOSTEK 68000 Assembler V1.4
Site 99994 MOSTEK
INITIAL.A68
Line S Location Value
460
00000696 5488
461
00000698 20BCFFE40000
462
0000069E 32BC8004
463
000006A2 4EB9000006CC
464
000006A8 08ACOO050024
465
000006AE 67F8
466
467
468
000006BO 247COOO04002
469
000006B6 34BCOOOO
470
000006 BA 267 COOO04000
471
472
000006CO 36BCOOFF
473
474
000006C4 08ACOO040024
000006CA 4E75
475
476
Source
CHECK4
***
ADDQ.L
MOVE.L
1102,AO
II$FFE40000, (AO)
MOVE.W
JSR
BCLR.B
BEQ
11$8004,(A1)
CSRINIT
1105, RINGSTAT(A4)
CHECK4
GENERATE ADDRESS OF TM02
MOVE BYTE COUNT(28 BYTES) TO TMD2 ON DESCRIPTOR
RING AND CLEAR OUT TM03
SET UP INIT BLOCK TO INTERNAL LOOPBACK
GO START UP THE LANCE
SEE IF THIS PORTION OF THE TEST IS COMPLETE
CHECK AGAIN
***
TURN OFF THE LANCE
MOVE.L
IIRAP ,A2
MOVE.W
IICSRO,(A2)
MOVE.L
IIRDP,A3
MOVE.W
II$OOFF, (A3)
BCLR.B
RTS
SELECT LANCE'S REGISTER ADDRESS PORT TO WRITE TO
LOAD REGISTER ADDRESS PORT OF LANCE WITH CSRO
SELECT LANCE'S REGISTER DATA PORT TO WRITE TO
TURN OFF THE LANCE
1104 ,RINGSTAT(A4)
CLEAR DIAGNOSTIC BIT
477
..
~
N
III
~
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
**X****
END OF INITIALIZATION AND DIAGNOSTIC ROUTINE
******
*******************************************************
*
INITIAL .DIAG. CSRINIT
INITIALIZES THE CONTROL AND STATUS REGISTERS
*******************************************************
000006CC
000006DO
000006D6
000006DA
000006EO
000006E6
000006E8
000006EC
000006EE
000006FO
000006F4
000006F8
000006FC
00000700
00000704
48E7FFFF
207C00004002
30BCOOOl
227C00004000
223C00002000
3281
30BC0002
4841
3281
30BC0003
32BC0006
30BCOOOO
32BC0043
4CDFFFFF
4E75
CSRINIT
***
MOVEM.L
MOVE.L
MOVE.W
MOVE.L
MOVE.L
MOVE.W
MOVE.W
SWAP
MOVE.W
MOVE.W
MOVE.W
MOVE.W
MOVE.W
MOVEM.L.
RTS
AO-A7 IDO-D7 ,-(A7)
IIRAP,AO
IICSR1,(AO)
IIRDP,A1
IIIADR,D1
D1,(A1)
IICSR2,(AO)
D1
D1,(A1)
IICSR3,(AO)
II$OO06,(A1)
IICSRO, (AO)
11$0043, (AI)
(A7)+,DO-D7/AO-A7
END OF CSRINIT SUBROUTINE
SAVE OLD REGISTERS
SELECT LANCE'S REGISTER ADDRESS PORT TO WRITE TO
LOAD REGISTER ADDRESS PORT OF LANCE WITH CSRI ADD.
SELECT LANCE'S REGISTER DATA PORT TO WRITE TO
GET INITIALIZATION BLOCK BASE ADDRESS
LOAD INITIALIZATION BLOCK STARTING ADDRESS IN CSRI
SELECT LANCE REGISTER ADDRESS PORT TO WRITE TO
GET HIGH ORDER BYTE OF INITIALIZATION ADDRESS
LOAD HIGH ORDER BYTE OF INIT. BLOCK INTO CSR2
LOAD REGISTER ADDRESS PORT OF LANCE WITH CSR3
INITIALIZE LANCE TO INTERFACE TO MK68000 FORMAT
LOAD REGISTER ADDRESS PORT OF LANCE WITH CSRO
INITIALIZES CSRO, LANCE IS NOW READY TO RUN
RETRIVE OLD REGISTERS
RETURN FROM THIS SUBROUTINE
***
*******************************************************
*
INITIAL. DIAG. CRC
CYCLE REDUNDENCY CHECK SOFTWARE cENERATIaN
~
I\)
UNITED TECHNOLOGIES MOSTEK 68000 Assembler V1.4
Site 99994 MOSTEK
INITIAL .A68
Line S Location
Value
511
512
*******************************************************'
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
N
I\)
Source
*
00000706
0000070A
00000710
00000716
000007lA
48E7FFFF
207C00003094
20BCB1109280
4CDFFFFF
4E75
CRCGEN
***
000007lC
00000734
00000736
00000738
0000073A
004400040000
0100
0100
0060
1020
0000073C 00000000
MOVEM. L
MOVE. L
MOVE.L
MOVEM.L
RTS
AO-A7 IDO-D7 ,-(A7)
11$ 3094 ,AO
II$B1109280,(AO)
(A7)+,DO-D7/AO-A7
END OF CRCGEN SUBROUTINE
PROGIADR
RBUFLEN
TBUFLEN
RBUFDISP
TBUFDISP
DC.W
DC.W
DC.W
DC. W
DC. W
SAVE OLD REGISTERS
GET ADDRESS OF CRC LOCATION
MOVE CRe FOR AAA ••• AAA OUT TO BUFFER
RETRIVE OLD REGISTERS
RETURN FROM THIS SUBROUTINE
***
MODE ,PADRI ,PADR2 ,PADR3 ,LADRI ,LADR2 ,LADR3 ,LADR4 ,RDRAl ,RDRA2, TDRAl, TDRA2
BUFLEN
BUFLEN
RBUFDIS
TBUFDIS
END
no errors detected.
en
Options in effect:
NOA,BRL,NOCEX,CL,FRL ,Me ,MD,NOMEX,O ,NOPCO,NOPCS ,LIST ,NOSTR,FORMAT ,NOMOTOROLA
UNITED TECHNOLOGIES MOSTEK 68000 Assembler V1.4
Site 99994 MOSTEK
INITIAL .A68
SYMBOL TAllLE LISTING
NAME
...
~
~
~
'"
BUFLEN
CALCDNE
CALCDONE
CHECKI
CHECK2
CHECK3
CHECK4
CLEAR
COUNT16
COUNT20
CRCGEN
CSRO
CSR1
CSR2
CSR3
CSRINIT
DATINTR
DIAG
DLENGTH
FIRSTRCV
FIRSTXM
GOINIT
IADR
INCREM
LADRI
LADR2
LADR3
LADR4
LANINTR
LASTRRNG
LASTTRNG
LOOPMCNT
LOOPXADD
MESS
MLENGTH
MODE
MORE
NEXTRRNG
NEXTTRNG
NXPOWER
NXTPOWER
NXTTRNG
ONE
PADR1
PADR2
ATTR
XDEF
XDEF
XDEF
XDEF
XREF
XDEF
XDEF
XREF
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
SECT
VALUE
00000100
000004CA
0000049C
00000602
00000638
0000066E
000006A8
00000400
0000047C
000004B2
00000706
00000000
00000001
00000002
00000003
000006CC
00000000
0000059A
00000034
000004FE
0000053E
00000590
00002000
00000474
00000008
00000000
00000000
00000000
00000000
00000014
00000018
00000020
00000028
000005C6
00000038
00000044
0000002C
000004F4
OOOOOOlC
000004BE
00000490
00000534
0000002E
00000004
00000000
!...
UNITED TECHNOLOGIES MOSTEK 68000 Assembler Vl.4
Site 99994 MOSTEK
INITIAL. A68
SYMBOL TA8LE LISTING
NAME
ATTR
PADR3
PROGIADR
RAP
....
N
N
CO
RBUFDIS
RBUFDISP
RBUFLEN
RDP
RDRAl
RDRA2
RETURN
RINGSTAT
RINGSTK
RLEN
RRNGBASE
RRNGBOT
STACK
TBUFDIS
TBUFDISP
TBUFLEN
TDRAl
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
TDRAZ
TLEN
TRINGCNT
TRNGBASE
TRNGBOT
WAIT
XDEF
XDEF
XDEF
XDEF
SECT
VALUE
00000000
0000071C
00004002
00000060
00000738
00000734
00004000
00002018
00006000
0000046A
00000024
000038CO
00000000
00000004
OOOOOOOC
0000387C
00001020
0000073A
00000736
00002058
00004000
00000002
00000022
00000008
00000010
00000596
8.2 APPENDIX B, LANCE INTERRUPT ASSEMBLY CODE
The following pages provide a listing of the LANCE interrupt assembly code.
1·229
8·15
'!:
'"
UNITED TECHNOLOGIES MOSTEK 68000 Assembler V1.4
Site 99994 MOSTEK
LEXCEPT .A68
Line S Location
....
~
W
C)
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
9 0
100
11 0
12 0
13 0
14 0
15 0
16 0
17 0
18 0
19 0
20 0
21 0
22 0
23 0
24 0
25 0
26 0
27 0
28 0
29 0
30 0
31 0
32 0
33 0
34 0
35 0
36 0
37 0
38 0
39 0
40 0
41 0
42 0
43 0
44 0
45 0
46 0
47 0
48 0
49 0
50 0
51 0
Value
Source
*****************************************************************+
*+**************************************************************+*
••
••
MODULE NAME: LEXCEPT
**
AUTHOR:
JIM FONTAINE
.*
**
PROGRAM: LANCE
**
.*
LATEST REVISION DATE: JANUARY 20, 1984
••
..
**
••
••
••
..-..-
******************************************************************
.*
**
**
THIS MODULE IS THE LANCE INTERRUPT HANDLING
DESCRIPTION:
ROUTINE. IT WILL EXAMINE THE CONTROL AND STATUS REGISTER
•• OF THE LANCE AND DETERMINE WHAT CAUSED LANCE TO INTERRUPT
** THE HOST PROCESSOR. AFTER IT DETERMINED WHAT CAUSED THE
THE INTERRUPT CAUSING CONDITION IT WILL SERVICE THE CON•• DITION OR REPORT THE ERROR.
*.
••
••
••
••
****************************************************************+*
*****************************************************************+
*************************************************
•
EQUATE TABLE
*************************************************
00003A20
OUTPUT
EQU
00003B20
MESSAGE
EQU
0000003C
TESTTMD1 EQU
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
XDEF
$3A20
$3B20
$3C
OUTPUT
MESSAGE
LANINTR
CRCERR
XRINGFIX
CLEANUP
PCKDONE
UNITED TECHNOLOGIES MOSTEK 68000 Assembler V1.4
Site 99994 MOSTEK
LEXCEPT • A68
Line S Location
...
N
~
CD
....
.!.
52 0
53 0
54 0
55 0
56 0
57 0
58 0
59 0
60 0
61 0
62 0
63 0
640
65 0
66 0
67 0
68 0
69 0
70 0
710
72 0
73 0
74 0
75 0
76 0
77 0
78 0
79 0
800
81 0
820
83 0
84 0
85 0
86 0
87 0
88 0
89 0
90 0
91 0
92 0
93 0
94 0
95 0
96 0
97 0
98 0
99 0
100 0
101 0
102 0
Value
Source
*
*
KEYWORD VALUE REFERENCE
XREF
XREF
RAP
RDP
XREF
XREF
XREF
XREF
CSRO
CSR1
CSR2
CSR3
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
RUN
TLEN
RRNGEASE
TRNGEASE
RRNGBOT
TRNGBOT
LASTRRNG
LASTTRNG
NEXTTRNG
LOOPMCNT
TRINGCNT
RINGSTAT
MLENGTH
MORE
ONE
LOOPXADD
DLENGTH
*
SUBROUTINE CALLS REFERENCE
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
BABLSUB
CERRSUB
MISSSUB
MERRSUB
FRANSUB
CRCSUB
OFLOSUB
BUFFSUB
RTRYSUB
STOP
LCARRSUB
COLLSUB
UFLOSUB
BUFRSUB
IDONSUB
XREF
XREF
XREF
XREF
SIZEERR
XMITSERV
PACKERR
CRCEAD
~
a>
UNITED TECHNOLOGIES MOSTEK 68000 Assembler Vl.4
Site 99994 MOSTEK
LEXCEPT .A68
Line
103
104
105
106
107
108
109
S Location
0
0
0
0
0
Value
00000800
110
...;.;.
W
II)
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
XREF
XREF
LP ACKERR
LMESSBAD
ORG
$800
*******************************************************
*
III
112
113
114
115
116
117
118
119
Source
*
*
LANCE INTERRUPT ERROR CHECKING SUBMODULE
LEXCEPT • ERROR
*
*******************************************************
00000800
00000806
oo00080A
00000810
00000814
0000081A
OOOO081C
0000081E
00000822
397CCCCCFFFF
48E7FFFE
247 CFFFFFFFF
34BCFFFF
267CFFFFFFFF
3413
3E02
0247FFBF
3687
LANINTR
ANOr.W
MOVE.W
**
0802000E
6706
4EB9FFFFFFFF
0802000D
6706
4EB9FFFFFFFF
0802000C
4EB9FFFFFFFF
0802000B
6706
4EB9FFFFFFFF
#$CCCC,WOPMCNT(A4 )
DO-D7/Ao-A6,-(A7)
URAP,AZ
#CSRO,(AZ)
#RDP,A3
(A3),D2
D2,D7
#$FFBF,D7
D7,(A3)
TEST
SAVE REGS ON STACK
SELECT LANCE'S RAP TO WRITE INTO
LOAD CSRO ADDRESS IN REG ADD PORT
WAD "REG DATA PORT·· ADDRESS INTO REG A3
MOVE CONTENTS OF CSRO INTO REG D2
GET A WORKING COPY OF CSRO
MASK OUT INTRRRUPT ENABLE BIT
DISABLE ··INTR. ENABLE" BIT & CLEAR OUR TIlE REST·
DETERMINE WHAT CAUSED TIlE INTERRUPT
00000824 0802000F
00000828 672E
oo00082A
0000082E
00000830
00000836
oo00083A
0000083C
00000842
00000846
oooo084C
00000850
00000852
MOVE. W
MOVEM.L
MOVEA.L
MOVE.W
MOVEA.L
MOVE.W
MOVE.W
ERROR
CERR
MISS
MERR
*
BTST
BEQ.S
#$OF ,D2
XMITCK
CHECK IF ··ERROR·· BIT IS SET IN CSRO
IF IT ISN'T, BRANCH TO XMIT INTR. CRECK
BTST
BEQ.S
JSR
BTST
BEQ.S
JSR
BTST
JSR
BTST
BEQ.S
JSR
U$OE,D2
CERR
EABLSUB
#$OD,D2
MISS
CERRSUB
#$OC,D2
MISSSUB
#$OB,D2
XMITCK
MRRRSUB
CHECK IF IT IS A BABBLE ERROR
IF NOT, CRECK IF IT IS A COLLISION ERROR
IF IT IS, JUMP TO BABBLE RANDLE ROUTINE
CHECK IF IT IS A COLLISION ERROR
IF NOT, CHECK IT IT IS A MISSED PACKET ERROR
IF IT IS, JUMP TO COLLISION RANDLE SUBR.
CHECK IF IT IS A MISSED PACKET ERROR
IF IT IS, JUMP TO MISSED PACKET SUBR.
CHECK IT IS A MEMORY ERROR
IF NOT, CHECK FOR XMIT INTR BIT SET
IF IT IS, JUMP TO MEMORY ERROR SUBR.
***********************************************
*
*
*
*
TRANSMIT INTERRUPT RANDLING ROUTINE
LEXCEPT .XMIT
*
*
*
*
***********************************************
00000858 08020009
0000085C 67ooo0BE
XMITCK
BTST
BEQ
#$09,D2
RVCRINT
CHECK FOR ··TRANSMIT INTR" BIT SET
IF IT ISN'T SEE IF RECEIVE INTERRUPT IS SET
UNITED TECHNOLOGIES MOSTEK 68000 Assembler V1.4
Site 99994 MOSTEK
LEXCEPT .A68
Line S Loca t ion
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
...
~
Co>
Co>
174
175
176
177
178
179
~
co
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
Val ue
Source
00000860
00000864
00000866
00000868
0000086A
0000086E
00000870
00000874
00000878
0000087 A
206CFFFF
2248
5488
3010
0800000C
6704
526CFFFF
0800000B
6704
526CFFFF
0000087E
00000882
00000884
00000886
00000888
0000088C
0000088E
00000894
00000896
0000089A
000008AO
000008A4
000008A6
000008AC
000008B2
000008B6
000008B8
000008SE
000008C4
000008C8
000008CA
000008DO
000008D6
000008DA
000008DC
000008E2
0800000E
6764
5888
3010
0800000A
6712
4EB9FFFFFFFF
3200
024103FF
4EB9FFFFFFFF
0800000B
670C
4EB9FFFFFFFF
4EB9FFFFFFFF
0800000C
670C
4EB9FFFFFFFF
4EB9FFFFFFFF
0800000E
670C
4EB9FFFFFFFF
4EB9FFFFFFFF
0800000F
670C
4EB9FFFFFFFF
4EB9FFFFFFFF
ERRORTST BTST
BEQ.S
ADD.L
MOVE.II
BTST
SEQ.S
JSR
MOVE.II
ANDI-II
JSR
LCARERR BTST
BEQ.S
JSR
JSR
LATECOLL BTST
SEQ.S
JSR
JSR
UFLOERR BTST
BEQ.S
JSR
JSR
NOBUFF
BTST
BEQ.S
JSR
JSR
000008E8
000008EE
000008FO
000008F2
000008F4
000008F8
000008FA
000008FC
082C0001FFFF
6712
2611
E15B
163COOOO
E05B
4843
2943FFFF
LOOPTEST BTST.B
BEQ.S
MOVE.L
ROL.II
MOVE.B
ROR.W
SIIAP
MOVE.L
ONETES'!:
******
*******
MOVE.L
MOVE.L
ADD.L
MOVE.II
BTST
BEQ.S
ADD.II
BTST
BEQ.S
ADD.W
LASTTRNG(A4) ,AO
AO,A1
#$02,AO
(AO) ,DO
#$OC,DO
ONETEST
#$01 ,MORE(A4)
#$OB, DO
ERRORTST
#$Ol,ONE(A4)
LOAD UP NEXT XMIT RING ADDRESS
GET A 1I0RKING COPY OF TIlE RING ADDRESS
GENERATE ADDRESS OF TMD1 (RING STATUS)
GET STATUS (TMD1) AND PUT IT IN REG DO
CHECK FOR '"MORE" BIT SET
IF NOT, GO CHECK "ONE'" BIT
IF SO, UPDATE '"MORES" COUNTER
CHECK FOR '"ONE" BIT SET
IF NOT, GO CHECK "ERROR'" BIT
IF SO, UPDATA '"ONE" COUNTER
TRANSMISSION ERROR DETERMINATION
LOOPBACK TESTING
*****
CHECK FOR "ERROR'" BIT SET
IF NOT, CONTINUE IIITR TRANSMIT ROUTINE
GENERATE ERROR STATUS ADDRESS
GET ERROR STATUS AND PUT IT IN REG DO
CHECK FOR "RETRY'" ERROR BIT SET
IF NOT, CHECK FOR LOSS OF CARRIER
IF SO, STOP LANCE AND TAKE CARE OF ERROR
MOVE TIME DOMAIN REFLECTOMETRY VALUE
MASK OFF STATUS BITS
JUMP TO RETRY ERROR SUBROUTINE
CHECK FOR "LOSS OF CARRIER" BIT SET
IF NOT, CHECK FOR LATE COLLISION
IF SO, STOP AND TAKE CARE OF IT
JUMP TO "LOSS OF CARRIER" SUBROUTINE
CHECK FOR "LATE COLLISION'" BIT SET
IF NOT, CHECK FOR UNDER FLOII
IF SO, STOP AND TAKE CARE OF ERROR
JUMP TO '"LATE COLLISION" SUBROUTINE
CHECK FOR '"UNDERFLOII'" BIT SET
IF NOT, CHECK FOR BUFFER ERROR
IF SO, STOP AND TAKE CARE OF IT
JUMP TO '"UNDERFLOII'" SUBROUTINE
CHECK FOR "BUFFER ERROR'" BIT SET
IF NOT, CONTINUE IIITH LOOPTEST
IF SO, STOP AND TAKE CARE OF ERROR
JUMP TO '"BUFFER ERROR" SUBROUTINE
#$OE,DO
LOOPTEST
#$04,AO
(AO) ,DO
#$OA,DO
LCARERR
STOP
DO,Dl
11$03FF ,Dl
RTRYSUB
#$OB,DO
LATECOLL
STOP
LCARRSUB
#$OC,DO
UFLOERR
STOP
COLLSUB
#$OE,DO
NOBUFF
STOP
UFLOSUB
#$OF ,DO
LOOPTEST
STOP
BUFRSUB
********
#l,RINGSTAT(A4)
FINISH
(A1) ,D3
#8,D3
1I00,D3
118,D3
D3
D3 ,LOOPXADD( A4 )
SEE IF lIE ARE IN THE LOOP BACK MODE
IF NOT, FINISH UP IIITH THE XMIT ROUTINE
IF IN LOOPBACK, GET XMIT BUFFER ADDRESS
POSITION TIlE UPPER BYTE OF LOIIER 1I0RD FOR CLEAR
CLEAR OUT STATUS PART OF RMD1
REPOSITION BYTES
REFORMAT THE LONG 1I0RD ADD FOR 68000 COMPATABIOLITY
SAVE A COPY ON TIlE STACK FOR LATER
~
UNITED TECHNOLOGIES MOSTEK 68000 Assembler VI. 4
Site 99994 MOSTEK
LEXCEPT .A68
Line S Location
N
Co)
~
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
Value
Source
00000900 601A
BRA.S
***
00000902
00000908
0000090C
0000090E
00000914
00000918
066C0001FFFF
B3ECFFFF
660A
296CFFFFFFFF
60000192
50ACFFFF
RVCRINT
GO CHECK IF RECEIVE INTER. BIT IS SET
TRANSMIT RING RESTORATION
ADDI.W
CMPA.L
BNE.S
MOVE.L
BRA
ADD.L
FINISH
INCRE
***
11$01, TRINGCNT(A4)
INCREMENT THE NUMBER OF AVAILABLE XMIT RINGS
TRNGBOT (A4 ) ,AI
SEE IF WE ARE ABOUT TO WRAP AROUND
IF NOT, INCREMENT THE RING POINTER
INCRE
TRNGBASE(A4) ,LASTTRNG(A4) MOVE THE RING BASE ADD ONTO LASTTRNG STACK SPOT
BRANCH TO CONT
IDONCHK
11$08 ,LASTTRNG(A4)
UPDATE LAST RING ADDRESS
END OF TRANSMIT INTERRUPT ROUTINE
****'***************************************
*
RECEIVE INTERRUPT HANDLING ROUTINE·
LEXCEPT .RVCR
*
*******************************************
0000091C 0802000A
00000920 67000186
RVCRINT
BTST
BEQ
II$OA,D2
IDONCHK
CHECK FOR "RECEIVE INTR" BIT SET
IF IT ISN'T, SEE IF INITIALIZATION DONE IS SET
00000924
00000928
0000092A
0000092C
0000092E
RVCRBUF
MOVE. L
MOVE.L
ADDQ.L
MOVE.W
SUBA.L
LASTRRNG(A4) ,AO
AO,A5
11$06,A5
(AS) ,D1
1104 ,AS
GET DESCRIPTOR RING STARTING ADDR. (RMDO)
MAKE A WORKING COPY OF IT IN REG AS
GENERATE ADDRESS OF ROM3
GET MESSAGE BYTE COUNT (MCNT)
GENERATE ADDRESS RMDl
206CFFFF
2A48
5C8D
3215
9BFC00000004
ERROR CHECKING
00000934 3015
00000936 0800000E
0000093A 66000110
MOVE.W
BTST
BNE
***
GET RECEIVED MESSAGE STATUS (ROM1)
SEE IF "ERROR" B IT IS SET
IF IS, FIND OUT WHAT CAUSED THE ERROR
CHECK TO SEE IF WE ARE IN LOOPBACK MODE
BTST.B
BEQ
0000093E 082C0001FFFF
00000944 670000BO
***
***
(AS) ,DO
II$OE ,DO
RECVERR
111,RINGSTAT(A4)
NOLOOP
LOOPBACK MESSAGE SIZE CHECK
CHECK TO SEE IF WE ARE IN LOOP BACK MODE
IF WE ARE 1I0T IN LOOPBACK MODE CONTINUE
***
248
249
250
251
252
253
254
25S
CMP.W
BEQ
JSR
00000948 B26CFFFF
0000094C 67000008
00000950 4EB9FFFFFFFF
MLENGTH(A4) ,01
PACKCHK
SIZEERR
LOOPBACK PACKET CHECK
00000956 08000009
PACKCHK
BTST
1109 ,DO
SEE IF RVCR MESSAGE IS EQUAL TO XMIT MESSAGE
IF SO CONTINUE
IF NOT) SERVICE ERROR ROUTINE
***
CHECK IF START OF PACKET BIT IS SET IN RMD1
UNITED TECHNOLOGIES MOSTEK 68000 Assembler VI. 4
Site 99994 MOSTEK
LEXCEPT .A68
Line
256
257
258
259·
260
261
262
263
264
265
266
267
268
269
270
Location
0000095A
0000095C
00000962
00000966
00000968
Value
6606
4EB9FFFFFFFF
08000008
6606
4EB9FFFFFFFF
0000096E
00000970
00000972
00000976
00000978
0000097 A
2610
E15B
l63COOOO
E05B
4843
3643
0000097C
00000980
00000982
00000986
00000988
0000098A
0000098C
0000098E
00000994
00000996
00000998
0000099C
0000099E
322CFFFF
72lC
226CFFFF
3A13
3Cll
BC45
6706
4EB9FFFFFFFF
548B
5489
04410002
6F02
60E6
N
Co>
en
~
000009M
000009AC
000009AE
000009BO
000009B2
000009B4
000009BA
000009BE
000009CO
000009C2
000009C4
7204
3A13
3Cll
BC45
6706
4EB9FFFFFFFF
04410002
6F06
548B
5489
60E6
INCR
MOVE.W
MOVE.L
MOVE.L
MOVE. W
MOVE.W
CMP.W
BEQ.S
JSR
ADDQ.L
ADDQ.L
SUBLW
BLE.S
BRA.S
MORECRC
IS, GO CHECK TBE END OF PACKET BIT
IS NOT JUMP TO PACKET ERROR SUBR.
IF END OF PACKET BIT IS SET
IS, GO GENERATE BUFFER ADDRESS
IS NOT, JUMP TO PACKET ERROR
***
MOVE RVCR BUFFER ADDRESS INTO REG D3
MOVE SECOND BYTE INTO POSITION TO BE CLEARED
CLEAR OUT THE STATUS
REPOSITION BYTES
REFORMAT FOR 68000 COMPATIBILITY
MOVE ADDRESS INTO AN ADDRESS REGISTER
(AO) ,D3
1I08,D3
11$00,D3
11$08,03
D3
D3,A3
DLENGTH(A4) ,Dl
II$OlC,Dl
LOOPXADD(A4) ,AI
(A3) ,D5
(AI) ,D6
D5,D6
INCR
LMESSBAD
11$2,A3
1I$2,Al
11$02,Dl
CRCCK
MOREWOS
SOFTWARE CRe TEST
CRCCK
DECR
MOVE.L
ROL.W
MOVE.B
ROR.W
SWAP
MOVE
LOOPBACK XMIT-RveR WORn COMPARISON
MOREWDS
***
IF IT
IF IT
CHECK
IF IT
IF IT
BITTST
LPACKERR
1108 ,DO
BADDGEN
LPACKERR
GET RVeR BUFFER STARTING ADDRESS
BADDGEN
***
000009AO 082C0004FFFF
000009A6 670000lE
BNE.S
JSR
BTST
BNE.S
JSR
BITTST
***
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
Source
***
GET MESSAGE DATA LENGTH
LOAD D1 WITH 28 (28 BYTES IS THE DATA SIZE)
GET LOOPBACK XMIT BUFFER STARTING ADDRESS
GET ONE WORD OF RVCR BUFFER MESSAGE
GET ONE WORD OF XMIT BUFFER MESSAGE
SEE IF TBE TWO WORDS ARE IDENTICAL
IF THEY ARE EQUAL, INCREMENT THE ADDRESS
IF THEY ARE NOT EQUAL, JUMP TO ERROR MESSAGE
OTHERWISE, INCREMENT ADDRESS
INCREMENT TBE ADDRESS
DECREMENT MESSAGE COUNT
IF NO MORE WORDS, CHECK THE CRC
GO GET SOME MORE WORDS TO COMPARE
***
BTST.B
BEQ
1104,RINGSTAT(A4)
XRINGFIX
SEE IF WE ARE IN LANCE DIAGONOSTICS
IF NOT, GO FIX UP RINGS
MOVE.L
MOVE. W
MOVE.W
CMP.W
BEQ.S
JSR
SUBLW
BLE.S
ADDQ.L
ADDQ.L
BRA.S
1I$004,Dl
(A3) ,D5
(AI) ,D6
D5,D6
DECR
CRCBAD
IIOZ·,Dl
XRINGFIX
112,A3
112 ,AI
LOAD Dl WITH 4 (4 BYTES IS THE CRC SIZE)
GET ONE WORD OF RVCR BUFFER MESSAGE
GET ONE WORD OF XMIT BUFFER MESSAGE
SEE IF THE TWO WORDS ARE IDENTICAL
IF TBEY ARE EQUAL, GO DECREMENT THE COUNT
IF THEY ARE NOT EQUAL, JUMP TO ERROR MESSAGE
DECREMENT MESSAGE COUNT
IF NO MORE WORDS, FIX UP THE XMIT RING
OTHERWISE, INCREMENT ADDRESS
INCREMENT THE ADDRESS
MOREeRC
GO GET SOME MORE WORDS TO COMPARE
XMIT RING RESTORATION
000009C6 082C0004FFFF
XRINGFIX BTST.B
1104,RINGSTAT(A4)
SEE IF WE ARE IN LANCE DIAGONOSTICS
~
UNITED TECHNOLOGIES MOSTEK 68000 Assembler V1.4
Site 99994 MOSTEK
LEXCEPT .A68
Line
307
308
309
310
311
312
313
314
315
316
317
318
319
320
Location Value
000009CC 660000CC
Source
000009DO
000009D6
000009DA
000009DE
000009EO
RINGFIX
066COOOIFFFF
206CFFFF
BIECFFFF
6AOC
06AC00000008
FFFF
000009E8 60000096
000009EC 296CFFFFFFFF
000009F2 6000008C
********
321
322
...N
w
'"
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
RINGGEN
**
000009F6 08000009
000009FA 6718
000009FC 08AC0002FFFF
00000A02
00000A06
OOOOOAOA
OOOOOAOC
00000Al2
00000A14
OOOOOAIA
OOOOOAIE
00000A22
00000A24
6600FFFF
08000008
661E
002C0004FFFF
6016
08AC0002FFFF
6700FFFF
08000008
6706
002C0004FFFF
00000A2A
00000A2C
00000A2E
00000A32
00000A34
00000A36
2610
E15B
163COOOO
E05B
4843
2643
OOOOOA38
00000A3E
00000A40
00000A42
00000A44
00000A48
00000A4A
227C00003A20
3293
548B
5489
04410002
6EF4
6034
NOLOOP
SETB4
**
PCKDONE
**
BNE
OWNSHIP
IF SO, LEAVE RINGS AS IS AND GIVE BACK OWNERSHIP
ADDI.W
MOVE.L
CMPA.L
BPL. S
ADDI. L
II$OI,TRINGCNT(A4)
LASTTRNG(A4) ,AO
TRNGBOT(A4) ,AO
RINGGEN
11$08 ,LASTTRNG(A4)
INCREMENT THE NUMBER A AVAILABLE XMIT RINGS
GET LAST XMIT RING ADDRESS
SEE IF WE ARE DOWN TO THE BOTTOM OF THE RINGS
IF WE ARE, GO GENERATE NEW LAST RING
OTHERWISE, GENERATE NEW LAST RING VALUE, AND PUT ON STACK
BRA
MOVE.L
BRA
CLEANUP
GO CLEAN UP RINGS
TRNGBASE(A4) ,LASTTRNG(A4) MAKE RING BASE THE NEW LAST RING ADDRESS
CLEANUP
GO CLEAN UP RINGS
"NON LOOPBACK" OPERATION
**********
PACKET DISCREPANCY CHECK
BTST
BEQ.S
BCLR.B
1109 ,DO
SETB4
1102 ,RINGSTAT(A4)
IS THE START OF PACKET BIT SET IN RMDI?
IF NOT, SEE IF IT WAS SET PREVIOUSLY
IF SO, SEE IF IT WAS SET PREVIOUSLY
BNE
BTST
BNE.S
ORI.B
BRA.S
BCLR. B
BEQ
BTST
BEQ.S
ORI.B
PACKERR
1108 ,DO
PCKDONE
11$04 ,RINGSTAT' A4)
PCKDONE
112, RINGSTAT(A4)
PACKERR
1108 ,DO
PCKDONE
11$04 ,RINGSTAT(A4)
IF IT WAS SET BEFORE YOU HAVE AN ERROR
IF NOT SET, CHECK IF END OF PACKET B IT IS SET
IF IT IS, WE HAVE THE WHOLE MESSAGE,CHECK DONE
IF NOT, THIS IS ONLY THE START OF PACKET
GO ON, PACKET CHECKS OUT
SEE IF START OF PACKET WAS SET PREVIOUSLY
IF IT WAS NOT SET BEFORE YOU HAVE AN ERROR
IF IT WAS SET, SEE IF END OF PACKET IS SET
IF ENP SET, WE HAVE WHOLE MESSAGE, CHECK DONE
IF NOT, THIS IS ONLY THE START OF MESSAGE
CONTINUE WITH NORMAL PROCESS
MOVE. L
ROLoW
MOVE.B
ROR.W
SWAP
MOVE.L
(AO),D3
1I08,D3
11$00,D3
11$08,D3
D3
D3,A3
MOVE RVCR BUFFER ADDRESS INTO REG D3
MOVE SECOND BYTE INTO POSITION TO BE CLEARED
CLEAR OUT THE STATUS
REPOSITION BYTES
REFORMAT FOR 68000 COMPATIBILITY
MOVE ADDRESS INTO AN ADDRESS REGISTER
MOVE RECEIVED MESSAGE FROM RECEIVE BUFFER INTO OUTPUT DEVICE
MOVE.L
SOMEMORE MOVE. W
ADD.L
ADD.L
SUBI.W
BGT.S
BRA.S
Ii0UTPUT ,AI
(A3) ,(AI)
11$2,A3
11$2 ,AI
1I02,DI
SOMEMORE
CLEANUP
MOVE OUTPUT ADDRESS INTO REG
MOVE MESSAGE WORD TO OUTPUT
INCREMENT THE MESSAGE BUFFER
INCREMENT THE MESSAGE OUTPUT
DECREMENT THE MESSAGE LENGTH
IF THERE ARE SOME MORE WORDS
FINISHED, GO CLEANUP RINGS
Al
ADDRESS
ADDRESS
REGISTER
TO XFER, DO IT
UNITED TECHNOLOGIES MOSTEK 68000 Assembler Vi.4
Site 99994 MOSTEK
LEXCEPT .A68
Line S Location Value
357
358
359
360
00000A4C 4EB9FFFFFFFF
361
00000A52 0800000D
362
00000A56 6712
363
00000A58 4EB9FFFFFFFF
364
00000A5E 0800000B
365
00000A62 6706
00000A64 4EB9FFFFFFFF
366
00000A6A 0800000C
367
368
00000A6E 6706
369
00000A70 4EB9FFFFFFFF
370
00000A76 0800000A
371
OOOOOA7 A 4EB9FFFFFFFF
Source
********
RECEIVE MESSAGE ERROR DETERMINATION
RECVERR
JSR
BTST
BEQ.S
JSR
CRCERR
BTST
OFLOERR
BUFF
BEQ.S
JSR
BTST
BEQ.S
JSR
BTST
JSR
STOP
II$OD,DO
OFLOERR
FRAMSUB
II$OB,DO
OFLOERR
CRCSUB
II$OC,DO
BUFF
OFLOSUB
II$OA,DO
BUFFSUB
*******
STOP AND FIND OUT WHAT THE ERROR IS
CHECK IF .. FRAME ERROR" BIT IS SET
IF NOT, CHECK IF OVER FLOW ERROR SET
IF SO, JUMP TO FRAM ERROR SU BROUTINE
CHECK IF "CRC ERROR" BIT IS SET
IF NOT, CHECK OVERFLOW ERROR
IF SO JUMP TO CRe ERROR SUBROUTINE
CHECK IF "OVER FLOW ERROR" BIT IS SET
IF NOT, CHECK BUFFER ERROR
IF SO JUMP TO OVER FLOW SUBROUTINE
CHECK IF "BUFFER ERROR" BIT IS SET
IF SO, JUMP TO BUFFER ERROR SUBROUTINE
372
...N
..,.
Co>
~
'"
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
00000A80
00000A84
00000A88
00000A8A
******
CLEANUP
CLEANUP
MOVE.L
CMPA.L
BPL. S
ADDI.L
226CFFFF
B3ECFFFF
6AOA
06AC00000008
FFFF
OOOOOAn 6006
00000A94 296CFFFFFFFF
00000A9A lABC0080
BRA. S
RINGLAST MOVE.L
OWNSHIP MOVE.B
00000A9E 082C0002FFFF
00000AA4 6600FE7E
BTST.B
BNE
******
LASTRRNG(A4) ,AI
RRNGBOT(A4) ,AI
RINGLAST
11$08,LASTRRNG(A4)
GO GET LAST RECEIVE RING ADDRESS
SEE IF WE ARE DOWN TO THE BOTTOM OF THE RINGS
IF WE ARE, GO GENERATE NEW LAST RING
GENERATE NEW LAST RING VALUE & PUT ON STACK
OWNSHIP
GO GIVE OWNERSHIP BACK TO LANCE
RRNGBASE(A4), LASTRRNG(A4) MAKE RING BASE THE NEW LAST RING ADDRESS
11$80,(AS)
GIVE OWNERSHIP BACK TO LANCE
1102,RINGSTAT(A4)
RVCRBUF
SEE IF START OF PACKET BIT IS SET
IF SO, THERE IS MORE THAT ONE BUFFER
END OF RVCR INTERRUPT ROUTINE •
*******************************************
LANCE INITIALIZATION DONE INTERRUPT
LEXCEPT. IDON
•
*******************************************
00000AA8 08020008
OOOOOAAC 6716
OOOOOAAE 4EB9FFFFFFFF
IDONCHK
00000AB4 082COOO4FFFF
OOOOOABA 67000008
OOOOOABE 08ECOO05FFFF
00000AC4 367 CFFFF
00000AC8 36BC0040
RESTORE
BTST
BEQ.S
JSR
11$08,D2
RESTORE
IDONSUB
CHECK FOR "INITIALIZATION DONE" BIT SET
IF NOT SET, RESTORE AND FINISH UP
IF IT IS, JUMP TO INITIALIZATION DONE SUBR.
BTST .B
BEQ
BSET .R
1104,RINGSTAT(A4)
RESTORE
115,RINGSTAT(A4)
SEE IF WE ARE IN LANCE DIAGONOSTICS
IF NOT CONTIUNE NORMALLY
IF SO. SET "TEST FINISHED" BIT
MOVE.W
MOVE.W
IiRDP ,A3
11$0040, (A3)
MOVE ADDRESS OF REGISTER OATA PORT TO A3
SET THE INTERRUPT ENABLE BIT IN CSRO
;
UNITED TECHNOLOGIES MOSTEK 68000 Assembler Vl.4
Site 99994 MOSTEK
LEXCEPT .A68
Line
407
408
409
Location
Value
OOOOOACC 4CDF7FFF
OOOOOADO 4E73
00000AD2 00000000
Source
MOVEM.L
RTE
(A7)+,Ao-A6/Do-D7
RETRIEVE OLD REGISTERS
RETURN FROM EXCEPTION HANDLING
END
no errors detected.
Options in effect:
NOA,BRL,NOCEX,CL ,FRL ,MC,MD,NOMEX,O ,NOpea ,NOpeS ,LIST ,NOSTR,FORMAT ,NOMOTOROLA
...N
Co)
GO
UNITED TECHNOLOGIES MOSTEK 68000 Assembler VI. 4
Site 99994 MOSTEK
LEXCEPT .A68
SYMBOL TABLE LISTING
...
~
Co)
CD
'1'
III
NAME
ATTR
BABLSUB
BADDGEN
BITTST
BUFF
BUFFSUB
BUFRSUB
CERR
CERRSUB
CLEANUP
COLLSUB
CRCBAD
CRCCK
CRCERR
CRCSUB
CSRO
CSRl
CSR2
CSR3
DECR
DLENGTH
ERROR
ERRORTST
FINISH
FRAMSUB
IDONCHK
IDONSUB
INCR
INCRE
LANINTR
LASTRRNG
LASTTRNG
LATECOLL
LCARERR
LCABRSUB
LMESSBAD
LOOPMCNT
LOOPTEST
LOOPXADD
LPACKERR
MERR
MERRSUB
MESSAGE
MISS
MISSSUB
MLENGTH
XREF
SECT
XREF
XREF
XREF
XDEF
XREF
XREF
*
XDEF
XREF
XREF
XREF
XREF
XREF
XREF
*
XREF
XREF
XDEF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XDEF
XREF
XREF
*
VALUE
00000000
0000096E
00000962
00000A76
00000000
00000000
00000836
00000000
00000A80
00000000
00000000
000009AO
OOOOOA5E
00000000
00000000
00000000
00000000
00000000
000009BA
00000000
0000082A
0000087E
00000902
00000000
00000M8
00000000
00000994
00000918
00000800
00000000
00000000
000008B2
000008AO
00000000
00000000
00000000
000008E8
00000000
00000000
0000084C
00000000
00003B20
00000842
00000000
00000000
'l'
'"
en
UNITED TECHNOLOGIES MOSTEK 68000 Assembler Vi. 4
Site 99994 MOSTEK
LEXCEPT .A68
SYMBOL TABLE LISTING
N
~
0
NAME
ATTR
MORE
MORECRC
MOREWDS
NEXTTRNG
NOBUFF
NOLOOP
OFLOERR
OFLOSUB
ONE
ONETEST
OUTPUT
OWNSHIP
PACKCHK
PACKERR
PCKDONE
RAP
RDP
RECVERR
RESTORE
RINGFIX
RINGGEN
RINGLAST
RINGSTAT
RLEN
RRNGBASE
RRNGBOT
RTRYSUB
RVCRBUF
RVCRINT
SETB4
SIZEERR
SOMEMORE
STOP
TESTTND!
TLEN
TRINGCNT
TRNGBASE
TRNGBOT
UFLOERR
UFLOSUB
XMITCK
XMITSERV
XRINGFIX
XREF
XREF
XREF
XREF
XDEF
XREF
XDEF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XDEF
SECT
VALUE
00000000
000009AC
00000986
00000000
000008D6
000009F6
00000A6A
00000000
00000000
00000874
00003A20
00000A9A
00000956
00000000
00000A2A
00000000
00000000
00000A4C
00000AC4
000009DO
000009EC
00000A94
00000000
00000000
00000000
00000000
00000000
00000924
000009lC
00000A14
00000000
OOOOOA3E
00000000
0000003C
00000000
00000000
00000000
00000000
000008C4
00000000
00000858
00000000
000009C6
8.3 APPENDIX C, MESSAGE INTERRUPT ASSEMBLY CODE
The following pages provide a listing of the message interrupt assembly code.
1-241
8-27
~
UNITED TECHNOLOGIES MOSTEK 68000 Assembler Vl.4
Site 99994 MOSTEK
MESSAGE .A68
Line
1
2
3
S Location
0
0
0
4 0
50
6 0
7 0
80
9 0
10 0
11 0
12
13
14
15
16
0
0
0
0
0
17 0
...
~
h)
18 0
19 0
200
21 0
22 0
23
24
25
26
0
0
0
0
27 0
280
29 0
30 0
31 0
32 0
Value
Source
*******************************************************+
*+*************************.**************.*****.*****+*
H
M
••
•• MODULE NAME: MESSAGE
••
•• AUTHOR: JIM FONTAINE
••
** PROGRAM: LANCE
••
•• LATEST REVISION DATE: JANUARY
••
••
••
••
••
********************************* •• **************.*****.
••
••
••
••
••
••
••
••
••
DESCRIPTION: THIS MODULE GENERATES A PSEUDO
••
MESSAGE THAT IS THEN PUT INTO THE TRANSMIT BUFFER • • •
THE MESSAGE CODE AND LENGTH IS DETERMINED BY THE
DLENGTH FOUND IN MEMORY LOCATION DLENGTH(A4)
THE BUFFER IS FILLED l/ITH CONSECUTIVE COUNTS,
NUMBERING FROM $0000 TO $(DLENGTH - 1). DLENGTH
MUST BE GREATER THAT 63 FOR NOHNAL DATA THANSMISSION AND LESS THAN 33 FOR LOOPBACK THANSMISSION.
••
••
••
••
••
••
••
*******.**********.********** •••• *•• ******************+*
***.*************************.*************************+
*******************************.****.************
•
•
•
•
EQUATE TABLE
*****.********.***.*************.*.******.*******
33 0
34 0
35 0
36 0
DESCRIPTOR RING STACK ALLOCATION
37 0
KEYWORD VALUE DEFINITION
38
39
40
41
42
43
0
0
0
0
0
0
44 0
45 0
46 0
47 0
48 0
490
50 0
51 0
••
••
••
20, 1958
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
XREF
RLEN
TLEN
TRNGBASE
TRNGBOT
LASTTRNG
NEXTTRNG
LOOPMCNT
TRINGCNT
RINGSTAT
LOOPXADD
MLENGTH
MESSAGE
•
UNITED TECHNOLOGIES MOSTEK 68000 Assembler Vl.4
Site 99994 MOSTEK
MESSAGE .A68
SYMBOL TABLE LISTING
NAME
...
N
~
Co)
~
BOTHBITS
DATINTR
DLENGTH
ENOBIT
ENOPAC
LASTTRNG
LOOPMCNT
LOOPXADD
MEMORY
MESSAGE
MLENGTH
MOREDATA
NEXTRNG
NEXTTRNG
NORINGS
NOUP
OUTPUT
RINGSTAT
RLEN
STABTPAC
STOP
TBUFLEN
TLEN
TMDFIX
TRINGCNT
TRNGBASE
TRNGBOT
UPDATE
XMITDONE
ATTR
XDEF
XREF
SECT
*
XREF
XREF
XREF
*
XREF
XREF
*
XREF
XREF
*
*
XREF
XREF
XREF
*
XREF
XREF
XREF
*
*
XREF
XREF
XREF
*
XDEF
*
VALUE
00000B74
OOOOOBOO
00000000
00000B6E
00000B66
00000000
00000000
00000000
00003FFO
00000000
00000000
00000B48
00000B12
00000000
00000000
00000B3C
00000000
00000000
00000000
00000B7A
00000000
00000000
00000000
00000B8C
00000000
00000000
00000000
00000B34
00000BB8
~
UNITED TECHNOLOGIES MOSTEK 68000 Assembler Vi. 4
Site 99994 MOSTEK
MESSAGE .A68
Line S Loeation
52 0
53 0
54 0
55 0
56 0
57 0
58 0
59 0
600
61 0
62 0
63 0
64 0
65 0
66 0
67 0
68 0
69 0
70
Value
Source
XREF
XREF
XREF
OUTPUT
DLENGTH
TBUFLEN
SUBROUTINE CALLS REFERENCE
OJOO3FFO
MEMORY
•••
XREF
XREF
STOP
NORINGS
XDEF
XDEF
XMITDONE
DATINTR
EQU
$3FFO
MAIN PROGRAM
OOOOOBOO
•••
ORG
$BOO
MOVEM.L
CLR.L
CLR.L
CLR.L
CLR.L
CLR.L
AO-A7/DO-D7,-(A7)
DO
D1
D2
D4
D5
MOVE.W
SUBI.W
BEQ
SUBI.W
MOVE.L
DLENGTH(A4) ,DO
1100, TRINGCNT(A4)
NORINGS
11$01, TRINGCNT(A4)
NEXTTRNG (A4 ) ,AO
CMPA.L
BNE.S
MOVE.L
BRA.S
TRNGBOT (A4 ) ,AO
SEE IF
IF NOT
UPDATE
TRNGBASE(A4) ,NEXTTRNG(A4) IF
BRANCH
NOUP
ADDI.L
11$08 ,NEXTTRNG(A4)
UPDATE THE ADDRESS OF THE NEXT XMIT RING
(AO) ,D3
II$OOFF ,D3
D3,D5
D3
D3,A3
II$Ol,m
D1,(A3)
11$01,D2
11$01,D4
D2,DO
GET XMIT BUFFER BASE ADD
CLEAR STATUS OUT OF REGISTER
STORE THE TMD1 WORD IN REG D5 FOR UPDATE
MOVE WORDS FOR 68000 COMPATIBILITY
MOVE XMIT BUFFER ADD. INTO AN ADD. REG
GENERATE NEXT MESSAGE BYTE TO OUTPUT
MOVE DATA BYTE INTO OUTPUT MEMORY LOCATION
INCREMENT BYTE COUNT 1 (TOTAL WORD COUNT)
INCREMENT BYTE COUNT 2 (BUFFER WORD COUNT)
SEE IF THERE ARE MORE DATA WORDS TO OUTPUT
71
.....
~
.,.,
.,.,
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
OOOOOBOO
00000B04
00000B06
00000B08
OOOOOBOA
OOOOOBOC
48E7FFFF
4280
4281
4282
4284
4285
OOOOOBOE
OOOOOB12
00000B18
OOOOOBIC
OOOOOB22
302CFFFF
046COOOOFFFF
6700FFFF
046COO01FFFF
206CFFFF
00000B26
00000B2A
00000B2C
00000B32
B1ECFFFF
6608
296CFFFFFFFF
6008
00000B34 06ACOOOOOO08
FFFF
OOOOOB3C 2610
00000B3E 024300FF
00000B42 3A03
00000B44 4843
00000B46 2643
00000B48 068100000001
00000B4E 1681
00000B50 06420001
00000B54 06440001
00000B58 B042
DATINTR
NEXTRNG
UPDATE
NOUP
MOVE.L
ANDI.W
MOVE.W
SWAP
MOVE.L
MOREDATA ADDI.L
MOVE.B
ADDI.W
ADDLW
CMP.W
SAVE OLD REGISTERS
CLEAR OUT REG
GET MESSAGE DATA SIZE
SEE IF THERE ARE TRANSMIT RINGS AVAILABLE
IF NONE LEFT, GIVE ERROR
IF THERE ARE SOME, DECREMENT THE COUNT
GET XMIT RING BASE ADDRESS
WE ARE ABOUT TO WRAP AROUND
UPDATE AS USUAL
SO, POINT TO TOP OF RING STACK
TO NO UPDATE
UNITED TECHNOLOGIES MOSTEK 68000 Assembler V1.4
Site 99994 MOSTEK
MESSAGE .A68
Line S Location Value
102
00000B5A 670A
00000B5C OC44FFFF
103
104
00000B60 6718
00000B62 528B
105
00000B64 60E2
106
107
108
109
110
00000B66 082C0002FFFF
00000B6C 6706
111
00000B6E 00450100
112
113
OOOOOB72 6018
00000B74 00450200
114
00000B78 60F4
115
00000B7 A 082C0002FFFF
116
00000B80 660A
117
00000B82 00450200
118
00000B86 08EC0002FFFF
119
120
121
....
~
122
123
124
125
126
127
128
129
130
131
132
133
134
135
00000B8C
00000B8E
00000B92
00000B96
00000B9A
00000B9C
00000B9E
OOOOOBAO
00000BA4
00000BA6
OOOOOBAA
5888
0A44FFFF
06440001
0044FOOO
3084
4284
5488
30BCOOOO
5988
00458000
3085
Source
BEQ.S
CMP.W
BEQ.S
ADDQ.L
BRA.S
*
CRECK IF START & END BITS ARE SET
ENDPAC
BTST.B
BEQ.S
ENDBIT
ORI.W
BRA.S
BOTHBITS ORI.W
BRA.S
STARTPAC BTST.B
BNE.S
ORI.W
BSET.B
*
IF
IF
IF
IF
GO
ADDQ.L
EORI.W
ADDI.W
ORI.W
MOVE.W
CLR.L
ADDQ.L
MOVE.W
SUBQ.L
ORI.W
MOVE.W
#02,RINGSTAT(A4)
BOTHBITS
#$0100,D5
TMDFIX
#$0200,D5
ENDBIT
#02,RINGSTAT(A4)
TMDFIX
#$0200,D5
#02 ,RINGSTAT(A4)
#04,AO
#$FFFF,D4
#$Ol,D4
#$FOoo,D4
D4,(AO)
D4
#$02,AO
#$0000, (AO)
#04,AO
#$80oo,D5
D5,(AO)
NOT, THIS IS THE END OF THE PACKET
SO, SEE IF THERE IS MORE BUF SPACE LEFT
NOT, GO CRECK IF THIS IS THE START OF PAC
SO, INCREMENT BUFFER ADD & GET NEXT WORD
GET ANOTHER WORD TO PUT INTO THR IIHFf'>:R
*
FIX UP THE TRANSMIT DESCRIPTOR RINGS
TMDFIX
*
ENDPAC
#TBUFLEN ,D4
STARTPAC
#$Ol,A3
MOREDATA
SEE IF START BIT HAD BEEN SET BEFORE
IF NOT, SET BOTH START & END OF PAC R ITS IN TH01
OTHERWISE SET ONLY THE END OF PACKET RIT
GO FINISH UP TRANSMIT DESCRIPTOR 1
SET END OF PACKET BIT IN TMD1
NOT GO SET END OF PACKET BIT
SEE IF START BIT HAD BEEN SET BEFORE
IF SO GO FINISH OF TMD1 STATUS
IF NOT SET START OF PACKET BIT IN TMD1
SET THE START STATUS BIT IN THE RINGSTATUS
*
GENERATE ADDRESS OF TMD2
TARE 2' S COMPLEMENT OF WORD COUNT
FORCE FOUR MSB TO ONES
MOVE MESSAGE BYTE COUNT INTO TMD2
CLEAR OUT MESSAGE COUNT FOR NEXT BUFFER
GENERATE ADDRESS OF TMD3
CLEAR OUT TMD3
GENERATE ADDRESS OF TMD1
SET OWN BIT, GIVING OWNERSHIP TO LANCE
PUT TMD1 BACK INTO XMIT RING
CRECK TO SEE IF WE NEED TO GENERATE ANOTHER MESSAGE BUFFER
136
137
138
139
140
141
142
143
144
OOOOOBAC B042
OOOOOBAE 6600FF62
00000BB2 08AC0002FFFF
00000BB8 4CDFFFFF
OOOOOBBC 4E73
OOOOOBBE 00000000
CMP.W
BNE
BCLR.B
XMITDONE MOVEM.L
RTE
END
D2,DO
NEXTRNG
#02 ,RINGSTAT(A4)
SEE IF THERE ARE MORE DATA WORDS TO OUTPUT
IF THERE ARE, SEE IF ANY BUFFER RINGS LEFT
CLEAR OUT THE START OF PACKET BIT ON RINGSTAT
(A7)+,Do-D7/AO-A7
RETRIVE OLD REGISTERS
RETURN FROM EXCEPTION PROCESSION
no errors detected.
Options in effect:
;
NOA,BRL ,NOCEX,CL ,FRL,MC ,MD,NOMEX ,0 ,NOpea ,NOpeS ,LIST ,NOSTR,FORMAT ,NOMOTOROLA
1·246
MI{68591/2(P,J,N)
-----~~-
SERIAL INTERFACE
ADAPTER (SIA)
COMMUNICATIONS PRODUCTS
FEATURES
o
Compatible with Ethernet and IEEE-802.3
Specifications
o
Crystal-controlled Manchester Encoder/Decoder
o
Manchester Decoder acquires clock and data
within six-bit times with an accuracy of ±3 ns.
CLSN
o
o
Guaranteed carrier and collision detection squelch
threshold limits
Carrier/collision detected for inputs more
negative than -275 mV
No carrier/collision for inputs more positive
than -175 mV
Input signal conditioning rejects transient noise
Transients <10 ns for collision detector
inputs
Transients < 20 ns for carrier detector
inputs
o
Receiver decodes Manchester data with up to ±20
ns clock jitter (at 10 MHz)
o
TTL-compatible host interface
o
Transmit oscillator accuracy ±0.01% (without
adjustments)
RX
Colllslon+
Collislon-
RENA
Receive+
RCLK
Reeelve-
TSEL
T ••t
GND,
Vee1
GND2
X,
.
VCC.
X.
RF
TX
GND3
TCLK
Transmit+
TENA
TrlHlsmit-
Figure 1. Pin Assignments
GENERAL DESCRIPTION
The MK68591/2 Serial Interface Adapter (SIA) is a
Manchester Encoder/Decoder compatible with Ethernet and IEEE-802.3 specifications. In an
EtherneUIEEE-802.3 application, the MK68591/2 interfaces the MK68590 Local Area Network Controller for
Ethernet (LANCElM) to the Ethernet transceiver cable,
acquires clock and data within 6 bit-times and decodes
Manchester data up to ± 20 ns phase jitter at 10 MHz.
SIA provides both guaranteed signal threshold limits
and transient noise suppression circuitry in both data
and collision paths to minimize false start conditions.
ETHERNET
CONTROLLER
Figure 2. 1\'plcal Ethernet Node
LANCE-is a trademark of Thomson Components ~ Mostek Corporation.
1-247
Receive Data ( R X ) . . - - - - f - - ; ; = = : - l
Receive Clock (RCLK)
I+-----l
t--~-Receive
+
~~+--Receive
-
Carrier Present (RENAl .....- - - - i
r;;:;;;--"'_--comsion +
...------1
Collision (CLSNI_----i
L~::..J'---collision -
Transmit Data (TXI _ _ _ _ _ _ _. r ; ; : : : ; ; ; : : : ; : ; - - , - - - - - - _ T r a n s m i t +
Transmit Enable ITENAI
Transmit -
Transmit Clock ITCLKI ....f - - - - - - - - - - 1
XTAL 2
Figure 3. MK68591/2 Block Diagram
PIN DESCRIPTION
CLSN
RX
TX
Collision (output). A TTL active high
output. Signals at the Collision ± terminals meeting threshold and pulse width
requirements will produce a logic high
at CLSN output. When no signal is
present at Collision ±, CLSN output will
be low.
Receive Data (output). A MOSmL
output, recovered data. When there is
no signal at Receive ± and TEST is
high, RX is high. RX is actuated with
RCLK and remains activated until end
of message. During reception, RX is
synchronous with RCLK and changes
after the rising edge of RCLK.
RENA
Receive Enable (output). A TTL active
high output. When there is no signal at
Receive ±, RENA is low. Signals at
Receive± meeting threshold and pulse
width requirements will produce a logic
high at RENA. When Receive ± becomes idle, RENA returns to the low
state synchronous with the rising edge
of RCLK.
RCLK
Receive Clock (output). A MOSmL
output recovered clock. When there is
no signal at Receive ± and TEST is
high, RCLK is low. RCLK is activated after the third negative data transition at
Receive ±, and remains active until end
of message. When TEST is low, RCLK is
enabled.
"O'ansmlt (Input). TTL compatible input.
When TENA is high, signals at TX meet·
ing setup and hold time to TLCK will be
encoded as normal Manchester at
Transmit + and Transmit -.
TX High: Transmit + is negative with
respect to Transmit - for first
half of data bit cell.
TX Low: Transmit + is positive with
respect to Transmit - for first
half of data bit cell.
TENA
"O'ansmit Enable (Input). TTL compatible input. Active high data encoder ena·
ble. Signals meeting setup and hold
time to TCLK allow encoding of Manchester data from TX to Transmit + and
Transmit -.
TCLK
"O'ansmlt Clock (output). MOSmL
output. TCLK provides symmetrical high
and low clock signals at data rate for
reference timing of data to be encoded.
It also provides clock signals for the
controller chip (MK68590 LANCE) and
an internal timing reference for receive
path voltage controlled oscillators.
"O'ansmlt +
"O'ansmlt -
"O'ansmit (outputs). A differential line
output. This line pair is intended to operate into terminated transmission lines.
For signals meeting setup and hold time
to TCLK at TEN A and TX. The Man·
chester clock and data are outputted at
Transmit +/Transmit -. When operating
into a 780 terminated transmission line,
signalling meets the required output
1-248
levels and skew for both Ethernet and
IEEE-802.3 drop cables.
Receive +
Receive -
Collision +
Collision -
Receiver (inputs). A differential input.
A pair of internally biased line receivers
consisting of a carrier detect receiver
with offset threshold and noise filtering
to detect the signal, and a data recovery receiver with no offset for Manchester data decoding.
trol for receive path loop damping.
Frequency of the receive Veo is internally limited to transmit frequency ±
12%. Nominal receive Veo gain is 0.25
reference Veo gain MHzN.
TEST
Collision (inputs). A differential input.
An internally biased line receiver input
with offset threshold and noise filtering.
Signals at Collision ± have no effect on
data path functions.
Test Control (input). A static input that
is connected to Vee for normal
MK68591/2 operation and to ground for
testing of receive path function. When
TEST is grounded, RCLK and RX are
enabled so that receive path loop may
be functionally tested.
High Current Ground
Logic Ground
TSEL
Transmit Mode Select. An open collector output and sense amplifier input.
TSEL Low: Idle transmit state Trans·
mit + is positive with
respect to Transmit -.
TSEL High: Idle transmit state Transmit + and Transmit - are
equal, providing "zero"
differential to operate
transformer
coupled
loads.
When connected with an RC network,
TSEL is held low during transmission.
At the end of transmission, the open collector output is disabled, allowing TSEL
to rise and provide a smooth transmission from logic high to "zero" differential idle. Delay and output return to zero
are externally controlled by the RC time
constant at TSEL. (See Figure 9.)
Biased Crystal Oscillator. X1 is the input and X2 is the bypass port. When
connected for crystal operation, the system clock which appears at TCLK is half
the frequency of the crystal oscillator. X1
may be driven from an external source
of two times the data rate. In which case
X2 should be left floating.
RF
PF
Frequency Setting Voltage Controlled
Oscillator (Vco) Loop Filter. This loop
filter output is a reference voltage for the
receive path phase detector. It also is a
reference for timing noise immunity
circuits in the collision and receive enable path. Nominal reference Veo gain
is 1.25 TCLK frequency MHzIV.
Voltage Controlled Oscillator Ground
V CC1
High Current and Logic Supply
V CC2
Voltage Controlled Oscillator Supply
FUNCTIONAL DESCRIPTION
The MK68591/2 Serial Interface Adapter (SIA) has three
basic functions. It is a Manchester Encoder/line driver
in the transmit path, a Manchester Decoder with noise
filtering and quick lock·on characteristics in the receive
path, and a signal detect/converter (10 MHz differential to TTL) in the collision path. In addition, the SIA provides the interface between the TTL logic environment
of the LANCE and the differential signaling environment
in the transceiver cable.
TRANSMIT PATH
The transmit section encodes separate clock and NRZ'
data input signals meeting the set up and hold time to
TCLK at TENA and TX, into a standard Manchester II
serial bit stream. The transmit outputs (Transmit
+/ Transmit -) are designed to operate into terminated transmission lines. When operating into a 780 terminated transmission line, signaling meets the required
output levels and skew for both Ethernet and
IEEE-802.3.
Transmitter Timing and Operation
A 20 MHz fundamental mode crystal oscillator provides
the basic timing reference in the SIA. It is divided by
two to create the transmit clock reference (TCLI<). Both
20 MHz and 10 MHz clocks are fed into the Manchester
Encoder to generate the transitions in the encoded data
stream. The 10 MHz clock, TCLK, is used by the SIA
to internally synchronize transmit data (TX) and transmit
Receive Path Vco Phase Lock Loop
Filter. This loop filter input is the con1-249
the receiver. This helps assure a valid response to
"real" data.
TX _ _ _.-jll MANCHESTER
TENA
1
ENCODER
TCLK
(10 MHz)
-------1+1
20 MHzEJ
111---=T=RA:-lN'!:.SMIT ±
11------..
The receiver section, shown in Figure 6, consists of two
data paths. The receive data path is designed to be a
zero threshold, high bandwidth receiver. The carrier
detection receiver has an additional bias generator. Only
data amplitudes larger than the bias level are interpreted as valid data. The noise rejection filter prevents noise
transients of less than 20 ns from enabling the data
receiver output. The collision detector similarly rejects
noise transients of less than 10 ns.
i
asc
-,-
Figure 4. li'ansmlt Section
Receiver Section Timing
Receive Enable (RENA) is the "carrier present" indication established when a signal of sufficient amplitude
(VIDe) and duration (t RPWR) is present at the receive
inputs. Receive Clock (RCLK) and Receive Data (RX)
become available after the third negative data transition
enable (TENA). TCLK is also used as a stable bit-rate
clock by the receive section of the SIA and by other
devices in the system (the MK68590 LANCE uses TCLK
to drive its internal state machine). The oscillator may
use an external 0.005% crystal or an external TIL level
input as a reference. Transmit accuracy of 0.01% is
achieved (no external adjustments are required).
TENA is activated when the first bit of data is made
available on TX. As long as TENA remains high, signals at TX will be encoded as Manchester and will appear at Transmit + and Transmit -. When TENA goes
low, the differential transmit outputs go to one of the
two idle states defined below:
RX
RCLK
• TSEL High: The idle state of Transmit +1 Transmit yields "zero" differential to operate transformer
coupled loads (see Figure 14a).
RENA
• TSEL Low: In this idle state, Transmit + is positive
to Transmit - yielding logical high (see Figure 14b).
Figure 5. Receiver
at Receive +1 Receive - inputs, and stay active until
the end of a packet. During reception, RX is synchronous with RCLK, changing after the rising edge of
RCLK.
RECEIVE PATH
The principle function of the receiver is the separation
of the Manchester encoded data stream into clock and
NRZ data.
Input Signal Conditioning
Before the data and clock can be separated, it must be
determined whether there is "real" data or unwanted
noise at the transceiver interface. The MK68591/2 SIA
carrier detection receiver provides a static noise margin of -175 to -275 mV for received carrier detection.
These DC thresholds assure that no signal more positive than -175 mV is ever decoded and that signals
more negative than -275 mV are always decoded.
Transient noise of less than 10ns duration in the collision path and 20 ns duration in the data path are also
rejected.
This signal conditioning prevents unwanted idle noise
on the transceiver cable from causing "false starts" in
The receiver detects the end of a packet when the normal transition on the differential inputs cease. After the
last low-to-high transition, RENA goes low and RCLK
completes one last cycle, storing the last data bit. It then
becomes and remains low (see Receive End of Packet
Timing diagrams). When TEST is low, RCLK continues
to run, tracking data (if available) or synchronizes with
TCLK.
Receive Clock Control
To insure quick capture of incoming data, the receiver
phase-locked-loop is frequency Ipcked to the transmit
oscillator and it phase locks to incoming data edges.
Clock and data are available within 6 bit times (accurate
to within ±3 ns). The SIA will decode jittered data of
up to ±20 ns (see Figure 7).
1-250
+
RX
40MHz
PHASE
DETECTOR
VCO
RCLK
RENA
NOISE
REJECT
FIl.TER
+
Figure 6. Receiver Section Detail
Differential 1/0 Terminations
The differential input for the Manchester data (receive
±) is externally terminated by two 40.2 O±1% resistors
and one optional common mode bypass capacitor. The
differential input impedance ZIDF and the common
mode input ZICM are specified so that the Ethernet specification for cable termination impedance is met USing standard 1% resistor terminators. The Collision ±
differential input is terminated in exactly the same way
as the receive input (see Figure 8).
a bipolar device, serial input and output circuits are
designed to meet the IEEE 802.3 specifications and
cannot be protected against ESD without affecting the
performance of the device.
Collision Detection
The Ethernet Transceiver detects collisions on the
Ethernet and generates a 10MHz signal on the transceiver cable (Collision +1 Collision -). This collision signal passes through an input stage which assures signal
levels and pulse duration. When the signal is detected
by the SIA, the SIA sets the CLSN line high. This condition continues for approximately 190ns after the last
low-to-high transition on Collision +1 Collision -.
±5ns
ALLOWABLE
SAMPLING ERROR
~---50ns----II~
APPLICATION RECOMMENDATIONS
The differential input and output pins should be transformer coupled to meet the IEEE 802.316 volt fault tolerance specifications.
This device is not recommended for operation in wire
wrapped boards.
This device should be handled with care to avoid
electro-static-discharge (ESD) failures. Although this is
1-251
Figure 7. Maximum Jitter Impact On Sampling
40.2Q 1%
RECEIVE + 22
R,
3KO
RECEIVE - 21
C,
680 pF
fEST
V CC1
V CC2
20 MHz
PARALLEL
MOOE
CRYSTAL
50 pF
0.005% ACCURATE
PF
RF
TX
16
GND3 15
TCLK
TRANSMIT + 14
TEN A
TRANSMIT - 13
NOTES:
1. Connect Rl, R2, C1 for 0 differential nontransmit. Connect to ground for
logic 1 differential nontransmit. (See Figure 9.)
2. Pin 20 shown for normal device operation.
3. Nodes A and B may be connected directly to ground for proper decoder
operations, or to the common mode bypass C4 and Cs. Some direct coupled transceivers require C4 and Cs to ground for proper operation.
Figure 8. MK68591/2 External Component Diagram
C,
680 pF
R2
TSEL
(PIN 5)
3KO
TSEL
(PIN 5)
TSEL LOW
TSEL HIGH
Figure 9. Transmit Mode Select (TSEL) Connection
1-252
ABSOWTE MAXIMUM RATINGS·
Storage Temperature ............................................................ -65 to +150°C
Temperature (Ambient) Under Bias ...................................................... 0 to 70°C
Supply Voltage to Ground Potential Continuous ............................................... +7.0V
DC Voltage Applied to Outputs for High Output State ............................... -0.5 to +VCC max
DC Input Voltage (Logic Inputs) ........................................................... +5.5V
DC Input Voltage (Receive/Collision) ................................................... -6 to +6 V
Transmit ± Output Current ........................................................ -50 to +5 mA
DC Output Current, Into Outputs ......................................................... 100 mA
DC Input Current (Logic Inputs) ......................................................... ±30 mA
·Stresses above those listed under ''Absolute Maximum Ratings" may causa permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE The following conditions apply unless otherwise
specified:
TA =
0 to 70°C, Vcc = 5.0 V±10 percent, MIN = 4.5 V, MAX = 5.5 V, period of crystal oscillator {Tose> = 50 ns
Parameters Description
Test Conditions
VOH
Output High Voltage RX, RENA,
CLSN, TCLK,RCLK
VOL
Output Low Voltage f'leLK, TCLK, RENA,
RX,CLSN,TSEL
VOD
Differential Output Voltage
(Transmit +) - (Transmit -)
10H ~ -1.0 mA
I
I
Min
2.4
l'yp
10L ~ 16 mA,
0.5
IOL~1mA
0.25
0.4
670
-670
770
-770
~
7811
550
Units
V
3.4
0.36
V
Vo
RL
Vo
Figure 19
-550
-20
0.5
20
mV
-0.5
±0.1
0.5
mA
0
2.5
5
V
5
20
mV
+50
pA
VOD OFF
Transmit Differential Output Idle Voltage
100 OFF
Transmit Differential Output Idle Current
RL ~78 II Figure 19
TSEL ~ HIGH
VCMT
Common Mode Output Transmit Voltage
Figure 19
VODI
Differential Output Voltage Imbalance
(Transmit ±) I I Vo I - I
II
RL
VIH
Input High Voltage TTL
IIH
Input High Current TTL
V IL
Input Low Voltage TTL
IlL
V IRD
Input Low Current TTL
VCC ~ Max, VIN ~ 0.4 V
Differential Input Threshold (Rec Data)
Figure 20
-25
VIDC
Differential Input Threshold (Carrier/Collision ±)
Figure 20
-175
Power Supply Current
tosc ~ 50 ns
125
ICC
Max
Va
~
7811
2.0
mV
V
VCC ~ Max, VIN ~ 2.7 V
0.8
V
-400
pA
0
+25
mV
-225
-275
mV
180
mA
-270
tosc ~ 50 ns, TA ~ Max
160
V IB
Input Breakdown Voltage VI ~ +5.5 (TX, TENA, 'fES'f)
II
VIC
Input Clamp Voltage
liN ~ -18 mA
ISCO
RX,TCLK,CLSN, RENA, RCLK
Short Circuit Current
-40
-80
-150
mA
RIDF
Differential Input Resistance
VCC ~ Oto Max
6k
8.4k
13k
ohm
ohm
~
1 mA
5.5
V
-1.2
V
RICM
Common Mode Input Resistance
VCC ~ Oto Max
1.5k
2.1k
7.5k
VICM
Receive and Collision Input Bias Voltage
liN ~ 0
1.5
3.5
4.2
V
IILD
Receive and Collision Input Low Curent
VIN ~ -1 V
-0.6
-1.06
-1.64
mA
IIHD
Receive and Collision Input High Current
VIN ~ 6 V
+0.4
+0.6
+1.10
mA
11HZ
Receive and Collision Input High Current
VCC ~ 0, VIN ~ +6 V
0.4
1.28
1.86
mA
1-253
SWITCHING CHARACTERISTICS OVER OPERATING RANGE The following conditions apply unless otherwise specified:
TA =
#
0 to 7Q°C, V cc = 5.0 V±10 percent, MIN = 4.5 V, MAX = 5.5 V, T osc = 50 ns
Signal
Parameters Description
Test Conditions
Min
l\'p
Max
Units
118
ns
RECEIVER SPECIFICATION
1
RCLK
tRCT
RCLK Cycle Time
85
100
2
RCLK
tRCH
RCLK High Time
38
50
3
RCLK
tRCL
RCLK Low Time
38
50
4
RCLK
tRCR
RCLK Rise Time
2.5
8
ns
5
RCLK
tRCF
RCLK Fall Time
2.5
8
ns
2.5
8
ns
2.5
8
ns
8
25
ns
Figures 10, 16a. and 20
50
80
ns
Figures 11 and 20
265
300
ns
6
RX
tRDR
RX Rise Time
7
RX
tRDF
RX Fall Time
8
RX
tRDH
RX Hold Time (RCLK to RX Change)
9
RX
tRDS
RX Prop Delay (RCLK to RX Stable)
10
RENA
tDPH
RENA Turn·On Delay (VIDC Max on
Receive ± to RENAH)
11
RENA
tDPO
RENA Turn·Off Delay (V IDC Min on
Receive ± to RENAL)
CL = 50 pF
Figure 17a
(See note)
5
12
RENA
tDPL
RENA Low Time
13
Rec
±
tRPWR
Receive ± Input Pulse Width to
Reject (InputVIDC Max)
Figures 16a and 20
15
RCLK
tRLT
Decoder Acquisition Time
Figure 11
120
ns
8
ns
ns
200
30
45
ns
20
ns
ns
30
Figure 10
390
450
ns
Figures 16b and 20
18
10
ns
COLLISION SPECIFICATION
16
Coli
±O
tCPWR
Collision Input Pulse Width to Reject
(InputVIDC Min)
20
CLSN
tCPH
CLSN Turn-On Delay (VIDC Max on
Collision ± to CLSNH)
21
CLSN
tcpo
CLSN Turn-Off Delay (V IDC Min on
Collision ± to CLSN L)
26
18
ns
80
117
ns
117
160
ns
33
50
ns
133
160
ns
45
50
55
ns
45
50
55
ns
2.5
8
ns
2.5
8
ns
Figures t5, 16b, and 20
TRANSMITTER SPECIFICATION
22
TCLK
tTCL
TCLK Low Time
23
TCLK
tTCH
TCLI{ High Time
24
TCLK
tTCR
TCLK Rise Time
TCLK Fall Time
tosc = 50 ns
Figures 17b and 18
25
TCLK
tTCF
26
TX, TENA
27
TX,
TENA
tTOS' tTES TX and TENA Setup Time to TCLK
tTDH' tTEH TX and TENA Hold Time to TCLK
28
TX
±
tTOCE
Transmit
to Edge)
29
TCLK
tOD
TCLK High to Transmit
30
±
TX ±
TX±
,tTOR
Transmit
tTOF
Transmit
31
32
TX
VOD
± Output,
Figures 13, 14a, 14b, and
17b
1.1
ns
5
-1.1
ns
49.5
50
50.5
ns
80
100
ns
2
4
ns
2
4
ns
-100
mV
(Bit Cell Center
Figures 14a, 14b, and 19
± Output
± Output
5
± Output
Rise Time
20 through 80 percent
Figure 19
Fall Time
Undershoot Voltage at Zero Differential Point on Transmit Return to
Zero (End of Message)
NOTE:
Assumes equal capacitance loading on RCLK and AX.
1-254
Figure 14a
-/100 ns
I I
l0
I
RECEIVE ±
(MEASURED
DIFFERENTIALLY)
RENA
RCLK
RX
• PULSE WIDTH OF '" 45 ns IS ALWAYS RECOGNIZED.
HOWEVER, PULSE WIDTH OF " 20 ns IS REJECTED.
Figure 10. Receiver Timing -
I
0
Start of Packet
I
RECEIVE ±
(MEASURED
DIFFERENTIALLY)
RENA
RCLK
RX
Figure 11. Receiver Timing - End of Packet (Last Bit = 0)
1-255
RECEIVE ±
(MEASURED
DIFFERENTIALLY)
RENA
RCLK
RX
Figure 12. Receiver Timing -
End of Packet (Last Bit = 1)
~:~::::lf~u_2_9_\=~~-+-·---JI-EBI,......J2'OV.-_\:~~_I_,--_\...
..J p:
TSEL LOW
TRANSMIT ±
(MEASURED
DIFFERENTIALLY)
27
TSEL HIGH
----....:.:=="'---------I
-670mV -
-
-
-
-
+,"--"'_-'
I
: '--_ _-+-_ _...J
I
I
I
I
10
I
I
I
I
I
BIT CELL
BOUNDARY
I
I
I
Figure 13. li'IInsmitter Timing - Start of li'IInsmission (TSEL Low, TSEL High)
1-256
BIT CELL
CENTER
TCLK
lENA
TRANSMIT ±
(MEASURED
DIFFERENTIALLY)
TSEL (HIGH)
~
------------------/
CASE 2
(LAST BIT "" 1)
--~~----.
TRANSMIT ±
(MEASURED
DIFFERENTIALLY)
Figure 14a. lhmsmitter Timing -
End of lhmsmlssion (TSEL High)
TCLK
rENA
(LA~:~ 1= 0)
TX
N:.tA__~__+--+_.D.~IOIlIllli!lll/IOIlIllliIk1lIlll!IIlIi~
TRANSMIT ±
(MEASURED
DIFFERENTIALLY)
TSEL(~W) -
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~• •
CASE 2
(LAST BIT = 1)
•
TRANSMIT ±
(MEASURED
DIFFERENTIALLy)
Figure 14b. Transmitter Timing -
End of llansmlssion (TSEL Low)
1-257
COLLISION
PRESENCE±
CLSN
_ _ _ _....
1:-::":::':'---------------21~
.8V
'" PULSE WIDTH OF -26 ns IS GUARANTEED TO BE
RECOGNIZED: HOWEVER, PULSE WIDTH OF :$ 10ns IS
REJECTED
Figure 15. Collision Timing
RECEIVE ±
(MEASURED
DIFFERENTIALLY)
COLLISION ±
(MEASURED
DIFFERENTIALLY)
RENA
CLSN
Figure 16a. Receive
± Input
Pulse Width Timing
RCLK
AX
_ ____
Figure 16b. Collision
---J~
/I
2.0V
± Input Pulse Width
TCLK
~
::j [::.
XJ8V
~
TX, TENA
Figure 17b. TCLK and TX Timing
Figure 17a. RCLK and RX Timing
1-258
Timing
TRANSMIT +
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
1: 50 pF
RL = 780
TRANSMIT-
Figure 19. 1nmsmit ± Output Test Circuit
Figure 18. Test Load For RX, RENA, and TCLK
fly
= 80.401%
+
DEVICE
UNDER
TEST
RT
-
Figure 20. Receive
+
± and Collision ± Input Test Circuit
1-259
MK68591 (600 mil)
24
~ I-l-.060~.D15
12
I
'I~
1.200!.0'0
·09'+.015
~
jmw~I __
----r-I
__ ! .
.120
MIN.
~
.020MIN •
~ ~
I
I
I
Tl---""-m"-~ I
olOi 002
j - - '''----i
l' EQUAlSPACES@.100
Ceramic Dual-In-Line Package (P)
24 Pin
MK68592 (300 mil)
00
='
1.085 MAX.
!.L.o25 MIN.
~
~~ :~~.j
f---.j
,.", MA>.
A
.240 MIN.
I
1--,-
! I
I-~
~~.
mN~
:~~o~;:I};-" ;::=~~ ,,,---1
L 1-1- -{IJ-I_~:::~~;-!
~
.015 MIN.
I
I
I
1115 MIN
I
.'''MA>.
1.160MAX.
" EQUA' .,ACES ••
.015 MAX.
0 -"
DIM
NOTES
1. OVERALL LENGTH INCLUDES .010 IN .
FLASH ON EITHER END OF THE PACKAGE.
.DDBMIN.
2
PACKAGE STANDOFF TO BE MEASURED
PER JEDEC REQUIREMENTS.
3. THE MAXIMUM LIMIT SHALL 8E
INCREASED BY .003 IN. WHEN
SOLDER LEAD FINISH IS SPECIFIED.
A
AI
A2
8
81
C
0
01
E
El
"
"
L
Cerdip Hermetic Package (J)
24 Pin
Plastic Package (N)
24 Pin
1-260
INCHES
NOTES
MIN
MAX
.210
2
.015
2
.120 .140
.015 ,021
3
.050 .070
3
.OOB ,012
1
1.220 1.250
.060 .075
.325
.300
.240 .270
.090 .110
.300 .400
120
-
MI{5030P,I{
StarLAN HUB CHIP
COMMUNICATIONS PRODUCTS
,
FEATURES
GND
Xl
X2
0 Complete Hub Logic device which conforms to
StarLAN specification.
OCLK
LEDO
LEDl
0 Supports Multi-point extension (MPE).
LED2
LED3
LEDEN
0 Auto compensation for wiring reversal.
o
12 port HUB.
CO
DO
Cl
0 Optional retime circuit.
0 Cascadable. Two levels may be cascaded and still
Dl
C2
D2
appear to the network as one yielding up to a 121
port HUB.
C3
D3
C4
D4
0 Supports up to a 10 layer network.
0 Auto preamble generation to eliminate bit loss.
C5
D5
C6
D6
VCC
0 Selectable active carrier polarity sense.
0 Jabber function isolates network failures.
0 Optional minimum frame length enforcement.
48
47
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
46
45
44
43
42
41
40
39
VCC
MODED
MODEl
MODE2
MODE3
MODE4
MODE5
MODE6
37
RESET
DXD
DXEN
UXD
36
35
34
UXEN
Dll
Cl1
33
32
31
Dl0
Cl0
D9
30
29
28
27
C9
D8
26
25
C7
GND
38
C8
D7
Figure 1. MK5030 Pin Assignment
0 Collision detection:
•
•
•
•
•
0 UPLINK and DOWNLINK collision status outputs.
multiple inputs
missing mid-bit transition
transitions too close together
transitions too far apart
AT&T release 1 collision presence signal.
0 Per port jabber status output.
0 On chip crystal oscillator circuitry.
0 Digital phase lock loop.
0 35 mW typical power disSipation.
0 6X clock yields 162 nS jitter tolerance.
0 CMOS technology.
0 Transmit Data Trailer enforcement.
0 48 pin DIP.
0 Input protection at end of frame (20 /Ls).
0 Pin selectable high-end HUB versus intermediate
HUB.
0 Optional internal pulse stretcher for carrier sense
o
Single 5-volt supply.
o
All inputs and outputs TTL compatible"
o
Industrial version available.
squelch.
GENERAL DESCRIPTION
0 UPLINK and DOWNLINK active status outputs.
The MK5030-HUB is a 48 pin CMOS VLSI device that
simplifies the design and implementation of a StarLAN
compatible HUB. This chip provides all the digital logic
necessary in a HUB.
*NOTE: Crystal inputs have CMOS thresholds.
1-261
PIN DESCRIPTION:
X1, X2
Inputs. Either connect a 6.00 ±.005%
MHz crystal between the pins, or leave
X2 not connected and apply a 6.0 MHz
±.01% square wave to X1. (Refer to
Figure 7.)
OClK
Output. Provides a TIL elK output from
the above crystal oscillator. This is useful when cascading devices.
CO-C11
Schmitt inputs. Carrier sense inputs. Active state is selectable. Refer to MODE4
below.
DO-D11
Inputs. Received data streams.
squelch function. Refer to Figure 2. If
MODE2 = 1, then the input carriers are
threshold set off the incoming data
stream and an internal pulse stretcher
must be used. With MODE2 = 1, users
do not need to use one-shots externally
for each port.
MODE3
Input. If MODE3 = 1, then the retimer
circuit is enabled as specified by IEEE
802.3. If MODE3 = 0, then the retimer
circuit is disabled. This allows HUBs in
close physical proximity to be cascaded
together and appear to the network as
one HUB. Refer to Figure 3.
MODE4
Input. Selects carrier active state. If
MODE4 = 0, then the carrier inputs
(CO-C11) are active low. If MODE4 = 1
then the carrier inputs (CO-C11) are active high.
MODE5
Input. If MODE5 = 1, then auto preamble generation is enabled. The chip will
initiate preamble transmission once
phase lock is obtained. Once the transmit FIFO is sufficiently full, transmit data
is obtaineq from the FIFO. This
decreases the amount of bits a HUB implementation will lose. Depending on the
implementation, bits may actually be
gained. If MODE5 = 0, then automatic
preamble generation is disabled.
MODE6
Input. If MODE 6 = 1, then minimum
frame length of 96 bits is enforced. If
MODE6 = 0, then no minimum frame
length is enforced.
Output. UPLINK data stream to the next
UPPER HUB, if any, in the network hierarchy.
Output. UPLINK transmit enable indicating that UXD contains valid data.
Output. Downlink data stream to all
ports. If MODE1 = 1, then this data
stream is derived from Port 11. If MODE1
= 0 then this data stream is identical to
UXD.
Output. Downlink transmit enable to all
ports. If MODE1 = 1, then this data
stream is derived from Port 11. If MODE1
= 0, then this data stream is identical to
UXEN.
MODEO
Input. Testmode. Should be tied high for
normal operation. Testmode is useful
only for semiconductor device production test.
MODE1
Input. If MODE1 = 1, then the chip is an
intermediate hub; and CO-10/DO-10 inputs will be used as UPLINK inputs and
C11/D11 as the DOWNLINK input. If
MODE1 = 0, then the chip is a high-end
hub; CO-11/DO-11 inputs will be used as
UPLINK inputs and DOWNLINK outputs
(DXD, DXEN) will internally be connected to the UPLINK outputs (UXD,
UXEN). See Figure 5.
MODE2
Inputs. If MODE2 = 0, then the input
carriers have been externally stretched
and no internal stretcher is desired. This
stretcher is required as part of the
1-262
Schmitt input. Active low. A low causes
the device to reset. Input must be high
for normal operation.
Input/output open drain. If lEDEN is externally connected to GND, then the lED
(0-3) provide static status information.
Otherwise, lEDEN should be pulled
high through a 2K ohm pull up resistor
and lED (0-3) will provide an ID of an
internal status monitoring point and wilt
pull lEDEN low if that monitoring point
is active. This allows connection of a single external multiplexer to drive indicating devices. Refer to Figure 4.
LEDO-LED3
Output. If LEDEN is connected to GND:
LEDO
LED1
LED2
LED3
UPLINK transmit enabled
UPLINK collision sense
DOWNLINK transmit
enabled
DOWNLINK collision sense.
If LEDEN is not connected to GND, then
LEDEN = 0 indicates that the LED (0-3)
specified function is active:
LED3
LED2
LED1
LEDO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
DESCRIPTION
PORTO
jabber
PORT 1
jabber
PORT 2
jabber
PORT 3
jabber
PORT 4
jabber
PORT 5
jabber
jabber
PORT 6
PORT 7
jabber
PORT 8
jabber
PORr 9
jabber
PORT 10
jabber
PORT 11
jabber
UPLINK
UPLINK collision
DOWNLINK
DOWNLINK collision
NOTE: 1. UPLINK and DOWNLINK status outputs are normally on and will
blink off for 147mS when a frame Is transmitted. LED on-time of
147rnS is guaranteed between each off blil"!k.
2. UPLINK and DOWLINK collision outputs are normally off and will
blink on for 147 ms when a collision Is detected. LED off time of 147
ma is guaranteed between each on blink.
vee
Power supply pin. +5 VDe ±5%
GND
Grou~.OVDC
1-263
LEDEN
=0
active
active
active
active
active
active
active
active
active
active
active
active
inactive
yes
inactive
yes
LEDEN
=1
inactive
inactive
inactive
inactive
inactive
inactive
inactive
inactive
inactive
inactive
inactive
inactive
active
no
active
no
~-----------------~Dn
MK5030
Vr
J"Lo------ICn
--------i
P.W.=2~S
'0' - - - - / MODE4
'0'
MODE2
EXTERNAL SQUELCH
>------fDn
MK5030
>------ICn
'0'----1 MODE4
'1'
INTERNAL SQUELCH
Figure 2. Internal Versus External Time Squelch
1·264
MODE2
RETIME MODE.
9 BIT ELASTIC
FIFO ENABLED.
}
MK5030
'0'
MODE1
"1"
MODE3
DXD
OXEN
011
C11
HEADER
HUB
CN
ON
UXD
UXEN
MK5030
RETIME MODE.
9 BIT ELASTIC
FIFO ENABLED
'1'
MODE1
'1'
MODE3
INTERMEDIATE
HUB
LEVEL
NO RETIME,
GATE DELAYS
ONLY.
_ _...L..._ _....
~
MK5030
MK5030
'1'
MODE1
'1'
MODE1
'0'
MODE3
'0'
MODE3
}~'
TO DTE'S OR LOWER LEVEL HUBS
NOTE: Sublevels A and B may either be on same circuit board or on separate
boards located in close proximity.
Figure 3. Example Showing Retime and No-Retime Modes
1-265
STATIC DISPLAY
W/O JABBER DISPLAY
0
LEDO
A
LED1
B
1
LEoEN
15
G1
2KO
v
~A
2200
-'VV\r
•
0
I
f""IIII
•
C
LED3
I~
•
•
74154
LED2
~
f""IIII
SCAN DISPLAY
WIJABBER DISPLAY
~
........
Vee
Figure 4. Status Display Modes
Overview of Circuit Description
and "jabbed" inputs.
The MK5030 HUB chip consists of three sub-modules:
the uplink, the downlink, and the status display module.
The Uplink Module
The uplink module multiplexes twelve inputs from stations and/or "lower" HUBS (see Fig. 3) and retimes,
if enabled, the multiplexed data to remove jitter. The uplink also handles several optional features including
retiming, disabled auto-preamble generation, and collision detectionltransmission. Refer to Figure 5, MK5030
HUB Block Diagram.
The uplink module has a carrier processor which performs the following:
The downlink module is used only in the intermediate
mode, and is nearly identical to the uplink (see Fig. 5).
The status display modules provide either static or
scanned display of the line activity, detected cOllisions,
6
1·266
• Detects carrier and outputs a carrier presence signal.
• Detects collision and outputs a collision presence
signal.
• Will ignore one, or more, inputs by the jabber or protection time functions.
• Provides time domain filtering to improve noise tolerance on carrier inputs.
• When in the retime mode:
-
Automatically compensates for wiring reversal.
-
Recovers clock using a DPLL (for internal HUB
chip use only).
-
Passes data through a serial 9 bit FIFO buffer.
-
When in minimum frame length mode, the frame
length is guaranteed to be greater than 96 bits.
-
Will perform Automatic Preamble Generation
(APG) if the optional APG is selected.
-
Detects end-of-frame using the DPLL.
Automatic Preamble Generator
If APG is enabled, preamble generation at the outputs
DXD and UXD is started as soon as the DPLL acquires lock. When the FIFO reaches the 4 bit watermark, the output data are taken from the FIFO. The APG
keeps the preamble from "shrinking" as a frame is
passed from HUB to HUB. Without APG, a HUB chip
will lose an average of 2 preamble bits, but with APG,
an average of 2 preamble bits are gained. This two bit
gain should be taken into account by system designers.
Automatic Compensation For Wiring Reversal
When installing twisted pair telephone wiring, it is often
difficult and expensive to maintain proper polarity on
the wire pairs. The MK5030 will automatically compensate for this reversal on a per port basis. Any frame that
is received with inverse polarity will be detected and
will be transmitted on the DXD and UXD pins with the
correct polarity. This polarity compensation is active
only while in the retime mode (MODE3 = 1).
• When NOT in the retime mode, the DPLL, APG, and
FIFO are bypassed, and the output is taken from the
selected input without any flip-flop delays (gate delays only). Also, automatic compensation for wiring
reversal is disabled when not in retime mode.
Carrier and Data Inputs
When an input has a signal present, the carrier will be
detected on the appropriate pin (CO - C11). The carrier
input is user selected for either external squelch (with
external one-shots) or internal squelch (a 2,..S pulse
stretcher is added by the HUB chip). MODE2 = 0
selects external squelch, and MODE2 = 1 selects internal.
Note, a carrier input must be active for at least three
clock samples for it to be recognized by the chip. Any
isolated pulse less than three clock samples wide will
be ignored. However, when using internal carrier
squelch, the carrier must be active for at least one clock
sample time every 2,..8 to be considered valid beyond
the initial carrier recognition. When not using internal
squelch, the carrier must be active during the entire
frame to avoid data loss. Ignoring carrier spikes provides extra noise protection and is also referred to as
time domain filtering (TDF).
Minimum Frame Length Enforcement
When minimum frame length enforcement (FLE) is enabled (MODE6 = 1) and the MK5030 is in retime mode,
the input carrier is assumed to be valid for at least 96
bit times. If either the incoming carrier goes inactive or
EOF is detected prior to 96 bit times, the MK5030 will
send collision presence (CP) for the remainder of the
96 bit times. This feature is important in mUlti-port environments where signal superposition may cause early
carrier dropout. NOTE: IEEE standards committee is,
at this printing, still defining FLE. The actual length
guaranteed is subject to change.
No-Retime Mode
If the retime mode is disabled, then the DPLL, FIFO,
and APG are bypassed. The outputs, DXD and UXD,
are taken from the selected input without clocked delays (i.e., flip-flops). There are gate delays only. End-offrame is detected by a counter instead of the DPLL. The
advantage of the no-retime mode is that two HUBs cascaded together will appear to the network as one. See
Fig. 3. In no-retime mode, an average of 2 bits will be
lost as outputs are enabled after the first rising edge
of the incoming data.
Retime Mode
The selected valid data input is fed to a digital phase
locked loop (DPLL). The DPLL is implemented with a
counter which clears on each transition. This gives a
jitter tolerance of 162ns peak to peak (83ns peak). This
is 40% more tolerance than required by the StarLAN
specification.
Protection Time
The valid input is passed through a 9 bit FIFO. Output
from the FIFO is prevented until the FIFO is 4 bits full.
This is called the 4 bit watermark, and gives the FIFO
4 bits of elasticity which is more than sufficient to absorb the allowable 0.01% clock tolerance.
At the end of each frame, all carrier inputs are ignored
for 20,..S. This is called the protection time and insures
immunity to post end-of-frame spikes caused by transformer coupling.
1-267
Collision
Jabber
A collision is defined when anyone of the following five
conditions exists: a. Multiple carrier inputs; b. Manchester code violations; c. FIFO underflow/overflow
exception. d. PLL lock acquisition timeout; e. frame
length violation. An IEEE defined collision presence
(CP) code is placed on the UXD output. The starting
pOint of the CP sequence is adjusted to allow faster CP
detection by the remote station or HUB. The HUB chip
is fully upward compatible with the existing AT&T release
1 CP signal. NOTE: b, C, and d are active collision
sources only while in retime mode.
If a station transmits data for greater than 27mS (which
allows twice its normal maximum frame size) then the
HUB will output a CP signal. This should correct the
error in the station in most cases. However, if that station continues to transmit for up to a total time of 54mS,
then the station is "jabbed". This means that the jabber function in the HUB chip will ignore that input and,
in effect, remove the station from the network. If the
"jabbed" station goes silent and then is the originator
of new data, the station is allowed back onto the network by the HUB chip.
Thus, StarLAN networks automatically adjust as portions of the network fail and are repaired.
-{] vee
MODE3
ool}----------j
-D vee
-D GNO
- { ] ONO
~-------.__iD~A
MUX
011ll''---~----:_::_'_-V
CO
e11)---+----I
>1
el1u--ri-L_-,-.,J
LEDO
LED1
X1
LED2
x,
LED3
RESETD-MODE1D-MODE2D-MODE3D-MODE4D-MODESD--
MooEeD-
Figure 5. MK5030 HUB Block Diagram
1·268
The Downlink Module
The downlink is identical to the uplink except without
the multiplexer, frame length enforcement, and jabber
functions. In the intermediate mode (MODE1 = 1), port
11 is a downlink input connected to the next "higher"
HUB downlink output. See Fig. 3. In the high-end mode
(MODE1 = 0), all twelve ports feed the uplink, and
DXD-DXEN are internally connected to UXD-UXEN.
CMOS input or a crystal. If pin X2 is left unconnected,
a 6.0MHz ± 0.01% CMOS clock may be applied to pin
X1. Alternately, a crystal circuit may be connected between X1 and X2 to form the basis of an oscillator. Typically, a 6.0 ± 0.005% parallel resonant crystal is needed
to insure the ± 0.01% frequency accuracy required for
StarLAN. Refer to Figure 7. A fundamental mode,
parallel resonance type crystal should be used with the
manufacturer's suggested load capacitance.
Status Display
OCLK provides a CMOS level clock output useful for
cascading HUB chips or driving surrounding logic.
Two display modes are supported: static and scan. When
LEDEN is externally tied to GND, then LEDO - LED3
provide static status information. When LEDEN is externally tied to VCC through a pull-up resistor, then an
external demultiplexer (such as a 74154) may be used
to provide 16 lines of status information. See Figures 4
and 6, and also see the description of pins LEDO - LED3.
Oscillator
The MK5030 will accept two forms of clock input: a
•••
=0<
Reset Input
The reset pin is an active low Schmidt trigger input. A
simple RC network may be used to insure correct operation upon power-up. Reset should be active for two
clock cycles (334 nS) to insure proper operation. In addition, if the mode inputs are changed after the application of power, reset must be reapplied. If either
MODE1 or MODE3 is changed, an internal reset is
generated automatically. Refer to Fig. 8.
X
0
X
W/!I!1l
WJ/////
r
r
v
STROBE POINTS
Figure 6. Scsn Display Timing
1-269
2
'WL
r
•••
LED3·0
•••
LEDEN
47p1
CMOS
X1
X1
LEVEL
CLOCK
NO
CONNECTION
6.0MHz
±.OO5%
0
X2
X2
-
47p1
B) CRYSTAL OPERATION
A) EXTERNAL CLOCK
Figure 7. Oscillator Operation
VCC
10K!l
e---------~
RESET
Figure 8. 1\tplcal RC Connection .For Power-On Reset
1-270
System Performance Considerations
Using the MK5030
The MK5030 has several modes of operation. This
allows designers flexibility in their design. Figure 9
shows a typical circuit diagram.
vee
vee
vee
PORTS 0-10 OUTPUT
6.0 MHz ± 0.005%
2'011
,
.,,,
.
, 74154
7
1~
""
""
48
.
c
45
44
41
v",
,Kn
PORT
of
10
39
11
38
.,
12
13
36
35
PORT 2 {
15
PORT 3{
34
16
33
17
32
18
31
19
PORT
s{
PORT 6 {
CIRCUIT
I
42
14
TYPICAl.. INPUT
47/,F
43
PORT 1{
3)11
10KIl
48
vee
30
20
"
21
22
28
27
"
28
25
PORT 11
OUTPUT
f PORT 11
} PORT 10
} PORT9
} PORT 8
} PORT 7
24
-=-
Figure 9. MK5030 External Component Diagram
1-271
ELECTRICAL SPECIFICATIONS
This chapter provides tabular presentations for Absolute Maximum Ratings, DC Characteristics, Capacitance, and
AC Timing Specifications. In addition, illustrations are provided for an Output Load Diagram (Figure 14) and HUB
Timing Diagrams.
ABSOWTE MAXIMUM RATINGS
Temperature Under Bias ....................................................... -25"C to +100"C
Storage Temperature .......................................................... -65"C to +150"C
Voltage on Any Pin with Respect to Ground .................................... -0.5 V to Vee +0.5 V
Power Dissipation (no load) .............................................................. 125mW
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other condition above those indicated in the operational sections of the specification is not Implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
TA = O"C to 7O"C, Vee = +5 V ±5% unless otherwise specified.
MIN
SYMBOL CONDITIONS
Vil
MAX
UNITS
-0.5
+0.8
V
VIH
Except Pin X1
+2.0
Vee +0.5
V
VIH
Pin X1
+3.5
Vee +0.5
V
VOL
@ IOl = 3.2 rnA
+0.5
V
VOH
@ IOH = -0.4 rnA
III
@ V IN = 0.4 to Vee
±10
pA
Icc
@TXI = 6 MHz
25
rnA
+2.4
V
CAPACITANCE
F = 1 MHz
SYMBOL CONDITIONS
MIN
MAX
UNITS
C IN
10
pf
COUT
10
pf
C IO
20
pf
AC TIMING SPECIFICATIONS·
TA = O"C to 7O"C, Vee = +5 V ±5% unless otherwise specified, VTH = 2.0 V, VTL = 0.8 V.
#
SIGNAL SYMBOL PARAMETER
MIN
TYP
MAX
ns
ns
ns
1
Xl
TXIT
X1 period
160
2
Xl
TXll
X1 low time
60
3
Xl
TXIH
X1 high time
60
4
Xl
TXIR
Rise time of X1
0
10
TXIF
Fall time of X1
0
10
5
Xl
1·272
AC TIMING SPECIFICATIONS (cont.)
TA = O°C to 70°C, VCC = +5 V ±5% unless otherwise specified.
SIGNAL
#
SYMBOL PARAMETER
TYP
ns
MIN
ns
6
X2
TX2
X2 delay from X1
7
OCLK
TOCLK
OCLK delay from X1
MAX
ns
30
45
8
UXD
TUXD
UXD delay from X1
45
65
9
UXEN
TUXEN
UXEN delay from X1
48
75
10
DXD
TDXD
DXD delay from X1
48
65
11
DXEN
T DXEN
DXEN delay from X1
51
75
2
4
2
4
I TUXDi-TUXD~ 1+2
I TDXD i -T DXD~ I +2
12
UXD
J UXD
Transmit jitter:
13
DXD
J DXD
Transmit jitter:
14
CO•11
Tcs
C O•11 Setup to X1
15
15
CO•11
TCH
C O•11 Hold from X1
15
16
DO•11
TDS
DO•11 Setup to X1
15
15
17
DO•11
TDH
DO•11 Hold from X1
18
DO•11
J DIN
DO•11 Incoming jitt!3r tolerance
19
UXD,DXD
TpXD
Delay from any D input
162
20
UXD,DXD
J NR
No retime mode jitter: I TXDi-TxD~ I :-2
21
LED O•3
TLED
Delay from X1
22
LEDEN
TLEDENR Guaranteed release time until LED o.3 change
23
LEDEN
,...
4_
/-
X2
...
4
2660
-
•
-'
2
1\~5
... ...
-
'r r
3
-
2
2600
1
X1
60
50
Delay from LEDO•3 transition
TLEDEN
42
OCLK
Figure .10. Oscillator Timing Diagram
1-273
..
f'-
V
X1
\
\.
r
~+-
iiXo
~L
UXEN
DXo
----
\
U
f f
101--
~\
OXeN
H
Jf
J;
~'rI
-l;r-
-
XXXXX
14
D'N
%XXX
16 I
I
XXXiX/..
15
xt:fXIY..
17
Figure 11. Retlmer Enabled (MODE3
DXD,iiXo
I
-l"tI
111---
C'N
10r---
= 1) Timing Diagram
~t1t=
d'
,
,{II+--.
__
------_
.....
Figure 12. Retimer Disabled (MODE3 = 0) Timing Diagram
X1
LEDO-3
_
_
__. . t'"'L..~-_-22_--_+=.j.oI
.______D
L
~t
Figure 13. Status Display Timing Diagram
1-274
FROM OUTPUT LEDEN
UNDER TEST
~'A<
1.
50pF
TEST
POINT
R,
=
1.2K
CR,
FROM ALL OTHER OUTPUTS (")._ _ _ _ _ _- - - -....- - - - / ( "
UNDER TEST
O.4mA
I
CL
= 50pF MIN
CR, .CR.
@ 1 MHz
= lN914 OR
EQUIVALENT
Figure 14. Output Load Diagram
GLOSSARY OF TERMS
automatic preamble
generator (APG)
protection
time
downlink
An optional circuit in the HUB
chip which will begin preamble
generation before the FIFO
reaches the 4 bit watermark.
The APG replaces a 2 bit loss in
the preamble through a HUB
with a 2 bit gain. See Retime
Mode.
A 20l'S period at the end of each
frame where all carrier inputs
are ignored. This protection insures immunity to post end-offrame spikes caused by transformer coupling. See Protection
Time.
The data path going from a
"higher" HUB to the next "lower': HUB, or going from a HUB
back to the stations.
1-275
high-end hub
A HUB that does not connect to
another "higher" HUB. The
downlink outputs, OXO and
OXEN, are internally connected
to the uplink outputs, UXO and
UXEN.
intermediate hub
A HUB that connects to another
"higher" HUB. Pins C11 and 011
must be used as downlink
inputs.
jabber
A circuit module inside the HUB
chip which protects the network
from a station which is constantly transmitting. See Jabber.
uplink
The data path going from a "lower" HUB to the next "higher"
HUB, or going from the stations
to a HUB.
PACKAGE
48
Pin C DESCRIPTION
ramIC
MKS030:
[
I. -
~
ri'
--
I
____
I __
'I
IB
PACKAGE
~~-------------48
Pin PI D~SCRIPTION
MKS030Nastic
]J
--~~=;:--:~--------
1·276
MI{ 5032 (P IN)
VARIABLE BIT-RATE (1 - 10 MHz)
IEEE 802 3 CONTROLLER
FEATURES
o
Identical pinout to MK68590 Ethernet Controller
o
Supports LAN Standards:
IEEE 802.3, Ethernet, Cheapernet, and StarLAN
o
Supports data rates from 1 to 10 Mbps
o
Supports system clocks from 1 to 10 MHz.
READ
o
o
iNTi
DiU
i5ALO
lIAs
On-chip DMA with buffer management using circular queues.
Complete CSMAlCD data link controller (MAC).
iiMo/8YTE
11M'; IIiliAirn
o
Preamble insertion and checking.
o
CRC insertion and stripping.
o
.
Vss
DAL07
DAL08
DAW.
DAL04
DAL03
DAL02
DAL01
DALOO
iiotiiliUSRQ
ALE/Ai
iiLDA
cs
ADR
General purpose bus interface compatible with 8086
and 68000 buses.
o
Cable fault detection.
o
48 pin DIP. +5V only. All inputs/outputs TIL compatible.
o
Compatible with MK5033, MK5034, MK50351, and
MK50361 Encoder/Decoder and with MK68591/2
Serial Interface Adaptor.
mDv
REsET
VSS
47
40
40
44
43
42
41
10
11
12
13
14
1.
16
17
18
19
20
21
22
23
24
DAL"
DAL12
DAL13
DAl14
40
OAL16
39
A16
A17
A18
A19
A20
A21
A22
A23
RX
38
MK5032
vee
DALOa
DALD9
DAL10
37
36
35
34
33
32
31
30
29
28
27
26
25
RENA
TX
CLSN
RCLK
TENA
SCLK
Figure 1. MK5032 Pin A88lgnment
DESCRIPTION
The 5032 Variable Bit-Rate LANCE is a 48-pin VLSI
device that simplifies the interfacing of a microcomputer
or a minicomputer to an IEEE 802.3 Local Area Network.
PIN DESCRIPTION
DALOO·DAL15
(Data/Address Bus)
Input/Output Three State. The time multiplexed Address/Data bus. These lines will be driven as a bus
master and as a bus slave.
READ
Input/Output Three State. Indicates the type of operation to be performed in the current bus cycle. When it
lANCE stands lOr L.ocaJ Area Network Controller for Ethernet.
LANCE Is a trademark of Thomson Components· Mostek Corporatlon
1-277
is a bus master, MK5032 drives this signal.
MK5032 as bus slave:
High - The chip places data on the DAL lines.
Low - The chip takes data off the DAL lines.
MK5032 as bus master:
High - The chip takes data off the DAL lines.
Low - The chip places data on the DAL lines.
INTR
(Interrupt)
Output Open Drain. When enabled, an attention signal that indicates the occurrence of one or more of the
following events: a message reception or transmission
has completed or an error has occurred during the
transaction; the initialjzation procedure has completed;
or a memory error has been encountered. Setting INEA
in CSRO (bit 06) enables INTR.
DALI
(Data/Address Line In)
Output Three State. An external bus transceiver controlline. When MK5032 is a bus master and reads from
the DAL lines, DALI is asserted during the data portion
of the transfer.
DALO
(Data/Address Line Out)
Output Three State. An external bus transceiver controlline. When MK5032 is a bus master and drives the
DAL lines, DALO is asserted during the address portion of a read transfer or for the duration of a write
transfer.
DAS
(Data/Strobe)
Input/Output Three State. Defines the data portion of
the bus transaction. DAS is driven only as a bus master.
BMO, BM1 or BYTE, BUSAKO
(Byte Mask)
Output Three State. Pins 15 and 16 are programmable
through bit (00) of CSR3 (known as BCON). Asserting
RESET clears CSR3.
CSR3(00) BCON = 0
PIN 16 = BM1 (Output Three State)
PIN 15 = BMO (Output Three State)
BMO, BM1 Byte Mask. Indicates the byte(s) of a bus
transaction to be read or written. The BM lines are
ignored as a bus slave and assume word transfers only.
The MK5032 drives the BM lines only when it is a bus
master. Byte selection occurs as follows:
Low
Low
High
High
Low
High
Low
High
Whole Word
Byte of DAL 08 - DAL 15
Byte of DAL 00 - DAL 07
None
BSWP = 0
BSWP = 1
BYTE DAL(OO) BYTE DAL(OO)
Low
Low
High
High
Low
High
High
Low
Low
Low
High
High
Low
High
Low
High
Whole· Word
Illegal Condition
Upper Byte
Lower Byte
BUSAKO. The DMA daisy chain output.
HOLD/BUSRQ
(Bus Hold Request)
Input/Output Open Drain. MK5032 asserts this signal
when it requires access to memory. HOLD is held low
for the entire bus transaction. This bit is programmable through bit (00) of CSR3 (known as BCON). In the
daisy chain DMA mode (BCON = 1) BUSRQ is asserted only if BUSRQ is inactive prior to assertion. Bit (00)
of CSR3 is cleared when RESET is asserted.
CSR3(00) BCON = 0
PIN 17 = HOLD (Output Open Drain)
CSR3(00) BCON = 1
PIN 17 = BUSRQ (Output Open Drain)
BUSRQ will be asserted only if PIN 17 is high prior
to assertion.
ALE/AS
(Address Latch Enable)
Output Three State. Used to demultiplex the DAL lines
and define the address portion of the bus cycle. This
pin is programmable through bit (01) of CSR3. As ALE,
the signal transitions from high to low at the end of the
address portion of the bus the address portion of the
bus transaction and remains low during the entire data
portion of the transaction. As AS, the signal transitions
from low to high at the end of the address portion of
the bus transaction and remains high throughout the
entire data portion of the transaction. The MK5032
drives the ALE/AS line only as a bus master.
CSR3(01) ACON = 0
PIN 18 = ALE
CSR3(01) ACON = 1
PIN 18 = AS
CSR3(00) BCON = 1
PIN 16 = BUSAKO (Output)
PIN 15 = BYTE (Output Three State)
BYTE. An alternate byte selection line. Byte selection
occurs when the BYTE and DAL (00) lines are latched
during the address portion of the bus transaction.
BYTE, BMO and BM1 are ignored when MK5032 is a
bus slave. There are two modes of ordering bytes depending on bit (02) of CSR3, (known as BSWP). This
programmable ordering of upper and lower bytes when
using BYTE and DAL (00) as selection signals is required to make the ordering compatible with various
16-bit microprocessors.
HLDA
(Bus Hold Acknowledge)
Input. A response to HOLD indicating that the MK5032
is the Bus Master. HLDA stops its response when HOLD
ends its assertion.
CS
(Chip Select)
Input. When asserted, CS indicates MK5032 is the
slave device of the data transfer. CS must be valid
throughout the data portion of the bus cycle.
1-278
ADR
(Register Address Port Select)
Input. When CS is asserted, ADR indicates which of the
two register ports is selected. ADR must be valid
throughout the data portion of the bus cycle.
ADR
Low
High
RENA
(Receive Enable)
Input. A logical input that indicates the presence of data
on the channel.
RX
(Receive)
Input. Receive input bit stream.
PORT
Register Data Port
Register Address Port
READY
Input/Output Open Drain. When the MK5032 is a bus
master, READY is an asynchronous acknowledgement
from external memory that will complete the data transfer. As a bus slave, the chip asserts READY when it has
put data on the bus, or is about to take data off the bus.
READY is a response to DAS. READY negates after
DAB negates. Note: If DAS or CS deassert prior to the
assertion of READY, READY cannot assert.
RESET
Input. Bus reset signal. Causes MK5032 to cease operation and to enter an idle state.
SCLK
(System Clock)
Input. A clock from 1 to 10 MHz.
A16-A23
(High-Order Address Bus)
Output Three State. The additional address bits necessary to extend the DAL lines to produce a 240bit address. These lines will be driven only as a bus master.
VCC
Power supply pin. +5 VDC ±5 percent.
Filtering: A power supply filter is recommended at the
MK5032 between Vee (48) and Vss (1,24). This filter
consists of two capaCitors in parallel having the values
of 10 p.f and .047 p.f respectively.
VSS
Ground. 0 VDC.
FUNCTIONAL CAPABILITIES
TENA
(ll'Imsmit Enable)
Output. Transmit Output Stream Enable. A level
asserted with the transmit output bit stream, TX, to enable the external transmit logic.
RCLK
(Receive Clock)
Input. Normally a 6 square wave synchronized to the
receive data and present only while receiving an input
bit stream.
CLSN
(Collision)
Input. A logical input that indicates that a collision is
occurring on the channel.
TX
(Transmit)
Output. Transmit output bit stream. This pin is programmable through bit (07) of the MODE REGISTER (MAN).
When this bit is a "zero" the output data stream will
be NRZ. When MAN is set to a "one", the data will be
Manchester Encoded starting at a zero level and ending at the end of packet in a marking condition. (Continuous one level.) This mode will function only when
the data rate is programmed less than the rate of SCLK.
Three other bits in the MODE register provide a data
rate divison of 1, 2, 4, 6, 8, or 10. This means that the
data rate of TX will be a division of SCLK. For more details on the MODE register, see the technical manual.
The MK5032 interfaces to a microprocessor bus characterized by time-multiplexed address and data lines. Typically, data transfers are 16 bits wide but byte transfers
occur if the buffer memory address boundaries are odd.
The address bus is 24 bits wide.
The IEEE 802.3 packet format consists of 64-bit preamble, a 48-bit destination address, a 48-bit source address, a 16-bit type field, and from a 46 to 1500 byte
data field terminated with a 32-bit CRC. The packets'
variable widths accommodate both short-status command and terminal traffic packets and long data packets to printers and disks (1024-byte disk sectors, for
example). Packets are spaced a minimum of 96 bit
times apart to allow one node enough time to receive
back-ta-back packets.
The MK5032 operates in a minimal configuration that
requires close coupling between local memory and a
processor. The local memory provides packet buffering
for the chip and serves as a communication link between chip and processor. During initiaHzation, the control processor loads the starting address of the
initialization block plus the operating mode of the chip
via two ports that can access four control registers into
MK5032. The host processor talks directly to MK5032
only during this initial phase. All further communications
are handled via a Direct Memory Access (DMA)
machine under microword control contained within
MK5032. Figure 2 shows a block diagram of the
MK5032 and PLS (MK68951, MK50351, MK50361, or
MK5033) device used to create an IEEE 802:3 interface
for a computer system.
1-279
C
o
M
P
MICROPROCESSOR
U
R
• MK68200
• MK68000
• 18086
S
• LSI·ll
T
E
• Z8000
• T·11
Y
S
T
E
M
B
U
S
-
16fATA
-
24-ADDRESS
IEEE 802.3
MEDIA ACCESS
CONTROLLER
(VLANCE)
MK5032
~
PHYSICAL
SIGNALING PLS
MK68591/5034
MK50351
MK50361
A
AUI
MAU
CABLE
POWER
.!r
LOCAL
MEMORY
NETWORK INTERFACE MODULE
Figure 2. Ethernet Local Area Network System Block Diagram
1-280
LOCAL
NETWORK
CABLE
OR
STARLAN
NETWORK
buffer. During reception, the detection of a collision
causes that reception to be aborted. Depending on
when the collision occurred, MK5032 will treat this packet as an error packet if the packet has an address mismatch, as a runt packet (a packet that has less than
64 bytes), or as a legal length packet with a CRC error.
FUNCTIONAL DESCRIPTION
SERIAL DATA HANDLING
MK5032 provides the IEEE 802.3 interface as follows.
In the transmit mode (since there is only one transmission path, IEEE 802.3 is a hal! duplex system), the
MK5032 reads data from a transmit buffer by using
DMA and appends the preamble, sync pattern (two
ones after alternating ones and zeros in the preamble),
and calculates and appends the complement of the
_32-bit CRC. In the receive mode, the destination address, source address, type, data, and CRC fields are
transferred to memory via DMA cycles. The CRC is calculated as data and transmitted CRC is received. At the
end of the packet, if this calculated CRC does not agree
with a constant, an error bit is set in RDMl of the
receiver descriptor ring. In the receive mode, MK5032
accepts packets under four modes of operation. The
first mode is a full comparison of the 48-bit destination
address in the packet with the node address that was
programmed into the MK5032 during an initialization
cycle. There are two types of logical addresses. One
is a group type mask where the 48-bit address in the
packet is put through a hash filter in order to map the
48-bit physical addresses into 1 of 64 logical groups.
This mode can be useful if simultaneously sending
packets to all of one type of a device on the network.
(i.e., send a packet to all file servers or all printer servers). The second logical address is a multicast address
where all nodes on the network receive the packet. The
last receive mode of operation is the so called "promiscuous mode" in which a node will accept all packets
on the cable regardless of their destination address.
Fatal error reporting is provided by the MK5032 through
a microprocessor interrupt and error flags in CSRO.
These error conditions are collision error (the failure of
the MAU to send a signal-quality-error message at the
conclusion of a normal transmission), transmitter ON
longer than 1518 bytes, a missed packet, and a memory
error (failure of a memory transaction to complete within 256 sys clocks).
Additional errors are reported through bits in the
descriptor rings (on a buffer by buffer basis). Receive
error conditions include framing, CRC and buffer errors,
and overflow. Transmit descriptor rings have error bits
indicating buffer, underflow, late collision, and loss of
carrier. Additionally, transmit descriptor rings have a bit
indicating that the transmitter has unsuccessfully tried
to transmit over a busy communication link.
Transmit descriptor rings also have ten bits reserved
for a Time Domain Reflectometry counter (TOR). On the
occurrance of a collision, the value in the TOR will give
the number of system clocks until the collision, which
can be used to determine the distance to the fault.
BUFFER MANAGEMENT
COLLISION DETECTION AND IMPLEMENTATION
The IEEE 802.3 CSMNCD network access algorithm
is implemented completely within MK5032. In addition
to listening for a clear network cable before transmitting, IEEE 802.3 handles collisions in a predetermined
way. Should two transmitters attempt to seize the network cable at the same time, they will collide, and the
data on the network cable will be garbled. MK5032 is
constantly monitoring the Collision (CLSN) pin. This signal is generated by the MAU when the signal level on
the network cable indicates the presence of signals
from two or more transmitters. I! MK5032 is transmitting when CLSN is asserted, it will continue to transmit
the preamble (collisions normally occur while the
preamble is being transmitted), then will "jam" the network for 32 bit times. This jamming ensures that all
nodes have enough time to detect the collision. The
transmitting nodes then delay a random amount of time
according to the "truncated binary backoff" algorithm
defined in the IEEE 802.3 specification to minimize the
probability of the colliding nodes having multiple collisions with each other. After 16 abortive attempts to
transmit a packet, MK5032 will report a RTRY error due
to excessive collisions and step over the transmitter
A key feature of the MK5032 and its DMA channel is
the flexibility and speed of communication between the
MK5032 and the host microprocessor through common
memory locations. The basic organization of the buffer
management is a circular queue of tasks in memory
called descriptor rings, as shown in Figure 3. These
rings control both transmit and receive operations. Up
to 128 tasks may be queued on a descriptor ring for execution by the MK5032. Each entry in a descriptor ring
holds a pointer to a data memory buffer and an entry
for the data buffer length. Data buffers can be chained
or cascaded to handle a long packet in multiple data
buffer areas. The MK5032 searches the descriptor rings
to determine the next empty buffer. This enables it to
chain buffers together or to handle back-to-back packets. As each buffer is filled, an "own" bit is reset, signaling the host processor to empty this buffer.
MICROPROCESSOR INTERFACE
The parallel interface of MK5032 has been designed
to be "friendly", or easy to interface, to many popular
16-bit microprocessors. These microprocessors include
the MK68000, zaooo, 8086, LSI-ll, T-11, and MK68200
(the MK68200 is a 16-bit single chip microcomputer
produced by Mostek, the architecture of which is modeled after the MK68000). MK5032 has a wide 24-bit
linear address space when in the Bus Master Mode,
1-281
demultiplexed data busses and features control signals
for address/data bus transceivers.
allowing it to DMA the entire address space of the above
microprocessors. MK5032 uses no segmentation or
paging methods. As such, MK5032 addressing is
closest to MK68000 addressing, but is compatible with
the other microprocessors. When MK5032 is a bus
master, a programmable mode of operation allows byte
addressing, either by employing a Byte/Word control
signal (much like that used on the 8086 or the Z8000)
or by using an Upper Data Strobe/Lower Data Strobe
much like that used on the MK68000, LSI-11 and
MK68200 microprocessors. A programmable polarity on
the Address Strobe signal eliminates the need for
external logic. MK5032 interfaces with multiplexed and
MK5032 CSR REGISTERS
rl
POINTER TO INITIALIZATION
BLOCK
After the initialization routine, packet reception or transmission, transmitter timeout error, a missed packet, or
memory error, the MK5032 generates an interrupt to the
host microprocessor.
The cause of the interrupt is ascertained by reading
CSRO. Bit (06) of CSRO, INEA, enables or disables
interrupts to the microprocessor. In the polling mode,
BIT (07) of CSRO is sampled to determine if an interrupt causing condition has occurred.
RECEIVE BUFFER
I
~~
,....""R_EC_E_'V_E_D_E_SC_R_'P_T_O_R_R_'N_G_S_______
~
r;:;
~::-
ADDRESSOFRECE'VEBUFFERO
~
BUFFER 0 BYTE COUNT
_ _----_ - ; ; ; ; : ; ; PACKET
. /'
~~
~~
----... MODE OF OPERATION
-
•
•
.
~;:::.
PHYSICAL ADDRESS
__ DATA
t:: -..f------:::--------t__---------tl1 PA~KET
LOGICAL ADDRESS fiLTER
POINTER TO RECEIVE RINGS
,
/ '
--:;:/:
',
//
INITIALIZATION
BLOCK
'---
BUFFEROSTATUS
N
--~~------~~--------~
-
NUMBER OF RECEIVE ENTRIES
POINTER TO TRANSMIT RINGS
TRANSMIT DESCRIPTOR RINGS
NUMBER OF TRANSMIT ENTRIES
TRANSMIT BUFFE
~~
PACKET 0
V/
:.-..-:
~
ADDRESS OF TRANSMIT BUFFERS 0
~ BUFFER 0 STATUS
~
~
g§
SUP EA 0 BYTE COUNT
-
,
:
§§
•
§§
:
./' -'
N
~
-
DATA
,
PACKET
@§~--:
-
-----J
---~__I~
PACKET
N
Figure 3. MK5032 Memory Management
1-282
MK5032 INTERFACE DESCRIPTION
ALE, DAS and READY time all data transfers from the
MK5032 in the Bus Master mode. The automatic adjustment of the MK5032 cycle by the READY signal
allows synchronization with variable cycle time memory
due either to memory refresh or to dual port access.
Bus cycles are a minimum of 600 ns long and can be
increased in 100 ns increments.
READ SEQUENCE
At the beginning of a read cycle, valid addresses are
placed on DALOO-DAL15 and A16-A21. The BYTE Mask
signals (BMO and BM1) become valid at the beginning
of this cycle as does READ, indicating the type of cycle. The trailing edge of ALE or AS strobes the
addresses AO-A15 into the external latches. Approximately 100 ns later, DALOO-DAL15 go into a three state
mode. There is a 50 ns delay to allow for transceiver
turnaround, then DAS falls low to signal the beginning
of the data portion of the cycle. At this point in the cycle, the MK5032 stalls waiting for the memory device
to assert READY. Upon assertion of READY, DAS
makes a transition from a zero to a one, latching
memory data. (DAS is low for a minimum of 200 ns).
The bus transceiver controls, DALI and DALO, control
the bus transceivers. DALI signals to strobe data toward
the MK5032 and DALO signals to strobe data or addresses away from the MK5032. During a read cycle, DALO
goes inactive before DALI goes active to avoid "spiking"
of bus transceivers.
WRITE SEQUENCE
The write cycle begins exactly like a read cycle with the
READ line remaining inactive. After ALE or AS pulse,
the DALOO-DAL15 change from addresses to data. DAS
goes active when the DALOO-DAL15 are stable. This
data remains valid on the bus until the memory device
asserts READY. At this pOint, DAS goes inactive,
latching data into the memory device. Data is held for
75 ns after the negation of DAS.
MK5032 INTERFACE DESCRIPTION MODE
BUS SLAVE
The MK5032 enters the Bus Slave Mode whenever CS
becomes active. This mode must be entered whenever
writing or reading the four status control registers
(CSRO, CSR1, CSR2, and CSR3) and the register address pOinter (RAP). RAP and CSRO may be read or
written to at any time, but the MK5032 must be stopped
(CSRO bit 02) when CSR1, CSR2, or CSR3 is to be written to or read.
1-283
MKS032 ELECTRICAL SPECIFICATION
ABSOWTE MAXIMUM RATINGS
Temperature Under Bias ....................................................... -25OC to +125OC
Storage Temperature .......................................................... -65OC to +150OC
Voltage on Any Pin with Respect to Ground ......................................... -0.3 V to +7 V
Power Dissipation ....................................................................... 2.0 W
Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other condition above those indicated In the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
TA=OOC to 7OOC, Vcc = +5 V ±5 percent unless otherwise specified.
SYMBOL PARAMETER
MIN
MAX
UNITS
-0.5
+0.8
V
+2.0
Vcc +0.5
V
+0.5
V
±10
,lAo
MAX
UNITS
10
pf
COUT
10
pf
CIO
20
pf
VIL
VIH
VOL
@ IOL = 3.2 rnA
VOH
@ IOH = -0.4 rnA
IlL
@ Vin = 0.4 to Vcc
+2.4
V
CAPACITANCE
F=1 MHz
SYMBOL PARAMETER
MIN
CIN
AC TIMING SPECIFICATIONS
T A = 0 OC to 70 OC, Vcc = +5 V ±5 percent, unless otherwise specified.
NO. SIGNAL
TEST
CONDITIONS
SYMBOL PARAMETER
MIN
(ns)
TYP
(ns)
MAX
(ns)
1
SCLK
TSCT
SCLK period
99
101
2
SCLK
TSCL
SCLK low time
45
55
3
SCLK
TSCH
SCLK high time
45
55
0
8
0
4
SCLK
TSCR
Rise time of SCLK
5
SCLK
TSCF
Fall time of SCLK
6
TENA
TTEP
TENA propagation delay after the
rising edge of SCLK
CL = 50 pf
7
TENA
TTEH
TENA hold time after the rising edge
.of SCLK
CL=50pf
1·284
8
75
5
AC TIMING SPECIFICATIONS (Continued)
TA = OOC to 70OC, VCC = +5 V ±5 percent, unless otherwise specified.
NO. SIGNAL SYMBOL
TEST
CONDITIONS
PARAMETER
MIN
(ns)
TYP
(ns)
MAX
(ns)
8
TX
TTOP
TX data propagation delay after the
rising edge of SCLK (See Note 1)
CL=50 pf
SA
TX
TTDTT
TX Transition - Transition (See Note 2)
CL=50 pF
B,-7
9
TX
TTOH
TX data hold time after the rising
edge of SCLK (See Note 1)
CL=50 pf
5
10
RCLK
TRCT
RCLK period
11
RCLK
TRCH
RCLK high time
38
12
RCLK
T RCL
RCLK low time
38
13
RCLK
TRCR
Rise time of RCLK
0
8
14
RCLK
TRCF
Fall time of RCLK
0
8
15
RX
TROR
RX data rise time
0
8
16
RX
TROF
RX data fall time
0
8
17
RX
T ROH
RX data hold time (RCLK to RX
data change)
5
18
RX
TROS
RX data setup time (RX data stable to
75
85
(See Note 3 the rising edge of RCLK)
B,+7
118
See
Note 3
19
RENA
T OPL
RENA low time
120
20
RENA
TRENH
RENA hold time after
rising edge of RCLK
40
80
21
CLSN
TCPH
CLSN high time
22
AlDAL
TOOFF
Bus master driver disable after rising
edge of HOLD
0
50
23
AlDAL
TOON
Bus master driver enable after falling
edge of HLDA
0
150
24
HLDA
THHA
Delay to falling edge of HLDA from
falling edge of HOLD (bus master)
0
25
RESET TRW
RESETpulse width low
200
26
AlDAL
TevCLE
Read/write, address/data cycle time
600
27
A
TXAS
Address setup time to the falling edge of
ALE
75
28
A
TXAH
Address hold time after the rising edge
ofDAS
35
29
DAL
TAS
Address setup time to the falling edge
of ALE
75
30
DAL
TAH
Address hold time after the falling
edge of ALE
35
31
DAL
T ROAS
Data setup time to the rising edge
of DAS (bus master read)
50
NOTE: I. This timing is for the NRZ mode only.
2. Bt = Bit time. This measurement is during preamble; valid for Manchester Mode only.
3. TROS (min) ~ TRCT - 25 ns. Therefore, TRCT ~ 100 ns when TROS (min) ~ 75 ns.
1-285
AC TIMING SPECIFICATIONS (Continued)
TA = OOC to 7OOC, Vee = +5 V ±5 percent, unless otherwise specified.
TEST
CONDITIONS
NO. SIGNAL SYMBOL PARAMETER
MIN
(ns)
TYP
(ns)
32
DAL
TROAH
Data hold time after the rising edge of
DAS (bus master read)
0
33
DAL
TOOAS
Data setup time to the falling edge
of DAS (bus master write)
0
34
DAL
Twos
Data setup time to the rising edge
of DAS (bus master write)
200
35
DAL
TWOH
Data hold time after the rising edge
of DAS (bus master write)
35
36
DAL
TSOOl
Data driver delay after the falling edge
of DAS (bus slave read)
(CSR 0,3, RAP)
400
:r7
DAL
TSOO2
Data driver delay after the falling edge
of DAS (bus slave read)
(CSR 1,2)
1200
38
DAL
TSROH
Data hold time after the rising edge
of DAS (bus slave read)
0
39
DAL
TSWOH
Data hold time after the rising edge
of DAS (bus slave write)
0
40
DAL
Tswos
Data setup time to the falling edge
of DAS (bus slave write)
0
41
ALE
TALEW
ALE width high
120
42
ALE
TOALE
Delay from rising edge of DAS to
the rising edge of ALE
70
43
DAS
Tosw
DAS width low
200
44
DAS
TAOAS
Delay from the falling edge of ALE to the
falling edge of DAS
80
45
DAS
TRIOF
Delay from the rising edge of DALO to the
falling edge of DAS (bus master read)
15
46
DAS
TRDYS
Delay from the falling edge of READY
Taryd=
to the rising edge of DAS
300 ns
75
47
DALI
TROIF
Delay from the rising edge of DALO to
the falling edge of DALI (bus master read)
15
48
DALI
TRIS
DALI setup time to the rising edge
of DAS (bus master read)
135
49
DALI
TRIH
DALI hold time after the rising edge
of DAS (bus master read)
0
50
DALI
TRIOF
Delay from the rising edge of DALI to the
falling edge of DALO (bus master read)
55
51
DALO
Tos
DALO setup time to the falling edge
of ALE (bus master read)
110
52
DALO
TROH
DALO hold time after the falling edge
of ALE (bus master read)
35
53
DALO
Twosl
Delay from the rising edge of DAS to the
rising edge of DALO (bus master write)
1·286
35
)
MAX
(ns)
35
150
130
250
..
AC TIMING SPECIFICATIONS (Continued)
TA = O°C to 70OC, Vee = +5 V ±5 percent, unless otherwise specified.
TEST
CONDITIONS
NO. SIGNAL SYMBOL PARAMETER
MIN
(ns)
TYP
(ns)
54
CS
TeSH
CS hold time after the rising edge of DAS
(Bus slave)
0
55
CS
Tess
CS setup time to the falling edge of DAS
(Bus slave)
0
56
ADR
TSAH
ADR hold time after the rising edge of
DAS (Bus slave)
0
57
ADR
TSAS
ADR setup time to the falling edge of
DAS (Bus slave)
0
58
READY
TARYD
Delay from the falling edge of ALE
to the falling edge of READY to insure a
minimum bus cycle time (600 ns)
59
READY
TSRDS
Data setup time to the falling edge of
READY (Bus slave read)
75
60
READY
TRDYH
READY hold time after the rising edge
of DAS (Bus master)
0
61
READY
TSR01
READY driver turn on after the falling
edge of DAS (Bus slave)
(CSR 0,3, RAP)
600
62
READY
TSR02
READY driver turn on after the falling
edge of DAS (Bus slave)
(CSR 1,2)
1400
63
READY
TSRYH
READY hold time after the rising
edge of DAS (Bus slave)
0
64
READ
TSRH
READ hold time after the rising
edge of DAS (Bus slave)
0
65
READ
TSRS
READ setup time to the falling
edge of DAS (Bus slave)
0
1·287
MAX
(ns)
80
35
TEST
POINT
v..
R,
= 1.2K
CR, ·CR.
_---+----<
FROM OUTPUT 0 - - - -.......
UNOERTEST
CR,
IN914 OR EQUIVALENT
C L = 100pf min@ 1 MHz
O.4mA
I
NOTE: This load is used on DALOO through DAL15. READ, DALI. OALQ, CAS, BMO. BM1. ALE/AS. A16 through A23, TENA. and lX.
Figura 4. Output Load Diagram
VCC
FROM OUTPUT
UNDER TEST
NOTE: ThIBIoad IB used on opsn drain outpUt8INTR. HOLOIBUSRQ. and READY.
Figura 5. Open Drain Output Load Diagram
1·288
~_______
,o
12
r-\
ACU<
AX
RENA
a~"
_1=:'.
7/!I/////II//JlJ/I//J/~
---.I
17
'5
13
"
14
X"''I2rr7!TT7~TT'jj
~rr;~'777!"T772TT,//rr7tTT7~TT71Z
1--20...,
SCLK
TlC
lENA
"'"
"0"
2.0V
2.0V
O.BV
INPUT
FLOAT
V
o.sv
OUTPUT
Nare: Timing measurements are made at the following voltages unless otherwise specified.
Figure 6. Physical Link Signaling Timing Diagram -·PLS-VMAC Interface Signals
1-289
O.OV
100
200
300
400
500
600
I
I
I
I
I
I
A 16-23
ALE
DAlO-15
(WRITE)
CALO
(WAITE)
i5AU
(WRITE)
-----'I
READ
(WAITE)
DAlO-15
(READ)
DALO
(READ)
I5Ai:i
(READ I
READ
(READ)
8MO.1
NOTE:
The Bus Master cycle time will increase from
a minimum of 600 ns in 100 ns steps until
the slave device returns READY.
Figure 7. MK5032 Bus Master Timing Diagram
1-290
1l
~.~
--=t"r~ -=:.~
ADA
~--"--------~W!////h
------61,62
--1
-------<~
05
READ
fREAD}
OALO-15
(READ)
DATA OUT
j-l=r---
READ
(WRITE)
~-'---,j3..r--~
-'-'-----_ _ _ _ l:L _ _
DATA IN
Figure 8. MK5032 Bus Slave Timing Diagram
1-291
1·292
MI(5033N
.----a..-~-
MANCHESTER ENCODERIDECODER
COMMUNICATIONS PRODUCTS
FEATURES
o
Conforms to StarLAN specifications.
o
o
o
Supports multi-point extension.
Auto compensation for line reversal.
Compatible with most Ethernet controller chips.
o
Data rates DC to 2.66Mbps supported.
o
Manchester or Differential Manchester data
encoding/decoding.
o
Full duplex or half duplex operation.
o
Supports Star, Bus, or Point-ta-Point network topologies.
o
Collision detection circuitry with the following
features:
• Detects miSSing mid-bit transitions
• Transitions too close together
• Transitions too far apart
• External collision input pin
• Carrier dropout
• Watchdog timer
• AT&T Release 1 collision presence signal
• Echo timeout
o Optional end-of-frame detection.
• Input protection at end-of-frame
o
o
Loopback capability.
Receive carrier automatically converted to a level
signal.
o Optional
Watchdog timer to prevent continuous
transmission.
o
Optional Echo timer to signal error if transmitted
frame is not received.
o
Optional Heartbeat generation.
o
In 82586182588 mode, insensitive to extra bits ahead
of preamble.
'Crystal Inputs have CMOS thresholds.
1·293
CMODEO
1
28
XSEL1
2
27
VCC
XD
LBACK
3
26
iEN
RD
4
25 TX
RC
5
24 TCLK
XSELO
6
23
ETDEN
CMODE1
7
22
HBEN
AIEN
ETEN
8
21
WDTEN
9
20
DMANEN
RENA
10
19
TENA
CLSN
11
18
X1
RCLK
12
17
X2
RX
13
16
ECLSN
GND
14
15
REsET
Figure 1. MK5033 Pin Assignment
o
Digital phase-locked loop.
o On chip crystal oscillator, 16, 10, 8, or 6X operation.
o CMOS technology.
o 28-pin DIP.
o Single 5-volt supply.
o All inputs and outputs TTL compatible.'
o Outputs are also CMOS compatible.
o
Industrial version available.
GENERAL DESCRIPTION
The MK5033 is a general purpose Manchester Encoder/Decoder. It incorporates several features that
make it an ideal StarLAN station Chip. The MK5033 performs three functions. It encodes data from a controller
chip into Manchester or Differential data. It decodes
Manchester or Differential Manchester data from the
line transceiver and produces NRZ data and clock for
the controller chip. It also detects collision and Signals
the controller chip that a collision has occurred.
Xl
-I
OSCILLATOR
=1
X2
TCLK·.
CLOCK DIVIDER
t
XSEL1, XSELO
XD
XEN
TENA
TRANSMIT
ENCODER
TX
WATCHDOG
TIMER
WDTEN
i
ECHO
TIMER
CMODEO
CMODEl
HOST
MODE
SELECTION
DMANEN
EcLsN
•
ETEN
ETDEN
1
COLLISION
DETECTION
~
HBEN
I
L~
~
0
RD
RC
LBACK
1
--
1--.
l'
RECEIVE
CARRIER
SQUELCH
VCC
..
GND
..
DIGITAL
PHASE
LOCKED
LOOP
MANCHESTER
DECODER
t
r--
,
Figure 2. Manchester Encoder/Decoder Block Diagram
1-294
~
~
~
AIEN
convert a pulse signal to a level
signal.
PIN DESCRIPTIONS:
CONTROLLER
INTERFACE
Input
RX
Output
RX is the serial receive data after decoding.
RENA
Output
This signal indicates that data is
available to the controller on the
RX output.
External collision input. When
this pin is held low for at least 20
nS an external collision is
signaled.
MISCELLANEOUS
CMODE1,
CMODEO
These two mode bits allow the
chip to be used with a variety of
controller chips.
RCLK
Output
This is the receive data clock
recovered from incoming data on
the RD pin.
TX
Input
This is the serial data to be transmitted. It is clocked into the chip
by TCLK.
TENA
Input
This signal indicates that data is
valid on the TX input. It goes active with the first bit of transmission.
Receive data (RX) transitions on the rising
edge of RCLK.
TENA - active low
RENA - active low - goes active when
phase locked loop is locked
CLSN - active low
TCLK
Output
This is the transmit data clock. All
transmit interface signals are synchronized to this clock. This clock
is always active.
CLSN
Output
This signal is asserted when a
Manchester violation is detected
on the RD line or when the external collision input (ECLSN) goes
active. It is also asserted if either
of the timers expire. It is deasserted when line idle is detected on
the RD line and TENA goes inactive.
TRANSCEIVER
XD
RD
Inputs
CMODE1 = 1, CMODEO = 0 (10)
(See Note)
82586/82588
Transmit data (TX) is sampled on the rising edge of TCLK.
CMODE1
1 CMODEO =
LANCE MK68590
=
1 (11)
MOSTEK
Transmit data (TX) is sampled on the failing edge of TCLK.
Receive data (RX) transitions on the failing edge of RCLK.
TENA - active high
RENA - active high - goes active when
receive carrier goes active
CLSN - active high
INTERFACE
Output
Transmit data output.
Output
Transmit output enable. This signal goes low to Signal XD active.
It goes high at the end of transmission. NOTE: If ETDEN is active XD will remain high for 2-bit
times at the end of a frame and
XEN will remain low during this
time.
Input
Receive data input.
Input
Receive carrier input. Receive
carrier can be either a pulse
stream or an active low signal to
indicate carrier active. The chip
contains internal squelch circuitry, as shown in Figure 3, to
1-295
CMODE1 = 0 CMODEO = 0 (00)
TEST Mode
This mode is only useful for production
testing.
NOTE: Compatibility with controller chips based on preliminary controller data
sheets.
CMODE1 = 0 CMODEO = 1 (01) Mostek
Variable Bit Rate LANCE MK5032 (See note)
TENA - active high
RENA - active high - goes active when
receive carrier goes active
CLSN - active high
DMANEN
HBEN
ETDEN
AI EN
Input
Input
Input
Input
in reset mode. All interface signals will be inhibited except
TCLK. RESET must remain active for at least three TCLK periods.
XSELO,
XSEL1
Inputs
When this pin is low the chip encodes and decodes serial data
using Differential Manchester.
When this pin is high it uses Manchester.
When this pin is high the chip will
signal CLSN after TENA is deasserted at the end of transmission.
CLSN remains active until link
idle is received on RD.
When this pin is high the chip will
recognize end-of-frame as specified in the StarLAN specification.
It will also ignore incoming data
on RD for 20 data bits after the
end of a received frame.
Input
When ETEN is high the echo
timer is activated. The echo timer
starts at the beginning of a transmitted frame. If a receive carrier
is not received with 510 TCLKS,
then collision will be asserted.
WDTEN
Input
When WDTEN is high the watchdog timer is activated. The timer
starts when TENA is asserted. If
TENA goes inactive before the
timer expires, the timer is reset.
If the timer expires, transmission
is aborted and collision asserted.
Input
When this pin is low the chip will
be put into internalloopback. The
transmit data will be internally
looped back into the input RD.
The outputs XD and XEN will be
held idle during loopback.
Input
When this pin is low the chip is
x
X
S
S
E
L
1
E
o
o
1
1
CLOCK
DIVISOR
L
o
o
16 X
1
ax
1
10 X
6X
o
X1, X2
Inputs
Crystal oscillator inputs. A crystal
can be connected between these
inputs, or a CMOS level square
wave can be connected to XI
while X2 is left unconnected.
VCC
Input
+5V
Auto Inversion Enable. If both
frame recognition is enabled and
Manchester is selected, then if
AIEN is high the frame polarity is
sensed and corrected if necessary. If AIEN is low, ETDEN is low,
or DMANEN is low, then auto
compensation for line reversal is
disabled.
ETEN
These inputs select which frequency clock or crystal is to be
connected to X1 and X2.
1·296
± 5%
GND
NOTE: Compatibility with controller chips based on preliminary controller data
sheets.
TI II ---..--
' > - - - - - - - - - - - - - - - 1 RD
-----+-----i
MK5033
JLo-------I
Vr ----------------~
RC
EXTERNAL SQUELCH
>-----;RD
MK5033
>-----fRC
INTERNAL SQUELCH
Figure 3. Internal Versus External Squelch
1-297
CIRCUIT DESCRIPTION
(RCLK) from the data. The NRZ data is output to the
controller on pin RX.
TRANSMITTER
RECEIVE CARRIER SQUELCH
The transmitter encodes NRZ data from the controller
chip into Manchester or Differential Manchester Space
data. The diagram below shows the two encoding
schemes.
The Receive carrier pin has internal squelch logic that
allows the signal to be either a level signal or a pulse
train. Receive carrier is active low. The receive carrier
I
J
I
I
I
I
I
I
CLOCK
NRZ
I
I
MAN.
~_--l1LJ
L ____
I
I
Lll'---:---__
....J
OMAN.
Data encoding and transmission begin when the controller chip brings TENA active. The start of data encoding is delayed by two bits when in 82586/82588
mode. TX data is sampled using TCLK as the clock.
Data is encoded into Manchester or Differential Manchester Space, as shown above, depending upon the
state of DMANEN. The encoded data is output on
XD. XEN goes low with the first bit of data output on
XD. The transmit delay, delay from TENA active to XEN
active, is less than 2 TCLKs in LANCE modes (4 TCLKS
in 82586/82588 mode). The controller chip signals end
of data by bringing TENA inactive. The pin ETDEN controls how the MK5033 handles the end transmission.
must be present for 3 clock samples to be considered
a valid carrier. Once the carrier is considered valid then
it must be active for only one ciock sample time every
two bit times to remain valid. (See Figure 3.)
If ETDEN is high the MK5033 will add a delimiter to the
data stream after the last bit is transmitted. In Manchester mode XD will be held high for 1.5 TCLKs if the
last data bit is a one and for 2 TCLKs if the last data
bit is a zero. During this time XEN is held active. In
Differential Manchester, XD is toggled after the last data
bit and held in that state for 2 TCLKs. XEN is active
during this time. After the delimiter has been sent, XEN
is brought inactive.
The digital phase locked loop is implemented with a
counter that clears on each transition of the receive
data. The phase locked loop will declare "lock" after
receiving data that has two "long transitions". A long
transition occurs when the receive data does not
change for at least 4/6 of a bit time in 6X mode (5/8 in
BX, 7/10 in 10X, and 11/16 in 16X). The phase locked loop
generates a clock frequency that is 2 times the data rate.
If ETDEN is low the MK5033 will not add any delimiter
to the data stream. XEN will be brought inactive after the
last data bit has been output.
AUTOMATIC COMPENSATION FOR WIRING
REVERSAL
When loopback is enabled (LBACK low) RD and RC are
ignored. Transmit data is internally looped back as
receive data. The transmitter outputs XD and XEN are
disabled during loopback.
DIGITAL PHASE LOCKED LOOP (DPLL)
When installing twisted pair telephone wiring, it is often
difficult and expensive to maintain proper polarity on
the wire pairs. The MK5033 will automatically compensate for this reversal. If Manchester coding is selected
with both ETDEN = 1 and AI EN = 1 then any frame
that is received with inverse polarity will be detected
and correct polarity established prior to data decoding.
RECEIVER
The receiver consists of four major sections:
1)
2)
3)
4)
LOOPBACK
Receive carrier squelch
Internal loop back
Digital phase locked loop
Manchester/Differential Manchester decoder
MANCHESTER/DIFFERENTIAL MANCHESTER
DECODER
Depending on the state of DMANEN, the receiver decodes Manchester or Differential Manchester space
data from pin RD into NRZ form. It also extracts timing
1-298
The receive data (after inversion if enabled) is fed into
the decoder along with the recovered 2x clock from the
DPLL. The decoder changes the receive data to NRZ
data. The NRZ data is output on RX. RENA signals the
controller chip that data is available. (See mode pin
descriptions.) RCLK is a 1x clock output that is synchronous with the data on RX.
8) Heartbeat
Heartbeat is enabled when HBEN is high. If it is enabled, then collision will be signaled 8 TCLKs after
TENA goes away, and collision will remain active for
at least 8 TCLKs.
PROTECTION TIME
Once CLSN is activated it remains active until both
TENA and RENA go inactive. The exception to this is
heartbeat. If heartbeat signals collision, then collision
is guaranteed to remain for 8 TCLKs or until TENA or
RENA go inactive, whichever is longer.
After the end of a received frame the receiver is disabled for 20 bit times. This protection time guarantees
immunity to spikes caused by transformer coupling after the end of frame.
WATCHDOG TIMER
COLLISION
CLSN is an output to the controller chip that indicates
a possible problem with the data. There are several
sources of collision.
1) Transitions too close together
Collision is signaled if the receive data stream transitions a second time in less than 2/6 bit times in 6X
mode (3/8 in 8X, 3110 in 10X, and 5/16 in 16X)
When enabled, the watchdog timer ensures that the
MK5033 will not transmit for more than 101K bit times.
The timer is enabled by bringing WDTEN high and disabled by bringing WDTEN low. If WDTEN is high, the
timer is activated when TENA goes active. The timer
resets when TENA goes inactive. If TENA remains active for more than 101K bit times, then the timer will time
out causing collision to be asserted and XEN to go
inactive. If loopback is enabled, watchdog timeout will
occur after 325 bit times. This permits run time testing
of the watchdog timer.
ECHO TIMER
2) Transitions too far apart
Collision is signaled if the receive data stream does
not transition again within 9/6 in 6X mode (10/8 in 8X,
12/10 in 10X, and 20/16 in 16X).
3) Manchester violation
If the data violates Manchester or Differential Manchester coding rules, depending on DMANEN, then
collision is signaled.
4) Watchdog timer
If the watchdog timer expires, then collision will be
signaled, if WDTEN is high.
5) Echo timer
If the echo timer expires, then collision will be signaled, if ETEN is high.
6) External collision
If the external collision pin (ECLSN) goes low for at
least 20ns, then collision will be signaled.
When the echo timer is enabled the MK5033 expects
the data that it is transmitting to be received on RD within 510 bit times. The echo timer is activated when
TENA goes active. If 510 bit times elapse before RENA
goes active, then the timer will time out causing collision to be activated.
Oscillator
The MK5033 will accept two forms of clock input: a
CMOS input or a crystal. If pin X2 is left unconnected,
a 6.0/8.0/10.0/16.0 MHz ± 0.01% CMOS clock may be
applied to pin X1. Alternately, a crystal circuit may be
connected between X1 and X2 to form the basis of an
oscillator. Typically, a 6.0/8.0/10.0/16.0 ± 0.005% parallel
resonant crystal is needed to insure the ±0.01 % frequency accuracy required for StarLAN. Refer to Figure
4. A fundamental mode, parallel resonance type crystal should be used with the manufacturer's suggested
load capacitance.
Reset Input
7) Receive carrier lost during transmission
If the MK5033 is transmitting and the receive carrier
goes active and then inactive before it is through
transmitting, then collision is signaled.
1-299
The reset pin is an active low Schmidt trigger input. A
simple RC network may be used to insure correct operation upon power-up. Refer to Fig. 5.
47pl
CMOS
Xl
Xl
LEVEL
CLOCK
6.0MHz
±.OO5%
NO
CONNECTION
0
X2
X2
47pl
B) CRYSTAL OPERATION
A) EXTERNAL CLOCK
Figure 4. Oscillator Operation
vee
10K!)
RESET
Figure 5. 1\tpical RC Connection For Power-On Reset
1-300
ELECTRICAL SPECIFICATIONS
This chapter provides tabular presentations for Absolute Maximum Ratings, DC Characteristics, Capacitance and
AC Timing Specifications. In addition, illustrations are provided for an Output Load Diagram (Figure 9) and Station
Timing Diagrams.
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ....................................................... -25°C to +100°C
Storage Temperature .......................................................... -65°C to +150°C
Voltage on Any Pin with Respect to Ground .................................... -0.5 V to Vee +0.5 V
Power Dissipation (no load) ............................................................... 50mW
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other condition above those Indicated in the operational sections of the specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
TA = O°C to 70°C, Vee = +5 V ±5% unless otherwise specified.
SYMBOL
CONDITIONS
VIL
MIN
MAX
UNITS
-0.5
+0.8
V
V IH
Except X1
+2.0
Vee +0.5
V
V IH
X1
+3.5
Vee +0.5
V
VOL
@ IOL
+0.5
V
VOH
@ IOH
VOH
@ IOH
IlL
@ VIN
CMODE1, ETEN
WDTEN, DMANEN, AIEN, HBEN, ETDEN
IlL
@ VIN == 0.4 to Vee, XSELO, CMODE1, ETEN
WDTEN, DMANEN, AIEN, HBEN, ETDEN
= 3.2 mA, except X2
= -0.4 mA, except X2
= -40"Po, except X2
= 0.4 to Vee, except XSELO,
V
+2.4
V
+3.2
±10
"Po
±100
"Po
8
mA
MAX
UNITS
CIN
10
pf
COUT
10
pf
CIO
20
pf
lee
CAPACITANCE
F = 1 MHz
SYMBOL
CONDITIONS
MIN
AC TIMING SPECIFICATIONS
TA = OOC to 70OC, Vee = +5 V ±5% unless otherwise specified, VTH
#
SIGNAL SYMBOL PARAMETER
1
X1
Txn
=
2.0 V, VTL
=
MIN
ns
X1 period
62
0.8 V.
TYP
ns
MAX
ns
2
X1
TX1L
X1 low time
24
3
X1
TX1H
X1 high time
24
4
X1
TX1R
Rise time of X1
0
8
5
X1
TX1F
Fall time of X1
0
8
1-301
AC TIMING SPECIFICATIONS (cont.)
TA = O°C to 70°C, VCC = +5 V ±5% unless otherwise specified, VTH = 2.0 V, V TL = 0.8 V.
#
SIGNAL SYMBOL PARAMETER
6
XEN
TXEN
7
XD
TXD
8
XD
J XD
Transmit jitter I T XD t-TXD~
9
TCLK
MIN
ns
TYP
ns
MAX
ns
XEN delay from Xl
40
65
XD delay from X1
40
65
4
6
I +2
TCLK
TCLK delay from Xl
10 TX
TTXST1
TX setup to falling edge of TCLK, CMODE = 1
90
11
TX
70
TTXHT1
TX hold from falling edge of TCLK, CMODE = 1
15
12 TX
TTXS
TX setup to X1
15
13 TX
TTXH
TX hold from X1
15
14 TENA
TTNAST1
TENA setup to falling edge of TCLK, CMODE = 1
90
15 TENA
T TNAST1
TENA hold from falling edge of TCLK, CMODE = 1
15
16 TENA
TTENAS
TENA setup to X1
15
17 TENA
TTENAH
TENA hold from Xl
15
18 TX
TTXSTO
TX setup to rising edge of TCLK, CMODE = 0
90
19 TX
TTXHTO
TX hold from rising edge of TCLK, CMODE = 0
15
20 TX
TTXS
TX setup to X1, CMODE = 0
15
TX
TTXH
TX hold from X1, CMODE = 0
15
22 TENA
21
TTNASTO
TENA setup to positive edge of TCLK, CMODE = 0
90
23 TENA
TTNAHTO
TENA hold from positive edge of TCLK, CMODE = 0
15
15
15
24 TENA
TTNAS
TENA setup to X1, CMODE = 0
25 TENA
TTNAH
TENA hold from X1, CMODE = 0
26 CLSN
T CLSN
CLSN delay from Xl
27 ECLSN
TECLSN
Minimum detected pulse width
28 RC
T RCS
RC setup to X1
29 RC
T RCH
RC hold from X1
15
30 RD
T RDS
RD setup to X1
15
RD
TRDH
RD hold from Xl
15
32 RD
J RD6
RD Incoming Jitter Tolerance,
6X mode, X1 = 6 MHz, Tx1T-1 TRDS t-T RDSt
I
RD Incoming Jitter Tolerance,
8X mode, Xl = 8 MHz, T x1T-1 T RDS t-T RDSt
I
31
33 RD
34 RD
J RDB
70
20
165
161
123
119
198
194
186
182
15
J RD10
RD Incoming Jitter Tolerance,
10X mode, X1 = 10 MHz, TX1T -1 TRDSt-TRDSt
I
J RD16
RD Incoming Jitter Tolerance,
16X mode, X1 = 16 MHz, T X1T -1 TRDSt-TRDS~
I
36 RCLK
T RCLK
RCLK delay from Xl, CMODE = 1
37 RX
TRXRCK1
RX delay from falling RCLK, CMODE = 1
38 RX
T RX
RX delay from Xl, CMODE = 1
35 RD
5
1-302
40
-30
65
30
40
65
AC TIMING SPECIFICATIONS (cont.)
TA =
#
O'C to 70'C,
+5
V
±5% unless otherwise specified,
V TH =
2.0
40 RENA
CLSN
T RNARCKl
RENA delay from falling RCLK, CMODE = 1
TRENA
RENA delay from X1, CMODE = 1
TCSNRCKl
CLSN delay from falling edge RCLK, CMODE = 1
T CLSN
CLSN delay from X1, CMODE = 1
43 RCLK
T RCLKO
RCLK delay from X1, CMODE = 0
44 RCLK
P RCLK
RCLK pulse width, CMODE = 0
45 RCLK
42 CLSN
0.8 V.
V, V TL =
SIGNAL SYMBOL PARAMETER
39 RENA
41
VCC =
MIN
TYP
MAX
ns
ns
ns
-30
-30
70
TX1T
-20
TX1T
-20
T RXCLK
RCLK delay from RX stable, CMODE = 0
TCLKRX
RX hold from falling edge of RCLK, CMODE = 0
47 RCLK
TRNACLK
RCLK delay from RENA stable, CMODE = 0
48 RENA
TCLKRNA
RENA hold from falling edge of RCLK, CMODE = 0
2 * T X1T -20
49 RCLK
TCSNCLK
Rising RCLK delay from CLSN stable, CMODE = 0
2 * T X1T -20
TCLKCSN
CLSN delay from rising edge of RCLK, CMODE ,= 0
1-303
65
30
40
46 RX
50 CLSN
30
45
2 * T X1T -20
TX1T
TX1T
-20
-20
65
T X1T +20
Xl_.J;, ~_5
2_~_
Xl
Figure 8. External X1 Timing Diagram
XD
TCLK
TX
I
CMODE = 1
(LANCE· 68590)
TENA
TX
XXX
XXX
!
~*l' L
CMODE
(82586)
--I
I
TENA
/
_ _ _...J
I
23
XXX
XXX
1~51~
26rCLSN
22
--I 1-
\~-
27
ECLSN
----------~~
'-----II~---------
Figura 7. li'ansmlt Timing Diagram
1·304
=0
RD
RCLK
XXXX
~
XXXX
36
---------'
t
------r=
137
RX
___I
~38t=
RENA
i1;
---1
CLSN
RCLK
RX
RENA
CMODE = 1
(LANCE·
68590)
39
~ I-
!1'E
~"=!~f43
~45~""":1---44-4-6~
xxxxxxx1-47--1"
XXXXXXX
48
_I
XXXXX>
-,
XXXXX>
"""1·f-----49------:·I~·-50__l
CLSN
XXXXXXX
XXXXX>
Figure 8. Receiver Timing Diagram
1-305
CMODE = 0
TEST
POINT
R,
~
1.2K
CR,
FRO~N~'E~ ~~~~UTS
o-----.....- - - -.....-~-_k'" 1---"
O.4mA
I
CL
~
50pF MIN @ 1 MHz
CR,.CR.
~
lN914 OR
EQUIVALENT
Figure 9. Output Load Diagram
1-306
PACKAGE DESC~IPT~N
Plast I'e Dual-In-Lme ( )
28-Pin
MK5033N
.100
NOM.
I--I
13 EQUAL SPACES@ .100 _ _ _
1-307
.090
NOM.
1-308
MI{5035N
-----,~-
StarLAN ENCODER DECODER
COMMUNICATIONS PRODUCTS
FEATURES
o
Conforms with StarLAN specification.
o
Supports multi-point extension.
o
Auto compensation for line reversal.
o Compatible with Mostek MK68590 LANCE and Intel 82586/82588.
o
Close pin compatibility with SEEQ8023.
o
Data rates to 2.66Mbps supported.
o
Manchester data encoding/decoding.
o
Collision detection circuitry with the following
features:
• Detects missing mid-bit transitions
• Transitions too close together
• Transitions too far apart
• External collision input pin
• Carrier dropout
• Watchdog timer
• AT&T Release 1 collision presence signal
• Echo timeout
P 20
P 19
•
CMODE
1L
XSEL
2L
LBACK
3L
M
RD
4L
K
RC
5L
5
RENA
6L
0
CLSN
7L
3
RCLK
BL
5
RX
9L
GND 10 L
o
Receive end-of-frame detection.
• Input protection at end-of-frame
o
Loopback capability.
o
Receive carrier automatically converted to a level
signal.
o
Echo timer to signal error if transmitted frame is not
received.
o
Heartbeat generation.
o
In 82586 mode, insensitive to extra bits ahead of
preamble
o
Digital phase-locked loop.
P lB
P17
P 16
P 15
P 14
P 13
P 12
P 11
VCC
XD
XEN
TX
TCLK
TENA
Xl
X2
ECLSN
RESET
Figure 1. MK5035 Pin Assignment
o
o
CMOS technology.
o
Single 5-volt supply.
o
All inputs and outputs TTL compatible.'
o
Outputs are also CMOS compatible.
o
Industrial version available.
20-pin DIP.
GENERAL DESCRIPTION
The MK5035 is a Manchester Encoder/Decoder chip
incorporating several features that make it an ideal
StarLAN station chip. The MK5035 performs three functions. It encodes data from a controller chip into Manchester data. It decodes Manchester data from the line
transceiver and produces NRZ data and ciock for the
controller chip. It also detects collisions and signals the
controller chip that a collision has occurred.
The MK5035 has several enhancements for StarLAN
and Multi-Point extension (MPE) StarLAN. These include auto compensation for wiring reversal, echo timer,
external collision detect, watchdog timer, and heartbeat,
among others.
o On chip crystal oscillator, 8X or 6X operation.
*Crystal inputs have CMOS thresholds.
1-309
PIN DESCRIPTIONS:
OTHER PINS
CONTROLLER
CMODE
RX
INTERFACE
Output
RX is the serial receive data after
decoding.
RENA
Output This signal indicates that data is
available to the controller on the
RX output.
RCLK
Output
Input
CMODE = 0,
Transmit data (TX) is sampled on
the rising edge of TCLK.
Receive data (RX) transitions on
the rising edge of RCLK.
RCLK is the receive data clock
recovered from the incoming data
RD.
TX
Input
TX is the serial data to be transmitted. It is clocked into the chip
by TCLK.
TENA
Input
This signal indicates that data is
valid on the TX input. It goes active with the first bit of transmission.
TENA - active low
RENA - active low - goes
active when phase lock
loop is locked.
CLSN - active low
CMODE = 1,
TCLK
CLSN
Transmit data (TX) is sampled on
the falling edge of TCLK.
Receive data (RX) transitions on
the falling edge of RCLK.
TENA - active high
RENA - active high - goes active
when phase lock loop is
locked.
CLSN - active high
Output This signal is asserted when a
manchester violation is detected
on the RD line or when the external collision input (ECLSN) goes
active.
Output
When this input is low the part will
be put into internalloopback. The
transmit data will be internally
looped back as receive data. See
Figure 2. The outputs XD and
XEN will be held inactive during
loopback.
Input
When this pin is low the chip is in
reset mode. All interface signals
will be inhibited except TCLK.
RESET should remain active for
three TCLK periods.
Input
This input selects the clock
divider.
Encoded transmit data output.
Input
Encoded receive data input.
Input
Receive carrier input. Receive
carrier can be either a pulse
stream or an active low signal to
indicate carrier active. The chip
contains internal squelch circuitry,
as shown in Figure 3, to convert
a pulse signal to a level signal.
Input
Input
INTERFACE
Output Transmit output enable. This signal goes low to indicate XD active.
It goes high at the end of transmission.
RD
MOSTEK LANCE MK68590
Output TCLK is the transmit data clock.
All transmit interface signals are
synchronized to this clock.
TRANSCEIVER
XD
This input allows the part to be
used with either Mostek or Intel
controllers:
82586/82588 (See Note)
XSEL
If XSEL = 0, it is 8X.
If XSEL = 1, it is ex.
External collision input. When this
pin is held low for at least 20 nS,
an external collision is signaled.
NOTE: Compatibility with controller chips based on preliminary controller data
sheets.
1-310
Inputs
X1,X2
Crystal oscillator inputs. A crystal
can be connected between these
inputs, or a CMOS level square
wave can be connected to X1
while X2 is left unconnected.
•
•
X1
X2
VCC
Input
+5V ± 5%
GND
OSCILLATOR
t
TIMER
TX
CMODE
--
-
~
i
RC
vce
GND
XEN
TRANSMIT ENCODER
XD
+
ECHO
TIMER
HOST MODE
SELECTION
~
+
~
L~
RD
XSEL
..
.
..
WATCHDOG
TENA
TCLK
CLOCK DIVIDER
COLLISION
DETECTION
t
~
DIGITAL
PHASE
LOCK
LOOP
r-----
L--.
MANCHESTER
DECODER
RECEIVE
CARRIER
SQUELCH
~ CLSN
f---+
Figure 2. StarLAN Encoder Decoder. MK5035
1·311
RX
~ RENA
-
RCLK
~---------------------------4RD
MK5035
J L 0 - - - - - - - - - 1 RC
VT ----------------~
EXTERNAL SQUELCH
>----------f RD
MK5035
:>------IRC
INTERNAL SQUELCH
Figure 3. Intornal Versus External Time Squelch
1-312
CIRCUIT DESCRIPTION
TRANSMITTER
difficult and expensive to maintain proper polarity on
the wire pairs. The MK5035 will automatically compensate for this reversal. Any frame that is received with
inverse polarity will be detected and decoded with the
correct polarity.
The transmitter encodes NRZ data from the controller
chip into the Manchester data. The diagram below
shows the two encoding schemes.
CLOCK
NRZ
~
I
I
MAN.
ILJ
L - - -_ _
Data encoding and transmission begin when the controller chip brings TENA active. The start of data encoding is delayed by two bits when in 82586/82588
mode. TX is sampled using TCLK as the clock. The encoded data is output on XD. XEN goes low with the first
bit of data output on XD. The transmit delay, delay from
TENA active to XEN active, is less than 2 TCLKs in
LANCE mode (4 TCLKs in 82586/82588 mode). The
controller chip signals end of data by bringing TENA
inactive.
XD will be held high for an additional 1.5 TCLKs if the
last data bit is a one, and for 2 TCLKs if the last data
bit is a zero. During this time XEN is held active.
I
LlI,--------,1
LOOPBACK
When loop back is enabled (LBACK low), RD and RC
are ignored. Transmit data is internally looped back as
receive data. The transmitter outputs XD and XEN are
disabled during loopback.
DIGITAL PHASE LOCKED LOOP (DPLL)
The digital phase locked loop is implemented with a
counter that clears on each transition of the receive
data. The phase locked loop will declare "lock" after
receiving data that has two "long transitions". A long
transition occurs when the receive data does not
change for at least 4/6 (5/8 in 8X mode) of a bit time.
RECEIVER
MANCHESTER DECODER
The receiver consists of four major sections.
1)
2)
3)
4)
Receive carrier squelch
Internal loopback
Digital phase locked loop
Manchester decoder
The receiver takes Manchester data in on RD, when
receive carrier (RC) is active, and decodes the data
into NRZ data and also produces clock (RCLK) from
the data. The NRZ data is output to the controller on RX.
RECEIVE CARRIER SQUELCH
The Receive carrier pin has internal squelch logic that
allows the signal to be either a level signal or a pulse
train. Receive carrier is active low. The receive carrier
must be present for 3 clock samples to be considered
a valid carrier. Once the carrier is considered valid then
it must be active for only one clock sample time every
two bit times to remain valid. (See Figure 3.)
The receive data (after inversion if needed) is fed into
the decoder along with the recovered 2X clock from the
DPLL. The decoder changes the receive data to NRZ
data. The NRZ data is output on RX. RENA signals the
controller chip that data is available. (See mode pin
descriptions.) RCLK is a 1X clock output that is synchronous with the data on RX.
PROTECTION TIME
After the end of a received frame the receiver is disabled for 20 bit times. This protection time guarantees
immunity to spikes caused by transformer coupling after the end of frame.
COLLISION
CLSN is an output to the controller chip that indicates
a possible problem with the data. There are several
sources of collision.
Automatic Compensation For Wiring Reversal
When installing twisted pair telephone wiring, it is often
1) Transitions too close together
Collision is signaled if the receive data stream tran-
1-313
sitions a second time in less than 216 (3/8 in 8X mode)
bit times.
2) Transitions too far apart
Collision is signaled if the receive data stream does
not transition again within 916 (10/8 in 8X mode) bit
times.
3) Manchester violation
If the data violates Manchester coding rules, then collision is signaled.
WATCHDOG TIMER
The watchdog timer ensures that the MK5035 will not
transmit for more than 101K bit times. The timer is started when TENA goes active. The timer resets when
TENA goes inactive. If TENA remains active for more
than 101K bit times, then the timer will time-out causing collision to be asserted and XEN to go inactive. If
loopback is enabled, watchdog timeout will occur after
325 bit times. This particular timer value allow StarLAN
HUBs to activate their own jabber functions, thereby
alerting net management.
A Manchester violation is a missing mid-bit transition.
ECHO TIMER
4) Watchdog timer
If the watchdog timer expires, then collision will be
signaled.
5) Echo timer
If the echo timer expires without receive carrier going active, then collision will be signaled.
6) External collision
If the external collision pin (ECLSN) goes low for
at least 20n8, then collision will be signaled.
7) Receive carrier lost during transmission
If the MK5035 is transmitting and the receive carrier
goes active and then inactive before it is through
transmitting, then collision is signaled.
8) Heartbeat
Collision, as a result of heartbeat, will be signaled
8 TCLKs after TENA goes away, and collision will remain active for at least 8 TCLKs.
The MK5035 expects the data that it is transmitting to
be received on RC/RD within 510 bit times. The echo
timer is activated when TENA goes active. If 510 bit
times elapse before RENA goes active, then the timer
will time out causing collision to be activated.
Oscillator
The MK5035 will accept two forms of clock input: a
CMOS input or a crystal. If pin X2 is left unconnected,
a 6.0/8.0 MHz ± 0.01% CMOS clock may be applied
to pin Xl. Alternately, a crystal circuit may be connected between Xl and X2 to form the basis of an oscillator. Typically, a 6.0/8.0 ± 0.005% parallel resonant crystal
is needed to insure the ± 0.01% frequency accuracy
required for StarLAN. Refer to Figure 4. A fundamental mode, parallel resonance type crystal should be used
with the manufacturer's suggested load capacitance.
Reset Input
Once CLSN is activated it remains active until both
TENA and RENA go inactive. The exception to this is
heartbeat. If heartbeat signals collision, then collision
is guaranteed to remain for 8 TCLKs.
The reset pin is an active low Schmidt trigger input. A
simple RC network may be used to insure correct operation upon power-up. Refer to Fig. 5.
1-314
47pf
CMOS
Xl
Xl
LEVEL
CLOCK
6.0MHz
±.OO5%
NO
CONNECTION
D
X2
X2
-
47pf
B) CRYSTAL OPERATION
A) EXTERNAL CLOCK
Figure 4. Oscillator Operation
VCC
10KO
RESET
Figure 5. Typical RC Connection For Power-On Reset
1-315
ELECTRICAL SPECIFICATIONS
This chapter provides tabular presentations for Absolute Maximum Ratings, DC Characteristics, Capacitance and
AC Timing Specifications. In addition, illustrations are provided for an Output Load Diagram (Figure 9) and Station
Timing Diagrams.
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ....................................................... -25°C to +100°C
Storage Temperature .......................................................... -65°C to +150°C
Voltage on Any Pin with Respect to Ground .................................... -0.5 V to Vee +0.5 V
Power Dissipation (no load) ............................................................... 50mW
Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other condition above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
TA = O°C to lO°C, Vee = +5 V ±5% unless otherwise specified.
SYMBOL
CONDITIONS
Except Xl
V IH
VOL
@ IOL
MIN
MAX
UNITS
-0.5
+0.8
V
+2.0
Vee +0.5
V
+3.5
Vee +0.5
V
+0.5
V
= 3.2 mA, except X2
----------------------------~--------+---------~------~
VOH
@
VOH
@ IOH = -40 pA, except X2
IOH = -0.4 mA, except X2
+2.4
V
+3.2
V
@ VIN = 0.4 to Vee
-pA
±10
8
mA
MAX
UNITS
CIN
10
pf
COUT
10
pf
CIO
20
pf
lee
CAPACITANCE
F = 1 MHz
SYMBOL
CONDITIONS
MIN
AC TIMING SPECIFICATIONS
TA = O°C to lO°C, Vee = +5 V ±5% unless otherwise specified, VTH = 2.0 V, VTL = 0.8 V.
#
SIGNAL SYMBOL PARAMETER
1
Xl
2
Xl
3
Xl
4
Xl
5
Xl
MIN
ns
TYP
ns
MAX
ns
TX1T
Xl period
62
TX1L
Xl low time
24
TX1H
Xl high time
24
TX1R
Rise time of Xl
0
8
TX1F
Fall time of Xl
0
8
1·316
AC TIMING SPECIFICATIONS (cont.)
TA = O°C to 70°C, Vcc = +5 V ±5% unless otherwise specified, VTH
#
=
2.0 V, VTL
SIGNAL SYMBOL PARAMETER
6
XEN
TXEN
XEN delay from X1
7
XD
TXD
XD delay from X1
8
XD
J XD
Transmit jitter \ T XD j-TXD~ \ +2
9
TCLK
=
MIN
TYP
MAX
ns
ns
ns
40
65
40
65
4
TCLK
TCLK delay from X1
10 TX
TTXST1
TX setup to falling edge of TCLK, CMODE
11
TTXHT1
TX hold from falling edge of TCLK, CMODE
15
12 TX
TTXS
TX setup to X1
15
13 TX
TTXH
TX hold from X1
14 TENA
TTNAST1
TENA setup to falling edge of TCLK, CMODE
90
15 TENA
TTNAST1
TENA hold from falling edge of TCLK,
15
16 TENA
TTENAS
TENA setup to X1
17 TENA
TTENAH
TENA hold from X1
18 TX
TTXSTO
TX setup to rising edge of TCLK, CMODE
90
19 TX
TTXHTO
TX hold from rising edge of TCLK,
15
20 TX
TTXS
TX setup to X1, CMODE
21
TX
TX
0.8 V.
6
70
=1
=1
90
15
=1
CMODE = 1
15
15
=0
CMODE = 0
=0
=0
15
TTXH
TX hold from X1, CMODE
15
22 TEN A
TTNASTO
TENA setup to positive edge of TCLK, CMODE
90
23 TENA
TTNAHTO
TENA hold from positive edge of TCLK,
15
24 TENA
TTNAS
TENA setup to X1, CMODE
15
25 TENA
TTNAH
TENA hold from X1,
15
26 CLSN
T CLSN
CLSN delay from X1
27 ECLSN
TECLSN
Minimum detected pulse width
28 RC
T RCS
RC setup to X1
15
29 RC
T RCH
RC hold from X1
15
30 RD
T RDS
RD setup to X1
15
TRDH
RD hold from X1
15
32 RD
=0
CMODE = 0
=0
CMODE = 0
70
5
20
J RD6
RD Incoming Jitter Tolerance,
6X mode, X1 = 6 MHz, Txn-\ TRDSj-TRDS~ \
165
161
33 RD
J RDe
RD Incoming Jitter Tolerance,
8X mode, X1 = 8 MHz, Txn-\ TRDSj-TRDS~ \
123
119
31
RD
=
34 RCLK
T RCLK
RCLK delay from X1, CMODE
35 RX
TRXRCK1
RX delay from falling RCLK, CMODE
36 RX
=
1
40
=
1
-30
40
T RX
RX delay from X1, CMODE
37 RENA
TRNARCK1
RENA delay from falling RCLK, CMODE
1
38 RENA
TRENA
RENA delay from X1, CMODE
39 CLSN
TCSNRCK1
CLSN delay from falling edge RCLK, CMODE
40 CLSN
T CLSN
CLSN delay from X1, CMODE
=
=
1·317
=
1
-30
1
1
1
-30
65
30
45
=
65
30
65
30
70
AC TIMING SPECIFICATIONS (cont.)
TA = O°C to 70°C, VCC = +5 V ±5% unless otherwise specified, VTH
#
SIGNAL SYMBOL PARAMETER
41
RCLK
=
2.0 V, VTL
T RCLKO
RCLK delay from Xl, CMODE
=
PRCLK
RCLK pulse width, CMODE
=
0
43 RCLK
TRXCLK
RCLK delay from RX stable, CMODE
44 RX
TCLKRX
RX hold from falling edge of RCLK, CMODE
45 RCLK
TRNACLK
RCLK delay from RENA stable, CMODE
46 RENA
TCLKRNP
47 RCLK
TCSNCL~
=0
Rising RCLK delay from CLSN stable, CMODE = 0
CLSN delay from rising edge of RCLK, CMODE = 0
TCLKCSN
0.8 V.
MIN
ns
42 RCLK
48 CLSN
=
0
40
TX1T -20
=
0
=
TX1T -20
=
0
0
RENA hold from falling edge of RCLK, CMODE
1·318
TYP
ns
2'Tx1T -20
TX1T -20
2'Tx1T -20
2'Tx1T -20
TX1T -20
MAX
ns
65
TX1T +20
Xl_.J- ,f_s
2_~_
Figure 6. External X1 Timing Diagram
CMODE = 1
(LANCE· 68590)
lENA
xxxxx
XXXXX
--116
17
I--
I
CMODE
(82586)
lENA
/
----
XXX
IEt625r-~
261-CLSN
XXX
_1 1_ "-27
ECLSN
----------~~
/~----------
"---../
Figure 7. Transmit Timing Diagram
1-319
=
0
CMODE = 1
(LANCE - 68590)
RX
xxxxxxx
XXXXX>
[--45-.,.1...- - - - 46
RENA
XXXXXXX
~I
XXXXX>
~---47·---_·""'1..-48__l
1-o
.
o.
1
CLSN
XXXX>
Figure 8. Receiver Timing Diagram
1-320
CMODE
=0
TEST
POINT
R,
~
1.2K
CR,
FROM ALL OUTPUTS
UNDER TEST
0 - - - - -.....----+----;( 1-_ _"
CL
O.4mA
I
~
50pF MIN @ 1 MHz
CR,.CR. ~ lN914 OR
EQUIVALENT
Figure 9. Output Load Diagram
1·321
PACKAGE DESCRIPTION
20 Pin Plastic
MK5035N
Ir::~j
L ,------{
l:f
-t
Ili
f-----------,------,
-I
.120
MIN •
.015
~I-I
MIN.
1-o1.t------"9
EQ~\S:OACES --:g-!-~-J
R
·OOB
..... --:012
L.350± .050j
~
NOTE: Overall length includes .010 flash on either end of package
1-322
260
·
~
MI(50351 N
----
--~~-----I!I
StarLAN ENCODER DECODER
COMMUNICATIONS PRODUCTS
FEATURES
D Conforms with StarLAN specification.
D Supports multi-point extension.
D Auto compensation for line reversal.
D Compatible with Mostek MK5032 Variable Bit Rate
LANCE and Intel 82586/82588.
D Close pin compatibility with SEEQ8023.
D Data rates to 2.66Mbps supported.
D Manchester data encoding/decoding.
P 20
P 19
•
CMODE
lL
XSEL
2L
LBACK
3L
M
::::J 18 XEN
RD
4L
K
::::J 17 TX
5L
5
::::J 16 TCLK
RENA
6L
0
::::J 15 TENA
CLSN
7L
3
::::J 14 Xl
RCLK
8L
5
::::J 13 X2
RX
9L
1
::::J 12 ECLSN
D Heartbeat generation.
D In 82586 mode, insensitive to extra bits ahead of
preamble
RESET
D CMOS technology.
::::J 20-pin DIP.
D Loopback capability.
D Echo timer to signal error if transmitted frame is not
received.
::::J 11
Figure 1. MK50351 Pin Assignment
D Receive end-of-frame detection.
• Input protection at end-of-frame
D Receive carrier automatically converted to a level
signal.
XD
RC
GND 10 L
D Collision detection circuitry with the following
features:
• Detects missing mid-bit transitions
• Transitions too close together
• Transitions too far apart
• External collision input pin
• Carrier dropout
• Watchdog timer
• AT&T Release 1 collision presence signal
• Echo timeout
VCC
o
Single 5-volt supply.
o
All inputs and outputs TTL compatible.*
o
Outputs are also CMOS compatible.
o
Industrial version available.
GENERAL DESCRIPTION
The MK50351 is a Manchester Encoder/Decoder chip
incorporating several features that make it an ideal
StarLAN station chip. The MK50351 performs three
functions. It encodes data from a controller chip into
Manchester data. It decodes Manchester data from the
line transceiver and produces NRZ data and clock for
the controller chip. It also detects collisions and signals
the controller chip that a collision has occurred.
D Digital phase-locked loop.
D On chip crystal oscillator, 8X or 10X operation.
*Crystal inputs have CMOS thresholds.
The MK50351 has several enhancements for StarLAN
and Multi-Point extension (MPE) StarLAN. These include auto compensation for wiring reversal, echo timer,
external collision detect, watchdog timer, and heartbeat,
among others.
1-323
PIN DESCRIPTIONS:
OTHER PINS
CONTROLLER
CMODE
RX
INTERFACE
Output
RX is the serial receive data after
decoding.
RENA
Output
This signal indicates that data is
available to the controller on the
RX output.
RCLK
Output
RCLK is the receive data clock
recovered from the incoming data
RD.
TX
Input
TX is the serial data to be transmitted. It is clocked into the chip
by TCLK.
TENA
Input
This signal indicates that data is
valid on the TX input. It goes active with the first bit of transmission.
TCLK
Output
TCLK is the transmit data clock.
All transmit interface signals are
synchronized to this clock.
CLSN
Output
This signal is asserted when a
manchester violation is detected
on the RD line or when the external collision input (ECLSN) goes
active.
TRANSCEIVER
Input
CMODE = 0,
This input allows the part to be
used with either Mostek or Intel
controllers:
82586/82588 (See Note)
Transmit data (TX) is sampled on
the rising edge of TCLK.
Receive data (RX) transitions on
the rising edge of RCLK.
TENA - active low
RENA - active low - goes
active when phase lock
loop is locked.
CLSN - active low
CMODE
MK5032
1,
MOSTEK Variable Bit Rate LANCE
TENA - active high
RENA - active high - goes active
when phase lock loop is
locked.
CLSN - active high
LBACK
Input
When this input is low the part will
be put into internalloopback. The
transmit data will be internally
looped back as receive data. See
Figure 2. The outputs XD and
XEN will be held inactive during
loopback.
RESET
Input
When this pin is low the chip is in
reset mode. All interface signals
will be inhibited except TCLK.
RESET should remain active for
three TCLK periods.
XSEL
Input
This input selects the clock
divider.
INTERFACE
XD
Output
Encoded transmit data output.
XEN
Output
Transmit output enable. This signal goes low to indicate XD active.
It goes high at the end of transmission.
RD
Input
Encoded receive data input.
RC
Input
Receive carrier input. Receive
carrier can be either a pulse
stream or an active low signal to
indicate carrier active. The chip
contains internal squelch circuitry,
as shown in Figure 3, to convert
a pulse signal to a level signal.
Input
External collision input. When this
pin is held low for at least 20 nS,
an external collision is signaled.
If XSEL = 0, it is 8X.
If XSEL = 1, it is 10X.
NOTE: Compatibility with controller chips based on preliminary controller data
sheets.
1-324
X1,X2
Inputs
Xl
..
Crystal oscillator inputs. A crystal
can be connected between these
inputs, or a CMOS level square
wave can be connected to X1
while X2 is left unconnected.
+5V ± 5%
Input
VCC
GND
OSCILLATOR
TCLK
CLOCK DIVIDER
X2
t
TIMER
~
!
t
XSEL
..
..
..
WATCHDOG
VCC
GND
TENA ~
TRANSMIT ENCODER
TX
------
XD
!
f
ECHO
TIMER
CMODE
-----+
HOST MODE
!
SELECTION
~
L~
RD
RC
+
COLLISION
CLSN
DETECTION
t
~
DIGITAL
PHASE
LOCK
LOOP
~
MANCHESTER
DECODER
-~
R){
RENA
RECEIVE
CARRIER
SQUELCH
r---+
~ RCLK
Figure 2. StarLAN Encoder Decoder. MK50351
1·325
TIII'----e-·~
~--------------------------4RD
MK50351
VT
-----------------1
JLo------IRC
EXTERNAL SQUELCH
>------IRD
MK50351
> - - - -.... RC
+
INTERNAL SQUELCH
Figure 3. Internal Versus External Time Squelch
1-326
CIRCUIT DESCRIPTION
TRANSMITTER
difficult and expensive to maintain proper polarity on
the wire pairs. The MK50351 will automatically compensate for this reversal. Any frame that is received with
inverse polarity will be detected and decoded with the
correct polarity.
The transmitter encodes NRZ data from the controller
chip into the Manchester data. The diagram below
shows the two encoding schemes.
CLOCK
NRZ
~
I
I
I
MAN.
I
'---_---IILJ
Data encoding and transmission begin when the controller chip brings TENA active. The start of data encoding is delayed by two bits when in 82586182588
mode. TX is sampled using TCLK as the clock. The encoded data is output on XD. XEN goes low with the first
bit of data output on XD. The transmit delay, delay from
TENA active to XEN active, is less than 2 TCLKs. The
controller chip signals end of data by bringing TENA
inactive.
LOOPBACK
When loopback is enabled (LBACK low), RD and RC
are ignored. Transmit data is internally looped back as
receive data. The transmitter outputs XD and XEN are
disabled during loopback.
DIGITAL PHASE LOCKED LOOP (DPLL)
RECEIVER
The digital phase locked loop is implemented with a
counter that clears on each transition of the receive
data. The phase locked loop will declare "lock" after
receiving data that has two "long transitions". A long
transition occurs when the receive data does not
change for at least 518 (7110 in lOX mode) of a bit time.
The receiver consists of four major sections.
MANCHESTER DECODER
1)
2)
3)
4)
The receive data (after inversion if needed) is fed into
the decoder along with the recovered 2X clock from the
DPLL. The decoder changes the receive data to NRZ
data. The NRZ data is output on RX. RENA signals the
controller chip that data is available. (See mode pin
descriptions.) RCLK is a lX clock output that is synchronous with the data on RX.
XD will be held high for an additional 1.5 TCLKs if the
last data bit is a one, and for 2 TCLKs if the last data
bit is a zero. During this time XEN is held active.
Receive carrier squelch
Internal loopback
Digital phase locked loop
Manchester decoder
The receiver takes Manchester data in on RD, when
receive carrier (RC) is active, and decodes the data
into NRZ data and also produces clock (RCLK) from
the data. The NRZ data is output to the controller on RX.
RECEIVE CARRIER SQUELCH
The Receive carrier pin has internal squelch logic that
allows the signal to be either a level signal or a pulse
train. Receive carrier is active low. The receive carrier
must be present for 3 clock samples to be considered
a valid carrier. Once the carrier is considered valid then
it must be active for only one clock sample time every
two bit times to remain valid. (See Figure 3.)
PROTECTION TIME
After the end of a received frame the receiver is disabled for 20 bit times. This protection time guarantees
immunity to spikes caused by transformer coupling after the end of frame.
COLLISION
CLSN is an output to the controller chip that indicates
a possible problem with the data. There are several
sources of collision.
Automatic Compensation For Wiring Reversal
When installing twisted pair telephone wiring, it is often
1) Transitions too close together
Collision is signaled if the receive data stream tran1-327
sitions a second time in less than 3/8 (3/10 in 10X
mode) bit times.
2) Transitions too far apart
Collision is signaled if the receive data stream does
not transition again within 10/8 (12/10 in 10X mode)
bit times.
3) Manchester violation
If the data violates Manchester coding rules, then collision is signaled.
WATCHDOG TIMER
The watchdog timer ensures that the MK50351 will not
transmit for more than 101K bit times. The timer is started when TENA goes active. The timer resets when
TENA goes inactive. If TENA remains active for more
than 101 K bit times, then the timer will time-out causing collision to be asserted and XEN to go inactive. If
loop back is enabled, watchdog timeout will occur after
325 bit times. This particular timer value allow StarLAN
HUBs to activate their own jabber functions, thereby
alerting net management.
A Manchester violation is a missing mid-bit transition.
ECHO TIMER
4) Watchdog timer
If the watchdog timer expires, then collision will be
signaled.
5) Echo timer
If the echo timer expires without receive carrier going active, then collision will be signaled.
The MK50351 expects the data that it is transmitting
to be received on RC/RD within 510 bit times. The echo
timer is activated when TENA goes active. If 510 bit
times elapse before RENA goes active, then the timer
will time out causing collision to be activated.
Oscillator
6) External collision
If the external collision pin (ECLSN) goes low for
at least 20ns, then collision will be signaled.
7) Receive carrier lost during transmission
If the MK50351 is transmitting and the ~eceive carrier goes active and then inactive before it is through
transmitting, then collision is signaled.
8) Heartbeat
Collision, as a result of heartbeat, will be signaled
8 TCLKs after TENA goes away, and collision will remain active for at least 8 TCLKs.
The MK50351 will accept two forms of clock input: a
CMOS input or a crystal. If pin X2 is left unconnected,
a 8.0/10.0 MHz ± 0.01% CMOS clock may be applied
to pin X1. Alternately, a crystal circuit may be connected between X1 and X2 to form the basis of an oscillator. Typically, a 8.0/10.0 ± 0.005% parallel resonant
crystal is needed to insure the ± 0.01% frequency accuracy required for StarLAN. Refer to Figure 4. A fundamental mode, parallel resonance type crystal should
be used with the manufacturer's suggested load
capacitance.
Reset Input
Once CLSN is activated it remains active until both
TENA and RENA go inactive. The exception to this is
heartbeat. If heartbeat signals collision, then collision
is guaranteed to remain for 8 TCLKs.
The reset pin is an active low Schmidt trigger input. A
simple RC network may be used to insure correct operation upon power-up. Refer to Fig. 5.
1-328
47pI
CMOS
Xl
Xl
LEVEL
CLOCK
NO
CONNECTION
10.0 MHz
±.005%
0
X2
X2
47pI
B) CRYSTAL OPERATION
A) EXTERNAL CLOCK
Figure 4. Oscillator Operation
VCC
10K!)
RESET
Figure 5. lYpical RC Connection For Power-On Reset
1-329
ELECTRICAL SPECIFICATIONS
This chapter provides tabular presentations for Absolute Maximum Ratings, DC Characteristics, Capacitance and
AC Timing Specifications. In addition, illustrations are provided for an Output Load Diagram (Figure 9) and Station
Timing Diagrams.
ABSOWTE MAXIMUM RATINGS
Temperature Under Bias ....................................................... -25°C to +100°C
Storage Temperature .......................................................... -65°C to +150°C
Voltage on Any Pin with Respect to Ground .................................... -0.5 V to Vee +0.5 V
Power Dissipation (no load) ............................................................... 50mW
Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other condition above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
TA = O°C to 70°C, Vee = +5 V ±5% unless otherwise specified.
CONDITIONS
MIN
VIH
Except Xi
V 1H
Xi
+3.5
VOL
@ IOL
VOH
@ IOH
VOH
@ IOH
SYMBOL
MAX
UNITS
-0.5
+0.8
V
+2.0
Vee +0.5
V
Vee +0.5
V
+0.5
V
V1L
= 3.2 mA, except X2
= -0.4 mA, except X2
= -40 pA, except X2
V
+2.4
V
+3.2
@ VIN = 0.4 to Vee
IlL
Icc
±10
pA
8
mA
CAPACITANCE
F = 1 MHz
SYMBOL
MIN
CONDITIONS
CIN.
_
MAX
..
COUT
CIO
_.
AC TIMING SPECIFICATIONS
TA = Doe to 70 oe, Vee = +5 V ±5% unless otherwise specified, VTH
=
2.0 V, VTL
=
I
UNITS
10
pf
10
pf
20
pf
I
j
0.8 V.
,-----
SIGNAL SYMBOL PARAMETER
1
Xi
TX1T
Xi period
62
2
Xi
TX1L
Xi low time
24
3
Xi
TX1H
Xi high time
24
4
Xi
TX1R
Rise time of Xi
0
8
5
Xi
TX1F
Fall time of Xi
0
8
--
MIN
ns
TYP
ns
MAX
ns
#
,,-
1·330
J
--"--
AC TIMING SPECIFICATIONS (cont.)
TA = O°C to 70°C, VCC = +5 V ±5% unless otherwise specified, VTH = 2.0 V, VTL = 0.8 V.
#
SIGNAL SYMBOL PARAMETER
6
XEN
7
XD
TXD
XD delay from X1
8
XD
J XD
Transmit jitter T XD t -T XD~
9
TCLK
XEN delay from X1
I
I +2
TCLK
10 TX
TTXST1
TX setup to falling edge of TCLK, CMODE = 1
90
11
TTXHT1
TX hold from falling edge of TCLK, CMODE = 1
15
12 TX
TTXS
TX setup to X1
15
TX
13 TX
TTXH
TX hold from X1
TTNAST1
TENA setup to falling edge of TCLK, CMODE
15 TENA
1
TENA hold from falling edge of TCLK, CMODE = 1
15
TTENAS
TENA setup to X1
15
17 TENA
TTENAH
TENA hold from X1
15
18 TX
TTXSTO
TX setup to rising edge of TCLK, CMODE = 0
90
19 TX
TTXHTO
TX hold from rising edge of TCLK, CMODE
20 TX
TTXS
TX setup to X1, CMODE = 0
21
TTXH
TX hold from X1, CMODE = 0
15
22 TENA
TTNASTO
TENA setup to positive edge of TCLK, CMODE = 0
90
23 TENA
TTNAHTO
TENA hold from positive edge of TCLK, CMODE = 0
15
24 TENA
TTNAS
TEN A setup to X1, CMODE = 0
15
25 TENA
TTNAH
TENA hold from X1, CMODE = 0
15
26 CLSN
T CLSN
CLSN delay from X1
27 ECLSN
TECLSN
Minimum deteoted pulse width
28 RC
T RCS
RC setup to X1
15
29 RC
T RCH
RC hold from X1
15
30 RD
T RDS
RD setup to X1
15
RD
TRDH
RD hold from X1
15
32 RD
J RD6
RD Incoming Jitter Tolerance,
8X mode, X1 = 8 MHz, T X1T
34 RCLK
40
65
6
=t---
"--
--
0
=
15
15
I
70
5
20
-- ----
-1
TRDSt-TRDS~
URDB
RD Incoming Jitter Tolerance,
10X mode, X1 = 10 MHz, TX1T
T RCLK
RCLK delay from X1, CMODE = 1
-1
I
TRDSt-TRDS~
I
35 TX
TRXRCK1
RX delay from falling RCLK, CMODE = 1
36 RX
T RX
RX delay from X1, CMODE = 1
37 RENA
T RNARCK1
RENA delay from falling RCLK, CMODE = 1
38 RENA
TRENA
RENA delay from X1, CMODE = 1
39 CLSN
TCSNRCK1
CLSN delay from falling edge RCLK, CMODE = 1
40 CLSN
T CLSN
CLSN delay from X1, CMODI:: - 1
--
65
90
TTNAST1
I
40
15
~"
16 TENA
33 RD
MAX
ns
70
14 TENA
TX
TYP
ns
4
TCLK delay from X1
31
-
TXEN
MIN
ns
1-331
123
119
198
194
40
65
-30
30
40
-30
45
-30
~
65
30
65
30
70
AC TIMING SPECIFICATIONS (cont.)
TA = O°C to 70 cC, Vcc = +5 V ±5% unless otherwise specified, VTH = 2.0 V, VTL = 0.8 V.
#
SIGNAL SYMBOL PARAMETER
MIN
ns
41 RCLK
T RCLKO
RCLK delay from X1, CMODE = 0
42 RCLK
PRCLK
RCLK pulse width, CMODE = 0
43 RCLK
TRXCLK
RCLK delay from RX stable, CMODE = 0
TX1T -20
44 RX
TCLKRX
RX hold from falling edge of RCLK, CMODE = 0
2*TX1T-2O
45 RCLK
TRNACLK
RCLK delay from RENA stable, CMODE = 0
TX1T -20
46 RENA
TCLKRNA
RENA hold from falling edge of RCLK, CMODE = 0
2*TX1T-2O
47 RCLK
TCSNCLK
Rising RCLK delay from CLSN stable, CMODE = 0
2*TX1T-2O
TCLKCSN
CLSN delay from rising edge of RCLK, CMODE = 0
TX1T -20
48 CLSN
1·332
TYP
ns
40
TX1T -20
MAX
ns
65
T X1T +20
Xl
~
j
---'=It-- ,-:F' -, "Jt--I
1
Figure 6. External Xl Timing Diagram
Xl
XD
CMODE = 1
(LANCE· 68590)
TENA
XXXXK
}XX>(X
-.j16
17
L_
r--
TX
I'~~
m
XXX
-j 20J:~
I
-t~L
TENAZZK
CLSN
__
26
AXX
1~25r-~
r-
~/'~--------",,--
_1 1_
27
------~~
ECLSN
/~-----
"-----./
Figure 7. Transmit Timing Diagram
1·333
CMODE
(82586)
=
0
X1
RC
I~~
XXIX
~
XXf:X
-1~r311-
RD
XIXX
YYXI
"r
-134 .
RCLK
RX
II
/
--, 36 C
RENA
-H/
---13~
CLSN
37
1-
II'E
-~
RCLK
"l F"
~43
RX
RENA
CLSN
CMODE = 1
(LANCE - 68590)
'XIYX:IXI
r-
XX!X/YY...
I-
45
__:
42
44
--j ..
~
46
~
XX/YX)
-,
'IYYXtJ
-1- -1
47
48
YXXIXYX
'/XIYY)
Figure 8. Receiver Timing Diagram
1-334
CMODE
=0
TEST
POINT
Vee
R,
= 1.2K
CR,
FROM ALL OUTPUTS
UNDER TEST
CL
= 50pF
MIN @ 1 MHz
CR,
O.4mA
CL
I
-
CR"CR.
CR3
CR.
-
Figure 9. Output Load Diagram
1-335
= 1N914 OR
EQUIVALENT
PACKAGE DESCRIPTION
20 Pin Plastic
MK50351N
I.) V
11
V V ' 'n----r---,--,-~-----r'
20
tt::::-j
.970
MAX
260
1 .
R
L
11
7120=
~
-t
.140
-I
.120
MIN •
.015
MIN.
~I-I
Ir-..
t - -_ _---=-9
.015
Jj2f
I
.350
~
EQUAL SPACES _ _ _
@l.100
NOTE: Overall length includes .010 flash on either end of package
1-336
·OOB
--J)'i2
± .050--1
~
CHAPTER 2 - MODEM ICs
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TSG7515
-----~~-
SINGLE CHIP DPSK
SINGLE CHIP DPSK AND FSK MODEM
(BELL 212A - BELL 103 - V22. A/B)
CMOS
SINGLE CHIP DPSK
AND FSK MODEM
The TSG7515 is a single chip DPSK and FSK voiceband modem, compatible
with the applicable BELL and CCITT recommended standards for 212A sets
including BELL 103 and V22 A-B type modems.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CASE CB·132
Monolithic device includes both transmit and receive filters.
Mixing analog and digital technics.
Standard low cost crystal (4.9152 MHz).
Available clock for microprocessor at 4.9152 MHz.
Low power consumption - CMOS technology.
Sharp adjacent channel rejection.
Fixed equalization in transmitter and receiver.
Test loops.
Carrier detect output.
CCITT and BELL signaling tone.
1200 bps and 600 bps bit synchronous format in DPSK.
1200 bps and 600 bps + 1%, - 2.5% or + 2.3%, - 2.5% character asynch·
ronous format (8, 9, 10 or 11 bits) in DPSK.
0 to 300 bps in FSK.
Break signal supervision.
External voice band tone filtering available (i.e. 560 Hz or DTMFi.
CMOS and TTL compatible .
Direct interface to THOMSON SEMICONDUCTEURS microprocessor
family.
Special line monitoring facility.
P SUFFIX
PLASTIC PACKAGE
C SUFFIX
MAIN OPERATING MODES
CERAMIC PACKAGE
•
•
•
•
•
Standard selection (BELL 212A!BELL 1031V22).
Answer tone selection.
Low speed mode selection.
Channel selection (Answer !Originatei.
Synchronous! Asynchronous mode selection.
• 8 bits to 11 bits word length selection in character asynchronous format
mode.
• Overspeed selection in character asynchronous format mode.
• Scrambler selection.
PIN ASSIGNMENT
v+
XlalOUT
• 1800 Hz guard tone selection in V22.
ATE
XI.IIN
• Test loop select;on (Digital/Analogi.
CIB
ClK
AIS
TxSClK
n::
TxD
BRS
RTS
RxD
2-1
TxClK
OSE
SEI
RxClK
GND
TEST
AID
DCD
RAI
ClS
EXI
RDI
ATO
RFO
v-
BLOCK DIAGRAM
EXI
TRANSMIT FilTER
WITH FIXED
CDMPROMISE
EQUALIZATION
RECEIVE FilTER
WITH FIXED
COMPROMISE EQUALIZATION
TxSClK
TxClK
RAI
RFD
RDI
AMPLIFIER AND
LIMITER
CARRIER DETECTIDN
ATD
FSK DEMDDUlATDR
TEST
RxClK
X .allN
GND
X .al OUT
ClK
RTS
BRS
AIO
n:
2-2
ATE
CIB
AIS
ClS
OSE
PIN DESCRIPTION
Common HCtlon Ilupply, clock, handohaklng and moda ....etlonl
Nama
Pin
Type
No
Funetlon
V+
I
1
Positive
V
I
15
GNO
I
20
Ground
XIN
I
'l:I
Oscillator
D.lcrlptlon
+5 V
power supply
Negative
power supply
-5 V
OV
input
This pin corresponds to the input of the oscillator. It is normally connected
to an external crystal but may also be connected to a pulse generator. Tha
OsclUator
This pin correspond. to the output of an inverter with sufficient loop gain
nominallrequancy 01 the osciUator is 4.9152 MHz.
XOUT
0
28
output
to start and maintain the crystal OICiliating.
ClK
0
28
Clock
This pin delivers e clock elgnal, the Irequency 01 which i. the cryllal Irequency. It may be used 8S II buffered clock for a microcentralle,.
C/B
I
3
CCITT/BEll
selection
This th ..... lI.t. input ..Iocts the laatu,.. corresponding to CCITT or BEll
A/S
I
4
Synchronousl
alynchronous
recommendation.
This three·.tat. input seteeta the synchronous bit format or the
asynchro~
noul character format mode in OPSK transmission. This input allows also
selection
char.c~ar
length ..Iection (reler to table B).
ClS
I
12
Character
length
This input selects the character length in conjunction with A/S input Irefer
OSE
I
6
Over·speed
..iectlon
This input selects the over-speed in asynchronous character format mode
required by CCITT racommandllion Iroler to table 8) .
BRS
1
7
Binary rate
selection
A logic "0" on this inpulturnathe chip on 1200 b~ r.ta. A logic "I" turns
tha chip on 600 bps or 0-300 bps .ccording to IB ..Iection.
A/O
I
19
Answ.lOrig.
selection
A logtc "0" on this input turns the chip on answer mode. A logic "1" turns
the chip on originate mode.
T..t loop
This three·llat. input, select. the test loops mode Ir.I.r to table 51.
Tl
I
5
totable 8).
selection
Tran.mlt ••ctlon
Name
Pin
Type
No
Function
O••crlptlon
'iXtI
I
23
Transmit
data
Data bits to be transmitted are serially presented on this input. A mark corresponds to a logic "1" and a space to a logic "0". This data determines
which phase or frequency appears at any instant at the ATO pin in DPSK
ATO
0
16
Analog
or FSK mod...
transmit
output
EXI
I
17
External
tone input
The analog output is the modulated carrier or the answer tonai to be conditionned and sent over the phone line mixed with the filtered signal from EXI.
This analog input allows external tone to be filterml2y an internal low-pass
li~.r. Fi~ered
Signal appears at ATO whateve, RTS.
ATE
I
SEI
I
21
Scrambler
enable input
A logic "0" on this input enables the internal scrambler. A logic "'" instructs the chip to bypass the scrambler.
TxClK
0
24
Transmit
modem
This output delivers a transmit bit clock generated by the chip in Bynchronous mode. When TxSClK is used, TxClK is locked on TxSClK.
This output generates a logic "1" in asynchronous mode.
Transmit
This input roceives a bit clock supplied by the OTE. This clock synchro·
clock Irom
terminal
nizes the internal transmit clock of the chip. In line monitoring mode
this input receives the filters clock.
Requ..t
When a logic "0" i. present on this input. the chip deliver. on ATO a
2
Answer tone
enabl.
A logic "0" on tme input instructs the chip to enter answer signaling tone
mode according C/B selection. A logic "'" turns the chip on transmit dati
mode Irel.r to table 9).
clock Irom
TxSClK
RTS
I
I
25
22
to send
terminal
modulated si9n81 or a signaling tone and the filtered signal from EXI.
When a logiC '1" ispre.ent on this input. ATO deliver. only the filtered
Signal from EXI. When a logic" -1" is present on this input, the receive
section may be used for line monitoring and ATO delivers only the
filtered signal Irom EXi.
2-3
PIn
NMM
Type
No
RAI
I
18
RFO
0
-
FunctIon
o-rlptlon
lnalog
This input recaIveo the lnalog ligna! from the hybrid. It corresponds to the
input of the raceNe filtel1l.
input
14
Rec:aiIIe
filta-
-
outpUt
RDI
I
13
DCD
0
11
Data carrier
RxD
0
8
Rec:aiIIe
-..Iator
This analog output is the ligna! received on RAI once filtered. The receNe
fiIta- ..... oquaIizoa the lignal for adoptotion to most exiding lines. This output
mull be connacted to RDI through I capacitor to IM8I the level detection
conditione.
This pin is the input of the carrier detection logic and of the demodulato<.
input
A logic "0" on this output Indicates that • valid carrier ligna! is P"'"""t on
RAI. A logic "I" meane that no vafod lignal is being received. The hysterelis IM8I standards recommendation.
Data bits demodulated Ire lvailable serially at this output.
data
RxClK
0
9
Racaive
clock
TEST
0
Test
10
This outpUt delivers. receive bit clock generated by the chip. In asynchro·
nous mode this clock is 18 times the modulation rate. In synchronous mode
the clock is equal to the bit rate.
This OUIPut is In intermediate demodulator OUIPul intented lor hendshake
Ind test purposes.
GENERAL DESCRIPTION
An filtering functions required for frequency generation, out·
of-band noise rejection and demodulation are performed by
on-chip awitched capscitor filters. In phase modulation the
madam provides all data buffering and scrambnng functions
. - r y for bit synchronous format and asynchronous character format modes of operation. Internal frequencies are
g_rated from a 4.9152 MHz crystal reference.
The TSG7516 isa general purpose monolithic DPSK arod FSK
modem implemented with double poly CMOS process. It
is capable of gen~ng arod receiving phaae modulated
signals at data rates of 1200 bps or
bps as _II as frequency modulated signals at data rates up to 300 bps on
voice-gracle teIaphona lines. It is offarad in a 2B pin psckage
capable of operating full-duplex according to three pin saIectabla standards :
• CCITT V22 A-B .
• Bel 212A with ita low speed mode:
• Bell 103.
eoo
2-4
FUNCTIONAL DESCRIPTION
TRANSMmER
The transmitter consists of two analog signal generators followed by switched capacitor and continuous filters. In phase
modulation operation mode the DP5K signal generator is
preceded by a selectable scrambler and an asynchronous
to synchronous converter is included in character asynchronous format mode.
Tone allocation: the modern on the end of the line which
initiates the call is called the originate modem. In normal
transmission operation it transmits in low channel and receives in high channel. The other modern is the answer modern
which transmits in high channel and receives in low channel.
Modulators
Transmit filters
To avoid unwanted frequency components to be echoed by
the hybrid in the reception path, to maintain the level of spurious out-of-band signals transmitted to the telephone line
below the limits specified by administrations (see figure
below) and to complete statistical amplitude and phase equalization, the analog signals are processed by ten poles sharp
pess-band switched capecitor filters. The response of these
filters depends on the selected channel (Answer/Originate)
and the selected standard (BELL 212-V22/BELL 1031. A continuous filter eliminates perasitic sampling effects. An additionallow-pass filter input is provided. This allows to mix
and filter such tones as DTMF signals or spacial guard tones
(550 Hz) to the transmitted signal.
DP5K modulator: the phase modulation type is differential
quadrature four phase shift keying (see table 1). The 1200
bps data stream to be transmitted is converted into two 300
dibits per second streams which modulate alternatively two
independant carriers. Consequently the base band shaping
is included is a 5 bit address ROM which generates samples
for a 8 bit switched capacitor DAC at a frequency equals
to 8 times the carrier frequency.
n-l
n
0
0
0
1
00
1
0
+270 0
Phase shift
+900
1
+180 0
0
+90 0
1
+270 0
Tabla 1: DPSK modulation
F5K modulator and tone generator: a frequency synthesizer provides accurate clocks to a switched capacitor sine
wave generator (see table 2). Phase continuity is maintained when a frequency shift occurs.
AIO
TxD
Standard frequency
0
0
2025 Hz
1
2225 Hz
0
1070 Hz
1
1270 Hz
1
Table 2: FSK modulation (BELL 1031
Standard
frequency
1070 Hz
o
-23
TxD
BRS
1
dBm
-27
-~
I
I
I
----~-~---------------~
16
3.4 4.3
f (kHzl
Figur. 1 : Tr.n .... itted signal templete
Scrambler
The scrambler used during phase modulation ensures the
transmission of a continuously changing pettem. This avoids
the receiving modem to drop out of lock on certain continuous repetitious data petterns. This scrambler may be disabled during handshaking procedures. In V22 a spacial unlocking sequence is performed on 64 spaces pattern at scrambler output.
Asynchronous to synchronous converter
The DP5K signal is synchronous in nature but the modem
has both an asynchronous as well as a synchronous mode
of operation in DP5K. So a data buffer is necessary to convert variable rate asynchronous character data to an equivalent bit oriented synchronous data stream. This is done
by inserting or deleting stop bits. In addition this converter
is able to recognize and format the break signal.
using 4.91 MHz
% deviation
from standard
1066.7 Hz
-0.3%
Frequency
Mode
BELL 103 Originate
1200 Hz
1200 Hz
1270 Hz
1269.4 Hz
-0.05%
1800 Hz
1807.1 Hz
+0.4%
Guard tone V22
2025 Hz
2021 Hz
-0.2%
BELL 103 Answer
2100 Hz
2104.1 Hz
+0.2%
Answer tone CCIIT
2225 Hz
2226.1 Hz
+0.05%
BELL 103
Answer or Answer tone BEll
2400 Hz
2400 Hz
BELL 212A or V22,Originate
BELL 103 Originate
BELL 212A or V22,Answer
Table 3: Output fraquency deviation
2-5
RECEIVER
Test output
The receiver includes two band-pass filters followed by an
amplifier and a hard limiter. Depending on selected standard,
the detector output is passed through a DPSK demodulator or a FSK demodulator. The DPSK damodulator is foliowad by a deserambler and a selectable synchronous to
asynchronous converter. In addition a carrier detector monitors the level of the received signal.
Once demodulated DPSK data are generally processed lef
next paragraph I but during call set-up procedures or data
set testing it is of importance to monitor the demodulator
output. So in DPSK mode demodulated data are available
on TEST pin.
Tone allocation: in normal transmission operation the originate modem receives in high channel and transmits in low
channel. The answer modem receives in low channel and
transmits in high channel.
Delcrambler and synchronous
to .synchronous converter
Data coming from the DPSK demodulator are unscrambled.
In V22 the unlo..king sequence is detected at descrambler
input and the original data are decoded before descrambling.
In asynchronous character format mode of operation a data
buffer is able to detect missing stop bits and reinsert them.
The converter is able to recognize the break signal and transmits it without modification.
Receive filters
The signal delivered by the hybrid to the receive analog input
is a mixture of transmitted signal, received signal and noise
with a level in the range from -48 d8m to -0 dBm. Depending on the oparating mode and the selected standard the
20 poles receive switched capacitor band-pass filter selects
the frequency band of the low channel or the high channel.
A ratio of 14/15 is applied on the sempling clock frequency
between FSK and DPSK in the same operating mode (Answer/Originate). These filters reject out-of-band transmission
noise components and undesirable adjacent channel echo
signals which can be fed from the transmit section into the
receive section. Fixed equalization is included in order to
assure low error rate.
Cerrler detector
Whenever valid signals are being received at the input of
the demodulator and are acceptable for demodulation, carrier detect output is pulled down. A delay is timed out before
the carrier received or carrier lost signal changes carrier
detect output to provide immunity against noise bursts. The
modem also provides at least 2 dB of hysteresis between
the carrier ON and the carrier OFF thresholds I~ee diagram
belowl.
Amplifier and hard limiter
Once filtered the received signal is amplified and fed to the
carrier detector. In order to limit analog parts in the design
all the demodulator techniques used in the TSG 7515 are
based on zero crossing detection. So the received signal is
just limited before entering demodulator.
I
RAI
... ---;-------
N_~L...m++l+H-~
-
,unu;d)roJ':,
H
•
Demodulator.
DPSK demodulator: a DPLL is used to recover the carrier
signal. This DPLL has a lock range of ±2 Hz but as theincoming carrier may present an offset of ± 7 Hz a second loop
allows the first DPLL to lock on the exact frequency of tha
carrier with an accuracy of ± 1 Hz and to follow its slow
variations. Then the limited received signal is mixed through
exclusive-Or with the recovered carrier and with the 90
degrees phase shifted recovered carrier. The results are processed through four poles Bessel filters which provide a good
amplitude propagation time compromise. The received sempiing clock is recovered from these base band data with a
simple DPLL. The received data are sampled by this clock
and then converted into a serial synchronous bit stream.
I
I
I
i
/J
-
I
---.--
I ___
~
In DPSK mode 105 ms 10 IdJI
VOS
-2
Load capacitance
OL
-
load resistance
RL
10
Signal distortion
0
-
+3
V
+500
mV
+2
V
20
pF
-
IdJ
-40
dB
ANALOG INTERFACE, TRANSMIT OUTPUT (ATOI
EX' connected to GND
Che,ecte,iltic
Output offset voltage
Symbol
Min
Typ·
Me.
Unit
VOF
-500
-
+500
mV
-
Output vo'tage swing IRLI 10 kll, CL=2O pFI
-
Carriers
Vo
Answer I Originate amplitude ratio
AR
Guard tone 1800 Hz
Vo
-
1.1
Vo
-
1.9
AT
55
Symbol
Clink"
NI
2400 Hz
w~h
1800 Hz
RTS attenuation
2.2
-1
+1
Vpp
dB
Vpp
-
-
MIn
Typ·
Me.
Unit
-1
10
9.8
mVp
N2
-
13.8
-
Nl/N2
2
-
5
dB
Vpp
dB
ANALOG INTERFACE, RECEIVE DEMODULATOR INPUT (ROil
Cherocteriatlc
Serial capacitor from RFO
Maximum detection level to valid OeD output
Minimum detection levet to valid OeD output
Hysteresis effect
.. This capacitor must be unpolarized type capacitor
2-14
p.F
mVp
DYNAMIC CHARACTERISTICS
RECEIVE FILTER TRANSFER CHARACTERISTICS IN DPSK
LOW CHANNEL
Symbol
Min
Typ·
Ma.
Unit
GA
GR
-
+6
-
dB
-
-45
-
dB
900 Hz
-
-0.5
dB
1500 Hz
-
+0.8
-
1800 Hz
-
-50
-
dB
2400 Hz
-
-65
-
dB
Symbol
Min
Typ·
Ma.
Unit
GA
GR
+6
-
dB
-0.2
-
dB
2700 Hz
-
+0.7
-
dB
1800 Hz
-
-25
-
dB
1200 Hz
-
-68
-
dB
Char.cterlatic
Absolute passband gain at
1200 Hz
600 Hz
Retative gain to GA at
dB
HIGH CHANNEL
Charlcteri,tlc
Absolute passband gain at
2400 Hz
Relative gain to GA at
2100 Hz
RECEIVE FILTER TRANSFER CHARACTERISTICS IN FSK
In FSK the receive filter is the same as in OPSK but the sampling frequency is multiplied by a 14115 ratio (i.e. 2400 Hz in DPSK becomes
2240 Hz in FSKI.
LOW CHANNEL
Characteristic
Absolute passband gain at
1120 Hz
HIGH CHANNEL
Characteristic
Absolute passband gain at
2240 Hz
2·15
SUMMARY OF THE DIFFERENCES BETWEEN BELL 212A AND V22 A·B
Feature
Low speed mode
BELl212A
V'l2
0·300 bps FSK
600 bps DPSK
No
1800 Hz optional·
Guard tone
2225 Hz
2100 Hz
Character length in asynchronous mode in DPSK
9,10 bits
8, 9, 10, 11 bits··
Over speed mode in asynchronous mode in DPSK
No
No
Yes·-
Answer tone
64 spaces detection
Yes
robl.l0
*
**
550 Hz may be externally generated and added to the transmit signal through EXI.
Features of V22 afe available in BELL 212A on the chip.
All these differences are taken into consideration inside the TSG7515
CASE CB·132
"'
.J
:f:::~;,:~~:~Jl:: ;-=_7_
28.,m
-
,
A51E
(EI
C8-132
D,A.T A
2-16
TSG7515
SINGLE-CHIP MULTI-STANDARD DPSK & FSK MODEM
APPLICATION NOTE
~~
J
I
,II
~
~
,
\
""-......01IIII
7
I
~
1fII""""IiI
~
J
I
,I
\
\,
,
\
\,
~
~
I
I
1\
\
,
IIirI..
~
~
1\
\
,
~
""-~
I
~
APPLICATION NOTE ANBy MaUfJCe PATRIGEON
Application Laboratory
MO') Ofvf~ion
___ ~!.4{~66~6.!l0() __ ~ _
_ _ _ _Telex ~!!.~~3__ ~ __ ~~_"
2-17
2-18
TABLE
OF
CONTENTS
Paragraph
CHAPTER I
-
MAIN CHARACTERISTICS OF TSG 7515
1.1
General Features..............................................••••••••••••••••• I - I
1.2
Pin Configuration .•.•....••.••.••.•.•..•••••.•..•.••..•••••••••••••••••••.•••• _. I - 2
1.3
Descripfian af Pins ...••••••••.••••••.••.•..••..•••••••••••.••••••••••••.•••.
1.4
General Description & Block Diagram ...•..••••••••••••••••••..•••••. 1-6
I- 2
1.5
Functional Description ....................................................... I - 8
1.5.1
Transmit Section ..••..••.•.•....•••...•...•.•.••••••••••.••••••••••.•.. 1-8
1.5.2
Receive Section .••••..••..•.•••.•••.••.......•.••••••••••.••••••.••.•.•• 1- 9
1.5.3
Common Units .•.•••••••••••••.•..•..•.•..•••••••••.••••••.••••.•••••.•.• 1-10
1.6
Functional Characteristics ••••••.••....•.••••••••••••.••••.••••.••••.••.•.. 1- 10
1.6. I
Asynchronous I Synchronous Converter .••••..••••••••••••••••• I - II
1.6.2
Synchronous to Asynchronous Converter .•...•.••••••••••... 1-12
1.6.3
Scrambler & Descrambler .......•••.••..•.••...••.•••.••••..•.••.• 1-13
1.6.4
Carrier & Tone Generators .•.....••••.••..•..••.•••.••.•..••••••• 1- 16
1.6.5
Transmitted Spectrum •..••••••.••••.•..•.•••••.••.•...••.••••..•.•.. 1- 16
1.6.6
1.6.6.1
1.6.6.2
Filters .•..•.••...•••••.••..•.•••••••••.••••..•..•.••.•••.••••..•.••.•••.••.. 1- 17
Transmit Filter ................................................ 1- 17
Receive Filter.................................................. 1- 17
1.6.7
Level Detector ••••••••••••••••••••..•••••..•.••••••••.•.••.•••.•••.•... I - 17
1.6.8
1.6.8.1
Synchronous Demodulator ......................................... I - 18
Demodulator Block Diagram............................. I - 18
1.6.9
1.6.9.1
Summary Tables af Operating Modes ....................... 1- 19
Synthesis of different modes for
Receive Section .............................................. 1-19
Synthesis of different modes for
Transmit Section ...........................................
I - 20
Mode selection in Phase mODulation
transmission ..................................................
1-21
Test pin ....................................................... 1-21
Call Progress Detection ............................. 1 . 22
1.6.9.2
1.6.9.3
1.6.9.4
1.7
CHAPTER 2 -
DETAILED DESCRIPTION OF
v.n
& BELL 212A STANDARDS
2.1
Foreword ..................................................................... ..
2- I
2.2
V.2] Standard ................................................................
2- I
General Description ............................................ ..
Variant A ................................................... ..
Variant B .................................................... .
2-1
2-2
2.2.1
2.2.1.1
2.2.1.2
2-19
2-2
2-20
TABLE OF CONTENTS (continued)
2.2.2
2.2.2.1
On -line Signals ....................................................
Levels of transmittea data Signals
, Guard Tone .......••...........••.•...•.•.•........••..•..
2-2
2.2.3
Fixea Delay Compromise Equalizer •••••••••••••••••••••••
Spectrum , Group Propagation Times .....••••..•.....•.
2-3
2-3
Modulation •••••••••••••••••••.••••••••••••••••••••••••••••••••••••••••
Bit Rate ...........................••...•.•..•.•.••.••••.•..•..
Data Bits Coding •••••••••••••.•••.••••.••••••••••••••••••••
2-.
2-.
2.2."
2.2.5
2.2.5.1
2.2.5.2
2.2.6
2.2.7
2.2.7.1
2.2.7.2
2.2.7.3
2.2.7."
2.2.7.5
2.2.8
2.2.8.1
2.2.8.2
2.2.9
2.2.10
2.2.10.1
2.2.11
2.2.12
2.2.12.1
2.2.13
2.2.13.1
2.2.13.2
2.2.14
2.2.1 "-1
2.2.1".2
2.2.1".3
2.2.1"."
2.2.15
2.2.15:1
2.2.15.2
2.3
Frequency tolerance of the receiveD signal ••••••••••
Connector Pins ••••••••••••••••••••••••••••••••••••••••••••••••••••••
Summary of pins •••••••••.••••••••••••••••••••••••••••••••
Thresholds of Pin 109 ••....•............•.•..•••...•....
Pin 111 , Bit R ate Control •••••••••••••.•••••••••••
Electrical characteristics of connector pins ••
Error conditions of connector pins •••••••••••••••
DTE I DCE Interface Modes of Operation ••••••••••••••
Variant A •••••••••••••••••••••••••••••••••••••••••••••••••••••
2-2
2-.
2-.
2-5
2-5
2-6
2-6
2-6
2-6
2- 7
Variant B •••••••••••••••••••••••••••••••••••••••••••••••••••••
2- 7
2-7
Transmitter ..........••.•••.....•.•.......••.•............••.•.•.....
2- 7
Fundamental Bit Rate •••••••••••••.••••••••••••••.••••••••••.•••
Higher bit rates ......•..•............•....................
2-8
2-8
Break Si gnal ••••••••••••••••••••••••••••••••••••••••.•••••..••..•..••
2-9
2- 9
Receiver •••••••.••••••••••.••••••••••••••••••••••••.••••••••••••••••••.
Break Signal •..•••••••.••••••••••••••••••••••••••••••••••••.
2- 9
2-9
Scrambler , Descrambler •••••••••••••••••••••••••••••••••••.•
Scrambler •••••.•••••••••••••••••••••••••••••••••••••••••••.••.
Descrambler •••••••••.••••••••••••••••••••••••.••••••••••••••
2 - 10
Sequence of Operation .............................. '........... .
Channel , Operating Mode Selection ••••.••••••.
Operation on switched telephone lines ......... .
Modem in Originate Moae ........................... .
Modem in Answer Mode ••••••.•..••.•••••.••.••..•.••.
2- 11
2- 11
2- II
2 - 13
2-13
Measurement facilities (Maintenance) •••••••••••.•..•••.
Type 2 loopback establishment .••••••.•.••..•..••..
Suppression of type 2 loopback •.•.•.•..••••.•••••..
2- 13
2 - 13
BELL 212A StanDard Description •.••••••••••.••.•••.•...•••.•••••••.
2 - 15
CH"APTER 3
-
2-9
2- 14
TSG 7515 APPLICATIONS
3.1
Introduction •••••••••.••.•.•..•••.••••••••..•.••••.••.•••.•••••••••••••.•••.••.
3- I
3.2
Application Diagram................................................•.•..•.
3- I
3.3
MODem Configuration Switches •.••••••••••••.••..•••.••.••••••••••..
3- 3
3.4
Terminal Interface ........................................................
3- 8
2·21
TABLE OF CONTENTS (continued)
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
Line Interface •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
4-wire l2-wire conversion •••••••.•••••••••.••••••..•••••••••••
Galvanic lsalation ••.•••.••.••••••••••••••••••••••••••••.•••••.•••••
Line current Regulation ........................................
Ring Detection •••••••••••.••••.••.•••...••.••..•.•.••.•••••..••••••
Pulse Dialing •••••••••••••••••••••••••••••••••••••..••••••••••••••••••
CHAPTER 4
4.1
4.1.1
4.1.2
4.1.3
11.1.4
4.1.5
4.1.6
4.7.7
-
3- J1
3- If
DESCRIPTION OF SOFTWARE
-
Definition of Software Modules .••••••••••••••.•••••••••••••••••••••
Idle state management module ••••••••••••••••••••••••••••••
CCITT handshake module •••••.••.•••••....•.••..•••••••.•.••••.
BELL handshake module •.•••••••••••••..••..•••••••••••••.••••.
CCITT transmission module .•••••.•••••••••••.••.•••••••••••••
BELL transmission module •••.•.•.•.•.•••..•..••••.•••..••.•••
RDL handshake module .•••.••••••.••••••••••••..••.••••••••••••
Loop 2 receive handshake module .•.••.••••••...••......•.
APPENDIX A
3-9
3-9
3- 10
3-11
II - I
II-I
II - I
4- 1
4-1
4-2
4-2
4-2
TSG 7575 HANDLING PRECAUTIONS
A.7
Power supplies decoupling & layout considerations •.••..••.
A-I
A.2
Carrier Recovery Loop •.•••...••••...•••••....•••••.•••.••••.....••••.•.
A- I
A.3
Frequency Precision of Crystal Osci/lator.......................
A- 2
APPENDIX B
-
APPENDIX C
GLOSSARY OF TERMS
-
BIBLIOGRAPHY
2-22
CHAPTER I -
MAIN CHARACTERISTICS OF TSG 7515
1.1 - General Features
TSG 7515 is a mono chip voice-band modem compatible with BELL 212A. CCITT
V.22 A and B standard requirements.
- Incluaes both Receive and Transmit Filters.
- Designed using analog and digital techniques.
- Requires standard iI.9152 MHz crystol osci/lator.
- Buffered clock aut put for microprocessor-based applications.
- Low power consumption - CMOS technology.
- High adjacent channel signol rejection.
- Fixed equalization in transmission ana reception.
- Mointenonce loop : type 2 and 3.
- Carrier detect aut put.
- CCITT ana BELL answer tones.
- 1200 and 600bps synchronous operation in DPSK mode.
- 1200 ana 600bps +1%. -2.5% or +2.3%. -2.5\ asynchronous operation
in DPSK mode.
- 8-. 9-. 10-. II-bit character format in asynchronous mode of operation.
- 0 to 300 bps data rate in FSK operation.
- Break Signal supervision.
- Special line monito'ring facilities.
Main Operating Modes
- BELL212A1BELLI03/v.22 Standard Selection.
- Answer tone selection.
- Fallbaclc Mode selection.
- Originate/Answer Channel Selection.
- Synchronous/Asynchronous Moae Selection.
- Character length selection in asynchronous moae.
- Overspeed Selection.
- Scrambler Selection.
Guard tone selection in V.22 mode.
- Analog/Digital test loop Selection.
2·23
1-1
1.2 - Pin Configuration
v'
iii
cIa
XIII/OUT
XW.IIN
ClK
T.seLIC.
T.Clk
hl)
ill
sri
..
GNO
'i/O
,
EX'
.TO
v-
1.3 - Description of Pins
V+
Pin
Positive power supply
Pin 2
5V +5%
Ai/;" (Answer Tone Enable)
This pin allows to configure the aevice in either mooem mooe or as a
transmitter of pure frequency (answer tone).
- A logic low (0) signal applied to this pin causes the device to
output through A TO (Analog Transmit Output) pin a pure sinewave
whose frequency depenos on the programming of 'C/S ((CITT/BELL)
Pin.
- Inversely, a logic hiyh (1) on
ATE
pin will configure the aevice
in modem moce.
Pin 3
LIB (CLTiiIBELL)
This three-state input selects one of CCITT
Pin ..
v.n
and BELL 212A stanaarcs.
A/S (Asynchronous/Synchronous)
In DPSK mode, this three-state input selects Asynchronous or Synchronous
moce of operation. In asynchronous operatIon, it
length selection.
1-2
2·24
0150
proYioes the character
7'[ (Test Loop)
Pin 5
Three-state input pin for the selection of Test loop 2 or Test loop
J.
OSE (Over Speed Enable)
Pin 6
In asynchronous mode, this input selects one of two possible over speed
configurations available in CCITT standard recommendations.
Pin 7
BRS (Binary Rate Selection)
This pin is used for the selection of binary rate as follows :
- A logic low (0) signal on this input configures the device to
receive and transmit data at 1200 bps.
- A logic high (1) signal applied to this input enables the CIrcuit
to receive and transmit data at 601l bps in CCITT moce or JOO bps
in BELL 212A mode.
RxD (ReceIve Data)
Pin B
This output provi:Jes binary data provided by the oem adulator.
Pin 9
RxCLK (Receive Clock)
ThIS output corresponds to Modem's receive bit clock.
- In synchronous mode, the clock is synchronized with data
output through RxD pin.
- In asynchrDnous mode, this pin delivers a clock rate 16 tImes
faster thon mDaem's mDdu/atlOn rate.
Pin 10
TEST
The output SIgnal is available Dn th,s pin before passing thrDUyh the
descrambler. ThIs pin IS intendea for "handshake" ana "remote loop request"
purpDses.
Pin 11
DCD (Data Carrier Detect)
Th,s pin will gD low when device receives a signal level higher than - 4J dBm
on RAI (ReceIve Analog Input) pin ana gDes high if the SIgnal level IS
lower than - 48 dBm. The - 43 dom to - 48 dBm range provooes a 5 dB hysteresis
for the initiatIOn of
DC15
function.
2-25
1·3
Pin J 2
:
CLS (Character Length Selection)
In conjunction with loIS pin, this input selects the character length.
Pin J3
RDI (Receive Demodulator 'nput)
:
This input receives analog signals and directs them to comparators
associated with demodulator ond signal detector. The signal is 0/50 applied
to various demodulation circuitry.
Pin 74
:
RFO (Receive Filter Output)
The analog signal first goes through various band-pass and equalization
filters and is then ovailable at this output pin.
Access to this pin simplifies in particular the device test proceoures.
While designing an application, and as for os possible, the P.e.Boaro
layout must be so arranged that RFO output could be reaaily couplea to
RDI input terminal through a single capacitor.
Pin 15
Y-
Negative power supply; -5Y !5%
Pin J6
:
ATO (Analog Transmit Output)
In conjunction with signal applied to
An
(Answer Tone Enable) terminal,
this output delivers either a modulated carrier or on answer tone.
Pin J7
With
EXI (External Tone 'nput)
rn
accepts an
(Request To Send) terminal at logic "1 ". this analog input
external tone which will be first filtered and the'; routed to
ATO (Analog Transmit Output) terminal.
Pin J8
RAI (Receive Analog Input)
This is input terminal to the receive filter. Signals receiveo via line are
applied to this pin.
1-4
2·26
Pin 19
:
A/O ('AriSWei-IOriginate)
Signal level applied to this pin selects modem's operating mode (Answer or
Originate) as follows :
A "0" applied to this pin selects Answer mode.
A
"J"
applied to' this pin selects Originate mode.
Note: In answer mode, upper channel (2400 Hz) and guard tone (l800 Hz)
may be transmitted simultaneously, provided that the guard tone
power level is 6dS less than that of modulated 2400 Hz Signal.
Transmission of this guard tone is enabled through CIS terminal.
Pin 20
: GND
This is the ground terminal common to all digital and analog sections of
TSG7515.
Pin
~ (Scrambler
27
Enable Input)
This input enables the scrambler operation.
A "0" applied to this input enables the scrambler.
A "I" applied to this input disables the scrambler.
rn
Pin 22
(Request To Send)
With a Icgic level "7" applied to this pin, the aevice outputs through ATO
pin the signal delivered by EXI terminal.
With a logic level "0" on this pin, the circuit aelivers through A TO terminal
a signal whose char'Jcteristics are determined by the state of ~ terminal.
With this pin at logic level "-'7 ", the TSG 7515 is configured as a
programmable filter. Thot is, TxSCLK input becomes a clock input running
at a frequency equal to twice the samplin§ frequency of the receive
filter, that may be assigned to upper or lower Channel, in accordance with
signal level applied to A/O terminal. In this configuration of rn, the signal
originated through rJC!5 terminal is the exact representation of the tone
envelope do tee ted via line.
Pin 23
:
TxD
(Transmit Data)
This input receives the data transmitted by terminal.
In DPSK and FSK operating modes, these data bits (1 and 0) determine
the phose (for DPSK) or the frequency (for FSK) of the signal output
through ATO pin.
2·27
1·5
Pin 24
:
TxCLK (Transmit C/ocle [Generated by Modem})
In the absence of TxSCLK. this output delivers the bit clock transmitted
by the modem for the synchronization of data output through TxD terminal.
BRS selects the frequency as fo/lows :
Pin 25
BRS = 0
==>
TxCLK
7200 Hz
BRS = 1
==>
TxCLK
600Hz
TxSCLK (Transmit Clock [Generated by Termina/})
This input corresponds to bit clock generated by the terminal whose frequency
is 1200 Hz if BRS=O and 600 Hz if BRS=I. This clock allows to locle the
modem's internal clock on the clock generated by terminal. thus providing
synchronization between these two clocks.
Pin 26
CLK (Clock)
This is buffered output of the clock running at 4.9152 MHz.
Pin 27
Xtal in (Osci/lator Input)
This pin corresponds to the osci/lator's input inverter. It is normally connected
to on external crystal but may also be fed by a pulse generator. The crystal
frequency must correspond to standard frequency of 4.9752 MHz.
Pin 28
Xtal out (Oscii/ator Output)
This pin corresponds to the output of on inverter with sufficient loop gain
to trigger and maintain the crystal oscillation.
1.4
-
General Description & Block Diagram
TSG 7515 is on integrated circuit fabricated resorting ,to silicon gate
CMOS technology,
Device includes major modem functions required for simultaneous bidirectional
transmission of asynchronous or synchronous data in accordance with the
following standard requiremenfs
CCITT V.22 variants A & B
BELL 212A DPSK operation
BELL 103 FSK
1-6
2·28
This modem operates using channel multiplexing techniques by frequency
allocation of 600 Bauds for modulations rate and 1200 bits/s (600 bits/s in
fallback
mode) for transmission rate.
Transmission made for each channel is Differential Phase Shift Keying
(DPSK) modulation combined with on-line synchronous transmission.
This feature is entirely reversible. i.e. operation is possible in either of
Originate or Answer modes.
When used in combination with appropriate line and controller circuits. this
device can operate on both 2-wire switched telephone network and
all point-to-point leased lines.
TSG 7515 Block Diagram
Figure
."
Sfl
4TO
TaO
1.SCLI(
1.CL1(,
",0
6'El5
'0'
iG'5
Tt"
,.
GNO
II: teo' OU'T
,,,
m
...
• 0
;;
m
2·29
Co
• s
ce,
oS!
'·7
1.5 -
Functionol Description
The device is organized in 3 distinct sections
Transmit section
1.5. I -
-
Receive section
-
Common units
Transmit Section
This section comprises
- An asynchronous to synchronous converter whose duty is to accept
chain of asynchronous characters and to convert it ta a form
suitable far 1200 bits/s or 600 bits/s +0.07 % synchronous transm ission.
This converter meets in all respects CCITT standard requirements
defined in Chapter "4.2.1" of V.22 recommendations.
In synchronous lJlode of operation. the converter is disabled.
- A variable ratio divider used for the generation of eight different
frequencies :
1200Hz +0.5 Hz
DPSK lower channel
(Originate Mode)
1800 Hz +20 Hz
Guard tone transmitted optionally with
upper channel
(CCITT Standards)
2100Hz+16Hz
Answer tone
2400Hz+ I Hz
DPSK upper channel
2225 Hz + 16 Hz
Answer tOIle
(Answer Mode)
(BELL Standa,.ds)
or
FSK upper channel
2025 Hz+ 10 Hz
FSK upper channel
1270 Hz + 5 Hz
FSK lower channel
1070Hz+ 5Hz
FSK lower channel
A transmit clack generator using a phase-locked loop circuit
in order to lock the transmission clock onto either the clock
generated by data terminal or the receive clock.
- A data scrambler in accordance with CCITT standard requirements
as defined in "Chapter 5.7" of V.22 recommendations.
1·8
2·30
- A buffer circuit that stores the last phase of the carrier and
generates appropriate phase shift thus providing the new phase
shift to be applied to the carrier.
- A carrier generator that uses two sub-carriers over modulated In
amplitude. to synthesize the DPSK signal.
- A transmit filter whose frequency response is determined by
selected mode of operation (Originate or Answer).
- A non switched smoothing filter that removes clock transients
and rejects out-of-band frequencies.
1.5.2
-
Receive Section
This section includes
- An anti-aliasing filter
- A bond-pass receive filter whose frequency response depends on
the selected mode of operation.
- A compromise equalizer filter that provides appropriate functional
performance on a variety of lines.
- A phase-locked loop. for the, recovery of carrier signal frequency
so as to perform a coherent differential phase demodulation on
received signal.
- A demodulator.
- Two low-pass digital filters for the extraction of Eyes Pattern
- A decision making module that converts the eyes pattern into logic
Signals, stores them, detects the phase shift and performs
identification of the receiVeo data.'
- A synchronization unit that recovers the moaulatian time base
and delivers RxCLK (Receive signal Clock) to the data terminal.
- A delayed hysteresis level detector that meets CCITT standara
requirements of connector pin 109 as oefined in Chapter 3.3 of
V.22 recommendations.
2-31
A data descrambler in accordance with CCITT V.22
recommendations.
- A synchronous to asynchronous converter whose duty is as follows
- Accept chain of characters originated from a V.22-type
asynchronous modem operating in transmit mode, demodulated
by a V.22- type synchronous demodulator
- Recover the initial character chain applied to the asynchronous
to synchronous converter of the transmitting modem.
This synchronous to asynchronous converter meets in all respects
the CCITT standard requirements as defined in Chapter 4.2.2 of
V.22 recommendations.
The converter is disabled in synchronous m.ode of operation.
1.5.3
Common Units
This section includes
- A time base generator that uses a standard 4.9152 MHz crystal
oscillator to derive all internal clock frequencies required for
modulator and demodulator operation.
- A reference voltage generator delivering on internal reference
voltage for
- Amplitude clamping of the transmitted signa/.
- DefinItion of demOdulator's two threshold
detection levels.
1.6
Functional Characteristics
Asynchronous/Synchronous & Synchronous/ Asynchronous Converters
Operating principles of these converters are covered in Sections 4.2.1 and
4.2.2 of CCITT
v.n
recommendations.
These converters are employed only in the case of variant B configuration.
1·10
2-32
J.Ii. J
-
Asynchronous/Synchronous Converter
{/) - If data to be transmitted is generated at a rate lower than
J200 bits/s (but within the over speed selection limits imposed
by OS£), the converter will insert the necessary stop elements
as illustrated by timing diagram below.
OTE transfers 10 the- converter 1M .;uta to ite
transmlUe-d at a rote lower '''on flOG bil,/s
t
c:
::n,-,-I_ _--'
:::nUlc==nll I
LI~I~
•
t.:on~'ler transfers to the modulatDt the data to
be tronsmi-tll:i1 at 1200 bits/i
--'I
L...L.._ _
1..C
______~IIL~______~ LC
.stop element insetted by
converter
b) - If data to be transmitted is generated at a rate higher than
1200 bits/s (but within over speed selection limits imposed
by 05£), the converter will suppress the stop elements as shown
in timing diogram below.
DTE transfers to the ennlle'rter the data to be
thon 1200 bltsls
IransmltteG at a rote
~
I I
=:n~
I
____~1 LI~1~===rILIJ:====:LL:====J1~====:JlLI:::
Converter transfers to
t~
modulator the dolo to
1100 bits/s
~ transmilteG 01
Stop element suppresseD
by converter
2-33
1·11
c) - Break· Signal
Break signal contains M to 2M+3 bits, 0/1 of which maintain
their initi?' state. M represents number of bits per character
corresponding to selected format. Upon detection of such signal,
the converter automatically generates 2M+3 bits all having
their initial polarity. Timing diagram be/ow illustrates this procedure.
Sreak ~gno' generated
by
...-___....,...,4--
=::J'lL...L___-' I
fTC
8K
IDS ms ..<' "I ~ 205 ms
~
.11-
,1< ]"5 ms
D~K
ICJ m .. f ,.1", .114
F~I<.
i5m'lo':"\L~15n1~
m~
Synchronous Demodulator
The signol received on line is first filtered and clamped at appropriate/evel
and then applied to this synchronous modulator which will deliver demodulated
dato synchronized on receive clock.
1.6.8.1 - Demodulator Block Diogram
Receol~d S'gnol
CFllrrr~ • Clampt"GJ
1)
Post~nlodul(Jllo
Fillers
1-18
2-40
f
C
res.
1.6.9 -Summary Tables af Operating Modes
1.6.9.1 - Synthesis of different Modes for Receive Section
CIS
-lor 0
BRS
TL
AlO
X
-I
0
DPSK Originate Loop J
1
DPSK Answer Loop J
0
DPSK Answer Loop 2
1
DPSK Originate Loop 2
0
DP5K Answer
1
DPSK Originate
0
DPSK Originate Loop J
0
1
J
0
- 1
Mode
Receive
!
DPSK Answer Loop 3
0
DP5K Answer Loop 2
1
DPSK Originate Loop 2
0
DP5K Answer
1
DPSK Originate
- 1
0
FSK Originate Loop 3
!
FSK Answer Loop 3
0
0
FSK Answer Loop 2
!
FSK
0
1
V.22
BELL212A
Inc/uaing
!
!
Originat~
0
F5K Answer
!
F5K Originate
Answer
Receive in Lower Chonnel
Originate
Receive in Upper Chonnel
Loop J
Analog Loop
Loop 2
Digital Loop
2-41
SELL 103
Loop 2
1-19
1.6.9.2 - Synthesis of different Modes for Transmit Section
ATE
CIS
0
1
SRS
A'O
Transmit
Moae
- 1 or 0
2100 Hz
Answer
1
2225Hz
- 1
0
0
DPSK 1200bps Answer
1
DPSK '200 bps Originate
0
D~K
600 bps Answer
D~K
600bps Originate
Tone
V.22
1
0
0
I
I
0
,
0
DPSK '200 bps Answer
1
DPSK J20Qbps Originate
0
DPSK 600 bps Answer
,
without
Guard
Tone
V.22
with
J800 Hz
Guard
DPSK 600 bps Originate
0
DP5K 1200 bps Answer
1
DPSK 1200 bps Originate
0
FSK 0 - 300 bps Answer
1
F5K 0 - 300 bps Originate
Tone
SELL
1
1-20
Answer
: Transmit in Upper Channel
Originate
: Transmit in Lower Channel
2-42
212 A
1.6.9.3 - Mode Selection in Phase Modulation Transmission
AIS.
CLS
OSE
Transmission
Mooe
-J
0
0
1
J
0
1
Character
Length
B
Overspeed
+1\ • -2.5\
+2.3\ • -2.5\
lJ
+ J\ • -2.5\
+ 2.3\ • - 2.5\
Asynchronous
0
0
0
9
1
1
0
10
1
1
1.6.9.4 -
0
+ 1\ • -2.5\
+ 2.3\ • - 2.5\
+ 1% • -2.5\
+ 2.3% • - 2.5%
0
Synchronous
Transmit
~
ATE
CIB
BRS
0
-lor 0
0
Receive
Test
600 bps
000
1
V.22 DPSK 1200 bps
0
BELL 212A DPSK 1200bps
000
000
BELL 103 FSK 0-300bps
HLO
V.22 DPSK
2100 Hz
1
2225 Hz
1
1
000
000
0
V.22 without Guard Tone DPSK 1200 bps
1
V.22 without Guard Tone DPSK
0
0
1
V.22 with Guard Tone DPSK 1200 bps
V.22 with Guard Tone DPSK 600 bps
000
000
1
0
BELL 212A DPSK 1200bps
000
1
BELL 103 FSK 0 - 300 bps
HLO
- 1
600 bps
000 : DPSK Demodulator Output
HLO : Hard Limiter Output
2-43
1-21
1.7
Call Progress Detection
The TSG7515 is a single chip 1200 bps (DPSK) and 300 bps (FSK)
voiceband modem. compatible with Bell 212A. Bell 103. and CCITT
V.22 A-B standards.
The device includes transmit and receive
filters implemented using switched capacitor techniques.
A
special mode has therefore been included in the TSG7515 to allow
for the variation of the recieve filter characteristics.
This
mode also features a fast carrier detect to facilitate call
progress detection.
By changing the passband and bandwidth
of
the receive filter it is then possible to monitor the line for
call progress tones such as busy and dial tone.
To select the line monitoring mode. a logic "-1" must be applied
to the RTS input (pin 22).
In this mode the receive filter clock
is directly derived from the TxSCLK input (pin 25). Since in this
mode the center frequency of the receive filters is proportional
to the TxSCLK frequency. it is possible to tune the passband
according to the frequencies to be detected.
Table 1 shows some
suggested clock frequencies that may be used to adjust the
receive filter passband for detection of certain call progress
signals.
Furthermore. the DCD output performs a fast carrier
detection of 3 - 5 mS that is equivalent to an envelope detection
of the call progress signal.
TABLE 1
Originate
TaSCLK
210 kHz
Anlwer
Cente,
p ... b.nd
frequlncy
Passband
It 3 dB
frequency
It 3 dB
2400 Hz
±4OO Hz
1200 Hz
±4OO Hz
510Hz
:85 Hz
Canter
Application
VOice
detection
440 Hz
delectron
45 kHz
260Hz
:85 Hz
440Hz
±150 Hz
330 Hz
dl!tI!ctlon
0lallon8 and
76.8 kHz
Busv tone
defection
It should also be noted that when in the line monitoring mode the
ATO output (pin 16) will only output to the line the filtered
signal from the EXI input (pin 17). In a typical application.
DTMF signals would be input to EXI for tone dialing purposes. and
the TSG7515 would be switched out of line monitoring mode once
the connection had been established.
With these and other
features the TSG 7515 provides the majority· of all the functions
necessary to implement an auto-dial/auto-answer modem.
1-22
2-44
CHAPTER 2 -
2.1
-
DETAILED DESCRIPTION OF V.22 I BELL212A STANDARDS
Foreword
Du~
fact that th~ pr~s~nt application not~ Is primarily Int~nd~d for
not possessing an In-d~pth know/~dg~ of this ·odvanc~a· fi~/a of
t~/~communications, it s~~m~d appropriate to inc/ud~ an ov~rvi~w of th~ most
r~c~nt publications co~ring sp~cificationsof th~ V.22 ana BELL 2121. standard
to
th~
t~chniclons
r~Quir~m~nts.
w~
shall also discuss
lin~ int~rfac~ charact~ristics
ana
r~Quir~m~nts
carri~r d~tection,
together with moau/atar, aemodu/ator,
user
RS-232C) must be appropriately ~mp/oyed - or ~/se, ~Quipm~nt of
manufactur~ will be unable to communicate with ~ach other.
On the other hand, if standara
then a system
implem~nted
reQuir~m~nts
in Japan and
and
anoth~r
which
int~rface
rV.2/j,
aiff~r~nt
ru/~s ar~ prop~rly obs~rved,
in France, will
b~ ab/~
to communicate withollt any difficulty.
2.2 -
V.22 Stondard
Modem
op~rating
Normaliz~d
2.2.1 -
at 1200bits/s In full duplex.
for op~ration on g~n~ral swltch~d t~/~phon~ Iin~s and IRS~d n~tworks.
G~nerol D~scriptlon
This
Mod~m
is
int~ndea
point-to-point leased
op~ration
for
on switched
t~/~phone
networks and
lin~s.
Main characteristics are as follows :
- Duplex
op~ration
on
switch~a
2-wire
te/~phone
ancl point-to-point
leasea lines.
- Frequency division channel
-
Differ~ntial Phas~
assignm~nt.
MOdulation for each channel with on-line
synchronoLls transmission at 600 bauas.
-
Scramb/~r
availability.
- Measurement facilities.
Since the application coverage is wiae, V.22 recomm~naations provid~ for
3 possible configuration voriants. As for as we are conc~rnea, we sholl limit
our discussion to two of these varionts.
2-45
2-1
Characteristics af these variants are as fallows
2.2.1.1 -
2.2.1.2 -
Variant A
1200 bits/s
synchronous
600bits/s
synchronous
Variant B
1200 bits/s
synchronous
600 bits/s
synchronous
j
Variant A
+
2.2.2 -
1200 bits/s
As ync hronous
600 bitsls
Asynchronous
On-line Signals
Carrier frequency and Guard Tone
Frequencies of the operation are respectIvely 1200 Hz! 0.5 Hz for lower channel
aM 21100 Hz! 1 Hz for upper channel. A 1800 Hz! 20 Hz Guard Tone is transmitteo
continuously whenever modem transmits in upper channel. This guard tone must
be disabled when modem transmits in lower channel.
An additional 550 Hz guaro tone may be transmitted for notional applications.
2.2.2.1 -
Levels of transmitted Data Signals & Guard Tone
The 7800 Hz guard tone must be 6 +17 dB below power level of data signals
transmitted in upper channel.
Total power of signal transmittea on-line must meet specifications aefmea
by V.2 recommenaotions :
Total power drawn from line by subscriber
equipment must not exceed 1 mW, whatever
the operatmg frequency.
Note that this power must be identical in both oirections (go & return).
Due to the presence of the guora tone, power level of upper channel signals
is approximately 70B below that of the lower channel signals.
2·2
2-46
2.2..3
-
Fixed delay Compromise Equolizer
This on-chip compromise equalizer is commonly sharea by both transmit
ana receive sections_
Note
This equalizer is mainly intendea to compensate for transmission line
irregularities causea by signal amplitude attenuation and group propagation
delay time
2.2•• -
g: .
Spectrum & Group Propagation Time:.
Signal transmitted on the line must conform to characteristics depicted in the
fonowing Figure.
~.75
~
-D.75
i~
-2
-.
-5
II
:=
=
S
;:
~
-9
-10
i
:IE
..
......'"
<
:;
<
-15
~'
I
i
~
I
II
-2.
1 ill
-25
-6.lI
I
-. 75
!
I, I
!
i
I
I
I
I
I
!
I
i
Ii
1
1
I
1
i
i
1
I
II
!
I
.......
I~\
i1
!
:
\!\
\\
,
I
-,lIlI
-200
i!
-125
125
-OUO
CAR~'ER
Figure 7 -
1
I
I,
I
............... f',...
,
I
: -5DlI: -'50 :
-55l1
II
I
I
I
.........
1 ..........
1/1
'
// : /
>/
i
I
2DlI
,.0i
:
I
I
II
'
:
.00 .SO· 51"'"
415
' OCICI
5~lI
FREQUENCY (H')
Amplitude limits of signal transmitted on-line (without equalization)
The group propagation time of transmitter output signals must fall within
:: 100 lIS limits in frequency range of 800 Hz to 1600 Hz (lower channel) ana
2000 Hz to 2800 Hz (upper channel)_
2-47
2-3
2.2.5 -
Modulation
2.2.5. I - Bit Rate
---As mentioned earlier, we shall only discuss variants A and B of V.22 •
Theon-line transmission bit rate must be either 1200bits/s or 600 bits/s! 0.01\
with a modulation rate of 600 bauds.:!: 0.01' •
2.2.5.2 - Data bits coding
Data stream to be transmitted is split into groups of consecutive 2 bits
called dibits. Each dibit is encoded by considering the relative phase change
with respect to previous phase element of the signal (see table below).
Dibit Value
(at 1200 bits/s)
Bit Value
(at 600 bits/s)
Phase Change
a
00
+90 0
01
00
1
J.1
10
Note
'+270 0
+ 180 0
The phase change is the actual phase shift on-line within signal
transition area situated between the middle of a signal element ana
the mid point of the following element.
Upon receipt, dibits are decoded and recovereD bits arranged in correct
order. The left number of the dibit appears first within the data streams as
they enter modem's demoDulater section located fallowing the scrambler.
The foregoing applies to bit rate of 1200 bits/so In the case of 6CJO bits/s,
each bit is coded by a phase change with respect to the preceding ph.ase of
the signal element.
2.2.6 -
Frequency tolerance of the received signal
The transmitter carrier frequency tolerance is at maximum! 1 Hz and
allowing a drift of
! 6 Hz due to transmission line characteristics. the receiver
mllst therefore be capable of accepting errors at
received frequencies.
2-4
2-48
+
7 Hz tolerance on
2.2.7
-
Connector Pins
The following table gives a list of indispensable and optionol connector pins
used for DTE / DCE Interface.
2.2.7.1 -
Summary of Connector Pins
Pin Number
102
102 a
102 b
103
104
105
106
107
108/1
10812
109
111
Function
Note
Signal Ground or Common return Line
DTE common return line
DCE common return line
Transmitted Data
Received Data
Request To Send
Clear To Send
Data Set Ready
Connect Data Set to Line
Data Terminal Ready
Received line signal (carrier detector)
Bit Rate Selection (DTE originated)
1
113
Transmit signal element timing (DTE source)
2
114
115
125
Transmit signal element timing (DCE source)
3
Receive signal element timing (DCE source)
3
Ring / Calling Indicator
4
140
Test / Diagnostic Loop
!III
Local Loop
142
Test Indicator
Note
This pin is optional.
2
Signals on this pin are ignored when modem not operating in
synchronous mode.
3
This pin is locked on OFF state when modem does not operate
synchronous mode.
..
Used only when modem is connected to public switched telephone
lines.
2·49
In
2·5
2.2.7.2 - Thresholds of Pin 109
Thresholds
of
pin 109 are specifiea at Modem input terminals, ignoring
effects produced by compromise equalizer,
This pin must not react to 1800 Hz Guard Tone ana 2100 Hz Answer Tone
transmitted duringca/f· establishment sequence.
Upper Channel threshold
Higher than - 43 dBm
Lower than - 48 dBm
=>
=>
Pin 109 ON
Pin 109 OFF
Lower Channel threshold
Higher than -43dBm
Lower than - 48 dBm
=>
=>
Pin 109 ON
Pin 109 OFF
The intermediate state of pin 109 between ON and OFF levels is not specifed.
However, the signal level detector must exibit a hysteresis higher than 2 aBo
2.2.7.3 - Pin "1 & Bit Rate Control
The bit rate is selected by
- Appropriate strap or switch settings on Modem Boara
- Using connector pin 111
- Or, combination
of
both.
If used, pin J 11 will in ON state enable 1200 bitsls operation, ana 600 bits/s
in OFF condition.
2.2.7.4 - Electrical Characteristics of Connector Pins
It is advised to respect electrical characteristics specified in V.28
recommendations. Applicable connector and pin spacing requirements are
defineo in ISO 2110 publicotion.
2.2.7.5 - Error Conditions of Connector Pins
Some applications require detection of failure conditions on connector pins,
a summary of whIch is given next.
2-6
2-50
1) - Lack of connection between OTE ana OCE
2) - Open-circuited interconnecting cable
JJ - Short-circuited interconnecting cable
Type I error: Data pins are rill at logic level "I ". Control ana timing pins
are in OFF state.
The OTE must consider an error on pin 107 as being in OFF state.
Similarly, failure conditions on pins 105 ana lOB, are considered as
OFF states by DeE.
2.2.B -
OTE' OCE Interface Modes of Operation
2.2.B.l - Variant A
The Modem may be configured for the following moaes of operation
- 1200 bits's! 0.01"
synchronous
-
synchronous
600 bits's! 0.07\
In these modes, the modem monitors pin 113 or pin
II~
and accepts through
pin 103 the synchronous data originated from OTE. These data are then
scromblea ana forwaraed to the modulator for COding.
In aadition to normal transmit timing element, the modem must proviae
the possibility of deriving the transmit signal element timing from receive
signal element timing.
2.2.B.2 - Variant B
- 1200bits/s!0.01"
synchronous
- 1200 bits/s asynchronous, 8-,9-, 10-, II-bit characters
-
600bits/s!0.01~
-
600 bits/s
synchronous
asynchronous, 8-,9-, 10-, II-bit characters
Synchronous modes are iaentical to those outlined for variant A.
2.2.9 -
Transmitter
In asynchronous moaes, modem accepts asynchronous data stream issuea by
OTE at a nominal rate of 1200 or 600 bps.
2·51
2·7
Asynchronous data are converted into suitable format for synchronous
transmission at 1200 or 600 bps! 0.01\, then scrambled and sent to the
modulator for encoding.
The converter must be configured to accept the following character formats
0) - One start bit, followed by seven data bits ona one stop bit
(9-bit character)
b) - One start bit, followed by eight data bits ana one stop bit
(lO-bit character)
c) - One start bit, followed by nine data bits and one stop bit
(II-bit character)
d) - One start bit, followed by six dota bits ond
(8-bit character)
2.2.1a...
one stop bit
Fundamental Bit Rate
The intercharacter binary bit rate (including start and information bits)
generated by OTE or provided through pin 103, must be 1200
0;
600bits/s
with tolerance fo/ling within + ·1\ to - 2.5\ limits.
When the choracter bit rate falls within the limits of theoretical values
(1200 or SOObits/s) and the maximum value (+ 1\), the asynchronous to
synchronous converter implemented in the transmitter section must suppress,
whenever necessary. the stop bits of the input characters.
Withi" 8 consecutive characters, at most one stop element may be ellminatea.
On the other hand, if the character bit rate falls within the limits of
theoretical values (f200 or SOD bits/s) and the minimum value (- 2.5%), then
the asynchronous to synchronous converter will provide more bits per second
than OTE is generating. As a consequence, the converter will insert additional
stop elements within the transmitted characters.
2.2.10.11 - Higher bit rates
Some Data Terminal Equipment ana Multiplexors exceea the + 1% bit rate
tolerance. The modem musf therefore be capable of accepting data provided
by OTE at 1200 or 600bits/s, tolerance between +2.3\ ana -2.5\. and
consequently suppress at most one stop element per 4 consecutive characters.
2-8
2·52
2.2. II -
Break Si gnal
If the converter detects M to 2M + 3 bits all of which have the polarity of
start bit. where M is the number of bits per character in selectea format.
it will transmit 2M + 3 bits all with start polarity. However. if more than
2M + 3 bits of start polarity are detected. the converter will transmit them
all with start polarity.
2.2.12 -
Receiver
Intercharacter bit rate aelivered to DTE through pin )04 must have a value
between 1200 and 1221 bits/so
For all characters. start and data elements shoula be af identical nominal
length. The wioth of the stop element should not be reduced by mare than
12.5% for fundamental bit rates so as
to allow aetection of any excessive
bit rate caused by transmission terminal equipment.
2.2.12.1 - Break Signal
Received 2M + 3 bits (or more) with start polarity sent by originating mooem
are supplied to pin 104. The modem aetects the transition from stop polarity
to start polarity in order to regenerate character synchronization.
2.2.13 -
Scrambler & Descrambler
2.2.13.1 - Scrambler
The modem includes 0 self-synchronizing scrambler that implements
1+" -III
+" -17 polynomial
generator. This scrambler is integrateo insioe the
transmitter section of the modem.
The data message sequence applieo to the scrambler are divided by the
polynomial generator. The resultant quotient coefficients, arrangea in
decreasing order, represent the data sequence to appear at scrambler output.
The scrambler output data sequence is given by the following expression.
D
= 0.0D
SIS
. ,,-11I 0D
S
. x- 17
Where
Ds ; Data sequence at Scrambler Output
Di ; Data sequence applied to Scrambler Input
o ; Modulo-2 Sum
"" ; Binary multiplication
2·53
2·9
I
ne tol/owing Figure illustrates Scrambler functional configuration.
Note 1: In order to avoid scrambler blocking to cause occasional ana unpreaicteo
occurrence of type-2 loopbock, 64 consecutive binary "l"s must be first
detected on scrambler output (Os) ana only then, the next signal applied to
scrambler input (Oi) will be inverted. This function must be disabled auring
both call establishment and type-2 loopbock sequences.
2.2.13.2 - Oescrombler
Modem's receiver integrates a self-synchronizing aescrombler implementing
the 1 + x -14 + x -17 polynomial. The ooto ·sequence obtained after aemooulotion
must be mu/tiplieo by I +x- 14 +x- 17 polynomial generator so as to obtain
the descrombled message. Coefficients of the regenerotea message, arranged
in decreasing order, represent the 'lata sequence on 0 0 output. This sequence
is defined by the following expression :
Figure below gives Oescrombler functional diagram.
a,_-.....--_..;
I
j
Dora
Output ...
2·10
2-54
Sequence of Operation (Permanent Carrier)
2.2.111 -
2.2.111.1 - Channel , Operating Maae Selection
In public switched telephone lines, the called mOOem receives Oata in lower
channel and transmits in upper channel.
2.2.11j.2 - Operation on switched telephone lines
Timing aiagram below illustrates how initial synchronization is establisheo
between originoting anO answering modem communicating through international
switched telephone networks.
~gnal
tronsm,Urd
on-line
l
I >.,,0,..5
Silent
'nle'1"Y01
j
I
U'! ""ns
I
Woit
155150
ms
-I
1I
ScrCllllblecr
Sinor)' 1
-
O••«lion
'nrenol of
non K' .... blea
..ncr,
I
I
I
110!."ms
t
I
Ooto
I
)is!
''''''5
Wo.t
C,,"newon to I, ••
MODEM IN
I
OetKtlOll
Jntenolof
ORIGINA TE MOOE
scrambleo
I
"n01'Y 1
~~
I
,i
I111.·:.....I __...;,..____
Loc... onto
Dlnary I
I""-f· I
Dora
.
II
MODE""
~I~no'
HOft scramblec
transmltteQ
on-JIM
binary 1 ono
11(.10 Hz
ConM'Ct.on to line
IN
-n:l-
OetectlOll
ms
MUOE
Wort
'ntervol of
scramble-o
tunary 0 or I
~
AN~wER
Ooto at I ~Ult tft
Not. :
Slnory " IS
orlSiinOleO
',om
wortont C
10. lockea onto btndf"y I
0)
A~"''''e'S
thot ConM'ctor pin lOS IIos
~"
I
timor'),
,I
Voto
sWllcheo to ON stote.
2·55
2-11
The following timing diogram depicts the call establishment sequence without
auto-answer capability, as aefinecJ in V.25 recommencJations.
St,ignol
kta-blro
a;nory I
transmit led
Oft-ItM'
Con~chon t o
11M
"OVE"
IN
O~lufNATf
0010
b;d
Detection
Drtection
'ntetwol of
non Kromblro
"nory )
_ ..ary I
WOII
ICrom~'eG
y,
.OVE
m"1
"".!."",,5
"'tervol of
~
locbo onto
&Mnewy I
10'
~)
18...1
I I
or)'
_,"
I
Dat.
I
i
I
I
I
I
Si9f'JOI
Non scramb/ea Dlnary I
x,.ombleCl blftGry I
18,,(1 Hz
'.00 Hz
•
•
Iransmltteo
on-lint'
t
Connect .on to Ime
MODEM
I
Ueteetlon
-!
I
~)
"'- or -"' •
I
MOO£
S-
Note:
I
Bmory " IS
OI'lymoleoo
trom
war,ont C
,(lot
0) Assumes thot
CDn~ctor
2-56
S.,tc~o
,
I
I
locleo onto omary 1
Pin 'US 11m. tJNon
• 't"L/Hz
I
WOlt
tNnary
• 01
AN~wER
2-12
I
16S~'Oms
f==~,:: I
I
IN
270! tOM!.
1>010
to ON stote.
Smory I
Ooto
2.2.14.3- Modem in Originate Mode
Once the originating Modem is connected to line, it must be conaitioned to
receive signals in upper channel by switching the connector pin 107 to ON
state as required by V.25 recommendations. Then, the modem remoins silent
until it detects a sequence of non scrambled "I "5 during on interval of
155:. 50 ms, waits another 456:. 10 ms and then begins senaing
0 sequence
scrambled "l"s in the lower channel. When it detects a sequence
of
of
scrambled
binary" 1lOS for a perioa of 270:. 40 ms in the upper channel, the mOdem
switches connector pin 109 (Received Line Signal) to ON state and then goes
silent for 765:. 10 ms. Then pin 106 (Clear To Send) will react in respunse
to the state of pin 105 (Request To Send).
When pin 106 (Clear To Send) goes to OFF state. pin 103 (Transmitted Data)
will be locked on binary "1 ".
2.2.14.4 - Modem in Answer Mode
Once the answering modem is connected to line, and immediately ofter
answer sequence defined by V.25 recommendations is terminated, the modem
will be conaitioned to receive signals in the lower channel. Connector pin 107
(Data Set Ready) .is switchea to ON state and' the moaem begins transmitting
a sequence of non scrambled binary "I "5. When it detects scramblea binary
"1 "s for an interval of 270 + 40 ms in lower channel, the modem begins
sending scrambled binary "1 lOS in the upper channel, waits 765:. 10 ms and
then switches pin '109 (Data Carrier Detect) to ON state and as a consequence
pin 106 will react in response to pin 105. In the case where pin 106
IS
OFF
connector pin 103 (Transmitted Data) will be lockee on binary stote "1"
The foregoing sequence must be applied whenever two moaems ore connectea
te the line mcnJ.clly cna irrespective of which mooem is connecteo first.
Once the contact has been estobl ish ed, any unpredicted loss and the reappearance
of the signal on line, must not cause the yeneration of another caU
establishment sequence.
2.2.15 -
Measurement Focilities (Maintenance)
The system must provide for both type-2 (local & remote) test loops an"
also type-3 loops, in accordance with V.54 recommendations.
2.2.15.1 _ Type-2 Loopback Establishment
Important: Signals used to establish type-2 loopback may
be transmitteo only after the conclusIOn ot
synchronIzatIOn handshake procedure.
2-57
2·13
As defined in V.S4 recommendations, from now on, the modems will be
called Modem A , Modem B.
When Modem A receives "through
G switch mounted on front pane'" an
instruction to establish type-2 loopback, it begins the transmission of
the initiation signal composed of non scrambled binary "I" elements.
Modem B detects this signal for a(l interval of 154 to 23 I ms and returns
to Modem A a sequence of scrambled alternate "I"s and ·O"s at 1200 bits/s
(or 600 bits/s).
Modem A detects alternate scrambled "I "s and ·O"s during an interval of
231 to 308 ms, ends the .initiation signal and transmits scrambled "I"s at
1200 bits/s (or 600bits/s).
Modem B detects the loss of the initiation Signal and consequently
establishes a type-2 loopback locally.
After the reception of scrambled binary "1"s during 231 to 308 ms,
Modem A informs the OTE that transmission of test messages may begin.
2.2.15.2 - Suppression of Type-2 Loopback
When Modem A receives instruction to remove the type-2 loopback, the
on-line signal transmission must be hoi ted for 77 + 10 ms interval, then
re-initiated.
Modem B detects, signal loss within 171: 7 ms, Signal reappearance within
155 + 50 ms, ana then resumes its normal mode of operation.
2·14
~·58
2.3
-
BELL 272A Standard Description
Previous discussion covered in detail V.22 standard requirements that approach
closely those of BELL 272A standards. In order to ovoid unnecessary repetition
of common topics, we sholl limit our discussion to differences between V.22
and BELL 212A standard requirements.
BELL 272A covers entirely the A ana B variants of V.22 with minor
differences indicated below :
- Variant B has no fallback mode at 600 bits/so
- Character lengths in asynchronous mode are limited to
9 and 10 bits.
Only one overspeed (+ 1\ • - 2.5\) is available.
BELL 212A standard includes a fallback mode called BELL 103.
BELL 10J Characteristics
Modulation Speed : 300 bits/s
Modulation Type
: Frequency Shift Keying (FSK)
Data Transfer
: Asynchronous, through both the RS-2J2C interface
connector and the telephone line.
Frequency
Spectrum
Communication
Bond Division
Full duplex
It differs from its CCITT equivalent in that logic
the high frequency and logic
"0"
"7"
is representea by
by the low frequency of the frequency pair
usee for the modulation.
Differences between BELL 212A .& V.22
- In answer mode, detection of originating mocem's speea.
- During call initiation sequence, the answering modem first senas
the answer tone and then transmits a sequence of scrambled "1 "s
without interruption of carrier signo/.
- Modem disconnection upon the reception of a sequence callee
Long Space.
- Transmission of Long Space to disconnect the cistont modem.
- Absence of 611 consecutive binary "1" ceteetion.
The following timing diagrams show different BELL 212A sequences.
2·59
2·15
BELL 212A LOW SPEED CONNECT !>EQUENCE
CD ON : Either Automatic ar Manual Operation
Set en'"'" Doto Moor ~rl'ter' manuall, ., ., ACU
(T"l 'n'erwal It 1011-100 IR'
ACU)
'ot
"\.1
Coli Or/gi.......
CC \\...._ _ _ _ _~.=.I.
U
ORIGINATING
~TATION
~W~~~~F~----------'"---------.;.I--.;.I.....:....:::::c.:....:
1 1-1:::11 : .~ I ~. ~,
________
T,ansm.rt.. OFF
C'17D Hz)
,_ 7SS.
CB
_---Jntl!rnolly
71. m:jr-I - - - -
I~
II
C/a~ped
~
bYICS
8A
t
I
I
..---C/ompe(l by CF---~Unclamf)e'OL
"
88
I
I
Answers e'ltber automatIcally at Ena of
~"~"-I
ON
TransmItter
OFF
CF
AN~WERING
Dota Rece;ft'(I
,
:+
,
~r
r
,:
I
III
~'.i;:,'~r!~,~:~ 1'''''_DD.l_DDms~~
____
i--
r--:F
STATION
C8
I
_ _ _ _ _ '"tentall)' CIDfftpPG'Y CB _ _ __
8A
_ - - - - - C I . , . " " " b, CF-----~
88
2·16
2·60
BELL 212A HIGH SPEED CONNECT SEQUENCE
CD ON : Either Automatic or Manual Operation
S.r enters Dato .. ~ Manuaf'y
Of' . ,
ACU
/TIH. I....."" • IOG-IOGm. tor ACUI
Call Ori,incrtH
CC
'
ORIGINATING
~r;'-IF
. . :I'- _1_5OI_-,_26_m_._- 1;-.,;.lp-,-,.~.~I~-·- r-.•-•-~-.
II
CF
Tr....
N
mj"...ON _ _ _ _
I lrn--r-
~TATION
:
I
lta
_---Cl. . ".. CF----J E~~~M
_ - - - _ 1.......11' clom"..
SA
SB
b, c s - - - - -..
b,
,
Set A"SW~5 tlthfor Automatically at l the' EnG' of
Rm"ng Cyc'~ or Manually
-
ANSWERING STATION
CS
IA
II
• Pu. il tM 1o_ NnO prtaseo ,"ill At¥tC'
si .... ' •
..."U'"
a marking "ora If'Quence.
PI" is tM .""IIar SI9nol in tu,,, bana.
2·61
2-17
BELL 212A DISCONNECT SEQUENCES ( High or Low Speed)
CD .... I bo OFF oil"., 'or •
",j,,,m,,", 0' SO ,"I Of' WIIH CC
fOeS OFF to guarontee CltKonnecL
CD
+I
...
L
_____________________
57-771-
CC
I
CD DISCONNECT
C8
CF
Car".,
\~J\j
CF
OFF
':0 l=
1
CA~~IER FAIL
I"'Q~ be' us~d
DISCONNECT
wIth long
space chsconnect]
i.....--.OS-.2S ...
CC
==L.
I
L
(;8
SB
Tel. Set
Toll - Data
Lead
Data
Recelft!'CI
/.--CI_'" .~ CF-
-=-1
Tal. Mo«
I
CC
DATA TO
TAL~
I
TRANY'ER
C8
CF
2-18
"'5s..7;;'~J'1=
2·62
I
I
I
BELL 212A DISCONNECT SEQUENCES (continued)
CD
~
I
CF
~~-------------
BS
Data r'------cl."peo.y C F - - - - - _
Recr,..:d
I
LONG SPACE TRANS"'T
BY CD OFF
{ThIs end inItIates d"connrcl
CC
l....--~r
CB
Transmittf:(2====t
I
SS
Date
I
Rt'ce-,W'ol
~ce'
ItKe,f'r'C2
~------
I!-___________________
II
LONG SPACE DISCONNECT
I nil!>
I!nct
dlSCClfIr'(
cc
1·11~~a:7H'_I--------
ts upoft
l'ecei"'"9 long SpGCe-}
I
CB
CF
2-63
2·19
BELL lllA DISCONNECT SEQUENCES (continued)
Carrier
CF
L-c,. .-
B8
by
LONG !J'ACf TRAH~""T
8Y
CAR~/E~
FAIL al!JCONHEC
CC
CS
SA
2·20
2-64
CF-----_
EIA CONNECTOR PIN ASSIGNMENTS
Pin Number
Name
Direction
Function
I
-
-
•
No connection (NC)
2
9A
To Data Set
TransmitteCl Data
3
4
5
6
BB
From Data Set
Received Data
-
-
NC
CB
From Data Set
Clear To Send
Data Set ReaCly
CC
From Dato Set
7
AB
-
Signal Ground
8
CF
From Data Set
ReceiveCl Line Signal Oetector
9
+P
From Data Set
Testing Voltage
10
-p
From Data Set
Testing Voltage
-....
11
-
NC
From Data Set
Speea Moae Indication
..
-
NC
From Data Set
Tronsmit ~ignol clement Timing
(Dota Communication Equipment Source)
...
-
Ne
From Data Set
Received Signal Element Timing
(Data Communication Equipment Source)
To Data Set
Make Busy I Analog Loop
CI
12
-
13
14
15
-
DB
16
-
17
DO
18
CN
....
19
-
20
CD
RL
21
22
23
24
....
CE
CH
....
DA
CN
...
...
or
25
TM
NC
-
NC
To Data Set
Data Terminal Reaay
To Data Set
Remote Digital Loop
From Data Set
Rinq Inaicator
To Data Set
Speea Select - Originate
To Data Set
Transmit Signal Element Timing-Data
(Terminal Eouipment Source)
To Data Set
Make Busy I Analog Loop
--From Dato Set
Test Mode
.
Protective Ground is provided on a screw terminal •
...
Moy be disconnected from interface via options.
2-65
2·21
CHAPTER 3 -
J. 7 -
TSG 7575 APPLICATIONS
Introduction
In this chapter, we sholl .discuss on TSG 75075 -based application implemented
in T!Jomson Semiconducteurs' Application Laboratory - MOS divisioil - EFCI5.
This is a stand-alone application providing for both V.22 and BELL 272A
standard requirements.
Following modes of operation are available
- Manual call mode
- Manual answer mode
- Automatic answer mode
In order to develop a practical configuration in conluction with the sub-section
called line interface (will be explained in oetail later J, the interface useo was
aeliberately selected among those currently.approuved by telecommunications
authorities.
3.2
-
Applicatian Diagram
The complete application diagrom is given ot the ena of this chopter.
- Moaulation - Demodulotion, Transmission - Reception Filtering,
Asynchronous - Synchronous Conversion, Scrambling - Descrambling
Carrier DetectiOn functions are accomplished by TSG 7s.f5.
- A 6805 CT single-chip microcomputer, configured in type 2
open moae, executes the modem management functions.
- The program memory is a 2732 - type PROM containing the
object code.
Since the selected mode of 6805 CT operation uses the available
C and 0 ports for Datn and Address Bus, it was as a consequence
necessary to aad 5 bi-directional po-rts within the area reservea
for this function. This explains the presence of 7/j LS 2/j/j ana
7/j LS 377 devices.
- Interface to the telephone line is implementea by "IRC 2000" of
L TT whose characteristics will be detailed later.
3-1
2·66
Additional detail. concerning the application diagram
- MUX I multiplexor: allows transmission of messages issueCl by the
microcomputer during connection establishment or
loopbock answer sequences.
(Description of software. chapter II. explains the
occurrence of these events)
- OR Gate connected to Pin lOll : Some particular sequences defineCl by V.22
onCl BELL 212A recommendations require the connector
pin 104 to go to logic "I" in response to the state of
V.24 connector pin 109.
- MUX 2 • MUX 3 , MUX 4 Multiplexors: Some of TSG 7515 terminals have
been designed to accept three-state input signals to
perform 3 different functions.
Suitable translation of these three-state signals is.
obtained by applying the two logic outputs to on
analog m·Jltiplexor. Various solutions, two of which
are outlinea next, are possible.
1 - Using a "4000" series CMOS multiplexor (e.g. MC 14052 B)
as shown below (example of type 2 and type 3 loops) •
•sv ~"
ov
.. 5V
I.
Xl
X2
1.)( I
•sv ..... '2
XO
......
.•...
x"
to II •.,..iflol
"
a
OJ
Port Acmrl!'s,!o . 120
This solution has the disadvantage of requiring one MC 14052 B
circuit or equivalent for each J-state input.
2-67
3-2
2 - Using a transistor array as shown below •
• IV
.IV
• --C:J--f
..- •
II
C
.IV -IV
~----------~-.c
tv .IV
.V
.IV .V .SV
.V OV .SV
-SV
This alternative offers the advantage of using currently available
resistor and transistor arrays thereby achieving component count
reduction.
- Purpose 01 adjustable resistors for on-line signal transmission I reception
Telecommunications authorities have establishe"
maximum admissible ('1M-line power level transmitted by
any device. In order to comply with these strict limits,
a combination, of fixed ana adjustable resistors is
used to achieve signal level adjustment.
Resistor briage on receive channel allows aajustment
of complete loop gain so as to enoble the carrier
"etection circuit (internal to TSG 1515) to meet the
requirements of V.22 on" BEL.L. 212A stan"ards
High level : - 43 dBm
Low level : - 48 dBm
3.3
-
on-line
on-line
Modem Configuration Switches
16 programming switches are available - some of them are US~D for the
selection of modem's operational status (Data format, channel selection .... )
and the others for monitoring purposes such as maintenance loop, remote loop
request, ......
A summary aescription of these switches is given next.
2·68
SWO : SRS (Binary Rate Selection)
Selects Data Transfer Rate as fallows
SWO Setting
Binary Rate
J200bits/s
J
600 bits/s (CCITT)
0
300 bits/s - FSK SELL
SW I :
ti
(Loop 2)
Configures the modem for type-2 maintenance loop operation.
Type-2 loop is intended to enable the station or the rietwork to monitor the
error - free operation of both the line (or
0
section of the line) and the
distant moaem.
SWI Setting
SW3 :
TI
Loop 2
I
Deselected
0
Selected
(Loop 3)
Configures the modem for type-J maintenance loop operation.
This is a local analog loop used to test modem's correct operation. It shoula be
as close to the line as possible.
In the case of our opplication, this loop is implementea by disconnecting the
modem from line which will couse on imbalance of Ii-wire 12-wire converter.
(Further details are given later in this chapter)
SW2 Setting
Loop 3
I
Deselected
0
Selected
2·69
SW3 : CIS
Configures the modem for operation in accordance with CCITT V.22 or SELL 212A
standards.
SWIj :
Gr
(Guard Tone)
In CCITT V.22 mode of operation, enables or disables the transmission of
1800 Hz guard tone.
When SW3 is switched to "1" level, a 1800! 20 Hz guard tone is continuously
transmitted while modem is sending in upper channel.
This guard tone is disabled when modem transmits in lower channel.
Transmit Channel
SW3 Setting
Lower
Upper
I
Without
1800 Hz
With
1800 Hz
0
Without
1800 Hz
Without
1800 Hz
SWS : SEI
Scrambler Enable I Disable. Employed for oebug mooe only.
SW6 : AIO
(AiiS"Wer I Originate)
Selection of Answer or Originate mode. This switch affects oirectly the
selection of the transmission channel (lower I upper), other channel being
automatically assigned to reception.
SW7
ill
(Answer Tone Enable)
This switch enables the transmission c;>f the answer tone.
Employed for debug mode only.
SW8 ; IID (Telephone I Data)
Allows to switch between telephone line (TPH) and Mooem (DATA) connections.
3-5
2-70
SW9 : RDL (Remote Digital Loop)
Used to sena loop 2 request to remote modem. This request initiates the
loopback hanoshake sequence.
Signals used for type-2 loopback establishment may be transmitted only
after the conclusion of contact initiation procedure for synchronization.
When a type-2 loopback sequence is terminated and when RDL switch returns
to "0", the modem sends a loopback suppression instruction.
ROl
I·
SW 10
No loopbOCk
I
~,
,I
Loopbock
I
Type 1 LOOPbOCkJ
Hondshokt!'
"
LOOpboC~ ~uppress,onJ
HandShake
AA (Auto Answer)
Enables or disables mocJem configuration for auto answer capability to
incoming calls.
SWII
: Si I A
SW12 : S21 A
1
Synchronous I Asynchronous Mode Selection
SW1J : CLS
SW14 : OSE
1
I~ asynchronous mode, sell'cts the character length ana configures
the mooem for overspeea function.
Table next page gives 0/1 possible configurations.
2-71
3·6
Si I A
S2/A
CLS
OSE
Mode of Operation
0
X
0
0
Synchronous
1
1
0
0
Asyn
9bits C+ J\ • -2.5\)
1
1
0
1
Asyn
9bits C+ 2.3\ • - 2.5\)
1
I
I
0
Asyn 10bits C+ 1\ • -2.5\)
1
I
I
I
Asyn 10bits C+ 2.3\ • - 2.5\)
I
0
0
0
Asyn
Bbits C+ 1\ • - 2.5\)
I
0
0
1
Asyn
Bbits C+ 2.3\ • - 2.5\)
I
0
1
0
Asyn IIbits C+ J\ • -2.5\)
1
0
I
1
Asyn IIbits (+2.3\ • -2.5\)
X : Don't care
Remarks concerning the above table
- When the application board is configured for synchronous
operation, it is strictly forbidden to set CLS and OSE switches
to any state other than
·0".
Any other setting will configure
the TSG 7515 for foctory test configurations.
In chopter 4 (Description of Software) the inclusion of this
illegol configuration is illustrated.
2 - Note that the following configurations are not available in
either asynchronous or BELL lIlA modes of operation
-
CLS
= Bbits
&
-
OSE
= +2.3\
• -2.5\
CLS
= Ilbits
The integrated firmware will alert the user of any illegal configuration.
SW15 : RTS
Disables the dato transmission. Employed for oebug mode only.
3-7
2-72
J.4
-
Terminal Interface
Terminal to Application board interconnection is implementea via a 25-pin
connector (ISO 2110 standards) mounteo on the Printed Circuit Baoro.
This interface meets both CCITT Vo24 I Vo2B ana EIA RS-232C specifications.
CCITT : Comite Consultatif International Tell!graphique et Tfllephonique.
EIA
: Electronic Industries ASSOCiation.
The following table gives
0
list of interface connector pins.
Pin
Number
CCITT
Circuit Number
French
American
Designation
Designation
2
103
ED
BA
3
104
RD
BB
4
105
OPE
-
5
106
PAE
CB
6
107
PDP
CC
7
102
TS
AB
8
109
OS
CF
12
112
-
CI
15
114
HEM
DB
17
115
HRM
DO
20
lOB
CPO
CD
22
125
IA
CE
24
113
HEr
DA
25
1112
IE
TM
2-73
Signal Direction
Terminol_
-Modem
---
o volt
----
-
3·8
3.5 -
Line Interface
This is a hybrid device inserted between TSG 7515 and the telephone line.
In general, it performs the fol/owing functions
- 4-wire 12-wire conversion
- Line current regulation
- Overvoltage protection
- Ring detection
- Pulse dialing
- Telephone I Data switching
- Galvanic Isolation
3.5.1 -
ii-wire 12-wire conversion
This configuration employs on operational amplifier - whose duty is to route
signals issued by the mOdulator towards the telephone line - while preventing,
by as much as possible, the signal reinjection into the demOdulator.
Inversely, it routes the signal received via line towards the demodulator with
minimal attenuation.
Figure below il/ustrates the arrangement of a popular 4-wire / 2-wire converter.
F"om
8uff~r
Output
l rne
'm~tlonce
A]
R}
To banopass F ,. t er
The gain between the on-line signal and modulator's output is
Al=~
R3+ R4
Where R4 is the Line Impedance theoretically considerec as 6000 resistive.
3·9
2·74
If the line is properly matched, R3 must be equal to R4
i.e.
R3
= R. = 6000
therefore : A J = 0.5
The gain between the modulator and the demodulotor (banapass filter) is
given by the following expression :
A2
= _R2
+(
RI
I +~ )
RJ
To obtain a null signal reinjection: A2
.
I.e.
0
=
R2
-Ri
(---B.L)
R3+R.
=0
R2) '21
+ ( 1+ Ri
after simplification:
R2
=
RJ
The goin between the demodulator and the line :
A3
= I+~
RI
therefore:
A3
=2
It is obviously clear that these calculations are purely theoretical. In practice,
the line impedance has a complex component whose value varies as a function
of the frequency. 110wever. the 4-wire 12-wire converter is consiaered as
acceptable if the Gain "A2" is approximately - 10dS.
Further discussion on this topic is beyond the scope of the present application
note. The interested reader is advisee to refer to specialized text books Tor
a full coverage of this subject.
3.5.2 -
Galvanic Isolation
This isolation is achievea by a transformer whose rating should be higher
than I 500 volts.
2·75
3·10
3.5.3 -
Lim: current Regulation
The on-chip regulation circuitry maintain the line current within two limits.
which vary from country to country according to specifications in force.
3.5.4 -
Line interface Device
M OJ(. Current
(mA)
Min. Current
IRC2000
50
20
(mA)
Ring Detection
In general. this output delivers a logic signal corresponding to ring signal envelope.
3.5.5 -
Pulse Dialing
In the case of IRe 2000, this pin delivers loop disconnect pulses for dialing and
mooem connection. In addition, it offers the possibility of telephone connection
disconnection.
3·11
2-76
1St.!---______ ... _ _ _ _ _._ _ __
2-77
3-12
CHAPTER.
".1
-
-
DESCRIPTION OF SOFTWARE
Definition of software madu/es
Each individual module given in this chapter is intendea for a particular function.
They cover the occurrence of events sequentially from the time of modem's
initial power on until the completion of on-line information tronsfer.
".1.1 -
Idle Stote Management Module
- Microcomputer configuration
- V.2. connector initialization
- Interface disconnection fram line
- Read the settings of programming switches. monitor absence
of error and configure the TSG iSIS accoraing to switch
settings.
- Loop 3 management
- Wait for an event causing connection to line
4.1.2 -
CCITT Handshake Module
- V.25 sequence
- Answer handshake
- Originate handshake
4.1.3 -
BELL Handshake Module
- 1200 Originate handshake
-
300 Originate handshake
- Answer handshake
".1.4 -
CCITT Transmission Module
- Telephone line monitoring
(appearance of special sequences)
- V.24 connector m'anagement
- Monitoring several switch settings
- Monitoring
4-1
DCo
terminal of TSG 7515
2-78
".!.5 -
BELL Tra nsmission Module
Identical to preceding CC/TT module. In aoaition, it provides for the identification
of "Long Space" for line disconnection.
".1.6 -
RDL Handshake Module
Protocol used for the initiation of remote loop sequence.
4.1.7 -
Loop 2 Receive Handshake Module
Protocol for the reception of type-2 loopback request initiatea by distant
modem.
2-79
4-2
Idle State Management Module
'DiG 751S T r _...... 0..1,
. , lOOCI D'tcaf!MCt....
.....
All .icroc::cwnllUler . . . ._
,..11.."
'0
l.pouibIro
canh......t'
........ Moor. if IJNn 101
iI_t . . .'atWr
--.
R'IIIOlt 1.ODD R~st
"IIOIoII.....
'nl,.,"
1 IS _I alJowI!'Cl'
HI ""S .Me.lle
~.,
PrDcftl11t9 of BELL.
djl/u}c!
0:)
ConI 'pOllon~
I
• RIA IS "llcrocornj)Ulpr')
Rp9'srl'" .,tt'lln _hie'"
R'"\JI"9StrOllP1
~
I
"'f'stOtt'C'
•
I.~
~:
:'1'
,
-,---,
LJ
T5(' 1515
IL-____________
I
~
4-3
OItSWf"
moor
con1'!JIoI~nI<0I'I
~~
2·80
CC/TT Handshake Module
o
This flowchart illustrates clearly the sequence of events. In the case of manual
answer, the software will ignore the V.2S module.
2·81
4-4
V.25 Sequence
2150",s Silace Interwar
Slop aM. .
'Me' TrCMSlllission
CanMerOf' Sip' ·Oate
s.t
Jl!eof,·
at oc,,"' lew'
Comment
Writing this· sequence meets no difficulty.
Only. CC/TT recommendations must be carefully observed.
2-82
Answer Handshake Sequence
0'
Detection
JC,.....1!'d Is ;15UH' .., 'fle ail''''
Modem lor a period 0' at least 210,"5
Sc,ambfer Enabled
De'ar
Connector pins cDflditiOMCr
Comments
Detection of scrambleo "I" on
RiCi5
terminal for an interval af
270 ms is performed as follows :
The sequence begins within a loop searching to detect a IOf/ic
"I" on 1rxD terminal while simultaneously. a lS-seconc
"time out" is initiatea. If within the loop a logic "0" is
detected on' RXi5 pin. 270 ms count is reset but the "time out"
continues. The software sequence will return to the starting
point (i.e. iale state management). if at the ena of IS-secona
interval a sequence of continuous "I "s for a 270 ms duration
has not been found.
2-83
Originate Handshake
'0
This ;nt~,.t'O' cor,.ftpOIIds
t1~ period durinv .,hieh
fM dlSlont M04I~ Ironsmrls IMJf'I scroml)'ecr
Oelo)'
Connector pin J09 contiDMd
Delo),
Con~tor pin '06 CortditU:If'N
4-7
2·84
-'-i.
BELL Handshake Module
o
NO
2·85
4-8
1200 Originate Handshake
0tc.Ige to
F~
..ooe
Test to .'e'er prftefICe of 2215 HI
D~ar
Transmissiofl of scrc.nb'"
-'·5
Df'tf'CtiOf'l of scrOlllbl" .,., sequlftCl' .,..gfftO.ee
tty Olllant
"'0GetIt
COMf'Ctor confipotl.,
O.'ay
COftMCrOt con(iyw01.OfI'I
Important Note
4·9
on this Module next page
2·86
Important : Sequenc~ of events in 8~" Answer Mod~ diff~rs slightly from
~quivo/~nt
CCITT
sequ~nc~
os follows :
There is no transistion betw~n the transmission of
Answer Tone ana Scrambled -IUs S~qu~nc~.
In the case of TSG 7515 ana upon -the appearonc~ of
scrambled ·I·s sequ~nce. this may result in ·Carrier
DPLL· locking on on incorrect frequency.
An efficient solution to overcome this problem would
be to program the TSG 7515. for a short intervol. in
loop' 3 configuration.
The follawing flowchart illustrates this recammenaed solution.
NE ~ T
2·87
4-10
300 Originate Handshake
Detect... of 1115 Ht
r"""'iaiDft ot JI7tH,
c.n-cror configure••aft
4-11
2·88
Answer Handshake
Ans.er TOM'
FSK
YES
> __",HO,,-_,
DPSK
Tesl 1M
r'G""'USIIOII
$pe'H
of tlte calling station
ConnectIon to F!tIC or Ll~K
Answeor Mooule
2-89
4-12
CCITT Transmission Module
JlETURN
NO
.,.
The Cuty of this module is to monitor either the user connector to detect a
line disconnect sequence, or to monitor the telephone line since programming
switch settings moy cause occurrence of speciol on-line sequences.
4·13
2·90
BELL Transmission Module
<$.r) 1.6,
E>
RCTURN
NO
I
2-91
4-14
ROL Handshake Module
Configuration of the user connector
Dele-ctiOf'! or AM.eor to Utis lil:eotle'st
End of A'DL Rt'CfUft' Signal
anCl trarnsm'sslDf'l o( .ctomblf'G • r·5
Oetpction of li9"O' ·Khopd- by oiston'
an ril) r~",j"al
"OOf'1ft
Confr9UFD1ion
or
tM user connector
Monitoring o( ROL .e-y
TransmIssIon o( loopbod suppresSIon se-qu"'nC'('
4-15
2-92
Loop 2 Receive Handshake Module
De.ect.on at 'rltoe" Ii....' loss
A.IN ..... Loop 2 ena
2·93
4-16
APPENDIX A
- A.7 -
TSG 7575 HANDLING PRECAUTIONS
Power supplies decoupling and layout considerations
Power supplies to digital systems may contain high amplitude spikes and other
noise. To optimize performances of the TSG 7575. operating in close proximity
to digital systems. supply and ground noise should be min(mized. This involves
attention to power supply design and circuit board layout.
The power supplies shoula be bypassea with tantalum or electrolytic type capacitors
to obtain noise - free operation. These capocitors should be located close to the
TSG 7575. The electrolytic type capacitors should be bypassed with ceramic
capocitors for improved high frequency performance.
Power supply connections shoula be short and airect. Grouna loops shoula
be avoided.
COUplin9 between analog inputs and aigital lines shoula be minimizea by careful
layout. The RDI input (pin 13) is extremely sensitive to noise. The connection
between this point and RFO (pin 14) thraugh a ceramic type capacitor should
be as short as possible and coupling between -this connection and digital signals
should be minimized by careful layout.
A.2 -
Carrier Recovery Loop
The carrier recovery loop utilizes a digital phase-/ockea loop. Performances of
the TSG 7515 depend airectly on this DPLL which neeas to be reset prior to
the reception of a DPSK carrier.
TSG 7515 offers three possibilities of resetting this DPLL
- A trailing eage on
i5C5
terminal
- Switching fram FSK mode to DPSK moae.
- Changing the receive channel
These three possibilities of resettmg the DPLL shoula be integratea within
the microcontroller so as to proviae for various set-up ana hanashake procedures.
Timing diagrams given in chapter 2 illustrate examples of V.22! V.2S ana
BELL 212A received signals in originate mode.
A-1
2·94
A.3
-
Frequency Precision of Crystal Oscillatar
In order to meet the frequency precision of the transmission baud rate requirecl
by V.22 and BELL 212A specifications. it is recommended to use a crystal
oscillator whose series resonance frequency preciSion is better than c.I}!\ with
respect to the theoretical frequency of •• 9152 MHz.
Such precision would be feasible by optimizing the capacitance values spread
around the quartz oscillator.
2-95
A-2
APPENDIX B
-
GLOSSARY OF TERMS
Acoustic Coupler : A device that permits the use of a telephone handset as a
connection to dial-up telephone lines (rather than a direct connection using DAA
interface) for data transmission by means of sound transducers. Usually
implemented for call origination, and is frequently used with portable terminals.
Analog Loopback : A diagnostic mode whereby the transmitted analog output is
internally conne£!ed to the analog 'received Signal input in a single bond
(determined by AID pin) so that the device's entire Signal' path is under test.
Answer Tone : A tone returned by the answering modem to the originating modem
and the network.
A SCI I ; A merican Standard Code for Information Interchange. This is a seven-bitplus-parity code established by the A merican National Standards Institute
(Formerly American Standards Association) to achieve compatibility between
data services. Also called USASCII.
Attenuation: The difference between transmitted and received power due to
transmission loss through equipment, lines or other communications devices.
Asynchronous Transmission : A data transmission scheme that handles data on 0
character-by-characterbasis (without synchronization by a clocking signa/).
Time intervals between transmitted characters may be of unequal length. The
character code includes a "start" bit to identify the beginning of a data
character, a "stop" bit (or bits) to identify the end of the data character
and a "parity" bit to check for errors in transmission. Also called "Start-Stop"
transmission.
Auto-Answer; A 'circuit in a m'odem system that can automatically make a connection
on the switched telephone system when its number is dialed.
Automatic Dialer: A device which will automatically dial telephone numbers on the
switched telephone network. An automatic dialer can be easily incorporated
into a TSG 7515 - basea moaem system.
Bandpass Filter : A filter circuit that posses a single bond of frequencies and filters
out, or excludes, all others.
Bandwidth : The range of. frequencies assigned to a channel or system; the difference
expressed in Hertz (Hz) between the highest and lowest fr~quencies of a bond.
Baud: A unit of signolling speed equal to the number of modulations or signal events
per second. In' FSK synchronous transmission, the unit of signalling speed
corresponding to one unit interval per second; that is, if the duration of the
unit interval is 20 milliseconds, the signalling speed is 50 baud. Baud is the
same as "bits per second" only if each signal event represents exactly one bit,
as in the frequency-shift keyed TSG 7515 modem.
As used in the TSG 7515 four-phose PSK transmission, every two bits of digital
data are encoded into dibits (Idibit = two bits) for translation or modulation
into phase shift information. II'l PSK the baud rate is one-half the bit rate.
Bit Error Rate (BER) : A measurement of the overage number of bits transmitted
before an error occurs. Usually expressed as the reciprocal of the overage.
B-1
2-96
GLOSSARY OF TERMS (continued)
Bit Rate : For modems using voicegrade telephone lines, the bit rate equals the data
rate. The baud rate is the actual number of times per second that the transmited
carrier is modulated or changes state. Each modulation may represent multiple
bits.
Carrier: An analog signal fixed in amplitude and frequency that can be combined in
a modulation process with a second information-bearing signal to produce a
signal for transmission.
C CIT T (Comite Consultatif International de Telegraphie et Telephonie) :
An international committee established by the United Nations to recommend
international telecommunications standards of transmission within the International
Telecommunications Union (ITU).
Channel: A communications path providing signal transfer in a single direction
at a time.
Circuit Grade : The grades of circuits are broadband, voice, sub-voice and telegraph.
Circuits are graded on the basic line speed expressed in characters per second,
bits per second, or words per second.
Coherent Detection: A method of phose-shift detection, used in the TSG 7515
PSK modem, in which the received modulated signal is compared with a purified
and locally-generated reference frequency, instead of using the instantaneous
value of the received carrier frequency (which is often distorted).
Common Carrier: A company which dedicates its facilities to a public offering
universal communications services and which is subiect to public utility regulations.
DAA
(Data Access Arrangement) : Originally this term was used to define a device,
provided by the telephone company, which was used to connect privately owned
or customer provided equipment (data sets) to the switched telephone network.
dB (Decibel) : The decibel is defined by the ratio of output signal power to input
signal power as dB = 10 .. Log 10 (Output Power).
Note that if the output power is less than the input power, the logarithmic
result is negative. In this cose the line is said to have a loss of that many dB.
dBm : Input and output signal powers may be related to a specific level called a
dBm for reference purposes. Zero dBm (log 1 = 0) equals lmW dissipa~ed in
600 D impedance. The reference frequency used in most circuits is 1000 Hz.
Measurements relative to reference frequency are expressed in decibels relative
to 1 mW as follows:
dBm
= 10
.. log 10 (Signal Power in mW/lmW)
Thus, zero dBm means lmW and absolute power levels may be expressed as so
many dBm.
dBSPL : In acoustics, the unit commonly utilizeCl to measure sound pressure level or
dBSPL. The zero reference for this measurement .is 0.0002 dynes per square
centimeter.
2-97
B·2
GLOSSARY OF TERMS (continued)
dBv : Microphone sensitivities are commonly related to a specific level called a dBv
for reference purposes. Zero dBv (log I
0) represents one mW dissipated in
1000 n impedance. The unit dBv is expressed in terms of the peak voltage of
a signal referenced to one volt.
=
dBv = 20
*
log 10 (Peak Voltage of Signal I 1 volt)
D C E (Data Communications Equipment) : Consists of the modem and any other
equipment related to the transmission or reception of analog signals over the
telephone lines, such as the FCC-approved Registered Protective Circuit.
Data Set ; - A modem,
- A collection of similar and related data records.
D T E (Data Terminal Equipment) : The digital equipment to which a data
communications path begins or ends.
Demodulator ; A component of a modem which recovers data from received analog
signals and converts them to a form suitable for the DTE.
Descrambler ; A Clevice or circuit that transposes or decodes a demodulated signal
to restore the original Clata prior to transmission by the remote transmitter
and scrambler.
Digital Loopback: A means of routing data from the transmit path bock to the
received Clata path by switches, as a means of testing a modem.
Equalization ; Compensation for the increases of attenuation with frequency. Its
purpose is to produce a flat frequency response.
F SK
(Frequency Shift Keying) ; A method of frequency modulation which varies the
carrier frequency at significant instants by smooth as well as abrupt transitions.
Full Duplex ; Simultaneous two-way independent transmission -in both directions on a
communications channel. Also called Duplex.
Cross Distortion; Distortion is on undisred change in a signal or data transmission.
The primary sources of distortion in moaem communication are in speed
differences between the Data Terminal Equipment (DTE) ana the moClem, ana
cirCUit variations and noise. The maximum gross (totall distortion in modem
communication is 45%, as defined by E/A stanClard RS-404.
Half Dvplex ; A circuit designed for transmission in either direction, but not in both
directions simultaneously. A modem in half-duplex moCle will be either transmitting
or receiving, but not both at the same time.
Handshaking; An exchange of predetermined signals when a connection is established
between two modems.
Host Computer; A computer attached to a network providing primary services such
as computation, data bose access, special programs, or programming languages.
Information Bit; A bit generated by the data source which is not used for error control.
Impulse Noise or Surge; A type of high-amplitude short-durotion interference on
communications lines caused by events s/Jch as lightning, electrical sparking action,
make/break action of switching devices, or electrostatic aischarge. A registered
protective network is required to protect the modem from such voltages which
occur on communications lines.
B-3
2-98
GLOSSARY OF TERMS (continued)
Mark : A logic one, or the presence of current or carrier on a digitol communications
chonnel in the idle condition. Compare with space.
Parity Check: Addition of non-information bits to data, making the number of ones
in each group either always even (for even parity) or odd (for odd parity).
This permits single error detection in each group.
Phase Locked Loop: An electronic servo system controlling an oscillator so that it
maintains a constant phose angle relative to a reference signal source.
P S K (Phose-Shift Keying) : A type of phose modulation in which the maculation
function shifts the instantaneous phase of the modulated wave between predeterminea
discrete values.
Protocol: A procedure used to control the orderly communications between stations
on 0 doto link. Examples of protocols are HDLC, SDLC, and Synchronous
Bit-Oriented protocolS.
Q A M (Quodrature A mplitude Modulation) : One form of 4-level differential
Phose-Shift Keying.
Reference Clock: A clock of high stability and accuracy used to govern the frequency
of a network of mutually synchronized clocks of lesser stability.
R D L
(Remote Digital Loopback) : A type of test in which a signal is transmitted
from a local modem to a remote modem, or other device or switch, to loop the
remote received data bock to the sending modem to measure or test the modem,
communications line, remote modem or device, or the entire circuit.
Scrambler: A device or circuit that encodes a data signal at the !ransmitting modem,
to make it unitelligible for data security purposes (at a receiver not equipped
with on appropriate descrambler), and to maintain carrier detect lock during idle
or slow data rate input.
Serial Transmission: A method of transmission in which each bit of information is
sent sequentially on a single channel, rather than simultaneously on several
channels, as in parallel transmission.
S N R (Signal-to-Noise Ratio) : The ratio of the signal power to the noise power on
o communications line, expressed in dB.
Space : A logi c zero, or the absence of current or carrier on 0 dIgital comm unications
channel. Compare with Mark.
Start Element : In character synchronous (stort-stop) transmission, the first element
'in each character, which serves to prepare the receiving equipment for the
reception and registrotion of the character.
Stort-Stop Transmission: Asynchronous tronsmission in which a group of code elements
are preceded by a start element (or bit) and ended with a stop element (or bit).
Statistical Equalizer: A modem compensation circuit which provides equalization of 0
communications line based on the averoge switched telephone line cirCUIt
distortion.
2-99
B·4
GLOSSARY OF TERMS (continued)
Stop Element : In character asynchronous (start-stop) transmission, the lost element
in each character, to which is assigned a minimum duration, during which the
receiving equipment is returned to its rest (idle) condition in preparation for
receiving the next character.
Switched Line : A communications link for which the physical path may vary each time
it is used, as in the dial-up (switched) public telephone network.
Synchronous Transmission : A data transmission scheme in which the data characters
and bits are transmitted at 0 fixed rate with the transmitter and receiver
synchronized. This eliminates the need for start-stop elements, thus providing
greater efficiency.
B·5
2·100
APPENDIX C
-
BIBLIOGRAPHY
- American Telephone and Telegraph Company
Bell System Reference Data Set lIlA Interface Specifications
PUB 41214 - January 1978
- Comite Consu/tatif International Te/egraphique et
Te"~phonique
Communicatians de Donnees sur Ie Reseau Te/ephonique
Avis cJe 10 serie V
Geneve Novembre 1980
- Thomson SemiconcJucteurs
EFG 7515 Advance Information Data Sheet
- Electronic Industries Association
EIA Standard : RS-l3lC Interface between Data Terminal Equipment and
Data Communication Equipment Employing Serial Binary
Data Interchange
August J969
2-101
C-1
2·102
COMMUNICATIONS PRODUCTS
Designed to interface an equipment with the telephone line, this
8 pins IC provides:
• Line adaptation.
• Ring detection.
LINE INTERFACE
It is particularly convenient for modem applications and fulfills a
wide range of international specifications.
Line adaptation: (DC characteristic)
• Zener characteristic with adjustable slope.
• Adjustable.dynamic impedance.
• Adjustable maximum amplitude of the signal.
• Use only a low cost dry transformer.
• Need no dialling relay.
CASECB-98
Ring detection:
• Adjustable detection level.
• Adjustable AC impedance.
• Very low line distortion.
• LogiC signal output.
Other:
• Low working voltage.
• Wide operating current range.
PLASTIC PACKAGE
PIN ASSIGNMENT
BLOCK DIAGRAM
UNO
2-103
PIN DESCRIPTION
VOLTAGE STABILIZER
Name
No.
Description
V,
,
Voltage over the Ie
Ve
2
CVST decouples the voltage stabilizer and RVST fixes the impedance
Re
3
Re fixes the voltage through RVST
RM
4
RM fixes the slope of the DC characteristic
GND
8
Ground
RING DETECTOR
Description
Name
No.
VR
5
Ring detection output connected to an optocoupling device
RS
6
RS fixes the ring detection level
RD
7
Ring detection input. RD fixes the impedance of the ring detector
Outlines
Line adaptation
Specially designed for the modem applications, this
8 pins IC provides line adaptation, ring detection and
easy pulse dialling. It is a Direct Connect Circuit
(DCC) which has been designed to fulfill a wide
range of AC and DC specifications for various
countries.
The DC characteristic can fulfill a wide range of DC
specifications:
- zener characteristic with adjustable slope fixed
by an external resistor,
- line current limitation using an external CTP.
Ring dectection
This circuit detects the incoming ringing signal and
generates a logic signal to the microcomputer via an
optocoupling device. The detection level can be fixed
by an external resistor. The dynamic impedance of
the ring detector is also fixed by an external resistor.
The line distortion of the ringing signal is very low
compared to the distortion introduced by a zener
detector.
2-104
The dynamic impedance is fixed by an external resistor RVST so as to match with different line impedances.
Th"e maximum amplitude of the signal is fixed by two
external resistors RVST and RC'
This circuit has been designed to be connected to a
low cost dry transformer.
The appl ication has been studied to avoid the use of
dialling relay.
With its possibility of ring detection, off-hook and
dialling this circuit is adapted to the application in
smart modems. Is also satisfies the FCC Rules Part
68.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VI
16
V
V7
16
V
Ptot
600
rnW
Toper
-25to+65
'C
Supply voltage
Power dissipation
Operating temperature
Tstg
Storage temperature
-
55 to + 150
'C
STATIC ELECTRICAL CHARACTERISTICS:
lamb = 25°C
Characteristic
Line current (Pin 1)
Max.
Unit
120
rnA
3
4.5
-
V
V
2.1
-
V
Unit
Symbol
Min.
IL
10
Typ.
-
-
Voltage over the IC (Pin 11
See note 1
IL = 10mA
I L =l00mA
VI
VI
-
Voltage stabilizer (Pin 21 See note 1
IL = 10mA
Vc
IL=l00mA
Vc
-
Symbol
Min.
Typ.
Max.
R.L.
15
-
-
3.5
V
DYNAMIC ELECTRICAL CHARACTERISTICS:
lamb = 25°C
Characteristic
Impedance of the transmission part.
See note 2
Return loss compared to 600 0:
300 Hz < f
< 5 kHz
Ring detection level (See note 3)
For a low level on pin 5 « 0,3 V)
: no detection
For a high level on pin 5 I> 0.8 VI : ring detection
dB
Vpp
VR
-
18
20
-
20
22
9.5
10.5
11.5
kn
-
-
-
-
Impedance of the ring detection part:
Typically RS + RD /13 (See note 31
ZR
Distortion in ring mode: f Ring = 50 Hz
(See note 41
2·105
Note 1: Static electrical characteristic test diagram:
TEA 7868
External components:
CVST = loopF
RC = 2.7 kCl
for: IL = 10 mA
Vl = 3.2 V
and Vc = 2.1 V
RVST= 1.2 kCl
RM = 12 Cl
for: 'L = 100 mA
Vl = 4.5 V
andVC = 3.4 V
Test conditions:
2-106
Note 2: Impedance measurement:
External components:
=
CYST 100pF
RC= 2.7kn
RVST= 1200n
RM=12n
Return loss is defined by:
R.L. = 20 log (
RPL= 1200n
Test conditions:
IL =20mA
- V1
l out-.IL
2·107
Ilout
Ilout
+ 6001
-
6001
Note 3: Ring detection part:
5.6 kll
10 kll
Test conditions:
• Impedance of the ring detection part:
• Ring detection level
for: VR
for: VR
= 18 Vpp
=22 Vpp
V(5) <0.3 V
V(5»0.8V
2-108
Note 4: Ring detection distortion:
10 kn
5.6 kn
2.2 kn
SPECTRUM
ANALYZER
RL
VR
fR ;50 Hz
No distortion peaks appear in the forbidden area of
the following shape:
Test conditions:
300n'-:-j__.....
12V
ELC
TEUPHQNE
SET
CPU _.
RING
DETECT
R4
SDkO
CPU
AI. A2: LM358
COMPLETE DAA INTERFACE CIRCUIT WITH TEA7868
2-114
PHYSICAL DIMENSIONS
CB-98
PLASTIC PACKAGE
{II Nomil'llldirnention
(21 TrulflO"'Ml1ricll poIitlon
8,i..
,
DIN
C8-98
ASOD
e"
o.... ,r. ... ,
2·115
2·116
MODEM APPLICATION COVERAGE
---------------r
,
V22 bls
Digital signal Processor
DSP
t--1-X-T"'S"'7'-5-2-4-0--i
2400 bps
-+
----BELL 208 (V27) HD
I
I
'L______48~0 bps
I
I
BELL9260g0(~p2;) HD
AF"--E_ _ __
1 x TS 7542
1
x
TS 68930
I
1 x TS 68951 Transmit
1 x TS 68951 Receive
1 x TS 68952 LogIc
1
1 x TS 68950 Tran. smit
1 x TS 68951 ReceIve
1 x TS 68952 LogIC
x
TS 68930
+______
I
1 x TS 68950 Trgnsmit
1 x TS 68930
I
~--- - · - - - - - - - - - 1 - - - - - 4800 bps
1/32 FD/EC
9600 bps
I
Fast RAM
256
16
i
Fast RAM
I
x
~_____ _ _ _ I
1
V26 1er FD/EC
V32 FD/EC
_
1 x TS 68930
1 x TS 68951 ReceIve
2 k x 16
____________~--='-'x:"..:.TS:.-=6-=8.~9-=5-=2-L-o--"g'-iC--__1_--- ________ -1
(14.4 bps)
2400 bps
i
--_I
---------~----------+-'-1.::x-=T=-S:..6=-8=-9=-5::-:0::-::T-'ra'-n·---s-m-::it--I
1
I
circuits
1 X TS 68951 Receive
1 x TS 68952 Logic
1 x TS 68930
:
V33 HD
----
Additional
l'~-s-68950 -Tr~-~;~it--'
---L--.-..-
BELL 201 (V26) HD
-----
Analog front end
i
I
1
x
TS 68930
__
3 x TS 68930
I
1 x TS 68951 Receive
Fast RAM
1 k x 16
~ :~: ::::-:..~:......~~..,:~~c=-sm-it---'f---
Fast RAM
--------1
l--_',--"X-,T-=S"6,,,8:,,9:,,5:,"':.:::R~ec':.e=_iv_·
2_k_X
1 6 _.____1
1 x TS 68952 Logic _ _t-_____
_
1 x TS 68950 Transmit
RAM
I
1 x TS 68951 Receive
Fast .
2 k x 16
I
1 x TS 6S,952 _t,c>!l~ __L -___________________ .."
2·117
2-118
----
TS 7524
--~~-
V 22 BIS V 22 BELL 212 / V 23. V 21. BELL 103
CHIP SET
ADVANCE INFORMATION
• DSP (TS75240) and Modem Analog
Front-End (MAFE-) implementation.
COMMUNICATIONS PRODUCTS
• Programmable transmit level.
• On-chip 4/2-wire hybrid function.
• QAM, DPSK and FSK Modulation
and Demodulation.
• Answer tone detection and generation for
CCrrT (2100 Hz) and Bell (2225HZ)
Standards.
• Auto-adaptalive Equalization.
• 550 Hz and 1800 Hz guard tone
generation.
• Transmit and Receive Filtering.
• Sharp adjacent channel rejection.
• Versatile high periormance Analog
Front-end (MAFE-).
• DTMF Tone Generation.
• Data transmission speed:
• Scrambler and Descrambler selection.
• Call progress tone detection.
• 2400 bps in QAM
• 1200,600 bps in DPSK
• 1200,300,75 bps in FSK
• 64-space detection feature .
• Supply voltages:
±
5 V.
r----..,I
I
MAFE
I
I
ATO
SYSTEM
SUS
AOO-AD7
T
S
7
RAI
5
2
Ci
I
I
I
I
4
Rs
0
SRM
iDs
;;;0
I
I
L_
I
I
I
-~
T.rm,n_ICloc:k
TS 7524 BLOCK DIAGRAM
- MAFE refers to TS6895D. TS689S1 and TS68952 devices (see appropriate data sheets).
These specifications are su'bject to change without notice.
2-119
CHAPTER 3 - DIGITAL SIGNAL PROCESSORS
& PERIPHERALS
TS68930 • TS68931
--.--~~-
PROGRAMMABLE SIGNAL PROCESSOR
MOSTEK
ADVANCE INFORMATION
HMOS2
The TS68930/1 (Programmable Signal Processor) is a high-speed
general purpose signal and arithmetic processo'r with on-chip
memory, multiplier, ALU, accumulators and I/Os. It is organized in
a parallel/pipeline structure to execute simultaneously one ALU,
function, multiplication, two reads and one write operation and
associated address calculation every 160 ns.
o
o
o
o
o
o
o
o
o
o
o
Parallel/pipeline Harvard architecture
3 data-bus structure
3 data types: 16-bit real, 32-bit real
: 16 + 16-bit complex number
2 versions: TS68930 (internal ROMs) 48-pin
: TS68931 (external ROMs) 84-pin
Pipeline complex multiplier
2 x 128 x 16-bit RAM
512 x 16-bit coefficient. ROM
32-bit instruction bus
64 k x 32-bit external program space
68000 family compatibility
Dual external buses : local/system
PROGRAMMABLE
SIGNAL PROCESSOR
CASE CB·229
T868930
P SUFFIX
PLASTIC PACKAGE
TS68931
E SUFFIX
LCCC84
PIN ASSIGNMENT
TYPiCAL APPLICATIONS
03
02
01
o
o
•
o
o
o
o
o
•
o
o
•
DO
Adaptive processing
Complex numbers
Digital filtering
Fast Fourier transform
Voice grade communication systems
High-speed modems
Speech processing
Audio Frequencies
Sonar f radar
Image processing
Robotics
Graphics processing
BE3
BE4
BSO
BSI
BS2
All
013
014
015
VSS
XTAL
EXTAL
vec
Al0
A9
AS
AD7
AD6
AD5
AD4
AD3
AD2
ADI
CLKOUT
OS
RIW
SRM
sl5!I
CS
AS
ADO
REm
BE5/BA
IRQ'L._ _ _,BE6/DTACK
TS88930
3-1
TABLE OF CONTENTS
Page
Number
Paragrap;.,
Numbe.
1.1
S4iCIIon 1
Block dIag.....
5
2.1
SectIon 2
PIn cklscrlpIIon
7
3.1
Section 3
.Summary of ....., "'rdwoIre
8
SectIon"
Architecture
10
4.1
4.1.1
Internal architet1ure
Parallei processing
4.1.2
4.1.3
Three-bus
4.1.4
4.2
4.2.1
4.2.2
10
10
10
10
10
5otructUf8
Wide instruction word
Pipeline
13
13
13
Ext.",.1 architecture .
System bus
Local bus
Section 5
functional d....,rlptlon
5.1
5.2
Control block
5.2.1
Instruction ROM
Program Counler
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.4
5.4.1
5.4.2
5.4.3
14
14
14
14
14
15
15
16
16
Operating modes
5.2.2
5.2.3
5.2.4
5.2.5
5.3
Sequencer
Return Address Register
Loop Counter
Processing block
Multiplier
Barrel shifter
Alu
Saturation mode
Status register
Accumulators
Fifo
Replace Code register
Transfer register
Memory block
17
17
17
18
19
19
20
20
21
21
21
21
Data memories
Addressing modes
Address calculation units
Pointers
5.4.4
14
22
5.4.5
Circular addressing mode
22
5.4.6
Ocld/.""n address
5.5
Access mode register
5.6
Reset
23
23
25
5.7
Halt
25
3·2
TABLE OF CONTENTS
(continued)
Paragraph
Number
Page
ntle
Number
Section 6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Input-Output
26
Dual-bus interface
Masterlslave
Local bus
System bus and mailbox ................................................... .
Mailbox protocol ......................................................... ..
Instruction bus ............................................................ .
Application eX(lmples
26
28
28
29
30
31
32
Section 7
Instructio'1 set
7.1
7.2
7.3
36
37
41
42
Operating code formats
Alu codes
Test conditions
Section 8
Performance BYaluation
Section 9
Electrical apecifications
9.1
9.2
9.3
9.4
9.5
9.6
Maximum ratings ........................................................ .
DC electrical characteristics ............................................... .
AC electrical specifications· clock and control pins timing .................•...
AC electrical specifications - Local bus timing .............................. ..
AC electrical specifications - System bus timing ...................•.•........
AC electrical specifications - Instruction bus timing ...•.•••••••.•••..•..•.••..
Section 10
Pin assignments afld
mechanical data
10.1
10.2
11.1
Pin assignment
44
44
44
44
46
47
48
49
50
51
Package dimensions
SactJon 11
Ordarlng Informadon
3-3
52
3-4
L-BUS
11
1
16
8
R-BUS
M
1
!
16
RIN
DTACK
N
MULT
15x16.,.32
V16
16
16
16
~
iROJ
MAILBOX
RS
CONTROL
SR/W
P
~~
ST A
Co)
en
r
~
cP1
Z-BUS
ROUT ,+~
16
~
~
~
2l-
YACU
Y
RAM
128 x 16
X
I
t4
RESET
---y;-
-y--
OC
u
:i"-
-,
~
I
4
BSOBS2, BE3-BE6
I
BRANCH CONDITIONS
C
ROM
512 x 16
Jtz
IR
ir
IROM
1 28K x 32
12
ECACU
Os
EO
~~
8
"-
INSTRUCTION BUS
II BUS}
TO ALL BLOCKS
I
rR/W
ABc!'IJ
~
CI ET
I
I
11
~
--yo
I
J--
16
C
EXfAL CLKOUT
c:c
4
X
RAM
128 x 16
SED
SDS
ADO-AD7
8
8
T
15
XT~L
1
SYSTEM
BUS
db
00015
LOCAL
BUS
OC/)
Om
"'0
2g
~Z
:0 .....
»
~
3-6
SECTION 2
PIN DESCRIPTION
LOCAL INTERFACE
Nama
Pin
Pin "b. Pin nb.
Type TS68930 TS&8931
D 10:15)
liD
45-48
A 18:111
DS
0
0
R/W
CLKOUT
Oeacrlptlon
Function
6-21
Data bus
Can be concatenated or separate 0 !0,71, 0 (8:15)
35_37;39
45-48
Address bus
17
18
27
Data Strobe
High order addresses for local interface
Synchronizes the transfer
0
28
Aead/write
Indicates the current bus cycle state
0
16
26
Clock output
The frequency of CLKOUT IS one half the frequency of the Input clock or
crystal
1-11
SYSTEM INTERFACE
Nama
Pin
Pin "b. Pin nb.
Type TS68930 TSII8931
AD 107)
1/0
27-34
35-42
Function
OHcrlptlon
System data bus
or
local address bus
The data exchanges between the processor and a master via a maIlbox
is the function of thiS bus. It IS also used to generate the addresses of an
external RAM
CS
I
21
31
Chip Select
Used by a master to gain access to
AS
I
22
32
Register Select
Used by a master to gain access to the mailbox and system bus
SDS
I
20
30
System Data Strobe
Synchronizes the transfer on the system bus
SR/W
I
~9
29
System Read/Write
DTACK
0
25
43
Data Transfer
Acknowledge
Indicates the current system bus cycle state
Indicates that the processor has recognized It IS being accessed
BA
0
0
26
44
Bus Available
Indicates availability of system bus to master
24
34
Interrupt Request
Handshake Signal sent to the master to gain access to the mailbox
IRO
the mailbox and system bus
EXTERNAL BRANCH CONDITIONS
Nama
Pin
Pin nb. Pin nb.
Type TS68930 TS68931
8S 10:21
8E {3:6)
I
I
42-40
44
43
26
'5
49-51
Function
53
Oucrlptlon
I
Branch on State
Branch on Edge
52
44
External conditions
External conditions
B E5 shares pin with
BE6 shares pin with
Can be programmed on a high or low state
E!!i!ing edge is memorised and reset when tested
~
I
DTACK
43
OTHER PINS
Nama
Pin
Pin nb. Pin nb,
Type TS68930 TSII8931
Function
EXTAl
I
15
XTAL
I
14
24
VDD
I
38
23-65
Power supply
VSS
I
Ground
I
13
23
22-64
RESET
25
33
O.. crlptlon
Clock
Crystal Input pin for internal oscillator or input pin for external oscillator
Clock
Together with EX TAL it is used for the external 25 M Hz crystal
Reset
INSTRUCTION INTERFACE (TS58931 only)
Name
I 10311
Pin
Pin
Type
nb_
1/0
1-5
56-83
56-84
HALT
INCYCLE
I
54
0
05
Function
DBlcrlption
Instruction
Address/data bus
Coefficient ROM
address bus
Instruction bus - 32-blt data
Instruction address - fi16 - 131)
External coefficient ROM address - (l6 - 115) lO-bit
(9-blt address + output enable signal)
Hal! Signal
Instruction
cycle clock
Hails the processor. ThiS signal freezes the program counter and loop counter
160 ns in REAL mode
320 ns in CPLX/DBPR Mode
3-7
SECTION 3
SUMMARY OF BASIC HARDWARE
OPERATING MODES
function
Reaource
2-bit register defining the operating mode 'real/complex/double precision).
Mode register
CONTROL BLOCK
Ruouree
Instruction ROM
'aragraph
function
Symbol
N°
5-2-1
IROM
1280 x 32-bit word read-only-memory containing program code and imme-
IR
32-bit register containing instructior..
16-bit register containing address of program memory.
diate data.
Instruction register
Program Counter
Sequencer
5-2-2
5-2-3
PC
5-2-4
5-2-5
RAR
LC
SEQ
The sequencer can test directly 16 conditions programmed on a high or low
state.
Return Address Register
Loop Counter
16-blt register for saving program counter in case of subroutine call.
Lei
15-bit register containing a control word for automatic loop. It is divided as
follows
4-blt register containing the number of instructIOns to be executed in the k>op.
LCR
B-bit register containing the number of loops.
LCD
3·blt register containing the number of instructions between declaration and
stan of the loop
PROCESSING BLOCK
RHourc8
Paragraph
5-3-1
Barrel Shifter
5-3-2
5-3-3
Arithmetic logiC Umt
Status
5-3-4
5-3-5
Accumulators
5-3-6
Fifo
5-3-7
Saturation
Symbol
N°
Pipeline Multiplier
function
+ 16-bit adderlsubstr8ctor to exe-
MULT
16 )( 16 - 32 parallel pipeline multiplier
cute complex multipltc8tions.
M, N
2 x l6-blt registers contalmng multiplier operands.
p
2 x l6-bit register containing multiplier result.
BS
ALU
Variable 0 - 15-bit right shift. left shift. right rotation barrel shifter.
2 port 16-bit arithmetic logic unit.
5 possible sources. 4 possible destinations. 27-functions.
Works on 32-bit in 2 cvcles.
D
SAT
AlU output register.
Flag. Indicates saturation m9de
STA
l5-bit register containing status of AlU. mode. status of address calculation
units.
A
B
F
2 x l6-bit accumulator.
2 x 16-blt accumulator
4 )( 16-bit first in first out register.
EF
Flag. Indicates that the fifo is empty; can be set by software.
Replace Code register
5-3-8
RC
6-bit register allowing replacement of AlU operation code by a data coming
Transfer register
5·3-9
T
2 x 16-bit register prOViding d.irect transfer between L-BUS and Z-iUS.
Empty Fifo
Irom L-BUS.
3·8
MEMORY BLOCK
RMource
Data RAMs
Data ROM
Address Calculation Units
,.,.g,.ph
N°
5-4-1
5-'1-3
Symbol
Function
XRAM
YRAM
2 • 128 )( 16-bit word random access mamo," containing data.
CROM
XACU
VACU
512 x 16-bil word read only memory containing coeffictents or constants.
2 x J-bit arithmetic units providing incramentation, decrementation. automalic loop of address.
XACU is dedicated to XRAM.
YACU is dedicated to YRAM.
ECACU
12-bil arithmetic unit providing incrementalion. decrementation of address.
XO,
X
YO,
V
CO,
EO,
2 )( 7-bit registers used for indirect addressing of XRAM.
Shafed between CROM and ERAM ,..terna' RAMI.
5-4-4
Pointers
XRAM Circular Flag
5-4-5
YRAM Circular Flag
Xl
XC
Supplementary register used tor circular addressing.
2 )( 7-bit registers used for indirect addressing for VRAM,
Supplementary registe, used for circular addressing.
2 )( 9-bit registers used for indirect addressing of CROM.
2 )( 12-bit registers used for indirect addressing of ERAM.
Flag. Indicates the circular addressing mode for XRAM.
YC
Flag. Indicates the circular addressing mode for YRAM.
Yl
Cl
El
INPUT/OUTPUT BLOCK
R..ource
Acces~
Mode Register
Input Register
P·'·II.ph
N°
Symbol
function
5-5
AMR
7·bit fegister defining the access mode on the 2 external buses (local and
systeml.
6-4
RIN
3 x B·bit shift register.
ROUT
3 x S·bit shift register.
RDVOIN
Mailbox output.
Flag used in the protocol to indicate which processor has access to the mailbox.
Mailbox input.
Output Register
Ready Out Internal
6-5
3-9
SECTION 4
ARCHITECTURE
4.1. INTERNAL ARCHITECTURE
4.1.1. Parallel processing
The processor internal architecture is organized around the following blocks:
- the arithmetic logic unit and its associated working registers
- the multiplier
- the 3 memories and their associated address calculation units
- the transfer register
- the 1/0 unit.
All these blocks can work simultaneously and independently.
4.1.2. Three-bus structure
To avoid memory access bottlenecks the processor architecture includes 3 data buses. Two read buses (L·BUS
and R-BUS) continuously feed the operating units. Thus making it possible to load the ALU and the multiplier
with the two operands simultaneously. The write bus (l-BUS) is used to transfer the results back into the RAMs
(Internal or external).
4.1.3. Wide instruction word
The 32-bit wide instruction format allows the processor to execute the following operations in 1 instruction cycle:
- Read two operands·lfrom internal or external memoriesl
Execute an ALU operation
Start a multiplication
Use the result of the multiplication started 2 cycles before
Write a result in internal/external memory
Post-modify 3 pointers independently
Store data mto the transfer register.
4.1.4. Pipeline (ct. tig. 4.1.1
The IIgure 4.1 outlines the overlap 01 the Instruction prefetch and execution as well as the pipelmeddata operation.
By using a pipeline structure. the processor performs efficiently on all digital signal processing algorithms. For
example the result of a multiplication started at instruction IN will be available at IN + 2. That will not prevent
from starting a new multiplication at IN + 1 which in turn will be available at IN + 3. etc ... in effect. giving a
multiplier throughput of 1 multiplication every cycle.
3·10
INSTRUCTION CYCLE
~
n- ~n- ~ n- ~
PROGRAM COUNTER
INSTRUCTION
XRAM ADDRESS
CROM ADDRESS
R-BUS DATA
A
L-BUS DATA
K
MULTIPLIER INPUT M
K
MULTIPLIER INPUT N
A
A_K
MULTIPLIER OUTPUT P
B+A.K
ALU OUTPUT
YRAM ADDRESS
B+A.K
I-BUS DATA
FIGURE 4.I.A. - PIPELINE DELAY
Example: READ, AIXRAMI. READ KICROMI. MULTIPLY A and K. ADD BIACCUMULATORI. WRITE RESULT A.K
3·11
+ B INTO YRAM.
INSTRUCTION CYCLE
"--LiL L_'L 'L L-IL
N
N+l
N+2
N+3
N+4
INSTRUCTION
N
N+l
N+2
N+3
N+4
XRAM ADDRESS
N
N 1
N+2
N+~
N+4
CROM ADDRESS
N
N+l
N+2
N+~
N+4
R·BUS DATA
N
N+l
N+2
N+3
N+4
L·BUS DATA
N
N+l
N+2
N+3
N+4
MUL TIPLlE~ ','IIPUT M
N
N+l
N+2
N+3
N+4
MULTIPLIER INPUT N
N
N+l
N+2
N+3
N+4
MULTIPLIER OUTPUT P
N
N+l
N+2
ALU OUTPUT
N
N+l
N+2
YRAM ADDRESS
N
N+l
N+2
Z·BUS DATA
N
N+l
N+2
PROGRAM COUNTER
FIGURE 4.1.B •• PIPELINE THROUGHPUT
Example: The operation A.K + B (described in fig. 4.1.A.I II executed every cycle.
3·12
4.2. EXTERNAL ARCHITECTURE
The TS68930 is provided with two external buses:
- the system bus: ADO·AD7
- the local bus: 00·015.
The processor is a slave on the system bus.
The processor is a master on the local bus.
r-----.,
AOO·A07
_ _ . . 00·015
----.
TS88930
SR/Vii
---+-
___ +
---+-
___ ... A/W
---.
___ ... 55
A8-11
4----
-----IL _____ ...J1
LOCAL
SYSTEM
SYSTEM 8US
The main use of the system bus is for the processor to exchange information with a general purpose
microprocessor or another TS68930 in a multiprocessor environment.
The informations are exchanged through a mailbox with a flag (iRQ) indicating to the master (the other processor)
that it can gain access to the mailbox.
LOCAL 8US
The main use of the local bus is for the processor to exchange information with an external memory, a
peripheral, a data converter or another TS68930 in a multiprocessor environment. All these external circuits
are defined as slaves.
The processor is the master of its local bus, i.e it generates the address and control signals which direct the
exchange on the local 'bus. This bus is a direct extension of the internal structure and all external circuits
connected on it, work in exactly the same way as the internal operating units,
3-13
SECTION 5
FUNCTIONAL DESCRIPTION
5.1. OPERATING MODES
The processor provides three operating modes set by programming, each mode representing a different data
type:
- REAL = 16-bit data
- COMPLEX (CPLXI = 2 x 16-bit data
- DOUBLE PRECISION (DBPRI = 32-bit data.
The modes are made transparent to the programmer as all operating units and all working registers are provided
with the right length.
Main differences between real mode and complex or double precision mode:
al In complex and double precision mode the memory space is reduced by half as all operands are 32-bit long (cl.
format below!.
bl The instruction cycle time is doubled (320 ns instead of 160 ns) as all operations are made sequentially.
even address
odd address
LOWER
UPPER
REAL
IMAGINARY
OOUBLE PRECISION
COMPLEX
5.2. CONTROL BLOCK
6.2.1. Instruction ROM: IROM
The instruction ROM has a capacity of 1280 x 32-bit in the MCU version. It can be extended to 64 K x 32-bit in
the MPU version.
6.2.2. Progrem counter: PC
The program counter is 16-bit wide, 11 bits are used in the MCU version.
6.2.3. Sequence,: SEQ
The sequencer increments the program counter except in case of sequence jump which are listed below:
al immediate branch
bl computed branch
cl jump to subroutine.
(cl 5.2.4.)
d) return from subroutine
e) automatic loop
I (cf 5.2.5.1
J
In case of immediate branch the PC is loaded with an immediate value whereas in case of computed branch the
PC is loaded with a value coming from the accumulators (A, BI, the FIFO (F) or the transfer register (Tl.
3-14
The sequencer can test directly 16 conditions programmed on a high or low state·
BRANCH NEVER/ALWAYS
EXTERNAL CONDITIONS
STATUS CONDITIONS
- SR
Sign IRea11
SI
Sign IImaginaryl
CR
Carry IReali
CI
Carry IImaginaryl
Z
Zero
OVF
Overflow
MOVF
Memorized overflow
The memorrzed overflow IMOVFI,s reset when tested
by the branch instruction
- BSO-BS2j
_ BE3-BE6
E
xternal pins
The falling edges of BE3-BE6 are memorized Internally and reset when tested by the branch Instruction
The external test conditions are used to synchronise
different processes or as a ready Input flag in
multiprocessor system
MAILBOX FLAG
- RDYOIN
Internal mailbox flag
5.2.4. Return address register: RAR
The JSR instruction allows one level of subroutine nesting with automatic saving of the PC on to the return address
register IRARI.
Multiple level of subroutine nesting can be implemented In RAM using either of the two pointers as stack pOinter.
In this case the RAR IS used as the last level of nesting
5.2.5. Loop counter: LC
a) The efficiency of executing repeated calculations often encountered in Digital Signal Processing is considerably
Improved by using the loop counter since the instructions for counter increment and range check are no longer needed.
This counter can implement a loop of up to 16 Instructions repeated 256 times with a delay of up to 8 Instructions.
bl DESCRIPTION:
LCI
LCR
LCD
Instruction Loop Counter: 4-bit
Counts the number of instructions to be executed in the loop
Repeat Loop Counter: 8-bit
Gives the number of times the loop Will be repeated.
Delay Loop Counter: 3-bi1.
Gives the delay between the declaration and the start of the loop.
cl USE:
A loop is declared by loading the instruction loop counter and the delay loop counter with a constant liN I Instructionl and LCR with a constant or a variable IINI or OPDI instruction!.
The loop counter contents can be saved ISVR instruction) with the following format:
17
18
19
20
14
13
12
11
21
22
23
24
25
26
27
28
29
30
31
I-BUS
10
LCD
14
13
12
11
LCI
LCR
I
I
LOOP
COUNTER
10
Z-BUS
Asserting HALT will freeze the state of the LC.
Asserting RESET will reset the LC.
&.3. PROCESSING BLOCK
&.3.1. Multiplier
al The multiplier executes a 16 x 16 ... 32-bit signed multiplication every instruction cycle with a delay of 2 cycles
independently of the operating mode.
The number representation is signed 2's complement and the result format for the 3 modee is shown in figure 5.3.1.
bl USE:
The multiplier is always active. To start a multiplication the two operands are loaded into the two input
registers(M, Nl.
The multiplication will be repeated every cycle until one or both operands are changed. The processor offers the
possibility of loading the two input registers independently.
The result is available in the product register (PI two cycles later.
cl COMPLEX MULTIPLICATION:
The processor executes a complex multiplication:
(A+jBI. (C+jOI - AC - BD + j (AD+BCI
every 320 ns thanks to an internal 80 ns clock.
As it can be seen from the equation the complex multiplication can generate an overflow. In this
multiplier overflow (OVFMI is memorised inside the status register.
case the
dl NOTES:
No provision is made for the operation 8000 x 8000 (hexadecimall.
If this condition arises the product will be 8000 (hexadecimal).
After changing modes the product P is calculated following the new mode.
The signal HALT (cf. Input/outpull will inhibit the loading of the product register P.
DBPR MODE
31
3()
P30
P29
31
30
16
P30
P29
P15
ae x 18 -
31
REAL MODE 18 x 1. - 18
15
P14 f..1
ROUNDING
(adding 1 TO BIT 14
31
I
AND TRUNCATION)
16
30
I I
p'301 p' 29 1
gives 16-BIT RESULT
P'15
COMPLEX MODE 18 x 18 - 1& 'HI
18 x 16 ..... 18 imaginary
31
I
R'30
16
30
1 R' 29 1
1 R' 15 1
31
30
16
1'30
1 1' 29 1
1' 15
IMAGINARY PART
after rounding
REAL PART
after rounding
FIGURE 5.3.1.· MULTIPLICATION OUTPUT REGISTER (PI FORMATS
3-16
1
5.3.2. Barrel Shifter (BSI
All shift and rotation operations are performed at the L-side Oeftl ALU input. The operand can come from two sources:
- LBUS
- P Iproduct registerl
There are two types of shift and rotate operations:
1I
-
The operations which are part of the ALU code:
arithmetic shift right by 1
IASRI
logical shift right
by 1
ILSRI
arithmetic shift left by 1
IASLI
logical shift left
by 1
I LS LI
logical shift right
by B
ILSRBI
logical shift left
by B
ILSLBI
rotate right
by 1
IRORI
21
-
The operations which are implemented
ASR 10 .... 151 arithmetic shift right by
LSR 10 .... 151 logical shift right
by
LSL 10 .... 151 logical shift left
by
ROR 10 .... 151 rotation right
by
through dedicated instructions:
N O .. N OS; 15
N
N
N
Note:
In double precision the shift operations are not executed on 32 bits, but on 2 x 16-bit as the barrel shifter is a 16-bit unit.
In complex mode the shift operations are executed on the real and"imaginary parts.
5.3.3 ALU
The ALU inputs are called LCSide ILefll and R·Side IRighll.
There are two possible sources on the L-Side:
• L BUS
• P Imultiplier output I.
There are two possible 1I0urces on the R-Side:
• R BUS
• Accumulators A or B.
The selection between A or B is made by the field ALU destination (refer to operating codesl. If the ALU destination
field is B then the ALU source is B. In all other cases A will be used.
The ALU output is called D.
There are four possible destinations for D:
• Accumulator A
• Accumulator B
··FIFO
• Z-BUS Ino working registers are modifiedl.
ALU CODES
There are 27 ALU codes. The list is shown in figure 7.9.
5.3.4. Saturation mode (SATI
If the saturation mode is set (SAT flagl the circuit will behave as follows:
• Positive overflow = ALU result is forced to 7FFF Ihexadecimall
• Negative overflow= ALU result is forced to 8000 (hexadecimall
The saturation mode does not apply to the double precision mode.
3-17
&.3.&. Status register: STA
a) DESCRIPTION
CONDITION CODE REGISTER ICCR):
SR
Sign (real)
Set if the msb of the ALU result is 1. Cleared otherwise.
SI
Sign (imaginary)
Set if the msb of ALU imaginary result is 1. Cleared otherwise.
CR
Carry (real)
Set if a carry is generated out of the msb of the operand for arithmetic and
shift operations. Cleared otherwise.
CI
Carry (imaginary)
Set if a carry is generated out of the msb of the imaginary pert for arithmetic
and shift operations. Cleared otherwise.
Z
Zero
Set if the result equals zero. In complex mode it is equivalent to the imaginary
and real parts being both zeros.
OVF
Overflow
Set if there was an arithmetic overflow.
This implies that the result is not representable in the operand size.
In complex mode it is equivalent to the overflow of the imaginary or real pert.
MOVF
Memorised overflow
Set as overflow. Reset when tested by a branch instruction.
AOVF
Advanced overflow
Exclusive or of bit 14 and bit 15 of the ALU.
Set if there was an arithmetic overflow on half capacity 115 bits in real/complex mode. 31 bits in double precision mode). Cleared otherwise.
OVFM
Overflow (Multiplier)
Set if the multiplier adder/substractor has overflowed. Only meaningful for
complex multiplication. Cleared otherwise.
STATE REGISTER
EF
Empty FIFO
Set if the FIFO is empty.
Cleared otherwise.
SAT
Saturation mode flag
Set if the PSI is in saturation mode.
Cleared otherwise.
MODE
(2 bits)
Operating mode
Real. complex or double precision.
XC
XRAM
Circular addressing mode flag.
YC
YRAM
Circular addressing mode flag.
b) USE
The status can be saved (instruction SVRI.
The condition code register can be read (in OPIN instruction) and it can be loaded from a RAM via L-BUS (ALU
code LCCR) without pessing through the ALU.
The stille register can be programmed by an INI instruction.
3·18
5.3.1i. Accumulators: A.B
a) The processor provides two distinct accumulators (A and B). In real mode they are 16-bit long. In complex and
double precision mode they are 32-bit long.
b) Changing modes, changes the length of the accumulator and the relation between the words described below.
CHANGING MODES
COMPLEX
REAL
DOUBLE PRECISION
REAL
COMPLEX
1
DOUBLE PRECISION
It must be noted that the imaginary (respectively lowerl part of the word remains unmodified when switching to
real mode.
5.3.7. FIFO:F
a) FUNCTION
Highly pipelined algorithms require a series of pipeline registers between the ALU output and the memories in order
to store intermediate results.
This is precisely the function of the 4 x 16-bit first-in first-out (FIFOI register.
bl DESCRIPTION
It is a 4 x 16-bit deep register tnat becomes 2 x 32-bit in complex and double precision modes (cf. format below!.
cl USE
When the FI FO is full it becomes impossible to write into it.
When the FIFO is empty a status bit (EF) 'is set.
This bit can also be set by programmation.
dlNOTE
In real mode, a result loaded at instruction IN into an empty FIFO will be available for transfer to the RAM at IN + 2.
In all other cases it will be at IN + 1.
REAL
IMAGINARY
UPPER
REAL
REAL
LOWER
REAL
IMAGINARY
UPPER
REAL
REAL
LOWER
REAL
COMPLEX
DOUBLE PRECISION
3-19
&.3.8. Replece code register: Re
a) FUNCTION
The function of this register is to control the ALU by a data coming from the memories via L-BUS instead of an
instruction. In other words it allows the data to lake control of program sequencing without using test instructions.
For this reason it can be said that the instructions are data controlled.
b) DESCRIPTION
It is a 6-bit register with the following format :
15
14
13
12
11
14
13
12
11
to
10
L·BUS
RC
I·BUS
BIT 1-5 = ALU code is substituted by this value
BIT 0
= 0 Destination of ALU output
accumulator A
= 1 Destination of ALU output = accumulator B
cl USE
This register is controlled by three ALU codes:
ALU code
RCR
Function
load ALU control code in RC
RCE
Execute AlU control code contained in RC
RCER
Execute ALU controf code contained in RC
Load new AlU control code in RC
&.3••• Trensfer regl.ter: T
a) FUNCTION
It is a bidirectionnal register standing between L·BUS, and Z-BUS.
It can be a source and a destination to both buses.
Among its numerous uses, it can perform the function of :
• Loop beck to the multiplier in one cycle
• Temporary register between memory and ALU
• Temporary register between memory and multiplier
• Operations between accumulators
• Memory to memory transfer.
• Saving program counter.
b) DESCRIPTION
It is a lS-bit register extended to 32 bits in complex and double precision mode.
c) USE
The relation between the 32·bit and the l6-bit word in case of mode switching is identical to the accumulators relation.
In branch instruction the register can be used to save the PC.
When the mode is complex the PC (lS-bit) is saved into the real part of the register, when the mode is DBPR the
PC is saved into the upper part of the register.
T can also be used as a source of the PC:
When the mode is complex the PC is loaded with the real part of the register, when the mode is DBPR the PC is
loaded with the upper part of the register.
3-20
6.4. MEMORY BLOCK
6.4.1. O.tII m.morl•• : XRAM. YRAM. CROM
The processor architecture allows the connection of four memories:
• 2 internal RAMs
XRAM 128 x 16-bit
YRAM 128 x 16·bit
• 1 internal data ROM separated from the program ROM
CROM 512 x 16-bit
In the microprocessor version this ROM is external.
• 1 external memory
ERAM 4 K x 16-bit
This external memory is accessed in a single cycle (160 nsl in exactly the same way as tha internal memories.
Moreover·it does not require any "glue" parts to be connected to the processor.
Notes :
1. In complex and double precision modes all data are 32-bit iong. Hence the available memory space is divided by two.
2. The instruction set allows any combinations of aimultaneoua u.. of
- Reading and writing in the same RAM ill the same cycle.
- Accessing CROM and ERAM simultaneously.
m.. rnernora ; the only restraints are:
6.4.2. Addr...lng mod ••
The processor provides four addressing modes:
• Indirect addressing with post modification.
• Direct addressing.
• Immediate addressing.
• Circular addressing mode (also called· virtual shift mode).
6.4.3. Addr... calcul.tlon unite: ACU
Combining these four addressing modes and the processor 3-bus structure implies the need to generate .t
e.ch in.truction cycle three diff.r.nt .ddr...... To realise these functions each memory is associated with
an address calculation unit:
- XRAM with XACU
- YRAM with YACU
- CRCM or ERAM with ECACU.
3-21
5.4.4. Pointers: XO. X1. YO. Y1. CO. C1. EO. E1. X. Y
Indirect addressing is the most commonly used addressing mode in vector or signal processing. For this reason
the processor offers a large number of pointers (1 0): XO, Xl, YO, Yl, CO, Cl, EO, El + X andYfor circular mode.
Each memory can be addressed by two poinlers and pointers can be increased ( + 1I decreased (- 1I or held (+ 0)
independently.
They can also be loaded with new addresses (constants or computed valuesl and saved in case of cqntext switching
(cf.format below!.
15
Ix
6
1
X
X
I
X
X
X
X
X
I "'
I
XO.Xl.YO.Yl
15
I
X
X
15
X
X
X
11
EO.El
x
== undefined
15
Z-BUS
5.4.5. Circular adressing mode
a) FUNCTION
This feature is used to simulate the function of a shift register without moving the data stored. It is particularly useful
in filtering and convolution functions.
bl DESCRIPTION
XO: lower limit
XI upper limit
X : current address
(respectively YO. YI, Y for YRAMI
The algorithm can be described as follows:
1. ADDRESS: ADDRESS + I (post-incrementation)
IF ADDRESS GREATER THAN UPPER LIMIT THEN ADDRESS
=
~OWER
LIMIT
2. ADDRESS: ADDRESS - 1 (post-decrementation)
iF ADDRESS SMALLER THAN LOWER LIMIT THEN ADDRESS = UPPER LIMIT
c) USE
Programming the circular addressing mode is done independently of the operating modes (real, complex or double
precision), in the following way. With reference to the instruction OPCODE: example XRAM.
1. Initialization instruction (lNII
Circular addressing bit set (K7= 1)
Load XO with lower limit.
2. Initialization instruction (lNII
Circular addressing bit set (K7 = 1)
Load XI with upper limit.
3. INI or OPDI instruction
Load X with current address (a value between XO and Xl).
After the first instruction the circular addressing mode is effective.
From now on the programmer has access only to pointer X and Xl. All instructions referencing pointer XO will now
physically reference pointer X.
To gain access again to pointer XO the programmer goes back to the normal mode by an initialisation instruction.
d)
FLAGS
When a RAM is in the circular addressing mode, a flag (XC, YCI is set inside the status.
3·22
5.4.6. ODD/EVEN addresses
a) In complex and double precision modes the processor automatically generates the two addresses of the word
(even then odd).
DBPR WORD
COMPlE" WORD
even address
odd address
rea! part
lower part
imaginary part
upper part
The processor offers the possibility to inverse this order by writing a 1 into the ADOF bit (refer to OPCODE).
ADOF
even followed by odd
1 odd followed by even.
o
bl USE
This feature is made available independently or simultaneously for XRAM and YRAM.
With reference to DPCDDE.
XRAM
Initialization instruction liND
- select complex or double precision mode
- select pointer XO or Xl and load it with J constant
- select ADOF bit as wanted (0 or 1I.
YRAM
Initialization in'struction liND
- select complex or double precision mode
- select pointer YO or Y 1 and load it with K constant
- select ADOF bit as wanted (0 or 1!.
5.5. ACCESS MODE REGISTER: AMR
al DESCRIPTION
This register defines the processor external access modes.
Its contents can be initialized with a constant and saved into memory, (el. format below!'
It is a 7-bit register each bit being defined as shown below:
FE/SE
:Fast exchange/slow exchange on local bus
SLIPS
:Slave/pseudo-S.lave on system bus
SB/CB
:Concatenated or separate local bus
j/M
: Local bus control signal types
DTACK/BE6 :BE6 pin redefinition
BA/BE5
:BE5 pin redefinition
MASK
:Allows the AMR to be masked by the external halt (microprocessor version only!.
BA
DTACK
i
58
SI
FE
BE5
BE6
M
CB
PS
SE
14
15
16
17
18
19
MASK
13
3·23
BIT 0: FE/SE
o
FAST EXCHANGE
1 SLOW EXCHANGE
= external access in 160 ns 11 cycle)
= external
access in 320 ns (2cycles).
The slow exchange mode:
• Can only be used in the real mode.
• The circuit automatically repeats the instruction which defines the external transfer.
• The control of the multiplier, ALU, ACUs, loop counter is the responsibility of the programmer who must take
into account the repetition of the instruction.
BIT 1: SI/PS
o=
1
=
Slave
Pseudo Slave.
A pseudo-slave processor can address an external RAM using the system bus (AOO-A07) as address lines for its
own local bus. Consequently the system bus is no more available for exchanging data between the pseudoslave processor and the bus master.
The pseudo-slave processor behaves differently from a slave processor since in case of exchange it must
relinquish this bus to the master following an exchange protocol. (Reference to 110)
BIT 2: SB/CB
o = Separate bus
1 = Concatenated bus.
The local bus can be used as two independent 8-bit buses 100-07), (08-015) or a single 16 bit-bus (00-015),
BIT 3: j/M
o = Control pulses Read
1
=
(AD) and Write (WR) are generated
Control pulses data strobe (OS') and Read/Write (R/W) are generated.
The local bus supports the two main types of interchange signal:
• A slave processor, a data converter such as the MAFE, a 68000 peripheral, etc. requiring a data strobe and a
readlwrite pulse.
• The standard bytewide RAM requiring a read and a write pulse.
BIT 4: OTACK/BE6
o = of ACK
1
=
BE6
Indicates transfer acknowledge on the system bus to insure 68000 family compatibility.
External test condition.
BIT 5: BA/BE5
0= BA
1
=
BE5
BUS availab'.:•• ),,·rjicates to the master that the pseudo-slave is not using the system bus for
generating ao·:),esses on local bus.
External test condition.
BIT 6: MASK (T568931 only)
o =AMR
1
= AMR
is not masked. When an external halt is applied to the processor the AMR register does not
change.
is masked. When an external halt is applied to the processor the AMR register cha~s to the
following state: FAST EXCHANGE, PSEUOO-SLAVE,CONCATENATEO BUS, RO andWR control
pulses.
This bit can be modified by the programmer even while the HALT is asserted.
3·24
5.6 RESET
The reset signal has the following effects on the different blocks on the circuit:
SEOUENCER
PC. LC cleared to zero.
IR loaded with NOP instruction.
STATUS:
• REAL mode
• no saturation
• empty FIFO IEF = 1)
• memorised overflow IMOVF) = O.
X orYRAM
• no circular addressing mode.
AMR
• Fast exchange
• Slave
• Concatenated bus
• RD and WR
• BE6
• BE5.
RESET must be maintained for a minimum of 3 clock cycles 1480 ns) to be effective.
5.7 HALT IT568931 only)
The external halt signal will freeze the program counter and the loop counter. The instruction register can then
be loaded from an external source. This signal is used for system development. lithe MASK bit = 1 It will force
the AMR into the following state: FAST EXCHANGE, SLAVE, SEPARATE BUS, RD and WR control pulses.
3-25
SECTION 6
INPUT/OUTPUT
6.1. DUAL-BUS INTERFACE
In order to permit a maximum versatility the processor interface provides two buses:
- the system Bus ADO-AD?
- the local Bus 00-05.
This dual-bus interface allows the processor to be used in the following ways:
a) a microprocessor peripheral (fig. 6A)
b) a slave of another processor (fig. 6.B.)
cl a stand-alone unit connected to a peripheral or a data converter (fig. 6.C.)
d) a processor and its external memory (fig. 6.0.)
e) an Intelligent peripheral connected to a general purpose microprocessor (fig. 6.E.1
These are some examples of the possibilities offered by the dual-bus interface. In addition very sophisticated
multiprocessor machines can be built based on the principle of tree hierarchy(fig. 6.F.).ln effect each processor
becomes nested in the multiprocessor machine in the same way as subroutines are nested in a program tree.
DO-D7
R/W.
HOST
OS.
-
ADO-AD7
DO-07
!+-:D"'A"'T"'A---JS=---I ADO-AD7
DATA
es. RS
R/W.
t-~iRQ"'R'F.""D"'TO=Ae"K;-----lT568930
TS68930
T56893D
DO-D15
S or 16
R/W.
-
OS
f---A:-D"'D"'R::-:E:-;:S"'S--~ ~~~~AL
F
2
4
16
4 Kx
RD.
I
iNN.
1~
A8-Alll
ADO-AD7
~AM
-
T568930 ...._.....!:L::::O~CA~L~BU~S~--I... RAM
FIGURE 6.0. - TS68930/RAM
FIGURE 6.C. - TS68930/PERIPHERAL
00·07
DATA
ADO-7
T568930
T568930 ...._~LO~C:!A~L:.,;B~U..S~--I.... PERIPHERAL
HOST
T568930
FIGURE 6.B. - TS68930/TS6B930
FIGURE 6.A. - HOSTlTS68930
DATA
OS. CS. lfS
rnn
"---
00·015
S
ADO·A07
5
RAM
R/W.
OS. CS. lfS
I----===="--·..
HOST
"1-~S.!.Y~ST!.!E;::M~BU~S2-_
TS68930
ITEMPORARY MASTER) •
• (PSEUDO-SLAVE) TS68930 ....
FIGURE 6.E.. TEMPORARY MASTER/PSEUDO·SLAVE
3-26
LOCAL BUS
RAM
SYSTEM
BUS
MB
P
P = Processor T568930/T568931
GRAPHICS
CONTROLLER
BIT
MAP
18
8
MB
MB
MB
MB
MB
MB
MB
P
P
P
P
P
P
P
18
8
MB
MB
MB
MB
P
P
P
P
18
RAM
18
RAM
18
RAM
PERIPH.
CONTROL
18
DAC
P
18
ADC
18
MB = MAILBOX
RAM
FIGURE 6.F. - MULTIPROCESSING MACHINE
3·27
MB
DATA
LINK
6.2. MASTER/SLAVE
The processor is a master on its local bus anda slave on its system bus. There are times where the processor
needs to access an external RAM and for that purpose will use the system bus to generate the addresses.
In this case this circuit prevents the master from using the bus freely and for that reason is called a pseudo-slave.
Since the master can only gain access to the bus temporarily it is now defined as a temporary master.
It is the programmer who decides whether the processor should behave as a slave or a pseudo-slave.
This is done by programming the Access Mode Register.
That gives four different types of processor configurations:
P81_
Deflnltlon
SLAVE ISL)
Its system bus is used to exchange data with a full master.
PSEUDO-SLAVE (PSI
Its system bus is also used to generate addresses for its local
exter~
nal memory.
FULL·MASTER (FMI
It has complete mastership of its local bus,
TEMPORARY·MASTER ITMI
Its local bus is shared with another processor which uses it to
generate addresses.
These exchange type can be summarized to three possible connections:
1) Full master ... slave
2) Full master ... memories or peripherals
31 Temporary master'" pseudo-slave.
Connection 1 (with reference to fig. 6.A., 6.B.!:
The data is exchanged through a mailbox and the exchange-follows the mailbox protocol.
Connection 2 (example 6.C., 6.0., 6.E.!:
The exchange is equivalent to reading and writing of data into locations or registers.
Connection 3 (example 6. E.):
The data is exchanged through a mailbox and the exchange follows the mailbox protocol.
'.3. LOCAL BUS PIN DESCRIPTION
00-07
08-015
TS68930
~
AS-A 11
t--.~~~~
L _ _J - - -
(ADO-A~7)j
16-bit data bus can be concatenated or separate.
4 address bits.
Control bits. Can be chosen among 2 sets.
Additional address bits.
~
= data strobe. Synchronizes the transfer.
R/W = indicates the direction of data.
'If[5 = read clock pulse.
WA = write clock pulse.
The bus can take the form of two independent 8-bit buses or a single 16-bit bus.
There are four address bits (As-A11) which are sufficient to address many slaves without requiring additionnal circuitry.
The address bus can be extended to 12 bits (ADO-A07) to access an external memory.
If a peripheral is too slow to answer in one instruction cycle the processor can be programmed into a slow
exchange mode. This mode is particularly useful for peripherals such as data converters, or the dedicated
analogue interface cj'roJit fabricated by THOM!'''N for modem applications. (The MAFE: Modem Analog
Front-End).
3-28
SEPARATION OF LOCAL BUS
The processor offers the possibility of dividing the local bus 00-015 into two independent 8-bit buses. This is
used when a pseudo-slave monopolizes the bus to generate its own RAM addresses (fig. 6.3.) on 00-07. By
separating the bus, the processor can remain a full-master on 08-015 even while being a temporary master on
00-07, and it does not require the use of a bus transceiver on 00-07.
The selection between the 2 )( B-bit buses is made by the addresses A 10-A11 .
...t-;D:::;8-::.D~15~---------.
~~A~~~ER
TS68930
MASTER
DO-D7
TS68930
L.-----.~-L--t PSEUDO
All
Al0
SELECTION
0
0
00-07
0
1
08-D15
1
0
OS·DI5
1
1
08-015
RAM
SLAVE
ADO-7
FIGURE 6.3. - SEPARATE LOCAL BUSES
6.4. SYSTEM BUS AND MAILBOX
ADO-AD7
CS
RS
SR/iN
SDS
DTACK
BA
IRO
ADO-AD7
~l
SR/iN
~
11m
15'fACi(
BA
= 8-bit data bus.
= Mailbox control signal. Also used by master to gain access to bus.
= System Read/Write
= System data strobe_
I
. .
Generated by axternal CircUit (master)
= Handshake signal.
Used by the master to gain access to mailbox (and bus!.
= Data acknowledge. Compatibility with 68000 family.
= Bus available. The PSI is not currently using the system bus to generate addresses_
MAILBOX
The mailbox is comprised of two sets of registers: RIN and ROUT.
RIN (3x8-bit shift registerl.
This register is read internally on the upper byte of L-BUS (L8-L15) and written externally from the system bus.
After each write operation (commanded by the external master) or slave read operation the data is shifted by 1.
ROUT (3 x 8-bit shift registerl.
This register is written internally with the upper byte of the Z-BUS (Z8-15) and read externally on the system bus
by the external master. After each master read operation or slave write operetion the data is shifted by 1.
3-29
6.5. MAILBOX PROTOCOL
ADO-AD7
00-015
A/W
example
SA/W
DS
SDS
A8
CS
A9
AS
8S0
TAd
MAILBOX
TS68930
TS68930
MASTER
SLAVE
This protocol is hardwired on the slave side and programmed on the master side. The mailbox is included in the
slave. The two slave address pins (CS, RSI are directly connected to two master address lines.
Therefore, the slave IS seen as two external memory locations by the master which will address it by generating
an external address directly or Indirectly (pointer EO or Ell
By addreSSing the location 00 the master echoes the IRQ to the slave and accesses the mailbox.
By addreSSing the location 01 the master releases the bus
The comple1e protocol IS explained below.
,
MASTER
SLAVE
MAIL80X IS AVAILABLE
Asserts IRQ, RDYOIN
I
Detects fRO ;::: 0
(one of 115 external test conditions)
Applies
+ AS
CS ""
0,
=
0
I
detects
CS
If pseudo-slave
,_
= 0
RS = 0
Irhe processor is put in Halt state
~nd releases the system bus
+
Negates IRQ
I
+
Detects IAQ = 1
MAILBOX ACCESS
(3 reads and 3 writes maximum)
END OF MAILBOX ACCESS
Applies CS = D, AS = 1
t
If pseudo·slave [
Internal Halt disappears. The processor
resumes program and
takes back control of the bus
+
negates ADYOIN
3-30
SIGNAL MEANING
RDYOIN
Internal flag indicating the property of the mailbox.
Slave has access to the mailbox
1 = Master has access to the mailbox.
o=
al RDYOIN is set by the slave and reset by the master. That means that the slave gives the mailbox to the master
when it finishes using it and vice-versa. In no case can the master or the slave request the mailbox, it can only wait
for the other to give it back.
bl From the slave point of view, RDYOIN is a flag:
- tested by a branch instruction
- set by an initialization instruction.
iRQ
Handshake signal used by the master to gain access to the mailbox;
al
JJm is asserted
by the slave to indicate the availability of the mailbox (at the same time as RDYOINI.
bl The master (after testing iRQl knows that it can access the mailbox but does not know if it has access to the
bus (since it does not know if the slave is behaving as a pseudo-slavel.
It requests the bus by generating the address"ES = 0, irn = O.
cl The slave internal 1/0 sequencer answers back by negating iRQ. The master has now full control of the bus and
the mailbox.
When the master has completed the exchange it generates the address CS = 0, irn = 1 and the slave internal
1/0 Sequencer resets RDYOIN..
HALT (intemal)
The internal halt has the following effects on the circuit :
- the program is stopped at the end of the current instruction; the program and loop counters are frozen
- a NOP is generated on the instruction bus
- no more addresses are generated on the system bus.
6.6. INSTRUCTION BUS (TS68931 only)
Forthe TS6B931, CROM (512 x 16-bit) and IROM (64kx 32-bit) are external. They are read using the I-BUS, on
which are multiplexed:
- the 16-bit instruction ROM address
- the 9-bit coefficient ROM address 1 Output Enable bit (ENCROM)
- the 32-bit instruction code.
+
In order to synchronize the exchanges, an additional signal is generated: INCYCLE.
It is the internal instruction clock.
Data from CROM are read on the local bus.
3-31
6.7. APPLICATION EXAMPLES
.
TS88930
A
00·07
...
MAFE
DO·07
-y
-
~
08·015
All
AlO
A9
A8
V-
--..f-~ f--
55iffD
r-- f--
R/Vii/WR
..-- f--
-
CSl
CSO
RSl
RSO
~
S
Towards
general purpose
{
S\..
R/Vii
DE
WE
-
ADO·AD7
microprocessor
55
cs
y
... f
DO-015
S
AO-AlO
11
RAM
2K x 16
(2x2Kx8)
All
Al0
A9
AS
1
0
X
X
MAFE
0
X
X
X
RAM
FIGURE 6.7A - CONFIGURATION EXAMPLE: TS68930 + RAM
3-32
+ MAFE
Sin
Sout
!
I
+
SSO-SSI
1IIll
A
DB-D15
r--v
~
DO-D7
ADO-AD7
...
T_
T588930
(1)
AS-All
~
A9
~.
ADO-AD7
R/W
B.
RS
m. SR/W
2
2
Towards
generaI purpose
microprocessor
4
~
~
m. SR/W
1IIll
ADO-AD7
B.ll!
AS
T588930
(2)
RAM lKx16
~
DB-DI5
y
DO-D7
AO-AS
ADO-AD7
AO-A9
CS
A10
All
A10
A9
AS
0
1
011
1
T568930
(1)
0
1
1
011
T568930
(2)
1
0
X
X
RAM
~
Wl
!
t
FIGURE 6.7.B. - CONFIGURATION EXAMPLE: 3 T56893O+ RAM
3-33
I--
MAFE
....
A
08-015
;.
..
S
DO-07
DO-07
OS,
~,m,ASl
Aiw
2
2
A/Vii,
"
TS68930
eso
...
eSl
~
eS2
,,
~
ASO
~
AS-All
'\
cml_
TS68930
(II
ADO-AD7
cs,liS
"S15S
SA/Vii
iliO
I
TS68930
(21
.
2
All, AS
-
ADO-AD7
CS,AS
"S15S
2
SA/Vii
-lAO
I
TS68930
(31
A
ADO-A07
"V
2
All, AlO
2
cs,liS
"S15S
AS-All
SA/Vii
A 11
Al0
A9
AS
1
0
X
X
MAFE
0
1
011
1
T568930
0
1
1
011
T568930
(21
1
T568930
(31
0
011
1
~
rna
I
f-71
2
DE, WE "'"
AO-A7
(11
AS-All
DO-015
AAM
4k x 16
FIGURE 6.7.C. - CONFIGURATION EXAMPLE: 4 T568930 + MAFE
3·34
+ RAM
I--
V'-...
0·bU5
TO OTHER
PERIPHERALS
00-015
16
OEIROM
CROM
OECROM
512.16
ENCROM
TS
&8931
LA
16·115
131·10
B
10
I·BUS
B
B
8
INSTRUCTION
ROM
IROM
(64Kx32)
FIGURE 6.7.0 .• I·BUS INTERFACE (TS68931)
3-35
SECTION 7
INSTRUCTION SET
Numb., of cycl ••
Type
Mnemonic
Operation
REAL
CPLX
OBPR
Calculation. Instruction with indirect
addreslng
OPIN
ThiS Instruction refers to operands indirectly
addressed
1
2
Calculation. instruction with direct
addressing
OPDI
The operand sourcing the L-BUS is directly
addressed
1
2
Calculation, instruction with immediate
operand
OPIM
An immedIate operand is read on R-AUS
1
2
General shift
Instruction
ASR
ASL
LSR
ROR
BRI
The operand sourcing the L-BUS can be
shifted/rotated by 0 ...... 15 bits
1
2
Conditional I unconditional
branch to direct address
2
2
Immediate branch
Instruction
Computed branch
Instruction
BRC
Conditional I unconditional
branch to computed address
Data transfer
Instruction
SVR
Initialization and control instruction
INI
This instruction is used to save register contents
In external or internal RAM
Pointers, access mode register, loop counter,
mode initialization
INSTRUCTION SET LANGUAGE DEFINITIONS
LDT
load L·BUS source into transfer register T
R SRC
R·BUS source
L SRC
l·BUS source
SL
ALU Input selection· left side
SR
ALU input selection· right side
ALU DST
AlU output destination
ALUCODE
ALU codes
LDM
Load L·8US source into multiplier input M
LDN
Load A·BUS source into multiplier input N
Z SRC
Z-BUS source
Z DST
Z·BUS destination
ZT
Load Z-BUS into transfer register T
ACE
Post incrementation: pointers CAOM or EAAM
AY
AX
Post incrementation: pointers YAAM
BRA
a,ranch address source
FT
False I T rue condition
Post Incrementation: pointers XAAM
SVPC
Save program counter
JDST
Destination regls,ter for J constant
KDST
Destination register for K constant
MODE
Operating mode
SAT
Saturation flag
ADOF
Even I odd flag
J7
YAAM circular addressing mode flag
J constant
a·bit constant used to initialize registers
K7
XAAM circular addressing mode flag
K constant
12·bit constant used to initiahze regIsters.
3-36
2
1
,
2
2
7.1. OPERATING CODE FORMATS
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Operation. and codlt.
Field
OP COOE
00
LOT
R SRC
O-NO LOAD. aBUS
01
10
00
[EO)
[YO)
[XO)
L SRC
[XO)
SL
SR
O-LBUS I I·P
O-RBUS I I·A/B IREFER TO ALU OST)
ALU CODE
CF. SPECIAL TABLE
ALU DST
00
0
01
F
10
A
11
B
Z SRC
000
001
F
010
A
011
8
LDM
LON
O-NO LOAD I
O-NO LOAD I
01
00
+0
+'
00
01
+0
+1
01
00
+0
+1
000
0
ACE
AY
AX
001
[X,)
000
Z DST
NONE
~
010
[YO)
011
RIN
100
T
101
[E')
100
T
101
CCR
011
[Y')
100
[EO)
110
111
[C,)
[CO)
110
111
-
-
101
[E')
110
[XO)
aBUS ~ M
I·RBUS ~ N
10
11
-,
-
11
- -,
10
10
-
-,
001
ROUT
010
[YO)
11
O-NO LOAD I l·ZBUS
ZT
T
11
[Yll
~
111
[X,)
T
FIGURE 7.1. . OPIN: CALCULATION INSTRUCTION WITH INOIRECT AODRESSING
Bit
0
1
Operation. and code.
Field
OP CODE
010
R SRC
00
[XO)
2
3
4
5
000
01
[EO)
001
10
[YO)
11
[Y')
010
Y
011
MIN
~
L SRC
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Z SRC
SR
0-0 I J.F
ALU CODE
CF. SPECIAL TABLE
ALU DST
O-F I l·A
MSB
X
-
100
T
101
E
110
-
111
C
O-RBUS I I·A
LBUS
DIRECT
ADDRESS
Z DST
LSB
0000
NONE
0001
XO
0010
ROUT
0011
X,
0100
[YOI
0101
YO
0110
[Y'I
0111
Y'
1000
[EOI
1001
EO
1010
[El)
1011
El
1100
[XOI
1101
CO
1110
LCR
1111
C'
FIGURE 7.2. - OPDI: CALCULATION INSTRUCTION WITH DIRECT ADDRESSING
3·37
OPERATING CODE FORMATS (Continued)
Bit
0
1
2
3
4
5
6
7
8
9
10
,1
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
Operations and cod..
OP CODE
01110
L SRC
000
[XOI
SL
SR
O-LBUS I l-P
O-RBUS I l-A
ALU CODE
CF. SPECIAL TABLE
ALU DST
O-F I l-A
MSB
001
[Xli
010
[VOl
100
T
011
RIN
101
[Ell
110
[COl
111
[Cl1
IMMEDIATE
VALUE
LSB
FIGURE 7.3. - OPIM: CALCULATION INSTRUCTION WITH IMMEDIATE OPERAND
Bit
Fiald
Operations and codas
0
1
2
3
4
5
6
7
B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
OP CODE
01111
L SRC
000
X
SL
O-LBUS I l-P
01
00
ASR
LSL
10
LSR
11
ROR
0000
0
.....
.....
1111
15
ALU CODE
SHIFT
VALUE
ALU DST
001
-
0001
1
010
V
011
RIN
100
T
101
E
}
110
-
111
C
NOTE: When LSR, ASR, ROR
shift value is complemented to 2
O-F I l-A
MSa
LaUS
DIRECT
ADDRESS
LSB
2s
29
30
31
FIGURE 7.4. - ASR, LSL, LSR, ROR: SHIFT INSTRUCTIONS
3-38
OPERATING CODE FORMATS (Continuedl
Bit
0
1
2
3
4
5
6
7
Field
Operations and codes
OP CODE
100
BRA
O-IR.l-RAR
Fl
O-FALSE. 1-TRUE
COND
REFER TO SPECIAL TABLE
SVPC
O-NO SVPC. l-PC MSB
8
9
10
11
12
13
14
15
16
17
18
19
RAR
BRANCH
ADDRESS
20
21
22
23
24
25
26
27
LSB
00
+0
AX
28
29
30
31
01
+1
10
11
-1
001
010
[YOI
Z DST
000
NONE
ZT
O-NO LOAD. 1-ZBUS - T
-
011
[YlI
100
101
-
-
110
[XOI
111
[XlI
FIGURE 7.5. - SRI: IMMEDIATE BRANCH INSTRUCTION
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Field
Operations and codes
OP CODE
1010
Fl'
O-FALSE. 1-TRUE
COND
REFER TO SPECIAL TABLE
SVPC
O-NO SVPC. 1-PC -
BRANCH
SOURCE
RAR
-
001
F
010
A
011
B
00
+0
01
+1
10
-
11
-1
001
010
[YOI
011
[Yl1
000
100
T
101
-
110
-
100
101
-
-
110
[XOI
111
-
20
21
22
23
24
25
26
27
AX
28
29
30
Z DST
000
NONE
31
ZT
O-NO LOAD. 1-ZBUS - T
-
FIGURE 7,6, - BRC: COMPUTED BRANCH INSTRUCTION
3-39
111
[XlI
OPERATING CODE FORMATS (Continued)
Bit
0
1
2
3
4
5
Operation, and cod..
Field
OP CODE
011000
0000
XO
1000
AMR
6
7
~
Z SRC
10
11
12
13
14
15
16
17
18
19
ZO
21
22
23
24
25
26
27
0010
VO
'~'
'~O
001
ROUT
010
V
0011
VI
1011
F
0100
EO
0101
EI
1101
STA
0110
OO
all
100
101
-
E
110
X
'h
0111
CI
1111
CO
1110
MSB
ZBUS
DIRECT
ADDRESS
LSB
Z8
29
30
31
0001
XI
Z DST
000
NONE
ZT
(}-NO LOAD. 1-ZBUS
~
-
111
-
T
FIGURE 7.7. - SVR: DATA TRANSFER INSTRUCTION
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
OP CODE
II
J DST
000
AMR
001
LCD
010
VO
011
VI
100
-
101
RDVOIN
110
EF
111
NONE
K DST
000
XO
001
XI
010
LCI·LeR
011
NONE
100
EO
101
EI
110
111
CI
MODE
CO
10
11
00
01
REAL
DBPR
CPLX
0
NO SATURATION MODE
NO INVERSION
0
J7 o VRAM NORMAL MODE
1 SATURATION MODE
1 INVERSION LSB ADDRESS X/V RAM
1 VRAM CIRCULAR ADDRESSING MODE
K7 0 XRAM NORMAL MODE
1 XRAM CIRCULAR ADDRESSING MODE
-
SAT
ADOF
J7
J CONSTANT
JO
K11
zo
21
22
23
24
25
26
27
Operation, and coda.
Field
Bit
K CONSTANT
Z8
29
30
31
KO
FIGURE 7.8. - INI: INITIALIZATION AND CONTROL INSTRUCTION
3·40
7.2. ALU CODeS
SR SI CR CI
Function
MNEMO·
ADD
A+B
ADDC
A+B+CARRY
ADDS
B + Al,.
ADDX
B + AO (COMPLEX CONJUGATEI
AND
A.B
ASL
CARRY
d
ASR
I-
0
~CAHRY
CLEAR
COM
COMPLEMENT A
COM
COMPLEMENT B
LCCR
LBUS - CCR
LSL
CARRY
LSLB
LSL BYTE
LSR
0
LSRa
LSR BYTE
D--1
-I
I-
0
!-DCARRY
0
0
0
0
CLR
0
0
0
0
0
1
0
0
0
0
II
A • B
RCE
EXECUTE RC
RCER
EXECUTE RC I LOAD NEW CODE
RCR
LOAD RC
ROR
rt
SBC
A+i+CARRY
SBCH
A+B+CARRY
~CARRY
0
0
SUBH
A+B+l
TRA
TRANSFER A
TRA
TRANSFER B
XOR
A(ilB
0
Affected bit,
11 AlB rel.r to ALU inputs (RESP, LSIDE/RSIDEI not to accumulators AlB
21 In ASL the Carry bit is equivalent to exclusive· or of bit 14 and 16.
3-41
11000
01001
0
,,00,
0
00111
0
(I
Notes :
10011
10110
11011
0
0
01110
0
•• • - •
••••••••
0
A+B+l
00001
01010
01111
0
.'.
00011
-
• • • • • • •- •
••
•••••••
• • • • • • •- •
•• • - •
•
•
••
•• • - •
SET
SUB
0
00010
01011
-
OR
CODE
-
0
NOP
•
••••••••
••••••••
••••••••
• • • • • • •- •
•• • •
•••••• •
•
•••••
• • • -- •
•• • •
••••••••
••••• - •
••••• - •
••••• - •
•- •- •- •- •- - - ••• • - •
••••••••
••••••••
0
D-1
MO AD
Z OV
F VF VF
0
11010
00000
01101
10001
10000
10010
10111
00101
01000
11100
00100
00110
0
0
0
0
0
0
10100
10101
0
0
0
01100
7.3. TEST CONDITIONS
TRUE CONOITION
FALSE CONDITION
BE3
NO BE3
0100
BE4
NO BE4
0010
BE5
NO BE5
0011
BE6
NO BE6
0001
BRANCH
ALWAYS
BRANCH NEVER
0000
BSO
NO BSO
1100
BS1
NO BSl
1101
BS2
NO BS2
1110
CI
NO CI
1010
CR
NO CR
0110
MOVF
NO MOVF
1011
OVF
NO OVF
0111
RDYOIN
NO RDYOIN
1111
SI
NO SI
1001
SR
NO SR
0101
Z
NO Z
1000
3-42
CODE
SECTION 8
PERFORMANCE EVALUATION
TIME IlLS)
TRANSVERSAL FILTER
(N COEFFICIENTSI (11
O.l60xN
REAL
COMPLEX
ADAPTIVE REAL
ADAPTIVE CMPLX
BIQUAD FIL TER
~
0_320 x N
0320 x N
0640xN
4 COEFF
0960
LATTICE FILTER - 10 STAGE 11)
AUTOCORRELATION
(240 samples)
(32-blt result)
FFT
(RADIX 2
~
~
6.4
10 th ORDER (21
8 j.1.s/sample
1.B ms total
DIF . algorithm) (2) 13)
64 ~ POINT COMPLEX
128· POINT REAL
256 ~ POINT COMPLEX
265
270
2000
COSINE CALCULATION
2.4
Notes
(1) Excluding Initialization, context sWllch,ng, pipeline
(2) Using external RAM.
(3) Including loading/unloading, scaling, bit reserve
3-43
SECTION 9
ELECTRICAL SPECIFICATIONS
9.1. MAXIMUM RATINGS
Rating
Symbol
Supply voltage
0.3 to 7.0
Vm -
-0.3 to 7.0
V
TA
o to 70
·C
-55 to 150
·C
Operating temperature range
Storage temperature range
Tslg
PDmax
Stresses above those hereby listed may
cause permanent damage to the device
The ratings are stress ones only and
functional operation of the device at
these or any conditions beyond those
Indicated in the operational sections of
this specification is not implied. Expo·
sure to maximum rating conditions for
extended periods may affect device
reliability. Standard MOS circuits handling procedure should be usedto avoid
possible damage to the device.
Unit
VCC'
Input voltage
Max. power dissipation
Value
3
V
W
• With respect to Vss
9.2. DC ELECTRICAL CHARACTERISTICS
VCC = 5.0 V ± 5 %, VSS = 0, TA = 0 to + 70 D C (Unless otherwise specified)
Symbol
Min
Typ
Max
Unit
VCC
4.75
5
5.25
V
Input low voltage
VIL
-0.3
-
0.8
V
Input high voltage
VIH
2.4
-
VCC
V
'in
-
-
to
.A
VOH
2.7
V
-
-
-
VOL
0.5
V
PD
-
1.5
-
W
-
10
-
pF
-
10
.A
Characterletic
Supply voltage
Input leak.age current
-300 .AI
Output high ....oltage (iload -
Output low voltage O'oad - 32 mAl
Power dissipation
Input capacitance
Cin
Three state (off state I input current
ITSI
9.3. AC ELECTRICAL SPECIFICATIONS - CLOCK AND CONTROL PINS TIMING
(Vec = 5.0 V
± 50/0,
+ 70o C; see figure 9.1.)
+ DC characteristics I load
TA = 0 0 to
OUTPUT LOAD = 50 pF
REFERENCE LEVELS: VIL: 0.8 V
VOL: 0.8 V
VIH: 2.4 V
VOH 2.4 V
tr, tf ,,; 5 ns for input signals
Symbol
Min
External clock cycle time
tcex
40
External clock fall time
Characteristic
Typ
Max
Unit
160
ns
tfex
5
ns
External clock nse time
trex
5
ns
EXTAL to CLKOUT hIgh delay
teah
25
EXTAL to CLKOUT low delay
teo I
25
CLKOUT rise time
teor
10
ns
CLKOUT fall time
teof
10
ns
CLKOUT to DS. AO. WA low
tdsl
5
ns
CLKOUT to OS. AD. WA hIgh
tdsh
5
ns
ns
ns
ns
Control inputs set-up time (SSO .. BS2. BE3BE6. Aeset, halt)
tse
20
Control,nputs hold time (BSO .. BS2. BE3 .BE6. Aeset. halt)
the
10
CLKOUT to control output low (IAQ. BA)
tdle
50
ns
CLKOUTto control output hIgh (BA)
tdhe
50
ns
3-44
ns
EXTAL
CLKOUT
~~
RESET. HALT
IRQ. BA
FIGURE 9.1. - CLOCK AND CONTROL PINS TIMING
INTERNAL CLOCK OPTION
A crystal oscillator can be connected acrossXTAL and EXTAL. The frequency of CLKOUT: tcl2 is half the crystal
fundamental frequency.
Cl
EXTAL ~-1--11--1
C1. C2 typical value = 10 pF
TS6B930
C2
XTAL
+--....-11-4
3-45
9.4. AC ELECTRICAL SPECIFICATIONS - LOCAL BUS TIMING
= 5.0 V ± 5 %. TA = 0 0 to + 700 e; see figure 9.2.)
(Vee
Che,.cterladc
Symbol
Min.
Max.
Unit
AD, WA, AS pulse width
tpw
112 te - 15
112 te
ns
address hold time
tAH
10
-
ns
data set-up time, write cycle
tosw
25
-
n,
data hold time. write cycle
tOHW
10
-
ns
data set-up time, read cycle
tOSR
20
-
ns
data hold time. read cycle
tOHA
5
-
n,
address valid to WA, AS. RD low
tARW
112tc-40
-
ns
~
ADDRESSES
»»») '}
~
tpw
];
\
tARW
k -I -
I
~ r-
R/W
\\'0c\\\\'\
/
tpw
\
/
tARW
Ir--
tpw
\
/
tARW
tDSW
/'~(
co
C>
E
l:I
l>
R;W
CSO/CS1
TS 68930.31
I
•
Y{
I
I
8 BIT DATA BUS
CTRL
I
CONTROL
REGISTER
RC4
RSO/RS1
I
I
I
L_
I
ADDRESS
ADDRESS REGISTER
ARC
~
v-
-0--0--0DGND
AGND
v+
~68~O_
-'
~
PIN DESCRIPTION
Name
No.
05·07
1·3
Function
8 bit data bus inputs giving access to Tx, estimated echo, control and address registers. (With pins
20·24).
E
4
Enable input. Data are strobed on the positive transitions of this input.
R/W
5
Read/write selection input. Internal registers can be written when R/W
CSO·CSI
6·7
Chip select inputs. The chip set is selected when CSO; 0 and CSI ; 1.
RSO·RSI
8·9
Register select inputs. Used to select D/A input registers or control/address registers in the write
mode.
OGNO
10
Digital ground; 0 V. All digital signals are referenced to that pin.
TEST
11
Test input. Used to reduce testing time.
V-
12
Negative power supply voltage; -5 V
AGNO
13
Analog ground; 0 V.
= O. Read mode is not used.
That pin must be connected to OGNO in all applications.
±
5%
Reference point for analog signals.
EXI
14
Programmable analog input tied to filter or attenuator input according to the RC4 register content.
ATO
15
Analog transmit output.
EEO
16
Analog echo cancelling output.
V+
17
Positive power supply voltage: +5 V
±
5%.
ClK
18
1.44 MHz clock input. Used for internal sequencing.
TxCClK
19
Transmit conversion clock input. Must be derived from elK.
00-04
20-24
See pins No. 1-3.
3-69
FUNCTIONAL DESCRIPTION
The TS68950 is a transmit analog interface circuit
dedicated to voice-grade MODEMs, telephony and
speech applications. The TS68950, the TS68951
(receive analog front-end circuit) and the TS68952
(clock generator) constitute an analog front-end chip
set useful for implementation of synchronous MODEMs operating on two or four wires according to the
CCITT V.26, V.26 bis, V.27, V.27 bis, V.27 ter and
V.29 recommendations or BELL 208 and 209 standards, or in two wires full-duplex according to CCITT
V.22, V.22 bis or BELL 212A (split band) and CCITT
V.26 ter and V.32 (echo cancelling).
By receiving digital samples from a DSP like the
TS68930/31, the TS68950 delivers two analog signals: the transmitted (Tx) signal that will be sent on
the line and the estimated echo signal that will be
subtracted from the received (Rx) signal on the
TS68951 Rx chip.
The digital Tx and estimated echo samples are converted to analog during the low state and the high
state of the TxCCLK clock, respectively.
Read/Write (R/W) - This signal is generated by the
DSP to control the direction of data transfers on the
data bus. A low level state on the TS68950 read/
write line .enables the input buffers and data is transferred from the DSP to the TS689500n the Esignal if
the circuit has been selected. The device is unselected when a high level signal is applied to the R/Vii
pin.
Chip Select (CSO, CS 1) - These two input signals are
used to select the chip. CSO must be low and CS1
must be high for selection of the device. Data
transfers are then performed under the control of
the enable and R/iN signals. The chip select lines
must be stable for the duration of the E pulse.
Register Select (RSO, RS1) - The two register select
lines are used to access the different registers inside
the chip. For instance these two lines are used in
conjunction with the internal control register ARCto
select a particular register RC4. The register select
lines must be stable when the E signal is low.
CLOCK INTERFACE BETWEEN TS68950 AND
T568952
MAIN FUNCTIONS (See block diagram)
12 bit digital to analog converter multiplexed on
two channels.
Tx signal sample and hold running with Tx sampling frequency TxCCLK.
Tx low-pass filter
smoothing.
with
continuous-time
•
Programmable attenuator from 0 to - 22 dB with
2 dB steps.
•
Estimated echo sample and hold running with Tx
sampling frequency TxCCLK.
The TS68950 receives two clock lines from the Clock
Generator TS68952.
Master clock sequencing (ClK)
The typical frequency is 1.44 MHz but the recurrence frequency must be an exact multiple of the
terminal clock frequency. The Tx DPLL included in
the clock generator circuit (T568952) operates by
adding or subtracting pulses to a 2.88 MHz internal
clock. This corresponds to phase leads or phase lags
of about 350 ns duration. To ensure correct device
operation, clock synchronization must be done
immediately after the negative-going transition of
TxCCLK clock.
TXCClK-----,~____________________
~NORMAl
DSP INTERFACE SIGNALS
The TS68950 interfaces to the signal processor via
an 8 bit data bus (only used in writing mode), two
chip select lines, two register select lines, a read/
write line and an enable line.
Data bus (DO-D7) - The write only data lines allow
the transfer of data from the DSP to the TS68950.
Input buffers are high-impedance devices.
Enable (E) - The enable pulse (E) is the basic timing
signal that is supplied to the TS68950. All the other
signals are referenced to the leading and trailing
edges of the Epulse.
ClK
LnJIIlIlJLJUL
lEAD
Transmit Conversion Clock (TxCClK)
The conversion clock TxCCLK must be derived from
the master clock CLK. Three nominal values are possible: 9.6 kHz, 8 kHz and 7.2 kHz. 9.6 kHz is the
highest allowable frequency. To run properly the
TxCCLK clock must be a submultiple of CLK/5:
3·70
TxCClK x 5 x N = ClK (with N integer)
Control register (RC4)
This is ensured when using the TS68952 clock
generator.
The sampling clock of the switched capacitor filter
section is obtained by dividing the ClK frequency by
five and performing internal synchronization on the
leading edges of TxCClK.
The Tx samples are converted from digital to analog
during the low state of TxCClK. The estimated echo
samples are converted during the high state of
TxCClK.
The RC4 control register has two different functions.
Its four most significant bits give the transmit attenuator gain following the table below.
07
Attenuation (dB)
0
0
0
0
0
0
1
2
0
0
I
0
4
0
0
1
1
6
0
1
0
0
8
0
1
0
1
10
0
1
1
0
12
0
1
1
1
14
1
0
0
0
16
320 ns cycle
number
1
0
0
1
18
1
0
1
0
20
2
1
0
1
1
22
1
1
0
0
Infinite
1
1
0
1
Infinite
1
1
1
0
Infinite
1
1
1
1
Infinite
I
2
I
0
ARC address register
I
I
I
RC4 control register (if addr....d
by ARCI
I
Sample registers (TR1 and TR2)
TR 1 is the transmitted sample register and TR2 the
estimated echo sample register. TR1 and TR2 store
two's complement 12 bit data (DACO to DAC11). As
indicated below, writing each sample requires two
cycles.
First
cycle
lo:clo:clo~clo~cl
03
X
-
0
0
04
RC4 REGISTER
0
TR2 estimated echo sample
register
05
EM2 EMI
DO
1
TR1 transmitted sample register
06
01
2
0
07
03 02
3
Internal addressing
0
04
4
Power-on
The chip contains internal power-on reset logic to
initialize the RC4 control register in order to avoid
undesirable signal transmission on the telephone
line.
Access
05
ATT ATT ATT ATT -
INTERNAL CONTROLS
RSO RSI
06
02
01
DO
X
X
X
Depending on the EM 1 and EM2 states in the RC4
register, the programmable analog input(EXI)can be
connected to the filter input or to the transmit attenuator input.
07
06
05
04
03 02
ATT ATT ATT ATT
4
Second
cycle
An internal flip-flop is used to select the first or the
second byte. It advances one count on the positivegoing edge of the Epulse when the sample registers
are selected (CSO = 0, CS1 = 1 and RSO = 0). When
the sample registers are disabled, the latch is reset
on any E positive-going edge. Both TR1 and TR2
registers are sampled by the DAC on the falling edge
of TxCClK. Therefore their contents must remain stable during this edge.
3
2
1
01
DO
RC4 REGISTER
-
EXIINPUT
EM2 EMI
0
0
disabled
0
1
transmit filter input
1
0
transmit attenuator input
1
1
disabled
Following power-up, all RC4 bits are preset at one,
EXI input is disabled and the transmit signal is cancelled.
DO and D3 bits are not used in the RC4 register.
3-71
The address of the ARC register is automatically
increased by one each time the control register is
accessed. This allows indirect or cyclical addressing
to RC4.
Address register (ARC)
The address register stores 3 bits (05, 06 and 07).
Among the 8 possible addresses, only one is used
inside the TS68950 (RC4 address).
EEO OUTPUT WAVEFORM
01
RC 4
06
05
0
04
03
02
01
DO
x
x
x
x
x
The EEO output is not valid during S/H sampling.
The outP'lt presents at this time the S/H offset voltage.
This off5;et voltage appears at the 24th ClK period
after risl) transition of TxCClK and disappears at the
31th.
X: don't care
Waveform
CLK
L.f1.
___ n n n2~n t--'r"l,,~JL.J"lJLfL
o
i1
-.r---1
•
TxCCLK
-'
2'4-'
2'5-'
29
30
31
32
sample
Offset Volt;;,qe
EEO
MAXIMUM RATINGS
Symbol
Value
Unit
DGND digital ground to AGND analog ground
- 0.3 to +0.3
V
V+ supply voltage to DGND or AGND ground
- 0.3 to +7
V
V- supply voltage to DGND or AGND ground
-1 to +0.3
V
V
Rating
.
Voltage at any digital input or output
VI
tlGNO - 0.3 to V+ + 0.3
Voltage at any analog input or output
V in
V- - 0.3 to V+ +0.3
V
Analog output current
'out
-10to+10
mA
Ptot
500
mW
Operating temperature range
tamb
Oto +70
Storage temperature range
t stot
65to+150
°c
°c
Power dissipation
Pin temperature hioldering 10
i.l
tsold
3-72
+260
°c
tions of this specification is not implied. Exposure to
maximum rating conditions for extended periods
may affect device reliability. Standard CMOS handling procedures should be employed to avoid possible damage to device.
Stresses above those listed under "Maximum
Ratings" may cause permanent damage~ to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational secELECTRICAL OPERATING CHARACTERISTICS
Symbol
Characteristic
Min
Typ
Max
Unit
Positive Supply Voltage
V+
4.75
5
5.25
v
Negative Supply Voltage
V-
- 5.25
- 5.0
-4.75
V
V+ OperatIng current
1+
-
15
rnA
V
I
-15
-
mA
Operating current
D.C. AND OPERATING CHARACTERISTICS
Unless otherwise noted. electrical characteristics are specified overthe operating range. Typical values are given
5 V and tamb 25°C.
for V' + 5 V. V-
=
=-
=
DIGITAL INTERFACE
Min
Symbol
Parameter
Typ
VIL
Input low level voltage
Max
0.8
Unit
V
V
Input high level voltage
VIH
2.2
Input low level current
DGND < VI < VILmax
IlL
-10
10
J.lA
Input high level current
VIHmin < VI < V·
IIH
-10
10
J.lA
Symbol
Min
Max
Unit
ANALOG INTERFACE. EXI PROGRAMMABLE INPUT
Parameter
Typ
Input voltage swing
Vin
-
2.5
+ 2.5
V
Input current
I Input Tx lilter selected)
lin
-10
+10
J.lA
Input capacitance
I Input ATT selected)
1< 50 kHz
I> 50 kHz
Cin
50
20
pF
pF
Input resistance
(Input A TT selected)
Rin
20
Symbol
Min
Output DC ollset
Vos
-250
Load capacitance
CL
Load resistance
RL
1200
Output voltage swing
RL >1200n
and CL < 50 pF
Vout
-2.5
Output resistance
Rout
kn
ANALOG INTERFACE. ATO TRANSMIT OUTPUT
Parameter
3-73
Typ
Max
Unit
+ 250
mV
50
pF
n
+ 2.5
V
5
n
ANALOG INTERFACE. EEO ESTIMATED ECHO OUTPUT
Parameter
Symbol
Min
Output DC offset
Vos
-100
Load capacitance
CL
Load resistance
RL
10
Output voltage swing
RL> 10 kOand
CL <50pF
Vout
-2.5
Output resistance
Rout
350
Symbol
Min
Typ
Max
Unit
+ 100
mV
50
pF
kO
+ 2.5
V
500
650
0
Typ
Max
Unit
DAC TRANSFER CHARACTERISTICS
Parameter
Converter resal ution
Nominal output peak to peak amplitude
Vout (max,
Least significant bit amplitude
LSB
Integral linearity error
Differential linearity error
12
Bit
5.0
V
1.2
mV
-1
+1
LSB
-0.7
+0.7
LSB
Max
Unit
TRANSMIT FILTER TRANSFER CHARACTERISTICS (see annexe 1)
Symbol
Parameter
Absolute passband gain at 1 kHz
GAR
Gain relative to gain at 1 kHz
without sin xix correction of OAC sampling
G RR
Below 3100Hz
3200 Hz
4000 Hz
5000 Hz to 12000 Hz
12000 Hz and above
Min
Typ
0
-0.5
-3
Absolute delay
600 Hz to 3000 Hz
DAR
dB
0.2
160
-36
-46
-50
dB
dB
dB
dB
dB
680
JlS
ATTENUATOR TRANSFER CHARACTERISTICS
Parameter
Symbol
Absolute gain at 0 dB nominal value
Min
Attenuation relative to nominal value
RAT
-6.0
Maximum attenuation
8AT
40
3·74
Typ
Max
Unit
dB
0
ATT
+0.6
dB
dB
GENERAL TRANSFER CHARACTERISTICS (from DATA BUS to ATO)
Parameter
AIO absolute gain at 1 kHz
Symbol
Min
Typ
Max
GAX
-0.5
0
+ 0.5
dB
100
pV
AID psophometric noise
Unit
ATO positive power supply rejection ratio.
Vac = 200 mVpp
f= 1 kHz
ATD negative power supply rejection ratio.
Vac = 200 mVpp
f= 1 kHz
40
dB
40
dB
dB
60
Signal to harmonic distorsion ratio (psophometric band)
GENERAL TRANSFER CHARACTERISTICS (from DATA BUS to EEO)
Parameter
EEO absolute gain at 1 kHz
Symbol
Min
Typ
Max
Unit
GAX
-0.5
0
+ 0.5
dB
100
pV
EEO psophometric noise
EEO positive power supply rejection ratio.
Vac = 200 mVpp
f = 1 kHz
40
dB
EEO negative power supply rejection ratio.
Vac = 200 mVpp
f= 1 kHz
40
dB
3-75
BUS TIMING CHARACTERISTICS (See Notes 1 and 2)
Idant
number
Characteristic
Symbol
Min
Unit
Max
1
Cycle time
tCYC
320
ns
2
Pulse width. E low level
tWEL
180
ns
3
Pulse width. E high level
tWEH
100
4
Clock rise and fall time
5
Control signal hold time
S
ns
20
tr·tf
ns
tHCE
10
ns
Control signal set-up time
tSCE
40
ns
7
Input data set-up time
tSOI
120
ns
8
Input data hold time
tHOI
10
ns
CD
G)
V
1\
@
CSO-CSI
RSD-RSI
RM
JD
G
-
0.
lK
X
-
CD
,
,
J
00-07
®
\
FIGURE 1 - BUS TIMING
Notes:
<
>
1. Voltage levels shoiNn are VL 0.4 V. VH 2.4 V. unless otherwise specified.
2. Measurement points shown are 0.8 V and 2.2 V, unless otherwise spacified.
3·76
CLOCK TIMING CHARACTERISTICS
Ident
number
Characteristic
1
ClK clock period
Symbol
Min
Pc
2
ClK phase leading clock period
3
ClK low level widlh
4
PCl
Typ
Max
Unit
695
ns
348
ns
IWCl
150
ns
ClK high level widlh
IWCH
150
ns
5
ClK rise and fall lime
IRC' IFC
100
ns
6
TxCClK rise and fall lime
IRT·IFT
100
ns
7
TxCClK delay lime
130
ns
IOC
20
00
0
@
IJ
1\
ClK
®
®
0
~
TxCC lK
®
FIGURE 2 - CLOCK TIMING
3-77
FREQUENCY
o.
.5
1.
(kHz)
3.
2.
4.
o.
-.5
-1
iD
:s
-1.5
z
;;:
"
-2
-2.5
-3
-3.5
TRANSMIT lOW-PASS FILTER TYPICAL RESPONSE AND LIMITS CHART
FREQUENCY
o.
5.
10.
(kHz)
15.
20.
25.
10.
0
-10.
iD - 20.
:s
z
«
-30.
"
-50.
-60.
-70.
- 80
TRANSMIT LOW-PASS FILTER TYPICAL RESPONSE AND LIMITS CHART
FREQUENCY (kHz)
o.
2.
1.
3.
4.
O.
-0.2
~
~
....
w
-0.4
--0.6
0
"-
:::J
0
-0.8
0:
(!)
-1.
-1.2
TRANSMIT LOW-PASS FILTER TYPICAL GROUP DELAY AND LIMITS CHART
APPENDIX 1
3-78
600
Tx signal
Estimated echo
EXI
----------------,
r
T568950
I
I
I
I
---l
I
I
I
I
I
I
I
I
I
I
I
.!..t
II)
I
I
I
t--------1
register
I
Di£:2.-Qh..K
Clock
8-bit bus
processor
T568930/31
6
CTRL
TxCCLK, RxCCLK
TxRCLK, RxRCLK
Terminal clock
CTRL ~ CSO, CS1, RSO, RS1,
E. RiW
MODEM
Tx and Rx clock
generator
T568952
RAI
-t
-<
~
I
Co)
MCU
LEI
T568951
I
Control
registers
Digital
signal
EEl
(';
MODEM
Ax analog
interface
»
.....
»
~
~
.....
(';
~
o
z
PHYSICAL DIMENSIONS
CB·68
ALSO AVAILABLE
C SUFFIX
CERAMIC PACKAGE
P SUFFIX
PLASTIC PACKAGE
" • 2,54(2)
.-,S7max.
"111
DIN
(1)
Nominal dimension
(2)
True geometric,1 position
,
CB-68
ASIC
eEl
J SUFFIX
CERCIP PACKAGE
O.A.T.A.
3·80
--,~-----11111111111111
TS68951
MODEM RECEIVE ANALOG INTERFACE
COMMUNICA TIONS PRODUCTS
DATA SHEET
CMOS
The TS68951 is the receive section of a MODEM analog front-end.
The MODEM consists of TS68950/51/52 analog front-end chip sets and
TS68930/31 digital signal processor; it is able to run voice-grade applications, which conforms to CCITT V.22/BIS, V.26/TER, V.27, V.29, V.32 and
V.33 recommendations as well as BELL 212A, 208 and 209 standards.
MODEM RECEIVE
ANALOG INTERFACE
Main features
•
•
•
•
•
•
•
•
•
•
CASE CB-132
Programmable band-pass filter.
Back channel rejection filter (selected by programming)
Reconstruction filter (selected by programming)
Continuous-time anti-aliasing and smoothing filters
Programmable gain amplifier (from 0 dB to 46.5 dB with 1.5 dB steps)
12 bit AID converter with asynchronous multiplexing of two
plesiochronous channels (one channel for echo cancellation)
Carrier level detector with programmable threshold.
Digital interface: 8 bit bi-directional data bus, 6 bit control bus.
Dual power supplies +5 V and -5 V
Designed to operate with TS68950 transmit unit and TS68952 clock
generator.
~
28
' ,
l
"
t'
1
P SUFFIX
PLASTIC PACKAGE
ALSO AVAILABLE
C SUFFIX
CERAMIC PACKAGE
J SUFFIX
CERDIP PACKAGE
PIN ASSIGNMENT
05
04
06
03
07
02
E
Dl
R/W
DO
CSO
TxCClK
CSl
RxCClK
RSO
ClK
v+
RSl
DGNO
AGC2
EEl
COl
lEI
AGC1
RFO
RAI
v-
AGND
3-81
EEl
LEI
TxCCLK
RSO
RSl
RAI
L________ ~-----------~
I
I
I
ASYNC
I
MUX
I
12 BIT
I
ADC
I
I
I
QI
~
oC')
I
r
I
Co)
---------l-------------4
'"c
I
I
Co
N
»
G)
::u
DATA
BUS
SCF
: Switched-capacitor filter
CTF
: Continuous-time filter
SCFl
: Rx band-pass filter
SCF2
: Back-channel rejection filter
SCF3
; Reconstruction filter
CTFl
: Anti-aliasing Rx I.:>w-pas$ filter
CTF2
: Smoothing low-pass filter
RCR3~:C5
k
==J
I
L _______ _
CONTROLk~==========================~
REGISTERS
RFO
AGel
CD1
RxGCLK
J
;-
s:~
PIN DESCRIPTION
Name
No.
D5·D7
1·3
E
4
Description
Data bus
Enable input. Enables selection inputs.
Active on a low level for read operation.
Active on a positive edge for write operation.
R/W
5
Read/write Selection input. Read operation is selected on a high level.
Write operation is selected on a low level.
Chip select inputs. The chip set is selected when CSO = 0 and CSI = 1.
CSO·CSI
6·7
RSO·RSI
8·9
Register select inputs. Select the register involved in a read or write operation.
DGND
10
Digital ground. All digital signals are referenced to this pin.
EEl
11
Estimated echo input. When operating in echo cancelling mode, this signal is added to the reception band·
pass filter output.
AGCl
12
Analog input of the automatic gain control amplifier and of the carrier level detector.
RFO
13
Reception filter analog output. Designed to be connected to AGCl input through a 1 pF non polarised
capacitor.
V-
14
Negative power supply. V - = - 5 V ± 5%.
AGND
15
Analog ground. All analog signals are referenced to this pin.
RAI
16
Receive analog input. Analog input tied to the transmission line.
LEI
17
Local echo input. Analog input subtracted from the receive anti-aliasing filter output.
CDI
18
This pin must be connected to the analog ground through a 1 pF non polarised capacitor, in order to
AGC2
19
This pin must be connected to the analog ground through a 1 pF non polarised capacitor, in order to
cancel the offset voltage of the AGC amplifier.
cancel the offset voltage of the carrier level detector amplifier.
V+
20
Positive power supply II' =
CLK
21
Master clock input. Nominal frequency 1.44 MHz.
RxCCLK
22
Receive conversion clock.
TxCCLK
23
Transmit conversion clock.
DO·D4
24·28
+
5V
± 5%.
Data bus.
3·83
LEI
EEl
P
RSO
AS1
RAI
."
.... 15
.:; e
0
"
.m
I
I
L----------------------i
:;~
;;1
m."
12 BIT
"0
:l>e
2"
o·
.:;
AD\,,:
CIl-
rm
"""
::;0
Co)
&.
....
:1>"
2 ....
:1>:;
59
G):;
CIl;;
m
15
2:1:
:1>:1>
rr
....
."
"0
DATA
BUS
me
:1>""
.... r
mX
I
I
.... 2
I
;;:m
I
2:1>
o
I
I
L _______ _
RC3. Res k~=======~
RCS
CONTROL
V
REGISTEASr':~============='J
RFO
AGel
RxCClK
LEI
EEl
RAI
>----
-
......
......
-,\
:;;::
CTFl
+"-.J
SCFl
i5
c
N
I
-t
0
~
n
:I:
0
n
l>
z
rr-
Z
l>
r-
......
Z
~
lIP
ASYNC.
MUX
12 BIT
SCF3
ADC
-
r-
f-
AGC
~
-'\
RR2
..
ourpUT
REGISTER
RRl
OUTPUT
REGISTER
~
I--
==
+ t
CDR
......
f---
RSl
-
:
n
m
Cl
S/H2
I
I
I
I
I
I
I
'mm"
l>
+"-
I
I
::;;
Co>
+f\
I
I
I
'm"
do
RSO
(
1
."
UI
TxCCLK
?,
()
SiHl
OUTPUT
REGISTER
'--
M
~
r---v
CTF2
0
Cl
t
Ul
i5
z
l>
r-t
CARRIER
f---
'm"
LEVEL
DETECTOR
l>
-t
;::
m
tL _________
Z
-t
RC3, RCS
ARC
RC6
ADDRESS
REGISTER
------CONTROL
REGISTERS
RFO
~~
AGCl
RxCCLK
"
["L-
f'r-
the echo signal generated by the transmission line
mismatch: this undesirable signal is then cancelled
at the output of the Rx band-pass filter.
Programming requirements:
• Band-pass filter cut-off frequencies.
• SCFl output as input of S/H2.
• Output of S/H2 as input of SCF3 and output of
SCF3 as input of CTF2.
• AGC gain.
• Carrier level detector threshold.
Residual signal samples from S/H2 output are
coded at TxCCLK rate and can be read from receive
register 2 (RR2), hence the signal processor may
correlate them with the transmit samples to update
the coefficients of the filter that generates the estimated echo.
The receive signal samples are coded at RxCCLK
rate and can be read from receive register 1 (RR1).
FUNCTIONAL DESCRIPTION
The TS68951 is a receive analog interface for voicegrade MODEM. It is able to perform the receive
interface function for three types of synchronous
MODEM:
• Four-wire or two-wire half duplex MODEM.
• Two-wire full duplex band-split MODEM.
• Two-wire full duplex echo cancelling MODEM.
Four-wire or two-wire half duplex MODEM and
two-wire band-split MODEM
In these modes of operation, EEl input must be tied
tothe analog ground. The analog signal treatment of
receive input is shown in figure 1.
Programming requirements:
• Band-pass filter cut-off frequencies.
• Back channel rejection filter(presence or absence
according to the application).
• SCFl or SCF2 output as input of CTF2.
• AGC gain.
• Carrier level detector threshold.
FUNCTIONAL SPECIFICATIONS
Bus and Registers Control
For any operatiQD...involving bus and regist~ the
chip select bits CSO and CS 1 must be valid (CSO =0
and CSl = 1).
The seven internal registers are divided in four write
only registers and three read-only registers.
The receive samples are coded at RxCCLK rate and
can be read from receive register (RR1).
Two-wire echo cancelling MODEM
This mude of operation uses the full capabilities of
the TS68951. The analog treatment of receive input
is shown in figure 2. The echo cancelling operation
is achieved by means of subtraction of the LEI signal
from the output of CTFl duplexer and addition of the
EEl signal to the output of SC1.
After the local echo reduction by the duplexer the
resultant signal consists of the receive signal plus
Write operation
There are three control registers (RC3, RC5, RC6)
and one address register (ARC) which can be written; but only ARC can be directly addressed.
The control re,gisters are indirectly addressed by the
word contained in ARC according to table 1.
Word contained in ARC
Addressed control
register
07
OS
05
04
03
02
01
DO
RC3
0
1
0
X
X
X
X
x
RC5
1
0
0
X
X
X
X
X
RCS
1
0
1
X
x
X
X
X
X: don't care
TABLE 1
When a write operation is selected (refer to table 3)
the data..eresent on the bus are strobed on a positive
edge of E and the content of ARC is incremented.
When the RMS value of CTF2 output is greater than
the programmed threshold, bit 7 of CDR is set. The
nominal response time of the carrier detector to a
signal settlement or removal is 1.78 ms.
Note: Addresses of RC3 and RC5 are separated by
two increments.
When a read operation is selected (refer to table 3)
the data are sent to the bus on a low level of E; a high
level on E sets the output bus drivers in a high
impedance state.
Read operation
There are two 12 bit receive registers (RR1, RR2)
and a 1 bit carrier detector register (CDR).
As the bus has only 8 bits, the content of RRl or RR2
must be read in two cycles. The four less significant
bits are transferred in the first cycle and the eight
most significant bits are transferred in the second
cycle according to the format, table 2.
RR2 contains the coded samples of the residual sig'nal and RRl the coded samplesofthe receive signal.
The active bit of CDR is 07: DOto 06 are forced to O.
3-86
First cycle
Second cycle
07
06
05
04
03
02
01
00
RRx3
RRx2
RRxl
RRxO
0
0
0
0
RRxll
RRxl0
RRx9
RRx8
RRx7
RRx6
RRx5
RRx4
TABLE 2
An internal latch selects the first or the second byte
ang is automatically incremented on a positive edge
of E when one of the receive registers is addressed.
This latch is'not reset at power-on, so it needs to be
reset before the first r£!.ad operation: reset occurs on
any positive edge of E for any operation, provided
none of the receive registers is addressed; the first
byte is selected when reset.
R/W
RSO
RS1
0
1
1
Write control register addressed by ARC
0
1
0
Write address register (ARC)
1
0
1
Read receive register 2 (RR2) (Residual signal sample)
1
0
0
Read receive register 1 (RR1) ( Receive signal sample)
1
1
0
Read carrier detector register (CDR)
Operation
TABLE 3
they must be initialized from program before .reading any word from the output registers.
RR1 and RR2 output code:
The output code is a 2's complement delivering
values from - 2048 up to 2047. Since the converter codes voltage between - V ref and V ref, the
theoretical decision voltage corresponding to code C
can be computed as follows:
+
Vc=
2C+ 1
+
Register RC3
The content of RC3 sets the - 3 dB cut-off frequencies of SCF1 receive band-pass filter, determines
the presence or the absence of SCF2 back channel
rejection filter and of SCF3 reconstruction filter, and
selects receive signal path to the second filtering
section; without echo- cancelling the output of
SCF1 or SCF2 is selected; with echo-cancelling the
output of S/H2 is selected.
Vref
4095
where V ref is the reference voltage of the AID
converter, V ref nominal value is2.5 Vand C
is the algebraic value of code C.
Example:
Assume the output code is the hexadecimal value
$8B 1; the algebraic value of this code C = - 1871
therefore Vc = - 2.283 V.
The band-pass filter consists of a 5th-order elliptic
low-pass filter and of a 2nd order high·pass filter
whose cut-off frequencies can be programmed by
(LP1, LP2)and (HP1, HP2) respectively, (refer table 4).
The rejection filter is present when REJ bit is high.
CONTROL REGISTERS DESCRIPTION
The reconstruction filter is present when REC bit is
high.
Power-on
The control registers are not initialized at power-on;
S/H2 output is selected when S/A bit is high.
3-87
07
HP2
06
HP1
05
LP2
04
LP1
03
REJ
02
S/A
01
REC
DO
RC3 REGISTER
LOW·PASS FILTER
0
0
1
1
0
1
0
1
Sampling frequency
(kHz)
- 3 dB Cut·off freq.
(Hz)
72
144
288
288
800
1600
3200
3200
X
X
X
X
HIGH·PASS FILTER
0
1
1
X
0
1
0
0
0
Sampling frequency
(kHz)
- 3 dB Cut·off fraq.
(Hz)
36
72
144
250
500
1600
X
X
X
HIGH·PASS AND REJECTION FILTER
1
1
0
1
1
1
X
X
Sampling
freq. (kHz)
- 3 dB Cut·off
freq. (Hz)
Rejected band
(Hz)
72
144
800
2200
370·470
800·1600
S/H2 SELECTION
0
1
X
X
Deselected
Selected
RECONSTRUCTION FILTER SELECTION
0
1
X
X
Deselected
Selected
TABLE 4
X: don't care
3·88
ISampling frequency = 288kHz)
Register Re5
The content of RC5 sets the gain of the AGC amplifier between 0 dB and 46.5 dB with 1.5 dB steps.
Note:
The AGC loop control is performed by the
signal processor.
07
06
05
04
03
02
01
DO
0
0
0
0
0
X
X
X
0
1.5
RC5
AGC gain (dB)
0
0
0
0
1
X
X
X
0
0
0
1
0
X
X
X
3
1
4.5
0
0
0
1
X
X
X
0
0
1
0
0
X
X
X
6
0
1
X
X
X
7.5
0
0
1
0
0
1
1
0
X
X
X
9
0
0
1
1
1
X
X
X
10.5
0
1
0
0
0
X
X
X
12
0
1
0
0
1
X
X
X
13.5
0
1
0
1
0
X
X
X
15
0
1
0
1
1
X
X
X
16.5
0
1
1
0
0
X
X
X
18
0
1
1
0
1
X
X
X
19.5
0
1
1
1
0
X
X
X
21
0
1
1
1
1
X
X
X
22.5
1
0
0
0
0
X
X
X
24
1
0
0
0
1
X
X
X
25.5
1
0
0
1
0
X
X
X
27
1
0
0
1
1
X
X
X
28.5
1
0
1
0
0
X
X
X
30
1
0
1
0
1
X
X
X
31.5
1
0
1
1
0
X
X
X
33
1
0
1
1
1
X
X
X
34.5
1
1
0
0
0
X
X
X
36
1
1
0
0
1
X
X
X
37.5
1
1
0
1
0
X
X
X
39
1
1
0
1
1
X
X
X
40.5
1
1
1
0
0
X
X
X
42
1
1
1
0
1
X
X
X
43.5
1
1
1
1
0
X
X
X
45
1
1
1
1
1
X
X
X
46.5
TABLE 5
X: don't care
3·89
----
.
-------
The threshold values are grouped by pair; values
belonging to each pair have 2.5 dB separation which
allows the signal processor to perform software
hysteresis.
Register RCS
The content of RC6 sets the carrier level detector
threshold. (Refer to table 6).
07
06
. _ - - - - /--
05
04
03
01
02
DO
RC6
Threshold (dBm)
•.
_-0
1-.
1--
0
0
X
X
X
X
X
- 29.85
0
0
1
X
X
X
X
X
-27.35
0
1
0
X
X
X
X
X
- 36.65
0
1
1
X
X
X
X
X
-34.15
1
0
0
X
X
X
X
X
-46.75
1
0
1
X
X
X
X
X
-44.25
1
1
0
X
X
X
X
X
-46.75
1
1
1
X
X
X
X
X
-44.25
TABLE 6
X: don't ca re
AID CONVERSION
The AID converter is a 12 bit resolution, 8 bit minimum integral linearity, monotonic converter. The
input voltage ranges from - 2.5 V to + 2.5 V; and the
conversion time is better than 50 115.
CLOCK
The master clock CLK, the receive conversion clock
(RxCCLK) and the transmit conversion clock
(TxCCLK) are generated in the TS68952 clock generator. There are three possible frequencies for the
conversion clocks: 7.2 kHz, 8 kHz and 9.6 kHz.
The frequency of RxCCLK and TxCCLK is controlled
by two independant Digital Phase Locked Loops
(DPLl). TxCCLK can be synchronised on an external
Terminal Clock (TxSCLK) or on the Rx bit rate clock;
in these cases 350 ns discrete phase shifts occurs
on ClK and TxCClK synchronously with TxCCLK
negative edge with a repetition rate of 600 Hz, 800
Hz or 1000 Hz according to the programmation of
RCl control register in the TS68952.
ASYNCHRONOUS MULTIPLEXING
Samples on the output of S/H 1 and S/H2 are
converted respectively at RxCCLK frequency and
TxCCLK frequency. Since RxCClK and TxCCLK are
plesiochronous, the order of conversion is determined by an asynchronous logic. The output register
RRl and RR2 are respectively loaded on the negative edge of RxCCLK and TxCCLK.
AGe and CLD AMPLIFIERS
The AGC consists of two cascaded amplifiers Aland
A2, fig. 3. AC coupling is obtained from Cl and C2
external capacitors. C2 can be used as an auxiliary
input for performing an analog loop located after
echo cancellation. The carrier level detector (CLD)
amplifier A3 also needs an external capacitor C3.
TO CARRIER
LEVEL DETECTOR
COl
Ax FILTER
1-<>4'-<>--~.A,J\,"v----,
RFO
C3~
AGC1
TO AID
CONVERTER
AGC2
ANALOG GROUND
C2~
FIGURE 3. Rx AMPLIFIERS SCHEMATIC
3·90
ELECTRICAL SPECIFICATIONS
The electrical specifications are given for operating temperature range (OOC, 70°C).
MAXIMUM RATINGS
Rating
Symbol
Supply voltage between V + and AG NC or DG NO
Supply voltage between V- and AGND or DGND
Voltage between AGND and DGND
Value
Unit
- 0.3 to + 7
V
-7to+D.3
V
-0.3 to + 0.3
V
Digital input voltage
DGND-0.3 to V++0.3
V
Digital output voltage
DGND-0.3 to V+ +0.3
V
Digital output current
- 20 to + 20
mA
Analog input voltage
V CC -0.3 to V++0.3
V
Analog output voltage
V CC -0.3 to V++O.3
V
-1010+10
mA
Analog output current
500
mW
Toper
010 + 70
'c
Tstg
- 65 to + 150
'C
Power dissipation
Operating temperature
Storage temperature
POWER SUPPLIES
DGND = AGND = 0 V
Symbol
Characteristic
Min
Typ
Max
Unit
Positive power supply
V+
4.75
-
5.25
Negative power supply
V-
-5.25
-
-4.75
V
Positive supply current (receive signal level 0 dBm)
1+
-
-
20
mA
Negative supply current (receive signal level 0 dBm)
1-
-20
-
-
mA
Symbol
Min
DIGITAL INTERFACE
Control inputs
Voltages referenced to DGND
V
=0 V
Characteristic
Typ
Max
Unit
-
0.8
V
Low level input voltage
V IL
-
High level input voltage
VIH
2.2
-
-
Low level input current DGND < VI
V IL
-10
-
10
/lA
VIH
-10
-
10
/lA
Symbol
Min
Typ
Max
Unit
< 0.8 V
High level input current 2.2 V < VI < V+
DATA BUS
Voltages referenced to DGND
V
=0 V
Characteristic
Low level input voltage
V IL
-
-
0.8
V
High level input voltage
VIH
2.2
-
-
V
Low level output voltage (lOL
~
2.5 mAl
VOL
-
-
0.4
V
High level output voltage (IOL
~
2.5 mAl
VOH
2.4
-
-
V
10Z
-50
-
50
/lA
High impedance output current
(when
Eis high
and DGND
< VI < V+)
3-91
ANALOG INTERFACE
All voltages referenced to AGND
=0 V
Characteristic
Input voltage EEI,LEI,RAI
Input current EEI,LEI,RAI (- 2.5 V < Yin
< 2.5 V)
Symbol
Min
Typ
Max
Unit
Vin
-2.5
-
2.5
V
lin
-I
-
I
pA
Input resistance AGC 1, AGC2
Ai"
1.5
-
-
kO
Input resistance CDl
Rin
D.7
-
-
kO
Vout
-2.5
-
2.5
V
Rout
-
2
0
-
kO
5D
pF
Max
Unit
Output voltage RFO C L= 5D pF, R L= I kO
Load resistance RFO
RL
I
-
Load capacitance RFO
CL
-
-
Symbol
Min
Typ
-
-
ns
Output resistance RFO
BUS TIMING CHARACTERISTICS
(See foot notes 1 and 2 on timing diagrams)
Characteristic
Cycle time
(1)
tCYC
320
(2)
tWEL
18D
-
-
ns
Pulse width E high level
(3)
tWEH
100
-
-
ns
Clock rise and fall timE:!
(4)
t r , 11
-
-
20
ns
Control signal hold time
(5)
tHCE
10
-
ns
Control signal set-up time
(6)
tSCE
40
-
Input data set-up time
(7)
tSDI
120
Input data hold time
(8)
tHDI
Output data set-up time
(9)
Pulse width
Elow level
(I TIL load and C L= 50 pF)
Output high impedance delay time
(I TIL load and C L= 50 pF)
-
ns
-
ns
10
-
-
ns
tSDO
-
-
150
ns
tdz
-
-
80
ns
(10)
RECEPTION CHARACTERISTICS
PERFORMANCE OF THE WHOLE RECEPTION CHAIN (input RAI or LEI. output RR1)
Characteristic
Gain.
(AGC gain = 0 dB, RxCCLK = 9600 Hz, Vin=775mV eff,1 = 2000 Hz)
Symbol
Min
Typ
Max
Unit
G
-0.5
-
0.5
dB
TO
-
-
-58
dB
-
1.2
mVel!
Typ
Max
Unit
-
-72
dB
Total harmonic distortion
(AGC gain = 0 dB, RxCCLK = 9600 Hz, V in =775mV elf, 1= 2000 Hz)
.-~-'."
Equivalent RMS noise
(AGC gain = 0 dB, RAI, LEI. EEl tied to AGND)
N
-.
j
Note: Noise depends on AGe gain value.
PERFORMANCE OF THE RECEPTION SUB-CHAIN (from RAI inp\i'{ 10 S/H2 input)
Parameter
Symbol
Total distortion
(RxCCLK = 9600 Hz, Yin = 1.6 Veil, I = 2000 Hz)
TD
Mi~
I
-
I
3-92
WRITE OPERATION
(2)
(3)
/
1\
CSO-CSl
RSO-RSl
R/W
G
0
@
-~
0.
K
®
0
,
)
00-07
\
F
READ OPERATION
G)
CD
II
1\
CSO-CSl
RSO-RSl
R/W
00-07
-
@
~
0
G)
®
:K
@
@
,
J
1\
V
....
Notes:
1. Voltage levels shown are VIL < 0.4 V. VIH > 2.4 V. unless otherwise specified.
2. Measurement points shown are 0.8 V and 2.2 V. unless otherwise specified.
3-93
RECEIVE BAND-PASS FILTER AND REJECTION FILTER (inputRAI. output RFO)
Characteristic
Symbol
Typ
Max
Unit
-0.5
-
0.5
dB
-0.4
-
-
0.3
0.3
-60
dB
dB
dB
Min
Low-P ••• filter IFs=288kHz)
Reference gain
(V in = 775 mV elf• f = 1800 Hz)
Grel
Relative gain to Gref
o Hz < f < 3000 Hz
1= 3200 Hz
f > 6250 Hz
Grel
Group propagation delay time
(I = 1800 Hz)
Tgp
-
-
300
ps
Tgpd
-
-
360
ps
-0.5
-
0.5
dB
-0.4
-3
-
dB
dB
dB
-3
Group propagation delay time distortion
(600 Hz < I
< 3000 Hz)
High-Po •• filter (F.=72kHz)
Reference gain
(Vin 775 mVefl . f = 1800 Hz)
Gref
Relative gain to Gref
Grel
=
o Hz < I <
3000 Hz
-
-
0.3
0.5
-25
Group propagation delay time
(f
1800 Hz)
Tgp
-
-
50
ps
Group propagation delay time distortion
Tgpd
-
.-
450
ps
-1
-
0
dB
-
-
-
-
-25
-27
-30
-27
0
dB
dB
dB
dB
dB
f = 500 Hz
f< 100Hz
c---
=
f-------.
-
(600 Hz < f < 3000 Hz)
High-Pa •• filter and rejection filter IF. =72kHz)
Reference gain
(Vin = 775 mVefl • f = 1800 Hz)
Grel
Relative gain to G ref
1= 100Hz
1= 370 Hz
390 Hz < I < 450 Hz
1=410Hz
f = 900 Hz
Grel
Group propagation delay time
(I = 1800 Hz)
TJ'.J
-
-
75
ps
Tgpd
-
-
1400
ps
Group propagation delay time distortion
-
(600 Hz < f < 3000 Hz)
Note: The measurement frequencies are integer sub-multiples of filters sampling frequencies.
3-94
RECONSTRUCTION FILTER
Symbol
Characteristic
Reconstruction filter
Reference gain
Min
Typ
Max
Unit
-
0.3
dB
-
IF. 288kHz)
Grel
-0.3
(V in = 775 mV ell . I = 2000 Hz)
G rel
Relative gain to Gref
o Hz < I < 2900 Hz
-0.4
-3
-
--
0.3
0.3
-60
dB
dB
dB
Tgp
-
-
300
I1S
Tgpd
-
-
440
/1S
-
0.5
dB
-
300
1=31ooHz
I> 6000 Hz
Group propagation delay time
(I = 1800 Hz)
Group propagation delay time distortion (600 Hz < I
< 3000 Hz)
Whole reception filtering chain (input RAI or LEI. output RFO)
Reference gain
Grel
-0.5
(V in = 775 mV ell • I = 2000 Hz. RC3 = $AO)
Noise on RFO
(RAI. LEI. EEl tied to AGNO 250 Hz < I
Nrlo
< 3200 Hz)
-
/1V. ff
I
PERFORMANCE OF RESIDUAL SIGNAL CHANNEL AND AID CONVERTER
(input EEl. output RR2)
Characteristic
Symbol
Min
Typ
Max
Unit
-
5
V
Vin
-
AID converter resolution
Resh
-
-
12
Bit
Analog increment
LSB
-
1.2
-
mV
LSB
Input voltage (peak to peak)
Integral linearity error
Differential linearity error
Offset voltage
..
-
Eil
-16
-
16
Edl
-0.7
-
0.7
LSB
Vas
-100
-
100
LSB
Min
Typ
Max
Unit
-0.5
-1
-
-
0.5
1
dB
dB
Vas
-70
-
70
LSB
Symbol
Min
Typ
Max
Unit
-0.5
-1
-
0.5
1
dB
dB
2
-
3
dB
-1
-2
-3
-
1
2
3
mV
mV
mV
3
ms
AGC AMPLIFIER AND AID CONVERTER (input AGC1, output RR1)
Symbol
Characteristic
Relative gain to programmed gain
Grel
o dB .; AGC .; 24 dB
25.5 dB .; AGC'; 46.5 dB
Offset voltage
CARRIER LEVEL DETECTOR (input AGC1, output CDR)
Characteristic
Relative threshold to programmed gain
OdB < AGC < 24 dB
25.5 dB .; AGC'; 46.5 dB
Trel
Hysteresis
Hyst
Input ollset voltage
1st threshold pair
Vas
2nd threshold pair
3rd threshold pair
Detection delay time
Tdd
o mVel1 to 775 mV eff
transition
or 775 mVeff to 0 V eff transition
3-95
1
-
-
4.
.5
o.
-.6
-1.
iD
:!2
z
-1.5
Cl
-2.
;{
-2.5
-3.
-3.5
Rx LOW.PASS FILTER TYPICAL RESPONSE AND LIMITS CHART IFs=288kHzl
FREQUENCY IkHzl
o.
20.
5.
25.
10.
o.
-10.
-20.
iD
:!2
z
;{
Cl
-30.
-40.
-50.
-60.
-70.
-80.
Rx LOW·PASS FILTER TYPICAL RESPONSE AND LIMITS CHART IFs=288kHzl
FREQUENCY IkHzl
o.
o.
2.
1.
3.
4.
-.1
-.2
]
-.3
>
-.4
«..J
w
-.5
0
"-
-.6
0
-.7
:J
II:
Cl
-.8
-.9
-1.
Rx LOW·PASS FILTER TYPICAL GROUP DELAY TIME AND LIMITS CHART IFs=288kHzl
3-96
FREQUENCY (kHz)
.25
O.
1.
.75
.5
5.
O.
-5.
-10.
iii
3!
z
-15.
'-'
-20.
:;;:
-25.
-30.
-35.
Rx HIGH·PASS FILTER TYPICAL RESPONSE AND LIMITS CHART (F.=72kHz)
FREQUENCY (kHz)
.8
1.6
2.4
3.2
4
Rx HIGH·PASS FILTER TYPICAL GROUP DELAY TIME AND LIMITS CHART (Fs=72kHz)
3-97
FREQUENCY (kHz)
O.
.5
O.
-.5
-1.
iii
-"
z
<'
"
-2.
-3.
-3.5
Rx BAND-PASS FILTER TYPICAL RESPONSE AND LIMITS CHART
(HP: F.=72kHz, LP. F.=288kHz)
FREQUENCY (kHz)
o.
O.
-.1
-.2
!
><>:
..J
w
0
"OJ
0
-.3
-.4
-.5
-.6
II:
-.7
"
-.8
-.9
-1.
Rx BAND-PASS FILTER TYPICAL GROUP DELAY TIME AND LIMITS CHART
(HP: F.=72kHz, LP: Fs=288kHz)
3·98
FREQUENCY IkHzl
O.
2.
1.
3.
4.
2.
O.
-2.
m
-4.
~
z
;;:
-Q.
c.:J
-8.
-10.
-12.
Rx BAND-PASS AND REJECTION FILTER TYPICAL RESPONSE AND LIMITS CHART
IHP AND REJ. : Fs=72kHz. LP: Fs=2BBkHzl
FREQUENCY IkHzl
4.
2.
O.
5.
O.
-5.
-10.
iii
~
z
;;:
c.:J
-15.
-20.
-25.
-30.
-35.
Rx BAND-PASS AND REJECTION FILTER TYPICAL RESPONSE AND LIMITS CHART
IHP AND REJ. :Fs=72kHz. LP: F.=2BBkHzl
FREQUENCY IkHzl
O.
o.
2.
1.
3.
4.
-6.
~
>..:
-1.
-'
-1.4
0
":l
-1.8
II:
c.:J
-2.2
w
0
-2.6
-3.
Rx BAND·PASS AND REJECTION FILTER TYPICAL GROUP DELAY TIME AND LIMITS CHART
IHP AND REJ. : F.=72kHz. LP: Fs=288kHzl
3-99
FREQUENCY (kHz)
.25
5.
.75
.5
I.
o.
-5.
iii
-10.
::g
z
-15.
(!)
-20.
;;:
-25.
-30.
-35.
Rx HIGH·PASS AND REJECTION FILTER TYPICAL RESPONSE AND LIMITS CHART (Fs=72kHz)
FREQUENCY (kHz)
o.
1.
2.
3.
4.
5.
o.
-5.
-10.
iii
::g
z
-15.
(!)
-20.
;;:
-25.
-30.
-35.
V:
Rx BAND-PASS FILTER TYPICAL RESPONSE FOR 22 MODE (LOW CHANNEL)
(HP: F.=72kHz, LP.: fo=l44kHz)
FREQUENCY (kHz)
o.
o.
3.
4.
-.2
-.4
!
>
c(
-.6
-.8
..J
o
W
-1.
0;:)
-1.2
a:
-1.4
o
(!)
-1.6
-1.8
-2.
Rx BAND-PASS FILTER TYPICAL GROUP DELAY TIME FOR V.22 MODE (LOW CHANNEL)
(HP: Fs=72kHz, LP: Fs=144kHz)
3-100
FREQUENCY (kHz)
o.
5.
3.
1.
4.
o.
-5.
iii
:!1
z
=i
"
-10.
-15.
-20.
-25.
-30.
-35.
Rx BAND·PASS FILTER TYPICAL RESPONSE FOR V.22 MODE (HIGH CHANNEL)
(HP AND REJ.: Fs=144kHz. LP: Fs=2B8kHz)
FREQUENCY (kHz)
o. o.
2.
1.
3.
4.
-.2
-.4
!>-
-.6
..J
OJ
-1.
<
...J
-.4
w
0
-.5
a..
:;)
0
..,
a:
-.6
-.7
-.8
-.9
-1.
RECONSTRUCTION FILTER TYPICAL GROUP DELAY TIME AND LIMITS CHART
3·102
25.
PHYSICAL DIMENSIONS
CB-132
ALSO AVAILABLE
C SUFFIX
CERAMIC PACKAGE
J SUFFIX
CERDIP PACKAGE
e=2,54(2j
P SUFFIX
PLASTIC PACKAGE
457mo~.
Q2
Q,3
15,24
21
t:=>------ ------- 0'(
Datum
0
1'7'
, .... ,_n...........
Nominal dimension
(2) Truegeometricalposition
,.
Yn-
38.1 mal<.
DIN
28.,",
,
C8-132
A51E
CEI
(1)
OA.T.A
3-103
3·104
=:J
DATA SHEET
The TS68952 generates all the clock frequencies needed to implement
standard voice-grade MODEMS up to 19200 bps according to the CCITT
V.22, V.26, V.27, V.29, V.32 and V.33 or BELL 212A, 208 and 209 recommendations.
SILICON GATE
CMOS
MODEM TRANSMIT/RECEIVE
CLOCK GENERATOR
It can be associated with the TS68950 and the TS68951 to give a
MODEM Analog Front-End Chip Set.
CASECB-132
Main features:
• Independent Tx and Rx clock generators with Digital Phase Locked
Loops (DPLLs).
• Tx DPLL synchronization on external terminal clock or internal Rx clock.
• Four external clocks available (plesiochronous on Tx and Rx channels):
bit rate clock, baud rate clock, sampling clock and multiplexing clock.
• Chip programming and control via a standard 8 bit bus.
PSUFFIX
PLASTIC PACKAGE
ALSO AVAILABLE
CSUFFIX
CERAMIC PACKAGE
BLOCK DIAGRAM
J SUFFIX
TERMINAL CLOCK
CEROIP PACKAGE
--,
TIiSCLIC
I
T, ACLX
TxCCLIC
T.CLIC
Tx MCLIC
I
I
I
I
I
~~~~~~~{:J~tj
05
04
I
06
03
I
07
02
I
I
e-
I
I
01 :D7
TxCCLK
I
CS6
TxCLK
I
CSI
AxCLK
I
l'
AIW
I
I
OS.
RSOIRSI
FIx elK
Rx RelIC
Rx CCLl(
T1I8t3.
OR TSII93,
ASO
RxCCLK
ASI
RxRCLK
TO
RxMCLK
TxSCLK
TxMCLK
Rx MCLK
I
I
I
I~~
L___ ~_~ ______ ~~ ______ ~
DGND
V+
3·105
01
RNi
I
DSP
PIN ASSIGNMENT
OGNO
v+
XTALI
TxRCLK
XTAL2
CLK
PIN DESCRIPTION
Description
Name
No.
05-07
1-3
E
4
Enable input. Data are strobed on the positive transitions of this input
R/W
5
Read/Write selection input. Internal registers can be writtenwhen R/W
only used for Rx analog front-end chip
CSO-CS1
6-7
Chip Select inputs. The chip set is selected when CSO
RSO-RS1
8-9
Register Select inputs. Used to select address or control registers
TO
10
Test Output. Must be left open
TxSClK
11
Transmit Synchronizing Clock input. Normally tied to an external terminal clock. When this
Data bus inputs to internal registers
= O.
Reading mode is
= 0 and CS1 = 1
pin is tied to a permanent logical level, transmit DPLL free-runs or can be synchronized tathe
receive clock system.
= 0 V. All digital signals are referenced to this pin
OGNO
12
Digital ground
XTAl1
13
Crystal oscillator or pulse generator input
XTAl2
14
Crystal oscillator output
ClK
15
1.44 MHz Clock output. Useful for Tx and Rx analog front-end chips
TxRClK
V·
16
Transmit baud Rate Clock output
17
Positive power supply voltage
TxMClK
18
Transmit Multiplexing Clock output
RxMClK
19
Receive Multiplexing Clock output
RxRClK
20
Receive baud Rate Clock output
RxCClK
21
Receive Conversion Clock output
RxClK
22
Receive bit rate Clock output
TxClK
23
Transmit bit rate Clock output
TxCClK
24
Transmit Conversion Clock output
01-04
25-28
=+5 V ± 5 %
Data bus inputs to internal registers (DO is not used)
FUNCTIONAL DESCRIPTION
The TS68952 is a purely digital circuit that synthesises
all the frequencies requested to implement synchronousvoice-grade MODEMs from 1200 bpsto 19200 bps.
It consists of two clock generators using Digital Phase
Locked Loops (DPLLs). Frequency programming and
DPLL updating can be obtained through four control
registers accessed by indirect or cyclical addressing.
This circuit is a part of a three chip Modem Analog
Front-End that also includes the TS68950 transmitting
analog interface and the TS68951 receiving analog
interface.
POWER-UP INITIAL CONDITIONS
Following power-up, the eight transmit and receive
clock outputs are undefined and may deliver any frequencies. Control registers RCI and RC2 must be properly programmed to obtain the wanted operation.
INTERNAL
2.88 MHz CLOCK
DPLlOUTPUT
LEAD
LAG
FIGURE 1 - DPLl LEAD AND lAG
3-106
CLOCK GENERATION
intervention, by periodic reset of the counters.
Master clock is obtained from either a crystal tied
between XTAL1 and XTAL2 pins or an external signal
connected to the XTAL 1 pin; in this case, the XTAL2 pin
should be left open. Clock frequency nominal value is
5.76 MHz,but5.12 MHzand5.40 MHz frequencies are
also specified for particular applications.
The different transmit (Tx) and receive (Rx) clocks are
obtained by frequency division in several counters and
output selection through digital multiplexers. They can
be synchronized on external signal via two independent
digital phase locked loops (DPLL).
Immediate phasing of these clocks on the synchronizing external TxSCLK or internal RxCLK clock can be
obtained through bit 7 of RC8 register. The content of
this register is automatically cleared after phasing
completion.
TRANSMIT DPLL
RxDPLL phase shifts are performed by addition and
subtraction of pulses from an internal 1.44 MHz clock
under the control of RC8 register. Two modes of
operation are provided:
The TS68952 also delivers, on pin CLK, a 1.44 MHz
clock that is synchronous with the Tx clock system and
will be used as the main clock of the TS68950/51
analog interface circuits.
RECEIVE DPLL
As shown on figure 1, the TxDPLL operates by adding or
subtracting pulses to a 2.88 MHz internal clock, with a
reference frequency that is a submultiple of the programmed "rate clock" frequency. This corresponds to
phase leads or phase lags of about 350 ns duration,
more precisely, two master clock periods.
The Tx DPLL can be synchronized on an external terminal clock tied to TxSCLK pin or on the receive bit clock
RxCLK internally generated from the RxDPLL. It can
also free-run without any phase shift, when the TxSCLK
input is tied to a fixed logical level.
•
a coarse phase lag whose amplitude has been
loaded into RC7 register, can be controlled byone bit
of RC8 register. This mode is useful for a fast synchronization of the RxDPLL. The phase lag is
obtained by suppressing a variable number of pulses
at the input of the counters,
• a fine phase shift with lead or lag amplitude equal to
two master clock periods, can be controlled by two
bits of RC8. This mode corresponds to normal operation. The phase shifts are obtained by addition or
suppression of pulses as indicated in figure 1.
TRANSMIT CLOCKS
The TS68952 delivers four synchronous Tx clocks:
RC8 register is automatically cleared when the programmed phase shift is completed. Simultaneous programming ofTx and Rx control bitsofthis register hasto
be avoided.
•
a bit clock, TxCLK, whose frequency equals the bit
rate of the MODEM,
• a baud clock, TxRCLK, whose frequency equals the
baud rate of the MODEM,
• a conversion clock, TxCCLK, that gives the sampling
frequency of the Tx converter,
• a multiplexing clock, TxMCLK, usable when several
terminals are multiplexed on a single physical link.
RECEIVE CLOCKS
The TS68952 delivers four Rx clocks with the same
nominal frequency values as their Tx counterparts:
•
•
•
•
The frequencies of these four clocks are programmable
through RC1 and RC2 control registers. Their cyclical
ratio is exactly 1 : 2, except for the 16.8 kHz frequency
whose cyclical ratio is slightly modulated around 1 : 2,
and their relative phase locking is ensured without user
a bit clock RxCLK,
a baud clock RxRCLK,
a conversion clock RxCCLK,
a multiplexing clock RxMCLK.
The Rx and Tx output clocks are plesiochronous.
3-107
BIT CLOCK FREQUENCY PROGRAMMING (Tx AND Rx)
RCl REGISTER
07
06
05
04
HB4 HB3 HB2 HBl
03
02
OUTPUT FREaUENCY (kHz)
01
HR3 Hfl2 HRl
Fa
0
= 5.76 MHz
Fa
= 5.40 MHz
Fa
= 5.12 MHz
19.2
0
0
0
0
0
0
1
16.8
0
0
1
0
14.4
0
0
1
1
12.0
0
1
0
0
9.6
0
1
0
1
7.2
0
1
1
0
6.4
6.0
0
1
1
1
1
0
0
0
4.8
1
0
0
1
3.2
1
a
1
0
2.4
1
0
1
1
1.2
1
1
0
0
0.6
1
1
0
1
0.6
1
1
1
0
0.6
1
1
1
1
0.6
6.4
3.0
FQ = crystal oscillator frequency
RATE CLOCK FREQUENCY PROGRAMMING (Tx AND Rx)
RCl REGISTER
07
06
05
04
03
02
OUTPUT FREaUENCY (kHz)
01
HB4 HB3 HB2 HBl HR3 HR2 HRl
Fa
= 5.76 MHz
0
0
0
2.4
0
0
1
2.0'
O.
1
0
1.6"
0
1
1
1.2
1
0
0
0.6
1
,
0
1
0.6
1
a
0.6
1
1
1
0.6
Fa
= 5.40 MHz
Fa
= 5.12 MHz
2.133
1.5
-
Note: Phase shift frequency of Tx DPLL is 600 Hz except for (*) 1000 Hz and for (* *)
2000 Hz.
3-108
CONVERSION CLOCK FREQUENCY PROGRAMMING (Tx AND Rx)
RC2 REGISTER
07
06
05
04
03
02
01
-
HM3 HM2 HM1 HS2 HS1 H_THR
OUTPUT FREaUENCY (kHz)
Fa = 5.40 MHz
Fa = 5.12 MHz
0
0
Fa = 5.76 MHz
9.6
9.0
8.533
0
1
8.0
7.5
1
0
7.2
1
1
7.2
MULTIPLEXING CLOCK FREQUENCY PROGRAMMING (Tx AND Rx)
RC2 REGISTER
07
06
05
04
02
03
01
OUTPUT FREaUENCY (kHz)
-
HM3 HM2 HM1 HS2 HS1 HTHR
Fa
= 5.76 MHz
0
0
0
1440
0
0
1
288
0
1
0
12
0
1
1
9.6
1
0
0
7.2
1
0
1
4.8
1
1
0
2.4
1
1
1
1.2
Tx SYNCHRONIZATION SIGNAL PROGRAMMING
RC2 REGISTER
07
06
05
04
03
02
01
-
HM3 HM2 HM1 HS2 HS1 HTHR
SYNCHRONIZATION SIGNAL
0
RxClK
TxSClK (note 1)
1
Note: 1 - TxDPLL free-runs if there is no transition on this input.
Tx CLOCK GENERAL RESET
RCB REGISTER Inotes 2.31
07
06
05
04
02
03
MPEISPRIAVREIVALIINITI-
1
I
0
I o I
0
I
0
I
RESETTING TRANSITION
01
1I
Next negative·going transition on synchronization clock
Note: 2 - RCB register is cleared after the programmed control operation is completed.
Note: 3 - INIT bit is only used for test purpose
3-109
Rx CLOCK PHASE SHIFT PROGRAMMING
RCB REGISTER (note 21
D7
D6
D5
D3
D4
MPE SPR AVRE VAL INIT
D2
D1
-
-
ACTION ON Rx DPLL
0
0
Phase lag of programmed amplitude
0
1
0
Phase lag of two main clock periods
1
1
0
Phase lead of two main clock periods
0
1
0
0
0
0
0
Rx CLOCK PHASE SHIFT AMPLITUDE PROGRAMMING
RC7 REGISTER
D7
D6
D5
D4
03
D2
D1
SP5
SP4 SP3
SP2
SPI
-
-
PHASE SHIFT IN DEGREES
1600 bauds
1200 bauds'
NUMBER OF MASTER CLOCK
PULSES SUPPRESSED
0
0
0
0
0
1.5
2
20
0
0
0
0
1
3
4
40
0
0
0
1
0
4.5
6
60
0
0
0
1
1
6
8
80
0
0
1
0
0
7.5
10
100
0
0
1
0
1
9
12
120
0
0
1
1
0
10.5·
14
140
0
0
1
1
1
12
16
160
0
1
0
0
0
13.5
18
180
0
1
0
0
1
15
20
200
0
0
1
0
1
0
16.5
22
220
1
0
1
1
18
24
240
0
1
1
0
0
19.5
26
260
0
1
1
0
1
21
28
280
0
1
1
1
0
22.5
30
300
0
1
1
1
1
24
32
320
1
0
0
0
0
22.5
30
300
1
0
0
0
1
45
60
600
1
0
1
0
67.5
90
900
1
0
0
0
1
1
90
120
1200
1
0
1
0
0
112.5
150
1500
1
0
1
1
135
180
1800
1
0
1
0
1
0
157.5
210
2100
1
0
1
1
1
180
240
2400
1
1
0
0
0
202.5
270
2700
1
1
0
0
1
225
300
3000
1
1
0
1
0
247.5
330
3300
1
1
1
1
270
360
3600
1
1
0
1
0
0
292.5
3900
1
1
1
0
1
315
4200
1
1
1
1
0
337.5
4500
1
1
1
1
1
360
4800
1*) 2400 bauds: multiply by two. 600 bauds: divide by two.
3-110
address is stored in the 3 bit ARC register. 'After each
write operation to a control register, the ARC register
value is automatically increased by one. This allows
cyclical addressing of the eight registers of the MODEM
chip set.
DATA BUS CONTROL
Six signals control the access from the bus to the internal registers according to the table and the timing diagram given below. Control registers are written using an
indirect addressing mode where the internal
R/W CSO CS1 RSO RS1
0
0
1
1
0
0
0
1
1
1
-E
ACCESSED REGISTER
S
.f
Address register ARC
Control register whose address is in ARC
BUS TIMING DIAGRAM
:~~: ~ _~_'
----'x\.___________________--Jx"-____
c_s_'__
-JX,.___I~_:_~_l___+I---JX
I
DATAB_U_S
_________
D1 : D7
VALID
\ lr----I
'---------
I
ENABLE E
'-----" I
I
DATA STROBING
DATA FORMAT
DATA LOADED IN ARC
07
06
05
ARC3
ARC2
ARC1
ADDRESSED REGISTER
0
0
0
RCI
0
0
1
RC2
1
1
0
RC7
1
1
1
RCB
3·111
MAXIMUM RATINGS
RATING
MIN.
V' supply voltage to DGND ground
Voltage at any input or output
Current at any output
MAX.
-0.3 V
7V
DGND·0.3 V
V' + 0.3 V
-20mA
20mA
Power dissipetion
500mW
Operating temperature range
Storage temperature range
OOC
700C
-65 ·C
+ 150·C
OPERATING RANGE
ELECTRICAL OPERATING CHARACTERISTICS
Unless otherwise noted. electrical characteristics are specified over the operating range. Tvpical values are given
for y+
5.0 V and tamb 25 DC.
=
CHARACTERISTIC
=
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
5.0
mA
O.BV
V
10
/lA
10
/lA
Power dissipation
Positive supply current
I'
Digital interface
Input low level voltage
VIL
Input high level voltage
VIH
Input low level current
IlL
DGND .;; VI .;; VIL max
2.2
V'
Input high level current
IIH
VIH min';; VI';;
Output low level current
VOL
10 =2.5 mA
Output high level current
VOH
10 = -2.5 mA
Input low level voltage
VIL
Input high level voltage
VIH
Input low level current
IlL
DGND .;; VI .;; VIL max
Input high level current
IIH
VIH min';; VI .;; V'
-10
-10
V
0.4
2.4
V
V
Crystal oscillator "interface
1.5
3.5
3·112
V
V
-15
/lA
15
/lA
TIMING CHARACTERISTICS
CHARACTERISTIC
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data bus access
Control signals set-up time
tSCE
~,CS1, RSO, RS1, R/Wto
E
40
ns
Control signals hold time
tHCE
CSO, CS1, RSO, RS1, R/W to E
10
ns
Data-in set-up time
tSOI
01
D7to E
120
ns
Data-in hold time
tHOI
01 : 07 to E
10
Enable signal low level width
tWE
E
CONTROL SIGNALS
CSO,CSl
RSO, RSl
R/W
2.2 V
0.8 V
tSCE
ns
180
tWE
2.2 V
ENABLE SIGNAL
E
tSOI
2.2 V
INPUT
DATA
VALID
DATA BUS
01: 07
O.B V
3-113
ns
TIMING CHARACTERISTICS (continued)
CHARACTERISTIC
SYMBOL
CONDITIONS
MIN.
TYP.
173.6
MAX.
UNIT
Clock wave forms
Main clock period
PC
XTAL1 input
150
Main clock low level width
tWCL
XTAL1 input
50
Main clock high level width
tWCH
XTAL 1 input
50
Main clock rise time
tRC
XTAL1 input
Main clock fall time
tFe
XTAL1 input
Clock output delay time
tDC
All clock outputs CL
Clock output transition time
tTC
= 50 pF
All clock outputs CL = 50 pF
ns
ns
ns
50
ns
50
ns
500
ns
100
ns
PC
tWCH
,
1/ 3.5 V
MAIN CLOCK
INPUT
XTAL 1
1.5 V
tRC
tWCL
!/
~
/
I
tDC
tFC
CLOCK OUTPUTS
(9 CLOCKS)
,
~
J
'I
2.2 V
08 V
\
tTC
3-114
V
TYPICAL APPLICATION
Tx ANALOG INTERFACE I-'A..:.T;...;O,,-_-,
TS68950
EEO
CTRL
DSP
8 BITS
Tx AND Rx
CLOCKS
TS68952
TS68930
'--r----;r-.......
TXANDRXL~~-!~~~~
__-!~JG~~==~~~
CLOCKS
MODEM ANALOG FRONT-END CHIP SET
NOTE:
zI. Digital ground
~
Analog ground
3-115
PHYSICAL DIMENSIONS
CB·132
ALSO AVAILABLE
C SUFFIX
PSUFFIX
CERAMIC PACKAGE
PLASTIC PACKAGE
JSUFFIX
CEROIP PACKAGE
15,24
-:t~::~~=~:JL~ =~28.,...
,
~
A51E
eEl
C8-132
D.A.T."'.
3-116
CHAPTER 4 - SUBSCRIBER LINE CARD
COMPONENTS
----
TS5070 • TS5071
--~~-
MONOLITHIC PROGRAMMABLE CODEC/FIL TER
COMBO 2ND GENERATION
ADVANCE INFORMATION
COMMUNICATIONS PRODUCTS
ADVANCE INFORMATION
CMOS
The TS5070 series are second-generation combined PCM CODEC and Filter
devices optimized for digital switching applications on subscriber and
trunk line cards. Using advanced switched capacitor techniques, COMBO
IIG combines transmit bandpass and receive lowpass channel filters with a
companding PCM encoder and decoder. The devices are A-law and !l-Iaw
selectable and employ a conventional serial PCM interface capableof being
clocked up to 4.096 MHz. A number of programmable functions may be
CASES
controlled via a serial control port.
Channel gains are programmable over a 25.4 dB range.in each direction,
J20A
and a p'rogrammable filter is included to enable Hybrid Balancing to be
adjusted to suit a wide range of loop impedance conditions. 80th transformer and active sLie interface circuits with real or complex termination
impedances can be balanced by this filter, with cancellation in excess of
30 dB being readily achievable when measured across the passband against
standard test termination networks.
To enable COMBO IIG to interface to the SLiC control leads, a number of
programmable latches are included; each may be configured as either an
input or an output. The TS5070 provides 6 latches and the TS5071
5 latches.
•
J SUFFIX
CERDIP PACKAGE
Complete CODEC and F I LTE R system including:
-
Transmit and receive PCM channel filters
.u-Iaw or A-law companding coder and decoder
Receive power amplifier drives 300 n
- 4,096 MHz serial PCM data (max)
•
Programmable Functions:
•
Transmit gain: 25.4 dB range, 0.1 dB steps
Receive gain: 25.4 dB range, 0.1 dB steps
Hybrid balance cancellation filter
Time-slot assignment: up to 64 slotslframe
2 port assignment (TS5070)
6 interface latches (TS5070)
A or !l-Iaw
Analog loopback
Digital loopback
Direct interface to solid-state SliCs
•
•
Simplifies transformer SLlC, single winding secondary
Standard serial control interface
CB-194
~I
~l11'20
I
I
PSUFFIX
PLASTIC PACKAGE
• 70 mW operating power (typ)
• 5 mW standby power (typ)
• Meets or exceeds all CCITT and LSSG R specifications
• TTL and CMOS compatible digital interfaces
• SeconeJ source of TP3070, TP3071
CB-520
TRI-STATE l:!l , and COMBO II'J) are registered trademarks of National
Semiconductor Corporation
4-1
•
FN SUFFIX
PLCC PACKAGE
BLOCK DIAGRAM
VCC
r-------!
-&------------,i
+5V
AZ
I
DXO
OX'
i¥
HYBRID
BALANCE
FILTER
TS X'
FS X
BCLK
FS R
ORO
DR'
MCLK
MR
,
cs
I
CCLK
CO
CI
I
L ____ _
IL51L41L31L21L 1110
4-2
PIN ASSIGNMENTS
TS5070
U)
"z
.,
0a:: 0
Z
!l)u.
> >
M
"
N
TS5071
-x
"0
> >u ~
u.
III
...
N
GND
!!l
0
NC
IL3
VFRO
2S
ILl
24
IL4
VFX I
VCC
ILO
VSS
IL3
ILl
IL4
IL2
23
ILS
IL2
FSR
22
FS X
FS R
FS X
DRI
21
TS X l
ORO
TSXO
ORO
20
TSXO
CliO
DX O
CO
19
DX 1
CCLK
~
U
;! ~ :!!
'" I~
""
0:
::0
..J
'"
..J
::
~
'"
0
X
..J
"co "::0
CS
BCLK/MCLK
MR
a
PIN DESCRIPTION
POWER SUPPLY, CLOCK
Nama
Pin Type
TS5070
TS5071
VCC
5
27
19
Vss
S
3
3
Negative power supplV
-SV±S%
GND
5
1
1
Ground
All analog and digital signals afe referenced
Description
Function
Positive power supply
+ SV±S%
to this pin.
BCLK
I
16
12
Bit clock
Bit clock input used to shift PCM data into and
out of the DR and DX pins. BCLK may vary
from 64 kHz to 4.096 MHz in 8 kHz increments.
and must be synchronous with MCLK.
MCLK
I
17
12
Master clock
Master clock input used by the switched capacitor
filters and the encoder and decoder sequencing
logic. Must be 512kHz. 1.536/1.544 MHz,
2,048 MHz or 4.096 MHz and synchronous with
BeLK.
TRANSMIT SECTION
FSx
I
22
lS
Transmit frame sync.
Normally a pulse or squarewave waveform with
an 8 kHz repetition rate is applied to this input
to define the start of the transmit time slot
assigned to this device (non-delayed frame mode).
or the start of the transmit frame (delayed frame
mode using the internal time-slot assignment
counter).
VFX I
I
28
20
Transmit analog
This in a high·impedance input. Voice frequency
signals present on this input are encoded as an
A·law or J.l.·law PCM bit stream and shifted out
on the selected DX pin.
DXO
DX 1
0'
0
18
19
13
Transmit Data
DX' is available on the TS507Q only, DXO is
available on all devices. These Transmit Dat8
TR '·STATE ® outputs remain in the high
impedance state except during the assigned
transmit time slot on the assigned port, during
which the transmit PCM data byte is shifted
out on the rising edges of BCLK.
TSXO
0
0
20
14
Transmit time slot
21
-
TSX 1 is available on the TS5070 only. TSXO is
available on all devices. Normally these opendrain outputs are floating in a high impedance
state except when a time·slr:t is active on one of
thE: Dxoutputs, when the appropriate TSX
output pulls low to enable a backplane line-driver.
TSX 1
-
4·3
I
RECEIVE SECTION
N'me
Pin type
TS5070
TS5071
Receive frame sync.
8
FSR
Description
Function
Normally a pulse or sQuarewave waveform with
an 8 kHz repetition rate is applied to this input
to define the start of the receive time slot
assigned to this device (non-delayed frame
model, or the start of the receive frame (delayed
frame mode using the internal time-slot
assignment counter).
VFRO
0
Receive analog
The Receive analog power amplifier output.
capable of driving load impedances as low as
300
n
(depending on the peak overload level
required). PCM data received on the assigned
DR pin is decoded and appears at this output as
voice frequency signals.
10
ORO
ORI
Receive Data
DA1 is available on the TS5070 only: ORO is
available on all devices. These receive data input(s)
are inactive except during the assigned receive
time slot of the assigned port when the receive
PCM data IS shifted in on the falling edqes of
8CLK.
Interface Latches
IL5 through ILO are available on the TS5070
IL4 through ILO are available on the TS5071
Each Interface Latch 1/0 pin may be individually
programmed as an input or an output determined
by the state of the corresponding bit In the Latch
pirection Register (LOR). For pins configured as
inputs, the logic state sensed on each input is
latched into the Interface Latch Register (tLAI
wheney!'r control data is written to COMBO JIG,
while CS is low, and the information is shifted
out on the CO (or ClIO) pin. When configured
as outputs, control data written into the I LR
appears at the corresponding IL pins.
9
INTERFACE, CONTROL, RESET
IL5
IL4
IL3
IL2
ILl
ILO
liO
110
110
110
110
110
CCLK
CliO
110
CI
CO
0
I
23
24
6
16
25
26
17
18
13
9
Control clock
This clock shifts serial control information into
or out from ClIO when the CS input is low,
depending on the current instruction CCLK may
be asynchronous with the other system clocks.
8
Control Data
input/output
This is the Control Data I/O pin which is
provitled on the TS5071. Serial control
information is shifted into or out from eOMOO II G
on this pin when CS is low. The direction of the
data is determined by the current instruction as
defined in Table I.
Control Data input
Control Data output
These are separate controls, availabh.!s ollly on the
TS5070. They can be Wired toqether if rl!qulfed.
4
12
11
CS
14
10
Chip select
When this pin is low. control information can he
written into or out from COMBO JIG via the CI/O
pin (or CI anti CO)
MR
15
11
Master Reset
ThiS logic input must be pulled low for normal
operation of COMBO ilG. When pulled
momentarily high. at least lJ.t sec, all proHrammahl1!
registers in the device are reset to the states spccifil:d
under "Power-On Initialization".
4·4
FUNCTIONAL DESCRIPTION
initialization. Following the Decoder is a 5th order lowpass switched capacitor filter with integral Sin xix correction for the B kHz sample and hold. A programmable gain
amplifier, which must be set by writing to the Receive
Gain Register, is included, and ~:nal!y a Post-Filter/Power
Amplifier capable of driving a 30012 load to ! 3.5 V, a
600 I! load to ± 3.B V or a 15 kSl load to ± 4.0 V at peak
overload.
A decode cycle begins immediately after each receive
time-slot, and 10 !J.s later the Decoder DAC output is
updated. The total signal delay is 10 /15 plus 120 /1S
Ifilter delay) plus 62.5/1s 11/2 frame) which gives approximately 190 /1S.
POWER-ON INITIALIZATION
When power is first applied, power-on reset circuitry
initializes the COMBO : IG and puts it into the powerdown state. The gain control registers for the transmit and
receive Jain sections are jJrogrammed for minimum gain,
the h'{~rid balance circuit is turned off, the power amp is
disabled and the device IS in the non-delayed timing mode.
The Latch Direction Register ILDR) is pre·set with alilL
pins programmed as inputs, placing the
sLie
interface
pins in a high impedance state. The CliO pin is set as an
input ready for the first control byte of the.initialization
sequence.
A reset to these same initial conditions may also be forced
by driving the MR pin momentarily high. This may be
PCM INTERFACE
The FSX and FSR frame sync inputs determine the begin·
ning of the 8-bit transmit and receive time-slots respectively. They may have any duration from a single cycle of
BCLK to a square wave. Two different relationships may
be established between the frame sync inputs and the
actual time-slots on the PCM busses by setting brt 3 in
the Control Register Isee Table II). Non-delayed data
mode is similar to long·frame timing on the ETC 5050/60
series of devices: time-slots beinq nominally coincident
with the rising edge of the appropriate FS input. The
alternative is to use Delayed Data mode which is similar
to short-frame sync timing, in which each FS input
must be high at least a half-cycle of llCLK earlier than the
time - slot. The Time-Slot Assignment circuit on the
device can only be used with Delayed Data timin~. When
using Time -Slot Assignment, the beginning of tire first
time-slot in a frame is identified by the appro!"iate FS
input. The actual transmit and receive time·slots are then
determined by the internal Time-Slot Assignment counters.
Transmit and Receive frames and time-slots may be
skewed from each other by any number of BCLK cycles
During each assigned Transmit time-slot, the selected
DXO/1 output shifts data out from the PCM register on
the rising edges of BCLK. 'YS'XO lor fSX1 as appropriate)
also pulls low for the first 7 1/2 bit times of the time-slot
to control the TRI-STATE Enable of a backplane line·
driver. Serial PCM data is shifted into the selected DRO/l
input during each assigned Receive time-slot on the falling
edges of BCLK. DXO or DX1 and DRO or DR" are selectable on the TS5070 only.
done either when powered-up or down. For normal
operation this pin must be pulled low.
The desired modes for all programmable functions may be
initialized via the control port prior to a Power-up
command.
POWER-OOWN STATE
Following a period of activity in the powered"up state the
power-down state may be re-entered by writing a PowerDown instruction into the serial control port as indicated
in Table I. The power down instruction may be included
within any other instruction code. It is recommended that
the chip be powered down before executing any instructions. In the power-down state, all non-essential cir·
cuitry is de-activated and the DXO (and DX1) outputs are
in the high impedance TRI-STATE condition.
The coefficients stored in the Hybrid Balance circuit and
the Gain Control registers, the data in the LDR and ILR,
and all control bits remain unchanged in the power-down
state unless changed by writing new data via the serial
control port, which remains active. The outputs of the
Interface Latches also remain active, maintaining the
ability to monitor and control the SLiC.
TRANSMIT FILTER AND ENCODER
The Transmit section input, VFXI, is a high impedance
summing input which is used as the differencing point
for the internal hybrid balance cancellation signal. No
external components are necessary to set the gain. Following this circuit is a programmable gain/attenuation
amplifier which is controlled by the contents of the
Transmit Gain Register (see Programmable Functions
section). An active pre-filter then precedes the 3rd order
high-pass and 5th order low-pass switched capacitor
filters. The A/D converter has a compressing characteristic
according to the standard CCITT A or /1255 coding laws,
which must be selected by a control instruction during
initialization (see Tables I and II). A precision on-chip
voltage reference ensures accurate and highly stable
transmission levels. Any offset voltage "rising in the gainset amplifier, the filters or the comparator is canceled
by an internal auto-zero circuit.
Each encode cycle begins immediately following the
assigned Transmit time-slot. The total signal delay referenced to the start of the time-slot is approximately
165/1s Idue to the Transmit Filter) plus 125/1s Idue to
encoding delay), which totals 290 /1S. Data is shifted out
on DXO or DX1 during the selected time slot on eight
rising edges of BCLK.
SERIAL CONTROL PORT
Control information and data are written into or readback from COMBO IIG via the serial control port consisting of the control clock CCLK; the serial data input/output. CliO, lor separate input, CI, and output, CO, on the
TS5070 only); and the Chip Select input, CS. All control
instructions require 2 bytes, as listed in Table I, with the
exception of a single byte power-up/down command.
To shift control data intoCOMBO IIG,CCLK must be pulsed high 8 times while CS is low. Data on the CliO lor CI)
input is shifted into the serial input ~egister on the falling
edge of each CCLK pulse. After all data is shifted in, the
contents of the input shift register are decoded, and may
indicate that a 2nd byte of control data will follow. This
second byte may either be defined by a second byte-wide
CS pulse or may follow the first contiguously, i. e. it is
not mandatory for CS to return high in between the first
and second control bytes. At the end of CCLKB in the
2nd control byte the data is luaded into the appropriate programmable register. CS may remain low continuously when .B!"ogramming successive registers, if desired. However, CS should be set high when no data transfers are in progress.
To readback interface Latch data or status information
DECODER ANO RECEIVE FILTER
PCM data is shifted into the Decoder's Receive PCM
Register via the ORO or DR1 pin during the selected
time-slot on the B falling edges of BCLK. The Decoder
consists of an expanding DAC with either A or /1255 law
decoding characteristic, which is selected by the same
control instruction used to select the Encode law during
4-5
from COMBO IIG, the first byte of thLappropriate ins·
truction is strob.!9 in during the first CS pulse, as defi·
ned in Table I. CS must then be taken low for a further B
CCLK cycles, during which the data is shifted onto the
CO or CI/O pin on the 'rising edges of CCLK. When CS is
high the CO or ClIO pin is in the high·impedance TR ~
Function
STATE, enabling the CIIQ pins of many devices to be
multiplexed together.
Thus, to summarize, 2·byte READ and WR ITE instruc·
tions may use either two 8·bit wide iSS pulses or a single
IS-bit wide CS pulse.
By•• 1 (Noto11
By•• 2 (Not. II
4
3
2
7
6
5
4
3
2
1
0
Single Byte Power-Up/Down
p
X
X
X
X
X
0
X
Write Control Register
p
0
0
0
0
0
0
0
1
1
X ,
X
See Table II
1
1
X
See Table V
X
See Table'V
1
1
X
See Table IV
X
See Table IV
1
1
X
X
See Table VIII
See Table VIII
X
X
See Table VII
See Table VII
7
6
5
None
Read-Back Control Register
P
Write to Interface Latch Register
Read Interface Latch Register
P
P
0
0
0
0
0
0
1
1
0
Write latch Direction Aegister
0
0
0
0
1
1
0
0
0
Read Latch Direction Regilter
p
p
Write Receive Gain Register
Read Aeceiye Gain Register
P
P
0
0
1
1
0
0
0
0
0
Write Transmit Gain Register
p
p
0
0
1
1
0
0
1
1
0
1
Read Transmit Gain Register
1
1
Write Receive Time-Slot/Port
Aead-Back Receive Time-Slot/Port
P
1
0
0
1
1
0
1
1
1
See Table VI
1
0
0
X
p
X
See Table VI
p
1
1
0
0
1
1
0
0
0
1
1
X
See Table VI
X
See Table VI
Write Transmit Time..$lot/Port
Read·Back Transmit Time-Slot/Port
P
1
1
1
1
0
See Table ,II
0
0
1
1
Notel: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI, CO or CIICO pin. X = don't care.
Note 2 : "P" is the power-up/down control bit, see "Power-up" section 1"0" :Power Up "I" :Power Down)
; iote 3 : 3 additional registers are provided for the Hybrid Balance Filter, see page 9.
TABLE I - Programmel. Register Instructions
PROGRAMMABLE FUNCTIONS
POWER·UP/DOWN CONTROL
Following power-on initialization, power-up and powerdown control may be accomplished by writing any of the
control instructions listed in Table I into COMBOIIGwith
the "P" bit set to "0" for power-up or "I" for powerdown. Normally it is recommended that all programmable
functions be initially programmed while the device is
powered down. Power state control can then be included
with the last programming instruction or the separate
single-byte instruction. Any of the programmable registers
may also be modified while the device is powered·up or
down be setting the "P" bit as indicated. When the power
up or down control is entered as a single byte instruction,
Bit one 11) must be reset to a O.
When a power-up command is givp.n, all de-activated circuits are activated, but the TRI-STATE PCM output(s),
DXO land DX1), will remain in the high impedance state
until the second FSXpulse after power·up.
CONTROL REGISTER INSTRUCTION
The first byte of a READ or WRITE instruction to the
Control Register is as shown in Table l. The second byte
fun~·tions are detailed in Table II.
MASTER CLOCK FREQUENCY SELECTION
A Master clock must be provided to COMBO IIG for
operation of the filter and coding/decoding functions.
The MCLK frequency must be either 512 kHz,1.S36 MHz,
1. 544 MHz, 2.048 MHz, or 4.096 MHz and must be
synchronous with BCLK. 8its Fl and FO Isee Table II)
must be set during initialization to select the correct
internal divider.
CODING LAW SELECTION
Bits "MA" and "IA" in Table II permit the selection of
,,255 coding or A-law coding, with or without-even bit
inversion.
ANALOG LOOPBACK
Analog Loopback mode i, entered by setting the "Al"
and "Ol" bits in the Control Register as shown in Table II.
In the analog loopback mode, the Transmit input VFXl is
isolated from the input pin and internally connectea to
the VFRO output, forming a loop from the Receive PCM
Register back to the Transmit PCM Register. The VF RO
pin remains active, and the programmed settings of the
Transmit and Receive gains remain unchanged, thus care
must be taken to ensure that overload levels are not
exceeded aAywhere in the loop.
DIGITAL LOOPBACK
Digital loopback mode is entered by setting the "AL"
and "0 l" bits in the Control Register as shown in Table II.
This mode p,ovides another stage of path verification by
enabling .data written into the Receive PCM Register to
be read back from that register in any Transmit time-
4·6
Bit Number
7
6
5
4
3
2
1
a
Fl
Fa
MA
IA
ON
OL
AL
pp
0
0
1
1
0
I
0
1
Function
= 512 kHz
MCLK = 1.536 or 1.544 MHz
MCLK = 2.048 MHz·x
MCLK = 4.096 MHz
MCLK
.
x
a
1
1
Select J.1 . 255 law·~
A·law, Including Even Bit Inversion
A-law, No Even Bit Inversion
0
1
--
Delayed Data Timing
Non-Delayed Data Timing :,
0
1
a
1
0
Normal Operation
Digital Loopback
Analog Loopback
0
X
1
~
Power Amp Enabled in PDN
Power Amp Disabled in PDN •
a
1
• =State at power-on initiolization.
TABLE II - Control Register Byte 2 Functions
True A-law with
even bit inversion
/.1255 law
MSB
LSB
MSB
A -law without
even bit inversion
LSB
MSB
LSB
VIN = + Full Scale
1
0
a
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
VIN =DV
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
a
1
1
0
0
1
1
0
0
1
1
1
0
0
a
0
0
a
0
0
0
0
0
0
a
0
a
a
a
a
0
a
a
a
a
a
a
1
a
1
a
1
0
a
1
1
1
1
1
1
1
VIN
=-
Full Scale
Note 1 ; The MSB is always the first PCM bit shifted in or out of COMBO IIG
TABLE III - Coding Law Conventions
7
I
6
La
I
Ll
I
I
_I Byte 2 Bit NUmjr
S
L2
Ln Bit
4
I
L3
1
I
3
2
L4
I I
LS
1
X
I
I
Bits L5-Lo must be set by writing the specified instruction to the LOR with the L bits in the second byte set
as specified in Table IV_
a
INTERfACE LATCH STATES
Interface Latches configured as outputs assume the state
determined by the appropriate data bit in the 2-byte
instruction written to the Interface Latch Register (I LRI
as shown in Tables I and V. Latches configured as inputs
will sense the state applied by an external source, such as
the Off-Hook detect output of a sLie. All bits of the I LR,
i.e. sensed inputs and the programmed state of outputs,
can be read back in the 2nd byte of a READ from the
ILR.
It is recommended that, during initialization, the state of
I L pins to be configured as outputs should first be programmed, followed immediately by the Latch Direction
'1 .. .,ister.
X
IL Direction
a
Input
1
Output
x = don't care.
TABLE IV - Byte 2 Functions of Latch Direction Register
slot at DX0/1. No PCM decoding or encoding takes place in this mode, VFRO maintains a low impedance
idle output.
Bit Number
INTERFACE LATCH DIRECTIONS
Immediately following power-on, all Interface Latches
assume they are inputs, and therefore all I L pins are in a
high impedance state. Each IL pin may be individually
programmed as a logic input or output by writing the
appropriate instruction to the LDR, see Tables I and IV.
a
x
DO
TABLE V - Interface Latch Data Bit Order
4·7
TIME-5LOT ASSIGNMENT
COMBO IIG can operate in either fixed time-slot or time-slot assignment mode for selecting the Transmit and
Receive PCM time-slots_ Following power-on, the device
is automatically in Non-Delayed Timing mode, in which
the time-slot always begins with the leading (rising) edge
of frame sync inputs FSX and FSR Time-Slot Assignment may only be used with Delayed Data timing: see
Figure 5_ FSX and FSR may have any phase relation ship
with each other in BCLK period movements_
Alternatively, the internal time-slot assignment counters
and comparators can be used to access any time-slot in a
frame, using the frame sync inputs as marker pulses for
the beginning of transmit and receive time-slot 0_ In this
mode, a frame may consist of up to 64 time-slots of
8 bits each_ A time-slot is assigned by a 2-byte instruction
as shown in Tables I and V I. The last 6 bits of the second
byte indicate the selected time-slot from 0-63 using
straight binary notation, A new assignment becomes
active on the second frame following the end of the ChipSelect for the second control byte. The "EN" bit allows
the PCM inputs, DROll, or outputs, DXO/1, as appropriate, to be enabled or disabled.
Time-Slot Assignment mode requires that the FSX and
FSR pulses must conform to the delayed timing format
shown in Figure 5.
Function
Bit Number
4
T4
3
T3
2
T2
1
Tl
0
TO
X
X
X
X
X
X
X
X
X
X
X
X
6
PS
5
T5
(Note 1)
(Note 2)
0
0
0
1
7
EN
1
0
Assign One Binary Coded Time-Slot from 0-63
Assign One Binary Coded Time-Slot from 0-63
1
1
Assign One Binarv Coded Time-Slot from 0-63
Assign One Binarv Coded Time-Slot from 0-63
Disable DXO Output (Transmit Instruction)
Disable ORO Input (Receive Instruction)
Disable 0X1 Output (Transmit Instruction)
Disable DR1 Input (Receive Instruction)
Enable oXO Output (Transmit Instruction)
Enable ORO Input (Receive Instruction)
Enable DX 1 Output (Transmit Instruction)
Enable DR1 Input (Receive Instruction)
Note 1: The "PS" bit MUST always be set to 0 for the TS5071
Note 2: T5 is the MSB of the Time-slot assignment.
TABLE VI - Time-Slot and Port Assignment instruction
PORT SELECTION
On the TS5070 only, an additional capability is available ; 2 Transmit serial PCM ports, DXO and DX1, and
2 Receive serial PCM ports, DRO and DR I, are provided
to enable two-way space switching to be implemented.
Port selections for transmit and receive are made within
the appropriate time-slot assignment instruction using
the "PS" bit in the second byte. Port Selection may
only be used in Delayed Data timing mode.
On the TS5071, only ports DXO and DRO are available,
therefore the "PS" bit MUST always be set to 0 for
these devices.
T abel V I shows the format for the second byte of both
transmit and receive time-slot and port assignment
instructions.
o dBmO Test Level
7
6
Bit Number
5 4 3 2
1
0
at VFx 1
0
0
0
0
0
0
0
0
No Output
0
0
0
0
0
0
0
1
0.087
0
0
0
0
0
0
1 0
0.088
1
1
1
1
1
1
1
0
1.600
1
1
1
1
1
1
1
1
1.619
(Vrmsl
TABLE VII - Byte 2 of Transmit Gain Instructions
TRANSMIT GAIN INSTRUCTION BYTE 2
The transmit gain can be programmed in 0.1 dB steps by
writing to the Transmit Gain Register as defined in
Tables! and VII. This corresponds to a range of 0 dBmO
levels at VFXI between 1.619 Vrms and 0.087 Vrms
(equivalent to + 6.4 dBm to - 19.0 dBm in 600 nl.
To calculate the binary code for byte 2 of this instruction
for any desired input 0 dBmO level in Vrms, take the
nearest integer to the decimal number given by;
200 x 1091O (VIO.085951
and convert to the binary equivalent. Some examples are
given in Table VII.
RECEIVE GAIN INSTRUCTION BYTE 2
The receive gain can be programmed in 0.1 dB steps by
writing to the Receive Gain Register as defined in Tables I
and VIII. Note the following restrictions on output drive
capability:
al 0 dBmO levels " 1.96 Vrms at VF RO may be driven
into a load of ;;:15 kn to GND,
bl 0 dBmO levels" 1.90 Vrms at VF RO may be driven
into a load.of ;;:600 n to GND,
cl 0 dBmO levels" 1.70 Vrms at VF RO may be driven
into a load of ;;: 300 n to GND.
4·8
To calculate the binary code for byte 2 of this instruction
for any desired output 0 dBmO level in Vrms, take the
nearest integer to the decimal number given by:
200 x 10910 (V/O.l046)
with a transformer SLiC in providing additional phase
correction for mid and high-band frequencies, typically
1 kHz to 3.4 ~Hz_ Such a correction is particularly useful if the test balance impedance includes a capacitor of
100 nF or less, such as the loaded and non-loaded loop
test networks in the United States. Independent placement of the pole and zero location is provided.
Figure 1 shows a simplified diagram of the local echo path
for a typical application with a transformer interface. The
magnitude and phase of the local echo signal, measured at
VFXI are a function of the termination impedance IT,
the line transformer and the impedance of the 2W loop,
ZL. If the impedance reflected back into the transformer
primary is expressed as Z L' then the echo path transfer
function from VF RO to VFXI is :
and convert to the binary equivalent. Some examples are
given in Table VIII.
o dBmO Test Level
6
Bit Number
5 4 3 2 1 0
0
0
0
0
0
0
0
0
No Output (Low Z to GNO)
0
0
0
0
0
0
0
1
0.106
0
0
0
0
0
0
1 0
0.107
1
1
1
1
1
1
1
0
1.95
1
1
1
1
1
1
1
1
1.96
7
(Vrms)
at \/.FRO
H(w) = ZL'/(ZT ; ZL')
TABLE VIII - Byte 2 of Receive Gain Instructions
HYBRID BALANCE FILTER
The Hybrid Balance Filter on COMBO II is a program·
mabie filter consisting of a second-order Bi-Quad section,
Hyball, followed by a first·order section, Hybal2, and a
programmable attenuatar. Either of the filter sections can
be bypassed if only one is required to achieve good cancellation. A selectable 180 degree inverting stage is included
to compensate for interface circuits which also invert the
transmit input relative to the receive output signal. The
Bi-quad is intended mainly to balance low frequency
signals across a transformer SLle, and the first order
section to balance midrange to higher audio 'frequency
signals.
As a Bi·Quad, Hyball has a pair of low freque~cy zeroes
and a pair of complex conjugate poles. When configuring
the Bi-Quad, matching the phase of the hybrid at low to
midband frequencies is most critical. Once the echo path
is correctly balanced in phase, the magnitude of the cancellation signal can be corrected by the programmable
attenuator.
The Bi-Quad mode of Hyball is most suitable for balancing interfaces with transformers having high inductance
of 1.5 Henries or more. An alternative configuration for
smaller transformers is available by converting Hyball to
a simple first·order section with a sinqle real low frequency pole and 0 Hz zero. In this mode, the pole frequency
may be programmed.
Many line interfaces can be adequately balanced by use
of the Hyball section only, in which case the Hybal2
filter should be de-selected to bypass it.
Hybal2, the higher frequency first-order section, is provided for balancing an electronic SLlC, and is also helpful
J'x,r--·--
(1)
PROGRAMMING THE FILTER
On initial power-up the Hybrid Balance filter is tlisilbled.
Before the hybrid balance filter can be programmed it is
necessary to design the transformer and termination
impedance in order to meet system 2W input return loss
specifications, which are normally measured against a
fixed test impedance (600 or 900 S! in most countries).
Only then can the echo path be modeled and the hybrid
balance filter programmed. Hybrid balancing is also
measured against a fixed test impedance, specified by
each national Telecom administration to provide adequate
control of talker and listener echo over the majority of
their network connections. This test impedance is ZL in
Figure 1. The echo signal and the degree of transhYbrid
loss obtained by the programmable filter must be measured from the PCM digital input, ORO, to the PCM
digital output, 0xO, either by digital test signal analysis
or by conversion back to analog by a PCM CODECI
Filter.
Three registers must be programmed in COMBO IIG to
fully configure the Hybrid Balance Filter as follows:
Register 1:
select/de-select Hybrid Balance Filter
invert/non-invert cancellation signal
select/de-select Hybal2 filter section
attenuatar setting
Register 2:
select/de-select Hyball filter
set Hyball to Bi-quad or 1st order
pole and zero frequency selection
program pole frequency in Hybal2 filter
Register 3:
program zero frequency in Hybal2 filter
Standard filter design techniques may be used to model
the echo path (see Equation 1) and design a matChing
hybrid balance filter configuration. Alternatively, the
frequency response of the echo path can be measured
and the hybrid balance filter designed to replicate it.
A Hybrid Balance fi Iter design guide and software optimization program are available under license from
THOMSON SEMICONOUCTEURS ( order TS5077).
~.---.-----
J" ~'-' I
L.....-._._.~.
__ . __ . __
FIGURE 1 . SIMPLIFIED DIAGRAM OF HYBRID BALANCE CIRCUIT
4·9
APPLICATIONS INFORMATIONS
Figure 2 shows a typical application of the TS5071
together with a transformer·based SLiC.
Four of the I L latches are configured as outputs to con·
trol the relay drivers on the SLlC, while I L4 is an input
for the Supervision signal. Figure 3 shows a similar arrangement with a monolithic SLiC.
always be followed. In applications where the printed
circuit card may be plugged into a hot socket with power
and clocks already present, an extra long ground pin on
the connector should be used.
To minimize noise sources all ground connections to each
POWER SUPPLIES
While the pins of the TS5070 COMBO IIG devices are well
protected against electrical m.isuse, it is recommended that
the standard CMOS practice of applying GND to the
device before any other conn~ctions are made should
to the GND pin in order to prevent the interaction of
ground return currents flowing through a common bus
impedance. Power supply decoupling capacitors of O.II1F
should be connected from this common point to VCC
and VSS as close to the device pins as possible.
device should meet at a common point as close as possible
I
Ij
V
ov
Hat ~.~
VFXI
r-:iJ--
I-- CLK
rs x
0.1/.
TIP
~ "xo
rS n
I-I--
TS5071
,on
--
zT
Wo
BGND
100
100
*7"
~
fi4 R3 H2 R, "0
)
RING
RL
It
LINE
SUPERVISION
VBAT~
SUP
filNG
He1
CIRCUIT
HC2
EN
RSYNC
Iva I Iv
-I- 5
V- 5
FIGURE 2· TYPICAL APPLICATION WITH TRANSFORMER
4·10
DnO
cs
CCLK
I-- CliO
VFRO
48 V
!,V
sLie
, - - - - - - - - -.....- - - - - +5 V
OV
CLK
FS X
°X O
FS R
ORO
TIP
CS
RING
CCLK
CliO
FIGURE 3· TYPICAL APPLICATION WITH MONOLITHIC SLiC
MAXIMUM RATINGS
Ading
Symbol
V.lue
Unit
VCCtoGNO
VCC
+7
V
Vssto GND
VsS
-7
V
VCC+ltoVss-l
V
Voltage at VFXI
Voltage at any digital input
VIN
Current at VFRO
Current at any digital output
Storage temperature range
Lead temperature (soldering, 10 seconds)
4·11
VCC
+ 1 to GND - 1
V
± 100
mA
10
±5O
mA
TitS
- 65, + 150
Tiled
300
·c
·c
ELECTRICAL OPERATING CHARACTERISTICS
GND. Typicals specified at VCC = + 5V, VSS = - 5V,
TA = 25'C.
All timing parameters are measured at VOH = 2.0 V and
VOL = 0.7 V.
See Definitions and Timing Conventions section for test
methods information.
Unless otherwise noted, limits printed in BOLO characters
are guaranteed for VCC = + 5 V ± 5 %; VSS = - 5V ± 5%,
TA = DoC to 70°C by correlation with 100 % electrical
testing at TA = 25'C. All other limits are assured by
correlation with other production tests and/or product
design and characterization. All signals referenced to
DIGITAL INTERFACE
Characteristic
Symbol
Input low 'Voltage
All digital inputs
(DC Meas.)
Input high voltage
All digital inputs
Min
Typ
Vil
VIH
Max
Unit
0.7
V
0.4
V
2.0
(DC Meas.)
Output low voltage
DxOand OX l ,
Il=3.2mA
VOL
All other Digital outputs, I L = 1 rnA
Output high voltage
DXO and DX1, IL= - 3.2 mA
VOH
All other Digital outputs except (TsX),
IL=-lmA
All digital outputs, IL
=-
2.4
VCC-' 0.5
l00~A
V
V
Input low current all digital inputs IGNO
_ _ c-._. _ ' - - - - . _
ANALOG INTERFACE
Input current VVFXI (- 3.3 V -
4
'FC
'RC
BYTE 2
I
If
'Hcsr~ i
L,oco
' I
iI
tSLC ~ L-., tHCL
i
i
IL5 - ILO
::x
x:
INPUTS ONLY
-~c
OUTPUTS ONL y
TRANSMISSION CHARACTERISTICS
Unless otherwise noted, limits printed in BOLD characters
are guaranteed for Vee = + 5V ± 5 %, VSS = - 5V ±
5 %, TA = O°C to 70'e by correlation with 100 %
electrical testing at TA = 25°e. f = 1015.625 Hz, VFXI =
o dBmO. DRO or DRl = 0 dBm peM code. All other
limits are assured by correlation with other production
tests and/or product design and characterization. All
signals referenced to GND. Typicals specified at Vee
+ 5V, VSS = - 5V, TA = 25'e.
AMPLITUDE RESPONSE
Symbol
Characteristic
Min
TVp
MI.
Unit
Absolute levels
The Maximum 0 dBmO Levels are:
VFXI
VFRO (15 kll Loadl
1.S19
1.9S3
Vrms
87.0
lOS.0
mVms
mVms
2.33
2.33
2.73
2.73
Vrms
Vrms
2.32
2.33
2.82
2.83
Vrrns
Vrms
124.9
125.3
152.2
152.7
mVrms
mVrms
mVrms
mVrms
Vrms
The Minimum 0 dBmO Levels are:
VFXI
VF RO (Any Load> 300 III
Maximum Overload
The Nominal Overload Levels are
Tmax
VFxl-A-law
t-t-1aw
VFRO-A·law (SOD II Loadl
fJ·law (SOD H Load I
Vrms
Vrms
The Maximum Overload Levels are:
VFXI-A-law
,u-Iaw
VFRO-A-Iaw (150 kll Load)
fJ-law (150 kll Load I
Vrms
Vrms
The Minimum Overload Levels are:
VFXI-A-law
~-Iaw
VFRo_A-law (Any Load> 300 HI
fJ-law (Any Load> 3000.1
Transmit Gain
Absolute Accurary
GXA
Transmit Gain Programmed for Maximum
Measure Deviation of Digital Code from
Ideal 0 dBmO PCM Code at D xO/1.
v dBmO Test Level
-0.15
0.15
dB
-·0.1
0.1
dB
TA = 25°e. Vee =5V, Vss =- 5V
Transmit Gain
Variation with Programmed Gain
GXAG
Measure Transmit Gain Over the Range
from Maximum to Minimum
Calculate the Deviation from the
Programmed Gain Relative to GXA
i.e., GXAG
= Gactual
- G prog - GXA
TA = 25°e. Vee =5V. Vss =-5V
4-17
=
AMPLITUDE RESPONSE (continued)
Symbol
Characteristic
Transmit Olin
Variation with Frequency
M••
Unit
- 26
- 0.1
0.15
0.0
14
32
dB
dB
dB
dB
dB
dB
-24.9
- 0.1
0.15
0.15
0.15
0.15
0.0
-13.5
- 32
- 32
- 32
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
- 0.1
0.1
dB
-0.05
0.05
dB
-0.2
-0.4
-1.2
0.2
0.4
1.2
dB
dB
dB
-0.15
0.15
dB
- 0.1
0.1
dB
- 0.1
0.1
dB
GXAF
Relative to 1015.625 Hz, (Note 41
Minimum Gain
GX
Maximum Gain
ORO (or DRt) =OdBmOCode
f = 60 Hz
f = 200 Hz
f = 300 Hz to 3000 Hz
f = 3400 Hz
<
<
f
Typ
Min
II
. 1.8
- 0.15
- 0.7
=4000 Hz
f ~ 4600 Hz Measure Response
at Alias Frequency from 0 kHz to 4 kHz
GX =OdB, VFxl
1.619 Vrms
ORO or OR' =0 dBmO Code (Note 4)
f =62.5 Hz
f = 203.125 Hz
f = 296.875 Hz
f = 515.625 Hz
f = 2796.875 Hz
f = 3015.625 Hz
f = 3406.250 Hz
f = 3984.375 Hz
f
4593.750 Hz, Measure 3406.25 Hz
f = 5015.625 Hz, Measure 2984.375 Hz
f = 10015.625 Hz, Measure 2015.625 Hz
=
-1.7
- 0.15
- 0.15
- 0.15
-0.15
-0.7
=
Transmit Gain
Variation with Temperature
GXAT
=
Measured Relative to GXA, Vee
5 v, VSS
Minimum gain 10kl2 )
RoXA
-
RLXA
10
GSx
CLXA
-
GSX
VOXA
± 2.8
AvXA
5000
(VFxl+ to GSx)
Unity gain bandwidth
FUXA
1
Offset voltage
VOSXA
-20
Common·mode voltage
VeMXA
-2.5
Common-mode rejectioh ratio
CMRRXA
60
Power supply rejection ratio
PSRRXA
60
1
3
Q
-
-
k!2
50
pF
2
-
-
V
-
V/V
MHz
20
mV
2.5
V
-
dB
-
dB
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
Output resistance
Load resistance
VFRO
IVFRO= ±2.5V)
Load capacitance
Output DC offset voltage
RORF
-
RLRF
600
CLRF
-
VOSRO
1
3
U
-
-
U
-
500
pF
-200
-
200
rnV
POWER DISSIPATION (ALL DEVICES)
current
IceD
1.5
rnA
leeO
-
0.5
Power-down current
0.05
0.3
rnA
Active current
Icc 1
-
6.0
9.0
rnA
Active current
,•• 1
-
6.0
9.0
mA
Power~down
4-30
TIMING SPECIFICATIONS
Characteristic
Frequency of master clocks
Symbol
Min
Typ
Max
Unit
l/tPM
-
1.536
-
MHz
-
1.544
2.048
-
Depends on the device used and the
BClKR/ClKSEl Pin
MCLKxand MClKR
-
Width of master clock high
MClKx and MClKR
tWMH
160
-
-
ns
Width oi master clock low
MClKx and MClKR
tWML
160
-
-
ns
Rise time of master clock
MClKX and MClKR
tRM
-
-
50
ns
Fall time of master clock
MClKx and MClKR
tFM
-
-
50
ns
Period of bit clock
tpB
485
488
15.725
ns
tWBH
160
-
ns
50
ns
50
ns
Width of bit clock low
IVIL=0.6V)
tWBL
160
Rise time of bit clock
ItpB=488ns)
tRB
-
tFB
-
-
tSBFM
100
-
-
ns
tHBF
0
-
-
ns
Width of bit clock high
Fall time of bit clock
IVIH=2.2V)
ItpB=488ns)
Set-up time from BClKX high to MClKx failing edge.
IFirst bit clock after the leading edge of FSx)
Holding time from bit clock low to the frame sync
Iiong frame only)
ns
Set-up time from frame sync to bit clock low (long frame only)
tSFB
80
-
-
ns
Hold time from 3rd period of bit clock
low to frame sync (long frame only)
tHBFI
100
-
-
ns
tOZF
20
-
165
ns
Delay time from BClKx high to data valid
ILoad=150 pF plus 2 LSTTl loads)
tOBO
0
-
180
ns
Delay time from BClKX low to data output disabled
toze
50
-
165
ns
Set-up time from DR valid to BClKR/X low
tSOB
50
-
-
ns
Hold time from BClKR/X low to DR invalid
tHBo
50
tHOLD
0
-
-
ns
Set-up time from FSX/R to BClKx/R low
Ishort frame sync pulse) - Note 1
tSF
50
-
-
ns
Hold time from BClKx/R low to fSX/R low
Ishort frame sync pulse) - Note 1
tHF
100
-
-
txop
-
140
tWFL
160
-
FSX or FSR
Delay time to valid data from FSX or BCLKX. whichever comes
later and delay time from FSx to data output disabled
ICL=O pF to 150 pf)
Holding time from bit clock high to frame sync
Ishort frame only)
Delay time to TSx low
Iload=150 pF plus 2 lSTTl loads)
Minimum width of the frame sync pulse Ilow level)
(64k bit/s operating mode)
-
ns
-
.- .ns
ns
Note1: For short frame sync timing, FSX and FSR must go high while their respective bit clocks are high.
--~
BClKx
BClKR
~~:- - -1....1
tWFL_
\. . _____________ l
I
FIGURE 2 - 64 k bits/s TIMING DIAGRAM (See next page for complete timing)
4-31
15,
1,1
tOlC _
_1\111
MCLK"
MClKi~
BLCK"
t
FS,
N
tIlBD-1
0,
(
I
X ' X
J
r
X,
tD:~I_
X \ X
BCLK Il
FS n
DR
FIGURE 3 - SHORT FRAME SYNC TIMING
b
X
I
8"----
MCLK,
MCLK"
BCLKx
1:
FS,
tHBFI
f~
~I
tw
D,
BCLK"
fS"
- - 'I
~
---
t""D_! l-
.-tll!f
tH8f_nr-~
x ' x ' x · x · x · x'.
·1
---Ii-· _:::~ ,,"
toac
-1-
-,-,
\
\
f'
\
D"
FIGURE 4 - LONG FRAME SYNC TIMING
TRANSMISSION CHARACTERISTICS
=O'G to 70'C, Vcc =5V ± 5%, VBB =-5V ±5%, GNDA = OV, f = 1.02 kHz, VIN
transmit input amplifier connected for unity-gain non··inverting. (Unless otherwise specified)
(All devices) TA
=0 dBmO
AMPLITUDE RESPONSE
Characteristic
Symbol
Absolute levels· Nominal 0 dBmO level is 4 dBm (600n)
o dBmO ETC 5057. ETC 5054
Max overload level
tMAX
3.14 dBmO
3.17 dBmO
ETC 5057
ETC 5054
Transmit gain. absolute (T A = 25'C. Vee = 5V. VBB = -5V)
Input at GSx = 0 dBmO at 1020 Hz
GXA
Transmit gain, relative to GXA
GXR
I = 16Hz
1= ·SOHz
I = 60Hz
1= lS0Hz
I = 200Hz
I = 300Hz·3000 Hz
I = 3300Hz
I = 3400Hz
I = 4000Hz
I = 4600Hz and up. measure reponse Irom OHz to 4000Hz
Absolute transmit gain varir:ttion with temperature
Absolute transmit gain variation with supply voltage
(Vee
= 5V
± 5%, VBB
= -5V
Sinusoidal test method relerence level
VFxl+ = -40dBmO to +3dBmO
VFxl+ = -50dSmO to -40dSmO
VFxl+ = -S5dBinO to -SOdSmO
= -1 OdBmO
GXAV
GRA
Receive gain. relative to GRA
GRR
I = OHz to 3000 Hz
I = 3300Hz
I = 3400Hz
I = 4000Hz
-
1.2276
-
Vrms
-
2.492
2.501
-0.15
-
0.15
-
-
GRAT
IT A = O°C to +SO'C)
Absolute receive gain variation with supply voltage
GRAV
(Vee = 5V:': 5%. VBB = -5V:': 5%)
Receive gain variations with level
Sinusoidal test method;reference input PCM code
corresponds to an ideally encoded -1 OdBmO'signal
dB
-
-
-40
-30
-26
-0.2
-0.1
0.15
0.05
0
-14
-32
-
-
±0.1
-
-
±0.05
-0.2
-0.4
-1.2
-
0.2
0.4
1.2
4·34
-
dB
dB
dB
-0.15
-
0.15
dB
dB
-
-
0.15
0.05
0
-14
-
-
:':0.1
-
-
:':0.05
~
-
dB
dB
dB
-0.2
-0.4
-1.2
VRO
VPK
-
GRRL
PCM level = -40dBmO to +3dBmO
PCM level = -50dBmO to -40dBmO
PCM level = -5SdBmO to -SOdBmO
(RL=600n)
-
dB
-O.lS
-0.35
-0.7
Absolute receive gain variation with temperature
Receive output drive level
Unit
GXRL
Receive gain, absolute
IT A = 25"C. Vee = 5V, VBB = -5V)
Input = digital code sequence lor OdBmO signal at 1020Hz
Max
-
± 5%)
Transmit gain variations with level
Typ
-2.S
-1.S
-0.15
-0.35
-0.7
GXAT
IT A = O"C to +SO"C)
Min
-2.5
-
-
0.2
0.4
1.2
-
2.5
V
TRANSMISSION CHARACTERISTICS
=
=
=
=
=
(All devices) TA
O"C to + 70"C, VCC
5V ± 5%, VBB
-5V ± 5%, GNDA OV, f
1.02 kHz, VIN
transmit input amplifier connected for unity-gain non-inverting. (Unless otherwise specified)
=0 dBmO,
ENVELOPE OElAY OISTORTION WITH FREQUENCY
Characteristic
Transmit delay. absolute
Symbol
Min
Typ
Max
Unit
DXA
-
290
315
ys
-
-
195
120
50
20
55
80
130
220
145
75
40
75
105
155
-
180
200
-40
-30
-
-
-25
-20
70
100
145
-
-74
-
-82
-79
(I = 1600Hz)
Transmit delay. relative to DXA
I =
I =
I =
I =
I =
I =
1=
DXR
500Hz-600Hz
600Hz-800Hz
800Hz-1000 Hz
1000Hz-1600Hz
1600Hz-2600Hz
2600Hz-2800Hz
2800Hz··3000Hz
Receive delay, absolute
(I = 1600Hz)
ORA
Receive delay. relative toDAA
I = 500Hz-1000Hz
1= 1000Hz-1600Hz
I = 1600Hz-2600Hz
I = 2600Hz-2800Hz
I = 2800Hz-3000Hz
ys
ORR
-
ys
ys
-
90
125
175
NOISE
Transmit noise. P message weighted
(ETC 5057, VFxl+ = OV)
Nxp
Receive noise. P message weighted
(ETC 5057, PCM code equals positive zero)
NRP
Transmit noise. C message weighted
-69
dBmOp
NxC
-
12
15
Receive noise. C message weighted
ETC 5054, PCM code equals alternating positive and
negative zero
NRC
-
8
11
Noise. single frequency
f = OkHz to 100kHz, loop around measurement,
VFxl+ = OVrms
NRS
(ETC 5054, VFxl+ = OV)
Positive power supply rejection, transmit
VFxl+ = OVrms, VCC = 5.0VOC+l OOmVrms,f = OkHz-5DkHz
PPSRX
Negative power supply rejection. transmit
VFxl+ = OVrms)/BB = -5.0VDC+l OOmVrms I = OkHz-50kHz
NPSRX
Positive power supply rejection. receive
(PCM code equals positive zero, VCC = 5.0VOC+l OOmVrms)
f = OHz-4DOOHz
f = 4kHz-25kHz
f = 25kHz-50kHz
PPSRR
Negative power supply rejection, receive
(PCM code equals positive zero, VBB = -5.0VOC+l OOmVrmsl
f = OHz-4000Hz
f = 4kHz-25kHz
f = 25kHz·50kHz
NPSRR
4-35
d8mOp
(Note 1J
dBrnCD
dBrnCO
dBmO
-
-
-53
40
-
-
40
-
-
-
-
dBp
dB
dB
-
-
dBp
dB
dB
dBp
40
40
36
40
40
36
dBp
TRANSMISSION CHARACTERISTICS (Continued)
(All devices) TA = O'C to + 70'C. Vcc = 5V ± 5%. VBB = -5V ± 5%. GNDA '" OV. f = 1.02 kHz. VIN
transmit input amplifier connected for unity-gain non-inverting. (Unless otherwise specified)
Characteristic
=0 dBmO.
Symbol
Min
Typ
Max
Unit
SOS
-
-
-30
dB
-
-
-32
-40
Spurious out~of-band signals at the channel output
Loop around measurement. 0 dBmO. 300Hz-3400Hz input
applied to VFxl+, measure individual image signals at VFRO
4600Hz-7600Hz
7600Hz-8400Hz
8400Hz-l00.000Hz
-32
DISTORTION
Signal to total distortion
(sinusoidal test method)
STOX
or
STOR
Transmit or receive half-channel
Level = 3.0dBmO
= OdBmO to -30dBmO
=-40dBmO
Single frequency distortion, transmit
SFDx
Single frequency distortion, receive
SFDR
Intermodulation distortion
Loop around measurement.VFxl+ = -4dBmO to -21 dBmO.
two frequencies in the range 300Hz-3400Hz
IMO
-
-
33
36
29
30
14
15
XMT
RCV
XMT
RCV
= -55dBmO
dBp
-
-
-46
dB
-46
dB
-41
dB
...
CROSSTALK
Transmit to receive crosstalk. OdBmO transmit level
f = 300Hz-3400Hz, DR = steady PCM code
CTX_R
Receive to transmit crosstalk. OdBmO receive level
f = 300Hz-3400Hz. VFxl = OV
CTR_X
dB
-
-90
-
-90
-75
dB
-70
(Note 2)
Note 1 Theoretical worst-case for a perfectly zeroed encoder with alternating sign bit, due to the decoding law.
Note 2. CTR_X is measured wIth a -40 dBmO activating signal applied at VFxl+
ENCODING FORMAT AT Ox OUTPUT
A-Law
(includes even bit inversion)
VIN(at GSx)
= +Full-scale
V,Nlat GS x) =
ov
V'Nlat GSx) = -Full·scale
1
0
16
1
1
0
0
1
0
0
1
0
1
1
0
4-36
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
~Law
1
0
0
16
1
1
0
1
1
0
0
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
APPLICATIONS INFORMATION
POWER SUPPLIES
While the pins ot the ETC5050 family are well protected against electrical misuse. it is recommended that
the standard CMOS practice be followed. ensuring
that ground is connected to the device before any
other connections are made. In applications where the
printed circuit board may be plugged into a "hot" socket with power and clocks already present. an extra
long ground pin in the connector is useful.
All ground connections to each device should meet at
a common point as close as possible to the GNDA pin.
= ZI
(
~~ ~ ~
) - 2
viZ1.Z2
R2=2~(~
Where: N = \
For best performance. the ground point of beach /FILTER on a card should be connected to a common card
This common ground point should be decoupled to
Vee and VBB with 10 I'F capacitors.
RECEIVE GAIN ADJUSTMENT
For applications where a ETC5050 family CODEC/filter receive output must drive a 6000 load. but a peak
swing lower then ± 2.5V is required. the receive gain
can be easily adjusted by inserting a matched T - pad or
7t-pad at the output. Table II lists the required resistor
values for 600 0 terminations. As these are generally
non-standard values. the equations can be used to
compute the attenuation of the closest pratical set of
resistors. It may be necessary to use unequal values
for the R 1 or R4 arms of the attenuators to achieve a
precise attenuation. Generally it is tolerable to allow a
small deviation of the input impedance from nominal
while still maintaining a good return loss. For example
a 30 dB return loss against 6000 is obtained if the
output impedance of the attenuator is in the range
2820 to_3190 (assuming a perfect transformerl.
T-PAD ATTENUATOR
R1
This minimizes the interaction of ground return currents flowing through a common bus impedance.
0.1 I' F supply decoupling capacitors should be connected from this common ground point to Vee and
VBB·
( N2 ~ 1
)
TABLE II.
Zl
Z2
=
POWER IN
POWER OUT
and
s=,IE
. Z2
Also: Z =
viZsc.Zoc
Where Zsc = impedance with short circuit termination
and Zoe = jmpedance with open circuit termination
7r - PAD ATTENUATOR
,V2
.....-+----,(]
R3 = \oj
Z~.Z2
( N2 ~ 1 )
N2 - 1
)
R4 = ZI ( N2 _ 2NS + 1
ATTENUATOR TABLES FOR
(ALL VALUES IN 0 I
= 300 0
dB
Rl
R2
R3
R4
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2
3
4
5
6
7
8
9
10
11
12
13
14
16
16
18
20
1.7
3.6
·6.2
6.9
8.5
10.4
12.1
13.8
15.5
17.3
34.4
51.3
68
84
100
116
379
143
156
168
180
190
200
210
218.
233
246
26k
13k
8.7k
6.5k
5.2k
4.4k
3.7k
3.3k
2.9k
2.6k
1.3k
850
650
494
402
380
284
244
211
184
161
142
125
110
98
77
61
3.5
6.9
10.4
13.8
17.3
21.3
24.2
27.7
31.1
34.6
70
107
144
183
224
269
317
370
427
490
550
635
720
816
924
1.17k
1.5k
52k
26k
·17.4k
13k
10.5k
8.7k
7.5k
6.5k
5.8k
5.2k
2.6k
1.8k
1.3k
Uk
900
785
698
630
527
535
500
473
450
430
413
386
366
4-37
FIGURE 5 - TYPICAL SYNCHRONOUS APPLICATION
- 5 v - - - - - -....-~~V:BB:--------VV~F:xl;:;+,.-------- from SlI~
VFxl-I+--.....
r---+--I GNDA
GS x
5V - - - - - _...._-1 Vee
--------1
to SLiC . .
ANALOG
INTERFACE
ETC5057
ETC 50 54
VFRO
FSR
DR
5V or
~-------------.Dx
--------+1
-t
DIGITAL
INTERFACE
GNDA-------------+l BCLKR/CLKSEL
PDN --------t~M~C,!;L.!5.KR!!:/~P:ED~N!___ _ _ _~~~.......- - - BCLKx 12.048 MHz /1.544 MHzl
Note1: XMIT gain
~
20 X log ( Rl+R2)
R2 .
IR1 + R21 >10kn
CASE J16A
J SUFFIX
CERDIP PACKAGE
0.785
119.9391
MAX
0.220 - 0.310
15.588 - 7.8741
0.180
14.5721
0.005 - 0.020
0.200 10.127 - 0.5081
15.0801
RAD TVP
-I ,::: ::;:, j:r
~_.L..""_"~\
MAX
~
0.150
13.8101
MIN
.------+-+-4-!MI N
0.008-0.012
----10.203-0.3051
--0.080
12.0321
MAX
BOTH
ENOS
-
0.100 ±0.010
12.540 ± 0.2541
PHYSICAL DIMENSIONS
4·38
ETC5067·ETC5064
r.l0NOLITHIC SERIAL INTERFACE CODEC/FILTER
WITH RECEIVE POWER AMPLLlFIER
COMMUNICATIONS PRODUCTS
CMOS
MONOLITHIC SERIAL INTERFACE CODEC/FILTER
WITH RECEIVE POWER AMPLIFIER
The ETC5064 (,.-Iaw) and ETC5067 (A-law) are monolithic PCM CODEC/FILTERS utilizing the AID and DIA conversion architecture shown in Figure 1,
and a aerial PCM interface. The devices are fabricated using National's advanced double-poly CMOS process (microCMOS).
Similar to the ETC5050 family, these devices feature an additional Receive Power
Amplifier to provide push-pull balanced output drive capacity. The receive gain
can be adjustad by means of two external resistors for an output level of up
to ± 6.6 V across a balanced 600 0 load.
Also included is an Analog Loopback switch and TSX output.
• Complete CODEC and filtering system including :
- Transmit high-pass and low-pass filtering.
- Receive low-pass filter with sin xIx correction.
- Active RC noise filters.
- I'-Iaw or A-law compatible COder and DECoder.
- Internal precision voltage reference.
- Serial 1/0 interface.
- Internal auto-zero circuitry.
- Receive push-pull power amplifiers.
• wlaw ETC6064
• A-law ETC5067
• Meets or exceeds all D3/04 and CCITT specifications.
• ± 5 V operation.
• Low operating power - typically 70 mW
;, Power-down standby mode - typically 3 mW
• Automatic power-down.
• TTL or CMOS compatible digital interfaces.
• Maximizes line interface card circuit density.
MONOLITHIC
SERIAL INTERFACE
CODEC/FILTER WITH
RECEIVE POWER AMPLIFIER
CASE J20A
20 lead Cavity
J SUFFIX
CERDIP PACKAGE
PIN ASSIGNMENT
VPO+
GNDA
VPO-
VBB
2
VFXI +
VFXGSX
VFRO
VCC
FSR
DR
4-39
ANLB
TSX
FSX
DX
BCLKR/CLKSEL
BCLKX
MCLKR/PDN
MCLKX
FIGURE 1 - BLOCK DIAGRAM
A2
VFX I Analog in-[=>--'....-!i~-j
Al
vro+
Ox
HC5067
TIMING
ANO
CONTAOl
HC5064
+5 V -5 V
L~~~ _____________ _
VCC VBB GNOA
MClKX BClKX MClKA/BClKA/ FSA FSx
rON ClKSEl
4-40
I
I
I
I
I
I
_J
PIN DESCRIPTION
NAME
PIN
TYPE
GNDA
GND
.
N°
o
VPO
The non-inverted output of the receive power amplifier.
Analog ground. All signals are referenced to this pin.
o
The inverted output of the receive power amplifier.
4
VPI
DESCRIPTION
Inverting input to the receive power amplifier. Also powers down both amplifiers when
connected to Ves
o
Vec
Analog output of the receive filter.
S
Positive power supply pin.
Vee = + 5 V ± 5%.
Receive frame sync pulse which enables BeLKA to shift PCM data into DR. FSA is an
8 kHz pulse train.
See Figures 2 and 3 for timing details.
8
Receive data input. PCM data is shifted into DR following the FSR leading edge.
The bit clock which shifts data into DR after the FSR Ie~ding edge. May vary from 64 kHz
eCLKR/CLKSEL
to 2.048 MHz.
Alternatively, may be a logic input which selects either 1.536 MHz/l.544 MHz or 2.048
MHz for master clock in synchronous mode and BCLKX is used for both transmit and receive
directions (see Table O.
10
Receive master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be synchronous
with MCLKX. but should be synchronous with MCLKX for best performance. When MeLKR
is connected continuously tow, MCLKX is selected for all internal timing. When
MCLKR is connected continuously high, the device is powered down.
MClKX
11
Transmit master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz.
eCLKX
12
The bit clock which shifts out the PCM data on OX- May vary from 64 kHz to 2.048 MHz,
but must be synchronous with MCLKX
13
The TRI-STATEo PCM data output which is enabled by FSX
14
Transmit frame sync pulse input which enables BCLKX to shift out the PCM data on Ox
FSX is an 8 kHz pulse train, see Figures 2 and 3 for timing details.
15
Open drain output which pulses low during the encoder time slot. Must
to be grounded if not used
16
Analog Loopback control input. Must be set to logic '0' for normal operation. When pulled
to logic '1', the transmit filter input is disconnected form the output of the transmit
preamplifier and connected to the VPO + output of the receive power amplifier.
17
Analog output of the transmit input amplifier. Used to externally set gain.
18
Inverting input of the transmit input amplifier.
May be asynchronous with MelKA
Ox
o
FSx
TSx
o
ANLB
GSx
o
VFX I
VeB
S
19
Non·inverting input of the transmit input amplifier.
20
Negative power supply pin. VSS = - 5 V
• I : Input, 0 : Output, S : Power supply.
TRI·STATE@is a trademark of National Semiconductor Corp.
4-41
± 5%,
FUNCTIONAL DESCRIPTION
POWER-UP
When power is first applied, power-on reset circuitry
initializes the COMBO and places it into the powerdown mode. All non-essential circuits are deactivated
and the Dx and VFRO outputs are put in high impedance states. To power-up the device, a logical low level or
clock must be applied to the MClKR/PDN pin and FSx
and/or FSR pulses must be present. Thus, 2 powerdown control modes are available. The first is to pull
the MClKR/PDN pin high; the alternative is to hold
both FSx and FSR inputs continuously low. The device
will power-down approximately 2 ms after the last
FSx or FSR pulse. Power-up will occur on the first FSX
or FSR pulse. The TRI-STATE PCM data output, Dx,
will remain in the high impedance state until the second FSx pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock
and bit clock should be used for both the transmit and
receive directions. In this mode, a clock must be applied to MClKx and the MClKR/ PDN pin can be used
as a power· down control. A low level on MClKR/PDN
powers up the device and a high level powers down
the device. In either case, MClKx will be selected as
the master clock for both the transmit and receive circuits. A bit clock must also be applied to BClKx and
the BClKR/ClKSEl can be used to select the proper
internal divider for a master clock of 1.536 MHz,
1.544 MHz or 2.048 MHz. For 1.544 MHz operation,
the device automatically compensates for the 193rd
clock pulse each frame.
With a fixed level on the BCLKR/ClKSEl pin, BClKX
will be selected as the bit clock for both the transmit
and receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on
the state of BClKR/ClKSEL. In this synchronous mode, the bit clock, BClKx, may be from 64 kHz to 2.048
MHz, but must be synchronous with MClKx.
TABLE 1 - SELECTION OF MASTER CLOCK
FREQUENCIES
BCLKR/CLKSEL
Clocked
0
1 (or open circUit)
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and
receive clocks may be applied. MClKx and MClKR
must be 2.048 MHz for the ETC5067 ,or 1.536 MHz,
1.544 MHz for the ETC5064 , and need not be synchronous. For best transmission performance,
however, MClKR should be synchronous with MClKX,
which is easily achieved by applying only static logic
levels to the MClKR/ PON pin. This will automatically
connect MClKX to all internal MClKR functions (see
Pin Description). For 1.544 MHz operation, the device
automatically compE'nsates for the 193rd clock pulse
each frame. FSx starts each encoding cycle and must
be synchronous with MClKX and BClKX. FSR starts
each decoding cycle and must be synchronous with
BClKR. BClKR must be a clock, the logic levels shown
in Table 1 are not valid in asynchronous mode. BClKx
and BClKR may operate from 64 kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse
or a long frame sync pulse. Upon power initialization,
the device assumes a short frame mode. In this mode,
both frame sync pulses, FSx and FSR, must be one bit
clock period long, with timing relationships specified
in Figure 3. With FSx high during a falling edge of
BClKx, the next rising edge of BClKx enables the DX
TRI-STATE output buffer, which will output the sign
bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge disables
the Dx output .. With FSR high during a falling edge of
BClKR (BClKx in synchronous mode), the next falling
edge of BClKR latches in the sign bit. The following
seven falling edges latch in the seven remaining bits.
Both devices may utilize the short frame sync pulse in
synchronous or asynchronous operating mode.
LONG FRAME SYNC OPERATION
Master clock
frequency selected
ETC5067
ETC5064
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
Each FSx pulse begins the encocting cycle and the
PCM data from the previous encode cycle is shifted
out of the enabled DX output on the positive edge of
BClKx. After 8 bit clock periods, the TRI-STATE Dx
output is returned to a high impedance state. With an
FSR pulse, PCM data is latched via the OR input on the
negative edge of BClKx(or BClKR if running). FSx and
FSR must be synchronous with MClKx/R.
1.536 MHz or
1.544 MHz
4-42
To use the long frame mode, both the frame sync pulses, FSx and . FSR, must be three or more bit
clock periods long, with timing relationships specified
in Figure 4. Based on the transmit frame sync. FSx, the
COMBO will sense whether short or long frame sync
pulses are being used. For 64 kHz operation, the frame
sync pulse must be kept low for a minimum of 160 ns
(See Fig. 2). The Ox TRI-STATE output buffer is enabled with the rising edge of FSX or the rising edge of
BClKX. whichever comes later. and the first bit clocked out is the sign bit. The following seven BClKx rising edges clock out the remaining seven bits. The Ox
output is disabled by the falling BClKx edge following
the eighth rising edge•.or by FSX going low. whichever
comes later. A rising edge on the receive frame sync
pulse. FSR. will cause the PCM data at DR to be latched
in on the next eight falling edges of BClKR (BClKx in
synchronous mode). Both devices may utilize the long
frame sync pulse in synchronous or asynchronous mode.
TRANSMIT SECTION
The transmit section input is an operational amplifier
with provision for gain adjustment using two external
resistors. see Figure 5. The low noise and wide bandwidth allow gains in excess of 20 dB across the audio
passband to be realized. The op amp drives a unitygain filter consisting of RC active pre-filter. followed
by an eighth order switched-capacitor bandpass filter
clocked at 256 kHz. The output of this filter directly
drives the encoder sample-and-hold circuit. The AID
is of cO)'llpanding type according to A-law ( ETC5067 )
or "law ( ETC5064 ) coding conventions. A precision
voltage reference is trimmed in manufacturing to provide an input overload (tMAX) of nominally 2.5V peak
(see table of Transmission Characteristics). The FSx
frame sync pulse controls the sampling of the filter
output. and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into a
buffer end shifted out through Ox at the next FSx pulse. The total encoding delay will be approximately
165" s (due to the transmitfilter) plus 125" s (dueto
encoding delay). wl)ich totals 290" Any offset voltage due to the filters or comparator is cancelled by
sign bit integration.
.
s.
~BSOLUTE
Rating
RECEIVE SECTION
The receive section consists of an expanding DAC
which drives a fifth order switched-capacitor low pass
filter clocked at 256 kHz. The decoder is A-law
( ETC5067 ) or" -law ( ETC5064 ) and the 5th order low
pass filter corrects for the sin xix attenuation due to
the 8 kHz sample and hold. The filter is then followed
by a 2nd order RC active post-filter and power amp"fier capable of driving a 600 n load to a level of
7.2 dBm. The receive section is unity-gain. Upon the
occurence of FSR. the data at the DR input is clocked in
on the falling edge of the next eight BClKR (BCLKx)
periods. At the end of the decoder time slot. thedecoding cycle begins. and 10 " s later the decoder DAC
output is updated. The total decoder delay is -1 0 " s
(filter delay) plus
(decoder update) plus 1; 0
62.5
(1 I 2 frame). which gives approximately
180" S.
"S
"S
RECEIVE POWER AMPLIFIERS
TwO inverting mode power amplifiers are provided for directly
driving a matched line interface transformer. The gain of the
first power amplifier can be adjusted to boost the ± 2.5 V
peak output signal from the. receive filter up ± 3.3 V peak
into an unbalanced 300 n load. or ± 4.0 V into an unba·
lanced 15 kn load. The second power amp Iifier is internally connected in unity-gain inverting mode to give 6 dB
of signal gain for balanced loads.
Maximum power transfer to a 6000 subscriber line termination
is obtained by differentially driving a balanced transformer
with a V2, 1 turns ratio. as shown in Figure 2. A total peak
power of 15.6 dBm can be delivered to the load plus
termination.
Both power amplifiers can be powered down independently
from the PDN input by connecting the VPI input to VBB.
saving approximately 12 mW of power.
MAXIMUM RATINGS
Symbol
Valua
Unit
Vee to GNDA
Vee
7
V
Vss to GNDA
Vsa
-7
V
VIN. Vour
Vee +0.3 to
Vae -0.3
V
Vee +0.3 to
GNDA-0.3
V
Voltage at any analog input
or output
Voltage at any digital input
or output
Operating temperature range
Storage temperature range
, Toper
Tstg
Lead temperature
(soldering. 10 seconds)
4·43
-25to+125
'C
-65 to +150
'C
300
'C
ELECTRICAL CHARACTERISTICS
Vcc=5.0V±5%, VBB=-5V±5%,GNDA=OV, TA=O'C to 70'C (Unless otherwise noted); typical
characteristics specified at VCC = 5.0V, VBB = - 5.0V, TA = 25'C;all signals are referenced to GNDA.
DIGITAL INTERFACE
Characteristic
Symbol
Min
Typ
Max
Unit
I nput low voltage
V,L
-
-
0.6
V
Input high voltage
V,H
2.2
-
-
V
Output low voltage
IL=3.2mA
IL =3.2mA. open drain
VOL
-
-
0.4
0.4
2.4
10
~A
10
~A
~
TSx
Output high voltage
IH=-3.2rnA
Input low current
VOH
IlL
-10
IIH
-10
-
-10
-
10
Dx
(GNDA':::VIN:SVIL, all digital inputs)
Input high current
(VIH-"'VIN:SVCC)
Output current in hight impedance state (TRI-STATE)
IOZ
(GNDA.:s:VO:SVcc)
DX
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
Input leakage current
Input resistance
(-2.5V:S v:S +2.5V)
(-2.5V'::: V-'" +2.5V)
IIXA
-200
-
200
nA
RIXA
10
-
-
MQ
GSx
(RL~lOkl! )
ROXA
-
1
3
Q
RLXA
10
-
-
kfl
GSX
CLXA
-
-
50
pF
GSx
VOXA
± 2.8
-
AvXA
5000
-
-
V/V
MHz
20
mV
Load capacitance
Voltage gain
~A
VFXI+ or VFXI
Load resistance
Output dynamic range
V
VFXI+ or VFxl
(closed loop, unity gain)
Output resistance
V
(VFxl+ to GSX)
Unity gain bandwidth
V
FuXA
,I
2
Offset voltage
VOSXA
-20
Common¥mode voltage
VCMXA
-2.5
-
2.5
V
Common-mode rejectio'n ratio
CMRRXA
60
-
-
dB
Power supply rejection ratio
PSRRXA
60
-
-
dB
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
Output resistance
Load resistance
VFRO
IVFRO=
± 25VI
Load capacitance
Output DC offset voltage
RORF
-
1
3
(I
RLRF
10
-
-
kU
CLRF
-
-
25
PF
VOSRO
-200
-
200
MV
-
100
nA
-
M{l
-
25
ANALOG INTERFACE WITH POWER AMPLIFIERS IAII devlcesl
Input leakage current! -1.0 V ~ VPI ~ 1.0 V)
Input resistance ( - 1.0 V ~ VPI ~ 1.0 V)
Input offset voltage
Output resistance (inverting unity-gain at VPO + or VPO
Unity-gain bandwidth, open loop (VPO
I
I
Power supply rejection of Vee or Ves (VPO
o kHz· 4 kHz
o kHz· 50 kHz
-100
10
VI OS
-25
ROP
-
1
-
mV
{l
400
-
kHz
-
-
100
500
1000
-I
-
60
36
-
-
0.5
1.5
rnA
0.05
0.3
mA
7.0
10.0
mA
7.0
10.0
rnA
FC
Load capacitance IVPO + or VPO - to GNDAI
RL;;.l500 (l
RL=6000
RL=300 !l
Gain VPO - to VPO + to GNDA, level at VPO
IPI
RIPI
CLP
=1.77 Vrms,,"3 dBmO)
connected to VPI)
GAp+
PSRRp
pF
-
V/V
dB
POWER DISSIPATION (ALL DEVICES)
Power -down current
ICCO
Power-down current
IssO
Active current
Icc 1
-
Active current
lee 1
-
4-44
TIMING SPECIFICATIONS
Characteristic
Frequency of master clocks
Symbol
Min
Typ
Max
Unit
l/tPM
-
1.536
-
MHz
1.544
2.048
-
-
Depends on the device used and the
BCLKA/CLKSEL Pm
MCLKxand MCLKA
Width of master clock high
MCLKX and MCLKA
tWMH
160
-
-
ns
Width of master clock low
MCLKx and MCLKA
IWMl
160
-
ns
Rise time of master clock
MCLKx and MClKA
tAM
-
-
50
ns
Fall time of master clock
MCLKx and MCLKA
tFM
-
-
50
ns
tPB
485
488
15.725
ns
tWBR
160
-
-
ns
Period of bit clock
W,dth of bit clock high
(V'H=2.2V)
Width of bit clock low
(V'L=0.6V)
tWBL
160
-
-
ns
Rise time of bit clock
(tpB=488ns)
tRB
-
-
50
ns
tFB
-
-
50
ns
tSBFM
100
-
-
ns
tHBF
0
-
-
ns
Fall time of b,t clock
(tpB=488ns)
Set-up time from BCLKx high to MCLKx falling edge.
(First bit clock after the leading edge of FSx)
Holding time from bit clock low to the frame sync
lIong frame only)
Set-up time from frame sync to bit clock low (long frame only)
tSFB
80
-
-
ns
Hold time from 3rd period of bit clock
tHBFI
100
-
-
ns
tDZF
20
-
165
ns
tDBD
0
-
150
ns
Delay time from BCLKx low to data output disabled
tDze
50
ns
tSDB
50
-
165
Set-up time from DA valid to BCLKA/X low
-
ns
Hold time from BCLKR/X low to DA ,nvalid
tHBD
50
-
ns
tHOLD
0
-
-
Set-up time from FSX/R to BCLKX/R low
(short frame sync pulse) - Note 1
tSF
50
-
-
ns
Hold time from BCLKX/A low to FSX/A low
(short frame sync pulse) - Note 1
tHF
100
-
-
ns
FSX or FSR
low to frame sync (long frame only)
Delay time to valid data from FSx or BCLKX, whichever comes
later and delay time from FSx to data output disabled
(CL=O pF to 150 pF)
Delay time from BCLKx high to data valid
(Load =150 pF plus 2 LSTTL loads)
Holding time from bit clock high to frame sync
ns
(short frame only)
Delay time to TSX low
(load=150 pF plus 2 LSTTL loads)
Minimum width of the frame sync pulse (low level)
tXDP
-
-
140
ns
tWFl
160
-
-
ns
(64k bit/s operating mode)
Notel: For short frame sync timing, FSX and FSR must go high while their respective bit clocks are hIgh.
--~
~~:- - -li
I
\
\.._-------
tWFL_
FIGURE 2 - 64 k bits/s TIMING DIAGRAM (See next page for complete timing)
4-45
1$,
J
,(_htH'
t01C_:
Mel",
Mel 1< .•
BLel<,
,
FS,
,#-
lOBO
D,
(
I
X
X
3
-I
r-
X,
ID:~I
X ,X
BCLKu
FS H
DR
FIGURE 3 - SHORT FRAME SYNC TIMING
b
X '
0J--
MelK.
MCLK .•
BCLKx
FS.
+:
tHBFI
,-1
-ton
~
[j,
--------~'U'__-~ ~_ _ _ ~_ __
J.
.....
~~=l~
-":.:'~
li)/!
iJelK.
\
,s,
\
\
\
t'
\
Do.
FIGURE 4 - LONG FRAME SYNC TIMING
TRANSMISSION CHARACTERISTICS
(All devices) TA = O"C to 70"C, VCC = 5V ± 5%, VBB = -5V ± 5%, GNDA = OV, f = 1.02 kHz, VIN
transmit input amplifier connected for unity-gain non-inverting. (Unless otherwise specified)
=0
dBmO
AMPLITUDE RESPONSE
Characteristic
Absolute levels - Nominal 0 dBmO level
o dBmO ETC5067, ETC5064
Symbol
IS
Max overload level
ETC5067
ETC5064
Transmit gain, absolute (TA = 25"C, Vee
Input at GSx = 0 dBmO at 1020 Hz
= 5V.
VBB
= -5V)
Transmit gain, relative to GXA
= 60Hz
= 180Hz
=
=
=
=
Absolute transmit gain variation with temperature
(T A ;= O°C to + 70 D e)
GXAT
Absolute transmit gain variation with supply voltage
GXAV
VBB = -5V.:!. 5%)
Transmit gain variations with level
Receive gam, absolute ITA = 25"C, Vee = 5V, VBB = -5V)
Input = digital code sequence for OdBmO signal at 1020Hz
GRA
Receive gain, relative to GRA
GRR
OHz to 3000 Hz
3300Hz
3400Hz
4000Hz
Absolute receive gain variation with temperature
IT A
= O"C
to + 70"C)
Vrms
-
2.492
2.501
-
-0.15
-
0.15
-
-
VPK
Receive gain variations with level
Sinusoidal test method;reference input PCM code
corresponds to an ideally encoded -1 OdBmO'signal
dB
-
-
-40
-30
-26
-0.2
-0.1
0.15
0.05
0
-14
-32
-
-
±0.1
-
-
±0.05
-0.2
-0.4
-1.2
-
-
0.2
0.4
1.2
-0.15
-
0.15
-0.15
-0.35
-0.7
-
-
0.15
0.05
0
-14
-
-
:':0.1
-
-
:': 0.05
-
dB
dB
dB
dB
dB
dB
-1.2
-
0.2
0.4
1.2
-2.5
-
2.5
-0.2
-0.4
= -50dBmO
to -40dBmO
-55dBmO to -50dBmO
RL = 10 kn
VRO
4·48
dB
dB
GRRL
= -40dBmO to +3dBmO
Receive filter output at YFRO
dB
GRAV
(Vee = 5V~ 5%, Vss = -5V~ 5%)
=
-
GRAT
Absolute receive gain variation with supply voltage
PCM level
PCM level
PCM level
1.2276
GXRL
Sinusoidal test method reference level = -10dBmO
VFxl+ = -40dBmO to +3dBmO
VFxl+ = -50dBmO to -40dBmO
VFXI+ = -55dBmO to -50dBmO
=
=
=
=
-
-2.8
-1.8
-0.15
-0.35
-0.7
= 200Hz
300Hz-3000 Hz
3300Hz
3400Hz
4000Hz
f = 4600Hz and up,measure reponse from OHz to 4000Hz
f
f
f
f
Unit
GXA
= 50Hz
5010,
Max
GXR
= 16Hz
(Vee = 5V ±
Typ
tMAX
3.14 dBmO
3.17 dBmO
f
f
f
f
f
f
f
f
f
Min
4 dBm (6000)
V
TRANSMISSION CHARACTERISTICS
(All devices) TA = O'C to + 70'C, Vcc = 5V
± 5%, VBB = -5V ± 5%, GNDA = OV, f = 1.02 kHz, VIN
transmit input amplifier connected for unity-gain non-inverting. (Unless otherwise specified)
=0
dBmO,
ENVELOPE DELAY DISTORTION WITH FREQUENCY
Characteristic
Transmit delay, absolute
(I = t600Hz)
Transmit delay, relative to DXA
I = 500Hz-600Hz
I = 600Hz-800Hz
1= 800Hz- 1000 Hz
I = I OOOHz- 1600Hz
I = 1600Hz-2600Hz
I = 2600Hz-2800Hz
I = 2800Hz-3000Hz
Receive delay, absolute
Symbol
Min
Typ
Max
Unit
DXA
-
290
315
~s
-
195
120
50
20
55
80
130
220
145
75
40
75
105
155
-
180
200
-40
-30
-
-
-25
-20
70
100
145
-
-74
DXR
(I = 1600Hz)
DRA
Receive delay, relative toDRA
1= 500Hz- 1000Hz
f = I OOOHz- 1600Hz
I = 1600Hz-2600Hz
I = 2600Hz-2800Hz
I = 2800Hz-3000Hz
~s
DAR
~s
~s
-
-
90
125
175
NOISE
Transmit noise. P message weighted
(ETC5067. VFxl+ = OV)
Nxp
-69
dBmOp
(Note 11
Receive noise, P message weighted
(ETC5067,
PCM code equals positive zero)
Transmit noise. C message weighted
NAP
(ETC5064, VFxl+ = OV)
NxC
Receive noise, C message weighted
ETC5064 , PCM code equals alternating positive and
negative zero
NRC
Noise, single frequency
1= OkHz to 100kHz, loop around measurement.
VFxl+ = OVrms
NRS
Positive power supply rejection. transmit
VFxl+ = OVrms, VCC = S.OVoc+l OOmVrms,1 = OkHz-50kHz
PPSRx
Negative power supply rejection. transmit
VFXI+ = OVrms)/ee = -5.0VOC+l OOmVrmsl = OkHz-50kHz
NPSRx
Positive power supply rejection, receive
(PCM code equals positive zero, Vce = 5.0Voc+l00mVrms)
I = OHz-4000Hz
I = 4kHz-25kHz
I = 25kHz-50kHz
PPSRR
Negative power supply rejection, receive
NPSRR
(PCM code equals positive zero, Vee = -S.OVoc+l00mVrms)
1= OHz-4000Hz
I = 4kHz-25kHz
I = 25kHz-50kHz
4-49
dBmOp
-
-82
-79
-
12
IS
-
8
II
dBrnCO
dBrnCO
dBmO
-
-
-53
40
-
-
40
-
-
40
40
36
-
-
dBp
dB
dB
40
40
36
-
-
dBp
dB
dB
dBp
dBp
-
-
TRANSMISSION CHARACTERISTICS (Continued)
(All devices) TA = O°C to+ 70°C, Vee = 5V ± 5%, VBB = -5V ± 5%, GNDA = OV, f = 1.02 kHz, VIN = 0 dBmO,
transmit input amplifier connected for unity-gain non-inverting. (Unless otherwise specified)
Characteristic
Symbol
Min
Typ
Max
Unit
SOS
-
-
-30
dB
-
-
-32
-40
-32
Spurious out-af-band signals at the channel output
Loop around measurement, 0 dBmO, 300Hz-3400Hz Input
applied to VFxl+, measure individual image signals at VFRO
4600Hz-7600Hz
7600Hz-8400Hz
8400Hz-l00,OOOHz
-
-
DISTORTION
Signal to total distortion
(sinusoidal test method)
dBp
STDx
or
STDR
Transmit or receive half-channel
Level = 3.0dBmO
= OdBmO to -30dBmO
= -40dBmO
-
33
36
29
30
14
15
-
-
-
Single frequency distortion, transmit
SFOx
-
-
-46
dB
Smgle frequency distortion, receive
SFDR
-
-
-46
dB
IMO
-
-
-41
dB
-
-90
-75
-
-90
XMT
Rev
XMT
RCV
= -55dBmO
Intermodulation distortion
Loop around measurement,VFXI+ = -4dBmO to -21 dBmO,
two frequencies In the range 300Hz-3400Hz
-
CROSSTALK
Transmit to receive crosstalk, OdBmO transmit level
f = 300Hz· 3400Hz. DR = steady PCM code
CTX_R
Receive to transmit crosstalk, OdBmO receive level
f = 300Hz-3400Hz, VFxl = OV
CTR_X
dB
dB
-70
(Note 2)
POWER AMPLIFtERS
Maximum 0 dBmO level for better than ± 0.1 dB linearity over the range
Vrms
VOL
10 dBmO to +3 dBmO (balanced load, RL connected between VPO+
and VPQ-
I
I
RL~600n
RL~1200n
RL~30kn
Signal I distortion RL
=0
600
n,
SlOp
0 dBmO
3.3
3.5
4.0
-
-
-
50
-
-
dB
Notel: Measured by extrapdation from the distortion test result
Note 2 : CTMX is measured with a - 40 dBmO activating signal applied at VFXI +
ENCODING FORMAT AT Ox OUTPUT
A-Law
(includes even bit inverSion)
V1N(at GS x) = +Full-scale
V'Nlat GSxi
= OV
V1N(at GS x) = -Full-scale
1
l~
0
0
1
1
0
1
0
0
1
0
1
1
0
4·50
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
~Law
1
l~
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
APPLICATIONS INFORMATION
POWER SUPPLIES
This minimizes the interaction of ground return currents flowing through a common bus impedance.
0.1 ~ F supply decoupling capacitors should be connected from this common ground point to VCC and
VSS·
While the pins ot the ETC5060 family are well protected against electrical misuse, it is recommended that
the standard CMOS practice be followed, ensuring
that ground is connected to the device before any
other connections are made. In applications wher~ the
printed circuit board may be plugged into a "hot" socket with power and clocks already present, an extra
long ground pin in the connector is useful.
For best performance, the ground point of each CODEC/
FILTER on a card should be connected to a common card
ground in start formation, rather than via a ground bus. This
common ground point should be decoupled to VCC and VBS
with 10 ~F capacitors.
All ground connections to each device should meet at
a common point as close as possible to the GNDA pin.
For best performance either, TSX should be grounded if not used.
TYPICAL ASYNCHRONOUS APPLICATION
600
v'2
HYBRID
1 300
12
300
R2
Rl
R3
R4
ANALOG lOOPBACK
TSx
FSR
FSx
DR
Ox
BClKR
BClKX
MClKR/PDN
MCKlX
Notel: Transmit gain =: 20 x log
(-~lA+2 R2)- (Rl + R2)~ 10 kU
Note 2 : Receive gain'" 20 x log ( )
~:3), R4~ 10
FIGURE 2
4-51
kll
CASE J20A
20 Lead Cavity
J SUFFIX
CERDIP PACKAGE
4·52
MI{5116(J,N)
-255 LAW COMPANDING CODEC
COMMUNICATIONS PRODUCTS
FEATURES
o
±5-Volt Power Supplies
o
Low Power Dissipation - 30mW (Typ)
o
Follows the w255 Companding Law
o
Synchronous or Asynchronous Operation
o
PIN CONNECTIONS
Figure 1
ANALOG INPUT _ _ 1
•
16_+VREF
15--VREF
14_ANALOG GROUND
13 _ _ ANALOG OUTPUT
N/C -
On-chip sample and hold
1 2 _ DIGITAL INPUT
MASTER CLOCK -
o On-Chip Offset Null Circuit Eliminates Long:rerm Drift
Errors and Need for Trimming
o
Single 16-Pin Package
o
Minimal External Circuity Required
XMITSYNC _
1 1 _ DIGITAL GROUND
XMITCLOCK _
1 0 _ RCV CLOCK
9_RCVSYNC
DIGITAL OUTPUT-
o Serial Data Output of 64kb/s-2.1 Mb/s at 8kHz Sampling Rate
o Separate Analog and Digital Grounding Pins Reduce
System Noise Problems
DESCRIPTION
A block diagram of a PCM system using the MK5116 is
shown in Figure 2.
PCM SYSTEM BLOCK DIAGRAM
Figure 2
The MK5116 is a monolithic CMOS companding CODEC
which contains two sections: (1) An analog-to-digital converter which has a transfer characteristic conforming to
the w255 companding law and (2) a digital-te-analog converter which also conforms to the w255 law.
TRANSMITTER
These two sections form a coder-decoder which is
designed to meet the needs of the telecommunications
industry for per-channel voice-frequency codecs used
in telephone digital switching and transmission systems.
Digital input and output are in serial format. Actual
transmission and reception of 8-bit data words containing the analog information is done at a 64kb/s-2.1 Mb/s
rate with analog signal sampling occurring at an 8kHz
rate. A sync pulse input is provided for synchronizing
transmission and reception of multi-channel information
being multiplexed over a single transmission line.
The pin configuration of the MK5116 is shown in Figure 1.
(A/'DI
2 WIRE
DIGITAL
TAUNK
C",UI
I
RECEIVER
I
ID/.I.'
I
I
DIGITAL
TRUNK
I
I
I
I
L
~C~E~~N~ _ _ _
FUNCTIONAL DESCRIPTION: (Refer to Figure 3 for a ,
Blo~k Dragram)
XMIT SYNC, Pin 6 (Refer to Figure 10 for the Timing
Diagram)
MK511~ BLOCK DIAGRAM
This input is synchronized with XMIT CLOCK. When
XMIT SYNC goes high, the digital output is activated, and
the ND conversion begins on the next positive edge of
MASTER CLOCK. The conversion by MASTER CLOCK
can be asynchronous with XMIT CLOCK. The serial output data is clocked out by the positive edges of XMIT
CLOCK. The negative edge of XMIT SYNC causes the
digital output to become three-state. XMIT SYNC may remain high longer than 8 XMIT CLOCK cycles, but must
go low for at least 1 master clock before the transmission of the next digital word (refer to Figure 12).
Flgunt 3
~--------------~--~
XMIT
SYNC
>
ns
XMIT Clock-to-XMIT Sync
(Negative Edge) Delay
200
ns
txss
XMIT Sync Set-Up Time
200
txoo
XMIT Data Delay
txop
XMIT Data Present
tXDT
XMIT Data Three State
tOOF
Digital Output Fall Time
tOOR
Digital Output Rise Time
tSRC
RVC Sync-to-Rev Clock Delay
tROS
6
ns
0
200
ns
4
0
200
ns
4
150
ns
4
50
100
ns
4
50
100
ns
4
50% of
tRC (tFS>
ns
6
Rev Data Set-Up Time
50
ns
7
tRDH
Rev Data Hold Time
200
ns
7
tRCS
Rev Clock-to-Rev Sync Delay
200
ns
tRSS
Rev Sync Set-Up Time
200
tSAO
Rev Sync-to-Analog Output Delay
7
p.S
SLEW+
Analog Output Positive Slew Rate
1
V/p.S
SLEW-
Analog Output Negative Slew Rate
1
V/p.S
DROOP
Analog Output Droop Rate
25
p.V/p.s
ns
AC CHARACTERISTICS (Refer to Figures 14 and 15)
SYM
PARAMETER
MIN
TYP
MAX
UNITS TEST CONDo
0.0
±0.1
±0.2
+.2
+.4
+1.25
dB
dB
dB
Analog Input=+3 to -37dBmO
Analog Input=-37 to -5OdBmO
Analog Input =-50 to -55dBmO
Relative to 0 dBmO
GTx
Gain Tracking Transmit
-.2
-.4
-1.25
GTR
Gain Tracking Receive
-.2
-.4
-1.25
0.0
±0.1
±0.2
±.2
+.4
+1.25
dB
dB
dB
Input Level =+3 to -37dBmO
Input Level =-37 to -SOdBmO
Input Level =-50 to -55dBmO
Relative to 0 dBmO
GTE_E
Gain Tracking End to End
-.4
0.0
±0.1
±0.2
+.4
+.8
+2.50
dB
dB
dB
Analog Input=+3 to -37dBmO
Analog Input=-37 to -5OdBmO
Analog Input=-50 to -55dBmO
Relative to 0 dBmO
-.8
-2.50
SDx
Signal to Distortion Transmit
'31
31
26
dB
dB
dB
Analog Input=O to -3OdBmO
Analog Input= -4OdBmO
Analog Input= -45dBmO
SDR
Signal to Distortion Receive
'31
31
26
dB
dB
dB
Input Level=O to -3OdBmO
Input Level= -4OdBmO
Input Level = -45dBmO
4-59
7
AC CHARACTERISTICS (Refer to Figures 14 and 15)
SYM
PARAMETER
SDE_E
Signal to Distortion End to End
MIN
TYP
MAX
UNITS TEST CONDo
Nx
Idle Channel Noise Transmit
17
dBncO Analog Input=O Volts
NR
N E_E
Idle Channel Noise Receive
0
dBncO Digital Input=O Code
Idle Channel Noise End to End
18
dBncO Analog Input=O Volts
CT RX
Crosstalk Receive to Transmit
-80
dB
Analog In = -50 dBmO at 2600 Hz
Digital Input= 0 dBmO at
t008 Hz digital
CTXR
Crosstalk Transmit to Receive
-80
dB
Analog In =0 dBmO at 1008 Hz
Digital Input=O Code
TLP
Transmission Level Point
dB
6000
dB
dB
dB
35
29
24
Analog Input=O to -30 dBmO
Analog Input= -40 dBmO
Analog Input = -45 dBmO
Digital Output to Digital Input
NOTES:
1. +VAEF and -VREF must be matched within
±
+4
1% in order to meet system
requirements.
2. Sampling is accomplished by charging an internal capacitor; therefore, the
designer should avoid excessive source impedance.
Input~related
RECOMMENDED ANALOG INPUT CIRCUIT
Figure 9
device
CODEC
characteristics are derived using the Recommended Analog Input Circuit.
See Figure 9.
3. When a transition from a "1" to a "0" takes place. the user must sink the
"1" current until reaching the "0" level.
4. Oriving 30pF with 10H = 100pA, 10L = SOO.A.
I
I
I
I
5. Results in 30 mW typical power dissipation (clocks applied) under normal
SOURCE
operating conditions.
6. This delay is necessary to avoid overlapping CLOCK and SYNC.
7. The first bit of data is loaded when the Sync and Clock are both "1" during
bit time 1 as shown on ReV timing diagram.
f"'!'(,'lit ..
-
I
I
I
I
4-60
TYPICAL
C INA , RINAS
I
I
-=-
I
I
I
TRANSMITTER SECTION TIMING
Figure 10
2.4V
1.4V
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V.
RECEIVER SECTION TIMING
Figure 11
2.4V
1.4V
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V.
4-61
64kHz OPERATION, TRANSMITTER SECTION TIMING
Figure 12
I~~~---------------------------------125"sec----------------------------------~
~
XMITSVNC
T~!SIGN8IT
MSB
S~'(NEXTWOROt
)
l
V
PCM DATA PRESENT
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V.
64kHz OPERATION, RECEIVER SECTION TIMING
Figure 13
~14~
______________________________ 125"SeC ________________________________
I ~CV SYNC
~
~
-I
I...-
,-
~·~1
I r;-;;;STER
LJ~~RIOOS
~~~~~
~
~
PWCLK
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V.
MK5116 SINGLE·ENDED SIGNAL TO DISTORTION
MK5116 SINGLE·ENDED GAIN TRACKING
Figure 14
Figure 15
INPUT LEVEL (dBmO)
INPUT LEVEL (dBmO)
4·62
r--(MINI
MI(5151(J,P)
.--a~
-255 LAW COMPANDING COOEC
.-~~-iiiiiiiiiiiiiiiiiii
____!11
COMMUNICA TIONS PRODUCTS
FEATURES
o ±5-Volt Power Supplies
o Low Power Dissipation - 30mW (Typ)
o Follows the p-255 Companding Law
o Zero Code Suppression and Sign-Magnitude Data
Format
an 8kHz rate. A sync pulse input is provided for
synchronizing transmission and reception of multichannel information being multiplexed over a single
transmission line.
The pin configuration of the MK5151 is shown in Figure
1.
PIN CONNECTIONS
Figure 1
o On-Chip Sample and Hold
DIGITAL OUTPUT _
1
XMIT CLOCK_2
AlB SEL (XMIT)_3
B SIGNAL IN_4
o On-Chip Offset Null Circuit Eliminates Long-Term
Drift Errors and Need for Trimming
A SIGNAL IN_5
RCV.SVNC_6
o Single 24-Pin Package
RCV. CLOCK_7
AlB SEL. (RCV.)_S
o Minimal External Circuitry Required
o Serial Data Output of 64kb/s - 2.1Mb/s at 8kHz
Sampling Rate
24-N/C
234-XMIT SYNC
22..-MASTER CLOCK
2'..-V+
20..-ANALOG INPUT
19 ........VREF
1S,,--VREF
17"-ANALOG GROUND
A SIGNAL OUT_9
B SIGNALOUT __ 10
16-N/C
DIGITAL INPUT-.,11
14..... ANALOG OUTPUT
13__ V-
DIGITAL GROUND .....12
15-N/C
o Separate Analog and Digital Grounding Pins Reduce
System Noise Problems
DESCRIPTION
The MK5151 is a monolithic CMOS companding
CODEC which contains two sections: (1) An analog-todigital converter which has a transfer characteristic
conforming to the 1'-255 companding law and (2) a
digital-to-analog converter which also conforms to the
1'-255 law.
A block diagram of a PCM system using the MK5151 is
shown in Figure 2.
PCM SYSTEM BLOCK DIAGRAM
Figure 2
These two sections form a coder-decoder which is
designed to meet the needs of the telecommunications
industry for per-channel voice-frequency codecs used
in telephone digital switching and transmission
systems. Digital input and output are in serial format.
Actual transmission and reception of 8-bit data words
containing the analog information is done at a 64kb/s2.1 Mb/s rate with analog signal sampling occuring at
,
I
~ l~C~f~H~"~
4-63
__ _
FUNCTIONAL DESCRIPTION: (Refer to Figure 3 for
a Block Diagram)
XMIT SYNC, Pin 23 (Refer to Figure 12 for the
Timing Diagram)
MK5151 BLOCK DIAGRAM
Figure 3
This input is synchronized with XMIT CLOCK. When
XMIT SYNC goes high, the digital output is activated and
the AID conversion begins on the next positive edge of
MASTER CLOCK. The conversion by MASTER CLOCK
can be asynchronous with XMIT CLOCK. The serial
output data is clocked out by the positive edges of XMIT
CLOCK. The negative edge of XMIT SYNC causes the
digital output to become three-state. XMIT SYNC must
go low for at least 1 master clock prior to the
transmission of the next digital word. (Refer to Figure
14).
,-______________-,
g~G;;~~
XMITCLOCK, Pin 2 (Referto Figure 12 for the Timing
Diagram)
The on-chip 8-bit output shift register of the MK5151 is
unloaded at the clock rate present on this pin. Clock
rates of 64kHz -2.1 MHz can be used for XMIT CLOCK.
The positive edge of the INTERNAL CLOCK transfers the
data from tile master to the slave of a master-slave flipflop(Referto Figure 5). lithe positive edge of XMIT SYNC
occurs after the positive edge of XMIT CLOCK, XMIT
SYNC will determine when the first positive edge of
INTERNAL CLOCK will occur. In this event, the hold time
for the first clock pulse is measured from the positive
edge of XMIT SYNC.
RCV. SYNC, Pin 6 (Refer to Figure 13 for the timing
diagram)
6 SIG
OUT
ASIG
OUT
POSITIVE AND NEGATIVE REFERENCE
VOLTAGES (+VREF and -VREF) Pins 19 and 18
These inputs provide the conversion references for the
digital-to-analog converters in the MK5151 . +VREF and
-VREF must maintain 100ppM/'C regulation over the
operating temperature range. Variation of the reference
directly affects system gain.
ANALOG INPUT, Pin 20
Voice-frequency analog signals which are bandwidthlimited to 4kHz are input at this pin. Typically, they are
then sampled at an 8kHz rate (Refer to Figure 4.). The
analog input must remain between +VREF and -VREF
for accurate conversion. The recommended input interface
circuit is shown in Figure 11.
MASTER CLOCK, Pin 22
This signal provides the basic timing and control signals
required for all internal conversions. It does not have to
be synchronized with RCV. SYNC, RCV. CLOCK, XMIT
SYNC or XMIT CLOCK and is not internally related to
them.
This input is synchronized with RCV. CLOCK and serial
data is clocked in by RCV. CLOCK. Duration of the RCV.
SYNC pulse is approximately 8 RCV. CLOCK periods.
The conversion from digital-to-analog starts after the
negative edge of the RCV. SYNC pulse (Refer to Figure
4). The negative edge of RCV. SYNC should occur before
the 9th positive clock edge to insure that only eight bits
are clocked in. RCV. SYNC must stay low for 17
MASTER CLOCKS (min.) before the next digital word is
to be received (Refer to Figure 15).
RCV CLOCK, Pin 7 (Refer to Figure 13 for Timing
Diagram)
The on-chip 8-bit shift register forthe MK5151 is loaded
at the clock rate present on this pin. Clock rates of
64kHz-2.1 MHz can be used for RCV. CLOCK. Valid data
should be applied to the digital input before the positive
edge of the internal clock (Refer to Figure 5). This set up
time, \'(I)S, allows the data to be transferred into the
MASTER of a master-slave flip-flop. The positive edge of
the INTERNAL CLOCK transfers the data to the SLAVE
of the master-slave flip-flop. A hold time, tRI)II, is
required to complete this transfer. If the rising edge of
RCV. SYNC occurs after the first rising edge of RCV.
CLOCK, RCV. SYNC will determine when the first
positive edge of INTERNAL CLOCK will occur. In this
4-64
AID, DIA CONVERSION TIMING
Figure 4
1,1_~===~--------125'"SeC-----------_"~1
____1
XMIT SYNC
______~
SAMPLE AND HOLD
SAMPLE TIME
r-
\ ' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....
~='5-20J.lSeC~
=
\1
32 MASTER CLOCKS
~------------------------------------------------~
/1-0...
_--------
ENABLE SAR
SAR REQUIRES
=128 MASTER CLOCKS
--------------------------------~/
RCV, SYNC
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----'/ ANALOG OUTPUT UPDATED
DATA INPUT IOUTPUT TIMING
Figure 5
I..200ns .1
~
XMIT
Required For Data To Transfer
From Master to Slave
MK5151
I
Internal
Clock
________~X
DIGITAL
OUT
XMIT SYNC
~r---
Rev.
~
Internal
Clock
~
------.X
I
t-
Valid Data
XMIT CLOCK
ReqUired To Transfer DatCl
200ns From Master to Slave
DIGITAL
IN
Rev SYNC
.
~50ns Required to load Master
RCV CLOCK
Valid Incoming Data
DIGITAL OUTPUT, Pin 1
while the Chord and Step Bits indicate the magnitude. In
the first Chord, the Step Bit has a value of O.6mV. In the
second Chord, the Step Bit has a value of 1.2mV, This
doubling of the step value continues for each of the six
successive Chords.
The MK5151 output register stores the B-bit encoded
sample of the analog input. This B-bit word isshiftedout
under control of XMIT SYNC and XMIT CLOCK. When
XMIT SYNC is low, the DIGITAL OUTPUT is an open
circuit. When XMIT SYNC is high, the state of the
DIGITAL OUTPUT is determined by the value of the
output bit in the serial shift register. The output is
composed of a Sign Bit, 3 Chord Bits, and 4 Step Bits.
The Sign Bit indicates the polarity of the analog input
Each Chord has a specific value and the Step Bits, 16 in
each Chord, specify the displacement from that value
(Refer to Table 1 ). Thus the output, which follows the
J.L-255 law, has resolution that is proportional to the
input level rather than to full scale. This provides the
resolution of a 12-bit AID converter at low input levels
and that of a 6-bit converter as the input approaches full
scale, The transfer characteristic of the AID converter
(J.L-Iaw Encoder) is shown in Figure 6.
event, the set-up and hold times for the first clock pulse
should be measured from the positive edge of RCV.
SYNC.
4-65
DIGITAL INPUT, Pin 11
DIGITAL OUTPUT CODE p.-LAW
Table 1
Chord Code
1. 111
2. 110
3. 101
4. 100
5. 011
6. 010
7. 001
8. 000
Chord Value
O.OmV
10.11mV
30.3mV
70.8mV
151.7mV
313mV
637mV
1.284V
The MK5151 input register accepts the 8-bit sample of
an analog value and loads it under control ofRCV. SYNC
and RCV. CLOCK. The timing diagram is shown in
Figure 13. When RCV. SYNC goes high, the MK5151
uses RCV. CLOCK to clock the serial data into its input
register. RCV. SYNC goes low to indicate the end of
serial input data. The 8 bits of the input data have the
same functions described for the SERIAL OUTPUT. The
transfer characteristic of the 01 A converter (p.-Iaw
Decoder) is shown in Figure 7.
Step Value
0.613mV
1.226mV
2.45mV
4.90mV
·9.81mV
19.61mV
39.2mV
78.4mV
EXAMPLE:
ANALOG OUTPUT, Pin 14
1
100 1101 = +70.8mV + (2 x 4.90mV)
Sign Bit
Chord Step Bits
The analog output is in the form of voltage steps (1 00%
If the sign bit were a zero, then both plus signs would be
duty cycle) having amplitude equal tothe analog sample
changed to minus signs.
which was encoded. This waveform is then filtered with
an external low-pass filter with sinxlx correction to
AID CONVERTER (p.-Law Encoder) TRANSFER
recreate the sampled voice signal. When the 8th bit of
CHARACTERISTIC
the word is a signalling bit, it is assigned a value of y,
Figure 6
step. This results in a lower system quantization error
rate than would result if the bit were arbitarily set to 0
1000 0000
(no step) or 1 (full step).
1000 "11
10011111
10101111
OPERATION OF CODEC WITH 64kHz XMITlRCV.
CLOCK FREQUENCIES
10111111
...
11001111
~
~
11011111
S
}
01111 ",1
;i 01111111
~
(3
1i
XMITIRCV. SYNC must not be allowed to remain at a
logic "I" state. XMIT SYNC is required to be at a logic
"0" state for 1 master clock period (min.) before the next
digital word is transmitted. RCV. SYNC is required to be
at a logic "0" state for 17 master clock periods (min.)
before the next digital word is received (Refer to Figures
14 and 15).
1110 1111
- - - - t o..+++-t-t-HHH-+-+-+-++~
01101111
0101 1111
0100 1111
0011 1111
0010 1111
00011111
0000 1111
ooooooxx
SIGNALING"" 1. XX '" 01
SIGNALING" O.
xx " 10
NO SIGNALLING, XX = 10
-VREF
,
:.YB.li
-,-
.VREF
AlB SIGNAL IN, Pins 4 and 5
+VREF
ANALOG INPUT (VOL TS~
These two pins allow insertion of signalling information
into the transmitted data stream. The inserted
information occurs as the 8th bit (LSB) in the
transmitted word. A positive transition occuring on AlB
SEL (XMIT) selects A SIGNAL IN while a negative
transition selects B SIGNAL IN.
01 A CONVERTER (p.-Law Decoder) TRANSFER
CHARACTERISTIC
Figure 7
+VREF
2
AlB SIGNAL OUT, Pins 9 and 10
ANALOG OUTPUT
(VOLTS)
These two pins are provided to output received
signalling information. A positive transition on AlB SEL
(RCV.) routes the Signal bit to A SIGNAL OUT while a
negative transition routes the signal bit (bit 8) to B
SIGNAL OUT. Refer to Figure 8.
AlB SEL (XMIT), Pin 3
This input selects either A SIGNAL IN or B SIGNAL IN as
described in the AlB SIGNAL IN paragraph above, and
should be changed only at the start of the 6th and 12th
frames as shown in Figure 9.
SIGNALING'" 1, XX " 01
SIGNALING'" 0, xx "10
NO SIGNALLING. XX " 10
0DIGITAL INPUTS
4-66
AlB SEL (RCV.). Pin B
AlB SELECT TIMING
Figure 8
This input routes the signalling bit, bit 8. either to A
SIGNAL OUT or to B SIGNAL OUT as described in the
AlB SIGNAL OUT paragraph above. and should be
changed only at the start of the 6th and 12th frames as
shown in Figure 9.
- -- , - - - - - - - - - - - 1" 1 .4V
~=~ :~;;
--------''-------------- - - -- -
TIME SLOT 24
OFFSET NULL
The offset null feature of the MK5151 eliminates longterm drift errors and conversion errors due to
temperature changes by going through an offset
adjustment cycle before every conversion. thus
guaranteeing accurate AID conversion for inputs near
ground. There is no offset adjust of the output amplifier
because, since the output is intended to be AC - coupled
to the external filter, the resultant DC error (VOFFSET/O)
will have no effect. The sign bit is not used to null the
analog input. Therefore, for an analog input of 0 volts,
the sign bit will be stable.
A/BIN
..... - -
,--------
- - -
PERFORMANCE EVALUATION
1.4V RCV. SYNC. TIME SLOT 1 I
The equipment connections shown in Figure 10 can be
used to evaluate the performance of the MK5151. An
analog signal provided by the HP3551A Transmission
Test Set is connected to the Analog Input (Pin 20) of the
MK5151. The Digital Output of the CODECis tied back
to the Digital Input and the Analog Output is fed through
a low-pass filter to the HP3551 A. Remaining pins ofthe
MK5151 are connected as follows:
RCV.
CLOCK
SE_L_EC_T_R~C_V_.
~_/_B_O_~~1.4V
t
__
___________
_A_/B
A SIGNAL OUT OR B SIGNAL OUT
(1)
(2)
(3)
AlB SEL. (RCV.) is tied to AlB SEL. (XMIT).
RCV. SYNC is tied to XMIT SYNC.
XMIT CLOCK is tied to MASTER CLOCK. The signal
is inverted and tied to RCV. CLOCK.
The following timing signals are required:
SIGNALLING TIMING REQUIREMENTS FOR
PERFORMANCE EVALUATION
Figure 9
(1)
(2)
(3)
MASTER CLOCK = 1.536 MHz
XMIT SYNC repetition rate = 8kHz
XMIT SYNC width = 8 MASTER CLOCK periods
Additional timing signals are shown in Figure 9.
I
ReV,SYNC
A SIGNAL IN
't
I
When all the above requirements are met, the setup of
Figure 10 permits the measurement of synchronous
system performance over a wide range of analog inputs.
The data register and ideal decoder provide a means of
checking the encoder portion of the MK5151
independently of the decoder section. Totestthe system
in the asynchronous mode, MASTER CLOCK should be
separated from XMIT CLOCK and MASTER CLOCK
should be separated from RCV. CLOCK. XMIT CLOCK
and RCV. CLOCK are separated also.
I "I I
I
BSIGNAL IN
Some experimental results obtained with the MK5151
are shown in Figure 16 and Figure 17. In each case, both
the measured results and the corresponding D3
Channel Bank specifications are shown. The MK5151
exceeds the requirements for Signal-to-Distortion ratio
(Figure 17) and for Gain Tracking (Figure 16).
4·67
SYSTEM CHARACTERISTICS TEST
CONFIGURATION
Figure 10
IDEAL
DECODER
14
I
I
ENCODER
ONLY
SYSTEM
L
NOTE: The ideal decoder consists of a digital decompander and a 13-bit precision OAe.
ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage, V+ ............................................................................... +6V
DC Supply Voltage, V- ............................................................................... -6V
Ambient Operating Temperature, TA .............................................................. O°C to 70°C
Storage Temperature .................................................................... -55°C to +125°C
Package Dissipation at 25°C (Derated 9mW/oC when soldered into PCB) ............................ 500mW
Digital Input ............................................................................ -0.5V :S VIN :S V+
Analog Input ............................................................................. V- :S +VIN :S V+
+VREF .............................................................................. -O.5V:S +VREF :SV+
-VREF .......................................... , ..................................... V- :S -VREF :S 0.5V
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ELECTRICAL OPERATING CHARACTERISTICS
POWER SUPPLY REQUIREMENTS
UNITS
5.0
5.25
V
-5.0
-4.75
V
TYP
NOTES
PARAMETER
V+
Positive Supply Voltage
4.75
V-
Negative Supply Voltage
-5.25
+VREF
Positive Reference Voltage
2.375
2.5
2.625
V
1
-VREF
Negative Reference Voltage
-2.625
-2.5
-2.375
V
1
TEST CONDITIONS: V+
DC CHARACTERISTICS
MIN
MAX
SYM
= 5.0 V, V- = -5.0 V, + VREF = 2.5 V, -VREF = -2.5 V, TA = O°C to 70°C
MIN
PARAMETER
RINAS
Analog Input Resistance During Sampling
2
k!1
RINANS
Analog Input Resistance Non-Sampling
100
M!1
CINA
Analog Input Capacitance
150
4·68
TYP
MAX UNITS
SYM
250
pF
NOTES
2
2
DC CHARACTERISTICS CONTINUED
SYM
PARAMETER
VOFFSET/I
Analog Input Offset Voltage
ROUTA
Analog Output Resistance
IOUTA
Analog Output Current
MIN
0.25
VOFFSET/O Analog Output Offset Voltage
TYP
MAX UNITS
±1
±8
20
50
0.5
mV
NOTES
2
n
mA
-200
±850
mV
IINLOW
Logic Input Low Current (VIN = 0.8V)
Digital Input, Clock Input, Sync Input
±0.1
±10
JJ.A
3
IINHIGH
Logic Input High Current (V IN = 2.4V)
Digital Input, Clock Input, Sync Input
-0.25
-0.8
mA
3
Coo
Digital Output Capacitance
8
12
pF
±0.1
±10
p.A
0.4
V
4
IDOL
Digital Output Leakage Current
VOUTLOW
Logic Output Low Voltage
Digital Output, AlB Signal Out
VOUTHIGH
Logic Output High Voltage
Digital Output, AlB Signal Out
V
4
1+
Positive Supply Current
4
10
mA
5
1-
Negative Supply Current
2
6
mA
5
IREF+
Positive Reference Current
4
20
p.A
IREF_
Negative Reference Current
4
20
p.A
3.9
AC CHARACTERISTICS (Refer to Figure 12 and Figure 13)
SYM
PARAMETER
MIN
TYP
MAX UNITS
1.5
1.544
2.1
MHz
0.064
1.544
2.1
MHz
FM
Master Clock Frequency
FR, Fx
Receive, Transmit Clock Frequency
PWCLK
Clock Pulse Width (MASTER, XMIT, RCV.)
t RC
Clock Rise Time (MASTER, XMIT, RCV.)
25% of
PWCLK
ns
tRS,t FS
Sync Fall, Rise Time (XMIT, RCV.)
25% of
PWCLK
ns
tOIR' tOIF
Digital Input Rise, Fall Time
25% of
PWCLK
ns
200
twsx , t WSR Sync Pulse Width (XMIT, RCV.)
tps
Sync Pulse Period (XMIT, RCV.)
t xcs
XMIT Clock-to-XMIT Sync Delay
t XCSN
NOTES
ns
8
FxlFR)
p's
125
p.s
50%of
t FC (t RS )
ns
XMIT Clock-to-XMIT Sync (Negative Edg'e) Delay
200
ns
t xss
XMIT Sync Set-Up Time
250
ns
t xoo
XMIT Data Delay
0
200
ns
4
t xop
XMIT Data Present
0
200
ns
4
t XOT
XMIT Data Three State
150
ns
4
4
4
tOOF
Digital Output Fall Time
50
100
ns
tOOR
Digital Output Rise Time
50
100
ns
4-69
6
AC CHARACTERISTICS CONTINUED (Refer to Figure 12 and 13)
SYM
PARAMETER
t SRC
RCV. Sync-to-RCV. Clock Delay
TYP
MIN
MAX UNITS
NOTES
50% of
t RC (tFs)
ns
6
tROS
RCV. Data Set-Up Time
50
ns
7
t ROH
RCV. Data Hold Time
200
ns
7
t RCS
RCV. Clock-to-RCV. Sync Delay
200
ns
200
tRSS
RCV. Sync Set-Up Time
t SAO
RCV. Sync-to-Analog Output Delay
tA/BI
AlB Signalling Input Setup Time
tA/BSH
AlB Select Hold Time
200
tA/BSS
AlB Select Setup Time
400
tA/BO
AlB Signalling Output Delay
7
ns
7
/lS
200
ns
ns
ns
200
400
ns
SLEW+
Analog Output Positive Slew Rate
1
V//ls
SLEW-
Analog Output Negative Slew Rate
1
V//ls
DROOP
Analog Output Droop Rate
25
/lV//ls
SYSTEM CHARACTERISTICS (Refer to Figures 16 and 17)
SVM
PARAMETER
SID
Signal-to-Distortion Ratio
GT
Gain Tracking
MIN
TYP
35
29
24
39
34
29
-0.4
-0.8
-2.5
±C.1
±0.1
±0.2
N IC
Idle Channel Noise
10
TLP
Transmission Level Point
+4
MAX
UNITS
TESTCOND.
dB
dB
dB
Analog Input=O to -3OdBmO
Analog Input=-4OdBmO
Analog Input=-45dmO
+0.4
+0.8
+2.5
dB
dB
dB
Analog Input=-37 to -5OdBmO
Analog Input=-50 to -55dBmO
18
dBrncO
Analog Input 0 Volts
Note 2
dB
600n
Analog Input=+3 to -37dBmO
RECOMMENDED ANALOG INPUT CIRCUIT
Figure 11
COOEC
NOTES:
1.
+VREF and -VREF must be matched within ± 1% in order to meet system
requirements
2.
Sampling is accomplished by charging an internal capacitor; therefore. the
designer should avoid excessive source Impedance. Input related device
characteristics are derived using the Recommended Analog tnput Circuit.
4.
5.
6.
7.
C 1NA, RINAS
~"F
See Figure 11 .
3.
TYPICAL
SOURCE
When a transistion from a "1 ., to a "0" takes place, the user must sink the
"1" current until reaching the "0" level.
Driving 30pF with IOH = -1 OO~A. IOL = 500,uA.
Results in 30 mW typical power dissipation (clocks applied) under normal
operating conditions.
This delay is necessary to avoid overlapping CLOCK and SYNC.
The first bit of data is loaded when the Sync and Clockare both "1 ., during
bit time 1 as shown on RCV timing diagram.
~
:
I
4-70
~
TRANSMITTER
SECTION TIMING
Figure 12
PCM DATA PRESENT
NOTEt All
flse
and tall limes are measured 'rom 0 4V and 2.4V
AU dela" times areme.sured hom' .4V
RECEIVER SECTION TIMING
Figure 13
2.4V
1.4V
NOTE: AN ri. . . fall time. are m...ured hom O.4V and 2 ....V. All clefay tim. . .,.
manured from 1.4V.
4-71
64kHz OPERATION. TRANSMITTER SECTION TIMING
Figure 14
l
V
PCM DATA PRESENT
NOTE: All nse and fall times are measured from O.4V and 2.4V. All delay times are
measured from 1.4V
64kHz OPERATION. RECEIVER SECTION TIMING
Figure 15
~1·'---------
I
~
_________________________
125"~C
____________________________________~."'!
I
RCV SYNC
-1 I -
U
_I
~
PWCLK
~l,I~
CLOCK
U
~
' U
L
l
j4---tRDH
tRDS~~
NOTE: All rise and fall times are measured from O.4V 8fld 2.4V. All delay times are
measured from 1.4V
4-72
~ASTER
1_
~,LOCK
PERIODS
r-- IMINI
MK5151 GAIN TRACKING PERFORMANCE
MK5151 SID RATIO VS. INPUT LEVel
Figure 16
Figure 17
T
INPUT LEVEL IdBmO,
PACKAGE DESCRIPTIONS
Cerdip (J)
24-Pin
24-Pin
MK5151P
Side-Braze Ceramic (P)
MK5151J
4-73
4-74
M1{5156(J,N)
1\ LAW COMPANDING CODEC
COMMUNICATIONS PRODUCTS
FEATURES
D ±5-Volt power supplies
D Low power dissipation - 30 mW (Typ)
D Follows the A-Law companding code
ANALOG INPUT --+ 1
D Includes CCITT recommended even-order-bit inversion
1S~-VREF
v-
14
--+3
NC-4
D Synchronous or asynchronous operation
MASTER CLOCK ....... 5
XMIT SYNC - - . 6
XMIT CLOCK --+ 7
D On-Chip sample and hold
16 -+-+VREF
v+ --+- 2
DIGITAL OUTPUT ____ 8
~ANALOG
GROUND
13 --.ANALOG OUTPUT
12 ........OIGITAL INPUT
11 ...--DIGITAL GROUND
10 ...-RCV CLOCK
9
~RCVSYNC
D On-chip offset null circuit eliminates long-term drift
errors and need for trimming
D Minimal external circuitry required
D Serial data output of 64 kb/s through 2.1 Mb/s at a
kHz sampling rate
Figure 1. Pin Connections
D Separate analog and digital grounds reduce noise
problems
DESCRIPTION
The MK5156 is a monolithic CMOS companding
CODEC that contains two sections: (1) An analog-todigital converter with a transfer characteristic conforming to the A-law companding code and (2) a digital-toanalog converter that also conforms to the A-law code.
r-------I
I
~i
DIGITAL
TRUNK
ANALOG
These two sections form a coder-decoder designed to
meet the needs of the telcommunications industry for
per-channel voice-frequency CODECs used in digital
switching and transmission systems. Digital input and
output are in serial format. Actual transmission and
reception of a-bit data words containing the analog information is done at a 64 kb/s through 2.1 Mb/s rate with
analog signal sampling occuring at an a kHz rate. A
sync pulse input is provided for synchronizing transmission and reception of multi-channel information being
multiplexed over a single transmission line. A block
diagram of a PCM system using the MK5156 is shown
in Figure 2.
DIGITAL
TRUNK
Figure 2. PCM System Block Diagram
4·75
control signals required for all internal conversions. It
does not have to be synchronized with Rev SYNC, RCV
CLOCK, XMIT SYNC or XMIT CLOCK and is not internally related to them.
XM.IT SYNC
Input. Pin 6. This input is synchronized with XMIT
CLOCK. When XMIT SYNC goes high, the digital output is activated and the AID conversion begins on the
next positive edge of MASTER CLOCK. The conversion
by MASTER CLOCK can be asynchronous with XMIT
CLOCK. The serial output data is clocked out by the
positive edges of XMIT CLOCK. The negative edge of
XMIT SYNC causes the digital output to become threestate. XMIT SYNC must go low for at least one master
clock period prior to the transmission of the next digital word. (See Figure 12.)
XMIT CLOCK
Input. Pin 7. The on-chip B-bit output shift register of
the MK5156 is unloaded at the clock rate present on
this pin. Clock rates of 64 kHz-2.1 MHz can be used
for XMIT CLOCK. The positive edge of the INTERNAL
CLOCK transfers the data from the master to the slave
of a master-slave flip-flop. (See Figure 5.) If the positive edge of XMIT SYNC occurs after the positive edge
of XMIT CLOCK, XMIT SYNC wiUdetermine when the
first positive edge of internal clock will occur. In this
event, the hold time for the first clock pulse is measured from the positive edge of XMIT SYNC.
Figure 3. MK5156. Block Diagram
FUNCTIONAL DESCRIPTION
+VREF AND -VREF
Input. Pins 16 and 15. These positive and negative
reference voltages provide the conversion references
·for the digital-to-analog converters in the MK5156.
+VREF and -VREF must maintain 100 ppM/oC regulation over the operating temperature range. Variation of
the reference directly affects system gain.
ANALOG INPUT
Input. Pin 1. Voice-frequency analog signals that are
bandwidth-limited to 4 kHz are input at this pin. Typically, they are then sampled at an 8 kHz rate. (See Figure
4.) The analog input must remain between +VREF and
- VREF for accurate conversion. The recommended input interface circuit is shown in Figure 9.
MASTER CLOCK
Input. Pin 5. This signal provides the basic timing and
4-76
RCV SYNC
Input. Pin 9. This input is synchrqnized with Rev
CLOCK and serial data is clocked in by RCV CLOCK.
Duration of the RCV SYNC pulse is approximately B
Rev CLOCK periods. The conversion from digital-toanalog starts after the negative edge of the Rev SYNC
pulse. (See Figure 4.) The negative edge of Rev SYNC
should occur before the 9th positive clock edge to insure that only eight bits are clocked in. Rev SYNC must
stay low for 17 MASTER CLOCKS (min.) before the next
digital word. is to be received (See Figure 13).
RCV CLOCK
Input. Pin 10. The on-chip B-bit shift register for the
MK5156 is loaded at the clock rate present on this pin.
Clock rates of 64 kHz-2.1 MHz can be used for Rev
CLOCK. Valid data should be applied to the digital input before the positive edge of the internal clock. (See
Figure 5.) This set up time, t ROS ' allows the data to be
transferred into the master of a master-slave flip-flop.
The positive edge of the internal clOCk transfers the data
to the slave of the master-slave flip-flop. A hold time,
tRoH , is required to complete this transfer. If the rising
edge of Rev SYNC occurs after the first rising edge of
1"'..rf---------------125~sec-------------_3_~1
-
__---Jr
XMIT SYNC
r-
\\.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
I--- =15-20~sec ~
\1
SAMPLE AND HOLD
SAMPLE TIME
~--------------------------------------~
MASTER CLOCKS ~._________
.
_
______~
= 32
ENABLE SAR
SAR REQUIRES
=128 MASTER CLOCKS
----------------~/
RCV.SYNC
/
------------------------------------------~
ANALOG OUTPUT UPDATED
Figure 4. AID, D/A Conversion Timing
XMIT
INTERNAL
CLOCK
I.
200ns
I REQUIRED FOR DATA TO TRANSFER
...
I
DIGITAL
OUT
______________-Jx
---'
RCV
INTERNAL
CLOCK
MK5156
FROM MASTER TO SLAVE
200ns
:j Ik___.JX
XMITSYNC
VALID DATA
XMITCLOCK
REQUIRED TO TRANSFER DATA
' - FROM MASTER TO SLAVE
DIGITAL
IN
RCV SYNC
50ns REQUIRED TO LOAD MASTER
RCV CLOCK
INTERNAL CLOCK
VALID INCOMING DATA
Figure 5. Data Input/Output Timing
RCV CLOCK, RCV SYNC will determine when the first
positive edge of internal clock will occur. In this event,
the set-up and hold times for the first clock pulse should
be measured from the positive edge of RCV SYNC.
magnitude. In the first two Chords, the Step Bit has a
value of 1.2 mV. In the third Chord, the Step Bit has a
value of 2.4 mV. This doubling of the step value continues for each of the five successive Chords.
Each Chord has a specific value and the Step Bits, 16
in each Chord, specify the displacement from that value
(Refer to Table 1). Thus the output, which follows the
A-law, has resolution that is proportional to the input
level rather than to full scale. This provides the resolution of a 12-bit AID converter at low input levels and that
of a 6-bit converter as the input approaches full scale.
The transfer characteristic of the AID converter (A-law
Encoder) is shown in Figure 6.
DIGITAL OUTPUT
Output. Pin 8. The MK5156 output register stores the
S-bit encoded sample of the analog input. This S-bit
word is shifted out under control of XMIT SYNC and
XMIT CLOCK. When XMIT SYNC is low, the DIGITAL
OUTPUT is an open circuit. When XMIT SYNC is high,
the state of the DIGITAL OUTPUT is determined by the
value of the output bit in the serial shift register. The
output is composed of a Sign Bit, 3 Chord Bits, and 4
Step Bits. The Sign Bit indicates the polarity of the
analog input while the Chord and Step Bits indicate the
DIGITAL INPUT
Input. Pin 12. The MK5156 input register accepts the
4·77
8-bit sample of an analog value and loads it under control of RCV SYNC and RVC CLOCK. The timing diagram is shown in Figure 11. When RCV SYNC goes
high, the MK5156 uses RCV CLOCK to clock the serial
data into its input register. RCV SYNC goes low to indicate the end of serial input data. The eight bits of the
input data have the same functions described for the
DIGITAL OUTPUT. The transfer characteristic of the D/A
converter (A-law Decoder) is shown in Figure 7.
ANALOG OUTPUT
Output. Pin 13. The analog output is in the form of voltage steps (100% duty cycle) having amplitude equal
to the analog sample which was encoded. This waveform is then filtered with an external low-pass filter with
slnxlx correction to recreate the sampled voice signal.
OPERATION OF CODEC WITH 64kHz XMIT/RCV.
CLOCK FREQUENCIES
Thble 1. Digital Output Code: A Law
1.
2.
3.
4.
5.
6.
7.
8.
Chord Code
101
100
111
110
001
000
011
010
Chord Value
O.OmV
20.1mV
40.3mV
80.6mV
161.1mV
332mV
645mV
1.289V
XMIT/RCV SYNC must not be allowed to remain at a
logic "1" state. XMIT SYNC is required to be at a logic
"0" state for one master clock period (min.) before the
next digital word is transmitted. RCV SYNC is required
to be at a logic "0" state for 17 master clock periods
(min.) before the next digital word is received (See
Figures 12 and 13).
Step Value
1.221 mV
1.221mV
2.44mV
4.88mV
9.77mV
19.53mV
39.1mV
78.1mV
OFFSET NULL
The offset null feature of the MK5156 eliminates longterm drift errors and conversion errors due to temperature changes by going through an offset adjustment cycle before every conversion, thus guaranteeing accurate
AID conversion for inputs near ground. There is no offset adjust of the output amplifier because, since the output is intended to be AC-coupled to the external filter,
the resultant DC error (VOFFSET 0> will have no effect.
The sign bit is not used to null the analog input. Therefore, for an analog input of 0 volts, the sign bit will be
stable.
EXAMPLE:
1
110
0111 = +80.6mV +(2 x 4.88mV)
Sign Bit Chord
Step Bits
If the sign bit were a zero, then both plus signs would
be changed to minus signs.
.
10101010
10100101
10110101
1000 0101
10010101
11100101
11110101
In
!;
!;
0
~
~
11010101}~
01010101
PERFORMANCE EVALUATION
0100 0101
0111 0101
01100101
00010101
00000101
001' 0101
00100101
00101010
The equipment connections shown in Figure 8 can be
used to evaluate the performance of the MK5156. An
analog signal provided by the HP3552A Transmission
Test Set is connected to the Analog Input (Pin 1) of the
MK5156. The Digital Output of the CODEC is tied back
to the Digital Input and the Analog Output is fed through
a low-pass filter to the HP3552A. Remaining pins of the
MK5156 are connected as follows:
,y REF ,yREF
-2-
"-VREF -VR
F
_E
2
ANALOG INPUT ,VOLTSI
Figure 6. AID Converter (A-Law Encoder) ThIns1er
Charecterlatlc
+VREF
(1) RCV SYNC is tied to XMIT SYNC
(2) XMIT CLOCK is tied to MASTER CLOCK. The signal is inverted and tied to RCV CLOCK.
+Y..8ll
2
•
ANALOG OUTPUT
IVOLTS)
The following timing signals are required:
-!!!Ill
2
(1) MASTER CLOCK = 1.536 MHz
(2) XMIT SYNC repetition rate = 8 kHz
(3) XMIT SYNC width = 8 XMIT CLOCK periods
-VREF
~~~~~~~~1~~~~~~~~
00-8-0-8
8§ 88 § 5 56
8-0-~-00
When all the above requirements are met, the setup
of Figure 8 permits the measurement of synchronous
system performance over a wide range of analog inputs.
;: :: :: ~ !.:! g g g
~
DIGITAL INPUTS
Figure 7. D/A Converter (A-Law Decoder) lhlnsfer
Charecterlatlc
4-78
separated from XMIT CLOCK and MASTER CLOCK
should be separated from RCV CLOCK. XMIT CLOCK
and RCV CLOCK are separated also.
The data register and ideal decoder provide a means
of checking the encoder portion of the MK5156 independently of the decoder section. To test the system in the
asynchronous mode, MASTER CLOCK should be
r-
----
I
I
I
I
I
I
IH
1.020kHz
SIGNAL
SOURCE
l:.,m",
INPUT
I
I
DIGITAL
OUTPUT
J.r
DATA
REGISTER
I
IDEAL
DECODER
MK5156
1
ANALOG
INPUT
I
I
ANALOG
13
OUTPUT
SYSTEM
I
L -- N
_
OUT
1.020 kHz
NOTCH
FILTER
P3552A
l
I
FILTER
I
L -- ------ J
NOTE: The ideal decoder consists of a digital decompander and a 13-blt
pRlCislon DAC.
Figure 8. System Characteristics Test Configuration
4-79
""
\
odDER
ONLY
ABSOWTE MAXIMUM RATINGS·
DC Supply Voltage, V+ " ' , , " " " , " " " " " " " " " " " " " " " " " , " , ' , " " , , " " " , ' , +6V
DC Supply Voltage, V- " " " " " " " " " " " " " " " " " " " ' , ' , ' , " " ' , " " " " " " " ' " -6V
Ambient Operating Temperature, TA ' , , , ' , , , , , , , , ' , , , , ' , , , , , , , , , , , , , , , , , , , , , , , , , , ' , , , , ,OOC to lOoC
Storage Temperature " " " " " , ' , " " ' , " , " " , ' , " , " " , " " " " " " " " " ' " -55°C to +125°C
Package Dissipation at 25 OC (Derated 9mW/oC when soldered into PCB), , , , , , , , , , , , , , , , ' , , , , , , , ,500mW
Digital Input, , , , , , , , , ' , , , , , ' , , , , , , ' , , , , , , ' , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ' , ,-O,5V",V IN ",V+
Analog Input " " " " " " " " " , ' , " " , ' , " " ' , ' , " , " ' , ' , " " ' , , " " " " " " " " V- ",VIN ",V+
+VREF " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " -O,5V",+VREF ",V+
-VREF " , " " " , ' , ' , " ' , " , " " , , " " " , " " " , , " " " " " " " " " " " ' " ,V-",-VREF ",+O,5V
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ELECTRICAL OPERATING CHARACTERISTICS
POWER SUPPLY
SYM
PARAMETER
V+
MIN
TYP
MAX
UNITS
NOTES
Positive Supply Voltage
4,75
5,0
5,25
V
V-
Negative Supply Voltage
-5,25
-5,0
-4,75
V
+VREF
Positive Reference Voltage
2,375
2,5
2,625
V
1
-VREF
Negative Reference Voltage
-2,625
-2,5
-2,375
V
1
TEST CONDITIONS: V+ = 5,OV, VDC CHARACTERISTICS
-5,OV, + VREF = 2,5V, -VREF = -2,5V, TA = O°C to 70°C
SYM
PARAMETER
RINAS
Analog Input Resistance During Sampling
MIN
RINANS
TYP
UNITS
NOTES
2
MAX
k{)
2
Analog Input Resistance Non-Sampling
100
M{)
C INA
Analog Input Capacitance
150
250
pF
2
VOFFSETI/I
Analog Input Offset Voltage
±1
±8
mV
2
1
50
{)
ROUTA
Analog Output Resistance
IOUTA
Analog Output Current
VOFFSET/O
Analog Output Offset Voltage
±50
±850
mV
IINlOW
Logic Input Low Current (VIN = O,8V)
Digital Input, Clock Input, Sync Input
±O,1
±10
pA
3
IINHIGH
Logic Input High Current (VIN = 2AV)
Digital Input, Clock Input, Sync Input
-0,25
-0,8
rnA
3
CDO
Digital Output Capacitance
8
12
pF
IDOL
Digital Output Leakage Current
±O,1
±10
pA
VOUTlOW
Digital Output Low Voltage
OA
V
4
V
4
0,25
0,5
rnA
3,9
VOUTHIGH
Digital Output High Voltage
1+
Positive Supply Current
4
10
rnA
5
1-
Negative Supply Current
2
6
rnA
5
IREF+
Positive Reference Current
4
20
pA
IREF-
Negative Reference Current
4
20
pA
4-80
AC CHARACTERISTICS
SYM
PARAMETER
GTx
Gain Tracking
Transmit
CCITT G712 Method 2
GT R
Gain Tracking
Receive
CCITT G712 Method 2
Gain Tracking
End to End
CCITT G712 Method 2
MIN
-.2
-.4
-1.25
TYP
-.2
-.4
-1.25
0.0
±0.1
±0.2
-0.4
-0.8
-2.5
±0.1
±0.1
±0.2
0.0
±0.1
±0.2
MAX UNITS TEST CONDITIONS
dB
+.2
Analog Input = +3 to -40 dBmO
Analog Input = -40 to -50 dBmO
dB
+.4
dB
Analog Input = -50 to -55 dBmO
+1.25
Relative to -10 dBmO
dB
Input Level = +3 to -40 dBmO
+.2
dB
Input Level = -40 to -50 dBmO
+.4
dB
Input Level = -50 to -55 dBmO
+1.25
Relative to -10 dBmO
Signal to Distortion
Transmit
CCITT G712 Method 1
30
36
34
30
15
dB
dB
dB
dB
dB
SD1 R Signal to Distortion
Receive
CCITT G712 Method 1
30
37
35
31
16
dB
dB
dB
dB
dB
37
31
25
dB
dB
dB
Analog Input = +3 to -40dBmO
Analog Input = -40 to -50dBmO
Analog Input = -50 to -55dBmO
Relative to -10dBmO
Analog Input = -3 dBmO
Analog Input = -6 to -27 dBmO
Analog Input = -34 dBmO
Analog Input = -40 dBmO
Analog Input = -55 dBmO
Narrow Band Noise Input
Input Level = -3 dBmO
Input Level = -6 to -27 dBmO
Input Level = -34 dBmO
Input Level = -40 dBmO
Input Level = -55 dBmO
Narrow Band Noise Input
Analog Input = 0 to -30 dBmO
Analog Input = -40 dBmO
Analog Input = -45 dBmO
37
31
25
dB
dB
dB
Input Level
Input Level
Input Level
GT EE
SD1 x
SD2 x
Signal to Distortion
Transmit
CCITT G712 Method 2
SD2 R Signal to Distortion
Receive
CCITT G712 Method 2
SDEE Signal to Distortion
End to End
CCITT G712 Method 2
Idle Channel Noise
Nx
Transmit
Idle Channel Noise
NR
Receive
Idle Channel Noise
NEE
End to End
35
29
24
±0.4
+0.8
+2.5
Analog
Analog
Analog
Analog
=
=
=
Input
Input
Input
Input
0 to -30 dBmO
-40 dBmO
-45 dBmO
=
=
=
=
0 to -30dBmO
-40dBmO
-45dmO
0 Volts
-68
db
db
dB
dBmOp
-90
dBmOp Digital Input
=
+0 Code
-68
dBmOp Analog Input
=
0 Volts
39
34
29
-80
dB
dB
dB
CT RX
Crosstalk
Receive to Transmit
-80
dB
CTXR
Crosstalk
Transmit to Receive
Transmission Level Point
-80
dB
Analog In = -50 dBmO at 2600 Hz
Digital Input = 0 dBmO at
1008 Hz digital
Analog In = 0 dBmO at 1008 Hz
Digital Input = +0 Code
dB
600n
TLP
+4
4-81
NOTES:
1. -VREF and -VREF must be matched within ±1% in order to moot system
requirements.
2. Sampling is aooomplished by charging an internal capacitor; therefore, the
designer should avoid excessive oource impedanca. Input related _
characteristics are derived ueing the Recommended Analog Input ClrcuH.
See Figure 9.
3. When a transition from a "1" to a "0" takes place, the user must sink the
'~" current until reading the "0" lovel.
4. Driving 30pF with IOH = -100 pA, IOL -500 pA.
S. Results In 30 mW typical power dlsalpallon (clocks appllad) under normal
operating conditions.
6. This delay Is neccassary to allOld overlapping Clock and Sync.
7. Thislirst bH"of data Is loaded when Sync and Clock are both "1" during bH
time 1 as shown on RCV timing diagram.
CODEC
TYPICAL
C INA , RINAS
Figure 9, Recommended Analog Input Circuit
4-82
TIMING SPECIFICATIONS (Refer to Figures 10 and 11)
#
SYM
PARAMETER
1
FM
Master Clock Frequency
2
FR, Fx
XMIT, RCV. Clock Frequency
3
PWCLK
Clock Pulse Width (MASTER, XMIT, RCV)
4
t RC t FC
Clock Rise, Fall Time (MASTER, XMIT, RCV)
5
6
t RS ' t FS
tOIR ' tOIF
MIN
TYP
MAX
UNITS
1.5
2.048
2.1
MHz
0.064
2.048
2.1
MHz
200
ns
Sync Rise, Fall Time (XMIT, RCV)
Data Input Rise, Fall Time
7
twsx , t WSF Sync Pulse Width (XMIT, RCV)
8
tps
Sync Pulse Period (XMIT, RCV)
9
t xcs
XMIT Clock-to-XMIT Sync Delay
25% of
PWCLK
ns
25% of
PWCLK
ns
25% of
PWCLK
ns
8
FX(FR)
p,s
125
p,s
50% of
tFdtRS)
ns
10 t XCSN
XMIT Clock·to·XMIT Sync (Negative Edge) Delay
200
ns
11
XMIT Sync Set-Up Time
200
ns
t xss
NOTES
6
12 t xoo
XMIT Data Delay
0
200
ns
4
13 t xop
XMIT Data Present
0
200
ns
4
14 tXDT
XMIT Data Three State
150
ns
4
15 tOOF
Digital Output Fall Time
50
100
ns
4
16 tOOR
Digital Output Rise Time
50
100
ns
4
17 tSRC
RCV Sync-to-RCV Clock Delay
50% of
t RC (t FS )
ns
6
50
ns
7
7
18 t ROS
RCV Data Set-Up Time
19 tRDH
RCV Data Hold Time
200
ns
20 t RCS
RCV Clock-to-RCV Sync Delay
200
ns
21 t RSS
RCV Sync Set-Up Time
200
ns
22 t SAO
RCV Sync-to-Analog Output Delay
7
p,S
23 SLEW+
Analog Output Positive Slew Rate
1
V/p,S
24 SLEW-
Analog Output Negative Slew Rate
25 DROOP
Analog Output Droop Rate
4-83
1
V/p,S
25
p,V/p,S
7
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V.
Figure 10. li'ansmitter Section Timing
ANALOG OUTPUT
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay· times are measured from 1.4V.
Figure 11. Receiver Section Timing
4-84
r·______________________8____________________~·1
I XMIT SYNC
~
I r-
~
U
1~~
~ I+--- CLOCK
-I 1 PERIOD
(MIN)
V
PCM DATA PRESENT
NOTE: AU rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V.
Figure 12. 64kHz Operation, Transmitter Section Timing
8
~
~ASTER
CLOCK PERIODS
RCVSYNC
-+I
NOTE: All rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V.
Figure 13. 64kHz Operation, Receiver Section Timing
4-85
~(MIN)
50.0
45.0
40.0
m-
35.0
~
z
~
~
~
c-'
z
~
30.0
25.0
20.0
15.0
10.0
5.0
0.0
10
o
-10
-20
-30
INPUT LEVEL (dBmO)
-40
-50
-60
Figure 14. MK5156 Single-Ended Signal To Distortion
1.5
1.0
I
.5
m~
-
CJ
~
~
0.0
I
I-
~
~
,.~M~
-"" I r
I
-.5
-1.0
-1.5
10
o
-10
-20
-30
-40
INPUT LEVEL (dBmO)
Figure 15. MK5156 Single-Ended Gain lI'acking
4-86
-so
-60
PACKAGE
Cerdlp
H DESCRIPTION
16.PI
ermetlc (J)
n MK5156
PACKAGE D
Plastic Dual.1 ESCRIPTION
16.Pin MK515~·Lin. (N)
4-87
4-88
INTRODUCTION
A general trend towards the conversion of voice signals to digital information is currently occurring.
TDM PCM is the most popular form of digital transmission_
per word are transmitted in a serial bit stream at
1.544 Mbits/sec. Each voice channel is sampled at an
8kHz rate so this signal must be bandlimited to less
than 4kHz in order to prevent undesirable aliasing.
Today there are several important applications for
this TDM scheme:
1. A high speed digital data link between central
offices to pass many conversations over one pair
of wires.
2. The electronic connection of two different circuit
paths.
3. Concentrators
Figure 1 shows how a 1kHz input signal is sampled
every 125 !-,sec. At each of these sampling times, the
analog information is converted into an eight-bit
digital word that is later sent out in serial format at
the 1.544 Mbits/sec rate.
Traditionally this connection had been done by
electromechanical crossreed switches. Very low "on"
resistance, low crosstalk, and immunity from the
large ringing or transient voltages were required_ Since
the electromechanical technique was deemed to be of
lower reliability, an all electronic approach was
desired. Electronic cross point switches were designed
and built, but because the electrical requirements
mentioned above are extremely difficult to meet, the
results were not entirely satisfying_
The digital approach obviates the analog switch problem by first performing an A to D conversion, then
assigning a time slot for each voice channel. For the
D3 channel bank, 24 channels of digital data of 8 bits
Figure 2 shows how the 24 voice channels are time
division multiplexed onto one wire (for simplicity
only simplex operation is shown).
Channell analog information is first bandlimited to
less than 4kHz, then sampled and converted to a companded digital code. This 8 bit word is serially transmitted to a multiplexer where digital information
from all the other channels are assimalated. The final
bit stream of 1.544mbit/sec is sent to the demultiplexer where the appropriate alphanumeric channel is
connected to numeric channel. This control (selection) is done by the main computer or processor.
One may see that any numeric channel could be connected to any alphanumeric channel by means of a
different time slot assignment. This completes the
switching in a completely digital manner.
8kHz SAMPLING SYSTEM
Figure 1
4-89
24 CHANNEL MULTIPLEXING
Figure 2
DIGITAL
J"l.J1.J"1..I"L
~.
DIGITAL
.Jl...J"L-fl..J
•
·••
••
·•••
DIGITAL INFO
(n
~
1.544 Mb s
24~
~
A~--rnkl
J"1J"""LfLJ"L
FILTER
-1"L-.J1..J"L
•
•
•
•
•
•
X~
-Il...J"LrL-
For T1 carrier systems, the digital PCM information
might be transmitted between central offices. For
PBX applications, the PCM technique is used to allow
the switching to be done digitally. The .accuracy of
the subsequent D·A conversion preserves the voice
quality so that insertion loss is not a problem.
We selected the metal gate CMOS process for several
reasons. First it is extremely low power, which is of
great concern. Secondly, it allows for high-quality,
matched capacitors in a minimum of chip size. Critical analog circuit design is done well in CMOS: for
example, high gain amplifiers and comparators. Also,
the metal gate CMOS process is one that is well
proven in high volume production.
By using the CMOS process, only two supplies are
necessary, plus and minus five volts. To minimize
power, all the digital logic is run from the plus 5V
supply to ground, and only the analog section operates from ± 5 volts.
CHIP ARCHITECTURE
Figure 3 shows the block diagram representation of
the CODEC chip. The important features of the
scheme used are listed below:
1. Two independent DAC's for encode and decode
functions provide system isolation not achievable
using shared DAC approach. The capacitive two
DAC approach also eliminates external sample/
hold capacitors as well as an external. filter for offset
which is required in the shared DAC approach. This
minimizes the external components required.
2. Complete signalling compatibility with D3 channel bank requirements.
3. Since the companding law is implemented uSing .8
to 13 bit converter, the DAC is a linear DAC thus
minimizing the number of analog components to
only the minimum required for system implemen·
tation, namely two: one comparator and only one
op-amp on the entire chip. Minimizing the linear
4-90
CODECBLOCK DIAGRAM
Figure 3
A SIG _
IN
B SIG
IN
_.1-------.,
.-----------+- ~~;~~~
--.jr-------,
XMIT
SYNC
XMIT
CLOCK
ANALOG_~~_____~fINPUT
______+-____~~~~
AlB SEL
(XMITI
MASTER
CLOCK
AI B SEL
IReV)
O'G'TAL_~4-{~~~J
INPUT
RCV
SYNC
RCV
nOCK
SECTION
B SIG A SIG
OUT OUT
components helps reduce system operating power
which was the overriding consideration in chip design_ Using the CMOS process, the digital portions
dissipate power only during transitions_ The linear
sections consume power continuously_
4_ The digital companding section allows easy conversion from mu-Iaw to A-law. The CODEC allows
data input/output rates from 64kHz to 2.1 MHz.
5. Asynchronous or synchronous operation.
MODES OF OPERATION
The XMIT and Receive function are completely independent of each other and of the master clock. Thus
the chip can operate in synchronous/asynchronous
mode at various input/output clock rates. The chip
timing diagram is shown in Figure 4 and the Receive
and XM IT modes of operation are described in detail
below:
(a) Receive Mode of Operation
In the receive mode of operation, the serial input
data is shifted into the input buffer at the receive
clock rate during the period receive sync. is high.
4·91
The encode process is halted after the falling edge
of receive sync pulse) for about 5 to 7 MS, and the
translated data from 8 to 13 bit converter is latched
into the 13 bit receive latch which updates the
output of the receive DAC with 100% duty cycle. The
receive DAC acts as a sample and hold and is
buffered by the unity gain op amp to the output.
During the signalling frame a 7 bit decode is per·
formed and the 8th data bit is latched into the
SigA/SigB output latch as selected by the A/B Select (RCV) input. When the eight bit of a word is
a signalling bit, it is assigned the value of 12 step.
This results in a lower SID ratio than if it were
arbitrarily set to either a one or zero.
(b) Transmit Mode of Operation:
I n this mode of operation the analog signal is
sampled in the input sample/hold which performs
the offset-null function simultaneously as described
in the circuit operation section. Following the hold
mode. the encoding process is completed using
successive approximation technique. The operation
-of the XMIT DAC is similar to the operation of the
receive DAC as described earlier. After the encode
AID AND DIA CONVERSION TIMING
Figure 4
""\_..--------125·,------+1-1n
n
XMITSYC
~r----~-t.~_::::~TR~A~N~S~M~IT~P~RE~V~IO~U~S~SA:M:P:L:E____----r-------~
L ___________
I..
RCVSYNC
RECEIVE NEXT SAMPLE
_____________________
t
~:-___:
I
UPDATE OUTPUT L ___________________________
ANALOG
----17., ~
process is completed. the output of the SAR is
loaded into the output buffer. The data is transmitted serially at the output clock rate during the
period the XMIT SYNC is high. During the signalling
frame. signalling information (SigA/SigB) is inserted into the output bit stream in place of the 8th
data bit as selected by the A/B select (SMIT) input.
CIRCUIT DESCRIPTION
The system timing is controlled by the sequence controller which operates at master clock rate of 1.5 - 2.1
MHz. All necessary signals. e.g. and S&H. SAR clock
Encode/Decode control~ etc; are generated in this
section. To insure proper encode operation. decode
interrupt is allowed only when the internal SAR clock is
CAPACITOR LADDER
Figure 6
4-92
low thus resulting in a variable (5-7 I's) decode interrupt
interval.
The 8 to 13 bit converter gives a one-to-one translation between 8 bit companded code at its input to a
13 bit linear code at its output thus allowing the use
of a linear OAC in the digital-to-analog conversion
process.
The 13-bit linear OAC operates on the charge distribution principal of a binary weighted capacitor
ladder.
As shown in Figure 5. the capacitor ladder has two
sections of 7 bits (7 most significant bits) and 6 bits
(6 least significant bits) connected by a 64: 1 capacitor divider. The equivalent circuit of the two sections
can be drawn as shown in Figure 6.
CAPACITOR LADDER EQUIVALENT CIRCUIT
•
DAC OUTPUT
Then switch S2 is opened and S1 is switched to analog ground. The voltage at the inverting input of the
op-amp is now Voff-V lr . Thus when the amplifier
operates with S2 open it ;;~ts as a comparator with
effectively zero offset ,',~d -Vin applied on its
inverting input. The othrc' end of the capacitor can
now be operated as a OA', Thus the capacitor ladder
performs all the necessa·''1 functions of offset-null
sample-hold as well as cc DAC in the encode section of
the chip,
7
~
n=
WHERE
1
WnCnV r
127
Wn = 0 or 1 for the n th bit
Cn
=
n th bit capacitor
Vr -' Reference Voltage j+Vret or
Vrf!f~
The output of the OAC can be written as:
VOAC =
~
128
[
7
L
Initially S1 is connected to Vin and S2 is closed. The
op. amp. is operating as a unity gain follower and its
offset voltage (Voff). along with the analog input voltage •
is stored on the capacitor.
EXPERIMENTAL RESULTS
Wn Cn +
n=1
13
]
Wn (C n/64)
L
n=8
which is equivalent to the output of a 13 bit OAC
with an equivalent output capacitance of 128pF.
The set up of Figure 8 was used to evaluate the chip
performance.
CHIP PERFORMANCE
Figure 8
Unit
In the encode section this equivalent capacitor of
128pF is also employed to perform the additional
function of offset-null and sample-hold as shown in
Figure 7.
OFFSET NULL/SAMPLE HOLD
F~re7
II'
Unit #2
XMIT 1
XMIT 2
Rev 1
Rev 2
The MK5151 CODEC performance exceeds the AT&
T 03 channel bank specifications. Figure 9 shows the
signal-to-quantizing distortion as a function of input
level.
b
""l~~
Idle channel noise of 13-14dBrnCO is better than the
03 spec by 9-10dB. Gain tracking is shown in Figure
10.
SIGNAL-TO-NOISE RATIO
Figure 9
42
42
40
30
20
15
10
-'0
,20
30
INPUT LEVel (demO)
4·93
-40
-45
-so
-60
GAIN TRACKING
Figure 10
o
c
°.05
05
-10
-20
-30
-01
-01
-01
-40
-so
-55
-60
-015
r"''' .. ", ::::"~;;:,;~: "" ", ~
01
~'"
-2
tl
-3
Operating power measured at room temperature typically is 30mW. This is low enough that a stand-by
mode is not deemed necessary. The European A-law
4-94
version of the CODEC is also available and is simply a
metal mask variation of this product_ Chip size is 170
x 184 mils.
ETC5040-ETC5040A
-----~~-
PCM MONOLITHIC FILTER
COMMUNICATIONS PRODUCTS
I
PCM MONOLITHIC FILTER
CMOS
The ETC5040/ETC5040A filter is a monolithic circuit containing both
transmit and receive filters specifically designed for PCM COOEC
filtering applications in 8 kHz sampled systems.
PCM
MONOLITHIC FILTER
The filter is manufactured using double-poly silicon gate CMOS
technology. Switched capacitor integrators are used to simulate
classical LC ladder filters which exhibit low component sensitivity.
CASE
TRANSMIT FILTER STAGE
~
The transmit filter is fifth order elliptic low pass filter in series
with a fourth order Chebychev high pass filter. It provides a flat
response in the passband and rejection of signals below 200 Hz
and above 3.4 kHz.
~GN~!U'
1
RECEIVE FILTER STAGE
J SUFFIX
The receive filter is a fifth order elliptic low pass filter designed to
reconstruct the voice signal from the decoded/demultiplexed signal
which, as a result of the sampling process, is a stair-step signal
having the inherent sin x/x frequency response. The receive filter
approximates the function required to compensate for the degraded
frequency response and restore the flat pass-band response.
CERDIP PACKAGE
• Exceeds all 03/04 and CCITI specifications
• + 5V, -5V power supplies
PIN ASSIGNMENT
• Low power consumption:
45 mW (600 0-0 dBm load)
30 mW (power amps disabled)
• Power down mode: 0.5 mW
• 20 dB gain adjust range
• No external anti-aliasing components
• Sin x/x correction in receive filter
• 50/60 Hz rejection in transmit filter
• TIL and CMOS compatible logic
• All inputs protected against static discharge due to handling
4-95
VFxl+
VF,O
VFx l-
GNOA
GSx
ClKO
VFRO
PDN
PWRI
ClK
PWRO+
GNDD
PWRO-
VFRI
VBB
VCC
BLOCK DIAGRAM
GS,
VFxl+
elK
1-------I
I
I
PWRI
r---~--,
Vee
FIGURE 1
4-96
VBB
GNDD
GNDA
PDN
PIN DESCRIPTION
Pin
Type
N'
VFxl+
I
1
The non-inverting input to the transmit filter stage
VFx l-
I
2
The inverting input to the transmit filter stage
Name
Description
GS x
0
3
The output used for gain adjustments of the transmit filter
VFRO
0
4
The low power receive filter output. This pin can directly drive
the receive port of an electronic hybrid.
PWRI
I
5
The input to the receive filter differential power amplifier.
PWRO+
0
6
The non-inverting output of the receive filter power amplifier.
This output can directly interface conventional transformer hybrids.
PWRO-
0
7
The inverting output of the receive filter power amplifier.
This output can be used with PWRO+ to differentially drive
a transformer hybrid.
VBB
S
8
The negative power supply pin. Recommended input is -5 V.
VCC
S
9
The positive power supply pin. The recommended input is 5 V.
VFRI
I
10
The input pin for the receive filter stage.
GND
11
Digital ground input pin. All digital signals are referenced to this pin.
CLK
I
12
Master input clock. Input frequency can be selected as 2.048 MHz,
1.544 MHz or 1.536 MHz.
PDN
I
13
The input pin used to power down the ETC5040jETC5040A during
idle periods. Logic 1 (VCC) input voltage causes a power down
condition. An internal pull-up is provided.
CLKO
I
14
This input pin selects internal counters in accordance with the ClK
input clock frequency:
CLK
Connect CLKO to:
2048 kHz
VCC
1544 kHz
GNDD
1536 kHz
VBB
An internal pull-up is provided.
GNDA
GND
15
Analog ground input pin. All analog signals are referenced to
this pin. Not internally connected to GNDD.
VFxO
0
16
The output of the transmit filter stage.
GNDD
4·97
'-
MAXIMUM RATINGS
Symbol
Value
Unit
Supply voltage
Rating
VCC
V
Input voltage
Operating temperature range
Vin
TA
±7
±7
-25°C to +125 °c
°c
Storage temperature
T stg
-65°C to + 150°C
°c
Po
llpackage
W
Power dissipation
Output short-circuit duration
continuous
Lead temperature
300
V
°c
DC ELECTRICAL CHARACTERISTICS
T A = ooe to + 70 oe, Vee = 5.0V ± 5%, Vss = - 5.0V ± 5%, clock frequency is 2.048 MHz
Typical parameters are specified at TA = + 25°e, Vee = 5.0V, Vss = - 5.0 V (Unless otherwise specified)
Digital interface voltages measured with respect to digital ground, GNDD. Analog voltages measured with
respect to analog ground. GNDA.
POWER DISSIPATION
Symbol
Min
Typ
Max
Unit
VCC standby current (pON = VOO. power down mode)
ICCO
-
50
100
~A
VBB standby current (PDN - VOD, power down model
IBBO
-
-50
-100
~A
Vee operating current (pWRI = VSS, power amp inactive)
ICCI
3.0
4.0
rnA
VBB operating current (PWRI = VSS. power amp inactive)
IBBl
-3.0
-4.0
rnA
Vee operating current (Note 1)
ICC2
4.6
6.4
rnA
V BS operating current (Note 1)
IBB2
-
-4.6
-6.4
rnA
Characteristic
DIGITAL INTERFACE
Symbol
Min
Typ
Max
Unit
I nput current, ClK (0 V '" VIN '" VCC)
IINC
-10
-
10
~A
Input current. PON (0 V '" VIN '" VCC-2 V)
IINP
-100
-
-
~A
Input current. ClKO (VBB '" VIN '" VCC-2 V)
IINO
-10
-0.1
~A
Input low voltage. ClK. PON
Vil
0
0.8
V
Input high voltage. ClK. PON
VIH
2.2
VCC
V
Input low voltage, CLKO
VllO
VBB
Input intermediate voltage, ClKO
VIIO
-0.8
Input high voltage. ClKO
VIHO
VCC-0.5
-
Characteristic
TRANSMIT INPUT AMP OP
Characteristic
VBB+0.5
V
0.8
V
VCC
V
Unit
Symbol
Min
Typ
Max
Input leakage current. VFxl (VBB '" VFxl '" VCC)
IBxl
-100
100
nA
Input resistance VFxl (VBB '" VFxl '" VCC)
Rlxl
10
-
MO
20
mV
VOSxl
-20
VCM
-2.5
Common-mode rejection ratio (-2.SV ::;;;; VIN :::£ 2.S"V)
CMRR
60
Power supply rejection of Vee or VBB
PSRR
60
-
ROl
-
1
Minimum load resistance, GS x
Rl
10
Maximum load capacitance, GS x
Cl
-
-
Output voltage swing. GS x (Rl '" 1 0 kOI
VOxl
± 2.5
-
Open loop voltage gain. GS x (RI '" 1 0 kO)
AVOl
5,000
FC
-
Input offset voltage. VFxl (-2.5 V '" VIN '" +2.5 VI
Common-mode range. VFxl
Open loop output resistance GS x
Open loop unity gain bandwidth, GS x
4·98
2.5
V
-
dB
dB
-
kO
kO
100
pF
-
-
V/V
2
-
MHz
V
AC ELECTRICAL CHARACTERISTICS
T A = + 25° C. All parameters are specified for a signal level of 0 dBmO at 1 kHz. The 0 dBmO level is assumed to be 1.54 Vrms measured at the output of the transmit or receive filter. (Unless otherwise specified).
TRANSMIT FILTER (Note 2)
Symbol
Characteristic
Minimum load resistance
-2.5 V
- 3.2 V
< V out <+ 2.5 V
< V out < + 3.2 V
Typ
Max
3
-
-
Output resistance. VFxO
100
1
3
VCC power supply rejection VF x llf=l kHz, VFxl+
= 0 Vrms)
Q
-
dB
VBB power supply rejection, VFxO. ISame as above)
Absolute gain If = 1 kHz)
-
PSRRl
30
PSRR2
35
-
2.9
2.875
3.0
3.0
3.1
3.125
-
-
-35
-35
-30
0
0.05
0.125
0.15
0.03
0.125
-0.1
-14
-32
GR x
Gain relative to GAx
Below 50 Hz
50 Hz
60 Hz
200 Hz
ETC5040A
ETC5040
ETC5040A
ETC5040
ETC5040A
ETC5040
300 Hz to 3 kHz
3.3 kHz
3.4 kHz
4.0 kHz
4.6 kHz and above
Absolute delay at 1 kHz
DAx
Differential envelope delay from 1 kHz to 2.6 kHz
Single frequency distortion products
DPx '
DPx2
Distortion at maximum signal level
= 20 dB,
RL
= 10 kQ
Total C message noise at VFxO
NC x l
Total C message noise at VFxO
NC x2
Gain setting Op Amp at 20 dB. non inverting, note 3, O"C';; T A';;
+ 70"C
Temperature coefficient of 1 kHz gain
GAxT
Supply voltage coefficient of 1 kHz gain
GAxS
Crosstalk, receive to transmit 20 log VFxO
CTRX
Receive filter output = 2.2 Vrms,
VFRO
VFxl+ = 0 Vrms, f= 0.2 kHz to 3.4 kHz, measure VFxO
Gaintracking relative to GAx
4-99
dB
dB
-41
-35
-1,5
-1.5
-0.125
-0.15
-0.35
-0.35
-0.70
-
-
-15
-
-
-
-
230
~s
60
~s
-
-48
dB
-
-
-45
2
5
-
3
6
dB
dBrncO
dBrncO
0.0004
-
dBfoC
0.01
-
dBN
dB
-
-
-70
-0.1
-0.05
-0.1
-
0.1
0.05
0.1
dB
GRxL
Output level = + 3 dBmO
+ 2 dBmO to - 40 dBmO
- 40 dBmO to - 55 dBmO
pF
dB
GAx
ETC5040A
ETC5040
Unit
kQ
10
CLx
Load capacitance, VFxO
1.6 Vrms, 1kHz signal applied to VFxl+, gain
Min
RLx
-
-
AC ELECTRICAL CHARACTERISTICS (Continued)
T A ~ + 25° C. All parameters are specified for a signal level of 0 dBmO at 1 kHz. The 0 dBmO level is assumed to be 1.54 Vrms measured at the output of the transmit or receive filter. (Unless otherwise specified).
RECEIVE FILTER (Unless otherwise noted, the receive filter is preceded by a sin x/x filter within an input
signal level of 1.54 Vrms).
Symbol
Min
Typ
Max
Input leakage current. VFRI (-3.2 V :i: VIN :i: 3.2 VI
IBR
-100
-
100
nA
Input resistance; VFRI
RIR
10
-
-
MO
Output resistance, VFRO
ROR
-
0
CLR
-
1
-
3
Load capacitance, VFRO
100
pF
RLR
10
-
-
kO
35
-
- 200
-
+ 200
-0.1
-0.125
0
0
0.1
0.125
-
-
0.125
Characteristic
Load resistance, VFRO
Power supply rejection 01 VCC or VBB (VFRO
VFRI connected to GNDA, 1 ~ 1 kHz)
PSRR3
Output DC offset, VFRO (VFRI connected to GNDA)
VOSRO
Absolute gain (f - 1 kHzl
dB
Gain relative to gain at 1 kHz below 300 Hz
300 Hz to 3.0 kHz
3.3 kHz
3.4 kHz
4.0 kHz
4.6 kHz and above
GRR
ETC5040A
ETC5040A
mV
dB
GAR
ETC5040A
ETC5040
Unit
-0.125
0.35
-0.70
=-
-
-
-
Absolute delay at 1 kHz
DAR
-
Differential envelope delay 1 kHz to 2.6 kHz
DDR
Single frequency distortion products ( f = 1 kHz)
DPRl
-
-
Distortion at maximum signal level
2.2 Vrms input to sin x/x filter, f = 1 kHz, RL = 10 kO
DPR2
-
-
dB
0.125
0.03
-0.1
-14
- 32
100
~s
100
~s
-48
dB
dB
-45
5
dBrneO
GART
-
3
Temperature coefficient of 1 kHz gain
0.0004
dB/oC
Supply voltage coefficient of 1 kHz gain
GARS
-
0.01
-
Crosstalk, transmit to receive 20 log
CTXR
Total C-message noise at VFRO
NCR
VFRO
VFxO
(Transmit filter output ~ 2.2 Vrms,
VF R I ~ 0 Vrms, f ~ 0.3 kHz to 3.4 kHz, measure VF RO)
Gaintraking relative to GAR
dB
-
-80
-70
-0.1
-0.05
-0.1
-
0.1
0.05
0.1
dB
GRRL
Output level ~ 3 dBmO
+ 2 dBmO to - 40 dBmO
- 40 dBmO to 55 dBmO
4·100
dBN
AC ELECTRICAL CHARACTERISTICS (Continued)
RECEIVE OUTPUT POWER AMPLIFIER
Symbol
Min
Typ
Max
Input leakage current, PWRI (-3.2 V S VIN S 3.2 V )
IBP
0.1
3
~A
Input resistance, PWRI
RIP
10
-
MO
Characteristic
Output resistance, PWRO+, PWRO - (amplifiers active)
1
-
CLP
-
-
500
pF
= 600 0
Gain, PWRI to PWROPWRO + and PWRO -, input, level
GAp+
-
1
-
V/V
-
-1
-
connected between)
-0.1
-0.1
-
01
0.1
-
-
-45
-45
=0 dBmO (Note 4)
GRpL
Signal/distortion
V = 2.05 Vrms, RL
V 1.75 Vrms, RL
SlOp
=
=
=
0
GAp-
Gaintraking relative to OdBmO output level
V 2.05 Vrms, R L 600 n (Notes 4, 5)
V 1.75 Vrms, R L 300 n (Notes 4, 5)
=
=
-
ROP1
Load capacitance, PWRO+, PWROGain, PWRI to PWRO+ ( RL
=600 n (Notes 4,5)
=300n (Notes 4,5)
Unit
V/V
dB
dB
Output DC offset. PWRO+, PWRD- ( PWRI connected to GNOA)
VOSP
-50
Power supply rejection of VCC or VBB (PWRI connected to GNOA)
PSRR5
45
-
50
mV
-
dB
Note 1. Maximum power consumption d.epend on ~he load impedance connected to the power amplifier. The specification listed
assumes 0 dBm is delivered to 600 0 connected from PWRO+ PWRO
Note 2. Transmit filter input op amp set to the non inverting unity gain mode, with VFxl+ = 1.1 Vrms, unless otherwise noted
Note 3, The 0 dBmO level for the filter is assumed to be 1.54 Vrms measured at the output of the XMT or RCV filter
Note 4. The 0 dBmO level for the power amplifiers is load dependent, For RL = - 600 n to GNDA, the 0 dBmO level is
1,43 Vrms measured at the amplifier output. For R L = 300 n the 0 dBmO level is 1,22 Vrms.
Note 5, VFRO connected to PWRI, input signal applied to VFRI
TYPICAL PERFORMANCE CHARACTERISTICS
TRANSMIT FILTER STAGE
RECEIVE FILTER STAGE
10
1 0 ;---r---rT'T'TTI"rr----r-r'TT'TTI"
o
i
~
~
-10
-20
t-/-,t-+t+++++t-~H-t+t+lj
I
ii
-10
w
-20
~
Q
::;)
-30
-40
5
-50
C
Il.
::E
-60
-70
L---I.........L..I..L.U.l.L..--.l.....J...J...J.J..U.IJ
IIIIII i '
Fil TER • SIN XIX JSIN
-30
IFI l TER
Yr
Lx
-40
-50
-60
0.1
II IIIL-l-
0
X~
.,
-
IBO~O
-70
10
0.1
FREQUENCY (kHz)
10
FREQUENCY (kHz)
4·101
SLiC
r-------------, -:I
TRANSFORMER
I I
:
~ ,:"VFXI+
IL
13
.
16
0.1 ~F
VFxOH
I
,
.1
Ox
VFx
~
PCM
.
OUT
I
I
I
I
I
I
...
i"
0
I\)
."
Q
c
:til
m
N
I
I
I
I
~I
GNDA I
ETC5040/ETC5040A
PON
13
-:GNOA
CODEC
8
n
II
VFRI
I
IL ____________ -.JI
PCM
IN
0
4
;;'
c Z
;:;' ....
..... m
~ ~
8li;
C m
m
n
Notel: Transmit voltage gain = Rl + R2
Note 2 : Receive gain = __R_4__ R2
R3
(R3 + R4 :;;; 10 kO)
x 12 (The filter itself introduces a 3 dB gain) (Rl
+ R2:;;;
10 kO)
+ R4
Note 3 : In the configuration shown. the receive filter power amplifiers will drive a 600 0 T to R termination to a signal level of 8,5 dBm.
An alternative arrangement using a transformer winding ratio equivalent to 1.414.1 and 300 Q resistor RS. will provide a maximum signal
level of 10 dBm across 600 0 termination impedance.
FUNCTIONAL DESCRIPTION
The ETC 5040/ETC 5040A monolithic filter contains
four main sections; Transmit Filter, Receive Filter,
Receive Filter Power Amplifier, and Frequency
Divider/Select Logic (figure 1). A brief description of the
circuit operation for each section is provided below.
Power down control
A power down mode is also provided. A logic, 1 power
down command applied on the PDN pin (pin 13) will
reduce the total filter power consumption to less than 1
mW and turn the power amplifier outputs into high
impedance state.
Transmit Filter
Frequency divider and select logic circuit
The input stage of the transmit filter is a CMOS
operational amplifier which provides an input resistance
greater than 10 M!l, a voltage gain of greater than
10.000, low power consumption (less than 3 mW), high
power supply rejection, and is capable of driving a 10 kO
load parallel with up to 25 pF. The inputs and output of
the amplifier are accessible for added flexibility. Noninverting mode, inverting mode, or differential amplifier
mode operation can be implemented with external
resistors. It can also be connected to provide a gain of up
to 20 dB without degrading the overall filter performance.
This circuit divides the external clock frequency down to
the switching frequency of the low pass switched
capacitor filters. The divider also contains a TTL-CMOS
interface circuit which converts the external TTL clock
level to the CMOS logic level required for the divider
logic. This interface circuit can also be directly driven by
CMOS logic.
The input stage is followed by a prefilter which is a twopole RC active low pass filter designed to attenuate high
frequency noise before the input signal enters the
switched-capacitor high pass and low pass filters.
A high pass filter is provided to reject 200 Hz or lower
noise which may exist in the signal path. The low pass
portion of the switched-capacitor filter provides
stopband attenuation which exceeds the D3 and D4
specifications as well as the CCITT G712 recommendations.
The output of the transmit filter, the postfilter, is also a
two-pole RC active low pass filter which attenuates
clock frequency noise by at least 40 dB. The output of
the transmit filter is capable of driving a ± 3.2 V peak to
peak signal into a 10 kO load in pa~allel with up to 25 pF.
Receive filter
The input stage of the receive filter is a prefilter which is
similar to the transmit prefilter. The prefilter attenuates
high frequency noise that may be present on the receive
input signal. A switched capacitor low pass filter follows
the prefilter to provide the necessary passband flatness,
stopband rejection and sin x/x gain correction. A
postfilter which is similar to the transmit postfilter
follows the low pass stage. It attenuates clock frequency
noise and provides a low output impedance capable of
directly driving an electronic subscriber-line-interface
circuit.
Receive filter power amplifiers
Two power amplifiers are also provided to interface to
transformer coupled line circuits. These two amplifiers
are driven by th~ output of the receive postfilter through
gain setting reolstors, R3, R4 (figure 2). The power
amplifiers can be deactivated, when not required, by
connecting the power amplifier input (pin 5) to the
negative power supply VBB. This reduces the total filter
power consumption by approximately 10 mW-20 mW
depending on output signal amplitude.
A frequency select circuit is provided to allow thefilterto
operate with 2.048 MHz, 1.544 MHz or 1.536 MHz
clock frequen-cies. By connecting the frequency select
pin CLKO (pin 14) to VCC, a 2.048 MHz clock input
frequency is selected. Digital ground selects 1 .544 MHz
and VBB selects 1.536 MHz.
APPLICATIONS INFORMATION
Gain adjust
Figure 2 shows the signal path interconnections
between the ETC5040/ETC5040A and single-channel"
CODEC. The transmit RC coupling components have
been chosen both for minimum passband droop and to
present the correct impedance to the CODEC during
sampling.
Optimum noise and distortion performance will be
obtained from the ETC5040/ETC5040A filter when
operated with system peak overload voltages of± 2.5 V
to ± 3.2 V at VFxO and VFRO. When interfacing to a
PCM CODEC with a peak overload voltage outside this
range, further gain or attenuation may be required.
For example, the ETC5040/ETC5040A filter can be
used with CODEC which has a 5.5 V peak overload
voltage. A gain stage following the transmit filter output
and an attenuation stage following the CODEC output
are required.
Board layout
Care must be taken in PCB layout to minimize power
supply and ground noise. Analog ground (GNDA) of
each filter should be connected to digital ground
(GNDD) at a single point, which should be bypassed to
both power supplies.
Further power supply decoupling adjacent to each filter
and CODEC is recommended. Ground loops should be
avoided, both between the GNDA traces of adjacent
filters and CODECs.
4-103
~
l~~U~"
1
J SUFFIX
CERDIP PACKAGE
.
O,NO-O.J2G
t--
]-1""'-"'" !
""
...
('i51'2'i
(OtDJ-OJD5)
_II Q,310~Q.l0
(78U-l0_1j
L
1-
6.1l1li
iIT32i
I
I,
II
I
M"~ I -
~~!~
II
-~
! ,:':~~!:':I~i-0100'0010
r--~
4·104
------~~-
T087711-T087722
SUBSCRIBER LINE INTERFACE CIRCUIT (SLlC)
COMMUNICATIONS PRODUCTS
This kit of two circuits is designed to ensure the BORSHTfunctionsofthe
central office line card.
•
Battery:
- Normal and reverse mode.
- Power down mode.
- Power denial.
•
Overvoltage:
- Voltage and current limitation.
•
Ringing:
- Ringing is externally injected.
- Ring trip is internally detected.
•
•
SUBSCRIBER LINE INTERFACE
CIRCUIT (SLlC)
CASES
CB 501
Signaling:
- Off-Hook detection.
- Ground key detection.
- Dialing detection.
Hybrid:
2 to 4·wire conversion.
-
• Test:
- External.
•
Complementary functions:
- Power saving.
- Tax metering signal sending.
- Automatic reset at power-up.
CB 132
~
~l:l'·
28
... "
,.
1
4-105
..
RING GEN.
c2:J
V BAT BG
Vee
AG
AG
CF
TTX
FILTER
Vci;
VEE
-+-4
1-1
III
5n
~
...
o
i"
.):
i
G)
I
HOOK
lON/OFF
TEST
LINE
RING
IDECAOIC
]
RELAY
110IALLING
RING TRIP
IGROUNO
11 KEY
D
,
:D
TOIFROM
COFIOEC
.I
_""BUS
~
I:
FUNCTIONAL DESCRIPTION
• Battery:
• Ringing:
- Programmable current limit.
- Apparent battery indepandent of actual battery.
- Programmable feeding resistor (ext. comp.).
- Max. battery voltage is 72 V.
- Power saving possibilities.
- In power down mode, power dissipation is 70 mW
(VBAT = 48 V).
- In power denial, line feeding disabled. Line is in
high impedance position.
-
Large AC and DC voltages allowed.
Perturbation free detection system.
• Hybrid:
- Synthesized impedence externally programmable
(complex impedance possible).
- 8alance impedance externally programmable
(complex impedance is possible).
•
• Overvoltage: power dissipation is maintained inside
S.O.A. of output devices. Thermal warning.
Complementary functions:
-
Power saving by comparison of battery voltage
and line voltage and connection of a reduced
voltage battery.
EXTERNAL COMPONENTS
(See block diagram)
Name
r
CI
AI
CAC
CAT
Arel
Zr
ZAC
ZT
ZB
CBW
C'BW
Typical value
Function
Protection CTP resistor
Battery voltage filtering capacitor
;;0300
470nF/l00V
Feeding bridge programming resistor, must be equal to: (total desired value ~ 2r) )( 2.5
A.C. coupling capacitor
Aing trip capacitor (50Hz ring Ireq.)
Reference resistor
Compensation of CTP resistor effect on gain and impedance, must be equal to :
50x2r
Impedance programing network. must be equal to : 50 x (DeSired imp. val. ~ 2 x r)
NB : can be complex
NB : can be complex
Bandwith capacitor, must be such that: CBW x (Zr + ZAC) =
Compansation 01 bandwith cap. lor transhybrid rejection C' BM x ZT =
ails
a !lS
Ring trip network
R, = R. = R. =R. relative precision ±O.5%.
R, = 500K absolute precision ±5%.
Ro =
3 KO (r
27 KO (Z
=30 0)
=600 0)
60 KO (Z = 600 Q)
60 KO (ZBal = 800 0)
K x Desired impedance value
K x Desired balance impedance val,.
R. =
1 KO
471lF/l0 V
220 nF110 V Ilow leakage
16KCll%
200Cl12W ±5%.
4-107
270 pF/l0 V
120pF/l0V
LOGIC INTERFACE
Input and output structuraa are serial register type.
Data Input
Two a·bit words can be written in the sLie.
B7
Val
BI
BI
B4
B3
B2
B1
BO
Date
Date
Date
Date
Date
Date
Regiat
Selact
For 80: "0"
B':Powerdown
B2: Special De characteristics
B3: Real battery voltage
84: I Limit' (30 mAl
Remark: Power denial mode if
For 80: "'"
B': General purpose
B2: Analog input/output "0"
B3:lTX
84: Reverse battery
B6: Ringing
B6: Not used
B7: Validation
B1.~.B5.B8 ="'"
B6: I Umit 2 (20 mAl
B6: I Umit 3 ('2 mAl
B7: Validation
= Input mode
Dataoutput
One '2·bit word can be read in the sue.
NOTE: • HS is always present on Data bus evan with·
out clock pulse
• At first clock rising edge HS can be read a
second time.
The data are written in the shift register at each clock
rise adge when CS = 0 and RIW = ,
HS: Hook Status
eRB: Comperieon Reault Bit between V BAT and V LINE
The data are read at each clock rise edge when CS
GK: Ground Key
andRIW=O
TW: Tharmal Warning
The first bit (80 = HS) can be read without clock when
The data ara latchad in tha sue when B7 (data input) =
"'" (Validation) and CS
CS=O
= "'"
The data ara stored in the 6 first reglstere if 80 =
and in the 6 last registere if 80 = "0"
=0
"'"
4-108
MAXIMUM RAnNG8
Rating
Power supply
Battery voltage
Supply voltage
Voltage drop between analog ground
(AG) and battery ground (BG) (For
IVBAT;;> 30 V)
Voltage drop between analog ground
(AG) and digital ground (OG)
Power supply rejection ratio (speech
band)
with: 0.2 V voltage ripple on
VeelVEE
0.6 V voltage ripple on VRAT
Symbol
Value
Unit
VBAT
Vee
VEE
·20to·72
+ 4.5to+ 5.5
·4.5 to· 5.5
·2 to + 2
V
V
V
V
• 1 to + 1
V
40
dB
Line
Line current (I Longituvinal +
I Transversal)
Line voltage
120 max
13
IVR~-.l-
Power diSSipation, in power down mode
(line current 0)
=
70
mA
V
mW
Overvoltage protection
TBD
Voltage on Tip or Ring during
overvoltage
All other inputs/outputs are protected
by diode clamping to supply rails
Temperature
Operating temperature range
Storage temperature range
Junction (thermal warning sets sLie in
power denial mode automatically)
Thermal resistance: junction to ambient
(case SIL 15: junction to case
=
4-109
Toper
Tstg
Oto + 70
• 55to+ 150
°C
°C
150
°C
40
oelW
3
°C/W
ELECTRICAL OPERATING CHARACTERISTICS
Unless otherwise specified
TA=25'C, VBAT= - 30to-72V. VCC=+ 5V±5%, VEE = - 5V± 5%
Transversal line current: IT = 30 rnA 0)
Longitudinal line currenl: IL = 0
Ch.racterlotic
Symbol
Min
Typ
0
0
-
Max
Unit
IVBATi- 13
V
rnA
Line feeding char8cterielicl
Line voltage (see DC curve, IT':'' llimit)
Line current (see DC curve)
Loop currant at conltant current feed
(lprog programmed by step. thru the bus)
Line wltage at constant voltage leed
Feeding bridge resistor (set by axt. comp.)
loop current in power denial mode
Loop current matching in normal/reverse battery mode
llimit
-6%
-60
- 1%
Off-hook detection threshold (Power down or power up)
On Ilook detection threshold (Power down or power up)
Off hook/on hook hysteresis
Dialing rale
Dialing distortion
Off-hook response time (I~~ = 20 rnA; power down)
Ground key detection thres 0 d
Ground key detection response time (lLONG DC 20 rnA)
Ring trip detection threshold
Ringing Irequency
Ring trip delay (lOC = 15 rnA. Ring Irequency = FR)
=
7
4
10
• Iprog
i"BAri- 13
--
-
3
-
llimit
+6%
800
1
+1%
10
7
-
-
-
22
3
70
20
260
10
70
4/FR
6.27
20
r - 10
-
r+ 10
-
5
16
-
rnA
V
Q
rnA
rnA
rnA
rnA
pulse/s
ms
ms
rnA
ms
rnA
Hz
s
Teletaxe lending
Line level (F
Gain
< 1B KHz, RL = 200 0)
AC characteristici (without TTX signal)
- 2 Wire port
Overload level (100 < f < 4000 Hz)
Return loss (300 < f < 3400 Hz)
Longitudinal impedance (on/off - hook - r = protection P TC)
Longitudinal balance
100<1<3400 Hz
100 < I < 3400 Hz on - hook
Longitudinal Signal generation (100
25On.
238ns
-=\-=--/= ""
4-123
CASE CB-79
C SUFFIX
CERA":1IC PACKAGE
PSUFFIX
PLASTIC PACKAGE
,
-
A~E
eEl
C~~
D.A T A
4-124
il:[·n~i.]~1
COMPONENTS
COMMUNICATIONS PRODUCTS
--~~---------
-------~---------------------------MOSTEK
APPLICATION
NOTE
CLOCK EXTRACTION MODULE-CIRCUIT 73321
AND
TERMINAL SWITCHING MODULE-CIRCUIT 7333
4-125
4-126
1 - CLOCK EXTRACTION MODULE (MEH) - CIRCUIT 73321
1.1 Circuit description
The specifications of this circuit are given in the TELECOM ICS catalog by THOMSONSEMICONDUCTEURS. This circuit provides the 2 Mbit/s - 6 dB -HDB3 interface as per
international standards.
PCM junction time recovery as defined by the CCITI generally requires a damped oscillator
sustained by logic 1's detected by the PCM junction.
Most of the time the oscillator consists of coils, capacitors, basic capacitors, and varicaps
whose wiring diagram is not easily integrated.
The solution retained is the use of a digital integrated circuit for PCM junction transmission
and reception (Fig. 1).
A 16,384 kHz crystal oscillator delivers a square clock signal with a 61 ns period to 73321
circuit(s). The circuit accepts external clock frequencies lower than or equal to 16,384 kHz for
in line outputs smaller than or equal to 2,048 kbits/s.
1.2 Bipolar and HDB3 conversion review
Portion A of Fig. 2 shows a series of NRZ (non return to zero) linear data to be transmitted.
The logic 1 or 0 is present throughout the propagation of a bit. There is no return to zero for a
logic 1 during this time.
In portion B this Signal is converted to bipolar form, logic O's remain as they are but 1 's
alternately take a positive and a negative value.
In portion C and 0 of the figure this same signal is converted to HDB3; not more than three O's
may be received in line. A fourth 0 would systematically be transmitted as a 1 whose
bipolarity has been violated with respect to the last 1 transmitted but whose bipolarity is
respected compared to the last violation.
Two cases are possible:
- In C offigure 2, the preceding violation not represented on the figure was positive, the first
4-bit word fill-in sequence will be:
OOOV
where V is negative, the following fill-in sequence will be :
BOOV
where B is a signal element different from zero, that is equal to + 1 in this case since B
should respect the polarity with respect to the last logic 1.
-
In D of figure 2, the preceding violation, not represented on the figure was negative. In
this case the first fill-in sequence will be:
BOOV
where V is positive since the preceding violation was negative, and in order that this
polarity really be a bipolarity violation, B is also positive. The value of the second
sequence is:
BOOV
where V is negative since the preceding bit V was positive and B is also negative and not
equal to zero to ensure violation.
Then, it is verified that the sequences described are such that the in-line dc component is
really equal to zero. Thus it is possible to use pulse transformers for galvanic insulation
between line and terminals.
4-127
CLOCK
DIVIDER BY 8
SYNCHRONIZATION
HD
HDB3+
JE+
CLOCK
TRANSMIT
FLIP· FLOP
C,LOCK
RECEIVE
FLIP· FLOP
HDB3-
JE-
RECEPTION
HI
JS+
JT+
CLOCK
INPUT
FLIP· FLOP
JT-
JS-
V..
FIGURE 1 - MEH BLOCK DIAGRAM
4-128
0
A
NRZ BINARY INFORMATION
B
BIPOLAR CODE
C
IN·LINE HDB3 CODE,
PRECEDING VIOLATION POSITIVE
D
IN·LlNE HDB3 CODE,
PRECEDING VIOLATION NEGATIVE
0
0
0
0
0
0
0
0
0
0
0
I
0
h
+
."
i5
c:
:II
m
...., '"I
...
N
CD
~
111
0
0
0
0
111
I
B
I
I
V
~
:II
m
n
m
<:
m
n
0
c
m
en
L:.J
P P
I V
2nd SEQUENCE
HDB3-
FOR D
HDB3'
_----on
ILfl
n,--_
1.3 Application No.1: using circuit 73321 with free oscillator
The Quartz oscillator shown in figure 3 is of the stand-alone type, its precision is on the order
of 50 X 10.6 , and its frequency in this application is 16,834 kHz.
It delivers several t 61 signals. Gates 74LS04 fan out is 8.
This oscillator can be constructed using HCMOS gates. The 6.8 k pull up resistors are thus
suppressed. The in-line signal is a HDB3 coded Signal with an attenuation of 6 dB max for a
3 V pulse delivered by a remote transmitter. Figure 6 shows the pulse for PCM CEPT junction.
Transmit and receive transformers are the same type. The transformation ratio between
primary winding and the two secondary windings of the receive transformer is 3 : 2. The
transmit transformer is of the step-down type (Fig 4.5).
Figure 4 shows an output transistor blocking device used in the event of a short-circuit on the
line.
1.3.1 RECEIVE SECTION
The information delivered in the form JE+ and JE- at the output of the 73321 circuit receive
side (which are the HDB3 signal rectified components) have a constant phase relationship
with the recovered clock signal HD. The HD clock period will be:
8t+/- 2t
where t is the crystal-delivered signal period (61 ns for our example).
1.3.2 IN-LINE TRANSMISSION
The phase relationship of information JS+ and JS- with local clock HL should be constant at
the transmission function input. The HL positive pulse width defines line pulse width.
There is no logical relationship between circuit 73321 transmit and receive sides.
In this application, transmission and reception are not synchronized.
The delay t1 caused at the input by the receive logic (between HDB3+ and JE+) is equal to
3t (if t = 61 ns, t1 = 183 ns).
The delay t2 caused at the output by the transmit logic (between JS+ and JT+) is 1.5 HL (if
HL = 488 ns, t2 = 732 ns).
1.4 Application No.2: using circuit 73321 with slaved oscillator
A buffer memory is used to overcom J the differences in the information bit durations caused
by the transmission and circuit 73321. The information will be written at HD rate and read at
the rate of the local clock from the oscillator slaved by HD rate. The buffer memory capacity
only depends from the jitter characteristics and the slaved oscillator correction speed. Figure
7 gives the block diagram of such a memory associated with circuit 73321. The functions
represented are:
• HDB3/BIN code conversion,
• slaved Crystal oscillator,
• frequency dividers,
• buffer memory and its write/read control.
1.4.1 HDB3/BIN CONVERSION
This circuit is used to convert the two HDB3 components to one NRZ signal with the same
jitter as the two original components. It makes also possible code conversion of a NRZ Signal
before amplification in circuit 73321 transmission section for application to the line.
1.4.2 CRYSTAL OSCILLATOR
The crystal oscillator frequency is 16,384 kHz. It delivers a time t61 in the form of a square
signal with a 61 ns period driving the internal logic of circuit 73321 and the oscillatorassociated frequency divider. A submultiple of the crystal frequency is slaved by a submultiple of the frequency received in line.
4·130
47pF
47pF
1--11--....-10 ..........- - 1 l---I
CRISTAL 18384 kHz
BUFFER
MEMORV
Zc TVPICAL LI NE
IMPEDANCE
J
T
+
DATA TO
BE SENT
2048 kBITS/S
PCM JUNCTION
LOCAL CLOCK
GENERATOR
FIGURE 3 - APPLICATION NO 1 - USING FREE CRYSTAL OSCILLATION
4-131
FIGURE 4 - MEH CIRCUIT BUlL T·IN TRANSMIT AMPLIFIER
10k
~
c:J~i-1
10 k
•
FIGURE 5- MEH CIRCUIT BUILT·IN RECEIVE AMPLIFIER
244 ns +25
244 - 25
nil
n.
24401- 50 ns
±20%
....,-
!
----
1
3 VOLTS
I
± 10%
'"--
-- -----
---
+50%
-
± 10%
I
~
IDEAL
\!
pxz"M'~
r---'-
~-
-20%
f--------.-
~
L-_
244
488
± 10%
nl
n.
48801
TSW ITH DU T PULSE
TS WITH PU LSE
FIGURE 6 - PULSE SHAPE FOR 2048 BITtS CEPT PCM JUNCTION
4-132
f---,
1.4.3 FREQUENCY DIVIDER ASSOCIATED WITH THE CRYSTAL
This is a counter in which each stage divides the input signal frequency by 2. The first 3 bits
deliver time t1 (at 2,048 kHz) corresponding to time HD whose jitter amplitude was reduced by
the extreme values taken by the slaved oscillator.
The following two bits A' and B' are used to select the buffer memory reading time (see timing
diagram of figure 8). The n following bit should be chosen by the user to set the crystal
oscillator correction frequency. If n = 6, the oscillator frequency will be corrected every
125 j1s.
1.4.4 FREQUENCY DIVIDER ASSOCIATED WITH HD
The first two bits A and B define the reading time in the buffer memory. If HD shows no jitter,
counters A' B' and A. B are in phase and reading takes places with a time delay of 2 bits after
writing.
Note: If 3 bits (A. Band C) define the writing time and 3 bits the reading time, reading will take
place with a time delay of 4 bit-durations compared to the writing time.
1.4.5 BUFFER MEMORY
This memory consists of a number of bistable circuits depending on the jitter to be recovered.
In our example the 4 bistable circuits are used to recover a signal with a jitter of + 1-2 bits in
amplitude without loosing information.
When the write counter A, B defines 2 as writing time, the read counter A' B' defines 0 as
reading time and so on.
The maximum phase shift between the two counters A, BandA', B' is 2 bits in either direction
without fault. Time t1 and data are the same residual jitter characteristic given by the slaved
crystal oscillator selected.
1.4.6 TRANSMIT SECTION
In this application signal t1 can be used to sample the data to be transmitted (Fig. 7).
Residual jitter is small enough to drive BIN/HDB3 decoder logic and to calibrate line pulse
width.
4-133
16384 kHz
n BiTS
+2"
11
HD
....Of"
w
"'"
~
+2"
JE+
HDB3
-BIN
JE-
p
HDB3 -6 dB
2 MbIS PCM
CEPT JUNCTION
JS'
BIN
-HDB3
JSTRANSMISSION PATH
.,
11
DATA TO BE SENT
FIGURE 7 - APPUCATION NO - USING SLAVED OSCILLATOR
DATA
RECEIVED
11
HD
,-I
-.
r-
LJ
I
I
I
A
B----------------~
NRZ
A BWRITEO
__b----'X
---.I
X
x=
X
X·I
I
0
:
L-
0
r-I
I
A BWRITE 1
A BWRITE 2
of"
....
Co)
c.n
211
•
A BWRITE 3
A' B' ROAD 2
---.I
2
1 . . . 1_ _ _ _ _ __
I
I
3
A' B' ROAD 3
3
L . . I_ _ _ _ _ _ _ _
_________________
~I
2
L
~
0
A' B'ROADO
A' B' ROAD 1
DATA RECEIVED
X
b
X
X
d
FIGURE 8 - APPLICATION TIMING DIAGRAM -72321 WITH SLAVED OSCILLATOR
X
C
2 • TERMINAL SWITCHING MODULE (MTC) CIRCUIT 7333
2.'
Circuit description
The specifications of this circuit are given in the TELECOM ICS catalog by THOMSONSEMICONDUCTEURS.lt conforms to CCITT recommendation G737. In most applications it is
connected between a clock extraction circuit of a MIC junction at 2.048 Mbits/s and multiplex
switching circuits at 2.048 Mbits/s.
The 7333 circuit buffer memory function is twofold:
• frame synchronization of PCM junction input section with local clock,
• absorption of line jitter whose amplitude and frequency are given in circuit 7333 specifications.
The receive function provides a multiplex signal at 2.048 Mbit/s synchronized with local
center clock (Fig. 9). The local center can be a connection network, a time concentrator, a
computer interface; etc.
So, the PCM junctions from various centers in a plesiochronous network can be synchronized
with the local center clock. Figure 10 shows that whatever the phase relationship between
remote clocks td1, td21 ... tdn, circuit 7333 associated with a remote center can set in phase
not only time slots but also incoming multiplex frames.
Special case
If remote centers are asynchronous, circuit 7333 synchronizes the multiplexes by skipping or
doubling frames without loss of synchronization.
In this application, HDB3-BIN conversion is made in circuit 7333 (pin 9 to VSS). A pin (MO) is
provided for this purpose without using associated microprocessor. In this case the three
alarms detected by the 7333 receive circuits:
- JDSY: junction desynchronized compared to CCITT algorithm,
- TE: error ratio too high compared to CCITT algorithm,
- MOX: clock missing (no Hd),
will be processed as follows:
They are considered as a logic OR whose value is transmitted in bit 3 of the odd frame time slot
o by the 7333 transmit circuits.
When pin MQ is wired as "'" a microprocessor can access the six registers R1 to R6.
Register' contains the outgoing junction even frame TSO value. Only TSO bit 1 can be
microprocessor-modified. The content of this register will be transmitted in line ifthe circuit is
not operating on the looping mode.
Register 2 contains the outgoing junction odd frame TSO value. Only bit 2 cannot be
microprocessor-modified, it remains 1. Bit 3 of register R2 can be either 1 or 0 as a result of a
logic OR with the 3 alarms defined above (junction desynchronized, error ratio too high, HD
clock missing). The content of register R2 will be transm,tted in line only if the circuit is not
operating on the looping mode.
Register R6 contains only one bit. It indicates whether a loop between outgoing and
incoming HDB3 components is desired for test. In this case:
Register R3 (8 bits) will contain a value to be introduced into even frame TSO and register 4
(8 bits) will contain a value to be introduced into odd frame TSO. The content of registers R3
and R4 is transmitted in line when the value of R6 (loop) = 1.
If R6 = 0 the contents of R1 and R2 are in line.
If R6 = , the contents of R3 and R4 are looped.
4·136
II
MEMORY
CONTROL
LOOP
....~
Co)
......
JUNCTION PCM
FRAME MEMORY
64 a·BIT WORDS
CONTROL
REGISTERS
TO MICROPROCESSOR
TO SWITCHING SYSTEM
ITO
FIGURE 9 - SWITCHING TERMINAL MODULE
~
R6=O
R6= 1
Content of
R1 and R2
Content of
R3 and R4
Content of
JE+ and JE-
Content of
R3 and R4
TSO
Out put
JS + and JSInput
Reception
Register R5 cannot be modified but only read by the microprocessor. It is managed by the
7333 circuit Receive function. The alarms detected are indicated in this register.
The value of bit 3 of incoming junction odd frame TSO is transferred in bit 1 of register R5.
When the value of this bit is 1, this means that the remote end does not control the frame it
receives any more (PVT: Perte de Verrouillage de Trame distante • Frame locking loss -).
Bit 2 of register R5 indicates that the 7333 sync device has found no frame locking code
(PVT1: Perte de Verrouillage de Trame locale - Local frame locking loss -).
Bit 3 of register R5 indicates that time HD is missing (MQHX). In this application, this
means that the crystal oscillator has stopped operating.
Bit 4 of register R5 indicates that the sync device is no more synchronized (JDSY).
Bit 5 of register R5 indicates the SIA value (SIA: Signal d'indication d'alarme distanteremote alarm indication signal). When JDSY == 0, the junction-is synchronized, SIA == 0; when
JDSY == 1 (junction not synchronized), during two frames.
Bit 6 of register R5 indicates an excessive error ratio higher than 10 -3 detected on the
frame locking code.
Bit 8 SAUT indicates frame skip or doubling on reading frame memory(if phase relationship
between remote end and local center is not defined: local and remote clock are plesiochronous).
Bit 7 of Register R5 indicates local clock lead (AV) or delay compared to remote clock.
If distant and local centers are synchronized by a common clock (not represented in figure 10)
thus circuits 7333 resynchronize multiplex signals without loss of information accepting a
peak-to-peak jitter of several TSs for very low jitter frequencies.
REMOTE CENTERS
•
SEVERAL KILOMETERS
LOCAL CENTER
.
II
2
LOCAL
CLOCK
Id2 b-----------------~~
SWITCHING
SYSTEM
FIGURE 10 - PLESIOCHRONOUS NETWORK
4-138
2.2 Application No.3: Binary inputs - Binary output
Figure 11 shows an environment where the 7333 incoming and outgoing data are binary. Pin
9 is used to select the incoming data code. In the receive mode a device external to circuit
7333 should deliver:
- the clock signal recovered from an amplifier that has reshaped the signal likely to have been
attenuated during line propagation,
- the associated information which has been converted (from HDB3 to binary):
In the same way, in the transmission mode circuit 7333 receives a multiplex signal from the
line, processes the 0 time slot content (ITO) in accordance with CCITI recommendations. A
device external to the 7333 circuit receives the processed multiplex signal and can convert it
from binary to HDB3 before transmitting it in line.
This application enables the user to select line reception and transmission amplifiers depending on transmission characteristics.
Id 7333
~
I
PCM JUNCTION
CLOCK EXTRACTION
DEVICE
BIN
SWITCHING
BIN
RECEIVE SECTION
CONNECTION MATRIX
1-----HDB3/BIN
CONVERSION
BIN
r----.BIN
TRANSMIT SECTION
+9
VCC
FIGURE 11 - BINARY INCOMING AND OUTGOING INFORMATION
4-139
CONNECTION MATRIX
2.3 Application No.4: 73321-7333 association
The diagram in figure 12 showS the whole switching terminal function. No additional circuitry
is required between circuits 73321 and 7333. They are designed for direct interface.
]
re...
r-e....
73~1
JE~
r-----
7333
J~-
/
JS
+JE
JE
1
HO
1
1~
!
1.
...... t'o
REMOTE F 4 kHz
t
CREATION OF
REMOTE
1T16WINOOW
HOB3IBIN
CREATION OF
LOCAL
1T16WINDOW
IT1B REMOTE
1 .'-
~
8·81T REGISTER
,
8·BIT REGISTER
r--
8
8
HOL.C FRAME
L.EVEL. 2
RECEPTION
HOL.C FRAME
L.EVEL.2
TRANSMISSION
MICROPROCESSOR BUS
IJP
FIGURE 12 - REMOTE TS16 EXTRACTION
2.4 Application No 5: extraction of IT16 content without loss of information
We have seen that, when the remote device was asynchronous with the local 7333 there may
be loss or repetition of information depending on th~ relative values of transmit and receive
clocks.
For 64 kbit-speech channels, the users will not be aware of frame skips or doubling, but, for
data channels, OSI system levels 2 (or 3) ensuring the exchange protocol between the two
units will request repetition of the message. The following device avoids message repetition
although the units are of the plesiochronous type.
4-140
Device description
One of the 7333 outputs labeled F4kHz (pin 15) delivers 4 kHz for the remote clock. The 7333
extracts the 4 kHz remote clock from the incoming junction in the same way as the 7332
extracts the Hd 2 MHz remote clock from the incoming junction.
It is possible to extract an TS content, for example TS16 content from incoming signals HD,
JE+, JE- and from signal F 4 kHz (Fig. 12).
An 8-bit word is delivered to a series-parallel register by a HDB3 converter operating at HD
clock rate. This word is selected by a device giving the time slot chosen, for example TS 16. At
the end ofTS16 the register content is loaded into a parallel-parallel register; a microprocessor can read this word after an interrupt for example. In the transmit mode, the microprocessor of figure 12 delivers a HDLe frame that can be inserted in TS16 of circuit 7333 local
mUltiplex JE (transmit side).
Position of signal F 4 kHz with respect to:
H,J-, HD
The 7333 internal logic works on HD falling edge (receive side). Figure 13 shows the
250 ps period F4kHz signal with respect to:
- recovered remote clock (pin 12),
- JE+,JE-,
.
the 4 kHz signal switches to another state on HD falling edge when bit 5 of ITO arrives on JE-,
JE+ (pins 7 and 8).
The delay (tpd) compared to HD falling edge is 250 ns max for a 50 pF load.
JDSY=O
HD
JE-. JE + BIT
DURATION
EVEN ITO
ITl
F4 kHz
JE-,JE+ BIT
DURATION
F 4 kHz
JDSY = 1
F4kHz=0
tpd--_~..
'pd':; 250
C ~50 pF
FIGURE 13 - F4kHz POSITION WITH RESPECT TO HC AND BIT
DURATION OF JE+I JE.
4-141
n.
CHAPTER 5 - TELEPHONE SET ICs
COMPONENTS
--------------------------~~---------------------------
-~----------------------------------------MOSTEK
COMPARISON OF THOMSON-MOSTEK TONEPULSETM DIALERS
Feature/Parameter
1.
Memory!
No. of Digits
2.
Key(s) Used For Redialing
3.
PulsefTone Switch able
###h'Y/#A~:/
Redial!
28
Redial!
28
Redial!
28
Redial!
28
10 no./
16 ea.
10 no./
16 ea
• or #
LND key
LND key
LND key
',0-9
" 0-9 or
Control 0-9
Manual
Manual or
Softswitch
Manual or
Softswitch
Manual or
Softswitch
Manual
Manual
Manual or
Softswitch
Manual or
Softswitch
Manual or
Softswitch
Yes
10 no./
18 ea.
10 no./
18 ea.
13 no./
18 ea.
Mem, 0-9
Single Keys
Single Keys
and LND Mem1-Mem9 Mem 1 - Mem 9
E1 - E3 & LND
and LND
4.
Pacifier Tone
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
5.
BCD Interface
No
Yes
No
No
No
No
No
No
No
6.
10!20 PPS Select
No
No
Yes
No
No
No
Yes
7.
M!B Ratio Select
No
No
Yes
No
No
Yes
No
No
Yes
8.
Continuous Tone
No
No
Yes
Yes
No
No
Yes
Yes
Yes
9.
Single Tones
No
No
Yes
Yes
No
No
Yes
Yes
Yes
10. Timed Hookflash
No
600 ms
Selectable
560 ms
No
No
560 ms
560 ms
Selectable
11. PABX Pause
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
12. Dialing Rate
Tone Pulse -
Fixed
5 TPS
10 PPS
Fixed
5 TPS
10 PPS
Selectable
5-6 TPS
10!20 PPS
Fixed
8 TPS
10 PPS
Fixed
8 TPS
10 PPS
Fixed
8 TPS
10 PPS
Selectable
5-6 TPS
10!20 PPS
2.5-6.0 V
2.5-6.0 V
2.5-6.0 V
2.5-6.0 V
2.5-6.0 V
1.8-6.0 V
2.5-6.0 V
1.8-6.0 V
2.5-6.0 V
2.5-6.0 V
2.5-6.0 V
2.5-6.0 V
2.5-6.0 V
1.8-6.0 V
2.5-6.0 V
1.8-6.0 V
2.5-6.0 V
1.8-6.0 V
18 pin
18 pin
20 pin
18 pin
18 pin
24 pin
18 pin
20 pin
24 pin
13. Voltage (Tone)
(Pulse)
14. Package Size
RC variable RC variable
RC Variable RC Variable
5 TPS typ
5 TPS typ
10 PPS typ 10 PPS typ
GLOSSARY
1. Control - To allow normal dialing of * and #, the MK5376 may use a separate Control Key for Butodialing.
2. Mem - The MK53761 , 53762, 53763 use separate Mem and PROG keys to stofe and autodial from
memories 0 to 9. The MK53763 also uses keys E1 - E3 to autodial 3 emergency numbers.
3. LND - Last Number Dialed; a separate redial key on the MK5371. MK53721. MK53731. MK53761.
MK53762. and MK53763.
6. RC - Resistor Capacitor; timing elements used to determine the dialing rate on the MK5375J6. So by varying the
RC values, the MK537516 may dial at rates from 5 to 10 TPS and 10 to 20 PPS.
7. Softswitch - Keyboard entry (storable in memory) to SWitch signalling modes.
a Continuous Tone - The selected DTMF tone will be output for the duration of the key closure. The MK53721,
53731,53761.53762 and MK53763 feature this as well as a guaranteed minimum output dura-
....
oA
5·2
MI{5375N
------~~-
TEN NUMBER REPERTORY
TONE/PULSE DIALER
COMMUNICATIONS PRODUCTS
FEATURES
o CMOS Technology provides low-voltage operation
o Converts push-button inputs to both DTMF and loopv+
18
iitii:iE
MOOE SELEcr
17
HKS
disconnect signals
o Stores ten 16-digit telephone numbers, including last
number dialed
o
Pacifier tone and PBX pause
o
o
o
Last-number-dialed (LND) privacy
o
OUTPUT
12
iiOWi
iiOW2
iiOW3
iiOW4
iiiiTE
0SC1
11
IW:IFlER lONEICHIP DISABLE
OSC2
10
DTMF OUTPUT
COL 1
18
COL 2
15
COL 3
14
vRATE CONTROL
13
7
Manual and auto-dialed digits may be cascaded
Ability to store and dial both "*,, and" #" DTMF
signals
Figure 1. Pin Connections
Variable dialing rate
DOn-chip power-up-clear guarantees data integrity
permanent locations may be easily protected from inadvertent key entries with the addition of a simple
"memory lock" switch to the application.
DESCRIPTION
The MK5375 is a monolithic, integrated circuit manufactured using Mostek's proprietary Silicon Gate CMOS
process. This circuit provides the necessary signals for
either DTMF or loop disconnect dialing. It also allows
for the storage of ten telephone numbers, including as
many as 16 digits each, in on-chip memory.
All of these options plus additional features are discussed in more detail in the following sections. The first
section contains a brief detailed description of each pin
function. The second section describes the device operation. This is followed by the DC and AC Electrical
Specifications, and a few application suggestions.
The MK5375 accepts rapid keypad inputs (up to 25 key
entries per second) and buffers these inputs in the FIFO
(First-In-First-Out) LND (Last-Number-Dialed) register.
Each digit entry is accompanied by a pacifier tone,
which is activated after the digit has been debounced,
decoded, and properly stored. Signaling occurs at a rate
determined by externally connected components, allowing the dialing rate to be adjusted for any system.
FUNCTIONAL PIN DESCRIPTION
v+
(Pin 1)
Pin 1 is the positive supply for the circuit and must meet
the maximum and minimum voltage requirements as
stated in the electrical specifications.
The flexibility of the dialer makes possible a variety of
applications, such as "scratchpad" number storage. In
"scratchpad" applications, the MK5375 inhibits signaling during entry, without interrupting a conversation.
MODE SELECT
(Pin 2)
In normal operations, Pin 2 determines the Signaling
mode used; a logic level 1 (V+) selects Tone Mode operation, while a logic level 0 (V-) selects Pulse Mode
operation. This input must be tied to one of the supplies to guarantee proper dialing.
Privacy is also an important feature. The MK5375 allows the LND (Last-Number-Dialed) buffer to be cleared
following a call, without affecting data stored in other
permanent memory locations. The memory in the
5-3
v+
v-
r------------l-}----------~--------l
I
I
I
I
I
CMOS
RAM
(64OSI1S)
KEYBOARD
-.rIO
1
2
3
4
5
•
7
•
••
0 ,
'--~~\r-I
t
15 ..
!~
~ I---I\r~----,
I
I
I
I
I
I
I
1---+-00 PiiUiE
I
I
I
I
I
IL ________________________________
"~
I
~
Figure 2. MK5375 Functional Block Diagram
KEYBOARD INPUT: COL1, COL2, COI.3, ROW4, ROWd,
this time the keypad is sampled, and if both row and
column information is valid, this information is buffered
into the LND location.
ROW2, ROW1
(Pins 3,4,5,13,14,15,16)
RATE CONTROL
The MK5375 keypad interface allows either the standard 2-of-7 keyboard with negative common or the inexpensive single-contact (FORM-A) keyboard to be
used (Figure 3). A valid key entry is defined by either
a single Row being connected to a single Column or
by V- being presented to both a single Rowand
Column. In standby mode either all the rows.will be a
logic 1 (V+) and all the columns will be a logic 0 (V-),
or vice versa.
(Pin 7)
The Rate Control input is a Single-pin RC oscillator. An
external resistor and capacitor determine the rate at
which signaling occurs in both Tone and Pulse modes.
An 8 kHz oscillation provides the nominal signaling
rates of 10 PPS (Pulses per second) in Pulse Mode and
5 TPS (Tones per second) in Tone Mode; the Tone duty
cycle is 98 ms on, 102 ms off. The RC values on this
input can be adjusted to a maximum oscillation frequency o~ 16 kHz resulting in an effective Pulse rate of 20
PPS and a Tone rate of 10 TPS.
The keyboard interface logic detects when an input is
pulled low and enables the RC (Rate Control) oscillator and keypad scan. Scanning consists of alternately
strobing the rows and columns high through on-chip
pullups. After both valid row and column key closures
have been detected, the debounce counter is enabled.
Breaks in contact continuity (bouncing contacts, etc.)
are ignored for a debounce period (TdtJ of 32 ms. At
The frequency of oscillation is approximated by the following equation:
Fosc = 1/(1.49RC).
5-4
(1.0)
The value suggested for the capacitor (C) should be a
maximum of 410 pF to guarantee the accuracy of the
oscillator. The resistor is then selected for the desired
signaling rate. Nominal frequency (8 kHz) is achieved
with component values of 390 pF and 220 kohms. Parasitics must be taken into account.
3A. Calculator-1\'pe Keypad
OSCIN, OSCOUT
(Pins 8,9)
Pins 8 and 9 are the input and output, respectively, of
an on-chip inverter with sufficient loop gain to oscillate
when used in conjunction with a low-cost television
color-burst crystal. The nominal crystal frequency is
3.579545 MHz, and any deviaton from this standard is
directly reflected in the Tone Output frequencies.
This oscillator is under direct control of the repertory
dialer and is enabled only when a tone signal is to be
transmitted. During all other times it remains off, and
the input has high impedance. The input OSCIN may
be driven by an external source.
DTMF OUTPUT
(Pin 10)
The DTMF Output pin is connected internally to the
emitter of an NPN transistor, which has its collector tied
to V+, as shown on the functional block diagram (Figure
2). The base of this transistor is the output of an onchip operational amplifier that mixes the Rowand
Column Tones together.
.3B. Standard lltlephone-1\'pe Keypad
The level of the DTMF Output is the sum of a single
row frequency and a single column frequency. A typical Single-tone sine wave is shown in Figure 4. This
waveform is synthesized using a resistor tree with
sinusoidally weighted taps.
~c,
The tone level of the MK5375 is a function of the supply voltage. The voltage to the device may be regulated to achieve the desired tone level, which is related
to the supply by either of the following equations:
T(O) = 20 LOG [(O.078V+)/0.775] dBm.
T(O) = O.078(V+) VRMS. (Row tones)
--,
...-0-- "'
(2.0)
(2.1)
PACIFIER TONE OUTPUT I CHIP DISABLE
(Pin 11)
L..---'-+--o--:--t--"*---- COMMON
(COtO
R"
R"
HOOKSWITCHES Sl AND 52 SHOWN IN ON·HOOK POSITION
(TELEPHONE TURNEO OFF, NOT IN USE)
220K
UK
""
220!(
toOO
teOK
tSOK
2401(
3.3K
110K
560K
0'
O.
0'
03
0'
06
2N5550
2N5550
VN10KM
VN10KM
2N540t
2N5550
""
tN4620
1N751
>OK
Figure 1. MK5375 Typical Application Without Battery Back-Up
5-59
C,
e,
390 PF
toO!'F
..
., .""
.,
,.0<
...."'"'
...
HOOlCBWtTCHES S, AND 82 SHOWN IN ()N.HOOl( POSmoN
(TELEPHONE TURNED 0fIF, NOT IS USE)
R7
RI.
."
."
Figure 2. MK5375 Typical Application Continuous Tone
5·60
.. ......
... ... ....
.,.
Q4
''''
220K
1GOn
110K
'SOK
240K
U •
t10K
....
10•
.N....
VNlOKM
YN10KM
2NI401
Z1
Z2
RI,
RI,
'N....
~:=
....
01
CO
CO
...PF
..."
MI{5370
-----~~-
SINGLE NUMBER PULSE TONE
SWITCH ABLE DIALER
COMMUNICATIONS PRODUCTS
FEATURES
v+
D Stand-alone DTMF and pulse signaling
D Recall of last number dialed (up to 28 digits long)
D Form-A and 2-of-7 keyboard interface
D Pacifier tone
D Powered from telephone line, low operating voltage
for long loop applications
18
PULSE OUTPUT
MODEfTEST
2
17
HKS
cr
3
16
R1
C2
4
15
C3
5
14
v-
6
13
R2
R3
R4
OSC1
7
12
MUTE1
OSC2
8
11
PACIFIER TONE
IC
9
10
DTMF OUTPUT
DESCRIPTION
Figure 1. Pin Connection
The MK5370 is a Mostek Silicon Gate CMOS IC that
provides necessary signals for either DTMF or loop disconnect (pulse) dialing. The MK5370 buffers up to 28
digits into memory that can be later redialed with a single key input. This memory capacity is sufficient for local, long distance, overseas, and even computerized
long-haul networks. Users can store all 12 signaling keys
and redial them using either the * or # as the first key
entry after going off-hook. Figure 2 shows the keypad
configuration.
A * or # key input automatically redials the last number dialed if it is the first key entered after a transition
from on-hook to off-hook (HKS input switched from a
high to low logic level). Auto-dialing is momentarily interrupted (during interdigital pause period or intersignal period) while manual keys are depressed, however
these inputs are not stored into memory.
FUNCTIONAL PIN DESCRIPTION
v+
Pin 1. V+ is the positive supply for the circuit and must
meet the maximum and minimum voltage requirements.
(See Electrical Specifications.)
MODE/TEST
Input. Pin 2. MODEITEST determines the dialer's default
operating mode. When the device is powered up or the
hookswitch input is switched from on-hook (V+) to offhook (V-) the default determines the signaling mode. A
V+ connection selects to tone mode operation and a Vconnection selects to pulse mode operation.
1
2
3
4
5
6
7
8
9
*
0
LND
#
LND
Figure 2. Keypad Configuration
Pin 2 also forces the device into test mode. Further information on this operation can be obtained from Mostek.
C1, C2, C3, R4, R3, R2, R1
Keyboard Input. Pins 3, 4, 5, 13, 14, 15, 16. The MK5370
interfaces with either the standard 2-of-7 with negative
common or the inexpensive single-contract (Form A)
keyboard.
A valid keypad entry is either a single Row connected to
a single Column or V- simultaneously presented to both
a single Row and Column. In its quiescent or standby state,
during normal off-hook operation, either the Rows or the
Columns are at a logic level 1 (V+). Pulling one input low
enables the on-chip oscillator to begin scanning the keypad. Scanning consists of Rows and Columns alternately
switching high through on-chip pull-ups.
5-61
After both a Rowand Column key have been detected,
the debounce counter is enabled and any noise (bouncing contacts, etc.) is ignored for a debounce period (Tdb)
of 32 ms. At this time, the keyboard is sampled and if
both Rowand Column information are valid, the information is buffered into the LND location. If switched on-
,
2
hook (pin 17 to pin 1), the keyboard inputs all pull high
through on-ohip pull-up resistors.
Ie
Input. Pin 9. Internal connection. This pin should be left
floating for normal operation.
3
KEYBOARD
INTERFACE
A.O
POmOU11'UT
DECODE
II1lTEl
3.4 KEYPAD
'"
DSC1
08C2
MOOeITEST INPUT
CONTROL
LOGIC
Figure 3. MK5370 Functional Block Diagram
5-62
vInput. Pin 6 is the negative supply input to the device.
This is the voltage reference for all specifications.
OSC1,OSC2
h,)utlOutput. Pins 7, 8. OSC1 and OSC2 are inputs to
em on-chip inverter used as the timing reference for the
circuit. It has sufficient loop gain to oscillate when used
with a low-cost television color-burst crystal. The nominal crystal frequency is 3.579545 MHz and any deviation from this standard is directly reflected in the Tone
output frequencies. The crystal oscillator provides· the
time reference for all circuit functions.
Figure 6. Spectral Response
DTMF OUTPUT
Output. Pin 10. An NPN transistor emitter with a collector tied to V+ drives the DTMF OUTPUT pin. The
transistor base is connected to an on-Chip operational
amplifier that mixes the Rowand Column tones. Figure
7 shows the timing at this pin.
Figure 4. Single Tone
The DTMF OUTPUT is the summation of a single Row
frequency and a single Column frequency. A typical single tone sine wave is shown in Figure 4. This waveform
is synthesized using a resistor tree with sinusoidally
weighted taps.
The MK5370 is designed to operate from a regulated
supply and the row (low group) TONE LEVEL is related to this supply by either of the following equations:
T01 = 20 LOG [(0.0776V+)/0.775] dBm
T01 = 0.0776(V+) VRMS
The DC component of the DTMF output while active is
described by the following equation:
VOC1 = 0.66 V+ - 0.6 Volts
Figure 5. Dual Tone
PACIFIER TONE OUTPUT
Output. Pin 11. A 500 Hz square wave is activated on
pin 11 upon acceptance of a valid key input, after the
32 ms debounce time. The square wave terminates after a maximum of 30 msor when the valid key is no
longer present. In pulse mode, all key entries activate
the pacifier tone. In tone mode, only a redial entry activates the pacifier tone. The pacifier tone provides audible feedback, confirming that the key has been
properly entered and accepted.
5-63
Table 1. DTMF Output Frequency
KEY INPUT
ROW
1
2
3
4
COL
1
2
3
DIAL SEQUENCE
STANDARD FREQUENCY
[2J G
ON-HOOK
ENTER
1215.9
1331.7
1471.9
+0.57
-0.32
-0.35
,---,
L...--...J
ENTER
,.....---l~
L...--...J
.
r--
3
, - - - - - - - - - - - - -_ _ _ _ _ _ __
L-.J
I
D~~~T
+0.31
-0.49
-0.54
+0.74
0
OFF-HOOK
KE:~~D ~---------
=.
699.1
766.2
847.4
948.0
1209
1336
1477
KEYBOARD - - - ,
'~~T I
% DEVIATION
697
770 .
852
941
ENTER
INPUT
ACTUAL FREQUENCY
_______
K~~~~S:A~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
rlj..._____________________
~j-;~-.-~---------~~~,1
n_J\IlIU
:--------------r----
r------'
Figure 7. Tone Mode Timing
5-64
n
-----------
mode signaling and Figure 7 for tone mode signaling.
MUTE1
Output. Pin 12. This pin is the Mute Output for both
tone and pulse modes. Timing is dependent upon
mode.
HKS
Input. Pin 17. Pin 17 is the hookswitch input to the
MK5370. This is a high-impedance input and must be
switched high for on-hook operation or low for off-hook
operation. A transition on this input causes the on-chip
logic to initialize, terminating any operation in progress
at the time. The signaling mode defaults to the mode
selected at pin 2.
The output consists of an open drain N-channel device.
During standby, the output is high impedance and
generally has an external pull-up resistor to the positive supply.
In tone mode, MUTEl removes the transmitter and the
receiver from the network during DTMF signaling. During dialing, MUTEl is active continuously until dialing
is completed.
PULSE OUTPUT
Output. Pin 18. This pin has a dual function determined
by the dialing mode selected. In Pulse Mode, the pin
is an output consisting of an open drain N-channel
device with zener protection. The break timing at this
output meets Bell Telephone and EIA specifications for
loop disconnect signaling. Figure 8 shows this timing.
In pulse mode, MUTEl removes the receiver or the
network from the line. Different circuitry is required for
tone and pulse muting external to the Ie and applications using both modes would not necessarily share circuitry. MUTEl timing is shown in Figure 8 for pulse
o [2J
DIAL SEQUENCE
ENTER
o
ONHOOK
OFF HOOK
ENTER
ENTER
[2J
G
~
KEYBOARD
INPUT
DIGIT 2
DIGIT 1
~6 _ _1
O~~~~~
MUTE
OUTPUT
[::J
-- - - -
J REDIAL
I
-LfU - - -u ---H-- - -- --Lf1J---U---
___ ~j.I·8
~
-l
I
I
,----,
~
,--4
TMo~t-
L.....J
I~:JT ~:L__________~O~F~F~HO~O~K~________~~H~L____________~OF~F~H~O~OK~__________~~K
:t;:~~~)
-14r--
___ I __ JIITL_ -----------u- ___ . . ______________ _
Figure 8. Pulse Mode Timing
5-65
DEVICE OPERATION (Tone Mode)
sign also ensures that data stored in the buffer exactly
matches the digits actually dialed.
When the MK5370 is not actively dialing, it consumes
very lillie current. While on-hook, all keypad input pins
are pulled high. Key entries are not recognized unless
they utilize a keypad common connection to force the
respective Rowand Column inputs low. These inputs
assume opposite states off-hook. The circuit verifies
that a valid key has been entered by alternately scanning the Rowand Column inputs. If the input is still valid
following 32 ms of debounce, the digit is stored into
memory, and dialing begins after a pre-signal delay of
100 ms. Each digit buffered into the RAM is dialed out
with a 98 ms burst of DTMF and an intersignaltime of
102 ms.
NORMAL DIALING (Off-Hook)
IDigit 31
Normal dialing is straightforward, all keyboard entries
will be stored in the buffer and signaled in succession.
LAST NUMBER DIALED (LND)
8
One important feature of the dialer is its ability to buffer
data into the RAM before signaling. This feature allows
less expensive keyboards to be used because signal
distortion and double digit entry caused by bouncing
and bounding of the keypad are eliminated. This de-
DIAL SEQUENCE
[!]
CHANGE MOQE
[!]
CHANGE MODE
ENTER
Last number dialing is accomplished by entering the
* or # key as the first entry after coming off-hook ..
[!]
=.;e III
. . -------------.U. . - - - - - -
ENTER
ENTER
KE~":."~"D
m
c:t= 0
L-Jr-----------.....U
K~:~RD
--um. _________________________
I~:~
.... ETC
K!!..~"!D_S~!
________________________ ~~~p
________~--------~~~FH~OO~K~-----------------~~
MODE
INPUT
DIAL DIGIT 2
O~:~T
______________________
_________________ _
I
I
I
I
-------lnru--------------------------------U------------'L____ r -------- - ---lL.__.....r------------ LJ------~
DIAL DIGIT 3
~U':-:T
O~~~T
DIAL DIOIT 1
..J
Figure 9. Pulse and Tone Mode Timing
5-66
Absolute Maximum Ratings·
DC Supply Voltage .................................................................... 6.5 Volt
Operating Temperature ......................................................... -30°C to +60°C
Storage Temperature ......................................................... -55°C to +125°C
Maximum Power Dissipation (25°C) ...................................................... 500 mW
Maximum Voltage on any Pin ................................................... (V+)+.3, (V-)-.3
Electrical Characteristics
* All specifications are for 2.5 Volt operation and full operating temperature range unless otherwise stated.
DC Characteristics
SYM
PARAMETER
MIN
V+
DC Operating Voltage (all functions)
2.5
VMR
Memory Retention Voltage
1.5
Is
Standby Current
0.2
IMR
Memory Retention Current
0.1
VMUTE Mute Output Operating Voltage
TYP
MAX
UNIT
6.0
Volts
1.3
NOTES
Volts
1, 6
1.0
/lA
1
0.75
/lA
5, 6
Volts
7
1.8
IT
Operating Current (Tone)
300
600
/lA
2
Ip
Operating Current (Pulse)
225
350
/lA
2
IML
Mute Output Sink Current (V + = 2.5 V)
1.0
2.0
mA
3
IpL
Pulse Output Sink Current
1.0
2.0
mA
3
Ipc
Pacifier Tone Sink/Source
250
500
/lA
4
KRU
Keypad Pull-up Resistance
100
kohm
KRD
Keypad Pull-down Resistance
750
ohm
V1L
Keypad Input Level-Low
0
0.3V+
Volt
V1H
Keypad Input Level-High
0.7V+
V+
Volt
NOTES
1. All inputs unloaded, Quiescent Mode (oscillator off)
2. All outputs unloaded, single key input
3. Your
=
5. Memory Retention Voltage is the point where memory is guaranteed
but circuit operation is not.
6. Proper memory retention is guaranteed if either the minimum IMR is
0.4 Volts
4. Sink Current for VOUT
=
0.5 volts, Source Current for Your
=
2.0 Volts
provided or the minimum V MR , The design does not have to provide both
the minimum current or voltage simultaneously.
7. Minimum supply voltage where activation of mute output with key entry is
ensured.
5-67
AC Characteristics-Keypad Inputs, Pacifier Tone
NO.
UNITS
NOTES
32
ms
1
250
Hz
1
4
ms
1
Frequency Pacifier Tone
500
Hz
1
Pacifier Tone Duration
30
ms
1
UNITS
NOTES
SYM
PARAMETER
3
TKO
Keypad Debounce Time
-
FKS
Keypad Scan Frequency
-
TRL
Two Key Rollover Time
-
FpT
4
TpT
MIN
TYP
MAX
NOTES
1. Crystal oscillator accuracy directly affects these times.
AC Characteristics-Pulse Mode Operation
NO.
MIN
TYP
MAX
SYM
PARAMETERS
-
PR
Pulse Rate
10
PPS
1
5
PDP
Predigital Pause
40
ms
2
6
IDP
Interdigital Pause
940
ms
2
7
TMO
Mute Overlap Time
2
ms
2
8
T8
Break Time
60
ms
2
NOTES
1. 10 PPS is the nominal rate.
2. Figure 8 illustrates this relationship.
5-68
AC Characteristics-Tone Mode
NO.
SYM
PARAMETER
MAX
UNITS
NOTES
-
TNK
Tone Output No Key Down
-80
dBm
1
-
TOd
Tone Output (dependent)
-13
173
-12
194
-11
218
dBm
mV rms
1,2
5
-
PEd
Pre-Emphasis, High Band
2.3
2.7
3.1
dB
-
De d
Tone Output DC Bias (V+
1.0
1.2
-
RE
Tone Output Load
-
T RIS
Tone Output Rise Time
-
DIS
-
MIN
= 2.5)
TYP
Volts
10
kohm
5
0.1
1.0
ms
6
Output Distortion
5.0
8.0
%
3
Tx
Tone Signaling Rate
5.0
1/sec
1
TpSD
Pre-Signal Delay
100
ms
2
T ISD
Inter-Signal Delay
100
ms
NOTES
1, 0 dBm equals 1 mW power into 600 ohms or 775 mVolts.
Important Note: The MK5370 is designed to drive a 10 kohm load. The 600
ohm load is only for reference.
2. Single tone (low group), varies when used in subscriber set.
3. Supply voltage = 2.5 to 6 Volts, RE =10 kohms.
4. RE=10 Kohms
7
5. Supply voltage = 2.5 Volts. These specifications are supply-dependent
6. Time from beginning of tone output waveform to 90% of final magnitude
of either frequency. Crystal parameters suggested for proper operation are
R,<100 n, Lm~96 mH, Cm~O.02pF, Ch~5 pF, f~3.579545 MHz, and
CL ~1B pF.
7. Time from initial key input until beginning of signaling.
5-69
TYPICAL APPLICATION
The MK5370 Mostek Pulse Tone dialer provides both
cost-effective telephone-line interface and the logic required for DTMF (Tone) and Loop Disconnect (Pulse)
signaling.
Pulse dialing originated with the rotary dial telephone.
The Mostek Pulse Tone dialer provides the same capability as the rotary dial telephone and the convenience
of pushbutton entry. The subscriber set (telephone) is
powered by loop current supplied by the telephone
company. Signaling, in Pulse Mode, is accomplished
by repeatedly interrupting the loop current. The central office senses, times, and counts each line "break";
the number of breaks corresponds to the digit dialed.
The duration of the break period, the dialing rate, and
the separation between consecutive digits (IDP time)
are controlled by the Pulse Tone dialer IC. Loop disconnect dialing is nearly a world-standard concept.
DTMF signaling consists of modulating the telephone
line with a signal comprised of two fundamental frequencies. Each frequency pair represents one of sixteen possible digit (or key) entries. Twelve of these
frequency pairs are commonly used (0, 1, 2, .... , " #).
The Mostek Pulse Tone dialer provides DTMF signalling capability controlling signal duration, separation,
level, and rate.
The typical application circuit in Figure 10 illustrates
one way the Pulse Tone dialer can be used. The pulse
output provides the signal to break the line to transistor 03. 03 switches off, eliminating the base current
to 04, which also switches off. The majority of the loop
current is then eliminated, resulting in a break condition. The IC dialer must be protected from large voltage fluctuations, such as that caused by interrupting
the loop current. Transistor 01 along with H2, C1, and
Z1 regulate the voltage to the dialer. The Mute Output
signal is active while signalling each digit to mute popping noises at the receiver (earpiece or speaker).
The DTMF tone output drives the base of 08, which
modulates the line. The tone level at tip and ring is determined by the effective impedance of the telephone
line and the speech network.
'Mode of operation is controlled by switch S1 (which sets
the default dialing mode).
Resistor R1 provides a small memory-retention bias
current to prevent the device from powering down while
on hook. The current required for long term memory
retention is less than 1!,A.
A ceramic sounder can also be interfaced to pin 11
(PACIFIER TONE) of the device. A pacifier tone signal
is activated for each key entry in pulse mode. This feature provides an audible indication for each valid key
entry. Keys may be entered faster than the maximum
signalling rate allows. Audible feedback confirms
proper key entry.
5-70
PACKAGE D
.
18.Pln DIP (N)ESCRIPTION
Plastic
(.300)
oej-'"'"
IVa V V \
I-----
18
.870 MAX.
.. _c kage
Overall length includ es .010 flash on either end of n 1500 .V6 =-10 dBV)
-'-'--t------r------t--7-~3-0 [:-B_%:-~-~-::'
Output noise level
-
-
65
Impedance: depends on external component. RZ
(Z = (V28/128) AC and RZ pin 11 = 750)
Z
500
600
OTMF Granerat or (note 4)
Crystal oscillator frequency
Tone frequency accur.acy
Low group tone level (depends on external components)
High group tone level (depends on external components)
Preemphasis (depends on external components)
Distortion DTMF signal (depends on external components)
-
- 1.5
- 11
- 9
+1
-
3.579545
+2
-
Logic inputs (note 5) keyboard mode
.Switch bounce elimination
Keyboard contact resistance "ON"
Keyboard contact resistance "OFF"
-
0.5
500
_,
-
MHz
+ 1.5
%
- 6
- 4
+3
- 26
dBm
dBm
dB
dB
I__-D~TM'-'-F~s~ig~n~a-I~le-v~el-s~p~re~a~d~(d~e~pe~n-d~s-o~n~ex~t~er_n~a_lc~0~m_p~0~n~e_n~ts~)~--------+_---~2---+---~-----1__--+-2---+i~---d.B----~
I
.
-
ms
II
I
10
kO
__ ~. __ kO .__._.
Logic inputs (note 6) MpU mode
I
Current drawn by A.B.C. and 0 input to go low
20
50
pPCurrent to force inputs E.F.G and H to go high
20!
50
/J. A
~. _~nputimP!da~c~e~ _______________________________I__------_t---------+_--~5~--+-___- ____i~---k~O.,--
~
Input max
volta~: _~~_ ~._~~~~_~~~:~~~~~~u_t_s_ _ _ _ _ ~__.L._ _- _ _L ._ _O_---'._ _-_ __'_
Ii
5-115
V_2_B____________V
____
_
Note 1: 1 ransmission mode
External components:
RAL1 = RAL2 = 0
CAL1 = CAL2 = 47 pF
RALB1 = RALB2 = 56 kO
REC 1 = REC2 = 6.2 kO
CEC1 = CEC2 = 2.2 nF
RDTMF = 5110
CF1 = 106 nF
RZ = 75 0
RCG1 = 60 kO
RCG2 = 14 kO
CF2
= 10 nF
5-116
~
test diagram
Note 1: test conditions (continued)
Maximum transmission gain for IL
GSmax
= 30 mA
Gain control:
= ~~
• For IL
• For IL
30
•
87
= 87 mAo GS = GS max -
6 dB.
IllmAI
CMRR
For other values of line current and corresponding
values of RCGl and RCG2: see application note.
•
For IL
Gain reduction during dialing
•
= 30 mAo GS = GSmax·
= 30 mA.
= V28 CMRR =
GSCM
Close swith S (pin 13).
Vm
GS max
GSCM
17<>----11
llJ.1
160----1
llJ.1
IV
Vm
Transmission noise level:
•
=
Measured on pin 28 with IL 30 mA and the corresponding diagram on the microphone inputs.
0>-------11 ~
0...------11~
5·117
200
n
Note 2: Antisidetone - test diagram
External components:
RZ = 75 0
RDTMF = 511 0
CFl = 106 nF
CF2 = 10 nF
RCGl = 60 kO
RCG2 = 14 kO
RAL 1 = 0
RALBI = 56 kO
CALt = 47 pF
RECI = 6,2 kO
CECI = 2,2 nF
RAL2 = 28 kO
RALB2 = 51 kO
CAL2 = 1,15 nF
REC2 = 2,7 kO
CEC2 = 2,2 nF
Test conditions:
• Short line: I L = 87 mA
•
1345>1
ZL = 600 0
Long line: IL = 30 mA
ZL = ZLL
ZLL represents a line 3,5 kilometers long with a
diameter = 0,4 mm,
Antisidetone efficiency:
V6
E = 20 log,o ( - )
V28
5-118
118 nF
Note 3: Receiving mode - Test diagram
External conponents:
=
=
RAll
RAL2
RECl
REC2
CFl =106 nF
= 0 CAll = CAL2 = 47 pF RALBl = RALB2 = 56 kO
= 2.2 nF RZ = 75 0 RCGl = 60 kO RCG2 = 14 kO
CECl = CEC2 = 62 kO
RDTMF = 5110
CF2 = 10 nF
Test conditions:
Maximum receivin"g gain:
• For
Ii.. =
30 rnA
GRmaX=~
VB
Gain control:
• For IL
• For IL
0=
30 rnA
87 rnA
GR = GR max
GR = GR max - 6 dB
Output noise level:
• Measured on pin 6, with the corresponding diagram
17
on microphone inputs.
18
O>-------II:=J
oo------tl
l).1f
5·119
200n
Note 4: DTMF - Test diagram
External conponents:
=
CAll = CAL2 = 47 pF
RALBl = RALB2 = 56 kO
RALl = RAL2 0
CECl = CEC2 = 62 kO
RECl = REC2 = 2.2 nF
RZ = 75 0
RCGl = 60 kO
RCG2 = 14 kO
RDTMF = 511 0
CFl =100 nF
CF2
10 nF
IL = 30 mA
=
Frequency accuracy, tone levels, preemphasis, distor-
tion can be measured by putting the right code on the
logic inputs for every couple of frequencies. See note 5
and 6.
Remaining receiving gain during dialing: the circuit
must be in test mode (single-tone).
Remaining gain = 20 log,o (V6/V28).
5-120
Note 5: Logic inputs table .. Keypad mode
EQUIVALENT DRAWING OF LOGIC INPUTS
INPUTS E. F. G. H
INPUTS A. B. C. 0
OPEN
20/1A
= HIGH
Inputs
Left OPEN = LOW
A
0
E
F
G
H
Mute
C
Generated
tones (Hz)
Symbol
8
H
H
H
H
L
L
L
L
-
-
off
L
H
H
H
L
L
L
L
697
on
H
L
H
H
L
L
L
L
770
-
H
H
L
H
L
L
L
L
852
-
on
H
H
H
L
L
L
L
L
941
-
on
H
H
H
H
H
L
L
L
1209
-
on
H
H
H
H
L
H
L
L
1336
-
on
H
H
H
H
L
L
H
L
1447
-
on
H
H
H
H
L
L
L
H
L
H
L
L
H
H
L
H
L
H
L
H
L
H
L
L
H
H
L
H
L
H
L
L
H
! L
H
L
L
-
on
"1"
on
697 + 1 336
"2"
on
697+1477
"3"
on
697 + 1 633
"A"
770 + 1 209
"4"
770 + 1336
"5"
on
770+1477
"6"
on
770 + 1633
"8"
on
852 + 1209
"]"
on
852 + 1 336
"8"
on
852+1477
"9"
on
852 + 1633
"C"
on
941 + 1 209
"*"
on
941 + 1336
"0"
on
"
on
941+1477
H
H
on
120
1633
697 +
H
941 + 1 633
5.1
5.2
5.3
._--
on
I
on
"0"
Note 5.1: Speech mode.
Not85.2: Test mode.
Low group tones.
Note 5.3: Test mode.
High group tones.
Note 5.4: This table is only valid if E,F,H,::: low
As soon as one of the inputs E,F,G,H, is high, the others are considered low.
As soon as one of the inputs AB,C,D, is low, the others are considered high.
5-121
Notes
I
5.4
1
Note 6: Logic inputs table - Microprocessor mode
--
I
Inputs
--
Generated
T
I
tones (Hzl
Symbol
Mute
G
L
L
-
6.1
L
-
off
H
on
6.2
H
H
697 + 1209
"I"
on
H
H
697 + 1336
"2"
on
H
H
H
697+1477
"3"
on
L
L
H
H
697 + 1633
"A"
on
L
H
H
H
H
770+ 1209
"4"
on
L
H
L
H
H
770+ 1336
"5"
on
i~f'H
L
L
H
H
H
770+1477
"6"
on
L
L
H
H
770+ 1633
"B"
on
H
H
852 + 1209
"7"
on
H
852 + 1336
"8"
on
H
852 + 1477
"9"
on
~-""
--- -f--+-- 941 + 1 209
"C"
on
A
B
C
D
H
H
H
H
X
X
X
X
H
H
H
H
H
H
H
L
H
H
L
H
H
H
_._H
LIH
H
H
---f-----
---
E
H
F
t-
-
~fi...T--.ti.-LiHL'H
H
---I-
l
'j
L
---+
"+'t1"
L
-
,
H
-t-
--
H
+--
H
._
.H _
L + L
H JL _ _
H
I L f_Lt L ; H+_....fi._-r-!i
L I L 1, L
,
H
H
L _-.l!_______
____ J
L._
,
.....
--+"H
t
J.. _____
6.3
on
941 + 1 336
"0"
on
941 +1477
941 + 1 633
"#"
On
"D"
on
___ '--__
Notes
Note 6.1: Speeck mode.
Note 6.2: Silence position.
Note 6.3: Mute coincides with tone borsts.
Impedance mute or silent setting
I I
EFH=MUTE
G
= ENABLE
TEA 3046
LINE SIGNAL
IL----_--'
__--'I
t I
A--wvwi~----,I~
SPEECH
DTMF
5-122
SILENCE
DTMF
SPEECH
FUNCTIONAL DESCRIPTION
TRANSMISSION AND LINE ADAPTATION
Includes microphone and telephone amplification, both
with line length depending gain control and a line impe-
The line length is sensed through the line current. 2
external components allow the gain control to compen-
sate any kind of line length and feeding bridge.
dance automatic matching 2-wireto 4-wire conversion.
The microphone preamplifier performs high CMRR, for
crosstalk and radio detection immunity and low noise
characteristic. Its architecture allows symmetrical and
asymmetrical inputs and external adjustment of gain to
fit difference microphone capsules. A single pole filter
limits the amplifier bandwidth for a best high frequency
figure.
The earphone amplifier is a low consumption type. It is
click free when muted and its gain can be externally
adjusted.
2-wire to 4-wire conversion is performed by subtracting
microphone signal from line before applying it to earphone amplifier. An automatic line impedance tracking
antisidetone circuit provides excellent sidetone efficiency for every line length.
The dynamic impedance of the circuit is set by an external resistor to match with different line impedances.
DTMF SIGNAL GENERATION
Tones are obtained from a crystal controlled ascill-atar
followed by two independent programmable dividers
and 2 sinewave synthetizers. The crystal is a low-cost
TV model 3.58 MHz oscillator.
The amplitude of the multi-frequency signal is set by an
external resistor.
The required tone frequencies are selected by either an
inexpensive single contact 4 x 4 keypad or by a micro~
computer. Single-tone operation for testing is also pro-
vided.
THE POWER SUPPLY
This is 0.6 mA current source with a typ max voltage
compliance of a 3.2 V.
It can power either and electret microphone or a microprocessor.
If this source is not used, pin 2 is connected to ground to
reduce the ICC (pin 28) current.
5-123
CASE CB-132
~
2)8~~11'-
C SUFFIX
PSUFFIX
CERAMIC PACKAGE
PLASTIC PACKAGE
11) Nom'naidimens'on
12~
i+-____3!H·I""mo"-'_ _ _ _-I
True geometrical position
"
'"
-
DIN
(8-132
A51E
'"
OA 1 A
5-124
.--.--......................
TEA 7531
.-~~-
TELEPHONE SET LOUDSPEAKER AMPLIFIER
COMMUNICATIONS PRODUCTS
TEA 7531
TELEPHONE SET LOUDSPEAKER AMPLIFIER
The TEA 7531 is a 16-pin DIL integrated circuit especially designed to be used as
a loudspeaker amplifier. It is the same as the TEA 7031 but without the switching
supply for MCU.
Functions and features implemented on the chip include:
• Amplifying the incoming signal and feeding it to the loudspeaker. PGO and PG1
inputs are used to set the loudspeaker gain in a range of 32dB to 14dB in 6dB
steps.
• Permitting the loudspeaker to be cut-off thus ensuring privacy of communication.
• Incorporating the antilarsen (Anti acoustic feedback) system.
• Producing maximum output power of 100 mW at 5 V or 25 mW at 3 V (into
a 50 Ohms loudspeaker).
BLOCK DIAGRAM
:.....
LEVEL CONTROl.
5-125
CHAPTER 6 - HIGH SPEED
DATA CONVERSION
TS8306
----
--~~-
20 MHz 6-BIT FLASH
AID CONVERTER
COMMUNICATIONS PRODUCTS
PRODUCT PREVIEW
HMOS2
VIDEO SPEED 6-BIT FLASH AID CONVERTER
The TS8306 is a monolithic 6 bit HMOS2 parallel (flash) AID converter designed for 20 MSPS conversion speed.
Parallel sampling is performed via a resistor ladder and 64 autobalanced comparators. Conversion is accomplished within one clock
20 MHz
6-BITFLASH
AID CONVERTER
pulse.
CASE CB-79
A very low input capacitance (less than 15 pF) and a low input
dynamic range (1 volt possible) allow very easy drive of the TS8306.
• 20 MHz sampling rate.
• 10M Hz input bandwidth without sample and hold.
• Accuracy better than 6 mV (operation at low reference possible).
•
•
•
•
•
•
Single +5V supply.
Logic inputs and outputs are TIL and CMOS compatible.
6 bit data. underflow and overflow lines are 3-state outputs.
16 pin package (chip also available).
Very low cost device.
Soon available in 5016 plastic micropackage.
•
•
•
•
•
•
•
•
High speed data acquisition.
TV video digitizing.
Radar pulse analysis.
Medical imaging.
General purpose hybrid ADC·s.
Optical recognition.
Fax machine and video printer.
All high speed AI 0 conversion applications where low power and
low cost are required.
PSUFFIX
PLASTIC PACKAGE
ALSO AVAilABLE
C SUFFIX
JSUFFIX
CERAMIC PACKAGE CEROIP PACKAGE
PIN ASSIGNMENT
8LOCK DIAGRAM
elK
OVFl
B6
IMSBI
B1
IlSBI
UNFl
IT
IN Voo
GNO
6-1
elK
ct
GNO
OVFl
V(ref+)
B61MSBI
REF/2
B5
V(r.n
B4
VIN
B3
VOO
B2
UNFl
B11lSBI
PIN DESCRIPTION
NAME
PIN
TYPE
N°
FUNCTION
OESCRIPTION
CLK
I
1
Clock input
TT L level accepted
GND
I
2
General ground
Inside, analog and digital ground are separated.
Vlref')
I
3
Upper reference
Access to the upper resistance ladder
REF/2
I
4
Middle reference
Access to the middle resistance ladder. The conversion law can be
changed by forcing this point by an external voltage source.
Vlrer)
I
5
Lower reference
Access to the lower resistance ladder.
VIN
I
6
Analog input
VDD
I
7
Positive supply
UNFL
0
8
Under flow
status line
Bl
ILSB)
to 86
IMSB)
0
OVFL
0
15
Overflow status
line
This line is set to logical "1" when the input signal is higher than the
Vlref') voltage; all data IBl to B6 are set to logical "1".
CE
I
16
Tristate enable
CE commands the tristate mode for all output buffers IBI to B6,
OVFL and UNFL).
When CE = "1" : tristate
CE = "0" : output valid
Inside, analog and digital supply are separated.
This line is set to logical "1" when the input signal is lower than the
Vlref-) voltage. All data 181 to B6) are reset to logical "0".
Output data
9 to
14
MAXIMUM RATINGS
Rating
Symbol
Value
SupplV voltage
VDD
o to + 7
Storage temperature
T stg
-60 to
Operating temperature
Tamb
-60to+130
°c
°c
Power supply current on pins (2.71
17.12
150
mA
+
Unit
150
6-2
V
ELECTRICAL CHARACTERISTICS
Tamb = +25 oC, VOO =+ 5 V, VREF+=+ 2 V, VREF -= Ov
Symbol
Min
0
-
Quantizing error
N
ILE
OLE
QE
Vollage supply
Power dillipalion 115 MHz)
VOO
Po
Characteristic
Resolution
Integral linearity error
Differential linearity error
Maximum sample rate
FS
Fe
la
Analog bendwilh
Aperture jitter
Reference I.dda~
lower reference voltage
REFREF+
REF+- REFRL
upper reference voltage
fuillcale range
ladder resistance
Input capacitence
Cin
Logic oulpullow vollage
high vollage
VOL
VOH
VIH
VIL
Digital input low voltage
high voltage
Typ
±
- 1/2
4
1/2
-
Max
Unit
6
0
1/4
+ 1/2
BIT
LSB
LSB
LSB
5.25
120
V
mW
-
MHz
MHz
pS
5
-
-
20
10
-
-0.5
0.8
0
2
2
1.5
-
-
2.4
-
250
VOO-l.5
-
kQ
-
15
pF
-
0.4
V
V
V
V
-
2.4
V
V
-
0.8
-
TIMING DIAGRAM
External clock
Auto-zeroN
N+'
N+2
eomparoton{
.,d
latches
Output
ma.ter {
slave register
I
I
Data available
d~,"~~~~"[=>< ___~X N., X~_N_-,X. . _N_+'---'!fJ),C N+ 2
I
I
I
I
i
Tp= 30 ns (maxi
I
6-3
><=
1
TYPICAL CONFIGURATION
.5V
I-----~ OVERFLOW
r----------.MSB
OUTPUT
DATA
driver
I-----~LSB
~------------~--------------------.UNDERFLOW
Conventions
•
•
Caution for use
Incoming ground pin
•
221lF tantalum capacitors
(as near as possible to the incoming
ground pin)
•
100 nF ceramic capacitors
(as near as possible to the device pin)
Ground plane connected to the incoming ground pin
6-4
•
Avoid DC current flows in the ground plane
•
Try to respect star connections for high DC current
flows (connection to the incoming pin)
CASES
SOB "'0'
].}e':A0
,
,
CB-79
5J
I
02
7~~_
03
o~
-
111
Nom.n~1
....
15'
d,menSion
1/1 TrU€9f'omelC1caipO>,110n
16"m
,
P SUFFIX
PLASTIC PACKAGE
ALSO AVAILABLE
C SUFFIX
CERAMIC PACKAGE
J SUFFIX
CERDIP PACKAGE
(6-79
A50E
llIOMSON
~I' '-·r+'-11-'-r+.
,-
i i. i
'I' :;:,
+]-;;;;;;-'
06J
I I
"', !
1
.!2
_4l
CB-359
.l
___ ..
5016
~04~
,
-
(8-359
eEl
OA T A
6-5
FP SUFFIX
PLASTI C PACKAGE
NOTES
6-6
TS8308
-----~~-
VIDEO SPEED 8-BIT FLASH
AID CONVERTER
COMMUNICATIONS PRODUCTS
ADVANCE INFORMATION
HMOS2
VIDEO SPEED 8-BIT FLASH AID CONVERTER
The TS8308 is a monolithic 8-bit HMOS2 parallel (flash) A/D converter
designed for 20 MSPS conversion speed.
Parallel sampling is performed via resistor ladder and 256 comparators.
Conversion is accomplished within one pulse.
A very low input capacitance (less than 30 pF) and a low input dynamic
range (1 V possible) allow a very easy drive of the TS8308.
Typical characteristics:
• Single +5 V supply.
• ±1 LS8 integral non linearity.
• ±o.5 LS8 differential non linearity.
• 20 MHz sampling rate.
• 5 MHz input signal without sample and hold adjunction.
• Very low input capacitance (max. 25 pF).
• All logic inputs and outputs are TTL compatible.
• Data output: 8-bit binary code + overflow.
• Output buffers for 8-bit data and overflow are 3-state type.
• Accuracy better than 6 mV.
• Pin to pin compatible with RCA CA 3308.
VIDEO SPEED
8-BIT FLASH
AID CONVERTER
CASE C8-68
~
2~ir['
P SUFFIX
PLASTIC PACKAGE
Typical applications:
• TV video digitizing.
•
•
•
•
•
•
•
•
•
Ultrasound signature analysis.
Transient signal analysis.
Radar pulse analysis.
High energy physics research.
High speed oscilloscope storage/display.
General purpose hybrid ADCs.
Optical character recognition.
Digital signal processor data acquisition systems.
Satellite operations.
•
Portable video speed products.
J SUFFIX
CERDIP PACKAGE
Ceramic package (C Suffix) is also available
PIN ASSIGNMENT
• Video printer.
• Fax machine.
• Image processing.
• Medical imaging.
• All high speed A/D conversion applications where low power and low
cost are required.
B11LSBI
3R/4
B3
VAEF ~
B4
vin
B5
R/2
86
PHASE
B7
CLK
B81MSBI
·OVFL
R/4
6·7
ASUP
B2
AGND
N.C
VREF-
DGND
GEl
DSUP
CE2
BLOCK DIAGRAM
4>1
4>2
CLOCK
CLOCK
GENERATOR
PHASE
4>2
OVFL
256 -8
ENCODER
IRDMI
~8
I
I
8 BIT
I
I
OUTPUT
I
I
MASTER
I
I
I
SLAVE
I
I
I
REGISTER
I
B1
1----....-!121------f171----....-!
VIN
ASUP
DSUP
AGND
• 5 V ANALOG
• 5 V DIGITAL
ANALOG
DIGITAL
FUNCTIONS
FUNCTIONS
GND
GND
6·8
PIN DESCRIPTION
Type
Name
B1(lSB)
l
I
Function
Description
~-----------------+I'----------------------------------------1
Number
1
____
to____+-___O
____+-____t~o_
f- B8(MSB)
OVFL
0
9
Output data
I
'I
Overflow status Ime
Tristate buffer outputs
This line is set to logical "'" when the input signal
is higher than the VREF+ voltage. All data (8, to 8a) are
set to logical" 1 ".
I
R!4
10
First quarter reference
DGND
11
Digital ground
Access to the first quarter reference voltage
+-___I____+-___1_2__-1_____D_'_gj_ta_l_s_UP_P_IY____~-----------------------------------------1
DSU__
P__
IcE2
I
13
Tristate command
CE2
= "a" ; tristate for both overflow status
and data lines
GE2 = "1" : overflow valid lout data lines
valid only if GEl ::= "0",
14
Tristate command
15
Lower reference
NC
16
Non connected
AGND
17
Analog ground
ClK
18
Clock input
TTL levels
PHASE
19
Phase input
When phase is "0" the input signal is sampled on
the failing edge of the input clock. When pbase is "1" "
the input signal is sampled on the rising edge of the
input clock
RI2
20
Half reference
21
Analog input
22
Upper refetence
Access to the lower reference voltage. A voltage
source must be applied (or ground)
Access to the half reference voltage
Access to the upper reference voltage. A voltage source
must be applied
3 R!4
23
Third Quarter reference
Access to the third Quarter reference voltage
r--------r--------+--------1------------------+------------------------------------------~
~_~~~P___
I____~___2_4__~_____A_n_a_IO_9_S_U_pp_I_Y____L __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
_ L_ _ _ _
6-9
MAXIMUM/ RATINGS
Rating
Symbol
Value
o to +
Unit
Supply voltage
VDD
Storage temperature
T stg
- 60 to +150
Toper
- 60to + 130
"C
17. 12
150
mA
Operating temperature
Power supply current on pins (2,7)
ELECTRICAL CHARACTERISTICS
Tamb = + 25'C ASUp = DSUp =+5 V
7
VREF+ = +2 V
Characteristic
V
"C
VREF- =0 V
Symbol
Resolution
linearityefror
Differential linearity error
Quantizing error
N
ILE
DLE
QE
Voltage supply
Power dissipation (15 MHz) : Analog supply
Digital supply
ASUP,DSUP
POA
PDD
Maximum sample rate
Analog bandwith
Aperture jitter
Fs
Fe
tIl
Reference ladder:
Lower reference voltage
Upper reference voltage
Full scale range
Ladder resistance
VREFVREF+
VREF+ - VREFRREF
Input capacitance
Gin
Logic output low voltage
VOL
VOH
VIH
VIL
high voltage
Digital input low voltage
high voltage
6·10
Min
Typ
-
-
-
-
-112
4
-
15
-
-0.5
1
1
400
2.4
2.4
± 112
± 1/4
-
5
150
250
20
5
-
Max
Unit
8
Bits
LSB
LSB
LSB
-
-
+ 112
5.25
-
250
-
V
mW
mW
MSPS
MHz
ps
0
2
2
650
VOO - 1.5
VOO - 1.5
900
.(}.
25
30
pF
-
0.4
V
V
V
V
--
-
0.8
V
V
V
TIMING DIAGRAM (PHASE =" 0 ")
External clock
~~-{
Auto-zero N
N+2
N+'
iD,
latch.s
~2
--{
~,
slew register
~2
I
Output
data change
I==><
Data available
X
N·'
N
X
X
N+'
I
!x
I
I
I
I
N+2
I
I
I
!
Tp = XI ns Imaxl
NB: If phase is set to "1", the external clock is inverted inside the circuit
6-11
><=
FUNCTIONAL DESCRIPTION
Circuit TS8308 includes:
•
•
•
•
a sequencer generating internal clock,
a core ensuring conversion,
an output circuit delivering digital data.
the sequencer generates 6 internal clocks from pins
ClK and PHASE:
-
Internal phases
4>1
r--
4>2
Value (PHASE = 0)
Circuits concerned
Function
Comparators
Autozero
elK
Comparators
Sampling and comparison
elK
4>2+0
4>3
Latches
Storage
4>4
Encoder
Transmission
4>2+0
4>5
Output master/slave flip - flop
Sampling
4>6
Output master/slave flip
4>.1 +0
4>2+0
~
flop
Storage
..-
N.B. : 0 is a time-delay introduced to compensate for signal propagation time.
• the core includes:
- A resistor linear network delivering 256 reference
voltages distributed linearly between external
reference voltages VREF+ and VREF -. Access to
quarter (R/4). half(R/2) and three quarter (3R/4)
bridges enable the following:
- either improve linearity by externally forcing
reference voltages.
- filter disturbances going through the bridge by
means of external capacitors.
- or delinearize the bridge by means of external
resistors (law of linear compression by blocks).
- A set of 256 voltage comparators parallel connected across the 256 taps of the reference bridge
and the input analog signal which defines the
256 (2') quantification levels.
In first phase 4>1. these comparators store their
flip-flop threshold then. in phase 4>2 they compare
the thresholds with the input signal.
The comparators with an input signal voltage
lower than the reference voltage present a given
state at the output. the others present the complementary state.
The 256 comparators output is stored in
256 latches at the end of phase 4>3 4>2.
=
- A 256 to 8 decoder detecting the transition between the comparators in a given state and the
ones in the complementary state.
The line enabled corresponds to the last comparator which has tripped. i.e. the comparator with the
reference voltage nearest by default to the input
signal.
- A ROM following the decoder and coding over
8 bits the detected comparison chain in binary.
If the input signal is lower than the lowest reference voltage (1 st comparator). code 0 is written
at the output.
If the input signal is highar than the upper most
reference voltage(256th comparator). code 255 is
written at the output and overflow bit is set to 1..
• The output stage consists of 9 identical parts (8 bits
and overflow) each formed of a flip-flop D connected
to the ROM output with an output buffer. This buffer
4>2 and includes a selecis enabled on phase 4>6
tive high impedance command.
Inputs CEl andCE2 switch the output bits to this3rd
state (with overflow bit if required) in order to facilitate the following<:
=
- parallel connection of the 2 converters thus providing a double sampling frequency while maintaining an 8 bit resolution.
- series connection of the 2 converters providing a
9 bit resolution while maintaining a 20 MHz
sampling frequency.
CEI
CE2
Bl .... BB in 3rd state
B9 (OVFL) in 3rd .tate
0
0
Ves
Ves
0
t
No
No
1
0
Ves
Ves
1
1
Ves
No
< See application information.
6·12
TYPICAL EVALUATION CIRCUIT
In order to eliminate the almost uncontrollable offsets introduced by the source generator or buffer
amplifier proper, two capacitors parallel mounted
(C,. and C,.) are added in series after the amplifier.
For low frequencies « 1MHz) tantalum capacitor
(C ..) is used as a short-circuit; for higherfrequencies
(> 1 MHz) the ceramic capacitor (C,.) is used as a
The general circuit used for the flash converter in typical
conditions (8 bits, 20 MHz) is represented on figure 1.
• Voltage reference.
Flash converter requiring a positive reference voltage (VREF') ranging from 1.5 V to 3 V (typ: 2 V), the
circuit generates a reference voltage of 2.5 V from
the power supply voltage (+5 V) and a precision regulation diode (lC,).
•
short~circuit.
After these capacitors, a potentiometer (P5) with the
middle point connected to the flash converter input
adds a DC component to the input signal. The signal
thus obtained has an overage value different from
zero,lying between YREF-and YREF+and which can
be converted by the flash converter.
Resistor bridge reference voltages.
The circuit allows to access some particular points on
the resistor bridge. These points correspond to 3/4,
1/2 and 1/4 of the bridge total resistance. This feature enables use of the flash convertor in two ways:
-
in linear operation with these 3 points grounded
by uncoupling capacitors in order to filter disturbances along the bridge (K2, K3 and K4 in position 2),
- in non-linear operation with the following 2 functions:
- improvement in flash converter integral linearity
by forcing the 3 points to their corresponding
voltages (K2, K3 and K4 on poisition 1),
- implementation of a non-linear conversion law
(compression law for instance) in order to better
observe the results of the conversion on one part
only of the transfer characteristic (K2, K3, K4 on
position 1).
• Analog signal.
The input analog signal must be driven by a wide
band buffer amplifier IC.) with a very low output
impedance.
•
Clock signal.
Clock signals are TTL or CMOS signals. The PHASE
command is used to invert (K, on position 1) or not(K,
on position 2) the external signal.
•
Considerations on electrical layout.
A certain number of elementary precautions should
be taken in the electrical layout when using high
frequencies.
The main ones are as follows:
- a ground plane for the components,
- the ground tracks corresponding to the various
signals (clock, input Signal, references) are separated and connected together to a single point,
- a star distributed power supplies(idem for ground)
to avoid any possible loop,
- a maximum capacitive uncoupling as close as
possible to each circuit.
* For typical application circuit, the same surroundings
can be used.
6-13
TYPICAL EVALUATION CIRCUIT
(continued)
j5V
+5V
s~
+5V
Ie,
+SV
6·14
+5V
8 81T RESOLUTION CONFIGURATION 20 MHZ SAMPLING RATE
Component
Valu.
Component
Value
Rl
5.6 K!1(1/4W)
Cl
l00nF63V
R2
3.3 KQ (114 W)
C2
100 nF 63 V
R3
1.2 KQ (1/4 W)
C3
100 nF 63 V
R4
560 Q (1/4 W)
C4
100 nF 63 V
R5
10KQ(1/4W)
C5
100 nF 63 V
R6
2 KQ (1/4 W)
C6
100 nF 63 V
R7
47Q(1/4W)
C7
100 nF 63 V
R8
47Q(1/4W)
C8
l00nF63V
PI
10 KQ (multiturns)
C9
100 nF 63 V
P2
10 KQ (multiturns)
Cl0
100 nF 63 V
P3
10 KQ (multiturns)
Cll
2211F 16 V (Tantalum)
P4
10 KQ (multiturns)
C12
l00nF63V
P5
10 KQ (multiturns)
C13
22I1F 16 V (Tantalum)
ICI
T080136
C14
100 nF 63 V
IC2
TOB 0084
C15
6811F 16 V (Tantalum)
IC3
LH 0002
C16
100 nF 63 V
IC4
TS 8308
6-15
TYPICAL APPLICATION
+5V
+5V
+sv
+sv
~.r
-I.r
ASUP
! - - - - -___ OVFL
..
. .W'
OVFl
OVFL
CLK
.-----_
W~
f-+._-----o-·S
f-++-.----'-'_S,
HJ:r.-
V'N
V AEF +
3AI4
••
.,
••
·0
.,
·3
.,
••
.,
-1"- "nTS8308
·5
-1"- RI'
I - V AEF
.- CEl
I-t+t-Hr-----o- .5
H-HH-I-.-----.. •,
H-HH-I+._---.. ·3
H+iH-f-++-.---" .,
'H"S~
"'ONO
INPUT
·3
.,
rx.'IO
t~~
.I1I
CLOCK
INPUT
.,
.,
CE,
f-++-t-H'-I-l+.....- .,
CLOCK
·5
.,
+]V
I--
I-HANALOG
INPUT
ANALOG
INPUT
I--
-I~v \(HI~v
CE,
PHASE
, OVFL
+svl--
CE,
•• f-
~
V REF +
.,r-
~
3AI4
TS8308
-II- "n
-1"- RI'
.,I-~
L _ _-ICLK
-
__...J
' - - - V,N
., 1-------'
.L
+sv
~"'"""'%""'"'% ~
ADND
~
V REF -
CLK
·3
.,
.,
+5v
A(.,fIIO
#-
',f--'
100nF (63V)
T
DONO
•• f-·51---
t
22
J1F
116 VI
OGNO
"4;
~
.L
T
ADNO~ODNO -'T-"
TYPICAL TS8308 9 BIT RESOLUTION CONFIGURATION
TVPICAL T58308 88IT RESOLUTION CONFIGURATION
20 MHz SAMPLING RATE
40 MHz SAMPLING RATE
6-16
100 nF 163 V)
22 pF (Hi V)
CASE
CB-68
J SUFFIX
C SUFFIX
PSUFFIX
CERDIP PACKAGE
CERAMIC PACKAGE
PLASTIC PACKAGE
0,
j 1)
Nominal dimen$ion
121
True geometrical position
D'N
A51D
'"
OA T A
6-17
NOTES
6·18
ADVANCE INFORMATION
HMOS2
VIDEO SPEED 8-BIT FLASH A-D CONVERTER
The TS8328 is the minimal configuration (20pins)ofthe TS8308 (24pins)
full flash ADC.
This monolithic parallel AID converter is designed for 20MSPS conversion rate. Sampling is performed via a resistor ladder and 256 autobalanced high speed and high accuracy comparators. Conversion is
accomplished within one clock pulse.
A very low input capacitimce (less than 25 pF) and a low input dynamic
range,(1 V possible) allow a very easy drive of the TS8328.
VIDEO SPEED
8 BIT FLASH ADC
CASECB-194
Typical characteristics:
•
•
•
•
•
•
•
•
•
•
•
Single +5 V supply.
±1 LS8 integral non linearity.
±0.5 LSB differential non linearity.
20 MHz sampling rate.
5 MHz input Signal without sample and hold adjunction.
Very low input capacitance (max 25 pF).
All logic inputs and outputs are TIL compatible.
Data output:' 8-bit binary code.
Output buffers for 8-bit data are 3-state type.
Accuracy bener than 6 mY.
20 pins slim line package (0.3 inch).
J SUFFIX
CERDIP PACKAGE
Typical applications:
•
•
•
•
•
•
•
Pulse coding for high energy phYSics experiments.
High speed data acquisition and instrumentation.
TV and video digitizing.
Radar pulse coding.
Medical and industrial imaging.
Optical recognition.
All high speed AID conversion applications where low power and low
cost are required.
~
1
PSUFFIX
PLASTIC PACKAGE
* Ceramic package (C Suffix) is also available.
PIN ASSIGNMENT
BLOCK DIAGRAM
3 RJ4
"2
B1
ASUP
B2
3 R/4
B3
V REF
84
VIN
B5
R/2
B6
ClK
B7
AGND
B8
R/4
Cf
AGNO
OGNO
Analog
Digital
GND
OND
6·19
DGND
+
V REF CE
DSUP
PIN DESCRIPTION
Name
Type
N°
I
Function
Description
I
.L.-
0
Output data
Tristate buffer, outputs
Bl (lSBI
to
BS (MSBI
(MSBI
1
to
8
R/4
I
9
First quarter reference
DGND
I
10
Digital ground
DSUP
I
11
Digital supply
CE
I
12
Tristate command
VREF-
I
13
Lower reference
AGND
I
14
Analog ground
ClK
I
15
Clock input
R/2
I
16
Half reference
VIN
I
17
Signal input
VREF+
I
18
Upper reference
3 R/4
I
19
Third quarter reference
ASUP
I
20
Analog supply
Access to the first quarter reference voltage
Commands the 3 state mode for data lines
CE = "0" : 3 state
CE = "'" : data valid
Access to the lower reference voltage. A voltage source
must be applied (or ground).
The input signal is sampled on the falling edge of the
clock. Output data are changing on the next rising edge.
Access to the half reference voltage.
Access to the upper reference voltage. A voltage source
must be applied.
Access to the third Quarter reference voltage.
MAXIMUM/RATINGS
--I
Rating
I Supply voltage
Storage temperature
Operating temperature
Power supply current
'-----------
Symbol
Value
Unit
VDD
- 0.3 to
+7
V
t Stg
- 60 to 150
'C
toper
- 60to 130
'C
110. Ill. 114. 120
150
rnA
6·20
ElECTRICAL CHARACTERISTICS
Tam b=+2S"C
ASUP=DSUP=+5V
VREF< = + 2 V
VREF-= 0 V
.Min
Symbol
Characteristic
Resolution
linearity error
Differential linearity error
N
ILE
DLE
DE
Quantizing error
Voltage supply
Power dissipation (15 MHz) . Analog supply
Digital supply
FS
Fe
'a
15
VREFVREF+
VREF+ - VREFRREF
0
Aperture jitter
Upper reference voltage
Full scale range
Ladder resistance
5
300
100
logic output low voltage
1
500
V
5.25
mW
mW
MSPS
MHz
ps
V
V
V
0
2
2
650
V DD -15
VO D - .1.5
800
n
25
30
pF
0.4
V
V
V
V
2.4
'(}?,H
IH
V IL
high voltage
Bits
LSB
LSB
LSB
250
VOL
high voltage
Digital input low voltage
Unit
B
20
5
Cin
Input capacitance
Max
+ 112
- 112
4
Maximum sample rate
Reference ladder:
Lower reference voltage
±1
± 1/2
ASUP,DSUP
PDA
PDD
Analog bandwidth
Typ
0.8
2.4
TIMING DIAGRAM
External clock
N+'
Auto-zero N
Output mast.. {
sla~
register
I
Output
data change
l-V
l ~____
X
..J..
I
!x
'---+--j'
Data available
N-'
X,----,N'-----.X
..
N<,
I
.--.
I
I
I
Tp
6-21
N<2
.
I
I
!
=
3J ns (max)
~
~
CASECB-194
CSUFFIX
CERAMIC PACKAGE
J SUFFIX
CERDIP PACKAGE
(I) Nomin.ldlme .... ion
(21 True gIIOnWtIicllpOIition
20.,..
,
DON
C~-194
eEl
D.....1.....
6-22
CHAPTER 7 - INTEGRATED CIRCUITS
SHORT FORM CATALOG
Summary
ASIC
ASIC PRODUcrs SEA-OF-GATES
DATA COMMUNICATION
ETHERNET: LANCE AND SIA
STARLAN: HUB AND STATION
PACKET SWITCHING: X.25 CONTROLLER
2
2
2
TELECOMMUNICATION
CIRCUITS
SWITCHING
CODEC AND FILTERS
TRANSIENT PROTECTION
TELEPHONE SET
DATA CONVERSION
MODEMs
DSP AND ANAWG FRONT END
ISDN
2-3
2
3
3-4
4
5
5
5
MILITARY PRODUCTS
MEMORIES
MICROCOMPONENTS
6-7
MICROPROCESSORS/
MICROCONTROLLERS
MEMORIES
6
DEVEWPMENT & EMULATION
4-BIT MICROPROCESSORS: 2900 FAMILY
8-BIT MICROPROCESSORS: 6800 FAMILY
8-BIT PERIPHERALS:
6800 FAMILY
3880 FAMILY
16-BIT MICROPROCESSORS: 68000 FAMILY
68000 FAMILY
16-BIT PERIPHERALS:
4-BIT MICROCONTROLLERS: 9400 FAMILY
8-BIT MICROCONTROLLERS: 6804 FAMILY
6805 FAMILY
38'l1l FAMILY
6801 FAMILY
STANDARD MICROCONTROLLERS: 38P'l1l (97sxx) FAMILY
GRAPHIC CIRCIDTS
10
11
11
11
12
12
12
13
ZEROPOWER AND TIMEKEEPER RAMs
BATTERY BACK-UP RAMs
STATIC RAMs
VERY FAST STATIC RAMs
CACHE TAGRAMs
BiPORT FIFO.
BiPORT RAMS
NMOS EPROMs
CMOS EPROMs
CMOS EEPROMs
ONE-TIME PROGRAMMABLE PROMs
BIPOLAR PROMs
14
14
14
15
15
15
15
16
16
16
16
17
8
8
9
9
9
10
AUTO-PROTECTED
CONTROLS
DRIVERS (LAMPS, RELAYS, TRIACS, MOTORS... )
SENSORS,DETECTORS
18
18
J-FET OP-AMPs
SINGLE
DUAL
QUAD
18
18
19
BIPOLAR OP-AMPs
SINGLE
DUAL
QUAD
19
19
19
COMPARATORS
SINGLE
DUAL
QUAD
19
20
20
VOLTAGE REGULATORS
FIXED
ADJUSTABLE
WATCHDOG
LOW DROP OUT AUTOMOTIVE
20
20
20
21
POWER-CONTROLLER
SWITCH MODE POWER SUPPLY
21
TIMERS, MISCELLANEOUS
21
MOfOR DRIVERS
STEPPER MOTOR CONTROLLERS
21
AUDIO/VIDEO
COMPONENTS
TELEVISION AND MONITOR DEFLECTION
VIDEO AND SOUND IF CIRCUITS
PERITELEVISION
REMOTE CONTROL-CHANNEL SELECTION
AF AMPLIFIERS
22
22
23
23
23
THOMSON COMPONENTS MOSTEK
ASIC PRODUCTS
ISB 12000 SERIES
FEATURES
• 1.2 micron HCMOS process, poly silicide gates, 2-layer metal with
Titanium barriers and hermetic silicon nitride passivation.
·2-input NAND gate delay=0.3ns, Fanout=2, TA =25 'C, Voo=5V.
• Channeliess architecture utilizing transistor gate isolation.
• Gate count ranging from 8,000 to 128,000.
• Extensive macrocell, macrofunction and megacelilibrary elements
available.
• Full function TIL and CMOS I/O cells.
• Configurable drive up to 8 mA with slew rate control. Buffers may
be paralleled to generate 16 mA of source/sink drive.
• Augmented metal grid to maximize power distribution.
• VI\X based design system, interfaces from multiple workstations.
• Latch-up trigger current > I A. ESD protection > 2000 V. Short circuit protection.
• ISB054 evaluation device available.
• Full military capability.
• Broad ceramic and plastiC package offering.
PRODUCT OUTLINE
DEVICE NUMBER
ISB12008
ISB12011
ISB12015
ISB12020
ISB12025
ISB12038
ISB12054
ISB12076
ISB12103
ISB12128
INTERNAL
CELLS
GATE (1)
COMPLEXITY
ESTIMATED (2)
USEABLE GATES
20,000
28,800
39,200
51,200
64,800
96,800
135,200
192,200
259,200
320,000
8,000
11,520
15,680
20,480
25,920
38,720
54,080
76,880
103,680
128,000
3,000
4,500
6,000
8,000
10,000
15,000
20,000
30,000
40,000
50,000
TOTAL (3)
DEVICE PADS
MAXIMUM
I/O
88
104
120
136
152
184
216
256
296
328
76
92
108
120
136
164
200
232
256 (4)
256 (4)
NOTES:
1. A factor of 2.5 is used to derive gate complexity from raw celis.
2. A conservative routing efficiency of 40% is quoted. This number will vary depending on the design.
3. Eight dedicated VddNss pads. I/O pads may be reconfigured for additional VddNss pads.
4. I/O signals currently limited to 256 by tester constraints.
ABSOWTE MAXIMUM RATINGS (REFERENCE TO VSS)
SYMBOL
PARAMETER
VAWE
UNIT
DC SUPPLY VOLTAGE
INPUT VOLTAGE
DC INPUT CURRENT
STORAGE TEMP. RANGE
(CERAMIC)
STORAGE TEMP. RANGE
(PLASTIC)
-0.5 to + 7.0
-0.5 to VDO +0.5
±20
-65 to 150
V
V
mA
'C
-40 to 125
'C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
DC SUPPLY
OPERATING
OPERATING
OPERATING
VOLTAGE
AMBIENT (MILITARY)
AMBIENT (INDUSTRIAL)
AMBIENT (COMMERCIAL)
VAWE
UNIT
+3 to + 6
-55 to +125
-40 to +85
o to 70
V
'C
'C
OC
PACKAGE SELECTOR GUIDE FOR THE ISB 12000 SERIES
DEVICE
NUMBER
TOTAL (3)
DEVICE PADS
84
ISB 12008
ISB 12011
88
104
ISB 12015
120
ISB 12020
136
ISB 12025
ISBM 12038
152
184
ISB 12054
216
ISB 12076
256
ISB 12103
296
ISB 12128
328
X
X
X
X
CERAMIC AND PLASTIC
PfN GRID ARRAY
120
180
224
X
X
X
X
X
X
X
X
X
X
296
PLASTIC AND CERAMIC
CHIP CARRIERS
68
84
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PLASTIC QUAD
FLAT PACK
100
132
X
X
X
X
X
X
X
THOMSON COMPONENTS MOSTEK
TELECOMMUNICATIONS/DATA
PART NO.
TECHNOLOGY
COMMUNIIC~
FUNCTION
SUPPLY
PINS/PACKAGE
ETHERNET
MK68590
NMOS
Local Area Network Controller for Ethernet (LANCE).
5V
48 DIP
MK68591
Bipolar
Serial Interface Adapter (SIA) with 10 Mbps Manchester
encoder/decoder for Ethernet
5V
24-DIP
600 mil width
MK68592
Bipolar
Serial Interface Adapter (SIA) same as 68591. but in smaller
package
5V
24 DIP
300 MIL width
STARLAN
MK5030
CMOS
StarLAN Hub - 12 pori. cascadable (Demo board available)
5V
48 DIP
MK5033
CMOS
General purpose std/dill. Manchester encoder/decoder
5V
28 DIP
MK5035
CMOS
StarLAN Station
5V
20 DIP
MK50351
CMOS
StarLAN Station for use with variable bit rate controller
5V
20 DIP
MK5025
CMOS
CCITT. X.25 LAPB/LAPD controller
1980 & 1984 specification compatible
5V
48 DIP
MK5027'
CMOS
CCITT. Common Channel Signalling System
Number Seven (SS7)
5V
48 DIP
PACKET SWITCHING
Switching connection and concentration
PART NO.
EF73321
Subscriber Board:
PART NO.
TECHNOLOGY
NMOS
FUNCTION
PCM clock recovery and transceiver.
SUPPLY
+
5
PINS
16
Single channel CODEC plus filters
TECHNOLOGY
FUNCTION
SUPPLY
PINS
± 5V
16
ETC5057
CMOS
Single channel A-law serial COFIDEC
compatible with NSC TP3057
ETC5054
CMOS
Single channel wlaw serial COFIDEC
compatible with NSC TP3054
± 5V
16
ETC5067
CMOS
Single channel A-law serial COFIDEC
with push-pull power amplifiers
± 5V
20
ETC5064
CMOS
Single channel wlaw serial COFIDEC
with push-pull power amplifiers
± 5V
20
TS5070'
TS5071 ,
CMOS
2nd generation COFIDEC
programmable functions and direct
interface to SLIC
± 5V
20
• To be Introduced
2
THOMSON COMPONENTS MOSTEK
TELECOMMUNICATIONS/DATA COMMUNICATIONS
Subscriber Board (Continued)
PART NO.
ETC5040
PART NO.
TECHNOLOGY
CMOS
FUNCTION
PCM filters for use with MK5116 series,
compatible with TP3040
TECHNOLOGY
SUPPLY
PINS
± 5V
16
PACKAGE
FUNCTION
TPA62
To
TPA270
Bipolar
Bidirectional transient protection breakdown voltage
62V ~ TPA62
270V ~ TPA270
Max Power ~ 1.3W
Axial Leads
F126
TPB62
To
TPB270
Bipolar
Bidirectional transient protection breakdown voltage
62V ~ TPB62
270V ~ TPB270
Max Power ~ 5W
Axial Leads
CB429
TPC62
To
TPC270
Bipolar
Dual bidirectional transient protection breakdown voltage
62V ~ TPC62
270V ~ TPC270
Max Power ~ 20W
PART NO.
TECHNOLOGY
TEA3046
Bipolar
To 220
SUPPLY
PINS
Telephone transmission and DMTF Dialer
Line supply
28
FUNCTION
TEA7031
Bipolar
Telephone loudspeaker amplifier.
Line supply
28
TEA7531
Bipolar
Telephone loudspeaker amplifier
Line supply
16
CMOS
DTMF generator for binary coded hexadecimal data
8 pin package with serial input port
+3 to 5.25V
EFG71891
3
14
8
THOMSON COMPONENTS MOSTEK
TELECOMMUNICATIONS/DATA COMMUNICATIONS
PART NO.
*
U
TECHNOLOGY
FUNCTION
SUPPLY
PINS
2.5V to 6.5V
18
2.5V to 6.5V
18
2.5V to 6V
20
+2.5V to +6.0V
18
MK5370
CMOS
TonePulseN switchable dialer,
with last # redial
MK5371
CMOS
TonePulseN switchable dialer,
with BCD input and last # redial
MK53721'
CMOS
TonePulseN WORLD DIALERN with redial
and options for various countries standards
MK5375
CMOS
TonePulseN switchable dialer
with 10 number memory
MK5376
CMOS
TonePulse™ switchable dialer with 10 number
memory for European market
2.5V to 6.0V
24
MK5380
CMOS
Low cost tone only dialer
2.5V to 10.0V
16
MK53731
CMOS
Full feature TonePulseN switchable dialer
with last number redial
2.5V to
ov
18
MK53761'
CMOS
Full feature TonePulseN repertory dialer
with 10 number memory
2.5V to 6V
18
MK53762'
CMOS
TonePulseN repertory dialer. 10 number
memory uses one key per number location
for recall
2.5V to 6V
20
MK53763"
CMOS
TonePulseN WORLD DIALERN with 13
number memory, single key auto-dialing,
and various country options.
2.5 V to 6V
24
300 MIL
width
To be Introduced In 1Q'88
To be Introduced In 30'88
PART NO.
TS8328
FUNCTION
SAMPLING
RATE
SUPPLY
PINS
8-bit flash ND Converter (min. version of TS8308)
20 MHz
+5V
20
4
THOMSON COMPONENTS MOSTEK
PART NO.
TECHNOLOGY
FUNCTION
BAUD RATE
SUPPLY
EFG7515
CMOS
Monochip OPSK modem. CCITT-V22
and BELL212A (Oemo board available).
TDA7868
Bipolar
Direct connect circuit for modem interfaces to
phone line.
Provides line adaptation and ring detection.
TS68930
HMOS2
High performance (10 MIPS, 160 ns cycle)
Oigital Signal Processor (Emulator board
available)
TS68931
HMOS2
External ROM version of TS68930
TS68950
CMOS
Modem analog front end transmitter
Y.22, V32 up to 19200 bps
±5V
TS68951
CMOS
Modem analog front end receiver
Y.22, V32 up to 19200 bps
±5V
TS68952
CMOS
Modem analog front end XMIT/RCVR
Clock generator
Y.22, V32 up to 19200 bps
±5V
SUPPLY
PINS
PART NO.
TECHNOLOGY
FUNCTION
Tx: 1200/300
Rx: 1200/300
Full Ouplex
±5V
NA
Telephone
Line Supply
25 MHz
5V
25 MHz
5V
TBO'
CMOS
ISON transceiver "S" interface device
+5V
20
TBO'
CMOS
HOLC controller
+5V
28
TBO'
CMOS
U interface
+5V
TBO
TBO'
CMOS
ISON power supply
Phone line
18
TBO'
CMOS
Telephone set COFIOEC
Phone line
TBO
• lb be announced
5
THOMSON COMPONENTS MOSTEK
MILITARY PRODUCTS
PART NO.
ACCESS
ORG.
DESCRIPTION
GRADE
TIME
MKB4116
MKJ4116
MKB/J4564
MKBlJ45F56
MKB41H68
MKB41H87
MKB48H64
MKBlJ4501
MKB4505
PART NO.
16K
16K
64K
256K
4K
64K
8K
512
1K
DRAM
DRAM
DRAM
DRAM
CMOS SRAM
CMOS SRAM
CMOS SRAM
Biport FIFO
Biport FIFO
X 1
X 1
X 1
X 1
X 4
X 1
X 8
X 9
X
883 (Last Time Buy)
JAN (Last Time Buy)
8831DESC/JAN
8831DESC/JAN
8831DESC
To be intro.
To be intro.
8831JAN
To be intro.
150,200,250 ns
200,250 ns
120, 150, 200 ns
100, 120, 150 ns
25,35,45 ns
35,45, 55 ns
35,45, 55 ns
65,80, 100, 120, 150,200 ns
35, 45, 55 ns
5
FUNCTION
ALT. SOURCE
PINS
GRADE
TS2901BMCBlB
TS2901CMCBlB
4-bit bipolar microprocessor slice
Improved speed 4 Bit microprocessor slice
Am2901B
AM2901C
40
40
883
883
TS2910MCBlB
Microprogram controlier
Am2910
40
883
TS2911AMCB/B
Microprogram sequencer
Am2911A
20
883
TS2914MCB/B
Vectored priority interrupt controlier
Am2914
40
883
TS2915AMCBlB
Quad 3·State Bus Transceiver with interface logic
Am2915A
24
883
TS2917AMCBlB
Quad 3·State Bus Transceiver with interface logic
Am2917A
20
883
TS2918MCBlB
Quad D register with standard and 30State Outputs
Am2918
16
883
TS2919MCBlB
Quad D register with Dual 30State Outputs
Am2919
20
883
6
THOMSON COMPONENTS MOSTEK
TECHNOLOGY
CLOCK FREQ. (MHz)
GRADE
EF6800MCB/B
PART NO.
NMOS
1,1.5
883
EF6802MCB/B
NMOS
1,1.5
883
EF6809MCB/B
HMOS
1,1.5
883
EF6821 MCB/B
NMOS
1,1.5
883
EF6840MCB/B
NMOS
1,1.5
883
EF6850MCB/B
NMOS
1,1.5
883
EF6852MCB/B
NMOS
1,1.5
883
EF6854MCB/B
NMOS
1,1.5
883
EF6810MCB/B
NMOS
1,1.5
883
Available In ceramic and cerdlp OIL packages as well 8S ceramic chip-carriers.
PART NO.
TECHNOLOGY
CLOCK FREQ. (MHz)
GRADE
M KB/J68000P
HMOS
4,6,8,10,12
883/DESCIJAN
MKB68901P
TS68000MCB/C
TS68008MCB/B
NMOS
HMOS
HMOS
4,5
8,10,12
8,10,12
883
883
883
8,10
883
Also available In ceramic OIL packages. pin-grid arrays and ceramic or chip-carrier.
TS68230MCB/B
HMOS
Available in ceramic OIL package and ceramic chip-carrier.
7
THOMSON COMPONENTS MOSTEK
PART NO.
FUNCTION
TST IN48
General purpose development tool for 4 and 8 bit micros
EFT-MU94
ET9400 family (CMOS and NMOS) emulator
EFT-MUP4
EFT-MUP5
EF6804P2/J2, EF68HC04P3 emulator
EF6805P2/P4/P6, EF6805R2/U2, EF6805R3/U3 emulator
FUNCTION
ALT. SOURCE
PINS
TS2901B
TS2901C
4-bit bipolar microprocessor slice
Improved speed 4 Bit microprocessor slice
Am2901B
Am2901C
40
40
TS2902A
High speed look-ahead carry generator
Am2902A'
16
TS2909A
Microprogram sequencer
Am2909A
28
TS2910
Microprogram controller
Am2910
40
TS2911A
Microprogram sequencer
Am2911A
20
TS2914
Vectored priority interrupt controller
Am2914
40
TS2915A
Quad 3-State Bus Transceiver with interface logic
Am2915A
24
TS2917A
Quad 3-State Bus Transceiver with interface logic
Am2917A
20
TS2918
Quad D register with standard and 3-State Outputs
Am2918
16
TS2919
Quad D register with Dual 3-State Outputs
Am2919
20
PART NO.
8
THOMSON COMPONENTS MOSTEK
MICROPROCESSORS/MICROCONTROLLERS
PART NO.
TECHNOLOGY
CLOCK FREQ. (MHz)
FEATURES
ALT. SOURCE
EF6802
EF68A02
EF68802
NMOS
1
1.5
2
6800 MPU, 128 bytes of RAM,
on-chip oscillator
MC6802
MC68A02
MC68802
40
EF6803
EF68A03
EF68803
HMOS
1
1.5
2
8-bit microp., 16-bit add. bus,
Multiply, RAM: 128b, SCI-Timer
MC6803
MC68A03
MC68803
40
EF6803U4
EF68A03U4
.EF68803U4
HMOS
1
1.5
2
Same as above but:
RAM: 192b, enhanced timer
MC6803U4
MC68A03U4
MC68803U4
40
EF6809
EF68A09
EF68809
HMOS
1
1.5
2
High performance 8-bit MPU,
6800 compatible, On-chip oscillator
MC6809
MC68A09
MC68809
40
EF6809E
EF68A09E
EF68809E
HMOS
1
1.5
2
High performance 8·bit MPU,
6800 compatible, External clock
MC6809E
MC68A09E
MC68809E
40
TS68008·8
TS68008-10
TS68008-12
HMOS
8
10
12.5
16·bit microprocessor
with 8-bit data bus
MC68008-8
MC68008-10
MC68008-12
40
PINS
Available In plastic, ceramic, canUp OIL packages and plastic or ceramic chip-carriers.
PART NO.
TECHNOLOGY
CLOCK FREQ. (MHz)
EF6821
EF68A21
EF68821
NMOS
1
1.5
EF6840
EF68A40
EF68840
NMOS
1
1.5
2
EF6850
EF68A50
EF68850
NMOS
1
1.5
2
EF6854
EF68A54
EF68854
NMOS
1
1.5
2
PART NO.
TECHNOLOGY
CLOCK FREQ. (MHz)
NMOS
4
MK3801-04
MK3801-06
FEATURES
PINS
Peripheral Interface Adapter (PIA)
40
Programmable Timer Module (PTM)
MC6840
MC68A40
MC68840
28
MC6850
MC68A50
MC68850
24
MC6854
MC68A54
MC68854
28
2
6
ALT. SOURCE
MC6821
MC68A21
MC68821
Asynchronous Communication
Interface Adapter (ACIA)
Advanced Data-Link
Controlier (ADLC)
FEATURES
Serial timer interrupt (STI)
ALT. SOURCE
PINS
40
Available In plastic OIL package.
* To be Introduced
9
THOMSON COMPONENTS MOSTEK
PART NO.
TS6800()'8
TS6800()'10
TS68000·12
TS68000·16
TS68008-8
TS68008·10
TS68008·12
HMOS
HMOS
8
10
12.5
16
16·bit microprocessor
with 32·bit internal structure
8
10
12.5
TS68000 8-bit bus version
.. To be Introduced
PART NO.
ALT. SOURCE
PINS
MC68000·8
MC6800()'10
MC68000·12
64
MC68008·8
MC68008-10
MC68008-12
48
Also available In ceramic and plastic DIL packages. pln.grld arrays and ceramic or plastic chip-carrier.
TECHNOLOGY CLOCK FREQ. (MHz)
MK68230-8
MK6823()'10
HMOS
8
10
MK68564
HMOS
4,5
TS68HC901
FEATURES
TECHNOLOGY CLOCK FREQ. (MHz)
FEATURES
Parallel interfacellimer
ALT. SOURCE
MC68230·8
MC68230·10
PINS
48
Serial I/O
48
CMOS multifunction
peripheral
48
HCMOS
4,5,8
MK68901
HMOS
4,5
TS68930
HMOS2
6.25
High performance digital
signal processor with
internal program ROM
160 ~s cycle time,
2 x 128 x 16·bit internal RAM
48
TS68931
HMOS2
6.25
ROMLESS version of TS68930
64K addressing range
84
MK68590
NMOS
10
Local Area Network Controller for
Ethernet (LANCE), cheapernet
MK68591
Bip
10
Serial Interface Adapler (SIA) with
10 Mb/s Manchester encoder/decoder
for Ethernet, cheapernet, etc.
MK68592
Bip
10
Serial Interface Adapter (SIA) same as
68591, but in smaller package
Multifunction
peripheral
Available In plastic and ceramic DIL packages, plaatlc chip carrier packages.
10
MC68901
AM7990
48
48 DIP
24 DIP
600 MIL width
AM7992
24 DIP
300 MIL width
THOMSON COMPONENTS MOSTEK
PART NO.
TECHNOLOGY
ROM x 8
RAM x 4
1/0
LINES
ETL9410/11/13
ETC9410111113
NMOS Low Power
CMOS
512
512
32
32
ET9420121122
ETL9420/21122
ETC9420121122
NMOS
NMOS Low Power
CMOS
1024
1024
1024
64
64
64
23119115
ETL9444145
ETC9444145
NMOS Low Power
CMOS
2048
2048
128
128
23119
INSTRUCTION
CYCLE (~s)
SUPPL)
(V)
15-40
4-DC
4.5-6.3
2.4-55
COP410U11/13L
COP410CJ11CI13C
4-10
15-40
4-DC
4.5-6.3
4.5-6.0
2.4-5.5
COP420/21122
28124120
COP420U21U22L
28124/20
COP424C125C/26C
28124120
15-40
4-DC
45-6.3
2.4-5.5
COP444U45L
28124
28124
19116115
ALT. SOURCE
COP444C/45C
PINS
24/20
24120
·To be Introduced
Common features: software compatible (same Instruction 881). Pin compaUble. Three levels of stack. 8 bidirectional tristate 1/0. Ser1a1 1/0 and Internal counter, Interrupt programmable I/O. All
devices are whh plastic package (OIL) and also sOle and PL.CC for some devices. Available with extended temperature range (-40"C to +85"C): E193XX or ETC93XX.
PART NO.
EF6804P2
EF6804J2
EF68HC04J3'
EF68HC04P3
TECHNOLOGY
ROM X 8
RAM X 8
1/0
ALT. SOURCE
PINS
HMOS
HMOS
HCMOS
HCMOS
1024
1024
2048
2048
32
32
124
124
20
12
12
20
MC6804P2
MC6804J2
MC68HC04J3
MC68HC04P3
28
20
20
28
Available In plastic, ceramic, OIL packages or chlp-camers. All software compatible. Timer.
ROM X 8
RAM X 8
1/0
EF6805P2
PART NO.
TECHNOLOGY
HMOS
1100
64
20
EF6805P6
EF6805R2
EF6805R3
HMOS
HMOS
HMOS
1796
2048
64
64
112
20
32
32
EF6805T2
EF6805U2
EF6805U3
HMOS
HMOS
HMOS
2508
2048
64
64
112
19
32
32
~
~
FEATURES
AID Converter
AID Converter
On-chip PLL
Avallabfe In plastic, C8l8mic, OIL packages or chlp-carrler. Ext. temp range (-40oc, +85"C). All software compatible. InteRllpt capabilities. Timer.
11
ALT. SOURCE
MC6805P2HD6805S1
MC6805P6
MC6805R2
MC6805R3HD6805WO
MC6805T2
MC6805U2
MC6805U3
PINS
28
28
40
40
28
40
40
THOMSON COMPONENTS MOSTEK
PART NO.
TECHNOLOGY
MK2870/10
MK3870/10
MK3870/20
MK3870/22
MK3870/40
MK3870/42
MK3873/22
MK3875/22
MK3875/42
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
NMOS
ROM
x8
RAM
1024
1024
2048
2048
4096
4032
2048
2048
4032
x8
FEATURES
1/0
64
64
64
128
64
128
128
128
128
20
32
32
32
32
32
29
29
29
51. SO, SLCK
51, SO, SLCK
51, SO, SLCK
ALT. SOURCE
M2872
M3872
M3870.2
M3872
M3872
M3872
M38730,33
M3875
M3875
PINS
28
40
40
40
40
40
40
40
40
Common feature.: Software compatible (ume Inltructlon let), tlmar, Interrupt cap.blll...., parallel 1/0 (TTL compallbla).
All device. are with pintle or ceramic packag. (OIL).
Allo IIYfIliable with extended temperature ranga.
PART NO.
TECHNOLOGY
ROM
x8
RAM x 8
1/0
FEATURES
EF6801
HMOS
2048
128
31
SCI, Timer, stand·by RAM
EF6801·U4
HMOS
4096
192
31
Enhanced SCI and Timer
Stand-by RAM
Common featurea: 8 x 8 multiply Instruction. Timer. 84K byte add,...lng apace. S.rlal
communlcatl~n
ALT. SOURCE
MC6801
H06801-S0
MC6801-U4
H06801-VO
PINS
40
40
Interface. All device' available In DIL ceramic or pl ••tlc package and pl••tlc
chip carrlar (PLCC)/-40°C to +85°C).
PART NO.
TECHNOLOGY
ADDRESSABLE
ROM x 8
ON CHIP
RAM x 8
1/0
FEATURES
SUPPORT
PINS
MK97400
MK97403
MK97410
NMOS
NMOS
NMOS
4096
4096
4096
128
128
128
32
32
32
TIL Ports
TIL Ports
Open drain ports
4K EPROM
4K EPROM
4K EPROM
40 (24/28)
40 (24/28)
40 (24/28)
MK97501
MK97521
NMOS
NMOS
65472
65472
128
128
32
32
TIL ports
Open drain and
TIL ports
8K EPROM
8K EPROM
40 (28)
40 (28)
Common fealures: EPROM verelon of MK3870, piggyback ceramic package accept. 24 or 28 plna memorle., pin to pin compallble with 3870. Available In extended temperature rangl.
12
THOMSON COMPONENTS MOSTEK
ICROPROCESSORS/MICROCONTROLLERS
PART NO.
TECHNOLOGY
EF9345
HMOS
EF9367
HMOS
FEATURES
ALT. SOURCE
Single chip alphanumeric and semigraphic display processor
25/21 rows of 40 or 80 characters. Color. 8IW
Graphic display processor. Up to 512
x
1024 interlaced
PINS
40
40
50/60 Hz - Color, 8IW
x
EF9369
HMOS
Palette circuit 16
EF9370
HMOS
Enhanced version of 9369
4096 compatible with all display circuits
28
TS68483
HMOS
High performance drawing processor
68
TS68493
HMOS
Enhanced version of 68483
68
TS68494
HMOS
Palette circuit 256
x
4096
28
48
... Alternate source to be announced.
13
THOMSON COMPONENTS MOSTEK
MEMORIES
DEVICE
ORGANIZATION
ACCESS
TIME
ICC
ISB
MK48Z02
2K x 8
SOmA
1 mA
MK48Z12
2K x 8
MK48Z08
MK48Z09
8K x 8
8K x 8
120,150,200,
250 ns
120,150,200,
250 ns
150,200,250 ns
150,200,250 ns
MK48Z18
MK48Z19
8K x 8
8K x 8
MK48Z32
32K x 8
FEATURES
ZEROPOWER
=
80mA
1 mA
Vee
80 mA
80 mA
1 mA
1 mA
150,200,250 ns
150,200,250 ns
SO mA
SO mA
1 mA
1 mA
150,200 ns
85 mA
10 mA
ZEROPOWER
Power Fail
Interrupt Output
Vee = ±10%
Power Fail
Interrupt Output
Vee = ±10%
ZEROPOWER
±10%
TEMP
RANGE
PINS
PKGS
C,I
24
B
C,I
24
B
C
C
28
28
B
B
C
C
28
28
B
B
C
28
B
TEMP
RANGE
PINS
PKGS
Cammon Features: Integral lithium battery tor data retention In the ab8ence of power. U.L. recognized versions available; designated MK48ZxxBU.
DEVICE
ORGANIZATION
MK4lIT02
2K
x
8
MK48T12
2K
x
8
ACCESS
TIME
ICC
ISB
120,150,200
250 ns
120,150,200,
250 ns
80 mA
3mA
TIMEKEEPER
C
24
B
80mA
3mA
Vee = ±10%
C
24
B
FEATURES
Common Featuru: CMOS SRAYS containing real time clock, crystal. and lithium battery In a single package. U.L. recognized version. available; designated MK481kxBU.
DEVtCE
MK48C02A
DEVICE
E12147H
ORGANIZATION
ACCESS
TIME
ICC
IBAT
TEMP
RANGE
PINS
PKGS
2K x 8
150,200,250 ns
SOmA
1pA
C
28
N
ORGANIZATION
ACCESS
TIME
ICC
TEMP
RANGE
PINS
PKGS
35,55 ns
1SO mA
C
18
4K
x1
• lb be Introduced
14
30 mA
THOMSON COMPONENTS MOSTEK
MEMORIES
DEVICE
MK41H66
MK41H67
MK41H68
MK41H69
MK41H79
MK48H64'
MK41H87'
DEVICE
ORGANIZATION
16K x
16K x
4K x
4K x
4K x
8K x
64K x
1
1
4
4
4
8
1
ACCESS
TIME
20,25,35
20,25,35
20,25,35
20,25,35
20,25,35
35,45,55
35,45,55
ns
ns
ns
ns
ns
ns
ns
ICC
ISB
120 mA
120 mA
120 mA
120 mA
120 mA
90 mA
60 mA
ORGANIZATION
ACCESS
TIME
ICC
MK41H80
4K x 4
20,25,35 ns
120 mA
MK4202
2K x 20
20,25 ns
200 mA
MK48H74'
8K x 8
35,45,55 ns
MK4850'
512 x 9
20 ns
95 mA
MK4852'
2K x 9
20 ns
125 rnA
DEVICE
MK4501
DESCRIPTION
BiPort FIFO 512 x 9
MK4503
BiPort FIFO 2K x 9
MK4505M
MK4505S
Clocked FIFO lK x 5
Clocked FIFO lK x 5
(3 State Outputs)
(64 x 5) x 2
(BiDirectional FIFO)
MK45264/5
50~
50~
10~
50~
ISB
FEATURES
TEMP
RANGE
PINS
PKGS
C
C
C
C
C
C
C
20
20
20
20
22
28
24
N
N
N
N
N
N
N
TEMP
RANGE
PINS
PKGS
Comparator
C
22
N
Comparator
C
68
K
Comparator
C
28
N
Comparator
C
24
N
Comparator
C
28
N
Fast CS Access
CE Power Down
CE Power Down
Fast CS Access
CE/OE/ClR
~, E2 Power Down
~ Power Down
FEATURES
Cache
w/ClR
Cache
w/ClR
Cache
w/ClR
Cache
w/ClR
Cache
w/ClR
ACCESS
TIME
CYCLE
TIME
ICC
TEMP
RANGE
PINS
PKGS
65,80,100,120,
150,200 ns
65,80,100,120,
150,200 ns
15,20,25 ns
15,20,25 ns
80,100,120,140,
175,235 ns
80,100,120,140,
175,235 ns
25,33,50 ns
25,33,50 ns
80 mA
C
28,32
N,K
120 mA
C
28,32
N,K
100 mA
100 mA
C
C
24
20
N
N
50 ns
60 ns
60 mA
C
24
N
DEVICE
DESCRIPTION
ACCESS
TIME
CYCLE
TIME
ICC
TEMP
RANGE
PINS
PKGS
MK4511
MK4532'
BiPort RAM 512 x 9
Dual Port RAM 2K x 8
(Master)
Dual Port RAM 2K x 8
(Master)
Dual Port RAM 2K x 8
(Slave)
Dual Port RAM 2K x 8
(Slave)
16K Dual Port RAM
w/x8 and x16 Ports
x8 Port ND Multiplexed
16K Dual Port RAM
w/x8 and x16 Ports
120,150,200 ns
55,70,90 ns
150,190,250 ns
55,70,90 ns
50 mA
60 mA
C
C
28,32
48,52
N
N,K
30,35,45 ns
30,35,45 ns
60 mA
C
48,52
N,K
55,70,90 ns
55,70,90 ns
60 mA
C
48,52
N,K
30,35,45 ns
30,35,45 ns
60 mA
C
48,52
N,K
60,70 ns
60,70 ns
60 mA
C
68
K
60,70 ns
60,70 ns
60 mA
C
68
K
MK4532A'
MK4542'
MK4542A'
MK45AMS'
MK45DP8'
• To be Introduced
Package Type: J CERDIP
N Plastic DIP
K Plastic Leadless Chip Carrier
E Ceramic Leadless Chip Carrier
B Plastic DIP wlTop Hat
Temperature Range: C oOC to +70°C
I
15
-40"C to +85"C
THOMSON COMPONENTS MOSTEK
MEMORIES
DEVICE
ORGANIZATION
ET2716
2K x 8
DEVICE
ORGANIZATION
ETC2716
ETC2732
TS27C64
TS27C256'
TS27C1024'
TS27C1001'
2K x 8
4K x 8
8K X 8
32K X 8
64K X 16
128K X 8
ACCESS
TIME
CONSUMPTION
TEMP
RANGE
PINS
350,450 ns
5251132 mW
C
24
ACCESS
TIME
CONSUMPTION
TEMP
RANGE
PINS
450,550 ns
350,450,550 ns
250,300 ns
150,200,250,300 ns
120,150,200,250 ns
120,150,200,250 ns
25/0.5 mW
25/0.5 mW
150/2.5 mW
200/2.5 mW
250/5.0 mW
250/5.0 mW
C,E,V
C,E,V
C,V
C,V
C,V
C,V
24
24
28
28
40
32
DEVICE
ORGANIZATION
TS59CW
64K X 16 or 128K X 8
64K X 16 or 128K X 8
2K X 8
2K X 8
8K X 8
TS93C46'
TS28C16N
TS28C17N
TS28C64'
DEVICE
TS27C64
TS27C256'
TS27C1024'
TS27C1001'
ORGANIZATION
8K x 8
32K x 8
64K x 16
128K x 8
ACCESS
TIME
CONSUMPTION
15/.5 mW
15/.5 mW
150 ns
150 ns
150,200,250 ns
1251.5 mW
125/.5 mW
150/.5 mW
CONSUMPTION
ACCESS
TIME
150,200,250,300
150,200,250,300
120,150,200,250
120,150,200,250
ns
ns
ns
ns
150/2.5
200/2.5
250/5.0
250/5.0
• To be Introduced
mW
mW
mW
mW
DATA
RETENTION
10
10
10
10
10
yrs
yrs
yrs
yrs
yrs
TEMP
RANGE
PINS
C
C
C
C
C
8
8
24
24
28
TEMP
RANGE
PINS
PKGS
C,V,T
C,V,T
C,V
C,V
28,32
28,32
40,44
32
p,FN
p,FN
p,FN
Package Type: P
FN
Temperature Range: C
E
V
16
P
Plastic DIP
Plastic Leadless Chip Carrier
0"0 to +70"C
-25OC to +70"0
-40"C to +65°C
-40~C to +105"0
THOMSON COMPONENTS MOSTEK
PART NO.
TECHNOLOGY
TS71181A'
TS71181B'
TS71181C'
TS71281A'
TS71281B'
TS71281C'
H
H
H
H
H
H
TS71191A
TS71191B
TS71191C
TS71191D
TS71291C
TS712910
Advanced
Advanced
Advanced
Advanced
H BIP II
H BIP II
T571321B'
T571321C'
TS71641'
ORGANIZATION
OUTPUT
ACCESS TIME
(IACC max)
SUPPLY
PINS
1K
1K
1K
1K
1K
1K
x
x
x
x
x
x
8
8
8
8
8
8
3-state
3-state
3-state
3-state
3-state
3-state
45
35
25
45
35
25
ns
ns
ns
ns
ns
ns
+5V
+5V
+5V
+5V
+5V
+5V
24
24
24
24 (Slim line)
24 (Slim line)
24 (Slim line)
2K
2K
2K
2K
2K
2K
x
x
x
x
x
x
8
8
8
8
8
8
3-state
3-state
3-state
3-state
3-state
3-state
60
45
35
25
35
25
ns
ns
ns
ns
ns
ns
+5V
+5V
+5V
+5V
+5V
+5V
24
24
24
24
24 (Slim line)
24 (Slim line)
H BIP II
H BIP II
4K x 8
4K x B
3-state
3-state
55 ns
45 ns
+5V
+5V
24
24
H BIP II
8K x B
3-state
55 ns
+5V
24
BIP
BIP
BIP
BIP
BIP
BIP
II
II
II
II
II
II
TIL
TIL
TIL
TIL
• To be Introduced
17
THOMSON COMPONENTS MOSTEK
PART NO.
TDE1607
TDE1647
TDE1737
TDE1747
TDE1767,A
TDF1778
TDF1779,A
TDE1787,A
TDE1798
TDE3207
TDE1780'
PART NO.
LM135 (235-335,A)
TDA0159A
TDE0160
TDA0161
TDA0162
PART NO.
TL061
TL071
TL081
LF155,A(255,A·355,A)
LF156,A(256,A·356,A)
LF157,A(257,A-357,A)
PART NO.
TL062
TL072
TL082
FEATURES
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
Vee
= 36V, lOUT
= 45V, lOUT
= 45V, lOUT
= 45V, lOUT
= 45V, lOUT
= 32V, lOUT
= 35V, lOUT
= 60V, lOUT
= 35V, lOUT
= 36V, lOUT
= 35V, lOUT
PACKAGES (2)
I
I
I
I
I
F
F
I
I
I
I
CM,DP
CM, DP, FP
CM, DP, FP
CM, DP, FP
DP
SP
SP
DP
DP
DP, FP
DP, SP
= 0.3 A
= 0.3 A
= 0.3 A
= 0.3 A
= 0.5 A
= 2 A (Dual)
= 2 A (Dual)
= 0.3 A
= 0.5 A
= 0.15 A
= 2 A (Dual)
FEATURES
Precision
Proximity
Proximity
Proximity
Proximity
TEMPERATURE
RANGE (0)
temp. sensors
detector
detector
detector
detector
FEATURES
TEMPERATURE
RANGE (1)
PACKAGES (2)
C, I, M
I
I
I
I
Z
FP, DP
FP, DP
CM, DP, FP
CM, DP, FP
TEMPERATURE
RANGE (1)
PACKAGES (2)
C, I, M
C, I, M
C, I, M
C,I,M
C,I,M
C,I,M
DP, FP, DG, GC, H
DP, FP, DG, GC, H
DP, FP, DG, GC, H
DP, DG, GC, H
DP, DG, GC, H
DP, DG, GC, H
TEMPERATURE
RANGE (1)
PACKAGES (2)
Low noise
C, I, M
C, I, M
Standard
C, I, M
DP, FP, DG, GC, H
DP, FP, DG, GC, H
DP, FP, DG, GC, H
Low power
Low noise
Standard
Low power
High speed
Very high speed
FEATURES
Low power
(1) C "" 0 -70: M = -55 -125°: I = -25 _85 or Max Junction li:Imp = 160(2) CM = 10100 Family Metal Can, DP = Dual In LIne PlastIc, DG = Dual In Line
Ceramic, FP ... Small Outline Ie - Plastic, H = 1099 Metal Can, GC = Ceramic
LCC, K -= 103 Metal Can, $P 10220 Family
• Product In developmen1
0
OIl
18
THOMSON COMPONENTS MOSTEK
PART NO.
TL064
TL074
TL084
PART NO.
LM101A(201A, 301A)
LM108(208-308)
LMI18(218-318)
UA709
UA741
UA748
UA776
TDB7910
PART NO.
LMI58(258-358)
LMI458(1558)
LM2904
MC4558
TE.l033
PART NO.
LM124(224,324)
LMl46(246,346)
LM148(248,348)
LM2902
MC3303(3403,3503)
TE.4033
PART NO.
LM111(211,311)
FEATURES
Low power
Low noise
Standard
FEATURES
Lowoffse1
Precision
High speed
Standard
Slandard
Slandard
Programmable
POwer op·amp.
TEMPERATURE
RANGE (1)
PACKAGES (2)
C, I, M
C, I, M
C, I, M
DP, FP, OG, DC, GC
Op, FP, OG, DC, GC
Op, FP, OG, ~C, GC
TEMPERATURE
RANGE (1)
PACKAGES (2)
C, I, M
C, I, M
C, I, M
M
C, I, M
C,M
C,M
C
DP, FP, OG, GC,
DP, FP, OG, GC,
DP, FP, OG, GC,
H
DP, FP, OG, GC,
DP, FP, OG, GC,
DP, FP, OG, GC,
OP
H
H
H
H
H
H
TEMPERATURE
RANGE (1)
PACKAGES(I)
C, I, M
C, I, M
I
C, M, I
I, C.
DP, FP, DG, GC, H
DP, FP, OG, GC, H
DP, FP
Op, FP, DG, H
DP, FP, DG, GC
FEATURES
TEMPERATURE
RANGE (1)
PACKAGES (2)
Single power supply
Programmable
Standard
Single power supply
Single power supply
General purpose
C, I, M
C, I, M
C, I, M
V
C,M
B, C·
DP, FP, OG, GC, DC
DP, FP, OG, GC
DP, FP, OG, GC
DP, FP
DP, FP, OG, GC
DP, FP, OG, GC
FEATURES
TEMPERATURE
RANGE (1)
PACKAGES (2)
C, I, M
DP, FP, OG, GC, H
FEATURES
Single power supply
Standard
Single power supply
Single power supply, high speed
For filter design
Standard
19
THOMSON COMPONENTS MOSTEK
PART NO.
LMl19(219,319)
LM193(293,393)
LM2903
PART NO.
LM139,A(239,A·339,A)
LM2901
MC3302
FEATURES
TEMPERATURE
RANGE (1)
PACKAGES (2)
Standard
Single power supply
Single power supply
C, I, M
C, I, M
C
DP, FP, DG, GC, H
DP, FP, GC, H
DP, FP
FEATURES
TEMPERATURE
RANGE (1)
PACKAGES (2)
Standard
Single power supply
Single power supply
C, I, M
I
I
DP, FP, DG, GC, DC
DP, FP
DP
PART NO.
OUTPUT
VOLTAGE
OUTPUT
CURRENT
TEMPERATURE
RANGE (1)
PACKAGES (2)
LM109 (209,309)
LM123 (223,323)
TEA5110
UA7B05,B
UA7BS05,B
UA7806
UA7808
UA78S09,B
UA7812,B
UA78S12;j3
UA7815
UA78S15,B
UA7818
UA7824
UA7905,B
UA7912,B
UA7915,B
5V
5V
5V (Dual)
5V
5V
6V
BV
9V
12V
12V
15V
15V
18V
24V
-5V
-12V
-15V
1.5 A or 2.5 A
3A
0.1 A
1.5 A
2A
1.5 A
1.5 A
2A
1.5 A
2A
1.5 A
2A
1,5 A
1,5 A
1,5 A
1,5 A
1.5 A
C, I, M
C, I, M
C
C, I, M
C
C, M
C,M
C
C, i, M
C
C, I, M
C
C, M
C, M
C, i, M
C, I, M
C, I, M
H,K
K
DP
SP, K
SP, K
SP, K
SP, K
Sp, K
Sp, K
Sp, K
SP, K
SP, K
SP, K
SP, K
SP, K
Sp, K
Sp, K
PART NO.
OUTPUT
VOLTAGE
OUTPUT
CURRENT
TEMPERATURE
RANGE (1)
PACKAGES (2)
2A
",25 rnA
I
C, I, M
SP5
H
LMl17 (217, 317)
2,85VI32V
4,5V140V (105, 205)
4,5V130V (305)
1,2V/40V
C, I, M
SP, H, K
LM137 (237, 337)
-1.2VI -40
C, I, M
S, H, K
LM138 (238, 338)
UA723, A
1,2V135V
2V/37V
1.5 A (K, SP)
0,5 A (H)
1.5 A (K, SP)
0,5 A (H)
5A
50 rnA
C, I, M
C, I, M
K
DP, FP, DG, H
PART NO.
OUTPUT
VOLTAGE
OUTPUT
CURRENT
TEMPERATURE
RANGE (1)
PACKAGES (2)
5V
100 rnA
C, I
DP
L200
LM105 (205, 305)
TEA7105
20
THOMSON COMPONENTS MOSTEK
LINEAR
PART NO.
OUTPUT
VOLTAGE
OUTPUT
CURRENT
TEMPERATURE
RANGE (1)
PACKAGES (2)
TEA7034
TEA7605'
+5V
+5V
;,,500 mA
500 mA
C,I
C
SP5·2
SP
PART NO.
FUNCTION
PACKAGE
(2)
TEA2018A
Power supply control circuit for fixed frequency fly·back power supplies up to BOW.
Direct drive of the switching transistor. Output current IB = Kl c '
Total protection from overload short·circuit and temperature. Low rest current.
Dp·8
TEA2019
Power supply control circuit for fixed frequency fly·back power supplies up to 80W.
Direct drive of the switching transistor. Output current IB = Kl c '
Total protection from overload, short·circuit and temperature.
Dp·14
- Low rest current.
- Sync. capability with internal PLL.
TEA2162
Control IC for fixed frequency fly·back power supplies up to 200W.
In conjunction width TEA2029, this IC provides full secondary regulation for color TV applications
(Master/Slave).
Optimized power stage drive current. Over·voltage / current protections. Soft·start procedure.
UAA4006B
Control circuit for fixed frequency fly·back power supplies up to 200W.
Direct drive of switching transistor with self regulated base current. Reduced storage time.
Total protection from overload, short·circuit and temperature. Very low rest current.
FEATURES
PART NO.
LMI34 (234-334)
LM236,A (336,A)
NE/SE555
NE/SE556
ESM683
JUCA4532
UAA4002
Adj. current source
2.5V voltage references
Timer
Timer
Analog gate
Thermal printhead driver
Transistor driver
Batwing
Dp·16
Dp·16
SP
TEMPERATURE
RANGE (I)
PACKAGES (2)
C,I, M
C,I
C,I, M
C,M
C
C
A
Z
Z
DP, FP, DG, H
DP, FP, DG
FP
Chip
DP
PART NO.
TYPE
OUTPUT CURRENT
TEMPERATURE
PACKAGE
TEA3717
TEA371B,S
L702
UCN4801
Bipolar
Bipolar
Unipolar
Unipolar
I A
1.5 A
2.0 A
400 mA
C
C
C
C
DP, SP
DP, SP
DP, SP
DP
UAA4003
TDAI154
UAA2081
DC
DC
Unipolar
1.2 A
I A (Dual)
C
C
C
DP
DP
DP
21
THOMSON COMPONENTS MOSTEK
PART NO.
FUNCTION
PACKAGE (2)
Complete horizontal and vertical deflection circuit for black and white TV sets.
Direct drive of frame yoke (maximum output current: ± 1.5 A), direct drive of
line darlington, muting output.
SP-15
TV scanning and power supply digital processor includes 50-60 Hz identification,
security and start-up systems.
DP-28
TEA2029C
TV scanning and power supply digital processor includes 50-60 Hz identification,
security and start-up systems. In conjunction with TEA2162, it provides SMPS
secondary regulation.
DP-28
TEA2037A
Low cost horizontal and vertical deflection circuit for black and white
TV sets and monochrome displays. Direct drive of frame yoke (maximum output
current: ± 1 A), direct drive of line darlington.
Batwing
DP-16
TEA2017
TEA2026C
Horizontal
and vertical
TBA920.S
Horizontal
TDA2593
TEA2031A
Parabolic
correction
PART NO.
Line Oscillator, syn, separator, phase comparator for monochrome TV sets.
DP-16
Line oscillator combination, burst, blanking and frame pulse separation
for color TV sets.
DP-16
Ensures the vertical rate, parabolic and keystone correction for 110" screens
DP-8
FUNCTION
PACKAGE (2)
TDA2540
IF amplifier with demodulator and AFC (CCIR standard) for NPN tune,
DP-16
TDA2541
IF amplifier with demodulator and AFC (CCIR standard) for PNP tuner.
DP-16
TDA2542
IF amplifier with demodulator and AFC (French standard).
DP-16
TDA4426
Very stable IF amplifier with demodulator and AFC for PNP tuner.
DP-18
TDA4427
Very stable IF amplifier with demodulator and AFC for PNP tuner
and inverted AFC.
DP-18
TDA4443
IF amplifier with demodulator for multistandard applications.
High input sensitivity. Large AGC capabilities.
DP-16
TDA4445A
Quasi parallel sound processing with quadrature inter-carrier demodulator.
Very high input sensitivity. Good AM suppression.
DP-16
AM/FM sound demodulator. Low AM distortion. Very high input sensitivity.
No adjustment for the AM demodulator.
DP-16
Video IF
Sound IF
TDA4445B
22
THOMSON COMPONENTS MOSTEK
CONSUMER CIRCUITS
PART NO.
FUNCTION
PACKAGE (2)
TEA1014
Video and
AF switch
For monosound TV sets. Follows the SCAAT specifications n° lOB.
TEA2014
Video
switch
Switched 2 Vpp video output. Not switched 75
TEA5114,A
A·G·B
switch
TEA5115
n,
Dp·14
1 Vpp video output.
DP·S
3-channel high frequency switch (20 MHz), designed for A·G·B and video appli·
cations. Low output impedance (75 0).
Dp·16
5·switch (A·G·B, Fast blanking, Sync.) video signal selector. 25 MHz bandwidth
for A·G·B signals.
Dp·IS
PART NO.
FUNCTION
PACKAGE (2)
For ultra-sonic or infra-red transmission, 32 command capability.
Dp·18
UAA4000
Transmitter
UAA4009
Receiver
Complete circuit for PPM demodulation. 12 channel tuning voltage switch
(remote and keyboard), one DC voltage output for volume adjustment,
standby information.
Dp·18
TEA5049
PreAmp
A low cost infra·red preamplifier for remote control reception
Dp·14
PART NO.
Pulse position modulation provides excellent noise immunity.
APPLICATION
TBA820M
lCA830SM
Aadio and portable
recorders
TEA2025B
Portable radio dual
AF amplifier
TDA2003
Car radio
TDA2006
MAX. VALUES
NORMAL CONDITIONS
Vcc(V)
lo(A)
VcC
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