1987_National_Random_Access_Memory_Databook 1987 National Random Access Memory Databook

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National
Semiconductor
Corporation

400085

Random Access Memory
DATABOOK

Static RAMs
TIL RAMs
TTL FIFOs

ECLRAMs
Physical Dimensions
iii

•III
fJi

01

1:11

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without notice, to change said Circuitry or specifications.

iv

::D

I\)

Random Access Memory
Databook Introduction

:::l
Co

o
3

~
~

The Random Access Memory databook contains comprehensive technical information on National's volatile
memory product lines. National offers a breadth of staticRAM products from high-speed, low-power MOS SRAMs
to ultra-high-performance EeL RAMs.

en
en
3:
CD

3

o

- output for bus interface
Separate Data In and Data Out pins
Single + 5V supply
Standard 18-pin dual-in-line package
Available in MIL-STD-BB3 class B screening

Block Diagram*

Logic Symbol*
::0

IIEMORY ARRAY
"ROWS
MCDLUMNS

DIN(DI
DDUT(Q)

..

AID

.. .

TUD/5257-2

Connection Diagram*
Dual-In-Une Package
II

AD

TLlD/5257 -1

Pin Names·
AO-A11
WErNJ
CS(S)
D,N (D)
DOUT(Q)
Vee
Vss

Address Inputs
Write Enable
Chip Select
Data In
Data Out
Power(5V)
Ground

vee

11 AI

AI

~

A2

Order Number NMC2147HJ-1,
NMC2147HJ-2, NMC2147HJ-3,
or NMC2147HJ-3L
NS Package Number J18A
Order Number NMC2147HN-1,
NMC2147HN-2, NMC2147HN-3
or ~~MC2147HN-3L
NS Package Number N18A

.
A3

A5
12 A11

DDUT(O) 7
WE(\'i)8

11 D'N(DI
10 Sill

vas

TL/D/5257-3

Top View

"The symbols in parentheses are proposed industry standard.

1-3

•

Absolute Maximum Ratings

Truth Table*

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage on Any Pin Relative to VSS
-3.5Vto +7V
Storage Temperature Range
Power Dissipation
DC Output Current

- 65'C to + 150'C
1.2W
20mA

Bias Temperature Range

- 65'C to + 135'C

Lead Temperature (Soldering. 10 sec.)

CS
(S)

WE

DIN
(D)

DOUT
(Q)

Mode

Power

X

X

L
L
H

H
L

Hi-Z
Hi-Z
Hi-Z
DOUT

Not Selected
Write 1
Write 0
Read

Standby
Active
Active
Active

(\\I)

H
L
L
L

X

300'C

DC Electrical Characteristics TA = O'Cto +70"C. VCC = 5V ± 10% (Notes 1 and 2)
Symbol

Parameter

Min

= OV to 5.5V. VCC = Max

IILlI

Input Load Current
(All Input Pins)

VIN

IILOI

Output Leakage
Current

CS = VIH. VOUT
VCC = Max

NMC2147H-1
NMC2147H-2
NMC2147H-3

NMC2147H-3L

Conditions

= GND to 4.5V.

Max

Min

NMC2147H

Max

Min

Units

Max

10

10

10

",A

50

50

50

",A
V

VIL

Input Low Voltage

-3.0

0.8

-3.0

0.8

-3.0

0.8

VIH

Input High Voltage

2.0

6.0

2.0

6.0

2.0

6.0

V

VOL

Output Low Voltage

0.4

V

VOH

Output High Voltage

ICC

Power Supply
Current

160

rnA

Output Open

ISB

Standby Current

VCC

IPO

Peak Power-On
Current

VCC = VSS 10 VCC Min.
CS = Lower 01 VCC orVIH Min

= 8.0 rnA
IOH = -4.0 rnA
VIN = 5.5V, TA = O'C.

0.4

IOL

0.4

2.4

= Min to Max, CS = VIH

2.4

2.4

V

125

180

20

30

20

rnA

30

40

30

rnA

Capacitance TA = 25'C, f = 1 MHz (Note 3)
Symbol

Parameter

Min

Conditions

Max

Units

CIN

Address/Control Capacitance

VIN = OV

5

pF

COUT

Output Capacitance

VOUT = OV

6

pF

Note 1: The operating amblen1temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
Note 2: These circuHs requira 500 I's time delay aiter vee nsaches the speclfled minimum limH to ensure proper orientation aiter power·on. This allows the
intemally generated substrate bias to reach Its functional level.
Nate 3: this perameter is guaranteed by periodic testing.

AC Test Conditions
Input Test Levels

GNDto 3.0V

Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level (H-l)
Output Timing Reference Level
(H-2. H-3. H-3L)
Output Load

DDUT

6V

5 ns
1.5V
510n

1.5V
0.8V and 2.0V
See Figure 1

•

3110Sl

=

30pF

~ (INCLUDING
SCDPEAND
FIXTURE)

~
FIGURE 1. Output Load
'Symbols In parentheses are proposed industry standard.

1-4

TL/D/5257-4

z

Read Cycle AC Electrical Characteristics TA = 0'Ct070'C, vcc =
Symbol

NMC2147H-1

NMC2147H-3
NMC2147H-3L

NMC2147H-2

Parameter
Alternate Standard
TAVAV

tRC

Min
Read Cycle Time

Max

35

Min

Min

Max

45

s::
(")

5V ±10% (Note 1)

N
.....

Max

55

Units
Min

Max

70

ns

tAA

TAVOV

Address Access Time

35

45

55

70

ns

tACS

TSLOV

Chip Select Access Time
(Notes 4)

35

45

55

70

ns

tLZ

TSLOX

Chip Select to Output Active
(Note 5)

5

tHZ

TSHOZ

Chip Deselect to Output
TRI-STATE (Note 5)

0

tOH

TAXOX

Output Hold from Address
Change

5
0

tpu

TSLIH

Chip Select to Power-Up

tpD

TSHIL

Chip Deselect to Power-Down

Max Access/Current

5
30

10

0

30

10

0

5

30

5

0

ns
30

0

20

20

ns
ns

5

0

20

0

""
::c
......

NMC2147H

ns
30

NMC2147H-1

NMC2147H-2

NMC2147H-3

NMC2147H-3L

Access (TAVOV-ns)

35

45

55

55

70

Active Current (ICC-mA)

180

180

180

125

160

Standby Current (ISB-mA)

30

30

30

20

20

ns

NMC2147H

Read Cycle Waveforms*
Read Cycle 1 (Continuous Selection CS

= VIL, WE = VIH)

~ 'Re

~

ADDRESS

-!~~.

"RV.V,
DATA OUT

PREVIDUS DATA VALtD

DATAVALtD

,TA,,,,

_'OH

TL/0/5257-5
Read Cycle 2 (Chip Select Switched, WE

= VI H) (Note 4)

'RC

".v.",
CiiiPSfiECf ~

I--rrit,Z ~t~~)
DATA OUT

DATA VALID

,GH 'MPEDANCI

tp

H'~iPEDANCE

I- crSH~L)

~LtH)
VCC ICC - - - - - SUWLY
CURRENT ISS

•

-

I

IO~\-

S""

TUD/5257-6

Addresses must be valid coincident with or prior to the chip select transition from high to low.
Note 5: Measured ± 50 mV from steady state voltage. This parameter is sampled and not 100% tested.
Note 4:

'The symbols in parentheses are proposed industry standard.

1-5

Write Cycle AC Electrical Characteristics TA =
Symbol

NMC2147H-1

Parameter

Alternate Standard

Min

O'C to 70'C, VCC = 5V

NMC2147H-2

Max

Min

± 10% (Note 1)

NMC2147H-3
NMC2147H-3L

Max

Min

NMC2147H

Max

Min

Unite

Max

two

TAVAV

Write Cycle TIme

35

45

55

70

ns

tow

TSLWH

Chip Select to End of Write

35

45

45

55

ns

tAW

TAVWH

Address Valid to End of Write

35

45

45

55

ns

tAS

TAVSL
TAVWL

Address Set-Up TIme

twp
twA

TWLWH
TWHAX

tow

TDVWH

;

0

0

0

0

ns

Write Pulse Width

20

25

25

40

ns

Write Aecovery Time

0

0

10

15

ns

Data Set-Up Time

20

25

25

30

ns

10

10

10

ns

tOH

TWHOX

Data Hold TIme

10

twz

TWLQZ

Write Enable to Output
TAl-STATE (Note 5)

0

tow

TWHQX

Output Active from End
of Write (Note 5)

0

Write Cycle Waveforms'"

20

0

25

0

0

25

0

0

35

ns
ns

(Note6)
Write Cycle 1 (Write Enable Umlted)

ADDRESS

0

*
.,

twc
CTAVAV)

--

tew
IT&LWn,

iilmmT~ ~

~ ~~
tAS

II

AY""

I

-~~!-

twR

',AY""'

IIW""",

twP
IIWLW",

.J~

TrnmIl

.ltIyt

~HDX)

\TUYW",

)

DATA III

twz

ITWLOZIDATADUT

l(

DATA IN VALID

1- ~QXI.
HIBH IMPEDAIICE

DATA

TlIO/5257-7

1-6

Write Cycle Waveforms*

(Note 6)
Write Cycle 2 (Chip Select Limited)

'cw

{TSLWHI

DATADUT

HIGH IMPEDANCE

DATA UNDEFINED

--------------------------~~
TLlO/S2S7-8

Note 6: The oulput remains TRI-8TATE if the CS and WE go high simultaneously. WE or CS or bolh must be high during the address transitions to prevent an
erroneous write.
'The symbols in parentheses are proposed industry standard.

•
1-7

Ij

National

August 1986

Semiconductor

CorporaHon

NMC2148H 1024 X 4 Static RAM
General Description

Features

The NMC2148H is a 1024-word by 4-bit static random access memory fabricated using N-channel silicon-gate technology. All internal circuits are fully static and therefore require no clocks or refreshing for operation. The data is read
out nondestructively and has the same polarity as the input
data.
The separate chip select input automatically switches the
part to its low power standby mode when it goes high. Common inpuVoutput pins are provided.

•
•
•
•
•
•
•
•

All inputs and outputs directly TTL compatible
Static operation-no clocks or refreshing required
Automatic power-down
High-speed-down to 45 ns access time
TRI-STATE4Il output for bus interface
Common data I/O pins
Single + 5V supply
Standard 18-pin dual-in-line package

Block Diagram *

Logic Symbol*

.. 0.;.----1

AD

~VCC

Ai 0;----1

....,!ova
M~---o4

MEMORY ARRAY
B4 ROWS
B4CDLUMNS

.. 0-::;11---04

1/03
101131

A.O-:;'·;......---I

A9

.70-:;17;......_ _-1

TL/DI7404-3
COLUMN 110 CIRCUITS

Connection Diagram*
Dual-In-Llne Package
18

A6

vee

A5

14110t

9111 ,.
ft~I~-1==~[)~

(061)

______________

13 1102
10GZI
1211U3

~

10631

TL/DI7404-'

Pin Names'
Address Inputs
WE(W)
Write Enable
CS(S)
Chip Select
1/01-1/04
Data Input/Output
(OQ1-004)
vee
Power(5V)
Ground
VSS
AO-A9

111104

10641
Order Number NMC2148HJ-L,
NMC2148HJ-3L, NMC2148HJ,
NMC2148HJ-2 or NMC2148HJ-3
NS Package Number J18A
Order Number NMC2148HN-L,
NMC2148HN-3L, NMC2148HN,
NMC2148HN-2 or NMC2148HN-3
NS Package Number N18A

'Symbols In parentheses are proposed industry standard.

1-8

10

vss

1'11111

TL/DI7404-2

Top View

Absolute Maximum Ratings

Truth Table

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltage at Any Pin with Respect to VSS
-3.5Vto +7V
Storate Temperature
Temperature with Bias

-65·Cto + 150"C
-10·C to +85·C

DC Output Current
Power Dissipation

20mA
1.2W

Lead Temperature (Soldering, 10 sec.)

300"C

CS

WE

I/O

Mode

Power

H
L
L
L

X

Hi-Z
H
L
DOUT

Standby
Write 1
Write 0
Read

Standby
Active
Active
Active

L
L
H

DC Electrical Characteristics TA = o·c to +70·C, VCC = 5V ± 10% (Notes 1 and 2)
Symbol

)

Parameter

Conditions

NMC2148H·L
NMC2148H·3L

NMC2148H
NMC2148H·2
NMC2148H·3

Min

Min

Max

IILlI

Input Load Current
(All Input Pins)

VIN = OVt05.5V,
VCC = Max

IILOI

Output Leakage Current

CS = VIH, VOUT
VCC = Max

VIL

Input Low Voltage

-2.5

0.8

VIH

Input High Voltage

2.1

6.0

VOL

Output Low Voltage

VOH

Output High Voltage

ICC

Power Supply Current

= GND to 4.5V,

= 8.0mA
10H = -4.0mA
VIN = 5.5V, TA = O·C,
10L

Units

Max

10

10

",A

50

50

",A

-2.5

0.8

V

2.1

6.0

V

0.4

V

125

180

mA

0.4
2.4

2.4

V

Output Open

= Min to Max, CS = VIH

ISB

Standby Current

VCC

IPO

Peak Power-On Current

VCC = VSS to vee Min,
CS = Lower of VCC or VIH Min

Iiosl

Output Short Circuit Current

VOUT

= GND to VCC

20

30

mA

30

40

mA

250

250

mA

Capacitance TA = 25·C,f = 1.0 MHz (Note 3)
Symbol

Parameter

Conditions

Min

= OV

CIN

Address/Control Capacitance

VIN

CliO

Input/Output Capacitance

VIICX:"" OV

Max

Units

5

pF

7

pF

Nole 1: The operating ambient temperature range Is guaranteed with transverse air flow exceeding 400 linear feet per minute.
Note 2: These circuits require 500 p.s time delay after vee reaches the specified minimum limit 10 ensure proper operation after power·on. This allows the
internally genereted substrate bias to reach its functional level.
Nole 3: This parameter is guaranteed by periodic testing.

AC Test Conditions
Input Test Levels
Input Rise and Fall Times

5 ns

Input Timing Reference Level

1.5V

Output Timing Reference Levels
Output Load

DQUT
)

GNDt03.0V

II

5V

4800

... q'. . . . .

0.8V and 2.0V
See Figure 1

~

30pF

AND AXTUREI

TL/DI7404-4

FIGURE 1. Output Load

1-9

Read Cycle AC Electrical Characteristics TA = o·c to + 70·C, vcc =
Symbol

NMC2148H-2

Parameter

Alternate Standard

Min

Max

5V ± 10% (Note 1)

NMC2148H-3
NMC2148H-3L
Min

45

NMC2148H
NMC2148H·L

Max

Units

Max

tRC

TAVAV

Read Cycle Time

tM

TAVQV

Address Access Time

45

55

70

ns

tACS1

TSLQV1

Chip Select Access Time (Notes 4 and 5)

45

55

70

ns

tACS2

TLSQV2

Chip Select Access Time (Notes 4 and 6)

55

65

80

ns

tLZ

TSLQX

Chip Select to Output Active (Note 7)

20

tHZ

TSHQZ

Chip Deselect to Output TRI·STATE (Note 7)

0

tOH

TAXQX

Output Hold from Address Change

5

5

5

ns

0

0

0

ns

tpu

TSLIH

Chip Select to Power·Up

tpD

TSHIL

Chip Deselect to Power-Down

Max Access/Current

55

Min
70

20
20

ns

ns

20
20

0

30

0

20

30

30

NMC2148H-2

NMC2148H-3

NMC2148H

NMC2148H-3L

Access (TAVQV-ns)

45

55

70

55

70

Active Current (ICC-mA)

180

180

180

125

125

Standby Current (ISB-mA)

30

30

30

20

20

ns

ns

NMC2148H·L

Read Cycle Waveforms*
Read Cycle 1 (Continuous Selection CS

=

VIL, WE

=

VIH)

~---------------"..-•.;t"~vC~"V"'---------------~

ADDRESS

~-"",L~----------"'';';';;''''---------''''J:Jr-------

L

,,'VUV

DATA OUT

==t~
PREV~IDU~S'D~ATA'~'
VAU~ID=-t1.til~~======~DATA~"V~AUD~======
I

.."-...
'.Ov·~nu,,·Y'----'

_

TL/D17404-5

Read Cycle 2 (Chip Select Switched, WE = VI H) (Note 4)

---------
TA~;V,---------I

1,...-----

CHIP SELECT I - - - - . . .

DATA OUT

---~-;.-~-;-~-~-~tl~z~:(:~:~~:~~)~~~i~ii;t=I====~~~~====t~1-~~"'~..~o,)~WVcr-~

(TSlOX)

DATA VAUD

HIGH IMPEDANCE

!Po

HIIGH IMPEDANCfE IpU

vee

ICC - - - - - - - -

SUPPLY

CURRENT

(TSlIH)

-

~

ITSHll )",," _ _ __
S •

50%

ISS - - - - - -

TL/DI74D4-6

Note 4: Addresses must be valid coincident with or prior to the chip select transition from high to low.
Note 5: Chip deselected longer than 55 ns.
Note 6: Chip deselected less than 55 ns.
Note 7: Measured

± 50 mV from steady state voltage. This parameter is sampled and not 100% tested.

·The symbols in parentheses are proposed industry standard.

1-10

Write Cycle AC Electrical Characteristics TA =
Symbol

O·Cto +70"C, vcc = 5V ±10% (Note 1)

NMC2148H-2

Parameter

Alternate Standard

Min

Max

NMC2148H-3
NMC2148H-3L
Min

Max

NMC2148H
NMC2148H-L Units
Min

Max

twc
lew

TAVAV

Write Cycle Time

45

55

70

ns

TSLWH

Chip Select to End of Write

40

50

65

ns

tAW

TAVWH

Address Valid to End of Write

40

50

65

ns

tAS

TAVSL
TAVWL

Address Set-Up Time

0

0

0

ns

twp

TWLWH

Write Pulse Width

35

40

50

ns

twR

TWHAX

Write Recovery Time

5

5

5

ns

tow

TDVWH

Data Set-Up TIme

20

20

25

ns

tOH

TWHDX

Data Hold Time

0

0

0

twz

TWLQZ

Write Enable to Output TRI-STATE (Note 7)

0

tow

TWHQX

Output Active from End of Write (Note 7)

0

Write Cycle Waveforms'"

15

0

20

0

0

0

ns
25

ns
ns

(NoteS)
Write Cycle 1 (Write Enable Umlted)

--

lT~iVI

-u-

-l
ICW
ITSLWHI

...,~ ~~

emrnmT~ ~ r

twR

lAW

JOn,

_~ill

""VIVL,
WRmENABLE

II """AI

'W,

(TWL""'
-'~~ r

7 fIDH
ITWHDXI

...., 'i-

DATA IN

-l I-

1-1r:~ZI-DATA OUT

1HIGH IM'EDANCE

DATA UNDEFINED

lOW
ITWHOXI
~ Q VIH. CMOS (Note 11)
CS2 > VIH. CMOS

2.0

5.5

V

< VIL. CMOS (Note 11)

2.0

VORl

Vee for Data Retention

VOR2

Vee for Data Retention

CS2

5.5

V

leeORl

Data Retention Current

Vec = 2V
CS1 > VIH. CMOS
CS2 > VIH. CMOS

40

fAA

. Vee = 2V
CS2 < VIL. CMOS

40

p.A

ICCDR2

Data Retention Current

teoR

Chip Deselect to Data Retention Time

See Retention Waveform

0

ns

tR

Operation Recovery Time

See Retention Waveform

tRe

ns

Low Vee Data Retention Waveforms
No.1 (CS1 Controlled)

~~~~~~~~~~~~-----~~
OR I-o-------DATARETENTIDN MODE------~-I-IH

CS1:::~_ _ _ _ _ _ _ _ _~~fS~1~=~~~,~CM~Q~S_ _ _ _ _ _ _ _ _ _ _~·~:::::::::

ov

TL/O/8B08-7

No.2 (CS2 Controlled)

ji! _____~---------D-M
AR~ET,E~NT,IQ~NmM.QD-E~~~~~~~~~~~~~~::~9:.-~~~~~:
~_
_:y..

CS2=V'L,CMQS

ov-------~~~~~~~~~==~~~~~~~------TLlO/8B08-8

1·17

•

-J

Z•

r--------------------------------------------------------------------------------,
NatiOnal

Semiconductor
.... ~ Corporation
CD

an

ADVANCED INFORMATION
April 1987

N

CD

o
z
......
z
CD
::::E

NMC61256N/NMC61256N-L 32,768 X 8-Bit Static RAM

an

General Description

Features

CD

The NMC61256NINMC61256N-L is a 32,768 by 8-bit, new
generation static RAM. It is fabricated with National's proprietary microCMOS double-polysilicon technology which combines high performance and high density with low power
consumption and excellent reliability.
The NMC61256N/NMC61256N-L operates with a single 5V
power supply with ± 10% tolerance. Additional battery
back-up operation is available (L version) for data retention
down to 2V, with low standby current.

•
•
•
•

....
N

o
::::E
z

Packaging is in standard 28-pin plastic DIP.
In addition to the inputs and outputs being TTL compatible,
the outputs are also CMOS compatible, in that capacitive
loads are driven to Vee or Vss.

•

•
•
•
•
•

Single power supply: 5V ± 10%
Fast access time 70 ns/100 ns/120 ns max
Equal access and cycle times
Completely static RAM: no clock or timing strobe
required
Low standby power and low power operation
Standby: 50 poW, typical
Operation: 10 mW/MHz, typical
Battery back-up operation available (L version) with
data retention supply voltage: 2V-5.5V
Common data input and output, TRI-STATE VIH. CMOS

Low Vee Data Retention Waveform

TL/D/BS07-7

1-22

Section 2
TTL RAMs

Section 2 Contents
PAGE
NUMBER
TTL RAM Selection Guide. . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3
DEVICE
DM54S189, DM74S189
DM74S289
DM54S189A, DM74S189A
DM85S06
DM75S07, DM85S07
DM75S07A, DM85S07A
DM75S68A, DM85S68,
DM75S68A, DM85S68A
IDM29705,29705A

DESCRIPTION
64-Bit (16 x 4) TRI-STATE RAM ......•.................
64-Bit Open-Collector RAM ....... ,................... .
High Speed 64-Bit TRI-STATE RAM ................... .
Open Collector ....•...............•.................
TRI-STATE ......................................... .
High Speed TRI-STATE Non-Inverting, 64-Bit
(16 x 4) RAMs .................... , ............... .
16 x 4 Edge Triggered Registers ...................... .
16 Word by 4-Bit Two Port RAM/Register File .......... .

2·2

2-4
2-4
2-4
2-12
2-12
2-12
2-20
2-24

~

TTL RAM Selection Guide

Size
(Bits)

Outputs'

Pins
(DIP)

PIN

TAA

Icc

Temp

16x4
16x4
16x4
16x4

TS
TS
TS
TS

16
16
16
16

DM54S189
DM74S189
DM54S189A
DM74S189A

50
35
30
25

110
110
100
100

- 55·C to + 125·C
O·Cto +70·C
- 55·C to + 125·C
O·Cto +70·C

16x4

OC

16

DM74S289

35

110

O·Cto +70·C

16x4
16x4
16x4
16x4

TS
TS
TS
TS

16
16
16
16

DM75S07
DM85S07
DM75S07A
DM85S07A

50
35
30
25

100
100
100
100

-55·C to + 125·C
O·Cto +70·C
-55·C to + 125·C
O·Cto +70·C

16x4

OC

16

DM85S06

35

100

O·Cto +70·C

TS
TS
TS
TS

18
18
18
18

DM75S68
DM85S68
DM75S68A
DM85S68A

55
40
45
24

100
100
100
100

-55·Cto +125·C
O·Cto +70·C
- 55·C to + 125·C
O·Cto +70·C

Organization

INVERTING RAMS

64

NON-INVERTING RAMS

64

EDGE TRIGGERED REGISTERS

64

16x4
16x4
116x4
16x4

'TS = TAl-STATE'" outputs
OC = Open Collector outputs

2·3

NatiOnal

~ Semiconductor

April 1987

Corporation

DM54S189/DM74S189 64-Bit (16 X 4) TRI-STATE® RAM
DM74S289 64-Bit Open-Collector RAM
DM54S189A/DM74S189A High Speed 64-Bit
TRI-STATE RAM
General Description
These 64-bit active-element memories are monolithic
Schottky-clamped transistor-transistor logic (TTL) arrays organized as 16 words of 4 bits each. They are fully decoded
and feature a chip-enable input to simplify decoding required to achieve the desired system organization. The
memories feature PNP input transistors that reduce the low
level input current requirement to a maximum of -0.25 mA,
only one-eighth that of a DM74S standard load factor. The
chip-enable circuitry is implemented with minimal delay
times to compensate for added system decoding.

available at the outputs when the read/write input is high
and the chip-enable is low. When the chip-enable is high,
the outputs will be in the high-impedance state.
The fast access time of the DM74S189A makes it particularly attractive for implementing high-performance memory
functions requiring access times less than 25 ns. The high
capacitive drive capability of the outputs permits expansion
without additional output buffering. The unique functional
capability of the DM74S189A outputs being at a high-impedance during writing, combined with the data inputs being
inhibited during reading, means that both data inputs and
outputs can be connected to the data lines of a bus-organized system without the need for interface circuits.

The TAl-STATE output combines the convenience of an
open-collector with the speed of a totem-pole output; it can
be bus-connected to other similar outputs; yet it retains the
fast rise time characteristics of the TTL totem-pole output.
Systems utilizing data bus lines with a defined pull-up impedance can employ the open-collector DM74S289.

Features
• Schottky-clamped for high speed applications (S189A)
Access from chip-enable input
17 ns max
Access from address inputs
25 ns max
• TAI-STATE outputs drive bus-organized systems and/or
high capacitive loads (S189, S189A)
• DM74S289 are functionally equivalent and have opencollector outputs
• DM54SXXX is guaranteed for operation over the full
military temperature range of - 55°C to + 125°C
• Compatible with most TTL circuits
• Chip-enable input simplifies system decoding

Write Cycle: The complement of the information at the data
input is written into the selected location when both the
chip-enable input and the read/write input are low. While
the read/write input is low, the outputs are in the high-impedance state. When a number of the DM74S189 outputs
are bus connected, this high-impedance state will neither
load nor drive the bus line, but it will allow the bus line to be
driven by another active output or a passive pull-up if desired.
Read Cycle: The stored information (complement of information applied at the data inputs during the write cycle) is

Connection Diagram

.

Truth Table

Dual-In-Llne Package
SELECT INPUTS

D'

B

13

DATA
INPUT
4
12

Inputs

OUTPUT
V4

DATA
INPUT
l

11

10

Function

OUTPUT
Vl

READI
WRITE

DATA
INPUT
1

OUTPUT
V1

DATA
INPUT
2

OUTPUT
Y2

Output

Write (Store
Complement of Data)

L

L

High-Impedance

Read

L

H

Stored Data

Inhibit

H

x

High-Impedance

H

SELECT CHIP
INPUT A ENABLE

Chlp- Readl
Enable Write

= !"ligh Level, L = Low Level, X = Don't Cere
Order Number DM54S189J, DM54S189AJ,
DM74S189J, DM74S189AJ,
DM74S289J, DM74S189N,
DM74S189AN or DM74S289N
See NS Package Number J16A or N16E

01:
TUl/9232-1

Top View

2-4

Absolute Maximum Ratings

Operating Conditions

(Note 1)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vee

7.0V

Input Voltage
Output Voltage

5.5V
5.5V

Storage Temperature Range

- 65·C to + 150·C

Lead Temperature (Soldering, 10 sec.)

Min

Max

Units

Supply Voltage (Vce>
DM54S189
DM74S189, DM74S289

4.5
4.75

5.5
5.25

V
V

Temperature (TAl
DM54S189
DM74S189, DM74S289

-55
0

+125
+70

·C
·C

Max

Units

0.8

V

+300·C

DM54S189, DM74S189, DM74S289 Electrical Characteristics
over recommended operating free-air temperature range unless otherwise noted (Notes 2 and 3)
Symbol
VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VOH

High Level Output
Voltage

ICEX

VOL

Conditions

Parameter

Min

Typ

2

Vee

=

=

Min

High Level Output Current
Open Collector Only

Vcc

Low Level Output
Voltage

Vcc = Min,
10L = 16mA

Min

10H = -2.0 mA,
DM54S189

2.4

3.4

V

10H = -6.5 mA,
DM74S189

2.4

3.2

V

VOH
VOH

=

=
=

IIH

High Level Input Current

Vee

II

High Level Input Current
at Maximum Voltage

Vee ,,; Max, VI

IlL

Low Level Input Current

Vee

los

Short Circuit Output
Current (Note 4)

= Max, VI =
Vcc = Max,
Va = OV

Icc

Supply Current (Note 5)

VCC

Max, VI

V

=
=

2.4V

40

5.5V

100

p,A

DM54S189

0.5

V

DM74S189,
DM74S289

0.45

V

25

p,A

1.0

mA

.>

-250

p,A

-30

-100

mA

110

mA

-1.2

V

50

p,A

2.7V
5.5V
0.45V
DM54S189,
DM74S189

VIC

Input Clamp Voltage

=
Vcc =

10ZH

TRI-STATE Output Current,
High Level Voltage Applied

Vcc = Max,
Va = 2.4V

DM54S189,
DM74S189

10ZL

TRI-STATE Output Current,
Low Level Voltage Applied

Vee = Max,
Va = 0.45V

DM54S189,
DM74S189

CIN

Input Capacitance

Vcc = 5V, VIN = 2V,
TA = 25·C, 1 MHz

4.0

pF

Co

Output Capacitance

Vee = 5V, Va = 2V,
T A = 25·C, 1 MHz,
Output "Off"

6.0

pF

75

Max
Min, II

=

-18 mA

2-5

-50

p,A

DM74S 189 Switching Characteristics
over recommended operating ranges of TA and Vcc unless otherwise noted
DM54S189
Symbol

Parameter

Conditions
Min

tAA

Access Times from Address

tCZH

Output Enable Time to
High Level

teZl

Output Enable Time to
Low Level

twZH

Output Enable Time to
High Level

twZl

Output Enable Time to
Low Level

teHZ

Output Disable Time
from High Level

tCLZ

Output Disable Time
from Low Level

twHZ

Output Disable Time
from High Level

Access Times from
Chip-Enable

Cl = 30pF,
Rl = 2800
(Figure 4)

Sense Recovery Times
from Read/Write

Disable Times from
Chip-Enable

Cl = 5pF,
Rl = 2800
(Agure4)

Disable Times from
Read/Write

tWLZ

Output Disable Time
from Low Level

twp

Width of Write Enable Pulse (Read/Write Low)

tASW

Set-Up Time (Agure 1)

Address to Read/Write

DM74S189

Typ
(Note 2)

Max

25

Units

Typ
(Note 2)

Max

50

25

35

ns

12

25

12

17

ns

12

25

12

17

ns

13

35

13

25

ns

13

35

13

25

ns

12

25

12

17

ns

12

25

12

17

ns

15

35

15

25

ns

15

35

15

25

ns

Min

25

25

ns

0

0

ns

tosw

Data to Read/Write

25

25

ns

tcsw

Chip-Enable to
Read/Write

0

0

ns

Hold Time (Figure 1)

Address from Read/Write

0

0

ns

tOHW

Data from Read/Write

0

0

ns

tCHW

Chip-Enable from
Read/Write

0

0

ns

tAHw

2-6

DM74S289 Switching Characteristics
over recommended operating ranges of TA and Vcc unless otherwise noted
DM74S289
Symbol

Parameter

Conditions
Min

CL = 30 pF,
RL1 = 300n,
RL2 = Goon
(Figure 4)

Units

Typ
(Note 2)

Max

25

35

ns

12

17

ns

12

25

ns

tM

Access Time from Address

tCHL

Enable Time from
Chip-Enable

tWHL

Enable Time from
Read/Write

tCLH

Disable Time from
Chip-Enable

12

20

ns

tWLH

Disable Time from
Read/Write

13

25

ns

Sense Recovery Time
from Read/Write

twp

Width of Write Enable Pulse (Read/Write Low)

25

tASW

Set-Up Time (Figure 2)

Address to Read/Write

0

ns

tDSW

Data to Read/Write

25

ns

tcsw

Chip-Enable to
Read/Write

0

ns

Address from Read/Write

0

ns

Data from Read/Write

0

ns

tAHW

Hold Time (Figure 2)

tDHW

ns

Chip-Enable from
tCHW
0
ns
Read/Wtite
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual davice

operation.

Note 2: Unless otherwise specified minImax limits apply across the -SS'C to + 12S'C temperature range for the DM54S1B9 and across the O'C to +70'C range
for the DM74S1B9/2B9. All typicals are given for Vee ~ S.OV and TA ~ 2S'C.
Note 3: All CUITents Into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

Note 4: Only one output at a time should be shorted.
Note 5: Icc is measured with all inputs grounded; and the outputs open.

2-7

Absolute Maximum Ratings (Note 1)

Operating Conditions

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
7.0V
Supply Voltage, Vee

Min

Max

Units

Supply Voltage (Vee)
DM54S189(A)
DM74S189(A)/DM74S289

4.5
4.75

5.5
5.25

V
V

Temperature (TAl
DM54S189(A)
DM74S189(A)/DM74S289

-55
0

+125
,+70

·C
·C

Input Voltage
Output Voltage
Storage Temperature Range

5.5V
5.5V
- 65·C to + 150·C
+300·C

Lead Temperature (Soldering, 10 sec)

DM54S189A, DM74S 189A Electrical Characteristics
over recommended operating free-air temperature range unless otherwise noted (Notes 2 and 3)
SYl¥lbol

Parameter

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VOH

High Level Output
Voltage

Typ

Max

2

Vee

Vee

IIH

High Level Input Current

Vee

II

High Level Input Current
at Maximum Voltage

Vee

IlL

Low Level Input Current

Vee

los

Short Circuit Output
Current (Note 4)

Vee

= Min

= Min

V

IOH = -2.0 mA,
DM54S189A

2.4

3.4

V

IOH = -6.5 mA,
DM74S189A

2.4

3.2

V

IOL
10L

= 16mA
= 20mA

0.45

V

0.5

= Max, VI = 2.4V
= Max, VI = 5.5V
= Max, VI = O.40V
= Max, Va = OV

Units
V

0.8

Low Level Output
Voltage

VOL

Min

Conditions

-20

= Max
= Min,ll = -18 mA
Vee = Max, Vo = 2.4V

75

10

/kA

1.0

mA

-250

/k A

-90

mA

lee

Supply Current (Note 5)

Vee

Vie

Input Clamp Voltage

Vee

IOZH

TRI-STATE Output Current,
High Level Voltage Applied

IOZL

TRI-STATE Output Current,
Low Level Voltage Applied

Vee

CIN

Input Capacitance

Vee = 5V, VIN = 2V,
TA = 25·C, 1 MHz

4.0

pF

Co

Output Capacitance

Vee = 5V, Vo = 2V,
TA = 25·C, 1 MHz,
Output "Off"

6.0

pF

,

= Max, Vo = 0.4V

2-8

mA
V

40

/kA

IJ.A

-40

.'

100
-1.2

DM54S 189A, DM7 4S 189A Switching Characteristics
over recommended operating ranges of TA and Vcc unless otherwise noted
DM54S189A
Symbol

Parameter

Conditions
Min

tAA

Access Time from Address

teZH

Output Enable Time to
High Level

teZL

Output Enable Time to
Low Level

tWZH

Output Enable Time to
High Level

tWZL

Output Enable Time to
Low Level

teHZ

Output Disable Time
from High Level

tCLl

Output Disable Time
from Low Level

tWHZ

Output Disable Time
from High Level

Access Times from
Chip-Enable

CL = 30pF,
RL = 2800
(Figure 4)

Sense Recovery Times
from Read/Write

Disable Times from
Chip-Enable

CL = 5pF,
RL = 2800
(Rgure4)

Disable Times from
Read/Write

DM74S189A

Typ
(Note 2)

Max

20

Units

Typ
(Note 2)

Max

30

20

25

ns

11

25

11

17

ns

11

25

11

17

ns

13

35

13

25

ns

13

35

13

25

ns

12

25

12

17

ns

12

25

12

17

ns

15

35

15

25

ns

15

35

15

25

ns

Min

twLl

Output Disable Time
from Low Level

twp

Width of Write Enable Pulse (Read/Write Low)

25

20

ns

tASW

Set-Up Time (Figure 1)

Address to Read/Write

0

0

ns

tDSW

Data to Read/Write

25

20

ns

tesw

Chip-Enable to
Read/Write

0

0

ns

Address from Read/Write

0

0

ns

tDHW

Data from Read/Write

0

0

ns

tCHW

Chip-Enable from
Read/Write

0

0

ns

tAHW

Hold Time (Figure 1)

Nole 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device

operation.
Note 2: Unless otherwise specified minImax limits apply across the -55'C to + 125'C temperature range for the DM54S1B9(A) and across the O'C to +70'C
range for the DM74S1B9(A). All typicals are given for Vcc = 5.0V and TA = 25'C.

Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Icc is measured wHh all inputs grounded; and the outputs open.

2-9

c(

en

CIO
.....
CI)

..,.
:::E
"""
Q
.....

~
CIO
.....
(f)

..,.

DM54S189(A), DM74S189(A) Switching Time Waveforms
Enable and Disable Time from Chip-Enable
CHIPENABlf
INPUT (NOTE 3)

Write Cycle

,v

>V

'v------~~----~----------r
WAVEFORM 1

ADDRESS

INPUTS

~.5V

,V

(NOTE 1)

DATA
INPUTS

v"

II)

:::E
Q
.....
en

WAVEFOHM2
{NOTE I)

v""
>V
tHIPENABLE
INPUT

"':1.5V

CIO
N

TLIL/9232-2

~

"""
:::E
Q
.....
en

"""
:::E

READ/WRITE
INPUT

~

'AA I

'AA:::l

::~ - - - - - - - - - - -

OUTPUT

"'k.: 'v

(NOTE 1)

v"
WAVEFORM 2

YO"

(51 OPEN,
SZCLDSED)

TL/Ll9232-3

CIO
.....

Q

WAVEfORM 1

__

/'.,v

.....
en
:::E

"'1.5V

~

Q

~
II)

'v

~~~w~ 'v~~~-------",~1SV
__ J
__
.
_____ .

CIO
.....
(f)

..,.

'v

Access Time from Address Inputs

(NOTE 11 "'r.5V

TL/L/9232-4

FIGURE 1
Note 1: Waveform 1 is for the output with internal ccnditions such that the output is low except when disabled. Waveform 2 is for the output with Internal conditions
such that the output is high except when disabled.
Note 2: When measuring delay times from address inputs, the chip·enable input is low and the read/write input is high.

Note 3: When measuring delay times from chip-enable input, the address inputs are steady-state and the read/write input is high.
Note 4: Input waveforms are supplied by pulse generators having the following characteristics: tr ,; 2.5 ns. tf ,; 2.5 ns, PRR ,; 1 MHz and ZOUT

= :::

500.

DM74S289 Switching Time Waveforms
Enable and Disable Time from Chip-Enable

'v~,."

CHIP ENABLE
INPUT
(NOTE 3)

v::~''''-l~.5V

WAVEFORM I
(NOTE 1)

Write Cycle

-1,"':~
r-

ADDRESS
INPUTS

DATA

v.. ---------------"---------__-'

'v

'v

INPUTS

TL/L/9232-5

Access Time from Address Inputs
ADDRESS
INPUTS

CHIPENA&"c.

,

1 SV

1 5V

(NOTE Z) OV _ _ J

'- _____ .

'AA:::l
OH

OUTPUT V

'v

INPUT

3V~"'_ _ _ - - - - " , {

------

~SV

-'AA I

'v

__

READrWRITE

INPUT

'v

Y;.5V

Vo, _________________ _____________'_
~.

YO"
WAVEFORM 1
{NOTE II

TLlLl9232-6

I--""")<~

-'-'~

1.5V

1.SV

v"

TUU9232-7

FIGURE 2
Note 1: Waveform 1 is for the output with internal conditions such that the output is low except when disabled.

Note 2: When measuring delay times from address inputs, the chip-enable input is low and the read/write input is high.
Note 3: When measuring delay times from chip·enable input, the address inputs are steady·state and the read/write input is high.
Note 4: Input waveforms are supplied by pulse generators having the following characteristics: tr ,; 2.5 ns, tf ,; 2.5 ns, PRR ,; 1 MHz and ZOUT ::: 500.

2-10

Block Diagram

ADDRESS
INPUTS

64·BIT MEMORV
MATRIX
ORGANIZED
16.4

ADDRESS
BUFFERS

4

DATA INPUTS

{~: _6~10~

_ _t - _ + -..

12

D4------t--+--~~

11
VI
\

V2

V4,

V3

OUTPUTS

TL/L/9232-B

FIGURE 3

AC Test Circuits
DM54S189(A)/DM74S189(A)

DM74S289

Vee

TEST
POINT

Vee

FROM
OUTPUT _ ...____....._ ........- .
UNDER
TEST

RL1
FROM
OUTPUT _ _..._ _ _,
UNDER
TeST

TLlU9232-10

TUU9232-9

CL includes probe and jig capacitance.
All diodes are 1N3064.

FIGURE 4

2·11

~ Semiconductor
National

March 1987

Corporation

DM85S06 Open-Collector
DM75S07/DM85S07 TRI-STATE®
DM75S07A/DM85S07 A High Speed TRI-STATE
Non-Inverting, 64-Bit (16 x 4) RAMs
General Description
These 64-bit \ active-element memories are monolithic
Schottky-clamped transistor-transistor logic (TTL) arrays organized as 16 words of 4 bits each. They are fully decoded
and feature a chip-enable input to simplify decoding required to achieve the desired system organization. The
memories feature PNP input transistors that reduce the low
level input current requirement to a maximum of -0.25 mA,
only one-eighth that of a DM54S/DM74S standard load factor. The chip-enable circuitry is implemented with minimal
delay times to compensate for added system decoding.
The TRI-STATE output combines the convenience of an
open-collector with the speed of a totem-pole output; it can
be bus-connected to other similar outputs; yet it retains the
fast rise time characteristics of the TTL totem-pole output.
Systems utilizing data bus lines with a defined pull-up impedance can employ the open-collector DM85S06.
Write Cycle: The information at the data input is written into
the selected location when both the chip-enable input and
the read/write input are low. While the read/write input is
low, the outputs are in the high-impedance state. When a
number of the DM85S07 outputs are bus-connected, this
high-impedance state will neither load nor drive the bus line,
but it will allow the bus line to be driven by another active
output or a passive pull-up if desired.
Read Cycle: The stored information is available at the outputs when the read/write input is high and the chip-enable

Connection Diagram

is low. When the chip-enable is high, the outputs will be in
the high-impedance state.
The fast access time of the DM75S07A makes it particularly
attractive for implementing high-performance memory functions requiring access times less than 25 ns. The high capaCitive drive capability of the outputs permits expansion
without additional output buffering. The unique functional
capability of the DM75S07 outputs being at a high-impedance during writing, combined with the data inputs being
inhibited during reading, means that both data inputs and
outputs can be connected to the data lines of a bus-organized system without the need for interface circuits.

Features
• Schottky-clamped for high speed applications (75S07A)
Access from chip-enable input
17 ns max
Access from address inputs
25 ns max
• TRI-STATE outputs drive bus-organized systems and/or
high capacitive loads
• DM85S06 is functionally equivalent and has open-collector outputs
• DM75SXX is guaranteed for operation over the full military temperature range of - 55°C to + 125°C
• Compatible with most TTL logiC circuits
• Chip-enable input simplifies system decoding

Truth Table

Dual·ln·Llne Package
DATA

SELECT INPUTS

INPUT
III

V;c
~ I"

"

14

1J

12

Inputs
Function

DATA
OUTPUT
V4

INPUT
3

11

10

OUTPUT
Y3

Read/
Write

L

L

High-Impedance

Read

L

H

Stored Data

Inhibit

H

x

High-Impedance

Write

-

H

Output

Chip·
Enable

=

High Level. L

= Low Level. X = Don't Cere

Order Number DM75S07J, DM75S07AJ, DM85S06J,
DM85S07J, DM85S07AJ, DM85S06N,
DM85S07N or DM85S07AN
See NS Package Number J16A or N16E
SELECT CHIP
INPUT A ENABLE

READI
WRITE

DATA

OUTPUT

DATA

OUTPUT

INPUT
1

Y1

INPUT
2

YZ

G1:
TL/L/9231-1

Top View

2-12

Absolute Maximum Ratings (Note 1)

Operating Conditions

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, Vcc
Input Voltage
Output Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)

7.0V
5.5V
5.5V
- 65·C to + 150·C

Min

Max

Units

Supply Voltage (Vcc)
DM75S07(A)
DMB5S06/DMB5S07(A)

4.5
4.75

5.5
5.25

V
V

Temperature (TAl
DM75S07(A)
DMB5S06/DMB5S07(A)

-55
0

+125
+70

·C
·C

Typ

Max

Units

+300·C

DM85S06, DM75S07/DM85S07, DM75S07A/DM85S07 A
Electrical Characteristics
over recommended operating free-air temperature range unless otherwise noted (Notes 2 and 3)
Symbol

Parameter

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VOH

High Level Output
Voltage

Conditions

2

V
O.B

Vcc

High Level Output Current
Open-Collector Only

Vee

VOL

Low Level Output
Voltage

Vee

IIH

High Level Input Current

Vce

II

High Level Input Current
at Maximum Voltage

ICEX

Min

=

=
=

Min

IOH = -2.0 mA,
DM75S07(A)

2.4

3.4

V

IOH = -5.2 mA,
DMB5S07(A)

2.4

3.2

V

= 2.4V
= 5.5V
10L = 16 rnA
10L = 20 rnA

Min

VOH

40

",A

VOH

100

",A

0.45

V

Min

=
Vcc =

Max, VI

=

Max, VI

=
=

5.5V

Max, VI

=

0.40V

2.4V

IlL

Low Level Input Current

Vec

los

Short Circuit Output
Current (Note 4)

Vee = Max, Va = OV
DM75S07(A), DM85S07(A)

Icc

Supply Current (Note 5)

Vcc

=
=
=

-30
75

Max

=

V

0.5

V

10

",A

1.0

mA

-250

",A

-90

rnA

100

rnA

-1.2

rnA

40

",A

VIC

Input Clamp Voltage

Vee

IOZH

TRI-STATE Output Current,
High Level Voltage Applied

Vee
Max, Va = 2.4V
DM75S07(A), DMB5S07(A)

10ZL

TRI-STATE Output Current,
Low Level Voltage Applied

Vee = Max, Va = 0.4V
DM75S07(A), DMB5S07(A)

CIN

Input Capacitance

Vee = 5V, VIN = 2V,
TA = 25·C,1 MHz

4

pF

Co

Output Capacitance

Vcc = 5V, Va = 2V,
TA = 25·C,1 MHz
Output "Off"

6

pF

Min,ll

-18 rnA

2-13

-40

",A

DM75S07/DM85S07 Switching Characteristics
over recommended operating ranges of TA and Vee unless otherwise noted
DM75S07
Symbol

Parameter

Conditions
Min

DM85S07

Typ
(Note 1)

Max

Min

Units

Typ
(Note 1)

Max

tAA

Access Time from Address

25

50

25

35

ns

tcZH

Output Enable Time to
High Level

12

25

12

17

ns

12

25

12

17

ns

13

35

13

25

ns

13

35

13

25

ns

12

25

12

17

ns

12

25

12

17

ns

15

35

15

25

ns

15

35

15

25

ns

tcZL
twZH

Output Enable Time to
Low Level
Output Enable Time to
High Level

tWZL

Output Enable Time to
Low Level

tcHZ

Output Disable Time
from High Level

tcLZ

Output Disable Time
from Low Level

twHZ

Output Disable Time
from High Level

twLZ

Output Disable Time
from Low Level

Access Times from
Chip-Enable

CL = 30pF,
RL = 2800

(Figure 4)
Sense Recovery Times
from Read/Write

Disable Times from
Chip-Enable
CL = 5pF,
RL = 2800

(Figure 4)
Disable Times from
Read/Write

twp

Width of Write Enable Pulse (Read/Write Low)

25

25

ns

tASW

Set-Up Time (Figure 1)

Address to Read/Write

0

0

ns

tosw

Data to Read/Write

25

25

ns

tesw

Chip-Enable to
Read/Write

0

0

ns

Address from Read/Write

0

0

ns

tOHW

Data from Read/Write

0

0

ns

tcHW

Chip-Enable from
Read/Write

0

0

ns

tAHW

Hold Time (Figure 1)

J

"
2-14

DM75S07A/DM85S07 A Switching Characteristics
over recommended operating ranges of TA and Vee unless otherwise noted
DM75S07A
Symbol

Parameter

Conditions
Min

DM85S07A

Typ
(Note 1)

Max

Min

Typ
(Note 1)

Units
Max

tAA

Access Time from Address

20

30

20

25

ns

tcZH

Output Enable Time to
High Level

12

25

12

17

ns

12

25

12

17

ns

13

35

13

25

ns

13

35

13

25

ns

12

25

12

17

ns

12

25

12

17

ns

15

35

15

25

ns

15

35

15

25

ns

tCZl

Output Enable TIme to
Low Level

tWZH

Output Enable Time to
High Level

tWZl

Output Enable Time to
Low Level

tcHZ

Output Disable Time
from High Level

tCLZ

Output Disable Time
from Low Level

tWHZ

Output Disable Time
from High Level

Access Times from
Chip-Enable

Cl = 30pF,
Rl = 2800
(Figure 4)

Sense Recovery Times
from Read/Write

Disable Times from
Chip-Enable
Cl = 5pF,
Rl = 2800
(Figure 4)
Disable Times from
Read/Write

tWLZ

Output Disable Time
from Low Level

twp

Width of Write Enable Pulse (Read/Write Low)

tASW

Set-Up Time (Figure 1)

25

<

20

ns

Address to Read/Write

0

0

ns

tosw

Data to Read/Write

25

20

ns

tcsw

Chip-Enable to
Read/Write

0

0

ns

Address from Read/Write

0

0

ns

Data from Read/Write

0

0

ns

tAHW

Hold Time (Figure 1)

tOHW

Chip-Enable from
tcHw
0
ns
0
Read/Write
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of Ihe device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.

Note 2: Unless otherwise specified minImax limits apply across the - 55'C to + 125"C temperature range for the DM75S07(A) and across the O'C to + 70'C range
for the DM85S07(A). All typicals are given for Vee = 5.0V and TA = 25'C.
Note 3: All currents into device pins shown as positive. out of device pins as negative, all voltages referenced to ground unless otherwise nOled. All values shown
as max or min on absolute value basis.

Note 4: Only one output at a time should be shorted.
Note 5: lee Is measured with all inputs grounded; and the outputs open.

2-15

DM75S07(A)/DM85S07(A) Switching Time Waveforms
Enable and Disable Time from Chip-Enable
3V---,

CHIP ENABLE
INPUT (NOTE 3)

~-------4-~----~-----------'

,-.L..

+ ___

"".5V _ _ _ _
WAVEFORM I
(NOTE I)

VOL---------t---------7~------------i--C-~~~

VOH--------~---------r~--~---------4--~-----_L_

WAVEFORM 2
(NOTE I)

"".5V - - - - - - - - : . . . - - - - , , TLlL/9231-2

Access Time from Address Inputs
ADDRESS
INPUTS
(NOTE 2)

3V~_-_-----~
,

OV _ _ J

I~

I~

tAA::/

'------.

tAAI _

OH - - - - - - - - ~5V
~t'1.5V
VOL __________
______--J
__

OUTPUT V

~~.

TLlLl9231-3

Write Cycle

3V

ADDRESS
INPUTS

3V----~-------4----~

DATA
INPUTS

OV--3V
CHIP ENABLE
INPUT
OV
3V
READIWRITE
INPUT
OV
"".5V

- - - - - - t - - - - h......-+---...;;:;;;...,-+---.l

O.&V

WAVEFDRM I
(NOTE 1)

VOL-------~----~~~
WAVEFORM 2

~~

OH

V

-----------,;..,----_,.-l----....L

:t

IwZHJf
2

52 CLOSED)
(NOTE 1) "".5V _ _ _ _ _ _ _ _ _ _ _ _~_....I._ _ _ _ _ _ _ _:...-..;0::r.5V

TLlL/9231-4

FIGURE 1
Note 1: Wavelorm I Is for the output with internal conditions such that the output Is low except when disabled. Waveform 21s for the output with Internal conditions
such that the outpulls high except when dissbled.
Note 2: When measuring delay times from address inputs, the chip-enable Input is low and the read/wrile input is high.
Note 3: When measuring delay times from chip-enable Inpul. the address Inputs are sleady-stele and Ihe read/write inpul is high.
Note 4: Input waveforms are supplied by pulse generators having Ihe following characteristics: t,. :s: 2.5 ns. tr :s: 2.5 ns. PRR :s: 1 MHz and ZOUT

2·16

= '" son.

c

!!:
co

DM75S06/DM85S06 Switching Characteristics

UI

over recommended operating ranges of TA and Vcc unless otherwise noted

en
0

DM75S06
Symbol

Parameter

Conditions
Min

tAA

Access Times from Address

tCHL

Enable Time from
Chip-Enable

Typ
(Note 1)

Max

25

CL = 30pF,
RL1 = 3000,
RL2 = 6000
(Agure4)

Sense Recovery Time
from Read/Write

DM85S06
Units

Typ
(Note 1)

Max

50

25

35

ns

12

25

12

17

ns

13

35

13

25

ns

Min

twHL

Enable Time from
Read/Write

tcLH

Disable Time from
Chip-Enable

twLH

Disable Time from
Read/Write

twp

Width of Write Enable Pulse (Read/Write Low)

25

25

ns

tASW

Set-Up Time (Figure 2)

Address to Read/Write

0

0

ns

tosw

Data to Read/Write

25

25

ns

tcsw

Chip-Enable to
Read/Write

0

0

ns

Address from Read/Write

0

0

ns

tOHW

Data from Read/Write

0

0

ns

tcHW

Chip-Enable from
Read/Write

0

0

ns

12

25

13

12
13

35

20
25

en
.....
C
!!:
.....
UI

en

0
.....
.....
C
!!:
.....
UI

U)

ns

0
.....
.....

ns

!!:
co

;a:.
C

UI

U)

0
.....
.....

C

!!:
co
UI

U)

tAHW

Hold Time (Figure 2)

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device
operation.
Note 2: Unless otherwise specified minImax limits apply across the -55'C to + 125'C temperature range for the DM75S07(A) and across the O'C to + 70'C range
for the DM85S07(A). All typlcals are given for Vee = 5.0V and TA = 25'C.
Note 3: All currents into device pins shown as pesRive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Icc Is measured with all inputs grounded; and the outputs open.

DM75S06/DM85S06 Switching Time Waveforms
Enable and Disable Time from Chip-Enable
CHIP ENABLE
INPUT
(NOTE 3)

3V

-1~

L~~,t
~

ov
VOH

WAVEFORM 1
(NOTE 1)

'J,:-

1.5V

1.5V

VOL

TLILI9231-5

Access Time from Address Inputs
3V~
_ _ _ _ _ _ _ _ "",~

AODRESS
INPUTS
,
(NOTE 2) OV-_J

1.5V

1.5V
'- _____ •

tAA:::::I

OUTPUT

VOH~.5V
VOL __________________

~.~.

tAA

~
1.5V

______________'_
TUL19231-6

FIGURE 2

2-17

0
.....
;a:.

DM75S06/DM85S06 Switching Time Waveforms (Continued)
Write Cycle
3V

ADDRESS
INPUTS

3V
DATA
INPUTS

3V

CHIPENA8LE
INPUT
OV
3V
READ/WRITE
INPUT
OV

"'~

VOM
WAVEFORM 1
(NOTE 1)

I.SV

VOL
TLlLl9231-7

FIGURE 2 (Continued)
Note 1: Waveform 1 Is for the output with internal condition. such thai the output I. low except when disabled.

Note 2: When measuring delay time. from addre.. inputs, \he chip-enable Input i. low and Ihe read/wrile inpul i. high.
Inpu~ Ihe addreBB Inputs are steady-state and \he read/write Input I. high.
Note 4: Input waveforms are supplied by pulse generators having \he following characteristics: Ir ~ 2.5 ns, If ~ 2.5 ns, PRR ~ 1 MHz and lour := 500.

Note 3: When measuring delay limes from chlp-enable

Block Diagram

ADDRESS
INPUTS

54-81T MEMORY
MATRIX
ORGANIZED

ADDRESS
BUFFERS

16x4

DATA INPUTS

{:~

4
_1==O_ _

-II--I~

i -__~

D4_1~Z____~__

11

,Yl

yz

Y3

OUTPUTS

FIGURE 3

2-18

Y4,
TL/Ll9231-B

c

:s:::

AC Test Circuits

CD

en

en
C)

DM75S06/DM85S06

en
.....
c
:s:::
.....

Vee

FROM
O::~~~

f§

.....
.....

__+ __..,

c
:s:::
.....

TEST

TLlLl9231-9

~
c

:s:::
CD

en

en
C)

DM75S07(A)/DM85S07(A)

.....
.....

Vee

c

TEST

:s:::

POINT

CD

en

FROM

en
~

O::~~~ -41~-~"-+1........_ .
TEST
I...... ~,

C)

-r1.Dk

~~

~~
TL/Ll9231-10

CL includes probe and jig capacitance.
All diodes are 1N3064.

FIGURE 4

2-19

National
Semiconductor
Corporation

_

March 1987

DM75S68/DM85S68/DM75S68A/DM85S68A
16 X 4 Edge Triggered Registers
General Description

Features

These Schottky memories are addressable "0" register
files. Any of its 16 four-bit words may be asynchronously
read or may be written into on the next clock transition. An
input terminal is provided to enable or disable the synchronous writing of the input data into the location specified by
the address terminals. An output disable terminal operates
only as a TRI-STATEIII> output control terminal. The addressable register data may be latched at the outputs and retained as long as the output store terminal is held in a low
state. This memory storage condition is independent of the
state of the output disable terminal.

•
•
•
•
•
•
•
•
•

On-chip output register
PNP inputs reduce input loading
Edge triggered write
High speed-20 ns typ
All parameters guaranteed over temperature
TRI-STATE output
Schottky-clamped for high speed
Optimized for register stack applications
Typical power dissipation-350 mW

All input terminals are high impedance at all times, and all
outputs have low impedance active drive logic states and
the high impedance TRI-STATE condition.

Logic and Block Diagram
IDATA INPUTS)
02
DJ
1

(WRITE CLOCK INPUT)

Pin Names

CLK
14

"

Ao-Aa

Address Inputs

01-0 4

Data Inputs

01-04

Data Outputs

(WAITt ENABlEI

WE

Write Enable

m~15~~______________~~~~~~~~~--~

ClK

Write Clock Input

OS

Output Store

00

Output Disable

. ~y-

Al~
1&.4MEMQRY CElL ARRAY

A'~

OD WE

A3~

0

X

X

0

0

X

CLK

X

1 Read Data

Data Stored in
Addressed Location

0 Output Store High Impedance State
1 Output Disable High Inpedance State

1

X

X

X

X

STORE)

o~

"

aD~)o~~~-------+~------~~------~

(OUTPUTS)

TL/F/9233-1

2-20

OUTPUTS
Data From Last
Addressed Location
Dependant on State
ofODendCi!l

1

IOUTPUT
DISABLE)

MODE

o Output store

../ X Write Data

13

'~~~U=T----~-----1--~----~~~----~-+~----'

OS

X

Low Level

1

= High Level

X

~

Don't Care

Absolute Maximum Ratings (Note 1)

Operating Conditions

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7.0V
Input Voltage
5.5V
Output Voltage
5.5V
Storage Temperature Range
- 65·C to + 150·C
Temperature (Soldering, 10 sec.)
300·C

Supply Voltage, Vee
DM85S68/DM85S68A
DM75S68/DM75S68A
Temperature, TA
DM85S68/DM85S68A
DM75S68/DM75S68A

Min

Max

Units

4.75
4.5

5.25
5.5

V
V

0
-55

70
+125

·C
·C

Electrical Characteristics
over recommended operating free-air temperature range unless otherwise noted (Notes 2 and 3)
Symbol

Parameter

Conditions

Min

Typ

Max

Units

'0

VIH

High Level Input Voltage

Vil

Low Level Input Voltage

VOH

High Level Output Voltage

VOL

Low Level Output Voltage

2

Vee = Min

Vee = Min,
10l = 16mA

2.4

V

10H = -5.2 mA,
DM85S68/DM85S68A

2.4

V

DM75S68/DM75S68A

0.5

V

DM85S68/DM85S68A

0.45

V

25

p.A

50

p.A

Clock Input

-500

p.A

All Others

-250

p.A

-55

mA

100

mA

High Level Input Current

Vee = Max, VIH = 2.4V

II

High Level Input Current
at Maximum Voltage

Vee = Max, VIH = 5.5V

III

Low Level Input Current

Vee = Max,
Vil = 0.5V

los

Vee = Max, VOL = OV

-20

lee

Supply Current

Vee = Max

Vie

Input Clamp Voltage

Vee = Min, liN = -18 mA

loz

TRI-STATE Output Current

Vee= Max

V

10H = -2.0 mA,
DM75S68/DM75S68A

IIH

Short Circuit Output Current
(Note 4)

V
0.8

70

Vo = 2.4V

-1.2

V

+40

p.A

-40
p.A
Vo = 0.5V
Nole 1: "'Absolute Maximum Ratings"' are those values beyond which the safety of the device cannot be guaranteed. Except for "'Operating Temperature Range"'
they are not meant to imply that the devices should be operated at these limits. The table of "'Electrical Characteristics"' provides conditions for actual device
operation.
Nate 2. Unless otherwise specified minImax limits apply across the -55'C to + 125'C temperature range for the DM75Se8/DM75Se8A and across the O'C to
+ 70'C range for the DM85S68/DM85Se8A. All typlcals are given for Vee = 5.0V and TA = 25'C.
Note 3: All currents into device pins shown as positive, out of device pins as negative. all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute valUB basis.
Nale 4: Only one output at a time should be shorted.

Switching Characteristics
Symbol

over recommended operating range of TA and Vee unless otherwise noted

Parameter

DM75S68
Min

Max

DM85S68
Min

Max

DM75S68A

DM85S68A

Min

Min

Max

Units

Max

tZH

Output Enable to High Level

40

35

40

35

ns

tZl

Output Enable to Low Level

30

24

30

24

ns

tHZ

Output Disable Time from High Level

35

15

35

15

ns

tLZ

Output Disable Time from Low Level

35

18

35

18

ns

tAA

Access Time

Address to Output

55

40

45

24

ns

tOSA

Output Store to Output

35

30

35

20

ns

teA

Clock to Output

50

40

50

35

ns

2-21

Switching Characteristics
over recommended operating range of TA and Vee unless otherwise noted (Continued)
Symbol

Min
tASC

Set-UpTime

, tose

DM85S68

DM75S68

Parameter

Max

Min

Max

DM75S68A

DM85S68A

Min

Min

Max

Units

Max

Address to Clock

25

15

25

15

ns

Data to Clock

15

5

15

5

ns

30

40

10

ns

Address to Output Store

40

twESC

Write Enable Set-Up Time

10

5

10

5

ns

tossc

Store before Write

15

10

15

10

ns

Address from Clock

15

10

15

10

ns

Data from Clock

20

15

20

15

ns

tASOS

tAHC
tOHC

Hold TIme

tAHOS

Address from Output Store

10

5

10

2

ns

tWEHC

Write Enable Hold TIme

20

15

20

10

ns

Connection Diagram
Dual·ln·Llne Package

1~18
-Vee

oz-

17

Ol..!.

_03

AU.!

r!! D4

4
AZ5
A3-

~Wl

AI.!

~OS

012.

~OD

OZ"!'

~04

GND..!

~03

14

~eLK

13_

TL/F/9233-2

Top View
Order Number DM75S68J, DM85S68J,
DM85S68N, DM75868AJ,
DM85S68AJ or DM85S68AN
See NS Package
Number J18A or N18A

2-22

AC Test Circuit and Switching Time Waveforms
5.0V

OUTPUT

CL
CL

~
~

5.0 pF for tHZ. tLZ
SO pF for all others

CL includes probe and jig capacitance

DM75S681
DM65S681
DM75568A1
DM85S68A

All diodes are 1NS064

TL/U9233-3

Write Cycle

Read Cycle

Clock Set-Up and Hold Time

Address to Output Access Time

r---~

ADDRESS
INPUT

1.5v\.r----------

ADDRESS

1.5V

INPUT

DATA
INPUT

}!\

-- - -./I_tAA -\

OUTPUTS _

_____

r-------

..:~'('-_ _ _ _ _ __

TUL/9233-6

--::xr --,

Output Store Access, Set-Up and Hold Time
DUTPUT
STORE

ADDRESS
INPUTS

1.5V

__ J .
WRITE
ENABLE

WRITE
CLOCK

OUTPUT
STORE

-----~

'J
If.. 1.5V
1-IAHos~I'--- ----1.5V

OUTPUTS
TUU9233-4

TL/L/9233-7

Clock to Output Access

I~~~~

1. 5V

X-----------

----./
WRITE
CLOCK

OUTPUTS

Output Disable and Enable Time
DUTPUT
DISABLE

.

' 1 Word

H

tpRFL

RC to FLAG Low
Transparent D to a

Empty, WC

tpwo

WC Rising to a

tpMIH

MRtolRHigh

tpMOL

MRtoORLow

tpMFL

MR to FLAG Low

H

L

63 Words, WC

tpoo

=

=

H

27

36

34

45

ns

Empty

34

45

ns

Full

28

38

ns

15

20

ns

28

38

ns

=

H

Pin Description
Vee
DO-D7

Standard Test Load

Supply voltage.

SV

8-bit data input bus.

iF

00-07 8-bit data output bus (non-inverted).
WC

RC

IR

OR

Write Clock input-latches in data word from
D-bus on a high-to-Iow transition (except when
FIFO is full). Data enters the memory while WC is
high.

OUTPUT

R2

--

Read Clock input-presents next data word onto
a-bus on a low-to-high transition (except when
FIFO is empty).

30 pr

IOL

R1

R2

8mA

5600

11000

4mA

11000

22000

....w

Input Pulse AmplHude = 3V
Input Rise and Fall Time (10%90%) = 2.5 ns
Measurements made at 1.5V

TULl8876-10

Functional Description

Input Ready status output-when high indicates
FIFO is ready for another write cycle, ie., FIFO is
not full. IR is forced low whenever WC is high (except during 64th write cycle) to accommodate cascading.

The NFT FIFO is implemented using a 64 x 8-bit RAM with
separate write and read ports. The write port is addressed
by the write pointer and the read port by the read pOinter.
While the WC input is high, a data word on the D inputs is
written into the write port of the RAM. The write pOinter
(initially zero) is incremented on the falling edge of WC, thus
concluding a write cycle. The RAM contents addressed by
the read pointer (also initially zero) are always presented on
the a outputs. Thus the first word appears on the a outputs
as it is being written. The rising edge of RC increments the
read pOinter which then accesses the next data word from
the RAM's read port.

Output Ready status output-when high indicates
FIFO is ready for another read cycle, ie., FIFO is
not empty. OR is forced low whenever RC is low
to accommodate cascading.

MR/FS Master Reset/FLAG Select input-resets the
FIFO to the empty state (internal pOinters reset to
zero) on either a low-to-high or high-to-Iow transistion. The state of the MR/FS input during operation selects the waveform to be presented on the
FLAG status output.
FLAG

TEST
POINT

U1

><
~

tpRO

=

co

When the value of the write pOinter equals the read pOinter,
then the FIFO is empty, ie., any data words which had been
written have also been read. When the value of the write
pointer exceeds the read pOinter by 64, then the FIFO is full,
ie., the next RAM location into which data should be written
contains the oldest word that has not yet been read.

Intermediate status FLAG output-if MR/FS input
is low, then a high output on FLAG indicates FIFO
is at least one quarter filled (16 or more words
remaining in memory). If MR/FS is high, then a
high output on FLAG indicates FIFO is at least
three quarters filled (48 or more words remaining).

The IR and OR status outputs indicate the full and empty
conditions, respectively. When WC is brought low at the end
of a write cycle, IR would go high if the FIFO is still not full. If
the FIFO becomes full, IR would become low until a vacant
3-5

•

...-><
C")

II)

CD

i2::E

Q

r-------------------------------------------------------------------------~

Functional Description (Continued)
RAM location is made available resulting from a read operation (or the Master Reset is activated). WC should remain
low until IR goes high. If WC is brought high while IR is still
low, then the entire write cycle would be ignored, the RAM
contents and write pOinter remaining unchanged.

",WORDS
STORED

IR is usually driven low whenever WC is high in order to
accommodate cascading as described later. However, during the final write cycle (in which the last vacant location is
being written) IR would remain high if and as long as RC is
high. This is to provide sufficient cycle times to guarantee
the proper transfer of data between cascaded devices while
reading.

FLAG OUTPUT
MR/FS = L

MR/FS = H

0-15

L

L

16-47

H

L

48-64

H

H

The FLAG output remains stable throughout all write and
read cycles which do not cross the above boundaries. Note
that the FLAG waveform selection cannot be switched without resetting the FIFO.
In a system, MR/FS may be connected to either a normallylow or normally-high system reset signal. Even though the
FIFO responds to input transitions, conventional system reset pulses, including wakeup circuits, would produce desired
results.

The OR output would go high after the rising edge of RC if
the FiFO remains not empty. OR is initially low following a
reset until the first word is written into the FIFO. RC should
remain high until OR goes high. If RC is brought low before
OR goes high, then the read cycle would be inhibited and
the next rising edge of RC would not increment the read
pointer.

FIFO buffers wider than 8 bits can be implemented by connecting multiple chips in parallel. For 64 x 8n configurations, the IR, OR and FLAG status information can be taken
from anyone of the chips since there is no fall-through delay which may otherwise cause output skew between chips.

The FIFO resets to the empty state (write and read painters
reset to zero) on either the rising or falling edge of the
MR/FS input. Following a reset, IR will be high, provided
WC is low, OR and FLAG will be low. WC and RC may be in
either state when a reset occurs.

FIFO buffers deeper than 64 words can also be implemented by connecting multiple chips in series. To do this, the Q,
OR and RC lines of one chip are connected to the D, WC
and IR lines, respectively, of the next chip in the series (see
"Cascading Devices" block diagram). When the first word is
written into the first chip, the resulting rising edge of its OR
initiates a write cycle into the second chip, which in tum
produces a read cycle from the first chip. The handshaking
signals passed over the OR/WC and RC/IR connections
between each adjacent pair of chips causes the data word
to be passed from one chip to the next until it settles onto
the outputs of the last chip in the series. See "Cascaded
Write Cycle Waveform" diagram.

If WC is high following a reset, the first write cycle would not
commence until after WC is returned low (a high output on
IR must be observed before the FIFO performs any write
cycle). Likewise, if RC is low following a reset, the first read
cycle would not commence until RC is returned high and a
high output is observed on OR (returning RC high does not
advance the read pointer).
The FIFO may be operated while the MR/FS input is held
either low or high. The state of the MR/FS input during operation selects one of two waveforms to appear on the
FLAG status output.

As the buffer fills, each chip, beginning with the last, becomes full. A buffer consisting of n chips connected in series can store 63n + 1 words. This is because the last word '
written into each full chip (except the first chip) remains on
the outputs of the previous Chip. Each time a word is read
from the last chip, one word is transferred down from each
of the previous chips (or until an empty chip is encountered).
See "Cascaded Read Cycle Waveform".
Write Cycle Timing Waveform

If the FIFO is operated while the MR/FS input is held low,
then the FLAG output would indicate when the FIFO is at
ieast one quarter filled, i.e., when the write pointer value
exceeds the read pointer by at least 16. If the FIFO is operated while MR/FS is high, then FLAG would indicate when
the FIFO is at least three quarters filled, as shown in the
following truth table:

LZZZ2lX
#1
XII/11/)//IIII!11/)/1/1114 _---:.;'6.;,.4_-,XII)II/(//
~~ TI tH~---,
we J . I
\
/----lH.J
\'--__
~t~llJ
FIPWIHi
[tPWUl'J
IR
I L \
/---\.J~
.... __________ L
L:: 1:::=1 I
tpRll' J (FUll)
QWI1/f1l/11J%.X
#1
~~~_ _ _ _~I_ ___
D

r

I--IPWOH ---J

OR _ _ _ _ _ _ _ _ _-..J/I"-----l

Re--------------~s ~S- - - - - \
'IR goes low following the first 01 these two events.

-----

3-6

TLlL/8876-3

c
s:::
.....

Functional Description (Continued)
Since the control signals and data are passed from chip to
chip in a serially cascaded buffer, some fall-through delay is
introduced between the input of the first chip and the output
of the last. The delay increases with the number of chips
cascaded serially.

Chips can be cascaded both serially and in parallel to produce deeper and wider buffers (as shown in "Cascading
Devices" block diagram). However, due to the resulting
chip-level fall-through delays, it may be necessary to ANDgate the IR outputs of the first level of chips, as with the OR
outputs of the last level.

U1
......
c»
U1

...~
W

Read Cycle Timing Waveform
~ tWRL

RC - - " ' "

--0'-1-'1'0--- tWRH ~

''''''----i r1

I

~""'J'_....;....r"""l-----""'
\
__1

~ ~

OR

.---

______,' _ __

~ tpRO --l

(Et.tPTY)
INVALID DATA ;;;,

-...;...------X. 1'---#-2---I(
(
.
~)

0 ------#-1

I.--

tpRIH

)(////Z

'#64

~

---+j

LAST DATA WORD WRlmN

--J,r-----iS i

IR _ _ _ _ _ _ _ _ _ _

TLlLl8676-4

Master Reset Timing Waveform

t.tR/FS

twt.t

:xI'

'I

WC"'

X

i-= tpt.tIH '"1

IR

Flag Output Timing Waveform

I

7

I-tPWFHi

I--tpt.tOL~

~

OR

I

RC

1
i- tPRFL"-1

I

FLAG

,

'-

TLlL/8676-5

I--tpt.tFL~
FLAG

X

0

1

I-tRt.tW

I

WC

TL/L/8S76-8

Cascading Devices
(190 x 16 Bit FIFO)
00-7
WC

0

0

0

0

WC

OR

WC

OR

IR

RC

IR

RC

0

0

WC

RC

IR

OR

IR
OPTIONAL

00-7

08-15
OR
OPTIONAL

3-7

•

RC

TL/Ll8676-7

_ r-----------------------------------------------------------------------,

CO)

;::an

Functional Description (Continued)

CD

ie
::a:

c

Write Cycle Waveform For
Two Devices Cascaded Serially
DEVICE DEVICE
iJl
112

~

~

X

/II

D

t

wc
Q- D

5

?wi
J

RC- IR

L

~\

#1

OR- WC

Q

i~

#2

wffijJ.i~

:;

I

(EMPTY)

/

)\
I
1/64

~

.•.......

i~

':Y

OR

#65

(FULL)

1/1

I

X

1164

sS
TL/Ll9876-8

Read Cycle Waveform For
Two Devices Cascade.d Serially
DEVICE DEVICE
111
1J2

~

~

IR

(

(FULL)
Q-

D

#64

RC- IR

RC

\X

#1

~
/X

~~

1165

1/

OR- WC

Q

SS

/

1J127

\-ss
/-

II

I #2

~~

~ ~

Ss

3-8

#64/

X

J......-

~X

?

(EMPTY)

1J65

\

X

~

#66

TLlLl8678-9

.------------------------------------------------------------------.0
_

National

PRELIMINARY

Semiconductor
Corporation

March 1987

a:

~
co

U'I

><

~
Co)

N
......

DM75/85X432 128 X 4, DM75/85X433 128 X 5,
No-Fall-Through FIFO Memories

o

a:
..,.

• Status outputs indicate full, empty and partially-filled
conditions
.. 18/20 pin 0.3" wide DIP package
• TTL 1/0 signal levels
• Single + 5V supply

General Description
The device is a first-in-first-out (FIFO) sequential memory
organized as 128 words by either 4 or 5 bits. Data words
written into the device are later read from a separate bus in
the same order as entered but at an independent rate. Write
and read operations may occur concurrently and at any time
with respect to each other. The FIFO is a no-fall-through
(NFT) type in which new input data becomes available for
output in less time than the minimum writelread cycle period.

~
co

U'I

~

Co)
Co)

Applications
.. Data rate translator for computer peripheral controller,
ego disc, tape, printer, graphic display, etc.
• Data rate translator for telecommunications or data
communications controller (including local area network)
I!! ADC or DAC interface buffer for real-time DSP
II Real-time data acquisition buffer
• Variable length shift register for real-time signal delay
• Variable length pipeline register for multiprocessing,
DSP, graphics, image analysis, etc.

Features
• 128 x 4/5 bit FIFO memory
• No fall-through delay (first word propagates to output in
less than one cycle period)
• 35 MHz write and read clock frequencies
• Totally independent asynchronous write and read
clocks
• 16 mA TRI-STATE® data outputs for bus drive
capability

Block and Connection Diagrams

Dual-In-Line Package

Q
Tl/l/9235-3

~--------------------------~TLll/9235-1

3-9

•

Absolute Maximum Ratings
Off-State Output Voltage
Storage Temperature
ESD Susceptibility (Note 4)

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
7V
Supply Voltage, Vee

5.5V
-65'C to + 150'C
To Be Determined

7V

Input Voltage

Electrical Characteristics Over Operating Conditions DM75/DM85X432/433
Symbol

Parameter

Guaranteed Limits

Conditions

Min

VIL

Low-Level Input Voltage

VIH

High-Level Input Voltage

VIC

Input Clamp Voltage

IlL

Low-Level Input Current

IIH

High-Level Input Current

II

Maximum Input Current

VOL

Low Level Output
Voltage

VOH

High Level Output
Voltage

0.8

V

-1.5

V

-0.4

rnA

2

= Min,ll = -18 rnA
Vee = Max, VI = 0.45V
Vee = Max, VI = 2.4V
Vee = Max, VI = 5.5V
10L = 16 mA for a Outputs
Vee = Min,
VIL = 0.8V,
10L = 4 rnA for F,
E and FLAG Outputs
VIH = 2V
10H = - 2.6 rnA for a Outputs
Vee = Min,
10L = -0.6 rnA for F,
VIL = 0.8V,
E and FLAG Outputs
VIH = 2V
Vee = Max, Vo = OV

V

Vee

los

Output Short-Circuit Current
(Note 1)

10ZH

High Voltage Off-State
Output Current

Vee

= 5.5V, VOH = 2.7V

IOZL

Low Voltage Off-State
Output Current

Vee

= 5.5V, VOL = 0.4V

50

p.A

1.0

rnA

0.5

V

2.4

V

-30

Vee = Max, Inputs Low,
Outputs Open
Note 1: Not more than one output should be shorted at a time and duration of the short-clrcuH should not exceed one second.

ICC

Units

Max

Supply Current

-80

rnA

20

p.A

-20

p.A

265

rnA

Operating Conditions (Note 3)
Symbol

Parameter

DM75X432/433

DM85X432/433

Min

Max

Min

Max

Units

Vee

Supply Voltage

4.5

5.5

4.75

5.25

V

TA

Operating Free-Air Temperature
(Note 2)

-55

+125

0

+70

'C

twwH

WC Pulse Width High

10

ns

tWWL

WC Pulse Width Low

15

ns

tsow

Input Data Setup

15

ns

tHOW

Input Data Hold Time

0

ns

!wAH

RC Pulse Width High

10

ns

tWAL

RC Pulse Width Low

10

ns

!wM

Master Reset Pulse Width

ns

Reset Recovery Time
ns
tAMW
2: Ambient Temperature.
Note 3: Since the FIFO is a very high speed device, cere must be taken In the design of the hardware. Proper device grounding and supply decoupllng are crucial to
the correct operation of the FIFO.
Note 4: Human body model, 100 pF discharged through a 1.5 kG rasistor.
Note

3-10

Switching Characteristics Over Operating Conditions
Symbol

Initial
Conditions

Parameter

DM75X432/433

DM85X432/433

Min

Min

Max

Units

Max

fwc

Write Frequency

35

MHz

fRC

Read Frequency

35

MHz

tpRQ

RC to Data Output

20

ns

tPWF

WC Rising to FLow

127 Words

15

ns

tpWE

WC Rising to E High

Empty

15

ns

tpRE

RC Rising to E Low

1 Word

15

ns

tpRF

RC Rising to F High

Full

15

ns

tPWI

WC Rising to FLAG High

20

ns

tpRI

RC Rising to FLAG Low

20

ns

tSRW

RC Rising Before WC

Full

ns

tswR

WC Rising Before RC

Empty

ns

tpDQ

Transparent D to Q

Empty, WC = Low

30

ns

tPWQ

WC Falling to Q

Empty

30

ns

tpMF

MR to F High

Full

30

ns

tpME

MRto E Low

30

ns

tpMI

MR to FLAG Low

30

ns

tpzx

Output Enable

20

ns

tpxz

Output Disable

20

ns

Pin Description
+5V supply.
Vee
00-03/4 4/5-bit data input bus.
00-03/44/5-bit data output bus (TRI-STATE non-inverted).
WC

RC

E

Write Clock input-latches in a data word from
D-bus on a low-to-high transition (except when
FIFO is full). Data enters the memory while WC is
low.

FLAG

Intermediate Status Flag Output-high while
FIFO is at least 1,4 filled (32 or more words remaining in memory) if the FS input is low, or while
FIFO is at least 3/4 filled (96 or more words) if FS
is high; otherwise FLAG remains low.

MR

Master Reset input-resets the FIFO to the
empty state (internal pointers reset to zero) while
low (level sensitive).
Output Enable input-when low, enables output
on the Q data bus; disables when high.

Standard Test Load
51

'~iF

Empty Status Output-goes low when last word
is read from FIFO (or when FIFO is reset); goes
high when first word is written into an empty FIFO.
Full Status Output-goes low when FIFO becomes full following a write; goes high when a
read cycle creates a vacancy (or when FIFO is
reset).

Flag Select Input-selects FIFO word-count
threshold for FLAG output (32 if low, 96 if high).

OE

Read Clock input-presents next data word onto
Q-bus on a low-to-high transition (except when
FIFO is empty).

F

FS

RI

OUlPUT

R2

-

3-11

~T

30 pF

TLlLl923S-B

IOL

R1

R2

16mA

3000

6000

4mA

11000

22000

Input Pulse Amplitude = 3V
Input Rise and Fall TIme (10%90%) = 2.5 ns
tpHZ measurement made at VOH
- 0.5V, tpLZ measurement made at
VOL + O.SV, all other measurements
made at 1.5V.

Functional Description
The FS input selects the waveform to appear on the FLAG
output. When FS is low, then the FLAG output indicates
when the FIFO is at least one quarter filled (i.e., when the
write pOinter value exceeds the read pointer by at least 32).
When FS is high, then FLAG indicates when the FIFO is at
least three quarters filled (write pOinter exceeds read pointer by at least 96). The FLAG output remains stable (without
glitches) except following the write or read cycle which
changes the FIFO's status with respect to the selected
threshold.

The RAM contents addressed by the read pointer (also initially zero) are presented on the Q outputs whenever the OE
input is low (Q bus outputs are disabled when OE is high).
Thus the first word may appear on the Q outputs as it is
being written. The rising edge of RC increments the read
pointer which then accesses the next data word from the
RAM's read port. (Each pointer automatically wraps around
from the last to the first RAM location.)
When the value of the read pOinter becomes equal to the
write pointer due to a read cycle, then the FIFO is empty, ie.
any data words which had been written have also been
read. When the value of the write pOinter exceeds the read
pointer by 128 due to a write cycle, then the FIFO is full, ie.
the next RAM location into which data should be written
contains the oldest word that has not yet been read.

It is recommended that the FS input be changed only while
the FIFO is empty or full. If FS is changed while the FIFO
contains between 32 and 96 words, the FLAG output may
not change to reflect the accurate status until a threshold is
crossed.

The E and F status outputs indicate the empty and full conditions, respectively. Initially (following a reset) F is high.
When WC is brought high at the end of any write cycle, F
would go low if the FIFO becomes full; otherwise it remains
high (without glitches). When the FIFO is full, F remains low
until a vacant RAM location is made available resulting from
a read operation (or the Master Reset is activated). F goes
high after the rising edge of RC which creates the first vacancy.
Writing is inhibited while F is low. If WC is brought low while
F was still low, new data would not begin to be written into
the RAM until after a read cycle causes F to go high (WC
must then remain low long enough to complete the write
cycle). Any low-to-high transitions on WC while F is low are
ignored (write pOinter not incremented).

FLAG Output Truth Table:
FLAG Output
# Words Stored

0-31
32-95
96-128

FS = L

FS= H

L
H
H

L
L
H

FIFO buffers wider than 4 or 5 bits can be implemented by
connecting multiple chips in parallel. The E, F and FLAG
status information can be taken from anyone of the chips
since there is no fall-through delay which may otherwise
cause output skew between chips.
FIFO buffers deeper than 128 words could also be implemented by connecting the D and Q lines of multiple devices
in parallel and alternating the WC and RC clocks between
each of the devices in turn (the OE input of each device
must then be connected to its own RC input). For example,
a 256 x 4/5 FIFO buffer could be implemented using two
FIFO chips plus a dual D-type flip-flop (eg. 74874) as shown
in the diagram, "External Cascading". Cascading more than
two devices (depth greater than 256) requires more sophisticated logic to generate the alternating WC and RC clocks;
registered programmable logic devices may be useful for
this. Note that when cascading in this manner, there are no
additional delays introduced. Also, the threshold boundaries
for the FLAG output are proportional to the number of devices cascaded.

Initially (followinig a reset) the E output is low. E remains low
while the FIFO is empty until the first write cycle is completed. E goes high after the rising edge of WC concluding the
first write cycle. When RC is brought high at the end of any
read cycle, E would go low if the FIFO becomes emtpy;
otherwise it remains high (without glitches).
Reading is inhibited while E is low. Any low-to-high transitions on RC while E is low are ignored (read pointer not
incremented). While the FIFO is empty, the Q outputs (if
enabled) would either be in an indetermined state if WC is
high, or would reflect D input data as it is written into the
memory if WC is low.
The FIFO is reset to the empty state (write and read pointers reset to zero) while the MR input is low. WC and RC
inputs are ignored and may be in either state during a reset.
If WC is low following a reset, it should remain low long
enough to complete the write cycle.

3-12

Functional Description (Continued)
External Cascading (256 x 4/5 FIFO)
NFT FIfO #1

4/5

4/5

QI---t---+-. Q
iiR-----1.....-

....



TL/U9235-4

Write Cycle Timing

tPWI1
FLAG

I~

----------~S~S----~I

-

r----I---_ _ _t_PW_FL

- - - - - - - - - I S !-oS----~S !S

-

TL/L/9235-5

Read Cycle Timing
(F5=L)

~~

RC
tPRQj
Q

II

X\.__..:#:.;;.2_ _ _m~~
S~

I--IpRF--j
(FULL>'

j

J

tpRI

D-INPUT

I-

-4S ~ S--+----

FLAG _ _ _ _ _ _ _ _ _ _ _ _ _

-----------~SS

~r

S~
TL/L/9235-6

3-13

Functional Description (Continued)
Reset and Miscellaneous Timing

we

r.: ~ 1~

~............;r
F'

(FULL)

'-u

....r

P----------------t-Rw--~t~

\~----~r_--------~----------J
I
(EMPTY)

FLAG

--~------~S

I-S- - - -

TLlLl9235-7

3·14

Section 4
ECLRAMs

•

Section 4 Contents
DEVICE
DM10414, DM10414A
DM10415, DM10415A
DM10422, DM10422A,
DM10422A-7
DM10470, DM10470A
DM10474A, DM10474A-10,
DM10474A-8
DM100422, DM100422A
DM100470, DM100470A
DM100474A, DM100474A-10,
DM100474A-8

DESCRIPTION

PAGE
NUMBER

256 x 1 Eel Random Access Memory ........•...•..•.•
1024 x 1 Eel Random Access Memory ................ .
1024-Bit (256 x 4) Eel RAM ..........................•

4-3
4-8
4-13

4096-Bit (4096 x 1) Eel RAMs ........................•
4096-Bit (1024 x 4) Eel RAMs ...............•..•..•...

4-19
4-24

1024-Bit (256 x 4) Eel RAM ....................•......
4096-Bit (4096 x 1) Eel RAMs .................•...•...
4096-Bit (1024 x 4) Eel RAM .....................•....

4-30
4-35
4-40

4-2

o

~ Semiconductor
NatiOnal

March 1987

0Iloo

Corporation

0Iloo
......
o

s::
....

DM10414/DM10414A
256 X 1 Eel Random Access Memory

o0Iloo

....
0Iloo

l>

General Description

Features

The DM10414, DM10414A is a 256-word by 1-bit ECl random access memory. The fully static memory is designed
with active low chip selects and separate I/O pins. Tha 8
address bits (AO through A7) are fully decoded on the chip.
Applications such as scratch pad, cache, and buffer memories are ideal for this high speed RAM.

• Fully compatible with standard and voltage compensated 10k series ECl
• Temperatura range
O'C to +75'C
• Unterminated emitter-follower output for wire-ORing
• Power dissipation decreases with increasing temperatura
• Typical addrass access
DM10414
10 ns
7ns
DM10414A
III Typical chip select access
DM10414
4ns
DM10414A
3 ns

An unterminated emitter-follower output is provided to allow
the outputs to be wire-ORed. Separate Data In and non-inverted Data Out pins are provided. These RAMs are compatible with compensated and uncompensated 10k ECl
families.

Block and Connection Diagrams
Dual-In-Llne Package
AO
AI
A2

16 Vcc

AO
ADDRESS
DECODER

s::
....
o
....

WORD
DRIVER

16 X 16 ARRAY

15 DDUT

AI

A3

14

A2

m

A3

m
rn

m

m

rn

6

m

10 AS

VEE

A4

TL/L/9236-2

Top VIew
Order Number DM10414J
or DM10414AJ
See NS Package J16A

A4 AS A6 A7

TUU9236-1

Pin Names

Logic Symbol
AO-A7

Address Inputs

DIN

Data Input

Dour

Data Output

CS1, CS2, CS3

Chip Select Inputs

WE

Write Enable

Truth Table
CS
H
l
l
l
L

WE DIN Dour

X

X

l
l
H

H
l

X

= low (-1.7V nominal)

H = high (- 0.9 nominal)

X = don't care

TUL/9236-3

4-3

MODE

Not Selected
Write 1
Write 0
Dour Read
l
l
l

....g~

....
::::E

Q
......

•....g
....
::::E
Q

Output Current (Output High)
-30 mA to +0.1 mA
Lead Temperature (Soldering. 10 sec.)
300'C

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications•
Temperature Under Bias (ambient)
- 55'C to + 125'C
Storage Temperature Range

Operating Conditions

-65'Cto + 1500C
-7.0Vto +0.5V

VEE Relative to Vcc
Any Input Relative to Vcc

Supply Voltage (VEE)
Ambient Temperature (TN

Min

Max

Units

-5.46
0

-4.94
+75

V
·C

VEE to +0.5V

DC Electrical Characteristics
VEE

=

-5.2V. Output Load

Symbol
VOH

VOL

VOHC

VOLC

VIH

VIL

=

50n and 30 pF to -2.0V, TA

Output Voltage Low

Output Voltage High

Output Voltage Low

Input Voltage High

Input Voltage Low

O'C to + 75'C (Notes 1-3)

Conditions

TA

Min
Limit

Max
Limit

Units

VIHMAX or VILMIN

O'C
+25"C
+ 75'C

-1000
-960
-900

-840
-810
-720

mV

O'C
+ 25'C
+ 75'C

-1870
-1850
-1830

-1665
-1650
-1625

mV

VIN = VIHMIN or VILMAX
Performed on One Input
at a TIme

O'C
+25'C
+75'C

-1020
-980
-920

VIN = VIHMIN or VILMAX
Performed on One Input
at a TIme

O'C
+25'C
+ 75'C

Guaranteed I,"put Voltage High
for All Inputs

O'C
+ 25'C
+ 75'C

Guaranteed Input Voltage Low
for All Inputs

O'C
+ 25'C
+ 75'C

Parameter
Output Voltage High

=

VIN

VIN

=

=

VIHMAX or VILMIN

mV
-1645
-1630
-1605

mV

-1145
-1105
-1045

-840
-810
-720

mV

-1870
-1850
-1830

-1490
-1475
-1450

mV

220

/LA

170

/LA

IIH

Input Current High

VIN = VIHMAX Performed
on One Input at a TIme

O'Cto
+ 75'C

IlL

Input Current Low,
CS All Others

VIN = VILMIN Performed
on One Input at a Time

OOCto
+ 75'C

0.5
-50

lEE

Power Supply Current
(Pin 8) (Note 4)

All Inputs and Outputs Open

OOCto
+ 75'C

-150

mA

Note 1: Conditions for testing not shown in the tables are chosen to guarantee operation under "worst case" conditions.
Note 2: The specified limits represent the "worst case" value for the parameter. Since Ihess "worst case" values normally occur at the temperature extremes,
additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
Note 3: Guaranteed wilh Iransverse air flow exceeding 500 linear F. P. M. and 2·minule warm·up period. Typical resistance values of the package are: 8JA,
(Junction to Ambient) = 90'C/W (still air); 6JA (Junction to Ambient) = SO'C/W (at SOD F. P. M. air flow); 6JC (Junction to Case) = 25'C/W.
Note 4: Typical values at VEE

= - S.2V: TA = O'C, lEE =

-105 mA; TA = 7S'C, lEE

4·4

= - 90 mAo

.-----------------------------------------------------------------------,0
Functional Description
Addressing the DM1 0414, DM1 0414A is achieved by means
of the 8 address lines AO-A7. Each of the 28 one-zero combinations of the address lines corresponds to a bit location
in the memory. The active low Chip Selects together with
the unterminated emitter-follower output allows for wire-ORing. A 50n resistor to - 2V (or an equivalent network) is
required to provide a low at the output when the device is
off. This termination is required for both single device or
wire-ORed operation.

The device is selected with CS low and deselected with CS
high. The operating mode is controlled by the active low
Write Enable (WE). WE low causes the data at the Data
Input (DIN) to be stored at the selected address. WE low
also causes the output to be disabled (low due to the 50n
pull-down resistor). WE high causes the data stored at the
selected address to be present at the Data Out (DOUT) pin.

!!:
.....
o
~

.....
......
o
!!:
.....
g.....
~

:=

AC Electrical Characteristics
VEE

= -

± 5%, Output Load = 50n, 30 pF to - 2.0V, T A = O'C to 75'C, air flow exceeding 500 LFM

5.2V

TEST CONDITIONS

loading Conditions
GTND
16

_

AD
AI

-

A2

-

A3

Vee

-~
'r
-1.7V

-A4
-

Inputs Levels

DDUT t-:':.:,S..._ _--.

AS

Ira If= Z.o ns TVP
TL/L/9236-9

-A6

All timing measurements referenced to 50% of input levels
GL = 30 pF including jig and stray capacitance

RT =

-

A7

-

A8

-

A9

,

son

RT

VEE

-z.OV
TUL/9236-8

Symbol

Parameter

DM10414A
Min

DM10414

Max

Min

Units
Max

READ MODE

ns

Address Access Time (Note 5)

10

15

Chip Select Access Time

5

7

ns

Chip Select Recovery Time

5

7

ns

Note 5: The maximum address access time is guaranteed to be the worst-case bit in the memory using a pseudorandom testing pattern.

III
4-5

..
..

~
.Switching Time Waveforms
o.-

Chip Select Access Time

:::i
C

\sO%

~

~
.o
.-

L-,RCS

tACS~

1.-

DATA OUTPUT

:::i

Q

50%

--l ~If

I

TL/Ll9236-4

Address Access Time

EW1~

ADDRESS INPUTS

DATA OUTPUT

TL/L/9236-5

Read Mode
ADDRESS INPUTS

.-::::J

I

-mnrmT"

DATA INPUT _

I

50%',

I

..

~~~ ~

WRmmm~.

--

61~

DATA OUTPUT

IACS __

--

I--

--

twSA

\

tRes

I--

TL/Ll9236-6

AC Electrical Characteristics (Continued)
VEE

= -5.2V ±5%, Output Load = 50n, 30 pF to -2.0V, TA = O'C to 75'C, 500 LFM
Symbol

DM10414A

Parameter

Min

DM10414

Max

Min

Units
Max

WRITE MODE
tw

Write Pulse Width

6

8

ns

twso

Data Set-Up Time
Prior to Write

2

2

ns

twHO

Data Hold Time
After Write

2

2

ns

twSA

Address Set-Up Time
Prior to Write

3

4

ns

tWHA

Address Hold Time
After Write

2

3

ns

twscs

Chip Select Set-Up
Time Prior to Write

2

2

ns

tWHCS

Chip Select Hold Time
After Write

2

2

ns

tws

Write Disable Time

5

7

ns

tWR

Write Recovery Time

5

7

ns

4-6

Ie

Switching Time Waveforms

s:::
....
o
a.
....
a.

(Continued)
Write Mode

ADDRESS INPUTS~
AO-A7--..:....J

....Ie

\

s:::
....
a.
....

Jf\-

o

mnrrm

50%\

ffi.m.rn

DATA INPUT
DIN

:t

I

"-

t:~

50%\/

'/

I---twWRITE ENABLE

50%\

WE

C-tWSD-1\

I

-tWSCSDATA DUTPUT
DDUT

tWHCS

-twHA---j

50%

r--twSA-

I--tws

- ::;;;;;
TL/L/9236-7

AC Electrical Characteristics (Continued)
VEE

=

-5.2V ±5%, Output Load

Symbol

I

=

500,30 pF to -2.0V, TA

I

Parameter

=

O·C to 75·C, 500 LFM

DM10414A

I

Min

Max

J

1

3,5

1

3.5

I
I

Min

Max

I

1

3.5

ns

1

3.5

ns

DM10414

Units

RISE TIME AND FALL TIME
tT
tf

I

I

Output Rise Time
Output Fall Time

I

I

Capacitance
DM10414A
Symbol

Parameter

CIN

Input Pin Capacitance

COUT

Output Pin Capacitance

Conditions

Min

Measure With a Pulse
Technique

4-7

Typ
(Note 5)

DM10414
Max

Min

Typ
(Note 5)

Max

Units

4

5

4

5

pF

7

8

7

8

pF

~
:; •
:E

National
Semiconductor
Corporation

i

DM10415/DM10415A

~

....Qan

April 1987

iQ 1024 X 1 Eel Random Access Memory
General Description

Features

The DM10415, DM10415A is a 1024-word by 1-bit ECL random access memory. This fully static memory is designed
with an active low chip select and separate 1/0 pins. The 10
address bits (AO through A9) are fully decoded on the chip.
Applications such as scratch pad, cache, and buffer memories are ideal for this high speed RAM.
An unterminated emitter-follower output is provided to allow
the outputs to be wire-ORed. Separate Data In and non-inverted Data Out pins are provided. These RAMs are compatible with compensated and uncompensated 10k ECL
families.

• Fully compatible with standard and voltage compensated 10k series ECL
• Temperature range
O·C to + 75·C
• Unterminated emitter-follower output for wire-ORlng
• Power dissipation decreases with increasing temperature
• Typical address access
DM10415
20 ns
DM10415A
12 ns
• Typical chip select access
DM10415
6ns
DM10415A
4ns

Block and Connection Diagrams
Dual·ln·Llne Package

AD
AI 3

A. •

ADDRESS

DECODER

WORD
DRIVER

32.3ZARRAY

DDUT

A3 '

.4

I

AD 2
AI 3
/U

A3 5

12 A9
11 A8

A4

IU A7

a

.6

TLlLl9237-2

Top View
AS AS A7 AI AI

Order Number DM10415J
or DM10415AJ
See NS Package J16A

TUL/9237-1

Logic Symbol
Pin Names
AO-A9

Address Inputs

DIN

Data Input

DOUT

Data Output

CS

Chip Select

WE

Write Enable

TL/L/9237 -3

4-8

Truth Table
cs WE DIN DOUT
H
L
L
L

X
L
L

H

X

H
L
X

L
L
L
DOUT

= low (-1. 7V nominal)
= high (- O.9V nominal)
X = don't care
L

H

MODE
Not Selected
Write 1
Write 0
Read

c

Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Temperature Under Bias (Ambient)
- 55'C to + 125'C
Storage Temperature Range
- 65'C to + 150'C
-7.0Vto +0.5V
VEE Relative to Vcc
Any Input Relative to Vcc
VEE to +0.5V

Output Current (Output High)

-30mAto +0.1 mA

Lead Temperature (Soldering, 10 sec.)

300'C

Operating Conditions
Supply Voltage (VEE)
Ambient Temperature (TA)

Min

Max

Units

-5.46
0

-4.94
+75

V

'c

....==C

....
,j:oo

U'I
.....
C
....
==
C

....
,j:oo

~

DC Electrical Characteristics
VEE

=

-5.2V, Output Load

Symbol
VOH

VOL

VOHC

VOLC

VIH

VIL

=

50n and 30 pF to -2.0V, TA

Parameter
Output Voltage High

Output Voltage Low

Output Voltage High

Output Voltage Low

Input Voltage High

Input Voltage Low

VIN

VIN

VIN

VIN

=

=

=

=

=

O'C to +75'C (Notes 1-3)

Conditions

TA

Min
Limit

Max
Limit

Units

VIHMAXorVILMIN

O'C
+ 25'C
+ 75'C

-1000
-960
-900

-840
-810
-720

mV

O'C
+ 25'C
+ 75'C

-1870
-1850
-1830

-1665
-1650
-1625

mV

O'C
+ 25'C
+ 75'C

-1020
-980
-920

VIHMAX or VILMIN

VIHMIN or VILMAX

VIHMIN or VILMAX

O'C
+ 25'C
+ 75'C

mV
-1645
-1630
-1605

mV

Guaranteed Input Voltage High
for All Inputs

O'C
+ 25'C
+ 75'C

-1145
-1105
-1045

-840
-810
-720

mV

Guaranteed Input Voltage Low
for All Inputs

O'C
+ 25'C
+ 75'C

-1870
-1850
-1830

-1490
-1475
-1450

mV

220

/LA

170

/LA

IIH

Input Current High

VIN

=

VIHMAX

O'Cto
+ 75'C

IlL

Input Current Low,
CSAIiOthers

VIN

=

VILMIN

O'Cto
+ 75'C

0.5
-50

Power Supply Current
All Inputs and Outputs Open
O'Cto
-150
mA
(Pin 8) (Note 4)
+ 75'C
Note 1: Conditions for testing not shown in the tables are chosen to guarantee operation under "worst case" conditions.
Note 2: The specified limits represent the "worst case" value for the parameter. Since these "worst case" values normally occur at the temperature extremes,
additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges.
Note 3: Guaranteed with transverse air flow exceeding 500 linear F. P. M. and 2·mlnute warm-up period. Typical resistance values of the package are: 8JA,
(Junction to Ambient) = 90'C/W (still air); BJA (Junction to Ambient) = 50'C/W (at 500 F. P. M. air flow); BJC (Junction to Case) = 25'C/W.
Note 4: Typical values al VEE = -5.2V: TA = O'C,IEE = -105 mA; TA = 75'C, tEE = -90 mAo
lEE

II
4·9

~
....

.......

C)

:::E

....Can

.......
....
:::E
C)

C

Functional Description
The device is selected with CS low and deselected with ~
high. The operating mode is controlled by the active low
Write Enable (WE). WE low causes the data at the Data
Input (DIN) to be stored at the selected address. WE low
also causes the output to be disabled (low due to the 50n
pull-down resistor). WE high causes the data stored at the
selected address to be present at the Data Out (DOUT) pin.

Addressing the DM10415/DM10415A is achieved by means
of the 10 address lines AO-A9. Each of the 2 10 one-zero
combinations of the address lines corresponds to a bit location in the memory. The active low Chip Select (CS) together with the unterminated emitter-follower output allows for
memory array expansion to 2048 words without additional
decoding. This emitter-follower output allows for wireORing. A 50n resistor to -2V (or an equivalent network) is
required to provide a low at the output when the device is
off. This termination is required for both single device or
wire-ORed operation.

AC Electrical Characteristics
VEE

=

-5.2V ±5%, Output Load

=

50n, 30 pF to -2.0V, TA

=

O·C to 75·C, Airflow exceeding 500 LFM

TEST CIRCUIT AND INPUT WAVEFORM
Loading Conditions
GND

Input Levels
-O.9V ---~--------"\l
DOUT ~1:.....-_ _.,

-1.7V--J(-

Ir • If = 2.0 ns TVP
TLlL/9237-9

All timing measurements referenced to 50% of Input levels
VEE

CL

RT

RT

~O.OI~F
-2.0V
TL/Ll9237-8

4-10

= 30 pF including jig and stray capacitance
= son

AC Electrical Characteristics
VEE

=

-5.2V ±5%, Output Load

=

50n, 30 pF to -2.0V, TA

=

O·C to 75·C, Airflow exceeding 500 LFM (Continued)

READ CYCLE TIMING DIAGRAMS
Select Access Time

tACS
DATA OUTPUT

TUU9237-4

Address Access Time
ADDRESS INPUTS

DATA OUTPUT

TL/L/9237-5

Read Mode

TL/U9237-6

Symbol

Units

Parameter

READ CYCLE
tAA

Address Access Time (Note 5)

tACS

Chip Select Access Time

tRCS

Chip Select Recovery Time

35

ns

8

10

ns

8

10

ns

20

Note 5: The maximum address access time is guaranteed to be the worst case bit in the memory using a pseudorandom testing pattern.

II

,

4-11

AC Electrical Characteristics
VEE = -5.2V ±5%, Output Load = 50n, 30 pF to -2.0V, TA = O'C to 75'C, Airflow exceeding 500 LFM (Continued)
WRITE CYCLE TIMING DIAGRAMS
ADDRESS INPUTS~1f

\
J'-

-.JI\.

50"\ I\.

'CilifllrnT'

J

5011\'

DATA INPUT

c-->WRITE ENABLE

J

I--twscs-

~tMA-

t ..

1/

5DII\
-twsD-"

DATA DUTPUT

"
twHCS

I--twHA--j

5::}
I--tws

I-twR
Tl/L/9237 -7

Symbol

DM10415A

Parameter

Min

DM10415

Max

Min

Units

Max

WRITE CYCLE
tw

Write Pulse Width
(to Guarantee Writing)

12

25

ns

tWSD

Data Set-Up Time
Prior to Write

4

5

ns

twHD

Data Hold Time
After Write

4

5

ns

tWSA

Address Set-Up Time
Prior to Write

5

B

ns

twHA

Address Hold Time
After Write

3

4

ns

twSCS

Chip Select Set-Up
Time Prior to Write

4

5

ns

twHCS

Chip Select Hold Time
After Write

4

5

ns

tws

Write Disable Time

10

10

ns

tWR

Write Recovery Time

10

10

ns

RISE TIME AND FALL TIME

t,.

Output Rise Time

1

3,5

1

3,5

ns

tf

Output Fall Time

1

3,5

1

3,5

ns

Capacitance
Symbol

Parameter

DM10415A
Min

DM10415

Max

Min

Unlta

Max

CIN

Input Pin Capacitance

5

5

pF

COUT

Output Pin Capacitance

B

B

pF

4-12

c

NaHonal

~ Semiconductor

December 1966

....s::o
0l:Io

N

CorporaHon

N
......

C

....s::o

OM 10422/0M 10422A/OM 10422A-7
1024-Bit (256 X 4) Eel RAM

0l:Io

N

~
......

General Description

Features

The DM10422/DM10422A1DM10422A-? is a 1024-bit ECL
random access memory organized as 4 blocks of 256 bits.
Since each block has its own Select input, the memory can
be configured for a maximum of 1024 by 1 bit through WireORing of the outputs. The high-speed access time allows its
use in scratch pad, buffer, and control storage applications.
The device is voltage compensated and is compatible with
all 10k ECL logic. Separate Data In and Data Out pins allow
the set-up of data for a write cycle while performing a read.

• 4 separate Block Select inputs for configurations from
256 x 4 to 1024 x 1
• Maximum address access time-DM10422
12 ns
-DM10422A
10 ns
-DM10422A-?
? ns
• Maximum Block Select access time-DM10422
5 ns
-DM10422A 5 ns
-DM10422A-? 4 ns
• 10 kH logic compatible with on-chip voltage compensation
• Oxide isolation process
• Unterminated emitter-follower output for easy memory
expansion
• Compatible with HM10422, MBM10422 and F10422

C

s::
....
o
0l:Io

N
N

~
.....

Block Diagram
AS

A6

A7

Y - DECODER / DRIVER

A4
A3

A2
Al
AO

WEo--------t

BS4
TLIL/8693-10

Truth Table (Positive Logic)
Input

H

~

Output

BS

WE

01

H
L
L
L

X

X

L
L
H

L
H

High Voltage Level

Pin Names

X

Mode
Disable
Write "0"
Write "1"
Read

L
L
L
Data

L ~ Low Voltage Lavel

X

~

Don't Care

4-13

BS1-BS4

Block Selects

AO-A?

Address Inputs

WE

Write Enable

011-014

Data Inputs

001-004

Data Outputs

•

Functional Description

Absolute Maximum Ratings

Addressing the OM10422/0M10422A10M10422A-7 is accomplished by means of the eight address lines (AO-A7).
Each of the 256 possible combinations of address inputs
corresponds to a unique four-bit word in the memory array.
The availability of four active-low Block Select inputs (9S1B84) and the unterminated emitter-follower outputs allow
the user to reconfigure the part into a 512 x 2 or 1024 x 1
architecture by wire-ORing the outputs and using the BS
inputs as address lines.
The device is selected with BS low and deselected with BS
high. A 500 resistor to -2V (or an equivalent network) is
required to provide a logic low at the output when the device
is turned off. This termination is required for both single device and wire-ORed operation. The BS inputs are internally
pulled low so that in cases where no memory expansion is
needed, no external connections are required.
The read and write operations are controlled by the activelow Write Enable input (WE). With WE and BS held low, the
data at the Oata Inputs (011-014) is written into addressed
location. WE low also causes the output to be disabled; the
termination will then pull the output low. To read, WE is held
high, while BS is held low. The rising edge of WE causes the
data present at the selected address to be transferred to
the Oata Outputs (001-004). The data presented at the
Oata Outputs is non-inverted.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sal'.!s Office/
Distributors for availability and specifications.
Temperature Under Bias (Ambient)
-55'Cto + 125'C

DC Electrical Characteristics VEE =
Symbol
VOH

VOL

VOHC

VOLC

VIH

VIL

IIH

IlL

lEE

Parameter
Output Voltage High

Output Voltage Low

Output Voltage High

Output Voltage Low

Input Voltage High

Input Voltage Low

Input Current High

Storage Temperature Range

-65'Cto +150'C
-7.0Vto +0.5V

VEE Relative to Vcc
Any Input Relative to Vcc
Output Current (Output High)

VEE to +0.5V
-30 mA to +0.1 mA

Lead Temperature (Soldering, 10 sec.)
ESO rating is to be determined.

300'C

Operating Conditions
Supply Voltage (VEE)

Min
-5.46

Max
-4.94

0

+75

Ambient Temperature (TA)

-5.2V, RT

=

500 to -2.0V, TA

=

O'Cto + 75'C, airflow

Units
V
'C

~ 500 LFM

Conditions

TA

Min

Max

Units

VIH Max or VIL Min

O'C
25'C
75'C

-1000
-960
-900

-840
-810
-720

mV

O'C
25'C
75'C

-1870
-1850
-1830

-1665
-1650
-1625

mV

O'C
25'C
75'C

-1020
-980
-920

O'C
25'C
75'C

-

-1645
-1630
-1605

mV

Guaranteed Input Voltage High
for All Inputs

O'C
25'C
75'C

-1145
-1105
-1045

-840
-810
-720

mV

Guaranteed Input Voltage Low
for All Inputs

O'C
25'C
75'C

-1870
-1850
-1830

-1490
-1475
-1450

mV

220

/LA

VIN

VIN

VIN

VIN

VIN

=
=

=

=

=
=

VIH Max or VIL Min

VIH Min or VIL Max

VIH Min or VIL Max

O'C
to
75'C

VIHMax

Input Current Low, CS
All Others

VIN

Power Supply Current

All Inputs and Outputs ~pen

O'C
to
75'C

VILMin

4-14

O'C
to
75'C

-

0.5
-50

-200

-

-

mV

170
/LA

-

mA

AC Electrical Characteristics
Vee

=

=

VeeA

OV, VEE

=

-5.2V

± 5%, RT

= 50n 10 - 2.0V, CL

=

30 pF, T A

=

ODC 10

+ 75DC, air flow exceeding 500 LFM

c
:s::::
.....
o

"'"

N

N
......

C

Test Circuit and Input Waveform

I I I I I
Dl

-

AD

-

AI

-

A2

-

-

-

D2 GND D3

D4

~::-i.~

Hr

111
.LCL

Oz

A3

A4

Ib

A5
A6

T

:s::::
.....

Rr

l~=-

-Ir~

~CL
T":' Rr

o

"'"

N
N

l>
......
C

-tl~

TL/L/8S93-S

~CL
T":' Rr

son

CL=30pF
All liming measurements are referenced from 50% of input levels to 50% of
input/output levels.

D4

A7

..LCL

WE
BS! BS2 \Iff BS3 BS4

I

It.

T

-2.DV

I I

"J"0.01~F
TL/U8S93-5

Read Cycle
Symbol

OM10422

Parameter

OM10422A

OM 10422A·7

Max

Min

Max

Min

Max

-

10

-

7

ns

4

ns

4

ns

Address Access Time
Block Select Access Time

-

12

lABS
tRBS

Block Select Recovery Time

-

5

-

5

5
5

Read Cycle Timing Diagrams
Address Access Time

~D%
~l

ADDRESS INPUTS

DATA OUTPUT

50%
TL/U8S93-7

Block Select Access
BLOCK SELECT

1
50

%

-J.~BS

DATA OUTPUT

Units

Min
lAA

50%

4-15

tt

TL/U8S93-8

"'"
N

Ir = II = 2.0 no ±10%
RT =

:s::::
.....
o

t

Write Cycle
Symbol

DM10422

Parameter

DM10422A

DM10422A·7

Units

Min

Max

Min

Max

Min

Max

-

5

ns

1.0

-

1.0

-

ns

-

4

ns

7

ns

tw

Write Pulse Width

7

-

6

twSD

Data Set-Up Time

2.0

-

2.0

twHD

Data Hold Time

2.0

-

2.0

twSA

Address Set-Up Time

3.0

-

2.0

twHA

Address Hold Time

2.0

-

2.0

twSBS

Block Select Set-Up Time

2.0

-

2.0

tWHBS

Block Select Hold Time

2.0

-

2.0

tws

Write Disable Time

5

twR

Write Recovery Time

7

-

1.0
1.0
1.0
1.0

5
7

ns
ns
ns
ns
ns

Write Cycle Timing Diagram
ADDRESS INPUlS

... ~,,,,~

DATA INPUts

BLOCK 5aECt

~'MO~

50%f:t wso

tWHD=*

50%{twsBS

I 1

1

tWHBS

k
'w;=t
",,' -''''3 -'"

WRITE ENABLE
DATA OUT

}...
TLlL/8693-11

Rise Time and Fall Time
Symbol

DM10422

Parameter

DM10422A

DM10422A·7

Min

Max

Min

Max

Min

Max

Units

tr

Output Rise Time

1

3.5

1

3.5

1

3.5

ns

t,

Output Fall Time

1

3.5

1

3.5

1

3.5

ns

Capacitance
Symbol

DM10422A

DM10422

Parameter

DM10422A·7

Units

Min

Max

Min

Max

Min

Max

-

5

pF

8

pF

CIN

Input Capacitance

-

5

-

5

CoUT

Output Capacitance

-

8

-

8

4-16

Typical Performance Characteristics
Address Access Time
vs Ambient Temperature
NOMINAL VEE' INPUT L£VElS AND
SPECIFIED AIRFLOW

Block Select Access Time
vs Ambient Temperature

Write Pulse Width
vs Ambient Temperature

NOMINAL VEE' INPUT L£VElS AND
SPECIFIED AIRFLOW

NOMINAL VEE' INPUT L£VElS AND
SPECIFIED AIRFLOW

5,,-,-..-.-,,-,-..

10
9

5,,-,-''-'-''-'-''

_r--

o

O~~~~~~~~~

-~

~

00

~

25

-~O

100

75

00

O~~~~~~~~~

100

-25

TA• AMBIENT !IMPERATURE (OC)

TA• AMBIENT TEMPERATURE (OC)

25

50

75

100

TA• AMBIENT !IMPERATURE (OC)

TL/L/8693-12

Address Setup and Hold Times
vs Ambient Temperature

Write Recovery Time
vs Write Pulse Width
25OC. NOMINAL VEE' INPUT L£VELS
AND SPECIFIED AIRFLOW

o

10
9

NOMINAL VEE' INPUT LEVELS AND
SPECIFIED AIRFLOW Tw = 19 ns

o

T~ """1:;:

I-

TWHA
6

Data Setup and Hold Times
vs Ambient Temperature
NOMINAL VEE' INPUT LEVElS AND
SPECIFIED AIRFLOW Tw = 10 ns

1-+-

,

5
4

3

i"""

o

-5

o

25

1 2 3 4 5 6 7 8 9 10

Tw. WRITE PULSE WIDTH (ns)

5D

75

-25

100

TA• AMBIENT !IMPERATURE (OC)

~

50

75

100

TA• AMBIENT TEMPERATURE (OC)

TL/L/B693-13

Supply Current (lEE)
vs Ambient Temperature

o

1:
!z
_

-80
-100

I

NOMINAL VEE' INPUTS OPEN AND
SPECIFIED AIRFLOW

NOMINAL VEE' INPUT i./YELS AND
SPECIFIED AIRFLOW

-1040

jI

-160
-180

-200

NOMINAL VEE' INPUT LEVELS AND
SPECIFIED AIRFLOW

I

>e"

>'

-820

i-B40
i!o...J

>

-860

--

-~

~O
%

~

75

TA• AWBIENT !IMPERATURE (OC)

100

o -1810

.:.

~
-~

-

5 -1790

1/

-1000
50

~-

S-1770

~-9BO

25

-1730

~ -1750

V

-920

-94D
-960

~ -1710

V"

-B80

-1650
-1670

~ -1690

./

~ -900

E -120
~

Output Low Voltage (Vou
vs Ambient Temperature

-BOO

-20
-40
-60

Output High Voltage (VOH)
vs Ambient Temperature

25

50

75

TA• AMBIENT TEMPERATURE (OC)

100

-1830
-1650

-25

~

50

75

100

TA• AMBIENT TEMPERATURE (OC)

TUU8693-14

4·17

~

..(

'"

'"
~
..-

r---------------------------------------------------------------------------------,
Connection Diagrams
Dual-In-Line Package

:::i
C

.....

..
..'"'"
~

'"..-o
:::i

c
.....

o..:::i

c

VCCA

24

VCC

001

23

004

BSI

22

BS4

002

21

003

BS2

20

BS3

011

19

014

012

18

013

WE

17

A4

16

A3

A5
A6

10

A2

A7

11

Al

VEE

12

AD
TL/L/8693-2

TOp View

Order Number DM10422J, DM10422AJ
or DM10422A-7J
See NS Package Number J24E

Quad Cerpack
A2

A1

AD

VEE

A7

A6

A5

A3

A4

17

WE

013

16

012
011

014
BS3

14

BS2

003

13

002

liM 004 VCC VeCA 001

BSI

Order Number DM10422W, DM10422AW
or DM10422A-7W
See NS Package Number W24B

4-18

TL/U8693-4

NatiOnal

~ Semiconductor

February 1987

...s:c
Q

.c:......

Corporation

Q

........
C

DM10470/DM10470A 4096-Bit (4096 X 1) Eel RAMs

...s:

General Description

features

~

The DM10470/DM10470A is a fully decoded 4096-bit, 10K
and 10 KH compatible, ECl read/write random access
memory designed for high-speed scratch pad and buffer
storage applications. This device is organized as 4096
words by 1 bit and has separate Data In and Data Out pins.
On-chip voltage compensation is provided for improved
noise margin. The active low Chip Select and unterminated
emitter-follower outputs allow for easy expansion.

III Two speed selected offerings for maximum
cost-performance:
DM10470
25 ns/200 mA max
15 ns/200 mA max
DM10470A
II 4096 x 1 bit organization
101 10K and 10 KH logic compatible
III On-chip voltage compensation for improved noise
margin
III Oxide isolation process
III Unterminated emitter-follower outputs for easy memory
expansion
III Compatible with HM10470, MBM10470 and F10470

Q

.c:......

logic Diagram
WORD
DRIVER

DOUT

64 X 64

ARRAY

ADDRESS

DECODER

A6 A7 AS A9 AID A11

AD AI A2 AJ A4 AS

TLlL/7723-1

Connection Diagram

Truth Table

Dual-In-Line Package

Output

Inputs

Mode

cs

WE

DIN

H
L
L
L

X

X

L

Not Selected

L

L

L

Write "0"

L
H

H

L

Write"!"

X

DOUT

H

~

High Voltage Level

L

~

Low Voltage Level

X

~

Don't Care

Open Emitter

Read

Pin Names
CS

Top View

TL/L/7723-2

Order Numbers DM10470J, DM10470AJ
See NS Package Number J18A
4-19

Chip Select Input

AO-AII

Address Inputs

WE

Write Enable

DIN

Data Input

DOUT

Data Output

•

Functional Description

Absolute Maximum Ratings

Addressing the DM10470/DM10470A is achieved by means
of the twelve address lines (AO-A11). Each of the 212 possible combinations of address inputs corresponds to a
unique bit location in memory. The memory array can be
expanded by wire-ORing the unterminated emitter-follower
outputs of two or more devices and using the active-low
Chip Select (CS) inputs as address lines.
The device is selected with CS low and deselected with CS
high. A 50n resistor to -2V (or an equivalent network) is
required to provide a logic low at the output when the device
is turned off. This termination is required for both single device and wire-ORed operation. The CS input is internally
pulled low so that in cases where no memory expansion is
needed, no external connections are required.
The read and write operations are controlled by the state of
the active-low Write Enable (WE). With WE and CS held
low, the data at the Data Input (DIN) is written into the addressed location. WE low also disables the output; the termination will then pull the output low. To read, WE is held
high while CS is held low. The rising edge of WE causes
data at the addressed location to be transferred to the Data
Output (DOUT). The Data presented at DOUT is non-inverted.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
- 5S·C to + 125·C
Temperature Under Bias (Ambient)
Storage Temperature Range

- 6S·C to + 150·C
-7.0Vto +0.5V

VEE Relative to Vcc
Any Input Relative to Vcc
Output Current (Output High)

VEE to +0.5V
-30 mA to +0.1 mA

Lead Temperature (Soldering, 10 sec.)

300·C

ESD Rating Is to be determined.

Operating Conditions
Min
-5.46
0

Supply Voltage (VEE)
Ambient Temperature (TAl

Max
-4.94
+75

Units
V
·C

DC Electrical Characteristics
VEE

=

-S.2V, RT

Symbol
VOH

VOL

VOHC

VOLC

VIH

VIL

IIH

=

son to -2.0V, TA

=

O·C to + 75·C, airflow exceeding 500 LFM

Parameter
Output Voltage High

Output Voltage Low

VIN

VIN

Output Voltage High

Output Voltage Low

VIN

VIN

Input Voltage High

Input Voltage Low

Input Current High

=

=

=

=

Conditions

TA

Min

Max

Units

VIH Max or VIL Min

O·C
25·C
75·C

-1000
-960
-900

-840
-810
-720

mV

O·C
25·C
7S·C

-1870
-1850
-1830

-166S
-16S0
-162S

mV

O·C
2S·C
7S·C

-1020
-980
-920

VIH Max or VIL Min

VIH Min or VIL Max

-114S
-110S
-104S

-840
-810
-720

mV

Guaranteed Input Voltage Low
for Alii nputs

O·C
25·C
75·C

-1870
-1850
-1830

-1490
-1475
-1450

mV

220

/LA

170

/LA

VIN

=

=

O"C
to
7S·C

VIHMax

O·C
to
7S·C

VIN

lEE

Power Supply Current
Pin 9 (Note 1)

All Inputs & Outputs Open

O·C. lEE

~

mV

O·C
25·C
75·C

Input Current Low, CS
All Others

~

-1645
-1630
-1605

Guaranteed Input Voltage High
for All Inputs

IlL

Note 1: Typical values at TA
-2.0V.

O·C
2S·C
7S·C

VIH Min or VIL Max

mV

-160 mA; TA

~

VILMin

25·C. lEE

~

155 mA, TA
4-20

~

O.S
-SO

O·C
to
75·C
75·C. lEE

~

140 mAo VEE

-200
~

- 5.2V. outputload

mA
~

50n and 30 pF to

AC Electrical Characteristics
= -5.2V ±5%, RT = 500 to -2.0V, CL = 30 pF, TA = OOC to

VEE

+75'C, airflow exceeding 500 LFM

Test Circuit and Input Waveform
Loading Conditions

-----

--

~:
0.01

~F

! Ts!

es Vce WE
AD
AI
A2
A3
A4
I
DDUT
A5
AS
A7
A8
A9
AID
All
VEE

Input Levels

:::~={
I,

RT

.18

6

-2.0V

80%
[\..20%

~

Ir=lf=2.onsTYP _

~

TL/U7723-9
All timing measurements referenced from 50% of input levels to 50% of
input/output levels
Cl = 30 pF including lig and stray capacitance
RT = 50n

T'
TL/LI7723-B

Read Cycle
Symbol

Parameter

tAA

Address Access Time

tACS

Chip Select Access Time

tRCS

Chip Select Recovery Time

DM10470

Conditions

Min

Measured at 50% of Input to
50% of Output (Note 2)

Max

DM10470A
Min

Max

Units

25

15

ns

10

8

ns

10

8

ns

Note 2: The maximum address access time is guaranteed to be the worst-case bit in the memory using a pseudorandom testing pattern.

Read Cycle Timing Diagrams
Address Access Time

to' 'M'~

ADDRESS INPUTS

DATA OUTPUT

TL/L/7723-5

Chip Select Access Time
CHIP SELECT

.~

'ACS
DATA OUTPUT

L

~IRCS

-

~II

80% 20%
~~ ________

-1

'r

4-21

II

50%
TLlLl7723-4

Write Cycle
DM10470A

DM 10470

Parameter

Symbol

Min

Max

Min

Max

Units

tw

Write Pulse Width (to Guarantee Writing)

15

10

ns

twso

Data Set-Up Time Prior To Write

2

2

ns

twHO

Data Hold TIme After Write

2

2

ns

twSA

Address Set-Up Time Prior to Write

3

3

ns

twHA

Address Hold Time After Write

2

2

ns

twscs

Chip Select Set-Up Time Prior to Write

2

2

ns

tWHCS

Chip Select Hold Time After Write

2

2

tws

Write Disable TIme

8

8

ns

Write Recovery Time

8

8

ns

twR

ns

Write Cycle Timing Diagram
Write Mode
ADDRESS INPUTS

DATA INPUT

CIIii'SEi1Cf

WRITE ENABLE

"'~t~9
tWSD

p:t_~

s'"'E

tWHD==*

itWHCS)

5Dx{twscs1

...{ t~~ {-t.=l~

DATA OUT
TLlLI7723-13

\

4-22

c

....

!:

Rise Time and Fall Time

Q

DM 10470
. Max
Min

Parameter

Conditions

tr

Output Rise TIme

tf

Output Fall Time

Measured Between 20%
and 80% Points

Symbol

DM10470A
Units

Min

Max

1

3.5

1

3.5

ns

1

3.5

1

3.5

ns

C

....

!:
Q

01:00
......

~

Capacitance
Symbol

01:00
......
Q
......

DM10470

Conditions

Parameter

Min
CIN

Input Pin Capacitance

COUT

Output Pin Capacitance

DM10470A

Max

Measure With a Pulse
Technique

Min

Units

Max

5

5

pF

8

8

pF

Typical Performance Characteristics
Chip Select Access Time
vs Ambient Temperature

Address Access Time
vs Ambient Temperature
NOMINAL VEE, INPUT LEVELS AND SPECIFIED AIRFLOW

~
51
1=

ia

!i!
m
~
j

2O,--,--,---r-r-r...,.-...,-..,....,-,
18
16
14
12
10
8
6

... -

4

NOMINAL VEe. INPUT LEVELS AND SPECIFIED AIRFLOW

]:
~

~

~
~

..,.fl

2
0
-25

0

25

50

75

Write Pulse Width
vs Ambient Temperature
NOMINAL VEE. INPUT LEVELS AND SPECIFIED AIRFLOW

10r-,--,--,---r-r-r...,.-...,-,-,

10r-,--,--,---r-r-r...,.-...,-,-,

9

]:
§

8
7
6
5

'"
~

4

~

3
2
1
0

~

,j
-25

100

TA• AM81ENT TEMPERTURE (oe)

0

25

50

75

9~~-4-+-+~~~~

8
7
6
5

4
3
2
1
0
-25

100

TA• AMBIENT TENPERTURE (oe)

0

25

50

100

75

TA• AM81!HT TEMPERTURE (oe)
TL/L/7723-10

Write Recovery Time
vs Write Pulse Width
25·C. NOMINAL VEE. INPUT LEVELS AND SPECIAED
AIRFLOW

.
.5

51
1=

I
~

~

j

Data Set-Up and Hold Times
vs Ambient Temperature

Address Set-Up and Hold Times
vs Ambient Temperature
NOMINAL VEE. INPUT LEVELS AND SPECIAED AIRFLOW
Tw"" 10ns

NOMINAL VEE. INPUT LEVELS AND SPECIFIED AIRFLOW
Tw = 10ns

10

1.0

9

'I
,I

8
7
6
5
4
3
2
1
0

~

~~

-1.0 f-H-t-t-t--+-~-+-~

~$
...

. '"

-1.0

1;;0
In",

-2.D

~~

-3.0

:>1=

'9

eo

-}
5 6 7 8 9 10 11 12 13 14 15

25

Tw. WRm: PULSE WIDTH (n.)

50

75

0

100

tWHD
twso

-01.0
-25

TA• AM8I!HT TENPERTURE (oe)

I
0

25

50

75

100

TA• AMBIENT TEMPERTURE (oe)
TLlL/7723-11

Supply Current (lEE)
vs Ambient Temperature
NOMINAL VEE. INPUTS OPEN AND SPECIFIED AIRFLOW

!

Ii

o "-..--r-r-r-.,-,,
-20 (---'H-t-t-t--+-~~~
-40

-so
-100

-120 HH-4-+-+~~~~
-140

-160

NOMINAL VEEo INPUT LEVELS AND SPECIFIED AIRFLOW

-600

r-T-,.--r-r-r-.,-"

E -820 ~-t-t-t--+-+-t-HA
~

-840

/

~ : : HH-t-+-t-+.",I.o"'H-t-l

-60

HH-t-+-t-_-±i""':;;I;;.-I-"1"9
jl -160 1-::j1;;;;;l-+""'I'q:++++-1

iii

Output High Voltage (VOH)
vs Ambient Temperature

HH-t-t-t--+-~~~

-200 L....J'-l--L--1.--'--'--'--'-...L....J

-25

0

25

50

75

TA• AMBENT TEMPERTURE (oe)

100

~ -900 I-iH-4-..fo'/<+-+-~-+-~

S -920 ~-47"FI.o"'~~+-t-~--l

5

-940

HIoo"'I-t-+-t-++++-1

~ -960 I"'L+-+-+-+-t-t--H-t-l

~

I-iH-4-+-t--+-~-+-~

-9tJJ
-1000 L....J'-l--L--1.--'--'--'--'-...L....J

-25

0

25

50

75

TA• AMBIENT TEMPERTURE (oe)

100

Output Low Voltage (VoL>
vs Ambient Temperature
NOMINAL VEE. INPUT LEVELS AND SPECIFIED AIRFLOW

-1650 r-r-1---r-r-r-r...,.-...,-,-,
-1670
l!J -1690
-1710
0
> -1730
I-o-i"'"
~ -1750

!:i

~

-

_...

E

-1770

-1790

0

i;! -1810

>

-1830

-1850
-25

0

25

50

75

100

TA• AMBIENT TEMPERTURE (oe)
TL/LI7723-12

4-23

•

~Nal10nal

March 1987

Semiconductor
CorporaHon

OM 1047 4A/OM 10474A-1 O/OM 1047 4A-8
4096-Bit (1024 X 4) Eel RAM
,

General Description

Features

The DM10474A1DM10474A-10/DM10474A-8 is a fully decoded 4096-bit, 10KH compatible, ECl read/write random
access memory designed for high-speed scratch pad and
buffer storage applications. This device is organized as
1024 words by 4 bits and has separate Data In and Data
Out pins. On-chip voltage compensation is provided for improved noise margin. The active-low Chip Select and unterminated emitter-follower outputs allow for easy expansion.

• Three speed selected offerings for maximum
cost-performance:
DM10474A
15 ns/-220 mA max
DM10474A-10
10 ns/-240 mA max
DM10474A-8
8 ns/-240 mA max
• 1024 words x 4 bit organization
• 10K and 10 KH logic compatible
• On-chip voltage compensation for improved noise
margin
• Oxide isolation process
• Unterminated emitter-follower outputs for easy memory
expansion
• Available in DIP and Flat Package
• Pin compatible with HM10474, MBM10474 and F10474

Block Diagram

i

i

AI

Ar

YDECOIIfR/DRIVER

I

I
A5A6A7AI-

XDECDDERI
DRIVER

-

I
I

I
SA/WA

WE

! !

Truth Table
Inputs

1

i

I

I

I

I

I
I
I
I

I

I

I

I

I

I

MEMORY CELL ARRAY

I

I

A9-

cs

I
I

A4-

I

I

I
•

SA/WA

I

I

SAIWA

I

I
SA/WA

I

J2 oL

ol" !

ol ot

TLlL/9229-1

Pin Names
CS
AO-A9

Address Inputs

Not Selected

WE

Write Enable

WRITE "0"

DIN

Data Input

DOUT

Data Output

Output

Mode

CS

WE

DIN

H

X

X

l

l

l

l

l

l

l

H

l

WRITE "1"

l

H

X

DOUT

Open Emitter

READ

H = High Voltage Level
L = Low Voltage Level
X = Oon'l Care

4-24

Chip Select Input

Functional Description

Absolute Maximum Ratings

Addressing the DM10474A1DM10474A-l0/DM10474A-8 is
achieved by means of the ten address lines (AO-A9). Each
of the 2 10 possible combinations of address inputs corresponds to a unique word location in memory. The memory
array can be expanded by wire-ORing the unterminated
emitter-follower outputs of two or more devices and using
the active-low Chip Select (CS) inputs as address lines.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Officel
Distributors for availability and specifications.
Temperature Under Bias (Ambient)
Storage Temperature Range
VEE Relative to Vcc
Any Input Relative to VCC
Output Current (Output High)

The device is selected with CS low and deselected with CS
high. A 50n resistor to - 2V (or an equivalent network) is
required to provide a logiC low at the output when the device
is turned off. This termination is required for both single device and wire-ORed operation. The CS input is internally
pulled low so that in cases where no memory expansion is
needed, no external connections are required.

Symbol
VOH

VOL

VOHC

VOLC

VIH

VIL

IIH

IlL

lEE

Parameter
Output Voltage High

Output Voltage Low

Output Voltage High

Output Voltage Low

Input Voltage High

Input Voltage Low

Input Current High

VIN

VIN

VIN

VIN

VEE to +0.5V
-30 mA to +0.1 mA

Lead Temperature (Soldering, 10 sec.)

300'C

ESD rating is to be determined.

Operating Conditions

The read and write operations are controlled by the state of
the active-low Write Enable (WE). With WE and CS held
low, the data at the Data Inputs (Dll-DI4) is written into the
addressed location. WE low also disables the output. The
termination will then pull the output low. To read, WE is held
high, while CS is held low. The rising edge of WE causes
data at the addressed location to be transferred to the Data
Outputs (D01-D04). The Data presented at Data Outputs
is non-inverted.

DC Electrical Characteristics VEE =

-55'Cto + 125'C
-65'C to + 150'C
-7.0Vto +0.5V

Supply Volt!!ge (VEE)
Ambient Temperature (TAl

-5.2V, RT

Min
-5.46
0

Max
-4.94
+75

Units
V
'C

= 50n to -2.0V, TA = O'Cto + 75'C

Conditions

TA

Min

Max

Units

= VIH Max or VIL Min

O'C
25'C
75'C

-1000
-960
-900

-840
-810
-720

mV

O'C
25'C
75'C

-1870
-1850
-1830

-1665
-1650
-1625

mV

O'C
25'C
75'C

-1020
-980
-920

= VIH Max or VIL Min
= VIH Min or VIL Max
= VIH Min or VIL Max

O'C
25'C
75'C

mV
I

-1645
-1630
-1605

mV

Guaranteed Input Voltage High
for All Inputs

O'C
25'C
75'C

-1145
-1105
-1045

-840
-810
-720

mV

Guaranteed Input Voltage Low
for All Inputs

O'C
25'C
75'C

-1870
-1850
-1830

-1490
-1475
-1450

mV

220

/LA

170

/LA

VIN

= VIHMax

O'C
to
75'C

= VILMin

Input Current Low, CS
All Others

VIN

Power Supply Current
Pin 9 (Note 1)

All Inputs & Outputs Open

O'C
to
75'C

0.5
-50

O'C
to
75'C

(10474-8) -240
(10474-10) -240
(10474-15) -220

mA

NDte 1: Typical value, al TA = O'C, lEE = -200 rnA; TA = 25'C, lEE = -190 mA, TA = 75'C, lEE = -175 mA, VEE = -5.2V, oulpulload = son and 30pFIo

-2.0V.

4-25

III

AC Electrical Characteristics
VEE

=

-5.2V ±5%, RT

=

500. to -2.0V, CL

=

30 pF, TA

=

O·Cta +75·C

Test Circuit and Input Waveform
Loading Conditions

------

! Gi~l!
es vee

AD
AI

WE

Input Levels

AZ

OUT

:~

I

A3
A4
AS

TULl9229-3
All timing maasuremenls referenced from 50% of Input levels to 50% of
InpuVoutpUilevels

AI

~:

0.01 pF

• HT

A7
AI
AI

VEE

II

0

-2.0V

Je-

t,-t!"2.0nsTVP

T'

~

= 30 pF Including pg and stray capacllsnca

RT

= son

TL/Ll9229-2

Read Cycle
Symbol

Parameter

DM10474A

DM10474A·10

DM10474A-8

Min

Min

Min

Conditions

tM

Address Access Time

tACS

Chip Select Access Time

tRCS

Chip Select Recovery Time

Measured at 50% of Input to
50% of Output (Note 2)

Max

Max

Units

15

10

8

ns

8

6

5

ns

8

6

5

ns

Note 2: The maximum address access time is guaranteed to be the worst-case bH In the memory using a psaudorandom testing pattern.

Read Cycle Timing Diagrams
Address Access Time

f=~,_

ADDRESS INPUTS

DATA DUTPUT

TL/Ll9229-4

/

Chip Select Access Time
flIlli'mm

b.

so%
'ACS

DATA OUTPUT

~~~;----~3t~
TULl9229-5

4-26

Max

Write Cycle
Symbol

DM10474A

Parameter

DM10474A-10

DM10474A-8

Min

Max

Min

Max

Min

Max

-

tw

Write Pulse Width

15

-

10

-

6

tWSD

Data Set-Up Time Prior To Write

2

-

2

1

tWHD

Data Hold Time After Write

2

-

2

tWSA

Address Set-Up Time

3

3

tWHA

Address Hold Time

2

-

-

twscs

Chip Select Set-Up
Time Prior to Write

2

2

tWHCS

Chip Select Hold Time

2

-

-

tws

Write Disable Time

-

8

8

tWR

Write Recovery Time

-

8

2

2

-

ns

-

ns

ns

1

-

1

-

ns

-

5

ns

8

ns

1
1
1

8

Units

ns

ns
ns

Write Cycle Timing Diagram
Write Mode
ADDRESS INPUTS

DATA INPUT

CHIP SELECT

WRITE ENABLE

DATA OUT

50% f==tWSA-----J

'''lL'~
50%

r----tWHA

'*

L,~~

.1

~ --I

~tWHCS~

twscs

. -=,,,
t~
- -,,, *'"
TL/U9229-06

4-27

Rise Time and Fall Time
DM10474A1DM10474A-10/DM10474A-8
Parameter

Conditions

tr

Output Rise Time

tf

Output Fall Time

Measured Between 20%
and 80% Points

Symbol

Min

Max

1

3.5
3.5

1

Units
ns
ns

CapaCitance
DM10474A/DM10474A-10/DM10474A-8
Parameter

Symbol

Conditions

CIN

Input Pin Capacitance

COUT

Output Pin Capacitance

Min

Units

Max

Measure With a Pulse
Technique

5

pF

8

pF

Typical Performance Characteristics
Address Access Time
vs Ambient Temperature
NOMINAL VEE. INPUT LEVELS AND SPECIAED AIRFLOW

...
oS

'FSI

;

i
j

10
9
8
7

Chip Select Access Time
vs Ambient Temperature
NOMINAL VEE.INPlIT LEVELS AND SPECIFIED AIRFLOW

...

oS

..........

6
5

'FSI

..........

;
...is~

4
3
2

j

1
0

-25

0

25

50

NOMINAL VEE. INPlIT LEVELS AND SPECIFIED AIRFLOW

5
4.5
4
3.5
3

...
oS

~
~

2.5

~

2

I,;

1.5
1
0.5
0

-25

100

75

Write Pulse Width
vs Ambient Temperature

TA' AIIBENT TEMPERATURE (ae)

0

25

50

75

10
9
8
7
6
5
4r"""'3
2

1
0

-25

100

.....

..........

0

25

50

75

100

TA' AMBIENT TEMPERATURE (ae)

TA' AMBIENT TEMPERATURE (ae)

TL/U9229-7

Write Recovery Time
vs Write Pulse Width

Address Set-Up and Hold Times
vs Ambient Temperature

2S'C, NOMINAL VEE. INPUT LEVELS AND SPECIFIED
AIRFLOW

10

.-.

!

'FSI

i

II!
~

I

!

9

8
7
6
5
4
3
2
1
0
5 6 7 8 9 10 11 12 13 14 15

,,

"

NOMINAL VEE. INPUT LEVELS AND SPECIFIED AIRFLOW

NOMINAL VEE. INPlIT LEVELS AND SPECIFIED AIRFLOW
Tw = 10ns

2.li

...

..si'
...
~

i!'SI

.. F

q

I~i
..
~

~~

-25

...

i'i...
F~

!Iii!!

'\,1;

'9

10-'-

h

10-'

~~

eo
~l

'WsA
25

50

-25

100

75

1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5

TA• AIIBIENT TEMPERATURE (ae)

Tw. WRITE PULSt WIDTH (nl)

= 10ns

2

c

IviHA

0

Tw

2.5

I
I
I

2

1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5

Data Set-Up and Hold Times
vs Ambient Temperature

IWHD

lSI)

I"

~

0

25

50

...
75

100

TA' AMBIENT TEMPERATURE (ae)

TL/U9229-8

Supply Current (lEE)
vs Ambient Temperature
NOMINAL VEE.INPlITS OPEN AND SPECIAED AIRFILOW

0
-25

]: -50
-75
-100
-125
~ -150
-175
iii -200

-0.75
S -0.775
-0.8
-0.825
Ii! -0.85
-0.875
-0.9
5
-0.925
0
• -0.95
} -0.975
-1

....

- -225-0

25

50

75

TA' AMBIENT TEMPERATURE (ae)

100

5

-25

NOMINAL VEE. INPUT LEVELS AND SPECIFIED AIRFLOW

-1.65

"
./

"

~

~

Output Low Voltage (Vou
vs Ambient Temperature

NOMINAL VEE. INPUT LEVELS AND SPECIFIED AIRFLOW

~

I

-250
-25

Output High Voltage (VOH)
vs Ambient Temperature

,;'

S

-1.675

III

-1.7

~

-1.725

~

~

-1.75

5 -1.775

§

,

, .....
1,..- .....

-1.8

.) -1.825
-1.65
0

25

50

75

TA' AMBIENT TEMPERATURE (ae)

100

-25

0

25

50

75

100

TA• AMBIENT TEMPERATURE (ae)

TL/U9229-9

4-28

Connection Diagrams
Dual-In-Llne Package
Veco

24

Vee

Oil.!

23

D02

00.

22

00,

AD

21

Dk

2D

DI3

Al
OM1D474

A2

19

012

A3

18

Oil

A4

17

cs

A5

1&

WE
A9

He

10

15

A&

11

14

AS

VEe

12

13

A7

TOP VIEW

TL/L/9229-10

Order Number DM10474AJ, DM10474A-10J or DM10474-8J
See NS Package Number J24E
Flat Pack

WE

cs

011
012
013
014

2
3
4
5
6

17
16
15
14
13

As
A.
A3
A2
Al

Au

8" &'
c >8 >tJo'"
c 0'"
c
TL/L/9229-11

Order Number DM10474AW, DM10474A-10W or DM10474A-8W
See NS Package Number W24B

4-29

:i
N

-=r
o

~NatiOnal

March 198?

Semiconductor
Corporation

o,...
:::!!

C
.....
N

OM 100422/0M 100422A
.... 1024-Bit (256 X 4) Eel RAM
N

~

o
o
:::!!
C

General Description

Features

The DM100422/DM100422A is a 1024-bit ECL random access memory organized as 4 blocks of 256 bits. Since each
block has its own Select input, the memory can be configured for a maximum of 1024 by 1 bit through Wire-ORing of
the outputs. The high-speed access time allows its use in
scratch pad, buffer, and control storage applications. The
device is voltage and temperature compensated and is
compatible with all 100k ECL logic. Separate Data In and
Data Out pins allow the set-up of data for a write cycle while
performing a read.

• 4 separate Block Select inputs for configurations from
256 x 4 to 1024 x 1
12 ns
• Maximum address access time-DM100422
-DM100422A
10 ns
• Maximum Block Select access time-DM100422
5 ns
-DM100422A 5 ns
• 100k logic compatible with on-chip voltage and temperature compensation
• Oxide isolation process
• Unterminated emitter-follower output for easy memory
expansion
• Compatible with HM100422, MBM100422 and F100422

Block Diagram

y

1

I

Y

Y- DECODER / DRIVER

I

{a
{a

~

8

~

A4e>--

...'"--

'"
......

A2e>--

c

c

ffi

0

Ale>-AOe>--

~

f::l

BLOCK 1

--+z-

tF-

BLOCK 2

256x 1

DATA
CONTROL

i----

DATA
CONTROL

256x 1

Hz

BLOCK 3

f---

DATA
CONTROL

256x 1

4

--+z-

BLOCK

f---

DATA
CONTROL

256x 1

c

I

x

0....-

WE

01,

01,

J,

012

J2

0'3

J2

oL

BL

0'4

ot

B1

TL/L/6749-1

Truth Table (Positive Logic)
Input

H

WE

01

H
L
L
L

X
L
L
H

X
L
H
X

High Voltage Level

Mode

Output

BS

~

Pin Names

Disable
Write "0"
Write "1"
Read

L
L
L
Data

L ~ Low Voltage Level

X

~

Don't Care

4-30

BS1-BS4

Block Selects

AD-A?

Address Inputs

WE

Write Enable

D11-D14

Data Inputs

D01-D04

Data Outputs

Functional Description

Absolute Maximum Ratings

Addressing the DM100422/DM100422A is accomplished
by means of the eight address lines (AO-A?). Each of the
256 possible combinations of address inputs corresponds
to a unique four·bit word in the memory array. The availability of four active-low Block Select inputs (BS1-B54) and the
unterminated emitter-follower outputs allow the user to reconfigure the part into a 512 x 2 or 1024 x 1 architecture by
wire-ORing the outputs and using the BS inputs as address
lines.
The device is selected with BS low and deselected with BS
high. A 50n resistor to - 2V (or an equivalent network) is
required to provide a logic low at the output when the device
is turned off. This termination is required for both single device and wire-ORed operation. The BS inputs are internally
pulled low so that in cases where no memory expansion is
needed, no external connections are required.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications.
Temperature Under Bias (Ambient)
- 55·C to + 125·C
Storage Temperature Range

- 65·C to + 150"C
-7.0Vto +0.5V

VEE Relative to Vee
Any Input Relative to Vee
Output Current (Output High)

VEE to +0.5V
-30 mAto +0.1 rnA
300·C
Lead Temperature (Soldering, 10 sec.)

ESD rating is to be determined.

Operating Conditions
Supply Voltage (VEE)

The read and write operations are controlled by the activelow Write Enable input (WE). With WE and BS held low, the
data at the Data Inputs (011-014) is written into addressed
location. WE low also causes the output to be disabled; the
termination will then pull the output low. To read, WE is held
high, while BS is held low. The rising edge of WE causes the
data present at the selected address to be transferred to
the Data Outputs (001-004). The data presented at the
Data Outputs is non-inverted.

Ambient Temperature (TAl

Min
-4.73

Max
-4.27

0

+85

Units
V
·C

DC Electrical Characteristics
VEE

=

-4.5V, RT

Symbol

=

50n to -2.0V, TA

=

O·C to + 85·C, airflow exceeding 500 LFM

Parameter

=
=
=
=

Conditions

Min

Max

Units

VIH Max or VIL Min

-1025

-880

mV

VIH Max or VIL Min

-1810

-1620

mV

VIH Min or VIL Max

-1035

-

mV

VIH Min or VIL Max

-

-1610

mV

-1165

-880

mV

-1810

-1475

mV

!LA

VOH

Output Voltage High

VIN

VOL

Output Voltage Low

VIN

VOHC

Output Voltage High

VIN

VOLC

Output Voltage Low

VIN

VIH

Input Voltage High

Guaranteed Input Voltage High
for All Inputs

VIL

Input Voltage Low

Guaranteed Input Voltage Low
for All Inputs

=
=

IIH

Input Current High

VIN

IlL

Input Current Low, BS
All Others

VIN

lEE

Power Supply Current

All Inputs and Outputs Open

VIHMax
VILMin

4-31

-

220

0.5
-50

170

-200

-

p.A
rnA

~
N

"'Ii'

o

o
,...

AC Electrical Characteristics
Vcc

= VCCA = OV, VEE =

-4.5V ±5%, RT

= 50n to -2.0V, CL = 30 pF, TA = O·C to + 85·C, air flow exceeding 500 LFM

:::E

C
....
N

Test Circuit and Input Waveform

I I III

N

00:1'

o

-

o
,...

-

:::E
C

-

-

01

02 6ND 03

04

RT

0.

AD

-'-CL

Al

T

A2

Ry

A3

-,n-J' fu-

..LCL

-:;fRy

M

20%

Ib

A5

-Ir-

ICL""

A6

-:;fRy
BS1 BS2 VEE BS3 BS4

I

~n I I

T

~

~

t,

2.0ns ±10%

~

RT ~ 50n

..LCL

WE

-I,

TUU6749-3

Ir

14

A7

i..

-0.9V

02

CL ~ 30pF

-2.0V

All timing measurements are referenced from 50% of input levels to 50% of
input/output levels.

O01tlf
•
TUU6749-2

Read Cycle
Symbol

DM100422

Parameter
Min

DM100422A

Units

Max

Min

Max

-

10

ns

5

ns

5

ns

tAA

Address Access Time

-

12

tABS

Block Select Access Time

5

tRBS

Block Select Recovery Time

-

5

Read Cycle Timing Diagrams
Address Access Time
ADDRESS INPUTS

DATA OUTPUT

Block Select Access

~'
~lm'

BLOCK SELECT

DATA OUTPUT
TUU6749-4

1
50

%

J.'"
50%

tt

TL/L/6749-5

4·32

Write Cycle
Symbol

OM100422

Parameter

OM100422A

Min

Max

-

tw

Write Pulse Width

7

twso

Data Set-Up Time

2.0

twHO

Data Hold Time

2.0

tWSA

Address Set-Up Time

3.0

tWHA

Address Hold Time

2.0

tWSBS

Block Select Set-Up Time

2.0

twHBS

Block Select Hold Time

2.0

tws

Write Disable Time

5

twA

Write Recovery Time

7

Min

Units

Max

6

-

ns

2.0

-

ns

-

ns

5

ns

7

ns

2.0
2.0
2.0
2.0
2.0

-

ns
ns

ns
ns

Write Cycle Timing Diagram

"'t;,_~
1

ADDRESS INPUTS

~'mJ
~WHD:5j(

5o,;Etws!....-

DATA INPUTS

50,;(

BLOCK SELECT

t WSBS

itWHBS}

",,'r";::c
~'~3 -,~ }'"

WRITE ENABLE

DATA OUT
TLlL/6749-6

Rise Time and Fall Time
Symbol

OM100422

Parameter

OM 100422A

Units

Min

Max

Min

Max

tr

Output Rise TIme

1

3.5

1

3.5

ns

tf

Output Fall Time

1

3.5

1

3.5

ns

Capacitance
Symbol

OM100422

Parameter

CIN

Input Capacitance

COUT

Output Capacitance

OM 100422A

Units

Min

Max

Min

Max

-

5

-

5

pF

8

8

pF

•

,
4-33

c(
C'I
C'I
~

Connection Diagram

0
0

..-

Dual·ln·Llne Package

:E
C
.....
C'I

VeeA

24

Vee

0
0

001

23

004

:E

BSI

22

BS4

002

21

003

BS2

20

BS3

011

19

014

012

18

013

WE

17

A4

A5

16

A3

C'I
~

..-

C

A6

10

15

A2

A7

11

14

AI

VEE

12

13

AD
TLlLl6749-7

Top View
Order Number DM100422J or DM100422AJ
See NS Package Number J24E
Quad Cerpack
A2

A3

AI

AD

VEE

A7

A6

1.

A5

A4

17

WE

013

16

012

014

15

011

BS3

14

8S2

003

13

002

BS4

004

Vee

VeeA 001

BSt

Order Number DM10422W. DM10422AW
or DM100422AJ
See NS Package Number W24B

4-34

TL/L/6749-B

,------------------------------------------------------------------.0
Ii:
....
NatiOnal
December 1986
o

~ Semiconductor

o

01:00

Corporation

~
.....

DM100470/DM100470A 4096-Bit (4096

X

1) Eel RAMs

~

General Description

Features

The DM100470/DM100470A is a fully decoded 4096-bit,
100K compatible, ECL readlwrite random access memory
designed for high-speed scratch pad and buffer storage applications. This device is organized as 4096 words by 1 bit
and has separate Data In and Data Out pins. On-Chip voltage and temperature compensation is provided for improved noise margin. The active-low Chip Select CS and
unterminated emitter-follower outputs allow for easy expansion.

• Two speed-selected offerings for maximum
cost-performance:
DM100470
25 ns/200 mA max
DM100470A
-15 ns/200 mA max
• 4096 x 1 bit organization
• 100K logic compatible
• On-chip voltage and temperature compensation for improved noise margin

.......

• Oxide-isolation process
• Unterminated emitter-follower outputs for easy memory
expansion
• Pin-compatible with HM100470 and F100470

Logic Diagram
DOUT
WORD

64X64
ARRAV

DRIVER

ADDRESS
DECODER

A6 A7 A8 A9 A'O A11

AD At A2 A3 A4 A5

TL/L/B639-1

Connection Diagram

Truth Table

Dual·ln·Llne Package
18
DOUT

11

AD

DIN

16 ~

AI

ISm

AZ

14

A3

Output

Inputs

Vee

All

H

CS

WE

DIN

Open EmiHer

H
L
L
L

X

X

L
L
H

L
H

L
L
L

~

X

High Voltage Level

Mode
Not Selected
Write "0"
Write "1"
Read

DOUT
L

~

Low Voltage Level

X

~

Don't Care

A4

Pin Names

AS

CS

A6
VEE
TLlL/B639-2

Top View
Order Number DM100470J or DM100470AJ
See NS Package Number J18A

4-35

o

....

Ii:
o
o

Chip Select Input

AO-A11

Address Inputs

WE

Write Enable

DIN

Data Input

DOUT

Data Output

~

~...
....
::E
g
Q

I
....

::E
Q

Functional Description

Absolute Maximum Ratings

Addressing the DM100470/DM100470A is achieved by
means of the twelve address lines (AO-All). Each of the
212 possible combinations of address inputs corresponds to
a unique bit location in memory. The memory array can be
expanded by wire-ORing the unterminated emitter-follower
outputs of two or more devices and using the active-low
Chip Select (CS) inputs as address lines.
The device is selected with CS low and deselected with CS
high. A 50n resistor to -2V (or an equivalent network) is
required to provide a logic low at the output when the device
is turned off. This termination is required for both single device and wire-ORed operation. The CS input is internally
pulled low so that in cases where no memory expansion is
needed, no external connections is required.
The read and write operations are controlled by the state of
the active-low Write Enable (WE). With WE and CS held
low, the data at the Data Input (DIN) is written into the addressed location. WE low also disables the output. The termination will then pull the output low. To read, WE is held
high while CS is held low. The rising edge of WE causes
data at the addressed location to be transferred to the Data
Output (DOUT)' The data presented at DOUT is non-inverted.

If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+0.5Vto -7.0V
Supply Voltage, VEE to Vee
Input Voltage, VIN
+0.5V to VEE
-30mA
Output Current
-55·Cto + 150"C
Storage Temperature, Tstg
Storage Temperature Under Bias,
-55·C to + 125·C
Tstg(Bias)
Lead Temperature (Soldering, 10 sec.)
300"C
ESC Rating to be determined.

Operating Conditions
Supply Voltage (VEE>
Ambient Temperature (TAl

Min
-4.73
0

Max
-4.27
+85

Units
V
·C

DC Electrical Characteristics
Vee

=

OV, VEE

=

-4.5V, RT

=

50n to -2.0V, TA

= O·C to

+85·C, air flow exceeding 500 LFM

Parameter

Symbol

Min

Max

Units

VOH

Output High Voltage (VIN

-880

mV

Output Low Voltage (VIN

-1810

-1620

mV

-1035

-

mV

VOLC

= VIHmax or VILmin)
= VIHmax or VILminl
Output High Voltage (VIN = VIHmin or VILmaxl
Output Low Voltage (VIN = VIHmin or VILmaxl

-1025

VOL

-

-1610

mV

VIH

Input High Voltage (Guaranteed Input Voltage High for All Inputs)

-1165

-880

mV

VIL

Input High Voltage (Guaranteed Input Voltage Low for All Inputs)

-1810

-1475

mV

IIH

Input High Current (VIN

220

p.A
p.A

VOHC

-50

-

IlL

= VIHmaxl
Input Low Current (VIN = VILminl
CS Input Low Current (VIN = VILmin)

0.5

170

p.A

lEE

Power Supply Current (All Inputs and Outputs Open)

-200

-

mA

IlL

4-36

AC Electrical Characteristics
Test Circuit and Input Waveforms
Loading Conditions

--------

.n:

0.01 "F

Input Levels

-o.ov

!
!es Gi~6
Vee WE

AO
AI
AZ
A3
A4
A5
A6
A7
A8
AD
AIO
A11

-1.7V~
I,
_

80%

\-ZOll
1,=II=Z.O.sTYP _

~
Tl/LlB639-9

DDUT

All timing measurements relerenced from 50% of input levels to 50% of
inpuVouiputlevels
CL = 3D pF Including lig and stray capacitance
RT = son

I

RT
VEE
18

c5

-Z.OV

T'
TLlL/B639-B

Read Cycle VEE =
Symbol

-4.5V ±5%, RT = 50n to -2.0V, CL = 30 pF, TA = O·Cto

Parameter

+ 85·C, airflow exceeding 500 LFM

DM100470

Conditions

Min

Max

DM100470A
Min

tAcS

Chip Select Access
Chip Select Recovery Time

-

10

tRCS

10

-

tAA

Address Access Time

-

25

-

Max
8

Units
ns

8

ns

15

ns

Read Cycle Timing Diagrams
Address Access Time

~~1m

ADDRESS INPUTS

DATA OUTPUT

TlIL/B639-5

Chip Select Access Time
C"iiiP"Smn

DATA OUTPUT

{

tOll

.~

'3~

Zoll

---j

~::_______

_I,

5011

~If
TlILlB639-4

4-37

•

~
~

g

....

::::E

Write Cycle

VEE= -4.5V ±5%, RT=50n to -2.0V, CL =30 pF, TA=O'C to +85'C, airflow exceeding 500 LFM
DM100470

Symbol

Units

c

~

Q
Q

....

::::E

c

DM100470A

Parameter
Write Pulse Width

tw

Min

Max

Min

15

-

10
2

Max

-

ns

twSD

Data Set-Up Time Prior to Write

2

twHD

Data Hold Time After Write

2

twSA

Address Set-Up TIme Prior to Write

3

twHA

Address Hold TIme After Write

2

twscs

Chip Select Set-Up Time Prior to Write

2

-

tWHCS

Chip Select Hold Time After Write

2

-

2

-

ns

tws

Write Disable Time

-

8

8

ns

tWR

Write Recovery Time

-

8

-

8

ns

ns

-

2

ns

-

3
2
2

ns
ns
ns

Write Cycle Timing Diagram
Write Mode

DATA INPUT

"'~=''''9

CHIP SELECT

5D%{t~1

ADDRESS INPUTS

WRIlE

p:'''~

50%Etws~

~WHDj(

itWHCS)

-''',

.,'C-";=t=
-,,,

ENABLE

DATA OUT

}

..
TL/L/8639-7

Rise Time and Fall Time
DM 100470
Symbol

Parameter

tr

Output Rise TIme

~

Output Fall Time

DM100470A
Units

Conditions
Measured Between 20%
and 80% Points

Min

Max

Min

Max

1

3.5

1

3.5

ns

1

3.5

1

3.5

ns

Capacitance
DM 100470
Symbol

Parameter

CIN

Input Pin Capacitance

COUT

Output Pin Capacitance

DM100470A

Conditions
Measure with a Pulse
Technique

4-38

Units
Min

Max

Min

Max

-

5

5

pF

-

8

-

8

pF

Typical Performance Characteristics
Address Access Time
vs Ambient Temperature
NOMINAL VEE. INPUT LEVELS AND SPECIAED AIRFLOW

Write Pulse Width
vs Ambient Temperature

Chip Select Access Time
vs Ambient Temperature
NOMINAL VEE. INPUT LEVELS AND SPECIFIED AIRFLOW

NOMINAL VEE> INPUT LEVELS AND SPECIFIED AIRFlOW

10,,-,-.,-,-,,-,-.,

20

10,-",,-.-r-r-r-,,-,
9r-~~-+-+-+-r-r~

18
16
14

1--1-'"

12

10 i""'

o

-25

OL.......J---'--!'--'---'---'--'---'---'--'
0

25

50

75

100

-25

25

50

75

100

TA• AIIBIENT TEMPERlIJRE (OC)

TA' AMBIENT TEIIPERlIJRE (OC)

TA' AMBIENT TEIIPERlIJRE (OC)

TL/L/8639-10

Address Set-Up and Hold Times
vs Ambient Temperature

Write Recovery Time
vs Write Pulse Width

we. NOMINAL VEE. INPUT LEVELS AND SPECIFIED

NOMINAL VEE. INPUT LEVELS AND SPECIAED AIRFLOW

AIRFLOW

Tw"" 10n8

10"TrI'-~rT-''-ro

Data Set-Up and Hold Times
vs Ambient Temperature

NOMINAL VEE. INPUT LEVELS AND SPECIFIED AIRFLOW
Tw"" 10ns

1.0

1.0

9r+~1~~~~1-~

-1.0

-1.0
tWHA

-2.0

"""

-4.0

-4.0

5 6 7 8 9 10 11 11 13 14 15

twso

-3.0

IWSA
O~-L~~~-L~~

t WHO

-2.0

-25

0

25

50

75

-25

100

25

50

75

100

TA• AIIBIENT TE~PERlIJRE ("C)

Tw. WRITE PUL5E WIDTH (ns)

TL/L/8639-11

Supply Current (lEE)
vs Ambient Temperature
NOMINAL VEE. INPUTS OPEN AND SPECIAED AIRFLOW

o

!-B70

!-40
~

jI

;:!;

-910

-1710
~ -17aD

~-950

~

~-990

S

-970

5
0

o -1010

.J -1030

.j

25

50

75

TA• AMBIENT TEIIPERAlURE (OC)

100

-1750
-1770
-1790

-1810
-1830

-1850

-1050

0

-1650
-1670
-1690

!:l

~

~ -930

-100

-t2O
-140
i""'
-160
-160
-200
-25

NOMINAL VEE. INPUT LEVELS AND SPECIFIED AIRFLOW

!III

1lI-890

l5 -60
!i -ao
u

NOMINAL VEEo INPUT LEVELS AND SPECIAED AIRFLOW

Output Low Voltage (Vod
vs Ambient Temperature

-850

-20

E

Output High Voltage (VOH)
vs Ambient Temperature

-25

0

25

50

75

TA' AMBIENT TEIIPERAlURE (OC)

100

-25

25

50

75

100

TA' AMBIENT TEIIPERAlIJRE (OC)
TL/L/8639-12

4-39

~

0a-

,----------------------------------------------------------------,

t; ~ NaHonal
Semiconductor
~
CorporaHon

September 1985

8

~ DM100474/DM100474A (1024 X 4) 4096-Bit,
8
.,... 100k Eel RAM
:E
C

General Description

Features

The DM100474 is a 4096-bit read/write random access
memory, organized in the popular 1024 words by 4-bit configuration. It is designed for high-speed scratchpad, control
and buffer storage applications. The device includes full onchip address decoding, separate Data input and non-inverting Data output lines, as well as an active-low chip select
line. The input and output levels are voltage compensated
100k ECL levels. The DM100474A has a maximum access
time of 15 ns, and the DM100474 has a maximum access
time of 25 ns.

• 1024 words x 4-bit organization
• On chip voltage compensation for improved noise
margin
• Fully compatible with industry standard 100k series ECL
families
• Address access time: 25 ns max for standard part,
15 ns max for "A" part.
• Chip select access time: 10 ns max for standard part,
8 ns max for "A" part.
• Low power dissipation: -220 mA max for "A" part,
-200 mA max for standard.
I!! Pin compatible with F100474 and MBM100474

Connection and Block Diagrams
Vcco

24

\It<:

Dib

23

DO!

00.

22

00,

AD

21

Di4

A1

20

Dl3

19

D~

A3

18

Dll

A4

17

cs

AS

16

~

10

15

A9

"

14

AI

13

A7

DM1D0474

A2

Ne
A6

12

Vu

I
I
XDECODERI
DRIVER

MEMORY

c'eu MlRAY
I

AI

I

AI

I

TL/L/6748-1

Top View
Order Number DM100474D
or DM100474AD
See NS Package D24K

IiI1

Inputs

Output

III,

DO,
TL/L/6748-2

Truth Table
CS

00,

Mode

WE D,N Open Emitter

H

X

X

L

Not Selected

L

L

L

L

WRITE "0"

L

L

H

L

WRITE "1"

L

H

X

DOUT

READ

H = high voltage level
L = low voltage level
x = don't care

4-40

Absolute Maximum Ratings
-7.0Vto +0.5V

Supply Voltage, VEE to Vcc
Input Voltage, VIN

Storage Temperature, TSTG

Output Current

-65'Cto + 150'C

Storage Temperature Under Bias,

VEE to +0.5V
-30 rnA to +0.1 rnA

-55'Cto + 125'C

TSTG (Bias)

DC Electrical Characteristics
(Vcc = OV, VEE = - 4.5V, output load = 50n to - 2.0V, T A = O'C to + 85'C and airflow ~ 500 LFM unless otherwise noted.)
Symbol

Parameter
Output High Voltage

VOH

(VIN = VIH max or VIL min)
Output Low Voltage

VOL

(VIN = VIH max or VIL min)
Output High Threshold Voltage

VOHC

Min

Typ

Max

Units

-1025

-955

-880

mV

-1810

-1715

-1620

mV

-1035

(VIN = VIH min or VIL max>
VOLC

Output Low Threshold Voltage
(VIN = VIH min or VIL max>

VIH

Input High Voltage
(Guaranteed Input Voltage High for All Inputs)

VIL

Input Low Voltage
(Guaranteed Input Voltage Low for All Inputs)

IIH

Input High Current (VIN = VIH max)

IlL

Input Low Current (VIN = VIL min)

IlL

CS Input Low Current (VIN = VIL min)

lEE

Power Supply Current
(All Inputs and Outputs Open)

mV
-1610

mV

-1165

-880

mV

-1810

-1475

mV

220

/LA

-50

/LA
170

0.5

/LA

-200
-220'

rnA

'For the DM100474A.

AC Test Circuit and Switching Time Waveform
(Full guaranteed operating ranges, output load = 50n to -2.0V and 30 pF to GND and airflow> 500 LFM unless otherwise
noted.)
Input Waveforms
-O.9V--- -../{....,.------~l:80;"
Vee

Vcco

I

-1.7V

--II-I,

~
j-Q

TLlL/6746-4

t,
-2.0V

TL/L/6748-3

Output Load: RL

=

50n

CL=30pF
(including iig and stray capacitance)

4·41

= tf = 2.0 nstype

AC Electrical Characteristics
= -4.5V ±5'Yo. output load = 50n to -2.0V. 30 pFto GND. TA =

VEE

o·Cto

+ 85·C • airflow;;' 500 LFM and 2 min warm up.

Read Cycle
Symbol

DM100474

Parameter
Typ

DM100474A

Max

Typ

Units

Max

tAA

Address Access Time

25

15

ns

tACS

Chip Select Access Time

10

8

ns

tRCS

Chip Select Recovery Time

10

8

ns

Read Cycle Timing Diagrams

5~I~s

t

t=
1.-

50%

DauT

~..

ADORESS

• -IRCS-

-llr-

w1m

DauT

jm%
50%

TLlLl6748-6

TLlL/6748-5

Write Cycle
Symbol

DM 100474

Parameter
Min

Typ

DM100474A
Min

Max

20

Typ

Units
Max

tw

Write Pulse Width

tws

Write Disable Time

10

15

8

ns

twR

Write Recovery Time

10

8

ns

twSA

Address Set Up Time

2

ns

2

ns
ns

twscs

Chip Select Set Up Time

2

2

twSD

Data Set Up Time

2

2

ns

twHA

Address Hold Time

2

2

ns

twHCS

Chip Select Hold Time

2

2

ns

twHO

Data Hold Time

2

2

ns

Write Cycle Timing Diagrams
5

~

}

I\c

V
}

ADORESS

~

11\
(

I
'!:.wso-

DIN

----

X
..1

,'f..

~

WE

DoUT

1-1_

1\
}-IwHAI - - - w -1---l1li-~twHCS-

---

Iwscs

.

.t

1
I--twR-I

Note: All timing measurements referenced to 50% inpul levels.

4-42

50%

TL/L/6748-7

Rise Time and Fall Time
Symbol

DM100474/DM100474A

Parameter
Min

Typ

tr

Output Rise Time

-

2.5

tf

Output Fall Time

-

2.5

4-43

Units
Max

-

ns
ns

Section 5
Physical Dimensions

III

Section 5 Contents
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Bookshelf
Sales and Distribution Offices

\

5-2

5-3

NatiOnal

~ Semiconductor

All dimensions are in inches (millimeters)

Corporation

1.195

~------(3D'35)------""~~1
24

23

22

21

20

MAX 17

19

18

16

15

14

13

~·. .1~ ~ 1~ ~ ~ ~ I~ ~ ]3~·~
1

0.009-0.012

(0.22~y:.305)

2

3

4

5

6

7

8

9

10

11

12

I
£l j'---.f...
1

0.390-0.410

(9.906-10.41)

D24KIREVAI

NS Package D24K

0.785~

MAX

(19.939)
13

0.025
(0.635)
RAO

12

11

10

9

~
0.220-0.310
(5.588-7.874)

'-r.rr';'T"T;"1!"'T7T'"T":'T"T':O"I~",..(-.-l

+.5

0.005-0.020
(0.127 - 0.508)
RAO TVP
0.200

I"

.,. pJJ\ '.'_':Jffi~~;;;~~~~~!;;;t;;;~I~~~M~AX_-4_""'"

(4.572)
MAX

-I

.~-.~

-

0.310-0.410
(7.874 -10.41)

'.~--j

(0.203- 0.305)

I--

(20~;J
80TH

,...,

Y

ENOS
J16A(REVKI

NS Package J16A

5-3

•

o

C

r-----------------------------------------------------------------------------,

o

"iii

c

CD

E

(~:~:) RAD MAX

is

B

f

"l
.c

0.310
(7.874) MAX

j:L

'"m-r:;;-;;"T""T"lT"!;""""""""""';;Tr.T"U
~MIN-­
(0.127)

0.200
l5.Osiii
MAX

- I 0.290-0.320 l I (7.366-8.128) I

0.020-0.060
(0.508-1.524)
0.125-0.200
(3.175-5.080)

r:~GLASSSEALANT"""""
0.180
4572
(MAX)

til

j

0.008-0.012
95°±5°
0.310 - 0.410
(7.874 -10.41)

L

I

(0.203-0.305)
860940j
TYP

L

0.100±0.010
(2.540± 0.254)

:JP

Lj

0.018±0.003 TYP
(0.457±0.076)

0.098

i2.4i9)
MAX

0.150
(3.810)
MIN

BOTH ENDS
J18AIREYLj

NS Package J18A

J.-_______

l.215 _ _ _ _ _ _ _~
(30.86)

MAX

0.025
(0.635)
RAD

0.030-0.055
(0.762 -1.397)
RAD TYP

0.180
(4.572)
0.225
(5.715)

MAX

--I

0.100±0.D1D
(2.540 ± 0.254)
TYP

,j.-

-=w
I'

O.OIB±O.003 -+
(0.457±0.076)
TYP

j.-

0.125
(3.175)
MIN

T
0.008 -0.012
(0.203-0.305)
TYP

J24EIAEVGI

NS Package J24E

5-4

1.290

1 - - - - - - - 132.71) M A X - - - - - - - - J

0.025 RAD
10.635)

0.030-0.055
10.762-1.397)

1

RADTVP

0.290-0.320
17.366-8.128)

--

A-.. - . "
I

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_

National

Semiconductor
Corporation

Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
Please contact your local National sales office for possible complimentary copies. A listing of sales offices follows this
bookshelf.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 23-200
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
For a recorded update of this listing plus ordering information for these books from National's Uterature Distribution operation,
please call (408)749-7378.

DATA CONVERSION/ACQUISITION DATABOOK-1984
Selection Guides. Active Filters. Amplifiers. Analog Switches. Analog-to-Digital Converters
Analog-to-Digital Display (DVM) • Digital-to-Analog Converters • Sample and Hold • Sensors/Transducers
Successive Approximation Registers/Comparators. Voltage References

HYBRID PRODUCTS DATABOOK-1982
Operational Amplifiers. Buffers. Instrumentation Amplifiers. Sample & Hold Amplifiers. Comparators
Non-Unear Functions 0 Precision Voltage Regulators and References. Analog Switches
MOS Clock Drivers • Digital Drivers. A-D Converters. D-A Converters. Fiber-Optic Products
Active Filters & Telecommunication Products. Precision Networks. 883/RETS

INTERFACE DATABOOK-1986
Transmission Une Drivers/Receivers. Bus Transceivers. Peripheral/Power Drivers. Display Controllers/Drivers
Memory Support. Microprocessor Support • level Translators/Buffers • Frequency Synthesis

INTERFACE/BIPOLAR LSI/BIPOLAR MEMORY/PROGRAMMABLE LOGIC
DATABOOK-1983
Transmission Une Drivers/Receivers. Bus Transceivers. Peripheral/Power Drivers
level Translators/Buffers. Display Controllers/Drivers. Memory Support. DynamiC Memory Support
Microprocessor Support • Data Communications Support. Disk Support. Frequency Synthesis
Interface Appendices. Bipolar PROMs. Bipolar and ECl RAMs. 2900 Family/Bipolar Microprocessor
Programmable logic

INTUITIVE IC CMOS EVOLUTION-1984
Thomas M. Frederiksen's new book targets some of the most significant transitions in semiconductor technology since the
change from germanium to silicon. Intuitive IC CMOS Evolution highlights the transition in the reduction in defect densities and
the development of new circuit topologies. The author's latest book is a vital aid to engineers, and industry observers who need
to stay abreast of the semiconductor industry.

INTUITIVE Ie OPAMPS-1984
Thomas M. Frederiksen's new book, Intuitive IC Op Amps, explores the many uses and applications of different IC op amps.
Frederiksen's detailed book differs from others in the way he focuses on the intuitive groundwork in the basic functioning
concepts of the op amp. Mr. Frederiksen's latest book is a vital aid to engineers, designers, and industry observers who need to
stay abreast of the computer industry.

LINEAR APPLICATIONS HANDBOOK-1986
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.

LINEAR SUPPLEMENT DATABOOK-1984
Amplifiers. Comparators. Voltage Regulators. Voltage References. Converters. Analog Switches
Sample and Hold • Sensors • Filters • Building Blocks. Motor Controllers. Consumer Circuits
Telecommunications Circuits • Speech • Special Analog Functions

LOGIC DATABOOK VOLUME 1-1984
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes • MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. LSIIVLSI

LOGIC DATABOOK VOLUME 11-1984
Introduction to Bipolar Logic. Advanced Low Power Schottky. Advanced Schottky. Low Power Schottky
Schottky • TTL • Low Power
'

LS/S/TTL DATABOOK-1987
Introduction to Bipolar Logic • Low Power Schottky. Schottky. TTL. Low Power

MASS STORAGE HANDBOOK-1986
Disk Interface Design Guide and User Manual • Winchester Disk Support • Winchester Disk Data Controller
Floppy Disk Support. Drive Interface Support Circuits

MEMORY SUPPORT HANDBOOK-1986
Dynamic Memory Control • Error Checking and Correction • Microprocessor Interface and Applications
Memory Drivers and Support

NON-VOLATILE MEMORY DATABOOK-1987
CMOS EPROMs • EEPROMs • Bipolar PROMs

THE NSC800 MICROPROCESSOR FAMILY DATABOOK-1985
CPU • Peripherals • Evaluation Board • Logic Devices • MA2000 Macrocomponent Family

SERIES 32000 DATABOOK-1986
Introduction • CPU-Central Processing Unit. Slave Processors. Peripherals • Data Communications and LAN's
Disk Control and Interface. DRAM Interface. Development Tools. Software Support. Application Notes

RELIABILITY HANDBOOK-1986
Reliability and the Die • Internal Construction. Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process. Reliability and the Hybrid Device. VLSIIVHSIC Devices
Radiation Environment. Electrostatic Discharge. Discrete Device. Standardization
Quality Assurance and Reliability Engineering • Reliability and Documentation • Commercial Grade Device
European Reliability Programs. Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total MilitarylAerospace Standardization Program
883B/RETSTM Products • MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products
Radiation Hardened Technology. Wafer Fabrication. Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms. Key Government Agencies. ANI Numbers and Acronyms
Bibliography· MIL-M-38510 and DESC Drawing Cross Listing

THE SWITCHED~CAPACITOR FILTER HANDBOOK-1985
Introduction to Filters. National's Switched-Capacitor Filters. Designing with Switched-Capacitor Filters
Application Circuits • Filter Design Program. Nomographs and Tables

TRANSISTOR DATABOOK-1982
NPN Transistors • PNP Transistors. Junction Field Effect Transistors. Selection Guides. Pro Electron Series
Consumer Series • NAINBINR Series. Process Characteristics Double-Diffused Epitaxial Transistors
Process Characteristics Power Transistors. Process Characteristics JFETs • JFET Applications Notes

VOLTAGE REGULATOR HANDBOOK-1982
Product Selection Procedures • Heat Flow & Thermal Resistance. Selection of Commercial Heat Sink
Custom Heat Sink Design ~ Applications Circuits and Descriptive Information • Power Supply Design
Data Sheets

48-SERIES MICROPROCESSOR HANDBOOK-1980
The 48-Series Microcomputers. The 48-Series Single-Chip System. The 48-Series Instruction Set
Expanding the 48-Series Microcomputers. Applications for the 48-Series • Development Support
Analog 110 Components. Communications Components. Digital 1/0 Components. Memory Components
Peripheral Control Components

------------

~

NatiOnal

Semiconductor
Corporation

-



---

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